diff options
517 files changed, 41799 insertions, 11038 deletions
diff --git a/Documentation/DocBook/videobook.tmpl b/Documentation/DocBook/videobook.tmpl index 89817795e668..0bc25949b668 100644 --- a/Documentation/DocBook/videobook.tmpl +++ b/Documentation/DocBook/videobook.tmpl | |||
| @@ -1648,7 +1648,7 @@ static struct video_buffer capture_fb; | |||
| 1648 | 1648 | ||
| 1649 | <chapter id="pubfunctions"> | 1649 | <chapter id="pubfunctions"> |
| 1650 | <title>Public Functions Provided</title> | 1650 | <title>Public Functions Provided</title> |
| 1651 | !Edrivers/media/video/videodev.c | 1651 | !Edrivers/media/video/v4l2-dev.c |
| 1652 | </chapter> | 1652 | </chapter> |
| 1653 | 1653 | ||
| 1654 | </book> | 1654 | </book> |
diff --git a/Documentation/DocBook/z8530book.tmpl b/Documentation/DocBook/z8530book.tmpl index 42c75ba71ba2..a42a8a4c7689 100644 --- a/Documentation/DocBook/z8530book.tmpl +++ b/Documentation/DocBook/z8530book.tmpl | |||
| @@ -69,12 +69,6 @@ | |||
| 69 | device to be used as both a tty interface and as a synchronous | 69 | device to be used as both a tty interface and as a synchronous |
| 70 | controller is a project for Linux post the 2.4 release | 70 | controller is a project for Linux post the 2.4 release |
| 71 | </para> | 71 | </para> |
| 72 | <para> | ||
| 73 | The support code handles most common card configurations and | ||
| 74 | supports running both Cisco HDLC and Synchronous PPP. With extra | ||
| 75 | glue the frame relay and X.25 protocols can also be used with this | ||
| 76 | driver. | ||
| 77 | </para> | ||
| 78 | </chapter> | 72 | </chapter> |
| 79 | 73 | ||
| 80 | <chapter id="Driver_Modes"> | 74 | <chapter id="Driver_Modes"> |
| @@ -179,35 +173,27 @@ | |||
| 179 | <para> | 173 | <para> |
| 180 | If you wish to use the network interface facilities of the driver, | 174 | If you wish to use the network interface facilities of the driver, |
| 181 | then you need to attach a network device to each channel that is | 175 | then you need to attach a network device to each channel that is |
| 182 | present and in use. In addition to use the SyncPPP and Cisco HDLC | 176 | present and in use. In addition to use the generic HDLC |
| 183 | you need to follow some additional plumbing rules. They may seem | 177 | you need to follow some additional plumbing rules. They may seem |
| 184 | complex but a look at the example hostess_sv11 driver should | 178 | complex but a look at the example hostess_sv11 driver should |
| 185 | reassure you. | 179 | reassure you. |
| 186 | </para> | 180 | </para> |
| 187 | <para> | 181 | <para> |
| 188 | The network device used for each channel should be pointed to by | 182 | The network device used for each channel should be pointed to by |
| 189 | the netdevice field of each channel. The dev-> priv field of the | 183 | the netdevice field of each channel. The hdlc-> priv field of the |
| 190 | network device points to your private data - you will need to be | 184 | network device points to your private data - you will need to be |
| 191 | able to find your ppp device from this. In addition to use the | 185 | able to find your private data from this. |
| 192 | sync ppp layer the private data must start with a void * pointer | ||
| 193 | to the syncppp structures. | ||
| 194 | </para> | 186 | </para> |
| 195 | <para> | 187 | <para> |
| 196 | The way most drivers approach this particular problem is to | 188 | The way most drivers approach this particular problem is to |
| 197 | create a structure holding the Z8530 device definition and | 189 | create a structure holding the Z8530 device definition and |
| 198 | put that and the syncppp pointer into the private field of | 190 | put that into the private field of the network device. The |
| 199 | the network device. The network device fields of the channels | 191 | network device fields of the channels then point back to the |
| 200 | then point back to the network devices. The ppp_device can also | 192 | network devices. |
| 201 | be put in the private structure conveniently. | ||
| 202 | </para> | 193 | </para> |
| 203 | <para> | 194 | <para> |
| 204 | If you wish to use the synchronous ppp then you need to attach | 195 | If you wish to use the generic HDLC then you need to register |
| 205 | the syncppp layer to the network device. You should do this before | 196 | the HDLC device. |
| 206 | you register the network device. The | ||
| 207 | <function>sppp_attach</function> requires that the first void * | ||
| 208 | pointer in your private data is pointing to an empty struct | ||
| 209 | ppp_device. The function fills in the initial data for the | ||
| 210 | ppp/hdlc layer. | ||
| 211 | </para> | 197 | </para> |
| 212 | <para> | 198 | <para> |
| 213 | Before you register your network device you will also need to | 199 | Before you register your network device you will also need to |
| @@ -314,10 +300,10 @@ | |||
| 314 | buffer in sk_buff format and queues it for transmission. The | 300 | buffer in sk_buff format and queues it for transmission. The |
| 315 | caller must provide the entire packet with the exception of the | 301 | caller must provide the entire packet with the exception of the |
| 316 | bitstuffing and CRC. This is normally done by the caller via | 302 | bitstuffing and CRC. This is normally done by the caller via |
| 317 | the syncppp interface layer. It returns 0 if the buffer has been | 303 | the generic HDLC interface layer. It returns 0 if the buffer has been |
| 318 | queued and non zero values for queue full. If the function accepts | 304 | queued and non zero values for queue full. If the function accepts |
| 319 | the buffer it becomes property of the Z8530 layer and the caller | 305 | the buffer it becomes property of the Z8530 layer and the caller |
| 320 | should not free it. | 306 | should not free it. |
| 321 | </para> | 307 | </para> |
| 322 | <para> | 308 | <para> |
| 323 | The function <function>z8530_get_stats</function> returns a pointer | 309 | The function <function>z8530_get_stats</function> returns a pointer |
diff --git a/Documentation/cciss.txt b/Documentation/cciss.txt index 63e59b8847c5..8244c6442faa 100644 --- a/Documentation/cciss.txt +++ b/Documentation/cciss.txt | |||
| @@ -112,27 +112,18 @@ Hot plug support for SCSI tape drives | |||
| 112 | 112 | ||
| 113 | Hot plugging of SCSI tape drives is supported, with some caveats. | 113 | Hot plugging of SCSI tape drives is supported, with some caveats. |
| 114 | The cciss driver must be informed that changes to the SCSI bus | 114 | The cciss driver must be informed that changes to the SCSI bus |
| 115 | have been made, in addition to and prior to informing the SCSI | 115 | have been made. This may be done via the /proc filesystem. |
| 116 | mid layer. This may be done via the /proc filesystem. For example: | 116 | For example: |
| 117 | 117 | ||
| 118 | echo "rescan" > /proc/scsi/cciss0/1 | 118 | echo "rescan" > /proc/scsi/cciss0/1 |
| 119 | 119 | ||
| 120 | This causes the adapter to query the adapter about changes to the | 120 | This causes the driver to query the adapter about changes to the |
| 121 | physical SCSI buses and/or fibre channel arbitrated loop and the | 121 | physical SCSI buses and/or fibre channel arbitrated loop and the |
| 122 | driver to make note of any new or removed sequential access devices | 122 | driver to make note of any new or removed sequential access devices |
| 123 | or medium changers. The driver will output messages indicating what | 123 | or medium changers. The driver will output messages indicating what |
| 124 | devices have been added or removed and the controller, bus, target and | 124 | devices have been added or removed and the controller, bus, target and |
| 125 | lun used to address the device. Once this is done, the SCSI mid layer | 125 | lun used to address the device. It then notifies the SCSI mid layer |
| 126 | can be informed of changes to the virtual SCSI bus which the driver | 126 | of these changes. |
| 127 | presents to it in the usual way. For example: | ||
| 128 | |||
| 129 | echo scsi add-single-device 3 2 1 0 > /proc/scsi/scsi | ||
| 130 | |||
| 131 | to add a device on controller 3, bus 2, target 1, lun 0. Note that | ||
| 132 | the driver makes an effort to preserve the devices positions | ||
| 133 | in the virtual SCSI bus, so if you are only moving tape drives | ||
| 134 | around on the same adapter and not adding or removing tape drives | ||
| 135 | from the adapter, informing the SCSI mid layer may not be necessary. | ||
| 136 | 127 | ||
| 137 | Note that the naming convention of the /proc filesystem entries | 128 | Note that the naming convention of the /proc filesystem entries |
| 138 | contains a number in addition to the driver name. (E.g. "cciss0" | 129 | contains a number in addition to the driver name. (E.g. "cciss0" |
diff --git a/Documentation/hwmon/dme1737 b/Documentation/hwmon/dme1737 index b1fe00999439..001d2e70bc11 100644 --- a/Documentation/hwmon/dme1737 +++ b/Documentation/hwmon/dme1737 | |||
| @@ -10,6 +10,10 @@ Supported chips: | |||
| 10 | Prefix: 'sch311x' | 10 | Prefix: 'sch311x' |
| 11 | Addresses scanned: none, address read from Super-I/O config space | 11 | Addresses scanned: none, address read from Super-I/O config space |
| 12 | Datasheet: http://www.nuhorizons.com/FeaturedProducts/Volume1/SMSC/311x.pdf | 12 | Datasheet: http://www.nuhorizons.com/FeaturedProducts/Volume1/SMSC/311x.pdf |
| 13 | * SMSC SCH5027 | ||
| 14 | Prefix: 'sch5027' | ||
| 15 | Addresses scanned: I2C 0x2c, 0x2d, 0x2e | ||
| 16 | Datasheet: Provided by SMSC upon request and under NDA | ||
| 13 | 17 | ||
| 14 | Authors: | 18 | Authors: |
| 15 | Juerg Haefliger <juergh@gmail.com> | 19 | Juerg Haefliger <juergh@gmail.com> |
| @@ -27,33 +31,31 @@ Module Parameters | |||
| 27 | following boards: | 31 | following boards: |
| 28 | - VIA EPIA SN18000 | 32 | - VIA EPIA SN18000 |
| 29 | 33 | ||
| 30 | Note that there is no need to use this parameter if the driver loads without | ||
| 31 | complaining. The driver will say so if it is necessary. | ||
| 32 | |||
| 33 | 34 | ||
| 34 | Description | 35 | Description |
| 35 | ----------- | 36 | ----------- |
| 36 | 37 | ||
| 37 | This driver implements support for the hardware monitoring capabilities of the | 38 | This driver implements support for the hardware monitoring capabilities of the |
| 38 | SMSC DME1737 and Asus A8000 (which are the same) and SMSC SCH311x Super-I/O | 39 | SMSC DME1737 and Asus A8000 (which are the same), SMSC SCH5027, and SMSC |
| 39 | chips. These chips feature monitoring of 3 temp sensors temp[1-3] (2 remote | 40 | SCH311x Super-I/O chips. These chips feature monitoring of 3 temp sensors |
| 40 | diodes and 1 internal), 7 voltages in[0-6] (6 external and 1 internal) and up | 41 | temp[1-3] (2 remote diodes and 1 internal), 7 voltages in[0-6] (6 external and |
| 41 | to 6 fan speeds fan[1-6]. Additionally, the chips implement up to 5 PWM | 42 | 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement |
| 42 | outputs pwm[1-3,5-6] for controlling fan speeds both manually and | 43 | up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and |
| 43 | automatically. | 44 | automatically. |
| 44 | 45 | ||
| 45 | For the DME1737 and A8000, fan[1-2] and pwm[1-2] are always present. Fan[3-6] | 46 | For the DME1737, A8000 and SCH5027, fan[1-2] and pwm[1-2] are always present. |
| 46 | and pwm[3,5-6] are optional features and their availability depends on the | 47 | Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on |
| 47 | configuration of the chip. The driver will detect which features are present | 48 | the configuration of the chip. The driver will detect which features are |
| 48 | during initialization and create the sysfs attributes accordingly. | 49 | present during initialization and create the sysfs attributes accordingly. |
| 49 | 50 | ||
| 50 | For the SCH311x, fan[1-3] and pwm[1-3] are always present and fan[4-6] and | 51 | For the SCH311x, fan[1-3] and pwm[1-3] are always present and fan[4-6] and |
| 51 | pwm[5-6] don't exist. | 52 | pwm[5-6] don't exist. |
| 52 | 53 | ||
| 53 | The hardware monitoring features of the DME1737 and A8000 are only accessible | 54 | The hardware monitoring features of the DME1737, A8000, and SCH5027 are only |
| 54 | via SMBus, while the SCH311x only provides access via the ISA bus. The driver | 55 | accessible via SMBus, while the SCH311x only provides access via the ISA bus. |
| 55 | will therefore register itself as an I2C client driver if it detects a DME1737 | 56 | The driver will therefore register itself as an I2C client driver if it detects |
| 56 | or A8000 and as a platform driver if it detects a SCH311x chip. | 57 | a DME1737, A8000, or SCH5027 and as a platform driver if it detects a SCH311x |
| 58 | chip. | ||
| 57 | 59 | ||
| 58 | 60 | ||
| 59 | Voltage Monitoring | 61 | Voltage Monitoring |
| @@ -64,6 +66,7 @@ scaling resistors. The values returned by the driver therefore reflect true | |||
| 64 | millivolts and don't need scaling. The voltage inputs are mapped as follows | 66 | millivolts and don't need scaling. The voltage inputs are mapped as follows |
| 65 | (the last column indicates the input ranges): | 67 | (the last column indicates the input ranges): |
| 66 | 68 | ||
| 69 | DME1737, A8000: | ||
| 67 | in0: +5VTR (+5V standby) 0V - 6.64V | 70 | in0: +5VTR (+5V standby) 0V - 6.64V |
| 68 | in1: Vccp (processor core) 0V - 3V | 71 | in1: Vccp (processor core) 0V - 3V |
| 69 | in2: VCC (internal +3.3V) 0V - 4.38V | 72 | in2: VCC (internal +3.3V) 0V - 4.38V |
| @@ -72,6 +75,24 @@ millivolts and don't need scaling. The voltage inputs are mapped as follows | |||
| 72 | in5: VTR (+3.3V standby) 0V - 4.38V | 75 | in5: VTR (+3.3V standby) 0V - 4.38V |
| 73 | in6: Vbat (+3.0V) 0V - 4.38V | 76 | in6: Vbat (+3.0V) 0V - 4.38V |
| 74 | 77 | ||
| 78 | SCH311x: | ||
| 79 | in0: +2.5V 0V - 6.64V | ||
| 80 | in1: Vccp (processor core) 0V - 2V | ||
| 81 | in2: VCC (internal +3.3V) 0V - 4.38V | ||
| 82 | in3: +5V 0V - 6.64V | ||
| 83 | in4: +12V 0V - 16V | ||
| 84 | in5: VTR (+3.3V standby) 0V - 4.38V | ||
| 85 | in6: Vbat (+3.0V) 0V - 4.38V | ||
| 86 | |||
| 87 | SCH5027: | ||
| 88 | in0: +5VTR (+5V standby) 0V - 6.64V | ||
| 89 | in1: Vccp (processor core) 0V - 3V | ||
| 90 | in2: VCC (internal +3.3V) 0V - 4.38V | ||
| 91 | in3: V2_IN 0V - 1.5V | ||
| 92 | in4: V1_IN 0V - 1.5V | ||
| 93 | in5: VTR (+3.3V standby) 0V - 4.38V | ||
| 94 | in6: Vbat (+3.0V) 0V - 4.38V | ||
| 95 | |||
| 75 | Each voltage input has associated min and max limits which trigger an alarm | 96 | Each voltage input has associated min and max limits which trigger an alarm |
| 76 | when crossed. | 97 | when crossed. |
| 77 | 98 | ||
diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 index f4ce1fdbeff6..3496b7020e7c 100644 --- a/Documentation/hwmon/it87 +++ b/Documentation/hwmon/it87 | |||
| @@ -6,12 +6,14 @@ Supported chips: | |||
| 6 | Prefix: 'it87' | 6 | Prefix: 'it87' |
| 7 | Addresses scanned: from Super I/O config space (8 I/O ports) | 7 | Addresses scanned: from Super I/O config space (8 I/O ports) |
| 8 | Datasheet: Publicly available at the ITE website | 8 | Datasheet: Publicly available at the ITE website |
| 9 | http://www.ite.com.tw/ | 9 | http://www.ite.com.tw/product_info/file/pc/IT8705F_V.0.4.1.pdf |
| 10 | * IT8712F | 10 | * IT8712F |
| 11 | Prefix: 'it8712' | 11 | Prefix: 'it8712' |
| 12 | Addresses scanned: from Super I/O config space (8 I/O ports) | 12 | Addresses scanned: from Super I/O config space (8 I/O ports) |
| 13 | Datasheet: Publicly available at the ITE website | 13 | Datasheet: Publicly available at the ITE website |
| 14 | http://www.ite.com.tw/ | 14 | http://www.ite.com.tw/product_info/file/pc/IT8712F_V0.9.1.pdf |
| 15 | http://www.ite.com.tw/product_info/file/pc/Errata%20V0.1%20for%20IT8712F%20V0.9.1.pdf | ||
| 16 | http://www.ite.com.tw/product_info/file/pc/IT8712F_V0.9.3.pdf | ||
| 15 | * IT8716F/IT8726F | 17 | * IT8716F/IT8726F |
| 16 | Prefix: 'it8716' | 18 | Prefix: 'it8716' |
| 17 | Addresses scanned: from Super I/O config space (8 I/O ports) | 19 | Addresses scanned: from Super I/O config space (8 I/O ports) |
| @@ -90,14 +92,13 @@ upper VID bits share their pins with voltage inputs (in5 and in6) so you | |||
| 90 | can't have both on a given board. | 92 | can't have both on a given board. |
| 91 | 93 | ||
| 92 | The IT8716F, IT8718F and later IT8712F revisions have support for | 94 | The IT8716F, IT8718F and later IT8712F revisions have support for |
| 93 | 2 additional fans. They are supported by the driver for the IT8716F and | 95 | 2 additional fans. The additional fans are supported by the driver. |
| 94 | IT8718F but not for the IT8712F | ||
| 95 | 96 | ||
| 96 | The IT8716F and IT8718F, and late IT8712F and IT8705F also have optional | 97 | The IT8716F and IT8718F, and late IT8712F and IT8705F also have optional |
| 97 | 16-bit tachometer counters for fans 1 to 3. This is better (no more fan | 98 | 16-bit tachometer counters for fans 1 to 3. This is better (no more fan |
| 98 | clock divider mess) but not compatible with the older chips and | 99 | clock divider mess) but not compatible with the older chips and |
| 99 | revisions. For now, the driver only uses the 16-bit mode on the | 100 | revisions. The 16-bit tachometer mode is enabled by the driver when one |
| 100 | IT8716F and IT8718F. | 101 | of the above chips is detected. |
| 101 | 102 | ||
| 102 | The IT8726F is just bit enhanced IT8716F with additional hardware | 103 | The IT8726F is just bit enhanced IT8716F with additional hardware |
| 103 | for AMD power sequencing. Therefore the chip will appear as IT8716F | 104 | for AMD power sequencing. Therefore the chip will appear as IT8716F |
diff --git a/Documentation/hwmon/w83627hf b/Documentation/hwmon/w83627hf index 880a59f53da9..6ee36dbafd64 100644 --- a/Documentation/hwmon/w83627hf +++ b/Documentation/hwmon/w83627hf | |||
| @@ -40,10 +40,6 @@ Module Parameters | |||
| 40 | (default is 1) | 40 | (default is 1) |
| 41 | Use 'init=0' to bypass initializing the chip. | 41 | Use 'init=0' to bypass initializing the chip. |
| 42 | Try this if your computer crashes when you load the module. | 42 | Try this if your computer crashes when you load the module. |
| 43 | * reset: int | ||
| 44 | (default is 0) | ||
| 45 | The driver used to reset the chip on load, but does no more. Use | ||
| 46 | 'reset=1' to restore the old behavior. Report if you need to do this. | ||
| 47 | 43 | ||
| 48 | Description | 44 | Description |
| 49 | ----------- | 45 | ----------- |
diff --git a/Documentation/hwmon/w83791d b/Documentation/hwmon/w83791d index f153b2f6d62c..a67d3b7a7098 100644 --- a/Documentation/hwmon/w83791d +++ b/Documentation/hwmon/w83791d | |||
| @@ -22,6 +22,7 @@ Credits: | |||
| 22 | 22 | ||
| 23 | Additional contributors: | 23 | Additional contributors: |
| 24 | Sven Anders <anders@anduras.de> | 24 | Sven Anders <anders@anduras.de> |
| 25 | Marc Hulsman <m.hulsman@tudelft.nl> | ||
| 25 | 26 | ||
| 26 | Module Parameters | 27 | Module Parameters |
| 27 | ----------------- | 28 | ----------------- |
| @@ -67,9 +68,8 @@ on until the temperature falls below the Hysteresis value. | |||
| 67 | 68 | ||
| 68 | Fan rotation speeds are reported in RPM (rotations per minute). An alarm is | 69 | Fan rotation speeds are reported in RPM (rotations per minute). An alarm is |
| 69 | triggered if the rotation speed has dropped below a programmable limit. Fan | 70 | triggered if the rotation speed has dropped below a programmable limit. Fan |
| 70 | readings can be divided by a programmable divider (1, 2, 4, 8 for fan 1/2/3 | 71 | readings can be divided by a programmable divider (1, 2, 4, 8, 16, |
| 71 | and 1, 2, 4, 8, 16, 32, 64 or 128 for fan 4/5) to give the readings more | 72 | 32, 64 or 128 for all fans) to give the readings more range or accuracy. |
| 72 | range or accuracy. | ||
| 73 | 73 | ||
| 74 | Voltage sensors (also known as IN sensors) report their values in millivolts. | 74 | Voltage sensors (also known as IN sensors) report their values in millivolts. |
| 75 | An alarm is triggered if the voltage has crossed a programmable minimum | 75 | An alarm is triggered if the voltage has crossed a programmable minimum |
diff --git a/Documentation/video4linux/gspca.txt b/Documentation/video4linux/gspca.txt index bcaf4ab383be..78a863ab8a5a 100644 --- a/Documentation/video4linux/gspca.txt +++ b/Documentation/video4linux/gspca.txt | |||
| @@ -226,6 +226,7 @@ sonixj 0c45:6130 Sonix Pccam | |||
| 226 | sonixj 0c45:6138 Sn9c120 Mo4000 | 226 | sonixj 0c45:6138 Sn9c120 Mo4000 |
| 227 | sonixj 0c45:613b Surfer SN-206 | 227 | sonixj 0c45:613b Surfer SN-206 |
| 228 | sonixj 0c45:613c Sonix Pccam168 | 228 | sonixj 0c45:613c Sonix Pccam168 |
| 229 | sonixj 0c45:6143 Sonix Pccam168 | ||
| 229 | sunplus 0d64:0303 Sunplus FashionCam DXG | 230 | sunplus 0d64:0303 Sunplus FashionCam DXG |
| 230 | etoms 102c:6151 Qcam Sangha CIF | 231 | etoms 102c:6151 Qcam Sangha CIF |
| 231 | etoms 102c:6251 Qcam xxxxxx VGA | 232 | etoms 102c:6251 Qcam xxxxxx VGA |
diff --git a/MAINTAINERS b/MAINTAINERS index 8223a521d7c3..41d7a1ed03d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -594,6 +594,11 @@ M: kernel@wantstofly.org | |||
| 594 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | 594 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) |
| 595 | S: Maintained | 595 | S: Maintained |
| 596 | 596 | ||
| 597 | ARM/MAGICIAN MACHINE SUPPORT | ||
| 598 | P: Philipp Zabel | ||
| 599 | M: philipp.zabel@gmail.com | ||
| 600 | S: Maintained | ||
| 601 | |||
| 597 | ARM/TOSA MACHINE SUPPORT | 602 | ARM/TOSA MACHINE SUPPORT |
| 598 | P: Dmitry Baryshkov | 603 | P: Dmitry Baryshkov |
| 599 | M: dbaryshkov@gmail.com | 604 | M: dbaryshkov@gmail.com |
| @@ -720,6 +725,15 @@ L: linux-wireless@vger.kernel.org | |||
| 720 | L: ath5k-devel@lists.ath5k.org | 725 | L: ath5k-devel@lists.ath5k.org |
| 721 | S: Maintained | 726 | S: Maintained |
| 722 | 727 | ||
| 728 | ATHEROS ATH9K WIRELESS DRIVER | ||
| 729 | P: Luis R. Rodriguez | ||
| 730 | M: lrodriguez@atheros.com | ||
| 731 | P: Jouni Malinen | ||
| 732 | M: jmalinen@atheros.com | ||
| 733 | L: linux-wireless@vger.kernel.org | ||
| 734 | L: ath9k-devel@lists.ath9k.org | ||
| 735 | S: Supported | ||
| 736 | |||
| 723 | ATI_REMOTE2 DRIVER | 737 | ATI_REMOTE2 DRIVER |
| 724 | P: Ville Syrjala | 738 | P: Ville Syrjala |
| 725 | M: syrjala@sci.fi | 739 | M: syrjala@sci.fi |
| @@ -1235,7 +1249,7 @@ S: Maintained | |||
| 1235 | CPU FREQUENCY DRIVERS | 1249 | CPU FREQUENCY DRIVERS |
| 1236 | P: Dave Jones | 1250 | P: Dave Jones |
| 1237 | M: davej@codemonkey.org.uk | 1251 | M: davej@codemonkey.org.uk |
| 1238 | L: cpufreq@lists.linux.org.uk | 1252 | L: cpufreq@vger.kernel.org |
| 1239 | W: http://www.codemonkey.org.uk/projects/cpufreq/ | 1253 | W: http://www.codemonkey.org.uk/projects/cpufreq/ |
| 1240 | T: git kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git | 1254 | T: git kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git |
| 1241 | S: Maintained | 1255 | S: Maintained |
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 5a7c09564d13..e9842f6767f9 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
| @@ -100,7 +100,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 100 | * a 1:1 mapping for the physical address of the kernel. | 100 | * a 1:1 mapping for the physical address of the kernel. |
| 101 | */ | 101 | */ |
| 102 | pgd = pgd_alloc(&init_mm); | 102 | pgd = pgd_alloc(&init_mm); |
| 103 | pmd = pmd_offset(pgd, PHYS_OFFSET); | 103 | pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET); |
| 104 | *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | | 104 | *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | |
| 105 | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); | 105 | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); |
| 106 | 106 | ||
| @@ -139,7 +139,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 139 | secondary_data.stack = NULL; | 139 | secondary_data.stack = NULL; |
| 140 | secondary_data.pgdir = 0; | 140 | secondary_data.pgdir = 0; |
| 141 | 141 | ||
| 142 | *pmd_offset(pgd, PHYS_OFFSET) = __pmd(0); | 142 | *pmd = __pmd(0); |
| 143 | pgd_free(&init_mm, pgd); | 143 | pgd_free(&init_mm, pgd); |
| 144 | 144 | ||
| 145 | if (ret) { | 145 | if (ret) { |
diff --git a/arch/arm/mach-pnx4008/include/mach/i2c.h b/arch/arm/mach-pnx4008/include/mach/i2c.h index 92e8d65006f7..259ac53abf40 100644 --- a/arch/arm/mach-pnx4008/include/mach/i2c.h +++ b/arch/arm/mach-pnx4008/include/mach/i2c.h | |||
| @@ -12,9 +12,6 @@ | |||
| 12 | #ifndef __ASM_ARCH_I2C_H__ | 12 | #ifndef __ASM_ARCH_I2C_H__ |
| 13 | #define __ASM_ARCH_I2C_H__ | 13 | #define __ASM_ARCH_I2C_H__ |
| 14 | 14 | ||
| 15 | #include <linux/pm.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | |||
| 18 | enum { | 15 | enum { |
| 19 | mstatus_tdi = 0x00000001, | 16 | mstatus_tdi = 0x00000001, |
| 20 | mstatus_afi = 0x00000002, | 17 | mstatus_afi = 0x00000002, |
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 2834b7fff78c..ceaed0076366 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
| @@ -26,9 +26,19 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | 27 | ||
| 28 | #include <mach/pxa-regs.h> | 28 | #include <mach/pxa-regs.h> |
| 29 | #include <mach/reset.h> | ||
| 29 | 30 | ||
| 30 | #include "generic.h" | 31 | #include "generic.h" |
| 31 | 32 | ||
| 33 | void clear_reset_status(unsigned int mask) | ||
| 34 | { | ||
| 35 | if (cpu_is_pxa2xx()) | ||
| 36 | pxa2xx_clear_reset_status(mask); | ||
| 37 | |||
| 38 | if (cpu_is_pxa3xx()) | ||
| 39 | pxa3xx_clear_reset_status(mask); | ||
| 40 | } | ||
| 41 | |||
| 32 | /* | 42 | /* |
| 33 | * Get the clock frequency as reflected by CCCR and the turbo flag. | 43 | * Get the clock frequency as reflected by CCCR and the turbo flag. |
| 34 | * We assume these values have been applied via a fcs. | 44 | * We assume these values have been applied via a fcs. |
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 5bb7ae757831..041c048320e4 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
| @@ -47,12 +47,20 @@ extern unsigned pxa27x_get_memclk_frequency_10khz(void); | |||
| 47 | #define pxa27x_get_memclk_frequency_10khz() (0) | 47 | #define pxa27x_get_memclk_frequency_10khz() (0) |
| 48 | #endif | 48 | #endif |
| 49 | 49 | ||
| 50 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) | ||
| 51 | extern void pxa2xx_clear_reset_status(unsigned int); | ||
| 52 | #else | ||
| 53 | static inline void pxa2xx_clear_reset_status(unsigned int mask) {} | ||
| 54 | #endif | ||
| 55 | |||
| 50 | #ifdef CONFIG_PXA3xx | 56 | #ifdef CONFIG_PXA3xx |
| 51 | extern unsigned pxa3xx_get_clk_frequency_khz(int); | 57 | extern unsigned pxa3xx_get_clk_frequency_khz(int); |
| 52 | extern unsigned pxa3xx_get_memclk_frequency_10khz(void); | 58 | extern unsigned pxa3xx_get_memclk_frequency_10khz(void); |
| 59 | extern void pxa3xx_clear_reset_status(unsigned int); | ||
| 53 | #else | 60 | #else |
| 54 | #define pxa3xx_get_clk_frequency_khz(x) (0) | 61 | #define pxa3xx_get_clk_frequency_khz(x) (0) |
| 55 | #define pxa3xx_get_memclk_frequency_10khz() (0) | 62 | #define pxa3xx_get_memclk_frequency_10khz() (0) |
| 63 | static inline void pxa3xx_clear_reset_status(unsigned int mask) {} | ||
| 56 | #endif | 64 | #endif |
| 57 | 65 | ||
| 58 | extern struct sysdev_class pxa_irq_sysclass; | 66 | extern struct sysdev_class pxa_irq_sysclass; |
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index f8fb1e75997f..e89df4d0d239 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h | |||
| @@ -224,11 +224,6 @@ extern void pxa_gpio_set_value(unsigned gpio, int value); | |||
| 224 | */ | 224 | */ |
| 225 | extern unsigned int get_memclk_frequency_10khz(void); | 225 | extern unsigned int get_memclk_frequency_10khz(void); |
| 226 | 226 | ||
| 227 | /* | ||
| 228 | * register GPIO as reset generator | ||
| 229 | */ | ||
| 230 | extern int init_gpio_reset(int gpio); | ||
| 231 | |||
| 232 | #endif | 227 | #endif |
| 233 | 228 | ||
| 234 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) | 229 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) |
diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h new file mode 100644 index 000000000000..9489a48871a8 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/reset.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | #ifndef __ASM_ARCH_RESET_H | ||
| 2 | #define __ASM_ARCH_RESET_H | ||
| 3 | |||
| 4 | #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ | ||
| 5 | #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ | ||
| 6 | #define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */ | ||
| 7 | #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ | ||
| 8 | #define RESET_STATUS_ALL (0xf) | ||
| 9 | |||
| 10 | extern unsigned int reset_status; | ||
| 11 | extern void clear_reset_status(unsigned int mask); | ||
| 12 | |||
| 13 | /* | ||
| 14 | * register GPIO as reset generator | ||
| 15 | */ | ||
| 16 | extern int init_gpio_reset(int gpio); | ||
| 17 | |||
| 18 | #endif /* __ASM_ARCH_RESET_H */ | ||
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 4ba8d3190721..bb9e09208b9f 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
| @@ -224,7 +224,7 @@ static struct platform_device sa1111_device = { | |||
| 224 | * for the temperature sensors. | 224 | * for the temperature sensors. |
| 225 | */ | 225 | */ |
| 226 | static struct pxa2xx_spi_master pxa_ssp_master_info = { | 226 | static struct pxa2xx_spi_master pxa_ssp_master_info = { |
| 227 | .num_chipselect = 0, | 227 | .num_chipselect = 1, |
| 228 | }; | 228 | }; |
| 229 | 229 | ||
| 230 | static int lubbock_ads7846_pendown_state(void) | 230 | static int lubbock_ads7846_pendown_state(void) |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 3c2d22de9a13..9e5d8a8c6424 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <mach/pxa-regs.h> | 28 | #include <mach/pxa-regs.h> |
| 29 | #include <mach/pxa2xx-regs.h> | 29 | #include <mach/pxa2xx-regs.h> |
| 30 | #include <mach/mfp-pxa25x.h> | 30 | #include <mach/mfp-pxa25x.h> |
| 31 | #include <mach/reset.h> | ||
| 31 | #include <mach/pm.h> | 32 | #include <mach/pm.h> |
| 32 | #include <mach/dma.h> | 33 | #include <mach/dma.h> |
| 33 | 34 | ||
| @@ -348,6 +349,9 @@ static int __init pxa25x_init(void) | |||
| 348 | clks_register(&pxa25x_hwuart_clk, 1); | 349 | clks_register(&pxa25x_hwuart_clk, 1); |
| 349 | 350 | ||
| 350 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { | 351 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { |
| 352 | |||
| 353 | reset_status = RCSR; | ||
| 354 | |||
| 351 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); | 355 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); |
| 352 | 356 | ||
| 353 | if ((ret = pxa_init_dma(16))) | 357 | if ((ret = pxa_init_dma(16))) |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 6bec43484ba7..f9f6a9c31f4b 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <mach/pxa-regs.h> | 24 | #include <mach/pxa-regs.h> |
| 25 | #include <mach/pxa2xx-regs.h> | 25 | #include <mach/pxa2xx-regs.h> |
| 26 | #include <mach/mfp-pxa27x.h> | 26 | #include <mach/mfp-pxa27x.h> |
| 27 | #include <mach/reset.h> | ||
| 27 | #include <mach/ohci.h> | 28 | #include <mach/ohci.h> |
| 28 | #include <mach/pm.h> | 29 | #include <mach/pm.h> |
| 29 | #include <mach/dma.h> | 30 | #include <mach/dma.h> |
| @@ -384,6 +385,9 @@ static int __init pxa27x_init(void) | |||
| 384 | int i, ret = 0; | 385 | int i, ret = 0; |
| 385 | 386 | ||
| 386 | if (cpu_is_pxa27x()) { | 387 | if (cpu_is_pxa27x()) { |
| 388 | |||
| 389 | reset_status = RCSR; | ||
| 390 | |||
| 387 | clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); | 391 | clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); |
| 388 | 392 | ||
| 389 | if ((ret = pxa_init_dma(32))) | 393 | if ((ret = pxa_init_dma(32))) |
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index 00b4de6d6bdd..73d04d81c75a 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c | |||
| @@ -14,10 +14,19 @@ | |||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
| 16 | 16 | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | #include <mach/pxa2xx-regs.h> | ||
| 17 | #include <mach/mfp-pxa2xx.h> | 19 | #include <mach/mfp-pxa2xx.h> |
| 18 | #include <mach/mfp-pxa25x.h> | 20 | #include <mach/mfp-pxa25x.h> |
| 21 | #include <mach/reset.h> | ||
| 19 | #include <mach/irda.h> | 22 | #include <mach/irda.h> |
| 20 | 23 | ||
| 24 | void pxa2xx_clear_reset_status(unsigned int mask) | ||
| 25 | { | ||
| 26 | /* RESET_STATUS_* has a 1:1 mapping with RCSR */ | ||
| 27 | RCSR = mask; | ||
| 28 | } | ||
| 29 | |||
| 21 | static unsigned long pxa2xx_mfp_fir[] = { | 30 | static unsigned long pxa2xx_mfp_fir[] = { |
| 22 | GPIO46_FICP_RXD, | 31 | GPIO46_FICP_RXD, |
| 23 | GPIO47_FICP_TXD, | 32 | GPIO47_FICP_TXD, |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 37b07212b5a5..03cbc38103ed 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <mach/pxa3xx-regs.h> | 26 | #include <mach/pxa3xx-regs.h> |
| 27 | #include <mach/reset.h> | ||
| 27 | #include <mach/ohci.h> | 28 | #include <mach/ohci.h> |
| 28 | #include <mach/pm.h> | 29 | #include <mach/pm.h> |
| 29 | #include <mach/dma.h> | 30 | #include <mach/dma.h> |
| @@ -109,6 +110,12 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void) | |||
| 109 | return (clk / 10000); | 110 | return (clk / 10000); |
| 110 | } | 111 | } |
| 111 | 112 | ||
| 113 | void pxa3xx_clear_reset_status(unsigned int mask) | ||
| 114 | { | ||
| 115 | /* RESET_STATUS_* has a 1:1 mapping with ARSR */ | ||
| 116 | ARSR = mask; | ||
| 117 | } | ||
| 118 | |||
| 112 | /* | 119 | /* |
| 113 | * Return the current AC97 clock frequency. | 120 | * Return the current AC97 clock frequency. |
| 114 | */ | 121 | */ |
| @@ -532,6 +539,9 @@ static int __init pxa3xx_init(void) | |||
| 532 | int i, ret = 0; | 539 | int i, ret = 0; |
| 533 | 540 | ||
| 534 | if (cpu_is_pxa3xx()) { | 541 | if (cpu_is_pxa3xx()) { |
| 542 | |||
| 543 | reset_status = ARSR; | ||
| 544 | |||
| 535 | /* | 545 | /* |
| 536 | * clear RDH bit every time after reset | 546 | * clear RDH bit every time after reset |
| 537 | * | 547 | * |
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index fabead71d681..9996c612c3d6 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c | |||
| @@ -11,7 +11,10 @@ | |||
| 11 | #include <asm/proc-fns.h> | 11 | #include <asm/proc-fns.h> |
| 12 | 12 | ||
| 13 | #include <mach/pxa-regs.h> | 13 | #include <mach/pxa-regs.h> |
| 14 | #include <mach/pxa2xx-regs.h> | 14 | #include <mach/reset.h> |
| 15 | |||
| 16 | unsigned int reset_status; | ||
| 17 | EXPORT_SYMBOL(reset_status); | ||
| 15 | 18 | ||
| 16 | static void do_hw_reset(void); | 19 | static void do_hw_reset(void); |
| 17 | 20 | ||
| @@ -77,8 +80,7 @@ static void do_hw_reset(void) | |||
| 77 | 80 | ||
| 78 | void arch_reset(char mode) | 81 | void arch_reset(char mode) |
| 79 | { | 82 | { |
| 80 | if (cpu_is_pxa2xx()) | 83 | clear_reset_status(RESET_STATUS_ALL); |
| 81 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | ||
| 82 | 84 | ||
| 83 | switch (mode) { | 85 | switch (mode) { |
| 84 | case 's': | 86 | case 's': |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 26b9fa56cffd..cd39005c98ff 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | #include <mach/pxa2xx-regs.h> | 39 | #include <mach/pxa2xx-regs.h> |
| 40 | #include <mach/pxa2xx-gpio.h> | 40 | #include <mach/pxa2xx-gpio.h> |
| 41 | #include <mach/pxa27x-udc.h> | 41 | #include <mach/pxa27x-udc.h> |
| 42 | #include <mach/reset.h> | ||
| 42 | #include <mach/irda.h> | 43 | #include <mach/irda.h> |
| 43 | #include <mach/mmc.h> | 44 | #include <mach/mmc.h> |
| 44 | #include <mach/ohci.h> | 45 | #include <mach/ohci.h> |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 38bc59c44110..5dab30eafddc 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| 37 | #include <mach/pxa2xx-regs.h> | 37 | #include <mach/pxa2xx-regs.h> |
| 38 | #include <mach/mfp-pxa25x.h> | 38 | #include <mach/mfp-pxa25x.h> |
| 39 | #include <mach/reset.h> | ||
| 39 | #include <mach/irda.h> | 40 | #include <mach/irda.h> |
| 40 | #include <mach/i2c.h> | 41 | #include <mach/i2c.h> |
| 41 | #include <mach/mmc.h> | 42 | #include <mach/mmc.h> |
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 8e0244631d65..8a5546e6d547 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile | |||
| @@ -46,9 +46,6 @@ led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o | |||
| 46 | # LEDs support | 46 | # LEDs support |
| 47 | obj-$(CONFIG_LEDS) += $(led-y) | 47 | obj-$(CONFIG_LEDS) += $(led-y) |
| 48 | 48 | ||
| 49 | # SA1110 USB client support | ||
| 50 | #obj-$(CONFIG_SA1100_USB) += usb/ | ||
| 51 | |||
| 52 | # Miscelaneous functions | 49 | # Miscelaneous functions |
| 53 | obj-$(CONFIG_PM) += pm.o sleep.o | 50 | obj-$(CONFIG_PM) += pm.o sleep.o |
| 54 | obj-$(CONFIG_SA1100_SSP) += ssp.o | 51 | obj-$(CONFIG_SA1100_SSP) += ssp.o |
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 5a08fe20a319..1362994c78aa 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
| @@ -31,6 +31,9 @@ | |||
| 31 | 31 | ||
| 32 | #include "generic.h" | 32 | #include "generic.h" |
| 33 | 33 | ||
| 34 | unsigned int reset_status; | ||
| 35 | EXPORT_SYMBOL(reset_status); | ||
| 36 | |||
| 34 | #define NR_FREQS 16 | 37 | #define NR_FREQS 16 |
| 35 | 38 | ||
| 36 | /* | 39 | /* |
diff --git a/arch/arm/mach-sa1100/include/mach/reset.h b/arch/arm/mach-sa1100/include/mach/reset.h new file mode 100644 index 000000000000..f61957e6842a --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/reset.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | #ifndef __ASM_ARCH_RESET_H | ||
| 2 | #define __ASM_ARCH_RESET_H | ||
| 3 | |||
| 4 | #include "hardware.h" | ||
| 5 | |||
| 6 | #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ | ||
| 7 | #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ | ||
| 8 | #define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */ | ||
| 9 | #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ | ||
| 10 | #define RESET_STATUS_ALL (0xf) | ||
| 11 | |||
| 12 | extern unsigned int reset_status; | ||
| 13 | static inline void clear_reset_status(unsigned int mask) | ||
| 14 | { | ||
| 15 | RCSR = mask; | ||
| 16 | } | ||
| 17 | |||
| 18 | #endif /* __ASM_ARCH_RESET_H */ | ||
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 451f2ffb137b..48e496fe1e75 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig | |||
| @@ -171,8 +171,8 @@ config IA64_SGI_SN2 | |||
| 171 | to select this option. If in doubt, select ia64 generic support | 171 | to select this option. If in doubt, select ia64 generic support |
| 172 | instead. | 172 | instead. |
| 173 | 173 | ||
| 174 | config IA64_SGI_UV` | 174 | config IA64_SGI_UV |
| 175 | bool "SGI-UV`" | 175 | bool "SGI-UV" |
| 176 | select NUMA | 176 | select NUMA |
| 177 | select ACPI_NUMA | 177 | select ACPI_NUMA |
| 178 | select SWIOTLB | 178 | select SWIOTLB |
| @@ -321,10 +321,10 @@ config SMP | |||
| 321 | If you don't know what to do here, say N. | 321 | If you don't know what to do here, say N. |
| 322 | 322 | ||
| 323 | config NR_CPUS | 323 | config NR_CPUS |
| 324 | int "Maximum number of CPUs (2-1024)" | 324 | int "Maximum number of CPUs (2-4096)" |
| 325 | range 2 1024 | 325 | range 2 4096 |
| 326 | depends on SMP | 326 | depends on SMP |
| 327 | default "1024" | 327 | default "4096" |
| 328 | help | 328 | help |
| 329 | You should set this to the number of CPUs in your system, but | 329 | You should set this to the number of CPUs in your system, but |
| 330 | keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but | 330 | keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but |
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig index 0210545e7f61..9f483976228f 100644 --- a/arch/ia64/configs/generic_defconfig +++ b/arch/ia64/configs/generic_defconfig | |||
| @@ -1,20 +1,16 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.22 | 3 | # Linux kernel version: 2.6.27-rc1 |
| 4 | # Thu Jul 19 13:55:32 2007 | 4 | # Mon Aug 4 15:38:01 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 6 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 7 | 7 | ||
| 8 | # | 8 | # |
| 9 | # Code maturity level options | 9 | # General setup |
| 10 | # | 10 | # |
| 11 | CONFIG_EXPERIMENTAL=y | 11 | CONFIG_EXPERIMENTAL=y |
| 12 | CONFIG_LOCK_KERNEL=y | 12 | CONFIG_LOCK_KERNEL=y |
| 13 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 13 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 14 | |||
| 15 | # | ||
| 16 | # General setup | ||
| 17 | # | ||
| 18 | CONFIG_LOCALVERSION="" | 14 | CONFIG_LOCALVERSION="" |
| 19 | CONFIG_LOCALVERSION_AUTO=y | 15 | CONFIG_LOCALVERSION_AUTO=y |
| 20 | CONFIG_SWAP=y | 16 | CONFIG_SWAP=y |
| @@ -23,20 +19,34 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 23 | CONFIG_POSIX_MQUEUE=y | 19 | CONFIG_POSIX_MQUEUE=y |
| 24 | # CONFIG_BSD_PROCESS_ACCT is not set | 20 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 25 | # CONFIG_TASKSTATS is not set | 21 | # CONFIG_TASKSTATS is not set |
| 26 | # CONFIG_USER_NS is not set | ||
| 27 | # CONFIG_AUDIT is not set | 22 | # CONFIG_AUDIT is not set |
| 28 | CONFIG_IKCONFIG=y | 23 | CONFIG_IKCONFIG=y |
| 29 | CONFIG_IKCONFIG_PROC=y | 24 | CONFIG_IKCONFIG_PROC=y |
| 30 | CONFIG_LOG_BUF_SHIFT=20 | 25 | CONFIG_LOG_BUF_SHIFT=20 |
| 31 | # CONFIG_CPUSETS is not set | 26 | CONFIG_CGROUPS=y |
| 27 | # CONFIG_CGROUP_DEBUG is not set | ||
| 28 | # CONFIG_CGROUP_NS is not set | ||
| 29 | # CONFIG_CGROUP_DEVICE is not set | ||
| 30 | CONFIG_CPUSETS=y | ||
| 31 | # CONFIG_GROUP_SCHED is not set | ||
| 32 | # CONFIG_CGROUP_CPUACCT is not set | ||
| 33 | # CONFIG_RESOURCE_COUNTERS is not set | ||
| 32 | CONFIG_SYSFS_DEPRECATED=y | 34 | CONFIG_SYSFS_DEPRECATED=y |
| 35 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 36 | CONFIG_PROC_PID_CPUSET=y | ||
| 33 | # CONFIG_RELAY is not set | 37 | # CONFIG_RELAY is not set |
| 38 | CONFIG_NAMESPACES=y | ||
| 39 | # CONFIG_UTS_NS is not set | ||
| 40 | # CONFIG_IPC_NS is not set | ||
| 41 | # CONFIG_USER_NS is not set | ||
| 42 | # CONFIG_PID_NS is not set | ||
| 34 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 35 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 36 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 45 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 37 | CONFIG_SYSCTL=y | 46 | CONFIG_SYSCTL=y |
| 38 | # CONFIG_EMBEDDED is not set | 47 | # CONFIG_EMBEDDED is not set |
| 39 | CONFIG_SYSCTL_SYSCALL=y | 48 | CONFIG_SYSCTL_SYSCALL=y |
| 49 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 40 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 41 | CONFIG_KALLSYMS_ALL=y | 51 | CONFIG_KALLSYMS_ALL=y |
| 42 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -44,6 +54,7 @@ CONFIG_HOTPLUG=y | |||
| 44 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 45 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 46 | CONFIG_ELF_CORE=y | 56 | CONFIG_ELF_CORE=y |
| 57 | CONFIG_COMPAT_BRK=y | ||
| 47 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 48 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 49 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| @@ -53,12 +64,30 @@ CONFIG_TIMERFD=y | |||
| 53 | CONFIG_EVENTFD=y | 64 | CONFIG_EVENTFD=y |
| 54 | CONFIG_SHMEM=y | 65 | CONFIG_SHMEM=y |
| 55 | CONFIG_VM_EVENT_COUNTERS=y | 66 | CONFIG_VM_EVENT_COUNTERS=y |
| 67 | CONFIG_SLUB_DEBUG=y | ||
| 68 | # CONFIG_SLAB is not set | ||
| 56 | CONFIG_SLUB=y | 69 | CONFIG_SLUB=y |
| 57 | # CONFIG_SLOB is not set | 70 | # CONFIG_SLOB is not set |
| 71 | # CONFIG_PROFILING is not set | ||
| 72 | # CONFIG_MARKERS is not set | ||
| 73 | CONFIG_HAVE_OPROFILE=y | ||
| 74 | # CONFIG_KPROBES is not set | ||
| 75 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 76 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 77 | CONFIG_HAVE_KPROBES=y | ||
| 78 | CONFIG_HAVE_KRETPROBES=y | ||
| 79 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 80 | CONFIG_HAVE_DMA_ATTRS=y | ||
| 81 | CONFIG_USE_GENERIC_SMP_HELPERS=y | ||
| 82 | # CONFIG_HAVE_CLK is not set | ||
| 83 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 84 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 85 | CONFIG_SLABINFO=y | ||
| 58 | CONFIG_RT_MUTEXES=y | 86 | CONFIG_RT_MUTEXES=y |
| 59 | # CONFIG_TINY_SHMEM is not set | 87 | # CONFIG_TINY_SHMEM is not set |
| 60 | CONFIG_BASE_SMALL=0 | 88 | CONFIG_BASE_SMALL=0 |
| 61 | CONFIG_MODULES=y | 89 | CONFIG_MODULES=y |
| 90 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 62 | CONFIG_MODULE_UNLOAD=y | 91 | CONFIG_MODULE_UNLOAD=y |
| 63 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 92 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 64 | CONFIG_MODVERSIONS=y | 93 | CONFIG_MODVERSIONS=y |
| @@ -68,6 +97,8 @@ CONFIG_STOP_MACHINE=y | |||
| 68 | CONFIG_BLOCK=y | 97 | CONFIG_BLOCK=y |
| 69 | # CONFIG_BLK_DEV_IO_TRACE is not set | 98 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 70 | # CONFIG_BLK_DEV_BSG is not set | 99 | # CONFIG_BLK_DEV_BSG is not set |
| 100 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 101 | CONFIG_BLOCK_COMPAT=y | ||
| 71 | 102 | ||
| 72 | # | 103 | # |
| 73 | # IO Schedulers | 104 | # IO Schedulers |
| @@ -81,6 +112,7 @@ CONFIG_DEFAULT_AS=y | |||
| 81 | # CONFIG_DEFAULT_CFQ is not set | 112 | # CONFIG_DEFAULT_CFQ is not set |
| 82 | # CONFIG_DEFAULT_NOOP is not set | 113 | # CONFIG_DEFAULT_NOOP is not set |
| 83 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 114 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 115 | CONFIG_CLASSIC_RCU=y | ||
| 84 | 116 | ||
| 85 | # | 117 | # |
| 86 | # Processor type and features | 118 | # Processor type and features |
| @@ -91,22 +123,28 @@ CONFIG_ZONE_DMA=y | |||
| 91 | CONFIG_QUICKLIST=y | 123 | CONFIG_QUICKLIST=y |
| 92 | CONFIG_MMU=y | 124 | CONFIG_MMU=y |
| 93 | CONFIG_SWIOTLB=y | 125 | CONFIG_SWIOTLB=y |
| 126 | CONFIG_IOMMU_HELPER=y | ||
| 94 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y | 127 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y |
| 95 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | 128 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set |
| 96 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 129 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 130 | CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y | ||
| 97 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 131 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 98 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 132 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 99 | CONFIG_GENERIC_TIME=y | 133 | CONFIG_GENERIC_TIME=y |
| 134 | CONFIG_GENERIC_TIME_VSYSCALL=y | ||
| 135 | CONFIG_HAVE_SETUP_PER_CPU_AREA=y | ||
| 100 | CONFIG_DMI=y | 136 | CONFIG_DMI=y |
| 101 | CONFIG_EFI=y | 137 | CONFIG_EFI=y |
| 102 | CONFIG_GENERIC_IOMAP=y | 138 | CONFIG_GENERIC_IOMAP=y |
| 103 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | 139 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y |
| 140 | CONFIG_IA64_UNCACHED_ALLOCATOR=y | ||
| 104 | CONFIG_AUDIT_ARCH=y | 141 | CONFIG_AUDIT_ARCH=y |
| 105 | CONFIG_IA64_GENERIC=y | 142 | CONFIG_IA64_GENERIC=y |
| 106 | # CONFIG_IA64_DIG is not set | 143 | # CONFIG_IA64_DIG is not set |
| 107 | # CONFIG_IA64_HP_ZX1 is not set | 144 | # CONFIG_IA64_HP_ZX1 is not set |
| 108 | # CONFIG_IA64_HP_ZX1_SWIOTLB is not set | 145 | # CONFIG_IA64_HP_ZX1_SWIOTLB is not set |
| 109 | # CONFIG_IA64_SGI_SN2 is not set | 146 | # CONFIG_IA64_SGI_SN2 is not set |
| 147 | # CONFIG_IA64_SGI_UV is not set | ||
| 110 | # CONFIG_IA64_HP_SIM is not set | 148 | # CONFIG_IA64_HP_SIM is not set |
| 111 | # CONFIG_ITANIUM is not set | 149 | # CONFIG_ITANIUM is not set |
| 112 | CONFIG_MCKINLEY=y | 150 | CONFIG_MCKINLEY=y |
| @@ -116,22 +154,26 @@ CONFIG_MCKINLEY=y | |||
| 116 | CONFIG_IA64_PAGE_SIZE_64KB=y | 154 | CONFIG_IA64_PAGE_SIZE_64KB=y |
| 117 | CONFIG_PGTABLE_3=y | 155 | CONFIG_PGTABLE_3=y |
| 118 | # CONFIG_PGTABLE_4 is not set | 156 | # CONFIG_PGTABLE_4 is not set |
| 157 | CONFIG_HZ=250 | ||
| 119 | # CONFIG_HZ_100 is not set | 158 | # CONFIG_HZ_100 is not set |
| 120 | CONFIG_HZ_250=y | 159 | CONFIG_HZ_250=y |
| 121 | # CONFIG_HZ_300 is not set | 160 | # CONFIG_HZ_300 is not set |
| 122 | # CONFIG_HZ_1000 is not set | 161 | # CONFIG_HZ_1000 is not set |
| 123 | CONFIG_HZ=250 | 162 | # CONFIG_SCHED_HRTICK is not set |
| 124 | CONFIG_IA64_L1_CACHE_SHIFT=7 | 163 | CONFIG_IA64_L1_CACHE_SHIFT=7 |
| 125 | CONFIG_IA64_CYCLONE=y | 164 | CONFIG_IA64_CYCLONE=y |
| 126 | CONFIG_IOSAPIC=y | 165 | CONFIG_IOSAPIC=y |
| 127 | # CONFIG_IA64_SGI_SN_XP is not set | ||
| 128 | CONFIG_FORCE_MAX_ZONEORDER=17 | 166 | CONFIG_FORCE_MAX_ZONEORDER=17 |
| 167 | # CONFIG_VIRT_CPU_ACCOUNTING is not set | ||
| 129 | CONFIG_SMP=y | 168 | CONFIG_SMP=y |
| 130 | CONFIG_NR_CPUS=512 | 169 | CONFIG_NR_CPUS=4096 |
| 131 | CONFIG_HOTPLUG_CPU=y | 170 | CONFIG_HOTPLUG_CPU=y |
| 132 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y | 171 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y |
| 172 | CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y | ||
| 133 | # CONFIG_SCHED_SMT is not set | 173 | # CONFIG_SCHED_SMT is not set |
| 134 | # CONFIG_PERMIT_BSP_REMOVE is not set | 174 | # CONFIG_PERMIT_BSP_REMOVE is not set |
| 175 | CONFIG_PREEMPT_NONE=y | ||
| 176 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 135 | # CONFIG_PREEMPT is not set | 177 | # CONFIG_PREEMPT is not set |
| 136 | CONFIG_SELECT_MEMORY_MODEL=y | 178 | CONFIG_SELECT_MEMORY_MODEL=y |
| 137 | # CONFIG_FLATMEM_MANUAL is not set | 179 | # CONFIG_FLATMEM_MANUAL is not set |
| @@ -141,6 +183,8 @@ CONFIG_DISCONTIGMEM=y | |||
| 141 | CONFIG_FLAT_NODE_MEM_MAP=y | 183 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 142 | CONFIG_NEED_MULTIPLE_NODES=y | 184 | CONFIG_NEED_MULTIPLE_NODES=y |
| 143 | # CONFIG_SPARSEMEM_STATIC is not set | 185 | # CONFIG_SPARSEMEM_STATIC is not set |
| 186 | CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y | ||
| 187 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 144 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 188 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 145 | CONFIG_MIGRATION=y | 189 | CONFIG_MIGRATION=y |
| 146 | CONFIG_RESOURCES_64BIT=y | 190 | CONFIG_RESOURCES_64BIT=y |
| @@ -148,6 +192,7 @@ CONFIG_ZONE_DMA_FLAG=1 | |||
| 148 | CONFIG_BOUNCE=y | 192 | CONFIG_BOUNCE=y |
| 149 | CONFIG_NR_QUICK=1 | 193 | CONFIG_NR_QUICK=1 |
| 150 | CONFIG_VIRT_TO_BUS=y | 194 | CONFIG_VIRT_TO_BUS=y |
| 195 | CONFIG_MMU_NOTIFIER=y | ||
| 151 | CONFIG_ARCH_SELECT_MEMORY_MODEL=y | 196 | CONFIG_ARCH_SELECT_MEMORY_MODEL=y |
| 152 | CONFIG_ARCH_DISCONTIGMEM_ENABLE=y | 197 | CONFIG_ARCH_DISCONTIGMEM_ENABLE=y |
| 153 | CONFIG_ARCH_FLATMEM_ENABLE=y | 198 | CONFIG_ARCH_FLATMEM_ENABLE=y |
| @@ -162,12 +207,14 @@ CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y | |||
| 162 | CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y | 207 | CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y |
| 163 | CONFIG_IA32_SUPPORT=y | 208 | CONFIG_IA32_SUPPORT=y |
| 164 | CONFIG_COMPAT=y | 209 | CONFIG_COMPAT=y |
| 210 | CONFIG_COMPAT_FOR_U64_ALIGNMENT=y | ||
| 165 | CONFIG_IA64_MCA_RECOVERY=y | 211 | CONFIG_IA64_MCA_RECOVERY=y |
| 166 | CONFIG_PERFMON=y | 212 | CONFIG_PERFMON=y |
| 167 | CONFIG_IA64_PALINFO=y | 213 | CONFIG_IA64_PALINFO=y |
| 168 | # CONFIG_IA64_MC_ERR_INJECT is not set | 214 | # CONFIG_IA64_MC_ERR_INJECT is not set |
| 169 | CONFIG_SGI_SN=y | 215 | CONFIG_SGI_SN=y |
| 170 | # CONFIG_IA64_ESI is not set | 216 | # CONFIG_IA64_ESI is not set |
| 217 | # CONFIG_IA64_HP_AML_NFW is not set | ||
| 171 | 218 | ||
| 172 | # | 219 | # |
| 173 | # SN Devices | 220 | # SN Devices |
| @@ -179,6 +226,7 @@ CONFIG_CRASH_DUMP=y | |||
| 179 | # | 226 | # |
| 180 | # Firmware Drivers | 227 | # Firmware Drivers |
| 181 | # | 228 | # |
| 229 | # CONFIG_FIRMWARE_MEMMAP is not set | ||
| 182 | CONFIG_EFI_VARS=y | 230 | CONFIG_EFI_VARS=y |
| 183 | CONFIG_EFI_PCDP=y | 231 | CONFIG_EFI_PCDP=y |
| 184 | CONFIG_DMIID=y | 232 | CONFIG_DMIID=y |
| @@ -189,24 +237,25 @@ CONFIG_BINFMT_MISC=m | |||
| 189 | # Power management and ACPI | 237 | # Power management and ACPI |
| 190 | # | 238 | # |
| 191 | CONFIG_PM=y | 239 | CONFIG_PM=y |
| 192 | CONFIG_PM_LEGACY=y | ||
| 193 | # CONFIG_PM_DEBUG is not set | 240 | # CONFIG_PM_DEBUG is not set |
| 194 | |||
| 195 | # | ||
| 196 | # ACPI (Advanced Configuration and Power Interface) Support | ||
| 197 | # | ||
| 198 | CONFIG_ACPI=y | 241 | CONFIG_ACPI=y |
| 199 | CONFIG_ACPI_PROCFS=y | 242 | CONFIG_ACPI_PROCFS=y |
| 243 | CONFIG_ACPI_PROCFS_POWER=y | ||
| 244 | CONFIG_ACPI_SYSFS_POWER=y | ||
| 245 | CONFIG_ACPI_PROC_EVENT=y | ||
| 200 | CONFIG_ACPI_BUTTON=m | 246 | CONFIG_ACPI_BUTTON=m |
| 201 | CONFIG_ACPI_FAN=m | 247 | CONFIG_ACPI_FAN=m |
| 202 | # CONFIG_ACPI_DOCK is not set | 248 | CONFIG_ACPI_DOCK=y |
| 249 | # CONFIG_ACPI_BAY is not set | ||
| 203 | CONFIG_ACPI_PROCESSOR=m | 250 | CONFIG_ACPI_PROCESSOR=m |
| 204 | CONFIG_ACPI_HOTPLUG_CPU=y | 251 | CONFIG_ACPI_HOTPLUG_CPU=y |
| 205 | CONFIG_ACPI_THERMAL=m | 252 | CONFIG_ACPI_THERMAL=m |
| 206 | CONFIG_ACPI_NUMA=y | 253 | CONFIG_ACPI_NUMA=y |
| 254 | # CONFIG_ACPI_CUSTOM_DSDT is not set | ||
| 207 | CONFIG_ACPI_BLACKLIST_YEAR=0 | 255 | CONFIG_ACPI_BLACKLIST_YEAR=0 |
| 208 | # CONFIG_ACPI_DEBUG is not set | 256 | # CONFIG_ACPI_DEBUG is not set |
| 209 | CONFIG_ACPI_EC=y | 257 | CONFIG_ACPI_EC=y |
| 258 | # CONFIG_ACPI_PCI_SLOT is not set | ||
| 210 | CONFIG_ACPI_POWER=y | 259 | CONFIG_ACPI_POWER=y |
| 211 | CONFIG_ACPI_SYSTEM=y | 260 | CONFIG_ACPI_SYSTEM=y |
| 212 | CONFIG_ACPI_CONTAINER=m | 261 | CONFIG_ACPI_CONTAINER=m |
| @@ -225,6 +274,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 225 | # CONFIG_PCIEPORTBUS is not set | 274 | # CONFIG_PCIEPORTBUS is not set |
| 226 | CONFIG_ARCH_SUPPORTS_MSI=y | 275 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 227 | # CONFIG_PCI_MSI is not set | 276 | # CONFIG_PCI_MSI is not set |
| 277 | CONFIG_PCI_LEGACY=y | ||
| 228 | # CONFIG_PCI_DEBUG is not set | 278 | # CONFIG_PCI_DEBUG is not set |
| 229 | CONFIG_HOTPLUG_PCI=m | 279 | CONFIG_HOTPLUG_PCI=m |
| 230 | # CONFIG_HOTPLUG_PCI_FAKE is not set | 280 | # CONFIG_HOTPLUG_PCI_FAKE is not set |
| @@ -233,15 +283,7 @@ CONFIG_HOTPLUG_PCI_ACPI=m | |||
| 233 | # CONFIG_HOTPLUG_PCI_CPCI is not set | 283 | # CONFIG_HOTPLUG_PCI_CPCI is not set |
| 234 | # CONFIG_HOTPLUG_PCI_SHPC is not set | 284 | # CONFIG_HOTPLUG_PCI_SHPC is not set |
| 235 | # CONFIG_HOTPLUG_PCI_SGI is not set | 285 | # CONFIG_HOTPLUG_PCI_SGI is not set |
| 236 | |||
| 237 | # | ||
| 238 | # PCCARD (PCMCIA/CardBus) support | ||
| 239 | # | ||
| 240 | # CONFIG_PCCARD is not set | 286 | # CONFIG_PCCARD is not set |
| 241 | |||
| 242 | # | ||
| 243 | # Networking | ||
| 244 | # | ||
| 245 | CONFIG_NET=y | 287 | CONFIG_NET=y |
| 246 | 288 | ||
| 247 | # | 289 | # |
| @@ -254,6 +296,7 @@ CONFIG_XFRM=y | |||
| 254 | # CONFIG_XFRM_USER is not set | 296 | # CONFIG_XFRM_USER is not set |
| 255 | # CONFIG_XFRM_SUB_POLICY is not set | 297 | # CONFIG_XFRM_SUB_POLICY is not set |
| 256 | # CONFIG_XFRM_MIGRATE is not set | 298 | # CONFIG_XFRM_MIGRATE is not set |
| 299 | # CONFIG_XFRM_STATISTICS is not set | ||
| 257 | # CONFIG_NET_KEY is not set | 300 | # CONFIG_NET_KEY is not set |
| 258 | CONFIG_INET=y | 301 | CONFIG_INET=y |
| 259 | CONFIG_IP_MULTICAST=y | 302 | CONFIG_IP_MULTICAST=y |
| @@ -273,6 +316,7 @@ CONFIG_SYN_COOKIES=y | |||
| 273 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 316 | CONFIG_INET_XFRM_MODE_TRANSPORT=y |
| 274 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 317 | CONFIG_INET_XFRM_MODE_TUNNEL=y |
| 275 | CONFIG_INET_XFRM_MODE_BEET=y | 318 | CONFIG_INET_XFRM_MODE_BEET=y |
| 319 | CONFIG_INET_LRO=m | ||
| 276 | CONFIG_INET_DIAG=y | 320 | CONFIG_INET_DIAG=y |
| 277 | CONFIG_INET_TCP_DIAG=y | 321 | CONFIG_INET_TCP_DIAG=y |
| 278 | # CONFIG_TCP_CONG_ADVANCED is not set | 322 | # CONFIG_TCP_CONG_ADVANCED is not set |
| @@ -280,8 +324,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 280 | CONFIG_DEFAULT_TCP_CONG="cubic" | 324 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 281 | # CONFIG_TCP_MD5SIG is not set | 325 | # CONFIG_TCP_MD5SIG is not set |
| 282 | # CONFIG_IPV6 is not set | 326 | # CONFIG_IPV6 is not set |
| 283 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 284 | # CONFIG_INET6_TUNNEL is not set | ||
| 285 | # CONFIG_NETWORK_SECMARK is not set | 327 | # CONFIG_NETWORK_SECMARK is not set |
| 286 | # CONFIG_NETFILTER is not set | 328 | # CONFIG_NETFILTER is not set |
| 287 | # CONFIG_IP_DCCP is not set | 329 | # CONFIG_IP_DCCP is not set |
| @@ -298,10 +340,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 298 | # CONFIG_LAPB is not set | 340 | # CONFIG_LAPB is not set |
| 299 | # CONFIG_ECONET is not set | 341 | # CONFIG_ECONET is not set |
| 300 | # CONFIG_WAN_ROUTER is not set | 342 | # CONFIG_WAN_ROUTER is not set |
| 301 | |||
| 302 | # | ||
| 303 | # QoS and/or fair queueing | ||
| 304 | # | ||
| 305 | # CONFIG_NET_SCHED is not set | 343 | # CONFIG_NET_SCHED is not set |
| 306 | 344 | ||
| 307 | # | 345 | # |
| @@ -309,6 +347,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 309 | # | 347 | # |
| 310 | # CONFIG_NET_PKTGEN is not set | 348 | # CONFIG_NET_PKTGEN is not set |
| 311 | # CONFIG_HAMRADIO is not set | 349 | # CONFIG_HAMRADIO is not set |
| 350 | # CONFIG_CAN is not set | ||
| 312 | # CONFIG_IRDA is not set | 351 | # CONFIG_IRDA is not set |
| 313 | # CONFIG_BT is not set | 352 | # CONFIG_BT is not set |
| 314 | # CONFIG_AF_RXRPC is not set | 353 | # CONFIG_AF_RXRPC is not set |
| @@ -330,13 +369,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 330 | # | 369 | # |
| 331 | # Generic Driver Options | 370 | # Generic Driver Options |
| 332 | # | 371 | # |
| 372 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 333 | CONFIG_STANDALONE=y | 373 | CONFIG_STANDALONE=y |
| 334 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 374 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 335 | CONFIG_FW_LOADER=m | 375 | CONFIG_FW_LOADER=y |
| 376 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 377 | CONFIG_EXTRA_FIRMWARE="" | ||
| 336 | # CONFIG_DEBUG_DRIVER is not set | 378 | # CONFIG_DEBUG_DRIVER is not set |
| 337 | # CONFIG_DEBUG_DEVRES is not set | 379 | # CONFIG_DEBUG_DEVRES is not set |
| 338 | # CONFIG_SYS_HYPERVISOR is not set | 380 | # CONFIG_SYS_HYPERVISOR is not set |
| 339 | # CONFIG_CONNECTOR is not set | 381 | CONFIG_CONNECTOR=y |
| 382 | CONFIG_PROC_EVENTS=y | ||
| 340 | # CONFIG_MTD is not set | 383 | # CONFIG_MTD is not set |
| 341 | # CONFIG_PARPORT is not set | 384 | # CONFIG_PARPORT is not set |
| 342 | CONFIG_PNP=y | 385 | CONFIG_PNP=y |
| @@ -360,25 +403,35 @@ CONFIG_BLK_DEV_NBD=m | |||
| 360 | CONFIG_BLK_DEV_RAM=y | 403 | CONFIG_BLK_DEV_RAM=y |
| 361 | CONFIG_BLK_DEV_RAM_COUNT=16 | 404 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 362 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 405 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 363 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 406 | # CONFIG_BLK_DEV_XIP is not set |
| 364 | # CONFIG_CDROM_PKTCDVD is not set | 407 | # CONFIG_CDROM_PKTCDVD is not set |
| 365 | # CONFIG_ATA_OVER_ETH is not set | 408 | # CONFIG_ATA_OVER_ETH is not set |
| 409 | # CONFIG_BLK_DEV_HD is not set | ||
| 366 | CONFIG_MISC_DEVICES=y | 410 | CONFIG_MISC_DEVICES=y |
| 367 | # CONFIG_PHANTOM is not set | 411 | # CONFIG_PHANTOM is not set |
| 368 | # CONFIG_EEPROM_93CX6 is not set | 412 | # CONFIG_EEPROM_93CX6 is not set |
| 369 | CONFIG_SGI_IOC4=y | 413 | CONFIG_SGI_IOC4=y |
| 370 | # CONFIG_TIFM_CORE is not set | 414 | # CONFIG_TIFM_CORE is not set |
| 415 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 416 | CONFIG_SGI_XP=m | ||
| 417 | # CONFIG_HP_ILO is not set | ||
| 418 | CONFIG_SGI_GRU=m | ||
| 419 | # CONFIG_SGI_GRU_DEBUG is not set | ||
| 420 | CONFIG_HAVE_IDE=y | ||
| 371 | CONFIG_IDE=y | 421 | CONFIG_IDE=y |
| 372 | CONFIG_IDE_MAX_HWIFS=4 | 422 | CONFIG_IDE_MAX_HWIFS=4 |
| 373 | CONFIG_BLK_DEV_IDE=y | 423 | CONFIG_BLK_DEV_IDE=y |
| 374 | 424 | ||
| 375 | # | 425 | # |
| 376 | # Please see Documentation/ide.txt for help/info on IDE drives | 426 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 377 | # | 427 | # |
| 428 | CONFIG_IDE_TIMINGS=y | ||
| 429 | CONFIG_IDE_ATAPI=y | ||
| 378 | # CONFIG_BLK_DEV_IDE_SATA is not set | 430 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 379 | CONFIG_BLK_DEV_IDEDISK=y | 431 | CONFIG_BLK_DEV_IDEDISK=y |
| 380 | # CONFIG_IDEDISK_MULTI_MODE is not set | 432 | # CONFIG_IDEDISK_MULTI_MODE is not set |
| 381 | CONFIG_BLK_DEV_IDECD=y | 433 | CONFIG_BLK_DEV_IDECD=y |
| 434 | CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y | ||
| 382 | # CONFIG_BLK_DEV_IDETAPE is not set | 435 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 383 | CONFIG_BLK_DEV_IDEFLOPPY=y | 436 | CONFIG_BLK_DEV_IDEFLOPPY=y |
| 384 | CONFIG_BLK_DEV_IDESCSI=m | 437 | CONFIG_BLK_DEV_IDESCSI=m |
| @@ -390,25 +443,26 @@ CONFIG_IDE_PROC_FS=y | |||
| 390 | # IDE chipset support/bugfixes | 443 | # IDE chipset support/bugfixes |
| 391 | # | 444 | # |
| 392 | # CONFIG_IDE_GENERIC is not set | 445 | # CONFIG_IDE_GENERIC is not set |
| 446 | # CONFIG_BLK_DEV_PLATFORM is not set | ||
| 393 | # CONFIG_BLK_DEV_IDEPNP is not set | 447 | # CONFIG_BLK_DEV_IDEPNP is not set |
| 448 | CONFIG_BLK_DEV_IDEDMA_SFF=y | ||
| 449 | |||
| 450 | # | ||
| 451 | # PCI IDE chipsets support | ||
| 452 | # | ||
| 394 | CONFIG_BLK_DEV_IDEPCI=y | 453 | CONFIG_BLK_DEV_IDEPCI=y |
| 395 | CONFIG_IDEPCI_SHARE_IRQ=y | ||
| 396 | CONFIG_IDEPCI_PCIBUS_ORDER=y | 454 | CONFIG_IDEPCI_PCIBUS_ORDER=y |
| 397 | # CONFIG_BLK_DEV_OFFBOARD is not set | 455 | # CONFIG_BLK_DEV_OFFBOARD is not set |
| 398 | CONFIG_BLK_DEV_GENERIC=y | 456 | CONFIG_BLK_DEV_GENERIC=y |
| 399 | # CONFIG_BLK_DEV_OPTI621 is not set | 457 | # CONFIG_BLK_DEV_OPTI621 is not set |
| 400 | CONFIG_BLK_DEV_IDEDMA_PCI=y | 458 | CONFIG_BLK_DEV_IDEDMA_PCI=y |
| 401 | # CONFIG_BLK_DEV_IDEDMA_FORCED is not set | ||
| 402 | # CONFIG_IDEDMA_ONLYDISK is not set | ||
| 403 | # CONFIG_BLK_DEV_AEC62XX is not set | 459 | # CONFIG_BLK_DEV_AEC62XX is not set |
| 404 | # CONFIG_BLK_DEV_ALI15X3 is not set | 460 | # CONFIG_BLK_DEV_ALI15X3 is not set |
| 405 | # CONFIG_BLK_DEV_AMD74XX is not set | 461 | # CONFIG_BLK_DEV_AMD74XX is not set |
| 406 | CONFIG_BLK_DEV_CMD64X=y | 462 | CONFIG_BLK_DEV_CMD64X=y |
| 407 | # CONFIG_BLK_DEV_TRIFLEX is not set | 463 | # CONFIG_BLK_DEV_TRIFLEX is not set |
| 408 | # CONFIG_BLK_DEV_CY82C693 is not set | ||
| 409 | # CONFIG_BLK_DEV_CS5520 is not set | 464 | # CONFIG_BLK_DEV_CS5520 is not set |
| 410 | # CONFIG_BLK_DEV_CS5530 is not set | 465 | # CONFIG_BLK_DEV_CS5530 is not set |
| 411 | # CONFIG_BLK_DEV_HPT34X is not set | ||
| 412 | # CONFIG_BLK_DEV_HPT366 is not set | 466 | # CONFIG_BLK_DEV_HPT366 is not set |
| 413 | # CONFIG_BLK_DEV_JMICRON is not set | 467 | # CONFIG_BLK_DEV_JMICRON is not set |
| 414 | # CONFIG_BLK_DEV_SC1200 is not set | 468 | # CONFIG_BLK_DEV_SC1200 is not set |
| @@ -425,10 +479,7 @@ CONFIG_BLK_DEV_SGIIOC4=y | |||
| 425 | # CONFIG_BLK_DEV_TRM290 is not set | 479 | # CONFIG_BLK_DEV_TRM290 is not set |
| 426 | # CONFIG_BLK_DEV_VIA82CXXX is not set | 480 | # CONFIG_BLK_DEV_VIA82CXXX is not set |
| 427 | # CONFIG_BLK_DEV_TC86C001 is not set | 481 | # CONFIG_BLK_DEV_TC86C001 is not set |
| 428 | # CONFIG_IDE_ARM is not set | ||
| 429 | CONFIG_BLK_DEV_IDEDMA=y | 482 | CONFIG_BLK_DEV_IDEDMA=y |
| 430 | # CONFIG_IDEDMA_IVB is not set | ||
| 431 | # CONFIG_BLK_DEV_HD is not set | ||
| 432 | 483 | ||
| 433 | # | 484 | # |
| 434 | # SCSI device support | 485 | # SCSI device support |
| @@ -468,10 +519,8 @@ CONFIG_SCSI_FC_ATTRS=y | |||
| 468 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 519 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 469 | CONFIG_SCSI_SAS_ATTRS=y | 520 | CONFIG_SCSI_SAS_ATTRS=y |
| 470 | # CONFIG_SCSI_SAS_LIBSAS is not set | 521 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 471 | 522 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 472 | # | 523 | CONFIG_SCSI_LOWLEVEL=y |
| 473 | # SCSI low-level drivers | ||
| 474 | # | ||
| 475 | # CONFIG_ISCSI_TCP is not set | 524 | # CONFIG_ISCSI_TCP is not set |
| 476 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 525 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 477 | # CONFIG_SCSI_3W_9XXX is not set | 526 | # CONFIG_SCSI_3W_9XXX is not set |
| @@ -481,6 +530,8 @@ CONFIG_SCSI_SAS_ATTRS=y | |||
| 481 | # CONFIG_SCSI_AIC7XXX_OLD is not set | 530 | # CONFIG_SCSI_AIC7XXX_OLD is not set |
| 482 | # CONFIG_SCSI_AIC79XX is not set | 531 | # CONFIG_SCSI_AIC79XX is not set |
| 483 | # CONFIG_SCSI_AIC94XX is not set | 532 | # CONFIG_SCSI_AIC94XX is not set |
| 533 | # CONFIG_SCSI_DPT_I2O is not set | ||
| 534 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 484 | # CONFIG_SCSI_ARCMSR is not set | 535 | # CONFIG_SCSI_ARCMSR is not set |
| 485 | # CONFIG_MEGARAID_NEWGEN is not set | 536 | # CONFIG_MEGARAID_NEWGEN is not set |
| 486 | # CONFIG_MEGARAID_LEGACY is not set | 537 | # CONFIG_MEGARAID_LEGACY is not set |
| @@ -491,12 +542,14 @@ CONFIG_SCSI_SAS_ATTRS=y | |||
| 491 | # CONFIG_SCSI_IPS is not set | 542 | # CONFIG_SCSI_IPS is not set |
| 492 | # CONFIG_SCSI_INITIO is not set | 543 | # CONFIG_SCSI_INITIO is not set |
| 493 | # CONFIG_SCSI_INIA100 is not set | 544 | # CONFIG_SCSI_INIA100 is not set |
| 545 | # CONFIG_SCSI_MVSAS is not set | ||
| 494 | # CONFIG_SCSI_STEX is not set | 546 | # CONFIG_SCSI_STEX is not set |
| 495 | CONFIG_SCSI_SYM53C8XX_2=y | 547 | CONFIG_SCSI_SYM53C8XX_2=y |
| 496 | CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 | 548 | CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 |
| 497 | CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 | 549 | CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 |
| 498 | CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 | 550 | CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 |
| 499 | CONFIG_SCSI_SYM53C8XX_MMIO=y | 551 | CONFIG_SCSI_SYM53C8XX_MMIO=y |
| 552 | # CONFIG_SCSI_IPR is not set | ||
| 500 | CONFIG_SCSI_QLOGIC_1280=y | 553 | CONFIG_SCSI_QLOGIC_1280=y |
| 501 | # CONFIG_SCSI_QLA_FC is not set | 554 | # CONFIG_SCSI_QLA_FC is not set |
| 502 | # CONFIG_SCSI_QLA_ISCSI is not set | 555 | # CONFIG_SCSI_QLA_ISCSI is not set |
| @@ -505,7 +558,68 @@ CONFIG_SCSI_QLOGIC_1280=y | |||
| 505 | # CONFIG_SCSI_DC390T is not set | 558 | # CONFIG_SCSI_DC390T is not set |
| 506 | # CONFIG_SCSI_DEBUG is not set | 559 | # CONFIG_SCSI_DEBUG is not set |
| 507 | # CONFIG_SCSI_SRP is not set | 560 | # CONFIG_SCSI_SRP is not set |
| 508 | # CONFIG_ATA is not set | 561 | # CONFIG_SCSI_DH is not set |
| 562 | CONFIG_ATA=y | ||
| 563 | CONFIG_ATA_NONSTANDARD=y | ||
| 564 | CONFIG_ATA_ACPI=y | ||
| 565 | CONFIG_SATA_PMP=y | ||
| 566 | # CONFIG_SATA_AHCI is not set | ||
| 567 | # CONFIG_SATA_SIL24 is not set | ||
| 568 | CONFIG_ATA_SFF=y | ||
| 569 | # CONFIG_SATA_SVW is not set | ||
| 570 | CONFIG_ATA_PIIX=y | ||
| 571 | # CONFIG_SATA_MV is not set | ||
| 572 | # CONFIG_SATA_NV is not set | ||
| 573 | # CONFIG_PDC_ADMA is not set | ||
| 574 | # CONFIG_SATA_QSTOR is not set | ||
| 575 | # CONFIG_SATA_PROMISE is not set | ||
| 576 | # CONFIG_SATA_SX4 is not set | ||
| 577 | # CONFIG_SATA_SIL is not set | ||
| 578 | # CONFIG_SATA_SIS is not set | ||
| 579 | # CONFIG_SATA_ULI is not set | ||
| 580 | # CONFIG_SATA_VIA is not set | ||
| 581 | # CONFIG_SATA_VITESSE is not set | ||
| 582 | # CONFIG_SATA_INIC162X is not set | ||
| 583 | # CONFIG_PATA_ACPI is not set | ||
| 584 | # CONFIG_PATA_ALI is not set | ||
| 585 | # CONFIG_PATA_AMD is not set | ||
| 586 | # CONFIG_PATA_ARTOP is not set | ||
| 587 | # CONFIG_PATA_ATIIXP is not set | ||
| 588 | # CONFIG_PATA_CMD640_PCI is not set | ||
| 589 | # CONFIG_PATA_CMD64X is not set | ||
| 590 | # CONFIG_PATA_CS5520 is not set | ||
| 591 | # CONFIG_PATA_CS5530 is not set | ||
| 592 | # CONFIG_PATA_CYPRESS is not set | ||
| 593 | # CONFIG_PATA_EFAR is not set | ||
| 594 | # CONFIG_ATA_GENERIC is not set | ||
| 595 | # CONFIG_PATA_HPT366 is not set | ||
| 596 | # CONFIG_PATA_HPT37X is not set | ||
| 597 | # CONFIG_PATA_HPT3X2N is not set | ||
| 598 | # CONFIG_PATA_HPT3X3 is not set | ||
| 599 | # CONFIG_PATA_IT821X is not set | ||
| 600 | # CONFIG_PATA_IT8213 is not set | ||
| 601 | # CONFIG_PATA_JMICRON is not set | ||
| 602 | # CONFIG_PATA_TRIFLEX is not set | ||
| 603 | # CONFIG_PATA_MARVELL is not set | ||
| 604 | # CONFIG_PATA_MPIIX is not set | ||
| 605 | # CONFIG_PATA_OLDPIIX is not set | ||
| 606 | # CONFIG_PATA_NETCELL is not set | ||
| 607 | # CONFIG_PATA_NINJA32 is not set | ||
| 608 | # CONFIG_PATA_NS87410 is not set | ||
| 609 | # CONFIG_PATA_NS87415 is not set | ||
| 610 | # CONFIG_PATA_OPTI is not set | ||
| 611 | # CONFIG_PATA_OPTIDMA is not set | ||
| 612 | # CONFIG_PATA_PDC_OLD is not set | ||
| 613 | # CONFIG_PATA_RADISYS is not set | ||
| 614 | # CONFIG_PATA_RZ1000 is not set | ||
| 615 | # CONFIG_PATA_SC1200 is not set | ||
| 616 | # CONFIG_PATA_SERVERWORKS is not set | ||
| 617 | # CONFIG_PATA_PDC2027X is not set | ||
| 618 | # CONFIG_PATA_SIL680 is not set | ||
| 619 | # CONFIG_PATA_SIS is not set | ||
| 620 | # CONFIG_PATA_VIA is not set | ||
| 621 | # CONFIG_PATA_WINBOND is not set | ||
| 622 | # CONFIG_PATA_SCH is not set | ||
| 509 | CONFIG_MD=y | 623 | CONFIG_MD=y |
| 510 | CONFIG_BLK_DEV_MD=m | 624 | CONFIG_BLK_DEV_MD=m |
| 511 | CONFIG_MD_LINEAR=m | 625 | CONFIG_MD_LINEAR=m |
| @@ -522,36 +636,52 @@ CONFIG_DM_SNAPSHOT=m | |||
| 522 | CONFIG_DM_MIRROR=m | 636 | CONFIG_DM_MIRROR=m |
| 523 | CONFIG_DM_ZERO=m | 637 | CONFIG_DM_ZERO=m |
| 524 | CONFIG_DM_MULTIPATH=m | 638 | CONFIG_DM_MULTIPATH=m |
| 525 | # CONFIG_DM_MULTIPATH_EMC is not set | ||
| 526 | # CONFIG_DM_MULTIPATH_RDAC is not set | ||
| 527 | # CONFIG_DM_DELAY is not set | 639 | # CONFIG_DM_DELAY is not set |
| 528 | 640 | # CONFIG_DM_UEVENT is not set | |
| 529 | # | ||
| 530 | # Fusion MPT device support | ||
| 531 | # | ||
| 532 | CONFIG_FUSION=y | 641 | CONFIG_FUSION=y |
| 533 | CONFIG_FUSION_SPI=y | 642 | CONFIG_FUSION_SPI=y |
| 534 | CONFIG_FUSION_FC=m | 643 | CONFIG_FUSION_FC=m |
| 535 | CONFIG_FUSION_SAS=y | 644 | CONFIG_FUSION_SAS=y |
| 536 | CONFIG_FUSION_MAX_SGE=128 | 645 | CONFIG_FUSION_MAX_SGE=128 |
| 537 | # CONFIG_FUSION_CTL is not set | 646 | # CONFIG_FUSION_CTL is not set |
| 647 | # CONFIG_FUSION_LOGGING is not set | ||
| 538 | 648 | ||
| 539 | # | 649 | # |
| 540 | # IEEE 1394 (FireWire) support | 650 | # IEEE 1394 (FireWire) support |
| 541 | # | 651 | # |
| 652 | |||
| 653 | # | ||
| 654 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 655 | # | ||
| 542 | # CONFIG_FIREWIRE is not set | 656 | # CONFIG_FIREWIRE is not set |
| 543 | # CONFIG_IEEE1394 is not set | 657 | # CONFIG_IEEE1394 is not set |
| 544 | # CONFIG_I2O is not set | 658 | # CONFIG_I2O is not set |
| 545 | CONFIG_NETDEVICES=y | 659 | CONFIG_NETDEVICES=y |
| 546 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 547 | CONFIG_DUMMY=m | 660 | CONFIG_DUMMY=m |
| 548 | # CONFIG_BONDING is not set | 661 | # CONFIG_BONDING is not set |
| 549 | # CONFIG_MACVLAN is not set | 662 | # CONFIG_MACVLAN is not set |
| 550 | # CONFIG_EQUALIZER is not set | 663 | # CONFIG_EQUALIZER is not set |
| 551 | # CONFIG_TUN is not set | 664 | # CONFIG_TUN is not set |
| 665 | # CONFIG_VETH is not set | ||
| 552 | # CONFIG_NET_SB1000 is not set | 666 | # CONFIG_NET_SB1000 is not set |
| 553 | # CONFIG_ARCNET is not set | 667 | # CONFIG_ARCNET is not set |
| 554 | # CONFIG_PHYLIB is not set | 668 | CONFIG_PHYLIB=y |
| 669 | |||
| 670 | # | ||
| 671 | # MII PHY device drivers | ||
| 672 | # | ||
| 673 | # CONFIG_MARVELL_PHY is not set | ||
| 674 | # CONFIG_DAVICOM_PHY is not set | ||
| 675 | # CONFIG_QSEMI_PHY is not set | ||
| 676 | # CONFIG_LXT_PHY is not set | ||
| 677 | # CONFIG_CICADA_PHY is not set | ||
| 678 | # CONFIG_VITESSE_PHY is not set | ||
| 679 | # CONFIG_SMSC_PHY is not set | ||
| 680 | # CONFIG_BROADCOM_PHY is not set | ||
| 681 | # CONFIG_ICPLUS_PHY is not set | ||
| 682 | # CONFIG_REALTEK_PHY is not set | ||
| 683 | # CONFIG_FIXED_PHY is not set | ||
| 684 | # CONFIG_MDIO_BITBANG is not set | ||
| 555 | CONFIG_NET_ETHERNET=y | 685 | CONFIG_NET_ETHERNET=y |
| 556 | CONFIG_MII=m | 686 | CONFIG_MII=m |
| 557 | # CONFIG_HAPPYMEAL is not set | 687 | # CONFIG_HAPPYMEAL is not set |
| @@ -569,13 +699,16 @@ CONFIG_TULIP=m | |||
| 569 | # CONFIG_DM9102 is not set | 699 | # CONFIG_DM9102 is not set |
| 570 | # CONFIG_ULI526X is not set | 700 | # CONFIG_ULI526X is not set |
| 571 | # CONFIG_HP100 is not set | 701 | # CONFIG_HP100 is not set |
| 702 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 703 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 704 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 705 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 572 | CONFIG_NET_PCI=y | 706 | CONFIG_NET_PCI=y |
| 573 | # CONFIG_PCNET32 is not set | 707 | # CONFIG_PCNET32 is not set |
| 574 | # CONFIG_AMD8111_ETH is not set | 708 | # CONFIG_AMD8111_ETH is not set |
| 575 | # CONFIG_ADAPTEC_STARFIRE is not set | 709 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 576 | # CONFIG_B44 is not set | 710 | # CONFIG_B44 is not set |
| 577 | # CONFIG_FORCEDETH is not set | 711 | # CONFIG_FORCEDETH is not set |
| 578 | # CONFIG_DGRS is not set | ||
| 579 | CONFIG_EEPRO100=m | 712 | CONFIG_EEPRO100=m |
| 580 | CONFIG_E100=m | 713 | CONFIG_E100=m |
| 581 | # CONFIG_FEALNX is not set | 714 | # CONFIG_FEALNX is not set |
| @@ -583,17 +716,22 @@ CONFIG_E100=m | |||
| 583 | # CONFIG_NE2K_PCI is not set | 716 | # CONFIG_NE2K_PCI is not set |
| 584 | # CONFIG_8139CP is not set | 717 | # CONFIG_8139CP is not set |
| 585 | # CONFIG_8139TOO is not set | 718 | # CONFIG_8139TOO is not set |
| 719 | # CONFIG_R6040 is not set | ||
| 586 | # CONFIG_SIS900 is not set | 720 | # CONFIG_SIS900 is not set |
| 587 | # CONFIG_EPIC100 is not set | 721 | # CONFIG_EPIC100 is not set |
| 588 | # CONFIG_SUNDANCE is not set | 722 | # CONFIG_SUNDANCE is not set |
| 723 | # CONFIG_TLAN is not set | ||
| 589 | # CONFIG_VIA_RHINE is not set | 724 | # CONFIG_VIA_RHINE is not set |
| 590 | # CONFIG_SC92031 is not set | 725 | # CONFIG_SC92031 is not set |
| 591 | CONFIG_NETDEV_1000=y | 726 | CONFIG_NETDEV_1000=y |
| 592 | # CONFIG_ACENIC is not set | 727 | # CONFIG_ACENIC is not set |
| 593 | # CONFIG_DL2K is not set | 728 | # CONFIG_DL2K is not set |
| 594 | CONFIG_E1000=y | 729 | CONFIG_E1000=y |
| 595 | # CONFIG_E1000_NAPI is not set | ||
| 596 | # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set | 730 | # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set |
| 731 | # CONFIG_E1000E is not set | ||
| 732 | # CONFIG_IP1000 is not set | ||
| 733 | CONFIG_IGB=y | ||
| 734 | # CONFIG_IGB_LRO is not set | ||
| 597 | # CONFIG_NS83820 is not set | 735 | # CONFIG_NS83820 is not set |
| 598 | # CONFIG_HAMACHI is not set | 736 | # CONFIG_HAMACHI is not set |
| 599 | # CONFIG_YELLOWFIN is not set | 737 | # CONFIG_YELLOWFIN is not set |
| @@ -606,14 +744,20 @@ CONFIG_TIGON3=y | |||
| 606 | # CONFIG_BNX2 is not set | 744 | # CONFIG_BNX2 is not set |
| 607 | # CONFIG_QLA3XXX is not set | 745 | # CONFIG_QLA3XXX is not set |
| 608 | # CONFIG_ATL1 is not set | 746 | # CONFIG_ATL1 is not set |
| 747 | # CONFIG_ATL1E is not set | ||
| 609 | CONFIG_NETDEV_10000=y | 748 | CONFIG_NETDEV_10000=y |
| 610 | # CONFIG_CHELSIO_T1 is not set | 749 | # CONFIG_CHELSIO_T1 is not set |
| 611 | # CONFIG_CHELSIO_T3 is not set | 750 | # CONFIG_CHELSIO_T3 is not set |
| 751 | # CONFIG_IXGBE is not set | ||
| 612 | # CONFIG_IXGB is not set | 752 | # CONFIG_IXGB is not set |
| 613 | # CONFIG_S2IO is not set | 753 | # CONFIG_S2IO is not set |
| 614 | # CONFIG_MYRI10GE is not set | 754 | # CONFIG_MYRI10GE is not set |
| 615 | # CONFIG_NETXEN_NIC is not set | 755 | # CONFIG_NETXEN_NIC is not set |
| 756 | # CONFIG_NIU is not set | ||
| 616 | # CONFIG_MLX4_CORE is not set | 757 | # CONFIG_MLX4_CORE is not set |
| 758 | # CONFIG_TEHUTI is not set | ||
| 759 | # CONFIG_BNX2X is not set | ||
| 760 | # CONFIG_SFC is not set | ||
| 617 | # CONFIG_TR is not set | 761 | # CONFIG_TR is not set |
| 618 | 762 | ||
| 619 | # | 763 | # |
| @@ -621,6 +765,7 @@ CONFIG_NETDEV_10000=y | |||
| 621 | # | 765 | # |
| 622 | # CONFIG_WLAN_PRE80211 is not set | 766 | # CONFIG_WLAN_PRE80211 is not set |
| 623 | # CONFIG_WLAN_80211 is not set | 767 | # CONFIG_WLAN_80211 is not set |
| 768 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 624 | 769 | ||
| 625 | # | 770 | # |
| 626 | # USB Network Adapters | 771 | # USB Network Adapters |
| @@ -629,7 +774,6 @@ CONFIG_NETDEV_10000=y | |||
| 629 | # CONFIG_USB_KAWETH is not set | 774 | # CONFIG_USB_KAWETH is not set |
| 630 | # CONFIG_USB_PEGASUS is not set | 775 | # CONFIG_USB_PEGASUS is not set |
| 631 | # CONFIG_USB_RTL8150 is not set | 776 | # CONFIG_USB_RTL8150 is not set |
| 632 | # CONFIG_USB_USBNET_MII is not set | ||
| 633 | # CONFIG_USB_USBNET is not set | 777 | # CONFIG_USB_USBNET is not set |
| 634 | # CONFIG_WAN is not set | 778 | # CONFIG_WAN is not set |
| 635 | # CONFIG_FDDI is not set | 779 | # CONFIG_FDDI is not set |
| @@ -637,8 +781,8 @@ CONFIG_NETDEV_10000=y | |||
| 637 | # CONFIG_PPP is not set | 781 | # CONFIG_PPP is not set |
| 638 | # CONFIG_SLIP is not set | 782 | # CONFIG_SLIP is not set |
| 639 | # CONFIG_NET_FC is not set | 783 | # CONFIG_NET_FC is not set |
| 640 | # CONFIG_SHAPER is not set | ||
| 641 | CONFIG_NETCONSOLE=y | 784 | CONFIG_NETCONSOLE=y |
| 785 | # CONFIG_NETCONSOLE_DYNAMIC is not set | ||
| 642 | CONFIG_NETPOLL=y | 786 | CONFIG_NETPOLL=y |
| 643 | # CONFIG_NETPOLL_TRAP is not set | 787 | # CONFIG_NETPOLL_TRAP is not set |
| 644 | CONFIG_NET_POLL_CONTROLLER=y | 788 | CONFIG_NET_POLL_CONTROLLER=y |
| @@ -660,7 +804,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 660 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 804 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 661 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 805 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 662 | # CONFIG_INPUT_JOYDEV is not set | 806 | # CONFIG_INPUT_JOYDEV is not set |
| 663 | # CONFIG_INPUT_TSDEV is not set | ||
| 664 | # CONFIG_INPUT_EVDEV is not set | 807 | # CONFIG_INPUT_EVDEV is not set |
| 665 | # CONFIG_INPUT_EVBUG is not set | 808 | # CONFIG_INPUT_EVBUG is not set |
| 666 | 809 | ||
| @@ -709,9 +852,11 @@ CONFIG_GAMEPORT=m | |||
| 709 | # Character devices | 852 | # Character devices |
| 710 | # | 853 | # |
| 711 | CONFIG_VT=y | 854 | CONFIG_VT=y |
| 855 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 712 | CONFIG_VT_CONSOLE=y | 856 | CONFIG_VT_CONSOLE=y |
| 713 | CONFIG_HW_CONSOLE=y | 857 | CONFIG_HW_CONSOLE=y |
| 714 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 858 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 859 | CONFIG_DEVKMEM=y | ||
| 715 | CONFIG_SERIAL_NONSTANDARD=y | 860 | CONFIG_SERIAL_NONSTANDARD=y |
| 716 | # CONFIG_COMPUTONE is not set | 861 | # CONFIG_COMPUTONE is not set |
| 717 | # CONFIG_ROCKETPORT is not set | 862 | # CONFIG_ROCKETPORT is not set |
| @@ -719,15 +864,16 @@ CONFIG_SERIAL_NONSTANDARD=y | |||
| 719 | # CONFIG_DIGIEPCA is not set | 864 | # CONFIG_DIGIEPCA is not set |
| 720 | # CONFIG_MOXA_INTELLIO is not set | 865 | # CONFIG_MOXA_INTELLIO is not set |
| 721 | # CONFIG_MOXA_SMARTIO is not set | 866 | # CONFIG_MOXA_SMARTIO is not set |
| 722 | # CONFIG_MOXA_SMARTIO_NEW is not set | ||
| 723 | # CONFIG_ISI is not set | 867 | # CONFIG_ISI is not set |
| 724 | # CONFIG_SYNCLINKMP is not set | 868 | # CONFIG_SYNCLINKMP is not set |
| 725 | # CONFIG_SYNCLINK_GT is not set | 869 | # CONFIG_SYNCLINK_GT is not set |
| 726 | # CONFIG_N_HDLC is not set | 870 | # CONFIG_N_HDLC is not set |
| 871 | # CONFIG_RISCOM8 is not set | ||
| 727 | # CONFIG_SPECIALIX is not set | 872 | # CONFIG_SPECIALIX is not set |
| 728 | # CONFIG_SX is not set | 873 | # CONFIG_SX is not set |
| 729 | # CONFIG_RIO is not set | 874 | # CONFIG_RIO is not set |
| 730 | # CONFIG_STALDRV is not set | 875 | # CONFIG_STALDRV is not set |
| 876 | # CONFIG_NOZOMI is not set | ||
| 731 | CONFIG_SGI_SNSC=y | 877 | CONFIG_SGI_SNSC=y |
| 732 | CONFIG_SGI_TIOCX=y | 878 | CONFIG_SGI_TIOCX=y |
| 733 | CONFIG_SGI_MBCS=m | 879 | CONFIG_SGI_MBCS=m |
| @@ -759,76 +905,100 @@ CONFIG_UNIX98_PTYS=y | |||
| 759 | CONFIG_LEGACY_PTYS=y | 905 | CONFIG_LEGACY_PTYS=y |
| 760 | CONFIG_LEGACY_PTY_COUNT=256 | 906 | CONFIG_LEGACY_PTY_COUNT=256 |
| 761 | # CONFIG_IPMI_HANDLER is not set | 907 | # CONFIG_IPMI_HANDLER is not set |
| 762 | # CONFIG_WATCHDOG is not set | ||
| 763 | # CONFIG_HW_RANDOM is not set | 908 | # CONFIG_HW_RANDOM is not set |
| 764 | CONFIG_EFI_RTC=y | 909 | CONFIG_EFI_RTC=y |
| 765 | # CONFIG_R3964 is not set | 910 | # CONFIG_R3964 is not set |
| 766 | # CONFIG_APPLICOM is not set | 911 | # CONFIG_APPLICOM is not set |
| 767 | CONFIG_AGP=m | ||
| 768 | CONFIG_AGP_I460=m | ||
| 769 | CONFIG_AGP_HP_ZX1=m | ||
| 770 | CONFIG_AGP_SGI_TIOCA=m | ||
| 771 | CONFIG_DRM=m | ||
| 772 | CONFIG_DRM_TDFX=m | ||
| 773 | CONFIG_DRM_R128=m | ||
| 774 | CONFIG_DRM_RADEON=m | ||
| 775 | CONFIG_DRM_MGA=m | ||
| 776 | CONFIG_DRM_SIS=m | ||
| 777 | # CONFIG_DRM_VIA is not set | ||
| 778 | # CONFIG_DRM_SAVAGE is not set | ||
| 779 | CONFIG_RAW_DRIVER=m | 912 | CONFIG_RAW_DRIVER=m |
| 780 | CONFIG_MAX_RAW_DEVS=256 | 913 | CONFIG_MAX_RAW_DEVS=256 |
| 781 | CONFIG_HPET=y | 914 | CONFIG_HPET=y |
| 782 | # CONFIG_HPET_RTC_IRQ is not set | ||
| 783 | CONFIG_HPET_MMAP=y | 915 | CONFIG_HPET_MMAP=y |
| 784 | # CONFIG_HANGCHECK_TIMER is not set | 916 | # CONFIG_HANGCHECK_TIMER is not set |
| 785 | CONFIG_MMTIMER=y | 917 | CONFIG_MMTIMER=y |
| 786 | # CONFIG_TCG_TPM is not set | 918 | # CONFIG_TCG_TPM is not set |
| 787 | CONFIG_DEVPORT=y | 919 | CONFIG_DEVPORT=y |
| 788 | # CONFIG_I2C is not set | 920 | # CONFIG_I2C is not set |
| 789 | |||
| 790 | # | ||
| 791 | # SPI support | ||
| 792 | # | ||
| 793 | # CONFIG_SPI is not set | 921 | # CONFIG_SPI is not set |
| 794 | # CONFIG_SPI_MASTER is not set | ||
| 795 | # CONFIG_W1 is not set | 922 | # CONFIG_W1 is not set |
| 796 | # CONFIG_POWER_SUPPLY is not set | 923 | CONFIG_POWER_SUPPLY=y |
| 924 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 925 | # CONFIG_PDA_POWER is not set | ||
| 926 | # CONFIG_BATTERY_DS2760 is not set | ||
| 797 | CONFIG_HWMON=y | 927 | CONFIG_HWMON=y |
| 798 | # CONFIG_HWMON_VID is not set | 928 | # CONFIG_HWMON_VID is not set |
| 799 | # CONFIG_SENSORS_ABITUGURU is not set | 929 | # CONFIG_SENSORS_I5K_AMB is not set |
| 800 | # CONFIG_SENSORS_F71805F is not set | 930 | # CONFIG_SENSORS_F71805F is not set |
| 931 | # CONFIG_SENSORS_F71882FG is not set | ||
| 932 | # CONFIG_SENSORS_IT87 is not set | ||
| 933 | # CONFIG_SENSORS_PC87360 is not set | ||
| 801 | # CONFIG_SENSORS_PC87427 is not set | 934 | # CONFIG_SENSORS_PC87427 is not set |
| 935 | # CONFIG_SENSORS_SIS5595 is not set | ||
| 802 | # CONFIG_SENSORS_SMSC47M1 is not set | 936 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 803 | # CONFIG_SENSORS_SMSC47B397 is not set | 937 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 938 | # CONFIG_SENSORS_VIA686A is not set | ||
| 804 | # CONFIG_SENSORS_VT1211 is not set | 939 | # CONFIG_SENSORS_VT1211 is not set |
| 940 | # CONFIG_SENSORS_VT8231 is not set | ||
| 805 | # CONFIG_SENSORS_W83627HF is not set | 941 | # CONFIG_SENSORS_W83627HF is not set |
| 942 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 806 | # CONFIG_HWMON_DEBUG_CHIP is not set | 943 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 944 | CONFIG_THERMAL=m | ||
| 945 | # CONFIG_THERMAL_HWMON is not set | ||
| 946 | # CONFIG_WATCHDOG is not set | ||
| 947 | |||
| 948 | # | ||
| 949 | # Sonics Silicon Backplane | ||
| 950 | # | ||
| 951 | CONFIG_SSB_POSSIBLE=y | ||
| 952 | # CONFIG_SSB is not set | ||
| 807 | 953 | ||
| 808 | # | 954 | # |
| 809 | # Multifunction device drivers | 955 | # Multifunction device drivers |
| 810 | # | 956 | # |
| 957 | # CONFIG_MFD_CORE is not set | ||
| 811 | # CONFIG_MFD_SM501 is not set | 958 | # CONFIG_MFD_SM501 is not set |
| 959 | # CONFIG_HTC_PASIC3 is not set | ||
| 812 | 960 | ||
| 813 | # | 961 | # |
| 814 | # Multimedia devices | 962 | # Multimedia devices |
| 815 | # | 963 | # |
| 964 | |||
| 965 | # | ||
| 966 | # Multimedia core support | ||
| 967 | # | ||
| 816 | # CONFIG_VIDEO_DEV is not set | 968 | # CONFIG_VIDEO_DEV is not set |
| 817 | # CONFIG_DVB_CORE is not set | 969 | # CONFIG_DVB_CORE is not set |
| 970 | # CONFIG_VIDEO_MEDIA is not set | ||
| 971 | |||
| 972 | # | ||
| 973 | # Multimedia drivers | ||
| 974 | # | ||
| 818 | CONFIG_DAB=y | 975 | CONFIG_DAB=y |
| 819 | # CONFIG_USB_DABUSB is not set | 976 | # CONFIG_USB_DABUSB is not set |
| 820 | 977 | ||
| 821 | # | 978 | # |
| 822 | # Graphics support | 979 | # Graphics support |
| 823 | # | 980 | # |
| 981 | CONFIG_AGP=m | ||
| 982 | CONFIG_AGP_I460=m | ||
| 983 | CONFIG_AGP_HP_ZX1=m | ||
| 984 | CONFIG_AGP_SGI_TIOCA=m | ||
| 985 | CONFIG_DRM=m | ||
| 986 | CONFIG_DRM_TDFX=m | ||
| 987 | CONFIG_DRM_R128=m | ||
| 988 | CONFIG_DRM_RADEON=m | ||
| 989 | CONFIG_DRM_MGA=m | ||
| 990 | CONFIG_DRM_SIS=m | ||
| 991 | # CONFIG_DRM_VIA is not set | ||
| 992 | # CONFIG_DRM_SAVAGE is not set | ||
| 993 | # CONFIG_VGASTATE is not set | ||
| 994 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 995 | # CONFIG_FB is not set | ||
| 824 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 996 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 825 | 997 | ||
| 826 | # | 998 | # |
| 827 | # Display device support | 999 | # Display device support |
| 828 | # | 1000 | # |
| 829 | # CONFIG_DISPLAY_SUPPORT is not set | 1001 | # CONFIG_DISPLAY_SUPPORT is not set |
| 830 | # CONFIG_VGASTATE is not set | ||
| 831 | # CONFIG_FB is not set | ||
| 832 | 1002 | ||
| 833 | # | 1003 | # |
| 834 | # Console display driver support | 1004 | # Console display driver support |
| @@ -836,15 +1006,7 @@ CONFIG_DAB=y | |||
| 836 | CONFIG_VGA_CONSOLE=y | 1006 | CONFIG_VGA_CONSOLE=y |
| 837 | # CONFIG_VGACON_SOFT_SCROLLBACK is not set | 1007 | # CONFIG_VGACON_SOFT_SCROLLBACK is not set |
| 838 | CONFIG_DUMMY_CONSOLE=y | 1008 | CONFIG_DUMMY_CONSOLE=y |
| 839 | |||
| 840 | # | ||
| 841 | # Sound | ||
| 842 | # | ||
| 843 | CONFIG_SOUND=m | 1009 | CONFIG_SOUND=m |
| 844 | |||
| 845 | # | ||
| 846 | # Advanced Linux Sound Architecture | ||
| 847 | # | ||
| 848 | CONFIG_SND=m | 1010 | CONFIG_SND=m |
| 849 | CONFIG_SND_TIMER=m | 1011 | CONFIG_SND_TIMER=m |
| 850 | CONFIG_SND_PCM=m | 1012 | CONFIG_SND_PCM=m |
| @@ -862,22 +1024,18 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 862 | CONFIG_SND_VERBOSE_PROCFS=y | 1024 | CONFIG_SND_VERBOSE_PROCFS=y |
| 863 | CONFIG_SND_VERBOSE_PRINTK=y | 1025 | CONFIG_SND_VERBOSE_PRINTK=y |
| 864 | # CONFIG_SND_DEBUG is not set | 1026 | # CONFIG_SND_DEBUG is not set |
| 865 | 1027 | CONFIG_SND_VMASTER=y | |
| 866 | # | ||
| 867 | # Generic devices | ||
| 868 | # | ||
| 869 | CONFIG_SND_MPU401_UART=m | 1028 | CONFIG_SND_MPU401_UART=m |
| 870 | CONFIG_SND_OPL3_LIB=m | 1029 | CONFIG_SND_OPL3_LIB=m |
| 871 | CONFIG_SND_AC97_CODEC=m | 1030 | CONFIG_SND_AC97_CODEC=m |
| 1031 | CONFIG_SND_DRIVERS=y | ||
| 872 | CONFIG_SND_DUMMY=m | 1032 | CONFIG_SND_DUMMY=m |
| 873 | CONFIG_SND_VIRMIDI=m | 1033 | CONFIG_SND_VIRMIDI=m |
| 874 | CONFIG_SND_MTPAV=m | 1034 | CONFIG_SND_MTPAV=m |
| 875 | CONFIG_SND_SERIAL_U16550=m | 1035 | CONFIG_SND_SERIAL_U16550=m |
| 876 | CONFIG_SND_MPU401=m | 1036 | CONFIG_SND_MPU401=m |
| 877 | 1037 | # CONFIG_SND_AC97_POWER_SAVE is not set | |
| 878 | # | 1038 | CONFIG_SND_PCI=y |
| 879 | # PCI devices | ||
| 880 | # | ||
| 881 | # CONFIG_SND_AD1889 is not set | 1039 | # CONFIG_SND_AD1889 is not set |
| 882 | # CONFIG_SND_ALS300 is not set | 1040 | # CONFIG_SND_ALS300 is not set |
| 883 | # CONFIG_SND_ALI5451 is not set | 1041 | # CONFIG_SND_ALI5451 is not set |
| @@ -886,10 +1044,12 @@ CONFIG_SND_MPU401=m | |||
| 886 | # CONFIG_SND_AU8810 is not set | 1044 | # CONFIG_SND_AU8810 is not set |
| 887 | # CONFIG_SND_AU8820 is not set | 1045 | # CONFIG_SND_AU8820 is not set |
| 888 | # CONFIG_SND_AU8830 is not set | 1046 | # CONFIG_SND_AU8830 is not set |
| 1047 | # CONFIG_SND_AW2 is not set | ||
| 889 | # CONFIG_SND_AZT3328 is not set | 1048 | # CONFIG_SND_AZT3328 is not set |
| 890 | # CONFIG_SND_BT87X is not set | 1049 | # CONFIG_SND_BT87X is not set |
| 891 | # CONFIG_SND_CA0106 is not set | 1050 | # CONFIG_SND_CA0106 is not set |
| 892 | # CONFIG_SND_CMIPCI is not set | 1051 | # CONFIG_SND_CMIPCI is not set |
| 1052 | # CONFIG_SND_OXYGEN is not set | ||
| 893 | CONFIG_SND_CS4281=m | 1053 | CONFIG_SND_CS4281=m |
| 894 | CONFIG_SND_CS46XX=m | 1054 | CONFIG_SND_CS46XX=m |
| 895 | CONFIG_SND_CS46XX_NEW_DSP=y | 1055 | CONFIG_SND_CS46XX_NEW_DSP=y |
| @@ -912,10 +1072,10 @@ CONFIG_SND_EMU10K1=m | |||
| 912 | # CONFIG_SND_ES1938 is not set | 1072 | # CONFIG_SND_ES1938 is not set |
| 913 | # CONFIG_SND_ES1968 is not set | 1073 | # CONFIG_SND_ES1968 is not set |
| 914 | CONFIG_SND_FM801=m | 1074 | CONFIG_SND_FM801=m |
| 915 | # CONFIG_SND_FM801_TEA575X_BOOL is not set | ||
| 916 | # CONFIG_SND_HDA_INTEL is not set | 1075 | # CONFIG_SND_HDA_INTEL is not set |
| 917 | # CONFIG_SND_HDSP is not set | 1076 | # CONFIG_SND_HDSP is not set |
| 918 | # CONFIG_SND_HDSPM is not set | 1077 | # CONFIG_SND_HDSPM is not set |
| 1078 | # CONFIG_SND_HIFIER is not set | ||
| 919 | # CONFIG_SND_ICE1712 is not set | 1079 | # CONFIG_SND_ICE1712 is not set |
| 920 | # CONFIG_SND_ICE1724 is not set | 1080 | # CONFIG_SND_ICE1724 is not set |
| 921 | # CONFIG_SND_INTEL8X0 is not set | 1081 | # CONFIG_SND_INTEL8X0 is not set |
| @@ -933,29 +1093,19 @@ CONFIG_SND_FM801=m | |||
| 933 | # CONFIG_SND_TRIDENT is not set | 1093 | # CONFIG_SND_TRIDENT is not set |
| 934 | # CONFIG_SND_VIA82XX is not set | 1094 | # CONFIG_SND_VIA82XX is not set |
| 935 | # CONFIG_SND_VIA82XX_MODEM is not set | 1095 | # CONFIG_SND_VIA82XX_MODEM is not set |
| 1096 | # CONFIG_SND_VIRTUOSO is not set | ||
| 936 | # CONFIG_SND_VX222 is not set | 1097 | # CONFIG_SND_VX222 is not set |
| 937 | # CONFIG_SND_YMFPCI is not set | 1098 | # CONFIG_SND_YMFPCI is not set |
| 938 | # CONFIG_SND_AC97_POWER_SAVE is not set | 1099 | CONFIG_SND_USB=y |
| 939 | |||
| 940 | # | ||
| 941 | # USB devices | ||
| 942 | # | ||
| 943 | # CONFIG_SND_USB_AUDIO is not set | 1100 | # CONFIG_SND_USB_AUDIO is not set |
| 944 | # CONFIG_SND_USB_CAIAQ is not set | 1101 | # CONFIG_SND_USB_CAIAQ is not set |
| 945 | |||
| 946 | # | ||
| 947 | # System on Chip audio support | ||
| 948 | # | ||
| 949 | # CONFIG_SND_SOC is not set | 1102 | # CONFIG_SND_SOC is not set |
| 950 | |||
| 951 | # | ||
| 952 | # Open Sound System | ||
| 953 | # | ||
| 954 | # CONFIG_SOUND_PRIME is not set | 1103 | # CONFIG_SOUND_PRIME is not set |
| 955 | CONFIG_AC97_BUS=m | 1104 | CONFIG_AC97_BUS=m |
| 956 | CONFIG_HID_SUPPORT=y | 1105 | CONFIG_HID_SUPPORT=y |
| 957 | CONFIG_HID=y | 1106 | CONFIG_HID=y |
| 958 | # CONFIG_HID_DEBUG is not set | 1107 | # CONFIG_HID_DEBUG is not set |
| 1108 | # CONFIG_HIDRAW is not set | ||
| 959 | 1109 | ||
| 960 | # | 1110 | # |
| 961 | # USB Input Devices | 1111 | # USB Input Devices |
| @@ -976,6 +1126,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y | |||
| 976 | CONFIG_USB_ARCH_HAS_EHCI=y | 1126 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 977 | CONFIG_USB=m | 1127 | CONFIG_USB=m |
| 978 | # CONFIG_USB_DEBUG is not set | 1128 | # CONFIG_USB_DEBUG is not set |
| 1129 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 979 | 1130 | ||
| 980 | # | 1131 | # |
| 981 | # Miscellaneous USB options | 1132 | # Miscellaneous USB options |
| @@ -984,17 +1135,17 @@ CONFIG_USB_DEVICEFS=y | |||
| 984 | CONFIG_USB_DEVICE_CLASS=y | 1135 | CONFIG_USB_DEVICE_CLASS=y |
| 985 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1136 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 986 | # CONFIG_USB_SUSPEND is not set | 1137 | # CONFIG_USB_SUSPEND is not set |
| 987 | # CONFIG_USB_PERSIST is not set | ||
| 988 | # CONFIG_USB_OTG is not set | 1138 | # CONFIG_USB_OTG is not set |
| 989 | 1139 | ||
| 990 | # | 1140 | # |
| 991 | # USB Host Controller Drivers | 1141 | # USB Host Controller Drivers |
| 992 | # | 1142 | # |
| 1143 | # CONFIG_USB_C67X00_HCD is not set | ||
| 993 | CONFIG_USB_EHCI_HCD=m | 1144 | CONFIG_USB_EHCI_HCD=m |
| 994 | # CONFIG_USB_EHCI_SPLIT_ISO is not set | ||
| 995 | # CONFIG_USB_EHCI_ROOT_HUB_TT is not set | 1145 | # CONFIG_USB_EHCI_ROOT_HUB_TT is not set |
| 996 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | 1146 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set |
| 997 | # CONFIG_USB_ISP116X_HCD is not set | 1147 | # CONFIG_USB_ISP116X_HCD is not set |
| 1148 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 998 | CONFIG_USB_OHCI_HCD=m | 1149 | CONFIG_USB_OHCI_HCD=m |
| 999 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | 1150 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 1000 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | 1151 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set |
| @@ -1008,6 +1159,7 @@ CONFIG_USB_UHCI_HCD=m | |||
| 1008 | # | 1159 | # |
| 1009 | # CONFIG_USB_ACM is not set | 1160 | # CONFIG_USB_ACM is not set |
| 1010 | # CONFIG_USB_PRINTER is not set | 1161 | # CONFIG_USB_PRINTER is not set |
| 1162 | # CONFIG_USB_WDM is not set | ||
| 1011 | 1163 | ||
| 1012 | # | 1164 | # |
| 1013 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1165 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' |
| @@ -1027,7 +1179,9 @@ CONFIG_USB_STORAGE=m | |||
| 1027 | # CONFIG_USB_STORAGE_SDDR55 is not set | 1179 | # CONFIG_USB_STORAGE_SDDR55 is not set |
| 1028 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | 1180 | # CONFIG_USB_STORAGE_JUMPSHOT is not set |
| 1029 | # CONFIG_USB_STORAGE_ALAUDA is not set | 1181 | # CONFIG_USB_STORAGE_ALAUDA is not set |
| 1182 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1030 | # CONFIG_USB_STORAGE_KARMA is not set | 1183 | # CONFIG_USB_STORAGE_KARMA is not set |
| 1184 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1031 | # CONFIG_USB_LIBUSUAL is not set | 1185 | # CONFIG_USB_LIBUSUAL is not set |
| 1032 | 1186 | ||
| 1033 | # | 1187 | # |
| @@ -1040,10 +1194,6 @@ CONFIG_USB_MON=y | |||
| 1040 | # | 1194 | # |
| 1041 | # USB port drivers | 1195 | # USB port drivers |
| 1042 | # | 1196 | # |
| 1043 | |||
| 1044 | # | ||
| 1045 | # USB Serial Converter support | ||
| 1046 | # | ||
| 1047 | # CONFIG_USB_SERIAL is not set | 1197 | # CONFIG_USB_SERIAL is not set |
| 1048 | 1198 | ||
| 1049 | # | 1199 | # |
| @@ -1069,67 +1219,32 @@ CONFIG_USB_MON=y | |||
| 1069 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1219 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1070 | # CONFIG_USB_IOWARRIOR is not set | 1220 | # CONFIG_USB_IOWARRIOR is not set |
| 1071 | # CONFIG_USB_TEST is not set | 1221 | # CONFIG_USB_TEST is not set |
| 1072 | 1222 | # CONFIG_USB_ISIGHTFW is not set | |
| 1073 | # | ||
| 1074 | # USB DSL modem support | ||
| 1075 | # | ||
| 1076 | |||
| 1077 | # | ||
| 1078 | # USB Gadget Support | ||
| 1079 | # | ||
| 1080 | # CONFIG_USB_GADGET is not set | 1223 | # CONFIG_USB_GADGET is not set |
| 1081 | # CONFIG_MMC is not set | 1224 | # CONFIG_MMC is not set |
| 1082 | 1225 | # CONFIG_MEMSTICK is not set | |
| 1083 | # | ||
| 1084 | # LED devices | ||
| 1085 | # | ||
| 1086 | # CONFIG_NEW_LEDS is not set | 1226 | # CONFIG_NEW_LEDS is not set |
| 1087 | 1227 | # CONFIG_ACCESSIBILITY is not set | |
| 1088 | # | ||
| 1089 | # LED drivers | ||
| 1090 | # | ||
| 1091 | |||
| 1092 | # | ||
| 1093 | # LED Triggers | ||
| 1094 | # | ||
| 1095 | CONFIG_INFINIBAND=m | 1228 | CONFIG_INFINIBAND=m |
| 1096 | # CONFIG_INFINIBAND_USER_MAD is not set | 1229 | # CONFIG_INFINIBAND_USER_MAD is not set |
| 1097 | # CONFIG_INFINIBAND_USER_ACCESS is not set | 1230 | # CONFIG_INFINIBAND_USER_ACCESS is not set |
| 1098 | CONFIG_INFINIBAND_ADDR_TRANS=y | 1231 | CONFIG_INFINIBAND_ADDR_TRANS=y |
| 1099 | CONFIG_INFINIBAND_MTHCA=m | 1232 | CONFIG_INFINIBAND_MTHCA=m |
| 1100 | CONFIG_INFINIBAND_MTHCA_DEBUG=y | 1233 | CONFIG_INFINIBAND_MTHCA_DEBUG=y |
| 1234 | # CONFIG_INFINIBAND_IPATH is not set | ||
| 1101 | # CONFIG_INFINIBAND_AMSO1100 is not set | 1235 | # CONFIG_INFINIBAND_AMSO1100 is not set |
| 1102 | # CONFIG_MLX4_INFINIBAND is not set | 1236 | # CONFIG_MLX4_INFINIBAND is not set |
| 1237 | # CONFIG_INFINIBAND_NES is not set | ||
| 1103 | CONFIG_INFINIBAND_IPOIB=m | 1238 | CONFIG_INFINIBAND_IPOIB=m |
| 1104 | # CONFIG_INFINIBAND_IPOIB_CM is not set | 1239 | # CONFIG_INFINIBAND_IPOIB_CM is not set |
| 1105 | CONFIG_INFINIBAND_IPOIB_DEBUG=y | 1240 | CONFIG_INFINIBAND_IPOIB_DEBUG=y |
| 1106 | # CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set | 1241 | # CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set |
| 1107 | # CONFIG_INFINIBAND_SRP is not set | 1242 | # CONFIG_INFINIBAND_SRP is not set |
| 1108 | # CONFIG_INFINIBAND_ISER is not set | 1243 | # CONFIG_INFINIBAND_ISER is not set |
| 1109 | |||
| 1110 | # | ||
| 1111 | # Real Time Clock | ||
| 1112 | # | ||
| 1113 | # CONFIG_RTC_CLASS is not set | 1244 | # CONFIG_RTC_CLASS is not set |
| 1114 | 1245 | # CONFIG_DMADEVICES is not set | |
| 1115 | # | ||
| 1116 | # DMA Engine support | ||
| 1117 | # | ||
| 1118 | # CONFIG_DMA_ENGINE is not set | ||
| 1119 | |||
| 1120 | # | ||
| 1121 | # DMA Clients | ||
| 1122 | # | ||
| 1123 | |||
| 1124 | # | ||
| 1125 | # DMA Devices | ||
| 1126 | # | ||
| 1127 | |||
| 1128 | # | ||
| 1129 | # Userspace I/O | ||
| 1130 | # | ||
| 1131 | # CONFIG_UIO is not set | 1246 | # CONFIG_UIO is not set |
| 1132 | # CONFIG_MSPEC is not set | 1247 | CONFIG_MSPEC=m |
| 1133 | 1248 | ||
| 1134 | # | 1249 | # |
| 1135 | # File systems | 1250 | # File systems |
| @@ -1145,7 +1260,6 @@ CONFIG_EXT3_FS_POSIX_ACL=y | |||
| 1145 | CONFIG_EXT3_FS_SECURITY=y | 1260 | CONFIG_EXT3_FS_SECURITY=y |
| 1146 | # CONFIG_EXT4DEV_FS is not set | 1261 | # CONFIG_EXT4DEV_FS is not set |
| 1147 | CONFIG_JBD=y | 1262 | CONFIG_JBD=y |
| 1148 | # CONFIG_JBD_DEBUG is not set | ||
| 1149 | CONFIG_FS_MBCACHE=y | 1263 | CONFIG_FS_MBCACHE=y |
| 1150 | CONFIG_REISERFS_FS=y | 1264 | CONFIG_REISERFS_FS=y |
| 1151 | # CONFIG_REISERFS_CHECK is not set | 1265 | # CONFIG_REISERFS_CHECK is not set |
| @@ -1157,17 +1271,15 @@ CONFIG_REISERFS_FS_SECURITY=y | |||
| 1157 | CONFIG_FS_POSIX_ACL=y | 1271 | CONFIG_FS_POSIX_ACL=y |
| 1158 | CONFIG_XFS_FS=y | 1272 | CONFIG_XFS_FS=y |
| 1159 | # CONFIG_XFS_QUOTA is not set | 1273 | # CONFIG_XFS_QUOTA is not set |
| 1160 | # CONFIG_XFS_SECURITY is not set | ||
| 1161 | # CONFIG_XFS_POSIX_ACL is not set | 1274 | # CONFIG_XFS_POSIX_ACL is not set |
| 1162 | # CONFIG_XFS_RT is not set | 1275 | # CONFIG_XFS_RT is not set |
| 1276 | # CONFIG_XFS_DEBUG is not set | ||
| 1163 | # CONFIG_GFS2_FS is not set | 1277 | # CONFIG_GFS2_FS is not set |
| 1164 | # CONFIG_OCFS2_FS is not set | 1278 | # CONFIG_OCFS2_FS is not set |
| 1165 | # CONFIG_MINIX_FS is not set | 1279 | CONFIG_DNOTIFY=y |
| 1166 | # CONFIG_ROMFS_FS is not set | ||
| 1167 | CONFIG_INOTIFY=y | 1280 | CONFIG_INOTIFY=y |
| 1168 | CONFIG_INOTIFY_USER=y | 1281 | CONFIG_INOTIFY_USER=y |
| 1169 | # CONFIG_QUOTA is not set | 1282 | # CONFIG_QUOTA is not set |
| 1170 | CONFIG_DNOTIFY=y | ||
| 1171 | CONFIG_AUTOFS_FS=y | 1283 | CONFIG_AUTOFS_FS=y |
| 1172 | CONFIG_AUTOFS4_FS=y | 1284 | CONFIG_AUTOFS4_FS=y |
| 1173 | # CONFIG_FUSE_FS is not set | 1285 | # CONFIG_FUSE_FS is not set |
| @@ -1205,7 +1317,6 @@ CONFIG_TMPFS=y | |||
| 1205 | # CONFIG_TMPFS_POSIX_ACL is not set | 1317 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1206 | CONFIG_HUGETLBFS=y | 1318 | CONFIG_HUGETLBFS=y |
| 1207 | CONFIG_HUGETLB_PAGE=y | 1319 | CONFIG_HUGETLB_PAGE=y |
| 1208 | CONFIG_RAMFS=y | ||
| 1209 | # CONFIG_CONFIGFS_FS is not set | 1320 | # CONFIG_CONFIGFS_FS is not set |
| 1210 | 1321 | ||
| 1211 | # | 1322 | # |
| @@ -1220,32 +1331,30 @@ CONFIG_RAMFS=y | |||
| 1220 | # CONFIG_EFS_FS is not set | 1331 | # CONFIG_EFS_FS is not set |
| 1221 | # CONFIG_CRAMFS is not set | 1332 | # CONFIG_CRAMFS is not set |
| 1222 | # CONFIG_VXFS_FS is not set | 1333 | # CONFIG_VXFS_FS is not set |
| 1334 | # CONFIG_MINIX_FS is not set | ||
| 1335 | # CONFIG_OMFS_FS is not set | ||
| 1223 | # CONFIG_HPFS_FS is not set | 1336 | # CONFIG_HPFS_FS is not set |
| 1224 | # CONFIG_QNX4FS_FS is not set | 1337 | # CONFIG_QNX4FS_FS is not set |
| 1338 | # CONFIG_ROMFS_FS is not set | ||
| 1225 | # CONFIG_SYSV_FS is not set | 1339 | # CONFIG_SYSV_FS is not set |
| 1226 | # CONFIG_UFS_FS is not set | 1340 | # CONFIG_UFS_FS is not set |
| 1227 | 1341 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1228 | # | ||
| 1229 | # Network File Systems | ||
| 1230 | # | ||
| 1231 | CONFIG_NFS_FS=m | 1342 | CONFIG_NFS_FS=m |
| 1232 | CONFIG_NFS_V3=y | 1343 | CONFIG_NFS_V3=y |
| 1233 | # CONFIG_NFS_V3_ACL is not set | 1344 | # CONFIG_NFS_V3_ACL is not set |
| 1234 | CONFIG_NFS_V4=y | 1345 | CONFIG_NFS_V4=y |
| 1235 | CONFIG_NFS_DIRECTIO=y | ||
| 1236 | CONFIG_NFSD=m | 1346 | CONFIG_NFSD=m |
| 1237 | CONFIG_NFSD_V3=y | 1347 | CONFIG_NFSD_V3=y |
| 1238 | # CONFIG_NFSD_V3_ACL is not set | 1348 | # CONFIG_NFSD_V3_ACL is not set |
| 1239 | CONFIG_NFSD_V4=y | 1349 | CONFIG_NFSD_V4=y |
| 1240 | CONFIG_NFSD_TCP=y | ||
| 1241 | CONFIG_LOCKD=m | 1350 | CONFIG_LOCKD=m |
| 1242 | CONFIG_LOCKD_V4=y | 1351 | CONFIG_LOCKD_V4=y |
| 1243 | CONFIG_EXPORTFS=m | 1352 | CONFIG_EXPORTFS=m |
| 1244 | CONFIG_NFS_COMMON=y | 1353 | CONFIG_NFS_COMMON=y |
| 1245 | CONFIG_SUNRPC=m | 1354 | CONFIG_SUNRPC=m |
| 1246 | CONFIG_SUNRPC_GSS=m | 1355 | CONFIG_SUNRPC_GSS=m |
| 1247 | # CONFIG_SUNRPC_BIND34 is not set | 1356 | CONFIG_SUNRPC_XPRT_RDMA=m |
| 1248 | CONFIG_RPCSEC_GSS_KRB5=y | 1357 | CONFIG_RPCSEC_GSS_KRB5=m |
| 1249 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1358 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1250 | CONFIG_SMB_FS=m | 1359 | CONFIG_SMB_FS=m |
| 1251 | CONFIG_SMB_NLS_DEFAULT=y | 1360 | CONFIG_SMB_NLS_DEFAULT=y |
| @@ -1281,10 +1390,6 @@ CONFIG_SGI_PARTITION=y | |||
| 1281 | # CONFIG_KARMA_PARTITION is not set | 1390 | # CONFIG_KARMA_PARTITION is not set |
| 1282 | CONFIG_EFI_PARTITION=y | 1391 | CONFIG_EFI_PARTITION=y |
| 1283 | # CONFIG_SYSV68_PARTITION is not set | 1392 | # CONFIG_SYSV68_PARTITION is not set |
| 1284 | |||
| 1285 | # | ||
| 1286 | # Native Language Support | ||
| 1287 | # | ||
| 1288 | CONFIG_NLS=y | 1393 | CONFIG_NLS=y |
| 1289 | CONFIG_NLS_DEFAULT="iso8859-1" | 1394 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1290 | CONFIG_NLS_CODEPAGE_437=y | 1395 | CONFIG_NLS_CODEPAGE_437=y |
| @@ -1325,22 +1430,24 @@ CONFIG_NLS_ISO8859_15=m | |||
| 1325 | CONFIG_NLS_KOI8_R=m | 1430 | CONFIG_NLS_KOI8_R=m |
| 1326 | CONFIG_NLS_KOI8_U=m | 1431 | CONFIG_NLS_KOI8_U=m |
| 1327 | CONFIG_NLS_UTF8=m | 1432 | CONFIG_NLS_UTF8=m |
| 1328 | |||
| 1329 | # | ||
| 1330 | # Distributed Lock Manager | ||
| 1331 | # | ||
| 1332 | # CONFIG_DLM is not set | 1433 | # CONFIG_DLM is not set |
| 1434 | CONFIG_HAVE_KVM=y | ||
| 1435 | CONFIG_VIRTUALIZATION=y | ||
| 1436 | # CONFIG_KVM is not set | ||
| 1333 | 1437 | ||
| 1334 | # | 1438 | # |
| 1335 | # Library routines | 1439 | # Library routines |
| 1336 | # | 1440 | # |
| 1337 | CONFIG_BITREVERSE=y | 1441 | CONFIG_BITREVERSE=y |
| 1442 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
| 1338 | # CONFIG_CRC_CCITT is not set | 1443 | # CONFIG_CRC_CCITT is not set |
| 1339 | # CONFIG_CRC16 is not set | 1444 | # CONFIG_CRC16 is not set |
| 1340 | # CONFIG_CRC_ITU_T is not set | 1445 | CONFIG_CRC_T10DIF=y |
| 1446 | CONFIG_CRC_ITU_T=m | ||
| 1341 | CONFIG_CRC32=y | 1447 | CONFIG_CRC32=y |
| 1342 | # CONFIG_CRC7 is not set | 1448 | # CONFIG_CRC7 is not set |
| 1343 | # CONFIG_LIBCRC32C is not set | 1449 | # CONFIG_LIBCRC32C is not set |
| 1450 | CONFIG_GENERIC_ALLOCATOR=y | ||
| 1344 | CONFIG_PLIST=y | 1451 | CONFIG_PLIST=y |
| 1345 | CONFIG_HAS_IOMEM=y | 1452 | CONFIG_HAS_IOMEM=y |
| 1346 | CONFIG_HAS_IOPORT=y | 1453 | CONFIG_HAS_IOPORT=y |
| @@ -1358,16 +1465,12 @@ CONFIG_IRQ_PER_CPU=y | |||
| 1358 | # CONFIG_HP_SIMSCSI is not set | 1465 | # CONFIG_HP_SIMSCSI is not set |
| 1359 | 1466 | ||
| 1360 | # | 1467 | # |
| 1361 | # Instrumentation Support | ||
| 1362 | # | ||
| 1363 | # CONFIG_PROFILING is not set | ||
| 1364 | # CONFIG_KPROBES is not set | ||
| 1365 | |||
| 1366 | # | ||
| 1367 | # Kernel hacking | 1468 | # Kernel hacking |
| 1368 | # | 1469 | # |
| 1369 | # CONFIG_PRINTK_TIME is not set | 1470 | # CONFIG_PRINTK_TIME is not set |
| 1471 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1370 | CONFIG_ENABLE_MUST_CHECK=y | 1472 | CONFIG_ENABLE_MUST_CHECK=y |
| 1473 | CONFIG_FRAME_WARN=2048 | ||
| 1371 | CONFIG_MAGIC_SYSRQ=y | 1474 | CONFIG_MAGIC_SYSRQ=y |
| 1372 | # CONFIG_UNUSED_SYMBOLS is not set | 1475 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1373 | # CONFIG_DEBUG_FS is not set | 1476 | # CONFIG_DEBUG_FS is not set |
| @@ -1375,10 +1478,14 @@ CONFIG_MAGIC_SYSRQ=y | |||
| 1375 | CONFIG_DEBUG_KERNEL=y | 1478 | CONFIG_DEBUG_KERNEL=y |
| 1376 | # CONFIG_DEBUG_SHIRQ is not set | 1479 | # CONFIG_DEBUG_SHIRQ is not set |
| 1377 | CONFIG_DETECT_SOFTLOCKUP=y | 1480 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1481 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1482 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1378 | CONFIG_SCHED_DEBUG=y | 1483 | CONFIG_SCHED_DEBUG=y |
| 1379 | # CONFIG_SCHEDSTATS is not set | 1484 | # CONFIG_SCHEDSTATS is not set |
| 1380 | # CONFIG_TIMER_STATS is not set | 1485 | # CONFIG_TIMER_STATS is not set |
| 1381 | # CONFIG_DEBUG_SLAB is not set | 1486 | # CONFIG_DEBUG_OBJECTS is not set |
| 1487 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1488 | # CONFIG_SLUB_STATS is not set | ||
| 1382 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1489 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1383 | # CONFIG_RT_MUTEX_TESTER is not set | 1490 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1384 | # CONFIG_DEBUG_SPINLOCK is not set | 1491 | # CONFIG_DEBUG_SPINLOCK is not set |
| @@ -1388,10 +1495,15 @@ CONFIG_DEBUG_MUTEXES=y | |||
| 1388 | # CONFIG_DEBUG_KOBJECT is not set | 1495 | # CONFIG_DEBUG_KOBJECT is not set |
| 1389 | # CONFIG_DEBUG_INFO is not set | 1496 | # CONFIG_DEBUG_INFO is not set |
| 1390 | # CONFIG_DEBUG_VM is not set | 1497 | # CONFIG_DEBUG_VM is not set |
| 1498 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1499 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1391 | # CONFIG_DEBUG_LIST is not set | 1500 | # CONFIG_DEBUG_LIST is not set |
| 1392 | CONFIG_FORCED_INLINING=y | 1501 | # CONFIG_DEBUG_SG is not set |
| 1502 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1393 | # CONFIG_RCU_TORTURE_TEST is not set | 1503 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1504 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1394 | # CONFIG_FAULT_INJECTION is not set | 1505 | # CONFIG_FAULT_INJECTION is not set |
| 1506 | # CONFIG_SAMPLES is not set | ||
| 1395 | CONFIG_IA64_GRANULE_16MB=y | 1507 | CONFIG_IA64_GRANULE_16MB=y |
| 1396 | # CONFIG_IA64_GRANULE_64MB is not set | 1508 | # CONFIG_IA64_GRANULE_64MB is not set |
| 1397 | # CONFIG_IA64_PRINT_HAZARDS is not set | 1509 | # CONFIG_IA64_PRINT_HAZARDS is not set |
| @@ -1405,41 +1517,85 @@ CONFIG_SYSVIPC_COMPAT=y | |||
| 1405 | # | 1517 | # |
| 1406 | # CONFIG_KEYS is not set | 1518 | # CONFIG_KEYS is not set |
| 1407 | # CONFIG_SECURITY is not set | 1519 | # CONFIG_SECURITY is not set |
| 1520 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1408 | CONFIG_CRYPTO=y | 1521 | CONFIG_CRYPTO=y |
| 1522 | |||
| 1523 | # | ||
| 1524 | # Crypto core or helper | ||
| 1525 | # | ||
| 1409 | CONFIG_CRYPTO_ALGAPI=y | 1526 | CONFIG_CRYPTO_ALGAPI=y |
| 1410 | CONFIG_CRYPTO_BLKCIPHER=m | 1527 | CONFIG_CRYPTO_BLKCIPHER=m |
| 1411 | CONFIG_CRYPTO_MANAGER=m | 1528 | CONFIG_CRYPTO_MANAGER=m |
| 1529 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1530 | # CONFIG_CRYPTO_NULL is not set | ||
| 1531 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1532 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1533 | # CONFIG_CRYPTO_TEST is not set | ||
| 1534 | |||
| 1535 | # | ||
| 1536 | # Authenticated Encryption with Associated Data | ||
| 1537 | # | ||
| 1538 | # CONFIG_CRYPTO_CCM is not set | ||
| 1539 | # CONFIG_CRYPTO_GCM is not set | ||
| 1540 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1541 | |||
| 1542 | # | ||
| 1543 | # Block modes | ||
| 1544 | # | ||
| 1545 | CONFIG_CRYPTO_CBC=m | ||
| 1546 | # CONFIG_CRYPTO_CTR is not set | ||
| 1547 | # CONFIG_CRYPTO_CTS is not set | ||
| 1548 | CONFIG_CRYPTO_ECB=m | ||
| 1549 | # CONFIG_CRYPTO_LRW is not set | ||
| 1550 | CONFIG_CRYPTO_PCBC=m | ||
| 1551 | # CONFIG_CRYPTO_XTS is not set | ||
| 1552 | |||
| 1553 | # | ||
| 1554 | # Hash modes | ||
| 1555 | # | ||
| 1412 | # CONFIG_CRYPTO_HMAC is not set | 1556 | # CONFIG_CRYPTO_HMAC is not set |
| 1413 | # CONFIG_CRYPTO_XCBC is not set | 1557 | # CONFIG_CRYPTO_XCBC is not set |
| 1414 | # CONFIG_CRYPTO_NULL is not set | 1558 | |
| 1559 | # | ||
| 1560 | # Digest | ||
| 1561 | # | ||
| 1562 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1415 | # CONFIG_CRYPTO_MD4 is not set | 1563 | # CONFIG_CRYPTO_MD4 is not set |
| 1416 | CONFIG_CRYPTO_MD5=y | 1564 | CONFIG_CRYPTO_MD5=y |
| 1565 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1566 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1567 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1568 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1569 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1417 | # CONFIG_CRYPTO_SHA1 is not set | 1570 | # CONFIG_CRYPTO_SHA1 is not set |
| 1418 | # CONFIG_CRYPTO_SHA256 is not set | 1571 | # CONFIG_CRYPTO_SHA256 is not set |
| 1419 | # CONFIG_CRYPTO_SHA512 is not set | 1572 | # CONFIG_CRYPTO_SHA512 is not set |
| 1420 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1421 | # CONFIG_CRYPTO_TGR192 is not set | 1573 | # CONFIG_CRYPTO_TGR192 is not set |
| 1422 | # CONFIG_CRYPTO_GF128MUL is not set | 1574 | # CONFIG_CRYPTO_WP512 is not set |
| 1423 | CONFIG_CRYPTO_ECB=m | 1575 | |
| 1424 | CONFIG_CRYPTO_CBC=m | 1576 | # |
| 1425 | CONFIG_CRYPTO_PCBC=m | 1577 | # Ciphers |
| 1426 | # CONFIG_CRYPTO_LRW is not set | 1578 | # |
| 1427 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1428 | CONFIG_CRYPTO_DES=m | ||
| 1429 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1430 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1431 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1432 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1433 | # CONFIG_CRYPTO_AES is not set | 1579 | # CONFIG_CRYPTO_AES is not set |
| 1580 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1581 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1582 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1583 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1434 | # CONFIG_CRYPTO_CAST5 is not set | 1584 | # CONFIG_CRYPTO_CAST5 is not set |
| 1435 | # CONFIG_CRYPTO_CAST6 is not set | 1585 | # CONFIG_CRYPTO_CAST6 is not set |
| 1436 | # CONFIG_CRYPTO_TEA is not set | 1586 | CONFIG_CRYPTO_DES=m |
| 1437 | # CONFIG_CRYPTO_ARC4 is not set | 1587 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1438 | # CONFIG_CRYPTO_KHAZAD is not set | 1588 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1439 | # CONFIG_CRYPTO_ANUBIS is not set | 1589 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1590 | # CONFIG_CRYPTO_SEED is not set | ||
| 1591 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1592 | # CONFIG_CRYPTO_TEA is not set | ||
| 1593 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1594 | |||
| 1595 | # | ||
| 1596 | # Compression | ||
| 1597 | # | ||
| 1440 | # CONFIG_CRYPTO_DEFLATE is not set | 1598 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1441 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1599 | # CONFIG_CRYPTO_LZO is not set |
| 1442 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1443 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1444 | # CONFIG_CRYPTO_TEST is not set | ||
| 1445 | CONFIG_CRYPTO_HW=y | 1600 | CONFIG_CRYPTO_HW=y |
| 1601 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | ||
diff --git a/arch/ia64/kernel/.gitignore b/arch/ia64/kernel/.gitignore index 98307759a3b8..21cb0da5ded8 100644 --- a/arch/ia64/kernel/.gitignore +++ b/arch/ia64/kernel/.gitignore | |||
| @@ -1 +1,2 @@ | |||
| 1 | gate.lds | 1 | gate.lds |
| 2 | vmlinux.lds | ||
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S index c39627df3cde..416a952b19bd 100644 --- a/arch/ia64/kernel/ivt.S +++ b/arch/ia64/kernel/ivt.S | |||
| @@ -1243,11 +1243,11 @@ ENTRY(speculation_vector) | |||
| 1243 | 1243 | ||
| 1244 | add r17=r17,r18 // now add the offset | 1244 | add r17=r17,r18 // now add the offset |
| 1245 | ;; | 1245 | ;; |
| 1246 | MOV_FROM_IIP(r17) | 1246 | MOV_TO_IIP(r17, r19) |
| 1247 | dep r16=0,r16,41,2 // clear EI | 1247 | dep r16=0,r16,41,2 // clear EI |
| 1248 | ;; | 1248 | ;; |
| 1249 | 1249 | ||
| 1250 | MOV_FROM_IPSR(p0, r16) | 1250 | MOV_TO_IPSR(p0, r16, r19) |
| 1251 | ;; | 1251 | ;; |
| 1252 | 1252 | ||
| 1253 | RFI | 1253 | RFI |
diff --git a/include/asm-m68knommu/Kbuild b/arch/m68knommu/include/asm/Kbuild index c68e1680da01..c68e1680da01 100644 --- a/include/asm-m68knommu/Kbuild +++ b/arch/m68knommu/include/asm/Kbuild | |||
diff --git a/include/asm-m68knommu/MC68328.h b/arch/m68knommu/include/asm/MC68328.h index a337e56d09bf..a337e56d09bf 100644 --- a/include/asm-m68knommu/MC68328.h +++ b/arch/m68knommu/include/asm/MC68328.h | |||
diff --git a/include/asm-m68knommu/MC68332.h b/arch/m68knommu/include/asm/MC68332.h index 6bb8f02685a2..6bb8f02685a2 100644 --- a/include/asm-m68knommu/MC68332.h +++ b/arch/m68knommu/include/asm/MC68332.h | |||
diff --git a/include/asm-m68knommu/MC68EZ328.h b/arch/m68knommu/include/asm/MC68EZ328.h index 69b7f9139e5e..69b7f9139e5e 100644 --- a/include/asm-m68knommu/MC68EZ328.h +++ b/arch/m68knommu/include/asm/MC68EZ328.h | |||
diff --git a/include/asm-m68knommu/MC68VZ328.h b/arch/m68knommu/include/asm/MC68VZ328.h index 2b9bf626a0a5..2b9bf626a0a5 100644 --- a/include/asm-m68knommu/MC68VZ328.h +++ b/arch/m68knommu/include/asm/MC68VZ328.h | |||
diff --git a/include/asm-m68knommu/a.out.h b/arch/m68knommu/include/asm/a.out.h index ce18ef99de04..ce18ef99de04 100644 --- a/include/asm-m68knommu/a.out.h +++ b/arch/m68knommu/include/asm/a.out.h | |||
diff --git a/include/asm-m68knommu/anchor.h b/arch/m68knommu/include/asm/anchor.h index 871c0d5cfc3d..871c0d5cfc3d 100644 --- a/include/asm-m68knommu/anchor.h +++ b/arch/m68knommu/include/asm/anchor.h | |||
diff --git a/include/asm-m68knommu/atomic.h b/arch/m68knommu/include/asm/atomic.h index d5632a305dae..d5632a305dae 100644 --- a/include/asm-m68knommu/atomic.h +++ b/arch/m68knommu/include/asm/atomic.h | |||
diff --git a/include/asm-m68knommu/auxvec.h b/arch/m68knommu/include/asm/auxvec.h index 844d6d52204b..844d6d52204b 100644 --- a/include/asm-m68knommu/auxvec.h +++ b/arch/m68knommu/include/asm/auxvec.h | |||
diff --git a/include/asm-m68knommu/bitops.h b/arch/m68knommu/include/asm/bitops.h index 6f3685eab44c..6f3685eab44c 100644 --- a/include/asm-m68knommu/bitops.h +++ b/arch/m68knommu/include/asm/bitops.h | |||
diff --git a/include/asm-m68knommu/bootinfo.h b/arch/m68knommu/include/asm/bootinfo.h index c12e526f5189..c12e526f5189 100644 --- a/include/asm-m68knommu/bootinfo.h +++ b/arch/m68knommu/include/asm/bootinfo.h | |||
diff --git a/include/asm-m68knommu/bootstd.h b/arch/m68knommu/include/asm/bootstd.h index bdc1a4ac4fe9..bdc1a4ac4fe9 100644 --- a/include/asm-m68knommu/bootstd.h +++ b/arch/m68knommu/include/asm/bootstd.h | |||
diff --git a/include/asm-m68knommu/bug.h b/arch/m68knommu/include/asm/bug.h index 70e7dc0af21a..70e7dc0af21a 100644 --- a/include/asm-m68knommu/bug.h +++ b/arch/m68knommu/include/asm/bug.h | |||
diff --git a/include/asm-m68knommu/bugs.h b/arch/m68knommu/include/asm/bugs.h index 5f382dac3a60..5f382dac3a60 100644 --- a/include/asm-m68knommu/bugs.h +++ b/arch/m68knommu/include/asm/bugs.h | |||
diff --git a/include/asm-m68knommu/byteorder.h b/arch/m68knommu/include/asm/byteorder.h index 20bb4426b610..20bb4426b610 100644 --- a/include/asm-m68knommu/byteorder.h +++ b/arch/m68knommu/include/asm/byteorder.h | |||
diff --git a/include/asm-m68knommu/cache.h b/arch/m68knommu/include/asm/cache.h index 24e9eace5f8c..24e9eace5f8c 100644 --- a/include/asm-m68knommu/cache.h +++ b/arch/m68knommu/include/asm/cache.h | |||
diff --git a/include/asm-m68knommu/cachectl.h b/arch/m68knommu/include/asm/cachectl.h index bcf5a6a9dd52..bcf5a6a9dd52 100644 --- a/include/asm-m68knommu/cachectl.h +++ b/arch/m68knommu/include/asm/cachectl.h | |||
diff --git a/include/asm-m68knommu/cacheflush.h b/arch/m68knommu/include/asm/cacheflush.h index 87e5dc0413b4..87e5dc0413b4 100644 --- a/include/asm-m68knommu/cacheflush.h +++ b/arch/m68knommu/include/asm/cacheflush.h | |||
diff --git a/include/asm-m68knommu/checksum.h b/arch/m68knommu/include/asm/checksum.h index 81883482ffb1..81883482ffb1 100644 --- a/include/asm-m68knommu/checksum.h +++ b/arch/m68knommu/include/asm/checksum.h | |||
diff --git a/include/asm-m68knommu/coldfire.h b/arch/m68knommu/include/asm/coldfire.h index 83a9fa4e618a..83a9fa4e618a 100644 --- a/include/asm-m68knommu/coldfire.h +++ b/arch/m68knommu/include/asm/coldfire.h | |||
diff --git a/include/asm-m68knommu/commproc.h b/arch/m68knommu/include/asm/commproc.h index edf5eb6c08d2..edf5eb6c08d2 100644 --- a/include/asm-m68knommu/commproc.h +++ b/arch/m68knommu/include/asm/commproc.h | |||
diff --git a/include/asm-m68knommu/cputime.h b/arch/m68knommu/include/asm/cputime.h index a0c4a660878d..a0c4a660878d 100644 --- a/include/asm-m68knommu/cputime.h +++ b/arch/m68knommu/include/asm/cputime.h | |||
diff --git a/include/asm-m68knommu/current.h b/arch/m68knommu/include/asm/current.h index 53ee0f9f7cef..53ee0f9f7cef 100644 --- a/include/asm-m68knommu/current.h +++ b/arch/m68knommu/include/asm/current.h | |||
diff --git a/include/asm-m68knommu/dbg.h b/arch/m68knommu/include/asm/dbg.h index 27af3270f671..27af3270f671 100644 --- a/include/asm-m68knommu/dbg.h +++ b/arch/m68knommu/include/asm/dbg.h | |||
diff --git a/include/asm-m68knommu/delay.h b/arch/m68knommu/include/asm/delay.h index 55cbd6294ab6..55cbd6294ab6 100644 --- a/include/asm-m68knommu/delay.h +++ b/arch/m68knommu/include/asm/delay.h | |||
diff --git a/include/asm-m68knommu/device.h b/arch/m68knommu/include/asm/device.h index d8f9872b0e2d..d8f9872b0e2d 100644 --- a/include/asm-m68knommu/device.h +++ b/arch/m68knommu/include/asm/device.h | |||
diff --git a/include/asm-m68knommu/div64.h b/arch/m68knommu/include/asm/div64.h index 6cd978cefb28..6cd978cefb28 100644 --- a/include/asm-m68knommu/div64.h +++ b/arch/m68knommu/include/asm/div64.h | |||
diff --git a/include/asm-m68knommu/dma-mapping.h b/arch/m68knommu/include/asm/dma-mapping.h index 6aeab18e58bd..6aeab18e58bd 100644 --- a/include/asm-m68knommu/dma-mapping.h +++ b/arch/m68knommu/include/asm/dma-mapping.h | |||
diff --git a/include/asm-m68knommu/dma.h b/arch/m68knommu/include/asm/dma.h index 939a02056217..939a02056217 100644 --- a/include/asm-m68knommu/dma.h +++ b/arch/m68knommu/include/asm/dma.h | |||
diff --git a/include/asm-m68knommu/elf.h b/arch/m68knommu/include/asm/elf.h index 27f0ec70fba8..27f0ec70fba8 100644 --- a/include/asm-m68knommu/elf.h +++ b/arch/m68knommu/include/asm/elf.h | |||
diff --git a/include/asm-m68knommu/elia.h b/arch/m68knommu/include/asm/elia.h index e037d4e2de33..e037d4e2de33 100644 --- a/include/asm-m68knommu/elia.h +++ b/arch/m68knommu/include/asm/elia.h | |||
diff --git a/include/asm-m68knommu/emergency-restart.h b/arch/m68knommu/include/asm/emergency-restart.h index 108d8c48e42e..108d8c48e42e 100644 --- a/include/asm-m68knommu/emergency-restart.h +++ b/arch/m68knommu/include/asm/emergency-restart.h | |||
diff --git a/include/asm-m68knommu/entry.h b/arch/m68knommu/include/asm/entry.h index c2553d26273d..c2553d26273d 100644 --- a/include/asm-m68knommu/entry.h +++ b/arch/m68knommu/include/asm/entry.h | |||
diff --git a/include/asm-m68knommu/errno.h b/arch/m68knommu/include/asm/errno.h index 7e8c22b9a5e6..7e8c22b9a5e6 100644 --- a/include/asm-m68knommu/errno.h +++ b/arch/m68knommu/include/asm/errno.h | |||
diff --git a/include/asm-m68knommu/fb.h b/arch/m68knommu/include/asm/fb.h index c7df38030992..c7df38030992 100644 --- a/include/asm-m68knommu/fb.h +++ b/arch/m68knommu/include/asm/fb.h | |||
diff --git a/include/asm-m68knommu/fcntl.h b/arch/m68knommu/include/asm/fcntl.h index f6a552cda4cd..f6a552cda4cd 100644 --- a/include/asm-m68knommu/fcntl.h +++ b/arch/m68knommu/include/asm/fcntl.h | |||
diff --git a/include/asm-m68knommu/flat.h b/arch/m68knommu/include/asm/flat.h index 814b5174a8e0..814b5174a8e0 100644 --- a/include/asm-m68knommu/flat.h +++ b/arch/m68knommu/include/asm/flat.h | |||
diff --git a/include/asm-m68knommu/fpu.h b/arch/m68knommu/include/asm/fpu.h index b16b2e4fca2a..b16b2e4fca2a 100644 --- a/include/asm-m68knommu/fpu.h +++ b/arch/m68knommu/include/asm/fpu.h | |||
diff --git a/include/asm-m68knommu/futex.h b/arch/m68knommu/include/asm/futex.h index 6a332a9f099c..6a332a9f099c 100644 --- a/include/asm-m68knommu/futex.h +++ b/arch/m68knommu/include/asm/futex.h | |||
diff --git a/include/asm-m68knommu/hardirq.h b/arch/m68knommu/include/asm/hardirq.h index bfad28149a49..bfad28149a49 100644 --- a/include/asm-m68knommu/hardirq.h +++ b/arch/m68knommu/include/asm/hardirq.h | |||
diff --git a/include/asm-m68knommu/hw_irq.h b/arch/m68knommu/include/asm/hw_irq.h index f3ec9e5ae049..f3ec9e5ae049 100644 --- a/include/asm-m68knommu/hw_irq.h +++ b/arch/m68knommu/include/asm/hw_irq.h | |||
diff --git a/include/asm-m68knommu/hwtest.h b/arch/m68knommu/include/asm/hwtest.h index 700626a1b1bf..700626a1b1bf 100644 --- a/include/asm-m68knommu/hwtest.h +++ b/arch/m68knommu/include/asm/hwtest.h | |||
diff --git a/include/asm-m68knommu/io.h b/arch/m68knommu/include/asm/io.h index 6adef1ee2082..6adef1ee2082 100644 --- a/include/asm-m68knommu/io.h +++ b/arch/m68knommu/include/asm/io.h | |||
diff --git a/include/asm-m68knommu/ioctl.h b/arch/m68knommu/include/asm/ioctl.h index b279fe06dfe5..b279fe06dfe5 100644 --- a/include/asm-m68knommu/ioctl.h +++ b/arch/m68knommu/include/asm/ioctl.h | |||
diff --git a/include/asm-m68knommu/ioctls.h b/arch/m68knommu/include/asm/ioctls.h index 0b1eb4d85059..0b1eb4d85059 100644 --- a/include/asm-m68knommu/ioctls.h +++ b/arch/m68knommu/include/asm/ioctls.h | |||
diff --git a/include/asm-m68knommu/ipcbuf.h b/arch/m68knommu/include/asm/ipcbuf.h index e4a7be6dd706..e4a7be6dd706 100644 --- a/include/asm-m68knommu/ipcbuf.h +++ b/arch/m68knommu/include/asm/ipcbuf.h | |||
diff --git a/include/asm-m68knommu/irq.h b/arch/m68knommu/include/asm/irq.h index 9373c31ac87d..9373c31ac87d 100644 --- a/include/asm-m68knommu/irq.h +++ b/arch/m68knommu/include/asm/irq.h | |||
diff --git a/include/asm-m68knommu/irq_regs.h b/arch/m68knommu/include/asm/irq_regs.h index 3dd9c0b70270..3dd9c0b70270 100644 --- a/include/asm-m68knommu/irq_regs.h +++ b/arch/m68knommu/include/asm/irq_regs.h | |||
diff --git a/include/asm-m68knommu/kdebug.h b/arch/m68knommu/include/asm/kdebug.h index 6ece1b037665..6ece1b037665 100644 --- a/include/asm-m68knommu/kdebug.h +++ b/arch/m68knommu/include/asm/kdebug.h | |||
diff --git a/include/asm-m68knommu/kmap_types.h b/arch/m68knommu/include/asm/kmap_types.h index bfb6707575d1..bfb6707575d1 100644 --- a/include/asm-m68knommu/kmap_types.h +++ b/arch/m68knommu/include/asm/kmap_types.h | |||
diff --git a/include/asm-m68knommu/linkage.h b/arch/m68knommu/include/asm/linkage.h index c288a19ff489..c288a19ff489 100644 --- a/include/asm-m68knommu/linkage.h +++ b/arch/m68knommu/include/asm/linkage.h | |||
diff --git a/include/asm-m68knommu/local.h b/arch/m68knommu/include/asm/local.h index 84a39c1b86f8..84a39c1b86f8 100644 --- a/include/asm-m68knommu/local.h +++ b/arch/m68knommu/include/asm/local.h | |||
diff --git a/include/asm-m68knommu/m5206sim.h b/arch/m68knommu/include/asm/m5206sim.h index 7e3594dea88b..7e3594dea88b 100644 --- a/include/asm-m68knommu/m5206sim.h +++ b/arch/m68knommu/include/asm/m5206sim.h | |||
diff --git a/include/asm-m68knommu/m520xsim.h b/arch/m68knommu/include/asm/m520xsim.h index 49d016e6391a..49d016e6391a 100644 --- a/include/asm-m68knommu/m520xsim.h +++ b/arch/m68knommu/include/asm/m520xsim.h | |||
diff --git a/include/asm-m68knommu/m523xsim.h b/arch/m68knommu/include/asm/m523xsim.h index bf397313e93f..bf397313e93f 100644 --- a/include/asm-m68knommu/m523xsim.h +++ b/arch/m68knommu/include/asm/m523xsim.h | |||
diff --git a/include/asm-m68knommu/m5249sim.h b/arch/m68knommu/include/asm/m5249sim.h index 366eb8602d2f..366eb8602d2f 100644 --- a/include/asm-m68knommu/m5249sim.h +++ b/arch/m68knommu/include/asm/m5249sim.h | |||
diff --git a/include/asm-m68knommu/m5272sim.h b/arch/m68knommu/include/asm/m5272sim.h index 6217edc21139..6217edc21139 100644 --- a/include/asm-m68knommu/m5272sim.h +++ b/arch/m68knommu/include/asm/m5272sim.h | |||
diff --git a/include/asm-m68knommu/m527xsim.h b/arch/m68knommu/include/asm/m527xsim.h index 1f63ab3fb3e6..1f63ab3fb3e6 100644 --- a/include/asm-m68knommu/m527xsim.h +++ b/arch/m68knommu/include/asm/m527xsim.h | |||
diff --git a/include/asm-m68knommu/m528xsim.h b/arch/m68knommu/include/asm/m528xsim.h index 28bf783a5d6d..28bf783a5d6d 100644 --- a/include/asm-m68knommu/m528xsim.h +++ b/arch/m68knommu/include/asm/m528xsim.h | |||
diff --git a/include/asm-m68knommu/m5307sim.h b/arch/m68knommu/include/asm/m5307sim.h index 5886728409c0..5886728409c0 100644 --- a/include/asm-m68knommu/m5307sim.h +++ b/arch/m68knommu/include/asm/m5307sim.h | |||
diff --git a/include/asm-m68knommu/m532xsim.h b/arch/m68knommu/include/asm/m532xsim.h index 1835fd20a82c..1835fd20a82c 100644 --- a/include/asm-m68knommu/m532xsim.h +++ b/arch/m68knommu/include/asm/m532xsim.h | |||
diff --git a/include/asm-m68knommu/m5407sim.h b/arch/m68knommu/include/asm/m5407sim.h index cc22c4a53005..cc22c4a53005 100644 --- a/include/asm-m68knommu/m5407sim.h +++ b/arch/m68knommu/include/asm/m5407sim.h | |||
diff --git a/include/asm-m68knommu/m68360.h b/arch/m68knommu/include/asm/m68360.h index eb7d39ef2855..eb7d39ef2855 100644 --- a/include/asm-m68knommu/m68360.h +++ b/arch/m68knommu/include/asm/m68360.h | |||
diff --git a/include/asm-m68knommu/m68360_enet.h b/arch/m68knommu/include/asm/m68360_enet.h index c36f4d059203..c36f4d059203 100644 --- a/include/asm-m68knommu/m68360_enet.h +++ b/arch/m68knommu/include/asm/m68360_enet.h | |||
diff --git a/include/asm-m68knommu/m68360_pram.h b/arch/m68knommu/include/asm/m68360_pram.h index e6088bbce93d..e6088bbce93d 100644 --- a/include/asm-m68knommu/m68360_pram.h +++ b/arch/m68knommu/include/asm/m68360_pram.h | |||
diff --git a/include/asm-m68knommu/m68360_quicc.h b/arch/m68knommu/include/asm/m68360_quicc.h index 6d40f4d18e10..6d40f4d18e10 100644 --- a/include/asm-m68knommu/m68360_quicc.h +++ b/arch/m68knommu/include/asm/m68360_quicc.h | |||
diff --git a/include/asm-m68knommu/m68360_regs.h b/arch/m68knommu/include/asm/m68360_regs.h index d57217ca4f27..d57217ca4f27 100644 --- a/include/asm-m68knommu/m68360_regs.h +++ b/arch/m68knommu/include/asm/m68360_regs.h | |||
diff --git a/include/asm-m68knommu/machdep.h b/arch/m68knommu/include/asm/machdep.h index de9f47a51cc2..de9f47a51cc2 100644 --- a/include/asm-m68knommu/machdep.h +++ b/arch/m68knommu/include/asm/machdep.h | |||
diff --git a/include/asm-m68knommu/math-emu.h b/arch/m68knommu/include/asm/math-emu.h index 7e7090517b72..7e7090517b72 100644 --- a/include/asm-m68knommu/math-emu.h +++ b/arch/m68knommu/include/asm/math-emu.h | |||
diff --git a/include/asm-m68knommu/mc146818rtc.h b/arch/m68knommu/include/asm/mc146818rtc.h index 907a0481a140..907a0481a140 100644 --- a/include/asm-m68knommu/mc146818rtc.h +++ b/arch/m68knommu/include/asm/mc146818rtc.h | |||
diff --git a/include/asm-m68knommu/mcfcache.h b/arch/m68knommu/include/asm/mcfcache.h index c042634fadaa..c042634fadaa 100644 --- a/include/asm-m68knommu/mcfcache.h +++ b/arch/m68knommu/include/asm/mcfcache.h | |||
diff --git a/include/asm-m68knommu/mcfdma.h b/arch/m68knommu/include/asm/mcfdma.h index 705c52c79cd8..705c52c79cd8 100644 --- a/include/asm-m68knommu/mcfdma.h +++ b/arch/m68knommu/include/asm/mcfdma.h | |||
diff --git a/include/asm-m68knommu/mcfmbus.h b/arch/m68knommu/include/asm/mcfmbus.h index 319899c47a2c..319899c47a2c 100644 --- a/include/asm-m68knommu/mcfmbus.h +++ b/arch/m68knommu/include/asm/mcfmbus.h | |||
diff --git a/include/asm-m68knommu/mcfne.h b/arch/m68knommu/include/asm/mcfne.h index 431f63aadd0e..431f63aadd0e 100644 --- a/include/asm-m68knommu/mcfne.h +++ b/arch/m68knommu/include/asm/mcfne.h | |||
diff --git a/include/asm-m68knommu/mcfpci.h b/arch/m68knommu/include/asm/mcfpci.h index f1507dd06ec6..f1507dd06ec6 100644 --- a/include/asm-m68knommu/mcfpci.h +++ b/arch/m68knommu/include/asm/mcfpci.h | |||
diff --git a/include/asm-m68knommu/mcfpit.h b/arch/m68knommu/include/asm/mcfpit.h index f570cf64fd29..f570cf64fd29 100644 --- a/include/asm-m68knommu/mcfpit.h +++ b/arch/m68knommu/include/asm/mcfpit.h | |||
diff --git a/include/asm-m68knommu/mcfsim.h b/arch/m68knommu/include/asm/mcfsim.h index da3f2ceff3a4..da3f2ceff3a4 100644 --- a/include/asm-m68knommu/mcfsim.h +++ b/arch/m68knommu/include/asm/mcfsim.h | |||
diff --git a/include/asm-m68knommu/mcfsmc.h b/arch/m68knommu/include/asm/mcfsmc.h index 2d7a4dbd9683..2d7a4dbd9683 100644 --- a/include/asm-m68knommu/mcfsmc.h +++ b/arch/m68knommu/include/asm/mcfsmc.h | |||
diff --git a/include/asm-m68knommu/mcftimer.h b/arch/m68knommu/include/asm/mcftimer.h index 0f90f6d2227a..0f90f6d2227a 100644 --- a/include/asm-m68knommu/mcftimer.h +++ b/arch/m68knommu/include/asm/mcftimer.h | |||
diff --git a/include/asm-m68knommu/mcfuart.h b/arch/m68knommu/include/asm/mcfuart.h index ef2293873612..ef2293873612 100644 --- a/include/asm-m68knommu/mcfuart.h +++ b/arch/m68knommu/include/asm/mcfuart.h | |||
diff --git a/include/asm-m68knommu/mcfwdebug.h b/arch/m68knommu/include/asm/mcfwdebug.h index 27f70e45d700..27f70e45d700 100644 --- a/include/asm-m68knommu/mcfwdebug.h +++ b/arch/m68knommu/include/asm/mcfwdebug.h | |||
diff --git a/include/asm-m68knommu/md.h b/arch/m68knommu/include/asm/md.h index d810c78de5ff..d810c78de5ff 100644 --- a/include/asm-m68knommu/md.h +++ b/arch/m68knommu/include/asm/md.h | |||
diff --git a/include/asm-m68knommu/mman.h b/arch/m68knommu/include/asm/mman.h index 4846c682efed..4846c682efed 100644 --- a/include/asm-m68knommu/mman.h +++ b/arch/m68knommu/include/asm/mman.h | |||
diff --git a/include/asm-m68knommu/mmu.h b/arch/m68knommu/include/asm/mmu.h index 5fa6b68353ba..5fa6b68353ba 100644 --- a/include/asm-m68knommu/mmu.h +++ b/arch/m68knommu/include/asm/mmu.h | |||
diff --git a/include/asm-m68knommu/mmu_context.h b/arch/m68knommu/include/asm/mmu_context.h index 9ccee4278c97..9ccee4278c97 100644 --- a/include/asm-m68knommu/mmu_context.h +++ b/arch/m68knommu/include/asm/mmu_context.h | |||
diff --git a/include/asm-m68knommu/module.h b/arch/m68knommu/include/asm/module.h index 2e45ab50b232..2e45ab50b232 100644 --- a/include/asm-m68knommu/module.h +++ b/arch/m68knommu/include/asm/module.h | |||
diff --git a/include/asm-m68knommu/movs.h b/arch/m68knommu/include/asm/movs.h index 81a16779e833..81a16779e833 100644 --- a/include/asm-m68knommu/movs.h +++ b/arch/m68knommu/include/asm/movs.h | |||
diff --git a/include/asm-m68knommu/msgbuf.h b/arch/m68knommu/include/asm/msgbuf.h index bdfadec4d52d..bdfadec4d52d 100644 --- a/include/asm-m68knommu/msgbuf.h +++ b/arch/m68knommu/include/asm/msgbuf.h | |||
diff --git a/include/asm-m68knommu/mutex.h b/arch/m68knommu/include/asm/mutex.h index 458c1f7fbc18..458c1f7fbc18 100644 --- a/include/asm-m68knommu/mutex.h +++ b/arch/m68knommu/include/asm/mutex.h | |||
diff --git a/include/asm-m68knommu/nettel.h b/arch/m68knommu/include/asm/nettel.h index 0299f6a2deeb..0299f6a2deeb 100644 --- a/include/asm-m68knommu/nettel.h +++ b/arch/m68knommu/include/asm/nettel.h | |||
diff --git a/include/asm-m68knommu/openprom.h b/arch/m68knommu/include/asm/openprom.h index fdba7953ff9f..fdba7953ff9f 100644 --- a/include/asm-m68knommu/openprom.h +++ b/arch/m68knommu/include/asm/openprom.h | |||
diff --git a/include/asm-m68knommu/oplib.h b/arch/m68knommu/include/asm/oplib.h index ce079dc332d9..ce079dc332d9 100644 --- a/include/asm-m68knommu/oplib.h +++ b/arch/m68knommu/include/asm/oplib.h | |||
diff --git a/include/asm-m68knommu/page.h b/arch/m68knommu/include/asm/page.h index 3a1ede4544cb..3a1ede4544cb 100644 --- a/include/asm-m68knommu/page.h +++ b/arch/m68knommu/include/asm/page.h | |||
diff --git a/include/asm-m68knommu/page_offset.h b/arch/m68knommu/include/asm/page_offset.h index d4e73e0ba646..d4e73e0ba646 100644 --- a/include/asm-m68knommu/page_offset.h +++ b/arch/m68knommu/include/asm/page_offset.h | |||
diff --git a/include/asm-m68knommu/param.h b/arch/m68knommu/include/asm/param.h index 6044397adb64..6044397adb64 100644 --- a/include/asm-m68knommu/param.h +++ b/arch/m68knommu/include/asm/param.h | |||
diff --git a/include/asm-m68knommu/pci.h b/arch/m68knommu/include/asm/pci.h index a13f3cc87451..a13f3cc87451 100644 --- a/include/asm-m68knommu/pci.h +++ b/arch/m68knommu/include/asm/pci.h | |||
diff --git a/include/asm-m68knommu/percpu.h b/arch/m68knommu/include/asm/percpu.h index 5de72c327efd..5de72c327efd 100644 --- a/include/asm-m68knommu/percpu.h +++ b/arch/m68knommu/include/asm/percpu.h | |||
diff --git a/include/asm-m68knommu/pgalloc.h b/arch/m68knommu/include/asm/pgalloc.h index d6352f671ec0..d6352f671ec0 100644 --- a/include/asm-m68knommu/pgalloc.h +++ b/arch/m68knommu/include/asm/pgalloc.h | |||
diff --git a/include/asm-m68knommu/pgtable.h b/arch/m68knommu/include/asm/pgtable.h index 46251016e821..46251016e821 100644 --- a/include/asm-m68knommu/pgtable.h +++ b/arch/m68knommu/include/asm/pgtable.h | |||
diff --git a/include/asm-m68knommu/poll.h b/arch/m68knommu/include/asm/poll.h index ee1b6cb549ca..ee1b6cb549ca 100644 --- a/include/asm-m68knommu/poll.h +++ b/arch/m68knommu/include/asm/poll.h | |||
diff --git a/include/asm-m68knommu/posix_types.h b/arch/m68knommu/include/asm/posix_types.h index 6205fb9392a3..6205fb9392a3 100644 --- a/include/asm-m68knommu/posix_types.h +++ b/arch/m68knommu/include/asm/posix_types.h | |||
diff --git a/include/asm-m68knommu/processor.h b/arch/m68knommu/include/asm/processor.h index 91cba18acdd3..91cba18acdd3 100644 --- a/include/asm-m68knommu/processor.h +++ b/arch/m68knommu/include/asm/processor.h | |||
diff --git a/include/asm-m68knommu/ptrace.h b/arch/m68knommu/include/asm/ptrace.h index 8c9194b98548..8c9194b98548 100644 --- a/include/asm-m68knommu/ptrace.h +++ b/arch/m68knommu/include/asm/ptrace.h | |||
diff --git a/include/asm-m68knommu/quicc_simple.h b/arch/m68knommu/include/asm/quicc_simple.h index c3636932d4bc..c3636932d4bc 100644 --- a/include/asm-m68knommu/quicc_simple.h +++ b/arch/m68knommu/include/asm/quicc_simple.h | |||
diff --git a/include/asm-m68knommu/resource.h b/arch/m68knommu/include/asm/resource.h index 7fa63d5ea576..7fa63d5ea576 100644 --- a/include/asm-m68knommu/resource.h +++ b/arch/m68knommu/include/asm/resource.h | |||
diff --git a/include/asm-m68knommu/rtc.h b/arch/m68knommu/include/asm/rtc.h index eaf18ec83c8e..eaf18ec83c8e 100644 --- a/include/asm-m68knommu/rtc.h +++ b/arch/m68knommu/include/asm/rtc.h | |||
diff --git a/include/asm-m68knommu/scatterlist.h b/arch/m68knommu/include/asm/scatterlist.h index afc4788b0d2c..afc4788b0d2c 100644 --- a/include/asm-m68knommu/scatterlist.h +++ b/arch/m68knommu/include/asm/scatterlist.h | |||
diff --git a/include/asm-m68knommu/sections.h b/arch/m68knommu/include/asm/sections.h index dd0ecb98ec08..dd0ecb98ec08 100644 --- a/include/asm-m68knommu/sections.h +++ b/arch/m68knommu/include/asm/sections.h | |||
diff --git a/include/asm-m68knommu/segment.h b/arch/m68knommu/include/asm/segment.h index 42318ebec7ec..42318ebec7ec 100644 --- a/include/asm-m68knommu/segment.h +++ b/arch/m68knommu/include/asm/segment.h | |||
diff --git a/include/asm-m68knommu/sembuf.h b/arch/m68knommu/include/asm/sembuf.h index 3a634f9ecf50..3a634f9ecf50 100644 --- a/include/asm-m68knommu/sembuf.h +++ b/arch/m68knommu/include/asm/sembuf.h | |||
diff --git a/include/asm-m68knommu/setup.h b/arch/m68knommu/include/asm/setup.h index fb86bb2a6078..fb86bb2a6078 100644 --- a/include/asm-m68knommu/setup.h +++ b/arch/m68knommu/include/asm/setup.h | |||
diff --git a/include/asm-m68knommu/shm.h b/arch/m68knommu/include/asm/shm.h index cc8e522d9050..cc8e522d9050 100644 --- a/include/asm-m68knommu/shm.h +++ b/arch/m68knommu/include/asm/shm.h | |||
diff --git a/include/asm-m68knommu/shmbuf.h b/arch/m68knommu/include/asm/shmbuf.h index bc34cf8eefce..bc34cf8eefce 100644 --- a/include/asm-m68knommu/shmbuf.h +++ b/arch/m68knommu/include/asm/shmbuf.h | |||
diff --git a/include/asm-m68knommu/shmparam.h b/arch/m68knommu/include/asm/shmparam.h index d7ee69648ebf..d7ee69648ebf 100644 --- a/include/asm-m68knommu/shmparam.h +++ b/arch/m68knommu/include/asm/shmparam.h | |||
diff --git a/include/asm-m68knommu/sigcontext.h b/arch/m68knommu/include/asm/sigcontext.h index 36c293fc133d..36c293fc133d 100644 --- a/include/asm-m68knommu/sigcontext.h +++ b/arch/m68knommu/include/asm/sigcontext.h | |||
diff --git a/include/asm-m68knommu/siginfo.h b/arch/m68knommu/include/asm/siginfo.h index b18e5f4064ae..b18e5f4064ae 100644 --- a/include/asm-m68knommu/siginfo.h +++ b/arch/m68knommu/include/asm/siginfo.h | |||
diff --git a/include/asm-m68knommu/signal.h b/arch/m68knommu/include/asm/signal.h index 216c08be54a0..216c08be54a0 100644 --- a/include/asm-m68knommu/signal.h +++ b/arch/m68knommu/include/asm/signal.h | |||
diff --git a/include/asm-m68knommu/smp.h b/arch/m68knommu/include/asm/smp.h index 9e9bd7e58922..9e9bd7e58922 100644 --- a/include/asm-m68knommu/smp.h +++ b/arch/m68knommu/include/asm/smp.h | |||
diff --git a/include/asm-m68knommu/socket.h b/arch/m68knommu/include/asm/socket.h index ac5478bf6371..ac5478bf6371 100644 --- a/include/asm-m68knommu/socket.h +++ b/arch/m68knommu/include/asm/socket.h | |||
diff --git a/include/asm-m68knommu/sockios.h b/arch/m68knommu/include/asm/sockios.h index dcc6a8900ce2..dcc6a8900ce2 100644 --- a/include/asm-m68knommu/sockios.h +++ b/arch/m68knommu/include/asm/sockios.h | |||
diff --git a/include/asm-m68knommu/spinlock.h b/arch/m68knommu/include/asm/spinlock.h index 6bb1f06c4781..6bb1f06c4781 100644 --- a/include/asm-m68knommu/spinlock.h +++ b/arch/m68knommu/include/asm/spinlock.h | |||
diff --git a/include/asm-m68knommu/stat.h b/arch/m68knommu/include/asm/stat.h index 3d4b260e7c03..3d4b260e7c03 100644 --- a/include/asm-m68knommu/stat.h +++ b/arch/m68knommu/include/asm/stat.h | |||
diff --git a/include/asm-m68knommu/statfs.h b/arch/m68knommu/include/asm/statfs.h index 2ce99eaf0970..2ce99eaf0970 100644 --- a/include/asm-m68knommu/statfs.h +++ b/arch/m68knommu/include/asm/statfs.h | |||
diff --git a/include/asm-m68knommu/string.h b/arch/m68knommu/include/asm/string.h index af09e17000fc..af09e17000fc 100644 --- a/include/asm-m68knommu/string.h +++ b/arch/m68knommu/include/asm/string.h | |||
diff --git a/include/asm-m68knommu/system.h b/arch/m68knommu/include/asm/system.h index 40f49de69821..40f49de69821 100644 --- a/include/asm-m68knommu/system.h +++ b/arch/m68knommu/include/asm/system.h | |||
diff --git a/include/asm-m68knommu/termbits.h b/arch/m68knommu/include/asm/termbits.h index 05dd6bc27285..05dd6bc27285 100644 --- a/include/asm-m68knommu/termbits.h +++ b/arch/m68knommu/include/asm/termbits.h | |||
diff --git a/include/asm-m68knommu/termios.h b/arch/m68knommu/include/asm/termios.h index e7337881a985..e7337881a985 100644 --- a/include/asm-m68knommu/termios.h +++ b/arch/m68knommu/include/asm/termios.h | |||
diff --git a/include/asm-m68knommu/thread_info.h b/arch/m68knommu/include/asm/thread_info.h index 0c9bc095f3f0..0c9bc095f3f0 100644 --- a/include/asm-m68knommu/thread_info.h +++ b/arch/m68knommu/include/asm/thread_info.h | |||
diff --git a/include/asm-m68knommu/timex.h b/arch/m68knommu/include/asm/timex.h index 109050f3fe91..109050f3fe91 100644 --- a/include/asm-m68knommu/timex.h +++ b/arch/m68knommu/include/asm/timex.h | |||
diff --git a/include/asm-m68knommu/tlb.h b/arch/m68knommu/include/asm/tlb.h index 77a7c51ca299..77a7c51ca299 100644 --- a/include/asm-m68knommu/tlb.h +++ b/arch/m68knommu/include/asm/tlb.h | |||
diff --git a/include/asm-m68knommu/tlbflush.h b/arch/m68knommu/include/asm/tlbflush.h index a470cfb803eb..a470cfb803eb 100644 --- a/include/asm-m68knommu/tlbflush.h +++ b/arch/m68knommu/include/asm/tlbflush.h | |||
diff --git a/include/asm-m68knommu/topology.h b/arch/m68knommu/include/asm/topology.h index ca173e9f26ff..ca173e9f26ff 100644 --- a/include/asm-m68knommu/topology.h +++ b/arch/m68knommu/include/asm/topology.h | |||
diff --git a/include/asm-m68knommu/traps.h b/arch/m68knommu/include/asm/traps.h index d0671e5f8e29..d0671e5f8e29 100644 --- a/include/asm-m68knommu/traps.h +++ b/arch/m68knommu/include/asm/traps.h | |||
diff --git a/include/asm-m68knommu/types.h b/arch/m68knommu/include/asm/types.h index 031238c2d180..031238c2d180 100644 --- a/include/asm-m68knommu/types.h +++ b/arch/m68knommu/include/asm/types.h | |||
diff --git a/include/asm-m68knommu/uaccess.h b/arch/m68knommu/include/asm/uaccess.h index 68bbe9b312f1..68bbe9b312f1 100644 --- a/include/asm-m68knommu/uaccess.h +++ b/arch/m68knommu/include/asm/uaccess.h | |||
diff --git a/include/asm-m68knommu/ucontext.h b/arch/m68knommu/include/asm/ucontext.h index 713a27f901cd..713a27f901cd 100644 --- a/include/asm-m68knommu/ucontext.h +++ b/arch/m68knommu/include/asm/ucontext.h | |||
diff --git a/include/asm-m68knommu/unaligned.h b/arch/m68knommu/include/asm/unaligned.h index eb1ea4cb9a59..eb1ea4cb9a59 100644 --- a/include/asm-m68knommu/unaligned.h +++ b/arch/m68knommu/include/asm/unaligned.h | |||
diff --git a/include/asm-m68knommu/unistd.h b/arch/m68knommu/include/asm/unistd.h index 4ba98b9c5d79..4ba98b9c5d79 100644 --- a/include/asm-m68knommu/unistd.h +++ b/arch/m68knommu/include/asm/unistd.h | |||
diff --git a/include/asm-m68knommu/user.h b/arch/m68knommu/include/asm/user.h index a5a555b761c4..a5a555b761c4 100644 --- a/include/asm-m68knommu/user.h +++ b/arch/m68knommu/include/asm/user.h | |||
diff --git a/arch/powerpc/.gitignore b/arch/powerpc/.gitignore deleted file mode 100644 index a1a869c8c840..000000000000 --- a/arch/powerpc/.gitignore +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | include | ||
diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig index ea3e541ac74f..45ffd8e542f4 100644 --- a/arch/powerpc/platforms/iseries/Kconfig +++ b/arch/powerpc/platforms/iseries/Kconfig | |||
| @@ -7,15 +7,6 @@ config PPC_ISERIES | |||
| 7 | menu "iSeries device drivers" | 7 | menu "iSeries device drivers" |
| 8 | depends on PPC_ISERIES | 8 | depends on PPC_ISERIES |
| 9 | 9 | ||
| 10 | config VIOCONS | ||
| 11 | bool "iSeries Virtual Console Support (Obsolete)" | ||
| 12 | depends on !HVC_ISERIES | ||
| 13 | default n | ||
| 14 | help | ||
| 15 | This is the old virtual console driver for legacy iSeries. | ||
| 16 | You should use the iSeries Hypervisor Virtual Console | ||
| 17 | support instead. | ||
| 18 | |||
| 19 | config VIODASD | 10 | config VIODASD |
| 20 | tristate "iSeries Virtual I/O disk support" | 11 | tristate "iSeries Virtual I/O disk support" |
| 21 | help | 12 | help |
| @@ -38,5 +29,5 @@ endmenu | |||
| 38 | 29 | ||
| 39 | config VIOPATH | 30 | config VIOPATH |
| 40 | bool | 31 | bool |
| 41 | depends on VIOCONS || VIODASD || VIOCD || VIOTAPE || ISERIES_VETH | 32 | depends on VIODASD || VIOCD || VIOTAPE || ISERIES_VETH |
| 42 | default y | 33 | default y |
diff --git a/arch/sh/include/asm/sh_eth.h b/arch/sh/include/asm/sh_eth.h new file mode 100644 index 000000000000..bb832584f3c1 --- /dev/null +++ b/arch/sh/include/asm/sh_eth.h | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | #ifndef __ASM_SH_ETH_H__ | ||
| 2 | #define __ASM_SH_ETH_H__ | ||
| 3 | |||
| 4 | enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN}; | ||
| 5 | |||
| 6 | struct sh_eth_plat_data { | ||
| 7 | int phy; | ||
| 8 | int edmac_endian; | ||
| 9 | }; | ||
| 10 | |||
| 11 | #endif | ||
diff --git a/arch/sparc/include/asm/ebus_32.h b/arch/sparc/include/asm/ebus_32.h index 29cb7dfc6b79..f91f0b267ce1 100644 --- a/arch/sparc/include/asm/ebus_32.h +++ b/arch/sparc/include/asm/ebus_32.h | |||
| @@ -12,9 +12,9 @@ | |||
| 12 | #ifndef _LINUX_IOPORT_H | 12 | #ifndef _LINUX_IOPORT_H |
| 13 | #include <linux/ioport.h> | 13 | #include <linux/ioport.h> |
| 14 | #endif | 14 | #endif |
| 15 | #include <linux/of_device.h> | ||
| 15 | #include <asm/oplib.h> | 16 | #include <asm/oplib.h> |
| 16 | #include <asm/prom.h> | 17 | #include <asm/prom.h> |
| 17 | #include <asm/of_device.h> | ||
| 18 | 18 | ||
| 19 | struct linux_ebus_child { | 19 | struct linux_ebus_child { |
| 20 | struct linux_ebus_child *next; | 20 | struct linux_ebus_child *next; |
diff --git a/arch/sparc/include/asm/ebus_64.h b/arch/sparc/include/asm/ebus_64.h index fcc62b97ced5..14c6a111f60c 100644 --- a/arch/sparc/include/asm/ebus_64.h +++ b/arch/sparc/include/asm/ebus_64.h | |||
| @@ -8,9 +8,10 @@ | |||
| 8 | #ifndef __SPARC64_EBUS_H | 8 | #ifndef __SPARC64_EBUS_H |
| 9 | #define __SPARC64_EBUS_H | 9 | #define __SPARC64_EBUS_H |
| 10 | 10 | ||
| 11 | #include <linux/of_device.h> | ||
| 12 | |||
| 11 | #include <asm/oplib.h> | 13 | #include <asm/oplib.h> |
| 12 | #include <asm/prom.h> | 14 | #include <asm/prom.h> |
| 13 | #include <asm/of_device.h> | ||
| 14 | 15 | ||
| 15 | struct linux_ebus_child { | 16 | struct linux_ebus_child { |
| 16 | struct linux_ebus_child *next; | 17 | struct linux_ebus_child *next; |
diff --git a/arch/sparc/include/asm/of_platform.h b/arch/sparc/include/asm/of_platform.h index 93a262c44022..2348ab90a57c 100644 --- a/arch/sparc/include/asm/of_platform.h +++ b/arch/sparc/include/asm/of_platform.h | |||
| @@ -13,9 +13,6 @@ | |||
| 13 | * | 13 | * |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /* This is just here during the transition */ | ||
| 17 | #include <linux/of_platform.h> | ||
| 18 | |||
| 19 | extern struct bus_type ebus_bus_type; | 16 | extern struct bus_type ebus_bus_type; |
| 20 | extern struct bus_type sbus_bus_type; | 17 | extern struct bus_type sbus_bus_type; |
| 21 | 18 | ||
diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h index 7818b2523b8d..d9830621c906 100644 --- a/arch/sparc/include/asm/parport.h +++ b/arch/sparc/include/asm/parport.h | |||
| @@ -6,9 +6,10 @@ | |||
| 6 | #ifndef _ASM_SPARC64_PARPORT_H | 6 | #ifndef _ASM_SPARC64_PARPORT_H |
| 7 | #define _ASM_SPARC64_PARPORT_H 1 | 7 | #define _ASM_SPARC64_PARPORT_H 1 |
| 8 | 8 | ||
| 9 | #include <linux/of_device.h> | ||
| 10 | |||
| 9 | #include <asm/ebus.h> | 11 | #include <asm/ebus.h> |
| 10 | #include <asm/ns87303.h> | 12 | #include <asm/ns87303.h> |
| 11 | #include <asm/of_device.h> | ||
| 12 | #include <asm/prom.h> | 13 | #include <asm/prom.h> |
| 13 | 14 | ||
| 14 | #define PARPORT_PC_MAX_PORTS PARPORT_MAX | 15 | #define PARPORT_PC_MAX_PORTS PARPORT_MAX |
diff --git a/arch/sparc/include/asm/sbus_32.h b/arch/sparc/include/asm/sbus_32.h index 77b5d3aadc99..a7b4fa21931d 100644 --- a/arch/sparc/include/asm/sbus_32.h +++ b/arch/sparc/include/asm/sbus_32.h | |||
| @@ -9,10 +9,10 @@ | |||
| 9 | 9 | ||
| 10 | #include <linux/dma-mapping.h> | 10 | #include <linux/dma-mapping.h> |
| 11 | #include <linux/ioport.h> | 11 | #include <linux/ioport.h> |
| 12 | #include <linux/of_device.h> | ||
| 12 | 13 | ||
| 13 | #include <asm/oplib.h> | 14 | #include <asm/oplib.h> |
| 14 | #include <asm/prom.h> | 15 | #include <asm/prom.h> |
| 15 | #include <asm/of_device.h> | ||
| 16 | #include <asm/scatterlist.h> | 16 | #include <asm/scatterlist.h> |
| 17 | 17 | ||
| 18 | /* We scan which devices are on the SBus using the PROM node device | 18 | /* We scan which devices are on the SBus using the PROM node device |
diff --git a/arch/sparc/include/asm/sbus_64.h b/arch/sparc/include/asm/sbus_64.h index 0e16b6dd7e96..b606c14343fb 100644 --- a/arch/sparc/include/asm/sbus_64.h +++ b/arch/sparc/include/asm/sbus_64.h | |||
| @@ -8,10 +8,10 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/dma-mapping.h> | 9 | #include <linux/dma-mapping.h> |
| 10 | #include <linux/ioport.h> | 10 | #include <linux/ioport.h> |
| 11 | #include <linux/of_device.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/oplib.h> | 13 | #include <asm/oplib.h> |
| 13 | #include <asm/prom.h> | 14 | #include <asm/prom.h> |
| 14 | #include <asm/of_device.h> | ||
| 15 | #include <asm/iommu.h> | 15 | #include <asm/iommu.h> |
| 16 | #include <asm/scatterlist.h> | 16 | #include <asm/scatterlist.h> |
| 17 | 17 | ||
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 487960919f1f..2a8a847764d8 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c | |||
| @@ -36,12 +36,12 @@ | |||
| 36 | #include <linux/pci.h> /* struct pci_dev */ | 36 | #include <linux/pci.h> /* struct pci_dev */ |
| 37 | #include <linux/proc_fs.h> | 37 | #include <linux/proc_fs.h> |
| 38 | #include <linux/scatterlist.h> | 38 | #include <linux/scatterlist.h> |
| 39 | #include <linux/of_device.h> | ||
| 39 | 40 | ||
| 40 | #include <asm/io.h> | 41 | #include <asm/io.h> |
| 41 | #include <asm/vaddrs.h> | 42 | #include <asm/vaddrs.h> |
| 42 | #include <asm/oplib.h> | 43 | #include <asm/oplib.h> |
| 43 | #include <asm/prom.h> | 44 | #include <asm/prom.h> |
| 44 | #include <asm/of_device.h> | ||
| 45 | #include <asm/sbus.h> | 45 | #include <asm/sbus.h> |
| 46 | #include <asm/page.h> | 46 | #include <asm/page.h> |
| 47 | #include <asm/pgalloc.h> | 47 | #include <asm/pgalloc.h> |
diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c index ab3dd0b257d3..0762f5db1924 100644 --- a/arch/sparc/kernel/time.c +++ b/arch/sparc/kernel/time.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <linux/pci.h> | 28 | #include <linux/pci.h> |
| 29 | #include <linux/ioport.h> | 29 | #include <linux/ioport.h> |
| 30 | #include <linux/profile.h> | 30 | #include <linux/profile.h> |
| 31 | #include <linux/of_device.h> | ||
| 31 | 32 | ||
| 32 | #include <asm/oplib.h> | 33 | #include <asm/oplib.h> |
| 33 | #include <asm/timer.h> | 34 | #include <asm/timer.h> |
| @@ -40,7 +41,6 @@ | |||
| 40 | #include <asm/sun4paddr.h> | 41 | #include <asm/sun4paddr.h> |
| 41 | #include <asm/page.h> | 42 | #include <asm/page.h> |
| 42 | #include <asm/pcic.h> | 43 | #include <asm/pcic.h> |
| 43 | #include <asm/of_device.h> | ||
| 44 | #include <asm/irq_regs.h> | 44 | #include <asm/irq_regs.h> |
| 45 | 45 | ||
| 46 | #include "irq.h" | 46 | #include "irq.h" |
diff --git a/arch/sparc64/kernel/auxio.c b/arch/sparc64/kernel/auxio.c index c55f0293eacd..dd5c7bf87619 100644 --- a/arch/sparc64/kernel/auxio.c +++ b/arch/sparc64/kernel/auxio.c | |||
| @@ -9,9 +9,9 @@ | |||
| 9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/ioport.h> | 11 | #include <linux/ioport.h> |
| 12 | #include <linux/of_device.h> | ||
| 12 | 13 | ||
| 13 | #include <asm/prom.h> | 14 | #include <asm/prom.h> |
| 14 | #include <asm/of_device.h> | ||
| 15 | #include <asm/io.h> | 15 | #include <asm/io.h> |
| 16 | #include <asm/auxio.h> | 16 | #include <asm/auxio.h> |
| 17 | 17 | ||
diff --git a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c index 4d58d7ce708d..60d36d142559 100644 --- a/arch/sparc64/kernel/ebus.c +++ b/arch/sparc64/kernel/ebus.c | |||
| @@ -14,13 +14,13 @@ | |||
| 14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
| 16 | #include <linux/pci.h> | 16 | #include <linux/pci.h> |
| 17 | #include <linux/of_device.h> | ||
| 17 | 18 | ||
| 18 | #include <asm/system.h> | 19 | #include <asm/system.h> |
| 19 | #include <asm/page.h> | 20 | #include <asm/page.h> |
| 20 | #include <asm/ebus.h> | 21 | #include <asm/ebus.h> |
| 21 | #include <asm/oplib.h> | 22 | #include <asm/oplib.h> |
| 22 | #include <asm/prom.h> | 23 | #include <asm/prom.h> |
| 23 | #include <asm/of_device.h> | ||
| 24 | #include <asm/bpp.h> | 24 | #include <asm/bpp.h> |
| 25 | #include <asm/irq.h> | 25 | #include <asm/irq.h> |
| 26 | #include <asm/io.h> | 26 | #include <asm/io.h> |
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c index 19fa621d6a60..09a5ec200c61 100644 --- a/arch/sparc64/kernel/pci_common.c +++ b/arch/sparc64/kernel/pci_common.c | |||
| @@ -8,9 +8,9 @@ | |||
| 8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
| 9 | #include <linux/pci.h> | 9 | #include <linux/pci.h> |
| 10 | #include <linux/device.h> | 10 | #include <linux/device.h> |
| 11 | #include <linux/of_device.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/prom.h> | 13 | #include <asm/prom.h> |
| 13 | #include <asm/of_device.h> | ||
| 14 | #include <asm/oplib.h> | 14 | #include <asm/oplib.h> |
| 15 | 15 | ||
| 16 | #include "pci_impl.h" | 16 | #include "pci_impl.h" |
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c index 994dbe0603da..ef5fe29202c2 100644 --- a/arch/sparc64/kernel/pci_psycho.c +++ b/arch/sparc64/kernel/pci_psycho.c | |||
| @@ -11,12 +11,12 @@ | |||
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/of_device.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/iommu.h> | 16 | #include <asm/iommu.h> |
| 16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
| 17 | #include <asm/starfire.h> | 18 | #include <asm/starfire.h> |
| 18 | #include <asm/prom.h> | 19 | #include <asm/prom.h> |
| 19 | #include <asm/of_device.h> | ||
| 20 | #include <asm/oplib.h> | 20 | #include <asm/oplib.h> |
| 21 | 21 | ||
| 22 | #include "pci_impl.h" | 22 | #include "pci_impl.h" |
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c index 4c34195baf37..ade5184e75d1 100644 --- a/arch/sparc64/kernel/pci_sabre.c +++ b/arch/sparc64/kernel/pci_sabre.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/of_device.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/apb.h> | 16 | #include <asm/apb.h> |
| 16 | #include <asm/iommu.h> | 17 | #include <asm/iommu.h> |
| @@ -18,7 +19,6 @@ | |||
| 18 | #include <asm/smp.h> | 19 | #include <asm/smp.h> |
| 19 | #include <asm/oplib.h> | 20 | #include <asm/oplib.h> |
| 20 | #include <asm/prom.h> | 21 | #include <asm/prom.h> |
| 21 | #include <asm/of_device.h> | ||
| 22 | 22 | ||
| 23 | #include "pci_impl.h" | 23 | #include "pci_impl.h" |
| 24 | #include "iommu_common.h" | 24 | #include "iommu_common.h" |
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c index 615edd9c8e2a..9248c6737f0e 100644 --- a/arch/sparc64/kernel/pci_schizo.c +++ b/arch/sparc64/kernel/pci_schizo.c | |||
| @@ -9,13 +9,13 @@ | |||
| 9 | #include <linux/init.h> | 9 | #include <linux/init.h> |
| 10 | #include <linux/slab.h> | 10 | #include <linux/slab.h> |
| 11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/of_device.h> | ||
| 12 | 13 | ||
| 13 | #include <asm/iommu.h> | 14 | #include <asm/iommu.h> |
| 14 | #include <asm/irq.h> | 15 | #include <asm/irq.h> |
| 15 | #include <asm/upa.h> | 16 | #include <asm/upa.h> |
| 16 | #include <asm/pstate.h> | 17 | #include <asm/pstate.h> |
| 17 | #include <asm/prom.h> | 18 | #include <asm/prom.h> |
| 18 | #include <asm/of_device.h> | ||
| 19 | #include <asm/oplib.h> | 19 | #include <asm/oplib.h> |
| 20 | 20 | ||
| 21 | #include "pci_impl.h" | 21 | #include "pci_impl.h" |
diff --git a/arch/sparc64/kernel/power.c b/arch/sparc64/kernel/power.c index eae8ca2a6ba5..3bb987a6d03c 100644 --- a/arch/sparc64/kernel/power.c +++ b/arch/sparc64/kernel/power.c | |||
| @@ -13,11 +13,11 @@ | |||
| 13 | #include <linux/pm.h> | 13 | #include <linux/pm.h> |
| 14 | #include <linux/syscalls.h> | 14 | #include <linux/syscalls.h> |
| 15 | #include <linux/reboot.h> | 15 | #include <linux/reboot.h> |
| 16 | #include <linux/of_device.h> | ||
| 16 | 17 | ||
| 17 | #include <asm/system.h> | 18 | #include <asm/system.h> |
| 18 | #include <asm/auxio.h> | 19 | #include <asm/auxio.h> |
| 19 | #include <asm/prom.h> | 20 | #include <asm/prom.h> |
| 20 | #include <asm/of_device.h> | ||
| 21 | #include <asm/io.h> | 21 | #include <asm/io.h> |
| 22 | #include <asm/sstate.h> | 22 | #include <asm/sstate.h> |
| 23 | #include <asm/reboot.h> | 23 | #include <asm/reboot.h> |
diff --git a/arch/sparc64/kernel/prom.c b/arch/sparc64/kernel/prom.c index ed03a18d3b36..3c048ac4e638 100644 --- a/arch/sparc64/kernel/prom.c +++ b/arch/sparc64/kernel/prom.c | |||
| @@ -21,9 +21,9 @@ | |||
| 21 | #include <linux/mm.h> | 21 | #include <linux/mm.h> |
| 22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
| 23 | #include <linux/lmb.h> | 23 | #include <linux/lmb.h> |
| 24 | #include <linux/of_device.h> | ||
| 24 | 25 | ||
| 25 | #include <asm/prom.h> | 26 | #include <asm/prom.h> |
| 26 | #include <asm/of_device.h> | ||
| 27 | #include <asm/oplib.h> | 27 | #include <asm/oplib.h> |
| 28 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| 29 | #include <asm/asi.h> | 29 | #include <asm/asi.h> |
diff --git a/arch/sparc64/kernel/stacktrace.c b/arch/sparc64/kernel/stacktrace.c index b3e3737750d8..e9d7f0660f2e 100644 --- a/arch/sparc64/kernel/stacktrace.c +++ b/arch/sparc64/kernel/stacktrace.c | |||
| @@ -26,13 +26,15 @@ void save_stack_trace(struct stack_trace *trace) | |||
| 26 | 26 | ||
| 27 | /* Bogus frame pointer? */ | 27 | /* Bogus frame pointer? */ |
| 28 | if (fp < (thread_base + sizeof(struct thread_info)) || | 28 | if (fp < (thread_base + sizeof(struct thread_info)) || |
| 29 | fp >= (thread_base + THREAD_SIZE)) | 29 | fp > (thread_base + THREAD_SIZE - sizeof(struct sparc_stackf))) |
| 30 | break; | 30 | break; |
| 31 | 31 | ||
| 32 | sf = (struct sparc_stackf *) fp; | 32 | sf = (struct sparc_stackf *) fp; |
| 33 | regs = (struct pt_regs *) (sf + 1); | 33 | regs = (struct pt_regs *) (sf + 1); |
| 34 | 34 | ||
| 35 | if ((regs->magic & ~0x1ff) == PT_REGS_MAGIC) { | 35 | if (((unsigned long)regs <= |
| 36 | (thread_base + THREAD_SIZE - sizeof(*regs))) && | ||
| 37 | (regs->magic & ~0x1ff) == PT_REGS_MAGIC) { | ||
| 36 | if (!(regs->tstate & TSTATE_PRIV)) | 38 | if (!(regs->tstate & TSTATE_PRIV)) |
| 37 | break; | 39 | break; |
| 38 | pc = regs->tpc; | 40 | pc = regs->tpc; |
diff --git a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c index 97b77fb5c50e..3d118531baff 100644 --- a/arch/sparc64/kernel/sys_sparc32.c +++ b/arch/sparc64/kernel/sys_sparc32.c | |||
| @@ -58,182 +58,6 @@ | |||
| 58 | #include <asm/mmu_context.h> | 58 | #include <asm/mmu_context.h> |
| 59 | #include <asm/compat_signal.h> | 59 | #include <asm/compat_signal.h> |
| 60 | 60 | ||
| 61 | asmlinkage long sys32_chown16(const char __user * filename, u16 user, u16 group) | ||
| 62 | { | ||
| 63 | return sys_chown(filename, low2highuid(user), low2highgid(group)); | ||
| 64 | } | ||
| 65 | |||
| 66 | asmlinkage long sys32_lchown16(const char __user * filename, u16 user, u16 group) | ||
| 67 | { | ||
| 68 | return sys_lchown(filename, low2highuid(user), low2highgid(group)); | ||
| 69 | } | ||
| 70 | |||
| 71 | asmlinkage long sys32_fchown16(unsigned int fd, u16 user, u16 group) | ||
| 72 | { | ||
| 73 | return sys_fchown(fd, low2highuid(user), low2highgid(group)); | ||
| 74 | } | ||
| 75 | |||
| 76 | asmlinkage long sys32_setregid16(u16 rgid, u16 egid) | ||
| 77 | { | ||
| 78 | return sys_setregid(low2highgid(rgid), low2highgid(egid)); | ||
| 79 | } | ||
| 80 | |||
| 81 | asmlinkage long sys32_setgid16(u16 gid) | ||
| 82 | { | ||
| 83 | return sys_setgid((gid_t)gid); | ||
| 84 | } | ||
| 85 | |||
| 86 | asmlinkage long sys32_setreuid16(u16 ruid, u16 euid) | ||
| 87 | { | ||
| 88 | return sys_setreuid(low2highuid(ruid), low2highuid(euid)); | ||
| 89 | } | ||
| 90 | |||
| 91 | asmlinkage long sys32_setuid16(u16 uid) | ||
| 92 | { | ||
| 93 | return sys_setuid((uid_t)uid); | ||
| 94 | } | ||
| 95 | |||
| 96 | asmlinkage long sys32_setresuid16(u16 ruid, u16 euid, u16 suid) | ||
| 97 | { | ||
| 98 | return sys_setresuid(low2highuid(ruid), low2highuid(euid), | ||
| 99 | low2highuid(suid)); | ||
| 100 | } | ||
| 101 | |||
| 102 | asmlinkage long sys32_getresuid16(u16 __user *ruid, u16 __user *euid, u16 __user *suid) | ||
| 103 | { | ||
| 104 | int retval; | ||
| 105 | |||
| 106 | if (!(retval = put_user(high2lowuid(current->uid), ruid)) && | ||
| 107 | !(retval = put_user(high2lowuid(current->euid), euid))) | ||
| 108 | retval = put_user(high2lowuid(current->suid), suid); | ||
| 109 | |||
| 110 | return retval; | ||
| 111 | } | ||
| 112 | |||
| 113 | asmlinkage long sys32_setresgid16(u16 rgid, u16 egid, u16 sgid) | ||
| 114 | { | ||
| 115 | return sys_setresgid(low2highgid(rgid), low2highgid(egid), | ||
| 116 | low2highgid(sgid)); | ||
| 117 | } | ||
| 118 | |||
| 119 | asmlinkage long sys32_getresgid16(u16 __user *rgid, u16 __user *egid, u16 __user *sgid) | ||
| 120 | { | ||
| 121 | int retval; | ||
| 122 | |||
| 123 | if (!(retval = put_user(high2lowgid(current->gid), rgid)) && | ||
| 124 | !(retval = put_user(high2lowgid(current->egid), egid))) | ||
| 125 | retval = put_user(high2lowgid(current->sgid), sgid); | ||
| 126 | |||
| 127 | return retval; | ||
| 128 | } | ||
| 129 | |||
| 130 | asmlinkage long sys32_setfsuid16(u16 uid) | ||
| 131 | { | ||
| 132 | return sys_setfsuid((uid_t)uid); | ||
| 133 | } | ||
| 134 | |||
| 135 | asmlinkage long sys32_setfsgid16(u16 gid) | ||
| 136 | { | ||
| 137 | return sys_setfsgid((gid_t)gid); | ||
| 138 | } | ||
| 139 | |||
| 140 | static int groups16_to_user(u16 __user *grouplist, struct group_info *group_info) | ||
| 141 | { | ||
| 142 | int i; | ||
| 143 | u16 group; | ||
| 144 | |||
| 145 | for (i = 0; i < group_info->ngroups; i++) { | ||
| 146 | group = (u16)GROUP_AT(group_info, i); | ||
| 147 | if (put_user(group, grouplist+i)) | ||
| 148 | return -EFAULT; | ||
| 149 | } | ||
| 150 | |||
| 151 | return 0; | ||
| 152 | } | ||
| 153 | |||
| 154 | static int groups16_from_user(struct group_info *group_info, u16 __user *grouplist) | ||
| 155 | { | ||
| 156 | int i; | ||
| 157 | u16 group; | ||
| 158 | |||
| 159 | for (i = 0; i < group_info->ngroups; i++) { | ||
| 160 | if (get_user(group, grouplist+i)) | ||
| 161 | return -EFAULT; | ||
| 162 | GROUP_AT(group_info, i) = (gid_t)group; | ||
| 163 | } | ||
| 164 | |||
| 165 | return 0; | ||
| 166 | } | ||
| 167 | |||
| 168 | asmlinkage long sys32_getgroups16(int gidsetsize, u16 __user *grouplist) | ||
| 169 | { | ||
| 170 | int i; | ||
| 171 | |||
| 172 | if (gidsetsize < 0) | ||
| 173 | return -EINVAL; | ||
| 174 | |||
| 175 | get_group_info(current->group_info); | ||
| 176 | i = current->group_info->ngroups; | ||
| 177 | if (gidsetsize) { | ||
| 178 | if (i > gidsetsize) { | ||
| 179 | i = -EINVAL; | ||
| 180 | goto out; | ||
| 181 | } | ||
| 182 | if (groups16_to_user(grouplist, current->group_info)) { | ||
| 183 | i = -EFAULT; | ||
| 184 | goto out; | ||
| 185 | } | ||
| 186 | } | ||
| 187 | out: | ||
| 188 | put_group_info(current->group_info); | ||
| 189 | return i; | ||
| 190 | } | ||
| 191 | |||
| 192 | asmlinkage long sys32_setgroups16(int gidsetsize, u16 __user *grouplist) | ||
| 193 | { | ||
| 194 | struct group_info *group_info; | ||
| 195 | int retval; | ||
| 196 | |||
| 197 | if (!capable(CAP_SETGID)) | ||
| 198 | return -EPERM; | ||
| 199 | if ((unsigned)gidsetsize > NGROUPS_MAX) | ||
| 200 | return -EINVAL; | ||
| 201 | |||
| 202 | group_info = groups_alloc(gidsetsize); | ||
| 203 | if (!group_info) | ||
| 204 | return -ENOMEM; | ||
| 205 | retval = groups16_from_user(group_info, grouplist); | ||
| 206 | if (retval) { | ||
| 207 | put_group_info(group_info); | ||
| 208 | return retval; | ||
| 209 | } | ||
| 210 | |||
| 211 | retval = set_current_groups(group_info); | ||
| 212 | put_group_info(group_info); | ||
| 213 | |||
| 214 | return retval; | ||
| 215 | } | ||
| 216 | |||
| 217 | asmlinkage long sys32_getuid16(void) | ||
| 218 | { | ||
| 219 | return high2lowuid(current->uid); | ||
| 220 | } | ||
| 221 | |||
| 222 | asmlinkage long sys32_geteuid16(void) | ||
| 223 | { | ||
| 224 | return high2lowuid(current->euid); | ||
| 225 | } | ||
| 226 | |||
| 227 | asmlinkage long sys32_getgid16(void) | ||
| 228 | { | ||
| 229 | return high2lowgid(current->gid); | ||
| 230 | } | ||
| 231 | |||
| 232 | asmlinkage long sys32_getegid16(void) | ||
| 233 | { | ||
| 234 | return high2lowgid(current->egid); | ||
| 235 | } | ||
| 236 | |||
| 237 | /* 32-bit timeval and related flotsam. */ | 61 | /* 32-bit timeval and related flotsam. */ |
| 238 | 62 | ||
| 239 | static inline long put_tv32(struct compat_timeval __user *o, struct timeval *i) | 63 | static inline long put_tv32(struct compat_timeval __user *o, struct timeval *i) |
diff --git a/arch/sparc64/kernel/systbls.S b/arch/sparc64/kernel/systbls.S index 1095bf4c5100..0fdbf3ba956e 100644 --- a/arch/sparc64/kernel/systbls.S +++ b/arch/sparc64/kernel/systbls.S | |||
| @@ -20,21 +20,21 @@ | |||
| 20 | sys_call_table32: | 20 | sys_call_table32: |
| 21 | /*0*/ .word sys_restart_syscall, sys32_exit, sys_fork, sys_read, sys_write | 21 | /*0*/ .word sys_restart_syscall, sys32_exit, sys_fork, sys_read, sys_write |
| 22 | /*5*/ .word sys32_open, sys_close, sys32_wait4, sys32_creat, sys_link | 22 | /*5*/ .word sys32_open, sys_close, sys32_wait4, sys32_creat, sys_link |
| 23 | /*10*/ .word sys_unlink, sunos_execv, sys_chdir, sys32_chown16, sys32_mknod | 23 | /*10*/ .word sys_unlink, sunos_execv, sys_chdir, sys_chown16, sys32_mknod |
| 24 | /*15*/ .word sys_chmod, sys32_lchown16, sparc_brk, sys32_perfctr, sys32_lseek | 24 | /*15*/ .word sys_chmod, sys_lchown16, sparc_brk, sys32_perfctr, sys32_lseek |
| 25 | /*20*/ .word sys_getpid, sys_capget, sys_capset, sys32_setuid16, sys32_getuid16 | 25 | /*20*/ .word sys_getpid, sys_capget, sys_capset, sys_setuid16, sys_getuid16 |
| 26 | /*25*/ .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, sys32_sigaltstack, sys32_pause | 26 | /*25*/ .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, sys32_sigaltstack, sys32_pause |
| 27 | /*30*/ .word compat_sys_utime, sys_lchown, sys_fchown, sys32_access, sys32_nice | 27 | /*30*/ .word compat_sys_utime, sys_lchown, sys_fchown, sys32_access, sys32_nice |
| 28 | .word sys_chown, sys_sync, sys32_kill, compat_sys_newstat, sys32_sendfile | 28 | .word sys_chown, sys_sync, sys32_kill, compat_sys_newstat, sys32_sendfile |
| 29 | /*40*/ .word compat_sys_newlstat, sys_dup, sys_pipe, compat_sys_times, sys_getuid | 29 | /*40*/ .word compat_sys_newlstat, sys_dup, sys_pipe, compat_sys_times, sys_getuid |
| 30 | .word sys32_umount, sys32_setgid16, sys32_getgid16, sys32_signal, sys32_geteuid16 | 30 | .word sys32_umount, sys_setgid16, sys_getgid16, sys32_signal, sys_geteuid16 |
| 31 | /*50*/ .word sys32_getegid16, sys_acct, sys_nis_syscall, sys_getgid, compat_sys_ioctl | 31 | /*50*/ .word sys_getegid16, sys_acct, sys_nis_syscall, sys_getgid, compat_sys_ioctl |
| 32 | .word sys32_reboot, sys32_mmap2, sys_symlink, sys32_readlink, sys32_execve | 32 | .word sys32_reboot, sys32_mmap2, sys_symlink, sys32_readlink, sys32_execve |
| 33 | /*60*/ .word sys32_umask, sys_chroot, compat_sys_newfstat, compat_sys_fstat64, sys_getpagesize | 33 | /*60*/ .word sys32_umask, sys_chroot, compat_sys_newfstat, compat_sys_fstat64, sys_getpagesize |
| 34 | .word sys32_msync, sys_vfork, sys32_pread64, sys32_pwrite64, sys_geteuid | 34 | .word sys32_msync, sys_vfork, sys32_pread64, sys32_pwrite64, sys_geteuid |
| 35 | /*70*/ .word sys_getegid, sys_mmap, sys_setreuid, sys_munmap, sys_mprotect | 35 | /*70*/ .word sys_getegid, sys_mmap, sys_setreuid, sys_munmap, sys_mprotect |
| 36 | .word sys_madvise, sys_vhangup, sys32_truncate64, sys_mincore, sys32_getgroups16 | 36 | .word sys_madvise, sys_vhangup, sys32_truncate64, sys_mincore, sys_getgroups16 |
| 37 | /*80*/ .word sys32_setgroups16, sys_getpgrp, sys32_setgroups, sys32_setitimer, sys32_ftruncate64 | 37 | /*80*/ .word sys_setgroups16, sys_getpgrp, sys32_setgroups, sys32_setitimer, sys32_ftruncate64 |
| 38 | .word sys32_swapon, sys32_getitimer, sys_setuid, sys32_sethostname, sys_setgid | 38 | .word sys32_swapon, sys32_getitimer, sys_setuid, sys32_sethostname, sys_setgid |
| 39 | /*90*/ .word sys_dup2, sys_setfsuid, compat_sys_fcntl, sys32_select, sys_setfsgid | 39 | /*90*/ .word sys_dup2, sys_setfsuid, compat_sys_fcntl, sys32_select, sys_setfsgid |
| 40 | .word sys_fsync, sys32_setpriority, sys_nis_syscall, sys_nis_syscall, sys_nis_syscall | 40 | .word sys_fsync, sys32_setpriority, sys_nis_syscall, sys_nis_syscall, sys_nis_syscall |
| @@ -42,8 +42,8 @@ sys_call_table32: | |||
| 42 | .word compat_sys_rt_sigtimedwait, sys32_rt_sigqueueinfo, compat_sys_rt_sigsuspend, sys_setresuid, sys_getresuid | 42 | .word compat_sys_rt_sigtimedwait, sys32_rt_sigqueueinfo, compat_sys_rt_sigsuspend, sys_setresuid, sys_getresuid |
| 43 | /*110*/ .word sys_setresgid, sys_getresgid, sys_setregid, sys_nis_syscall, sys_nis_syscall | 43 | /*110*/ .word sys_setresgid, sys_getresgid, sys_setregid, sys_nis_syscall, sys_nis_syscall |
| 44 | .word sys32_getgroups, sys32_gettimeofday, sys32_getrusage, sys_nis_syscall, sys_getcwd | 44 | .word sys32_getgroups, sys32_gettimeofday, sys32_getrusage, sys_nis_syscall, sys_getcwd |
| 45 | /*120*/ .word compat_sys_readv, compat_sys_writev, sys32_settimeofday, sys32_fchown16, sys_fchmod | 45 | /*120*/ .word compat_sys_readv, compat_sys_writev, sys32_settimeofday, sys_fchown16, sys_fchmod |
| 46 | .word sys_nis_syscall, sys32_setreuid16, sys32_setregid16, sys_rename, sys_truncate | 46 | .word sys_nis_syscall, sys_setreuid16, sys_setregid16, sys_rename, sys_truncate |
| 47 | /*130*/ .word sys_ftruncate, sys_flock, compat_sys_lstat64, sys_nis_syscall, sys_nis_syscall | 47 | /*130*/ .word sys_ftruncate, sys_flock, compat_sys_lstat64, sys_nis_syscall, sys_nis_syscall |
| 48 | .word sys_nis_syscall, sys32_mkdir, sys_rmdir, compat_sys_utimes, compat_sys_stat64 | 48 | .word sys_nis_syscall, sys32_mkdir, sys_rmdir, compat_sys_utimes, compat_sys_stat64 |
| 49 | /*140*/ .word sys32_sendfile64, sys_nis_syscall, sys32_futex, sys_gettid, compat_sys_getrlimit | 49 | /*140*/ .word sys32_sendfile64, sys_nis_syscall, sys32_futex, sys_gettid, compat_sys_getrlimit |
| @@ -63,7 +63,7 @@ sys_call_table32: | |||
| 63 | /*210*/ .word sys32_fadvise64_64, sys32_tgkill, sys32_waitpid, sys_swapoff, compat_sys_sysinfo | 63 | /*210*/ .word sys32_fadvise64_64, sys32_tgkill, sys32_waitpid, sys_swapoff, compat_sys_sysinfo |
| 64 | .word compat_sys_ipc, sys32_sigreturn, sys_clone, sys32_ioprio_get, compat_sys_adjtimex | 64 | .word compat_sys_ipc, sys32_sigreturn, sys_clone, sys32_ioprio_get, compat_sys_adjtimex |
| 65 | /*220*/ .word sys32_sigprocmask, sys_ni_syscall, sys32_delete_module, sys_ni_syscall, sys32_getpgid | 65 | /*220*/ .word sys32_sigprocmask, sys_ni_syscall, sys32_delete_module, sys_ni_syscall, sys32_getpgid |
| 66 | .word sys32_bdflush, sys32_sysfs, sys_nis_syscall, sys32_setfsuid16, sys32_setfsgid16 | 66 | .word sys32_bdflush, sys32_sysfs, sys_nis_syscall, sys_setfsuid16, sys_setfsgid16 |
| 67 | /*230*/ .word sys32_select, compat_sys_time, sys32_splice, compat_sys_stime, compat_sys_statfs64 | 67 | /*230*/ .word sys32_select, compat_sys_time, sys32_splice, compat_sys_stime, compat_sys_statfs64 |
| 68 | .word compat_sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys32_mlockall | 68 | .word compat_sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys32_mlockall |
| 69 | /*240*/ .word sys_munlockall, sys32_sched_setparam, sys32_sched_getparam, sys32_sched_setscheduler, sys32_sched_getscheduler | 69 | /*240*/ .word sys_munlockall, sys32_sched_setparam, sys32_sched_getparam, sys32_sched_setscheduler, sys32_sched_getscheduler |
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c index a0c6a97eec6e..cc16fdcf98af 100644 --- a/arch/sparc64/kernel/time.c +++ b/arch/sparc64/kernel/time.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <linux/kernel_stat.h> | 33 | #include <linux/kernel_stat.h> |
| 34 | #include <linux/clockchips.h> | 34 | #include <linux/clockchips.h> |
| 35 | #include <linux/clocksource.h> | 35 | #include <linux/clocksource.h> |
| 36 | #include <linux/of_device.h> | ||
| 36 | 37 | ||
| 37 | #include <asm/oplib.h> | 38 | #include <asm/oplib.h> |
| 38 | #include <asm/mostek.h> | 39 | #include <asm/mostek.h> |
| @@ -40,7 +41,6 @@ | |||
| 40 | #include <asm/irq.h> | 41 | #include <asm/irq.h> |
| 41 | #include <asm/io.h> | 42 | #include <asm/io.h> |
| 42 | #include <asm/prom.h> | 43 | #include <asm/prom.h> |
| 43 | #include <asm/of_device.h> | ||
| 44 | #include <asm/starfire.h> | 44 | #include <asm/starfire.h> |
| 45 | #include <asm/smp.h> | 45 | #include <asm/smp.h> |
| 46 | #include <asm/sections.h> | 46 | #include <asm/sections.h> |
diff --git a/arch/x86/kernel/cpu/cpufreq/Kconfig b/arch/x86/kernel/cpu/cpufreq/Kconfig index cb7a5715596d..efae3b22a0ff 100644 --- a/arch/x86/kernel/cpu/cpufreq/Kconfig +++ b/arch/x86/kernel/cpu/cpufreq/Kconfig | |||
| @@ -235,9 +235,9 @@ config X86_LONGHAUL | |||
| 235 | If in doubt, say N. | 235 | If in doubt, say N. |
| 236 | 236 | ||
| 237 | config X86_E_POWERSAVER | 237 | config X86_E_POWERSAVER |
| 238 | tristate "VIA C7 Enhanced PowerSaver (EXPERIMENTAL)" | 238 | tristate "VIA C7 Enhanced PowerSaver" |
| 239 | select CPU_FREQ_TABLE | 239 | select CPU_FREQ_TABLE |
| 240 | depends on X86_32 && EXPERIMENTAL | 240 | depends on X86_32 |
| 241 | help | 241 | help |
| 242 | This adds the CPUFreq driver for VIA C7 processors. | 242 | This adds the CPUFreq driver for VIA C7 processors. |
| 243 | 243 | ||
diff --git a/arch/x86/kernel/cpu/cpufreq/elanfreq.c b/arch/x86/kernel/cpu/cpufreq/elanfreq.c index 94619c22f563..e4a4bf870e94 100644 --- a/arch/x86/kernel/cpu/cpufreq/elanfreq.c +++ b/arch/x86/kernel/cpu/cpufreq/elanfreq.c | |||
| @@ -44,7 +44,7 @@ struct s_elan_multiplier { | |||
| 44 | * It is important that the frequencies | 44 | * It is important that the frequencies |
| 45 | * are listed in ascending order here! | 45 | * are listed in ascending order here! |
| 46 | */ | 46 | */ |
| 47 | struct s_elan_multiplier elan_multiplier[] = { | 47 | static struct s_elan_multiplier elan_multiplier[] = { |
| 48 | {1000, 0x02, 0x18}, | 48 | {1000, 0x02, 0x18}, |
| 49 | {2000, 0x02, 0x10}, | 49 | {2000, 0x02, 0x10}, |
| 50 | {4000, 0x02, 0x08}, | 50 | {4000, 0x02, 0x08}, |
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index c45ca6d4dce1..4e7271999a74 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c | |||
| @@ -66,7 +66,6 @@ static u32 find_freq_from_fid(u32 fid) | |||
| 66 | return 800 + (fid * 100); | 66 | return 800 + (fid * 100); |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | |||
| 70 | /* Return a frequency in KHz, given an input fid */ | 69 | /* Return a frequency in KHz, given an input fid */ |
| 71 | static u32 find_khz_freq_from_fid(u32 fid) | 70 | static u32 find_khz_freq_from_fid(u32 fid) |
| 72 | { | 71 | { |
| @@ -78,7 +77,6 @@ static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, u32 p | |||
| 78 | return data[pstate].frequency; | 77 | return data[pstate].frequency; |
| 79 | } | 78 | } |
| 80 | 79 | ||
| 81 | |||
| 82 | /* Return the vco fid for an input fid | 80 | /* Return the vco fid for an input fid |
| 83 | * | 81 | * |
| 84 | * Each "low" fid has corresponding "high" fid, and you can get to "low" fids | 82 | * Each "low" fid has corresponding "high" fid, and you can get to "low" fids |
| @@ -166,7 +164,6 @@ static void fidvid_msr_init(void) | |||
| 166 | wrmsr(MSR_FIDVID_CTL, lo, hi); | 164 | wrmsr(MSR_FIDVID_CTL, lo, hi); |
| 167 | } | 165 | } |
| 168 | 166 | ||
| 169 | |||
| 170 | /* write the new fid value along with the other control fields to the msr */ | 167 | /* write the new fid value along with the other control fields to the msr */ |
| 171 | static int write_new_fid(struct powernow_k8_data *data, u32 fid) | 168 | static int write_new_fid(struct powernow_k8_data *data, u32 fid) |
| 172 | { | 169 | { |
| @@ -740,44 +737,63 @@ static int find_psb_table(struct powernow_k8_data *data) | |||
| 740 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI | 737 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI |
| 741 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) | 738 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) |
| 742 | { | 739 | { |
| 743 | if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE)) | 740 | if (!data->acpi_data->state_count || (cpu_family == CPU_HW_PSTATE)) |
| 744 | return; | 741 | return; |
| 745 | 742 | ||
| 746 | data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK; | 743 | data->irt = (data->acpi_data->states[index].control >> IRT_SHIFT) & IRT_MASK; |
| 747 | data->rvo = (data->acpi_data.states[index].control >> RVO_SHIFT) & RVO_MASK; | 744 | data->rvo = (data->acpi_data->states[index].control >> RVO_SHIFT) & RVO_MASK; |
| 748 | data->exttype = (data->acpi_data.states[index].control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; | 745 | data->exttype = (data->acpi_data->states[index].control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; |
| 749 | data->plllock = (data->acpi_data.states[index].control >> PLL_L_SHIFT) & PLL_L_MASK; | 746 | data->plllock = (data->acpi_data->states[index].control >> PLL_L_SHIFT) & PLL_L_MASK; |
| 750 | data->vidmvs = 1 << ((data->acpi_data.states[index].control >> MVS_SHIFT) & MVS_MASK); | 747 | data->vidmvs = 1 << ((data->acpi_data->states[index].control >> MVS_SHIFT) & MVS_MASK); |
| 751 | data->vstable = (data->acpi_data.states[index].control >> VST_SHIFT) & VST_MASK; | 748 | data->vstable = (data->acpi_data->states[index].control >> VST_SHIFT) & VST_MASK; |
| 749 | } | ||
| 750 | |||
| 751 | |||
| 752 | static struct acpi_processor_performance *acpi_perf_data; | ||
| 753 | static int preregister_valid; | ||
| 754 | |||
| 755 | static int powernow_k8_cpu_preinit_acpi(void) | ||
| 756 | { | ||
| 757 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); | ||
| 758 | if (!acpi_perf_data) | ||
| 759 | return -ENODEV; | ||
| 760 | |||
| 761 | if (acpi_processor_preregister_performance(acpi_perf_data)) | ||
| 762 | return -ENODEV; | ||
| 763 | else | ||
| 764 | preregister_valid = 1; | ||
| 765 | return 0; | ||
| 752 | } | 766 | } |
| 753 | 767 | ||
| 754 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) | 768 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) |
| 755 | { | 769 | { |
| 756 | struct cpufreq_frequency_table *powernow_table; | 770 | struct cpufreq_frequency_table *powernow_table; |
| 757 | int ret_val; | 771 | int ret_val; |
| 772 | int cpu = 0; | ||
| 758 | 773 | ||
| 759 | if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { | 774 | data->acpi_data = percpu_ptr(acpi_perf_data, cpu); |
| 775 | if (acpi_processor_register_performance(data->acpi_data, data->cpu)) { | ||
| 760 | dprintk("register performance failed: bad ACPI data\n"); | 776 | dprintk("register performance failed: bad ACPI data\n"); |
| 761 | return -EIO; | 777 | return -EIO; |
| 762 | } | 778 | } |
| 763 | 779 | ||
| 764 | /* verify the data contained in the ACPI structures */ | 780 | /* verify the data contained in the ACPI structures */ |
| 765 | if (data->acpi_data.state_count <= 1) { | 781 | if (data->acpi_data->state_count <= 1) { |
| 766 | dprintk("No ACPI P-States\n"); | 782 | dprintk("No ACPI P-States\n"); |
| 767 | goto err_out; | 783 | goto err_out; |
| 768 | } | 784 | } |
| 769 | 785 | ||
| 770 | if ((data->acpi_data.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) || | 786 | if ((data->acpi_data->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) || |
| 771 | (data->acpi_data.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { | 787 | (data->acpi_data->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { |
| 772 | dprintk("Invalid control/status registers (%x - %x)\n", | 788 | dprintk("Invalid control/status registers (%x - %x)\n", |
| 773 | data->acpi_data.control_register.space_id, | 789 | data->acpi_data->control_register.space_id, |
| 774 | data->acpi_data.status_register.space_id); | 790 | data->acpi_data->status_register.space_id); |
| 775 | goto err_out; | 791 | goto err_out; |
| 776 | } | 792 | } |
| 777 | 793 | ||
| 778 | /* fill in data->powernow_table */ | 794 | /* fill in data->powernow_table */ |
| 779 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | 795 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) |
| 780 | * (data->acpi_data.state_count + 1)), GFP_KERNEL); | 796 | * (data->acpi_data->state_count + 1)), GFP_KERNEL); |
| 781 | if (!powernow_table) { | 797 | if (!powernow_table) { |
| 782 | dprintk("powernow_table memory alloc failure\n"); | 798 | dprintk("powernow_table memory alloc failure\n"); |
| 783 | goto err_out; | 799 | goto err_out; |
| @@ -790,12 +806,12 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) | |||
| 790 | if (ret_val) | 806 | if (ret_val) |
| 791 | goto err_out_mem; | 807 | goto err_out_mem; |
| 792 | 808 | ||
| 793 | powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END; | 809 | powernow_table[data->acpi_data->state_count].frequency = CPUFREQ_TABLE_END; |
| 794 | powernow_table[data->acpi_data.state_count].index = 0; | 810 | powernow_table[data->acpi_data->state_count].index = 0; |
| 795 | data->powernow_table = powernow_table; | 811 | data->powernow_table = powernow_table; |
| 796 | 812 | ||
| 797 | /* fill in data */ | 813 | /* fill in data */ |
| 798 | data->numps = data->acpi_data.state_count; | 814 | data->numps = data->acpi_data->state_count; |
| 799 | if (first_cpu(per_cpu(cpu_core_map, data->cpu)) == data->cpu) | 815 | if (first_cpu(per_cpu(cpu_core_map, data->cpu)) == data->cpu) |
| 800 | print_basics(data); | 816 | print_basics(data); |
| 801 | powernow_k8_acpi_pst_values(data, 0); | 817 | powernow_k8_acpi_pst_values(data, 0); |
| @@ -803,16 +819,31 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) | |||
| 803 | /* notify BIOS that we exist */ | 819 | /* notify BIOS that we exist */ |
| 804 | acpi_processor_notify_smm(THIS_MODULE); | 820 | acpi_processor_notify_smm(THIS_MODULE); |
| 805 | 821 | ||
| 822 | /* determine affinity, from ACPI if available */ | ||
| 823 | if (preregister_valid) { | ||
| 824 | if ((data->acpi_data->shared_type == CPUFREQ_SHARED_TYPE_ALL) || | ||
| 825 | (data->acpi_data->shared_type == CPUFREQ_SHARED_TYPE_ANY)) | ||
| 826 | data->starting_core_affinity = data->acpi_data->shared_cpu_map; | ||
| 827 | else | ||
| 828 | data->starting_core_affinity = cpumask_of_cpu(data->cpu); | ||
| 829 | } else { | ||
| 830 | /* best guess from family if not */ | ||
| 831 | if (cpu_family == CPU_HW_PSTATE) | ||
| 832 | data->starting_core_affinity = cpumask_of_cpu(data->cpu); | ||
| 833 | else | ||
| 834 | data->starting_core_affinity = per_cpu(cpu_core_map, data->cpu); | ||
| 835 | } | ||
| 836 | |||
| 806 | return 0; | 837 | return 0; |
| 807 | 838 | ||
| 808 | err_out_mem: | 839 | err_out_mem: |
| 809 | kfree(powernow_table); | 840 | kfree(powernow_table); |
| 810 | 841 | ||
| 811 | err_out: | 842 | err_out: |
| 812 | acpi_processor_unregister_performance(&data->acpi_data, data->cpu); | 843 | acpi_processor_unregister_performance(data->acpi_data, data->cpu); |
| 813 | 844 | ||
| 814 | /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */ | 845 | /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */ |
| 815 | data->acpi_data.state_count = 0; | 846 | data->acpi_data->state_count = 0; |
| 816 | 847 | ||
| 817 | return -ENODEV; | 848 | return -ENODEV; |
| 818 | } | 849 | } |
| @@ -824,10 +855,10 @@ static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpuf | |||
| 824 | rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo); | 855 | rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo); |
| 825 | data->max_hw_pstate = (hi & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT; | 856 | data->max_hw_pstate = (hi & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT; |
| 826 | 857 | ||
| 827 | for (i = 0; i < data->acpi_data.state_count; i++) { | 858 | for (i = 0; i < data->acpi_data->state_count; i++) { |
| 828 | u32 index; | 859 | u32 index; |
| 829 | 860 | ||
| 830 | index = data->acpi_data.states[i].control & HW_PSTATE_MASK; | 861 | index = data->acpi_data->states[i].control & HW_PSTATE_MASK; |
| 831 | if (index > data->max_hw_pstate) { | 862 | if (index > data->max_hw_pstate) { |
| 832 | printk(KERN_ERR PFX "invalid pstate %d - bad value %d.\n", i, index); | 863 | printk(KERN_ERR PFX "invalid pstate %d - bad value %d.\n", i, index); |
| 833 | printk(KERN_ERR PFX "Please report to BIOS manufacturer\n"); | 864 | printk(KERN_ERR PFX "Please report to BIOS manufacturer\n"); |
| @@ -843,7 +874,7 @@ static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpuf | |||
| 843 | 874 | ||
| 844 | powernow_table[i].index = index; | 875 | powernow_table[i].index = index; |
| 845 | 876 | ||
| 846 | powernow_table[i].frequency = data->acpi_data.states[i].core_frequency * 1000; | 877 | powernow_table[i].frequency = data->acpi_data->states[i].core_frequency * 1000; |
| 847 | } | 878 | } |
| 848 | return 0; | 879 | return 0; |
| 849 | } | 880 | } |
| @@ -852,16 +883,16 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpuf | |||
| 852 | { | 883 | { |
| 853 | int i; | 884 | int i; |
| 854 | int cntlofreq = 0; | 885 | int cntlofreq = 0; |
| 855 | for (i = 0; i < data->acpi_data.state_count; i++) { | 886 | for (i = 0; i < data->acpi_data->state_count; i++) { |
| 856 | u32 fid; | 887 | u32 fid; |
| 857 | u32 vid; | 888 | u32 vid; |
| 858 | 889 | ||
| 859 | if (data->exttype) { | 890 | if (data->exttype) { |
| 860 | fid = data->acpi_data.states[i].status & EXT_FID_MASK; | 891 | fid = data->acpi_data->states[i].status & EXT_FID_MASK; |
| 861 | vid = (data->acpi_data.states[i].status >> VID_SHIFT) & EXT_VID_MASK; | 892 | vid = (data->acpi_data->states[i].status >> VID_SHIFT) & EXT_VID_MASK; |
| 862 | } else { | 893 | } else { |
| 863 | fid = data->acpi_data.states[i].control & FID_MASK; | 894 | fid = data->acpi_data->states[i].control & FID_MASK; |
| 864 | vid = (data->acpi_data.states[i].control >> VID_SHIFT) & VID_MASK; | 895 | vid = (data->acpi_data->states[i].control >> VID_SHIFT) & VID_MASK; |
| 865 | } | 896 | } |
| 866 | 897 | ||
| 867 | dprintk(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); | 898 | dprintk(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); |
| @@ -902,10 +933,10 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpuf | |||
| 902 | cntlofreq = i; | 933 | cntlofreq = i; |
| 903 | } | 934 | } |
| 904 | 935 | ||
| 905 | if (powernow_table[i].frequency != (data->acpi_data.states[i].core_frequency * 1000)) { | 936 | if (powernow_table[i].frequency != (data->acpi_data->states[i].core_frequency * 1000)) { |
| 906 | printk(KERN_INFO PFX "invalid freq entries %u kHz vs. %u kHz\n", | 937 | printk(KERN_INFO PFX "invalid freq entries %u kHz vs. %u kHz\n", |
| 907 | powernow_table[i].frequency, | 938 | powernow_table[i].frequency, |
| 908 | (unsigned int) (data->acpi_data.states[i].core_frequency * 1000)); | 939 | (unsigned int) (data->acpi_data->states[i].core_frequency * 1000)); |
| 909 | powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID; | 940 | powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID; |
| 910 | continue; | 941 | continue; |
| 911 | } | 942 | } |
| @@ -915,11 +946,12 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpuf | |||
| 915 | 946 | ||
| 916 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) | 947 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) |
| 917 | { | 948 | { |
| 918 | if (data->acpi_data.state_count) | 949 | if (data->acpi_data->state_count) |
| 919 | acpi_processor_unregister_performance(&data->acpi_data, data->cpu); | 950 | acpi_processor_unregister_performance(data->acpi_data, data->cpu); |
| 920 | } | 951 | } |
| 921 | 952 | ||
| 922 | #else | 953 | #else |
| 954 | static int powernow_k8_cpu_preinit_acpi(void) { return -ENODEV; } | ||
| 923 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) { return -ENODEV; } | 955 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) { return -ENODEV; } |
| 924 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) { return; } | 956 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) { return; } |
| 925 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) { return; } | 957 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) { return; } |
| @@ -1104,7 +1136,7 @@ static int powernowk8_verify(struct cpufreq_policy *pol) | |||
| 1104 | static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) | 1136 | static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) |
| 1105 | { | 1137 | { |
| 1106 | struct powernow_k8_data *data; | 1138 | struct powernow_k8_data *data; |
| 1107 | cpumask_t oldmask; | 1139 | cpumask_t oldmask = CPU_MASK_ALL; |
| 1108 | int rc; | 1140 | int rc; |
| 1109 | 1141 | ||
| 1110 | if (!cpu_online(pol->cpu)) | 1142 | if (!cpu_online(pol->cpu)) |
| @@ -1177,10 +1209,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) | |||
| 1177 | /* run on any CPU again */ | 1209 | /* run on any CPU again */ |
| 1178 | set_cpus_allowed_ptr(current, &oldmask); | 1210 | set_cpus_allowed_ptr(current, &oldmask); |
| 1179 | 1211 | ||
| 1180 | if (cpu_family == CPU_HW_PSTATE) | 1212 | pol->cpus = data->starting_core_affinity; |
| 1181 | pol->cpus = cpumask_of_cpu(pol->cpu); | ||
| 1182 | else | ||
| 1183 | pol->cpus = per_cpu(cpu_core_map, pol->cpu); | ||
| 1184 | data->available_cores = &(pol->cpus); | 1213 | data->available_cores = &(pol->cpus); |
| 1185 | 1214 | ||
| 1186 | /* Take a crude guess here. | 1215 | /* Take a crude guess here. |
| @@ -1303,6 +1332,7 @@ static int __cpuinit powernowk8_init(void) | |||
| 1303 | } | 1332 | } |
| 1304 | 1333 | ||
| 1305 | if (supported_cpus == num_online_cpus()) { | 1334 | if (supported_cpus == num_online_cpus()) { |
| 1335 | powernow_k8_cpu_preinit_acpi(); | ||
| 1306 | printk(KERN_INFO PFX "Found %d %s " | 1336 | printk(KERN_INFO PFX "Found %d %s " |
| 1307 | "processors (%d cpu cores) (" VERSION ")\n", | 1337 | "processors (%d cpu cores) (" VERSION ")\n", |
| 1308 | num_online_nodes(), | 1338 | num_online_nodes(), |
| @@ -1319,6 +1349,10 @@ static void __exit powernowk8_exit(void) | |||
| 1319 | dprintk("exit\n"); | 1349 | dprintk("exit\n"); |
| 1320 | 1350 | ||
| 1321 | cpufreq_unregister_driver(&cpufreq_amd64_driver); | 1351 | cpufreq_unregister_driver(&cpufreq_amd64_driver); |
| 1352 | |||
| 1353 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI | ||
| 1354 | free_percpu(acpi_perf_data); | ||
| 1355 | #endif | ||
| 1322 | } | 1356 | } |
| 1323 | 1357 | ||
| 1324 | MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and Mark Langsdorf <mark.langsdorf@amd.com>"); | 1358 | MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and Mark Langsdorf <mark.langsdorf@amd.com>"); |
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h index ab48cfed4d96..a62612cd4be8 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h | |||
| @@ -33,12 +33,13 @@ struct powernow_k8_data { | |||
| 33 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI | 33 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI |
| 34 | /* the acpi table needs to be kept. it's only available if ACPI was | 34 | /* the acpi table needs to be kept. it's only available if ACPI was |
| 35 | * used to determine valid frequency/vid/fid states */ | 35 | * used to determine valid frequency/vid/fid states */ |
| 36 | struct acpi_processor_performance acpi_data; | 36 | struct acpi_processor_performance *acpi_data; |
| 37 | #endif | 37 | #endif |
| 38 | /* we need to keep track of associated cores, but let cpufreq | 38 | /* we need to keep track of associated cores, but let cpufreq |
| 39 | * handle hotplug events - so just point at cpufreq pol->cpus | 39 | * handle hotplug events - so just point at cpufreq pol->cpus |
| 40 | * structure */ | 40 | * structure */ |
| 41 | cpumask_t *available_cores; | 41 | cpumask_t *available_cores; |
| 42 | cpumask_t starting_core_affinity; | ||
| 42 | }; | 43 | }; |
| 43 | 44 | ||
| 44 | 45 | ||
diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 65974c6d3d7a..c029d3eb9ef0 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c | |||
| @@ -263,11 +263,12 @@ async_xor_zero_sum(struct page *dest, struct page **src_list, | |||
| 263 | if (unlikely(!tx)) { | 263 | if (unlikely(!tx)) { |
| 264 | async_tx_quiesce(&depend_tx); | 264 | async_tx_quiesce(&depend_tx); |
| 265 | 265 | ||
| 266 | while (!tx) | 266 | while (!tx) { |
| 267 | dma_async_issue_pending(chan); | 267 | dma_async_issue_pending(chan); |
| 268 | tx = device->device_prep_dma_zero_sum(chan, | 268 | tx = device->device_prep_dma_zero_sum(chan, |
| 269 | dma_src, src_cnt, len, result, | 269 | dma_src, src_cnt, len, result, |
| 270 | dma_prep_flags); | 270 | dma_prep_flags); |
| 271 | } | ||
| 271 | } | 272 | } |
| 272 | 273 | ||
| 273 | async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); | 274 | async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); |
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 0ce0c279aabf..b73116ef9236 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c | |||
| @@ -159,7 +159,7 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, | |||
| 159 | static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo); | 159 | static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo); |
| 160 | 160 | ||
| 161 | static int cciss_revalidate(struct gendisk *disk); | 161 | static int cciss_revalidate(struct gendisk *disk); |
| 162 | static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk); | 162 | static int rebuild_lun_table(ctlr_info_t *h, int first_time); |
| 163 | static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, | 163 | static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, |
| 164 | int clear_all); | 164 | int clear_all); |
| 165 | 165 | ||
| @@ -171,7 +171,6 @@ static void cciss_geometry_inquiry(int ctlr, int logvol, | |||
| 171 | int withirq, sector_t total_size, | 171 | int withirq, sector_t total_size, |
| 172 | unsigned int block_size, InquiryData_struct *inq_buff, | 172 | unsigned int block_size, InquiryData_struct *inq_buff, |
| 173 | drive_info_struct *drv); | 173 | drive_info_struct *drv); |
| 174 | static void cciss_getgeometry(int cntl_num); | ||
| 175 | static void __devinit cciss_interrupt_mode(ctlr_info_t *, struct pci_dev *, | 174 | static void __devinit cciss_interrupt_mode(ctlr_info_t *, struct pci_dev *, |
| 176 | __u32); | 175 | __u32); |
| 177 | static void start_io(ctlr_info_t *h); | 176 | static void start_io(ctlr_info_t *h); |
| @@ -929,8 +928,10 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, | |||
| 929 | return 0; | 928 | return 0; |
| 930 | } | 929 | } |
| 931 | 930 | ||
| 931 | case CCISS_DEREGDISK: | ||
| 932 | case CCISS_REGNEWD: | ||
| 932 | case CCISS_REVALIDVOLS: | 933 | case CCISS_REVALIDVOLS: |
| 933 | return rebuild_lun_table(host, NULL); | 934 | return rebuild_lun_table(host, 0); |
| 934 | 935 | ||
| 935 | case CCISS_GETLUNINFO:{ | 936 | case CCISS_GETLUNINFO:{ |
| 936 | LogvolInfo_struct luninfo; | 937 | LogvolInfo_struct luninfo; |
| @@ -943,12 +944,6 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, | |||
| 943 | return -EFAULT; | 944 | return -EFAULT; |
| 944 | return 0; | 945 | return 0; |
| 945 | } | 946 | } |
| 946 | case CCISS_DEREGDISK: | ||
| 947 | return rebuild_lun_table(host, disk); | ||
| 948 | |||
| 949 | case CCISS_REGNEWD: | ||
| 950 | return rebuild_lun_table(host, NULL); | ||
| 951 | |||
| 952 | case CCISS_PASSTHRU: | 947 | case CCISS_PASSTHRU: |
| 953 | { | 948 | { |
| 954 | IOCTL_Command_struct iocommand; | 949 | IOCTL_Command_struct iocommand; |
| @@ -1134,7 +1129,7 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, | |||
| 1134 | if (ioc->Request.Type.Direction == XFER_WRITE) { | 1129 | if (ioc->Request.Type.Direction == XFER_WRITE) { |
| 1135 | if (copy_from_user | 1130 | if (copy_from_user |
| 1136 | (buff[sg_used], data_ptr, sz)) { | 1131 | (buff[sg_used], data_ptr, sz)) { |
| 1137 | status = -ENOMEM; | 1132 | status = -EFAULT; |
| 1138 | goto cleanup1; | 1133 | goto cleanup1; |
| 1139 | } | 1134 | } |
| 1140 | } else { | 1135 | } else { |
| @@ -1330,15 +1325,84 @@ static void cciss_softirq_done(struct request *rq) | |||
| 1330 | spin_unlock_irqrestore(&h->lock, flags); | 1325 | spin_unlock_irqrestore(&h->lock, flags); |
| 1331 | } | 1326 | } |
| 1332 | 1327 | ||
| 1328 | /* This function gets the serial number of a logical drive via | ||
| 1329 | * inquiry page 0x83. Serial no. is 16 bytes. If the serial | ||
| 1330 | * number cannot be had, for whatever reason, 16 bytes of 0xff | ||
| 1331 | * are returned instead. | ||
| 1332 | */ | ||
| 1333 | static void cciss_get_serial_no(int ctlr, int logvol, int withirq, | ||
| 1334 | unsigned char *serial_no, int buflen) | ||
| 1335 | { | ||
| 1336 | #define PAGE_83_INQ_BYTES 64 | ||
| 1337 | int rc; | ||
| 1338 | unsigned char *buf; | ||
| 1339 | |||
| 1340 | if (buflen > 16) | ||
| 1341 | buflen = 16; | ||
| 1342 | memset(serial_no, 0xff, buflen); | ||
| 1343 | buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL); | ||
| 1344 | if (!buf) | ||
| 1345 | return; | ||
| 1346 | memset(serial_no, 0, buflen); | ||
| 1347 | if (withirq) | ||
| 1348 | rc = sendcmd_withirq(CISS_INQUIRY, ctlr, buf, | ||
| 1349 | PAGE_83_INQ_BYTES, 1, logvol, 0x83, TYPE_CMD); | ||
| 1350 | else | ||
| 1351 | rc = sendcmd(CISS_INQUIRY, ctlr, buf, | ||
| 1352 | PAGE_83_INQ_BYTES, 1, logvol, 0x83, NULL, TYPE_CMD); | ||
| 1353 | if (rc == IO_OK) | ||
| 1354 | memcpy(serial_no, &buf[8], buflen); | ||
| 1355 | kfree(buf); | ||
| 1356 | return; | ||
| 1357 | } | ||
| 1358 | |||
| 1359 | static void cciss_add_disk(ctlr_info_t *h, struct gendisk *disk, | ||
| 1360 | int drv_index) | ||
| 1361 | { | ||
| 1362 | disk->queue = blk_init_queue(do_cciss_request, &h->lock); | ||
| 1363 | sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index); | ||
| 1364 | disk->major = h->major; | ||
| 1365 | disk->first_minor = drv_index << NWD_SHIFT; | ||
| 1366 | disk->fops = &cciss_fops; | ||
| 1367 | disk->private_data = &h->drv[drv_index]; | ||
| 1368 | |||
| 1369 | /* Set up queue information */ | ||
| 1370 | blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask); | ||
| 1371 | |||
| 1372 | /* This is a hardware imposed limit. */ | ||
| 1373 | blk_queue_max_hw_segments(disk->queue, MAXSGENTRIES); | ||
| 1374 | |||
| 1375 | /* This is a limit in the driver and could be eliminated. */ | ||
| 1376 | blk_queue_max_phys_segments(disk->queue, MAXSGENTRIES); | ||
| 1377 | |||
| 1378 | blk_queue_max_sectors(disk->queue, h->cciss_max_sectors); | ||
| 1379 | |||
| 1380 | blk_queue_softirq_done(disk->queue, cciss_softirq_done); | ||
| 1381 | |||
| 1382 | disk->queue->queuedata = h; | ||
| 1383 | |||
| 1384 | blk_queue_hardsect_size(disk->queue, | ||
| 1385 | h->drv[drv_index].block_size); | ||
| 1386 | |||
| 1387 | /* Make sure all queue data is written out before */ | ||
| 1388 | /* setting h->drv[drv_index].queue, as setting this */ | ||
| 1389 | /* allows the interrupt handler to start the queue */ | ||
| 1390 | wmb(); | ||
| 1391 | h->drv[drv_index].queue = disk->queue; | ||
| 1392 | add_disk(disk); | ||
| 1393 | } | ||
| 1394 | |||
| 1333 | /* This function will check the usage_count of the drive to be updated/added. | 1395 | /* This function will check the usage_count of the drive to be updated/added. |
| 1334 | * If the usage_count is zero then the drive information will be updated and | 1396 | * If the usage_count is zero and it is a heretofore unknown drive, or, |
| 1335 | * the disk will be re-registered with the kernel. If not then it will be | 1397 | * the drive's capacity, geometry, or serial number has changed, |
| 1336 | * left alone for the next reboot. The exception to this is disk 0 which | 1398 | * then the drive information will be updated and the disk will be |
| 1337 | * will always be left registered with the kernel since it is also the | 1399 | * re-registered with the kernel. If these conditions don't hold, |
| 1338 | * controller node. Any changes to disk 0 will show up on the next | 1400 | * then it will be left alone for the next reboot. The exception to this |
| 1339 | * reboot. | 1401 | * is disk 0 which will always be left registered with the kernel since it |
| 1402 | * is also the controller node. Any changes to disk 0 will show up on | ||
| 1403 | * the next reboot. | ||
| 1340 | */ | 1404 | */ |
| 1341 | static void cciss_update_drive_info(int ctlr, int drv_index) | 1405 | static void cciss_update_drive_info(int ctlr, int drv_index, int first_time) |
| 1342 | { | 1406 | { |
| 1343 | ctlr_info_t *h = hba[ctlr]; | 1407 | ctlr_info_t *h = hba[ctlr]; |
| 1344 | struct gendisk *disk; | 1408 | struct gendisk *disk; |
| @@ -1347,16 +1411,81 @@ static void cciss_update_drive_info(int ctlr, int drv_index) | |||
| 1347 | sector_t total_size; | 1411 | sector_t total_size; |
| 1348 | unsigned long flags = 0; | 1412 | unsigned long flags = 0; |
| 1349 | int ret = 0; | 1413 | int ret = 0; |
| 1414 | drive_info_struct *drvinfo; | ||
| 1415 | int was_only_controller_node; | ||
| 1416 | |||
| 1417 | /* Get information about the disk and modify the driver structure */ | ||
| 1418 | inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); | ||
| 1419 | drvinfo = kmalloc(sizeof(*drvinfo), GFP_KERNEL); | ||
| 1420 | if (inq_buff == NULL || drvinfo == NULL) | ||
| 1421 | goto mem_msg; | ||
| 1422 | |||
| 1423 | /* See if we're trying to update the "controller node" | ||
| 1424 | * this will happen the when the first logical drive gets | ||
| 1425 | * created by ACU. | ||
| 1426 | */ | ||
| 1427 | was_only_controller_node = (drv_index == 0 && | ||
| 1428 | h->drv[0].raid_level == -1); | ||
| 1350 | 1429 | ||
| 1351 | /* if the disk already exists then deregister it before proceeding */ | 1430 | /* testing to see if 16-byte CDBs are already being used */ |
| 1352 | if (h->drv[drv_index].raid_level != -1) { | 1431 | if (h->cciss_read == CCISS_READ_16) { |
| 1432 | cciss_read_capacity_16(h->ctlr, drv_index, 1, | ||
| 1433 | &total_size, &block_size); | ||
| 1434 | |||
| 1435 | } else { | ||
| 1436 | cciss_read_capacity(ctlr, drv_index, 1, | ||
| 1437 | &total_size, &block_size); | ||
| 1438 | |||
| 1439 | /* if read_capacity returns all F's this volume is >2TB */ | ||
| 1440 | /* in size so we switch to 16-byte CDB's for all */ | ||
| 1441 | /* read/write ops */ | ||
| 1442 | if (total_size == 0xFFFFFFFFULL) { | ||
| 1443 | cciss_read_capacity_16(ctlr, drv_index, 1, | ||
| 1444 | &total_size, &block_size); | ||
| 1445 | h->cciss_read = CCISS_READ_16; | ||
| 1446 | h->cciss_write = CCISS_WRITE_16; | ||
| 1447 | } else { | ||
| 1448 | h->cciss_read = CCISS_READ_10; | ||
| 1449 | h->cciss_write = CCISS_WRITE_10; | ||
| 1450 | } | ||
| 1451 | } | ||
| 1452 | |||
| 1453 | cciss_geometry_inquiry(ctlr, drv_index, 1, total_size, block_size, | ||
| 1454 | inq_buff, drvinfo); | ||
| 1455 | drvinfo->block_size = block_size; | ||
| 1456 | drvinfo->nr_blocks = total_size + 1; | ||
| 1457 | |||
| 1458 | cciss_get_serial_no(ctlr, drv_index, 1, drvinfo->serial_no, | ||
| 1459 | sizeof(drvinfo->serial_no)); | ||
| 1460 | |||
| 1461 | /* Is it the same disk we already know, and nothing's changed? */ | ||
| 1462 | if (h->drv[drv_index].raid_level != -1 && | ||
| 1463 | ((memcmp(drvinfo->serial_no, | ||
| 1464 | h->drv[drv_index].serial_no, 16) == 0) && | ||
| 1465 | drvinfo->block_size == h->drv[drv_index].block_size && | ||
| 1466 | drvinfo->nr_blocks == h->drv[drv_index].nr_blocks && | ||
| 1467 | drvinfo->heads == h->drv[drv_index].heads && | ||
| 1468 | drvinfo->sectors == h->drv[drv_index].sectors && | ||
| 1469 | drvinfo->cylinders == h->drv[drv_index].cylinders)) | ||
| 1470 | /* The disk is unchanged, nothing to update */ | ||
| 1471 | goto freeret; | ||
| 1472 | |||
| 1473 | /* If we get here it's not the same disk, or something's changed, | ||
| 1474 | * so we need to * deregister it, and re-register it, if it's not | ||
| 1475 | * in use. | ||
| 1476 | * If the disk already exists then deregister it before proceeding | ||
| 1477 | * (unless it's the first disk (for the controller node). | ||
| 1478 | */ | ||
| 1479 | if (h->drv[drv_index].raid_level != -1 && drv_index != 0) { | ||
| 1480 | printk(KERN_WARNING "disk %d has changed.\n", drv_index); | ||
| 1353 | spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); | 1481 | spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); |
| 1354 | h->drv[drv_index].busy_configuring = 1; | 1482 | h->drv[drv_index].busy_configuring = 1; |
| 1355 | spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); | 1483 | spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); |
| 1356 | 1484 | ||
| 1357 | /* deregister_disk sets h->drv[drv_index].queue = NULL */ | 1485 | /* deregister_disk sets h->drv[drv_index].queue = NULL |
| 1358 | /* which keeps the interrupt handler from starting */ | 1486 | * which keeps the interrupt handler from starting |
| 1359 | /* the queue. */ | 1487 | * the queue. |
| 1488 | */ | ||
| 1360 | ret = deregister_disk(h->gendisk[drv_index], | 1489 | ret = deregister_disk(h->gendisk[drv_index], |
| 1361 | &h->drv[drv_index], 0); | 1490 | &h->drv[drv_index], 0); |
| 1362 | h->drv[drv_index].busy_configuring = 0; | 1491 | h->drv[drv_index].busy_configuring = 0; |
| @@ -1364,81 +1493,37 @@ static void cciss_update_drive_info(int ctlr, int drv_index) | |||
| 1364 | 1493 | ||
| 1365 | /* If the disk is in use return */ | 1494 | /* If the disk is in use return */ |
| 1366 | if (ret) | 1495 | if (ret) |
| 1367 | return; | 1496 | goto freeret; |
| 1368 | 1497 | ||
| 1369 | /* Get information about the disk and modify the driver structure */ | 1498 | /* Save the new information from cciss_geometry_inquiry |
| 1370 | inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); | 1499 | * and serial number inquiry. |
| 1371 | if (inq_buff == NULL) | 1500 | */ |
| 1372 | goto mem_msg; | 1501 | h->drv[drv_index].block_size = drvinfo->block_size; |
| 1373 | 1502 | h->drv[drv_index].nr_blocks = drvinfo->nr_blocks; | |
| 1374 | /* testing to see if 16-byte CDBs are already being used */ | 1503 | h->drv[drv_index].heads = drvinfo->heads; |
| 1375 | if (h->cciss_read == CCISS_READ_16) { | 1504 | h->drv[drv_index].sectors = drvinfo->sectors; |
| 1376 | cciss_read_capacity_16(h->ctlr, drv_index, 1, | 1505 | h->drv[drv_index].cylinders = drvinfo->cylinders; |
| 1377 | &total_size, &block_size); | 1506 | h->drv[drv_index].raid_level = drvinfo->raid_level; |
| 1378 | goto geo_inq; | 1507 | memcpy(h->drv[drv_index].serial_no, drvinfo->serial_no, 16); |
| 1379 | } | ||
| 1380 | |||
| 1381 | cciss_read_capacity(ctlr, drv_index, 1, | ||
| 1382 | &total_size, &block_size); | ||
| 1383 | |||
| 1384 | /* if read_capacity returns all F's this volume is >2TB in size */ | ||
| 1385 | /* so we switch to 16-byte CDB's for all read/write ops */ | ||
| 1386 | if (total_size == 0xFFFFFFFFULL) { | ||
| 1387 | cciss_read_capacity_16(ctlr, drv_index, 1, | ||
| 1388 | &total_size, &block_size); | ||
| 1389 | h->cciss_read = CCISS_READ_16; | ||
| 1390 | h->cciss_write = CCISS_WRITE_16; | ||
| 1391 | } else { | ||
| 1392 | h->cciss_read = CCISS_READ_10; | ||
| 1393 | h->cciss_write = CCISS_WRITE_10; | ||
| 1394 | } | ||
| 1395 | geo_inq: | ||
| 1396 | cciss_geometry_inquiry(ctlr, drv_index, 1, total_size, block_size, | ||
| 1397 | inq_buff, &h->drv[drv_index]); | ||
| 1398 | 1508 | ||
| 1399 | ++h->num_luns; | 1509 | ++h->num_luns; |
| 1400 | disk = h->gendisk[drv_index]; | 1510 | disk = h->gendisk[drv_index]; |
| 1401 | set_capacity(disk, h->drv[drv_index].nr_blocks); | 1511 | set_capacity(disk, h->drv[drv_index].nr_blocks); |
| 1402 | 1512 | ||
| 1403 | /* if it's the controller it's already added */ | 1513 | /* If it's not disk 0 (drv_index != 0) |
| 1404 | if (drv_index) { | 1514 | * or if it was disk 0, but there was previously |
| 1405 | disk->queue = blk_init_queue(do_cciss_request, &h->lock); | 1515 | * no actual corresponding configured logical drive |
| 1406 | sprintf(disk->disk_name, "cciss/c%dd%d", ctlr, drv_index); | 1516 | * (raid_leve == -1) then we want to update the |
| 1407 | disk->major = h->major; | 1517 | * logical drive's information. |
| 1408 | disk->first_minor = drv_index << NWD_SHIFT; | 1518 | */ |
| 1409 | disk->fops = &cciss_fops; | 1519 | if (drv_index || first_time) |
| 1410 | disk->private_data = &h->drv[drv_index]; | 1520 | cciss_add_disk(h, disk, drv_index); |
| 1411 | |||
| 1412 | /* Set up queue information */ | ||
| 1413 | blk_queue_bounce_limit(disk->queue, hba[ctlr]->pdev->dma_mask); | ||
| 1414 | |||
| 1415 | /* This is a hardware imposed limit. */ | ||
| 1416 | blk_queue_max_hw_segments(disk->queue, MAXSGENTRIES); | ||
| 1417 | |||
| 1418 | /* This is a limit in the driver and could be eliminated. */ | ||
| 1419 | blk_queue_max_phys_segments(disk->queue, MAXSGENTRIES); | ||
| 1420 | |||
| 1421 | blk_queue_max_sectors(disk->queue, h->cciss_max_sectors); | ||
| 1422 | |||
| 1423 | blk_queue_softirq_done(disk->queue, cciss_softirq_done); | ||
| 1424 | |||
| 1425 | disk->queue->queuedata = hba[ctlr]; | ||
| 1426 | |||
| 1427 | blk_queue_hardsect_size(disk->queue, | ||
| 1428 | hba[ctlr]->drv[drv_index].block_size); | ||
| 1429 | |||
| 1430 | /* Make sure all queue data is written out before */ | ||
| 1431 | /* setting h->drv[drv_index].queue, as setting this */ | ||
| 1432 | /* allows the interrupt handler to start the queue */ | ||
| 1433 | wmb(); | ||
| 1434 | h->drv[drv_index].queue = disk->queue; | ||
| 1435 | add_disk(disk); | ||
| 1436 | } | ||
| 1437 | 1521 | ||
| 1438 | freeret: | 1522 | freeret: |
| 1439 | kfree(inq_buff); | 1523 | kfree(inq_buff); |
| 1524 | kfree(drvinfo); | ||
| 1440 | return; | 1525 | return; |
| 1441 | mem_msg: | 1526 | mem_msg: |
| 1442 | printk(KERN_ERR "cciss: out of memory\n"); | 1527 | printk(KERN_ERR "cciss: out of memory\n"); |
| 1443 | goto freeret; | 1528 | goto freeret; |
| 1444 | } | 1529 | } |
| @@ -1448,21 +1533,91 @@ geo_inq: | |||
| 1448 | * where new drives will be added. If the index to be returned is greater | 1533 | * where new drives will be added. If the index to be returned is greater |
| 1449 | * than the highest_lun index for the controller then highest_lun is set | 1534 | * than the highest_lun index for the controller then highest_lun is set |
| 1450 | * to this new index. If there are no available indexes then -1 is returned. | 1535 | * to this new index. If there are no available indexes then -1 is returned. |
| 1536 | * "controller_node" is used to know if this is a real logical drive, or just | ||
| 1537 | * the controller node, which determines if this counts towards highest_lun. | ||
| 1451 | */ | 1538 | */ |
| 1452 | static int cciss_find_free_drive_index(int ctlr) | 1539 | static int cciss_find_free_drive_index(int ctlr, int controller_node) |
| 1453 | { | 1540 | { |
| 1454 | int i; | 1541 | int i; |
| 1455 | 1542 | ||
| 1456 | for (i = 0; i < CISS_MAX_LUN; i++) { | 1543 | for (i = 0; i < CISS_MAX_LUN; i++) { |
| 1457 | if (hba[ctlr]->drv[i].raid_level == -1) { | 1544 | if (hba[ctlr]->drv[i].raid_level == -1) { |
| 1458 | if (i > hba[ctlr]->highest_lun) | 1545 | if (i > hba[ctlr]->highest_lun) |
| 1459 | hba[ctlr]->highest_lun = i; | 1546 | if (!controller_node) |
| 1547 | hba[ctlr]->highest_lun = i; | ||
| 1460 | return i; | 1548 | return i; |
| 1461 | } | 1549 | } |
| 1462 | } | 1550 | } |
| 1463 | return -1; | 1551 | return -1; |
| 1464 | } | 1552 | } |
| 1465 | 1553 | ||
| 1554 | /* cciss_add_gendisk finds a free hba[]->drv structure | ||
| 1555 | * and allocates a gendisk if needed, and sets the lunid | ||
| 1556 | * in the drvinfo structure. It returns the index into | ||
| 1557 | * the ->drv[] array, or -1 if none are free. | ||
| 1558 | * is_controller_node indicates whether highest_lun should | ||
| 1559 | * count this disk, or if it's only being added to provide | ||
| 1560 | * a means to talk to the controller in case no logical | ||
| 1561 | * drives have yet been configured. | ||
| 1562 | */ | ||
| 1563 | static int cciss_add_gendisk(ctlr_info_t *h, __u32 lunid, int controller_node) | ||
| 1564 | { | ||
| 1565 | int drv_index; | ||
| 1566 | |||
| 1567 | drv_index = cciss_find_free_drive_index(h->ctlr, controller_node); | ||
| 1568 | if (drv_index == -1) | ||
| 1569 | return -1; | ||
| 1570 | /*Check if the gendisk needs to be allocated */ | ||
| 1571 | if (!h->gendisk[drv_index]) { | ||
| 1572 | h->gendisk[drv_index] = | ||
| 1573 | alloc_disk(1 << NWD_SHIFT); | ||
| 1574 | if (!h->gendisk[drv_index]) { | ||
| 1575 | printk(KERN_ERR "cciss%d: could not " | ||
| 1576 | "allocate a new disk %d\n", | ||
| 1577 | h->ctlr, drv_index); | ||
| 1578 | return -1; | ||
| 1579 | } | ||
| 1580 | } | ||
| 1581 | h->drv[drv_index].LunID = lunid; | ||
| 1582 | |||
| 1583 | /* Don't need to mark this busy because nobody */ | ||
| 1584 | /* else knows about this disk yet to contend */ | ||
| 1585 | /* for access to it. */ | ||
| 1586 | h->drv[drv_index].busy_configuring = 0; | ||
| 1587 | wmb(); | ||
| 1588 | return drv_index; | ||
| 1589 | } | ||
| 1590 | |||
| 1591 | /* This is for the special case of a controller which | ||
| 1592 | * has no logical drives. In this case, we still need | ||
| 1593 | * to register a disk so the controller can be accessed | ||
| 1594 | * by the Array Config Utility. | ||
| 1595 | */ | ||
| 1596 | static void cciss_add_controller_node(ctlr_info_t *h) | ||
| 1597 | { | ||
| 1598 | struct gendisk *disk; | ||
| 1599 | int drv_index; | ||
| 1600 | |||
| 1601 | if (h->gendisk[0] != NULL) /* already did this? Then bail. */ | ||
| 1602 | return; | ||
| 1603 | |||
| 1604 | drv_index = cciss_add_gendisk(h, 0, 1); | ||
| 1605 | if (drv_index == -1) { | ||
| 1606 | printk(KERN_WARNING "cciss%d: could not " | ||
| 1607 | "add disk 0.\n", h->ctlr); | ||
| 1608 | return; | ||
| 1609 | } | ||
| 1610 | h->drv[drv_index].block_size = 512; | ||
| 1611 | h->drv[drv_index].nr_blocks = 0; | ||
| 1612 | h->drv[drv_index].heads = 0; | ||
| 1613 | h->drv[drv_index].sectors = 0; | ||
| 1614 | h->drv[drv_index].cylinders = 0; | ||
| 1615 | h->drv[drv_index].raid_level = -1; | ||
| 1616 | memset(h->drv[drv_index].serial_no, 0, 16); | ||
| 1617 | disk = h->gendisk[drv_index]; | ||
| 1618 | cciss_add_disk(h, disk, drv_index); | ||
| 1619 | } | ||
| 1620 | |||
| 1466 | /* This function will add and remove logical drives from the Logical | 1621 | /* This function will add and remove logical drives from the Logical |
| 1467 | * drive array of the controller and maintain persistency of ordering | 1622 | * drive array of the controller and maintain persistency of ordering |
| 1468 | * so that mount points are preserved until the next reboot. This allows | 1623 | * so that mount points are preserved until the next reboot. This allows |
| @@ -1470,15 +1625,12 @@ static int cciss_find_free_drive_index(int ctlr) | |||
| 1470 | * without a re-ordering of those drives. | 1625 | * without a re-ordering of those drives. |
| 1471 | * INPUT | 1626 | * INPUT |
| 1472 | * h = The controller to perform the operations on | 1627 | * h = The controller to perform the operations on |
| 1473 | * del_disk = The disk to remove if specified. If the value given | ||
| 1474 | * is NULL then no disk is removed. | ||
| 1475 | */ | 1628 | */ |
| 1476 | static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) | 1629 | static int rebuild_lun_table(ctlr_info_t *h, int first_time) |
| 1477 | { | 1630 | { |
| 1478 | int ctlr = h->ctlr; | 1631 | int ctlr = h->ctlr; |
| 1479 | int num_luns; | 1632 | int num_luns; |
| 1480 | ReportLunData_struct *ld_buff = NULL; | 1633 | ReportLunData_struct *ld_buff = NULL; |
| 1481 | drive_info_struct *drv = NULL; | ||
| 1482 | int return_code; | 1634 | int return_code; |
| 1483 | int listlength = 0; | 1635 | int listlength = 0; |
| 1484 | int i; | 1636 | int i; |
| @@ -1487,6 +1639,9 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) | |||
| 1487 | __u32 lunid = 0; | 1639 | __u32 lunid = 0; |
| 1488 | unsigned long flags; | 1640 | unsigned long flags; |
| 1489 | 1641 | ||
| 1642 | if (!capable(CAP_SYS_RAWIO)) | ||
| 1643 | return -EPERM; | ||
| 1644 | |||
| 1490 | /* Set busy_configuring flag for this operation */ | 1645 | /* Set busy_configuring flag for this operation */ |
| 1491 | spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); | 1646 | spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); |
| 1492 | if (h->busy_configuring) { | 1647 | if (h->busy_configuring) { |
| @@ -1494,100 +1649,100 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) | |||
| 1494 | return -EBUSY; | 1649 | return -EBUSY; |
| 1495 | } | 1650 | } |
| 1496 | h->busy_configuring = 1; | 1651 | h->busy_configuring = 1; |
| 1652 | spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); | ||
| 1497 | 1653 | ||
| 1498 | /* if del_disk is NULL then we are being called to add a new disk | 1654 | ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); |
| 1499 | * and update the logical drive table. If it is not NULL then | 1655 | if (ld_buff == NULL) |
| 1500 | * we will check if the disk is in use or not. | 1656 | goto mem_msg; |
| 1501 | */ | ||
| 1502 | if (del_disk != NULL) { | ||
| 1503 | drv = get_drv(del_disk); | ||
| 1504 | drv->busy_configuring = 1; | ||
| 1505 | spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); | ||
| 1506 | return_code = deregister_disk(del_disk, drv, 1); | ||
| 1507 | drv->busy_configuring = 0; | ||
| 1508 | h->busy_configuring = 0; | ||
| 1509 | return return_code; | ||
| 1510 | } else { | ||
| 1511 | spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); | ||
| 1512 | if (!capable(CAP_SYS_RAWIO)) | ||
| 1513 | return -EPERM; | ||
| 1514 | 1657 | ||
| 1515 | ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); | 1658 | return_code = sendcmd_withirq(CISS_REPORT_LOG, ctlr, ld_buff, |
| 1516 | if (ld_buff == NULL) | 1659 | sizeof(ReportLunData_struct), 0, |
| 1517 | goto mem_msg; | 1660 | 0, 0, TYPE_CMD); |
| 1518 | |||
| 1519 | return_code = sendcmd_withirq(CISS_REPORT_LOG, ctlr, ld_buff, | ||
| 1520 | sizeof(ReportLunData_struct), 0, | ||
| 1521 | 0, 0, TYPE_CMD); | ||
| 1522 | |||
| 1523 | if (return_code == IO_OK) { | ||
| 1524 | listlength = | ||
| 1525 | be32_to_cpu(*(__be32 *) ld_buff->LUNListLength); | ||
| 1526 | } else { /* reading number of logical volumes failed */ | ||
| 1527 | printk(KERN_WARNING "cciss: report logical volume" | ||
| 1528 | " command failed\n"); | ||
| 1529 | listlength = 0; | ||
| 1530 | goto freeret; | ||
| 1531 | } | ||
| 1532 | 1661 | ||
| 1533 | num_luns = listlength / 8; /* 8 bytes per entry */ | 1662 | if (return_code == IO_OK) |
| 1534 | if (num_luns > CISS_MAX_LUN) { | 1663 | listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength); |
| 1535 | num_luns = CISS_MAX_LUN; | 1664 | else { /* reading number of logical volumes failed */ |
| 1536 | printk(KERN_WARNING "cciss: more luns configured" | 1665 | printk(KERN_WARNING "cciss: report logical volume" |
| 1537 | " on controller than can be handled by" | 1666 | " command failed\n"); |
| 1538 | " this driver.\n"); | 1667 | listlength = 0; |
| 1668 | goto freeret; | ||
| 1669 | } | ||
| 1670 | |||
| 1671 | num_luns = listlength / 8; /* 8 bytes per entry */ | ||
| 1672 | if (num_luns > CISS_MAX_LUN) { | ||
| 1673 | num_luns = CISS_MAX_LUN; | ||
| 1674 | printk(KERN_WARNING "cciss: more luns configured" | ||
| 1675 | " on controller than can be handled by" | ||
| 1676 | " this driver.\n"); | ||
| 1677 | } | ||
| 1678 | |||
| 1679 | if (num_luns == 0) | ||
| 1680 | cciss_add_controller_node(h); | ||
| 1681 | |||
| 1682 | /* Compare controller drive array to driver's drive array | ||
| 1683 | * to see if any drives are missing on the controller due | ||
| 1684 | * to action of Array Config Utility (user deletes drive) | ||
| 1685 | * and deregister logical drives which have disappeared. | ||
| 1686 | */ | ||
| 1687 | for (i = 0; i <= h->highest_lun; i++) { | ||
| 1688 | int j; | ||
| 1689 | drv_found = 0; | ||
| 1690 | for (j = 0; j < num_luns; j++) { | ||
| 1691 | memcpy(&lunid, &ld_buff->LUN[j][0], 4); | ||
| 1692 | lunid = le32_to_cpu(lunid); | ||
| 1693 | if (h->drv[i].LunID == lunid) { | ||
| 1694 | drv_found = 1; | ||
| 1695 | break; | ||
| 1696 | } | ||
| 1539 | } | 1697 | } |
| 1698 | if (!drv_found) { | ||
| 1699 | /* Deregister it from the OS, it's gone. */ | ||
| 1700 | spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); | ||
| 1701 | h->drv[i].busy_configuring = 1; | ||
| 1702 | spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); | ||
| 1703 | return_code = deregister_disk(h->gendisk[i], | ||
| 1704 | &h->drv[i], 1); | ||
| 1705 | h->drv[i].busy_configuring = 0; | ||
| 1706 | } | ||
| 1707 | } | ||
| 1708 | |||
| 1709 | /* Compare controller drive array to driver's drive array. | ||
| 1710 | * Check for updates in the drive information and any new drives | ||
| 1711 | * on the controller due to ACU adding logical drives, or changing | ||
| 1712 | * a logical drive's size, etc. Reregister any new/changed drives | ||
| 1713 | */ | ||
| 1714 | for (i = 0; i < num_luns; i++) { | ||
| 1715 | int j; | ||
| 1540 | 1716 | ||
| 1541 | /* Compare controller drive array to drivers drive array. | 1717 | drv_found = 0; |
| 1542 | * Check for updates in the drive information and any new drives | 1718 | |
| 1543 | * on the controller. | 1719 | memcpy(&lunid, &ld_buff->LUN[i][0], 4); |
| 1720 | lunid = le32_to_cpu(lunid); | ||
| 1721 | |||
| 1722 | /* Find if the LUN is already in the drive array | ||
| 1723 | * of the driver. If so then update its info | ||
| 1724 | * if not in use. If it does not exist then find | ||
| 1725 | * the first free index and add it. | ||
| 1544 | */ | 1726 | */ |
| 1545 | for (i = 0; i < num_luns; i++) { | 1727 | for (j = 0; j <= h->highest_lun; j++) { |
| 1546 | int j; | 1728 | if (h->drv[j].raid_level != -1 && |
| 1547 | 1729 | h->drv[j].LunID == lunid) { | |
| 1548 | drv_found = 0; | 1730 | drv_index = j; |
| 1549 | 1731 | drv_found = 1; | |
| 1550 | lunid = (0xff & | 1732 | break; |
| 1551 | (unsigned int)(ld_buff->LUN[i][3])) << 24; | ||
| 1552 | lunid |= (0xff & | ||
| 1553 | (unsigned int)(ld_buff->LUN[i][2])) << 16; | ||
| 1554 | lunid |= (0xff & | ||
| 1555 | (unsigned int)(ld_buff->LUN[i][1])) << 8; | ||
| 1556 | lunid |= 0xff & (unsigned int)(ld_buff->LUN[i][0]); | ||
| 1557 | |||
| 1558 | /* Find if the LUN is already in the drive array | ||
| 1559 | * of the controller. If so then update its info | ||
| 1560 | * if not is use. If it does not exist then find | ||
| 1561 | * the first free index and add it. | ||
| 1562 | */ | ||
| 1563 | for (j = 0; j <= h->highest_lun; j++) { | ||
| 1564 | if (h->drv[j].LunID == lunid) { | ||
| 1565 | drv_index = j; | ||
| 1566 | drv_found = 1; | ||
| 1567 | } | ||
| 1568 | } | 1733 | } |
| 1734 | } | ||
| 1569 | 1735 | ||
| 1570 | /* check if the drive was found already in the array */ | 1736 | /* check if the drive was found already in the array */ |
| 1571 | if (!drv_found) { | 1737 | if (!drv_found) { |
| 1572 | drv_index = cciss_find_free_drive_index(ctlr); | 1738 | drv_index = cciss_add_gendisk(h, lunid, 0); |
| 1573 | if (drv_index == -1) | 1739 | if (drv_index == -1) |
| 1574 | goto freeret; | 1740 | goto freeret; |
| 1575 | 1741 | } | |
| 1576 | /*Check if the gendisk needs to be allocated */ | 1742 | cciss_update_drive_info(ctlr, drv_index, first_time); |
| 1577 | if (!h->gendisk[drv_index]){ | 1743 | } /* end for */ |
| 1578 | h->gendisk[drv_index] = alloc_disk(1 << NWD_SHIFT); | ||
| 1579 | if (!h->gendisk[drv_index]){ | ||
| 1580 | printk(KERN_ERR "cciss: could not allocate new disk %d\n", drv_index); | ||
| 1581 | goto mem_msg; | ||
| 1582 | } | ||
| 1583 | } | ||
| 1584 | } | ||
| 1585 | h->drv[drv_index].LunID = lunid; | ||
| 1586 | cciss_update_drive_info(ctlr, drv_index); | ||
| 1587 | } /* end for */ | ||
| 1588 | } /* end else */ | ||
| 1589 | 1744 | ||
| 1590 | freeret: | 1745 | freeret: |
| 1591 | kfree(ld_buff); | 1746 | kfree(ld_buff); |
| 1592 | h->busy_configuring = 0; | 1747 | h->busy_configuring = 0; |
| 1593 | /* We return -1 here to tell the ACU that we have registered/updated | 1748 | /* We return -1 here to tell the ACU that we have registered/updated |
| @@ -1595,8 +1750,9 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) | |||
| 1595 | * additional times. | 1750 | * additional times. |
| 1596 | */ | 1751 | */ |
| 1597 | return -1; | 1752 | return -1; |
| 1598 | mem_msg: | 1753 | mem_msg: |
| 1599 | printk(KERN_ERR "cciss: out of memory\n"); | 1754 | printk(KERN_ERR "cciss: out of memory\n"); |
| 1755 | h->busy_configuring = 0; | ||
| 1600 | goto freeret; | 1756 | goto freeret; |
| 1601 | } | 1757 | } |
| 1602 | 1758 | ||
| @@ -1652,15 +1808,15 @@ static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, | |||
| 1652 | * other than disk 0 we will call put_disk. We do not | 1808 | * other than disk 0 we will call put_disk. We do not |
| 1653 | * do this for disk 0 as we need it to be able to | 1809 | * do this for disk 0 as we need it to be able to |
| 1654 | * configure the controller. | 1810 | * configure the controller. |
| 1655 | */ | 1811 | */ |
| 1656 | if (clear_all){ | 1812 | if (clear_all){ |
| 1657 | /* This isn't pretty, but we need to find the | 1813 | /* This isn't pretty, but we need to find the |
| 1658 | * disk in our array and NULL our the pointer. | 1814 | * disk in our array and NULL our the pointer. |
| 1659 | * This is so that we will call alloc_disk if | 1815 | * This is so that we will call alloc_disk if |
| 1660 | * this index is used again later. | 1816 | * this index is used again later. |
| 1661 | */ | 1817 | */ |
| 1662 | for (i=0; i < CISS_MAX_LUN; i++){ | 1818 | for (i=0; i < CISS_MAX_LUN; i++){ |
| 1663 | if(h->gendisk[i] == disk){ | 1819 | if (h->gendisk[i] == disk) { |
| 1664 | h->gendisk[i] = NULL; | 1820 | h->gendisk[i] = NULL; |
| 1665 | break; | 1821 | break; |
| 1666 | } | 1822 | } |
| @@ -1688,7 +1844,7 @@ static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, | |||
| 1688 | if (drv == h->drv + h->highest_lun) { | 1844 | if (drv == h->drv + h->highest_lun) { |
| 1689 | /* if so, find the new hightest lun */ | 1845 | /* if so, find the new hightest lun */ |
| 1690 | int i, newhighest = -1; | 1846 | int i, newhighest = -1; |
| 1691 | for (i = 0; i < h->highest_lun; i++) { | 1847 | for (i = 0; i <= h->highest_lun; i++) { |
| 1692 | /* if the disk has size > 0, it is available */ | 1848 | /* if the disk has size > 0, it is available */ |
| 1693 | if (h->drv[i].heads) | 1849 | if (h->drv[i].heads) |
| 1694 | newhighest = i; | 1850 | newhighest = i; |
| @@ -3199,136 +3355,9 @@ err_out_free_res: | |||
| 3199 | return err; | 3355 | return err; |
| 3200 | } | 3356 | } |
| 3201 | 3357 | ||
| 3202 | /* | 3358 | /* Function to find the first free pointer into our hba[] array |
| 3203 | * Gets information about the local volumes attached to the controller. | 3359 | * Returns -1 if no free entries are left. |
| 3204 | */ | 3360 | */ |
| 3205 | static void cciss_getgeometry(int cntl_num) | ||
| 3206 | { | ||
| 3207 | ReportLunData_struct *ld_buff; | ||
| 3208 | InquiryData_struct *inq_buff; | ||
| 3209 | int return_code; | ||
| 3210 | int i; | ||
| 3211 | int listlength = 0; | ||
| 3212 | __u32 lunid = 0; | ||
| 3213 | unsigned block_size; | ||
| 3214 | sector_t total_size; | ||
| 3215 | |||
| 3216 | ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); | ||
| 3217 | if (ld_buff == NULL) { | ||
| 3218 | printk(KERN_ERR "cciss: out of memory\n"); | ||
| 3219 | return; | ||
| 3220 | } | ||
| 3221 | inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); | ||
| 3222 | if (inq_buff == NULL) { | ||
| 3223 | printk(KERN_ERR "cciss: out of memory\n"); | ||
| 3224 | kfree(ld_buff); | ||
| 3225 | return; | ||
| 3226 | } | ||
| 3227 | /* Get the firmware version */ | ||
| 3228 | return_code = sendcmd(CISS_INQUIRY, cntl_num, inq_buff, | ||
| 3229 | sizeof(InquiryData_struct), 0, 0, 0, NULL, | ||
| 3230 | TYPE_CMD); | ||
| 3231 | if (return_code == IO_OK) { | ||
| 3232 | hba[cntl_num]->firm_ver[0] = inq_buff->data_byte[32]; | ||
| 3233 | hba[cntl_num]->firm_ver[1] = inq_buff->data_byte[33]; | ||
| 3234 | hba[cntl_num]->firm_ver[2] = inq_buff->data_byte[34]; | ||
| 3235 | hba[cntl_num]->firm_ver[3] = inq_buff->data_byte[35]; | ||
| 3236 | } else { /* send command failed */ | ||
| 3237 | |||
| 3238 | printk(KERN_WARNING "cciss: unable to determine firmware" | ||
| 3239 | " version of controller\n"); | ||
| 3240 | } | ||
| 3241 | /* Get the number of logical volumes */ | ||
| 3242 | return_code = sendcmd(CISS_REPORT_LOG, cntl_num, ld_buff, | ||
| 3243 | sizeof(ReportLunData_struct), 0, 0, 0, NULL, | ||
| 3244 | TYPE_CMD); | ||
| 3245 | |||
| 3246 | if (return_code == IO_OK) { | ||
| 3247 | #ifdef CCISS_DEBUG | ||
| 3248 | printk("LUN Data\n--------------------------\n"); | ||
| 3249 | #endif /* CCISS_DEBUG */ | ||
| 3250 | |||
| 3251 | listlength |= | ||
| 3252 | (0xff & (unsigned int)(ld_buff->LUNListLength[0])) << 24; | ||
| 3253 | listlength |= | ||
| 3254 | (0xff & (unsigned int)(ld_buff->LUNListLength[1])) << 16; | ||
| 3255 | listlength |= | ||
| 3256 | (0xff & (unsigned int)(ld_buff->LUNListLength[2])) << 8; | ||
| 3257 | listlength |= 0xff & (unsigned int)(ld_buff->LUNListLength[3]); | ||
| 3258 | } else { /* reading number of logical volumes failed */ | ||
| 3259 | |||
| 3260 | printk(KERN_WARNING "cciss: report logical volume" | ||
| 3261 | " command failed\n"); | ||
| 3262 | listlength = 0; | ||
| 3263 | } | ||
| 3264 | hba[cntl_num]->num_luns = listlength / 8; // 8 bytes pre entry | ||
| 3265 | if (hba[cntl_num]->num_luns > CISS_MAX_LUN) { | ||
| 3266 | printk(KERN_ERR | ||
| 3267 | "ciss: only %d number of logical volumes supported\n", | ||
| 3268 | CISS_MAX_LUN); | ||
| 3269 | hba[cntl_num]->num_luns = CISS_MAX_LUN; | ||
| 3270 | } | ||
| 3271 | #ifdef CCISS_DEBUG | ||
| 3272 | printk(KERN_DEBUG "Length = %x %x %x %x = %d\n", | ||
| 3273 | ld_buff->LUNListLength[0], ld_buff->LUNListLength[1], | ||
| 3274 | ld_buff->LUNListLength[2], ld_buff->LUNListLength[3], | ||
| 3275 | hba[cntl_num]->num_luns); | ||
| 3276 | #endif /* CCISS_DEBUG */ | ||
| 3277 | |||
| 3278 | hba[cntl_num]->highest_lun = hba[cntl_num]->num_luns - 1; | ||
| 3279 | for (i = 0; i < CISS_MAX_LUN; i++) { | ||
| 3280 | if (i < hba[cntl_num]->num_luns) { | ||
| 3281 | lunid = (0xff & (unsigned int)(ld_buff->LUN[i][3])) | ||
| 3282 | << 24; | ||
| 3283 | lunid |= (0xff & (unsigned int)(ld_buff->LUN[i][2])) | ||
| 3284 | << 16; | ||
| 3285 | lunid |= (0xff & (unsigned int)(ld_buff->LUN[i][1])) | ||
| 3286 | << 8; | ||
| 3287 | lunid |= 0xff & (unsigned int)(ld_buff->LUN[i][0]); | ||
| 3288 | |||
| 3289 | hba[cntl_num]->drv[i].LunID = lunid; | ||
| 3290 | |||
| 3291 | #ifdef CCISS_DEBUG | ||
| 3292 | printk(KERN_DEBUG "LUN[%d]: %x %x %x %x = %x\n", i, | ||
| 3293 | ld_buff->LUN[i][0], ld_buff->LUN[i][1], | ||
| 3294 | ld_buff->LUN[i][2], ld_buff->LUN[i][3], | ||
| 3295 | hba[cntl_num]->drv[i].LunID); | ||
| 3296 | #endif /* CCISS_DEBUG */ | ||
| 3297 | |||
| 3298 | /* testing to see if 16-byte CDBs are already being used */ | ||
| 3299 | if(hba[cntl_num]->cciss_read == CCISS_READ_16) { | ||
| 3300 | cciss_read_capacity_16(cntl_num, i, 0, | ||
| 3301 | &total_size, &block_size); | ||
| 3302 | goto geo_inq; | ||
| 3303 | } | ||
| 3304 | cciss_read_capacity(cntl_num, i, 0, &total_size, &block_size); | ||
| 3305 | |||
| 3306 | /* If read_capacity returns all F's the logical is >2TB */ | ||
| 3307 | /* so we switch to 16-byte CDBs for all read/write ops */ | ||
| 3308 | if(total_size == 0xFFFFFFFFULL) { | ||
| 3309 | cciss_read_capacity_16(cntl_num, i, 0, | ||
| 3310 | &total_size, &block_size); | ||
| 3311 | hba[cntl_num]->cciss_read = CCISS_READ_16; | ||
| 3312 | hba[cntl_num]->cciss_write = CCISS_WRITE_16; | ||
| 3313 | } else { | ||
| 3314 | hba[cntl_num]->cciss_read = CCISS_READ_10; | ||
| 3315 | hba[cntl_num]->cciss_write = CCISS_WRITE_10; | ||
| 3316 | } | ||
| 3317 | geo_inq: | ||
| 3318 | cciss_geometry_inquiry(cntl_num, i, 0, total_size, | ||
| 3319 | block_size, inq_buff, | ||
| 3320 | &hba[cntl_num]->drv[i]); | ||
| 3321 | } else { | ||
| 3322 | /* initialize raid_level to indicate a free space */ | ||
| 3323 | hba[cntl_num]->drv[i].raid_level = -1; | ||
| 3324 | } | ||
| 3325 | } | ||
| 3326 | kfree(ld_buff); | ||
| 3327 | kfree(inq_buff); | ||
| 3328 | } | ||
| 3329 | |||
| 3330 | /* Function to find the first free pointer into our hba[] array */ | ||
| 3331 | /* Returns -1 if no free entries are left. */ | ||
| 3332 | static int alloc_cciss_hba(void) | 3361 | static int alloc_cciss_hba(void) |
| 3333 | { | 3362 | { |
| 3334 | int i; | 3363 | int i; |
| @@ -3340,11 +3369,6 @@ static int alloc_cciss_hba(void) | |||
| 3340 | p = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL); | 3369 | p = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL); |
| 3341 | if (!p) | 3370 | if (!p) |
| 3342 | goto Enomem; | 3371 | goto Enomem; |
| 3343 | p->gendisk[0] = alloc_disk(1 << NWD_SHIFT); | ||
| 3344 | if (!p->gendisk[0]) { | ||
| 3345 | kfree(p); | ||
| 3346 | goto Enomem; | ||
| 3347 | } | ||
| 3348 | hba[i] = p; | 3372 | hba[i] = p; |
| 3349 | return i; | 3373 | return i; |
| 3350 | } | 3374 | } |
| @@ -3472,11 +3496,13 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, | |||
| 3472 | ((hba[i]->nr_cmds + BITS_PER_LONG - | 3496 | ((hba[i]->nr_cmds + BITS_PER_LONG - |
| 3473 | 1) / BITS_PER_LONG) * sizeof(unsigned long)); | 3497 | 1) / BITS_PER_LONG) * sizeof(unsigned long)); |
| 3474 | 3498 | ||
| 3475 | #ifdef CCISS_DEBUG | 3499 | hba[i]->num_luns = 0; |
| 3476 | printk(KERN_DEBUG "Scanning for drives on controller cciss%d\n", i); | 3500 | hba[i]->highest_lun = -1; |
| 3477 | #endif /* CCISS_DEBUG */ | 3501 | for (j = 0; j < CISS_MAX_LUN; j++) { |
| 3478 | 3502 | hba[i]->drv[j].raid_level = -1; | |
| 3479 | cciss_getgeometry(i); | 3503 | hba[i]->drv[j].queue = NULL; |
| 3504 | hba[i]->gendisk[j] = NULL; | ||
| 3505 | } | ||
| 3480 | 3506 | ||
| 3481 | cciss_scsi_setup(i); | 3507 | cciss_scsi_setup(i); |
| 3482 | 3508 | ||
| @@ -3489,76 +3515,10 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, | |||
| 3489 | 3515 | ||
| 3490 | hba[i]->busy_initializing = 0; | 3516 | hba[i]->busy_initializing = 0; |
| 3491 | 3517 | ||
| 3492 | do { | 3518 | rebuild_lun_table(hba[i], 1); |
| 3493 | drive_info_struct *drv = &(hba[i]->drv[j]); | ||
| 3494 | struct gendisk *disk = hba[i]->gendisk[j]; | ||
| 3495 | struct request_queue *q; | ||
| 3496 | |||
| 3497 | /* Check if the disk was allocated already */ | ||
| 3498 | if (!disk){ | ||
| 3499 | hba[i]->gendisk[j] = alloc_disk(1 << NWD_SHIFT); | ||
| 3500 | disk = hba[i]->gendisk[j]; | ||
| 3501 | } | ||
| 3502 | |||
| 3503 | /* Check that the disk was able to be allocated */ | ||
| 3504 | if (!disk) { | ||
| 3505 | printk(KERN_ERR "cciss: unable to allocate memory for disk %d\n", j); | ||
| 3506 | goto clean4; | ||
| 3507 | } | ||
| 3508 | |||
| 3509 | q = blk_init_queue(do_cciss_request, &hba[i]->lock); | ||
| 3510 | if (!q) { | ||
| 3511 | printk(KERN_ERR | ||
| 3512 | "cciss: unable to allocate queue for disk %d\n", | ||
| 3513 | j); | ||
| 3514 | goto clean4; | ||
| 3515 | } | ||
| 3516 | drv->queue = q; | ||
| 3517 | |||
| 3518 | blk_queue_bounce_limit(q, hba[i]->pdev->dma_mask); | ||
| 3519 | |||
| 3520 | /* This is a hardware imposed limit. */ | ||
| 3521 | blk_queue_max_hw_segments(q, MAXSGENTRIES); | ||
| 3522 | |||
| 3523 | /* This is a limit in the driver and could be eliminated. */ | ||
| 3524 | blk_queue_max_phys_segments(q, MAXSGENTRIES); | ||
| 3525 | |||
| 3526 | blk_queue_max_sectors(q, hba[i]->cciss_max_sectors); | ||
| 3527 | |||
| 3528 | blk_queue_softirq_done(q, cciss_softirq_done); | ||
| 3529 | |||
| 3530 | q->queuedata = hba[i]; | ||
| 3531 | sprintf(disk->disk_name, "cciss/c%dd%d", i, j); | ||
| 3532 | disk->major = hba[i]->major; | ||
| 3533 | disk->first_minor = j << NWD_SHIFT; | ||
| 3534 | disk->fops = &cciss_fops; | ||
| 3535 | disk->queue = q; | ||
| 3536 | disk->private_data = drv; | ||
| 3537 | disk->driverfs_dev = &pdev->dev; | ||
| 3538 | /* we must register the controller even if no disks exist */ | ||
| 3539 | /* this is for the online array utilities */ | ||
| 3540 | if (!drv->heads && j) | ||
| 3541 | continue; | ||
| 3542 | blk_queue_hardsect_size(q, drv->block_size); | ||
| 3543 | set_capacity(disk, drv->nr_blocks); | ||
| 3544 | j++; | ||
| 3545 | } while (j <= hba[i]->highest_lun); | ||
| 3546 | |||
| 3547 | /* Make sure all queue data is written out before */ | ||
| 3548 | /* interrupt handler, triggered by add_disk, */ | ||
| 3549 | /* is allowed to start them. */ | ||
| 3550 | wmb(); | ||
| 3551 | |||
| 3552 | for (j = 0; j <= hba[i]->highest_lun; j++) | ||
| 3553 | add_disk(hba[i]->gendisk[j]); | ||
| 3554 | |||
| 3555 | /* we must register the controller even if no disks exist */ | ||
| 3556 | if (hba[i]->highest_lun == -1) | ||
| 3557 | add_disk(hba[i]->gendisk[0]); | ||
| 3558 | |||
| 3559 | return 1; | 3519 | return 1; |
| 3560 | 3520 | ||
| 3561 | clean4: | 3521 | clean4: |
| 3562 | #ifdef CONFIG_CISS_SCSI_TAPE | 3522 | #ifdef CONFIG_CISS_SCSI_TAPE |
| 3563 | kfree(hba[i]->scsi_rejects.complete); | 3523 | kfree(hba[i]->scsi_rejects.complete); |
| 3564 | #endif | 3524 | #endif |
| @@ -3573,9 +3533,9 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, | |||
| 3573 | hba[i]->errinfo_pool, | 3533 | hba[i]->errinfo_pool, |
| 3574 | hba[i]->errinfo_pool_dhandle); | 3534 | hba[i]->errinfo_pool_dhandle); |
| 3575 | free_irq(hba[i]->intr[SIMPLE_MODE_INT], hba[i]); | 3535 | free_irq(hba[i]->intr[SIMPLE_MODE_INT], hba[i]); |
| 3576 | clean2: | 3536 | clean2: |
| 3577 | unregister_blkdev(hba[i]->major, hba[i]->devname); | 3537 | unregister_blkdev(hba[i]->major, hba[i]->devname); |
| 3578 | clean1: | 3538 | clean1: |
| 3579 | hba[i]->busy_initializing = 0; | 3539 | hba[i]->busy_initializing = 0; |
| 3580 | /* cleanup any queues that may have been initialized */ | 3540 | /* cleanup any queues that may have been initialized */ |
| 3581 | for (j=0; j <= hba[i]->highest_lun; j++){ | 3541 | for (j=0; j <= hba[i]->highest_lun; j++){ |
| @@ -3654,7 +3614,9 @@ static void __devexit cciss_remove_one(struct pci_dev *pdev) | |||
| 3654 | } | 3614 | } |
| 3655 | } | 3615 | } |
| 3656 | 3616 | ||
| 3617 | #ifdef CONFIG_CISS_SCSI_TAPE | ||
| 3657 | cciss_unregister_scsi(i); /* unhook from SCSI subsystem */ | 3618 | cciss_unregister_scsi(i); /* unhook from SCSI subsystem */ |
| 3619 | #endif | ||
| 3658 | 3620 | ||
| 3659 | cciss_shutdown(pdev); | 3621 | cciss_shutdown(pdev); |
| 3660 | 3622 | ||
diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h index b70988dd33ec..24a7efa993ab 100644 --- a/drivers/block/cciss.h +++ b/drivers/block/cciss.h | |||
| @@ -39,6 +39,8 @@ typedef struct _drive_info_struct | |||
| 39 | *to prevent it from being opened or it's queue | 39 | *to prevent it from being opened or it's queue |
| 40 | *from being started. | 40 | *from being started. |
| 41 | */ | 41 | */ |
| 42 | __u8 serial_no[16]; /* from inquiry page 0x83, */ | ||
| 43 | /* not necc. null terminated. */ | ||
| 42 | } drive_info_struct; | 44 | } drive_info_struct; |
| 43 | 45 | ||
| 44 | #ifdef CONFIG_CISS_SCSI_TAPE | 46 | #ifdef CONFIG_CISS_SCSI_TAPE |
diff --git a/drivers/block/cciss_scsi.c b/drivers/block/cciss_scsi.c index e4bf9a11ca0d..e1233aabda77 100644 --- a/drivers/block/cciss_scsi.c +++ b/drivers/block/cciss_scsi.c | |||
| @@ -358,23 +358,68 @@ find_bus_target_lun(int ctlr, int *bus, int *target, int *lun) | |||
| 358 | } | 358 | } |
| 359 | return (!found); | 359 | return (!found); |
| 360 | } | 360 | } |
| 361 | struct scsi2map { | ||
| 362 | char scsi3addr[8]; | ||
| 363 | int bus, target, lun; | ||
| 364 | }; | ||
| 361 | 365 | ||
| 362 | static int | 366 | static int |
| 363 | cciss_scsi_add_entry(int ctlr, int hostno, | 367 | cciss_scsi_add_entry(int ctlr, int hostno, |
| 364 | unsigned char *scsi3addr, int devtype) | 368 | unsigned char *scsi3addr, int devtype, |
| 369 | struct scsi2map *added, int *nadded) | ||
| 365 | { | 370 | { |
| 366 | /* assumes hba[ctlr]->scsi_ctlr->lock is held */ | 371 | /* assumes hba[ctlr]->scsi_ctlr->lock is held */ |
| 367 | int n = ccissscsi[ctlr].ndevices; | 372 | int n = ccissscsi[ctlr].ndevices; |
| 368 | struct cciss_scsi_dev_t *sd; | 373 | struct cciss_scsi_dev_t *sd; |
| 374 | int i, bus, target, lun; | ||
| 375 | unsigned char addr1[8], addr2[8]; | ||
| 369 | 376 | ||
| 370 | if (n >= CCISS_MAX_SCSI_DEVS_PER_HBA) { | 377 | if (n >= CCISS_MAX_SCSI_DEVS_PER_HBA) { |
| 371 | printk("cciss%d: Too many devices, " | 378 | printk("cciss%d: Too many devices, " |
| 372 | "some will be inaccessible.\n", ctlr); | 379 | "some will be inaccessible.\n", ctlr); |
| 373 | return -1; | 380 | return -1; |
| 374 | } | 381 | } |
| 382 | |||
| 383 | bus = target = -1; | ||
| 384 | lun = 0; | ||
| 385 | /* Is this device a non-zero lun of a multi-lun device */ | ||
| 386 | /* byte 4 of the 8-byte LUN addr will contain the logical unit no. */ | ||
| 387 | if (scsi3addr[4] != 0) { | ||
| 388 | /* Search through our list and find the device which */ | ||
| 389 | /* has the same 8 byte LUN address, excepting byte 4. */ | ||
| 390 | /* Assign the same bus and target for this new LUN. */ | ||
| 391 | /* Use the logical unit number from the firmware. */ | ||
| 392 | memcpy(addr1, scsi3addr, 8); | ||
| 393 | addr1[4] = 0; | ||
| 394 | for (i = 0; i < n; i++) { | ||
| 395 | sd = &ccissscsi[ctlr].dev[i]; | ||
| 396 | memcpy(addr2, sd->scsi3addr, 8); | ||
| 397 | addr2[4] = 0; | ||
| 398 | /* differ only in byte 4? */ | ||
| 399 | if (memcmp(addr1, addr2, 8) == 0) { | ||
| 400 | bus = sd->bus; | ||
| 401 | target = sd->target; | ||
| 402 | lun = scsi3addr[4]; | ||
| 403 | break; | ||
| 404 | } | ||
| 405 | } | ||
| 406 | } | ||
| 407 | |||
| 375 | sd = &ccissscsi[ctlr].dev[n]; | 408 | sd = &ccissscsi[ctlr].dev[n]; |
| 376 | if (find_bus_target_lun(ctlr, &sd->bus, &sd->target, &sd->lun) != 0) | 409 | if (lun == 0) { |
| 377 | return -1; | 410 | if (find_bus_target_lun(ctlr, |
| 411 | &sd->bus, &sd->target, &sd->lun) != 0) | ||
| 412 | return -1; | ||
| 413 | } else { | ||
| 414 | sd->bus = bus; | ||
| 415 | sd->target = target; | ||
| 416 | sd->lun = lun; | ||
| 417 | } | ||
| 418 | added[*nadded].bus = sd->bus; | ||
| 419 | added[*nadded].target = sd->target; | ||
| 420 | added[*nadded].lun = sd->lun; | ||
| 421 | (*nadded)++; | ||
| 422 | |||
| 378 | memcpy(&sd->scsi3addr[0], scsi3addr, 8); | 423 | memcpy(&sd->scsi3addr[0], scsi3addr, 8); |
| 379 | sd->devtype = devtype; | 424 | sd->devtype = devtype; |
| 380 | ccissscsi[ctlr].ndevices++; | 425 | ccissscsi[ctlr].ndevices++; |
| @@ -390,7 +435,8 @@ cciss_scsi_add_entry(int ctlr, int hostno, | |||
| 390 | } | 435 | } |
| 391 | 436 | ||
| 392 | static void | 437 | static void |
| 393 | cciss_scsi_remove_entry(int ctlr, int hostno, int entry) | 438 | cciss_scsi_remove_entry(int ctlr, int hostno, int entry, |
| 439 | struct scsi2map *removed, int *nremoved) | ||
| 394 | { | 440 | { |
| 395 | /* assumes hba[ctlr]->scsi_ctlr->lock is held */ | 441 | /* assumes hba[ctlr]->scsi_ctlr->lock is held */ |
| 396 | int i; | 442 | int i; |
| @@ -398,6 +444,10 @@ cciss_scsi_remove_entry(int ctlr, int hostno, int entry) | |||
| 398 | 444 | ||
| 399 | if (entry < 0 || entry >= CCISS_MAX_SCSI_DEVS_PER_HBA) return; | 445 | if (entry < 0 || entry >= CCISS_MAX_SCSI_DEVS_PER_HBA) return; |
| 400 | sd = ccissscsi[ctlr].dev[entry]; | 446 | sd = ccissscsi[ctlr].dev[entry]; |
| 447 | removed[*nremoved].bus = sd.bus; | ||
| 448 | removed[*nremoved].target = sd.target; | ||
| 449 | removed[*nremoved].lun = sd.lun; | ||
| 450 | (*nremoved)++; | ||
| 401 | for (i=entry;i<ccissscsi[ctlr].ndevices-1;i++) | 451 | for (i=entry;i<ccissscsi[ctlr].ndevices-1;i++) |
| 402 | ccissscsi[ctlr].dev[i] = ccissscsi[ctlr].dev[i+1]; | 452 | ccissscsi[ctlr].dev[i] = ccissscsi[ctlr].dev[i+1]; |
| 403 | ccissscsi[ctlr].ndevices--; | 453 | ccissscsi[ctlr].ndevices--; |
| @@ -417,6 +467,26 @@ cciss_scsi_remove_entry(int ctlr, int hostno, int entry) | |||
| 417 | (a)[1] == (b)[1] && \ | 467 | (a)[1] == (b)[1] && \ |
| 418 | (a)[0] == (b)[0]) | 468 | (a)[0] == (b)[0]) |
| 419 | 469 | ||
| 470 | static void fixup_botched_add(int ctlr, char *scsi3addr) | ||
| 471 | { | ||
| 472 | /* called when scsi_add_device fails in order to re-adjust */ | ||
| 473 | /* ccissscsi[] to match the mid layer's view. */ | ||
| 474 | unsigned long flags; | ||
| 475 | int i, j; | ||
| 476 | CPQ_TAPE_LOCK(ctlr, flags); | ||
| 477 | for (i = 0; i < ccissscsi[ctlr].ndevices; i++) { | ||
| 478 | if (memcmp(scsi3addr, | ||
| 479 | ccissscsi[ctlr].dev[i].scsi3addr, 8) == 0) { | ||
| 480 | for (j = i; j < ccissscsi[ctlr].ndevices-1; j++) | ||
| 481 | ccissscsi[ctlr].dev[j] = | ||
| 482 | ccissscsi[ctlr].dev[j+1]; | ||
| 483 | ccissscsi[ctlr].ndevices--; | ||
| 484 | break; | ||
| 485 | } | ||
| 486 | } | ||
| 487 | CPQ_TAPE_UNLOCK(ctlr, flags); | ||
| 488 | } | ||
| 489 | |||
| 420 | static int | 490 | static int |
| 421 | adjust_cciss_scsi_table(int ctlr, int hostno, | 491 | adjust_cciss_scsi_table(int ctlr, int hostno, |
| 422 | struct cciss_scsi_dev_t sd[], int nsds) | 492 | struct cciss_scsi_dev_t sd[], int nsds) |
| @@ -429,13 +499,33 @@ adjust_cciss_scsi_table(int ctlr, int hostno, | |||
| 429 | int i,j, found, changes=0; | 499 | int i,j, found, changes=0; |
| 430 | struct cciss_scsi_dev_t *csd; | 500 | struct cciss_scsi_dev_t *csd; |
| 431 | unsigned long flags; | 501 | unsigned long flags; |
| 502 | struct scsi2map *added, *removed; | ||
| 503 | int nadded, nremoved; | ||
| 504 | struct Scsi_Host *sh = NULL; | ||
| 505 | |||
| 506 | added = kzalloc(sizeof(*added) * CCISS_MAX_SCSI_DEVS_PER_HBA, | ||
| 507 | GFP_KERNEL); | ||
| 508 | removed = kzalloc(sizeof(*removed) * CCISS_MAX_SCSI_DEVS_PER_HBA, | ||
| 509 | GFP_KERNEL); | ||
| 510 | |||
| 511 | if (!added || !removed) { | ||
| 512 | printk(KERN_WARNING "cciss%d: Out of memory in " | ||
| 513 | "adjust_cciss_scsi_table\n", ctlr); | ||
| 514 | goto free_and_out; | ||
| 515 | } | ||
| 432 | 516 | ||
| 433 | CPQ_TAPE_LOCK(ctlr, flags); | 517 | CPQ_TAPE_LOCK(ctlr, flags); |
| 434 | 518 | ||
| 519 | if (hostno != -1) /* if it's not the first time... */ | ||
| 520 | sh = ((struct cciss_scsi_adapter_data_t *) | ||
| 521 | hba[ctlr]->scsi_ctlr)->scsi_host; | ||
| 522 | |||
| 435 | /* find any devices in ccissscsi[] that are not in | 523 | /* find any devices in ccissscsi[] that are not in |
| 436 | sd[] and remove them from ccissscsi[] */ | 524 | sd[] and remove them from ccissscsi[] */ |
| 437 | 525 | ||
| 438 | i = 0; | 526 | i = 0; |
| 527 | nremoved = 0; | ||
| 528 | nadded = 0; | ||
| 439 | while(i<ccissscsi[ctlr].ndevices) { | 529 | while(i<ccissscsi[ctlr].ndevices) { |
| 440 | csd = &ccissscsi[ctlr].dev[i]; | 530 | csd = &ccissscsi[ctlr].dev[i]; |
| 441 | found=0; | 531 | found=0; |
| @@ -455,8 +545,9 @@ adjust_cciss_scsi_table(int ctlr, int hostno, | |||
| 455 | /* printk("cciss%d: %s device c%db%dt%dl%d removed.\n", | 545 | /* printk("cciss%d: %s device c%db%dt%dl%d removed.\n", |
| 456 | ctlr, scsi_device_type(csd->devtype), hostno, | 546 | ctlr, scsi_device_type(csd->devtype), hostno, |
| 457 | csd->bus, csd->target, csd->lun); */ | 547 | csd->bus, csd->target, csd->lun); */ |
| 458 | cciss_scsi_remove_entry(ctlr, hostno, i); | 548 | cciss_scsi_remove_entry(ctlr, hostno, i, |
| 459 | /* note, i not incremented */ | 549 | removed, &nremoved); |
| 550 | /* remove ^^^, hence i not incremented */ | ||
| 460 | } | 551 | } |
| 461 | else if (found == 1) { /* device is different kind */ | 552 | else if (found == 1) { /* device is different kind */ |
| 462 | changes++; | 553 | changes++; |
| @@ -464,8 +555,15 @@ adjust_cciss_scsi_table(int ctlr, int hostno, | |||
| 464 | "(device type now %s).\n", | 555 | "(device type now %s).\n", |
| 465 | ctlr, hostno, csd->bus, csd->target, csd->lun, | 556 | ctlr, hostno, csd->bus, csd->target, csd->lun, |
| 466 | scsi_device_type(csd->devtype)); | 557 | scsi_device_type(csd->devtype)); |
| 558 | cciss_scsi_remove_entry(ctlr, hostno, i, | ||
| 559 | removed, &nremoved); | ||
| 560 | /* remove ^^^, hence i not incremented */ | ||
| 561 | if (cciss_scsi_add_entry(ctlr, hostno, | ||
| 562 | &sd[j].scsi3addr[0], sd[j].devtype, | ||
| 563 | added, &nadded) != 0) | ||
| 564 | /* we just removed one, so add can't fail. */ | ||
| 565 | BUG(); | ||
| 467 | csd->devtype = sd[j].devtype; | 566 | csd->devtype = sd[j].devtype; |
| 468 | i++; /* so just move along. */ | ||
| 469 | } else /* device is same as it ever was, */ | 567 | } else /* device is same as it ever was, */ |
| 470 | i++; /* so just move along. */ | 568 | i++; /* so just move along. */ |
| 471 | } | 569 | } |
| @@ -489,7 +587,9 @@ adjust_cciss_scsi_table(int ctlr, int hostno, | |||
| 489 | if (!found) { | 587 | if (!found) { |
| 490 | changes++; | 588 | changes++; |
| 491 | if (cciss_scsi_add_entry(ctlr, hostno, | 589 | if (cciss_scsi_add_entry(ctlr, hostno, |
| 492 | &sd[i].scsi3addr[0], sd[i].devtype) != 0) | 590 | |
| 591 | &sd[i].scsi3addr[0], sd[i].devtype, | ||
| 592 | added, &nadded) != 0) | ||
| 493 | break; | 593 | break; |
| 494 | } else if (found == 1) { | 594 | } else if (found == 1) { |
| 495 | /* should never happen... */ | 595 | /* should never happen... */ |
| @@ -501,9 +601,50 @@ adjust_cciss_scsi_table(int ctlr, int hostno, | |||
| 501 | } | 601 | } |
| 502 | CPQ_TAPE_UNLOCK(ctlr, flags); | 602 | CPQ_TAPE_UNLOCK(ctlr, flags); |
| 503 | 603 | ||
| 504 | if (!changes) | 604 | /* Don't notify scsi mid layer of any changes the first time through */ |
| 505 | printk("cciss%d: No device changes detected.\n", ctlr); | 605 | /* (or if there are no changes) scsi_scan_host will do it later the */ |
| 606 | /* first time through. */ | ||
| 607 | if (hostno == -1 || !changes) | ||
| 608 | goto free_and_out; | ||
| 609 | |||
| 610 | /* Notify scsi mid layer of any removed devices */ | ||
| 611 | for (i = 0; i < nremoved; i++) { | ||
| 612 | struct scsi_device *sdev = | ||
| 613 | scsi_device_lookup(sh, removed[i].bus, | ||
| 614 | removed[i].target, removed[i].lun); | ||
| 615 | if (sdev != NULL) { | ||
| 616 | scsi_remove_device(sdev); | ||
| 617 | scsi_device_put(sdev); | ||
| 618 | } else { | ||
| 619 | /* We don't expect to get here. */ | ||
| 620 | /* future cmds to this device will get selection */ | ||
| 621 | /* timeout as if the device was gone. */ | ||
| 622 | printk(KERN_WARNING "cciss%d: didn't find " | ||
| 623 | "c%db%dt%dl%d\n for removal.", | ||
| 624 | ctlr, hostno, removed[i].bus, | ||
| 625 | removed[i].target, removed[i].lun); | ||
| 626 | } | ||
| 627 | } | ||
| 628 | |||
| 629 | /* Notify scsi mid layer of any added devices */ | ||
| 630 | for (i = 0; i < nadded; i++) { | ||
| 631 | int rc; | ||
| 632 | rc = scsi_add_device(sh, added[i].bus, | ||
| 633 | added[i].target, added[i].lun); | ||
| 634 | if (rc == 0) | ||
| 635 | continue; | ||
| 636 | printk(KERN_WARNING "cciss%d: scsi_add_device " | ||
| 637 | "c%db%dt%dl%d failed, device not added.\n", | ||
| 638 | ctlr, hostno, | ||
| 639 | added[i].bus, added[i].target, added[i].lun); | ||
| 640 | /* now we have to remove it from ccissscsi, */ | ||
| 641 | /* since it didn't get added to scsi mid layer */ | ||
| 642 | fixup_botched_add(ctlr, added[i].scsi3addr); | ||
| 643 | } | ||
| 506 | 644 | ||
| 645 | free_and_out: | ||
| 646 | kfree(added); | ||
| 647 | kfree(removed); | ||
| 507 | return 0; | 648 | return 0; |
| 508 | } | 649 | } |
| 509 | 650 | ||
| @@ -1355,32 +1496,6 @@ cciss_unregister_scsi(int ctlr) | |||
| 1355 | } | 1496 | } |
| 1356 | 1497 | ||
| 1357 | static int | 1498 | static int |
| 1358 | cciss_register_scsi(int ctlr) | ||
| 1359 | { | ||
| 1360 | unsigned long flags; | ||
| 1361 | |||
| 1362 | CPQ_TAPE_LOCK(ctlr, flags); | ||
| 1363 | |||
| 1364 | /* Since this is really a block driver, the SCSI core may not be | ||
| 1365 | initialized at init time, in which case, calling scsi_register_host | ||
| 1366 | would hang. Instead, we do it later, via /proc filesystem | ||
| 1367 | and rc scripts, when we know SCSI core is good to go. */ | ||
| 1368 | |||
| 1369 | /* Only register if SCSI devices are detected. */ | ||
| 1370 | if (ccissscsi[ctlr].ndevices != 0) { | ||
| 1371 | ((struct cciss_scsi_adapter_data_t *) | ||
| 1372 | hba[ctlr]->scsi_ctlr)->registered = 1; | ||
| 1373 | CPQ_TAPE_UNLOCK(ctlr, flags); | ||
| 1374 | return cciss_scsi_detect(ctlr); | ||
| 1375 | } | ||
| 1376 | CPQ_TAPE_UNLOCK(ctlr, flags); | ||
| 1377 | printk(KERN_INFO | ||
| 1378 | "cciss%d: No appropriate SCSI device detected, " | ||
| 1379 | "SCSI subsystem not engaged.\n", ctlr); | ||
| 1380 | return 0; | ||
| 1381 | } | ||
| 1382 | |||
| 1383 | static int | ||
| 1384 | cciss_engage_scsi(int ctlr) | 1499 | cciss_engage_scsi(int ctlr) |
| 1385 | { | 1500 | { |
| 1386 | struct cciss_scsi_adapter_data_t *sa; | 1501 | struct cciss_scsi_adapter_data_t *sa; |
| @@ -1391,15 +1506,15 @@ cciss_engage_scsi(int ctlr) | |||
| 1391 | sa = (struct cciss_scsi_adapter_data_t *) hba[ctlr]->scsi_ctlr; | 1506 | sa = (struct cciss_scsi_adapter_data_t *) hba[ctlr]->scsi_ctlr; |
| 1392 | stk = &sa->cmd_stack; | 1507 | stk = &sa->cmd_stack; |
| 1393 | 1508 | ||
| 1394 | if (((struct cciss_scsi_adapter_data_t *) | 1509 | if (sa->registered) { |
| 1395 | hba[ctlr]->scsi_ctlr)->registered) { | ||
| 1396 | printk("cciss%d: SCSI subsystem already engaged.\n", ctlr); | 1510 | printk("cciss%d: SCSI subsystem already engaged.\n", ctlr); |
| 1397 | spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags); | 1511 | spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags); |
| 1398 | return ENXIO; | 1512 | return ENXIO; |
| 1399 | } | 1513 | } |
| 1514 | sa->registered = 1; | ||
| 1400 | spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags); | 1515 | spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags); |
| 1401 | cciss_update_non_disk_devices(ctlr, -1); | 1516 | cciss_update_non_disk_devices(ctlr, -1); |
| 1402 | cciss_register_scsi(ctlr); | 1517 | cciss_scsi_detect(ctlr); |
| 1403 | return 0; | 1518 | return 0; |
| 1404 | } | 1519 | } |
| 1405 | 1520 | ||
| @@ -1493,7 +1608,5 @@ static int cciss_eh_abort_handler(struct scsi_cmnd *scsicmd) | |||
| 1493 | /* If no tape support, then these become defined out of existence */ | 1608 | /* If no tape support, then these become defined out of existence */ |
| 1494 | 1609 | ||
| 1495 | #define cciss_scsi_setup(cntl_num) | 1610 | #define cciss_scsi_setup(cntl_num) |
| 1496 | #define cciss_unregister_scsi(ctlr) | ||
| 1497 | #define cciss_register_scsi(ctlr) | ||
| 1498 | 1611 | ||
| 1499 | #endif /* CONFIG_CISS_SCSI_TAPE */ | 1612 | #endif /* CONFIG_CISS_SCSI_TAPE */ |
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index 9ae05c584234..3ca643cafccd 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c | |||
| @@ -154,8 +154,8 @@ static int blkif_getgeo(struct block_device *bd, struct hd_geometry *hg) | |||
| 154 | return 0; | 154 | return 0; |
| 155 | } | 155 | } |
| 156 | 156 | ||
| 157 | int blkif_ioctl(struct inode *inode, struct file *filep, | 157 | static int blkif_ioctl(struct inode *inode, struct file *filep, |
| 158 | unsigned command, unsigned long argument) | 158 | unsigned command, unsigned long argument) |
| 159 | { | 159 | { |
| 160 | struct blkfront_info *info = | 160 | struct blkfront_info *info = |
| 161 | inode->i_bdev->bd_disk->private_data; | 161 | inode->i_bdev->bd_disk->private_data; |
diff --git a/drivers/bluetooth/bcm203x.c b/drivers/bluetooth/bcm203x.c index 8919ccf8274b..ee40201c7278 100644 --- a/drivers/bluetooth/bcm203x.c +++ b/drivers/bluetooth/bcm203x.c | |||
| @@ -42,9 +42,7 @@ | |||
| 42 | #define BT_DBG(D...) | 42 | #define BT_DBG(D...) |
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | #define VERSION "1.1" | 45 | #define VERSION "1.2" |
| 46 | |||
| 47 | static int ignore = 0; | ||
| 48 | 46 | ||
| 49 | static struct usb_device_id bcm203x_table[] = { | 47 | static struct usb_device_id bcm203x_table[] = { |
| 50 | /* Broadcom Blutonium (BCM2033) */ | 48 | /* Broadcom Blutonium (BCM2033) */ |
| @@ -175,7 +173,7 @@ static int bcm203x_probe(struct usb_interface *intf, const struct usb_device_id | |||
| 175 | 173 | ||
| 176 | BT_DBG("intf %p id %p", intf, id); | 174 | BT_DBG("intf %p id %p", intf, id); |
| 177 | 175 | ||
| 178 | if (ignore || (intf->cur_altsetting->desc.bInterfaceNumber != 0)) | 176 | if (intf->cur_altsetting->desc.bInterfaceNumber != 0) |
| 179 | return -ENODEV; | 177 | return -ENODEV; |
| 180 | 178 | ||
| 181 | data = kzalloc(sizeof(*data), GFP_KERNEL); | 179 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| @@ -300,9 +298,6 @@ static void __exit bcm203x_exit(void) | |||
| 300 | module_init(bcm203x_init); | 298 | module_init(bcm203x_init); |
| 301 | module_exit(bcm203x_exit); | 299 | module_exit(bcm203x_exit); |
| 302 | 300 | ||
| 303 | module_param(ignore, bool, 0644); | ||
| 304 | MODULE_PARM_DESC(ignore, "Ignore devices from the matching table"); | ||
| 305 | |||
| 306 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); | 301 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); |
| 307 | MODULE_DESCRIPTION("Broadcom Blutonium firmware driver ver " VERSION); | 302 | MODULE_DESCRIPTION("Broadcom Blutonium firmware driver ver " VERSION); |
| 308 | MODULE_VERSION(VERSION); | 303 | MODULE_VERSION(VERSION); |
diff --git a/drivers/bluetooth/bfusb.c b/drivers/bluetooth/bfusb.c index 0c211adbc063..90a094634630 100644 --- a/drivers/bluetooth/bfusb.c +++ b/drivers/bluetooth/bfusb.c | |||
| @@ -43,9 +43,7 @@ | |||
| 43 | #define BT_DBG(D...) | 43 | #define BT_DBG(D...) |
| 44 | #endif | 44 | #endif |
| 45 | 45 | ||
| 46 | #define VERSION "1.1" | 46 | #define VERSION "1.2" |
| 47 | |||
| 48 | static int ignore = 0; | ||
| 49 | 47 | ||
| 50 | static struct usb_driver bfusb_driver; | 48 | static struct usb_driver bfusb_driver; |
| 51 | 49 | ||
| @@ -656,9 +654,6 @@ static int bfusb_probe(struct usb_interface *intf, const struct usb_device_id *i | |||
| 656 | 654 | ||
| 657 | BT_DBG("intf %p id %p", intf, id); | 655 | BT_DBG("intf %p id %p", intf, id); |
| 658 | 656 | ||
| 659 | if (ignore) | ||
| 660 | return -ENODEV; | ||
| 661 | |||
| 662 | /* Check number of endpoints */ | 657 | /* Check number of endpoints */ |
| 663 | if (intf->cur_altsetting->desc.bNumEndpoints < 2) | 658 | if (intf->cur_altsetting->desc.bNumEndpoints < 2) |
| 664 | return -EIO; | 659 | return -EIO; |
| @@ -795,9 +790,6 @@ static void __exit bfusb_exit(void) | |||
| 795 | module_init(bfusb_init); | 790 | module_init(bfusb_init); |
| 796 | module_exit(bfusb_exit); | 791 | module_exit(bfusb_exit); |
| 797 | 792 | ||
| 798 | module_param(ignore, bool, 0644); | ||
| 799 | MODULE_PARM_DESC(ignore, "Ignore devices from the matching table"); | ||
| 800 | |||
| 801 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); | 793 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); |
| 802 | MODULE_DESCRIPTION("BlueFRITZ! USB driver ver " VERSION); | 794 | MODULE_DESCRIPTION("BlueFRITZ! USB driver ver " VERSION); |
| 803 | MODULE_VERSION(VERSION); | 795 | MODULE_VERSION(VERSION); |
diff --git a/drivers/bluetooth/bpa10x.c b/drivers/bluetooth/bpa10x.c index 3b28658f5a1f..1e55a658e6ce 100644 --- a/drivers/bluetooth/bpa10x.c +++ b/drivers/bluetooth/bpa10x.c | |||
| @@ -40,9 +40,7 @@ | |||
| 40 | #define BT_DBG(D...) | 40 | #define BT_DBG(D...) |
| 41 | #endif | 41 | #endif |
| 42 | 42 | ||
| 43 | #define VERSION "0.9" | 43 | #define VERSION "0.10" |
| 44 | |||
| 45 | static int ignore = 0; | ||
| 46 | 44 | ||
| 47 | static struct usb_device_id bpa10x_table[] = { | 45 | static struct usb_device_id bpa10x_table[] = { |
| 48 | /* Tektronix BPA 100/105 (Digianswer) */ | 46 | /* Tektronix BPA 100/105 (Digianswer) */ |
| @@ -460,9 +458,6 @@ static int bpa10x_probe(struct usb_interface *intf, const struct usb_device_id * | |||
| 460 | 458 | ||
| 461 | BT_DBG("intf %p id %p", intf, id); | 459 | BT_DBG("intf %p id %p", intf, id); |
| 462 | 460 | ||
| 463 | if (ignore) | ||
| 464 | return -ENODEV; | ||
| 465 | |||
| 466 | if (intf->cur_altsetting->desc.bInterfaceNumber != 0) | 461 | if (intf->cur_altsetting->desc.bInterfaceNumber != 0) |
| 467 | return -ENODEV; | 462 | return -ENODEV; |
| 468 | 463 | ||
| @@ -546,9 +541,6 @@ static void __exit bpa10x_exit(void) | |||
| 546 | module_init(bpa10x_init); | 541 | module_init(bpa10x_init); |
| 547 | module_exit(bpa10x_exit); | 542 | module_exit(bpa10x_exit); |
| 548 | 543 | ||
| 549 | module_param(ignore, bool, 0644); | ||
| 550 | MODULE_PARM_DESC(ignore, "Ignore devices from the matching table"); | ||
| 551 | |||
| 552 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); | 544 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); |
| 553 | MODULE_DESCRIPTION("Digianswer Bluetooth USB driver ver " VERSION); | 545 | MODULE_DESCRIPTION("Digianswer Bluetooth USB driver ver " VERSION); |
| 554 | MODULE_VERSION(VERSION); | 546 | MODULE_VERSION(VERSION); |
diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 12e108914f19..95ae9ba5661e 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c | |||
| @@ -41,18 +41,122 @@ | |||
| 41 | #define BT_DBG(D...) | 41 | #define BT_DBG(D...) |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | #define VERSION "0.1" | 44 | #define VERSION "0.2" |
| 45 | |||
| 46 | static int ignore_dga; | ||
| 47 | static int ignore_csr; | ||
| 48 | static int ignore_sniffer; | ||
| 49 | static int disable_scofix; | ||
| 50 | static int force_scofix; | ||
| 51 | static int reset; | ||
| 52 | |||
| 53 | static struct usb_driver btusb_driver; | ||
| 54 | |||
| 55 | #define BTUSB_IGNORE 0x01 | ||
| 56 | #define BTUSB_RESET 0x02 | ||
| 57 | #define BTUSB_DIGIANSWER 0x04 | ||
| 58 | #define BTUSB_CSR 0x08 | ||
| 59 | #define BTUSB_SNIFFER 0x10 | ||
| 60 | #define BTUSB_BCM92035 0x20 | ||
| 61 | #define BTUSB_BROKEN_ISOC 0x40 | ||
| 62 | #define BTUSB_WRONG_SCO_MTU 0x80 | ||
| 45 | 63 | ||
| 46 | static struct usb_device_id btusb_table[] = { | 64 | static struct usb_device_id btusb_table[] = { |
| 47 | /* Generic Bluetooth USB device */ | 65 | /* Generic Bluetooth USB device */ |
| 48 | { USB_DEVICE_INFO(0xe0, 0x01, 0x01) }, | 66 | { USB_DEVICE_INFO(0xe0, 0x01, 0x01) }, |
| 49 | 67 | ||
| 68 | /* AVM BlueFRITZ! USB v2.0 */ | ||
| 69 | { USB_DEVICE(0x057c, 0x3800) }, | ||
| 70 | |||
| 71 | /* Bluetooth Ultraport Module from IBM */ | ||
| 72 | { USB_DEVICE(0x04bf, 0x030a) }, | ||
| 73 | |||
| 74 | /* ALPS Modules with non-standard id */ | ||
| 75 | { USB_DEVICE(0x044e, 0x3001) }, | ||
| 76 | { USB_DEVICE(0x044e, 0x3002) }, | ||
| 77 | |||
| 78 | /* Ericsson with non-standard id */ | ||
| 79 | { USB_DEVICE(0x0bdb, 0x1002) }, | ||
| 80 | |||
| 81 | /* Canyon CN-BTU1 with HID interfaces */ | ||
| 82 | { USB_DEVICE(0x0c10, 0x0000), .driver_info = BTUSB_RESET }, | ||
| 83 | |||
| 50 | { } /* Terminating entry */ | 84 | { } /* Terminating entry */ |
| 51 | }; | 85 | }; |
| 52 | 86 | ||
| 53 | MODULE_DEVICE_TABLE(usb, btusb_table); | 87 | MODULE_DEVICE_TABLE(usb, btusb_table); |
| 54 | 88 | ||
| 55 | static struct usb_device_id blacklist_table[] = { | 89 | static struct usb_device_id blacklist_table[] = { |
| 90 | /* CSR BlueCore devices */ | ||
| 91 | { USB_DEVICE(0x0a12, 0x0001), .driver_info = BTUSB_CSR }, | ||
| 92 | |||
| 93 | /* Broadcom BCM2033 without firmware */ | ||
| 94 | { USB_DEVICE(0x0a5c, 0x2033), .driver_info = BTUSB_IGNORE }, | ||
| 95 | |||
| 96 | /* Broadcom BCM2035 */ | ||
| 97 | { USB_DEVICE(0x0a5c, 0x2035), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 98 | { USB_DEVICE(0x0a5c, 0x200a), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 99 | |||
| 100 | /* Broadcom BCM2045 */ | ||
| 101 | { USB_DEVICE(0x0a5c, 0x2039), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 102 | { USB_DEVICE(0x0a5c, 0x2101), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 103 | |||
| 104 | /* Broadcom BCM2046 */ | ||
| 105 | { USB_DEVICE(0x0a5c, 0x2151), .driver_info = BTUSB_RESET }, | ||
| 106 | |||
| 107 | /* IBM/Lenovo ThinkPad with Broadcom chip */ | ||
| 108 | { USB_DEVICE(0x0a5c, 0x201e), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 109 | { USB_DEVICE(0x0a5c, 0x2110), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 110 | |||
| 111 | /* Targus ACB10US */ | ||
| 112 | { USB_DEVICE(0x0a5c, 0x2100), .driver_info = BTUSB_RESET }, | ||
| 113 | |||
| 114 | /* ANYCOM Bluetooth USB-200 and USB-250 */ | ||
| 115 | { USB_DEVICE(0x0a5c, 0x2111), .driver_info = BTUSB_RESET }, | ||
| 116 | |||
| 117 | /* HP laptop with Broadcom chip */ | ||
| 118 | { USB_DEVICE(0x03f0, 0x171d), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 119 | |||
| 120 | /* Dell laptop with Broadcom chip */ | ||
| 121 | { USB_DEVICE(0x413c, 0x8126), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 122 | |||
| 123 | /* Dell Wireless 370 */ | ||
| 124 | { USB_DEVICE(0x413c, 0x8156), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 125 | |||
| 126 | /* Dell Wireless 410 */ | ||
| 127 | { USB_DEVICE(0x413c, 0x8152), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 128 | |||
| 129 | /* Microsoft Wireless Transceiver for Bluetooth 2.0 */ | ||
| 130 | { USB_DEVICE(0x045e, 0x009c), .driver_info = BTUSB_RESET }, | ||
| 131 | |||
| 132 | /* Kensington Bluetooth USB adapter */ | ||
| 133 | { USB_DEVICE(0x047d, 0x105d), .driver_info = BTUSB_RESET }, | ||
| 134 | { USB_DEVICE(0x047d, 0x105e), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 135 | |||
| 136 | /* ISSC Bluetooth Adapter v3.1 */ | ||
| 137 | { USB_DEVICE(0x1131, 0x1001), .driver_info = BTUSB_RESET }, | ||
| 138 | |||
| 139 | /* RTX Telecom based adapters with buggy SCO support */ | ||
| 140 | { USB_DEVICE(0x0400, 0x0807), .driver_info = BTUSB_BROKEN_ISOC }, | ||
| 141 | { USB_DEVICE(0x0400, 0x080a), .driver_info = BTUSB_BROKEN_ISOC }, | ||
| 142 | |||
| 143 | /* CONWISE Technology based adapters with buggy SCO support */ | ||
| 144 | { USB_DEVICE(0x0e5e, 0x6622), .driver_info = BTUSB_BROKEN_ISOC }, | ||
| 145 | |||
| 146 | /* Belkin F8T012 and F8T013 devices */ | ||
| 147 | { USB_DEVICE(0x050d, 0x0012), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 148 | { USB_DEVICE(0x050d, 0x0013), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU }, | ||
| 149 | |||
| 150 | /* Digianswer devices */ | ||
| 151 | { USB_DEVICE(0x08fd, 0x0001), .driver_info = BTUSB_DIGIANSWER }, | ||
| 152 | { USB_DEVICE(0x08fd, 0x0002), .driver_info = BTUSB_IGNORE }, | ||
| 153 | |||
| 154 | /* CSR BlueCore Bluetooth Sniffer */ | ||
| 155 | { USB_DEVICE(0x0a12, 0x0002), .driver_info = BTUSB_SNIFFER }, | ||
| 156 | |||
| 157 | /* Frontline ComProbe Bluetooth Sniffer */ | ||
| 158 | { USB_DEVICE(0x16d3, 0x0002), .driver_info = BTUSB_SNIFFER }, | ||
| 159 | |||
| 56 | { } /* Terminating entry */ | 160 | { } /* Terminating entry */ |
| 57 | }; | 161 | }; |
| 58 | 162 | ||
| @@ -433,6 +537,7 @@ static int btusb_probe(struct usb_interface *intf, | |||
| 433 | 537 | ||
| 434 | BT_DBG("intf %p id %p", intf, id); | 538 | BT_DBG("intf %p id %p", intf, id); |
| 435 | 539 | ||
| 540 | /* interface numbers are hardcoded in the spec */ | ||
| 436 | if (intf->cur_altsetting->desc.bInterfaceNumber != 0) | 541 | if (intf->cur_altsetting->desc.bInterfaceNumber != 0) |
| 437 | return -ENODEV; | 542 | return -ENODEV; |
| 438 | 543 | ||
| @@ -443,6 +548,18 @@ static int btusb_probe(struct usb_interface *intf, | |||
| 443 | id = match; | 548 | id = match; |
| 444 | } | 549 | } |
| 445 | 550 | ||
| 551 | if (id->driver_info == BTUSB_IGNORE) | ||
| 552 | return -ENODEV; | ||
| 553 | |||
| 554 | if (ignore_dga && id->driver_info & BTUSB_DIGIANSWER) | ||
| 555 | return -ENODEV; | ||
| 556 | |||
| 557 | if (ignore_csr && id->driver_info & BTUSB_CSR) | ||
| 558 | return -ENODEV; | ||
| 559 | |||
| 560 | if (ignore_sniffer && id->driver_info & BTUSB_SNIFFER) | ||
| 561 | return -ENODEV; | ||
| 562 | |||
| 446 | data = kzalloc(sizeof(*data), GFP_KERNEL); | 563 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 447 | if (!data) | 564 | if (!data) |
| 448 | return -ENOMEM; | 565 | return -ENOMEM; |
| @@ -503,7 +620,31 @@ static int btusb_probe(struct usb_interface *intf, | |||
| 503 | 620 | ||
| 504 | hdev->owner = THIS_MODULE; | 621 | hdev->owner = THIS_MODULE; |
| 505 | 622 | ||
| 506 | set_bit(HCI_QUIRK_RESET_ON_INIT, &hdev->quirks); | 623 | if (reset || id->driver_info & BTUSB_RESET) |
| 624 | set_bit(HCI_QUIRK_RESET_ON_INIT, &hdev->quirks); | ||
| 625 | |||
| 626 | if (force_scofix || id->driver_info & BTUSB_WRONG_SCO_MTU) { | ||
| 627 | if (!disable_scofix) | ||
| 628 | set_bit(HCI_QUIRK_FIXUP_BUFFER_SIZE, &hdev->quirks); | ||
| 629 | } | ||
| 630 | |||
| 631 | if (id->driver_info & BTUSB_SNIFFER) { | ||
| 632 | struct usb_device *udev = interface_to_usbdev(intf); | ||
| 633 | |||
| 634 | if (le16_to_cpu(udev->descriptor.bcdDevice) > 0x997) | ||
| 635 | set_bit(HCI_QUIRK_RAW_DEVICE, &hdev->quirks); | ||
| 636 | } | ||
| 637 | |||
| 638 | if (id->driver_info & BTUSB_BCM92035) { | ||
| 639 | unsigned char cmd[] = { 0x3b, 0xfc, 0x01, 0x00 }; | ||
| 640 | struct sk_buff *skb; | ||
| 641 | |||
| 642 | skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL); | ||
| 643 | if (skb) { | ||
| 644 | memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd)); | ||
| 645 | skb_queue_tail(&hdev->driver_init, skb); | ||
| 646 | } | ||
| 647 | } | ||
| 507 | 648 | ||
| 508 | err = hci_register_dev(hdev); | 649 | err = hci_register_dev(hdev); |
| 509 | if (err < 0) { | 650 | if (err < 0) { |
| @@ -558,6 +699,24 @@ static void __exit btusb_exit(void) | |||
| 558 | module_init(btusb_init); | 699 | module_init(btusb_init); |
| 559 | module_exit(btusb_exit); | 700 | module_exit(btusb_exit); |
| 560 | 701 | ||
| 702 | module_param(ignore_dga, bool, 0644); | ||
| 703 | MODULE_PARM_DESC(ignore_dga, "Ignore devices with id 08fd:0001"); | ||
| 704 | |||
| 705 | module_param(ignore_csr, bool, 0644); | ||
| 706 | MODULE_PARM_DESC(ignore_csr, "Ignore devices with id 0a12:0001"); | ||
| 707 | |||
| 708 | module_param(ignore_sniffer, bool, 0644); | ||
| 709 | MODULE_PARM_DESC(ignore_sniffer, "Ignore devices with id 0a12:0002"); | ||
| 710 | |||
| 711 | module_param(disable_scofix, bool, 0644); | ||
| 712 | MODULE_PARM_DESC(disable_scofix, "Disable fixup of wrong SCO buffer size"); | ||
| 713 | |||
| 714 | module_param(force_scofix, bool, 0644); | ||
| 715 | MODULE_PARM_DESC(force_scofix, "Force fixup of wrong SCO buffers size"); | ||
| 716 | |||
| 717 | module_param(reset, bool, 0644); | ||
| 718 | MODULE_PARM_DESC(reset, "Send HCI reset command on initialization"); | ||
| 719 | |||
| 561 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); | 720 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); |
| 562 | MODULE_DESCRIPTION("Generic Bluetooth USB driver ver " VERSION); | 721 | MODULE_DESCRIPTION("Generic Bluetooth USB driver ver " VERSION); |
| 563 | MODULE_VERSION(VERSION); | 722 | MODULE_VERSION(VERSION); |
diff --git a/drivers/bluetooth/hci_usb.c b/drivers/bluetooth/hci_usb.c index c33bb59ed1fa..e397572bf574 100644 --- a/drivers/bluetooth/hci_usb.c +++ b/drivers/bluetooth/hci_usb.c | |||
| @@ -62,7 +62,6 @@ | |||
| 62 | #define URB_ZERO_PACKET 0 | 62 | #define URB_ZERO_PACKET 0 |
| 63 | #endif | 63 | #endif |
| 64 | 64 | ||
| 65 | static int ignore; | ||
| 66 | static int ignore_dga; | 65 | static int ignore_dga; |
| 67 | static int ignore_csr; | 66 | static int ignore_csr; |
| 68 | static int ignore_sniffer; | 67 | static int ignore_sniffer; |
| @@ -74,7 +73,7 @@ static int reset; | |||
| 74 | static int isoc = 2; | 73 | static int isoc = 2; |
| 75 | #endif | 74 | #endif |
| 76 | 75 | ||
| 77 | #define VERSION "2.9" | 76 | #define VERSION "2.10" |
| 78 | 77 | ||
| 79 | static struct usb_driver hci_usb_driver; | 78 | static struct usb_driver hci_usb_driver; |
| 80 | 79 | ||
| @@ -801,7 +800,7 @@ static int hci_usb_probe(struct usb_interface *intf, const struct usb_device_id | |||
| 801 | id = match; | 800 | id = match; |
| 802 | } | 801 | } |
| 803 | 802 | ||
| 804 | if (ignore || id->driver_info & HCI_IGNORE) | 803 | if (id->driver_info & HCI_IGNORE) |
| 805 | return -ENODEV; | 804 | return -ENODEV; |
| 806 | 805 | ||
| 807 | if (ignore_dga && id->driver_info & HCI_DIGIANSWER) | 806 | if (ignore_dga && id->driver_info & HCI_DIGIANSWER) |
| @@ -1108,9 +1107,6 @@ static void __exit hci_usb_exit(void) | |||
| 1108 | module_init(hci_usb_init); | 1107 | module_init(hci_usb_init); |
| 1109 | module_exit(hci_usb_exit); | 1108 | module_exit(hci_usb_exit); |
| 1110 | 1109 | ||
| 1111 | module_param(ignore, bool, 0644); | ||
| 1112 | MODULE_PARM_DESC(ignore, "Ignore devices from the matching table"); | ||
| 1113 | |||
| 1114 | module_param(ignore_dga, bool, 0644); | 1110 | module_param(ignore_dga, bool, 0644); |
| 1115 | MODULE_PARM_DESC(ignore_dga, "Ignore devices with id 08fd:0001"); | 1111 | MODULE_PARM_DESC(ignore_dga, "Ignore devices with id 08fd:0001"); |
| 1116 | 1112 | ||
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index d0ac944e1696..caff85149b9d 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig | |||
| @@ -8,7 +8,7 @@ config VT | |||
| 8 | bool "Virtual terminal" if EMBEDDED | 8 | bool "Virtual terminal" if EMBEDDED |
| 9 | depends on !S390 | 9 | depends on !S390 |
| 10 | select INPUT | 10 | select INPUT |
| 11 | default y if !VIOCONS | 11 | default y |
| 12 | ---help--- | 12 | ---help--- |
| 13 | If you say Y here, you will get support for terminal devices with | 13 | If you say Y here, you will get support for terminal devices with |
| 14 | display and keyboard devices. These are called "virtual" because you | 14 | display and keyboard devices. These are called "virtual" because you |
diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 8a161c30e1dc..6850f6da7576 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile | |||
| @@ -55,7 +55,6 @@ obj-$(CONFIG_RAW_DRIVER) += raw.o | |||
| 55 | obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o | 55 | obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o |
| 56 | obj-$(CONFIG_MSPEC) += mspec.o | 56 | obj-$(CONFIG_MSPEC) += mspec.o |
| 57 | obj-$(CONFIG_MMTIMER) += mmtimer.o | 57 | obj-$(CONFIG_MMTIMER) += mmtimer.o |
| 58 | obj-$(CONFIG_VIOCONS) += viocons.o | ||
| 59 | obj-$(CONFIG_VIOTAPE) += viotape.o | 58 | obj-$(CONFIG_VIOTAPE) += viotape.o |
| 60 | obj-$(CONFIG_HVCS) += hvcs.o | 59 | obj-$(CONFIG_HVCS) += hvcs.o |
| 61 | obj-$(CONFIG_IBM_BSR) += bsr.o | 60 | obj-$(CONFIG_IBM_BSR) += bsr.o |
diff --git a/drivers/char/amiserial.c b/drivers/char/amiserial.c index 3530ff417a51..6e763e3f5a81 100644 --- a/drivers/char/amiserial.c +++ b/drivers/char/amiserial.c | |||
| @@ -1254,7 +1254,7 @@ static int rs_break(struct tty_struct *tty, int break_state) | |||
| 1254 | unsigned long flags; | 1254 | unsigned long flags; |
| 1255 | 1255 | ||
| 1256 | if (serial_paranoia_check(info, tty->name, "rs_break")) | 1256 | if (serial_paranoia_check(info, tty->name, "rs_break")) |
| 1257 | return; | 1257 | return -EINVAL; |
| 1258 | 1258 | ||
| 1259 | local_irq_save(flags); | 1259 | local_irq_save(flags); |
| 1260 | if (break_state == -1) | 1260 | if (break_state == -1) |
diff --git a/drivers/char/pcmcia/synclink_cs.c b/drivers/char/pcmcia/synclink_cs.c index d1fceabe3aef..c240562c218b 100644 --- a/drivers/char/pcmcia/synclink_cs.c +++ b/drivers/char/pcmcia/synclink_cs.c | |||
| @@ -232,7 +232,6 @@ typedef struct _mgslpc_info { | |||
| 232 | 232 | ||
| 233 | /* SPPP/Cisco HDLC device parts */ | 233 | /* SPPP/Cisco HDLC device parts */ |
| 234 | int netcount; | 234 | int netcount; |
| 235 | int dosyncppp; | ||
| 236 | spinlock_t netlock; | 235 | spinlock_t netlock; |
| 237 | 236 | ||
| 238 | #if SYNCLINK_GENERIC_HDLC | 237 | #if SYNCLINK_GENERIC_HDLC |
| @@ -459,13 +458,11 @@ static int ttymajor=0; | |||
| 459 | 458 | ||
| 460 | static int debug_level = 0; | 459 | static int debug_level = 0; |
| 461 | static int maxframe[MAX_DEVICE_COUNT] = {0,}; | 460 | static int maxframe[MAX_DEVICE_COUNT] = {0,}; |
| 462 | static int dosyncppp[MAX_DEVICE_COUNT] = {1,1,1,1}; | ||
| 463 | 461 | ||
| 464 | module_param(break_on_load, bool, 0); | 462 | module_param(break_on_load, bool, 0); |
| 465 | module_param(ttymajor, int, 0); | 463 | module_param(ttymajor, int, 0); |
| 466 | module_param(debug_level, int, 0); | 464 | module_param(debug_level, int, 0); |
| 467 | module_param_array(maxframe, int, NULL, 0); | 465 | module_param_array(maxframe, int, NULL, 0); |
| 468 | module_param_array(dosyncppp, int, NULL, 0); | ||
| 469 | 466 | ||
| 470 | MODULE_LICENSE("GPL"); | 467 | MODULE_LICENSE("GPL"); |
| 471 | 468 | ||
| @@ -2915,7 +2912,6 @@ static void mgslpc_add_device(MGSLPC_INFO *info) | |||
| 2915 | if (info->line < MAX_DEVICE_COUNT) { | 2912 | if (info->line < MAX_DEVICE_COUNT) { |
| 2916 | if (maxframe[info->line]) | 2913 | if (maxframe[info->line]) |
| 2917 | info->max_frame_size = maxframe[info->line]; | 2914 | info->max_frame_size = maxframe[info->line]; |
| 2918 | info->dosyncppp = dosyncppp[info->line]; | ||
| 2919 | } | 2915 | } |
| 2920 | 2916 | ||
| 2921 | mgslpc_device_count++; | 2917 | mgslpc_device_count++; |
diff --git a/drivers/char/synclink.c b/drivers/char/synclink.c index ef6706f09061..500f5176b6ba 100644 --- a/drivers/char/synclink.c +++ b/drivers/char/synclink.c | |||
| @@ -304,7 +304,6 @@ struct mgsl_struct { | |||
| 304 | 304 | ||
| 305 | /* generic HDLC device parts */ | 305 | /* generic HDLC device parts */ |
| 306 | int netcount; | 306 | int netcount; |
| 307 | int dosyncppp; | ||
| 308 | spinlock_t netlock; | 307 | spinlock_t netlock; |
| 309 | 308 | ||
| 310 | #if SYNCLINK_GENERIC_HDLC | 309 | #if SYNCLINK_GENERIC_HDLC |
| @@ -868,7 +867,6 @@ static int irq[MAX_ISA_DEVICES]; | |||
| 868 | static int dma[MAX_ISA_DEVICES]; | 867 | static int dma[MAX_ISA_DEVICES]; |
| 869 | static int debug_level; | 868 | static int debug_level; |
| 870 | static int maxframe[MAX_TOTAL_DEVICES]; | 869 | static int maxframe[MAX_TOTAL_DEVICES]; |
| 871 | static int dosyncppp[MAX_TOTAL_DEVICES]; | ||
| 872 | static int txdmabufs[MAX_TOTAL_DEVICES]; | 870 | static int txdmabufs[MAX_TOTAL_DEVICES]; |
| 873 | static int txholdbufs[MAX_TOTAL_DEVICES]; | 871 | static int txholdbufs[MAX_TOTAL_DEVICES]; |
| 874 | 872 | ||
| @@ -879,7 +877,6 @@ module_param_array(irq, int, NULL, 0); | |||
| 879 | module_param_array(dma, int, NULL, 0); | 877 | module_param_array(dma, int, NULL, 0); |
| 880 | module_param(debug_level, int, 0); | 878 | module_param(debug_level, int, 0); |
| 881 | module_param_array(maxframe, int, NULL, 0); | 879 | module_param_array(maxframe, int, NULL, 0); |
| 882 | module_param_array(dosyncppp, int, NULL, 0); | ||
| 883 | module_param_array(txdmabufs, int, NULL, 0); | 880 | module_param_array(txdmabufs, int, NULL, 0); |
| 884 | module_param_array(txholdbufs, int, NULL, 0); | 881 | module_param_array(txholdbufs, int, NULL, 0); |
| 885 | 882 | ||
| @@ -4258,7 +4255,6 @@ static void mgsl_add_device( struct mgsl_struct *info ) | |||
| 4258 | if (info->line < MAX_TOTAL_DEVICES) { | 4255 | if (info->line < MAX_TOTAL_DEVICES) { |
| 4259 | if (maxframe[info->line]) | 4256 | if (maxframe[info->line]) |
| 4260 | info->max_frame_size = maxframe[info->line]; | 4257 | info->max_frame_size = maxframe[info->line]; |
| 4261 | info->dosyncppp = dosyncppp[info->line]; | ||
| 4262 | 4258 | ||
| 4263 | if (txdmabufs[info->line]) { | 4259 | if (txdmabufs[info->line]) { |
| 4264 | info->num_tx_dma_buffers = txdmabufs[info->line]; | 4260 | info->num_tx_dma_buffers = txdmabufs[info->line]; |
diff --git a/drivers/char/synclink_gt.c b/drivers/char/synclink_gt.c index 3e9058993e41..509c89ac5bd3 100644 --- a/drivers/char/synclink_gt.c +++ b/drivers/char/synclink_gt.c | |||
| @@ -128,17 +128,14 @@ static int slgt_device_count; | |||
| 128 | static int ttymajor; | 128 | static int ttymajor; |
| 129 | static int debug_level; | 129 | static int debug_level; |
| 130 | static int maxframe[MAX_DEVICES]; | 130 | static int maxframe[MAX_DEVICES]; |
| 131 | static int dosyncppp[MAX_DEVICES]; | ||
| 132 | 131 | ||
| 133 | module_param(ttymajor, int, 0); | 132 | module_param(ttymajor, int, 0); |
| 134 | module_param(debug_level, int, 0); | 133 | module_param(debug_level, int, 0); |
| 135 | module_param_array(maxframe, int, NULL, 0); | 134 | module_param_array(maxframe, int, NULL, 0); |
| 136 | module_param_array(dosyncppp, int, NULL, 0); | ||
| 137 | 135 | ||
| 138 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); | 136 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); |
| 139 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); | 137 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); |
| 140 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); | 138 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); |
| 141 | MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable"); | ||
| 142 | 139 | ||
| 143 | /* | 140 | /* |
| 144 | * tty support and callbacks | 141 | * tty support and callbacks |
| @@ -349,7 +346,6 @@ struct slgt_info { | |||
| 349 | /* SPPP/Cisco HDLC device parts */ | 346 | /* SPPP/Cisco HDLC device parts */ |
| 350 | 347 | ||
| 351 | int netcount; | 348 | int netcount; |
| 352 | int dosyncppp; | ||
| 353 | spinlock_t netlock; | 349 | spinlock_t netlock; |
| 354 | #if SYNCLINK_GENERIC_HDLC | 350 | #if SYNCLINK_GENERIC_HDLC |
| 355 | struct net_device *netdev; | 351 | struct net_device *netdev; |
| @@ -3405,7 +3401,6 @@ static void add_device(struct slgt_info *info) | |||
| 3405 | if (info->line < MAX_DEVICES) { | 3401 | if (info->line < MAX_DEVICES) { |
| 3406 | if (maxframe[info->line]) | 3402 | if (maxframe[info->line]) |
| 3407 | info->max_frame_size = maxframe[info->line]; | 3403 | info->max_frame_size = maxframe[info->line]; |
| 3408 | info->dosyncppp = dosyncppp[info->line]; | ||
| 3409 | } | 3404 | } |
| 3410 | 3405 | ||
| 3411 | slgt_device_count++; | 3406 | slgt_device_count++; |
diff --git a/drivers/char/synclinkmp.c b/drivers/char/synclinkmp.c index c0490cbd0db2..6bdb44f7bec2 100644 --- a/drivers/char/synclinkmp.c +++ b/drivers/char/synclinkmp.c | |||
| @@ -270,7 +270,6 @@ typedef struct _synclinkmp_info { | |||
| 270 | 270 | ||
| 271 | /* SPPP/Cisco HDLC device parts */ | 271 | /* SPPP/Cisco HDLC device parts */ |
| 272 | int netcount; | 272 | int netcount; |
| 273 | int dosyncppp; | ||
| 274 | spinlock_t netlock; | 273 | spinlock_t netlock; |
| 275 | 274 | ||
| 276 | #if SYNCLINK_GENERIC_HDLC | 275 | #if SYNCLINK_GENERIC_HDLC |
| @@ -469,13 +468,11 @@ static int ttymajor = 0; | |||
| 469 | */ | 468 | */ |
| 470 | static int debug_level = 0; | 469 | static int debug_level = 0; |
| 471 | static int maxframe[MAX_DEVICES] = {0,}; | 470 | static int maxframe[MAX_DEVICES] = {0,}; |
| 472 | static int dosyncppp[MAX_DEVICES] = {0,}; | ||
| 473 | 471 | ||
| 474 | module_param(break_on_load, bool, 0); | 472 | module_param(break_on_load, bool, 0); |
| 475 | module_param(ttymajor, int, 0); | 473 | module_param(ttymajor, int, 0); |
| 476 | module_param(debug_level, int, 0); | 474 | module_param(debug_level, int, 0); |
| 477 | module_param_array(maxframe, int, NULL, 0); | 475 | module_param_array(maxframe, int, NULL, 0); |
| 478 | module_param_array(dosyncppp, int, NULL, 0); | ||
| 479 | 476 | ||
| 480 | static char *driver_name = "SyncLink MultiPort driver"; | 477 | static char *driver_name = "SyncLink MultiPort driver"; |
| 481 | static char *driver_version = "$Revision: 4.38 $"; | 478 | static char *driver_version = "$Revision: 4.38 $"; |
| @@ -3752,7 +3749,6 @@ static void add_device(SLMP_INFO *info) | |||
| 3752 | if (info->line < MAX_DEVICES) { | 3749 | if (info->line < MAX_DEVICES) { |
| 3753 | if (maxframe[info->line]) | 3750 | if (maxframe[info->line]) |
| 3754 | info->max_frame_size = maxframe[info->line]; | 3751 | info->max_frame_size = maxframe[info->line]; |
| 3755 | info->dosyncppp = dosyncppp[info->line]; | ||
| 3756 | } | 3752 | } |
| 3757 | 3753 | ||
| 3758 | synclinkmp_device_count++; | 3754 | synclinkmp_device_count++; |
diff --git a/drivers/char/viocons.c b/drivers/char/viocons.c deleted file mode 100644 index 65fb848e1cce..000000000000 --- a/drivers/char/viocons.c +++ /dev/null | |||
| @@ -1,1171 +0,0 @@ | |||
| 1 | /* -*- linux-c -*- | ||
| 2 | * | ||
| 3 | * drivers/char/viocons.c | ||
| 4 | * | ||
| 5 | * iSeries Virtual Terminal | ||
| 6 | * | ||
| 7 | * Authors: Dave Boutcher <boutcher@us.ibm.com> | ||
| 8 | * Ryan Arnold <ryanarn@us.ibm.com> | ||
| 9 | * Colin Devilbiss <devilbis@us.ibm.com> | ||
| 10 | * Stephen Rothwell | ||
| 11 | * | ||
| 12 | * (C) Copyright 2000, 2001, 2002, 2003, 2004 IBM Corporation | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License as | ||
| 16 | * published by the Free Software Foundation; either version 2 of the | ||
| 17 | * License, or (at your option) anyu later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, but | ||
| 20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 22 | * General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, write to the Free Software Foundation, | ||
| 26 | * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 27 | */ | ||
| 28 | #include <linux/kernel.h> | ||
| 29 | #include <linux/proc_fs.h> | ||
| 30 | #include <linux/errno.h> | ||
| 31 | #include <linux/vmalloc.h> | ||
| 32 | #include <linux/mm.h> | ||
| 33 | #include <linux/console.h> | ||
| 34 | #include <linux/module.h> | ||
| 35 | #include <asm/uaccess.h> | ||
| 36 | #include <linux/init.h> | ||
| 37 | #include <linux/wait.h> | ||
| 38 | #include <linux/spinlock.h> | ||
| 39 | #include <asm/ioctls.h> | ||
| 40 | #include <linux/kd.h> | ||
| 41 | #include <linux/tty.h> | ||
| 42 | #include <linux/tty_flip.h> | ||
| 43 | #include <linux/sysrq.h> | ||
| 44 | |||
| 45 | #include <asm/firmware.h> | ||
| 46 | #include <asm/iseries/vio.h> | ||
| 47 | #include <asm/iseries/hv_lp_event.h> | ||
| 48 | #include <asm/iseries/hv_call_event.h> | ||
| 49 | #include <asm/iseries/hv_lp_config.h> | ||
| 50 | #include <asm/iseries/hv_call.h> | ||
| 51 | |||
| 52 | #ifdef CONFIG_VT | ||
| 53 | #error You must turn off CONFIG_VT to use CONFIG_VIOCONS | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #define VIOTTY_MAGIC (0x0DCB) | ||
| 57 | #define VTTY_PORTS 10 | ||
| 58 | |||
| 59 | #define VIOCONS_KERN_WARN KERN_WARNING "viocons: " | ||
| 60 | #define VIOCONS_KERN_INFO KERN_INFO "viocons: " | ||
| 61 | |||
| 62 | static DEFINE_SPINLOCK(consolelock); | ||
| 63 | static DEFINE_SPINLOCK(consoleloglock); | ||
| 64 | |||
| 65 | static int vio_sysrq_pressed; | ||
| 66 | |||
| 67 | #define VIOCHAR_NUM_BUF 16 | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Our port information. We store a pointer to one entry in the | ||
| 71 | * tty_driver_data | ||
| 72 | */ | ||
| 73 | static struct port_info { | ||
| 74 | int magic; | ||
| 75 | struct tty_struct *tty; | ||
| 76 | HvLpIndex lp; | ||
| 77 | u8 vcons; | ||
| 78 | u64 seq; /* sequence number of last HV send */ | ||
| 79 | u64 ack; /* last ack from HV */ | ||
| 80 | /* | ||
| 81 | * When we get writes faster than we can send it to the partition, | ||
| 82 | * buffer the data here. Note that used is a bit map of used buffers. | ||
| 83 | * It had better have enough bits to hold VIOCHAR_NUM_BUF the bitops assume | ||
| 84 | * it is a multiple of unsigned long | ||
| 85 | */ | ||
| 86 | unsigned long used; | ||
| 87 | u8 *buffer[VIOCHAR_NUM_BUF]; | ||
| 88 | int bufferBytes[VIOCHAR_NUM_BUF]; | ||
| 89 | int curbuf; | ||
| 90 | int bufferOverflow; | ||
| 91 | int overflowMessage; | ||
| 92 | } port_info[VTTY_PORTS]; | ||
| 93 | |||
| 94 | #define viochar_is_console(pi) ((pi) == &port_info[0]) | ||
| 95 | #define viochar_port(pi) ((pi) - &port_info[0]) | ||
| 96 | |||
| 97 | static void initDataEvent(struct viocharlpevent *viochar, HvLpIndex lp); | ||
| 98 | |||
| 99 | static struct tty_driver *viotty_driver; | ||
| 100 | |||
| 101 | static void hvlog(char *fmt, ...) | ||
| 102 | { | ||
| 103 | int i; | ||
| 104 | unsigned long flags; | ||
| 105 | va_list args; | ||
| 106 | static char buf[256]; | ||
| 107 | |||
| 108 | spin_lock_irqsave(&consoleloglock, flags); | ||
| 109 | va_start(args, fmt); | ||
| 110 | i = vscnprintf(buf, sizeof(buf) - 1, fmt, args); | ||
| 111 | va_end(args); | ||
| 112 | buf[i++] = '\r'; | ||
| 113 | HvCall_writeLogBuffer(buf, i); | ||
| 114 | spin_unlock_irqrestore(&consoleloglock, flags); | ||
| 115 | } | ||
| 116 | |||
| 117 | static void hvlogOutput(const char *buf, int count) | ||
| 118 | { | ||
| 119 | unsigned long flags; | ||
| 120 | int begin; | ||
| 121 | int index; | ||
| 122 | static const char cr = '\r'; | ||
| 123 | |||
| 124 | begin = 0; | ||
| 125 | spin_lock_irqsave(&consoleloglock, flags); | ||
| 126 | for (index = 0; index < count; index++) { | ||
| 127 | if (buf[index] == '\n') { | ||
| 128 | /* | ||
| 129 | * Start right after the last '\n' or at the zeroth | ||
| 130 | * array position and output the number of characters | ||
| 131 | * including the newline. | ||
| 132 | */ | ||
| 133 | HvCall_writeLogBuffer(&buf[begin], index - begin + 1); | ||
| 134 | begin = index + 1; | ||
| 135 | HvCall_writeLogBuffer(&cr, 1); | ||
| 136 | } | ||
| 137 | } | ||
| 138 | if ((index - begin) > 0) | ||
| 139 | HvCall_writeLogBuffer(&buf[begin], index - begin); | ||
| 140 | spin_unlock_irqrestore(&consoleloglock, flags); | ||
| 141 | } | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Make sure we're pointing to a valid port_info structure. Shamelessly | ||
| 145 | * plagerized from serial.c | ||
| 146 | */ | ||
| 147 | static inline int viotty_paranoia_check(struct port_info *pi, | ||
| 148 | char *name, const char *routine) | ||
| 149 | { | ||
| 150 | static const char *bad_pi_addr = VIOCONS_KERN_WARN | ||
| 151 | "warning: bad address for port_info struct (%s) in %s\n"; | ||
| 152 | static const char *badmagic = VIOCONS_KERN_WARN | ||
| 153 | "warning: bad magic number for port_info struct (%s) in %s\n"; | ||
| 154 | |||
| 155 | if ((pi < &port_info[0]) || (viochar_port(pi) > VTTY_PORTS)) { | ||
| 156 | printk(bad_pi_addr, name, routine); | ||
| 157 | return 1; | ||
| 158 | } | ||
| 159 | if (pi->magic != VIOTTY_MAGIC) { | ||
| 160 | printk(badmagic, name, routine); | ||
| 161 | return 1; | ||
| 162 | } | ||
| 163 | return 0; | ||
| 164 | } | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Add data to our pending-send buffers. | ||
| 168 | * | ||
| 169 | * NOTE: Don't use printk in here because it gets nastily recursive. | ||
| 170 | * hvlog can be used to log to the hypervisor buffer | ||
| 171 | */ | ||
| 172 | static int buffer_add(struct port_info *pi, const char *buf, size_t len) | ||
| 173 | { | ||
| 174 | size_t bleft; | ||
| 175 | size_t curlen; | ||
| 176 | const char *curbuf; | ||
| 177 | int nextbuf; | ||
| 178 | |||
| 179 | curbuf = buf; | ||
| 180 | bleft = len; | ||
| 181 | while (bleft > 0) { | ||
| 182 | /* | ||
| 183 | * If there is no space left in the current buffer, we have | ||
| 184 | * filled everything up, so return. If we filled the previous | ||
| 185 | * buffer we would already have moved to the next one. | ||
| 186 | */ | ||
| 187 | if (pi->bufferBytes[pi->curbuf] == VIOCHAR_MAX_DATA) { | ||
| 188 | hvlog ("\n\rviocons: No overflow buffer available for memcpy().\n"); | ||
| 189 | pi->bufferOverflow++; | ||
| 190 | pi->overflowMessage = 1; | ||
| 191 | break; | ||
| 192 | } | ||
| 193 | |||
| 194 | /* | ||
| 195 | * Turn on the "used" bit for this buffer. If it's already on, | ||
| 196 | * that's fine. | ||
| 197 | */ | ||
| 198 | set_bit(pi->curbuf, &pi->used); | ||
| 199 | |||
| 200 | /* | ||
| 201 | * See if this buffer has been allocated. If not, allocate it. | ||
| 202 | */ | ||
| 203 | if (pi->buffer[pi->curbuf] == NULL) { | ||
| 204 | pi->buffer[pi->curbuf] = | ||
| 205 | kmalloc(VIOCHAR_MAX_DATA, GFP_ATOMIC); | ||
| 206 | if (pi->buffer[pi->curbuf] == NULL) { | ||
| 207 | hvlog("\n\rviocons: kmalloc failed allocating spaces for buffer %d.", | ||
| 208 | pi->curbuf); | ||
| 209 | break; | ||
| 210 | } | ||
| 211 | } | ||
| 212 | |||
| 213 | /* Figure out how much we can copy into this buffer. */ | ||
| 214 | if (bleft < (VIOCHAR_MAX_DATA - pi->bufferBytes[pi->curbuf])) | ||
| 215 | curlen = bleft; | ||
| 216 | else | ||
| 217 | curlen = VIOCHAR_MAX_DATA - pi->bufferBytes[pi->curbuf]; | ||
| 218 | |||
| 219 | /* Copy the data into the buffer. */ | ||
| 220 | memcpy(pi->buffer[pi->curbuf] + pi->bufferBytes[pi->curbuf], | ||
| 221 | curbuf, curlen); | ||
| 222 | |||
| 223 | pi->bufferBytes[pi->curbuf] += curlen; | ||
| 224 | curbuf += curlen; | ||
| 225 | bleft -= curlen; | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Now see if we've filled this buffer. If not then | ||
| 229 | * we'll try to use it again later. If we've filled it | ||
| 230 | * up then we'll advance the curbuf to the next in the | ||
| 231 | * circular queue. | ||
| 232 | */ | ||
| 233 | if (pi->bufferBytes[pi->curbuf] == VIOCHAR_MAX_DATA) { | ||
| 234 | nextbuf = (pi->curbuf + 1) % VIOCHAR_NUM_BUF; | ||
| 235 | /* | ||
| 236 | * Move to the next buffer if it hasn't been used yet | ||
| 237 | */ | ||
| 238 | if (test_bit(nextbuf, &pi->used) == 0) | ||
| 239 | pi->curbuf = nextbuf; | ||
| 240 | } | ||
| 241 | } | ||
| 242 | return len - bleft; | ||
| 243 | } | ||
| 244 | |||
| 245 | /* | ||
| 246 | * Send pending data | ||
| 247 | * | ||
| 248 | * NOTE: Don't use printk in here because it gets nastily recursive. | ||
| 249 | * hvlog can be used to log to the hypervisor buffer | ||
| 250 | */ | ||
| 251 | static void send_buffers(struct port_info *pi) | ||
| 252 | { | ||
| 253 | HvLpEvent_Rc hvrc; | ||
| 254 | int nextbuf; | ||
| 255 | struct viocharlpevent *viochar; | ||
| 256 | unsigned long flags; | ||
| 257 | |||
| 258 | spin_lock_irqsave(&consolelock, flags); | ||
| 259 | |||
| 260 | viochar = (struct viocharlpevent *) | ||
| 261 | vio_get_event_buffer(viomajorsubtype_chario); | ||
| 262 | |||
| 263 | /* Make sure we got a buffer */ | ||
| 264 | if (viochar == NULL) { | ||
| 265 | hvlog("\n\rviocons: Can't get viochar buffer in sendBuffers()."); | ||
| 266 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 267 | return; | ||
| 268 | } | ||
| 269 | |||
| 270 | if (pi->used == 0) { | ||
| 271 | hvlog("\n\rviocons: in sendbuffers(), but no buffers used.\n"); | ||
| 272 | vio_free_event_buffer(viomajorsubtype_chario, viochar); | ||
| 273 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 274 | return; | ||
| 275 | } | ||
| 276 | |||
| 277 | /* | ||
| 278 | * curbuf points to the buffer we're filling. We want to | ||
| 279 | * start sending AFTER this one. | ||
| 280 | */ | ||
| 281 | nextbuf = (pi->curbuf + 1) % VIOCHAR_NUM_BUF; | ||
| 282 | |||
| 283 | /* | ||
| 284 | * Loop until we find a buffer with the used bit on | ||
| 285 | */ | ||
| 286 | while (test_bit(nextbuf, &pi->used) == 0) | ||
| 287 | nextbuf = (nextbuf + 1) % VIOCHAR_NUM_BUF; | ||
| 288 | |||
| 289 | initDataEvent(viochar, pi->lp); | ||
| 290 | |||
| 291 | /* | ||
| 292 | * While we have buffers with data, and our send window | ||
| 293 | * is open, send them | ||
| 294 | */ | ||
| 295 | while ((test_bit(nextbuf, &pi->used)) && | ||
| 296 | ((pi->seq - pi->ack) < VIOCHAR_WINDOW)) { | ||
| 297 | viochar->len = pi->bufferBytes[nextbuf]; | ||
| 298 | viochar->event.xCorrelationToken = pi->seq++; | ||
| 299 | viochar->event.xSizeMinus1 = | ||
| 300 | offsetof(struct viocharlpevent, data) + viochar->len; | ||
| 301 | |||
| 302 | memcpy(viochar->data, pi->buffer[nextbuf], viochar->len); | ||
| 303 | |||
| 304 | hvrc = HvCallEvent_signalLpEvent(&viochar->event); | ||
| 305 | if (hvrc) { | ||
| 306 | /* | ||
| 307 | * MUST unlock the spinlock before doing a printk | ||
| 308 | */ | ||
| 309 | vio_free_event_buffer(viomajorsubtype_chario, viochar); | ||
| 310 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 311 | |||
| 312 | printk(VIOCONS_KERN_WARN | ||
| 313 | "error sending event! return code %d\n", | ||
| 314 | (int)hvrc); | ||
| 315 | return; | ||
| 316 | } | ||
| 317 | |||
| 318 | /* | ||
| 319 | * clear the used bit, zero the number of bytes in | ||
| 320 | * this buffer, and move to the next buffer | ||
| 321 | */ | ||
| 322 | clear_bit(nextbuf, &pi->used); | ||
| 323 | pi->bufferBytes[nextbuf] = 0; | ||
| 324 | nextbuf = (nextbuf + 1) % VIOCHAR_NUM_BUF; | ||
| 325 | } | ||
| 326 | |||
| 327 | /* | ||
| 328 | * If we have emptied all the buffers, start at 0 again. | ||
| 329 | * this will re-use any allocated buffers | ||
| 330 | */ | ||
| 331 | if (pi->used == 0) { | ||
| 332 | pi->curbuf = 0; | ||
| 333 | |||
| 334 | if (pi->overflowMessage) | ||
| 335 | pi->overflowMessage = 0; | ||
| 336 | |||
| 337 | if (pi->tty) { | ||
| 338 | tty_wakeup(pi->tty); | ||
| 339 | } | ||
| 340 | } | ||
| 341 | |||
| 342 | vio_free_event_buffer(viomajorsubtype_chario, viochar); | ||
| 343 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 344 | } | ||
| 345 | |||
| 346 | /* | ||
| 347 | * Our internal writer. Gets called both from the console device and | ||
| 348 | * the tty device. the tty pointer will be NULL if called from the console. | ||
| 349 | * Return total number of bytes "written". | ||
| 350 | * | ||
| 351 | * NOTE: Don't use printk in here because it gets nastily recursive. hvlog | ||
| 352 | * can be used to log to the hypervisor buffer | ||
| 353 | */ | ||
| 354 | static int internal_write(struct port_info *pi, const char *buf, size_t len) | ||
| 355 | { | ||
| 356 | HvLpEvent_Rc hvrc; | ||
| 357 | size_t bleft; | ||
| 358 | size_t curlen; | ||
| 359 | const char *curbuf; | ||
| 360 | unsigned long flags; | ||
| 361 | struct viocharlpevent *viochar; | ||
| 362 | |||
| 363 | /* | ||
| 364 | * Write to the hvlog of inbound data are now done prior to | ||
| 365 | * calling internal_write() since internal_write() is only called in | ||
| 366 | * the event that an lp event path is active, which isn't the case for | ||
| 367 | * logging attempts prior to console initialization. | ||
| 368 | * | ||
| 369 | * If there is already data queued for this port, send it prior to | ||
| 370 | * attempting to send any new data. | ||
| 371 | */ | ||
| 372 | if (pi->used) | ||
| 373 | send_buffers(pi); | ||
| 374 | |||
| 375 | spin_lock_irqsave(&consolelock, flags); | ||
| 376 | |||
| 377 | viochar = vio_get_event_buffer(viomajorsubtype_chario); | ||
| 378 | if (viochar == NULL) { | ||
| 379 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 380 | hvlog("\n\rviocons: Can't get vio buffer in internal_write()."); | ||
| 381 | return -EAGAIN; | ||
| 382 | } | ||
| 383 | initDataEvent(viochar, pi->lp); | ||
| 384 | |||
| 385 | curbuf = buf; | ||
| 386 | bleft = len; | ||
| 387 | |||
| 388 | while ((bleft > 0) && (pi->used == 0) && | ||
| 389 | ((pi->seq - pi->ack) < VIOCHAR_WINDOW)) { | ||
| 390 | if (bleft > VIOCHAR_MAX_DATA) | ||
| 391 | curlen = VIOCHAR_MAX_DATA; | ||
| 392 | else | ||
| 393 | curlen = bleft; | ||
| 394 | |||
| 395 | viochar->event.xCorrelationToken = pi->seq++; | ||
| 396 | memcpy(viochar->data, curbuf, curlen); | ||
| 397 | viochar->len = curlen; | ||
| 398 | viochar->event.xSizeMinus1 = | ||
| 399 | offsetof(struct viocharlpevent, data) + curlen; | ||
| 400 | |||
| 401 | hvrc = HvCallEvent_signalLpEvent(&viochar->event); | ||
| 402 | if (hvrc) { | ||
| 403 | hvlog("viocons: error sending event! %d\n", (int)hvrc); | ||
| 404 | goto out; | ||
| 405 | } | ||
| 406 | curbuf += curlen; | ||
| 407 | bleft -= curlen; | ||
| 408 | } | ||
| 409 | |||
| 410 | /* If we didn't send it all, buffer as much of it as we can. */ | ||
| 411 | if (bleft > 0) | ||
| 412 | bleft -= buffer_add(pi, curbuf, bleft); | ||
| 413 | out: | ||
| 414 | vio_free_event_buffer(viomajorsubtype_chario, viochar); | ||
| 415 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 416 | return len - bleft; | ||
| 417 | } | ||
| 418 | |||
| 419 | static struct port_info *get_port_data(struct tty_struct *tty) | ||
| 420 | { | ||
| 421 | unsigned long flags; | ||
| 422 | struct port_info *pi; | ||
| 423 | |||
| 424 | spin_lock_irqsave(&consolelock, flags); | ||
| 425 | if (tty) { | ||
| 426 | pi = (struct port_info *)tty->driver_data; | ||
| 427 | if (!pi || viotty_paranoia_check(pi, tty->name, | ||
| 428 | "get_port_data")) { | ||
| 429 | pi = NULL; | ||
| 430 | } | ||
| 431 | } else | ||
| 432 | /* | ||
| 433 | * If this is the console device, use the lp from | ||
| 434 | * the first port entry | ||
| 435 | */ | ||
| 436 | pi = &port_info[0]; | ||
| 437 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 438 | return pi; | ||
| 439 | } | ||
| 440 | |||
| 441 | /* | ||
| 442 | * Initialize the common fields in a charLpEvent | ||
| 443 | */ | ||
| 444 | static void initDataEvent(struct viocharlpevent *viochar, HvLpIndex lp) | ||
| 445 | { | ||
| 446 | struct HvLpEvent *hev = &viochar->event; | ||
| 447 | |||
| 448 | memset(viochar, 0, sizeof(struct viocharlpevent)); | ||
| 449 | |||
| 450 | hev->flags = HV_LP_EVENT_VALID | HV_LP_EVENT_DEFERRED_ACK | | ||
| 451 | HV_LP_EVENT_INT; | ||
| 452 | hev->xType = HvLpEvent_Type_VirtualIo; | ||
| 453 | hev->xSubtype = viomajorsubtype_chario | viochardata; | ||
| 454 | hev->xSourceLp = HvLpConfig_getLpIndex(); | ||
| 455 | hev->xTargetLp = lp; | ||
| 456 | hev->xSizeMinus1 = sizeof(struct viocharlpevent); | ||
| 457 | hev->xSourceInstanceId = viopath_sourceinst(lp); | ||
| 458 | hev->xTargetInstanceId = viopath_targetinst(lp); | ||
| 459 | } | ||
| 460 | |||
| 461 | /* | ||
| 462 | * early console device write | ||
| 463 | */ | ||
| 464 | static void viocons_write_early(struct console *co, const char *s, unsigned count) | ||
| 465 | { | ||
| 466 | hvlogOutput(s, count); | ||
| 467 | } | ||
| 468 | |||
| 469 | /* | ||
| 470 | * console device write | ||
| 471 | */ | ||
| 472 | static void viocons_write(struct console *co, const char *s, unsigned count) | ||
| 473 | { | ||
| 474 | int index; | ||
| 475 | int begin; | ||
| 476 | struct port_info *pi; | ||
| 477 | |||
| 478 | static const char cr = '\r'; | ||
| 479 | |||
| 480 | /* | ||
| 481 | * Check port data first because the target LP might be valid but | ||
| 482 | * simply not active, in which case we want to hvlog the output. | ||
| 483 | */ | ||
| 484 | pi = get_port_data(NULL); | ||
| 485 | if (pi == NULL) { | ||
| 486 | hvlog("\n\rviocons_write: unable to get port data."); | ||
| 487 | return; | ||
| 488 | } | ||
| 489 | |||
| 490 | hvlogOutput(s, count); | ||
| 491 | |||
| 492 | if (!viopath_isactive(pi->lp)) | ||
| 493 | return; | ||
| 494 | |||
| 495 | /* | ||
| 496 | * Any newline character found will cause a | ||
| 497 | * carriage return character to be emitted as well. | ||
| 498 | */ | ||
| 499 | begin = 0; | ||
| 500 | for (index = 0; index < count; index++) { | ||
| 501 | if (s[index] == '\n') { | ||
| 502 | /* | ||
| 503 | * Newline found. Print everything up to and | ||
| 504 | * including the newline | ||
| 505 | */ | ||
| 506 | internal_write(pi, &s[begin], index - begin + 1); | ||
| 507 | begin = index + 1; | ||
| 508 | /* Emit a carriage return as well */ | ||
| 509 | internal_write(pi, &cr, 1); | ||
| 510 | } | ||
| 511 | } | ||
| 512 | |||
| 513 | /* If any characters left to write, write them now */ | ||
| 514 | if ((index - begin) > 0) | ||
| 515 | internal_write(pi, &s[begin], index - begin); | ||
| 516 | } | ||
| 517 | |||
| 518 | /* | ||
| 519 | * Work out the device associate with this console | ||
| 520 | */ | ||
| 521 | static struct tty_driver *viocons_device(struct console *c, int *index) | ||
| 522 | { | ||
| 523 | *index = c->index; | ||
| 524 | return viotty_driver; | ||
| 525 | } | ||
| 526 | |||
| 527 | /* | ||
| 528 | * console device I/O methods | ||
| 529 | */ | ||
| 530 | static struct console viocons_early = { | ||
| 531 | .name = "viocons", | ||
| 532 | .write = viocons_write_early, | ||
| 533 | .flags = CON_PRINTBUFFER, | ||
| 534 | .index = -1, | ||
| 535 | }; | ||
| 536 | |||
| 537 | static struct console viocons = { | ||
| 538 | .name = "viocons", | ||
| 539 | .write = viocons_write, | ||
| 540 | .device = viocons_device, | ||
| 541 | .flags = CON_PRINTBUFFER, | ||
| 542 | .index = -1, | ||
| 543 | }; | ||
| 544 | |||
| 545 | /* | ||
| 546 | * TTY Open method | ||
| 547 | */ | ||
| 548 | static int viotty_open(struct tty_struct *tty, struct file *filp) | ||
| 549 | { | ||
| 550 | int port; | ||
| 551 | unsigned long flags; | ||
| 552 | struct port_info *pi; | ||
| 553 | |||
| 554 | port = tty->index; | ||
| 555 | |||
| 556 | if ((port < 0) || (port >= VTTY_PORTS)) | ||
| 557 | return -ENODEV; | ||
| 558 | |||
| 559 | spin_lock_irqsave(&consolelock, flags); | ||
| 560 | |||
| 561 | pi = &port_info[port]; | ||
| 562 | /* If some other TTY is already connected here, reject the open */ | ||
| 563 | if ((pi->tty) && (pi->tty != tty)) { | ||
| 564 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 565 | printk(VIOCONS_KERN_WARN | ||
| 566 | "attempt to open device twice from different ttys\n"); | ||
| 567 | return -EBUSY; | ||
| 568 | } | ||
| 569 | tty->driver_data = pi; | ||
| 570 | pi->tty = tty; | ||
| 571 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 572 | |||
| 573 | return 0; | ||
| 574 | } | ||
| 575 | |||
| 576 | /* | ||
| 577 | * TTY Close method | ||
| 578 | */ | ||
| 579 | static void viotty_close(struct tty_struct *tty, struct file *filp) | ||
| 580 | { | ||
| 581 | unsigned long flags; | ||
| 582 | struct port_info *pi; | ||
| 583 | |||
| 584 | spin_lock_irqsave(&consolelock, flags); | ||
| 585 | pi = (struct port_info *)tty->driver_data; | ||
| 586 | |||
| 587 | if (!pi || viotty_paranoia_check(pi, tty->name, "viotty_close")) { | ||
| 588 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 589 | return; | ||
| 590 | } | ||
| 591 | if (tty->count == 1) | ||
| 592 | pi->tty = NULL; | ||
| 593 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 594 | } | ||
| 595 | |||
| 596 | /* | ||
| 597 | * TTY Write method | ||
| 598 | */ | ||
| 599 | static int viotty_write(struct tty_struct *tty, const unsigned char *buf, | ||
| 600 | int count) | ||
| 601 | { | ||
| 602 | struct port_info *pi; | ||
| 603 | |||
| 604 | pi = get_port_data(tty); | ||
| 605 | if (pi == NULL) { | ||
| 606 | hvlog("\n\rviotty_write: no port data."); | ||
| 607 | return -ENODEV; | ||
| 608 | } | ||
| 609 | |||
| 610 | if (viochar_is_console(pi)) | ||
| 611 | hvlogOutput(buf, count); | ||
| 612 | |||
| 613 | /* | ||
| 614 | * If the path to this LP is closed, don't bother doing anything more. | ||
| 615 | * just dump the data on the floor and return count. For some reason | ||
| 616 | * some user level programs will attempt to probe available tty's and | ||
| 617 | * they'll attempt a viotty_write on an invalid port which maps to an | ||
| 618 | * invalid target lp. If this is the case then ignore the | ||
| 619 | * viotty_write call and, since the viopath isn't active to this | ||
| 620 | * partition, return count. | ||
| 621 | */ | ||
| 622 | if (!viopath_isactive(pi->lp)) | ||
| 623 | return count; | ||
| 624 | |||
| 625 | return internal_write(pi, buf, count); | ||
| 626 | } | ||
| 627 | |||
| 628 | /* | ||
| 629 | * TTY put_char method | ||
| 630 | */ | ||
| 631 | static int viotty_put_char(struct tty_struct *tty, unsigned char ch) | ||
| 632 | { | ||
| 633 | struct port_info *pi; | ||
| 634 | |||
| 635 | pi = get_port_data(tty); | ||
| 636 | if (pi == NULL) | ||
| 637 | return 0; | ||
| 638 | |||
| 639 | /* This will append '\r' as well if the char is '\n' */ | ||
| 640 | if (viochar_is_console(pi)) | ||
| 641 | hvlogOutput(&ch, 1); | ||
| 642 | |||
| 643 | if (viopath_isactive(pi->lp)) | ||
| 644 | internal_write(pi, &ch, 1); | ||
| 645 | return 1; | ||
| 646 | } | ||
| 647 | |||
| 648 | /* | ||
| 649 | * TTY write_room method | ||
| 650 | */ | ||
| 651 | static int viotty_write_room(struct tty_struct *tty) | ||
| 652 | { | ||
| 653 | int i; | ||
| 654 | int room = 0; | ||
| 655 | struct port_info *pi; | ||
| 656 | unsigned long flags; | ||
| 657 | |||
| 658 | spin_lock_irqsave(&consolelock, flags); | ||
| 659 | pi = (struct port_info *)tty->driver_data; | ||
| 660 | if (!pi || viotty_paranoia_check(pi, tty->name, "viotty_write_room")) { | ||
| 661 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 662 | return 0; | ||
| 663 | } | ||
| 664 | |||
| 665 | /* If no buffers are used, return the max size. */ | ||
| 666 | if (pi->used == 0) { | ||
| 667 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 668 | return VIOCHAR_MAX_DATA * VIOCHAR_NUM_BUF; | ||
| 669 | } | ||
| 670 | |||
| 671 | /* | ||
| 672 | * We retain the spinlock because we want to get an accurate | ||
| 673 | * count and it can change on us between each operation if we | ||
| 674 | * don't hold the spinlock. | ||
| 675 | */ | ||
| 676 | for (i = 0; ((i < VIOCHAR_NUM_BUF) && (room < VIOCHAR_MAX_DATA)); i++) | ||
| 677 | room += (VIOCHAR_MAX_DATA - pi->bufferBytes[i]); | ||
| 678 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 679 | |||
| 680 | if (room > VIOCHAR_MAX_DATA) | ||
| 681 | room = VIOCHAR_MAX_DATA; | ||
| 682 | return room; | ||
| 683 | } | ||
| 684 | |||
| 685 | /* | ||
| 686 | * TTY chars_in_buffer method | ||
| 687 | */ | ||
| 688 | static int viotty_chars_in_buffer(struct tty_struct *tty) | ||
| 689 | { | ||
| 690 | return 0; | ||
| 691 | } | ||
| 692 | |||
| 693 | static int viotty_ioctl(struct tty_struct *tty, struct file *file, | ||
| 694 | unsigned int cmd, unsigned long arg) | ||
| 695 | { | ||
| 696 | switch (cmd) { | ||
| 697 | /* | ||
| 698 | * the ioctls below read/set the flags usually shown in the leds | ||
| 699 | * don't use them - they will go away without warning | ||
| 700 | */ | ||
| 701 | case KDGETLED: | ||
| 702 | case KDGKBLED: | ||
| 703 | return put_user(0, (char *)arg); | ||
| 704 | |||
| 705 | case KDSKBLED: | ||
| 706 | return 0; | ||
| 707 | } | ||
| 708 | /* FIXME: WTF is this being called for ??? */ | ||
| 709 | lock_kernel(); | ||
| 710 | ret = n_tty_ioctl(tty, file, cmd, arg); | ||
| 711 | unlock_kernel(); | ||
| 712 | return ret; | ||
| 713 | } | ||
| 714 | |||
| 715 | /* | ||
| 716 | * Handle an open charLpEvent. Could be either interrupt or ack | ||
| 717 | */ | ||
| 718 | static void vioHandleOpenEvent(struct HvLpEvent *event) | ||
| 719 | { | ||
| 720 | unsigned long flags; | ||
| 721 | struct viocharlpevent *cevent = (struct viocharlpevent *)event; | ||
| 722 | u8 port = cevent->virtual_device; | ||
| 723 | struct port_info *pi; | ||
| 724 | int reject = 0; | ||
| 725 | |||
| 726 | if (hvlpevent_is_ack(event)) { | ||
| 727 | if (port >= VTTY_PORTS) | ||
| 728 | return; | ||
| 729 | |||
| 730 | spin_lock_irqsave(&consolelock, flags); | ||
| 731 | /* Got the lock, don't cause console output */ | ||
| 732 | |||
| 733 | pi = &port_info[port]; | ||
| 734 | if (event->xRc == HvLpEvent_Rc_Good) { | ||
| 735 | pi->seq = pi->ack = 0; | ||
| 736 | /* | ||
| 737 | * This line allows connections from the primary | ||
| 738 | * partition but once one is connected from the | ||
| 739 | * primary partition nothing short of a reboot | ||
| 740 | * of linux will allow access from the hosting | ||
| 741 | * partition again without a required iSeries fix. | ||
| 742 | */ | ||
| 743 | pi->lp = event->xTargetLp; | ||
| 744 | } | ||
| 745 | |||
| 746 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 747 | if (event->xRc != HvLpEvent_Rc_Good) | ||
| 748 | printk(VIOCONS_KERN_WARN | ||
| 749 | "handle_open_event: event->xRc == (%d).\n", | ||
| 750 | event->xRc); | ||
| 751 | |||
| 752 | if (event->xCorrelationToken != 0) { | ||
| 753 | atomic_t *aptr= (atomic_t *)event->xCorrelationToken; | ||
| 754 | atomic_set(aptr, 1); | ||
| 755 | } else | ||
| 756 | printk(VIOCONS_KERN_WARN | ||
| 757 | "weird...got open ack without atomic\n"); | ||
| 758 | return; | ||
| 759 | } | ||
| 760 | |||
| 761 | /* This had better require an ack, otherwise complain */ | ||
| 762 | if (!hvlpevent_need_ack(event)) { | ||
| 763 | printk(VIOCONS_KERN_WARN "viocharopen without ack bit!\n"); | ||
| 764 | return; | ||
| 765 | } | ||
| 766 | |||
| 767 | spin_lock_irqsave(&consolelock, flags); | ||
| 768 | /* Got the lock, don't cause console output */ | ||
| 769 | |||
| 770 | /* Make sure this is a good virtual tty */ | ||
| 771 | if (port >= VTTY_PORTS) { | ||
| 772 | event->xRc = HvLpEvent_Rc_SubtypeError; | ||
| 773 | cevent->subtype_result_code = viorc_openRejected; | ||
| 774 | /* | ||
| 775 | * Flag state here since we can't printk while holding | ||
| 776 | * a spinlock. | ||
| 777 | */ | ||
| 778 | reject = 1; | ||
| 779 | } else { | ||
| 780 | pi = &port_info[port]; | ||
| 781 | if ((pi->lp != HvLpIndexInvalid) && | ||
| 782 | (pi->lp != event->xSourceLp)) { | ||
| 783 | /* | ||
| 784 | * If this is tty is already connected to a different | ||
| 785 | * partition, fail. | ||
| 786 | */ | ||
| 787 | event->xRc = HvLpEvent_Rc_SubtypeError; | ||
| 788 | cevent->subtype_result_code = viorc_openRejected; | ||
| 789 | reject = 2; | ||
| 790 | } else { | ||
| 791 | pi->lp = event->xSourceLp; | ||
| 792 | event->xRc = HvLpEvent_Rc_Good; | ||
| 793 | cevent->subtype_result_code = viorc_good; | ||
| 794 | pi->seq = pi->ack = 0; | ||
| 795 | reject = 0; | ||
| 796 | } | ||
| 797 | } | ||
| 798 | |||
| 799 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 800 | |||
| 801 | if (reject == 1) | ||
| 802 | printk(VIOCONS_KERN_WARN "open rejected: bad virtual tty.\n"); | ||
| 803 | else if (reject == 2) | ||
| 804 | printk(VIOCONS_KERN_WARN | ||
| 805 | "open rejected: console in exclusive use by another partition.\n"); | ||
| 806 | |||
| 807 | /* Return the acknowledgement */ | ||
| 808 | HvCallEvent_ackLpEvent(event); | ||
| 809 | } | ||
| 810 | |||
| 811 | /* | ||
| 812 | * Handle a close charLpEvent. This should ONLY be an Interrupt because the | ||
| 813 | * virtual console should never actually issue a close event to the hypervisor | ||
| 814 | * because the virtual console never goes away. A close event coming from the | ||
| 815 | * hypervisor simply means that there are no client consoles connected to the | ||
| 816 | * virtual console. | ||
| 817 | * | ||
| 818 | * Regardless of the number of connections masqueraded on the other side of | ||
| 819 | * the hypervisor ONLY ONE close event should be called to accompany the ONE | ||
| 820 | * open event that is called. The close event should ONLY be called when NO | ||
| 821 | * MORE connections (masqueraded or not) exist on the other side of the | ||
| 822 | * hypervisor. | ||
| 823 | */ | ||
| 824 | static void vioHandleCloseEvent(struct HvLpEvent *event) | ||
| 825 | { | ||
| 826 | unsigned long flags; | ||
| 827 | struct viocharlpevent *cevent = (struct viocharlpevent *)event; | ||
| 828 | u8 port = cevent->virtual_device; | ||
| 829 | |||
| 830 | if (hvlpevent_is_int(event)) { | ||
| 831 | if (port >= VTTY_PORTS) { | ||
| 832 | printk(VIOCONS_KERN_WARN | ||
| 833 | "close message from invalid virtual device.\n"); | ||
| 834 | return; | ||
| 835 | } | ||
| 836 | |||
| 837 | /* For closes, just mark the console partition invalid */ | ||
| 838 | spin_lock_irqsave(&consolelock, flags); | ||
| 839 | /* Got the lock, don't cause console output */ | ||
| 840 | |||
| 841 | if (port_info[port].lp == event->xSourceLp) | ||
| 842 | port_info[port].lp = HvLpIndexInvalid; | ||
| 843 | |||
| 844 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 845 | printk(VIOCONS_KERN_INFO "close from %d\n", event->xSourceLp); | ||
| 846 | } else | ||
| 847 | printk(VIOCONS_KERN_WARN | ||
| 848 | "got unexpected close acknowlegement\n"); | ||
| 849 | } | ||
| 850 | |||
| 851 | /* | ||
| 852 | * Handle a config charLpEvent. Could be either interrupt or ack | ||
| 853 | */ | ||
| 854 | static void vioHandleConfig(struct HvLpEvent *event) | ||
| 855 | { | ||
| 856 | struct viocharlpevent *cevent = (struct viocharlpevent *)event; | ||
| 857 | |||
| 858 | HvCall_writeLogBuffer(cevent->data, cevent->len); | ||
| 859 | |||
| 860 | if (cevent->data[0] == 0x01) | ||
| 861 | printk(VIOCONS_KERN_INFO "window resized to %d: %d: %d: %d\n", | ||
| 862 | cevent->data[1], cevent->data[2], | ||
| 863 | cevent->data[3], cevent->data[4]); | ||
| 864 | else | ||
| 865 | printk(VIOCONS_KERN_WARN "unknown config event\n"); | ||
| 866 | } | ||
| 867 | |||
| 868 | /* | ||
| 869 | * Handle a data charLpEvent. | ||
| 870 | */ | ||
| 871 | static void vioHandleData(struct HvLpEvent *event) | ||
| 872 | { | ||
| 873 | struct tty_struct *tty; | ||
| 874 | unsigned long flags; | ||
| 875 | struct viocharlpevent *cevent = (struct viocharlpevent *)event; | ||
| 876 | struct port_info *pi; | ||
| 877 | int index; | ||
| 878 | int num_pushed; | ||
| 879 | u8 port = cevent->virtual_device; | ||
| 880 | |||
| 881 | if (port >= VTTY_PORTS) { | ||
| 882 | printk(VIOCONS_KERN_WARN "data on invalid virtual device %d\n", | ||
| 883 | port); | ||
| 884 | return; | ||
| 885 | } | ||
| 886 | |||
| 887 | /* | ||
| 888 | * Hold the spinlock so that we don't take an interrupt that | ||
| 889 | * changes tty between the time we fetch the port_info | ||
| 890 | * pointer and the time we paranoia check. | ||
| 891 | */ | ||
| 892 | spin_lock_irqsave(&consolelock, flags); | ||
| 893 | pi = &port_info[port]; | ||
| 894 | |||
| 895 | /* | ||
| 896 | * Change 05/01/2003 - Ryan Arnold: If a partition other than | ||
| 897 | * the current exclusive partition tries to send us data | ||
| 898 | * events then just drop them on the floor because we don't | ||
| 899 | * want his stinking data. He isn't authorized to receive | ||
| 900 | * data because he wasn't the first one to get the console, | ||
| 901 | * therefore he shouldn't be allowed to send data either. | ||
| 902 | * This will work without an iSeries fix. | ||
| 903 | */ | ||
| 904 | if (pi->lp != event->xSourceLp) { | ||
| 905 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 906 | return; | ||
| 907 | } | ||
| 908 | |||
| 909 | tty = pi->tty; | ||
| 910 | if (tty == NULL) { | ||
| 911 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 912 | printk(VIOCONS_KERN_WARN "no tty for virtual device %d\n", | ||
| 913 | port); | ||
| 914 | return; | ||
| 915 | } | ||
| 916 | |||
| 917 | if (tty->magic != TTY_MAGIC) { | ||
| 918 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 919 | printk(VIOCONS_KERN_WARN "tty bad magic\n"); | ||
| 920 | return; | ||
| 921 | } | ||
| 922 | |||
| 923 | /* | ||
| 924 | * Just to be paranoid, make sure the tty points back to this port | ||
| 925 | */ | ||
| 926 | pi = (struct port_info *)tty->driver_data; | ||
| 927 | if (!pi || viotty_paranoia_check(pi, tty->name, "vioHandleData")) { | ||
| 928 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 929 | return; | ||
| 930 | } | ||
| 931 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 932 | |||
| 933 | /* | ||
| 934 | * Change 07/21/2003 - Ryan Arnold: functionality added to | ||
| 935 | * support sysrq utilizing ^O as the sysrq key. The sysrq | ||
| 936 | * functionality will only work if built into the kernel and | ||
| 937 | * then only if sysrq is enabled through the proc filesystem. | ||
| 938 | */ | ||
| 939 | num_pushed = 0; | ||
| 940 | for (index = 0; index < cevent->len; index++) { | ||
| 941 | /* | ||
| 942 | * Will be optimized away if !CONFIG_MAGIC_SYSRQ: | ||
| 943 | */ | ||
| 944 | if (sysrq_on()) { | ||
| 945 | /* 0x0f is the ascii character for ^O */ | ||
| 946 | if (cevent->data[index] == '\x0f') { | ||
| 947 | vio_sysrq_pressed = 1; | ||
| 948 | /* | ||
| 949 | * continue because we don't want to add | ||
| 950 | * the sysrq key into the data string. | ||
| 951 | */ | ||
| 952 | continue; | ||
| 953 | } else if (vio_sysrq_pressed) { | ||
| 954 | handle_sysrq(cevent->data[index], tty); | ||
| 955 | vio_sysrq_pressed = 0; | ||
| 956 | /* | ||
| 957 | * continue because we don't want to add | ||
| 958 | * the sysrq sequence into the data string. | ||
| 959 | */ | ||
| 960 | continue; | ||
| 961 | } | ||
| 962 | } | ||
| 963 | /* | ||
| 964 | * The sysrq sequence isn't included in this check if | ||
| 965 | * sysrq is enabled and compiled into the kernel because | ||
| 966 | * the sequence will never get inserted into the buffer. | ||
| 967 | * Don't attempt to copy more data into the buffer than we | ||
| 968 | * have room for because it would fail without indication. | ||
| 969 | */ | ||
| 970 | if(tty_insert_flip_char(tty, cevent->data[index], TTY_NORMAL) == 0) { | ||
| 971 | printk(VIOCONS_KERN_WARN "input buffer overflow!\n"); | ||
| 972 | break; | ||
| 973 | } | ||
| 974 | num_pushed++; | ||
| 975 | } | ||
| 976 | |||
| 977 | if (num_pushed) | ||
| 978 | tty_flip_buffer_push(tty); | ||
| 979 | } | ||
| 980 | |||
| 981 | /* | ||
| 982 | * Handle an ack charLpEvent. | ||
| 983 | */ | ||
| 984 | static void vioHandleAck(struct HvLpEvent *event) | ||
| 985 | { | ||
| 986 | struct viocharlpevent *cevent = (struct viocharlpevent *)event; | ||
| 987 | unsigned long flags; | ||
| 988 | u8 port = cevent->virtual_device; | ||
| 989 | |||
| 990 | if (port >= VTTY_PORTS) { | ||
| 991 | printk(VIOCONS_KERN_WARN "data on invalid virtual device\n"); | ||
| 992 | return; | ||
| 993 | } | ||
| 994 | |||
| 995 | spin_lock_irqsave(&consolelock, flags); | ||
| 996 | port_info[port].ack = event->xCorrelationToken; | ||
| 997 | spin_unlock_irqrestore(&consolelock, flags); | ||
| 998 | |||
| 999 | if (port_info[port].used) | ||
| 1000 | send_buffers(&port_info[port]); | ||
| 1001 | } | ||
| 1002 | |||
| 1003 | /* | ||
| 1004 | * Handle charLpEvents and route to the appropriate routine | ||
| 1005 | */ | ||
| 1006 | static void vioHandleCharEvent(struct HvLpEvent *event) | ||
| 1007 | { | ||
| 1008 | int charminor; | ||
| 1009 | |||
| 1010 | if (event == NULL) | ||
| 1011 | return; | ||
| 1012 | |||
| 1013 | charminor = event->xSubtype & VIOMINOR_SUBTYPE_MASK; | ||
| 1014 | switch (charminor) { | ||
| 1015 | case viocharopen: | ||
| 1016 | vioHandleOpenEvent(event); | ||
| 1017 | break; | ||
| 1018 | case viocharclose: | ||
| 1019 | vioHandleCloseEvent(event); | ||
| 1020 | break; | ||
| 1021 | case viochardata: | ||
| 1022 | vioHandleData(event); | ||
| 1023 | break; | ||
| 1024 | case viocharack: | ||
| 1025 | vioHandleAck(event); | ||
| 1026 | break; | ||
| 1027 | case viocharconfig: | ||
| 1028 | vioHandleConfig(event); | ||
| 1029 | break; | ||
| 1030 | default: | ||
| 1031 | if (hvlpevent_is_int(event) && hvlpevent_need_ack(event)) { | ||
| 1032 | event->xRc = HvLpEvent_Rc_InvalidSubtype; | ||
| 1033 | HvCallEvent_ackLpEvent(event); | ||
| 1034 | } | ||
| 1035 | } | ||
| 1036 | } | ||
| 1037 | |||
| 1038 | /* | ||
| 1039 | * Send an open event | ||
| 1040 | */ | ||
| 1041 | static int send_open(HvLpIndex remoteLp, void *sem) | ||
| 1042 | { | ||
| 1043 | return HvCallEvent_signalLpEventFast(remoteLp, | ||
| 1044 | HvLpEvent_Type_VirtualIo, | ||
| 1045 | viomajorsubtype_chario | viocharopen, | ||
| 1046 | HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck, | ||
| 1047 | viopath_sourceinst(remoteLp), | ||
| 1048 | viopath_targetinst(remoteLp), | ||
| 1049 | (u64)(unsigned long)sem, VIOVERSION << 16, | ||
| 1050 | 0, 0, 0, 0); | ||
| 1051 | } | ||
| 1052 | |||
| 1053 | static const struct tty_operations serial_ops = { | ||
| 1054 | .open = viotty_open, | ||
| 1055 | .close = viotty_close, | ||
| 1056 | .write = viotty_write, | ||
| 1057 | .put_char = viotty_put_char, | ||
| 1058 | .write_room = viotty_write_room, | ||
| 1059 | .chars_in_buffer = viotty_chars_in_buffer, | ||
| 1060 | .ioctl = viotty_ioctl, | ||
| 1061 | }; | ||
| 1062 | |||
| 1063 | static int __init viocons_init2(void) | ||
| 1064 | { | ||
| 1065 | atomic_t wait_flag; | ||
| 1066 | int rc; | ||
| 1067 | |||
| 1068 | if (!firmware_has_feature(FW_FEATURE_ISERIES)) | ||
| 1069 | return -ENODEV; | ||
| 1070 | |||
| 1071 | /* +2 for fudge */ | ||
| 1072 | rc = viopath_open(HvLpConfig_getPrimaryLpIndex(), | ||
| 1073 | viomajorsubtype_chario, VIOCHAR_WINDOW + 2); | ||
| 1074 | if (rc) | ||
| 1075 | printk(VIOCONS_KERN_WARN "error opening to primary %d\n", rc); | ||
| 1076 | |||
| 1077 | if (viopath_hostLp == HvLpIndexInvalid) | ||
| 1078 | vio_set_hostlp(); | ||
| 1079 | |||
| 1080 | /* | ||
| 1081 | * And if the primary is not the same as the hosting LP, open to the | ||
| 1082 | * hosting lp | ||
| 1083 | */ | ||
| 1084 | if ((viopath_hostLp != HvLpIndexInvalid) && | ||
| 1085 | (viopath_hostLp != HvLpConfig_getPrimaryLpIndex())) { | ||
| 1086 | printk(VIOCONS_KERN_INFO "open path to hosting (%d)\n", | ||
| 1087 | viopath_hostLp); | ||
| 1088 | rc = viopath_open(viopath_hostLp, viomajorsubtype_chario, | ||
| 1089 | VIOCHAR_WINDOW + 2); /* +2 for fudge */ | ||
| 1090 | if (rc) | ||
| 1091 | printk(VIOCONS_KERN_WARN | ||
| 1092 | "error opening to partition %d: %d\n", | ||
| 1093 | viopath_hostLp, rc); | ||
| 1094 | } | ||
| 1095 | |||
| 1096 | if (vio_setHandler(viomajorsubtype_chario, vioHandleCharEvent) < 0) | ||
| 1097 | printk(VIOCONS_KERN_WARN | ||
| 1098 | "error seting handler for console events!\n"); | ||
| 1099 | |||
| 1100 | /* | ||
| 1101 | * First, try to open the console to the hosting lp. | ||
| 1102 | * Wait on a semaphore for the response. | ||
| 1103 | */ | ||
| 1104 | atomic_set(&wait_flag, 0); | ||
| 1105 | if ((viopath_isactive(viopath_hostLp)) && | ||
| 1106 | (send_open(viopath_hostLp, (void *)&wait_flag) == 0)) { | ||
| 1107 | printk(VIOCONS_KERN_INFO "hosting partition %d\n", | ||
| 1108 | viopath_hostLp); | ||
| 1109 | while (atomic_read(&wait_flag) == 0) | ||
| 1110 | mb(); | ||
| 1111 | atomic_set(&wait_flag, 0); | ||
| 1112 | } | ||
| 1113 | |||
| 1114 | /* | ||
| 1115 | * If we don't have an active console, try the primary | ||
| 1116 | */ | ||
| 1117 | if ((!viopath_isactive(port_info[0].lp)) && | ||
| 1118 | (viopath_isactive(HvLpConfig_getPrimaryLpIndex())) && | ||
| 1119 | (send_open(HvLpConfig_getPrimaryLpIndex(), (void *)&wait_flag) | ||
| 1120 | == 0)) { | ||
| 1121 | printk(VIOCONS_KERN_INFO "opening console to primary partition\n"); | ||
| 1122 | while (atomic_read(&wait_flag) == 0) | ||
| 1123 | mb(); | ||
| 1124 | } | ||
| 1125 | |||
| 1126 | /* Initialize the tty_driver structure */ | ||
| 1127 | viotty_driver = alloc_tty_driver(VTTY_PORTS); | ||
| 1128 | viotty_driver->owner = THIS_MODULE; | ||
| 1129 | viotty_driver->driver_name = "vioconsole"; | ||
| 1130 | viotty_driver->name = "tty"; | ||
| 1131 | viotty_driver->name_base = 1; | ||
| 1132 | viotty_driver->major = TTY_MAJOR; | ||
| 1133 | viotty_driver->minor_start = 1; | ||
| 1134 | viotty_driver->type = TTY_DRIVER_TYPE_CONSOLE; | ||
| 1135 | viotty_driver->subtype = 1; | ||
| 1136 | viotty_driver->init_termios = tty_std_termios; | ||
| 1137 | viotty_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_RESET_TERMIOS; | ||
| 1138 | tty_set_operations(viotty_driver, &serial_ops); | ||
| 1139 | |||
| 1140 | if (tty_register_driver(viotty_driver)) { | ||
| 1141 | printk(VIOCONS_KERN_WARN "couldn't register console driver\n"); | ||
| 1142 | put_tty_driver(viotty_driver); | ||
| 1143 | viotty_driver = NULL; | ||
| 1144 | } | ||
| 1145 | |||
| 1146 | unregister_console(&viocons_early); | ||
| 1147 | register_console(&viocons); | ||
| 1148 | |||
| 1149 | return 0; | ||
| 1150 | } | ||
| 1151 | |||
| 1152 | static int __init viocons_init(void) | ||
| 1153 | { | ||
| 1154 | int i; | ||
| 1155 | |||
| 1156 | if (!firmware_has_feature(FW_FEATURE_ISERIES)) | ||
| 1157 | return -ENODEV; | ||
| 1158 | |||
| 1159 | printk(VIOCONS_KERN_INFO "registering console\n"); | ||
| 1160 | for (i = 0; i < VTTY_PORTS; i++) { | ||
| 1161 | port_info[i].lp = HvLpIndexInvalid; | ||
| 1162 | port_info[i].magic = VIOTTY_MAGIC; | ||
| 1163 | } | ||
| 1164 | HvCall_setLogBufferFormatAndCodepage(HvCall_LogBuffer_ASCII, 437); | ||
| 1165 | add_preferred_console("viocons", 0, NULL); | ||
| 1166 | register_console(&viocons_early); | ||
| 1167 | return 0; | ||
| 1168 | } | ||
| 1169 | |||
| 1170 | console_initcall(viocons_init); | ||
| 1171 | module_init(viocons_init2); | ||
diff --git a/drivers/cpufreq/cpufreq_conservative.c b/drivers/cpufreq/cpufreq_conservative.c index fe565ee43757..ac0bbf2d234f 100644 --- a/drivers/cpufreq/cpufreq_conservative.c +++ b/drivers/cpufreq/cpufreq_conservative.c | |||
| @@ -333,7 +333,7 @@ static void dbs_check_cpu(int cpu) | |||
| 333 | { | 333 | { |
| 334 | unsigned int idle_ticks, up_idle_ticks, down_idle_ticks; | 334 | unsigned int idle_ticks, up_idle_ticks, down_idle_ticks; |
| 335 | unsigned int tmp_idle_ticks, total_idle_ticks; | 335 | unsigned int tmp_idle_ticks, total_idle_ticks; |
| 336 | unsigned int freq_step; | 336 | unsigned int freq_target; |
| 337 | unsigned int freq_down_sampling_rate; | 337 | unsigned int freq_down_sampling_rate; |
| 338 | struct cpu_dbs_info_s *this_dbs_info = &per_cpu(cpu_dbs_info, cpu); | 338 | struct cpu_dbs_info_s *this_dbs_info = &per_cpu(cpu_dbs_info, cpu); |
| 339 | struct cpufreq_policy *policy; | 339 | struct cpufreq_policy *policy; |
| @@ -383,13 +383,13 @@ static void dbs_check_cpu(int cpu) | |||
| 383 | if (this_dbs_info->requested_freq == policy->max) | 383 | if (this_dbs_info->requested_freq == policy->max) |
| 384 | return; | 384 | return; |
| 385 | 385 | ||
| 386 | freq_step = (dbs_tuners_ins.freq_step * policy->max) / 100; | 386 | freq_target = (dbs_tuners_ins.freq_step * policy->max) / 100; |
| 387 | 387 | ||
| 388 | /* max freq cannot be less than 100. But who knows.... */ | 388 | /* max freq cannot be less than 100. But who knows.... */ |
| 389 | if (unlikely(freq_step == 0)) | 389 | if (unlikely(freq_target == 0)) |
| 390 | freq_step = 5; | 390 | freq_target = 5; |
| 391 | 391 | ||
| 392 | this_dbs_info->requested_freq += freq_step; | 392 | this_dbs_info->requested_freq += freq_target; |
| 393 | if (this_dbs_info->requested_freq > policy->max) | 393 | if (this_dbs_info->requested_freq > policy->max) |
| 394 | this_dbs_info->requested_freq = policy->max; | 394 | this_dbs_info->requested_freq = policy->max; |
| 395 | 395 | ||
| @@ -425,19 +425,19 @@ static void dbs_check_cpu(int cpu) | |||
| 425 | /* | 425 | /* |
| 426 | * if we are already at the lowest speed then break out early | 426 | * if we are already at the lowest speed then break out early |
| 427 | * or if we 'cannot' reduce the speed as the user might want | 427 | * or if we 'cannot' reduce the speed as the user might want |
| 428 | * freq_step to be zero | 428 | * freq_target to be zero |
| 429 | */ | 429 | */ |
| 430 | if (this_dbs_info->requested_freq == policy->min | 430 | if (this_dbs_info->requested_freq == policy->min |
| 431 | || dbs_tuners_ins.freq_step == 0) | 431 | || dbs_tuners_ins.freq_step == 0) |
| 432 | return; | 432 | return; |
| 433 | 433 | ||
| 434 | freq_step = (dbs_tuners_ins.freq_step * policy->max) / 100; | 434 | freq_target = (dbs_tuners_ins.freq_step * policy->max) / 100; |
| 435 | 435 | ||
| 436 | /* max freq cannot be less than 100. But who knows.... */ | 436 | /* max freq cannot be less than 100. But who knows.... */ |
| 437 | if (unlikely(freq_step == 0)) | 437 | if (unlikely(freq_target == 0)) |
| 438 | freq_step = 5; | 438 | freq_target = 5; |
| 439 | 439 | ||
| 440 | this_dbs_info->requested_freq -= freq_step; | 440 | this_dbs_info->requested_freq -= freq_target; |
| 441 | if (this_dbs_info->requested_freq < policy->min) | 441 | if (this_dbs_info->requested_freq < policy->min) |
| 442 | this_dbs_info->requested_freq = policy->min; | 442 | this_dbs_info->requested_freq = policy->min; |
| 443 | 443 | ||
diff --git a/drivers/dma/ioat_dma.c b/drivers/dma/ioat_dma.c index a52156e56886..bc8c6e3470ca 100644 --- a/drivers/dma/ioat_dma.c +++ b/drivers/dma/ioat_dma.c | |||
| @@ -551,7 +551,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) | |||
| 551 | /* write address into NextDescriptor field of last desc in chain */ | 551 | /* write address into NextDescriptor field of last desc in chain */ |
| 552 | to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = | 552 | to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = |
| 553 | first->async_tx.phys; | 553 | first->async_tx.phys; |
| 554 | __list_splice(&new_chain, ioat_chan->used_desc.prev); | 554 | list_splice_tail(&new_chain, &ioat_chan->used_desc); |
| 555 | 555 | ||
| 556 | ioat_chan->dmacount += desc_count; | 556 | ioat_chan->dmacount += desc_count; |
| 557 | ioat_chan->pending += desc_count; | 557 | ioat_chan->pending += desc_count; |
diff --git a/drivers/firewire/fw-cdev.c b/drivers/firewire/fw-cdev.c index bc81d6fcd2fd..2e6d5848d217 100644 --- a/drivers/firewire/fw-cdev.c +++ b/drivers/firewire/fw-cdev.c | |||
| @@ -369,22 +369,33 @@ complete_transaction(struct fw_card *card, int rcode, | |||
| 369 | struct response *response = data; | 369 | struct response *response = data; |
| 370 | struct client *client = response->client; | 370 | struct client *client = response->client; |
| 371 | unsigned long flags; | 371 | unsigned long flags; |
| 372 | struct fw_cdev_event_response *r = &response->response; | ||
| 372 | 373 | ||
| 373 | if (length < response->response.length) | 374 | if (length < r->length) |
| 374 | response->response.length = length; | 375 | r->length = length; |
| 375 | if (rcode == RCODE_COMPLETE) | 376 | if (rcode == RCODE_COMPLETE) |
| 376 | memcpy(response->response.data, payload, | 377 | memcpy(r->data, payload, r->length); |
| 377 | response->response.length); | ||
| 378 | 378 | ||
| 379 | spin_lock_irqsave(&client->lock, flags); | 379 | spin_lock_irqsave(&client->lock, flags); |
| 380 | list_del(&response->resource.link); | 380 | list_del(&response->resource.link); |
| 381 | spin_unlock_irqrestore(&client->lock, flags); | 381 | spin_unlock_irqrestore(&client->lock, flags); |
| 382 | 382 | ||
| 383 | response->response.type = FW_CDEV_EVENT_RESPONSE; | 383 | r->type = FW_CDEV_EVENT_RESPONSE; |
| 384 | response->response.rcode = rcode; | 384 | r->rcode = rcode; |
| 385 | queue_event(client, &response->event, &response->response, | 385 | |
| 386 | sizeof(response->response) + response->response.length, | 386 | /* |
| 387 | NULL, 0); | 387 | * In the case that sizeof(*r) doesn't align with the position of the |
| 388 | * data, and the read is short, preserve an extra copy of the data | ||
| 389 | * to stay compatible with a pre-2.6.27 bug. Since the bug is harmless | ||
| 390 | * for short reads and some apps depended on it, this is both safe | ||
| 391 | * and prudent for compatibility. | ||
| 392 | */ | ||
| 393 | if (r->length <= sizeof(*r) - offsetof(typeof(*r), data)) | ||
| 394 | queue_event(client, &response->event, r, sizeof(*r), | ||
| 395 | r->data, r->length); | ||
| 396 | else | ||
| 397 | queue_event(client, &response->event, r, sizeof(*r) + r->length, | ||
| 398 | NULL, 0); | ||
| 388 | } | 399 | } |
| 389 | 400 | ||
| 390 | static int ioctl_send_request(struct client *client, void *buffer) | 401 | static int ioctl_send_request(struct client *client, void *buffer) |
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index c882fd05cf29..bf4ebfb86fa5 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig | |||
| @@ -57,6 +57,16 @@ config SENSORS_ABITUGURU3 | |||
| 57 | This driver can also be built as a module. If so, the module | 57 | This driver can also be built as a module. If so, the module |
| 58 | will be called abituguru3. | 58 | will be called abituguru3. |
| 59 | 59 | ||
| 60 | config SENSORS_AD7414 | ||
| 61 | tristate "Analog Devices AD7414" | ||
| 62 | depends on I2C && EXPERIMENTAL | ||
| 63 | help | ||
| 64 | If you say yes here you get support for the Analog Devices | ||
| 65 | AD7414 temperature monitoring chip. | ||
| 66 | |||
| 67 | This driver can also be built as a module. If so, the module | ||
| 68 | will be called ad7414. | ||
| 69 | |||
| 60 | config SENSORS_AD7418 | 70 | config SENSORS_AD7418 |
| 61 | tristate "Analog Devices AD7416, AD7417 and AD7418" | 71 | tristate "Analog Devices AD7416, AD7417 and AD7418" |
| 62 | depends on I2C && EXPERIMENTAL | 72 | depends on I2C && EXPERIMENTAL |
| @@ -124,7 +134,7 @@ config SENSORS_ADM1031 | |||
| 124 | 134 | ||
| 125 | config SENSORS_ADM9240 | 135 | config SENSORS_ADM9240 |
| 126 | tristate "Analog Devices ADM9240 and compatibles" | 136 | tristate "Analog Devices ADM9240 and compatibles" |
| 127 | depends on I2C && EXPERIMENTAL | 137 | depends on I2C |
| 128 | select HWMON_VID | 138 | select HWMON_VID |
| 129 | help | 139 | help |
| 130 | If you say yes here you get support for Analog Devices ADM9240, | 140 | If you say yes here you get support for Analog Devices ADM9240, |
| @@ -575,8 +585,8 @@ config SENSORS_DME1737 | |||
| 575 | select HWMON_VID | 585 | select HWMON_VID |
| 576 | help | 586 | help |
| 577 | If you say yes here you get support for the hardware monitoring | 587 | If you say yes here you get support for the hardware monitoring |
| 578 | and fan control features of the SMSC DME1737 (and compatibles | 588 | and fan control features of the SMSC DME1737, SCH311x, SCH5027, and |
| 579 | like the Asus A8000) and SCH311x Super-I/O chips. | 589 | Asus A8000 Super-I/O chips. |
| 580 | 590 | ||
| 581 | This driver can also be built as a module. If so, the module | 591 | This driver can also be built as a module. If so, the module |
| 582 | will be called dme1737. | 592 | will be called dme1737. |
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index d098677e08de..7943e5cefb06 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile | |||
| @@ -15,6 +15,7 @@ obj-$(CONFIG_SENSORS_W83791D) += w83791d.o | |||
| 15 | 15 | ||
| 16 | obj-$(CONFIG_SENSORS_ABITUGURU) += abituguru.o | 16 | obj-$(CONFIG_SENSORS_ABITUGURU) += abituguru.o |
| 17 | obj-$(CONFIG_SENSORS_ABITUGURU3)+= abituguru3.o | 17 | obj-$(CONFIG_SENSORS_ABITUGURU3)+= abituguru3.o |
| 18 | obj-$(CONFIG_SENSORS_AD7414) += ad7414.o | ||
| 18 | obj-$(CONFIG_SENSORS_AD7418) += ad7418.o | 19 | obj-$(CONFIG_SENSORS_AD7418) += ad7418.o |
| 19 | obj-$(CONFIG_SENSORS_ADM1021) += adm1021.o | 20 | obj-$(CONFIG_SENSORS_ADM1021) += adm1021.o |
| 20 | obj-$(CONFIG_SENSORS_ADM1025) += adm1025.o | 21 | obj-$(CONFIG_SENSORS_ADM1025) += adm1025.o |
diff --git a/drivers/hwmon/ad7414.c b/drivers/hwmon/ad7414.c new file mode 100644 index 000000000000..ce8d94fbfd7e --- /dev/null +++ b/drivers/hwmon/ad7414.c | |||
| @@ -0,0 +1,268 @@ | |||
| 1 | /* | ||
| 2 | * An hwmon driver for the Analog Devices AD7414 | ||
| 3 | * | ||
| 4 | * Copyright 2006 Stefan Roese <sr at denx.de>, DENX Software Engineering | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 PIKA Technologies | ||
| 7 | * Sean MacLennan <smaclennan@pikatech.com> | ||
| 8 | * | ||
| 9 | * Copyright (c) 2008 Spansion Inc. | ||
| 10 | * Frank Edelhaeuser <frank.edelhaeuser at spansion.com> | ||
| 11 | * (converted to "new style" I2C driver model, removed checkpatch.pl warnings) | ||
| 12 | * | ||
| 13 | * Based on ad7418.c | ||
| 14 | * Copyright 2006 Tower Technologies, Alessandro Zummo <a.zummo at towertech.it> | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2 of the License, or | ||
| 19 | * (at your option) any later version. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/module.h> | ||
| 23 | #include <linux/jiffies.h> | ||
| 24 | #include <linux/i2c.h> | ||
| 25 | #include <linux/hwmon.h> | ||
| 26 | #include <linux/hwmon-sysfs.h> | ||
| 27 | #include <linux/err.h> | ||
| 28 | #include <linux/mutex.h> | ||
| 29 | #include <linux/sysfs.h> | ||
| 30 | |||
| 31 | |||
| 32 | /* AD7414 registers */ | ||
| 33 | #define AD7414_REG_TEMP 0x00 | ||
| 34 | #define AD7414_REG_CONF 0x01 | ||
| 35 | #define AD7414_REG_T_HIGH 0x02 | ||
| 36 | #define AD7414_REG_T_LOW 0x03 | ||
| 37 | |||
| 38 | static u8 AD7414_REG_LIMIT[] = { AD7414_REG_T_HIGH, AD7414_REG_T_LOW }; | ||
| 39 | |||
| 40 | struct ad7414_data { | ||
| 41 | struct device *hwmon_dev; | ||
| 42 | struct mutex lock; /* atomic read data updates */ | ||
| 43 | char valid; /* !=0 if following fields are valid */ | ||
| 44 | unsigned long next_update; /* In jiffies */ | ||
| 45 | s16 temp_input; /* Register values */ | ||
| 46 | s8 temps[ARRAY_SIZE(AD7414_REG_LIMIT)]; | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* REG: (0.25C/bit, two's complement) << 6 */ | ||
| 50 | static inline int ad7414_temp_from_reg(s16 reg) | ||
| 51 | { | ||
| 52 | /* use integer division instead of equivalent right shift to | ||
| 53 | * guarantee arithmetic shift and preserve the sign | ||
| 54 | */ | ||
| 55 | return ((int)reg / 64) * 250; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline int ad7414_read(struct i2c_client *client, u8 reg) | ||
| 59 | { | ||
| 60 | if (reg == AD7414_REG_TEMP) { | ||
| 61 | int value = i2c_smbus_read_word_data(client, reg); | ||
| 62 | return (value < 0) ? value : swab16(value); | ||
| 63 | } else | ||
| 64 | return i2c_smbus_read_byte_data(client, reg); | ||
| 65 | } | ||
| 66 | |||
| 67 | static inline int ad7414_write(struct i2c_client *client, u8 reg, u8 value) | ||
| 68 | { | ||
| 69 | return i2c_smbus_write_byte_data(client, reg, value); | ||
| 70 | } | ||
| 71 | |||
| 72 | struct ad7414_data *ad7414_update_device(struct device *dev) | ||
| 73 | { | ||
| 74 | struct i2c_client *client = to_i2c_client(dev); | ||
| 75 | struct ad7414_data *data = i2c_get_clientdata(client); | ||
| 76 | |||
| 77 | mutex_lock(&data->lock); | ||
| 78 | |||
| 79 | if (time_after(jiffies, data->next_update) || !data->valid) { | ||
| 80 | int value, i; | ||
| 81 | |||
| 82 | dev_dbg(&client->dev, "starting ad7414 update\n"); | ||
| 83 | |||
| 84 | value = ad7414_read(client, AD7414_REG_TEMP); | ||
| 85 | if (value < 0) | ||
| 86 | dev_dbg(&client->dev, "AD7414_REG_TEMP err %d\n", | ||
| 87 | value); | ||
| 88 | else | ||
| 89 | data->temp_input = value; | ||
| 90 | |||
| 91 | for (i = 0; i < ARRAY_SIZE(AD7414_REG_LIMIT); ++i) { | ||
| 92 | value = ad7414_read(client, AD7414_REG_LIMIT[i]); | ||
| 93 | if (value < 0) | ||
| 94 | dev_dbg(&client->dev, "AD7414 reg %d err %d\n", | ||
| 95 | AD7414_REG_LIMIT[i], value); | ||
| 96 | else | ||
| 97 | data->temps[i] = value; | ||
| 98 | } | ||
| 99 | |||
| 100 | data->next_update = jiffies + HZ + HZ / 2; | ||
| 101 | data->valid = 1; | ||
| 102 | } | ||
| 103 | |||
| 104 | mutex_unlock(&data->lock); | ||
| 105 | |||
| 106 | return data; | ||
| 107 | } | ||
| 108 | |||
| 109 | static ssize_t show_temp_input(struct device *dev, | ||
| 110 | struct device_attribute *attr, char *buf) | ||
| 111 | { | ||
| 112 | struct ad7414_data *data = ad7414_update_device(dev); | ||
| 113 | return sprintf(buf, "%d\n", ad7414_temp_from_reg(data->temp_input)); | ||
| 114 | } | ||
| 115 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp_input, NULL, 0); | ||
| 116 | |||
| 117 | static ssize_t show_max_min(struct device *dev, struct device_attribute *attr, | ||
| 118 | char *buf) | ||
| 119 | { | ||
| 120 | int index = to_sensor_dev_attr(attr)->index; | ||
| 121 | struct ad7414_data *data = ad7414_update_device(dev); | ||
| 122 | return sprintf(buf, "%d\n", data->temps[index] * 1000); | ||
| 123 | } | ||
| 124 | |||
| 125 | static ssize_t set_max_min(struct device *dev, | ||
| 126 | struct device_attribute *attr, | ||
| 127 | const char *buf, size_t count) | ||
| 128 | { | ||
| 129 | struct i2c_client *client = to_i2c_client(dev); | ||
| 130 | struct ad7414_data *data = i2c_get_clientdata(client); | ||
| 131 | int index = to_sensor_dev_attr(attr)->index; | ||
| 132 | u8 reg = AD7414_REG_LIMIT[index]; | ||
| 133 | long temp = simple_strtol(buf, NULL, 10); | ||
| 134 | |||
| 135 | temp = SENSORS_LIMIT(temp, -40000, 85000); | ||
| 136 | temp = (temp + (temp < 0 ? -500 : 500)) / 1000; | ||
| 137 | |||
| 138 | mutex_lock(&data->lock); | ||
| 139 | data->temps[index] = temp; | ||
| 140 | ad7414_write(client, reg, temp); | ||
| 141 | mutex_unlock(&data->lock); | ||
| 142 | return count; | ||
| 143 | } | ||
| 144 | |||
| 145 | static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO, | ||
| 146 | show_max_min, set_max_min, 0); | ||
| 147 | static SENSOR_DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO, | ||
| 148 | show_max_min, set_max_min, 1); | ||
| 149 | |||
| 150 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, | ||
| 151 | char *buf) | ||
| 152 | { | ||
| 153 | int bitnr = to_sensor_dev_attr(attr)->index; | ||
| 154 | struct ad7414_data *data = ad7414_update_device(dev); | ||
| 155 | int value = (data->temp_input >> bitnr) & 1; | ||
| 156 | return sprintf(buf, "%d\n", value); | ||
| 157 | } | ||
| 158 | |||
| 159 | static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL, 3); | ||
| 160 | static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL, 4); | ||
| 161 | |||
| 162 | static struct attribute *ad7414_attributes[] = { | ||
| 163 | &sensor_dev_attr_temp1_input.dev_attr.attr, | ||
| 164 | &sensor_dev_attr_temp1_max.dev_attr.attr, | ||
| 165 | &sensor_dev_attr_temp1_min.dev_attr.attr, | ||
| 166 | &sensor_dev_attr_temp1_max_alarm.dev_attr.attr, | ||
| 167 | &sensor_dev_attr_temp1_min_alarm.dev_attr.attr, | ||
| 168 | NULL | ||
| 169 | }; | ||
| 170 | |||
| 171 | static const struct attribute_group ad7414_group = { | ||
| 172 | .attrs = ad7414_attributes, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static int ad7414_probe(struct i2c_client *client, | ||
| 176 | const struct i2c_device_id *dev_id) | ||
| 177 | { | ||
| 178 | struct ad7414_data *data; | ||
| 179 | int conf; | ||
| 180 | int err = 0; | ||
| 181 | |||
| 182 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA | | ||
| 183 | I2C_FUNC_SMBUS_READ_WORD_DATA)) | ||
| 184 | goto exit; | ||
| 185 | |||
| 186 | data = kzalloc(sizeof(struct ad7414_data), GFP_KERNEL); | ||
| 187 | if (!data) { | ||
| 188 | err = -ENOMEM; | ||
| 189 | goto exit; | ||
| 190 | } | ||
| 191 | |||
| 192 | i2c_set_clientdata(client, data); | ||
| 193 | mutex_init(&data->lock); | ||
| 194 | |||
| 195 | dev_info(&client->dev, "chip found\n"); | ||
| 196 | |||
| 197 | /* Make sure the chip is powered up. */ | ||
| 198 | conf = i2c_smbus_read_byte_data(client, AD7414_REG_CONF); | ||
| 199 | if (conf < 0) | ||
| 200 | dev_warn(&client->dev, | ||
| 201 | "ad7414_probe unable to read config register.\n"); | ||
| 202 | else { | ||
| 203 | conf &= ~(1 << 7); | ||
| 204 | i2c_smbus_write_byte_data(client, AD7414_REG_CONF, conf); | ||
| 205 | } | ||
| 206 | |||
| 207 | /* Register sysfs hooks */ | ||
| 208 | err = sysfs_create_group(&client->dev.kobj, &ad7414_group); | ||
| 209 | if (err) | ||
| 210 | goto exit_free; | ||
| 211 | |||
| 212 | data->hwmon_dev = hwmon_device_register(&client->dev); | ||
| 213 | if (IS_ERR(data->hwmon_dev)) { | ||
| 214 | err = PTR_ERR(data->hwmon_dev); | ||
| 215 | goto exit_remove; | ||
| 216 | } | ||
| 217 | |||
| 218 | return 0; | ||
| 219 | |||
| 220 | exit_remove: | ||
| 221 | sysfs_remove_group(&client->dev.kobj, &ad7414_group); | ||
| 222 | exit_free: | ||
| 223 | kfree(data); | ||
| 224 | exit: | ||
| 225 | return err; | ||
| 226 | } | ||
| 227 | |||
| 228 | static int __devexit ad7414_remove(struct i2c_client *client) | ||
| 229 | { | ||
| 230 | struct ad7414_data *data = i2c_get_clientdata(client); | ||
| 231 | |||
| 232 | hwmon_device_unregister(data->hwmon_dev); | ||
| 233 | sysfs_remove_group(&client->dev.kobj, &ad7414_group); | ||
| 234 | kfree(data); | ||
| 235 | return 0; | ||
| 236 | } | ||
| 237 | |||
| 238 | static const struct i2c_device_id ad7414_id[] = { | ||
| 239 | { "ad7414", 0 }, | ||
| 240 | {} | ||
| 241 | }; | ||
| 242 | |||
| 243 | static struct i2c_driver ad7414_driver = { | ||
| 244 | .driver = { | ||
| 245 | .name = "ad7414", | ||
| 246 | }, | ||
| 247 | .probe = ad7414_probe, | ||
| 248 | .remove = __devexit_p(ad7414_remove), | ||
| 249 | .id_table = ad7414_id, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static int __init ad7414_init(void) | ||
| 253 | { | ||
| 254 | return i2c_add_driver(&ad7414_driver); | ||
| 255 | } | ||
| 256 | module_init(ad7414_init); | ||
| 257 | |||
| 258 | static void __exit ad7414_exit(void) | ||
| 259 | { | ||
| 260 | i2c_del_driver(&ad7414_driver); | ||
| 261 | } | ||
| 262 | module_exit(ad7414_exit); | ||
| 263 | |||
| 264 | MODULE_AUTHOR("Stefan Roese <sr at denx.de>, " | ||
| 265 | "Frank Edelhaeuser <frank.edelhaeuser at spansion.com>"); | ||
| 266 | |||
| 267 | MODULE_DESCRIPTION("AD7414 driver"); | ||
| 268 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/hwmon/dme1737.c b/drivers/hwmon/dme1737.c index 5e2cf0aef480..cdb8311e4ef7 100644 --- a/drivers/hwmon/dme1737.c +++ b/drivers/hwmon/dme1737.c | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * dme1737.c - Driver for the SMSC DME1737, Asus A8000, and SMSC SCH311x | 2 | * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x and |
| 3 | * Super-I/O chips integrated hardware monitoring features. | 3 | * SCH5027 Super-I/O chips integrated hardware monitoring features. |
| 4 | * Copyright (c) 2007 Juerg Haefliger <juergh@gmail.com> | 4 | * Copyright (c) 2007, 2008 Juerg Haefliger <juergh@gmail.com> |
| 5 | * | 5 | * |
| 6 | * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access | 6 | * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access |
| 7 | * the chip registers if a DME1737 (or A8000) is found and the ISA bus if a | 7 | * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus |
| 8 | * SCH311x chip is found. Both types of chips have very similar hardware | 8 | * if a SCH311x chip is found. Both types of chips have very similar hardware |
| 9 | * monitoring capabilities but differ in the way they can be accessed. | 9 | * monitoring capabilities but differ in the way they can be accessed. |
| 10 | * | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| @@ -57,7 +57,10 @@ MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC " | |||
| 57 | static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; | 57 | static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; |
| 58 | 58 | ||
| 59 | /* Insmod parameters */ | 59 | /* Insmod parameters */ |
| 60 | I2C_CLIENT_INSMOD_1(dme1737); | 60 | I2C_CLIENT_INSMOD_2(dme1737, sch5027); |
| 61 | |||
| 62 | /* ISA chip types */ | ||
| 63 | enum isa_chips { sch311x = sch5027 + 1 }; | ||
| 61 | 64 | ||
| 62 | /* --------------------------------------------------------------------- | 65 | /* --------------------------------------------------------------------- |
| 63 | * Registers | 66 | * Registers |
| @@ -163,6 +166,7 @@ static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; | |||
| 163 | #define DME1737_VERSTEP 0x88 | 166 | #define DME1737_VERSTEP 0x88 |
| 164 | #define DME1737_VERSTEP_MASK 0xf8 | 167 | #define DME1737_VERSTEP_MASK 0xf8 |
| 165 | #define SCH311X_DEVICE 0x8c | 168 | #define SCH311X_DEVICE 0x8c |
| 169 | #define SCH5027_VERSTEP 0x69 | ||
| 166 | 170 | ||
| 167 | /* Length of ISA address segment */ | 171 | /* Length of ISA address segment */ |
| 168 | #define DME1737_EXTENT 2 | 172 | #define DME1737_EXTENT 2 |
| @@ -182,6 +186,7 @@ struct dme1737_data { | |||
| 182 | unsigned long last_update; /* in jiffies */ | 186 | unsigned long last_update; /* in jiffies */ |
| 183 | unsigned long last_vbat; /* in jiffies */ | 187 | unsigned long last_vbat; /* in jiffies */ |
| 184 | enum chips type; | 188 | enum chips type; |
| 189 | const int *in_nominal; /* pointer to IN_NOMINAL array */ | ||
| 185 | 190 | ||
| 186 | u8 vid; | 191 | u8 vid; |
| 187 | u8 pwm_rr_en; | 192 | u8 pwm_rr_en; |
| @@ -220,23 +225,23 @@ static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, | |||
| 220 | 3300}; | 225 | 3300}; |
| 221 | static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, | 226 | static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, |
| 222 | 3300}; | 227 | 3300}; |
| 223 | #define IN_NOMINAL(ix, type) (((type) == dme1737) ? \ | 228 | static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, |
| 224 | IN_NOMINAL_DME1737[(ix)] : \ | 229 | 3300}; |
| 225 | IN_NOMINAL_SCH311x[(ix)]) | 230 | #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ |
| 231 | (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ | ||
| 232 | IN_NOMINAL_DME1737) | ||
| 226 | 233 | ||
| 227 | /* Voltage input | 234 | /* Voltage input |
| 228 | * Voltage inputs have 16 bits resolution, limit values have 8 bits | 235 | * Voltage inputs have 16 bits resolution, limit values have 8 bits |
| 229 | * resolution. */ | 236 | * resolution. */ |
| 230 | static inline int IN_FROM_REG(int reg, int ix, int res, int type) | 237 | static inline int IN_FROM_REG(int reg, int nominal, int res) |
| 231 | { | 238 | { |
| 232 | return (reg * IN_NOMINAL(ix, type) + (3 << (res - 3))) / | 239 | return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); |
| 233 | (3 << (res - 2)); | ||
| 234 | } | 240 | } |
| 235 | 241 | ||
| 236 | static inline int IN_TO_REG(int val, int ix, int type) | 242 | static inline int IN_TO_REG(int val, int nominal) |
| 237 | { | 243 | { |
| 238 | return SENSORS_LIMIT((val * 192 + IN_NOMINAL(ix, type) / 2) / | 244 | return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); |
| 239 | IN_NOMINAL(ix, type), 0, 255); | ||
| 240 | } | 245 | } |
| 241 | 246 | ||
| 242 | /* Temperature input | 247 | /* Temperature input |
| @@ -565,7 +570,10 @@ static struct dme1737_data *dme1737_update_device(struct device *dev) | |||
| 565 | 570 | ||
| 566 | /* Sample register contents every 1 sec */ | 571 | /* Sample register contents every 1 sec */ |
| 567 | if (time_after(jiffies, data->last_update + HZ) || !data->valid) { | 572 | if (time_after(jiffies, data->last_update + HZ) || !data->valid) { |
| 568 | data->vid = dme1737_read(client, DME1737_REG_VID) & 0x3f; | 573 | if (data->type != sch5027) { |
| 574 | data->vid = dme1737_read(client, DME1737_REG_VID) & | ||
| 575 | 0x3f; | ||
| 576 | } | ||
| 569 | 577 | ||
| 570 | /* In (voltage) registers */ | 578 | /* In (voltage) registers */ |
| 571 | for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { | 579 | for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { |
| @@ -593,8 +601,10 @@ static struct dme1737_data *dme1737_update_device(struct device *dev) | |||
| 593 | DME1737_REG_TEMP_MIN(ix)); | 601 | DME1737_REG_TEMP_MIN(ix)); |
| 594 | data->temp_max[ix] = dme1737_read(client, | 602 | data->temp_max[ix] = dme1737_read(client, |
| 595 | DME1737_REG_TEMP_MAX(ix)); | 603 | DME1737_REG_TEMP_MAX(ix)); |
| 596 | data->temp_offset[ix] = dme1737_read(client, | 604 | if (data->type != sch5027) { |
| 597 | DME1737_REG_TEMP_OFFSET(ix)); | 605 | data->temp_offset[ix] = dme1737_read(client, |
| 606 | DME1737_REG_TEMP_OFFSET(ix)); | ||
| 607 | } | ||
| 598 | } | 608 | } |
| 599 | 609 | ||
| 600 | /* In and temp LSB registers | 610 | /* In and temp LSB registers |
| @@ -669,9 +679,11 @@ static struct dme1737_data *dme1737_update_device(struct device *dev) | |||
| 669 | data->zone_abs[ix] = dme1737_read(client, | 679 | data->zone_abs[ix] = dme1737_read(client, |
| 670 | DME1737_REG_ZONE_ABS(ix)); | 680 | DME1737_REG_ZONE_ABS(ix)); |
| 671 | } | 681 | } |
| 672 | for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { | 682 | if (data->type != sch5027) { |
| 673 | data->zone_hyst[ix] = dme1737_read(client, | 683 | for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { |
| 684 | data->zone_hyst[ix] = dme1737_read(client, | ||
| 674 | DME1737_REG_ZONE_HYST(ix)); | 685 | DME1737_REG_ZONE_HYST(ix)); |
| 686 | } | ||
| 675 | } | 687 | } |
| 676 | 688 | ||
| 677 | /* Alarm registers */ | 689 | /* Alarm registers */ |
| @@ -735,13 +747,13 @@ static ssize_t show_in(struct device *dev, struct device_attribute *attr, | |||
| 735 | 747 | ||
| 736 | switch (fn) { | 748 | switch (fn) { |
| 737 | case SYS_IN_INPUT: | 749 | case SYS_IN_INPUT: |
| 738 | res = IN_FROM_REG(data->in[ix], ix, 16, data->type); | 750 | res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); |
| 739 | break; | 751 | break; |
| 740 | case SYS_IN_MIN: | 752 | case SYS_IN_MIN: |
| 741 | res = IN_FROM_REG(data->in_min[ix], ix, 8, data->type); | 753 | res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); |
| 742 | break; | 754 | break; |
| 743 | case SYS_IN_MAX: | 755 | case SYS_IN_MAX: |
| 744 | res = IN_FROM_REG(data->in_max[ix], ix, 8, data->type); | 756 | res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); |
| 745 | break; | 757 | break; |
| 746 | case SYS_IN_ALARM: | 758 | case SYS_IN_ALARM: |
| 747 | res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; | 759 | res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; |
| @@ -768,12 +780,12 @@ static ssize_t set_in(struct device *dev, struct device_attribute *attr, | |||
| 768 | mutex_lock(&data->update_lock); | 780 | mutex_lock(&data->update_lock); |
| 769 | switch (fn) { | 781 | switch (fn) { |
| 770 | case SYS_IN_MIN: | 782 | case SYS_IN_MIN: |
| 771 | data->in_min[ix] = IN_TO_REG(val, ix, data->type); | 783 | data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); |
| 772 | dme1737_write(client, DME1737_REG_IN_MIN(ix), | 784 | dme1737_write(client, DME1737_REG_IN_MIN(ix), |
| 773 | data->in_min[ix]); | 785 | data->in_min[ix]); |
| 774 | break; | 786 | break; |
| 775 | case SYS_IN_MAX: | 787 | case SYS_IN_MAX: |
| 776 | data->in_max[ix] = IN_TO_REG(val, ix, data->type); | 788 | data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); |
| 777 | dme1737_write(client, DME1737_REG_IN_MAX(ix), | 789 | dme1737_write(client, DME1737_REG_IN_MAX(ix), |
| 778 | data->in_max[ix]); | 790 | data->in_max[ix]); |
| 779 | break; | 791 | break; |
| @@ -1166,7 +1178,7 @@ static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, | |||
| 1166 | return sprintf(buf, "%d\n", res); | 1178 | return sprintf(buf, "%d\n", res); |
| 1167 | } | 1179 | } |
| 1168 | 1180 | ||
| 1169 | static struct attribute *dme1737_attr_pwm[]; | 1181 | static struct attribute *dme1737_pwm_chmod_attr[]; |
| 1170 | static void dme1737_chmod_file(struct device*, struct attribute*, mode_t); | 1182 | static void dme1737_chmod_file(struct device*, struct attribute*, mode_t); |
| 1171 | 1183 | ||
| 1172 | static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, | 1184 | static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, |
| @@ -1230,7 +1242,7 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, | |||
| 1230 | switch (val) { | 1242 | switch (val) { |
| 1231 | case 0: | 1243 | case 0: |
| 1232 | /* Change permissions of pwm[ix] to read-only */ | 1244 | /* Change permissions of pwm[ix] to read-only */ |
| 1233 | dme1737_chmod_file(dev, dme1737_attr_pwm[ix], | 1245 | dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], |
| 1234 | S_IRUGO); | 1246 | S_IRUGO); |
| 1235 | /* Turn fan fully on */ | 1247 | /* Turn fan fully on */ |
| 1236 | data->pwm_config[ix] = PWM_EN_TO_REG(0, | 1248 | data->pwm_config[ix] = PWM_EN_TO_REG(0, |
| @@ -1245,12 +1257,12 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, | |||
| 1245 | dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), | 1257 | dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), |
| 1246 | data->pwm_config[ix]); | 1258 | data->pwm_config[ix]); |
| 1247 | /* Change permissions of pwm[ix] to read-writeable */ | 1259 | /* Change permissions of pwm[ix] to read-writeable */ |
| 1248 | dme1737_chmod_file(dev, dme1737_attr_pwm[ix], | 1260 | dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], |
| 1249 | S_IRUGO | S_IWUSR); | 1261 | S_IRUGO | S_IWUSR); |
| 1250 | break; | 1262 | break; |
| 1251 | case 2: | 1263 | case 2: |
| 1252 | /* Change permissions of pwm[ix] to read-only */ | 1264 | /* Change permissions of pwm[ix] to read-only */ |
| 1253 | dme1737_chmod_file(dev, dme1737_attr_pwm[ix], | 1265 | dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], |
| 1254 | S_IRUGO); | 1266 | S_IRUGO); |
| 1255 | /* Turn on auto mode using the saved zone channel | 1267 | /* Turn on auto mode using the saved zone channel |
| 1256 | * assignment */ | 1268 | * assignment */ |
| @@ -1570,88 +1582,98 @@ static struct attribute *dme1737_attr[] ={ | |||
| 1570 | &sensor_dev_attr_temp1_max.dev_attr.attr, | 1582 | &sensor_dev_attr_temp1_max.dev_attr.attr, |
| 1571 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, | 1583 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, |
| 1572 | &sensor_dev_attr_temp1_fault.dev_attr.attr, | 1584 | &sensor_dev_attr_temp1_fault.dev_attr.attr, |
| 1573 | &sensor_dev_attr_temp1_offset.dev_attr.attr, | ||
| 1574 | &sensor_dev_attr_temp2_input.dev_attr.attr, | 1585 | &sensor_dev_attr_temp2_input.dev_attr.attr, |
| 1575 | &sensor_dev_attr_temp2_min.dev_attr.attr, | 1586 | &sensor_dev_attr_temp2_min.dev_attr.attr, |
| 1576 | &sensor_dev_attr_temp2_max.dev_attr.attr, | 1587 | &sensor_dev_attr_temp2_max.dev_attr.attr, |
| 1577 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, | 1588 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, |
| 1578 | &sensor_dev_attr_temp2_fault.dev_attr.attr, | 1589 | &sensor_dev_attr_temp2_fault.dev_attr.attr, |
| 1579 | &sensor_dev_attr_temp2_offset.dev_attr.attr, | ||
| 1580 | &sensor_dev_attr_temp3_input.dev_attr.attr, | 1590 | &sensor_dev_attr_temp3_input.dev_attr.attr, |
| 1581 | &sensor_dev_attr_temp3_min.dev_attr.attr, | 1591 | &sensor_dev_attr_temp3_min.dev_attr.attr, |
| 1582 | &sensor_dev_attr_temp3_max.dev_attr.attr, | 1592 | &sensor_dev_attr_temp3_max.dev_attr.attr, |
| 1583 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, | 1593 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, |
| 1584 | &sensor_dev_attr_temp3_fault.dev_attr.attr, | 1594 | &sensor_dev_attr_temp3_fault.dev_attr.attr, |
| 1585 | &sensor_dev_attr_temp3_offset.dev_attr.attr, | ||
| 1586 | /* Zones */ | 1595 | /* Zones */ |
| 1587 | &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1588 | &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, | 1596 | &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, |
| 1589 | &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, | 1597 | &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, |
| 1590 | &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, | 1598 | &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, |
| 1591 | &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, | 1599 | &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, |
| 1592 | &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1593 | &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, | 1600 | &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, |
| 1594 | &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, | 1601 | &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, |
| 1595 | &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, | 1602 | &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, |
| 1596 | &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, | 1603 | &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, |
| 1597 | &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1598 | &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, | 1604 | &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, |
| 1599 | &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, | 1605 | &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, |
| 1600 | &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, | 1606 | &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, |
| 1601 | &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, | 1607 | &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, |
| 1608 | NULL | ||
| 1609 | }; | ||
| 1610 | |||
| 1611 | static const struct attribute_group dme1737_group = { | ||
| 1612 | .attrs = dme1737_attr, | ||
| 1613 | }; | ||
| 1614 | |||
| 1615 | /* The following struct holds misc attributes, which are not available in all | ||
| 1616 | * chips. Their creation depends on the chip type which is determined during | ||
| 1617 | * module load. */ | ||
| 1618 | static struct attribute *dme1737_misc_attr[] = { | ||
| 1619 | /* Temperatures */ | ||
| 1620 | &sensor_dev_attr_temp1_offset.dev_attr.attr, | ||
| 1621 | &sensor_dev_attr_temp2_offset.dev_attr.attr, | ||
| 1622 | &sensor_dev_attr_temp3_offset.dev_attr.attr, | ||
| 1623 | /* Zones */ | ||
| 1624 | &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1625 | &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1626 | &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1602 | /* Misc */ | 1627 | /* Misc */ |
| 1603 | &dev_attr_vrm.attr, | 1628 | &dev_attr_vrm.attr, |
| 1604 | &dev_attr_cpu0_vid.attr, | 1629 | &dev_attr_cpu0_vid.attr, |
| 1605 | NULL | 1630 | NULL |
| 1606 | }; | 1631 | }; |
| 1607 | 1632 | ||
| 1608 | static const struct attribute_group dme1737_group = { | 1633 | static const struct attribute_group dme1737_misc_group = { |
| 1609 | .attrs = dme1737_attr, | 1634 | .attrs = dme1737_misc_attr, |
| 1610 | }; | 1635 | }; |
| 1611 | 1636 | ||
| 1612 | /* The following structs hold the PWM attributes, some of which are optional. | 1637 | /* The following structs hold the PWM attributes, some of which are optional. |
| 1613 | * Their creation depends on the chip configuration which is determined during | 1638 | * Their creation depends on the chip configuration which is determined during |
| 1614 | * module load. */ | 1639 | * module load. */ |
| 1615 | static struct attribute *dme1737_attr_pwm1[] = { | 1640 | static struct attribute *dme1737_pwm1_attr[] = { |
| 1616 | &sensor_dev_attr_pwm1.dev_attr.attr, | 1641 | &sensor_dev_attr_pwm1.dev_attr.attr, |
| 1617 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, | 1642 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, |
| 1618 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, | 1643 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, |
| 1619 | &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, | 1644 | &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, |
| 1620 | &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, | 1645 | &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, |
| 1621 | &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, | ||
| 1622 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, | 1646 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, |
| 1623 | &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, | 1647 | &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, |
| 1624 | NULL | 1648 | NULL |
| 1625 | }; | 1649 | }; |
| 1626 | static struct attribute *dme1737_attr_pwm2[] = { | 1650 | static struct attribute *dme1737_pwm2_attr[] = { |
| 1627 | &sensor_dev_attr_pwm2.dev_attr.attr, | 1651 | &sensor_dev_attr_pwm2.dev_attr.attr, |
| 1628 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, | 1652 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, |
| 1629 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, | 1653 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, |
| 1630 | &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, | 1654 | &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, |
| 1631 | &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, | 1655 | &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, |
| 1632 | &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, | ||
| 1633 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, | 1656 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, |
| 1634 | &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, | 1657 | &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, |
| 1635 | NULL | 1658 | NULL |
| 1636 | }; | 1659 | }; |
| 1637 | static struct attribute *dme1737_attr_pwm3[] = { | 1660 | static struct attribute *dme1737_pwm3_attr[] = { |
| 1638 | &sensor_dev_attr_pwm3.dev_attr.attr, | 1661 | &sensor_dev_attr_pwm3.dev_attr.attr, |
| 1639 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, | 1662 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, |
| 1640 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, | 1663 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, |
| 1641 | &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, | 1664 | &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, |
| 1642 | &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, | 1665 | &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, |
| 1643 | &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, | ||
| 1644 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, | 1666 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, |
| 1645 | &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, | 1667 | &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, |
| 1646 | NULL | 1668 | NULL |
| 1647 | }; | 1669 | }; |
| 1648 | static struct attribute *dme1737_attr_pwm5[] = { | 1670 | static struct attribute *dme1737_pwm5_attr[] = { |
| 1649 | &sensor_dev_attr_pwm5.dev_attr.attr, | 1671 | &sensor_dev_attr_pwm5.dev_attr.attr, |
| 1650 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, | 1672 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, |
| 1651 | &sensor_dev_attr_pwm5_enable.dev_attr.attr, | 1673 | &sensor_dev_attr_pwm5_enable.dev_attr.attr, |
| 1652 | NULL | 1674 | NULL |
| 1653 | }; | 1675 | }; |
| 1654 | static struct attribute *dme1737_attr_pwm6[] = { | 1676 | static struct attribute *dme1737_pwm6_attr[] = { |
| 1655 | &sensor_dev_attr_pwm6.dev_attr.attr, | 1677 | &sensor_dev_attr_pwm6.dev_attr.attr, |
| 1656 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, | 1678 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, |
| 1657 | &sensor_dev_attr_pwm6_enable.dev_attr.attr, | 1679 | &sensor_dev_attr_pwm6_enable.dev_attr.attr, |
| @@ -1659,53 +1681,62 @@ static struct attribute *dme1737_attr_pwm6[] = { | |||
| 1659 | }; | 1681 | }; |
| 1660 | 1682 | ||
| 1661 | static const struct attribute_group dme1737_pwm_group[] = { | 1683 | static const struct attribute_group dme1737_pwm_group[] = { |
| 1662 | { .attrs = dme1737_attr_pwm1 }, | 1684 | { .attrs = dme1737_pwm1_attr }, |
| 1663 | { .attrs = dme1737_attr_pwm2 }, | 1685 | { .attrs = dme1737_pwm2_attr }, |
| 1664 | { .attrs = dme1737_attr_pwm3 }, | 1686 | { .attrs = dme1737_pwm3_attr }, |
| 1665 | { .attrs = NULL }, | 1687 | { .attrs = NULL }, |
| 1666 | { .attrs = dme1737_attr_pwm5 }, | 1688 | { .attrs = dme1737_pwm5_attr }, |
| 1667 | { .attrs = dme1737_attr_pwm6 }, | 1689 | { .attrs = dme1737_pwm6_attr }, |
| 1690 | }; | ||
| 1691 | |||
| 1692 | /* The following struct holds misc PWM attributes, which are not available in | ||
| 1693 | * all chips. Their creation depends on the chip type which is determined | ||
| 1694 | * during module load. */ | ||
| 1695 | static struct attribute *dme1737_pwm_misc_attr[] = { | ||
| 1696 | &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, | ||
| 1697 | &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, | ||
| 1698 | &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, | ||
| 1668 | }; | 1699 | }; |
| 1669 | 1700 | ||
| 1670 | /* The following structs hold the fan attributes, some of which are optional. | 1701 | /* The following structs hold the fan attributes, some of which are optional. |
| 1671 | * Their creation depends on the chip configuration which is determined during | 1702 | * Their creation depends on the chip configuration which is determined during |
| 1672 | * module load. */ | 1703 | * module load. */ |
| 1673 | static struct attribute *dme1737_attr_fan1[] = { | 1704 | static struct attribute *dme1737_fan1_attr[] = { |
| 1674 | &sensor_dev_attr_fan1_input.dev_attr.attr, | 1705 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
| 1675 | &sensor_dev_attr_fan1_min.dev_attr.attr, | 1706 | &sensor_dev_attr_fan1_min.dev_attr.attr, |
| 1676 | &sensor_dev_attr_fan1_alarm.dev_attr.attr, | 1707 | &sensor_dev_attr_fan1_alarm.dev_attr.attr, |
| 1677 | &sensor_dev_attr_fan1_type.dev_attr.attr, | 1708 | &sensor_dev_attr_fan1_type.dev_attr.attr, |
| 1678 | NULL | 1709 | NULL |
| 1679 | }; | 1710 | }; |
| 1680 | static struct attribute *dme1737_attr_fan2[] = { | 1711 | static struct attribute *dme1737_fan2_attr[] = { |
| 1681 | &sensor_dev_attr_fan2_input.dev_attr.attr, | 1712 | &sensor_dev_attr_fan2_input.dev_attr.attr, |
| 1682 | &sensor_dev_attr_fan2_min.dev_attr.attr, | 1713 | &sensor_dev_attr_fan2_min.dev_attr.attr, |
| 1683 | &sensor_dev_attr_fan2_alarm.dev_attr.attr, | 1714 | &sensor_dev_attr_fan2_alarm.dev_attr.attr, |
| 1684 | &sensor_dev_attr_fan2_type.dev_attr.attr, | 1715 | &sensor_dev_attr_fan2_type.dev_attr.attr, |
| 1685 | NULL | 1716 | NULL |
| 1686 | }; | 1717 | }; |
| 1687 | static struct attribute *dme1737_attr_fan3[] = { | 1718 | static struct attribute *dme1737_fan3_attr[] = { |
| 1688 | &sensor_dev_attr_fan3_input.dev_attr.attr, | 1719 | &sensor_dev_attr_fan3_input.dev_attr.attr, |
| 1689 | &sensor_dev_attr_fan3_min.dev_attr.attr, | 1720 | &sensor_dev_attr_fan3_min.dev_attr.attr, |
| 1690 | &sensor_dev_attr_fan3_alarm.dev_attr.attr, | 1721 | &sensor_dev_attr_fan3_alarm.dev_attr.attr, |
| 1691 | &sensor_dev_attr_fan3_type.dev_attr.attr, | 1722 | &sensor_dev_attr_fan3_type.dev_attr.attr, |
| 1692 | NULL | 1723 | NULL |
| 1693 | }; | 1724 | }; |
| 1694 | static struct attribute *dme1737_attr_fan4[] = { | 1725 | static struct attribute *dme1737_fan4_attr[] = { |
| 1695 | &sensor_dev_attr_fan4_input.dev_attr.attr, | 1726 | &sensor_dev_attr_fan4_input.dev_attr.attr, |
| 1696 | &sensor_dev_attr_fan4_min.dev_attr.attr, | 1727 | &sensor_dev_attr_fan4_min.dev_attr.attr, |
| 1697 | &sensor_dev_attr_fan4_alarm.dev_attr.attr, | 1728 | &sensor_dev_attr_fan4_alarm.dev_attr.attr, |
| 1698 | &sensor_dev_attr_fan4_type.dev_attr.attr, | 1729 | &sensor_dev_attr_fan4_type.dev_attr.attr, |
| 1699 | NULL | 1730 | NULL |
| 1700 | }; | 1731 | }; |
| 1701 | static struct attribute *dme1737_attr_fan5[] = { | 1732 | static struct attribute *dme1737_fan5_attr[] = { |
| 1702 | &sensor_dev_attr_fan5_input.dev_attr.attr, | 1733 | &sensor_dev_attr_fan5_input.dev_attr.attr, |
| 1703 | &sensor_dev_attr_fan5_min.dev_attr.attr, | 1734 | &sensor_dev_attr_fan5_min.dev_attr.attr, |
| 1704 | &sensor_dev_attr_fan5_alarm.dev_attr.attr, | 1735 | &sensor_dev_attr_fan5_alarm.dev_attr.attr, |
| 1705 | &sensor_dev_attr_fan5_max.dev_attr.attr, | 1736 | &sensor_dev_attr_fan5_max.dev_attr.attr, |
| 1706 | NULL | 1737 | NULL |
| 1707 | }; | 1738 | }; |
| 1708 | static struct attribute *dme1737_attr_fan6[] = { | 1739 | static struct attribute *dme1737_fan6_attr[] = { |
| 1709 | &sensor_dev_attr_fan6_input.dev_attr.attr, | 1740 | &sensor_dev_attr_fan6_input.dev_attr.attr, |
| 1710 | &sensor_dev_attr_fan6_min.dev_attr.attr, | 1741 | &sensor_dev_attr_fan6_min.dev_attr.attr, |
| 1711 | &sensor_dev_attr_fan6_alarm.dev_attr.attr, | 1742 | &sensor_dev_attr_fan6_alarm.dev_attr.attr, |
| @@ -1714,94 +1745,83 @@ static struct attribute *dme1737_attr_fan6[] = { | |||
| 1714 | }; | 1745 | }; |
| 1715 | 1746 | ||
| 1716 | static const struct attribute_group dme1737_fan_group[] = { | 1747 | static const struct attribute_group dme1737_fan_group[] = { |
| 1717 | { .attrs = dme1737_attr_fan1 }, | 1748 | { .attrs = dme1737_fan1_attr }, |
| 1718 | { .attrs = dme1737_attr_fan2 }, | 1749 | { .attrs = dme1737_fan2_attr }, |
| 1719 | { .attrs = dme1737_attr_fan3 }, | 1750 | { .attrs = dme1737_fan3_attr }, |
| 1720 | { .attrs = dme1737_attr_fan4 }, | 1751 | { .attrs = dme1737_fan4_attr }, |
| 1721 | { .attrs = dme1737_attr_fan5 }, | 1752 | { .attrs = dme1737_fan5_attr }, |
| 1722 | { .attrs = dme1737_attr_fan6 }, | 1753 | { .attrs = dme1737_fan6_attr }, |
| 1723 | }; | 1754 | }; |
| 1724 | 1755 | ||
| 1725 | /* The permissions of all of the following attributes are changed to read- | 1756 | /* The permissions of the following zone attributes are changed to read- |
| 1726 | * writeable if the chip is *not* locked. Otherwise they stay read-only. */ | 1757 | * writeable if the chip is *not* locked. Otherwise they stay read-only. */ |
| 1727 | static struct attribute *dme1737_attr_lock[] = { | 1758 | static struct attribute *dme1737_zone_chmod_attr[] = { |
| 1728 | /* Temperatures */ | ||
| 1729 | &sensor_dev_attr_temp1_offset.dev_attr.attr, | ||
| 1730 | &sensor_dev_attr_temp2_offset.dev_attr.attr, | ||
| 1731 | &sensor_dev_attr_temp3_offset.dev_attr.attr, | ||
| 1732 | /* Zones */ | ||
| 1733 | &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1734 | &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, | 1759 | &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, |
| 1735 | &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, | 1760 | &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, |
| 1736 | &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, | 1761 | &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, |
| 1737 | &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1738 | &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, | 1762 | &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, |
| 1739 | &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, | 1763 | &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, |
| 1740 | &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, | 1764 | &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, |
| 1741 | &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, | ||
| 1742 | &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, | 1765 | &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, |
| 1743 | &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, | 1766 | &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, |
| 1744 | &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, | 1767 | &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, |
| 1745 | NULL | 1768 | NULL |
| 1746 | }; | 1769 | }; |
| 1747 | 1770 | ||
| 1748 | static const struct attribute_group dme1737_lock_group = { | 1771 | static const struct attribute_group dme1737_zone_chmod_group = { |
| 1749 | .attrs = dme1737_attr_lock, | 1772 | .attrs = dme1737_zone_chmod_attr, |
| 1750 | }; | 1773 | }; |
| 1751 | 1774 | ||
| 1752 | /* The permissions of the following PWM attributes are changed to read- | 1775 | /* The permissions of the following PWM attributes are changed to read- |
| 1753 | * writeable if the chip is *not* locked and the respective PWM is available. | 1776 | * writeable if the chip is *not* locked and the respective PWM is available. |
| 1754 | * Otherwise they stay read-only. */ | 1777 | * Otherwise they stay read-only. */ |
| 1755 | static struct attribute *dme1737_attr_pwm1_lock[] = { | 1778 | static struct attribute *dme1737_pwm1_chmod_attr[] = { |
| 1756 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, | 1779 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, |
| 1757 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, | 1780 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, |
| 1758 | &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, | 1781 | &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, |
| 1759 | &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, | 1782 | &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, |
| 1760 | &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, | ||
| 1761 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, | 1783 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, |
| 1762 | NULL | 1784 | NULL |
| 1763 | }; | 1785 | }; |
| 1764 | static struct attribute *dme1737_attr_pwm2_lock[] = { | 1786 | static struct attribute *dme1737_pwm2_chmod_attr[] = { |
| 1765 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, | 1787 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, |
| 1766 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, | 1788 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, |
| 1767 | &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, | 1789 | &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, |
| 1768 | &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, | 1790 | &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, |
| 1769 | &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, | ||
| 1770 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, | 1791 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, |
| 1771 | NULL | 1792 | NULL |
| 1772 | }; | 1793 | }; |
| 1773 | static struct attribute *dme1737_attr_pwm3_lock[] = { | 1794 | static struct attribute *dme1737_pwm3_chmod_attr[] = { |
| 1774 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, | 1795 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, |
| 1775 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, | 1796 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, |
| 1776 | &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, | 1797 | &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, |
| 1777 | &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, | 1798 | &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, |
| 1778 | &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, | ||
| 1779 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, | 1799 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, |
| 1780 | NULL | 1800 | NULL |
| 1781 | }; | 1801 | }; |
| 1782 | static struct attribute *dme1737_attr_pwm5_lock[] = { | 1802 | static struct attribute *dme1737_pwm5_chmod_attr[] = { |
| 1783 | &sensor_dev_attr_pwm5.dev_attr.attr, | 1803 | &sensor_dev_attr_pwm5.dev_attr.attr, |
| 1784 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, | 1804 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, |
| 1785 | NULL | 1805 | NULL |
| 1786 | }; | 1806 | }; |
| 1787 | static struct attribute *dme1737_attr_pwm6_lock[] = { | 1807 | static struct attribute *dme1737_pwm6_chmod_attr[] = { |
| 1788 | &sensor_dev_attr_pwm6.dev_attr.attr, | 1808 | &sensor_dev_attr_pwm6.dev_attr.attr, |
| 1789 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, | 1809 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, |
| 1790 | NULL | 1810 | NULL |
| 1791 | }; | 1811 | }; |
| 1792 | 1812 | ||
| 1793 | static const struct attribute_group dme1737_pwm_lock_group[] = { | 1813 | static const struct attribute_group dme1737_pwm_chmod_group[] = { |
| 1794 | { .attrs = dme1737_attr_pwm1_lock }, | 1814 | { .attrs = dme1737_pwm1_chmod_attr }, |
| 1795 | { .attrs = dme1737_attr_pwm2_lock }, | 1815 | { .attrs = dme1737_pwm2_chmod_attr }, |
| 1796 | { .attrs = dme1737_attr_pwm3_lock }, | 1816 | { .attrs = dme1737_pwm3_chmod_attr }, |
| 1797 | { .attrs = NULL }, | 1817 | { .attrs = NULL }, |
| 1798 | { .attrs = dme1737_attr_pwm5_lock }, | 1818 | { .attrs = dme1737_pwm5_chmod_attr }, |
| 1799 | { .attrs = dme1737_attr_pwm6_lock }, | 1819 | { .attrs = dme1737_pwm6_chmod_attr }, |
| 1800 | }; | 1820 | }; |
| 1801 | 1821 | ||
| 1802 | /* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the | 1822 | /* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the |
| 1803 | * chip is not locked. Otherwise they are read-only. */ | 1823 | * chip is not locked. Otherwise they are read-only. */ |
| 1804 | static struct attribute *dme1737_attr_pwm[] = { | 1824 | static struct attribute *dme1737_pwm_chmod_attr[] = { |
| 1805 | &sensor_dev_attr_pwm1.dev_attr.attr, | 1825 | &sensor_dev_attr_pwm1.dev_attr.attr, |
| 1806 | &sensor_dev_attr_pwm2.dev_attr.attr, | 1826 | &sensor_dev_attr_pwm2.dev_attr.attr, |
| 1807 | &sensor_dev_attr_pwm3.dev_attr.attr, | 1827 | &sensor_dev_attr_pwm3.dev_attr.attr, |
| @@ -1875,9 +1895,17 @@ static void dme1737_remove_files(struct device *dev) | |||
| 1875 | if (data->has_pwm & (1 << ix)) { | 1895 | if (data->has_pwm & (1 << ix)) { |
| 1876 | sysfs_remove_group(&dev->kobj, | 1896 | sysfs_remove_group(&dev->kobj, |
| 1877 | &dme1737_pwm_group[ix]); | 1897 | &dme1737_pwm_group[ix]); |
| 1898 | if (data->type != sch5027 && ix < 3) { | ||
| 1899 | sysfs_remove_file(&dev->kobj, | ||
| 1900 | dme1737_pwm_misc_attr[ix]); | ||
| 1901 | } | ||
| 1878 | } | 1902 | } |
| 1879 | } | 1903 | } |
| 1880 | 1904 | ||
| 1905 | if (data->type != sch5027) { | ||
| 1906 | sysfs_remove_group(&dev->kobj, &dme1737_misc_group); | ||
| 1907 | } | ||
| 1908 | |||
| 1881 | sysfs_remove_group(&dev->kobj, &dme1737_group); | 1909 | sysfs_remove_group(&dev->kobj, &dme1737_group); |
| 1882 | 1910 | ||
| 1883 | if (!data->client.driver) { | 1911 | if (!data->client.driver) { |
| @@ -1901,6 +1929,13 @@ static int dme1737_create_files(struct device *dev) | |||
| 1901 | goto exit_remove; | 1929 | goto exit_remove; |
| 1902 | } | 1930 | } |
| 1903 | 1931 | ||
| 1932 | /* Create misc sysfs attributes */ | ||
| 1933 | if ((data->type != sch5027) && | ||
| 1934 | (err = sysfs_create_group(&dev->kobj, | ||
| 1935 | &dme1737_misc_group))) { | ||
| 1936 | goto exit_remove; | ||
| 1937 | } | ||
| 1938 | |||
| 1904 | /* Create fan sysfs attributes */ | 1939 | /* Create fan sysfs attributes */ |
| 1905 | for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { | 1940 | for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { |
| 1906 | if (data->has_fan & (1 << ix)) { | 1941 | if (data->has_fan & (1 << ix)) { |
| @@ -1918,6 +1953,11 @@ static int dme1737_create_files(struct device *dev) | |||
| 1918 | &dme1737_pwm_group[ix]))) { | 1953 | &dme1737_pwm_group[ix]))) { |
| 1919 | goto exit_remove; | 1954 | goto exit_remove; |
| 1920 | } | 1955 | } |
| 1956 | if (data->type != sch5027 && ix < 3 && | ||
| 1957 | (err = sysfs_create_file(&dev->kobj, | ||
| 1958 | dme1737_pwm_misc_attr[ix]))) { | ||
| 1959 | goto exit_remove; | ||
| 1960 | } | ||
| 1921 | } | 1961 | } |
| 1922 | } | 1962 | } |
| 1923 | 1963 | ||
| @@ -1927,16 +1967,27 @@ static int dme1737_create_files(struct device *dev) | |||
| 1927 | dev_info(dev, "Device is locked. Some attributes " | 1967 | dev_info(dev, "Device is locked. Some attributes " |
| 1928 | "will be read-only.\n"); | 1968 | "will be read-only.\n"); |
| 1929 | } else { | 1969 | } else { |
| 1930 | /* Change permissions of standard attributes */ | 1970 | /* Change permissions of zone sysfs attributes */ |
| 1931 | dme1737_chmod_group(dev, &dme1737_lock_group, | 1971 | dme1737_chmod_group(dev, &dme1737_zone_chmod_group, |
| 1932 | S_IRUGO | S_IWUSR); | 1972 | S_IRUGO | S_IWUSR); |
| 1933 | 1973 | ||
| 1934 | /* Change permissions of PWM attributes */ | 1974 | /* Change permissions of misc sysfs attributes */ |
| 1935 | for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_lock_group); ix++) { | 1975 | if (data->type != sch5027) { |
| 1976 | dme1737_chmod_group(dev, &dme1737_misc_group, | ||
| 1977 | S_IRUGO | S_IWUSR); | ||
| 1978 | } | ||
| 1979 | |||
| 1980 | /* Change permissions of PWM sysfs attributes */ | ||
| 1981 | for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { | ||
| 1936 | if (data->has_pwm & (1 << ix)) { | 1982 | if (data->has_pwm & (1 << ix)) { |
| 1937 | dme1737_chmod_group(dev, | 1983 | dme1737_chmod_group(dev, |
| 1938 | &dme1737_pwm_lock_group[ix], | 1984 | &dme1737_pwm_chmod_group[ix], |
| 1985 | S_IRUGO | S_IWUSR); | ||
| 1986 | if (data->type != sch5027 && ix < 3) { | ||
| 1987 | dme1737_chmod_file(dev, | ||
| 1988 | dme1737_pwm_misc_attr[ix], | ||
| 1939 | S_IRUGO | S_IWUSR); | 1989 | S_IRUGO | S_IWUSR); |
| 1990 | } | ||
| 1940 | } | 1991 | } |
| 1941 | } | 1992 | } |
| 1942 | 1993 | ||
| @@ -1945,7 +1996,7 @@ static int dme1737_create_files(struct device *dev) | |||
| 1945 | if ((data->has_pwm & (1 << ix)) && | 1996 | if ((data->has_pwm & (1 << ix)) && |
| 1946 | (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { | 1997 | (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { |
| 1947 | dme1737_chmod_file(dev, | 1998 | dme1737_chmod_file(dev, |
| 1948 | dme1737_attr_pwm[ix], | 1999 | dme1737_pwm_chmod_attr[ix], |
| 1949 | S_IRUGO | S_IWUSR); | 2000 | S_IRUGO | S_IWUSR); |
| 1950 | } | 2001 | } |
| 1951 | } | 2002 | } |
| @@ -1966,6 +2017,9 @@ static int dme1737_init_device(struct device *dev) | |||
| 1966 | int ix; | 2017 | int ix; |
| 1967 | u8 reg; | 2018 | u8 reg; |
| 1968 | 2019 | ||
| 2020 | /* Point to the right nominal voltages array */ | ||
| 2021 | data->in_nominal = IN_NOMINAL(data->type); | ||
| 2022 | |||
| 1969 | data->config = dme1737_read(client, DME1737_REG_CONFIG); | 2023 | data->config = dme1737_read(client, DME1737_REG_CONFIG); |
| 1970 | /* Inform if part is not monitoring/started */ | 2024 | /* Inform if part is not monitoring/started */ |
| 1971 | if (!(data->config & 0x01)) { | 2025 | if (!(data->config & 0x01)) { |
| @@ -2076,7 +2130,9 @@ static int dme1737_init_device(struct device *dev) | |||
| 2076 | data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ | 2130 | data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ |
| 2077 | 2131 | ||
| 2078 | /* Set VRM */ | 2132 | /* Set VRM */ |
| 2079 | data->vrm = vid_which_vrm(); | 2133 | if (data->type != sch5027) { |
| 2134 | data->vrm = vid_which_vrm(); | ||
| 2135 | } | ||
| 2080 | 2136 | ||
| 2081 | return 0; | 2137 | return 0; |
| 2082 | } | 2138 | } |
| @@ -2095,9 +2151,10 @@ static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) | |||
| 2095 | dme1737_sio_enter(sio_cip); | 2151 | dme1737_sio_enter(sio_cip); |
| 2096 | 2152 | ||
| 2097 | /* Check device ID | 2153 | /* Check device ID |
| 2098 | * The DME1737 can return either 0x78 or 0x77 as its device ID. */ | 2154 | * The DME1737 can return either 0x78 or 0x77 as its device ID. |
| 2155 | * The SCH5027 returns 0x89 as its device ID. */ | ||
| 2099 | reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); | 2156 | reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); |
| 2100 | if (!(reg == 0x77 || reg == 0x78)) { | 2157 | if (!(reg == 0x77 || reg == 0x78 || reg == 0x89)) { |
| 2101 | err = -ENODEV; | 2158 | err = -ENODEV; |
| 2102 | goto exit; | 2159 | goto exit; |
| 2103 | } | 2160 | } |
| @@ -2166,15 +2223,24 @@ static int dme1737_i2c_detect(struct i2c_adapter *adapter, int address, | |||
| 2166 | company = dme1737_read(client, DME1737_REG_COMPANY); | 2223 | company = dme1737_read(client, DME1737_REG_COMPANY); |
| 2167 | verstep = dme1737_read(client, DME1737_REG_VERSTEP); | 2224 | verstep = dme1737_read(client, DME1737_REG_VERSTEP); |
| 2168 | 2225 | ||
| 2169 | if (!((company == DME1737_COMPANY_SMSC) && | 2226 | if (company == DME1737_COMPANY_SMSC && |
| 2170 | ((verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP))) { | 2227 | (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { |
| 2228 | kind = dme1737; | ||
| 2229 | } else if (company == DME1737_COMPANY_SMSC && | ||
| 2230 | verstep == SCH5027_VERSTEP) { | ||
| 2231 | kind = sch5027; | ||
| 2232 | } else { | ||
| 2171 | err = -ENODEV; | 2233 | err = -ENODEV; |
| 2172 | goto exit_kfree; | 2234 | goto exit_kfree; |
| 2173 | } | 2235 | } |
| 2174 | } | 2236 | } |
| 2175 | 2237 | ||
| 2176 | kind = dme1737; | 2238 | if (kind == sch5027) { |
| 2177 | name = "dme1737"; | 2239 | name = "sch5027"; |
| 2240 | } else { | ||
| 2241 | kind = dme1737; | ||
| 2242 | name = "dme1737"; | ||
| 2243 | } | ||
| 2178 | data->type = kind; | 2244 | data->type = kind; |
| 2179 | 2245 | ||
| 2180 | /* Fill in the remaining client fields and put it into the global | 2246 | /* Fill in the remaining client fields and put it into the global |
| @@ -2187,8 +2253,9 @@ static int dme1737_i2c_detect(struct i2c_adapter *adapter, int address, | |||
| 2187 | goto exit_kfree; | 2253 | goto exit_kfree; |
| 2188 | } | 2254 | } |
| 2189 | 2255 | ||
| 2190 | dev_info(dev, "Found a DME1737 chip at 0x%02x (rev 0x%02x).\n", | 2256 | dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", |
| 2191 | client->addr, verstep); | 2257 | kind == sch5027 ? "SCH5027" : "DME1737", client->addr, |
| 2258 | verstep); | ||
| 2192 | 2259 | ||
| 2193 | /* Initialize the DME1737 chip */ | 2260 | /* Initialize the DME1737 chip */ |
| 2194 | if ((err = dme1737_init_device(dev))) { | 2261 | if ((err = dme1737_init_device(dev))) { |
| @@ -2360,15 +2427,18 @@ static int __devinit dme1737_isa_probe(struct platform_device *pdev) | |||
| 2360 | client->addr = res->start; | 2427 | client->addr = res->start; |
| 2361 | platform_set_drvdata(pdev, data); | 2428 | platform_set_drvdata(pdev, data); |
| 2362 | 2429 | ||
| 2363 | company = dme1737_read(client, DME1737_REG_COMPANY); | 2430 | /* Skip chip detection if module is loaded with force_id parameter */ |
| 2364 | device = dme1737_read(client, DME1737_REG_DEVICE); | 2431 | if (!force_id) { |
| 2432 | company = dme1737_read(client, DME1737_REG_COMPANY); | ||
| 2433 | device = dme1737_read(client, DME1737_REG_DEVICE); | ||
| 2365 | 2434 | ||
| 2366 | if (!((company == DME1737_COMPANY_SMSC) && | 2435 | if (!((company == DME1737_COMPANY_SMSC) && |
| 2367 | (device == SCH311X_DEVICE))) { | 2436 | (device == SCH311X_DEVICE))) { |
| 2368 | err = -ENODEV; | 2437 | err = -ENODEV; |
| 2369 | goto exit_kfree; | 2438 | goto exit_kfree; |
| 2439 | } | ||
| 2370 | } | 2440 | } |
| 2371 | data->type = -1; | 2441 | data->type = sch311x; |
| 2372 | 2442 | ||
| 2373 | /* Fill in the remaining client fields and initialize the mutex */ | 2443 | /* Fill in the remaining client fields and initialize the mutex */ |
| 2374 | strlcpy(client->name, "sch311x", I2C_NAME_SIZE); | 2444 | strlcpy(client->name, "sch311x", I2C_NAME_SIZE); |
diff --git a/drivers/hwmon/f71882fg.c b/drivers/hwmon/f71882fg.c index cbeb4984b5c7..67067e9a323e 100644 --- a/drivers/hwmon/f71882fg.c +++ b/drivers/hwmon/f71882fg.c | |||
| @@ -87,8 +87,6 @@ static inline void superio_enter(int base); | |||
| 87 | static inline void superio_select(int base, int ld); | 87 | static inline void superio_select(int base, int ld); |
| 88 | static inline void superio_exit(int base); | 88 | static inline void superio_exit(int base); |
| 89 | 89 | ||
| 90 | static inline u16 fan_from_reg ( u16 reg ); | ||
| 91 | |||
| 92 | struct f71882fg_data { | 90 | struct f71882fg_data { |
| 93 | unsigned short addr; | 91 | unsigned short addr; |
| 94 | struct device *hwmon_dev; | 92 | struct device *hwmon_dev; |
| @@ -116,10 +114,6 @@ struct f71882fg_data { | |||
| 116 | u8 temp_diode_open; | 114 | u8 temp_diode_open; |
| 117 | }; | 115 | }; |
| 118 | 116 | ||
| 119 | static u8 f71882fg_read8(struct f71882fg_data *data, u8 reg); | ||
| 120 | static u16 f71882fg_read16(struct f71882fg_data *data, u8 reg); | ||
| 121 | static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val); | ||
| 122 | |||
| 123 | /* Sysfs in*/ | 117 | /* Sysfs in*/ |
| 124 | static ssize_t show_in(struct device *dev, struct device_attribute *devattr, | 118 | static ssize_t show_in(struct device *dev, struct device_attribute *devattr, |
| 125 | char *buf); | 119 | char *buf); |
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c index 3330667280b9..7b0a32c4dcfb 100644 --- a/drivers/hwmon/hwmon-vid.c +++ b/drivers/hwmon/hwmon-vid.c | |||
| @@ -1,76 +1,74 @@ | |||
| 1 | /* | 1 | /* |
| 2 | hwmon-vid.c - VID/VRM/VRD voltage conversions | 2 | * hwmon-vid.c - VID/VRM/VRD voltage conversions |
| 3 | 3 | * | |
| 4 | Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz> | 4 | * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz> |
| 5 | 5 | * | |
| 6 | Partly imported from i2c-vid.h of the lm_sensors project | 6 | * Partly imported from i2c-vid.h of the lm_sensors project |
| 7 | Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com> | 7 | * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com> |
| 8 | With assistance from Trent Piepho <xyzzy@speakeasy.org> | 8 | * With assistance from Trent Piepho <xyzzy@speakeasy.org> |
| 9 | 9 | * | |
| 10 | This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by | 11 | * it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 2 of the License, or | 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | 14 | * | |
| 15 | This program is distributed in the hope that it will be useful, | 15 | * This program is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. | 18 | * GNU General Public License for more details. |
| 19 | 19 | * | |
| 20 | You should have received a copy of the GNU General Public License | 20 | * You should have received a copy of the GNU General Public License |
| 21 | along with this program; if not, write to the Free Software | 21 | * along with this program; if not, write to the Free Software |
| 22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | 22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <linux/module.h> | 25 | #include <linux/module.h> |
| 26 | #include <linux/kernel.h> | 26 | #include <linux/kernel.h> |
| 27 | #include <linux/hwmon-vid.h> | 27 | #include <linux/hwmon-vid.h> |
| 28 | 28 | ||
| 29 | /* | 29 | /* |
| 30 | Common code for decoding VID pins. | 30 | * Common code for decoding VID pins. |
| 31 | 31 | * | |
| 32 | References: | 32 | * References: |
| 33 | 33 | * | |
| 34 | For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines", | 34 | * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines", |
| 35 | available at http://developer.intel.com/. | 35 | * available at http://developer.intel.com/. |
| 36 | 36 | * | |
| 37 | For VRD 10.0 and up, "VRD x.y Design Guide", | 37 | * For VRD 10.0 and up, "VRD x.y Design Guide", |
| 38 | available at http://developer.intel.com/. | 38 | * available at http://developer.intel.com/. |
| 39 | 39 | * | |
| 40 | AMD Opteron processors don't follow the Intel specifications. | 40 | * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559, |
| 41 | I'm going to "make up" 2.4 as the spec number for the Opterons. | 41 | * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf |
| 42 | No good reason just a mnemonic for the 24x Opteron processor | 42 | * Table 71. VID Code Voltages |
| 43 | series. | 43 | * AMD Opteron processors don't follow the Intel specifications. |
| 44 | 44 | * I'm going to "make up" 2.4 as the spec number for the Opterons. | |
| 45 | Opteron VID encoding is: | 45 | * No good reason just a mnemonic for the 24x Opteron processor |
| 46 | 00000 = 1.550 V | 46 | * series. |
| 47 | 00001 = 1.525 V | 47 | * |
| 48 | . . . . | 48 | * The 17 specification is in fact Intel Mobile Voltage Positioning - |
| 49 | 11110 = 0.800 V | 49 | * (IMVP-II). You can find more information in the datasheet of Max1718 |
| 50 | 11111 = 0.000 V (off) | 50 | * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452 |
| 51 | 51 | * | |
| 52 | The 17 specification is in fact Intel Mobile Voltage Positioning - | 52 | * The 13 specification corresponds to the Intel Pentium M series. There |
| 53 | (IMVP-II). You can find more information in the datasheet of Max1718 | 53 | * doesn't seem to be any named specification for these. The conversion |
| 54 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452 | 54 | * tables are detailed directly in the various Pentium M datasheets: |
| 55 | 55 | * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm | |
| 56 | The 13 specification corresponds to the Intel Pentium M series. There | 56 | * |
| 57 | doesn't seem to be any named specification for these. The conversion | 57 | * The 14 specification corresponds to Intel Core series. There |
| 58 | tables are detailed directly in the various Pentium M datasheets: | 58 | * doesn't seem to be any named specification for these. The conversion |
| 59 | http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm | 59 | * tables are detailed directly in the various Pentium Core datasheets: |
| 60 | 60 | * http://www.intel.com/design/mobile/datashts/309221.htm | |
| 61 | The 14 specification corresponds to Intel Core series. There | 61 | * |
| 62 | doesn't seem to be any named specification for these. The conversion | 62 | * The 110 (VRM 11) specification corresponds to Intel Conroe based series. |
| 63 | tables are detailed directly in the various Pentium Core datasheets: | 63 | * http://www.intel.com/design/processor/applnots/313214.htm |
| 64 | http://www.intel.com/design/mobile/datashts/309221.htm | 64 | */ |
| 65 | 65 | ||
| 66 | The 110 (VRM 11) specification corresponds to Intel Conroe based series. | 66 | /* |
| 67 | http://www.intel.com/design/processor/applnots/313214.htm | 67 | * vrm is the VRM/VRD document version multiplied by 10. |
| 68 | */ | 68 | * val is the 4-bit or more VID code. |
| 69 | 69 | * Returned value is in mV to avoid floating point in the kernel. | |
| 70 | /* vrm is the VRM/VRD document version multiplied by 10. | 70 | * Some VID have some bits in uV scale, this is rounded to mV. |
| 71 | val is the 4-bit or more VID code. | 71 | */ |
| 72 | Returned value is in mV to avoid floating point in the kernel. | ||
| 73 | Some VID have some bits in uV scale, this is rounded to mV */ | ||
| 74 | int vid_from_reg(int val, u8 vrm) | 72 | int vid_from_reg(int val, u8 vrm) |
| 75 | { | 73 | { |
| 76 | int vid; | 74 | int vid; |
| @@ -96,9 +94,11 @@ int vid_from_reg(int val, u8 vrm) | |||
| 96 | if (val < 0x02 || val > 0xb2) | 94 | if (val < 0x02 || val > 0xb2) |
| 97 | return 0; | 95 | return 0; |
| 98 | return((1600000 - (val - 2) * 6250 + 500) / 1000); | 96 | return((1600000 - (val - 2) * 6250 + 500) / 1000); |
| 99 | case 24: /* Opteron processor */ | 97 | |
| 100 | val &= 0x1f; | 98 | case 24: /* AMD NPT 0Fh (Athlon64 & Opteron) */ |
| 101 | return(val == 0x1f ? 0 : 1550 - val * 25); | 99 | val &= 0x3f; |
| 100 | return (val < 32) ? 1550 - 25 * val | ||
| 101 | : 775 - (25 * (val - 31)) / 2; | ||
| 102 | 102 | ||
| 103 | case 91: /* VRM 9.1 */ | 103 | case 91: /* VRM 9.1 */ |
| 104 | case 90: /* VRM 9.0 */ | 104 | case 90: /* VRM 9.0 */ |
| @@ -141,9 +141,9 @@ int vid_from_reg(int val, u8 vrm) | |||
| 141 | 141 | ||
| 142 | 142 | ||
| 143 | /* | 143 | /* |
| 144 | After this point is the code to automatically determine which | 144 | * After this point is the code to automatically determine which |
| 145 | VRM/VRD specification should be used depending on the CPU. | 145 | * VRM/VRD specification should be used depending on the CPU. |
| 146 | */ | 146 | */ |
| 147 | 147 | ||
| 148 | struct vrm_model { | 148 | struct vrm_model { |
| 149 | u8 vendor; | 149 | u8 vendor; |
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index e12c132ff83a..30cdb0956779 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c | |||
| @@ -151,9 +151,9 @@ static int fix_pwm_polarity; | |||
| 151 | /* The IT8718F has the VID value in a different register, in Super-I/O | 151 | /* The IT8718F has the VID value in a different register, in Super-I/O |
| 152 | configuration space. */ | 152 | configuration space. */ |
| 153 | #define IT87_REG_VID 0x0a | 153 | #define IT87_REG_VID 0x0a |
| 154 | /* Warning: register 0x0b is used for something completely different in | 154 | /* The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b |
| 155 | new chips/revisions. I suspect only 16-bit tachometer mode will work | 155 | for fan divisors. Later IT8712F revisions must use 16-bit tachometer |
| 156 | for these. */ | 156 | mode. */ |
| 157 | #define IT87_REG_FAN_DIV 0x0b | 157 | #define IT87_REG_FAN_DIV 0x0b |
| 158 | #define IT87_REG_FAN_16BIT 0x0c | 158 | #define IT87_REG_FAN_16BIT 0x0c |
| 159 | 159 | ||
| @@ -234,6 +234,7 @@ static const unsigned int pwm_freq[8] = { | |||
| 234 | struct it87_sio_data { | 234 | struct it87_sio_data { |
| 235 | enum chips type; | 235 | enum chips type; |
| 236 | /* Values read from Super-I/O config space */ | 236 | /* Values read from Super-I/O config space */ |
| 237 | u8 revision; | ||
| 237 | u8 vid_value; | 238 | u8 vid_value; |
| 238 | }; | 239 | }; |
| 239 | 240 | ||
| @@ -242,6 +243,7 @@ struct it87_sio_data { | |||
| 242 | struct it87_data { | 243 | struct it87_data { |
| 243 | struct device *hwmon_dev; | 244 | struct device *hwmon_dev; |
| 244 | enum chips type; | 245 | enum chips type; |
| 246 | u8 revision; | ||
| 245 | 247 | ||
| 246 | unsigned short addr; | 248 | unsigned short addr; |
| 247 | const char *name; | 249 | const char *name; |
| @@ -268,6 +270,16 @@ struct it87_data { | |||
| 268 | u8 manual_pwm_ctl[3]; /* manual PWM value set by user */ | 270 | u8 manual_pwm_ctl[3]; /* manual PWM value set by user */ |
| 269 | }; | 271 | }; |
| 270 | 272 | ||
| 273 | static inline int has_16bit_fans(const struct it87_data *data) | ||
| 274 | { | ||
| 275 | /* IT8705F Datasheet 0.4.1, 3h == Version G. | ||
| 276 | IT8712F Datasheet 0.9.1, section 8.3.5 indicates 7h == Version I. | ||
| 277 | These are the first revisions with 16bit tachometer support. */ | ||
| 278 | return (data->type == it87 && data->revision >= 0x03) | ||
| 279 | || (data->type == it8712 && data->revision >= 0x07) | ||
| 280 | || data->type == it8716 | ||
| 281 | || data->type == it8718; | ||
| 282 | } | ||
| 271 | 283 | ||
| 272 | static int it87_probe(struct platform_device *pdev); | 284 | static int it87_probe(struct platform_device *pdev); |
| 273 | static int __devexit it87_remove(struct platform_device *pdev); | 285 | static int __devexit it87_remove(struct platform_device *pdev); |
| @@ -991,8 +1003,9 @@ static int __init it87_find(unsigned short *address, | |||
| 991 | } | 1003 | } |
| 992 | 1004 | ||
| 993 | err = 0; | 1005 | err = 0; |
| 1006 | sio_data->revision = superio_inb(DEVREV) & 0x0f; | ||
| 994 | pr_info("it87: Found IT%04xF chip at 0x%x, revision %d\n", | 1007 | pr_info("it87: Found IT%04xF chip at 0x%x, revision %d\n", |
| 995 | chip_type, *address, superio_inb(DEVREV) & 0x0f); | 1008 | chip_type, *address, sio_data->revision); |
| 996 | 1009 | ||
| 997 | /* Read GPIO config and VID value from LDN 7 (GPIO) */ | 1010 | /* Read GPIO config and VID value from LDN 7 (GPIO) */ |
| 998 | if (chip_type != IT8705F_DEVID) { | 1011 | if (chip_type != IT8705F_DEVID) { |
| @@ -1045,6 +1058,7 @@ static int __devinit it87_probe(struct platform_device *pdev) | |||
| 1045 | 1058 | ||
| 1046 | data->addr = res->start; | 1059 | data->addr = res->start; |
| 1047 | data->type = sio_data->type; | 1060 | data->type = sio_data->type; |
| 1061 | data->revision = sio_data->revision; | ||
| 1048 | data->name = names[sio_data->type]; | 1062 | data->name = names[sio_data->type]; |
| 1049 | 1063 | ||
| 1050 | /* Now, we do the remaining detection. */ | 1064 | /* Now, we do the remaining detection. */ |
| @@ -1069,7 +1083,7 @@ static int __devinit it87_probe(struct platform_device *pdev) | |||
| 1069 | goto ERROR2; | 1083 | goto ERROR2; |
| 1070 | 1084 | ||
| 1071 | /* Do not create fan files for disabled fans */ | 1085 | /* Do not create fan files for disabled fans */ |
| 1072 | if (data->type == it8716 || data->type == it8718) { | 1086 | if (has_16bit_fans(data)) { |
| 1073 | /* 16-bit tachometers */ | 1087 | /* 16-bit tachometers */ |
| 1074 | if (data->has_fan & (1 << 0)) { | 1088 | if (data->has_fan & (1 << 0)) { |
| 1075 | if ((err = device_create_file(dev, | 1089 | if ((err = device_create_file(dev, |
| @@ -1350,7 +1364,7 @@ static void __devinit it87_init_device(struct platform_device *pdev) | |||
| 1350 | data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; | 1364 | data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; |
| 1351 | 1365 | ||
| 1352 | /* Set tachometers to 16-bit mode if needed */ | 1366 | /* Set tachometers to 16-bit mode if needed */ |
| 1353 | if (data->type == it8716 || data->type == it8718) { | 1367 | if (has_16bit_fans(data)) { |
| 1354 | tmp = it87_read_value(data, IT87_REG_FAN_16BIT); | 1368 | tmp = it87_read_value(data, IT87_REG_FAN_16BIT); |
| 1355 | if (~tmp & 0x07 & data->has_fan) { | 1369 | if (~tmp & 0x07 & data->has_fan) { |
| 1356 | dev_dbg(&pdev->dev, | 1370 | dev_dbg(&pdev->dev, |
| @@ -1358,10 +1372,13 @@ static void __devinit it87_init_device(struct platform_device *pdev) | |||
| 1358 | it87_write_value(data, IT87_REG_FAN_16BIT, | 1372 | it87_write_value(data, IT87_REG_FAN_16BIT, |
| 1359 | tmp | 0x07); | 1373 | tmp | 0x07); |
| 1360 | } | 1374 | } |
| 1361 | if (tmp & (1 << 4)) | 1375 | /* IT8705F only supports three fans. */ |
| 1362 | data->has_fan |= (1 << 3); /* fan4 enabled */ | 1376 | if (data->type != it87) { |
| 1363 | if (tmp & (1 << 5)) | 1377 | if (tmp & (1 << 4)) |
| 1364 | data->has_fan |= (1 << 4); /* fan5 enabled */ | 1378 | data->has_fan |= (1 << 3); /* fan4 enabled */ |
| 1379 | if (tmp & (1 << 5)) | ||
| 1380 | data->has_fan |= (1 << 4); /* fan5 enabled */ | ||
| 1381 | } | ||
| 1365 | } | 1382 | } |
| 1366 | 1383 | ||
| 1367 | /* Set current fan mode registers and the default settings for the | 1384 | /* Set current fan mode registers and the default settings for the |
| @@ -1426,7 +1443,7 @@ static struct it87_data *it87_update_device(struct device *dev) | |||
| 1426 | data->fan[i] = it87_read_value(data, | 1443 | data->fan[i] = it87_read_value(data, |
| 1427 | IT87_REG_FAN[i]); | 1444 | IT87_REG_FAN[i]); |
| 1428 | /* Add high byte if in 16-bit mode */ | 1445 | /* Add high byte if in 16-bit mode */ |
| 1429 | if (data->type == it8716 || data->type == it8718) { | 1446 | if (has_16bit_fans(data)) { |
| 1430 | data->fan[i] |= it87_read_value(data, | 1447 | data->fan[i] |= it87_read_value(data, |
| 1431 | IT87_REG_FANX[i]) << 8; | 1448 | IT87_REG_FANX[i]) << 8; |
| 1432 | data->fan_min[i] |= it87_read_value(data, | 1449 | data->fan_min[i] |= it87_read_value(data, |
| @@ -1443,8 +1460,7 @@ static struct it87_data *it87_update_device(struct device *dev) | |||
| 1443 | } | 1460 | } |
| 1444 | 1461 | ||
| 1445 | /* Newer chips don't have clock dividers */ | 1462 | /* Newer chips don't have clock dividers */ |
| 1446 | if ((data->has_fan & 0x07) && data->type != it8716 | 1463 | if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { |
| 1447 | && data->type != it8718) { | ||
| 1448 | i = it87_read_value(data, IT87_REG_FAN_DIV); | 1464 | i = it87_read_value(data, IT87_REG_FAN_DIV); |
| 1449 | data->fan_div[0] = i & 0x07; | 1465 | data->fan_div[0] = i & 0x07; |
| 1450 | data->fan_div[1] = (i >> 3) & 0x07; | 1466 | data->fan_div[1] = (i >> 3) & 0x07; |
| @@ -1460,7 +1476,8 @@ static struct it87_data *it87_update_device(struct device *dev) | |||
| 1460 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); | 1476 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); |
| 1461 | 1477 | ||
| 1462 | data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); | 1478 | data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); |
| 1463 | /* The 8705 does not have VID capability */ | 1479 | /* The 8705 does not have VID capability. |
| 1480 | The 8718 does not use IT87_REG_VID for the same purpose. */ | ||
| 1464 | if (data->type == it8712 || data->type == it8716) { | 1481 | if (data->type == it8712 || data->type == it8716) { |
| 1465 | data->vid = it87_read_value(data, IT87_REG_VID); | 1482 | data->vid = it87_read_value(data, IT87_REG_VID); |
| 1466 | /* The older IT8712F revisions had only 5 VID pins, | 1483 | /* The older IT8712F revisions had only 5 VID pins, |
diff --git a/drivers/hwmon/thmc50.c b/drivers/hwmon/thmc50.c index 3b01001108c1..7d97431e132f 100644 --- a/drivers/hwmon/thmc50.c +++ b/drivers/hwmon/thmc50.c | |||
| @@ -55,8 +55,11 @@ I2C_CLIENT_MODULE_PARM(adm1022_temp3, "List of adapter,address pairs " | |||
| 55 | static const u8 THMC50_REG_TEMP[] = { 0x27, 0x26, 0x20 }; | 55 | static const u8 THMC50_REG_TEMP[] = { 0x27, 0x26, 0x20 }; |
| 56 | static const u8 THMC50_REG_TEMP_MIN[] = { 0x3A, 0x38, 0x2C }; | 56 | static const u8 THMC50_REG_TEMP_MIN[] = { 0x3A, 0x38, 0x2C }; |
| 57 | static const u8 THMC50_REG_TEMP_MAX[] = { 0x39, 0x37, 0x2B }; | 57 | static const u8 THMC50_REG_TEMP_MAX[] = { 0x39, 0x37, 0x2B }; |
| 58 | static const u8 THMC50_REG_TEMP_CRITICAL[] = { 0x13, 0x14, 0x14 }; | ||
| 59 | static const u8 THMC50_REG_TEMP_DEFAULT[] = { 0x17, 0x18, 0x18 }; | ||
| 58 | 60 | ||
| 59 | #define THMC50_REG_CONF_nFANOFF 0x20 | 61 | #define THMC50_REG_CONF_nFANOFF 0x20 |
| 62 | #define THMC50_REG_CONF_PROGRAMMED 0x08 | ||
| 60 | 63 | ||
| 61 | /* Each client has this additional data */ | 64 | /* Each client has this additional data */ |
| 62 | struct thmc50_data { | 65 | struct thmc50_data { |
| @@ -72,6 +75,7 @@ struct thmc50_data { | |||
| 72 | s8 temp_input[3]; | 75 | s8 temp_input[3]; |
| 73 | s8 temp_max[3]; | 76 | s8 temp_max[3]; |
| 74 | s8 temp_min[3]; | 77 | s8 temp_min[3]; |
| 78 | s8 temp_critical[3]; | ||
| 75 | u8 analog_out; | 79 | u8 analog_out; |
| 76 | u8 alarms; | 80 | u8 alarms; |
| 77 | }; | 81 | }; |
| @@ -199,6 +203,15 @@ static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr, | |||
| 199 | return count; | 203 | return count; |
| 200 | } | 204 | } |
| 201 | 205 | ||
| 206 | static ssize_t show_temp_critical(struct device *dev, | ||
| 207 | struct device_attribute *attr, | ||
| 208 | char *buf) | ||
| 209 | { | ||
| 210 | int nr = to_sensor_dev_attr(attr)->index; | ||
| 211 | struct thmc50_data *data = thmc50_update_device(dev); | ||
| 212 | return sprintf(buf, "%d\n", data->temp_critical[nr] * 1000); | ||
| 213 | } | ||
| 214 | |||
| 202 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, | 215 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, |
| 203 | char *buf) | 216 | char *buf) |
| 204 | { | 217 | { |
| @@ -214,7 +227,9 @@ static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_temp, \ | |||
| 214 | static SENSOR_DEVICE_ATTR(temp##offset##_min, S_IRUGO | S_IWUSR, \ | 227 | static SENSOR_DEVICE_ATTR(temp##offset##_min, S_IRUGO | S_IWUSR, \ |
| 215 | show_temp_min, set_temp_min, offset - 1); \ | 228 | show_temp_min, set_temp_min, offset - 1); \ |
| 216 | static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \ | 229 | static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \ |
| 217 | show_temp_max, set_temp_max, offset - 1); | 230 | show_temp_max, set_temp_max, offset - 1); \ |
| 231 | static SENSOR_DEVICE_ATTR(temp##offset##_crit, S_IRUGO, \ | ||
| 232 | show_temp_critical, NULL, offset - 1); | ||
| 218 | 233 | ||
| 219 | temp_reg(1); | 234 | temp_reg(1); |
| 220 | temp_reg(2); | 235 | temp_reg(2); |
| @@ -234,10 +249,12 @@ static struct attribute *thmc50_attributes[] = { | |||
| 234 | &sensor_dev_attr_temp1_max.dev_attr.attr, | 249 | &sensor_dev_attr_temp1_max.dev_attr.attr, |
| 235 | &sensor_dev_attr_temp1_min.dev_attr.attr, | 250 | &sensor_dev_attr_temp1_min.dev_attr.attr, |
| 236 | &sensor_dev_attr_temp1_input.dev_attr.attr, | 251 | &sensor_dev_attr_temp1_input.dev_attr.attr, |
| 252 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | ||
| 237 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, | 253 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, |
| 238 | &sensor_dev_attr_temp2_max.dev_attr.attr, | 254 | &sensor_dev_attr_temp2_max.dev_attr.attr, |
| 239 | &sensor_dev_attr_temp2_min.dev_attr.attr, | 255 | &sensor_dev_attr_temp2_min.dev_attr.attr, |
| 240 | &sensor_dev_attr_temp2_input.dev_attr.attr, | 256 | &sensor_dev_attr_temp2_input.dev_attr.attr, |
| 257 | &sensor_dev_attr_temp2_crit.dev_attr.attr, | ||
| 241 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, | 258 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, |
| 242 | &sensor_dev_attr_temp2_fault.dev_attr.attr, | 259 | &sensor_dev_attr_temp2_fault.dev_attr.attr, |
| 243 | &sensor_dev_attr_pwm1.dev_attr.attr, | 260 | &sensor_dev_attr_pwm1.dev_attr.attr, |
| @@ -254,6 +271,7 @@ static struct attribute *temp3_attributes[] = { | |||
| 254 | &sensor_dev_attr_temp3_max.dev_attr.attr, | 271 | &sensor_dev_attr_temp3_max.dev_attr.attr, |
| 255 | &sensor_dev_attr_temp3_min.dev_attr.attr, | 272 | &sensor_dev_attr_temp3_min.dev_attr.attr, |
| 256 | &sensor_dev_attr_temp3_input.dev_attr.attr, | 273 | &sensor_dev_attr_temp3_input.dev_attr.attr, |
| 274 | &sensor_dev_attr_temp3_crit.dev_attr.attr, | ||
| 257 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, | 275 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, |
| 258 | &sensor_dev_attr_temp3_fault.dev_attr.attr, | 276 | &sensor_dev_attr_temp3_fault.dev_attr.attr, |
| 259 | NULL | 277 | NULL |
| @@ -429,6 +447,10 @@ static struct thmc50_data *thmc50_update_device(struct device *dev) | |||
| 429 | 447 | ||
| 430 | int temps = data->has_temp3 ? 3 : 2; | 448 | int temps = data->has_temp3 ? 3 : 2; |
| 431 | int i; | 449 | int i; |
| 450 | int prog = i2c_smbus_read_byte_data(client, THMC50_REG_CONF); | ||
| 451 | |||
| 452 | prog &= THMC50_REG_CONF_PROGRAMMED; | ||
| 453 | |||
| 432 | for (i = 0; i < temps; i++) { | 454 | for (i = 0; i < temps; i++) { |
| 433 | data->temp_input[i] = i2c_smbus_read_byte_data(client, | 455 | data->temp_input[i] = i2c_smbus_read_byte_data(client, |
| 434 | THMC50_REG_TEMP[i]); | 456 | THMC50_REG_TEMP[i]); |
| @@ -436,6 +458,10 @@ static struct thmc50_data *thmc50_update_device(struct device *dev) | |||
| 436 | THMC50_REG_TEMP_MAX[i]); | 458 | THMC50_REG_TEMP_MAX[i]); |
| 437 | data->temp_min[i] = i2c_smbus_read_byte_data(client, | 459 | data->temp_min[i] = i2c_smbus_read_byte_data(client, |
| 438 | THMC50_REG_TEMP_MIN[i]); | 460 | THMC50_REG_TEMP_MIN[i]); |
| 461 | data->temp_critical[i] = | ||
| 462 | i2c_smbus_read_byte_data(client, | ||
| 463 | prog ? THMC50_REG_TEMP_CRITICAL[i] | ||
| 464 | : THMC50_REG_TEMP_DEFAULT[i]); | ||
| 439 | } | 465 | } |
| 440 | data->analog_out = | 466 | data->analog_out = |
| 441 | i2c_smbus_read_byte_data(client, THMC50_REG_ANALOG_OUT); | 467 | i2c_smbus_read_byte_data(client, THMC50_REG_ANALOG_OUT); |
diff --git a/drivers/hwmon/w83627hf.c b/drivers/hwmon/w83627hf.c index 9564fb069957..b30e5796cb26 100644 --- a/drivers/hwmon/w83627hf.c +++ b/drivers/hwmon/w83627hf.c | |||
| @@ -67,10 +67,6 @@ module_param(force_i2c, byte, 0); | |||
| 67 | MODULE_PARM_DESC(force_i2c, | 67 | MODULE_PARM_DESC(force_i2c, |
| 68 | "Initialize the i2c address of the sensors"); | 68 | "Initialize the i2c address of the sensors"); |
| 69 | 69 | ||
| 70 | static int reset; | ||
| 71 | module_param(reset, bool, 0); | ||
| 72 | MODULE_PARM_DESC(reset, "Set to one to reset chip on load"); | ||
| 73 | |||
| 74 | static int init = 1; | 70 | static int init = 1; |
| 75 | module_param(init, bool, 0); | 71 | module_param(init, bool, 0); |
| 76 | MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization"); | 72 | MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization"); |
| @@ -209,6 +205,13 @@ static const u16 w83627hf_reg_temp_over[] = { 0x39, 0x155, 0x255 }; | |||
| 209 | #define W83627HF_REG_PWM1 0x5A | 205 | #define W83627HF_REG_PWM1 0x5A |
| 210 | #define W83627HF_REG_PWM2 0x5B | 206 | #define W83627HF_REG_PWM2 0x5B |
| 211 | 207 | ||
| 208 | static const u8 W83627THF_REG_PWM_ENABLE[] = { | ||
| 209 | 0x04, /* FAN 1 mode */ | ||
| 210 | 0x04, /* FAN 2 mode */ | ||
| 211 | 0x12, /* FAN AUX mode */ | ||
| 212 | }; | ||
| 213 | static const u8 W83627THF_PWM_ENABLE_SHIFT[] = { 2, 4, 1 }; | ||
| 214 | |||
| 212 | #define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */ | 215 | #define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */ |
| 213 | #define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */ | 216 | #define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */ |
| 214 | #define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */ | 217 | #define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */ |
| @@ -366,6 +369,9 @@ struct w83627hf_data { | |||
| 366 | u32 alarms; /* Register encoding, combined */ | 369 | u32 alarms; /* Register encoding, combined */ |
| 367 | u32 beep_mask; /* Register encoding, combined */ | 370 | u32 beep_mask; /* Register encoding, combined */ |
| 368 | u8 pwm[3]; /* Register value */ | 371 | u8 pwm[3]; /* Register value */ |
| 372 | u8 pwm_enable[3]; /* 1 = manual | ||
| 373 | 2 = thermal cruise (also called SmartFan I) | ||
| 374 | 3 = fan speed cruise */ | ||
| 369 | u8 pwm_freq[3]; /* Register value */ | 375 | u8 pwm_freq[3]; /* Register value */ |
| 370 | u16 sens[3]; /* 1 = pentium diode; 2 = 3904 diode; | 376 | u16 sens[3]; /* 1 = pentium diode; 2 = 3904 diode; |
| 371 | 4 = thermistor */ | 377 | 4 = thermistor */ |
| @@ -957,6 +963,42 @@ static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 1); | |||
| 957 | static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 2); | 963 | static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 2); |
| 958 | 964 | ||
| 959 | static ssize_t | 965 | static ssize_t |
| 966 | show_pwm_enable(struct device *dev, struct device_attribute *devattr, char *buf) | ||
| 967 | { | ||
| 968 | int nr = to_sensor_dev_attr(devattr)->index; | ||
| 969 | struct w83627hf_data *data = w83627hf_update_device(dev); | ||
| 970 | return sprintf(buf, "%d\n", data->pwm_enable[nr]); | ||
| 971 | } | ||
| 972 | |||
| 973 | static ssize_t | ||
| 974 | store_pwm_enable(struct device *dev, struct device_attribute *devattr, | ||
| 975 | const char *buf, size_t count) | ||
| 976 | { | ||
| 977 | int nr = to_sensor_dev_attr(devattr)->index; | ||
| 978 | struct w83627hf_data *data = dev_get_drvdata(dev); | ||
| 979 | unsigned long val = simple_strtoul(buf, NULL, 10); | ||
| 980 | u8 reg; | ||
| 981 | |||
| 982 | if (!val || (val > 3)) /* modes 1, 2 and 3 are supported */ | ||
| 983 | return -EINVAL; | ||
| 984 | mutex_lock(&data->update_lock); | ||
| 985 | data->pwm_enable[nr] = val; | ||
| 986 | reg = w83627hf_read_value(data, W83627THF_REG_PWM_ENABLE[nr]); | ||
| 987 | reg &= ~(0x03 << W83627THF_PWM_ENABLE_SHIFT[nr]); | ||
| 988 | reg |= (val - 1) << W83627THF_PWM_ENABLE_SHIFT[nr]; | ||
| 989 | w83627hf_write_value(data, W83627THF_REG_PWM_ENABLE[nr], reg); | ||
| 990 | mutex_unlock(&data->update_lock); | ||
| 991 | return count; | ||
| 992 | } | ||
| 993 | |||
| 994 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO|S_IWUSR, show_pwm_enable, | ||
| 995 | store_pwm_enable, 0); | ||
| 996 | static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO|S_IWUSR, show_pwm_enable, | ||
| 997 | store_pwm_enable, 1); | ||
| 998 | static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO|S_IWUSR, show_pwm_enable, | ||
| 999 | store_pwm_enable, 2); | ||
| 1000 | |||
| 1001 | static ssize_t | ||
| 960 | show_pwm_freq(struct device *dev, struct device_attribute *devattr, char *buf) | 1002 | show_pwm_freq(struct device *dev, struct device_attribute *devattr, char *buf) |
| 961 | { | 1003 | { |
| 962 | int nr = to_sensor_dev_attr(devattr)->index; | 1004 | int nr = to_sensor_dev_attr(devattr)->index; |
| @@ -1223,6 +1265,11 @@ static struct attribute *w83627hf_attributes_opt[] = { | |||
| 1223 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, | 1265 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, |
| 1224 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, | 1266 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, |
| 1225 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, | 1267 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, |
| 1268 | |||
| 1269 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, | ||
| 1270 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, | ||
| 1271 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, | ||
| 1272 | |||
| 1226 | NULL | 1273 | NULL |
| 1227 | }; | 1274 | }; |
| 1228 | 1275 | ||
| @@ -1366,6 +1413,19 @@ static int __devinit w83627hf_probe(struct platform_device *pdev) | |||
| 1366 | &sensor_dev_attr_pwm3_freq.dev_attr))) | 1413 | &sensor_dev_attr_pwm3_freq.dev_attr))) |
| 1367 | goto ERROR4; | 1414 | goto ERROR4; |
| 1368 | 1415 | ||
| 1416 | if (data->type != w83627hf) | ||
| 1417 | if ((err = device_create_file(dev, | ||
| 1418 | &sensor_dev_attr_pwm1_enable.dev_attr)) | ||
| 1419 | || (err = device_create_file(dev, | ||
| 1420 | &sensor_dev_attr_pwm2_enable.dev_attr))) | ||
| 1421 | goto ERROR4; | ||
| 1422 | |||
| 1423 | if (data->type == w83627thf || data->type == w83637hf | ||
| 1424 | || data->type == w83687thf) | ||
| 1425 | if ((err = device_create_file(dev, | ||
| 1426 | &sensor_dev_attr_pwm3_enable.dev_attr))) | ||
| 1427 | goto ERROR4; | ||
| 1428 | |||
| 1369 | data->hwmon_dev = hwmon_device_register(dev); | 1429 | data->hwmon_dev = hwmon_device_register(dev); |
| 1370 | if (IS_ERR(data->hwmon_dev)) { | 1430 | if (IS_ERR(data->hwmon_dev)) { |
| 1371 | err = PTR_ERR(data->hwmon_dev); | 1431 | err = PTR_ERR(data->hwmon_dev); |
| @@ -1536,29 +1596,6 @@ static void __devinit w83627hf_init_device(struct platform_device *pdev) | |||
| 1536 | enum chips type = data->type; | 1596 | enum chips type = data->type; |
| 1537 | u8 tmp; | 1597 | u8 tmp; |
| 1538 | 1598 | ||
| 1539 | if (reset) { | ||
| 1540 | /* Resetting the chip has been the default for a long time, | ||
| 1541 | but repeatedly caused problems (fans going to full | ||
| 1542 | speed...) so it is now optional. It might even go away if | ||
| 1543 | nobody reports it as being useful, as I see very little | ||
| 1544 | reason why this would be needed at all. */ | ||
| 1545 | dev_info(&pdev->dev, "If reset=1 solved a problem you were " | ||
| 1546 | "having, please report!\n"); | ||
| 1547 | |||
| 1548 | /* save this register */ | ||
| 1549 | i = w83627hf_read_value(data, W83781D_REG_BEEP_CONFIG); | ||
| 1550 | /* Reset all except Watchdog values and last conversion values | ||
| 1551 | This sets fan-divs to 2, among others */ | ||
| 1552 | w83627hf_write_value(data, W83781D_REG_CONFIG, 0x80); | ||
| 1553 | /* Restore the register and disable power-on abnormal beep. | ||
| 1554 | This saves FAN 1/2/3 input/output values set by BIOS. */ | ||
| 1555 | w83627hf_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80); | ||
| 1556 | /* Disable master beep-enable (reset turns it on). | ||
| 1557 | Individual beeps should be reset to off but for some reason | ||
| 1558 | disabling this bit helps some people not get beeped */ | ||
| 1559 | w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, 0); | ||
| 1560 | } | ||
| 1561 | |||
| 1562 | /* Minimize conflicts with other winbond i2c-only clients... */ | 1599 | /* Minimize conflicts with other winbond i2c-only clients... */ |
| 1563 | /* disable i2c subclients... how to disable main i2c client?? */ | 1600 | /* disable i2c subclients... how to disable main i2c client?? */ |
| 1564 | /* force i2c address to relatively uncommon address */ | 1601 | /* force i2c address to relatively uncommon address */ |
| @@ -1655,6 +1692,7 @@ static struct w83627hf_data *w83627hf_update_device(struct device *dev) | |||
| 1655 | { | 1692 | { |
| 1656 | struct w83627hf_data *data = dev_get_drvdata(dev); | 1693 | struct w83627hf_data *data = dev_get_drvdata(dev); |
| 1657 | int i, num_temps = (data->type == w83697hf) ? 2 : 3; | 1694 | int i, num_temps = (data->type == w83697hf) ? 2 : 3; |
| 1695 | int num_pwms = (data->type == w83697hf) ? 2 : 3; | ||
| 1658 | 1696 | ||
| 1659 | mutex_lock(&data->update_lock); | 1697 | mutex_lock(&data->update_lock); |
| 1660 | 1698 | ||
| @@ -1707,6 +1745,15 @@ static struct w83627hf_data *w83627hf_update_device(struct device *dev) | |||
| 1707 | break; | 1745 | break; |
| 1708 | } | 1746 | } |
| 1709 | } | 1747 | } |
| 1748 | if (data->type != w83627hf) { | ||
| 1749 | for (i = 0; i < num_pwms; i++) { | ||
| 1750 | u8 tmp = w83627hf_read_value(data, | ||
| 1751 | W83627THF_REG_PWM_ENABLE[i]); | ||
| 1752 | data->pwm_enable[i] = | ||
| 1753 | ((tmp >> W83627THF_PWM_ENABLE_SHIFT[i]) | ||
| 1754 | & 0x03) + 1; | ||
| 1755 | } | ||
| 1756 | } | ||
| 1710 | for (i = 0; i < num_temps; i++) { | 1757 | for (i = 0; i < num_temps; i++) { |
| 1711 | data->temp[i] = w83627hf_read_value( | 1758 | data->temp[i] = w83627hf_read_value( |
| 1712 | data, w83627hf_reg_temp[i]); | 1759 | data, w83627hf_reg_temp[i]); |
diff --git a/drivers/hwmon/w83791d.c b/drivers/hwmon/w83791d.c index e4e91c9d480a..daa7d121483b 100644 --- a/drivers/hwmon/w83791d.c +++ b/drivers/hwmon/w83791d.c | |||
| @@ -233,11 +233,9 @@ static u8 fan_to_reg(long rpm, int div) | |||
| 233 | static u8 div_to_reg(int nr, long val) | 233 | static u8 div_to_reg(int nr, long val) |
| 234 | { | 234 | { |
| 235 | int i; | 235 | int i; |
| 236 | int max; | ||
| 237 | 236 | ||
| 238 | /* first three fan's divisor max out at 8, rest max out at 128 */ | 237 | /* fan divisors max out at 128 */ |
| 239 | max = (nr < 3) ? 8 : 128; | 238 | val = SENSORS_LIMIT(val, 1, 128) >> 1; |
| 240 | val = SENSORS_LIMIT(val, 1, max) >> 1; | ||
| 241 | for (i = 0; i < 7; i++) { | 239 | for (i = 0; i < 7; i++) { |
| 242 | if (val == 0) | 240 | if (val == 0) |
| 243 | break; | 241 | break; |
| @@ -530,6 +528,7 @@ static ssize_t store_fan_div(struct device *dev, struct device_attribute *attr, | |||
| 530 | unsigned long min; | 528 | unsigned long min; |
| 531 | u8 tmp_fan_div; | 529 | u8 tmp_fan_div; |
| 532 | u8 fan_div_reg; | 530 | u8 fan_div_reg; |
| 531 | u8 vbat_reg; | ||
| 533 | int indx = 0; | 532 | int indx = 0; |
| 534 | u8 keep_mask = 0; | 533 | u8 keep_mask = 0; |
| 535 | u8 new_shift = 0; | 534 | u8 new_shift = 0; |
| @@ -581,6 +580,16 @@ static ssize_t store_fan_div(struct device *dev, struct device_attribute *attr, | |||
| 581 | w83791d_write(client, W83791D_REG_FAN_DIV[indx], | 580 | w83791d_write(client, W83791D_REG_FAN_DIV[indx], |
| 582 | fan_div_reg | tmp_fan_div); | 581 | fan_div_reg | tmp_fan_div); |
| 583 | 582 | ||
| 583 | /* Bit 2 of fans 0-2 is stored in the vbat register (bits 5-7) */ | ||
| 584 | if (nr < 3) { | ||
| 585 | keep_mask = ~(1 << (nr + 5)); | ||
| 586 | vbat_reg = w83791d_read(client, W83791D_REG_VBAT) | ||
| 587 | & keep_mask; | ||
| 588 | tmp_fan_div = (data->fan_div[nr] << (3 + nr)) & ~keep_mask; | ||
| 589 | w83791d_write(client, W83791D_REG_VBAT, | ||
| 590 | vbat_reg | tmp_fan_div); | ||
| 591 | } | ||
| 592 | |||
| 584 | /* Restore fan_min */ | 593 | /* Restore fan_min */ |
| 585 | data->fan_min[nr] = fan_to_reg(min, DIV_FROM_REG(data->fan_div[nr])); | 594 | data->fan_min[nr] = fan_to_reg(min, DIV_FROM_REG(data->fan_div[nr])); |
| 586 | w83791d_write(client, W83791D_REG_FAN_MIN[nr], data->fan_min[nr]); | 595 | w83791d_write(client, W83791D_REG_FAN_MIN[nr], data->fan_min[nr]); |
| @@ -1182,6 +1191,7 @@ static struct w83791d_data *w83791d_update_device(struct device *dev) | |||
| 1182 | struct w83791d_data *data = i2c_get_clientdata(client); | 1191 | struct w83791d_data *data = i2c_get_clientdata(client); |
| 1183 | int i, j; | 1192 | int i, j; |
| 1184 | u8 reg_array_tmp[3]; | 1193 | u8 reg_array_tmp[3]; |
| 1194 | u8 vbat_reg; | ||
| 1185 | 1195 | ||
| 1186 | mutex_lock(&data->update_lock); | 1196 | mutex_lock(&data->update_lock); |
| 1187 | 1197 | ||
| @@ -1219,6 +1229,12 @@ static struct w83791d_data *w83791d_update_device(struct device *dev) | |||
| 1219 | data->fan_div[3] = reg_array_tmp[2] & 0x07; | 1229 | data->fan_div[3] = reg_array_tmp[2] & 0x07; |
| 1220 | data->fan_div[4] = (reg_array_tmp[2] >> 4) & 0x07; | 1230 | data->fan_div[4] = (reg_array_tmp[2] >> 4) & 0x07; |
| 1221 | 1231 | ||
| 1232 | /* The fan divisor for fans 0-2 get bit 2 from | ||
| 1233 | bits 5-7 respectively of vbat register */ | ||
| 1234 | vbat_reg = w83791d_read(client, W83791D_REG_VBAT); | ||
| 1235 | for (i = 0; i < 3; i++) | ||
| 1236 | data->fan_div[i] |= (vbat_reg >> (3 + i)) & 0x04; | ||
| 1237 | |||
| 1222 | /* Update the first temperature sensor */ | 1238 | /* Update the first temperature sensor */ |
| 1223 | for (i = 0; i < 3; i++) { | 1239 | for (i = 0; i < 3; i++) { |
| 1224 | data->temp1[i] = w83791d_read(client, | 1240 | data->temp1[i] = w83791d_read(client, |
diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c index e980ff3335db..d951896ff7fc 100644 --- a/drivers/infiniband/core/cma.c +++ b/drivers/infiniband/core/cma.c | |||
| @@ -155,9 +155,7 @@ struct cma_multicast { | |||
| 155 | } multicast; | 155 | } multicast; |
| 156 | struct list_head list; | 156 | struct list_head list; |
| 157 | void *context; | 157 | void *context; |
| 158 | struct sockaddr addr; | 158 | struct sockaddr_storage addr; |
| 159 | u8 pad[sizeof(struct sockaddr_in6) - | ||
| 160 | sizeof(struct sockaddr)]; | ||
| 161 | }; | 159 | }; |
| 162 | 160 | ||
| 163 | struct cma_work { | 161 | struct cma_work { |
| @@ -786,8 +784,8 @@ static void cma_cancel_operation(struct rdma_id_private *id_priv, | |||
| 786 | cma_cancel_route(id_priv); | 784 | cma_cancel_route(id_priv); |
| 787 | break; | 785 | break; |
| 788 | case CMA_LISTEN: | 786 | case CMA_LISTEN: |
| 789 | if (cma_any_addr(&id_priv->id.route.addr.src_addr) && | 787 | if (cma_any_addr((struct sockaddr *) &id_priv->id.route.addr.src_addr) |
| 790 | !id_priv->cma_dev) | 788 | && !id_priv->cma_dev) |
| 791 | cma_cancel_listens(id_priv); | 789 | cma_cancel_listens(id_priv); |
| 792 | break; | 790 | break; |
| 793 | default: | 791 | default: |
| @@ -1026,7 +1024,7 @@ static struct rdma_id_private *cma_new_conn_id(struct rdma_cm_id *listen_id, | |||
| 1026 | rt->path_rec[1] = *ib_event->param.req_rcvd.alternate_path; | 1024 | rt->path_rec[1] = *ib_event->param.req_rcvd.alternate_path; |
| 1027 | 1025 | ||
| 1028 | ib_addr_set_dgid(&rt->addr.dev_addr, &rt->path_rec[0].dgid); | 1026 | ib_addr_set_dgid(&rt->addr.dev_addr, &rt->path_rec[0].dgid); |
| 1029 | ret = rdma_translate_ip(&id->route.addr.src_addr, | 1027 | ret = rdma_translate_ip((struct sockaddr *) &id->route.addr.src_addr, |
| 1030 | &id->route.addr.dev_addr); | 1028 | &id->route.addr.dev_addr); |
| 1031 | if (ret) | 1029 | if (ret) |
| 1032 | goto destroy_id; | 1030 | goto destroy_id; |
| @@ -1064,7 +1062,7 @@ static struct rdma_id_private *cma_new_udp_id(struct rdma_cm_id *listen_id, | |||
| 1064 | cma_save_net_info(&id->route.addr, &listen_id->route.addr, | 1062 | cma_save_net_info(&id->route.addr, &listen_id->route.addr, |
| 1065 | ip_ver, port, src, dst); | 1063 | ip_ver, port, src, dst); |
| 1066 | 1064 | ||
| 1067 | ret = rdma_translate_ip(&id->route.addr.src_addr, | 1065 | ret = rdma_translate_ip((struct sockaddr *) &id->route.addr.src_addr, |
| 1068 | &id->route.addr.dev_addr); | 1066 | &id->route.addr.dev_addr); |
| 1069 | if (ret) | 1067 | if (ret) |
| 1070 | goto err; | 1068 | goto err; |
| @@ -1377,7 +1375,7 @@ static int cma_ib_listen(struct rdma_id_private *id_priv) | |||
| 1377 | if (IS_ERR(id_priv->cm_id.ib)) | 1375 | if (IS_ERR(id_priv->cm_id.ib)) |
| 1378 | return PTR_ERR(id_priv->cm_id.ib); | 1376 | return PTR_ERR(id_priv->cm_id.ib); |
| 1379 | 1377 | ||
| 1380 | addr = &id_priv->id.route.addr.src_addr; | 1378 | addr = (struct sockaddr *) &id_priv->id.route.addr.src_addr; |
| 1381 | svc_id = cma_get_service_id(id_priv->id.ps, addr); | 1379 | svc_id = cma_get_service_id(id_priv->id.ps, addr); |
| 1382 | if (cma_any_addr(addr)) | 1380 | if (cma_any_addr(addr)) |
| 1383 | ret = ib_cm_listen(id_priv->cm_id.ib, svc_id, 0, NULL); | 1381 | ret = ib_cm_listen(id_priv->cm_id.ib, svc_id, 0, NULL); |
| @@ -1443,7 +1441,7 @@ static void cma_listen_on_dev(struct rdma_id_private *id_priv, | |||
| 1443 | 1441 | ||
| 1444 | dev_id_priv->state = CMA_ADDR_BOUND; | 1442 | dev_id_priv->state = CMA_ADDR_BOUND; |
| 1445 | memcpy(&id->route.addr.src_addr, &id_priv->id.route.addr.src_addr, | 1443 | memcpy(&id->route.addr.src_addr, &id_priv->id.route.addr.src_addr, |
| 1446 | ip_addr_size(&id_priv->id.route.addr.src_addr)); | 1444 | ip_addr_size((struct sockaddr *) &id_priv->id.route.addr.src_addr)); |
| 1447 | 1445 | ||
| 1448 | cma_attach_to_dev(dev_id_priv, cma_dev); | 1446 | cma_attach_to_dev(dev_id_priv, cma_dev); |
| 1449 | list_add_tail(&dev_id_priv->listen_list, &id_priv->listen_list); | 1447 | list_add_tail(&dev_id_priv->listen_list, &id_priv->listen_list); |
| @@ -1563,13 +1561,14 @@ static int cma_query_ib_route(struct rdma_id_private *id_priv, int timeout_ms, | |||
| 1563 | path_rec.pkey = cpu_to_be16(ib_addr_get_pkey(&addr->dev_addr)); | 1561 | path_rec.pkey = cpu_to_be16(ib_addr_get_pkey(&addr->dev_addr)); |
| 1564 | path_rec.numb_path = 1; | 1562 | path_rec.numb_path = 1; |
| 1565 | path_rec.reversible = 1; | 1563 | path_rec.reversible = 1; |
| 1566 | path_rec.service_id = cma_get_service_id(id_priv->id.ps, &addr->dst_addr); | 1564 | path_rec.service_id = cma_get_service_id(id_priv->id.ps, |
| 1565 | (struct sockaddr *) &addr->dst_addr); | ||
| 1567 | 1566 | ||
| 1568 | comp_mask = IB_SA_PATH_REC_DGID | IB_SA_PATH_REC_SGID | | 1567 | comp_mask = IB_SA_PATH_REC_DGID | IB_SA_PATH_REC_SGID | |
| 1569 | IB_SA_PATH_REC_PKEY | IB_SA_PATH_REC_NUMB_PATH | | 1568 | IB_SA_PATH_REC_PKEY | IB_SA_PATH_REC_NUMB_PATH | |
| 1570 | IB_SA_PATH_REC_REVERSIBLE | IB_SA_PATH_REC_SERVICE_ID; | 1569 | IB_SA_PATH_REC_REVERSIBLE | IB_SA_PATH_REC_SERVICE_ID; |
| 1571 | 1570 | ||
| 1572 | if (addr->src_addr.sa_family == AF_INET) { | 1571 | if (addr->src_addr.ss_family == AF_INET) { |
| 1573 | path_rec.qos_class = cpu_to_be16((u16) id_priv->tos); | 1572 | path_rec.qos_class = cpu_to_be16((u16) id_priv->tos); |
| 1574 | comp_mask |= IB_SA_PATH_REC_QOS_CLASS; | 1573 | comp_mask |= IB_SA_PATH_REC_QOS_CLASS; |
| 1575 | } else { | 1574 | } else { |
| @@ -1848,7 +1847,7 @@ static int cma_resolve_loopback(struct rdma_id_private *id_priv) | |||
| 1848 | ib_addr_get_sgid(&id_priv->id.route.addr.dev_addr, &gid); | 1847 | ib_addr_get_sgid(&id_priv->id.route.addr.dev_addr, &gid); |
| 1849 | ib_addr_set_dgid(&id_priv->id.route.addr.dev_addr, &gid); | 1848 | ib_addr_set_dgid(&id_priv->id.route.addr.dev_addr, &gid); |
| 1850 | 1849 | ||
| 1851 | if (cma_zero_addr(&id_priv->id.route.addr.src_addr)) { | 1850 | if (cma_zero_addr((struct sockaddr *) &id_priv->id.route.addr.src_addr)) { |
| 1852 | src_in = (struct sockaddr_in *)&id_priv->id.route.addr.src_addr; | 1851 | src_in = (struct sockaddr_in *)&id_priv->id.route.addr.src_addr; |
| 1853 | dst_in = (struct sockaddr_in *)&id_priv->id.route.addr.dst_addr; | 1852 | dst_in = (struct sockaddr_in *)&id_priv->id.route.addr.dst_addr; |
| 1854 | src_in->sin_family = dst_in->sin_family; | 1853 | src_in->sin_family = dst_in->sin_family; |
| @@ -1897,7 +1896,7 @@ int rdma_resolve_addr(struct rdma_cm_id *id, struct sockaddr *src_addr, | |||
| 1897 | if (cma_any_addr(dst_addr)) | 1896 | if (cma_any_addr(dst_addr)) |
| 1898 | ret = cma_resolve_loopback(id_priv); | 1897 | ret = cma_resolve_loopback(id_priv); |
| 1899 | else | 1898 | else |
| 1900 | ret = rdma_resolve_ip(&addr_client, &id->route.addr.src_addr, | 1899 | ret = rdma_resolve_ip(&addr_client, (struct sockaddr *) &id->route.addr.src_addr, |
| 1901 | dst_addr, &id->route.addr.dev_addr, | 1900 | dst_addr, &id->route.addr.dev_addr, |
| 1902 | timeout_ms, addr_handler, id_priv); | 1901 | timeout_ms, addr_handler, id_priv); |
| 1903 | if (ret) | 1902 | if (ret) |
| @@ -2021,11 +2020,11 @@ static int cma_use_port(struct idr *ps, struct rdma_id_private *id_priv) | |||
| 2021 | * We don't support binding to any address if anyone is bound to | 2020 | * We don't support binding to any address if anyone is bound to |
| 2022 | * a specific address on the same port. | 2021 | * a specific address on the same port. |
| 2023 | */ | 2022 | */ |
| 2024 | if (cma_any_addr(&id_priv->id.route.addr.src_addr)) | 2023 | if (cma_any_addr((struct sockaddr *) &id_priv->id.route.addr.src_addr)) |
| 2025 | return -EADDRNOTAVAIL; | 2024 | return -EADDRNOTAVAIL; |
| 2026 | 2025 | ||
| 2027 | hlist_for_each_entry(cur_id, node, &bind_list->owners, node) { | 2026 | hlist_for_each_entry(cur_id, node, &bind_list->owners, node) { |
| 2028 | if (cma_any_addr(&cur_id->id.route.addr.src_addr)) | 2027 | if (cma_any_addr((struct sockaddr *) &cur_id->id.route.addr.src_addr)) |
| 2029 | return -EADDRNOTAVAIL; | 2028 | return -EADDRNOTAVAIL; |
| 2030 | 2029 | ||
| 2031 | cur_sin = (struct sockaddr_in *) &cur_id->id.route.addr.src_addr; | 2030 | cur_sin = (struct sockaddr_in *) &cur_id->id.route.addr.src_addr; |
| @@ -2060,7 +2059,7 @@ static int cma_get_port(struct rdma_id_private *id_priv) | |||
| 2060 | } | 2059 | } |
| 2061 | 2060 | ||
| 2062 | mutex_lock(&lock); | 2061 | mutex_lock(&lock); |
| 2063 | if (cma_any_port(&id_priv->id.route.addr.src_addr)) | 2062 | if (cma_any_port((struct sockaddr *) &id_priv->id.route.addr.src_addr)) |
| 2064 | ret = cma_alloc_any_port(ps, id_priv); | 2063 | ret = cma_alloc_any_port(ps, id_priv); |
| 2065 | else | 2064 | else |
| 2066 | ret = cma_use_port(ps, id_priv); | 2065 | ret = cma_use_port(ps, id_priv); |
| @@ -2232,7 +2231,7 @@ static int cma_resolve_ib_udp(struct rdma_id_private *id_priv, | |||
| 2232 | 2231 | ||
| 2233 | req.path = route->path_rec; | 2232 | req.path = route->path_rec; |
| 2234 | req.service_id = cma_get_service_id(id_priv->id.ps, | 2233 | req.service_id = cma_get_service_id(id_priv->id.ps, |
| 2235 | &route->addr.dst_addr); | 2234 | (struct sockaddr *) &route->addr.dst_addr); |
| 2236 | req.timeout_ms = 1 << (CMA_CM_RESPONSE_TIMEOUT - 8); | 2235 | req.timeout_ms = 1 << (CMA_CM_RESPONSE_TIMEOUT - 8); |
| 2237 | req.max_cm_retries = CMA_MAX_CM_RETRIES; | 2236 | req.max_cm_retries = CMA_MAX_CM_RETRIES; |
| 2238 | 2237 | ||
| @@ -2283,7 +2282,7 @@ static int cma_connect_ib(struct rdma_id_private *id_priv, | |||
| 2283 | req.alternate_path = &route->path_rec[1]; | 2282 | req.alternate_path = &route->path_rec[1]; |
| 2284 | 2283 | ||
| 2285 | req.service_id = cma_get_service_id(id_priv->id.ps, | 2284 | req.service_id = cma_get_service_id(id_priv->id.ps, |
| 2286 | &route->addr.dst_addr); | 2285 | (struct sockaddr *) &route->addr.dst_addr); |
| 2287 | req.qp_num = id_priv->qp_num; | 2286 | req.qp_num = id_priv->qp_num; |
| 2288 | req.qp_type = IB_QPT_RC; | 2287 | req.qp_type = IB_QPT_RC; |
| 2289 | req.starting_psn = id_priv->seq_num; | 2288 | req.starting_psn = id_priv->seq_num; |
| @@ -2667,7 +2666,7 @@ static int cma_join_ib_multicast(struct rdma_id_private *id_priv, | |||
| 2667 | if (ret) | 2666 | if (ret) |
| 2668 | return ret; | 2667 | return ret; |
| 2669 | 2668 | ||
| 2670 | cma_set_mgid(id_priv, &mc->addr, &rec.mgid); | 2669 | cma_set_mgid(id_priv, (struct sockaddr *) &mc->addr, &rec.mgid); |
| 2671 | if (id_priv->id.ps == RDMA_PS_UDP) | 2670 | if (id_priv->id.ps == RDMA_PS_UDP) |
| 2672 | rec.qkey = cpu_to_be32(RDMA_UDP_QKEY); | 2671 | rec.qkey = cpu_to_be32(RDMA_UDP_QKEY); |
| 2673 | ib_addr_get_sgid(dev_addr, &rec.port_gid); | 2672 | ib_addr_get_sgid(dev_addr, &rec.port_gid); |
diff --git a/drivers/infiniband/core/mad_rmpp.c b/drivers/infiniband/core/mad_rmpp.c index d0ef7d61c037..3af2b84cd838 100644 --- a/drivers/infiniband/core/mad_rmpp.c +++ b/drivers/infiniband/core/mad_rmpp.c | |||
| @@ -133,7 +133,7 @@ static void ack_recv(struct mad_rmpp_recv *rmpp_recv, | |||
| 133 | msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp, | 133 | msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp, |
| 134 | recv_wc->wc->pkey_index, 1, hdr_len, | 134 | recv_wc->wc->pkey_index, 1, hdr_len, |
| 135 | 0, GFP_KERNEL); | 135 | 0, GFP_KERNEL); |
| 136 | if (!msg) | 136 | if (IS_ERR(msg)) |
| 137 | return; | 137 | return; |
| 138 | 138 | ||
| 139 | format_ack(msg, (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv); | 139 | format_ack(msg, (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv); |
diff --git a/drivers/infiniband/core/ucma.c b/drivers/infiniband/core/ucma.c index b41dd26bbfa1..3ddacf39b7ba 100644 --- a/drivers/infiniband/core/ucma.c +++ b/drivers/infiniband/core/ucma.c | |||
| @@ -81,9 +81,7 @@ struct ucma_multicast { | |||
| 81 | 81 | ||
| 82 | u64 uid; | 82 | u64 uid; |
| 83 | struct list_head list; | 83 | struct list_head list; |
| 84 | struct sockaddr addr; | 84 | struct sockaddr_storage addr; |
| 85 | u8 pad[sizeof(struct sockaddr_in6) - | ||
| 86 | sizeof(struct sockaddr)]; | ||
| 87 | }; | 85 | }; |
| 88 | 86 | ||
| 89 | struct ucma_event { | 87 | struct ucma_event { |
| @@ -603,11 +601,11 @@ static ssize_t ucma_query_route(struct ucma_file *file, | |||
| 603 | return PTR_ERR(ctx); | 601 | return PTR_ERR(ctx); |
| 604 | 602 | ||
| 605 | memset(&resp, 0, sizeof resp); | 603 | memset(&resp, 0, sizeof resp); |
| 606 | addr = &ctx->cm_id->route.addr.src_addr; | 604 | addr = (struct sockaddr *) &ctx->cm_id->route.addr.src_addr; |
| 607 | memcpy(&resp.src_addr, addr, addr->sa_family == AF_INET ? | 605 | memcpy(&resp.src_addr, addr, addr->sa_family == AF_INET ? |
| 608 | sizeof(struct sockaddr_in) : | 606 | sizeof(struct sockaddr_in) : |
| 609 | sizeof(struct sockaddr_in6)); | 607 | sizeof(struct sockaddr_in6)); |
| 610 | addr = &ctx->cm_id->route.addr.dst_addr; | 608 | addr = (struct sockaddr *) &ctx->cm_id->route.addr.dst_addr; |
| 611 | memcpy(&resp.dst_addr, addr, addr->sa_family == AF_INET ? | 609 | memcpy(&resp.dst_addr, addr, addr->sa_family == AF_INET ? |
| 612 | sizeof(struct sockaddr_in) : | 610 | sizeof(struct sockaddr_in) : |
| 613 | sizeof(struct sockaddr_in6)); | 611 | sizeof(struct sockaddr_in6)); |
| @@ -913,7 +911,7 @@ static ssize_t ucma_join_multicast(struct ucma_file *file, | |||
| 913 | 911 | ||
| 914 | mc->uid = cmd.uid; | 912 | mc->uid = cmd.uid; |
| 915 | memcpy(&mc->addr, &cmd.addr, sizeof cmd.addr); | 913 | memcpy(&mc->addr, &cmd.addr, sizeof cmd.addr); |
| 916 | ret = rdma_join_multicast(ctx->cm_id, &mc->addr, mc); | 914 | ret = rdma_join_multicast(ctx->cm_id, (struct sockaddr *) &mc->addr, mc); |
| 917 | if (ret) | 915 | if (ret) |
| 918 | goto err2; | 916 | goto err2; |
| 919 | 917 | ||
| @@ -929,7 +927,7 @@ static ssize_t ucma_join_multicast(struct ucma_file *file, | |||
| 929 | return 0; | 927 | return 0; |
| 930 | 928 | ||
| 931 | err3: | 929 | err3: |
| 932 | rdma_leave_multicast(ctx->cm_id, &mc->addr); | 930 | rdma_leave_multicast(ctx->cm_id, (struct sockaddr *) &mc->addr); |
| 933 | ucma_cleanup_mc_events(mc); | 931 | ucma_cleanup_mc_events(mc); |
| 934 | err2: | 932 | err2: |
| 935 | mutex_lock(&mut); | 933 | mutex_lock(&mut); |
| @@ -975,7 +973,7 @@ static ssize_t ucma_leave_multicast(struct ucma_file *file, | |||
| 975 | goto out; | 973 | goto out; |
| 976 | } | 974 | } |
| 977 | 975 | ||
| 978 | rdma_leave_multicast(mc->ctx->cm_id, &mc->addr); | 976 | rdma_leave_multicast(mc->ctx->cm_id, (struct sockaddr *) &mc->addr); |
| 979 | mutex_lock(&mc->ctx->file->mut); | 977 | mutex_lock(&mc->ctx->file->mut); |
| 980 | ucma_cleanup_mc_events(mc); | 978 | ucma_cleanup_mc_events(mc); |
| 981 | list_del(&mc->list); | 979 | list_del(&mc->list); |
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c index f6d5747153a5..4dcf08b3fd83 100644 --- a/drivers/infiniband/hw/cxgb3/cxio_hal.c +++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c | |||
| @@ -725,9 +725,9 @@ static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry, | |||
| 725 | V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid)); | 725 | V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid)); |
| 726 | BUG_ON(page_size >= 28); | 726 | BUG_ON(page_size >= 28); |
| 727 | tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) | | 727 | tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) | |
| 728 | F_TPT_MW_BIND_ENABLE | | 728 | ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) | |
| 729 | V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) | | 729 | V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) | |
| 730 | V_TPT_PAGE_SIZE(page_size)); | 730 | V_TPT_PAGE_SIZE(page_size)); |
| 731 | tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 : | 731 | tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 : |
| 732 | cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3)); | 732 | cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3)); |
| 733 | tpt.len = cpu_to_be32(len); | 733 | tpt.len = cpu_to_be32(len); |
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.c b/drivers/infiniband/hw/cxgb3/iwch_provider.c index b89640aa6e10..eb778bfd6f66 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_provider.c +++ b/drivers/infiniband/hw/cxgb3/iwch_provider.c | |||
| @@ -1187,28 +1187,6 @@ static ssize_t show_rev(struct device *dev, struct device_attribute *attr, | |||
| 1187 | return sprintf(buf, "%d\n", iwch_dev->rdev.t3cdev_p->type); | 1187 | return sprintf(buf, "%d\n", iwch_dev->rdev.t3cdev_p->type); |
| 1188 | } | 1188 | } |
| 1189 | 1189 | ||
| 1190 | static int fw_supports_fastreg(struct iwch_dev *iwch_dev) | ||
| 1191 | { | ||
| 1192 | struct ethtool_drvinfo info; | ||
| 1193 | struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev; | ||
| 1194 | char *cp, *next; | ||
| 1195 | unsigned fw_maj, fw_min; | ||
| 1196 | |||
| 1197 | rtnl_lock(); | ||
| 1198 | lldev->ethtool_ops->get_drvinfo(lldev, &info); | ||
| 1199 | rtnl_unlock(); | ||
| 1200 | |||
| 1201 | next = info.fw_version+1; | ||
| 1202 | cp = strsep(&next, "."); | ||
| 1203 | sscanf(cp, "%i", &fw_maj); | ||
| 1204 | cp = strsep(&next, "."); | ||
| 1205 | sscanf(cp, "%i", &fw_min); | ||
| 1206 | |||
| 1207 | PDBG("%s maj %u min %u\n", __func__, fw_maj, fw_min); | ||
| 1208 | |||
| 1209 | return fw_maj > 6 || (fw_maj == 6 && fw_min > 0); | ||
| 1210 | } | ||
| 1211 | |||
| 1212 | static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, char *buf) | 1190 | static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, char *buf) |
| 1213 | { | 1191 | { |
| 1214 | struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev, | 1192 | struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev, |
| @@ -1325,12 +1303,12 @@ int iwch_register_device(struct iwch_dev *dev) | |||
| 1325 | memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid)); | 1303 | memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid)); |
| 1326 | memcpy(&dev->ibdev.node_guid, dev->rdev.t3cdev_p->lldev->dev_addr, 6); | 1304 | memcpy(&dev->ibdev.node_guid, dev->rdev.t3cdev_p->lldev->dev_addr, 6); |
| 1327 | dev->ibdev.owner = THIS_MODULE; | 1305 | dev->ibdev.owner = THIS_MODULE; |
| 1328 | dev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY | IB_DEVICE_MEM_WINDOW; | 1306 | dev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY | |
| 1307 | IB_DEVICE_MEM_WINDOW | | ||
| 1308 | IB_DEVICE_MEM_MGT_EXTENSIONS; | ||
| 1329 | 1309 | ||
| 1330 | /* cxgb3 supports STag 0. */ | 1310 | /* cxgb3 supports STag 0. */ |
| 1331 | dev->ibdev.local_dma_lkey = 0; | 1311 | dev->ibdev.local_dma_lkey = 0; |
| 1332 | if (fw_supports_fastreg(dev)) | ||
| 1333 | dev->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; | ||
| 1334 | 1312 | ||
| 1335 | dev->ibdev.uverbs_cmd_mask = | 1313 | dev->ibdev.uverbs_cmd_mask = |
| 1336 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | | 1314 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | |
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.h b/drivers/infiniband/hw/cxgb3/iwch_provider.h index f5ceca05c435..a237d49bdcc9 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_provider.h +++ b/drivers/infiniband/hw/cxgb3/iwch_provider.h | |||
| @@ -293,9 +293,16 @@ static inline u32 iwch_ib_to_tpt_access(int acc) | |||
| 293 | return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) | | 293 | return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) | |
| 294 | (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) | | 294 | (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) | |
| 295 | (acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) | | 295 | (acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) | |
| 296 | (acc & IB_ACCESS_MW_BIND ? TPT_MW_BIND : 0) | | ||
| 296 | TPT_LOCAL_READ; | 297 | TPT_LOCAL_READ; |
| 297 | } | 298 | } |
| 298 | 299 | ||
| 300 | static inline u32 iwch_ib_to_tpt_bind_access(int acc) | ||
| 301 | { | ||
| 302 | return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) | | ||
| 303 | (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0); | ||
| 304 | } | ||
| 305 | |||
| 299 | enum iwch_mmid_state { | 306 | enum iwch_mmid_state { |
| 300 | IWCH_STAG_STATE_VALID, | 307 | IWCH_STAG_STATE_VALID, |
| 301 | IWCH_STAG_STATE_INVALID | 308 | IWCH_STAG_STATE_INVALID |
diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c index 9a3be3a9d5dc..3e4585c2318a 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_qp.c +++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c | |||
| @@ -565,7 +565,7 @@ int iwch_bind_mw(struct ib_qp *qp, | |||
| 565 | wqe->bind.type = TPT_VATO; | 565 | wqe->bind.type = TPT_VATO; |
| 566 | 566 | ||
| 567 | /* TBD: check perms */ | 567 | /* TBD: check perms */ |
| 568 | wqe->bind.perms = iwch_ib_to_tpt_access(mw_bind->mw_access_flags); | 568 | wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags); |
| 569 | wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey); | 569 | wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey); |
| 570 | wqe->bind.mw_stag = cpu_to_be32(mw->rkey); | 570 | wqe->bind.mw_stag = cpu_to_be32(mw->rkey); |
| 571 | wqe->bind.mw_len = cpu_to_be32(mw_bind->length); | 571 | wqe->bind.mw_len = cpu_to_be32(mw_bind->length); |
| @@ -879,20 +879,13 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp, | |||
| 879 | (qhp->attr.mpa_attr.xmit_marker_enabled << 1) | | 879 | (qhp->attr.mpa_attr.xmit_marker_enabled << 1) | |
| 880 | (qhp->attr.mpa_attr.crc_enabled << 2); | 880 | (qhp->attr.mpa_attr.crc_enabled << 2); |
| 881 | 881 | ||
| 882 | /* | 882 | init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE | |
| 883 | * XXX - The IWCM doesn't quite handle getting these | 883 | uP_RI_QP_RDMA_WRITE_ENABLE | |
| 884 | * attrs set before going into RTS. For now, just turn | 884 | uP_RI_QP_BIND_ENABLE; |
| 885 | * them on always... | 885 | if (!qhp->ibqp.uobject) |
| 886 | */ | 886 | init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE | |
| 887 | #if 0 | 887 | uP_RI_QP_FAST_REGISTER_ENABLE; |
| 888 | init_attr.qpcaps = qhp->attr.enableRdmaRead | | 888 | |
| 889 | (qhp->attr.enableRdmaWrite << 1) | | ||
| 890 | (qhp->attr.enableBind << 2) | | ||
| 891 | (qhp->attr.enable_stag0_fastreg << 3) | | ||
| 892 | (qhp->attr.enable_stag0_fastreg << 4); | ||
| 893 | #else | ||
| 894 | init_attr.qpcaps = 0x1f; | ||
| 895 | #endif | ||
| 896 | init_attr.tcp_emss = qhp->ep->emss; | 889 | init_attr.tcp_emss = qhp->ep->emss; |
| 897 | init_attr.ord = qhp->attr.max_ord; | 890 | init_attr.ord = qhp->attr.max_ord; |
| 898 | init_attr.ird = qhp->attr.max_ird; | 891 | init_attr.ird = qhp->attr.max_ird; |
| @@ -900,8 +893,6 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp, | |||
| 900 | init_attr.qp_dma_size = (1UL << qhp->wq.size_log2); | 893 | init_attr.qp_dma_size = (1UL << qhp->wq.size_log2); |
| 901 | init_attr.rqe_count = iwch_rqes_posted(qhp); | 894 | init_attr.rqe_count = iwch_rqes_posted(qhp); |
| 902 | init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0; | 895 | init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0; |
| 903 | if (!qhp->ibqp.uobject) | ||
| 904 | init_attr.flags |= PRIV_QP; | ||
| 905 | if (peer2peer) { | 896 | if (peer2peer) { |
| 906 | init_attr.rtr_type = RTR_READ; | 897 | init_attr.rtr_type = RTR_READ; |
| 907 | if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator) | 898 | if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator) |
diff --git a/drivers/infiniband/hw/ipath/ipath_driver.c b/drivers/infiniband/hw/ipath/ipath_driver.c index daad09a45910..ad0aab60b051 100644 --- a/drivers/infiniband/hw/ipath/ipath_driver.c +++ b/drivers/infiniband/hw/ipath/ipath_driver.c | |||
| @@ -1259,7 +1259,7 @@ reloop: | |||
| 1259 | */ | 1259 | */ |
| 1260 | ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf" | 1260 | ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf" |
| 1261 | " %x, len %x hdrq+%x rhf: %Lx\n", | 1261 | " %x, len %x hdrq+%x rhf: %Lx\n", |
| 1262 | etail, tlen, l, | 1262 | etail, tlen, l, (unsigned long long) |
| 1263 | le64_to_cpu(*(__le64 *) rhf_addr)); | 1263 | le64_to_cpu(*(__le64 *) rhf_addr)); |
| 1264 | if (ipath_debug & __IPATH_ERRPKTDBG) { | 1264 | if (ipath_debug & __IPATH_ERRPKTDBG) { |
| 1265 | u32 j, *d, dw = rsize-2; | 1265 | u32 j, *d, dw = rsize-2; |
| @@ -1457,7 +1457,8 @@ static void ipath_reset_availshadow(struct ipath_devdata *dd) | |||
| 1457 | 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */ | 1457 | 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */ |
| 1458 | if (oldval != dd->ipath_pioavailshadow[i]) | 1458 | if (oldval != dd->ipath_pioavailshadow[i]) |
| 1459 | ipath_dbg("shadow[%d] was %Lx, now %lx\n", | 1459 | ipath_dbg("shadow[%d] was %Lx, now %lx\n", |
| 1460 | i, oldval, dd->ipath_pioavailshadow[i]); | 1460 | i, (unsigned long long) oldval, |
| 1461 | dd->ipath_pioavailshadow[i]); | ||
| 1461 | } | 1462 | } |
| 1462 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); | 1463 | spin_unlock_irqrestore(&ipath_pioavail_lock, flags); |
| 1463 | } | 1464 | } |
diff --git a/drivers/infiniband/hw/ipath/ipath_iba7220.c b/drivers/infiniband/hw/ipath/ipath_iba7220.c index fadbfbf55a6a..d90f5e9a54fa 100644 --- a/drivers/infiniband/hw/ipath/ipath_iba7220.c +++ b/drivers/infiniband/hw/ipath/ipath_iba7220.c | |||
| @@ -1032,7 +1032,7 @@ static int ipath_7220_bringup_serdes(struct ipath_devdata *dd) | |||
| 1032 | ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n", | 1032 | ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n", |
| 1033 | (unsigned long long) | 1033 | (unsigned long long) |
| 1034 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig), | 1034 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig), |
| 1035 | prev_val); | 1035 | (unsigned long long) prev_val); |
| 1036 | 1036 | ||
| 1037 | guid = be64_to_cpu(dd->ipath_guid); | 1037 | guid = be64_to_cpu(dd->ipath_guid); |
| 1038 | 1038 | ||
| @@ -1042,7 +1042,8 @@ static int ipath_7220_bringup_serdes(struct ipath_devdata *dd) | |||
| 1042 | ipath_dbg("No GUID for heartbeat, faking %llx\n", | 1042 | ipath_dbg("No GUID for heartbeat, faking %llx\n", |
| 1043 | (unsigned long long)guid); | 1043 | (unsigned long long)guid); |
| 1044 | } else | 1044 | } else |
| 1045 | ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n", guid); | 1045 | ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n", |
| 1046 | (unsigned long long) guid); | ||
| 1046 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid); | 1047 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid); |
| 1047 | return ret; | 1048 | return ret; |
| 1048 | } | 1049 | } |
| @@ -2505,7 +2506,7 @@ done: | |||
| 2505 | if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) { | 2506 | if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) { |
| 2506 | ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n", | 2507 | ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n", |
| 2507 | ipath_ib_state(dd, dd->ipath_lastibcstat), | 2508 | ipath_ib_state(dd, dd->ipath_lastibcstat), |
| 2508 | jiffies_to_msecs(jiffies)-startms); | 2509 | (unsigned long long) jiffies_to_msecs(jiffies)-startms); |
| 2509 | dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG; | 2510 | dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG; |
| 2510 | if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) { | 2511 | if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) { |
| 2511 | dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED; | 2512 | dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED; |
diff --git a/drivers/infiniband/hw/ipath/ipath_intr.c b/drivers/infiniband/hw/ipath/ipath_intr.c index 26900b3b7a4e..6c21b4b5ec71 100644 --- a/drivers/infiniband/hw/ipath/ipath_intr.c +++ b/drivers/infiniband/hw/ipath/ipath_intr.c | |||
| @@ -356,9 +356,10 @@ static void handle_e_ibstatuschanged(struct ipath_devdata *dd, | |||
| 356 | dd->ipath_cregs->cr_iblinkerrrecovcnt); | 356 | dd->ipath_cregs->cr_iblinkerrrecovcnt); |
| 357 | if (linkrecov != dd->ipath_lastlinkrecov) { | 357 | if (linkrecov != dd->ipath_lastlinkrecov) { |
| 358 | ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n", | 358 | ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n", |
| 359 | ibcs, ib_linkstate(dd, ibcs), | 359 | (unsigned long long) ibcs, |
| 360 | ib_linkstate(dd, ibcs), | ||
| 360 | ipath_ibcstatus_str[ltstate], | 361 | ipath_ibcstatus_str[ltstate], |
| 361 | linkrecov); | 362 | (unsigned long long) linkrecov); |
| 362 | /* and no more until active again */ | 363 | /* and no more until active again */ |
| 363 | dd->ipath_lastlinkrecov = 0; | 364 | dd->ipath_lastlinkrecov = 0; |
| 364 | ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); | 365 | ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); |
| @@ -1118,9 +1119,11 @@ irqreturn_t ipath_intr(int irq, void *data) | |||
| 1118 | if (unlikely(istat & ~dd->ipath_i_bitsextant)) | 1119 | if (unlikely(istat & ~dd->ipath_i_bitsextant)) |
| 1119 | ipath_dev_err(dd, | 1120 | ipath_dev_err(dd, |
| 1120 | "interrupt with unknown interrupts %Lx set\n", | 1121 | "interrupt with unknown interrupts %Lx set\n", |
| 1122 | (unsigned long long) | ||
| 1121 | istat & ~dd->ipath_i_bitsextant); | 1123 | istat & ~dd->ipath_i_bitsextant); |
| 1122 | else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */ | 1124 | else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */ |
| 1123 | ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n", istat); | 1125 | ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n", |
| 1126 | (unsigned long long) istat); | ||
| 1124 | 1127 | ||
| 1125 | if (istat & INFINIPATH_I_ERROR) { | 1128 | if (istat & INFINIPATH_I_ERROR) { |
| 1126 | ipath_stats.sps_errints++; | 1129 | ipath_stats.sps_errints++; |
| @@ -1128,7 +1131,8 @@ irqreturn_t ipath_intr(int irq, void *data) | |||
| 1128 | dd->ipath_kregs->kr_errorstatus); | 1131 | dd->ipath_kregs->kr_errorstatus); |
| 1129 | if (!estat) | 1132 | if (!estat) |
| 1130 | dev_info(&dd->pcidev->dev, "error interrupt (%Lx), " | 1133 | dev_info(&dd->pcidev->dev, "error interrupt (%Lx), " |
| 1131 | "but no error bits set!\n", istat); | 1134 | "but no error bits set!\n", |
| 1135 | (unsigned long long) istat); | ||
| 1132 | else if (estat == -1LL) | 1136 | else if (estat == -1LL) |
| 1133 | /* | 1137 | /* |
| 1134 | * should we try clearing all, or hope next read | 1138 | * should we try clearing all, or hope next read |
diff --git a/drivers/infiniband/hw/ipath/ipath_verbs.c b/drivers/infiniband/hw/ipath/ipath_verbs.c index 55c718828826..b766e40e9ebf 100644 --- a/drivers/infiniband/hw/ipath/ipath_verbs.c +++ b/drivers/infiniband/hw/ipath/ipath_verbs.c | |||
| @@ -1021,7 +1021,7 @@ static void sdma_complete(void *cookie, int status) | |||
| 1021 | struct ipath_verbs_txreq *tx = cookie; | 1021 | struct ipath_verbs_txreq *tx = cookie; |
| 1022 | struct ipath_qp *qp = tx->qp; | 1022 | struct ipath_qp *qp = tx->qp; |
| 1023 | struct ipath_ibdev *dev = to_idev(qp->ibqp.device); | 1023 | struct ipath_ibdev *dev = to_idev(qp->ibqp.device); |
| 1024 | unsigned int flags; | 1024 | unsigned long flags; |
| 1025 | enum ib_wc_status ibs = status == IPATH_SDMA_TXREQ_S_OK ? | 1025 | enum ib_wc_status ibs = status == IPATH_SDMA_TXREQ_S_OK ? |
| 1026 | IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR; | 1026 | IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR; |
| 1027 | 1027 | ||
| @@ -1051,7 +1051,7 @@ static void sdma_complete(void *cookie, int status) | |||
| 1051 | 1051 | ||
| 1052 | static void decrement_dma_busy(struct ipath_qp *qp) | 1052 | static void decrement_dma_busy(struct ipath_qp *qp) |
| 1053 | { | 1053 | { |
| 1054 | unsigned int flags; | 1054 | unsigned long flags; |
| 1055 | 1055 | ||
| 1056 | if (atomic_dec_and_test(&qp->s_dma_busy)) { | 1056 | if (atomic_dec_and_test(&qp->s_dma_busy)) { |
| 1057 | spin_lock_irqsave(&qp->s_lock, flags); | 1057 | spin_lock_irqsave(&qp->s_lock, flags); |
| @@ -1221,7 +1221,7 @@ static int ipath_verbs_send_pio(struct ipath_qp *qp, | |||
| 1221 | unsigned flush_wc; | 1221 | unsigned flush_wc; |
| 1222 | u32 control; | 1222 | u32 control; |
| 1223 | int ret; | 1223 | int ret; |
| 1224 | unsigned int flags; | 1224 | unsigned long flags; |
| 1225 | 1225 | ||
| 1226 | piobuf = ipath_getpiobuf(dd, plen, NULL); | 1226 | piobuf = ipath_getpiobuf(dd, plen, NULL); |
| 1227 | if (unlikely(piobuf == NULL)) { | 1227 | if (unlikely(piobuf == NULL)) { |
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c index a1464574bfdd..d0866a3636e2 100644 --- a/drivers/infiniband/hw/mlx4/cq.c +++ b/drivers/infiniband/hw/mlx4/cq.c | |||
| @@ -515,17 +515,17 @@ static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, | |||
| 515 | wc->vendor_err = cqe->vendor_err_syndrome; | 515 | wc->vendor_err = cqe->vendor_err_syndrome; |
| 516 | } | 516 | } |
| 517 | 517 | ||
| 518 | static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum) | 518 | static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) |
| 519 | { | 519 | { |
| 520 | return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | | 520 | return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | |
| 521 | MLX4_CQE_IPOIB_STATUS_IPV4F | | 521 | MLX4_CQE_STATUS_IPV4F | |
| 522 | MLX4_CQE_IPOIB_STATUS_IPV4OPT | | 522 | MLX4_CQE_STATUS_IPV4OPT | |
| 523 | MLX4_CQE_IPOIB_STATUS_IPV6 | | 523 | MLX4_CQE_STATUS_IPV6 | |
| 524 | MLX4_CQE_IPOIB_STATUS_IPOK)) == | 524 | MLX4_CQE_STATUS_IPOK)) == |
| 525 | cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | | 525 | cpu_to_be16(MLX4_CQE_STATUS_IPV4 | |
| 526 | MLX4_CQE_IPOIB_STATUS_IPOK)) && | 526 | MLX4_CQE_STATUS_IPOK)) && |
| 527 | (status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP | | 527 | (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | |
| 528 | MLX4_CQE_IPOIB_STATUS_TCP)) && | 528 | MLX4_CQE_STATUS_TCP)) && |
| 529 | checksum == cpu_to_be16(0xffff); | 529 | checksum == cpu_to_be16(0xffff); |
| 530 | } | 530 | } |
| 531 | 531 | ||
| @@ -582,17 +582,17 @@ repoll: | |||
| 582 | } | 582 | } |
| 583 | 583 | ||
| 584 | if (!*cur_qp || | 584 | if (!*cur_qp || |
| 585 | (be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) { | 585 | (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { |
| 586 | /* | 586 | /* |
| 587 | * We do not have to take the QP table lock here, | 587 | * We do not have to take the QP table lock here, |
| 588 | * because CQs will be locked while QPs are removed | 588 | * because CQs will be locked while QPs are removed |
| 589 | * from the table. | 589 | * from the table. |
| 590 | */ | 590 | */ |
| 591 | mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, | 591 | mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, |
| 592 | be32_to_cpu(cqe->my_qpn)); | 592 | be32_to_cpu(cqe->vlan_my_qpn)); |
| 593 | if (unlikely(!mqp)) { | 593 | if (unlikely(!mqp)) { |
| 594 | printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n", | 594 | printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n", |
| 595 | cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff); | 595 | cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK); |
| 596 | return -EINVAL; | 596 | return -EINVAL; |
| 597 | } | 597 | } |
| 598 | 598 | ||
| @@ -692,14 +692,13 @@ repoll: | |||
| 692 | } | 692 | } |
| 693 | 693 | ||
| 694 | wc->slid = be16_to_cpu(cqe->rlid); | 694 | wc->slid = be16_to_cpu(cqe->rlid); |
| 695 | wc->sl = cqe->sl >> 4; | 695 | wc->sl = be16_to_cpu(cqe->sl_vid >> 12); |
| 696 | g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); | 696 | g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); |
| 697 | wc->src_qp = g_mlpath_rqpn & 0xffffff; | 697 | wc->src_qp = g_mlpath_rqpn & 0xffffff; |
| 698 | wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; | 698 | wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; |
| 699 | wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; | 699 | wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; |
| 700 | wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; | 700 | wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; |
| 701 | wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status, | 701 | wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum); |
| 702 | cqe->checksum); | ||
| 703 | } | 702 | } |
| 704 | 703 | ||
| 705 | return 0; | 704 | return 0; |
| @@ -767,7 +766,7 @@ void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |||
| 767 | */ | 766 | */ |
| 768 | while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { | 767 | while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { |
| 769 | cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); | 768 | cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); |
| 770 | if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) { | 769 | if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { |
| 771 | if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) | 770 | if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) |
| 772 | mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); | 771 | mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); |
| 773 | ++nfreed; | 772 | ++nfreed; |
diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index f7bc7dd8578a..f29dbb767e87 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c | |||
| @@ -902,7 +902,7 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, | |||
| 902 | context->mtu_msgmax = (IB_MTU_4096 << 5) | | 902 | context->mtu_msgmax = (IB_MTU_4096 << 5) | |
| 903 | ilog2(dev->dev->caps.max_gso_sz); | 903 | ilog2(dev->dev->caps.max_gso_sz); |
| 904 | else | 904 | else |
| 905 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; | 905 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; |
| 906 | } else if (attr_mask & IB_QP_PATH_MTU) { | 906 | } else if (attr_mask & IB_QP_PATH_MTU) { |
| 907 | if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { | 907 | if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { |
| 908 | printk(KERN_ERR "path MTU (%u) is invalid\n", | 908 | printk(KERN_ERR "path MTU (%u) is invalid\n", |
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c index 0f2d3045061a..7ebc400a4b3d 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c | |||
| @@ -337,7 +337,7 @@ static void ipoib_cm_init_rx_wr(struct net_device *dev, | |||
| 337 | sge[i].length = PAGE_SIZE; | 337 | sge[i].length = PAGE_SIZE; |
| 338 | 338 | ||
| 339 | wr->next = NULL; | 339 | wr->next = NULL; |
| 340 | wr->sg_list = priv->cm.rx_sge; | 340 | wr->sg_list = sge; |
| 341 | wr->num_sge = priv->cm.num_frags; | 341 | wr->num_sge = priv->cm.num_frags; |
| 342 | } | 342 | } |
| 343 | 343 | ||
diff --git a/drivers/input/serio/i8042-sparcio.h b/drivers/input/serio/i8042-sparcio.h index d9ca55891cd7..66bafe308b0c 100644 --- a/drivers/input/serio/i8042-sparcio.h +++ b/drivers/input/serio/i8042-sparcio.h | |||
| @@ -41,6 +41,8 @@ static inline void i8042_write_command(int val) | |||
| 41 | writeb(val, kbd_iobase + 0x64UL); | 41 | writeb(val, kbd_iobase + 0x64UL); |
| 42 | } | 42 | } |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_PCI | ||
| 45 | |||
| 44 | #define OBP_PS2KBD_NAME1 "kb_ps2" | 46 | #define OBP_PS2KBD_NAME1 "kb_ps2" |
| 45 | #define OBP_PS2KBD_NAME2 "keyboard" | 47 | #define OBP_PS2KBD_NAME2 "keyboard" |
| 46 | #define OBP_PS2MS_NAME1 "kdmouse" | 48 | #define OBP_PS2MS_NAME1 "kdmouse" |
| @@ -101,9 +103,6 @@ static struct of_platform_driver sparc_i8042_driver = { | |||
| 101 | 103 | ||
| 102 | static int __init i8042_platform_init(void) | 104 | static int __init i8042_platform_init(void) |
| 103 | { | 105 | { |
| 104 | #ifndef CONFIG_PCI | ||
| 105 | return -ENODEV; | ||
| 106 | #else | ||
| 107 | struct device_node *root = of_find_node_by_path("/"); | 106 | struct device_node *root = of_find_node_by_path("/"); |
| 108 | 107 | ||
| 109 | if (!strcmp(root->name, "SUNW,JavaStation-1")) { | 108 | if (!strcmp(root->name, "SUNW,JavaStation-1")) { |
| @@ -131,17 +130,25 @@ static int __init i8042_platform_init(void) | |||
| 131 | i8042_reset = 1; | 130 | i8042_reset = 1; |
| 132 | 131 | ||
| 133 | return 0; | 132 | return 0; |
| 134 | #endif /* CONFIG_PCI */ | ||
| 135 | } | 133 | } |
| 136 | 134 | ||
| 137 | static inline void i8042_platform_exit(void) | 135 | static inline void i8042_platform_exit(void) |
| 138 | { | 136 | { |
| 139 | #ifdef CONFIG_PCI | ||
| 140 | struct device_node *root = of_find_node_by_path("/"); | 137 | struct device_node *root = of_find_node_by_path("/"); |
| 141 | 138 | ||
| 142 | if (strcmp(root->name, "SUNW,JavaStation-1")) | 139 | if (strcmp(root->name, "SUNW,JavaStation-1")) |
| 143 | of_unregister_driver(&sparc_i8042_driver); | 140 | of_unregister_driver(&sparc_i8042_driver); |
| 144 | #endif | ||
| 145 | } | 141 | } |
| 146 | 142 | ||
| 143 | #else /* !CONFIG_PCI */ | ||
| 144 | static int __init i8042_platform_init(void) | ||
| 145 | { | ||
| 146 | return -ENODEV; | ||
| 147 | } | ||
| 148 | |||
| 149 | static inline void i8042_platform_exit(void) | ||
| 150 | { | ||
| 151 | } | ||
| 152 | #endif /* !CONFIG_PCI */ | ||
| 153 | |||
| 147 | #endif /* _I8042_SPARCIO_H */ | 154 | #endif /* _I8042_SPARCIO_H */ |
diff --git a/drivers/media/dvb/dvb-usb/cxusb.c b/drivers/media/dvb/dvb-usb/cxusb.c index 578afce6884c..aaa0b6f0b521 100644 --- a/drivers/media/dvb/dvb-usb/cxusb.c +++ b/drivers/media/dvb/dvb-usb/cxusb.c | |||
| @@ -565,7 +565,8 @@ static int cxusb_lgh064f_tuner_attach(struct dvb_usb_adapter *adap) | |||
| 565 | 565 | ||
| 566 | static int dvico_bluebird_xc2028_callback(void *ptr, int command, int arg) | 566 | static int dvico_bluebird_xc2028_callback(void *ptr, int command, int arg) |
| 567 | { | 567 | { |
| 568 | struct dvb_usb_device *d = ptr; | 568 | struct dvb_usb_adapter *adap = ptr; |
| 569 | struct dvb_usb_device *d = adap->dev; | ||
| 569 | 570 | ||
| 570 | switch (command) { | 571 | switch (command) { |
| 571 | case XC2028_TUNER_RESET: | 572 | case XC2028_TUNER_RESET: |
| @@ -593,9 +594,9 @@ static int cxusb_dvico_xc3028_tuner_attach(struct dvb_usb_adapter *adap) | |||
| 593 | .callback = dvico_bluebird_xc2028_callback, | 594 | .callback = dvico_bluebird_xc2028_callback, |
| 594 | }; | 595 | }; |
| 595 | static struct xc2028_ctrl ctl = { | 596 | static struct xc2028_ctrl ctl = { |
| 596 | .fname = "xc3028-dvico-au-01.fw", | 597 | .fname = "xc3028-v27.fw", |
| 597 | .max_len = 64, | 598 | .max_len = 64, |
| 598 | .scode_table = XC3028_FE_ZARLINK456, | 599 | .demod = XC3028_FE_ZARLINK456, |
| 599 | }; | 600 | }; |
| 600 | 601 | ||
| 601 | fe = dvb_attach(xc2028_attach, adap->fe, &cfg); | 602 | fe = dvb_attach(xc2028_attach, adap->fe, &cfg); |
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 574dffe91b68..7dbb4a223c99 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig | |||
| @@ -135,9 +135,8 @@ config DVB_CX22702 | |||
| 135 | 135 | ||
| 136 | config DVB_DRX397XD | 136 | config DVB_DRX397XD |
| 137 | tristate "Micronas DRX3975D/DRX3977D based" | 137 | tristate "Micronas DRX3975D/DRX3977D based" |
| 138 | depends on DVB_CORE && I2C && HOTPLUG | 138 | depends on DVB_CORE && I2C |
| 139 | default m if DVB_FE_CUSTOMISE | 139 | default m if DVB_FE_CUSTOMISE |
| 140 | select FW_LOADER | ||
| 141 | help | 140 | help |
| 142 | A DVB-T tuner module. Say Y when you want to support this frontend. | 141 | A DVB-T tuner module. Say Y when you want to support this frontend. |
| 143 | 142 | ||
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index d4a6e56a7135..ecbfa1b39b70 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig | |||
| @@ -630,7 +630,7 @@ config VIDEO_ZORAN_ZR36060 | |||
| 630 | depends on VIDEO_ZORAN | 630 | depends on VIDEO_ZORAN |
| 631 | help | 631 | help |
| 632 | Say Y to support Zoran boards based on 36060 chips. | 632 | Say Y to support Zoran boards based on 36060 chips. |
| 633 | This includes Iomega Bus, Pinnacle DC10, Linux media Labs 33 | 633 | This includes Iomega Buz, Pinnacle DC10, Linux media Labs 33 |
| 634 | and 33 R10 and AverMedia 6 boards. | 634 | and 33 R10 and AverMedia 6 boards. |
| 635 | 635 | ||
| 636 | config VIDEO_ZORAN_BUZ | 636 | config VIDEO_ZORAN_BUZ |
diff --git a/drivers/media/video/arv.c b/drivers/media/video/arv.c index 56ebfd5ef6fa..9e436ad3d34b 100644 --- a/drivers/media/video/arv.c +++ b/drivers/media/video/arv.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/sched.h> | 29 | #include <linux/sched.h> |
| 30 | #include <linux/videodev.h> | 30 | #include <linux/videodev.h> |
| 31 | #include <media/v4l2-common.h> | 31 | #include <media/v4l2-common.h> |
| 32 | #include <media/v4l2-ioctl.h> | ||
| 32 | #include <linux/mutex.h> | 33 | #include <linux/mutex.h> |
| 33 | 34 | ||
| 34 | #include <asm/uaccess.h> | 35 | #include <asm/uaccess.h> |
| @@ -755,7 +756,6 @@ static const struct file_operations ar_fops = { | |||
| 755 | 756 | ||
| 756 | static struct video_device ar_template = { | 757 | static struct video_device ar_template = { |
| 757 | .name = "Colour AR VGA", | 758 | .name = "Colour AR VGA", |
| 758 | .type = VID_TYPE_CAPTURE, | ||
| 759 | .fops = &ar_fops, | 759 | .fops = &ar_fops, |
| 760 | .release = ar_release, | 760 | .release = ar_release, |
| 761 | .minor = -1, | 761 | .minor = -1, |
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c index 476ae44a62d2..452da70e719f 100644 --- a/drivers/media/video/em28xx/em28xx-cards.c +++ b/drivers/media/video/em28xx/em28xx-cards.c | |||
| @@ -1015,6 +1015,7 @@ struct em28xx_board em28xx_boards[] = { | |||
| 1015 | .valid = EM28XX_BOARD_NOT_VALIDATED, | 1015 | .valid = EM28XX_BOARD_NOT_VALIDATED, |
| 1016 | .vchannels = 3, | 1016 | .vchannels = 3, |
| 1017 | .tuner_type = TUNER_XC2028, | 1017 | .tuner_type = TUNER_XC2028, |
| 1018 | .mts_firmware = 1, | ||
| 1018 | .decoder = EM28XX_TVP5150, | 1019 | .decoder = EM28XX_TVP5150, |
| 1019 | .input = { { | 1020 | .input = { { |
| 1020 | .type = EM28XX_VMUX_TELEVISION, | 1021 | .type = EM28XX_VMUX_TELEVISION, |
diff --git a/drivers/media/video/gspca/conex.c b/drivers/media/video/gspca/conex.c index 44b0bffeb20e..cd3a3f5829b2 100644 --- a/drivers/media/video/gspca/conex.c +++ b/drivers/media/video/gspca/conex.c | |||
| @@ -123,7 +123,7 @@ static void reg_r(struct gspca_dev *gspca_dev, | |||
| 123 | { | 123 | { |
| 124 | struct usb_device *dev = gspca_dev->dev; | 124 | struct usb_device *dev = gspca_dev->dev; |
| 125 | 125 | ||
| 126 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 126 | #ifdef GSPCA_DEBUG |
| 127 | if (len > sizeof gspca_dev->usb_buf) { | 127 | if (len > sizeof gspca_dev->usb_buf) { |
| 128 | err("reg_r: buffer overflow"); | 128 | err("reg_r: buffer overflow"); |
| 129 | return; | 129 | return; |
| @@ -163,7 +163,7 @@ static void reg_w(struct gspca_dev *gspca_dev, | |||
| 163 | { | 163 | { |
| 164 | struct usb_device *dev = gspca_dev->dev; | 164 | struct usb_device *dev = gspca_dev->dev; |
| 165 | 165 | ||
| 166 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 166 | #ifdef GSPCA_DEBUG |
| 167 | if (len > sizeof gspca_dev->usb_buf) { | 167 | if (len > sizeof gspca_dev->usb_buf) { |
| 168 | err("reg_w: buffer overflow"); | 168 | err("reg_w: buffer overflow"); |
| 169 | return; | 169 | return; |
diff --git a/drivers/media/video/gspca/etoms.c b/drivers/media/video/gspca/etoms.c index c8c2f02fcf00..1dbe92d01e6a 100644 --- a/drivers/media/video/gspca/etoms.c +++ b/drivers/media/video/gspca/etoms.c | |||
| @@ -233,7 +233,7 @@ static void reg_r(struct gspca_dev *gspca_dev, | |||
| 233 | { | 233 | { |
| 234 | struct usb_device *dev = gspca_dev->dev; | 234 | struct usb_device *dev = gspca_dev->dev; |
| 235 | 235 | ||
| 236 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 236 | #ifdef GSPCA_DEBUG |
| 237 | if (len > sizeof gspca_dev->usb_buf) { | 237 | if (len > sizeof gspca_dev->usb_buf) { |
| 238 | err("reg_r: buffer overflow"); | 238 | err("reg_r: buffer overflow"); |
| 239 | return; | 239 | return; |
| @@ -271,7 +271,7 @@ static void reg_w(struct gspca_dev *gspca_dev, | |||
| 271 | { | 271 | { |
| 272 | struct usb_device *dev = gspca_dev->dev; | 272 | struct usb_device *dev = gspca_dev->dev; |
| 273 | 273 | ||
| 274 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 274 | #ifdef GSPCA_DEBUG |
| 275 | if (len > sizeof gspca_dev->usb_buf) { | 275 | if (len > sizeof gspca_dev->usb_buf) { |
| 276 | err("reg_w: buffer overflow"); | 276 | err("reg_w: buffer overflow"); |
| 277 | return; | 277 | return; |
| @@ -461,6 +461,52 @@ static void Et_init2(struct gspca_dev *gspca_dev) | |||
| 461 | reg_w_val(gspca_dev, 0x80, 0x20); /* 0x20; */ | 461 | reg_w_val(gspca_dev, 0x80, 0x20); /* 0x20; */ |
| 462 | } | 462 | } |
| 463 | 463 | ||
| 464 | static void setbrightness(struct gspca_dev *gspca_dev) | ||
| 465 | { | ||
| 466 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 467 | int i; | ||
| 468 | __u8 brightness = sd->brightness; | ||
| 469 | |||
| 470 | for (i = 0; i < 4; i++) | ||
| 471 | reg_w_val(gspca_dev, ET_O_RED + i, brightness); | ||
| 472 | } | ||
| 473 | |||
| 474 | static void getbrightness(struct gspca_dev *gspca_dev) | ||
| 475 | { | ||
| 476 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 477 | int i; | ||
| 478 | int brightness = 0; | ||
| 479 | |||
| 480 | for (i = 0; i < 4; i++) { | ||
| 481 | reg_r(gspca_dev, ET_O_RED + i, 1); | ||
| 482 | brightness += gspca_dev->usb_buf[0]; | ||
| 483 | } | ||
| 484 | sd->brightness = brightness >> 3; | ||
| 485 | } | ||
| 486 | |||
| 487 | static void setcontrast(struct gspca_dev *gspca_dev) | ||
| 488 | { | ||
| 489 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 490 | __u8 RGBG[] = { 0x80, 0x80, 0x80, 0x80, 0x00, 0x00 }; | ||
| 491 | __u8 contrast = sd->contrast; | ||
| 492 | |||
| 493 | memset(RGBG, contrast, sizeof(RGBG) - 2); | ||
| 494 | reg_w(gspca_dev, ET_G_RED, RGBG, 6); | ||
| 495 | } | ||
| 496 | |||
| 497 | static void getcontrast(struct gspca_dev *gspca_dev) | ||
| 498 | { | ||
| 499 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 500 | int i; | ||
| 501 | int contrast = 0; | ||
| 502 | |||
| 503 | for (i = 0; i < 4; i++) { | ||
| 504 | reg_r(gspca_dev, ET_G_RED + i, 1); | ||
| 505 | contrast += gspca_dev->usb_buf[0]; | ||
| 506 | } | ||
| 507 | sd->contrast = contrast >> 2; | ||
| 508 | } | ||
| 509 | |||
| 464 | static void setcolors(struct gspca_dev *gspca_dev) | 510 | static void setcolors(struct gspca_dev *gspca_dev) |
| 465 | { | 511 | { |
| 466 | struct sd *sd = (struct sd *) gspca_dev; | 512 | struct sd *sd = (struct sd *) gspca_dev; |
| @@ -492,6 +538,16 @@ static void getcolors(struct gspca_dev *gspca_dev) | |||
| 492 | } | 538 | } |
| 493 | } | 539 | } |
| 494 | 540 | ||
| 541 | static void setautogain(struct gspca_dev *gspca_dev) | ||
| 542 | { | ||
| 543 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 544 | |||
| 545 | if (sd->autogain) | ||
| 546 | sd->ag_cnt = AG_CNT_START; | ||
| 547 | else | ||
| 548 | sd->ag_cnt = -1; | ||
| 549 | } | ||
| 550 | |||
| 495 | static void Et_init1(struct gspca_dev *gspca_dev) | 551 | static void Et_init1(struct gspca_dev *gspca_dev) |
| 496 | { | 552 | { |
| 497 | __u8 value; | 553 | __u8 value; |
| @@ -614,6 +670,7 @@ static int sd_config(struct gspca_dev *gspca_dev, | |||
| 614 | sd->contrast = CONTRAST_DEF; | 670 | sd->contrast = CONTRAST_DEF; |
| 615 | sd->colors = COLOR_DEF; | 671 | sd->colors = COLOR_DEF; |
| 616 | sd->autogain = AUTOGAIN_DEF; | 672 | sd->autogain = AUTOGAIN_DEF; |
| 673 | sd->ag_cnt = -1; | ||
| 617 | return 0; | 674 | return 0; |
| 618 | } | 675 | } |
| 619 | 676 | ||
| @@ -641,6 +698,8 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 641 | else | 698 | else |
| 642 | Et_init2(gspca_dev); | 699 | Et_init2(gspca_dev); |
| 643 | 700 | ||
| 701 | setautogain(gspca_dev); | ||
| 702 | |||
| 644 | reg_w_val(gspca_dev, ET_RESET_ALL, 0x08); | 703 | reg_w_val(gspca_dev, ET_RESET_ALL, 0x08); |
| 645 | et_video(gspca_dev, 1); /* video on */ | 704 | et_video(gspca_dev, 1); /* video on */ |
| 646 | } | 705 | } |
| @@ -658,52 +717,6 @@ static void sd_close(struct gspca_dev *gspca_dev) | |||
| 658 | { | 717 | { |
| 659 | } | 718 | } |
| 660 | 719 | ||
| 661 | static void setbrightness(struct gspca_dev *gspca_dev) | ||
| 662 | { | ||
| 663 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 664 | int i; | ||
| 665 | __u8 brightness = sd->brightness; | ||
| 666 | |||
| 667 | for (i = 0; i < 4; i++) | ||
| 668 | reg_w_val(gspca_dev, ET_O_RED + i, brightness); | ||
| 669 | } | ||
| 670 | |||
| 671 | static void getbrightness(struct gspca_dev *gspca_dev) | ||
| 672 | { | ||
| 673 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 674 | int i; | ||
| 675 | int brightness = 0; | ||
| 676 | |||
| 677 | for (i = 0; i < 4; i++) { | ||
| 678 | reg_r(gspca_dev, ET_O_RED + i, 1); | ||
| 679 | brightness += gspca_dev->usb_buf[0]; | ||
| 680 | } | ||
| 681 | sd->brightness = brightness >> 3; | ||
| 682 | } | ||
| 683 | |||
| 684 | static void setcontrast(struct gspca_dev *gspca_dev) | ||
| 685 | { | ||
| 686 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 687 | __u8 RGBG[] = { 0x80, 0x80, 0x80, 0x80, 0x00, 0x00 }; | ||
| 688 | __u8 contrast = sd->contrast; | ||
| 689 | |||
| 690 | memset(RGBG, contrast, sizeof(RGBG) - 2); | ||
| 691 | reg_w(gspca_dev, ET_G_RED, RGBG, 6); | ||
| 692 | } | ||
| 693 | |||
| 694 | static void getcontrast(struct gspca_dev *gspca_dev) | ||
| 695 | { | ||
| 696 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 697 | int i; | ||
| 698 | int contrast = 0; | ||
| 699 | |||
| 700 | for (i = 0; i < 4; i++) { | ||
| 701 | reg_r(gspca_dev, ET_G_RED + i, 1); | ||
| 702 | contrast += gspca_dev->usb_buf[0]; | ||
| 703 | } | ||
| 704 | sd->contrast = contrast >> 2; | ||
| 705 | } | ||
| 706 | |||
| 707 | static __u8 Et_getgainG(struct gspca_dev *gspca_dev) | 720 | static __u8 Et_getgainG(struct gspca_dev *gspca_dev) |
| 708 | { | 721 | { |
| 709 | struct sd *sd = (struct sd *) gspca_dev; | 722 | struct sd *sd = (struct sd *) gspca_dev; |
| @@ -733,15 +746,22 @@ static void Et_setgainG(struct gspca_dev *gspca_dev, __u8 gain) | |||
| 733 | #define LIMIT(color) \ | 746 | #define LIMIT(color) \ |
| 734 | (unsigned char)((color > 0xff)?0xff:((color < 0)?0:color)) | 747 | (unsigned char)((color > 0xff)?0xff:((color < 0)?0:color)) |
| 735 | 748 | ||
| 736 | static void setautogain(struct gspca_dev *gspca_dev) | 749 | static void do_autogain(struct gspca_dev *gspca_dev) |
| 737 | { | 750 | { |
| 738 | __u8 luma = 0; | 751 | struct sd *sd = (struct sd *) gspca_dev; |
| 752 | __u8 luma; | ||
| 739 | __u8 luma_mean = 128; | 753 | __u8 luma_mean = 128; |
| 740 | __u8 luma_delta = 20; | 754 | __u8 luma_delta = 20; |
| 741 | __u8 spring = 4; | 755 | __u8 spring = 4; |
| 742 | int Gbright = 0; | 756 | int Gbright; |
| 743 | __u8 r, g, b; | 757 | __u8 r, g, b; |
| 744 | 758 | ||
| 759 | if (sd->ag_cnt < 0) | ||
| 760 | return; | ||
| 761 | if (--sd->ag_cnt >= 0) | ||
| 762 | return; | ||
| 763 | sd->ag_cnt = AG_CNT_START; | ||
| 764 | |||
| 745 | Gbright = Et_getgainG(gspca_dev); | 765 | Gbright = Et_getgainG(gspca_dev); |
| 746 | reg_r(gspca_dev, ET_LUMA_CENTER, 4); | 766 | reg_r(gspca_dev, ET_LUMA_CENTER, 4); |
| 747 | g = (gspca_dev->usb_buf[0] + gspca_dev->usb_buf[3]) >> 1; | 767 | g = (gspca_dev->usb_buf[0] + gspca_dev->usb_buf[3]) >> 1; |
| @@ -768,7 +788,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 768 | __u8 *data, /* isoc packet */ | 788 | __u8 *data, /* isoc packet */ |
| 769 | int len) /* iso packet length */ | 789 | int len) /* iso packet length */ |
| 770 | { | 790 | { |
| 771 | struct sd *sd; | ||
| 772 | int seqframe; | 791 | int seqframe; |
| 773 | 792 | ||
| 774 | seqframe = data[0] & 0x3f; | 793 | seqframe = data[0] & 0x3f; |
| @@ -783,13 +802,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 783 | frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, | 802 | frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, |
| 784 | data, 0); | 803 | data, 0); |
| 785 | gspca_frame_add(gspca_dev, FIRST_PACKET, frame, data, len); | 804 | gspca_frame_add(gspca_dev, FIRST_PACKET, frame, data, len); |
| 786 | sd = (struct sd *) gspca_dev; | ||
| 787 | if (sd->ag_cnt >= 0) { | ||
| 788 | if (--sd->ag_cnt < 0) { | ||
| 789 | sd->ag_cnt = AG_CNT_START; | ||
| 790 | setautogain(gspca_dev); | ||
| 791 | } | ||
| 792 | } | ||
| 793 | return; | 805 | return; |
| 794 | } | 806 | } |
| 795 | if (len) { | 807 | if (len) { |
| @@ -862,10 +874,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) | |||
| 862 | struct sd *sd = (struct sd *) gspca_dev; | 874 | struct sd *sd = (struct sd *) gspca_dev; |
| 863 | 875 | ||
| 864 | sd->autogain = val; | 876 | sd->autogain = val; |
| 865 | if (val) | 877 | if (gspca_dev->streaming) |
| 866 | sd->ag_cnt = AG_CNT_START; | 878 | setautogain(gspca_dev); |
| 867 | else | ||
| 868 | sd->ag_cnt = -1; | ||
| 869 | return 0; | 879 | return 0; |
| 870 | } | 880 | } |
| 871 | 881 | ||
| @@ -889,6 +899,7 @@ static struct sd_desc sd_desc = { | |||
| 889 | .stop0 = sd_stop0, | 899 | .stop0 = sd_stop0, |
| 890 | .close = sd_close, | 900 | .close = sd_close, |
| 891 | .pkt_scan = sd_pkt_scan, | 901 | .pkt_scan = sd_pkt_scan, |
| 902 | .dq_callback = do_autogain, | ||
| 892 | }; | 903 | }; |
| 893 | 904 | ||
| 894 | /* -- module initialisation -- */ | 905 | /* -- module initialisation -- */ |
diff --git a/drivers/media/video/gspca/gspca.c b/drivers/media/video/gspca/gspca.c index 3a051c925ff6..15d302b28b79 100644 --- a/drivers/media/video/gspca/gspca.c +++ b/drivers/media/video/gspca/gspca.c | |||
| @@ -47,7 +47,7 @@ MODULE_LICENSE("GPL"); | |||
| 47 | 47 | ||
| 48 | static int video_nr = -1; | 48 | static int video_nr = -1; |
| 49 | 49 | ||
| 50 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 50 | #ifdef GSPCA_DEBUG |
| 51 | int gspca_debug = D_ERR | D_PROBE; | 51 | int gspca_debug = D_ERR | D_PROBE; |
| 52 | EXPORT_SYMBOL(gspca_debug); | 52 | EXPORT_SYMBOL(gspca_debug); |
| 53 | 53 | ||
| @@ -677,7 +677,7 @@ static int try_fmt_vid_cap(struct gspca_dev *gspca_dev, | |||
| 677 | w = fmt->fmt.pix.width; | 677 | w = fmt->fmt.pix.width; |
| 678 | h = fmt->fmt.pix.height; | 678 | h = fmt->fmt.pix.height; |
| 679 | 679 | ||
| 680 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 680 | #ifdef GSPCA_DEBUG |
| 681 | if (gspca_debug & D_CONF) | 681 | if (gspca_debug & D_CONF) |
| 682 | PDEBUG_MODE("try fmt cap", fmt->fmt.pix.pixelformat, w, h); | 682 | PDEBUG_MODE("try fmt cap", fmt->fmt.pix.pixelformat, w, h); |
| 683 | #endif | 683 | #endif |
| @@ -785,7 +785,7 @@ static int dev_open(struct inode *inode, struct file *file) | |||
| 785 | } | 785 | } |
| 786 | gspca_dev->users++; | 786 | gspca_dev->users++; |
| 787 | file->private_data = gspca_dev; | 787 | file->private_data = gspca_dev; |
| 788 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 788 | #ifdef GSPCA_DEBUG |
| 789 | /* activate the v4l2 debug */ | 789 | /* activate the v4l2 debug */ |
| 790 | if (gspca_debug & D_V4L2) | 790 | if (gspca_debug & D_V4L2) |
| 791 | gspca_dev->vdev.debug |= 3; | 791 | gspca_dev->vdev.debug |= 3; |
| @@ -904,7 +904,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, | |||
| 904 | if (ctrl->id != ctrls->qctrl.id) | 904 | if (ctrl->id != ctrls->qctrl.id) |
| 905 | continue; | 905 | continue; |
| 906 | if (ctrl->value < ctrls->qctrl.minimum | 906 | if (ctrl->value < ctrls->qctrl.minimum |
| 907 | && ctrl->value > ctrls->qctrl.maximum) | 907 | || ctrl->value > ctrls->qctrl.maximum) |
| 908 | return -ERANGE; | 908 | return -ERANGE; |
| 909 | PDEBUG(D_CONF, "set ctrl [%08x] = %d", ctrl->id, ctrl->value); | 909 | PDEBUG(D_CONF, "set ctrl [%08x] = %d", ctrl->id, ctrl->value); |
| 910 | if (mutex_lock_interruptible(&gspca_dev->usb_lock)) | 910 | if (mutex_lock_interruptible(&gspca_dev->usb_lock)) |
| @@ -1080,7 +1080,7 @@ static int vidioc_streamon(struct file *file, void *priv, | |||
| 1080 | if (ret < 0) | 1080 | if (ret < 0) |
| 1081 | goto out; | 1081 | goto out; |
| 1082 | } | 1082 | } |
| 1083 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 1083 | #ifdef GSPCA_DEBUG |
| 1084 | if (gspca_debug & D_STREAM) { | 1084 | if (gspca_debug & D_STREAM) { |
| 1085 | PDEBUG_MODE("stream on OK", | 1085 | PDEBUG_MODE("stream on OK", |
| 1086 | gspca_dev->pixfmt, | 1086 | gspca_dev->pixfmt, |
| @@ -1913,7 +1913,7 @@ static void __exit gspca_exit(void) | |||
| 1913 | module_init(gspca_init); | 1913 | module_init(gspca_init); |
| 1914 | module_exit(gspca_exit); | 1914 | module_exit(gspca_exit); |
| 1915 | 1915 | ||
| 1916 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 1916 | #ifdef GSPCA_DEBUG |
| 1917 | module_param_named(debug, gspca_debug, int, 0644); | 1917 | module_param_named(debug, gspca_debug, int, 0644); |
| 1918 | MODULE_PARM_DESC(debug, | 1918 | MODULE_PARM_DESC(debug, |
| 1919 | "Debug (bit) 0x01:error 0x02:probe 0x04:config" | 1919 | "Debug (bit) 0x01:error 0x02:probe 0x04:config" |
diff --git a/drivers/media/video/gspca/gspca.h b/drivers/media/video/gspca/gspca.h index 3fd2c4eee204..67e448940eaa 100644 --- a/drivers/media/video/gspca/gspca.h +++ b/drivers/media/video/gspca/gspca.h | |||
| @@ -9,7 +9,10 @@ | |||
| 9 | #include <media/v4l2-common.h> | 9 | #include <media/v4l2-common.h> |
| 10 | #include <linux/mutex.h> | 10 | #include <linux/mutex.h> |
| 11 | 11 | ||
| 12 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 12 | /* compilation option */ |
| 13 | #define GSPCA_DEBUG 1 | ||
| 14 | |||
| 15 | #ifdef GSPCA_DEBUG | ||
| 13 | /* GSPCA our debug messages */ | 16 | /* GSPCA our debug messages */ |
| 14 | extern int gspca_debug; | 17 | extern int gspca_debug; |
| 15 | #define PDEBUG(level, fmt, args...) \ | 18 | #define PDEBUG(level, fmt, args...) \ |
diff --git a/drivers/media/video/gspca/ov519.c b/drivers/media/video/gspca/ov519.c index 83139efc4629..b4f00ec0885c 100644 --- a/drivers/media/video/gspca/ov519.c +++ b/drivers/media/video/gspca/ov519.c | |||
| @@ -40,14 +40,15 @@ struct sd { | |||
| 40 | struct gspca_dev gspca_dev; /* !! must be the first item */ | 40 | struct gspca_dev gspca_dev; /* !! must be the first item */ |
| 41 | 41 | ||
| 42 | /* Determined by sensor type */ | 42 | /* Determined by sensor type */ |
| 43 | short maxwidth; | 43 | char sif; |
| 44 | short maxheight; | ||
| 45 | 44 | ||
| 46 | unsigned char primary_i2c_slave; /* I2C write id of sensor */ | 45 | unsigned char primary_i2c_slave; /* I2C write id of sensor */ |
| 47 | 46 | ||
| 48 | unsigned char brightness; | 47 | unsigned char brightness; |
| 49 | unsigned char contrast; | 48 | unsigned char contrast; |
| 50 | unsigned char colors; | 49 | unsigned char colors; |
| 50 | __u8 hflip; | ||
| 51 | __u8 vflip; | ||
| 51 | 52 | ||
| 52 | char compress; /* Should the next frame be compressed? */ | 53 | char compress; /* Should the next frame be compressed? */ |
| 53 | char compress_inited; /* Are compression params uploaded? */ | 54 | char compress_inited; /* Are compression params uploaded? */ |
| @@ -77,9 +78,12 @@ static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val); | |||
| 77 | static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val); | 78 | static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val); |
| 78 | static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val); | 79 | static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val); |
| 79 | static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val); | 80 | static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val); |
| 81 | static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val); | ||
| 82 | static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val); | ||
| 83 | static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val); | ||
| 84 | static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val); | ||
| 80 | 85 | ||
| 81 | static struct ctrl sd_ctrls[] = { | 86 | static struct ctrl sd_ctrls[] = { |
| 82 | #define SD_BRIGHTNESS 0 | ||
| 83 | { | 87 | { |
| 84 | { | 88 | { |
| 85 | .id = V4L2_CID_BRIGHTNESS, | 89 | .id = V4L2_CID_BRIGHTNESS, |
| @@ -88,12 +92,12 @@ static struct ctrl sd_ctrls[] = { | |||
| 88 | .minimum = 0, | 92 | .minimum = 0, |
| 89 | .maximum = 255, | 93 | .maximum = 255, |
| 90 | .step = 1, | 94 | .step = 1, |
| 91 | .default_value = 127, | 95 | #define BRIGHTNESS_DEF 127 |
| 96 | .default_value = BRIGHTNESS_DEF, | ||
| 92 | }, | 97 | }, |
| 93 | .set = sd_setbrightness, | 98 | .set = sd_setbrightness, |
| 94 | .get = sd_getbrightness, | 99 | .get = sd_getbrightness, |
| 95 | }, | 100 | }, |
| 96 | #define SD_CONTRAST 1 | ||
| 97 | { | 101 | { |
| 98 | { | 102 | { |
| 99 | .id = V4L2_CID_CONTRAST, | 103 | .id = V4L2_CID_CONTRAST, |
| @@ -102,31 +106,61 @@ static struct ctrl sd_ctrls[] = { | |||
| 102 | .minimum = 0, | 106 | .minimum = 0, |
| 103 | .maximum = 255, | 107 | .maximum = 255, |
| 104 | .step = 1, | 108 | .step = 1, |
| 105 | .default_value = 127, | 109 | #define CONTRAST_DEF 127 |
| 110 | .default_value = CONTRAST_DEF, | ||
| 106 | }, | 111 | }, |
| 107 | .set = sd_setcontrast, | 112 | .set = sd_setcontrast, |
| 108 | .get = sd_getcontrast, | 113 | .get = sd_getcontrast, |
| 109 | }, | 114 | }, |
| 110 | #define SD_COLOR 2 | ||
| 111 | { | 115 | { |
| 112 | { | 116 | { |
| 113 | .id = V4L2_CID_SATURATION, | 117 | .id = V4L2_CID_SATURATION, |
| 114 | .type = V4L2_CTRL_TYPE_INTEGER, | 118 | .type = V4L2_CTRL_TYPE_INTEGER, |
| 115 | .name = "Saturation", | 119 | .name = "Color", |
| 116 | .minimum = 0, | 120 | .minimum = 0, |
| 117 | .maximum = 255, | 121 | .maximum = 255, |
| 118 | .step = 1, | 122 | .step = 1, |
| 119 | .default_value = 127, | 123 | #define COLOR_DEF 127 |
| 124 | .default_value = COLOR_DEF, | ||
| 120 | }, | 125 | }, |
| 121 | .set = sd_setcolors, | 126 | .set = sd_setcolors, |
| 122 | .get = sd_getcolors, | 127 | .get = sd_getcolors, |
| 123 | }, | 128 | }, |
| 129 | /* next controls work with ov7670 only */ | ||
| 130 | { | ||
| 131 | { | ||
| 132 | .id = V4L2_CID_HFLIP, | ||
| 133 | .type = V4L2_CTRL_TYPE_BOOLEAN, | ||
| 134 | .name = "Mirror", | ||
| 135 | .minimum = 0, | ||
| 136 | .maximum = 1, | ||
| 137 | .step = 1, | ||
| 138 | #define HFLIP_DEF 0 | ||
| 139 | .default_value = HFLIP_DEF, | ||
| 140 | }, | ||
| 141 | .set = sd_sethflip, | ||
| 142 | .get = sd_gethflip, | ||
| 143 | }, | ||
| 144 | { | ||
| 145 | { | ||
| 146 | .id = V4L2_CID_VFLIP, | ||
| 147 | .type = V4L2_CTRL_TYPE_BOOLEAN, | ||
| 148 | .name = "Vflip", | ||
| 149 | .minimum = 0, | ||
| 150 | .maximum = 1, | ||
| 151 | .step = 1, | ||
| 152 | #define VFLIP_DEF 0 | ||
| 153 | .default_value = VFLIP_DEF, | ||
| 154 | }, | ||
| 155 | .set = sd_setvflip, | ||
| 156 | .get = sd_getvflip, | ||
| 157 | }, | ||
| 124 | }; | 158 | }; |
| 125 | 159 | ||
| 126 | static struct v4l2_pix_format vga_mode[] = { | 160 | static struct v4l2_pix_format vga_mode[] = { |
| 127 | {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, | 161 | {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, |
| 128 | .bytesperline = 320, | 162 | .bytesperline = 320, |
| 129 | .sizeimage = 320 * 240 * 3 / 8 + 589, | 163 | .sizeimage = 320 * 240 * 3 / 8 + 590, |
| 130 | .colorspace = V4L2_COLORSPACE_JPEG, | 164 | .colorspace = V4L2_COLORSPACE_JPEG, |
| 131 | .priv = 1}, | 165 | .priv = 1}, |
| 132 | {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, | 166 | {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, |
| @@ -138,12 +172,12 @@ static struct v4l2_pix_format vga_mode[] = { | |||
| 138 | static struct v4l2_pix_format sif_mode[] = { | 172 | static struct v4l2_pix_format sif_mode[] = { |
| 139 | {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, | 173 | {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, |
| 140 | .bytesperline = 176, | 174 | .bytesperline = 176, |
| 141 | .sizeimage = 176 * 144 * 3 / 8 + 589, | 175 | .sizeimage = 176 * 144 * 3 / 8 + 590, |
| 142 | .colorspace = V4L2_COLORSPACE_JPEG, | 176 | .colorspace = V4L2_COLORSPACE_JPEG, |
| 143 | .priv = 1}, | 177 | .priv = 1}, |
| 144 | {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, | 178 | {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, |
| 145 | .bytesperline = 352, | 179 | .bytesperline = 352, |
| 146 | .sizeimage = 352 * 288 * 3 / 8 + 589, | 180 | .sizeimage = 352 * 288 * 3 / 8 + 590, |
| 147 | .colorspace = V4L2_COLORSPACE_JPEG, | 181 | .colorspace = V4L2_COLORSPACE_JPEG, |
| 148 | .priv = 0}, | 182 | .priv = 0}, |
| 149 | }; | 183 | }; |
| @@ -225,6 +259,7 @@ static struct v4l2_pix_format sif_mode[] = { | |||
| 225 | #define OV7670_REG_VSTART 0x19 /* Vert start high bits */ | 259 | #define OV7670_REG_VSTART 0x19 /* Vert start high bits */ |
| 226 | #define OV7670_REG_VSTOP 0x1a /* Vert stop high bits */ | 260 | #define OV7670_REG_VSTOP 0x1a /* Vert stop high bits */ |
| 227 | #define OV7670_REG_MVFP 0x1e /* Mirror / vflip */ | 261 | #define OV7670_REG_MVFP 0x1e /* Mirror / vflip */ |
| 262 | #define OV7670_MVFP_VFLIP 0x10 /* vertical flip */ | ||
| 228 | #define OV7670_MVFP_MIRROR 0x20 /* Mirror image */ | 263 | #define OV7670_MVFP_MIRROR 0x20 /* Mirror image */ |
| 229 | #define OV7670_REG_AEW 0x24 /* AGC upper limit */ | 264 | #define OV7670_REG_AEW 0x24 /* AGC upper limit */ |
| 230 | #define OV7670_REG_AEB 0x25 /* AGC lower limit */ | 265 | #define OV7670_REG_AEB 0x25 /* AGC lower limit */ |
| @@ -258,16 +293,6 @@ static struct v4l2_pix_format sif_mode[] = { | |||
| 258 | #define OV7670_REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ | 293 | #define OV7670_REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ |
| 259 | #define OV7670_REG_BD60MAX 0xab /* 60hz banding step limit */ | 294 | #define OV7670_REG_BD60MAX 0xab /* 60hz banding step limit */ |
| 260 | 295 | ||
| 261 | struct ovsensor_window { | ||
| 262 | short x; | ||
| 263 | short y; | ||
| 264 | short width; | ||
| 265 | short height; | ||
| 266 | /* int format; */ | ||
| 267 | short quarter; /* Scale width and height down 2x */ | ||
| 268 | short clockdiv; /* Clock divisor setting */ | ||
| 269 | }; | ||
| 270 | |||
| 271 | static unsigned char ov7670_abs_to_sm(unsigned char v) | 296 | static unsigned char ov7670_abs_to_sm(unsigned char v) |
| 272 | { | 297 | { |
| 273 | if (v > 127) | 298 | if (v > 127) |
| @@ -499,19 +524,6 @@ static int init_ov_sensor(struct sd *sd) | |||
| 499 | return 0; | 524 | return 0; |
| 500 | } | 525 | } |
| 501 | 526 | ||
| 502 | /* Switch on standard JPEG compression. Returns 0 for success. */ | ||
| 503 | static int ov519_init_compression(struct sd *sd) | ||
| 504 | { | ||
| 505 | if (!sd->compress_inited) { | ||
| 506 | if (reg_w_mask(sd, OV519_SYS_EN_CLK1, 1 << 2, 1 << 2) < 0) { | ||
| 507 | PDEBUG(D_ERR, "Error switching to compressed mode"); | ||
| 508 | return -EIO; | ||
| 509 | } | ||
| 510 | sd->compress_inited = 1; | ||
| 511 | } | ||
| 512 | return 0; | ||
| 513 | } | ||
| 514 | |||
| 515 | /* Set the read and write slave IDs. The "slave" argument is the write slave, | 527 | /* Set the read and write slave IDs. The "slave" argument is the write slave, |
| 516 | * and the read slave will be set to (slave + 1). | 528 | * and the read slave will be set to (slave + 1). |
| 517 | * This should not be called from outside the i2c I/O functions. | 529 | * This should not be called from outside the i2c I/O functions. |
| @@ -681,21 +693,17 @@ static int ov8xx0_configure(struct sd *sd) | |||
| 681 | return -1; | 693 | return -1; |
| 682 | } | 694 | } |
| 683 | if ((rc & 3) == 1) { | 695 | if ((rc & 3) == 1) { |
| 684 | PDEBUG(D_PROBE, "Sensor is an OV8610"); | ||
| 685 | sd->sensor = SEN_OV8610; | 696 | sd->sensor = SEN_OV8610; |
| 686 | } else { | 697 | } else { |
| 687 | PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3); | 698 | PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3); |
| 688 | return -1; | 699 | return -1; |
| 689 | } | 700 | } |
| 690 | PDEBUG(D_PROBE, "Writing 8610 registers"); | 701 | PDEBUG(D_PROBE, "Writing 8610 registers"); |
| 691 | if (write_i2c_regvals(sd, | 702 | if (write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610))) |
| 692 | norm_8610, | ||
| 693 | sizeof norm_8610 / sizeof norm_8610[0])) | ||
| 694 | return -1; | 703 | return -1; |
| 695 | 704 | ||
| 696 | /* Set sensor-specific vars */ | 705 | /* Set sensor-specific vars */ |
| 697 | sd->maxwidth = 640; | 706 | /* sd->sif = 0; already done */ |
| 698 | sd->maxheight = 480; | ||
| 699 | return 0; | 707 | return 0; |
| 700 | } | 708 | } |
| 701 | 709 | ||
| @@ -825,7 +833,7 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 825 | { OV7670_REG_COM7, OV7670_COM7_RESET }, | 833 | { OV7670_REG_COM7, OV7670_COM7_RESET }, |
| 826 | { OV7670_REG_TSLB, 0x04 }, /* OV */ | 834 | { OV7670_REG_TSLB, 0x04 }, /* OV */ |
| 827 | { OV7670_REG_COM7, OV7670_COM7_FMT_VGA }, /* VGA */ | 835 | { OV7670_REG_COM7, OV7670_COM7_FMT_VGA }, /* VGA */ |
| 828 | { OV7670_REG_CLKRC, 0x1 }, | 836 | { OV7670_REG_CLKRC, 0x01 }, |
| 829 | /* | 837 | /* |
| 830 | * Set the hardware window. These values from OV don't entirely | 838 | * Set the hardware window. These values from OV don't entirely |
| 831 | * make sense - hstop is less than hstart. But they work... | 839 | * make sense - hstop is less than hstart. But they work... |
| @@ -839,16 +847,12 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 839 | { 0x70, 0x3a }, { 0x71, 0x35 }, | 847 | { 0x70, 0x3a }, { 0x71, 0x35 }, |
| 840 | { 0x72, 0x11 }, { 0x73, 0xf0 }, | 848 | { 0x72, 0x11 }, { 0x73, 0xf0 }, |
| 841 | { 0xa2, 0x02 }, | 849 | { 0xa2, 0x02 }, |
| 842 | /* jfm */ | 850 | /* { OV7670_REG_COM10, 0x0 }, */ |
| 843 | /* { OV7670_REG_COM10, 0x0 }, */ | ||
| 844 | 851 | ||
| 845 | /* Gamma curve values */ | 852 | /* Gamma curve values */ |
| 846 | { 0x7a, 0x20 }, | 853 | { 0x7a, 0x20 }, |
| 847 | /* jfm:win 7b=1c */ | ||
| 848 | { 0x7b, 0x10 }, | 854 | { 0x7b, 0x10 }, |
| 849 | /* jfm:win 7c=28 */ | ||
| 850 | { 0x7c, 0x1e }, | 855 | { 0x7c, 0x1e }, |
| 851 | /* jfm:win 7d=3c */ | ||
| 852 | { 0x7d, 0x35 }, | 856 | { 0x7d, 0x35 }, |
| 853 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, | 857 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, |
| 854 | { 0x80, 0x76 }, { 0x81, 0x80 }, | 858 | { 0x80, 0x76 }, { 0x81, 0x80 }, |
| @@ -864,13 +868,11 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 864 | | OV7670_COM8_BFILT }, | 868 | | OV7670_COM8_BFILT }, |
| 865 | { OV7670_REG_GAIN, 0 }, { OV7670_REG_AECH, 0 }, | 869 | { OV7670_REG_GAIN, 0 }, { OV7670_REG_AECH, 0 }, |
| 866 | { OV7670_REG_COM4, 0x40 }, /* magic reserved bit */ | 870 | { OV7670_REG_COM4, 0x40 }, /* magic reserved bit */ |
| 867 | /* jfm:win 14=38 */ | ||
| 868 | { OV7670_REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ | 871 | { OV7670_REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ |
| 869 | { OV7670_REG_BD50MAX, 0x05 }, { OV7670_REG_BD60MAX, 0x07 }, | 872 | { OV7670_REG_BD50MAX, 0x05 }, { OV7670_REG_BD60MAX, 0x07 }, |
| 870 | { OV7670_REG_AEW, 0x95 }, { OV7670_REG_AEB, 0x33 }, | 873 | { OV7670_REG_AEW, 0x95 }, { OV7670_REG_AEB, 0x33 }, |
| 871 | { OV7670_REG_VPT, 0xe3 }, { OV7670_REG_HAECC1, 0x78 }, | 874 | { OV7670_REG_VPT, 0xe3 }, { OV7670_REG_HAECC1, 0x78 }, |
| 872 | { OV7670_REG_HAECC2, 0x68 }, | 875 | { OV7670_REG_HAECC2, 0x68 }, |
| 873 | /* jfm:win a1=0b */ | ||
| 874 | { 0xa1, 0x03 }, /* magic */ | 876 | { 0xa1, 0x03 }, /* magic */ |
| 875 | { OV7670_REG_HAECC3, 0xd8 }, { OV7670_REG_HAECC4, 0xd8 }, | 877 | { OV7670_REG_HAECC3, 0xd8 }, { OV7670_REG_HAECC4, 0xd8 }, |
| 876 | { OV7670_REG_HAECC5, 0xf0 }, { OV7670_REG_HAECC6, 0x90 }, | 878 | { OV7670_REG_HAECC5, 0xf0 }, { OV7670_REG_HAECC6, 0x90 }, |
| @@ -884,8 +886,6 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 884 | /* Almost all of these are magic "reserved" values. */ | 886 | /* Almost all of these are magic "reserved" values. */ |
| 885 | { OV7670_REG_COM5, 0x61 }, { OV7670_REG_COM6, 0x4b }, | 887 | { OV7670_REG_COM5, 0x61 }, { OV7670_REG_COM6, 0x4b }, |
| 886 | { 0x16, 0x02 }, | 888 | { 0x16, 0x02 }, |
| 887 | /* jfm */ | ||
| 888 | /* { OV7670_REG_MVFP, 0x07|OV7670_MVFP_MIRROR }, */ | ||
| 889 | { OV7670_REG_MVFP, 0x07 }, | 889 | { OV7670_REG_MVFP, 0x07 }, |
| 890 | { 0x21, 0x02 }, { 0x22, 0x91 }, | 890 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
| 891 | { 0x29, 0x07 }, { 0x33, 0x0b }, | 891 | { 0x29, 0x07 }, { 0x33, 0x0b }, |
| @@ -930,7 +930,10 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 930 | { OV7670_REG_EDGE, 0 }, | 930 | { OV7670_REG_EDGE, 0 }, |
| 931 | { 0x75, 0x05 }, { 0x76, 0xe1 }, | 931 | { 0x75, 0x05 }, { 0x76, 0xe1 }, |
| 932 | { 0x4c, 0 }, { 0x77, 0x01 }, | 932 | { 0x4c, 0 }, { 0x77, 0x01 }, |
| 933 | { OV7670_REG_COM13, 0xc3 }, { 0x4b, 0x09 }, | 933 | { OV7670_REG_COM13, OV7670_COM13_GAMMA |
| 934 | | OV7670_COM13_UVSAT | ||
| 935 | | 2}, /* was 3 */ | ||
| 936 | { 0x4b, 0x09 }, | ||
| 934 | { 0xc9, 0x60 }, { OV7670_REG_COM16, 0x38 }, | 937 | { 0xc9, 0x60 }, { OV7670_REG_COM16, 0x38 }, |
| 935 | { 0x56, 0x40 }, | 938 | { 0x56, 0x40 }, |
| 936 | 939 | ||
| @@ -956,30 +959,10 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 956 | { 0x79, 0x03 }, { 0xc8, 0x40 }, | 959 | { 0x79, 0x03 }, { 0xc8, 0x40 }, |
| 957 | { 0x79, 0x05 }, { 0xc8, 0x30 }, | 960 | { 0x79, 0x05 }, { 0xc8, 0x30 }, |
| 958 | { 0x79, 0x26 }, | 961 | { 0x79, 0x26 }, |
| 959 | 962 | }; | |
| 960 | /* Format YUV422 */ | ||
| 961 | { OV7670_REG_COM7, OV7670_COM7_YUV }, /* Selects YUV mode */ | ||
| 962 | { OV7670_REG_RGB444, 0 }, /* No RGB444 please */ | ||
| 963 | { OV7670_REG_COM1, 0 }, | ||
| 964 | { OV7670_REG_COM15, OV7670_COM15_R00FF }, | ||
| 965 | { OV7670_REG_COM9, 0x18 }, | ||
| 966 | /* 4x gain ceiling; 0x8 is reserved bit */ | ||
| 967 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ | ||
| 968 | { 0x50, 0x80 }, /* "matrix coefficient 2" */ | ||
| 969 | { 0x52, 0x22 }, /* "matrix coefficient 4" */ | ||
| 970 | { 0x53, 0x5e }, /* "matrix coefficient 5" */ | ||
| 971 | { 0x54, 0x80 }, /* "matrix coefficient 6" */ | ||
| 972 | { OV7670_REG_COM13, OV7670_COM13_GAMMA|OV7670_COM13_UVSAT }, | ||
| 973 | }; | ||
| 974 | 963 | ||
| 975 | PDEBUG(D_PROBE, "starting OV7xx0 configuration"); | 964 | PDEBUG(D_PROBE, "starting OV7xx0 configuration"); |
| 976 | 965 | ||
| 977 | /* jfm:already done? */ | ||
| 978 | if (init_ov_sensor(sd) < 0) | ||
| 979 | PDEBUG(D_ERR, "Failed to read sensor ID"); | ||
| 980 | else | ||
| 981 | PDEBUG(D_PROBE, "OV7xx0 initialized"); | ||
| 982 | |||
| 983 | /* Detect sensor (sub)type */ | 966 | /* Detect sensor (sub)type */ |
| 984 | rc = i2c_r(sd, OV7610_REG_COM_I); | 967 | rc = i2c_r(sd, OV7610_REG_COM_I); |
| 985 | 968 | ||
| @@ -1025,20 +1008,25 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 1025 | return low; | 1008 | return low; |
| 1026 | } | 1009 | } |
| 1027 | if (high == 0x76) { | 1010 | if (high == 0x76) { |
| 1028 | if (low == 0x30) { | 1011 | switch (low) { |
| 1012 | case 0x30: | ||
| 1029 | PDEBUG(D_PROBE, "Sensor is an OV7630/OV7635"); | 1013 | PDEBUG(D_PROBE, "Sensor is an OV7630/OV7635"); |
| 1030 | sd->sensor = SEN_OV7630; | 1014 | sd->sensor = SEN_OV7630; |
| 1031 | } else if (low == 0x40) { | 1015 | break; |
| 1016 | case 0x40: | ||
| 1032 | PDEBUG(D_PROBE, "Sensor is an OV7645"); | 1017 | PDEBUG(D_PROBE, "Sensor is an OV7645"); |
| 1033 | sd->sensor = SEN_OV7640; /* FIXME */ | 1018 | sd->sensor = SEN_OV7640; /* FIXME */ |
| 1034 | } else if (low == 0x45) { | 1019 | break; |
| 1020 | case 0x45: | ||
| 1035 | PDEBUG(D_PROBE, "Sensor is an OV7645B"); | 1021 | PDEBUG(D_PROBE, "Sensor is an OV7645B"); |
| 1036 | sd->sensor = SEN_OV7640; /* FIXME */ | 1022 | sd->sensor = SEN_OV7640; /* FIXME */ |
| 1037 | } else if (low == 0x48) { | 1023 | break; |
| 1024 | case 0x48: | ||
| 1038 | PDEBUG(D_PROBE, "Sensor is an OV7648"); | 1025 | PDEBUG(D_PROBE, "Sensor is an OV7648"); |
| 1039 | sd->sensor = SEN_OV7640; /* FIXME */ | 1026 | sd->sensor = SEN_OV7640; /* FIXME */ |
| 1040 | } else { | 1027 | break; |
| 1041 | PDEBUG(D_PROBE, "Unknown sensor: 0x76%X", low); | 1028 | default: |
| 1029 | PDEBUG(D_PROBE, "Unknown sensor: 0x76%x", low); | ||
| 1042 | return -1; | 1030 | return -1; |
| 1043 | } | 1031 | } |
| 1044 | } else { | 1032 | } else { |
| @@ -1050,34 +1038,34 @@ static int ov7xx0_configure(struct sd *sd) | |||
| 1050 | return -1; | 1038 | return -1; |
| 1051 | } | 1039 | } |
| 1052 | 1040 | ||
| 1053 | if (sd->sensor == SEN_OV7620) { | 1041 | switch (sd->sensor) { |
| 1042 | case SEN_OV7620: | ||
| 1054 | PDEBUG(D_PROBE, "Writing 7620 registers"); | 1043 | PDEBUG(D_PROBE, "Writing 7620 registers"); |
| 1055 | if (write_i2c_regvals(sd, norm_7620, | 1044 | if (write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620))) |
| 1056 | sizeof norm_7620 / sizeof norm_7620[0])) | ||
| 1057 | return -1; | 1045 | return -1; |
| 1058 | } else if (sd->sensor == SEN_OV7630) { | 1046 | break; |
| 1047 | case SEN_OV7630: | ||
| 1059 | PDEBUG(D_ERR, "7630 is not supported by this driver version"); | 1048 | PDEBUG(D_ERR, "7630 is not supported by this driver version"); |
| 1060 | return -1; | 1049 | return -1; |
| 1061 | } else if (sd->sensor == SEN_OV7640) { | 1050 | case SEN_OV7640: |
| 1062 | PDEBUG(D_PROBE, "Writing 7640 registers"); | 1051 | PDEBUG(D_PROBE, "Writing 7640 registers"); |
| 1063 | if (write_i2c_regvals(sd, norm_7640, | 1052 | if (write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640))) |
| 1064 | sizeof norm_7640 / sizeof norm_7640[0])) | ||
| 1065 | return -1; | 1053 | return -1; |
| 1066 | } else if (sd->sensor == SEN_OV7670) { | 1054 | break; |
| 1055 | case SEN_OV7670: | ||
| 1067 | PDEBUG(D_PROBE, "Writing 7670 registers"); | 1056 | PDEBUG(D_PROBE, "Writing 7670 registers"); |
| 1068 | if (write_i2c_regvals(sd, norm_7670, | 1057 | if (write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670))) |
| 1069 | sizeof norm_7670 / sizeof norm_7670[0])) | ||
| 1070 | return -1; | 1058 | return -1; |
| 1071 | } else { | 1059 | break; |
| 1060 | default: | ||
| 1072 | PDEBUG(D_PROBE, "Writing 7610 registers"); | 1061 | PDEBUG(D_PROBE, "Writing 7610 registers"); |
| 1073 | if (write_i2c_regvals(sd, norm_7610, | 1062 | if (write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610))) |
| 1074 | sizeof norm_7610 / sizeof norm_7610[0])) | ||
| 1075 | return -1; | 1063 | return -1; |
| 1064 | break; | ||
| 1076 | } | 1065 | } |
| 1077 | 1066 | ||
| 1078 | /* Set sensor-specific vars */ | 1067 | /* Set sensor-specific vars */ |
| 1079 | sd->maxwidth = 640; | 1068 | /* sd->sif = 0; already done */ |
| 1080 | sd->maxheight = 480; | ||
| 1081 | return 0; | 1069 | return 0; |
| 1082 | } | 1070 | } |
| 1083 | 1071 | ||
| @@ -1231,43 +1219,45 @@ static int ov6xx0_configure(struct sd *sd) | |||
| 1231 | /* Ugh. The first two bits are the version bits, but | 1219 | /* Ugh. The first two bits are the version bits, but |
| 1232 | * the entire register value must be used. I guess OVT | 1220 | * the entire register value must be used. I guess OVT |
| 1233 | * underestimated how many variants they would make. */ | 1221 | * underestimated how many variants they would make. */ |
| 1234 | if (rc == 0x00) { | 1222 | switch (rc) { |
| 1223 | case 0x00: | ||
| 1235 | sd->sensor = SEN_OV6630; | 1224 | sd->sensor = SEN_OV6630; |
| 1236 | PDEBUG(D_ERR, | 1225 | PDEBUG(D_ERR, |
| 1237 | "WARNING: Sensor is an OV66308. Your camera may have"); | 1226 | "WARNING: Sensor is an OV66308. Your camera may have"); |
| 1238 | PDEBUG(D_ERR, "been misdetected in previous driver versions."); | 1227 | PDEBUG(D_ERR, "been misdetected in previous driver versions."); |
| 1239 | } else if (rc == 0x01) { | 1228 | break; |
| 1229 | case 0x01: | ||
| 1240 | sd->sensor = SEN_OV6620; | 1230 | sd->sensor = SEN_OV6620; |
| 1241 | PDEBUG(D_PROBE, "Sensor is an OV6620"); | 1231 | break; |
| 1242 | } else if (rc == 0x02) { | 1232 | case 0x02: |
| 1243 | sd->sensor = SEN_OV6630; | 1233 | sd->sensor = SEN_OV6630; |
| 1244 | PDEBUG(D_PROBE, "Sensor is an OV66308AE"); | 1234 | PDEBUG(D_PROBE, "Sensor is an OV66308AE"); |
| 1245 | } else if (rc == 0x03) { | 1235 | break; |
| 1236 | case 0x03: | ||
| 1246 | sd->sensor = SEN_OV6630; | 1237 | sd->sensor = SEN_OV6630; |
| 1247 | PDEBUG(D_PROBE, "Sensor is an OV66308AF"); | 1238 | PDEBUG(D_PROBE, "Sensor is an OV66308AF"); |
| 1248 | } else if (rc == 0x90) { | 1239 | break; |
| 1240 | case 0x90: | ||
| 1249 | sd->sensor = SEN_OV6630; | 1241 | sd->sensor = SEN_OV6630; |
| 1250 | PDEBUG(D_ERR, | 1242 | PDEBUG(D_ERR, |
| 1251 | "WARNING: Sensor is an OV66307. Your camera may have"); | 1243 | "WARNING: Sensor is an OV66307. Your camera may have"); |
| 1252 | PDEBUG(D_ERR, "been misdetected in previous driver versions."); | 1244 | PDEBUG(D_ERR, "been misdetected in previous driver versions."); |
| 1253 | } else { | 1245 | break; |
| 1246 | default: | ||
| 1254 | PDEBUG(D_ERR, "FATAL: Unknown sensor version: 0x%02x", rc); | 1247 | PDEBUG(D_ERR, "FATAL: Unknown sensor version: 0x%02x", rc); |
| 1255 | return -1; | 1248 | return -1; |
| 1256 | } | 1249 | } |
| 1257 | 1250 | ||
| 1258 | /* Set sensor-specific vars */ | 1251 | /* Set sensor-specific vars */ |
| 1259 | sd->maxwidth = 352; | 1252 | sd->sif = 1; |
| 1260 | sd->maxheight = 288; | ||
| 1261 | 1253 | ||
| 1262 | if (sd->sensor == SEN_OV6620) { | 1254 | if (sd->sensor == SEN_OV6620) { |
| 1263 | PDEBUG(D_PROBE, "Writing 6x20 registers"); | 1255 | PDEBUG(D_PROBE, "Writing 6x20 registers"); |
| 1264 | if (write_i2c_regvals(sd, norm_6x20, | 1256 | if (write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20))) |
| 1265 | sizeof norm_6x20 / sizeof norm_6x20[0])) | ||
| 1266 | return -1; | 1257 | return -1; |
| 1267 | } else { | 1258 | } else { |
| 1268 | PDEBUG(D_PROBE, "Writing 6x30 registers"); | 1259 | PDEBUG(D_PROBE, "Writing 6x30 registers"); |
| 1269 | if (write_i2c_regvals(sd, norm_6x30, | 1260 | if (write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30))) |
| 1270 | sizeof norm_6x30 / sizeof norm_6x30[0])) | ||
| 1271 | return -1; | 1261 | return -1; |
| 1272 | } | 1262 | } |
| 1273 | return 0; | 1263 | return 0; |
| @@ -1276,14 +1266,8 @@ static int ov6xx0_configure(struct sd *sd) | |||
| 1276 | /* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */ | 1266 | /* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */ |
| 1277 | static void ov51x_led_control(struct sd *sd, int on) | 1267 | static void ov51x_led_control(struct sd *sd, int on) |
| 1278 | { | 1268 | { |
| 1279 | PDEBUG(D_STREAM, "LED (%s)", on ? "on" : "off"); | 1269 | /* PDEBUG(D_STREAM, "LED (%s)", on ? "on" : "off"); */ |
| 1280 | 1270 | reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1); /* 0 / 1 */ | |
| 1281 | /* if (sd->bridge == BRG_OV511PLUS) */ | ||
| 1282 | /* reg_w(sd, R511_SYS_LED_CTL, on ? 1 : 0); */ | ||
| 1283 | /* else if (sd->bridge == BRG_OV519) */ | ||
| 1284 | reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1); /* 0 / 1 */ | ||
| 1285 | /* else if (sd->bclass == BCL_OV518) */ | ||
| 1286 | /* reg_w_mask(sd, R518_GPIO_OUT, on ? 0x02 : 0x00, 0x02); */ | ||
| 1287 | } | 1271 | } |
| 1288 | 1272 | ||
| 1289 | /* this function is called at probe time */ | 1273 | /* this function is called at probe time */ |
| @@ -1293,11 +1277,8 @@ static int sd_config(struct gspca_dev *gspca_dev, | |||
| 1293 | struct sd *sd = (struct sd *) gspca_dev; | 1277 | struct sd *sd = (struct sd *) gspca_dev; |
| 1294 | struct cam *cam; | 1278 | struct cam *cam; |
| 1295 | 1279 | ||
| 1296 | /* (from ov519_configure) */ | ||
| 1297 | static const struct ov_regvals init_519[] = { | 1280 | static const struct ov_regvals init_519[] = { |
| 1298 | { 0x5a, 0x6d }, /* EnableSystem */ | 1281 | { 0x5a, 0x6d }, /* EnableSystem */ |
| 1299 | /* jfm trace usbsnoop3-1.txt */ | ||
| 1300 | /* jfm 53 = fb */ | ||
| 1301 | { 0x53, 0x9b }, | 1282 | { 0x53, 0x9b }, |
| 1302 | { 0x54, 0xff }, /* set bit2 to enable jpeg */ | 1283 | { 0x54, 0xff }, /* set bit2 to enable jpeg */ |
| 1303 | { 0x5d, 0x03 }, | 1284 | { 0x5d, 0x03 }, |
| @@ -1314,9 +1295,6 @@ static int sd_config(struct gspca_dev *gspca_dev, | |||
| 1314 | 1295 | ||
| 1315 | if (write_regvals(sd, init_519, ARRAY_SIZE(init_519))) | 1296 | if (write_regvals(sd, init_519, ARRAY_SIZE(init_519))) |
| 1316 | goto error; | 1297 | goto error; |
| 1317 | /* jfm: not seen in windows trace */ | ||
| 1318 | if (ov519_init_compression(sd)) | ||
| 1319 | goto error; | ||
| 1320 | ov51x_led_control(sd, 0); /* turn LED off */ | 1298 | ov51x_led_control(sd, 0); /* turn LED off */ |
| 1321 | 1299 | ||
| 1322 | /* Test for 76xx */ | 1300 | /* Test for 76xx */ |
| @@ -1365,16 +1343,18 @@ static int sd_config(struct gspca_dev *gspca_dev, | |||
| 1365 | 1343 | ||
| 1366 | cam = &gspca_dev->cam; | 1344 | cam = &gspca_dev->cam; |
| 1367 | cam->epaddr = OV511_ENDPOINT_ADDRESS; | 1345 | cam->epaddr = OV511_ENDPOINT_ADDRESS; |
| 1368 | if (sd->maxwidth == 640) { | 1346 | if (!sd->sif) { |
| 1369 | cam->cam_mode = vga_mode; | 1347 | cam->cam_mode = vga_mode; |
| 1370 | cam->nmodes = sizeof vga_mode / sizeof vga_mode[0]; | 1348 | cam->nmodes = ARRAY_SIZE(vga_mode); |
| 1371 | } else { | 1349 | } else { |
| 1372 | cam->cam_mode = sif_mode; | 1350 | cam->cam_mode = sif_mode; |
| 1373 | cam->nmodes = sizeof sif_mode / sizeof sif_mode[0]; | 1351 | cam->nmodes = ARRAY_SIZE(sif_mode); |
| 1374 | } | 1352 | } |
| 1375 | sd->brightness = sd_ctrls[SD_BRIGHTNESS].qctrl.default_value; | 1353 | sd->brightness = BRIGHTNESS_DEF; |
| 1376 | sd->contrast = sd_ctrls[SD_CONTRAST].qctrl.default_value; | 1354 | sd->contrast = CONTRAST_DEF; |
| 1377 | sd->colors = sd_ctrls[SD_COLOR].qctrl.default_value; | 1355 | sd->colors = COLOR_DEF; |
| 1356 | sd->hflip = HFLIP_DEF; | ||
| 1357 | sd->vflip = VFLIP_DEF; | ||
| 1378 | return 0; | 1358 | return 0; |
| 1379 | error: | 1359 | error: |
| 1380 | PDEBUG(D_ERR, "OV519 Config failed"); | 1360 | PDEBUG(D_ERR, "OV519 Config failed"); |
| @@ -1394,8 +1374,7 @@ static int sd_open(struct gspca_dev *gspca_dev) | |||
| 1394 | * | 1374 | * |
| 1395 | * Do not put any sensor-specific code in here (including I2C I/O functions) | 1375 | * Do not put any sensor-specific code in here (including I2C I/O functions) |
| 1396 | */ | 1376 | */ |
| 1397 | static int ov519_mode_init_regs(struct sd *sd, | 1377 | static int ov519_mode_init_regs(struct sd *sd) |
| 1398 | int width, int height) | ||
| 1399 | { | 1378 | { |
| 1400 | static const struct ov_regvals mode_init_519_ov7670[] = { | 1379 | static const struct ov_regvals mode_init_519_ov7670[] = { |
| 1401 | { 0x5d, 0x03 }, /* Turn off suspend mode */ | 1380 | { 0x5d, 0x03 }, /* Turn off suspend mode */ |
| @@ -1441,36 +1420,23 @@ static int ov519_mode_init_regs(struct sd *sd, | |||
| 1441 | /* windows reads 0x55 at this point, why? */ | 1420 | /* windows reads 0x55 at this point, why? */ |
| 1442 | }; | 1421 | }; |
| 1443 | 1422 | ||
| 1444 | /* int hi_res; */ | ||
| 1445 | |||
| 1446 | PDEBUG(D_CONF, "mode init %dx%d", width, height); | ||
| 1447 | |||
| 1448 | /* if (width >= 800 && height >= 600) | ||
| 1449 | hi_res = 1; | ||
| 1450 | else | ||
| 1451 | hi_res = 0; */ | ||
| 1452 | |||
| 1453 | /* if (ov51x_stop(sd) < 0) | ||
| 1454 | return -EIO; */ | ||
| 1455 | |||
| 1456 | /******** Set the mode ********/ | 1423 | /******** Set the mode ********/ |
| 1457 | if (sd->sensor != SEN_OV7670) { | 1424 | if (sd->sensor != SEN_OV7670) { |
| 1458 | if (write_regvals(sd, mode_init_519, | 1425 | if (write_regvals(sd, mode_init_519, |
| 1459 | ARRAY_SIZE(mode_init_519))) | 1426 | ARRAY_SIZE(mode_init_519))) |
| 1460 | return -EIO; | 1427 | return -EIO; |
| 1428 | if (sd->sensor == SEN_OV7640) { | ||
| 1429 | /* Select 8-bit input mode */ | ||
| 1430 | reg_w_mask(sd, OV519_CAM_DFR, 0x10, 0x10); | ||
| 1431 | } | ||
| 1461 | } else { | 1432 | } else { |
| 1462 | if (write_regvals(sd, mode_init_519_ov7670, | 1433 | if (write_regvals(sd, mode_init_519_ov7670, |
| 1463 | ARRAY_SIZE(mode_init_519_ov7670))) | 1434 | ARRAY_SIZE(mode_init_519_ov7670))) |
| 1464 | return -EIO; | 1435 | return -EIO; |
| 1465 | } | 1436 | } |
| 1466 | 1437 | ||
| 1467 | if (sd->sensor == SEN_OV7640) { | 1438 | reg_w(sd, OV519_CAM_H_SIZE, sd->gspca_dev.width >> 4); |
| 1468 | /* Select 8-bit input mode */ | 1439 | reg_w(sd, OV519_CAM_V_SIZE, sd->gspca_dev.height >> 3); |
| 1469 | reg_w_mask(sd, OV519_CAM_DFR, 0x10, 0x10); | ||
| 1470 | } | ||
| 1471 | |||
| 1472 | reg_w(sd, OV519_CAM_H_SIZE, width >> 4); | ||
| 1473 | reg_w(sd, OV519_CAM_V_SIZE, height >> 3); | ||
| 1474 | reg_w(sd, OV519_CAM_X_OFFSETL, 0x00); | 1440 | reg_w(sd, OV519_CAM_X_OFFSETL, 0x00); |
| 1475 | reg_w(sd, OV519_CAM_X_OFFSETH, 0x00); | 1441 | reg_w(sd, OV519_CAM_X_OFFSETH, 0x00); |
| 1476 | reg_w(sd, OV519_CAM_Y_OFFSETL, 0x00); | 1442 | reg_w(sd, OV519_CAM_Y_OFFSETL, 0x00); |
| @@ -1485,9 +1451,10 @@ static int ov519_mode_init_regs(struct sd *sd, | |||
| 1485 | 1451 | ||
| 1486 | /* FIXME: These are only valid at the max resolution. */ | 1452 | /* FIXME: These are only valid at the max resolution. */ |
| 1487 | sd->clockdiv = 0; | 1453 | sd->clockdiv = 0; |
| 1488 | if (sd->sensor == SEN_OV7640) { | 1454 | switch (sd->sensor) { |
| 1455 | case SEN_OV7640: | ||
| 1489 | switch (sd->frame_rate) { | 1456 | switch (sd->frame_rate) { |
| 1490 | /*jfm: default was 30 fps */ | 1457 | /*fixme: default was 30 fps */ |
| 1491 | case 30: | 1458 | case 30: |
| 1492 | reg_w(sd, 0xa4, 0x0c); | 1459 | reg_w(sd, 0xa4, 0x0c); |
| 1493 | reg_w(sd, 0x23, 0xff); | 1460 | reg_w(sd, 0x23, 0xff); |
| @@ -1517,7 +1484,8 @@ static int ov519_mode_init_regs(struct sd *sd, | |||
| 1517 | sd->clockdiv = 1; | 1484 | sd->clockdiv = 1; |
| 1518 | break; | 1485 | break; |
| 1519 | } | 1486 | } |
| 1520 | } else if (sd->sensor == SEN_OV8610) { | 1487 | break; |
| 1488 | case SEN_OV8610: | ||
| 1521 | switch (sd->frame_rate) { | 1489 | switch (sd->frame_rate) { |
| 1522 | default: /* 15 fps */ | 1490 | default: /* 15 fps */ |
| 1523 | /* case 15: */ | 1491 | /* case 15: */ |
| @@ -1533,41 +1501,37 @@ static int ov519_mode_init_regs(struct sd *sd, | |||
| 1533 | reg_w(sd, 0x23, 0x1b); | 1501 | reg_w(sd, 0x23, 0x1b); |
| 1534 | break; | 1502 | break; |
| 1535 | } | 1503 | } |
| 1536 | sd->clockdiv = 0; | 1504 | break; |
| 1537 | } else if (sd->sensor == SEN_OV7670) { /* guesses, based on 7640 */ | 1505 | case SEN_OV7670: /* guesses, based on 7640 */ |
| 1538 | PDEBUG(D_STREAM, "Setting framerate to %d fps", | 1506 | PDEBUG(D_STREAM, "Setting framerate to %d fps", |
| 1539 | (sd->frame_rate == 0) ? 15 : sd->frame_rate); | 1507 | (sd->frame_rate == 0) ? 15 : sd->frame_rate); |
| 1508 | reg_w(sd, 0xa4, 0x10); | ||
| 1540 | switch (sd->frame_rate) { | 1509 | switch (sd->frame_rate) { |
| 1541 | case 30: | 1510 | case 30: |
| 1542 | reg_w(sd, 0xa4, 0x10); | ||
| 1543 | reg_w(sd, 0x23, 0xff); | 1511 | reg_w(sd, 0x23, 0xff); |
| 1544 | break; | 1512 | break; |
| 1545 | case 20: | 1513 | case 20: |
| 1546 | reg_w(sd, 0xa4, 0x10); | ||
| 1547 | reg_w(sd, 0x23, 0x1b); | 1514 | reg_w(sd, 0x23, 0x1b); |
| 1548 | break; | 1515 | break; |
| 1549 | default: /* 15 fps */ | 1516 | default: |
| 1550 | /* case 15: */ | 1517 | /* case 15: */ |
| 1551 | reg_w(sd, 0xa4, 0x10); | ||
| 1552 | reg_w(sd, 0x23, 0xff); | 1518 | reg_w(sd, 0x23, 0xff); |
| 1553 | sd->clockdiv = 1; | 1519 | sd->clockdiv = 1; |
| 1554 | break; | 1520 | break; |
| 1555 | } | 1521 | } |
| 1522 | break; | ||
| 1556 | } | 1523 | } |
| 1557 | 1524 | ||
| 1558 | /* if (ov51x_restart(sd) < 0) | ||
| 1559 | return -EIO; */ | ||
| 1560 | |||
| 1561 | /* Reset it just for good measure */ | ||
| 1562 | /* if (ov51x_reset(sd, OV511_RESET_NOREGS) < 0) | ||
| 1563 | return -EIO; */ | ||
| 1564 | return 0; | 1525 | return 0; |
| 1565 | } | 1526 | } |
| 1566 | 1527 | ||
| 1567 | static int mode_init_ov_sensor_regs(struct sd *sd, | 1528 | static int mode_init_ov_sensor_regs(struct sd *sd) |
| 1568 | struct ovsensor_window *win) | ||
| 1569 | { | 1529 | { |
| 1570 | int qvga = win->quarter; | 1530 | struct gspca_dev *gspca_dev; |
| 1531 | int qvga; | ||
| 1532 | |||
| 1533 | gspca_dev = &sd->gspca_dev; | ||
| 1534 | qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv; | ||
| 1571 | 1535 | ||
| 1572 | /******** Mode (VGA/QVGA) and sensor specific regs ********/ | 1536 | /******** Mode (VGA/QVGA) and sensor specific regs ********/ |
| 1573 | switch (sd->sensor) { | 1537 | switch (sd->sensor) { |
| @@ -1611,8 +1575,6 @@ static int mode_init_ov_sensor_regs(struct sd *sd, | |||
| 1611 | OV7670_COM7_FMT_MASK); | 1575 | OV7670_COM7_FMT_MASK); |
| 1612 | break; | 1576 | break; |
| 1613 | case SEN_OV6620: | 1577 | case SEN_OV6620: |
| 1614 | i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20); | ||
| 1615 | break; | ||
| 1616 | case SEN_OV6630: | 1578 | case SEN_OV6630: |
| 1617 | i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20); | 1579 | i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20); |
| 1618 | break; | 1580 | break; |
| @@ -1621,24 +1583,21 @@ static int mode_init_ov_sensor_regs(struct sd *sd, | |||
| 1621 | } | 1583 | } |
| 1622 | 1584 | ||
| 1623 | /******** Palette-specific regs ********/ | 1585 | /******** Palette-specific regs ********/ |
| 1624 | /* Need to do work here for the OV7670 */ | 1586 | if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { |
| 1625 | 1587 | /* not valid on the OV6620/OV7620/6630? */ | |
| 1626 | if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { | 1588 | i2c_w_mask(sd, 0x0e, 0x00, 0x40); |
| 1627 | /* not valid on the OV6620/OV7620/6630? */ | 1589 | } |
| 1628 | i2c_w_mask(sd, 0x0e, 0x00, 0x40); | ||
| 1629 | } | ||
| 1630 | 1590 | ||
| 1631 | /* The OV518 needs special treatment. Although both the OV518 | 1591 | /* The OV518 needs special treatment. Although both the OV518 |
| 1632 | * and the OV6630 support a 16-bit video bus, only the 8 bit Y | 1592 | * and the OV6630 support a 16-bit video bus, only the 8 bit Y |
| 1633 | * bus is actually used. The UV bus is tied to ground. | 1593 | * bus is actually used. The UV bus is tied to ground. |
| 1634 | * Therefore, the OV6630 needs to be in 8-bit multiplexed | 1594 | * Therefore, the OV6630 needs to be in 8-bit multiplexed |
| 1635 | * output mode */ | 1595 | * output mode */ |
| 1636 | 1596 | ||
| 1637 | /* OV7640 is 8-bit only */ | 1597 | /* OV7640 is 8-bit only */ |
| 1638 | 1598 | ||
| 1639 | if (sd->sensor != SEN_OV6630 && sd->sensor != SEN_OV7640) | 1599 | if (sd->sensor != SEN_OV6630 && sd->sensor != SEN_OV7640) |
| 1640 | i2c_w_mask(sd, 0x13, 0x00, 0x20); | 1600 | i2c_w_mask(sd, 0x13, 0x00, 0x20); |
| 1641 | /* } */ | ||
| 1642 | 1601 | ||
| 1643 | /******** Clock programming ********/ | 1602 | /******** Clock programming ********/ |
| 1644 | /* The OV6620 needs special handling. This prevents the | 1603 | /* The OV6620 needs special handling. This prevents the |
| @@ -1647,14 +1606,14 @@ static int mode_init_ov_sensor_regs(struct sd *sd, | |||
| 1647 | 1606 | ||
| 1648 | /* Clock down */ | 1607 | /* Clock down */ |
| 1649 | i2c_w(sd, 0x2a, 0x04); | 1608 | i2c_w(sd, 0x2a, 0x04); |
| 1650 | i2c_w(sd, 0x11, win->clockdiv); | 1609 | i2c_w(sd, 0x11, sd->clockdiv); |
| 1651 | i2c_w(sd, 0x2a, 0x84); | 1610 | i2c_w(sd, 0x2a, 0x84); |
| 1652 | /* This next setting is critical. It seems to improve | 1611 | /* This next setting is critical. It seems to improve |
| 1653 | * the gain or the contrast. The "reserved" bits seem | 1612 | * the gain or the contrast. The "reserved" bits seem |
| 1654 | * to have some effect in this case. */ | 1613 | * to have some effect in this case. */ |
| 1655 | i2c_w(sd, 0x2d, 0x85); | 1614 | i2c_w(sd, 0x2d, 0x85); |
| 1656 | } else if (win->clockdiv >= 0) { | 1615 | } else if (sd->clockdiv >= 0) { |
| 1657 | i2c_w(sd, 0x11, win->clockdiv); | 1616 | i2c_w(sd, 0x11, sd->clockdiv); |
| 1658 | } | 1617 | } |
| 1659 | 1618 | ||
| 1660 | /******** Special Features ********/ | 1619 | /******** Special Features ********/ |
| @@ -1674,7 +1633,7 @@ static int mode_init_ov_sensor_regs(struct sd *sd, | |||
| 1674 | /* is fully tested. */ | 1633 | /* is fully tested. */ |
| 1675 | /* 7620/6620/6630? don't have register 0x35, so play it safe */ | 1634 | /* 7620/6620/6630? don't have register 0x35, so play it safe */ |
| 1676 | if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { | 1635 | if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { |
| 1677 | if (win->width == 640 /*&& win->height == 480*/) | 1636 | if (!qvga) |
| 1678 | i2c_w(sd, 0x35, 0x9e); | 1637 | i2c_w(sd, 0x35, 0x9e); |
| 1679 | else | 1638 | else |
| 1680 | i2c_w(sd, 0x35, 0x1e); | 1639 | i2c_w(sd, 0x35, 0x1e); |
| @@ -1682,13 +1641,31 @@ static int mode_init_ov_sensor_regs(struct sd *sd, | |||
| 1682 | return 0; | 1641 | return 0; |
| 1683 | } | 1642 | } |
| 1684 | 1643 | ||
| 1685 | static int set_ov_sensor_window(struct sd *sd, | 1644 | static void sethvflip(struct sd *sd) |
| 1686 | struct ovsensor_window *win) | ||
| 1687 | { | 1645 | { |
| 1646 | if (sd->sensor != SEN_OV7670) | ||
| 1647 | return; | ||
| 1648 | if (sd->gspca_dev.streaming) | ||
| 1649 | ov51x_stop(sd); | ||
| 1650 | i2c_w_mask(sd, OV7670_REG_MVFP, | ||
| 1651 | OV7670_MVFP_MIRROR * sd->hflip | ||
| 1652 | | OV7670_MVFP_VFLIP * sd->vflip, | ||
| 1653 | OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP); | ||
| 1654 | if (sd->gspca_dev.streaming) | ||
| 1655 | ov51x_restart(sd); | ||
| 1656 | } | ||
| 1657 | |||
| 1658 | static int set_ov_sensor_window(struct sd *sd) | ||
| 1659 | { | ||
| 1660 | struct gspca_dev *gspca_dev; | ||
| 1661 | int qvga; | ||
| 1688 | int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale; | 1662 | int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale; |
| 1689 | int ret, hstart, hstop, vstop, vstart; | 1663 | int ret, hstart, hstop, vstop, vstart; |
| 1690 | __u8 v; | 1664 | __u8 v; |
| 1691 | 1665 | ||
| 1666 | gspca_dev = &sd->gspca_dev; | ||
| 1667 | qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv; | ||
| 1668 | |||
| 1692 | /* The different sensor ICs handle setting up of window differently. | 1669 | /* The different sensor ICs handle setting up of window differently. |
| 1693 | * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */ | 1670 | * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */ |
| 1694 | switch (sd->sensor) { | 1671 | switch (sd->sensor) { |
| @@ -1733,7 +1710,7 @@ static int set_ov_sensor_window(struct sd *sd, | |||
| 1733 | switch (sd->sensor) { | 1710 | switch (sd->sensor) { |
| 1734 | case SEN_OV6620: | 1711 | case SEN_OV6620: |
| 1735 | case SEN_OV6630: | 1712 | case SEN_OV6630: |
| 1736 | if (win->quarter) { /* QCIF */ | 1713 | if (qvga) { /* QCIF */ |
| 1737 | hwscale = 0; | 1714 | hwscale = 0; |
| 1738 | vwscale = 0; | 1715 | vwscale = 0; |
| 1739 | } else { /* CIF */ | 1716 | } else { /* CIF */ |
| @@ -1743,7 +1720,7 @@ static int set_ov_sensor_window(struct sd *sd, | |||
| 1743 | } | 1720 | } |
| 1744 | break; | 1721 | break; |
| 1745 | case SEN_OV8610: | 1722 | case SEN_OV8610: |
| 1746 | if (win->quarter) { /* QSVGA */ | 1723 | if (qvga) { /* QSVGA */ |
| 1747 | hwscale = 1; | 1724 | hwscale = 1; |
| 1748 | vwscale = 1; | 1725 | vwscale = 1; |
| 1749 | } else { /* SVGA */ | 1726 | } else { /* SVGA */ |
| @@ -1752,7 +1729,7 @@ static int set_ov_sensor_window(struct sd *sd, | |||
| 1752 | } | 1729 | } |
| 1753 | break; | 1730 | break; |
| 1754 | default: /* SEN_OV7xx0 */ | 1731 | default: /* SEN_OV7xx0 */ |
| 1755 | if (win->quarter) { /* QVGA */ | 1732 | if (qvga) { /* QVGA */ |
| 1756 | hwscale = 1; | 1733 | hwscale = 1; |
| 1757 | vwscale = 0; | 1734 | vwscale = 0; |
| 1758 | } else { /* VGA */ | 1735 | } else { /* VGA */ |
| @@ -1761,7 +1738,7 @@ static int set_ov_sensor_window(struct sd *sd, | |||
| 1761 | } | 1738 | } |
| 1762 | } | 1739 | } |
| 1763 | 1740 | ||
| 1764 | ret = mode_init_ov_sensor_regs(sd, win); | 1741 | ret = mode_init_ov_sensor_regs(sd); |
| 1765 | if (ret < 0) | 1742 | if (ret < 0) |
| 1766 | return ret; | 1743 | return ret; |
| 1767 | 1744 | ||
| @@ -1782,7 +1759,7 @@ static int set_ov_sensor_window(struct sd *sd, | |||
| 1782 | /* I can hard code this for OV7670s */ | 1759 | /* I can hard code this for OV7670s */ |
| 1783 | /* Yes, these numbers do look odd, but they're tested and work! */ | 1760 | /* Yes, these numbers do look odd, but they're tested and work! */ |
| 1784 | if (sd->sensor == SEN_OV7670) { | 1761 | if (sd->sensor == SEN_OV7670) { |
| 1785 | if (win->quarter) { /* QVGA from ov7670.c by | 1762 | if (qvga) { /* QVGA from ov7670.c by |
| 1786 | * Jonathan Corbet */ | 1763 | * Jonathan Corbet */ |
| 1787 | hstart = 164; | 1764 | hstart = 164; |
| 1788 | hstop = 20; | 1765 | hstop = 20; |
| @@ -1796,75 +1773,45 @@ static int set_ov_sensor_window(struct sd *sd, | |||
| 1796 | } | 1773 | } |
| 1797 | /* OV7670 hardware window registers are split across | 1774 | /* OV7670 hardware window registers are split across |
| 1798 | * multiple locations */ | 1775 | * multiple locations */ |
| 1799 | i2c_w(sd, OV7670_REG_HSTART, (hstart >> 3) & 0xff); | 1776 | i2c_w(sd, OV7670_REG_HSTART, hstart >> 3); |
| 1800 | i2c_w(sd, OV7670_REG_HSTOP, (hstop >> 3) & 0xff); | 1777 | i2c_w(sd, OV7670_REG_HSTOP, hstop >> 3); |
| 1801 | v = i2c_r(sd, OV7670_REG_HREF); | 1778 | v = i2c_r(sd, OV7670_REG_HREF); |
| 1802 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x07); | 1779 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x07); |
| 1803 | msleep(10); /* need to sleep between read and write to | 1780 | msleep(10); /* need to sleep between read and write to |
| 1804 | * same reg! */ | 1781 | * same reg! */ |
| 1805 | i2c_w(sd, OV7670_REG_HREF, v); | 1782 | i2c_w(sd, OV7670_REG_HREF, v); |
| 1806 | 1783 | ||
| 1807 | i2c_w(sd, OV7670_REG_VSTART, (vstart >> 2) & 0xff); | 1784 | i2c_w(sd, OV7670_REG_VSTART, vstart >> 2); |
| 1808 | i2c_w(sd, OV7670_REG_VSTOP, (vstop >> 2) & 0xff); | 1785 | i2c_w(sd, OV7670_REG_VSTOP, vstop >> 2); |
| 1809 | v = i2c_r(sd, OV7670_REG_VREF); | 1786 | v = i2c_r(sd, OV7670_REG_VREF); |
| 1810 | v = (v & 0xc0) | ((vstop & 0x3) << 2) | (vstart & 0x03); | 1787 | v = (v & 0xc0) | ((vstop & 0x3) << 2) | (vstart & 0x03); |
| 1811 | msleep(10); /* need to sleep between read and write to | 1788 | msleep(10); /* need to sleep between read and write to |
| 1812 | * same reg! */ | 1789 | * same reg! */ |
| 1813 | i2c_w(sd, OV7670_REG_VREF, v); | 1790 | i2c_w(sd, OV7670_REG_VREF, v); |
| 1814 | 1791 | sethvflip(sd); | |
| 1815 | } else { | 1792 | } else { |
| 1816 | i2c_w(sd, 0x17, hwsbase + (win->x >> hwscale)); | 1793 | i2c_w(sd, 0x17, hwsbase); |
| 1817 | i2c_w(sd, 0x18, hwebase + ((win->x + win->width) >> hwscale)); | 1794 | i2c_w(sd, 0x18, hwebase + (sd->gspca_dev.width >> hwscale)); |
| 1818 | i2c_w(sd, 0x19, vwsbase + (win->y >> vwscale)); | 1795 | i2c_w(sd, 0x19, vwsbase); |
| 1819 | i2c_w(sd, 0x1a, vwebase + ((win->y + win->height) >> vwscale)); | 1796 | i2c_w(sd, 0x1a, vwebase + (sd->gspca_dev.height >> vwscale)); |
| 1820 | } | 1797 | } |
| 1821 | return 0; | 1798 | return 0; |
| 1822 | } | 1799 | } |
| 1823 | 1800 | ||
| 1824 | static int ov_sensor_mode_setup(struct sd *sd, | ||
| 1825 | int width, int height) | ||
| 1826 | { | ||
| 1827 | struct ovsensor_window win; | ||
| 1828 | |||
| 1829 | /* win.format = mode; */ | ||
| 1830 | |||
| 1831 | /* Unless subcapture is enabled, | ||
| 1832 | * center the image window and downsample | ||
| 1833 | * if possible to increase the field of view */ | ||
| 1834 | /* NOTE: OV518(+) and OV519 does downsampling on its own */ | ||
| 1835 | win.width = width; | ||
| 1836 | win.height = height; | ||
| 1837 | if (width == sd->maxwidth) | ||
| 1838 | win.quarter = 0; | ||
| 1839 | else | ||
| 1840 | win.quarter = 1; | ||
| 1841 | |||
| 1842 | /* Center it */ | ||
| 1843 | win.x = (win.width - width) / 2; | ||
| 1844 | win.y = (win.height - height) / 2; | ||
| 1845 | |||
| 1846 | /* Clock is determined by OV519 frame rate code */ | ||
| 1847 | win.clockdiv = sd->clockdiv; | ||
| 1848 | |||
| 1849 | PDEBUG(D_CONF, "Setting clock divider to %d", win.clockdiv); | ||
| 1850 | return set_ov_sensor_window(sd, &win); | ||
| 1851 | } | ||
| 1852 | |||
| 1853 | /* -- start the camera -- */ | 1801 | /* -- start the camera -- */ |
| 1854 | static void sd_start(struct gspca_dev *gspca_dev) | 1802 | static void sd_start(struct gspca_dev *gspca_dev) |
| 1855 | { | 1803 | { |
| 1856 | struct sd *sd = (struct sd *) gspca_dev; | 1804 | struct sd *sd = (struct sd *) gspca_dev; |
| 1857 | int ret; | 1805 | int ret; |
| 1858 | 1806 | ||
| 1859 | 1807 | ret = ov519_mode_init_regs(sd); | |
| 1860 | ret = ov519_mode_init_regs(sd, gspca_dev->width, gspca_dev->height); | ||
| 1861 | if (ret < 0) | 1808 | if (ret < 0) |
| 1862 | goto out; | 1809 | goto out; |
| 1863 | ret = ov_sensor_mode_setup(sd, gspca_dev->width, gspca_dev->height); | 1810 | ret = set_ov_sensor_window(sd); |
| 1864 | if (ret < 0) | 1811 | if (ret < 0) |
| 1865 | goto out; | 1812 | goto out; |
| 1866 | 1813 | ||
| 1867 | ret = ov51x_restart((struct sd *) gspca_dev); | 1814 | ret = ov51x_restart(sd); |
| 1868 | if (ret < 0) | 1815 | if (ret < 0) |
| 1869 | goto out; | 1816 | goto out; |
| 1870 | PDEBUG(D_STREAM, "camera started alt: 0x%02x", gspca_dev->alt); | 1817 | PDEBUG(D_STREAM, "camera started alt: 0x%02x", gspca_dev->alt); |
| @@ -1938,12 +1885,10 @@ static void setbrightness(struct gspca_dev *gspca_dev) | |||
| 1938 | { | 1885 | { |
| 1939 | struct sd *sd = (struct sd *) gspca_dev; | 1886 | struct sd *sd = (struct sd *) gspca_dev; |
| 1940 | int val; | 1887 | int val; |
| 1941 | /* int was_streaming; */ | ||
| 1942 | 1888 | ||
| 1943 | val = sd->brightness; | 1889 | val = sd->brightness; |
| 1944 | PDEBUG(D_CONF, "brightness:%d", val); | 1890 | PDEBUG(D_CONF, "brightness:%d", val); |
| 1945 | /* was_streaming = gspca_dev->streaming; | 1891 | /* if (gspca_dev->streaming) |
| 1946 | * if (was_streaming) | ||
| 1947 | * ov51x_stop(sd); */ | 1892 | * ov51x_stop(sd); */ |
| 1948 | switch (sd->sensor) { | 1893 | switch (sd->sensor) { |
| 1949 | case SEN_OV8610: | 1894 | case SEN_OV8610: |
| @@ -1961,12 +1906,12 @@ static void setbrightness(struct gspca_dev *gspca_dev) | |||
| 1961 | i2c_w(sd, OV7610_REG_BRT, val); | 1906 | i2c_w(sd, OV7610_REG_BRT, val); |
| 1962 | break; | 1907 | break; |
| 1963 | case SEN_OV7670: | 1908 | case SEN_OV7670: |
| 1964 | /*jfm - from windblows | 1909 | /*win trace |
| 1965 | * i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_AEC); */ | 1910 | * i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_AEC); */ |
| 1966 | i2c_w(sd, OV7670_REG_BRIGHT, ov7670_abs_to_sm(val)); | 1911 | i2c_w(sd, OV7670_REG_BRIGHT, ov7670_abs_to_sm(val)); |
| 1967 | break; | 1912 | break; |
| 1968 | } | 1913 | } |
| 1969 | /* if (was_streaming) | 1914 | /* if (gspca_dev->streaming) |
| 1970 | * ov51x_restart(sd); */ | 1915 | * ov51x_restart(sd); */ |
| 1971 | } | 1916 | } |
| 1972 | 1917 | ||
| @@ -1974,12 +1919,10 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 1974 | { | 1919 | { |
| 1975 | struct sd *sd = (struct sd *) gspca_dev; | 1920 | struct sd *sd = (struct sd *) gspca_dev; |
| 1976 | int val; | 1921 | int val; |
| 1977 | /* int was_streaming; */ | ||
| 1978 | 1922 | ||
| 1979 | val = sd->contrast; | 1923 | val = sd->contrast; |
| 1980 | PDEBUG(D_CONF, "contrast:%d", val); | 1924 | PDEBUG(D_CONF, "contrast:%d", val); |
| 1981 | /* was_streaming = gspca_dev->streaming; | 1925 | /* if (gspca_dev->streaming) |
| 1982 | if (was_streaming) | ||
| 1983 | ov51x_stop(sd); */ | 1926 | ov51x_stop(sd); */ |
| 1984 | switch (sd->sensor) { | 1927 | switch (sd->sensor) { |
| 1985 | case SEN_OV7610: | 1928 | case SEN_OV7610: |
| @@ -2016,7 +1959,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 2016 | i2c_w(sd, OV7670_REG_CONTRAS, val >> 1); | 1959 | i2c_w(sd, OV7670_REG_CONTRAS, val >> 1); |
| 2017 | break; | 1960 | break; |
| 2018 | } | 1961 | } |
| 2019 | /* if (was_streaming) | 1962 | /* if (gspca_dev->streaming) |
| 2020 | ov51x_restart(sd); */ | 1963 | ov51x_restart(sd); */ |
| 2021 | } | 1964 | } |
| 2022 | 1965 | ||
| @@ -2024,12 +1967,10 @@ static void setcolors(struct gspca_dev *gspca_dev) | |||
| 2024 | { | 1967 | { |
| 2025 | struct sd *sd = (struct sd *) gspca_dev; | 1968 | struct sd *sd = (struct sd *) gspca_dev; |
| 2026 | int val; | 1969 | int val; |
| 2027 | /* int was_streaming; */ | ||
| 2028 | 1970 | ||
| 2029 | val = sd->colors; | 1971 | val = sd->colors; |
| 2030 | PDEBUG(D_CONF, "saturation:%d", val); | 1972 | PDEBUG(D_CONF, "saturation:%d", val); |
| 2031 | /* was_streaming = gspca_dev->streaming; | 1973 | /* if (gspca_dev->streaming) |
| 2032 | if (was_streaming) | ||
| 2033 | ov51x_stop(sd); */ | 1974 | ov51x_stop(sd); */ |
| 2034 | switch (sd->sensor) { | 1975 | switch (sd->sensor) { |
| 2035 | case SEN_OV8610: | 1976 | case SEN_OV8610: |
| @@ -2055,7 +1996,7 @@ static void setcolors(struct gspca_dev *gspca_dev) | |||
| 2055 | /* set REG_COM13 values for UV sat auto mode */ | 1996 | /* set REG_COM13 values for UV sat auto mode */ |
| 2056 | break; | 1997 | break; |
| 2057 | } | 1998 | } |
| 2058 | /* if (was_streaming) | 1999 | /* if (gspca_dev->streaming) |
| 2059 | ov51x_restart(sd); */ | 2000 | ov51x_restart(sd); */ |
| 2060 | } | 2001 | } |
| 2061 | 2002 | ||
| @@ -2110,6 +2051,40 @@ static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val) | |||
| 2110 | return 0; | 2051 | return 0; |
| 2111 | } | 2052 | } |
| 2112 | 2053 | ||
| 2054 | static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val) | ||
| 2055 | { | ||
| 2056 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 2057 | |||
| 2058 | sd->hflip = val; | ||
| 2059 | sethvflip(sd); | ||
| 2060 | return 0; | ||
| 2061 | } | ||
| 2062 | |||
| 2063 | static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val) | ||
| 2064 | { | ||
| 2065 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 2066 | |||
| 2067 | *val = sd->hflip; | ||
| 2068 | return 0; | ||
| 2069 | } | ||
| 2070 | |||
| 2071 | static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val) | ||
| 2072 | { | ||
| 2073 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 2074 | |||
| 2075 | sd->vflip = val; | ||
| 2076 | sethvflip(sd); | ||
| 2077 | return 0; | ||
| 2078 | } | ||
| 2079 | |||
| 2080 | static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val) | ||
| 2081 | { | ||
| 2082 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 2083 | |||
| 2084 | *val = sd->vflip; | ||
| 2085 | return 0; | ||
| 2086 | } | ||
| 2087 | |||
| 2113 | /* sub-driver description */ | 2088 | /* sub-driver description */ |
| 2114 | static const struct sd_desc sd_desc = { | 2089 | static const struct sd_desc sd_desc = { |
| 2115 | .name = MODULE_NAME, | 2090 | .name = MODULE_NAME, |
| @@ -2178,4 +2153,3 @@ module_exit(sd_mod_exit); | |||
| 2178 | 2153 | ||
| 2179 | module_param(frame_rate, int, 0644); | 2154 | module_param(frame_rate, int, 0644); |
| 2180 | MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)"); | 2155 | MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)"); |
| 2181 | |||
diff --git a/drivers/media/video/gspca/pac7311.c b/drivers/media/video/gspca/pac7311.c index ea3d7021f401..815bea6edc44 100644 --- a/drivers/media/video/gspca/pac7311.c +++ b/drivers/media/video/gspca/pac7311.c | |||
| @@ -31,7 +31,9 @@ MODULE_LICENSE("GPL"); | |||
| 31 | struct sd { | 31 | struct sd { |
| 32 | struct gspca_dev gspca_dev; /* !! must be the first item */ | 32 | struct gspca_dev gspca_dev; /* !! must be the first item */ |
| 33 | 33 | ||
| 34 | int avg_lum; | 34 | int lum_sum; |
| 35 | atomic_t avg_lum; | ||
| 36 | atomic_t do_gain; | ||
| 35 | 37 | ||
| 36 | unsigned char brightness; | 38 | unsigned char brightness; |
| 37 | unsigned char contrast; | 39 | unsigned char contrast; |
| @@ -271,6 +273,7 @@ static int sd_config(struct gspca_dev *gspca_dev, | |||
| 271 | sd->contrast = CONTRAST_DEF; | 273 | sd->contrast = CONTRAST_DEF; |
| 272 | sd->colors = COLOR_DEF; | 274 | sd->colors = COLOR_DEF; |
| 273 | sd->autogain = AUTOGAIN_DEF; | 275 | sd->autogain = AUTOGAIN_DEF; |
| 276 | sd->ag_cnt = -1; | ||
| 274 | return 0; | 277 | return 0; |
| 275 | } | 278 | } |
| 276 | 279 | ||
| @@ -311,6 +314,18 @@ static void setcolors(struct gspca_dev *gspca_dev) | |||
| 311 | PDEBUG(D_CONF|D_STREAM, "color: %i", sd->colors); | 314 | PDEBUG(D_CONF|D_STREAM, "color: %i", sd->colors); |
| 312 | } | 315 | } |
| 313 | 316 | ||
| 317 | static void setautogain(struct gspca_dev *gspca_dev) | ||
| 318 | { | ||
| 319 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 320 | |||
| 321 | if (sd->autogain) { | ||
| 322 | sd->lum_sum = 0; | ||
| 323 | sd->ag_cnt = AG_CNT_START; | ||
| 324 | } else { | ||
| 325 | sd->ag_cnt = -1; | ||
| 326 | } | ||
| 327 | } | ||
| 328 | |||
| 314 | /* this function is called at open time */ | 329 | /* this function is called at open time */ |
| 315 | static int sd_open(struct gspca_dev *gspca_dev) | 330 | static int sd_open(struct gspca_dev *gspca_dev) |
| 316 | { | 331 | { |
| @@ -320,8 +335,6 @@ static int sd_open(struct gspca_dev *gspca_dev) | |||
| 320 | 335 | ||
| 321 | static void sd_start(struct gspca_dev *gspca_dev) | 336 | static void sd_start(struct gspca_dev *gspca_dev) |
| 322 | { | 337 | { |
| 323 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 324 | |||
| 325 | reg_w(gspca_dev, 0xff, 0x01); | 338 | reg_w(gspca_dev, 0xff, 0x01); |
| 326 | reg_w_buf(gspca_dev, 0x0002, "\x48\x0a\x40\x08\x00\x00\x08\x00", 8); | 339 | reg_w_buf(gspca_dev, 0x0002, "\x48\x0a\x40\x08\x00\x00\x08\x00", 8); |
| 327 | reg_w_buf(gspca_dev, 0x000a, "\x06\xff\x11\xff\x5a\x30\x90\x4c", 8); | 340 | reg_w_buf(gspca_dev, 0x000a, "\x06\xff\x11\xff\x5a\x30\x90\x4c", 8); |
| @@ -394,6 +407,7 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 394 | setcontrast(gspca_dev); | 407 | setcontrast(gspca_dev); |
| 395 | setbrightness(gspca_dev); | 408 | setbrightness(gspca_dev); |
| 396 | setcolors(gspca_dev); | 409 | setcolors(gspca_dev); |
| 410 | setautogain(gspca_dev); | ||
| 397 | 411 | ||
| 398 | /* set correct resolution */ | 412 | /* set correct resolution */ |
| 399 | switch (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv) { | 413 | switch (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv) { |
| @@ -431,13 +445,6 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 431 | reg_w(gspca_dev, 0xff, 0x01); | 445 | reg_w(gspca_dev, 0xff, 0x01); |
| 432 | reg_w(gspca_dev, 0x78, 0x04); | 446 | reg_w(gspca_dev, 0x78, 0x04); |
| 433 | reg_w(gspca_dev, 0x78, 0x05); | 447 | reg_w(gspca_dev, 0x78, 0x05); |
| 434 | |||
| 435 | if (sd->autogain) { | ||
| 436 | sd->ag_cnt = AG_CNT_START; | ||
| 437 | sd->avg_lum = 0; | ||
| 438 | } else { | ||
| 439 | sd->ag_cnt = -1; | ||
| 440 | } | ||
| 441 | } | 448 | } |
| 442 | 449 | ||
| 443 | static void sd_stopN(struct gspca_dev *gspca_dev) | 450 | static void sd_stopN(struct gspca_dev *gspca_dev) |
| @@ -473,13 +480,20 @@ static void sd_close(struct gspca_dev *gspca_dev) | |||
| 473 | reg_w(gspca_dev, 0x78, 0x44); /* Bit_0=start stream, Bit_7=LED */ | 480 | reg_w(gspca_dev, 0x78, 0x44); /* Bit_0=start stream, Bit_7=LED */ |
| 474 | } | 481 | } |
| 475 | 482 | ||
| 476 | static void setautogain(struct gspca_dev *gspca_dev, int luma) | 483 | static void do_autogain(struct gspca_dev *gspca_dev) |
| 477 | { | 484 | { |
| 485 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 486 | int luma; | ||
| 478 | int luma_mean = 128; | 487 | int luma_mean = 128; |
| 479 | int luma_delta = 20; | 488 | int luma_delta = 20; |
| 480 | __u8 spring = 5; | 489 | __u8 spring = 5; |
| 481 | int Gbright; | 490 | int Gbright; |
| 482 | 491 | ||
| 492 | if (!atomic_read(&sd->do_gain)) | ||
| 493 | return; | ||
| 494 | atomic_set(&sd->do_gain, 0); | ||
| 495 | |||
| 496 | luma = atomic_read(&sd->avg_lum); | ||
| 483 | Gbright = reg_r(gspca_dev, 0x02); | 497 | Gbright = reg_r(gspca_dev, 0x02); |
| 484 | PDEBUG(D_FRAM, "luma mean %d", luma); | 498 | PDEBUG(D_FRAM, "luma mean %d", luma); |
| 485 | if (luma < luma_mean - luma_delta || | 499 | if (luma < luma_mean - luma_delta || |
| @@ -523,12 +537,13 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 523 | 537 | ||
| 524 | /* start of frame */ | 538 | /* start of frame */ |
| 525 | if (sd->ag_cnt >= 0 && p > 28) { | 539 | if (sd->ag_cnt >= 0 && p > 28) { |
| 526 | sd->avg_lum += data[p - 23]; | 540 | sd->lum_sum += data[p - 23]; |
| 527 | if (--sd->ag_cnt < 0) { | 541 | if (--sd->ag_cnt < 0) { |
| 528 | sd->ag_cnt = AG_CNT_START; | 542 | sd->ag_cnt = AG_CNT_START; |
| 529 | setautogain(gspca_dev, | 543 | atomic_set(&sd->avg_lum, |
| 530 | sd->avg_lum / AG_CNT_START); | 544 | sd->lum_sum / AG_CNT_START); |
| 531 | sd->avg_lum = 0; | 545 | sd->lum_sum = 0; |
| 546 | atomic_set(&sd->do_gain, 1); | ||
| 532 | } | 547 | } |
| 533 | } | 548 | } |
| 534 | 549 | ||
| @@ -677,12 +692,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) | |||
| 677 | struct sd *sd = (struct sd *) gspca_dev; | 692 | struct sd *sd = (struct sd *) gspca_dev; |
| 678 | 693 | ||
| 679 | sd->autogain = val; | 694 | sd->autogain = val; |
| 680 | if (val) { | 695 | if (gspca_dev->streaming) |
| 681 | sd->ag_cnt = AG_CNT_START; | 696 | setautogain(gspca_dev); |
| 682 | sd->avg_lum = 0; | ||
| 683 | } else { | ||
| 684 | sd->ag_cnt = -1; | ||
| 685 | } | ||
| 686 | return 0; | 697 | return 0; |
| 687 | } | 698 | } |
| 688 | 699 | ||
| @@ -706,6 +717,7 @@ static struct sd_desc sd_desc = { | |||
| 706 | .stop0 = sd_stop0, | 717 | .stop0 = sd_stop0, |
| 707 | .close = sd_close, | 718 | .close = sd_close, |
| 708 | .pkt_scan = sd_pkt_scan, | 719 | .pkt_scan = sd_pkt_scan, |
| 720 | .dq_callback = do_autogain, | ||
| 709 | }; | 721 | }; |
| 710 | 722 | ||
| 711 | /* -- module initialisation -- */ | 723 | /* -- module initialisation -- */ |
diff --git a/drivers/media/video/gspca/sonixb.c b/drivers/media/video/gspca/sonixb.c index e18748c5a14d..11210c71f66c 100644 --- a/drivers/media/video/gspca/sonixb.c +++ b/drivers/media/video/gspca/sonixb.c | |||
| @@ -408,7 +408,7 @@ static void reg_w(struct gspca_dev *gspca_dev, | |||
| 408 | const __u8 *buffer, | 408 | const __u8 *buffer, |
| 409 | int len) | 409 | int len) |
| 410 | { | 410 | { |
| 411 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 411 | #ifdef GSPCA_DEBUG |
| 412 | if (len > sizeof gspca_dev->usb_buf) { | 412 | if (len > sizeof gspca_dev->usb_buf) { |
| 413 | PDEBUG(D_ERR|D_PACK, "reg_w: buffer overflow"); | 413 | PDEBUG(D_ERR|D_PACK, "reg_w: buffer overflow"); |
| 414 | return; | 414 | return; |
diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c index 33a3df1f6915..245a30ec5fb1 100644 --- a/drivers/media/video/gspca/sonixj.c +++ b/drivers/media/video/gspca/sonixj.c | |||
| @@ -32,7 +32,7 @@ MODULE_LICENSE("GPL"); | |||
| 32 | struct sd { | 32 | struct sd { |
| 33 | struct gspca_dev gspca_dev; /* !! must be the first item */ | 33 | struct gspca_dev gspca_dev; /* !! must be the first item */ |
| 34 | 34 | ||
| 35 | int avg_lum; | 35 | atomic_t avg_lum; |
| 36 | unsigned int exposure; | 36 | unsigned int exposure; |
| 37 | 37 | ||
| 38 | unsigned short brightness; | 38 | unsigned short brightness; |
| @@ -148,55 +148,58 @@ static struct v4l2_pix_format vga_mode[] = { | |||
| 148 | 148 | ||
| 149 | /*Data from sn9c102p+hv71331r */ | 149 | /*Data from sn9c102p+hv71331r */ |
| 150 | static const __u8 sn_hv7131[] = { | 150 | static const __u8 sn_hv7131[] = { |
| 151 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 reg9 */ | 151 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ |
| 152 | 0x00, 0x03, 0x64, 0x00, 0x1A, 0x20, 0x20, 0x20, 0xA1, 0x11, | 152 | 0x00, 0x03, 0x64, 0x00, 0x1a, 0x20, 0x20, 0x20, |
| 153 | /* rega regb regc regd rege regf reg10 reg11 */ | 153 | /* reg8 reg9 rega regb regc regd rege regf */ |
| 154 | 0x02, 0x09, 0x00, 0x00, 0x00, 0x10, 0x03, 0x00, /* 00 */ | 154 | 0xa1, 0x11, 0x02, 0x09, 0x00, 0x00, 0x00, 0x10, |
| 155 | /* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a reg1b */ | 155 | /* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ |
| 156 | 0x00, 0x01, 0x03, 0x28, 0x1e, 0x41, 0x0a, 0x00, 0x00, 0x00, | 156 | 0x03, 0x00, 0x00, 0x01, 0x03, 0x28, 0x1e, 0x41, |
| 157 | /* reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23 */ | 157 | /* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ |
| 158 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 | 158 | 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | static const __u8 sn_mi0360[] = { | 161 | static const __u8 sn_mi0360[] = { |
| 162 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 reg9 */ | 162 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ |
| 163 | 0x00, 0x61, 0x44, 0x00, 0x1a, 0x20, 0x20, 0x20, 0xb1, 0x5d, | 163 | 0x00, 0x61, 0x44, 0x00, 0x1a, 0x20, 0x20, 0x20, |
| 164 | /* rega regb regc regd rege regf reg10 reg11 */ | 164 | /* reg8 reg9 rega regb regc regd rege regf */ |
| 165 | 0x07, 0x00, 0x00, 0x00, 0x00, 0x10, 0x03, 0x00, | 165 | 0xb1, 0x5d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 166 | /* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a reg1b */ | 166 | /* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ |
| 167 | 0x00, 0x02, 0x0a, 0x28, 0x1e, 0x61, 0x06, 0x00, 0x00, 0x00, | 167 | 0x03, 0x00, 0x00, 0x02, 0x0a, 0x28, 0x1e, 0x61, |
| 168 | /* reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23 */ | 168 | /* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ |
| 169 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 | 169 | 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 170 | }; | 170 | }; |
| 171 | 171 | ||
| 172 | static const __u8 sn_mo4000[] = { | 172 | static const __u8 sn_mo4000[] = { |
| 173 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 */ | 173 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ |
| 174 | 0x12, 0x23, 0x60, 0x00, 0x1A, 0x00, 0x20, 0x18, 0x81, | 174 | 0x12, 0x23, 0x60, 0x00, 0x1a, 0x00, 0x20, 0x18, |
| 175 | /* reg9 rega regb regc regd rege regf reg10 reg11*/ | 175 | /* reg8 reg9 rega regb regc regd rege regf */ |
| 176 | 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, | 176 | 0x81, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 177 | /* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a*/ | 177 | /* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ |
| 178 | 0x0b, 0x0f, 0x14, 0x28, 0x1e, 0x40, 0x08, 0x00, 0x00, | 178 | 0x03, 0x00, 0x0b, 0x0f, 0x14, 0x28, 0x1e, 0x40, |
| 179 | /* reg1b reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23*/ | 179 | /* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ |
| 180 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x25, 0x39, 0x4b, | 180 | 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 181 | 0x5c, 0x6b, 0x79, 0x87, 0x95, 0xa2, 0xaf, 0xbb, 0xc7, | ||
| 182 | 0xd3, 0xdf, 0xea, 0xf5 | ||
| 183 | }; | 181 | }; |
| 184 | 182 | ||
| 185 | static const __u8 sn_ov7648[] = { | 183 | static const __u8 sn_ov7648[] = { |
| 186 | 0x00, 0x21, 0x62, 0x00, 0x1a, 0x20, 0x20, 0x20, 0xA1, 0x6E, 0x18, 0x65, | 184 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ |
| 187 | 0x00, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x06, 0x06, 0x28, 0x1E, 0x82, | 185 | 0x00, 0x21, 0x62, 0x00, 0x1a, 0x20, 0x20, 0x20, |
| 188 | 0x07, 0x00, 0x00, 0x00, 0x00, 0x00 | 186 | /* reg8 reg9 rega regb regc regd rege regf */ |
| 187 | 0xa1, 0x6e, 0x18, 0x65, 0x00, 0x00, 0x00, 0x10, | ||
| 188 | /* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ | ||
| 189 | 0x03, 0x00, 0x00, 0x06, 0x06, 0x28, 0x1e, 0x82, | ||
| 190 | /* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ | ||
| 191 | 0x07, 0x00, 0x00, 0x00, 0x00, 0x00 | ||
| 189 | }; | 192 | }; |
| 190 | 193 | ||
| 191 | static const __u8 sn_ov7660[] = { | 194 | static const __u8 sn_ov7660[] = { |
| 192 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 */ | 195 | /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ |
| 193 | 0x00, 0x61, 0x40, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x81, | 196 | 0x00, 0x61, 0x40, 0x00, 0x1a, 0x20, 0x20, 0x20, |
| 194 | /* reg9 rega regb regc regd rege regf reg10 reg11*/ | 197 | /* reg8 reg9 rega regb regc regd rege regf */ |
| 195 | 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, | 198 | 0x81, 0x21, 0x07, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 196 | /* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a*/ | 199 | /* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ |
| 197 | 0x01, 0x01, 0x14, 0x28, 0x1e, 0x00, 0x07, 0x00, 0x00, | 200 | 0x03, 0x00, 0x01, 0x01, 0x08, 0x28, 0x1e, 0x20, |
| 198 | /* reg1b reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23*/ | 201 | /* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ |
| 199 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 | 202 | 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 200 | }; | 203 | }; |
| 201 | 204 | ||
| 202 | /* sequence specific to the sensors - !! index = SENSOR_xxx */ | 205 | /* sequence specific to the sensors - !! index = SENSOR_xxx */ |
| @@ -212,10 +215,6 @@ static const __u8 regsn20[] = { | |||
| 212 | 0x00, 0x2d, 0x46, 0x5a, 0x6c, 0x7c, 0x8b, 0x99, | 215 | 0x00, 0x2d, 0x46, 0x5a, 0x6c, 0x7c, 0x8b, 0x99, |
| 213 | 0xa6, 0xb2, 0xbf, 0xca, 0xd5, 0xe0, 0xeb, 0xf5, 0xff | 216 | 0xa6, 0xb2, 0xbf, 0xca, 0xd5, 0xe0, 0xeb, 0xf5, 0xff |
| 214 | }; | 217 | }; |
| 215 | static const __u8 regsn20_sn9c120[] = { | ||
| 216 | 0x00, 0x25, 0x3c, 0x50, 0x62, 0x72, 0x81, 0x90, | ||
| 217 | 0x9e, 0xab, 0xb8, 0xc5, 0xd1, 0xdd, 0xe9, 0xf4, 0xff | ||
| 218 | }; | ||
| 219 | static const __u8 regsn20_sn9c325[] = { | 218 | static const __u8 regsn20_sn9c325[] = { |
| 220 | 0x0a, 0x3a, 0x56, 0x6c, 0x7e, 0x8d, 0x9a, 0xa4, | 219 | 0x0a, 0x3a, 0x56, 0x6c, 0x7e, 0x8d, 0x9a, 0xa4, |
| 221 | 0xaf, 0xbb, 0xc5, 0xcd, 0xd5, 0xde, 0xe8, 0xed, 0xf5 | 220 | 0xaf, 0xbb, 0xc5, 0xcd, 0xd5, 0xde, 0xe8, 0xed, 0xf5 |
| @@ -227,21 +226,6 @@ static const __u8 reg84[] = { | |||
| 227 | /* 0x00, 0x00, 0x00, 0x00, 0x00 */ | 226 | /* 0x00, 0x00, 0x00, 0x00, 0x00 */ |
| 228 | 0xf7, 0x0f, 0x0a, 0x00, 0x00 | 227 | 0xf7, 0x0f, 0x0a, 0x00, 0x00 |
| 229 | }; | 228 | }; |
| 230 | static const __u8 reg84_sn9c120_1[] = { | ||
| 231 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | ||
| 232 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | ||
| 233 | 0x00, 0x00, 0x0c, 0x00, 0x00 | ||
| 234 | }; | ||
| 235 | static const __u8 reg84_sn9c120_2[] = { | ||
| 236 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | ||
| 237 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | ||
| 238 | 0x00, 0x00, 0x0c, 0x02, 0x3b | ||
| 239 | }; | ||
| 240 | static const __u8 reg84_sn9c120_3[] = { | ||
| 241 | 0x14, 0x00, 0x27, 0x00, 0x08, 0x00, 0xeb, 0x0f, | ||
| 242 | 0xd5, 0x0f, 0x42, 0x00, 0x41, 0x00, 0xca, 0x0f, | ||
| 243 | 0xf5, 0x0f, 0x0c, 0x02, 0x3b | ||
| 244 | }; | ||
| 245 | static const __u8 reg84_sn9c325[] = { | 229 | static const __u8 reg84_sn9c325[] = { |
| 246 | 0x14, 0x00, 0x27, 0x00, 0x07, 0x00, 0xe4, 0x0f, | 230 | 0x14, 0x00, 0x27, 0x00, 0x07, 0x00, 0xe4, 0x0f, |
| 247 | 0xd3, 0x0f, 0x4b, 0x00, 0x48, 0x00, 0xc0, 0x0f, | 231 | 0xd3, 0x0f, 0x4b, 0x00, 0x48, 0x00, 0xc0, 0x0f, |
| @@ -360,17 +344,15 @@ static const __u8 ov7660_sensor_init[][8] = { | |||
| 360 | {0xa1, 0x21, 0x12, 0x80, 0x00, 0x00, 0x00, 0x10}, /* reset SCCB */ | 344 | {0xa1, 0x21, 0x12, 0x80, 0x00, 0x00, 0x00, 0x10}, /* reset SCCB */ |
| 361 | /* (delay 20ms) */ | 345 | /* (delay 20ms) */ |
| 362 | {0xa1, 0x21, 0x12, 0x05, 0x00, 0x00, 0x00, 0x10}, | 346 | {0xa1, 0x21, 0x12, 0x05, 0x00, 0x00, 0x00, 0x10}, |
| 363 | /* Outformat ?? rawRGB */ | 347 | /* Outformat = rawRGB */ |
| 364 | {0xa1, 0x21, 0x13, 0xb8, 0x00, 0x00, 0x00, 0x10}, /* init COM8 */ | 348 | {0xa1, 0x21, 0x13, 0xb8, 0x00, 0x00, 0x00, 0x10}, /* init COM8 */ |
| 365 | {0xd1, 0x21, 0x00, 0x01, 0x74, 0x92, 0x00, 0x10}, | 349 | {0xd1, 0x21, 0x00, 0x01, 0x74, 0x74, 0x00, 0x10}, |
| 366 | /* {0xd1, 0x21, 0x00, 0x01, 0x74, 0x74, 0x00, 0x10}, */ | ||
| 367 | /* GAIN BLUE RED VREF */ | 350 | /* GAIN BLUE RED VREF */ |
| 368 | {0xd1, 0x21, 0x04, 0x00, 0x7d, 0x62, 0x00, 0x10}, | 351 | {0xd1, 0x21, 0x04, 0x00, 0x7d, 0x62, 0x00, 0x10}, |
| 369 | /* COM 1 BAVE GEAVE AECHH */ | 352 | /* COM 1 BAVE GEAVE AECHH */ |
| 370 | {0xb1, 0x21, 0x08, 0x83, 0x01, 0x00, 0x00, 0x10}, /* RAVE COM2 */ | 353 | {0xb1, 0x21, 0x08, 0x83, 0x01, 0x00, 0x00, 0x10}, /* RAVE COM2 */ |
| 371 | {0xd1, 0x21, 0x0c, 0x00, 0x08, 0x04, 0x4f, 0x10}, /* COM 3 4 5 6 */ | 354 | {0xd1, 0x21, 0x0c, 0x00, 0x08, 0x04, 0x4f, 0x10}, /* COM 3 4 5 6 */ |
| 372 | {0xd1, 0x21, 0x10, 0x7f, 0x40, 0x05, 0xf8, 0x10}, | 355 | {0xd1, 0x21, 0x10, 0x7f, 0x40, 0x05, 0xff, 0x10}, |
| 373 | /* {0xd1, 0x21, 0x10, 0x7f, 0x40, 0x05, 0xff, 0x10}, */ | ||
| 374 | /* AECH CLKRC COM7 COM8 */ | 356 | /* AECH CLKRC COM7 COM8 */ |
| 375 | {0xc1, 0x21, 0x14, 0x2c, 0x00, 0x02, 0x00, 0x10}, /* COM9 COM10 */ | 357 | {0xc1, 0x21, 0x14, 0x2c, 0x00, 0x02, 0x00, 0x10}, /* COM9 COM10 */ |
| 376 | {0xd1, 0x21, 0x17, 0x10, 0x60, 0x02, 0x7b, 0x10}, | 358 | {0xd1, 0x21, 0x17, 0x10, 0x60, 0x02, 0x7b, 0x10}, |
| @@ -379,8 +361,8 @@ static const __u8 ov7660_sensor_init[][8] = { | |||
| 379 | {0xb1, 0x21, 0x1e, 0x01, 0x0e, 0x00, 0x00, 0x10}, /* MVFP LAEC */ | 361 | {0xb1, 0x21, 0x1e, 0x01, 0x0e, 0x00, 0x00, 0x10}, /* MVFP LAEC */ |
| 380 | {0xd1, 0x21, 0x20, 0x07, 0x07, 0x07, 0x07, 0x10}, | 362 | {0xd1, 0x21, 0x20, 0x07, 0x07, 0x07, 0x07, 0x10}, |
| 381 | /* BOS GBOS GROS ROS (BGGR offset) */ | 363 | /* BOS GBOS GROS ROS (BGGR offset) */ |
| 382 | {0xd1, 0x21, 0x24, 0x68, 0x58, 0xd4, 0x80, 0x10}, | 364 | /* {0xd1, 0x21, 0x24, 0x68, 0x58, 0xd4, 0x80, 0x10}, */ |
| 383 | /* {0xd1, 0x21, 0x24, 0x78, 0x68, 0xd4, 0x80, 0x10}, */ | 365 | {0xd1, 0x21, 0x24, 0x78, 0x68, 0xd4, 0x80, 0x10}, |
| 384 | /* AEW AEB VPT BBIAS */ | 366 | /* AEW AEB VPT BBIAS */ |
| 385 | {0xd1, 0x21, 0x28, 0x80, 0x30, 0x00, 0x00, 0x10}, | 367 | {0xd1, 0x21, 0x28, 0x80, 0x30, 0x00, 0x00, 0x10}, |
| 386 | /* GbBIAS RSVD EXHCH EXHCL */ | 368 | /* GbBIAS RSVD EXHCH EXHCL */ |
| @@ -407,9 +389,9 @@ static const __u8 ov7660_sensor_init[][8] = { | |||
| 407 | {0xd1, 0x21, 0x62, 0x00, 0x00, 0x50, 0x30, 0x10}, | 389 | {0xd1, 0x21, 0x62, 0x00, 0x00, 0x50, 0x30, 0x10}, |
| 408 | /* LCC1 LCC2 LCC3 LCC4 */ | 390 | /* LCC1 LCC2 LCC3 LCC4 */ |
| 409 | {0xa1, 0x21, 0x66, 0x00, 0x00, 0x00, 0x00, 0x10}, /* LCC5 */ | 391 | {0xa1, 0x21, 0x66, 0x00, 0x00, 0x00, 0x00, 0x10}, /* LCC5 */ |
| 410 | {0xd1, 0x21, 0x67, 0x80, 0x7a, 0x90, 0x80, 0x10}, | 392 | {0xd1, 0x21, 0x67, 0x80, 0x7a, 0x90, 0x80, 0x10}, /* MANU */ |
| 411 | {0xa1, 0x21, 0x6b, 0x0a, 0x00, 0x00, 0x00, 0x10}, | 393 | {0xa1, 0x21, 0x6b, 0x0a, 0x00, 0x00, 0x00, 0x10}, |
| 412 | /* band gap reference [0..3] DBLV */ | 394 | /* band gap reference [0:3] DBLV */ |
| 413 | {0xd1, 0x21, 0x6c, 0x30, 0x48, 0x80, 0x74, 0x10}, /* gamma curve */ | 395 | {0xd1, 0x21, 0x6c, 0x30, 0x48, 0x80, 0x74, 0x10}, /* gamma curve */ |
| 414 | {0xd1, 0x21, 0x70, 0x64, 0x60, 0x5c, 0x58, 0x10}, /* gamma curve */ | 396 | {0xd1, 0x21, 0x70, 0x64, 0x60, 0x5c, 0x58, 0x10}, /* gamma curve */ |
| 415 | {0xd1, 0x21, 0x74, 0x54, 0x4c, 0x40, 0x38, 0x10}, /* gamma curve */ | 397 | {0xd1, 0x21, 0x74, 0x54, 0x4c, 0x40, 0x38, 0x10}, /* gamma curve */ |
| @@ -419,37 +401,35 @@ static const __u8 ov7660_sensor_init[][8] = { | |||
| 419 | {0xd1, 0x21, 0x84, 0x6e, 0x77, 0x87, 0x95, 0x10}, /* gamma curve */ | 401 | {0xd1, 0x21, 0x84, 0x6e, 0x77, 0x87, 0x95, 0x10}, /* gamma curve */ |
| 420 | {0xc1, 0x21, 0x88, 0xaf, 0xc7, 0xdf, 0x00, 0x10}, /* gamma curve */ | 402 | {0xc1, 0x21, 0x88, 0xaf, 0xc7, 0xdf, 0x00, 0x10}, /* gamma curve */ |
| 421 | {0xc1, 0x21, 0x8b, 0x99, 0x99, 0xcf, 0x00, 0x10}, /* reserved */ | 403 | {0xc1, 0x21, 0x8b, 0x99, 0x99, 0xcf, 0x00, 0x10}, /* reserved */ |
| 422 | {0xb1, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x10}, | 404 | {0xb1, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x10}, /* DM_LNL/H */ |
| 423 | /****** (some exchanges in the win trace) ******/ | 405 | /****** (some exchanges in the win trace) ******/ |
| 424 | {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, | 406 | {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, /* MVFP */ |
| 425 | /* bits[3..0]reserved */ | 407 | /* bits[3..0]reserved */ |
| 426 | {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, | 408 | {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, |
| 427 | {0xa1, 0x21, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10}, | 409 | {0xa1, 0x21, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10}, |
| 428 | /* VREF vertical frame ctrl */ | 410 | /* VREF vertical frame ctrl */ |
| 429 | {0xa1, 0x21, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10}, | 411 | {0xa1, 0x21, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10}, |
| 430 | {0xa1, 0x21, 0x10, 0x20, 0x00, 0x00, 0x00, 0x10}, /* 0x20 */ | 412 | {0xa1, 0x21, 0x10, 0x20, 0x00, 0x00, 0x00, 0x10}, /* AECH 0x20 */ |
| 431 | {0xa1, 0x21, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x10}, | 413 | {0xa1, 0x21, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x10}, /* ADVFL */ |
| 432 | {0xa1, 0x21, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x10}, | 414 | {0xa1, 0x21, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x10}, /* ADVFH */ |
| 433 | /* {0xa1, 0x21, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x10}, */ | 415 | {0xa1, 0x21, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x10}, /* GAIN */ |
| 434 | {0xa1, 0x21, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x10}, | 416 | /* {0xb1, 0x21, 0x01, 0x78, 0x78, 0x00, 0x00, 0x10}, * BLUE */ |
| 435 | {0xb1, 0x21, 0x01, 0x78, 0x78, 0x00, 0x00, 0x10}, | ||
| 436 | /****** (some exchanges in the win trace) ******/ | 417 | /****** (some exchanges in the win trace) ******/ |
| 437 | {0xa1, 0x21, 0x93, 0x00, 0x00, 0x00, 0x00, 0x10},/* dummy line hight */ | 418 | {0xa1, 0x21, 0x93, 0x00, 0x00, 0x00, 0x00, 0x10},/* dummy line hight */ |
| 438 | {0xa1, 0x21, 0x92, 0x25, 0x00, 0x00, 0x00, 0x10},/* dummy line low */ | 419 | {0xa1, 0x21, 0x92, 0x25, 0x00, 0x00, 0x00, 0x10}, /* dummy line low */ |
| 439 | {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, | 420 | {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, /* EXHCH */ |
| 440 | {0xa1, 0x21, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x10}, | 421 | {0xa1, 0x21, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x10}, /* EXHCL */ |
| 441 | {0xa1, 0x21, 0x02, 0x90, 0x00, 0x00, 0x00, 0x10}, | 422 | /* {0xa1, 0x21, 0x02, 0x90, 0x00, 0x00, 0x00, 0x10}, * RED */ |
| 442 | /****** (some exchanges in the win trace) ******/ | 423 | /****** (some exchanges in the win trace) ******/ |
| 443 | /**********startsensor KO if changed !!****/ | 424 | /******!! startsensor KO if changed !!****/ |
| 444 | {0xa1, 0x21, 0x93, 0x01, 0x00, 0x00, 0x00, 0x10}, | 425 | {0xa1, 0x21, 0x93, 0x01, 0x00, 0x00, 0x00, 0x10}, |
| 445 | {0xa1, 0x21, 0x92, 0xff, 0x00, 0x00, 0x00, 0x10}, | 426 | {0xa1, 0x21, 0x92, 0xff, 0x00, 0x00, 0x00, 0x10}, |
| 446 | {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, | 427 | {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, |
| 447 | {0xa1, 0x21, 0x2b, 0xc3, 0x00, 0x00, 0x00, 0x10}, | 428 | {0xa1, 0x21, 0x2b, 0xc3, 0x00, 0x00, 0x00, 0x10}, |
| 448 | /* here may start the isoc exchanges */ | ||
| 449 | {} | 429 | {} |
| 450 | }; | 430 | }; |
| 451 | /* reg0x04 reg0x07 reg 0x10 */ | 431 | /* reg 0x04 reg 0x07 reg 0x10 */ |
| 452 | /* expo = (COM1 & 0x02) | (AECHH & 0x2f <<10) [ (AECh << 2) */ | 432 | /* expo = (COM1 & 0x02) | ((AECHH & 0x2f) << 10) | (AECh << 2) */ |
| 453 | 433 | ||
| 454 | static const __u8 ov7648_sensor_init[][8] = { | 434 | static const __u8 ov7648_sensor_init[][8] = { |
| 455 | {0xC1, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00}, | 435 | {0xC1, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00}, |
| @@ -680,13 +660,12 @@ static int configure_gpio(struct gspca_dev *gspca_dev, | |||
| 680 | const __u8 *reg9a; | 660 | const __u8 *reg9a; |
| 681 | static const __u8 reg9a_def[] = | 661 | static const __u8 reg9a_def[] = |
| 682 | {0x08, 0x40, 0x20, 0x10, 0x00, 0x04}; | 662 | {0x08, 0x40, 0x20, 0x10, 0x00, 0x04}; |
| 683 | static const __u8 reg9a_sn9c120[] = /* from win trace */ | ||
| 684 | {0x00, 0x40, 0x38, 0x30, 0x00, 0x20}; | ||
| 685 | static const __u8 reg9a_sn9c325[] = | 663 | static const __u8 reg9a_sn9c325[] = |
| 686 | {0x0a, 0x40, 0x38, 0x30, 0x00, 0x20}; | 664 | {0x0a, 0x40, 0x38, 0x30, 0x00, 0x20}; |
| 665 | static const __u8 regd4[] = {0x60, 0x00, 0x00}; | ||
| 687 | 666 | ||
| 688 | reg_w1(gspca_dev, 0xf1, 0x00); | 667 | reg_w1(gspca_dev, 0xf1, 0x00); |
| 689 | reg_w1(gspca_dev, 0x01, sn9c1xx[0]); /*fixme:jfm was [1] en v1*/ | 668 | reg_w1(gspca_dev, 0x01, 0x00); /*jfm was sn9c1xx[1] in v1*/ |
| 690 | 669 | ||
| 691 | /* configure gpio */ | 670 | /* configure gpio */ |
| 692 | reg_w(gspca_dev, 0x01, &sn9c1xx[1], 2); | 671 | reg_w(gspca_dev, 0x01, &sn9c1xx[1], 2); |
| @@ -696,25 +675,17 @@ static int configure_gpio(struct gspca_dev *gspca_dev, | |||
| 696 | case BRIDGE_SN9C325: | 675 | case BRIDGE_SN9C325: |
| 697 | reg9a = reg9a_sn9c325; | 676 | reg9a = reg9a_sn9c325; |
| 698 | break; | 677 | break; |
| 699 | case BRIDGE_SN9C120: | ||
| 700 | reg9a = reg9a_sn9c120; | ||
| 701 | break; | ||
| 702 | default: | 678 | default: |
| 703 | reg9a = reg9a_def; | 679 | reg9a = reg9a_def; |
| 704 | break; | 680 | break; |
| 705 | } | 681 | } |
| 706 | reg_w(gspca_dev, 0x9a, reg9a, 6); | 682 | reg_w(gspca_dev, 0x9a, reg9a, 6); |
| 707 | 683 | ||
| 708 | reg_w1(gspca_dev, 0xd4, 0x60); /*fixme:jfm 60 00 00 (3) ? */ | 684 | reg_w(gspca_dev, 0xd4, regd4, sizeof regd4); /*fixme:jfm was 60 only*/ |
| 709 | 685 | ||
| 710 | reg_w(gspca_dev, 0x03, &sn9c1xx[3], 0x0f); | 686 | reg_w(gspca_dev, 0x03, &sn9c1xx[3], 0x0f); |
| 711 | 687 | ||
| 712 | switch (sd->bridge) { | 688 | switch (sd->bridge) { |
| 713 | case BRIDGE_SN9C120: /* from win trace */ | ||
| 714 | reg_w1(gspca_dev, 0x01, 0x61); | ||
| 715 | reg_w1(gspca_dev, 0x17, 0x20); | ||
| 716 | reg_w1(gspca_dev, 0x01, 0x60); | ||
| 717 | break; | ||
| 718 | case BRIDGE_SN9C325: | 689 | case BRIDGE_SN9C325: |
| 719 | reg_w1(gspca_dev, 0x01, 0x43); | 690 | reg_w1(gspca_dev, 0x01, 0x43); |
| 720 | reg_w1(gspca_dev, 0x17, 0xae); | 691 | reg_w1(gspca_dev, 0x17, 0xae); |
| @@ -810,6 +781,8 @@ static int sd_config(struct gspca_dev *gspca_dev, | |||
| 810 | sd->contrast = CONTRAST_DEF; | 781 | sd->contrast = CONTRAST_DEF; |
| 811 | sd->colors = COLOR_DEF; | 782 | sd->colors = COLOR_DEF; |
| 812 | sd->autogain = AUTOGAIN_DEF; | 783 | sd->autogain = AUTOGAIN_DEF; |
| 784 | sd->ag_cnt = -1; | ||
| 785 | |||
| 813 | return 0; | 786 | return 0; |
| 814 | } | 787 | } |
| 815 | 788 | ||
| @@ -823,10 +796,11 @@ static int sd_open(struct gspca_dev *gspca_dev) | |||
| 823 | 796 | ||
| 824 | /* setup a selector by bridge */ | 797 | /* setup a selector by bridge */ |
| 825 | reg_w1(gspca_dev, 0xf1, 0x01); | 798 | reg_w1(gspca_dev, 0xf1, 0x01); |
| 826 | reg_r(gspca_dev, 0x00, 1); /* -> regF1 = 0x00 */ | ||
| 827 | reg_w1(gspca_dev, 0xf1, gspca_dev->usb_buf[0]); | ||
| 828 | reg_r(gspca_dev, 0x00, 1); | 799 | reg_r(gspca_dev, 0x00, 1); |
| 800 | reg_w1(gspca_dev, 0xf1, gspca_dev->usb_buf[0]); | ||
| 801 | reg_r(gspca_dev, 0x00, 1); /* get sonix chip id */ | ||
| 829 | regF1 = gspca_dev->usb_buf[0]; | 802 | regF1 = gspca_dev->usb_buf[0]; |
| 803 | PDEBUG(D_PROBE, "Sonix chip id: %02x", regF1); | ||
| 830 | switch (sd->bridge) { | 804 | switch (sd->bridge) { |
| 831 | case BRIDGE_SN9C102P: | 805 | case BRIDGE_SN9C102P: |
| 832 | if (regF1 != 0x11) | 806 | if (regF1 != 0x11) |
| @@ -937,15 +911,10 @@ static void setbrightness(struct gspca_dev *gspca_dev) | |||
| 937 | sd->exposure = setexposure(gspca_dev, expo); | 911 | sd->exposure = setexposure(gspca_dev, expo); |
| 938 | break; | 912 | break; |
| 939 | case SENSOR_MI0360: | 913 | case SENSOR_MI0360: |
| 940 | expo = sd->brightness >> 4; | ||
| 941 | sd->exposure = setexposure(gspca_dev, expo); | ||
| 942 | break; | ||
| 943 | case SENSOR_MO4000: | 914 | case SENSOR_MO4000: |
| 944 | expo = sd->brightness >> 4; | 915 | expo = sd->brightness >> 4; |
| 945 | sd->exposure = setexposure(gspca_dev, expo); | 916 | sd->exposure = setexposure(gspca_dev, expo); |
| 946 | break; | 917 | break; |
| 947 | case SENSOR_OV7660: | ||
| 948 | return; /*jfm??*/ | ||
| 949 | } | 918 | } |
| 950 | 919 | ||
| 951 | k2 = sd->brightness >> 10; | 920 | k2 = sd->brightness >> 10; |
| @@ -958,8 +927,6 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 958 | __u8 k2; | 927 | __u8 k2; |
| 959 | __u8 contrast[] = { 0x00, 0x00, 0x28, 0x00, 0x07, 0x00 }; | 928 | __u8 contrast[] = { 0x00, 0x00, 0x28, 0x00, 0x07, 0x00 }; |
| 960 | 929 | ||
| 961 | if (sd->sensor == SENSOR_OV7660) | ||
| 962 | return; /*jfm??*/ | ||
| 963 | k2 = sd->contrast; | 930 | k2 = sd->contrast; |
| 964 | contrast[2] = k2; | 931 | contrast[2] = k2; |
| 965 | contrast[0] = (k2 + 1) >> 1; | 932 | contrast[0] = (k2 + 1) >> 1; |
| @@ -981,20 +948,32 @@ static void setcolors(struct gspca_dev *gspca_dev) | |||
| 981 | reg_w1(gspca_dev, 0x05, data); | 948 | reg_w1(gspca_dev, 0x05, data); |
| 982 | } | 949 | } |
| 983 | 950 | ||
| 951 | static void setautogain(struct gspca_dev *gspca_dev) | ||
| 952 | { | ||
| 953 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 954 | |||
| 955 | switch (sd->sensor) { | ||
| 956 | case SENSOR_HV7131R: | ||
| 957 | case SENSOR_MO4000: | ||
| 958 | case SENSOR_MI0360: | ||
| 959 | if (sd->autogain) | ||
| 960 | sd->ag_cnt = AG_CNT_START; | ||
| 961 | else | ||
| 962 | sd->ag_cnt = -1; | ||
| 963 | break; | ||
| 964 | } | ||
| 965 | } | ||
| 966 | |||
| 984 | /* -- start the camera -- */ | 967 | /* -- start the camera -- */ |
| 985 | static void sd_start(struct gspca_dev *gspca_dev) | 968 | static void sd_start(struct gspca_dev *gspca_dev) |
| 986 | { | 969 | { |
| 987 | struct sd *sd = (struct sd *) gspca_dev; | 970 | struct sd *sd = (struct sd *) gspca_dev; |
| 988 | int i; | 971 | int i; |
| 989 | __u8 data; | 972 | __u8 reg1, reg17, reg18; |
| 990 | __u8 reg1; | ||
| 991 | __u8 reg17; | ||
| 992 | const __u8 *sn9c1xx; | 973 | const __u8 *sn9c1xx; |
| 993 | int mode; | 974 | int mode; |
| 994 | static const __u8 C0[] = { 0x2d, 0x2d, 0x3a, 0x05, 0x04, 0x3f }; | 975 | static const __u8 C0[] = { 0x2d, 0x2d, 0x3a, 0x05, 0x04, 0x3f }; |
| 995 | static const __u8 CA[] = { 0x28, 0xd8, 0x14, 0xec }; | 976 | static const __u8 CA[] = { 0x28, 0xd8, 0x14, 0xec }; |
| 996 | static const __u8 CA_sn9c120[] = | ||
| 997 | { 0x14, 0xec, 0x0a, 0xf6 }; /* SN9C120 */ | ||
| 998 | static const __u8 CE[] = { 0x32, 0xdd, 0x2d, 0xdd }; /* MI0360 */ | 977 | static const __u8 CE[] = { 0x32, 0xdd, 0x2d, 0xdd }; /* MI0360 */ |
| 999 | static const __u8 CE_sn9c325[] = | 978 | static const __u8 CE_sn9c325[] = |
| 1000 | { 0x32, 0xdd, 0x32, 0xdd }; /* OV7648 - SN9C325 */ | 979 | { 0x32, 0xdd, 0x32, 0xdd }; /* OV7648 - SN9C325 */ |
| @@ -1002,9 +981,7 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 1002 | sn9c1xx = sn_tb[(int) sd->sensor]; | 981 | sn9c1xx = sn_tb[(int) sd->sensor]; |
| 1003 | configure_gpio(gspca_dev, sn9c1xx); | 982 | configure_gpio(gspca_dev, sn9c1xx); |
| 1004 | 983 | ||
| 1005 | /*fixme:jfm this sequence should appear at end of sd_start */ | 984 | /* reg_w1(gspca_dev, 0x01, 0x44); jfm from win trace*/ |
| 1006 | /* with | ||
| 1007 | reg_w1(gspca_dev, 0x01, 0x44); */ | ||
| 1008 | reg_w1(gspca_dev, 0x15, sn9c1xx[0x15]); | 985 | reg_w1(gspca_dev, 0x15, sn9c1xx[0x15]); |
| 1009 | reg_w1(gspca_dev, 0x16, sn9c1xx[0x16]); | 986 | reg_w1(gspca_dev, 0x16, sn9c1xx[0x16]); |
| 1010 | reg_w1(gspca_dev, 0x12, sn9c1xx[0x12]); | 987 | reg_w1(gspca_dev, 0x12, sn9c1xx[0x12]); |
| @@ -1016,20 +993,16 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 1016 | reg_w1(gspca_dev, 0xc7, 0x00); | 993 | reg_w1(gspca_dev, 0xc7, 0x00); |
| 1017 | reg_w1(gspca_dev, 0xc8, 0x50); | 994 | reg_w1(gspca_dev, 0xc8, 0x50); |
| 1018 | reg_w1(gspca_dev, 0xc9, 0x3c); | 995 | reg_w1(gspca_dev, 0xc9, 0x3c); |
| 1019 | /*fixme:jfm end of ending sequence */ | ||
| 1020 | reg_w1(gspca_dev, 0x18, sn9c1xx[0x18]); | 996 | reg_w1(gspca_dev, 0x18, sn9c1xx[0x18]); |
| 1021 | switch (sd->bridge) { | 997 | switch (sd->bridge) { |
| 1022 | case BRIDGE_SN9C325: | 998 | case BRIDGE_SN9C325: |
| 1023 | data = 0xae; | 999 | reg17 = 0xae; |
| 1024 | break; | ||
| 1025 | case BRIDGE_SN9C120: | ||
| 1026 | data = 0xa0; | ||
| 1027 | break; | 1000 | break; |
| 1028 | default: | 1001 | default: |
| 1029 | data = 0x60; | 1002 | reg17 = 0x60; |
| 1030 | break; | 1003 | break; |
| 1031 | } | 1004 | } |
| 1032 | reg_w1(gspca_dev, 0x17, data); | 1005 | reg_w1(gspca_dev, 0x17, reg17); |
| 1033 | reg_w1(gspca_dev, 0x05, sn9c1xx[5]); | 1006 | reg_w1(gspca_dev, 0x05, sn9c1xx[5]); |
| 1034 | reg_w1(gspca_dev, 0x07, sn9c1xx[7]); | 1007 | reg_w1(gspca_dev, 0x07, sn9c1xx[7]); |
| 1035 | reg_w1(gspca_dev, 0x06, sn9c1xx[6]); | 1008 | reg_w1(gspca_dev, 0x06, sn9c1xx[6]); |
| @@ -1044,20 +1017,6 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 1044 | reg_w1(gspca_dev, 0x9a, 0x0a); | 1017 | reg_w1(gspca_dev, 0x9a, 0x0a); |
| 1045 | reg_w1(gspca_dev, 0x99, 0x60); | 1018 | reg_w1(gspca_dev, 0x99, 0x60); |
| 1046 | break; | 1019 | break; |
| 1047 | case BRIDGE_SN9C120: | ||
| 1048 | reg_w(gspca_dev, 0x20, regsn20_sn9c120, | ||
| 1049 | sizeof regsn20_sn9c120); | ||
| 1050 | for (i = 0; i < 2; i++) | ||
| 1051 | reg_w(gspca_dev, 0x84, reg84_sn9c120_1, | ||
| 1052 | sizeof reg84_sn9c120_1); | ||
| 1053 | for (i = 0; i < 6; i++) | ||
| 1054 | reg_w(gspca_dev, 0x84, reg84_sn9c120_2, | ||
| 1055 | sizeof reg84_sn9c120_2); | ||
| 1056 | reg_w(gspca_dev, 0x84, reg84_sn9c120_3, | ||
| 1057 | sizeof reg84_sn9c120_3); | ||
| 1058 | reg_w1(gspca_dev, 0x9a, 0x05); | ||
| 1059 | reg_w1(gspca_dev, 0x99, 0x5b); | ||
| 1060 | break; | ||
| 1061 | default: | 1020 | default: |
| 1062 | reg_w(gspca_dev, 0x20, regsn20, sizeof regsn20); | 1021 | reg_w(gspca_dev, 0x20, regsn20, sizeof regsn20); |
| 1063 | for (i = 0; i < 8; i++) | 1022 | for (i = 0; i < 8; i++) |
| @@ -1107,22 +1066,14 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 1107 | /* reg1 = 0x44; */ | 1066 | /* reg1 = 0x44; */ |
| 1108 | /* reg1 = 0x46; (done) */ | 1067 | /* reg1 = 0x46; (done) */ |
| 1109 | } else { | 1068 | } else { |
| 1110 | reg17 = 0xa2; /* 640 */ | 1069 | reg17 = 0x22; /* 640 MCKSIZE */ |
| 1111 | reg1 = 0x40; | 1070 | reg1 = 0x06; |
| 1112 | } | 1071 | } |
| 1113 | break; | 1072 | break; |
| 1114 | } | 1073 | } |
| 1115 | reg_w(gspca_dev, 0xc0, C0, 6); | 1074 | reg_w(gspca_dev, 0xc0, C0, 6); |
| 1075 | reg_w(gspca_dev, 0xca, CA, 4); | ||
| 1116 | switch (sd->bridge) { | 1076 | switch (sd->bridge) { |
| 1117 | case BRIDGE_SN9C120: /*jfm ?? */ | ||
| 1118 | reg_w(gspca_dev, 0xca, CA_sn9c120, 4); | ||
| 1119 | break; | ||
| 1120 | default: | ||
| 1121 | reg_w(gspca_dev, 0xca, CA, 4); | ||
| 1122 | break; | ||
| 1123 | } | ||
| 1124 | switch (sd->bridge) { | ||
| 1125 | case BRIDGE_SN9C120: /*jfm ?? */ | ||
| 1126 | case BRIDGE_SN9C325: | 1077 | case BRIDGE_SN9C325: |
| 1127 | reg_w(gspca_dev, 0xce, CE_sn9c325, 4); | 1078 | reg_w(gspca_dev, 0xce, CE_sn9c325, 4); |
| 1128 | break; | 1079 | break; |
| @@ -1133,19 +1084,19 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 1133 | } | 1084 | } |
| 1134 | 1085 | ||
| 1135 | /* here change size mode 0 -> VGA; 1 -> CIF */ | 1086 | /* here change size mode 0 -> VGA; 1 -> CIF */ |
| 1136 | data = 0x40 | sn9c1xx[0x18] | (mode << 4); | 1087 | reg18 = sn9c1xx[0x18] | (mode << 4); |
| 1137 | reg_w1(gspca_dev, 0x18, data); | 1088 | reg_w1(gspca_dev, 0x18, reg18 | 0x40); |
| 1138 | 1089 | ||
| 1139 | reg_w(gspca_dev, 0x100, qtable4, 0x40); | 1090 | reg_w(gspca_dev, 0x100, qtable4, 0x40); |
| 1140 | reg_w(gspca_dev, 0x140, qtable4 + 0x40, 0x40); | 1091 | reg_w(gspca_dev, 0x140, qtable4 + 0x40, 0x40); |
| 1141 | 1092 | ||
| 1142 | data = sn9c1xx[0x18] | (mode << 4); | 1093 | reg_w1(gspca_dev, 0x18, reg18); |
| 1143 | reg_w1(gspca_dev, 0x18, data); | ||
| 1144 | 1094 | ||
| 1145 | reg_w1(gspca_dev, 0x17, reg17); | 1095 | reg_w1(gspca_dev, 0x17, reg17); |
| 1146 | reg_w1(gspca_dev, 0x01, reg1); | 1096 | reg_w1(gspca_dev, 0x01, reg1); |
| 1147 | setbrightness(gspca_dev); | 1097 | setbrightness(gspca_dev); |
| 1148 | setcontrast(gspca_dev); | 1098 | setcontrast(gspca_dev); |
| 1099 | setautogain(gspca_dev); | ||
| 1149 | } | 1100 | } |
| 1150 | 1101 | ||
| 1151 | static void sd_stopN(struct gspca_dev *gspca_dev) | 1102 | static void sd_stopN(struct gspca_dev *gspca_dev) |
| @@ -1168,12 +1119,11 @@ static void sd_stopN(struct gspca_dev *gspca_dev) | |||
| 1168 | i2c_w8(gspca_dev, stopmi0360); | 1119 | i2c_w8(gspca_dev, stopmi0360); |
| 1169 | data = 0x29; | 1120 | data = 0x29; |
| 1170 | break; | 1121 | break; |
| 1171 | case SENSOR_MO4000: | ||
| 1172 | break; | ||
| 1173 | case SENSOR_OV7648: | 1122 | case SENSOR_OV7648: |
| 1174 | data = 0x29; | 1123 | data = 0x29; |
| 1175 | break; | 1124 | break; |
| 1176 | default: | 1125 | default: |
| 1126 | /* case SENSOR_MO4000: */ | ||
| 1177 | /* case SENSOR_OV7660: */ | 1127 | /* case SENSOR_OV7660: */ |
| 1178 | break; | 1128 | break; |
| 1179 | } | 1129 | } |
| @@ -1193,16 +1143,23 @@ static void sd_close(struct gspca_dev *gspca_dev) | |||
| 1193 | { | 1143 | { |
| 1194 | } | 1144 | } |
| 1195 | 1145 | ||
| 1196 | static void setautogain(struct gspca_dev *gspca_dev) | 1146 | static void do_autogain(struct gspca_dev *gspca_dev) |
| 1197 | { | 1147 | { |
| 1198 | struct sd *sd = (struct sd *) gspca_dev; | 1148 | struct sd *sd = (struct sd *) gspca_dev; |
| 1199 | /* Thanks S., without your advice, autobright should not work :) */ | ||
| 1200 | int delta; | 1149 | int delta; |
| 1201 | int expotimes = 0; | 1150 | int expotimes; |
| 1202 | __u8 luma_mean = 130; | 1151 | __u8 luma_mean = 130; |
| 1203 | __u8 luma_delta = 20; | 1152 | __u8 luma_delta = 20; |
| 1204 | 1153 | ||
| 1205 | delta = sd->avg_lum; | 1154 | /* Thanks S., without your advice, autobright should not work :) */ |
| 1155 | if (sd->ag_cnt < 0) | ||
| 1156 | return; | ||
| 1157 | if (--sd->ag_cnt >= 0) | ||
| 1158 | return; | ||
| 1159 | sd->ag_cnt = AG_CNT_START; | ||
| 1160 | |||
| 1161 | delta = atomic_read(&sd->avg_lum); | ||
| 1162 | PDEBUG(D_FRAM, "mean lum %d", delta); | ||
| 1206 | if (delta < luma_mean - luma_delta || | 1163 | if (delta < luma_mean - luma_delta || |
| 1207 | delta > luma_mean + luma_delta) { | 1164 | delta > luma_mean + luma_delta) { |
| 1208 | switch (sd->sensor) { | 1165 | switch (sd->sensor) { |
| @@ -1214,8 +1171,9 @@ static void setautogain(struct gspca_dev *gspca_dev) | |||
| 1214 | sd->exposure = setexposure(gspca_dev, | 1171 | sd->exposure = setexposure(gspca_dev, |
| 1215 | (unsigned int) (expotimes << 8)); | 1172 | (unsigned int) (expotimes << 8)); |
| 1216 | break; | 1173 | break; |
| 1217 | case SENSOR_MO4000: | 1174 | default: |
| 1218 | case SENSOR_MI0360: | 1175 | /* case SENSOR_MO4000: */ |
| 1176 | /* case SENSOR_MI0360: */ | ||
| 1219 | expotimes = sd->exposure; | 1177 | expotimes = sd->exposure; |
| 1220 | expotimes += (luma_mean - delta) >> 6; | 1178 | expotimes += (luma_mean - delta) >> 6; |
| 1221 | if (expotimes < 0) | 1179 | if (expotimes < 0) |
| @@ -1228,6 +1186,8 @@ static void setautogain(struct gspca_dev *gspca_dev) | |||
| 1228 | } | 1186 | } |
| 1229 | } | 1187 | } |
| 1230 | 1188 | ||
| 1189 | /* scan the URB packets */ | ||
| 1190 | /* This function is run at interrupt level. */ | ||
| 1231 | static void sd_pkt_scan(struct gspca_dev *gspca_dev, | 1191 | static void sd_pkt_scan(struct gspca_dev *gspca_dev, |
| 1232 | struct gspca_frame *frame, /* target */ | 1192 | struct gspca_frame *frame, /* target */ |
| 1233 | __u8 *data, /* isoc packet */ | 1193 | __u8 *data, /* isoc packet */ |
| @@ -1244,9 +1204,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 1244 | frame, data, sof + 2); | 1204 | frame, data, sof + 2); |
| 1245 | if (sd->ag_cnt < 0) | 1205 | if (sd->ag_cnt < 0) |
| 1246 | return; | 1206 | return; |
| 1247 | if (--sd->ag_cnt >= 0) | ||
| 1248 | return; | ||
| 1249 | sd->ag_cnt = AG_CNT_START; | ||
| 1250 | /* w1 w2 w3 */ | 1207 | /* w1 w2 w3 */ |
| 1251 | /* w4 w5 w6 */ | 1208 | /* w4 w5 w6 */ |
| 1252 | /* w7 w8 */ | 1209 | /* w7 w8 */ |
| @@ -1261,9 +1218,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 1261 | /* w5 */ | 1218 | /* w5 */ |
| 1262 | avg_lum += ((data[sof + 31] << 8) | data[sof + 32]) >> 4; | 1219 | avg_lum += ((data[sof + 31] << 8) | data[sof + 32]) >> 4; |
| 1263 | avg_lum >>= 4; | 1220 | avg_lum >>= 4; |
| 1264 | sd->avg_lum = avg_lum; | 1221 | atomic_set(&sd->avg_lum, avg_lum); |
| 1265 | PDEBUG(D_PACK, "mean lum %d", avg_lum); | ||
| 1266 | setautogain(gspca_dev); | ||
| 1267 | return; | 1222 | return; |
| 1268 | } | 1223 | } |
| 1269 | if (gspca_dev->last_packet_type == LAST_PACKET) { | 1224 | if (gspca_dev->last_packet_type == LAST_PACKET) { |
| @@ -1300,6 +1255,7 @@ static unsigned int getexposure(struct gspca_dev *gspca_dev) | |||
| 1300 | (hexpo << 10) | (mexpo << 2) | lexpo); | 1255 | (hexpo << 10) | (mexpo << 2) | lexpo); |
| 1301 | return (hexpo << 10) | (mexpo << 2) | lexpo; | 1256 | return (hexpo << 10) | (mexpo << 2) | lexpo; |
| 1302 | default: | 1257 | default: |
| 1258 | /* case SENSOR_OV7648: * jfm: is it ok for 7648? */ | ||
| 1303 | /* case SENSOR_OV7660: */ | 1259 | /* case SENSOR_OV7660: */ |
| 1304 | /* read sensor exposure */ | 1260 | /* read sensor exposure */ |
| 1305 | i2c_r5(gspca_dev, 0x04); | 1261 | i2c_r5(gspca_dev, 0x04); |
| @@ -1318,14 +1274,12 @@ static void getbrightness(struct gspca_dev *gspca_dev) | |||
| 1318 | /* hardcoded registers seem not readable */ | 1274 | /* hardcoded registers seem not readable */ |
| 1319 | switch (sd->sensor) { | 1275 | switch (sd->sensor) { |
| 1320 | case SENSOR_HV7131R: | 1276 | case SENSOR_HV7131R: |
| 1321 | /* sd->brightness = 0x7fff; */ | ||
| 1322 | sd->brightness = getexposure(gspca_dev) >> 4; | 1277 | sd->brightness = getexposure(gspca_dev) >> 4; |
| 1323 | break; | 1278 | break; |
| 1324 | case SENSOR_MI0360: | 1279 | case SENSOR_MI0360: |
| 1325 | sd->brightness = getexposure(gspca_dev) << 4; | 1280 | sd->brightness = getexposure(gspca_dev) << 4; |
| 1326 | break; | 1281 | break; |
| 1327 | case SENSOR_MO4000: | 1282 | case SENSOR_MO4000: |
| 1328 | /* sd->brightness = 0x1fff; */ | ||
| 1329 | sd->brightness = getexposure(gspca_dev) << 4; | 1283 | sd->brightness = getexposure(gspca_dev) << 4; |
| 1330 | break; | 1284 | break; |
| 1331 | } | 1285 | } |
| @@ -1391,10 +1345,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) | |||
| 1391 | struct sd *sd = (struct sd *) gspca_dev; | 1345 | struct sd *sd = (struct sd *) gspca_dev; |
| 1392 | 1346 | ||
| 1393 | sd->autogain = val; | 1347 | sd->autogain = val; |
| 1394 | if (val) | 1348 | if (gspca_dev->streaming) |
| 1395 | sd->ag_cnt = AG_CNT_START; | 1349 | setautogain(gspca_dev); |
| 1396 | else | ||
| 1397 | sd->ag_cnt = -1; | ||
| 1398 | return 0; | 1350 | return 0; |
| 1399 | } | 1351 | } |
| 1400 | 1352 | ||
| @@ -1418,6 +1370,7 @@ static const struct sd_desc sd_desc = { | |||
| 1418 | .stop0 = sd_stop0, | 1370 | .stop0 = sd_stop0, |
| 1419 | .close = sd_close, | 1371 | .close = sd_close, |
| 1420 | .pkt_scan = sd_pkt_scan, | 1372 | .pkt_scan = sd_pkt_scan, |
| 1373 | .dq_callback = do_autogain, | ||
| 1421 | }; | 1374 | }; |
| 1422 | 1375 | ||
| 1423 | /* -- module initialisation -- */ | 1376 | /* -- module initialisation -- */ |
diff --git a/drivers/media/video/gspca/spca505.c b/drivers/media/video/gspca/spca505.c index 3c2be80cbd65..eda29d609359 100644 --- a/drivers/media/video/gspca/spca505.c +++ b/drivers/media/video/gspca/spca505.c | |||
| @@ -61,27 +61,27 @@ static struct ctrl sd_ctrls[] = { | |||
| 61 | 61 | ||
| 62 | static struct v4l2_pix_format vga_mode[] = { | 62 | static struct v4l2_pix_format vga_mode[] = { |
| 63 | {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 63 | {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 64 | .bytesperline = 160 * 3, | 64 | .bytesperline = 160, |
| 65 | .sizeimage = 160 * 120 * 3 / 2, | 65 | .sizeimage = 160 * 120 * 3 / 2, |
| 66 | .colorspace = V4L2_COLORSPACE_SRGB, | 66 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 67 | .priv = 5}, | 67 | .priv = 5}, |
| 68 | {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 68 | {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 69 | .bytesperline = 176 * 3, | 69 | .bytesperline = 176, |
| 70 | .sizeimage = 176 * 144 * 3 / 2, | 70 | .sizeimage = 176 * 144 * 3 / 2, |
| 71 | .colorspace = V4L2_COLORSPACE_SRGB, | 71 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 72 | .priv = 4}, | 72 | .priv = 4}, |
| 73 | {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 73 | {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 74 | .bytesperline = 320 * 3, | 74 | .bytesperline = 320, |
| 75 | .sizeimage = 320 * 240 * 3 / 2, | 75 | .sizeimage = 320 * 240 * 3 / 2, |
| 76 | .colorspace = V4L2_COLORSPACE_SRGB, | 76 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 77 | .priv = 2}, | 77 | .priv = 2}, |
| 78 | {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 78 | {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 79 | .bytesperline = 352 * 3, | 79 | .bytesperline = 352, |
| 80 | .sizeimage = 352 * 288 * 3 / 2, | 80 | .sizeimage = 352 * 288 * 3 / 2, |
| 81 | .colorspace = V4L2_COLORSPACE_SRGB, | 81 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 82 | .priv = 1}, | 82 | .priv = 1}, |
| 83 | {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 83 | {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 84 | .bytesperline = 640 * 3, | 84 | .bytesperline = 640, |
| 85 | .sizeimage = 640 * 480 * 3 / 2, | 85 | .sizeimage = 640 * 480 * 3 / 2, |
| 86 | .colorspace = V4L2_COLORSPACE_SRGB, | 86 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 87 | .priv = 0}, | 87 | .priv = 0}, |
| @@ -776,7 +776,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 776 | default: | 776 | default: |
| 777 | data += 1; | 777 | data += 1; |
| 778 | len -= 1; | 778 | len -= 1; |
| 779 | gspca_frame_add(gspca_dev, FIRST_PACKET, frame, | 779 | gspca_frame_add(gspca_dev, INTER_PACKET, frame, |
| 780 | data, len); | 780 | data, len); |
| 781 | break; | 781 | break; |
| 782 | } | 782 | } |
diff --git a/drivers/media/video/gspca/spca506.c b/drivers/media/video/gspca/spca506.c index 6fe715c80ad2..f622fa75766d 100644 --- a/drivers/media/video/gspca/spca506.c +++ b/drivers/media/video/gspca/spca506.c | |||
| @@ -112,27 +112,27 @@ static struct ctrl sd_ctrls[] = { | |||
| 112 | 112 | ||
| 113 | static struct v4l2_pix_format vga_mode[] = { | 113 | static struct v4l2_pix_format vga_mode[] = { |
| 114 | {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 114 | {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 115 | .bytesperline = 160 * 3, | 115 | .bytesperline = 160, |
| 116 | .sizeimage = 160 * 120 * 3 / 2, | 116 | .sizeimage = 160 * 120 * 3 / 2, |
| 117 | .colorspace = V4L2_COLORSPACE_SRGB, | 117 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 118 | .priv = 5}, | 118 | .priv = 5}, |
| 119 | {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 119 | {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 120 | .bytesperline = 176 * 3, | 120 | .bytesperline = 176, |
| 121 | .sizeimage = 176 * 144 * 3 / 2, | 121 | .sizeimage = 176 * 144 * 3 / 2, |
| 122 | .colorspace = V4L2_COLORSPACE_SRGB, | 122 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 123 | .priv = 4}, | 123 | .priv = 4}, |
| 124 | {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 124 | {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 125 | .bytesperline = 320 * 3, | 125 | .bytesperline = 320, |
| 126 | .sizeimage = 320 * 240 * 3 / 2, | 126 | .sizeimage = 320 * 240 * 3 / 2, |
| 127 | .colorspace = V4L2_COLORSPACE_SRGB, | 127 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 128 | .priv = 2}, | 128 | .priv = 2}, |
| 129 | {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 129 | {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 130 | .bytesperline = 352 * 3, | 130 | .bytesperline = 352, |
| 131 | .sizeimage = 352 * 288 * 3 / 2, | 131 | .sizeimage = 352 * 288 * 3 / 2, |
| 132 | .colorspace = V4L2_COLORSPACE_SRGB, | 132 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 133 | .priv = 1}, | 133 | .priv = 1}, |
| 134 | {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, | 134 | {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, |
| 135 | .bytesperline = 640 * 3, | 135 | .bytesperline = 640, |
| 136 | .sizeimage = 640 * 480 * 3 / 2, | 136 | .sizeimage = 640 * 480 * 3 / 2, |
| 137 | .colorspace = V4L2_COLORSPACE_SRGB, | 137 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 138 | .priv = 0}, | 138 | .priv = 0}, |
| @@ -588,7 +588,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 588 | default: | 588 | default: |
| 589 | data += 1; | 589 | data += 1; |
| 590 | len -= 1; | 590 | len -= 1; |
| 591 | gspca_frame_add(gspca_dev, FIRST_PACKET, frame, | 591 | gspca_frame_add(gspca_dev, INTER_PACKET, frame, |
| 592 | data, len); | 592 | data, len); |
| 593 | break; | 593 | break; |
| 594 | } | 594 | } |
diff --git a/drivers/media/video/gspca/spca508.c b/drivers/media/video/gspca/spca508.c index b608a27ad115..699340c17dea 100644 --- a/drivers/media/video/gspca/spca508.c +++ b/drivers/media/video/gspca/spca508.c | |||
| @@ -63,23 +63,23 @@ static struct ctrl sd_ctrls[] = { | |||
| 63 | }; | 63 | }; |
| 64 | 64 | ||
| 65 | static struct v4l2_pix_format sif_mode[] = { | 65 | static struct v4l2_pix_format sif_mode[] = { |
| 66 | {160, 120, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, | 66 | {160, 120, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, |
| 67 | .bytesperline = 160 * 3, | 67 | .bytesperline = 160, |
| 68 | .sizeimage = 160 * 120 * 3 / 2, | 68 | .sizeimage = 160 * 120 * 3 / 2, |
| 69 | .colorspace = V4L2_COLORSPACE_SRGB, | 69 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 70 | .priv = 3}, | 70 | .priv = 3}, |
| 71 | {176, 144, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, | 71 | {176, 144, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, |
| 72 | .bytesperline = 176 * 3, | 72 | .bytesperline = 176, |
| 73 | .sizeimage = 176 * 144 * 3 / 2, | 73 | .sizeimage = 176 * 144 * 3 / 2, |
| 74 | .colorspace = V4L2_COLORSPACE_SRGB, | 74 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 75 | .priv = 2}, | 75 | .priv = 2}, |
| 76 | {320, 240, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, | 76 | {320, 240, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, |
| 77 | .bytesperline = 320 * 3, | 77 | .bytesperline = 320, |
| 78 | .sizeimage = 320 * 240 * 3 / 2, | 78 | .sizeimage = 320 * 240 * 3 / 2, |
| 79 | .colorspace = V4L2_COLORSPACE_SRGB, | 79 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 80 | .priv = 1}, | 80 | .priv = 1}, |
| 81 | {352, 288, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, | 81 | {352, 288, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, |
| 82 | .bytesperline = 352 * 3, | 82 | .bytesperline = 352, |
| 83 | .sizeimage = 352 * 288 * 3 / 2, | 83 | .sizeimage = 352 * 288 * 3 / 2, |
| 84 | .colorspace = V4L2_COLORSPACE_SRGB, | 84 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 85 | .priv = 0}, | 85 | .priv = 0}, |
| @@ -1583,7 +1583,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 1583 | default: | 1583 | default: |
| 1584 | data += 1; | 1584 | data += 1; |
| 1585 | len -= 1; | 1585 | len -= 1; |
| 1586 | gspca_frame_add(gspca_dev, FIRST_PACKET, frame, | 1586 | gspca_frame_add(gspca_dev, INTER_PACKET, frame, |
| 1587 | data, len); | 1587 | data, len); |
| 1588 | break; | 1588 | break; |
| 1589 | } | 1589 | } |
diff --git a/drivers/media/video/gspca/spca561.c b/drivers/media/video/gspca/spca561.c index a26174508cb9..1073ac3d2ec6 100644 --- a/drivers/media/video/gspca/spca561.c +++ b/drivers/media/video/gspca/spca561.c | |||
| @@ -644,6 +644,18 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 644 | } | 644 | } |
| 645 | } | 645 | } |
| 646 | 646 | ||
| 647 | static void setautogain(struct gspca_dev *gspca_dev) | ||
| 648 | { | ||
| 649 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 650 | |||
| 651 | if (sd->chip_revision == Rev072A) { | ||
| 652 | if (sd->autogain) | ||
| 653 | sd->ag_cnt = AG_CNT_START; | ||
| 654 | else | ||
| 655 | sd->ag_cnt = -1; | ||
| 656 | } | ||
| 657 | } | ||
| 658 | |||
| 647 | static void sd_start(struct gspca_dev *gspca_dev) | 659 | static void sd_start(struct gspca_dev *gspca_dev) |
| 648 | { | 660 | { |
| 649 | struct sd *sd = (struct sd *) gspca_dev; | 661 | struct sd *sd = (struct sd *) gspca_dev; |
| @@ -671,6 +683,7 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
| 671 | reg_w_val(dev, 0x8500, mode); /* mode */ | 683 | reg_w_val(dev, 0x8500, mode); /* mode */ |
| 672 | reg_w_val(dev, 0x8700, Clck); /* 0x27 clock */ | 684 | reg_w_val(dev, 0x8700, Clck); /* 0x27 clock */ |
| 673 | reg_w_val(dev, 0x8112, 0x10 | 0x20); | 685 | reg_w_val(dev, 0x8112, 0x10 | 0x20); |
| 686 | setautogain(gspca_dev); | ||
| 674 | break; | 687 | break; |
| 675 | default: | 688 | default: |
| 676 | /* case Rev012A: */ | 689 | /* case Rev012A: */ |
| @@ -720,18 +733,24 @@ static void sd_close(struct gspca_dev *gspca_dev) | |||
| 720 | reg_w_val(gspca_dev->dev, 0x8114, 0); | 733 | reg_w_val(gspca_dev->dev, 0x8114, 0); |
| 721 | } | 734 | } |
| 722 | 735 | ||
| 723 | static void setautogain(struct gspca_dev *gspca_dev) | 736 | static void do_autogain(struct gspca_dev *gspca_dev) |
| 724 | { | 737 | { |
| 725 | struct sd *sd = (struct sd *) gspca_dev; | 738 | struct sd *sd = (struct sd *) gspca_dev; |
| 726 | int expotimes = 0; | 739 | int expotimes; |
| 727 | int pixelclk = 0; | 740 | int pixelclk; |
| 728 | int gainG = 0; | 741 | int gainG; |
| 729 | __u8 R, Gr, Gb, B; | 742 | __u8 R, Gr, Gb, B; |
| 730 | int y; | 743 | int y; |
| 731 | __u8 luma_mean = 110; | 744 | __u8 luma_mean = 110; |
| 732 | __u8 luma_delta = 20; | 745 | __u8 luma_delta = 20; |
| 733 | __u8 spring = 4; | 746 | __u8 spring = 4; |
| 734 | 747 | ||
| 748 | if (sd->ag_cnt < 0) | ||
| 749 | return; | ||
| 750 | if (--sd->ag_cnt >= 0) | ||
| 751 | return; | ||
| 752 | sd->ag_cnt = AG_CNT_START; | ||
| 753 | |||
| 735 | switch (sd->chip_revision) { | 754 | switch (sd->chip_revision) { |
| 736 | case Rev072A: | 755 | case Rev072A: |
| 737 | reg_r(gspca_dev, 0x8621, 1); | 756 | reg_r(gspca_dev, 0x8621, 1); |
| @@ -795,18 +814,10 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, | |||
| 795 | __u8 *data, /* isoc packet */ | 814 | __u8 *data, /* isoc packet */ |
| 796 | int len) /* iso packet length */ | 815 | int len) /* iso packet length */ |
| 797 | { | 816 | { |
| 798 | struct sd *sd = (struct sd *) gspca_dev; | ||
| 799 | |||
| 800 | switch (data[0]) { | 817 | switch (data[0]) { |
| 801 | case 0: /* start of frame */ | 818 | case 0: /* start of frame */ |
| 802 | frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, | 819 | frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, |
| 803 | data, 0); | 820 | data, 0); |
| 804 | if (sd->ag_cnt >= 0) { | ||
| 805 | if (--sd->ag_cnt < 0) { | ||
| 806 | sd->ag_cnt = AG_CNT_START; | ||
| 807 | setautogain(gspca_dev); | ||
| 808 | } | ||
| 809 | } | ||
| 810 | data += SPCA561_OFFSET_DATA; | 821 | data += SPCA561_OFFSET_DATA; |
| 811 | len -= SPCA561_OFFSET_DATA; | 822 | len -= SPCA561_OFFSET_DATA; |
| 812 | if (data[1] & 0x10) { | 823 | if (data[1] & 0x10) { |
| @@ -944,10 +955,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) | |||
| 944 | struct sd *sd = (struct sd *) gspca_dev; | 955 | struct sd *sd = (struct sd *) gspca_dev; |
| 945 | 956 | ||
| 946 | sd->autogain = val; | 957 | sd->autogain = val; |
| 947 | if (val) | 958 | if (gspca_dev->streaming) |
| 948 | sd->ag_cnt = AG_CNT_START; | 959 | setautogain(gspca_dev); |
| 949 | else | ||
| 950 | sd->ag_cnt = -1; | ||
| 951 | return 0; | 960 | return 0; |
| 952 | } | 961 | } |
| 953 | 962 | ||
| @@ -971,6 +980,7 @@ static const struct sd_desc sd_desc = { | |||
| 971 | .stop0 = sd_stop0, | 980 | .stop0 = sd_stop0, |
| 972 | .close = sd_close, | 981 | .close = sd_close, |
| 973 | .pkt_scan = sd_pkt_scan, | 982 | .pkt_scan = sd_pkt_scan, |
| 983 | .dq_callback = do_autogain, | ||
| 974 | }; | 984 | }; |
| 975 | 985 | ||
| 976 | /* -- module initialisation -- */ | 986 | /* -- module initialisation -- */ |
diff --git a/drivers/media/video/gspca/vc032x.c b/drivers/media/video/gspca/vc032x.c index a4221753e1bf..f4a52956e0d9 100644 --- a/drivers/media/video/gspca/vc032x.c +++ b/drivers/media/video/gspca/vc032x.c | |||
| @@ -88,12 +88,12 @@ static struct ctrl sd_ctrls[] = { | |||
| 88 | 88 | ||
| 89 | static struct v4l2_pix_format vc0321_mode[] = { | 89 | static struct v4l2_pix_format vc0321_mode[] = { |
| 90 | {320, 240, V4L2_PIX_FMT_YUV420, V4L2_FIELD_NONE, | 90 | {320, 240, V4L2_PIX_FMT_YUV420, V4L2_FIELD_NONE, |
| 91 | .bytesperline = 320 * 2, | 91 | .bytesperline = 320, |
| 92 | .sizeimage = 320 * 240 * 2, | 92 | .sizeimage = 320 * 240 * 2, |
| 93 | .colorspace = V4L2_COLORSPACE_SRGB, | 93 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 94 | .priv = 1}, | 94 | .priv = 1}, |
| 95 | {640, 480, V4L2_PIX_FMT_YUV420, V4L2_FIELD_NONE, | 95 | {640, 480, V4L2_PIX_FMT_YUV420, V4L2_FIELD_NONE, |
| 96 | .bytesperline = 640 * 2, | 96 | .bytesperline = 640, |
| 97 | .sizeimage = 640 * 480 * 2, | 97 | .sizeimage = 640 * 480 * 2, |
| 98 | .colorspace = V4L2_COLORSPACE_SRGB, | 98 | .colorspace = V4L2_COLORSPACE_SRGB, |
| 99 | .priv = 0}, | 99 | .priv = 0}, |
diff --git a/drivers/media/video/gspca/zc3xx.c b/drivers/media/video/gspca/zc3xx.c index 22a994ccb1d5..bc7d0eedcd81 100644 --- a/drivers/media/video/gspca/zc3xx.c +++ b/drivers/media/video/gspca/zc3xx.c | |||
| @@ -6469,7 +6469,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 6469 | NULL, Tgradient_1, Tgradient_2, | 6469 | NULL, Tgradient_1, Tgradient_2, |
| 6470 | Tgradient_3, Tgradient_4, Tgradient_5, Tgradient_6 | 6470 | Tgradient_3, Tgradient_4, Tgradient_5, Tgradient_6 |
| 6471 | }; | 6471 | }; |
| 6472 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 6472 | #ifdef GSPCA_DEBUG |
| 6473 | __u8 v[16]; | 6473 | __u8 v[16]; |
| 6474 | #endif | 6474 | #endif |
| 6475 | 6475 | ||
| @@ -6487,7 +6487,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 6487 | else if (g <= 0) | 6487 | else if (g <= 0) |
| 6488 | g = 1; | 6488 | g = 1; |
| 6489 | reg_w(dev, g, 0x0120 + i); /* gamma */ | 6489 | reg_w(dev, g, 0x0120 + i); /* gamma */ |
| 6490 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 6490 | #ifdef GSPCA_DEBUG |
| 6491 | if (gspca_debug & D_CONF) | 6491 | if (gspca_debug & D_CONF) |
| 6492 | v[i] = g; | 6492 | v[i] = g; |
| 6493 | #endif | 6493 | #endif |
| @@ -6507,7 +6507,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
| 6507 | g = 1; | 6507 | g = 1; |
| 6508 | } | 6508 | } |
| 6509 | reg_w(dev, g, 0x0130 + i); /* gradient */ | 6509 | reg_w(dev, g, 0x0130 + i); /* gradient */ |
| 6510 | #ifdef CONFIG_VIDEO_ADV_DEBUG | 6510 | #ifdef GSPCA_DEBUG |
| 6511 | if (gspca_debug & D_CONF) | 6511 | if (gspca_debug & D_CONF) |
| 6512 | v[i] = g; | 6512 | v[i] = g; |
| 6513 | #endif | 6513 | #endif |
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index 5e7ebca1968e..388cf94055d3 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c | |||
| @@ -128,6 +128,8 @@ struct pxa_camera_dev { | |||
| 128 | 128 | ||
| 129 | struct pxa_buffer *active; | 129 | struct pxa_buffer *active; |
| 130 | struct pxa_dma_desc *sg_tail[3]; | 130 | struct pxa_dma_desc *sg_tail[3]; |
| 131 | |||
| 132 | u32 save_cicr[5]; | ||
| 131 | }; | 133 | }; |
| 132 | 134 | ||
| 133 | static const char *pxa_cam_driver_description = "PXA_Camera"; | 135 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
| @@ -997,10 +999,64 @@ static int pxa_camera_querycap(struct soc_camera_host *ici, | |||
| 997 | return 0; | 999 | return 0; |
| 998 | } | 1000 | } |
| 999 | 1001 | ||
| 1002 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) | ||
| 1003 | { | ||
| 1004 | struct soc_camera_host *ici = | ||
| 1005 | to_soc_camera_host(icd->dev.parent); | ||
| 1006 | struct pxa_camera_dev *pcdev = ici->priv; | ||
| 1007 | int i = 0, ret = 0; | ||
| 1008 | |||
| 1009 | pcdev->save_cicr[i++] = CICR0; | ||
| 1010 | pcdev->save_cicr[i++] = CICR1; | ||
| 1011 | pcdev->save_cicr[i++] = CICR2; | ||
| 1012 | pcdev->save_cicr[i++] = CICR3; | ||
| 1013 | pcdev->save_cicr[i++] = CICR4; | ||
| 1014 | |||
| 1015 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | ||
| 1016 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | ||
| 1017 | |||
| 1018 | return ret; | ||
| 1019 | } | ||
| 1020 | |||
| 1021 | static int pxa_camera_resume(struct soc_camera_device *icd) | ||
| 1022 | { | ||
| 1023 | struct soc_camera_host *ici = | ||
| 1024 | to_soc_camera_host(icd->dev.parent); | ||
| 1025 | struct pxa_camera_dev *pcdev = ici->priv; | ||
| 1026 | int i = 0, ret = 0; | ||
| 1027 | |||
| 1028 | DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD; | ||
| 1029 | DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD; | ||
| 1030 | DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD; | ||
| 1031 | |||
| 1032 | CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB; | ||
| 1033 | CICR1 = pcdev->save_cicr[i++]; | ||
| 1034 | CICR2 = pcdev->save_cicr[i++]; | ||
| 1035 | CICR3 = pcdev->save_cicr[i++]; | ||
| 1036 | CICR4 = pcdev->save_cicr[i++]; | ||
| 1037 | |||
| 1038 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | ||
| 1039 | ret = pcdev->icd->ops->resume(pcdev->icd); | ||
| 1040 | |||
| 1041 | /* Restart frame capture if active buffer exists */ | ||
| 1042 | if (!ret && pcdev->active) { | ||
| 1043 | /* Reset the FIFOs */ | ||
| 1044 | CIFR |= CIFR_RESET_F; | ||
| 1045 | /* Enable End-Of-Frame Interrupt */ | ||
| 1046 | CICR0 &= ~CICR0_EOFM; | ||
| 1047 | /* Restart the Capture Interface */ | ||
| 1048 | CICR0 |= CICR0_ENB; | ||
| 1049 | } | ||
| 1050 | |||
| 1051 | return ret; | ||
| 1052 | } | ||
| 1053 | |||
| 1000 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { | 1054 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
| 1001 | .owner = THIS_MODULE, | 1055 | .owner = THIS_MODULE, |
| 1002 | .add = pxa_camera_add_device, | 1056 | .add = pxa_camera_add_device, |
| 1003 | .remove = pxa_camera_remove_device, | 1057 | .remove = pxa_camera_remove_device, |
| 1058 | .suspend = pxa_camera_suspend, | ||
| 1059 | .resume = pxa_camera_resume, | ||
| 1004 | .set_fmt_cap = pxa_camera_set_fmt_cap, | 1060 | .set_fmt_cap = pxa_camera_set_fmt_cap, |
| 1005 | .try_fmt_cap = pxa_camera_try_fmt_cap, | 1061 | .try_fmt_cap = pxa_camera_try_fmt_cap, |
| 1006 | .init_videobuf = pxa_camera_init_videobuf, | 1062 | .init_videobuf = pxa_camera_init_videobuf, |
| @@ -1198,7 +1254,7 @@ static int __devinit pxa_camera_init(void) | |||
| 1198 | 1254 | ||
| 1199 | static void __exit pxa_camera_exit(void) | 1255 | static void __exit pxa_camera_exit(void) |
| 1200 | { | 1256 | { |
| 1201 | return platform_driver_unregister(&pxa_camera_driver); | 1257 | platform_driver_unregister(&pxa_camera_driver); |
| 1202 | } | 1258 | } |
| 1203 | 1259 | ||
| 1204 | module_init(pxa_camera_init); | 1260 | module_init(pxa_camera_init); |
diff --git a/drivers/media/video/sh_mobile_ceu_camera.c b/drivers/media/video/sh_mobile_ceu_camera.c index f7ca3cb9340a..318754e73132 100644 --- a/drivers/media/video/sh_mobile_ceu_camera.c +++ b/drivers/media/video/sh_mobile_ceu_camera.c | |||
| @@ -647,7 +647,7 @@ static int __init sh_mobile_ceu_init(void) | |||
| 647 | 647 | ||
| 648 | static void __exit sh_mobile_ceu_exit(void) | 648 | static void __exit sh_mobile_ceu_exit(void) |
| 649 | { | 649 | { |
| 650 | return platform_driver_unregister(&sh_mobile_ceu_driver); | 650 | platform_driver_unregister(&sh_mobile_ceu_driver); |
| 651 | } | 651 | } |
| 652 | 652 | ||
| 653 | module_init(sh_mobile_ceu_init); | 653 | module_init(sh_mobile_ceu_init); |
diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c index b6be5ee678b6..66ebe5956a87 100644 --- a/drivers/media/video/soc_camera.c +++ b/drivers/media/video/soc_camera.c | |||
| @@ -732,10 +732,36 @@ static int soc_camera_remove(struct device *dev) | |||
| 732 | return 0; | 732 | return 0; |
| 733 | } | 733 | } |
| 734 | 734 | ||
| 735 | static int soc_camera_suspend(struct device *dev, pm_message_t state) | ||
| 736 | { | ||
| 737 | struct soc_camera_device *icd = to_soc_camera_dev(dev); | ||
| 738 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | ||
| 739 | int ret = 0; | ||
| 740 | |||
| 741 | if (ici->ops->suspend) | ||
| 742 | ret = ici->ops->suspend(icd, state); | ||
| 743 | |||
| 744 | return ret; | ||
| 745 | } | ||
| 746 | |||
| 747 | static int soc_camera_resume(struct device *dev) | ||
| 748 | { | ||
| 749 | struct soc_camera_device *icd = to_soc_camera_dev(dev); | ||
| 750 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | ||
| 751 | int ret = 0; | ||
| 752 | |||
| 753 | if (ici->ops->resume) | ||
| 754 | ret = ici->ops->resume(icd); | ||
| 755 | |||
| 756 | return ret; | ||
| 757 | } | ||
| 758 | |||
| 735 | static struct bus_type soc_camera_bus_type = { | 759 | static struct bus_type soc_camera_bus_type = { |
| 736 | .name = "soc-camera", | 760 | .name = "soc-camera", |
| 737 | .probe = soc_camera_probe, | 761 | .probe = soc_camera_probe, |
| 738 | .remove = soc_camera_remove, | 762 | .remove = soc_camera_remove, |
| 763 | .suspend = soc_camera_suspend, | ||
| 764 | .resume = soc_camera_resume, | ||
| 739 | }; | 765 | }; |
| 740 | 766 | ||
| 741 | static struct device_driver ic_drv = { | 767 | static struct device_driver ic_drv = { |
diff --git a/drivers/media/video/soc_camera_platform.c b/drivers/media/video/soc_camera_platform.c index eefb0327ebb6..1adc257ebdb9 100644 --- a/drivers/media/video/soc_camera_platform.c +++ b/drivers/media/video/soc_camera_platform.c | |||
| @@ -187,7 +187,7 @@ static int __init soc_camera_platform_module_init(void) | |||
| 187 | 187 | ||
| 188 | static void __exit soc_camera_platform_module_exit(void) | 188 | static void __exit soc_camera_platform_module_exit(void) |
| 189 | { | 189 | { |
| 190 | return platform_driver_unregister(&soc_camera_platform_driver); | 190 | platform_driver_unregister(&soc_camera_platform_driver); |
| 191 | } | 191 | } |
| 192 | 192 | ||
| 193 | module_init(soc_camera_platform_module_init); | 193 | module_init(soc_camera_platform_module_init); |
diff --git a/drivers/media/video/uvc/uvc_ctrl.c b/drivers/media/video/uvc/uvc_ctrl.c index 626f4ad7e876..6ef3e5297de8 100644 --- a/drivers/media/video/uvc/uvc_ctrl.c +++ b/drivers/media/video/uvc/uvc_ctrl.c | |||
| @@ -585,13 +585,17 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, | |||
| 585 | struct uvc_control_mapping *mapping; | 585 | struct uvc_control_mapping *mapping; |
| 586 | struct uvc_menu_info *menu; | 586 | struct uvc_menu_info *menu; |
| 587 | unsigned int i; | 587 | unsigned int i; |
| 588 | __u8 data[8]; | 588 | __u8 *data; |
| 589 | int ret; | 589 | int ret; |
| 590 | 590 | ||
| 591 | ctrl = uvc_find_control(video, v4l2_ctrl->id, &mapping); | 591 | ctrl = uvc_find_control(video, v4l2_ctrl->id, &mapping); |
| 592 | if (ctrl == NULL) | 592 | if (ctrl == NULL) |
| 593 | return -EINVAL; | 593 | return -EINVAL; |
| 594 | 594 | ||
| 595 | data = kmalloc(8, GFP_KERNEL); | ||
| 596 | if (data == NULL) | ||
| 597 | return -ENOMEM; | ||
| 598 | |||
| 595 | memset(v4l2_ctrl, 0, sizeof *v4l2_ctrl); | 599 | memset(v4l2_ctrl, 0, sizeof *v4l2_ctrl); |
| 596 | v4l2_ctrl->id = mapping->id; | 600 | v4l2_ctrl->id = mapping->id; |
| 597 | v4l2_ctrl->type = mapping->v4l2_type; | 601 | v4l2_ctrl->type = mapping->v4l2_type; |
| @@ -604,8 +608,8 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, | |||
| 604 | if (ctrl->info->flags & UVC_CONTROL_GET_DEF) { | 608 | if (ctrl->info->flags & UVC_CONTROL_GET_DEF) { |
| 605 | if ((ret = uvc_query_ctrl(video->dev, GET_DEF, ctrl->entity->id, | 609 | if ((ret = uvc_query_ctrl(video->dev, GET_DEF, ctrl->entity->id, |
| 606 | video->dev->intfnum, ctrl->info->selector, | 610 | video->dev->intfnum, ctrl->info->selector, |
| 607 | &data, ctrl->info->size)) < 0) | 611 | data, ctrl->info->size)) < 0) |
| 608 | return ret; | 612 | goto out; |
| 609 | v4l2_ctrl->default_value = uvc_get_le_value(data, mapping); | 613 | v4l2_ctrl->default_value = uvc_get_le_value(data, mapping); |
| 610 | } | 614 | } |
| 611 | 615 | ||
| @@ -623,13 +627,15 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, | |||
| 623 | } | 627 | } |
| 624 | } | 628 | } |
| 625 | 629 | ||
| 626 | return 0; | 630 | ret = 0; |
| 631 | goto out; | ||
| 627 | 632 | ||
| 628 | case V4L2_CTRL_TYPE_BOOLEAN: | 633 | case V4L2_CTRL_TYPE_BOOLEAN: |
| 629 | v4l2_ctrl->minimum = 0; | 634 | v4l2_ctrl->minimum = 0; |
| 630 | v4l2_ctrl->maximum = 1; | 635 | v4l2_ctrl->maximum = 1; |
| 631 | v4l2_ctrl->step = 1; | 636 | v4l2_ctrl->step = 1; |
| 632 | return 0; | 637 | ret = 0; |
| 638 | goto out; | ||
| 633 | 639 | ||
| 634 | default: | 640 | default: |
| 635 | break; | 641 | break; |
| @@ -638,26 +644,29 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, | |||
| 638 | if (ctrl->info->flags & UVC_CONTROL_GET_MIN) { | 644 | if (ctrl->info->flags & UVC_CONTROL_GET_MIN) { |
| 639 | if ((ret = uvc_query_ctrl(video->dev, GET_MIN, ctrl->entity->id, | 645 | if ((ret = uvc_query_ctrl(video->dev, GET_MIN, ctrl->entity->id, |
| 640 | video->dev->intfnum, ctrl->info->selector, | 646 | video->dev->intfnum, ctrl->info->selector, |
| 641 | &data, ctrl->info->size)) < 0) | 647 | data, ctrl->info->size)) < 0) |
| 642 | return ret; | 648 | goto out; |
| 643 | v4l2_ctrl->minimum = uvc_get_le_value(data, mapping); | 649 | v4l2_ctrl->minimum = uvc_get_le_value(data, mapping); |
| 644 | } | 650 | } |
| 645 | if (ctrl->info->flags & UVC_CONTROL_GET_MAX) { | 651 | if (ctrl->info->flags & UVC_CONTROL_GET_MAX) { |
| 646 | if ((ret = uvc_query_ctrl(video->dev, GET_MAX, ctrl->entity->id, | 652 | if ((ret = uvc_query_ctrl(video->dev, GET_MAX, ctrl->entity->id, |
| 647 | video->dev->intfnum, ctrl->info->selector, | 653 | video->dev->intfnum, ctrl->info->selector, |
| 648 | &data, ctrl->info->size)) < 0) | 654 | data, ctrl->info->size)) < 0) |
| 649 | return ret; | 655 | goto out; |
| 650 | v4l2_ctrl->maximum = uvc_get_le_value(data, mapping); | 656 | v4l2_ctrl->maximum = uvc_get_le_value(data, mapping); |
| 651 | } | 657 | } |
| 652 | if (ctrl->info->flags & UVC_CONTROL_GET_RES) { | 658 | if (ctrl->info->flags & UVC_CONTROL_GET_RES) { |
| 653 | if ((ret = uvc_query_ctrl(video->dev, GET_RES, ctrl->entity->id, | 659 | if ((ret = uvc_query_ctrl(video->dev, GET_RES, ctrl->entity->id, |
| 654 | video->dev->intfnum, ctrl->info->selector, | 660 | video->dev->intfnum, ctrl->info->selector, |
| 655 | &data, ctrl->info->size)) < 0) | 661 | data, ctrl->info->size)) < 0) |
| 656 | return ret; | 662 | goto out; |
| 657 | v4l2_ctrl->step = uvc_get_le_value(data, mapping); | 663 | v4l2_ctrl->step = uvc_get_le_value(data, mapping); |
| 658 | } | 664 | } |
| 659 | 665 | ||
| 660 | return 0; | 666 | ret = 0; |
| 667 | out: | ||
| 668 | kfree(data); | ||
| 669 | return ret; | ||
| 661 | } | 670 | } |
| 662 | 671 | ||
| 663 | 672 | ||
diff --git a/drivers/media/video/uvc/uvc_driver.c b/drivers/media/video/uvc/uvc_driver.c index b3c4d75e8490..7e102034d38d 100644 --- a/drivers/media/video/uvc/uvc_driver.c +++ b/drivers/media/video/uvc/uvc_driver.c | |||
| @@ -1884,7 +1884,7 @@ static struct usb_device_id uvc_ids[] = { | |||
| 1884 | .bInterfaceSubClass = 1, | 1884 | .bInterfaceSubClass = 1, |
| 1885 | .bInterfaceProtocol = 0, | 1885 | .bInterfaceProtocol = 0, |
| 1886 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | 1886 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, |
| 1887 | /* Packard Bell OEM Webcam */ | 1887 | /* Packard Bell OEM Webcam - Bison Electronics */ |
| 1888 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | 1888 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
| 1889 | | USB_DEVICE_ID_MATCH_INT_INFO, | 1889 | | USB_DEVICE_ID_MATCH_INT_INFO, |
| 1890 | .idVendor = 0x5986, | 1890 | .idVendor = 0x5986, |
| @@ -1893,7 +1893,7 @@ static struct usb_device_id uvc_ids[] = { | |||
| 1893 | .bInterfaceSubClass = 1, | 1893 | .bInterfaceSubClass = 1, |
| 1894 | .bInterfaceProtocol = 0, | 1894 | .bInterfaceProtocol = 0, |
| 1895 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | 1895 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, |
| 1896 | /* Acer Crystal Eye webcam */ | 1896 | /* Acer Crystal Eye webcam - Bison Electronics */ |
| 1897 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | 1897 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
| 1898 | | USB_DEVICE_ID_MATCH_INT_INFO, | 1898 | | USB_DEVICE_ID_MATCH_INT_INFO, |
| 1899 | .idVendor = 0x5986, | 1899 | .idVendor = 0x5986, |
| @@ -1902,7 +1902,7 @@ static struct usb_device_id uvc_ids[] = { | |||
| 1902 | .bInterfaceSubClass = 1, | 1902 | .bInterfaceSubClass = 1, |
| 1903 | .bInterfaceProtocol = 0, | 1903 | .bInterfaceProtocol = 0, |
| 1904 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | 1904 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, |
| 1905 | /* Medion Akoya Mini E1210 */ | 1905 | /* Medion Akoya Mini E1210 - Bison Electronics */ |
| 1906 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | 1906 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
| 1907 | | USB_DEVICE_ID_MATCH_INT_INFO, | 1907 | | USB_DEVICE_ID_MATCH_INT_INFO, |
| 1908 | .idVendor = 0x5986, | 1908 | .idVendor = 0x5986, |
| @@ -1911,7 +1911,7 @@ static struct usb_device_id uvc_ids[] = { | |||
| 1911 | .bInterfaceSubClass = 1, | 1911 | .bInterfaceSubClass = 1, |
| 1912 | .bInterfaceProtocol = 0, | 1912 | .bInterfaceProtocol = 0, |
| 1913 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | 1913 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, |
| 1914 | /* Acer OrbiCam - Unknown vendor */ | 1914 | /* Acer OrbiCam - Bison Electronics */ |
| 1915 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | 1915 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
| 1916 | | USB_DEVICE_ID_MATCH_INT_INFO, | 1916 | | USB_DEVICE_ID_MATCH_INT_INFO, |
| 1917 | .idVendor = 0x5986, | 1917 | .idVendor = 0x5986, |
| @@ -1920,6 +1920,24 @@ static struct usb_device_id uvc_ids[] = { | |||
| 1920 | .bInterfaceSubClass = 1, | 1920 | .bInterfaceSubClass = 1, |
| 1921 | .bInterfaceProtocol = 0, | 1921 | .bInterfaceProtocol = 0, |
| 1922 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | 1922 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, |
| 1923 | /* Bison Electronics */ | ||
| 1924 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
| 1925 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
| 1926 | .idVendor = 0x5986, | ||
| 1927 | .idProduct = 0x0300, | ||
| 1928 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
| 1929 | .bInterfaceSubClass = 1, | ||
| 1930 | .bInterfaceProtocol = 0, | ||
| 1931 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
| 1932 | /* Clevo M570TU - Bison Electronics */ | ||
| 1933 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
| 1934 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
| 1935 | .idVendor = 0x5986, | ||
| 1936 | .idProduct = 0x0303, | ||
| 1937 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
| 1938 | .bInterfaceSubClass = 1, | ||
| 1939 | .bInterfaceProtocol = 0, | ||
| 1940 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
| 1923 | /* Generic USB Video Class */ | 1941 | /* Generic USB Video Class */ |
| 1924 | { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) }, | 1942 | { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) }, |
| 1925 | {} | 1943 | {} |
diff --git a/drivers/media/video/uvc/uvc_video.c b/drivers/media/video/uvc/uvc_video.c index ad63794fda77..6854ac78a161 100644 --- a/drivers/media/video/uvc/uvc_video.c +++ b/drivers/media/video/uvc/uvc_video.c | |||
| @@ -90,17 +90,20 @@ static void uvc_fixup_buffer_size(struct uvc_video_device *video, | |||
| 90 | static int uvc_get_video_ctrl(struct uvc_video_device *video, | 90 | static int uvc_get_video_ctrl(struct uvc_video_device *video, |
| 91 | struct uvc_streaming_control *ctrl, int probe, __u8 query) | 91 | struct uvc_streaming_control *ctrl, int probe, __u8 query) |
| 92 | { | 92 | { |
| 93 | __u8 data[34]; | 93 | __u8 *data; |
| 94 | __u8 size; | 94 | __u16 size; |
| 95 | int ret; | 95 | int ret; |
| 96 | 96 | ||
| 97 | size = video->dev->uvc_version >= 0x0110 ? 34 : 26; | 97 | size = video->dev->uvc_version >= 0x0110 ? 34 : 26; |
| 98 | data = kmalloc(size, GFP_KERNEL); | ||
| 99 | if (data == NULL) | ||
| 100 | return -ENOMEM; | ||
| 101 | |||
| 98 | ret = __uvc_query_ctrl(video->dev, query, 0, video->streaming->intfnum, | 102 | ret = __uvc_query_ctrl(video->dev, query, 0, video->streaming->intfnum, |
| 99 | probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, &data, size, | 103 | probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, data, size, |
| 100 | UVC_CTRL_STREAMING_TIMEOUT); | 104 | UVC_CTRL_STREAMING_TIMEOUT); |
| 101 | |||
| 102 | if (ret < 0) | 105 | if (ret < 0) |
| 103 | return ret; | 106 | goto out; |
| 104 | 107 | ||
| 105 | ctrl->bmHint = le16_to_cpup((__le16 *)&data[0]); | 108 | ctrl->bmHint = le16_to_cpup((__le16 *)&data[0]); |
| 106 | ctrl->bFormatIndex = data[2]; | 109 | ctrl->bFormatIndex = data[2]; |
| @@ -136,17 +139,22 @@ static int uvc_get_video_ctrl(struct uvc_video_device *video, | |||
| 136 | */ | 139 | */ |
| 137 | uvc_fixup_buffer_size(video, ctrl); | 140 | uvc_fixup_buffer_size(video, ctrl); |
| 138 | 141 | ||
| 139 | return 0; | 142 | out: |
| 143 | kfree(data); | ||
| 144 | return ret; | ||
| 140 | } | 145 | } |
| 141 | 146 | ||
| 142 | int uvc_set_video_ctrl(struct uvc_video_device *video, | 147 | int uvc_set_video_ctrl(struct uvc_video_device *video, |
| 143 | struct uvc_streaming_control *ctrl, int probe) | 148 | struct uvc_streaming_control *ctrl, int probe) |
| 144 | { | 149 | { |
| 145 | __u8 data[34]; | 150 | __u8 *data; |
| 146 | __u8 size; | 151 | __u16 size; |
| 152 | int ret; | ||
| 147 | 153 | ||
| 148 | size = video->dev->uvc_version >= 0x0110 ? 34 : 26; | 154 | size = video->dev->uvc_version >= 0x0110 ? 34 : 26; |
| 149 | memset(data, 0, sizeof data); | 155 | data = kzalloc(size, GFP_KERNEL); |
| 156 | if (data == NULL) | ||
| 157 | return -ENOMEM; | ||
| 150 | 158 | ||
| 151 | *(__le16 *)&data[0] = cpu_to_le16(ctrl->bmHint); | 159 | *(__le16 *)&data[0] = cpu_to_le16(ctrl->bmHint); |
| 152 | data[2] = ctrl->bFormatIndex; | 160 | data[2] = ctrl->bFormatIndex; |
| @@ -174,10 +182,13 @@ int uvc_set_video_ctrl(struct uvc_video_device *video, | |||
| 174 | data[33] = ctrl->bMaxVersion; | 182 | data[33] = ctrl->bMaxVersion; |
| 175 | } | 183 | } |
| 176 | 184 | ||
| 177 | return __uvc_query_ctrl(video->dev, SET_CUR, 0, | 185 | ret = __uvc_query_ctrl(video->dev, SET_CUR, 0, |
| 178 | video->streaming->intfnum, | 186 | video->streaming->intfnum, |
| 179 | probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, &data, size, | 187 | probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, data, size, |
| 180 | UVC_CTRL_STREAMING_TIMEOUT); | 188 | UVC_CTRL_STREAMING_TIMEOUT); |
| 189 | |||
| 190 | kfree(data); | ||
| 191 | return ret; | ||
| 181 | } | 192 | } |
| 182 | 193 | ||
| 183 | int uvc_probe_video(struct uvc_video_device *video, | 194 | int uvc_probe_video(struct uvc_video_device *video, |
diff --git a/drivers/media/video/v4l2-dev.c b/drivers/media/video/v4l2-dev.c index 556615fe93de..6f36006aecda 100644 --- a/drivers/media/video/v4l2-dev.c +++ b/drivers/media/video/v4l2-dev.c | |||
| @@ -222,11 +222,13 @@ int video_register_device(struct video_device *vfd, int type, int nr) | |||
| 222 | EXPORT_SYMBOL(video_register_device); | 222 | EXPORT_SYMBOL(video_register_device); |
| 223 | 223 | ||
| 224 | /** | 224 | /** |
| 225 | * video_register_device - register video4linux devices | 225 | * video_register_device_index - register video4linux devices |
| 226 | * @vfd: video device structure we want to register | 226 | * @vfd: video device structure we want to register |
| 227 | * @type: type of device to register | 227 | * @type: type of device to register |
| 228 | * @nr: which device number (0 == /dev/video0, 1 == /dev/video1, ... | 228 | * @nr: which device number (0 == /dev/video0, 1 == /dev/video1, ... |
| 229 | * -1 == first free) | 229 | * -1 == first free) |
| 230 | * @index: stream number based on parent device; | ||
| 231 | * -1 if auto assign, requested number otherwise | ||
| 230 | * | 232 | * |
| 231 | * The registration code assigns minor numbers based on the type | 233 | * The registration code assigns minor numbers based on the type |
| 232 | * requested. -ENFILE is returned in all the device slots for this | 234 | * requested. -ENFILE is returned in all the device slots for this |
diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c index ef7572cbc4ab..1edda456fc64 100644 --- a/drivers/media/video/vino.c +++ b/drivers/media/video/vino.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #include <linux/videodev2.h> | 41 | #include <linux/videodev2.h> |
| 42 | #include <media/v4l2-ioctl.h> | 42 | #include <media/v4l2-ioctl.h> |
| 43 | #include <media/v4l2-common.h> | 43 | #include <media/v4l2-common.h> |
| 44 | #include <media/v4l2-ioctl.h> | ||
| 44 | #include <linux/video_decoder.h> | 45 | #include <linux/video_decoder.h> |
| 45 | #include <linux/mutex.h> | 46 | #include <linux/mutex.h> |
| 46 | 47 | ||
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 82af385460e4..a726f3b01a6b 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig | |||
| @@ -427,10 +427,10 @@ config ENCLOSURE_SERVICES | |||
| 427 | config SGI_XP | 427 | config SGI_XP |
| 428 | tristate "Support communication between SGI SSIs" | 428 | tristate "Support communication between SGI SSIs" |
| 429 | depends on NET | 429 | depends on NET |
| 430 | depends on IA64_GENERIC || IA64_SGI_SN2 || IA64_SGI_UV || (X86_64 && SMP) | 430 | depends on (IA64_GENERIC || IA64_SGI_SN2 || IA64_SGI_UV || X86_64) && SMP |
| 431 | select IA64_UNCACHED_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2 | 431 | select IA64_UNCACHED_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2 |
| 432 | select GENERIC_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2 | 432 | select GENERIC_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2 |
| 433 | select SGI_GRU if IA64_GENERIC || IA64_SGI_UV || (X86_64 && SMP) | 433 | select SGI_GRU if (IA64_GENERIC || IA64_SGI_UV || X86_64) && SMP |
| 434 | ---help--- | 434 | ---help--- |
| 435 | An SGI machine can be divided into multiple Single System | 435 | An SGI machine can be divided into multiple Single System |
| 436 | Images which act independently of each other and have | 436 | Images which act independently of each other and have |
diff --git a/drivers/net/3c523.c b/drivers/net/3c523.c index dc6e474229b1..e2ce41d3828e 100644 --- a/drivers/net/3c523.c +++ b/drivers/net/3c523.c | |||
| @@ -640,10 +640,8 @@ static int init586(struct net_device *dev) | |||
| 640 | cfg_cmd->time_low = 0x00; | 640 | cfg_cmd->time_low = 0x00; |
| 641 | cfg_cmd->time_high = 0xf2; | 641 | cfg_cmd->time_high = 0xf2; |
| 642 | cfg_cmd->promisc = 0; | 642 | cfg_cmd->promisc = 0; |
| 643 | if (dev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { | 643 | if (dev->flags & (IFF_ALLMULTI | IFF_PROMISC)) |
| 644 | cfg_cmd->promisc = 1; | 644 | cfg_cmd->promisc = 1; |
| 645 | dev->flags |= IFF_PROMISC; | ||
| 646 | } | ||
| 647 | cfg_cmd->carr_coll = 0x00; | 645 | cfg_cmd->carr_coll = 0x00; |
| 648 | 646 | ||
| 649 | p->scb->cbl_offset = make16(cfg_cmd); | 647 | p->scb->cbl_offset = make16(cfg_cmd); |
diff --git a/drivers/net/3c527.c b/drivers/net/3c527.c index 6aca0c640f13..abc84f765973 100644 --- a/drivers/net/3c527.c +++ b/drivers/net/3c527.c | |||
| @@ -1521,14 +1521,11 @@ static void do_mc32_set_multicast_list(struct net_device *dev, int retry) | |||
| 1521 | struct mc32_local *lp = netdev_priv(dev); | 1521 | struct mc32_local *lp = netdev_priv(dev); |
| 1522 | u16 filt = (1<<2); /* Save Bad Packets, for stats purposes */ | 1522 | u16 filt = (1<<2); /* Save Bad Packets, for stats purposes */ |
| 1523 | 1523 | ||
| 1524 | if (dev->flags&IFF_PROMISC) | 1524 | if ((dev->flags&IFF_PROMISC) || |
| 1525 | (dev->flags&IFF_ALLMULTI) || | ||
| 1526 | dev->mc_count > 10) | ||
| 1525 | /* Enable promiscuous mode */ | 1527 | /* Enable promiscuous mode */ |
| 1526 | filt |= 1; | 1528 | filt |= 1; |
| 1527 | else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > 10) | ||
| 1528 | { | ||
| 1529 | dev->flags|=IFF_PROMISC; | ||
| 1530 | filt |= 1; | ||
| 1531 | } | ||
| 1532 | else if(dev->mc_count) | 1529 | else if(dev->mc_count) |
| 1533 | { | 1530 | { |
| 1534 | unsigned char block[62]; | 1531 | unsigned char block[62]; |
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c index 8db4e6b89482..491ee16da5c1 100644 --- a/drivers/net/3c59x.c +++ b/drivers/net/3c59x.c | |||
| @@ -1692,12 +1692,14 @@ vortex_open(struct net_device *dev) | |||
| 1692 | vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1)); | 1692 | vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1)); |
| 1693 | vp->rx_ring[i].status = 0; /* Clear complete bit. */ | 1693 | vp->rx_ring[i].status = 0; /* Clear complete bit. */ |
| 1694 | vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); | 1694 | vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); |
| 1695 | skb = dev_alloc_skb(PKT_BUF_SZ); | 1695 | |
| 1696 | skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN, | ||
| 1697 | GFP_KERNEL); | ||
| 1696 | vp->rx_skbuff[i] = skb; | 1698 | vp->rx_skbuff[i] = skb; |
| 1697 | if (skb == NULL) | 1699 | if (skb == NULL) |
| 1698 | break; /* Bad news! */ | 1700 | break; /* Bad news! */ |
| 1699 | skb->dev = dev; /* Mark as being used by this device. */ | 1701 | |
| 1700 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ | 1702 | skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */ |
| 1701 | vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); | 1703 | vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); |
| 1702 | } | 1704 | } |
| 1703 | if (i != RX_RING_SIZE) { | 1705 | if (i != RX_RING_SIZE) { |
| @@ -2538,7 +2540,7 @@ boomerang_rx(struct net_device *dev) | |||
| 2538 | struct sk_buff *skb; | 2540 | struct sk_buff *skb; |
| 2539 | entry = vp->dirty_rx % RX_RING_SIZE; | 2541 | entry = vp->dirty_rx % RX_RING_SIZE; |
| 2540 | if (vp->rx_skbuff[entry] == NULL) { | 2542 | if (vp->rx_skbuff[entry] == NULL) { |
| 2541 | skb = dev_alloc_skb(PKT_BUF_SZ); | 2543 | skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
| 2542 | if (skb == NULL) { | 2544 | if (skb == NULL) { |
| 2543 | static unsigned long last_jif; | 2545 | static unsigned long last_jif; |
| 2544 | if (time_after(jiffies, last_jif + 10 * HZ)) { | 2546 | if (time_after(jiffies, last_jif + 10 * HZ)) { |
| @@ -2549,8 +2551,8 @@ boomerang_rx(struct net_device *dev) | |||
| 2549 | mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1)); | 2551 | mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1)); |
| 2550 | break; /* Bad news! */ | 2552 | break; /* Bad news! */ |
| 2551 | } | 2553 | } |
| 2552 | skb->dev = dev; /* Mark as being used by this device. */ | 2554 | |
| 2553 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ | 2555 | skb_reserve(skb, NET_IP_ALIGN); |
| 2554 | vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); | 2556 | vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); |
| 2555 | vp->rx_skbuff[entry] = skb; | 2557 | vp->rx_skbuff[entry] = skb; |
| 2556 | } | 2558 | } |
diff --git a/drivers/net/8390.c b/drivers/net/8390.c index dc5d2584bd0c..f72a2e87d569 100644 --- a/drivers/net/8390.c +++ b/drivers/net/8390.c | |||
| @@ -9,42 +9,39 @@ int ei_open(struct net_device *dev) | |||
| 9 | { | 9 | { |
| 10 | return __ei_open(dev); | 10 | return __ei_open(dev); |
| 11 | } | 11 | } |
| 12 | EXPORT_SYMBOL(ei_open); | ||
| 12 | 13 | ||
| 13 | int ei_close(struct net_device *dev) | 14 | int ei_close(struct net_device *dev) |
| 14 | { | 15 | { |
| 15 | return __ei_close(dev); | 16 | return __ei_close(dev); |
| 16 | } | 17 | } |
| 18 | EXPORT_SYMBOL(ei_close); | ||
| 17 | 19 | ||
| 18 | irqreturn_t ei_interrupt(int irq, void *dev_id) | 20 | irqreturn_t ei_interrupt(int irq, void *dev_id) |
| 19 | { | 21 | { |
| 20 | return __ei_interrupt(irq, dev_id); | 22 | return __ei_interrupt(irq, dev_id); |
| 21 | } | 23 | } |
| 24 | EXPORT_SYMBOL(ei_interrupt); | ||
| 22 | 25 | ||
| 23 | #ifdef CONFIG_NET_POLL_CONTROLLER | 26 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 24 | void ei_poll(struct net_device *dev) | 27 | void ei_poll(struct net_device *dev) |
| 25 | { | 28 | { |
| 26 | __ei_poll(dev); | 29 | __ei_poll(dev); |
| 27 | } | 30 | } |
| 31 | EXPORT_SYMBOL(ei_poll); | ||
| 28 | #endif | 32 | #endif |
| 29 | 33 | ||
| 30 | struct net_device *__alloc_ei_netdev(int size) | 34 | struct net_device *__alloc_ei_netdev(int size) |
| 31 | { | 35 | { |
| 32 | return ____alloc_ei_netdev(size); | 36 | return ____alloc_ei_netdev(size); |
| 33 | } | 37 | } |
| 38 | EXPORT_SYMBOL(__alloc_ei_netdev); | ||
| 34 | 39 | ||
| 35 | void NS8390_init(struct net_device *dev, int startp) | 40 | void NS8390_init(struct net_device *dev, int startp) |
| 36 | { | 41 | { |
| 37 | __NS8390_init(dev, startp); | 42 | __NS8390_init(dev, startp); |
| 38 | } | 43 | } |
| 39 | |||
| 40 | EXPORT_SYMBOL(ei_open); | ||
| 41 | EXPORT_SYMBOL(ei_close); | ||
| 42 | EXPORT_SYMBOL(ei_interrupt); | ||
| 43 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
| 44 | EXPORT_SYMBOL(ei_poll); | ||
| 45 | #endif | ||
| 46 | EXPORT_SYMBOL(NS8390_init); | 44 | EXPORT_SYMBOL(NS8390_init); |
| 47 | EXPORT_SYMBOL(__alloc_ei_netdev); | ||
| 48 | 45 | ||
| 49 | #if defined(MODULE) | 46 | #if defined(MODULE) |
| 50 | 47 | ||
diff --git a/drivers/net/8390p.c b/drivers/net/8390p.c index 71f19884c4b1..4c6eea4611a2 100644 --- a/drivers/net/8390p.c +++ b/drivers/net/8390p.c | |||
| @@ -4,9 +4,9 @@ static const char version[] = | |||
| 4 | "8390p.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n"; | 4 | "8390p.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n"; |
| 5 | 5 | ||
| 6 | #define ei_inb(_p) inb(_p) | 6 | #define ei_inb(_p) inb(_p) |
| 7 | #define ei_outb(_v,_p) outb(_v,_p) | 7 | #define ei_outb(_v, _p) outb(_v, _p) |
| 8 | #define ei_inb_p(_p) inb_p(_p) | 8 | #define ei_inb_p(_p) inb_p(_p) |
| 9 | #define ei_outb_p(_v,_p) outb_p(_v,_p) | 9 | #define ei_outb_p(_v, _p) outb_p(_v, _p) |
| 10 | 10 | ||
| 11 | #include "lib8390.c" | 11 | #include "lib8390.c" |
| 12 | 12 | ||
| @@ -14,42 +14,39 @@ int eip_open(struct net_device *dev) | |||
| 14 | { | 14 | { |
| 15 | return __ei_open(dev); | 15 | return __ei_open(dev); |
| 16 | } | 16 | } |
| 17 | EXPORT_SYMBOL(eip_open); | ||
| 17 | 18 | ||
| 18 | int eip_close(struct net_device *dev) | 19 | int eip_close(struct net_device *dev) |
| 19 | { | 20 | { |
| 20 | return __ei_close(dev); | 21 | return __ei_close(dev); |
| 21 | } | 22 | } |
| 23 | EXPORT_SYMBOL(eip_close); | ||
| 22 | 24 | ||
| 23 | irqreturn_t eip_interrupt(int irq, void *dev_id) | 25 | irqreturn_t eip_interrupt(int irq, void *dev_id) |
| 24 | { | 26 | { |
| 25 | return __ei_interrupt(irq, dev_id); | 27 | return __ei_interrupt(irq, dev_id); |
| 26 | } | 28 | } |
| 29 | EXPORT_SYMBOL(eip_interrupt); | ||
| 27 | 30 | ||
| 28 | #ifdef CONFIG_NET_POLL_CONTROLLER | 31 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 29 | void eip_poll(struct net_device *dev) | 32 | void eip_poll(struct net_device *dev) |
| 30 | { | 33 | { |
| 31 | __ei_poll(dev); | 34 | __ei_poll(dev); |
| 32 | } | 35 | } |
| 36 | EXPORT_SYMBOL(eip_poll); | ||
| 33 | #endif | 37 | #endif |
| 34 | 38 | ||
| 35 | struct net_device *__alloc_eip_netdev(int size) | 39 | struct net_device *__alloc_eip_netdev(int size) |
| 36 | { | 40 | { |
| 37 | return ____alloc_ei_netdev(size); | 41 | return ____alloc_ei_netdev(size); |
| 38 | } | 42 | } |
| 43 | EXPORT_SYMBOL(__alloc_eip_netdev); | ||
| 39 | 44 | ||
| 40 | void NS8390p_init(struct net_device *dev, int startp) | 45 | void NS8390p_init(struct net_device *dev, int startp) |
| 41 | { | 46 | { |
| 42 | return __NS8390_init(dev, startp); | 47 | __NS8390_init(dev, startp); |
| 43 | } | 48 | } |
| 44 | |||
| 45 | EXPORT_SYMBOL(eip_open); | ||
| 46 | EXPORT_SYMBOL(eip_close); | ||
| 47 | EXPORT_SYMBOL(eip_interrupt); | ||
| 48 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
| 49 | EXPORT_SYMBOL(eip_poll); | ||
| 50 | #endif | ||
| 51 | EXPORT_SYMBOL(NS8390p_init); | 49 | EXPORT_SYMBOL(NS8390p_init); |
| 52 | EXPORT_SYMBOL(__alloc_eip_netdev); | ||
| 53 | 50 | ||
| 54 | #if defined(MODULE) | 51 | #if defined(MODULE) |
| 55 | 52 | ||
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8a03875ec877..4b4cb2bf4f11 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
| @@ -510,14 +510,15 @@ config STNIC | |||
| 510 | config SH_ETH | 510 | config SH_ETH |
| 511 | tristate "Renesas SuperH Ethernet support" | 511 | tristate "Renesas SuperH Ethernet support" |
| 512 | depends on SUPERH && \ | 512 | depends on SUPERH && \ |
| 513 | (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763) | 513 | (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763 || \ |
| 514 | CPU_SUBTYPE_SH7619) | ||
| 514 | select CRC32 | 515 | select CRC32 |
| 515 | select MII | 516 | select MII |
| 516 | select MDIO_BITBANG | 517 | select MDIO_BITBANG |
| 517 | select PHYLIB | 518 | select PHYLIB |
| 518 | help | 519 | help |
| 519 | Renesas SuperH Ethernet device driver. | 520 | Renesas SuperH Ethernet device driver. |
| 520 | This driver support SH7710, SH7712 and SH7763. | 521 | This driver support SH7710, SH7712, SH7763 and SH7619. |
| 521 | 522 | ||
| 522 | config SUNLANCE | 523 | config SUNLANCE |
| 523 | tristate "Sun LANCE support" | 524 | tristate "Sun LANCE support" |
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c index f12e3d12474b..e6a7bb79d4df 100644 --- a/drivers/net/atlx/atl1.c +++ b/drivers/net/atlx/atl1.c | |||
| @@ -1790,6 +1790,17 @@ static void atl1_rx_checksum(struct atl1_adapter *adapter, | |||
| 1790 | { | 1790 | { |
| 1791 | struct pci_dev *pdev = adapter->pdev; | 1791 | struct pci_dev *pdev = adapter->pdev; |
| 1792 | 1792 | ||
| 1793 | /* | ||
| 1794 | * The L1 hardware contains a bug that erroneously sets the | ||
| 1795 | * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a | ||
| 1796 | * fragmented IP packet is received, even though the packet | ||
| 1797 | * is perfectly valid and its checksum is correct. There's | ||
| 1798 | * no way to distinguish between one of these good packets | ||
| 1799 | * and a packet that actually contains a TCP/UDP checksum | ||
| 1800 | * error, so all we can do is allow it to be handed up to | ||
| 1801 | * the higher layers and let it be sorted out there. | ||
| 1802 | */ | ||
| 1803 | |||
| 1793 | skb->ip_summed = CHECKSUM_NONE; | 1804 | skb->ip_summed = CHECKSUM_NONE; |
| 1794 | 1805 | ||
| 1795 | if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { | 1806 | if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { |
| @@ -1816,14 +1827,6 @@ static void atl1_rx_checksum(struct atl1_adapter *adapter, | |||
| 1816 | return; | 1827 | return; |
| 1817 | } | 1828 | } |
| 1818 | 1829 | ||
| 1819 | /* IPv4, but hardware thinks its checksum is wrong */ | ||
| 1820 | if (netif_msg_rx_err(adapter)) | ||
| 1821 | dev_printk(KERN_DEBUG, &pdev->dev, | ||
| 1822 | "hw csum wrong, pkt_flag:%x, err_flag:%x\n", | ||
| 1823 | rrd->pkt_flg, rrd->err_flg); | ||
| 1824 | skb->ip_summed = CHECKSUM_COMPLETE; | ||
| 1825 | skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum); | ||
| 1826 | adapter->hw_csum_err++; | ||
| 1827 | return; | 1830 | return; |
| 1828 | } | 1831 | } |
| 1829 | 1832 | ||
diff --git a/drivers/net/atp.c b/drivers/net/atp.c index 3d4433358a36..c10cd8058e23 100644 --- a/drivers/net/atp.c +++ b/drivers/net/atp.c | |||
| @@ -854,14 +854,9 @@ static void set_rx_mode_8002(struct net_device *dev) | |||
| 854 | struct net_local *lp = netdev_priv(dev); | 854 | struct net_local *lp = netdev_priv(dev); |
| 855 | long ioaddr = dev->base_addr; | 855 | long ioaddr = dev->base_addr; |
| 856 | 856 | ||
| 857 | if ( dev->mc_count > 0 || (dev->flags & (IFF_ALLMULTI|IFF_PROMISC))) { | 857 | if (dev->mc_count > 0 || (dev->flags & (IFF_ALLMULTI|IFF_PROMISC))) |
| 858 | /* We must make the kernel realise we had to move | ||
| 859 | * into promisc mode or we start all out war on | ||
| 860 | * the cable. - AC | ||
| 861 | */ | ||
| 862 | dev->flags|=IFF_PROMISC; | ||
| 863 | lp->addr_mode = CMR2h_PROMISC; | 858 | lp->addr_mode = CMR2h_PROMISC; |
| 864 | } else | 859 | else |
| 865 | lp->addr_mode = CMR2h_Normal; | 860 | lp->addr_mode = CMR2h_Normal; |
| 866 | write_reg_high(ioaddr, CMR2, lp->addr_mode); | 861 | write_reg_high(ioaddr, CMR2, lp->addr_mode); |
| 867 | } | 862 | } |
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index af251a5df844..272a4bd25953 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
| @@ -7202,7 +7202,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) | |||
| 7202 | bp->link_params.req_flow_ctrl = (bp->port.link_config & | 7202 | bp->link_params.req_flow_ctrl = (bp->port.link_config & |
| 7203 | PORT_FEATURE_FLOW_CONTROL_MASK); | 7203 | PORT_FEATURE_FLOW_CONTROL_MASK); |
| 7204 | if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) && | 7204 | if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) && |
| 7205 | (!bp->port.supported & SUPPORTED_Autoneg)) | 7205 | !(bp->port.supported & SUPPORTED_Autoneg)) |
| 7206 | bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE; | 7206 | bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE; |
| 7207 | 7207 | ||
| 7208 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x" | 7208 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x" |
diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c index ebb539e090c3..6106660a4a44 100644 --- a/drivers/net/bonding/bond_3ad.c +++ b/drivers/net/bonding/bond_3ad.c | |||
| @@ -2107,6 +2107,7 @@ void bond_3ad_state_machine_handler(struct work_struct *work) | |||
| 2107 | aggregator = __get_first_agg(port); | 2107 | aggregator = __get_first_agg(port); |
| 2108 | ad_agg_selection_logic(aggregator); | 2108 | ad_agg_selection_logic(aggregator); |
| 2109 | } | 2109 | } |
| 2110 | bond_3ad_set_carrier(bond); | ||
| 2110 | } | 2111 | } |
| 2111 | 2112 | ||
| 2112 | // for each port run the state machines | 2113 | // for each port run the state machines |
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index a641eeaa2a2f..c792138511e6 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c | |||
| @@ -2223,272 +2223,217 @@ static int bond_slave_info_query(struct net_device *bond_dev, struct ifslave *in | |||
| 2223 | 2223 | ||
| 2224 | /*-------------------------------- Monitoring -------------------------------*/ | 2224 | /*-------------------------------- Monitoring -------------------------------*/ |
| 2225 | 2225 | ||
| 2226 | /* | ||
| 2227 | * if !have_locks, return nonzero if a failover is necessary. if | ||
| 2228 | * have_locks, do whatever failover activities are needed. | ||
| 2229 | * | ||
| 2230 | * This is to separate the inspection and failover steps for locking | ||
| 2231 | * purposes; failover requires rtnl, but acquiring it for every | ||
| 2232 | * inspection is undesirable, so a wrapper first does inspection, and | ||
| 2233 | * the acquires the necessary locks and calls again to perform | ||
| 2234 | * failover if needed. Since all locks are dropped, a complete | ||
| 2235 | * restart is needed between calls. | ||
| 2236 | */ | ||
| 2237 | static int __bond_mii_monitor(struct bonding *bond, int have_locks) | ||
| 2238 | { | ||
| 2239 | struct slave *slave, *oldcurrent; | ||
| 2240 | int do_failover = 0; | ||
| 2241 | int i; | ||
| 2242 | |||
| 2243 | if (bond->slave_cnt == 0) | ||
| 2244 | goto out; | ||
| 2245 | 2226 | ||
| 2246 | /* we will try to read the link status of each of our slaves, and | 2227 | static int bond_miimon_inspect(struct bonding *bond) |
| 2247 | * set their IFF_RUNNING flag appropriately. For each slave not | 2228 | { |
| 2248 | * supporting MII status, we won't do anything so that a user-space | 2229 | struct slave *slave; |
| 2249 | * program could monitor the link itself if needed. | 2230 | int i, link_state, commit = 0; |
| 2250 | */ | ||
| 2251 | |||
| 2252 | read_lock(&bond->curr_slave_lock); | ||
| 2253 | oldcurrent = bond->curr_active_slave; | ||
| 2254 | read_unlock(&bond->curr_slave_lock); | ||
| 2255 | 2231 | ||
| 2256 | bond_for_each_slave(bond, slave, i) { | 2232 | bond_for_each_slave(bond, slave, i) { |
| 2257 | struct net_device *slave_dev = slave->dev; | 2233 | slave->new_link = BOND_LINK_NOCHANGE; |
| 2258 | int link_state; | ||
| 2259 | u16 old_speed = slave->speed; | ||
| 2260 | u8 old_duplex = slave->duplex; | ||
| 2261 | 2234 | ||
| 2262 | link_state = bond_check_dev_link(bond, slave_dev, 0); | 2235 | link_state = bond_check_dev_link(bond, slave->dev, 0); |
| 2263 | 2236 | ||
| 2264 | switch (slave->link) { | 2237 | switch (slave->link) { |
| 2265 | case BOND_LINK_UP: /* the link was up */ | 2238 | case BOND_LINK_UP: |
| 2266 | if (link_state == BMSR_LSTATUS) { | 2239 | if (link_state) |
| 2267 | if (!oldcurrent) { | 2240 | continue; |
| 2268 | if (!have_locks) | ||
| 2269 | return 1; | ||
| 2270 | do_failover = 1; | ||
| 2271 | } | ||
| 2272 | break; | ||
| 2273 | } else { /* link going down */ | ||
| 2274 | slave->link = BOND_LINK_FAIL; | ||
| 2275 | slave->delay = bond->params.downdelay; | ||
| 2276 | |||
| 2277 | if (slave->link_failure_count < UINT_MAX) { | ||
| 2278 | slave->link_failure_count++; | ||
| 2279 | } | ||
| 2280 | 2241 | ||
| 2281 | if (bond->params.downdelay) { | 2242 | slave->link = BOND_LINK_FAIL; |
| 2282 | printk(KERN_INFO DRV_NAME | 2243 | slave->delay = bond->params.downdelay; |
| 2283 | ": %s: link status down for %s " | 2244 | if (slave->delay) { |
| 2284 | "interface %s, disabling it in " | 2245 | printk(KERN_INFO DRV_NAME |
| 2285 | "%d ms.\n", | 2246 | ": %s: link status down for %s" |
| 2286 | bond->dev->name, | 2247 | "interface %s, disabling it in %d ms.\n", |
| 2287 | IS_UP(slave_dev) | 2248 | bond->dev->name, |
| 2288 | ? ((bond->params.mode == BOND_MODE_ACTIVEBACKUP) | 2249 | (bond->params.mode == |
| 2289 | ? ((slave == oldcurrent) | 2250 | BOND_MODE_ACTIVEBACKUP) ? |
| 2290 | ? "active " : "backup ") | 2251 | ((slave->state == BOND_STATE_ACTIVE) ? |
| 2291 | : "") | 2252 | "active " : "backup ") : "", |
| 2292 | : "idle ", | 2253 | slave->dev->name, |
| 2293 | slave_dev->name, | 2254 | bond->params.downdelay * bond->params.miimon); |
| 2294 | bond->params.downdelay * bond->params.miimon); | ||
| 2295 | } | ||
| 2296 | } | 2255 | } |
| 2297 | /* no break ! fall through the BOND_LINK_FAIL test to | 2256 | /*FALLTHRU*/ |
| 2298 | ensure proper action to be taken | 2257 | case BOND_LINK_FAIL: |
| 2299 | */ | 2258 | if (link_state) { |
| 2300 | case BOND_LINK_FAIL: /* the link has just gone down */ | 2259 | /* |
| 2301 | if (link_state != BMSR_LSTATUS) { | 2260 | * recovered before downdelay expired |
| 2302 | /* link stays down */ | 2261 | */ |
| 2303 | if (slave->delay <= 0) { | 2262 | slave->link = BOND_LINK_UP; |
| 2304 | if (!have_locks) | ||
| 2305 | return 1; | ||
| 2306 | |||
| 2307 | /* link down for too long time */ | ||
| 2308 | slave->link = BOND_LINK_DOWN; | ||
| 2309 | |||
| 2310 | /* in active/backup mode, we must | ||
| 2311 | * completely disable this interface | ||
| 2312 | */ | ||
| 2313 | if ((bond->params.mode == BOND_MODE_ACTIVEBACKUP) || | ||
| 2314 | (bond->params.mode == BOND_MODE_8023AD)) { | ||
| 2315 | bond_set_slave_inactive_flags(slave); | ||
| 2316 | } | ||
| 2317 | |||
| 2318 | printk(KERN_INFO DRV_NAME | ||
| 2319 | ": %s: link status definitely " | ||
| 2320 | "down for interface %s, " | ||
| 2321 | "disabling it\n", | ||
| 2322 | bond->dev->name, | ||
| 2323 | slave_dev->name); | ||
| 2324 | |||
| 2325 | /* notify ad that the link status has changed */ | ||
| 2326 | if (bond->params.mode == BOND_MODE_8023AD) { | ||
| 2327 | bond_3ad_handle_link_change(slave, BOND_LINK_DOWN); | ||
| 2328 | } | ||
| 2329 | |||
| 2330 | if ((bond->params.mode == BOND_MODE_TLB) || | ||
| 2331 | (bond->params.mode == BOND_MODE_ALB)) { | ||
| 2332 | bond_alb_handle_link_change(bond, slave, BOND_LINK_DOWN); | ||
| 2333 | } | ||
| 2334 | |||
| 2335 | if (slave == oldcurrent) { | ||
| 2336 | do_failover = 1; | ||
| 2337 | } | ||
| 2338 | } else { | ||
| 2339 | slave->delay--; | ||
| 2340 | } | ||
| 2341 | } else { | ||
| 2342 | /* link up again */ | ||
| 2343 | slave->link = BOND_LINK_UP; | ||
| 2344 | slave->jiffies = jiffies; | 2263 | slave->jiffies = jiffies; |
| 2345 | printk(KERN_INFO DRV_NAME | 2264 | printk(KERN_INFO DRV_NAME |
| 2346 | ": %s: link status up again after %d " | 2265 | ": %s: link status up again after %d " |
| 2347 | "ms for interface %s.\n", | 2266 | "ms for interface %s.\n", |
| 2348 | bond->dev->name, | 2267 | bond->dev->name, |
| 2349 | (bond->params.downdelay - slave->delay) * bond->params.miimon, | 2268 | (bond->params.downdelay - slave->delay) * |
| 2350 | slave_dev->name); | 2269 | bond->params.miimon, |
| 2270 | slave->dev->name); | ||
| 2271 | continue; | ||
| 2351 | } | 2272 | } |
| 2352 | break; | ||
| 2353 | case BOND_LINK_DOWN: /* the link was down */ | ||
| 2354 | if (link_state != BMSR_LSTATUS) { | ||
| 2355 | /* the link stays down, nothing more to do */ | ||
| 2356 | break; | ||
| 2357 | } else { /* link going up */ | ||
| 2358 | slave->link = BOND_LINK_BACK; | ||
| 2359 | slave->delay = bond->params.updelay; | ||
| 2360 | 2273 | ||
| 2361 | if (bond->params.updelay) { | 2274 | if (slave->delay <= 0) { |
| 2362 | /* if updelay == 0, no need to | 2275 | slave->new_link = BOND_LINK_DOWN; |
| 2363 | advertise about a 0 ms delay */ | 2276 | commit++; |
| 2364 | printk(KERN_INFO DRV_NAME | 2277 | continue; |
| 2365 | ": %s: link status up for " | ||
| 2366 | "interface %s, enabling it " | ||
| 2367 | "in %d ms.\n", | ||
| 2368 | bond->dev->name, | ||
| 2369 | slave_dev->name, | ||
| 2370 | bond->params.updelay * bond->params.miimon); | ||
| 2371 | } | ||
| 2372 | } | 2278 | } |
| 2373 | /* no break ! fall through the BOND_LINK_BACK state in | ||
| 2374 | case there's something to do. | ||
| 2375 | */ | ||
| 2376 | case BOND_LINK_BACK: /* the link has just come back */ | ||
| 2377 | if (link_state != BMSR_LSTATUS) { | ||
| 2378 | /* link down again */ | ||
| 2379 | slave->link = BOND_LINK_DOWN; | ||
| 2380 | 2279 | ||
| 2280 | slave->delay--; | ||
| 2281 | break; | ||
| 2282 | |||
| 2283 | case BOND_LINK_DOWN: | ||
| 2284 | if (!link_state) | ||
| 2285 | continue; | ||
| 2286 | |||
| 2287 | slave->link = BOND_LINK_BACK; | ||
| 2288 | slave->delay = bond->params.updelay; | ||
| 2289 | |||
| 2290 | if (slave->delay) { | ||
| 2291 | printk(KERN_INFO DRV_NAME | ||
| 2292 | ": %s: link status up for " | ||
| 2293 | "interface %s, enabling it in %d ms.\n", | ||
| 2294 | bond->dev->name, slave->dev->name, | ||
| 2295 | bond->params.updelay * | ||
| 2296 | bond->params.miimon); | ||
| 2297 | } | ||
| 2298 | /*FALLTHRU*/ | ||
| 2299 | case BOND_LINK_BACK: | ||
| 2300 | if (!link_state) { | ||
| 2301 | slave->link = BOND_LINK_DOWN; | ||
| 2381 | printk(KERN_INFO DRV_NAME | 2302 | printk(KERN_INFO DRV_NAME |
| 2382 | ": %s: link status down again after %d " | 2303 | ": %s: link status down again after %d " |
| 2383 | "ms for interface %s.\n", | 2304 | "ms for interface %s.\n", |
| 2384 | bond->dev->name, | 2305 | bond->dev->name, |
| 2385 | (bond->params.updelay - slave->delay) * bond->params.miimon, | 2306 | (bond->params.updelay - slave->delay) * |
| 2386 | slave_dev->name); | 2307 | bond->params.miimon, |
| 2387 | } else { | 2308 | slave->dev->name); |
| 2388 | /* link stays up */ | ||
| 2389 | if (slave->delay == 0) { | ||
| 2390 | if (!have_locks) | ||
| 2391 | return 1; | ||
| 2392 | |||
| 2393 | /* now the link has been up for long time enough */ | ||
| 2394 | slave->link = BOND_LINK_UP; | ||
| 2395 | slave->jiffies = jiffies; | ||
| 2396 | |||
| 2397 | if (bond->params.mode == BOND_MODE_8023AD) { | ||
| 2398 | /* prevent it from being the active one */ | ||
| 2399 | slave->state = BOND_STATE_BACKUP; | ||
| 2400 | } else if (bond->params.mode != BOND_MODE_ACTIVEBACKUP) { | ||
| 2401 | /* make it immediately active */ | ||
| 2402 | slave->state = BOND_STATE_ACTIVE; | ||
| 2403 | } else if (slave != bond->primary_slave) { | ||
| 2404 | /* prevent it from being the active one */ | ||
| 2405 | slave->state = BOND_STATE_BACKUP; | ||
| 2406 | } | ||
| 2407 | 2309 | ||
| 2408 | printk(KERN_INFO DRV_NAME | 2310 | continue; |
| 2409 | ": %s: link status definitely " | ||
| 2410 | "up for interface %s.\n", | ||
| 2411 | bond->dev->name, | ||
| 2412 | slave_dev->name); | ||
| 2413 | |||
| 2414 | /* notify ad that the link status has changed */ | ||
| 2415 | if (bond->params.mode == BOND_MODE_8023AD) { | ||
| 2416 | bond_3ad_handle_link_change(slave, BOND_LINK_UP); | ||
| 2417 | } | ||
| 2418 | |||
| 2419 | if ((bond->params.mode == BOND_MODE_TLB) || | ||
| 2420 | (bond->params.mode == BOND_MODE_ALB)) { | ||
| 2421 | bond_alb_handle_link_change(bond, slave, BOND_LINK_UP); | ||
| 2422 | } | ||
| 2423 | |||
| 2424 | if ((!oldcurrent) || | ||
| 2425 | (slave == bond->primary_slave)) { | ||
| 2426 | do_failover = 1; | ||
| 2427 | } | ||
| 2428 | } else { | ||
| 2429 | slave->delay--; | ||
| 2430 | } | ||
| 2431 | } | 2311 | } |
| 2312 | |||
| 2313 | if (slave->delay <= 0) { | ||
| 2314 | slave->new_link = BOND_LINK_UP; | ||
| 2315 | commit++; | ||
| 2316 | continue; | ||
| 2317 | } | ||
| 2318 | |||
| 2319 | slave->delay--; | ||
| 2432 | break; | 2320 | break; |
| 2433 | default: | 2321 | } |
| 2434 | /* Should not happen */ | 2322 | } |
| 2435 | printk(KERN_ERR DRV_NAME | ||
| 2436 | ": %s: Error: %s Illegal value (link=%d)\n", | ||
| 2437 | bond->dev->name, | ||
| 2438 | slave->dev->name, | ||
| 2439 | slave->link); | ||
| 2440 | goto out; | ||
| 2441 | } /* end of switch (slave->link) */ | ||
| 2442 | 2323 | ||
| 2443 | bond_update_speed_duplex(slave); | 2324 | return commit; |
| 2325 | } | ||
| 2444 | 2326 | ||
| 2445 | if (bond->params.mode == BOND_MODE_8023AD) { | 2327 | static void bond_miimon_commit(struct bonding *bond) |
| 2446 | if (old_speed != slave->speed) { | 2328 | { |
| 2447 | bond_3ad_adapter_speed_changed(slave); | 2329 | struct slave *slave; |
| 2448 | } | 2330 | int i; |
| 2331 | |||
| 2332 | bond_for_each_slave(bond, slave, i) { | ||
| 2333 | switch (slave->new_link) { | ||
| 2334 | case BOND_LINK_NOCHANGE: | ||
| 2335 | continue; | ||
| 2336 | |||
| 2337 | case BOND_LINK_UP: | ||
| 2338 | slave->link = BOND_LINK_UP; | ||
| 2339 | slave->jiffies = jiffies; | ||
| 2449 | 2340 | ||
| 2450 | if (old_duplex != slave->duplex) { | 2341 | if (bond->params.mode == BOND_MODE_8023AD) { |
| 2451 | bond_3ad_adapter_duplex_changed(slave); | 2342 | /* prevent it from being the active one */ |
| 2343 | slave->state = BOND_STATE_BACKUP; | ||
| 2344 | } else if (bond->params.mode != BOND_MODE_ACTIVEBACKUP) { | ||
| 2345 | /* make it immediately active */ | ||
| 2346 | slave->state = BOND_STATE_ACTIVE; | ||
| 2347 | } else if (slave != bond->primary_slave) { | ||
| 2348 | /* prevent it from being the active one */ | ||
| 2349 | slave->state = BOND_STATE_BACKUP; | ||
| 2452 | } | 2350 | } |
| 2453 | } | ||
| 2454 | 2351 | ||
| 2455 | } /* end of for */ | 2352 | printk(KERN_INFO DRV_NAME |
| 2353 | ": %s: link status definitely " | ||
| 2354 | "up for interface %s.\n", | ||
| 2355 | bond->dev->name, slave->dev->name); | ||
| 2456 | 2356 | ||
| 2457 | if (do_failover) { | 2357 | /* notify ad that the link status has changed */ |
| 2458 | ASSERT_RTNL(); | 2358 | if (bond->params.mode == BOND_MODE_8023AD) |
| 2359 | bond_3ad_handle_link_change(slave, BOND_LINK_UP); | ||
| 2459 | 2360 | ||
| 2460 | write_lock_bh(&bond->curr_slave_lock); | 2361 | if ((bond->params.mode == BOND_MODE_TLB) || |
| 2362 | (bond->params.mode == BOND_MODE_ALB)) | ||
| 2363 | bond_alb_handle_link_change(bond, slave, | ||
| 2364 | BOND_LINK_UP); | ||
| 2461 | 2365 | ||
| 2462 | bond_select_active_slave(bond); | 2366 | if (!bond->curr_active_slave || |
| 2367 | (slave == bond->primary_slave)) | ||
| 2368 | goto do_failover; | ||
| 2463 | 2369 | ||
| 2464 | write_unlock_bh(&bond->curr_slave_lock); | 2370 | continue; |
| 2465 | 2371 | ||
| 2466 | } else | 2372 | case BOND_LINK_DOWN: |
| 2467 | bond_set_carrier(bond); | 2373 | slave->link = BOND_LINK_DOWN; |
| 2468 | 2374 | ||
| 2469 | out: | 2375 | if (bond->params.mode == BOND_MODE_ACTIVEBACKUP || |
| 2470 | return 0; | 2376 | bond->params.mode == BOND_MODE_8023AD) |
| 2377 | bond_set_slave_inactive_flags(slave); | ||
| 2378 | |||
| 2379 | printk(KERN_INFO DRV_NAME | ||
| 2380 | ": %s: link status definitely down for " | ||
| 2381 | "interface %s, disabling it\n", | ||
| 2382 | bond->dev->name, slave->dev->name); | ||
| 2383 | |||
| 2384 | if (bond->params.mode == BOND_MODE_8023AD) | ||
| 2385 | bond_3ad_handle_link_change(slave, | ||
| 2386 | BOND_LINK_DOWN); | ||
| 2387 | |||
| 2388 | if (bond->params.mode == BOND_MODE_TLB || | ||
| 2389 | bond->params.mode == BOND_MODE_ALB) | ||
| 2390 | bond_alb_handle_link_change(bond, slave, | ||
| 2391 | BOND_LINK_DOWN); | ||
| 2392 | |||
| 2393 | if (slave == bond->curr_active_slave) | ||
| 2394 | goto do_failover; | ||
| 2395 | |||
| 2396 | continue; | ||
| 2397 | |||
| 2398 | default: | ||
| 2399 | printk(KERN_ERR DRV_NAME | ||
| 2400 | ": %s: invalid new link %d on slave %s\n", | ||
| 2401 | bond->dev->name, slave->new_link, | ||
| 2402 | slave->dev->name); | ||
| 2403 | slave->new_link = BOND_LINK_NOCHANGE; | ||
| 2404 | |||
| 2405 | continue; | ||
| 2406 | } | ||
| 2407 | |||
| 2408 | do_failover: | ||
| 2409 | ASSERT_RTNL(); | ||
| 2410 | write_lock_bh(&bond->curr_slave_lock); | ||
| 2411 | bond_select_active_slave(bond); | ||
| 2412 | write_unlock_bh(&bond->curr_slave_lock); | ||
| 2413 | } | ||
| 2414 | |||
| 2415 | bond_set_carrier(bond); | ||
| 2471 | } | 2416 | } |
| 2472 | 2417 | ||
| 2473 | /* | 2418 | /* |
| 2474 | * bond_mii_monitor | 2419 | * bond_mii_monitor |
| 2475 | * | 2420 | * |
| 2476 | * Really a wrapper that splits the mii monitor into two phases: an | 2421 | * Really a wrapper that splits the mii monitor into two phases: an |
| 2477 | * inspection, then (if inspection indicates something needs to be | 2422 | * inspection, then (if inspection indicates something needs to be done) |
| 2478 | * done) an acquisition of appropriate locks followed by another pass | 2423 | * an acquisition of appropriate locks followed by a commit phase to |
| 2479 | * to implement whatever link state changes are indicated. | 2424 | * implement whatever link state changes are indicated. |
| 2480 | */ | 2425 | */ |
| 2481 | void bond_mii_monitor(struct work_struct *work) | 2426 | void bond_mii_monitor(struct work_struct *work) |
| 2482 | { | 2427 | { |
| 2483 | struct bonding *bond = container_of(work, struct bonding, | 2428 | struct bonding *bond = container_of(work, struct bonding, |
| 2484 | mii_work.work); | 2429 | mii_work.work); |
| 2485 | unsigned long delay; | ||
| 2486 | 2430 | ||
| 2487 | read_lock(&bond->lock); | 2431 | read_lock(&bond->lock); |
| 2488 | if (bond->kill_timers) { | 2432 | if (bond->kill_timers) |
| 2489 | read_unlock(&bond->lock); | 2433 | goto out; |
| 2490 | return; | 2434 | |
| 2491 | } | 2435 | if (bond->slave_cnt == 0) |
| 2436 | goto re_arm; | ||
| 2492 | 2437 | ||
| 2493 | if (bond->send_grat_arp) { | 2438 | if (bond->send_grat_arp) { |
| 2494 | read_lock(&bond->curr_slave_lock); | 2439 | read_lock(&bond->curr_slave_lock); |
| @@ -2496,19 +2441,24 @@ void bond_mii_monitor(struct work_struct *work) | |||
| 2496 | read_unlock(&bond->curr_slave_lock); | 2441 | read_unlock(&bond->curr_slave_lock); |
| 2497 | } | 2442 | } |
| 2498 | 2443 | ||
| 2499 | if (__bond_mii_monitor(bond, 0)) { | 2444 | if (bond_miimon_inspect(bond)) { |
| 2500 | read_unlock(&bond->lock); | 2445 | read_unlock(&bond->lock); |
| 2501 | rtnl_lock(); | 2446 | rtnl_lock(); |
| 2502 | read_lock(&bond->lock); | 2447 | read_lock(&bond->lock); |
| 2503 | __bond_mii_monitor(bond, 1); | 2448 | |
| 2449 | bond_miimon_commit(bond); | ||
| 2450 | |||
| 2504 | read_unlock(&bond->lock); | 2451 | read_unlock(&bond->lock); |
| 2505 | rtnl_unlock(); /* might sleep, hold no other locks */ | 2452 | rtnl_unlock(); /* might sleep, hold no other locks */ |
| 2506 | read_lock(&bond->lock); | 2453 | read_lock(&bond->lock); |
| 2507 | } | 2454 | } |
| 2508 | 2455 | ||
| 2509 | delay = msecs_to_jiffies(bond->params.miimon); | 2456 | re_arm: |
| 2457 | if (bond->params.miimon) | ||
| 2458 | queue_delayed_work(bond->wq, &bond->mii_work, | ||
| 2459 | msecs_to_jiffies(bond->params.miimon)); | ||
| 2460 | out: | ||
| 2510 | read_unlock(&bond->lock); | 2461 | read_unlock(&bond->lock); |
| 2511 | queue_delayed_work(bond->wq, &bond->mii_work, delay); | ||
| 2512 | } | 2462 | } |
| 2513 | 2463 | ||
| 2514 | static __be32 bond_glean_dev_ip(struct net_device *dev) | 2464 | static __be32 bond_glean_dev_ip(struct net_device *dev) |
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index 6caac0ffb2f2..3bdb47382521 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c | |||
| @@ -350,9 +350,6 @@ static ssize_t bonding_store_slaves(struct device *d, | |||
| 350 | if (dev) { | 350 | if (dev) { |
| 351 | printk(KERN_INFO DRV_NAME ": %s: Removing slave %s\n", | 351 | printk(KERN_INFO DRV_NAME ": %s: Removing slave %s\n", |
| 352 | bond->dev->name, dev->name); | 352 | bond->dev->name, dev->name); |
| 353 | if (bond->setup_by_slave) | ||
| 354 | res = bond_release_and_destroy(bond->dev, dev); | ||
| 355 | else | ||
| 356 | res = bond_release(bond->dev, dev); | 353 | res = bond_release(bond->dev, dev); |
| 357 | if (res) { | 354 | if (res) { |
| 358 | ret = res; | 355 | ret = res; |
diff --git a/drivers/net/de620.c b/drivers/net/de620.c index 3f5190c654cf..d454e143483e 100644 --- a/drivers/net/de620.c +++ b/drivers/net/de620.c | |||
| @@ -488,13 +488,6 @@ static void de620_set_multicast_list(struct net_device *dev) | |||
| 488 | { | 488 | { |
| 489 | if (dev->mc_count || dev->flags&(IFF_ALLMULTI|IFF_PROMISC)) | 489 | if (dev->mc_count || dev->flags&(IFF_ALLMULTI|IFF_PROMISC)) |
| 490 | { /* Enable promiscuous mode */ | 490 | { /* Enable promiscuous mode */ |
| 491 | /* | ||
| 492 | * We must make the kernel realise we had to move | ||
| 493 | * into promisc mode or we start all out war on | ||
| 494 | * the cable. - AC | ||
| 495 | */ | ||
| 496 | dev->flags|=IFF_PROMISC; | ||
| 497 | |||
| 498 | de620_set_register(dev, W_TCR, (TCR_DEF & ~RXPBM) | RXALL); | 491 | de620_set_register(dev, W_TCR, (TCR_DEF & ~RXPBM) | RXALL); |
| 499 | } | 492 | } |
| 500 | else | 493 | else |
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c index 0b0f1c407a7e..f42c23f42652 100644 --- a/drivers/net/dm9000.c +++ b/drivers/net/dm9000.c | |||
| @@ -1374,6 +1374,11 @@ dm9000_probe(struct platform_device *pdev) | |||
| 1374 | for (i = 0; i < 6; i += 2) | 1374 | for (i = 0; i < 6; i += 2) |
| 1375 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | 1375 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); |
| 1376 | 1376 | ||
| 1377 | if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) { | ||
| 1378 | mac_src = "platform data"; | ||
| 1379 | memcpy(ndev->dev_addr, pdata->dev_addr, 6); | ||
| 1380 | } | ||
| 1381 | |||
| 1377 | if (!is_valid_ether_addr(ndev->dev_addr)) { | 1382 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
| 1378 | /* try reading from mac */ | 1383 | /* try reading from mac */ |
| 1379 | 1384 | ||
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index 4a4f62e002b2..cf57050d99d8 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
| @@ -41,24 +41,25 @@ | |||
| 41 | 41 | ||
| 42 | struct e1000_info; | 42 | struct e1000_info; |
| 43 | 43 | ||
| 44 | #define ndev_printk(level, netdev, format, arg...) \ | 44 | #define e_printk(level, adapter, format, arg...) \ |
| 45 | printk(level "%s: " format, (netdev)->name, ## arg) | 45 | printk(level "%s: %s: " format, pci_name(adapter->pdev), \ |
| 46 | adapter->netdev->name, ## arg) | ||
| 46 | 47 | ||
| 47 | #ifdef DEBUG | 48 | #ifdef DEBUG |
| 48 | #define ndev_dbg(netdev, format, arg...) \ | 49 | #define e_dbg(format, arg...) \ |
| 49 | ndev_printk(KERN_DEBUG , netdev, format, ## arg) | 50 | e_printk(KERN_DEBUG , adapter, format, ## arg) |
| 50 | #else | 51 | #else |
| 51 | #define ndev_dbg(netdev, format, arg...) do { (void)(netdev); } while (0) | 52 | #define e_dbg(format, arg...) do { (void)(adapter); } while (0) |
| 52 | #endif | 53 | #endif |
| 53 | 54 | ||
| 54 | #define ndev_err(netdev, format, arg...) \ | 55 | #define e_err(format, arg...) \ |
| 55 | ndev_printk(KERN_ERR , netdev, format, ## arg) | 56 | e_printk(KERN_ERR, adapter, format, ## arg) |
| 56 | #define ndev_info(netdev, format, arg...) \ | 57 | #define e_info(format, arg...) \ |
| 57 | ndev_printk(KERN_INFO , netdev, format, ## arg) | 58 | e_printk(KERN_INFO, adapter, format, ## arg) |
| 58 | #define ndev_warn(netdev, format, arg...) \ | 59 | #define e_warn(format, arg...) \ |
| 59 | ndev_printk(KERN_WARNING , netdev, format, ## arg) | 60 | e_printk(KERN_WARNING, adapter, format, ## arg) |
| 60 | #define ndev_notice(netdev, format, arg...) \ | 61 | #define e_notice(format, arg...) \ |
| 61 | ndev_printk(KERN_NOTICE , netdev, format, ## arg) | 62 | e_printk(KERN_NOTICE, adapter, format, ## arg) |
| 62 | 63 | ||
| 63 | 64 | ||
| 64 | /* Tx/Rx descriptor defines */ | 65 | /* Tx/Rx descriptor defines */ |
| @@ -283,10 +284,6 @@ struct e1000_adapter { | |||
| 283 | unsigned long led_status; | 284 | unsigned long led_status; |
| 284 | 285 | ||
| 285 | unsigned int flags; | 286 | unsigned int flags; |
| 286 | |||
| 287 | /* for ioport free */ | ||
| 288 | int bars; | ||
| 289 | int need_ioport; | ||
| 290 | }; | 287 | }; |
| 291 | 288 | ||
| 292 | struct e1000_info { | 289 | struct e1000_info { |
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index 9350564065e7..cf9679f2b7c4 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c | |||
| @@ -189,8 +189,7 @@ static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) | |||
| 189 | /* Fiber NICs only allow 1000 gbps Full duplex */ | 189 | /* Fiber NICs only allow 1000 gbps Full duplex */ |
| 190 | if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && | 190 | if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && |
| 191 | spddplx != (SPEED_1000 + DUPLEX_FULL)) { | 191 | spddplx != (SPEED_1000 + DUPLEX_FULL)) { |
| 192 | ndev_err(adapter->netdev, "Unsupported Speed/Duplex " | 192 | e_err("Unsupported Speed/Duplex configuration\n"); |
| 193 | "configuration\n"); | ||
| 194 | return -EINVAL; | 193 | return -EINVAL; |
| 195 | } | 194 | } |
| 196 | 195 | ||
| @@ -213,8 +212,7 @@ static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) | |||
| 213 | break; | 212 | break; |
| 214 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | 213 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ |
| 215 | default: | 214 | default: |
| 216 | ndev_err(adapter->netdev, "Unsupported Speed/Duplex " | 215 | e_err("Unsupported Speed/Duplex configuration\n"); |
| 217 | "configuration\n"); | ||
| 218 | return -EINVAL; | 216 | return -EINVAL; |
| 219 | } | 217 | } |
| 220 | return 0; | 218 | return 0; |
| @@ -231,8 +229,8 @@ static int e1000_set_settings(struct net_device *netdev, | |||
| 231 | * cannot be changed | 229 | * cannot be changed |
| 232 | */ | 230 | */ |
| 233 | if (e1000_check_reset_block(hw)) { | 231 | if (e1000_check_reset_block(hw)) { |
| 234 | ndev_err(netdev, "Cannot change link " | 232 | e_err("Cannot change link characteristics when SoL/IDER is " |
| 235 | "characteristics when SoL/IDER is active.\n"); | 233 | "active.\n"); |
| 236 | return -EINVAL; | 234 | return -EINVAL; |
| 237 | } | 235 | } |
| 238 | 236 | ||
| @@ -380,8 +378,7 @@ static int e1000_set_tso(struct net_device *netdev, u32 data) | |||
| 380 | netdev->features &= ~NETIF_F_TSO6; | 378 | netdev->features &= ~NETIF_F_TSO6; |
| 381 | } | 379 | } |
| 382 | 380 | ||
| 383 | ndev_info(netdev, "TSO is %s\n", | 381 | e_info("TSO is %s\n", data ? "Enabled" : "Disabled"); |
| 384 | data ? "Enabled" : "Disabled"); | ||
| 385 | adapter->flags |= FLAG_TSO_FORCE; | 382 | adapter->flags |= FLAG_TSO_FORCE; |
| 386 | return 0; | 383 | return 0; |
| 387 | } | 384 | } |
| @@ -722,10 +719,9 @@ static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, | |||
| 722 | (test[pat] & write)); | 719 | (test[pat] & write)); |
| 723 | val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset); | 720 | val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset); |
| 724 | if (val != (test[pat] & write & mask)) { | 721 | if (val != (test[pat] & write & mask)) { |
| 725 | ndev_err(adapter->netdev, "pattern test reg %04X " | 722 | e_err("pattern test reg %04X failed: got 0x%08X " |
| 726 | "failed: got 0x%08X expected 0x%08X\n", | 723 | "expected 0x%08X\n", reg + offset, val, |
| 727 | reg + offset, | 724 | (test[pat] & write & mask)); |
| 728 | val, (test[pat] & write & mask)); | ||
| 729 | *data = reg; | 725 | *data = reg; |
| 730 | return 1; | 726 | return 1; |
| 731 | } | 727 | } |
| @@ -740,9 +736,8 @@ static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data, | |||
| 740 | __ew32(&adapter->hw, reg, write & mask); | 736 | __ew32(&adapter->hw, reg, write & mask); |
| 741 | val = __er32(&adapter->hw, reg); | 737 | val = __er32(&adapter->hw, reg); |
| 742 | if ((write & mask) != (val & mask)) { | 738 | if ((write & mask) != (val & mask)) { |
| 743 | ndev_err(adapter->netdev, "set/check reg %04X test failed: " | 739 | e_err("set/check reg %04X test failed: got 0x%08X " |
| 744 | "got 0x%08X expected 0x%08X\n", reg, (val & mask), | 740 | "expected 0x%08X\n", reg, (val & mask), (write & mask)); |
| 745 | (write & mask)); | ||
| 746 | *data = reg; | 741 | *data = reg; |
| 747 | return 1; | 742 | return 1; |
| 748 | } | 743 | } |
| @@ -766,7 +761,6 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
| 766 | { | 761 | { |
| 767 | struct e1000_hw *hw = &adapter->hw; | 762 | struct e1000_hw *hw = &adapter->hw; |
| 768 | struct e1000_mac_info *mac = &adapter->hw.mac; | 763 | struct e1000_mac_info *mac = &adapter->hw.mac; |
| 769 | struct net_device *netdev = adapter->netdev; | ||
| 770 | u32 value; | 764 | u32 value; |
| 771 | u32 before; | 765 | u32 before; |
| 772 | u32 after; | 766 | u32 after; |
| @@ -799,8 +793,8 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
| 799 | ew32(STATUS, toggle); | 793 | ew32(STATUS, toggle); |
| 800 | after = er32(STATUS) & toggle; | 794 | after = er32(STATUS) & toggle; |
| 801 | if (value != after) { | 795 | if (value != after) { |
| 802 | ndev_err(netdev, "failed STATUS register test got: " | 796 | e_err("failed STATUS register test got: 0x%08X expected: " |
| 803 | "0x%08X expected: 0x%08X\n", after, value); | 797 | "0x%08X\n", after, value); |
| 804 | *data = 1; | 798 | *data = 1; |
| 805 | return 1; | 799 | return 1; |
| 806 | } | 800 | } |
| @@ -903,8 +897,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) | |||
| 903 | *data = 1; | 897 | *data = 1; |
| 904 | return -1; | 898 | return -1; |
| 905 | } | 899 | } |
| 906 | ndev_info(netdev, "testing %s interrupt\n", | 900 | e_info("testing %s interrupt\n", (shared_int ? "shared" : "unshared")); |
| 907 | (shared_int ? "shared" : "unshared")); | ||
| 908 | 901 | ||
| 909 | /* Disable all the interrupts */ | 902 | /* Disable all the interrupts */ |
| 910 | ew32(IMC, 0xFFFFFFFF); | 903 | ew32(IMC, 0xFFFFFFFF); |
| @@ -1526,8 +1519,7 @@ static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data) | |||
| 1526 | * sessions are active | 1519 | * sessions are active |
| 1527 | */ | 1520 | */ |
| 1528 | if (e1000_check_reset_block(&adapter->hw)) { | 1521 | if (e1000_check_reset_block(&adapter->hw)) { |
| 1529 | ndev_err(adapter->netdev, "Cannot do PHY loopback test " | 1522 | e_err("Cannot do PHY loopback test when SoL/IDER is active.\n"); |
| 1530 | "when SoL/IDER is active.\n"); | ||
| 1531 | *data = 0; | 1523 | *data = 0; |
| 1532 | goto out; | 1524 | goto out; |
| 1533 | } | 1525 | } |
| @@ -1612,7 +1604,7 @@ static void e1000_diag_test(struct net_device *netdev, | |||
| 1612 | forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; | 1604 | forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; |
| 1613 | autoneg = adapter->hw.mac.autoneg; | 1605 | autoneg = adapter->hw.mac.autoneg; |
| 1614 | 1606 | ||
| 1615 | ndev_info(netdev, "offline testing starting\n"); | 1607 | e_info("offline testing starting\n"); |
| 1616 | 1608 | ||
| 1617 | /* | 1609 | /* |
| 1618 | * Link test performed before hardware reset so autoneg doesn't | 1610 | * Link test performed before hardware reset so autoneg doesn't |
| @@ -1658,7 +1650,7 @@ static void e1000_diag_test(struct net_device *netdev, | |||
| 1658 | if (if_running) | 1650 | if (if_running) |
| 1659 | dev_open(netdev); | 1651 | dev_open(netdev); |
| 1660 | } else { | 1652 | } else { |
| 1661 | ndev_info(netdev, "online testing starting\n"); | 1653 | e_info("online testing starting\n"); |
| 1662 | /* Online tests */ | 1654 | /* Online tests */ |
| 1663 | if (e1000_link_test(adapter, &data[4])) | 1655 | if (e1000_link_test(adapter, &data[4])) |
| 1664 | eth_test->flags |= ETH_TEST_FL_FAILED; | 1656 | eth_test->flags |= ETH_TEST_FL_FAILED; |
| @@ -1694,8 +1686,8 @@ static void e1000_get_wol(struct net_device *netdev, | |||
| 1694 | wol->supported &= ~WAKE_UCAST; | 1686 | wol->supported &= ~WAKE_UCAST; |
| 1695 | 1687 | ||
| 1696 | if (adapter->wol & E1000_WUFC_EX) | 1688 | if (adapter->wol & E1000_WUFC_EX) |
| 1697 | ndev_err(netdev, "Interface does not support " | 1689 | e_err("Interface does not support directed (unicast) " |
| 1698 | "directed (unicast) frame wake-up packets\n"); | 1690 | "frame wake-up packets\n"); |
| 1699 | } | 1691 | } |
| 1700 | 1692 | ||
| 1701 | if (adapter->wol & E1000_WUFC_EX) | 1693 | if (adapter->wol & E1000_WUFC_EX) |
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index d13677899767..05b0b2f9c54b 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
| @@ -484,8 +484,8 @@ static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, | |||
| 484 | * packet, also make sure the frame isn't just CRC only */ | 484 | * packet, also make sure the frame isn't just CRC only */ |
| 485 | if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) { | 485 | if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) { |
| 486 | /* All receives must fit into a single buffer */ | 486 | /* All receives must fit into a single buffer */ |
| 487 | ndev_dbg(netdev, "%s: Receive packet consumed " | 487 | e_dbg("%s: Receive packet consumed multiple buffers\n", |
| 488 | "multiple buffers\n", netdev->name); | 488 | netdev->name); |
| 489 | /* recycle */ | 489 | /* recycle */ |
| 490 | buffer_info->skb = skb; | 490 | buffer_info->skb = skb; |
| 491 | goto next_desc; | 491 | goto next_desc; |
| @@ -576,28 +576,26 @@ static void e1000_print_tx_hang(struct e1000_adapter *adapter) | |||
| 576 | unsigned int i = tx_ring->next_to_clean; | 576 | unsigned int i = tx_ring->next_to_clean; |
| 577 | unsigned int eop = tx_ring->buffer_info[i].next_to_watch; | 577 | unsigned int eop = tx_ring->buffer_info[i].next_to_watch; |
| 578 | struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); | 578 | struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); |
| 579 | struct net_device *netdev = adapter->netdev; | ||
| 580 | 579 | ||
| 581 | /* detected Tx unit hang */ | 580 | /* detected Tx unit hang */ |
| 582 | ndev_err(netdev, | 581 | e_err("Detected Tx Unit Hang:\n" |
| 583 | "Detected Tx Unit Hang:\n" | 582 | " TDH <%x>\n" |
| 584 | " TDH <%x>\n" | 583 | " TDT <%x>\n" |
| 585 | " TDT <%x>\n" | 584 | " next_to_use <%x>\n" |
| 586 | " next_to_use <%x>\n" | 585 | " next_to_clean <%x>\n" |
| 587 | " next_to_clean <%x>\n" | 586 | "buffer_info[next_to_clean]:\n" |
| 588 | "buffer_info[next_to_clean]:\n" | 587 | " time_stamp <%lx>\n" |
| 589 | " time_stamp <%lx>\n" | 588 | " next_to_watch <%x>\n" |
| 590 | " next_to_watch <%x>\n" | 589 | " jiffies <%lx>\n" |
| 591 | " jiffies <%lx>\n" | 590 | " next_to_watch.status <%x>\n", |
| 592 | " next_to_watch.status <%x>\n", | 591 | readl(adapter->hw.hw_addr + tx_ring->head), |
| 593 | readl(adapter->hw.hw_addr + tx_ring->head), | 592 | readl(adapter->hw.hw_addr + tx_ring->tail), |
| 594 | readl(adapter->hw.hw_addr + tx_ring->tail), | 593 | tx_ring->next_to_use, |
| 595 | tx_ring->next_to_use, | 594 | tx_ring->next_to_clean, |
| 596 | tx_ring->next_to_clean, | 595 | tx_ring->buffer_info[eop].time_stamp, |
| 597 | tx_ring->buffer_info[eop].time_stamp, | 596 | eop, |
| 598 | eop, | 597 | jiffies, |
| 599 | jiffies, | 598 | eop_desc->upper.fields.status); |
| 600 | eop_desc->upper.fields.status); | ||
| 601 | } | 599 | } |
| 602 | 600 | ||
| 603 | /** | 601 | /** |
| @@ -747,8 +745,8 @@ static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, | |||
| 747 | buffer_info->dma = 0; | 745 | buffer_info->dma = 0; |
| 748 | 746 | ||
| 749 | if (!(staterr & E1000_RXD_STAT_EOP)) { | 747 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
| 750 | ndev_dbg(netdev, "%s: Packet Split buffers didn't pick " | 748 | e_dbg("%s: Packet Split buffers didn't pick up the " |
| 751 | "up the full packet\n", netdev->name); | 749 | "full packet\n", netdev->name); |
| 752 | dev_kfree_skb_irq(skb); | 750 | dev_kfree_skb_irq(skb); |
| 753 | goto next_desc; | 751 | goto next_desc; |
| 754 | } | 752 | } |
| @@ -761,8 +759,8 @@ static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, | |||
| 761 | length = le16_to_cpu(rx_desc->wb.middle.length0); | 759 | length = le16_to_cpu(rx_desc->wb.middle.length0); |
| 762 | 760 | ||
| 763 | if (!length) { | 761 | if (!length) { |
| 764 | ndev_dbg(netdev, "%s: Last part of the packet spanning" | 762 | e_dbg("%s: Last part of the packet spanning multiple " |
| 765 | " multiple descriptors\n", netdev->name); | 763 | "descriptors\n", netdev->name); |
| 766 | dev_kfree_skb_irq(skb); | 764 | dev_kfree_skb_irq(skb); |
| 767 | goto next_desc; | 765 | goto next_desc; |
| 768 | } | 766 | } |
| @@ -1011,7 +1009,7 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter, | |||
| 1011 | 1009 | ||
| 1012 | /* eth type trans needs skb->data to point to something */ | 1010 | /* eth type trans needs skb->data to point to something */ |
| 1013 | if (!pskb_may_pull(skb, ETH_HLEN)) { | 1011 | if (!pskb_may_pull(skb, ETH_HLEN)) { |
| 1014 | ndev_err(netdev, "pskb_may_pull failed.\n"); | 1012 | e_err("pskb_may_pull failed.\n"); |
| 1015 | dev_kfree_skb(skb); | 1013 | dev_kfree_skb(skb); |
| 1016 | goto next_desc; | 1014 | goto next_desc; |
| 1017 | } | 1015 | } |
| @@ -1251,10 +1249,8 @@ static int e1000_request_irq(struct e1000_adapter *adapter) | |||
| 1251 | err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, | 1249 | err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, |
| 1252 | netdev); | 1250 | netdev); |
| 1253 | if (err) { | 1251 | if (err) { |
| 1254 | ndev_err(netdev, | 1252 | e_err("Unable to allocate %s interrupt (return: %d)\n", |
| 1255 | "Unable to allocate %s interrupt (return: %d)\n", | 1253 | adapter->flags & FLAG_MSI_ENABLED ? "MSI":"INTx", err); |
| 1256 | adapter->flags & FLAG_MSI_ENABLED ? "MSI":"INTx", | ||
| 1257 | err); | ||
| 1258 | if (adapter->flags & FLAG_MSI_ENABLED) | 1254 | if (adapter->flags & FLAG_MSI_ENABLED) |
| 1259 | pci_disable_msi(adapter->pdev); | 1255 | pci_disable_msi(adapter->pdev); |
| 1260 | } | 1256 | } |
| @@ -1395,8 +1391,7 @@ int e1000e_setup_tx_resources(struct e1000_adapter *adapter) | |||
| 1395 | return 0; | 1391 | return 0; |
| 1396 | err: | 1392 | err: |
| 1397 | vfree(tx_ring->buffer_info); | 1393 | vfree(tx_ring->buffer_info); |
| 1398 | ndev_err(adapter->netdev, | 1394 | e_err("Unable to allocate memory for the transmit descriptor ring\n"); |
| 1399 | "Unable to allocate memory for the transmit descriptor ring\n"); | ||
| 1400 | return err; | 1395 | return err; |
| 1401 | } | 1396 | } |
| 1402 | 1397 | ||
| @@ -1450,8 +1445,7 @@ err_pages: | |||
| 1450 | } | 1445 | } |
| 1451 | err: | 1446 | err: |
| 1452 | vfree(rx_ring->buffer_info); | 1447 | vfree(rx_ring->buffer_info); |
| 1453 | ndev_err(adapter->netdev, | 1448 | e_err("Unable to allocate memory for the transmit descriptor ring\n"); |
| 1454 | "Unable to allocate memory for the transmit descriptor ring\n"); | ||
| 1455 | return err; | 1449 | return err; |
| 1456 | } | 1450 | } |
| 1457 | 1451 | ||
| @@ -2450,13 +2444,13 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
| 2450 | * For parts with AMT enabled, let the firmware know | 2444 | * For parts with AMT enabled, let the firmware know |
| 2451 | * that the network interface is in control | 2445 | * that the network interface is in control |
| 2452 | */ | 2446 | */ |
| 2453 | if ((adapter->flags & FLAG_HAS_AMT) && e1000e_check_mng_mode(hw)) | 2447 | if (adapter->flags & FLAG_HAS_AMT) |
| 2454 | e1000_get_hw_control(adapter); | 2448 | e1000_get_hw_control(adapter); |
| 2455 | 2449 | ||
| 2456 | ew32(WUC, 0); | 2450 | ew32(WUC, 0); |
| 2457 | 2451 | ||
| 2458 | if (mac->ops.init_hw(hw)) | 2452 | if (mac->ops.init_hw(hw)) |
| 2459 | ndev_err(adapter->netdev, "Hardware Error\n"); | 2453 | e_err("Hardware Error\n"); |
| 2460 | 2454 | ||
| 2461 | e1000_update_mng_vlan(adapter); | 2455 | e1000_update_mng_vlan(adapter); |
| 2462 | 2456 | ||
| @@ -2591,7 +2585,7 @@ static int __devinit e1000_sw_init(struct e1000_adapter *adapter) | |||
| 2591 | return 0; | 2585 | return 0; |
| 2592 | 2586 | ||
| 2593 | err: | 2587 | err: |
| 2594 | ndev_err(netdev, "Unable to allocate memory for queues\n"); | 2588 | e_err("Unable to allocate memory for queues\n"); |
| 2595 | kfree(adapter->rx_ring); | 2589 | kfree(adapter->rx_ring); |
| 2596 | kfree(adapter->tx_ring); | 2590 | kfree(adapter->tx_ring); |
| 2597 | return -ENOMEM; | 2591 | return -ENOMEM; |
| @@ -2640,8 +2634,7 @@ static int e1000_open(struct net_device *netdev) | |||
| 2640 | * If AMT is enabled, let the firmware know that the network | 2634 | * If AMT is enabled, let the firmware know that the network |
| 2641 | * interface is now open | 2635 | * interface is now open |
| 2642 | */ | 2636 | */ |
| 2643 | if ((adapter->flags & FLAG_HAS_AMT) && | 2637 | if (adapter->flags & FLAG_HAS_AMT) |
| 2644 | e1000e_check_mng_mode(&adapter->hw)) | ||
| 2645 | e1000_get_hw_control(adapter); | 2638 | e1000_get_hw_control(adapter); |
| 2646 | 2639 | ||
| 2647 | /* | 2640 | /* |
| @@ -2719,8 +2712,7 @@ static int e1000_close(struct net_device *netdev) | |||
| 2719 | * If AMT is enabled, let the firmware know that the network | 2712 | * If AMT is enabled, let the firmware know that the network |
| 2720 | * interface is now closed | 2713 | * interface is now closed |
| 2721 | */ | 2714 | */ |
| 2722 | if ((adapter->flags & FLAG_HAS_AMT) && | 2715 | if (adapter->flags & FLAG_HAS_AMT) |
| 2723 | e1000e_check_mng_mode(&adapter->hw)) | ||
| 2724 | e1000_release_hw_control(adapter); | 2716 | e1000_release_hw_control(adapter); |
| 2725 | 2717 | ||
| 2726 | return 0; | 2718 | return 0; |
| @@ -2917,8 +2909,7 @@ static void e1000_phy_read_status(struct e1000_adapter *adapter) | |||
| 2917 | ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000); | 2909 | ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000); |
| 2918 | ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus); | 2910 | ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus); |
| 2919 | if (ret_val) | 2911 | if (ret_val) |
| 2920 | ndev_warn(adapter->netdev, | 2912 | e_warn("Error reading PHY register\n"); |
| 2921 | "Error reading PHY register\n"); | ||
| 2922 | } else { | 2913 | } else { |
| 2923 | /* | 2914 | /* |
| 2924 | * Do not read PHY registers if link is not up | 2915 | * Do not read PHY registers if link is not up |
| @@ -2943,18 +2934,16 @@ static void e1000_phy_read_status(struct e1000_adapter *adapter) | |||
| 2943 | static void e1000_print_link_info(struct e1000_adapter *adapter) | 2934 | static void e1000_print_link_info(struct e1000_adapter *adapter) |
| 2944 | { | 2935 | { |
| 2945 | struct e1000_hw *hw = &adapter->hw; | 2936 | struct e1000_hw *hw = &adapter->hw; |
| 2946 | struct net_device *netdev = adapter->netdev; | ||
| 2947 | u32 ctrl = er32(CTRL); | 2937 | u32 ctrl = er32(CTRL); |
| 2948 | 2938 | ||
| 2949 | ndev_info(netdev, | 2939 | e_info("Link is Up %d Mbps %s, Flow Control: %s\n", |
| 2950 | "Link is Up %d Mbps %s, Flow Control: %s\n", | 2940 | adapter->link_speed, |
| 2951 | adapter->link_speed, | 2941 | (adapter->link_duplex == FULL_DUPLEX) ? |
| 2952 | (adapter->link_duplex == FULL_DUPLEX) ? | 2942 | "Full Duplex" : "Half Duplex", |
| 2953 | "Full Duplex" : "Half Duplex", | 2943 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ? |
| 2954 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ? | 2944 | "RX/TX" : |
| 2955 | "RX/TX" : | 2945 | ((ctrl & E1000_CTRL_RFCE) ? "RX" : |
| 2956 | ((ctrl & E1000_CTRL_RFCE) ? "RX" : | 2946 | ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None" ))); |
| 2957 | ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None" ))); | ||
| 2958 | } | 2947 | } |
| 2959 | 2948 | ||
| 2960 | static bool e1000_has_link(struct e1000_adapter *adapter) | 2949 | static bool e1000_has_link(struct e1000_adapter *adapter) |
| @@ -2994,8 +2983,7 @@ static bool e1000_has_link(struct e1000_adapter *adapter) | |||
| 2994 | if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && | 2983 | if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && |
| 2995 | (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { | 2984 | (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { |
| 2996 | /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ | 2985 | /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ |
| 2997 | ndev_info(adapter->netdev, | 2986 | e_info("Gigabit has been disabled, downgrading speed\n"); |
| 2998 | "Gigabit has been disabled, downgrading speed\n"); | ||
| 2999 | } | 2987 | } |
| 3000 | 2988 | ||
| 3001 | return link_active; | 2989 | return link_active; |
| @@ -3096,8 +3084,7 @@ static void e1000_watchdog_task(struct work_struct *work) | |||
| 3096 | switch (adapter->link_speed) { | 3084 | switch (adapter->link_speed) { |
| 3097 | case SPEED_10: | 3085 | case SPEED_10: |
| 3098 | case SPEED_100: | 3086 | case SPEED_100: |
| 3099 | ndev_info(netdev, | 3087 | e_info("10/100 speed: disabling TSO\n"); |
| 3100 | "10/100 speed: disabling TSO\n"); | ||
| 3101 | netdev->features &= ~NETIF_F_TSO; | 3088 | netdev->features &= ~NETIF_F_TSO; |
| 3102 | netdev->features &= ~NETIF_F_TSO6; | 3089 | netdev->features &= ~NETIF_F_TSO6; |
| 3103 | break; | 3090 | break; |
| @@ -3130,7 +3117,7 @@ static void e1000_watchdog_task(struct work_struct *work) | |||
| 3130 | if (netif_carrier_ok(netdev)) { | 3117 | if (netif_carrier_ok(netdev)) { |
| 3131 | adapter->link_speed = 0; | 3118 | adapter->link_speed = 0; |
| 3132 | adapter->link_duplex = 0; | 3119 | adapter->link_duplex = 0; |
| 3133 | ndev_info(netdev, "Link is Down\n"); | 3120 | e_info("Link is Down\n"); |
| 3134 | netif_carrier_off(netdev); | 3121 | netif_carrier_off(netdev); |
| 3135 | netif_tx_stop_all_queues(netdev); | 3122 | netif_tx_stop_all_queues(netdev); |
| 3136 | if (!test_bit(__E1000_DOWN, &adapter->state)) | 3123 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
| @@ -3604,8 +3591,7 @@ static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
| 3604 | 3591 | ||
| 3605 | pull_size = min((unsigned int)4, skb->data_len); | 3592 | pull_size = min((unsigned int)4, skb->data_len); |
| 3606 | if (!__pskb_pull_tail(skb, pull_size)) { | 3593 | if (!__pskb_pull_tail(skb, pull_size)) { |
| 3607 | ndev_err(netdev, | 3594 | e_err("__pskb_pull_tail failed.\n"); |
| 3608 | "__pskb_pull_tail failed.\n"); | ||
| 3609 | dev_kfree_skb_any(skb); | 3595 | dev_kfree_skb_any(skb); |
| 3610 | return NETDEV_TX_OK; | 3596 | return NETDEV_TX_OK; |
| 3611 | } | 3597 | } |
| @@ -3737,25 +3723,25 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
| 3737 | 3723 | ||
| 3738 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | 3724 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || |
| 3739 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | 3725 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
| 3740 | ndev_err(netdev, "Invalid MTU setting\n"); | 3726 | e_err("Invalid MTU setting\n"); |
| 3741 | return -EINVAL; | 3727 | return -EINVAL; |
| 3742 | } | 3728 | } |
| 3743 | 3729 | ||
| 3744 | /* Jumbo frame size limits */ | 3730 | /* Jumbo frame size limits */ |
| 3745 | if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) { | 3731 | if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) { |
| 3746 | if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { | 3732 | if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { |
| 3747 | ndev_err(netdev, "Jumbo Frames not supported.\n"); | 3733 | e_err("Jumbo Frames not supported.\n"); |
| 3748 | return -EINVAL; | 3734 | return -EINVAL; |
| 3749 | } | 3735 | } |
| 3750 | if (adapter->hw.phy.type == e1000_phy_ife) { | 3736 | if (adapter->hw.phy.type == e1000_phy_ife) { |
| 3751 | ndev_err(netdev, "Jumbo Frames not supported.\n"); | 3737 | e_err("Jumbo Frames not supported.\n"); |
| 3752 | return -EINVAL; | 3738 | return -EINVAL; |
| 3753 | } | 3739 | } |
| 3754 | } | 3740 | } |
| 3755 | 3741 | ||
| 3756 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 | 3742 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 |
| 3757 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { | 3743 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
| 3758 | ndev_err(netdev, "MTU > 9216 not supported.\n"); | 3744 | e_err("MTU > 9216 not supported.\n"); |
| 3759 | return -EINVAL; | 3745 | return -EINVAL; |
| 3760 | } | 3746 | } |
| 3761 | 3747 | ||
| @@ -3792,8 +3778,7 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
| 3792 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN | 3778 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN |
| 3793 | + ETH_FCS_LEN; | 3779 | + ETH_FCS_LEN; |
| 3794 | 3780 | ||
| 3795 | ndev_info(netdev, "changing MTU from %d to %d\n", | 3781 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
| 3796 | netdev->mtu, new_mtu); | ||
| 3797 | netdev->mtu = new_mtu; | 3782 | netdev->mtu = new_mtu; |
| 3798 | 3783 | ||
| 3799 | if (netif_running(netdev)) | 3784 | if (netif_running(netdev)) |
| @@ -4006,10 +3991,7 @@ static int e1000_resume(struct pci_dev *pdev) | |||
| 4006 | pci_restore_state(pdev); | 3991 | pci_restore_state(pdev); |
| 4007 | e1000e_disable_l1aspm(pdev); | 3992 | e1000e_disable_l1aspm(pdev); |
| 4008 | 3993 | ||
| 4009 | if (adapter->need_ioport) | 3994 | err = pci_enable_device_mem(pdev); |
| 4010 | err = pci_enable_device(pdev); | ||
| 4011 | else | ||
| 4012 | err = pci_enable_device_mem(pdev); | ||
| 4013 | if (err) { | 3995 | if (err) { |
| 4014 | dev_err(&pdev->dev, | 3996 | dev_err(&pdev->dev, |
| 4015 | "Cannot enable PCI device from suspend\n"); | 3997 | "Cannot enable PCI device from suspend\n"); |
| @@ -4043,7 +4025,7 @@ static int e1000_resume(struct pci_dev *pdev) | |||
| 4043 | * is up. For all other cases, let the f/w know that the h/w is now | 4025 | * is up. For all other cases, let the f/w know that the h/w is now |
| 4044 | * under the control of the driver. | 4026 | * under the control of the driver. |
| 4045 | */ | 4027 | */ |
| 4046 | if (!(adapter->flags & FLAG_HAS_AMT) || !e1000e_check_mng_mode(&adapter->hw)) | 4028 | if (!(adapter->flags & FLAG_HAS_AMT)) |
| 4047 | e1000_get_hw_control(adapter); | 4029 | e1000_get_hw_control(adapter); |
| 4048 | 4030 | ||
| 4049 | return 0; | 4031 | return 0; |
| @@ -4111,10 +4093,7 @@ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) | |||
| 4111 | int err; | 4093 | int err; |
| 4112 | 4094 | ||
| 4113 | e1000e_disable_l1aspm(pdev); | 4095 | e1000e_disable_l1aspm(pdev); |
| 4114 | if (adapter->need_ioport) | 4096 | err = pci_enable_device_mem(pdev); |
| 4115 | err = pci_enable_device(pdev); | ||
| 4116 | else | ||
| 4117 | err = pci_enable_device_mem(pdev); | ||
| 4118 | if (err) { | 4097 | if (err) { |
| 4119 | dev_err(&pdev->dev, | 4098 | dev_err(&pdev->dev, |
| 4120 | "Cannot re-enable PCI device after reset.\n"); | 4099 | "Cannot re-enable PCI device after reset.\n"); |
| @@ -4162,8 +4141,7 @@ static void e1000_io_resume(struct pci_dev *pdev) | |||
| 4162 | * is up. For all other cases, let the f/w know that the h/w is now | 4141 | * is up. For all other cases, let the f/w know that the h/w is now |
| 4163 | * under the control of the driver. | 4142 | * under the control of the driver. |
| 4164 | */ | 4143 | */ |
| 4165 | if (!(adapter->flags & FLAG_HAS_AMT) || | 4144 | if (!(adapter->flags & FLAG_HAS_AMT)) |
| 4166 | !e1000e_check_mng_mode(&adapter->hw)) | ||
| 4167 | e1000_get_hw_control(adapter); | 4145 | e1000_get_hw_control(adapter); |
| 4168 | 4146 | ||
| 4169 | } | 4147 | } |
| @@ -4175,36 +4153,40 @@ static void e1000_print_device_info(struct e1000_adapter *adapter) | |||
| 4175 | u32 pba_num; | 4153 | u32 pba_num; |
| 4176 | 4154 | ||
| 4177 | /* print bus type/speed/width info */ | 4155 | /* print bus type/speed/width info */ |
| 4178 | ndev_info(netdev, "(PCI Express:2.5GB/s:%s) " | 4156 | e_info("(PCI Express:2.5GB/s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 4179 | "%02x:%02x:%02x:%02x:%02x:%02x\n", | 4157 | /* bus width */ |
| 4180 | /* bus width */ | 4158 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
| 4181 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : | 4159 | "Width x1"), |
| 4182 | "Width x1"), | 4160 | /* MAC address */ |
| 4183 | /* MAC address */ | 4161 | netdev->dev_addr[0], netdev->dev_addr[1], |
| 4184 | netdev->dev_addr[0], netdev->dev_addr[1], | 4162 | netdev->dev_addr[2], netdev->dev_addr[3], |
| 4185 | netdev->dev_addr[2], netdev->dev_addr[3], | 4163 | netdev->dev_addr[4], netdev->dev_addr[5]); |
| 4186 | netdev->dev_addr[4], netdev->dev_addr[5]); | 4164 | e_info("Intel(R) PRO/%s Network Connection\n", |
| 4187 | ndev_info(netdev, "Intel(R) PRO/%s Network Connection\n", | 4165 | (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); |
| 4188 | (hw->phy.type == e1000_phy_ife) | ||
| 4189 | ? "10/100" : "1000"); | ||
| 4190 | e1000e_read_pba_num(hw, &pba_num); | 4166 | e1000e_read_pba_num(hw, &pba_num); |
| 4191 | ndev_info(netdev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | 4167 | e_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n", |
| 4192 | hw->mac.type, hw->phy.type, | 4168 | hw->mac.type, hw->phy.type, (pba_num >> 8), (pba_num & 0xff)); |
| 4193 | (pba_num >> 8), (pba_num & 0xff)); | ||
| 4194 | } | 4169 | } |
| 4195 | 4170 | ||
| 4196 | /** | 4171 | static void e1000_eeprom_checks(struct e1000_adapter *adapter) |
| 4197 | * e1000e_is_need_ioport - determine if an adapter needs ioport resources or not | ||
| 4198 | * @pdev: PCI device information struct | ||
| 4199 | * | ||
| 4200 | * Returns true if an adapters needs ioport resources | ||
| 4201 | **/ | ||
| 4202 | static int e1000e_is_need_ioport(struct pci_dev *pdev) | ||
| 4203 | { | 4172 | { |
| 4204 | switch (pdev->device) { | 4173 | struct e1000_hw *hw = &adapter->hw; |
| 4205 | /* Currently there are no adapters that need ioport resources */ | 4174 | int ret_val; |
| 4206 | default: | 4175 | u16 buf = 0; |
| 4207 | return false; | 4176 | |
| 4177 | if (hw->mac.type != e1000_82573) | ||
| 4178 | return; | ||
| 4179 | |||
| 4180 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); | ||
| 4181 | if (!(le16_to_cpu(buf) & (1 << 0))) { | ||
| 4182 | /* Deep Smart Power Down (DSPD) */ | ||
| 4183 | e_warn("Warning: detected DSPD enabled in EEPROM\n"); | ||
| 4184 | } | ||
| 4185 | |||
| 4186 | ret_val = e1000_read_nvm(hw, NVM_INIT_3GIO_3, 1, &buf); | ||
| 4187 | if (le16_to_cpu(buf) & (3 << 2)) { | ||
| 4188 | /* ASPM enable */ | ||
| 4189 | e_warn("Warning: detected ASPM enabled in EEPROM\n"); | ||
| 4208 | } | 4190 | } |
| 4209 | } | 4191 | } |
| 4210 | 4192 | ||
| @@ -4233,19 +4215,10 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4233 | int i, err, pci_using_dac; | 4215 | int i, err, pci_using_dac; |
| 4234 | u16 eeprom_data = 0; | 4216 | u16 eeprom_data = 0; |
| 4235 | u16 eeprom_apme_mask = E1000_EEPROM_APME; | 4217 | u16 eeprom_apme_mask = E1000_EEPROM_APME; |
| 4236 | int bars, need_ioport; | ||
| 4237 | 4218 | ||
| 4238 | e1000e_disable_l1aspm(pdev); | 4219 | e1000e_disable_l1aspm(pdev); |
| 4239 | 4220 | ||
| 4240 | /* do not allocate ioport bars when not needed */ | 4221 | err = pci_enable_device_mem(pdev); |
| 4241 | need_ioport = e1000e_is_need_ioport(pdev); | ||
| 4242 | if (need_ioport) { | ||
| 4243 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); | ||
| 4244 | err = pci_enable_device(pdev); | ||
| 4245 | } else { | ||
| 4246 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | ||
| 4247 | err = pci_enable_device_mem(pdev); | ||
| 4248 | } | ||
| 4249 | if (err) | 4222 | if (err) |
| 4250 | return err; | 4223 | return err; |
| 4251 | 4224 | ||
| @@ -4268,7 +4241,9 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4268 | } | 4241 | } |
| 4269 | } | 4242 | } |
| 4270 | 4243 | ||
| 4271 | err = pci_request_selected_regions(pdev, bars, e1000e_driver_name); | 4244 | err = pci_request_selected_regions(pdev, |
| 4245 | pci_select_bars(pdev, IORESOURCE_MEM), | ||
| 4246 | e1000e_driver_name); | ||
| 4272 | if (err) | 4247 | if (err) |
| 4273 | goto err_pci_reg; | 4248 | goto err_pci_reg; |
| 4274 | 4249 | ||
| @@ -4293,8 +4268,6 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4293 | adapter->hw.adapter = adapter; | 4268 | adapter->hw.adapter = adapter; |
| 4294 | adapter->hw.mac.type = ei->mac; | 4269 | adapter->hw.mac.type = ei->mac; |
| 4295 | adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1; | 4270 | adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1; |
| 4296 | adapter->bars = bars; | ||
| 4297 | adapter->need_ioport = need_ioport; | ||
| 4298 | 4271 | ||
| 4299 | mmio_start = pci_resource_start(pdev, 0); | 4272 | mmio_start = pci_resource_start(pdev, 0); |
| 4300 | mmio_len = pci_resource_len(pdev, 0); | 4273 | mmio_len = pci_resource_len(pdev, 0); |
| @@ -4366,8 +4339,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4366 | } | 4339 | } |
| 4367 | 4340 | ||
| 4368 | if (e1000_check_reset_block(&adapter->hw)) | 4341 | if (e1000_check_reset_block(&adapter->hw)) |
| 4369 | ndev_info(netdev, | 4342 | e_info("PHY reset is blocked due to SOL/IDER session.\n"); |
| 4370 | "PHY reset is blocked due to SOL/IDER session.\n"); | ||
| 4371 | 4343 | ||
| 4372 | netdev->features = NETIF_F_SG | | 4344 | netdev->features = NETIF_F_SG | |
| 4373 | NETIF_F_HW_CSUM | | 4345 | NETIF_F_HW_CSUM | |
| @@ -4411,25 +4383,26 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4411 | if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) | 4383 | if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) |
| 4412 | break; | 4384 | break; |
| 4413 | if (i == 2) { | 4385 | if (i == 2) { |
| 4414 | ndev_err(netdev, "The NVM Checksum Is Not Valid\n"); | 4386 | e_err("The NVM Checksum Is Not Valid\n"); |
| 4415 | err = -EIO; | 4387 | err = -EIO; |
| 4416 | goto err_eeprom; | 4388 | goto err_eeprom; |
| 4417 | } | 4389 | } |
| 4418 | } | 4390 | } |
| 4419 | 4391 | ||
| 4392 | e1000_eeprom_checks(adapter); | ||
| 4393 | |||
| 4420 | /* copy the MAC address out of the NVM */ | 4394 | /* copy the MAC address out of the NVM */ |
| 4421 | if (e1000e_read_mac_addr(&adapter->hw)) | 4395 | if (e1000e_read_mac_addr(&adapter->hw)) |
| 4422 | ndev_err(netdev, "NVM Read Error while reading MAC address\n"); | 4396 | e_err("NVM Read Error while reading MAC address\n"); |
| 4423 | 4397 | ||
| 4424 | memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); | 4398 | memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); |
| 4425 | memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); | 4399 | memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); |
| 4426 | 4400 | ||
| 4427 | if (!is_valid_ether_addr(netdev->perm_addr)) { | 4401 | if (!is_valid_ether_addr(netdev->perm_addr)) { |
| 4428 | ndev_err(netdev, "Invalid MAC Address: " | 4402 | e_err("Invalid MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 4429 | "%02x:%02x:%02x:%02x:%02x:%02x\n", | 4403 | netdev->perm_addr[0], netdev->perm_addr[1], |
| 4430 | netdev->perm_addr[0], netdev->perm_addr[1], | 4404 | netdev->perm_addr[2], netdev->perm_addr[3], |
| 4431 | netdev->perm_addr[2], netdev->perm_addr[3], | 4405 | netdev->perm_addr[4], netdev->perm_addr[5]); |
| 4432 | netdev->perm_addr[4], netdev->perm_addr[5]); | ||
| 4433 | err = -EIO; | 4406 | err = -EIO; |
| 4434 | goto err_eeprom; | 4407 | goto err_eeprom; |
| 4435 | } | 4408 | } |
| @@ -4499,8 +4472,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4499 | * is up. For all other cases, let the f/w know that the h/w is now | 4472 | * is up. For all other cases, let the f/w know that the h/w is now |
| 4500 | * under the control of the driver. | 4473 | * under the control of the driver. |
| 4501 | */ | 4474 | */ |
| 4502 | if (!(adapter->flags & FLAG_HAS_AMT) || | 4475 | if (!(adapter->flags & FLAG_HAS_AMT)) |
| 4503 | !e1000e_check_mng_mode(&adapter->hw)) | ||
| 4504 | e1000_get_hw_control(adapter); | 4476 | e1000_get_hw_control(adapter); |
| 4505 | 4477 | ||
| 4506 | /* tell the stack to leave us alone until e1000_open() is called */ | 4478 | /* tell the stack to leave us alone until e1000_open() is called */ |
| @@ -4517,24 +4489,25 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
| 4517 | return 0; | 4489 | return 0; |
| 4518 | 4490 | ||
| 4519 | err_register: | 4491 | err_register: |
| 4520 | err_hw_init: | 4492 | if (!(adapter->flags & FLAG_HAS_AMT)) |
| 4521 | e1000_release_hw_control(adapter); | 4493 | e1000_release_hw_control(adapter); |
| 4522 | err_eeprom: | 4494 | err_eeprom: |
| 4523 | if (!e1000_check_reset_block(&adapter->hw)) | 4495 | if (!e1000_check_reset_block(&adapter->hw)) |
| 4524 | e1000_phy_hw_reset(&adapter->hw); | 4496 | e1000_phy_hw_reset(&adapter->hw); |
| 4497 | err_hw_init: | ||
| 4525 | 4498 | ||
| 4526 | if (adapter->hw.flash_address) | ||
| 4527 | iounmap(adapter->hw.flash_address); | ||
| 4528 | |||
| 4529 | err_flashmap: | ||
| 4530 | kfree(adapter->tx_ring); | 4499 | kfree(adapter->tx_ring); |
| 4531 | kfree(adapter->rx_ring); | 4500 | kfree(adapter->rx_ring); |
| 4532 | err_sw_init: | 4501 | err_sw_init: |
| 4502 | if (adapter->hw.flash_address) | ||
| 4503 | iounmap(adapter->hw.flash_address); | ||
| 4504 | err_flashmap: | ||
| 4533 | iounmap(adapter->hw.hw_addr); | 4505 | iounmap(adapter->hw.hw_addr); |
| 4534 | err_ioremap: | 4506 | err_ioremap: |
| 4535 | free_netdev(netdev); | 4507 | free_netdev(netdev); |
| 4536 | err_alloc_etherdev: | 4508 | err_alloc_etherdev: |
| 4537 | pci_release_selected_regions(pdev, bars); | 4509 | pci_release_selected_regions(pdev, |
| 4510 | pci_select_bars(pdev, IORESOURCE_MEM)); | ||
| 4538 | err_pci_reg: | 4511 | err_pci_reg: |
| 4539 | err_dma: | 4512 | err_dma: |
| 4540 | pci_disable_device(pdev); | 4513 | pci_disable_device(pdev); |
| @@ -4582,7 +4555,8 @@ static void __devexit e1000_remove(struct pci_dev *pdev) | |||
| 4582 | iounmap(adapter->hw.hw_addr); | 4555 | iounmap(adapter->hw.hw_addr); |
| 4583 | if (adapter->hw.flash_address) | 4556 | if (adapter->hw.flash_address) |
| 4584 | iounmap(adapter->hw.flash_address); | 4557 | iounmap(adapter->hw.flash_address); |
| 4585 | pci_release_selected_regions(pdev, adapter->bars); | 4558 | pci_release_selected_regions(pdev, |
| 4559 | pci_select_bars(pdev, IORESOURCE_MEM)); | ||
| 4586 | 4560 | ||
| 4587 | free_netdev(netdev); | 4561 | free_netdev(netdev); |
| 4588 | 4562 | ||
diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c index a66b92efcf80..8effc3107f9a 100644 --- a/drivers/net/e1000e/param.c +++ b/drivers/net/e1000e/param.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | *******************************************************************************/ | 27 | *******************************************************************************/ |
| 28 | 28 | ||
| 29 | #include <linux/netdevice.h> | 29 | #include <linux/netdevice.h> |
| 30 | #include <linux/pci.h> | ||
| 30 | 31 | ||
| 31 | #include "e1000.h" | 32 | #include "e1000.h" |
| 32 | 33 | ||
| @@ -162,17 +163,16 @@ static int __devinit e1000_validate_option(unsigned int *value, | |||
| 162 | case enable_option: | 163 | case enable_option: |
| 163 | switch (*value) { | 164 | switch (*value) { |
| 164 | case OPTION_ENABLED: | 165 | case OPTION_ENABLED: |
| 165 | ndev_info(adapter->netdev, "%s Enabled\n", opt->name); | 166 | e_info("%s Enabled\n", opt->name); |
| 166 | return 0; | 167 | return 0; |
| 167 | case OPTION_DISABLED: | 168 | case OPTION_DISABLED: |
| 168 | ndev_info(adapter->netdev, "%s Disabled\n", opt->name); | 169 | e_info("%s Disabled\n", opt->name); |
| 169 | return 0; | 170 | return 0; |
| 170 | } | 171 | } |
| 171 | break; | 172 | break; |
| 172 | case range_option: | 173 | case range_option: |
| 173 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { | 174 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { |
| 174 | ndev_info(adapter->netdev, | 175 | e_info("%s set to %i\n", opt->name, *value); |
| 175 | "%s set to %i\n", opt->name, *value); | ||
| 176 | return 0; | 176 | return 0; |
| 177 | } | 177 | } |
| 178 | break; | 178 | break; |
| @@ -184,8 +184,7 @@ static int __devinit e1000_validate_option(unsigned int *value, | |||
| 184 | ent = &opt->arg.l.p[i]; | 184 | ent = &opt->arg.l.p[i]; |
| 185 | if (*value == ent->i) { | 185 | if (*value == ent->i) { |
| 186 | if (ent->str[0] != '\0') | 186 | if (ent->str[0] != '\0') |
| 187 | ndev_info(adapter->netdev, "%s\n", | 187 | e_info("%s\n", ent->str); |
| 188 | ent->str); | ||
| 189 | return 0; | 188 | return 0; |
| 190 | } | 189 | } |
| 191 | } | 190 | } |
| @@ -195,8 +194,8 @@ static int __devinit e1000_validate_option(unsigned int *value, | |||
| 195 | BUG(); | 194 | BUG(); |
| 196 | } | 195 | } |
| 197 | 196 | ||
| 198 | ndev_info(adapter->netdev, "Invalid %s value specified (%i) %s\n", | 197 | e_info("Invalid %s value specified (%i) %s\n", opt->name, *value, |
| 199 | opt->name, *value, opt->err); | 198 | opt->err); |
| 200 | *value = opt->def; | 199 | *value = opt->def; |
| 201 | return -1; | 200 | return -1; |
| 202 | } | 201 | } |
| @@ -213,13 +212,11 @@ static int __devinit e1000_validate_option(unsigned int *value, | |||
| 213 | void __devinit e1000e_check_options(struct e1000_adapter *adapter) | 212 | void __devinit e1000e_check_options(struct e1000_adapter *adapter) |
| 214 | { | 213 | { |
| 215 | struct e1000_hw *hw = &adapter->hw; | 214 | struct e1000_hw *hw = &adapter->hw; |
| 216 | struct net_device *netdev = adapter->netdev; | ||
| 217 | int bd = adapter->bd_number; | 215 | int bd = adapter->bd_number; |
| 218 | 216 | ||
| 219 | if (bd >= E1000_MAX_NIC) { | 217 | if (bd >= E1000_MAX_NIC) { |
| 220 | ndev_notice(netdev, | 218 | e_notice("Warning: no configuration for board #%i\n", bd); |
| 221 | "Warning: no configuration for board #%i\n", bd); | 219 | e_notice("Using defaults for all values\n"); |
| 222 | ndev_notice(netdev, "Using defaults for all values\n"); | ||
| 223 | } | 220 | } |
| 224 | 221 | ||
| 225 | { /* Transmit Interrupt Delay */ | 222 | { /* Transmit Interrupt Delay */ |
| @@ -313,19 +310,15 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter) | |||
| 313 | adapter->itr = InterruptThrottleRate[bd]; | 310 | adapter->itr = InterruptThrottleRate[bd]; |
| 314 | switch (adapter->itr) { | 311 | switch (adapter->itr) { |
| 315 | case 0: | 312 | case 0: |
| 316 | ndev_info(netdev, "%s turned off\n", | 313 | e_info("%s turned off\n", opt.name); |
| 317 | opt.name); | ||
| 318 | break; | 314 | break; |
| 319 | case 1: | 315 | case 1: |
| 320 | ndev_info(netdev, | 316 | e_info("%s set to dynamic mode\n", opt.name); |
| 321 | "%s set to dynamic mode\n", | ||
| 322 | opt.name); | ||
| 323 | adapter->itr_setting = adapter->itr; | 317 | adapter->itr_setting = adapter->itr; |
| 324 | adapter->itr = 20000; | 318 | adapter->itr = 20000; |
| 325 | break; | 319 | break; |
| 326 | case 3: | 320 | case 3: |
| 327 | ndev_info(netdev, | 321 | e_info("%s set to dynamic conservative mode\n", |
| 328 | "%s set to dynamic conservative mode\n", | ||
| 329 | opt.name); | 322 | opt.name); |
| 330 | adapter->itr_setting = adapter->itr; | 323 | adapter->itr_setting = adapter->itr; |
| 331 | adapter->itr = 20000; | 324 | adapter->itr = 20000; |
diff --git a/drivers/net/eepro.c b/drivers/net/eepro.c index 56f50491a453..1f11350e16cf 100644 --- a/drivers/net/eepro.c +++ b/drivers/net/eepro.c | |||
| @@ -1283,14 +1283,6 @@ set_multicast_list(struct net_device *dev) | |||
| 1283 | 1283 | ||
| 1284 | if (dev->flags&(IFF_ALLMULTI|IFF_PROMISC) || dev->mc_count > 63) | 1284 | if (dev->flags&(IFF_ALLMULTI|IFF_PROMISC) || dev->mc_count > 63) |
| 1285 | { | 1285 | { |
| 1286 | /* | ||
| 1287 | * We must make the kernel realise we had to move | ||
| 1288 | * into promisc mode or we start all out war on | ||
| 1289 | * the cable. If it was a promisc request the | ||
| 1290 | * flag is already set. If not we assert it. | ||
| 1291 | */ | ||
| 1292 | dev->flags|=IFF_PROMISC; | ||
| 1293 | |||
| 1294 | eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */ | 1286 | eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */ |
| 1295 | mode = inb(ioaddr + REG2); | 1287 | mode = inb(ioaddr + REG2); |
| 1296 | outb(mode | PRMSC_Mode, ioaddr + REG2); | 1288 | outb(mode | PRMSC_Mode, ioaddr + REG2); |
diff --git a/drivers/net/eth16i.c b/drivers/net/eth16i.c index e3dd8b136908..bee8b3fbc565 100644 --- a/drivers/net/eth16i.c +++ b/drivers/net/eth16i.c | |||
| @@ -1356,7 +1356,6 @@ static void eth16i_multicast(struct net_device *dev) | |||
| 1356 | 1356 | ||
| 1357 | if(dev->mc_count || dev->flags&(IFF_ALLMULTI|IFF_PROMISC)) | 1357 | if(dev->mc_count || dev->flags&(IFF_ALLMULTI|IFF_PROMISC)) |
| 1358 | { | 1358 | { |
| 1359 | dev->flags|=IFF_PROMISC; /* Must do this */ | ||
| 1360 | outb(3, ioaddr + RECEIVE_MODE_REG); | 1359 | outb(3, ioaddr + RECEIVE_MODE_REG); |
| 1361 | } else { | 1360 | } else { |
| 1362 | outb(2, ioaddr + RECEIVE_MODE_REG); | 1361 | outb(2, ioaddr + RECEIVE_MODE_REG); |
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 01b38b092c76..053971e5fc94 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
| @@ -77,26 +77,27 @@ | |||
| 77 | * Hardware access: | 77 | * Hardware access: |
| 78 | */ | 78 | */ |
| 79 | 79 | ||
| 80 | #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */ | 80 | #define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */ |
| 81 | #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */ | 81 | #define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */ |
| 82 | #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */ | 82 | #define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */ |
| 83 | #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */ | 83 | #define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */ |
| 84 | #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */ | 84 | #define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */ |
| 85 | #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */ | 85 | #define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */ |
| 86 | #define DEV_HAS_MSI 0x00040 /* device supports MSI */ | 86 | #define DEV_HAS_MSI 0x000040 /* device supports MSI */ |
| 87 | #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */ | 87 | #define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */ |
| 88 | #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */ | 88 | #define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */ |
| 89 | #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */ | 89 | #define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */ |
| 90 | #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */ | 90 | #define DEV_HAS_STATISTICS_V2 0x000400 /* device supports hw statistics version 2 */ |
| 91 | #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */ | 91 | #define DEV_HAS_STATISTICS_V3 0x000800 /* device supports hw statistics version 3 */ |
| 92 | #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */ | 92 | #define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */ |
| 93 | #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */ | 93 | #define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */ |
| 94 | #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */ | 94 | #define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */ |
| 95 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */ | 95 | #define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */ |
| 96 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */ | 96 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */ |
| 97 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */ | 97 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */ |
| 98 | #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */ | 98 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */ |
| 99 | #define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */ | 99 | #define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */ |
| 100 | #define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */ | ||
| 100 | 101 | ||
| 101 | enum { | 102 | enum { |
| 102 | NvRegIrqStatus = 0x000, | 103 | NvRegIrqStatus = 0x000, |
| @@ -248,6 +249,8 @@ enum { | |||
| 248 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | 249 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 |
| 249 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | 250 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 |
| 250 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | 251 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 |
| 252 | NvRegTxPauseFrameLimit = 0x174, | ||
| 253 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | ||
| 251 | NvRegMIIStatus = 0x180, | 254 | NvRegMIIStatus = 0x180, |
| 252 | #define NVREG_MIISTAT_ERROR 0x0001 | 255 | #define NVREG_MIISTAT_ERROR 0x0001 |
| 253 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | 256 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 |
| @@ -270,6 +273,9 @@ enum { | |||
| 270 | #define NVREG_MIICTL_WRITE 0x00400 | 273 | #define NVREG_MIICTL_WRITE 0x00400 |
| 271 | #define NVREG_MIICTL_ADDRSHIFT 5 | 274 | #define NVREG_MIICTL_ADDRSHIFT 5 |
| 272 | NvRegMIIData = 0x194, | 275 | NvRegMIIData = 0x194, |
| 276 | NvRegTxUnicast = 0x1a0, | ||
| 277 | NvRegTxMulticast = 0x1a4, | ||
| 278 | NvRegTxBroadcast = 0x1a8, | ||
| 273 | NvRegWakeUpFlags = 0x200, | 279 | NvRegWakeUpFlags = 0x200, |
| 274 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | 280 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 |
| 275 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | 281 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 |
| @@ -402,6 +408,7 @@ union ring_type { | |||
| 402 | #define NV_RX_FRAMINGERR (1<<29) | 408 | #define NV_RX_FRAMINGERR (1<<29) |
| 403 | #define NV_RX_ERROR (1<<30) | 409 | #define NV_RX_ERROR (1<<30) |
| 404 | #define NV_RX_AVAIL (1<<31) | 410 | #define NV_RX_AVAIL (1<<31) |
| 411 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) | ||
| 405 | 412 | ||
| 406 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | 413 | #define NV_RX2_CHECKSUMMASK (0x1C000000) |
| 407 | #define NV_RX2_CHECKSUM_IP (0x10000000) | 414 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
| @@ -419,6 +426,7 @@ union ring_type { | |||
| 419 | /* error and avail are the same for both */ | 426 | /* error and avail are the same for both */ |
| 420 | #define NV_RX2_ERROR (1<<30) | 427 | #define NV_RX2_ERROR (1<<30) |
| 421 | #define NV_RX2_AVAIL (1<<31) | 428 | #define NV_RX2_AVAIL (1<<31) |
| 429 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) | ||
| 422 | 430 | ||
| 423 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) | 431 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
| 424 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | 432 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) |
| @@ -616,7 +624,12 @@ static const struct nv_ethtool_str nv_estats_str[] = { | |||
| 616 | { "rx_bytes" }, | 624 | { "rx_bytes" }, |
| 617 | { "tx_pause" }, | 625 | { "tx_pause" }, |
| 618 | { "rx_pause" }, | 626 | { "rx_pause" }, |
| 619 | { "rx_drop_frame" } | 627 | { "rx_drop_frame" }, |
| 628 | |||
| 629 | /* version 3 stats */ | ||
| 630 | { "tx_unicast" }, | ||
| 631 | { "tx_multicast" }, | ||
| 632 | { "tx_broadcast" } | ||
| 620 | }; | 633 | }; |
| 621 | 634 | ||
| 622 | struct nv_ethtool_stats { | 635 | struct nv_ethtool_stats { |
| @@ -652,9 +665,15 @@ struct nv_ethtool_stats { | |||
| 652 | u64 tx_pause; | 665 | u64 tx_pause; |
| 653 | u64 rx_pause; | 666 | u64 rx_pause; |
| 654 | u64 rx_drop_frame; | 667 | u64 rx_drop_frame; |
| 668 | |||
| 669 | /* version 3 stats */ | ||
| 670 | u64 tx_unicast; | ||
| 671 | u64 tx_multicast; | ||
| 672 | u64 tx_broadcast; | ||
| 655 | }; | 673 | }; |
| 656 | 674 | ||
| 657 | #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) | 675 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
| 676 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | ||
| 658 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) | 677 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
| 659 | 678 | ||
| 660 | /* diagnostics */ | 679 | /* diagnostics */ |
| @@ -1628,6 +1647,12 @@ static void nv_get_hw_stats(struct net_device *dev) | |||
| 1628 | np->estats.rx_pause += readl(base + NvRegRxPause); | 1647 | np->estats.rx_pause += readl(base + NvRegRxPause); |
| 1629 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | 1648 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); |
| 1630 | } | 1649 | } |
| 1650 | |||
| 1651 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | ||
| 1652 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | ||
| 1653 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | ||
| 1654 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | ||
| 1655 | } | ||
| 1631 | } | 1656 | } |
| 1632 | 1657 | ||
| 1633 | /* | 1658 | /* |
| @@ -1641,7 +1666,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev) | |||
| 1641 | struct fe_priv *np = netdev_priv(dev); | 1666 | struct fe_priv *np = netdev_priv(dev); |
| 1642 | 1667 | ||
| 1643 | /* If the nic supports hw counters then retrieve latest values */ | 1668 | /* If the nic supports hw counters then retrieve latest values */ |
| 1644 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) { | 1669 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) { |
| 1645 | nv_get_hw_stats(dev); | 1670 | nv_get_hw_stats(dev); |
| 1646 | 1671 | ||
| 1647 | /* copy to net_device stats */ | 1672 | /* copy to net_device stats */ |
| @@ -2632,7 +2657,7 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
| 2632 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { | 2657 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
| 2633 | len = flags & LEN_MASK_V1; | 2658 | len = flags & LEN_MASK_V1; |
| 2634 | if (unlikely(flags & NV_RX_ERROR)) { | 2659 | if (unlikely(flags & NV_RX_ERROR)) { |
| 2635 | if (flags & NV_RX_ERROR4) { | 2660 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
| 2636 | len = nv_getlen(dev, skb->data, len); | 2661 | len = nv_getlen(dev, skb->data, len); |
| 2637 | if (len < 0) { | 2662 | if (len < 0) { |
| 2638 | dev->stats.rx_errors++; | 2663 | dev->stats.rx_errors++; |
| @@ -2641,7 +2666,7 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
| 2641 | } | 2666 | } |
| 2642 | } | 2667 | } |
| 2643 | /* framing errors are soft errors */ | 2668 | /* framing errors are soft errors */ |
| 2644 | else if (flags & NV_RX_FRAMINGERR) { | 2669 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
| 2645 | if (flags & NV_RX_SUBSTRACT1) { | 2670 | if (flags & NV_RX_SUBSTRACT1) { |
| 2646 | len--; | 2671 | len--; |
| 2647 | } | 2672 | } |
| @@ -2667,7 +2692,7 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
| 2667 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | 2692 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
| 2668 | len = flags & LEN_MASK_V2; | 2693 | len = flags & LEN_MASK_V2; |
| 2669 | if (unlikely(flags & NV_RX2_ERROR)) { | 2694 | if (unlikely(flags & NV_RX2_ERROR)) { |
| 2670 | if (flags & NV_RX2_ERROR4) { | 2695 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
| 2671 | len = nv_getlen(dev, skb->data, len); | 2696 | len = nv_getlen(dev, skb->data, len); |
| 2672 | if (len < 0) { | 2697 | if (len < 0) { |
| 2673 | dev->stats.rx_errors++; | 2698 | dev->stats.rx_errors++; |
| @@ -2676,7 +2701,7 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
| 2676 | } | 2701 | } |
| 2677 | } | 2702 | } |
| 2678 | /* framing errors are soft errors */ | 2703 | /* framing errors are soft errors */ |
| 2679 | else if (flags & NV_RX2_FRAMINGERR) { | 2704 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
| 2680 | if (flags & NV_RX2_SUBSTRACT1) { | 2705 | if (flags & NV_RX2_SUBSTRACT1) { |
| 2681 | len--; | 2706 | len--; |
| 2682 | } | 2707 | } |
| @@ -2766,7 +2791,7 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit) | |||
| 2766 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | 2791 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
| 2767 | len = flags & LEN_MASK_V2; | 2792 | len = flags & LEN_MASK_V2; |
| 2768 | if (unlikely(flags & NV_RX2_ERROR)) { | 2793 | if (unlikely(flags & NV_RX2_ERROR)) { |
| 2769 | if (flags & NV_RX2_ERROR4) { | 2794 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
| 2770 | len = nv_getlen(dev, skb->data, len); | 2795 | len = nv_getlen(dev, skb->data, len); |
| 2771 | if (len < 0) { | 2796 | if (len < 0) { |
| 2772 | dev_kfree_skb(skb); | 2797 | dev_kfree_skb(skb); |
| @@ -2774,7 +2799,7 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit) | |||
| 2774 | } | 2799 | } |
| 2775 | } | 2800 | } |
| 2776 | /* framing errors are soft errors */ | 2801 | /* framing errors are soft errors */ |
| 2777 | else if (flags & NV_RX2_FRAMINGERR) { | 2802 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
| 2778 | if (flags & NV_RX2_SUBSTRACT1) { | 2803 | if (flags & NV_RX2_SUBSTRACT1) { |
| 2779 | len--; | 2804 | len--; |
| 2780 | } | 2805 | } |
| @@ -3053,8 +3078,11 @@ static void nv_update_pause(struct net_device *dev, u32 pause_flags) | |||
| 3053 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; | 3078 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
| 3054 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | 3079 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) |
| 3055 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | 3080 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; |
| 3056 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) | 3081 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
| 3057 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; | 3082 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
| 3083 | /* limit the number of tx pause frames to a default of 8 */ | ||
| 3084 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | ||
| 3085 | } | ||
| 3058 | writel(pause_enable, base + NvRegTxPauseFrame); | 3086 | writel(pause_enable, base + NvRegTxPauseFrame); |
| 3059 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); | 3087 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
| 3060 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | 3088 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
| @@ -4740,6 +4768,8 @@ static int nv_get_sset_count(struct net_device *dev, int sset) | |||
| 4740 | return NV_DEV_STATISTICS_V1_COUNT; | 4768 | return NV_DEV_STATISTICS_V1_COUNT; |
| 4741 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) | 4769 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) |
| 4742 | return NV_DEV_STATISTICS_V2_COUNT; | 4770 | return NV_DEV_STATISTICS_V2_COUNT; |
| 4771 | else if (np->driver_data & DEV_HAS_STATISTICS_V3) | ||
| 4772 | return NV_DEV_STATISTICS_V3_COUNT; | ||
| 4743 | else | 4773 | else |
| 4744 | return 0; | 4774 | return 0; |
| 4745 | default: | 4775 | default: |
| @@ -5324,7 +5354,7 @@ static int nv_open(struct net_device *dev) | |||
| 5324 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | 5354 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
| 5325 | 5355 | ||
| 5326 | /* start statistics timer */ | 5356 | /* start statistics timer */ |
| 5327 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) | 5357 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
| 5328 | mod_timer(&np->stats_poll, | 5358 | mod_timer(&np->stats_poll, |
| 5329 | round_jiffies(jiffies + STATS_INTERVAL)); | 5359 | round_jiffies(jiffies + STATS_INTERVAL)); |
| 5330 | 5360 | ||
| @@ -5428,7 +5458,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
| 5428 | if (err < 0) | 5458 | if (err < 0) |
| 5429 | goto out_disable; | 5459 | goto out_disable; |
| 5430 | 5460 | ||
| 5431 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2)) | 5461 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
| 5432 | np->register_size = NV_PCI_REGSZ_VER3; | 5462 | np->register_size = NV_PCI_REGSZ_VER3; |
| 5433 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | 5463 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) |
| 5434 | np->register_size = NV_PCI_REGSZ_VER2; | 5464 | np->register_size = NV_PCI_REGSZ_VER2; |
| @@ -6083,35 +6113,35 @@ static struct pci_device_id pci_tbl[] = { | |||
| 6083 | }, | 6113 | }, |
| 6084 | { /* MCP77 Ethernet Controller */ | 6114 | { /* MCP77 Ethernet Controller */ |
| 6085 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), | 6115 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), |
| 6086 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6116 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6087 | }, | 6117 | }, |
| 6088 | { /* MCP77 Ethernet Controller */ | 6118 | { /* MCP77 Ethernet Controller */ |
| 6089 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), | 6119 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), |
| 6090 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6120 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6091 | }, | 6121 | }, |
| 6092 | { /* MCP77 Ethernet Controller */ | 6122 | { /* MCP77 Ethernet Controller */ |
| 6093 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), | 6123 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), |
| 6094 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6124 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6095 | }, | 6125 | }, |
| 6096 | { /* MCP77 Ethernet Controller */ | 6126 | { /* MCP77 Ethernet Controller */ |
| 6097 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), | 6127 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), |
| 6098 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6128 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6099 | }, | 6129 | }, |
| 6100 | { /* MCP79 Ethernet Controller */ | 6130 | { /* MCP79 Ethernet Controller */ |
| 6101 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), | 6131 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), |
| 6102 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6132 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6103 | }, | 6133 | }, |
| 6104 | { /* MCP79 Ethernet Controller */ | 6134 | { /* MCP79 Ethernet Controller */ |
| 6105 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), | 6135 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), |
| 6106 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6136 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6107 | }, | 6137 | }, |
| 6108 | { /* MCP79 Ethernet Controller */ | 6138 | { /* MCP79 Ethernet Controller */ |
| 6109 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), | 6139 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), |
| 6110 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6140 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6111 | }, | 6141 | }, |
| 6112 | { /* MCP79 Ethernet Controller */ | 6142 | { /* MCP79 Ethernet Controller */ |
| 6113 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), | 6143 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), |
| 6114 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6144 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6115 | }, | 6145 | }, |
| 6116 | {0,}, | 6146 | {0,}, |
| 6117 | }; | 6147 | }; |
diff --git a/drivers/net/fs_enet/mac-fcc.c b/drivers/net/fs_enet/mac-fcc.c index 0a97fc2d97ec..1c7ef812a8e3 100644 --- a/drivers/net/fs_enet/mac-fcc.c +++ b/drivers/net/fs_enet/mac-fcc.c | |||
| @@ -126,7 +126,7 @@ out: | |||
| 126 | #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB) | 126 | #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB) |
| 127 | #define FCC_RX_EVENT (FCC_ENET_RXF) | 127 | #define FCC_RX_EVENT (FCC_ENET_RXF) |
| 128 | #define FCC_TX_EVENT (FCC_ENET_TXB) | 128 | #define FCC_TX_EVENT (FCC_ENET_TXB) |
| 129 | #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY) | 129 | #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE) |
| 130 | 130 | ||
| 131 | static int setup_data(struct net_device *dev) | 131 | static int setup_data(struct net_device *dev) |
| 132 | { | 132 | { |
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index b8394cf134e8..ca6cf6ecb37b 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c | |||
| @@ -414,9 +414,7 @@ static int gfar_suspend(struct platform_device *pdev, pm_message_t state) | |||
| 414 | spin_unlock(&priv->rxlock); | 414 | spin_unlock(&priv->rxlock); |
| 415 | spin_unlock_irqrestore(&priv->txlock, flags); | 415 | spin_unlock_irqrestore(&priv->txlock, flags); |
| 416 | 416 | ||
| 417 | #ifdef CONFIG_GFAR_NAPI | ||
| 418 | napi_disable(&priv->napi); | 417 | napi_disable(&priv->napi); |
| 419 | #endif | ||
| 420 | 418 | ||
| 421 | if (magic_packet) { | 419 | if (magic_packet) { |
| 422 | /* Enable interrupt on Magic Packet */ | 420 | /* Enable interrupt on Magic Packet */ |
| @@ -469,9 +467,7 @@ static int gfar_resume(struct platform_device *pdev) | |||
| 469 | 467 | ||
| 470 | netif_device_attach(dev); | 468 | netif_device_attach(dev); |
| 471 | 469 | ||
| 472 | #ifdef CONFIG_GFAR_NAPI | ||
| 473 | napi_enable(&priv->napi); | 470 | napi_enable(&priv->napi); |
| 474 | #endif | ||
| 475 | 471 | ||
| 476 | return 0; | 472 | return 0; |
| 477 | } | 473 | } |
diff --git a/drivers/net/hamradio/mkiss.c b/drivers/net/hamradio/mkiss.c index 3249df5e0f17..b8e25c4624d2 100644 --- a/drivers/net/hamradio/mkiss.c +++ b/drivers/net/hamradio/mkiss.c | |||
| @@ -548,7 +548,7 @@ static int ax_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 548 | } | 548 | } |
| 549 | 549 | ||
| 550 | printk(KERN_ERR "mkiss: %s: transmit timed out, %s?\n", dev->name, | 550 | printk(KERN_ERR "mkiss: %s: transmit timed out, %s?\n", dev->name, |
| 551 | (ax->tty->ops->chars_in_buffer(ax->tty) || ax->xleft) ? | 551 | (tty_chars_in_buffer(ax->tty) || ax->xleft) ? |
| 552 | "bad line quality" : "driver error"); | 552 | "bad line quality" : "driver error"); |
| 553 | 553 | ||
| 554 | ax->xleft = 0; | 554 | ax->xleft = 0; |
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c index e098f234770f..bb823acc7443 100644 --- a/drivers/net/igb/e1000_82575.c +++ b/drivers/net/igb/e1000_82575.c | |||
| @@ -850,7 +850,7 @@ void igb_update_mc_addr_list_82575(struct e1000_hw *hw, | |||
| 850 | for (; mc_addr_count > 0; mc_addr_count--) { | 850 | for (; mc_addr_count > 0; mc_addr_count--) { |
| 851 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); | 851 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); |
| 852 | hw_dbg("Hash value = 0x%03X\n", hash_value); | 852 | hw_dbg("Hash value = 0x%03X\n", hash_value); |
| 853 | hw->mac.ops.mta_set(hw, hash_value); | 853 | igb_mta_set(hw, hash_value); |
| 854 | mc_addr_list += ETH_ALEN; | 854 | mc_addr_list += ETH_ALEN; |
| 855 | } | 855 | } |
| 856 | } | 856 | } |
| @@ -1136,6 +1136,12 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw) | |||
| 1136 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ | 1136 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ |
| 1137 | hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); | 1137 | hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); |
| 1138 | } | 1138 | } |
| 1139 | |||
| 1140 | if (hw->mac.type == e1000_82576) { | ||
| 1141 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | ||
| 1142 | igb_force_mac_fc(hw); | ||
| 1143 | } | ||
| 1144 | |||
| 1139 | wr32(E1000_PCS_LCTL, reg); | 1145 | wr32(E1000_PCS_LCTL, reg); |
| 1140 | 1146 | ||
| 1141 | return 0; | 1147 | return 0; |
| @@ -1232,70 +1238,6 @@ out: | |||
| 1232 | } | 1238 | } |
| 1233 | 1239 | ||
| 1234 | /** | 1240 | /** |
| 1235 | * igb_translate_register_82576 - Translate the proper register offset | ||
| 1236 | * @reg: e1000 register to be read | ||
| 1237 | * | ||
| 1238 | * Registers in 82576 are located in different offsets than other adapters | ||
| 1239 | * even though they function in the same manner. This function takes in | ||
| 1240 | * the name of the register to read and returns the correct offset for | ||
| 1241 | * 82576 silicon. | ||
| 1242 | **/ | ||
| 1243 | u32 igb_translate_register_82576(u32 reg) | ||
| 1244 | { | ||
| 1245 | /* | ||
| 1246 | * Some of the Kawela registers are located at different | ||
| 1247 | * offsets than they are in older adapters. | ||
| 1248 | * Despite the difference in location, the registers | ||
| 1249 | * function in the same manner. | ||
| 1250 | */ | ||
| 1251 | switch (reg) { | ||
| 1252 | case E1000_TDBAL(0): | ||
| 1253 | reg = 0x0E000; | ||
| 1254 | break; | ||
| 1255 | case E1000_TDBAH(0): | ||
| 1256 | reg = 0x0E004; | ||
| 1257 | break; | ||
| 1258 | case E1000_TDLEN(0): | ||
| 1259 | reg = 0x0E008; | ||
| 1260 | break; | ||
| 1261 | case E1000_TDH(0): | ||
| 1262 | reg = 0x0E010; | ||
| 1263 | break; | ||
| 1264 | case E1000_TDT(0): | ||
| 1265 | reg = 0x0E018; | ||
| 1266 | break; | ||
| 1267 | case E1000_TXDCTL(0): | ||
| 1268 | reg = 0x0E028; | ||
| 1269 | break; | ||
| 1270 | case E1000_RDBAL(0): | ||
| 1271 | reg = 0x0C000; | ||
| 1272 | break; | ||
| 1273 | case E1000_RDBAH(0): | ||
| 1274 | reg = 0x0C004; | ||
| 1275 | break; | ||
| 1276 | case E1000_RDLEN(0): | ||
| 1277 | reg = 0x0C008; | ||
| 1278 | break; | ||
| 1279 | case E1000_RDH(0): | ||
| 1280 | reg = 0x0C010; | ||
| 1281 | break; | ||
| 1282 | case E1000_RDT(0): | ||
| 1283 | reg = 0x0C018; | ||
| 1284 | break; | ||
| 1285 | case E1000_RXDCTL(0): | ||
| 1286 | reg = 0x0C028; | ||
| 1287 | break; | ||
| 1288 | case E1000_SRRCTL(0): | ||
| 1289 | reg = 0x0C00C; | ||
| 1290 | break; | ||
| 1291 | default: | ||
| 1292 | break; | ||
| 1293 | } | ||
| 1294 | |||
| 1295 | return reg; | ||
| 1296 | } | ||
| 1297 | |||
| 1298 | /** | ||
| 1299 | * igb_reset_init_script_82575 - Inits HW defaults after reset | 1241 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
| 1300 | * @hw: pointer to the HW structure | 1242 | * @hw: pointer to the HW structure |
| 1301 | * | 1243 | * |
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h index 2f848e578a24..c1928b5efe1f 100644 --- a/drivers/net/igb/e1000_82575.h +++ b/drivers/net/igb/e1000_82575.h | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #ifndef _E1000_82575_H_ | 28 | #ifndef _E1000_82575_H_ |
| 29 | #define _E1000_82575_H_ | 29 | #define _E1000_82575_H_ |
| 30 | 30 | ||
| 31 | u32 igb_translate_register_82576(u32 reg); | ||
| 32 | void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32); | 31 | void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32); |
| 33 | extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); | 32 | extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); |
| 34 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); | 33 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); |
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index afdba3c9073c..ce700689fb57 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h | |||
| @@ -257,6 +257,7 @@ | |||
| 257 | #define E1000_PCS_LCTL_FDV_FULL 8 | 257 | #define E1000_PCS_LCTL_FDV_FULL 8 |
| 258 | #define E1000_PCS_LCTL_FSD 0x10 | 258 | #define E1000_PCS_LCTL_FSD 0x10 |
| 259 | #define E1000_PCS_LCTL_FORCE_LINK 0x20 | 259 | #define E1000_PCS_LCTL_FORCE_LINK 0x20 |
| 260 | #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 | ||
| 260 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 | 261 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 |
| 261 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 | 262 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 |
| 262 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 | 263 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 |
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h index 19fa4ee96f2e..a65ccc3095c3 100644 --- a/drivers/net/igb/e1000_hw.h +++ b/drivers/net/igb/e1000_hw.h | |||
| @@ -420,7 +420,6 @@ struct e1000_mac_operations { | |||
| 420 | void (*rar_set)(struct e1000_hw *, u8 *, u32); | 420 | void (*rar_set)(struct e1000_hw *, u8 *, u32); |
| 421 | s32 (*read_mac_addr)(struct e1000_hw *); | 421 | s32 (*read_mac_addr)(struct e1000_hw *); |
| 422 | s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); | 422 | s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); |
| 423 | void (*mta_set)(struct e1000_hw *, u32); | ||
| 424 | }; | 423 | }; |
| 425 | 424 | ||
| 426 | struct e1000_phy_operations { | 425 | struct e1000_phy_operations { |
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c index 20408aa1f916..e18747c70bec 100644 --- a/drivers/net/igb/e1000_mac.c +++ b/drivers/net/igb/e1000_mac.c | |||
| @@ -144,34 +144,6 @@ void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) | |||
| 144 | } | 144 | } |
| 145 | 145 | ||
| 146 | /** | 146 | /** |
| 147 | * igb_init_rx_addrs - Initialize receive address's | ||
| 148 | * @hw: pointer to the HW structure | ||
| 149 | * @rar_count: receive address registers | ||
| 150 | * | ||
| 151 | * Setups the receive address registers by setting the base receive address | ||
| 152 | * register to the devices MAC address and clearing all the other receive | ||
| 153 | * address registers to 0. | ||
| 154 | **/ | ||
| 155 | void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) | ||
| 156 | { | ||
| 157 | u32 i; | ||
| 158 | |||
| 159 | /* Setup the receive address */ | ||
| 160 | hw_dbg("Programming MAC Address into RAR[0]\n"); | ||
| 161 | |||
| 162 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); | ||
| 163 | |||
| 164 | /* Zero out the other (rar_entry_count - 1) receive addresses */ | ||
| 165 | hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); | ||
| 166 | for (i = 1; i < rar_count; i++) { | ||
| 167 | array_wr32(E1000_RA, (i << 1), 0); | ||
| 168 | wrfl(); | ||
| 169 | array_wr32(E1000_RA, ((i << 1) + 1), 0); | ||
| 170 | wrfl(); | ||
| 171 | } | ||
| 172 | } | ||
| 173 | |||
| 174 | /** | ||
| 175 | * igb_check_alt_mac_addr - Check for alternate MAC addr | 147 | * igb_check_alt_mac_addr - Check for alternate MAC addr |
| 176 | * @hw: pointer to the HW structure | 148 | * @hw: pointer to the HW structure |
| 177 | * | 149 | * |
| @@ -271,7 +243,7 @@ void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) | |||
| 271 | * current value is read, the new bit is OR'd in and the new value is | 243 | * current value is read, the new bit is OR'd in and the new value is |
| 272 | * written back into the register. | 244 | * written back into the register. |
| 273 | **/ | 245 | **/ |
| 274 | static void igb_mta_set(struct e1000_hw *hw, u32 hash_value) | 246 | void igb_mta_set(struct e1000_hw *hw, u32 hash_value) |
| 275 | { | 247 | { |
| 276 | u32 hash_bit, hash_reg, mta; | 248 | u32 hash_bit, hash_reg, mta; |
| 277 | 249 | ||
| @@ -297,60 +269,6 @@ static void igb_mta_set(struct e1000_hw *hw, u32 hash_value) | |||
| 297 | } | 269 | } |
| 298 | 270 | ||
| 299 | /** | 271 | /** |
| 300 | * igb_update_mc_addr_list - Update Multicast addresses | ||
| 301 | * @hw: pointer to the HW structure | ||
| 302 | * @mc_addr_list: array of multicast addresses to program | ||
| 303 | * @mc_addr_count: number of multicast addresses to program | ||
| 304 | * @rar_used_count: the first RAR register free to program | ||
| 305 | * @rar_count: total number of supported Receive Address Registers | ||
| 306 | * | ||
| 307 | * Updates the Receive Address Registers and Multicast Table Array. | ||
| 308 | * The caller must have a packed mc_addr_list of multicast addresses. | ||
| 309 | * The parameter rar_count will usually be hw->mac.rar_entry_count | ||
| 310 | * unless there are workarounds that change this. | ||
| 311 | **/ | ||
| 312 | void igb_update_mc_addr_list(struct e1000_hw *hw, | ||
| 313 | u8 *mc_addr_list, u32 mc_addr_count, | ||
| 314 | u32 rar_used_count, u32 rar_count) | ||
| 315 | { | ||
| 316 | u32 hash_value; | ||
| 317 | u32 i; | ||
| 318 | |||
| 319 | /* | ||
| 320 | * Load the first set of multicast addresses into the exact | ||
| 321 | * filters (RAR). If there are not enough to fill the RAR | ||
| 322 | * array, clear the filters. | ||
| 323 | */ | ||
| 324 | for (i = rar_used_count; i < rar_count; i++) { | ||
| 325 | if (mc_addr_count) { | ||
| 326 | hw->mac.ops.rar_set(hw, mc_addr_list, i); | ||
| 327 | mc_addr_count--; | ||
| 328 | mc_addr_list += ETH_ALEN; | ||
| 329 | } else { | ||
| 330 | array_wr32(E1000_RA, i << 1, 0); | ||
| 331 | wrfl(); | ||
| 332 | array_wr32(E1000_RA, (i << 1) + 1, 0); | ||
| 333 | wrfl(); | ||
| 334 | } | ||
| 335 | } | ||
| 336 | |||
| 337 | /* Clear the old settings from the MTA */ | ||
| 338 | hw_dbg("Clearing MTA\n"); | ||
| 339 | for (i = 0; i < hw->mac.mta_reg_count; i++) { | ||
| 340 | array_wr32(E1000_MTA, i, 0); | ||
| 341 | wrfl(); | ||
| 342 | } | ||
| 343 | |||
| 344 | /* Load any remaining multicast addresses into the hash table. */ | ||
| 345 | for (; mc_addr_count > 0; mc_addr_count--) { | ||
| 346 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); | ||
| 347 | hw_dbg("Hash value = 0x%03X\n", hash_value); | ||
| 348 | igb_mta_set(hw, hash_value); | ||
| 349 | mc_addr_list += ETH_ALEN; | ||
| 350 | } | ||
| 351 | } | ||
| 352 | |||
| 353 | /** | ||
| 354 | * igb_hash_mc_addr - Generate a multicast hash value | 272 | * igb_hash_mc_addr - Generate a multicast hash value |
| 355 | * @hw: pointer to the HW structure | 273 | * @hw: pointer to the HW structure |
| 356 | * @mc_addr: pointer to a multicast address | 274 | * @mc_addr: pointer to a multicast address |
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h index dc2f8cce15e7..cbee6af7d912 100644 --- a/drivers/net/igb/e1000_mac.h +++ b/drivers/net/igb/e1000_mac.h | |||
| @@ -51,9 +51,6 @@ s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, | |||
| 51 | u16 *duplex); | 51 | u16 *duplex); |
| 52 | s32 igb_id_led_init(struct e1000_hw *hw); | 52 | s32 igb_id_led_init(struct e1000_hw *hw); |
| 53 | s32 igb_led_off(struct e1000_hw *hw); | 53 | s32 igb_led_off(struct e1000_hw *hw); |
| 54 | void igb_update_mc_addr_list(struct e1000_hw *hw, | ||
| 55 | u8 *mc_addr_list, u32 mc_addr_count, | ||
| 56 | u32 rar_used_count, u32 rar_count); | ||
| 57 | s32 igb_setup_link(struct e1000_hw *hw); | 54 | s32 igb_setup_link(struct e1000_hw *hw); |
| 58 | s32 igb_validate_mdi_setting(struct e1000_hw *hw); | 55 | s32 igb_validate_mdi_setting(struct e1000_hw *hw); |
| 59 | s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, | 56 | s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, |
| @@ -62,7 +59,7 @@ s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, | |||
| 62 | void igb_clear_hw_cntrs_base(struct e1000_hw *hw); | 59 | void igb_clear_hw_cntrs_base(struct e1000_hw *hw); |
| 63 | void igb_clear_vfta(struct e1000_hw *hw); | 60 | void igb_clear_vfta(struct e1000_hw *hw); |
| 64 | void igb_config_collision_dist(struct e1000_hw *hw); | 61 | void igb_config_collision_dist(struct e1000_hw *hw); |
| 65 | void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); | 62 | void igb_mta_set(struct e1000_hw *hw, u32 hash_value); |
| 66 | void igb_put_hw_semaphore(struct e1000_hw *hw); | 63 | void igb_put_hw_semaphore(struct e1000_hw *hw); |
| 67 | void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); | 64 | void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); |
| 68 | s32 igb_check_alt_mac_addr(struct e1000_hw *hw); | 65 | s32 igb_check_alt_mac_addr(struct e1000_hw *hw); |
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h index b95093d24c09..95523af26056 100644 --- a/drivers/net/igb/e1000_regs.h +++ b/drivers/net/igb/e1000_regs.h | |||
| @@ -262,9 +262,6 @@ | |||
| 262 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) | 262 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) |
| 263 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ | 263 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ |
| 264 | 264 | ||
| 265 | #define E1000_REGISTER(a, reg) (((a)->mac.type < e1000_82576) \ | ||
| 266 | ? reg : e1000_translate_register_82576(reg)) | ||
| 267 | |||
| 268 | #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) | 265 | #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) |
| 269 | #define rd32(reg) (readl(hw->hw_addr + reg)) | 266 | #define rd32(reg) (readl(hw->hw_addr + reg)) |
| 270 | #define wrfl() ((void)rd32(E1000_STATUS)) | 267 | #define wrfl() ((void)rd32(E1000_STATUS)) |
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index b602c4dd0d14..8f66e15ec8d6 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
| @@ -311,7 +311,7 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
| 311 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | 311 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
| 312 | break; | 312 | break; |
| 313 | case e1000_82576: | 313 | case e1000_82576: |
| 314 | /* Kawela uses a table-based method for assigning vectors. | 314 | /* The 82576 uses a table-based method for assigning vectors. |
| 315 | Each queue has a single entry in the table to which we write | 315 | Each queue has a single entry in the table to which we write |
| 316 | a vector number along with a "valid" bit. Sadly, the layout | 316 | a vector number along with a "valid" bit. Sadly, the layout |
| 317 | of the table is somewhat counterintuitive. */ | 317 | of the table is somewhat counterintuitive. */ |
| @@ -720,28 +720,6 @@ static void igb_get_hw_control(struct igb_adapter *adapter) | |||
| 720 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | 720 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); |
| 721 | } | 721 | } |
| 722 | 722 | ||
| 723 | static void igb_init_manageability(struct igb_adapter *adapter) | ||
| 724 | { | ||
| 725 | struct e1000_hw *hw = &adapter->hw; | ||
| 726 | |||
| 727 | if (adapter->en_mng_pt) { | ||
| 728 | u32 manc2h = rd32(E1000_MANC2H); | ||
| 729 | u32 manc = rd32(E1000_MANC); | ||
| 730 | |||
| 731 | /* enable receiving management packets to the host */ | ||
| 732 | /* this will probably generate destination unreachable messages | ||
| 733 | * from the host OS, but the packets will be handled on SMBUS */ | ||
| 734 | manc |= E1000_MANC_EN_MNG2HOST; | ||
| 735 | #define E1000_MNG2HOST_PORT_623 (1 << 5) | ||
| 736 | #define E1000_MNG2HOST_PORT_664 (1 << 6) | ||
| 737 | manc2h |= E1000_MNG2HOST_PORT_623; | ||
| 738 | manc2h |= E1000_MNG2HOST_PORT_664; | ||
| 739 | wr32(E1000_MANC2H, manc2h); | ||
| 740 | |||
| 741 | wr32(E1000_MANC, manc); | ||
| 742 | } | ||
| 743 | } | ||
| 744 | |||
| 745 | /** | 723 | /** |
| 746 | * igb_configure - configure the hardware for RX and TX | 724 | * igb_configure - configure the hardware for RX and TX |
| 747 | * @adapter: private board structure | 725 | * @adapter: private board structure |
| @@ -755,7 +733,6 @@ static void igb_configure(struct igb_adapter *adapter) | |||
| 755 | igb_set_multi(netdev); | 733 | igb_set_multi(netdev); |
| 756 | 734 | ||
| 757 | igb_restore_vlan(adapter); | 735 | igb_restore_vlan(adapter); |
| 758 | igb_init_manageability(adapter); | ||
| 759 | 736 | ||
| 760 | igb_configure_tx(adapter); | 737 | igb_configure_tx(adapter); |
| 761 | igb_setup_rctl(adapter); | 738 | igb_setup_rctl(adapter); |
| @@ -1372,7 +1349,8 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
| 1372 | 1349 | ||
| 1373 | unregister_netdev(netdev); | 1350 | unregister_netdev(netdev); |
| 1374 | 1351 | ||
| 1375 | if (!igb_check_reset_block(&adapter->hw)) | 1352 | if (adapter->hw.phy.ops.reset_phy && |
| 1353 | !igb_check_reset_block(&adapter->hw)) | ||
| 1376 | adapter->hw.phy.ops.reset_phy(&adapter->hw); | 1354 | adapter->hw.phy.ops.reset_phy(&adapter->hw); |
| 1377 | 1355 | ||
| 1378 | igb_remove_device(&adapter->hw); | 1356 | igb_remove_device(&adapter->hw); |
| @@ -4523,8 +4501,6 @@ static void igb_io_resume(struct pci_dev *pdev) | |||
| 4523 | struct net_device *netdev = pci_get_drvdata(pdev); | 4501 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 4524 | struct igb_adapter *adapter = netdev_priv(netdev); | 4502 | struct igb_adapter *adapter = netdev_priv(netdev); |
| 4525 | 4503 | ||
| 4526 | igb_init_manageability(adapter); | ||
| 4527 | |||
| 4528 | if (netif_running(netdev)) { | 4504 | if (netif_running(netdev)) { |
| 4529 | if (igb_up(adapter)) { | 4505 | if (igb_up(adapter)) { |
| 4530 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | 4506 | dev_err(&pdev->dev, "igb_up failed after reset\n"); |
diff --git a/drivers/net/lp486e.c b/drivers/net/lp486e.c index 591a7e4220c7..83fa9d82a004 100644 --- a/drivers/net/lp486e.c +++ b/drivers/net/lp486e.c | |||
| @@ -1272,8 +1272,6 @@ static void set_multicast_list(struct net_device *dev) { | |||
| 1272 | return; | 1272 | return; |
| 1273 | } | 1273 | } |
| 1274 | if (dev->mc_count == 0 && !(dev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { | 1274 | if (dev->mc_count == 0 && !(dev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { |
| 1275 | if (dev->flags & IFF_ALLMULTI) | ||
| 1276 | dev->flags |= IFF_PROMISC; | ||
| 1277 | lp->i596_config[8] &= ~0x01; | 1275 | lp->i596_config[8] &= ~0x01; |
| 1278 | } else { | 1276 | } else { |
| 1279 | lp->i596_config[8] |= 0x01; | 1277 | lp->i596_config[8] |= 0x01; |
diff --git a/drivers/net/meth.c b/drivers/net/meth.c index 4cb364e67dc6..0a97c26df6ab 100644 --- a/drivers/net/meth.c +++ b/drivers/net/meth.c | |||
| @@ -100,7 +100,7 @@ static inline void load_eaddr(struct net_device *dev) | |||
| 100 | DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr)); | 100 | DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr)); |
| 101 | macaddr = 0; | 101 | macaddr = 0; |
| 102 | for (i = 0; i < 6; i++) | 102 | for (i = 0; i < 6; i++) |
| 103 | macaddr |= dev->dev_addr[i] << ((5 - i) * 8); | 103 | macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8); |
| 104 | 104 | ||
| 105 | mace->eth.mac_addr = macaddr; | 105 | mace->eth.mac_addr = macaddr; |
| 106 | } | 106 | } |
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c index 3ab0e5289f7a..f1de38f8b742 100644 --- a/drivers/net/myri10ge/myri10ge.c +++ b/drivers/net/myri10ge/myri10ge.c | |||
| @@ -3699,6 +3699,7 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 3699 | dev_err(&pdev->dev, "Error %d setting DMA mask\n", status); | 3699 | dev_err(&pdev->dev, "Error %d setting DMA mask\n", status); |
| 3700 | goto abort_with_netdev; | 3700 | goto abort_with_netdev; |
| 3701 | } | 3701 | } |
| 3702 | (void)pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | ||
| 3702 | mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd), | 3703 | mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd), |
| 3703 | &mgp->cmd_bus, GFP_KERNEL); | 3704 | &mgp->cmd_bus, GFP_KERNEL); |
| 3704 | if (mgp->cmd == NULL) | 3705 | if (mgp->cmd == NULL) |
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h index fdbeeee07372..993721090777 100644 --- a/drivers/net/myri10ge/myri10ge_mcp.h +++ b/drivers/net/myri10ge/myri10ge_mcp.h | |||
| @@ -101,6 +101,8 @@ struct mcp_kreq_ether_recv { | |||
| 101 | #define MXGEFW_ETH_SEND_3 0x2c0000 | 101 | #define MXGEFW_ETH_SEND_3 0x2c0000 |
| 102 | #define MXGEFW_ETH_RECV_SMALL 0x300000 | 102 | #define MXGEFW_ETH_RECV_SMALL 0x300000 |
| 103 | #define MXGEFW_ETH_RECV_BIG 0x340000 | 103 | #define MXGEFW_ETH_RECV_BIG 0x340000 |
| 104 | #define MXGEFW_ETH_SEND_GO 0x380000 | ||
| 105 | #define MXGEFW_ETH_SEND_STOP 0x3C0000 | ||
| 104 | 106 | ||
| 105 | #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) | 107 | #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) |
| 106 | #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) | 108 | #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) |
| @@ -120,6 +122,11 @@ enum myri10ge_mcp_cmd_type { | |||
| 120 | * MXGEFW_CMD_RESET is issued */ | 122 | * MXGEFW_CMD_RESET is issued */ |
| 121 | 123 | ||
| 122 | MXGEFW_CMD_SET_INTRQ_DMA, | 124 | MXGEFW_CMD_SET_INTRQ_DMA, |
| 125 | /* data0 = LSW of the host address | ||
| 126 | * data1 = MSW of the host address | ||
| 127 | * data2 = slice number if multiple slices are used | ||
| 128 | */ | ||
| 129 | |||
| 123 | MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ | 130 | MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ |
| 124 | MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ | 131 | MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ |
| 125 | 132 | ||
| @@ -129,6 +136,8 @@ enum myri10ge_mcp_cmd_type { | |||
| 129 | MXGEFW_CMD_GET_SEND_OFFSET, | 136 | MXGEFW_CMD_GET_SEND_OFFSET, |
| 130 | MXGEFW_CMD_GET_SMALL_RX_OFFSET, | 137 | MXGEFW_CMD_GET_SMALL_RX_OFFSET, |
| 131 | MXGEFW_CMD_GET_BIG_RX_OFFSET, | 138 | MXGEFW_CMD_GET_BIG_RX_OFFSET, |
| 139 | /* data0 = slice number if multiple slices are used */ | ||
| 140 | |||
| 132 | MXGEFW_CMD_GET_IRQ_ACK_OFFSET, | 141 | MXGEFW_CMD_GET_IRQ_ACK_OFFSET, |
| 133 | MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, | 142 | MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, |
| 134 | 143 | ||
| @@ -200,7 +209,12 @@ enum myri10ge_mcp_cmd_type { | |||
| 200 | MXGEFW_CMD_SET_STATS_DMA_V2, | 209 | MXGEFW_CMD_SET_STATS_DMA_V2, |
| 201 | /* data0, data1 = bus addr, | 210 | /* data0, data1 = bus addr, |
| 202 | * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows | 211 | * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows |
| 203 | * adding new stuff to mcp_irq_data without changing the ABI */ | 212 | * adding new stuff to mcp_irq_data without changing the ABI |
| 213 | * | ||
| 214 | * If multiple slices are used, data2 contains both the size of the | ||
| 215 | * structure (in the lower 16 bits) and the slice number | ||
| 216 | * (in the upper 16 bits). | ||
| 217 | */ | ||
| 204 | 218 | ||
| 205 | MXGEFW_CMD_UNALIGNED_TEST, | 219 | MXGEFW_CMD_UNALIGNED_TEST, |
| 206 | /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned | 220 | /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned |
| @@ -222,13 +236,18 @@ enum myri10ge_mcp_cmd_type { | |||
| 222 | MXGEFW_CMD_GET_MAX_RSS_QUEUES, | 236 | MXGEFW_CMD_GET_MAX_RSS_QUEUES, |
| 223 | MXGEFW_CMD_ENABLE_RSS_QUEUES, | 237 | MXGEFW_CMD_ENABLE_RSS_QUEUES, |
| 224 | /* data0 = number of slices n (0, 1, ..., n-1) to enable | 238 | /* data0 = number of slices n (0, 1, ..., n-1) to enable |
| 225 | * data1 = interrupt mode. | 239 | * data1 = interrupt mode | use of multiple transmit queues. |
| 226 | * 0=share one INTx/MSI, 1=use one MSI-X per queue. | 240 | * 0=share one INTx/MSI. |
| 241 | * 1=use one MSI-X per queue. | ||
| 227 | * If all queues share one interrupt, the driver must have set | 242 | * If all queues share one interrupt, the driver must have set |
| 228 | * RSS_SHARED_INTERRUPT_DMA before enabling queues. | 243 | * RSS_SHARED_INTERRUPT_DMA before enabling queues. |
| 244 | * 2=enable both receive and send queues. | ||
| 245 | * Without this bit set, only one send queue (slice 0's send queue) | ||
| 246 | * is enabled. The receive queues are always enabled. | ||
| 229 | */ | 247 | */ |
| 230 | #define MXGEFW_SLICE_INTR_MODE_SHARED 0 | 248 | #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 |
| 231 | #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1 | 249 | #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 |
| 250 | #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 | ||
| 232 | 251 | ||
| 233 | MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, | 252 | MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, |
| 234 | MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, | 253 | MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, |
| @@ -250,10 +269,13 @@ enum myri10ge_mcp_cmd_type { | |||
| 250 | * 2: TCP_IPV4 (required by RSS) | 269 | * 2: TCP_IPV4 (required by RSS) |
| 251 | * 3: IPV4 | TCP_IPV4 (required by RSS) | 270 | * 3: IPV4 | TCP_IPV4 (required by RSS) |
| 252 | * 4: source port | 271 | * 4: source port |
| 272 | * 5: source port + destination port | ||
| 253 | */ | 273 | */ |
| 254 | #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 | 274 | #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 |
| 255 | #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 | 275 | #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 |
| 256 | #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 | 276 | #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 |
| 277 | #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 | ||
| 278 | #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 | ||
| 257 | 279 | ||
| 258 | MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, | 280 | MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, |
| 259 | /* Return data = the max. size of the entire headers of a IPv6 TSO packet. | 281 | /* Return data = the max. size of the entire headers of a IPv6 TSO packet. |
| @@ -329,6 +351,20 @@ enum myri10ge_mcp_cmd_type { | |||
| 329 | 351 | ||
| 330 | MXGEFW_CMD_GET_DCA_OFFSET, | 352 | MXGEFW_CMD_GET_DCA_OFFSET, |
| 331 | /* offset of dca control for WDMAs */ | 353 | /* offset of dca control for WDMAs */ |
| 354 | |||
| 355 | /* VMWare NetQueue commands */ | ||
| 356 | MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE, | ||
| 357 | MXGEFW_CMD_NETQ_ADD_FILTER, | ||
| 358 | /* data0 = filter_id << 16 | queue << 8 | type */ | ||
| 359 | /* data1 = MS4 of MAC Addr */ | ||
| 360 | /* data2 = LS2_MAC << 16 | VLAN_tag */ | ||
| 361 | MXGEFW_CMD_NETQ_DEL_FILTER, | ||
| 362 | /* data0 = filter_id */ | ||
| 363 | MXGEFW_CMD_NETQ_QUERY1, | ||
| 364 | MXGEFW_CMD_NETQ_QUERY2, | ||
| 365 | MXGEFW_CMD_NETQ_QUERY3, | ||
| 366 | MXGEFW_CMD_NETQ_QUERY4, | ||
| 367 | |||
| 332 | }; | 368 | }; |
| 333 | 369 | ||
| 334 | enum myri10ge_mcp_cmd_status { | 370 | enum myri10ge_mcp_cmd_status { |
| @@ -381,4 +417,10 @@ struct mcp_irq_data { | |||
| 381 | u8 valid; | 417 | u8 valid; |
| 382 | }; | 418 | }; |
| 383 | 419 | ||
| 420 | /* definitions for NETQ filter type */ | ||
| 421 | #define MXGEFW_NETQ_FILTERTYPE_NONE 0 | ||
| 422 | #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 | ||
| 423 | #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 | ||
| 424 | #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 | ||
| 425 | |||
| 384 | #endif /* __MYRI10GE_MCP_H__ */ | 426 | #endif /* __MYRI10GE_MCP_H__ */ |
diff --git a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h index 07d65c2cbb24..a8662ea8079a 100644 --- a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h +++ b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h | |||
| @@ -35,7 +35,7 @@ struct mcp_gen_header { | |||
| 35 | unsigned char mcp_index; | 35 | unsigned char mcp_index; |
| 36 | unsigned char disable_rabbit; | 36 | unsigned char disable_rabbit; |
| 37 | unsigned char unaligned_tlp; | 37 | unsigned char unaligned_tlp; |
| 38 | unsigned char pad1; | 38 | unsigned char pcie_link_algo; |
| 39 | unsigned counters_addr; | 39 | unsigned counters_addr; |
| 40 | unsigned copy_block_info; /* for small mcps loaded with "lload -d" */ | 40 | unsigned copy_block_info; /* for small mcps loaded with "lload -d" */ |
| 41 | unsigned short handoff_id_major; /* must be equal */ | 41 | unsigned short handoff_id_major; /* must be equal */ |
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h index 8e736614407d..93a7b9b668d5 100644 --- a/drivers/net/netxen/netxen_nic.h +++ b/drivers/net/netxen/netxen_nic.h | |||
| @@ -508,6 +508,8 @@ typedef enum { | |||
| 508 | NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027, | 508 | NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027, |
| 509 | NETXEN_BRDTYPE_P3_XG_LOM = 0x0028, | 509 | NETXEN_BRDTYPE_P3_XG_LOM = 0x0028, |
| 510 | NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029, | 510 | NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029, |
| 511 | NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a, | ||
| 512 | NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b, | ||
| 511 | NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031, | 513 | NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031, |
| 512 | NETXEN_BRDTYPE_P3_10G_XFP = 0x0032 | 514 | NETXEN_BRDTYPE_P3_10G_XFP = 0x0032 |
| 513 | 515 | ||
| @@ -1170,6 +1172,36 @@ typedef struct { | |||
| 1170 | nx_nic_intr_coalesce_data_t irq; | 1172 | nx_nic_intr_coalesce_data_t irq; |
| 1171 | } nx_nic_intr_coalesce_t; | 1173 | } nx_nic_intr_coalesce_t; |
| 1172 | 1174 | ||
| 1175 | #define NX_HOST_REQUEST 0x13 | ||
| 1176 | #define NX_NIC_REQUEST 0x14 | ||
| 1177 | |||
| 1178 | #define NX_MAC_EVENT 0x1 | ||
| 1179 | |||
| 1180 | enum { | ||
| 1181 | NX_NIC_H2C_OPCODE_START = 0, | ||
| 1182 | NX_NIC_H2C_OPCODE_CONFIG_RSS, | ||
| 1183 | NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL, | ||
| 1184 | NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE, | ||
| 1185 | NX_NIC_H2C_OPCODE_CONFIG_LED, | ||
| 1186 | NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS, | ||
| 1187 | NX_NIC_H2C_OPCODE_CONFIG_L2_MAC, | ||
| 1188 | NX_NIC_H2C_OPCODE_LRO_REQUEST, | ||
| 1189 | NX_NIC_H2C_OPCODE_GET_SNMP_STATS, | ||
| 1190 | NX_NIC_H2C_OPCODE_PROXY_START_REQUEST, | ||
| 1191 | NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST, | ||
| 1192 | NX_NIC_H2C_OPCODE_PROXY_SET_MTU, | ||
| 1193 | NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE, | ||
| 1194 | NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST, | ||
| 1195 | NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST, | ||
| 1196 | NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST, | ||
| 1197 | NX_NIC_H2C_OPCODE_GET_NET_STATS, | ||
| 1198 | NX_NIC_H2C_OPCODE_LAST | ||
| 1199 | }; | ||
| 1200 | |||
| 1201 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | ||
| 1202 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | ||
| 1203 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | ||
| 1204 | |||
| 1173 | typedef struct { | 1205 | typedef struct { |
| 1174 | u64 qhdr; | 1206 | u64 qhdr; |
| 1175 | u64 req_hdr; | 1207 | u64 req_hdr; |
| @@ -1288,7 +1320,7 @@ struct netxen_adapter { | |||
| 1288 | int (*disable_phy_interrupts) (struct netxen_adapter *); | 1320 | int (*disable_phy_interrupts) (struct netxen_adapter *); |
| 1289 | int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); | 1321 | int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); |
| 1290 | int (*set_mtu) (struct netxen_adapter *, int); | 1322 | int (*set_mtu) (struct netxen_adapter *, int); |
| 1291 | int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t); | 1323 | int (*set_promisc) (struct netxen_adapter *, u32); |
| 1292 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); | 1324 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); |
| 1293 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); | 1325 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); |
| 1294 | int (*init_port) (struct netxen_adapter *, int); | 1326 | int (*init_port) (struct netxen_adapter *, int); |
| @@ -1465,9 +1497,10 @@ int netxen_process_cmd_ring(struct netxen_adapter *adapter); | |||
| 1465 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); | 1497 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); |
| 1466 | void netxen_p2_nic_set_multi(struct net_device *netdev); | 1498 | void netxen_p2_nic_set_multi(struct net_device *netdev); |
| 1467 | void netxen_p3_nic_set_multi(struct net_device *netdev); | 1499 | void netxen_p3_nic_set_multi(struct net_device *netdev); |
| 1500 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); | ||
| 1468 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); | 1501 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); |
| 1469 | 1502 | ||
| 1470 | u32 nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, u32 mtu); | 1503 | int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); |
| 1471 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); | 1504 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); |
| 1472 | 1505 | ||
| 1473 | int netxen_nic_set_mac(struct net_device *netdev, void *p); | 1506 | int netxen_nic_set_mac(struct net_device *netdev, void *p); |
| @@ -1502,7 +1535,9 @@ static const struct netxen_brdinfo netxen_boards[] = { | |||
| 1502 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, | 1535 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, |
| 1503 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, | 1536 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, |
| 1504 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, | 1537 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, |
| 1505 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "Quad GB - March Madness"}, | 1538 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, |
| 1539 | {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, | ||
| 1540 | {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, | ||
| 1506 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, | 1541 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, |
| 1507 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} | 1542 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} |
| 1508 | }; | 1543 | }; |
diff --git a/drivers/net/netxen/netxen_nic_ctx.c b/drivers/net/netxen/netxen_nic_ctx.c index 64babc59e699..64b51643c626 100644 --- a/drivers/net/netxen/netxen_nic_ctx.c +++ b/drivers/net/netxen/netxen_nic_ctx.c | |||
| @@ -145,8 +145,8 @@ netxen_issue_cmd(struct netxen_adapter *adapter, | |||
| 145 | return rcode; | 145 | return rcode; |
| 146 | } | 146 | } |
| 147 | 147 | ||
| 148 | u32 | 148 | int |
| 149 | nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, u32 mtu) | 149 | nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu) |
| 150 | { | 150 | { |
| 151 | u32 rcode = NX_RCODE_SUCCESS; | 151 | u32 rcode = NX_RCODE_SUCCESS; |
| 152 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; | 152 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; |
| @@ -160,7 +160,10 @@ nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, u32 mtu) | |||
| 160 | 0, | 160 | 0, |
| 161 | NX_CDRP_CMD_SET_MTU); | 161 | NX_CDRP_CMD_SET_MTU); |
| 162 | 162 | ||
| 163 | return rcode; | 163 | if (rcode != NX_RCODE_SUCCESS) |
| 164 | return -EIO; | ||
| 165 | |||
| 166 | return 0; | ||
| 164 | } | 167 | } |
| 165 | 168 | ||
| 166 | static int | 169 | static int |
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c index 48ee06b6f4e9..4ad3e0844b99 100644 --- a/drivers/net/netxen/netxen_nic_ethtool.c +++ b/drivers/net/netxen/netxen_nic_ethtool.c | |||
| @@ -140,18 +140,33 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
| 140 | if (netif_running(dev)) { | 140 | if (netif_running(dev)) { |
| 141 | ecmd->speed = adapter->link_speed; | 141 | ecmd->speed = adapter->link_speed; |
| 142 | ecmd->duplex = adapter->link_duplex; | 142 | ecmd->duplex = adapter->link_duplex; |
| 143 | } else | 143 | ecmd->autoneg = adapter->link_autoneg; |
| 144 | return -EIO; /* link absent */ | 144 | } |
| 145 | |||
| 145 | } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { | 146 | } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { |
| 146 | ecmd->supported = (SUPPORTED_TP | | 147 | u32 val; |
| 147 | SUPPORTED_1000baseT_Full | | 148 | |
| 148 | SUPPORTED_10000baseT_Full); | 149 | adapter->hw_read_wx(adapter, NETXEN_PORT_MODE_ADDR, &val, 4); |
| 149 | ecmd->advertising = (ADVERTISED_TP | | 150 | if (val == NETXEN_PORT_MODE_802_3_AP) { |
| 150 | ADVERTISED_1000baseT_Full | | 151 | ecmd->supported = SUPPORTED_1000baseT_Full; |
| 151 | ADVERTISED_10000baseT_Full); | 152 | ecmd->advertising = ADVERTISED_1000baseT_Full; |
| 153 | } else { | ||
| 154 | ecmd->supported = SUPPORTED_10000baseT_Full; | ||
| 155 | ecmd->advertising = ADVERTISED_10000baseT_Full; | ||
| 156 | } | ||
| 157 | |||
| 152 | ecmd->port = PORT_TP; | 158 | ecmd->port = PORT_TP; |
| 153 | 159 | ||
| 154 | ecmd->speed = SPEED_10000; | 160 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
| 161 | u16 pcifn = adapter->ahw.pci_func; | ||
| 162 | |||
| 163 | adapter->hw_read_wx(adapter, | ||
| 164 | P3_LINK_SPEED_REG(pcifn), &val, 4); | ||
| 165 | ecmd->speed = P3_LINK_SPEED_MHZ * | ||
| 166 | P3_LINK_SPEED_VAL(pcifn, val); | ||
| 167 | } else | ||
| 168 | ecmd->speed = SPEED_10000; | ||
| 169 | |||
| 155 | ecmd->duplex = DUPLEX_FULL; | 170 | ecmd->duplex = DUPLEX_FULL; |
| 156 | ecmd->autoneg = AUTONEG_DISABLE; | 171 | ecmd->autoneg = AUTONEG_DISABLE; |
| 157 | } else | 172 | } else |
| @@ -192,6 +207,8 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
| 192 | break; | 207 | break; |
| 193 | case NETXEN_BRDTYPE_P2_SB31_10G: | 208 | case NETXEN_BRDTYPE_P2_SB31_10G: |
| 194 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: | 209 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: |
| 210 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: | ||
| 211 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: | ||
| 195 | case NETXEN_BRDTYPE_P3_10G_XFP: | 212 | case NETXEN_BRDTYPE_P3_10G_XFP: |
| 196 | ecmd->supported |= SUPPORTED_FIBRE; | 213 | ecmd->supported |= SUPPORTED_FIBRE; |
| 197 | ecmd->advertising |= ADVERTISED_FIBRE; | 214 | ecmd->advertising |= ADVERTISED_FIBRE; |
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h index 3ce13e451aac..e8e8d73f6ed7 100644 --- a/drivers/net/netxen/netxen_nic_hdr.h +++ b/drivers/net/netxen/netxen_nic_hdr.h | |||
| @@ -724,6 +724,13 @@ enum { | |||
| 724 | #define XG_LINK_STATE_P3(pcifn,val) \ | 724 | #define XG_LINK_STATE_P3(pcifn,val) \ |
| 725 | (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) | 725 | (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) |
| 726 | 726 | ||
| 727 | #define P3_LINK_SPEED_MHZ 100 | ||
| 728 | #define P3_LINK_SPEED_MASK 0xff | ||
| 729 | #define P3_LINK_SPEED_REG(pcifn) \ | ||
| 730 | (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4)) | ||
| 731 | #define P3_LINK_SPEED_VAL(pcifn, reg) \ | ||
| 732 | (((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK) | ||
| 733 | |||
| 727 | #define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000) | 734 | #define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000) |
| 728 | #define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg)) | 735 | #define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg)) |
| 729 | #define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150)) | 736 | #define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150)) |
| @@ -836,9 +843,11 @@ enum { | |||
| 836 | 843 | ||
| 837 | #define PCIE_SETUP_FUNCTION (0x12040) | 844 | #define PCIE_SETUP_FUNCTION (0x12040) |
| 838 | #define PCIE_SETUP_FUNCTION2 (0x12048) | 845 | #define PCIE_SETUP_FUNCTION2 (0x12048) |
| 846 | #define PCIE_MISCCFG_RC (0x1206c) | ||
| 839 | #define PCIE_TGT_SPLIT_CHICKEN (0x12080) | 847 | #define PCIE_TGT_SPLIT_CHICKEN (0x12080) |
| 840 | #define PCIE_CHICKEN3 (0x120c8) | 848 | #define PCIE_CHICKEN3 (0x120c8) |
| 841 | 849 | ||
| 850 | #define ISR_INT_STATE_REG (NETXEN_PCIX_PS_REG(PCIE_MISCCFG_RC)) | ||
| 842 | #define PCIE_MAX_MASTER_SPLIT (0x14048) | 851 | #define PCIE_MAX_MASTER_SPLIT (0x14048) |
| 843 | 852 | ||
| 844 | #define NETXEN_PORT_MODE_NONE 0 | 853 | #define NETXEN_PORT_MODE_NONE 0 |
| @@ -854,6 +863,7 @@ enum { | |||
| 854 | #define NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL (0x14) | 863 | #define NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL (0x14) |
| 855 | 864 | ||
| 856 | #define ISR_MSI_INT_TRIGGER(FUNC) (NETXEN_PCIX_PS_REG(PCIX_MSI_F(FUNC))) | 865 | #define ISR_MSI_INT_TRIGGER(FUNC) (NETXEN_PCIX_PS_REG(PCIX_MSI_F(FUNC))) |
| 866 | #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) | ||
| 857 | 867 | ||
| 858 | /* | 868 | /* |
| 859 | * PCI Interrupt Vector Values. | 869 | * PCI Interrupt Vector Values. |
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 96a3bc6426e2..9aa20f961618 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c | |||
| @@ -285,14 +285,7 @@ static unsigned crb_hub_agt[64] = | |||
| 285 | #define ADDR_IN_RANGE(addr, low, high) \ | 285 | #define ADDR_IN_RANGE(addr, low, high) \ |
| 286 | (((addr) <= (high)) && ((addr) >= (low))) | 286 | (((addr) <= (high)) && ((addr) >= (low))) |
| 287 | 287 | ||
| 288 | #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE | ||
| 289 | #define NETXEN_MIN_MTU 64 | ||
| 290 | #define NETXEN_ETH_FCS_SIZE 4 | ||
| 291 | #define NETXEN_ENET_HEADER_SIZE 14 | ||
| 292 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ | 288 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
| 293 | #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) | ||
| 294 | #define NETXEN_NIU_HDRSIZE (0x1 << 6) | ||
| 295 | #define NETXEN_NIU_TLRSIZE (0x1 << 5) | ||
| 296 | 289 | ||
| 297 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL | 290 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL |
| 298 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL | 291 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL |
| @@ -541,9 +534,6 @@ netxen_send_cmd_descs(struct netxen_adapter *adapter, | |||
| 541 | return 0; | 534 | return 0; |
| 542 | } | 535 | } |
| 543 | 536 | ||
| 544 | #define NIC_REQUEST 0x14 | ||
| 545 | #define NETXEN_MAC_EVENT 0x1 | ||
| 546 | |||
| 547 | static int nx_p3_sre_macaddr_change(struct net_device *dev, | 537 | static int nx_p3_sre_macaddr_change(struct net_device *dev, |
| 548 | u8 *addr, unsigned op) | 538 | u8 *addr, unsigned op) |
| 549 | { | 539 | { |
| @@ -553,8 +543,8 @@ static int nx_p3_sre_macaddr_change(struct net_device *dev, | |||
| 553 | int rv; | 543 | int rv; |
| 554 | 544 | ||
| 555 | memset(&req, 0, sizeof(nx_nic_req_t)); | 545 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 556 | req.qhdr |= (NIC_REQUEST << 23); | 546 | req.qhdr |= (NX_NIC_REQUEST << 23); |
| 557 | req.req_hdr |= NETXEN_MAC_EVENT; | 547 | req.req_hdr |= NX_MAC_EVENT; |
| 558 | req.req_hdr |= ((u64)adapter->portnum << 16); | 548 | req.req_hdr |= ((u64)adapter->portnum << 16); |
| 559 | mac_req.op = op; | 549 | mac_req.op = op; |
| 560 | memcpy(&mac_req.mac_addr, addr, 6); | 550 | memcpy(&mac_req.mac_addr, addr, 6); |
| @@ -575,31 +565,35 @@ void netxen_p3_nic_set_multi(struct net_device *netdev) | |||
| 575 | nx_mac_list_t *cur, *next, *del_list, *add_list = NULL; | 565 | nx_mac_list_t *cur, *next, *del_list, *add_list = NULL; |
| 576 | struct dev_mc_list *mc_ptr; | 566 | struct dev_mc_list *mc_ptr; |
| 577 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | 567 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 578 | 568 | u32 mode = VPORT_MISS_MODE_DROP; | |
| 579 | adapter->set_promisc(adapter, NETXEN_NIU_PROMISC_MODE); | ||
| 580 | |||
| 581 | /* | ||
| 582 | * Programming mac addresses will automaticly enabling L2 filtering. | ||
| 583 | * HW will replace timestamp with L2 conid when L2 filtering is | ||
| 584 | * enabled. This causes problem for LSA. Do not enabling L2 filtering | ||
| 585 | * until that problem is fixed. | ||
| 586 | */ | ||
| 587 | if ((netdev->flags & IFF_PROMISC) || | ||
| 588 | (netdev->mc_count > adapter->max_mc_count)) | ||
| 589 | return; | ||
| 590 | 569 | ||
| 591 | del_list = adapter->mac_list; | 570 | del_list = adapter->mac_list; |
| 592 | adapter->mac_list = NULL; | 571 | adapter->mac_list = NULL; |
| 593 | 572 | ||
| 594 | nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list); | 573 | nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list); |
| 574 | nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list); | ||
| 575 | |||
| 576 | if (netdev->flags & IFF_PROMISC) { | ||
| 577 | mode = VPORT_MISS_MODE_ACCEPT_ALL; | ||
| 578 | goto send_fw_cmd; | ||
| 579 | } | ||
| 580 | |||
| 581 | if ((netdev->flags & IFF_ALLMULTI) || | ||
| 582 | (netdev->mc_count > adapter->max_mc_count)) { | ||
| 583 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; | ||
| 584 | goto send_fw_cmd; | ||
| 585 | } | ||
| 586 | |||
| 595 | if (netdev->mc_count > 0) { | 587 | if (netdev->mc_count > 0) { |
| 596 | nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list); | ||
| 597 | for (mc_ptr = netdev->mc_list; mc_ptr; | 588 | for (mc_ptr = netdev->mc_list; mc_ptr; |
| 598 | mc_ptr = mc_ptr->next) { | 589 | mc_ptr = mc_ptr->next) { |
| 599 | nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, | 590 | nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, |
| 600 | &add_list, &del_list); | 591 | &add_list, &del_list); |
| 601 | } | 592 | } |
| 602 | } | 593 | } |
| 594 | |||
| 595 | send_fw_cmd: | ||
| 596 | adapter->set_promisc(adapter, mode); | ||
| 603 | for (cur = del_list; cur;) { | 597 | for (cur = del_list; cur;) { |
| 604 | nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL); | 598 | nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL); |
| 605 | next = cur->next; | 599 | next = cur->next; |
| @@ -615,6 +609,21 @@ void netxen_p3_nic_set_multi(struct net_device *netdev) | |||
| 615 | } | 609 | } |
| 616 | } | 610 | } |
| 617 | 611 | ||
| 612 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) | ||
| 613 | { | ||
| 614 | nx_nic_req_t req; | ||
| 615 | |||
| 616 | memset(&req, 0, sizeof(nx_nic_req_t)); | ||
| 617 | |||
| 618 | req.qhdr |= (NX_HOST_REQUEST << 23); | ||
| 619 | req.req_hdr |= NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE; | ||
| 620 | req.req_hdr |= ((u64)adapter->portnum << 16); | ||
| 621 | req.words[0] = cpu_to_le64(mode); | ||
| 622 | |||
| 623 | return netxen_send_cmd_descs(adapter, | ||
| 624 | (struct cmd_desc_type0 *)&req, 1); | ||
| 625 | } | ||
| 626 | |||
| 618 | #define NETXEN_CONFIG_INTR_COALESCE 3 | 627 | #define NETXEN_CONFIG_INTR_COALESCE 3 |
| 619 | 628 | ||
| 620 | /* | 629 | /* |
| @@ -627,7 +636,7 @@ int netxen_config_intr_coalesce(struct netxen_adapter *adapter) | |||
| 627 | 636 | ||
| 628 | memset(&req, 0, sizeof(nx_nic_req_t)); | 637 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 629 | 638 | ||
| 630 | req.qhdr |= (NIC_REQUEST << 23); | 639 | req.qhdr |= (NX_NIC_REQUEST << 23); |
| 631 | req.req_hdr |= NETXEN_CONFIG_INTR_COALESCE; | 640 | req.req_hdr |= NETXEN_CONFIG_INTR_COALESCE; |
| 632 | req.req_hdr |= ((u64)adapter->portnum << 16); | 641 | req.req_hdr |= ((u64)adapter->portnum << 16); |
| 633 | 642 | ||
| @@ -653,6 +662,7 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |||
| 653 | { | 662 | { |
| 654 | struct netxen_adapter *adapter = netdev_priv(netdev); | 663 | struct netxen_adapter *adapter = netdev_priv(netdev); |
| 655 | int max_mtu; | 664 | int max_mtu; |
| 665 | int rc = 0; | ||
| 656 | 666 | ||
| 657 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | 667 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
| 658 | max_mtu = P3_MAX_MTU; | 668 | max_mtu = P3_MAX_MTU; |
| @@ -666,16 +676,12 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |||
| 666 | } | 676 | } |
| 667 | 677 | ||
| 668 | if (adapter->set_mtu) | 678 | if (adapter->set_mtu) |
| 669 | adapter->set_mtu(adapter, mtu); | 679 | rc = adapter->set_mtu(adapter, mtu); |
| 670 | netdev->mtu = mtu; | ||
| 671 | 680 | ||
| 672 | mtu += MTU_FUDGE_FACTOR; | 681 | if (!rc) |
| 673 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | 682 | netdev->mtu = mtu; |
| 674 | nx_fw_cmd_set_mtu(adapter, mtu); | ||
| 675 | else if (adapter->set_mtu) | ||
| 676 | adapter->set_mtu(adapter, mtu); | ||
| 677 | 683 | ||
| 678 | return 0; | 684 | return rc; |
| 679 | } | 685 | } |
| 680 | 686 | ||
| 681 | int netxen_is_flash_supported(struct netxen_adapter *adapter) | 687 | int netxen_is_flash_supported(struct netxen_adapter *adapter) |
| @@ -1411,7 +1417,8 @@ static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter, | |||
| 1411 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { | 1417 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1412 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | 1418 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1413 | printk(KERN_ERR "%s out of bound pci memory access. " | 1419 | printk(KERN_ERR "%s out of bound pci memory access. " |
| 1414 | "offset is 0x%llx\n", netxen_nic_driver_name, off); | 1420 | "offset is 0x%llx\n", netxen_nic_driver_name, |
| 1421 | (unsigned long long)off); | ||
| 1415 | return -1; | 1422 | return -1; |
| 1416 | } | 1423 | } |
| 1417 | 1424 | ||
| @@ -1484,7 +1491,8 @@ netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off, | |||
| 1484 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { | 1491 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1485 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | 1492 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1486 | printk(KERN_ERR "%s out of bound pci memory access. " | 1493 | printk(KERN_ERR "%s out of bound pci memory access. " |
| 1487 | "offset is 0x%llx\n", netxen_nic_driver_name, off); | 1494 | "offset is 0x%llx\n", netxen_nic_driver_name, |
| 1495 | (unsigned long long)off); | ||
| 1488 | return -1; | 1496 | return -1; |
| 1489 | } | 1497 | } |
| 1490 | 1498 | ||
| @@ -2016,6 +2024,8 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter) | |||
| 2016 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: | 2024 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: |
| 2017 | case NETXEN_BRDTYPE_P3_IMEZ: | 2025 | case NETXEN_BRDTYPE_P3_IMEZ: |
| 2018 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: | 2026 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: |
| 2027 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: | ||
| 2028 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: | ||
| 2019 | case NETXEN_BRDTYPE_P3_10G_XFP: | 2029 | case NETXEN_BRDTYPE_P3_10G_XFP: |
| 2020 | case NETXEN_BRDTYPE_P3_10000_BASE_T: | 2030 | case NETXEN_BRDTYPE_P3_10000_BASE_T: |
| 2021 | 2031 | ||
| @@ -2034,6 +2044,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter) | |||
| 2034 | default: | 2044 | default: |
| 2035 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, | 2045 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, |
| 2036 | boardinfo->board_type); | 2046 | boardinfo->board_type); |
| 2047 | rv = -ENODEV; | ||
| 2037 | break; | 2048 | break; |
| 2038 | } | 2049 | } |
| 2039 | 2050 | ||
| @@ -2044,6 +2055,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter) | |||
| 2044 | 2055 | ||
| 2045 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) | 2056 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
| 2046 | { | 2057 | { |
| 2058 | new_mtu += MTU_FUDGE_FACTOR; | ||
| 2047 | netxen_nic_write_w0(adapter, | 2059 | netxen_nic_write_w0(adapter, |
| 2048 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), | 2060 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
| 2049 | new_mtu); | 2061 | new_mtu); |
| @@ -2052,7 +2064,7 @@ int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) | |||
| 2052 | 2064 | ||
| 2053 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) | 2065 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
| 2054 | { | 2066 | { |
| 2055 | new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; | 2067 | new_mtu += MTU_FUDGE_FACTOR; |
| 2056 | if (adapter->physical_port == 0) | 2068 | if (adapter->physical_port == 0) |
| 2057 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, | 2069 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, |
| 2058 | new_mtu); | 2070 | new_mtu); |
| @@ -2074,12 +2086,22 @@ void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) | |||
| 2074 | __u32 status; | 2086 | __u32 status; |
| 2075 | __u32 autoneg; | 2087 | __u32 autoneg; |
| 2076 | __u32 mode; | 2088 | __u32 mode; |
| 2089 | __u32 port_mode; | ||
| 2077 | 2090 | ||
| 2078 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); | 2091 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); |
| 2079 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ | 2092 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ |
| 2093 | |||
| 2094 | adapter->hw_read_wx(adapter, | ||
| 2095 | NETXEN_PORT_MODE_ADDR, &port_mode, 4); | ||
| 2096 | if (port_mode == NETXEN_PORT_MODE_802_3_AP) { | ||
| 2097 | adapter->link_speed = SPEED_1000; | ||
| 2098 | adapter->link_duplex = DUPLEX_FULL; | ||
| 2099 | adapter->link_autoneg = AUTONEG_DISABLE; | ||
| 2100 | return; | ||
| 2101 | } | ||
| 2102 | |||
| 2080 | if (adapter->phy_read | 2103 | if (adapter->phy_read |
| 2081 | && adapter-> | 2104 | && adapter->phy_read(adapter, |
| 2082 | phy_read(adapter, | ||
| 2083 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, | 2105 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
| 2084 | &status) == 0) { | 2106 | &status) == 0) { |
| 2085 | if (netxen_get_phy_link(status)) { | 2107 | if (netxen_get_phy_link(status)) { |
| @@ -2109,8 +2131,7 @@ void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) | |||
| 2109 | break; | 2131 | break; |
| 2110 | } | 2132 | } |
| 2111 | if (adapter->phy_read | 2133 | if (adapter->phy_read |
| 2112 | && adapter-> | 2134 | && adapter->phy_read(adapter, |
| 2113 | phy_read(adapter, | ||
| 2114 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, | 2135 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
| 2115 | &autoneg) != 0) | 2136 | &autoneg) != 0) |
| 2116 | adapter->link_autoneg = autoneg; | 2137 | adapter->link_autoneg = autoneg; |
diff --git a/drivers/net/netxen/netxen_nic_hw.h b/drivers/net/netxen/netxen_nic_hw.h index b8e0030f03d7..aae737dc77a8 100644 --- a/drivers/net/netxen/netxen_nic_hw.h +++ b/drivers/net/netxen/netxen_nic_hw.h | |||
| @@ -419,12 +419,9 @@ typedef enum { | |||
| 419 | #define netxen_get_niu_enable_ge(config_word) \ | 419 | #define netxen_get_niu_enable_ge(config_word) \ |
| 420 | _netxen_crb_get_bit(config_word, 1) | 420 | _netxen_crb_get_bit(config_word, 1) |
| 421 | 421 | ||
| 422 | /* Promiscous mode options (GbE mode only) */ | 422 | #define NETXEN_NIU_NON_PROMISC_MODE 0 |
| 423 | typedef enum { | 423 | #define NETXEN_NIU_PROMISC_MODE 1 |
| 424 | NETXEN_NIU_PROMISC_MODE = 0, | 424 | #define NETXEN_NIU_ALLMULTI_MODE 2 |
| 425 | NETXEN_NIU_NON_PROMISC_MODE, | ||
| 426 | NETXEN_NIU_ALLMULTI_MODE | ||
| 427 | } netxen_niu_prom_mode_t; | ||
| 428 | 425 | ||
| 429 | /* | 426 | /* |
| 430 | * NIU GB Drop CRC Register | 427 | * NIU GB Drop CRC Register |
| @@ -471,9 +468,9 @@ typedef enum { | |||
| 471 | 468 | ||
| 472 | /* Set promiscuous mode for a GbE interface */ | 469 | /* Set promiscuous mode for a GbE interface */ |
| 473 | int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, | 470 | int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, |
| 474 | netxen_niu_prom_mode_t mode); | 471 | u32 mode); |
| 475 | int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, | 472 | int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, |
| 476 | netxen_niu_prom_mode_t mode); | 473 | u32 mode); |
| 477 | 474 | ||
| 478 | /* set the MAC address for a given MAC */ | 475 | /* set the MAC address for a given MAC */ |
| 479 | int netxen_niu_macaddr_set(struct netxen_adapter *adapter, | 476 | int netxen_niu_macaddr_set(struct netxen_adapter *adapter, |
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c index 01ab31b34a85..519fc860e17e 100644 --- a/drivers/net/netxen/netxen_nic_init.c +++ b/drivers/net/netxen/netxen_nic_init.c | |||
| @@ -364,6 +364,11 @@ void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) | |||
| 364 | default: | 364 | default: |
| 365 | break; | 365 | break; |
| 366 | } | 366 | } |
| 367 | |||
| 368 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | ||
| 369 | adapter->set_mtu = nx_fw_cmd_set_mtu; | ||
| 370 | adapter->set_promisc = netxen_p3_nic_set_promisc; | ||
| 371 | } | ||
| 367 | } | 372 | } |
| 368 | 373 | ||
| 369 | /* | 374 | /* |
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c index 91d209a8f6cb..7615c715e66e 100644 --- a/drivers/net/netxen/netxen_nic_main.c +++ b/drivers/net/netxen/netxen_nic_main.c | |||
| @@ -166,7 +166,8 @@ static void netxen_nic_disable_int(struct netxen_adapter *adapter) | |||
| 166 | if (!NETXEN_IS_MSI_FAMILY(adapter)) { | 166 | if (!NETXEN_IS_MSI_FAMILY(adapter)) { |
| 167 | do { | 167 | do { |
| 168 | adapter->pci_write_immediate(adapter, | 168 | adapter->pci_write_immediate(adapter, |
| 169 | ISR_INT_TARGET_STATUS, 0xffffffff); | 169 | adapter->legacy_intr.tgt_status_reg, |
| 170 | 0xffffffff); | ||
| 170 | mask = adapter->pci_read_immediate(adapter, | 171 | mask = adapter->pci_read_immediate(adapter, |
| 171 | ISR_INT_VECTOR); | 172 | ISR_INT_VECTOR); |
| 172 | if (!(mask & 0x80)) | 173 | if (!(mask & 0x80)) |
| @@ -175,7 +176,7 @@ static void netxen_nic_disable_int(struct netxen_adapter *adapter) | |||
| 175 | } while (--retries); | 176 | } while (--retries); |
| 176 | 177 | ||
| 177 | if (!retries) { | 178 | if (!retries) { |
| 178 | printk(KERN_NOTICE "%s: Failed to disable interrupt completely\n", | 179 | printk(KERN_NOTICE "%s: Failed to disable interrupt\n", |
| 179 | netxen_nic_driver_name); | 180 | netxen_nic_driver_name); |
| 180 | } | 181 | } |
| 181 | } else { | 182 | } else { |
| @@ -190,8 +191,6 @@ static void netxen_nic_enable_int(struct netxen_adapter *adapter) | |||
| 190 | { | 191 | { |
| 191 | u32 mask; | 192 | u32 mask; |
| 192 | 193 | ||
| 193 | DPRINTK(1, INFO, "Entered ISR Enable \n"); | ||
| 194 | |||
| 195 | if (adapter->intr_scheme != -1 && | 194 | if (adapter->intr_scheme != -1 && |
| 196 | adapter->intr_scheme != INTR_SCHEME_PERPORT) { | 195 | adapter->intr_scheme != INTR_SCHEME_PERPORT) { |
| 197 | switch (adapter->ahw.board_type) { | 196 | switch (adapter->ahw.board_type) { |
| @@ -213,16 +212,13 @@ static void netxen_nic_enable_int(struct netxen_adapter *adapter) | |||
| 213 | 212 | ||
| 214 | if (!NETXEN_IS_MSI_FAMILY(adapter)) { | 213 | if (!NETXEN_IS_MSI_FAMILY(adapter)) { |
| 215 | mask = 0xbff; | 214 | mask = 0xbff; |
| 216 | if (adapter->intr_scheme != -1 && | 215 | if (adapter->intr_scheme == INTR_SCHEME_PERPORT) |
| 217 | adapter->intr_scheme != INTR_SCHEME_PERPORT) { | 216 | adapter->pci_write_immediate(adapter, |
| 217 | adapter->legacy_intr.tgt_mask_reg, mask); | ||
| 218 | else | ||
| 218 | adapter->pci_write_normalize(adapter, | 219 | adapter->pci_write_normalize(adapter, |
| 219 | CRB_INT_VECTOR, 0); | 220 | CRB_INT_VECTOR, 0); |
| 220 | } | ||
| 221 | adapter->pci_write_immediate(adapter, | ||
| 222 | ISR_INT_TARGET_MASK, mask); | ||
| 223 | } | 221 | } |
| 224 | |||
| 225 | DPRINTK(1, INFO, "Done with enable Int\n"); | ||
| 226 | } | 222 | } |
| 227 | 223 | ||
| 228 | static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id) | 224 | static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id) |
| @@ -284,6 +280,8 @@ static void netxen_check_options(struct netxen_adapter *adapter) | |||
| 284 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: | 280 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: |
| 285 | case NETXEN_BRDTYPE_P3_IMEZ: | 281 | case NETXEN_BRDTYPE_P3_IMEZ: |
| 286 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: | 282 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: |
| 283 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: | ||
| 284 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: | ||
| 287 | case NETXEN_BRDTYPE_P3_10G_XFP: | 285 | case NETXEN_BRDTYPE_P3_10G_XFP: |
| 288 | case NETXEN_BRDTYPE_P3_10000_BASE_T: | 286 | case NETXEN_BRDTYPE_P3_10000_BASE_T: |
| 289 | adapter->msix_supported = !!use_msi_x; | 287 | adapter->msix_supported = !!use_msi_x; |
| @@ -301,6 +299,10 @@ static void netxen_check_options(struct netxen_adapter *adapter) | |||
| 301 | case NETXEN_BRDTYPE_P3_REF_QG: | 299 | case NETXEN_BRDTYPE_P3_REF_QG: |
| 302 | case NETXEN_BRDTYPE_P3_4_GB: | 300 | case NETXEN_BRDTYPE_P3_4_GB: |
| 303 | case NETXEN_BRDTYPE_P3_4_GB_MM: | 301 | case NETXEN_BRDTYPE_P3_4_GB_MM: |
| 302 | adapter->msix_supported = 0; | ||
| 303 | adapter->max_rx_desc_count = MAX_RCV_DESCRIPTORS_10G; | ||
| 304 | break; | ||
| 305 | |||
| 304 | case NETXEN_BRDTYPE_P2_SB35_4G: | 306 | case NETXEN_BRDTYPE_P2_SB35_4G: |
| 305 | case NETXEN_BRDTYPE_P2_SB31_2G: | 307 | case NETXEN_BRDTYPE_P2_SB31_2G: |
| 306 | adapter->msix_supported = 0; | 308 | adapter->msix_supported = 0; |
| @@ -700,13 +702,10 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 700 | adapter->status &= ~NETXEN_NETDEV_STATUS; | 702 | adapter->status &= ~NETXEN_NETDEV_STATUS; |
| 701 | adapter->rx_csum = 1; | 703 | adapter->rx_csum = 1; |
| 702 | adapter->mc_enabled = 0; | 704 | adapter->mc_enabled = 0; |
| 703 | if (NX_IS_REVISION_P3(revision_id)) { | 705 | if (NX_IS_REVISION_P3(revision_id)) |
| 704 | adapter->max_mc_count = 38; | 706 | adapter->max_mc_count = 38; |
| 705 | adapter->max_rds_rings = 2; | 707 | else |
| 706 | } else { | ||
| 707 | adapter->max_mc_count = 16; | 708 | adapter->max_mc_count = 16; |
| 708 | adapter->max_rds_rings = 3; | ||
| 709 | } | ||
| 710 | 709 | ||
| 711 | netdev->open = netxen_nic_open; | 710 | netdev->open = netxen_nic_open; |
| 712 | netdev->stop = netxen_nic_close; | 711 | netdev->stop = netxen_nic_close; |
| @@ -779,10 +778,6 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 779 | if (adapter->portnum == 0) | 778 | if (adapter->portnum == 0) |
| 780 | first_driver = 1; | 779 | first_driver = 1; |
| 781 | } | 780 | } |
| 782 | adapter->crb_addr_cmd_producer = crb_cmd_producer[adapter->portnum]; | ||
| 783 | adapter->crb_addr_cmd_consumer = crb_cmd_consumer[adapter->portnum]; | ||
| 784 | netxen_nic_update_cmd_producer(adapter, 0); | ||
| 785 | netxen_nic_update_cmd_consumer(adapter, 0); | ||
| 786 | 781 | ||
| 787 | if (first_driver) { | 782 | if (first_driver) { |
| 788 | first_boot = adapter->pci_read_normalize(adapter, | 783 | first_boot = adapter->pci_read_normalize(adapter, |
| @@ -1053,6 +1048,11 @@ static int netxen_nic_open(struct net_device *netdev) | |||
| 1053 | return -EIO; | 1048 | return -EIO; |
| 1054 | } | 1049 | } |
| 1055 | 1050 | ||
| 1051 | if (adapter->fw_major < 4) | ||
| 1052 | adapter->max_rds_rings = 3; | ||
| 1053 | else | ||
| 1054 | adapter->max_rds_rings = 2; | ||
| 1055 | |||
| 1056 | err = netxen_alloc_sw_resources(adapter); | 1056 | err = netxen_alloc_sw_resources(adapter); |
| 1057 | if (err) { | 1057 | if (err) { |
| 1058 | printk(KERN_ERR "%s: Error in setting sw resources\n", | 1058 | printk(KERN_ERR "%s: Error in setting sw resources\n", |
| @@ -1074,10 +1074,10 @@ static int netxen_nic_open(struct net_device *netdev) | |||
| 1074 | crb_cmd_producer[adapter->portnum]; | 1074 | crb_cmd_producer[adapter->portnum]; |
| 1075 | adapter->crb_addr_cmd_consumer = | 1075 | adapter->crb_addr_cmd_consumer = |
| 1076 | crb_cmd_consumer[adapter->portnum]; | 1076 | crb_cmd_consumer[adapter->portnum]; |
| 1077 | } | ||
| 1078 | 1077 | ||
| 1079 | netxen_nic_update_cmd_producer(adapter, 0); | 1078 | netxen_nic_update_cmd_producer(adapter, 0); |
| 1080 | netxen_nic_update_cmd_consumer(adapter, 0); | 1079 | netxen_nic_update_cmd_consumer(adapter, 0); |
| 1080 | } | ||
| 1081 | 1081 | ||
| 1082 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | 1082 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { |
| 1083 | for (ring = 0; ring < adapter->max_rds_rings; ring++) | 1083 | for (ring = 0; ring < adapter->max_rds_rings; ring++) |
| @@ -1113,9 +1113,7 @@ static int netxen_nic_open(struct net_device *netdev) | |||
| 1113 | netxen_nic_set_link_parameters(adapter); | 1113 | netxen_nic_set_link_parameters(adapter); |
| 1114 | 1114 | ||
| 1115 | netdev->set_multicast_list(netdev); | 1115 | netdev->set_multicast_list(netdev); |
| 1116 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | 1116 | if (adapter->set_mtu) |
| 1117 | nx_fw_cmd_set_mtu(adapter, netdev->mtu); | ||
| 1118 | else | ||
| 1119 | adapter->set_mtu(adapter, netdev->mtu); | 1117 | adapter->set_mtu(adapter, netdev->mtu); |
| 1120 | 1118 | ||
| 1121 | mod_timer(&adapter->watchdog_timer, jiffies); | 1119 | mod_timer(&adapter->watchdog_timer, jiffies); |
| @@ -1410,20 +1408,17 @@ static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter) | |||
| 1410 | 1408 | ||
| 1411 | port = adapter->physical_port; | 1409 | port = adapter->physical_port; |
| 1412 | 1410 | ||
| 1413 | if (adapter->ahw.board_type == NETXEN_NIC_GBE) { | 1411 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
| 1414 | val = adapter->pci_read_normalize(adapter, CRB_XG_STATE); | 1412 | val = adapter->pci_read_normalize(adapter, CRB_XG_STATE_P3); |
| 1415 | linkup = (val >> port) & 1; | 1413 | val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); |
| 1414 | linkup = (val == XG_LINK_UP_P3); | ||
| 1416 | } else { | 1415 | } else { |
| 1417 | if (adapter->fw_major < 4) { | 1416 | val = adapter->pci_read_normalize(adapter, CRB_XG_STATE); |
| 1418 | val = adapter->pci_read_normalize(adapter, | 1417 | if (adapter->ahw.board_type == NETXEN_NIC_GBE) |
| 1419 | CRB_XG_STATE); | 1418 | linkup = (val >> port) & 1; |
| 1419 | else { | ||
| 1420 | val = (val >> port*8) & 0xff; | 1420 | val = (val >> port*8) & 0xff; |
| 1421 | linkup = (val == XG_LINK_UP); | 1421 | linkup = (val == XG_LINK_UP); |
| 1422 | } else { | ||
| 1423 | val = adapter->pci_read_normalize(adapter, | ||
| 1424 | CRB_XG_STATE_P3); | ||
| 1425 | val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); | ||
| 1426 | linkup = (val == XG_LINK_UP_P3); | ||
| 1427 | } | 1422 | } |
| 1428 | } | 1423 | } |
| 1429 | 1424 | ||
| @@ -1535,15 +1530,33 @@ static irqreturn_t netxen_intr(int irq, void *data) | |||
| 1535 | struct netxen_adapter *adapter = data; | 1530 | struct netxen_adapter *adapter = data; |
| 1536 | u32 our_int = 0; | 1531 | u32 our_int = 0; |
| 1537 | 1532 | ||
| 1538 | our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR); | 1533 | u32 status = 0; |
| 1539 | /* not our interrupt */ | 1534 | |
| 1540 | if ((our_int & (0x80 << adapter->portnum)) == 0) | 1535 | status = adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); |
| 1536 | |||
| 1537 | if (!(status & adapter->legacy_intr.int_vec_bit)) | ||
| 1541 | return IRQ_NONE; | 1538 | return IRQ_NONE; |
| 1542 | 1539 | ||
| 1543 | if (adapter->intr_scheme == INTR_SCHEME_PERPORT) { | 1540 | if (adapter->ahw.revision_id >= NX_P3_B1) { |
| 1544 | /* claim interrupt */ | 1541 | /* check interrupt state machine, to be sure */ |
| 1545 | adapter->pci_write_normalize(adapter, CRB_INT_VECTOR, | 1542 | status = adapter->pci_read_immediate(adapter, |
| 1543 | ISR_INT_STATE_REG); | ||
| 1544 | if (!ISR_LEGACY_INT_TRIGGERED(status)) | ||
| 1545 | return IRQ_NONE; | ||
| 1546 | |||
| 1547 | } else if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | ||
| 1548 | |||
| 1549 | our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR); | ||
| 1550 | /* not our interrupt */ | ||
| 1551 | if ((our_int & (0x80 << adapter->portnum)) == 0) | ||
| 1552 | return IRQ_NONE; | ||
| 1553 | |||
| 1554 | if (adapter->intr_scheme == INTR_SCHEME_PERPORT) { | ||
| 1555 | /* claim interrupt */ | ||
| 1556 | adapter->pci_write_normalize(adapter, | ||
| 1557 | CRB_INT_VECTOR, | ||
| 1546 | our_int & ~((u32)(0x80 << adapter->portnum))); | 1558 | our_int & ~((u32)(0x80 << adapter->portnum))); |
| 1559 | } | ||
| 1547 | } | 1560 | } |
| 1548 | 1561 | ||
| 1549 | netxen_handle_int(adapter); | 1562 | netxen_handle_int(adapter); |
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c index 4cb8f4a1cf4b..27f07f6a45b1 100644 --- a/drivers/net/netxen/netxen_nic_niu.c +++ b/drivers/net/netxen/netxen_nic_niu.c | |||
| @@ -610,6 +610,9 @@ int netxen_niu_macaddr_set(struct netxen_adapter *adapter, | |||
| 610 | int i; | 610 | int i; |
| 611 | DECLARE_MAC_BUF(mac); | 611 | DECLARE_MAC_BUF(mac); |
| 612 | 612 | ||
| 613 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | ||
| 614 | return 0; | ||
| 615 | |||
| 613 | for (i = 0; i < 10; i++) { | 616 | for (i = 0; i < 10; i++) { |
| 614 | temp[0] = temp[1] = 0; | 617 | temp[0] = temp[1] = 0; |
| 615 | memcpy(temp + 2, addr, 2); | 618 | memcpy(temp + 2, addr, 2); |
| @@ -727,6 +730,9 @@ int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter) | |||
| 727 | __u32 mac_cfg0; | 730 | __u32 mac_cfg0; |
| 728 | u32 port = adapter->physical_port; | 731 | u32 port = adapter->physical_port; |
| 729 | 732 | ||
| 733 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | ||
| 734 | return 0; | ||
| 735 | |||
| 730 | if (port > NETXEN_NIU_MAX_GBE_PORTS) | 736 | if (port > NETXEN_NIU_MAX_GBE_PORTS) |
| 731 | return -EINVAL; | 737 | return -EINVAL; |
| 732 | mac_cfg0 = 0; | 738 | mac_cfg0 = 0; |
| @@ -743,6 +749,9 @@ int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) | |||
| 743 | __u32 mac_cfg; | 749 | __u32 mac_cfg; |
| 744 | u32 port = adapter->physical_port; | 750 | u32 port = adapter->physical_port; |
| 745 | 751 | ||
| 752 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | ||
| 753 | return 0; | ||
| 754 | |||
| 746 | if (port > NETXEN_NIU_MAX_XG_PORTS) | 755 | if (port > NETXEN_NIU_MAX_XG_PORTS) |
| 747 | return -EINVAL; | 756 | return -EINVAL; |
| 748 | 757 | ||
| @@ -755,7 +764,7 @@ int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) | |||
| 755 | 764 | ||
| 756 | /* Set promiscuous mode for a GbE interface */ | 765 | /* Set promiscuous mode for a GbE interface */ |
| 757 | int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, | 766 | int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, |
| 758 | netxen_niu_prom_mode_t mode) | 767 | u32 mode) |
| 759 | { | 768 | { |
| 760 | __u32 reg; | 769 | __u32 reg; |
| 761 | u32 port = adapter->physical_port; | 770 | u32 port = adapter->physical_port; |
| @@ -819,6 +828,9 @@ int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter, | |||
| 819 | u8 temp[4]; | 828 | u8 temp[4]; |
| 820 | u32 val; | 829 | u32 val; |
| 821 | 830 | ||
| 831 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | ||
| 832 | return 0; | ||
| 833 | |||
| 822 | if ((phy < 0) || (phy > NETXEN_NIU_MAX_XG_PORTS)) | 834 | if ((phy < 0) || (phy > NETXEN_NIU_MAX_XG_PORTS)) |
| 823 | return -EIO; | 835 | return -EIO; |
| 824 | 836 | ||
| @@ -894,7 +906,7 @@ int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, | |||
| 894 | #endif /* 0 */ | 906 | #endif /* 0 */ |
| 895 | 907 | ||
| 896 | int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, | 908 | int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, |
| 897 | netxen_niu_prom_mode_t mode) | 909 | u32 mode) |
| 898 | { | 910 | { |
| 899 | __u32 reg; | 911 | __u32 reg; |
| 900 | u32 port = adapter->physical_port; | 912 | u32 port = adapter->physical_port; |
diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h index 3bfa51b62a4f..83e5ee57bfef 100644 --- a/drivers/net/netxen/netxen_nic_phan_reg.h +++ b/drivers/net/netxen/netxen_nic_phan_reg.h | |||
| @@ -95,8 +95,8 @@ | |||
| 95 | #define CRB_HOST_STS_PROD NETXEN_NIC_REG(0xdc) | 95 | #define CRB_HOST_STS_PROD NETXEN_NIC_REG(0xdc) |
| 96 | #define CRB_HOST_STS_CONS NETXEN_NIC_REG(0xe0) | 96 | #define CRB_HOST_STS_CONS NETXEN_NIC_REG(0xe0) |
| 97 | #define CRB_PEG_CMD_PROD NETXEN_NIC_REG(0xe4) | 97 | #define CRB_PEG_CMD_PROD NETXEN_NIC_REG(0xe4) |
| 98 | #define CRB_PEG_CMD_CONS NETXEN_NIC_REG(0xe8) | 98 | #define CRB_PF_LINK_SPEED_1 NETXEN_NIC_REG(0xe8) |
| 99 | #define CRB_HOST_BUFFER_PROD NETXEN_NIC_REG(0xec) | 99 | #define CRB_PF_LINK_SPEED_2 NETXEN_NIC_REG(0xec) |
| 100 | #define CRB_HOST_BUFFER_CONS NETXEN_NIC_REG(0xf0) | 100 | #define CRB_HOST_BUFFER_CONS NETXEN_NIC_REG(0xf0) |
| 101 | #define CRB_JUMBO_BUFFER_PROD NETXEN_NIC_REG(0xf4) | 101 | #define CRB_JUMBO_BUFFER_PROD NETXEN_NIC_REG(0xf4) |
| 102 | #define CRB_JUMBO_BUFFER_CONS NETXEN_NIC_REG(0xf8) | 102 | #define CRB_JUMBO_BUFFER_CONS NETXEN_NIC_REG(0xf8) |
diff --git a/drivers/net/ni5010.c b/drivers/net/ni5010.c index a20005c09e07..8e0ca9f4e404 100644 --- a/drivers/net/ni5010.c +++ b/drivers/net/ni5010.c | |||
| @@ -648,7 +648,6 @@ static void ni5010_set_multicast_list(struct net_device *dev) | |||
| 648 | PRINTK2((KERN_DEBUG "%s: entering set_multicast_list\n", dev->name)); | 648 | PRINTK2((KERN_DEBUG "%s: entering set_multicast_list\n", dev->name)); |
| 649 | 649 | ||
| 650 | if (dev->flags&IFF_PROMISC || dev->flags&IFF_ALLMULTI || dev->mc_list) { | 650 | if (dev->flags&IFF_PROMISC || dev->flags&IFF_ALLMULTI || dev->mc_list) { |
| 651 | dev->flags |= IFF_PROMISC; | ||
| 652 | outb(RMD_PROMISC, EDLC_RMODE); /* Enable promiscuous mode */ | 651 | outb(RMD_PROMISC, EDLC_RMODE); /* Enable promiscuous mode */ |
| 653 | PRINTK((KERN_DEBUG "%s: Entering promiscuous mode\n", dev->name)); | 652 | PRINTK((KERN_DEBUG "%s: Entering promiscuous mode\n", dev->name)); |
| 654 | } else { | 653 | } else { |
diff --git a/drivers/net/ni52.c b/drivers/net/ni52.c index a316dcc8a06d..b9a882d362da 100644 --- a/drivers/net/ni52.c +++ b/drivers/net/ni52.c | |||
| @@ -621,7 +621,7 @@ static int init586(struct net_device *dev) | |||
| 621 | if (num_addrs > len) { | 621 | if (num_addrs > len) { |
| 622 | printk(KERN_ERR "%s: switching to promisc. mode\n", | 622 | printk(KERN_ERR "%s: switching to promisc. mode\n", |
| 623 | dev->name); | 623 | dev->name); |
| 624 | dev->flags |= IFF_PROMISC; | 624 | writeb(0x01, &cfg_cmd->promisc); |
| 625 | } | 625 | } |
| 626 | } | 626 | } |
| 627 | if (dev->flags & IFF_PROMISC) | 627 | if (dev->flags & IFF_PROMISC) |
diff --git a/drivers/net/qla3xxx.c b/drivers/net/qla3xxx.c index e82b37bbd6c3..3cdd07c45b6d 100644 --- a/drivers/net/qla3xxx.c +++ b/drivers/net/qla3xxx.c | |||
| @@ -38,7 +38,7 @@ | |||
| 38 | 38 | ||
| 39 | #define DRV_NAME "qla3xxx" | 39 | #define DRV_NAME "qla3xxx" |
| 40 | #define DRV_STRING "QLogic ISP3XXX Network Driver" | 40 | #define DRV_STRING "QLogic ISP3XXX Network Driver" |
| 41 | #define DRV_VERSION "v2.03.00-k4" | 41 | #define DRV_VERSION "v2.03.00-k5" |
| 42 | #define PFX DRV_NAME " " | 42 | #define PFX DRV_NAME " " |
| 43 | 43 | ||
| 44 | static const char ql3xxx_driver_name[] = DRV_NAME; | 44 | static const char ql3xxx_driver_name[] = DRV_NAME; |
| @@ -3495,8 +3495,6 @@ static void ql_set_mac_info(struct ql3_adapter *qdev) | |||
| 3495 | case ISP_CONTROL_FN0_NET: | 3495 | case ISP_CONTROL_FN0_NET: |
| 3496 | qdev->mac_index = 0; | 3496 | qdev->mac_index = 0; |
| 3497 | qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; | 3497 | qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; |
| 3498 | qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number; | ||
| 3499 | qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number; | ||
| 3500 | qdev->mb_bit_mask = FN0_MA_BITS_MASK; | 3498 | qdev->mb_bit_mask = FN0_MA_BITS_MASK; |
| 3501 | qdev->PHYAddr = PORT0_PHY_ADDRESS; | 3499 | qdev->PHYAddr = PORT0_PHY_ADDRESS; |
| 3502 | if (port_status & PORT_STATUS_SM0) | 3500 | if (port_status & PORT_STATUS_SM0) |
| @@ -3508,8 +3506,6 @@ static void ql_set_mac_info(struct ql3_adapter *qdev) | |||
| 3508 | case ISP_CONTROL_FN1_NET: | 3506 | case ISP_CONTROL_FN1_NET: |
| 3509 | qdev->mac_index = 1; | 3507 | qdev->mac_index = 1; |
| 3510 | qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; | 3508 | qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; |
| 3511 | qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number; | ||
| 3512 | qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number; | ||
| 3513 | qdev->mb_bit_mask = FN1_MA_BITS_MASK; | 3509 | qdev->mb_bit_mask = FN1_MA_BITS_MASK; |
| 3514 | qdev->PHYAddr = PORT1_PHY_ADDRESS; | 3510 | qdev->PHYAddr = PORT1_PHY_ADDRESS; |
| 3515 | if (port_status & PORT_STATUS_SM1) | 3511 | if (port_status & PORT_STATUS_SM1) |
| @@ -3730,14 +3726,6 @@ static int ql3xxx_open(struct net_device *ndev) | |||
| 3730 | return (ql_adapter_up(qdev)); | 3726 | return (ql_adapter_up(qdev)); |
| 3731 | } | 3727 | } |
| 3732 | 3728 | ||
| 3733 | static void ql3xxx_set_multicast_list(struct net_device *ndev) | ||
| 3734 | { | ||
| 3735 | /* | ||
| 3736 | * We are manually parsing the list in the net_device structure. | ||
| 3737 | */ | ||
| 3738 | return; | ||
| 3739 | } | ||
| 3740 | |||
| 3741 | static int ql3xxx_set_mac_address(struct net_device *ndev, void *p) | 3729 | static int ql3xxx_set_mac_address(struct net_device *ndev, void *p) |
| 3742 | { | 3730 | { |
| 3743 | struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev); | 3731 | struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev); |
| @@ -4007,7 +3995,11 @@ static int __devinit ql3xxx_probe(struct pci_dev *pdev, | |||
| 4007 | ndev->open = ql3xxx_open; | 3995 | ndev->open = ql3xxx_open; |
| 4008 | ndev->hard_start_xmit = ql3xxx_send; | 3996 | ndev->hard_start_xmit = ql3xxx_send; |
| 4009 | ndev->stop = ql3xxx_close; | 3997 | ndev->stop = ql3xxx_close; |
| 4010 | ndev->set_multicast_list = ql3xxx_set_multicast_list; | 3998 | /* ndev->set_multicast_list |
| 3999 | * This device is one side of a two-function adapter | ||
| 4000 | * (NIC and iSCSI). Promiscuous mode setting/clearing is | ||
| 4001 | * not allowed from the NIC side. | ||
| 4002 | */ | ||
| 4011 | SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops); | 4003 | SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops); |
| 4012 | ndev->set_mac_address = ql3xxx_set_mac_address; | 4004 | ndev->set_mac_address = ql3xxx_set_mac_address; |
| 4013 | ndev->tx_timeout = ql3xxx_tx_timeout; | 4005 | ndev->tx_timeout = ql3xxx_tx_timeout; |
| @@ -4040,9 +4032,6 @@ static int __devinit ql3xxx_probe(struct pci_dev *pdev, | |||
| 4040 | 4032 | ||
| 4041 | ndev->tx_queue_len = NUM_REQ_Q_ENTRIES; | 4033 | ndev->tx_queue_len = NUM_REQ_Q_ENTRIES; |
| 4042 | 4034 | ||
| 4043 | /* Turn off support for multicasting */ | ||
| 4044 | ndev->flags &= ~IFF_MULTICAST; | ||
| 4045 | |||
| 4046 | /* Record PCI bus information. */ | 4035 | /* Record PCI bus information. */ |
| 4047 | ql_get_board_info(qdev); | 4036 | ql_get_board_info(qdev); |
| 4048 | 4037 | ||
diff --git a/drivers/net/qla3xxx.h b/drivers/net/qla3xxx.h index 58a086fddec6..7113e71b15a1 100644 --- a/drivers/net/qla3xxx.h +++ b/drivers/net/qla3xxx.h | |||
| @@ -14,24 +14,14 @@ | |||
| 14 | 14 | ||
| 15 | #define OPCODE_OB_MAC_IOCB_FN0 0x01 | 15 | #define OPCODE_OB_MAC_IOCB_FN0 0x01 |
| 16 | #define OPCODE_OB_MAC_IOCB_FN2 0x21 | 16 | #define OPCODE_OB_MAC_IOCB_FN2 0x21 |
| 17 | #define OPCODE_OB_TCP_IOCB_FN0 0x03 | ||
| 18 | #define OPCODE_OB_TCP_IOCB_FN2 0x23 | ||
| 19 | #define OPCODE_UPDATE_NCB_IOCB_FN0 0x00 | ||
| 20 | #define OPCODE_UPDATE_NCB_IOCB_FN2 0x20 | ||
| 21 | 17 | ||
| 22 | #define OPCODE_UPDATE_NCB_IOCB 0xF0 | ||
| 23 | #define OPCODE_IB_MAC_IOCB 0xF9 | 18 | #define OPCODE_IB_MAC_IOCB 0xF9 |
| 24 | #define OPCODE_IB_3032_MAC_IOCB 0x09 | 19 | #define OPCODE_IB_3032_MAC_IOCB 0x09 |
| 25 | #define OPCODE_IB_IP_IOCB 0xFA | 20 | #define OPCODE_IB_IP_IOCB 0xFA |
| 26 | #define OPCODE_IB_3032_IP_IOCB 0x0A | 21 | #define OPCODE_IB_3032_IP_IOCB 0x0A |
| 27 | #define OPCODE_IB_TCP_IOCB 0xFB | ||
| 28 | #define OPCODE_DUMP_PROTO_IOCB 0xFE | ||
| 29 | #define OPCODE_BUFFER_ALERT_IOCB 0xFB | ||
| 30 | 22 | ||
| 31 | #define OPCODE_FUNC_ID_MASK 0x30 | 23 | #define OPCODE_FUNC_ID_MASK 0x30 |
| 32 | #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */ | 24 | #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */ |
| 33 | #define OUTBOUND_TCP_IOCB 0x03 /* plus function bits */ | ||
| 34 | #define UPDATE_NCB_IOCB 0x00 /* plus function bits */ | ||
| 35 | 25 | ||
| 36 | #define FN0_MA_BITS_MASK 0x00 | 26 | #define FN0_MA_BITS_MASK 0x00 |
| 37 | #define FN1_MA_BITS_MASK 0x80 | 27 | #define FN1_MA_BITS_MASK 0x80 |
| @@ -159,75 +149,6 @@ struct ob_ip_iocb_rsp { | |||
| 159 | __le32 reserved2; | 149 | __le32 reserved2; |
| 160 | }; | 150 | }; |
| 161 | 151 | ||
| 162 | struct ob_tcp_iocb_req { | ||
| 163 | u8 opcode; | ||
| 164 | |||
| 165 | u8 flags0; | ||
| 166 | #define OB_TCP_IOCB_REQ_P 0x80 | ||
| 167 | #define OB_TCP_IOCB_REQ_CI 0x20 | ||
| 168 | #define OB_TCP_IOCB_REQ_H 0x10 | ||
| 169 | #define OB_TCP_IOCB_REQ_LN 0x08 | ||
| 170 | #define OB_TCP_IOCB_REQ_K 0x04 | ||
| 171 | #define OB_TCP_IOCB_REQ_D 0x02 | ||
| 172 | #define OB_TCP_IOCB_REQ_I 0x01 | ||
| 173 | |||
| 174 | u8 flags1; | ||
| 175 | #define OB_TCP_IOCB_REQ_OSM 0x40 | ||
| 176 | #define OB_TCP_IOCB_REQ_URG 0x20 | ||
| 177 | #define OB_TCP_IOCB_REQ_ACK 0x10 | ||
| 178 | #define OB_TCP_IOCB_REQ_PSH 0x08 | ||
| 179 | #define OB_TCP_IOCB_REQ_RST 0x04 | ||
| 180 | #define OB_TCP_IOCB_REQ_SYN 0x02 | ||
| 181 | #define OB_TCP_IOCB_REQ_FIN 0x01 | ||
| 182 | |||
| 183 | u8 options_len; | ||
| 184 | #define OB_TCP_IOCB_REQ_OMASK 0xF0 | ||
| 185 | #define OB_TCP_IOCB_REQ_SHIFT 4 | ||
| 186 | |||
| 187 | __le32 transaction_id; | ||
| 188 | __le32 data_len; | ||
| 189 | __le32 hncb_ptr_low; | ||
| 190 | __le32 hncb_ptr_high; | ||
| 191 | __le32 buf_addr0_low; | ||
| 192 | __le32 buf_addr0_high; | ||
| 193 | __le32 buf_0_len; | ||
| 194 | __le32 buf_addr1_low; | ||
| 195 | __le32 buf_addr1_high; | ||
| 196 | __le32 buf_1_len; | ||
| 197 | __le32 buf_addr2_low; | ||
| 198 | __le32 buf_addr2_high; | ||
| 199 | __le32 buf_2_len; | ||
| 200 | __le32 time_stamp; | ||
| 201 | __le32 reserved1; | ||
| 202 | }; | ||
| 203 | |||
| 204 | struct ob_tcp_iocb_rsp { | ||
| 205 | u8 opcode; | ||
| 206 | |||
| 207 | u8 flags0; | ||
| 208 | #define OB_TCP_IOCB_RSP_C 0x20 | ||
| 209 | #define OB_TCP_IOCB_RSP_H 0x10 | ||
| 210 | #define OB_TCP_IOCB_RSP_LN 0x08 | ||
| 211 | #define OB_TCP_IOCB_RSP_K 0x04 | ||
| 212 | #define OB_TCP_IOCB_RSP_D 0x02 | ||
| 213 | #define OB_TCP_IOCB_RSP_I 0x01 | ||
| 214 | |||
| 215 | u8 flags1; | ||
| 216 | #define OB_TCP_IOCB_RSP_E 0x10 | ||
| 217 | #define OB_TCP_IOCB_RSP_W 0x08 | ||
| 218 | #define OB_TCP_IOCB_RSP_P 0x04 | ||
| 219 | #define OB_TCP_IOCB_RSP_T 0x02 | ||
| 220 | #define OB_TCP_IOCB_RSP_F 0x01 | ||
| 221 | |||
| 222 | u8 state; | ||
| 223 | #define OB_TCP_IOCB_RSP_SMASK 0xF0 | ||
| 224 | #define OB_TCP_IOCB_RSP_SHIFT 4 | ||
| 225 | |||
| 226 | __le32 transaction_id; | ||
| 227 | __le32 local_ncb_ptr; | ||
| 228 | __le32 reserved0; | ||
| 229 | }; | ||
| 230 | |||
| 231 | struct ib_ip_iocb_rsp { | 152 | struct ib_ip_iocb_rsp { |
| 232 | u8 opcode; | 153 | u8 opcode; |
| 233 | #define IB_IP_IOCB_RSP_3032_V 0x80 | 154 | #define IB_IP_IOCB_RSP_3032_V 0x80 |
| @@ -256,25 +177,6 @@ struct ib_ip_iocb_rsp { | |||
| 256 | __le32 ial_high; | 177 | __le32 ial_high; |
| 257 | }; | 178 | }; |
| 258 | 179 | ||
| 259 | struct ib_tcp_iocb_rsp { | ||
| 260 | u8 opcode; | ||
| 261 | u8 flags; | ||
| 262 | #define IB_TCP_IOCB_RSP_P 0x80 | ||
| 263 | #define IB_TCP_IOCB_RSP_T 0x40 | ||
| 264 | #define IB_TCP_IOCB_RSP_D 0x20 | ||
| 265 | #define IB_TCP_IOCB_RSP_N 0x10 | ||
| 266 | #define IB_TCP_IOCB_RSP_IP 0x03 | ||
| 267 | #define IB_TCP_FLAG_MASK 0xf0 | ||
| 268 | #define IB_TCP_FLAG_IOCB_SYN 0x00 | ||
| 269 | |||
| 270 | #define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK) | ||
| 271 | |||
| 272 | __le16 length; | ||
| 273 | __le32 hncb_ref_num; | ||
| 274 | __le32 ial_low; | ||
| 275 | __le32 ial_high; | ||
| 276 | }; | ||
| 277 | |||
| 278 | struct net_rsp_iocb { | 180 | struct net_rsp_iocb { |
| 279 | u8 opcode; | 181 | u8 opcode; |
| 280 | u8 flags; | 182 | u8 flags; |
| @@ -1266,20 +1168,13 @@ struct ql3_adapter { | |||
| 1266 | u32 small_buf_release_cnt; | 1168 | u32 small_buf_release_cnt; |
| 1267 | u32 small_buf_total_size; | 1169 | u32 small_buf_total_size; |
| 1268 | 1170 | ||
| 1269 | /* ISR related, saves status for DPC. */ | ||
| 1270 | u32 control_status; | ||
| 1271 | |||
| 1272 | struct eeprom_data nvram_data; | 1171 | struct eeprom_data nvram_data; |
| 1273 | struct timer_list ioctl_timer; | ||
| 1274 | u32 port_link_state; | 1172 | u32 port_link_state; |
| 1275 | u32 last_rsp_offset; | ||
| 1276 | 1173 | ||
| 1277 | /* 4022 specific */ | 1174 | /* 4022 specific */ |
| 1278 | u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */ | 1175 | u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */ |
| 1279 | u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */ | 1176 | u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */ |
| 1280 | u32 mac_ob_opcode; /* Opcode to use on mac transmission */ | 1177 | u32 mac_ob_opcode; /* Opcode to use on mac transmission */ |
| 1281 | u32 tcp_ob_opcode; /* Opcode to use on tcp transmission */ | ||
| 1282 | u32 update_ob_opcode; /* Opcode to use for updating NCB */ | ||
| 1283 | u32 mb_bit_mask; /* MA Bits mask to use on transmission */ | 1178 | u32 mb_bit_mask; /* MA Bits mask to use on transmission */ |
| 1284 | u32 numPorts; | 1179 | u32 numPorts; |
| 1285 | struct workqueue_struct *workqueue; | 1180 | struct workqueue_struct *workqueue; |
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 6a06b9503e4f..25e62cf58d3a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c | |||
| @@ -34,6 +34,29 @@ | |||
| 34 | 34 | ||
| 35 | #include "sh_eth.h" | 35 | #include "sh_eth.h" |
| 36 | 36 | ||
| 37 | /* CPU <-> EDMAC endian convert */ | ||
| 38 | static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) | ||
| 39 | { | ||
| 40 | switch (mdp->edmac_endian) { | ||
| 41 | case EDMAC_LITTLE_ENDIAN: | ||
| 42 | return cpu_to_le32(x); | ||
| 43 | case EDMAC_BIG_ENDIAN: | ||
| 44 | return cpu_to_be32(x); | ||
| 45 | } | ||
| 46 | return x; | ||
| 47 | } | ||
| 48 | |||
| 49 | static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) | ||
| 50 | { | ||
| 51 | switch (mdp->edmac_endian) { | ||
| 52 | case EDMAC_LITTLE_ENDIAN: | ||
| 53 | return le32_to_cpu(x); | ||
| 54 | case EDMAC_BIG_ENDIAN: | ||
| 55 | return be32_to_cpu(x); | ||
| 56 | } | ||
| 57 | return x; | ||
| 58 | } | ||
| 59 | |||
| 37 | /* | 60 | /* |
| 38 | * Program the hardware MAC address from dev->dev_addr. | 61 | * Program the hardware MAC address from dev->dev_addr. |
| 39 | */ | 62 | */ |
| @@ -240,7 +263,7 @@ static void sh_eth_ring_format(struct net_device *ndev) | |||
| 240 | /* RX descriptor */ | 263 | /* RX descriptor */ |
| 241 | rxdesc = &mdp->rx_ring[i]; | 264 | rxdesc = &mdp->rx_ring[i]; |
| 242 | rxdesc->addr = (u32)skb->data & ~0x3UL; | 265 | rxdesc->addr = (u32)skb->data & ~0x3UL; |
| 243 | rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); | 266 | rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); |
| 244 | 267 | ||
| 245 | /* The size of the buffer is 16 byte boundary. */ | 268 | /* The size of the buffer is 16 byte boundary. */ |
| 246 | rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F; | 269 | rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F; |
| @@ -262,7 +285,7 @@ static void sh_eth_ring_format(struct net_device *ndev) | |||
| 262 | mdp->dirty_rx = (u32) (i - RX_RING_SIZE); | 285 | mdp->dirty_rx = (u32) (i - RX_RING_SIZE); |
| 263 | 286 | ||
| 264 | /* Mark the last entry as wrapping the ring. */ | 287 | /* Mark the last entry as wrapping the ring. */ |
| 265 | rxdesc->status |= cpu_to_le32(RD_RDEL); | 288 | rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); |
| 266 | 289 | ||
| 267 | memset(mdp->tx_ring, 0, tx_ringsize); | 290 | memset(mdp->tx_ring, 0, tx_ringsize); |
| 268 | 291 | ||
| @@ -270,10 +293,10 @@ static void sh_eth_ring_format(struct net_device *ndev) | |||
| 270 | for (i = 0; i < TX_RING_SIZE; i++) { | 293 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 271 | mdp->tx_skbuff[i] = NULL; | 294 | mdp->tx_skbuff[i] = NULL; |
| 272 | txdesc = &mdp->tx_ring[i]; | 295 | txdesc = &mdp->tx_ring[i]; |
| 273 | txdesc->status = cpu_to_le32(TD_TFP); | 296 | txdesc->status = cpu_to_edmac(mdp, TD_TFP); |
| 274 | txdesc->buffer_length = 0; | 297 | txdesc->buffer_length = 0; |
| 275 | if (i == 0) { | 298 | if (i == 0) { |
| 276 | /* Rx descriptor address set */ | 299 | /* Tx descriptor address set */ |
| 277 | ctrl_outl((u32)txdesc, ioaddr + TDLAR); | 300 | ctrl_outl((u32)txdesc, ioaddr + TDLAR); |
| 278 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | 301 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 279 | ctrl_outl((u32)txdesc, ioaddr + TDFAR); | 302 | ctrl_outl((u32)txdesc, ioaddr + TDFAR); |
| @@ -281,13 +304,13 @@ static void sh_eth_ring_format(struct net_device *ndev) | |||
| 281 | } | 304 | } |
| 282 | } | 305 | } |
| 283 | 306 | ||
| 284 | /* Rx descriptor address set */ | 307 | /* Tx descriptor address set */ |
| 285 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | 308 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 286 | ctrl_outl((u32)txdesc, ioaddr + TDFXR); | 309 | ctrl_outl((u32)txdesc, ioaddr + TDFXR); |
| 287 | ctrl_outl(0x1, ioaddr + TDFFR); | 310 | ctrl_outl(0x1, ioaddr + TDFFR); |
| 288 | #endif | 311 | #endif |
| 289 | 312 | ||
| 290 | txdesc->status |= cpu_to_le32(TD_TDLE); | 313 | txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); |
| 291 | } | 314 | } |
| 292 | 315 | ||
| 293 | /* Get skb and descriptor buffer */ | 316 | /* Get skb and descriptor buffer */ |
| @@ -455,7 +478,7 @@ static int sh_eth_txfree(struct net_device *ndev) | |||
| 455 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { | 478 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { |
| 456 | entry = mdp->dirty_tx % TX_RING_SIZE; | 479 | entry = mdp->dirty_tx % TX_RING_SIZE; |
| 457 | txdesc = &mdp->tx_ring[entry]; | 480 | txdesc = &mdp->tx_ring[entry]; |
| 458 | if (txdesc->status & cpu_to_le32(TD_TACT)) | 481 | if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) |
| 459 | break; | 482 | break; |
| 460 | /* Free the original skb. */ | 483 | /* Free the original skb. */ |
| 461 | if (mdp->tx_skbuff[entry]) { | 484 | if (mdp->tx_skbuff[entry]) { |
| @@ -463,9 +486,9 @@ static int sh_eth_txfree(struct net_device *ndev) | |||
| 463 | mdp->tx_skbuff[entry] = NULL; | 486 | mdp->tx_skbuff[entry] = NULL; |
| 464 | freeNum++; | 487 | freeNum++; |
| 465 | } | 488 | } |
| 466 | txdesc->status = cpu_to_le32(TD_TFP); | 489 | txdesc->status = cpu_to_edmac(mdp, TD_TFP); |
| 467 | if (entry >= TX_RING_SIZE - 1) | 490 | if (entry >= TX_RING_SIZE - 1) |
| 468 | txdesc->status |= cpu_to_le32(TD_TDLE); | 491 | txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); |
| 469 | 492 | ||
| 470 | mdp->stats.tx_packets++; | 493 | mdp->stats.tx_packets++; |
| 471 | mdp->stats.tx_bytes += txdesc->buffer_length; | 494 | mdp->stats.tx_bytes += txdesc->buffer_length; |
| @@ -486,8 +509,8 @@ static int sh_eth_rx(struct net_device *ndev) | |||
| 486 | u32 desc_status, reserve = 0; | 509 | u32 desc_status, reserve = 0; |
| 487 | 510 | ||
| 488 | rxdesc = &mdp->rx_ring[entry]; | 511 | rxdesc = &mdp->rx_ring[entry]; |
| 489 | while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { | 512 | while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { |
| 490 | desc_status = le32_to_cpu(rxdesc->status); | 513 | desc_status = edmac_to_cpu(mdp, rxdesc->status); |
| 491 | pkt_len = rxdesc->frame_length; | 514 | pkt_len = rxdesc->frame_length; |
| 492 | 515 | ||
| 493 | if (--boguscnt < 0) | 516 | if (--boguscnt < 0) |
| @@ -522,7 +545,7 @@ static int sh_eth_rx(struct net_device *ndev) | |||
| 522 | mdp->stats.rx_packets++; | 545 | mdp->stats.rx_packets++; |
| 523 | mdp->stats.rx_bytes += pkt_len; | 546 | mdp->stats.rx_bytes += pkt_len; |
| 524 | } | 547 | } |
| 525 | rxdesc->status |= cpu_to_le32(RD_RACT); | 548 | rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); |
| 526 | entry = (++mdp->cur_rx) % RX_RING_SIZE; | 549 | entry = (++mdp->cur_rx) % RX_RING_SIZE; |
| 527 | } | 550 | } |
| 528 | 551 | ||
| @@ -552,10 +575,10 @@ static int sh_eth_rx(struct net_device *ndev) | |||
| 552 | } | 575 | } |
| 553 | if (entry >= RX_RING_SIZE - 1) | 576 | if (entry >= RX_RING_SIZE - 1) |
| 554 | rxdesc->status |= | 577 | rxdesc->status |= |
| 555 | cpu_to_le32(RD_RACT | RD_RFP | RD_RDEL); | 578 | cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); |
| 556 | else | 579 | else |
| 557 | rxdesc->status |= | 580 | rxdesc->status |= |
| 558 | cpu_to_le32(RD_RACT | RD_RFP); | 581 | cpu_to_edmac(mdp, RD_RACT | RD_RFP); |
| 559 | } | 582 | } |
| 560 | 583 | ||
| 561 | /* Restart Rx engine if stopped. */ | 584 | /* Restart Rx engine if stopped. */ |
| @@ -931,9 +954,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
| 931 | txdesc->buffer_length = skb->len; | 954 | txdesc->buffer_length = skb->len; |
| 932 | 955 | ||
| 933 | if (entry >= TX_RING_SIZE - 1) | 956 | if (entry >= TX_RING_SIZE - 1) |
| 934 | txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); | 957 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); |
| 935 | else | 958 | else |
| 936 | txdesc->status |= cpu_to_le32(TD_TACT); | 959 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT); |
| 937 | 960 | ||
| 938 | mdp->cur_tx++; | 961 | mdp->cur_tx++; |
| 939 | 962 | ||
| @@ -1159,6 +1182,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev) | |||
| 1159 | struct resource *res; | 1182 | struct resource *res; |
| 1160 | struct net_device *ndev = NULL; | 1183 | struct net_device *ndev = NULL; |
| 1161 | struct sh_eth_private *mdp; | 1184 | struct sh_eth_private *mdp; |
| 1185 | struct sh_eth_plat_data *pd; | ||
| 1162 | 1186 | ||
| 1163 | /* get base addr */ | 1187 | /* get base addr */ |
| 1164 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1188 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| @@ -1196,8 +1220,11 @@ static int sh_eth_drv_probe(struct platform_device *pdev) | |||
| 1196 | mdp = netdev_priv(ndev); | 1220 | mdp = netdev_priv(ndev); |
| 1197 | spin_lock_init(&mdp->lock); | 1221 | spin_lock_init(&mdp->lock); |
| 1198 | 1222 | ||
| 1223 | pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data); | ||
| 1199 | /* get PHY ID */ | 1224 | /* get PHY ID */ |
| 1200 | mdp->phy_id = (int)pdev->dev.platform_data; | 1225 | mdp->phy_id = pd->phy; |
| 1226 | /* EDMAC endian */ | ||
| 1227 | mdp->edmac_endian = pd->edmac_endian; | ||
| 1201 | 1228 | ||
| 1202 | /* set function */ | 1229 | /* set function */ |
| 1203 | ndev->open = sh_eth_open; | 1230 | ndev->open = sh_eth_open; |
| @@ -1217,12 +1244,16 @@ static int sh_eth_drv_probe(struct platform_device *pdev) | |||
| 1217 | 1244 | ||
| 1218 | /* First device only init */ | 1245 | /* First device only init */ |
| 1219 | if (!devno) { | 1246 | if (!devno) { |
| 1247 | #if defined(ARSTR) | ||
| 1220 | /* reset device */ | 1248 | /* reset device */ |
| 1221 | ctrl_outl(ARSTR_ARSTR, ARSTR); | 1249 | ctrl_outl(ARSTR_ARSTR, ARSTR); |
| 1222 | mdelay(1); | 1250 | mdelay(1); |
| 1251 | #endif | ||
| 1223 | 1252 | ||
| 1253 | #if defined(SH_TSU_ADDR) | ||
| 1224 | /* TSU init (Init only)*/ | 1254 | /* TSU init (Init only)*/ |
| 1225 | sh_eth_tsu_init(SH_TSU_ADDR); | 1255 | sh_eth_tsu_init(SH_TSU_ADDR); |
| 1256 | #endif | ||
| 1226 | } | 1257 | } |
| 1227 | 1258 | ||
| 1228 | /* network device register */ | 1259 | /* network device register */ |
| @@ -1240,8 +1271,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev) | |||
| 1240 | ndev->name, CARDNAME, (u32) ndev->base_addr); | 1271 | ndev->name, CARDNAME, (u32) ndev->base_addr); |
| 1241 | 1272 | ||
| 1242 | for (i = 0; i < 5; i++) | 1273 | for (i = 0; i < 5; i++) |
| 1243 | printk(KERN_INFO "%02X:", ndev->dev_addr[i]); | 1274 | printk("%02X:", ndev->dev_addr[i]); |
| 1244 | printk(KERN_INFO "%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq); | 1275 | printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq); |
| 1245 | 1276 | ||
| 1246 | platform_set_drvdata(pdev, ndev); | 1277 | platform_set_drvdata(pdev, ndev); |
| 1247 | 1278 | ||
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 45ad1b09ca5a..73bc7181cc18 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h | |||
| @@ -30,6 +30,8 @@ | |||
| 30 | #include <linux/netdevice.h> | 30 | #include <linux/netdevice.h> |
| 31 | #include <linux/phy.h> | 31 | #include <linux/phy.h> |
| 32 | 32 | ||
| 33 | #include <asm/sh_eth.h> | ||
| 34 | |||
| 33 | #define CARDNAME "sh-eth" | 35 | #define CARDNAME "sh-eth" |
| 34 | #define TX_TIMEOUT (5*HZ) | 36 | #define TX_TIMEOUT (5*HZ) |
| 35 | #define TX_RING_SIZE 64 /* Tx ring size */ | 37 | #define TX_RING_SIZE 64 /* Tx ring size */ |
| @@ -143,10 +145,11 @@ | |||
| 143 | 145 | ||
| 144 | #else /* CONFIG_CPU_SUBTYPE_SH7763 */ | 146 | #else /* CONFIG_CPU_SUBTYPE_SH7763 */ |
| 145 | # define RX_OFFSET 2 /* skb offset */ | 147 | # define RX_OFFSET 2 /* skb offset */ |
| 148 | #ifndef CONFIG_CPU_SUBTYPE_SH7619 | ||
| 146 | /* Chip base address */ | 149 | /* Chip base address */ |
| 147 | # define SH_TSU_ADDR 0xA7000804 | 150 | # define SH_TSU_ADDR 0xA7000804 |
| 148 | # define ARSTR 0xA7000800 | 151 | # define ARSTR 0xA7000800 |
| 149 | 152 | #endif | |
| 150 | /* Chip Registers */ | 153 | /* Chip Registers */ |
| 151 | /* E-DMAC */ | 154 | /* E-DMAC */ |
| 152 | # define EDMR 0x0000 | 155 | # define EDMR 0x0000 |
| @@ -384,7 +387,11 @@ enum FCFTR_BIT { | |||
| 384 | FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, | 387 | FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, |
| 385 | }; | 388 | }; |
| 386 | #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) | 389 | #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) |
| 390 | #ifndef CONFIG_CPU_SUBTYPE_SH7619 | ||
| 387 | #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) | 391 | #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) |
| 392 | #else | ||
| 393 | #define FIFO_F_D_RFD (FCFTR_RFD0) | ||
| 394 | #endif | ||
| 388 | 395 | ||
| 389 | /* Transfer descriptor bit */ | 396 | /* Transfer descriptor bit */ |
| 390 | enum TD_STS_BIT { | 397 | enum TD_STS_BIT { |
| @@ -414,8 +421,10 @@ enum FELIC_MODE_BIT { | |||
| 414 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 | 421 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 |
| 415 | #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\ | 422 | #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\ |
| 416 | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) | 423 | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) |
| 424 | #elif CONFIG_CPU_SUBTYPE_SH7619 | ||
| 425 | #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) | ||
| 417 | #else | 426 | #else |
| 418 | #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT) | 427 | #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) |
| 419 | #endif | 428 | #endif |
| 420 | 429 | ||
| 421 | /* ECSR */ | 430 | /* ECSR */ |
| @@ -485,7 +494,11 @@ enum RPADIR_BIT { | |||
| 485 | 494 | ||
| 486 | /* FDR */ | 495 | /* FDR */ |
| 487 | enum FIFO_SIZE_BIT { | 496 | enum FIFO_SIZE_BIT { |
| 497 | #ifndef CONFIG_CPU_SUBTYPE_SH7619 | ||
| 488 | FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, | 498 | FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, |
| 499 | #else | ||
| 500 | FIFO_SIZE_T = 0x00000100, FIFO_SIZE_R = 0x00000001, | ||
| 501 | #endif | ||
| 489 | }; | 502 | }; |
| 490 | enum phy_offsets { | 503 | enum phy_offsets { |
| 491 | PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, | 504 | PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, |
| @@ -601,7 +614,7 @@ struct sh_eth_txdesc { | |||
| 601 | #endif | 614 | #endif |
| 602 | u32 addr; /* TD2 */ | 615 | u32 addr; /* TD2 */ |
| 603 | u32 pad1; /* padding data */ | 616 | u32 pad1; /* padding data */ |
| 604 | }; | 617 | } __attribute__((aligned(2), packed)); |
| 605 | 618 | ||
| 606 | /* | 619 | /* |
| 607 | * The sh ether Rx buffer descriptors. | 620 | * The sh ether Rx buffer descriptors. |
| @@ -618,7 +631,7 @@ struct sh_eth_rxdesc { | |||
| 618 | #endif | 631 | #endif |
| 619 | u32 addr; /* RD2 */ | 632 | u32 addr; /* RD2 */ |
| 620 | u32 pad0; /* padding data */ | 633 | u32 pad0; /* padding data */ |
| 621 | }; | 634 | } __attribute__((aligned(2), packed)); |
| 622 | 635 | ||
| 623 | struct sh_eth_private { | 636 | struct sh_eth_private { |
| 624 | dma_addr_t rx_desc_dma; | 637 | dma_addr_t rx_desc_dma; |
| @@ -633,6 +646,7 @@ struct sh_eth_private { | |||
| 633 | u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ | 646 | u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ |
| 634 | u32 cur_tx, dirty_tx; | 647 | u32 cur_tx, dirty_tx; |
| 635 | u32 rx_buf_sz; /* Based on MTU+slack. */ | 648 | u32 rx_buf_sz; /* Based on MTU+slack. */ |
| 649 | int edmac_endian; | ||
| 636 | /* MII transceiver section. */ | 650 | /* MII transceiver section. */ |
| 637 | u32 phy_id; /* PHY ID */ | 651 | u32 phy_id; /* PHY ID */ |
| 638 | struct mii_bus *mii_bus; /* MDIO bus control */ | 652 | struct mii_bus *mii_bus; /* MDIO bus control */ |
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 5257cf464f1a..7d29edcd40b4 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
| @@ -275,86 +275,6 @@ static void sky2_power_aux(struct sky2_hw *hw) | |||
| 275 | PC_VAUX_ON | PC_VCC_OFF)); | 275 | PC_VAUX_ON | PC_VCC_OFF)); |
| 276 | } | 276 | } |
| 277 | 277 | ||
| 278 | static void sky2_power_state(struct sky2_hw *hw, pci_power_t state) | ||
| 279 | { | ||
| 280 | u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); | ||
| 281 | int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP); | ||
| 282 | u32 reg; | ||
| 283 | |||
| 284 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | ||
| 285 | |||
| 286 | switch (state) { | ||
| 287 | case PCI_D0: | ||
| 288 | break; | ||
| 289 | |||
| 290 | case PCI_D1: | ||
| 291 | power_control |= 1; | ||
| 292 | break; | ||
| 293 | |||
| 294 | case PCI_D2: | ||
| 295 | power_control |= 2; | ||
| 296 | break; | ||
| 297 | |||
| 298 | case PCI_D3hot: | ||
| 299 | case PCI_D3cold: | ||
| 300 | power_control |= 3; | ||
| 301 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { | ||
| 302 | /* additional power saving measurements */ | ||
| 303 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); | ||
| 304 | |||
| 305 | /* set gating core clock for LTSSM in L1 state */ | ||
| 306 | reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) | | ||
| 307 | /* auto clock gated scheme controlled by CLKREQ */ | ||
| 308 | P_ASPM_A1_MODE_SELECT | | ||
| 309 | /* enable Gate Root Core Clock */ | ||
| 310 | P_CLK_GATE_ROOT_COR_ENA; | ||
| 311 | |||
| 312 | if (pex && (hw->flags & SKY2_HW_CLK_POWER)) { | ||
| 313 | /* enable Clock Power Management (CLKREQ) */ | ||
| 314 | u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL); | ||
| 315 | |||
| 316 | ctrl |= PCI_EXP_DEVCTL_AUX_PME; | ||
| 317 | sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl); | ||
| 318 | } else | ||
| 319 | /* force CLKREQ Enable in Our4 (A1b only) */ | ||
| 320 | reg |= P_ASPM_FORCE_CLKREQ_ENA; | ||
| 321 | |||
| 322 | /* set Mask Register for Release/Gate Clock */ | ||
| 323 | sky2_pci_write32(hw, PCI_DEV_REG5, | ||
| 324 | P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST | | ||
| 325 | P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE | | ||
| 326 | P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN); | ||
| 327 | } else | ||
| 328 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT); | ||
| 329 | |||
| 330 | /* put CPU into reset state */ | ||
| 331 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET); | ||
| 332 | if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0) | ||
| 333 | /* put CPU into halt state */ | ||
| 334 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED); | ||
| 335 | |||
| 336 | if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) { | ||
| 337 | reg = sky2_pci_read32(hw, PCI_DEV_REG1); | ||
| 338 | /* force to PCIe L1 */ | ||
| 339 | reg |= PCI_FORCE_PEX_L1; | ||
| 340 | sky2_pci_write32(hw, PCI_DEV_REG1, reg); | ||
| 341 | } | ||
| 342 | break; | ||
| 343 | |||
| 344 | default: | ||
| 345 | dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ", | ||
| 346 | state); | ||
| 347 | return; | ||
| 348 | } | ||
| 349 | |||
| 350 | power_control |= PCI_PM_CTRL_PME_ENABLE; | ||
| 351 | /* Finally, set the new power state. */ | ||
| 352 | sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control); | ||
| 353 | |||
| 354 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | ||
| 355 | sky2_pci_read32(hw, B0_CTST); | ||
| 356 | } | ||
| 357 | |||
| 358 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) | 278 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
| 359 | { | 279 | { |
| 360 | u16 reg; | 280 | u16 reg; |
| @@ -709,6 +629,11 @@ static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) | |||
| 709 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | 629 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
| 710 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | 630 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
| 711 | sky2_pci_read32(hw, PCI_DEV_REG1); | 631 | sky2_pci_read32(hw, PCI_DEV_REG1); |
| 632 | |||
| 633 | if (hw->chip_id == CHIP_ID_YUKON_FE) | ||
| 634 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); | ||
| 635 | else if (hw->flags & SKY2_HW_ADV_POWER_CTL) | ||
| 636 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | ||
| 712 | } | 637 | } |
| 713 | 638 | ||
| 714 | static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) | 639 | static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) |
| @@ -2855,10 +2780,6 @@ static int __devinit sky2_init(struct sky2_hw *hw) | |||
| 2855 | hw->flags = SKY2_HW_GIGABIT | 2780 | hw->flags = SKY2_HW_GIGABIT |
| 2856 | | SKY2_HW_NEWER_PHY | 2781 | | SKY2_HW_NEWER_PHY |
| 2857 | | SKY2_HW_ADV_POWER_CTL; | 2782 | | SKY2_HW_ADV_POWER_CTL; |
| 2858 | |||
| 2859 | /* check for Rev. A1 dev 4200 */ | ||
| 2860 | if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0) | ||
| 2861 | hw->flags |= SKY2_HW_CLK_POWER; | ||
| 2862 | break; | 2783 | break; |
| 2863 | 2784 | ||
| 2864 | case CHIP_ID_YUKON_EX: | 2785 | case CHIP_ID_YUKON_EX: |
| @@ -2914,12 +2835,6 @@ static int __devinit sky2_init(struct sky2_hw *hw) | |||
| 2914 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') | 2835 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') |
| 2915 | hw->flags |= SKY2_HW_FIBRE_PHY; | 2836 | hw->flags |= SKY2_HW_FIBRE_PHY; |
| 2916 | 2837 | ||
| 2917 | hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM); | ||
| 2918 | if (hw->pm_cap == 0) { | ||
| 2919 | dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n"); | ||
| 2920 | return -EIO; | ||
| 2921 | } | ||
| 2922 | |||
| 2923 | hw->ports = 1; | 2838 | hw->ports = 1; |
| 2924 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | 2839 | t8 = sky2_read8(hw, B2_Y2_HW_RES); |
| 2925 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | 2840 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { |
| @@ -4512,7 +4427,7 @@ static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |||
| 4512 | 4427 | ||
| 4513 | pci_save_state(pdev); | 4428 | pci_save_state(pdev); |
| 4514 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); | 4429 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); |
| 4515 | sky2_power_state(hw, pci_choose_state(pdev, state)); | 4430 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 4516 | 4431 | ||
| 4517 | return 0; | 4432 | return 0; |
| 4518 | } | 4433 | } |
| @@ -4525,7 +4440,9 @@ static int sky2_resume(struct pci_dev *pdev) | |||
| 4525 | if (!hw) | 4440 | if (!hw) |
| 4526 | return 0; | 4441 | return 0; |
| 4527 | 4442 | ||
| 4528 | sky2_power_state(hw, PCI_D0); | 4443 | err = pci_set_power_state(pdev, PCI_D0); |
| 4444 | if (err) | ||
| 4445 | goto out; | ||
| 4529 | 4446 | ||
| 4530 | err = pci_restore_state(pdev); | 4447 | err = pci_restore_state(pdev); |
| 4531 | if (err) | 4448 | if (err) |
| @@ -4595,7 +4512,7 @@ static void sky2_shutdown(struct pci_dev *pdev) | |||
| 4595 | pci_enable_wake(pdev, PCI_D3cold, wol); | 4512 | pci_enable_wake(pdev, PCI_D3cold, wol); |
| 4596 | 4513 | ||
| 4597 | pci_disable_device(pdev); | 4514 | pci_disable_device(pdev); |
| 4598 | sky2_power_state(hw, PCI_D3hot); | 4515 | pci_set_power_state(pdev, PCI_D3hot); |
| 4599 | } | 4516 | } |
| 4600 | 4517 | ||
| 4601 | static struct pci_driver sky2_driver = { | 4518 | static struct pci_driver sky2_driver = { |
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 4d9c4a19bb85..92fb24b27d45 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
| @@ -2072,9 +2072,7 @@ struct sky2_hw { | |||
| 2072 | #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */ | 2072 | #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */ |
| 2073 | #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */ | 2073 | #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */ |
| 2074 | #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */ | 2074 | #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */ |
| 2075 | #define SKY2_HW_CLK_POWER 0x00000100 /* clock power management */ | ||
| 2076 | 2075 | ||
| 2077 | int pm_cap; | ||
| 2078 | u8 chip_id; | 2076 | u8 chip_id; |
| 2079 | u8 chip_rev; | 2077 | u8 chip_rev; |
| 2080 | u8 pmd_type; | 2078 | u8 pmd_type; |
diff --git a/drivers/net/sun3_82586.c b/drivers/net/sun3_82586.c index 9b2a7f7bb258..e531302d95f5 100644 --- a/drivers/net/sun3_82586.c +++ b/drivers/net/sun3_82586.c | |||
| @@ -425,14 +425,11 @@ static int init586(struct net_device *dev) | |||
| 425 | int len = ((char *) p->iscp - (char *) ptr - 8) / 6; | 425 | int len = ((char *) p->iscp - (char *) ptr - 8) / 6; |
| 426 | if(num_addrs > len) { | 426 | if(num_addrs > len) { |
| 427 | printk("%s: switching to promisc. mode\n",dev->name); | 427 | printk("%s: switching to promisc. mode\n",dev->name); |
| 428 | dev->flags|=IFF_PROMISC; | 428 | cfg_cmd->promisc = 1; |
| 429 | } | 429 | } |
| 430 | } | 430 | } |
| 431 | if(dev->flags&IFF_PROMISC) | 431 | if(dev->flags&IFF_PROMISC) |
| 432 | { | 432 | cfg_cmd->promisc = 1; |
| 433 | cfg_cmd->promisc=1; | ||
| 434 | dev->flags|=IFF_PROMISC; | ||
| 435 | } | ||
| 436 | cfg_cmd->carr_coll = 0x00; | 433 | cfg_cmd->carr_coll = 0x00; |
| 437 | 434 | ||
| 438 | p->scb->cbl_offset = make16(cfg_cmd); | 435 | p->scb->cbl_offset = make16(cfg_cmd); |
diff --git a/drivers/net/usb/pegasus.c b/drivers/net/usb/pegasus.c index b588c890ea70..a84ba487c713 100644 --- a/drivers/net/usb/pegasus.c +++ b/drivers/net/usb/pegasus.c | |||
| @@ -1285,6 +1285,21 @@ static void check_carrier(struct work_struct *work) | |||
| 1285 | } | 1285 | } |
| 1286 | } | 1286 | } |
| 1287 | 1287 | ||
| 1288 | static int pegasus_blacklisted(struct usb_device *udev) | ||
| 1289 | { | ||
| 1290 | struct usb_device_descriptor *udd = &udev->descriptor; | ||
| 1291 | |||
| 1292 | /* Special quirk to keep the driver from handling the Belkin Bluetooth | ||
| 1293 | * dongle which happens to have the same ID. | ||
| 1294 | */ | ||
| 1295 | if ((udd->idVendor == VENDOR_BELKIN && udd->idProduct == 0x0121) && | ||
| 1296 | (udd->bDeviceClass == USB_CLASS_WIRELESS_CONTROLLER) && | ||
| 1297 | (udd->bDeviceProtocol == 1)) | ||
| 1298 | return 1; | ||
| 1299 | |||
| 1300 | return 0; | ||
| 1301 | } | ||
| 1302 | |||
| 1288 | static int pegasus_probe(struct usb_interface *intf, | 1303 | static int pegasus_probe(struct usb_interface *intf, |
| 1289 | const struct usb_device_id *id) | 1304 | const struct usb_device_id *id) |
| 1290 | { | 1305 | { |
| @@ -1296,6 +1311,12 @@ static int pegasus_probe(struct usb_interface *intf, | |||
| 1296 | DECLARE_MAC_BUF(mac); | 1311 | DECLARE_MAC_BUF(mac); |
| 1297 | 1312 | ||
| 1298 | usb_get_dev(dev); | 1313 | usb_get_dev(dev); |
| 1314 | |||
| 1315 | if (pegasus_blacklisted(dev)) { | ||
| 1316 | res = -ENODEV; | ||
| 1317 | goto out; | ||
| 1318 | } | ||
| 1319 | |||
| 1299 | net = alloc_etherdev(sizeof(struct pegasus)); | 1320 | net = alloc_etherdev(sizeof(struct pegasus)); |
| 1300 | if (!net) { | 1321 | if (!net) { |
| 1301 | dev_err(&intf->dev, "can't allocate %s\n", "device"); | 1322 | dev_err(&intf->dev, "can't allocate %s\n", "device"); |
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index 370ce30f2f45..007c12970065 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c | |||
| @@ -662,6 +662,10 @@ static void velocity_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid | |||
| 662 | spin_unlock_irq(&vptr->lock); | 662 | spin_unlock_irq(&vptr->lock); |
| 663 | } | 663 | } |
| 664 | 664 | ||
| 665 | static void velocity_init_rx_ring_indexes(struct velocity_info *vptr) | ||
| 666 | { | ||
| 667 | vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0; | ||
| 668 | } | ||
| 665 | 669 | ||
| 666 | /** | 670 | /** |
| 667 | * velocity_rx_reset - handle a receive reset | 671 | * velocity_rx_reset - handle a receive reset |
| @@ -677,16 +681,16 @@ static void velocity_rx_reset(struct velocity_info *vptr) | |||
| 677 | struct mac_regs __iomem * regs = vptr->mac_regs; | 681 | struct mac_regs __iomem * regs = vptr->mac_regs; |
| 678 | int i; | 682 | int i; |
| 679 | 683 | ||
| 680 | vptr->rd_dirty = vptr->rd_filled = vptr->rd_curr = 0; | 684 | velocity_init_rx_ring_indexes(vptr); |
| 681 | 685 | ||
| 682 | /* | 686 | /* |
| 683 | * Init state, all RD entries belong to the NIC | 687 | * Init state, all RD entries belong to the NIC |
| 684 | */ | 688 | */ |
| 685 | for (i = 0; i < vptr->options.numrx; ++i) | 689 | for (i = 0; i < vptr->options.numrx; ++i) |
| 686 | vptr->rd_ring[i].rdesc0.len |= OWNED_BY_NIC; | 690 | vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC; |
| 687 | 691 | ||
| 688 | writew(vptr->options.numrx, ®s->RBRDU); | 692 | writew(vptr->options.numrx, ®s->RBRDU); |
| 689 | writel(vptr->rd_pool_dma, ®s->RDBaseLo); | 693 | writel(vptr->rx.pool_dma, ®s->RDBaseLo); |
| 690 | writew(0, ®s->RDIdx); | 694 | writew(0, ®s->RDIdx); |
| 691 | writew(vptr->options.numrx - 1, ®s->RDCSize); | 695 | writew(vptr->options.numrx - 1, ®s->RDCSize); |
| 692 | } | 696 | } |
| @@ -779,15 +783,15 @@ static void velocity_init_registers(struct velocity_info *vptr, | |||
| 779 | 783 | ||
| 780 | vptr->int_mask = INT_MASK_DEF; | 784 | vptr->int_mask = INT_MASK_DEF; |
| 781 | 785 | ||
| 782 | writel(vptr->rd_pool_dma, ®s->RDBaseLo); | 786 | writel(vptr->rx.pool_dma, ®s->RDBaseLo); |
| 783 | writew(vptr->options.numrx - 1, ®s->RDCSize); | 787 | writew(vptr->options.numrx - 1, ®s->RDCSize); |
| 784 | mac_rx_queue_run(regs); | 788 | mac_rx_queue_run(regs); |
| 785 | mac_rx_queue_wake(regs); | 789 | mac_rx_queue_wake(regs); |
| 786 | 790 | ||
| 787 | writew(vptr->options.numtx - 1, ®s->TDCSize); | 791 | writew(vptr->options.numtx - 1, ®s->TDCSize); |
| 788 | 792 | ||
| 789 | for (i = 0; i < vptr->num_txq; i++) { | 793 | for (i = 0; i < vptr->tx.numq; i++) { |
| 790 | writel(vptr->td_pool_dma[i], ®s->TDBaseLo[i]); | 794 | writel(vptr->tx.pool_dma[i], ®s->TDBaseLo[i]); |
| 791 | mac_tx_queue_run(regs, i); | 795 | mac_tx_queue_run(regs, i); |
| 792 | } | 796 | } |
| 793 | 797 | ||
| @@ -1047,7 +1051,7 @@ static void __devinit velocity_init_info(struct pci_dev *pdev, | |||
| 1047 | 1051 | ||
| 1048 | vptr->pdev = pdev; | 1052 | vptr->pdev = pdev; |
| 1049 | vptr->chip_id = info->chip_id; | 1053 | vptr->chip_id = info->chip_id; |
| 1050 | vptr->num_txq = info->txqueue; | 1054 | vptr->tx.numq = info->txqueue; |
| 1051 | vptr->multicast_limit = MCAM_SIZE; | 1055 | vptr->multicast_limit = MCAM_SIZE; |
| 1052 | spin_lock_init(&vptr->lock); | 1056 | spin_lock_init(&vptr->lock); |
| 1053 | INIT_LIST_HEAD(&vptr->list); | 1057 | INIT_LIST_HEAD(&vptr->list); |
| @@ -1093,14 +1097,14 @@ static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pc | |||
| 1093 | } | 1097 | } |
| 1094 | 1098 | ||
| 1095 | /** | 1099 | /** |
| 1096 | * velocity_init_rings - set up DMA rings | 1100 | * velocity_init_dma_rings - set up DMA rings |
| 1097 | * @vptr: Velocity to set up | 1101 | * @vptr: Velocity to set up |
| 1098 | * | 1102 | * |
| 1099 | * Allocate PCI mapped DMA rings for the receive and transmit layer | 1103 | * Allocate PCI mapped DMA rings for the receive and transmit layer |
| 1100 | * to use. | 1104 | * to use. |
| 1101 | */ | 1105 | */ |
| 1102 | 1106 | ||
| 1103 | static int velocity_init_rings(struct velocity_info *vptr) | 1107 | static int velocity_init_dma_rings(struct velocity_info *vptr) |
| 1104 | { | 1108 | { |
| 1105 | struct velocity_opt *opt = &vptr->options; | 1109 | struct velocity_opt *opt = &vptr->options; |
| 1106 | const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc); | 1110 | const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc); |
| @@ -1116,7 +1120,7 @@ static int velocity_init_rings(struct velocity_info *vptr) | |||
| 1116 | * pci_alloc_consistent() fulfills the requirement for 64 bytes | 1120 | * pci_alloc_consistent() fulfills the requirement for 64 bytes |
| 1117 | * alignment | 1121 | * alignment |
| 1118 | */ | 1122 | */ |
| 1119 | pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->num_txq + | 1123 | pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq + |
| 1120 | rx_ring_size, &pool_dma); | 1124 | rx_ring_size, &pool_dma); |
| 1121 | if (!pool) { | 1125 | if (!pool) { |
| 1122 | dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n", | 1126 | dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n", |
| @@ -1124,15 +1128,15 @@ static int velocity_init_rings(struct velocity_info *vptr) | |||
| 1124 | return -ENOMEM; | 1128 | return -ENOMEM; |
| 1125 | } | 1129 | } |
| 1126 | 1130 | ||
| 1127 | vptr->rd_ring = pool; | 1131 | vptr->rx.ring = pool; |
| 1128 | vptr->rd_pool_dma = pool_dma; | 1132 | vptr->rx.pool_dma = pool_dma; |
| 1129 | 1133 | ||
| 1130 | pool += rx_ring_size; | 1134 | pool += rx_ring_size; |
| 1131 | pool_dma += rx_ring_size; | 1135 | pool_dma += rx_ring_size; |
| 1132 | 1136 | ||
| 1133 | for (i = 0; i < vptr->num_txq; i++) { | 1137 | for (i = 0; i < vptr->tx.numq; i++) { |
| 1134 | vptr->td_rings[i] = pool; | 1138 | vptr->tx.rings[i] = pool; |
| 1135 | vptr->td_pool_dma[i] = pool_dma; | 1139 | vptr->tx.pool_dma[i] = pool_dma; |
| 1136 | pool += tx_ring_size; | 1140 | pool += tx_ring_size; |
| 1137 | pool_dma += tx_ring_size; | 1141 | pool_dma += tx_ring_size; |
| 1138 | } | 1142 | } |
| @@ -1141,18 +1145,18 @@ static int velocity_init_rings(struct velocity_info *vptr) | |||
| 1141 | } | 1145 | } |
| 1142 | 1146 | ||
| 1143 | /** | 1147 | /** |
| 1144 | * velocity_free_rings - free PCI ring pointers | 1148 | * velocity_free_dma_rings - free PCI ring pointers |
| 1145 | * @vptr: Velocity to free from | 1149 | * @vptr: Velocity to free from |
| 1146 | * | 1150 | * |
| 1147 | * Clean up the PCI ring buffers allocated to this velocity. | 1151 | * Clean up the PCI ring buffers allocated to this velocity. |
| 1148 | */ | 1152 | */ |
| 1149 | 1153 | ||
| 1150 | static void velocity_free_rings(struct velocity_info *vptr) | 1154 | static void velocity_free_dma_rings(struct velocity_info *vptr) |
| 1151 | { | 1155 | { |
| 1152 | const int size = vptr->options.numrx * sizeof(struct rx_desc) + | 1156 | const int size = vptr->options.numrx * sizeof(struct rx_desc) + |
| 1153 | vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq; | 1157 | vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq; |
| 1154 | 1158 | ||
| 1155 | pci_free_consistent(vptr->pdev, size, vptr->rd_ring, vptr->rd_pool_dma); | 1159 | pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma); |
| 1156 | } | 1160 | } |
| 1157 | 1161 | ||
| 1158 | static void velocity_give_many_rx_descs(struct velocity_info *vptr) | 1162 | static void velocity_give_many_rx_descs(struct velocity_info *vptr) |
| @@ -1164,44 +1168,44 @@ static void velocity_give_many_rx_descs(struct velocity_info *vptr) | |||
| 1164 | * RD number must be equal to 4X per hardware spec | 1168 | * RD number must be equal to 4X per hardware spec |
| 1165 | * (programming guide rev 1.20, p.13) | 1169 | * (programming guide rev 1.20, p.13) |
| 1166 | */ | 1170 | */ |
| 1167 | if (vptr->rd_filled < 4) | 1171 | if (vptr->rx.filled < 4) |
| 1168 | return; | 1172 | return; |
| 1169 | 1173 | ||
| 1170 | wmb(); | 1174 | wmb(); |
| 1171 | 1175 | ||
| 1172 | unusable = vptr->rd_filled & 0x0003; | 1176 | unusable = vptr->rx.filled & 0x0003; |
| 1173 | dirty = vptr->rd_dirty - unusable; | 1177 | dirty = vptr->rx.dirty - unusable; |
| 1174 | for (avail = vptr->rd_filled & 0xfffc; avail; avail--) { | 1178 | for (avail = vptr->rx.filled & 0xfffc; avail; avail--) { |
| 1175 | dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1; | 1179 | dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1; |
| 1176 | vptr->rd_ring[dirty].rdesc0.len |= OWNED_BY_NIC; | 1180 | vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC; |
| 1177 | } | 1181 | } |
| 1178 | 1182 | ||
| 1179 | writew(vptr->rd_filled & 0xfffc, ®s->RBRDU); | 1183 | writew(vptr->rx.filled & 0xfffc, ®s->RBRDU); |
| 1180 | vptr->rd_filled = unusable; | 1184 | vptr->rx.filled = unusable; |
| 1181 | } | 1185 | } |
| 1182 | 1186 | ||
| 1183 | static int velocity_rx_refill(struct velocity_info *vptr) | 1187 | static int velocity_rx_refill(struct velocity_info *vptr) |
| 1184 | { | 1188 | { |
| 1185 | int dirty = vptr->rd_dirty, done = 0; | 1189 | int dirty = vptr->rx.dirty, done = 0; |
| 1186 | 1190 | ||
| 1187 | do { | 1191 | do { |
| 1188 | struct rx_desc *rd = vptr->rd_ring + dirty; | 1192 | struct rx_desc *rd = vptr->rx.ring + dirty; |
| 1189 | 1193 | ||
| 1190 | /* Fine for an all zero Rx desc at init time as well */ | 1194 | /* Fine for an all zero Rx desc at init time as well */ |
| 1191 | if (rd->rdesc0.len & OWNED_BY_NIC) | 1195 | if (rd->rdesc0.len & OWNED_BY_NIC) |
| 1192 | break; | 1196 | break; |
| 1193 | 1197 | ||
| 1194 | if (!vptr->rd_info[dirty].skb) { | 1198 | if (!vptr->rx.info[dirty].skb) { |
| 1195 | if (velocity_alloc_rx_buf(vptr, dirty) < 0) | 1199 | if (velocity_alloc_rx_buf(vptr, dirty) < 0) |
| 1196 | break; | 1200 | break; |
| 1197 | } | 1201 | } |
| 1198 | done++; | 1202 | done++; |
| 1199 | dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0; | 1203 | dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0; |
| 1200 | } while (dirty != vptr->rd_curr); | 1204 | } while (dirty != vptr->rx.curr); |
| 1201 | 1205 | ||
| 1202 | if (done) { | 1206 | if (done) { |
| 1203 | vptr->rd_dirty = dirty; | 1207 | vptr->rx.dirty = dirty; |
| 1204 | vptr->rd_filled += done; | 1208 | vptr->rx.filled += done; |
| 1205 | } | 1209 | } |
| 1206 | 1210 | ||
| 1207 | return done; | 1211 | return done; |
| @@ -1209,7 +1213,7 @@ static int velocity_rx_refill(struct velocity_info *vptr) | |||
| 1209 | 1213 | ||
| 1210 | static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu) | 1214 | static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu) |
| 1211 | { | 1215 | { |
| 1212 | vptr->rx_buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32; | 1216 | vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32; |
| 1213 | } | 1217 | } |
| 1214 | 1218 | ||
| 1215 | /** | 1219 | /** |
| @@ -1224,12 +1228,12 @@ static int velocity_init_rd_ring(struct velocity_info *vptr) | |||
| 1224 | { | 1228 | { |
| 1225 | int ret = -ENOMEM; | 1229 | int ret = -ENOMEM; |
| 1226 | 1230 | ||
| 1227 | vptr->rd_info = kcalloc(vptr->options.numrx, | 1231 | vptr->rx.info = kcalloc(vptr->options.numrx, |
| 1228 | sizeof(struct velocity_rd_info), GFP_KERNEL); | 1232 | sizeof(struct velocity_rd_info), GFP_KERNEL); |
| 1229 | if (!vptr->rd_info) | 1233 | if (!vptr->rx.info) |
| 1230 | goto out; | 1234 | goto out; |
| 1231 | 1235 | ||
| 1232 | vptr->rd_filled = vptr->rd_dirty = vptr->rd_curr = 0; | 1236 | velocity_init_rx_ring_indexes(vptr); |
| 1233 | 1237 | ||
| 1234 | if (velocity_rx_refill(vptr) != vptr->options.numrx) { | 1238 | if (velocity_rx_refill(vptr) != vptr->options.numrx) { |
| 1235 | VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR | 1239 | VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR |
| @@ -1255,18 +1259,18 @@ static void velocity_free_rd_ring(struct velocity_info *vptr) | |||
| 1255 | { | 1259 | { |
| 1256 | int i; | 1260 | int i; |
| 1257 | 1261 | ||
| 1258 | if (vptr->rd_info == NULL) | 1262 | if (vptr->rx.info == NULL) |
| 1259 | return; | 1263 | return; |
| 1260 | 1264 | ||
| 1261 | for (i = 0; i < vptr->options.numrx; i++) { | 1265 | for (i = 0; i < vptr->options.numrx; i++) { |
| 1262 | struct velocity_rd_info *rd_info = &(vptr->rd_info[i]); | 1266 | struct velocity_rd_info *rd_info = &(vptr->rx.info[i]); |
| 1263 | struct rx_desc *rd = vptr->rd_ring + i; | 1267 | struct rx_desc *rd = vptr->rx.ring + i; |
| 1264 | 1268 | ||
| 1265 | memset(rd, 0, sizeof(*rd)); | 1269 | memset(rd, 0, sizeof(*rd)); |
| 1266 | 1270 | ||
| 1267 | if (!rd_info->skb) | 1271 | if (!rd_info->skb) |
| 1268 | continue; | 1272 | continue; |
| 1269 | pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx_buf_sz, | 1273 | pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz, |
| 1270 | PCI_DMA_FROMDEVICE); | 1274 | PCI_DMA_FROMDEVICE); |
| 1271 | rd_info->skb_dma = (dma_addr_t) NULL; | 1275 | rd_info->skb_dma = (dma_addr_t) NULL; |
| 1272 | 1276 | ||
| @@ -1274,8 +1278,8 @@ static void velocity_free_rd_ring(struct velocity_info *vptr) | |||
| 1274 | rd_info->skb = NULL; | 1278 | rd_info->skb = NULL; |
| 1275 | } | 1279 | } |
| 1276 | 1280 | ||
| 1277 | kfree(vptr->rd_info); | 1281 | kfree(vptr->rx.info); |
| 1278 | vptr->rd_info = NULL; | 1282 | vptr->rx.info = NULL; |
| 1279 | } | 1283 | } |
| 1280 | 1284 | ||
| 1281 | /** | 1285 | /** |
| @@ -1293,19 +1297,19 @@ static int velocity_init_td_ring(struct velocity_info *vptr) | |||
| 1293 | unsigned int j; | 1297 | unsigned int j; |
| 1294 | 1298 | ||
| 1295 | /* Init the TD ring entries */ | 1299 | /* Init the TD ring entries */ |
| 1296 | for (j = 0; j < vptr->num_txq; j++) { | 1300 | for (j = 0; j < vptr->tx.numq; j++) { |
| 1297 | curr = vptr->td_pool_dma[j]; | 1301 | curr = vptr->tx.pool_dma[j]; |
| 1298 | 1302 | ||
| 1299 | vptr->td_infos[j] = kcalloc(vptr->options.numtx, | 1303 | vptr->tx.infos[j] = kcalloc(vptr->options.numtx, |
| 1300 | sizeof(struct velocity_td_info), | 1304 | sizeof(struct velocity_td_info), |
| 1301 | GFP_KERNEL); | 1305 | GFP_KERNEL); |
| 1302 | if (!vptr->td_infos[j]) { | 1306 | if (!vptr->tx.infos[j]) { |
| 1303 | while(--j >= 0) | 1307 | while(--j >= 0) |
| 1304 | kfree(vptr->td_infos[j]); | 1308 | kfree(vptr->tx.infos[j]); |
| 1305 | return -ENOMEM; | 1309 | return -ENOMEM; |
| 1306 | } | 1310 | } |
| 1307 | 1311 | ||
| 1308 | vptr->td_tail[j] = vptr->td_curr[j] = vptr->td_used[j] = 0; | 1312 | vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0; |
| 1309 | } | 1313 | } |
| 1310 | return 0; | 1314 | return 0; |
| 1311 | } | 1315 | } |
| @@ -1317,7 +1321,7 @@ static int velocity_init_td_ring(struct velocity_info *vptr) | |||
| 1317 | static void velocity_free_td_ring_entry(struct velocity_info *vptr, | 1321 | static void velocity_free_td_ring_entry(struct velocity_info *vptr, |
| 1318 | int q, int n) | 1322 | int q, int n) |
| 1319 | { | 1323 | { |
| 1320 | struct velocity_td_info * td_info = &(vptr->td_infos[q][n]); | 1324 | struct velocity_td_info * td_info = &(vptr->tx.infos[q][n]); |
| 1321 | int i; | 1325 | int i; |
| 1322 | 1326 | ||
| 1323 | if (td_info == NULL) | 1327 | if (td_info == NULL) |
| @@ -1349,15 +1353,15 @@ static void velocity_free_td_ring(struct velocity_info *vptr) | |||
| 1349 | { | 1353 | { |
| 1350 | int i, j; | 1354 | int i, j; |
| 1351 | 1355 | ||
| 1352 | for (j = 0; j < vptr->num_txq; j++) { | 1356 | for (j = 0; j < vptr->tx.numq; j++) { |
| 1353 | if (vptr->td_infos[j] == NULL) | 1357 | if (vptr->tx.infos[j] == NULL) |
| 1354 | continue; | 1358 | continue; |
| 1355 | for (i = 0; i < vptr->options.numtx; i++) { | 1359 | for (i = 0; i < vptr->options.numtx; i++) { |
| 1356 | velocity_free_td_ring_entry(vptr, j, i); | 1360 | velocity_free_td_ring_entry(vptr, j, i); |
| 1357 | 1361 | ||
| 1358 | } | 1362 | } |
| 1359 | kfree(vptr->td_infos[j]); | 1363 | kfree(vptr->tx.infos[j]); |
| 1360 | vptr->td_infos[j] = NULL; | 1364 | vptr->tx.infos[j] = NULL; |
| 1361 | } | 1365 | } |
| 1362 | } | 1366 | } |
| 1363 | 1367 | ||
| @@ -1374,13 +1378,13 @@ static void velocity_free_td_ring(struct velocity_info *vptr) | |||
| 1374 | static int velocity_rx_srv(struct velocity_info *vptr, int status) | 1378 | static int velocity_rx_srv(struct velocity_info *vptr, int status) |
| 1375 | { | 1379 | { |
| 1376 | struct net_device_stats *stats = &vptr->stats; | 1380 | struct net_device_stats *stats = &vptr->stats; |
| 1377 | int rd_curr = vptr->rd_curr; | 1381 | int rd_curr = vptr->rx.curr; |
| 1378 | int works = 0; | 1382 | int works = 0; |
| 1379 | 1383 | ||
| 1380 | do { | 1384 | do { |
| 1381 | struct rx_desc *rd = vptr->rd_ring + rd_curr; | 1385 | struct rx_desc *rd = vptr->rx.ring + rd_curr; |
| 1382 | 1386 | ||
| 1383 | if (!vptr->rd_info[rd_curr].skb) | 1387 | if (!vptr->rx.info[rd_curr].skb) |
| 1384 | break; | 1388 | break; |
| 1385 | 1389 | ||
| 1386 | if (rd->rdesc0.len & OWNED_BY_NIC) | 1390 | if (rd->rdesc0.len & OWNED_BY_NIC) |
| @@ -1412,7 +1416,7 @@ static int velocity_rx_srv(struct velocity_info *vptr, int status) | |||
| 1412 | rd_curr = 0; | 1416 | rd_curr = 0; |
| 1413 | } while (++works <= 15); | 1417 | } while (++works <= 15); |
| 1414 | 1418 | ||
| 1415 | vptr->rd_curr = rd_curr; | 1419 | vptr->rx.curr = rd_curr; |
| 1416 | 1420 | ||
| 1417 | if ((works > 0) && (velocity_rx_refill(vptr) > 0)) | 1421 | if ((works > 0) && (velocity_rx_refill(vptr) > 0)) |
| 1418 | velocity_give_many_rx_descs(vptr); | 1422 | velocity_give_many_rx_descs(vptr); |
| @@ -1510,8 +1514,8 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx) | |||
| 1510 | { | 1514 | { |
| 1511 | void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int); | 1515 | void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int); |
| 1512 | struct net_device_stats *stats = &vptr->stats; | 1516 | struct net_device_stats *stats = &vptr->stats; |
| 1513 | struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]); | 1517 | struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]); |
| 1514 | struct rx_desc *rd = &(vptr->rd_ring[idx]); | 1518 | struct rx_desc *rd = &(vptr->rx.ring[idx]); |
| 1515 | int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff; | 1519 | int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff; |
| 1516 | struct sk_buff *skb; | 1520 | struct sk_buff *skb; |
| 1517 | 1521 | ||
| @@ -1527,7 +1531,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx) | |||
| 1527 | skb = rd_info->skb; | 1531 | skb = rd_info->skb; |
| 1528 | 1532 | ||
| 1529 | pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma, | 1533 | pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma, |
| 1530 | vptr->rx_buf_sz, PCI_DMA_FROMDEVICE); | 1534 | vptr->rx.buf_sz, PCI_DMA_FROMDEVICE); |
| 1531 | 1535 | ||
| 1532 | /* | 1536 | /* |
| 1533 | * Drop frame not meeting IEEE 802.3 | 1537 | * Drop frame not meeting IEEE 802.3 |
| @@ -1550,7 +1554,7 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx) | |||
| 1550 | rd_info->skb = NULL; | 1554 | rd_info->skb = NULL; |
| 1551 | } | 1555 | } |
| 1552 | 1556 | ||
| 1553 | pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx_buf_sz, | 1557 | pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz, |
| 1554 | PCI_DMA_FROMDEVICE); | 1558 | PCI_DMA_FROMDEVICE); |
| 1555 | 1559 | ||
| 1556 | skb_put(skb, pkt_len - 4); | 1560 | skb_put(skb, pkt_len - 4); |
| @@ -1580,10 +1584,10 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx) | |||
| 1580 | 1584 | ||
| 1581 | static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx) | 1585 | static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx) |
| 1582 | { | 1586 | { |
| 1583 | struct rx_desc *rd = &(vptr->rd_ring[idx]); | 1587 | struct rx_desc *rd = &(vptr->rx.ring[idx]); |
| 1584 | struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]); | 1588 | struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]); |
| 1585 | 1589 | ||
| 1586 | rd_info->skb = netdev_alloc_skb(vptr->dev, vptr->rx_buf_sz + 64); | 1590 | rd_info->skb = dev_alloc_skb(vptr->rx.buf_sz + 64); |
| 1587 | if (rd_info->skb == NULL) | 1591 | if (rd_info->skb == NULL) |
| 1588 | return -ENOMEM; | 1592 | return -ENOMEM; |
| 1589 | 1593 | ||
| @@ -1592,14 +1596,15 @@ static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx) | |||
| 1592 | * 64byte alignment. | 1596 | * 64byte alignment. |
| 1593 | */ | 1597 | */ |
| 1594 | skb_reserve(rd_info->skb, (unsigned long) rd_info->skb->data & 63); | 1598 | skb_reserve(rd_info->skb, (unsigned long) rd_info->skb->data & 63); |
| 1595 | rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data, vptr->rx_buf_sz, PCI_DMA_FROMDEVICE); | 1599 | rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data, |
| 1600 | vptr->rx.buf_sz, PCI_DMA_FROMDEVICE); | ||
| 1596 | 1601 | ||
| 1597 | /* | 1602 | /* |
| 1598 | * Fill in the descriptor to match | 1603 | * Fill in the descriptor to match |
| 1599 | */ | 1604 | */ |
| 1600 | 1605 | ||
| 1601 | *((u32 *) & (rd->rdesc0)) = 0; | 1606 | *((u32 *) & (rd->rdesc0)) = 0; |
| 1602 | rd->size = cpu_to_le16(vptr->rx_buf_sz) | RX_INTEN; | 1607 | rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN; |
| 1603 | rd->pa_low = cpu_to_le32(rd_info->skb_dma); | 1608 | rd->pa_low = cpu_to_le32(rd_info->skb_dma); |
| 1604 | rd->pa_high = 0; | 1609 | rd->pa_high = 0; |
| 1605 | return 0; | 1610 | return 0; |
| @@ -1625,15 +1630,15 @@ static int velocity_tx_srv(struct velocity_info *vptr, u32 status) | |||
| 1625 | struct velocity_td_info *tdinfo; | 1630 | struct velocity_td_info *tdinfo; |
| 1626 | struct net_device_stats *stats = &vptr->stats; | 1631 | struct net_device_stats *stats = &vptr->stats; |
| 1627 | 1632 | ||
| 1628 | for (qnum = 0; qnum < vptr->num_txq; qnum++) { | 1633 | for (qnum = 0; qnum < vptr->tx.numq; qnum++) { |
| 1629 | for (idx = vptr->td_tail[qnum]; vptr->td_used[qnum] > 0; | 1634 | for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0; |
| 1630 | idx = (idx + 1) % vptr->options.numtx) { | 1635 | idx = (idx + 1) % vptr->options.numtx) { |
| 1631 | 1636 | ||
| 1632 | /* | 1637 | /* |
| 1633 | * Get Tx Descriptor | 1638 | * Get Tx Descriptor |
| 1634 | */ | 1639 | */ |
| 1635 | td = &(vptr->td_rings[qnum][idx]); | 1640 | td = &(vptr->tx.rings[qnum][idx]); |
| 1636 | tdinfo = &(vptr->td_infos[qnum][idx]); | 1641 | tdinfo = &(vptr->tx.infos[qnum][idx]); |
| 1637 | 1642 | ||
| 1638 | if (td->tdesc0.len & OWNED_BY_NIC) | 1643 | if (td->tdesc0.len & OWNED_BY_NIC) |
| 1639 | break; | 1644 | break; |
| @@ -1657,9 +1662,9 @@ static int velocity_tx_srv(struct velocity_info *vptr, u32 status) | |||
| 1657 | stats->tx_bytes += tdinfo->skb->len; | 1662 | stats->tx_bytes += tdinfo->skb->len; |
| 1658 | } | 1663 | } |
| 1659 | velocity_free_tx_buf(vptr, tdinfo); | 1664 | velocity_free_tx_buf(vptr, tdinfo); |
| 1660 | vptr->td_used[qnum]--; | 1665 | vptr->tx.used[qnum]--; |
| 1661 | } | 1666 | } |
| 1662 | vptr->td_tail[qnum] = idx; | 1667 | vptr->tx.tail[qnum] = idx; |
| 1663 | 1668 | ||
| 1664 | if (AVAIL_TD(vptr, qnum) < 1) { | 1669 | if (AVAIL_TD(vptr, qnum) < 1) { |
| 1665 | full = 1; | 1670 | full = 1; |
| @@ -1846,6 +1851,40 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_ | |||
| 1846 | tdinfo->skb = NULL; | 1851 | tdinfo->skb = NULL; |
| 1847 | } | 1852 | } |
| 1848 | 1853 | ||
| 1854 | static int velocity_init_rings(struct velocity_info *vptr, int mtu) | ||
| 1855 | { | ||
| 1856 | int ret; | ||
| 1857 | |||
| 1858 | velocity_set_rxbufsize(vptr, mtu); | ||
| 1859 | |||
| 1860 | ret = velocity_init_dma_rings(vptr); | ||
| 1861 | if (ret < 0) | ||
| 1862 | goto out; | ||
| 1863 | |||
| 1864 | ret = velocity_init_rd_ring(vptr); | ||
| 1865 | if (ret < 0) | ||
| 1866 | goto err_free_dma_rings_0; | ||
| 1867 | |||
| 1868 | ret = velocity_init_td_ring(vptr); | ||
| 1869 | if (ret < 0) | ||
| 1870 | goto err_free_rd_ring_1; | ||
| 1871 | out: | ||
| 1872 | return ret; | ||
| 1873 | |||
| 1874 | err_free_rd_ring_1: | ||
| 1875 | velocity_free_rd_ring(vptr); | ||
| 1876 | err_free_dma_rings_0: | ||
| 1877 | velocity_free_dma_rings(vptr); | ||
| 1878 | goto out; | ||
| 1879 | } | ||
| 1880 | |||
| 1881 | static void velocity_free_rings(struct velocity_info *vptr) | ||
| 1882 | { | ||
| 1883 | velocity_free_td_ring(vptr); | ||
| 1884 | velocity_free_rd_ring(vptr); | ||
| 1885 | velocity_free_dma_rings(vptr); | ||
| 1886 | } | ||
| 1887 | |||
| 1849 | /** | 1888 | /** |
| 1850 | * velocity_open - interface activation callback | 1889 | * velocity_open - interface activation callback |
| 1851 | * @dev: network layer device to open | 1890 | * @dev: network layer device to open |
| @@ -1862,20 +1901,10 @@ static int velocity_open(struct net_device *dev) | |||
| 1862 | struct velocity_info *vptr = netdev_priv(dev); | 1901 | struct velocity_info *vptr = netdev_priv(dev); |
| 1863 | int ret; | 1902 | int ret; |
| 1864 | 1903 | ||
| 1865 | velocity_set_rxbufsize(vptr, dev->mtu); | 1904 | ret = velocity_init_rings(vptr, dev->mtu); |
| 1866 | |||
| 1867 | ret = velocity_init_rings(vptr); | ||
| 1868 | if (ret < 0) | 1905 | if (ret < 0) |
| 1869 | goto out; | 1906 | goto out; |
| 1870 | 1907 | ||
| 1871 | ret = velocity_init_rd_ring(vptr); | ||
| 1872 | if (ret < 0) | ||
| 1873 | goto err_free_desc_rings; | ||
| 1874 | |||
| 1875 | ret = velocity_init_td_ring(vptr); | ||
| 1876 | if (ret < 0) | ||
| 1877 | goto err_free_rd_ring; | ||
| 1878 | |||
| 1879 | /* Ensure chip is running */ | 1908 | /* Ensure chip is running */ |
| 1880 | pci_set_power_state(vptr->pdev, PCI_D0); | 1909 | pci_set_power_state(vptr->pdev, PCI_D0); |
| 1881 | 1910 | ||
| @@ -1888,7 +1917,8 @@ static int velocity_open(struct net_device *dev) | |||
| 1888 | if (ret < 0) { | 1917 | if (ret < 0) { |
| 1889 | /* Power down the chip */ | 1918 | /* Power down the chip */ |
| 1890 | pci_set_power_state(vptr->pdev, PCI_D3hot); | 1919 | pci_set_power_state(vptr->pdev, PCI_D3hot); |
| 1891 | goto err_free_td_ring; | 1920 | velocity_free_rings(vptr); |
| 1921 | goto out; | ||
| 1892 | } | 1922 | } |
| 1893 | 1923 | ||
| 1894 | mac_enable_int(vptr->mac_regs); | 1924 | mac_enable_int(vptr->mac_regs); |
| @@ -1896,14 +1926,6 @@ static int velocity_open(struct net_device *dev) | |||
| 1896 | vptr->flags |= VELOCITY_FLAGS_OPENED; | 1926 | vptr->flags |= VELOCITY_FLAGS_OPENED; |
| 1897 | out: | 1927 | out: |
| 1898 | return ret; | 1928 | return ret; |
| 1899 | |||
| 1900 | err_free_td_ring: | ||
| 1901 | velocity_free_td_ring(vptr); | ||
| 1902 | err_free_rd_ring: | ||
| 1903 | velocity_free_rd_ring(vptr); | ||
| 1904 | err_free_desc_rings: | ||
| 1905 | velocity_free_rings(vptr); | ||
| 1906 | goto out; | ||
| 1907 | } | 1929 | } |
| 1908 | 1930 | ||
| 1909 | /** | 1931 | /** |
| @@ -1919,50 +1941,72 @@ err_free_desc_rings: | |||
| 1919 | static int velocity_change_mtu(struct net_device *dev, int new_mtu) | 1941 | static int velocity_change_mtu(struct net_device *dev, int new_mtu) |
| 1920 | { | 1942 | { |
| 1921 | struct velocity_info *vptr = netdev_priv(dev); | 1943 | struct velocity_info *vptr = netdev_priv(dev); |
| 1922 | unsigned long flags; | ||
| 1923 | int oldmtu = dev->mtu; | ||
| 1924 | int ret = 0; | 1944 | int ret = 0; |
| 1925 | 1945 | ||
| 1926 | if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) { | 1946 | if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) { |
| 1927 | VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n", | 1947 | VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n", |
| 1928 | vptr->dev->name); | 1948 | vptr->dev->name); |
| 1929 | return -EINVAL; | 1949 | ret = -EINVAL; |
| 1950 | goto out_0; | ||
| 1930 | } | 1951 | } |
| 1931 | 1952 | ||
| 1932 | if (!netif_running(dev)) { | 1953 | if (!netif_running(dev)) { |
| 1933 | dev->mtu = new_mtu; | 1954 | dev->mtu = new_mtu; |
| 1934 | return 0; | 1955 | goto out_0; |
| 1935 | } | 1956 | } |
| 1936 | 1957 | ||
| 1937 | if (new_mtu != oldmtu) { | 1958 | if (dev->mtu != new_mtu) { |
| 1959 | struct velocity_info *tmp_vptr; | ||
| 1960 | unsigned long flags; | ||
| 1961 | struct rx_info rx; | ||
| 1962 | struct tx_info tx; | ||
| 1963 | |||
| 1964 | tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL); | ||
| 1965 | if (!tmp_vptr) { | ||
| 1966 | ret = -ENOMEM; | ||
| 1967 | goto out_0; | ||
| 1968 | } | ||
| 1969 | |||
| 1970 | tmp_vptr->dev = dev; | ||
| 1971 | tmp_vptr->pdev = vptr->pdev; | ||
| 1972 | tmp_vptr->options = vptr->options; | ||
| 1973 | tmp_vptr->tx.numq = vptr->tx.numq; | ||
| 1974 | |||
| 1975 | ret = velocity_init_rings(tmp_vptr, new_mtu); | ||
| 1976 | if (ret < 0) | ||
| 1977 | goto out_free_tmp_vptr_1; | ||
| 1978 | |||
| 1938 | spin_lock_irqsave(&vptr->lock, flags); | 1979 | spin_lock_irqsave(&vptr->lock, flags); |
| 1939 | 1980 | ||
| 1940 | netif_stop_queue(dev); | 1981 | netif_stop_queue(dev); |
| 1941 | velocity_shutdown(vptr); | 1982 | velocity_shutdown(vptr); |
| 1942 | 1983 | ||
| 1943 | velocity_free_td_ring(vptr); | 1984 | rx = vptr->rx; |
| 1944 | velocity_free_rd_ring(vptr); | 1985 | tx = vptr->tx; |
| 1945 | 1986 | ||
| 1946 | dev->mtu = new_mtu; | 1987 | vptr->rx = tmp_vptr->rx; |
| 1988 | vptr->tx = tmp_vptr->tx; | ||
| 1947 | 1989 | ||
| 1948 | velocity_set_rxbufsize(vptr, new_mtu); | 1990 | tmp_vptr->rx = rx; |
| 1991 | tmp_vptr->tx = tx; | ||
| 1949 | 1992 | ||
| 1950 | ret = velocity_init_rd_ring(vptr); | 1993 | dev->mtu = new_mtu; |
| 1951 | if (ret < 0) | ||
| 1952 | goto out_unlock; | ||
| 1953 | 1994 | ||
| 1954 | ret = velocity_init_td_ring(vptr); | 1995 | velocity_give_many_rx_descs(vptr); |
| 1955 | if (ret < 0) | ||
| 1956 | goto out_unlock; | ||
| 1957 | 1996 | ||
| 1958 | velocity_init_registers(vptr, VELOCITY_INIT_COLD); | 1997 | velocity_init_registers(vptr, VELOCITY_INIT_COLD); |
| 1959 | 1998 | ||
| 1960 | mac_enable_int(vptr->mac_regs); | 1999 | mac_enable_int(vptr->mac_regs); |
| 1961 | netif_start_queue(dev); | 2000 | netif_start_queue(dev); |
| 1962 | out_unlock: | 2001 | |
| 1963 | spin_unlock_irqrestore(&vptr->lock, flags); | 2002 | spin_unlock_irqrestore(&vptr->lock, flags); |
| 1964 | } | ||
| 1965 | 2003 | ||
| 2004 | velocity_free_rings(tmp_vptr); | ||
| 2005 | |||
| 2006 | out_free_tmp_vptr_1: | ||
| 2007 | kfree(tmp_vptr); | ||
| 2008 | } | ||
| 2009 | out_0: | ||
| 1966 | return ret; | 2010 | return ret; |
| 1967 | } | 2011 | } |
| 1968 | 2012 | ||
| @@ -2008,9 +2052,6 @@ static int velocity_close(struct net_device *dev) | |||
| 2008 | /* Power down the chip */ | 2052 | /* Power down the chip */ |
| 2009 | pci_set_power_state(vptr->pdev, PCI_D3hot); | 2053 | pci_set_power_state(vptr->pdev, PCI_D3hot); |
| 2010 | 2054 | ||
| 2011 | /* Free the resources */ | ||
| 2012 | velocity_free_td_ring(vptr); | ||
| 2013 | velocity_free_rd_ring(vptr); | ||
| 2014 | velocity_free_rings(vptr); | 2055 | velocity_free_rings(vptr); |
| 2015 | 2056 | ||
| 2016 | vptr->flags &= (~VELOCITY_FLAGS_OPENED); | 2057 | vptr->flags &= (~VELOCITY_FLAGS_OPENED); |
| @@ -2056,9 +2097,9 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2056 | 2097 | ||
| 2057 | spin_lock_irqsave(&vptr->lock, flags); | 2098 | spin_lock_irqsave(&vptr->lock, flags); |
| 2058 | 2099 | ||
| 2059 | index = vptr->td_curr[qnum]; | 2100 | index = vptr->tx.curr[qnum]; |
| 2060 | td_ptr = &(vptr->td_rings[qnum][index]); | 2101 | td_ptr = &(vptr->tx.rings[qnum][index]); |
| 2061 | tdinfo = &(vptr->td_infos[qnum][index]); | 2102 | tdinfo = &(vptr->tx.infos[qnum][index]); |
| 2062 | 2103 | ||
| 2063 | td_ptr->tdesc1.TCR = TCR0_TIC; | 2104 | td_ptr->tdesc1.TCR = TCR0_TIC; |
| 2064 | td_ptr->td_buf[0].size &= ~TD_QUEUE; | 2105 | td_ptr->td_buf[0].size &= ~TD_QUEUE; |
| @@ -2071,9 +2112,9 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2071 | skb_copy_from_linear_data(skb, tdinfo->buf, skb->len); | 2112 | skb_copy_from_linear_data(skb, tdinfo->buf, skb->len); |
| 2072 | tdinfo->skb_dma[0] = tdinfo->buf_dma; | 2113 | tdinfo->skb_dma[0] = tdinfo->buf_dma; |
| 2073 | td_ptr->tdesc0.len = len; | 2114 | td_ptr->tdesc0.len = len; |
| 2074 | td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]); | 2115 | td_ptr->tx.buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]); |
| 2075 | td_ptr->td_buf[0].pa_high = 0; | 2116 | td_ptr->tx.buf[0].pa_high = 0; |
| 2076 | td_ptr->td_buf[0].size = len; /* queue is 0 anyway */ | 2117 | td_ptr->tx.buf[0].size = len; /* queue is 0 anyway */ |
| 2077 | tdinfo->nskb_dma = 1; | 2118 | tdinfo->nskb_dma = 1; |
| 2078 | } else { | 2119 | } else { |
| 2079 | int i = 0; | 2120 | int i = 0; |
| @@ -2084,9 +2125,9 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2084 | td_ptr->tdesc0.len = len; | 2125 | td_ptr->tdesc0.len = len; |
| 2085 | 2126 | ||
| 2086 | /* FIXME: support 48bit DMA later */ | 2127 | /* FIXME: support 48bit DMA later */ |
| 2087 | td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma); | 2128 | td_ptr->tx.buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma); |
| 2088 | td_ptr->td_buf[i].pa_high = 0; | 2129 | td_ptr->tx.buf[i].pa_high = 0; |
| 2089 | td_ptr->td_buf[i].size = cpu_to_le16(skb_headlen(skb)); | 2130 | td_ptr->tx.buf[i].size = cpu_to_le16(skb_headlen(skb)); |
| 2090 | 2131 | ||
| 2091 | for (i = 0; i < nfrags; i++) { | 2132 | for (i = 0; i < nfrags; i++) { |
| 2092 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | 2133 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| @@ -2094,9 +2135,9 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2094 | 2135 | ||
| 2095 | tdinfo->skb_dma[i + 1] = pci_map_single(vptr->pdev, addr, frag->size, PCI_DMA_TODEVICE); | 2136 | tdinfo->skb_dma[i + 1] = pci_map_single(vptr->pdev, addr, frag->size, PCI_DMA_TODEVICE); |
| 2096 | 2137 | ||
| 2097 | td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]); | 2138 | td_ptr->tx.buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]); |
| 2098 | td_ptr->td_buf[i + 1].pa_high = 0; | 2139 | td_ptr->tx.buf[i + 1].pa_high = 0; |
| 2099 | td_ptr->td_buf[i + 1].size = cpu_to_le16(frag->size); | 2140 | td_ptr->tx.buf[i + 1].size = cpu_to_le16(frag->size); |
| 2100 | } | 2141 | } |
| 2101 | tdinfo->nskb_dma = i - 1; | 2142 | tdinfo->nskb_dma = i - 1; |
| 2102 | } | 2143 | } |
| @@ -2142,13 +2183,13 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2142 | if (prev < 0) | 2183 | if (prev < 0) |
| 2143 | prev = vptr->options.numtx - 1; | 2184 | prev = vptr->options.numtx - 1; |
| 2144 | td_ptr->tdesc0.len |= OWNED_BY_NIC; | 2185 | td_ptr->tdesc0.len |= OWNED_BY_NIC; |
| 2145 | vptr->td_used[qnum]++; | 2186 | vptr->tx.used[qnum]++; |
| 2146 | vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx; | 2187 | vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx; |
| 2147 | 2188 | ||
| 2148 | if (AVAIL_TD(vptr, qnum) < 1) | 2189 | if (AVAIL_TD(vptr, qnum) < 1) |
| 2149 | netif_stop_queue(dev); | 2190 | netif_stop_queue(dev); |
| 2150 | 2191 | ||
| 2151 | td_ptr = &(vptr->td_rings[qnum][prev]); | 2192 | td_ptr = &(vptr->tx.rings[qnum][prev]); |
| 2152 | td_ptr->td_buf[0].size |= TD_QUEUE; | 2193 | td_ptr->td_buf[0].size |= TD_QUEUE; |
| 2153 | mac_tx_queue_wake(vptr->mac_regs, qnum); | 2194 | mac_tx_queue_wake(vptr->mac_regs, qnum); |
| 2154 | } | 2195 | } |
| @@ -3405,8 +3446,8 @@ static int velocity_resume(struct pci_dev *pdev) | |||
| 3405 | 3446 | ||
| 3406 | velocity_tx_srv(vptr, 0); | 3447 | velocity_tx_srv(vptr, 0); |
| 3407 | 3448 | ||
| 3408 | for (i = 0; i < vptr->num_txq; i++) { | 3449 | for (i = 0; i < vptr->tx.numq; i++) { |
| 3409 | if (vptr->td_used[i]) { | 3450 | if (vptr->tx.used[i]) { |
| 3410 | mac_tx_queue_wake(vptr->mac_regs, i); | 3451 | mac_tx_queue_wake(vptr->mac_regs, i); |
| 3411 | } | 3452 | } |
| 3412 | } | 3453 | } |
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h index 86446147284c..1b95b04c9257 100644 --- a/drivers/net/via-velocity.h +++ b/drivers/net/via-velocity.h | |||
| @@ -1494,6 +1494,10 @@ struct velocity_opt { | |||
| 1494 | u32 flags; | 1494 | u32 flags; |
| 1495 | }; | 1495 | }; |
| 1496 | 1496 | ||
| 1497 | #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)])) | ||
| 1498 | |||
| 1499 | #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) | ||
| 1500 | |||
| 1497 | struct velocity_info { | 1501 | struct velocity_info { |
| 1498 | struct list_head list; | 1502 | struct list_head list; |
| 1499 | 1503 | ||
| @@ -1501,9 +1505,6 @@ struct velocity_info { | |||
| 1501 | struct net_device *dev; | 1505 | struct net_device *dev; |
| 1502 | struct net_device_stats stats; | 1506 | struct net_device_stats stats; |
| 1503 | 1507 | ||
| 1504 | dma_addr_t rd_pool_dma; | ||
| 1505 | dma_addr_t td_pool_dma[TX_QUEUE_NO]; | ||
| 1506 | |||
| 1507 | struct vlan_group *vlgrp; | 1508 | struct vlan_group *vlgrp; |
| 1508 | u8 ip_addr[4]; | 1509 | u8 ip_addr[4]; |
| 1509 | enum chip_type chip_id; | 1510 | enum chip_type chip_id; |
| @@ -1512,25 +1513,29 @@ struct velocity_info { | |||
| 1512 | unsigned long memaddr; | 1513 | unsigned long memaddr; |
| 1513 | unsigned long ioaddr; | 1514 | unsigned long ioaddr; |
| 1514 | 1515 | ||
| 1515 | u8 rev_id; | 1516 | struct tx_info { |
| 1516 | 1517 | int numq; | |
| 1517 | #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)])) | 1518 | |
| 1519 | /* FIXME: the locality of the data seems rather poor. */ | ||
| 1520 | int used[TX_QUEUE_NO]; | ||
| 1521 | int curr[TX_QUEUE_NO]; | ||
| 1522 | int tail[TX_QUEUE_NO]; | ||
| 1523 | struct tx_desc *rings[TX_QUEUE_NO]; | ||
| 1524 | struct velocity_td_info *infos[TX_QUEUE_NO]; | ||
| 1525 | dma_addr_t pool_dma[TX_QUEUE_NO]; | ||
| 1526 | } tx; | ||
| 1527 | |||
| 1528 | struct rx_info { | ||
| 1529 | int buf_sz; | ||
| 1530 | |||
| 1531 | int dirty; | ||
| 1532 | int curr; | ||
| 1533 | u32 filled; | ||
| 1534 | struct rx_desc *ring; | ||
| 1535 | struct velocity_rd_info *info; /* It's an array */ | ||
| 1536 | dma_addr_t pool_dma; | ||
| 1537 | } rx; | ||
| 1518 | 1538 | ||
| 1519 | int num_txq; | ||
| 1520 | |||
| 1521 | volatile int td_used[TX_QUEUE_NO]; | ||
| 1522 | int td_curr[TX_QUEUE_NO]; | ||
| 1523 | int td_tail[TX_QUEUE_NO]; | ||
| 1524 | struct tx_desc *td_rings[TX_QUEUE_NO]; | ||
| 1525 | struct velocity_td_info *td_infos[TX_QUEUE_NO]; | ||
| 1526 | |||
| 1527 | int rd_curr; | ||
| 1528 | int rd_dirty; | ||
| 1529 | u32 rd_filled; | ||
| 1530 | struct rx_desc *rd_ring; | ||
| 1531 | struct velocity_rd_info *rd_info; /* It's an array */ | ||
| 1532 | |||
| 1533 | #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) | ||
| 1534 | u32 mib_counter[MAX_HW_MIB_COUNTER]; | 1539 | u32 mib_counter[MAX_HW_MIB_COUNTER]; |
| 1535 | struct velocity_opt options; | 1540 | struct velocity_opt options; |
| 1536 | 1541 | ||
| @@ -1538,7 +1543,6 @@ struct velocity_info { | |||
| 1538 | 1543 | ||
| 1539 | u32 flags; | 1544 | u32 flags; |
| 1540 | 1545 | ||
| 1541 | int rx_buf_sz; | ||
| 1542 | u32 mii_status; | 1546 | u32 mii_status; |
| 1543 | u32 phy_id; | 1547 | u32 phy_id; |
| 1544 | int multicast_limit; | 1548 | int multicast_limit; |
| @@ -1554,8 +1558,8 @@ struct velocity_info { | |||
| 1554 | struct velocity_context context; | 1558 | struct velocity_context context; |
| 1555 | 1559 | ||
| 1556 | u32 ticks; | 1560 | u32 ticks; |
| 1557 | u32 rx_bytes; | ||
| 1558 | 1561 | ||
| 1562 | u8 rev_id; | ||
| 1559 | }; | 1563 | }; |
| 1560 | 1564 | ||
| 1561 | /** | 1565 | /** |
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index 846be60e7821..2ae2ec40015d 100644 --- a/drivers/net/wan/Kconfig +++ b/drivers/net/wan/Kconfig | |||
| @@ -25,7 +25,7 @@ if WAN | |||
| 25 | # There is no way to detect a comtrol sv11 - force it modular for now. | 25 | # There is no way to detect a comtrol sv11 - force it modular for now. |
| 26 | config HOSTESS_SV11 | 26 | config HOSTESS_SV11 |
| 27 | tristate "Comtrol Hostess SV-11 support" | 27 | tristate "Comtrol Hostess SV-11 support" |
| 28 | depends on ISA && m && ISA_DMA_API && INET | 28 | depends on ISA && m && ISA_DMA_API && INET && HDLC |
| 29 | help | 29 | help |
| 30 | Driver for Comtrol Hostess SV-11 network card which | 30 | Driver for Comtrol Hostess SV-11 network card which |
| 31 | operates on low speed synchronous serial links at up to | 31 | operates on low speed synchronous serial links at up to |
| @@ -37,7 +37,7 @@ config HOSTESS_SV11 | |||
| 37 | # The COSA/SRP driver has not been tested as non-modular yet. | 37 | # The COSA/SRP driver has not been tested as non-modular yet. |
| 38 | config COSA | 38 | config COSA |
| 39 | tristate "COSA/SRP sync serial boards support" | 39 | tristate "COSA/SRP sync serial boards support" |
| 40 | depends on ISA && m && ISA_DMA_API | 40 | depends on ISA && m && ISA_DMA_API && HDLC |
| 41 | ---help--- | 41 | ---help--- |
| 42 | Driver for COSA and SRP synchronous serial boards. | 42 | Driver for COSA and SRP synchronous serial boards. |
| 43 | 43 | ||
| @@ -61,7 +61,7 @@ config COSA | |||
| 61 | # | 61 | # |
| 62 | config LANMEDIA | 62 | config LANMEDIA |
| 63 | tristate "LanMedia Corp. SSI/V.35, T1/E1, HSSI, T3 boards" | 63 | tristate "LanMedia Corp. SSI/V.35, T1/E1, HSSI, T3 boards" |
| 64 | depends on PCI && VIRT_TO_BUS | 64 | depends on PCI && VIRT_TO_BUS && HDLC |
| 65 | ---help--- | 65 | ---help--- |
| 66 | Driver for the following Lan Media family of serial boards: | 66 | Driver for the following Lan Media family of serial boards: |
| 67 | 67 | ||
| @@ -78,9 +78,8 @@ config LANMEDIA | |||
| 78 | - LMC 5245 board connects directly to a T3 circuit saving the | 78 | - LMC 5245 board connects directly to a T3 circuit saving the |
| 79 | additional external hardware. | 79 | additional external hardware. |
| 80 | 80 | ||
| 81 | To change setting such as syncPPP vs Cisco HDLC or clock source you | 81 | To change setting such as clock source you will need lmcctl. |
| 82 | will need lmcctl. It is available at <ftp://ftp.lanmedia.com/> | 82 | It is available at <ftp://ftp.lanmedia.com/> (broken link). |
| 83 | (broken link). | ||
| 84 | 83 | ||
| 85 | To compile this driver as a module, choose M here: the | 84 | To compile this driver as a module, choose M here: the |
| 86 | module will be called lmc. | 85 | module will be called lmc. |
| @@ -88,7 +87,7 @@ config LANMEDIA | |||
| 88 | # There is no way to detect a Sealevel board. Force it modular | 87 | # There is no way to detect a Sealevel board. Force it modular |
| 89 | config SEALEVEL_4021 | 88 | config SEALEVEL_4021 |
| 90 | tristate "Sealevel Systems 4021 support" | 89 | tristate "Sealevel Systems 4021 support" |
| 91 | depends on ISA && m && ISA_DMA_API && INET | 90 | depends on ISA && m && ISA_DMA_API && INET && HDLC |
| 92 | help | 91 | help |
| 93 | This is a driver for the Sealevel Systems ACB 56 serial I/O adapter. | 92 | This is a driver for the Sealevel Systems ACB 56 serial I/O adapter. |
| 94 | 93 | ||
| @@ -154,8 +153,6 @@ config HDLC_PPP | |||
| 154 | help | 153 | help |
| 155 | Generic HDLC driver supporting PPP over WAN connections. | 154 | Generic HDLC driver supporting PPP over WAN connections. |
| 156 | 155 | ||
| 157 | It will be replaced by new PPP implementation in Linux 2.6.26. | ||
| 158 | |||
| 159 | If unsure, say N. | 156 | If unsure, say N. |
| 160 | 157 | ||
| 161 | config HDLC_X25 | 158 | config HDLC_X25 |
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile index d61fef36afc9..102549605d09 100644 --- a/drivers/net/wan/Makefile +++ b/drivers/net/wan/Makefile | |||
| @@ -21,12 +21,11 @@ pc300-y := pc300_drv.o | |||
| 21 | pc300-$(CONFIG_PC300_MLPPP) += pc300_tty.o | 21 | pc300-$(CONFIG_PC300_MLPPP) += pc300_tty.o |
| 22 | pc300-objs := $(pc300-y) | 22 | pc300-objs := $(pc300-y) |
| 23 | 23 | ||
| 24 | obj-$(CONFIG_HOSTESS_SV11) += z85230.o syncppp.o hostess_sv11.o | 24 | obj-$(CONFIG_HOSTESS_SV11) += z85230.o hostess_sv11.o |
| 25 | obj-$(CONFIG_SEALEVEL_4021) += z85230.o syncppp.o sealevel.o | 25 | obj-$(CONFIG_SEALEVEL_4021) += z85230.o sealevel.o |
| 26 | obj-$(CONFIG_COSA) += syncppp.o cosa.o | 26 | obj-$(CONFIG_COSA) += cosa.o |
| 27 | obj-$(CONFIG_FARSYNC) += syncppp.o farsync.o | 27 | obj-$(CONFIG_FARSYNC) += farsync.o |
| 28 | obj-$(CONFIG_DSCC4) += dscc4.o | 28 | obj-$(CONFIG_DSCC4) += dscc4.o |
| 29 | obj-$(CONFIG_LANMEDIA) += syncppp.o | ||
| 30 | obj-$(CONFIG_X25_ASY) += x25_asy.o | 29 | obj-$(CONFIG_X25_ASY) += x25_asy.o |
| 31 | 30 | ||
| 32 | obj-$(CONFIG_LANMEDIA) += lmc/ | 31 | obj-$(CONFIG_LANMEDIA) += lmc/ |
diff --git a/drivers/net/wan/cosa.c b/drivers/net/wan/cosa.c index f7d3349dc3ec..f14051556c87 100644 --- a/drivers/net/wan/cosa.c +++ b/drivers/net/wan/cosa.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | 2 | ||
| 3 | /* | 3 | /* |
| 4 | * Copyright (C) 1995-1997 Jan "Yenya" Kasprzak <kas@fi.muni.cz> | 4 | * Copyright (C) 1995-1997 Jan "Yenya" Kasprzak <kas@fi.muni.cz> |
| 5 | * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl> | ||
| 5 | * | 6 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by | 8 | * it under the terms of the GNU General Public License as published by |
| @@ -54,7 +55,7 @@ | |||
| 54 | * | 55 | * |
| 55 | * The Linux driver (unlike the present *BSD drivers :-) can work even | 56 | * The Linux driver (unlike the present *BSD drivers :-) can work even |
| 56 | * for the COSA and SRP in one computer and allows each channel to work | 57 | * for the COSA and SRP in one computer and allows each channel to work |
| 57 | * in one of the three modes (character device, Cisco HDLC, Sync PPP). | 58 | * in one of the two modes (character or network device). |
| 58 | * | 59 | * |
| 59 | * AUTHOR | 60 | * AUTHOR |
| 60 | * | 61 | * |
| @@ -72,12 +73,6 @@ | |||
| 72 | * The Comtrol Hostess SV11 driver by Alan Cox | 73 | * The Comtrol Hostess SV11 driver by Alan Cox |
| 73 | * The Sync PPP/Cisco HDLC layer (syncppp.c) ported to Linux by Alan Cox | 74 | * The Sync PPP/Cisco HDLC layer (syncppp.c) ported to Linux by Alan Cox |
| 74 | */ | 75 | */ |
| 75 | /* | ||
| 76 | * 5/25/1999 : Marcelo Tosatti <marcelo@conectiva.com.br> | ||
| 77 | * fixed a deadlock in cosa_sppp_open | ||
| 78 | */ | ||
| 79 | |||
| 80 | /* ---------- Headers, macros, data structures ---------- */ | ||
| 81 | 76 | ||
| 82 | #include <linux/module.h> | 77 | #include <linux/module.h> |
| 83 | #include <linux/kernel.h> | 78 | #include <linux/kernel.h> |
| @@ -86,6 +81,7 @@ | |||
| 86 | #include <linux/fs.h> | 81 | #include <linux/fs.h> |
| 87 | #include <linux/interrupt.h> | 82 | #include <linux/interrupt.h> |
| 88 | #include <linux/delay.h> | 83 | #include <linux/delay.h> |
| 84 | #include <linux/hdlc.h> | ||
| 89 | #include <linux/errno.h> | 85 | #include <linux/errno.h> |
| 90 | #include <linux/ioport.h> | 86 | #include <linux/ioport.h> |
| 91 | #include <linux/netdevice.h> | 87 | #include <linux/netdevice.h> |
| @@ -93,14 +89,12 @@ | |||
| 93 | #include <linux/mutex.h> | 89 | #include <linux/mutex.h> |
| 94 | #include <linux/device.h> | 90 | #include <linux/device.h> |
| 95 | #include <linux/smp_lock.h> | 91 | #include <linux/smp_lock.h> |
| 96 | |||
| 97 | #undef COSA_SLOW_IO /* for testing purposes only */ | ||
| 98 | |||
| 99 | #include <asm/io.h> | 92 | #include <asm/io.h> |
| 100 | #include <asm/dma.h> | 93 | #include <asm/dma.h> |
| 101 | #include <asm/byteorder.h> | 94 | #include <asm/byteorder.h> |
| 102 | 95 | ||
| 103 | #include <net/syncppp.h> | 96 | #undef COSA_SLOW_IO /* for testing purposes only */ |
| 97 | |||
| 104 | #include "cosa.h" | 98 | #include "cosa.h" |
| 105 | 99 | ||
| 106 | /* Maximum length of the identification string. */ | 100 | /* Maximum length of the identification string. */ |
| @@ -112,7 +106,6 @@ | |||
| 112 | /* Per-channel data structure */ | 106 | /* Per-channel data structure */ |
| 113 | 107 | ||
| 114 | struct channel_data { | 108 | struct channel_data { |
| 115 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | ||
| 116 | int usage; /* Usage count; >0 for chrdev, -1 for netdev */ | 109 | int usage; /* Usage count; >0 for chrdev, -1 for netdev */ |
| 117 | int num; /* Number of the channel */ | 110 | int num; /* Number of the channel */ |
| 118 | struct cosa_data *cosa; /* Pointer to the per-card structure */ | 111 | struct cosa_data *cosa; /* Pointer to the per-card structure */ |
| @@ -136,10 +129,9 @@ struct channel_data { | |||
| 136 | wait_queue_head_t txwaitq, rxwaitq; | 129 | wait_queue_head_t txwaitq, rxwaitq; |
| 137 | int tx_status, rx_status; | 130 | int tx_status, rx_status; |
| 138 | 131 | ||
| 139 | /* SPPP/HDLC device parts */ | 132 | /* generic HDLC device parts */ |
| 140 | struct ppp_device pppdev; | 133 | struct net_device *netdev; |
| 141 | struct sk_buff *rx_skb, *tx_skb; | 134 | struct sk_buff *rx_skb, *tx_skb; |
| 142 | struct net_device_stats stats; | ||
| 143 | }; | 135 | }; |
| 144 | 136 | ||
| 145 | /* cosa->firmware_status bits */ | 137 | /* cosa->firmware_status bits */ |
| @@ -281,21 +273,19 @@ static int cosa_start_tx(struct channel_data *channel, char *buf, int size); | |||
| 281 | static void cosa_kick(struct cosa_data *cosa); | 273 | static void cosa_kick(struct cosa_data *cosa); |
| 282 | static int cosa_dma_able(struct channel_data *chan, char *buf, int data); | 274 | static int cosa_dma_able(struct channel_data *chan, char *buf, int data); |
| 283 | 275 | ||
| 284 | /* SPPP/HDLC stuff */ | 276 | /* Network device stuff */ |
| 285 | static void sppp_channel_init(struct channel_data *chan); | 277 | static int cosa_net_attach(struct net_device *dev, unsigned short encoding, |
| 286 | static void sppp_channel_delete(struct channel_data *chan); | 278 | unsigned short parity); |
| 287 | static int cosa_sppp_open(struct net_device *d); | 279 | static int cosa_net_open(struct net_device *d); |
| 288 | static int cosa_sppp_close(struct net_device *d); | 280 | static int cosa_net_close(struct net_device *d); |
| 289 | static void cosa_sppp_timeout(struct net_device *d); | 281 | static void cosa_net_timeout(struct net_device *d); |
| 290 | static int cosa_sppp_tx(struct sk_buff *skb, struct net_device *d); | 282 | static int cosa_net_tx(struct sk_buff *skb, struct net_device *d); |
| 291 | static char *sppp_setup_rx(struct channel_data *channel, int size); | 283 | static char *cosa_net_setup_rx(struct channel_data *channel, int size); |
| 292 | static int sppp_rx_done(struct channel_data *channel); | 284 | static int cosa_net_rx_done(struct channel_data *channel); |
| 293 | static int sppp_tx_done(struct channel_data *channel, int size); | 285 | static int cosa_net_tx_done(struct channel_data *channel, int size); |
| 294 | static int cosa_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); | 286 | static int cosa_net_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
| 295 | static struct net_device_stats *cosa_net_stats(struct net_device *dev); | ||
| 296 | 287 | ||
| 297 | /* Character device */ | 288 | /* Character device */ |
| 298 | static void chardev_channel_init(struct channel_data *chan); | ||
| 299 | static char *chrdev_setup_rx(struct channel_data *channel, int size); | 289 | static char *chrdev_setup_rx(struct channel_data *channel, int size); |
| 300 | static int chrdev_rx_done(struct channel_data *channel); | 290 | static int chrdev_rx_done(struct channel_data *channel); |
| 301 | static int chrdev_tx_done(struct channel_data *channel, int size); | 291 | static int chrdev_tx_done(struct channel_data *channel, int size); |
| @@ -357,17 +347,17 @@ static void debug_status_in(struct cosa_data *cosa, int status); | |||
| 357 | static void debug_status_out(struct cosa_data *cosa, int status); | 347 | static void debug_status_out(struct cosa_data *cosa, int status); |
| 358 | #endif | 348 | #endif |
| 359 | 349 | ||
| 360 | 350 | static inline struct channel_data* dev_to_chan(struct net_device *dev) | |
| 351 | { | ||
| 352 | return (struct channel_data *)dev_to_hdlc(dev)->priv; | ||
| 353 | } | ||
| 354 | |||
| 361 | /* ---------- Initialization stuff ---------- */ | 355 | /* ---------- Initialization stuff ---------- */ |
| 362 | 356 | ||
| 363 | static int __init cosa_init(void) | 357 | static int __init cosa_init(void) |
| 364 | { | 358 | { |
| 365 | int i, err = 0; | 359 | int i, err = 0; |
| 366 | 360 | ||
| 367 | printk(KERN_INFO "cosa v1.08 (c) 1997-2000 Jan Kasprzak <kas@fi.muni.cz>\n"); | ||
| 368 | #ifdef CONFIG_SMP | ||
| 369 | printk(KERN_INFO "cosa: SMP found. Please mail any success/failure reports to the author.\n"); | ||
| 370 | #endif | ||
| 371 | if (cosa_major > 0) { | 361 | if (cosa_major > 0) { |
| 372 | if (register_chrdev(cosa_major, "cosa", &cosa_fops)) { | 362 | if (register_chrdev(cosa_major, "cosa", &cosa_fops)) { |
| 373 | printk(KERN_WARNING "cosa: unable to get major %d\n", | 363 | printk(KERN_WARNING "cosa: unable to get major %d\n", |
| @@ -402,7 +392,7 @@ static int __init cosa_init(void) | |||
| 402 | NULL, "cosa%d", i); | 392 | NULL, "cosa%d", i); |
| 403 | err = 0; | 393 | err = 0; |
| 404 | goto out; | 394 | goto out; |
| 405 | 395 | ||
| 406 | out_chrdev: | 396 | out_chrdev: |
| 407 | unregister_chrdev(cosa_major, "cosa"); | 397 | unregister_chrdev(cosa_major, "cosa"); |
| 408 | out: | 398 | out: |
| @@ -414,43 +404,29 @@ static void __exit cosa_exit(void) | |||
| 414 | { | 404 | { |
| 415 | struct cosa_data *cosa; | 405 | struct cosa_data *cosa; |
| 416 | int i; | 406 | int i; |
| 417 | printk(KERN_INFO "Unloading the cosa module\n"); | ||
| 418 | 407 | ||
| 419 | for (i=0; i<nr_cards; i++) | 408 | for (i = 0; i < nr_cards; i++) |
| 420 | device_destroy(cosa_class, MKDEV(cosa_major, i)); | 409 | device_destroy(cosa_class, MKDEV(cosa_major, i)); |
| 421 | class_destroy(cosa_class); | 410 | class_destroy(cosa_class); |
| 422 | for (cosa=cosa_cards; nr_cards--; cosa++) { | 411 | |
| 412 | for (cosa = cosa_cards; nr_cards--; cosa++) { | ||
| 423 | /* Clean up the per-channel data */ | 413 | /* Clean up the per-channel data */ |
| 424 | for (i=0; i<cosa->nchannels; i++) { | 414 | for (i = 0; i < cosa->nchannels; i++) { |
| 425 | /* Chardev driver has no alloc'd per-channel data */ | 415 | /* Chardev driver has no alloc'd per-channel data */ |
| 426 | sppp_channel_delete(cosa->chan+i); | 416 | unregister_hdlc_device(cosa->chan[i].netdev); |
| 417 | free_netdev(cosa->chan[i].netdev); | ||
| 427 | } | 418 | } |
| 428 | /* Clean up the per-card data */ | 419 | /* Clean up the per-card data */ |
| 429 | kfree(cosa->chan); | 420 | kfree(cosa->chan); |
| 430 | kfree(cosa->bouncebuf); | 421 | kfree(cosa->bouncebuf); |
| 431 | free_irq(cosa->irq, cosa); | 422 | free_irq(cosa->irq, cosa); |
| 432 | free_dma(cosa->dma); | 423 | free_dma(cosa->dma); |
| 433 | release_region(cosa->datareg,is_8bit(cosa)?2:4); | 424 | release_region(cosa->datareg, is_8bit(cosa) ? 2 : 4); |
| 434 | } | 425 | } |
| 435 | unregister_chrdev(cosa_major, "cosa"); | 426 | unregister_chrdev(cosa_major, "cosa"); |
| 436 | } | 427 | } |
| 437 | module_exit(cosa_exit); | 428 | module_exit(cosa_exit); |
| 438 | 429 | ||
| 439 | /* | ||
| 440 | * This function should register all the net devices needed for the | ||
| 441 | * single channel. | ||
| 442 | */ | ||
| 443 | static __inline__ void channel_init(struct channel_data *chan) | ||
| 444 | { | ||
| 445 | sprintf(chan->name, "cosa%dc%d", chan->cosa->num, chan->num); | ||
| 446 | |||
| 447 | /* Initialize the chardev data structures */ | ||
| 448 | chardev_channel_init(chan); | ||
| 449 | |||
| 450 | /* Register the sppp interface */ | ||
| 451 | sppp_channel_init(chan); | ||
| 452 | } | ||
| 453 | |||
| 454 | static int cosa_probe(int base, int irq, int dma) | 430 | static int cosa_probe(int base, int irq, int dma) |
| 455 | { | 431 | { |
| 456 | struct cosa_data *cosa = cosa_cards+nr_cards; | 432 | struct cosa_data *cosa = cosa_cards+nr_cards; |
| @@ -576,13 +552,43 @@ static int cosa_probe(int base, int irq, int dma) | |||
| 576 | /* Initialize the per-channel data */ | 552 | /* Initialize the per-channel data */ |
| 577 | cosa->chan = kcalloc(cosa->nchannels, sizeof(struct channel_data), GFP_KERNEL); | 553 | cosa->chan = kcalloc(cosa->nchannels, sizeof(struct channel_data), GFP_KERNEL); |
| 578 | if (!cosa->chan) { | 554 | if (!cosa->chan) { |
| 579 | err = -ENOMEM; | 555 | err = -ENOMEM; |
| 580 | goto err_out3; | 556 | goto err_out3; |
| 581 | } | 557 | } |
| 582 | for (i=0; i<cosa->nchannels; i++) { | 558 | |
| 583 | cosa->chan[i].cosa = cosa; | 559 | for (i = 0; i < cosa->nchannels; i++) { |
| 584 | cosa->chan[i].num = i; | 560 | struct channel_data *chan = &cosa->chan[i]; |
| 585 | channel_init(cosa->chan+i); | 561 | |
| 562 | chan->cosa = cosa; | ||
| 563 | chan->num = i; | ||
| 564 | sprintf(chan->name, "cosa%dc%d", chan->cosa->num, i); | ||
| 565 | |||
| 566 | /* Initialize the chardev data structures */ | ||
| 567 | mutex_init(&chan->rlock); | ||
| 568 | init_MUTEX(&chan->wsem); | ||
| 569 | |||
| 570 | /* Register the network interface */ | ||
| 571 | if (!(chan->netdev = alloc_hdlcdev(chan))) { | ||
| 572 | printk(KERN_WARNING "%s: alloc_hdlcdev failed.\n", | ||
| 573 | chan->name); | ||
| 574 | goto err_hdlcdev; | ||
| 575 | } | ||
| 576 | dev_to_hdlc(chan->netdev)->attach = cosa_net_attach; | ||
| 577 | dev_to_hdlc(chan->netdev)->xmit = cosa_net_tx; | ||
| 578 | chan->netdev->open = cosa_net_open; | ||
| 579 | chan->netdev->stop = cosa_net_close; | ||
| 580 | chan->netdev->do_ioctl = cosa_net_ioctl; | ||
| 581 | chan->netdev->tx_timeout = cosa_net_timeout; | ||
| 582 | chan->netdev->watchdog_timeo = TX_TIMEOUT; | ||
| 583 | chan->netdev->base_addr = chan->cosa->datareg; | ||
| 584 | chan->netdev->irq = chan->cosa->irq; | ||
| 585 | chan->netdev->dma = chan->cosa->dma; | ||
| 586 | if (register_hdlc_device(chan->netdev)) { | ||
| 587 | printk(KERN_WARNING "%s: register_hdlc_device()" | ||
| 588 | " failed.\n", chan->netdev->name); | ||
| 589 | free_netdev(chan->netdev); | ||
| 590 | goto err_hdlcdev; | ||
| 591 | } | ||
| 586 | } | 592 | } |
| 587 | 593 | ||
| 588 | printk (KERN_INFO "cosa%d: %s (%s at 0x%x irq %d dma %d), %d channels\n", | 594 | printk (KERN_INFO "cosa%d: %s (%s at 0x%x irq %d dma %d), %d channels\n", |
| @@ -590,13 +596,20 @@ static int cosa_probe(int base, int irq, int dma) | |||
| 590 | cosa->datareg, cosa->irq, cosa->dma, cosa->nchannels); | 596 | cosa->datareg, cosa->irq, cosa->dma, cosa->nchannels); |
| 591 | 597 | ||
| 592 | return nr_cards++; | 598 | return nr_cards++; |
| 599 | |||
| 600 | err_hdlcdev: | ||
| 601 | while (i-- > 0) { | ||
| 602 | unregister_hdlc_device(cosa->chan[i].netdev); | ||
| 603 | free_netdev(cosa->chan[i].netdev); | ||
| 604 | } | ||
| 605 | kfree(cosa->chan); | ||
| 593 | err_out3: | 606 | err_out3: |
| 594 | kfree(cosa->bouncebuf); | 607 | kfree(cosa->bouncebuf); |
| 595 | err_out2: | 608 | err_out2: |
| 596 | free_dma(cosa->dma); | 609 | free_dma(cosa->dma); |
| 597 | err_out1: | 610 | err_out1: |
| 598 | free_irq(cosa->irq, cosa); | 611 | free_irq(cosa->irq, cosa); |
| 599 | err_out: | 612 | err_out: |
| 600 | release_region(cosa->datareg,is_8bit(cosa)?2:4); | 613 | release_region(cosa->datareg,is_8bit(cosa)?2:4); |
| 601 | printk(KERN_NOTICE "cosa%d: allocating resources failed\n", | 614 | printk(KERN_NOTICE "cosa%d: allocating resources failed\n", |
| 602 | cosa->num); | 615 | cosa->num); |
| @@ -604,54 +617,19 @@ err_out: | |||
| 604 | } | 617 | } |
| 605 | 618 | ||
| 606 | 619 | ||
| 607 | /*---------- SPPP/HDLC netdevice ---------- */ | 620 | /*---------- network device ---------- */ |
| 608 | 621 | ||
| 609 | static void cosa_setup(struct net_device *d) | 622 | static int cosa_net_attach(struct net_device *dev, unsigned short encoding, |
| 623 | unsigned short parity) | ||
| 610 | { | 624 | { |
| 611 | d->open = cosa_sppp_open; | 625 | if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT) |
| 612 | d->stop = cosa_sppp_close; | 626 | return 0; |
| 613 | d->hard_start_xmit = cosa_sppp_tx; | 627 | return -EINVAL; |
| 614 | d->do_ioctl = cosa_sppp_ioctl; | ||
| 615 | d->get_stats = cosa_net_stats; | ||
| 616 | d->tx_timeout = cosa_sppp_timeout; | ||
| 617 | d->watchdog_timeo = TX_TIMEOUT; | ||
| 618 | } | ||
| 619 | |||
| 620 | static void sppp_channel_init(struct channel_data *chan) | ||
| 621 | { | ||
| 622 | struct net_device *d; | ||
| 623 | chan->if_ptr = &chan->pppdev; | ||
| 624 | d = alloc_netdev(0, chan->name, cosa_setup); | ||
| 625 | if (!d) { | ||
| 626 | printk(KERN_WARNING "%s: alloc_netdev failed.\n", chan->name); | ||
| 627 | return; | ||
| 628 | } | ||
| 629 | chan->pppdev.dev = d; | ||
| 630 | d->base_addr = chan->cosa->datareg; | ||
| 631 | d->irq = chan->cosa->irq; | ||
| 632 | d->dma = chan->cosa->dma; | ||
| 633 | d->ml_priv = chan; | ||
| 634 | sppp_attach(&chan->pppdev); | ||
| 635 | if (register_netdev(d)) { | ||
| 636 | printk(KERN_WARNING "%s: register_netdev failed.\n", d->name); | ||
| 637 | sppp_detach(d); | ||
| 638 | free_netdev(d); | ||
| 639 | chan->pppdev.dev = NULL; | ||
| 640 | return; | ||
| 641 | } | ||
| 642 | } | ||
| 643 | |||
| 644 | static void sppp_channel_delete(struct channel_data *chan) | ||
| 645 | { | ||
| 646 | unregister_netdev(chan->pppdev.dev); | ||
| 647 | sppp_detach(chan->pppdev.dev); | ||
| 648 | free_netdev(chan->pppdev.dev); | ||
| 649 | chan->pppdev.dev = NULL; | ||
| 650 | } | 628 | } |
| 651 | 629 | ||
| 652 | static int cosa_sppp_open(struct net_device *d) | 630 | static int cosa_net_open(struct net_device *dev) |
| 653 | { | 631 | { |
| 654 | struct channel_data *chan = d->ml_priv; | 632 | struct channel_data *chan = dev_to_chan(dev); |
| 655 | int err; | 633 | int err; |
| 656 | unsigned long flags; | 634 | unsigned long flags; |
| 657 | 635 | ||
| @@ -662,36 +640,35 @@ static int cosa_sppp_open(struct net_device *d) | |||
| 662 | } | 640 | } |
| 663 | spin_lock_irqsave(&chan->cosa->lock, flags); | 641 | spin_lock_irqsave(&chan->cosa->lock, flags); |
| 664 | if (chan->usage != 0) { | 642 | if (chan->usage != 0) { |
| 665 | printk(KERN_WARNING "%s: sppp_open called with usage count %d\n", | 643 | printk(KERN_WARNING "%s: cosa_net_open called with usage count" |
| 666 | chan->name, chan->usage); | 644 | " %d\n", chan->name, chan->usage); |
| 667 | spin_unlock_irqrestore(&chan->cosa->lock, flags); | 645 | spin_unlock_irqrestore(&chan->cosa->lock, flags); |
| 668 | return -EBUSY; | 646 | return -EBUSY; |
| 669 | } | 647 | } |
| 670 | chan->setup_rx = sppp_setup_rx; | 648 | chan->setup_rx = cosa_net_setup_rx; |
| 671 | chan->tx_done = sppp_tx_done; | 649 | chan->tx_done = cosa_net_tx_done; |
| 672 | chan->rx_done = sppp_rx_done; | 650 | chan->rx_done = cosa_net_rx_done; |
| 673 | chan->usage=-1; | 651 | chan->usage = -1; |
| 674 | chan->cosa->usage++; | 652 | chan->cosa->usage++; |
| 675 | spin_unlock_irqrestore(&chan->cosa->lock, flags); | 653 | spin_unlock_irqrestore(&chan->cosa->lock, flags); |
| 676 | 654 | ||
| 677 | err = sppp_open(d); | 655 | err = hdlc_open(dev); |
| 678 | if (err) { | 656 | if (err) { |
| 679 | spin_lock_irqsave(&chan->cosa->lock, flags); | 657 | spin_lock_irqsave(&chan->cosa->lock, flags); |
| 680 | chan->usage=0; | 658 | chan->usage = 0; |
| 681 | chan->cosa->usage--; | 659 | chan->cosa->usage--; |
| 682 | |||
| 683 | spin_unlock_irqrestore(&chan->cosa->lock, flags); | 660 | spin_unlock_irqrestore(&chan->cosa->lock, flags); |
| 684 | return err; | 661 | return err; |
| 685 | } | 662 | } |
| 686 | 663 | ||
| 687 | netif_start_queue(d); | 664 | netif_start_queue(dev); |
| 688 | cosa_enable_rx(chan); | 665 | cosa_enable_rx(chan); |
| 689 | return 0; | 666 | return 0; |
| 690 | } | 667 | } |
| 691 | 668 | ||
| 692 | static int cosa_sppp_tx(struct sk_buff *skb, struct net_device *dev) | 669 | static int cosa_net_tx(struct sk_buff *skb, struct net_device *dev) |
| 693 | { | 670 | { |
| 694 | struct channel_data *chan = dev->ml_priv; | 671 | struct channel_data *chan = dev_to_chan(dev); |
| 695 | 672 | ||
| 696 | netif_stop_queue(dev); | 673 | netif_stop_queue(dev); |
| 697 | 674 | ||
| @@ -700,16 +677,16 @@ static int cosa_sppp_tx(struct sk_buff *skb, struct net_device *dev) | |||
| 700 | return 0; | 677 | return 0; |
| 701 | } | 678 | } |
| 702 | 679 | ||
| 703 | static void cosa_sppp_timeout(struct net_device *dev) | 680 | static void cosa_net_timeout(struct net_device *dev) |
| 704 | { | 681 | { |
| 705 | struct channel_data *chan = dev->ml_priv; | 682 | struct channel_data *chan = dev_to_chan(dev); |
| 706 | 683 | ||
| 707 | if (test_bit(RXBIT, &chan->cosa->rxtx)) { | 684 | if (test_bit(RXBIT, &chan->cosa->rxtx)) { |
| 708 | chan->stats.rx_errors++; | 685 | chan->netdev->stats.rx_errors++; |
| 709 | chan->stats.rx_missed_errors++; | 686 | chan->netdev->stats.rx_missed_errors++; |
| 710 | } else { | 687 | } else { |
| 711 | chan->stats.tx_errors++; | 688 | chan->netdev->stats.tx_errors++; |
| 712 | chan->stats.tx_aborted_errors++; | 689 | chan->netdev->stats.tx_aborted_errors++; |
| 713 | } | 690 | } |
| 714 | cosa_kick(chan->cosa); | 691 | cosa_kick(chan->cosa); |
| 715 | if (chan->tx_skb) { | 692 | if (chan->tx_skb) { |
| @@ -719,13 +696,13 @@ static void cosa_sppp_timeout(struct net_device *dev) | |||
| 719 | netif_wake_queue(dev); | 696 | netif_wake_queue(dev); |
| 720 | } | 697 | } |
| 721 | 698 | ||
| 722 | static int cosa_sppp_close(struct net_device *d) | 699 | static int cosa_net_close(struct net_device *dev) |
| 723 | { | 700 | { |
| 724 | struct channel_data *chan = d->ml_priv; | 701 | struct channel_data *chan = dev_to_chan(dev); |
| 725 | unsigned long flags; | 702 | unsigned long flags; |
| 726 | 703 | ||
| 727 | netif_stop_queue(d); | 704 | netif_stop_queue(dev); |
| 728 | sppp_close(d); | 705 | hdlc_close(dev); |
| 729 | cosa_disable_rx(chan); | 706 | cosa_disable_rx(chan); |
| 730 | spin_lock_irqsave(&chan->cosa->lock, flags); | 707 | spin_lock_irqsave(&chan->cosa->lock, flags); |
| 731 | if (chan->rx_skb) { | 708 | if (chan->rx_skb) { |
| @@ -736,13 +713,13 @@ static int cosa_sppp_close(struct net_device *d) | |||
| 736 | kfree_skb(chan->tx_skb); | 713 | kfree_skb(chan->tx_skb); |
| 737 | chan->tx_skb = NULL; | 714 | chan->tx_skb = NULL; |
| 738 | } | 715 | } |
| 739 | chan->usage=0; | 716 | chan->usage = 0; |
| 740 | chan->cosa->usage--; | 717 | chan->cosa->usage--; |
| 741 | spin_unlock_irqrestore(&chan->cosa->lock, flags); | 718 | spin_unlock_irqrestore(&chan->cosa->lock, flags); |
| 742 | return 0; | 719 | return 0; |
| 743 | } | 720 | } |
| 744 | 721 | ||
| 745 | static char *sppp_setup_rx(struct channel_data *chan, int size) | 722 | static char *cosa_net_setup_rx(struct channel_data *chan, int size) |
| 746 | { | 723 | { |
| 747 | /* | 724 | /* |
| 748 | * We can safely fall back to non-dma-able memory, because we have | 725 | * We can safely fall back to non-dma-able memory, because we have |
| @@ -754,66 +731,53 @@ static char *sppp_setup_rx(struct channel_data *chan, int size) | |||
| 754 | if (chan->rx_skb == NULL) { | 731 | if (chan->rx_skb == NULL) { |
| 755 | printk(KERN_NOTICE "%s: Memory squeeze, dropping packet\n", | 732 | printk(KERN_NOTICE "%s: Memory squeeze, dropping packet\n", |
| 756 | chan->name); | 733 | chan->name); |
| 757 | chan->stats.rx_dropped++; | 734 | chan->netdev->stats.rx_dropped++; |
| 758 | return NULL; | 735 | return NULL; |
| 759 | } | 736 | } |
| 760 | chan->pppdev.dev->trans_start = jiffies; | 737 | chan->netdev->trans_start = jiffies; |
| 761 | return skb_put(chan->rx_skb, size); | 738 | return skb_put(chan->rx_skb, size); |
| 762 | } | 739 | } |
| 763 | 740 | ||
| 764 | static int sppp_rx_done(struct channel_data *chan) | 741 | static int cosa_net_rx_done(struct channel_data *chan) |
| 765 | { | 742 | { |
| 766 | if (!chan->rx_skb) { | 743 | if (!chan->rx_skb) { |
| 767 | printk(KERN_WARNING "%s: rx_done with empty skb!\n", | 744 | printk(KERN_WARNING "%s: rx_done with empty skb!\n", |
| 768 | chan->name); | 745 | chan->name); |
| 769 | chan->stats.rx_errors++; | 746 | chan->netdev->stats.rx_errors++; |
| 770 | chan->stats.rx_frame_errors++; | 747 | chan->netdev->stats.rx_frame_errors++; |
| 771 | return 0; | 748 | return 0; |
| 772 | } | 749 | } |
| 773 | chan->rx_skb->protocol = htons(ETH_P_WAN_PPP); | 750 | chan->rx_skb->protocol = hdlc_type_trans(chan->rx_skb, chan->netdev); |
| 774 | chan->rx_skb->dev = chan->pppdev.dev; | 751 | chan->rx_skb->dev = chan->netdev; |
| 775 | skb_reset_mac_header(chan->rx_skb); | 752 | skb_reset_mac_header(chan->rx_skb); |
| 776 | chan->stats.rx_packets++; | 753 | chan->netdev->stats.rx_packets++; |
| 777 | chan->stats.rx_bytes += chan->cosa->rxsize; | 754 | chan->netdev->stats.rx_bytes += chan->cosa->rxsize; |
| 778 | netif_rx(chan->rx_skb); | 755 | netif_rx(chan->rx_skb); |
| 779 | chan->rx_skb = NULL; | 756 | chan->rx_skb = NULL; |
| 780 | chan->pppdev.dev->last_rx = jiffies; | 757 | chan->netdev->last_rx = jiffies; |
| 781 | return 0; | 758 | return 0; |
| 782 | } | 759 | } |
| 783 | 760 | ||
| 784 | /* ARGSUSED */ | 761 | /* ARGSUSED */ |
| 785 | static int sppp_tx_done(struct channel_data *chan, int size) | 762 | static int cosa_net_tx_done(struct channel_data *chan, int size) |
| 786 | { | 763 | { |
| 787 | if (!chan->tx_skb) { | 764 | if (!chan->tx_skb) { |
| 788 | printk(KERN_WARNING "%s: tx_done with empty skb!\n", | 765 | printk(KERN_WARNING "%s: tx_done with empty skb!\n", |
| 789 | chan->name); | 766 | chan->name); |
| 790 | chan->stats.tx_errors++; | 767 | chan->netdev->stats.tx_errors++; |
| 791 | chan->stats.tx_aborted_errors++; | 768 | chan->netdev->stats.tx_aborted_errors++; |
| 792 | return 1; | 769 | return 1; |
| 793 | } | 770 | } |
| 794 | dev_kfree_skb_irq(chan->tx_skb); | 771 | dev_kfree_skb_irq(chan->tx_skb); |
| 795 | chan->tx_skb = NULL; | 772 | chan->tx_skb = NULL; |
| 796 | chan->stats.tx_packets++; | 773 | chan->netdev->stats.tx_packets++; |
| 797 | chan->stats.tx_bytes += size; | 774 | chan->netdev->stats.tx_bytes += size; |
| 798 | netif_wake_queue(chan->pppdev.dev); | 775 | netif_wake_queue(chan->netdev); |
| 799 | return 1; | 776 | return 1; |
| 800 | } | 777 | } |
| 801 | 778 | ||
| 802 | static struct net_device_stats *cosa_net_stats(struct net_device *dev) | ||
| 803 | { | ||
| 804 | struct channel_data *chan = dev->ml_priv; | ||
| 805 | return &chan->stats; | ||
| 806 | } | ||
| 807 | |||
| 808 | |||
| 809 | /*---------- Character device ---------- */ | 779 | /*---------- Character device ---------- */ |
| 810 | 780 | ||
| 811 | static void chardev_channel_init(struct channel_data *chan) | ||
| 812 | { | ||
| 813 | mutex_init(&chan->rlock); | ||
| 814 | init_MUTEX(&chan->wsem); | ||
| 815 | } | ||
| 816 | |||
| 817 | static ssize_t cosa_read(struct file *file, | 781 | static ssize_t cosa_read(struct file *file, |
| 818 | char __user *buf, size_t count, loff_t *ppos) | 782 | char __user *buf, size_t count, loff_t *ppos) |
| 819 | { | 783 | { |
| @@ -1223,16 +1187,15 @@ static int cosa_ioctl_common(struct cosa_data *cosa, | |||
| 1223 | return -ENOIOCTLCMD; | 1187 | return -ENOIOCTLCMD; |
| 1224 | } | 1188 | } |
| 1225 | 1189 | ||
| 1226 | static int cosa_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, | 1190 | static int cosa_net_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 1227 | int cmd) | ||
| 1228 | { | 1191 | { |
| 1229 | int rv; | 1192 | int rv; |
| 1230 | struct channel_data *chan = dev->ml_priv; | 1193 | struct channel_data *chan = dev_to_chan(dev); |
| 1231 | rv = cosa_ioctl_common(chan->cosa, chan, cmd, (unsigned long)ifr->ifr_data); | 1194 | rv = cosa_ioctl_common(chan->cosa, chan, cmd, |
| 1232 | if (rv == -ENOIOCTLCMD) { | 1195 | (unsigned long)ifr->ifr_data); |
| 1233 | return sppp_do_ioctl(dev, ifr, cmd); | 1196 | if (rv != -ENOIOCTLCMD) |
| 1234 | } | 1197 | return rv; |
| 1235 | return rv; | 1198 | return hdlc_ioctl(dev, ifr, cmd); |
| 1236 | } | 1199 | } |
| 1237 | 1200 | ||
| 1238 | static int cosa_chardev_ioctl(struct inode *inode, struct file *file, | 1201 | static int cosa_chardev_ioctl(struct inode *inode, struct file *file, |
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c index 50ef5b4efd6d..f5d55ad02267 100644 --- a/drivers/net/wan/dscc4.c +++ b/drivers/net/wan/dscc4.c | |||
| @@ -103,7 +103,6 @@ | |||
| 103 | #include <linux/netdevice.h> | 103 | #include <linux/netdevice.h> |
| 104 | #include <linux/skbuff.h> | 104 | #include <linux/skbuff.h> |
| 105 | #include <linux/delay.h> | 105 | #include <linux/delay.h> |
| 106 | #include <net/syncppp.h> | ||
| 107 | #include <linux/hdlc.h> | 106 | #include <linux/hdlc.h> |
| 108 | #include <linux/mutex.h> | 107 | #include <linux/mutex.h> |
| 109 | 108 | ||
diff --git a/drivers/net/wan/farsync.c b/drivers/net/wan/farsync.c index 754f00809e3e..9557ad078ab8 100644 --- a/drivers/net/wan/farsync.c +++ b/drivers/net/wan/farsync.c | |||
| @@ -47,10 +47,7 @@ MODULE_LICENSE("GPL"); | |||
| 47 | /* Default parameters for the link | 47 | /* Default parameters for the link |
| 48 | */ | 48 | */ |
| 49 | #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is | 49 | #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is |
| 50 | * useful, the syncppp module forces | 50 | * useful */ |
| 51 | * this down assuming a slower line I | ||
| 52 | * guess. | ||
| 53 | */ | ||
| 54 | #define FST_TXQ_DEPTH 16 /* This one is for the buffering | 51 | #define FST_TXQ_DEPTH 16 /* This one is for the buffering |
| 55 | * of frames on the way down to the card | 52 | * of frames on the way down to the card |
| 56 | * so that we can keep the card busy | 53 | * so that we can keep the card busy |
diff --git a/drivers/net/wan/farsync.h b/drivers/net/wan/farsync.h index d871dafa87a1..6b27e7c3d449 100644 --- a/drivers/net/wan/farsync.h +++ b/drivers/net/wan/farsync.h | |||
| @@ -54,9 +54,6 @@ | |||
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | /* Ioctl call command values | 56 | /* Ioctl call command values |
| 57 | * | ||
| 58 | * The first three private ioctls are used by the sync-PPP module, | ||
| 59 | * allowing a little room for expansion we start our numbering at 10. | ||
| 60 | */ | 57 | */ |
| 61 | #define FSTWRITE (SIOCDEVPRIVATE+10) | 58 | #define FSTWRITE (SIOCDEVPRIVATE+10) |
| 62 | #define FSTCPURESET (SIOCDEVPRIVATE+11) | 59 | #define FSTCPURESET (SIOCDEVPRIVATE+11) |
| @@ -202,9 +199,6 @@ struct fstioc_info { | |||
| 202 | #define J1 7 | 199 | #define J1 7 |
| 203 | 200 | ||
| 204 | /* "proto" */ | 201 | /* "proto" */ |
| 205 | #define FST_HDLC 1 /* Cisco compatible HDLC */ | ||
| 206 | #define FST_PPP 2 /* Sync PPP */ | ||
| 207 | #define FST_MONITOR 3 /* Monitor only (raw packet reception) */ | ||
| 208 | #define FST_RAW 4 /* Two way raw packets */ | 202 | #define FST_RAW 4 /* Two way raw packets */ |
| 209 | #define FST_GEN_HDLC 5 /* Using "Generic HDLC" module */ | 203 | #define FST_GEN_HDLC 5 /* Using "Generic HDLC" module */ |
| 210 | 204 | ||
diff --git a/drivers/net/wan/hdlc.c b/drivers/net/wan/hdlc.c index e3a536477c7e..1f2a140c9f7c 100644 --- a/drivers/net/wan/hdlc.c +++ b/drivers/net/wan/hdlc.c | |||
| @@ -22,20 +22,19 @@ | |||
| 22 | * - proto->start() and stop() are called with spin_lock_irq held. | 22 | * - proto->start() and stop() are called with spin_lock_irq held. |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/kernel.h> | ||
| 27 | #include <linux/slab.h> | ||
| 28 | #include <linux/poll.h> | ||
| 29 | #include <linux/errno.h> | 25 | #include <linux/errno.h> |
| 26 | #include <linux/hdlc.h> | ||
| 30 | #include <linux/if_arp.h> | 27 | #include <linux/if_arp.h> |
| 28 | #include <linux/inetdevice.h> | ||
| 31 | #include <linux/init.h> | 29 | #include <linux/init.h> |
| 32 | #include <linux/skbuff.h> | 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> | ||
| 32 | #include <linux/notifier.h> | ||
| 33 | #include <linux/pkt_sched.h> | 33 | #include <linux/pkt_sched.h> |
| 34 | #include <linux/inetdevice.h> | 34 | #include <linux/poll.h> |
| 35 | #include <linux/lapb.h> | ||
| 36 | #include <linux/rtnetlink.h> | 35 | #include <linux/rtnetlink.h> |
| 37 | #include <linux/notifier.h> | 36 | #include <linux/skbuff.h> |
| 38 | #include <linux/hdlc.h> | 37 | #include <linux/slab.h> |
| 39 | #include <net/net_namespace.h> | 38 | #include <net/net_namespace.h> |
| 40 | 39 | ||
| 41 | 40 | ||
| @@ -109,7 +108,7 @@ static int hdlc_device_event(struct notifier_block *this, unsigned long event, | |||
| 109 | 108 | ||
| 110 | if (dev->get_stats != hdlc_get_stats) | 109 | if (dev->get_stats != hdlc_get_stats) |
| 111 | return NOTIFY_DONE; /* not an HDLC device */ | 110 | return NOTIFY_DONE; /* not an HDLC device */ |
| 112 | 111 | ||
| 113 | if (event != NETDEV_CHANGE) | 112 | if (event != NETDEV_CHANGE) |
| 114 | return NOTIFY_DONE; /* Only interrested in carrier changes */ | 113 | return NOTIFY_DONE; /* Only interrested in carrier changes */ |
| 115 | 114 | ||
| @@ -357,7 +356,7 @@ static struct packet_type hdlc_packet_type = { | |||
| 357 | 356 | ||
| 358 | 357 | ||
| 359 | static struct notifier_block hdlc_notifier = { | 358 | static struct notifier_block hdlc_notifier = { |
| 360 | .notifier_call = hdlc_device_event, | 359 | .notifier_call = hdlc_device_event, |
| 361 | }; | 360 | }; |
| 362 | 361 | ||
| 363 | 362 | ||
| @@ -367,8 +366,8 @@ static int __init hdlc_module_init(void) | |||
| 367 | 366 | ||
| 368 | printk(KERN_INFO "%s\n", version); | 367 | printk(KERN_INFO "%s\n", version); |
| 369 | if ((result = register_netdevice_notifier(&hdlc_notifier)) != 0) | 368 | if ((result = register_netdevice_notifier(&hdlc_notifier)) != 0) |
| 370 | return result; | 369 | return result; |
| 371 | dev_add_pack(&hdlc_packet_type); | 370 | dev_add_pack(&hdlc_packet_type); |
| 372 | return 0; | 371 | return 0; |
| 373 | } | 372 | } |
| 374 | 373 | ||
diff --git a/drivers/net/wan/hdlc_cisco.c b/drivers/net/wan/hdlc_cisco.c index 849819c2552d..44e64b15dbd1 100644 --- a/drivers/net/wan/hdlc_cisco.c +++ b/drivers/net/wan/hdlc_cisco.c | |||
| @@ -9,19 +9,18 @@ | |||
| 9 | * as published by the Free Software Foundation. | 9 | * as published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/slab.h> | ||
| 15 | #include <linux/poll.h> | ||
| 16 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/hdlc.h> | ||
| 17 | #include <linux/if_arp.h> | 14 | #include <linux/if_arp.h> |
| 15 | #include <linux/inetdevice.h> | ||
| 18 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 19 | #include <linux/skbuff.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> | ||
| 20 | #include <linux/pkt_sched.h> | 19 | #include <linux/pkt_sched.h> |
| 21 | #include <linux/inetdevice.h> | 20 | #include <linux/poll.h> |
| 22 | #include <linux/lapb.h> | ||
| 23 | #include <linux/rtnetlink.h> | 21 | #include <linux/rtnetlink.h> |
| 24 | #include <linux/hdlc.h> | 22 | #include <linux/skbuff.h> |
| 23 | #include <linux/slab.h> | ||
| 25 | 24 | ||
| 26 | #undef DEBUG_HARD_HEADER | 25 | #undef DEBUG_HARD_HEADER |
| 27 | 26 | ||
| @@ -68,9 +67,9 @@ struct cisco_state { | |||
| 68 | static int cisco_ioctl(struct net_device *dev, struct ifreq *ifr); | 67 | static int cisco_ioctl(struct net_device *dev, struct ifreq *ifr); |
| 69 | 68 | ||
| 70 | 69 | ||
| 71 | static inline struct cisco_state * state(hdlc_device *hdlc) | 70 | static inline struct cisco_state* state(hdlc_device *hdlc) |
| 72 | { | 71 | { |
| 73 | return(struct cisco_state *)(hdlc->state); | 72 | return (struct cisco_state *)hdlc->state; |
| 74 | } | 73 | } |
| 75 | 74 | ||
| 76 | 75 | ||
| @@ -172,7 +171,7 @@ static int cisco_rx(struct sk_buff *skb) | |||
| 172 | data->address != CISCO_UNICAST) | 171 | data->address != CISCO_UNICAST) |
| 173 | goto rx_error; | 172 | goto rx_error; |
| 174 | 173 | ||
| 175 | switch(ntohs(data->protocol)) { | 174 | switch (ntohs(data->protocol)) { |
| 176 | case CISCO_SYS_INFO: | 175 | case CISCO_SYS_INFO: |
| 177 | /* Packet is not needed, drop it. */ | 176 | /* Packet is not needed, drop it. */ |
| 178 | dev_kfree_skb_any(skb); | 177 | dev_kfree_skb_any(skb); |
| @@ -336,7 +335,7 @@ static struct hdlc_proto proto = { | |||
| 336 | static const struct header_ops cisco_header_ops = { | 335 | static const struct header_ops cisco_header_ops = { |
| 337 | .create = cisco_hard_header, | 336 | .create = cisco_hard_header, |
| 338 | }; | 337 | }; |
| 339 | 338 | ||
| 340 | static int cisco_ioctl(struct net_device *dev, struct ifreq *ifr) | 339 | static int cisco_ioctl(struct net_device *dev, struct ifreq *ifr) |
| 341 | { | 340 | { |
| 342 | cisco_proto __user *cisco_s = ifr->ifr_settings.ifs_ifsu.cisco; | 341 | cisco_proto __user *cisco_s = ifr->ifr_settings.ifs_ifsu.cisco; |
| @@ -359,10 +358,10 @@ static int cisco_ioctl(struct net_device *dev, struct ifreq *ifr) | |||
| 359 | return 0; | 358 | return 0; |
| 360 | 359 | ||
| 361 | case IF_PROTO_CISCO: | 360 | case IF_PROTO_CISCO: |
| 362 | if(!capable(CAP_NET_ADMIN)) | 361 | if (!capable(CAP_NET_ADMIN)) |
| 363 | return -EPERM; | 362 | return -EPERM; |
| 364 | 363 | ||
| 365 | if(dev->flags & IFF_UP) | 364 | if (dev->flags & IFF_UP) |
| 366 | return -EBUSY; | 365 | return -EBUSY; |
| 367 | 366 | ||
| 368 | if (copy_from_user(&new_settings, cisco_s, size)) | 367 | if (copy_from_user(&new_settings, cisco_s, size)) |
| @@ -372,7 +371,7 @@ static int cisco_ioctl(struct net_device *dev, struct ifreq *ifr) | |||
| 372 | new_settings.timeout < 2) | 371 | new_settings.timeout < 2) |
| 373 | return -EINVAL; | 372 | return -EINVAL; |
| 374 | 373 | ||
| 375 | result=hdlc->attach(dev, ENCODING_NRZ,PARITY_CRC16_PR1_CCITT); | 374 | result = hdlc->attach(dev, ENCODING_NRZ,PARITY_CRC16_PR1_CCITT); |
| 376 | if (result) | 375 | if (result) |
| 377 | return result; | 376 | return result; |
| 378 | 377 | ||
diff --git a/drivers/net/wan/hdlc_fr.c b/drivers/net/wan/hdlc_fr.c index 62e93dac6b13..d3d5055741ad 100644 --- a/drivers/net/wan/hdlc_fr.c +++ b/drivers/net/wan/hdlc_fr.c | |||
| @@ -33,20 +33,19 @@ | |||
| 33 | 33 | ||
| 34 | */ | 34 | */ |
| 35 | 35 | ||
| 36 | #include <linux/module.h> | ||
| 37 | #include <linux/kernel.h> | ||
| 38 | #include <linux/slab.h> | ||
| 39 | #include <linux/poll.h> | ||
| 40 | #include <linux/errno.h> | 36 | #include <linux/errno.h> |
| 37 | #include <linux/etherdevice.h> | ||
| 38 | #include <linux/hdlc.h> | ||
| 41 | #include <linux/if_arp.h> | 39 | #include <linux/if_arp.h> |
| 40 | #include <linux/inetdevice.h> | ||
| 42 | #include <linux/init.h> | 41 | #include <linux/init.h> |
| 43 | #include <linux/skbuff.h> | 42 | #include <linux/kernel.h> |
| 43 | #include <linux/module.h> | ||
| 44 | #include <linux/pkt_sched.h> | 44 | #include <linux/pkt_sched.h> |
| 45 | #include <linux/inetdevice.h> | 45 | #include <linux/poll.h> |
| 46 | #include <linux/lapb.h> | ||
| 47 | #include <linux/rtnetlink.h> | 46 | #include <linux/rtnetlink.h> |
| 48 | #include <linux/etherdevice.h> | 47 | #include <linux/skbuff.h> |
| 49 | #include <linux/hdlc.h> | 48 | #include <linux/slab.h> |
| 50 | 49 | ||
| 51 | #undef DEBUG_PKT | 50 | #undef DEBUG_PKT |
| 52 | #undef DEBUG_ECN | 51 | #undef DEBUG_ECN |
| @@ -96,7 +95,7 @@ typedef struct { | |||
| 96 | unsigned ea1: 1; | 95 | unsigned ea1: 1; |
| 97 | unsigned cr: 1; | 96 | unsigned cr: 1; |
| 98 | unsigned dlcih: 6; | 97 | unsigned dlcih: 6; |
| 99 | 98 | ||
| 100 | unsigned ea2: 1; | 99 | unsigned ea2: 1; |
| 101 | unsigned de: 1; | 100 | unsigned de: 1; |
| 102 | unsigned becn: 1; | 101 | unsigned becn: 1; |
diff --git a/drivers/net/wan/hdlc_ppp.c b/drivers/net/wan/hdlc_ppp.c index 00308337928e..4efe9e6d32d5 100644 --- a/drivers/net/wan/hdlc_ppp.c +++ b/drivers/net/wan/hdlc_ppp.c | |||
| @@ -9,19 +9,18 @@ | |||
| 9 | * as published by the Free Software Foundation. | 9 | * as published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/slab.h> | ||
| 15 | #include <linux/poll.h> | ||
| 16 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/hdlc.h> | ||
| 17 | #include <linux/if_arp.h> | 14 | #include <linux/if_arp.h> |
| 15 | #include <linux/inetdevice.h> | ||
| 18 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 19 | #include <linux/skbuff.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> | ||
| 20 | #include <linux/pkt_sched.h> | 19 | #include <linux/pkt_sched.h> |
| 21 | #include <linux/inetdevice.h> | 20 | #include <linux/poll.h> |
| 22 | #include <linux/lapb.h> | ||
| 23 | #include <linux/rtnetlink.h> | 21 | #include <linux/rtnetlink.h> |
| 24 | #include <linux/hdlc.h> | 22 | #include <linux/skbuff.h> |
| 23 | #include <linux/slab.h> | ||
| 25 | #include <net/syncppp.h> | 24 | #include <net/syncppp.h> |
| 26 | 25 | ||
| 27 | struct ppp_state { | 26 | struct ppp_state { |
diff --git a/drivers/net/wan/hdlc_raw.c b/drivers/net/wan/hdlc_raw.c index bbbb819d764c..8612311748f4 100644 --- a/drivers/net/wan/hdlc_raw.c +++ b/drivers/net/wan/hdlc_raw.c | |||
| @@ -9,19 +9,18 @@ | |||
| 9 | * as published by the Free Software Foundation. | 9 | * as published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/slab.h> | ||
| 15 | #include <linux/poll.h> | ||
| 16 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/hdlc.h> | ||
| 17 | #include <linux/if_arp.h> | 14 | #include <linux/if_arp.h> |
| 15 | #include <linux/inetdevice.h> | ||
| 18 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 19 | #include <linux/skbuff.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> | ||
| 20 | #include <linux/pkt_sched.h> | 19 | #include <linux/pkt_sched.h> |
| 21 | #include <linux/inetdevice.h> | 20 | #include <linux/poll.h> |
| 22 | #include <linux/lapb.h> | ||
| 23 | #include <linux/rtnetlink.h> | 21 | #include <linux/rtnetlink.h> |
| 24 | #include <linux/hdlc.h> | 22 | #include <linux/skbuff.h> |
| 23 | #include <linux/slab.h> | ||
| 25 | 24 | ||
| 26 | 25 | ||
| 27 | static int raw_ioctl(struct net_device *dev, struct ifreq *ifr); | 26 | static int raw_ioctl(struct net_device *dev, struct ifreq *ifr); |
diff --git a/drivers/net/wan/hdlc_raw_eth.c b/drivers/net/wan/hdlc_raw_eth.c index 26dee600506f..a13fc3207520 100644 --- a/drivers/net/wan/hdlc_raw_eth.c +++ b/drivers/net/wan/hdlc_raw_eth.c | |||
| @@ -9,20 +9,19 @@ | |||
| 9 | * as published by the Free Software Foundation. | 9 | * as published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/slab.h> | ||
| 15 | #include <linux/poll.h> | ||
| 16 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/etherdevice.h> | ||
| 14 | #include <linux/hdlc.h> | ||
| 17 | #include <linux/if_arp.h> | 15 | #include <linux/if_arp.h> |
| 16 | #include <linux/inetdevice.h> | ||
| 18 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 19 | #include <linux/skbuff.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/pkt_sched.h> | 20 | #include <linux/pkt_sched.h> |
| 21 | #include <linux/inetdevice.h> | 21 | #include <linux/poll.h> |
| 22 | #include <linux/lapb.h> | ||
| 23 | #include <linux/rtnetlink.h> | 22 | #include <linux/rtnetlink.h> |
| 24 | #include <linux/etherdevice.h> | 23 | #include <linux/skbuff.h> |
| 25 | #include <linux/hdlc.h> | 24 | #include <linux/slab.h> |
| 26 | 25 | ||
| 27 | static int raw_eth_ioctl(struct net_device *dev, struct ifreq *ifr); | 26 | static int raw_eth_ioctl(struct net_device *dev, struct ifreq *ifr); |
| 28 | 27 | ||
diff --git a/drivers/net/wan/hdlc_x25.c b/drivers/net/wan/hdlc_x25.c index e808720030ef..8b7e5d2e2ac9 100644 --- a/drivers/net/wan/hdlc_x25.c +++ b/drivers/net/wan/hdlc_x25.c | |||
| @@ -9,20 +9,19 @@ | |||
| 9 | * as published by the Free Software Foundation. | 9 | * as published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/slab.h> | ||
| 15 | #include <linux/poll.h> | ||
| 16 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/hdlc.h> | ||
| 17 | #include <linux/if_arp.h> | 14 | #include <linux/if_arp.h> |
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/skbuff.h> | ||
| 20 | #include <linux/pkt_sched.h> | ||
| 21 | #include <linux/inetdevice.h> | 15 | #include <linux/inetdevice.h> |
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 22 | #include <linux/lapb.h> | 18 | #include <linux/lapb.h> |
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/pkt_sched.h> | ||
| 21 | #include <linux/poll.h> | ||
| 23 | #include <linux/rtnetlink.h> | 22 | #include <linux/rtnetlink.h> |
| 24 | #include <linux/hdlc.h> | 23 | #include <linux/skbuff.h> |
| 25 | 24 | #include <linux/slab.h> | |
| 26 | #include <net/x25device.h> | 25 | #include <net/x25device.h> |
| 27 | 26 | ||
| 28 | static int x25_ioctl(struct net_device *dev, struct ifreq *ifr); | 27 | static int x25_ioctl(struct net_device *dev, struct ifreq *ifr); |
diff --git a/drivers/net/wan/hostess_sv11.c b/drivers/net/wan/hostess_sv11.c index f3065d3473fd..e299313f828a 100644 --- a/drivers/net/wan/hostess_sv11.c +++ b/drivers/net/wan/hostess_sv11.c | |||
| @@ -16,6 +16,8 @@ | |||
| 16 | * touching control registers. | 16 | * touching control registers. |
| 17 | * | 17 | * |
| 18 | * Port B isnt wired (why - beats me) | 18 | * Port B isnt wired (why - beats me) |
| 19 | * | ||
| 20 | * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl> | ||
| 19 | */ | 21 | */ |
| 20 | 22 | ||
| 21 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| @@ -26,6 +28,7 @@ | |||
| 26 | #include <linux/netdevice.h> | 28 | #include <linux/netdevice.h> |
| 27 | #include <linux/if_arp.h> | 29 | #include <linux/if_arp.h> |
| 28 | #include <linux/delay.h> | 30 | #include <linux/delay.h> |
| 31 | #include <linux/hdlc.h> | ||
| 29 | #include <linux/ioport.h> | 32 | #include <linux/ioport.h> |
| 30 | #include <net/arp.h> | 33 | #include <net/arp.h> |
| 31 | 34 | ||
| @@ -33,34 +36,31 @@ | |||
| 33 | #include <asm/io.h> | 36 | #include <asm/io.h> |
| 34 | #include <asm/dma.h> | 37 | #include <asm/dma.h> |
| 35 | #include <asm/byteorder.h> | 38 | #include <asm/byteorder.h> |
| 36 | #include <net/syncppp.h> | ||
| 37 | #include "z85230.h" | 39 | #include "z85230.h" |
| 38 | 40 | ||
| 39 | static int dma; | 41 | static int dma; |
| 40 | 42 | ||
| 41 | struct sv11_device | ||
| 42 | { | ||
| 43 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | ||
| 44 | struct z8530_dev sync; | ||
| 45 | struct ppp_device netdev; | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* | 43 | /* |
| 49 | * Network driver support routines | 44 | * Network driver support routines |
| 50 | */ | 45 | */ |
| 51 | 46 | ||
| 47 | static inline struct z8530_dev* dev_to_sv(struct net_device *dev) | ||
| 48 | { | ||
| 49 | return (struct z8530_dev *)dev_to_hdlc(dev)->priv; | ||
| 50 | } | ||
| 51 | |||
| 52 | /* | 52 | /* |
| 53 | * Frame receive. Simple for our card as we do sync ppp and there | 53 | * Frame receive. Simple for our card as we do HDLC and there |
| 54 | * is no funny garbage involved | 54 | * is no funny garbage involved |
| 55 | */ | 55 | */ |
| 56 | 56 | ||
| 57 | static void hostess_input(struct z8530_channel *c, struct sk_buff *skb) | 57 | static void hostess_input(struct z8530_channel *c, struct sk_buff *skb) |
| 58 | { | 58 | { |
| 59 | /* Drop the CRC - it's not a good idea to try and negotiate it ;) */ | 59 | /* Drop the CRC - it's not a good idea to try and negotiate it ;) */ |
| 60 | skb_trim(skb, skb->len-2); | 60 | skb_trim(skb, skb->len - 2); |
| 61 | skb->protocol=__constant_htons(ETH_P_WAN_PPP); | 61 | skb->protocol = hdlc_type_trans(skb, c->netdevice); |
| 62 | skb_reset_mac_header(skb); | 62 | skb_reset_mac_header(skb); |
| 63 | skb->dev=c->netdevice; | 63 | skb->dev = c->netdevice; |
| 64 | /* | 64 | /* |
| 65 | * Send it to the PPP layer. We don't have time to process | 65 | * Send it to the PPP layer. We don't have time to process |
| 66 | * it right now. | 66 | * it right now. |
| @@ -68,56 +68,51 @@ static void hostess_input(struct z8530_channel *c, struct sk_buff *skb) | |||
| 68 | netif_rx(skb); | 68 | netif_rx(skb); |
| 69 | c->netdevice->last_rx = jiffies; | 69 | c->netdevice->last_rx = jiffies; |
| 70 | } | 70 | } |
| 71 | 71 | ||
| 72 | /* | 72 | /* |
| 73 | * We've been placed in the UP state | 73 | * We've been placed in the UP state |
| 74 | */ | 74 | */ |
| 75 | 75 | ||
| 76 | static int hostess_open(struct net_device *d) | 76 | static int hostess_open(struct net_device *d) |
| 77 | { | 77 | { |
| 78 | struct sv11_device *sv11=d->ml_priv; | 78 | struct z8530_dev *sv11 = dev_to_sv(d); |
| 79 | int err = -1; | 79 | int err = -1; |
| 80 | 80 | ||
| 81 | /* | 81 | /* |
| 82 | * Link layer up | 82 | * Link layer up |
| 83 | */ | 83 | */ |
| 84 | switch(dma) | 84 | switch (dma) { |
| 85 | { | ||
| 86 | case 0: | 85 | case 0: |
| 87 | err=z8530_sync_open(d, &sv11->sync.chanA); | 86 | err = z8530_sync_open(d, &sv11->chanA); |
| 88 | break; | 87 | break; |
| 89 | case 1: | 88 | case 1: |
| 90 | err=z8530_sync_dma_open(d, &sv11->sync.chanA); | 89 | err = z8530_sync_dma_open(d, &sv11->chanA); |
| 91 | break; | 90 | break; |
| 92 | case 2: | 91 | case 2: |
| 93 | err=z8530_sync_txdma_open(d, &sv11->sync.chanA); | 92 | err = z8530_sync_txdma_open(d, &sv11->chanA); |
| 94 | break; | 93 | break; |
| 95 | } | 94 | } |
| 96 | 95 | ||
| 97 | if(err) | 96 | if (err) |
| 98 | return err; | 97 | return err; |
| 99 | /* | 98 | |
| 100 | * Begin PPP | 99 | err = hdlc_open(d); |
| 101 | */ | 100 | if (err) { |
| 102 | err=sppp_open(d); | 101 | switch (dma) { |
| 103 | if(err) | ||
| 104 | { | ||
| 105 | switch(dma) | ||
| 106 | { | ||
| 107 | case 0: | 102 | case 0: |
| 108 | z8530_sync_close(d, &sv11->sync.chanA); | 103 | z8530_sync_close(d, &sv11->chanA); |
| 109 | break; | 104 | break; |
| 110 | case 1: | 105 | case 1: |
| 111 | z8530_sync_dma_close(d, &sv11->sync.chanA); | 106 | z8530_sync_dma_close(d, &sv11->chanA); |
| 112 | break; | 107 | break; |
| 113 | case 2: | 108 | case 2: |
| 114 | z8530_sync_txdma_close(d, &sv11->sync.chanA); | 109 | z8530_sync_txdma_close(d, &sv11->chanA); |
| 115 | break; | 110 | break; |
| 116 | } | 111 | } |
| 117 | return err; | 112 | return err; |
| 118 | } | 113 | } |
| 119 | sv11->sync.chanA.rx_function=hostess_input; | 114 | sv11->chanA.rx_function = hostess_input; |
| 120 | 115 | ||
| 121 | /* | 116 | /* |
| 122 | * Go go go | 117 | * Go go go |
| 123 | */ | 118 | */ |
| @@ -128,30 +123,24 @@ static int hostess_open(struct net_device *d) | |||
| 128 | 123 | ||
| 129 | static int hostess_close(struct net_device *d) | 124 | static int hostess_close(struct net_device *d) |
| 130 | { | 125 | { |
| 131 | struct sv11_device *sv11=d->ml_priv; | 126 | struct z8530_dev *sv11 = dev_to_sv(d); |
| 132 | /* | 127 | /* |
| 133 | * Discard new frames | 128 | * Discard new frames |
| 134 | */ | 129 | */ |
| 135 | sv11->sync.chanA.rx_function=z8530_null_rx; | 130 | sv11->chanA.rx_function = z8530_null_rx; |
| 136 | /* | 131 | |
| 137 | * PPP off | 132 | hdlc_close(d); |
| 138 | */ | ||
| 139 | sppp_close(d); | ||
| 140 | /* | ||
| 141 | * Link layer down | ||
| 142 | */ | ||
| 143 | netif_stop_queue(d); | 133 | netif_stop_queue(d); |
| 144 | 134 | ||
| 145 | switch(dma) | 135 | switch (dma) { |
| 146 | { | ||
| 147 | case 0: | 136 | case 0: |
| 148 | z8530_sync_close(d, &sv11->sync.chanA); | 137 | z8530_sync_close(d, &sv11->chanA); |
| 149 | break; | 138 | break; |
| 150 | case 1: | 139 | case 1: |
| 151 | z8530_sync_dma_close(d, &sv11->sync.chanA); | 140 | z8530_sync_dma_close(d, &sv11->chanA); |
| 152 | break; | 141 | break; |
| 153 | case 2: | 142 | case 2: |
| 154 | z8530_sync_txdma_close(d, &sv11->sync.chanA); | 143 | z8530_sync_txdma_close(d, &sv11->chanA); |
| 155 | break; | 144 | break; |
| 156 | } | 145 | } |
| 157 | return 0; | 146 | return 0; |
| @@ -159,232 +148,174 @@ static int hostess_close(struct net_device *d) | |||
| 159 | 148 | ||
| 160 | static int hostess_ioctl(struct net_device *d, struct ifreq *ifr, int cmd) | 149 | static int hostess_ioctl(struct net_device *d, struct ifreq *ifr, int cmd) |
| 161 | { | 150 | { |
| 162 | /* struct sv11_device *sv11=d->ml_priv; | 151 | /* struct z8530_dev *sv11=dev_to_sv(d); |
| 163 | z8530_ioctl(d,&sv11->sync.chanA,ifr,cmd) */ | 152 | z8530_ioctl(d,&sv11->chanA,ifr,cmd) */ |
| 164 | return sppp_do_ioctl(d, ifr,cmd); | 153 | return hdlc_ioctl(d, ifr, cmd); |
| 165 | } | ||
| 166 | |||
| 167 | static struct net_device_stats *hostess_get_stats(struct net_device *d) | ||
| 168 | { | ||
| 169 | struct sv11_device *sv11=d->ml_priv; | ||
| 170 | if(sv11) | ||
| 171 | return z8530_get_stats(&sv11->sync.chanA); | ||
| 172 | else | ||
| 173 | return NULL; | ||
| 174 | } | 154 | } |
| 175 | 155 | ||
| 176 | /* | 156 | /* |
| 177 | * Passed PPP frames, fire them downwind. | 157 | * Passed network frames, fire them downwind. |
| 178 | */ | 158 | */ |
| 179 | 159 | ||
| 180 | static int hostess_queue_xmit(struct sk_buff *skb, struct net_device *d) | 160 | static int hostess_queue_xmit(struct sk_buff *skb, struct net_device *d) |
| 181 | { | 161 | { |
| 182 | struct sv11_device *sv11=d->ml_priv; | 162 | return z8530_queue_xmit(&dev_to_sv(d)->chanA, skb); |
| 183 | return z8530_queue_xmit(&sv11->sync.chanA, skb); | ||
| 184 | } | 163 | } |
| 185 | 164 | ||
| 186 | static int hostess_neigh_setup(struct neighbour *n) | 165 | static int hostess_attach(struct net_device *dev, unsigned short encoding, |
| 166 | unsigned short parity) | ||
| 187 | { | 167 | { |
| 188 | if (n->nud_state == NUD_NONE) { | 168 | if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT) |
| 189 | n->ops = &arp_broken_ops; | 169 | return 0; |
| 190 | n->output = n->ops->output; | 170 | return -EINVAL; |
| 191 | } | ||
| 192 | return 0; | ||
| 193 | } | ||
| 194 | |||
| 195 | static int hostess_neigh_setup_dev(struct net_device *dev, struct neigh_parms *p) | ||
| 196 | { | ||
| 197 | if (p->tbl->family == AF_INET) { | ||
| 198 | p->neigh_setup = hostess_neigh_setup; | ||
| 199 | p->ucast_probes = 0; | ||
| 200 | p->mcast_probes = 0; | ||
| 201 | } | ||
| 202 | return 0; | ||
| 203 | } | ||
| 204 | |||
| 205 | static void sv11_setup(struct net_device *dev) | ||
| 206 | { | ||
| 207 | dev->open = hostess_open; | ||
| 208 | dev->stop = hostess_close; | ||
| 209 | dev->hard_start_xmit = hostess_queue_xmit; | ||
| 210 | dev->get_stats = hostess_get_stats; | ||
| 211 | dev->do_ioctl = hostess_ioctl; | ||
| 212 | dev->neigh_setup = hostess_neigh_setup_dev; | ||
| 213 | } | 171 | } |
| 214 | 172 | ||
| 215 | /* | 173 | /* |
| 216 | * Description block for a Comtrol Hostess SV11 card | 174 | * Description block for a Comtrol Hostess SV11 card |
| 217 | */ | 175 | */ |
| 218 | 176 | ||
| 219 | static struct sv11_device *sv11_init(int iobase, int irq) | 177 | static struct z8530_dev *sv11_init(int iobase, int irq) |
| 220 | { | 178 | { |
| 221 | struct z8530_dev *dev; | 179 | struct z8530_dev *sv; |
| 222 | struct sv11_device *sv; | 180 | struct net_device *netdev; |
| 223 | |||
| 224 | /* | 181 | /* |
| 225 | * Get the needed I/O space | 182 | * Get the needed I/O space |
| 226 | */ | 183 | */ |
| 227 | 184 | ||
| 228 | if(!request_region(iobase, 8, "Comtrol SV11")) | 185 | if (!request_region(iobase, 8, "Comtrol SV11")) { |
| 229 | { | 186 | printk(KERN_WARNING "hostess: I/O 0x%X already in use.\n", |
| 230 | printk(KERN_WARNING "hostess: I/O 0x%X already in use.\n", iobase); | 187 | iobase); |
| 231 | return NULL; | 188 | return NULL; |
| 232 | } | 189 | } |
| 233 | 190 | ||
| 234 | sv = kzalloc(sizeof(struct sv11_device), GFP_KERNEL); | 191 | sv = kzalloc(sizeof(struct z8530_dev), GFP_KERNEL); |
| 235 | if(!sv) | 192 | if (!sv) |
| 236 | goto fail3; | 193 | goto err_kzalloc; |
| 237 | 194 | ||
| 238 | sv->if_ptr=&sv->netdev; | ||
| 239 | |||
| 240 | sv->netdev.dev = alloc_netdev(0, "hdlc%d", sv11_setup); | ||
| 241 | if(!sv->netdev.dev) | ||
| 242 | goto fail2; | ||
| 243 | |||
| 244 | dev=&sv->sync; | ||
| 245 | |||
| 246 | /* | 195 | /* |
| 247 | * Stuff in the I/O addressing | 196 | * Stuff in the I/O addressing |
| 248 | */ | 197 | */ |
| 249 | 198 | ||
| 250 | dev->active = 0; | 199 | sv->active = 0; |
| 251 | 200 | ||
| 252 | dev->chanA.ctrlio=iobase+1; | 201 | sv->chanA.ctrlio = iobase + 1; |
| 253 | dev->chanA.dataio=iobase+3; | 202 | sv->chanA.dataio = iobase + 3; |
| 254 | dev->chanB.ctrlio=-1; | 203 | sv->chanB.ctrlio = -1; |
| 255 | dev->chanB.dataio=-1; | 204 | sv->chanB.dataio = -1; |
| 256 | dev->chanA.irqs=&z8530_nop; | 205 | sv->chanA.irqs = &z8530_nop; |
| 257 | dev->chanB.irqs=&z8530_nop; | 206 | sv->chanB.irqs = &z8530_nop; |
| 258 | 207 | ||
| 259 | outb(0, iobase+4); /* DMA off */ | 208 | outb(0, iobase + 4); /* DMA off */ |
| 260 | 209 | ||
| 261 | /* We want a fast IRQ for this device. Actually we'd like an even faster | 210 | /* We want a fast IRQ for this device. Actually we'd like an even faster |
| 262 | IRQ ;) - This is one driver RtLinux is made for */ | 211 | IRQ ;) - This is one driver RtLinux is made for */ |
| 263 | 212 | ||
| 264 | if(request_irq(irq, &z8530_interrupt, IRQF_DISABLED, "Hostess SV11", dev)<0) | 213 | if (request_irq(irq, &z8530_interrupt, IRQF_DISABLED, |
| 265 | { | 214 | "Hostess SV11", sv) < 0) { |
| 266 | printk(KERN_WARNING "hostess: IRQ %d already in use.\n", irq); | 215 | printk(KERN_WARNING "hostess: IRQ %d already in use.\n", irq); |
| 267 | goto fail1; | 216 | goto err_irq; |
| 268 | } | 217 | } |
| 269 | 218 | ||
| 270 | dev->irq=irq; | 219 | sv->irq = irq; |
| 271 | dev->chanA.private=sv; | 220 | sv->chanA.private = sv; |
| 272 | dev->chanA.netdevice=sv->netdev.dev; | 221 | sv->chanA.dev = sv; |
| 273 | dev->chanA.dev=dev; | 222 | sv->chanB.dev = sv; |
| 274 | dev->chanB.dev=dev; | 223 | |
| 275 | 224 | if (dma) { | |
| 276 | if(dma) | ||
| 277 | { | ||
| 278 | /* | 225 | /* |
| 279 | * You can have DMA off or 1 and 3 thats the lot | 226 | * You can have DMA off or 1 and 3 thats the lot |
| 280 | * on the Comtrol. | 227 | * on the Comtrol. |
| 281 | */ | 228 | */ |
| 282 | dev->chanA.txdma=3; | 229 | sv->chanA.txdma = 3; |
| 283 | dev->chanA.rxdma=1; | 230 | sv->chanA.rxdma = 1; |
| 284 | outb(0x03|0x08, iobase+4); /* DMA on */ | 231 | outb(0x03 | 0x08, iobase + 4); /* DMA on */ |
| 285 | if(request_dma(dev->chanA.txdma, "Hostess SV/11 (TX)")!=0) | 232 | if (request_dma(sv->chanA.txdma, "Hostess SV/11 (TX)")) |
| 286 | goto fail; | 233 | goto err_txdma; |
| 287 | 234 | ||
| 288 | if(dma==1) | 235 | if (dma == 1) |
| 289 | { | 236 | if (request_dma(sv->chanA.rxdma, "Hostess SV/11 (RX)")) |
| 290 | if(request_dma(dev->chanA.rxdma, "Hostess SV/11 (RX)")!=0) | 237 | goto err_rxdma; |
| 291 | goto dmafail; | ||
| 292 | } | ||
| 293 | } | 238 | } |
| 294 | 239 | ||
| 295 | /* Kill our private IRQ line the hostess can end up chattering | 240 | /* Kill our private IRQ line the hostess can end up chattering |
| 296 | until the configuration is set */ | 241 | until the configuration is set */ |
| 297 | disable_irq(irq); | 242 | disable_irq(irq); |
| 298 | 243 | ||
| 299 | /* | 244 | /* |
| 300 | * Begin normal initialise | 245 | * Begin normal initialise |
| 301 | */ | 246 | */ |
| 302 | 247 | ||
| 303 | if(z8530_init(dev)!=0) | 248 | if (z8530_init(sv)) { |
| 304 | { | ||
| 305 | printk(KERN_ERR "Z8530 series device not found.\n"); | 249 | printk(KERN_ERR "Z8530 series device not found.\n"); |
| 306 | enable_irq(irq); | 250 | enable_irq(irq); |
| 307 | goto dmafail2; | 251 | goto free_dma; |
| 308 | } | 252 | } |
| 309 | z8530_channel_load(&dev->chanB, z8530_dead_port); | 253 | z8530_channel_load(&sv->chanB, z8530_dead_port); |
| 310 | if(dev->type==Z85C30) | 254 | if (sv->type == Z85C30) |
| 311 | z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream); | 255 | z8530_channel_load(&sv->chanA, z8530_hdlc_kilostream); |
| 312 | else | 256 | else |
| 313 | z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream_85230); | 257 | z8530_channel_load(&sv->chanA, z8530_hdlc_kilostream_85230); |
| 314 | 258 | ||
| 315 | enable_irq(irq); | 259 | enable_irq(irq); |
| 316 | |||
| 317 | 260 | ||
| 318 | /* | 261 | /* |
| 319 | * Now we can take the IRQ | 262 | * Now we can take the IRQ |
| 320 | */ | 263 | */ |
| 321 | if(dev_alloc_name(dev->chanA.netdevice,"hdlc%d")>=0) | ||
| 322 | { | ||
| 323 | struct net_device *d=dev->chanA.netdevice; | ||
| 324 | 264 | ||
| 325 | /* | 265 | sv->chanA.netdevice = netdev = alloc_hdlcdev(sv); |
| 326 | * Initialise the PPP components | 266 | if (!netdev) |
| 327 | */ | 267 | goto free_dma; |
| 328 | d->ml_priv = sv; | ||
| 329 | sppp_attach(&sv->netdev); | ||
| 330 | |||
| 331 | /* | ||
| 332 | * Local fields | ||
| 333 | */ | ||
| 334 | |||
| 335 | d->base_addr = iobase; | ||
| 336 | d->irq = irq; | ||
| 337 | |||
| 338 | if(register_netdev(d)) | ||
| 339 | { | ||
| 340 | printk(KERN_ERR "%s: unable to register device.\n", | ||
| 341 | d->name); | ||
| 342 | sppp_detach(d); | ||
| 343 | goto dmafail2; | ||
| 344 | } | ||
| 345 | 268 | ||
| 346 | z8530_describe(dev, "I/O", iobase); | 269 | dev_to_hdlc(netdev)->attach = hostess_attach; |
| 347 | dev->active=1; | 270 | dev_to_hdlc(netdev)->xmit = hostess_queue_xmit; |
| 348 | return sv; | 271 | netdev->open = hostess_open; |
| 272 | netdev->stop = hostess_close; | ||
| 273 | netdev->do_ioctl = hostess_ioctl; | ||
| 274 | netdev->base_addr = iobase; | ||
| 275 | netdev->irq = irq; | ||
| 276 | |||
| 277 | if (register_hdlc_device(netdev)) { | ||
| 278 | printk(KERN_ERR "hostess: unable to register HDLC device.\n"); | ||
| 279 | free_netdev(netdev); | ||
| 280 | goto free_dma; | ||
| 349 | } | 281 | } |
| 350 | dmafail2: | 282 | |
| 351 | if(dma==1) | 283 | z8530_describe(sv, "I/O", iobase); |
| 352 | free_dma(dev->chanA.rxdma); | 284 | sv->active = 1; |
| 353 | dmafail: | 285 | return sv; |
| 354 | if(dma) | 286 | |
| 355 | free_dma(dev->chanA.txdma); | 287 | free_dma: |
| 356 | fail: | 288 | if (dma == 1) |
| 357 | free_irq(irq, dev); | 289 | free_dma(sv->chanA.rxdma); |
| 358 | fail1: | 290 | err_rxdma: |
| 359 | free_netdev(sv->netdev.dev); | 291 | if (dma) |
| 360 | fail2: | 292 | free_dma(sv->chanA.txdma); |
| 293 | err_txdma: | ||
| 294 | free_irq(irq, sv); | ||
| 295 | err_irq: | ||
| 361 | kfree(sv); | 296 | kfree(sv); |
| 362 | fail3: | 297 | err_kzalloc: |
| 363 | release_region(iobase,8); | 298 | release_region(iobase, 8); |
| 364 | return NULL; | 299 | return NULL; |
| 365 | } | 300 | } |
| 366 | 301 | ||
| 367 | static void sv11_shutdown(struct sv11_device *dev) | 302 | static void sv11_shutdown(struct z8530_dev *dev) |
| 368 | { | 303 | { |
| 369 | sppp_detach(dev->netdev.dev); | 304 | unregister_hdlc_device(dev->chanA.netdevice); |
| 370 | unregister_netdev(dev->netdev.dev); | 305 | z8530_shutdown(dev); |
| 371 | z8530_shutdown(&dev->sync); | 306 | free_irq(dev->irq, dev); |
| 372 | free_irq(dev->sync.irq, dev); | 307 | if (dma) { |
| 373 | if(dma) | 308 | if (dma == 1) |
| 374 | { | 309 | free_dma(dev->chanA.rxdma); |
| 375 | if(dma==1) | 310 | free_dma(dev->chanA.txdma); |
| 376 | free_dma(dev->sync.chanA.rxdma); | ||
| 377 | free_dma(dev->sync.chanA.txdma); | ||
| 378 | } | 311 | } |
| 379 | release_region(dev->sync.chanA.ctrlio-1, 8); | 312 | release_region(dev->chanA.ctrlio - 1, 8); |
| 380 | free_netdev(dev->netdev.dev); | 313 | free_netdev(dev->chanA.netdevice); |
| 381 | kfree(dev); | 314 | kfree(dev); |
| 382 | } | 315 | } |
| 383 | 316 | ||
| 384 | #ifdef MODULE | 317 | static int io = 0x200; |
| 385 | 318 | static int irq = 9; | |
| 386 | static int io=0x200; | ||
| 387 | static int irq=9; | ||
| 388 | 319 | ||
| 389 | module_param(io, int, 0); | 320 | module_param(io, int, 0); |
| 390 | MODULE_PARM_DESC(io, "The I/O base of the Comtrol Hostess SV11 card"); | 321 | MODULE_PARM_DESC(io, "The I/O base of the Comtrol Hostess SV11 card"); |
| @@ -397,22 +328,17 @@ MODULE_AUTHOR("Alan Cox"); | |||
| 397 | MODULE_LICENSE("GPL"); | 328 | MODULE_LICENSE("GPL"); |
| 398 | MODULE_DESCRIPTION("Modular driver for the Comtrol Hostess SV11"); | 329 | MODULE_DESCRIPTION("Modular driver for the Comtrol Hostess SV11"); |
| 399 | 330 | ||
| 400 | static struct sv11_device *sv11_unit; | 331 | static struct z8530_dev *sv11_unit; |
| 401 | 332 | ||
| 402 | int init_module(void) | 333 | int init_module(void) |
| 403 | { | 334 | { |
| 404 | printk(KERN_INFO "SV-11 Z85230 Synchronous Driver v 0.03.\n"); | 335 | if ((sv11_unit = sv11_init(io, irq)) == NULL) |
| 405 | printk(KERN_INFO "(c) Copyright 2001, Red Hat Inc.\n"); | ||
| 406 | if((sv11_unit=sv11_init(io,irq))==NULL) | ||
| 407 | return -ENODEV; | 336 | return -ENODEV; |
| 408 | return 0; | 337 | return 0; |
| 409 | } | 338 | } |
| 410 | 339 | ||
| 411 | void cleanup_module(void) | 340 | void cleanup_module(void) |
| 412 | { | 341 | { |
| 413 | if(sv11_unit) | 342 | if (sv11_unit) |
| 414 | sv11_shutdown(sv11_unit); | 343 | sv11_shutdown(sv11_unit); |
| 415 | } | 344 | } |
| 416 | |||
| 417 | #endif | ||
| 418 | |||
diff --git a/drivers/net/wan/lmc/lmc.h b/drivers/net/wan/lmc/lmc.h index 882e58c1bfd7..4ced7ac16c2c 100644 --- a/drivers/net/wan/lmc/lmc.h +++ b/drivers/net/wan/lmc/lmc.h | |||
| @@ -11,12 +11,12 @@ unsigned lmc_mii_readreg(lmc_softc_t * const sc, unsigned | |||
| 11 | devaddr, unsigned regno); | 11 | devaddr, unsigned regno); |
| 12 | void lmc_mii_writereg(lmc_softc_t * const sc, unsigned devaddr, | 12 | void lmc_mii_writereg(lmc_softc_t * const sc, unsigned devaddr, |
| 13 | unsigned regno, unsigned data); | 13 | unsigned regno, unsigned data); |
| 14 | void lmc_led_on(lmc_softc_t * const, u_int32_t); | 14 | void lmc_led_on(lmc_softc_t * const, u32); |
| 15 | void lmc_led_off(lmc_softc_t * const, u_int32_t); | 15 | void lmc_led_off(lmc_softc_t * const, u32); |
| 16 | unsigned lmc_mii_readreg(lmc_softc_t * const, unsigned, unsigned); | 16 | unsigned lmc_mii_readreg(lmc_softc_t * const, unsigned, unsigned); |
| 17 | void lmc_mii_writereg(lmc_softc_t * const, unsigned, unsigned, unsigned); | 17 | void lmc_mii_writereg(lmc_softc_t * const, unsigned, unsigned, unsigned); |
| 18 | void lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits); | 18 | void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits); |
| 19 | void lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits); | 19 | void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits); |
| 20 | 20 | ||
| 21 | int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); | 21 | int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
| 22 | 22 | ||
| @@ -26,8 +26,7 @@ extern lmc_media_t lmc_t1_media; | |||
| 26 | extern lmc_media_t lmc_hssi_media; | 26 | extern lmc_media_t lmc_hssi_media; |
| 27 | 27 | ||
| 28 | #ifdef _DBG_EVENTLOG | 28 | #ifdef _DBG_EVENTLOG |
| 29 | static void lmcEventLog( u_int32_t EventNum, u_int32_t arg2, u_int32_t arg3 ); | 29 | static void lmcEventLog(u32 EventNum, u32 arg2, u32 arg3); |
| 30 | #endif | 30 | #endif |
| 31 | 31 | ||
| 32 | #endif | 32 | #endif |
| 33 | |||
diff --git a/drivers/net/wan/lmc/lmc_debug.c b/drivers/net/wan/lmc/lmc_debug.c index 3b94352b0d03..15049d711f47 100644 --- a/drivers/net/wan/lmc/lmc_debug.c +++ b/drivers/net/wan/lmc/lmc_debug.c | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | |||
| 2 | #include <linux/types.h> | 1 | #include <linux/types.h> |
| 3 | #include <linux/netdevice.h> | 2 | #include <linux/netdevice.h> |
| 4 | #include <linux/interrupt.h> | 3 | #include <linux/interrupt.h> |
| @@ -48,10 +47,10 @@ void lmcConsoleLog(char *type, unsigned char *ucData, int iLen) | |||
| 48 | #endif | 47 | #endif |
| 49 | 48 | ||
| 50 | #ifdef DEBUG | 49 | #ifdef DEBUG |
| 51 | u_int32_t lmcEventLogIndex = 0; | 50 | u32 lmcEventLogIndex; |
| 52 | u_int32_t lmcEventLogBuf[LMC_EVENTLOGSIZE * LMC_EVENTLOGARGS]; | 51 | u32 lmcEventLogBuf[LMC_EVENTLOGSIZE * LMC_EVENTLOGARGS]; |
| 53 | 52 | ||
| 54 | void lmcEventLog (u_int32_t EventNum, u_int32_t arg2, u_int32_t arg3) | 53 | void lmcEventLog(u32 EventNum, u32 arg2, u32 arg3) |
| 55 | { | 54 | { |
| 56 | lmcEventLogBuf[lmcEventLogIndex++] = EventNum; | 55 | lmcEventLogBuf[lmcEventLogIndex++] = EventNum; |
| 57 | lmcEventLogBuf[lmcEventLogIndex++] = arg2; | 56 | lmcEventLogBuf[lmcEventLogIndex++] = arg2; |
diff --git a/drivers/net/wan/lmc/lmc_debug.h b/drivers/net/wan/lmc/lmc_debug.h index cf3563859bf3..2d46f121549f 100644 --- a/drivers/net/wan/lmc/lmc_debug.h +++ b/drivers/net/wan/lmc/lmc_debug.h | |||
| @@ -38,15 +38,15 @@ | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | #ifdef DEBUG | 40 | #ifdef DEBUG |
| 41 | extern u_int32_t lmcEventLogIndex; | 41 | extern u32 lmcEventLogIndex; |
| 42 | extern u_int32_t lmcEventLogBuf[LMC_EVENTLOGSIZE * LMC_EVENTLOGARGS]; | 42 | extern u32 lmcEventLogBuf[LMC_EVENTLOGSIZE * LMC_EVENTLOGARGS]; |
| 43 | #define LMC_EVENT_LOG(x, y, z) lmcEventLog((x), (y), (z)) | 43 | #define LMC_EVENT_LOG(x, y, z) lmcEventLog((x), (y), (z)) |
| 44 | #else | 44 | #else |
| 45 | #define LMC_EVENT_LOG(x,y,z) | 45 | #define LMC_EVENT_LOG(x,y,z) |
| 46 | #endif /* end ifdef _DBG_EVENTLOG */ | 46 | #endif /* end ifdef _DBG_EVENTLOG */ |
| 47 | 47 | ||
| 48 | void lmcConsoleLog(char *type, unsigned char *ucData, int iLen); | 48 | void lmcConsoleLog(char *type, unsigned char *ucData, int iLen); |
| 49 | void lmcEventLog (u_int32_t EventNum, u_int32_t arg2, u_int32_t arg3); | 49 | void lmcEventLog(u32 EventNum, u32 arg2, u32 arg3); |
| 50 | void lmc_trace(struct net_device *dev, char *msg); | 50 | void lmc_trace(struct net_device *dev, char *msg); |
| 51 | 51 | ||
| 52 | #endif | 52 | #endif |
diff --git a/drivers/net/wan/lmc/lmc_ioctl.h b/drivers/net/wan/lmc/lmc_ioctl.h index 57dd861cd3db..72fb113a44ca 100644 --- a/drivers/net/wan/lmc/lmc_ioctl.h +++ b/drivers/net/wan/lmc/lmc_ioctl.h | |||
| @@ -61,7 +61,7 @@ | |||
| 61 | /* | 61 | /* |
| 62 | * IFTYPE defines | 62 | * IFTYPE defines |
| 63 | */ | 63 | */ |
| 64 | #define LMC_PPP 1 /* use sppp interface */ | 64 | #define LMC_PPP 1 /* use generic HDLC interface */ |
| 65 | #define LMC_NET 2 /* use direct net interface */ | 65 | #define LMC_NET 2 /* use direct net interface */ |
| 66 | #define LMC_RAW 3 /* use direct net interface */ | 66 | #define LMC_RAW 3 /* use direct net interface */ |
| 67 | 67 | ||
diff --git a/drivers/net/wan/lmc/lmc_main.c b/drivers/net/wan/lmc/lmc_main.c index 62133cee446a..f80640f5a744 100644 --- a/drivers/net/wan/lmc/lmc_main.c +++ b/drivers/net/wan/lmc/lmc_main.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 1997-2000 LAN Media Corporation (LMC) | 2 | * Copyright (c) 1997-2000 LAN Media Corporation (LMC) |
| 3 | * All rights reserved. www.lanmedia.com | 3 | * All rights reserved. www.lanmedia.com |
| 4 | * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl> | ||
| 4 | * | 5 | * |
| 5 | * This code is written by: | 6 | * This code is written by: |
| 6 | * Andrew Stanley-Jones (asj@cban.com) | 7 | * Andrew Stanley-Jones (asj@cban.com) |
| @@ -36,8 +37,6 @@ | |||
| 36 | * | 37 | * |
| 37 | */ | 38 | */ |
| 38 | 39 | ||
| 39 | /* $Id: lmc_main.c,v 1.36 2000/04/11 05:25:25 asj Exp $ */ | ||
| 40 | |||
| 41 | #include <linux/kernel.h> | 40 | #include <linux/kernel.h> |
| 42 | #include <linux/module.h> | 41 | #include <linux/module.h> |
| 43 | #include <linux/string.h> | 42 | #include <linux/string.h> |
| @@ -49,6 +48,7 @@ | |||
| 49 | #include <linux/interrupt.h> | 48 | #include <linux/interrupt.h> |
| 50 | #include <linux/pci.h> | 49 | #include <linux/pci.h> |
| 51 | #include <linux/delay.h> | 50 | #include <linux/delay.h> |
| 51 | #include <linux/hdlc.h> | ||
| 52 | #include <linux/init.h> | 52 | #include <linux/init.h> |
| 53 | #include <linux/in.h> | 53 | #include <linux/in.h> |
| 54 | #include <linux/if_arp.h> | 54 | #include <linux/if_arp.h> |
| @@ -57,9 +57,6 @@ | |||
| 57 | #include <linux/skbuff.h> | 57 | #include <linux/skbuff.h> |
| 58 | #include <linux/inet.h> | 58 | #include <linux/inet.h> |
| 59 | #include <linux/bitops.h> | 59 | #include <linux/bitops.h> |
| 60 | |||
| 61 | #include <net/syncppp.h> | ||
| 62 | |||
| 63 | #include <asm/processor.h> /* Processor type for cache alignment. */ | 60 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
| 64 | #include <asm/io.h> | 61 | #include <asm/io.h> |
| 65 | #include <asm/dma.h> | 62 | #include <asm/dma.h> |
| @@ -78,8 +75,6 @@ | |||
| 78 | #include "lmc_debug.h" | 75 | #include "lmc_debug.h" |
| 79 | #include "lmc_proto.h" | 76 | #include "lmc_proto.h" |
| 80 | 77 | ||
| 81 | static int lmc_first_load = 0; | ||
| 82 | |||
| 83 | static int LMC_PKT_BUF_SZ = 1542; | 78 | static int LMC_PKT_BUF_SZ = 1542; |
| 84 | 79 | ||
| 85 | static struct pci_device_id lmc_pci_tbl[] = { | 80 | static struct pci_device_id lmc_pci_tbl[] = { |
| @@ -91,11 +86,10 @@ static struct pci_device_id lmc_pci_tbl[] = { | |||
| 91 | }; | 86 | }; |
| 92 | 87 | ||
| 93 | MODULE_DEVICE_TABLE(pci, lmc_pci_tbl); | 88 | MODULE_DEVICE_TABLE(pci, lmc_pci_tbl); |
| 94 | MODULE_LICENSE("GPL"); | 89 | MODULE_LICENSE("GPL v2"); |
| 95 | 90 | ||
| 96 | 91 | ||
| 97 | static int lmc_start_xmit(struct sk_buff *skb, struct net_device *dev); | 92 | static int lmc_start_xmit(struct sk_buff *skb, struct net_device *dev); |
| 98 | static int lmc_start_xmit(struct sk_buff *skb, struct net_device *dev); | ||
| 99 | static int lmc_rx (struct net_device *dev); | 93 | static int lmc_rx (struct net_device *dev); |
| 100 | static int lmc_open(struct net_device *dev); | 94 | static int lmc_open(struct net_device *dev); |
| 101 | static int lmc_close(struct net_device *dev); | 95 | static int lmc_close(struct net_device *dev); |
| @@ -114,20 +108,14 @@ static void lmc_driver_timeout(struct net_device *dev); | |||
| 114 | * linux reserves 16 device specific IOCTLs. We call them | 108 | * linux reserves 16 device specific IOCTLs. We call them |
| 115 | * LMCIOC* to control various bits of our world. | 109 | * LMCIOC* to control various bits of our world. |
| 116 | */ | 110 | */ |
| 117 | int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | 111 | int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ |
| 118 | { | 112 | { |
| 119 | lmc_softc_t *sc; | 113 | lmc_softc_t *sc = dev_to_sc(dev); |
| 120 | lmc_ctl_t ctl; | 114 | lmc_ctl_t ctl; |
| 121 | int ret; | 115 | int ret = -EOPNOTSUPP; |
| 122 | u_int16_t regVal; | 116 | u16 regVal; |
| 123 | unsigned long flags; | 117 | unsigned long flags; |
| 124 | 118 | ||
| 125 | struct sppp *sp; | ||
| 126 | |||
| 127 | ret = -EOPNOTSUPP; | ||
| 128 | |||
| 129 | sc = dev->priv; | ||
| 130 | |||
| 131 | lmc_trace(dev, "lmc_ioctl in"); | 119 | lmc_trace(dev, "lmc_ioctl in"); |
| 132 | 120 | ||
| 133 | /* | 121 | /* |
| @@ -149,7 +137,6 @@ int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | |||
| 149 | break; | 137 | break; |
| 150 | 138 | ||
| 151 | case LMCIOCSINFO: /*fold01*/ | 139 | case LMCIOCSINFO: /*fold01*/ |
| 152 | sp = &((struct ppp_device *) dev)->sppp; | ||
| 153 | if (!capable(CAP_NET_ADMIN)) { | 140 | if (!capable(CAP_NET_ADMIN)) { |
| 154 | ret = -EPERM; | 141 | ret = -EPERM; |
| 155 | break; | 142 | break; |
| @@ -175,25 +162,20 @@ int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | |||
| 175 | sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE; | 162 | sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE; |
| 176 | } | 163 | } |
| 177 | 164 | ||
| 178 | if (ctl.keepalive_onoff == LMC_CTL_OFF) | ||
| 179 | sp->pp_flags &= ~PP_KEEPALIVE; /* Turn off */ | ||
| 180 | else | ||
| 181 | sp->pp_flags |= PP_KEEPALIVE; /* Turn on */ | ||
| 182 | |||
| 183 | ret = 0; | 165 | ret = 0; |
| 184 | break; | 166 | break; |
| 185 | 167 | ||
| 186 | case LMCIOCIFTYPE: /*fold01*/ | 168 | case LMCIOCIFTYPE: /*fold01*/ |
| 187 | { | 169 | { |
| 188 | u_int16_t old_type = sc->if_type; | 170 | u16 old_type = sc->if_type; |
| 189 | u_int16_t new_type; | 171 | u16 new_type; |
| 190 | 172 | ||
| 191 | if (!capable(CAP_NET_ADMIN)) { | 173 | if (!capable(CAP_NET_ADMIN)) { |
| 192 | ret = -EPERM; | 174 | ret = -EPERM; |
| 193 | break; | 175 | break; |
| 194 | } | 176 | } |
| 195 | 177 | ||
| 196 | if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u_int16_t))) { | 178 | if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) { |
| 197 | ret = -EFAULT; | 179 | ret = -EFAULT; |
| 198 | break; | 180 | break; |
| 199 | } | 181 | } |
| @@ -206,15 +188,11 @@ int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | |||
| 206 | } | 188 | } |
| 207 | 189 | ||
| 208 | lmc_proto_close(sc); | 190 | lmc_proto_close(sc); |
| 209 | lmc_proto_detach(sc); | ||
| 210 | 191 | ||
| 211 | sc->if_type = new_type; | 192 | sc->if_type = new_type; |
| 212 | // lmc_proto_init(sc); | ||
| 213 | lmc_proto_attach(sc); | 193 | lmc_proto_attach(sc); |
| 214 | lmc_proto_open(sc); | 194 | ret = lmc_proto_open(sc); |
| 215 | 195 | break; | |
| 216 | ret = 0 ; | ||
| 217 | break ; | ||
| 218 | } | 196 | } |
| 219 | 197 | ||
| 220 | case LMCIOCGETXINFO: /*fold01*/ | 198 | case LMCIOCGETXINFO: /*fold01*/ |
| @@ -241,51 +219,53 @@ int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | |||
| 241 | 219 | ||
| 242 | break; | 220 | break; |
| 243 | 221 | ||
| 244 | case LMCIOCGETLMCSTATS: /*fold01*/ | 222 | case LMCIOCGETLMCSTATS: |
| 245 | if (sc->lmc_cardtype == LMC_CARDTYPE_T1){ | 223 | if (sc->lmc_cardtype == LMC_CARDTYPE_T1) { |
| 246 | lmc_mii_writereg (sc, 0, 17, T1FRAMER_FERR_LSB); | 224 | lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB); |
| 247 | sc->stats.framingBitErrorCount += | 225 | sc->extra_stats.framingBitErrorCount += |
| 248 | lmc_mii_readreg (sc, 0, 18) & 0xff; | 226 | lmc_mii_readreg(sc, 0, 18) & 0xff; |
| 249 | lmc_mii_writereg (sc, 0, 17, T1FRAMER_FERR_MSB); | 227 | lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB); |
| 250 | sc->stats.framingBitErrorCount += | 228 | sc->extra_stats.framingBitErrorCount += |
| 251 | (lmc_mii_readreg (sc, 0, 18) & 0xff) << 8; | 229 | (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8; |
| 252 | lmc_mii_writereg (sc, 0, 17, T1FRAMER_LCV_LSB); | 230 | lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB); |
| 253 | sc->stats.lineCodeViolationCount += | 231 | sc->extra_stats.lineCodeViolationCount += |
| 254 | lmc_mii_readreg (sc, 0, 18) & 0xff; | 232 | lmc_mii_readreg(sc, 0, 18) & 0xff; |
| 255 | lmc_mii_writereg (sc, 0, 17, T1FRAMER_LCV_MSB); | 233 | lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB); |
| 256 | sc->stats.lineCodeViolationCount += | 234 | sc->extra_stats.lineCodeViolationCount += |
| 257 | (lmc_mii_readreg (sc, 0, 18) & 0xff) << 8; | 235 | (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8; |
| 258 | lmc_mii_writereg (sc, 0, 17, T1FRAMER_AERR); | 236 | lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR); |
| 259 | regVal = lmc_mii_readreg (sc, 0, 18) & 0xff; | 237 | regVal = lmc_mii_readreg(sc, 0, 18) & 0xff; |
| 260 | 238 | ||
| 261 | sc->stats.lossOfFrameCount += | 239 | sc->extra_stats.lossOfFrameCount += |
| 262 | (regVal & T1FRAMER_LOF_MASK) >> 4; | 240 | (regVal & T1FRAMER_LOF_MASK) >> 4; |
| 263 | sc->stats.changeOfFrameAlignmentCount += | 241 | sc->extra_stats.changeOfFrameAlignmentCount += |
| 264 | (regVal & T1FRAMER_COFA_MASK) >> 2; | 242 | (regVal & T1FRAMER_COFA_MASK) >> 2; |
| 265 | sc->stats.severelyErroredFrameCount += | 243 | sc->extra_stats.severelyErroredFrameCount += |
| 266 | regVal & T1FRAMER_SEF_MASK; | 244 | regVal & T1FRAMER_SEF_MASK; |
| 267 | } | 245 | } |
| 268 | 246 | if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats, | |
| 269 | if (copy_to_user(ifr->ifr_data, &sc->stats, | 247 | sizeof(sc->lmc_device->stats)) || |
| 270 | sizeof (struct lmc_statistics))) | 248 | copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats), |
| 271 | ret = -EFAULT; | 249 | &sc->extra_stats, sizeof(sc->extra_stats))) |
| 272 | else | 250 | ret = -EFAULT; |
| 273 | ret = 0; | 251 | else |
| 274 | break; | 252 | ret = 0; |
| 253 | break; | ||
| 275 | 254 | ||
| 276 | case LMCIOCCLEARLMCSTATS: /*fold01*/ | 255 | case LMCIOCCLEARLMCSTATS: |
| 277 | if (!capable(CAP_NET_ADMIN)){ | 256 | if (!capable(CAP_NET_ADMIN)) { |
| 278 | ret = -EPERM; | 257 | ret = -EPERM; |
| 279 | break; | 258 | break; |
| 280 | } | 259 | } |
| 281 | 260 | ||
| 282 | memset (&sc->stats, 0, sizeof (struct lmc_statistics)); | 261 | memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats)); |
| 283 | sc->stats.check = STATCHECK; | 262 | memset(&sc->extra_stats, 0, sizeof(sc->extra_stats)); |
| 284 | sc->stats.version_size = (DRIVER_VERSION << 16) + | 263 | sc->extra_stats.check = STATCHECK; |
| 285 | sizeof (struct lmc_statistics); | 264 | sc->extra_stats.version_size = (DRIVER_VERSION << 16) + |
| 286 | sc->stats.lmc_cardtype = sc->lmc_cardtype; | 265 | sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats); |
| 287 | ret = 0; | 266 | sc->extra_stats.lmc_cardtype = sc->lmc_cardtype; |
| 288 | break; | 267 | ret = 0; |
| 268 | break; | ||
| 289 | 269 | ||
| 290 | case LMCIOCSETCIRCUIT: /*fold01*/ | 270 | case LMCIOCSETCIRCUIT: /*fold01*/ |
| 291 | if (!capable(CAP_NET_ADMIN)){ | 271 | if (!capable(CAP_NET_ADMIN)){ |
| @@ -330,7 +310,8 @@ int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | |||
| 330 | ret = -EFAULT; | 310 | ret = -EFAULT; |
| 331 | break; | 311 | break; |
| 332 | } | 312 | } |
| 333 | if (copy_to_user(ifr->ifr_data + sizeof (u32), lmcEventLogBuf, sizeof (lmcEventLogBuf))) | 313 | if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf, |
| 314 | sizeof(lmcEventLogBuf))) | ||
| 334 | ret = -EFAULT; | 315 | ret = -EFAULT; |
| 335 | else | 316 | else |
| 336 | ret = 0; | 317 | ret = 0; |
| @@ -641,14 +622,12 @@ int lmc_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/ | |||
| 641 | /* the watchdog process that cruises around */ | 622 | /* the watchdog process that cruises around */ |
| 642 | static void lmc_watchdog (unsigned long data) /*fold00*/ | 623 | static void lmc_watchdog (unsigned long data) /*fold00*/ |
| 643 | { | 624 | { |
| 644 | struct net_device *dev = (struct net_device *) data; | 625 | struct net_device *dev = (struct net_device *)data; |
| 645 | lmc_softc_t *sc; | 626 | lmc_softc_t *sc = dev_to_sc(dev); |
| 646 | int link_status; | 627 | int link_status; |
| 647 | u_int32_t ticks; | 628 | u32 ticks; |
| 648 | unsigned long flags; | 629 | unsigned long flags; |
| 649 | 630 | ||
| 650 | sc = dev->priv; | ||
| 651 | |||
| 652 | lmc_trace(dev, "lmc_watchdog in"); | 631 | lmc_trace(dev, "lmc_watchdog in"); |
| 653 | 632 | ||
| 654 | spin_lock_irqsave(&sc->lmc_lock, flags); | 633 | spin_lock_irqsave(&sc->lmc_lock, flags); |
| @@ -677,22 +656,22 @@ static void lmc_watchdog (unsigned long data) /*fold00*/ | |||
| 677 | * check for a transmit interrupt timeout | 656 | * check for a transmit interrupt timeout |
| 678 | * Has the packet xmt vs xmt serviced threshold been exceeded */ | 657 | * Has the packet xmt vs xmt serviced threshold been exceeded */ |
| 679 | if (sc->lmc_taint_tx == sc->lastlmc_taint_tx && | 658 | if (sc->lmc_taint_tx == sc->lastlmc_taint_tx && |
| 680 | sc->stats.tx_packets > sc->lasttx_packets && | 659 | sc->lmc_device->stats.tx_packets > sc->lasttx_packets && |
| 681 | sc->tx_TimeoutInd == 0) | 660 | sc->tx_TimeoutInd == 0) |
| 682 | { | 661 | { |
| 683 | 662 | ||
| 684 | /* wait for the watchdog to come around again */ | 663 | /* wait for the watchdog to come around again */ |
| 685 | sc->tx_TimeoutInd = 1; | 664 | sc->tx_TimeoutInd = 1; |
| 686 | } | 665 | } |
| 687 | else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx && | 666 | else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx && |
| 688 | sc->stats.tx_packets > sc->lasttx_packets && | 667 | sc->lmc_device->stats.tx_packets > sc->lasttx_packets && |
| 689 | sc->tx_TimeoutInd) | 668 | sc->tx_TimeoutInd) |
| 690 | { | 669 | { |
| 691 | 670 | ||
| 692 | LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0); | 671 | LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0); |
| 693 | 672 | ||
| 694 | sc->tx_TimeoutDisplay = 1; | 673 | sc->tx_TimeoutDisplay = 1; |
| 695 | sc->stats.tx_TimeoutCnt++; | 674 | sc->extra_stats.tx_TimeoutCnt++; |
| 696 | 675 | ||
| 697 | /* DEC chip is stuck, hit it with a RESET!!!! */ | 676 | /* DEC chip is stuck, hit it with a RESET!!!! */ |
| 698 | lmc_running_reset (dev); | 677 | lmc_running_reset (dev); |
| @@ -712,13 +691,11 @@ static void lmc_watchdog (unsigned long data) /*fold00*/ | |||
| 712 | /* reset the transmit timeout detection flag */ | 691 | /* reset the transmit timeout detection flag */ |
| 713 | sc->tx_TimeoutInd = 0; | 692 | sc->tx_TimeoutInd = 0; |
| 714 | sc->lastlmc_taint_tx = sc->lmc_taint_tx; | 693 | sc->lastlmc_taint_tx = sc->lmc_taint_tx; |
| 715 | sc->lasttx_packets = sc->stats.tx_packets; | 694 | sc->lasttx_packets = sc->lmc_device->stats.tx_packets; |
| 716 | } | 695 | } else { |
| 717 | else | ||
| 718 | { | ||
| 719 | sc->tx_TimeoutInd = 0; | 696 | sc->tx_TimeoutInd = 0; |
| 720 | sc->lastlmc_taint_tx = sc->lmc_taint_tx; | 697 | sc->lastlmc_taint_tx = sc->lmc_taint_tx; |
| 721 | sc->lasttx_packets = sc->stats.tx_packets; | 698 | sc->lasttx_packets = sc->lmc_device->stats.tx_packets; |
| 722 | } | 699 | } |
| 723 | 700 | ||
| 724 | /* --- end time out check ----------------------------------- */ | 701 | /* --- end time out check ----------------------------------- */ |
| @@ -748,19 +725,7 @@ static void lmc_watchdog (unsigned long data) /*fold00*/ | |||
| 748 | sc->last_link_status = 1; | 725 | sc->last_link_status = 1; |
| 749 | /* lmc_reset (sc); Again why reset??? */ | 726 | /* lmc_reset (sc); Again why reset??? */ |
| 750 | 727 | ||
| 751 | /* Inform the world that link protocol is back up. */ | ||
| 752 | netif_carrier_on(dev); | 728 | netif_carrier_on(dev); |
| 753 | |||
| 754 | /* Now we have to tell the syncppp that we had an outage | ||
| 755 | * and that it should deal. Calling sppp_reopen here | ||
| 756 | * should do the trick, but we may have to call sppp_close | ||
| 757 | * when the link goes down, and call sppp_open here. | ||
| 758 | * Subject to more testing. | ||
| 759 | * --bbraun | ||
| 760 | */ | ||
| 761 | |||
| 762 | lmc_proto_reopen(sc); | ||
| 763 | |||
| 764 | } | 729 | } |
| 765 | 730 | ||
| 766 | /* Call media specific watchdog functions */ | 731 | /* Call media specific watchdog functions */ |
| @@ -816,114 +781,93 @@ kick_timer: | |||
| 816 | 781 | ||
| 817 | } | 782 | } |
| 818 | 783 | ||
| 819 | static void lmc_setup(struct net_device * const dev) /*fold00*/ | 784 | static int lmc_attach(struct net_device *dev, unsigned short encoding, |
| 785 | unsigned short parity) | ||
| 820 | { | 786 | { |
| 821 | lmc_trace(dev, "lmc_setup in"); | 787 | if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT) |
| 822 | 788 | return 0; | |
| 823 | dev->type = ARPHRD_HDLC; | 789 | return -EINVAL; |
| 824 | dev->hard_start_xmit = lmc_start_xmit; | ||
| 825 | dev->open = lmc_open; | ||
| 826 | dev->stop = lmc_close; | ||
| 827 | dev->get_stats = lmc_get_stats; | ||
| 828 | dev->do_ioctl = lmc_ioctl; | ||
| 829 | dev->tx_timeout = lmc_driver_timeout; | ||
| 830 | dev->watchdog_timeo = (HZ); /* 1 second */ | ||
| 831 | |||
| 832 | lmc_trace(dev, "lmc_setup out"); | ||
| 833 | } | 790 | } |
| 834 | 791 | ||
| 835 | |||
| 836 | static int __devinit lmc_init_one(struct pci_dev *pdev, | 792 | static int __devinit lmc_init_one(struct pci_dev *pdev, |
| 837 | const struct pci_device_id *ent) | 793 | const struct pci_device_id *ent) |
| 838 | { | 794 | { |
| 839 | struct net_device *dev; | 795 | lmc_softc_t *sc; |
| 840 | lmc_softc_t *sc; | 796 | struct net_device *dev; |
| 841 | u16 subdevice; | 797 | u16 subdevice; |
| 842 | u_int16_t AdapModelNum; | 798 | u16 AdapModelNum; |
| 843 | int err = -ENOMEM; | 799 | int err; |
| 844 | static int cards_found; | 800 | static int cards_found; |
| 845 | #ifndef GCOM | 801 | |
| 846 | /* We name by type not by vendor */ | 802 | /* lmc_trace(dev, "lmc_init_one in"); */ |
| 847 | static const char lmcname[] = "hdlc%d"; | 803 | |
| 848 | #else | 804 | err = pci_enable_device(pdev); |
| 849 | /* | 805 | if (err) { |
| 850 | * GCOM uses LMC vendor name so that clients can know which card | 806 | printk(KERN_ERR "lmc: pci enable failed: %d\n", err); |
| 851 | * to attach to. | 807 | return err; |
| 852 | */ | 808 | } |
| 853 | static const char lmcname[] = "lmc%d"; | ||
| 854 | #endif | ||
| 855 | |||
| 856 | |||
| 857 | /* | ||
| 858 | * Allocate our own device structure | ||
| 859 | */ | ||
| 860 | dev = alloc_netdev(sizeof(lmc_softc_t), lmcname, lmc_setup); | ||
| 861 | if (!dev) { | ||
| 862 | printk (KERN_ERR "lmc:alloc_netdev for device failed\n"); | ||
| 863 | goto out1; | ||
| 864 | } | ||
| 865 | |||
| 866 | lmc_trace(dev, "lmc_init_one in"); | ||
| 867 | |||
| 868 | err = pci_enable_device(pdev); | ||
| 869 | if (err) { | ||
| 870 | printk(KERN_ERR "lmc: pci enable failed:%d\n", err); | ||
| 871 | goto out2; | ||
| 872 | } | ||
| 873 | |||
| 874 | if (pci_request_regions(pdev, "lmc")) { | ||
| 875 | printk(KERN_ERR "lmc: pci_request_region failed\n"); | ||
| 876 | err = -EIO; | ||
| 877 | goto out3; | ||
| 878 | } | ||
| 879 | |||
| 880 | pci_set_drvdata(pdev, dev); | ||
| 881 | |||
| 882 | if(lmc_first_load == 0){ | ||
| 883 | printk(KERN_INFO "Lan Media Corporation WAN Driver Version %d.%d.%d\n", | ||
| 884 | DRIVER_MAJOR_VERSION, DRIVER_MINOR_VERSION,DRIVER_SUB_VERSION); | ||
| 885 | lmc_first_load = 1; | ||
| 886 | } | ||
| 887 | |||
| 888 | sc = dev->priv; | ||
| 889 | sc->lmc_device = dev; | ||
| 890 | sc->name = dev->name; | ||
| 891 | |||
| 892 | /* Initialize the sppp layer */ | ||
| 893 | /* An ioctl can cause a subsequent detach for raw frame interface */ | ||
| 894 | dev->ml_priv = sc; | ||
| 895 | sc->if_type = LMC_PPP; | ||
| 896 | sc->check = 0xBEAFCAFE; | ||
| 897 | dev->base_addr = pci_resource_start(pdev, 0); | ||
| 898 | dev->irq = pdev->irq; | ||
| 899 | |||
| 900 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
| 901 | |||
| 902 | /* | ||
| 903 | * This will get the protocol layer ready and do any 1 time init's | ||
| 904 | * Must have a valid sc and dev structure | ||
| 905 | */ | ||
| 906 | lmc_proto_init(sc); | ||
| 907 | |||
| 908 | lmc_proto_attach(sc); | ||
| 909 | 809 | ||
| 910 | /* | 810 | err = pci_request_regions(pdev, "lmc"); |
| 911 | * Why were we changing this??? | 811 | if (err) { |
| 912 | dev->tx_queue_len = 100; | 812 | printk(KERN_ERR "lmc: pci_request_region failed\n"); |
| 913 | */ | 813 | goto err_req_io; |
| 814 | } | ||
| 914 | 815 | ||
| 915 | /* Init the spin lock so can call it latter */ | 816 | /* |
| 817 | * Allocate our own device structure | ||
| 818 | */ | ||
| 819 | sc = kzalloc(sizeof(lmc_softc_t), GFP_KERNEL); | ||
| 820 | if (!sc) { | ||
| 821 | err = -ENOMEM; | ||
| 822 | goto err_kzalloc; | ||
| 823 | } | ||
| 916 | 824 | ||
| 917 | spin_lock_init(&sc->lmc_lock); | 825 | dev = alloc_hdlcdev(sc); |
| 918 | pci_set_master(pdev); | 826 | if (!dev) { |
| 827 | printk(KERN_ERR "lmc:alloc_netdev for device failed\n"); | ||
| 828 | goto err_hdlcdev; | ||
| 829 | } | ||
| 919 | 830 | ||
| 920 | printk ("%s: detected at %lx, irq %d\n", dev->name, | ||
| 921 | dev->base_addr, dev->irq); | ||
| 922 | 831 | ||
| 923 | if (register_netdev (dev) != 0) { | 832 | dev->type = ARPHRD_HDLC; |
| 924 | printk (KERN_ERR "%s: register_netdev failed.\n", dev->name); | 833 | dev_to_hdlc(dev)->xmit = lmc_start_xmit; |
| 925 | goto out4; | 834 | dev_to_hdlc(dev)->attach = lmc_attach; |
| 926 | } | 835 | dev->open = lmc_open; |
| 836 | dev->stop = lmc_close; | ||
| 837 | dev->get_stats = lmc_get_stats; | ||
| 838 | dev->do_ioctl = lmc_ioctl; | ||
| 839 | dev->tx_timeout = lmc_driver_timeout; | ||
| 840 | dev->watchdog_timeo = HZ; /* 1 second */ | ||
| 841 | dev->tx_queue_len = 100; | ||
| 842 | sc->lmc_device = dev; | ||
| 843 | sc->name = dev->name; | ||
| 844 | sc->if_type = LMC_PPP; | ||
| 845 | sc->check = 0xBEAFCAFE; | ||
| 846 | dev->base_addr = pci_resource_start(pdev, 0); | ||
| 847 | dev->irq = pdev->irq; | ||
| 848 | pci_set_drvdata(pdev, dev); | ||
| 849 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
| 850 | |||
| 851 | /* | ||
| 852 | * This will get the protocol layer ready and do any 1 time init's | ||
| 853 | * Must have a valid sc and dev structure | ||
| 854 | */ | ||
| 855 | lmc_proto_attach(sc); | ||
| 856 | |||
| 857 | /* Init the spin lock so can call it latter */ | ||
| 858 | |||
| 859 | spin_lock_init(&sc->lmc_lock); | ||
| 860 | pci_set_master(pdev); | ||
| 861 | |||
| 862 | printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name, | ||
| 863 | dev->base_addr, dev->irq); | ||
| 864 | |||
| 865 | err = register_hdlc_device(dev); | ||
| 866 | if (err) { | ||
| 867 | printk(KERN_ERR "%s: register_netdev failed.\n", dev->name); | ||
| 868 | free_netdev(dev); | ||
| 869 | goto err_hdlcdev; | ||
| 870 | } | ||
| 927 | 871 | ||
| 928 | sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN; | 872 | sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN; |
| 929 | sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT; | 873 | sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT; |
| @@ -939,27 +883,27 @@ static int __devinit lmc_init_one(struct pci_dev *pdev, | |||
| 939 | 883 | ||
| 940 | switch (subdevice) { | 884 | switch (subdevice) { |
| 941 | case PCI_DEVICE_ID_LMC_HSSI: | 885 | case PCI_DEVICE_ID_LMC_HSSI: |
| 942 | printk ("%s: LMC HSSI\n", dev->name); | 886 | printk(KERN_INFO "%s: LMC HSSI\n", dev->name); |
| 943 | sc->lmc_cardtype = LMC_CARDTYPE_HSSI; | 887 | sc->lmc_cardtype = LMC_CARDTYPE_HSSI; |
| 944 | sc->lmc_media = &lmc_hssi_media; | 888 | sc->lmc_media = &lmc_hssi_media; |
| 945 | break; | 889 | break; |
| 946 | case PCI_DEVICE_ID_LMC_DS3: | 890 | case PCI_DEVICE_ID_LMC_DS3: |
| 947 | printk ("%s: LMC DS3\n", dev->name); | 891 | printk(KERN_INFO "%s: LMC DS3\n", dev->name); |
| 948 | sc->lmc_cardtype = LMC_CARDTYPE_DS3; | 892 | sc->lmc_cardtype = LMC_CARDTYPE_DS3; |
| 949 | sc->lmc_media = &lmc_ds3_media; | 893 | sc->lmc_media = &lmc_ds3_media; |
| 950 | break; | 894 | break; |
| 951 | case PCI_DEVICE_ID_LMC_SSI: | 895 | case PCI_DEVICE_ID_LMC_SSI: |
| 952 | printk ("%s: LMC SSI\n", dev->name); | 896 | printk(KERN_INFO "%s: LMC SSI\n", dev->name); |
| 953 | sc->lmc_cardtype = LMC_CARDTYPE_SSI; | 897 | sc->lmc_cardtype = LMC_CARDTYPE_SSI; |
| 954 | sc->lmc_media = &lmc_ssi_media; | 898 | sc->lmc_media = &lmc_ssi_media; |
| 955 | break; | 899 | break; |
| 956 | case PCI_DEVICE_ID_LMC_T1: | 900 | case PCI_DEVICE_ID_LMC_T1: |
| 957 | printk ("%s: LMC T1\n", dev->name); | 901 | printk(KERN_INFO "%s: LMC T1\n", dev->name); |
| 958 | sc->lmc_cardtype = LMC_CARDTYPE_T1; | 902 | sc->lmc_cardtype = LMC_CARDTYPE_T1; |
| 959 | sc->lmc_media = &lmc_t1_media; | 903 | sc->lmc_media = &lmc_t1_media; |
| 960 | break; | 904 | break; |
| 961 | default: | 905 | default: |
| 962 | printk (KERN_WARNING "%s: LMC UNKOWN CARD!\n", dev->name); | 906 | printk(KERN_WARNING "%s: LMC UNKOWN CARD!\n", dev->name); |
| 963 | break; | 907 | break; |
| 964 | } | 908 | } |
| 965 | 909 | ||
| @@ -977,32 +921,28 @@ static int __devinit lmc_init_one(struct pci_dev *pdev, | |||
| 977 | */ | 921 | */ |
| 978 | AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4; | 922 | AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4; |
| 979 | 923 | ||
| 980 | if ((AdapModelNum == LMC_ADAP_T1 | 924 | if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */ |
| 981 | && subdevice == PCI_DEVICE_ID_LMC_T1) || /* detect LMC1200 */ | 925 | subdevice != PCI_DEVICE_ID_LMC_T1) && |
| 982 | (AdapModelNum == LMC_ADAP_SSI | 926 | (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */ |
| 983 | && subdevice == PCI_DEVICE_ID_LMC_SSI) || /* detect LMC1000 */ | 927 | subdevice != PCI_DEVICE_ID_LMC_SSI) && |
| 984 | (AdapModelNum == LMC_ADAP_DS3 | 928 | (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */ |
| 985 | && subdevice == PCI_DEVICE_ID_LMC_DS3) || /* detect LMC5245 */ | 929 | subdevice != PCI_DEVICE_ID_LMC_DS3) && |
| 986 | (AdapModelNum == LMC_ADAP_HSSI | 930 | (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */ |
| 987 | && subdevice == PCI_DEVICE_ID_LMC_HSSI)) | 931 | subdevice != PCI_DEVICE_ID_LMC_HSSI)) |
| 988 | { /* detect LMC5200 */ | 932 | printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI" |
| 933 | " Subsystem ID = 0x%04x\n", | ||
| 934 | dev->name, AdapModelNum, subdevice); | ||
| 989 | 935 | ||
| 990 | } | ||
| 991 | else { | ||
| 992 | printk ("%s: Model number (%d) miscompare for PCI Subsystem ID = 0x%04x\n", | ||
| 993 | dev->name, AdapModelNum, subdevice); | ||
| 994 | // return (NULL); | ||
| 995 | } | ||
| 996 | /* | 936 | /* |
| 997 | * reset clock | 937 | * reset clock |
| 998 | */ | 938 | */ |
| 999 | LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL); | 939 | LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL); |
| 1000 | 940 | ||
| 1001 | sc->board_idx = cards_found++; | 941 | sc->board_idx = cards_found++; |
| 1002 | sc->stats.check = STATCHECK; | 942 | sc->extra_stats.check = STATCHECK; |
| 1003 | sc->stats.version_size = (DRIVER_VERSION << 16) + | 943 | sc->extra_stats.version_size = (DRIVER_VERSION << 16) + |
| 1004 | sizeof (struct lmc_statistics); | 944 | sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats); |
| 1005 | sc->stats.lmc_cardtype = sc->lmc_cardtype; | 945 | sc->extra_stats.lmc_cardtype = sc->lmc_cardtype; |
| 1006 | 946 | ||
| 1007 | sc->lmc_ok = 0; | 947 | sc->lmc_ok = 0; |
| 1008 | sc->last_link_status = 0; | 948 | sc->last_link_status = 0; |
| @@ -1010,58 +950,51 @@ static int __devinit lmc_init_one(struct pci_dev *pdev, | |||
| 1010 | lmc_trace(dev, "lmc_init_one out"); | 950 | lmc_trace(dev, "lmc_init_one out"); |
| 1011 | return 0; | 951 | return 0; |
| 1012 | 952 | ||
| 1013 | out4: | 953 | err_hdlcdev: |
| 1014 | lmc_proto_detach(sc); | 954 | pci_set_drvdata(pdev, NULL); |
| 1015 | out3: | 955 | kfree(sc); |
| 1016 | if (pdev) { | 956 | err_kzalloc: |
| 1017 | pci_release_regions(pdev); | 957 | pci_release_regions(pdev); |
| 1018 | pci_set_drvdata(pdev, NULL); | 958 | err_req_io: |
| 1019 | } | 959 | pci_disable_device(pdev); |
| 1020 | out2: | 960 | return err; |
| 1021 | free_netdev(dev); | ||
| 1022 | out1: | ||
| 1023 | return err; | ||
| 1024 | } | 961 | } |
| 1025 | 962 | ||
| 1026 | /* | 963 | /* |
| 1027 | * Called from pci when removing module. | 964 | * Called from pci when removing module. |
| 1028 | */ | 965 | */ |
| 1029 | static void __devexit lmc_remove_one (struct pci_dev *pdev) | 966 | static void __devexit lmc_remove_one(struct pci_dev *pdev) |
| 1030 | { | 967 | { |
| 1031 | struct net_device *dev = pci_get_drvdata(pdev); | 968 | struct net_device *dev = pci_get_drvdata(pdev); |
| 1032 | 969 | ||
| 1033 | if (dev) { | 970 | if (dev) { |
| 1034 | lmc_softc_t *sc = dev->priv; | 971 | printk(KERN_DEBUG "%s: removing...\n", dev->name); |
| 1035 | 972 | unregister_hdlc_device(dev); | |
| 1036 | printk("%s: removing...\n", dev->name); | 973 | free_netdev(dev); |
| 1037 | lmc_proto_detach(sc); | 974 | pci_release_regions(pdev); |
| 1038 | unregister_netdev(dev); | 975 | pci_disable_device(pdev); |
| 1039 | free_netdev(dev); | 976 | pci_set_drvdata(pdev, NULL); |
| 1040 | pci_release_regions(pdev); | 977 | } |
| 1041 | pci_disable_device(pdev); | ||
| 1042 | pci_set_drvdata(pdev, NULL); | ||
| 1043 | } | ||
| 1044 | } | 978 | } |
| 1045 | 979 | ||
| 1046 | /* After this is called, packets can be sent. | 980 | /* After this is called, packets can be sent. |
| 1047 | * Does not initialize the addresses | 981 | * Does not initialize the addresses |
| 1048 | */ | 982 | */ |
| 1049 | static int lmc_open (struct net_device *dev) /*fold00*/ | 983 | static int lmc_open(struct net_device *dev) |
| 1050 | { | 984 | { |
| 1051 | lmc_softc_t *sc = dev->priv; | 985 | lmc_softc_t *sc = dev_to_sc(dev); |
| 986 | int err; | ||
| 1052 | 987 | ||
| 1053 | lmc_trace(dev, "lmc_open in"); | 988 | lmc_trace(dev, "lmc_open in"); |
| 1054 | 989 | ||
| 1055 | lmc_led_on(sc, LMC_DS3_LED0); | 990 | lmc_led_on(sc, LMC_DS3_LED0); |
| 1056 | 991 | ||
| 1057 | lmc_dec_reset (sc); | 992 | lmc_dec_reset(sc); |
| 1058 | lmc_reset (sc); | 993 | lmc_reset(sc); |
| 1059 | |||
| 1060 | LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0); | ||
| 1061 | LMC_EVENT_LOG(LMC_EVENT_RESET2, | ||
| 1062 | lmc_mii_readreg (sc, 0, 16), | ||
| 1063 | lmc_mii_readreg (sc, 0, 17)); | ||
| 1064 | 994 | ||
| 995 | LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0); | ||
| 996 | LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16), | ||
| 997 | lmc_mii_readreg(sc, 0, 17)); | ||
| 1065 | 998 | ||
| 1066 | if (sc->lmc_ok){ | 999 | if (sc->lmc_ok){ |
| 1067 | lmc_trace(dev, "lmc_open lmc_ok out"); | 1000 | lmc_trace(dev, "lmc_open lmc_ok out"); |
| @@ -1106,14 +1039,14 @@ static int lmc_open (struct net_device *dev) /*fold00*/ | |||
| 1106 | 1039 | ||
| 1107 | /* dev->flags |= IFF_UP; */ | 1040 | /* dev->flags |= IFF_UP; */ |
| 1108 | 1041 | ||
| 1109 | lmc_proto_open(sc); | 1042 | if ((err = lmc_proto_open(sc)) != 0) |
| 1043 | return err; | ||
| 1110 | 1044 | ||
| 1111 | dev->do_ioctl = lmc_ioctl; | 1045 | dev->do_ioctl = lmc_ioctl; |
| 1112 | 1046 | ||
| 1113 | 1047 | ||
| 1114 | netif_start_queue(dev); | 1048 | netif_start_queue(dev); |
| 1115 | 1049 | sc->extra_stats.tx_tbusy0++; | |
| 1116 | sc->stats.tx_tbusy0++ ; | ||
| 1117 | 1050 | ||
| 1118 | /* | 1051 | /* |
| 1119 | * select what interrupts we want to get | 1052 | * select what interrupts we want to get |
| @@ -1165,8 +1098,7 @@ static int lmc_open (struct net_device *dev) /*fold00*/ | |||
| 1165 | 1098 | ||
| 1166 | static void lmc_running_reset (struct net_device *dev) /*fold00*/ | 1099 | static void lmc_running_reset (struct net_device *dev) /*fold00*/ |
| 1167 | { | 1100 | { |
| 1168 | 1101 | lmc_softc_t *sc = dev_to_sc(dev); | |
| 1169 | lmc_softc_t *sc = (lmc_softc_t *) dev->priv; | ||
| 1170 | 1102 | ||
| 1171 | lmc_trace(dev, "lmc_runnig_reset in"); | 1103 | lmc_trace(dev, "lmc_runnig_reset in"); |
| 1172 | 1104 | ||
| @@ -1184,7 +1116,7 @@ static void lmc_running_reset (struct net_device *dev) /*fold00*/ | |||
| 1184 | netif_wake_queue(dev); | 1116 | netif_wake_queue(dev); |
| 1185 | 1117 | ||
| 1186 | sc->lmc_txfull = 0; | 1118 | sc->lmc_txfull = 0; |
| 1187 | sc->stats.tx_tbusy0++ ; | 1119 | sc->extra_stats.tx_tbusy0++; |
| 1188 | 1120 | ||
| 1189 | sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK; | 1121 | sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK; |
| 1190 | LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask); | 1122 | LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask); |
| @@ -1200,14 +1132,13 @@ static void lmc_running_reset (struct net_device *dev) /*fold00*/ | |||
| 1200 | * This disables the timer for the watchdog and keepalives, | 1132 | * This disables the timer for the watchdog and keepalives, |
| 1201 | * and disables the irq for dev. | 1133 | * and disables the irq for dev. |
| 1202 | */ | 1134 | */ |
| 1203 | static int lmc_close (struct net_device *dev) /*fold00*/ | 1135 | static int lmc_close(struct net_device *dev) |
| 1204 | { | 1136 | { |
| 1205 | /* not calling release_region() as we should */ | 1137 | /* not calling release_region() as we should */ |
| 1206 | lmc_softc_t *sc; | 1138 | lmc_softc_t *sc = dev_to_sc(dev); |
| 1207 | 1139 | ||
| 1208 | lmc_trace(dev, "lmc_close in"); | 1140 | lmc_trace(dev, "lmc_close in"); |
| 1209 | 1141 | ||
| 1210 | sc = dev->priv; | ||
| 1211 | sc->lmc_ok = 0; | 1142 | sc->lmc_ok = 0; |
| 1212 | sc->lmc_media->set_link_status (sc, 0); | 1143 | sc->lmc_media->set_link_status (sc, 0); |
| 1213 | del_timer (&sc->timer); | 1144 | del_timer (&sc->timer); |
| @@ -1215,7 +1146,7 @@ static int lmc_close (struct net_device *dev) /*fold00*/ | |||
| 1215 | lmc_ifdown (dev); | 1146 | lmc_ifdown (dev); |
| 1216 | 1147 | ||
| 1217 | lmc_trace(dev, "lmc_close out"); | 1148 | lmc_trace(dev, "lmc_close out"); |
| 1218 | 1149 | ||
| 1219 | return 0; | 1150 | return 0; |
| 1220 | } | 1151 | } |
| 1221 | 1152 | ||
| @@ -1223,16 +1154,16 @@ static int lmc_close (struct net_device *dev) /*fold00*/ | |||
| 1223 | /* When the interface goes down, this is called */ | 1154 | /* When the interface goes down, this is called */ |
| 1224 | static int lmc_ifdown (struct net_device *dev) /*fold00*/ | 1155 | static int lmc_ifdown (struct net_device *dev) /*fold00*/ |
| 1225 | { | 1156 | { |
| 1226 | lmc_softc_t *sc = dev->priv; | 1157 | lmc_softc_t *sc = dev_to_sc(dev); |
| 1227 | u32 csr6; | 1158 | u32 csr6; |
| 1228 | int i; | 1159 | int i; |
| 1229 | 1160 | ||
| 1230 | lmc_trace(dev, "lmc_ifdown in"); | 1161 | lmc_trace(dev, "lmc_ifdown in"); |
| 1231 | 1162 | ||
| 1232 | /* Don't let anything else go on right now */ | 1163 | /* Don't let anything else go on right now */ |
| 1233 | // dev->start = 0; | 1164 | // dev->start = 0; |
| 1234 | netif_stop_queue(dev); | 1165 | netif_stop_queue(dev); |
| 1235 | sc->stats.tx_tbusy1++ ; | 1166 | sc->extra_stats.tx_tbusy1++; |
| 1236 | 1167 | ||
| 1237 | /* stop interrupts */ | 1168 | /* stop interrupts */ |
| 1238 | /* Clear the interrupt mask */ | 1169 | /* Clear the interrupt mask */ |
| @@ -1244,8 +1175,8 @@ static int lmc_ifdown (struct net_device *dev) /*fold00*/ | |||
| 1244 | csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */ | 1175 | csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */ |
| 1245 | LMC_CSR_WRITE (sc, csr_command, csr6); | 1176 | LMC_CSR_WRITE (sc, csr_command, csr6); |
| 1246 | 1177 | ||
| 1247 | sc->stats.rx_missed_errors += | 1178 | sc->lmc_device->stats.rx_missed_errors += |
| 1248 | LMC_CSR_READ (sc, csr_missed_frames) & 0xffff; | 1179 | LMC_CSR_READ(sc, csr_missed_frames) & 0xffff; |
| 1249 | 1180 | ||
| 1250 | /* release the interrupt */ | 1181 | /* release the interrupt */ |
| 1251 | if(sc->got_irq == 1){ | 1182 | if(sc->got_irq == 1){ |
| @@ -1276,7 +1207,7 @@ static int lmc_ifdown (struct net_device *dev) /*fold00*/ | |||
| 1276 | lmc_led_off (sc, LMC_MII16_LED_ALL); | 1207 | lmc_led_off (sc, LMC_MII16_LED_ALL); |
| 1277 | 1208 | ||
| 1278 | netif_wake_queue(dev); | 1209 | netif_wake_queue(dev); |
| 1279 | sc->stats.tx_tbusy0++ ; | 1210 | sc->extra_stats.tx_tbusy0++; |
| 1280 | 1211 | ||
| 1281 | lmc_trace(dev, "lmc_ifdown out"); | 1212 | lmc_trace(dev, "lmc_ifdown out"); |
| 1282 | 1213 | ||
| @@ -1289,7 +1220,7 @@ static int lmc_ifdown (struct net_device *dev) /*fold00*/ | |||
| 1289 | static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/ | 1220 | static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/ |
| 1290 | { | 1221 | { |
| 1291 | struct net_device *dev = (struct net_device *) dev_instance; | 1222 | struct net_device *dev = (struct net_device *) dev_instance; |
| 1292 | lmc_softc_t *sc; | 1223 | lmc_softc_t *sc = dev_to_sc(dev); |
| 1293 | u32 csr; | 1224 | u32 csr; |
| 1294 | int i; | 1225 | int i; |
| 1295 | s32 stat; | 1226 | s32 stat; |
| @@ -1300,8 +1231,6 @@ static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/ | |||
| 1300 | 1231 | ||
| 1301 | lmc_trace(dev, "lmc_interrupt in"); | 1232 | lmc_trace(dev, "lmc_interrupt in"); |
| 1302 | 1233 | ||
| 1303 | sc = dev->priv; | ||
| 1304 | |||
| 1305 | spin_lock(&sc->lmc_lock); | 1234 | spin_lock(&sc->lmc_lock); |
| 1306 | 1235 | ||
| 1307 | /* | 1236 | /* |
| @@ -1354,7 +1283,7 @@ static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/ | |||
| 1354 | 1283 | ||
| 1355 | int n_compl = 0 ; | 1284 | int n_compl = 0 ; |
| 1356 | /* reset the transmit timeout detection flag -baz */ | 1285 | /* reset the transmit timeout detection flag -baz */ |
| 1357 | sc->stats.tx_NoCompleteCnt = 0; | 1286 | sc->extra_stats.tx_NoCompleteCnt = 0; |
| 1358 | 1287 | ||
| 1359 | badtx = sc->lmc_taint_tx; | 1288 | badtx = sc->lmc_taint_tx; |
| 1360 | i = badtx % LMC_TXDESCS; | 1289 | i = badtx % LMC_TXDESCS; |
| @@ -1378,27 +1307,25 @@ static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/ | |||
| 1378 | if (sc->lmc_txq[i] == NULL) | 1307 | if (sc->lmc_txq[i] == NULL) |
| 1379 | continue; | 1308 | continue; |
| 1380 | 1309 | ||
| 1381 | /* | 1310 | /* |
| 1382 | * Check the total error summary to look for any errors | 1311 | * Check the total error summary to look for any errors |
| 1383 | */ | 1312 | */ |
| 1384 | if (stat & 0x8000) { | 1313 | if (stat & 0x8000) { |
| 1385 | sc->stats.tx_errors++; | 1314 | sc->lmc_device->stats.tx_errors++; |
| 1386 | if (stat & 0x4104) | 1315 | if (stat & 0x4104) |
| 1387 | sc->stats.tx_aborted_errors++; | 1316 | sc->lmc_device->stats.tx_aborted_errors++; |
| 1388 | if (stat & 0x0C00) | 1317 | if (stat & 0x0C00) |
| 1389 | sc->stats.tx_carrier_errors++; | 1318 | sc->lmc_device->stats.tx_carrier_errors++; |
| 1390 | if (stat & 0x0200) | 1319 | if (stat & 0x0200) |
| 1391 | sc->stats.tx_window_errors++; | 1320 | sc->lmc_device->stats.tx_window_errors++; |
| 1392 | if (stat & 0x0002) | 1321 | if (stat & 0x0002) |
| 1393 | sc->stats.tx_fifo_errors++; | 1322 | sc->lmc_device->stats.tx_fifo_errors++; |
| 1394 | } | 1323 | } else { |
| 1395 | else { | 1324 | sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff; |
| 1396 | 1325 | ||
| 1397 | sc->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff; | 1326 | sc->lmc_device->stats.tx_packets++; |
| 1398 | |||
| 1399 | sc->stats.tx_packets++; | ||
| 1400 | } | 1327 | } |
| 1401 | 1328 | ||
| 1402 | // dev_kfree_skb(sc->lmc_txq[i]); | 1329 | // dev_kfree_skb(sc->lmc_txq[i]); |
| 1403 | dev_kfree_skb_irq(sc->lmc_txq[i]); | 1330 | dev_kfree_skb_irq(sc->lmc_txq[i]); |
| 1404 | sc->lmc_txq[i] = NULL; | 1331 | sc->lmc_txq[i] = NULL; |
| @@ -1415,13 +1342,13 @@ static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/ | |||
| 1415 | LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0); | 1342 | LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0); |
| 1416 | sc->lmc_txfull = 0; | 1343 | sc->lmc_txfull = 0; |
| 1417 | netif_wake_queue(dev); | 1344 | netif_wake_queue(dev); |
| 1418 | sc->stats.tx_tbusy0++ ; | 1345 | sc->extra_stats.tx_tbusy0++; |
| 1419 | 1346 | ||
| 1420 | 1347 | ||
| 1421 | #ifdef DEBUG | 1348 | #ifdef DEBUG |
| 1422 | sc->stats.dirtyTx = badtx; | 1349 | sc->extra_stats.dirtyTx = badtx; |
| 1423 | sc->stats.lmc_next_tx = sc->lmc_next_tx; | 1350 | sc->extra_stats.lmc_next_tx = sc->lmc_next_tx; |
| 1424 | sc->stats.lmc_txfull = sc->lmc_txfull; | 1351 | sc->extra_stats.lmc_txfull = sc->lmc_txfull; |
| 1425 | #endif | 1352 | #endif |
| 1426 | sc->lmc_taint_tx = badtx; | 1353 | sc->lmc_taint_tx = badtx; |
| 1427 | 1354 | ||
| @@ -1476,9 +1403,9 @@ lmc_int_fail_out: | |||
| 1476 | return IRQ_RETVAL(handled); | 1403 | return IRQ_RETVAL(handled); |
| 1477 | } | 1404 | } |
| 1478 | 1405 | ||
| 1479 | static int lmc_start_xmit (struct sk_buff *skb, struct net_device *dev) /*fold00*/ | 1406 | static int lmc_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 1480 | { | 1407 | { |
| 1481 | lmc_softc_t *sc; | 1408 | lmc_softc_t *sc = dev_to_sc(dev); |
| 1482 | u32 flag; | 1409 | u32 flag; |
| 1483 | int entry; | 1410 | int entry; |
| 1484 | int ret = 0; | 1411 | int ret = 0; |
| @@ -1486,8 +1413,6 @@ static int lmc_start_xmit (struct sk_buff *skb, struct net_device *dev) /*fold00 | |||
| 1486 | 1413 | ||
| 1487 | lmc_trace(dev, "lmc_start_xmit in"); | 1414 | lmc_trace(dev, "lmc_start_xmit in"); |
| 1488 | 1415 | ||
| 1489 | sc = dev->priv; | ||
| 1490 | |||
| 1491 | spin_lock_irqsave(&sc->lmc_lock, flags); | 1416 | spin_lock_irqsave(&sc->lmc_lock, flags); |
| 1492 | 1417 | ||
| 1493 | /* normal path, tbusy known to be zero */ | 1418 | /* normal path, tbusy known to be zero */ |
| @@ -1532,8 +1457,8 @@ static int lmc_start_xmit (struct sk_buff *skb, struct net_device *dev) /*fold00 | |||
| 1532 | if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1) | 1457 | if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1) |
| 1533 | { /* ring full, go busy */ | 1458 | { /* ring full, go busy */ |
| 1534 | sc->lmc_txfull = 1; | 1459 | sc->lmc_txfull = 1; |
| 1535 | netif_stop_queue(dev); | 1460 | netif_stop_queue(dev); |
| 1536 | sc->stats.tx_tbusy1++ ; | 1461 | sc->extra_stats.tx_tbusy1++; |
| 1537 | LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0); | 1462 | LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0); |
| 1538 | } | 1463 | } |
| 1539 | #endif | 1464 | #endif |
| @@ -1550,7 +1475,7 @@ static int lmc_start_xmit (struct sk_buff *skb, struct net_device *dev) /*fold00 | |||
| 1550 | * the watchdog timer handler. -baz | 1475 | * the watchdog timer handler. -baz |
| 1551 | */ | 1476 | */ |
| 1552 | 1477 | ||
| 1553 | sc->stats.tx_NoCompleteCnt++; | 1478 | sc->extra_stats.tx_NoCompleteCnt++; |
| 1554 | sc->lmc_next_tx++; | 1479 | sc->lmc_next_tx++; |
| 1555 | 1480 | ||
| 1556 | /* give ownership to the chip */ | 1481 | /* give ownership to the chip */ |
| @@ -1569,9 +1494,9 @@ static int lmc_start_xmit (struct sk_buff *skb, struct net_device *dev) /*fold00 | |||
| 1569 | } | 1494 | } |
| 1570 | 1495 | ||
| 1571 | 1496 | ||
| 1572 | static int lmc_rx (struct net_device *dev) /*fold00*/ | 1497 | static int lmc_rx(struct net_device *dev) |
| 1573 | { | 1498 | { |
| 1574 | lmc_softc_t *sc; | 1499 | lmc_softc_t *sc = dev_to_sc(dev); |
| 1575 | int i; | 1500 | int i; |
| 1576 | int rx_work_limit = LMC_RXDESCS; | 1501 | int rx_work_limit = LMC_RXDESCS; |
| 1577 | unsigned int next_rx; | 1502 | unsigned int next_rx; |
| @@ -1583,8 +1508,6 @@ static int lmc_rx (struct net_device *dev) /*fold00*/ | |||
| 1583 | 1508 | ||
| 1584 | lmc_trace(dev, "lmc_rx in"); | 1509 | lmc_trace(dev, "lmc_rx in"); |
| 1585 | 1510 | ||
| 1586 | sc = dev->priv; | ||
| 1587 | |||
| 1588 | lmc_led_on(sc, LMC_DS3_LED3); | 1511 | lmc_led_on(sc, LMC_DS3_LED3); |
| 1589 | 1512 | ||
| 1590 | rxIntLoopCnt = 0; /* debug -baz */ | 1513 | rxIntLoopCnt = 0; /* debug -baz */ |
| @@ -1597,39 +1520,38 @@ static int lmc_rx (struct net_device *dev) /*fold00*/ | |||
| 1597 | rxIntLoopCnt++; /* debug -baz */ | 1520 | rxIntLoopCnt++; /* debug -baz */ |
| 1598 | len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER); | 1521 | len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER); |
| 1599 | if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */ | 1522 | if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */ |
| 1600 | if ((stat & 0x0000ffff) != 0x7fff) { | 1523 | if ((stat & 0x0000ffff) != 0x7fff) { |
| 1601 | /* Oversized frame */ | 1524 | /* Oversized frame */ |
| 1602 | sc->stats.rx_length_errors++; | 1525 | sc->lmc_device->stats.rx_length_errors++; |
| 1603 | goto skip_packet; | 1526 | goto skip_packet; |
| 1604 | } | 1527 | } |
| 1605 | } | 1528 | } |
| 1606 | |||
| 1607 | if(stat & 0x00000008){ /* Catch a dribbling bit error */ | ||
| 1608 | sc->stats.rx_errors++; | ||
| 1609 | sc->stats.rx_frame_errors++; | ||
| 1610 | goto skip_packet; | ||
| 1611 | } | ||
| 1612 | 1529 | ||
| 1530 | if (stat & 0x00000008) { /* Catch a dribbling bit error */ | ||
| 1531 | sc->lmc_device->stats.rx_errors++; | ||
| 1532 | sc->lmc_device->stats.rx_frame_errors++; | ||
| 1533 | goto skip_packet; | ||
| 1534 | } | ||
| 1613 | 1535 | ||
| 1614 | if(stat & 0x00000004){ /* Catch a CRC error by the Xilinx */ | ||
| 1615 | sc->stats.rx_errors++; | ||
| 1616 | sc->stats.rx_crc_errors++; | ||
| 1617 | goto skip_packet; | ||
| 1618 | } | ||
| 1619 | 1536 | ||
| 1537 | if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */ | ||
| 1538 | sc->lmc_device->stats.rx_errors++; | ||
| 1539 | sc->lmc_device->stats.rx_crc_errors++; | ||
| 1540 | goto skip_packet; | ||
| 1541 | } | ||
| 1620 | 1542 | ||
| 1621 | if (len > LMC_PKT_BUF_SZ){ | 1543 | if (len > LMC_PKT_BUF_SZ) { |
| 1622 | sc->stats.rx_length_errors++; | 1544 | sc->lmc_device->stats.rx_length_errors++; |
| 1623 | localLengthErrCnt++; | 1545 | localLengthErrCnt++; |
| 1624 | goto skip_packet; | 1546 | goto skip_packet; |
| 1625 | } | 1547 | } |
| 1626 | 1548 | ||
| 1627 | if (len < sc->lmc_crcSize + 2) { | 1549 | if (len < sc->lmc_crcSize + 2) { |
| 1628 | sc->stats.rx_length_errors++; | 1550 | sc->lmc_device->stats.rx_length_errors++; |
| 1629 | sc->stats.rx_SmallPktCnt++; | 1551 | sc->extra_stats.rx_SmallPktCnt++; |
| 1630 | localLengthErrCnt++; | 1552 | localLengthErrCnt++; |
| 1631 | goto skip_packet; | 1553 | goto skip_packet; |
| 1632 | } | 1554 | } |
| 1633 | 1555 | ||
| 1634 | if(stat & 0x00004000){ | 1556 | if(stat & 0x00004000){ |
| 1635 | printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name); | 1557 | printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name); |
| @@ -1656,8 +1578,8 @@ static int lmc_rx (struct net_device *dev) /*fold00*/ | |||
| 1656 | } | 1578 | } |
| 1657 | 1579 | ||
| 1658 | dev->last_rx = jiffies; | 1580 | dev->last_rx = jiffies; |
| 1659 | sc->stats.rx_packets++; | 1581 | sc->lmc_device->stats.rx_packets++; |
| 1660 | sc->stats.rx_bytes += len; | 1582 | sc->lmc_device->stats.rx_bytes += len; |
| 1661 | 1583 | ||
| 1662 | LMC_CONSOLE_LOG("recv", skb->data, len); | 1584 | LMC_CONSOLE_LOG("recv", skb->data, len); |
| 1663 | 1585 | ||
| @@ -1679,7 +1601,6 @@ static int lmc_rx (struct net_device *dev) /*fold00*/ | |||
| 1679 | 1601 | ||
| 1680 | skb_put (skb, len); | 1602 | skb_put (skb, len); |
| 1681 | skb->protocol = lmc_proto_type(sc, skb); | 1603 | skb->protocol = lmc_proto_type(sc, skb); |
| 1682 | skb->protocol = htons(ETH_P_WAN_PPP); | ||
| 1683 | skb_reset_mac_header(skb); | 1604 | skb_reset_mac_header(skb); |
| 1684 | /* skb_reset_network_header(skb); */ | 1605 | /* skb_reset_network_header(skb); */ |
| 1685 | skb->dev = dev; | 1606 | skb->dev = dev; |
| @@ -1704,7 +1625,7 @@ static int lmc_rx (struct net_device *dev) /*fold00*/ | |||
| 1704 | * in which care we'll try to allocate the buffer | 1625 | * in which care we'll try to allocate the buffer |
| 1705 | * again. (once a second) | 1626 | * again. (once a second) |
| 1706 | */ | 1627 | */ |
| 1707 | sc->stats.rx_BuffAllocErr++; | 1628 | sc->extra_stats.rx_BuffAllocErr++; |
| 1708 | LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len); | 1629 | LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len); |
| 1709 | sc->failed_recv_alloc = 1; | 1630 | sc->failed_recv_alloc = 1; |
| 1710 | goto skip_out_of_mem; | 1631 | goto skip_out_of_mem; |
| @@ -1739,16 +1660,14 @@ static int lmc_rx (struct net_device *dev) /*fold00*/ | |||
| 1739 | * descriptors with bogus packets | 1660 | * descriptors with bogus packets |
| 1740 | * | 1661 | * |
| 1741 | if (localLengthErrCnt > LMC_RXDESCS - 3) { | 1662 | if (localLengthErrCnt > LMC_RXDESCS - 3) { |
| 1742 | sc->stats.rx_BadPktSurgeCnt++; | 1663 | sc->extra_stats.rx_BadPktSurgeCnt++; |
| 1743 | LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, | 1664 | LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt, |
| 1744 | localLengthErrCnt, | 1665 | sc->extra_stats.rx_BadPktSurgeCnt); |
| 1745 | sc->stats.rx_BadPktSurgeCnt); | ||
| 1746 | } */ | 1666 | } */ |
| 1747 | 1667 | ||
| 1748 | /* save max count of receive descriptors serviced */ | 1668 | /* save max count of receive descriptors serviced */ |
| 1749 | if (rxIntLoopCnt > sc->stats.rxIntLoopCnt) { | 1669 | if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt) |
| 1750 | sc->stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */ | 1670 | sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */ |
| 1751 | } | ||
| 1752 | 1671 | ||
| 1753 | #ifdef DEBUG | 1672 | #ifdef DEBUG |
| 1754 | if (rxIntLoopCnt == 0) | 1673 | if (rxIntLoopCnt == 0) |
| @@ -1775,23 +1694,22 @@ skip_out_of_mem: | |||
| 1775 | return 0; | 1694 | return 0; |
| 1776 | } | 1695 | } |
| 1777 | 1696 | ||
| 1778 | static struct net_device_stats *lmc_get_stats (struct net_device *dev) /*fold00*/ | 1697 | static struct net_device_stats *lmc_get_stats(struct net_device *dev) |
| 1779 | { | 1698 | { |
| 1780 | lmc_softc_t *sc = dev->priv; | 1699 | lmc_softc_t *sc = dev_to_sc(dev); |
| 1781 | unsigned long flags; | 1700 | unsigned long flags; |
| 1782 | 1701 | ||
| 1783 | lmc_trace(dev, "lmc_get_stats in"); | 1702 | lmc_trace(dev, "lmc_get_stats in"); |
| 1784 | 1703 | ||
| 1785 | |||
| 1786 | spin_lock_irqsave(&sc->lmc_lock, flags); | 1704 | spin_lock_irqsave(&sc->lmc_lock, flags); |
| 1787 | 1705 | ||
| 1788 | sc->stats.rx_missed_errors += LMC_CSR_READ (sc, csr_missed_frames) & 0xffff; | 1706 | sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff; |
| 1789 | 1707 | ||
| 1790 | spin_unlock_irqrestore(&sc->lmc_lock, flags); | 1708 | spin_unlock_irqrestore(&sc->lmc_lock, flags); |
| 1791 | 1709 | ||
| 1792 | lmc_trace(dev, "lmc_get_stats out"); | 1710 | lmc_trace(dev, "lmc_get_stats out"); |
| 1793 | 1711 | ||
| 1794 | return (struct net_device_stats *) &sc->stats; | 1712 | return &sc->lmc_device->stats; |
| 1795 | } | 1713 | } |
| 1796 | 1714 | ||
| 1797 | static struct pci_driver lmc_driver = { | 1715 | static struct pci_driver lmc_driver = { |
| @@ -1970,7 +1888,7 @@ static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/ | |||
| 1970 | { | 1888 | { |
| 1971 | if (sc->lmc_txq[i] != NULL){ /* have buffer */ | 1889 | if (sc->lmc_txq[i] != NULL){ /* have buffer */ |
| 1972 | dev_kfree_skb(sc->lmc_txq[i]); /* free it */ | 1890 | dev_kfree_skb(sc->lmc_txq[i]); /* free it */ |
| 1973 | sc->stats.tx_dropped++; /* We just dropped a packet */ | 1891 | sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */ |
| 1974 | } | 1892 | } |
| 1975 | sc->lmc_txq[i] = NULL; | 1893 | sc->lmc_txq[i] = NULL; |
| 1976 | sc->lmc_txring[i].status = 0x00000000; | 1894 | sc->lmc_txring[i].status = 0x00000000; |
| @@ -1982,7 +1900,7 @@ static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/ | |||
| 1982 | lmc_trace(sc->lmc_device, "lmc_softreset out"); | 1900 | lmc_trace(sc->lmc_device, "lmc_softreset out"); |
| 1983 | } | 1901 | } |
| 1984 | 1902 | ||
| 1985 | void lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits) /*fold00*/ | 1903 | void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/ |
| 1986 | { | 1904 | { |
| 1987 | lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in"); | 1905 | lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in"); |
| 1988 | sc->lmc_gpio_io &= ~bits; | 1906 | sc->lmc_gpio_io &= ~bits; |
| @@ -1990,7 +1908,7 @@ void lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits) /*fold00*/ | |||
| 1990 | lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out"); | 1908 | lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out"); |
| 1991 | } | 1909 | } |
| 1992 | 1910 | ||
| 1993 | void lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits) /*fold00*/ | 1911 | void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/ |
| 1994 | { | 1912 | { |
| 1995 | lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in"); | 1913 | lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in"); |
| 1996 | sc->lmc_gpio_io |= bits; | 1914 | sc->lmc_gpio_io |= bits; |
| @@ -1998,7 +1916,7 @@ void lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits) /*fold00*/ | |||
| 1998 | lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out"); | 1916 | lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out"); |
| 1999 | } | 1917 | } |
| 2000 | 1918 | ||
| 2001 | void lmc_led_on(lmc_softc_t * const sc, u_int32_t led) /*fold00*/ | 1919 | void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/ |
| 2002 | { | 1920 | { |
| 2003 | lmc_trace(sc->lmc_device, "lmc_led_on in"); | 1921 | lmc_trace(sc->lmc_device, "lmc_led_on in"); |
| 2004 | if((~sc->lmc_miireg16) & led){ /* Already on! */ | 1922 | if((~sc->lmc_miireg16) & led){ /* Already on! */ |
| @@ -2011,7 +1929,7 @@ void lmc_led_on(lmc_softc_t * const sc, u_int32_t led) /*fold00*/ | |||
| 2011 | lmc_trace(sc->lmc_device, "lmc_led_on out"); | 1929 | lmc_trace(sc->lmc_device, "lmc_led_on out"); |
| 2012 | } | 1930 | } |
| 2013 | 1931 | ||
| 2014 | void lmc_led_off(lmc_softc_t * const sc, u_int32_t led) /*fold00*/ | 1932 | void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/ |
| 2015 | { | 1933 | { |
| 2016 | lmc_trace(sc->lmc_device, "lmc_led_off in"); | 1934 | lmc_trace(sc->lmc_device, "lmc_led_off in"); |
| 2017 | if(sc->lmc_miireg16 & led){ /* Already set don't do anything */ | 1935 | if(sc->lmc_miireg16 & led){ /* Already set don't do anything */ |
| @@ -2061,13 +1979,13 @@ static void lmc_reset(lmc_softc_t * const sc) /*fold00*/ | |||
| 2061 | */ | 1979 | */ |
| 2062 | sc->lmc_media->init(sc); | 1980 | sc->lmc_media->init(sc); |
| 2063 | 1981 | ||
| 2064 | sc->stats.resetCount++; | 1982 | sc->extra_stats.resetCount++; |
| 2065 | lmc_trace(sc->lmc_device, "lmc_reset out"); | 1983 | lmc_trace(sc->lmc_device, "lmc_reset out"); |
| 2066 | } | 1984 | } |
| 2067 | 1985 | ||
| 2068 | static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/ | 1986 | static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/ |
| 2069 | { | 1987 | { |
| 2070 | u_int32_t val; | 1988 | u32 val; |
| 2071 | lmc_trace(sc->lmc_device, "lmc_dec_reset in"); | 1989 | lmc_trace(sc->lmc_device, "lmc_dec_reset in"); |
| 2072 | 1990 | ||
| 2073 | /* | 1991 | /* |
| @@ -2151,23 +2069,21 @@ static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00 | |||
| 2151 | lmc_trace(sc->lmc_device, "lmc_initcsrs out"); | 2069 | lmc_trace(sc->lmc_device, "lmc_initcsrs out"); |
| 2152 | } | 2070 | } |
| 2153 | 2071 | ||
| 2154 | static void lmc_driver_timeout(struct net_device *dev) { /*fold00*/ | 2072 | static void lmc_driver_timeout(struct net_device *dev) |
| 2155 | lmc_softc_t *sc; | 2073 | { |
| 2074 | lmc_softc_t *sc = dev_to_sc(dev); | ||
| 2156 | u32 csr6; | 2075 | u32 csr6; |
| 2157 | unsigned long flags; | 2076 | unsigned long flags; |
| 2158 | 2077 | ||
| 2159 | lmc_trace(dev, "lmc_driver_timeout in"); | 2078 | lmc_trace(dev, "lmc_driver_timeout in"); |
| 2160 | 2079 | ||
| 2161 | sc = dev->priv; | ||
| 2162 | |||
| 2163 | spin_lock_irqsave(&sc->lmc_lock, flags); | 2080 | spin_lock_irqsave(&sc->lmc_lock, flags); |
| 2164 | 2081 | ||
| 2165 | printk("%s: Xmitter busy|\n", dev->name); | 2082 | printk("%s: Xmitter busy|\n", dev->name); |
| 2166 | 2083 | ||
| 2167 | sc->stats.tx_tbusy_calls++ ; | 2084 | sc->extra_stats.tx_tbusy_calls++; |
| 2168 | if (jiffies - dev->trans_start < TX_TIMEOUT) { | 2085 | if (jiffies - dev->trans_start < TX_TIMEOUT) |
| 2169 | goto bug_out; | 2086 | goto bug_out; |
| 2170 | } | ||
| 2171 | 2087 | ||
| 2172 | /* | 2088 | /* |
| 2173 | * Chip seems to have locked up | 2089 | * Chip seems to have locked up |
| @@ -2178,7 +2094,7 @@ static void lmc_driver_timeout(struct net_device *dev) { /*fold00*/ | |||
| 2178 | 2094 | ||
| 2179 | LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO, | 2095 | LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO, |
| 2180 | LMC_CSR_READ (sc, csr_status), | 2096 | LMC_CSR_READ (sc, csr_status), |
| 2181 | sc->stats.tx_ProcTimeout); | 2097 | sc->extra_stats.tx_ProcTimeout); |
| 2182 | 2098 | ||
| 2183 | lmc_running_reset (dev); | 2099 | lmc_running_reset (dev); |
| 2184 | 2100 | ||
| @@ -2195,8 +2111,8 @@ static void lmc_driver_timeout(struct net_device *dev) { /*fold00*/ | |||
| 2195 | /* immediate transmit */ | 2111 | /* immediate transmit */ |
| 2196 | LMC_CSR_WRITE (sc, csr_txpoll, 0); | 2112 | LMC_CSR_WRITE (sc, csr_txpoll, 0); |
| 2197 | 2113 | ||
| 2198 | sc->stats.tx_errors++; | 2114 | sc->lmc_device->stats.tx_errors++; |
| 2199 | sc->stats.tx_ProcTimeout++; /* -baz */ | 2115 | sc->extra_stats.tx_ProcTimeout++; /* -baz */ |
| 2200 | 2116 | ||
| 2201 | dev->trans_start = jiffies; | 2117 | dev->trans_start = jiffies; |
| 2202 | 2118 | ||
diff --git a/drivers/net/wan/lmc/lmc_media.c b/drivers/net/wan/lmc/lmc_media.c index 8aa461c941ce..f327674fc93a 100644 --- a/drivers/net/wan/lmc/lmc_media.c +++ b/drivers/net/wan/lmc/lmc_media.c | |||
| @@ -16,8 +16,6 @@ | |||
| 16 | #include <linux/inet.h> | 16 | #include <linux/inet.h> |
| 17 | #include <linux/bitops.h> | 17 | #include <linux/bitops.h> |
| 18 | 18 | ||
| 19 | #include <net/syncppp.h> | ||
| 20 | |||
| 21 | #include <asm/processor.h> /* Processor type for cache alignment. */ | 19 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
| 22 | #include <asm/io.h> | 20 | #include <asm/io.h> |
| 23 | #include <asm/dma.h> | 21 | #include <asm/dma.h> |
| @@ -95,8 +93,7 @@ static void lmc_dummy_set_1 (lmc_softc_t * const, int); | |||
| 95 | static void lmc_dummy_set2_1 (lmc_softc_t * const, lmc_ctl_t *); | 93 | static void lmc_dummy_set2_1 (lmc_softc_t * const, lmc_ctl_t *); |
| 96 | 94 | ||
| 97 | static inline void write_av9110_bit (lmc_softc_t *, int); | 95 | static inline void write_av9110_bit (lmc_softc_t *, int); |
| 98 | static void write_av9110 (lmc_softc_t *, u_int32_t, u_int32_t, u_int32_t, | 96 | static void write_av9110(lmc_softc_t *, u32, u32, u32, u32, u32); |
| 99 | u_int32_t, u_int32_t); | ||
| 100 | 97 | ||
| 101 | lmc_media_t lmc_ds3_media = { | 98 | lmc_media_t lmc_ds3_media = { |
| 102 | lmc_ds3_init, /* special media init stuff */ | 99 | lmc_ds3_init, /* special media init stuff */ |
| @@ -427,7 +424,7 @@ lmc_ds3_set_scram (lmc_softc_t * const sc, int ie) | |||
| 427 | static int | 424 | static int |
| 428 | lmc_ds3_get_link_status (lmc_softc_t * const sc) | 425 | lmc_ds3_get_link_status (lmc_softc_t * const sc) |
| 429 | { | 426 | { |
| 430 | u_int16_t link_status, link_status_11; | 427 | u16 link_status, link_status_11; |
| 431 | int ret = 1; | 428 | int ret = 1; |
| 432 | 429 | ||
| 433 | lmc_mii_writereg (sc, 0, 17, 7); | 430 | lmc_mii_writereg (sc, 0, 17, 7); |
| @@ -449,7 +446,7 @@ lmc_ds3_get_link_status (lmc_softc_t * const sc) | |||
| 449 | (link_status & LMC_FRAMER_REG0_OOFS)){ | 446 | (link_status & LMC_FRAMER_REG0_OOFS)){ |
| 450 | ret = 0; | 447 | ret = 0; |
| 451 | if(sc->last_led_err[3] != 1){ | 448 | if(sc->last_led_err[3] != 1){ |
| 452 | u16 r1; | 449 | u16 r1; |
| 453 | lmc_mii_writereg (sc, 0, 17, 01); /* Turn on Xbit error as our cisco does */ | 450 | lmc_mii_writereg (sc, 0, 17, 01); /* Turn on Xbit error as our cisco does */ |
| 454 | r1 = lmc_mii_readreg (sc, 0, 18); | 451 | r1 = lmc_mii_readreg (sc, 0, 18); |
| 455 | r1 &= 0xfe; | 452 | r1 &= 0xfe; |
| @@ -462,7 +459,7 @@ lmc_ds3_get_link_status (lmc_softc_t * const sc) | |||
| 462 | else { | 459 | else { |
| 463 | lmc_led_off(sc, LMC_DS3_LED3); /* turn on red LED */ | 460 | lmc_led_off(sc, LMC_DS3_LED3); /* turn on red LED */ |
| 464 | if(sc->last_led_err[3] == 1){ | 461 | if(sc->last_led_err[3] == 1){ |
| 465 | u16 r1; | 462 | u16 r1; |
| 466 | lmc_mii_writereg (sc, 0, 17, 01); /* Turn off Xbit error */ | 463 | lmc_mii_writereg (sc, 0, 17, 01); /* Turn off Xbit error */ |
| 467 | r1 = lmc_mii_readreg (sc, 0, 18); | 464 | r1 = lmc_mii_readreg (sc, 0, 18); |
| 468 | r1 |= 0x01; | 465 | r1 |= 0x01; |
| @@ -540,20 +537,19 @@ lmc_ds3_watchdog (lmc_softc_t * const sc) | |||
| 540 | * SSI methods | 537 | * SSI methods |
| 541 | */ | 538 | */ |
| 542 | 539 | ||
| 543 | static void | 540 | static void lmc_ssi_init(lmc_softc_t * const sc) |
| 544 | lmc_ssi_init (lmc_softc_t * const sc) | ||
| 545 | { | 541 | { |
| 546 | u_int16_t mii17; | 542 | u16 mii17; |
| 547 | int cable; | 543 | int cable; |
| 548 | 544 | ||
| 549 | sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1000; | 545 | sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1000; |
| 550 | 546 | ||
| 551 | mii17 = lmc_mii_readreg (sc, 0, 17); | 547 | mii17 = lmc_mii_readreg(sc, 0, 17); |
| 552 | 548 | ||
| 553 | cable = (mii17 & LMC_MII17_SSI_CABLE_MASK) >> LMC_MII17_SSI_CABLE_SHIFT; | 549 | cable = (mii17 & LMC_MII17_SSI_CABLE_MASK) >> LMC_MII17_SSI_CABLE_SHIFT; |
| 554 | sc->ictl.cable_type = cable; | 550 | sc->ictl.cable_type = cable; |
| 555 | 551 | ||
| 556 | lmc_gpio_mkoutput (sc, LMC_GEP_SSI_TXCLOCK); | 552 | lmc_gpio_mkoutput(sc, LMC_GEP_SSI_TXCLOCK); |
| 557 | } | 553 | } |
| 558 | 554 | ||
| 559 | static void | 555 | static void |
| @@ -681,11 +677,11 @@ lmc_ssi_set_speed (lmc_softc_t * const sc, lmc_ctl_t * ctl) | |||
| 681 | static int | 677 | static int |
| 682 | lmc_ssi_get_link_status (lmc_softc_t * const sc) | 678 | lmc_ssi_get_link_status (lmc_softc_t * const sc) |
| 683 | { | 679 | { |
| 684 | u_int16_t link_status; | 680 | u16 link_status; |
| 685 | u_int32_t ticks; | 681 | u32 ticks; |
| 686 | int ret = 1; | 682 | int ret = 1; |
| 687 | int hw_hdsk = 1; | 683 | int hw_hdsk = 1; |
| 688 | 684 | ||
| 689 | /* | 685 | /* |
| 690 | * missing CTS? Hmm. If we require CTS on, we may never get the | 686 | * missing CTS? Hmm. If we require CTS on, we may never get the |
| 691 | * link to come up, so omit it in this test. | 687 | * link to come up, so omit it in this test. |
| @@ -720,9 +716,9 @@ lmc_ssi_get_link_status (lmc_softc_t * const sc) | |||
| 720 | } | 716 | } |
| 721 | else if (ticks == 0 ) { /* no clock found ? */ | 717 | else if (ticks == 0 ) { /* no clock found ? */ |
| 722 | ret = 0; | 718 | ret = 0; |
| 723 | if(sc->last_led_err[3] != 1){ | 719 | if (sc->last_led_err[3] != 1) { |
| 724 | sc->stats.tx_lossOfClockCnt++; | 720 | sc->extra_stats.tx_lossOfClockCnt++; |
| 725 | printk(KERN_WARNING "%s: Lost Clock, Link Down\n", sc->name); | 721 | printk(KERN_WARNING "%s: Lost Clock, Link Down\n", sc->name); |
| 726 | } | 722 | } |
| 727 | sc->last_led_err[3] = 1; | 723 | sc->last_led_err[3] = 1; |
| 728 | lmc_led_on (sc, LMC_MII16_LED3); /* turn ON red LED */ | 724 | lmc_led_on (sc, LMC_MII16_LED3); /* turn ON red LED */ |
| @@ -838,9 +834,7 @@ write_av9110_bit (lmc_softc_t * sc, int c) | |||
| 838 | LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio); | 834 | LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio); |
| 839 | } | 835 | } |
| 840 | 836 | ||
| 841 | static void | 837 | static void write_av9110(lmc_softc_t *sc, u32 n, u32 m, u32 v, u32 x, u32 r) |
| 842 | write_av9110 (lmc_softc_t * sc, u_int32_t n, u_int32_t m, u_int32_t v, | ||
| 843 | u_int32_t x, u_int32_t r) | ||
| 844 | { | 838 | { |
| 845 | int i; | 839 | int i; |
| 846 | 840 | ||
| @@ -887,19 +881,13 @@ write_av9110 (lmc_softc_t * sc, u_int32_t n, u_int32_t m, u_int32_t v, | |||
| 887 | | LMC_GEP_SSI_GENERATOR)); | 881 | | LMC_GEP_SSI_GENERATOR)); |
| 888 | } | 882 | } |
| 889 | 883 | ||
| 890 | static void | 884 | static void lmc_ssi_watchdog(lmc_softc_t * const sc) |
| 891 | lmc_ssi_watchdog (lmc_softc_t * const sc) | ||
| 892 | { | 885 | { |
| 893 | u_int16_t mii17 = lmc_mii_readreg (sc, 0, 17); | 886 | u16 mii17 = lmc_mii_readreg(sc, 0, 17); |
| 894 | if (((mii17 >> 3) & 7) == 7) | 887 | if (((mii17 >> 3) & 7) == 7) |
| 895 | { | 888 | lmc_led_off(sc, LMC_MII16_LED2); |
| 896 | lmc_led_off (sc, LMC_MII16_LED2); | 889 | else |
| 897 | } | 890 | lmc_led_on(sc, LMC_MII16_LED2); |
| 898 | else | ||
| 899 | { | ||
| 900 | lmc_led_on (sc, LMC_MII16_LED2); | ||
| 901 | } | ||
| 902 | |||
| 903 | } | 891 | } |
| 904 | 892 | ||
| 905 | /* | 893 | /* |
| @@ -929,7 +917,7 @@ lmc_t1_read (lmc_softc_t * const sc, int a) | |||
| 929 | static void | 917 | static void |
| 930 | lmc_t1_init (lmc_softc_t * const sc) | 918 | lmc_t1_init (lmc_softc_t * const sc) |
| 931 | { | 919 | { |
| 932 | u_int16_t mii16; | 920 | u16 mii16; |
| 933 | int i; | 921 | int i; |
| 934 | 922 | ||
| 935 | sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1200; | 923 | sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1200; |
| @@ -1028,7 +1016,7 @@ lmc_t1_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl) | |||
| 1028 | */ static int | 1016 | */ static int |
| 1029 | lmc_t1_get_link_status (lmc_softc_t * const sc) | 1017 | lmc_t1_get_link_status (lmc_softc_t * const sc) |
| 1030 | { | 1018 | { |
| 1031 | u_int16_t link_status; | 1019 | u16 link_status; |
| 1032 | int ret = 1; | 1020 | int ret = 1; |
| 1033 | 1021 | ||
| 1034 | /* LMC5245 (DS3) & LMC1200 (DS1) LED definitions | 1022 | /* LMC5245 (DS3) & LMC1200 (DS1) LED definitions |
diff --git a/drivers/net/wan/lmc/lmc_proto.c b/drivers/net/wan/lmc/lmc_proto.c index 85315758198d..be9877ff551e 100644 --- a/drivers/net/wan/lmc/lmc_proto.c +++ b/drivers/net/wan/lmc/lmc_proto.c | |||
| @@ -36,9 +36,6 @@ | |||
| 36 | #include <linux/workqueue.h> | 36 | #include <linux/workqueue.h> |
| 37 | #include <linux/proc_fs.h> | 37 | #include <linux/proc_fs.h> |
| 38 | #include <linux/bitops.h> | 38 | #include <linux/bitops.h> |
| 39 | |||
| 40 | #include <net/syncppp.h> | ||
| 41 | |||
| 42 | #include <asm/processor.h> /* Processor type for cache alignment. */ | 39 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
| 43 | #include <asm/io.h> | 40 | #include <asm/io.h> |
| 44 | #include <asm/dma.h> | 41 | #include <asm/dma.h> |
| @@ -50,48 +47,6 @@ | |||
| 50 | #include "lmc_ioctl.h" | 47 | #include "lmc_ioctl.h" |
| 51 | #include "lmc_proto.h" | 48 | #include "lmc_proto.h" |
| 52 | 49 | ||
| 53 | /* | ||
| 54 | * The compile-time variable SPPPSTUP causes the module to be | ||
| 55 | * compiled without referencing any of the sync ppp routines. | ||
| 56 | */ | ||
| 57 | #ifdef SPPPSTUB | ||
| 58 | #define SPPP_detach(d) (void)0 | ||
| 59 | #define SPPP_open(d) 0 | ||
| 60 | #define SPPP_reopen(d) (void)0 | ||
| 61 | #define SPPP_close(d) (void)0 | ||
| 62 | #define SPPP_attach(d) (void)0 | ||
| 63 | #define SPPP_do_ioctl(d,i,c) -EOPNOTSUPP | ||
| 64 | #else | ||
| 65 | #define SPPP_attach(x) sppp_attach((x)->pd) | ||
| 66 | #define SPPP_detach(x) sppp_detach((x)->pd->dev) | ||
| 67 | #define SPPP_open(x) sppp_open((x)->pd->dev) | ||
| 68 | #define SPPP_reopen(x) sppp_reopen((x)->pd->dev) | ||
| 69 | #define SPPP_close(x) sppp_close((x)->pd->dev) | ||
| 70 | #define SPPP_do_ioctl(x, y, z) sppp_do_ioctl((x)->pd->dev, (y), (z)) | ||
| 71 | #endif | ||
| 72 | |||
| 73 | // init | ||
| 74 | void lmc_proto_init(lmc_softc_t *sc) /*FOLD00*/ | ||
| 75 | { | ||
| 76 | lmc_trace(sc->lmc_device, "lmc_proto_init in"); | ||
| 77 | switch(sc->if_type){ | ||
| 78 | case LMC_PPP: | ||
| 79 | sc->pd = kmalloc(sizeof(struct ppp_device), GFP_KERNEL); | ||
| 80 | if (!sc->pd) { | ||
| 81 | printk("lmc_proto_init(): kmalloc failure!\n"); | ||
| 82 | return; | ||
| 83 | } | ||
| 84 | sc->pd->dev = sc->lmc_device; | ||
| 85 | sc->if_ptr = sc->pd; | ||
| 86 | break; | ||
| 87 | case LMC_RAW: | ||
| 88 | break; | ||
| 89 | default: | ||
| 90 | break; | ||
| 91 | } | ||
| 92 | lmc_trace(sc->lmc_device, "lmc_proto_init out"); | ||
| 93 | } | ||
| 94 | |||
| 95 | // attach | 50 | // attach |
| 96 | void lmc_proto_attach(lmc_softc_t *sc) /*FOLD00*/ | 51 | void lmc_proto_attach(lmc_softc_t *sc) /*FOLD00*/ |
| 97 | { | 52 | { |
| @@ -100,7 +55,6 @@ void lmc_proto_attach(lmc_softc_t *sc) /*FOLD00*/ | |||
| 100 | case LMC_PPP: | 55 | case LMC_PPP: |
| 101 | { | 56 | { |
| 102 | struct net_device *dev = sc->lmc_device; | 57 | struct net_device *dev = sc->lmc_device; |
| 103 | SPPP_attach(sc); | ||
| 104 | dev->do_ioctl = lmc_ioctl; | 58 | dev->do_ioctl = lmc_ioctl; |
| 105 | } | 59 | } |
| 106 | break; | 60 | break; |
| @@ -108,7 +62,7 @@ void lmc_proto_attach(lmc_softc_t *sc) /*FOLD00*/ | |||
| 108 | { | 62 | { |
| 109 | struct net_device *dev = sc->lmc_device; | 63 | struct net_device *dev = sc->lmc_device; |
| 110 | /* | 64 | /* |
| 111 | * They set a few basics because they don't use sync_ppp | 65 | * They set a few basics because they don't use HDLC |
| 112 | */ | 66 | */ |
| 113 | dev->flags |= IFF_POINTOPOINT; | 67 | dev->flags |= IFF_POINTOPOINT; |
| 114 | 68 | ||
| @@ -124,88 +78,39 @@ void lmc_proto_attach(lmc_softc_t *sc) /*FOLD00*/ | |||
| 124 | lmc_trace(sc->lmc_device, "lmc_proto_attach out"); | 78 | lmc_trace(sc->lmc_device, "lmc_proto_attach out"); |
| 125 | } | 79 | } |
| 126 | 80 | ||
| 127 | // detach | 81 | int lmc_proto_ioctl(lmc_softc_t *sc, struct ifreq *ifr, int cmd) |
| 128 | void lmc_proto_detach(lmc_softc_t *sc) /*FOLD00*/ | ||
| 129 | { | 82 | { |
| 130 | switch(sc->if_type){ | 83 | lmc_trace(sc->lmc_device, "lmc_proto_ioctl"); |
| 131 | case LMC_PPP: | 84 | if (sc->if_type == LMC_PPP) |
| 132 | SPPP_detach(sc); | 85 | return hdlc_ioctl(sc->lmc_device, ifr, cmd); |
| 133 | break; | 86 | return -EOPNOTSUPP; |
| 134 | case LMC_RAW: /* Tell someone we're detaching? */ | ||
| 135 | break; | ||
| 136 | default: | ||
| 137 | break; | ||
| 138 | } | ||
| 139 | |||
| 140 | } | 87 | } |
| 141 | 88 | ||
| 142 | // reopen | 89 | int lmc_proto_open(lmc_softc_t *sc) |
| 143 | void lmc_proto_reopen(lmc_softc_t *sc) /*FOLD00*/ | ||
| 144 | { | 90 | { |
| 145 | lmc_trace(sc->lmc_device, "lmc_proto_reopen in"); | 91 | int ret = 0; |
| 146 | switch(sc->if_type){ | ||
| 147 | case LMC_PPP: | ||
| 148 | SPPP_reopen(sc); | ||
| 149 | break; | ||
| 150 | case LMC_RAW: /* Reset the interface after being down, prerape to receive packets again */ | ||
| 151 | break; | ||
| 152 | default: | ||
| 153 | break; | ||
| 154 | } | ||
| 155 | lmc_trace(sc->lmc_device, "lmc_proto_reopen out"); | ||
| 156 | } | ||
| 157 | 92 | ||
| 93 | lmc_trace(sc->lmc_device, "lmc_proto_open in"); | ||
| 158 | 94 | ||
| 159 | // ioctl | 95 | if (sc->if_type == LMC_PPP) { |
| 160 | int lmc_proto_ioctl(lmc_softc_t *sc, struct ifreq *ifr, int cmd) /*FOLD00*/ | 96 | ret = hdlc_open(sc->lmc_device); |
| 161 | { | 97 | if (ret < 0) |
| 162 | lmc_trace(sc->lmc_device, "lmc_proto_ioctl out"); | 98 | printk(KERN_WARNING "%s: HDLC open failed: %d\n", |
| 163 | switch(sc->if_type){ | 99 | sc->name, ret); |
| 164 | case LMC_PPP: | 100 | } |
| 165 | return SPPP_do_ioctl (sc, ifr, cmd); | 101 | |
| 166 | break; | 102 | lmc_trace(sc->lmc_device, "lmc_proto_open out"); |
| 167 | default: | 103 | return ret; |
| 168 | return -EOPNOTSUPP; | ||
| 169 | break; | ||
| 170 | } | ||
| 171 | lmc_trace(sc->lmc_device, "lmc_proto_ioctl out"); | ||
| 172 | } | 104 | } |
| 173 | 105 | ||
| 174 | // open | 106 | void lmc_proto_close(lmc_softc_t *sc) |
| 175 | void lmc_proto_open(lmc_softc_t *sc) /*FOLD00*/ | ||
| 176 | { | 107 | { |
| 177 | int ret; | 108 | lmc_trace(sc->lmc_device, "lmc_proto_close in"); |
| 178 | 109 | ||
| 179 | lmc_trace(sc->lmc_device, "lmc_proto_open in"); | 110 | if (sc->if_type == LMC_PPP) |
| 180 | switch(sc->if_type){ | 111 | hdlc_close(sc->lmc_device); |
| 181 | case LMC_PPP: | ||
| 182 | ret = SPPP_open(sc); | ||
| 183 | if(ret < 0) | ||
| 184 | printk("%s: syncPPP open failed: %d\n", sc->name, ret); | ||
| 185 | break; | ||
| 186 | case LMC_RAW: /* We're about to start getting packets! */ | ||
| 187 | break; | ||
| 188 | default: | ||
| 189 | break; | ||
| 190 | } | ||
| 191 | lmc_trace(sc->lmc_device, "lmc_proto_open out"); | ||
| 192 | } | ||
| 193 | |||
| 194 | // close | ||
| 195 | 112 | ||
| 196 | void lmc_proto_close(lmc_softc_t *sc) /*FOLD00*/ | 113 | lmc_trace(sc->lmc_device, "lmc_proto_close out"); |
| 197 | { | ||
| 198 | lmc_trace(sc->lmc_device, "lmc_proto_close in"); | ||
| 199 | switch(sc->if_type){ | ||
| 200 | case LMC_PPP: | ||
| 201 | SPPP_close(sc); | ||
| 202 | break; | ||
| 203 | case LMC_RAW: /* Interface going down */ | ||
| 204 | break; | ||
| 205 | default: | ||
| 206 | break; | ||
| 207 | } | ||
| 208 | lmc_trace(sc->lmc_device, "lmc_proto_close out"); | ||
| 209 | } | 114 | } |
| 210 | 115 | ||
| 211 | __be16 lmc_proto_type(lmc_softc_t *sc, struct sk_buff *skb) /*FOLD00*/ | 116 | __be16 lmc_proto_type(lmc_softc_t *sc, struct sk_buff *skb) /*FOLD00*/ |
| @@ -213,8 +118,8 @@ __be16 lmc_proto_type(lmc_softc_t *sc, struct sk_buff *skb) /*FOLD00*/ | |||
| 213 | lmc_trace(sc->lmc_device, "lmc_proto_type in"); | 118 | lmc_trace(sc->lmc_device, "lmc_proto_type in"); |
| 214 | switch(sc->if_type){ | 119 | switch(sc->if_type){ |
| 215 | case LMC_PPP: | 120 | case LMC_PPP: |
| 216 | return htons(ETH_P_WAN_PPP); | 121 | return hdlc_type_trans(skb, sc->lmc_device); |
| 217 | break; | 122 | break; |
| 218 | case LMC_NET: | 123 | case LMC_NET: |
| 219 | return htons(ETH_P_802_2); | 124 | return htons(ETH_P_802_2); |
| 220 | break; | 125 | break; |
| @@ -245,4 +150,3 @@ void lmc_proto_netif(lmc_softc_t *sc, struct sk_buff *skb) /*FOLD00*/ | |||
| 245 | } | 150 | } |
| 246 | lmc_trace(sc->lmc_device, "lmc_proto_netif out"); | 151 | lmc_trace(sc->lmc_device, "lmc_proto_netif out"); |
| 247 | } | 152 | } |
| 248 | |||
diff --git a/drivers/net/wan/lmc/lmc_proto.h b/drivers/net/wan/lmc/lmc_proto.h index ccaa69e8b3c7..662148c54644 100644 --- a/drivers/net/wan/lmc/lmc_proto.h +++ b/drivers/net/wan/lmc/lmc_proto.h | |||
| @@ -1,16 +1,18 @@ | |||
| 1 | #ifndef _LMC_PROTO_H_ | 1 | #ifndef _LMC_PROTO_H_ |
| 2 | #define _LMC_PROTO_H_ | 2 | #define _LMC_PROTO_H_ |
| 3 | 3 | ||
| 4 | void lmc_proto_init(lmc_softc_t *sc); | 4 | #include <linux/hdlc.h> |
| 5 | |||
| 5 | void lmc_proto_attach(lmc_softc_t *sc); | 6 | void lmc_proto_attach(lmc_softc_t *sc); |
| 6 | void lmc_proto_detach(lmc_softc_t *sc); | ||
| 7 | void lmc_proto_reopen(lmc_softc_t *sc); | ||
| 8 | int lmc_proto_ioctl(lmc_softc_t *sc, struct ifreq *ifr, int cmd); | 7 | int lmc_proto_ioctl(lmc_softc_t *sc, struct ifreq *ifr, int cmd); |
| 9 | void lmc_proto_open(lmc_softc_t *sc); | 8 | int lmc_proto_open(lmc_softc_t *sc); |
| 10 | void lmc_proto_close(lmc_softc_t *sc); | 9 | void lmc_proto_close(lmc_softc_t *sc); |
| 11 | __be16 lmc_proto_type(lmc_softc_t *sc, struct sk_buff *skb); | 10 | __be16 lmc_proto_type(lmc_softc_t *sc, struct sk_buff *skb); |
| 12 | void lmc_proto_netif(lmc_softc_t *sc, struct sk_buff *skb); | 11 | void lmc_proto_netif(lmc_softc_t *sc, struct sk_buff *skb); |
| 13 | int lmc_skb_rawpackets(char *buf, char **start, off_t offset, int len, int unused); | ||
| 14 | 12 | ||
| 15 | #endif | 13 | static inline lmc_softc_t* dev_to_sc(struct net_device *dev) |
| 14 | { | ||
| 15 | return (lmc_softc_t *)dev_to_hdlc(dev)->priv; | ||
| 16 | } | ||
| 16 | 17 | ||
| 18 | #endif | ||
diff --git a/drivers/net/wan/lmc/lmc_var.h b/drivers/net/wan/lmc/lmc_var.h index 6d003a39bfad..65d01978e784 100644 --- a/drivers/net/wan/lmc/lmc_var.h +++ b/drivers/net/wan/lmc/lmc_var.h | |||
| @@ -1,8 +1,6 @@ | |||
| 1 | #ifndef _LMC_VAR_H_ | 1 | #ifndef _LMC_VAR_H_ |
| 2 | #define _LMC_VAR_H_ | 2 | #define _LMC_VAR_H_ |
| 3 | 3 | ||
| 4 | /* $Id: lmc_var.h,v 1.17 2000/04/06 12:16:47 asj Exp $ */ | ||
| 5 | |||
| 6 | /* | 4 | /* |
| 7 | * Copyright (c) 1997-2000 LAN Media Corporation (LMC) | 5 | * Copyright (c) 1997-2000 LAN Media Corporation (LMC) |
| 8 | * All rights reserved. www.lanmedia.com | 6 | * All rights reserved. www.lanmedia.com |
| @@ -19,23 +17,6 @@ | |||
| 19 | 17 | ||
| 20 | #include <linux/timer.h> | 18 | #include <linux/timer.h> |
| 21 | 19 | ||
| 22 | #ifndef __KERNEL__ | ||
| 23 | typedef signed char s8; | ||
| 24 | typedef unsigned char u8; | ||
| 25 | |||
| 26 | typedef signed short s16; | ||
| 27 | typedef unsigned short u16; | ||
| 28 | |||
| 29 | typedef signed int s32; | ||
| 30 | typedef unsigned int u32; | ||
| 31 | |||
| 32 | typedef signed long long s64; | ||
| 33 | typedef unsigned long long u64; | ||
| 34 | |||
| 35 | #define BITS_PER_LONG 32 | ||
| 36 | |||
| 37 | #endif | ||
| 38 | |||
| 39 | /* | 20 | /* |
| 40 | * basic definitions used in lmc include files | 21 | * basic definitions used in lmc include files |
| 41 | */ | 22 | */ |
| @@ -45,9 +26,6 @@ typedef struct lmc___media lmc_media_t; | |||
| 45 | typedef struct lmc___ctl lmc_ctl_t; | 26 | typedef struct lmc___ctl lmc_ctl_t; |
| 46 | 27 | ||
| 47 | #define lmc_csrptr_t unsigned long | 28 | #define lmc_csrptr_t unsigned long |
| 48 | #define u_int16_t u16 | ||
| 49 | #define u_int8_t u8 | ||
| 50 | #define tulip_uint32_t u32 | ||
| 51 | 29 | ||
| 52 | #define LMC_REG_RANGE 0x80 | 30 | #define LMC_REG_RANGE 0x80 |
| 53 | 31 | ||
| @@ -122,45 +100,45 @@ struct lmc_regfile_t { | |||
| 122 | * used to define bits in the second tulip_desc_t field (length) | 100 | * used to define bits in the second tulip_desc_t field (length) |
| 123 | * for the transmit descriptor -baz */ | 101 | * for the transmit descriptor -baz */ |
| 124 | 102 | ||
| 125 | #define LMC_TDES_FIRST_BUFFER_SIZE ((u_int32_t)(0x000007FF)) | 103 | #define LMC_TDES_FIRST_BUFFER_SIZE ((u32)(0x000007FF)) |
| 126 | #define LMC_TDES_SECOND_BUFFER_SIZE ((u_int32_t)(0x003FF800)) | 104 | #define LMC_TDES_SECOND_BUFFER_SIZE ((u32)(0x003FF800)) |
| 127 | #define LMC_TDES_HASH_FILTERING ((u_int32_t)(0x00400000)) | 105 | #define LMC_TDES_HASH_FILTERING ((u32)(0x00400000)) |
| 128 | #define LMC_TDES_DISABLE_PADDING ((u_int32_t)(0x00800000)) | 106 | #define LMC_TDES_DISABLE_PADDING ((u32)(0x00800000)) |
| 129 | #define LMC_TDES_SECOND_ADDR_CHAINED ((u_int32_t)(0x01000000)) | 107 | #define LMC_TDES_SECOND_ADDR_CHAINED ((u32)(0x01000000)) |
| 130 | #define LMC_TDES_END_OF_RING ((u_int32_t)(0x02000000)) | 108 | #define LMC_TDES_END_OF_RING ((u32)(0x02000000)) |
| 131 | #define LMC_TDES_ADD_CRC_DISABLE ((u_int32_t)(0x04000000)) | 109 | #define LMC_TDES_ADD_CRC_DISABLE ((u32)(0x04000000)) |
| 132 | #define LMC_TDES_SETUP_PACKET ((u_int32_t)(0x08000000)) | 110 | #define LMC_TDES_SETUP_PACKET ((u32)(0x08000000)) |
| 133 | #define LMC_TDES_INVERSE_FILTERING ((u_int32_t)(0x10000000)) | 111 | #define LMC_TDES_INVERSE_FILTERING ((u32)(0x10000000)) |
| 134 | #define LMC_TDES_FIRST_SEGMENT ((u_int32_t)(0x20000000)) | 112 | #define LMC_TDES_FIRST_SEGMENT ((u32)(0x20000000)) |
| 135 | #define LMC_TDES_LAST_SEGMENT ((u_int32_t)(0x40000000)) | 113 | #define LMC_TDES_LAST_SEGMENT ((u32)(0x40000000)) |
| 136 | #define LMC_TDES_INTERRUPT_ON_COMPLETION ((u_int32_t)(0x80000000)) | 114 | #define LMC_TDES_INTERRUPT_ON_COMPLETION ((u32)(0x80000000)) |
| 137 | 115 | ||
| 138 | #define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER 11 | 116 | #define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER 11 |
| 139 | #define TDES_COLLISION_COUNT_BIT_NUMBER 3 | 117 | #define TDES_COLLISION_COUNT_BIT_NUMBER 3 |
| 140 | 118 | ||
| 141 | /* Constants for the RCV descriptor RDES */ | 119 | /* Constants for the RCV descriptor RDES */ |
| 142 | 120 | ||
| 143 | #define LMC_RDES_OVERFLOW ((u_int32_t)(0x00000001)) | 121 | #define LMC_RDES_OVERFLOW ((u32)(0x00000001)) |
| 144 | #define LMC_RDES_CRC_ERROR ((u_int32_t)(0x00000002)) | 122 | #define LMC_RDES_CRC_ERROR ((u32)(0x00000002)) |
| 145 | #define LMC_RDES_DRIBBLING_BIT ((u_int32_t)(0x00000004)) | 123 | #define LMC_RDES_DRIBBLING_BIT ((u32)(0x00000004)) |
| 146 | #define LMC_RDES_REPORT_ON_MII_ERR ((u_int32_t)(0x00000008)) | 124 | #define LMC_RDES_REPORT_ON_MII_ERR ((u32)(0x00000008)) |
| 147 | #define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u_int32_t)(0x00000010)) | 125 | #define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u32)(0x00000010)) |
| 148 | #define LMC_RDES_FRAME_TYPE ((u_int32_t)(0x00000020)) | 126 | #define LMC_RDES_FRAME_TYPE ((u32)(0x00000020)) |
| 149 | #define LMC_RDES_COLLISION_SEEN ((u_int32_t)(0x00000040)) | 127 | #define LMC_RDES_COLLISION_SEEN ((u32)(0x00000040)) |
| 150 | #define LMC_RDES_FRAME_TOO_LONG ((u_int32_t)(0x00000080)) | 128 | #define LMC_RDES_FRAME_TOO_LONG ((u32)(0x00000080)) |
| 151 | #define LMC_RDES_LAST_DESCRIPTOR ((u_int32_t)(0x00000100)) | 129 | #define LMC_RDES_LAST_DESCRIPTOR ((u32)(0x00000100)) |
| 152 | #define LMC_RDES_FIRST_DESCRIPTOR ((u_int32_t)(0x00000200)) | 130 | #define LMC_RDES_FIRST_DESCRIPTOR ((u32)(0x00000200)) |
| 153 | #define LMC_RDES_MULTICAST_FRAME ((u_int32_t)(0x00000400)) | 131 | #define LMC_RDES_MULTICAST_FRAME ((u32)(0x00000400)) |
| 154 | #define LMC_RDES_RUNT_FRAME ((u_int32_t)(0x00000800)) | 132 | #define LMC_RDES_RUNT_FRAME ((u32)(0x00000800)) |
| 155 | #define LMC_RDES_DATA_TYPE ((u_int32_t)(0x00003000)) | 133 | #define LMC_RDES_DATA_TYPE ((u32)(0x00003000)) |
| 156 | #define LMC_RDES_LENGTH_ERROR ((u_int32_t)(0x00004000)) | 134 | #define LMC_RDES_LENGTH_ERROR ((u32)(0x00004000)) |
| 157 | #define LMC_RDES_ERROR_SUMMARY ((u_int32_t)(0x00008000)) | 135 | #define LMC_RDES_ERROR_SUMMARY ((u32)(0x00008000)) |
| 158 | #define LMC_RDES_FRAME_LENGTH ((u_int32_t)(0x3FFF0000)) | 136 | #define LMC_RDES_FRAME_LENGTH ((u32)(0x3FFF0000)) |
| 159 | #define LMC_RDES_OWN_BIT ((u_int32_t)(0x80000000)) | 137 | #define LMC_RDES_OWN_BIT ((u32)(0x80000000)) |
| 160 | 138 | ||
| 161 | #define RDES_FRAME_LENGTH_BIT_NUMBER 16 | 139 | #define RDES_FRAME_LENGTH_BIT_NUMBER 16 |
| 162 | 140 | ||
| 163 | #define LMC_RDES_ERROR_MASK ( (u_int32_t)( \ | 141 | #define LMC_RDES_ERROR_MASK ( (u32)( \ |
| 164 | LMC_RDES_OVERFLOW \ | 142 | LMC_RDES_OVERFLOW \ |
| 165 | | LMC_RDES_DRIBBLING_BIT \ | 143 | | LMC_RDES_DRIBBLING_BIT \ |
| 166 | | LMC_RDES_REPORT_ON_MII_ERR \ | 144 | | LMC_RDES_REPORT_ON_MII_ERR \ |
| @@ -172,32 +150,32 @@ struct lmc_regfile_t { | |||
| 172 | */ | 150 | */ |
| 173 | 151 | ||
| 174 | typedef struct { | 152 | typedef struct { |
| 175 | u_int32_t n; | 153 | u32 n; |
| 176 | u_int32_t m; | 154 | u32 m; |
| 177 | u_int32_t v; | 155 | u32 v; |
| 178 | u_int32_t x; | 156 | u32 x; |
| 179 | u_int32_t r; | 157 | u32 r; |
| 180 | u_int32_t f; | 158 | u32 f; |
| 181 | u_int32_t exact; | 159 | u32 exact; |
| 182 | } lmc_av9110_t; | 160 | } lmc_av9110_t; |
| 183 | 161 | ||
| 184 | /* | 162 | /* |
| 185 | * Common structure passed to the ioctl code. | 163 | * Common structure passed to the ioctl code. |
| 186 | */ | 164 | */ |
| 187 | struct lmc___ctl { | 165 | struct lmc___ctl { |
| 188 | u_int32_t cardtype; | 166 | u32 cardtype; |
| 189 | u_int32_t clock_source; /* HSSI, T1 */ | 167 | u32 clock_source; /* HSSI, T1 */ |
| 190 | u_int32_t clock_rate; /* T1 */ | 168 | u32 clock_rate; /* T1 */ |
| 191 | u_int32_t crc_length; | 169 | u32 crc_length; |
| 192 | u_int32_t cable_length; /* DS3 */ | 170 | u32 cable_length; /* DS3 */ |
| 193 | u_int32_t scrambler_onoff; /* DS3 */ | 171 | u32 scrambler_onoff; /* DS3 */ |
| 194 | u_int32_t cable_type; /* T1 */ | 172 | u32 cable_type; /* T1 */ |
| 195 | u_int32_t keepalive_onoff; /* protocol */ | 173 | u32 keepalive_onoff; /* protocol */ |
| 196 | u_int32_t ticks; /* ticks/sec */ | 174 | u32 ticks; /* ticks/sec */ |
| 197 | union { | 175 | union { |
| 198 | lmc_av9110_t ssi; | 176 | lmc_av9110_t ssi; |
| 199 | } cardspec; | 177 | } cardspec; |
| 200 | u_int32_t circuit_type; /* T1 or E1 */ | 178 | u32 circuit_type; /* T1 or E1 */ |
| 201 | }; | 179 | }; |
| 202 | 180 | ||
| 203 | 181 | ||
| @@ -244,108 +222,69 @@ struct lmc___media { | |||
| 244 | 222 | ||
| 245 | #define STATCHECK 0xBEEFCAFE | 223 | #define STATCHECK 0xBEEFCAFE |
| 246 | 224 | ||
| 247 | /* Included in this structure are first | 225 | struct lmc_extra_statistics |
| 248 | * - standard net_device_stats | ||
| 249 | * - some other counters used for debug and driver performance | ||
| 250 | * evaluation -baz | ||
| 251 | */ | ||
| 252 | struct lmc_statistics | ||
| 253 | { | 226 | { |
| 254 | unsigned long rx_packets; /* total packets received */ | 227 | u32 version_size; |
| 255 | unsigned long tx_packets; /* total packets transmitted */ | 228 | u32 lmc_cardtype; |
| 256 | unsigned long rx_bytes; | 229 | |
| 257 | unsigned long tx_bytes; | 230 | u32 tx_ProcTimeout; |
| 258 | 231 | u32 tx_IntTimeout; | |
| 259 | unsigned long rx_errors; /* bad packets received */ | 232 | u32 tx_NoCompleteCnt; |
| 260 | unsigned long tx_errors; /* packet transmit problems */ | 233 | u32 tx_MaxXmtsB4Int; |
| 261 | unsigned long rx_dropped; /* no space in linux buffers */ | 234 | u32 tx_TimeoutCnt; |
| 262 | unsigned long tx_dropped; /* no space available in linux */ | 235 | u32 tx_OutOfSyncPtr; |
| 263 | unsigned long multicast; /* multicast packets received */ | 236 | u32 tx_tbusy0; |
| 264 | unsigned long collisions; | 237 | u32 tx_tbusy1; |
| 265 | 238 | u32 tx_tbusy_calls; | |
| 266 | /* detailed rx_errors: */ | 239 | u32 resetCount; |
| 267 | unsigned long rx_length_errors; | 240 | u32 lmc_txfull; |
| 268 | unsigned long rx_over_errors; /* receiver ring buff overflow */ | 241 | u32 tbusy; |
| 269 | unsigned long rx_crc_errors; /* recved pkt with crc error */ | 242 | u32 dirtyTx; |
| 270 | unsigned long rx_frame_errors; /* recv'd frame alignment error */ | 243 | u32 lmc_next_tx; |
| 271 | unsigned long rx_fifo_errors; /* recv'r fifo overrun */ | 244 | u32 otherTypeCnt; |
| 272 | unsigned long rx_missed_errors; /* receiver missed packet */ | 245 | u32 lastType; |
| 273 | 246 | u32 lastTypeOK; | |
| 274 | /* detailed tx_errors */ | 247 | u32 txLoopCnt; |
| 275 | unsigned long tx_aborted_errors; | 248 | u32 usedXmtDescripCnt; |
| 276 | unsigned long tx_carrier_errors; | 249 | u32 txIndexCnt; |
| 277 | unsigned long tx_fifo_errors; | 250 | u32 rxIntLoopCnt; |
| 278 | unsigned long tx_heartbeat_errors; | 251 | |
| 279 | unsigned long tx_window_errors; | 252 | u32 rx_SmallPktCnt; |
| 280 | 253 | u32 rx_BadPktSurgeCnt; | |
| 281 | /* for cslip etc */ | 254 | u32 rx_BuffAllocErr; |
| 282 | unsigned long rx_compressed; | 255 | u32 tx_lossOfClockCnt; |
| 283 | unsigned long tx_compressed; | 256 | |
| 284 | 257 | /* T1 error counters */ | |
| 285 | /* ------------------------------------- | 258 | u32 framingBitErrorCount; |
| 286 | * Custom stats & counters follow -baz */ | 259 | u32 lineCodeViolationCount; |
| 287 | u_int32_t version_size; | 260 | |
| 288 | u_int32_t lmc_cardtype; | 261 | u32 lossOfFrameCount; |
| 289 | 262 | u32 changeOfFrameAlignmentCount; | |
| 290 | u_int32_t tx_ProcTimeout; | 263 | u32 severelyErroredFrameCount; |
| 291 | u_int32_t tx_IntTimeout; | 264 | |
| 292 | u_int32_t tx_NoCompleteCnt; | 265 | u32 check; |
| 293 | u_int32_t tx_MaxXmtsB4Int; | ||
| 294 | u_int32_t tx_TimeoutCnt; | ||
| 295 | u_int32_t tx_OutOfSyncPtr; | ||
| 296 | u_int32_t tx_tbusy0; | ||
| 297 | u_int32_t tx_tbusy1; | ||
| 298 | u_int32_t tx_tbusy_calls; | ||
| 299 | u_int32_t resetCount; | ||
| 300 | u_int32_t lmc_txfull; | ||
| 301 | u_int32_t tbusy; | ||
| 302 | u_int32_t dirtyTx; | ||
| 303 | u_int32_t lmc_next_tx; | ||
| 304 | u_int32_t otherTypeCnt; | ||
| 305 | u_int32_t lastType; | ||
| 306 | u_int32_t lastTypeOK; | ||
| 307 | u_int32_t txLoopCnt; | ||
| 308 | u_int32_t usedXmtDescripCnt; | ||
| 309 | u_int32_t txIndexCnt; | ||
| 310 | u_int32_t rxIntLoopCnt; | ||
| 311 | |||
| 312 | u_int32_t rx_SmallPktCnt; | ||
| 313 | u_int32_t rx_BadPktSurgeCnt; | ||
| 314 | u_int32_t rx_BuffAllocErr; | ||
| 315 | u_int32_t tx_lossOfClockCnt; | ||
| 316 | |||
| 317 | /* T1 error counters */ | ||
| 318 | u_int32_t framingBitErrorCount; | ||
| 319 | u_int32_t lineCodeViolationCount; | ||
| 320 | |||
| 321 | u_int32_t lossOfFrameCount; | ||
| 322 | u_int32_t changeOfFrameAlignmentCount; | ||
| 323 | u_int32_t severelyErroredFrameCount; | ||
| 324 | |||
| 325 | u_int32_t check; | ||
| 326 | }; | 266 | }; |
| 327 | 267 | ||
| 328 | |||
| 329 | typedef struct lmc_xinfo { | 268 | typedef struct lmc_xinfo { |
| 330 | u_int32_t Magic0; /* BEEFCAFE */ | 269 | u32 Magic0; /* BEEFCAFE */ |
| 331 | 270 | ||
| 332 | u_int32_t PciCardType; | 271 | u32 PciCardType; |
| 333 | u_int32_t PciSlotNumber; /* PCI slot number */ | 272 | u32 PciSlotNumber; /* PCI slot number */ |
| 334 | 273 | ||
| 335 | u_int16_t DriverMajorVersion; | 274 | u16 DriverMajorVersion; |
| 336 | u_int16_t DriverMinorVersion; | 275 | u16 DriverMinorVersion; |
| 337 | u_int16_t DriverSubVersion; | 276 | u16 DriverSubVersion; |
| 338 | 277 | ||
| 339 | u_int16_t XilinxRevisionNumber; | 278 | u16 XilinxRevisionNumber; |
| 340 | u_int16_t MaxFrameSize; | 279 | u16 MaxFrameSize; |
| 341 | 280 | ||
| 342 | u_int16_t t1_alarm1_status; | 281 | u16 t1_alarm1_status; |
| 343 | u_int16_t t1_alarm2_status; | 282 | u16 t1_alarm2_status; |
| 344 | 283 | ||
| 345 | int link_status; | 284 | int link_status; |
| 346 | u_int32_t mii_reg16; | 285 | u32 mii_reg16; |
| 347 | 286 | ||
| 348 | u_int32_t Magic1; /* DEADBEEF */ | 287 | u32 Magic1; /* DEADBEEF */ |
| 349 | } LMC_XINFO; | 288 | } LMC_XINFO; |
| 350 | 289 | ||
| 351 | 290 | ||
| @@ -353,23 +292,22 @@ typedef struct lmc_xinfo { | |||
| 353 | * forward decl | 292 | * forward decl |
| 354 | */ | 293 | */ |
| 355 | struct lmc___softc { | 294 | struct lmc___softc { |
| 356 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | ||
| 357 | char *name; | 295 | char *name; |
| 358 | u8 board_idx; | 296 | u8 board_idx; |
| 359 | struct lmc_statistics stats; | 297 | struct lmc_extra_statistics extra_stats; |
| 360 | struct net_device *lmc_device; | 298 | struct net_device *lmc_device; |
| 361 | 299 | ||
| 362 | int hang, rxdesc, bad_packet, some_counter; | 300 | int hang, rxdesc, bad_packet, some_counter; |
| 363 | u_int32_t txgo; | 301 | u32 txgo; |
| 364 | struct lmc_regfile_t lmc_csrs; | 302 | struct lmc_regfile_t lmc_csrs; |
| 365 | volatile u_int32_t lmc_txtick; | 303 | volatile u32 lmc_txtick; |
| 366 | volatile u_int32_t lmc_rxtick; | 304 | volatile u32 lmc_rxtick; |
| 367 | u_int32_t lmc_flags; | 305 | u32 lmc_flags; |
| 368 | u_int32_t lmc_intrmask; /* our copy of csr_intr */ | 306 | u32 lmc_intrmask; /* our copy of csr_intr */ |
| 369 | u_int32_t lmc_cmdmode; /* our copy of csr_cmdmode */ | 307 | u32 lmc_cmdmode; /* our copy of csr_cmdmode */ |
| 370 | u_int32_t lmc_busmode; /* our copy of csr_busmode */ | 308 | u32 lmc_busmode; /* our copy of csr_busmode */ |
| 371 | u_int32_t lmc_gpio_io; /* state of in/out settings */ | 309 | u32 lmc_gpio_io; /* state of in/out settings */ |
| 372 | u_int32_t lmc_gpio; /* state of outputs */ | 310 | u32 lmc_gpio; /* state of outputs */ |
| 373 | struct sk_buff* lmc_txq[LMC_TXDESCS]; | 311 | struct sk_buff* lmc_txq[LMC_TXDESCS]; |
| 374 | struct sk_buff* lmc_rxq[LMC_RXDESCS]; | 312 | struct sk_buff* lmc_rxq[LMC_RXDESCS]; |
| 375 | volatile | 313 | volatile |
| @@ -381,42 +319,41 @@ struct lmc___softc { | |||
| 381 | unsigned int lmc_taint_tx, lmc_taint_rx; | 319 | unsigned int lmc_taint_tx, lmc_taint_rx; |
| 382 | int lmc_tx_start, lmc_txfull; | 320 | int lmc_tx_start, lmc_txfull; |
| 383 | int lmc_txbusy; | 321 | int lmc_txbusy; |
| 384 | u_int16_t lmc_miireg16; | 322 | u16 lmc_miireg16; |
| 385 | int lmc_ok; | 323 | int lmc_ok; |
| 386 | int last_link_status; | 324 | int last_link_status; |
| 387 | int lmc_cardtype; | 325 | int lmc_cardtype; |
| 388 | u_int32_t last_frameerr; | 326 | u32 last_frameerr; |
| 389 | lmc_media_t *lmc_media; | 327 | lmc_media_t *lmc_media; |
| 390 | struct timer_list timer; | 328 | struct timer_list timer; |
| 391 | lmc_ctl_t ictl; | 329 | lmc_ctl_t ictl; |
| 392 | u_int32_t TxDescriptControlInit; | 330 | u32 TxDescriptControlInit; |
| 393 | 331 | ||
| 394 | int tx_TimeoutInd; /* additional driver state */ | 332 | int tx_TimeoutInd; /* additional driver state */ |
| 395 | int tx_TimeoutDisplay; | 333 | int tx_TimeoutDisplay; |
| 396 | unsigned int lastlmc_taint_tx; | 334 | unsigned int lastlmc_taint_tx; |
| 397 | int lasttx_packets; | 335 | int lasttx_packets; |
| 398 | u_int32_t tx_clockState; | 336 | u32 tx_clockState; |
| 399 | u_int32_t lmc_crcSize; | 337 | u32 lmc_crcSize; |
| 400 | LMC_XINFO lmc_xinfo; | 338 | LMC_XINFO lmc_xinfo; |
| 401 | char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */ | 339 | char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */ |
| 402 | char lmc_timing; /* for HSSI and SSI */ | 340 | char lmc_timing; /* for HSSI and SSI */ |
| 403 | int got_irq; | 341 | int got_irq; |
| 404 | 342 | ||
| 405 | char last_led_err[4]; | 343 | char last_led_err[4]; |
| 406 | 344 | ||
| 407 | u32 last_int; | 345 | u32 last_int; |
| 408 | u32 num_int; | 346 | u32 num_int; |
| 409 | 347 | ||
| 410 | spinlock_t lmc_lock; | 348 | spinlock_t lmc_lock; |
| 411 | u_int16_t if_type; /* PPP or NET */ | 349 | u16 if_type; /* HDLC/PPP or NET */ |
| 412 | struct ppp_device *pd; | ||
| 413 | 350 | ||
| 414 | /* Failure cases */ | 351 | /* Failure cases */ |
| 415 | u8 failed_ring; | 352 | u8 failed_ring; |
| 416 | u8 failed_recv_alloc; | 353 | u8 failed_recv_alloc; |
| 417 | 354 | ||
| 418 | /* Structure check */ | 355 | /* Structure check */ |
| 419 | u32 check; | 356 | u32 check; |
| 420 | }; | 357 | }; |
| 421 | 358 | ||
| 422 | #define LMC_PCI_TIME 1 | 359 | #define LMC_PCI_TIME 1 |
| @@ -512,8 +449,8 @@ struct lmc___softc { | |||
| 512 | | TULIP_STS_TXUNDERFLOW\ | 449 | | TULIP_STS_TXUNDERFLOW\ |
| 513 | | TULIP_STS_RXSTOPPED ) | 450 | | TULIP_STS_RXSTOPPED ) |
| 514 | 451 | ||
| 515 | #define DESC_OWNED_BY_SYSTEM ((u_int32_t)(0x00000000)) | 452 | #define DESC_OWNED_BY_SYSTEM ((u32)(0x00000000)) |
| 516 | #define DESC_OWNED_BY_DC21X4 ((u_int32_t)(0x80000000)) | 453 | #define DESC_OWNED_BY_DC21X4 ((u32)(0x80000000)) |
| 517 | 454 | ||
| 518 | #ifndef TULIP_CMD_RECEIVEALL | 455 | #ifndef TULIP_CMD_RECEIVEALL |
| 519 | #define TULIP_CMD_RECEIVEALL 0x40000000L | 456 | #define TULIP_CMD_RECEIVEALL 0x40000000L |
| @@ -525,46 +462,9 @@ struct lmc___softc { | |||
| 525 | #define LMC_ADAP_SSI 4 | 462 | #define LMC_ADAP_SSI 4 |
| 526 | #define LMC_ADAP_T1 5 | 463 | #define LMC_ADAP_T1 5 |
| 527 | 464 | ||
| 528 | #define HDLC_HDR_LEN 4 | ||
| 529 | #define HDLC_ADDR_LEN 1 | ||
| 530 | #define HDLC_SLARP 0x8035 | ||
| 531 | #define LMC_MTU 1500 | 465 | #define LMC_MTU 1500 |
| 532 | #define SLARP_LINECHECK 2 | ||
| 533 | 466 | ||
| 534 | #define LMC_CRC_LEN_16 2 /* 16-bit CRC */ | 467 | #define LMC_CRC_LEN_16 2 /* 16-bit CRC */ |
| 535 | #define LMC_CRC_LEN_32 4 | 468 | #define LMC_CRC_LEN_32 4 |
| 536 | 469 | ||
| 537 | #ifdef LMC_HDLC | ||
| 538 | /* definition of an hdlc header. */ | ||
| 539 | struct hdlc_hdr | ||
| 540 | { | ||
| 541 | u8 address; | ||
| 542 | u8 control; | ||
| 543 | u16 type; | ||
| 544 | }; | ||
| 545 | |||
| 546 | /* definition of a slarp header. */ | ||
| 547 | struct slarp | ||
| 548 | { | ||
| 549 | long code; | ||
| 550 | union sl | ||
| 551 | { | ||
| 552 | struct | ||
| 553 | { | ||
| 554 | ulong address; | ||
| 555 | ulong mask; | ||
| 556 | ushort unused; | ||
| 557 | } add; | ||
| 558 | struct | ||
| 559 | { | ||
| 560 | ulong mysequence; | ||
| 561 | ulong yoursequence; | ||
| 562 | ushort reliability; | ||
| 563 | ulong time; | ||
| 564 | } chk; | ||
| 565 | } t; | ||
| 566 | }; | ||
| 567 | #endif /* LMC_HDLC */ | ||
| 568 | |||
| 569 | |||
| 570 | #endif /* _LMC_VAR_H_ */ | 470 | #endif /* _LMC_VAR_H_ */ |
diff --git a/drivers/net/wan/pc300.h b/drivers/net/wan/pc300.h index 63e9fcf31fb8..2e4f84f6cad4 100644 --- a/drivers/net/wan/pc300.h +++ b/drivers/net/wan/pc300.h | |||
| @@ -100,31 +100,14 @@ | |||
| 100 | #define _PC300_H | 100 | #define _PC300_H |
| 101 | 101 | ||
| 102 | #include <linux/hdlc.h> | 102 | #include <linux/hdlc.h> |
| 103 | #include <net/syncppp.h> | ||
| 104 | #include "hd64572.h" | 103 | #include "hd64572.h" |
| 105 | #include "pc300-falc-lh.h" | 104 | #include "pc300-falc-lh.h" |
| 106 | 105 | ||
| 107 | #ifndef CY_TYPES | 106 | #define PC300_PROTO_MLPPP 1 |
| 108 | #define CY_TYPES | ||
| 109 | typedef __u64 ucdouble; /* 64 bits, unsigned */ | ||
| 110 | typedef __u32 uclong; /* 32 bits, unsigned */ | ||
| 111 | typedef __u16 ucshort; /* 16 bits, unsigned */ | ||
| 112 | typedef __u8 ucchar; /* 8 bits, unsigned */ | ||
| 113 | #endif /* CY_TYPES */ | ||
| 114 | 107 | ||
| 115 | #define PC300_PROTO_MLPPP 1 | ||
| 116 | |||
| 117 | #define PC300_KERNEL "2.4.x" /* Kernel supported by this driver */ | ||
| 118 | |||
| 119 | #define PC300_DEVNAME "hdlc" /* Dev. name base (for hdlc0, hdlc1, etc.) */ | ||
| 120 | #define PC300_MAXINDEX 100 /* Max dev. name index (the '0' in hdlc0) */ | ||
| 121 | |||
| 122 | #define PC300_MAXCARDS 4 /* Max number of cards per system */ | ||
| 123 | #define PC300_MAXCHAN 2 /* Number of channels per card */ | 108 | #define PC300_MAXCHAN 2 /* Number of channels per card */ |
| 124 | 109 | ||
| 125 | #define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */ | ||
| 126 | #define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */ | 110 | #define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */ |
| 127 | #define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */ | ||
| 128 | #define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */ | 111 | #define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */ |
| 129 | 112 | ||
| 130 | #define PC300_OSC_CLOCK 24576000 | 113 | #define PC300_OSC_CLOCK 24576000 |
| @@ -160,26 +143,14 @@ typedef __u8 ucchar; /* 8 bits, unsigned */ | |||
| 160 | * Memory access functions/macros * | 143 | * Memory access functions/macros * |
| 161 | * (required to support Alpha systems) * | 144 | * (required to support Alpha systems) * |
| 162 | ***************************************/ | 145 | ***************************************/ |
| 163 | #ifdef __KERNEL__ | 146 | #define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();} |
| 164 | #define cpc_writeb(port,val) {writeb((ucchar)(val),(port)); mb();} | ||
| 165 | #define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();} | 147 | #define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();} |
| 166 | #define cpc_writel(port,val) {writel((uclong)(val),(port)); mb();} | 148 | #define cpc_writel(port,val) {writel((u32)(val),(port)); mb();} |
| 167 | 149 | ||
| 168 | #define cpc_readb(port) readb(port) | 150 | #define cpc_readb(port) readb(port) |
| 169 | #define cpc_readw(port) readw(port) | 151 | #define cpc_readw(port) readw(port) |
| 170 | #define cpc_readl(port) readl(port) | 152 | #define cpc_readl(port) readl(port) |
| 171 | 153 | ||
| 172 | #else /* __KERNEL__ */ | ||
| 173 | #define cpc_writeb(port,val) (*(volatile ucchar *)(port) = (ucchar)(val)) | ||
| 174 | #define cpc_writew(port,val) (*(volatile ucshort *)(port) = (ucshort)(val)) | ||
| 175 | #define cpc_writel(port,val) (*(volatile uclong *)(port) = (uclong)(val)) | ||
| 176 | |||
| 177 | #define cpc_readb(port) (*(volatile ucchar *)(port)) | ||
| 178 | #define cpc_readw(port) (*(volatile ucshort *)(port)) | ||
| 179 | #define cpc_readl(port) (*(volatile uclong *)(port)) | ||
| 180 | |||
| 181 | #endif /* __KERNEL__ */ | ||
| 182 | |||
| 183 | /****** Data Structures *****************************************************/ | 154 | /****** Data Structures *****************************************************/ |
| 184 | 155 | ||
| 185 | /* | 156 | /* |
| @@ -188,15 +159,15 @@ typedef __u8 ucchar; /* 8 bits, unsigned */ | |||
| 188 | * (memory mapped). | 159 | * (memory mapped). |
| 189 | */ | 160 | */ |
| 190 | struct RUNTIME_9050 { | 161 | struct RUNTIME_9050 { |
| 191 | uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ | 162 | u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ |
| 192 | uclong loc_rom_range; /* 10h : Local ROM Range */ | 163 | u32 loc_rom_range; /* 10h : Local ROM Range */ |
| 193 | uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ | 164 | u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ |
| 194 | uclong loc_rom_base; /* 24h : Local ROM Base */ | 165 | u32 loc_rom_base; /* 24h : Local ROM Base */ |
| 195 | uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ | 166 | u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ |
| 196 | uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */ | 167 | u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ |
| 197 | uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ | 168 | u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ |
| 198 | uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ | 169 | u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ |
| 199 | uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ | 170 | u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ |
| 200 | }; | 171 | }; |
| 201 | 172 | ||
| 202 | #define PLX_9050_LINT1_ENABLE 0x01 | 173 | #define PLX_9050_LINT1_ENABLE 0x01 |
| @@ -240,66 +211,66 @@ struct RUNTIME_9050 { | |||
| 240 | #define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */ | 211 | #define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */ |
| 241 | 212 | ||
| 242 | typedef struct falc { | 213 | typedef struct falc { |
| 243 | ucchar sync; /* If true FALC is synchronized */ | 214 | u8 sync; /* If true FALC is synchronized */ |
| 244 | ucchar active; /* if TRUE then already active */ | 215 | u8 active; /* if TRUE then already active */ |
| 245 | ucchar loop_active; /* if TRUE a line loopback UP was received */ | 216 | u8 loop_active; /* if TRUE a line loopback UP was received */ |
| 246 | ucchar loop_gen; /* if TRUE a line loopback UP was issued */ | 217 | u8 loop_gen; /* if TRUE a line loopback UP was issued */ |
| 247 | 218 | ||
| 248 | ucchar num_channels; | 219 | u8 num_channels; |
| 249 | ucchar offset; /* 1 for T1, 0 for E1 */ | 220 | u8 offset; /* 1 for T1, 0 for E1 */ |
| 250 | ucchar full_bandwidth; | 221 | u8 full_bandwidth; |
| 251 | 222 | ||
| 252 | ucchar xmb_cause; | 223 | u8 xmb_cause; |
| 253 | ucchar multiframe_mode; | 224 | u8 multiframe_mode; |
| 254 | 225 | ||
| 255 | /* Statistics */ | 226 | /* Statistics */ |
| 256 | ucshort pden; /* Pulse Density violation count */ | 227 | u16 pden; /* Pulse Density violation count */ |
| 257 | ucshort los; /* Loss of Signal count */ | 228 | u16 los; /* Loss of Signal count */ |
| 258 | ucshort losr; /* Loss of Signal recovery count */ | 229 | u16 losr; /* Loss of Signal recovery count */ |
| 259 | ucshort lfa; /* Loss of frame alignment count */ | 230 | u16 lfa; /* Loss of frame alignment count */ |
| 260 | ucshort farec; /* Frame Alignment Recovery count */ | 231 | u16 farec; /* Frame Alignment Recovery count */ |
| 261 | ucshort lmfa; /* Loss of multiframe alignment count */ | 232 | u16 lmfa; /* Loss of multiframe alignment count */ |
| 262 | ucshort ais; /* Remote Alarm indication Signal count */ | 233 | u16 ais; /* Remote Alarm indication Signal count */ |
| 263 | ucshort sec; /* One-second timer */ | 234 | u16 sec; /* One-second timer */ |
| 264 | ucshort es; /* Errored second */ | 235 | u16 es; /* Errored second */ |
| 265 | ucshort rai; /* remote alarm received */ | 236 | u16 rai; /* remote alarm received */ |
| 266 | ucshort bec; | 237 | u16 bec; |
| 267 | ucshort fec; | 238 | u16 fec; |
| 268 | ucshort cvc; | 239 | u16 cvc; |
| 269 | ucshort cec; | 240 | u16 cec; |
| 270 | ucshort ebc; | 241 | u16 ebc; |
| 271 | 242 | ||
| 272 | /* Status */ | 243 | /* Status */ |
| 273 | ucchar red_alarm; | 244 | u8 red_alarm; |
| 274 | ucchar blue_alarm; | 245 | u8 blue_alarm; |
| 275 | ucchar loss_fa; | 246 | u8 loss_fa; |
| 276 | ucchar yellow_alarm; | 247 | u8 yellow_alarm; |
| 277 | ucchar loss_mfa; | 248 | u8 loss_mfa; |
| 278 | ucchar prbs; | 249 | u8 prbs; |
| 279 | } falc_t; | 250 | } falc_t; |
| 280 | 251 | ||
| 281 | typedef struct falc_status { | 252 | typedef struct falc_status { |
| 282 | ucchar sync; /* If true FALC is synchronized */ | 253 | u8 sync; /* If true FALC is synchronized */ |
| 283 | ucchar red_alarm; | 254 | u8 red_alarm; |
| 284 | ucchar blue_alarm; | 255 | u8 blue_alarm; |
| 285 | ucchar loss_fa; | 256 | u8 loss_fa; |
| 286 | ucchar yellow_alarm; | 257 | u8 yellow_alarm; |
| 287 | ucchar loss_mfa; | 258 | u8 loss_mfa; |
| 288 | ucchar prbs; | 259 | u8 prbs; |
| 289 | } falc_status_t; | 260 | } falc_status_t; |
| 290 | 261 | ||
| 291 | typedef struct rsv_x21_status { | 262 | typedef struct rsv_x21_status { |
| 292 | ucchar dcd; | 263 | u8 dcd; |
| 293 | ucchar dsr; | 264 | u8 dsr; |
| 294 | ucchar cts; | 265 | u8 cts; |
| 295 | ucchar rts; | 266 | u8 rts; |
| 296 | ucchar dtr; | 267 | u8 dtr; |
| 297 | } rsv_x21_status_t; | 268 | } rsv_x21_status_t; |
| 298 | 269 | ||
| 299 | typedef struct pc300stats { | 270 | typedef struct pc300stats { |
| 300 | int hw_type; | 271 | int hw_type; |
| 301 | uclong line_on; | 272 | u32 line_on; |
| 302 | uclong line_off; | 273 | u32 line_off; |
| 303 | struct net_device_stats gen_stats; | 274 | struct net_device_stats gen_stats; |
| 304 | falc_t te_stats; | 275 | falc_t te_stats; |
| 305 | } pc300stats_t; | 276 | } pc300stats_t; |
| @@ -317,28 +288,19 @@ typedef struct pc300loopback { | |||
| 317 | 288 | ||
| 318 | typedef struct pc300patterntst { | 289 | typedef struct pc300patterntst { |
| 319 | char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */ | 290 | char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */ |
| 320 | ucshort num_errors; | 291 | u16 num_errors; |
| 321 | } pc300patterntst_t; | 292 | } pc300patterntst_t; |
| 322 | 293 | ||
| 323 | typedef struct pc300dev { | 294 | typedef struct pc300dev { |
| 324 | void *if_ptr; /* General purpose pointer */ | ||
| 325 | struct pc300ch *chan; | 295 | struct pc300ch *chan; |
| 326 | ucchar trace_on; | 296 | u8 trace_on; |
| 327 | uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */ | 297 | u32 line_on; /* DCD(X.21, RSV) / sync(TE) change counters */ |
| 328 | uclong line_off; | 298 | u32 line_off; |
| 329 | #ifdef __KERNEL__ | ||
| 330 | char name[16]; | 299 | char name[16]; |
| 331 | struct net_device *dev; | 300 | struct net_device *dev; |
| 332 | |||
| 333 | void *private; | ||
| 334 | struct sk_buff *tx_skb; | ||
| 335 | union { /* This union has all the protocol-specific structures */ | ||
| 336 | struct ppp_device pppdev; | ||
| 337 | }ifu; | ||
| 338 | #ifdef CONFIG_PC300_MLPPP | 301 | #ifdef CONFIG_PC300_MLPPP |
| 339 | void *cpc_tty; /* information to PC300 TTY driver */ | 302 | void *cpc_tty; /* information to PC300 TTY driver */ |
| 340 | #endif | 303 | #endif |
| 341 | #endif /* __KERNEL__ */ | ||
| 342 | }pc300dev_t; | 304 | }pc300dev_t; |
| 343 | 305 | ||
| 344 | typedef struct pc300hw { | 306 | typedef struct pc300hw { |
| @@ -346,43 +308,42 @@ typedef struct pc300hw { | |||
| 346 | int bus; /* Bus (PCI, PMC, etc.) */ | 308 | int bus; /* Bus (PCI, PMC, etc.) */ |
| 347 | int nchan; /* number of channels */ | 309 | int nchan; /* number of channels */ |
| 348 | int irq; /* interrupt request level */ | 310 | int irq; /* interrupt request level */ |
| 349 | uclong clock; /* Board clock */ | 311 | u32 clock; /* Board clock */ |
| 350 | ucchar cpld_id; /* CPLD ID (TE only) */ | 312 | u8 cpld_id; /* CPLD ID (TE only) */ |
| 351 | ucshort cpld_reg1; /* CPLD reg 1 (TE only) */ | 313 | u16 cpld_reg1; /* CPLD reg 1 (TE only) */ |
| 352 | ucshort cpld_reg2; /* CPLD reg 2 (TE only) */ | 314 | u16 cpld_reg2; /* CPLD reg 2 (TE only) */ |
| 353 | ucshort gpioc_reg; /* PLX GPIOC reg */ | 315 | u16 gpioc_reg; /* PLX GPIOC reg */ |
| 354 | ucshort intctl_reg; /* PLX Int Ctrl/Status reg */ | 316 | u16 intctl_reg; /* PLX Int Ctrl/Status reg */ |
| 355 | uclong iophys; /* PLX registers I/O base */ | 317 | u32 iophys; /* PLX registers I/O base */ |
| 356 | uclong iosize; /* PLX registers I/O size */ | 318 | u32 iosize; /* PLX registers I/O size */ |
| 357 | uclong plxphys; /* PLX registers MMIO base (physical) */ | 319 | u32 plxphys; /* PLX registers MMIO base (physical) */ |
| 358 | void __iomem * plxbase; /* PLX registers MMIO base (virtual) */ | 320 | void __iomem * plxbase; /* PLX registers MMIO base (virtual) */ |
| 359 | uclong plxsize; /* PLX registers MMIO size */ | 321 | u32 plxsize; /* PLX registers MMIO size */ |
| 360 | uclong scaphys; /* SCA registers MMIO base (physical) */ | 322 | u32 scaphys; /* SCA registers MMIO base (physical) */ |
| 361 | void __iomem * scabase; /* SCA registers MMIO base (virtual) */ | 323 | void __iomem * scabase; /* SCA registers MMIO base (virtual) */ |
| 362 | uclong scasize; /* SCA registers MMIO size */ | 324 | u32 scasize; /* SCA registers MMIO size */ |
| 363 | uclong ramphys; /* On-board RAM MMIO base (physical) */ | 325 | u32 ramphys; /* On-board RAM MMIO base (physical) */ |
| 364 | void __iomem * rambase; /* On-board RAM MMIO base (virtual) */ | 326 | void __iomem * rambase; /* On-board RAM MMIO base (virtual) */ |
| 365 | uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */ | 327 | u32 alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */ |
| 366 | uclong ramsize; /* On-board RAM MMIO size */ | 328 | u32 ramsize; /* On-board RAM MMIO size */ |
| 367 | uclong falcphys; /* FALC registers MMIO base (physical) */ | 329 | u32 falcphys; /* FALC registers MMIO base (physical) */ |
| 368 | void __iomem * falcbase;/* FALC registers MMIO base (virtual) */ | 330 | void __iomem * falcbase;/* FALC registers MMIO base (virtual) */ |
| 369 | uclong falcsize; /* FALC registers MMIO size */ | 331 | u32 falcsize; /* FALC registers MMIO size */ |
| 370 | } pc300hw_t; | 332 | } pc300hw_t; |
| 371 | 333 | ||
| 372 | typedef struct pc300chconf { | 334 | typedef struct pc300chconf { |
| 373 | sync_serial_settings phys_settings; /* Clock type/rate (in bps), | 335 | sync_serial_settings phys_settings; /* Clock type/rate (in bps), |
| 374 | loopback mode */ | 336 | loopback mode */ |
| 375 | raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */ | 337 | raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */ |
| 376 | uclong media; /* HW media (RS232, V.35, etc.) */ | 338 | u32 media; /* HW media (RS232, V.35, etc.) */ |
| 377 | uclong proto; /* Protocol (PPP, X.25, etc.) */ | 339 | u32 proto; /* Protocol (PPP, X.25, etc.) */ |
| 378 | ucchar monitor; /* Monitor mode (0 = off, !0 = on) */ | ||
| 379 | 340 | ||
| 380 | /* TE-specific parameters */ | 341 | /* TE-specific parameters */ |
| 381 | ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */ | 342 | u8 lcode; /* Line Code (AMI, B8ZS, etc.) */ |
| 382 | ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */ | 343 | u8 fr_mode; /* Frame Mode (ESF, D4, etc.) */ |
| 383 | ucchar lbo; /* Line Build Out */ | 344 | u8 lbo; /* Line Build Out */ |
| 384 | ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */ | 345 | u8 rx_sens; /* Rx Sensitivity (long- or short-haul) */ |
| 385 | uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */ | 346 | u32 tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */ |
| 386 | } pc300chconf_t; | 347 | } pc300chconf_t; |
| 387 | 348 | ||
| 388 | typedef struct pc300ch { | 349 | typedef struct pc300ch { |
| @@ -390,20 +351,18 @@ typedef struct pc300ch { | |||
| 390 | int channel; | 351 | int channel; |
| 391 | pc300dev_t d; | 352 | pc300dev_t d; |
| 392 | pc300chconf_t conf; | 353 | pc300chconf_t conf; |
| 393 | ucchar tx_first_bd; /* First TX DMA block descr. w/ data */ | 354 | u8 tx_first_bd; /* First TX DMA block descr. w/ data */ |
| 394 | ucchar tx_next_bd; /* Next free TX DMA block descriptor */ | 355 | u8 tx_next_bd; /* Next free TX DMA block descriptor */ |
| 395 | ucchar rx_first_bd; /* First free RX DMA block descriptor */ | 356 | u8 rx_first_bd; /* First free RX DMA block descriptor */ |
| 396 | ucchar rx_last_bd; /* Last free RX DMA block descriptor */ | 357 | u8 rx_last_bd; /* Last free RX DMA block descriptor */ |
| 397 | ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */ | 358 | u8 nfree_tx_bd; /* Number of free TX DMA block descriptors */ |
| 398 | falc_t falc; /* FALC structure (TE only) */ | 359 | falc_t falc; /* FALC structure (TE only) */ |
| 399 | } pc300ch_t; | 360 | } pc300ch_t; |
| 400 | 361 | ||
| 401 | typedef struct pc300 { | 362 | typedef struct pc300 { |
| 402 | pc300hw_t hw; /* hardware config. */ | 363 | pc300hw_t hw; /* hardware config. */ |
| 403 | pc300ch_t chan[PC300_MAXCHAN]; | 364 | pc300ch_t chan[PC300_MAXCHAN]; |
| 404 | #ifdef __KERNEL__ | ||
| 405 | spinlock_t card_lock; | 365 | spinlock_t card_lock; |
| 406 | #endif /* __KERNEL__ */ | ||
| 407 | } pc300_t; | 366 | } pc300_t; |
| 408 | 367 | ||
| 409 | typedef struct pc300conf { | 368 | typedef struct pc300conf { |
| @@ -471,12 +430,7 @@ enum pc300_loopback_cmds { | |||
| 471 | #define PC300_TX_QUEUE_LEN 100 | 430 | #define PC300_TX_QUEUE_LEN 100 |
| 472 | #define PC300_DEF_MTU 1600 | 431 | #define PC300_DEF_MTU 1600 |
| 473 | 432 | ||
| 474 | #ifdef __KERNEL__ | ||
| 475 | /* Function Prototypes */ | 433 | /* Function Prototypes */ |
| 476 | void tx_dma_start(pc300_t *, int); | ||
| 477 | int cpc_open(struct net_device *dev); | 434 | int cpc_open(struct net_device *dev); |
| 478 | int cpc_set_media(hdlc_device *, int); | ||
| 479 | #endif /* __KERNEL__ */ | ||
| 480 | 435 | ||
| 481 | #endif /* _PC300_H */ | 436 | #endif /* _PC300_H */ |
| 482 | |||
diff --git a/drivers/net/wan/pc300_drv.c b/drivers/net/wan/pc300_drv.c index 334170527755..d0a8d1e352ac 100644 --- a/drivers/net/wan/pc300_drv.c +++ b/drivers/net/wan/pc300_drv.c | |||
| @@ -227,8 +227,6 @@ static char rcsid[] = | |||
| 227 | #include <linux/netdevice.h> | 227 | #include <linux/netdevice.h> |
| 228 | #include <linux/spinlock.h> | 228 | #include <linux/spinlock.h> |
| 229 | #include <linux/if.h> | 229 | #include <linux/if.h> |
| 230 | |||
| 231 | #include <net/syncppp.h> | ||
| 232 | #include <net/arp.h> | 230 | #include <net/arp.h> |
| 233 | 231 | ||
| 234 | #include <asm/io.h> | 232 | #include <asm/io.h> |
| @@ -285,8 +283,8 @@ static void rx_dma_buf_init(pc300_t *, int); | |||
| 285 | static void tx_dma_buf_check(pc300_t *, int); | 283 | static void tx_dma_buf_check(pc300_t *, int); |
| 286 | static void rx_dma_buf_check(pc300_t *, int); | 284 | static void rx_dma_buf_check(pc300_t *, int); |
| 287 | static irqreturn_t cpc_intr(int, void *); | 285 | static irqreturn_t cpc_intr(int, void *); |
| 288 | static int clock_rate_calc(uclong, uclong, int *); | 286 | static int clock_rate_calc(u32, u32, int *); |
| 289 | static uclong detect_ram(pc300_t *); | 287 | static u32 detect_ram(pc300_t *); |
| 290 | static void plx_init(pc300_t *); | 288 | static void plx_init(pc300_t *); |
| 291 | static void cpc_trace(struct net_device *, struct sk_buff *, char); | 289 | static void cpc_trace(struct net_device *, struct sk_buff *, char); |
| 292 | static int cpc_attach(struct net_device *, unsigned short, unsigned short); | 290 | static int cpc_attach(struct net_device *, unsigned short, unsigned short); |
| @@ -311,10 +309,10 @@ static void tx_dma_buf_pt_init(pc300_t * card, int ch) | |||
| 311 | + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); | 309 | + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); |
| 312 | 310 | ||
| 313 | for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) { | 311 | for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) { |
| 314 | cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE + | 312 | cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE + |
| 315 | (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t))); | 313 | (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t))); |
| 316 | cpc_writel(&ptdescr->ptbuf, | 314 | cpc_writel(&ptdescr->ptbuf, |
| 317 | (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN)); | 315 | (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN)); |
| 318 | } | 316 | } |
| 319 | } | 317 | } |
| 320 | 318 | ||
| @@ -341,10 +339,10 @@ static void rx_dma_buf_pt_init(pc300_t * card, int ch) | |||
| 341 | + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); | 339 | + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); |
| 342 | 340 | ||
| 343 | for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) { | 341 | for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) { |
| 344 | cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE + | 342 | cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE + |
| 345 | (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t))); | 343 | (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t))); |
| 346 | cpc_writel(&ptdescr->ptbuf, | 344 | cpc_writel(&ptdescr->ptbuf, |
| 347 | (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN)); | 345 | (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN)); |
| 348 | } | 346 | } |
| 349 | } | 347 | } |
| 350 | 348 | ||
| @@ -367,8 +365,8 @@ static void tx_dma_buf_check(pc300_t * card, int ch) | |||
| 367 | { | 365 | { |
| 368 | volatile pcsca_bd_t __iomem *ptdescr; | 366 | volatile pcsca_bd_t __iomem *ptdescr; |
| 369 | int i; | 367 | int i; |
| 370 | ucshort first_bd = card->chan[ch].tx_first_bd; | 368 | u16 first_bd = card->chan[ch].tx_first_bd; |
| 371 | ucshort next_bd = card->chan[ch].tx_next_bd; | 369 | u16 next_bd = card->chan[ch].tx_next_bd; |
| 372 | 370 | ||
| 373 | printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch, | 371 | printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch, |
| 374 | first_bd, TX_BD_ADDR(ch, first_bd), | 372 | first_bd, TX_BD_ADDR(ch, first_bd), |
| @@ -392,9 +390,9 @@ static void tx1_dma_buf_check(pc300_t * card, int ch) | |||
| 392 | { | 390 | { |
| 393 | volatile pcsca_bd_t __iomem *ptdescr; | 391 | volatile pcsca_bd_t __iomem *ptdescr; |
| 394 | int i; | 392 | int i; |
| 395 | ucshort first_bd = card->chan[ch].tx_first_bd; | 393 | u16 first_bd = card->chan[ch].tx_first_bd; |
| 396 | ucshort next_bd = card->chan[ch].tx_next_bd; | 394 | u16 next_bd = card->chan[ch].tx_next_bd; |
| 397 | uclong scabase = card->hw.scabase; | 395 | u32 scabase = card->hw.scabase; |
| 398 | 396 | ||
| 399 | printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd); | 397 | printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd); |
| 400 | printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch, | 398 | printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch, |
| @@ -413,13 +411,13 @@ static void tx1_dma_buf_check(pc300_t * card, int ch) | |||
| 413 | printk("\n"); | 411 | printk("\n"); |
| 414 | } | 412 | } |
| 415 | #endif | 413 | #endif |
| 416 | 414 | ||
| 417 | static void rx_dma_buf_check(pc300_t * card, int ch) | 415 | static void rx_dma_buf_check(pc300_t * card, int ch) |
| 418 | { | 416 | { |
| 419 | volatile pcsca_bd_t __iomem *ptdescr; | 417 | volatile pcsca_bd_t __iomem *ptdescr; |
| 420 | int i; | 418 | int i; |
| 421 | ucshort first_bd = card->chan[ch].rx_first_bd; | 419 | u16 first_bd = card->chan[ch].rx_first_bd; |
| 422 | ucshort last_bd = card->chan[ch].rx_last_bd; | 420 | u16 last_bd = card->chan[ch].rx_last_bd; |
| 423 | int ch_factor; | 421 | int ch_factor; |
| 424 | 422 | ||
| 425 | ch_factor = ch * N_DMA_RX_BUF; | 423 | ch_factor = ch * N_DMA_RX_BUF; |
| @@ -440,9 +438,9 @@ static void rx_dma_buf_check(pc300_t * card, int ch) | |||
| 440 | static int dma_get_rx_frame_size(pc300_t * card, int ch) | 438 | static int dma_get_rx_frame_size(pc300_t * card, int ch) |
| 441 | { | 439 | { |
| 442 | volatile pcsca_bd_t __iomem *ptdescr; | 440 | volatile pcsca_bd_t __iomem *ptdescr; |
| 443 | ucshort first_bd = card->chan[ch].rx_first_bd; | 441 | u16 first_bd = card->chan[ch].rx_first_bd; |
| 444 | int rcvd = 0; | 442 | int rcvd = 0; |
| 445 | volatile ucchar status; | 443 | volatile u8 status; |
| 446 | 444 | ||
| 447 | ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd)); | 445 | ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd)); |
| 448 | while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) { | 446 | while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) { |
| @@ -462,12 +460,12 @@ static int dma_get_rx_frame_size(pc300_t * card, int ch) | |||
| 462 | * dma_buf_write: writes a frame to the Tx DMA buffers | 460 | * dma_buf_write: writes a frame to the Tx DMA buffers |
| 463 | * NOTE: this function writes one frame at a time. | 461 | * NOTE: this function writes one frame at a time. |
| 464 | */ | 462 | */ |
| 465 | static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len) | 463 | static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len) |
| 466 | { | 464 | { |
| 467 | int i, nchar; | 465 | int i, nchar; |
| 468 | volatile pcsca_bd_t __iomem *ptdescr; | 466 | volatile pcsca_bd_t __iomem *ptdescr; |
| 469 | int tosend = len; | 467 | int tosend = len; |
| 470 | ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1; | 468 | u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1; |
| 471 | 469 | ||
| 472 | if (nbuf >= card->chan[ch].nfree_tx_bd) { | 470 | if (nbuf >= card->chan[ch].nfree_tx_bd) { |
| 473 | return -ENOMEM; | 471 | return -ENOMEM; |
| @@ -509,7 +507,7 @@ static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb) | |||
| 509 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; | 507 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; |
| 510 | volatile pcsca_bd_t __iomem *ptdescr; | 508 | volatile pcsca_bd_t __iomem *ptdescr; |
| 511 | int rcvd = 0; | 509 | int rcvd = 0; |
| 512 | volatile ucchar status; | 510 | volatile u8 status; |
| 513 | 511 | ||
| 514 | ptdescr = (card->hw.rambase + | 512 | ptdescr = (card->hw.rambase + |
| 515 | RX_BD_ADDR(ch, chan->rx_first_bd)); | 513 | RX_BD_ADDR(ch, chan->rx_first_bd)); |
| @@ -563,8 +561,8 @@ static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb) | |||
| 563 | static void tx_dma_stop(pc300_t * card, int ch) | 561 | static void tx_dma_stop(pc300_t * card, int ch) |
| 564 | { | 562 | { |
| 565 | void __iomem *scabase = card->hw.scabase; | 563 | void __iomem *scabase = card->hw.scabase; |
| 566 | ucchar drr_ena_bit = 1 << (5 + 2 * ch); | 564 | u8 drr_ena_bit = 1 << (5 + 2 * ch); |
| 567 | ucchar drr_rst_bit = 1 << (1 + 2 * ch); | 565 | u8 drr_rst_bit = 1 << (1 + 2 * ch); |
| 568 | 566 | ||
| 569 | /* Disable DMA */ | 567 | /* Disable DMA */ |
| 570 | cpc_writeb(scabase + DRR, drr_ena_bit); | 568 | cpc_writeb(scabase + DRR, drr_ena_bit); |
| @@ -574,8 +572,8 @@ static void tx_dma_stop(pc300_t * card, int ch) | |||
| 574 | static void rx_dma_stop(pc300_t * card, int ch) | 572 | static void rx_dma_stop(pc300_t * card, int ch) |
| 575 | { | 573 | { |
| 576 | void __iomem *scabase = card->hw.scabase; | 574 | void __iomem *scabase = card->hw.scabase; |
| 577 | ucchar drr_ena_bit = 1 << (4 + 2 * ch); | 575 | u8 drr_ena_bit = 1 << (4 + 2 * ch); |
| 578 | ucchar drr_rst_bit = 1 << (2 * ch); | 576 | u8 drr_rst_bit = 1 << (2 * ch); |
| 579 | 577 | ||
| 580 | /* Disable DMA */ | 578 | /* Disable DMA */ |
| 581 | cpc_writeb(scabase + DRR, drr_ena_bit); | 579 | cpc_writeb(scabase + DRR, drr_ena_bit); |
| @@ -607,7 +605,7 @@ static void rx_dma_start(pc300_t * card, int ch) | |||
| 607 | /*************************/ | 605 | /*************************/ |
| 608 | /*** FALC Routines ***/ | 606 | /*** FALC Routines ***/ |
| 609 | /*************************/ | 607 | /*************************/ |
| 610 | static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd) | 608 | static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd) |
| 611 | { | 609 | { |
| 612 | void __iomem *falcbase = card->hw.falcbase; | 610 | void __iomem *falcbase = card->hw.falcbase; |
| 613 | unsigned long i = 0; | 611 | unsigned long i = 0; |
| @@ -675,7 +673,7 @@ static void falc_intr_enable(pc300_t * card, int ch) | |||
| 675 | static void falc_open_timeslot(pc300_t * card, int ch, int timeslot) | 673 | static void falc_open_timeslot(pc300_t * card, int ch, int timeslot) |
| 676 | { | 674 | { |
| 677 | void __iomem *falcbase = card->hw.falcbase; | 675 | void __iomem *falcbase = card->hw.falcbase; |
| 678 | ucchar tshf = card->chan[ch].falc.offset; | 676 | u8 tshf = card->chan[ch].falc.offset; |
| 679 | 677 | ||
| 680 | cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch), | 678 | cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch), |
| 681 | cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) & | 679 | cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) & |
| @@ -691,7 +689,7 @@ static void falc_open_timeslot(pc300_t * card, int ch, int timeslot) | |||
| 691 | static void falc_close_timeslot(pc300_t * card, int ch, int timeslot) | 689 | static void falc_close_timeslot(pc300_t * card, int ch, int timeslot) |
| 692 | { | 690 | { |
| 693 | void __iomem *falcbase = card->hw.falcbase; | 691 | void __iomem *falcbase = card->hw.falcbase; |
| 694 | ucchar tshf = card->chan[ch].falc.offset; | 692 | u8 tshf = card->chan[ch].falc.offset; |
| 695 | 693 | ||
| 696 | cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch), | 694 | cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch), |
| 697 | cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) | | 695 | cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) | |
| @@ -812,7 +810,7 @@ static void falc_init_t1(pc300_t * card, int ch) | |||
| 812 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; | 810 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; |
| 813 | falc_t *pfalc = (falc_t *) & chan->falc; | 811 | falc_t *pfalc = (falc_t *) & chan->falc; |
| 814 | void __iomem *falcbase = card->hw.falcbase; | 812 | void __iomem *falcbase = card->hw.falcbase; |
| 815 | ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); | 813 | u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); |
| 816 | 814 | ||
| 817 | /* Switch to T1 mode (PCM 24) */ | 815 | /* Switch to T1 mode (PCM 24) */ |
| 818 | cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD); | 816 | cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD); |
| @@ -981,7 +979,7 @@ static void falc_init_e1(pc300_t * card, int ch) | |||
| 981 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; | 979 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; |
| 982 | falc_t *pfalc = (falc_t *) & chan->falc; | 980 | falc_t *pfalc = (falc_t *) & chan->falc; |
| 983 | void __iomem *falcbase = card->hw.falcbase; | 981 | void __iomem *falcbase = card->hw.falcbase; |
| 984 | ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); | 982 | u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); |
| 985 | 983 | ||
| 986 | /* Switch to E1 mode (PCM 30) */ | 984 | /* Switch to E1 mode (PCM 30) */ |
| 987 | cpc_writeb(falcbase + F_REG(FMR1, ch), | 985 | cpc_writeb(falcbase + F_REG(FMR1, ch), |
| @@ -1187,7 +1185,7 @@ static void te_config(pc300_t * card, int ch) | |||
| 1187 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; | 1185 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; |
| 1188 | falc_t *pfalc = (falc_t *) & chan->falc; | 1186 | falc_t *pfalc = (falc_t *) & chan->falc; |
| 1189 | void __iomem *falcbase = card->hw.falcbase; | 1187 | void __iomem *falcbase = card->hw.falcbase; |
| 1190 | ucchar dummy; | 1188 | u8 dummy; |
| 1191 | unsigned long flags; | 1189 | unsigned long flags; |
| 1192 | 1190 | ||
| 1193 | memset(pfalc, 0, sizeof(falc_t)); | 1191 | memset(pfalc, 0, sizeof(falc_t)); |
| @@ -1403,7 +1401,7 @@ static void falc_update_stats(pc300_t * card, int ch) | |||
| 1403 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; | 1401 | pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; |
| 1404 | falc_t *pfalc = (falc_t *) & chan->falc; | 1402 | falc_t *pfalc = (falc_t *) & chan->falc; |
| 1405 | void __iomem *falcbase = card->hw.falcbase; | 1403 | void __iomem *falcbase = card->hw.falcbase; |
| 1406 | ucshort counter; | 1404 | u16 counter; |
| 1407 | 1405 | ||
| 1408 | counter = cpc_readb(falcbase + F_REG(FECL, ch)); | 1406 | counter = cpc_readb(falcbase + F_REG(FECL, ch)); |
| 1409 | counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8; | 1407 | counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8; |
| @@ -1729,7 +1727,7 @@ static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate) | |||
| 1729 | * Description: This routine returns the bit error counter value | 1727 | * Description: This routine returns the bit error counter value |
| 1730 | *---------------------------------------------------------------------------- | 1728 | *---------------------------------------------------------------------------- |
| 1731 | */ | 1729 | */ |
| 1732 | static ucshort falc_pattern_test_error(pc300_t * card, int ch) | 1730 | static u16 falc_pattern_test_error(pc300_t * card, int ch) |
| 1733 | { | 1731 | { |
| 1734 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; | 1732 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; |
| 1735 | falc_t *pfalc = (falc_t *) & chan->falc; | 1733 | falc_t *pfalc = (falc_t *) & chan->falc; |
| @@ -1776,7 +1774,7 @@ static void cpc_tx_timeout(struct net_device *dev) | |||
| 1776 | pc300_t *card = (pc300_t *) chan->card; | 1774 | pc300_t *card = (pc300_t *) chan->card; |
| 1777 | int ch = chan->channel; | 1775 | int ch = chan->channel; |
| 1778 | unsigned long flags; | 1776 | unsigned long flags; |
| 1779 | ucchar ilar; | 1777 | u8 ilar; |
| 1780 | 1778 | ||
| 1781 | dev->stats.tx_errors++; | 1779 | dev->stats.tx_errors++; |
| 1782 | dev->stats.tx_aborted_errors++; | 1780 | dev->stats.tx_aborted_errors++; |
| @@ -1807,11 +1805,7 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 1807 | int i; | 1805 | int i; |
| 1808 | #endif | 1806 | #endif |
| 1809 | 1807 | ||
| 1810 | if (chan->conf.monitor) { | 1808 | if (!netif_carrier_ok(dev)) { |
| 1811 | /* In monitor mode no Tx is done: ignore packet */ | ||
| 1812 | dev_kfree_skb(skb); | ||
| 1813 | return 0; | ||
| 1814 | } else if (!netif_carrier_ok(dev)) { | ||
| 1815 | /* DCD must be OFF: drop packet */ | 1809 | /* DCD must be OFF: drop packet */ |
| 1816 | dev_kfree_skb(skb); | 1810 | dev_kfree_skb(skb); |
| 1817 | dev->stats.tx_errors++; | 1811 | dev->stats.tx_errors++; |
| @@ -1836,7 +1830,7 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 1836 | } | 1830 | } |
| 1837 | 1831 | ||
| 1838 | /* Write buffer to DMA buffers */ | 1832 | /* Write buffer to DMA buffers */ |
| 1839 | if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) { | 1833 | if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) { |
| 1840 | // printk("%s: write error. Dropping TX packet.\n", dev->name); | 1834 | // printk("%s: write error. Dropping TX packet.\n", dev->name); |
| 1841 | netif_stop_queue(dev); | 1835 | netif_stop_queue(dev); |
| 1842 | dev_kfree_skb(skb); | 1836 | dev_kfree_skb(skb); |
| @@ -2001,7 +1995,7 @@ static void sca_tx_intr(pc300dev_t *dev) | |||
| 2001 | static void sca_intr(pc300_t * card) | 1995 | static void sca_intr(pc300_t * card) |
| 2002 | { | 1996 | { |
| 2003 | void __iomem *scabase = card->hw.scabase; | 1997 | void __iomem *scabase = card->hw.scabase; |
| 2004 | volatile uclong status; | 1998 | volatile u32 status; |
| 2005 | int ch; | 1999 | int ch; |
| 2006 | int intr_count = 0; | 2000 | int intr_count = 0; |
| 2007 | unsigned char dsr_rx; | 2001 | unsigned char dsr_rx; |
| @@ -2016,7 +2010,7 @@ static void sca_intr(pc300_t * card) | |||
| 2016 | 2010 | ||
| 2017 | /**** Reception ****/ | 2011 | /**** Reception ****/ |
| 2018 | if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) { | 2012 | if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) { |
| 2019 | ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch)); | 2013 | u8 drx_stat = cpc_readb(scabase + DSR_RX(ch)); |
| 2020 | 2014 | ||
| 2021 | /* Clear RX interrupts */ | 2015 | /* Clear RX interrupts */ |
| 2022 | cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE); | 2016 | cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE); |
| @@ -2090,7 +2084,7 @@ static void sca_intr(pc300_t * card) | |||
| 2090 | 2084 | ||
| 2091 | /**** Transmission ****/ | 2085 | /**** Transmission ****/ |
| 2092 | if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) { | 2086 | if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) { |
| 2093 | ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch)); | 2087 | u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch)); |
| 2094 | 2088 | ||
| 2095 | /* Clear TX interrupts */ | 2089 | /* Clear TX interrupts */ |
| 2096 | cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE); | 2090 | cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE); |
| @@ -2134,7 +2128,7 @@ static void sca_intr(pc300_t * card) | |||
| 2134 | 2128 | ||
| 2135 | /**** MSCI ****/ | 2129 | /**** MSCI ****/ |
| 2136 | if (status & IR0_M(IR0_RXINTA, ch)) { | 2130 | if (status & IR0_M(IR0_RXINTA, ch)) { |
| 2137 | ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch)); | 2131 | u8 st1 = cpc_readb(scabase + M_REG(ST1, ch)); |
| 2138 | 2132 | ||
| 2139 | /* Clear MSCI interrupts */ | 2133 | /* Clear MSCI interrupts */ |
| 2140 | cpc_writeb(scabase + M_REG(ST1, ch), st1); | 2134 | cpc_writeb(scabase + M_REG(ST1, ch), st1); |
| @@ -2176,7 +2170,7 @@ static void sca_intr(pc300_t * card) | |||
| 2176 | } | 2170 | } |
| 2177 | } | 2171 | } |
| 2178 | 2172 | ||
| 2179 | static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1) | 2173 | static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1) |
| 2180 | { | 2174 | { |
| 2181 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; | 2175 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; |
| 2182 | falc_t *pfalc = (falc_t *) & chan->falc; | 2176 | falc_t *pfalc = (falc_t *) & chan->falc; |
| @@ -2201,7 +2195,7 @@ static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1) | |||
| 2201 | } | 2195 | } |
| 2202 | } | 2196 | } |
| 2203 | 2197 | ||
| 2204 | static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp) | 2198 | static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp) |
| 2205 | { | 2199 | { |
| 2206 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; | 2200 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; |
| 2207 | falc_t *pfalc = (falc_t *) & chan->falc; | 2201 | falc_t *pfalc = (falc_t *) & chan->falc; |
| @@ -2231,8 +2225,8 @@ static void falc_t1_intr(pc300_t * card, int ch) | |||
| 2231 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; | 2225 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; |
| 2232 | falc_t *pfalc = (falc_t *) & chan->falc; | 2226 | falc_t *pfalc = (falc_t *) & chan->falc; |
| 2233 | void __iomem *falcbase = card->hw.falcbase; | 2227 | void __iomem *falcbase = card->hw.falcbase; |
| 2234 | ucchar isr0, isr3, gis; | 2228 | u8 isr0, isr3, gis; |
| 2235 | ucchar dummy; | 2229 | u8 dummy; |
| 2236 | 2230 | ||
| 2237 | while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) { | 2231 | while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) { |
| 2238 | if (gis & GIS_ISR0) { | 2232 | if (gis & GIS_ISR0) { |
| @@ -2278,8 +2272,8 @@ static void falc_e1_intr(pc300_t * card, int ch) | |||
| 2278 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; | 2272 | pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; |
| 2279 | falc_t *pfalc = (falc_t *) & chan->falc; | 2273 | falc_t *pfalc = (falc_t *) & chan->falc; |
| 2280 | void __iomem *falcbase = card->hw.falcbase; | 2274 | void __iomem *falcbase = card->hw.falcbase; |
| 2281 | ucchar isr1, isr2, isr3, gis, rsp; | 2275 | u8 isr1, isr2, isr3, gis, rsp; |
| 2282 | ucchar dummy; | 2276 | u8 dummy; |
| 2283 | 2277 | ||
| 2284 | while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) { | 2278 | while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) { |
| 2285 | rsp = cpc_readb(falcbase + F_REG(RSP, ch)); | 2279 | rsp = cpc_readb(falcbase + F_REG(RSP, ch)); |
| @@ -2361,7 +2355,7 @@ static void falc_intr(pc300_t * card) | |||
| 2361 | static irqreturn_t cpc_intr(int irq, void *dev_id) | 2355 | static irqreturn_t cpc_intr(int irq, void *dev_id) |
| 2362 | { | 2356 | { |
| 2363 | pc300_t *card = dev_id; | 2357 | pc300_t *card = dev_id; |
| 2364 | volatile ucchar plx_status; | 2358 | volatile u8 plx_status; |
| 2365 | 2359 | ||
| 2366 | if (!card) { | 2360 | if (!card) { |
| 2367 | #ifdef PC300_DEBUG_INTR | 2361 | #ifdef PC300_DEBUG_INTR |
| @@ -2400,7 +2394,7 @@ static irqreturn_t cpc_intr(int irq, void *dev_id) | |||
| 2400 | 2394 | ||
| 2401 | static void cpc_sca_status(pc300_t * card, int ch) | 2395 | static void cpc_sca_status(pc300_t * card, int ch) |
| 2402 | { | 2396 | { |
| 2403 | ucchar ilar; | 2397 | u8 ilar; |
| 2404 | void __iomem *scabase = card->hw.scabase; | 2398 | void __iomem *scabase = card->hw.scabase; |
| 2405 | unsigned long flags; | 2399 | unsigned long flags; |
| 2406 | 2400 | ||
| @@ -2818,7 +2812,7 @@ static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |||
| 2818 | } | 2812 | } |
| 2819 | } | 2813 | } |
| 2820 | 2814 | ||
| 2821 | static int clock_rate_calc(uclong rate, uclong clock, int *br_io) | 2815 | static int clock_rate_calc(u32 rate, u32 clock, int *br_io) |
| 2822 | { | 2816 | { |
| 2823 | int br, tc; | 2817 | int br, tc; |
| 2824 | int br_pwr, error; | 2818 | int br_pwr, error; |
| @@ -2855,12 +2849,12 @@ static int ch_config(pc300dev_t * d) | |||
| 2855 | void __iomem *scabase = card->hw.scabase; | 2849 | void __iomem *scabase = card->hw.scabase; |
| 2856 | void __iomem *plxbase = card->hw.plxbase; | 2850 | void __iomem *plxbase = card->hw.plxbase; |
| 2857 | int ch = chan->channel; | 2851 | int ch = chan->channel; |
| 2858 | uclong clkrate = chan->conf.phys_settings.clock_rate; | 2852 | u32 clkrate = chan->conf.phys_settings.clock_rate; |
| 2859 | uclong clktype = chan->conf.phys_settings.clock_type; | 2853 | u32 clktype = chan->conf.phys_settings.clock_type; |
| 2860 | ucshort encoding = chan->conf.proto_settings.encoding; | 2854 | u16 encoding = chan->conf.proto_settings.encoding; |
| 2861 | ucshort parity = chan->conf.proto_settings.parity; | 2855 | u16 parity = chan->conf.proto_settings.parity; |
| 2862 | ucchar md0, md2; | 2856 | u8 md0, md2; |
| 2863 | 2857 | ||
| 2864 | /* Reset the channel */ | 2858 | /* Reset the channel */ |
| 2865 | cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST); | 2859 | cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST); |
| 2866 | 2860 | ||
| @@ -3152,19 +3146,10 @@ int cpc_open(struct net_device *dev) | |||
| 3152 | printk("pc300: cpc_open"); | 3146 | printk("pc300: cpc_open"); |
| 3153 | #endif | 3147 | #endif |
| 3154 | 3148 | ||
| 3155 | #ifdef FIXME | ||
| 3156 | if (hdlc->proto.id == IF_PROTO_PPP) { | ||
| 3157 | d->if_ptr = &hdlc->state.ppp.pppdev; | ||
| 3158 | } | ||
| 3159 | #endif | ||
| 3160 | |||
| 3161 | result = hdlc_open(dev); | 3149 | result = hdlc_open(dev); |
| 3162 | if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) { | 3150 | |
| 3163 | dev->priv = d; | 3151 | if (result) |
| 3164 | } | ||
| 3165 | if (result) { | ||
| 3166 | return result; | 3152 | return result; |
| 3167 | } | ||
| 3168 | 3153 | ||
| 3169 | sprintf(ifr.ifr_name, "%s", dev->name); | 3154 | sprintf(ifr.ifr_name, "%s", dev->name); |
| 3170 | result = cpc_opench(d); | 3155 | result = cpc_opench(d); |
| @@ -3197,9 +3182,7 @@ static int cpc_close(struct net_device *dev) | |||
| 3197 | CPC_UNLOCK(card, flags); | 3182 | CPC_UNLOCK(card, flags); |
| 3198 | 3183 | ||
| 3199 | hdlc_close(dev); | 3184 | hdlc_close(dev); |
| 3200 | if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) { | 3185 | |
| 3201 | d->if_ptr = NULL; | ||
| 3202 | } | ||
| 3203 | #ifdef CONFIG_PC300_MLPPP | 3186 | #ifdef CONFIG_PC300_MLPPP |
| 3204 | if (chan->conf.proto == PC300_PROTO_MLPPP) { | 3187 | if (chan->conf.proto == PC300_PROTO_MLPPP) { |
| 3205 | cpc_tty_unregister_service(d); | 3188 | cpc_tty_unregister_service(d); |
| @@ -3210,16 +3193,16 @@ static int cpc_close(struct net_device *dev) | |||
| 3210 | return 0; | 3193 | return 0; |
| 3211 | } | 3194 | } |
| 3212 | 3195 | ||
| 3213 | static uclong detect_ram(pc300_t * card) | 3196 | static u32 detect_ram(pc300_t * card) |
| 3214 | { | 3197 | { |
| 3215 | uclong i; | 3198 | u32 i; |
| 3216 | ucchar data; | 3199 | u8 data; |
| 3217 | void __iomem *rambase = card->hw.rambase; | 3200 | void __iomem *rambase = card->hw.rambase; |
| 3218 | 3201 | ||
| 3219 | card->hw.ramsize = PC300_RAMSIZE; | 3202 | card->hw.ramsize = PC300_RAMSIZE; |
| 3220 | /* Let's find out how much RAM is present on this board */ | 3203 | /* Let's find out how much RAM is present on this board */ |
| 3221 | for (i = 0; i < card->hw.ramsize; i++) { | 3204 | for (i = 0; i < card->hw.ramsize; i++) { |
| 3222 | data = (ucchar) (i & 0xff); | 3205 | data = (u8)(i & 0xff); |
| 3223 | cpc_writeb(rambase + i, data); | 3206 | cpc_writeb(rambase + i, data); |
| 3224 | if (cpc_readb(rambase + i) != data) { | 3207 | if (cpc_readb(rambase + i) != data) { |
| 3225 | break; | 3208 | break; |
| @@ -3296,7 +3279,7 @@ static void cpc_init_card(pc300_t * card) | |||
| 3296 | cpc_writeb(card->hw.scabase + DMER, 0x80); | 3279 | cpc_writeb(card->hw.scabase + DMER, 0x80); |
| 3297 | 3280 | ||
| 3298 | if (card->hw.type == PC300_TE) { | 3281 | if (card->hw.type == PC300_TE) { |
| 3299 | ucchar reg1; | 3282 | u8 reg1; |
| 3300 | 3283 | ||
| 3301 | /* Check CPLD version */ | 3284 | /* Check CPLD version */ |
| 3302 | reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1); | 3285 | reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1); |
| @@ -3360,7 +3343,6 @@ static void cpc_init_card(pc300_t * card) | |||
| 3360 | chan->nfree_tx_bd = N_DMA_TX_BUF; | 3343 | chan->nfree_tx_bd = N_DMA_TX_BUF; |
| 3361 | 3344 | ||
| 3362 | d->chan = chan; | 3345 | d->chan = chan; |
| 3363 | d->tx_skb = NULL; | ||
| 3364 | d->trace_on = 0; | 3346 | d->trace_on = 0; |
| 3365 | d->line_on = 0; | 3347 | d->line_on = 0; |
| 3366 | d->line_off = 0; | 3348 | d->line_off = 0; |
| @@ -3431,7 +3413,7 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 3431 | { | 3413 | { |
| 3432 | static int first_time = 1; | 3414 | static int first_time = 1; |
| 3433 | int err, eeprom_outdated = 0; | 3415 | int err, eeprom_outdated = 0; |
| 3434 | ucshort device_id; | 3416 | u16 device_id; |
| 3435 | pc300_t *card; | 3417 | pc300_t *card; |
| 3436 | 3418 | ||
| 3437 | if (first_time) { | 3419 | if (first_time) { |
diff --git a/drivers/net/wan/sealevel.c b/drivers/net/wan/sealevel.c index 44a89df1b8bf..c0235844a4d5 100644 --- a/drivers/net/wan/sealevel.c +++ b/drivers/net/wan/sealevel.c | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * | 8 | * |
| 9 | * (c) Copyright 1999, 2001 Alan Cox | 9 | * (c) Copyright 1999, 2001 Alan Cox |
| 10 | * (c) Copyright 2001 Red Hat Inc. | 10 | * (c) Copyright 2001 Red Hat Inc. |
| 11 | * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl> | ||
| 11 | * | 12 | * |
| 12 | */ | 13 | */ |
| 13 | 14 | ||
| @@ -19,6 +20,7 @@ | |||
| 19 | #include <linux/netdevice.h> | 20 | #include <linux/netdevice.h> |
| 20 | #include <linux/if_arp.h> | 21 | #include <linux/if_arp.h> |
| 21 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/hdlc.h> | ||
| 22 | #include <linux/ioport.h> | 24 | #include <linux/ioport.h> |
| 23 | #include <linux/init.h> | 25 | #include <linux/init.h> |
| 24 | #include <net/arp.h> | 26 | #include <net/arp.h> |
| @@ -27,22 +29,19 @@ | |||
| 27 | #include <asm/io.h> | 29 | #include <asm/io.h> |
| 28 | #include <asm/dma.h> | 30 | #include <asm/dma.h> |
| 29 | #include <asm/byteorder.h> | 31 | #include <asm/byteorder.h> |
| 30 | #include <net/syncppp.h> | ||
| 31 | #include "z85230.h" | 32 | #include "z85230.h" |
| 32 | 33 | ||
| 33 | 34 | ||
| 34 | struct slvl_device | 35 | struct slvl_device |
| 35 | { | 36 | { |
| 36 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | ||
| 37 | struct z8530_channel *chan; | 37 | struct z8530_channel *chan; |
| 38 | struct ppp_device pppdev; | ||
| 39 | int channel; | 38 | int channel; |
| 40 | }; | 39 | }; |
| 41 | 40 | ||
| 42 | 41 | ||
| 43 | struct slvl_board | 42 | struct slvl_board |
| 44 | { | 43 | { |
| 45 | struct slvl_device *dev[2]; | 44 | struct slvl_device dev[2]; |
| 46 | struct z8530_dev board; | 45 | struct z8530_dev board; |
| 47 | int iobase; | 46 | int iobase; |
| 48 | }; | 47 | }; |
| @@ -51,72 +50,69 @@ struct slvl_board | |||
| 51 | * Network driver support routines | 50 | * Network driver support routines |
| 52 | */ | 51 | */ |
| 53 | 52 | ||
| 53 | static inline struct slvl_device* dev_to_chan(struct net_device *dev) | ||
| 54 | { | ||
| 55 | return (struct slvl_device *)dev_to_hdlc(dev)->priv; | ||
| 56 | } | ||
| 57 | |||
| 54 | /* | 58 | /* |
| 55 | * Frame receive. Simple for our card as we do sync ppp and there | 59 | * Frame receive. Simple for our card as we do HDLC and there |
| 56 | * is no funny garbage involved | 60 | * is no funny garbage involved |
| 57 | */ | 61 | */ |
| 58 | 62 | ||
| 59 | static void sealevel_input(struct z8530_channel *c, struct sk_buff *skb) | 63 | static void sealevel_input(struct z8530_channel *c, struct sk_buff *skb) |
| 60 | { | 64 | { |
| 61 | /* Drop the CRC - it's not a good idea to try and negotiate it ;) */ | 65 | /* Drop the CRC - it's not a good idea to try and negotiate it ;) */ |
| 62 | skb_trim(skb, skb->len-2); | 66 | skb_trim(skb, skb->len - 2); |
| 63 | skb->protocol=htons(ETH_P_WAN_PPP); | 67 | skb->protocol = hdlc_type_trans(skb, c->netdevice); |
| 64 | skb_reset_mac_header(skb); | 68 | skb_reset_mac_header(skb); |
| 65 | skb->dev=c->netdevice; | 69 | skb->dev = c->netdevice; |
| 66 | /* | ||
| 67 | * Send it to the PPP layer. We don't have time to process | ||
| 68 | * it right now. | ||
| 69 | */ | ||
| 70 | netif_rx(skb); | 70 | netif_rx(skb); |
| 71 | c->netdevice->last_rx = jiffies; | 71 | c->netdevice->last_rx = jiffies; |
| 72 | } | 72 | } |
| 73 | 73 | ||
| 74 | /* | 74 | /* |
| 75 | * We've been placed in the UP state | 75 | * We've been placed in the UP state |
| 76 | */ | 76 | */ |
| 77 | 77 | ||
| 78 | static int sealevel_open(struct net_device *d) | 78 | static int sealevel_open(struct net_device *d) |
| 79 | { | 79 | { |
| 80 | struct slvl_device *slvl=d->priv; | 80 | struct slvl_device *slvl = dev_to_chan(d); |
| 81 | int err = -1; | 81 | int err = -1; |
| 82 | int unit = slvl->channel; | 82 | int unit = slvl->channel; |
| 83 | 83 | ||
| 84 | /* | 84 | /* |
| 85 | * Link layer up. | 85 | * Link layer up. |
| 86 | */ | 86 | */ |
| 87 | 87 | ||
| 88 | switch(unit) | 88 | switch (unit) |
| 89 | { | 89 | { |
| 90 | case 0: | 90 | case 0: |
| 91 | err=z8530_sync_dma_open(d, slvl->chan); | 91 | err = z8530_sync_dma_open(d, slvl->chan); |
| 92 | break; | 92 | break; |
| 93 | case 1: | 93 | case 1: |
| 94 | err=z8530_sync_open(d, slvl->chan); | 94 | err = z8530_sync_open(d, slvl->chan); |
| 95 | break; | 95 | break; |
| 96 | } | 96 | } |
| 97 | 97 | ||
| 98 | if(err) | 98 | if (err) |
| 99 | return err; | 99 | return err; |
| 100 | /* | 100 | |
| 101 | * Begin PPP | 101 | err = hdlc_open(d); |
| 102 | */ | 102 | if (err) { |
| 103 | err=sppp_open(d); | 103 | switch (unit) { |
| 104 | if(err) | ||
| 105 | { | ||
| 106 | switch(unit) | ||
| 107 | { | ||
| 108 | case 0: | 104 | case 0: |
| 109 | z8530_sync_dma_close(d, slvl->chan); | 105 | z8530_sync_dma_close(d, slvl->chan); |
| 110 | break; | 106 | break; |
| 111 | case 1: | 107 | case 1: |
| 112 | z8530_sync_close(d, slvl->chan); | 108 | z8530_sync_close(d, slvl->chan); |
| 113 | break; | 109 | break; |
| 114 | } | 110 | } |
| 115 | return err; | 111 | return err; |
| 116 | } | 112 | } |
| 117 | 113 | ||
| 118 | slvl->chan->rx_function=sealevel_input; | 114 | slvl->chan->rx_function = sealevel_input; |
| 119 | 115 | ||
| 120 | /* | 116 | /* |
| 121 | * Go go go | 117 | * Go go go |
| 122 | */ | 118 | */ |
| @@ -126,26 +122,19 @@ static int sealevel_open(struct net_device *d) | |||
| 126 | 122 | ||
| 127 | static int sealevel_close(struct net_device *d) | 123 | static int sealevel_close(struct net_device *d) |
| 128 | { | 124 | { |
| 129 | struct slvl_device *slvl=d->priv; | 125 | struct slvl_device *slvl = dev_to_chan(d); |
| 130 | int unit = slvl->channel; | 126 | int unit = slvl->channel; |
| 131 | 127 | ||
| 132 | /* | 128 | /* |
| 133 | * Discard new frames | 129 | * Discard new frames |
| 134 | */ | 130 | */ |
| 135 | |||
| 136 | slvl->chan->rx_function=z8530_null_rx; | ||
| 137 | |||
| 138 | /* | ||
| 139 | * PPP off | ||
| 140 | */ | ||
| 141 | sppp_close(d); | ||
| 142 | /* | ||
| 143 | * Link layer down | ||
| 144 | */ | ||
| 145 | 131 | ||
| 132 | slvl->chan->rx_function = z8530_null_rx; | ||
| 133 | |||
| 134 | hdlc_close(d); | ||
| 146 | netif_stop_queue(d); | 135 | netif_stop_queue(d); |
| 147 | 136 | ||
| 148 | switch(unit) | 137 | switch (unit) |
| 149 | { | 138 | { |
| 150 | case 0: | 139 | case 0: |
| 151 | z8530_sync_dma_close(d, slvl->chan); | 140 | z8530_sync_dma_close(d, slvl->chan); |
| @@ -159,210 +148,153 @@ static int sealevel_close(struct net_device *d) | |||
| 159 | 148 | ||
| 160 | static int sealevel_ioctl(struct net_device *d, struct ifreq *ifr, int cmd) | 149 | static int sealevel_ioctl(struct net_device *d, struct ifreq *ifr, int cmd) |
| 161 | { | 150 | { |
| 162 | /* struct slvl_device *slvl=d->priv; | 151 | /* struct slvl_device *slvl=dev_to_chan(d); |
| 163 | z8530_ioctl(d,&slvl->sync.chanA,ifr,cmd) */ | 152 | z8530_ioctl(d,&slvl->sync.chanA,ifr,cmd) */ |
| 164 | return sppp_do_ioctl(d, ifr,cmd); | 153 | return hdlc_ioctl(d, ifr, cmd); |
| 165 | } | ||
| 166 | |||
| 167 | static struct net_device_stats *sealevel_get_stats(struct net_device *d) | ||
| 168 | { | ||
| 169 | struct slvl_device *slvl=d->priv; | ||
| 170 | if(slvl) | ||
| 171 | return z8530_get_stats(slvl->chan); | ||
| 172 | else | ||
| 173 | return NULL; | ||
| 174 | } | 154 | } |
| 175 | 155 | ||
| 176 | /* | 156 | /* |
| 177 | * Passed PPP frames, fire them downwind. | 157 | * Passed network frames, fire them downwind. |
| 178 | */ | 158 | */ |
| 179 | 159 | ||
| 180 | static int sealevel_queue_xmit(struct sk_buff *skb, struct net_device *d) | 160 | static int sealevel_queue_xmit(struct sk_buff *skb, struct net_device *d) |
| 181 | { | 161 | { |
| 182 | struct slvl_device *slvl=d->priv; | 162 | return z8530_queue_xmit(dev_to_chan(d)->chan, skb); |
| 183 | return z8530_queue_xmit(slvl->chan, skb); | ||
| 184 | } | 163 | } |
| 185 | 164 | ||
| 186 | static int sealevel_neigh_setup(struct neighbour *n) | 165 | static int sealevel_attach(struct net_device *dev, unsigned short encoding, |
| 166 | unsigned short parity) | ||
| 187 | { | 167 | { |
| 188 | if (n->nud_state == NUD_NONE) { | 168 | if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT) |
| 189 | n->ops = &arp_broken_ops; | 169 | return 0; |
| 190 | n->output = n->ops->output; | 170 | return -EINVAL; |
| 191 | } | ||
| 192 | return 0; | ||
| 193 | } | 171 | } |
| 194 | 172 | ||
| 195 | static int sealevel_neigh_setup_dev(struct net_device *dev, struct neigh_parms *p) | 173 | static int slvl_setup(struct slvl_device *sv, int iobase, int irq) |
| 196 | { | 174 | { |
| 197 | if (p->tbl->family == AF_INET) { | 175 | struct net_device *dev = alloc_hdlcdev(sv); |
| 198 | p->neigh_setup = sealevel_neigh_setup; | 176 | if (!dev) |
| 199 | p->ucast_probes = 0; | 177 | return -1; |
| 200 | p->mcast_probes = 0; | 178 | |
| 179 | dev_to_hdlc(dev)->attach = sealevel_attach; | ||
| 180 | dev_to_hdlc(dev)->xmit = sealevel_queue_xmit; | ||
| 181 | dev->open = sealevel_open; | ||
| 182 | dev->stop = sealevel_close; | ||
| 183 | dev->do_ioctl = sealevel_ioctl; | ||
| 184 | dev->base_addr = iobase; | ||
| 185 | dev->irq = irq; | ||
| 186 | |||
| 187 | if (register_hdlc_device(dev)) { | ||
| 188 | printk(KERN_ERR "sealevel: unable to register HDLC device\n"); | ||
| 189 | free_netdev(dev); | ||
| 190 | return -1; | ||
| 201 | } | 191 | } |
| 202 | return 0; | ||
| 203 | } | ||
| 204 | 192 | ||
| 205 | static int sealevel_attach(struct net_device *dev) | 193 | sv->chan->netdevice = dev; |
| 206 | { | ||
| 207 | struct slvl_device *sv = dev->priv; | ||
| 208 | sppp_attach(&sv->pppdev); | ||
| 209 | return 0; | 194 | return 0; |
| 210 | } | 195 | } |
| 211 | 196 | ||
| 212 | static void sealevel_detach(struct net_device *dev) | ||
| 213 | { | ||
| 214 | sppp_detach(dev); | ||
| 215 | } | ||
| 216 | |||
| 217 | static void slvl_setup(struct net_device *d) | ||
| 218 | { | ||
| 219 | d->open = sealevel_open; | ||
| 220 | d->stop = sealevel_close; | ||
| 221 | d->init = sealevel_attach; | ||
| 222 | d->uninit = sealevel_detach; | ||
| 223 | d->hard_start_xmit = sealevel_queue_xmit; | ||
| 224 | d->get_stats = sealevel_get_stats; | ||
| 225 | d->set_multicast_list = NULL; | ||
| 226 | d->do_ioctl = sealevel_ioctl; | ||
| 227 | d->neigh_setup = sealevel_neigh_setup_dev; | ||
| 228 | d->set_mac_address = NULL; | ||
| 229 | |||
| 230 | } | ||
| 231 | |||
| 232 | static inline struct slvl_device *slvl_alloc(int iobase, int irq) | ||
| 233 | { | ||
| 234 | struct net_device *d; | ||
| 235 | struct slvl_device *sv; | ||
| 236 | |||
| 237 | d = alloc_netdev(sizeof(struct slvl_device), "hdlc%d", | ||
| 238 | slvl_setup); | ||
| 239 | |||
| 240 | if (!d) | ||
| 241 | return NULL; | ||
| 242 | |||
| 243 | sv = d->priv; | ||
| 244 | d->ml_priv = sv; | ||
| 245 | sv->if_ptr = &sv->pppdev; | ||
| 246 | sv->pppdev.dev = d; | ||
| 247 | d->base_addr = iobase; | ||
| 248 | d->irq = irq; | ||
| 249 | |||
| 250 | return sv; | ||
| 251 | } | ||
| 252 | |||
| 253 | 197 | ||
| 254 | /* | 198 | /* |
| 255 | * Allocate and setup Sealevel board. | 199 | * Allocate and setup Sealevel board. |
| 256 | */ | 200 | */ |
| 257 | 201 | ||
| 258 | static __init struct slvl_board *slvl_init(int iobase, int irq, | 202 | static __init struct slvl_board *slvl_init(int iobase, int irq, |
| 259 | int txdma, int rxdma, int slow) | 203 | int txdma, int rxdma, int slow) |
| 260 | { | 204 | { |
| 261 | struct z8530_dev *dev; | 205 | struct z8530_dev *dev; |
| 262 | struct slvl_board *b; | 206 | struct slvl_board *b; |
| 263 | 207 | ||
| 264 | /* | 208 | /* |
| 265 | * Get the needed I/O space | 209 | * Get the needed I/O space |
| 266 | */ | 210 | */ |
| 267 | 211 | ||
| 268 | if(!request_region(iobase, 8, "Sealevel 4021")) | 212 | if (!request_region(iobase, 8, "Sealevel 4021")) { |
| 269 | { | 213 | printk(KERN_WARNING "sealevel: I/O 0x%X already in use.\n", |
| 270 | printk(KERN_WARNING "sealevel: I/O 0x%X already in use.\n", iobase); | 214 | iobase); |
| 271 | return NULL; | 215 | return NULL; |
| 272 | } | 216 | } |
| 273 | |||
| 274 | b = kzalloc(sizeof(struct slvl_board), GFP_KERNEL); | ||
| 275 | if(!b) | ||
| 276 | goto fail3; | ||
| 277 | 217 | ||
| 278 | if (!(b->dev[0]= slvl_alloc(iobase, irq))) | 218 | b = kzalloc(sizeof(struct slvl_board), GFP_KERNEL); |
| 279 | goto fail2; | 219 | if (!b) |
| 220 | goto err_kzalloc; | ||
| 280 | 221 | ||
| 281 | b->dev[0]->chan = &b->board.chanA; | 222 | b->dev[0].chan = &b->board.chanA; |
| 282 | b->dev[0]->channel = 0; | 223 | b->dev[0].channel = 0; |
| 283 | |||
| 284 | if (!(b->dev[1] = slvl_alloc(iobase, irq))) | ||
| 285 | goto fail1_0; | ||
| 286 | 224 | ||
| 287 | b->dev[1]->chan = &b->board.chanB; | 225 | b->dev[1].chan = &b->board.chanB; |
| 288 | b->dev[1]->channel = 1; | 226 | b->dev[1].channel = 1; |
| 289 | 227 | ||
| 290 | dev = &b->board; | 228 | dev = &b->board; |
| 291 | 229 | ||
| 292 | /* | 230 | /* |
| 293 | * Stuff in the I/O addressing | 231 | * Stuff in the I/O addressing |
| 294 | */ | 232 | */ |
| 295 | 233 | ||
| 296 | dev->active = 0; | 234 | dev->active = 0; |
| 297 | 235 | ||
| 298 | b->iobase = iobase; | 236 | b->iobase = iobase; |
| 299 | 237 | ||
| 300 | /* | 238 | /* |
| 301 | * Select 8530 delays for the old board | 239 | * Select 8530 delays for the old board |
| 302 | */ | 240 | */ |
| 303 | 241 | ||
| 304 | if(slow) | 242 | if (slow) |
| 305 | iobase |= Z8530_PORT_SLEEP; | 243 | iobase |= Z8530_PORT_SLEEP; |
| 306 | 244 | ||
| 307 | dev->chanA.ctrlio=iobase+1; | 245 | dev->chanA.ctrlio = iobase + 1; |
| 308 | dev->chanA.dataio=iobase; | 246 | dev->chanA.dataio = iobase; |
| 309 | dev->chanB.ctrlio=iobase+3; | 247 | dev->chanB.ctrlio = iobase + 3; |
| 310 | dev->chanB.dataio=iobase+2; | 248 | dev->chanB.dataio = iobase + 2; |
| 311 | 249 | ||
| 312 | dev->chanA.irqs=&z8530_nop; | 250 | dev->chanA.irqs = &z8530_nop; |
| 313 | dev->chanB.irqs=&z8530_nop; | 251 | dev->chanB.irqs = &z8530_nop; |
| 314 | 252 | ||
| 315 | /* | 253 | /* |
| 316 | * Assert DTR enable DMA | 254 | * Assert DTR enable DMA |
| 317 | */ | 255 | */ |
| 318 | 256 | ||
| 319 | outb(3|(1<<7), b->iobase+4); | 257 | outb(3 | (1 << 7), b->iobase + 4); |
| 320 | 258 | ||
| 321 | 259 | ||
| 322 | /* We want a fast IRQ for this device. Actually we'd like an even faster | 260 | /* We want a fast IRQ for this device. Actually we'd like an even faster |
| 323 | IRQ ;) - This is one driver RtLinux is made for */ | 261 | IRQ ;) - This is one driver RtLinux is made for */ |
| 324 | 262 | ||
| 325 | if(request_irq(irq, &z8530_interrupt, IRQF_DISABLED, "SeaLevel", dev)<0) | 263 | if (request_irq(irq, &z8530_interrupt, IRQF_DISABLED, |
| 326 | { | 264 | "SeaLevel", dev) < 0) { |
| 327 | printk(KERN_WARNING "sealevel: IRQ %d already in use.\n", irq); | 265 | printk(KERN_WARNING "sealevel: IRQ %d already in use.\n", irq); |
| 328 | goto fail1_1; | 266 | goto err_request_irq; |
| 329 | } | 267 | } |
| 330 | 268 | ||
| 331 | dev->irq=irq; | 269 | dev->irq = irq; |
| 332 | dev->chanA.private=&b->dev[0]; | 270 | dev->chanA.private = &b->dev[0]; |
| 333 | dev->chanB.private=&b->dev[1]; | 271 | dev->chanB.private = &b->dev[1]; |
| 334 | dev->chanA.netdevice=b->dev[0]->pppdev.dev; | 272 | dev->chanA.dev = dev; |
| 335 | dev->chanB.netdevice=b->dev[1]->pppdev.dev; | 273 | dev->chanB.dev = dev; |
| 336 | dev->chanA.dev=dev; | 274 | |
| 337 | dev->chanB.dev=dev; | 275 | dev->chanA.txdma = 3; |
| 338 | 276 | dev->chanA.rxdma = 1; | |
| 339 | dev->chanA.txdma=3; | 277 | if (request_dma(dev->chanA.txdma, "SeaLevel (TX)")) |
| 340 | dev->chanA.rxdma=1; | 278 | goto err_dma_tx; |
| 341 | if(request_dma(dev->chanA.txdma, "SeaLevel (TX)")!=0) | 279 | |
| 342 | goto fail; | 280 | if (request_dma(dev->chanA.rxdma, "SeaLevel (RX)")) |
| 343 | 281 | goto err_dma_rx; | |
| 344 | if(request_dma(dev->chanA.rxdma, "SeaLevel (RX)")!=0) | 282 | |
| 345 | goto dmafail; | ||
| 346 | |||
| 347 | disable_irq(irq); | 283 | disable_irq(irq); |
| 348 | 284 | ||
| 349 | /* | 285 | /* |
| 350 | * Begin normal initialise | 286 | * Begin normal initialise |
| 351 | */ | 287 | */ |
| 352 | 288 | ||
| 353 | if(z8530_init(dev)!=0) | 289 | if (z8530_init(dev) != 0) { |
| 354 | { | ||
| 355 | printk(KERN_ERR "Z8530 series device not found.\n"); | 290 | printk(KERN_ERR "Z8530 series device not found.\n"); |
| 356 | enable_irq(irq); | 291 | enable_irq(irq); |
| 357 | goto dmafail2; | 292 | goto free_hw; |
| 358 | } | 293 | } |
| 359 | if(dev->type==Z85C30) | 294 | if (dev->type == Z85C30) { |
| 360 | { | ||
| 361 | z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream); | 295 | z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream); |
| 362 | z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream); | 296 | z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream); |
| 363 | } | 297 | } else { |
| 364 | else | ||
| 365 | { | ||
| 366 | z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream_85230); | 298 | z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream_85230); |
| 367 | z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream_85230); | 299 | z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream_85230); |
| 368 | } | 300 | } |
| @@ -370,36 +302,31 @@ static __init struct slvl_board *slvl_init(int iobase, int irq, | |||
| 370 | /* | 302 | /* |
| 371 | * Now we can take the IRQ | 303 | * Now we can take the IRQ |
| 372 | */ | 304 | */ |
| 373 | 305 | ||
| 374 | enable_irq(irq); | 306 | enable_irq(irq); |
| 375 | 307 | ||
| 376 | if (register_netdev(b->dev[0]->pppdev.dev)) | 308 | if (slvl_setup(&b->dev[0], iobase, irq)) |
| 377 | goto dmafail2; | 309 | goto free_hw; |
| 378 | 310 | if (slvl_setup(&b->dev[1], iobase, irq)) | |
| 379 | if (register_netdev(b->dev[1]->pppdev.dev)) | 311 | goto free_netdev0; |
| 380 | goto fail_unit; | ||
| 381 | 312 | ||
| 382 | z8530_describe(dev, "I/O", iobase); | 313 | z8530_describe(dev, "I/O", iobase); |
| 383 | dev->active=1; | 314 | dev->active = 1; |
| 384 | return b; | 315 | return b; |
| 385 | 316 | ||
| 386 | fail_unit: | 317 | free_netdev0: |
| 387 | unregister_netdev(b->dev[0]->pppdev.dev); | 318 | unregister_hdlc_device(b->dev[0].chan->netdevice); |
| 388 | 319 | free_netdev(b->dev[0].chan->netdevice); | |
| 389 | dmafail2: | 320 | free_hw: |
| 390 | free_dma(dev->chanA.rxdma); | 321 | free_dma(dev->chanA.rxdma); |
| 391 | dmafail: | 322 | err_dma_rx: |
| 392 | free_dma(dev->chanA.txdma); | 323 | free_dma(dev->chanA.txdma); |
| 393 | fail: | 324 | err_dma_tx: |
| 394 | free_irq(irq, dev); | 325 | free_irq(irq, dev); |
| 395 | fail1_1: | 326 | err_request_irq: |
| 396 | free_netdev(b->dev[1]->pppdev.dev); | ||
| 397 | fail1_0: | ||
| 398 | free_netdev(b->dev[0]->pppdev.dev); | ||
| 399 | fail2: | ||
| 400 | kfree(b); | 327 | kfree(b); |
| 401 | fail3: | 328 | err_kzalloc: |
| 402 | release_region(iobase,8); | 329 | release_region(iobase, 8); |
| 403 | return NULL; | 330 | return NULL; |
| 404 | } | 331 | } |
| 405 | 332 | ||
| @@ -408,14 +335,14 @@ static void __exit slvl_shutdown(struct slvl_board *b) | |||
| 408 | int u; | 335 | int u; |
| 409 | 336 | ||
| 410 | z8530_shutdown(&b->board); | 337 | z8530_shutdown(&b->board); |
| 411 | 338 | ||
| 412 | for(u=0; u<2; u++) | 339 | for (u = 0; u < 2; u++) |
| 413 | { | 340 | { |
| 414 | struct net_device *d = b->dev[u]->pppdev.dev; | 341 | struct net_device *d = b->dev[u].chan->netdevice; |
| 415 | unregister_netdev(d); | 342 | unregister_hdlc_device(d); |
| 416 | free_netdev(d); | 343 | free_netdev(d); |
| 417 | } | 344 | } |
| 418 | 345 | ||
| 419 | free_irq(b->board.irq, &b->board); | 346 | free_irq(b->board.irq, &b->board); |
| 420 | free_dma(b->board.chanA.rxdma); | 347 | free_dma(b->board.chanA.rxdma); |
| 421 | free_dma(b->board.chanA.txdma); | 348 | free_dma(b->board.chanA.txdma); |
| @@ -451,10 +378,6 @@ static struct slvl_board *slvl_unit; | |||
| 451 | 378 | ||
| 452 | static int __init slvl_init_module(void) | 379 | static int __init slvl_init_module(void) |
| 453 | { | 380 | { |
| 454 | #ifdef MODULE | ||
| 455 | printk(KERN_INFO "SeaLevel Z85230 Synchronous Driver v 0.02.\n"); | ||
| 456 | printk(KERN_INFO "(c) Copyright 1998, Building Number Three Ltd.\n"); | ||
| 457 | #endif | ||
| 458 | slvl_unit = slvl_init(io, irq, txdma, rxdma, slow); | 381 | slvl_unit = slvl_init(io, irq, txdma, rxdma, slow); |
| 459 | 382 | ||
| 460 | return slvl_unit ? 0 : -ENODEV; | 383 | return slvl_unit ? 0 : -ENODEV; |
diff --git a/drivers/net/wan/syncppp.c b/drivers/net/wan/syncppp.c index 29b4b94e4947..327d58589e12 100644 --- a/drivers/net/wan/syncppp.c +++ b/drivers/net/wan/syncppp.c | |||
| @@ -230,13 +230,6 @@ static void sppp_input (struct net_device *dev, struct sk_buff *skb) | |||
| 230 | skb->dev=dev; | 230 | skb->dev=dev; |
| 231 | skb_reset_mac_header(skb); | 231 | skb_reset_mac_header(skb); |
| 232 | 232 | ||
| 233 | if (dev->flags & IFF_RUNNING) | ||
| 234 | { | ||
| 235 | /* Count received bytes, add FCS and one flag */ | ||
| 236 | sp->ibytes+= skb->len + 3; | ||
| 237 | sp->ipkts++; | ||
| 238 | } | ||
| 239 | |||
| 240 | if (!pskb_may_pull(skb, PPP_HEADER_LEN)) { | 233 | if (!pskb_may_pull(skb, PPP_HEADER_LEN)) { |
| 241 | /* Too small packet, drop it. */ | 234 | /* Too small packet, drop it. */ |
| 242 | if (sp->pp_flags & PP_DEBUG) | 235 | if (sp->pp_flags & PP_DEBUG) |
| @@ -832,7 +825,6 @@ static void sppp_cp_send (struct sppp *sp, u16 proto, u8 type, | |||
| 832 | sppp_print_bytes ((u8*) (lh+1), len); | 825 | sppp_print_bytes ((u8*) (lh+1), len); |
| 833 | printk (">\n"); | 826 | printk (">\n"); |
| 834 | } | 827 | } |
| 835 | sp->obytes += skb->len; | ||
| 836 | /* Control is high priority so it doesn't get queued behind data */ | 828 | /* Control is high priority so it doesn't get queued behind data */ |
| 837 | skb->priority=TC_PRIO_CONTROL; | 829 | skb->priority=TC_PRIO_CONTROL; |
| 838 | skb->dev = dev; | 830 | skb->dev = dev; |
| @@ -875,7 +867,6 @@ static void sppp_cisco_send (struct sppp *sp, int type, u32 par1, u32 par2) | |||
| 875 | printk (KERN_WARNING "%s: cisco output: <%xh %xh %xh %xh %xh-%xh>\n", | 867 | printk (KERN_WARNING "%s: cisco output: <%xh %xh %xh %xh %xh-%xh>\n", |
| 876 | dev->name, ntohl (ch->type), ch->par1, | 868 | dev->name, ntohl (ch->type), ch->par1, |
| 877 | ch->par2, ch->rel, ch->time0, ch->time1); | 869 | ch->par2, ch->rel, ch->time0, ch->time1); |
| 878 | sp->obytes += skb->len; | ||
| 879 | skb->priority=TC_PRIO_CONTROL; | 870 | skb->priority=TC_PRIO_CONTROL; |
| 880 | skb->dev = dev; | 871 | skb->dev = dev; |
| 881 | skb_queue_tail(&tx_queue, skb); | 872 | skb_queue_tail(&tx_queue, skb); |
diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 98ef400908b8..243bd8d918fe 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #include <linux/netdevice.h> | 43 | #include <linux/netdevice.h> |
| 44 | #include <linux/if_arp.h> | 44 | #include <linux/if_arp.h> |
| 45 | #include <linux/delay.h> | 45 | #include <linux/delay.h> |
| 46 | #include <linux/hdlc.h> | ||
| 46 | #include <linux/ioport.h> | 47 | #include <linux/ioport.h> |
| 47 | #include <linux/init.h> | 48 | #include <linux/init.h> |
| 48 | #include <asm/dma.h> | 49 | #include <asm/dma.h> |
| @@ -51,7 +52,6 @@ | |||
| 51 | #define RT_UNLOCK | 52 | #define RT_UNLOCK |
| 52 | #include <linux/spinlock.h> | 53 | #include <linux/spinlock.h> |
| 53 | 54 | ||
| 54 | #include <net/syncppp.h> | ||
| 55 | #include "z85230.h" | 55 | #include "z85230.h" |
| 56 | 56 | ||
| 57 | 57 | ||
| @@ -440,51 +440,46 @@ static void z8530_tx(struct z8530_channel *c) | |||
| 440 | * A status event occurred in PIO synchronous mode. There are several | 440 | * A status event occurred in PIO synchronous mode. There are several |
| 441 | * reasons the chip will bother us here. A transmit underrun means we | 441 | * reasons the chip will bother us here. A transmit underrun means we |
| 442 | * failed to feed the chip fast enough and just broke a packet. A DCD | 442 | * failed to feed the chip fast enough and just broke a packet. A DCD |
| 443 | * change is a line up or down. We communicate that back to the protocol | 443 | * change is a line up or down. |
| 444 | * layer for synchronous PPP to renegotiate. | ||
| 445 | */ | 444 | */ |
| 446 | 445 | ||
| 447 | static void z8530_status(struct z8530_channel *chan) | 446 | static void z8530_status(struct z8530_channel *chan) |
| 448 | { | 447 | { |
| 449 | u8 status, altered; | 448 | u8 status, altered; |
| 450 | 449 | ||
| 451 | status=read_zsreg(chan, R0); | 450 | status = read_zsreg(chan, R0); |
| 452 | altered=chan->status^status; | 451 | altered = chan->status ^ status; |
| 453 | 452 | ||
| 454 | chan->status=status; | 453 | chan->status = status; |
| 455 | 454 | ||
| 456 | if(status&TxEOM) | 455 | if (status & TxEOM) { |
| 457 | { | ||
| 458 | /* printk("%s: Tx underrun.\n", chan->dev->name); */ | 456 | /* printk("%s: Tx underrun.\n", chan->dev->name); */ |
| 459 | chan->stats.tx_fifo_errors++; | 457 | chan->netdevice->stats.tx_fifo_errors++; |
| 460 | write_zsctrl(chan, ERR_RES); | 458 | write_zsctrl(chan, ERR_RES); |
| 461 | z8530_tx_done(chan); | 459 | z8530_tx_done(chan); |
| 462 | } | 460 | } |
| 463 | 461 | ||
| 464 | if(altered&chan->dcdcheck) | 462 | if (altered & chan->dcdcheck) |
| 465 | { | 463 | { |
| 466 | if(status&chan->dcdcheck) | 464 | if (status & chan->dcdcheck) { |
| 467 | { | ||
| 468 | printk(KERN_INFO "%s: DCD raised\n", chan->dev->name); | 465 | printk(KERN_INFO "%s: DCD raised\n", chan->dev->name); |
| 469 | write_zsreg(chan, R3, chan->regs[3]|RxENABLE); | 466 | write_zsreg(chan, R3, chan->regs[3] | RxENABLE); |
| 470 | if(chan->netdevice && | 467 | if (chan->netdevice) |
| 471 | ((chan->netdevice->type == ARPHRD_HDLC) || | 468 | netif_carrier_on(chan->netdevice); |
| 472 | (chan->netdevice->type == ARPHRD_PPP))) | 469 | } else { |
| 473 | sppp_reopen(chan->netdevice); | ||
| 474 | } | ||
| 475 | else | ||
| 476 | { | ||
| 477 | printk(KERN_INFO "%s: DCD lost\n", chan->dev->name); | 470 | printk(KERN_INFO "%s: DCD lost\n", chan->dev->name); |
| 478 | write_zsreg(chan, R3, chan->regs[3]&~RxENABLE); | 471 | write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE); |
| 479 | z8530_flush_fifo(chan); | 472 | z8530_flush_fifo(chan); |
| 473 | if (chan->netdevice) | ||
| 474 | netif_carrier_off(chan->netdevice); | ||
| 480 | } | 475 | } |
| 481 | 476 | ||
| 482 | } | 477 | } |
| 483 | write_zsctrl(chan, RES_EXT_INT); | 478 | write_zsctrl(chan, RES_EXT_INT); |
| 484 | write_zsctrl(chan, RES_H_IUS); | 479 | write_zsctrl(chan, RES_H_IUS); |
| 485 | } | 480 | } |
| 486 | 481 | ||
| 487 | struct z8530_irqhandler z8530_sync= | 482 | struct z8530_irqhandler z8530_sync = |
| 488 | { | 483 | { |
| 489 | z8530_rx, | 484 | z8530_rx, |
| 490 | z8530_tx, | 485 | z8530_tx, |
| @@ -556,8 +551,7 @@ static void z8530_dma_tx(struct z8530_channel *chan) | |||
| 556 | * | 551 | * |
| 557 | * A status event occurred on the Z8530. We receive these for two reasons | 552 | * A status event occurred on the Z8530. We receive these for two reasons |
| 558 | * when in DMA mode. Firstly if we finished a packet transfer we get one | 553 | * when in DMA mode. Firstly if we finished a packet transfer we get one |
| 559 | * and kick the next packet out. Secondly we may see a DCD change and | 554 | * and kick the next packet out. Secondly we may see a DCD change. |
| 560 | * have to poke the protocol layer. | ||
| 561 | * | 555 | * |
| 562 | */ | 556 | */ |
| 563 | 557 | ||
| @@ -586,24 +580,21 @@ static void z8530_dma_status(struct z8530_channel *chan) | |||
| 586 | } | 580 | } |
| 587 | } | 581 | } |
| 588 | 582 | ||
| 589 | if(altered&chan->dcdcheck) | 583 | if (altered & chan->dcdcheck) |
| 590 | { | 584 | { |
| 591 | if(status&chan->dcdcheck) | 585 | if (status & chan->dcdcheck) { |
| 592 | { | ||
| 593 | printk(KERN_INFO "%s: DCD raised\n", chan->dev->name); | 586 | printk(KERN_INFO "%s: DCD raised\n", chan->dev->name); |
| 594 | write_zsreg(chan, R3, chan->regs[3]|RxENABLE); | 587 | write_zsreg(chan, R3, chan->regs[3] | RxENABLE); |
| 595 | if(chan->netdevice && | 588 | if (chan->netdevice) |
| 596 | ((chan->netdevice->type == ARPHRD_HDLC) || | 589 | netif_carrier_on(chan->netdevice); |
| 597 | (chan->netdevice->type == ARPHRD_PPP))) | 590 | } else { |
| 598 | sppp_reopen(chan->netdevice); | ||
| 599 | } | ||
| 600 | else | ||
| 601 | { | ||
| 602 | printk(KERN_INFO "%s:DCD lost\n", chan->dev->name); | 591 | printk(KERN_INFO "%s:DCD lost\n", chan->dev->name); |
| 603 | write_zsreg(chan, R3, chan->regs[3]&~RxENABLE); | 592 | write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE); |
| 604 | z8530_flush_fifo(chan); | 593 | z8530_flush_fifo(chan); |
| 594 | if (chan->netdevice) | ||
| 595 | netif_carrier_off(chan->netdevice); | ||
| 605 | } | 596 | } |
| 606 | } | 597 | } |
| 607 | 598 | ||
| 608 | write_zsctrl(chan, RES_EXT_INT); | 599 | write_zsctrl(chan, RES_EXT_INT); |
| 609 | write_zsctrl(chan, RES_H_IUS); | 600 | write_zsctrl(chan, RES_H_IUS); |
| @@ -1459,10 +1450,10 @@ static void z8530_tx_begin(struct z8530_channel *c) | |||
| 1459 | /* | 1450 | /* |
| 1460 | * Check if we crapped out. | 1451 | * Check if we crapped out. |
| 1461 | */ | 1452 | */ |
| 1462 | if(get_dma_residue(c->txdma)) | 1453 | if (get_dma_residue(c->txdma)) |
| 1463 | { | 1454 | { |
| 1464 | c->stats.tx_dropped++; | 1455 | c->netdevice->stats.tx_dropped++; |
| 1465 | c->stats.tx_fifo_errors++; | 1456 | c->netdevice->stats.tx_fifo_errors++; |
| 1466 | } | 1457 | } |
| 1467 | release_dma_lock(flags); | 1458 | release_dma_lock(flags); |
| 1468 | } | 1459 | } |
| @@ -1534,21 +1525,21 @@ static void z8530_tx_begin(struct z8530_channel *c) | |||
| 1534 | * packet. This code is fairly timing sensitive. | 1525 | * packet. This code is fairly timing sensitive. |
| 1535 | * | 1526 | * |
| 1536 | * Called with the register lock held. | 1527 | * Called with the register lock held. |
| 1537 | */ | 1528 | */ |
| 1538 | 1529 | ||
| 1539 | static void z8530_tx_done(struct z8530_channel *c) | 1530 | static void z8530_tx_done(struct z8530_channel *c) |
| 1540 | { | 1531 | { |
| 1541 | struct sk_buff *skb; | 1532 | struct sk_buff *skb; |
| 1542 | 1533 | ||
| 1543 | /* Actually this can happen.*/ | 1534 | /* Actually this can happen.*/ |
| 1544 | if(c->tx_skb==NULL) | 1535 | if (c->tx_skb == NULL) |
| 1545 | return; | 1536 | return; |
| 1546 | 1537 | ||
| 1547 | skb=c->tx_skb; | 1538 | skb = c->tx_skb; |
| 1548 | c->tx_skb=NULL; | 1539 | c->tx_skb = NULL; |
| 1549 | z8530_tx_begin(c); | 1540 | z8530_tx_begin(c); |
| 1550 | c->stats.tx_packets++; | 1541 | c->netdevice->stats.tx_packets++; |
| 1551 | c->stats.tx_bytes+=skb->len; | 1542 | c->netdevice->stats.tx_bytes += skb->len; |
| 1552 | dev_kfree_skb_irq(skb); | 1543 | dev_kfree_skb_irq(skb); |
| 1553 | } | 1544 | } |
| 1554 | 1545 | ||
| @@ -1558,7 +1549,7 @@ static void z8530_tx_done(struct z8530_channel *c) | |||
| 1558 | * @skb: The buffer | 1549 | * @skb: The buffer |
| 1559 | * | 1550 | * |
| 1560 | * We point the receive handler at this function when idle. Instead | 1551 | * We point the receive handler at this function when idle. Instead |
| 1561 | * of syncppp processing the frames we get to throw them away. | 1552 | * of processing the frames we get to throw them away. |
| 1562 | */ | 1553 | */ |
| 1563 | 1554 | ||
| 1564 | void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb) | 1555 | void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb) |
| @@ -1635,10 +1626,11 @@ static void z8530_rx_done(struct z8530_channel *c) | |||
| 1635 | else | 1626 | else |
| 1636 | /* Can't occur as we dont reenable the DMA irq until | 1627 | /* Can't occur as we dont reenable the DMA irq until |
| 1637 | after the flip is done */ | 1628 | after the flip is done */ |
| 1638 | printk(KERN_WARNING "%s: DMA flip overrun!\n", c->netdevice->name); | 1629 | printk(KERN_WARNING "%s: DMA flip overrun!\n", |
| 1639 | 1630 | c->netdevice->name); | |
| 1631 | |||
| 1640 | release_dma_lock(flags); | 1632 | release_dma_lock(flags); |
| 1641 | 1633 | ||
| 1642 | /* | 1634 | /* |
| 1643 | * Shove the old buffer into an sk_buff. We can't DMA | 1635 | * Shove the old buffer into an sk_buff. We can't DMA |
| 1644 | * directly into one on a PC - it might be above the 16Mb | 1636 | * directly into one on a PC - it might be above the 16Mb |
| @@ -1646,27 +1638,23 @@ static void z8530_rx_done(struct z8530_channel *c) | |||
| 1646 | * can avoid the copy. Optimisation 2 - make the memcpy | 1638 | * can avoid the copy. Optimisation 2 - make the memcpy |
| 1647 | * a copychecksum. | 1639 | * a copychecksum. |
| 1648 | */ | 1640 | */ |
| 1649 | 1641 | ||
| 1650 | skb=dev_alloc_skb(ct); | 1642 | skb = dev_alloc_skb(ct); |
| 1651 | if(skb==NULL) | 1643 | if (skb == NULL) { |
| 1652 | { | 1644 | c->netdevice->stats.rx_dropped++; |
| 1653 | c->stats.rx_dropped++; | 1645 | printk(KERN_WARNING "%s: Memory squeeze.\n", |
| 1654 | printk(KERN_WARNING "%s: Memory squeeze.\n", c->netdevice->name); | 1646 | c->netdevice->name); |
| 1655 | } | 1647 | } else { |
| 1656 | else | ||
| 1657 | { | ||
| 1658 | skb_put(skb, ct); | 1648 | skb_put(skb, ct); |
| 1659 | skb_copy_to_linear_data(skb, rxb, ct); | 1649 | skb_copy_to_linear_data(skb, rxb, ct); |
| 1660 | c->stats.rx_packets++; | 1650 | c->netdevice->stats.rx_packets++; |
| 1661 | c->stats.rx_bytes+=ct; | 1651 | c->netdevice->stats.rx_bytes += ct; |
| 1662 | } | 1652 | } |
| 1663 | c->dma_ready=1; | 1653 | c->dma_ready = 1; |
| 1664 | } | 1654 | } else { |
| 1665 | else | 1655 | RT_LOCK; |
| 1666 | { | 1656 | skb = c->skb; |
| 1667 | RT_LOCK; | 1657 | |
| 1668 | skb=c->skb; | ||
| 1669 | |||
| 1670 | /* | 1658 | /* |
| 1671 | * The game we play for non DMA is similar. We want to | 1659 | * The game we play for non DMA is similar. We want to |
| 1672 | * get the controller set up for the next packet as fast | 1660 | * get the controller set up for the next packet as fast |
| @@ -1677,48 +1665,39 @@ static void z8530_rx_done(struct z8530_channel *c) | |||
| 1677 | * if you build a system where the sync irq isnt blocked | 1665 | * if you build a system where the sync irq isnt blocked |
| 1678 | * by the kernel IRQ disable then you need only block the | 1666 | * by the kernel IRQ disable then you need only block the |
| 1679 | * sync IRQ for the RT_LOCK area. | 1667 | * sync IRQ for the RT_LOCK area. |
| 1680 | * | 1668 | * |
| 1681 | */ | 1669 | */ |
| 1682 | ct=c->count; | 1670 | ct=c->count; |
| 1683 | 1671 | ||
| 1684 | c->skb = c->skb2; | 1672 | c->skb = c->skb2; |
| 1685 | c->count = 0; | 1673 | c->count = 0; |
| 1686 | c->max = c->mtu; | 1674 | c->max = c->mtu; |
| 1687 | if(c->skb) | 1675 | if (c->skb) { |
| 1688 | { | ||
| 1689 | c->dptr = c->skb->data; | 1676 | c->dptr = c->skb->data; |
| 1690 | c->max = c->mtu; | 1677 | c->max = c->mtu; |
| 1691 | } | 1678 | } else { |
| 1692 | else | 1679 | c->count = 0; |
| 1693 | { | ||
| 1694 | c->count= 0; | ||
| 1695 | c->max = 0; | 1680 | c->max = 0; |
| 1696 | } | 1681 | } |
| 1697 | RT_UNLOCK; | 1682 | RT_UNLOCK; |
| 1698 | 1683 | ||
| 1699 | c->skb2 = dev_alloc_skb(c->mtu); | 1684 | c->skb2 = dev_alloc_skb(c->mtu); |
| 1700 | if(c->skb2==NULL) | 1685 | if (c->skb2 == NULL) |
| 1701 | printk(KERN_WARNING "%s: memory squeeze.\n", | 1686 | printk(KERN_WARNING "%s: memory squeeze.\n", |
| 1702 | c->netdevice->name); | 1687 | c->netdevice->name); |
| 1703 | else | 1688 | else |
| 1704 | { | 1689 | skb_put(c->skb2, c->mtu); |
| 1705 | skb_put(c->skb2,c->mtu); | 1690 | c->netdevice->stats.rx_packets++; |
| 1706 | } | 1691 | c->netdevice->stats.rx_bytes += ct; |
| 1707 | c->stats.rx_packets++; | ||
| 1708 | c->stats.rx_bytes+=ct; | ||
| 1709 | |||
| 1710 | } | 1692 | } |
| 1711 | /* | 1693 | /* |
| 1712 | * If we received a frame we must now process it. | 1694 | * If we received a frame we must now process it. |
| 1713 | */ | 1695 | */ |
| 1714 | if(skb) | 1696 | if (skb) { |
| 1715 | { | ||
| 1716 | skb_trim(skb, ct); | 1697 | skb_trim(skb, ct); |
| 1717 | c->rx_function(c,skb); | 1698 | c->rx_function(c, skb); |
| 1718 | } | 1699 | } else { |
| 1719 | else | 1700 | c->netdevice->stats.rx_dropped++; |
| 1720 | { | ||
| 1721 | c->stats.rx_dropped++; | ||
| 1722 | printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name); | 1701 | printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name); |
| 1723 | } | 1702 | } |
| 1724 | } | 1703 | } |
| @@ -1730,7 +1709,7 @@ static void z8530_rx_done(struct z8530_channel *c) | |||
| 1730 | * Returns true if the buffer cross a DMA boundary on a PC. The poor | 1709 | * Returns true if the buffer cross a DMA boundary on a PC. The poor |
| 1731 | * thing can only DMA within a 64K block not across the edges of it. | 1710 | * thing can only DMA within a 64K block not across the edges of it. |
| 1732 | */ | 1711 | */ |
| 1733 | 1712 | ||
| 1734 | static inline int spans_boundary(struct sk_buff *skb) | 1713 | static inline int spans_boundary(struct sk_buff *skb) |
| 1735 | { | 1714 | { |
| 1736 | unsigned long a=(unsigned long)skb->data; | 1715 | unsigned long a=(unsigned long)skb->data; |
| @@ -1799,24 +1778,6 @@ int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) | |||
| 1799 | 1778 | ||
| 1800 | EXPORT_SYMBOL(z8530_queue_xmit); | 1779 | EXPORT_SYMBOL(z8530_queue_xmit); |
| 1801 | 1780 | ||
| 1802 | /** | ||
| 1803 | * z8530_get_stats - Get network statistics | ||
| 1804 | * @c: The channel to use | ||
| 1805 | * | ||
| 1806 | * Get the statistics block. We keep the statistics in software as | ||
| 1807 | * the chip doesn't do it for us. | ||
| 1808 | * | ||
| 1809 | * Locking is ignored here - we could lock for a copy but its | ||
| 1810 | * not likely to be that big an issue | ||
| 1811 | */ | ||
| 1812 | |||
| 1813 | struct net_device_stats *z8530_get_stats(struct z8530_channel *c) | ||
| 1814 | { | ||
| 1815 | return &c->stats; | ||
| 1816 | } | ||
| 1817 | |||
| 1818 | EXPORT_SYMBOL(z8530_get_stats); | ||
| 1819 | |||
| 1820 | /* | 1781 | /* |
| 1821 | * Module support | 1782 | * Module support |
| 1822 | */ | 1783 | */ |
diff --git a/drivers/net/wan/z85230.h b/drivers/net/wan/z85230.h index 158aea7b8eac..4f372396c512 100644 --- a/drivers/net/wan/z85230.h +++ b/drivers/net/wan/z85230.h | |||
| @@ -325,7 +325,6 @@ struct z8530_channel | |||
| 325 | 325 | ||
| 326 | void *private; /* For our owner */ | 326 | void *private; /* For our owner */ |
| 327 | struct net_device *netdevice; /* Network layer device */ | 327 | struct net_device *netdevice; /* Network layer device */ |
| 328 | struct net_device_stats stats; /* Network layer statistics */ | ||
| 329 | 328 | ||
| 330 | /* | 329 | /* |
| 331 | * Async features | 330 | * Async features |
| @@ -366,13 +365,13 @@ struct z8530_channel | |||
| 366 | unsigned char tx_active; /* character is being xmitted */ | 365 | unsigned char tx_active; /* character is being xmitted */ |
| 367 | unsigned char tx_stopped; /* output is suspended */ | 366 | unsigned char tx_stopped; /* output is suspended */ |
| 368 | 367 | ||
| 369 | spinlock_t *lock; /* Devicr lock */ | 368 | spinlock_t *lock; /* Device lock */ |
| 370 | }; | 369 | }; |
| 371 | 370 | ||
| 372 | /* | 371 | /* |
| 373 | * Each Z853x0 device. | 372 | * Each Z853x0 device. |
| 374 | */ | 373 | */ |
| 375 | 374 | ||
| 376 | struct z8530_dev | 375 | struct z8530_dev |
| 377 | { | 376 | { |
| 378 | char *name; /* Device instance name */ | 377 | char *name; /* Device instance name */ |
| @@ -408,7 +407,6 @@ extern int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *); | |||
| 408 | extern int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *); | 407 | extern int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *); |
| 409 | extern int z8530_channel_load(struct z8530_channel *, u8 *); | 408 | extern int z8530_channel_load(struct z8530_channel *, u8 *); |
| 410 | extern int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb); | 409 | extern int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb); |
| 411 | extern struct net_device_stats *z8530_get_stats(struct z8530_channel *c); | ||
| 412 | extern void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb); | 410 | extern void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb); |
| 413 | 411 | ||
| 414 | 412 | ||
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 4c7ff61a1a9c..9931b5ab59cd 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig | |||
| @@ -695,6 +695,7 @@ config MAC80211_HWSIM | |||
| 695 | 695 | ||
| 696 | source "drivers/net/wireless/p54/Kconfig" | 696 | source "drivers/net/wireless/p54/Kconfig" |
| 697 | source "drivers/net/wireless/ath5k/Kconfig" | 697 | source "drivers/net/wireless/ath5k/Kconfig" |
| 698 | source "drivers/net/wireless/ath9k/Kconfig" | ||
| 698 | source "drivers/net/wireless/iwlwifi/Kconfig" | 699 | source "drivers/net/wireless/iwlwifi/Kconfig" |
| 699 | source "drivers/net/wireless/hostap/Kconfig" | 700 | source "drivers/net/wireless/hostap/Kconfig" |
| 700 | source "drivers/net/wireless/b43/Kconfig" | 701 | source "drivers/net/wireless/b43/Kconfig" |
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile index 54a4f6f1db67..59aa89ec6e81 100644 --- a/drivers/net/wireless/Makefile +++ b/drivers/net/wireless/Makefile | |||
| @@ -62,5 +62,6 @@ obj-$(CONFIG_RT2X00) += rt2x00/ | |||
| 62 | obj-$(CONFIG_P54_COMMON) += p54/ | 62 | obj-$(CONFIG_P54_COMMON) += p54/ |
| 63 | 63 | ||
| 64 | obj-$(CONFIG_ATH5K) += ath5k/ | 64 | obj-$(CONFIG_ATH5K) += ath5k/ |
| 65 | obj-$(CONFIG_ATH9K) += ath9k/ | ||
| 65 | 66 | ||
| 66 | obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o | 67 | obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o |
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index ebf19bc11f5b..2028866f5995 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c | |||
| @@ -95,8 +95,6 @@ static struct pci_device_id ath5k_pci_id_table[] __devinitdata = { | |||
| 95 | { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ | 95 | { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ |
| 96 | { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ | 96 | { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ |
| 97 | { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ | 97 | { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ |
| 98 | { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */ | ||
| 99 | { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */ | ||
| 100 | { 0 } | 98 | { 0 } |
| 101 | }; | 99 | }; |
| 102 | MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); | 100 | MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); |
diff --git a/drivers/net/wireless/ath9k/Kconfig b/drivers/net/wireless/ath9k/Kconfig new file mode 100644 index 000000000000..9e19dcceb3a2 --- /dev/null +++ b/drivers/net/wireless/ath9k/Kconfig | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | config ATH9K | ||
| 2 | tristate "Atheros 802.11n wireless cards support" | ||
| 3 | depends on PCI && MAC80211 && WLAN_80211 | ||
| 4 | ---help--- | ||
| 5 | This module adds support for wireless adapters based on | ||
| 6 | Atheros IEEE 802.11n AR5008 and AR9001 family of chipsets. | ||
| 7 | |||
| 8 | If you choose to build a module, it'll be called ath9k. | ||
diff --git a/drivers/net/wireless/ath9k/Makefile b/drivers/net/wireless/ath9k/Makefile new file mode 100644 index 000000000000..a6411517e5f8 --- /dev/null +++ b/drivers/net/wireless/ath9k/Makefile | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | ath9k-y += hw.o \ | ||
| 2 | phy.o \ | ||
| 3 | regd.o \ | ||
| 4 | beacon.o \ | ||
| 5 | main.o \ | ||
| 6 | recv.o \ | ||
| 7 | xmit.o \ | ||
| 8 | rc.o \ | ||
| 9 | core.o | ||
| 10 | |||
| 11 | obj-$(CONFIG_ATH9K) += ath9k.o | ||
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h new file mode 100644 index 000000000000..d1b0fbae5a32 --- /dev/null +++ b/drivers/net/wireless/ath9k/ath9k.h | |||
| @@ -0,0 +1,1021 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef ATH9K_H | ||
| 18 | #define ATH9K_H | ||
| 19 | |||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #define ATHEROS_VENDOR_ID 0x168c | ||
| 23 | |||
| 24 | #define AR5416_DEVID_PCI 0x0023 | ||
| 25 | #define AR5416_DEVID_PCIE 0x0024 | ||
| 26 | #define AR9160_DEVID_PCI 0x0027 | ||
| 27 | #define AR9280_DEVID_PCI 0x0029 | ||
| 28 | #define AR9280_DEVID_PCIE 0x002a | ||
| 29 | |||
| 30 | #define AR5416_AR9100_DEVID 0x000b | ||
| 31 | |||
| 32 | #define AR_SUBVENDOR_ID_NOG 0x0e11 | ||
| 33 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | ||
| 34 | |||
| 35 | #define ATH9K_TXERR_XRETRY 0x01 | ||
| 36 | #define ATH9K_TXERR_FILT 0x02 | ||
| 37 | #define ATH9K_TXERR_FIFO 0x04 | ||
| 38 | #define ATH9K_TXERR_XTXOP 0x08 | ||
| 39 | #define ATH9K_TXERR_TIMER_EXPIRED 0x10 | ||
| 40 | |||
| 41 | #define ATH9K_TX_BA 0x01 | ||
| 42 | #define ATH9K_TX_PWRMGMT 0x02 | ||
| 43 | #define ATH9K_TX_DESC_CFG_ERR 0x04 | ||
| 44 | #define ATH9K_TX_DATA_UNDERRUN 0x08 | ||
| 45 | #define ATH9K_TX_DELIM_UNDERRUN 0x10 | ||
| 46 | #define ATH9K_TX_SW_ABORTED 0x40 | ||
| 47 | #define ATH9K_TX_SW_FILTERED 0x80 | ||
| 48 | |||
| 49 | #define NBBY 8 | ||
| 50 | |||
| 51 | struct ath_tx_status { | ||
| 52 | u32 ts_tstamp; | ||
| 53 | u16 ts_seqnum; | ||
| 54 | u8 ts_status; | ||
| 55 | u8 ts_ratecode; | ||
| 56 | u8 ts_rateindex; | ||
| 57 | int8_t ts_rssi; | ||
| 58 | u8 ts_shortretry; | ||
| 59 | u8 ts_longretry; | ||
| 60 | u8 ts_virtcol; | ||
| 61 | u8 ts_antenna; | ||
| 62 | u8 ts_flags; | ||
| 63 | int8_t ts_rssi_ctl0; | ||
| 64 | int8_t ts_rssi_ctl1; | ||
| 65 | int8_t ts_rssi_ctl2; | ||
| 66 | int8_t ts_rssi_ext0; | ||
| 67 | int8_t ts_rssi_ext1; | ||
| 68 | int8_t ts_rssi_ext2; | ||
| 69 | u8 pad[3]; | ||
| 70 | u32 ba_low; | ||
| 71 | u32 ba_high; | ||
| 72 | u32 evm0; | ||
| 73 | u32 evm1; | ||
| 74 | u32 evm2; | ||
| 75 | }; | ||
| 76 | |||
| 77 | struct ath_rx_status { | ||
| 78 | u32 rs_tstamp; | ||
| 79 | u16 rs_datalen; | ||
| 80 | u8 rs_status; | ||
| 81 | u8 rs_phyerr; | ||
| 82 | int8_t rs_rssi; | ||
| 83 | u8 rs_keyix; | ||
| 84 | u8 rs_rate; | ||
| 85 | u8 rs_antenna; | ||
| 86 | u8 rs_more; | ||
| 87 | int8_t rs_rssi_ctl0; | ||
| 88 | int8_t rs_rssi_ctl1; | ||
| 89 | int8_t rs_rssi_ctl2; | ||
| 90 | int8_t rs_rssi_ext0; | ||
| 91 | int8_t rs_rssi_ext1; | ||
| 92 | int8_t rs_rssi_ext2; | ||
| 93 | u8 rs_isaggr; | ||
| 94 | u8 rs_moreaggr; | ||
| 95 | u8 rs_num_delims; | ||
| 96 | u8 rs_flags; | ||
| 97 | u32 evm0; | ||
| 98 | u32 evm1; | ||
| 99 | u32 evm2; | ||
| 100 | }; | ||
| 101 | |||
| 102 | #define ATH9K_RXERR_CRC 0x01 | ||
| 103 | #define ATH9K_RXERR_PHY 0x02 | ||
| 104 | #define ATH9K_RXERR_FIFO 0x04 | ||
| 105 | #define ATH9K_RXERR_DECRYPT 0x08 | ||
| 106 | #define ATH9K_RXERR_MIC 0x10 | ||
| 107 | |||
| 108 | #define ATH9K_RX_MORE 0x01 | ||
| 109 | #define ATH9K_RX_MORE_AGGR 0x02 | ||
| 110 | #define ATH9K_RX_GI 0x04 | ||
| 111 | #define ATH9K_RX_2040 0x08 | ||
| 112 | #define ATH9K_RX_DELIM_CRC_PRE 0x10 | ||
| 113 | #define ATH9K_RX_DELIM_CRC_POST 0x20 | ||
| 114 | #define ATH9K_RX_DECRYPT_BUSY 0x40 | ||
| 115 | |||
| 116 | #define ATH9K_RXKEYIX_INVALID ((u8)-1) | ||
| 117 | #define ATH9K_TXKEYIX_INVALID ((u32)-1) | ||
| 118 | |||
| 119 | struct ath_desc { | ||
| 120 | u32 ds_link; | ||
| 121 | u32 ds_data; | ||
| 122 | u32 ds_ctl0; | ||
| 123 | u32 ds_ctl1; | ||
| 124 | u32 ds_hw[20]; | ||
| 125 | union { | ||
| 126 | struct ath_tx_status tx; | ||
| 127 | struct ath_rx_status rx; | ||
| 128 | void *stats; | ||
| 129 | } ds_us; | ||
| 130 | void *ds_vdata; | ||
| 131 | } __packed; | ||
| 132 | |||
| 133 | #define ds_txstat ds_us.tx | ||
| 134 | #define ds_rxstat ds_us.rx | ||
| 135 | #define ds_stat ds_us.stats | ||
| 136 | |||
| 137 | #define ATH9K_TXDESC_CLRDMASK 0x0001 | ||
| 138 | #define ATH9K_TXDESC_NOACK 0x0002 | ||
| 139 | #define ATH9K_TXDESC_RTSENA 0x0004 | ||
| 140 | #define ATH9K_TXDESC_CTSENA 0x0008 | ||
| 141 | #define ATH9K_TXDESC_INTREQ 0x0010 | ||
| 142 | #define ATH9K_TXDESC_VEOL 0x0020 | ||
| 143 | #define ATH9K_TXDESC_EXT_ONLY 0x0040 | ||
| 144 | #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 | ||
| 145 | #define ATH9K_TXDESC_VMF 0x0100 | ||
| 146 | #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 | ||
| 147 | |||
| 148 | #define ATH9K_RXDESC_INTREQ 0x0020 | ||
| 149 | |||
| 150 | enum wireless_mode { | ||
| 151 | ATH9K_MODE_11A = 0, | ||
| 152 | ATH9K_MODE_11B = 2, | ||
| 153 | ATH9K_MODE_11G = 3, | ||
| 154 | ATH9K_MODE_11NA_HT20 = 6, | ||
| 155 | ATH9K_MODE_11NG_HT20 = 7, | ||
| 156 | ATH9K_MODE_11NA_HT40PLUS = 8, | ||
| 157 | ATH9K_MODE_11NA_HT40MINUS = 9, | ||
| 158 | ATH9K_MODE_11NG_HT40PLUS = 10, | ||
| 159 | ATH9K_MODE_11NG_HT40MINUS = 11, | ||
| 160 | ATH9K_MODE_MAX | ||
| 161 | }; | ||
| 162 | |||
| 163 | enum ath9k_hw_caps { | ||
| 164 | ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), | ||
| 165 | ATH9K_HW_CAP_MIC_AESCCM = BIT(1), | ||
| 166 | ATH9K_HW_CAP_MIC_CKIP = BIT(2), | ||
| 167 | ATH9K_HW_CAP_MIC_TKIP = BIT(3), | ||
| 168 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), | ||
| 169 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), | ||
| 170 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), | ||
| 171 | ATH9K_HW_CAP_VEOL = BIT(7), | ||
| 172 | ATH9K_HW_CAP_BSSIDMASK = BIT(8), | ||
| 173 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), | ||
| 174 | ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), | ||
| 175 | ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), | ||
| 176 | ATH9K_HW_CAP_HT = BIT(12), | ||
| 177 | ATH9K_HW_CAP_GTT = BIT(13), | ||
| 178 | ATH9K_HW_CAP_FASTCC = BIT(14), | ||
| 179 | ATH9K_HW_CAP_RFSILENT = BIT(15), | ||
| 180 | ATH9K_HW_CAP_WOW = BIT(16), | ||
| 181 | ATH9K_HW_CAP_CST = BIT(17), | ||
| 182 | ATH9K_HW_CAP_ENHANCEDPM = BIT(18), | ||
| 183 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), | ||
| 184 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), | ||
| 185 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), | ||
| 186 | }; | ||
| 187 | |||
| 188 | enum ath9k_capability_type { | ||
| 189 | ATH9K_CAP_CIPHER = 0, | ||
| 190 | ATH9K_CAP_TKIP_MIC, | ||
| 191 | ATH9K_CAP_TKIP_SPLIT, | ||
| 192 | ATH9K_CAP_PHYCOUNTERS, | ||
| 193 | ATH9K_CAP_DIVERSITY, | ||
| 194 | ATH9K_CAP_TXPOW, | ||
| 195 | ATH9K_CAP_PHYDIAG, | ||
| 196 | ATH9K_CAP_MCAST_KEYSRCH, | ||
| 197 | ATH9K_CAP_TSF_ADJUST, | ||
| 198 | ATH9K_CAP_WME_TKIPMIC, | ||
| 199 | ATH9K_CAP_RFSILENT, | ||
| 200 | ATH9K_CAP_ANT_CFG_2GHZ, | ||
| 201 | ATH9K_CAP_ANT_CFG_5GHZ | ||
| 202 | }; | ||
| 203 | |||
| 204 | struct ath9k_hw_capabilities { | ||
| 205 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | ||
| 206 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ | ||
| 207 | u16 total_queues; | ||
| 208 | u16 keycache_size; | ||
| 209 | u16 low_5ghz_chan, high_5ghz_chan; | ||
| 210 | u16 low_2ghz_chan, high_2ghz_chan; | ||
| 211 | u16 num_mr_retries; | ||
| 212 | u16 rts_aggr_limit; | ||
| 213 | u8 tx_chainmask; | ||
| 214 | u8 rx_chainmask; | ||
| 215 | u16 tx_triglevel_max; | ||
| 216 | u16 reg_cap; | ||
| 217 | u8 num_gpio_pins; | ||
| 218 | u8 num_antcfg_2ghz; | ||
| 219 | u8 num_antcfg_5ghz; | ||
| 220 | }; | ||
| 221 | |||
| 222 | struct ath9k_ops_config { | ||
| 223 | int dma_beacon_response_time; | ||
| 224 | int sw_beacon_response_time; | ||
| 225 | int additional_swba_backoff; | ||
| 226 | int ack_6mb; | ||
| 227 | int cwm_ignore_extcca; | ||
| 228 | u8 pcie_powersave_enable; | ||
| 229 | u8 pcie_l1skp_enable; | ||
| 230 | u8 pcie_clock_req; | ||
| 231 | u32 pcie_waen; | ||
| 232 | int pcie_power_reset; | ||
| 233 | u8 pcie_restore; | ||
| 234 | u8 analog_shiftreg; | ||
| 235 | u8 ht_enable; | ||
| 236 | u32 ofdm_trig_low; | ||
| 237 | u32 ofdm_trig_high; | ||
| 238 | u32 cck_trig_high; | ||
| 239 | u32 cck_trig_low; | ||
| 240 | u32 enable_ani; | ||
| 241 | u8 noise_immunity_level; | ||
| 242 | u32 ofdm_weaksignal_det; | ||
| 243 | u32 cck_weaksignal_thr; | ||
| 244 | u8 spur_immunity_level; | ||
| 245 | u8 firstep_level; | ||
| 246 | int8_t rssi_thr_high; | ||
| 247 | int8_t rssi_thr_low; | ||
| 248 | u16 diversity_control; | ||
| 249 | u16 antenna_switch_swap; | ||
| 250 | int serialize_regmode; | ||
| 251 | int intr_mitigation; | ||
| 252 | #define SPUR_DISABLE 0 | ||
| 253 | #define SPUR_ENABLE_IOCTL 1 | ||
| 254 | #define SPUR_ENABLE_EEPROM 2 | ||
| 255 | #define AR_EEPROM_MODAL_SPURS 5 | ||
| 256 | #define AR_SPUR_5413_1 1640 | ||
| 257 | #define AR_SPUR_5413_2 1200 | ||
| 258 | #define AR_NO_SPUR 0x8000 | ||
| 259 | #define AR_BASE_FREQ_2GHZ 2300 | ||
| 260 | #define AR_BASE_FREQ_5GHZ 4900 | ||
| 261 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | ||
| 262 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | ||
| 263 | int spurmode; | ||
| 264 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | ||
| 265 | }; | ||
| 266 | |||
| 267 | enum ath9k_tx_queue { | ||
| 268 | ATH9K_TX_QUEUE_INACTIVE = 0, | ||
| 269 | ATH9K_TX_QUEUE_DATA, | ||
| 270 | ATH9K_TX_QUEUE_BEACON, | ||
| 271 | ATH9K_TX_QUEUE_CAB, | ||
| 272 | ATH9K_TX_QUEUE_UAPSD, | ||
| 273 | ATH9K_TX_QUEUE_PSPOLL | ||
| 274 | }; | ||
| 275 | |||
| 276 | #define ATH9K_NUM_TX_QUEUES 10 | ||
| 277 | |||
| 278 | enum ath9k_tx_queue_subtype { | ||
| 279 | ATH9K_WME_AC_BK = 0, | ||
| 280 | ATH9K_WME_AC_BE, | ||
| 281 | ATH9K_WME_AC_VI, | ||
| 282 | ATH9K_WME_AC_VO, | ||
| 283 | ATH9K_WME_UPSD | ||
| 284 | }; | ||
| 285 | |||
| 286 | enum ath9k_tx_queue_flags { | ||
| 287 | TXQ_FLAG_TXOKINT_ENABLE = 0x0001, | ||
| 288 | TXQ_FLAG_TXERRINT_ENABLE = 0x0001, | ||
| 289 | TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, | ||
| 290 | TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, | ||
| 291 | TXQ_FLAG_TXURNINT_ENABLE = 0x0008, | ||
| 292 | TXQ_FLAG_BACKOFF_DISABLE = 0x0010, | ||
| 293 | TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, | ||
| 294 | TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, | ||
| 295 | TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, | ||
| 296 | }; | ||
| 297 | |||
| 298 | #define ATH9K_TXQ_USEDEFAULT ((u32) -1) | ||
| 299 | |||
| 300 | #define ATH9K_DECOMP_MASK_SIZE 128 | ||
| 301 | #define ATH9K_READY_TIME_LO_BOUND 50 | ||
| 302 | #define ATH9K_READY_TIME_HI_BOUND 96 | ||
| 303 | |||
| 304 | enum ath9k_pkt_type { | ||
| 305 | ATH9K_PKT_TYPE_NORMAL = 0, | ||
| 306 | ATH9K_PKT_TYPE_ATIM, | ||
| 307 | ATH9K_PKT_TYPE_PSPOLL, | ||
| 308 | ATH9K_PKT_TYPE_BEACON, | ||
| 309 | ATH9K_PKT_TYPE_PROBE_RESP, | ||
| 310 | ATH9K_PKT_TYPE_CHIRP, | ||
| 311 | ATH9K_PKT_TYPE_GRP_POLL, | ||
| 312 | }; | ||
| 313 | |||
| 314 | struct ath9k_tx_queue_info { | ||
| 315 | u32 tqi_ver; | ||
| 316 | enum ath9k_tx_queue tqi_type; | ||
| 317 | enum ath9k_tx_queue_subtype tqi_subtype; | ||
| 318 | enum ath9k_tx_queue_flags tqi_qflags; | ||
| 319 | u32 tqi_priority; | ||
| 320 | u32 tqi_aifs; | ||
| 321 | u32 tqi_cwmin; | ||
| 322 | u32 tqi_cwmax; | ||
| 323 | u16 tqi_shretry; | ||
| 324 | u16 tqi_lgretry; | ||
| 325 | u32 tqi_cbrPeriod; | ||
| 326 | u32 tqi_cbrOverflowLimit; | ||
| 327 | u32 tqi_burstTime; | ||
| 328 | u32 tqi_readyTime; | ||
| 329 | u32 tqi_physCompBuf; | ||
| 330 | u32 tqi_intFlags; | ||
| 331 | }; | ||
| 332 | |||
| 333 | enum ath9k_rx_filter { | ||
| 334 | ATH9K_RX_FILTER_UCAST = 0x00000001, | ||
| 335 | ATH9K_RX_FILTER_MCAST = 0x00000002, | ||
| 336 | ATH9K_RX_FILTER_BCAST = 0x00000004, | ||
| 337 | ATH9K_RX_FILTER_CONTROL = 0x00000008, | ||
| 338 | ATH9K_RX_FILTER_BEACON = 0x00000010, | ||
| 339 | ATH9K_RX_FILTER_PROM = 0x00000020, | ||
| 340 | ATH9K_RX_FILTER_PROBEREQ = 0x00000080, | ||
| 341 | ATH9K_RX_FILTER_PSPOLL = 0x00004000, | ||
| 342 | ATH9K_RX_FILTER_PHYERR = 0x00000100, | ||
| 343 | ATH9K_RX_FILTER_PHYRADAR = 0x00002000, | ||
| 344 | }; | ||
| 345 | |||
| 346 | enum ath9k_int { | ||
| 347 | ATH9K_INT_RX = 0x00000001, | ||
| 348 | ATH9K_INT_RXDESC = 0x00000002, | ||
| 349 | ATH9K_INT_RXNOFRM = 0x00000008, | ||
| 350 | ATH9K_INT_RXEOL = 0x00000010, | ||
| 351 | ATH9K_INT_RXORN = 0x00000020, | ||
| 352 | ATH9K_INT_TX = 0x00000040, | ||
| 353 | ATH9K_INT_TXDESC = 0x00000080, | ||
| 354 | ATH9K_INT_TIM_TIMER = 0x00000100, | ||
| 355 | ATH9K_INT_TXURN = 0x00000800, | ||
| 356 | ATH9K_INT_MIB = 0x00001000, | ||
| 357 | ATH9K_INT_RXPHY = 0x00004000, | ||
| 358 | ATH9K_INT_RXKCM = 0x00008000, | ||
| 359 | ATH9K_INT_SWBA = 0x00010000, | ||
| 360 | ATH9K_INT_BMISS = 0x00040000, | ||
| 361 | ATH9K_INT_BNR = 0x00100000, | ||
| 362 | ATH9K_INT_TIM = 0x00200000, | ||
| 363 | ATH9K_INT_DTIM = 0x00400000, | ||
| 364 | ATH9K_INT_DTIMSYNC = 0x00800000, | ||
| 365 | ATH9K_INT_GPIO = 0x01000000, | ||
| 366 | ATH9K_INT_CABEND = 0x02000000, | ||
| 367 | ATH9K_INT_CST = 0x10000000, | ||
| 368 | ATH9K_INT_GTT = 0x20000000, | ||
| 369 | ATH9K_INT_FATAL = 0x40000000, | ||
| 370 | ATH9K_INT_GLOBAL = 0x80000000, | ||
| 371 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | ||
| 372 | ATH9K_INT_DTIM | | ||
| 373 | ATH9K_INT_DTIMSYNC | | ||
| 374 | ATH9K_INT_CABEND, | ||
| 375 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | ||
| 376 | ATH9K_INT_RXDESC | | ||
| 377 | ATH9K_INT_RXEOL | | ||
| 378 | ATH9K_INT_RXORN | | ||
| 379 | ATH9K_INT_TXURN | | ||
| 380 | ATH9K_INT_TXDESC | | ||
| 381 | ATH9K_INT_MIB | | ||
| 382 | ATH9K_INT_RXPHY | | ||
| 383 | ATH9K_INT_RXKCM | | ||
| 384 | ATH9K_INT_SWBA | | ||
| 385 | ATH9K_INT_BMISS | | ||
| 386 | ATH9K_INT_GPIO, | ||
| 387 | ATH9K_INT_NOCARD = 0xffffffff | ||
| 388 | }; | ||
| 389 | |||
| 390 | struct ath9k_rate_table { | ||
| 391 | int rateCount; | ||
| 392 | u8 rateCodeToIndex[256]; | ||
| 393 | struct { | ||
| 394 | u8 valid; | ||
| 395 | u8 phy; | ||
| 396 | u32 rateKbps; | ||
| 397 | u8 rateCode; | ||
| 398 | u8 shortPreamble; | ||
| 399 | u8 dot11Rate; | ||
| 400 | u8 controlRate; | ||
| 401 | u16 lpAckDuration; | ||
| 402 | u16 spAckDuration; | ||
| 403 | } info[32]; | ||
| 404 | }; | ||
| 405 | |||
| 406 | #define ATH9K_RATESERIES_RTS_CTS 0x0001 | ||
| 407 | #define ATH9K_RATESERIES_2040 0x0002 | ||
| 408 | #define ATH9K_RATESERIES_HALFGI 0x0004 | ||
| 409 | |||
| 410 | struct ath9k_11n_rate_series { | ||
| 411 | u32 Tries; | ||
| 412 | u32 Rate; | ||
| 413 | u32 PktDuration; | ||
| 414 | u32 ChSel; | ||
| 415 | u32 RateFlags; | ||
| 416 | }; | ||
| 417 | |||
| 418 | #define CHANNEL_CW_INT 0x00002 | ||
| 419 | #define CHANNEL_CCK 0x00020 | ||
| 420 | #define CHANNEL_OFDM 0x00040 | ||
| 421 | #define CHANNEL_2GHZ 0x00080 | ||
| 422 | #define CHANNEL_5GHZ 0x00100 | ||
| 423 | #define CHANNEL_PASSIVE 0x00200 | ||
| 424 | #define CHANNEL_DYN 0x00400 | ||
| 425 | #define CHANNEL_HALF 0x04000 | ||
| 426 | #define CHANNEL_QUARTER 0x08000 | ||
| 427 | #define CHANNEL_HT20 0x10000 | ||
| 428 | #define CHANNEL_HT40PLUS 0x20000 | ||
| 429 | #define CHANNEL_HT40MINUS 0x40000 | ||
| 430 | |||
| 431 | #define CHANNEL_INTERFERENCE 0x01 | ||
| 432 | #define CHANNEL_DFS 0x02 | ||
| 433 | #define CHANNEL_4MS_LIMIT 0x04 | ||
| 434 | #define CHANNEL_DFS_CLEAR 0x08 | ||
| 435 | #define CHANNEL_DISALLOW_ADHOC 0x10 | ||
| 436 | #define CHANNEL_PER_11D_ADHOC 0x20 | ||
| 437 | |||
| 438 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) | ||
| 439 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | ||
| 440 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | ||
| 441 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | ||
| 442 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | ||
| 443 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | ||
| 444 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | ||
| 445 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | ||
| 446 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | ||
| 447 | #define CHANNEL_ALL \ | ||
| 448 | (CHANNEL_OFDM| \ | ||
| 449 | CHANNEL_CCK| \ | ||
| 450 | CHANNEL_2GHZ | \ | ||
| 451 | CHANNEL_5GHZ | \ | ||
| 452 | CHANNEL_HT20 | \ | ||
| 453 | CHANNEL_HT40PLUS | \ | ||
| 454 | CHANNEL_HT40MINUS) | ||
| 455 | |||
| 456 | struct ath9k_channel { | ||
| 457 | u16 channel; | ||
| 458 | u32 channelFlags; | ||
| 459 | u8 privFlags; | ||
| 460 | int8_t maxRegTxPower; | ||
| 461 | int8_t maxTxPower; | ||
| 462 | int8_t minTxPower; | ||
| 463 | u32 chanmode; | ||
| 464 | int32_t CalValid; | ||
| 465 | bool oneTimeCalsDone; | ||
| 466 | int8_t iCoff; | ||
| 467 | int8_t qCoff; | ||
| 468 | int16_t rawNoiseFloor; | ||
| 469 | int8_t antennaMax; | ||
| 470 | u32 regDmnFlags; | ||
| 471 | u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */ | ||
| 472 | #ifdef ATH_NF_PER_CHAN | ||
| 473 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; | ||
| 474 | #endif | ||
| 475 | }; | ||
| 476 | |||
| 477 | #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ | ||
| 478 | (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ | ||
| 479 | (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ | ||
| 480 | (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) | ||
| 481 | #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) | ||
| 482 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ | ||
| 483 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | ||
| 484 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | ||
| 485 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | ||
| 486 | #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) | ||
| 487 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | ||
| 488 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | ||
| 489 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | ||
| 490 | #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) | ||
| 491 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) | ||
| 492 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | ||
| 493 | |||
| 494 | /* These macros check chanmode and not channelFlags */ | ||
| 495 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | ||
| 496 | ((_c)->chanmode == CHANNEL_G_HT20)) | ||
| 497 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | ||
| 498 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | ||
| 499 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | ||
| 500 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | ||
| 501 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | ||
| 502 | |||
| 503 | #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) | ||
| 504 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ | ||
| 505 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ | ||
| 506 | (((_c)->channel % 20) != 0) && \ | ||
| 507 | (((_c)->channel % 10) != 0)) | ||
| 508 | |||
| 509 | struct ath9k_keyval { | ||
| 510 | u8 kv_type; | ||
| 511 | u8 kv_pad; | ||
| 512 | u16 kv_len; | ||
| 513 | u8 kv_val[16]; | ||
| 514 | u8 kv_mic[8]; | ||
| 515 | u8 kv_txmic[8]; | ||
| 516 | }; | ||
| 517 | |||
| 518 | enum ath9k_key_type { | ||
| 519 | ATH9K_KEY_TYPE_CLEAR, | ||
| 520 | ATH9K_KEY_TYPE_WEP, | ||
| 521 | ATH9K_KEY_TYPE_AES, | ||
| 522 | ATH9K_KEY_TYPE_TKIP, | ||
| 523 | }; | ||
| 524 | |||
| 525 | enum ath9k_cipher { | ||
| 526 | ATH9K_CIPHER_WEP = 0, | ||
| 527 | ATH9K_CIPHER_AES_OCB = 1, | ||
| 528 | ATH9K_CIPHER_AES_CCM = 2, | ||
| 529 | ATH9K_CIPHER_CKIP = 3, | ||
| 530 | ATH9K_CIPHER_TKIP = 4, | ||
| 531 | ATH9K_CIPHER_CLR = 5, | ||
| 532 | ATH9K_CIPHER_MIC = 127 | ||
| 533 | }; | ||
| 534 | |||
| 535 | #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 | ||
| 536 | #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 | ||
| 537 | #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 | ||
| 538 | #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 | ||
| 539 | #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 | ||
| 540 | #define AR_EEPROM_EEPCAP_MAXQCU_S 4 | ||
| 541 | #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 | ||
| 542 | #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 | ||
| 543 | #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 | ||
| 544 | |||
| 545 | #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 | ||
| 546 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 | ||
| 547 | #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 | ||
| 548 | #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 | ||
| 549 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 | ||
| 550 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 | ||
| 551 | |||
| 552 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 | ||
| 553 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 | ||
| 554 | |||
| 555 | #define SD_NO_CTL 0xE0 | ||
| 556 | #define NO_CTL 0xff | ||
| 557 | #define CTL_MODE_M 7 | ||
| 558 | #define CTL_11A 0 | ||
| 559 | #define CTL_11B 1 | ||
| 560 | #define CTL_11G 2 | ||
| 561 | #define CTL_2GHT20 5 | ||
| 562 | #define CTL_5GHT20 6 | ||
| 563 | #define CTL_2GHT40 7 | ||
| 564 | #define CTL_5GHT40 8 | ||
| 565 | |||
| 566 | #define AR_EEPROM_MAC(i) (0x1d+(i)) | ||
| 567 | #define EEP_SCALE 100 | ||
| 568 | #define EEP_DELTA 10 | ||
| 569 | |||
| 570 | #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c | ||
| 571 | #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 | ||
| 572 | #define AR_EEPROM_RFSILENT_POLARITY 0x0002 | ||
| 573 | #define AR_EEPROM_RFSILENT_POLARITY_S 1 | ||
| 574 | |||
| 575 | #define CTRY_DEBUG 0x1ff | ||
| 576 | #define CTRY_DEFAULT 0 | ||
| 577 | |||
| 578 | enum reg_ext_bitmap { | ||
| 579 | REG_EXT_JAPAN_MIDBAND = 1, | ||
| 580 | REG_EXT_FCC_DFS_HT40 = 2, | ||
| 581 | REG_EXT_JAPAN_NONDFS_HT40 = 3, | ||
| 582 | REG_EXT_JAPAN_DFS_HT40 = 4 | ||
| 583 | }; | ||
| 584 | |||
| 585 | struct ath9k_country_entry { | ||
| 586 | u16 countryCode; | ||
| 587 | u16 regDmnEnum; | ||
| 588 | u16 regDmn5G; | ||
| 589 | u16 regDmn2G; | ||
| 590 | u8 isMultidomain; | ||
| 591 | u8 iso[3]; | ||
| 592 | }; | ||
| 593 | |||
| 594 | #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) | ||
| 595 | #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) | ||
| 596 | |||
| 597 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | ||
| 598 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | ||
| 599 | #define REG_RMW(_a, _r, _set, _clr) \ | ||
| 600 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | ||
| 601 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | ||
| 602 | REG_WRITE(_a, _r, \ | ||
| 603 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | ||
| 604 | #define REG_SET_BIT(_a, _r, _f) \ | ||
| 605 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | ||
| 606 | #define REG_CLR_BIT(_a, _r, _f) \ | ||
| 607 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | ||
| 608 | |||
| 609 | #define ATH9K_COMP_BUF_MAX_SIZE 9216 | ||
| 610 | #define ATH9K_COMP_BUF_ALIGN_SIZE 512 | ||
| 611 | |||
| 612 | #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 | ||
| 613 | |||
| 614 | #define INIT_AIFS 2 | ||
| 615 | #define INIT_CWMIN 15 | ||
| 616 | #define INIT_CWMIN_11B 31 | ||
| 617 | #define INIT_CWMAX 1023 | ||
| 618 | #define INIT_SH_RETRY 10 | ||
| 619 | #define INIT_LG_RETRY 10 | ||
| 620 | #define INIT_SSH_RETRY 32 | ||
| 621 | #define INIT_SLG_RETRY 32 | ||
| 622 | |||
| 623 | #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) | ||
| 624 | |||
| 625 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) | ||
| 626 | #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX | ||
| 627 | |||
| 628 | #define IEEE80211_WEP_IVLEN 3 | ||
| 629 | #define IEEE80211_WEP_KIDLEN 1 | ||
| 630 | #define IEEE80211_WEP_CRCLEN 4 | ||
| 631 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | ||
| 632 | (IEEE80211_WEP_IVLEN + \ | ||
| 633 | IEEE80211_WEP_KIDLEN + \ | ||
| 634 | IEEE80211_WEP_CRCLEN)) | ||
| 635 | #define IEEE80211_MAX_LEN (2300 + FCS_LEN + \ | ||
| 636 | (IEEE80211_WEP_IVLEN + \ | ||
| 637 | IEEE80211_WEP_KIDLEN + \ | ||
| 638 | IEEE80211_WEP_CRCLEN)) | ||
| 639 | |||
| 640 | #define MAX_REG_ADD_COUNT 129 | ||
| 641 | #define MAX_RATE_POWER 63 | ||
| 642 | |||
| 643 | enum ath9k_power_mode { | ||
| 644 | ATH9K_PM_AWAKE = 0, | ||
| 645 | ATH9K_PM_FULL_SLEEP, | ||
| 646 | ATH9K_PM_NETWORK_SLEEP, | ||
| 647 | ATH9K_PM_UNDEFINED | ||
| 648 | }; | ||
| 649 | |||
| 650 | struct ath9k_mib_stats { | ||
| 651 | u32 ackrcv_bad; | ||
| 652 | u32 rts_bad; | ||
| 653 | u32 rts_good; | ||
| 654 | u32 fcs_bad; | ||
| 655 | u32 beacons; | ||
| 656 | }; | ||
| 657 | |||
| 658 | enum ath9k_ant_setting { | ||
| 659 | ATH9K_ANT_VARIABLE = 0, | ||
| 660 | ATH9K_ANT_FIXED_A, | ||
| 661 | ATH9K_ANT_FIXED_B | ||
| 662 | }; | ||
| 663 | |||
| 664 | enum ath9k_opmode { | ||
| 665 | ATH9K_M_STA = 1, | ||
| 666 | ATH9K_M_IBSS = 0, | ||
| 667 | ATH9K_M_HOSTAP = 6, | ||
| 668 | ATH9K_M_MONITOR = 8 | ||
| 669 | }; | ||
| 670 | |||
| 671 | #define ATH9K_SLOT_TIME_6 6 | ||
| 672 | #define ATH9K_SLOT_TIME_9 9 | ||
| 673 | #define ATH9K_SLOT_TIME_20 20 | ||
| 674 | |||
| 675 | enum ath9k_ht_macmode { | ||
| 676 | ATH9K_HT_MACMODE_20 = 0, | ||
| 677 | ATH9K_HT_MACMODE_2040 = 1, | ||
| 678 | }; | ||
| 679 | |||
| 680 | enum ath9k_ht_extprotspacing { | ||
| 681 | ATH9K_HT_EXTPROTSPACING_20 = 0, | ||
| 682 | ATH9K_HT_EXTPROTSPACING_25 = 1, | ||
| 683 | }; | ||
| 684 | |||
| 685 | struct ath9k_ht_cwm { | ||
| 686 | enum ath9k_ht_macmode ht_macmode; | ||
| 687 | enum ath9k_ht_extprotspacing ht_extprotspacing; | ||
| 688 | }; | ||
| 689 | |||
| 690 | enum ath9k_ani_cmd { | ||
| 691 | ATH9K_ANI_PRESENT = 0x1, | ||
| 692 | ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, | ||
| 693 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, | ||
| 694 | ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, | ||
| 695 | ATH9K_ANI_FIRSTEP_LEVEL = 0x10, | ||
| 696 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, | ||
| 697 | ATH9K_ANI_MODE = 0x40, | ||
| 698 | ATH9K_ANI_PHYERR_RESET = 0x80, | ||
| 699 | ATH9K_ANI_ALL = 0xff | ||
| 700 | }; | ||
| 701 | |||
| 702 | enum phytype { | ||
| 703 | PHY_DS, | ||
| 704 | PHY_FH, | ||
| 705 | PHY_OFDM, | ||
| 706 | PHY_HT, | ||
| 707 | }; | ||
| 708 | #define PHY_CCK PHY_DS | ||
| 709 | |||
| 710 | enum start_adhoc_option { | ||
| 711 | START_ADHOC_NO_11A, | ||
| 712 | START_ADHOC_PER_11D, | ||
| 713 | START_ADHOC_IN_11A, | ||
| 714 | START_ADHOC_IN_11B, | ||
| 715 | }; | ||
| 716 | |||
| 717 | enum ath9k_tp_scale { | ||
| 718 | ATH9K_TP_SCALE_MAX = 0, | ||
| 719 | ATH9K_TP_SCALE_50, | ||
| 720 | ATH9K_TP_SCALE_25, | ||
| 721 | ATH9K_TP_SCALE_12, | ||
| 722 | ATH9K_TP_SCALE_MIN | ||
| 723 | }; | ||
| 724 | |||
| 725 | enum ser_reg_mode { | ||
| 726 | SER_REG_MODE_OFF = 0, | ||
| 727 | SER_REG_MODE_ON = 1, | ||
| 728 | SER_REG_MODE_AUTO = 2, | ||
| 729 | }; | ||
| 730 | |||
| 731 | #define AR_PHY_CCA_MAX_GOOD_VALUE -85 | ||
| 732 | #define AR_PHY_CCA_MAX_HIGH_VALUE -62 | ||
| 733 | #define AR_PHY_CCA_MIN_BAD_VALUE -121 | ||
| 734 | #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3 | ||
| 735 | #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5 | ||
| 736 | |||
| 737 | #define ATH9K_NF_CAL_HIST_MAX 5 | ||
| 738 | #define NUM_NF_READINGS 6 | ||
| 739 | |||
| 740 | struct ath9k_nfcal_hist { | ||
| 741 | int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; | ||
| 742 | u8 currIndex; | ||
| 743 | int16_t privNF; | ||
| 744 | u8 invalidNFcount; | ||
| 745 | }; | ||
| 746 | |||
| 747 | struct ath9k_beacon_state { | ||
| 748 | u32 bs_nexttbtt; | ||
| 749 | u32 bs_nextdtim; | ||
| 750 | u32 bs_intval; | ||
| 751 | #define ATH9K_BEACON_PERIOD 0x0000ffff | ||
| 752 | #define ATH9K_BEACON_ENA 0x00800000 | ||
| 753 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | ||
| 754 | u32 bs_dtimperiod; | ||
| 755 | u16 bs_cfpperiod; | ||
| 756 | u16 bs_cfpmaxduration; | ||
| 757 | u32 bs_cfpnext; | ||
| 758 | u16 bs_timoffset; | ||
| 759 | u16 bs_bmissthreshold; | ||
| 760 | u32 bs_sleepduration; | ||
| 761 | }; | ||
| 762 | |||
| 763 | struct ath9k_node_stats { | ||
| 764 | u32 ns_avgbrssi; | ||
| 765 | u32 ns_avgrssi; | ||
| 766 | u32 ns_avgtxrssi; | ||
| 767 | u32 ns_avgtxrate; | ||
| 768 | }; | ||
| 769 | |||
| 770 | #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) | ||
| 771 | |||
| 772 | enum ath9k_gpio_output_mux_type { | ||
| 773 | ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT, | ||
| 774 | ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, | ||
| 775 | ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, | ||
| 776 | ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, | ||
| 777 | ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED, | ||
| 778 | ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES | ||
| 779 | }; | ||
| 780 | |||
| 781 | enum { | ||
| 782 | ATH9K_RESET_POWER_ON, | ||
| 783 | ATH9K_RESET_WARM, | ||
| 784 | ATH9K_RESET_COLD, | ||
| 785 | }; | ||
| 786 | |||
| 787 | #define AH_USE_EEPROM 0x1 | ||
| 788 | |||
| 789 | struct ath_hal { | ||
| 790 | u32 ah_magic; | ||
| 791 | u16 ah_devid; | ||
| 792 | u16 ah_subvendorid; | ||
| 793 | struct ath_softc *ah_sc; | ||
| 794 | void __iomem *ah_sh; | ||
| 795 | u16 ah_countryCode; | ||
| 796 | u32 ah_macVersion; | ||
| 797 | u16 ah_macRev; | ||
| 798 | u16 ah_phyRev; | ||
| 799 | u16 ah_analog5GhzRev; | ||
| 800 | u16 ah_analog2GhzRev; | ||
| 801 | u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE]; | ||
| 802 | u32 ah_flags; | ||
| 803 | enum ath9k_opmode ah_opmode; | ||
| 804 | struct ath9k_ops_config ah_config; | ||
| 805 | struct ath9k_hw_capabilities ah_caps; | ||
| 806 | int16_t ah_powerLimit; | ||
| 807 | u16 ah_maxPowerLevel; | ||
| 808 | u32 ah_tpScale; | ||
| 809 | u16 ah_currentRD; | ||
| 810 | u16 ah_currentRDExt; | ||
| 811 | u16 ah_currentRDInUse; | ||
| 812 | u16 ah_currentRD5G; | ||
| 813 | u16 ah_currentRD2G; | ||
| 814 | char ah_iso[4]; | ||
| 815 | enum start_adhoc_option ah_adHocMode; | ||
| 816 | bool ah_commonMode; | ||
| 817 | struct ath9k_channel ah_channels[150]; | ||
| 818 | u32 ah_nchan; | ||
| 819 | struct ath9k_channel *ah_curchan; | ||
| 820 | u16 ah_rfsilent; | ||
| 821 | bool ah_rfkillEnabled; | ||
| 822 | bool ah_isPciExpress; | ||
| 823 | u16 ah_txTrigLevel; | ||
| 824 | #ifndef ATH_NF_PER_CHAN | ||
| 825 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; | ||
| 826 | #endif | ||
| 827 | }; | ||
| 828 | |||
| 829 | struct chan_centers { | ||
| 830 | u16 synth_center; | ||
| 831 | u16 ctl_center; | ||
| 832 | u16 ext_center; | ||
| 833 | }; | ||
| 834 | |||
| 835 | int ath_hal_getcapability(struct ath_hal *ah, | ||
| 836 | enum ath9k_capability_type type, | ||
| 837 | u32 capability, | ||
| 838 | u32 *result); | ||
| 839 | const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, | ||
| 840 | u32 mode); | ||
| 841 | void ath9k_hw_detach(struct ath_hal *ah); | ||
| 842 | struct ath_hal *ath9k_hw_attach(u16 devid, | ||
| 843 | struct ath_softc *sc, | ||
| 844 | void __iomem *mem, | ||
| 845 | int *error); | ||
| 846 | bool ath9k_regd_init_channels(struct ath_hal *ah, | ||
| 847 | u32 maxchans, u32 *nchans, | ||
| 848 | u8 *regclassids, | ||
| 849 | u32 maxregids, u32 *nregids, | ||
| 850 | u16 cc, | ||
| 851 | bool enableOutdoor, | ||
| 852 | bool enableExtendedChannels); | ||
| 853 | u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); | ||
| 854 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, | ||
| 855 | enum ath9k_int ints); | ||
| 856 | bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode, | ||
| 857 | struct ath9k_channel *chan, | ||
| 858 | enum ath9k_ht_macmode macmode, | ||
| 859 | u8 txchainmask, u8 rxchainmask, | ||
| 860 | enum ath9k_ht_extprotspacing extprotspacing, | ||
| 861 | bool bChannelChange, | ||
| 862 | int *status); | ||
| 863 | bool ath9k_hw_phy_disable(struct ath_hal *ah); | ||
| 864 | void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, | ||
| 865 | bool *isCalDone); | ||
| 866 | void ath9k_hw_ani_monitor(struct ath_hal *ah, | ||
| 867 | const struct ath9k_node_stats *stats, | ||
| 868 | struct ath9k_channel *chan); | ||
| 869 | bool ath9k_hw_calibrate(struct ath_hal *ah, | ||
| 870 | struct ath9k_channel *chan, | ||
| 871 | u8 rxchainmask, | ||
| 872 | bool longcal, | ||
| 873 | bool *isCalDone); | ||
| 874 | int16_t ath9k_hw_getchan_noise(struct ath_hal *ah, | ||
| 875 | struct ath9k_channel *chan); | ||
| 876 | void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, | ||
| 877 | u16 assocId); | ||
| 878 | void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); | ||
| 879 | void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, | ||
| 880 | u16 assocId); | ||
| 881 | bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); | ||
| 882 | void ath9k_hw_reset_tsf(struct ath_hal *ah); | ||
| 883 | bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); | ||
| 884 | bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, | ||
| 885 | const u8 *mac); | ||
| 886 | bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, | ||
| 887 | u16 entry, | ||
| 888 | const struct ath9k_keyval *k, | ||
| 889 | const u8 *mac, | ||
| 890 | int xorKey); | ||
| 891 | bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, | ||
| 892 | u32 setting); | ||
| 893 | void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); | ||
| 894 | bool ath9k_hw_intrpend(struct ath_hal *ah); | ||
| 895 | bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); | ||
| 896 | bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, | ||
| 897 | bool bIncTrigLevel); | ||
| 898 | void ath9k_hw_procmibevent(struct ath_hal *ah, | ||
| 899 | const struct ath9k_node_stats *stats); | ||
| 900 | bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); | ||
| 901 | void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); | ||
| 902 | bool ath9k_hw_phycounters(struct ath_hal *ah); | ||
| 903 | bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); | ||
| 904 | bool ath9k_hw_getcapability(struct ath_hal *ah, | ||
| 905 | enum ath9k_capability_type type, | ||
| 906 | u32 capability, | ||
| 907 | u32 *result); | ||
| 908 | bool ath9k_hw_setcapability(struct ath_hal *ah, | ||
| 909 | enum ath9k_capability_type type, | ||
| 910 | u32 capability, | ||
| 911 | u32 setting, | ||
| 912 | int *status); | ||
| 913 | u32 ath9k_hw_getdefantenna(struct ath_hal *ah); | ||
| 914 | void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac); | ||
| 915 | void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask); | ||
| 916 | bool ath9k_hw_setbssidmask(struct ath_hal *ah, | ||
| 917 | const u8 *mask); | ||
| 918 | bool ath9k_hw_setpower(struct ath_hal *ah, | ||
| 919 | enum ath9k_power_mode mode); | ||
| 920 | enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); | ||
| 921 | u64 ath9k_hw_gettsf64(struct ath_hal *ah); | ||
| 922 | u32 ath9k_hw_getdefantenna(struct ath_hal *ah); | ||
| 923 | bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); | ||
| 924 | bool ath9k_hw_setantennaswitch(struct ath_hal *ah, | ||
| 925 | enum ath9k_ant_setting settings, | ||
| 926 | struct ath9k_channel *chan, | ||
| 927 | u8 *tx_chainmask, | ||
| 928 | u8 *rx_chainmask, | ||
| 929 | u8 *antenna_cfgd); | ||
| 930 | void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); | ||
| 931 | int ath9k_hw_select_antconfig(struct ath_hal *ah, | ||
| 932 | u32 cfg); | ||
| 933 | bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, | ||
| 934 | u32 txdp); | ||
| 935 | bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); | ||
| 936 | u16 ath9k_hw_computetxtime(struct ath_hal *ah, | ||
| 937 | const struct ath9k_rate_table *rates, | ||
| 938 | u32 frameLen, u16 rateix, | ||
| 939 | bool shortPreamble); | ||
| 940 | void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, | ||
| 941 | struct ath_desc *lastds, | ||
| 942 | u32 durUpdateEn, u32 rtsctsRate, | ||
| 943 | u32 rtsctsDuration, | ||
| 944 | struct ath9k_11n_rate_series series[], | ||
| 945 | u32 nseries, u32 flags); | ||
| 946 | void ath9k_hw_set11n_burstduration(struct ath_hal *ah, | ||
| 947 | struct ath_desc *ds, | ||
| 948 | u32 burstDuration); | ||
| 949 | void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); | ||
| 950 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); | ||
| 951 | bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); | ||
| 952 | u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); | ||
| 953 | u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah, | ||
| 954 | struct ath9k_channel *chan); | ||
| 955 | u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); | ||
| 956 | bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, | ||
| 957 | struct ath9k_tx_queue_info *qinfo); | ||
| 958 | bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, | ||
| 959 | const struct ath9k_tx_queue_info *qinfo); | ||
| 960 | struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah, | ||
| 961 | const struct ath9k_channel *c); | ||
| 962 | void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 963 | u32 pktLen, enum ath9k_pkt_type type, | ||
| 964 | u32 txPower, u32 keyIx, | ||
| 965 | enum ath9k_key_type keyType, u32 flags); | ||
| 966 | bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 967 | u32 segLen, bool firstSeg, | ||
| 968 | bool lastSeg, | ||
| 969 | const struct ath_desc *ds0); | ||
| 970 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, | ||
| 971 | u32 *rxc_pcnt, | ||
| 972 | u32 *rxf_pcnt, | ||
| 973 | u32 *txf_pcnt); | ||
| 974 | void ath9k_hw_dmaRegDump(struct ath_hal *ah); | ||
| 975 | void ath9k_hw_beaconinit(struct ath_hal *ah, | ||
| 976 | u32 next_beacon, u32 beacon_period); | ||
| 977 | void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, | ||
| 978 | const struct ath9k_beacon_state *bs); | ||
| 979 | bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 980 | u32 size, u32 flags); | ||
| 981 | void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); | ||
| 982 | void ath9k_hw_rxena(struct ath_hal *ah); | ||
| 983 | void ath9k_hw_setopmode(struct ath_hal *ah); | ||
| 984 | bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); | ||
| 985 | void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, | ||
| 986 | u32 filter1); | ||
| 987 | u32 ath9k_hw_getrxfilter(struct ath_hal *ah); | ||
| 988 | void ath9k_hw_startpcureceive(struct ath_hal *ah); | ||
| 989 | void ath9k_hw_stoppcurecv(struct ath_hal *ah); | ||
| 990 | bool ath9k_hw_stopdmarecv(struct ath_hal *ah); | ||
| 991 | int ath9k_hw_rxprocdesc(struct ath_hal *ah, | ||
| 992 | struct ath_desc *ds, u32 pa, | ||
| 993 | struct ath_desc *nds, u64 tsf); | ||
| 994 | u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); | ||
| 995 | int ath9k_hw_txprocdesc(struct ath_hal *ah, | ||
| 996 | struct ath_desc *ds); | ||
| 997 | void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, | ||
| 998 | u32 numDelims); | ||
| 999 | void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, | ||
| 1000 | u32 aggrLen); | ||
| 1001 | void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); | ||
| 1002 | bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); | ||
| 1003 | void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); | ||
| 1004 | void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); | ||
| 1005 | void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, | ||
| 1006 | struct ath_desc *ds, u32 vmf); | ||
| 1007 | bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); | ||
| 1008 | bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah); | ||
| 1009 | int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, | ||
| 1010 | const struct ath9k_tx_queue_info *qinfo); | ||
| 1011 | u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); | ||
| 1012 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); | ||
| 1013 | bool ath9k_hw_disable(struct ath_hal *ah); | ||
| 1014 | void ath9k_hw_rfdetach(struct ath_hal *ah); | ||
| 1015 | void ath9k_hw_get_channel_centers(struct ath_hal *ah, | ||
| 1016 | struct ath9k_channel *chan, | ||
| 1017 | struct chan_centers *centers); | ||
| 1018 | bool ath9k_get_channel_edges(struct ath_hal *ah, | ||
| 1019 | u16 flags, u16 *low, | ||
| 1020 | u16 *high); | ||
| 1021 | #endif | ||
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c new file mode 100644 index 000000000000..caf569401a34 --- /dev/null +++ b/drivers/net/wireless/ath9k/beacon.c | |||
| @@ -0,0 +1,979 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* Implementation of beacon processing. */ | ||
| 18 | |||
| 19 | #include <asm/unaligned.h> | ||
| 20 | #include "core.h" | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Configure parameters for the beacon queue | ||
| 24 | * | ||
| 25 | * This function will modify certain transmit queue properties depending on | ||
| 26 | * the operating mode of the station (AP or AdHoc). Parameters are AIFS | ||
| 27 | * settings and channel width min/max | ||
| 28 | */ | ||
| 29 | |||
| 30 | static int ath_beaconq_config(struct ath_softc *sc) | ||
| 31 | { | ||
| 32 | struct ath_hal *ah = sc->sc_ah; | ||
| 33 | struct ath9k_tx_queue_info qi; | ||
| 34 | |||
| 35 | ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi); | ||
| 36 | if (sc->sc_opmode == ATH9K_M_HOSTAP) { | ||
| 37 | /* Always burst out beacon and CAB traffic. */ | ||
| 38 | qi.tqi_aifs = 1; | ||
| 39 | qi.tqi_cwmin = 0; | ||
| 40 | qi.tqi_cwmax = 0; | ||
| 41 | } else { | ||
| 42 | /* Adhoc mode; important thing is to use 2x cwmin. */ | ||
| 43 | qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs; | ||
| 44 | qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin; | ||
| 45 | qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax; | ||
| 46 | } | ||
| 47 | |||
| 48 | if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { | ||
| 49 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 50 | "%s: unable to update h/w beacon queue parameters\n", | ||
| 51 | __func__); | ||
| 52 | return 0; | ||
| 53 | } else { | ||
| 54 | ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ | ||
| 55 | return 1; | ||
| 56 | } | ||
| 57 | } | ||
| 58 | |||
| 59 | /* | ||
| 60 | * Setup the beacon frame for transmit. | ||
| 61 | * | ||
| 62 | * Associates the beacon frame buffer with a transmit descriptor. Will set | ||
| 63 | * up all required antenna switch parameters, rate codes, and channel flags. | ||
| 64 | * Beacons are always sent out at the lowest rate, and are not retried. | ||
| 65 | */ | ||
| 66 | |||
| 67 | static void ath_beacon_setup(struct ath_softc *sc, | ||
| 68 | struct ath_vap *avp, struct ath_buf *bf) | ||
| 69 | { | ||
| 70 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | ||
| 71 | struct ath_hal *ah = sc->sc_ah; | ||
| 72 | struct ath_desc *ds; | ||
| 73 | int flags, antenna; | ||
| 74 | const struct ath9k_rate_table *rt; | ||
| 75 | u8 rix, rate; | ||
| 76 | int ctsrate = 0; | ||
| 77 | int ctsduration = 0; | ||
| 78 | struct ath9k_11n_rate_series series[4]; | ||
| 79 | |||
| 80 | DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n", | ||
| 81 | __func__, skb, skb->len); | ||
| 82 | |||
| 83 | /* setup descriptors */ | ||
| 84 | ds = bf->bf_desc; | ||
| 85 | |||
| 86 | flags = ATH9K_TXDESC_NOACK; | ||
| 87 | |||
| 88 | if (sc->sc_opmode == ATH9K_M_IBSS && | ||
| 89 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { | ||
| 90 | ds->ds_link = bf->bf_daddr; /* self-linked */ | ||
| 91 | flags |= ATH9K_TXDESC_VEOL; | ||
| 92 | /* Let hardware handle antenna switching. */ | ||
| 93 | antenna = 0; | ||
| 94 | } else { | ||
| 95 | ds->ds_link = 0; | ||
| 96 | /* | ||
| 97 | * Switch antenna every beacon. | ||
| 98 | * Should only switch every beacon period, not for every | ||
| 99 | * SWBA's | ||
| 100 | * XXX assumes two antenna | ||
| 101 | */ | ||
| 102 | antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); | ||
| 103 | } | ||
| 104 | |||
| 105 | ds->ds_data = bf->bf_buf_addr; | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Calculate rate code. | ||
| 109 | * XXX everything at min xmit rate | ||
| 110 | */ | ||
| 111 | rix = 0; | ||
| 112 | rt = sc->sc_currates; | ||
| 113 | rate = rt->info[rix].rateCode; | ||
| 114 | if (sc->sc_flags & ATH_PREAMBLE_SHORT) | ||
| 115 | rate |= rt->info[rix].shortPreamble; | ||
| 116 | |||
| 117 | ath9k_hw_set11n_txdesc(ah, ds | ||
| 118 | , skb->len + FCS_LEN /* frame length */ | ||
| 119 | , ATH9K_PKT_TYPE_BEACON /* Atheros packet type */ | ||
| 120 | , avp->av_btxctl.txpower /* txpower XXX */ | ||
| 121 | , ATH9K_TXKEYIX_INVALID /* no encryption */ | ||
| 122 | , ATH9K_KEY_TYPE_CLEAR /* no encryption */ | ||
| 123 | , flags /* no ack, veol for beacons */ | ||
| 124 | ); | ||
| 125 | |||
| 126 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | ||
| 127 | ath9k_hw_filltxdesc(ah, ds | ||
| 128 | , roundup(skb->len, 4) /* buffer length */ | ||
| 129 | , true /* first segment */ | ||
| 130 | , true /* last segment */ | ||
| 131 | , ds /* first descriptor */ | ||
| 132 | ); | ||
| 133 | |||
| 134 | memzero(series, sizeof(struct ath9k_11n_rate_series) * 4); | ||
| 135 | series[0].Tries = 1; | ||
| 136 | series[0].Rate = rate; | ||
| 137 | series[0].ChSel = sc->sc_tx_chainmask; | ||
| 138 | series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; | ||
| 139 | ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, | ||
| 140 | ctsrate, ctsduration, series, 4, 0); | ||
| 141 | } | ||
| 142 | |||
| 143 | /* Move everything from the vap's mcast queue to the hardware cab queue. | ||
| 144 | * Caller must hold mcasq lock and cabq lock | ||
| 145 | * XXX MORE_DATA bit? | ||
| 146 | */ | ||
| 147 | static void empty_mcastq_into_cabq(struct ath_hal *ah, | ||
| 148 | struct ath_txq *mcastq, struct ath_txq *cabq) | ||
| 149 | { | ||
| 150 | struct ath_buf *bfmcast; | ||
| 151 | |||
| 152 | BUG_ON(list_empty(&mcastq->axq_q)); | ||
| 153 | |||
| 154 | bfmcast = list_first_entry(&mcastq->axq_q, struct ath_buf, list); | ||
| 155 | |||
| 156 | /* link the descriptors */ | ||
| 157 | if (!cabq->axq_link) | ||
| 158 | ath9k_hw_puttxbuf(ah, cabq->axq_qnum, bfmcast->bf_daddr); | ||
| 159 | else | ||
| 160 | *cabq->axq_link = bfmcast->bf_daddr; | ||
| 161 | |||
| 162 | /* append the private vap mcast list to the cabq */ | ||
| 163 | |||
| 164 | cabq->axq_depth += mcastq->axq_depth; | ||
| 165 | cabq->axq_totalqueued += mcastq->axq_totalqueued; | ||
| 166 | cabq->axq_linkbuf = mcastq->axq_linkbuf; | ||
| 167 | cabq->axq_link = mcastq->axq_link; | ||
| 168 | list_splice_tail_init(&mcastq->axq_q, &cabq->axq_q); | ||
| 169 | mcastq->axq_depth = 0; | ||
| 170 | mcastq->axq_totalqueued = 0; | ||
| 171 | mcastq->axq_linkbuf = NULL; | ||
| 172 | mcastq->axq_link = NULL; | ||
| 173 | } | ||
| 174 | |||
| 175 | /* This is only run at DTIM. We move everything from the vap's mcast queue | ||
| 176 | * to the hardware cab queue. Caller must hold the mcastq lock. */ | ||
| 177 | static void trigger_mcastq(struct ath_hal *ah, | ||
| 178 | struct ath_txq *mcastq, struct ath_txq *cabq) | ||
| 179 | { | ||
| 180 | spin_lock_bh(&cabq->axq_lock); | ||
| 181 | |||
| 182 | if (!list_empty(&mcastq->axq_q)) | ||
| 183 | empty_mcastq_into_cabq(ah, mcastq, cabq); | ||
| 184 | |||
| 185 | /* cabq is gated by beacon so it is safe to start here */ | ||
| 186 | if (!list_empty(&cabq->axq_q)) | ||
| 187 | ath9k_hw_txstart(ah, cabq->axq_qnum); | ||
| 188 | |||
| 189 | spin_unlock_bh(&cabq->axq_lock); | ||
| 190 | } | ||
| 191 | |||
| 192 | /* | ||
| 193 | * Generate beacon frame and queue cab data for a vap. | ||
| 194 | * | ||
| 195 | * Updates the contents of the beacon frame. It is assumed that the buffer for | ||
| 196 | * the beacon frame has been allocated in the ATH object, and simply needs to | ||
| 197 | * be filled for this cycle. Also, any CAB (crap after beacon?) traffic will | ||
| 198 | * be added to the beacon frame at this point. | ||
| 199 | */ | ||
| 200 | static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) | ||
| 201 | { | ||
| 202 | struct ath_hal *ah = sc->sc_ah; | ||
| 203 | struct ath_buf *bf; | ||
| 204 | struct ath_vap *avp; | ||
| 205 | struct sk_buff *skb; | ||
| 206 | int cabq_depth; | ||
| 207 | int mcastq_depth; | ||
| 208 | int is_beacon_dtim = 0; | ||
| 209 | unsigned int curlen; | ||
| 210 | struct ath_txq *cabq; | ||
| 211 | struct ath_txq *mcastq; | ||
| 212 | avp = sc->sc_vaps[if_id]; | ||
| 213 | |||
| 214 | mcastq = &avp->av_mcastq; | ||
| 215 | cabq = sc->sc_cabq; | ||
| 216 | |||
| 217 | ASSERT(avp); | ||
| 218 | |||
| 219 | if (avp->av_bcbuf == NULL) { | ||
| 220 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | ||
| 221 | __func__, avp, avp->av_bcbuf); | ||
| 222 | return NULL; | ||
| 223 | } | ||
| 224 | bf = avp->av_bcbuf; | ||
| 225 | skb = (struct sk_buff *) bf->bf_mpdu; | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Update dynamic beacon contents. If this returns | ||
| 229 | * non-zero then we need to remap the memory because | ||
| 230 | * the beacon frame changed size (probably because | ||
| 231 | * of the TIM bitmap). | ||
| 232 | */ | ||
| 233 | curlen = skb->len; | ||
| 234 | |||
| 235 | /* XXX: spin_lock_bh should not be used here, but sparse bitches | ||
| 236 | * otherwise. We should fix sparse :) */ | ||
| 237 | spin_lock_bh(&mcastq->axq_lock); | ||
| 238 | mcastq_depth = avp->av_mcastq.axq_depth; | ||
| 239 | |||
| 240 | if (ath_update_beacon(sc, if_id, &avp->av_boff, skb, mcastq_depth) == | ||
| 241 | 1) { | ||
| 242 | ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE, | ||
| 243 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 244 | bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE, | ||
| 245 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 246 | } else { | ||
| 247 | pci_dma_sync_single_for_cpu(sc->pdev, | ||
| 248 | bf->bf_buf_addr, | ||
| 249 | skb_tailroom(skb), | ||
| 250 | PCI_DMA_TODEVICE); | ||
| 251 | } | ||
| 252 | |||
| 253 | /* | ||
| 254 | * if the CABQ traffic from previous DTIM is pending and the current | ||
| 255 | * beacon is also a DTIM. | ||
| 256 | * 1) if there is only one vap let the cab traffic continue. | ||
| 257 | * 2) if there are more than one vap and we are using staggered | ||
| 258 | * beacons, then drain the cabq by dropping all the frames in | ||
| 259 | * the cabq so that the current vaps cab traffic can be scheduled. | ||
| 260 | */ | ||
| 261 | spin_lock_bh(&cabq->axq_lock); | ||
| 262 | cabq_depth = cabq->axq_depth; | ||
| 263 | spin_unlock_bh(&cabq->axq_lock); | ||
| 264 | |||
| 265 | is_beacon_dtim = avp->av_boff.bo_tim[4] & 1; | ||
| 266 | |||
| 267 | if (mcastq_depth && is_beacon_dtim && cabq_depth) { | ||
| 268 | /* | ||
| 269 | * Unlock the cabq lock as ath_tx_draintxq acquires | ||
| 270 | * the lock again which is a common function and that | ||
| 271 | * acquires txq lock inside. | ||
| 272 | */ | ||
| 273 | if (sc->sc_nvaps > 1) { | ||
| 274 | ath_tx_draintxq(sc, cabq, false); | ||
| 275 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 276 | "%s: flush previous cabq traffic\n", __func__); | ||
| 277 | } | ||
| 278 | } | ||
| 279 | |||
| 280 | /* Construct tx descriptor. */ | ||
| 281 | ath_beacon_setup(sc, avp, bf); | ||
| 282 | |||
| 283 | /* | ||
| 284 | * Enable the CAB queue before the beacon queue to | ||
| 285 | * insure cab frames are triggered by this beacon. | ||
| 286 | */ | ||
| 287 | if (is_beacon_dtim) | ||
| 288 | trigger_mcastq(ah, mcastq, cabq); | ||
| 289 | |||
| 290 | spin_unlock_bh(&mcastq->axq_lock); | ||
| 291 | return bf; | ||
| 292 | } | ||
| 293 | |||
| 294 | /* | ||
| 295 | * Startup beacon transmission for adhoc mode when they are sent entirely | ||
| 296 | * by the hardware using the self-linked descriptor + veol trick. | ||
| 297 | */ | ||
| 298 | |||
| 299 | static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) | ||
| 300 | { | ||
| 301 | struct ath_hal *ah = sc->sc_ah; | ||
| 302 | struct ath_buf *bf; | ||
| 303 | struct ath_vap *avp; | ||
| 304 | struct sk_buff *skb; | ||
| 305 | |||
| 306 | avp = sc->sc_vaps[if_id]; | ||
| 307 | ASSERT(avp); | ||
| 308 | |||
| 309 | if (avp->av_bcbuf == NULL) { | ||
| 310 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | ||
| 311 | __func__, avp, avp != NULL ? avp->av_bcbuf : NULL); | ||
| 312 | return; | ||
| 313 | } | ||
| 314 | bf = avp->av_bcbuf; | ||
| 315 | skb = (struct sk_buff *) bf->bf_mpdu; | ||
| 316 | |||
| 317 | /* Construct tx descriptor. */ | ||
| 318 | ath_beacon_setup(sc, avp, bf); | ||
| 319 | |||
| 320 | /* NB: caller is known to have already stopped tx dma */ | ||
| 321 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); | ||
| 322 | ath9k_hw_txstart(ah, sc->sc_bhalq); | ||
| 323 | DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__, | ||
| 324 | sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); | ||
| 325 | } | ||
| 326 | |||
| 327 | /* | ||
| 328 | * Setup a h/w transmit queue for beacons. | ||
| 329 | * | ||
| 330 | * This function allocates an information structure (struct ath9k_txq_info) | ||
| 331 | * on the stack, sets some specific parameters (zero out channel width | ||
| 332 | * min/max, and enable aifs). The info structure does not need to be | ||
| 333 | * persistant. | ||
| 334 | */ | ||
| 335 | |||
| 336 | int ath_beaconq_setup(struct ath_hal *ah) | ||
| 337 | { | ||
| 338 | struct ath9k_tx_queue_info qi; | ||
| 339 | |||
| 340 | memzero(&qi, sizeof(qi)); | ||
| 341 | qi.tqi_aifs = 1; | ||
| 342 | qi.tqi_cwmin = 0; | ||
| 343 | qi.tqi_cwmax = 0; | ||
| 344 | /* NB: don't enable any interrupts */ | ||
| 345 | return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); | ||
| 346 | } | ||
| 347 | |||
| 348 | |||
| 349 | /* | ||
| 350 | * Allocate and setup an initial beacon frame. | ||
| 351 | * | ||
| 352 | * Allocate a beacon state variable for a specific VAP instance created on | ||
| 353 | * the ATH interface. This routine also calculates the beacon "slot" for | ||
| 354 | * staggared beacons in the mBSSID case. | ||
| 355 | */ | ||
| 356 | |||
| 357 | int ath_beacon_alloc(struct ath_softc *sc, int if_id) | ||
| 358 | { | ||
| 359 | struct ath_vap *avp; | ||
| 360 | struct ieee80211_hdr *wh; | ||
| 361 | struct ath_buf *bf; | ||
| 362 | struct sk_buff *skb; | ||
| 363 | |||
| 364 | avp = sc->sc_vaps[if_id]; | ||
| 365 | ASSERT(avp); | ||
| 366 | |||
| 367 | /* Allocate a beacon descriptor if we haven't done so. */ | ||
| 368 | if (!avp->av_bcbuf) { | ||
| 369 | /* | ||
| 370 | * Allocate beacon state for hostap/ibss. We know | ||
| 371 | * a buffer is available. | ||
| 372 | */ | ||
| 373 | |||
| 374 | avp->av_bcbuf = list_first_entry(&sc->sc_bbuf, | ||
| 375 | struct ath_buf, list); | ||
| 376 | list_del(&avp->av_bcbuf->list); | ||
| 377 | |||
| 378 | if (sc->sc_opmode == ATH9K_M_HOSTAP || | ||
| 379 | !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { | ||
| 380 | int slot; | ||
| 381 | /* | ||
| 382 | * Assign the vap to a beacon xmit slot. As | ||
| 383 | * above, this cannot fail to find one. | ||
| 384 | */ | ||
| 385 | avp->av_bslot = 0; | ||
| 386 | for (slot = 0; slot < ATH_BCBUF; slot++) | ||
| 387 | if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) { | ||
| 388 | /* | ||
| 389 | * XXX hack, space out slots to better | ||
| 390 | * deal with misses | ||
| 391 | */ | ||
| 392 | if (slot+1 < ATH_BCBUF && | ||
| 393 | sc->sc_bslot[slot+1] == | ||
| 394 | ATH_IF_ID_ANY) { | ||
| 395 | avp->av_bslot = slot+1; | ||
| 396 | break; | ||
| 397 | } | ||
| 398 | avp->av_bslot = slot; | ||
| 399 | /* NB: keep looking for a double slot */ | ||
| 400 | } | ||
| 401 | BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY); | ||
| 402 | sc->sc_bslot[avp->av_bslot] = if_id; | ||
| 403 | sc->sc_nbcnvaps++; | ||
| 404 | } | ||
| 405 | } | ||
| 406 | |||
| 407 | /* release the previous beacon frame , if it already exists. */ | ||
| 408 | bf = avp->av_bcbuf; | ||
| 409 | if (bf->bf_mpdu != NULL) { | ||
| 410 | skb = (struct sk_buff *)bf->bf_mpdu; | ||
| 411 | ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE, | ||
| 412 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 413 | dev_kfree_skb_any(skb); | ||
| 414 | bf->bf_mpdu = NULL; | ||
| 415 | } | ||
| 416 | |||
| 417 | /* | ||
| 418 | * NB: the beacon data buffer must be 32-bit aligned; | ||
| 419 | * we assume the wbuf routines will return us something | ||
| 420 | * with this alignment (perhaps should assert). | ||
| 421 | * FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and | ||
| 422 | * avp->av_btxctl.shortPreamble | ||
| 423 | */ | ||
| 424 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); | ||
| 425 | if (skb == NULL) { | ||
| 426 | DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n", | ||
| 427 | __func__); | ||
| 428 | return -ENOMEM; | ||
| 429 | } | ||
| 430 | |||
| 431 | /* | ||
| 432 | * Calculate a TSF adjustment factor required for | ||
| 433 | * staggered beacons. Note that we assume the format | ||
| 434 | * of the beacon frame leaves the tstamp field immediately | ||
| 435 | * following the header. | ||
| 436 | */ | ||
| 437 | if (avp->av_bslot > 0) { | ||
| 438 | u64 tsfadjust; | ||
| 439 | __le64 val; | ||
| 440 | int intval; | ||
| 441 | |||
| 442 | /* FIXME: Use default value for now: Sujith */ | ||
| 443 | |||
| 444 | intval = ATH_DEFAULT_BINTVAL; | ||
| 445 | |||
| 446 | /* | ||
| 447 | * The beacon interval is in TU's; the TSF in usecs. | ||
| 448 | * We figure out how many TU's to add to align the | ||
| 449 | * timestamp then convert to TSF units and handle | ||
| 450 | * byte swapping before writing it in the frame. | ||
| 451 | * The hardware will then add this each time a beacon | ||
| 452 | * frame is sent. Note that we align vap's 1..N | ||
| 453 | * and leave vap 0 untouched. This means vap 0 | ||
| 454 | * has a timestamp in one beacon interval while the | ||
| 455 | * others get a timestamp aligned to the next interval. | ||
| 456 | */ | ||
| 457 | tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF; | ||
| 458 | val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ | ||
| 459 | |||
| 460 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 461 | "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n", | ||
| 462 | __func__, "stagger", | ||
| 463 | avp->av_bslot, intval, (unsigned long long)tsfadjust); | ||
| 464 | |||
| 465 | wh = (struct ieee80211_hdr *)skb->data; | ||
| 466 | memcpy(&wh[1], &val, sizeof(val)); | ||
| 467 | } | ||
| 468 | |||
| 469 | bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE, | ||
| 470 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 471 | bf->bf_mpdu = skb; | ||
| 472 | |||
| 473 | return 0; | ||
| 474 | } | ||
| 475 | |||
| 476 | /* | ||
| 477 | * Reclaim beacon resources and return buffer to the pool. | ||
| 478 | * | ||
| 479 | * Checks the VAP to put the beacon frame buffer back to the ATH object | ||
| 480 | * queue, and de-allocates any wbuf frames that were sent as CAB traffic. | ||
| 481 | */ | ||
| 482 | |||
| 483 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) | ||
| 484 | { | ||
| 485 | if (avp->av_bcbuf != NULL) { | ||
| 486 | struct ath_buf *bf; | ||
| 487 | |||
| 488 | if (avp->av_bslot != -1) { | ||
| 489 | sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY; | ||
| 490 | sc->sc_nbcnvaps--; | ||
| 491 | } | ||
| 492 | |||
| 493 | bf = avp->av_bcbuf; | ||
| 494 | if (bf->bf_mpdu != NULL) { | ||
| 495 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | ||
| 496 | ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE, | ||
| 497 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 498 | dev_kfree_skb_any(skb); | ||
| 499 | bf->bf_mpdu = NULL; | ||
| 500 | } | ||
| 501 | list_add_tail(&bf->list, &sc->sc_bbuf); | ||
| 502 | |||
| 503 | avp->av_bcbuf = NULL; | ||
| 504 | } | ||
| 505 | } | ||
| 506 | |||
| 507 | /* | ||
| 508 | * Reclaim beacon resources and return buffer to the pool. | ||
| 509 | * | ||
| 510 | * This function will free any wbuf frames that are still attached to the | ||
| 511 | * beacon buffers in the ATH object. Note that this does not de-allocate | ||
| 512 | * any wbuf objects that are in the transmit queue and have not yet returned | ||
| 513 | * to the ATH object. | ||
| 514 | */ | ||
| 515 | |||
| 516 | void ath_beacon_free(struct ath_softc *sc) | ||
| 517 | { | ||
| 518 | struct ath_buf *bf; | ||
| 519 | |||
| 520 | list_for_each_entry(bf, &sc->sc_bbuf, list) { | ||
| 521 | if (bf->bf_mpdu != NULL) { | ||
| 522 | struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu; | ||
| 523 | ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE, | ||
| 524 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 525 | dev_kfree_skb_any(skb); | ||
| 526 | bf->bf_mpdu = NULL; | ||
| 527 | } | ||
| 528 | } | ||
| 529 | } | ||
| 530 | |||
| 531 | /* | ||
| 532 | * Tasklet for Sending Beacons | ||
| 533 | * | ||
| 534 | * Transmit one or more beacon frames at SWBA. Dynamic updates to the frame | ||
| 535 | * contents are done as needed and the slot time is also adjusted based on | ||
| 536 | * current state. | ||
| 537 | * | ||
| 538 | * This tasklet is not scheduled, it's called in ISR context. | ||
| 539 | */ | ||
| 540 | |||
| 541 | void ath9k_beacon_tasklet(unsigned long data) | ||
| 542 | { | ||
| 543 | #define TSF_TO_TU(_h,_l) \ | ||
| 544 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | ||
| 545 | |||
| 546 | struct ath_softc *sc = (struct ath_softc *)data; | ||
| 547 | struct ath_hal *ah = sc->sc_ah; | ||
| 548 | struct ath_buf *bf = NULL; | ||
| 549 | int slot, if_id; | ||
| 550 | u32 bfaddr; | ||
| 551 | u32 rx_clear = 0, rx_frame = 0, tx_frame = 0; | ||
| 552 | u32 show_cycles = 0; | ||
| 553 | u32 bc = 0; /* beacon count */ | ||
| 554 | u64 tsf; | ||
| 555 | u32 tsftu; | ||
| 556 | u16 intval; | ||
| 557 | |||
| 558 | if (sc->sc_noreset) { | ||
| 559 | show_cycles = ath9k_hw_GetMibCycleCountsPct(ah, | ||
| 560 | &rx_clear, | ||
| 561 | &rx_frame, | ||
| 562 | &tx_frame); | ||
| 563 | } | ||
| 564 | |||
| 565 | /* | ||
| 566 | * Check if the previous beacon has gone out. If | ||
| 567 | * not don't try to post another, skip this period | ||
| 568 | * and wait for the next. Missed beacons indicate | ||
| 569 | * a problem and should not occur. If we miss too | ||
| 570 | * many consecutive beacons reset the device. | ||
| 571 | */ | ||
| 572 | if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) { | ||
| 573 | sc->sc_bmisscount++; | ||
| 574 | /* XXX: doth needs the chanchange IE countdown decremented. | ||
| 575 | * We should consider adding a mac80211 call to indicate | ||
| 576 | * a beacon miss so appropriate action could be taken | ||
| 577 | * (in that layer). | ||
| 578 | */ | ||
| 579 | if (sc->sc_bmisscount < BSTUCK_THRESH) { | ||
| 580 | if (sc->sc_noreset) { | ||
| 581 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 582 | "%s: missed %u consecutive beacons\n", | ||
| 583 | __func__, sc->sc_bmisscount); | ||
| 584 | if (show_cycles) { | ||
| 585 | /* | ||
| 586 | * Display cycle counter stats | ||
| 587 | * from HW to aide in debug of | ||
| 588 | * stickiness. | ||
| 589 | */ | ||
| 590 | DPRINTF(sc, | ||
| 591 | ATH_DBG_BEACON, | ||
| 592 | "%s: busy times: rx_clear=%d, " | ||
| 593 | "rx_frame=%d, tx_frame=%d\n", | ||
| 594 | __func__, rx_clear, rx_frame, | ||
| 595 | tx_frame); | ||
| 596 | } else { | ||
| 597 | DPRINTF(sc, | ||
| 598 | ATH_DBG_BEACON, | ||
| 599 | "%s: unable to obtain " | ||
| 600 | "busy times\n", __func__); | ||
| 601 | } | ||
| 602 | } else { | ||
| 603 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 604 | "%s: missed %u consecutive beacons\n", | ||
| 605 | __func__, sc->sc_bmisscount); | ||
| 606 | } | ||
| 607 | } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { | ||
| 608 | if (sc->sc_noreset) { | ||
| 609 | if (sc->sc_bmisscount == BSTUCK_THRESH) { | ||
| 610 | DPRINTF(sc, | ||
| 611 | ATH_DBG_BEACON, | ||
| 612 | "%s: beacon is officially " | ||
| 613 | "stuck\n", __func__); | ||
| 614 | ath9k_hw_dmaRegDump(ah); | ||
| 615 | } | ||
| 616 | } else { | ||
| 617 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 618 | "%s: beacon is officially stuck\n", | ||
| 619 | __func__); | ||
| 620 | ath_bstuck_process(sc); | ||
| 621 | } | ||
| 622 | } | ||
| 623 | |||
| 624 | return; | ||
| 625 | } | ||
| 626 | if (sc->sc_bmisscount != 0) { | ||
| 627 | if (sc->sc_noreset) { | ||
| 628 | DPRINTF(sc, | ||
| 629 | ATH_DBG_BEACON, | ||
| 630 | "%s: resume beacon xmit after %u misses\n", | ||
| 631 | __func__, sc->sc_bmisscount); | ||
| 632 | } else { | ||
| 633 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 634 | "%s: resume beacon xmit after %u misses\n", | ||
| 635 | __func__, sc->sc_bmisscount); | ||
| 636 | } | ||
| 637 | sc->sc_bmisscount = 0; | ||
| 638 | } | ||
| 639 | |||
| 640 | /* | ||
| 641 | * Generate beacon frames. we are sending frames | ||
| 642 | * staggered so calculate the slot for this frame based | ||
| 643 | * on the tsf to safeguard against missing an swba. | ||
| 644 | */ | ||
| 645 | |||
| 646 | /* FIXME: Use default value for now - Sujith */ | ||
| 647 | intval = ATH_DEFAULT_BINTVAL; | ||
| 648 | |||
| 649 | tsf = ath9k_hw_gettsf64(ah); | ||
| 650 | tsftu = TSF_TO_TU(tsf>>32, tsf); | ||
| 651 | slot = ((tsftu % intval) * ATH_BCBUF) / intval; | ||
| 652 | if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; | ||
| 653 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 654 | "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", | ||
| 655 | __func__, slot, (unsigned long long) tsf, tsftu, | ||
| 656 | intval, if_id); | ||
| 657 | bfaddr = 0; | ||
| 658 | if (if_id != ATH_IF_ID_ANY) { | ||
| 659 | bf = ath_beacon_generate(sc, if_id); | ||
| 660 | if (bf != NULL) { | ||
| 661 | bfaddr = bf->bf_daddr; | ||
| 662 | bc = 1; | ||
| 663 | } | ||
| 664 | } | ||
| 665 | /* | ||
| 666 | * Handle slot time change when a non-ERP station joins/leaves | ||
| 667 | * an 11g network. The 802.11 layer notifies us via callback, | ||
| 668 | * we mark updateslot, then wait one beacon before effecting | ||
| 669 | * the change. This gives associated stations at least one | ||
| 670 | * beacon interval to note the state change. | ||
| 671 | * | ||
| 672 | * NB: The slot time change state machine is clocked according | ||
| 673 | * to whether we are bursting or staggering beacons. We | ||
| 674 | * recognize the request to update and record the current | ||
| 675 | * slot then don't transition until that slot is reached | ||
| 676 | * again. If we miss a beacon for that slot then we'll be | ||
| 677 | * slow to transition but we'll be sure at least one beacon | ||
| 678 | * interval has passed. When bursting slot is always left | ||
| 679 | * set to ATH_BCBUF so this check is a noop. | ||
| 680 | */ | ||
| 681 | /* XXX locking */ | ||
| 682 | if (sc->sc_updateslot == UPDATE) { | ||
| 683 | sc->sc_updateslot = COMMIT; /* commit next beacon */ | ||
| 684 | sc->sc_slotupdate = slot; | ||
| 685 | } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) | ||
| 686 | ath_setslottime(sc); /* commit change to hardware */ | ||
| 687 | |||
| 688 | if (bfaddr != 0) { | ||
| 689 | /* | ||
| 690 | * Stop any current dma and put the new frame(s) on the queue. | ||
| 691 | * This should never fail since we check above that no frames | ||
| 692 | * are still pending on the queue. | ||
| 693 | */ | ||
| 694 | if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { | ||
| 695 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 696 | "%s: beacon queue %u did not stop?\n", | ||
| 697 | __func__, sc->sc_bhalq); | ||
| 698 | /* NB: the HAL still stops DMA, so proceed */ | ||
| 699 | } | ||
| 700 | |||
| 701 | /* NB: cabq traffic should already be queued and primed */ | ||
| 702 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr); | ||
| 703 | ath9k_hw_txstart(ah, sc->sc_bhalq); | ||
| 704 | |||
| 705 | sc->ast_be_xmit += bc; /* XXX per-vap? */ | ||
| 706 | } | ||
| 707 | #undef TSF_TO_TU | ||
| 708 | } | ||
| 709 | |||
| 710 | /* | ||
| 711 | * Tasklet for Beacon Stuck processing | ||
| 712 | * | ||
| 713 | * Processing for Beacon Stuck. | ||
| 714 | * Basically calls the ath_internal_reset function to reset the chip. | ||
| 715 | */ | ||
| 716 | |||
| 717 | void ath_bstuck_process(struct ath_softc *sc) | ||
| 718 | { | ||
| 719 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 720 | "%s: stuck beacon; resetting (bmiss count %u)\n", | ||
| 721 | __func__, sc->sc_bmisscount); | ||
| 722 | ath_internal_reset(sc); | ||
| 723 | } | ||
| 724 | |||
| 725 | /* | ||
| 726 | * Configure the beacon and sleep timers. | ||
| 727 | * | ||
| 728 | * When operating as an AP this resets the TSF and sets | ||
| 729 | * up the hardware to notify us when we need to issue beacons. | ||
| 730 | * | ||
| 731 | * When operating in station mode this sets up the beacon | ||
| 732 | * timers according to the timestamp of the last received | ||
| 733 | * beacon and the current TSF, configures PCF and DTIM | ||
| 734 | * handling, programs the sleep registers so the hardware | ||
| 735 | * will wakeup in time to receive beacons, and configures | ||
| 736 | * the beacon miss handling so we'll receive a BMISS | ||
| 737 | * interrupt when we stop seeing beacons from the AP | ||
| 738 | * we've associated with. | ||
| 739 | */ | ||
| 740 | |||
| 741 | void ath_beacon_config(struct ath_softc *sc, int if_id) | ||
| 742 | { | ||
| 743 | #define TSF_TO_TU(_h,_l) \ | ||
| 744 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | ||
| 745 | struct ath_hal *ah = sc->sc_ah; | ||
| 746 | u32 nexttbtt, intval; | ||
| 747 | struct ath_beacon_config conf; | ||
| 748 | enum ath9k_opmode av_opmode; | ||
| 749 | |||
| 750 | if (if_id != ATH_IF_ID_ANY) | ||
| 751 | av_opmode = sc->sc_vaps[if_id]->av_opmode; | ||
| 752 | else | ||
| 753 | av_opmode = sc->sc_opmode; | ||
| 754 | |||
| 755 | memzero(&conf, sizeof(struct ath_beacon_config)); | ||
| 756 | |||
| 757 | /* FIXME: Use default values for now - Sujith */ | ||
| 758 | /* Query beacon configuration first */ | ||
| 759 | /* | ||
| 760 | * Protocol stack doesn't support dynamic beacon configuration, | ||
| 761 | * use default configurations. | ||
| 762 | */ | ||
| 763 | conf.beacon_interval = ATH_DEFAULT_BINTVAL; | ||
| 764 | conf.listen_interval = 1; | ||
| 765 | conf.dtim_period = conf.beacon_interval; | ||
| 766 | conf.dtim_count = 1; | ||
| 767 | conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval; | ||
| 768 | |||
| 769 | /* extract tstamp from last beacon and convert to TU */ | ||
| 770 | nexttbtt = TSF_TO_TU(get_unaligned_le32(conf.u.last_tstamp + 4), | ||
| 771 | get_unaligned_le32(conf.u.last_tstamp)); | ||
| 772 | /* XXX conditionalize multi-bss support? */ | ||
| 773 | if (sc->sc_opmode == ATH9K_M_HOSTAP) { | ||
| 774 | /* | ||
| 775 | * For multi-bss ap support beacons are either staggered | ||
| 776 | * evenly over N slots or burst together. For the former | ||
| 777 | * arrange for the SWBA to be delivered for each slot. | ||
| 778 | * Slots that are not occupied will generate nothing. | ||
| 779 | */ | ||
| 780 | /* NB: the beacon interval is kept internally in TU's */ | ||
| 781 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | ||
| 782 | intval /= ATH_BCBUF; /* for staggered beacons */ | ||
| 783 | } else { | ||
| 784 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | ||
| 785 | } | ||
| 786 | |||
| 787 | if (nexttbtt == 0) /* e.g. for ap mode */ | ||
| 788 | nexttbtt = intval; | ||
| 789 | else if (intval) /* NB: can be 0 for monitor mode */ | ||
| 790 | nexttbtt = roundup(nexttbtt, intval); | ||
| 791 | DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", | ||
| 792 | __func__, nexttbtt, intval, conf.beacon_interval); | ||
| 793 | /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */ | ||
| 794 | if (sc->sc_opmode == ATH9K_M_STA) { | ||
| 795 | struct ath9k_beacon_state bs; | ||
| 796 | u64 tsf; | ||
| 797 | u32 tsftu; | ||
| 798 | int dtimperiod, dtimcount, sleepduration; | ||
| 799 | int cfpperiod, cfpcount; | ||
| 800 | |||
| 801 | /* | ||
| 802 | * Setup dtim and cfp parameters according to | ||
| 803 | * last beacon we received (which may be none). | ||
| 804 | */ | ||
| 805 | dtimperiod = conf.dtim_period; | ||
| 806 | if (dtimperiod <= 0) /* NB: 0 if not known */ | ||
| 807 | dtimperiod = 1; | ||
| 808 | dtimcount = conf.dtim_count; | ||
| 809 | if (dtimcount >= dtimperiod) /* NB: sanity check */ | ||
| 810 | dtimcount = 0; /* XXX? */ | ||
| 811 | cfpperiod = 1; /* NB: no PCF support yet */ | ||
| 812 | cfpcount = 0; | ||
| 813 | |||
| 814 | sleepduration = conf.listen_interval * intval; | ||
| 815 | if (sleepduration <= 0) | ||
| 816 | sleepduration = intval; | ||
| 817 | |||
| 818 | #define FUDGE 2 | ||
| 819 | /* | ||
| 820 | * Pull nexttbtt forward to reflect the current | ||
| 821 | * TSF and calculate dtim+cfp state for the result. | ||
| 822 | */ | ||
| 823 | tsf = ath9k_hw_gettsf64(ah); | ||
| 824 | tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; | ||
| 825 | do { | ||
| 826 | nexttbtt += intval; | ||
| 827 | if (--dtimcount < 0) { | ||
| 828 | dtimcount = dtimperiod - 1; | ||
| 829 | if (--cfpcount < 0) | ||
| 830 | cfpcount = cfpperiod - 1; | ||
| 831 | } | ||
| 832 | } while (nexttbtt < tsftu); | ||
| 833 | #undef FUDGE | ||
| 834 | memzero(&bs, sizeof(bs)); | ||
| 835 | bs.bs_intval = intval; | ||
| 836 | bs.bs_nexttbtt = nexttbtt; | ||
| 837 | bs.bs_dtimperiod = dtimperiod*intval; | ||
| 838 | bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; | ||
| 839 | bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; | ||
| 840 | bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; | ||
| 841 | bs.bs_cfpmaxduration = 0; | ||
| 842 | /* | ||
| 843 | * Calculate the number of consecutive beacons to miss | ||
| 844 | * before taking a BMISS interrupt. The configuration | ||
| 845 | * is specified in TU so we only need calculate based | ||
| 846 | * on the beacon interval. Note that we clamp the | ||
| 847 | * result to at most 15 beacons. | ||
| 848 | */ | ||
| 849 | if (sleepduration > intval) { | ||
| 850 | bs.bs_bmissthreshold = | ||
| 851 | conf.listen_interval * | ||
| 852 | ATH_DEFAULT_BMISS_LIMIT / 2; | ||
| 853 | } else { | ||
| 854 | bs.bs_bmissthreshold = | ||
| 855 | DIV_ROUND_UP(conf.bmiss_timeout, intval); | ||
| 856 | if (bs.bs_bmissthreshold > 15) | ||
| 857 | bs.bs_bmissthreshold = 15; | ||
| 858 | else if (bs.bs_bmissthreshold <= 0) | ||
| 859 | bs.bs_bmissthreshold = 1; | ||
| 860 | } | ||
| 861 | |||
| 862 | /* | ||
| 863 | * Calculate sleep duration. The configuration is | ||
| 864 | * given in ms. We insure a multiple of the beacon | ||
| 865 | * period is used. Also, if the sleep duration is | ||
| 866 | * greater than the DTIM period then it makes senses | ||
| 867 | * to make it a multiple of that. | ||
| 868 | * | ||
| 869 | * XXX fixed at 100ms | ||
| 870 | */ | ||
| 871 | |||
| 872 | bs.bs_sleepduration = | ||
| 873 | roundup(IEEE80211_MS_TO_TU(100), sleepduration); | ||
| 874 | if (bs.bs_sleepduration > bs.bs_dtimperiod) | ||
| 875 | bs.bs_sleepduration = bs.bs_dtimperiod; | ||
| 876 | |||
| 877 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 878 | "%s: tsf %llu " | ||
| 879 | "tsf:tu %u " | ||
| 880 | "intval %u " | ||
| 881 | "nexttbtt %u " | ||
| 882 | "dtim %u " | ||
| 883 | "nextdtim %u " | ||
| 884 | "bmiss %u " | ||
| 885 | "sleep %u " | ||
| 886 | "cfp:period %u " | ||
| 887 | "maxdur %u " | ||
| 888 | "next %u " | ||
| 889 | "timoffset %u\n" | ||
| 890 | , __func__ | ||
| 891 | , (unsigned long long)tsf, tsftu | ||
| 892 | , bs.bs_intval | ||
| 893 | , bs.bs_nexttbtt | ||
| 894 | , bs.bs_dtimperiod | ||
| 895 | , bs.bs_nextdtim | ||
| 896 | , bs.bs_bmissthreshold | ||
| 897 | , bs.bs_sleepduration | ||
| 898 | , bs.bs_cfpperiod | ||
| 899 | , bs.bs_cfpmaxduration | ||
| 900 | , bs.bs_cfpnext | ||
| 901 | , bs.bs_timoffset | ||
| 902 | ); | ||
| 903 | |||
| 904 | ath9k_hw_set_interrupts(ah, 0); | ||
| 905 | ath9k_hw_set_sta_beacon_timers(ah, &bs); | ||
| 906 | sc->sc_imask |= ATH9K_INT_BMISS; | ||
| 907 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | ||
| 908 | } else { | ||
| 909 | u64 tsf; | ||
| 910 | u32 tsftu; | ||
| 911 | ath9k_hw_set_interrupts(ah, 0); | ||
| 912 | if (nexttbtt == intval) | ||
| 913 | intval |= ATH9K_BEACON_RESET_TSF; | ||
| 914 | if (sc->sc_opmode == ATH9K_M_IBSS) { | ||
| 915 | /* | ||
| 916 | * Pull nexttbtt forward to reflect the current | ||
| 917 | * TSF . | ||
| 918 | */ | ||
| 919 | #define FUDGE 2 | ||
| 920 | if (!(intval & ATH9K_BEACON_RESET_TSF)) { | ||
| 921 | tsf = ath9k_hw_gettsf64(ah); | ||
| 922 | tsftu = TSF_TO_TU((u32)(tsf>>32), | ||
| 923 | (u32)tsf) + FUDGE; | ||
| 924 | do { | ||
| 925 | nexttbtt += intval; | ||
| 926 | } while (nexttbtt < tsftu); | ||
| 927 | } | ||
| 928 | #undef FUDGE | ||
| 929 | DPRINTF(sc, ATH_DBG_BEACON, | ||
| 930 | "%s: IBSS nexttbtt %u intval %u (%u)\n", | ||
| 931 | __func__, nexttbtt, | ||
| 932 | intval & ~ATH9K_BEACON_RESET_TSF, | ||
| 933 | conf.beacon_interval); | ||
| 934 | |||
| 935 | /* | ||
| 936 | * In IBSS mode enable the beacon timers but only | ||
| 937 | * enable SWBA interrupts if we need to manually | ||
| 938 | * prepare beacon frames. Otherwise we use a | ||
| 939 | * self-linked tx descriptor and let the hardware | ||
| 940 | * deal with things. | ||
| 941 | */ | ||
| 942 | intval |= ATH9K_BEACON_ENA; | ||
| 943 | if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) | ||
| 944 | sc->sc_imask |= ATH9K_INT_SWBA; | ||
| 945 | ath_beaconq_config(sc); | ||
| 946 | } else if (sc->sc_opmode == ATH9K_M_HOSTAP) { | ||
| 947 | /* | ||
| 948 | * In AP mode we enable the beacon timers and | ||
| 949 | * SWBA interrupts to prepare beacon frames. | ||
| 950 | */ | ||
| 951 | intval |= ATH9K_BEACON_ENA; | ||
| 952 | sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */ | ||
| 953 | ath_beaconq_config(sc); | ||
| 954 | } | ||
| 955 | ath9k_hw_beaconinit(ah, nexttbtt, intval); | ||
| 956 | sc->sc_bmisscount = 0; | ||
| 957 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | ||
| 958 | /* | ||
| 959 | * When using a self-linked beacon descriptor in | ||
| 960 | * ibss mode load it once here. | ||
| 961 | */ | ||
| 962 | if (sc->sc_opmode == ATH9K_M_IBSS && | ||
| 963 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) | ||
| 964 | ath_beacon_start_adhoc(sc, 0); | ||
| 965 | } | ||
| 966 | #undef TSF_TO_TU | ||
| 967 | } | ||
| 968 | |||
| 969 | /* Function to collect beacon rssi data and resync beacon if necessary */ | ||
| 970 | |||
| 971 | void ath_beacon_sync(struct ath_softc *sc, int if_id) | ||
| 972 | { | ||
| 973 | /* | ||
| 974 | * Resync beacon timers using the tsf of the | ||
| 975 | * beacon frame we just received. | ||
| 976 | */ | ||
| 977 | ath_beacon_config(sc, if_id); | ||
| 978 | sc->sc_beacons = 1; | ||
| 979 | } | ||
diff --git a/drivers/net/wireless/ath9k/core.c b/drivers/net/wireless/ath9k/core.c new file mode 100644 index 000000000000..f6c45288d0e7 --- /dev/null +++ b/drivers/net/wireless/ath9k/core.c | |||
| @@ -0,0 +1,1923 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008, Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* Implementation of the main "ATH" layer. */ | ||
| 18 | |||
| 19 | #include "core.h" | ||
| 20 | #include "regd.h" | ||
| 21 | |||
| 22 | static int ath_outdoor; /* enable outdoor use */ | ||
| 23 | |||
| 24 | static const u8 ath_bcast_mac[ETH_ALEN] = | ||
| 25 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | ||
| 26 | |||
| 27 | static u32 ath_chainmask_sel_up_rssi_thres = | ||
| 28 | ATH_CHAINMASK_SEL_UP_RSSI_THRES; | ||
| 29 | static u32 ath_chainmask_sel_down_rssi_thres = | ||
| 30 | ATH_CHAINMASK_SEL_DOWN_RSSI_THRES; | ||
| 31 | static u32 ath_chainmask_sel_period = | ||
| 32 | ATH_CHAINMASK_SEL_TIMEOUT; | ||
| 33 | |||
| 34 | /* return bus cachesize in 4B word units */ | ||
| 35 | |||
| 36 | static void bus_read_cachesize(struct ath_softc *sc, int *csz) | ||
| 37 | { | ||
| 38 | u8 u8tmp; | ||
| 39 | |||
| 40 | pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp); | ||
| 41 | *csz = (int)u8tmp; | ||
| 42 | |||
| 43 | /* | ||
| 44 | * This check was put in to avoid "unplesant" consequences if | ||
| 45 | * the bootrom has not fully initialized all PCI devices. | ||
| 46 | * Sometimes the cache line size register is not set | ||
| 47 | */ | ||
| 48 | |||
| 49 | if (*csz == 0) | ||
| 50 | *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ | ||
| 51 | } | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Set current operating mode | ||
| 55 | * | ||
| 56 | * This function initializes and fills the rate table in the ATH object based | ||
| 57 | * on the operating mode. The blink rates are also set up here, although | ||
| 58 | * they have been superceeded by the ath_led module. | ||
| 59 | */ | ||
| 60 | |||
| 61 | static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode) | ||
| 62 | { | ||
| 63 | const struct ath9k_rate_table *rt; | ||
| 64 | int i; | ||
| 65 | |||
| 66 | memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); | ||
| 67 | rt = ath9k_hw_getratetable(sc->sc_ah, mode); | ||
| 68 | BUG_ON(!rt); | ||
| 69 | |||
| 70 | for (i = 0; i < rt->rateCount; i++) | ||
| 71 | sc->sc_rixmap[rt->info[i].rateCode] = (u8) i; | ||
| 72 | |||
| 73 | memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap)); | ||
| 74 | for (i = 0; i < 256; i++) { | ||
| 75 | u8 ix = rt->rateCodeToIndex[i]; | ||
| 76 | |||
| 77 | if (ix == 0xff) | ||
| 78 | continue; | ||
| 79 | |||
| 80 | sc->sc_hwmap[i].ieeerate = | ||
| 81 | rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; | ||
| 82 | sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps; | ||
| 83 | |||
| 84 | if (rt->info[ix].shortPreamble || | ||
| 85 | rt->info[ix].phy == PHY_OFDM) { | ||
| 86 | /* XXX: Handle this */ | ||
| 87 | } | ||
| 88 | |||
| 89 | /* NB: this uses the last entry if the rate isn't found */ | ||
| 90 | /* XXX beware of overlow */ | ||
| 91 | } | ||
| 92 | sc->sc_currates = rt; | ||
| 93 | sc->sc_curmode = mode; | ||
| 94 | /* | ||
| 95 | * All protection frames are transmited at 2Mb/s for | ||
| 96 | * 11g, otherwise at 1Mb/s. | ||
| 97 | * XXX select protection rate index from rate table. | ||
| 98 | */ | ||
| 99 | sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0); | ||
| 100 | } | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Set up rate table (legacy rates) | ||
| 104 | */ | ||
| 105 | static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) | ||
| 106 | { | ||
| 107 | struct ath_hal *ah = sc->sc_ah; | ||
| 108 | const struct ath9k_rate_table *rt = NULL; | ||
| 109 | struct ieee80211_supported_band *sband; | ||
| 110 | struct ieee80211_rate *rate; | ||
| 111 | int i, maxrates; | ||
| 112 | |||
| 113 | switch (band) { | ||
| 114 | case IEEE80211_BAND_2GHZ: | ||
| 115 | rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11G); | ||
| 116 | break; | ||
| 117 | case IEEE80211_BAND_5GHZ: | ||
| 118 | rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11A); | ||
| 119 | break; | ||
| 120 | default: | ||
| 121 | break; | ||
| 122 | } | ||
| 123 | |||
| 124 | if (rt == NULL) | ||
| 125 | return; | ||
| 126 | |||
| 127 | sband = &sc->sbands[band]; | ||
| 128 | rate = sc->rates[band]; | ||
| 129 | |||
| 130 | if (rt->rateCount > ATH_RATE_MAX) | ||
| 131 | maxrates = ATH_RATE_MAX; | ||
| 132 | else | ||
| 133 | maxrates = rt->rateCount; | ||
| 134 | |||
| 135 | for (i = 0; i < maxrates; i++) { | ||
| 136 | rate[i].bitrate = rt->info[i].rateKbps / 100; | ||
| 137 | rate[i].hw_value = rt->info[i].rateCode; | ||
| 138 | sband->n_bitrates++; | ||
| 139 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 140 | "%s: Rate: %2dMbps, ratecode: %2d\n", | ||
| 141 | __func__, | ||
| 142 | rate[i].bitrate / 10, | ||
| 143 | rate[i].hw_value); | ||
| 144 | } | ||
| 145 | } | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Set up channel list | ||
| 149 | */ | ||
| 150 | static int ath_setup_channels(struct ath_softc *sc) | ||
| 151 | { | ||
| 152 | struct ath_hal *ah = sc->sc_ah; | ||
| 153 | int nchan, i, a = 0, b = 0; | ||
| 154 | u8 regclassids[ATH_REGCLASSIDS_MAX]; | ||
| 155 | u32 nregclass = 0; | ||
| 156 | struct ieee80211_supported_band *band_2ghz; | ||
| 157 | struct ieee80211_supported_band *band_5ghz; | ||
| 158 | struct ieee80211_channel *chan_2ghz; | ||
| 159 | struct ieee80211_channel *chan_5ghz; | ||
| 160 | struct ath9k_channel *c; | ||
| 161 | |||
| 162 | /* Fill in ah->ah_channels */ | ||
| 163 | if (!ath9k_regd_init_channels(ah, | ||
| 164 | ATH_CHAN_MAX, | ||
| 165 | (u32 *)&nchan, | ||
| 166 | regclassids, | ||
| 167 | ATH_REGCLASSIDS_MAX, | ||
| 168 | &nregclass, | ||
| 169 | CTRY_DEFAULT, | ||
| 170 | false, | ||
| 171 | 1)) { | ||
| 172 | u32 rd = ah->ah_currentRD; | ||
| 173 | |||
| 174 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 175 | "%s: unable to collect channel list; " | ||
| 176 | "regdomain likely %u country code %u\n", | ||
| 177 | __func__, rd, CTRY_DEFAULT); | ||
| 178 | return -EINVAL; | ||
| 179 | } | ||
| 180 | |||
| 181 | band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ]; | ||
| 182 | band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ]; | ||
| 183 | chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ]; | ||
| 184 | chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ]; | ||
| 185 | |||
| 186 | for (i = 0; i < nchan; i++) { | ||
| 187 | c = &ah->ah_channels[i]; | ||
| 188 | if (IS_CHAN_2GHZ(c)) { | ||
| 189 | chan_2ghz[a].band = IEEE80211_BAND_2GHZ; | ||
| 190 | chan_2ghz[a].center_freq = c->channel; | ||
| 191 | chan_2ghz[a].max_power = c->maxTxPower; | ||
| 192 | |||
| 193 | if (c->privFlags & CHANNEL_DISALLOW_ADHOC) | ||
| 194 | chan_2ghz[a].flags |= | ||
| 195 | IEEE80211_CHAN_NO_IBSS; | ||
| 196 | if (c->channelFlags & CHANNEL_PASSIVE) | ||
| 197 | chan_2ghz[a].flags |= | ||
| 198 | IEEE80211_CHAN_PASSIVE_SCAN; | ||
| 199 | |||
| 200 | band_2ghz->n_channels = ++a; | ||
| 201 | |||
| 202 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 203 | "%s: 2MHz channel: %d, " | ||
| 204 | "channelFlags: 0x%x\n", | ||
| 205 | __func__, | ||
| 206 | c->channel, | ||
| 207 | c->channelFlags); | ||
| 208 | } else if (IS_CHAN_5GHZ(c)) { | ||
| 209 | chan_5ghz[b].band = IEEE80211_BAND_5GHZ; | ||
| 210 | chan_5ghz[b].center_freq = c->channel; | ||
| 211 | chan_5ghz[b].max_power = c->maxTxPower; | ||
| 212 | |||
| 213 | if (c->privFlags & CHANNEL_DISALLOW_ADHOC) | ||
| 214 | chan_5ghz[b].flags |= | ||
| 215 | IEEE80211_CHAN_NO_IBSS; | ||
| 216 | if (c->channelFlags & CHANNEL_PASSIVE) | ||
| 217 | chan_5ghz[b].flags |= | ||
| 218 | IEEE80211_CHAN_PASSIVE_SCAN; | ||
| 219 | |||
| 220 | band_5ghz->n_channels = ++b; | ||
| 221 | |||
| 222 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 223 | "%s: 5MHz channel: %d, " | ||
| 224 | "channelFlags: 0x%x\n", | ||
| 225 | __func__, | ||
| 226 | c->channel, | ||
| 227 | c->channelFlags); | ||
| 228 | } | ||
| 229 | } | ||
| 230 | |||
| 231 | return 0; | ||
| 232 | } | ||
| 233 | |||
| 234 | /* | ||
| 235 | * Determine mode from channel flags | ||
| 236 | * | ||
| 237 | * This routine will provide the enumerated WIRELESSS_MODE value based | ||
| 238 | * on the settings of the channel flags. If ho valid set of flags | ||
| 239 | * exist, the lowest mode (11b) is selected. | ||
| 240 | */ | ||
| 241 | |||
| 242 | static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan) | ||
| 243 | { | ||
| 244 | if (chan->chanmode == CHANNEL_A) | ||
| 245 | return ATH9K_MODE_11A; | ||
| 246 | else if (chan->chanmode == CHANNEL_G) | ||
| 247 | return ATH9K_MODE_11G; | ||
| 248 | else if (chan->chanmode == CHANNEL_B) | ||
| 249 | return ATH9K_MODE_11B; | ||
| 250 | else if (chan->chanmode == CHANNEL_A_HT20) | ||
| 251 | return ATH9K_MODE_11NA_HT20; | ||
| 252 | else if (chan->chanmode == CHANNEL_G_HT20) | ||
| 253 | return ATH9K_MODE_11NG_HT20; | ||
| 254 | else if (chan->chanmode == CHANNEL_A_HT40PLUS) | ||
| 255 | return ATH9K_MODE_11NA_HT40PLUS; | ||
| 256 | else if (chan->chanmode == CHANNEL_A_HT40MINUS) | ||
| 257 | return ATH9K_MODE_11NA_HT40MINUS; | ||
| 258 | else if (chan->chanmode == CHANNEL_G_HT40PLUS) | ||
| 259 | return ATH9K_MODE_11NG_HT40PLUS; | ||
| 260 | else if (chan->chanmode == CHANNEL_G_HT40MINUS) | ||
| 261 | return ATH9K_MODE_11NG_HT40MINUS; | ||
| 262 | |||
| 263 | /* NB: should not get here */ | ||
| 264 | return ATH9K_MODE_11B; | ||
| 265 | } | ||
| 266 | |||
| 267 | /* | ||
| 268 | * Stop the device, grabbing the top-level lock to protect | ||
| 269 | * against concurrent entry through ath_init (which can happen | ||
| 270 | * if another thread does a system call and the thread doing the | ||
| 271 | * stop is preempted). | ||
| 272 | */ | ||
| 273 | |||
| 274 | static int ath_stop(struct ath_softc *sc) | ||
| 275 | { | ||
| 276 | struct ath_hal *ah = sc->sc_ah; | ||
| 277 | |||
| 278 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n", | ||
| 279 | __func__, sc->sc_invalid); | ||
| 280 | |||
| 281 | /* | ||
| 282 | * Shutdown the hardware and driver: | ||
| 283 | * stop output from above | ||
| 284 | * reset 802.11 state machine | ||
| 285 | * (sends station deassoc/deauth frames) | ||
| 286 | * turn off timers | ||
| 287 | * disable interrupts | ||
| 288 | * clear transmit machinery | ||
| 289 | * clear receive machinery | ||
| 290 | * turn off the radio | ||
| 291 | * reclaim beacon resources | ||
| 292 | * | ||
| 293 | * Note that some of this work is not possible if the | ||
| 294 | * hardware is gone (invalid). | ||
| 295 | */ | ||
| 296 | |||
| 297 | if (!sc->sc_invalid) | ||
| 298 | ath9k_hw_set_interrupts(ah, 0); | ||
| 299 | ath_draintxq(sc, false); | ||
| 300 | if (!sc->sc_invalid) { | ||
| 301 | ath_stoprecv(sc); | ||
| 302 | ath9k_hw_phy_disable(ah); | ||
| 303 | } else | ||
| 304 | sc->sc_rxlink = NULL; | ||
| 305 | |||
| 306 | return 0; | ||
| 307 | } | ||
| 308 | |||
| 309 | /* | ||
| 310 | * Start Scan | ||
| 311 | * | ||
| 312 | * This function is called when starting a channel scan. It will perform | ||
| 313 | * power save wakeup processing, set the filter for the scan, and get the | ||
| 314 | * chip ready to send broadcast packets out during the scan. | ||
| 315 | */ | ||
| 316 | |||
| 317 | void ath_scan_start(struct ath_softc *sc) | ||
| 318 | { | ||
| 319 | struct ath_hal *ah = sc->sc_ah; | ||
| 320 | u32 rfilt; | ||
| 321 | u32 now = (u32) jiffies_to_msecs(get_timestamp()); | ||
| 322 | |||
| 323 | sc->sc_scanning = 1; | ||
| 324 | rfilt = ath_calcrxfilter(sc); | ||
| 325 | ath9k_hw_setrxfilter(ah, rfilt); | ||
| 326 | ath9k_hw_write_associd(ah, ath_bcast_mac, 0); | ||
| 327 | |||
| 328 | /* Restore previous power management state. */ | ||
| 329 | |||
| 330 | DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n", | ||
| 331 | now / 1000, now % 1000, __func__, rfilt); | ||
| 332 | } | ||
| 333 | |||
| 334 | /* | ||
| 335 | * Scan End | ||
| 336 | * | ||
| 337 | * This routine is called by the upper layer when the scan is completed. This | ||
| 338 | * will set the filters back to normal operating mode, set the BSSID to the | ||
| 339 | * correct value, and restore the power save state. | ||
| 340 | */ | ||
| 341 | |||
| 342 | void ath_scan_end(struct ath_softc *sc) | ||
| 343 | { | ||
| 344 | struct ath_hal *ah = sc->sc_ah; | ||
| 345 | u32 rfilt; | ||
| 346 | u32 now = (u32) jiffies_to_msecs(get_timestamp()); | ||
| 347 | |||
| 348 | sc->sc_scanning = 0; | ||
| 349 | /* Request for a full reset due to rx packet filter changes */ | ||
| 350 | sc->sc_full_reset = 1; | ||
| 351 | rfilt = ath_calcrxfilter(sc); | ||
| 352 | ath9k_hw_setrxfilter(ah, rfilt); | ||
| 353 | ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid); | ||
| 354 | |||
| 355 | DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n", | ||
| 356 | now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid); | ||
| 357 | } | ||
| 358 | |||
| 359 | /* | ||
| 360 | * Set the current channel | ||
| 361 | * | ||
| 362 | * Set/change channels. If the channel is really being changed, it's done | ||
| 363 | * by reseting the chip. To accomplish this we must first cleanup any pending | ||
| 364 | * DMA, then restart stuff after a la ath_init. | ||
| 365 | */ | ||
| 366 | int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) | ||
| 367 | { | ||
| 368 | struct ath_hal *ah = sc->sc_ah; | ||
| 369 | bool fastcc = true, stopped; | ||
| 370 | enum ath9k_ht_macmode ht_macmode; | ||
| 371 | |||
| 372 | if (sc->sc_invalid) /* if the device is invalid or removed */ | ||
| 373 | return -EIO; | ||
| 374 | |||
| 375 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 376 | "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n", | ||
| 377 | __func__, | ||
| 378 | ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel, | ||
| 379 | sc->sc_curchan.channelFlags), | ||
| 380 | sc->sc_curchan.channel, | ||
| 381 | ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags), | ||
| 382 | hchan->channel, hchan->channelFlags); | ||
| 383 | |||
| 384 | ht_macmode = ath_cwm_macmode(sc); | ||
| 385 | |||
| 386 | if (hchan->channel != sc->sc_curchan.channel || | ||
| 387 | hchan->channelFlags != sc->sc_curchan.channelFlags || | ||
| 388 | sc->sc_update_chainmask || sc->sc_full_reset) { | ||
| 389 | int status; | ||
| 390 | /* | ||
| 391 | * This is only performed if the channel settings have | ||
| 392 | * actually changed. | ||
| 393 | * | ||
| 394 | * To switch channels clear any pending DMA operations; | ||
| 395 | * wait long enough for the RX fifo to drain, reset the | ||
| 396 | * hardware at the new frequency, and then re-enable | ||
| 397 | * the relevant bits of the h/w. | ||
| 398 | */ | ||
| 399 | ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */ | ||
| 400 | ath_draintxq(sc, false); /* clear pending tx frames */ | ||
| 401 | stopped = ath_stoprecv(sc); /* turn off frame recv */ | ||
| 402 | |||
| 403 | /* XXX: do not flush receive queue here. We don't want | ||
| 404 | * to flush data frames already in queue because of | ||
| 405 | * changing channel. */ | ||
| 406 | |||
| 407 | if (!stopped || sc->sc_full_reset) | ||
| 408 | fastcc = false; | ||
| 409 | |||
| 410 | spin_lock_bh(&sc->sc_resetlock); | ||
| 411 | if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan, | ||
| 412 | ht_macmode, sc->sc_tx_chainmask, | ||
| 413 | sc->sc_rx_chainmask, | ||
| 414 | sc->sc_ht_extprotspacing, | ||
| 415 | fastcc, &status)) { | ||
| 416 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 417 | "%s: unable to reset channel %u (%uMhz) " | ||
| 418 | "flags 0x%x hal status %u\n", __func__, | ||
| 419 | ath9k_hw_mhz2ieee(ah, hchan->channel, | ||
| 420 | hchan->channelFlags), | ||
| 421 | hchan->channel, hchan->channelFlags, status); | ||
| 422 | spin_unlock_bh(&sc->sc_resetlock); | ||
| 423 | return -EIO; | ||
| 424 | } | ||
| 425 | spin_unlock_bh(&sc->sc_resetlock); | ||
| 426 | |||
| 427 | sc->sc_curchan = *hchan; | ||
| 428 | sc->sc_update_chainmask = 0; | ||
| 429 | sc->sc_full_reset = 0; | ||
| 430 | |||
| 431 | /* Re-enable rx framework */ | ||
| 432 | if (ath_startrecv(sc) != 0) { | ||
| 433 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 434 | "%s: unable to restart recv logic\n", __func__); | ||
| 435 | return -EIO; | ||
| 436 | } | ||
| 437 | /* | ||
| 438 | * Change channels and update the h/w rate map | ||
| 439 | * if we're switching; e.g. 11a to 11b/g. | ||
| 440 | */ | ||
| 441 | ath_setcurmode(sc, ath_chan2mode(hchan)); | ||
| 442 | |||
| 443 | ath_update_txpow(sc); /* update tx power state */ | ||
| 444 | /* | ||
| 445 | * Re-enable interrupts. | ||
| 446 | */ | ||
| 447 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | ||
| 448 | } | ||
| 449 | return 0; | ||
| 450 | } | ||
| 451 | |||
| 452 | /**********************/ | ||
| 453 | /* Chainmask Handling */ | ||
| 454 | /**********************/ | ||
| 455 | |||
| 456 | static void ath_chainmask_sel_timertimeout(unsigned long data) | ||
| 457 | { | ||
| 458 | struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data; | ||
| 459 | cm->switch_allowed = 1; | ||
| 460 | } | ||
| 461 | |||
| 462 | /* Start chainmask select timer */ | ||
| 463 | static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm) | ||
| 464 | { | ||
| 465 | cm->switch_allowed = 0; | ||
| 466 | mod_timer(&cm->timer, ath_chainmask_sel_period); | ||
| 467 | } | ||
| 468 | |||
| 469 | /* Stop chainmask select timer */ | ||
| 470 | static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm) | ||
| 471 | { | ||
| 472 | cm->switch_allowed = 0; | ||
| 473 | del_timer_sync(&cm->timer); | ||
| 474 | } | ||
| 475 | |||
| 476 | static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an) | ||
| 477 | { | ||
| 478 | struct ath_chainmask_sel *cm = &an->an_chainmask_sel; | ||
| 479 | |||
| 480 | memzero(cm, sizeof(struct ath_chainmask_sel)); | ||
| 481 | |||
| 482 | cm->cur_tx_mask = sc->sc_tx_chainmask; | ||
| 483 | cm->cur_rx_mask = sc->sc_rx_chainmask; | ||
| 484 | cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER; | ||
| 485 | setup_timer(&cm->timer, | ||
| 486 | ath_chainmask_sel_timertimeout, (unsigned long) cm); | ||
| 487 | } | ||
| 488 | |||
| 489 | int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an) | ||
| 490 | { | ||
| 491 | struct ath_chainmask_sel *cm = &an->an_chainmask_sel; | ||
| 492 | |||
| 493 | /* | ||
| 494 | * Disable auto-swtiching in one of the following if conditions. | ||
| 495 | * sc_chainmask_auto_sel is used for internal global auto-switching | ||
| 496 | * enabled/disabled setting | ||
| 497 | */ | ||
| 498 | if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) { | ||
| 499 | cm->cur_tx_mask = sc->sc_tx_chainmask; | ||
| 500 | return cm->cur_tx_mask; | ||
| 501 | } | ||
| 502 | |||
| 503 | if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER) | ||
| 504 | return cm->cur_tx_mask; | ||
| 505 | |||
| 506 | if (cm->switch_allowed) { | ||
| 507 | /* Switch down from tx 3 to tx 2. */ | ||
| 508 | if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 && | ||
| 509 | ATH_RSSI_OUT(cm->tx_avgrssi) >= | ||
| 510 | ath_chainmask_sel_down_rssi_thres) { | ||
| 511 | cm->cur_tx_mask = sc->sc_tx_chainmask; | ||
| 512 | |||
| 513 | /* Don't let another switch happen until | ||
| 514 | * this timer expires */ | ||
| 515 | ath_chainmask_sel_timerstart(cm); | ||
| 516 | } | ||
| 517 | /* Switch up from tx 2 to 3. */ | ||
| 518 | else if (cm->cur_tx_mask == sc->sc_tx_chainmask && | ||
| 519 | ATH_RSSI_OUT(cm->tx_avgrssi) <= | ||
| 520 | ath_chainmask_sel_up_rssi_thres) { | ||
| 521 | cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3; | ||
| 522 | |||
| 523 | /* Don't let another switch happen | ||
| 524 | * until this timer expires */ | ||
| 525 | ath_chainmask_sel_timerstart(cm); | ||
| 526 | } | ||
| 527 | } | ||
| 528 | |||
| 529 | return cm->cur_tx_mask; | ||
| 530 | } | ||
| 531 | |||
| 532 | /* | ||
| 533 | * Update tx/rx chainmask. For legacy association, | ||
| 534 | * hard code chainmask to 1x1, for 11n association, use | ||
| 535 | * the chainmask configuration. | ||
| 536 | */ | ||
| 537 | |||
| 538 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) | ||
| 539 | { | ||
| 540 | sc->sc_update_chainmask = 1; | ||
| 541 | if (is_ht) { | ||
| 542 | sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; | ||
| 543 | sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; | ||
| 544 | } else { | ||
| 545 | sc->sc_tx_chainmask = 1; | ||
| 546 | sc->sc_rx_chainmask = 1; | ||
| 547 | } | ||
| 548 | |||
| 549 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n", | ||
| 550 | __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask); | ||
| 551 | } | ||
| 552 | |||
| 553 | /******************/ | ||
| 554 | /* VAP management */ | ||
| 555 | /******************/ | ||
| 556 | |||
| 557 | /* | ||
| 558 | * VAP in Listen mode | ||
| 559 | * | ||
| 560 | * This routine brings the VAP out of the down state into a "listen" state | ||
| 561 | * where it waits for association requests. This is used in AP and AdHoc | ||
| 562 | * modes. | ||
| 563 | */ | ||
| 564 | |||
| 565 | int ath_vap_listen(struct ath_softc *sc, int if_id) | ||
| 566 | { | ||
| 567 | struct ath_hal *ah = sc->sc_ah; | ||
| 568 | struct ath_vap *avp; | ||
| 569 | u32 rfilt = 0; | ||
| 570 | DECLARE_MAC_BUF(mac); | ||
| 571 | |||
| 572 | avp = sc->sc_vaps[if_id]; | ||
| 573 | if (avp == NULL) { | ||
| 574 | DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n", | ||
| 575 | __func__, if_id); | ||
| 576 | return -EINVAL; | ||
| 577 | } | ||
| 578 | |||
| 579 | #ifdef CONFIG_SLOW_ANT_DIV | ||
| 580 | ath_slow_ant_div_stop(&sc->sc_antdiv); | ||
| 581 | #endif | ||
| 582 | |||
| 583 | /* update ratectrl about the new state */ | ||
| 584 | ath_rate_newstate(sc, avp); | ||
| 585 | |||
| 586 | rfilt = ath_calcrxfilter(sc); | ||
| 587 | ath9k_hw_setrxfilter(ah, rfilt); | ||
| 588 | |||
| 589 | if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) { | ||
| 590 | memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN); | ||
| 591 | ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid); | ||
| 592 | } else | ||
| 593 | sc->sc_curaid = 0; | ||
| 594 | |||
| 595 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 596 | "%s: RX filter 0x%x bssid %s aid 0x%x\n", | ||
| 597 | __func__, rfilt, print_mac(mac, | ||
| 598 | sc->sc_curbssid), sc->sc_curaid); | ||
| 599 | |||
| 600 | /* | ||
| 601 | * XXXX | ||
| 602 | * Disable BMISS interrupt when we're not associated | ||
| 603 | */ | ||
| 604 | ath9k_hw_set_interrupts(ah, | ||
| 605 | sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS)); | ||
| 606 | sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); | ||
| 607 | /* need to reconfigure the beacons when it moves to RUN */ | ||
| 608 | sc->sc_beacons = 0; | ||
| 609 | |||
| 610 | return 0; | ||
| 611 | } | ||
| 612 | |||
| 613 | int ath_vap_attach(struct ath_softc *sc, | ||
| 614 | int if_id, | ||
| 615 | struct ieee80211_vif *if_data, | ||
| 616 | enum ath9k_opmode opmode) | ||
| 617 | { | ||
| 618 | struct ath_vap *avp; | ||
| 619 | |||
| 620 | if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) { | ||
| 621 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 622 | "%s: Invalid interface id = %u\n", __func__, if_id); | ||
| 623 | return -EINVAL; | ||
| 624 | } | ||
| 625 | |||
| 626 | switch (opmode) { | ||
| 627 | case ATH9K_M_STA: | ||
| 628 | case ATH9K_M_IBSS: | ||
| 629 | case ATH9K_M_MONITOR: | ||
| 630 | break; | ||
| 631 | case ATH9K_M_HOSTAP: | ||
| 632 | /* XXX not right, beacon buffer is allocated on RUN trans */ | ||
| 633 | if (list_empty(&sc->sc_bbuf)) | ||
| 634 | return -ENOMEM; | ||
| 635 | break; | ||
| 636 | default: | ||
| 637 | return -EINVAL; | ||
| 638 | } | ||
| 639 | |||
| 640 | /* create ath_vap */ | ||
| 641 | avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL); | ||
| 642 | if (avp == NULL) | ||
| 643 | return -ENOMEM; | ||
| 644 | |||
| 645 | memzero(avp, sizeof(struct ath_vap)); | ||
| 646 | avp->av_if_data = if_data; | ||
| 647 | /* Set the VAP opmode */ | ||
| 648 | avp->av_opmode = opmode; | ||
| 649 | avp->av_bslot = -1; | ||
| 650 | INIT_LIST_HEAD(&avp->av_mcastq.axq_q); | ||
| 651 | INIT_LIST_HEAD(&avp->av_mcastq.axq_acq); | ||
| 652 | spin_lock_init(&avp->av_mcastq.axq_lock); | ||
| 653 | |||
| 654 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); | ||
| 655 | |||
| 656 | sc->sc_vaps[if_id] = avp; | ||
| 657 | sc->sc_nvaps++; | ||
| 658 | /* Set the device opmode */ | ||
| 659 | sc->sc_opmode = opmode; | ||
| 660 | |||
| 661 | /* default VAP configuration */ | ||
| 662 | avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE; | ||
| 663 | avp->av_config.av_fixed_retryset = 0x03030303; | ||
| 664 | |||
| 665 | return 0; | ||
| 666 | } | ||
| 667 | |||
| 668 | int ath_vap_detach(struct ath_softc *sc, int if_id) | ||
| 669 | { | ||
| 670 | struct ath_hal *ah = sc->sc_ah; | ||
| 671 | struct ath_vap *avp; | ||
| 672 | |||
| 673 | avp = sc->sc_vaps[if_id]; | ||
| 674 | if (avp == NULL) { | ||
| 675 | DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n", | ||
| 676 | __func__, if_id); | ||
| 677 | return -EINVAL; | ||
| 678 | } | ||
| 679 | |||
| 680 | /* | ||
| 681 | * Quiesce the hardware while we remove the vap. In | ||
| 682 | * particular we need to reclaim all references to the | ||
| 683 | * vap state by any frames pending on the tx queues. | ||
| 684 | * | ||
| 685 | * XXX can we do this w/o affecting other vap's? | ||
| 686 | */ | ||
| 687 | ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */ | ||
| 688 | ath_draintxq(sc, false); /* stop xmit side */ | ||
| 689 | ath_stoprecv(sc); /* stop recv side */ | ||
| 690 | ath_flushrecv(sc); /* flush recv queue */ | ||
| 691 | |||
| 692 | /* Reclaim any pending mcast bufs on the vap. */ | ||
| 693 | ath_tx_draintxq(sc, &avp->av_mcastq, false); | ||
| 694 | |||
| 695 | kfree(avp); | ||
| 696 | sc->sc_vaps[if_id] = NULL; | ||
| 697 | sc->sc_nvaps--; | ||
| 698 | |||
| 699 | return 0; | ||
| 700 | } | ||
| 701 | |||
| 702 | int ath_vap_config(struct ath_softc *sc, | ||
| 703 | int if_id, struct ath_vap_config *if_config) | ||
| 704 | { | ||
| 705 | struct ath_vap *avp; | ||
| 706 | |||
| 707 | if (if_id >= ATH_BCBUF) { | ||
| 708 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 709 | "%s: Invalid interface id = %u\n", __func__, if_id); | ||
| 710 | return -EINVAL; | ||
| 711 | } | ||
| 712 | |||
| 713 | avp = sc->sc_vaps[if_id]; | ||
| 714 | ASSERT(avp != NULL); | ||
| 715 | |||
| 716 | if (avp) | ||
| 717 | memcpy(&avp->av_config, if_config, sizeof(avp->av_config)); | ||
| 718 | |||
| 719 | return 0; | ||
| 720 | } | ||
| 721 | |||
| 722 | /********/ | ||
| 723 | /* Core */ | ||
| 724 | /********/ | ||
| 725 | |||
| 726 | int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan) | ||
| 727 | { | ||
| 728 | struct ath_hal *ah = sc->sc_ah; | ||
| 729 | int status; | ||
| 730 | int error = 0; | ||
| 731 | enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc); | ||
| 732 | |||
| 733 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode); | ||
| 734 | |||
| 735 | /* | ||
| 736 | * Stop anything previously setup. This is safe | ||
| 737 | * whether this is the first time through or not. | ||
| 738 | */ | ||
| 739 | ath_stop(sc); | ||
| 740 | |||
| 741 | /* Initialize chanmask selection */ | ||
| 742 | sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask; | ||
| 743 | sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; | ||
| 744 | |||
| 745 | /* Reset SERDES registers */ | ||
| 746 | ath9k_hw_configpcipowersave(ah, 0); | ||
| 747 | |||
| 748 | /* | ||
| 749 | * The basic interface to setting the hardware in a good | ||
| 750 | * state is ``reset''. On return the hardware is known to | ||
| 751 | * be powered up and with interrupts disabled. This must | ||
| 752 | * be followed by initialization of the appropriate bits | ||
| 753 | * and then setup of the interrupt mask. | ||
| 754 | */ | ||
| 755 | sc->sc_curchan = *initial_chan; | ||
| 756 | |||
| 757 | spin_lock_bh(&sc->sc_resetlock); | ||
| 758 | if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode, | ||
| 759 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, | ||
| 760 | sc->sc_ht_extprotspacing, false, &status)) { | ||
| 761 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 762 | "%s: unable to reset hardware; hal status %u " | ||
| 763 | "(freq %u flags 0x%x)\n", __func__, status, | ||
| 764 | sc->sc_curchan.channel, sc->sc_curchan.channelFlags); | ||
| 765 | error = -EIO; | ||
| 766 | spin_unlock_bh(&sc->sc_resetlock); | ||
| 767 | goto done; | ||
| 768 | } | ||
| 769 | spin_unlock_bh(&sc->sc_resetlock); | ||
| 770 | /* | ||
| 771 | * This is needed only to setup initial state | ||
| 772 | * but it's best done after a reset. | ||
| 773 | */ | ||
| 774 | ath_update_txpow(sc); | ||
| 775 | |||
| 776 | /* | ||
| 777 | * Setup the hardware after reset: | ||
| 778 | * The receive engine is set going. | ||
| 779 | * Frame transmit is handled entirely | ||
| 780 | * in the frame output path; there's nothing to do | ||
| 781 | * here except setup the interrupt mask. | ||
| 782 | */ | ||
| 783 | if (ath_startrecv(sc) != 0) { | ||
| 784 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 785 | "%s: unable to start recv logic\n", __func__); | ||
| 786 | error = -EIO; | ||
| 787 | goto done; | ||
| 788 | } | ||
| 789 | /* Setup our intr mask. */ | ||
| 790 | sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX | ||
| 791 | | ATH9K_INT_RXEOL | ATH9K_INT_RXORN | ||
| 792 | | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; | ||
| 793 | |||
| 794 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) | ||
| 795 | sc->sc_imask |= ATH9K_INT_GTT; | ||
| 796 | |||
| 797 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) | ||
| 798 | sc->sc_imask |= ATH9K_INT_CST; | ||
| 799 | |||
| 800 | /* | ||
| 801 | * Enable MIB interrupts when there are hardware phy counters. | ||
| 802 | * Note we only do this (at the moment) for station mode. | ||
| 803 | */ | ||
| 804 | if (ath9k_hw_phycounters(ah) && | ||
| 805 | ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS))) | ||
| 806 | sc->sc_imask |= ATH9K_INT_MIB; | ||
| 807 | /* | ||
| 808 | * Some hardware processes the TIM IE and fires an | ||
| 809 | * interrupt when the TIM bit is set. For hardware | ||
| 810 | * that does, if not overridden by configuration, | ||
| 811 | * enable the TIM interrupt when operating as station. | ||
| 812 | */ | ||
| 813 | if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && | ||
| 814 | (sc->sc_opmode == ATH9K_M_STA) && | ||
| 815 | !sc->sc_config.swBeaconProcess) | ||
| 816 | sc->sc_imask |= ATH9K_INT_TIM; | ||
| 817 | /* | ||
| 818 | * Don't enable interrupts here as we've not yet built our | ||
| 819 | * vap and node data structures, which will be needed as soon | ||
| 820 | * as we start receiving. | ||
| 821 | */ | ||
| 822 | ath_setcurmode(sc, ath_chan2mode(initial_chan)); | ||
| 823 | |||
| 824 | /* XXX: we must make sure h/w is ready and clear invalid flag | ||
| 825 | * before turning on interrupt. */ | ||
| 826 | sc->sc_invalid = 0; | ||
| 827 | done: | ||
| 828 | return error; | ||
| 829 | } | ||
| 830 | |||
| 831 | /* | ||
| 832 | * Reset the hardware w/o losing operational state. This is | ||
| 833 | * basically a more efficient way of doing ath_stop, ath_init, | ||
| 834 | * followed by state transitions to the current 802.11 | ||
| 835 | * operational state. Used to recover from errors rx overrun | ||
| 836 | * and to reset the hardware when rf gain settings must be reset. | ||
| 837 | */ | ||
| 838 | |||
| 839 | static int ath_reset_start(struct ath_softc *sc, u32 flag) | ||
| 840 | { | ||
| 841 | struct ath_hal *ah = sc->sc_ah; | ||
| 842 | |||
| 843 | ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */ | ||
| 844 | ath_draintxq(sc, flag & RESET_RETRY_TXQ); /* stop xmit side */ | ||
| 845 | ath_stoprecv(sc); /* stop recv side */ | ||
| 846 | ath_flushrecv(sc); /* flush recv queue */ | ||
| 847 | |||
| 848 | return 0; | ||
| 849 | } | ||
| 850 | |||
| 851 | static int ath_reset_end(struct ath_softc *sc, u32 flag) | ||
| 852 | { | ||
| 853 | struct ath_hal *ah = sc->sc_ah; | ||
| 854 | |||
| 855 | if (ath_startrecv(sc) != 0) /* restart recv */ | ||
| 856 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 857 | "%s: unable to start recv logic\n", __func__); | ||
| 858 | |||
| 859 | /* | ||
| 860 | * We may be doing a reset in response to a request | ||
| 861 | * that changes the channel so update any state that | ||
| 862 | * might change as a result. | ||
| 863 | */ | ||
| 864 | ath_setcurmode(sc, ath_chan2mode(&sc->sc_curchan)); | ||
| 865 | |||
| 866 | ath_update_txpow(sc); /* update tx power state */ | ||
| 867 | |||
| 868 | if (sc->sc_beacons) | ||
| 869 | ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */ | ||
| 870 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | ||
| 871 | |||
| 872 | /* Restart the txq */ | ||
| 873 | if (flag & RESET_RETRY_TXQ) { | ||
| 874 | int i; | ||
| 875 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | ||
| 876 | if (ATH_TXQ_SETUP(sc, i)) { | ||
| 877 | spin_lock_bh(&sc->sc_txq[i].axq_lock); | ||
| 878 | ath_txq_schedule(sc, &sc->sc_txq[i]); | ||
| 879 | spin_unlock_bh(&sc->sc_txq[i].axq_lock); | ||
| 880 | } | ||
| 881 | } | ||
| 882 | } | ||
| 883 | return 0; | ||
| 884 | } | ||
| 885 | |||
| 886 | int ath_reset(struct ath_softc *sc) | ||
| 887 | { | ||
| 888 | struct ath_hal *ah = sc->sc_ah; | ||
| 889 | int status; | ||
| 890 | int error = 0; | ||
| 891 | enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc); | ||
| 892 | |||
| 893 | /* NB: indicate channel change so we do a full reset */ | ||
| 894 | spin_lock_bh(&sc->sc_resetlock); | ||
| 895 | if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, | ||
| 896 | ht_macmode, | ||
| 897 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, | ||
| 898 | sc->sc_ht_extprotspacing, false, &status)) { | ||
| 899 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 900 | "%s: unable to reset hardware; hal status %u\n", | ||
| 901 | __func__, status); | ||
| 902 | error = -EIO; | ||
| 903 | } | ||
| 904 | spin_unlock_bh(&sc->sc_resetlock); | ||
| 905 | |||
| 906 | return error; | ||
| 907 | } | ||
| 908 | |||
| 909 | int ath_suspend(struct ath_softc *sc) | ||
| 910 | { | ||
| 911 | struct ath_hal *ah = sc->sc_ah; | ||
| 912 | |||
| 913 | /* No I/O if device has been surprise removed */ | ||
| 914 | if (sc->sc_invalid) | ||
| 915 | return -EIO; | ||
| 916 | |||
| 917 | /* Shut off the interrupt before setting sc->sc_invalid to '1' */ | ||
| 918 | ath9k_hw_set_interrupts(ah, 0); | ||
| 919 | |||
| 920 | /* XXX: we must make sure h/w will not generate any interrupt | ||
| 921 | * before setting the invalid flag. */ | ||
| 922 | sc->sc_invalid = 1; | ||
| 923 | |||
| 924 | /* disable HAL and put h/w to sleep */ | ||
| 925 | ath9k_hw_disable(sc->sc_ah); | ||
| 926 | |||
| 927 | ath9k_hw_configpcipowersave(sc->sc_ah, 1); | ||
| 928 | |||
| 929 | return 0; | ||
| 930 | } | ||
| 931 | |||
| 932 | /* Interrupt handler. Most of the actual processing is deferred. | ||
| 933 | * It's the caller's responsibility to ensure the chip is awake. */ | ||
| 934 | |||
| 935 | irqreturn_t ath_isr(int irq, void *dev) | ||
| 936 | { | ||
| 937 | struct ath_softc *sc = dev; | ||
| 938 | struct ath_hal *ah = sc->sc_ah; | ||
| 939 | enum ath9k_int status; | ||
| 940 | bool sched = false; | ||
| 941 | |||
| 942 | do { | ||
| 943 | if (sc->sc_invalid) { | ||
| 944 | /* | ||
| 945 | * The hardware is not ready/present, don't | ||
| 946 | * touch anything. Note this can happen early | ||
| 947 | * on if the IRQ is shared. | ||
| 948 | */ | ||
| 949 | return IRQ_NONE; | ||
| 950 | } | ||
| 951 | if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */ | ||
| 952 | return IRQ_NONE; | ||
| 953 | } | ||
| 954 | |||
| 955 | /* | ||
| 956 | * Figure out the reason(s) for the interrupt. Note | ||
| 957 | * that the hal returns a pseudo-ISR that may include | ||
| 958 | * bits we haven't explicitly enabled so we mask the | ||
| 959 | * value to insure we only process bits we requested. | ||
| 960 | */ | ||
| 961 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | ||
| 962 | |||
| 963 | status &= sc->sc_imask; /* discard unasked-for bits */ | ||
| 964 | |||
| 965 | /* | ||
| 966 | * If there are no status bits set, then this interrupt was not | ||
| 967 | * for me (should have been caught above). | ||
| 968 | */ | ||
| 969 | |||
| 970 | if (!status) | ||
| 971 | return IRQ_NONE; | ||
| 972 | |||
| 973 | sc->sc_intrstatus = status; | ||
| 974 | |||
| 975 | if (status & ATH9K_INT_FATAL) { | ||
| 976 | /* need a chip reset */ | ||
| 977 | sched = true; | ||
| 978 | } else if (status & ATH9K_INT_RXORN) { | ||
| 979 | /* need a chip reset */ | ||
| 980 | sched = true; | ||
| 981 | } else { | ||
| 982 | if (status & ATH9K_INT_SWBA) { | ||
| 983 | /* schedule a tasklet for beacon handling */ | ||
| 984 | tasklet_schedule(&sc->bcon_tasklet); | ||
| 985 | } | ||
| 986 | if (status & ATH9K_INT_RXEOL) { | ||
| 987 | /* | ||
| 988 | * NB: the hardware should re-read the link when | ||
| 989 | * RXE bit is written, but it doesn't work | ||
| 990 | * at least on older hardware revs. | ||
| 991 | */ | ||
| 992 | sched = true; | ||
| 993 | } | ||
| 994 | |||
| 995 | if (status & ATH9K_INT_TXURN) | ||
| 996 | /* bump tx trigger level */ | ||
| 997 | ath9k_hw_updatetxtriglevel(ah, true); | ||
| 998 | /* XXX: optimize this */ | ||
| 999 | if (status & ATH9K_INT_RX) | ||
| 1000 | sched = true; | ||
| 1001 | if (status & ATH9K_INT_TX) | ||
| 1002 | sched = true; | ||
| 1003 | if (status & ATH9K_INT_BMISS) | ||
| 1004 | sched = true; | ||
| 1005 | /* carrier sense timeout */ | ||
| 1006 | if (status & ATH9K_INT_CST) | ||
| 1007 | sched = true; | ||
| 1008 | if (status & ATH9K_INT_MIB) { | ||
| 1009 | /* | ||
| 1010 | * Disable interrupts until we service the MIB | ||
| 1011 | * interrupt; otherwise it will continue to | ||
| 1012 | * fire. | ||
| 1013 | */ | ||
| 1014 | ath9k_hw_set_interrupts(ah, 0); | ||
| 1015 | /* | ||
| 1016 | * Let the hal handle the event. We assume | ||
| 1017 | * it will clear whatever condition caused | ||
| 1018 | * the interrupt. | ||
| 1019 | */ | ||
| 1020 | ath9k_hw_procmibevent(ah, &sc->sc_halstats); | ||
| 1021 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | ||
| 1022 | } | ||
| 1023 | if (status & ATH9K_INT_TIM_TIMER) { | ||
| 1024 | if (!(ah->ah_caps.hw_caps & | ||
| 1025 | ATH9K_HW_CAP_AUTOSLEEP)) { | ||
| 1026 | /* Clear RxAbort bit so that we can | ||
| 1027 | * receive frames */ | ||
| 1028 | ath9k_hw_setrxabort(ah, 0); | ||
| 1029 | sched = true; | ||
| 1030 | } | ||
| 1031 | } | ||
| 1032 | } | ||
| 1033 | } while (0); | ||
| 1034 | |||
| 1035 | if (sched) { | ||
| 1036 | /* turn off every interrupt except SWBA */ | ||
| 1037 | ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA)); | ||
| 1038 | tasklet_schedule(&sc->intr_tq); | ||
| 1039 | } | ||
| 1040 | |||
| 1041 | return IRQ_HANDLED; | ||
| 1042 | } | ||
| 1043 | |||
| 1044 | /* Deferred interrupt processing */ | ||
| 1045 | |||
| 1046 | static void ath9k_tasklet(unsigned long data) | ||
| 1047 | { | ||
| 1048 | struct ath_softc *sc = (struct ath_softc *)data; | ||
| 1049 | u32 status = sc->sc_intrstatus; | ||
| 1050 | |||
| 1051 | if (status & ATH9K_INT_FATAL) { | ||
| 1052 | /* need a chip reset */ | ||
| 1053 | ath_internal_reset(sc); | ||
| 1054 | return; | ||
| 1055 | } else { | ||
| 1056 | |||
| 1057 | if (status & | ||
| 1058 | (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { | ||
| 1059 | /* XXX: fill me in */ | ||
| 1060 | /* | ||
| 1061 | if (status & ATH9K_INT_RXORN) { | ||
| 1062 | } | ||
| 1063 | if (status & ATH9K_INT_RXEOL) { | ||
| 1064 | } | ||
| 1065 | */ | ||
| 1066 | spin_lock_bh(&sc->sc_rxflushlock); | ||
| 1067 | ath_rx_tasklet(sc, 0); | ||
| 1068 | spin_unlock_bh(&sc->sc_rxflushlock); | ||
| 1069 | } | ||
| 1070 | /* XXX: optimize this */ | ||
| 1071 | if (status & ATH9K_INT_TX) | ||
| 1072 | ath_tx_tasklet(sc); | ||
| 1073 | /* XXX: fill me in */ | ||
| 1074 | /* | ||
| 1075 | if (status & ATH9K_INT_BMISS) { | ||
| 1076 | } | ||
| 1077 | if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) { | ||
| 1078 | if (status & ATH9K_INT_TIM) { | ||
| 1079 | } | ||
| 1080 | if (status & ATH9K_INT_DTIMSYNC) { | ||
| 1081 | } | ||
| 1082 | } | ||
| 1083 | */ | ||
| 1084 | } | ||
| 1085 | |||
| 1086 | /* re-enable hardware interrupt */ | ||
| 1087 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); | ||
| 1088 | } | ||
| 1089 | |||
| 1090 | int ath_init(u16 devid, struct ath_softc *sc) | ||
| 1091 | { | ||
| 1092 | struct ath_hal *ah = NULL; | ||
| 1093 | int status; | ||
| 1094 | int error = 0, i; | ||
| 1095 | int csz = 0; | ||
| 1096 | u32 rd; | ||
| 1097 | |||
| 1098 | /* XXX: hardware will not be ready until ath_open() being called */ | ||
| 1099 | sc->sc_invalid = 1; | ||
| 1100 | |||
| 1101 | sc->sc_debug = DBG_DEFAULT; | ||
| 1102 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid); | ||
| 1103 | |||
| 1104 | /* Initialize tasklet */ | ||
| 1105 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | ||
| 1106 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, | ||
| 1107 | (unsigned long)sc); | ||
| 1108 | |||
| 1109 | /* | ||
| 1110 | * Cache line size is used to size and align various | ||
| 1111 | * structures used to communicate with the hardware. | ||
| 1112 | */ | ||
| 1113 | bus_read_cachesize(sc, &csz); | ||
| 1114 | /* XXX assert csz is non-zero */ | ||
| 1115 | sc->sc_cachelsz = csz << 2; /* convert to bytes */ | ||
| 1116 | |||
| 1117 | spin_lock_init(&sc->sc_resetlock); | ||
| 1118 | |||
| 1119 | ah = ath9k_hw_attach(devid, sc, sc->mem, &status); | ||
| 1120 | if (ah == NULL) { | ||
| 1121 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1122 | "%s: unable to attach hardware; HAL status %u\n", | ||
| 1123 | __func__, status); | ||
| 1124 | error = -ENXIO; | ||
| 1125 | goto bad; | ||
| 1126 | } | ||
| 1127 | sc->sc_ah = ah; | ||
| 1128 | |||
| 1129 | /* Get the chipset-specific aggr limit. */ | ||
| 1130 | sc->sc_rtsaggrlimit = ah->ah_caps.rts_aggr_limit; | ||
| 1131 | |||
| 1132 | /* Get the hardware key cache size. */ | ||
| 1133 | sc->sc_keymax = ah->ah_caps.keycache_size; | ||
| 1134 | if (sc->sc_keymax > ATH_KEYMAX) { | ||
| 1135 | DPRINTF(sc, ATH_DBG_KEYCACHE, | ||
| 1136 | "%s: Warning, using only %u entries in %u key cache\n", | ||
| 1137 | __func__, ATH_KEYMAX, sc->sc_keymax); | ||
| 1138 | sc->sc_keymax = ATH_KEYMAX; | ||
| 1139 | } | ||
| 1140 | |||
| 1141 | /* | ||
| 1142 | * Reset the key cache since some parts do not | ||
| 1143 | * reset the contents on initial power up. | ||
| 1144 | */ | ||
| 1145 | for (i = 0; i < sc->sc_keymax; i++) | ||
| 1146 | ath9k_hw_keyreset(ah, (u16) i); | ||
| 1147 | /* | ||
| 1148 | * Mark key cache slots associated with global keys | ||
| 1149 | * as in use. If we knew TKIP was not to be used we | ||
| 1150 | * could leave the +32, +64, and +32+64 slots free. | ||
| 1151 | * XXX only for splitmic. | ||
| 1152 | */ | ||
| 1153 | for (i = 0; i < IEEE80211_WEP_NKID; i++) { | ||
| 1154 | set_bit(i, sc->sc_keymap); | ||
| 1155 | set_bit(i + 32, sc->sc_keymap); | ||
| 1156 | set_bit(i + 64, sc->sc_keymap); | ||
| 1157 | set_bit(i + 32 + 64, sc->sc_keymap); | ||
| 1158 | } | ||
| 1159 | /* | ||
| 1160 | * Collect the channel list using the default country | ||
| 1161 | * code and including outdoor channels. The 802.11 layer | ||
| 1162 | * is resposible for filtering this list based on settings | ||
| 1163 | * like the phy mode. | ||
| 1164 | */ | ||
| 1165 | rd = ah->ah_currentRD; | ||
| 1166 | |||
| 1167 | error = ath_setup_channels(sc); | ||
| 1168 | if (error) | ||
| 1169 | goto bad; | ||
| 1170 | |||
| 1171 | /* default to STA mode */ | ||
| 1172 | sc->sc_opmode = ATH9K_M_MONITOR; | ||
| 1173 | |||
| 1174 | /* Setup rate tables */ | ||
| 1175 | |||
| 1176 | ath_setup_rates(sc, IEEE80211_BAND_2GHZ); | ||
| 1177 | ath_setup_rates(sc, IEEE80211_BAND_5GHZ); | ||
| 1178 | |||
| 1179 | /* NB: setup here so ath_rate_update is happy */ | ||
| 1180 | ath_setcurmode(sc, ATH9K_MODE_11A); | ||
| 1181 | |||
| 1182 | /* | ||
| 1183 | * Allocate hardware transmit queues: one queue for | ||
| 1184 | * beacon frames and one data queue for each QoS | ||
| 1185 | * priority. Note that the hal handles reseting | ||
| 1186 | * these queues at the needed time. | ||
| 1187 | */ | ||
| 1188 | sc->sc_bhalq = ath_beaconq_setup(ah); | ||
| 1189 | if (sc->sc_bhalq == -1) { | ||
| 1190 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1191 | "%s: unable to setup a beacon xmit queue\n", __func__); | ||
| 1192 | error = -EIO; | ||
| 1193 | goto bad2; | ||
| 1194 | } | ||
| 1195 | sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); | ||
| 1196 | if (sc->sc_cabq == NULL) { | ||
| 1197 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1198 | "%s: unable to setup CAB xmit queue\n", __func__); | ||
| 1199 | error = -EIO; | ||
| 1200 | goto bad2; | ||
| 1201 | } | ||
| 1202 | |||
| 1203 | sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME; | ||
| 1204 | ath_cabq_update(sc); | ||
| 1205 | |||
| 1206 | for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++) | ||
| 1207 | sc->sc_haltype2q[i] = -1; | ||
| 1208 | |||
| 1209 | /* Setup data queues */ | ||
| 1210 | /* NB: ensure BK queue is the lowest priority h/w queue */ | ||
| 1211 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { | ||
| 1212 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1213 | "%s: unable to setup xmit queue for BK traffic\n", | ||
| 1214 | __func__); | ||
| 1215 | error = -EIO; | ||
| 1216 | goto bad2; | ||
| 1217 | } | ||
| 1218 | |||
| 1219 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { | ||
| 1220 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1221 | "%s: unable to setup xmit queue for BE traffic\n", | ||
| 1222 | __func__); | ||
| 1223 | error = -EIO; | ||
| 1224 | goto bad2; | ||
| 1225 | } | ||
| 1226 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { | ||
| 1227 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1228 | "%s: unable to setup xmit queue for VI traffic\n", | ||
| 1229 | __func__); | ||
| 1230 | error = -EIO; | ||
| 1231 | goto bad2; | ||
| 1232 | } | ||
| 1233 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { | ||
| 1234 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1235 | "%s: unable to setup xmit queue for VO traffic\n", | ||
| 1236 | __func__); | ||
| 1237 | error = -EIO; | ||
| 1238 | goto bad2; | ||
| 1239 | } | ||
| 1240 | |||
| 1241 | sc->sc_rc = ath_rate_attach(ah); | ||
| 1242 | if (sc->sc_rc == NULL) { | ||
| 1243 | error = EIO; | ||
| 1244 | goto bad2; | ||
| 1245 | } | ||
| 1246 | |||
| 1247 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | ||
| 1248 | ATH9K_CIPHER_TKIP, NULL)) { | ||
| 1249 | /* | ||
| 1250 | * Whether we should enable h/w TKIP MIC. | ||
| 1251 | * XXX: if we don't support WME TKIP MIC, then we wouldn't | ||
| 1252 | * report WMM capable, so it's always safe to turn on | ||
| 1253 | * TKIP MIC in this case. | ||
| 1254 | */ | ||
| 1255 | ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, | ||
| 1256 | 0, 1, NULL); | ||
| 1257 | } | ||
| 1258 | |||
| 1259 | /* | ||
| 1260 | * Check whether the separate key cache entries | ||
| 1261 | * are required to handle both tx+rx MIC keys. | ||
| 1262 | * With split mic keys the number of stations is limited | ||
| 1263 | * to 27 otherwise 59. | ||
| 1264 | */ | ||
| 1265 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | ||
| 1266 | ATH9K_CIPHER_TKIP, NULL) | ||
| 1267 | && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | ||
| 1268 | ATH9K_CIPHER_MIC, NULL) | ||
| 1269 | && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, | ||
| 1270 | 0, NULL)) | ||
| 1271 | sc->sc_splitmic = 1; | ||
| 1272 | |||
| 1273 | /* turn on mcast key search if possible */ | ||
| 1274 | if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) | ||
| 1275 | (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, | ||
| 1276 | 1, NULL); | ||
| 1277 | |||
| 1278 | sc->sc_config.txpowlimit = ATH_TXPOWER_MAX; | ||
| 1279 | sc->sc_config.txpowlimit_override = 0; | ||
| 1280 | |||
| 1281 | /* 11n Capabilities */ | ||
| 1282 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { | ||
| 1283 | sc->sc_txaggr = 1; | ||
| 1284 | sc->sc_rxaggr = 1; | ||
| 1285 | } | ||
| 1286 | |||
| 1287 | sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask; | ||
| 1288 | sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; | ||
| 1289 | |||
| 1290 | /* Configuration for rx chain detection */ | ||
| 1291 | sc->sc_rxchaindetect_ref = 0; | ||
| 1292 | sc->sc_rxchaindetect_thresh5GHz = 35; | ||
| 1293 | sc->sc_rxchaindetect_thresh2GHz = 35; | ||
| 1294 | sc->sc_rxchaindetect_delta5GHz = 30; | ||
| 1295 | sc->sc_rxchaindetect_delta2GHz = 30; | ||
| 1296 | |||
| 1297 | ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); | ||
| 1298 | sc->sc_defant = ath9k_hw_getdefantenna(ah); | ||
| 1299 | |||
| 1300 | ath9k_hw_getmac(ah, sc->sc_myaddr); | ||
| 1301 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { | ||
| 1302 | ath9k_hw_getbssidmask(ah, sc->sc_bssidmask); | ||
| 1303 | ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask); | ||
| 1304 | ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); | ||
| 1305 | } | ||
| 1306 | sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ | ||
| 1307 | |||
| 1308 | /* initialize beacon slots */ | ||
| 1309 | for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++) | ||
| 1310 | sc->sc_bslot[i] = ATH_IF_ID_ANY; | ||
| 1311 | |||
| 1312 | /* save MISC configurations */ | ||
| 1313 | sc->sc_config.swBeaconProcess = 1; | ||
| 1314 | |||
| 1315 | #ifdef CONFIG_SLOW_ANT_DIV | ||
| 1316 | /* range is 40 - 255, we use something in the middle */ | ||
| 1317 | ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127); | ||
| 1318 | #endif | ||
| 1319 | |||
| 1320 | return 0; | ||
| 1321 | bad2: | ||
| 1322 | /* cleanup tx queues */ | ||
| 1323 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | ||
| 1324 | if (ATH_TXQ_SETUP(sc, i)) | ||
| 1325 | ath_tx_cleanupq(sc, &sc->sc_txq[i]); | ||
| 1326 | bad: | ||
| 1327 | if (ah) | ||
| 1328 | ath9k_hw_detach(ah); | ||
| 1329 | return error; | ||
| 1330 | } | ||
| 1331 | |||
| 1332 | void ath_deinit(struct ath_softc *sc) | ||
| 1333 | { | ||
| 1334 | struct ath_hal *ah = sc->sc_ah; | ||
| 1335 | int i; | ||
| 1336 | |||
| 1337 | DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__); | ||
| 1338 | |||
| 1339 | ath_stop(sc); | ||
| 1340 | if (!sc->sc_invalid) | ||
| 1341 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | ||
| 1342 | ath_rate_detach(sc->sc_rc); | ||
| 1343 | /* cleanup tx queues */ | ||
| 1344 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | ||
| 1345 | if (ATH_TXQ_SETUP(sc, i)) | ||
| 1346 | ath_tx_cleanupq(sc, &sc->sc_txq[i]); | ||
| 1347 | ath9k_hw_detach(ah); | ||
| 1348 | } | ||
| 1349 | |||
| 1350 | /*******************/ | ||
| 1351 | /* Node Management */ | ||
| 1352 | /*******************/ | ||
| 1353 | |||
| 1354 | struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id) | ||
| 1355 | { | ||
| 1356 | struct ath_vap *avp; | ||
| 1357 | struct ath_node *an; | ||
| 1358 | DECLARE_MAC_BUF(mac); | ||
| 1359 | |||
| 1360 | avp = sc->sc_vaps[if_id]; | ||
| 1361 | ASSERT(avp != NULL); | ||
| 1362 | |||
| 1363 | /* mac80211 sta_notify callback is from an IRQ context, so no sleep */ | ||
| 1364 | an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC); | ||
| 1365 | if (an == NULL) | ||
| 1366 | return NULL; | ||
| 1367 | memzero(an, sizeof(*an)); | ||
| 1368 | |||
| 1369 | an->an_sc = sc; | ||
| 1370 | memcpy(an->an_addr, addr, ETH_ALEN); | ||
| 1371 | atomic_set(&an->an_refcnt, 1); | ||
| 1372 | |||
| 1373 | /* set up per-node tx/rx state */ | ||
| 1374 | ath_tx_node_init(sc, an); | ||
| 1375 | ath_rx_node_init(sc, an); | ||
| 1376 | |||
| 1377 | ath_chainmask_sel_init(sc, an); | ||
| 1378 | ath_chainmask_sel_timerstart(&an->an_chainmask_sel); | ||
| 1379 | list_add(&an->list, &sc->node_list); | ||
| 1380 | |||
| 1381 | return an; | ||
| 1382 | } | ||
| 1383 | |||
| 1384 | void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag) | ||
| 1385 | { | ||
| 1386 | unsigned long flags; | ||
| 1387 | |||
| 1388 | DECLARE_MAC_BUF(mac); | ||
| 1389 | |||
| 1390 | ath_chainmask_sel_timerstop(&an->an_chainmask_sel); | ||
| 1391 | an->an_flags |= ATH_NODE_CLEAN; | ||
| 1392 | ath_tx_node_cleanup(sc, an, bh_flag); | ||
| 1393 | ath_rx_node_cleanup(sc, an); | ||
| 1394 | |||
| 1395 | ath_tx_node_free(sc, an); | ||
| 1396 | ath_rx_node_free(sc, an); | ||
| 1397 | |||
| 1398 | spin_lock_irqsave(&sc->node_lock, flags); | ||
| 1399 | |||
| 1400 | list_del(&an->list); | ||
| 1401 | |||
| 1402 | spin_unlock_irqrestore(&sc->node_lock, flags); | ||
| 1403 | |||
| 1404 | kfree(an); | ||
| 1405 | } | ||
| 1406 | |||
| 1407 | /* Finds a node and increases the refcnt if found */ | ||
| 1408 | |||
| 1409 | struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr) | ||
| 1410 | { | ||
| 1411 | struct ath_node *an = NULL, *an_found = NULL; | ||
| 1412 | |||
| 1413 | if (list_empty(&sc->node_list)) /* FIXME */ | ||
| 1414 | goto out; | ||
| 1415 | list_for_each_entry(an, &sc->node_list, list) { | ||
| 1416 | if (!compare_ether_addr(an->an_addr, addr)) { | ||
| 1417 | atomic_inc(&an->an_refcnt); | ||
| 1418 | an_found = an; | ||
| 1419 | break; | ||
| 1420 | } | ||
| 1421 | } | ||
| 1422 | out: | ||
| 1423 | return an_found; | ||
| 1424 | } | ||
| 1425 | |||
| 1426 | /* Decrements the refcnt and if it drops to zero, detach the node */ | ||
| 1427 | |||
| 1428 | void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag) | ||
| 1429 | { | ||
| 1430 | if (atomic_dec_and_test(&an->an_refcnt)) | ||
| 1431 | ath_node_detach(sc, an, bh_flag); | ||
| 1432 | } | ||
| 1433 | |||
| 1434 | /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */ | ||
| 1435 | struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr) | ||
| 1436 | { | ||
| 1437 | struct ath_node *an = NULL, *an_found = NULL; | ||
| 1438 | |||
| 1439 | if (list_empty(&sc->node_list)) | ||
| 1440 | return NULL; | ||
| 1441 | |||
| 1442 | list_for_each_entry(an, &sc->node_list, list) | ||
| 1443 | if (!compare_ether_addr(an->an_addr, addr)) { | ||
| 1444 | an_found = an; | ||
| 1445 | break; | ||
| 1446 | } | ||
| 1447 | |||
| 1448 | return an_found; | ||
| 1449 | } | ||
| 1450 | |||
| 1451 | /* | ||
| 1452 | * Set up New Node | ||
| 1453 | * | ||
| 1454 | * Setup driver-specific state for a newly associated node. This routine | ||
| 1455 | * really only applies if compression or XR are enabled, there is no code | ||
| 1456 | * covering any other cases. | ||
| 1457 | */ | ||
| 1458 | |||
| 1459 | void ath_newassoc(struct ath_softc *sc, | ||
| 1460 | struct ath_node *an, int isnew, int isuapsd) | ||
| 1461 | { | ||
| 1462 | int tidno; | ||
| 1463 | |||
| 1464 | /* if station reassociates, tear down the aggregation state. */ | ||
| 1465 | if (!isnew) { | ||
| 1466 | for (tidno = 0; tidno < WME_NUM_TID; tidno++) { | ||
| 1467 | if (sc->sc_txaggr) | ||
| 1468 | ath_tx_aggr_teardown(sc, an, tidno); | ||
| 1469 | if (sc->sc_rxaggr) | ||
| 1470 | ath_rx_aggr_teardown(sc, an, tidno); | ||
| 1471 | } | ||
| 1472 | } | ||
| 1473 | an->an_flags = 0; | ||
| 1474 | } | ||
| 1475 | |||
| 1476 | /**************/ | ||
| 1477 | /* Encryption */ | ||
| 1478 | /**************/ | ||
| 1479 | |||
| 1480 | void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot) | ||
| 1481 | { | ||
| 1482 | ath9k_hw_keyreset(sc->sc_ah, keyix); | ||
| 1483 | if (freeslot) | ||
| 1484 | clear_bit(keyix, sc->sc_keymap); | ||
| 1485 | } | ||
| 1486 | |||
| 1487 | int ath_keyset(struct ath_softc *sc, | ||
| 1488 | u16 keyix, | ||
| 1489 | struct ath9k_keyval *hk, | ||
| 1490 | const u8 mac[ETH_ALEN]) | ||
| 1491 | { | ||
| 1492 | bool status; | ||
| 1493 | |||
| 1494 | status = ath9k_hw_set_keycache_entry(sc->sc_ah, | ||
| 1495 | keyix, hk, mac, false); | ||
| 1496 | |||
| 1497 | return status != false; | ||
| 1498 | } | ||
| 1499 | |||
| 1500 | /***********************/ | ||
| 1501 | /* TX Power/Regulatory */ | ||
| 1502 | /***********************/ | ||
| 1503 | |||
| 1504 | /* | ||
| 1505 | * Set Transmit power in HAL | ||
| 1506 | * | ||
| 1507 | * This routine makes the actual HAL calls to set the new transmit power | ||
| 1508 | * limit. | ||
| 1509 | */ | ||
| 1510 | |||
| 1511 | void ath_update_txpow(struct ath_softc *sc) | ||
| 1512 | { | ||
| 1513 | struct ath_hal *ah = sc->sc_ah; | ||
| 1514 | u32 txpow; | ||
| 1515 | |||
| 1516 | if (sc->sc_curtxpow != sc->sc_config.txpowlimit) { | ||
| 1517 | ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit); | ||
| 1518 | /* read back in case value is clamped */ | ||
| 1519 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | ||
| 1520 | sc->sc_curtxpow = txpow; | ||
| 1521 | } | ||
| 1522 | } | ||
| 1523 | |||
| 1524 | /* Return the current country and domain information */ | ||
| 1525 | void ath_get_currentCountry(struct ath_softc *sc, | ||
| 1526 | struct ath9k_country_entry *ctry) | ||
| 1527 | { | ||
| 1528 | ath9k_regd_get_current_country(sc->sc_ah, ctry); | ||
| 1529 | |||
| 1530 | /* If HAL not specific yet, since it is band dependent, | ||
| 1531 | * use the one we passed in. */ | ||
| 1532 | if (ctry->countryCode == CTRY_DEFAULT) { | ||
| 1533 | ctry->iso[0] = 0; | ||
| 1534 | ctry->iso[1] = 0; | ||
| 1535 | } else if (ctry->iso[0] && ctry->iso[1]) { | ||
| 1536 | if (!ctry->iso[2]) { | ||
| 1537 | if (ath_outdoor) | ||
| 1538 | ctry->iso[2] = 'O'; | ||
| 1539 | else | ||
| 1540 | ctry->iso[2] = 'I'; | ||
| 1541 | } | ||
| 1542 | } | ||
| 1543 | } | ||
| 1544 | |||
| 1545 | /**************************/ | ||
| 1546 | /* Slow Antenna Diversity */ | ||
| 1547 | /**************************/ | ||
| 1548 | |||
| 1549 | void ath_slow_ant_div_init(struct ath_antdiv *antdiv, | ||
| 1550 | struct ath_softc *sc, | ||
| 1551 | int32_t rssitrig) | ||
| 1552 | { | ||
| 1553 | int trig; | ||
| 1554 | |||
| 1555 | /* antdivf_rssitrig can range from 40 - 0xff */ | ||
| 1556 | trig = (rssitrig > 0xff) ? 0xff : rssitrig; | ||
| 1557 | trig = (rssitrig < 40) ? 40 : rssitrig; | ||
| 1558 | |||
| 1559 | antdiv->antdiv_sc = sc; | ||
| 1560 | antdiv->antdivf_rssitrig = trig; | ||
| 1561 | } | ||
| 1562 | |||
| 1563 | void ath_slow_ant_div_start(struct ath_antdiv *antdiv, | ||
| 1564 | u8 num_antcfg, | ||
| 1565 | const u8 *bssid) | ||
| 1566 | { | ||
| 1567 | antdiv->antdiv_num_antcfg = | ||
| 1568 | num_antcfg < ATH_ANT_DIV_MAX_CFG ? | ||
| 1569 | num_antcfg : ATH_ANT_DIV_MAX_CFG; | ||
| 1570 | antdiv->antdiv_state = ATH_ANT_DIV_IDLE; | ||
| 1571 | antdiv->antdiv_curcfg = 0; | ||
| 1572 | antdiv->antdiv_bestcfg = 0; | ||
| 1573 | antdiv->antdiv_laststatetsf = 0; | ||
| 1574 | |||
| 1575 | memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid)); | ||
| 1576 | |||
| 1577 | antdiv->antdiv_start = 1; | ||
| 1578 | } | ||
| 1579 | |||
| 1580 | void ath_slow_ant_div_stop(struct ath_antdiv *antdiv) | ||
| 1581 | { | ||
| 1582 | antdiv->antdiv_start = 0; | ||
| 1583 | } | ||
| 1584 | |||
| 1585 | static int32_t ath_find_max_val(int32_t *val, | ||
| 1586 | u8 num_val, u8 *max_index) | ||
| 1587 | { | ||
| 1588 | u32 MaxVal = *val++; | ||
| 1589 | u32 cur_index = 0; | ||
| 1590 | |||
| 1591 | *max_index = 0; | ||
| 1592 | while (++cur_index < num_val) { | ||
| 1593 | if (*val > MaxVal) { | ||
| 1594 | MaxVal = *val; | ||
| 1595 | *max_index = cur_index; | ||
| 1596 | } | ||
| 1597 | |||
| 1598 | val++; | ||
| 1599 | } | ||
| 1600 | |||
| 1601 | return MaxVal; | ||
| 1602 | } | ||
| 1603 | |||
| 1604 | void ath_slow_ant_div(struct ath_antdiv *antdiv, | ||
| 1605 | struct ieee80211_hdr *hdr, | ||
| 1606 | struct ath_rx_status *rx_stats) | ||
| 1607 | { | ||
| 1608 | struct ath_softc *sc = antdiv->antdiv_sc; | ||
| 1609 | struct ath_hal *ah = sc->sc_ah; | ||
| 1610 | u64 curtsf = 0; | ||
| 1611 | u8 bestcfg, curcfg = antdiv->antdiv_curcfg; | ||
| 1612 | __le16 fc = hdr->frame_control; | ||
| 1613 | |||
| 1614 | if (antdiv->antdiv_start && ieee80211_is_beacon(fc) | ||
| 1615 | && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) { | ||
| 1616 | antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi; | ||
| 1617 | antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah); | ||
| 1618 | curtsf = antdiv->antdiv_lastbtsf[curcfg]; | ||
| 1619 | } else { | ||
| 1620 | return; | ||
| 1621 | } | ||
| 1622 | |||
| 1623 | switch (antdiv->antdiv_state) { | ||
| 1624 | case ATH_ANT_DIV_IDLE: | ||
| 1625 | if ((antdiv->antdiv_lastbrssi[curcfg] < | ||
| 1626 | antdiv->antdivf_rssitrig) | ||
| 1627 | && ((curtsf - antdiv->antdiv_laststatetsf) > | ||
| 1628 | ATH_ANT_DIV_MIN_IDLE_US)) { | ||
| 1629 | |||
| 1630 | curcfg++; | ||
| 1631 | if (curcfg == antdiv->antdiv_num_antcfg) | ||
| 1632 | curcfg = 0; | ||
| 1633 | |||
| 1634 | if (!ath9k_hw_select_antconfig(ah, curcfg)) { | ||
| 1635 | antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg; | ||
| 1636 | antdiv->antdiv_curcfg = curcfg; | ||
| 1637 | antdiv->antdiv_laststatetsf = curtsf; | ||
| 1638 | antdiv->antdiv_state = ATH_ANT_DIV_SCAN; | ||
| 1639 | } | ||
| 1640 | } | ||
| 1641 | break; | ||
| 1642 | |||
| 1643 | case ATH_ANT_DIV_SCAN: | ||
| 1644 | if ((curtsf - antdiv->antdiv_laststatetsf) < | ||
| 1645 | ATH_ANT_DIV_MIN_SCAN_US) | ||
| 1646 | break; | ||
| 1647 | |||
| 1648 | curcfg++; | ||
| 1649 | if (curcfg == antdiv->antdiv_num_antcfg) | ||
| 1650 | curcfg = 0; | ||
| 1651 | |||
| 1652 | if (curcfg == antdiv->antdiv_bestcfg) { | ||
| 1653 | ath_find_max_val(antdiv->antdiv_lastbrssi, | ||
| 1654 | antdiv->antdiv_num_antcfg, &bestcfg); | ||
| 1655 | if (!ath9k_hw_select_antconfig(ah, bestcfg)) { | ||
| 1656 | antdiv->antdiv_bestcfg = bestcfg; | ||
| 1657 | antdiv->antdiv_curcfg = bestcfg; | ||
| 1658 | antdiv->antdiv_laststatetsf = curtsf; | ||
| 1659 | antdiv->antdiv_state = ATH_ANT_DIV_IDLE; | ||
| 1660 | } | ||
| 1661 | } else { | ||
| 1662 | if (!ath9k_hw_select_antconfig(ah, curcfg)) { | ||
| 1663 | antdiv->antdiv_curcfg = curcfg; | ||
| 1664 | antdiv->antdiv_laststatetsf = curtsf; | ||
| 1665 | antdiv->antdiv_state = ATH_ANT_DIV_SCAN; | ||
| 1666 | } | ||
| 1667 | } | ||
| 1668 | |||
| 1669 | break; | ||
| 1670 | } | ||
| 1671 | } | ||
| 1672 | |||
| 1673 | /***********************/ | ||
| 1674 | /* Descriptor Handling */ | ||
| 1675 | /***********************/ | ||
| 1676 | |||
| 1677 | /* | ||
| 1678 | * Set up DMA descriptors | ||
| 1679 | * | ||
| 1680 | * This function will allocate both the DMA descriptor structure, and the | ||
| 1681 | * buffers it contains. These are used to contain the descriptors used | ||
| 1682 | * by the system. | ||
| 1683 | */ | ||
| 1684 | |||
| 1685 | int ath_descdma_setup(struct ath_softc *sc, | ||
| 1686 | struct ath_descdma *dd, | ||
| 1687 | struct list_head *head, | ||
| 1688 | const char *name, | ||
| 1689 | int nbuf, | ||
| 1690 | int ndesc) | ||
| 1691 | { | ||
| 1692 | #define DS2PHYS(_dd, _ds) \ | ||
| 1693 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | ||
| 1694 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | ||
| 1695 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | ||
| 1696 | |||
| 1697 | struct ath_desc *ds; | ||
| 1698 | struct ath_buf *bf; | ||
| 1699 | int i, bsize, error; | ||
| 1700 | |||
| 1701 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n", | ||
| 1702 | __func__, name, nbuf, ndesc); | ||
| 1703 | |||
| 1704 | /* ath_desc must be a multiple of DWORDs */ | ||
| 1705 | if ((sizeof(struct ath_desc) % 4) != 0) { | ||
| 1706 | DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n", | ||
| 1707 | __func__); | ||
| 1708 | ASSERT((sizeof(struct ath_desc) % 4) == 0); | ||
| 1709 | error = -ENOMEM; | ||
| 1710 | goto fail; | ||
| 1711 | } | ||
| 1712 | |||
| 1713 | dd->dd_name = name; | ||
| 1714 | dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; | ||
| 1715 | |||
| 1716 | /* | ||
| 1717 | * Need additional DMA memory because we can't use | ||
| 1718 | * descriptors that cross the 4K page boundary. Assume | ||
| 1719 | * one skipped descriptor per 4K page. | ||
| 1720 | */ | ||
| 1721 | if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | ||
| 1722 | u32 ndesc_skipped = | ||
| 1723 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | ||
| 1724 | u32 dma_len; | ||
| 1725 | |||
| 1726 | while (ndesc_skipped) { | ||
| 1727 | dma_len = ndesc_skipped * sizeof(struct ath_desc); | ||
| 1728 | dd->dd_desc_len += dma_len; | ||
| 1729 | |||
| 1730 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | ||
| 1731 | }; | ||
| 1732 | } | ||
| 1733 | |||
| 1734 | /* allocate descriptors */ | ||
| 1735 | dd->dd_desc = pci_alloc_consistent(sc->pdev, | ||
| 1736 | dd->dd_desc_len, | ||
| 1737 | &dd->dd_desc_paddr); | ||
| 1738 | if (dd->dd_desc == NULL) { | ||
| 1739 | error = -ENOMEM; | ||
| 1740 | goto fail; | ||
| 1741 | } | ||
| 1742 | ds = dd->dd_desc; | ||
| 1743 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n", | ||
| 1744 | __func__, dd->dd_name, ds, (u32) dd->dd_desc_len, | ||
| 1745 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | ||
| 1746 | |||
| 1747 | /* allocate buffers */ | ||
| 1748 | bsize = sizeof(struct ath_buf) * nbuf; | ||
| 1749 | bf = kmalloc(bsize, GFP_KERNEL); | ||
| 1750 | if (bf == NULL) { | ||
| 1751 | error = -ENOMEM; | ||
| 1752 | goto fail2; | ||
| 1753 | } | ||
| 1754 | memzero(bf, bsize); | ||
| 1755 | dd->dd_bufptr = bf; | ||
| 1756 | |||
| 1757 | INIT_LIST_HEAD(head); | ||
| 1758 | for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { | ||
| 1759 | bf->bf_desc = ds; | ||
| 1760 | bf->bf_daddr = DS2PHYS(dd, ds); | ||
| 1761 | |||
| 1762 | if (!(sc->sc_ah->ah_caps.hw_caps & | ||
| 1763 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | ||
| 1764 | /* | ||
| 1765 | * Skip descriptor addresses which can cause 4KB | ||
| 1766 | * boundary crossing (addr + length) with a 32 dword | ||
| 1767 | * descriptor fetch. | ||
| 1768 | */ | ||
| 1769 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | ||
| 1770 | ASSERT((caddr_t) bf->bf_desc < | ||
| 1771 | ((caddr_t) dd->dd_desc + | ||
| 1772 | dd->dd_desc_len)); | ||
| 1773 | |||
| 1774 | ds += ndesc; | ||
| 1775 | bf->bf_desc = ds; | ||
| 1776 | bf->bf_daddr = DS2PHYS(dd, ds); | ||
| 1777 | } | ||
| 1778 | } | ||
| 1779 | list_add_tail(&bf->list, head); | ||
| 1780 | } | ||
| 1781 | return 0; | ||
| 1782 | fail2: | ||
| 1783 | pci_free_consistent(sc->pdev, | ||
| 1784 | dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr); | ||
| 1785 | fail: | ||
| 1786 | memzero(dd, sizeof(*dd)); | ||
| 1787 | return error; | ||
| 1788 | #undef ATH_DESC_4KB_BOUND_CHECK | ||
| 1789 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | ||
| 1790 | #undef DS2PHYS | ||
| 1791 | } | ||
| 1792 | |||
| 1793 | /* | ||
| 1794 | * Cleanup DMA descriptors | ||
| 1795 | * | ||
| 1796 | * This function will free the DMA block that was allocated for the descriptor | ||
| 1797 | * pool. Since this was allocated as one "chunk", it is freed in the same | ||
| 1798 | * manner. | ||
| 1799 | */ | ||
| 1800 | |||
| 1801 | void ath_descdma_cleanup(struct ath_softc *sc, | ||
| 1802 | struct ath_descdma *dd, | ||
| 1803 | struct list_head *head) | ||
| 1804 | { | ||
| 1805 | /* Free memory associated with descriptors */ | ||
| 1806 | pci_free_consistent(sc->pdev, | ||
| 1807 | dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr); | ||
| 1808 | |||
| 1809 | INIT_LIST_HEAD(head); | ||
| 1810 | kfree(dd->dd_bufptr); | ||
| 1811 | memzero(dd, sizeof(*dd)); | ||
| 1812 | } | ||
| 1813 | |||
| 1814 | /*************/ | ||
| 1815 | /* Utilities */ | ||
| 1816 | /*************/ | ||
| 1817 | |||
| 1818 | void ath_internal_reset(struct ath_softc *sc) | ||
| 1819 | { | ||
| 1820 | ath_reset_start(sc, 0); | ||
| 1821 | ath_reset(sc); | ||
| 1822 | ath_reset_end(sc, 0); | ||
| 1823 | } | ||
| 1824 | |||
| 1825 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) | ||
| 1826 | { | ||
| 1827 | int qnum; | ||
| 1828 | |||
| 1829 | switch (queue) { | ||
| 1830 | case 0: | ||
| 1831 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO]; | ||
| 1832 | break; | ||
| 1833 | case 1: | ||
| 1834 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI]; | ||
| 1835 | break; | ||
| 1836 | case 2: | ||
| 1837 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; | ||
| 1838 | break; | ||
| 1839 | case 3: | ||
| 1840 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK]; | ||
| 1841 | break; | ||
| 1842 | default: | ||
| 1843 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; | ||
| 1844 | break; | ||
| 1845 | } | ||
| 1846 | |||
| 1847 | return qnum; | ||
| 1848 | } | ||
| 1849 | |||
| 1850 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | ||
| 1851 | { | ||
| 1852 | int qnum; | ||
| 1853 | |||
| 1854 | switch (queue) { | ||
| 1855 | case ATH9K_WME_AC_VO: | ||
| 1856 | qnum = 0; | ||
| 1857 | break; | ||
| 1858 | case ATH9K_WME_AC_VI: | ||
| 1859 | qnum = 1; | ||
| 1860 | break; | ||
| 1861 | case ATH9K_WME_AC_BE: | ||
| 1862 | qnum = 2; | ||
| 1863 | break; | ||
| 1864 | case ATH9K_WME_AC_BK: | ||
| 1865 | qnum = 3; | ||
| 1866 | break; | ||
| 1867 | default: | ||
| 1868 | qnum = -1; | ||
| 1869 | break; | ||
| 1870 | } | ||
| 1871 | |||
| 1872 | return qnum; | ||
| 1873 | } | ||
| 1874 | |||
| 1875 | |||
| 1876 | /* | ||
| 1877 | * Expand time stamp to TSF | ||
| 1878 | * | ||
| 1879 | * Extend 15-bit time stamp from rx descriptor to | ||
| 1880 | * a full 64-bit TSF using the current h/w TSF. | ||
| 1881 | */ | ||
| 1882 | |||
| 1883 | u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | ||
| 1884 | { | ||
| 1885 | u64 tsf; | ||
| 1886 | |||
| 1887 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | ||
| 1888 | if ((tsf & 0x7fff) < rstamp) | ||
| 1889 | tsf -= 0x8000; | ||
| 1890 | return (tsf & ~0x7fff) | rstamp; | ||
| 1891 | } | ||
| 1892 | |||
| 1893 | /* | ||
| 1894 | * Set Default Antenna | ||
| 1895 | * | ||
| 1896 | * Call into the HAL to set the default antenna to use. Not really valid for | ||
| 1897 | * MIMO technology. | ||
| 1898 | */ | ||
| 1899 | |||
| 1900 | void ath_setdefantenna(void *context, u32 antenna) | ||
| 1901 | { | ||
| 1902 | struct ath_softc *sc = (struct ath_softc *)context; | ||
| 1903 | struct ath_hal *ah = sc->sc_ah; | ||
| 1904 | |||
| 1905 | /* XXX block beacon interrupts */ | ||
| 1906 | ath9k_hw_setantenna(ah, antenna); | ||
| 1907 | sc->sc_defant = antenna; | ||
| 1908 | sc->sc_rxotherant = 0; | ||
| 1909 | } | ||
| 1910 | |||
| 1911 | /* | ||
| 1912 | * Set Slot Time | ||
| 1913 | * | ||
| 1914 | * This will wake up the chip if required, and set the slot time for the | ||
| 1915 | * frame (maximum transmit time). Slot time is assumed to be already set | ||
| 1916 | * in the ATH object member sc_slottime | ||
| 1917 | */ | ||
| 1918 | |||
| 1919 | void ath_setslottime(struct ath_softc *sc) | ||
| 1920 | { | ||
| 1921 | ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime); | ||
| 1922 | sc->sc_updateslot = OK; | ||
| 1923 | } | ||
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h new file mode 100644 index 000000000000..673b3d81133a --- /dev/null +++ b/drivers/net/wireless/ath9k/core.h | |||
| @@ -0,0 +1,1072 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef CORE_H | ||
| 18 | #define CORE_H | ||
| 19 | |||
| 20 | #include <linux/version.h> | ||
| 21 | #include <linux/autoconf.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/module.h> | ||
| 24 | #include <linux/spinlock.h> | ||
| 25 | #include <linux/errno.h> | ||
| 26 | #include <linux/skbuff.h> | ||
| 27 | #include <linux/netdevice.h> | ||
| 28 | #include <linux/etherdevice.h> | ||
| 29 | #include <linux/ip.h> | ||
| 30 | #include <linux/tcp.h> | ||
| 31 | #include <linux/in.h> | ||
| 32 | #include <linux/delay.h> | ||
| 33 | #include <linux/wait.h> | ||
| 34 | #include <linux/pci.h> | ||
| 35 | #include <linux/interrupt.h> | ||
| 36 | #include <linux/sched.h> | ||
| 37 | #include <linux/list.h> | ||
| 38 | #include <asm/byteorder.h> | ||
| 39 | #include <linux/scatterlist.h> | ||
| 40 | #include <asm/page.h> | ||
| 41 | #include <net/mac80211.h> | ||
| 42 | |||
| 43 | #include "ath9k.h" | ||
| 44 | #include "rc.h" | ||
| 45 | |||
| 46 | struct ath_node; | ||
| 47 | |||
| 48 | /******************/ | ||
| 49 | /* Utility macros */ | ||
| 50 | /******************/ | ||
| 51 | |||
| 52 | /* Macro to expand scalars to 64-bit objects */ | ||
| 53 | |||
| 54 | #define ito64(x) (sizeof(x) == 8) ? \ | ||
| 55 | (((unsigned long long int)(x)) & (0xff)) : \ | ||
| 56 | (sizeof(x) == 16) ? \ | ||
| 57 | (((unsigned long long int)(x)) & 0xffff) : \ | ||
| 58 | ((sizeof(x) == 32) ? \ | ||
| 59 | (((unsigned long long int)(x)) & 0xffffffff) : \ | ||
| 60 | (unsigned long long int)(x)) | ||
| 61 | |||
| 62 | /* increment with wrap-around */ | ||
| 63 | #define INCR(_l, _sz) do { \ | ||
| 64 | (_l)++; \ | ||
| 65 | (_l) &= ((_sz) - 1); \ | ||
| 66 | } while (0) | ||
| 67 | |||
| 68 | /* decrement with wrap-around */ | ||
| 69 | #define DECR(_l, _sz) do { \ | ||
| 70 | (_l)--; \ | ||
| 71 | (_l) &= ((_sz) - 1); \ | ||
| 72 | } while (0) | ||
| 73 | |||
| 74 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | ||
| 75 | |||
| 76 | #define ASSERT(exp) do { \ | ||
| 77 | if (unlikely(!(exp))) { \ | ||
| 78 | BUG(); \ | ||
| 79 | } \ | ||
| 80 | } while (0) | ||
| 81 | |||
| 82 | /* XXX: remove */ | ||
| 83 | #define memzero(_buf, _len) memset(_buf, 0, _len) | ||
| 84 | |||
| 85 | #define get_dma_mem_context(var, field) (&((var)->field)) | ||
| 86 | #define copy_dma_mem_context(dst, src) (*dst = *src) | ||
| 87 | |||
| 88 | #define ATH9K_BH_STATUS_INTACT 0 | ||
| 89 | #define ATH9K_BH_STATUS_CHANGE 1 | ||
| 90 | |||
| 91 | #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) | ||
| 92 | |||
| 93 | static inline unsigned long get_timestamp(void) | ||
| 94 | { | ||
| 95 | return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ); | ||
| 96 | } | ||
| 97 | |||
| 98 | /*************/ | ||
| 99 | /* Debugging */ | ||
| 100 | /*************/ | ||
| 101 | |||
| 102 | enum ATH_DEBUG { | ||
| 103 | ATH_DBG_RESET = 0x00000001, | ||
| 104 | ATH_DBG_PHY_IO = 0x00000002, | ||
| 105 | ATH_DBG_REG_IO = 0x00000004, | ||
| 106 | ATH_DBG_QUEUE = 0x00000008, | ||
| 107 | ATH_DBG_EEPROM = 0x00000010, | ||
| 108 | ATH_DBG_NF_CAL = 0x00000020, | ||
| 109 | ATH_DBG_CALIBRATE = 0x00000040, | ||
| 110 | ATH_DBG_CHANNEL = 0x00000080, | ||
| 111 | ATH_DBG_INTERRUPT = 0x00000100, | ||
| 112 | ATH_DBG_REGULATORY = 0x00000200, | ||
| 113 | ATH_DBG_ANI = 0x00000400, | ||
| 114 | ATH_DBG_POWER_MGMT = 0x00000800, | ||
| 115 | ATH_DBG_XMIT = 0x00001000, | ||
| 116 | ATH_DBG_BEACON = 0x00002000, | ||
| 117 | ATH_DBG_RATE = 0x00004000, | ||
| 118 | ATH_DBG_CONFIG = 0x00008000, | ||
| 119 | ATH_DBG_KEYCACHE = 0x00010000, | ||
| 120 | ATH_DBG_AGGR = 0x00020000, | ||
| 121 | ATH_DBG_FATAL = 0x00040000, | ||
| 122 | ATH_DBG_ANY = 0xffffffff | ||
| 123 | }; | ||
| 124 | |||
| 125 | #define DBG_DEFAULT (ATH_DBG_FATAL) | ||
| 126 | |||
| 127 | #define DPRINTF(sc, _m, _fmt, ...) do { \ | ||
| 128 | if (sc->sc_debug & (_m)) \ | ||
| 129 | printk(_fmt , ##__VA_ARGS__); \ | ||
| 130 | } while (0) | ||
| 131 | |||
| 132 | /***************************/ | ||
| 133 | /* Load-time Configuration */ | ||
| 134 | /***************************/ | ||
| 135 | |||
| 136 | /* Per-instance load-time (note: NOT run-time) configurations | ||
| 137 | * for Atheros Device */ | ||
| 138 | struct ath_config { | ||
| 139 | u32 ath_aggr_prot; | ||
| 140 | u16 txpowlimit; | ||
| 141 | u16 txpowlimit_override; | ||
| 142 | u8 cabqReadytime; /* Cabq Readytime % */ | ||
| 143 | u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */ | ||
| 144 | }; | ||
| 145 | |||
| 146 | /***********************/ | ||
| 147 | /* Chainmask Selection */ | ||
| 148 | /***********************/ | ||
| 149 | |||
| 150 | #define ATH_CHAINMASK_SEL_TIMEOUT 6000 | ||
| 151 | /* Default - Number of last RSSI values that is used for | ||
| 152 | * chainmask selection */ | ||
| 153 | #define ATH_CHAINMASK_SEL_RSSI_CNT 10 | ||
| 154 | /* Means use 3x3 chainmask instead of configured chainmask */ | ||
| 155 | #define ATH_CHAINMASK_SEL_3X3 7 | ||
| 156 | /* Default - Rssi threshold below which we have to switch to 3x3 */ | ||
| 157 | #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20 | ||
| 158 | /* Default - Rssi threshold above which we have to switch to | ||
| 159 | * user configured values */ | ||
| 160 | #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35 | ||
| 161 | /* Struct to store the chainmask select related info */ | ||
| 162 | struct ath_chainmask_sel { | ||
| 163 | struct timer_list timer; | ||
| 164 | int cur_tx_mask; /* user configured or 3x3 */ | ||
| 165 | int cur_rx_mask; /* user configured or 3x3 */ | ||
| 166 | int tx_avgrssi; | ||
| 167 | u8 switch_allowed:1, /* timer will set this */ | ||
| 168 | cm_sel_enabled : 1; | ||
| 169 | }; | ||
| 170 | |||
| 171 | int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an); | ||
| 172 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | ||
| 173 | |||
| 174 | /*************************/ | ||
| 175 | /* Descriptor Management */ | ||
| 176 | /*************************/ | ||
| 177 | |||
| 178 | /* Number of descriptors per buffer. The only case where we see skbuff | ||
| 179 | chains is due to FF aggregation in the driver. */ | ||
| 180 | #define ATH_TXDESC 1 | ||
| 181 | /* if there's more fragment for this MSDU */ | ||
| 182 | #define ATH_BF_MORE_MPDU 1 | ||
| 183 | #define ATH_TXBUF_RESET(_bf) do { \ | ||
| 184 | (_bf)->bf_status = 0; \ | ||
| 185 | (_bf)->bf_lastbf = NULL; \ | ||
| 186 | (_bf)->bf_lastfrm = NULL; \ | ||
| 187 | (_bf)->bf_next = NULL; \ | ||
| 188 | memzero(&((_bf)->bf_state), \ | ||
| 189 | sizeof(struct ath_buf_state)); \ | ||
| 190 | } while (0) | ||
| 191 | |||
| 192 | struct ath_buf_state { | ||
| 193 | int bfs_nframes; /* # frames in aggregate */ | ||
| 194 | u16 bfs_al; /* length of aggregate */ | ||
| 195 | u16 bfs_frmlen; /* length of frame */ | ||
| 196 | int bfs_seqno; /* sequence number */ | ||
| 197 | int bfs_tidno; /* tid of this frame */ | ||
| 198 | int bfs_retries; /* current retries */ | ||
| 199 | struct ath_rc_series bfs_rcs[4]; /* rate series */ | ||
| 200 | u8 bfs_isdata:1; /* is a data frame/aggregate */ | ||
| 201 | u8 bfs_isaggr:1; /* is an aggregate */ | ||
| 202 | u8 bfs_isampdu:1; /* is an a-mpdu, aggregate or not */ | ||
| 203 | u8 bfs_ht:1; /* is an HT frame */ | ||
| 204 | u8 bfs_isretried:1; /* is retried */ | ||
| 205 | u8 bfs_isxretried:1; /* is excessive retried */ | ||
| 206 | u8 bfs_shpreamble:1; /* is short preamble */ | ||
| 207 | u8 bfs_isbar:1; /* is a BAR */ | ||
| 208 | u8 bfs_ispspoll:1; /* is a PS-Poll */ | ||
| 209 | u8 bfs_aggrburst:1; /* is a aggr burst */ | ||
| 210 | u8 bfs_calcairtime:1; /* requests airtime be calculated | ||
| 211 | when set for tx frame */ | ||
| 212 | int bfs_rifsburst_elem; /* RIFS burst/bar */ | ||
| 213 | int bfs_nrifsubframes; /* # of elements in burst */ | ||
| 214 | /* key type use to encrypt this frame */ | ||
| 215 | enum ath9k_key_type bfs_keytype; | ||
| 216 | }; | ||
| 217 | |||
| 218 | #define bf_nframes bf_state.bfs_nframes | ||
| 219 | #define bf_al bf_state.bfs_al | ||
| 220 | #define bf_frmlen bf_state.bfs_frmlen | ||
| 221 | #define bf_retries bf_state.bfs_retries | ||
| 222 | #define bf_seqno bf_state.bfs_seqno | ||
| 223 | #define bf_tidno bf_state.bfs_tidno | ||
| 224 | #define bf_rcs bf_state.bfs_rcs | ||
| 225 | #define bf_isdata bf_state.bfs_isdata | ||
| 226 | #define bf_isaggr bf_state.bfs_isaggr | ||
| 227 | #define bf_isampdu bf_state.bfs_isampdu | ||
| 228 | #define bf_ht bf_state.bfs_ht | ||
| 229 | #define bf_isretried bf_state.bfs_isretried | ||
| 230 | #define bf_isxretried bf_state.bfs_isxretried | ||
| 231 | #define bf_shpreamble bf_state.bfs_shpreamble | ||
| 232 | #define bf_rifsburst_elem bf_state.bfs_rifsburst_elem | ||
| 233 | #define bf_nrifsubframes bf_state.bfs_nrifsubframes | ||
| 234 | #define bf_keytype bf_state.bfs_keytype | ||
| 235 | #define bf_isbar bf_state.bfs_isbar | ||
| 236 | #define bf_ispspoll bf_state.bfs_ispspoll | ||
| 237 | #define bf_aggrburst bf_state.bfs_aggrburst | ||
| 238 | #define bf_calcairtime bf_state.bfs_calcairtime | ||
| 239 | |||
| 240 | /* | ||
| 241 | * Abstraction of a contiguous buffer to transmit/receive. There is only | ||
| 242 | * a single hw descriptor encapsulated here. | ||
| 243 | */ | ||
| 244 | |||
| 245 | struct ath_buf { | ||
| 246 | struct list_head list; | ||
| 247 | struct list_head *last; | ||
| 248 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | ||
| 249 | an aggregate) */ | ||
| 250 | struct ath_buf *bf_lastfrm; /* last buf of this frame */ | ||
| 251 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | ||
| 252 | struct ath_buf *bf_rifslast; /* last buf for RIFS burst */ | ||
| 253 | void *bf_mpdu; /* enclosing frame structure */ | ||
| 254 | void *bf_node; /* pointer to the node */ | ||
| 255 | struct ath_desc *bf_desc; /* virtual addr of desc */ | ||
| 256 | dma_addr_t bf_daddr; /* physical addr of desc */ | ||
| 257 | dma_addr_t bf_buf_addr; /* physical addr of data buffer */ | ||
| 258 | u32 bf_status; | ||
| 259 | u16 bf_flags; /* tx descriptor flags */ | ||
| 260 | struct ath_buf_state bf_state; /* buffer state */ | ||
| 261 | dma_addr_t bf_dmacontext; | ||
| 262 | }; | ||
| 263 | |||
| 264 | /* | ||
| 265 | * reset the rx buffer. | ||
| 266 | * any new fields added to the athbuf and require | ||
| 267 | * reset need to be added to this macro. | ||
| 268 | * currently bf_status is the only one requires that | ||
| 269 | * requires reset. | ||
| 270 | */ | ||
| 271 | #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) | ||
| 272 | |||
| 273 | /* hw processing complete, desc processed by hal */ | ||
| 274 | #define ATH_BUFSTATUS_DONE 0x00000001 | ||
| 275 | /* hw processing complete, desc hold for hw */ | ||
| 276 | #define ATH_BUFSTATUS_STALE 0x00000002 | ||
| 277 | /* Rx-only: OS is done with this packet and it's ok to queued it to hw */ | ||
| 278 | #define ATH_BUFSTATUS_FREE 0x00000004 | ||
| 279 | |||
| 280 | /* DMA state for tx/rx descriptors */ | ||
| 281 | |||
| 282 | struct ath_descdma { | ||
| 283 | const char *dd_name; | ||
| 284 | struct ath_desc *dd_desc; /* descriptors */ | ||
| 285 | dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ | ||
| 286 | u32 dd_desc_len; /* size of dd_desc */ | ||
| 287 | struct ath_buf *dd_bufptr; /* associated buffers */ | ||
| 288 | dma_addr_t dd_dmacontext; | ||
| 289 | }; | ||
| 290 | |||
| 291 | /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */ | ||
| 292 | |||
| 293 | struct ath_rx_context { | ||
| 294 | struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */ | ||
| 295 | }; | ||
| 296 | #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb) | ||
| 297 | |||
| 298 | int ath_descdma_setup(struct ath_softc *sc, | ||
| 299 | struct ath_descdma *dd, | ||
| 300 | struct list_head *head, | ||
| 301 | const char *name, | ||
| 302 | int nbuf, | ||
| 303 | int ndesc); | ||
| 304 | int ath_desc_alloc(struct ath_softc *sc); | ||
| 305 | void ath_desc_free(struct ath_softc *sc); | ||
| 306 | void ath_descdma_cleanup(struct ath_softc *sc, | ||
| 307 | struct ath_descdma *dd, | ||
| 308 | struct list_head *head); | ||
| 309 | |||
| 310 | /******/ | ||
| 311 | /* RX */ | ||
| 312 | /******/ | ||
| 313 | |||
| 314 | #define ATH_MAX_ANTENNA 3 | ||
| 315 | #define ATH_RXBUF 512 | ||
| 316 | #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */ | ||
| 317 | #define WME_NUM_TID 16 | ||
| 318 | #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */ | ||
| 319 | #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */ | ||
| 320 | |||
| 321 | enum ATH_RX_TYPE { | ||
| 322 | ATH_RX_NON_CONSUMED = 0, | ||
| 323 | ATH_RX_CONSUMED | ||
| 324 | }; | ||
| 325 | |||
| 326 | /* per frame rx status block */ | ||
| 327 | struct ath_recv_status { | ||
| 328 | u64 tsf; /* mac tsf */ | ||
| 329 | int8_t rssi; /* RSSI (noise floor ajusted) */ | ||
| 330 | int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ | ||
| 331 | int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ | ||
| 332 | int8_t abs_rssi; /* absolute RSSI */ | ||
| 333 | u8 rateieee; /* data rate received (IEEE rate code) */ | ||
| 334 | u8 ratecode; /* phy rate code */ | ||
| 335 | int rateKbps; /* data rate received (Kbps) */ | ||
| 336 | int antenna; /* rx antenna */ | ||
| 337 | int flags; /* status of associated skb */ | ||
| 338 | #define ATH_RX_FCS_ERROR 0x01 | ||
| 339 | #define ATH_RX_MIC_ERROR 0x02 | ||
| 340 | #define ATH_RX_DECRYPT_ERROR 0x04 | ||
| 341 | #define ATH_RX_RSSI_VALID 0x08 | ||
| 342 | /* if any of ctl,extn chainrssis are valid */ | ||
| 343 | #define ATH_RX_CHAIN_RSSI_VALID 0x10 | ||
| 344 | /* if extn chain rssis are valid */ | ||
| 345 | #define ATH_RX_RSSI_EXTN_VALID 0x20 | ||
| 346 | /* set if 40Mhz, clear if 20Mhz */ | ||
| 347 | #define ATH_RX_40MHZ 0x40 | ||
| 348 | /* set if short GI, clear if full GI */ | ||
| 349 | #define ATH_RX_SHORT_GI 0x80 | ||
| 350 | }; | ||
| 351 | |||
| 352 | struct ath_rxbuf { | ||
| 353 | struct sk_buff *rx_wbuf; | ||
| 354 | unsigned long rx_time; /* system time when received */ | ||
| 355 | struct ath_recv_status rx_status; /* cached rx status */ | ||
| 356 | }; | ||
| 357 | |||
| 358 | /* Per-TID aggregate receiver state for a node */ | ||
| 359 | struct ath_arx_tid { | ||
| 360 | struct ath_node *an; | ||
| 361 | struct ath_rxbuf *rxbuf; /* re-ordering buffer */ | ||
| 362 | struct timer_list timer; | ||
| 363 | spinlock_t tidlock; | ||
| 364 | int baw_head; /* seq_next at head */ | ||
| 365 | int baw_tail; /* tail of block-ack window */ | ||
| 366 | int seq_reset; /* need to reset start sequence */ | ||
| 367 | int addba_exchangecomplete; | ||
| 368 | u16 seq_next; /* next expected sequence */ | ||
| 369 | u16 baw_size; /* block-ack window size */ | ||
| 370 | }; | ||
| 371 | |||
| 372 | /* Per-node receiver aggregate state */ | ||
| 373 | struct ath_arx { | ||
| 374 | struct ath_arx_tid tid[WME_NUM_TID]; | ||
| 375 | }; | ||
| 376 | |||
| 377 | int ath_startrecv(struct ath_softc *sc); | ||
| 378 | bool ath_stoprecv(struct ath_softc *sc); | ||
| 379 | void ath_flushrecv(struct ath_softc *sc); | ||
| 380 | u32 ath_calcrxfilter(struct ath_softc *sc); | ||
| 381 | void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an); | ||
| 382 | void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an); | ||
| 383 | void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | ||
| 384 | void ath_handle_rx_intr(struct ath_softc *sc); | ||
| 385 | int ath_rx_init(struct ath_softc *sc, int nbufs); | ||
| 386 | void ath_rx_cleanup(struct ath_softc *sc); | ||
| 387 | int ath_rx_tasklet(struct ath_softc *sc, int flush); | ||
| 388 | int ath_rx_input(struct ath_softc *sc, | ||
| 389 | struct ath_node *node, | ||
| 390 | int is_ampdu, | ||
| 391 | struct sk_buff *skb, | ||
| 392 | struct ath_recv_status *rx_status, | ||
| 393 | enum ATH_RX_TYPE *status); | ||
| 394 | int ath__rx_indicate(struct ath_softc *sc, | ||
| 395 | struct sk_buff *skb, | ||
| 396 | struct ath_recv_status *status, | ||
| 397 | u16 keyix); | ||
| 398 | int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb, | ||
| 399 | struct ath_recv_status *status); | ||
| 400 | |||
| 401 | /******/ | ||
| 402 | /* TX */ | ||
| 403 | /******/ | ||
| 404 | |||
| 405 | #define ATH_FRAG_PER_MSDU 1 | ||
| 406 | #define ATH_TXBUF (512/ATH_FRAG_PER_MSDU) | ||
| 407 | /* max number of transmit attempts (tries) */ | ||
| 408 | #define ATH_TXMAXTRY 13 | ||
| 409 | /* max number of 11n transmit attempts (tries) */ | ||
| 410 | #define ATH_11N_TXMAXTRY 10 | ||
| 411 | /* max number of tries for management and control frames */ | ||
| 412 | #define ATH_MGT_TXMAXTRY 4 | ||
| 413 | #define WME_BA_BMP_SIZE 64 | ||
| 414 | #define WME_MAX_BA WME_BA_BMP_SIZE | ||
| 415 | #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) | ||
| 416 | #define TID_TO_WME_AC(_tid) \ | ||
| 417 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | ||
| 418 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | ||
| 419 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | ||
| 420 | WME_AC_VO) | ||
| 421 | |||
| 422 | |||
| 423 | /* Wireless Multimedia Extension Defines */ | ||
| 424 | #define WME_AC_BE 0 /* best effort */ | ||
| 425 | #define WME_AC_BK 1 /* background */ | ||
| 426 | #define WME_AC_VI 2 /* video */ | ||
| 427 | #define WME_AC_VO 3 /* voice */ | ||
| 428 | #define WME_NUM_AC 4 | ||
| 429 | |||
| 430 | enum ATH_SM_PWRSAV{ | ||
| 431 | ATH_SM_ENABLE, | ||
| 432 | ATH_SM_PWRSAV_STATIC, | ||
| 433 | ATH_SM_PWRSAV_DYNAMIC, | ||
| 434 | }; | ||
| 435 | |||
| 436 | /* | ||
| 437 | * Data transmit queue state. One of these exists for each | ||
| 438 | * hardware transmit queue. Packets sent to us from above | ||
| 439 | * are assigned to queues based on their priority. Not all | ||
| 440 | * devices support a complete set of hardware transmit queues. | ||
| 441 | * For those devices the array sc_ac2q will map multiple | ||
| 442 | * priorities to fewer hardware queues (typically all to one | ||
| 443 | * hardware queue). | ||
| 444 | */ | ||
| 445 | struct ath_txq { | ||
| 446 | u32 axq_qnum; /* hardware q number */ | ||
| 447 | u32 *axq_link; /* link ptr in last TX desc */ | ||
| 448 | struct list_head axq_q; /* transmit queue */ | ||
| 449 | spinlock_t axq_lock; | ||
| 450 | unsigned long axq_lockflags; /* intr state when must cli */ | ||
| 451 | u32 axq_depth; /* queue depth */ | ||
| 452 | u8 axq_aggr_depth; /* aggregates queued */ | ||
| 453 | u32 axq_totalqueued; /* total ever queued */ | ||
| 454 | |||
| 455 | /* count to determine if descriptor should generate int on this txq. */ | ||
| 456 | u32 axq_intrcnt; | ||
| 457 | |||
| 458 | bool stopped; /* Is mac80211 queue stopped ? */ | ||
| 459 | struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ | ||
| 460 | |||
| 461 | /* first desc of the last descriptor that contains CTS */ | ||
| 462 | struct ath_desc *axq_lastdsWithCTS; | ||
| 463 | |||
| 464 | /* final desc of the gating desc that determines whether | ||
| 465 | lastdsWithCTS has been DMA'ed or not */ | ||
| 466 | struct ath_desc *axq_gatingds; | ||
| 467 | |||
| 468 | struct list_head axq_acq; | ||
| 469 | }; | ||
| 470 | |||
| 471 | /* per TID aggregate tx state for a destination */ | ||
| 472 | struct ath_atx_tid { | ||
| 473 | struct list_head list; /* round-robin tid entry */ | ||
| 474 | struct list_head buf_q; /* pending buffers */ | ||
| 475 | struct ath_node *an; | ||
| 476 | struct ath_atx_ac *ac; | ||
| 477 | struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ | ||
| 478 | u16 seq_start; | ||
| 479 | u16 seq_next; | ||
| 480 | u16 baw_size; | ||
| 481 | int tidno; | ||
| 482 | int baw_head; /* first un-acked tx buffer */ | ||
| 483 | int baw_tail; /* next unused tx buffer slot */ | ||
| 484 | int sched; | ||
| 485 | int paused; | ||
| 486 | int cleanup_inprogress; | ||
| 487 | u32 addba_exchangecomplete:1; | ||
| 488 | int32_t addba_exchangeinprogress; | ||
| 489 | int addba_exchangeattempts; | ||
| 490 | }; | ||
| 491 | |||
| 492 | /* per access-category aggregate tx state for a destination */ | ||
| 493 | struct ath_atx_ac { | ||
| 494 | int sched; /* dest-ac is scheduled */ | ||
| 495 | int qnum; /* H/W queue number associated | ||
| 496 | with this AC */ | ||
| 497 | struct list_head list; /* round-robin txq entry */ | ||
| 498 | struct list_head tid_q; /* queue of TIDs with buffers */ | ||
| 499 | }; | ||
| 500 | |||
| 501 | /* per dest tx state */ | ||
| 502 | struct ath_atx { | ||
| 503 | struct ath_atx_tid tid[WME_NUM_TID]; | ||
| 504 | struct ath_atx_ac ac[WME_NUM_AC]; | ||
| 505 | }; | ||
| 506 | |||
| 507 | /* per-frame tx control block */ | ||
| 508 | struct ath_tx_control { | ||
| 509 | struct ath_node *an; | ||
| 510 | int if_id; | ||
| 511 | int qnum; | ||
| 512 | u32 ht:1; | ||
| 513 | u32 ps:1; | ||
| 514 | u32 use_minrate:1; | ||
| 515 | enum ath9k_pkt_type atype; | ||
| 516 | enum ath9k_key_type keytype; | ||
| 517 | u32 flags; | ||
| 518 | u16 seqno; | ||
| 519 | u16 tidno; | ||
| 520 | u16 txpower; | ||
| 521 | u16 frmlen; | ||
| 522 | u32 keyix; | ||
| 523 | int min_rate; | ||
| 524 | int mcast_rate; | ||
| 525 | u16 nextfraglen; | ||
| 526 | struct ath_softc *dev; | ||
| 527 | dma_addr_t dmacontext; | ||
| 528 | }; | ||
| 529 | |||
| 530 | /* per frame tx status block */ | ||
| 531 | struct ath_xmit_status { | ||
| 532 | int retries; /* number of retries to successufully | ||
| 533 | transmit this frame */ | ||
| 534 | int flags; /* status of transmit */ | ||
| 535 | #define ATH_TX_ERROR 0x01 | ||
| 536 | #define ATH_TX_XRETRY 0x02 | ||
| 537 | #define ATH_TX_BAR 0x04 | ||
| 538 | }; | ||
| 539 | |||
| 540 | struct ath_tx_stat { | ||
| 541 | int rssi; /* RSSI (noise floor ajusted) */ | ||
| 542 | int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ | ||
| 543 | int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ | ||
| 544 | int rateieee; /* data rate xmitted (IEEE rate code) */ | ||
| 545 | int rateKbps; /* data rate xmitted (Kbps) */ | ||
| 546 | int ratecode; /* phy rate code */ | ||
| 547 | int flags; /* validity flags */ | ||
| 548 | /* if any of ctl,extn chain rssis are valid */ | ||
| 549 | #define ATH_TX_CHAIN_RSSI_VALID 0x01 | ||
| 550 | /* if extn chain rssis are valid */ | ||
| 551 | #define ATH_TX_RSSI_EXTN_VALID 0x02 | ||
| 552 | u32 airtime; /* time on air per final tx rate */ | ||
| 553 | }; | ||
| 554 | |||
| 555 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); | ||
| 556 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | ||
| 557 | int ath_tx_setup(struct ath_softc *sc, int haltype); | ||
| 558 | void ath_draintxq(struct ath_softc *sc, bool retry_tx); | ||
| 559 | void ath_tx_draintxq(struct ath_softc *sc, | ||
| 560 | struct ath_txq *txq, bool retry_tx); | ||
| 561 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | ||
| 562 | void ath_tx_node_cleanup(struct ath_softc *sc, | ||
| 563 | struct ath_node *an, bool bh_flag); | ||
| 564 | void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an); | ||
| 565 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | ||
| 566 | int ath_tx_init(struct ath_softc *sc, int nbufs); | ||
| 567 | int ath_tx_cleanup(struct ath_softc *sc); | ||
| 568 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); | ||
| 569 | int ath_txq_update(struct ath_softc *sc, int qnum, | ||
| 570 | struct ath9k_tx_queue_info *q); | ||
| 571 | int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb); | ||
| 572 | void ath_tx_tasklet(struct ath_softc *sc); | ||
| 573 | u32 ath_txq_depth(struct ath_softc *sc, int qnum); | ||
| 574 | u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum); | ||
| 575 | void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth); | ||
| 576 | void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | ||
| 577 | struct ath_xmit_status *tx_status, struct ath_node *an); | ||
| 578 | |||
| 579 | /**********************/ | ||
| 580 | /* Node / Aggregation */ | ||
| 581 | /**********************/ | ||
| 582 | |||
| 583 | /* indicates the node is clened up */ | ||
| 584 | #define ATH_NODE_CLEAN 0x1 | ||
| 585 | /* indicates the node is 80211 power save */ | ||
| 586 | #define ATH_NODE_PWRSAVE 0x2 | ||
| 587 | |||
| 588 | #define ADDBA_TIMEOUT 200 /* 200 milliseconds */ | ||
| 589 | #define ADDBA_EXCHANGE_ATTEMPTS 10 | ||
| 590 | #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ | ||
| 591 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | ||
| 592 | /* number of delimiters for encryption padding */ | ||
| 593 | #define ATH_AGGR_ENCRYPTDELIM 10 | ||
| 594 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | ||
| 595 | #define ATH_AGGR_MIN_QDEPTH 2 | ||
| 596 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | ||
| 597 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | ||
| 598 | #define IEEE80211_SEQ_MAX 4096 | ||
| 599 | #define IEEE80211_MIN_AMPDU_BUF 0x8 | ||
| 600 | |||
| 601 | /* return whether a bit at index _n in bitmap _bm is set | ||
| 602 | * _sz is the size of the bitmap */ | ||
| 603 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | ||
| 604 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | ||
| 605 | |||
| 606 | /* return block-ack bitmap index given sequence and starting sequence */ | ||
| 607 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | ||
| 608 | |||
| 609 | /* returns delimiter padding required given the packet length */ | ||
| 610 | #define ATH_AGGR_GET_NDELIM(_len) \ | ||
| 611 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | ||
| 612 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | ||
| 613 | |||
| 614 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | ||
| 615 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | ||
| 616 | |||
| 617 | #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) | ||
| 618 | #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) | ||
| 619 | #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) | ||
| 620 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)]) | ||
| 621 | |||
| 622 | enum ATH_AGGR_STATUS { | ||
| 623 | ATH_AGGR_DONE, | ||
| 624 | ATH_AGGR_BAW_CLOSED, | ||
| 625 | ATH_AGGR_LIMITED, | ||
| 626 | ATH_AGGR_SHORTPKT, | ||
| 627 | ATH_AGGR_8K_LIMITED, | ||
| 628 | }; | ||
| 629 | |||
| 630 | enum ATH_AGGR_CHECK { | ||
| 631 | AGGR_NOT_REQUIRED, | ||
| 632 | AGGR_REQUIRED, | ||
| 633 | AGGR_CLEANUP_PROGRESS, | ||
| 634 | AGGR_EXCHANGE_PROGRESS, | ||
| 635 | AGGR_EXCHANGE_DONE | ||
| 636 | }; | ||
| 637 | |||
| 638 | struct aggr_rifs_param { | ||
| 639 | int param_max_frames; | ||
| 640 | int param_max_len; | ||
| 641 | int param_rl; | ||
| 642 | int param_al; | ||
| 643 | struct ath_rc_series *param_rcs; | ||
| 644 | }; | ||
| 645 | |||
| 646 | /* Per-node aggregation state */ | ||
| 647 | struct ath_node_aggr { | ||
| 648 | struct ath_atx tx; /* node transmit state */ | ||
| 649 | struct ath_arx rx; /* node receive state */ | ||
| 650 | }; | ||
| 651 | |||
| 652 | /* driver-specific node state */ | ||
| 653 | struct ath_node { | ||
| 654 | struct list_head list; | ||
| 655 | struct ath_softc *an_sc; | ||
| 656 | atomic_t an_refcnt; | ||
| 657 | struct ath_chainmask_sel an_chainmask_sel; | ||
| 658 | struct ath_node_aggr an_aggr; | ||
| 659 | u8 an_smmode; /* SM Power save mode */ | ||
| 660 | u8 an_flags; | ||
| 661 | u8 an_addr[ETH_ALEN]; | ||
| 662 | }; | ||
| 663 | |||
| 664 | void ath_tx_resume_tid(struct ath_softc *sc, | ||
| 665 | struct ath_atx_tid *tid); | ||
| 666 | enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc, | ||
| 667 | struct ath_node *an, u8 tidno); | ||
| 668 | void ath_tx_aggr_teardown(struct ath_softc *sc, | ||
| 669 | struct ath_node *an, u8 tidno); | ||
| 670 | void ath_rx_aggr_teardown(struct ath_softc *sc, | ||
| 671 | struct ath_node *an, u8 tidno); | ||
| 672 | int ath_rx_aggr_start(struct ath_softc *sc, | ||
| 673 | const u8 *addr, | ||
| 674 | u16 tid, | ||
| 675 | u16 *ssn); | ||
| 676 | int ath_rx_aggr_stop(struct ath_softc *sc, | ||
| 677 | const u8 *addr, | ||
| 678 | u16 tid); | ||
| 679 | int ath_tx_aggr_start(struct ath_softc *sc, | ||
| 680 | const u8 *addr, | ||
| 681 | u16 tid, | ||
| 682 | u16 *ssn); | ||
| 683 | int ath_tx_aggr_stop(struct ath_softc *sc, | ||
| 684 | const u8 *addr, | ||
| 685 | u16 tid); | ||
| 686 | void ath_newassoc(struct ath_softc *sc, | ||
| 687 | struct ath_node *node, int isnew, int isuapsd); | ||
| 688 | struct ath_node *ath_node_attach(struct ath_softc *sc, | ||
| 689 | u8 addr[ETH_ALEN], int if_id); | ||
| 690 | void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag); | ||
| 691 | struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]); | ||
| 692 | void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag); | ||
| 693 | struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr); | ||
| 694 | |||
| 695 | /*******************/ | ||
| 696 | /* Beacon Handling */ | ||
| 697 | /*******************/ | ||
| 698 | |||
| 699 | /* | ||
| 700 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | ||
| 701 | * number of BSSIDs) if a given beacon does not go out even after waiting this | ||
| 702 | * number of beacon intervals, the game's up. | ||
| 703 | */ | ||
| 704 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | ||
| 705 | #define ATH_BCBUF 4 /* number of beacon buffers */ | ||
| 706 | #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */ | ||
| 707 | #define ATH_DEFAULT_BMISS_LIMIT 10 | ||
| 708 | #define ATH_BEACON_AIFS_DEFAULT 0 /* Default aifs for ap beacon q */ | ||
| 709 | #define ATH_BEACON_CWMIN_DEFAULT 0 /* Default cwmin for ap beacon q */ | ||
| 710 | #define ATH_BEACON_CWMAX_DEFAULT 0 /* Default cwmax for ap beacon q */ | ||
| 711 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | ||
| 712 | |||
| 713 | /* beacon configuration */ | ||
| 714 | struct ath_beacon_config { | ||
| 715 | u16 beacon_interval; | ||
| 716 | u16 listen_interval; | ||
| 717 | u16 dtim_period; | ||
| 718 | u16 bmiss_timeout; | ||
| 719 | u8 dtim_count; | ||
| 720 | u8 tim_offset; | ||
| 721 | union { | ||
| 722 | u64 last_tsf; | ||
| 723 | u8 last_tstamp[8]; | ||
| 724 | } u; /* last received beacon/probe response timestamp of this BSS. */ | ||
| 725 | }; | ||
| 726 | |||
| 727 | /* offsets in a beacon frame for | ||
| 728 | * quick acess of beacon content by low-level driver */ | ||
| 729 | struct ath_beacon_offset { | ||
| 730 | u8 *bo_tim; /* start of atim/dtim */ | ||
| 731 | }; | ||
| 732 | |||
| 733 | void ath9k_beacon_tasklet(unsigned long data); | ||
| 734 | void ath_beacon_config(struct ath_softc *sc, int if_id); | ||
| 735 | int ath_beaconq_setup(struct ath_hal *ah); | ||
| 736 | int ath_beacon_alloc(struct ath_softc *sc, int if_id); | ||
| 737 | void ath_bstuck_process(struct ath_softc *sc); | ||
| 738 | void ath_beacon_tasklet(struct ath_softc *sc, int *needmark); | ||
| 739 | void ath_beacon_free(struct ath_softc *sc); | ||
| 740 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp); | ||
| 741 | void ath_beacon_sync(struct ath_softc *sc, int if_id); | ||
| 742 | void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi); | ||
| 743 | void ath_get_beaconconfig(struct ath_softc *sc, | ||
| 744 | int if_id, | ||
| 745 | struct ath_beacon_config *conf); | ||
| 746 | int ath_update_beacon(struct ath_softc *sc, | ||
| 747 | int if_id, | ||
| 748 | struct ath_beacon_offset *bo, | ||
| 749 | struct sk_buff *skb, | ||
| 750 | int mcast); | ||
| 751 | /********/ | ||
| 752 | /* VAPs */ | ||
| 753 | /********/ | ||
| 754 | |||
| 755 | /* | ||
| 756 | * Define the scheme that we select MAC address for multiple | ||
| 757 | * BSS on the same radio. The very first VAP will just use the MAC | ||
| 758 | * address from the EEPROM. For the next 3 VAPs, we set the | ||
| 759 | * U/L bit (bit 1) in MAC address, and use the next two bits as the | ||
| 760 | * index of the VAP. | ||
| 761 | */ | ||
| 762 | |||
| 763 | #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ | ||
| 764 | ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) | ||
| 765 | |||
| 766 | /* VAP configuration (from protocol layer) */ | ||
| 767 | struct ath_vap_config { | ||
| 768 | u32 av_fixed_rateset; | ||
| 769 | u32 av_fixed_retryset; | ||
| 770 | }; | ||
| 771 | |||
| 772 | /* driver-specific vap state */ | ||
| 773 | struct ath_vap { | ||
| 774 | struct ieee80211_vif *av_if_data; | ||
| 775 | enum ath9k_opmode av_opmode; /* VAP operational mode */ | ||
| 776 | struct ath_buf *av_bcbuf; /* beacon buffer */ | ||
| 777 | struct ath_beacon_offset av_boff; /* dynamic update state */ | ||
| 778 | struct ath_tx_control av_btxctl; /* txctl information for beacon */ | ||
| 779 | int av_bslot; /* beacon slot index */ | ||
| 780 | struct ath_txq av_mcastq; /* multicast transmit queue */ | ||
| 781 | struct ath_vap_config av_config;/* vap configuration parameters*/ | ||
| 782 | struct ath_rate_node *rc_node; | ||
| 783 | }; | ||
| 784 | |||
| 785 | int ath_vap_attach(struct ath_softc *sc, | ||
| 786 | int if_id, | ||
| 787 | struct ieee80211_vif *if_data, | ||
| 788 | enum ath9k_opmode opmode); | ||
| 789 | int ath_vap_detach(struct ath_softc *sc, int if_id); | ||
| 790 | int ath_vap_config(struct ath_softc *sc, | ||
| 791 | int if_id, struct ath_vap_config *if_config); | ||
| 792 | int ath_vap_listen(struct ath_softc *sc, int if_id); | ||
| 793 | |||
| 794 | /*********************/ | ||
| 795 | /* Antenna diversity */ | ||
| 796 | /*********************/ | ||
| 797 | |||
| 798 | #define ATH_ANT_DIV_MAX_CFG 2 | ||
| 799 | #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */ | ||
| 800 | #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */ | ||
| 801 | |||
| 802 | enum ATH_ANT_DIV_STATE{ | ||
| 803 | ATH_ANT_DIV_IDLE, | ||
| 804 | ATH_ANT_DIV_SCAN, /* evaluating antenna */ | ||
| 805 | }; | ||
| 806 | |||
| 807 | struct ath_antdiv { | ||
| 808 | struct ath_softc *antdiv_sc; | ||
| 809 | u8 antdiv_start; | ||
| 810 | enum ATH_ANT_DIV_STATE antdiv_state; | ||
| 811 | u8 antdiv_num_antcfg; | ||
| 812 | u8 antdiv_curcfg; | ||
| 813 | u8 antdiv_bestcfg; | ||
| 814 | int32_t antdivf_rssitrig; | ||
| 815 | int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG]; | ||
| 816 | u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG]; | ||
| 817 | u64 antdiv_laststatetsf; | ||
| 818 | u8 antdiv_bssid[ETH_ALEN]; | ||
| 819 | }; | ||
| 820 | |||
| 821 | void ath_slow_ant_div_init(struct ath_antdiv *antdiv, | ||
| 822 | struct ath_softc *sc, int32_t rssitrig); | ||
| 823 | void ath_slow_ant_div_start(struct ath_antdiv *antdiv, | ||
| 824 | u8 num_antcfg, | ||
| 825 | const u8 *bssid); | ||
| 826 | void ath_slow_ant_div_stop(struct ath_antdiv *antdiv); | ||
| 827 | void ath_slow_ant_div(struct ath_antdiv *antdiv, | ||
| 828 | struct ieee80211_hdr *wh, | ||
| 829 | struct ath_rx_status *rx_stats); | ||
| 830 | void ath_setdefantenna(void *sc, u32 antenna); | ||
| 831 | |||
| 832 | /********************/ | ||
| 833 | /* Main driver core */ | ||
| 834 | /********************/ | ||
| 835 | |||
| 836 | /* | ||
| 837 | * Default cache line size, in bytes. | ||
| 838 | * Used when PCI device not fully initialized by bootrom/BIOS | ||
| 839 | */ | ||
| 840 | #define DEFAULT_CACHELINE 32 | ||
| 841 | #define ATH_DEFAULT_NOISE_FLOOR -95 | ||
| 842 | #define ATH_REGCLASSIDS_MAX 10 | ||
| 843 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | ||
| 844 | #define ATH_PREAMBLE_SHORT (1<<0) | ||
| 845 | #define ATH_PROTECT_ENABLE (1<<1) | ||
| 846 | #define ATH_MAX_SW_RETRIES 10 | ||
| 847 | /* Num farmes difference in tx to flip default recv */ | ||
| 848 | #define ATH_ANTENNA_DIFF 2 | ||
| 849 | #define ATH_CHAN_MAX 255 | ||
| 850 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | ||
| 851 | #define IEEE80211_RATE_VAL 0x7f | ||
| 852 | /* | ||
| 853 | * The key cache is used for h/w cipher state and also for | ||
| 854 | * tracking station state such as the current tx antenna. | ||
| 855 | * We also setup a mapping table between key cache slot indices | ||
| 856 | * and station state to short-circuit node lookups on rx. | ||
| 857 | * Different parts have different size key caches. We handle | ||
| 858 | * up to ATH_KEYMAX entries (could dynamically allocate state). | ||
| 859 | */ | ||
| 860 | #define ATH_KEYMAX 128 /* max key cache size we handle */ | ||
| 861 | |||
| 862 | #define RESET_RETRY_TXQ 0x00000001 | ||
| 863 | #define ATH_IF_ID_ANY 0xff | ||
| 864 | |||
| 865 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ | ||
| 866 | |||
| 867 | #define RSSI_LPF_THRESHOLD -20 | ||
| 868 | #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ | ||
| 869 | #define ATH_RATE_DUMMY_MARKER 0 | ||
| 870 | #define ATH_RSSI_LPF_LEN 10 | ||
| 871 | #define ATH_RSSI_DUMMY_MARKER 0x127 | ||
| 872 | |||
| 873 | #define ATH_EP_MUL(x, mul) ((x) * (mul)) | ||
| 874 | #define ATH_EP_RND(x, mul) \ | ||
| 875 | ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) | ||
| 876 | #define ATH_RSSI_OUT(x) \ | ||
| 877 | (((x) != ATH_RSSI_DUMMY_MARKER) ? \ | ||
| 878 | (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER) | ||
| 879 | #define ATH_RSSI_IN(x) \ | ||
| 880 | (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER)) | ||
| 881 | #define ATH_LPF_RSSI(x, y, len) \ | ||
| 882 | ((x != ATH_RSSI_DUMMY_MARKER) ? \ | ||
| 883 | (((x) * ((len) - 1) + (y)) / (len)) : (y)) | ||
| 884 | #define ATH_RSSI_LPF(x, y) do { \ | ||
| 885 | if ((y) >= RSSI_LPF_THRESHOLD) \ | ||
| 886 | x = ATH_LPF_RSSI((x), \ | ||
| 887 | ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ | ||
| 888 | } while (0) | ||
| 889 | |||
| 890 | |||
| 891 | enum PROT_MODE { | ||
| 892 | PROT_M_NONE = 0, | ||
| 893 | PROT_M_RTSCTS, | ||
| 894 | PROT_M_CTSONLY | ||
| 895 | }; | ||
| 896 | |||
| 897 | enum RATE_TYPE { | ||
| 898 | NORMAL_RATE = 0, | ||
| 899 | HALF_RATE, | ||
| 900 | QUARTER_RATE | ||
| 901 | }; | ||
| 902 | |||
| 903 | struct ath_ht_info { | ||
| 904 | enum ath9k_ht_macmode tx_chan_width; | ||
| 905 | u16 maxampdu; | ||
| 906 | u8 mpdudensity; | ||
| 907 | u8 ext_chan_offset; | ||
| 908 | }; | ||
| 909 | |||
| 910 | struct ath_softc { | ||
| 911 | struct ieee80211_hw *hw; | ||
| 912 | struct pci_dev *pdev; | ||
| 913 | void __iomem *mem; | ||
| 914 | struct tasklet_struct intr_tq; | ||
| 915 | struct tasklet_struct bcon_tasklet; | ||
| 916 | struct ath_config sc_config; /* load-time parameters */ | ||
| 917 | int sc_debug; | ||
| 918 | struct ath_hal *sc_ah; | ||
| 919 | struct ath_rate_softc *sc_rc; /* tx rate control support */ | ||
| 920 | u32 sc_intrstatus; | ||
| 921 | enum ath9k_opmode sc_opmode; /* current operating mode */ | ||
| 922 | |||
| 923 | u8 sc_invalid; /* being detached */ | ||
| 924 | u8 sc_beacons; /* beacons running */ | ||
| 925 | u8 sc_scanning; /* scanning active */ | ||
| 926 | u8 sc_txaggr; /* enable 11n tx aggregation */ | ||
| 927 | u8 sc_rxaggr; /* enable 11n rx aggregation */ | ||
| 928 | u8 sc_update_chainmask; /* change chain mask */ | ||
| 929 | u8 sc_full_reset; /* force full reset */ | ||
| 930 | enum wireless_mode sc_curmode; /* current phy mode */ | ||
| 931 | u16 sc_curtxpow; | ||
| 932 | u16 sc_curaid; | ||
| 933 | u8 sc_curbssid[ETH_ALEN]; | ||
| 934 | u8 sc_myaddr[ETH_ALEN]; | ||
| 935 | enum PROT_MODE sc_protmode; | ||
| 936 | u8 sc_mcastantenna; | ||
| 937 | u8 sc_txantenna; /* data tx antenna (fixed or auto) */ | ||
| 938 | u8 sc_nbcnvaps; /* # of vaps sending beacons */ | ||
| 939 | u16 sc_nvaps; /* # of active virtual ap's */ | ||
| 940 | struct ath_vap *sc_vaps[ATH_BCBUF]; | ||
| 941 | enum ath9k_int sc_imask; | ||
| 942 | u8 sc_bssidmask[ETH_ALEN]; | ||
| 943 | u8 sc_defant; /* current default antenna */ | ||
| 944 | u8 sc_rxotherant; /* rx's on non-default antenna */ | ||
| 945 | u16 sc_cachelsz; | ||
| 946 | int sc_slotupdate; /* slot to next advance fsm */ | ||
| 947 | int sc_slottime; | ||
| 948 | u8 sc_noreset; | ||
| 949 | int sc_bslot[ATH_BCBUF]; | ||
| 950 | struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ | ||
| 951 | struct list_head node_list; | ||
| 952 | struct ath_ht_info sc_ht_info; | ||
| 953 | int16_t sc_noise_floor; /* signal noise floor in dBm */ | ||
| 954 | enum ath9k_ht_extprotspacing sc_ht_extprotspacing; | ||
| 955 | u8 sc_tx_chainmask; | ||
| 956 | u8 sc_rx_chainmask; | ||
| 957 | u8 sc_rxchaindetect_ref; | ||
| 958 | u8 sc_rxchaindetect_thresh5GHz; | ||
| 959 | u8 sc_rxchaindetect_thresh2GHz; | ||
| 960 | u8 sc_rxchaindetect_delta5GHz; | ||
| 961 | u8 sc_rxchaindetect_delta2GHz; | ||
| 962 | u32 sc_rtsaggrlimit; /* Chipset specific aggr limit */ | ||
| 963 | u32 sc_flags; | ||
| 964 | #ifdef CONFIG_SLOW_ANT_DIV | ||
| 965 | struct ath_antdiv sc_antdiv; | ||
| 966 | #endif | ||
| 967 | enum { | ||
| 968 | OK, /* no change needed */ | ||
| 969 | UPDATE, /* update pending */ | ||
| 970 | COMMIT /* beacon sent, commit change */ | ||
| 971 | } sc_updateslot; /* slot time update fsm */ | ||
| 972 | |||
| 973 | /* Crypto */ | ||
| 974 | u32 sc_keymax; /* size of key cache */ | ||
| 975 | DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */ | ||
| 976 | u8 sc_splitmic; /* split TKIP MIC keys */ | ||
| 977 | int sc_keytype; | ||
| 978 | |||
| 979 | /* RX */ | ||
| 980 | struct list_head sc_rxbuf; | ||
| 981 | struct ath_descdma sc_rxdma; | ||
| 982 | int sc_rxbufsize; /* rx size based on mtu */ | ||
| 983 | u32 *sc_rxlink; /* link ptr in last RX desc */ | ||
| 984 | u32 sc_rxflush; /* rx flush in progress */ | ||
| 985 | u64 sc_lastrx; /* tsf of last rx'd frame */ | ||
| 986 | |||
| 987 | /* TX */ | ||
| 988 | struct list_head sc_txbuf; | ||
| 989 | struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; | ||
| 990 | struct ath_descdma sc_txdma; | ||
| 991 | u32 sc_txqsetup; | ||
| 992 | u32 sc_txintrperiod; /* tx interrupt batching */ | ||
| 993 | int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */ | ||
| 994 | u32 sc_ant_tx[8]; /* recent tx frames/antenna */ | ||
| 995 | |||
| 996 | /* Beacon */ | ||
| 997 | struct ath9k_tx_queue_info sc_beacon_qi; | ||
| 998 | struct ath_descdma sc_bdma; | ||
| 999 | struct ath_txq *sc_cabq; | ||
| 1000 | struct list_head sc_bbuf; | ||
| 1001 | u32 sc_bhalq; | ||
| 1002 | u32 sc_bmisscount; | ||
| 1003 | u32 ast_be_xmit; /* beacons transmitted */ | ||
| 1004 | |||
| 1005 | /* Rate */ | ||
| 1006 | struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; | ||
| 1007 | const struct ath9k_rate_table *sc_currates; | ||
| 1008 | u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */ | ||
| 1009 | u8 sc_protrix; /* protection rate index */ | ||
| 1010 | struct { | ||
| 1011 | u32 rateKbps; /* transfer rate in kbs */ | ||
| 1012 | u8 ieeerate; /* IEEE rate */ | ||
| 1013 | } sc_hwmap[256]; /* h/w rate ix mappings */ | ||
| 1014 | |||
| 1015 | /* Channel, Band */ | ||
| 1016 | struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX]; | ||
| 1017 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; | ||
| 1018 | struct ath9k_channel sc_curchan; | ||
| 1019 | |||
| 1020 | /* Locks */ | ||
| 1021 | spinlock_t sc_rxflushlock; | ||
| 1022 | spinlock_t sc_rxbuflock; | ||
| 1023 | spinlock_t sc_txbuflock; | ||
| 1024 | spinlock_t sc_resetlock; | ||
| 1025 | spinlock_t node_lock; | ||
| 1026 | }; | ||
| 1027 | |||
| 1028 | int ath_init(u16 devid, struct ath_softc *sc); | ||
| 1029 | void ath_deinit(struct ath_softc *sc); | ||
| 1030 | int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan); | ||
| 1031 | int ath_suspend(struct ath_softc *sc); | ||
| 1032 | irqreturn_t ath_isr(int irq, void *dev); | ||
| 1033 | int ath_reset(struct ath_softc *sc); | ||
| 1034 | void ath_scan_start(struct ath_softc *sc); | ||
| 1035 | void ath_scan_end(struct ath_softc *sc); | ||
| 1036 | int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan); | ||
| 1037 | void ath_setup_rate(struct ath_softc *sc, | ||
| 1038 | enum wireless_mode wMode, | ||
| 1039 | enum RATE_TYPE type, | ||
| 1040 | const struct ath9k_rate_table *rt); | ||
| 1041 | |||
| 1042 | /*********************/ | ||
| 1043 | /* Utility Functions */ | ||
| 1044 | /*********************/ | ||
| 1045 | |||
| 1046 | void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot); | ||
| 1047 | int ath_keyset(struct ath_softc *sc, | ||
| 1048 | u16 keyix, | ||
| 1049 | struct ath9k_keyval *hk, | ||
| 1050 | const u8 mac[ETH_ALEN]); | ||
| 1051 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | ||
| 1052 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | ||
| 1053 | void ath_setslottime(struct ath_softc *sc); | ||
| 1054 | void ath_update_txpow(struct ath_softc *sc); | ||
| 1055 | int ath_cabq_update(struct ath_softc *); | ||
| 1056 | void ath_get_currentCountry(struct ath_softc *sc, | ||
| 1057 | struct ath9k_country_entry *ctry); | ||
| 1058 | u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp); | ||
| 1059 | void ath_internal_reset(struct ath_softc *sc); | ||
| 1060 | u32 ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc); | ||
| 1061 | dma_addr_t ath_skb_map_single(struct ath_softc *sc, | ||
| 1062 | struct sk_buff *skb, | ||
| 1063 | int direction, | ||
| 1064 | dma_addr_t *pa); | ||
| 1065 | void ath_skb_unmap_single(struct ath_softc *sc, | ||
| 1066 | struct sk_buff *skb, | ||
| 1067 | int direction, | ||
| 1068 | dma_addr_t *pa); | ||
| 1069 | void ath_mcast_merge(struct ath_softc *sc, u32 mfilt[2]); | ||
| 1070 | enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc); | ||
| 1071 | |||
| 1072 | #endif /* CORE_H */ | ||
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c new file mode 100644 index 000000000000..bde162f128ab --- /dev/null +++ b/drivers/net/wireless/ath9k/hw.c | |||
| @@ -0,0 +1,8571 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/io.h> | ||
| 18 | #include <asm/unaligned.h> | ||
| 19 | |||
| 20 | #include "core.h" | ||
| 21 | #include "hw.h" | ||
| 22 | #include "reg.h" | ||
| 23 | #include "phy.h" | ||
| 24 | #include "initvals.h" | ||
| 25 | |||
| 26 | static void ath9k_hw_iqcal_collect(struct ath_hal *ah); | ||
| 27 | static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains); | ||
| 28 | static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah); | ||
| 29 | static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, | ||
| 30 | u8 numChains); | ||
| 31 | static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah); | ||
| 32 | static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, | ||
| 33 | u8 numChains); | ||
| 34 | |||
| 35 | static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 }; | ||
| 36 | static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 }; | ||
| 37 | |||
| 38 | static const struct hal_percal_data iq_cal_multi_sample = { | ||
| 39 | IQ_MISMATCH_CAL, | ||
| 40 | MAX_CAL_SAMPLES, | ||
| 41 | PER_MIN_LOG_COUNT, | ||
| 42 | ath9k_hw_iqcal_collect, | ||
| 43 | ath9k_hw_iqcalibrate | ||
| 44 | }; | ||
| 45 | static const struct hal_percal_data iq_cal_single_sample = { | ||
| 46 | IQ_MISMATCH_CAL, | ||
| 47 | MIN_CAL_SAMPLES, | ||
| 48 | PER_MAX_LOG_COUNT, | ||
| 49 | ath9k_hw_iqcal_collect, | ||
| 50 | ath9k_hw_iqcalibrate | ||
| 51 | }; | ||
| 52 | static const struct hal_percal_data adc_gain_cal_multi_sample = { | ||
| 53 | ADC_GAIN_CAL, | ||
| 54 | MAX_CAL_SAMPLES, | ||
| 55 | PER_MIN_LOG_COUNT, | ||
| 56 | ath9k_hw_adc_gaincal_collect, | ||
| 57 | ath9k_hw_adc_gaincal_calibrate | ||
| 58 | }; | ||
| 59 | static const struct hal_percal_data adc_gain_cal_single_sample = { | ||
| 60 | ADC_GAIN_CAL, | ||
| 61 | MIN_CAL_SAMPLES, | ||
| 62 | PER_MAX_LOG_COUNT, | ||
| 63 | ath9k_hw_adc_gaincal_collect, | ||
| 64 | ath9k_hw_adc_gaincal_calibrate | ||
| 65 | }; | ||
| 66 | static const struct hal_percal_data adc_dc_cal_multi_sample = { | ||
| 67 | ADC_DC_CAL, | ||
| 68 | MAX_CAL_SAMPLES, | ||
| 69 | PER_MIN_LOG_COUNT, | ||
| 70 | ath9k_hw_adc_dccal_collect, | ||
| 71 | ath9k_hw_adc_dccal_calibrate | ||
| 72 | }; | ||
| 73 | static const struct hal_percal_data adc_dc_cal_single_sample = { | ||
| 74 | ADC_DC_CAL, | ||
| 75 | MIN_CAL_SAMPLES, | ||
| 76 | PER_MAX_LOG_COUNT, | ||
| 77 | ath9k_hw_adc_dccal_collect, | ||
| 78 | ath9k_hw_adc_dccal_calibrate | ||
| 79 | }; | ||
| 80 | static const struct hal_percal_data adc_init_dc_cal = { | ||
| 81 | ADC_DC_INIT_CAL, | ||
| 82 | MIN_CAL_SAMPLES, | ||
| 83 | INIT_LOG_COUNT, | ||
| 84 | ath9k_hw_adc_dccal_collect, | ||
| 85 | ath9k_hw_adc_dccal_calibrate | ||
| 86 | }; | ||
| 87 | |||
| 88 | static const struct ath_hal ar5416hal = { | ||
| 89 | AR5416_MAGIC, | ||
| 90 | 0, | ||
| 91 | 0, | ||
| 92 | NULL, | ||
| 93 | NULL, | ||
| 94 | CTRY_DEFAULT, | ||
| 95 | 0, | ||
| 96 | 0, | ||
| 97 | 0, | ||
| 98 | 0, | ||
| 99 | 0, | ||
| 100 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 101 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 102 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 103 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 104 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 105 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 106 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 107 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 108 | }, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct ath9k_rate_table ar5416_11a_table = { | ||
| 112 | 8, | ||
| 113 | {0}, | ||
| 114 | { | ||
| 115 | {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0}, | ||
| 116 | {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0}, | ||
| 117 | {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2}, | ||
| 118 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2}, | ||
| 119 | {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4}, | ||
| 120 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4}, | ||
| 121 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4}, | ||
| 122 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4} | ||
| 123 | }, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct ath9k_rate_table ar5416_11b_table = { | ||
| 127 | 4, | ||
| 128 | {0}, | ||
| 129 | { | ||
| 130 | {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, | ||
| 131 | {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, | ||
| 132 | {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1}, | ||
| 133 | {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1} | ||
| 134 | }, | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct ath9k_rate_table ar5416_11g_table = { | ||
| 138 | 12, | ||
| 139 | {0}, | ||
| 140 | { | ||
| 141 | {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, | ||
| 142 | {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, | ||
| 143 | {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2}, | ||
| 144 | {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3}, | ||
| 145 | |||
| 146 | {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4}, | ||
| 147 | {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4}, | ||
| 148 | {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6}, | ||
| 149 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6}, | ||
| 150 | {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8}, | ||
| 151 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8}, | ||
| 152 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8}, | ||
| 153 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8} | ||
| 154 | }, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct ath9k_rate_table ar5416_11ng_table = { | ||
| 158 | 28, | ||
| 159 | {0}, | ||
| 160 | { | ||
| 161 | {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, | ||
| 162 | {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, | ||
| 163 | {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2}, | ||
| 164 | {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3}, | ||
| 165 | |||
| 166 | {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4}, | ||
| 167 | {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4}, | ||
| 168 | {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6}, | ||
| 169 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6}, | ||
| 170 | {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8}, | ||
| 171 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8}, | ||
| 172 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8}, | ||
| 173 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}, | ||
| 174 | {true, PHY_HT, 6500, 0x80, 0x00, 0, 4}, | ||
| 175 | {true, PHY_HT, 13000, 0x81, 0x00, 1, 6}, | ||
| 176 | {true, PHY_HT, 19500, 0x82, 0x00, 2, 6}, | ||
| 177 | {true, PHY_HT, 26000, 0x83, 0x00, 3, 8}, | ||
| 178 | {true, PHY_HT, 39000, 0x84, 0x00, 4, 8}, | ||
| 179 | {true, PHY_HT, 52000, 0x85, 0x00, 5, 8}, | ||
| 180 | {true, PHY_HT, 58500, 0x86, 0x00, 6, 8}, | ||
| 181 | {true, PHY_HT, 65000, 0x87, 0x00, 7, 8}, | ||
| 182 | {true, PHY_HT, 13000, 0x88, 0x00, 8, 4}, | ||
| 183 | {true, PHY_HT, 26000, 0x89, 0x00, 9, 6}, | ||
| 184 | {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6}, | ||
| 185 | {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8}, | ||
| 186 | {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8}, | ||
| 187 | {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8}, | ||
| 188 | {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8}, | ||
| 189 | {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8}, | ||
| 190 | }, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct ath9k_rate_table ar5416_11na_table = { | ||
| 194 | 24, | ||
| 195 | {0}, | ||
| 196 | { | ||
| 197 | {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0}, | ||
| 198 | {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0}, | ||
| 199 | {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2}, | ||
| 200 | {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2}, | ||
| 201 | {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4}, | ||
| 202 | {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4}, | ||
| 203 | {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4}, | ||
| 204 | {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}, | ||
| 205 | {true, PHY_HT, 6500, 0x80, 0x00, 0, 0}, | ||
| 206 | {true, PHY_HT, 13000, 0x81, 0x00, 1, 2}, | ||
| 207 | {true, PHY_HT, 19500, 0x82, 0x00, 2, 2}, | ||
| 208 | {true, PHY_HT, 26000, 0x83, 0x00, 3, 4}, | ||
| 209 | {true, PHY_HT, 39000, 0x84, 0x00, 4, 4}, | ||
| 210 | {true, PHY_HT, 52000, 0x85, 0x00, 5, 4}, | ||
| 211 | {true, PHY_HT, 58500, 0x86, 0x00, 6, 4}, | ||
| 212 | {true, PHY_HT, 65000, 0x87, 0x00, 7, 4}, | ||
| 213 | {true, PHY_HT, 13000, 0x88, 0x00, 8, 0}, | ||
| 214 | {true, PHY_HT, 26000, 0x89, 0x00, 9, 2}, | ||
| 215 | {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2}, | ||
| 216 | {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4}, | ||
| 217 | {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4}, | ||
| 218 | {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4}, | ||
| 219 | {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4}, | ||
| 220 | {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4}, | ||
| 221 | }, | ||
| 222 | }; | ||
| 223 | |||
| 224 | static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, | ||
| 225 | const struct ath9k_channel *chan) | ||
| 226 | { | ||
| 227 | if (IS_CHAN_CCK(chan)) | ||
| 228 | return ATH9K_MODE_11A; | ||
| 229 | if (IS_CHAN_G(chan)) | ||
| 230 | return ATH9K_MODE_11G; | ||
| 231 | return ATH9K_MODE_11A; | ||
| 232 | } | ||
| 233 | |||
| 234 | static bool ath9k_hw_wait(struct ath_hal *ah, | ||
| 235 | u32 reg, | ||
| 236 | u32 mask, | ||
| 237 | u32 val) | ||
| 238 | { | ||
| 239 | int i; | ||
| 240 | |||
| 241 | for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) { | ||
| 242 | if ((REG_READ(ah, reg) & mask) == val) | ||
| 243 | return true; | ||
| 244 | |||
| 245 | udelay(AH_TIME_QUANTUM); | ||
| 246 | } | ||
| 247 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | ||
| 248 | "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | ||
| 249 | __func__, reg, REG_READ(ah, reg), mask, val); | ||
| 250 | return false; | ||
| 251 | } | ||
| 252 | |||
| 253 | static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off, | ||
| 254 | u16 *data) | ||
| 255 | { | ||
| 256 | (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); | ||
| 257 | |||
| 258 | if (!ath9k_hw_wait(ah, | ||
| 259 | AR_EEPROM_STATUS_DATA, | ||
| 260 | AR_EEPROM_STATUS_DATA_BUSY | | ||
| 261 | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) { | ||
| 262 | return false; | ||
| 263 | } | ||
| 264 | |||
| 265 | *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), | ||
| 266 | AR_EEPROM_STATUS_DATA_VAL); | ||
| 267 | |||
| 268 | return true; | ||
| 269 | } | ||
| 270 | |||
| 271 | static int ath9k_hw_flash_map(struct ath_hal *ah) | ||
| 272 | { | ||
| 273 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 274 | |||
| 275 | ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX); | ||
| 276 | |||
| 277 | if (!ahp->ah_cal_mem) { | ||
| 278 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 279 | "%s: cannot remap eeprom region \n", __func__); | ||
| 280 | return -EIO; | ||
| 281 | } | ||
| 282 | |||
| 283 | return 0; | ||
| 284 | } | ||
| 285 | |||
| 286 | static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off, | ||
| 287 | u16 *data) | ||
| 288 | { | ||
| 289 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 290 | |||
| 291 | *data = ioread16(ahp->ah_cal_mem + off); | ||
| 292 | return true; | ||
| 293 | } | ||
| 294 | |||
| 295 | static void ath9k_hw_read_revisions(struct ath_hal *ah) | ||
| 296 | { | ||
| 297 | u32 val; | ||
| 298 | |||
| 299 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; | ||
| 300 | |||
| 301 | if (val == 0xFF) { | ||
| 302 | val = REG_READ(ah, AR_SREV); | ||
| 303 | |||
| 304 | ah->ah_macVersion = | ||
| 305 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | ||
| 306 | |||
| 307 | ah->ah_macRev = MS(val, AR_SREV_REVISION2); | ||
| 308 | ah->ah_isPciExpress = | ||
| 309 | (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; | ||
| 310 | |||
| 311 | } else { | ||
| 312 | if (!AR_SREV_9100(ah)) | ||
| 313 | ah->ah_macVersion = MS(val, AR_SREV_VERSION); | ||
| 314 | |||
| 315 | ah->ah_macRev = val & AR_SREV_REVISION; | ||
| 316 | |||
| 317 | if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) | ||
| 318 | ah->ah_isPciExpress = true; | ||
| 319 | } | ||
| 320 | } | ||
| 321 | |||
| 322 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | ||
| 323 | { | ||
| 324 | u32 retval; | ||
| 325 | int i; | ||
| 326 | |||
| 327 | for (i = 0, retval = 0; i < n; i++) { | ||
| 328 | retval = (retval << 1) | (val & 1); | ||
| 329 | val >>= 1; | ||
| 330 | } | ||
| 331 | return retval; | ||
| 332 | } | ||
| 333 | |||
| 334 | static void ath9k_hw_set_defaults(struct ath_hal *ah) | ||
| 335 | { | ||
| 336 | int i; | ||
| 337 | |||
| 338 | ah->ah_config.dma_beacon_response_time = 2; | ||
| 339 | ah->ah_config.sw_beacon_response_time = 10; | ||
| 340 | ah->ah_config.additional_swba_backoff = 0; | ||
| 341 | ah->ah_config.ack_6mb = 0x0; | ||
| 342 | ah->ah_config.cwm_ignore_extcca = 0; | ||
| 343 | ah->ah_config.pcie_powersave_enable = 0; | ||
| 344 | ah->ah_config.pcie_l1skp_enable = 0; | ||
| 345 | ah->ah_config.pcie_clock_req = 0; | ||
| 346 | ah->ah_config.pcie_power_reset = 0x100; | ||
| 347 | ah->ah_config.pcie_restore = 0; | ||
| 348 | ah->ah_config.pcie_waen = 0; | ||
| 349 | ah->ah_config.analog_shiftreg = 1; | ||
| 350 | ah->ah_config.ht_enable = 1; | ||
| 351 | ah->ah_config.ofdm_trig_low = 200; | ||
| 352 | ah->ah_config.ofdm_trig_high = 500; | ||
| 353 | ah->ah_config.cck_trig_high = 200; | ||
| 354 | ah->ah_config.cck_trig_low = 100; | ||
| 355 | ah->ah_config.enable_ani = 0; | ||
| 356 | ah->ah_config.noise_immunity_level = 4; | ||
| 357 | ah->ah_config.ofdm_weaksignal_det = 1; | ||
| 358 | ah->ah_config.cck_weaksignal_thr = 0; | ||
| 359 | ah->ah_config.spur_immunity_level = 2; | ||
| 360 | ah->ah_config.firstep_level = 0; | ||
| 361 | ah->ah_config.rssi_thr_high = 40; | ||
| 362 | ah->ah_config.rssi_thr_low = 7; | ||
| 363 | ah->ah_config.diversity_control = 0; | ||
| 364 | ah->ah_config.antenna_switch_swap = 0; | ||
| 365 | |||
| 366 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { | ||
| 367 | ah->ah_config.spurchans[i][0] = AR_NO_SPUR; | ||
| 368 | ah->ah_config.spurchans[i][1] = AR_NO_SPUR; | ||
| 369 | } | ||
| 370 | |||
| 371 | ah->ah_config.intr_mitigation = 0; | ||
| 372 | } | ||
| 373 | |||
| 374 | static inline void ath9k_hw_override_ini(struct ath_hal *ah, | ||
| 375 | struct ath9k_channel *chan) | ||
| 376 | { | ||
| 377 | if (!AR_SREV_5416_V20_OR_LATER(ah) | ||
| 378 | || AR_SREV_9280_10_OR_LATER(ah)) | ||
| 379 | return; | ||
| 380 | |||
| 381 | REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); | ||
| 382 | } | ||
| 383 | |||
| 384 | static inline void ath9k_hw_init_bb(struct ath_hal *ah, | ||
| 385 | struct ath9k_channel *chan) | ||
| 386 | { | ||
| 387 | u32 synthDelay; | ||
| 388 | |||
| 389 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | ||
| 390 | if (IS_CHAN_CCK(chan)) | ||
| 391 | synthDelay = (4 * synthDelay) / 22; | ||
| 392 | else | ||
| 393 | synthDelay /= 10; | ||
| 394 | |||
| 395 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); | ||
| 396 | |||
| 397 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | ||
| 398 | } | ||
| 399 | |||
| 400 | static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, | ||
| 401 | enum ath9k_opmode opmode) | ||
| 402 | { | ||
| 403 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 404 | |||
| 405 | ahp->ah_maskReg = AR_IMR_TXERR | | ||
| 406 | AR_IMR_TXURN | | ||
| 407 | AR_IMR_RXERR | | ||
| 408 | AR_IMR_RXORN | | ||
| 409 | AR_IMR_BCNMISC; | ||
| 410 | |||
| 411 | if (ahp->ah_intrMitigation) | ||
| 412 | ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | ||
| 413 | else | ||
| 414 | ahp->ah_maskReg |= AR_IMR_RXOK; | ||
| 415 | |||
| 416 | ahp->ah_maskReg |= AR_IMR_TXOK; | ||
| 417 | |||
| 418 | if (opmode == ATH9K_M_HOSTAP) | ||
| 419 | ahp->ah_maskReg |= AR_IMR_MIB; | ||
| 420 | |||
| 421 | REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); | ||
| 422 | REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); | ||
| 423 | |||
| 424 | if (!AR_SREV_9100(ah)) { | ||
| 425 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | ||
| 426 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | ||
| 427 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | ||
| 428 | } | ||
| 429 | } | ||
| 430 | |||
| 431 | static inline void ath9k_hw_init_qos(struct ath_hal *ah) | ||
| 432 | { | ||
| 433 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); | ||
| 434 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | ||
| 435 | |||
| 436 | REG_WRITE(ah, AR_QOS_NO_ACK, | ||
| 437 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | ||
| 438 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | ||
| 439 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | ||
| 440 | |||
| 441 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | ||
| 442 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | ||
| 443 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | ||
| 444 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | ||
| 445 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | ||
| 446 | } | ||
| 447 | |||
| 448 | static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, | ||
| 449 | u32 reg, | ||
| 450 | u32 mask, | ||
| 451 | u32 shift, | ||
| 452 | u32 val) | ||
| 453 | { | ||
| 454 | u32 regVal; | ||
| 455 | |||
| 456 | regVal = REG_READ(ah, reg) & ~mask; | ||
| 457 | regVal |= (val << shift) & mask; | ||
| 458 | |||
| 459 | REG_WRITE(ah, reg, regVal); | ||
| 460 | |||
| 461 | if (ah->ah_config.analog_shiftreg) | ||
| 462 | udelay(100); | ||
| 463 | |||
| 464 | return; | ||
| 465 | } | ||
| 466 | |||
| 467 | static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp, | ||
| 468 | enum ieee80211_band freq_band) | ||
| 469 | { | ||
| 470 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | ||
| 471 | struct modal_eep_header *pModal = | ||
| 472 | &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]); | ||
| 473 | struct base_eep_header *pBase = &eep->baseEepHeader; | ||
| 474 | u8 num_ant_config; | ||
| 475 | |||
| 476 | num_ant_config = 1; | ||
| 477 | |||
| 478 | if (pBase->version >= 0x0E0D) | ||
| 479 | if (pModal->useAnt1) | ||
| 480 | num_ant_config += 1; | ||
| 481 | |||
| 482 | return num_ant_config; | ||
| 483 | } | ||
| 484 | |||
| 485 | static int | ||
| 486 | ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp, | ||
| 487 | struct ath9k_channel *chan, | ||
| 488 | u8 index, | ||
| 489 | u16 *config) | ||
| 490 | { | ||
| 491 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | ||
| 492 | struct modal_eep_header *pModal = | ||
| 493 | &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | ||
| 494 | struct base_eep_header *pBase = &eep->baseEepHeader; | ||
| 495 | |||
| 496 | switch (index) { | ||
| 497 | case 0: | ||
| 498 | *config = pModal->antCtrlCommon & 0xFFFF; | ||
| 499 | return 0; | ||
| 500 | case 1: | ||
| 501 | if (pBase->version >= 0x0E0D) { | ||
| 502 | if (pModal->useAnt1) { | ||
| 503 | *config = | ||
| 504 | ((pModal->antCtrlCommon & 0xFFFF0000) >> 16); | ||
| 505 | return 0; | ||
| 506 | } | ||
| 507 | } | ||
| 508 | break; | ||
| 509 | default: | ||
| 510 | break; | ||
| 511 | } | ||
| 512 | |||
| 513 | return -EINVAL; | ||
| 514 | } | ||
| 515 | |||
| 516 | static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, | ||
| 517 | u32 off, | ||
| 518 | u16 *data) | ||
| 519 | { | ||
| 520 | if (ath9k_hw_use_flash(ah)) | ||
| 521 | return ath9k_hw_flash_read(ah, off, data); | ||
| 522 | else | ||
| 523 | return ath9k_hw_eeprom_read(ah, off, data); | ||
| 524 | } | ||
| 525 | |||
| 526 | static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah) | ||
| 527 | { | ||
| 528 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 529 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | ||
| 530 | u16 *eep_data; | ||
| 531 | int addr, ar5416_eep_start_loc = 0; | ||
| 532 | |||
| 533 | if (!ath9k_hw_use_flash(ah)) { | ||
| 534 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 535 | "%s: Reading from EEPROM, not flash\n", __func__); | ||
| 536 | ar5416_eep_start_loc = 256; | ||
| 537 | } | ||
| 538 | if (AR_SREV_9100(ah)) | ||
| 539 | ar5416_eep_start_loc = 256; | ||
| 540 | |||
| 541 | eep_data = (u16 *) eep; | ||
| 542 | for (addr = 0; | ||
| 543 | addr < sizeof(struct ar5416_eeprom) / sizeof(u16); | ||
| 544 | addr++) { | ||
| 545 | if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, | ||
| 546 | eep_data)) { | ||
| 547 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 548 | "%s: Unable to read eeprom region \n", | ||
| 549 | __func__); | ||
| 550 | return false; | ||
| 551 | } | ||
| 552 | eep_data++; | ||
| 553 | } | ||
| 554 | return true; | ||
| 555 | } | ||
| 556 | |||
| 557 | /* XXX: Clean me up, make me more legible */ | ||
| 558 | static bool | ||
| 559 | ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, | ||
| 560 | struct ath9k_channel *chan) | ||
| 561 | { | ||
| 562 | struct modal_eep_header *pModal; | ||
| 563 | int i, regChainOffset; | ||
| 564 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 565 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | ||
| 566 | u8 txRxAttenLocal; | ||
| 567 | u16 ant_config; | ||
| 568 | |||
| 569 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | ||
| 570 | |||
| 571 | txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; | ||
| 572 | |||
| 573 | ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config); | ||
| 574 | REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); | ||
| 575 | |||
| 576 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 577 | if (AR_SREV_9280(ah)) { | ||
| 578 | if (i >= 2) | ||
| 579 | break; | ||
| 580 | } | ||
| 581 | |||
| 582 | if (AR_SREV_5416_V20_OR_LATER(ah) && | ||
| 583 | (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) | ||
| 584 | && (i != 0)) | ||
| 585 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | ||
| 586 | else | ||
| 587 | regChainOffset = i * 0x1000; | ||
| 588 | |||
| 589 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, | ||
| 590 | pModal->antCtrlChain[i]); | ||
| 591 | |||
| 592 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, | ||
| 593 | (REG_READ(ah, | ||
| 594 | AR_PHY_TIMING_CTRL4(0) + | ||
| 595 | regChainOffset) & | ||
| 596 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | | ||
| 597 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | ||
| 598 | SM(pModal->iqCalICh[i], | ||
| 599 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | ||
| 600 | SM(pModal->iqCalQCh[i], | ||
| 601 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | ||
| 602 | |||
| 603 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { | ||
| 604 | if ((eep->baseEepHeader.version & | ||
| 605 | AR5416_EEP_VER_MINOR_MASK) >= | ||
| 606 | AR5416_EEP_MINOR_VER_3) { | ||
| 607 | txRxAttenLocal = pModal->txRxAttenCh[i]; | ||
| 608 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 609 | REG_RMW_FIELD(ah, | ||
| 610 | AR_PHY_GAIN_2GHZ + | ||
| 611 | regChainOffset, | ||
| 612 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | ||
| 613 | pModal-> | ||
| 614 | bswMargin[i]); | ||
| 615 | REG_RMW_FIELD(ah, | ||
| 616 | AR_PHY_GAIN_2GHZ + | ||
| 617 | regChainOffset, | ||
| 618 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, | ||
| 619 | pModal-> | ||
| 620 | bswAtten[i]); | ||
| 621 | REG_RMW_FIELD(ah, | ||
| 622 | AR_PHY_GAIN_2GHZ + | ||
| 623 | regChainOffset, | ||
| 624 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | ||
| 625 | pModal-> | ||
| 626 | xatten2Margin[i]); | ||
| 627 | REG_RMW_FIELD(ah, | ||
| 628 | AR_PHY_GAIN_2GHZ + | ||
| 629 | regChainOffset, | ||
| 630 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, | ||
| 631 | pModal-> | ||
| 632 | xatten2Db[i]); | ||
| 633 | } else { | ||
| 634 | REG_WRITE(ah, | ||
| 635 | AR_PHY_GAIN_2GHZ + | ||
| 636 | regChainOffset, | ||
| 637 | (REG_READ(ah, | ||
| 638 | AR_PHY_GAIN_2GHZ + | ||
| 639 | regChainOffset) & | ||
| 640 | ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | ||
| 641 | | SM(pModal-> | ||
| 642 | bswMargin[i], | ||
| 643 | AR_PHY_GAIN_2GHZ_BSW_MARGIN)); | ||
| 644 | REG_WRITE(ah, | ||
| 645 | AR_PHY_GAIN_2GHZ + | ||
| 646 | regChainOffset, | ||
| 647 | (REG_READ(ah, | ||
| 648 | AR_PHY_GAIN_2GHZ + | ||
| 649 | regChainOffset) & | ||
| 650 | ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | ||
| 651 | | SM(pModal->bswAtten[i], | ||
| 652 | AR_PHY_GAIN_2GHZ_BSW_ATTEN)); | ||
| 653 | } | ||
| 654 | } | ||
| 655 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 656 | REG_RMW_FIELD(ah, | ||
| 657 | AR_PHY_RXGAIN + | ||
| 658 | regChainOffset, | ||
| 659 | AR9280_PHY_RXGAIN_TXRX_ATTEN, | ||
| 660 | txRxAttenLocal); | ||
| 661 | REG_RMW_FIELD(ah, | ||
| 662 | AR_PHY_RXGAIN + | ||
| 663 | regChainOffset, | ||
| 664 | AR9280_PHY_RXGAIN_TXRX_MARGIN, | ||
| 665 | pModal->rxTxMarginCh[i]); | ||
| 666 | } else { | ||
| 667 | REG_WRITE(ah, | ||
| 668 | AR_PHY_RXGAIN + regChainOffset, | ||
| 669 | (REG_READ(ah, | ||
| 670 | AR_PHY_RXGAIN + | ||
| 671 | regChainOffset) & | ||
| 672 | ~AR_PHY_RXGAIN_TXRX_ATTEN) | | ||
| 673 | SM(txRxAttenLocal, | ||
| 674 | AR_PHY_RXGAIN_TXRX_ATTEN)); | ||
| 675 | REG_WRITE(ah, | ||
| 676 | AR_PHY_GAIN_2GHZ + | ||
| 677 | regChainOffset, | ||
| 678 | (REG_READ(ah, | ||
| 679 | AR_PHY_GAIN_2GHZ + | ||
| 680 | regChainOffset) & | ||
| 681 | ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | | ||
| 682 | SM(pModal->rxTxMarginCh[i], | ||
| 683 | AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); | ||
| 684 | } | ||
| 685 | } | ||
| 686 | } | ||
| 687 | |||
| 688 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 689 | if (IS_CHAN_2GHZ(chan)) { | ||
| 690 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | ||
| 691 | AR_AN_RF2G1_CH0_OB, | ||
| 692 | AR_AN_RF2G1_CH0_OB_S, | ||
| 693 | pModal->ob); | ||
| 694 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | ||
| 695 | AR_AN_RF2G1_CH0_DB, | ||
| 696 | AR_AN_RF2G1_CH0_DB_S, | ||
| 697 | pModal->db); | ||
| 698 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | ||
| 699 | AR_AN_RF2G1_CH1_OB, | ||
| 700 | AR_AN_RF2G1_CH1_OB_S, | ||
| 701 | pModal->ob_ch1); | ||
| 702 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | ||
| 703 | AR_AN_RF2G1_CH1_DB, | ||
| 704 | AR_AN_RF2G1_CH1_DB_S, | ||
| 705 | pModal->db_ch1); | ||
| 706 | } else { | ||
| 707 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | ||
| 708 | AR_AN_RF5G1_CH0_OB5, | ||
| 709 | AR_AN_RF5G1_CH0_OB5_S, | ||
| 710 | pModal->ob); | ||
| 711 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | ||
| 712 | AR_AN_RF5G1_CH0_DB5, | ||
| 713 | AR_AN_RF5G1_CH0_DB5_S, | ||
| 714 | pModal->db); | ||
| 715 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | ||
| 716 | AR_AN_RF5G1_CH1_OB5, | ||
| 717 | AR_AN_RF5G1_CH1_OB5_S, | ||
| 718 | pModal->ob_ch1); | ||
| 719 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | ||
| 720 | AR_AN_RF5G1_CH1_DB5, | ||
| 721 | AR_AN_RF5G1_CH1_DB5_S, | ||
| 722 | pModal->db_ch1); | ||
| 723 | } | ||
| 724 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | ||
| 725 | AR_AN_TOP2_XPABIAS_LVL, | ||
| 726 | AR_AN_TOP2_XPABIAS_LVL_S, | ||
| 727 | pModal->xpaBiasLvl); | ||
| 728 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | ||
| 729 | AR_AN_TOP2_LOCALBIAS, | ||
| 730 | AR_AN_TOP2_LOCALBIAS_S, | ||
| 731 | pModal->local_bias); | ||
| 732 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n", | ||
| 733 | pModal->force_xpaon); | ||
| 734 | REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, | ||
| 735 | pModal->force_xpaon); | ||
| 736 | } | ||
| 737 | |||
| 738 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, | ||
| 739 | pModal->switchSettling); | ||
| 740 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | ||
| 741 | pModal->adcDesiredSize); | ||
| 742 | |||
| 743 | if (!AR_SREV_9280_10_OR_LATER(ah)) | ||
| 744 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | ||
| 745 | AR_PHY_DESIRED_SZ_PGA, | ||
| 746 | pModal->pgaDesiredSize); | ||
| 747 | |||
| 748 | REG_WRITE(ah, AR_PHY_RF_CTL4, | ||
| 749 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | ||
| 750 | | SM(pModal->txEndToXpaOff, | ||
| 751 | AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | ||
| 752 | | SM(pModal->txFrameToXpaOn, | ||
| 753 | AR_PHY_RF_CTL4_FRAME_XPAA_ON) | ||
| 754 | | SM(pModal->txFrameToXpaOn, | ||
| 755 | AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | ||
| 756 | |||
| 757 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | ||
| 758 | pModal->txEndToRxOn); | ||
| 759 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 760 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, | ||
| 761 | pModal->thresh62); | ||
| 762 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, | ||
| 763 | AR_PHY_EXT_CCA0_THRESH62, | ||
| 764 | pModal->thresh62); | ||
| 765 | } else { | ||
| 766 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, | ||
| 767 | pModal->thresh62); | ||
| 768 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | ||
| 769 | AR_PHY_EXT_CCA_THRESH62, | ||
| 770 | pModal->thresh62); | ||
| 771 | } | ||
| 772 | |||
| 773 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | ||
| 774 | AR5416_EEP_MINOR_VER_2) { | ||
| 775 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, | ||
| 776 | AR_PHY_TX_END_DATA_START, | ||
| 777 | pModal->txFrameToDataStart); | ||
| 778 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | ||
| 779 | pModal->txFrameToPaOn); | ||
| 780 | } | ||
| 781 | |||
| 782 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | ||
| 783 | AR5416_EEP_MINOR_VER_3) { | ||
| 784 | if (IS_CHAN_HT40(chan)) | ||
| 785 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | ||
| 786 | AR_PHY_SETTLING_SWITCH, | ||
| 787 | pModal->swSettleHt40); | ||
| 788 | } | ||
| 789 | |||
| 790 | return true; | ||
| 791 | } | ||
| 792 | |||
| 793 | static inline int ath9k_hw_check_eeprom(struct ath_hal *ah) | ||
| 794 | { | ||
| 795 | u32 sum = 0, el; | ||
| 796 | u16 *eepdata; | ||
| 797 | int i; | ||
| 798 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 799 | bool need_swap = false; | ||
| 800 | struct ar5416_eeprom *eep = | ||
| 801 | (struct ar5416_eeprom *) &ahp->ah_eeprom; | ||
| 802 | |||
| 803 | if (!ath9k_hw_use_flash(ah)) { | ||
| 804 | u16 magic, magic2; | ||
| 805 | int addr; | ||
| 806 | |||
| 807 | if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, | ||
| 808 | &magic)) { | ||
| 809 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 810 | "%s: Reading Magic # failed\n", __func__); | ||
| 811 | return false; | ||
| 812 | } | ||
| 813 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n", | ||
| 814 | __func__, magic); | ||
| 815 | |||
| 816 | if (magic != AR5416_EEPROM_MAGIC) { | ||
| 817 | magic2 = swab16(magic); | ||
| 818 | |||
| 819 | if (magic2 == AR5416_EEPROM_MAGIC) { | ||
| 820 | need_swap = true; | ||
| 821 | eepdata = (u16 *) (&ahp->ah_eeprom); | ||
| 822 | |||
| 823 | for (addr = 0; | ||
| 824 | addr < | ||
| 825 | sizeof(struct ar5416_eeprom) / | ||
| 826 | sizeof(u16); addr++) { | ||
| 827 | u16 temp; | ||
| 828 | |||
| 829 | temp = swab16(*eepdata); | ||
| 830 | *eepdata = temp; | ||
| 831 | eepdata++; | ||
| 832 | |||
| 833 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 834 | "0x%04X ", *eepdata); | ||
| 835 | if (((addr + 1) % 6) == 0) | ||
| 836 | DPRINTF(ah->ah_sc, | ||
| 837 | ATH_DBG_EEPROM, | ||
| 838 | "\n"); | ||
| 839 | } | ||
| 840 | } else { | ||
| 841 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 842 | "Invalid EEPROM Magic. " | ||
| 843 | "endianness missmatch.\n"); | ||
| 844 | return -EINVAL; | ||
| 845 | } | ||
| 846 | } | ||
| 847 | } | ||
| 848 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", | ||
| 849 | need_swap ? "True" : "False"); | ||
| 850 | |||
| 851 | if (need_swap) | ||
| 852 | el = swab16(ahp->ah_eeprom.baseEepHeader.length); | ||
| 853 | else | ||
| 854 | el = ahp->ah_eeprom.baseEepHeader.length; | ||
| 855 | |||
| 856 | if (el > sizeof(struct ar5416_eeprom)) | ||
| 857 | el = sizeof(struct ar5416_eeprom) / sizeof(u16); | ||
| 858 | else | ||
| 859 | el = el / sizeof(u16); | ||
| 860 | |||
| 861 | eepdata = (u16 *) (&ahp->ah_eeprom); | ||
| 862 | |||
| 863 | for (i = 0; i < el; i++) | ||
| 864 | sum ^= *eepdata++; | ||
| 865 | |||
| 866 | if (need_swap) { | ||
| 867 | u32 integer, j; | ||
| 868 | u16 word; | ||
| 869 | |||
| 870 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 871 | "EEPROM Endianness is not native.. Changing \n"); | ||
| 872 | |||
| 873 | word = swab16(eep->baseEepHeader.length); | ||
| 874 | eep->baseEepHeader.length = word; | ||
| 875 | |||
| 876 | word = swab16(eep->baseEepHeader.checksum); | ||
| 877 | eep->baseEepHeader.checksum = word; | ||
| 878 | |||
| 879 | word = swab16(eep->baseEepHeader.version); | ||
| 880 | eep->baseEepHeader.version = word; | ||
| 881 | |||
| 882 | word = swab16(eep->baseEepHeader.regDmn[0]); | ||
| 883 | eep->baseEepHeader.regDmn[0] = word; | ||
| 884 | |||
| 885 | word = swab16(eep->baseEepHeader.regDmn[1]); | ||
| 886 | eep->baseEepHeader.regDmn[1] = word; | ||
| 887 | |||
| 888 | word = swab16(eep->baseEepHeader.rfSilent); | ||
| 889 | eep->baseEepHeader.rfSilent = word; | ||
| 890 | |||
| 891 | word = swab16(eep->baseEepHeader.blueToothOptions); | ||
| 892 | eep->baseEepHeader.blueToothOptions = word; | ||
| 893 | |||
| 894 | word = swab16(eep->baseEepHeader.deviceCap); | ||
| 895 | eep->baseEepHeader.deviceCap = word; | ||
| 896 | |||
| 897 | for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { | ||
| 898 | struct modal_eep_header *pModal = | ||
| 899 | &eep->modalHeader[j]; | ||
| 900 | integer = swab32(pModal->antCtrlCommon); | ||
| 901 | pModal->antCtrlCommon = integer; | ||
| 902 | |||
| 903 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 904 | integer = swab32(pModal->antCtrlChain[i]); | ||
| 905 | pModal->antCtrlChain[i] = integer; | ||
| 906 | } | ||
| 907 | |||
| 908 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | ||
| 909 | word = swab16(pModal->spurChans[i].spurChan); | ||
| 910 | pModal->spurChans[i].spurChan = word; | ||
| 911 | } | ||
| 912 | } | ||
| 913 | } | ||
| 914 | |||
| 915 | if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || | ||
| 916 | ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { | ||
| 917 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 918 | "Bad EEPROM checksum 0x%x or revision 0x%04x\n", | ||
| 919 | sum, ar5416_get_eep_ver(ahp)); | ||
| 920 | return -EINVAL; | ||
| 921 | } | ||
| 922 | |||
| 923 | return 0; | ||
| 924 | } | ||
| 925 | |||
| 926 | static bool ath9k_hw_chip_test(struct ath_hal *ah) | ||
| 927 | { | ||
| 928 | u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; | ||
| 929 | u32 regHold[2]; | ||
| 930 | u32 patternData[4] = { 0x55555555, | ||
| 931 | 0xaaaaaaaa, | ||
| 932 | 0x66666666, | ||
| 933 | 0x99999999 }; | ||
| 934 | int i, j; | ||
| 935 | |||
| 936 | for (i = 0; i < 2; i++) { | ||
| 937 | u32 addr = regAddr[i]; | ||
| 938 | u32 wrData, rdData; | ||
| 939 | |||
| 940 | regHold[i] = REG_READ(ah, addr); | ||
| 941 | for (j = 0; j < 0x100; j++) { | ||
| 942 | wrData = (j << 16) | j; | ||
| 943 | REG_WRITE(ah, addr, wrData); | ||
| 944 | rdData = REG_READ(ah, addr); | ||
| 945 | if (rdData != wrData) { | ||
| 946 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 947 | "%s: address test failed " | ||
| 948 | "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | ||
| 949 | __func__, addr, wrData, rdData); | ||
| 950 | return false; | ||
| 951 | } | ||
| 952 | } | ||
| 953 | for (j = 0; j < 4; j++) { | ||
| 954 | wrData = patternData[j]; | ||
| 955 | REG_WRITE(ah, addr, wrData); | ||
| 956 | rdData = REG_READ(ah, addr); | ||
| 957 | if (wrData != rdData) { | ||
| 958 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 959 | "%s: address test failed " | ||
| 960 | "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | ||
| 961 | __func__, addr, wrData, rdData); | ||
| 962 | return false; | ||
| 963 | } | ||
| 964 | } | ||
| 965 | REG_WRITE(ah, regAddr[i], regHold[i]); | ||
| 966 | } | ||
| 967 | udelay(100); | ||
| 968 | return true; | ||
| 969 | } | ||
| 970 | |||
| 971 | u32 ath9k_hw_getrxfilter(struct ath_hal *ah) | ||
| 972 | { | ||
| 973 | u32 bits = REG_READ(ah, AR_RX_FILTER); | ||
| 974 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | ||
| 975 | |||
| 976 | if (phybits & AR_PHY_ERR_RADAR) | ||
| 977 | bits |= ATH9K_RX_FILTER_PHYRADAR; | ||
| 978 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | ||
| 979 | bits |= ATH9K_RX_FILTER_PHYERR; | ||
| 980 | return bits; | ||
| 981 | } | ||
| 982 | |||
| 983 | void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) | ||
| 984 | { | ||
| 985 | u32 phybits; | ||
| 986 | |||
| 987 | REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR); | ||
| 988 | phybits = 0; | ||
| 989 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | ||
| 990 | phybits |= AR_PHY_ERR_RADAR; | ||
| 991 | if (bits & ATH9K_RX_FILTER_PHYERR) | ||
| 992 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | ||
| 993 | REG_WRITE(ah, AR_PHY_ERR, phybits); | ||
| 994 | |||
| 995 | if (phybits) | ||
| 996 | REG_WRITE(ah, AR_RXCFG, | ||
| 997 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | ||
| 998 | else | ||
| 999 | REG_WRITE(ah, AR_RXCFG, | ||
| 1000 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | ||
| 1001 | } | ||
| 1002 | |||
| 1003 | bool ath9k_hw_setcapability(struct ath_hal *ah, | ||
| 1004 | enum ath9k_capability_type type, | ||
| 1005 | u32 capability, | ||
| 1006 | u32 setting, | ||
| 1007 | int *status) | ||
| 1008 | { | ||
| 1009 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 1010 | u32 v; | ||
| 1011 | |||
| 1012 | switch (type) { | ||
| 1013 | case ATH9K_CAP_TKIP_MIC: | ||
| 1014 | if (setting) | ||
| 1015 | ahp->ah_staId1Defaults |= | ||
| 1016 | AR_STA_ID1_CRPT_MIC_ENABLE; | ||
| 1017 | else | ||
| 1018 | ahp->ah_staId1Defaults &= | ||
| 1019 | ~AR_STA_ID1_CRPT_MIC_ENABLE; | ||
| 1020 | return true; | ||
| 1021 | case ATH9K_CAP_DIVERSITY: | ||
| 1022 | v = REG_READ(ah, AR_PHY_CCK_DETECT); | ||
| 1023 | if (setting) | ||
| 1024 | v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | ||
| 1025 | else | ||
| 1026 | v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | ||
| 1027 | REG_WRITE(ah, AR_PHY_CCK_DETECT, v); | ||
| 1028 | return true; | ||
| 1029 | case ATH9K_CAP_MCAST_KEYSRCH: | ||
| 1030 | if (setting) | ||
| 1031 | ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; | ||
| 1032 | else | ||
| 1033 | ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; | ||
| 1034 | return true; | ||
| 1035 | case ATH9K_CAP_TSF_ADJUST: | ||
| 1036 | if (setting) | ||
| 1037 | ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; | ||
| 1038 | else | ||
| 1039 | ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; | ||
| 1040 | return true; | ||
| 1041 | default: | ||
| 1042 | return false; | ||
| 1043 | } | ||
| 1044 | } | ||
| 1045 | |||
| 1046 | void ath9k_hw_dmaRegDump(struct ath_hal *ah) | ||
| 1047 | { | ||
| 1048 | u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; | ||
| 1049 | int qcuOffset = 0, dcuOffset = 0; | ||
| 1050 | u32 *qcuBase = &val[0], *dcuBase = &val[4]; | ||
| 1051 | int i; | ||
| 1052 | |||
| 1053 | REG_WRITE(ah, AR_MACMISC, | ||
| 1054 | ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | | ||
| 1055 | (AR_MACMISC_MISC_OBS_BUS_1 << | ||
| 1056 | AR_MACMISC_MISC_OBS_BUS_MSB_S))); | ||
| 1057 | |||
| 1058 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n"); | ||
| 1059 | for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) { | ||
| 1060 | if (i % 4 == 0) | ||
| 1061 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n"); | ||
| 1062 | |||
| 1063 | val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))); | ||
| 1064 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]); | ||
| 1065 | } | ||
| 1066 | |||
| 1067 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n"); | ||
| 1068 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1069 | "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); | ||
| 1070 | |||
| 1071 | for (i = 0; i < ATH9K_NUM_QUEUES; | ||
| 1072 | i++, qcuOffset += 4, dcuOffset += 5) { | ||
| 1073 | if (i == 8) { | ||
| 1074 | qcuOffset = 0; | ||
| 1075 | qcuBase++; | ||
| 1076 | } | ||
| 1077 | |||
| 1078 | if (i == 6) { | ||
| 1079 | dcuOffset = 0; | ||
| 1080 | dcuBase++; | ||
| 1081 | } | ||
| 1082 | |||
| 1083 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1084 | "%2d %2x %1x %2x %2x\n", | ||
| 1085 | i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset, | ||
| 1086 | (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + | ||
| 1087 | 3), | ||
| 1088 | val[2] & (0x7 << (i * 3)) >> (i * 3), | ||
| 1089 | (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset); | ||
| 1090 | } | ||
| 1091 | |||
| 1092 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n"); | ||
| 1093 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1094 | "qcu_stitch state: %2x qcu_fetch state: %2x\n", | ||
| 1095 | (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); | ||
| 1096 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1097 | "qcu_complete state: %2x dcu_complete state: %2x\n", | ||
| 1098 | (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); | ||
| 1099 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1100 | "dcu_arb state: %2x dcu_fp state: %2x\n", | ||
| 1101 | (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); | ||
| 1102 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1103 | "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", | ||
| 1104 | (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); | ||
| 1105 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1106 | "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", | ||
| 1107 | (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); | ||
| 1108 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1109 | "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", | ||
| 1110 | (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); | ||
| 1111 | |||
| 1112 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n", | ||
| 1113 | REG_READ(ah, AR_OBS_BUS_1)); | ||
| 1114 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 1115 | "AR_CR 0x%x \n", REG_READ(ah, AR_CR)); | ||
| 1116 | } | ||
| 1117 | |||
| 1118 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, | ||
| 1119 | u32 *rxc_pcnt, | ||
| 1120 | u32 *rxf_pcnt, | ||
| 1121 | u32 *txf_pcnt) | ||
| 1122 | { | ||
| 1123 | static u32 cycles, rx_clear, rx_frame, tx_frame; | ||
| 1124 | u32 good = 1; | ||
| 1125 | |||
| 1126 | u32 rc = REG_READ(ah, AR_RCCNT); | ||
| 1127 | u32 rf = REG_READ(ah, AR_RFCNT); | ||
| 1128 | u32 tf = REG_READ(ah, AR_TFCNT); | ||
| 1129 | u32 cc = REG_READ(ah, AR_CCCNT); | ||
| 1130 | |||
| 1131 | if (cycles == 0 || cycles > cc) { | ||
| 1132 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 1133 | "%s: cycle counter wrap. ExtBusy = 0\n", | ||
| 1134 | __func__); | ||
| 1135 | good = 0; | ||
| 1136 | } else { | ||
| 1137 | u32 cc_d = cc - cycles; | ||
| 1138 | u32 rc_d = rc - rx_clear; | ||
| 1139 | u32 rf_d = rf - rx_frame; | ||
| 1140 | u32 tf_d = tf - tx_frame; | ||
| 1141 | |||
| 1142 | if (cc_d != 0) { | ||
| 1143 | *rxc_pcnt = rc_d * 100 / cc_d; | ||
| 1144 | *rxf_pcnt = rf_d * 100 / cc_d; | ||
| 1145 | *txf_pcnt = tf_d * 100 / cc_d; | ||
| 1146 | } else { | ||
| 1147 | good = 0; | ||
| 1148 | } | ||
| 1149 | } | ||
| 1150 | |||
| 1151 | cycles = cc; | ||
| 1152 | rx_frame = rf; | ||
| 1153 | rx_clear = rc; | ||
| 1154 | tx_frame = tf; | ||
| 1155 | |||
| 1156 | return good; | ||
| 1157 | } | ||
| 1158 | |||
| 1159 | void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) | ||
| 1160 | { | ||
| 1161 | u32 macmode; | ||
| 1162 | |||
| 1163 | if (mode == ATH9K_HT_MACMODE_2040 && | ||
| 1164 | !ah->ah_config.cwm_ignore_extcca) | ||
| 1165 | macmode = AR_2040_JOINED_RX_CLEAR; | ||
| 1166 | else | ||
| 1167 | macmode = 0; | ||
| 1168 | |||
| 1169 | REG_WRITE(ah, AR_2040_MODE, macmode); | ||
| 1170 | } | ||
| 1171 | |||
| 1172 | static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) | ||
| 1173 | { | ||
| 1174 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | ||
| 1175 | } | ||
| 1176 | |||
| 1177 | |||
| 1178 | static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, | ||
| 1179 | struct ath_softc *sc, | ||
| 1180 | void __iomem *mem, | ||
| 1181 | int *status) | ||
| 1182 | { | ||
| 1183 | static const u8 defbssidmask[ETH_ALEN] = | ||
| 1184 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | ||
| 1185 | struct ath_hal_5416 *ahp; | ||
| 1186 | struct ath_hal *ah; | ||
| 1187 | |||
| 1188 | ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); | ||
| 1189 | if (ahp == NULL) { | ||
| 1190 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1191 | "%s: cannot allocate memory for state block\n", | ||
| 1192 | __func__); | ||
| 1193 | *status = -ENOMEM; | ||
| 1194 | return NULL; | ||
| 1195 | } | ||
| 1196 | |||
| 1197 | ah = &ahp->ah; | ||
| 1198 | |||
| 1199 | memcpy(&ahp->ah, &ar5416hal, sizeof(struct ath_hal)); | ||
| 1200 | |||
| 1201 | ah->ah_sc = sc; | ||
| 1202 | ah->ah_sh = mem; | ||
| 1203 | |||
| 1204 | ah->ah_devid = devid; | ||
| 1205 | ah->ah_subvendorid = 0; | ||
| 1206 | |||
| 1207 | ah->ah_flags = 0; | ||
| 1208 | if ((devid == AR5416_AR9100_DEVID)) | ||
| 1209 | ah->ah_macVersion = AR_SREV_VERSION_9100; | ||
| 1210 | if (!AR_SREV_9100(ah)) | ||
| 1211 | ah->ah_flags = AH_USE_EEPROM; | ||
| 1212 | |||
| 1213 | ah->ah_powerLimit = MAX_RATE_POWER; | ||
| 1214 | ah->ah_tpScale = ATH9K_TP_SCALE_MAX; | ||
| 1215 | |||
| 1216 | ahp->ah_atimWindow = 0; | ||
| 1217 | ahp->ah_diversityControl = ah->ah_config.diversity_control; | ||
| 1218 | ahp->ah_antennaSwitchSwap = | ||
| 1219 | ah->ah_config.antenna_switch_swap; | ||
| 1220 | |||
| 1221 | ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; | ||
| 1222 | ahp->ah_beaconInterval = 100; | ||
| 1223 | ahp->ah_enable32kHzClock = DONT_USE_32KHZ; | ||
| 1224 | ahp->ah_slottime = (u32) -1; | ||
| 1225 | ahp->ah_acktimeout = (u32) -1; | ||
| 1226 | ahp->ah_ctstimeout = (u32) -1; | ||
| 1227 | ahp->ah_globaltxtimeout = (u32) -1; | ||
| 1228 | memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN); | ||
| 1229 | |||
| 1230 | ahp->ah_gBeaconRate = 0; | ||
| 1231 | |||
| 1232 | return ahp; | ||
| 1233 | } | ||
| 1234 | |||
| 1235 | static int ath9k_hw_eeprom_attach(struct ath_hal *ah) | ||
| 1236 | { | ||
| 1237 | int status; | ||
| 1238 | |||
| 1239 | if (ath9k_hw_use_flash(ah)) | ||
| 1240 | ath9k_hw_flash_map(ah); | ||
| 1241 | |||
| 1242 | if (!ath9k_hw_fill_eeprom(ah)) | ||
| 1243 | return -EIO; | ||
| 1244 | |||
| 1245 | status = ath9k_hw_check_eeprom(ah); | ||
| 1246 | |||
| 1247 | return status; | ||
| 1248 | } | ||
| 1249 | |||
| 1250 | u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp, | ||
| 1251 | enum eeprom_param param) | ||
| 1252 | { | ||
| 1253 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | ||
| 1254 | struct modal_eep_header *pModal = eep->modalHeader; | ||
| 1255 | struct base_eep_header *pBase = &eep->baseEepHeader; | ||
| 1256 | |||
| 1257 | switch (param) { | ||
| 1258 | case EEP_NFTHRESH_5: | ||
| 1259 | return -pModal[0].noiseFloorThreshCh[0]; | ||
| 1260 | case EEP_NFTHRESH_2: | ||
| 1261 | return -pModal[1].noiseFloorThreshCh[0]; | ||
| 1262 | case AR_EEPROM_MAC(0): | ||
| 1263 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; | ||
| 1264 | case AR_EEPROM_MAC(1): | ||
| 1265 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; | ||
| 1266 | case AR_EEPROM_MAC(2): | ||
| 1267 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; | ||
| 1268 | case EEP_REG_0: | ||
| 1269 | return pBase->regDmn[0]; | ||
| 1270 | case EEP_REG_1: | ||
| 1271 | return pBase->regDmn[1]; | ||
| 1272 | case EEP_OP_CAP: | ||
| 1273 | return pBase->deviceCap; | ||
| 1274 | case EEP_OP_MODE: | ||
| 1275 | return pBase->opCapFlags; | ||
| 1276 | case EEP_RF_SILENT: | ||
| 1277 | return pBase->rfSilent; | ||
| 1278 | case EEP_OB_5: | ||
| 1279 | return pModal[0].ob; | ||
| 1280 | case EEP_DB_5: | ||
| 1281 | return pModal[0].db; | ||
| 1282 | case EEP_OB_2: | ||
| 1283 | return pModal[1].ob; | ||
| 1284 | case EEP_DB_2: | ||
| 1285 | return pModal[1].db; | ||
| 1286 | case EEP_MINOR_REV: | ||
| 1287 | return pBase->version & AR5416_EEP_VER_MINOR_MASK; | ||
| 1288 | case EEP_TX_MASK: | ||
| 1289 | return pBase->txMask; | ||
| 1290 | case EEP_RX_MASK: | ||
| 1291 | return pBase->rxMask; | ||
| 1292 | default: | ||
| 1293 | return 0; | ||
| 1294 | } | ||
| 1295 | } | ||
| 1296 | |||
| 1297 | static inline int ath9k_hw_get_radiorev(struct ath_hal *ah) | ||
| 1298 | { | ||
| 1299 | u32 val; | ||
| 1300 | int i; | ||
| 1301 | |||
| 1302 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); | ||
| 1303 | for (i = 0; i < 8; i++) | ||
| 1304 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); | ||
| 1305 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; | ||
| 1306 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); | ||
| 1307 | return ath9k_hw_reverse_bits(val, 8); | ||
| 1308 | } | ||
| 1309 | |||
| 1310 | static inline int ath9k_hw_init_macaddr(struct ath_hal *ah) | ||
| 1311 | { | ||
| 1312 | u32 sum; | ||
| 1313 | int i; | ||
| 1314 | u16 eeval; | ||
| 1315 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 1316 | DECLARE_MAC_BUF(mac); | ||
| 1317 | |||
| 1318 | sum = 0; | ||
| 1319 | for (i = 0; i < 3; i++) { | ||
| 1320 | eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i)); | ||
| 1321 | sum += eeval; | ||
| 1322 | ahp->ah_macaddr[2 * i] = eeval >> 8; | ||
| 1323 | ahp->ah_macaddr[2 * i + 1] = eeval & 0xff; | ||
| 1324 | } | ||
| 1325 | if (sum == 0 || sum == 0xffff * 3) { | ||
| 1326 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 1327 | "%s: mac address read failed: %s\n", __func__, | ||
| 1328 | print_mac(mac, ahp->ah_macaddr)); | ||
| 1329 | return -EADDRNOTAVAIL; | ||
| 1330 | } | ||
| 1331 | |||
| 1332 | return 0; | ||
| 1333 | } | ||
| 1334 | |||
| 1335 | static inline int16_t ath9k_hw_interpolate(u16 target, | ||
| 1336 | u16 srcLeft, | ||
| 1337 | u16 srcRight, | ||
| 1338 | int16_t targetLeft, | ||
| 1339 | int16_t targetRight) | ||
| 1340 | { | ||
| 1341 | int16_t rv; | ||
| 1342 | |||
| 1343 | if (srcRight == srcLeft) { | ||
| 1344 | rv = targetLeft; | ||
| 1345 | } else { | ||
| 1346 | rv = (int16_t) (((target - srcLeft) * targetRight + | ||
| 1347 | (srcRight - target) * targetLeft) / | ||
| 1348 | (srcRight - srcLeft)); | ||
| 1349 | } | ||
| 1350 | return rv; | ||
| 1351 | } | ||
| 1352 | |||
| 1353 | static inline u16 ath9k_hw_fbin2freq(u8 fbin, | ||
| 1354 | bool is2GHz) | ||
| 1355 | { | ||
| 1356 | |||
| 1357 | if (fbin == AR5416_BCHAN_UNUSED) | ||
| 1358 | return fbin; | ||
| 1359 | |||
| 1360 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); | ||
| 1361 | } | ||
| 1362 | |||
| 1363 | static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, | ||
| 1364 | u16 i, | ||
| 1365 | bool is2GHz) | ||
| 1366 | { | ||
| 1367 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 1368 | struct ar5416_eeprom *eep = | ||
| 1369 | (struct ar5416_eeprom *) &ahp->ah_eeprom; | ||
| 1370 | u16 spur_val = AR_NO_SPUR; | ||
| 1371 | |||
| 1372 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 1373 | "Getting spur idx %d is2Ghz. %d val %x\n", | ||
| 1374 | i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); | ||
| 1375 | |||
| 1376 | switch (ah->ah_config.spurmode) { | ||
| 1377 | case SPUR_DISABLE: | ||
| 1378 | break; | ||
| 1379 | case SPUR_ENABLE_IOCTL: | ||
| 1380 | spur_val = ah->ah_config.spurchans[i][is2GHz]; | ||
| 1381 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 1382 | "Getting spur val from new loc. %d\n", spur_val); | ||
| 1383 | break; | ||
| 1384 | case SPUR_ENABLE_EEPROM: | ||
| 1385 | spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan; | ||
| 1386 | break; | ||
| 1387 | |||
| 1388 | } | ||
| 1389 | return spur_val; | ||
| 1390 | } | ||
| 1391 | |||
| 1392 | static inline int ath9k_hw_rfattach(struct ath_hal *ah) | ||
| 1393 | { | ||
| 1394 | bool rfStatus = false; | ||
| 1395 | int ecode = 0; | ||
| 1396 | |||
| 1397 | rfStatus = ath9k_hw_init_rf(ah, &ecode); | ||
| 1398 | if (!rfStatus) { | ||
| 1399 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 1400 | "%s: RF setup failed, status %u\n", __func__, | ||
| 1401 | ecode); | ||
| 1402 | return ecode; | ||
| 1403 | } | ||
| 1404 | |||
| 1405 | return 0; | ||
| 1406 | } | ||
| 1407 | |||
| 1408 | static int ath9k_hw_rf_claim(struct ath_hal *ah) | ||
| 1409 | { | ||
| 1410 | u32 val; | ||
| 1411 | |||
| 1412 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | ||
| 1413 | |||
| 1414 | val = ath9k_hw_get_radiorev(ah); | ||
| 1415 | switch (val & AR_RADIO_SREV_MAJOR) { | ||
| 1416 | case 0: | ||
| 1417 | val = AR_RAD5133_SREV_MAJOR; | ||
| 1418 | break; | ||
| 1419 | case AR_RAD5133_SREV_MAJOR: | ||
| 1420 | case AR_RAD5122_SREV_MAJOR: | ||
| 1421 | case AR_RAD2133_SREV_MAJOR: | ||
| 1422 | case AR_RAD2122_SREV_MAJOR: | ||
| 1423 | break; | ||
| 1424 | default: | ||
| 1425 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 1426 | "%s: 5G Radio Chip Rev 0x%02X is not " | ||
| 1427 | "supported by this driver\n", | ||
| 1428 | __func__, ah->ah_analog5GhzRev); | ||
| 1429 | return -EOPNOTSUPP; | ||
| 1430 | } | ||
| 1431 | |||
| 1432 | ah->ah_analog5GhzRev = val; | ||
| 1433 | |||
| 1434 | return 0; | ||
| 1435 | } | ||
| 1436 | |||
| 1437 | static inline void ath9k_hw_init_pll(struct ath_hal *ah, | ||
| 1438 | struct ath9k_channel *chan) | ||
| 1439 | { | ||
| 1440 | u32 pll; | ||
| 1441 | |||
| 1442 | if (AR_SREV_9100(ah)) { | ||
| 1443 | if (chan && IS_CHAN_5GHZ(chan)) | ||
| 1444 | pll = 0x1450; | ||
| 1445 | else | ||
| 1446 | pll = 0x1458; | ||
| 1447 | } else { | ||
| 1448 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 1449 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | ||
| 1450 | |||
| 1451 | if (chan && IS_CHAN_HALF_RATE(chan)) | ||
| 1452 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | ||
| 1453 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | ||
| 1454 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | ||
| 1455 | |||
| 1456 | if (chan && IS_CHAN_5GHZ(chan)) { | ||
| 1457 | pll |= SM(0x28, AR_RTC_9160_PLL_DIV); | ||
| 1458 | |||
| 1459 | |||
| 1460 | if (AR_SREV_9280_20(ah)) { | ||
| 1461 | if (((chan->channel % 20) == 0) | ||
| 1462 | || ((chan->channel % 10) == 0)) | ||
| 1463 | pll = 0x2850; | ||
| 1464 | else | ||
| 1465 | pll = 0x142c; | ||
| 1466 | } | ||
| 1467 | } else { | ||
| 1468 | pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); | ||
| 1469 | } | ||
| 1470 | |||
| 1471 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | ||
| 1472 | |||
| 1473 | pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); | ||
| 1474 | |||
| 1475 | if (chan && IS_CHAN_HALF_RATE(chan)) | ||
| 1476 | pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); | ||
| 1477 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | ||
| 1478 | pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); | ||
| 1479 | |||
| 1480 | if (chan && IS_CHAN_5GHZ(chan)) | ||
| 1481 | pll |= SM(0x50, AR_RTC_9160_PLL_DIV); | ||
| 1482 | else | ||
| 1483 | pll |= SM(0x58, AR_RTC_9160_PLL_DIV); | ||
| 1484 | } else { | ||
| 1485 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; | ||
| 1486 | |||
| 1487 | if (chan && IS_CHAN_HALF_RATE(chan)) | ||
| 1488 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); | ||
| 1489 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | ||
| 1490 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); | ||
| 1491 | |||
| 1492 | if (chan && IS_CHAN_5GHZ(chan)) | ||
| 1493 | pll |= SM(0xa, AR_RTC_PLL_DIV); | ||
| 1494 | else | ||
| 1495 | pll |= SM(0xb, AR_RTC_PLL_DIV); | ||
| 1496 | } | ||
| 1497 | } | ||
| 1498 | REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll); | ||
| 1499 | |||
| 1500 | udelay(RTC_PLL_SETTLE_DELAY); | ||
| 1501 | |||
| 1502 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | ||
| 1503 | } | ||
| 1504 | |||
| 1505 | static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, | ||
| 1506 | enum ath9k_ht_macmode macmode) | ||
| 1507 | { | ||
| 1508 | u32 phymode; | ||
| 1509 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 1510 | |||
| 1511 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 | ||
| 1512 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH; | ||
| 1513 | |||
| 1514 | if (IS_CHAN_HT40(chan)) { | ||
| 1515 | phymode |= AR_PHY_FC_DYN2040_EN; | ||
| 1516 | |||
| 1517 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || | ||
| 1518 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | ||
| 1519 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; | ||
| 1520 | |||
| 1521 | if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) | ||
| 1522 | phymode |= AR_PHY_FC_DYN2040_EXT_CH; | ||
| 1523 | } | ||
| 1524 | REG_WRITE(ah, AR_PHY_TURBO, phymode); | ||
| 1525 | |||
| 1526 | ath9k_hw_set11nmac2040(ah, macmode); | ||
| 1527 | |||
| 1528 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); | ||
| 1529 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | ||
| 1530 | } | ||
| 1531 | |||
| 1532 | static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) | ||
| 1533 | { | ||
| 1534 | u32 val; | ||
| 1535 | |||
| 1536 | val = REG_READ(ah, AR_STA_ID1); | ||
| 1537 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | ||
| 1538 | switch (opmode) { | ||
| 1539 | case ATH9K_M_HOSTAP: | ||
| 1540 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP | ||
| 1541 | | AR_STA_ID1_KSRCH_MODE); | ||
| 1542 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | ||
| 1543 | break; | ||
| 1544 | case ATH9K_M_IBSS: | ||
| 1545 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC | ||
| 1546 | | AR_STA_ID1_KSRCH_MODE); | ||
| 1547 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | ||
| 1548 | break; | ||
| 1549 | case ATH9K_M_STA: | ||
| 1550 | case ATH9K_M_MONITOR: | ||
| 1551 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); | ||
| 1552 | break; | ||
| 1553 | } | ||
| 1554 | } | ||
| 1555 | |||
| 1556 | static inline void | ||
| 1557 | ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) | ||
| 1558 | { | ||
| 1559 | u32 rfMode = 0; | ||
| 1560 | |||
| 1561 | if (chan == NULL) | ||
| 1562 | return; | ||
| 1563 | |||
| 1564 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) | ||
| 1565 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; | ||
| 1566 | |||
| 1567 | if (!AR_SREV_9280_10_OR_LATER(ah)) | ||
| 1568 | rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ : | ||
| 1569 | AR_PHY_MODE_RF2GHZ; | ||
| 1570 | |||
| 1571 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) | ||
| 1572 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); | ||
| 1573 | |||
| 1574 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | ||
| 1575 | } | ||
| 1576 | |||
| 1577 | static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) | ||
| 1578 | { | ||
| 1579 | u32 rst_flags; | ||
| 1580 | u32 tmpReg; | ||
| 1581 | |||
| 1582 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | ||
| 1583 | AR_RTC_FORCE_WAKE_ON_INT); | ||
| 1584 | |||
| 1585 | if (AR_SREV_9100(ah)) { | ||
| 1586 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | ||
| 1587 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | ||
| 1588 | } else { | ||
| 1589 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | ||
| 1590 | if (tmpReg & | ||
| 1591 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | ||
| 1592 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | ||
| 1593 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | ||
| 1594 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | ||
| 1595 | } else { | ||
| 1596 | REG_WRITE(ah, AR_RC, AR_RC_AHB); | ||
| 1597 | } | ||
| 1598 | |||
| 1599 | rst_flags = AR_RTC_RC_MAC_WARM; | ||
| 1600 | if (type == ATH9K_RESET_COLD) | ||
| 1601 | rst_flags |= AR_RTC_RC_MAC_COLD; | ||
| 1602 | } | ||
| 1603 | |||
| 1604 | REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags); | ||
| 1605 | udelay(50); | ||
| 1606 | |||
| 1607 | REG_WRITE(ah, (u16) (AR_RTC_RC), 0); | ||
| 1608 | if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) { | ||
| 1609 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 1610 | "%s: RTC stuck in MAC reset\n", | ||
| 1611 | __func__); | ||
| 1612 | return false; | ||
| 1613 | } | ||
| 1614 | |||
| 1615 | if (!AR_SREV_9100(ah)) | ||
| 1616 | REG_WRITE(ah, AR_RC, 0); | ||
| 1617 | |||
| 1618 | ath9k_hw_init_pll(ah, NULL); | ||
| 1619 | |||
| 1620 | if (AR_SREV_9100(ah)) | ||
| 1621 | udelay(50); | ||
| 1622 | |||
| 1623 | return true; | ||
| 1624 | } | ||
| 1625 | |||
| 1626 | static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) | ||
| 1627 | { | ||
| 1628 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | ||
| 1629 | AR_RTC_FORCE_WAKE_ON_INT); | ||
| 1630 | |||
| 1631 | REG_WRITE(ah, (u16) (AR_RTC_RESET), 0); | ||
| 1632 | REG_WRITE(ah, (u16) (AR_RTC_RESET), 1); | ||
| 1633 | |||
| 1634 | if (!ath9k_hw_wait(ah, | ||
| 1635 | AR_RTC_STATUS, | ||
| 1636 | AR_RTC_STATUS_M, | ||
| 1637 | AR_RTC_STATUS_ON)) { | ||
| 1638 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n", | ||
| 1639 | __func__); | ||
| 1640 | return false; | ||
| 1641 | } | ||
| 1642 | |||
| 1643 | ath9k_hw_read_revisions(ah); | ||
| 1644 | |||
| 1645 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | ||
| 1646 | } | ||
| 1647 | |||
| 1648 | static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, | ||
| 1649 | u32 type) | ||
| 1650 | { | ||
| 1651 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | ||
| 1652 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | ||
| 1653 | |||
| 1654 | switch (type) { | ||
| 1655 | case ATH9K_RESET_POWER_ON: | ||
| 1656 | return ath9k_hw_set_reset_power_on(ah); | ||
| 1657 | break; | ||
| 1658 | case ATH9K_RESET_WARM: | ||
| 1659 | case ATH9K_RESET_COLD: | ||
| 1660 | return ath9k_hw_set_reset(ah, type); | ||
| 1661 | break; | ||
| 1662 | default: | ||
| 1663 | return false; | ||
| 1664 | } | ||
| 1665 | } | ||
| 1666 | |||
| 1667 | static inline | ||
| 1668 | struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah, | ||
| 1669 | struct ath9k_channel *chan) | ||
| 1670 | { | ||
| 1671 | if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) { | ||
| 1672 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 1673 | "%s: invalid channel %u/0x%x; not marked as " | ||
| 1674 | "2GHz or 5GHz\n", __func__, chan->channel, | ||
| 1675 | chan->channelFlags); | ||
| 1676 | return NULL; | ||
| 1677 | } | ||
| 1678 | |||
| 1679 | if (!IS_CHAN_OFDM(chan) && | ||
| 1680 | !IS_CHAN_CCK(chan) && | ||
| 1681 | !IS_CHAN_HT20(chan) && | ||
| 1682 | !IS_CHAN_HT40(chan)) { | ||
| 1683 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 1684 | "%s: invalid channel %u/0x%x; not marked as " | ||
| 1685 | "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", | ||
| 1686 | __func__, chan->channel, chan->channelFlags); | ||
| 1687 | return NULL; | ||
| 1688 | } | ||
| 1689 | |||
| 1690 | return ath9k_regd_check_channel(ah, chan); | ||
| 1691 | } | ||
| 1692 | |||
| 1693 | static inline bool | ||
| 1694 | ath9k_hw_get_lower_upper_index(u8 target, | ||
| 1695 | u8 *pList, | ||
| 1696 | u16 listSize, | ||
| 1697 | u16 *indexL, | ||
| 1698 | u16 *indexR) | ||
| 1699 | { | ||
| 1700 | u16 i; | ||
| 1701 | |||
| 1702 | if (target <= pList[0]) { | ||
| 1703 | *indexL = *indexR = 0; | ||
| 1704 | return true; | ||
| 1705 | } | ||
| 1706 | if (target >= pList[listSize - 1]) { | ||
| 1707 | *indexL = *indexR = (u16) (listSize - 1); | ||
| 1708 | return true; | ||
| 1709 | } | ||
| 1710 | |||
| 1711 | for (i = 0; i < listSize - 1; i++) { | ||
| 1712 | if (pList[i] == target) { | ||
| 1713 | *indexL = *indexR = i; | ||
| 1714 | return true; | ||
| 1715 | } | ||
| 1716 | if (target < pList[i + 1]) { | ||
| 1717 | *indexL = i; | ||
| 1718 | *indexR = (u16) (i + 1); | ||
| 1719 | return false; | ||
| 1720 | } | ||
| 1721 | } | ||
| 1722 | return false; | ||
| 1723 | } | ||
| 1724 | |||
| 1725 | static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer) | ||
| 1726 | { | ||
| 1727 | int16_t nfval; | ||
| 1728 | int16_t sort[ATH9K_NF_CAL_HIST_MAX]; | ||
| 1729 | int i, j; | ||
| 1730 | |||
| 1731 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++) | ||
| 1732 | sort[i] = nfCalBuffer[i]; | ||
| 1733 | |||
| 1734 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) { | ||
| 1735 | for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) { | ||
| 1736 | if (sort[j] > sort[j - 1]) { | ||
| 1737 | nfval = sort[j]; | ||
| 1738 | sort[j] = sort[j - 1]; | ||
| 1739 | sort[j - 1] = nfval; | ||
| 1740 | } | ||
| 1741 | } | ||
| 1742 | } | ||
| 1743 | nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1]; | ||
| 1744 | |||
| 1745 | return nfval; | ||
| 1746 | } | ||
| 1747 | |||
| 1748 | static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, | ||
| 1749 | int16_t *nfarray) | ||
| 1750 | { | ||
| 1751 | int i; | ||
| 1752 | |||
| 1753 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
| 1754 | h[i].nfCalBuffer[h[i].currIndex] = nfarray[i]; | ||
| 1755 | |||
| 1756 | if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX) | ||
| 1757 | h[i].currIndex = 0; | ||
| 1758 | |||
| 1759 | if (h[i].invalidNFcount > 0) { | ||
| 1760 | if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE | ||
| 1761 | || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) { | ||
| 1762 | h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX; | ||
| 1763 | } else { | ||
| 1764 | h[i].invalidNFcount--; | ||
| 1765 | h[i].privNF = nfarray[i]; | ||
| 1766 | } | ||
| 1767 | } else { | ||
| 1768 | h[i].privNF = | ||
| 1769 | ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer); | ||
| 1770 | } | ||
| 1771 | } | ||
| 1772 | return; | ||
| 1773 | } | ||
| 1774 | |||
| 1775 | static void ar5416GetNoiseFloor(struct ath_hal *ah, | ||
| 1776 | int16_t nfarray[NUM_NF_READINGS]) | ||
| 1777 | { | ||
| 1778 | int16_t nf; | ||
| 1779 | |||
| 1780 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 1781 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); | ||
| 1782 | else | ||
| 1783 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); | ||
| 1784 | |||
| 1785 | if (nf & 0x100) | ||
| 1786 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
| 1787 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 1788 | "NF calibrated [ctl] [chain 0] is %d\n", nf); | ||
| 1789 | nfarray[0] = nf; | ||
| 1790 | |||
| 1791 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 1792 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), | ||
| 1793 | AR9280_PHY_CH1_MINCCA_PWR); | ||
| 1794 | else | ||
| 1795 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), | ||
| 1796 | AR_PHY_CH1_MINCCA_PWR); | ||
| 1797 | |||
| 1798 | if (nf & 0x100) | ||
| 1799 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
| 1800 | DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, | ||
| 1801 | "NF calibrated [ctl] [chain 1] is %d\n", nf); | ||
| 1802 | nfarray[1] = nf; | ||
| 1803 | |||
| 1804 | if (!AR_SREV_9280(ah)) { | ||
| 1805 | nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), | ||
| 1806 | AR_PHY_CH2_MINCCA_PWR); | ||
| 1807 | if (nf & 0x100) | ||
| 1808 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
| 1809 | DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, | ||
| 1810 | "NF calibrated [ctl] [chain 2] is %d\n", nf); | ||
| 1811 | nfarray[2] = nf; | ||
| 1812 | } | ||
| 1813 | |||
| 1814 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 1815 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), | ||
| 1816 | AR9280_PHY_EXT_MINCCA_PWR); | ||
| 1817 | else | ||
| 1818 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), | ||
| 1819 | AR_PHY_EXT_MINCCA_PWR); | ||
| 1820 | |||
| 1821 | if (nf & 0x100) | ||
| 1822 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
| 1823 | DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, | ||
| 1824 | "NF calibrated [ext] [chain 0] is %d\n", nf); | ||
| 1825 | nfarray[3] = nf; | ||
| 1826 | |||
| 1827 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 1828 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), | ||
| 1829 | AR9280_PHY_CH1_EXT_MINCCA_PWR); | ||
| 1830 | else | ||
| 1831 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), | ||
| 1832 | AR_PHY_CH1_EXT_MINCCA_PWR); | ||
| 1833 | |||
| 1834 | if (nf & 0x100) | ||
| 1835 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
| 1836 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 1837 | "NF calibrated [ext] [chain 1] is %d\n", nf); | ||
| 1838 | nfarray[4] = nf; | ||
| 1839 | |||
| 1840 | if (!AR_SREV_9280(ah)) { | ||
| 1841 | nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), | ||
| 1842 | AR_PHY_CH2_EXT_MINCCA_PWR); | ||
| 1843 | if (nf & 0x100) | ||
| 1844 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
| 1845 | DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, | ||
| 1846 | "NF calibrated [ext] [chain 2] is %d\n", nf); | ||
| 1847 | nfarray[5] = nf; | ||
| 1848 | } | ||
| 1849 | } | ||
| 1850 | |||
| 1851 | static bool | ||
| 1852 | getNoiseFloorThresh(struct ath_hal *ah, | ||
| 1853 | const struct ath9k_channel *chan, | ||
| 1854 | int16_t *nft) | ||
| 1855 | { | ||
| 1856 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 1857 | |||
| 1858 | switch (chan->chanmode) { | ||
| 1859 | case CHANNEL_A: | ||
| 1860 | case CHANNEL_A_HT20: | ||
| 1861 | case CHANNEL_A_HT40PLUS: | ||
| 1862 | case CHANNEL_A_HT40MINUS: | ||
| 1863 | *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5); | ||
| 1864 | break; | ||
| 1865 | case CHANNEL_B: | ||
| 1866 | case CHANNEL_G: | ||
| 1867 | case CHANNEL_G_HT20: | ||
| 1868 | case CHANNEL_G_HT40PLUS: | ||
| 1869 | case CHANNEL_G_HT40MINUS: | ||
| 1870 | *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2); | ||
| 1871 | break; | ||
| 1872 | default: | ||
| 1873 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 1874 | "%s: invalid channel flags 0x%x\n", __func__, | ||
| 1875 | chan->channelFlags); | ||
| 1876 | return false; | ||
| 1877 | } | ||
| 1878 | return true; | ||
| 1879 | } | ||
| 1880 | |||
| 1881 | static void ath9k_hw_start_nfcal(struct ath_hal *ah) | ||
| 1882 | { | ||
| 1883 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, | ||
| 1884 | AR_PHY_AGC_CONTROL_ENABLE_NF); | ||
| 1885 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, | ||
| 1886 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | ||
| 1887 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | ||
| 1888 | } | ||
| 1889 | |||
| 1890 | static void | ||
| 1891 | ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) | ||
| 1892 | { | ||
| 1893 | struct ath9k_nfcal_hist *h; | ||
| 1894 | int i, j; | ||
| 1895 | int32_t val; | ||
| 1896 | const u32 ar5416_cca_regs[6] = { | ||
| 1897 | AR_PHY_CCA, | ||
| 1898 | AR_PHY_CH1_CCA, | ||
| 1899 | AR_PHY_CH2_CCA, | ||
| 1900 | AR_PHY_EXT_CCA, | ||
| 1901 | AR_PHY_CH1_EXT_CCA, | ||
| 1902 | AR_PHY_CH2_EXT_CCA | ||
| 1903 | }; | ||
| 1904 | u8 chainmask; | ||
| 1905 | |||
| 1906 | if (AR_SREV_9280(ah)) | ||
| 1907 | chainmask = 0x1B; | ||
| 1908 | else | ||
| 1909 | chainmask = 0x3F; | ||
| 1910 | |||
| 1911 | #ifdef ATH_NF_PER_CHAN | ||
| 1912 | h = chan->nfCalHist; | ||
| 1913 | #else | ||
| 1914 | h = ah->nfCalHist; | ||
| 1915 | #endif | ||
| 1916 | |||
| 1917 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
| 1918 | if (chainmask & (1 << i)) { | ||
| 1919 | val = REG_READ(ah, ar5416_cca_regs[i]); | ||
| 1920 | val &= 0xFFFFFE00; | ||
| 1921 | val |= (((u32) (h[i].privNF) << 1) & 0x1ff); | ||
| 1922 | REG_WRITE(ah, ar5416_cca_regs[i], val); | ||
| 1923 | } | ||
| 1924 | } | ||
| 1925 | |||
| 1926 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | ||
| 1927 | AR_PHY_AGC_CONTROL_ENABLE_NF); | ||
| 1928 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | ||
| 1929 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | ||
| 1930 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | ||
| 1931 | |||
| 1932 | for (j = 0; j < 1000; j++) { | ||
| 1933 | if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & | ||
| 1934 | AR_PHY_AGC_CONTROL_NF) == 0) | ||
| 1935 | break; | ||
| 1936 | udelay(10); | ||
| 1937 | } | ||
| 1938 | |||
| 1939 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
| 1940 | if (chainmask & (1 << i)) { | ||
| 1941 | val = REG_READ(ah, ar5416_cca_regs[i]); | ||
| 1942 | val &= 0xFFFFFE00; | ||
| 1943 | val |= (((u32) (-50) << 1) & 0x1ff); | ||
| 1944 | REG_WRITE(ah, ar5416_cca_regs[i], val); | ||
| 1945 | } | ||
| 1946 | } | ||
| 1947 | } | ||
| 1948 | |||
| 1949 | static int16_t ath9k_hw_getnf(struct ath_hal *ah, | ||
| 1950 | struct ath9k_channel *chan) | ||
| 1951 | { | ||
| 1952 | int16_t nf, nfThresh; | ||
| 1953 | int16_t nfarray[NUM_NF_READINGS] = { 0 }; | ||
| 1954 | struct ath9k_nfcal_hist *h; | ||
| 1955 | u8 chainmask; | ||
| 1956 | |||
| 1957 | if (AR_SREV_9280(ah)) | ||
| 1958 | chainmask = 0x1B; | ||
| 1959 | else | ||
| 1960 | chainmask = 0x3F; | ||
| 1961 | |||
| 1962 | chan->channelFlags &= (~CHANNEL_CW_INT); | ||
| 1963 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { | ||
| 1964 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 1965 | "%s: NF did not complete in calibration window\n", | ||
| 1966 | __func__); | ||
| 1967 | nf = 0; | ||
| 1968 | chan->rawNoiseFloor = nf; | ||
| 1969 | return chan->rawNoiseFloor; | ||
| 1970 | } else { | ||
| 1971 | ar5416GetNoiseFloor(ah, nfarray); | ||
| 1972 | nf = nfarray[0]; | ||
| 1973 | if (getNoiseFloorThresh(ah, chan, &nfThresh) | ||
| 1974 | && nf > nfThresh) { | ||
| 1975 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 1976 | "%s: noise floor failed detected; " | ||
| 1977 | "detected %d, threshold %d\n", __func__, | ||
| 1978 | nf, nfThresh); | ||
| 1979 | chan->channelFlags |= CHANNEL_CW_INT; | ||
| 1980 | } | ||
| 1981 | } | ||
| 1982 | |||
| 1983 | #ifdef ATH_NF_PER_CHAN | ||
| 1984 | h = chan->nfCalHist; | ||
| 1985 | #else | ||
| 1986 | h = ah->nfCalHist; | ||
| 1987 | #endif | ||
| 1988 | |||
| 1989 | ath9k_hw_update_nfcal_hist_buffer(h, nfarray); | ||
| 1990 | chan->rawNoiseFloor = h[0].privNF; | ||
| 1991 | |||
| 1992 | return chan->rawNoiseFloor; | ||
| 1993 | } | ||
| 1994 | |||
| 1995 | static void ath9k_hw_update_mibstats(struct ath_hal *ah, | ||
| 1996 | struct ath9k_mib_stats *stats) | ||
| 1997 | { | ||
| 1998 | stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); | ||
| 1999 | stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); | ||
| 2000 | stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); | ||
| 2001 | stats->rts_good += REG_READ(ah, AR_RTS_OK); | ||
| 2002 | stats->beacons += REG_READ(ah, AR_BEACON_CNT); | ||
| 2003 | } | ||
| 2004 | |||
| 2005 | static void ath9k_enable_mib_counters(struct ath_hal *ah) | ||
| 2006 | { | ||
| 2007 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2008 | |||
| 2009 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n"); | ||
| 2010 | |||
| 2011 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | ||
| 2012 | |||
| 2013 | REG_WRITE(ah, AR_FILT_OFDM, 0); | ||
| 2014 | REG_WRITE(ah, AR_FILT_CCK, 0); | ||
| 2015 | REG_WRITE(ah, AR_MIBC, | ||
| 2016 | ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) | ||
| 2017 | & 0x0f); | ||
| 2018 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); | ||
| 2019 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | ||
| 2020 | } | ||
| 2021 | |||
| 2022 | static void ath9k_hw_disable_mib_counters(struct ath_hal *ah) | ||
| 2023 | { | ||
| 2024 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2025 | |||
| 2026 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n"); | ||
| 2027 | |||
| 2028 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); | ||
| 2029 | |||
| 2030 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | ||
| 2031 | |||
| 2032 | REG_WRITE(ah, AR_FILT_OFDM, 0); | ||
| 2033 | REG_WRITE(ah, AR_FILT_CCK, 0); | ||
| 2034 | } | ||
| 2035 | |||
| 2036 | static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, | ||
| 2037 | struct ath9k_channel *chan) | ||
| 2038 | { | ||
| 2039 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2040 | int i; | ||
| 2041 | |||
| 2042 | for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { | ||
| 2043 | if (ahp->ah_ani[i].c.channel == chan->channel) | ||
| 2044 | return i; | ||
| 2045 | if (ahp->ah_ani[i].c.channel == 0) { | ||
| 2046 | ahp->ah_ani[i].c.channel = chan->channel; | ||
| 2047 | ahp->ah_ani[i].c.channelFlags = chan->channelFlags; | ||
| 2048 | return i; | ||
| 2049 | } | ||
| 2050 | } | ||
| 2051 | |||
| 2052 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2053 | "No more channel states left. Using channel 0\n"); | ||
| 2054 | return 0; | ||
| 2055 | } | ||
| 2056 | |||
| 2057 | static void ath9k_hw_ani_attach(struct ath_hal *ah) | ||
| 2058 | { | ||
| 2059 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2060 | int i; | ||
| 2061 | |||
| 2062 | ahp->ah_hasHwPhyCounters = 1; | ||
| 2063 | |||
| 2064 | memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); | ||
| 2065 | for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { | ||
| 2066 | ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; | ||
| 2067 | ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; | ||
| 2068 | ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; | ||
| 2069 | ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; | ||
| 2070 | ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; | ||
| 2071 | ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; | ||
| 2072 | ahp->ah_ani[i].ofdmWeakSigDetectOff = | ||
| 2073 | !ATH9K_ANI_USE_OFDM_WEAK_SIG; | ||
| 2074 | ahp->ah_ani[i].cckWeakSigThreshold = | ||
| 2075 | ATH9K_ANI_CCK_WEAK_SIG_THR; | ||
| 2076 | ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; | ||
| 2077 | ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; | ||
| 2078 | if (ahp->ah_hasHwPhyCounters) { | ||
| 2079 | ahp->ah_ani[i].ofdmPhyErrBase = | ||
| 2080 | AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; | ||
| 2081 | ahp->ah_ani[i].cckPhyErrBase = | ||
| 2082 | AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; | ||
| 2083 | } | ||
| 2084 | } | ||
| 2085 | if (ahp->ah_hasHwPhyCounters) { | ||
| 2086 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2087 | "Setting OfdmErrBase = 0x%08x\n", | ||
| 2088 | ahp->ah_ani[0].ofdmPhyErrBase); | ||
| 2089 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", | ||
| 2090 | ahp->ah_ani[0].cckPhyErrBase); | ||
| 2091 | |||
| 2092 | REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); | ||
| 2093 | REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); | ||
| 2094 | ath9k_enable_mib_counters(ah); | ||
| 2095 | } | ||
| 2096 | ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; | ||
| 2097 | if (ah->ah_config.enable_ani) | ||
| 2098 | ahp->ah_procPhyErr |= HAL_PROCESS_ANI; | ||
| 2099 | } | ||
| 2100 | |||
| 2101 | static inline void ath9k_hw_ani_setup(struct ath_hal *ah) | ||
| 2102 | { | ||
| 2103 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2104 | int i; | ||
| 2105 | |||
| 2106 | const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; | ||
| 2107 | const int coarseHigh[] = { -14, -14, -14, -14, -12 }; | ||
| 2108 | const int coarseLow[] = { -64, -64, -64, -64, -70 }; | ||
| 2109 | const int firpwr[] = { -78, -78, -78, -78, -80 }; | ||
| 2110 | |||
| 2111 | for (i = 0; i < 5; i++) { | ||
| 2112 | ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; | ||
| 2113 | ahp->ah_coarseHigh[i] = coarseHigh[i]; | ||
| 2114 | ahp->ah_coarseLow[i] = coarseLow[i]; | ||
| 2115 | ahp->ah_firpwr[i] = firpwr[i]; | ||
| 2116 | } | ||
| 2117 | } | ||
| 2118 | |||
| 2119 | static void ath9k_hw_ani_detach(struct ath_hal *ah) | ||
| 2120 | { | ||
| 2121 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2122 | |||
| 2123 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n"); | ||
| 2124 | if (ahp->ah_hasHwPhyCounters) { | ||
| 2125 | ath9k_hw_disable_mib_counters(ah); | ||
| 2126 | REG_WRITE(ah, AR_PHY_ERR_1, 0); | ||
| 2127 | REG_WRITE(ah, AR_PHY_ERR_2, 0); | ||
| 2128 | } | ||
| 2129 | } | ||
| 2130 | |||
| 2131 | |||
| 2132 | static bool ath9k_hw_ani_control(struct ath_hal *ah, | ||
| 2133 | enum ath9k_ani_cmd cmd, int param) | ||
| 2134 | { | ||
| 2135 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2136 | struct ar5416AniState *aniState = ahp->ah_curani; | ||
| 2137 | |||
| 2138 | switch (cmd & ahp->ah_ani_function) { | ||
| 2139 | case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ | ||
| 2140 | u32 level = param; | ||
| 2141 | |||
| 2142 | if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { | ||
| 2143 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2144 | "%s: level out of range (%u > %u)\n", | ||
| 2145 | __func__, level, | ||
| 2146 | (unsigned) ARRAY_SIZE(ahp-> | ||
| 2147 | ah_totalSizeDesired)); | ||
| 2148 | return false; | ||
| 2149 | } | ||
| 2150 | |||
| 2151 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | ||
| 2152 | AR_PHY_DESIRED_SZ_TOT_DES, | ||
| 2153 | ahp->ah_totalSizeDesired[level]); | ||
| 2154 | REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, | ||
| 2155 | AR_PHY_AGC_CTL1_COARSE_LOW, | ||
| 2156 | ahp->ah_coarseLow[level]); | ||
| 2157 | REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, | ||
| 2158 | AR_PHY_AGC_CTL1_COARSE_HIGH, | ||
| 2159 | ahp->ah_coarseHigh[level]); | ||
| 2160 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | ||
| 2161 | AR_PHY_FIND_SIG_FIRPWR, | ||
| 2162 | ahp->ah_firpwr[level]); | ||
| 2163 | |||
| 2164 | if (level > aniState->noiseImmunityLevel) | ||
| 2165 | ahp->ah_stats.ast_ani_niup++; | ||
| 2166 | else if (level < aniState->noiseImmunityLevel) | ||
| 2167 | ahp->ah_stats.ast_ani_nidown++; | ||
| 2168 | aniState->noiseImmunityLevel = level; | ||
| 2169 | break; | ||
| 2170 | } | ||
| 2171 | case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ | ||
| 2172 | const int m1ThreshLow[] = { 127, 50 }; | ||
| 2173 | const int m2ThreshLow[] = { 127, 40 }; | ||
| 2174 | const int m1Thresh[] = { 127, 0x4d }; | ||
| 2175 | const int m2Thresh[] = { 127, 0x40 }; | ||
| 2176 | const int m2CountThr[] = { 31, 16 }; | ||
| 2177 | const int m2CountThrLow[] = { 63, 48 }; | ||
| 2178 | u32 on = param ? 1 : 0; | ||
| 2179 | |||
| 2180 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | ||
| 2181 | AR_PHY_SFCORR_LOW_M1_THRESH_LOW, | ||
| 2182 | m1ThreshLow[on]); | ||
| 2183 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | ||
| 2184 | AR_PHY_SFCORR_LOW_M2_THRESH_LOW, | ||
| 2185 | m2ThreshLow[on]); | ||
| 2186 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | ||
| 2187 | AR_PHY_SFCORR_M1_THRESH, | ||
| 2188 | m1Thresh[on]); | ||
| 2189 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | ||
| 2190 | AR_PHY_SFCORR_M2_THRESH, | ||
| 2191 | m2Thresh[on]); | ||
| 2192 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | ||
| 2193 | AR_PHY_SFCORR_M2COUNT_THR, | ||
| 2194 | m2CountThr[on]); | ||
| 2195 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | ||
| 2196 | AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, | ||
| 2197 | m2CountThrLow[on]); | ||
| 2198 | |||
| 2199 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
| 2200 | AR_PHY_SFCORR_EXT_M1_THRESH_LOW, | ||
| 2201 | m1ThreshLow[on]); | ||
| 2202 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
| 2203 | AR_PHY_SFCORR_EXT_M2_THRESH_LOW, | ||
| 2204 | m2ThreshLow[on]); | ||
| 2205 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
| 2206 | AR_PHY_SFCORR_EXT_M1_THRESH, | ||
| 2207 | m1Thresh[on]); | ||
| 2208 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
| 2209 | AR_PHY_SFCORR_EXT_M2_THRESH, | ||
| 2210 | m2Thresh[on]); | ||
| 2211 | |||
| 2212 | if (on) | ||
| 2213 | REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, | ||
| 2214 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | ||
| 2215 | else | ||
| 2216 | REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, | ||
| 2217 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | ||
| 2218 | |||
| 2219 | if (!on != aniState->ofdmWeakSigDetectOff) { | ||
| 2220 | if (on) | ||
| 2221 | ahp->ah_stats.ast_ani_ofdmon++; | ||
| 2222 | else | ||
| 2223 | ahp->ah_stats.ast_ani_ofdmoff++; | ||
| 2224 | aniState->ofdmWeakSigDetectOff = !on; | ||
| 2225 | } | ||
| 2226 | break; | ||
| 2227 | } | ||
| 2228 | case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{ | ||
| 2229 | const int weakSigThrCck[] = { 8, 6 }; | ||
| 2230 | u32 high = param ? 1 : 0; | ||
| 2231 | |||
| 2232 | REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, | ||
| 2233 | AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, | ||
| 2234 | weakSigThrCck[high]); | ||
| 2235 | if (high != aniState->cckWeakSigThreshold) { | ||
| 2236 | if (high) | ||
| 2237 | ahp->ah_stats.ast_ani_cckhigh++; | ||
| 2238 | else | ||
| 2239 | ahp->ah_stats.ast_ani_ccklow++; | ||
| 2240 | aniState->cckWeakSigThreshold = high; | ||
| 2241 | } | ||
| 2242 | break; | ||
| 2243 | } | ||
| 2244 | case ATH9K_ANI_FIRSTEP_LEVEL:{ | ||
| 2245 | const int firstep[] = { 0, 4, 8 }; | ||
| 2246 | u32 level = param; | ||
| 2247 | |||
| 2248 | if (level >= ARRAY_SIZE(firstep)) { | ||
| 2249 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2250 | "%s: level out of range (%u > %u)\n", | ||
| 2251 | __func__, level, | ||
| 2252 | (unsigned) ARRAY_SIZE(firstep)); | ||
| 2253 | return false; | ||
| 2254 | } | ||
| 2255 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | ||
| 2256 | AR_PHY_FIND_SIG_FIRSTEP, | ||
| 2257 | firstep[level]); | ||
| 2258 | if (level > aniState->firstepLevel) | ||
| 2259 | ahp->ah_stats.ast_ani_stepup++; | ||
| 2260 | else if (level < aniState->firstepLevel) | ||
| 2261 | ahp->ah_stats.ast_ani_stepdown++; | ||
| 2262 | aniState->firstepLevel = level; | ||
| 2263 | break; | ||
| 2264 | } | ||
| 2265 | case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ | ||
| 2266 | const int cycpwrThr1[] = | ||
| 2267 | { 2, 4, 6, 8, 10, 12, 14, 16 }; | ||
| 2268 | u32 level = param; | ||
| 2269 | |||
| 2270 | if (level >= ARRAY_SIZE(cycpwrThr1)) { | ||
| 2271 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2272 | "%s: level out of range (%u > %u)\n", | ||
| 2273 | __func__, level, | ||
| 2274 | (unsigned) | ||
| 2275 | ARRAY_SIZE(cycpwrThr1)); | ||
| 2276 | return false; | ||
| 2277 | } | ||
| 2278 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, | ||
| 2279 | AR_PHY_TIMING5_CYCPWR_THR1, | ||
| 2280 | cycpwrThr1[level]); | ||
| 2281 | if (level > aniState->spurImmunityLevel) | ||
| 2282 | ahp->ah_stats.ast_ani_spurup++; | ||
| 2283 | else if (level < aniState->spurImmunityLevel) | ||
| 2284 | ahp->ah_stats.ast_ani_spurdown++; | ||
| 2285 | aniState->spurImmunityLevel = level; | ||
| 2286 | break; | ||
| 2287 | } | ||
| 2288 | case ATH9K_ANI_PRESENT: | ||
| 2289 | break; | ||
| 2290 | default: | ||
| 2291 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2292 | "%s: invalid cmd %u\n", __func__, cmd); | ||
| 2293 | return false; | ||
| 2294 | } | ||
| 2295 | |||
| 2296 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__); | ||
| 2297 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2298 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, " | ||
| 2299 | "ofdmWeakSigDetectOff=%d\n", | ||
| 2300 | aniState->noiseImmunityLevel, aniState->spurImmunityLevel, | ||
| 2301 | !aniState->ofdmWeakSigDetectOff); | ||
| 2302 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2303 | "cckWeakSigThreshold=%d, " | ||
| 2304 | "firstepLevel=%d, listenTime=%d\n", | ||
| 2305 | aniState->cckWeakSigThreshold, aniState->firstepLevel, | ||
| 2306 | aniState->listenTime); | ||
| 2307 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2308 | "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", | ||
| 2309 | aniState->cycleCount, aniState->ofdmPhyErrCount, | ||
| 2310 | aniState->cckPhyErrCount); | ||
| 2311 | return true; | ||
| 2312 | } | ||
| 2313 | |||
| 2314 | static void ath9k_ani_restart(struct ath_hal *ah) | ||
| 2315 | { | ||
| 2316 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2317 | struct ar5416AniState *aniState; | ||
| 2318 | |||
| 2319 | if (!DO_ANI(ah)) | ||
| 2320 | return; | ||
| 2321 | |||
| 2322 | aniState = ahp->ah_curani; | ||
| 2323 | |||
| 2324 | aniState->listenTime = 0; | ||
| 2325 | if (ahp->ah_hasHwPhyCounters) { | ||
| 2326 | if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { | ||
| 2327 | aniState->ofdmPhyErrBase = 0; | ||
| 2328 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2329 | "OFDM Trigger is too high for hw counters\n"); | ||
| 2330 | } else { | ||
| 2331 | aniState->ofdmPhyErrBase = | ||
| 2332 | AR_PHY_COUNTMAX - aniState->ofdmTrigHigh; | ||
| 2333 | } | ||
| 2334 | if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { | ||
| 2335 | aniState->cckPhyErrBase = 0; | ||
| 2336 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2337 | "CCK Trigger is too high for hw counters\n"); | ||
| 2338 | } else { | ||
| 2339 | aniState->cckPhyErrBase = | ||
| 2340 | AR_PHY_COUNTMAX - aniState->cckTrigHigh; | ||
| 2341 | } | ||
| 2342 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2343 | "%s: Writing ofdmbase=%u cckbase=%u\n", | ||
| 2344 | __func__, aniState->ofdmPhyErrBase, | ||
| 2345 | aniState->cckPhyErrBase); | ||
| 2346 | REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); | ||
| 2347 | REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); | ||
| 2348 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); | ||
| 2349 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | ||
| 2350 | |||
| 2351 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | ||
| 2352 | } | ||
| 2353 | aniState->ofdmPhyErrCount = 0; | ||
| 2354 | aniState->cckPhyErrCount = 0; | ||
| 2355 | } | ||
| 2356 | |||
| 2357 | static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) | ||
| 2358 | { | ||
| 2359 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2360 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 2361 | struct ar5416AniState *aniState; | ||
| 2362 | enum wireless_mode mode; | ||
| 2363 | int32_t rssi; | ||
| 2364 | |||
| 2365 | if (!DO_ANI(ah)) | ||
| 2366 | return; | ||
| 2367 | |||
| 2368 | aniState = ahp->ah_curani; | ||
| 2369 | |||
| 2370 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { | ||
| 2371 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | ||
| 2372 | aniState->noiseImmunityLevel + 1)) { | ||
| 2373 | return; | ||
| 2374 | } | ||
| 2375 | } | ||
| 2376 | |||
| 2377 | if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) { | ||
| 2378 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | ||
| 2379 | aniState->spurImmunityLevel + 1)) { | ||
| 2380 | return; | ||
| 2381 | } | ||
| 2382 | } | ||
| 2383 | |||
| 2384 | if (ah->ah_opmode == ATH9K_M_HOSTAP) { | ||
| 2385 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { | ||
| 2386 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2387 | aniState->firstepLevel + 1); | ||
| 2388 | } | ||
| 2389 | return; | ||
| 2390 | } | ||
| 2391 | rssi = BEACON_RSSI(ahp); | ||
| 2392 | if (rssi > aniState->rssiThrHigh) { | ||
| 2393 | if (!aniState->ofdmWeakSigDetectOff) { | ||
| 2394 | if (ath9k_hw_ani_control(ah, | ||
| 2395 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | ||
| 2396 | false)) { | ||
| 2397 | ath9k_hw_ani_control(ah, | ||
| 2398 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | ||
| 2399 | 0); | ||
| 2400 | return; | ||
| 2401 | } | ||
| 2402 | } | ||
| 2403 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { | ||
| 2404 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2405 | aniState->firstepLevel + 1); | ||
| 2406 | return; | ||
| 2407 | } | ||
| 2408 | } else if (rssi > aniState->rssiThrLow) { | ||
| 2409 | if (aniState->ofdmWeakSigDetectOff) | ||
| 2410 | ath9k_hw_ani_control(ah, | ||
| 2411 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | ||
| 2412 | true); | ||
| 2413 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) | ||
| 2414 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2415 | aniState->firstepLevel + 1); | ||
| 2416 | return; | ||
| 2417 | } else { | ||
| 2418 | mode = ath9k_hw_chan2wmode(ah, chan); | ||
| 2419 | if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) { | ||
| 2420 | if (!aniState->ofdmWeakSigDetectOff) | ||
| 2421 | ath9k_hw_ani_control(ah, | ||
| 2422 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | ||
| 2423 | false); | ||
| 2424 | if (aniState->firstepLevel > 0) | ||
| 2425 | ath9k_hw_ani_control(ah, | ||
| 2426 | ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2427 | 0); | ||
| 2428 | return; | ||
| 2429 | } | ||
| 2430 | } | ||
| 2431 | } | ||
| 2432 | |||
| 2433 | static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) | ||
| 2434 | { | ||
| 2435 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2436 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 2437 | struct ar5416AniState *aniState; | ||
| 2438 | enum wireless_mode mode; | ||
| 2439 | int32_t rssi; | ||
| 2440 | |||
| 2441 | if (!DO_ANI(ah)) | ||
| 2442 | return; | ||
| 2443 | |||
| 2444 | aniState = ahp->ah_curani; | ||
| 2445 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { | ||
| 2446 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | ||
| 2447 | aniState->noiseImmunityLevel + 1)) { | ||
| 2448 | return; | ||
| 2449 | } | ||
| 2450 | } | ||
| 2451 | if (ah->ah_opmode == ATH9K_M_HOSTAP) { | ||
| 2452 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { | ||
| 2453 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2454 | aniState->firstepLevel + 1); | ||
| 2455 | } | ||
| 2456 | return; | ||
| 2457 | } | ||
| 2458 | rssi = BEACON_RSSI(ahp); | ||
| 2459 | if (rssi > aniState->rssiThrLow) { | ||
| 2460 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) | ||
| 2461 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2462 | aniState->firstepLevel + 1); | ||
| 2463 | } else { | ||
| 2464 | mode = ath9k_hw_chan2wmode(ah, chan); | ||
| 2465 | if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) { | ||
| 2466 | if (aniState->firstepLevel > 0) | ||
| 2467 | ath9k_hw_ani_control(ah, | ||
| 2468 | ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2469 | 0); | ||
| 2470 | } | ||
| 2471 | } | ||
| 2472 | } | ||
| 2473 | |||
| 2474 | static void ath9k_ani_reset(struct ath_hal *ah) | ||
| 2475 | { | ||
| 2476 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2477 | struct ar5416AniState *aniState; | ||
| 2478 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 2479 | int index; | ||
| 2480 | |||
| 2481 | if (!DO_ANI(ah)) | ||
| 2482 | return; | ||
| 2483 | |||
| 2484 | index = ath9k_hw_get_ani_channel_idx(ah, chan); | ||
| 2485 | aniState = &ahp->ah_ani[index]; | ||
| 2486 | ahp->ah_curani = aniState; | ||
| 2487 | |||
| 2488 | if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA | ||
| 2489 | && ah->ah_opmode != ATH9K_M_IBSS) { | ||
| 2490 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2491 | "%s: Reset ANI state opmode %u\n", __func__, | ||
| 2492 | ah->ah_opmode); | ||
| 2493 | ahp->ah_stats.ast_ani_reset++; | ||
| 2494 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); | ||
| 2495 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); | ||
| 2496 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0); | ||
| 2497 | ath9k_hw_ani_control(ah, | ||
| 2498 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | ||
| 2499 | !ATH9K_ANI_USE_OFDM_WEAK_SIG); | ||
| 2500 | ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, | ||
| 2501 | ATH9K_ANI_CCK_WEAK_SIG_THR); | ||
| 2502 | ath9k_hw_setrxfilter(ah, | ||
| 2503 | ath9k_hw_getrxfilter(ah) | | ||
| 2504 | ATH9K_RX_FILTER_PHYERR); | ||
| 2505 | if (ah->ah_opmode == ATH9K_M_HOSTAP) { | ||
| 2506 | ahp->ah_curani->ofdmTrigHigh = | ||
| 2507 | ah->ah_config.ofdm_trig_high; | ||
| 2508 | ahp->ah_curani->ofdmTrigLow = | ||
| 2509 | ah->ah_config.ofdm_trig_low; | ||
| 2510 | ahp->ah_curani->cckTrigHigh = | ||
| 2511 | ah->ah_config.cck_trig_high; | ||
| 2512 | ahp->ah_curani->cckTrigLow = | ||
| 2513 | ah->ah_config.cck_trig_low; | ||
| 2514 | } | ||
| 2515 | ath9k_ani_restart(ah); | ||
| 2516 | return; | ||
| 2517 | } | ||
| 2518 | |||
| 2519 | if (aniState->noiseImmunityLevel != 0) | ||
| 2520 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | ||
| 2521 | aniState->noiseImmunityLevel); | ||
| 2522 | if (aniState->spurImmunityLevel != 0) | ||
| 2523 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | ||
| 2524 | aniState->spurImmunityLevel); | ||
| 2525 | if (aniState->ofdmWeakSigDetectOff) | ||
| 2526 | ath9k_hw_ani_control(ah, | ||
| 2527 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | ||
| 2528 | !aniState->ofdmWeakSigDetectOff); | ||
| 2529 | if (aniState->cckWeakSigThreshold) | ||
| 2530 | ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, | ||
| 2531 | aniState->cckWeakSigThreshold); | ||
| 2532 | if (aniState->firstepLevel != 0) | ||
| 2533 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2534 | aniState->firstepLevel); | ||
| 2535 | if (ahp->ah_hasHwPhyCounters) { | ||
| 2536 | ath9k_hw_setrxfilter(ah, | ||
| 2537 | ath9k_hw_getrxfilter(ah) & | ||
| 2538 | ~ATH9K_RX_FILTER_PHYERR); | ||
| 2539 | ath9k_ani_restart(ah); | ||
| 2540 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); | ||
| 2541 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | ||
| 2542 | |||
| 2543 | } else { | ||
| 2544 | ath9k_ani_restart(ah); | ||
| 2545 | ath9k_hw_setrxfilter(ah, | ||
| 2546 | ath9k_hw_getrxfilter(ah) | | ||
| 2547 | ATH9K_RX_FILTER_PHYERR); | ||
| 2548 | } | ||
| 2549 | } | ||
| 2550 | |||
| 2551 | void ath9k_hw_procmibevent(struct ath_hal *ah, | ||
| 2552 | const struct ath9k_node_stats *stats) | ||
| 2553 | { | ||
| 2554 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2555 | u32 phyCnt1, phyCnt2; | ||
| 2556 | |||
| 2557 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n"); | ||
| 2558 | |||
| 2559 | REG_WRITE(ah, AR_FILT_OFDM, 0); | ||
| 2560 | REG_WRITE(ah, AR_FILT_CCK, 0); | ||
| 2561 | if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) | ||
| 2562 | REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); | ||
| 2563 | |||
| 2564 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | ||
| 2565 | ahp->ah_stats.ast_nodestats = *stats; | ||
| 2566 | |||
| 2567 | if (!DO_ANI(ah)) | ||
| 2568 | return; | ||
| 2569 | |||
| 2570 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); | ||
| 2571 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | ||
| 2572 | if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || | ||
| 2573 | ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { | ||
| 2574 | struct ar5416AniState *aniState = ahp->ah_curani; | ||
| 2575 | u32 ofdmPhyErrCnt, cckPhyErrCnt; | ||
| 2576 | |||
| 2577 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; | ||
| 2578 | ahp->ah_stats.ast_ani_ofdmerrs += | ||
| 2579 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; | ||
| 2580 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; | ||
| 2581 | |||
| 2582 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; | ||
| 2583 | ahp->ah_stats.ast_ani_cckerrs += | ||
| 2584 | cckPhyErrCnt - aniState->cckPhyErrCount; | ||
| 2585 | aniState->cckPhyErrCount = cckPhyErrCnt; | ||
| 2586 | |||
| 2587 | if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh) | ||
| 2588 | ath9k_hw_ani_ofdm_err_trigger(ah); | ||
| 2589 | if (aniState->cckPhyErrCount > aniState->cckTrigHigh) | ||
| 2590 | ath9k_hw_ani_cck_err_trigger(ah); | ||
| 2591 | |||
| 2592 | ath9k_ani_restart(ah); | ||
| 2593 | } | ||
| 2594 | } | ||
| 2595 | |||
| 2596 | static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) | ||
| 2597 | { | ||
| 2598 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2599 | struct ar5416AniState *aniState; | ||
| 2600 | int32_t rssi; | ||
| 2601 | |||
| 2602 | aniState = ahp->ah_curani; | ||
| 2603 | |||
| 2604 | if (ah->ah_opmode == ATH9K_M_HOSTAP) { | ||
| 2605 | if (aniState->firstepLevel > 0) { | ||
| 2606 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2607 | aniState->firstepLevel - 1)) { | ||
| 2608 | return; | ||
| 2609 | } | ||
| 2610 | } | ||
| 2611 | } else { | ||
| 2612 | rssi = BEACON_RSSI(ahp); | ||
| 2613 | if (rssi > aniState->rssiThrHigh) { | ||
| 2614 | /* XXX: Handle me */ | ||
| 2615 | } else if (rssi > aniState->rssiThrLow) { | ||
| 2616 | if (aniState->ofdmWeakSigDetectOff) { | ||
| 2617 | if (ath9k_hw_ani_control(ah, | ||
| 2618 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | ||
| 2619 | true) == | ||
| 2620 | true) { | ||
| 2621 | return; | ||
| 2622 | } | ||
| 2623 | } | ||
| 2624 | if (aniState->firstepLevel > 0) { | ||
| 2625 | if (ath9k_hw_ani_control | ||
| 2626 | (ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2627 | aniState->firstepLevel - 1) == | ||
| 2628 | true) { | ||
| 2629 | return; | ||
| 2630 | } | ||
| 2631 | } | ||
| 2632 | } else { | ||
| 2633 | if (aniState->firstepLevel > 0) { | ||
| 2634 | if (ath9k_hw_ani_control | ||
| 2635 | (ah, ATH9K_ANI_FIRSTEP_LEVEL, | ||
| 2636 | aniState->firstepLevel - 1) == | ||
| 2637 | true) { | ||
| 2638 | return; | ||
| 2639 | } | ||
| 2640 | } | ||
| 2641 | } | ||
| 2642 | } | ||
| 2643 | |||
| 2644 | if (aniState->spurImmunityLevel > 0) { | ||
| 2645 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | ||
| 2646 | aniState->spurImmunityLevel - 1)) { | ||
| 2647 | return; | ||
| 2648 | } | ||
| 2649 | } | ||
| 2650 | |||
| 2651 | if (aniState->noiseImmunityLevel > 0) { | ||
| 2652 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | ||
| 2653 | aniState->noiseImmunityLevel - 1); | ||
| 2654 | return; | ||
| 2655 | } | ||
| 2656 | } | ||
| 2657 | |||
| 2658 | static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) | ||
| 2659 | { | ||
| 2660 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2661 | struct ar5416AniState *aniState; | ||
| 2662 | u32 txFrameCount, rxFrameCount, cycleCount; | ||
| 2663 | int32_t listenTime; | ||
| 2664 | |||
| 2665 | txFrameCount = REG_READ(ah, AR_TFCNT); | ||
| 2666 | rxFrameCount = REG_READ(ah, AR_RFCNT); | ||
| 2667 | cycleCount = REG_READ(ah, AR_CCCNT); | ||
| 2668 | |||
| 2669 | aniState = ahp->ah_curani; | ||
| 2670 | if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { | ||
| 2671 | |||
| 2672 | listenTime = 0; | ||
| 2673 | ahp->ah_stats.ast_ani_lzero++; | ||
| 2674 | } else { | ||
| 2675 | int32_t ccdelta = cycleCount - aniState->cycleCount; | ||
| 2676 | int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; | ||
| 2677 | int32_t tfdelta = txFrameCount - aniState->txFrameCount; | ||
| 2678 | listenTime = (ccdelta - rfdelta - tfdelta) / 44000; | ||
| 2679 | } | ||
| 2680 | aniState->cycleCount = cycleCount; | ||
| 2681 | aniState->txFrameCount = txFrameCount; | ||
| 2682 | aniState->rxFrameCount = rxFrameCount; | ||
| 2683 | |||
| 2684 | return listenTime; | ||
| 2685 | } | ||
| 2686 | |||
| 2687 | void ath9k_hw_ani_monitor(struct ath_hal *ah, | ||
| 2688 | const struct ath9k_node_stats *stats, | ||
| 2689 | struct ath9k_channel *chan) | ||
| 2690 | { | ||
| 2691 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2692 | struct ar5416AniState *aniState; | ||
| 2693 | int32_t listenTime; | ||
| 2694 | |||
| 2695 | aniState = ahp->ah_curani; | ||
| 2696 | ahp->ah_stats.ast_nodestats = *stats; | ||
| 2697 | |||
| 2698 | listenTime = ath9k_hw_ani_get_listen_time(ah); | ||
| 2699 | if (listenTime < 0) { | ||
| 2700 | ahp->ah_stats.ast_ani_lneg++; | ||
| 2701 | ath9k_ani_restart(ah); | ||
| 2702 | return; | ||
| 2703 | } | ||
| 2704 | |||
| 2705 | aniState->listenTime += listenTime; | ||
| 2706 | |||
| 2707 | if (ahp->ah_hasHwPhyCounters) { | ||
| 2708 | u32 phyCnt1, phyCnt2; | ||
| 2709 | u32 ofdmPhyErrCnt, cckPhyErrCnt; | ||
| 2710 | |||
| 2711 | ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); | ||
| 2712 | |||
| 2713 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); | ||
| 2714 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | ||
| 2715 | |||
| 2716 | if (phyCnt1 < aniState->ofdmPhyErrBase || | ||
| 2717 | phyCnt2 < aniState->cckPhyErrBase) { | ||
| 2718 | if (phyCnt1 < aniState->ofdmPhyErrBase) { | ||
| 2719 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2720 | "%s: phyCnt1 0x%x, resetting " | ||
| 2721 | "counter value to 0x%x\n", | ||
| 2722 | __func__, phyCnt1, | ||
| 2723 | aniState->ofdmPhyErrBase); | ||
| 2724 | REG_WRITE(ah, AR_PHY_ERR_1, | ||
| 2725 | aniState->ofdmPhyErrBase); | ||
| 2726 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, | ||
| 2727 | AR_PHY_ERR_OFDM_TIMING); | ||
| 2728 | } | ||
| 2729 | if (phyCnt2 < aniState->cckPhyErrBase) { | ||
| 2730 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | ||
| 2731 | "%s: phyCnt2 0x%x, resetting " | ||
| 2732 | "counter value to 0x%x\n", | ||
| 2733 | __func__, phyCnt2, | ||
| 2734 | aniState->cckPhyErrBase); | ||
| 2735 | REG_WRITE(ah, AR_PHY_ERR_2, | ||
| 2736 | aniState->cckPhyErrBase); | ||
| 2737 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, | ||
| 2738 | AR_PHY_ERR_CCK_TIMING); | ||
| 2739 | } | ||
| 2740 | return; | ||
| 2741 | } | ||
| 2742 | |||
| 2743 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; | ||
| 2744 | ahp->ah_stats.ast_ani_ofdmerrs += | ||
| 2745 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; | ||
| 2746 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; | ||
| 2747 | |||
| 2748 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; | ||
| 2749 | ahp->ah_stats.ast_ani_cckerrs += | ||
| 2750 | cckPhyErrCnt - aniState->cckPhyErrCount; | ||
| 2751 | aniState->cckPhyErrCount = cckPhyErrCnt; | ||
| 2752 | } | ||
| 2753 | |||
| 2754 | if (!DO_ANI(ah)) | ||
| 2755 | return; | ||
| 2756 | |||
| 2757 | if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { | ||
| 2758 | if (aniState->ofdmPhyErrCount <= aniState->listenTime * | ||
| 2759 | aniState->ofdmTrigLow / 1000 && | ||
| 2760 | aniState->cckPhyErrCount <= aniState->listenTime * | ||
| 2761 | aniState->cckTrigLow / 1000) | ||
| 2762 | ath9k_hw_ani_lower_immunity(ah); | ||
| 2763 | ath9k_ani_restart(ah); | ||
| 2764 | } else if (aniState->listenTime > ahp->ah_aniPeriod) { | ||
| 2765 | if (aniState->ofdmPhyErrCount > aniState->listenTime * | ||
| 2766 | aniState->ofdmTrigHigh / 1000) { | ||
| 2767 | ath9k_hw_ani_ofdm_err_trigger(ah); | ||
| 2768 | ath9k_ani_restart(ah); | ||
| 2769 | } else if (aniState->cckPhyErrCount > | ||
| 2770 | aniState->listenTime * aniState->cckTrigHigh / | ||
| 2771 | 1000) { | ||
| 2772 | ath9k_hw_ani_cck_err_trigger(ah); | ||
| 2773 | ath9k_ani_restart(ah); | ||
| 2774 | } | ||
| 2775 | } | ||
| 2776 | } | ||
| 2777 | |||
| 2778 | #ifndef ATH_NF_PER_CHAN | ||
| 2779 | static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) | ||
| 2780 | { | ||
| 2781 | int i, j; | ||
| 2782 | |||
| 2783 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
| 2784 | ah->nfCalHist[i].currIndex = 0; | ||
| 2785 | ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE; | ||
| 2786 | ah->nfCalHist[i].invalidNFcount = | ||
| 2787 | AR_PHY_CCA_FILTERWINDOW_LENGTH; | ||
| 2788 | for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) { | ||
| 2789 | ah->nfCalHist[i].nfCalBuffer[j] = | ||
| 2790 | AR_PHY_CCA_MAX_GOOD_VALUE; | ||
| 2791 | } | ||
| 2792 | } | ||
| 2793 | return; | ||
| 2794 | } | ||
| 2795 | #endif | ||
| 2796 | |||
| 2797 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, | ||
| 2798 | u32 gpio, u32 type) | ||
| 2799 | { | ||
| 2800 | int addr; | ||
| 2801 | u32 gpio_shift, tmp; | ||
| 2802 | |||
| 2803 | if (gpio > 11) | ||
| 2804 | addr = AR_GPIO_OUTPUT_MUX3; | ||
| 2805 | else if (gpio > 5) | ||
| 2806 | addr = AR_GPIO_OUTPUT_MUX2; | ||
| 2807 | else | ||
| 2808 | addr = AR_GPIO_OUTPUT_MUX1; | ||
| 2809 | |||
| 2810 | gpio_shift = (gpio % 6) * 5; | ||
| 2811 | |||
| 2812 | if (AR_SREV_9280_20_OR_LATER(ah) | ||
| 2813 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | ||
| 2814 | REG_RMW(ah, addr, (type << gpio_shift), | ||
| 2815 | (0x1f << gpio_shift)); | ||
| 2816 | } else { | ||
| 2817 | tmp = REG_READ(ah, addr); | ||
| 2818 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | ||
| 2819 | tmp &= ~(0x1f << gpio_shift); | ||
| 2820 | tmp |= (type << gpio_shift); | ||
| 2821 | REG_WRITE(ah, addr, tmp); | ||
| 2822 | } | ||
| 2823 | } | ||
| 2824 | |||
| 2825 | static bool ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, | ||
| 2826 | enum ath9k_gpio_output_mux_type | ||
| 2827 | halSignalType) | ||
| 2828 | { | ||
| 2829 | u32 ah_signal_type; | ||
| 2830 | u32 gpio_shift; | ||
| 2831 | |||
| 2832 | static u32 MuxSignalConversionTable[] = { | ||
| 2833 | |||
| 2834 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT, | ||
| 2835 | |||
| 2836 | AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, | ||
| 2837 | |||
| 2838 | AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, | ||
| 2839 | |||
| 2840 | AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, | ||
| 2841 | |||
| 2842 | AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED, | ||
| 2843 | }; | ||
| 2844 | |||
| 2845 | if ((halSignalType >= 0) | ||
| 2846 | && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable))) | ||
| 2847 | ah_signal_type = MuxSignalConversionTable[halSignalType]; | ||
| 2848 | else | ||
| 2849 | return false; | ||
| 2850 | |||
| 2851 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); | ||
| 2852 | |||
| 2853 | gpio_shift = 2 * gpio; | ||
| 2854 | |||
| 2855 | REG_RMW(ah, | ||
| 2856 | AR_GPIO_OE_OUT, | ||
| 2857 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | ||
| 2858 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | ||
| 2859 | |||
| 2860 | return true; | ||
| 2861 | } | ||
| 2862 | |||
| 2863 | static bool ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, | ||
| 2864 | u32 val) | ||
| 2865 | { | ||
| 2866 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), | ||
| 2867 | AR_GPIO_BIT(gpio)); | ||
| 2868 | return true; | ||
| 2869 | } | ||
| 2870 | |||
| 2871 | static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) | ||
| 2872 | { | ||
| 2873 | if (gpio >= ah->ah_caps.num_gpio_pins) | ||
| 2874 | return 0xffffffff; | ||
| 2875 | |||
| 2876 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 2877 | return (MS | ||
| 2878 | (REG_READ(ah, AR_GPIO_IN_OUT), | ||
| 2879 | AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0; | ||
| 2880 | } else { | ||
| 2881 | return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) & | ||
| 2882 | AR_GPIO_BIT(gpio)) != 0; | ||
| 2883 | } | ||
| 2884 | } | ||
| 2885 | |||
| 2886 | static inline int ath9k_hw_post_attach(struct ath_hal *ah) | ||
| 2887 | { | ||
| 2888 | int ecode; | ||
| 2889 | |||
| 2890 | if (!ath9k_hw_chip_test(ah)) { | ||
| 2891 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 2892 | "%s: hardware self-test failed\n", __func__); | ||
| 2893 | return -ENODEV; | ||
| 2894 | } | ||
| 2895 | |||
| 2896 | ecode = ath9k_hw_rf_claim(ah); | ||
| 2897 | if (ecode != 0) | ||
| 2898 | return ecode; | ||
| 2899 | |||
| 2900 | ecode = ath9k_hw_eeprom_attach(ah); | ||
| 2901 | if (ecode != 0) | ||
| 2902 | return ecode; | ||
| 2903 | ecode = ath9k_hw_rfattach(ah); | ||
| 2904 | if (ecode != 0) | ||
| 2905 | return ecode; | ||
| 2906 | |||
| 2907 | if (!AR_SREV_9100(ah)) { | ||
| 2908 | ath9k_hw_ani_setup(ah); | ||
| 2909 | ath9k_hw_ani_attach(ah); | ||
| 2910 | } | ||
| 2911 | return 0; | ||
| 2912 | } | ||
| 2913 | |||
| 2914 | static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, | ||
| 2915 | struct ar5416_eeprom *pEepData, | ||
| 2916 | u32 reg, u32 value) | ||
| 2917 | { | ||
| 2918 | struct base_eep_header *pBase = &(pEepData->baseEepHeader); | ||
| 2919 | |||
| 2920 | switch (ah->ah_devid) { | ||
| 2921 | case AR9280_DEVID_PCI: | ||
| 2922 | if (reg == 0x7894) { | ||
| 2923 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 2924 | "ini VAL: %x EEPROM: %x\n", value, | ||
| 2925 | (pBase->version & 0xff)); | ||
| 2926 | |||
| 2927 | if ((pBase->version & 0xff) > 0x0a) { | ||
| 2928 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 2929 | "PWDCLKIND: %d\n", | ||
| 2930 | pBase->pwdclkind); | ||
| 2931 | value &= ~AR_AN_TOP2_PWDCLKIND; | ||
| 2932 | value |= AR_AN_TOP2_PWDCLKIND & (pBase-> | ||
| 2933 | pwdclkind << AR_AN_TOP2_PWDCLKIND_S); | ||
| 2934 | } else { | ||
| 2935 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 2936 | "PWDCLKIND Earlier Rev\n"); | ||
| 2937 | } | ||
| 2938 | |||
| 2939 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 2940 | "final ini VAL: %x\n", value); | ||
| 2941 | } | ||
| 2942 | break; | ||
| 2943 | } | ||
| 2944 | return value; | ||
| 2945 | } | ||
| 2946 | |||
| 2947 | static bool ath9k_hw_fill_cap_info(struct ath_hal *ah) | ||
| 2948 | { | ||
| 2949 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 2950 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 2951 | u16 capField = 0, eeval; | ||
| 2952 | |||
| 2953 | eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0); | ||
| 2954 | |||
| 2955 | ah->ah_currentRD = eeval; | ||
| 2956 | |||
| 2957 | eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1); | ||
| 2958 | ah->ah_currentRDExt = eeval; | ||
| 2959 | |||
| 2960 | capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP); | ||
| 2961 | |||
| 2962 | if (ah->ah_opmode != ATH9K_M_HOSTAP && | ||
| 2963 | ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { | ||
| 2964 | if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65) | ||
| 2965 | ah->ah_currentRD += 5; | ||
| 2966 | else if (ah->ah_currentRD == 0x41) | ||
| 2967 | ah->ah_currentRD = 0x43; | ||
| 2968 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 2969 | "%s: regdomain mapped to 0x%x\n", __func__, | ||
| 2970 | ah->ah_currentRD); | ||
| 2971 | } | ||
| 2972 | |||
| 2973 | eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE); | ||
| 2974 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); | ||
| 2975 | |||
| 2976 | if (eeval & AR5416_OPFLAGS_11A) { | ||
| 2977 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); | ||
| 2978 | if (ah->ah_config.ht_enable) { | ||
| 2979 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) | ||
| 2980 | set_bit(ATH9K_MODE_11NA_HT20, | ||
| 2981 | pCap->wireless_modes); | ||
| 2982 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { | ||
| 2983 | set_bit(ATH9K_MODE_11NA_HT40PLUS, | ||
| 2984 | pCap->wireless_modes); | ||
| 2985 | set_bit(ATH9K_MODE_11NA_HT40MINUS, | ||
| 2986 | pCap->wireless_modes); | ||
| 2987 | } | ||
| 2988 | } | ||
| 2989 | } | ||
| 2990 | |||
| 2991 | if (eeval & AR5416_OPFLAGS_11G) { | ||
| 2992 | set_bit(ATH9K_MODE_11B, pCap->wireless_modes); | ||
| 2993 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); | ||
| 2994 | if (ah->ah_config.ht_enable) { | ||
| 2995 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) | ||
| 2996 | set_bit(ATH9K_MODE_11NG_HT20, | ||
| 2997 | pCap->wireless_modes); | ||
| 2998 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { | ||
| 2999 | set_bit(ATH9K_MODE_11NG_HT40PLUS, | ||
| 3000 | pCap->wireless_modes); | ||
| 3001 | set_bit(ATH9K_MODE_11NG_HT40MINUS, | ||
| 3002 | pCap->wireless_modes); | ||
| 3003 | } | ||
| 3004 | } | ||
| 3005 | } | ||
| 3006 | |||
| 3007 | pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK); | ||
| 3008 | if ((ah->ah_isPciExpress) | ||
| 3009 | || (eeval & AR5416_OPFLAGS_11A)) { | ||
| 3010 | pCap->rx_chainmask = | ||
| 3011 | ath9k_hw_get_eeprom(ahp, EEP_RX_MASK); | ||
| 3012 | } else { | ||
| 3013 | pCap->rx_chainmask = | ||
| 3014 | (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; | ||
| 3015 | } | ||
| 3016 | |||
| 3017 | if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) | ||
| 3018 | ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; | ||
| 3019 | |||
| 3020 | pCap->low_2ghz_chan = 2312; | ||
| 3021 | pCap->high_2ghz_chan = 2732; | ||
| 3022 | |||
| 3023 | pCap->low_5ghz_chan = 4920; | ||
| 3024 | pCap->high_5ghz_chan = 6100; | ||
| 3025 | |||
| 3026 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; | ||
| 3027 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; | ||
| 3028 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; | ||
| 3029 | |||
| 3030 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; | ||
| 3031 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; | ||
| 3032 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; | ||
| 3033 | |||
| 3034 | pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; | ||
| 3035 | |||
| 3036 | if (ah->ah_config.ht_enable) | ||
| 3037 | pCap->hw_caps |= ATH9K_HW_CAP_HT; | ||
| 3038 | else | ||
| 3039 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | ||
| 3040 | |||
| 3041 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; | ||
| 3042 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; | ||
| 3043 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; | ||
| 3044 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; | ||
| 3045 | |||
| 3046 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) | ||
| 3047 | pCap->total_queues = | ||
| 3048 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | ||
| 3049 | else | ||
| 3050 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | ||
| 3051 | |||
| 3052 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) | ||
| 3053 | pCap->keycache_size = | ||
| 3054 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | ||
| 3055 | else | ||
| 3056 | pCap->keycache_size = AR_KEYTABLE_SIZE; | ||
| 3057 | |||
| 3058 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; | ||
| 3059 | pCap->num_mr_retries = 4; | ||
| 3060 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | ||
| 3061 | |||
| 3062 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 3063 | pCap->num_gpio_pins = AR928X_NUM_GPIO; | ||
| 3064 | else | ||
| 3065 | pCap->num_gpio_pins = AR_NUM_GPIO; | ||
| 3066 | |||
| 3067 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 3068 | pCap->hw_caps |= ATH9K_HW_CAP_WOW; | ||
| 3069 | pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | ||
| 3070 | } else { | ||
| 3071 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW; | ||
| 3072 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | ||
| 3073 | } | ||
| 3074 | |||
| 3075 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { | ||
| 3076 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | ||
| 3077 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | ||
| 3078 | } else { | ||
| 3079 | pCap->rts_aggr_limit = (8 * 1024); | ||
| 3080 | } | ||
| 3081 | |||
| 3082 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; | ||
| 3083 | |||
| 3084 | ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT); | ||
| 3085 | if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { | ||
| 3086 | ahp->ah_gpioSelect = | ||
| 3087 | MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); | ||
| 3088 | ahp->ah_polarity = | ||
| 3089 | MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); | ||
| 3090 | |||
| 3091 | ath9k_hw_setcapability(ah, ATH9K_CAP_RFSILENT, 1, true, | ||
| 3092 | NULL); | ||
| 3093 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | ||
| 3094 | } | ||
| 3095 | |||
| 3096 | if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || | ||
| 3097 | (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || | ||
| 3098 | (ah->ah_macVersion == AR_SREV_VERSION_9160) || | ||
| 3099 | (ah->ah_macVersion == AR_SREV_VERSION_9100) || | ||
| 3100 | (ah->ah_macVersion == AR_SREV_VERSION_9280)) | ||
| 3101 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | ||
| 3102 | else | ||
| 3103 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; | ||
| 3104 | |||
| 3105 | if (AR_SREV_9280(ah)) | ||
| 3106 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; | ||
| 3107 | else | ||
| 3108 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | ||
| 3109 | |||
| 3110 | if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { | ||
| 3111 | pCap->reg_cap = | ||
| 3112 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | ||
| 3113 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | ||
| 3114 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | ||
| 3115 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | ||
| 3116 | } else { | ||
| 3117 | pCap->reg_cap = | ||
| 3118 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | ||
| 3119 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | ||
| 3120 | } | ||
| 3121 | |||
| 3122 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; | ||
| 3123 | |||
| 3124 | pCap->num_antcfg_5ghz = | ||
| 3125 | ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ); | ||
| 3126 | pCap->num_antcfg_2ghz = | ||
| 3127 | ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ); | ||
| 3128 | |||
| 3129 | return true; | ||
| 3130 | } | ||
| 3131 | |||
| 3132 | static void ar5416DisablePciePhy(struct ath_hal *ah) | ||
| 3133 | { | ||
| 3134 | if (!AR_SREV_9100(ah)) | ||
| 3135 | return; | ||
| 3136 | |||
| 3137 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | ||
| 3138 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | ||
| 3139 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | ||
| 3140 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | ||
| 3141 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | ||
| 3142 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | ||
| 3143 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | ||
| 3144 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | ||
| 3145 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | ||
| 3146 | |||
| 3147 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | ||
| 3148 | } | ||
| 3149 | |||
| 3150 | static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) | ||
| 3151 | { | ||
| 3152 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | ||
| 3153 | if (setChip) { | ||
| 3154 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | ||
| 3155 | AR_RTC_FORCE_WAKE_EN); | ||
| 3156 | if (!AR_SREV_9100(ah)) | ||
| 3157 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | ||
| 3158 | |||
| 3159 | REG_CLR_BIT(ah, (u16) (AR_RTC_RESET), | ||
| 3160 | AR_RTC_RESET_EN); | ||
| 3161 | } | ||
| 3162 | } | ||
| 3163 | |||
| 3164 | static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) | ||
| 3165 | { | ||
| 3166 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | ||
| 3167 | if (setChip) { | ||
| 3168 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 3169 | |||
| 3170 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | ||
| 3171 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | ||
| 3172 | AR_RTC_FORCE_WAKE_ON_INT); | ||
| 3173 | } else { | ||
| 3174 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, | ||
| 3175 | AR_RTC_FORCE_WAKE_EN); | ||
| 3176 | } | ||
| 3177 | } | ||
| 3178 | } | ||
| 3179 | |||
| 3180 | static bool ath9k_hw_set_power_awake(struct ath_hal *ah, | ||
| 3181 | int setChip) | ||
| 3182 | { | ||
| 3183 | u32 val; | ||
| 3184 | int i; | ||
| 3185 | |||
| 3186 | if (setChip) { | ||
| 3187 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == | ||
| 3188 | AR_RTC_STATUS_SHUTDOWN) { | ||
| 3189 | if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON) | ||
| 3190 | != true) { | ||
| 3191 | return false; | ||
| 3192 | } | ||
| 3193 | } | ||
| 3194 | if (AR_SREV_9100(ah)) | ||
| 3195 | REG_SET_BIT(ah, AR_RTC_RESET, | ||
| 3196 | AR_RTC_RESET_EN); | ||
| 3197 | |||
| 3198 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | ||
| 3199 | AR_RTC_FORCE_WAKE_EN); | ||
| 3200 | udelay(50); | ||
| 3201 | |||
| 3202 | for (i = POWER_UP_TIME / 50; i > 0; i--) { | ||
| 3203 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | ||
| 3204 | if (val == AR_RTC_STATUS_ON) | ||
| 3205 | break; | ||
| 3206 | udelay(50); | ||
| 3207 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | ||
| 3208 | AR_RTC_FORCE_WAKE_EN); | ||
| 3209 | } | ||
| 3210 | if (i == 0) { | ||
| 3211 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 3212 | "%s: Failed to wakeup in %uus\n", | ||
| 3213 | __func__, POWER_UP_TIME / 20); | ||
| 3214 | return false; | ||
| 3215 | } | ||
| 3216 | } | ||
| 3217 | |||
| 3218 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | ||
| 3219 | return true; | ||
| 3220 | } | ||
| 3221 | |||
| 3222 | bool ath9k_hw_setpower(struct ath_hal *ah, | ||
| 3223 | enum ath9k_power_mode mode) | ||
| 3224 | { | ||
| 3225 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 3226 | static const char *modes[] = { | ||
| 3227 | "AWAKE", | ||
| 3228 | "FULL-SLEEP", | ||
| 3229 | "NETWORK SLEEP", | ||
| 3230 | "UNDEFINED" | ||
| 3231 | }; | ||
| 3232 | int status = true, setChip = true; | ||
| 3233 | |||
| 3234 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, | ||
| 3235 | modes[ahp->ah_powerMode], modes[mode], | ||
| 3236 | setChip ? "set chip " : ""); | ||
| 3237 | |||
| 3238 | switch (mode) { | ||
| 3239 | case ATH9K_PM_AWAKE: | ||
| 3240 | status = ath9k_hw_set_power_awake(ah, setChip); | ||
| 3241 | break; | ||
| 3242 | case ATH9K_PM_FULL_SLEEP: | ||
| 3243 | ath9k_set_power_sleep(ah, setChip); | ||
| 3244 | ahp->ah_chipFullSleep = true; | ||
| 3245 | break; | ||
| 3246 | case ATH9K_PM_NETWORK_SLEEP: | ||
| 3247 | ath9k_set_power_network_sleep(ah, setChip); | ||
| 3248 | break; | ||
| 3249 | default: | ||
| 3250 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 3251 | "%s: unknown power mode %u\n", __func__, mode); | ||
| 3252 | return false; | ||
| 3253 | } | ||
| 3254 | ahp->ah_powerMode = mode; | ||
| 3255 | return status; | ||
| 3256 | } | ||
| 3257 | |||
| 3258 | static struct ath_hal *ath9k_hw_do_attach(u16 devid, | ||
| 3259 | struct ath_softc *sc, | ||
| 3260 | void __iomem *mem, | ||
| 3261 | int *status) | ||
| 3262 | { | ||
| 3263 | struct ath_hal_5416 *ahp; | ||
| 3264 | struct ath_hal *ah; | ||
| 3265 | int ecode; | ||
| 3266 | #ifndef CONFIG_SLOW_ANT_DIV | ||
| 3267 | u32 i; | ||
| 3268 | u32 j; | ||
| 3269 | #endif | ||
| 3270 | |||
| 3271 | ahp = ath9k_hw_newstate(devid, sc, mem, status); | ||
| 3272 | if (ahp == NULL) | ||
| 3273 | return NULL; | ||
| 3274 | |||
| 3275 | ah = &ahp->ah; | ||
| 3276 | |||
| 3277 | ath9k_hw_set_defaults(ah); | ||
| 3278 | |||
| 3279 | if (ah->ah_config.intr_mitigation != 0) | ||
| 3280 | ahp->ah_intrMitigation = true; | ||
| 3281 | |||
| 3282 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | ||
| 3283 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n", | ||
| 3284 | __func__); | ||
| 3285 | ecode = -EIO; | ||
| 3286 | goto bad; | ||
| 3287 | } | ||
| 3288 | |||
| 3289 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { | ||
| 3290 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n", | ||
| 3291 | __func__); | ||
| 3292 | ecode = -EIO; | ||
| 3293 | goto bad; | ||
| 3294 | } | ||
| 3295 | |||
| 3296 | if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { | ||
| 3297 | if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) { | ||
| 3298 | ah->ah_config.serialize_regmode = | ||
| 3299 | SER_REG_MODE_ON; | ||
| 3300 | } else { | ||
| 3301 | ah->ah_config.serialize_regmode = | ||
| 3302 | SER_REG_MODE_OFF; | ||
| 3303 | } | ||
| 3304 | } | ||
| 3305 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 3306 | "%s: serialize_regmode is %d\n", | ||
| 3307 | __func__, ah->ah_config.serialize_regmode); | ||
| 3308 | |||
| 3309 | if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && | ||
| 3310 | (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && | ||
| 3311 | (ah->ah_macVersion != AR_SREV_VERSION_9160) && | ||
| 3312 | (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { | ||
| 3313 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 3314 | "%s: Mac Chip Rev 0x%02x.%x is not supported by " | ||
| 3315 | "this driver\n", __func__, | ||
| 3316 | ah->ah_macVersion, ah->ah_macRev); | ||
| 3317 | ecode = -EOPNOTSUPP; | ||
| 3318 | goto bad; | ||
| 3319 | } | ||
| 3320 | |||
| 3321 | if (AR_SREV_9100(ah)) { | ||
| 3322 | ahp->ah_iqCalData.calData = &iq_cal_multi_sample; | ||
| 3323 | ahp->ah_suppCals = IQ_MISMATCH_CAL; | ||
| 3324 | ah->ah_isPciExpress = false; | ||
| 3325 | } | ||
| 3326 | ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); | ||
| 3327 | |||
| 3328 | if (AR_SREV_9160_10_OR_LATER(ah)) { | ||
| 3329 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 3330 | ahp->ah_iqCalData.calData = &iq_cal_single_sample; | ||
| 3331 | ahp->ah_adcGainCalData.calData = | ||
| 3332 | &adc_gain_cal_single_sample; | ||
| 3333 | ahp->ah_adcDcCalData.calData = | ||
| 3334 | &adc_dc_cal_single_sample; | ||
| 3335 | ahp->ah_adcDcCalInitData.calData = | ||
| 3336 | &adc_init_dc_cal; | ||
| 3337 | } else { | ||
| 3338 | ahp->ah_iqCalData.calData = &iq_cal_multi_sample; | ||
| 3339 | ahp->ah_adcGainCalData.calData = | ||
| 3340 | &adc_gain_cal_multi_sample; | ||
| 3341 | ahp->ah_adcDcCalData.calData = | ||
| 3342 | &adc_dc_cal_multi_sample; | ||
| 3343 | ahp->ah_adcDcCalInitData.calData = | ||
| 3344 | &adc_init_dc_cal; | ||
| 3345 | } | ||
| 3346 | ahp->ah_suppCals = | ||
| 3347 | ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; | ||
| 3348 | } | ||
| 3349 | |||
| 3350 | if (AR_SREV_9160(ah)) { | ||
| 3351 | ah->ah_config.enable_ani = 1; | ||
| 3352 | ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | | ||
| 3353 | ATH9K_ANI_FIRSTEP_LEVEL); | ||
| 3354 | } else { | ||
| 3355 | ahp->ah_ani_function = ATH9K_ANI_ALL; | ||
| 3356 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 3357 | ahp->ah_ani_function &= | ||
| 3358 | ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; | ||
| 3359 | } | ||
| 3360 | } | ||
| 3361 | |||
| 3362 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 3363 | "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, | ||
| 3364 | ah->ah_macVersion, ah->ah_macRev); | ||
| 3365 | |||
| 3366 | if (AR_SREV_9280_20_OR_LATER(ah)) { | ||
| 3367 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, | ||
| 3368 | ARRAY_SIZE(ar9280Modes_9280_2), 6); | ||
| 3369 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, | ||
| 3370 | ARRAY_SIZE(ar9280Common_9280_2), 2); | ||
| 3371 | |||
| 3372 | if (ah->ah_config.pcie_clock_req) { | ||
| 3373 | INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, | ||
| 3374 | ar9280PciePhy_clkreq_off_L1_9280, | ||
| 3375 | ARRAY_SIZE | ||
| 3376 | (ar9280PciePhy_clkreq_off_L1_9280), | ||
| 3377 | 2); | ||
| 3378 | } else { | ||
| 3379 | INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, | ||
| 3380 | ar9280PciePhy_clkreq_always_on_L1_9280, | ||
| 3381 | ARRAY_SIZE | ||
| 3382 | (ar9280PciePhy_clkreq_always_on_L1_9280), | ||
| 3383 | 2); | ||
| 3384 | } | ||
| 3385 | INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, | ||
| 3386 | ar9280Modes_fast_clock_9280_2, | ||
| 3387 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), | ||
| 3388 | 3); | ||
| 3389 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 3390 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, | ||
| 3391 | ARRAY_SIZE(ar9280Modes_9280), 6); | ||
| 3392 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, | ||
| 3393 | ARRAY_SIZE(ar9280Common_9280), 2); | ||
| 3394 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | ||
| 3395 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, | ||
| 3396 | ARRAY_SIZE(ar5416Modes_9160), 6); | ||
| 3397 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, | ||
| 3398 | ARRAY_SIZE(ar5416Common_9160), 2); | ||
| 3399 | INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, | ||
| 3400 | ARRAY_SIZE(ar5416Bank0_9160), 2); | ||
| 3401 | INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, | ||
| 3402 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); | ||
| 3403 | INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, | ||
| 3404 | ARRAY_SIZE(ar5416Bank1_9160), 2); | ||
| 3405 | INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, | ||
| 3406 | ARRAY_SIZE(ar5416Bank2_9160), 2); | ||
| 3407 | INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, | ||
| 3408 | ARRAY_SIZE(ar5416Bank3_9160), 3); | ||
| 3409 | INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, | ||
| 3410 | ARRAY_SIZE(ar5416Bank6_9160), 3); | ||
| 3411 | INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, | ||
| 3412 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); | ||
| 3413 | INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, | ||
| 3414 | ARRAY_SIZE(ar5416Bank7_9160), 2); | ||
| 3415 | if (AR_SREV_9160_11(ah)) { | ||
| 3416 | INIT_INI_ARRAY(&ahp->ah_iniAddac, | ||
| 3417 | ar5416Addac_91601_1, | ||
| 3418 | ARRAY_SIZE(ar5416Addac_91601_1), 2); | ||
| 3419 | } else { | ||
| 3420 | INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, | ||
| 3421 | ARRAY_SIZE(ar5416Addac_9160), 2); | ||
| 3422 | } | ||
| 3423 | } else if (AR_SREV_9100_OR_LATER(ah)) { | ||
| 3424 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, | ||
| 3425 | ARRAY_SIZE(ar5416Modes_9100), 6); | ||
| 3426 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, | ||
| 3427 | ARRAY_SIZE(ar5416Common_9100), 2); | ||
| 3428 | INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, | ||
| 3429 | ARRAY_SIZE(ar5416Bank0_9100), 2); | ||
| 3430 | INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, | ||
| 3431 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); | ||
| 3432 | INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, | ||
| 3433 | ARRAY_SIZE(ar5416Bank1_9100), 2); | ||
| 3434 | INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, | ||
| 3435 | ARRAY_SIZE(ar5416Bank2_9100), 2); | ||
| 3436 | INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, | ||
| 3437 | ARRAY_SIZE(ar5416Bank3_9100), 3); | ||
| 3438 | INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, | ||
| 3439 | ARRAY_SIZE(ar5416Bank6_9100), 3); | ||
| 3440 | INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, | ||
| 3441 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); | ||
| 3442 | INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, | ||
| 3443 | ARRAY_SIZE(ar5416Bank7_9100), 2); | ||
| 3444 | INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, | ||
| 3445 | ARRAY_SIZE(ar5416Addac_9100), 2); | ||
| 3446 | } else { | ||
| 3447 | INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, | ||
| 3448 | ARRAY_SIZE(ar5416Modes), 6); | ||
| 3449 | INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, | ||
| 3450 | ARRAY_SIZE(ar5416Common), 2); | ||
| 3451 | INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, | ||
| 3452 | ARRAY_SIZE(ar5416Bank0), 2); | ||
| 3453 | INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, | ||
| 3454 | ARRAY_SIZE(ar5416BB_RfGain), 3); | ||
| 3455 | INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, | ||
| 3456 | ARRAY_SIZE(ar5416Bank1), 2); | ||
| 3457 | INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, | ||
| 3458 | ARRAY_SIZE(ar5416Bank2), 2); | ||
| 3459 | INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, | ||
| 3460 | ARRAY_SIZE(ar5416Bank3), 3); | ||
| 3461 | INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, | ||
| 3462 | ARRAY_SIZE(ar5416Bank6), 3); | ||
| 3463 | INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, | ||
| 3464 | ARRAY_SIZE(ar5416Bank6TPC), 3); | ||
| 3465 | INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, | ||
| 3466 | ARRAY_SIZE(ar5416Bank7), 2); | ||
| 3467 | INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, | ||
| 3468 | ARRAY_SIZE(ar5416Addac), 2); | ||
| 3469 | } | ||
| 3470 | |||
| 3471 | if (ah->ah_isPciExpress) | ||
| 3472 | ath9k_hw_configpcipowersave(ah, 0); | ||
| 3473 | else | ||
| 3474 | ar5416DisablePciePhy(ah); | ||
| 3475 | |||
| 3476 | ecode = ath9k_hw_post_attach(ah); | ||
| 3477 | if (ecode != 0) | ||
| 3478 | goto bad; | ||
| 3479 | |||
| 3480 | #ifndef CONFIG_SLOW_ANT_DIV | ||
| 3481 | if (ah->ah_devid == AR9280_DEVID_PCI) { | ||
| 3482 | for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { | ||
| 3483 | u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); | ||
| 3484 | |||
| 3485 | for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { | ||
| 3486 | u32 val = INI_RA(&ahp->ah_iniModes, i, j); | ||
| 3487 | |||
| 3488 | INI_RA(&ahp->ah_iniModes, i, j) = | ||
| 3489 | ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, | ||
| 3490 | reg, val); | ||
| 3491 | } | ||
| 3492 | } | ||
| 3493 | } | ||
| 3494 | #endif | ||
| 3495 | |||
| 3496 | if (!ath9k_hw_fill_cap_info(ah)) { | ||
| 3497 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 3498 | "%s:failed ath9k_hw_fill_cap_info\n", __func__); | ||
| 3499 | ecode = -EINVAL; | ||
| 3500 | goto bad; | ||
| 3501 | } | ||
| 3502 | |||
| 3503 | ecode = ath9k_hw_init_macaddr(ah); | ||
| 3504 | if (ecode != 0) { | ||
| 3505 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 3506 | "%s: failed initializing mac address\n", | ||
| 3507 | __func__); | ||
| 3508 | goto bad; | ||
| 3509 | } | ||
| 3510 | |||
| 3511 | if (AR_SREV_9285(ah)) | ||
| 3512 | ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); | ||
| 3513 | else | ||
| 3514 | ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); | ||
| 3515 | |||
| 3516 | #ifndef ATH_NF_PER_CHAN | ||
| 3517 | |||
| 3518 | ath9k_init_nfcal_hist_buffer(ah); | ||
| 3519 | #endif | ||
| 3520 | |||
| 3521 | return ah; | ||
| 3522 | |||
| 3523 | bad: | ||
| 3524 | if (ahp) | ||
| 3525 | ath9k_hw_detach((struct ath_hal *) ahp); | ||
| 3526 | if (status) | ||
| 3527 | *status = ecode; | ||
| 3528 | return NULL; | ||
| 3529 | } | ||
| 3530 | |||
| 3531 | void ath9k_hw_detach(struct ath_hal *ah) | ||
| 3532 | { | ||
| 3533 | if (!AR_SREV_9100(ah)) | ||
| 3534 | ath9k_hw_ani_detach(ah); | ||
| 3535 | ath9k_hw_rfdetach(ah); | ||
| 3536 | |||
| 3537 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); | ||
| 3538 | kfree(ah); | ||
| 3539 | } | ||
| 3540 | |||
| 3541 | bool ath9k_get_channel_edges(struct ath_hal *ah, | ||
| 3542 | u16 flags, u16 *low, | ||
| 3543 | u16 *high) | ||
| 3544 | { | ||
| 3545 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 3546 | |||
| 3547 | if (flags & CHANNEL_5GHZ) { | ||
| 3548 | *low = pCap->low_5ghz_chan; | ||
| 3549 | *high = pCap->high_5ghz_chan; | ||
| 3550 | return true; | ||
| 3551 | } | ||
| 3552 | if ((flags & CHANNEL_2GHZ)) { | ||
| 3553 | *low = pCap->low_2ghz_chan; | ||
| 3554 | *high = pCap->high_2ghz_chan; | ||
| 3555 | |||
| 3556 | return true; | ||
| 3557 | } | ||
| 3558 | return false; | ||
| 3559 | } | ||
| 3560 | |||
| 3561 | static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, | ||
| 3562 | u8 pwrMax, | ||
| 3563 | u8 *pPwrList, | ||
| 3564 | u8 *pVpdList, | ||
| 3565 | u16 | ||
| 3566 | numIntercepts, | ||
| 3567 | u8 *pRetVpdList) | ||
| 3568 | { | ||
| 3569 | u16 i, k; | ||
| 3570 | u8 currPwr = pwrMin; | ||
| 3571 | u16 idxL = 0, idxR = 0; | ||
| 3572 | |||
| 3573 | for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { | ||
| 3574 | ath9k_hw_get_lower_upper_index(currPwr, pPwrList, | ||
| 3575 | numIntercepts, &(idxL), | ||
| 3576 | &(idxR)); | ||
| 3577 | if (idxR < 1) | ||
| 3578 | idxR = 1; | ||
| 3579 | if (idxL == numIntercepts - 1) | ||
| 3580 | idxL = (u16) (numIntercepts - 2); | ||
| 3581 | if (pPwrList[idxL] == pPwrList[idxR]) | ||
| 3582 | k = pVpdList[idxL]; | ||
| 3583 | else | ||
| 3584 | k = (u16) (((currPwr - | ||
| 3585 | pPwrList[idxL]) * | ||
| 3586 | pVpdList[idxR] + | ||
| 3587 | (pPwrList[idxR] - | ||
| 3588 | currPwr) * pVpdList[idxL]) / | ||
| 3589 | (pPwrList[idxR] - | ||
| 3590 | pPwrList[idxL])); | ||
| 3591 | pRetVpdList[i] = (u8) k; | ||
| 3592 | currPwr += 2; | ||
| 3593 | } | ||
| 3594 | |||
| 3595 | return true; | ||
| 3596 | } | ||
| 3597 | |||
| 3598 | static inline void | ||
| 3599 | ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah, | ||
| 3600 | struct ath9k_channel *chan, | ||
| 3601 | struct cal_data_per_freq *pRawDataSet, | ||
| 3602 | u8 *bChans, | ||
| 3603 | u16 availPiers, | ||
| 3604 | u16 tPdGainOverlap, | ||
| 3605 | int16_t *pMinCalPower, | ||
| 3606 | u16 *pPdGainBoundaries, | ||
| 3607 | u8 *pPDADCValues, | ||
| 3608 | u16 numXpdGains) | ||
| 3609 | { | ||
| 3610 | int i, j, k; | ||
| 3611 | int16_t ss; | ||
| 3612 | u16 idxL = 0, idxR = 0, numPiers; | ||
| 3613 | static u8 vpdTableL[AR5416_NUM_PD_GAINS] | ||
| 3614 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | ||
| 3615 | static u8 vpdTableR[AR5416_NUM_PD_GAINS] | ||
| 3616 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | ||
| 3617 | static u8 vpdTableI[AR5416_NUM_PD_GAINS] | ||
| 3618 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | ||
| 3619 | |||
| 3620 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | ||
| 3621 | u8 minPwrT4[AR5416_NUM_PD_GAINS]; | ||
| 3622 | u8 maxPwrT4[AR5416_NUM_PD_GAINS]; | ||
| 3623 | int16_t vpdStep; | ||
| 3624 | int16_t tmpVal; | ||
| 3625 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | ||
| 3626 | bool match; | ||
| 3627 | int16_t minDelta = 0; | ||
| 3628 | struct chan_centers centers; | ||
| 3629 | |||
| 3630 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 3631 | |||
| 3632 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | ||
| 3633 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) | ||
| 3634 | break; | ||
| 3635 | } | ||
| 3636 | |||
| 3637 | match = ath9k_hw_get_lower_upper_index((u8) | ||
| 3638 | FREQ2FBIN(centers. | ||
| 3639 | synth_center, | ||
| 3640 | IS_CHAN_2GHZ | ||
| 3641 | (chan)), bChans, | ||
| 3642 | numPiers, &idxL, &idxR); | ||
| 3643 | |||
| 3644 | if (match) { | ||
| 3645 | for (i = 0; i < numXpdGains; i++) { | ||
| 3646 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; | ||
| 3647 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; | ||
| 3648 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | ||
| 3649 | pRawDataSet[idxL]. | ||
| 3650 | pwrPdg[i], | ||
| 3651 | pRawDataSet[idxL]. | ||
| 3652 | vpdPdg[i], | ||
| 3653 | AR5416_PD_GAIN_ICEPTS, | ||
| 3654 | vpdTableI[i]); | ||
| 3655 | } | ||
| 3656 | } else { | ||
| 3657 | for (i = 0; i < numXpdGains; i++) { | ||
| 3658 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; | ||
| 3659 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; | ||
| 3660 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; | ||
| 3661 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; | ||
| 3662 | |||
| 3663 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); | ||
| 3664 | |||
| 3665 | maxPwrT4[i] = | ||
| 3666 | min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], | ||
| 3667 | pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); | ||
| 3668 | |||
| 3669 | |||
| 3670 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | ||
| 3671 | pPwrL, pVpdL, | ||
| 3672 | AR5416_PD_GAIN_ICEPTS, | ||
| 3673 | vpdTableL[i]); | ||
| 3674 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | ||
| 3675 | pPwrR, pVpdR, | ||
| 3676 | AR5416_PD_GAIN_ICEPTS, | ||
| 3677 | vpdTableR[i]); | ||
| 3678 | |||
| 3679 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | ||
| 3680 | vpdTableI[i][j] = | ||
| 3681 | (u8) (ath9k_hw_interpolate | ||
| 3682 | ((u16) | ||
| 3683 | FREQ2FBIN(centers. | ||
| 3684 | synth_center, | ||
| 3685 | IS_CHAN_2GHZ | ||
| 3686 | (chan)), | ||
| 3687 | bChans[idxL], | ||
| 3688 | bChans[idxR], vpdTableL[i] | ||
| 3689 | [j], vpdTableR[i] | ||
| 3690 | [j])); | ||
| 3691 | } | ||
| 3692 | } | ||
| 3693 | } | ||
| 3694 | |||
| 3695 | *pMinCalPower = (int16_t) (minPwrT4[0] / 2); | ||
| 3696 | |||
| 3697 | k = 0; | ||
| 3698 | for (i = 0; i < numXpdGains; i++) { | ||
| 3699 | if (i == (numXpdGains - 1)) | ||
| 3700 | pPdGainBoundaries[i] = | ||
| 3701 | (u16) (maxPwrT4[i] / 2); | ||
| 3702 | else | ||
| 3703 | pPdGainBoundaries[i] = | ||
| 3704 | (u16) ((maxPwrT4[i] + | ||
| 3705 | minPwrT4[i + 1]) / 4); | ||
| 3706 | |||
| 3707 | pPdGainBoundaries[i] = | ||
| 3708 | min((u16) AR5416_MAX_RATE_POWER, | ||
| 3709 | pPdGainBoundaries[i]); | ||
| 3710 | |||
| 3711 | if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { | ||
| 3712 | minDelta = pPdGainBoundaries[0] - 23; | ||
| 3713 | pPdGainBoundaries[0] = 23; | ||
| 3714 | } else { | ||
| 3715 | minDelta = 0; | ||
| 3716 | } | ||
| 3717 | |||
| 3718 | if (i == 0) { | ||
| 3719 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 3720 | ss = (int16_t) (0 - (minPwrT4[i] / 2)); | ||
| 3721 | else | ||
| 3722 | ss = 0; | ||
| 3723 | } else { | ||
| 3724 | ss = (int16_t) ((pPdGainBoundaries[i - 1] - | ||
| 3725 | (minPwrT4[i] / 2)) - | ||
| 3726 | tPdGainOverlap + 1 + minDelta); | ||
| 3727 | } | ||
| 3728 | vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]); | ||
| 3729 | vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep); | ||
| 3730 | |||
| 3731 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | ||
| 3732 | tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep); | ||
| 3733 | pPDADCValues[k++] = | ||
| 3734 | (u8) ((tmpVal < 0) ? 0 : tmpVal); | ||
| 3735 | ss++; | ||
| 3736 | } | ||
| 3737 | |||
| 3738 | sizeCurrVpdTable = | ||
| 3739 | (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); | ||
| 3740 | tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap - | ||
| 3741 | (minPwrT4[i] / 2)); | ||
| 3742 | maxIndex = (tgtIndex < | ||
| 3743 | sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; | ||
| 3744 | |||
| 3745 | while ((ss < maxIndex) | ||
| 3746 | && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | ||
| 3747 | pPDADCValues[k++] = vpdTableI[i][ss++]; | ||
| 3748 | } | ||
| 3749 | |||
| 3750 | vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] - | ||
| 3751 | vpdTableI[i][sizeCurrVpdTable - 2]); | ||
| 3752 | vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep); | ||
| 3753 | |||
| 3754 | if (tgtIndex > maxIndex) { | ||
| 3755 | while ((ss <= tgtIndex) | ||
| 3756 | && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | ||
| 3757 | tmpVal = (int16_t) ((vpdTableI[i] | ||
| 3758 | [sizeCurrVpdTable - | ||
| 3759 | 1] + (ss - maxIndex + | ||
| 3760 | 1) * vpdStep)); | ||
| 3761 | pPDADCValues[k++] = (u8) ((tmpVal > | ||
| 3762 | 255) ? 255 : tmpVal); | ||
| 3763 | ss++; | ||
| 3764 | } | ||
| 3765 | } | ||
| 3766 | } | ||
| 3767 | |||
| 3768 | while (i < AR5416_PD_GAINS_IN_MASK) { | ||
| 3769 | pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; | ||
| 3770 | i++; | ||
| 3771 | } | ||
| 3772 | |||
| 3773 | while (k < AR5416_NUM_PDADC_VALUES) { | ||
| 3774 | pPDADCValues[k] = pPDADCValues[k - 1]; | ||
| 3775 | k++; | ||
| 3776 | } | ||
| 3777 | return; | ||
| 3778 | } | ||
| 3779 | |||
| 3780 | static inline bool | ||
| 3781 | ath9k_hw_set_power_cal_table(struct ath_hal *ah, | ||
| 3782 | struct ar5416_eeprom *pEepData, | ||
| 3783 | struct ath9k_channel *chan, | ||
| 3784 | int16_t *pTxPowerIndexOffset) | ||
| 3785 | { | ||
| 3786 | struct cal_data_per_freq *pRawDataset; | ||
| 3787 | u8 *pCalBChans = NULL; | ||
| 3788 | u16 pdGainOverlap_t2; | ||
| 3789 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | ||
| 3790 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; | ||
| 3791 | u16 numPiers, i, j; | ||
| 3792 | int16_t tMinCalPower; | ||
| 3793 | u16 numXpdGain, xpdMask; | ||
| 3794 | u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; | ||
| 3795 | u32 reg32, regOffset, regChainOffset; | ||
| 3796 | int16_t modalIdx; | ||
| 3797 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 3798 | |||
| 3799 | modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; | ||
| 3800 | xpdMask = pEepData->modalHeader[modalIdx].xpdGain; | ||
| 3801 | |||
| 3802 | if ((pEepData->baseEepHeader. | ||
| 3803 | version & AR5416_EEP_VER_MINOR_MASK) >= | ||
| 3804 | AR5416_EEP_MINOR_VER_2) { | ||
| 3805 | pdGainOverlap_t2 = | ||
| 3806 | pEepData->modalHeader[modalIdx].pdGainOverlap; | ||
| 3807 | } else { | ||
| 3808 | pdGainOverlap_t2 = | ||
| 3809 | (u16) (MS | ||
| 3810 | (REG_READ(ah, AR_PHY_TPCRG5), | ||
| 3811 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | ||
| 3812 | } | ||
| 3813 | |||
| 3814 | if (IS_CHAN_2GHZ(chan)) { | ||
| 3815 | pCalBChans = pEepData->calFreqPier2G; | ||
| 3816 | numPiers = AR5416_NUM_2G_CAL_PIERS; | ||
| 3817 | } else { | ||
| 3818 | pCalBChans = pEepData->calFreqPier5G; | ||
| 3819 | numPiers = AR5416_NUM_5G_CAL_PIERS; | ||
| 3820 | } | ||
| 3821 | |||
| 3822 | numXpdGain = 0; | ||
| 3823 | |||
| 3824 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { | ||
| 3825 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | ||
| 3826 | if (numXpdGain >= AR5416_NUM_PD_GAINS) | ||
| 3827 | break; | ||
| 3828 | xpdGainValues[numXpdGain] = | ||
| 3829 | (u16) (AR5416_PD_GAINS_IN_MASK - i); | ||
| 3830 | numXpdGain++; | ||
| 3831 | } | ||
| 3832 | } | ||
| 3833 | |||
| 3834 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | ||
| 3835 | (numXpdGain - 1) & 0x3); | ||
| 3836 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | ||
| 3837 | xpdGainValues[0]); | ||
| 3838 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | ||
| 3839 | xpdGainValues[1]); | ||
| 3840 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, | ||
| 3841 | xpdGainValues[2]); | ||
| 3842 | |||
| 3843 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 3844 | if (AR_SREV_5416_V20_OR_LATER(ah) && | ||
| 3845 | (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) | ||
| 3846 | && (i != 0)) { | ||
| 3847 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | ||
| 3848 | } else | ||
| 3849 | regChainOffset = i * 0x1000; | ||
| 3850 | if (pEepData->baseEepHeader.txMask & (1 << i)) { | ||
| 3851 | if (IS_CHAN_2GHZ(chan)) | ||
| 3852 | pRawDataset = pEepData->calPierData2G[i]; | ||
| 3853 | else | ||
| 3854 | pRawDataset = pEepData->calPierData5G[i]; | ||
| 3855 | |||
| 3856 | ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, | ||
| 3857 | pRawDataset, | ||
| 3858 | pCalBChans, | ||
| 3859 | numPiers, | ||
| 3860 | pdGainOverlap_t2, | ||
| 3861 | &tMinCalPower, | ||
| 3862 | gainBoundaries, | ||
| 3863 | pdadcValues, | ||
| 3864 | numXpdGain); | ||
| 3865 | |||
| 3866 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { | ||
| 3867 | |||
| 3868 | REG_WRITE(ah, | ||
| 3869 | AR_PHY_TPCRG5 + regChainOffset, | ||
| 3870 | SM(pdGainOverlap_t2, | ||
| 3871 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | ||
| 3872 | | SM(gainBoundaries[0], | ||
| 3873 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | ||
| 3874 | | SM(gainBoundaries[1], | ||
| 3875 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | ||
| 3876 | | SM(gainBoundaries[2], | ||
| 3877 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | ||
| 3878 | | SM(gainBoundaries[3], | ||
| 3879 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | ||
| 3880 | } | ||
| 3881 | |||
| 3882 | regOffset = | ||
| 3883 | AR_PHY_BASE + (672 << 2) + regChainOffset; | ||
| 3884 | for (j = 0; j < 32; j++) { | ||
| 3885 | reg32 = | ||
| 3886 | ((pdadcValues[4 * j + 0] & 0xFF) << 0) | ||
| 3887 | | ((pdadcValues[4 * j + 1] & 0xFF) << | ||
| 3888 | 8) | ((pdadcValues[4 * j + 2] & | ||
| 3889 | 0xFF) << 16) | | ||
| 3890 | ((pdadcValues[4 * j + 3] & 0xFF) << | ||
| 3891 | 24); | ||
| 3892 | REG_WRITE(ah, regOffset, reg32); | ||
| 3893 | |||
| 3894 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | ||
| 3895 | "PDADC (%d,%4x): %4.4x %8.8x\n", | ||
| 3896 | i, regChainOffset, regOffset, | ||
| 3897 | reg32); | ||
| 3898 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | ||
| 3899 | "PDADC: Chain %d | PDADC %3d Value %3d | " | ||
| 3900 | "PDADC %3d Value %3d | PDADC %3d Value %3d | " | ||
| 3901 | "PDADC %3d Value %3d |\n", | ||
| 3902 | i, 4 * j, pdadcValues[4 * j], | ||
| 3903 | 4 * j + 1, pdadcValues[4 * j + 1], | ||
| 3904 | 4 * j + 2, pdadcValues[4 * j + 2], | ||
| 3905 | 4 * j + 3, | ||
| 3906 | pdadcValues[4 * j + 3]); | ||
| 3907 | |||
| 3908 | regOffset += 4; | ||
| 3909 | } | ||
| 3910 | } | ||
| 3911 | } | ||
| 3912 | *pTxPowerIndexOffset = 0; | ||
| 3913 | |||
| 3914 | return true; | ||
| 3915 | } | ||
| 3916 | |||
| 3917 | void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) | ||
| 3918 | { | ||
| 3919 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 3920 | u8 i; | ||
| 3921 | |||
| 3922 | if (ah->ah_isPciExpress != true) | ||
| 3923 | return; | ||
| 3924 | |||
| 3925 | if (ah->ah_config.pcie_powersave_enable == 2) | ||
| 3926 | return; | ||
| 3927 | |||
| 3928 | if (restore) | ||
| 3929 | return; | ||
| 3930 | |||
| 3931 | if (AR_SREV_9280_20_OR_LATER(ah)) { | ||
| 3932 | for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { | ||
| 3933 | REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), | ||
| 3934 | INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); | ||
| 3935 | } | ||
| 3936 | udelay(1000); | ||
| 3937 | } else if (AR_SREV_9280(ah) | ||
| 3938 | && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) { | ||
| 3939 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); | ||
| 3940 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | ||
| 3941 | |||
| 3942 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); | ||
| 3943 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | ||
| 3944 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | ||
| 3945 | |||
| 3946 | if (ah->ah_config.pcie_clock_req) | ||
| 3947 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); | ||
| 3948 | else | ||
| 3949 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | ||
| 3950 | |||
| 3951 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | ||
| 3952 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | ||
| 3953 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); | ||
| 3954 | |||
| 3955 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | ||
| 3956 | |||
| 3957 | udelay(1000); | ||
| 3958 | } else { | ||
| 3959 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | ||
| 3960 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | ||
| 3961 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); | ||
| 3962 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | ||
| 3963 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | ||
| 3964 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); | ||
| 3965 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | ||
| 3966 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | ||
| 3967 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); | ||
| 3968 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | ||
| 3969 | } | ||
| 3970 | |||
| 3971 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); | ||
| 3972 | |||
| 3973 | if (ah->ah_config.pcie_waen) { | ||
| 3974 | REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); | ||
| 3975 | } else { | ||
| 3976 | if (AR_SREV_9280(ah)) | ||
| 3977 | REG_WRITE(ah, AR_WA, 0x0040073f); | ||
| 3978 | else | ||
| 3979 | REG_WRITE(ah, AR_WA, 0x0000073f); | ||
| 3980 | } | ||
| 3981 | } | ||
| 3982 | |||
| 3983 | static inline void | ||
| 3984 | ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, | ||
| 3985 | struct ath9k_channel *chan, | ||
| 3986 | struct cal_target_power_leg *powInfo, | ||
| 3987 | u16 numChannels, | ||
| 3988 | struct cal_target_power_leg *pNewPower, | ||
| 3989 | u16 numRates, | ||
| 3990 | bool isExtTarget) | ||
| 3991 | { | ||
| 3992 | u16 clo, chi; | ||
| 3993 | int i; | ||
| 3994 | int matchIndex = -1, lowIndex = -1; | ||
| 3995 | u16 freq; | ||
| 3996 | struct chan_centers centers; | ||
| 3997 | |||
| 3998 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 3999 | freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; | ||
| 4000 | |||
| 4001 | if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, | ||
| 4002 | IS_CHAN_2GHZ(chan))) { | ||
| 4003 | matchIndex = 0; | ||
| 4004 | } else { | ||
| 4005 | for (i = 0; (i < numChannels) | ||
| 4006 | && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | ||
| 4007 | if (freq == | ||
| 4008 | ath9k_hw_fbin2freq(powInfo[i].bChannel, | ||
| 4009 | IS_CHAN_2GHZ(chan))) { | ||
| 4010 | matchIndex = i; | ||
| 4011 | break; | ||
| 4012 | } else if ((freq < | ||
| 4013 | ath9k_hw_fbin2freq(powInfo[i].bChannel, | ||
| 4014 | IS_CHAN_2GHZ(chan))) | ||
| 4015 | && (freq > | ||
| 4016 | ath9k_hw_fbin2freq(powInfo[i - 1]. | ||
| 4017 | bChannel, | ||
| 4018 | IS_CHAN_2GHZ | ||
| 4019 | (chan)))) { | ||
| 4020 | lowIndex = i - 1; | ||
| 4021 | break; | ||
| 4022 | } | ||
| 4023 | } | ||
| 4024 | if ((matchIndex == -1) && (lowIndex == -1)) | ||
| 4025 | matchIndex = i - 1; | ||
| 4026 | } | ||
| 4027 | |||
| 4028 | if (matchIndex != -1) { | ||
| 4029 | *pNewPower = powInfo[matchIndex]; | ||
| 4030 | } else { | ||
| 4031 | clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, | ||
| 4032 | IS_CHAN_2GHZ(chan)); | ||
| 4033 | chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, | ||
| 4034 | IS_CHAN_2GHZ(chan)); | ||
| 4035 | |||
| 4036 | for (i = 0; i < numRates; i++) { | ||
| 4037 | pNewPower->tPow2x[i] = | ||
| 4038 | (u8) ath9k_hw_interpolate(freq, clo, chi, | ||
| 4039 | powInfo | ||
| 4040 | [lowIndex]. | ||
| 4041 | tPow2x[i], | ||
| 4042 | powInfo | ||
| 4043 | [lowIndex + | ||
| 4044 | 1].tPow2x[i]); | ||
| 4045 | } | ||
| 4046 | } | ||
| 4047 | } | ||
| 4048 | |||
| 4049 | static inline void | ||
| 4050 | ath9k_hw_get_target_powers(struct ath_hal *ah, | ||
| 4051 | struct ath9k_channel *chan, | ||
| 4052 | struct cal_target_power_ht *powInfo, | ||
| 4053 | u16 numChannels, | ||
| 4054 | struct cal_target_power_ht *pNewPower, | ||
| 4055 | u16 numRates, | ||
| 4056 | bool isHt40Target) | ||
| 4057 | { | ||
| 4058 | u16 clo, chi; | ||
| 4059 | int i; | ||
| 4060 | int matchIndex = -1, lowIndex = -1; | ||
| 4061 | u16 freq; | ||
| 4062 | struct chan_centers centers; | ||
| 4063 | |||
| 4064 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 4065 | freq = isHt40Target ? centers.synth_center : centers.ctl_center; | ||
| 4066 | |||
| 4067 | if (freq <= | ||
| 4068 | ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { | ||
| 4069 | matchIndex = 0; | ||
| 4070 | } else { | ||
| 4071 | for (i = 0; (i < numChannels) | ||
| 4072 | && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | ||
| 4073 | if (freq == | ||
| 4074 | ath9k_hw_fbin2freq(powInfo[i].bChannel, | ||
| 4075 | IS_CHAN_2GHZ(chan))) { | ||
| 4076 | matchIndex = i; | ||
| 4077 | break; | ||
| 4078 | } else | ||
| 4079 | if ((freq < | ||
| 4080 | ath9k_hw_fbin2freq(powInfo[i].bChannel, | ||
| 4081 | IS_CHAN_2GHZ(chan))) | ||
| 4082 | && (freq > | ||
| 4083 | ath9k_hw_fbin2freq(powInfo[i - 1]. | ||
| 4084 | bChannel, | ||
| 4085 | IS_CHAN_2GHZ | ||
| 4086 | (chan)))) { | ||
| 4087 | lowIndex = i - 1; | ||
| 4088 | break; | ||
| 4089 | } | ||
| 4090 | } | ||
| 4091 | if ((matchIndex == -1) && (lowIndex == -1)) | ||
| 4092 | matchIndex = i - 1; | ||
| 4093 | } | ||
| 4094 | |||
| 4095 | if (matchIndex != -1) { | ||
| 4096 | *pNewPower = powInfo[matchIndex]; | ||
| 4097 | } else { | ||
| 4098 | clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, | ||
| 4099 | IS_CHAN_2GHZ(chan)); | ||
| 4100 | chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, | ||
| 4101 | IS_CHAN_2GHZ(chan)); | ||
| 4102 | |||
| 4103 | for (i = 0; i < numRates; i++) { | ||
| 4104 | pNewPower->tPow2x[i] = | ||
| 4105 | (u8) ath9k_hw_interpolate(freq, clo, chi, | ||
| 4106 | powInfo | ||
| 4107 | [lowIndex]. | ||
| 4108 | tPow2x[i], | ||
| 4109 | powInfo | ||
| 4110 | [lowIndex + | ||
| 4111 | 1].tPow2x[i]); | ||
| 4112 | } | ||
| 4113 | } | ||
| 4114 | } | ||
| 4115 | |||
| 4116 | static inline u16 | ||
| 4117 | ath9k_hw_get_max_edge_power(u16 freq, | ||
| 4118 | struct cal_ctl_edges *pRdEdgesPower, | ||
| 4119 | bool is2GHz) | ||
| 4120 | { | ||
| 4121 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | ||
| 4122 | int i; | ||
| 4123 | |||
| 4124 | for (i = 0; (i < AR5416_NUM_BAND_EDGES) | ||
| 4125 | && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | ||
| 4126 | if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, | ||
| 4127 | is2GHz)) { | ||
| 4128 | twiceMaxEdgePower = pRdEdgesPower[i].tPower; | ||
| 4129 | break; | ||
| 4130 | } else if ((i > 0) | ||
| 4131 | && (freq < | ||
| 4132 | ath9k_hw_fbin2freq(pRdEdgesPower[i]. | ||
| 4133 | bChannel, is2GHz))) { | ||
| 4134 | if (ath9k_hw_fbin2freq | ||
| 4135 | (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq | ||
| 4136 | && pRdEdgesPower[i - 1].flag) { | ||
| 4137 | twiceMaxEdgePower = | ||
| 4138 | pRdEdgesPower[i - 1].tPower; | ||
| 4139 | } | ||
| 4140 | break; | ||
| 4141 | } | ||
| 4142 | } | ||
| 4143 | return twiceMaxEdgePower; | ||
| 4144 | } | ||
| 4145 | |||
| 4146 | static inline bool | ||
| 4147 | ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, | ||
| 4148 | struct ar5416_eeprom *pEepData, | ||
| 4149 | struct ath9k_channel *chan, | ||
| 4150 | int16_t *ratesArray, | ||
| 4151 | u16 cfgCtl, | ||
| 4152 | u8 AntennaReduction, | ||
| 4153 | u8 twiceMaxRegulatoryPower, | ||
| 4154 | u8 powerLimit) | ||
| 4155 | { | ||
| 4156 | u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | ||
| 4157 | static const u16 tpScaleReductionTable[5] = | ||
| 4158 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | ||
| 4159 | |||
| 4160 | int i; | ||
| 4161 | int8_t twiceLargestAntenna; | ||
| 4162 | struct cal_ctl_data *rep; | ||
| 4163 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { | ||
| 4164 | 0, { 0, 0, 0, 0} | ||
| 4165 | }; | ||
| 4166 | struct cal_target_power_leg targetPowerOfdmExt = { | ||
| 4167 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | ||
| 4168 | 0, { 0, 0, 0, 0 } | ||
| 4169 | }; | ||
| 4170 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | ||
| 4171 | 0, {0, 0, 0, 0} | ||
| 4172 | }; | ||
| 4173 | u8 scaledPower = 0, minCtlPower, maxRegAllowedPower; | ||
| 4174 | u16 ctlModesFor11a[] = | ||
| 4175 | { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; | ||
| 4176 | u16 ctlModesFor11g[] = | ||
| 4177 | { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, | ||
| 4178 | CTL_2GHT40 | ||
| 4179 | }; | ||
| 4180 | u16 numCtlModes, *pCtlMode, ctlMode, freq; | ||
| 4181 | struct chan_centers centers; | ||
| 4182 | int tx_chainmask; | ||
| 4183 | u8 twiceMinEdgePower; | ||
| 4184 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 4185 | |||
| 4186 | tx_chainmask = ahp->ah_txchainmask; | ||
| 4187 | |||
| 4188 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 4189 | |||
| 4190 | twiceLargestAntenna = max( | ||
| 4191 | pEepData->modalHeader | ||
| 4192 | [IS_CHAN_2GHZ(chan)].antennaGainCh[0], | ||
| 4193 | pEepData->modalHeader | ||
| 4194 | [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); | ||
| 4195 | |||
| 4196 | twiceLargestAntenna = max((u8) twiceLargestAntenna, | ||
| 4197 | pEepData->modalHeader | ||
| 4198 | [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); | ||
| 4199 | |||
| 4200 | twiceLargestAntenna = | ||
| 4201 | (int8_t) min(AntennaReduction - twiceLargestAntenna, 0); | ||
| 4202 | |||
| 4203 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | ||
| 4204 | |||
| 4205 | if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { | ||
| 4206 | maxRegAllowedPower -= | ||
| 4207 | (tpScaleReductionTable[(ah->ah_tpScale)] * 2); | ||
| 4208 | } | ||
| 4209 | |||
| 4210 | scaledPower = min(powerLimit, maxRegAllowedPower); | ||
| 4211 | |||
| 4212 | switch (ar5416_get_ntxchains(tx_chainmask)) { | ||
| 4213 | case 1: | ||
| 4214 | break; | ||
| 4215 | case 2: | ||
| 4216 | scaledPower -= | ||
| 4217 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)]. | ||
| 4218 | pwrDecreaseFor2Chain; | ||
| 4219 | break; | ||
| 4220 | case 3: | ||
| 4221 | scaledPower -= | ||
| 4222 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)]. | ||
| 4223 | pwrDecreaseFor3Chain; | ||
| 4224 | break; | ||
| 4225 | } | ||
| 4226 | |||
| 4227 | scaledPower = max(0, (int32_t) scaledPower); | ||
| 4228 | |||
| 4229 | if (IS_CHAN_2GHZ(chan)) { | ||
| 4230 | numCtlModes = | ||
| 4231 | ARRAY_SIZE(ctlModesFor11g) - | ||
| 4232 | SUB_NUM_CTL_MODES_AT_2G_40; | ||
| 4233 | pCtlMode = ctlModesFor11g; | ||
| 4234 | |||
| 4235 | ath9k_hw_get_legacy_target_powers(ah, chan, | ||
| 4236 | pEepData-> | ||
| 4237 | calTargetPowerCck, | ||
| 4238 | AR5416_NUM_2G_CCK_TARGET_POWERS, | ||
| 4239 | &targetPowerCck, 4, | ||
| 4240 | false); | ||
| 4241 | ath9k_hw_get_legacy_target_powers(ah, chan, | ||
| 4242 | pEepData-> | ||
| 4243 | calTargetPower2G, | ||
| 4244 | AR5416_NUM_2G_20_TARGET_POWERS, | ||
| 4245 | &targetPowerOfdm, 4, | ||
| 4246 | false); | ||
| 4247 | ath9k_hw_get_target_powers(ah, chan, | ||
| 4248 | pEepData->calTargetPower2GHT20, | ||
| 4249 | AR5416_NUM_2G_20_TARGET_POWERS, | ||
| 4250 | &targetPowerHt20, 8, false); | ||
| 4251 | |||
| 4252 | if (IS_CHAN_HT40(chan)) { | ||
| 4253 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | ||
| 4254 | ath9k_hw_get_target_powers(ah, chan, | ||
| 4255 | pEepData-> | ||
| 4256 | calTargetPower2GHT40, | ||
| 4257 | AR5416_NUM_2G_40_TARGET_POWERS, | ||
| 4258 | &targetPowerHt40, 8, | ||
| 4259 | true); | ||
| 4260 | ath9k_hw_get_legacy_target_powers(ah, chan, | ||
| 4261 | pEepData-> | ||
| 4262 | calTargetPowerCck, | ||
| 4263 | AR5416_NUM_2G_CCK_TARGET_POWERS, | ||
| 4264 | &targetPowerCckExt, | ||
| 4265 | 4, true); | ||
| 4266 | ath9k_hw_get_legacy_target_powers(ah, chan, | ||
| 4267 | pEepData-> | ||
| 4268 | calTargetPower2G, | ||
| 4269 | AR5416_NUM_2G_20_TARGET_POWERS, | ||
| 4270 | &targetPowerOfdmExt, | ||
| 4271 | 4, true); | ||
| 4272 | } | ||
| 4273 | } else { | ||
| 4274 | |||
| 4275 | numCtlModes = | ||
| 4276 | ARRAY_SIZE(ctlModesFor11a) - | ||
| 4277 | SUB_NUM_CTL_MODES_AT_5G_40; | ||
| 4278 | pCtlMode = ctlModesFor11a; | ||
| 4279 | |||
| 4280 | ath9k_hw_get_legacy_target_powers(ah, chan, | ||
| 4281 | pEepData-> | ||
| 4282 | calTargetPower5G, | ||
| 4283 | AR5416_NUM_5G_20_TARGET_POWERS, | ||
| 4284 | &targetPowerOfdm, 4, | ||
| 4285 | false); | ||
| 4286 | ath9k_hw_get_target_powers(ah, chan, | ||
| 4287 | pEepData->calTargetPower5GHT20, | ||
| 4288 | AR5416_NUM_5G_20_TARGET_POWERS, | ||
| 4289 | &targetPowerHt20, 8, false); | ||
| 4290 | |||
| 4291 | if (IS_CHAN_HT40(chan)) { | ||
| 4292 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); | ||
| 4293 | ath9k_hw_get_target_powers(ah, chan, | ||
| 4294 | pEepData-> | ||
| 4295 | calTargetPower5GHT40, | ||
| 4296 | AR5416_NUM_5G_40_TARGET_POWERS, | ||
| 4297 | &targetPowerHt40, 8, | ||
| 4298 | true); | ||
| 4299 | ath9k_hw_get_legacy_target_powers(ah, chan, | ||
| 4300 | pEepData-> | ||
| 4301 | calTargetPower5G, | ||
| 4302 | AR5416_NUM_5G_20_TARGET_POWERS, | ||
| 4303 | &targetPowerOfdmExt, | ||
| 4304 | 4, true); | ||
| 4305 | } | ||
| 4306 | } | ||
| 4307 | |||
| 4308 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | ||
| 4309 | bool isHt40CtlMode = | ||
| 4310 | (pCtlMode[ctlMode] == CTL_5GHT40) | ||
| 4311 | || (pCtlMode[ctlMode] == CTL_2GHT40); | ||
| 4312 | if (isHt40CtlMode) | ||
| 4313 | freq = centers.synth_center; | ||
| 4314 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | ||
| 4315 | freq = centers.ext_center; | ||
| 4316 | else | ||
| 4317 | freq = centers.ctl_center; | ||
| 4318 | |||
| 4319 | if (ar5416_get_eep_ver(ahp) == 14 | ||
| 4320 | && ar5416_get_eep_rev(ahp) <= 2) | ||
| 4321 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | ||
| 4322 | |||
| 4323 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 4324 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " | ||
| 4325 | "EXT_ADDITIVE %d\n", | ||
| 4326 | ctlMode, numCtlModes, isHt40CtlMode, | ||
| 4327 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | ||
| 4328 | |||
| 4329 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; | ||
| 4330 | i++) { | ||
| 4331 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 4332 | " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " | ||
| 4333 | "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " | ||
| 4334 | "chan %d\n", | ||
| 4335 | i, cfgCtl, pCtlMode[ctlMode], | ||
| 4336 | pEepData->ctlIndex[i], chan->channel); | ||
| 4337 | |||
| 4338 | if ((((cfgCtl & ~CTL_MODE_M) | | ||
| 4339 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | ||
| 4340 | pEepData->ctlIndex[i]) | ||
| 4341 | || | ||
| 4342 | (((cfgCtl & ~CTL_MODE_M) | | ||
| 4343 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | ||
| 4344 | ((pEepData-> | ||
| 4345 | ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { | ||
| 4346 | rep = &(pEepData->ctlData[i]); | ||
| 4347 | |||
| 4348 | twiceMinEdgePower = | ||
| 4349 | ath9k_hw_get_max_edge_power(freq, | ||
| 4350 | rep-> | ||
| 4351 | ctlEdges | ||
| 4352 | [ar5416_get_ntxchains | ||
| 4353 | (tx_chainmask) | ||
| 4354 | - 1], | ||
| 4355 | IS_CHAN_2GHZ | ||
| 4356 | (chan)); | ||
| 4357 | |||
| 4358 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 4359 | " MATCH-EE_IDX %d: ch %d is2 %d " | ||
| 4360 | "2xMinEdge %d chainmask %d chains %d\n", | ||
| 4361 | i, freq, IS_CHAN_2GHZ(chan), | ||
| 4362 | twiceMinEdgePower, tx_chainmask, | ||
| 4363 | ar5416_get_ntxchains | ||
| 4364 | (tx_chainmask)); | ||
| 4365 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | ||
| 4366 | twiceMaxEdgePower = | ||
| 4367 | min(twiceMaxEdgePower, | ||
| 4368 | twiceMinEdgePower); | ||
| 4369 | } else { | ||
| 4370 | twiceMaxEdgePower = | ||
| 4371 | twiceMinEdgePower; | ||
| 4372 | break; | ||
| 4373 | } | ||
| 4374 | } | ||
| 4375 | } | ||
| 4376 | |||
| 4377 | minCtlPower = min(twiceMaxEdgePower, scaledPower); | ||
| 4378 | |||
| 4379 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 4380 | " SEL-Min ctlMode %d pCtlMode %d " | ||
| 4381 | "2xMaxEdge %d sP %d minCtlPwr %d\n", | ||
| 4382 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | ||
| 4383 | scaledPower, minCtlPower); | ||
| 4384 | |||
| 4385 | switch (pCtlMode[ctlMode]) { | ||
| 4386 | case CTL_11B: | ||
| 4387 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); | ||
| 4388 | i++) { | ||
| 4389 | targetPowerCck.tPow2x[i] = | ||
| 4390 | min(targetPowerCck.tPow2x[i], | ||
| 4391 | minCtlPower); | ||
| 4392 | } | ||
| 4393 | break; | ||
| 4394 | case CTL_11A: | ||
| 4395 | case CTL_11G: | ||
| 4396 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); | ||
| 4397 | i++) { | ||
| 4398 | targetPowerOfdm.tPow2x[i] = | ||
| 4399 | min(targetPowerOfdm.tPow2x[i], | ||
| 4400 | minCtlPower); | ||
| 4401 | } | ||
| 4402 | break; | ||
| 4403 | case CTL_5GHT20: | ||
| 4404 | case CTL_2GHT20: | ||
| 4405 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); | ||
| 4406 | i++) { | ||
| 4407 | targetPowerHt20.tPow2x[i] = | ||
| 4408 | min(targetPowerHt20.tPow2x[i], | ||
| 4409 | minCtlPower); | ||
| 4410 | } | ||
| 4411 | break; | ||
| 4412 | case CTL_11B_EXT: | ||
| 4413 | targetPowerCckExt.tPow2x[0] = | ||
| 4414 | min(targetPowerCckExt.tPow2x[0], minCtlPower); | ||
| 4415 | break; | ||
| 4416 | case CTL_11A_EXT: | ||
| 4417 | case CTL_11G_EXT: | ||
| 4418 | targetPowerOfdmExt.tPow2x[0] = | ||
| 4419 | min(targetPowerOfdmExt.tPow2x[0], minCtlPower); | ||
| 4420 | break; | ||
| 4421 | case CTL_5GHT40: | ||
| 4422 | case CTL_2GHT40: | ||
| 4423 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); | ||
| 4424 | i++) { | ||
| 4425 | targetPowerHt40.tPow2x[i] = | ||
| 4426 | min(targetPowerHt40.tPow2x[i], | ||
| 4427 | minCtlPower); | ||
| 4428 | } | ||
| 4429 | break; | ||
| 4430 | default: | ||
| 4431 | break; | ||
| 4432 | } | ||
| 4433 | } | ||
| 4434 | |||
| 4435 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = | ||
| 4436 | ratesArray[rate18mb] = ratesArray[rate24mb] = | ||
| 4437 | targetPowerOfdm.tPow2x[0]; | ||
| 4438 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; | ||
| 4439 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | ||
| 4440 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | ||
| 4441 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | ||
| 4442 | |||
| 4443 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | ||
| 4444 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | ||
| 4445 | |||
| 4446 | if (IS_CHAN_2GHZ(chan)) { | ||
| 4447 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | ||
| 4448 | ratesArray[rate2s] = ratesArray[rate2l] = | ||
| 4449 | targetPowerCck.tPow2x[1]; | ||
| 4450 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = | ||
| 4451 | targetPowerCck.tPow2x[2]; | ||
| 4452 | ; | ||
| 4453 | ratesArray[rate11s] = ratesArray[rate11l] = | ||
| 4454 | targetPowerCck.tPow2x[3]; | ||
| 4455 | ; | ||
| 4456 | } | ||
| 4457 | if (IS_CHAN_HT40(chan)) { | ||
| 4458 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | ||
| 4459 | ratesArray[rateHt40_0 + i] = | ||
| 4460 | targetPowerHt40.tPow2x[i]; | ||
| 4461 | } | ||
| 4462 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | ||
| 4463 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | ||
| 4464 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | ||
| 4465 | if (IS_CHAN_2GHZ(chan)) { | ||
| 4466 | ratesArray[rateExtCck] = | ||
| 4467 | targetPowerCckExt.tPow2x[0]; | ||
| 4468 | } | ||
| 4469 | } | ||
| 4470 | return true; | ||
| 4471 | } | ||
| 4472 | |||
| 4473 | static int | ||
| 4474 | ath9k_hw_set_txpower(struct ath_hal *ah, | ||
| 4475 | struct ar5416_eeprom *pEepData, | ||
| 4476 | struct ath9k_channel *chan, | ||
| 4477 | u16 cfgCtl, | ||
| 4478 | u8 twiceAntennaReduction, | ||
| 4479 | u8 twiceMaxRegulatoryPower, | ||
| 4480 | u8 powerLimit) | ||
| 4481 | { | ||
| 4482 | struct modal_eep_header *pModal = | ||
| 4483 | &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); | ||
| 4484 | int16_t ratesArray[Ar5416RateSize]; | ||
| 4485 | int16_t txPowerIndexOffset = 0; | ||
| 4486 | u8 ht40PowerIncForPdadc = 2; | ||
| 4487 | int i; | ||
| 4488 | |||
| 4489 | memset(ratesArray, 0, sizeof(ratesArray)); | ||
| 4490 | |||
| 4491 | if ((pEepData->baseEepHeader. | ||
| 4492 | version & AR5416_EEP_VER_MINOR_MASK) >= | ||
| 4493 | AR5416_EEP_MINOR_VER_2) { | ||
| 4494 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | ||
| 4495 | } | ||
| 4496 | |||
| 4497 | if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan, | ||
| 4498 | &ratesArray[0], cfgCtl, | ||
| 4499 | twiceAntennaReduction, | ||
| 4500 | twiceMaxRegulatoryPower, | ||
| 4501 | powerLimit)) { | ||
| 4502 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 4503 | "ath9k_hw_set_txpower: unable to set " | ||
| 4504 | "tx power per rate table\n"); | ||
| 4505 | return -EIO; | ||
| 4506 | } | ||
| 4507 | |||
| 4508 | if (!ath9k_hw_set_power_cal_table | ||
| 4509 | (ah, pEepData, chan, &txPowerIndexOffset)) { | ||
| 4510 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 4511 | "ath9k_hw_set_txpower: unable to set power table\n"); | ||
| 4512 | return -EIO; | ||
| 4513 | } | ||
| 4514 | |||
| 4515 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | ||
| 4516 | ratesArray[i] = | ||
| 4517 | (int16_t) (txPowerIndexOffset + ratesArray[i]); | ||
| 4518 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | ||
| 4519 | ratesArray[i] = AR5416_MAX_RATE_POWER; | ||
| 4520 | } | ||
| 4521 | |||
| 4522 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 4523 | for (i = 0; i < Ar5416RateSize; i++) | ||
| 4524 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; | ||
| 4525 | } | ||
| 4526 | |||
| 4527 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, | ||
| 4528 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | ||
| 4529 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | ||
| 4530 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | ||
| 4531 | | ATH9K_POW_SM(ratesArray[rate6mb], 0) | ||
| 4532 | ); | ||
| 4533 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | ||
| 4534 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | ||
| 4535 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | ||
| 4536 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | ||
| 4537 | | ATH9K_POW_SM(ratesArray[rate24mb], 0) | ||
| 4538 | ); | ||
| 4539 | |||
| 4540 | if (IS_CHAN_2GHZ(chan)) { | ||
| 4541 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | ||
| 4542 | ATH9K_POW_SM(ratesArray[rate2s], 24) | ||
| 4543 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | ||
| 4544 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | ||
| 4545 | | ATH9K_POW_SM(ratesArray[rate1l], 0) | ||
| 4546 | ); | ||
| 4547 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | ||
| 4548 | ATH9K_POW_SM(ratesArray[rate11s], 24) | ||
| 4549 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | ||
| 4550 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | ||
| 4551 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0) | ||
| 4552 | ); | ||
| 4553 | } | ||
| 4554 | |||
| 4555 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, | ||
| 4556 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | ||
| 4557 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | ||
| 4558 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | ||
| 4559 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0) | ||
| 4560 | ); | ||
| 4561 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | ||
| 4562 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | ||
| 4563 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | ||
| 4564 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | ||
| 4565 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0) | ||
| 4566 | ); | ||
| 4567 | |||
| 4568 | if (IS_CHAN_HT40(chan)) { | ||
| 4569 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | ||
| 4570 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | ||
| 4571 | ht40PowerIncForPdadc, 24) | ||
| 4572 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | ||
| 4573 | ht40PowerIncForPdadc, 16) | ||
| 4574 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | ||
| 4575 | ht40PowerIncForPdadc, 8) | ||
| 4576 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | ||
| 4577 | ht40PowerIncForPdadc, 0) | ||
| 4578 | ); | ||
| 4579 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | ||
| 4580 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | ||
| 4581 | ht40PowerIncForPdadc, 24) | ||
| 4582 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | ||
| 4583 | ht40PowerIncForPdadc, 16) | ||
| 4584 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | ||
| 4585 | ht40PowerIncForPdadc, 8) | ||
| 4586 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | ||
| 4587 | ht40PowerIncForPdadc, 0) | ||
| 4588 | ); | ||
| 4589 | |||
| 4590 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | ||
| 4591 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | ||
| 4592 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | ||
| 4593 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | ||
| 4594 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0) | ||
| 4595 | ); | ||
| 4596 | } | ||
| 4597 | |||
| 4598 | REG_WRITE(ah, AR_PHY_POWER_TX_SUB, | ||
| 4599 | ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) | ||
| 4600 | | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0) | ||
| 4601 | ); | ||
| 4602 | |||
| 4603 | i = rate6mb; | ||
| 4604 | if (IS_CHAN_HT40(chan)) | ||
| 4605 | i = rateHt40_0; | ||
| 4606 | else if (IS_CHAN_HT20(chan)) | ||
| 4607 | i = rateHt20_0; | ||
| 4608 | |||
| 4609 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 4610 | ah->ah_maxPowerLevel = | ||
| 4611 | ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; | ||
| 4612 | else | ||
| 4613 | ah->ah_maxPowerLevel = ratesArray[i]; | ||
| 4614 | |||
| 4615 | return 0; | ||
| 4616 | } | ||
| 4617 | |||
| 4618 | static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, | ||
| 4619 | u32 coef_scaled, | ||
| 4620 | u32 *coef_mantissa, | ||
| 4621 | u32 *coef_exponent) | ||
| 4622 | { | ||
| 4623 | u32 coef_exp, coef_man; | ||
| 4624 | |||
| 4625 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | ||
| 4626 | if ((coef_scaled >> coef_exp) & 0x1) | ||
| 4627 | break; | ||
| 4628 | |||
| 4629 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | ||
| 4630 | |||
| 4631 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | ||
| 4632 | |||
| 4633 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | ||
| 4634 | *coef_exponent = coef_exp - 16; | ||
| 4635 | } | ||
| 4636 | |||
| 4637 | static void | ||
| 4638 | ath9k_hw_set_delta_slope(struct ath_hal *ah, | ||
| 4639 | struct ath9k_channel *chan) | ||
| 4640 | { | ||
| 4641 | u32 coef_scaled, ds_coef_exp, ds_coef_man; | ||
| 4642 | u32 clockMhzScaled = 0x64000000; | ||
| 4643 | struct chan_centers centers; | ||
| 4644 | |||
| 4645 | if (IS_CHAN_HALF_RATE(chan)) | ||
| 4646 | clockMhzScaled = clockMhzScaled >> 1; | ||
| 4647 | else if (IS_CHAN_QUARTER_RATE(chan)) | ||
| 4648 | clockMhzScaled = clockMhzScaled >> 2; | ||
| 4649 | |||
| 4650 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 4651 | coef_scaled = clockMhzScaled / centers.synth_center; | ||
| 4652 | |||
| 4653 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | ||
| 4654 | &ds_coef_exp); | ||
| 4655 | |||
| 4656 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | ||
| 4657 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | ||
| 4658 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | ||
| 4659 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | ||
| 4660 | |||
| 4661 | coef_scaled = (9 * coef_scaled) / 10; | ||
| 4662 | |||
| 4663 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | ||
| 4664 | &ds_coef_exp); | ||
| 4665 | |||
| 4666 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | ||
| 4667 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); | ||
| 4668 | REG_RMW_FIELD(ah, AR_PHY_HALFGI, | ||
| 4669 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); | ||
| 4670 | } | ||
| 4671 | |||
| 4672 | static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, | ||
| 4673 | struct ath9k_channel *chan) | ||
| 4674 | { | ||
| 4675 | int bb_spur = AR_NO_SPUR; | ||
| 4676 | int freq; | ||
| 4677 | int bin, cur_bin; | ||
| 4678 | int bb_spur_off, spur_subchannel_sd; | ||
| 4679 | int spur_freq_sd; | ||
| 4680 | int spur_delta_phase; | ||
| 4681 | int denominator; | ||
| 4682 | int upper, lower, cur_vit_mask; | ||
| 4683 | int tmp, newVal; | ||
| 4684 | int i; | ||
| 4685 | int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, | ||
| 4686 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | ||
| 4687 | }; | ||
| 4688 | int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, | ||
| 4689 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | ||
| 4690 | }; | ||
| 4691 | int inc[4] = { 0, 100, 0, 0 }; | ||
| 4692 | struct chan_centers centers; | ||
| 4693 | |||
| 4694 | int8_t mask_m[123]; | ||
| 4695 | int8_t mask_p[123]; | ||
| 4696 | int8_t mask_amt; | ||
| 4697 | int tmp_mask; | ||
| 4698 | int cur_bb_spur; | ||
| 4699 | bool is2GHz = IS_CHAN_2GHZ(chan); | ||
| 4700 | |||
| 4701 | memset(&mask_m, 0, sizeof(int8_t) * 123); | ||
| 4702 | memset(&mask_p, 0, sizeof(int8_t) * 123); | ||
| 4703 | |||
| 4704 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 4705 | freq = centers.synth_center; | ||
| 4706 | |||
| 4707 | ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; | ||
| 4708 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { | ||
| 4709 | cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); | ||
| 4710 | |||
| 4711 | if (is2GHz) | ||
| 4712 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; | ||
| 4713 | else | ||
| 4714 | cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; | ||
| 4715 | |||
| 4716 | if (AR_NO_SPUR == cur_bb_spur) | ||
| 4717 | break; | ||
| 4718 | cur_bb_spur = cur_bb_spur - freq; | ||
| 4719 | |||
| 4720 | if (IS_CHAN_HT40(chan)) { | ||
| 4721 | if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && | ||
| 4722 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { | ||
| 4723 | bb_spur = cur_bb_spur; | ||
| 4724 | break; | ||
| 4725 | } | ||
| 4726 | } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && | ||
| 4727 | (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { | ||
| 4728 | bb_spur = cur_bb_spur; | ||
| 4729 | break; | ||
| 4730 | } | ||
| 4731 | } | ||
| 4732 | |||
| 4733 | if (AR_NO_SPUR == bb_spur) { | ||
| 4734 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, | ||
| 4735 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); | ||
| 4736 | return; | ||
| 4737 | } else { | ||
| 4738 | REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, | ||
| 4739 | AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); | ||
| 4740 | } | ||
| 4741 | |||
| 4742 | bin = bb_spur * 320; | ||
| 4743 | |||
| 4744 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); | ||
| 4745 | |||
| 4746 | newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | ||
| 4747 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | ||
| 4748 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | ||
| 4749 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | ||
| 4750 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); | ||
| 4751 | |||
| 4752 | newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | | ||
| 4753 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | ||
| 4754 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | ||
| 4755 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | ||
| 4756 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | ||
| 4757 | REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); | ||
| 4758 | |||
| 4759 | if (IS_CHAN_HT40(chan)) { | ||
| 4760 | if (bb_spur < 0) { | ||
| 4761 | spur_subchannel_sd = 1; | ||
| 4762 | bb_spur_off = bb_spur + 10; | ||
| 4763 | } else { | ||
| 4764 | spur_subchannel_sd = 0; | ||
| 4765 | bb_spur_off = bb_spur - 10; | ||
| 4766 | } | ||
| 4767 | } else { | ||
| 4768 | spur_subchannel_sd = 0; | ||
| 4769 | bb_spur_off = bb_spur; | ||
| 4770 | } | ||
| 4771 | |||
| 4772 | if (IS_CHAN_HT40(chan)) | ||
| 4773 | spur_delta_phase = | ||
| 4774 | ((bb_spur * 262144) / | ||
| 4775 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; | ||
| 4776 | else | ||
| 4777 | spur_delta_phase = | ||
| 4778 | ((bb_spur * 524288) / | ||
| 4779 | 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; | ||
| 4780 | |||
| 4781 | denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; | ||
| 4782 | spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; | ||
| 4783 | |||
| 4784 | newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | | ||
| 4785 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | ||
| 4786 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | ||
| 4787 | REG_WRITE(ah, AR_PHY_TIMING11, newVal); | ||
| 4788 | |||
| 4789 | newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; | ||
| 4790 | REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); | ||
| 4791 | |||
| 4792 | cur_bin = -6000; | ||
| 4793 | upper = bin + 100; | ||
| 4794 | lower = bin - 100; | ||
| 4795 | |||
| 4796 | for (i = 0; i < 4; i++) { | ||
| 4797 | int pilot_mask = 0; | ||
| 4798 | int chan_mask = 0; | ||
| 4799 | int bp = 0; | ||
| 4800 | for (bp = 0; bp < 30; bp++) { | ||
| 4801 | if ((cur_bin > lower) && (cur_bin < upper)) { | ||
| 4802 | pilot_mask = pilot_mask | 0x1 << bp; | ||
| 4803 | chan_mask = chan_mask | 0x1 << bp; | ||
| 4804 | } | ||
| 4805 | cur_bin += 100; | ||
| 4806 | } | ||
| 4807 | cur_bin += inc[i]; | ||
| 4808 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | ||
| 4809 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | ||
| 4810 | } | ||
| 4811 | |||
| 4812 | cur_vit_mask = 6100; | ||
| 4813 | upper = bin + 120; | ||
| 4814 | lower = bin - 120; | ||
| 4815 | |||
| 4816 | for (i = 0; i < 123; i++) { | ||
| 4817 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | ||
| 4818 | |||
| 4819 | /* workaround for gcc bug #37014 */ | ||
| 4820 | volatile int tmp = abs(cur_vit_mask - bin); | ||
| 4821 | |||
| 4822 | if (tmp < 75) | ||
| 4823 | mask_amt = 1; | ||
| 4824 | else | ||
| 4825 | mask_amt = 0; | ||
| 4826 | if (cur_vit_mask < 0) | ||
| 4827 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | ||
| 4828 | else | ||
| 4829 | mask_p[cur_vit_mask / 100] = mask_amt; | ||
| 4830 | } | ||
| 4831 | cur_vit_mask -= 100; | ||
| 4832 | } | ||
| 4833 | |||
| 4834 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | ||
| 4835 | | (mask_m[48] << 26) | (mask_m[49] << 24) | ||
| 4836 | | (mask_m[50] << 22) | (mask_m[51] << 20) | ||
| 4837 | | (mask_m[52] << 18) | (mask_m[53] << 16) | ||
| 4838 | | (mask_m[54] << 14) | (mask_m[55] << 12) | ||
| 4839 | | (mask_m[56] << 10) | (mask_m[57] << 8) | ||
| 4840 | | (mask_m[58] << 6) | (mask_m[59] << 4) | ||
| 4841 | | (mask_m[60] << 2) | (mask_m[61] << 0); | ||
| 4842 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | ||
| 4843 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | ||
| 4844 | |||
| 4845 | tmp_mask = (mask_m[31] << 28) | ||
| 4846 | | (mask_m[32] << 26) | (mask_m[33] << 24) | ||
| 4847 | | (mask_m[34] << 22) | (mask_m[35] << 20) | ||
| 4848 | | (mask_m[36] << 18) | (mask_m[37] << 16) | ||
| 4849 | | (mask_m[48] << 14) | (mask_m[39] << 12) | ||
| 4850 | | (mask_m[40] << 10) | (mask_m[41] << 8) | ||
| 4851 | | (mask_m[42] << 6) | (mask_m[43] << 4) | ||
| 4852 | | (mask_m[44] << 2) | (mask_m[45] << 0); | ||
| 4853 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | ||
| 4854 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | ||
| 4855 | |||
| 4856 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | ||
| 4857 | | (mask_m[18] << 26) | (mask_m[18] << 24) | ||
| 4858 | | (mask_m[20] << 22) | (mask_m[20] << 20) | ||
| 4859 | | (mask_m[22] << 18) | (mask_m[22] << 16) | ||
| 4860 | | (mask_m[24] << 14) | (mask_m[24] << 12) | ||
| 4861 | | (mask_m[25] << 10) | (mask_m[26] << 8) | ||
| 4862 | | (mask_m[27] << 6) | (mask_m[28] << 4) | ||
| 4863 | | (mask_m[29] << 2) | (mask_m[30] << 0); | ||
| 4864 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | ||
| 4865 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | ||
| 4866 | |||
| 4867 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | ||
| 4868 | | (mask_m[2] << 26) | (mask_m[3] << 24) | ||
| 4869 | | (mask_m[4] << 22) | (mask_m[5] << 20) | ||
| 4870 | | (mask_m[6] << 18) | (mask_m[7] << 16) | ||
| 4871 | | (mask_m[8] << 14) | (mask_m[9] << 12) | ||
| 4872 | | (mask_m[10] << 10) | (mask_m[11] << 8) | ||
| 4873 | | (mask_m[12] << 6) | (mask_m[13] << 4) | ||
| 4874 | | (mask_m[14] << 2) | (mask_m[15] << 0); | ||
| 4875 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | ||
| 4876 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | ||
| 4877 | |||
| 4878 | tmp_mask = (mask_p[15] << 28) | ||
| 4879 | | (mask_p[14] << 26) | (mask_p[13] << 24) | ||
| 4880 | | (mask_p[12] << 22) | (mask_p[11] << 20) | ||
| 4881 | | (mask_p[10] << 18) | (mask_p[9] << 16) | ||
| 4882 | | (mask_p[8] << 14) | (mask_p[7] << 12) | ||
| 4883 | | (mask_p[6] << 10) | (mask_p[5] << 8) | ||
| 4884 | | (mask_p[4] << 6) | (mask_p[3] << 4) | ||
| 4885 | | (mask_p[2] << 2) | (mask_p[1] << 0); | ||
| 4886 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | ||
| 4887 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | ||
| 4888 | |||
| 4889 | tmp_mask = (mask_p[30] << 28) | ||
| 4890 | | (mask_p[29] << 26) | (mask_p[28] << 24) | ||
| 4891 | | (mask_p[27] << 22) | (mask_p[26] << 20) | ||
| 4892 | | (mask_p[25] << 18) | (mask_p[24] << 16) | ||
| 4893 | | (mask_p[23] << 14) | (mask_p[22] << 12) | ||
| 4894 | | (mask_p[21] << 10) | (mask_p[20] << 8) | ||
| 4895 | | (mask_p[19] << 6) | (mask_p[18] << 4) | ||
| 4896 | | (mask_p[17] << 2) | (mask_p[16] << 0); | ||
| 4897 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | ||
| 4898 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | ||
| 4899 | |||
| 4900 | tmp_mask = (mask_p[45] << 28) | ||
| 4901 | | (mask_p[44] << 26) | (mask_p[43] << 24) | ||
| 4902 | | (mask_p[42] << 22) | (mask_p[41] << 20) | ||
| 4903 | | (mask_p[40] << 18) | (mask_p[39] << 16) | ||
| 4904 | | (mask_p[38] << 14) | (mask_p[37] << 12) | ||
| 4905 | | (mask_p[36] << 10) | (mask_p[35] << 8) | ||
| 4906 | | (mask_p[34] << 6) | (mask_p[33] << 4) | ||
| 4907 | | (mask_p[32] << 2) | (mask_p[31] << 0); | ||
| 4908 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | ||
| 4909 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | ||
| 4910 | |||
| 4911 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) | ||
| 4912 | | (mask_p[59] << 26) | (mask_p[58] << 24) | ||
| 4913 | | (mask_p[57] << 22) | (mask_p[56] << 20) | ||
| 4914 | | (mask_p[55] << 18) | (mask_p[54] << 16) | ||
| 4915 | | (mask_p[53] << 14) | (mask_p[52] << 12) | ||
| 4916 | | (mask_p[51] << 10) | (mask_p[50] << 8) | ||
| 4917 | | (mask_p[49] << 6) | (mask_p[48] << 4) | ||
| 4918 | | (mask_p[47] << 2) | (mask_p[46] << 0); | ||
| 4919 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | ||
| 4920 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | ||
| 4921 | } | ||
| 4922 | |||
| 4923 | static void ath9k_hw_spur_mitigate(struct ath_hal *ah, | ||
| 4924 | struct ath9k_channel *chan) | ||
| 4925 | { | ||
| 4926 | int bb_spur = AR_NO_SPUR; | ||
| 4927 | int bin, cur_bin; | ||
| 4928 | int spur_freq_sd; | ||
| 4929 | int spur_delta_phase; | ||
| 4930 | int denominator; | ||
| 4931 | int upper, lower, cur_vit_mask; | ||
| 4932 | int tmp, new; | ||
| 4933 | int i; | ||
| 4934 | int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, | ||
| 4935 | AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 | ||
| 4936 | }; | ||
| 4937 | int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, | ||
| 4938 | AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 | ||
| 4939 | }; | ||
| 4940 | int inc[4] = { 0, 100, 0, 0 }; | ||
| 4941 | |||
| 4942 | int8_t mask_m[123]; | ||
| 4943 | int8_t mask_p[123]; | ||
| 4944 | int8_t mask_amt; | ||
| 4945 | int tmp_mask; | ||
| 4946 | int cur_bb_spur; | ||
| 4947 | bool is2GHz = IS_CHAN_2GHZ(chan); | ||
| 4948 | |||
| 4949 | memset(&mask_m, 0, sizeof(int8_t) * 123); | ||
| 4950 | memset(&mask_p, 0, sizeof(int8_t) * 123); | ||
| 4951 | |||
| 4952 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { | ||
| 4953 | cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); | ||
| 4954 | if (AR_NO_SPUR == cur_bb_spur) | ||
| 4955 | break; | ||
| 4956 | cur_bb_spur = cur_bb_spur - (chan->channel * 10); | ||
| 4957 | if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { | ||
| 4958 | bb_spur = cur_bb_spur; | ||
| 4959 | break; | ||
| 4960 | } | ||
| 4961 | } | ||
| 4962 | |||
| 4963 | if (AR_NO_SPUR == bb_spur) | ||
| 4964 | return; | ||
| 4965 | |||
| 4966 | bin = bb_spur * 32; | ||
| 4967 | |||
| 4968 | tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); | ||
| 4969 | new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | | ||
| 4970 | AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | | ||
| 4971 | AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | | ||
| 4972 | AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); | ||
| 4973 | |||
| 4974 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); | ||
| 4975 | |||
| 4976 | new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | | ||
| 4977 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM | | ||
| 4978 | AR_PHY_SPUR_REG_MASK_RATE_SELECT | | ||
| 4979 | AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | | ||
| 4980 | SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); | ||
| 4981 | REG_WRITE(ah, AR_PHY_SPUR_REG, new); | ||
| 4982 | |||
| 4983 | spur_delta_phase = ((bb_spur * 524288) / 100) & | ||
| 4984 | AR_PHY_TIMING11_SPUR_DELTA_PHASE; | ||
| 4985 | |||
| 4986 | denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; | ||
| 4987 | spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; | ||
| 4988 | |||
| 4989 | new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | | ||
| 4990 | SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | | ||
| 4991 | SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); | ||
| 4992 | REG_WRITE(ah, AR_PHY_TIMING11, new); | ||
| 4993 | |||
| 4994 | cur_bin = -6000; | ||
| 4995 | upper = bin + 100; | ||
| 4996 | lower = bin - 100; | ||
| 4997 | |||
| 4998 | for (i = 0; i < 4; i++) { | ||
| 4999 | int pilot_mask = 0; | ||
| 5000 | int chan_mask = 0; | ||
| 5001 | int bp = 0; | ||
| 5002 | for (bp = 0; bp < 30; bp++) { | ||
| 5003 | if ((cur_bin > lower) && (cur_bin < upper)) { | ||
| 5004 | pilot_mask = pilot_mask | 0x1 << bp; | ||
| 5005 | chan_mask = chan_mask | 0x1 << bp; | ||
| 5006 | } | ||
| 5007 | cur_bin += 100; | ||
| 5008 | } | ||
| 5009 | cur_bin += inc[i]; | ||
| 5010 | REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); | ||
| 5011 | REG_WRITE(ah, chan_mask_reg[i], chan_mask); | ||
| 5012 | } | ||
| 5013 | |||
| 5014 | cur_vit_mask = 6100; | ||
| 5015 | upper = bin + 120; | ||
| 5016 | lower = bin - 120; | ||
| 5017 | |||
| 5018 | for (i = 0; i < 123; i++) { | ||
| 5019 | if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { | ||
| 5020 | if ((abs(cur_vit_mask - bin)) < 75) | ||
| 5021 | mask_amt = 1; | ||
| 5022 | else | ||
| 5023 | mask_amt = 0; | ||
| 5024 | if (cur_vit_mask < 0) | ||
| 5025 | mask_m[abs(cur_vit_mask / 100)] = mask_amt; | ||
| 5026 | else | ||
| 5027 | mask_p[cur_vit_mask / 100] = mask_amt; | ||
| 5028 | } | ||
| 5029 | cur_vit_mask -= 100; | ||
| 5030 | } | ||
| 5031 | |||
| 5032 | tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | ||
| 5033 | | (mask_m[48] << 26) | (mask_m[49] << 24) | ||
| 5034 | | (mask_m[50] << 22) | (mask_m[51] << 20) | ||
| 5035 | | (mask_m[52] << 18) | (mask_m[53] << 16) | ||
| 5036 | | (mask_m[54] << 14) | (mask_m[55] << 12) | ||
| 5037 | | (mask_m[56] << 10) | (mask_m[57] << 8) | ||
| 5038 | | (mask_m[58] << 6) | (mask_m[59] << 4) | ||
| 5039 | | (mask_m[60] << 2) | (mask_m[61] << 0); | ||
| 5040 | REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); | ||
| 5041 | REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); | ||
| 5042 | |||
| 5043 | tmp_mask = (mask_m[31] << 28) | ||
| 5044 | | (mask_m[32] << 26) | (mask_m[33] << 24) | ||
| 5045 | | (mask_m[34] << 22) | (mask_m[35] << 20) | ||
| 5046 | | (mask_m[36] << 18) | (mask_m[37] << 16) | ||
| 5047 | | (mask_m[48] << 14) | (mask_m[39] << 12) | ||
| 5048 | | (mask_m[40] << 10) | (mask_m[41] << 8) | ||
| 5049 | | (mask_m[42] << 6) | (mask_m[43] << 4) | ||
| 5050 | | (mask_m[44] << 2) | (mask_m[45] << 0); | ||
| 5051 | REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); | ||
| 5052 | REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); | ||
| 5053 | |||
| 5054 | tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | ||
| 5055 | | (mask_m[18] << 26) | (mask_m[18] << 24) | ||
| 5056 | | (mask_m[20] << 22) | (mask_m[20] << 20) | ||
| 5057 | | (mask_m[22] << 18) | (mask_m[22] << 16) | ||
| 5058 | | (mask_m[24] << 14) | (mask_m[24] << 12) | ||
| 5059 | | (mask_m[25] << 10) | (mask_m[26] << 8) | ||
| 5060 | | (mask_m[27] << 6) | (mask_m[28] << 4) | ||
| 5061 | | (mask_m[29] << 2) | (mask_m[30] << 0); | ||
| 5062 | REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); | ||
| 5063 | REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); | ||
| 5064 | |||
| 5065 | tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | ||
| 5066 | | (mask_m[2] << 26) | (mask_m[3] << 24) | ||
| 5067 | | (mask_m[4] << 22) | (mask_m[5] << 20) | ||
| 5068 | | (mask_m[6] << 18) | (mask_m[7] << 16) | ||
| 5069 | | (mask_m[8] << 14) | (mask_m[9] << 12) | ||
| 5070 | | (mask_m[10] << 10) | (mask_m[11] << 8) | ||
| 5071 | | (mask_m[12] << 6) | (mask_m[13] << 4) | ||
| 5072 | | (mask_m[14] << 2) | (mask_m[15] << 0); | ||
| 5073 | REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); | ||
| 5074 | REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); | ||
| 5075 | |||
| 5076 | tmp_mask = (mask_p[15] << 28) | ||
| 5077 | | (mask_p[14] << 26) | (mask_p[13] << 24) | ||
| 5078 | | (mask_p[12] << 22) | (mask_p[11] << 20) | ||
| 5079 | | (mask_p[10] << 18) | (mask_p[9] << 16) | ||
| 5080 | | (mask_p[8] << 14) | (mask_p[7] << 12) | ||
| 5081 | | (mask_p[6] << 10) | (mask_p[5] << 8) | ||
| 5082 | | (mask_p[4] << 6) | (mask_p[3] << 4) | ||
| 5083 | | (mask_p[2] << 2) | (mask_p[1] << 0); | ||
| 5084 | REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); | ||
| 5085 | REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); | ||
| 5086 | |||
| 5087 | tmp_mask = (mask_p[30] << 28) | ||
| 5088 | | (mask_p[29] << 26) | (mask_p[28] << 24) | ||
| 5089 | | (mask_p[27] << 22) | (mask_p[26] << 20) | ||
| 5090 | | (mask_p[25] << 18) | (mask_p[24] << 16) | ||
| 5091 | | (mask_p[23] << 14) | (mask_p[22] << 12) | ||
| 5092 | | (mask_p[21] << 10) | (mask_p[20] << 8) | ||
| 5093 | | (mask_p[19] << 6) | (mask_p[18] << 4) | ||
| 5094 | | (mask_p[17] << 2) | (mask_p[16] << 0); | ||
| 5095 | REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); | ||
| 5096 | REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); | ||
| 5097 | |||
| 5098 | tmp_mask = (mask_p[45] << 28) | ||
| 5099 | | (mask_p[44] << 26) | (mask_p[43] << 24) | ||
| 5100 | | (mask_p[42] << 22) | (mask_p[41] << 20) | ||
| 5101 | | (mask_p[40] << 18) | (mask_p[39] << 16) | ||
| 5102 | | (mask_p[38] << 14) | (mask_p[37] << 12) | ||
| 5103 | | (mask_p[36] << 10) | (mask_p[35] << 8) | ||
| 5104 | | (mask_p[34] << 6) | (mask_p[33] << 4) | ||
| 5105 | | (mask_p[32] << 2) | (mask_p[31] << 0); | ||
| 5106 | REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); | ||
| 5107 | REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); | ||
| 5108 | |||
| 5109 | tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) | ||
| 5110 | | (mask_p[59] << 26) | (mask_p[58] << 24) | ||
| 5111 | | (mask_p[57] << 22) | (mask_p[56] << 20) | ||
| 5112 | | (mask_p[55] << 18) | (mask_p[54] << 16) | ||
| 5113 | | (mask_p[53] << 14) | (mask_p[52] << 12) | ||
| 5114 | | (mask_p[51] << 10) | (mask_p[50] << 8) | ||
| 5115 | | (mask_p[49] << 6) | (mask_p[48] << 4) | ||
| 5116 | | (mask_p[47] << 2) | (mask_p[46] << 0); | ||
| 5117 | REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); | ||
| 5118 | REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); | ||
| 5119 | } | ||
| 5120 | |||
| 5121 | static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah) | ||
| 5122 | { | ||
| 5123 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5124 | int rx_chainmask, tx_chainmask; | ||
| 5125 | |||
| 5126 | rx_chainmask = ahp->ah_rxchainmask; | ||
| 5127 | tx_chainmask = ahp->ah_txchainmask; | ||
| 5128 | |||
| 5129 | switch (rx_chainmask) { | ||
| 5130 | case 0x5: | ||
| 5131 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | ||
| 5132 | AR_PHY_SWAP_ALT_CHAIN); | ||
| 5133 | case 0x3: | ||
| 5134 | if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) { | ||
| 5135 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); | ||
| 5136 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); | ||
| 5137 | break; | ||
| 5138 | } | ||
| 5139 | case 0x1: | ||
| 5140 | case 0x2: | ||
| 5141 | if (!AR_SREV_9280(ah)) | ||
| 5142 | break; | ||
| 5143 | case 0x7: | ||
| 5144 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | ||
| 5145 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | ||
| 5146 | break; | ||
| 5147 | default: | ||
| 5148 | break; | ||
| 5149 | } | ||
| 5150 | |||
| 5151 | REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); | ||
| 5152 | if (tx_chainmask == 0x5) { | ||
| 5153 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | ||
| 5154 | AR_PHY_SWAP_ALT_CHAIN); | ||
| 5155 | } | ||
| 5156 | if (AR_SREV_9100(ah)) | ||
| 5157 | REG_WRITE(ah, AR_PHY_ANALOG_SWAP, | ||
| 5158 | REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); | ||
| 5159 | } | ||
| 5160 | |||
| 5161 | static void ath9k_hw_set_addac(struct ath_hal *ah, | ||
| 5162 | struct ath9k_channel *chan) | ||
| 5163 | { | ||
| 5164 | struct modal_eep_header *pModal; | ||
| 5165 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5166 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | ||
| 5167 | u8 biaslevel; | ||
| 5168 | |||
| 5169 | if (ah->ah_macVersion != AR_SREV_VERSION_9160) | ||
| 5170 | return; | ||
| 5171 | |||
| 5172 | if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) | ||
| 5173 | return; | ||
| 5174 | |||
| 5175 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | ||
| 5176 | |||
| 5177 | if (pModal->xpaBiasLvl != 0xff) { | ||
| 5178 | biaslevel = pModal->xpaBiasLvl; | ||
| 5179 | } else { | ||
| 5180 | |||
| 5181 | u16 resetFreqBin, freqBin, freqCount = 0; | ||
| 5182 | struct chan_centers centers; | ||
| 5183 | |||
| 5184 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 5185 | |||
| 5186 | resetFreqBin = | ||
| 5187 | FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)); | ||
| 5188 | freqBin = pModal->xpaBiasLvlFreq[0] & 0xff; | ||
| 5189 | biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14); | ||
| 5190 | |||
| 5191 | freqCount++; | ||
| 5192 | |||
| 5193 | while (freqCount < 3) { | ||
| 5194 | if (pModal->xpaBiasLvlFreq[freqCount] == 0x0) | ||
| 5195 | break; | ||
| 5196 | |||
| 5197 | freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff; | ||
| 5198 | if (resetFreqBin >= freqBin) { | ||
| 5199 | biaslevel = | ||
| 5200 | (u8) (pModal-> | ||
| 5201 | xpaBiasLvlFreq[freqCount] | ||
| 5202 | >> 14); | ||
| 5203 | } else { | ||
| 5204 | break; | ||
| 5205 | } | ||
| 5206 | freqCount++; | ||
| 5207 | } | ||
| 5208 | } | ||
| 5209 | |||
| 5210 | if (IS_CHAN_2GHZ(chan)) { | ||
| 5211 | INI_RA(&ahp->ah_iniAddac, 7, 1) = | ||
| 5212 | (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel | ||
| 5213 | << 3; | ||
| 5214 | } else { | ||
| 5215 | INI_RA(&ahp->ah_iniAddac, 6, 1) = | ||
| 5216 | (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel | ||
| 5217 | << 6; | ||
| 5218 | } | ||
| 5219 | } | ||
| 5220 | |||
| 5221 | static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) | ||
| 5222 | { | ||
| 5223 | if (ah->ah_curchan != NULL) | ||
| 5224 | return clks / | ||
| 5225 | CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]; | ||
| 5226 | else | ||
| 5227 | return clks / CLOCK_RATE[ATH9K_MODE_11B]; | ||
| 5228 | } | ||
| 5229 | |||
| 5230 | static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) | ||
| 5231 | { | ||
| 5232 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 5233 | |||
| 5234 | if (chan && IS_CHAN_HT40(chan)) | ||
| 5235 | return ath9k_hw_mac_usec(ah, clks) / 2; | ||
| 5236 | else | ||
| 5237 | return ath9k_hw_mac_usec(ah, clks); | ||
| 5238 | } | ||
| 5239 | |||
| 5240 | static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) | ||
| 5241 | { | ||
| 5242 | if (ah->ah_curchan != NULL) | ||
| 5243 | return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, | ||
| 5244 | ah->ah_curchan)]; | ||
| 5245 | else | ||
| 5246 | return usecs * CLOCK_RATE[ATH9K_MODE_11B]; | ||
| 5247 | } | ||
| 5248 | |||
| 5249 | static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) | ||
| 5250 | { | ||
| 5251 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 5252 | |||
| 5253 | if (chan && IS_CHAN_HT40(chan)) | ||
| 5254 | return ath9k_hw_mac_clks(ah, usecs) * 2; | ||
| 5255 | else | ||
| 5256 | return ath9k_hw_mac_clks(ah, usecs); | ||
| 5257 | } | ||
| 5258 | |||
| 5259 | static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) | ||
| 5260 | { | ||
| 5261 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5262 | |||
| 5263 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { | ||
| 5264 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n", | ||
| 5265 | __func__, us); | ||
| 5266 | ahp->ah_acktimeout = (u32) -1; | ||
| 5267 | return false; | ||
| 5268 | } else { | ||
| 5269 | REG_RMW_FIELD(ah, AR_TIME_OUT, | ||
| 5270 | AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); | ||
| 5271 | ahp->ah_acktimeout = us; | ||
| 5272 | return true; | ||
| 5273 | } | ||
| 5274 | } | ||
| 5275 | |||
| 5276 | static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) | ||
| 5277 | { | ||
| 5278 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5279 | |||
| 5280 | if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { | ||
| 5281 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n", | ||
| 5282 | __func__, us); | ||
| 5283 | ahp->ah_ctstimeout = (u32) -1; | ||
| 5284 | return false; | ||
| 5285 | } else { | ||
| 5286 | REG_RMW_FIELD(ah, AR_TIME_OUT, | ||
| 5287 | AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); | ||
| 5288 | ahp->ah_ctstimeout = us; | ||
| 5289 | return true; | ||
| 5290 | } | ||
| 5291 | } | ||
| 5292 | static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, | ||
| 5293 | u32 tu) | ||
| 5294 | { | ||
| 5295 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5296 | |||
| 5297 | if (tu > 0xFFFF) { | ||
| 5298 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, | ||
| 5299 | "%s: bad global tx timeout %u\n", __func__, tu); | ||
| 5300 | ahp->ah_globaltxtimeout = (u32) -1; | ||
| 5301 | return false; | ||
| 5302 | } else { | ||
| 5303 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | ||
| 5304 | ahp->ah_globaltxtimeout = tu; | ||
| 5305 | return true; | ||
| 5306 | } | ||
| 5307 | } | ||
| 5308 | |||
| 5309 | bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) | ||
| 5310 | { | ||
| 5311 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5312 | |||
| 5313 | if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { | ||
| 5314 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n", | ||
| 5315 | __func__, us); | ||
| 5316 | ahp->ah_slottime = (u32) -1; | ||
| 5317 | return false; | ||
| 5318 | } else { | ||
| 5319 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); | ||
| 5320 | ahp->ah_slottime = us; | ||
| 5321 | return true; | ||
| 5322 | } | ||
| 5323 | } | ||
| 5324 | |||
| 5325 | static inline void ath9k_hw_init_user_settings(struct ath_hal *ah) | ||
| 5326 | { | ||
| 5327 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5328 | |||
| 5329 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n", | ||
| 5330 | __func__, ahp->ah_miscMode); | ||
| 5331 | if (ahp->ah_miscMode != 0) | ||
| 5332 | REG_WRITE(ah, AR_PCU_MISC, | ||
| 5333 | REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); | ||
| 5334 | if (ahp->ah_slottime != (u32) -1) | ||
| 5335 | ath9k_hw_setslottime(ah, ahp->ah_slottime); | ||
| 5336 | if (ahp->ah_acktimeout != (u32) -1) | ||
| 5337 | ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); | ||
| 5338 | if (ahp->ah_ctstimeout != (u32) -1) | ||
| 5339 | ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); | ||
| 5340 | if (ahp->ah_globaltxtimeout != (u32) -1) | ||
| 5341 | ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); | ||
| 5342 | } | ||
| 5343 | |||
| 5344 | static inline int | ||
| 5345 | ath9k_hw_process_ini(struct ath_hal *ah, | ||
| 5346 | struct ath9k_channel *chan, | ||
| 5347 | enum ath9k_ht_macmode macmode) | ||
| 5348 | { | ||
| 5349 | int i, regWrites = 0; | ||
| 5350 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5351 | u32 modesIndex, freqIndex; | ||
| 5352 | int status; | ||
| 5353 | |||
| 5354 | switch (chan->chanmode) { | ||
| 5355 | case CHANNEL_A: | ||
| 5356 | case CHANNEL_A_HT20: | ||
| 5357 | modesIndex = 1; | ||
| 5358 | freqIndex = 1; | ||
| 5359 | break; | ||
| 5360 | case CHANNEL_A_HT40PLUS: | ||
| 5361 | case CHANNEL_A_HT40MINUS: | ||
| 5362 | modesIndex = 2; | ||
| 5363 | freqIndex = 1; | ||
| 5364 | break; | ||
| 5365 | case CHANNEL_G: | ||
| 5366 | case CHANNEL_G_HT20: | ||
| 5367 | case CHANNEL_B: | ||
| 5368 | modesIndex = 4; | ||
| 5369 | freqIndex = 2; | ||
| 5370 | break; | ||
| 5371 | case CHANNEL_G_HT40PLUS: | ||
| 5372 | case CHANNEL_G_HT40MINUS: | ||
| 5373 | modesIndex = 3; | ||
| 5374 | freqIndex = 2; | ||
| 5375 | break; | ||
| 5376 | |||
| 5377 | default: | ||
| 5378 | return -EINVAL; | ||
| 5379 | } | ||
| 5380 | |||
| 5381 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | ||
| 5382 | |||
| 5383 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); | ||
| 5384 | |||
| 5385 | ath9k_hw_set_addac(ah, chan); | ||
| 5386 | |||
| 5387 | if (AR_SREV_5416_V22_OR_LATER(ah)) { | ||
| 5388 | REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); | ||
| 5389 | } else { | ||
| 5390 | struct ar5416IniArray temp; | ||
| 5391 | u32 addacSize = | ||
| 5392 | sizeof(u32) * ahp->ah_iniAddac.ia_rows * | ||
| 5393 | ahp->ah_iniAddac.ia_columns; | ||
| 5394 | |||
| 5395 | memcpy(ahp->ah_addac5416_21, | ||
| 5396 | ahp->ah_iniAddac.ia_array, addacSize); | ||
| 5397 | |||
| 5398 | (ahp->ah_addac5416_21)[31 * | ||
| 5399 | ahp->ah_iniAddac.ia_columns + 1] = 0; | ||
| 5400 | |||
| 5401 | temp.ia_array = ahp->ah_addac5416_21; | ||
| 5402 | temp.ia_columns = ahp->ah_iniAddac.ia_columns; | ||
| 5403 | temp.ia_rows = ahp->ah_iniAddac.ia_rows; | ||
| 5404 | REG_WRITE_ARRAY(&temp, 1, regWrites); | ||
| 5405 | } | ||
| 5406 | REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); | ||
| 5407 | |||
| 5408 | for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { | ||
| 5409 | u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); | ||
| 5410 | u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); | ||
| 5411 | |||
| 5412 | #ifdef CONFIG_SLOW_ANT_DIV | ||
| 5413 | if (ah->ah_devid == AR9280_DEVID_PCI) | ||
| 5414 | val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, | ||
| 5415 | val); | ||
| 5416 | #endif | ||
| 5417 | |||
| 5418 | REG_WRITE(ah, reg, val); | ||
| 5419 | |||
| 5420 | if (reg >= 0x7800 && reg < 0x78a0 | ||
| 5421 | && ah->ah_config.analog_shiftreg) { | ||
| 5422 | udelay(100); | ||
| 5423 | } | ||
| 5424 | |||
| 5425 | DO_DELAY(regWrites); | ||
| 5426 | } | ||
| 5427 | |||
| 5428 | for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { | ||
| 5429 | u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); | ||
| 5430 | u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); | ||
| 5431 | |||
| 5432 | REG_WRITE(ah, reg, val); | ||
| 5433 | |||
| 5434 | if (reg >= 0x7800 && reg < 0x78a0 | ||
| 5435 | && ah->ah_config.analog_shiftreg) { | ||
| 5436 | udelay(100); | ||
| 5437 | } | ||
| 5438 | |||
| 5439 | DO_DELAY(regWrites); | ||
| 5440 | } | ||
| 5441 | |||
| 5442 | ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); | ||
| 5443 | |||
| 5444 | if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { | ||
| 5445 | REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, | ||
| 5446 | regWrites); | ||
| 5447 | } | ||
| 5448 | |||
| 5449 | ath9k_hw_override_ini(ah, chan); | ||
| 5450 | ath9k_hw_set_regs(ah, chan, macmode); | ||
| 5451 | ath9k_hw_init_chain_masks(ah); | ||
| 5452 | |||
| 5453 | status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan, | ||
| 5454 | ath9k_regd_get_ctl(ah, chan), | ||
| 5455 | ath9k_regd_get_antenna_allowed(ah, | ||
| 5456 | chan), | ||
| 5457 | chan->maxRegTxPower * 2, | ||
| 5458 | min((u32) MAX_RATE_POWER, | ||
| 5459 | (u32) ah->ah_powerLimit)); | ||
| 5460 | if (status != 0) { | ||
| 5461 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | ||
| 5462 | "%s: error init'ing transmit power\n", __func__); | ||
| 5463 | return -EIO; | ||
| 5464 | } | ||
| 5465 | |||
| 5466 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { | ||
| 5467 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
| 5468 | "%s: ar5416SetRfRegs failed\n", __func__); | ||
| 5469 | return -EIO; | ||
| 5470 | } | ||
| 5471 | |||
| 5472 | return 0; | ||
| 5473 | } | ||
| 5474 | |||
| 5475 | static inline void ath9k_hw_setup_calibration(struct ath_hal *ah, | ||
| 5476 | struct hal_cal_list *currCal) | ||
| 5477 | { | ||
| 5478 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), | ||
| 5479 | AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, | ||
| 5480 | currCal->calData->calCountMax); | ||
| 5481 | |||
| 5482 | switch (currCal->calData->calType) { | ||
| 5483 | case IQ_MISMATCH_CAL: | ||
| 5484 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | ||
| 5485 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5486 | "%s: starting IQ Mismatch Calibration\n", | ||
| 5487 | __func__); | ||
| 5488 | break; | ||
| 5489 | case ADC_GAIN_CAL: | ||
| 5490 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); | ||
| 5491 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5492 | "%s: starting ADC Gain Calibration\n", __func__); | ||
| 5493 | break; | ||
| 5494 | case ADC_DC_CAL: | ||
| 5495 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); | ||
| 5496 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5497 | "%s: starting ADC DC Calibration\n", __func__); | ||
| 5498 | break; | ||
| 5499 | case ADC_DC_INIT_CAL: | ||
| 5500 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); | ||
| 5501 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5502 | "%s: starting Init ADC DC Calibration\n", | ||
| 5503 | __func__); | ||
| 5504 | break; | ||
| 5505 | } | ||
| 5506 | |||
| 5507 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), | ||
| 5508 | AR_PHY_TIMING_CTRL4_DO_CAL); | ||
| 5509 | } | ||
| 5510 | |||
| 5511 | static inline void ath9k_hw_reset_calibration(struct ath_hal *ah, | ||
| 5512 | struct hal_cal_list *currCal) | ||
| 5513 | { | ||
| 5514 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5515 | int i; | ||
| 5516 | |||
| 5517 | ath9k_hw_setup_calibration(ah, currCal); | ||
| 5518 | |||
| 5519 | currCal->calState = CAL_RUNNING; | ||
| 5520 | |||
| 5521 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 5522 | ahp->ah_Meas0.sign[i] = 0; | ||
| 5523 | ahp->ah_Meas1.sign[i] = 0; | ||
| 5524 | ahp->ah_Meas2.sign[i] = 0; | ||
| 5525 | ahp->ah_Meas3.sign[i] = 0; | ||
| 5526 | } | ||
| 5527 | |||
| 5528 | ahp->ah_CalSamples = 0; | ||
| 5529 | } | ||
| 5530 | |||
| 5531 | static inline void | ||
| 5532 | ath9k_hw_per_calibration(struct ath_hal *ah, | ||
| 5533 | struct ath9k_channel *ichan, | ||
| 5534 | u8 rxchainmask, | ||
| 5535 | struct hal_cal_list *currCal, | ||
| 5536 | bool *isCalDone) | ||
| 5537 | { | ||
| 5538 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5539 | |||
| 5540 | *isCalDone = false; | ||
| 5541 | |||
| 5542 | if (currCal->calState == CAL_RUNNING) { | ||
| 5543 | if (!(REG_READ(ah, | ||
| 5544 | AR_PHY_TIMING_CTRL4(0)) & | ||
| 5545 | AR_PHY_TIMING_CTRL4_DO_CAL)) { | ||
| 5546 | |||
| 5547 | currCal->calData->calCollect(ah); | ||
| 5548 | |||
| 5549 | ahp->ah_CalSamples++; | ||
| 5550 | |||
| 5551 | if (ahp->ah_CalSamples >= | ||
| 5552 | currCal->calData->calNumSamples) { | ||
| 5553 | int i, numChains = 0; | ||
| 5554 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 5555 | if (rxchainmask & (1 << i)) | ||
| 5556 | numChains++; | ||
| 5557 | } | ||
| 5558 | |||
| 5559 | currCal->calData->calPostProc(ah, | ||
| 5560 | numChains); | ||
| 5561 | |||
| 5562 | ichan->CalValid |= | ||
| 5563 | currCal->calData->calType; | ||
| 5564 | currCal->calState = CAL_DONE; | ||
| 5565 | *isCalDone = true; | ||
| 5566 | } else { | ||
| 5567 | ath9k_hw_setup_calibration(ah, currCal); | ||
| 5568 | } | ||
| 5569 | } | ||
| 5570 | } else if (!(ichan->CalValid & currCal->calData->calType)) { | ||
| 5571 | ath9k_hw_reset_calibration(ah, currCal); | ||
| 5572 | } | ||
| 5573 | } | ||
| 5574 | |||
| 5575 | static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah, | ||
| 5576 | int init_cal_count) | ||
| 5577 | { | ||
| 5578 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5579 | struct ath9k_channel ichan; | ||
| 5580 | bool isCalDone; | ||
| 5581 | struct hal_cal_list *currCal = ahp->ah_cal_list_curr; | ||
| 5582 | const struct hal_percal_data *calData = currCal->calData; | ||
| 5583 | int i; | ||
| 5584 | |||
| 5585 | if (currCal == NULL) | ||
| 5586 | return false; | ||
| 5587 | |||
| 5588 | ichan.CalValid = 0; | ||
| 5589 | |||
| 5590 | for (i = 0; i < init_cal_count; i++) { | ||
| 5591 | ath9k_hw_reset_calibration(ah, currCal); | ||
| 5592 | |||
| 5593 | if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0), | ||
| 5594 | AR_PHY_TIMING_CTRL4_DO_CAL, 0)) { | ||
| 5595 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5596 | "%s: Cal %d failed to complete in 100ms.\n", | ||
| 5597 | __func__, calData->calType); | ||
| 5598 | |||
| 5599 | ahp->ah_cal_list = ahp->ah_cal_list_last = | ||
| 5600 | ahp->ah_cal_list_curr = NULL; | ||
| 5601 | return false; | ||
| 5602 | } | ||
| 5603 | |||
| 5604 | ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask, | ||
| 5605 | currCal, &isCalDone); | ||
| 5606 | if (!isCalDone) { | ||
| 5607 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5608 | "%s: Not able to run Init Cal %d.\n", | ||
| 5609 | __func__, calData->calType); | ||
| 5610 | } | ||
| 5611 | if (currCal->calNext) { | ||
| 5612 | currCal = currCal->calNext; | ||
| 5613 | calData = currCal->calData; | ||
| 5614 | } | ||
| 5615 | } | ||
| 5616 | |||
| 5617 | ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL; | ||
| 5618 | return true; | ||
| 5619 | } | ||
| 5620 | |||
| 5621 | static inline bool | ||
| 5622 | ath9k_hw_channel_change(struct ath_hal *ah, | ||
| 5623 | struct ath9k_channel *chan, | ||
| 5624 | enum ath9k_ht_macmode macmode) | ||
| 5625 | { | ||
| 5626 | u32 synthDelay, qnum; | ||
| 5627 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5628 | |||
| 5629 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | ||
| 5630 | if (ath9k_hw_numtxpending(ah, qnum)) { | ||
| 5631 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | ||
| 5632 | "%s: Transmit frames pending on queue %d\n", | ||
| 5633 | __func__, qnum); | ||
| 5634 | return false; | ||
| 5635 | } | ||
| 5636 | } | ||
| 5637 | |||
| 5638 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); | ||
| 5639 | if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | ||
| 5640 | AR_PHY_RFBUS_GRANT_EN)) { | ||
| 5641 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | ||
| 5642 | "%s: Could not kill baseband RX\n", __func__); | ||
| 5643 | return false; | ||
| 5644 | } | ||
| 5645 | |||
| 5646 | ath9k_hw_set_regs(ah, chan, macmode); | ||
| 5647 | |||
| 5648 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 5649 | if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { | ||
| 5650 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 5651 | "%s: failed to set channel\n", __func__); | ||
| 5652 | return false; | ||
| 5653 | } | ||
| 5654 | } else { | ||
| 5655 | if (!(ath9k_hw_set_channel(ah, chan))) { | ||
| 5656 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 5657 | "%s: failed to set channel\n", __func__); | ||
| 5658 | return false; | ||
| 5659 | } | ||
| 5660 | } | ||
| 5661 | |||
| 5662 | if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan, | ||
| 5663 | ath9k_regd_get_ctl(ah, chan), | ||
| 5664 | ath9k_regd_get_antenna_allowed(ah, chan), | ||
| 5665 | chan->maxRegTxPower * 2, | ||
| 5666 | min((u32) MAX_RATE_POWER, | ||
| 5667 | (u32) ah->ah_powerLimit)) != 0) { | ||
| 5668 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 5669 | "%s: error init'ing transmit power\n", __func__); | ||
| 5670 | return false; | ||
| 5671 | } | ||
| 5672 | |||
| 5673 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | ||
| 5674 | if (IS_CHAN_CCK(chan)) | ||
| 5675 | synthDelay = (4 * synthDelay) / 22; | ||
| 5676 | else | ||
| 5677 | synthDelay /= 10; | ||
| 5678 | |||
| 5679 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | ||
| 5680 | |||
| 5681 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | ||
| 5682 | |||
| 5683 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) | ||
| 5684 | ath9k_hw_set_delta_slope(ah, chan); | ||
| 5685 | |||
| 5686 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 5687 | ath9k_hw_9280_spur_mitigate(ah, chan); | ||
| 5688 | else | ||
| 5689 | ath9k_hw_spur_mitigate(ah, chan); | ||
| 5690 | |||
| 5691 | if (!chan->oneTimeCalsDone) | ||
| 5692 | chan->oneTimeCalsDone = true; | ||
| 5693 | |||
| 5694 | return true; | ||
| 5695 | } | ||
| 5696 | |||
| 5697 | static bool ath9k_hw_chip_reset(struct ath_hal *ah, | ||
| 5698 | struct ath9k_channel *chan) | ||
| 5699 | { | ||
| 5700 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5701 | |||
| 5702 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) | ||
| 5703 | return false; | ||
| 5704 | |||
| 5705 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) | ||
| 5706 | return false; | ||
| 5707 | |||
| 5708 | ahp->ah_chipFullSleep = false; | ||
| 5709 | |||
| 5710 | ath9k_hw_init_pll(ah, chan); | ||
| 5711 | |||
| 5712 | ath9k_hw_set_rfmode(ah, chan); | ||
| 5713 | |||
| 5714 | return true; | ||
| 5715 | } | ||
| 5716 | |||
| 5717 | static inline void ath9k_hw_set_dma(struct ath_hal *ah) | ||
| 5718 | { | ||
| 5719 | u32 regval; | ||
| 5720 | |||
| 5721 | regval = REG_READ(ah, AR_AHB_MODE); | ||
| 5722 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | ||
| 5723 | |||
| 5724 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; | ||
| 5725 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | ||
| 5726 | |||
| 5727 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); | ||
| 5728 | |||
| 5729 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; | ||
| 5730 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | ||
| 5731 | |||
| 5732 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); | ||
| 5733 | |||
| 5734 | if (AR_SREV_9285(ah)) { | ||
| 5735 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, | ||
| 5736 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | ||
| 5737 | } else { | ||
| 5738 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, | ||
| 5739 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | ||
| 5740 | } | ||
| 5741 | } | ||
| 5742 | |||
| 5743 | bool ath9k_hw_stopdmarecv(struct ath_hal *ah) | ||
| 5744 | { | ||
| 5745 | REG_WRITE(ah, AR_CR, AR_CR_RXD); | ||
| 5746 | if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { | ||
| 5747 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | ||
| 5748 | "%s: dma failed to stop in 10ms\n" | ||
| 5749 | "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", | ||
| 5750 | __func__, | ||
| 5751 | REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); | ||
| 5752 | return false; | ||
| 5753 | } else { | ||
| 5754 | return true; | ||
| 5755 | } | ||
| 5756 | } | ||
| 5757 | |||
| 5758 | void ath9k_hw_startpcureceive(struct ath_hal *ah) | ||
| 5759 | { | ||
| 5760 | REG_CLR_BIT(ah, AR_DIAG_SW, | ||
| 5761 | (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | ||
| 5762 | |||
| 5763 | ath9k_enable_mib_counters(ah); | ||
| 5764 | |||
| 5765 | ath9k_ani_reset(ah); | ||
| 5766 | } | ||
| 5767 | |||
| 5768 | void ath9k_hw_stoppcurecv(struct ath_hal *ah) | ||
| 5769 | { | ||
| 5770 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); | ||
| 5771 | |||
| 5772 | ath9k_hw_disable_mib_counters(ah); | ||
| 5773 | } | ||
| 5774 | |||
| 5775 | static bool ath9k_hw_iscal_supported(struct ath_hal *ah, | ||
| 5776 | struct ath9k_channel *chan, | ||
| 5777 | enum hal_cal_types calType) | ||
| 5778 | { | ||
| 5779 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5780 | bool retval = false; | ||
| 5781 | |||
| 5782 | switch (calType & ahp->ah_suppCals) { | ||
| 5783 | case IQ_MISMATCH_CAL: | ||
| 5784 | if (!IS_CHAN_B(chan)) | ||
| 5785 | retval = true; | ||
| 5786 | break; | ||
| 5787 | case ADC_GAIN_CAL: | ||
| 5788 | case ADC_DC_CAL: | ||
| 5789 | if (!IS_CHAN_B(chan) | ||
| 5790 | && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan))) | ||
| 5791 | retval = true; | ||
| 5792 | break; | ||
| 5793 | } | ||
| 5794 | |||
| 5795 | return retval; | ||
| 5796 | } | ||
| 5797 | |||
| 5798 | static inline bool ath9k_hw_init_cal(struct ath_hal *ah, | ||
| 5799 | struct ath9k_channel *chan) | ||
| 5800 | { | ||
| 5801 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5802 | struct ath9k_channel *ichan = | ||
| 5803 | ath9k_regd_check_channel(ah, chan); | ||
| 5804 | |||
| 5805 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, | ||
| 5806 | REG_READ(ah, AR_PHY_AGC_CONTROL) | | ||
| 5807 | AR_PHY_AGC_CONTROL_CAL); | ||
| 5808 | |||
| 5809 | if (!ath9k_hw_wait | ||
| 5810 | (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { | ||
| 5811 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5812 | "%s: offset calibration failed to complete in 1ms; " | ||
| 5813 | "noisy environment?\n", __func__); | ||
| 5814 | return false; | ||
| 5815 | } | ||
| 5816 | |||
| 5817 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, | ||
| 5818 | REG_READ(ah, AR_PHY_AGC_CONTROL) | | ||
| 5819 | AR_PHY_AGC_CONTROL_NF); | ||
| 5820 | |||
| 5821 | ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = | ||
| 5822 | NULL; | ||
| 5823 | |||
| 5824 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { | ||
| 5825 | if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) { | ||
| 5826 | INIT_CAL(&ahp->ah_adcGainCalData); | ||
| 5827 | INSERT_CAL(ahp, &ahp->ah_adcGainCalData); | ||
| 5828 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5829 | "%s: enabling ADC Gain Calibration.\n", | ||
| 5830 | __func__); | ||
| 5831 | } | ||
| 5832 | if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) { | ||
| 5833 | INIT_CAL(&ahp->ah_adcDcCalData); | ||
| 5834 | INSERT_CAL(ahp, &ahp->ah_adcDcCalData); | ||
| 5835 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5836 | "%s: enabling ADC DC Calibration.\n", | ||
| 5837 | __func__); | ||
| 5838 | } | ||
| 5839 | if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) { | ||
| 5840 | INIT_CAL(&ahp->ah_iqCalData); | ||
| 5841 | INSERT_CAL(ahp, &ahp->ah_iqCalData); | ||
| 5842 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 5843 | "%s: enabling IQ Calibration.\n", | ||
| 5844 | __func__); | ||
| 5845 | } | ||
| 5846 | |||
| 5847 | ahp->ah_cal_list_curr = ahp->ah_cal_list; | ||
| 5848 | |||
| 5849 | if (ahp->ah_cal_list_curr) | ||
| 5850 | ath9k_hw_reset_calibration(ah, | ||
| 5851 | ahp->ah_cal_list_curr); | ||
| 5852 | } | ||
| 5853 | |||
| 5854 | ichan->CalValid = 0; | ||
| 5855 | |||
| 5856 | return true; | ||
| 5857 | } | ||
| 5858 | |||
| 5859 | |||
| 5860 | bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode, | ||
| 5861 | struct ath9k_channel *chan, | ||
| 5862 | enum ath9k_ht_macmode macmode, | ||
| 5863 | u8 txchainmask, u8 rxchainmask, | ||
| 5864 | enum ath9k_ht_extprotspacing extprotspacing, | ||
| 5865 | bool bChannelChange, | ||
| 5866 | int *status) | ||
| 5867 | { | ||
| 5868 | #define FAIL(_code) do { ecode = _code; goto bad; } while (0) | ||
| 5869 | u32 saveLedState; | ||
| 5870 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 5871 | struct ath9k_channel *curchan = ah->ah_curchan; | ||
| 5872 | u32 saveDefAntenna; | ||
| 5873 | u32 macStaId1; | ||
| 5874 | int ecode; | ||
| 5875 | int i, rx_chainmask; | ||
| 5876 | |||
| 5877 | ahp->ah_extprotspacing = extprotspacing; | ||
| 5878 | ahp->ah_txchainmask = txchainmask; | ||
| 5879 | ahp->ah_rxchainmask = rxchainmask; | ||
| 5880 | |||
| 5881 | if (AR_SREV_9280(ah)) { | ||
| 5882 | ahp->ah_txchainmask &= 0x3; | ||
| 5883 | ahp->ah_rxchainmask &= 0x3; | ||
| 5884 | } | ||
| 5885 | |||
| 5886 | if (ath9k_hw_check_chan(ah, chan) == NULL) { | ||
| 5887 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 5888 | "%s: invalid channel %u/0x%x; no mapping\n", | ||
| 5889 | __func__, chan->channel, chan->channelFlags); | ||
| 5890 | FAIL(-EINVAL); | ||
| 5891 | } | ||
| 5892 | |||
| 5893 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) | ||
| 5894 | return false; | ||
| 5895 | |||
| 5896 | if (curchan) | ||
| 5897 | ath9k_hw_getnf(ah, curchan); | ||
| 5898 | |||
| 5899 | if (bChannelChange && | ||
| 5900 | (ahp->ah_chipFullSleep != true) && | ||
| 5901 | (ah->ah_curchan != NULL) && | ||
| 5902 | (chan->channel != ah->ah_curchan->channel) && | ||
| 5903 | ((chan->channelFlags & CHANNEL_ALL) == | ||
| 5904 | (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && | ||
| 5905 | (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && | ||
| 5906 | !IS_CHAN_A_5MHZ_SPACED(ah-> | ||
| 5907 | ah_curchan)))) { | ||
| 5908 | |||
| 5909 | if (ath9k_hw_channel_change(ah, chan, macmode)) { | ||
| 5910 | ath9k_hw_loadnf(ah, ah->ah_curchan); | ||
| 5911 | ath9k_hw_start_nfcal(ah); | ||
| 5912 | return true; | ||
| 5913 | } | ||
| 5914 | } | ||
| 5915 | |||
| 5916 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | ||
| 5917 | if (saveDefAntenna == 0) | ||
| 5918 | saveDefAntenna = 1; | ||
| 5919 | |||
| 5920 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | ||
| 5921 | |||
| 5922 | saveLedState = REG_READ(ah, AR_CFG_LED) & | ||
| 5923 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | ||
| 5924 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | ||
| 5925 | |||
| 5926 | ath9k_hw_mark_phy_inactive(ah); | ||
| 5927 | |||
| 5928 | if (!ath9k_hw_chip_reset(ah, chan)) { | ||
| 5929 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n", | ||
| 5930 | __func__); | ||
| 5931 | FAIL(-EIO); | ||
| 5932 | } | ||
| 5933 | |||
| 5934 | if (AR_SREV_9280(ah)) { | ||
| 5935 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
| 5936 | AR_GPIO_JTAG_DISABLE); | ||
| 5937 | |||
| 5938 | if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) { | ||
| 5939 | if (IS_CHAN_5GHZ(chan)) | ||
| 5940 | ath9k_hw_set_gpio(ah, 9, 0); | ||
| 5941 | else | ||
| 5942 | ath9k_hw_set_gpio(ah, 9, 1); | ||
| 5943 | } | ||
| 5944 | ath9k_hw_cfg_output(ah, 9, ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT); | ||
| 5945 | } | ||
| 5946 | |||
| 5947 | ecode = ath9k_hw_process_ini(ah, chan, macmode); | ||
| 5948 | if (ecode != 0) | ||
| 5949 | goto bad; | ||
| 5950 | |||
| 5951 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) | ||
| 5952 | ath9k_hw_set_delta_slope(ah, chan); | ||
| 5953 | |||
| 5954 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 5955 | ath9k_hw_9280_spur_mitigate(ah, chan); | ||
| 5956 | else | ||
| 5957 | ath9k_hw_spur_mitigate(ah, chan); | ||
| 5958 | |||
| 5959 | if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { | ||
| 5960 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | ||
| 5961 | "%s: error setting board options\n", __func__); | ||
| 5962 | FAIL(-EIO); | ||
| 5963 | } | ||
| 5964 | |||
| 5965 | ath9k_hw_decrease_chain_power(ah, chan); | ||
| 5966 | |||
| 5967 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr)); | ||
| 5968 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4) | ||
| 5969 | | macStaId1 | ||
| 5970 | | AR_STA_ID1_RTS_USE_DEF | ||
| 5971 | | (ah->ah_config. | ||
| 5972 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) | ||
| 5973 | | ahp->ah_staId1Defaults); | ||
| 5974 | ath9k_hw_set_operating_mode(ah, opmode); | ||
| 5975 | |||
| 5976 | REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); | ||
| 5977 | REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); | ||
| 5978 | |||
| 5979 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | ||
| 5980 | |||
| 5981 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); | ||
| 5982 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | | ||
| 5983 | ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S)); | ||
| 5984 | |||
| 5985 | REG_WRITE(ah, AR_ISR, ~0); | ||
| 5986 | |||
| 5987 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | ||
| 5988 | |||
| 5989 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 5990 | if (!(ath9k_hw_ar9280_set_channel(ah, chan))) | ||
| 5991 | FAIL(-EIO); | ||
| 5992 | } else { | ||
| 5993 | if (!(ath9k_hw_set_channel(ah, chan))) | ||
| 5994 | FAIL(-EIO); | ||
| 5995 | } | ||
| 5996 | |||
| 5997 | for (i = 0; i < AR_NUM_DCU; i++) | ||
| 5998 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | ||
| 5999 | |||
| 6000 | ahp->ah_intrTxqs = 0; | ||
| 6001 | for (i = 0; i < ah->ah_caps.total_queues; i++) | ||
| 6002 | ath9k_hw_resettxqueue(ah, i); | ||
| 6003 | |||
| 6004 | ath9k_hw_init_interrupt_masks(ah, opmode); | ||
| 6005 | ath9k_hw_init_qos(ah); | ||
| 6006 | |||
| 6007 | ath9k_hw_init_user_settings(ah); | ||
| 6008 | |||
| 6009 | ah->ah_opmode = opmode; | ||
| 6010 | |||
| 6011 | REG_WRITE(ah, AR_STA_ID1, | ||
| 6012 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | ||
| 6013 | |||
| 6014 | ath9k_hw_set_dma(ah); | ||
| 6015 | |||
| 6016 | REG_WRITE(ah, AR_OBS, 8); | ||
| 6017 | |||
| 6018 | if (ahp->ah_intrMitigation) { | ||
| 6019 | |||
| 6020 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); | ||
| 6021 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | ||
| 6022 | } | ||
| 6023 | |||
| 6024 | ath9k_hw_init_bb(ah, chan); | ||
| 6025 | |||
| 6026 | if (!ath9k_hw_init_cal(ah, chan)) | ||
| 6027 | FAIL(-ENODEV); | ||
| 6028 | |||
| 6029 | rx_chainmask = ahp->ah_rxchainmask; | ||
| 6030 | if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { | ||
| 6031 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); | ||
| 6032 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); | ||
| 6033 | } | ||
| 6034 | |||
| 6035 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); | ||
| 6036 | |||
| 6037 | if (AR_SREV_9100(ah)) { | ||
| 6038 | u32 mask; | ||
| 6039 | mask = REG_READ(ah, AR_CFG); | ||
| 6040 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | ||
| 6041 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 6042 | "%s CFG Byte Swap Set 0x%x\n", __func__, | ||
| 6043 | mask); | ||
| 6044 | } else { | ||
| 6045 | mask = | ||
| 6046 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | ||
| 6047 | REG_WRITE(ah, AR_CFG, mask); | ||
| 6048 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 6049 | "%s Setting CFG 0x%x\n", __func__, | ||
| 6050 | REG_READ(ah, AR_CFG)); | ||
| 6051 | } | ||
| 6052 | } else { | ||
| 6053 | #ifdef __BIG_ENDIAN | ||
| 6054 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | ||
| 6055 | #endif | ||
| 6056 | } | ||
| 6057 | |||
| 6058 | return true; | ||
| 6059 | bad: | ||
| 6060 | if (status) | ||
| 6061 | *status = ecode; | ||
| 6062 | return false; | ||
| 6063 | #undef FAIL | ||
| 6064 | } | ||
| 6065 | |||
| 6066 | bool ath9k_hw_phy_disable(struct ath_hal *ah) | ||
| 6067 | { | ||
| 6068 | return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); | ||
| 6069 | } | ||
| 6070 | |||
| 6071 | bool ath9k_hw_disable(struct ath_hal *ah) | ||
| 6072 | { | ||
| 6073 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) | ||
| 6074 | return false; | ||
| 6075 | |||
| 6076 | return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); | ||
| 6077 | } | ||
| 6078 | |||
| 6079 | bool | ||
| 6080 | ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, | ||
| 6081 | u8 rxchainmask, bool longcal, | ||
| 6082 | bool *isCalDone) | ||
| 6083 | { | ||
| 6084 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6085 | struct hal_cal_list *currCal = ahp->ah_cal_list_curr; | ||
| 6086 | struct ath9k_channel *ichan = | ||
| 6087 | ath9k_regd_check_channel(ah, chan); | ||
| 6088 | |||
| 6089 | *isCalDone = true; | ||
| 6090 | |||
| 6091 | if (ichan == NULL) { | ||
| 6092 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 6093 | "%s: invalid channel %u/0x%x; no mapping\n", | ||
| 6094 | __func__, chan->channel, chan->channelFlags); | ||
| 6095 | return false; | ||
| 6096 | } | ||
| 6097 | |||
| 6098 | if (currCal && | ||
| 6099 | (currCal->calState == CAL_RUNNING || | ||
| 6100 | currCal->calState == CAL_WAITING)) { | ||
| 6101 | ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal, | ||
| 6102 | isCalDone); | ||
| 6103 | if (*isCalDone) { | ||
| 6104 | ahp->ah_cal_list_curr = currCal = currCal->calNext; | ||
| 6105 | |||
| 6106 | if (currCal->calState == CAL_WAITING) { | ||
| 6107 | *isCalDone = false; | ||
| 6108 | ath9k_hw_reset_calibration(ah, currCal); | ||
| 6109 | } | ||
| 6110 | } | ||
| 6111 | } | ||
| 6112 | |||
| 6113 | if (longcal) { | ||
| 6114 | ath9k_hw_getnf(ah, ichan); | ||
| 6115 | ath9k_hw_loadnf(ah, ah->ah_curchan); | ||
| 6116 | ath9k_hw_start_nfcal(ah); | ||
| 6117 | |||
| 6118 | if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) { | ||
| 6119 | |||
| 6120 | chan->channelFlags |= CHANNEL_CW_INT; | ||
| 6121 | ichan->channelFlags &= ~CHANNEL_CW_INT; | ||
| 6122 | } | ||
| 6123 | } | ||
| 6124 | |||
| 6125 | return true; | ||
| 6126 | } | ||
| 6127 | |||
| 6128 | static void ath9k_hw_iqcal_collect(struct ath_hal *ah) | ||
| 6129 | { | ||
| 6130 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6131 | int i; | ||
| 6132 | |||
| 6133 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 6134 | ahp->ah_totalPowerMeasI[i] += | ||
| 6135 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); | ||
| 6136 | ahp->ah_totalPowerMeasQ[i] += | ||
| 6137 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | ||
| 6138 | ahp->ah_totalIqCorrMeas[i] += | ||
| 6139 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | ||
| 6140 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6141 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | ||
| 6142 | ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i], | ||
| 6143 | ahp->ah_totalPowerMeasQ[i], | ||
| 6144 | ahp->ah_totalIqCorrMeas[i]); | ||
| 6145 | } | ||
| 6146 | } | ||
| 6147 | |||
| 6148 | static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) | ||
| 6149 | { | ||
| 6150 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6151 | int i; | ||
| 6152 | |||
| 6153 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 6154 | ahp->ah_totalAdcIOddPhase[i] += | ||
| 6155 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); | ||
| 6156 | ahp->ah_totalAdcIEvenPhase[i] += | ||
| 6157 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | ||
| 6158 | ahp->ah_totalAdcQOddPhase[i] += | ||
| 6159 | REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | ||
| 6160 | ahp->ah_totalAdcQEvenPhase[i] += | ||
| 6161 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | ||
| 6162 | |||
| 6163 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6164 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | ||
| 6165 | "oddq=0x%08x; evenq=0x%08x;\n", | ||
| 6166 | ahp->ah_CalSamples, i, | ||
| 6167 | ahp->ah_totalAdcIOddPhase[i], | ||
| 6168 | ahp->ah_totalAdcIEvenPhase[i], | ||
| 6169 | ahp->ah_totalAdcQOddPhase[i], | ||
| 6170 | ahp->ah_totalAdcQEvenPhase[i]); | ||
| 6171 | } | ||
| 6172 | } | ||
| 6173 | |||
| 6174 | static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) | ||
| 6175 | { | ||
| 6176 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6177 | int i; | ||
| 6178 | |||
| 6179 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | ||
| 6180 | ahp->ah_totalAdcDcOffsetIOddPhase[i] += | ||
| 6181 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); | ||
| 6182 | ahp->ah_totalAdcDcOffsetIEvenPhase[i] += | ||
| 6183 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | ||
| 6184 | ahp->ah_totalAdcDcOffsetQOddPhase[i] += | ||
| 6185 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | ||
| 6186 | ahp->ah_totalAdcDcOffsetQEvenPhase[i] += | ||
| 6187 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | ||
| 6188 | |||
| 6189 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6190 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | ||
| 6191 | "oddq=0x%08x; evenq=0x%08x;\n", | ||
| 6192 | ahp->ah_CalSamples, i, | ||
| 6193 | ahp->ah_totalAdcDcOffsetIOddPhase[i], | ||
| 6194 | ahp->ah_totalAdcDcOffsetIEvenPhase[i], | ||
| 6195 | ahp->ah_totalAdcDcOffsetQOddPhase[i], | ||
| 6196 | ahp->ah_totalAdcDcOffsetQEvenPhase[i]); | ||
| 6197 | } | ||
| 6198 | } | ||
| 6199 | |||
| 6200 | static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) | ||
| 6201 | { | ||
| 6202 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6203 | u32 powerMeasQ, powerMeasI, iqCorrMeas; | ||
| 6204 | u32 qCoffDenom, iCoffDenom; | ||
| 6205 | int32_t qCoff, iCoff; | ||
| 6206 | int iqCorrNeg, i; | ||
| 6207 | |||
| 6208 | for (i = 0; i < numChains; i++) { | ||
| 6209 | powerMeasI = ahp->ah_totalPowerMeasI[i]; | ||
| 6210 | powerMeasQ = ahp->ah_totalPowerMeasQ[i]; | ||
| 6211 | iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; | ||
| 6212 | |||
| 6213 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6214 | "Starting IQ Cal and Correction for Chain %d\n", | ||
| 6215 | i); | ||
| 6216 | |||
| 6217 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6218 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", | ||
| 6219 | i, ahp->ah_totalIqCorrMeas[i]); | ||
| 6220 | |||
| 6221 | iqCorrNeg = 0; | ||
| 6222 | |||
| 6223 | |||
| 6224 | if (iqCorrMeas > 0x80000000) { | ||
| 6225 | iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; | ||
| 6226 | iqCorrNeg = 1; | ||
| 6227 | } | ||
| 6228 | |||
| 6229 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6230 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | ||
| 6231 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6232 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | ||
| 6233 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | ||
| 6234 | iqCorrNeg); | ||
| 6235 | |||
| 6236 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; | ||
| 6237 | qCoffDenom = powerMeasQ / 64; | ||
| 6238 | |||
| 6239 | if (powerMeasQ != 0) { | ||
| 6240 | |||
| 6241 | iCoff = iqCorrMeas / iCoffDenom; | ||
| 6242 | qCoff = powerMeasI / qCoffDenom - 64; | ||
| 6243 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6244 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | ||
| 6245 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6246 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | ||
| 6247 | |||
| 6248 | |||
| 6249 | iCoff = iCoff & 0x3f; | ||
| 6250 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6251 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); | ||
| 6252 | if (iqCorrNeg == 0x0) | ||
| 6253 | iCoff = 0x40 - iCoff; | ||
| 6254 | |||
| 6255 | if (qCoff > 15) | ||
| 6256 | qCoff = 15; | ||
| 6257 | else if (qCoff <= -16) | ||
| 6258 | qCoff = 16; | ||
| 6259 | |||
| 6260 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6261 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | ||
| 6262 | i, iCoff, qCoff); | ||
| 6263 | |||
| 6264 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | ||
| 6265 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, | ||
| 6266 | iCoff); | ||
| 6267 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | ||
| 6268 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, | ||
| 6269 | qCoff); | ||
| 6270 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6271 | "IQ Cal and Correction done for Chain %d\n", | ||
| 6272 | i); | ||
| 6273 | } | ||
| 6274 | } | ||
| 6275 | |||
| 6276 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), | ||
| 6277 | AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); | ||
| 6278 | } | ||
| 6279 | |||
| 6280 | static void | ||
| 6281 | ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) | ||
| 6282 | { | ||
| 6283 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6284 | u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, | ||
| 6285 | qEvenMeasOffset; | ||
| 6286 | u32 qGainMismatch, iGainMismatch, val, i; | ||
| 6287 | |||
| 6288 | for (i = 0; i < numChains; i++) { | ||
| 6289 | iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i]; | ||
| 6290 | iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i]; | ||
| 6291 | qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i]; | ||
| 6292 | qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i]; | ||
| 6293 | |||
| 6294 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6295 | "Starting ADC Gain Cal for Chain %d\n", i); | ||
| 6296 | |||
| 6297 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6298 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, | ||
| 6299 | iOddMeasOffset); | ||
| 6300 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6301 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, | ||
| 6302 | iEvenMeasOffset); | ||
| 6303 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6304 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, | ||
| 6305 | qOddMeasOffset); | ||
| 6306 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6307 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, | ||
| 6308 | qEvenMeasOffset); | ||
| 6309 | |||
| 6310 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { | ||
| 6311 | iGainMismatch = | ||
| 6312 | ((iEvenMeasOffset * 32) / | ||
| 6313 | iOddMeasOffset) & 0x3f; | ||
| 6314 | qGainMismatch = | ||
| 6315 | ((qOddMeasOffset * 32) / | ||
| 6316 | qEvenMeasOffset) & 0x3f; | ||
| 6317 | |||
| 6318 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6319 | "Chn %d gain_mismatch_i = 0x%08x\n", i, | ||
| 6320 | iGainMismatch); | ||
| 6321 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6322 | "Chn %d gain_mismatch_q = 0x%08x\n", i, | ||
| 6323 | qGainMismatch); | ||
| 6324 | |||
| 6325 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | ||
| 6326 | val &= 0xfffff000; | ||
| 6327 | val |= (qGainMismatch) | (iGainMismatch << 6); | ||
| 6328 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | ||
| 6329 | |||
| 6330 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6331 | "ADC Gain Cal done for Chain %d\n", i); | ||
| 6332 | } | ||
| 6333 | } | ||
| 6334 | |||
| 6335 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | ||
| 6336 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | | ||
| 6337 | AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); | ||
| 6338 | } | ||
| 6339 | |||
| 6340 | static void | ||
| 6341 | ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) | ||
| 6342 | { | ||
| 6343 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6344 | u32 iOddMeasOffset, iEvenMeasOffset, val, i; | ||
| 6345 | int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; | ||
| 6346 | const struct hal_percal_data *calData = | ||
| 6347 | ahp->ah_cal_list_curr->calData; | ||
| 6348 | u32 numSamples = | ||
| 6349 | (1 << (calData->calCountMax + 5)) * calData->calNumSamples; | ||
| 6350 | |||
| 6351 | for (i = 0; i < numChains; i++) { | ||
| 6352 | iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i]; | ||
| 6353 | iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i]; | ||
| 6354 | qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i]; | ||
| 6355 | qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i]; | ||
| 6356 | |||
| 6357 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6358 | "Starting ADC DC Offset Cal for Chain %d\n", i); | ||
| 6359 | |||
| 6360 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6361 | "Chn %d pwr_meas_odd_i = %d\n", i, | ||
| 6362 | iOddMeasOffset); | ||
| 6363 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6364 | "Chn %d pwr_meas_even_i = %d\n", i, | ||
| 6365 | iEvenMeasOffset); | ||
| 6366 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6367 | "Chn %d pwr_meas_odd_q = %d\n", i, | ||
| 6368 | qOddMeasOffset); | ||
| 6369 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6370 | "Chn %d pwr_meas_even_q = %d\n", i, | ||
| 6371 | qEvenMeasOffset); | ||
| 6372 | |||
| 6373 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / | ||
| 6374 | numSamples) & 0x1ff; | ||
| 6375 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / | ||
| 6376 | numSamples) & 0x1ff; | ||
| 6377 | |||
| 6378 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6379 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, | ||
| 6380 | iDcMismatch); | ||
| 6381 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6382 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, | ||
| 6383 | qDcMismatch); | ||
| 6384 | |||
| 6385 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | ||
| 6386 | val &= 0xc0000fff; | ||
| 6387 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); | ||
| 6388 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | ||
| 6389 | |||
| 6390 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6391 | "ADC DC Offset Cal done for Chain %d\n", i); | ||
| 6392 | } | ||
| 6393 | |||
| 6394 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | ||
| 6395 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | | ||
| 6396 | AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE); | ||
| 6397 | } | ||
| 6398 | |||
| 6399 | bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) | ||
| 6400 | { | ||
| 6401 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6402 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 6403 | |||
| 6404 | ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER); | ||
| 6405 | |||
| 6406 | if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan, | ||
| 6407 | ath9k_regd_get_ctl(ah, chan), | ||
| 6408 | ath9k_regd_get_antenna_allowed(ah, | ||
| 6409 | chan), | ||
| 6410 | chan->maxRegTxPower * 2, | ||
| 6411 | min((u32) MAX_RATE_POWER, | ||
| 6412 | (u32) ah->ah_powerLimit)) != 0) | ||
| 6413 | return false; | ||
| 6414 | |||
| 6415 | return true; | ||
| 6416 | } | ||
| 6417 | |||
| 6418 | void | ||
| 6419 | ath9k_hw_get_channel_centers(struct ath_hal *ah, | ||
| 6420 | struct ath9k_channel *chan, | ||
| 6421 | struct chan_centers *centers) | ||
| 6422 | { | ||
| 6423 | int8_t extoff; | ||
| 6424 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6425 | |||
| 6426 | if (!IS_CHAN_HT40(chan)) { | ||
| 6427 | centers->ctl_center = centers->ext_center = | ||
| 6428 | centers->synth_center = chan->channel; | ||
| 6429 | return; | ||
| 6430 | } | ||
| 6431 | |||
| 6432 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || | ||
| 6433 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | ||
| 6434 | centers->synth_center = | ||
| 6435 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | ||
| 6436 | extoff = 1; | ||
| 6437 | } else { | ||
| 6438 | centers->synth_center = | ||
| 6439 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | ||
| 6440 | extoff = -1; | ||
| 6441 | } | ||
| 6442 | |||
| 6443 | centers->ctl_center = centers->synth_center - (extoff * | ||
| 6444 | HT40_CHANNEL_CENTER_SHIFT); | ||
| 6445 | centers->ext_center = centers->synth_center + (extoff * | ||
| 6446 | ((ahp-> | ||
| 6447 | ah_extprotspacing | ||
| 6448 | == | ||
| 6449 | ATH9K_HT_EXTPROTSPACING_20) | ||
| 6450 | ? | ||
| 6451 | HT40_CHANNEL_CENTER_SHIFT | ||
| 6452 | : 15)); | ||
| 6453 | |||
| 6454 | } | ||
| 6455 | |||
| 6456 | void | ||
| 6457 | ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, | ||
| 6458 | bool *isCalDone) | ||
| 6459 | { | ||
| 6460 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6461 | struct ath9k_channel *ichan = | ||
| 6462 | ath9k_regd_check_channel(ah, chan); | ||
| 6463 | struct hal_cal_list *currCal = ahp->ah_cal_list_curr; | ||
| 6464 | |||
| 6465 | *isCalDone = true; | ||
| 6466 | |||
| 6467 | if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) | ||
| 6468 | return; | ||
| 6469 | |||
| 6470 | if (currCal == NULL) | ||
| 6471 | return; | ||
| 6472 | |||
| 6473 | if (ichan == NULL) { | ||
| 6474 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6475 | "%s: invalid channel %u/0x%x; no mapping\n", | ||
| 6476 | __func__, chan->channel, chan->channelFlags); | ||
| 6477 | return; | ||
| 6478 | } | ||
| 6479 | |||
| 6480 | |||
| 6481 | if (currCal->calState != CAL_DONE) { | ||
| 6482 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6483 | "%s: Calibration state incorrect, %d\n", | ||
| 6484 | __func__, currCal->calState); | ||
| 6485 | return; | ||
| 6486 | } | ||
| 6487 | |||
| 6488 | |||
| 6489 | if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType)) | ||
| 6490 | return; | ||
| 6491 | |||
| 6492 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | ||
| 6493 | "%s: Resetting Cal %d state for channel %u/0x%x\n", | ||
| 6494 | __func__, currCal->calData->calType, chan->channel, | ||
| 6495 | chan->channelFlags); | ||
| 6496 | |||
| 6497 | ichan->CalValid &= ~currCal->calData->calType; | ||
| 6498 | currCal->calState = CAL_WAITING; | ||
| 6499 | |||
| 6500 | *isCalDone = false; | ||
| 6501 | } | ||
| 6502 | |||
| 6503 | void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac) | ||
| 6504 | { | ||
| 6505 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6506 | |||
| 6507 | memcpy(mac, ahp->ah_macaddr, ETH_ALEN); | ||
| 6508 | } | ||
| 6509 | |||
| 6510 | bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) | ||
| 6511 | { | ||
| 6512 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6513 | |||
| 6514 | memcpy(ahp->ah_macaddr, mac, ETH_ALEN); | ||
| 6515 | return true; | ||
| 6516 | } | ||
| 6517 | |||
| 6518 | void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask) | ||
| 6519 | { | ||
| 6520 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6521 | |||
| 6522 | memcpy(mask, ahp->ah_bssidmask, ETH_ALEN); | ||
| 6523 | } | ||
| 6524 | |||
| 6525 | bool | ||
| 6526 | ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) | ||
| 6527 | { | ||
| 6528 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6529 | |||
| 6530 | memcpy(ahp->ah_bssidmask, mask, ETH_ALEN); | ||
| 6531 | |||
| 6532 | REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); | ||
| 6533 | REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); | ||
| 6534 | |||
| 6535 | return true; | ||
| 6536 | } | ||
| 6537 | |||
| 6538 | #ifdef CONFIG_ATH9K_RFKILL | ||
| 6539 | static void ath9k_enable_rfkill(struct ath_hal *ah) | ||
| 6540 | { | ||
| 6541 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6542 | |||
| 6543 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
| 6544 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | ||
| 6545 | |||
| 6546 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, | ||
| 6547 | AR_GPIO_INPUT_MUX2_RFSILENT); | ||
| 6548 | |||
| 6549 | ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect); | ||
| 6550 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); | ||
| 6551 | |||
| 6552 | if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) { | ||
| 6553 | |||
| 6554 | ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect, | ||
| 6555 | !ahp->ah_gpioBit); | ||
| 6556 | } else { | ||
| 6557 | ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect, | ||
| 6558 | ahp->ah_gpioBit); | ||
| 6559 | } | ||
| 6560 | } | ||
| 6561 | #endif | ||
| 6562 | |||
| 6563 | void | ||
| 6564 | ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, | ||
| 6565 | u16 assocId) | ||
| 6566 | { | ||
| 6567 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6568 | |||
| 6569 | memcpy(ahp->ah_bssid, bssid, ETH_ALEN); | ||
| 6570 | ahp->ah_assocId = assocId; | ||
| 6571 | |||
| 6572 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); | ||
| 6573 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | | ||
| 6574 | ((assocId & 0x3fff) << AR_BSS_ID1_AID_S)); | ||
| 6575 | } | ||
| 6576 | |||
| 6577 | u64 ath9k_hw_gettsf64(struct ath_hal *ah) | ||
| 6578 | { | ||
| 6579 | u64 tsf; | ||
| 6580 | |||
| 6581 | tsf = REG_READ(ah, AR_TSF_U32); | ||
| 6582 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); | ||
| 6583 | return tsf; | ||
| 6584 | } | ||
| 6585 | |||
| 6586 | void ath9k_hw_reset_tsf(struct ath_hal *ah) | ||
| 6587 | { | ||
| 6588 | int count; | ||
| 6589 | |||
| 6590 | count = 0; | ||
| 6591 | while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { | ||
| 6592 | count++; | ||
| 6593 | if (count > 10) { | ||
| 6594 | DPRINTF(ah->ah_sc, ATH_DBG_RESET, | ||
| 6595 | "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", | ||
| 6596 | __func__); | ||
| 6597 | break; | ||
| 6598 | } | ||
| 6599 | udelay(10); | ||
| 6600 | } | ||
| 6601 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); | ||
| 6602 | } | ||
| 6603 | |||
| 6604 | u32 ath9k_hw_getdefantenna(struct ath_hal *ah) | ||
| 6605 | { | ||
| 6606 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; | ||
| 6607 | } | ||
| 6608 | |||
| 6609 | void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) | ||
| 6610 | { | ||
| 6611 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); | ||
| 6612 | } | ||
| 6613 | |||
| 6614 | bool | ||
| 6615 | ath9k_hw_setantennaswitch(struct ath_hal *ah, | ||
| 6616 | enum ath9k_ant_setting settings, | ||
| 6617 | struct ath9k_channel *chan, | ||
| 6618 | u8 *tx_chainmask, | ||
| 6619 | u8 *rx_chainmask, | ||
| 6620 | u8 *antenna_cfgd) | ||
| 6621 | { | ||
| 6622 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6623 | static u8 tx_chainmask_cfg, rx_chainmask_cfg; | ||
| 6624 | |||
| 6625 | if (AR_SREV_9280(ah)) { | ||
| 6626 | if (!tx_chainmask_cfg) { | ||
| 6627 | |||
| 6628 | tx_chainmask_cfg = *tx_chainmask; | ||
| 6629 | rx_chainmask_cfg = *rx_chainmask; | ||
| 6630 | } | ||
| 6631 | |||
| 6632 | switch (settings) { | ||
| 6633 | case ATH9K_ANT_FIXED_A: | ||
| 6634 | *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK; | ||
| 6635 | *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK; | ||
| 6636 | *antenna_cfgd = true; | ||
| 6637 | break; | ||
| 6638 | case ATH9K_ANT_FIXED_B: | ||
| 6639 | if (ah->ah_caps.tx_chainmask > | ||
| 6640 | ATH9K_ANTENNA1_CHAINMASK) { | ||
| 6641 | *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; | ||
| 6642 | } | ||
| 6643 | *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK; | ||
| 6644 | *antenna_cfgd = true; | ||
| 6645 | break; | ||
| 6646 | case ATH9K_ANT_VARIABLE: | ||
| 6647 | *tx_chainmask = tx_chainmask_cfg; | ||
| 6648 | *rx_chainmask = rx_chainmask_cfg; | ||
| 6649 | *antenna_cfgd = true; | ||
| 6650 | break; | ||
| 6651 | default: | ||
| 6652 | break; | ||
| 6653 | } | ||
| 6654 | } else { | ||
| 6655 | ahp->ah_diversityControl = settings; | ||
| 6656 | } | ||
| 6657 | |||
| 6658 | return true; | ||
| 6659 | } | ||
| 6660 | |||
| 6661 | void ath9k_hw_setopmode(struct ath_hal *ah) | ||
| 6662 | { | ||
| 6663 | ath9k_hw_set_operating_mode(ah, ah->ah_opmode); | ||
| 6664 | } | ||
| 6665 | |||
| 6666 | bool | ||
| 6667 | ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, | ||
| 6668 | u32 capability, u32 *result) | ||
| 6669 | { | ||
| 6670 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6671 | const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 6672 | |||
| 6673 | switch (type) { | ||
| 6674 | case ATH9K_CAP_CIPHER: | ||
| 6675 | switch (capability) { | ||
| 6676 | case ATH9K_CIPHER_AES_CCM: | ||
| 6677 | case ATH9K_CIPHER_AES_OCB: | ||
| 6678 | case ATH9K_CIPHER_TKIP: | ||
| 6679 | case ATH9K_CIPHER_WEP: | ||
| 6680 | case ATH9K_CIPHER_MIC: | ||
| 6681 | case ATH9K_CIPHER_CLR: | ||
| 6682 | return true; | ||
| 6683 | default: | ||
| 6684 | return false; | ||
| 6685 | } | ||
| 6686 | case ATH9K_CAP_TKIP_MIC: | ||
| 6687 | switch (capability) { | ||
| 6688 | case 0: | ||
| 6689 | return true; | ||
| 6690 | case 1: | ||
| 6691 | return (ahp->ah_staId1Defaults & | ||
| 6692 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : | ||
| 6693 | false; | ||
| 6694 | } | ||
| 6695 | case ATH9K_CAP_TKIP_SPLIT: | ||
| 6696 | return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? | ||
| 6697 | false : true; | ||
| 6698 | case ATH9K_CAP_WME_TKIPMIC: | ||
| 6699 | return 0; | ||
| 6700 | case ATH9K_CAP_PHYCOUNTERS: | ||
| 6701 | return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; | ||
| 6702 | case ATH9K_CAP_DIVERSITY: | ||
| 6703 | return (REG_READ(ah, AR_PHY_CCK_DETECT) & | ||
| 6704 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? | ||
| 6705 | true : false; | ||
| 6706 | case ATH9K_CAP_PHYDIAG: | ||
| 6707 | return true; | ||
| 6708 | case ATH9K_CAP_MCAST_KEYSRCH: | ||
| 6709 | switch (capability) { | ||
| 6710 | case 0: | ||
| 6711 | return true; | ||
| 6712 | case 1: | ||
| 6713 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { | ||
| 6714 | return false; | ||
| 6715 | } else { | ||
| 6716 | return (ahp->ah_staId1Defaults & | ||
| 6717 | AR_STA_ID1_MCAST_KSRCH) ? true : | ||
| 6718 | false; | ||
| 6719 | } | ||
| 6720 | } | ||
| 6721 | return false; | ||
| 6722 | case ATH9K_CAP_TSF_ADJUST: | ||
| 6723 | return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? | ||
| 6724 | true : false; | ||
| 6725 | case ATH9K_CAP_RFSILENT: | ||
| 6726 | if (capability == 3) | ||
| 6727 | return false; | ||
| 6728 | case ATH9K_CAP_ANT_CFG_2GHZ: | ||
| 6729 | *result = pCap->num_antcfg_2ghz; | ||
| 6730 | return true; | ||
| 6731 | case ATH9K_CAP_ANT_CFG_5GHZ: | ||
| 6732 | *result = pCap->num_antcfg_5ghz; | ||
| 6733 | return true; | ||
| 6734 | case ATH9K_CAP_TXPOW: | ||
| 6735 | switch (capability) { | ||
| 6736 | case 0: | ||
| 6737 | return 0; | ||
| 6738 | case 1: | ||
| 6739 | *result = ah->ah_powerLimit; | ||
| 6740 | return 0; | ||
| 6741 | case 2: | ||
| 6742 | *result = ah->ah_maxPowerLevel; | ||
| 6743 | return 0; | ||
| 6744 | case 3: | ||
| 6745 | *result = ah->ah_tpScale; | ||
| 6746 | return 0; | ||
| 6747 | } | ||
| 6748 | return false; | ||
| 6749 | default: | ||
| 6750 | return false; | ||
| 6751 | } | ||
| 6752 | } | ||
| 6753 | |||
| 6754 | int | ||
| 6755 | ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg) | ||
| 6756 | { | ||
| 6757 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6758 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 6759 | const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 6760 | u16 ant_config; | ||
| 6761 | u32 halNumAntConfig; | ||
| 6762 | |||
| 6763 | halNumAntConfig = | ||
| 6764 | IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap-> | ||
| 6765 | num_antcfg_5ghz; | ||
| 6766 | |||
| 6767 | if (cfg < halNumAntConfig) { | ||
| 6768 | if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, | ||
| 6769 | cfg, &ant_config)) { | ||
| 6770 | REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); | ||
| 6771 | return 0; | ||
| 6772 | } | ||
| 6773 | } | ||
| 6774 | |||
| 6775 | return -EINVAL; | ||
| 6776 | } | ||
| 6777 | |||
| 6778 | bool ath9k_hw_intrpend(struct ath_hal *ah) | ||
| 6779 | { | ||
| 6780 | u32 host_isr; | ||
| 6781 | |||
| 6782 | if (AR_SREV_9100(ah)) | ||
| 6783 | return true; | ||
| 6784 | |||
| 6785 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); | ||
| 6786 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) | ||
| 6787 | return true; | ||
| 6788 | |||
| 6789 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); | ||
| 6790 | if ((host_isr & AR_INTR_SYNC_DEFAULT) | ||
| 6791 | && (host_isr != AR_INTR_SPURIOUS)) | ||
| 6792 | return true; | ||
| 6793 | |||
| 6794 | return false; | ||
| 6795 | } | ||
| 6796 | |||
| 6797 | bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) | ||
| 6798 | { | ||
| 6799 | u32 isr = 0; | ||
| 6800 | u32 mask2 = 0; | ||
| 6801 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 6802 | u32 sync_cause = 0; | ||
| 6803 | bool fatal_int = false; | ||
| 6804 | |||
| 6805 | if (!AR_SREV_9100(ah)) { | ||
| 6806 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { | ||
| 6807 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) | ||
| 6808 | == AR_RTC_STATUS_ON) { | ||
| 6809 | isr = REG_READ(ah, AR_ISR); | ||
| 6810 | } | ||
| 6811 | } | ||
| 6812 | |||
| 6813 | sync_cause = | ||
| 6814 | REG_READ(ah, | ||
| 6815 | AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; | ||
| 6816 | |||
| 6817 | *masked = 0; | ||
| 6818 | |||
| 6819 | if (!isr && !sync_cause) | ||
| 6820 | return false; | ||
| 6821 | } else { | ||
| 6822 | *masked = 0; | ||
| 6823 | isr = REG_READ(ah, AR_ISR); | ||
| 6824 | } | ||
| 6825 | |||
| 6826 | if (isr) { | ||
| 6827 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6828 | |||
| 6829 | if (isr & AR_ISR_BCNMISC) { | ||
| 6830 | u32 isr2; | ||
| 6831 | isr2 = REG_READ(ah, AR_ISR_S2); | ||
| 6832 | if (isr2 & AR_ISR_S2_TIM) | ||
| 6833 | mask2 |= ATH9K_INT_TIM; | ||
| 6834 | if (isr2 & AR_ISR_S2_DTIM) | ||
| 6835 | mask2 |= ATH9K_INT_DTIM; | ||
| 6836 | if (isr2 & AR_ISR_S2_DTIMSYNC) | ||
| 6837 | mask2 |= ATH9K_INT_DTIMSYNC; | ||
| 6838 | if (isr2 & (AR_ISR_S2_CABEND)) | ||
| 6839 | mask2 |= ATH9K_INT_CABEND; | ||
| 6840 | if (isr2 & AR_ISR_S2_GTT) | ||
| 6841 | mask2 |= ATH9K_INT_GTT; | ||
| 6842 | if (isr2 & AR_ISR_S2_CST) | ||
| 6843 | mask2 |= ATH9K_INT_CST; | ||
| 6844 | } | ||
| 6845 | |||
| 6846 | isr = REG_READ(ah, AR_ISR_RAC); | ||
| 6847 | if (isr == 0xffffffff) { | ||
| 6848 | *masked = 0; | ||
| 6849 | return false; | ||
| 6850 | } | ||
| 6851 | |||
| 6852 | *masked = isr & ATH9K_INT_COMMON; | ||
| 6853 | |||
| 6854 | if (ahp->ah_intrMitigation) { | ||
| 6855 | |||
| 6856 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) | ||
| 6857 | *masked |= ATH9K_INT_RX; | ||
| 6858 | } | ||
| 6859 | |||
| 6860 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) | ||
| 6861 | *masked |= ATH9K_INT_RX; | ||
| 6862 | if (isr & | ||
| 6863 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | | ||
| 6864 | AR_ISR_TXEOL)) { | ||
| 6865 | u32 s0_s, s1_s; | ||
| 6866 | |||
| 6867 | *masked |= ATH9K_INT_TX; | ||
| 6868 | |||
| 6869 | s0_s = REG_READ(ah, AR_ISR_S0_S); | ||
| 6870 | ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); | ||
| 6871 | ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); | ||
| 6872 | |||
| 6873 | s1_s = REG_READ(ah, AR_ISR_S1_S); | ||
| 6874 | ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); | ||
| 6875 | ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); | ||
| 6876 | } | ||
| 6877 | |||
| 6878 | if (isr & AR_ISR_RXORN) { | ||
| 6879 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | ||
| 6880 | "%s: receive FIFO overrun interrupt\n", | ||
| 6881 | __func__); | ||
| 6882 | } | ||
| 6883 | |||
| 6884 | if (!AR_SREV_9100(ah)) { | ||
| 6885 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | ||
| 6886 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); | ||
| 6887 | if (isr5 & AR_ISR_S5_TIM_TIMER) | ||
| 6888 | *masked |= ATH9K_INT_TIM_TIMER; | ||
| 6889 | } | ||
| 6890 | } | ||
| 6891 | |||
| 6892 | *masked |= mask2; | ||
| 6893 | } | ||
| 6894 | if (AR_SREV_9100(ah)) | ||
| 6895 | return true; | ||
| 6896 | if (sync_cause) { | ||
| 6897 | fatal_int = | ||
| 6898 | (sync_cause & | ||
| 6899 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) | ||
| 6900 | ? true : false; | ||
| 6901 | |||
| 6902 | if (fatal_int) { | ||
| 6903 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | ||
| 6904 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 6905 | "%s: received PCI FATAL interrupt\n", | ||
| 6906 | __func__); | ||
| 6907 | } | ||
| 6908 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | ||
| 6909 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 6910 | "%s: received PCI PERR interrupt\n", | ||
| 6911 | __func__); | ||
| 6912 | } | ||
| 6913 | } | ||
| 6914 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | ||
| 6915 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | ||
| 6916 | "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", | ||
| 6917 | __func__); | ||
| 6918 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); | ||
| 6919 | REG_WRITE(ah, AR_RC, 0); | ||
| 6920 | *masked |= ATH9K_INT_FATAL; | ||
| 6921 | } | ||
| 6922 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | ||
| 6923 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | ||
| 6924 | "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", | ||
| 6925 | __func__); | ||
| 6926 | } | ||
| 6927 | |||
| 6928 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | ||
| 6929 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | ||
| 6930 | } | ||
| 6931 | return true; | ||
| 6932 | } | ||
| 6933 | |||
| 6934 | enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) | ||
| 6935 | { | ||
| 6936 | return AH5416(ah)->ah_maskReg; | ||
| 6937 | } | ||
| 6938 | |||
| 6939 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) | ||
| 6940 | { | ||
| 6941 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 6942 | u32 omask = ahp->ah_maskReg; | ||
| 6943 | u32 mask, mask2; | ||
| 6944 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 6945 | |||
| 6946 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, | ||
| 6947 | omask, ints); | ||
| 6948 | |||
| 6949 | if (omask & ATH9K_INT_GLOBAL) { | ||
| 6950 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n", | ||
| 6951 | __func__); | ||
| 6952 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); | ||
| 6953 | (void) REG_READ(ah, AR_IER); | ||
| 6954 | if (!AR_SREV_9100(ah)) { | ||
| 6955 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); | ||
| 6956 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); | ||
| 6957 | |||
| 6958 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | ||
| 6959 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); | ||
| 6960 | } | ||
| 6961 | } | ||
| 6962 | |||
| 6963 | mask = ints & ATH9K_INT_COMMON; | ||
| 6964 | mask2 = 0; | ||
| 6965 | |||
| 6966 | if (ints & ATH9K_INT_TX) { | ||
| 6967 | if (ahp->ah_txOkInterruptMask) | ||
| 6968 | mask |= AR_IMR_TXOK; | ||
| 6969 | if (ahp->ah_txDescInterruptMask) | ||
| 6970 | mask |= AR_IMR_TXDESC; | ||
| 6971 | if (ahp->ah_txErrInterruptMask) | ||
| 6972 | mask |= AR_IMR_TXERR; | ||
| 6973 | if (ahp->ah_txEolInterruptMask) | ||
| 6974 | mask |= AR_IMR_TXEOL; | ||
| 6975 | } | ||
| 6976 | if (ints & ATH9K_INT_RX) { | ||
| 6977 | mask |= AR_IMR_RXERR; | ||
| 6978 | if (ahp->ah_intrMitigation) | ||
| 6979 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; | ||
| 6980 | else | ||
| 6981 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; | ||
| 6982 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) | ||
| 6983 | mask |= AR_IMR_GENTMR; | ||
| 6984 | } | ||
| 6985 | |||
| 6986 | if (ints & (ATH9K_INT_BMISC)) { | ||
| 6987 | mask |= AR_IMR_BCNMISC; | ||
| 6988 | if (ints & ATH9K_INT_TIM) | ||
| 6989 | mask2 |= AR_IMR_S2_TIM; | ||
| 6990 | if (ints & ATH9K_INT_DTIM) | ||
| 6991 | mask2 |= AR_IMR_S2_DTIM; | ||
| 6992 | if (ints & ATH9K_INT_DTIMSYNC) | ||
| 6993 | mask2 |= AR_IMR_S2_DTIMSYNC; | ||
| 6994 | if (ints & ATH9K_INT_CABEND) | ||
| 6995 | mask2 |= (AR_IMR_S2_CABEND); | ||
| 6996 | } | ||
| 6997 | |||
| 6998 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { | ||
| 6999 | mask |= AR_IMR_BCNMISC; | ||
| 7000 | if (ints & ATH9K_INT_GTT) | ||
| 7001 | mask2 |= AR_IMR_S2_GTT; | ||
| 7002 | if (ints & ATH9K_INT_CST) | ||
| 7003 | mask2 |= AR_IMR_S2_CST; | ||
| 7004 | } | ||
| 7005 | |||
| 7006 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, | ||
| 7007 | mask); | ||
| 7008 | REG_WRITE(ah, AR_IMR, mask); | ||
| 7009 | mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | | ||
| 7010 | AR_IMR_S2_DTIM | | ||
| 7011 | AR_IMR_S2_DTIMSYNC | | ||
| 7012 | AR_IMR_S2_CABEND | | ||
| 7013 | AR_IMR_S2_CABTO | | ||
| 7014 | AR_IMR_S2_TSFOOR | | ||
| 7015 | AR_IMR_S2_GTT | AR_IMR_S2_CST); | ||
| 7016 | REG_WRITE(ah, AR_IMR_S2, mask | mask2); | ||
| 7017 | ahp->ah_maskReg = ints; | ||
| 7018 | |||
| 7019 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | ||
| 7020 | if (ints & ATH9K_INT_TIM_TIMER) | ||
| 7021 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | ||
| 7022 | else | ||
| 7023 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | ||
| 7024 | } | ||
| 7025 | |||
| 7026 | if (ints & ATH9K_INT_GLOBAL) { | ||
| 7027 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n", | ||
| 7028 | __func__); | ||
| 7029 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); | ||
| 7030 | if (!AR_SREV_9100(ah)) { | ||
| 7031 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, | ||
| 7032 | AR_INTR_MAC_IRQ); | ||
| 7033 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); | ||
| 7034 | |||
| 7035 | |||
| 7036 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, | ||
| 7037 | AR_INTR_SYNC_DEFAULT); | ||
| 7038 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | ||
| 7039 | AR_INTR_SYNC_DEFAULT); | ||
| 7040 | } | ||
| 7041 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", | ||
| 7042 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | ||
| 7043 | } | ||
| 7044 | |||
| 7045 | return omask; | ||
| 7046 | } | ||
| 7047 | |||
| 7048 | void | ||
| 7049 | ath9k_hw_beaconinit(struct ath_hal *ah, | ||
| 7050 | u32 next_beacon, u32 beacon_period) | ||
| 7051 | { | ||
| 7052 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7053 | int flags = 0; | ||
| 7054 | |||
| 7055 | ahp->ah_beaconInterval = beacon_period; | ||
| 7056 | |||
| 7057 | switch (ah->ah_opmode) { | ||
| 7058 | case ATH9K_M_STA: | ||
| 7059 | case ATH9K_M_MONITOR: | ||
| 7060 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); | ||
| 7061 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); | ||
| 7062 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); | ||
| 7063 | flags |= AR_TBTT_TIMER_EN; | ||
| 7064 | break; | ||
| 7065 | case ATH9K_M_IBSS: | ||
| 7066 | REG_SET_BIT(ah, AR_TXCFG, | ||
| 7067 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | ||
| 7068 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | ||
| 7069 | TU_TO_USEC(next_beacon + | ||
| 7070 | (ahp->ah_atimWindow ? ahp-> | ||
| 7071 | ah_atimWindow : 1))); | ||
| 7072 | flags |= AR_NDP_TIMER_EN; | ||
| 7073 | case ATH9K_M_HOSTAP: | ||
| 7074 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); | ||
| 7075 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | ||
| 7076 | TU_TO_USEC(next_beacon - | ||
| 7077 | ah->ah_config. | ||
| 7078 | dma_beacon_response_time)); | ||
| 7079 | REG_WRITE(ah, AR_NEXT_SWBA, | ||
| 7080 | TU_TO_USEC(next_beacon - | ||
| 7081 | ah->ah_config. | ||
| 7082 | sw_beacon_response_time)); | ||
| 7083 | flags |= | ||
| 7084 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | ||
| 7085 | break; | ||
| 7086 | } | ||
| 7087 | |||
| 7088 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | ||
| 7089 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | ||
| 7090 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | ||
| 7091 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | ||
| 7092 | |||
| 7093 | beacon_period &= ~ATH9K_BEACON_ENA; | ||
| 7094 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | ||
| 7095 | beacon_period &= ~ATH9K_BEACON_RESET_TSF; | ||
| 7096 | ath9k_hw_reset_tsf(ah); | ||
| 7097 | } | ||
| 7098 | |||
| 7099 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | ||
| 7100 | } | ||
| 7101 | |||
| 7102 | void | ||
| 7103 | ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, | ||
| 7104 | const struct ath9k_beacon_state *bs) | ||
| 7105 | { | ||
| 7106 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | ||
| 7107 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7108 | |||
| 7109 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); | ||
| 7110 | |||
| 7111 | REG_WRITE(ah, AR_BEACON_PERIOD, | ||
| 7112 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | ||
| 7113 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | ||
| 7114 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | ||
| 7115 | |||
| 7116 | REG_RMW_FIELD(ah, AR_RSSI_THR, | ||
| 7117 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | ||
| 7118 | |||
| 7119 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | ||
| 7120 | |||
| 7121 | if (bs->bs_sleepduration > beaconintval) | ||
| 7122 | beaconintval = bs->bs_sleepduration; | ||
| 7123 | |||
| 7124 | dtimperiod = bs->bs_dtimperiod; | ||
| 7125 | if (bs->bs_sleepduration > dtimperiod) | ||
| 7126 | dtimperiod = bs->bs_sleepduration; | ||
| 7127 | |||
| 7128 | if (beaconintval == dtimperiod) | ||
| 7129 | nextTbtt = bs->bs_nextdtim; | ||
| 7130 | else | ||
| 7131 | nextTbtt = bs->bs_nexttbtt; | ||
| 7132 | |||
| 7133 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__, | ||
| 7134 | bs->bs_nextdtim); | ||
| 7135 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__, | ||
| 7136 | nextTbtt); | ||
| 7137 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__, | ||
| 7138 | beaconintval); | ||
| 7139 | DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__, | ||
| 7140 | dtimperiod); | ||
| 7141 | |||
| 7142 | REG_WRITE(ah, AR_NEXT_DTIM, | ||
| 7143 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | ||
| 7144 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | ||
| 7145 | |||
| 7146 | REG_WRITE(ah, AR_SLEEP1, | ||
| 7147 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | ||
| 7148 | | AR_SLEEP1_ASSUME_DTIM); | ||
| 7149 | |||
| 7150 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) | ||
| 7151 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | ||
| 7152 | else | ||
| 7153 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | ||
| 7154 | |||
| 7155 | REG_WRITE(ah, AR_SLEEP2, | ||
| 7156 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | ||
| 7157 | |||
| 7158 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); | ||
| 7159 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | ||
| 7160 | |||
| 7161 | REG_SET_BIT(ah, AR_TIMER_MODE, | ||
| 7162 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | ||
| 7163 | AR_DTIM_TIMER_EN); | ||
| 7164 | |||
| 7165 | } | ||
| 7166 | |||
| 7167 | bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) | ||
| 7168 | { | ||
| 7169 | if (entry < ah->ah_caps.keycache_size) { | ||
| 7170 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); | ||
| 7171 | if (val & AR_KEYTABLE_VALID) | ||
| 7172 | return true; | ||
| 7173 | } | ||
| 7174 | return false; | ||
| 7175 | } | ||
| 7176 | |||
| 7177 | bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) | ||
| 7178 | { | ||
| 7179 | u32 keyType; | ||
| 7180 | |||
| 7181 | if (entry >= ah->ah_caps.keycache_size) { | ||
| 7182 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7183 | "%s: entry %u out of range\n", __func__, entry); | ||
| 7184 | return false; | ||
| 7185 | } | ||
| 7186 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); | ||
| 7187 | |||
| 7188 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); | ||
| 7189 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); | ||
| 7190 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); | ||
| 7191 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); | ||
| 7192 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); | ||
| 7193 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); | ||
| 7194 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); | ||
| 7195 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); | ||
| 7196 | |||
| 7197 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { | ||
| 7198 | u16 micentry = entry + 64; | ||
| 7199 | |||
| 7200 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); | ||
| 7201 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | ||
| 7202 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); | ||
| 7203 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | ||
| 7204 | |||
| 7205 | } | ||
| 7206 | |||
| 7207 | if (ah->ah_curchan == NULL) | ||
| 7208 | return true; | ||
| 7209 | |||
| 7210 | return true; | ||
| 7211 | } | ||
| 7212 | |||
| 7213 | bool | ||
| 7214 | ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, | ||
| 7215 | const u8 *mac) | ||
| 7216 | { | ||
| 7217 | u32 macHi, macLo; | ||
| 7218 | |||
| 7219 | if (entry >= ah->ah_caps.keycache_size) { | ||
| 7220 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7221 | "%s: entry %u out of range\n", __func__, entry); | ||
| 7222 | return false; | ||
| 7223 | } | ||
| 7224 | |||
| 7225 | if (mac != NULL) { | ||
| 7226 | macHi = (mac[5] << 8) | mac[4]; | ||
| 7227 | macLo = (mac[3] << 24) | (mac[2] << 16) | ||
| 7228 | | (mac[1] << 8) | mac[0]; | ||
| 7229 | macLo >>= 1; | ||
| 7230 | macLo |= (macHi & 1) << 31; | ||
| 7231 | macHi >>= 1; | ||
| 7232 | } else { | ||
| 7233 | macLo = macHi = 0; | ||
| 7234 | } | ||
| 7235 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); | ||
| 7236 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); | ||
| 7237 | |||
| 7238 | return true; | ||
| 7239 | } | ||
| 7240 | |||
| 7241 | bool | ||
| 7242 | ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, | ||
| 7243 | const struct ath9k_keyval *k, | ||
| 7244 | const u8 *mac, int xorKey) | ||
| 7245 | { | ||
| 7246 | const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7247 | u32 key0, key1, key2, key3, key4; | ||
| 7248 | u32 keyType; | ||
| 7249 | u32 xorMask = xorKey ? | ||
| 7250 | (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 | ||
| 7251 | | ATH9K_KEY_XOR) : 0; | ||
| 7252 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7253 | |||
| 7254 | if (entry >= pCap->keycache_size) { | ||
| 7255 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7256 | "%s: entry %u out of range\n", __func__, entry); | ||
| 7257 | return false; | ||
| 7258 | } | ||
| 7259 | switch (k->kv_type) { | ||
| 7260 | case ATH9K_CIPHER_AES_OCB: | ||
| 7261 | keyType = AR_KEYTABLE_TYPE_AES; | ||
| 7262 | break; | ||
| 7263 | case ATH9K_CIPHER_AES_CCM: | ||
| 7264 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { | ||
| 7265 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7266 | "%s: AES-CCM not supported by " | ||
| 7267 | "mac rev 0x%x\n", __func__, | ||
| 7268 | ah->ah_macRev); | ||
| 7269 | return false; | ||
| 7270 | } | ||
| 7271 | keyType = AR_KEYTABLE_TYPE_CCM; | ||
| 7272 | break; | ||
| 7273 | case ATH9K_CIPHER_TKIP: | ||
| 7274 | keyType = AR_KEYTABLE_TYPE_TKIP; | ||
| 7275 | if (ATH9K_IS_MIC_ENABLED(ah) | ||
| 7276 | && entry + 64 >= pCap->keycache_size) { | ||
| 7277 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7278 | "%s: entry %u inappropriate for TKIP\n", | ||
| 7279 | __func__, entry); | ||
| 7280 | return false; | ||
| 7281 | } | ||
| 7282 | break; | ||
| 7283 | case ATH9K_CIPHER_WEP: | ||
| 7284 | if (k->kv_len < 40 / NBBY) { | ||
| 7285 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7286 | "%s: WEP key length %u too small\n", | ||
| 7287 | __func__, k->kv_len); | ||
| 7288 | return false; | ||
| 7289 | } | ||
| 7290 | if (k->kv_len <= 40 / NBBY) | ||
| 7291 | keyType = AR_KEYTABLE_TYPE_40; | ||
| 7292 | else if (k->kv_len <= 104 / NBBY) | ||
| 7293 | keyType = AR_KEYTABLE_TYPE_104; | ||
| 7294 | else | ||
| 7295 | keyType = AR_KEYTABLE_TYPE_128; | ||
| 7296 | break; | ||
| 7297 | case ATH9K_CIPHER_CLR: | ||
| 7298 | keyType = AR_KEYTABLE_TYPE_CLR; | ||
| 7299 | break; | ||
| 7300 | default: | ||
| 7301 | DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, | ||
| 7302 | "%s: cipher %u not supported\n", __func__, | ||
| 7303 | k->kv_type); | ||
| 7304 | return false; | ||
| 7305 | } | ||
| 7306 | |||
| 7307 | key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask; | ||
| 7308 | key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff; | ||
| 7309 | key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask; | ||
| 7310 | key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff; | ||
| 7311 | key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask; | ||
| 7312 | if (k->kv_len <= 104 / NBBY) | ||
| 7313 | key4 &= 0xff; | ||
| 7314 | |||
| 7315 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { | ||
| 7316 | u16 micentry = entry + 64; | ||
| 7317 | |||
| 7318 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); | ||
| 7319 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); | ||
| 7320 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); | ||
| 7321 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | ||
| 7322 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); | ||
| 7323 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | ||
| 7324 | (void) ath9k_hw_keysetmac(ah, entry, mac); | ||
| 7325 | |||
| 7326 | if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { | ||
| 7327 | u32 mic0, mic1, mic2, mic3, mic4; | ||
| 7328 | |||
| 7329 | mic0 = get_unaligned_le32(k->kv_mic + 0); | ||
| 7330 | mic2 = get_unaligned_le32(k->kv_mic + 4); | ||
| 7331 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; | ||
| 7332 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; | ||
| 7333 | mic4 = get_unaligned_le32(k->kv_txmic + 4); | ||
| 7334 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); | ||
| 7335 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); | ||
| 7336 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); | ||
| 7337 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); | ||
| 7338 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); | ||
| 7339 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | ||
| 7340 | AR_KEYTABLE_TYPE_CLR); | ||
| 7341 | |||
| 7342 | } else { | ||
| 7343 | u32 mic0, mic2; | ||
| 7344 | |||
| 7345 | mic0 = get_unaligned_le32(k->kv_mic + 0); | ||
| 7346 | mic2 = get_unaligned_le32(k->kv_mic + 4); | ||
| 7347 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); | ||
| 7348 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | ||
| 7349 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); | ||
| 7350 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | ||
| 7351 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); | ||
| 7352 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | ||
| 7353 | AR_KEYTABLE_TYPE_CLR); | ||
| 7354 | } | ||
| 7355 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); | ||
| 7356 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); | ||
| 7357 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); | ||
| 7358 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | ||
| 7359 | } else { | ||
| 7360 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); | ||
| 7361 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | ||
| 7362 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); | ||
| 7363 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | ||
| 7364 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); | ||
| 7365 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | ||
| 7366 | |||
| 7367 | (void) ath9k_hw_keysetmac(ah, entry, mac); | ||
| 7368 | } | ||
| 7369 | |||
| 7370 | if (ah->ah_curchan == NULL) | ||
| 7371 | return true; | ||
| 7372 | |||
| 7373 | return true; | ||
| 7374 | } | ||
| 7375 | |||
| 7376 | bool | ||
| 7377 | ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) | ||
| 7378 | { | ||
| 7379 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7380 | u32 txcfg, curLevel, newLevel; | ||
| 7381 | enum ath9k_int omask; | ||
| 7382 | |||
| 7383 | if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) | ||
| 7384 | return false; | ||
| 7385 | |||
| 7386 | omask = ath9k_hw_set_interrupts(ah, | ||
| 7387 | ahp->ah_maskReg & ~ATH9K_INT_GLOBAL); | ||
| 7388 | |||
| 7389 | txcfg = REG_READ(ah, AR_TXCFG); | ||
| 7390 | curLevel = MS(txcfg, AR_FTRIG); | ||
| 7391 | newLevel = curLevel; | ||
| 7392 | if (bIncTrigLevel) { | ||
| 7393 | if (curLevel < MAX_TX_FIFO_THRESHOLD) | ||
| 7394 | newLevel++; | ||
| 7395 | } else if (curLevel > MIN_TX_FIFO_THRESHOLD) | ||
| 7396 | newLevel--; | ||
| 7397 | if (newLevel != curLevel) | ||
| 7398 | REG_WRITE(ah, AR_TXCFG, | ||
| 7399 | (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); | ||
| 7400 | |||
| 7401 | ath9k_hw_set_interrupts(ah, omask); | ||
| 7402 | |||
| 7403 | ah->ah_txTrigLevel = newLevel; | ||
| 7404 | |||
| 7405 | return newLevel != curLevel; | ||
| 7406 | } | ||
| 7407 | |||
| 7408 | bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, | ||
| 7409 | const struct ath9k_tx_queue_info *qinfo) | ||
| 7410 | { | ||
| 7411 | u32 cw; | ||
| 7412 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7413 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7414 | struct ath9k_tx_queue_info *qi; | ||
| 7415 | |||
| 7416 | if (q >= pCap->total_queues) { | ||
| 7417 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | ||
| 7418 | __func__, q); | ||
| 7419 | return false; | ||
| 7420 | } | ||
| 7421 | |||
| 7422 | qi = &ahp->ah_txq[q]; | ||
| 7423 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | ||
| 7424 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", | ||
| 7425 | __func__); | ||
| 7426 | return false; | ||
| 7427 | } | ||
| 7428 | |||
| 7429 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); | ||
| 7430 | |||
| 7431 | qi->tqi_ver = qinfo->tqi_ver; | ||
| 7432 | qi->tqi_subtype = qinfo->tqi_subtype; | ||
| 7433 | qi->tqi_qflags = qinfo->tqi_qflags; | ||
| 7434 | qi->tqi_priority = qinfo->tqi_priority; | ||
| 7435 | if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT) | ||
| 7436 | qi->tqi_aifs = min(qinfo->tqi_aifs, 255U); | ||
| 7437 | else | ||
| 7438 | qi->tqi_aifs = INIT_AIFS; | ||
| 7439 | if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) { | ||
| 7440 | cw = min(qinfo->tqi_cwmin, 1024U); | ||
| 7441 | qi->tqi_cwmin = 1; | ||
| 7442 | while (qi->tqi_cwmin < cw) | ||
| 7443 | qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1; | ||
| 7444 | } else | ||
| 7445 | qi->tqi_cwmin = qinfo->tqi_cwmin; | ||
| 7446 | if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) { | ||
| 7447 | cw = min(qinfo->tqi_cwmax, 1024U); | ||
| 7448 | qi->tqi_cwmax = 1; | ||
| 7449 | while (qi->tqi_cwmax < cw) | ||
| 7450 | qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1; | ||
| 7451 | } else | ||
| 7452 | qi->tqi_cwmax = INIT_CWMAX; | ||
| 7453 | |||
| 7454 | if (qinfo->tqi_shretry != 0) | ||
| 7455 | qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); | ||
| 7456 | else | ||
| 7457 | qi->tqi_shretry = INIT_SH_RETRY; | ||
| 7458 | if (qinfo->tqi_lgretry != 0) | ||
| 7459 | qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); | ||
| 7460 | else | ||
| 7461 | qi->tqi_lgretry = INIT_LG_RETRY; | ||
| 7462 | qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod; | ||
| 7463 | qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit; | ||
| 7464 | qi->tqi_burstTime = qinfo->tqi_burstTime; | ||
| 7465 | qi->tqi_readyTime = qinfo->tqi_readyTime; | ||
| 7466 | |||
| 7467 | switch (qinfo->tqi_subtype) { | ||
| 7468 | case ATH9K_WME_UPSD: | ||
| 7469 | if (qi->tqi_type == ATH9K_TX_QUEUE_DATA) | ||
| 7470 | qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS; | ||
| 7471 | break; | ||
| 7472 | default: | ||
| 7473 | break; | ||
| 7474 | } | ||
| 7475 | return true; | ||
| 7476 | } | ||
| 7477 | |||
| 7478 | bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, | ||
| 7479 | struct ath9k_tx_queue_info *qinfo) | ||
| 7480 | { | ||
| 7481 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7482 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7483 | struct ath9k_tx_queue_info *qi; | ||
| 7484 | |||
| 7485 | if (q >= pCap->total_queues) { | ||
| 7486 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | ||
| 7487 | __func__, q); | ||
| 7488 | return false; | ||
| 7489 | } | ||
| 7490 | |||
| 7491 | qi = &ahp->ah_txq[q]; | ||
| 7492 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | ||
| 7493 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", | ||
| 7494 | __func__); | ||
| 7495 | return false; | ||
| 7496 | } | ||
| 7497 | |||
| 7498 | qinfo->tqi_qflags = qi->tqi_qflags; | ||
| 7499 | qinfo->tqi_ver = qi->tqi_ver; | ||
| 7500 | qinfo->tqi_subtype = qi->tqi_subtype; | ||
| 7501 | qinfo->tqi_qflags = qi->tqi_qflags; | ||
| 7502 | qinfo->tqi_priority = qi->tqi_priority; | ||
| 7503 | qinfo->tqi_aifs = qi->tqi_aifs; | ||
| 7504 | qinfo->tqi_cwmin = qi->tqi_cwmin; | ||
| 7505 | qinfo->tqi_cwmax = qi->tqi_cwmax; | ||
| 7506 | qinfo->tqi_shretry = qi->tqi_shretry; | ||
| 7507 | qinfo->tqi_lgretry = qi->tqi_lgretry; | ||
| 7508 | qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod; | ||
| 7509 | qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit; | ||
| 7510 | qinfo->tqi_burstTime = qi->tqi_burstTime; | ||
| 7511 | qinfo->tqi_readyTime = qi->tqi_readyTime; | ||
| 7512 | |||
| 7513 | return true; | ||
| 7514 | } | ||
| 7515 | |||
| 7516 | int | ||
| 7517 | ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, | ||
| 7518 | const struct ath9k_tx_queue_info *qinfo) | ||
| 7519 | { | ||
| 7520 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7521 | struct ath9k_tx_queue_info *qi; | ||
| 7522 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7523 | int q; | ||
| 7524 | |||
| 7525 | switch (type) { | ||
| 7526 | case ATH9K_TX_QUEUE_BEACON: | ||
| 7527 | q = pCap->total_queues - 1; | ||
| 7528 | break; | ||
| 7529 | case ATH9K_TX_QUEUE_CAB: | ||
| 7530 | q = pCap->total_queues - 2; | ||
| 7531 | break; | ||
| 7532 | case ATH9K_TX_QUEUE_PSPOLL: | ||
| 7533 | q = 1; | ||
| 7534 | break; | ||
| 7535 | case ATH9K_TX_QUEUE_UAPSD: | ||
| 7536 | q = pCap->total_queues - 3; | ||
| 7537 | break; | ||
| 7538 | case ATH9K_TX_QUEUE_DATA: | ||
| 7539 | for (q = 0; q < pCap->total_queues; q++) | ||
| 7540 | if (ahp->ah_txq[q].tqi_type == | ||
| 7541 | ATH9K_TX_QUEUE_INACTIVE) | ||
| 7542 | break; | ||
| 7543 | if (q == pCap->total_queues) { | ||
| 7544 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | ||
| 7545 | "%s: no available tx queue\n", __func__); | ||
| 7546 | return -1; | ||
| 7547 | } | ||
| 7548 | break; | ||
| 7549 | default: | ||
| 7550 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n", | ||
| 7551 | __func__, type); | ||
| 7552 | return -1; | ||
| 7553 | } | ||
| 7554 | |||
| 7555 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); | ||
| 7556 | |||
| 7557 | qi = &ahp->ah_txq[q]; | ||
| 7558 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { | ||
| 7559 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | ||
| 7560 | "%s: tx queue %u already active\n", __func__, q); | ||
| 7561 | return -1; | ||
| 7562 | } | ||
| 7563 | memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); | ||
| 7564 | qi->tqi_type = type; | ||
| 7565 | if (qinfo == NULL) { | ||
| 7566 | qi->tqi_qflags = | ||
| 7567 | TXQ_FLAG_TXOKINT_ENABLE | ||
| 7568 | | TXQ_FLAG_TXERRINT_ENABLE | ||
| 7569 | | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE; | ||
| 7570 | qi->tqi_aifs = INIT_AIFS; | ||
| 7571 | qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | ||
| 7572 | qi->tqi_cwmax = INIT_CWMAX; | ||
| 7573 | qi->tqi_shretry = INIT_SH_RETRY; | ||
| 7574 | qi->tqi_lgretry = INIT_LG_RETRY; | ||
| 7575 | qi->tqi_physCompBuf = 0; | ||
| 7576 | } else { | ||
| 7577 | qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; | ||
| 7578 | (void) ath9k_hw_set_txq_props(ah, q, qinfo); | ||
| 7579 | } | ||
| 7580 | |||
| 7581 | return q; | ||
| 7582 | } | ||
| 7583 | |||
| 7584 | static void | ||
| 7585 | ath9k_hw_set_txq_interrupts(struct ath_hal *ah, | ||
| 7586 | struct ath9k_tx_queue_info *qi) | ||
| 7587 | { | ||
| 7588 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7589 | |||
| 7590 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | ||
| 7591 | "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", | ||
| 7592 | __func__, ahp->ah_txOkInterruptMask, | ||
| 7593 | ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask, | ||
| 7594 | ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask); | ||
| 7595 | |||
| 7596 | REG_WRITE(ah, AR_IMR_S0, | ||
| 7597 | SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) | ||
| 7598 | | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); | ||
| 7599 | REG_WRITE(ah, AR_IMR_S1, | ||
| 7600 | SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) | ||
| 7601 | | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); | ||
| 7602 | REG_RMW_FIELD(ah, AR_IMR_S2, | ||
| 7603 | AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); | ||
| 7604 | } | ||
| 7605 | |||
| 7606 | bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) | ||
| 7607 | { | ||
| 7608 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7609 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7610 | struct ath9k_tx_queue_info *qi; | ||
| 7611 | |||
| 7612 | if (q >= pCap->total_queues) { | ||
| 7613 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | ||
| 7614 | __func__, q); | ||
| 7615 | return false; | ||
| 7616 | } | ||
| 7617 | qi = &ahp->ah_txq[q]; | ||
| 7618 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | ||
| 7619 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", | ||
| 7620 | __func__, q); | ||
| 7621 | return false; | ||
| 7622 | } | ||
| 7623 | |||
| 7624 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n", | ||
| 7625 | __func__, q); | ||
| 7626 | |||
| 7627 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; | ||
| 7628 | ahp->ah_txOkInterruptMask &= ~(1 << q); | ||
| 7629 | ahp->ah_txErrInterruptMask &= ~(1 << q); | ||
| 7630 | ahp->ah_txDescInterruptMask &= ~(1 << q); | ||
| 7631 | ahp->ah_txEolInterruptMask &= ~(1 << q); | ||
| 7632 | ahp->ah_txUrnInterruptMask &= ~(1 << q); | ||
| 7633 | ath9k_hw_set_txq_interrupts(ah, qi); | ||
| 7634 | |||
| 7635 | return true; | ||
| 7636 | } | ||
| 7637 | |||
| 7638 | bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) | ||
| 7639 | { | ||
| 7640 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7641 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 7642 | struct ath9k_channel *chan = ah->ah_curchan; | ||
| 7643 | struct ath9k_tx_queue_info *qi; | ||
| 7644 | u32 cwMin, chanCwMin, value; | ||
| 7645 | |||
| 7646 | if (q >= pCap->total_queues) { | ||
| 7647 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | ||
| 7648 | __func__, q); | ||
| 7649 | return false; | ||
| 7650 | } | ||
| 7651 | qi = &ahp->ah_txq[q]; | ||
| 7652 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | ||
| 7653 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", | ||
| 7654 | __func__, q); | ||
| 7655 | return true; | ||
| 7656 | } | ||
| 7657 | |||
| 7658 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); | ||
| 7659 | |||
| 7660 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { | ||
| 7661 | if (chan && IS_CHAN_B(chan)) | ||
| 7662 | chanCwMin = INIT_CWMIN_11B; | ||
| 7663 | else | ||
| 7664 | chanCwMin = INIT_CWMIN; | ||
| 7665 | |||
| 7666 | for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); | ||
| 7667 | } else | ||
| 7668 | cwMin = qi->tqi_cwmin; | ||
| 7669 | |||
| 7670 | REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN) | ||
| 7671 | | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | ||
| 7672 | | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); | ||
| 7673 | |||
| 7674 | REG_WRITE(ah, AR_DRETRY_LIMIT(q), | ||
| 7675 | SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | ||
| 7676 | | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | ||
| 7677 | | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH) | ||
| 7678 | ); | ||
| 7679 | |||
| 7680 | REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); | ||
| 7681 | REG_WRITE(ah, AR_DMISC(q), | ||
| 7682 | AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); | ||
| 7683 | |||
| 7684 | if (qi->tqi_cbrPeriod) { | ||
| 7685 | REG_WRITE(ah, AR_QCBRCFG(q), | ||
| 7686 | SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | ||
| 7687 | | SM(qi->tqi_cbrOverflowLimit, | ||
| 7688 | AR_Q_CBRCFG_OVF_THRESH)); | ||
| 7689 | REG_WRITE(ah, AR_QMISC(q), | ||
| 7690 | REG_READ(ah, | ||
| 7691 | AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi-> | ||
| 7692 | tqi_cbrOverflowLimit | ||
| 7693 | ? | ||
| 7694 | AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN | ||
| 7695 | : | ||
| 7696 | 0)); | ||
| 7697 | } | ||
| 7698 | if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { | ||
| 7699 | REG_WRITE(ah, AR_QRDYTIMECFG(q), | ||
| 7700 | SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | | ||
| 7701 | AR_Q_RDYTIMECFG_EN); | ||
| 7702 | } | ||
| 7703 | |||
| 7704 | REG_WRITE(ah, AR_DCHNTIME(q), | ||
| 7705 | SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | | ||
| 7706 | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); | ||
| 7707 | |||
| 7708 | if (qi->tqi_burstTime | ||
| 7709 | && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) { | ||
| 7710 | REG_WRITE(ah, AR_QMISC(q), | ||
| 7711 | REG_READ(ah, | ||
| 7712 | AR_QMISC(q)) | | ||
| 7713 | AR_Q_MISC_RDYTIME_EXP_POLICY); | ||
| 7714 | |||
| 7715 | } | ||
| 7716 | |||
| 7717 | if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) { | ||
| 7718 | REG_WRITE(ah, AR_DMISC(q), | ||
| 7719 | REG_READ(ah, AR_DMISC(q)) | | ||
| 7720 | AR_D_MISC_POST_FR_BKOFF_DIS); | ||
| 7721 | } | ||
| 7722 | if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { | ||
| 7723 | REG_WRITE(ah, AR_DMISC(q), | ||
| 7724 | REG_READ(ah, AR_DMISC(q)) | | ||
| 7725 | AR_D_MISC_FRAG_BKOFF_EN); | ||
| 7726 | } | ||
| 7727 | switch (qi->tqi_type) { | ||
| 7728 | case ATH9K_TX_QUEUE_BEACON: | ||
| 7729 | REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) | ||
| 7730 | | AR_Q_MISC_FSP_DBA_GATED | ||
| 7731 | | AR_Q_MISC_BEACON_USE | ||
| 7732 | | AR_Q_MISC_CBR_INCR_DIS1); | ||
| 7733 | |||
| 7734 | REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) | ||
| 7735 | | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << | ||
| 7736 | AR_D_MISC_ARB_LOCKOUT_CNTRL_S) | ||
| 7737 | | AR_D_MISC_BEACON_USE | ||
| 7738 | | AR_D_MISC_POST_FR_BKOFF_DIS); | ||
| 7739 | break; | ||
| 7740 | case ATH9K_TX_QUEUE_CAB: | ||
| 7741 | REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) | ||
| 7742 | | AR_Q_MISC_FSP_DBA_GATED | ||
| 7743 | | AR_Q_MISC_CBR_INCR_DIS1 | ||
| 7744 | | AR_Q_MISC_CBR_INCR_DIS0); | ||
| 7745 | value = (qi->tqi_readyTime | ||
| 7746 | - (ah->ah_config.sw_beacon_response_time - | ||
| 7747 | ah->ah_config.dma_beacon_response_time) | ||
| 7748 | - | ||
| 7749 | ah->ah_config.additional_swba_backoff) * | ||
| 7750 | 1024; | ||
| 7751 | REG_WRITE(ah, AR_QRDYTIMECFG(q), | ||
| 7752 | value | AR_Q_RDYTIMECFG_EN); | ||
| 7753 | REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) | ||
| 7754 | | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << | ||
| 7755 | AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); | ||
| 7756 | break; | ||
| 7757 | case ATH9K_TX_QUEUE_PSPOLL: | ||
| 7758 | REG_WRITE(ah, AR_QMISC(q), | ||
| 7759 | REG_READ(ah, | ||
| 7760 | AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1); | ||
| 7761 | break; | ||
| 7762 | case ATH9K_TX_QUEUE_UAPSD: | ||
| 7763 | REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) | ||
| 7764 | | AR_D_MISC_POST_FR_BKOFF_DIS); | ||
| 7765 | break; | ||
| 7766 | default: | ||
| 7767 | break; | ||
| 7768 | } | ||
| 7769 | |||
| 7770 | if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { | ||
| 7771 | REG_WRITE(ah, AR_DMISC(q), | ||
| 7772 | REG_READ(ah, AR_DMISC(q)) | | ||
| 7773 | SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, | ||
| 7774 | AR_D_MISC_ARB_LOCKOUT_CNTRL) | | ||
| 7775 | AR_D_MISC_POST_FR_BKOFF_DIS); | ||
| 7776 | } | ||
| 7777 | |||
| 7778 | if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) | ||
| 7779 | ahp->ah_txOkInterruptMask |= 1 << q; | ||
| 7780 | else | ||
| 7781 | ahp->ah_txOkInterruptMask &= ~(1 << q); | ||
| 7782 | if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) | ||
| 7783 | ahp->ah_txErrInterruptMask |= 1 << q; | ||
| 7784 | else | ||
| 7785 | ahp->ah_txErrInterruptMask &= ~(1 << q); | ||
| 7786 | if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) | ||
| 7787 | ahp->ah_txDescInterruptMask |= 1 << q; | ||
| 7788 | else | ||
| 7789 | ahp->ah_txDescInterruptMask &= ~(1 << q); | ||
| 7790 | if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) | ||
| 7791 | ahp->ah_txEolInterruptMask |= 1 << q; | ||
| 7792 | else | ||
| 7793 | ahp->ah_txEolInterruptMask &= ~(1 << q); | ||
| 7794 | if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) | ||
| 7795 | ahp->ah_txUrnInterruptMask |= 1 << q; | ||
| 7796 | else | ||
| 7797 | ahp->ah_txUrnInterruptMask &= ~(1 << q); | ||
| 7798 | ath9k_hw_set_txq_interrupts(ah, qi); | ||
| 7799 | |||
| 7800 | return true; | ||
| 7801 | } | ||
| 7802 | |||
| 7803 | void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs) | ||
| 7804 | { | ||
| 7805 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7806 | *txqs &= ahp->ah_intrTxqs; | ||
| 7807 | ahp->ah_intrTxqs &= ~(*txqs); | ||
| 7808 | } | ||
| 7809 | |||
| 7810 | bool | ||
| 7811 | ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 7812 | u32 segLen, bool firstSeg, | ||
| 7813 | bool lastSeg, const struct ath_desc *ds0) | ||
| 7814 | { | ||
| 7815 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 7816 | |||
| 7817 | if (firstSeg) { | ||
| 7818 | ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore); | ||
| 7819 | } else if (lastSeg) { | ||
| 7820 | ads->ds_ctl0 = 0; | ||
| 7821 | ads->ds_ctl1 = segLen; | ||
| 7822 | ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; | ||
| 7823 | ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; | ||
| 7824 | } else { | ||
| 7825 | ads->ds_ctl0 = 0; | ||
| 7826 | ads->ds_ctl1 = segLen | AR_TxMore; | ||
| 7827 | ads->ds_ctl2 = 0; | ||
| 7828 | ads->ds_ctl3 = 0; | ||
| 7829 | } | ||
| 7830 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; | ||
| 7831 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; | ||
| 7832 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; | ||
| 7833 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; | ||
| 7834 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; | ||
| 7835 | return true; | ||
| 7836 | } | ||
| 7837 | |||
| 7838 | void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) | ||
| 7839 | { | ||
| 7840 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 7841 | |||
| 7842 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; | ||
| 7843 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; | ||
| 7844 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; | ||
| 7845 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; | ||
| 7846 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; | ||
| 7847 | } | ||
| 7848 | |||
| 7849 | int | ||
| 7850 | ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds) | ||
| 7851 | { | ||
| 7852 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 7853 | |||
| 7854 | if ((ads->ds_txstatus9 & AR_TxDone) == 0) | ||
| 7855 | return -EINPROGRESS; | ||
| 7856 | |||
| 7857 | ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum); | ||
| 7858 | ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp; | ||
| 7859 | ds->ds_txstat.ts_status = 0; | ||
| 7860 | ds->ds_txstat.ts_flags = 0; | ||
| 7861 | |||
| 7862 | if (ads->ds_txstatus1 & AR_ExcessiveRetries) | ||
| 7863 | ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY; | ||
| 7864 | if (ads->ds_txstatus1 & AR_Filtered) | ||
| 7865 | ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT; | ||
| 7866 | if (ads->ds_txstatus1 & AR_FIFOUnderrun) | ||
| 7867 | ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO; | ||
| 7868 | if (ads->ds_txstatus9 & AR_TxOpExceeded) | ||
| 7869 | ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP; | ||
| 7870 | if (ads->ds_txstatus1 & AR_TxTimerExpired) | ||
| 7871 | ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED; | ||
| 7872 | |||
| 7873 | if (ads->ds_txstatus1 & AR_DescCfgErr) | ||
| 7874 | ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR; | ||
| 7875 | if (ads->ds_txstatus1 & AR_TxDataUnderrun) { | ||
| 7876 | ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN; | ||
| 7877 | ath9k_hw_updatetxtriglevel(ah, true); | ||
| 7878 | } | ||
| 7879 | if (ads->ds_txstatus1 & AR_TxDelimUnderrun) { | ||
| 7880 | ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN; | ||
| 7881 | ath9k_hw_updatetxtriglevel(ah, true); | ||
| 7882 | } | ||
| 7883 | if (ads->ds_txstatus0 & AR_TxBaStatus) { | ||
| 7884 | ds->ds_txstat.ts_flags |= ATH9K_TX_BA; | ||
| 7885 | ds->ds_txstat.ba_low = ads->AR_BaBitmapLow; | ||
| 7886 | ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh; | ||
| 7887 | } | ||
| 7888 | |||
| 7889 | ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx); | ||
| 7890 | switch (ds->ds_txstat.ts_rateindex) { | ||
| 7891 | case 0: | ||
| 7892 | ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0); | ||
| 7893 | break; | ||
| 7894 | case 1: | ||
| 7895 | ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1); | ||
| 7896 | break; | ||
| 7897 | case 2: | ||
| 7898 | ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2); | ||
| 7899 | break; | ||
| 7900 | case 3: | ||
| 7901 | ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3); | ||
| 7902 | break; | ||
| 7903 | } | ||
| 7904 | |||
| 7905 | ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined); | ||
| 7906 | ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00); | ||
| 7907 | ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01); | ||
| 7908 | ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02); | ||
| 7909 | ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10); | ||
| 7910 | ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11); | ||
| 7911 | ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12); | ||
| 7912 | ds->ds_txstat.evm0 = ads->AR_TxEVM0; | ||
| 7913 | ds->ds_txstat.evm1 = ads->AR_TxEVM1; | ||
| 7914 | ds->ds_txstat.evm2 = ads->AR_TxEVM2; | ||
| 7915 | ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt); | ||
| 7916 | ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt); | ||
| 7917 | ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt); | ||
| 7918 | ds->ds_txstat.ts_antenna = 1; | ||
| 7919 | |||
| 7920 | return 0; | ||
| 7921 | } | ||
| 7922 | |||
| 7923 | void | ||
| 7924 | ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 7925 | u32 pktLen, enum ath9k_pkt_type type, u32 txPower, | ||
| 7926 | u32 keyIx, enum ath9k_key_type keyType, u32 flags) | ||
| 7927 | { | ||
| 7928 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 7929 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 7930 | |||
| 7931 | txPower += ahp->ah_txPowerIndexOffset; | ||
| 7932 | if (txPower > 63) | ||
| 7933 | txPower = 63; | ||
| 7934 | |||
| 7935 | ads->ds_ctl0 = (pktLen & AR_FrameLen) | ||
| 7936 | | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | ||
| 7937 | | SM(txPower, AR_XmitPower) | ||
| 7938 | | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | ||
| 7939 | | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) | ||
| 7940 | | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) | ||
| 7941 | | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0); | ||
| 7942 | |||
| 7943 | ads->ds_ctl1 = | ||
| 7944 | (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) | ||
| 7945 | | SM(type, AR_FrameType) | ||
| 7946 | | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | ||
| 7947 | | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | ||
| 7948 | | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | ||
| 7949 | |||
| 7950 | ads->ds_ctl6 = SM(keyType, AR_EncrType); | ||
| 7951 | |||
| 7952 | if (AR_SREV_9285(ah)) { | ||
| 7953 | |||
| 7954 | ads->ds_ctl8 = 0; | ||
| 7955 | ads->ds_ctl9 = 0; | ||
| 7956 | ads->ds_ctl10 = 0; | ||
| 7957 | ads->ds_ctl11 = 0; | ||
| 7958 | } | ||
| 7959 | } | ||
| 7960 | |||
| 7961 | void | ||
| 7962 | ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, | ||
| 7963 | struct ath_desc *lastds, | ||
| 7964 | u32 durUpdateEn, u32 rtsctsRate, | ||
| 7965 | u32 rtsctsDuration, | ||
| 7966 | struct ath9k_11n_rate_series series[], | ||
| 7967 | u32 nseries, u32 flags) | ||
| 7968 | { | ||
| 7969 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 7970 | struct ar5416_desc *last_ads = AR5416DESC(lastds); | ||
| 7971 | u32 ds_ctl0; | ||
| 7972 | |||
| 7973 | (void) nseries; | ||
| 7974 | (void) rtsctsDuration; | ||
| 7975 | |||
| 7976 | if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { | ||
| 7977 | ds_ctl0 = ads->ds_ctl0; | ||
| 7978 | |||
| 7979 | if (flags & ATH9K_TXDESC_RTSENA) { | ||
| 7980 | ds_ctl0 &= ~AR_CTSEnable; | ||
| 7981 | ds_ctl0 |= AR_RTSEnable; | ||
| 7982 | } else { | ||
| 7983 | ds_ctl0 &= ~AR_RTSEnable; | ||
| 7984 | ds_ctl0 |= AR_CTSEnable; | ||
| 7985 | } | ||
| 7986 | |||
| 7987 | ads->ds_ctl0 = ds_ctl0; | ||
| 7988 | } else { | ||
| 7989 | ads->ds_ctl0 = | ||
| 7990 | (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); | ||
| 7991 | } | ||
| 7992 | |||
| 7993 | ads->ds_ctl2 = set11nTries(series, 0) | ||
| 7994 | | set11nTries(series, 1) | ||
| 7995 | | set11nTries(series, 2) | ||
| 7996 | | set11nTries(series, 3) | ||
| 7997 | | (durUpdateEn ? AR_DurUpdateEna : 0) | ||
| 7998 | | SM(0, AR_BurstDur); | ||
| 7999 | |||
| 8000 | ads->ds_ctl3 = set11nRate(series, 0) | ||
| 8001 | | set11nRate(series, 1) | ||
| 8002 | | set11nRate(series, 2) | ||
| 8003 | | set11nRate(series, 3); | ||
| 8004 | |||
| 8005 | ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) | ||
| 8006 | | set11nPktDurRTSCTS(series, 1); | ||
| 8007 | |||
| 8008 | ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) | ||
| 8009 | | set11nPktDurRTSCTS(series, 3); | ||
| 8010 | |||
| 8011 | ads->ds_ctl7 = set11nRateFlags(series, 0) | ||
| 8012 | | set11nRateFlags(series, 1) | ||
| 8013 | | set11nRateFlags(series, 2) | ||
| 8014 | | set11nRateFlags(series, 3) | ||
| 8015 | | SM(rtsctsRate, AR_RTSCTSRate); | ||
| 8016 | last_ads->ds_ctl2 = ads->ds_ctl2; | ||
| 8017 | last_ads->ds_ctl3 = ads->ds_ctl3; | ||
| 8018 | } | ||
| 8019 | |||
| 8020 | void | ||
| 8021 | ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, | ||
| 8022 | u32 aggrLen) | ||
| 8023 | { | ||
| 8024 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8025 | |||
| 8026 | ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); | ||
| 8027 | |||
| 8028 | ads->ds_ctl6 &= ~AR_AggrLen; | ||
| 8029 | ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); | ||
| 8030 | } | ||
| 8031 | |||
| 8032 | void | ||
| 8033 | ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, | ||
| 8034 | u32 numDelims) | ||
| 8035 | { | ||
| 8036 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8037 | unsigned int ctl6; | ||
| 8038 | |||
| 8039 | ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); | ||
| 8040 | |||
| 8041 | ctl6 = ads->ds_ctl6; | ||
| 8042 | ctl6 &= ~AR_PadDelim; | ||
| 8043 | ctl6 |= SM(numDelims, AR_PadDelim); | ||
| 8044 | ads->ds_ctl6 = ctl6; | ||
| 8045 | } | ||
| 8046 | |||
| 8047 | void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) | ||
| 8048 | { | ||
| 8049 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8050 | |||
| 8051 | ads->ds_ctl1 |= AR_IsAggr; | ||
| 8052 | ads->ds_ctl1 &= ~AR_MoreAggr; | ||
| 8053 | ads->ds_ctl6 &= ~AR_PadDelim; | ||
| 8054 | } | ||
| 8055 | |||
| 8056 | void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds) | ||
| 8057 | { | ||
| 8058 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8059 | |||
| 8060 | ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); | ||
| 8061 | } | ||
| 8062 | |||
| 8063 | void | ||
| 8064 | ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, | ||
| 8065 | u32 burstDuration) | ||
| 8066 | { | ||
| 8067 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8068 | |||
| 8069 | ads->ds_ctl2 &= ~AR_BurstDur; | ||
| 8070 | ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); | ||
| 8071 | } | ||
| 8072 | |||
| 8073 | void | ||
| 8074 | ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, | ||
| 8075 | u32 vmf) | ||
| 8076 | { | ||
| 8077 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8078 | |||
| 8079 | if (vmf) | ||
| 8080 | ads->ds_ctl0 |= AR_VirtMoreFrag; | ||
| 8081 | else | ||
| 8082 | ads->ds_ctl0 &= ~AR_VirtMoreFrag; | ||
| 8083 | } | ||
| 8084 | |||
| 8085 | void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp) | ||
| 8086 | { | ||
| 8087 | REG_WRITE(ah, AR_RXDP, rxdp); | ||
| 8088 | } | ||
| 8089 | |||
| 8090 | void ath9k_hw_rxena(struct ath_hal *ah) | ||
| 8091 | { | ||
| 8092 | REG_WRITE(ah, AR_CR, AR_CR_RXE); | ||
| 8093 | } | ||
| 8094 | |||
| 8095 | bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) | ||
| 8096 | { | ||
| 8097 | if (set) { | ||
| 8098 | |||
| 8099 | REG_SET_BIT(ah, AR_DIAG_SW, | ||
| 8100 | (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | ||
| 8101 | |||
| 8102 | if (!ath9k_hw_wait | ||
| 8103 | (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) { | ||
| 8104 | u32 reg; | ||
| 8105 | |||
| 8106 | REG_CLR_BIT(ah, AR_DIAG_SW, | ||
| 8107 | (AR_DIAG_RX_DIS | | ||
| 8108 | AR_DIAG_RX_ABORT)); | ||
| 8109 | |||
| 8110 | reg = REG_READ(ah, AR_OBS_BUS_1); | ||
| 8111 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | ||
| 8112 | "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", | ||
| 8113 | __func__, reg); | ||
| 8114 | |||
| 8115 | return false; | ||
| 8116 | } | ||
| 8117 | } else { | ||
| 8118 | REG_CLR_BIT(ah, AR_DIAG_SW, | ||
| 8119 | (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | ||
| 8120 | } | ||
| 8121 | |||
| 8122 | return true; | ||
| 8123 | } | ||
| 8124 | |||
| 8125 | void | ||
| 8126 | ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, | ||
| 8127 | u32 filter1) | ||
| 8128 | { | ||
| 8129 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); | ||
| 8130 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | ||
| 8131 | } | ||
| 8132 | |||
| 8133 | bool | ||
| 8134 | ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 8135 | u32 size, u32 flags) | ||
| 8136 | { | ||
| 8137 | struct ar5416_desc *ads = AR5416DESC(ds); | ||
| 8138 | struct ath9k_hw_capabilities *pCap = &ah->ah_caps; | ||
| 8139 | |||
| 8140 | ads->ds_ctl1 = size & AR_BufLen; | ||
| 8141 | if (flags & ATH9K_RXDESC_INTREQ) | ||
| 8142 | ads->ds_ctl1 |= AR_RxIntrReq; | ||
| 8143 | |||
| 8144 | ads->ds_rxstatus8 &= ~AR_RxDone; | ||
| 8145 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) | ||
| 8146 | memset(&(ads->u), 0, sizeof(ads->u)); | ||
| 8147 | return true; | ||
| 8148 | } | ||
| 8149 | |||
| 8150 | int | ||
| 8151 | ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, | ||
| 8152 | u32 pa, struct ath_desc *nds, u64 tsf) | ||
| 8153 | { | ||
| 8154 | struct ar5416_desc ads; | ||
| 8155 | struct ar5416_desc *adsp = AR5416DESC(ds); | ||
| 8156 | |||
| 8157 | if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) | ||
| 8158 | return -EINPROGRESS; | ||
| 8159 | |||
| 8160 | ads.u.rx = adsp->u.rx; | ||
| 8161 | |||
| 8162 | ds->ds_rxstat.rs_status = 0; | ||
| 8163 | ds->ds_rxstat.rs_flags = 0; | ||
| 8164 | |||
| 8165 | ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen; | ||
| 8166 | ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp; | ||
| 8167 | |||
| 8168 | ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); | ||
| 8169 | ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); | ||
| 8170 | ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); | ||
| 8171 | ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02); | ||
| 8172 | ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10); | ||
| 8173 | ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11); | ||
| 8174 | ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12); | ||
| 8175 | if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) | ||
| 8176 | ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); | ||
| 8177 | else | ||
| 8178 | ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID; | ||
| 8179 | |||
| 8180 | ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads)); | ||
| 8181 | ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; | ||
| 8182 | |||
| 8183 | ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; | ||
| 8184 | ds->ds_rxstat.rs_moreaggr = | ||
| 8185 | (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; | ||
| 8186 | ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); | ||
| 8187 | ds->ds_rxstat.rs_flags = | ||
| 8188 | (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0; | ||
| 8189 | ds->ds_rxstat.rs_flags |= | ||
| 8190 | (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0; | ||
| 8191 | |||
| 8192 | if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) | ||
| 8193 | ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE; | ||
| 8194 | if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) | ||
| 8195 | ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST; | ||
| 8196 | if (ads.ds_rxstatus8 & AR_DecryptBusyErr) | ||
| 8197 | ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY; | ||
| 8198 | |||
| 8199 | if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { | ||
| 8200 | |||
| 8201 | if (ads.ds_rxstatus8 & AR_CRCErr) | ||
| 8202 | ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC; | ||
| 8203 | else if (ads.ds_rxstatus8 & AR_PHYErr) { | ||
| 8204 | u32 phyerr; | ||
| 8205 | |||
| 8206 | ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY; | ||
| 8207 | phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); | ||
| 8208 | ds->ds_rxstat.rs_phyerr = phyerr; | ||
| 8209 | } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) | ||
| 8210 | ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT; | ||
| 8211 | else if (ads.ds_rxstatus8 & AR_MichaelErr) | ||
| 8212 | ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC; | ||
| 8213 | } | ||
| 8214 | |||
| 8215 | return 0; | ||
| 8216 | } | ||
| 8217 | |||
| 8218 | static void ath9k_hw_setup_rate_table(struct ath_hal *ah, | ||
| 8219 | struct ath9k_rate_table *rt) | ||
| 8220 | { | ||
| 8221 | int i; | ||
| 8222 | |||
| 8223 | if (rt->rateCodeToIndex[0] != 0) | ||
| 8224 | return; | ||
| 8225 | for (i = 0; i < 256; i++) | ||
| 8226 | rt->rateCodeToIndex[i] = (u8) -1; | ||
| 8227 | for (i = 0; i < rt->rateCount; i++) { | ||
| 8228 | u8 code = rt->info[i].rateCode; | ||
| 8229 | u8 cix = rt->info[i].controlRate; | ||
| 8230 | |||
| 8231 | rt->rateCodeToIndex[code] = i; | ||
| 8232 | rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i; | ||
| 8233 | |||
| 8234 | rt->info[i].lpAckDuration = | ||
| 8235 | ath9k_hw_computetxtime(ah, rt, | ||
| 8236 | WLAN_CTRL_FRAME_SIZE, | ||
| 8237 | cix, | ||
| 8238 | false); | ||
| 8239 | rt->info[i].spAckDuration = | ||
| 8240 | ath9k_hw_computetxtime(ah, rt, | ||
| 8241 | WLAN_CTRL_FRAME_SIZE, | ||
| 8242 | cix, | ||
| 8243 | true); | ||
| 8244 | } | ||
| 8245 | } | ||
| 8246 | |||
| 8247 | const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, | ||
| 8248 | u32 mode) | ||
| 8249 | { | ||
| 8250 | struct ath9k_rate_table *rt; | ||
| 8251 | switch (mode) { | ||
| 8252 | case ATH9K_MODE_11A: | ||
| 8253 | rt = &ar5416_11a_table; | ||
| 8254 | break; | ||
| 8255 | case ATH9K_MODE_11B: | ||
| 8256 | rt = &ar5416_11b_table; | ||
| 8257 | break; | ||
| 8258 | case ATH9K_MODE_11G: | ||
| 8259 | rt = &ar5416_11g_table; | ||
| 8260 | break; | ||
| 8261 | case ATH9K_MODE_11NG_HT20: | ||
| 8262 | case ATH9K_MODE_11NG_HT40PLUS: | ||
| 8263 | case ATH9K_MODE_11NG_HT40MINUS: | ||
| 8264 | rt = &ar5416_11ng_table; | ||
| 8265 | break; | ||
| 8266 | case ATH9K_MODE_11NA_HT20: | ||
| 8267 | case ATH9K_MODE_11NA_HT40PLUS: | ||
| 8268 | case ATH9K_MODE_11NA_HT40MINUS: | ||
| 8269 | rt = &ar5416_11na_table; | ||
| 8270 | break; | ||
| 8271 | default: | ||
| 8272 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n", | ||
| 8273 | __func__, mode); | ||
| 8274 | return NULL; | ||
| 8275 | } | ||
| 8276 | ath9k_hw_setup_rate_table(ah, rt); | ||
| 8277 | return rt; | ||
| 8278 | } | ||
| 8279 | |||
| 8280 | static const char *ath9k_hw_devname(u16 devid) | ||
| 8281 | { | ||
| 8282 | switch (devid) { | ||
| 8283 | case AR5416_DEVID_PCI: | ||
| 8284 | case AR5416_DEVID_PCIE: | ||
| 8285 | return "Atheros 5416"; | ||
| 8286 | case AR9160_DEVID_PCI: | ||
| 8287 | return "Atheros 9160"; | ||
| 8288 | case AR9280_DEVID_PCI: | ||
| 8289 | case AR9280_DEVID_PCIE: | ||
| 8290 | return "Atheros 9280"; | ||
| 8291 | } | ||
| 8292 | return NULL; | ||
| 8293 | } | ||
| 8294 | |||
| 8295 | const char *ath9k_hw_probe(u16 vendorid, u16 devid) | ||
| 8296 | { | ||
| 8297 | return vendorid == ATHEROS_VENDOR_ID ? | ||
| 8298 | ath9k_hw_devname(devid) : NULL; | ||
| 8299 | } | ||
| 8300 | |||
| 8301 | struct ath_hal *ath9k_hw_attach(u16 devid, | ||
| 8302 | struct ath_softc *sc, | ||
| 8303 | void __iomem *mem, | ||
| 8304 | int *error) | ||
| 8305 | { | ||
| 8306 | struct ath_hal *ah = NULL; | ||
| 8307 | |||
| 8308 | switch (devid) { | ||
| 8309 | case AR5416_DEVID_PCI: | ||
| 8310 | case AR5416_DEVID_PCIE: | ||
| 8311 | case AR9160_DEVID_PCI: | ||
| 8312 | case AR9280_DEVID_PCI: | ||
| 8313 | case AR9280_DEVID_PCIE: | ||
| 8314 | ah = ath9k_hw_do_attach(devid, sc, mem, error); | ||
| 8315 | break; | ||
| 8316 | default: | ||
| 8317 | DPRINTF(ah->ah_sc, ATH_DBG_ANY, | ||
| 8318 | "devid=0x%x not supported.\n", devid); | ||
| 8319 | ah = NULL; | ||
| 8320 | *error = -ENXIO; | ||
| 8321 | break; | ||
| 8322 | } | ||
| 8323 | if (ah != NULL) { | ||
| 8324 | ah->ah_devid = ah->ah_devid; | ||
| 8325 | ah->ah_subvendorid = ah->ah_subvendorid; | ||
| 8326 | ah->ah_macVersion = ah->ah_macVersion; | ||
| 8327 | ah->ah_macRev = ah->ah_macRev; | ||
| 8328 | ah->ah_phyRev = ah->ah_phyRev; | ||
| 8329 | ah->ah_analog5GhzRev = ah->ah_analog5GhzRev; | ||
| 8330 | ah->ah_analog2GhzRev = ah->ah_analog2GhzRev; | ||
| 8331 | } | ||
| 8332 | return ah; | ||
| 8333 | } | ||
| 8334 | |||
| 8335 | u16 | ||
| 8336 | ath9k_hw_computetxtime(struct ath_hal *ah, | ||
| 8337 | const struct ath9k_rate_table *rates, | ||
| 8338 | u32 frameLen, u16 rateix, | ||
| 8339 | bool shortPreamble) | ||
| 8340 | { | ||
| 8341 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; | ||
| 8342 | u32 kbps; | ||
| 8343 | |||
| 8344 | kbps = rates->info[rateix].rateKbps; | ||
| 8345 | |||
| 8346 | if (kbps == 0) | ||
| 8347 | return 0; | ||
| 8348 | switch (rates->info[rateix].phy) { | ||
| 8349 | |||
| 8350 | case PHY_CCK: | ||
| 8351 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; | ||
| 8352 | if (shortPreamble && rates->info[rateix].shortPreamble) | ||
| 8353 | phyTime >>= 1; | ||
| 8354 | numBits = frameLen << 3; | ||
| 8355 | txTime = CCK_SIFS_TIME + phyTime | ||
| 8356 | + ((numBits * 1000) / kbps); | ||
| 8357 | break; | ||
| 8358 | case PHY_OFDM: | ||
| 8359 | if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { | ||
| 8360 | bitsPerSymbol = | ||
| 8361 | (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; | ||
| 8362 | |||
| 8363 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | ||
| 8364 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | ||
| 8365 | txTime = OFDM_SIFS_TIME_QUARTER | ||
| 8366 | + OFDM_PREAMBLE_TIME_QUARTER | ||
| 8367 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | ||
| 8368 | } else if (ah->ah_curchan && | ||
| 8369 | IS_CHAN_HALF_RATE(ah->ah_curchan)) { | ||
| 8370 | bitsPerSymbol = | ||
| 8371 | (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; | ||
| 8372 | |||
| 8373 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | ||
| 8374 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | ||
| 8375 | txTime = OFDM_SIFS_TIME_HALF + | ||
| 8376 | OFDM_PREAMBLE_TIME_HALF | ||
| 8377 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | ||
| 8378 | } else { | ||
| 8379 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | ||
| 8380 | |||
| 8381 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | ||
| 8382 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | ||
| 8383 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | ||
| 8384 | + (numSymbols * OFDM_SYMBOL_TIME); | ||
| 8385 | } | ||
| 8386 | break; | ||
| 8387 | |||
| 8388 | default: | ||
| 8389 | DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, | ||
| 8390 | "%s: unknown phy %u (rate ix %u)\n", __func__, | ||
| 8391 | rates->info[rateix].phy, rateix); | ||
| 8392 | txTime = 0; | ||
| 8393 | break; | ||
| 8394 | } | ||
| 8395 | return txTime; | ||
| 8396 | } | ||
| 8397 | |||
| 8398 | u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags) | ||
| 8399 | { | ||
| 8400 | if (flags & CHANNEL_2GHZ) { | ||
| 8401 | if (freq == 2484) | ||
| 8402 | return 14; | ||
| 8403 | if (freq < 2484) | ||
| 8404 | return (freq - 2407) / 5; | ||
| 8405 | else | ||
| 8406 | return 15 + ((freq - 2512) / 20); | ||
| 8407 | } else if (flags & CHANNEL_5GHZ) { | ||
| 8408 | if (ath9k_regd_is_public_safety_sku(ah) && | ||
| 8409 | IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) { | ||
| 8410 | return ((freq * 10) + | ||
| 8411 | (((freq % 5) == 2) ? 5 : 0) - 49400) / 5; | ||
| 8412 | } else if ((flags & CHANNEL_A) && (freq <= 5000)) { | ||
| 8413 | return (freq - 4000) / 5; | ||
| 8414 | } else { | ||
| 8415 | return (freq - 5000) / 5; | ||
| 8416 | } | ||
| 8417 | } else { | ||
| 8418 | if (freq == 2484) | ||
| 8419 | return 14; | ||
| 8420 | if (freq < 2484) | ||
| 8421 | return (freq - 2407) / 5; | ||
| 8422 | if (freq < 5000) { | ||
| 8423 | if (ath9k_regd_is_public_safety_sku(ah) | ||
| 8424 | && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) { | ||
| 8425 | return ((freq * 10) + | ||
| 8426 | (((freq % 5) == | ||
| 8427 | 2) ? 5 : 0) - 49400) / 5; | ||
| 8428 | } else if (freq > 4900) { | ||
| 8429 | return (freq - 4000) / 5; | ||
| 8430 | } else { | ||
| 8431 | return 15 + ((freq - 2512) / 20); | ||
| 8432 | } | ||
| 8433 | } | ||
| 8434 | return (freq - 5000) / 5; | ||
| 8435 | } | ||
| 8436 | } | ||
| 8437 | |||
| 8438 | int16_t | ||
| 8439 | ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) | ||
| 8440 | { | ||
| 8441 | struct ath9k_channel *ichan; | ||
| 8442 | |||
| 8443 | ichan = ath9k_regd_check_channel(ah, chan); | ||
| 8444 | if (ichan == NULL) { | ||
| 8445 | DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, | ||
| 8446 | "%s: invalid channel %u/0x%x; no mapping\n", | ||
| 8447 | __func__, chan->channel, chan->channelFlags); | ||
| 8448 | return 0; | ||
| 8449 | } | ||
| 8450 | if (ichan->rawNoiseFloor == 0) { | ||
| 8451 | enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan); | ||
| 8452 | return NOISE_FLOOR[mode]; | ||
| 8453 | } else | ||
| 8454 | return ichan->rawNoiseFloor; | ||
| 8455 | } | ||
| 8456 | |||
| 8457 | bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) | ||
| 8458 | { | ||
| 8459 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 8460 | |||
| 8461 | if (setting) | ||
| 8462 | ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; | ||
| 8463 | else | ||
| 8464 | ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; | ||
| 8465 | return true; | ||
| 8466 | } | ||
| 8467 | |||
| 8468 | bool ath9k_hw_phycounters(struct ath_hal *ah) | ||
| 8469 | { | ||
| 8470 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 8471 | |||
| 8472 | return ahp->ah_hasHwPhyCounters ? true : false; | ||
| 8473 | } | ||
| 8474 | |||
| 8475 | u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) | ||
| 8476 | { | ||
| 8477 | return REG_READ(ah, AR_QTXDP(q)); | ||
| 8478 | } | ||
| 8479 | |||
| 8480 | bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, | ||
| 8481 | u32 txdp) | ||
| 8482 | { | ||
| 8483 | REG_WRITE(ah, AR_QTXDP(q), txdp); | ||
| 8484 | |||
| 8485 | return true; | ||
| 8486 | } | ||
| 8487 | |||
| 8488 | bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) | ||
| 8489 | { | ||
| 8490 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); | ||
| 8491 | |||
| 8492 | REG_WRITE(ah, AR_Q_TXE, 1 << q); | ||
| 8493 | |||
| 8494 | return true; | ||
| 8495 | } | ||
| 8496 | |||
| 8497 | u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) | ||
| 8498 | { | ||
| 8499 | u32 npend; | ||
| 8500 | |||
| 8501 | npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; | ||
| 8502 | if (npend == 0) { | ||
| 8503 | |||
| 8504 | if (REG_READ(ah, AR_Q_TXE) & (1 << q)) | ||
| 8505 | npend = 1; | ||
| 8506 | } | ||
| 8507 | return npend; | ||
| 8508 | } | ||
| 8509 | |||
| 8510 | bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) | ||
| 8511 | { | ||
| 8512 | u32 wait; | ||
| 8513 | |||
| 8514 | REG_WRITE(ah, AR_Q_TXD, 1 << q); | ||
| 8515 | |||
| 8516 | for (wait = 1000; wait != 0; wait--) { | ||
| 8517 | if (ath9k_hw_numtxpending(ah, q) == 0) | ||
| 8518 | break; | ||
| 8519 | udelay(100); | ||
| 8520 | } | ||
| 8521 | |||
| 8522 | if (ath9k_hw_numtxpending(ah, q)) { | ||
| 8523 | u32 tsfLow, j; | ||
| 8524 | |||
| 8525 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | ||
| 8526 | "%s: Num of pending TX Frames %d on Q %d\n", | ||
| 8527 | __func__, ath9k_hw_numtxpending(ah, q), q); | ||
| 8528 | |||
| 8529 | for (j = 0; j < 2; j++) { | ||
| 8530 | tsfLow = REG_READ(ah, AR_TSF_L32); | ||
| 8531 | REG_WRITE(ah, AR_QUIET2, | ||
| 8532 | SM(10, AR_QUIET2_QUIET_DUR)); | ||
| 8533 | REG_WRITE(ah, AR_QUIET_PERIOD, 100); | ||
| 8534 | REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10); | ||
| 8535 | REG_SET_BIT(ah, AR_TIMER_MODE, | ||
| 8536 | AR_QUIET_TIMER_EN); | ||
| 8537 | |||
| 8538 | if ((REG_READ(ah, AR_TSF_L32) >> 10) == | ||
| 8539 | (tsfLow >> 10)) { | ||
| 8540 | break; | ||
| 8541 | } | ||
| 8542 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | ||
| 8543 | "%s: TSF have moved while trying to set " | ||
| 8544 | "quiet time TSF: 0x%08x\n", | ||
| 8545 | __func__, tsfLow); | ||
| 8546 | } | ||
| 8547 | |||
| 8548 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); | ||
| 8549 | |||
| 8550 | udelay(200); | ||
| 8551 | REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); | ||
| 8552 | |||
| 8553 | wait = 1000; | ||
| 8554 | |||
| 8555 | while (ath9k_hw_numtxpending(ah, q)) { | ||
| 8556 | if ((--wait) == 0) { | ||
| 8557 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, | ||
| 8558 | "%s: Failed to stop Tx DMA in 100 " | ||
| 8559 | "msec after killing last frame\n", | ||
| 8560 | __func__); | ||
| 8561 | break; | ||
| 8562 | } | ||
| 8563 | udelay(100); | ||
| 8564 | } | ||
| 8565 | |||
| 8566 | REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); | ||
| 8567 | } | ||
| 8568 | |||
| 8569 | REG_WRITE(ah, AR_Q_TXD, 0); | ||
| 8570 | return wait != 0; | ||
| 8571 | } | ||
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h new file mode 100644 index 000000000000..ae680f21ba7e --- /dev/null +++ b/drivers/net/wireless/ath9k/hw.h | |||
| @@ -0,0 +1,969 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef HW_H | ||
| 18 | #define HW_H | ||
| 19 | |||
| 20 | #include <linux/if_ether.h> | ||
| 21 | #include <linux/delay.h> | ||
| 22 | |||
| 23 | struct ar5416_desc { | ||
| 24 | u32 ds_link; | ||
| 25 | u32 ds_data; | ||
| 26 | u32 ds_ctl0; | ||
| 27 | u32 ds_ctl1; | ||
| 28 | union { | ||
| 29 | struct { | ||
| 30 | u32 ctl2; | ||
| 31 | u32 ctl3; | ||
| 32 | u32 ctl4; | ||
| 33 | u32 ctl5; | ||
| 34 | u32 ctl6; | ||
| 35 | u32 ctl7; | ||
| 36 | u32 ctl8; | ||
| 37 | u32 ctl9; | ||
| 38 | u32 ctl10; | ||
| 39 | u32 ctl11; | ||
| 40 | u32 status0; | ||
| 41 | u32 status1; | ||
| 42 | u32 status2; | ||
| 43 | u32 status3; | ||
| 44 | u32 status4; | ||
| 45 | u32 status5; | ||
| 46 | u32 status6; | ||
| 47 | u32 status7; | ||
| 48 | u32 status8; | ||
| 49 | u32 status9; | ||
| 50 | } tx; | ||
| 51 | struct { | ||
| 52 | u32 status0; | ||
| 53 | u32 status1; | ||
| 54 | u32 status2; | ||
| 55 | u32 status3; | ||
| 56 | u32 status4; | ||
| 57 | u32 status5; | ||
| 58 | u32 status6; | ||
| 59 | u32 status7; | ||
| 60 | u32 status8; | ||
| 61 | } rx; | ||
| 62 | } u; | ||
| 63 | } __packed; | ||
| 64 | |||
| 65 | #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) | ||
| 66 | #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) | ||
| 67 | |||
| 68 | #define ds_ctl2 u.tx.ctl2 | ||
| 69 | #define ds_ctl3 u.tx.ctl3 | ||
| 70 | #define ds_ctl4 u.tx.ctl4 | ||
| 71 | #define ds_ctl5 u.tx.ctl5 | ||
| 72 | #define ds_ctl6 u.tx.ctl6 | ||
| 73 | #define ds_ctl7 u.tx.ctl7 | ||
| 74 | #define ds_ctl8 u.tx.ctl8 | ||
| 75 | #define ds_ctl9 u.tx.ctl9 | ||
| 76 | #define ds_ctl10 u.tx.ctl10 | ||
| 77 | #define ds_ctl11 u.tx.ctl11 | ||
| 78 | |||
| 79 | #define ds_txstatus0 u.tx.status0 | ||
| 80 | #define ds_txstatus1 u.tx.status1 | ||
| 81 | #define ds_txstatus2 u.tx.status2 | ||
| 82 | #define ds_txstatus3 u.tx.status3 | ||
| 83 | #define ds_txstatus4 u.tx.status4 | ||
| 84 | #define ds_txstatus5 u.tx.status5 | ||
| 85 | #define ds_txstatus6 u.tx.status6 | ||
| 86 | #define ds_txstatus7 u.tx.status7 | ||
| 87 | #define ds_txstatus8 u.tx.status8 | ||
| 88 | #define ds_txstatus9 u.tx.status9 | ||
| 89 | |||
| 90 | #define ds_rxstatus0 u.rx.status0 | ||
| 91 | #define ds_rxstatus1 u.rx.status1 | ||
| 92 | #define ds_rxstatus2 u.rx.status2 | ||
| 93 | #define ds_rxstatus3 u.rx.status3 | ||
| 94 | #define ds_rxstatus4 u.rx.status4 | ||
| 95 | #define ds_rxstatus5 u.rx.status5 | ||
| 96 | #define ds_rxstatus6 u.rx.status6 | ||
| 97 | #define ds_rxstatus7 u.rx.status7 | ||
| 98 | #define ds_rxstatus8 u.rx.status8 | ||
| 99 | |||
| 100 | #define AR_FrameLen 0x00000fff | ||
| 101 | #define AR_VirtMoreFrag 0x00001000 | ||
| 102 | #define AR_TxCtlRsvd00 0x0000e000 | ||
| 103 | #define AR_XmitPower 0x003f0000 | ||
| 104 | #define AR_XmitPower_S 16 | ||
| 105 | #define AR_RTSEnable 0x00400000 | ||
| 106 | #define AR_VEOL 0x00800000 | ||
| 107 | #define AR_ClrDestMask 0x01000000 | ||
| 108 | #define AR_TxCtlRsvd01 0x1e000000 | ||
| 109 | #define AR_TxIntrReq 0x20000000 | ||
| 110 | #define AR_DestIdxValid 0x40000000 | ||
| 111 | #define AR_CTSEnable 0x80000000 | ||
| 112 | |||
| 113 | #define AR_BufLen 0x00000fff | ||
| 114 | #define AR_TxMore 0x00001000 | ||
| 115 | #define AR_DestIdx 0x000fe000 | ||
| 116 | #define AR_DestIdx_S 13 | ||
| 117 | #define AR_FrameType 0x00f00000 | ||
| 118 | #define AR_FrameType_S 20 | ||
| 119 | #define AR_NoAck 0x01000000 | ||
| 120 | #define AR_InsertTS 0x02000000 | ||
| 121 | #define AR_CorruptFCS 0x04000000 | ||
| 122 | #define AR_ExtOnly 0x08000000 | ||
| 123 | #define AR_ExtAndCtl 0x10000000 | ||
| 124 | #define AR_MoreAggr 0x20000000 | ||
| 125 | #define AR_IsAggr 0x40000000 | ||
| 126 | |||
| 127 | #define AR_BurstDur 0x00007fff | ||
| 128 | #define AR_BurstDur_S 0 | ||
| 129 | #define AR_DurUpdateEna 0x00008000 | ||
| 130 | #define AR_XmitDataTries0 0x000f0000 | ||
| 131 | #define AR_XmitDataTries0_S 16 | ||
| 132 | #define AR_XmitDataTries1 0x00f00000 | ||
| 133 | #define AR_XmitDataTries1_S 20 | ||
| 134 | #define AR_XmitDataTries2 0x0f000000 | ||
| 135 | #define AR_XmitDataTries2_S 24 | ||
| 136 | #define AR_XmitDataTries3 0xf0000000 | ||
| 137 | #define AR_XmitDataTries3_S 28 | ||
| 138 | |||
| 139 | #define AR_XmitRate0 0x000000ff | ||
| 140 | #define AR_XmitRate0_S 0 | ||
| 141 | #define AR_XmitRate1 0x0000ff00 | ||
| 142 | #define AR_XmitRate1_S 8 | ||
| 143 | #define AR_XmitRate2 0x00ff0000 | ||
| 144 | #define AR_XmitRate2_S 16 | ||
| 145 | #define AR_XmitRate3 0xff000000 | ||
| 146 | #define AR_XmitRate3_S 24 | ||
| 147 | |||
| 148 | #define AR_PacketDur0 0x00007fff | ||
| 149 | #define AR_PacketDur0_S 0 | ||
| 150 | #define AR_RTSCTSQual0 0x00008000 | ||
| 151 | #define AR_PacketDur1 0x7fff0000 | ||
| 152 | #define AR_PacketDur1_S 16 | ||
| 153 | #define AR_RTSCTSQual1 0x80000000 | ||
| 154 | |||
| 155 | #define AR_PacketDur2 0x00007fff | ||
| 156 | #define AR_PacketDur2_S 0 | ||
| 157 | #define AR_RTSCTSQual2 0x00008000 | ||
| 158 | #define AR_PacketDur3 0x7fff0000 | ||
| 159 | #define AR_PacketDur3_S 16 | ||
| 160 | #define AR_RTSCTSQual3 0x80000000 | ||
| 161 | |||
| 162 | #define AR_AggrLen 0x0000ffff | ||
| 163 | #define AR_AggrLen_S 0 | ||
| 164 | #define AR_TxCtlRsvd60 0x00030000 | ||
| 165 | #define AR_PadDelim 0x03fc0000 | ||
| 166 | #define AR_PadDelim_S 18 | ||
| 167 | #define AR_EncrType 0x0c000000 | ||
| 168 | #define AR_EncrType_S 26 | ||
| 169 | #define AR_TxCtlRsvd61 0xf0000000 | ||
| 170 | |||
| 171 | #define AR_2040_0 0x00000001 | ||
| 172 | #define AR_GI0 0x00000002 | ||
| 173 | #define AR_ChainSel0 0x0000001c | ||
| 174 | #define AR_ChainSel0_S 2 | ||
| 175 | #define AR_2040_1 0x00000020 | ||
| 176 | #define AR_GI1 0x00000040 | ||
| 177 | #define AR_ChainSel1 0x00000380 | ||
| 178 | #define AR_ChainSel1_S 7 | ||
| 179 | #define AR_2040_2 0x00000400 | ||
| 180 | #define AR_GI2 0x00000800 | ||
| 181 | #define AR_ChainSel2 0x00007000 | ||
| 182 | #define AR_ChainSel2_S 12 | ||
| 183 | #define AR_2040_3 0x00008000 | ||
| 184 | #define AR_GI3 0x00010000 | ||
| 185 | #define AR_ChainSel3 0x000e0000 | ||
| 186 | #define AR_ChainSel3_S 17 | ||
| 187 | #define AR_RTSCTSRate 0x0ff00000 | ||
| 188 | #define AR_RTSCTSRate_S 20 | ||
| 189 | #define AR_TxCtlRsvd70 0xf0000000 | ||
| 190 | |||
| 191 | #define AR_TxRSSIAnt00 0x000000ff | ||
| 192 | #define AR_TxRSSIAnt00_S 0 | ||
| 193 | #define AR_TxRSSIAnt01 0x0000ff00 | ||
| 194 | #define AR_TxRSSIAnt01_S 8 | ||
| 195 | #define AR_TxRSSIAnt02 0x00ff0000 | ||
| 196 | #define AR_TxRSSIAnt02_S 16 | ||
| 197 | #define AR_TxStatusRsvd00 0x3f000000 | ||
| 198 | #define AR_TxBaStatus 0x40000000 | ||
| 199 | #define AR_TxStatusRsvd01 0x80000000 | ||
| 200 | |||
| 201 | #define AR_FrmXmitOK 0x00000001 | ||
| 202 | #define AR_ExcessiveRetries 0x00000002 | ||
| 203 | #define AR_FIFOUnderrun 0x00000004 | ||
| 204 | #define AR_Filtered 0x00000008 | ||
| 205 | #define AR_RTSFailCnt 0x000000f0 | ||
| 206 | #define AR_RTSFailCnt_S 4 | ||
| 207 | #define AR_DataFailCnt 0x00000f00 | ||
| 208 | #define AR_DataFailCnt_S 8 | ||
| 209 | #define AR_VirtRetryCnt 0x0000f000 | ||
| 210 | #define AR_VirtRetryCnt_S 12 | ||
| 211 | #define AR_TxDelimUnderrun 0x00010000 | ||
| 212 | #define AR_TxDataUnderrun 0x00020000 | ||
| 213 | #define AR_DescCfgErr 0x00040000 | ||
| 214 | #define AR_TxTimerExpired 0x00080000 | ||
| 215 | #define AR_TxStatusRsvd10 0xfff00000 | ||
| 216 | |||
| 217 | #define AR_SendTimestamp ds_txstatus2 | ||
| 218 | #define AR_BaBitmapLow ds_txstatus3 | ||
| 219 | #define AR_BaBitmapHigh ds_txstatus4 | ||
| 220 | |||
| 221 | #define AR_TxRSSIAnt10 0x000000ff | ||
| 222 | #define AR_TxRSSIAnt10_S 0 | ||
| 223 | #define AR_TxRSSIAnt11 0x0000ff00 | ||
| 224 | #define AR_TxRSSIAnt11_S 8 | ||
| 225 | #define AR_TxRSSIAnt12 0x00ff0000 | ||
| 226 | #define AR_TxRSSIAnt12_S 16 | ||
| 227 | #define AR_TxRSSICombined 0xff000000 | ||
| 228 | #define AR_TxRSSICombined_S 24 | ||
| 229 | |||
| 230 | #define AR_TxEVM0 ds_txstatus5 | ||
| 231 | #define AR_TxEVM1 ds_txstatus6 | ||
| 232 | #define AR_TxEVM2 ds_txstatus7 | ||
| 233 | |||
| 234 | #define AR_TxDone 0x00000001 | ||
| 235 | #define AR_SeqNum 0x00001ffe | ||
| 236 | #define AR_SeqNum_S 1 | ||
| 237 | #define AR_TxStatusRsvd80 0x0001e000 | ||
| 238 | #define AR_TxOpExceeded 0x00020000 | ||
| 239 | #define AR_TxStatusRsvd81 0x001c0000 | ||
| 240 | #define AR_FinalTxIdx 0x00600000 | ||
| 241 | #define AR_FinalTxIdx_S 21 | ||
| 242 | #define AR_TxStatusRsvd82 0x01800000 | ||
| 243 | #define AR_PowerMgmt 0x02000000 | ||
| 244 | #define AR_TxStatusRsvd83 0xfc000000 | ||
| 245 | |||
| 246 | #define AR_RxCTLRsvd00 0xffffffff | ||
| 247 | |||
| 248 | #define AR_BufLen 0x00000fff | ||
| 249 | #define AR_RxCtlRsvd00 0x00001000 | ||
| 250 | #define AR_RxIntrReq 0x00002000 | ||
| 251 | #define AR_RxCtlRsvd01 0xffffc000 | ||
| 252 | |||
| 253 | #define AR_RxRSSIAnt00 0x000000ff | ||
| 254 | #define AR_RxRSSIAnt00_S 0 | ||
| 255 | #define AR_RxRSSIAnt01 0x0000ff00 | ||
| 256 | #define AR_RxRSSIAnt01_S 8 | ||
| 257 | #define AR_RxRSSIAnt02 0x00ff0000 | ||
| 258 | #define AR_RxRSSIAnt02_S 16 | ||
| 259 | #define AR_RxRate 0xff000000 | ||
| 260 | #define AR_RxRate_S 24 | ||
| 261 | #define AR_RxStatusRsvd00 0xff000000 | ||
| 262 | |||
| 263 | #define AR_DataLen 0x00000fff | ||
| 264 | #define AR_RxMore 0x00001000 | ||
| 265 | #define AR_NumDelim 0x003fc000 | ||
| 266 | #define AR_NumDelim_S 14 | ||
| 267 | #define AR_RxStatusRsvd10 0xff800000 | ||
| 268 | |||
| 269 | #define AR_RcvTimestamp ds_rxstatus2 | ||
| 270 | |||
| 271 | #define AR_GI 0x00000001 | ||
| 272 | #define AR_2040 0x00000002 | ||
| 273 | #define AR_Parallel40 0x00000004 | ||
| 274 | #define AR_Parallel40_S 2 | ||
| 275 | #define AR_RxStatusRsvd30 0x000000f8 | ||
| 276 | #define AR_RxAntenna 0xffffff00 | ||
| 277 | #define AR_RxAntenna_S 8 | ||
| 278 | |||
| 279 | #define AR_RxRSSIAnt10 0x000000ff | ||
| 280 | #define AR_RxRSSIAnt10_S 0 | ||
| 281 | #define AR_RxRSSIAnt11 0x0000ff00 | ||
| 282 | #define AR_RxRSSIAnt11_S 8 | ||
| 283 | #define AR_RxRSSIAnt12 0x00ff0000 | ||
| 284 | #define AR_RxRSSIAnt12_S 16 | ||
| 285 | #define AR_RxRSSICombined 0xff000000 | ||
| 286 | #define AR_RxRSSICombined_S 24 | ||
| 287 | |||
| 288 | #define AR_RxEVM0 ds_rxstatus4 | ||
| 289 | #define AR_RxEVM1 ds_rxstatus5 | ||
| 290 | #define AR_RxEVM2 ds_rxstatus6 | ||
| 291 | |||
| 292 | #define AR_RxDone 0x00000001 | ||
| 293 | #define AR_RxFrameOK 0x00000002 | ||
| 294 | #define AR_CRCErr 0x00000004 | ||
| 295 | #define AR_DecryptCRCErr 0x00000008 | ||
| 296 | #define AR_PHYErr 0x00000010 | ||
| 297 | #define AR_MichaelErr 0x00000020 | ||
| 298 | #define AR_PreDelimCRCErr 0x00000040 | ||
| 299 | #define AR_RxStatusRsvd70 0x00000080 | ||
| 300 | #define AR_RxKeyIdxValid 0x00000100 | ||
| 301 | #define AR_KeyIdx 0x0000fe00 | ||
| 302 | #define AR_KeyIdx_S 9 | ||
| 303 | #define AR_PHYErrCode 0x0000ff00 | ||
| 304 | #define AR_PHYErrCode_S 8 | ||
| 305 | #define AR_RxMoreAggr 0x00010000 | ||
| 306 | #define AR_RxAggr 0x00020000 | ||
| 307 | #define AR_PostDelimCRCErr 0x00040000 | ||
| 308 | #define AR_RxStatusRsvd71 0x3ff80000 | ||
| 309 | #define AR_DecryptBusyErr 0x40000000 | ||
| 310 | #define AR_KeyMiss 0x80000000 | ||
| 311 | |||
| 312 | #define AR5416_MAGIC 0x19641014 | ||
| 313 | |||
| 314 | #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ | ||
| 315 | MS(ads->ds_rxstatus0, AR_RxRate) : \ | ||
| 316 | (ads->ds_rxstatus3 >> 2) & 0xFF) | ||
| 317 | #define RXSTATUS_DUPLICATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ | ||
| 318 | MS(ads->ds_rxstatus3, AR_Parallel40) : \ | ||
| 319 | (ads->ds_rxstatus3 >> 10) & 0x1) | ||
| 320 | |||
| 321 | #define set11nTries(_series, _index) \ | ||
| 322 | (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) | ||
| 323 | |||
| 324 | #define set11nRate(_series, _index) \ | ||
| 325 | (SM((_series)[_index].Rate, AR_XmitRate##_index)) | ||
| 326 | |||
| 327 | #define set11nPktDurRTSCTS(_series, _index) \ | ||
| 328 | (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ | ||
| 329 | ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ | ||
| 330 | AR_RTSCTSQual##_index : 0)) | ||
| 331 | |||
| 332 | #define set11nRateFlags(_series, _index) \ | ||
| 333 | (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ | ||
| 334 | AR_2040_##_index : 0) \ | ||
| 335 | |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ | ||
| 336 | AR_GI##_index : 0) \ | ||
| 337 | |SM((_series)[_index].ChSel, AR_ChainSel##_index)) | ||
| 338 | |||
| 339 | #define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) | ||
| 340 | |||
| 341 | #define INIT_CONFIG_STATUS 0x00000000 | ||
| 342 | #define INIT_RSSI_THR 0x00000700 | ||
| 343 | #define INIT_BCON_CNTRL_REG 0x00000000 | ||
| 344 | |||
| 345 | #define MIN_TX_FIFO_THRESHOLD 0x1 | ||
| 346 | #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) | ||
| 347 | #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD | ||
| 348 | |||
| 349 | #define NUM_CORNER_FIX_BITS_2133 7 | ||
| 350 | #define CCK_OFDM_GAIN_DELTA 15 | ||
| 351 | |||
| 352 | struct ar5416AniState { | ||
| 353 | struct ath9k_channel c; | ||
| 354 | u8 noiseImmunityLevel; | ||
| 355 | u8 spurImmunityLevel; | ||
| 356 | u8 firstepLevel; | ||
| 357 | u8 ofdmWeakSigDetectOff; | ||
| 358 | u8 cckWeakSigThreshold; | ||
| 359 | u32 listenTime; | ||
| 360 | u32 ofdmTrigHigh; | ||
| 361 | u32 ofdmTrigLow; | ||
| 362 | int32_t cckTrigHigh; | ||
| 363 | int32_t cckTrigLow; | ||
| 364 | int32_t rssiThrLow; | ||
| 365 | int32_t rssiThrHigh; | ||
| 366 | u32 noiseFloor; | ||
| 367 | u32 txFrameCount; | ||
| 368 | u32 rxFrameCount; | ||
| 369 | u32 cycleCount; | ||
| 370 | u32 ofdmPhyErrCount; | ||
| 371 | u32 cckPhyErrCount; | ||
| 372 | u32 ofdmPhyErrBase; | ||
| 373 | u32 cckPhyErrBase; | ||
| 374 | int16_t pktRssi[2]; | ||
| 375 | int16_t ofdmErrRssi[2]; | ||
| 376 | int16_t cckErrRssi[2]; | ||
| 377 | }; | ||
| 378 | |||
| 379 | #define HAL_PROCESS_ANI 0x00000001 | ||
| 380 | #define HAL_RADAR_EN 0x80000000 | ||
| 381 | #define HAL_AR_EN 0x40000000 | ||
| 382 | |||
| 383 | #define DO_ANI(ah) \ | ||
| 384 | ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) | ||
| 385 | |||
| 386 | struct ar5416Stats { | ||
| 387 | u32 ast_ani_niup; | ||
| 388 | u32 ast_ani_nidown; | ||
| 389 | u32 ast_ani_spurup; | ||
| 390 | u32 ast_ani_spurdown; | ||
| 391 | u32 ast_ani_ofdmon; | ||
| 392 | u32 ast_ani_ofdmoff; | ||
| 393 | u32 ast_ani_cckhigh; | ||
| 394 | u32 ast_ani_ccklow; | ||
| 395 | u32 ast_ani_stepup; | ||
| 396 | u32 ast_ani_stepdown; | ||
| 397 | u32 ast_ani_ofdmerrs; | ||
| 398 | u32 ast_ani_cckerrs; | ||
| 399 | u32 ast_ani_reset; | ||
| 400 | u32 ast_ani_lzero; | ||
| 401 | u32 ast_ani_lneg; | ||
| 402 | struct ath9k_mib_stats ast_mibstats; | ||
| 403 | struct ath9k_node_stats ast_nodestats; | ||
| 404 | }; | ||
| 405 | |||
| 406 | #define AR5416_OPFLAGS_11A 0x01 | ||
| 407 | #define AR5416_OPFLAGS_11G 0x02 | ||
| 408 | #define AR5416_OPFLAGS_N_5G_HT40 0x04 | ||
| 409 | #define AR5416_OPFLAGS_N_2G_HT40 0x08 | ||
| 410 | #define AR5416_OPFLAGS_N_5G_HT20 0x10 | ||
| 411 | #define AR5416_OPFLAGS_N_2G_HT20 0x20 | ||
| 412 | |||
| 413 | #define EEP_RFSILENT_ENABLED 0x0001 | ||
| 414 | #define EEP_RFSILENT_ENABLED_S 0 | ||
| 415 | #define EEP_RFSILENT_POLARITY 0x0002 | ||
| 416 | #define EEP_RFSILENT_POLARITY_S 1 | ||
| 417 | #define EEP_RFSILENT_GPIO_SEL 0x001c | ||
| 418 | #define EEP_RFSILENT_GPIO_SEL_S 2 | ||
| 419 | |||
| 420 | #define AR5416_EEP_NO_BACK_VER 0x1 | ||
| 421 | #define AR5416_EEP_VER 0xE | ||
| 422 | #define AR5416_EEP_VER_MINOR_MASK 0x0FFF | ||
| 423 | #define AR5416_EEP_MINOR_VER_2 0x2 | ||
| 424 | #define AR5416_EEP_MINOR_VER_3 0x3 | ||
| 425 | #define AR5416_EEP_MINOR_VER_7 0x7 | ||
| 426 | #define AR5416_EEP_MINOR_VER_9 0x9 | ||
| 427 | |||
| 428 | #define AR5416_EEP_START_LOC 256 | ||
| 429 | #define AR5416_NUM_5G_CAL_PIERS 8 | ||
| 430 | #define AR5416_NUM_2G_CAL_PIERS 4 | ||
| 431 | #define AR5416_NUM_5G_20_TARGET_POWERS 8 | ||
| 432 | #define AR5416_NUM_5G_40_TARGET_POWERS 8 | ||
| 433 | #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 | ||
| 434 | #define AR5416_NUM_2G_20_TARGET_POWERS 4 | ||
| 435 | #define AR5416_NUM_2G_40_TARGET_POWERS 4 | ||
| 436 | #define AR5416_NUM_CTLS 24 | ||
| 437 | #define AR5416_NUM_BAND_EDGES 8 | ||
| 438 | #define AR5416_NUM_PD_GAINS 4 | ||
| 439 | #define AR5416_PD_GAINS_IN_MASK 4 | ||
| 440 | #define AR5416_PD_GAIN_ICEPTS 5 | ||
| 441 | #define AR5416_EEPROM_MODAL_SPURS 5 | ||
| 442 | #define AR5416_MAX_RATE_POWER 63 | ||
| 443 | #define AR5416_NUM_PDADC_VALUES 128 | ||
| 444 | #define AR5416_NUM_RATES 16 | ||
| 445 | #define AR5416_BCHAN_UNUSED 0xFF | ||
| 446 | #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 | ||
| 447 | #define AR5416_EEPMISC_BIG_ENDIAN 0x01 | ||
| 448 | #define AR5416_MAX_CHAINS 3 | ||
| 449 | #define AR5416_ANT_16S 25 | ||
| 450 | |||
| 451 | #define AR5416_NUM_ANT_CHAIN_FIELDS 7 | ||
| 452 | #define AR5416_NUM_ANT_COMMON_FIELDS 4 | ||
| 453 | #define AR5416_SIZE_ANT_CHAIN_FIELD 3 | ||
| 454 | #define AR5416_SIZE_ANT_COMMON_FIELD 4 | ||
| 455 | #define AR5416_ANT_CHAIN_MASK 0x7 | ||
| 456 | #define AR5416_ANT_COMMON_MASK 0xf | ||
| 457 | #define AR5416_CHAIN_0_IDX 0 | ||
| 458 | #define AR5416_CHAIN_1_IDX 1 | ||
| 459 | #define AR5416_CHAIN_2_IDX 2 | ||
| 460 | |||
| 461 | #define AR5416_PWR_TABLE_OFFSET -5 | ||
| 462 | #define AR5416_LEGACY_CHAINMASK 1 | ||
| 463 | |||
| 464 | enum eeprom_param { | ||
| 465 | EEP_NFTHRESH_5, | ||
| 466 | EEP_NFTHRESH_2, | ||
| 467 | EEP_MAC_MSW, | ||
| 468 | EEP_MAC_MID, | ||
| 469 | EEP_MAC_LSW, | ||
| 470 | EEP_REG_0, | ||
| 471 | EEP_REG_1, | ||
| 472 | EEP_OP_CAP, | ||
| 473 | EEP_OP_MODE, | ||
| 474 | EEP_RF_SILENT, | ||
| 475 | EEP_OB_5, | ||
| 476 | EEP_DB_5, | ||
| 477 | EEP_OB_2, | ||
| 478 | EEP_DB_2, | ||
| 479 | EEP_MINOR_REV, | ||
| 480 | EEP_TX_MASK, | ||
| 481 | EEP_RX_MASK, | ||
| 482 | }; | ||
| 483 | |||
| 484 | enum ar5416_rates { | ||
| 485 | rate6mb, rate9mb, rate12mb, rate18mb, | ||
| 486 | rate24mb, rate36mb, rate48mb, rate54mb, | ||
| 487 | rate1l, rate2l, rate2s, rate5_5l, | ||
| 488 | rate5_5s, rate11l, rate11s, rateXr, | ||
| 489 | rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, | ||
| 490 | rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, | ||
| 491 | rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, | ||
| 492 | rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, | ||
| 493 | rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, | ||
| 494 | Ar5416RateSize | ||
| 495 | }; | ||
| 496 | |||
| 497 | struct base_eep_header { | ||
| 498 | u16 length; | ||
| 499 | u16 checksum; | ||
| 500 | u16 version; | ||
| 501 | u8 opCapFlags; | ||
| 502 | u8 eepMisc; | ||
| 503 | u16 regDmn[2]; | ||
| 504 | u8 macAddr[6]; | ||
| 505 | u8 rxMask; | ||
| 506 | u8 txMask; | ||
| 507 | u16 rfSilent; | ||
| 508 | u16 blueToothOptions; | ||
| 509 | u16 deviceCap; | ||
| 510 | u32 binBuildNumber; | ||
| 511 | u8 deviceType; | ||
| 512 | u8 pwdclkind; | ||
| 513 | u8 futureBase[32]; | ||
| 514 | } __packed; | ||
| 515 | |||
| 516 | struct spur_chan { | ||
| 517 | u16 spurChan; | ||
| 518 | u8 spurRangeLow; | ||
| 519 | u8 spurRangeHigh; | ||
| 520 | } __packed; | ||
| 521 | |||
| 522 | struct modal_eep_header { | ||
| 523 | u32 antCtrlChain[AR5416_MAX_CHAINS]; | ||
| 524 | u32 antCtrlCommon; | ||
| 525 | u8 antennaGainCh[AR5416_MAX_CHAINS]; | ||
| 526 | u8 switchSettling; | ||
| 527 | u8 txRxAttenCh[AR5416_MAX_CHAINS]; | ||
| 528 | u8 rxTxMarginCh[AR5416_MAX_CHAINS]; | ||
| 529 | u8 adcDesiredSize; | ||
| 530 | u8 pgaDesiredSize; | ||
| 531 | u8 xlnaGainCh[AR5416_MAX_CHAINS]; | ||
| 532 | u8 txEndToXpaOff; | ||
| 533 | u8 txEndToRxOn; | ||
| 534 | u8 txFrameToXpaOn; | ||
| 535 | u8 thresh62; | ||
| 536 | u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; | ||
| 537 | u8 xpdGain; | ||
| 538 | u8 xpd; | ||
| 539 | u8 iqCalICh[AR5416_MAX_CHAINS]; | ||
| 540 | u8 iqCalQCh[AR5416_MAX_CHAINS]; | ||
| 541 | u8 pdGainOverlap; | ||
| 542 | u8 ob; | ||
| 543 | u8 db; | ||
| 544 | u8 xpaBiasLvl; | ||
| 545 | u8 pwrDecreaseFor2Chain; | ||
| 546 | u8 pwrDecreaseFor3Chain; | ||
| 547 | u8 txFrameToDataStart; | ||
| 548 | u8 txFrameToPaOn; | ||
| 549 | u8 ht40PowerIncForPdadc; | ||
| 550 | u8 bswAtten[AR5416_MAX_CHAINS]; | ||
| 551 | u8 bswMargin[AR5416_MAX_CHAINS]; | ||
| 552 | u8 swSettleHt40; | ||
| 553 | u8 xatten2Db[AR5416_MAX_CHAINS]; | ||
| 554 | u8 xatten2Margin[AR5416_MAX_CHAINS]; | ||
| 555 | u8 ob_ch1; | ||
| 556 | u8 db_ch1; | ||
| 557 | u8 useAnt1:1, | ||
| 558 | force_xpaon:1, | ||
| 559 | local_bias:1, | ||
| 560 | femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; | ||
| 561 | u8 futureModalar9280; | ||
| 562 | u16 xpaBiasLvlFreq[3]; | ||
| 563 | u8 futureModal[6]; | ||
| 564 | |||
| 565 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | ||
| 566 | } __packed; | ||
| 567 | |||
| 568 | struct cal_data_per_freq { | ||
| 569 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | ||
| 570 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | ||
| 571 | } __packed; | ||
| 572 | |||
| 573 | struct cal_target_power_leg { | ||
| 574 | u8 bChannel; | ||
| 575 | u8 tPow2x[4]; | ||
| 576 | } __packed; | ||
| 577 | |||
| 578 | struct cal_target_power_ht { | ||
| 579 | u8 bChannel; | ||
| 580 | u8 tPow2x[8]; | ||
| 581 | } __packed; | ||
| 582 | |||
| 583 | #ifdef __BIG_ENDIAN_BITFIELD | ||
| 584 | struct cal_ctl_edges { | ||
| 585 | u8 bChannel; | ||
| 586 | u8 flag:2, tPower:6; | ||
| 587 | } __packed; | ||
| 588 | #else | ||
| 589 | struct cal_ctl_edges { | ||
| 590 | u8 bChannel; | ||
| 591 | u8 tPower:6, flag:2; | ||
| 592 | } __packed; | ||
| 593 | #endif | ||
| 594 | |||
| 595 | struct cal_ctl_data { | ||
| 596 | struct cal_ctl_edges | ||
| 597 | ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; | ||
| 598 | } __packed; | ||
| 599 | |||
| 600 | struct ar5416_eeprom { | ||
| 601 | struct base_eep_header baseEepHeader; | ||
| 602 | u8 custData[64]; | ||
| 603 | struct modal_eep_header modalHeader[2]; | ||
| 604 | u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; | ||
| 605 | u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; | ||
| 606 | struct cal_data_per_freq | ||
| 607 | calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; | ||
| 608 | struct cal_data_per_freq | ||
| 609 | calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; | ||
| 610 | struct cal_target_power_leg | ||
| 611 | calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; | ||
| 612 | struct cal_target_power_ht | ||
| 613 | calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; | ||
| 614 | struct cal_target_power_ht | ||
| 615 | calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; | ||
| 616 | struct cal_target_power_leg | ||
| 617 | calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; | ||
| 618 | struct cal_target_power_leg | ||
| 619 | calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; | ||
| 620 | struct cal_target_power_ht | ||
| 621 | calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; | ||
| 622 | struct cal_target_power_ht | ||
| 623 | calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; | ||
| 624 | u8 ctlIndex[AR5416_NUM_CTLS]; | ||
| 625 | struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; | ||
| 626 | u8 padding; | ||
| 627 | } __packed; | ||
| 628 | |||
| 629 | struct ar5416IniArray { | ||
| 630 | u32 *ia_array; | ||
| 631 | u32 ia_rows; | ||
| 632 | u32 ia_columns; | ||
| 633 | }; | ||
| 634 | |||
| 635 | #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ | ||
| 636 | (iniarray)->ia_array = (u32 *)(array); \ | ||
| 637 | (iniarray)->ia_rows = (rows); \ | ||
| 638 | (iniarray)->ia_columns = (columns); \ | ||
| 639 | } while (0) | ||
| 640 | |||
| 641 | #define INI_RA(iniarray, row, column) \ | ||
| 642 | (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) | ||
| 643 | |||
| 644 | #define INIT_CAL(_perCal) do { \ | ||
| 645 | (_perCal)->calState = CAL_WAITING; \ | ||
| 646 | (_perCal)->calNext = NULL; \ | ||
| 647 | } while (0) | ||
| 648 | |||
| 649 | #define INSERT_CAL(_ahp, _perCal) \ | ||
| 650 | do { \ | ||
| 651 | if ((_ahp)->ah_cal_list_last == NULL) { \ | ||
| 652 | (_ahp)->ah_cal_list = \ | ||
| 653 | (_ahp)->ah_cal_list_last = (_perCal); \ | ||
| 654 | ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ | ||
| 655 | } else { \ | ||
| 656 | ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ | ||
| 657 | (_ahp)->ah_cal_list_last = (_perCal); \ | ||
| 658 | (_perCal)->calNext = (_ahp)->ah_cal_list; \ | ||
| 659 | } \ | ||
| 660 | } while (0) | ||
| 661 | |||
| 662 | enum hal_cal_types { | ||
| 663 | ADC_DC_INIT_CAL = 0x1, | ||
| 664 | ADC_GAIN_CAL = 0x2, | ||
| 665 | ADC_DC_CAL = 0x4, | ||
| 666 | IQ_MISMATCH_CAL = 0x8 | ||
| 667 | }; | ||
| 668 | |||
| 669 | enum hal_cal_state { | ||
| 670 | CAL_INACTIVE, | ||
| 671 | CAL_WAITING, | ||
| 672 | CAL_RUNNING, | ||
| 673 | CAL_DONE | ||
| 674 | }; | ||
| 675 | |||
| 676 | #define MIN_CAL_SAMPLES 1 | ||
| 677 | #define MAX_CAL_SAMPLES 64 | ||
| 678 | #define INIT_LOG_COUNT 5 | ||
| 679 | #define PER_MIN_LOG_COUNT 2 | ||
| 680 | #define PER_MAX_LOG_COUNT 10 | ||
| 681 | |||
| 682 | struct hal_percal_data { | ||
| 683 | enum hal_cal_types calType; | ||
| 684 | u32 calNumSamples; | ||
| 685 | u32 calCountMax; | ||
| 686 | void (*calCollect) (struct ath_hal *); | ||
| 687 | void (*calPostProc) (struct ath_hal *, u8); | ||
| 688 | }; | ||
| 689 | |||
| 690 | struct hal_cal_list { | ||
| 691 | const struct hal_percal_data *calData; | ||
| 692 | enum hal_cal_state calState; | ||
| 693 | struct hal_cal_list *calNext; | ||
| 694 | }; | ||
| 695 | |||
| 696 | struct ath_hal_5416 { | ||
| 697 | struct ath_hal ah; | ||
| 698 | struct ar5416_eeprom ah_eeprom; | ||
| 699 | u8 ah_macaddr[ETH_ALEN]; | ||
| 700 | u8 ah_bssid[ETH_ALEN]; | ||
| 701 | u8 ah_bssidmask[ETH_ALEN]; | ||
| 702 | u16 ah_assocId; | ||
| 703 | int16_t ah_curchanRadIndex; | ||
| 704 | u32 ah_maskReg; | ||
| 705 | struct ar5416Stats ah_stats; | ||
| 706 | u32 ah_txDescMask; | ||
| 707 | u32 ah_txOkInterruptMask; | ||
| 708 | u32 ah_txErrInterruptMask; | ||
| 709 | u32 ah_txDescInterruptMask; | ||
| 710 | u32 ah_txEolInterruptMask; | ||
| 711 | u32 ah_txUrnInterruptMask; | ||
| 712 | struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; | ||
| 713 | enum ath9k_power_mode ah_powerMode; | ||
| 714 | bool ah_chipFullSleep; | ||
| 715 | u32 ah_atimWindow; | ||
| 716 | enum ath9k_ant_setting ah_diversityControl; | ||
| 717 | u16 ah_antennaSwitchSwap; | ||
| 718 | enum hal_cal_types ah_suppCals; | ||
| 719 | struct hal_cal_list ah_iqCalData; | ||
| 720 | struct hal_cal_list ah_adcGainCalData; | ||
| 721 | struct hal_cal_list ah_adcDcCalInitData; | ||
| 722 | struct hal_cal_list ah_adcDcCalData; | ||
| 723 | struct hal_cal_list *ah_cal_list; | ||
| 724 | struct hal_cal_list *ah_cal_list_last; | ||
| 725 | struct hal_cal_list *ah_cal_list_curr; | ||
| 726 | #define ah_totalPowerMeasI ah_Meas0.unsign | ||
| 727 | #define ah_totalPowerMeasQ ah_Meas1.unsign | ||
| 728 | #define ah_totalIqCorrMeas ah_Meas2.sign | ||
| 729 | #define ah_totalAdcIOddPhase ah_Meas0.unsign | ||
| 730 | #define ah_totalAdcIEvenPhase ah_Meas1.unsign | ||
| 731 | #define ah_totalAdcQOddPhase ah_Meas2.unsign | ||
| 732 | #define ah_totalAdcQEvenPhase ah_Meas3.unsign | ||
| 733 | #define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign | ||
| 734 | #define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign | ||
| 735 | #define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign | ||
| 736 | #define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign | ||
| 737 | union { | ||
| 738 | u32 unsign[AR5416_MAX_CHAINS]; | ||
| 739 | int32_t sign[AR5416_MAX_CHAINS]; | ||
| 740 | } ah_Meas0; | ||
| 741 | union { | ||
| 742 | u32 unsign[AR5416_MAX_CHAINS]; | ||
| 743 | int32_t sign[AR5416_MAX_CHAINS]; | ||
| 744 | } ah_Meas1; | ||
| 745 | union { | ||
| 746 | u32 unsign[AR5416_MAX_CHAINS]; | ||
| 747 | int32_t sign[AR5416_MAX_CHAINS]; | ||
| 748 | } ah_Meas2; | ||
| 749 | union { | ||
| 750 | u32 unsign[AR5416_MAX_CHAINS]; | ||
| 751 | int32_t sign[AR5416_MAX_CHAINS]; | ||
| 752 | } ah_Meas3; | ||
| 753 | u16 ah_CalSamples; | ||
| 754 | u32 ah_tx6PowerInHalfDbm; | ||
| 755 | u32 ah_staId1Defaults; | ||
| 756 | u32 ah_miscMode; | ||
| 757 | bool ah_tpcEnabled; | ||
| 758 | u32 ah_beaconInterval; | ||
| 759 | enum { | ||
| 760 | AUTO_32KHZ, | ||
| 761 | USE_32KHZ, | ||
| 762 | DONT_USE_32KHZ, | ||
| 763 | } ah_enable32kHzClock; | ||
| 764 | u32 *ah_analogBank0Data; | ||
| 765 | u32 *ah_analogBank1Data; | ||
| 766 | u32 *ah_analogBank2Data; | ||
| 767 | u32 *ah_analogBank3Data; | ||
| 768 | u32 *ah_analogBank6Data; | ||
| 769 | u32 *ah_analogBank6TPCData; | ||
| 770 | u32 *ah_analogBank7Data; | ||
| 771 | u32 *ah_addac5416_21; | ||
| 772 | u32 *ah_bank6Temp; | ||
| 773 | u32 ah_ofdmTxPower; | ||
| 774 | int16_t ah_txPowerIndexOffset; | ||
| 775 | u32 ah_slottime; | ||
| 776 | u32 ah_acktimeout; | ||
| 777 | u32 ah_ctstimeout; | ||
| 778 | u32 ah_globaltxtimeout; | ||
| 779 | u8 ah_gBeaconRate; | ||
| 780 | u32 ah_gpioSelect; | ||
| 781 | u32 ah_polarity; | ||
| 782 | u32 ah_gpioBit; | ||
| 783 | bool ah_eepEnabled; | ||
| 784 | u32 ah_procPhyErr; | ||
| 785 | bool ah_hasHwPhyCounters; | ||
| 786 | u32 ah_aniPeriod; | ||
| 787 | struct ar5416AniState *ah_curani; | ||
| 788 | struct ar5416AniState ah_ani[255]; | ||
| 789 | int ah_totalSizeDesired[5]; | ||
| 790 | int ah_coarseHigh[5]; | ||
| 791 | int ah_coarseLow[5]; | ||
| 792 | int ah_firpwr[5]; | ||
| 793 | u16 ah_ratesArray[16]; | ||
| 794 | u32 ah_intrTxqs; | ||
| 795 | bool ah_intrMitigation; | ||
| 796 | u32 ah_cycleCount; | ||
| 797 | u32 ah_ctlBusy; | ||
| 798 | u32 ah_extBusy; | ||
| 799 | enum ath9k_ht_extprotspacing ah_extprotspacing; | ||
| 800 | u8 ah_txchainmask; | ||
| 801 | u8 ah_rxchainmask; | ||
| 802 | int ah_hwp; | ||
| 803 | void __iomem *ah_cal_mem; | ||
| 804 | enum ath9k_ani_cmd ah_ani_function; | ||
| 805 | struct ar5416IniArray ah_iniModes; | ||
| 806 | struct ar5416IniArray ah_iniCommon; | ||
| 807 | struct ar5416IniArray ah_iniBank0; | ||
| 808 | struct ar5416IniArray ah_iniBB_RfGain; | ||
| 809 | struct ar5416IniArray ah_iniBank1; | ||
| 810 | struct ar5416IniArray ah_iniBank2; | ||
| 811 | struct ar5416IniArray ah_iniBank3; | ||
| 812 | struct ar5416IniArray ah_iniBank6; | ||
| 813 | struct ar5416IniArray ah_iniBank6TPC; | ||
| 814 | struct ar5416IniArray ah_iniBank7; | ||
| 815 | struct ar5416IniArray ah_iniAddac; | ||
| 816 | struct ar5416IniArray ah_iniPcieSerdes; | ||
| 817 | struct ar5416IniArray ah_iniModesAdditional; | ||
| 818 | }; | ||
| 819 | #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) | ||
| 820 | |||
| 821 | #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) | ||
| 822 | |||
| 823 | #define IS_5416_EMU(ah) \ | ||
| 824 | ((ah->ah_devid == AR5416_DEVID_EMU) || \ | ||
| 825 | (ah->ah_devid == AR5416_DEVID_EMU_PCIE)) | ||
| 826 | |||
| 827 | #define ar5416RfDetach(ah) do { \ | ||
| 828 | if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \ | ||
| 829 | AH5416(ah)->ah_rfHal.rfDetach(ah); \ | ||
| 830 | } while (0) | ||
| 831 | |||
| 832 | #define ath9k_hw_use_flash(_ah) \ | ||
| 833 | (!(_ah->ah_flags & AH_USE_EEPROM)) | ||
| 834 | |||
| 835 | |||
| 836 | #define DO_DELAY(x) do { \ | ||
| 837 | if ((++(x) % 64) == 0) \ | ||
| 838 | udelay(1); \ | ||
| 839 | } while (0) | ||
| 840 | |||
| 841 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ | ||
| 842 | int r; \ | ||
| 843 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | ||
| 844 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ | ||
| 845 | INI_RA((iniarray), r, (column))); \ | ||
| 846 | DO_DELAY(regWr); \ | ||
| 847 | } \ | ||
| 848 | } while (0) | ||
| 849 | |||
| 850 | #define BASE_ACTIVATE_DELAY 100 | ||
| 851 | #define RTC_PLL_SETTLE_DELAY 1000 | ||
| 852 | #define COEF_SCALE_S 24 | ||
| 853 | #define HT40_CHANNEL_CENTER_SHIFT 10 | ||
| 854 | |||
| 855 | #define ar5416CheckOpMode(_opmode) \ | ||
| 856 | ((_opmode == ATH9K_M_STA) || (_opmode == ATH9K_M_IBSS) || \ | ||
| 857 | (_opmode == ATH9K_M_HOSTAP) || (_opmode == ATH9K_M_MONITOR)) | ||
| 858 | |||
| 859 | #define AR5416_EEPROM_MAGIC_OFFSET 0x0 | ||
| 860 | |||
| 861 | #define AR5416_EEPROM_S 2 | ||
| 862 | #define AR5416_EEPROM_OFFSET 0x2000 | ||
| 863 | #define AR5416_EEPROM_START_ADDR \ | ||
| 864 | (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 | ||
| 865 | #define AR5416_EEPROM_MAX 0xae0 | ||
| 866 | #define ar5416_get_eep_ver(_ahp) \ | ||
| 867 | (((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF) | ||
| 868 | #define ar5416_get_eep_rev(_ahp) \ | ||
| 869 | (((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF) | ||
| 870 | #define ar5416_get_ntxchains(_txchainmask) \ | ||
| 871 | (((_txchainmask >> 2) & 1) + \ | ||
| 872 | ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) | ||
| 873 | |||
| 874 | #define IS_EEP_MINOR_V3(_ahp) \ | ||
| 875 | (ath9k_hw_get_eeprom((_ahp), EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_3) | ||
| 876 | |||
| 877 | #define FIXED_CCA_THRESHOLD 15 | ||
| 878 | |||
| 879 | #ifdef __BIG_ENDIAN | ||
| 880 | #define AR5416_EEPROM_MAGIC 0x5aa5 | ||
| 881 | #else | ||
| 882 | #define AR5416_EEPROM_MAGIC 0xa55a | ||
| 883 | #endif | ||
| 884 | |||
| 885 | #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) | ||
| 886 | |||
| 887 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 | ||
| 888 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | ||
| 889 | |||
| 890 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | ||
| 891 | #define ATH9K_NUM_QUEUES 10 | ||
| 892 | |||
| 893 | #define HAL_NOISE_IMMUNE_MAX 4 | ||
| 894 | #define HAL_SPUR_IMMUNE_MAX 7 | ||
| 895 | #define HAL_FIRST_STEP_MAX 2 | ||
| 896 | |||
| 897 | #define ATH9K_ANI_OFDM_TRIG_HIGH 500 | ||
| 898 | #define ATH9K_ANI_OFDM_TRIG_LOW 200 | ||
| 899 | #define ATH9K_ANI_CCK_TRIG_HIGH 200 | ||
| 900 | #define ATH9K_ANI_CCK_TRIG_LOW 100 | ||
| 901 | #define ATH9K_ANI_NOISE_IMMUNE_LVL 4 | ||
| 902 | #define ATH9K_ANI_USE_OFDM_WEAK_SIG true | ||
| 903 | #define ATH9K_ANI_CCK_WEAK_SIG_THR false | ||
| 904 | #define ATH9K_ANI_SPUR_IMMUNE_LVL 7 | ||
| 905 | #define ATH9K_ANI_FIRSTEP_LVL 0 | ||
| 906 | #define ATH9K_ANI_RSSI_THR_HIGH 40 | ||
| 907 | #define ATH9K_ANI_RSSI_THR_LOW 7 | ||
| 908 | #define ATH9K_ANI_PERIOD 100 | ||
| 909 | |||
| 910 | #define AR_GPIOD_MASK 0x00001FFF | ||
| 911 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | ||
| 912 | |||
| 913 | #define MAX_ANALOG_START 319 | ||
| 914 | |||
| 915 | #define HAL_EP_RND(x, mul) \ | ||
| 916 | ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) | ||
| 917 | #define BEACON_RSSI(ahp) \ | ||
| 918 | HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ | ||
| 919 | ATH9K_RSSI_EP_MULTIPLIER) | ||
| 920 | |||
| 921 | #define ah_mibStats ah_stats.ast_mibstats | ||
| 922 | |||
| 923 | #define AH_TIMEOUT 100000 | ||
| 924 | #define AH_TIME_QUANTUM 10 | ||
| 925 | |||
| 926 | #define IS(_c, _f) (((_c)->channelFlags & _f) || 0) | ||
| 927 | |||
| 928 | #define AR_KEYTABLE_SIZE 128 | ||
| 929 | #define POWER_UP_TIME 200000 | ||
| 930 | |||
| 931 | #define EXT_ADDITIVE (0x8000) | ||
| 932 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) | ||
| 933 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) | ||
| 934 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) | ||
| 935 | |||
| 936 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 | ||
| 937 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 | ||
| 938 | #define SPUR_RSSI_THRESH 40 | ||
| 939 | |||
| 940 | #define TU_TO_USEC(_tu) ((_tu) << 10) | ||
| 941 | |||
| 942 | #define CAB_TIMEOUT_VAL 10 | ||
| 943 | #define BEACON_TIMEOUT_VAL 10 | ||
| 944 | #define MIN_BEACON_TIMEOUT_VAL 1 | ||
| 945 | #define SLEEP_SLOP 3 | ||
| 946 | |||
| 947 | #define CCK_SIFS_TIME 10 | ||
| 948 | #define CCK_PREAMBLE_BITS 144 | ||
| 949 | #define CCK_PLCP_BITS 48 | ||
| 950 | |||
| 951 | #define OFDM_SIFS_TIME 16 | ||
| 952 | #define OFDM_PREAMBLE_TIME 20 | ||
| 953 | #define OFDM_PLCP_BITS 22 | ||
| 954 | #define OFDM_SYMBOL_TIME 4 | ||
| 955 | |||
| 956 | #define OFDM_SIFS_TIME_HALF 32 | ||
| 957 | #define OFDM_PREAMBLE_TIME_HALF 40 | ||
| 958 | #define OFDM_PLCP_BITS_HALF 22 | ||
| 959 | #define OFDM_SYMBOL_TIME_HALF 8 | ||
| 960 | |||
| 961 | #define OFDM_SIFS_TIME_QUARTER 64 | ||
| 962 | #define OFDM_PREAMBLE_TIME_QUARTER 80 | ||
| 963 | #define OFDM_PLCP_BITS_QUARTER 22 | ||
| 964 | #define OFDM_SYMBOL_TIME_QUARTER 16 | ||
| 965 | |||
| 966 | u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp, | ||
| 967 | enum eeprom_param param); | ||
| 968 | |||
| 969 | #endif | ||
diff --git a/drivers/net/wireless/ath9k/initvals.h b/drivers/net/wireless/ath9k/initvals.h new file mode 100644 index 000000000000..3dd3815940a4 --- /dev/null +++ b/drivers/net/wireless/ath9k/initvals.h | |||
| @@ -0,0 +1,3146 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | static const u32 ar5416Modes_9100[][6] = { | ||
| 18 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | ||
| 19 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | ||
| 20 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | ||
| 21 | { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, | ||
| 22 | { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, | ||
| 23 | { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf }, | ||
| 24 | { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, | ||
| 25 | { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, | ||
| 26 | { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 27 | { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, | ||
| 28 | { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 29 | { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, | ||
| 30 | { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 }, | ||
| 31 | { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 32 | { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 33 | { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 34 | { 0x00009850, 0x6de8b4e0, 0x6de8b4e0, 0x6de8b0de, 0x6de8b0de, 0x6de8b0de }, | ||
| 35 | { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, | ||
| 36 | { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e }, | ||
| 37 | { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 }, | ||
| 38 | { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, | ||
| 39 | { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 }, | ||
| 40 | { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, | ||
| 41 | { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 }, | ||
| 42 | { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 }, | ||
| 43 | { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b }, | ||
| 44 | { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 }, | ||
| 45 | { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, | ||
| 46 | { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, | ||
| 47 | { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, | ||
| 48 | { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 }, | ||
| 49 | { 0x0000c9bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 }, | ||
| 50 | { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, | ||
| 51 | { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, | ||
| 52 | { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c }, | ||
| 53 | { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, | ||
| 54 | { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, | ||
| 55 | { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 56 | { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 57 | { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 }, | ||
| 58 | { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 }, | ||
| 59 | { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 60 | { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 61 | { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 62 | { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, | ||
| 63 | { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, | ||
| 64 | { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa }, | ||
| 65 | { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 }, | ||
| 66 | { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 }, | ||
| 67 | { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 }, | ||
| 68 | { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b }, | ||
| 69 | { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b }, | ||
| 70 | { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a }, | ||
| 71 | { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf }, | ||
| 72 | { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f }, | ||
| 73 | { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f }, | ||
| 74 | { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f }, | ||
| 75 | { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 76 | { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 77 | { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 78 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static const u32 ar5416Common_9100[][2] = { | ||
| 82 | { 0x0000000c, 0x00000000 }, | ||
| 83 | { 0x00000030, 0x00020015 }, | ||
| 84 | { 0x00000034, 0x00000005 }, | ||
| 85 | { 0x00000040, 0x00000000 }, | ||
| 86 | { 0x00000044, 0x00000008 }, | ||
| 87 | { 0x00000048, 0x00000008 }, | ||
| 88 | { 0x0000004c, 0x00000010 }, | ||
| 89 | { 0x00000050, 0x00000000 }, | ||
| 90 | { 0x00000054, 0x0000001f }, | ||
| 91 | { 0x00000800, 0x00000000 }, | ||
| 92 | { 0x00000804, 0x00000000 }, | ||
| 93 | { 0x00000808, 0x00000000 }, | ||
| 94 | { 0x0000080c, 0x00000000 }, | ||
| 95 | { 0x00000810, 0x00000000 }, | ||
| 96 | { 0x00000814, 0x00000000 }, | ||
| 97 | { 0x00000818, 0x00000000 }, | ||
| 98 | { 0x0000081c, 0x00000000 }, | ||
| 99 | { 0x00000820, 0x00000000 }, | ||
| 100 | { 0x00000824, 0x00000000 }, | ||
| 101 | { 0x00001040, 0x002ffc0f }, | ||
| 102 | { 0x00001044, 0x002ffc0f }, | ||
| 103 | { 0x00001048, 0x002ffc0f }, | ||
| 104 | { 0x0000104c, 0x002ffc0f }, | ||
| 105 | { 0x00001050, 0x002ffc0f }, | ||
| 106 | { 0x00001054, 0x002ffc0f }, | ||
| 107 | { 0x00001058, 0x002ffc0f }, | ||
| 108 | { 0x0000105c, 0x002ffc0f }, | ||
| 109 | { 0x00001060, 0x002ffc0f }, | ||
| 110 | { 0x00001064, 0x002ffc0f }, | ||
| 111 | { 0x00001230, 0x00000000 }, | ||
| 112 | { 0x00001270, 0x00000000 }, | ||
| 113 | { 0x00001038, 0x00000000 }, | ||
| 114 | { 0x00001078, 0x00000000 }, | ||
| 115 | { 0x000010b8, 0x00000000 }, | ||
| 116 | { 0x000010f8, 0x00000000 }, | ||
| 117 | { 0x00001138, 0x00000000 }, | ||
| 118 | { 0x00001178, 0x00000000 }, | ||
| 119 | { 0x000011b8, 0x00000000 }, | ||
| 120 | { 0x000011f8, 0x00000000 }, | ||
| 121 | { 0x00001238, 0x00000000 }, | ||
| 122 | { 0x00001278, 0x00000000 }, | ||
| 123 | { 0x000012b8, 0x00000000 }, | ||
| 124 | { 0x000012f8, 0x00000000 }, | ||
| 125 | { 0x00001338, 0x00000000 }, | ||
| 126 | { 0x00001378, 0x00000000 }, | ||
| 127 | { 0x000013b8, 0x00000000 }, | ||
| 128 | { 0x000013f8, 0x00000000 }, | ||
| 129 | { 0x00001438, 0x00000000 }, | ||
| 130 | { 0x00001478, 0x00000000 }, | ||
| 131 | { 0x000014b8, 0x00000000 }, | ||
| 132 | { 0x000014f8, 0x00000000 }, | ||
| 133 | { 0x00001538, 0x00000000 }, | ||
| 134 | { 0x00001578, 0x00000000 }, | ||
| 135 | { 0x000015b8, 0x00000000 }, | ||
| 136 | { 0x000015f8, 0x00000000 }, | ||
| 137 | { 0x00001638, 0x00000000 }, | ||
| 138 | { 0x00001678, 0x00000000 }, | ||
| 139 | { 0x000016b8, 0x00000000 }, | ||
| 140 | { 0x000016f8, 0x00000000 }, | ||
| 141 | { 0x00001738, 0x00000000 }, | ||
| 142 | { 0x00001778, 0x00000000 }, | ||
| 143 | { 0x000017b8, 0x00000000 }, | ||
| 144 | { 0x000017f8, 0x00000000 }, | ||
| 145 | { 0x0000103c, 0x00000000 }, | ||
| 146 | { 0x0000107c, 0x00000000 }, | ||
| 147 | { 0x000010bc, 0x00000000 }, | ||
| 148 | { 0x000010fc, 0x00000000 }, | ||
| 149 | { 0x0000113c, 0x00000000 }, | ||
| 150 | { 0x0000117c, 0x00000000 }, | ||
| 151 | { 0x000011bc, 0x00000000 }, | ||
| 152 | { 0x000011fc, 0x00000000 }, | ||
| 153 | { 0x0000123c, 0x00000000 }, | ||
| 154 | { 0x0000127c, 0x00000000 }, | ||
| 155 | { 0x000012bc, 0x00000000 }, | ||
| 156 | { 0x000012fc, 0x00000000 }, | ||
| 157 | { 0x0000133c, 0x00000000 }, | ||
| 158 | { 0x0000137c, 0x00000000 }, | ||
| 159 | { 0x000013bc, 0x00000000 }, | ||
| 160 | { 0x000013fc, 0x00000000 }, | ||
| 161 | { 0x0000143c, 0x00000000 }, | ||
| 162 | { 0x0000147c, 0x00000000 }, | ||
| 163 | { 0x00004030, 0x00000002 }, | ||
| 164 | { 0x0000403c, 0x00000002 }, | ||
| 165 | { 0x00007010, 0x00000000 }, | ||
| 166 | { 0x00007038, 0x000004c2 }, | ||
| 167 | { 0x00008004, 0x00000000 }, | ||
| 168 | { 0x00008008, 0x00000000 }, | ||
| 169 | { 0x0000800c, 0x00000000 }, | ||
| 170 | { 0x00008018, 0x00000700 }, | ||
| 171 | { 0x00008020, 0x00000000 }, | ||
| 172 | { 0x00008038, 0x00000000 }, | ||
| 173 | { 0x0000803c, 0x00000000 }, | ||
| 174 | { 0x00008048, 0x40000000 }, | ||
| 175 | { 0x00008054, 0x00000000 }, | ||
| 176 | { 0x00008058, 0x00000000 }, | ||
| 177 | { 0x0000805c, 0x000fc78f }, | ||
| 178 | { 0x00008060, 0x0000000f }, | ||
| 179 | { 0x00008064, 0x00000000 }, | ||
| 180 | { 0x000080c0, 0x2a82301a }, | ||
| 181 | { 0x000080c4, 0x05dc01e0 }, | ||
| 182 | { 0x000080c8, 0x1f402710 }, | ||
| 183 | { 0x000080cc, 0x01f40000 }, | ||
| 184 | { 0x000080d0, 0x00001e00 }, | ||
| 185 | { 0x000080d4, 0x00000000 }, | ||
| 186 | { 0x000080d8, 0x00400000 }, | ||
| 187 | { 0x000080e0, 0xffffffff }, | ||
| 188 | { 0x000080e4, 0x0000ffff }, | ||
| 189 | { 0x000080e8, 0x003f3f3f }, | ||
| 190 | { 0x000080ec, 0x00000000 }, | ||
| 191 | { 0x000080f0, 0x00000000 }, | ||
| 192 | { 0x000080f4, 0x00000000 }, | ||
| 193 | { 0x000080f8, 0x00000000 }, | ||
| 194 | { 0x000080fc, 0x00020000 }, | ||
| 195 | { 0x00008100, 0x00020000 }, | ||
| 196 | { 0x00008104, 0x00000001 }, | ||
| 197 | { 0x00008108, 0x00000052 }, | ||
| 198 | { 0x0000810c, 0x00000000 }, | ||
| 199 | { 0x00008110, 0x00000168 }, | ||
| 200 | { 0x00008118, 0x000100aa }, | ||
| 201 | { 0x0000811c, 0x00003210 }, | ||
| 202 | { 0x00008120, 0x08f04800 }, | ||
| 203 | { 0x00008124, 0x00000000 }, | ||
| 204 | { 0x00008128, 0x00000000 }, | ||
| 205 | { 0x0000812c, 0x00000000 }, | ||
| 206 | { 0x00008130, 0x00000000 }, | ||
| 207 | { 0x00008134, 0x00000000 }, | ||
| 208 | { 0x00008138, 0x00000000 }, | ||
| 209 | { 0x0000813c, 0x00000000 }, | ||
| 210 | { 0x00008144, 0x00000000 }, | ||
| 211 | { 0x00008168, 0x00000000 }, | ||
| 212 | { 0x0000816c, 0x00000000 }, | ||
| 213 | { 0x00008170, 0x32143320 }, | ||
| 214 | { 0x00008174, 0xfaa4fa50 }, | ||
| 215 | { 0x00008178, 0x00000100 }, | ||
| 216 | { 0x0000817c, 0x00000000 }, | ||
| 217 | { 0x000081c4, 0x00000000 }, | ||
| 218 | { 0x000081d0, 0x00003210 }, | ||
| 219 | { 0x000081ec, 0x00000000 }, | ||
| 220 | { 0x000081f0, 0x00000000 }, | ||
| 221 | { 0x000081f4, 0x00000000 }, | ||
| 222 | { 0x000081f8, 0x00000000 }, | ||
| 223 | { 0x000081fc, 0x00000000 }, | ||
| 224 | { 0x00008200, 0x00000000 }, | ||
| 225 | { 0x00008204, 0x00000000 }, | ||
| 226 | { 0x00008208, 0x00000000 }, | ||
| 227 | { 0x0000820c, 0x00000000 }, | ||
| 228 | { 0x00008210, 0x00000000 }, | ||
| 229 | { 0x00008214, 0x00000000 }, | ||
| 230 | { 0x00008218, 0x00000000 }, | ||
| 231 | { 0x0000821c, 0x00000000 }, | ||
| 232 | { 0x00008220, 0x00000000 }, | ||
| 233 | { 0x00008224, 0x00000000 }, | ||
| 234 | { 0x00008228, 0x00000000 }, | ||
| 235 | { 0x0000822c, 0x00000000 }, | ||
| 236 | { 0x00008230, 0x00000000 }, | ||
| 237 | { 0x00008234, 0x00000000 }, | ||
| 238 | { 0x00008238, 0x00000000 }, | ||
| 239 | { 0x0000823c, 0x00000000 }, | ||
| 240 | { 0x00008240, 0x00100000 }, | ||
| 241 | { 0x00008244, 0x0010f400 }, | ||
| 242 | { 0x00008248, 0x00000100 }, | ||
| 243 | { 0x0000824c, 0x0001e800 }, | ||
| 244 | { 0x00008250, 0x00000000 }, | ||
| 245 | { 0x00008254, 0x00000000 }, | ||
| 246 | { 0x00008258, 0x00000000 }, | ||
| 247 | { 0x0000825c, 0x400000ff }, | ||
| 248 | { 0x00008260, 0x00080922 }, | ||
| 249 | { 0x00008270, 0x00000000 }, | ||
| 250 | { 0x00008274, 0x40000000 }, | ||
| 251 | { 0x00008278, 0x003e4180 }, | ||
| 252 | { 0x0000827c, 0x00000000 }, | ||
| 253 | { 0x00008284, 0x0000002c }, | ||
| 254 | { 0x00008288, 0x0000002c }, | ||
| 255 | { 0x0000828c, 0x00000000 }, | ||
| 256 | { 0x00008294, 0x00000000 }, | ||
| 257 | { 0x00008298, 0x00000000 }, | ||
| 258 | { 0x00008300, 0x00000000 }, | ||
| 259 | { 0x00008304, 0x00000000 }, | ||
| 260 | { 0x00008308, 0x00000000 }, | ||
| 261 | { 0x0000830c, 0x00000000 }, | ||
| 262 | { 0x00008310, 0x00000000 }, | ||
| 263 | { 0x00008314, 0x00000000 }, | ||
| 264 | { 0x00008318, 0x00000000 }, | ||
| 265 | { 0x00008328, 0x00000000 }, | ||
| 266 | { 0x0000832c, 0x00000007 }, | ||
| 267 | { 0x00008330, 0x00000302 }, | ||
| 268 | { 0x00008334, 0x00000e00 }, | ||
| 269 | { 0x00008338, 0x00000000 }, | ||
| 270 | { 0x0000833c, 0x00000000 }, | ||
| 271 | { 0x00008340, 0x000107ff }, | ||
| 272 | { 0x00009808, 0x00000000 }, | ||
| 273 | { 0x0000980c, 0xad848e19 }, | ||
| 274 | { 0x00009810, 0x7d14e000 }, | ||
| 275 | { 0x00009814, 0x9c0a9f6b }, | ||
| 276 | { 0x0000981c, 0x00000000 }, | ||
| 277 | { 0x0000982c, 0x0000a000 }, | ||
| 278 | { 0x00009830, 0x00000000 }, | ||
| 279 | { 0x0000983c, 0x00200400 }, | ||
| 280 | { 0x00009840, 0x206a002e }, | ||
| 281 | { 0x0000984c, 0x1284233c }, | ||
| 282 | { 0x00009854, 0x00000859 }, | ||
| 283 | { 0x00009900, 0x00000000 }, | ||
| 284 | { 0x00009904, 0x00000000 }, | ||
| 285 | { 0x00009908, 0x00000000 }, | ||
| 286 | { 0x0000990c, 0x00000000 }, | ||
| 287 | { 0x0000991c, 0x10000fff }, | ||
| 288 | { 0x00009920, 0x05100000 }, | ||
| 289 | { 0x0000a920, 0x05100000 }, | ||
| 290 | { 0x0000b920, 0x05100000 }, | ||
| 291 | { 0x00009928, 0x00000001 }, | ||
| 292 | { 0x0000992c, 0x00000004 }, | ||
| 293 | { 0x00009934, 0x1e1f2022 }, | ||
| 294 | { 0x00009938, 0x0a0b0c0d }, | ||
| 295 | { 0x0000993c, 0x00000000 }, | ||
| 296 | { 0x00009948, 0x9280b212 }, | ||
| 297 | { 0x0000994c, 0x00020028 }, | ||
| 298 | { 0x00009954, 0x5d50e188 }, | ||
| 299 | { 0x00009958, 0x00081fff }, | ||
| 300 | { 0x0000c95c, 0x004b6a8e }, | ||
| 301 | { 0x0000c968, 0x000003ce }, | ||
| 302 | { 0x00009970, 0x190fb515 }, | ||
| 303 | { 0x00009974, 0x00000000 }, | ||
| 304 | { 0x00009978, 0x00000001 }, | ||
| 305 | { 0x0000997c, 0x00000000 }, | ||
| 306 | { 0x00009980, 0x00000000 }, | ||
| 307 | { 0x00009984, 0x00000000 }, | ||
| 308 | { 0x00009988, 0x00000000 }, | ||
| 309 | { 0x0000998c, 0x00000000 }, | ||
| 310 | { 0x00009990, 0x00000000 }, | ||
| 311 | { 0x00009994, 0x00000000 }, | ||
| 312 | { 0x00009998, 0x00000000 }, | ||
| 313 | { 0x0000999c, 0x00000000 }, | ||
| 314 | { 0x000099a0, 0x00000000 }, | ||
| 315 | { 0x000099a4, 0x00000001 }, | ||
| 316 | { 0x000099a8, 0x001fff00 }, | ||
| 317 | { 0x000099ac, 0x00000000 }, | ||
| 318 | { 0x000099b0, 0x03051000 }, | ||
| 319 | { 0x000099dc, 0x00000000 }, | ||
| 320 | { 0x000099e0, 0x00000200 }, | ||
| 321 | { 0x000099e4, 0xaaaaaaaa }, | ||
| 322 | { 0x000099e8, 0x3c466478 }, | ||
| 323 | { 0x000099ec, 0x000000aa }, | ||
| 324 | { 0x000099fc, 0x00001042 }, | ||
| 325 | { 0x00009b00, 0x00000000 }, | ||
| 326 | { 0x00009b04, 0x00000001 }, | ||
| 327 | { 0x00009b08, 0x00000002 }, | ||
| 328 | { 0x00009b0c, 0x00000003 }, | ||
| 329 | { 0x00009b10, 0x00000004 }, | ||
| 330 | { 0x00009b14, 0x00000005 }, | ||
| 331 | { 0x00009b18, 0x00000008 }, | ||
| 332 | { 0x00009b1c, 0x00000009 }, | ||
| 333 | { 0x00009b20, 0x0000000a }, | ||
| 334 | { 0x00009b24, 0x0000000b }, | ||
| 335 | { 0x00009b28, 0x0000000c }, | ||
| 336 | { 0x00009b2c, 0x0000000d }, | ||
| 337 | { 0x00009b30, 0x00000010 }, | ||
| 338 | { 0x00009b34, 0x00000011 }, | ||
| 339 | { 0x00009b38, 0x00000012 }, | ||
| 340 | { 0x00009b3c, 0x00000013 }, | ||
| 341 | { 0x00009b40, 0x00000014 }, | ||
| 342 | { 0x00009b44, 0x00000015 }, | ||
| 343 | { 0x00009b48, 0x00000018 }, | ||
| 344 | { 0x00009b4c, 0x00000019 }, | ||
| 345 | { 0x00009b50, 0x0000001a }, | ||
| 346 | { 0x00009b54, 0x0000001b }, | ||
| 347 | { 0x00009b58, 0x0000001c }, | ||
| 348 | { 0x00009b5c, 0x0000001d }, | ||
| 349 | { 0x00009b60, 0x00000020 }, | ||
| 350 | { 0x00009b64, 0x00000021 }, | ||
| 351 | { 0x00009b68, 0x00000022 }, | ||
| 352 | { 0x00009b6c, 0x00000023 }, | ||
| 353 | { 0x00009b70, 0x00000024 }, | ||
| 354 | { 0x00009b74, 0x00000025 }, | ||
| 355 | { 0x00009b78, 0x00000028 }, | ||
| 356 | { 0x00009b7c, 0x00000029 }, | ||
| 357 | { 0x00009b80, 0x0000002a }, | ||
| 358 | { 0x00009b84, 0x0000002b }, | ||
| 359 | { 0x00009b88, 0x0000002c }, | ||
| 360 | { 0x00009b8c, 0x0000002d }, | ||
| 361 | { 0x00009b90, 0x00000030 }, | ||
| 362 | { 0x00009b94, 0x00000031 }, | ||
| 363 | { 0x00009b98, 0x00000032 }, | ||
| 364 | { 0x00009b9c, 0x00000033 }, | ||
| 365 | { 0x00009ba0, 0x00000034 }, | ||
| 366 | { 0x00009ba4, 0x00000035 }, | ||
| 367 | { 0x00009ba8, 0x00000035 }, | ||
| 368 | { 0x00009bac, 0x00000035 }, | ||
| 369 | { 0x00009bb0, 0x00000035 }, | ||
| 370 | { 0x00009bb4, 0x00000035 }, | ||
| 371 | { 0x00009bb8, 0x00000035 }, | ||
| 372 | { 0x00009bbc, 0x00000035 }, | ||
| 373 | { 0x00009bc0, 0x00000035 }, | ||
| 374 | { 0x00009bc4, 0x00000035 }, | ||
| 375 | { 0x00009bc8, 0x00000035 }, | ||
| 376 | { 0x00009bcc, 0x00000035 }, | ||
| 377 | { 0x00009bd0, 0x00000035 }, | ||
| 378 | { 0x00009bd4, 0x00000035 }, | ||
| 379 | { 0x00009bd8, 0x00000035 }, | ||
| 380 | { 0x00009bdc, 0x00000035 }, | ||
| 381 | { 0x00009be0, 0x00000035 }, | ||
| 382 | { 0x00009be4, 0x00000035 }, | ||
| 383 | { 0x00009be8, 0x00000035 }, | ||
| 384 | { 0x00009bec, 0x00000035 }, | ||
| 385 | { 0x00009bf0, 0x00000035 }, | ||
| 386 | { 0x00009bf4, 0x00000035 }, | ||
| 387 | { 0x00009bf8, 0x00000010 }, | ||
| 388 | { 0x00009bfc, 0x0000001a }, | ||
| 389 | { 0x0000a210, 0x40806333 }, | ||
| 390 | { 0x0000a214, 0x00106c10 }, | ||
| 391 | { 0x0000a218, 0x009c4060 }, | ||
| 392 | { 0x0000a220, 0x018830c6 }, | ||
| 393 | { 0x0000a224, 0x00000400 }, | ||
| 394 | { 0x0000a228, 0x00000bb5 }, | ||
| 395 | { 0x0000a22c, 0x00000011 }, | ||
| 396 | { 0x0000a234, 0x20202020 }, | ||
| 397 | { 0x0000a238, 0x20202020 }, | ||
| 398 | { 0x0000a23c, 0x13c889af }, | ||
| 399 | { 0x0000a240, 0x38490a20 }, | ||
| 400 | { 0x0000a244, 0x00007bb6 }, | ||
| 401 | { 0x0000a248, 0x0fff3ffc }, | ||
| 402 | { 0x0000a24c, 0x00000001 }, | ||
| 403 | { 0x0000a250, 0x0000a000 }, | ||
| 404 | { 0x0000a254, 0x00000000 }, | ||
| 405 | { 0x0000a258, 0x0cc75380 }, | ||
| 406 | { 0x0000a25c, 0x0f0f0f01 }, | ||
| 407 | { 0x0000a260, 0xdfa91f01 }, | ||
| 408 | { 0x0000a268, 0x00000000 }, | ||
| 409 | { 0x0000a26c, 0x0ebae9c6 }, | ||
| 410 | { 0x0000b26c, 0x0ebae9c6 }, | ||
| 411 | { 0x0000c26c, 0x0ebae9c6 }, | ||
| 412 | { 0x0000d270, 0x00820820 }, | ||
| 413 | { 0x0000a278, 0x1ce739ce }, | ||
| 414 | { 0x0000a27c, 0x051701ce }, | ||
| 415 | { 0x0000a338, 0x00000000 }, | ||
| 416 | { 0x0000a33c, 0x00000000 }, | ||
| 417 | { 0x0000a340, 0x00000000 }, | ||
| 418 | { 0x0000a344, 0x00000000 }, | ||
| 419 | { 0x0000a348, 0x3fffffff }, | ||
| 420 | { 0x0000a34c, 0x3fffffff }, | ||
| 421 | { 0x0000a350, 0x3fffffff }, | ||
| 422 | { 0x0000a354, 0x0003ffff }, | ||
| 423 | { 0x0000a358, 0x79a8aa1f }, | ||
| 424 | { 0x0000d35c, 0x07ffffef }, | ||
| 425 | { 0x0000d360, 0x0fffffe7 }, | ||
| 426 | { 0x0000d364, 0x17ffffe5 }, | ||
| 427 | { 0x0000d368, 0x1fffffe4 }, | ||
| 428 | { 0x0000d36c, 0x37ffffe3 }, | ||
| 429 | { 0x0000d370, 0x3fffffe3 }, | ||
| 430 | { 0x0000d374, 0x57ffffe3 }, | ||
| 431 | { 0x0000d378, 0x5fffffe2 }, | ||
| 432 | { 0x0000d37c, 0x7fffffe2 }, | ||
| 433 | { 0x0000d380, 0x7f3c7bba }, | ||
| 434 | { 0x0000d384, 0xf3307ff0 }, | ||
| 435 | { 0x0000a388, 0x08000000 }, | ||
| 436 | { 0x0000a38c, 0x20202020 }, | ||
| 437 | { 0x0000a390, 0x20202020 }, | ||
| 438 | { 0x0000a394, 0x1ce739ce }, | ||
| 439 | { 0x0000a398, 0x000001ce }, | ||
| 440 | { 0x0000a39c, 0x00000001 }, | ||
| 441 | { 0x0000a3a0, 0x00000000 }, | ||
| 442 | { 0x0000a3a4, 0x00000000 }, | ||
| 443 | { 0x0000a3a8, 0x00000000 }, | ||
| 444 | { 0x0000a3ac, 0x00000000 }, | ||
| 445 | { 0x0000a3b0, 0x00000000 }, | ||
| 446 | { 0x0000a3b4, 0x00000000 }, | ||
| 447 | { 0x0000a3b8, 0x00000000 }, | ||
| 448 | { 0x0000a3bc, 0x00000000 }, | ||
| 449 | { 0x0000a3c0, 0x00000000 }, | ||
| 450 | { 0x0000a3c4, 0x00000000 }, | ||
| 451 | { 0x0000a3c8, 0x00000246 }, | ||
| 452 | { 0x0000a3cc, 0x20202020 }, | ||
| 453 | { 0x0000a3d0, 0x20202020 }, | ||
| 454 | { 0x0000a3d4, 0x20202020 }, | ||
| 455 | { 0x0000a3dc, 0x1ce739ce }, | ||
| 456 | { 0x0000a3e0, 0x000001ce }, | ||
| 457 | }; | ||
| 458 | |||
| 459 | static const u32 ar5416Bank0_9100[][2] = { | ||
| 460 | { 0x000098b0, 0x1e5795e5 }, | ||
| 461 | { 0x000098e0, 0x02008020 }, | ||
| 462 | }; | ||
| 463 | |||
| 464 | static const u32 ar5416BB_RfGain_9100[][3] = { | ||
| 465 | { 0x00009a00, 0x00000000, 0x00000000 }, | ||
| 466 | { 0x00009a04, 0x00000040, 0x00000040 }, | ||
| 467 | { 0x00009a08, 0x00000080, 0x00000080 }, | ||
| 468 | { 0x00009a0c, 0x000001a1, 0x00000141 }, | ||
| 469 | { 0x00009a10, 0x000001e1, 0x00000181 }, | ||
| 470 | { 0x00009a14, 0x00000021, 0x000001c1 }, | ||
| 471 | { 0x00009a18, 0x00000061, 0x00000001 }, | ||
| 472 | { 0x00009a1c, 0x00000168, 0x00000041 }, | ||
| 473 | { 0x00009a20, 0x000001a8, 0x000001a8 }, | ||
| 474 | { 0x00009a24, 0x000001e8, 0x000001e8 }, | ||
| 475 | { 0x00009a28, 0x00000028, 0x00000028 }, | ||
| 476 | { 0x00009a2c, 0x00000068, 0x00000068 }, | ||
| 477 | { 0x00009a30, 0x00000189, 0x000000a8 }, | ||
| 478 | { 0x00009a34, 0x000001c9, 0x00000169 }, | ||
| 479 | { 0x00009a38, 0x00000009, 0x000001a9 }, | ||
| 480 | { 0x00009a3c, 0x00000049, 0x000001e9 }, | ||
| 481 | { 0x00009a40, 0x00000089, 0x00000029 }, | ||
| 482 | { 0x00009a44, 0x00000170, 0x00000069 }, | ||
| 483 | { 0x00009a48, 0x000001b0, 0x00000190 }, | ||
| 484 | { 0x00009a4c, 0x000001f0, 0x000001d0 }, | ||
| 485 | { 0x00009a50, 0x00000030, 0x00000010 }, | ||
| 486 | { 0x00009a54, 0x00000070, 0x00000050 }, | ||
| 487 | { 0x00009a58, 0x00000191, 0x00000090 }, | ||
| 488 | { 0x00009a5c, 0x000001d1, 0x00000151 }, | ||
| 489 | { 0x00009a60, 0x00000011, 0x00000191 }, | ||
| 490 | { 0x00009a64, 0x00000051, 0x000001d1 }, | ||
| 491 | { 0x00009a68, 0x00000091, 0x00000011 }, | ||
| 492 | { 0x00009a6c, 0x000001b8, 0x00000051 }, | ||
| 493 | { 0x00009a70, 0x000001f8, 0x00000198 }, | ||
| 494 | { 0x00009a74, 0x00000038, 0x000001d8 }, | ||
| 495 | { 0x00009a78, 0x00000078, 0x00000018 }, | ||
| 496 | { 0x00009a7c, 0x00000199, 0x00000058 }, | ||
| 497 | { 0x00009a80, 0x000001d9, 0x00000098 }, | ||
| 498 | { 0x00009a84, 0x00000019, 0x00000159 }, | ||
| 499 | { 0x00009a88, 0x00000059, 0x00000199 }, | ||
| 500 | { 0x00009a8c, 0x00000099, 0x000001d9 }, | ||
| 501 | { 0x00009a90, 0x000000d9, 0x00000019 }, | ||
| 502 | { 0x00009a94, 0x000000f9, 0x00000059 }, | ||
| 503 | { 0x00009a98, 0x000000f9, 0x00000099 }, | ||
| 504 | { 0x00009a9c, 0x000000f9, 0x000000d9 }, | ||
| 505 | { 0x00009aa0, 0x000000f9, 0x000000f9 }, | ||
| 506 | { 0x00009aa4, 0x000000f9, 0x000000f9 }, | ||
| 507 | { 0x00009aa8, 0x000000f9, 0x000000f9 }, | ||
| 508 | { 0x00009aac, 0x000000f9, 0x000000f9 }, | ||
| 509 | { 0x00009ab0, 0x000000f9, 0x000000f9 }, | ||
| 510 | { 0x00009ab4, 0x000000f9, 0x000000f9 }, | ||
| 511 | { 0x00009ab8, 0x000000f9, 0x000000f9 }, | ||
| 512 | { 0x00009abc, 0x000000f9, 0x000000f9 }, | ||
| 513 | { 0x00009ac0, 0x000000f9, 0x000000f9 }, | ||
| 514 | { 0x00009ac4, 0x000000f9, 0x000000f9 }, | ||
| 515 | { 0x00009ac8, 0x000000f9, 0x000000f9 }, | ||
| 516 | { 0x00009acc, 0x000000f9, 0x000000f9 }, | ||
| 517 | { 0x00009ad0, 0x000000f9, 0x000000f9 }, | ||
| 518 | { 0x00009ad4, 0x000000f9, 0x000000f9 }, | ||
| 519 | { 0x00009ad8, 0x000000f9, 0x000000f9 }, | ||
| 520 | { 0x00009adc, 0x000000f9, 0x000000f9 }, | ||
| 521 | { 0x00009ae0, 0x000000f9, 0x000000f9 }, | ||
| 522 | { 0x00009ae4, 0x000000f9, 0x000000f9 }, | ||
| 523 | { 0x00009ae8, 0x000000f9, 0x000000f9 }, | ||
| 524 | { 0x00009aec, 0x000000f9, 0x000000f9 }, | ||
| 525 | { 0x00009af0, 0x000000f9, 0x000000f9 }, | ||
| 526 | { 0x00009af4, 0x000000f9, 0x000000f9 }, | ||
| 527 | { 0x00009af8, 0x000000f9, 0x000000f9 }, | ||
| 528 | { 0x00009afc, 0x000000f9, 0x000000f9 }, | ||
| 529 | }; | ||
| 530 | |||
| 531 | static const u32 ar5416Bank1_9100[][2] = { | ||
| 532 | { 0x000098b0, 0x02108421 }, | ||
| 533 | { 0x000098ec, 0x00000008 }, | ||
| 534 | }; | ||
| 535 | |||
| 536 | static const u32 ar5416Bank2_9100[][2] = { | ||
| 537 | { 0x000098b0, 0x0e73ff17 }, | ||
| 538 | { 0x000098e0, 0x00000420 }, | ||
| 539 | }; | ||
| 540 | |||
| 541 | static const u32 ar5416Bank3_9100[][3] = { | ||
| 542 | { 0x000098f0, 0x01400018, 0x01c00018 }, | ||
| 543 | }; | ||
| 544 | |||
| 545 | static const u32 ar5416Bank6_9100[][3] = { | ||
| 546 | |||
| 547 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 548 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 549 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 550 | { 0x0000989c, 0x00e00000, 0x00e00000 }, | ||
| 551 | { 0x0000989c, 0x005e0000, 0x005e0000 }, | ||
| 552 | { 0x0000989c, 0x00120000, 0x00120000 }, | ||
| 553 | { 0x0000989c, 0x00620000, 0x00620000 }, | ||
| 554 | { 0x0000989c, 0x00020000, 0x00020000 }, | ||
| 555 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 556 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 557 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 558 | { 0x0000989c, 0x40ff0000, 0x40ff0000 }, | ||
| 559 | { 0x0000989c, 0x005f0000, 0x005f0000 }, | ||
| 560 | { 0x0000989c, 0x00870000, 0x00870000 }, | ||
| 561 | { 0x0000989c, 0x00f90000, 0x00f90000 }, | ||
| 562 | { 0x0000989c, 0x007b0000, 0x007b0000 }, | ||
| 563 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 564 | { 0x0000989c, 0x00f50000, 0x00f50000 }, | ||
| 565 | { 0x0000989c, 0x00dc0000, 0x00dc0000 }, | ||
| 566 | { 0x0000989c, 0x00110000, 0x00110000 }, | ||
| 567 | { 0x0000989c, 0x006100a8, 0x006100a8 }, | ||
| 568 | { 0x0000989c, 0x004210a2, 0x004210a2 }, | ||
| 569 | { 0x0000989c, 0x0014008f, 0x0014008f }, | ||
| 570 | { 0x0000989c, 0x00c40003, 0x00c40003 }, | ||
| 571 | { 0x0000989c, 0x003000f2, 0x003000f2 }, | ||
| 572 | { 0x0000989c, 0x00440016, 0x00440016 }, | ||
| 573 | { 0x0000989c, 0x00410040, 0x00410040 }, | ||
| 574 | { 0x0000989c, 0x0001805e, 0x0001805e }, | ||
| 575 | { 0x0000989c, 0x0000c0ab, 0x0000c0ab }, | ||
| 576 | { 0x0000989c, 0x000000f1, 0x000000f1 }, | ||
| 577 | { 0x0000989c, 0x00002081, 0x00002081 }, | ||
| 578 | { 0x0000989c, 0x000000d4, 0x000000d4 }, | ||
| 579 | { 0x000098d0, 0x0000000f, 0x0010000f }, | ||
| 580 | }; | ||
| 581 | |||
| 582 | static const u32 ar5416Bank6TPC_9100[][3] = { | ||
| 583 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 584 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 585 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 586 | { 0x0000989c, 0x00e00000, 0x00e00000 }, | ||
| 587 | { 0x0000989c, 0x005e0000, 0x005e0000 }, | ||
| 588 | { 0x0000989c, 0x00120000, 0x00120000 }, | ||
| 589 | { 0x0000989c, 0x00620000, 0x00620000 }, | ||
| 590 | { 0x0000989c, 0x00020000, 0x00020000 }, | ||
| 591 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 592 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 593 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 594 | { 0x0000989c, 0x40ff0000, 0x40ff0000 }, | ||
| 595 | { 0x0000989c, 0x005f0000, 0x005f0000 }, | ||
| 596 | { 0x0000989c, 0x00870000, 0x00870000 }, | ||
| 597 | { 0x0000989c, 0x00f90000, 0x00f90000 }, | ||
| 598 | { 0x0000989c, 0x007b0000, 0x007b0000 }, | ||
| 599 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 600 | { 0x0000989c, 0x00f50000, 0x00f50000 }, | ||
| 601 | { 0x0000989c, 0x00dc0000, 0x00dc0000 }, | ||
| 602 | { 0x0000989c, 0x00110000, 0x00110000 }, | ||
| 603 | { 0x0000989c, 0x006100a8, 0x006100a8 }, | ||
| 604 | { 0x0000989c, 0x00423022, 0x00423022 }, | ||
| 605 | { 0x0000989c, 0x201400df, 0x201400df }, | ||
| 606 | { 0x0000989c, 0x00c40002, 0x00c40002 }, | ||
| 607 | { 0x0000989c, 0x003000f2, 0x003000f2 }, | ||
| 608 | { 0x0000989c, 0x00440016, 0x00440016 }, | ||
| 609 | { 0x0000989c, 0x00410040, 0x00410040 }, | ||
| 610 | { 0x0000989c, 0x0001805e, 0x0001805e }, | ||
| 611 | { 0x0000989c, 0x0000c0ab, 0x0000c0ab }, | ||
| 612 | { 0x0000989c, 0x000000e1, 0x000000e1 }, | ||
| 613 | { 0x0000989c, 0x00007081, 0x00007081 }, | ||
| 614 | { 0x0000989c, 0x000000d4, 0x000000d4 }, | ||
| 615 | { 0x000098d0, 0x0000000f, 0x0010000f }, | ||
| 616 | }; | ||
| 617 | |||
| 618 | static const u32 ar5416Bank7_9100[][2] = { | ||
| 619 | { 0x0000989c, 0x00000500 }, | ||
| 620 | { 0x0000989c, 0x00000800 }, | ||
| 621 | { 0x000098cc, 0x0000000e }, | ||
| 622 | }; | ||
| 623 | |||
| 624 | static const u32 ar5416Addac_9100[][2] = { | ||
| 625 | {0x0000989c, 0x00000000 }, | ||
| 626 | {0x0000989c, 0x00000003 }, | ||
| 627 | {0x0000989c, 0x00000000 }, | ||
| 628 | {0x0000989c, 0x0000000c }, | ||
| 629 | {0x0000989c, 0x00000000 }, | ||
| 630 | {0x0000989c, 0x00000030 }, | ||
| 631 | {0x0000989c, 0x00000000 }, | ||
| 632 | {0x0000989c, 0x00000000 }, | ||
| 633 | {0x0000989c, 0x00000000 }, | ||
| 634 | {0x0000989c, 0x00000000 }, | ||
| 635 | {0x0000989c, 0x00000000 }, | ||
| 636 | {0x0000989c, 0x00000000 }, | ||
| 637 | {0x0000989c, 0x00000000 }, | ||
| 638 | {0x0000989c, 0x00000000 }, | ||
| 639 | {0x0000989c, 0x00000000 }, | ||
| 640 | {0x0000989c, 0x00000000 }, | ||
| 641 | {0x0000989c, 0x00000000 }, | ||
| 642 | {0x0000989c, 0x00000000 }, | ||
| 643 | {0x0000989c, 0x00000060 }, | ||
| 644 | {0x0000989c, 0x00000000 }, | ||
| 645 | {0x0000989c, 0x00000000 }, | ||
| 646 | {0x0000989c, 0x00000000 }, | ||
| 647 | {0x0000989c, 0x00000000 }, | ||
| 648 | {0x0000989c, 0x00000000 }, | ||
| 649 | {0x0000989c, 0x00000000 }, | ||
| 650 | {0x0000989c, 0x00000000 }, | ||
| 651 | {0x0000989c, 0x00000000 }, | ||
| 652 | {0x0000989c, 0x00000000 }, | ||
| 653 | {0x0000989c, 0x00000000 }, | ||
| 654 | {0x0000989c, 0x00000000 }, | ||
| 655 | {0x0000989c, 0x00000000 }, | ||
| 656 | {0x0000989c, 0x00000058 }, | ||
| 657 | {0x0000989c, 0x00000000 }, | ||
| 658 | {0x0000989c, 0x00000000 }, | ||
| 659 | {0x0000989c, 0x00000000 }, | ||
| 660 | {0x0000989c, 0x00000000 }, | ||
| 661 | {0x000098c4, 0x00000000 }, | ||
| 662 | }; | ||
| 663 | |||
| 664 | static const u32 ar5416Modes[][6] = { | ||
| 665 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | ||
| 666 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | ||
| 667 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | ||
| 668 | { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, | ||
| 669 | { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, | ||
| 670 | { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf }, | ||
| 671 | { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, | ||
| 672 | { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, | ||
| 673 | { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 674 | { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, | ||
| 675 | { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 676 | { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, | ||
| 677 | { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 }, | ||
| 678 | { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 679 | { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 680 | { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 681 | { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 }, | ||
| 682 | { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e }, | ||
| 683 | { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e }, | ||
| 684 | { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 }, | ||
| 685 | { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, | ||
| 686 | { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 }, | ||
| 687 | { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, | ||
| 688 | { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 }, | ||
| 689 | { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, | ||
| 690 | { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d }, | ||
| 691 | { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 }, | ||
| 692 | { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 }, | ||
| 693 | { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e }, | ||
| 694 | { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff }, | ||
| 695 | #ifdef TB243 | ||
| 696 | { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 }, | ||
| 697 | { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 }, | ||
| 698 | { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 }, | ||
| 699 | { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 }, | ||
| 700 | #else | ||
| 701 | { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 }, | ||
| 702 | { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 }, | ||
| 703 | { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 }, | ||
| 704 | { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 }, | ||
| 705 | #endif | ||
| 706 | { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 }, | ||
| 707 | { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, | ||
| 708 | { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, | ||
| 709 | { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 }, | ||
| 710 | { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, | ||
| 711 | { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, | ||
| 712 | { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 713 | { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 714 | { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 }, | ||
| 715 | { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 }, | ||
| 716 | { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 717 | { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 718 | { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 719 | { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, | ||
| 720 | { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, | ||
| 721 | { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa }, | ||
| 722 | { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 }, | ||
| 723 | { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 }, | ||
| 724 | { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 }, | ||
| 725 | { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b }, | ||
| 726 | { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b }, | ||
| 727 | { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a }, | ||
| 728 | { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf }, | ||
| 729 | { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f }, | ||
| 730 | { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f }, | ||
| 731 | { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f }, | ||
| 732 | { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 733 | { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 734 | { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 735 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 736 | }; | ||
| 737 | |||
| 738 | static const u32 ar5416Common[][2] = { | ||
| 739 | { 0x0000000c, 0x00000000 }, | ||
| 740 | { 0x00000030, 0x00020015 }, | ||
| 741 | { 0x00000034, 0x00000005 }, | ||
| 742 | { 0x00000040, 0x00000000 }, | ||
| 743 | { 0x00000044, 0x00000008 }, | ||
| 744 | { 0x00000048, 0x00000008 }, | ||
| 745 | { 0x0000004c, 0x00000010 }, | ||
| 746 | { 0x00000050, 0x00000000 }, | ||
| 747 | { 0x00000054, 0x0000001f }, | ||
| 748 | { 0x00000800, 0x00000000 }, | ||
| 749 | { 0x00000804, 0x00000000 }, | ||
| 750 | { 0x00000808, 0x00000000 }, | ||
| 751 | { 0x0000080c, 0x00000000 }, | ||
| 752 | { 0x00000810, 0x00000000 }, | ||
| 753 | { 0x00000814, 0x00000000 }, | ||
| 754 | { 0x00000818, 0x00000000 }, | ||
| 755 | { 0x0000081c, 0x00000000 }, | ||
| 756 | { 0x00000820, 0x00000000 }, | ||
| 757 | { 0x00000824, 0x00000000 }, | ||
| 758 | { 0x00001040, 0x002ffc0f }, | ||
| 759 | { 0x00001044, 0x002ffc0f }, | ||
| 760 | { 0x00001048, 0x002ffc0f }, | ||
| 761 | { 0x0000104c, 0x002ffc0f }, | ||
| 762 | { 0x00001050, 0x002ffc0f }, | ||
| 763 | { 0x00001054, 0x002ffc0f }, | ||
| 764 | { 0x00001058, 0x002ffc0f }, | ||
| 765 | { 0x0000105c, 0x002ffc0f }, | ||
| 766 | { 0x00001060, 0x002ffc0f }, | ||
| 767 | { 0x00001064, 0x002ffc0f }, | ||
| 768 | { 0x00001230, 0x00000000 }, | ||
| 769 | { 0x00001270, 0x00000000 }, | ||
| 770 | { 0x00001038, 0x00000000 }, | ||
| 771 | { 0x00001078, 0x00000000 }, | ||
| 772 | { 0x000010b8, 0x00000000 }, | ||
| 773 | { 0x000010f8, 0x00000000 }, | ||
| 774 | { 0x00001138, 0x00000000 }, | ||
| 775 | { 0x00001178, 0x00000000 }, | ||
| 776 | { 0x000011b8, 0x00000000 }, | ||
| 777 | { 0x000011f8, 0x00000000 }, | ||
| 778 | { 0x00001238, 0x00000000 }, | ||
| 779 | { 0x00001278, 0x00000000 }, | ||
| 780 | { 0x000012b8, 0x00000000 }, | ||
| 781 | { 0x000012f8, 0x00000000 }, | ||
| 782 | { 0x00001338, 0x00000000 }, | ||
| 783 | { 0x00001378, 0x00000000 }, | ||
| 784 | { 0x000013b8, 0x00000000 }, | ||
| 785 | { 0x000013f8, 0x00000000 }, | ||
| 786 | { 0x00001438, 0x00000000 }, | ||
| 787 | { 0x00001478, 0x00000000 }, | ||
| 788 | { 0x000014b8, 0x00000000 }, | ||
| 789 | { 0x000014f8, 0x00000000 }, | ||
| 790 | { 0x00001538, 0x00000000 }, | ||
| 791 | { 0x00001578, 0x00000000 }, | ||
| 792 | { 0x000015b8, 0x00000000 }, | ||
| 793 | { 0x000015f8, 0x00000000 }, | ||
| 794 | { 0x00001638, 0x00000000 }, | ||
| 795 | { 0x00001678, 0x00000000 }, | ||
| 796 | { 0x000016b8, 0x00000000 }, | ||
| 797 | { 0x000016f8, 0x00000000 }, | ||
| 798 | { 0x00001738, 0x00000000 }, | ||
| 799 | { 0x00001778, 0x00000000 }, | ||
| 800 | { 0x000017b8, 0x00000000 }, | ||
| 801 | { 0x000017f8, 0x00000000 }, | ||
| 802 | { 0x0000103c, 0x00000000 }, | ||
| 803 | { 0x0000107c, 0x00000000 }, | ||
| 804 | { 0x000010bc, 0x00000000 }, | ||
| 805 | { 0x000010fc, 0x00000000 }, | ||
| 806 | { 0x0000113c, 0x00000000 }, | ||
| 807 | { 0x0000117c, 0x00000000 }, | ||
| 808 | { 0x000011bc, 0x00000000 }, | ||
| 809 | { 0x000011fc, 0x00000000 }, | ||
| 810 | { 0x0000123c, 0x00000000 }, | ||
| 811 | { 0x0000127c, 0x00000000 }, | ||
| 812 | { 0x000012bc, 0x00000000 }, | ||
| 813 | { 0x000012fc, 0x00000000 }, | ||
| 814 | { 0x0000133c, 0x00000000 }, | ||
| 815 | { 0x0000137c, 0x00000000 }, | ||
| 816 | { 0x000013bc, 0x00000000 }, | ||
| 817 | { 0x000013fc, 0x00000000 }, | ||
| 818 | { 0x0000143c, 0x00000000 }, | ||
| 819 | { 0x0000147c, 0x00000000 }, | ||
| 820 | { 0x00020010, 0x00000003 }, | ||
| 821 | { 0x00020038, 0x000004c2 }, | ||
| 822 | { 0x00008004, 0x00000000 }, | ||
| 823 | { 0x00008008, 0x00000000 }, | ||
| 824 | { 0x0000800c, 0x00000000 }, | ||
| 825 | { 0x00008018, 0x00000700 }, | ||
| 826 | { 0x00008020, 0x00000000 }, | ||
| 827 | { 0x00008038, 0x00000000 }, | ||
| 828 | { 0x0000803c, 0x00000000 }, | ||
| 829 | { 0x00008048, 0x40000000 }, | ||
| 830 | { 0x00008054, 0x00004000 }, | ||
| 831 | { 0x00008058, 0x00000000 }, | ||
| 832 | { 0x0000805c, 0x000fc78f }, | ||
| 833 | { 0x00008060, 0x0000000f }, | ||
| 834 | { 0x00008064, 0x00000000 }, | ||
| 835 | { 0x000080c0, 0x2a82301a }, | ||
| 836 | { 0x000080c4, 0x05dc01e0 }, | ||
| 837 | { 0x000080c8, 0x1f402710 }, | ||
| 838 | { 0x000080cc, 0x01f40000 }, | ||
| 839 | { 0x000080d0, 0x00001e00 }, | ||
| 840 | { 0x000080d4, 0x00000000 }, | ||
| 841 | { 0x000080d8, 0x00400000 }, | ||
| 842 | { 0x000080e0, 0xffffffff }, | ||
| 843 | { 0x000080e4, 0x0000ffff }, | ||
| 844 | { 0x000080e8, 0x003f3f3f }, | ||
| 845 | { 0x000080ec, 0x00000000 }, | ||
| 846 | { 0x000080f0, 0x00000000 }, | ||
| 847 | { 0x000080f4, 0x00000000 }, | ||
| 848 | { 0x000080f8, 0x00000000 }, | ||
| 849 | { 0x000080fc, 0x00020000 }, | ||
| 850 | { 0x00008100, 0x00020000 }, | ||
| 851 | { 0x00008104, 0x00000001 }, | ||
| 852 | { 0x00008108, 0x00000052 }, | ||
| 853 | { 0x0000810c, 0x00000000 }, | ||
| 854 | { 0x00008110, 0x00000168 }, | ||
| 855 | { 0x00008118, 0x000100aa }, | ||
| 856 | { 0x0000811c, 0x00003210 }, | ||
| 857 | { 0x00008120, 0x08f04800 }, | ||
| 858 | { 0x00008124, 0x00000000 }, | ||
| 859 | { 0x00008128, 0x00000000 }, | ||
| 860 | { 0x0000812c, 0x00000000 }, | ||
| 861 | { 0x00008130, 0x00000000 }, | ||
| 862 | { 0x00008134, 0x00000000 }, | ||
| 863 | { 0x00008138, 0x00000000 }, | ||
| 864 | { 0x0000813c, 0x00000000 }, | ||
| 865 | { 0x00008144, 0x00000000 }, | ||
| 866 | { 0x00008168, 0x00000000 }, | ||
| 867 | { 0x0000816c, 0x00000000 }, | ||
| 868 | { 0x00008170, 0x32143320 }, | ||
| 869 | { 0x00008174, 0xfaa4fa50 }, | ||
| 870 | { 0x00008178, 0x00000100 }, | ||
| 871 | { 0x0000817c, 0x00000000 }, | ||
| 872 | { 0x000081c4, 0x00000000 }, | ||
| 873 | { 0x000081d0, 0x00003210 }, | ||
| 874 | { 0x000081ec, 0x00000000 }, | ||
| 875 | { 0x000081f0, 0x00000000 }, | ||
| 876 | { 0x000081f4, 0x00000000 }, | ||
| 877 | { 0x000081f8, 0x00000000 }, | ||
| 878 | { 0x000081fc, 0x00000000 }, | ||
| 879 | { 0x00008200, 0x00000000 }, | ||
| 880 | { 0x00008204, 0x00000000 }, | ||
| 881 | { 0x00008208, 0x00000000 }, | ||
| 882 | { 0x0000820c, 0x00000000 }, | ||
| 883 | { 0x00008210, 0x00000000 }, | ||
| 884 | { 0x00008214, 0x00000000 }, | ||
| 885 | { 0x00008218, 0x00000000 }, | ||
| 886 | { 0x0000821c, 0x00000000 }, | ||
| 887 | { 0x00008220, 0x00000000 }, | ||
| 888 | { 0x00008224, 0x00000000 }, | ||
| 889 | { 0x00008228, 0x00000000 }, | ||
| 890 | { 0x0000822c, 0x00000000 }, | ||
| 891 | { 0x00008230, 0x00000000 }, | ||
| 892 | { 0x00008234, 0x00000000 }, | ||
| 893 | { 0x00008238, 0x00000000 }, | ||
| 894 | { 0x0000823c, 0x00000000 }, | ||
| 895 | { 0x00008240, 0x00100000 }, | ||
| 896 | { 0x00008244, 0x0010f400 }, | ||
| 897 | { 0x00008248, 0x00000100 }, | ||
| 898 | { 0x0000824c, 0x0001e800 }, | ||
| 899 | { 0x00008250, 0x00000000 }, | ||
| 900 | { 0x00008254, 0x00000000 }, | ||
| 901 | { 0x00008258, 0x00000000 }, | ||
| 902 | { 0x0000825c, 0x400000ff }, | ||
| 903 | { 0x00008260, 0x00080922 }, | ||
| 904 | { 0x00008270, 0x00000000 }, | ||
| 905 | { 0x00008274, 0x40000000 }, | ||
| 906 | { 0x00008278, 0x003e4180 }, | ||
| 907 | { 0x0000827c, 0x00000000 }, | ||
| 908 | { 0x00008284, 0x0000002c }, | ||
| 909 | { 0x00008288, 0x0000002c }, | ||
| 910 | { 0x0000828c, 0x00000000 }, | ||
| 911 | { 0x00008294, 0x00000000 }, | ||
| 912 | { 0x00008298, 0x00000000 }, | ||
| 913 | { 0x00008300, 0x00000000 }, | ||
| 914 | { 0x00008304, 0x00000000 }, | ||
| 915 | { 0x00008308, 0x00000000 }, | ||
| 916 | { 0x0000830c, 0x00000000 }, | ||
| 917 | { 0x00008310, 0x00000000 }, | ||
| 918 | { 0x00008314, 0x00000000 }, | ||
| 919 | { 0x00008318, 0x00000000 }, | ||
| 920 | { 0x00008328, 0x00000000 }, | ||
| 921 | { 0x0000832c, 0x00000007 }, | ||
| 922 | { 0x00008330, 0x00000302 }, | ||
| 923 | { 0x00008334, 0x00000e00 }, | ||
| 924 | { 0x00008338, 0x00000000 }, | ||
| 925 | { 0x0000833c, 0x00000000 }, | ||
| 926 | { 0x00008340, 0x000107ff }, | ||
| 927 | { 0x00009808, 0x00000000 }, | ||
| 928 | { 0x0000980c, 0xad848e19 }, | ||
| 929 | { 0x00009810, 0x7d14e000 }, | ||
| 930 | { 0x00009814, 0x9c0a9f6b }, | ||
| 931 | { 0x0000981c, 0x00000000 }, | ||
| 932 | { 0x0000982c, 0x0000a000 }, | ||
| 933 | { 0x00009830, 0x00000000 }, | ||
| 934 | { 0x0000983c, 0x00200400 }, | ||
| 935 | { 0x00009840, 0x206a01ae }, | ||
| 936 | { 0x0000984c, 0x1284233c }, | ||
| 937 | { 0x00009854, 0x00000859 }, | ||
| 938 | { 0x00009900, 0x00000000 }, | ||
| 939 | { 0x00009904, 0x00000000 }, | ||
| 940 | { 0x00009908, 0x00000000 }, | ||
| 941 | { 0x0000990c, 0x00000000 }, | ||
| 942 | { 0x0000991c, 0x10000fff }, | ||
| 943 | { 0x00009920, 0x05100000 }, | ||
| 944 | { 0x0000a920, 0x05100000 }, | ||
| 945 | { 0x0000b920, 0x05100000 }, | ||
| 946 | { 0x00009928, 0x00000001 }, | ||
| 947 | { 0x0000992c, 0x00000004 }, | ||
| 948 | { 0x00009934, 0x1e1f2022 }, | ||
| 949 | { 0x00009938, 0x0a0b0c0d }, | ||
| 950 | { 0x0000993c, 0x00000000 }, | ||
| 951 | { 0x00009948, 0x9280b212 }, | ||
| 952 | { 0x0000994c, 0x00020028 }, | ||
| 953 | { 0x0000c95c, 0x004b6a8e }, | ||
| 954 | { 0x0000c968, 0x000003ce }, | ||
| 955 | { 0x00009970, 0x190fb514 }, | ||
| 956 | { 0x00009974, 0x00000000 }, | ||
| 957 | { 0x00009978, 0x00000001 }, | ||
| 958 | { 0x0000997c, 0x00000000 }, | ||
| 959 | { 0x00009980, 0x00000000 }, | ||
| 960 | { 0x00009984, 0x00000000 }, | ||
| 961 | { 0x00009988, 0x00000000 }, | ||
| 962 | { 0x0000998c, 0x00000000 }, | ||
| 963 | { 0x00009990, 0x00000000 }, | ||
| 964 | { 0x00009994, 0x00000000 }, | ||
| 965 | { 0x00009998, 0x00000000 }, | ||
| 966 | { 0x0000999c, 0x00000000 }, | ||
| 967 | { 0x000099a0, 0x00000000 }, | ||
| 968 | { 0x000099a4, 0x00000001 }, | ||
| 969 | { 0x000099a8, 0x201fff00 }, | ||
| 970 | { 0x000099ac, 0x006f0000 }, | ||
| 971 | { 0x000099b0, 0x03051000 }, | ||
| 972 | { 0x000099dc, 0x00000000 }, | ||
| 973 | { 0x000099e0, 0x00000200 }, | ||
| 974 | { 0x000099e4, 0xaaaaaaaa }, | ||
| 975 | { 0x000099e8, 0x3c466478 }, | ||
| 976 | { 0x000099ec, 0x0cc80caa }, | ||
| 977 | { 0x000099fc, 0x00001042 }, | ||
| 978 | { 0x00009b00, 0x00000000 }, | ||
| 979 | { 0x00009b04, 0x00000001 }, | ||
| 980 | { 0x00009b08, 0x00000002 }, | ||
| 981 | { 0x00009b0c, 0x00000003 }, | ||
| 982 | { 0x00009b10, 0x00000004 }, | ||
| 983 | { 0x00009b14, 0x00000005 }, | ||
| 984 | { 0x00009b18, 0x00000008 }, | ||
| 985 | { 0x00009b1c, 0x00000009 }, | ||
| 986 | { 0x00009b20, 0x0000000a }, | ||
| 987 | { 0x00009b24, 0x0000000b }, | ||
| 988 | { 0x00009b28, 0x0000000c }, | ||
| 989 | { 0x00009b2c, 0x0000000d }, | ||
| 990 | { 0x00009b30, 0x00000010 }, | ||
| 991 | { 0x00009b34, 0x00000011 }, | ||
| 992 | { 0x00009b38, 0x00000012 }, | ||
| 993 | { 0x00009b3c, 0x00000013 }, | ||
| 994 | { 0x00009b40, 0x00000014 }, | ||
| 995 | { 0x00009b44, 0x00000015 }, | ||
| 996 | { 0x00009b48, 0x00000018 }, | ||
| 997 | { 0x00009b4c, 0x00000019 }, | ||
| 998 | { 0x00009b50, 0x0000001a }, | ||
| 999 | { 0x00009b54, 0x0000001b }, | ||
| 1000 | { 0x00009b58, 0x0000001c }, | ||
| 1001 | { 0x00009b5c, 0x0000001d }, | ||
| 1002 | { 0x00009b60, 0x00000020 }, | ||
| 1003 | { 0x00009b64, 0x00000021 }, | ||
| 1004 | { 0x00009b68, 0x00000022 }, | ||
| 1005 | { 0x00009b6c, 0x00000023 }, | ||
| 1006 | { 0x00009b70, 0x00000024 }, | ||
| 1007 | { 0x00009b74, 0x00000025 }, | ||
| 1008 | { 0x00009b78, 0x00000028 }, | ||
| 1009 | { 0x00009b7c, 0x00000029 }, | ||
| 1010 | { 0x00009b80, 0x0000002a }, | ||
| 1011 | { 0x00009b84, 0x0000002b }, | ||
| 1012 | { 0x00009b88, 0x0000002c }, | ||
| 1013 | { 0x00009b8c, 0x0000002d }, | ||
| 1014 | { 0x00009b90, 0x00000030 }, | ||
| 1015 | { 0x00009b94, 0x00000031 }, | ||
| 1016 | { 0x00009b98, 0x00000032 }, | ||
| 1017 | { 0x00009b9c, 0x00000033 }, | ||
| 1018 | { 0x00009ba0, 0x00000034 }, | ||
| 1019 | { 0x00009ba4, 0x00000035 }, | ||
| 1020 | { 0x00009ba8, 0x00000035 }, | ||
| 1021 | { 0x00009bac, 0x00000035 }, | ||
| 1022 | { 0x00009bb0, 0x00000035 }, | ||
| 1023 | { 0x00009bb4, 0x00000035 }, | ||
| 1024 | { 0x00009bb8, 0x00000035 }, | ||
| 1025 | { 0x00009bbc, 0x00000035 }, | ||
| 1026 | { 0x00009bc0, 0x00000035 }, | ||
| 1027 | { 0x00009bc4, 0x00000035 }, | ||
| 1028 | { 0x00009bc8, 0x00000035 }, | ||
| 1029 | { 0x00009bcc, 0x00000035 }, | ||
| 1030 | { 0x00009bd0, 0x00000035 }, | ||
| 1031 | { 0x00009bd4, 0x00000035 }, | ||
| 1032 | { 0x00009bd8, 0x00000035 }, | ||
| 1033 | { 0x00009bdc, 0x00000035 }, | ||
| 1034 | { 0x00009be0, 0x00000035 }, | ||
| 1035 | { 0x00009be4, 0x00000035 }, | ||
| 1036 | { 0x00009be8, 0x00000035 }, | ||
| 1037 | { 0x00009bec, 0x00000035 }, | ||
| 1038 | { 0x00009bf0, 0x00000035 }, | ||
| 1039 | { 0x00009bf4, 0x00000035 }, | ||
| 1040 | { 0x00009bf8, 0x00000010 }, | ||
| 1041 | { 0x00009bfc, 0x0000001a }, | ||
| 1042 | { 0x0000a210, 0x40806333 }, | ||
| 1043 | { 0x0000a214, 0x00106c10 }, | ||
| 1044 | { 0x0000a218, 0x009c4060 }, | ||
| 1045 | { 0x0000a220, 0x018830c6 }, | ||
| 1046 | { 0x0000a224, 0x00000400 }, | ||
| 1047 | { 0x0000a228, 0x001a0bb5 }, | ||
| 1048 | { 0x0000a22c, 0x00000000 }, | ||
| 1049 | { 0x0000a234, 0x20202020 }, | ||
| 1050 | { 0x0000a238, 0x20202020 }, | ||
| 1051 | { 0x0000a23c, 0x13c889ae }, | ||
| 1052 | { 0x0000a240, 0x38490a20 }, | ||
| 1053 | { 0x0000a244, 0x00007bb6 }, | ||
| 1054 | { 0x0000a248, 0x0fff3ffc }, | ||
| 1055 | { 0x0000a24c, 0x00000001 }, | ||
| 1056 | { 0x0000a250, 0x0000a000 }, | ||
| 1057 | { 0x0000a254, 0x00000000 }, | ||
| 1058 | { 0x0000a258, 0x0cc75380 }, | ||
| 1059 | { 0x0000a25c, 0x0f0f0f01 }, | ||
| 1060 | { 0x0000a260, 0xdfa91f01 }, | ||
| 1061 | { 0x0000a268, 0x00000001 }, | ||
| 1062 | { 0x0000a26c, 0x0ebae9c6 }, | ||
| 1063 | { 0x0000b26c, 0x0ebae9c6 }, | ||
| 1064 | { 0x0000c26c, 0x0ebae9c6 }, | ||
| 1065 | { 0x0000d270, 0x00820820 }, | ||
| 1066 | { 0x0000a278, 0x1ce739ce }, | ||
| 1067 | { 0x0000a27c, 0x050701ce }, | ||
| 1068 | { 0x0000a338, 0x00000000 }, | ||
| 1069 | { 0x0000a33c, 0x00000000 }, | ||
| 1070 | { 0x0000a340, 0x00000000 }, | ||
| 1071 | { 0x0000a344, 0x00000000 }, | ||
| 1072 | { 0x0000a348, 0x3fffffff }, | ||
| 1073 | { 0x0000a34c, 0x3fffffff }, | ||
| 1074 | { 0x0000a350, 0x3fffffff }, | ||
| 1075 | { 0x0000a354, 0x0003ffff }, | ||
| 1076 | { 0x0000a358, 0x79a8aa33 }, | ||
| 1077 | { 0x0000d35c, 0x07ffffef }, | ||
| 1078 | { 0x0000d360, 0x0fffffe7 }, | ||
| 1079 | { 0x0000d364, 0x17ffffe5 }, | ||
| 1080 | { 0x0000d368, 0x1fffffe4 }, | ||
| 1081 | { 0x0000d36c, 0x37ffffe3 }, | ||
| 1082 | { 0x0000d370, 0x3fffffe3 }, | ||
| 1083 | { 0x0000d374, 0x57ffffe3 }, | ||
| 1084 | { 0x0000d378, 0x5fffffe2 }, | ||
| 1085 | { 0x0000d37c, 0x7fffffe2 }, | ||
| 1086 | { 0x0000d380, 0x7f3c7bba }, | ||
| 1087 | { 0x0000d384, 0xf3307ff0 }, | ||
| 1088 | { 0x0000a388, 0x0c000000 }, | ||
| 1089 | { 0x0000a38c, 0x20202020 }, | ||
| 1090 | { 0x0000a390, 0x20202020 }, | ||
| 1091 | { 0x0000a394, 0x1ce739ce }, | ||
| 1092 | { 0x0000a398, 0x000001ce }, | ||
| 1093 | { 0x0000a39c, 0x00000001 }, | ||
| 1094 | { 0x0000a3a0, 0x00000000 }, | ||
| 1095 | { 0x0000a3a4, 0x00000000 }, | ||
| 1096 | { 0x0000a3a8, 0x00000000 }, | ||
| 1097 | { 0x0000a3ac, 0x00000000 }, | ||
| 1098 | { 0x0000a3b0, 0x00000000 }, | ||
| 1099 | { 0x0000a3b4, 0x00000000 }, | ||
| 1100 | { 0x0000a3b8, 0x00000000 }, | ||
| 1101 | { 0x0000a3bc, 0x00000000 }, | ||
| 1102 | { 0x0000a3c0, 0x00000000 }, | ||
| 1103 | { 0x0000a3c4, 0x00000000 }, | ||
| 1104 | { 0x0000a3c8, 0x00000246 }, | ||
| 1105 | { 0x0000a3cc, 0x20202020 }, | ||
| 1106 | { 0x0000a3d0, 0x20202020 }, | ||
| 1107 | { 0x0000a3d4, 0x20202020 }, | ||
| 1108 | { 0x0000a3dc, 0x1ce739ce }, | ||
| 1109 | { 0x0000a3e0, 0x000001ce }, | ||
| 1110 | }; | ||
| 1111 | |||
| 1112 | static const u32 ar5416Bank0[][2] = { | ||
| 1113 | { 0x000098b0, 0x1e5795e5 }, | ||
| 1114 | { 0x000098e0, 0x02008020 }, | ||
| 1115 | }; | ||
| 1116 | |||
| 1117 | static const u32 ar5416BB_RfGain[][3] = { | ||
| 1118 | { 0x00009a00, 0x00000000, 0x00000000 }, | ||
| 1119 | { 0x00009a04, 0x00000040, 0x00000040 }, | ||
| 1120 | { 0x00009a08, 0x00000080, 0x00000080 }, | ||
| 1121 | { 0x00009a0c, 0x000001a1, 0x00000141 }, | ||
| 1122 | { 0x00009a10, 0x000001e1, 0x00000181 }, | ||
| 1123 | { 0x00009a14, 0x00000021, 0x000001c1 }, | ||
| 1124 | { 0x00009a18, 0x00000061, 0x00000001 }, | ||
| 1125 | { 0x00009a1c, 0x00000168, 0x00000041 }, | ||
| 1126 | { 0x00009a20, 0x000001a8, 0x000001a8 }, | ||
| 1127 | { 0x00009a24, 0x000001e8, 0x000001e8 }, | ||
| 1128 | { 0x00009a28, 0x00000028, 0x00000028 }, | ||
| 1129 | { 0x00009a2c, 0x00000068, 0x00000068 }, | ||
| 1130 | { 0x00009a30, 0x00000189, 0x000000a8 }, | ||
| 1131 | { 0x00009a34, 0x000001c9, 0x00000169 }, | ||
| 1132 | { 0x00009a38, 0x00000009, 0x000001a9 }, | ||
| 1133 | { 0x00009a3c, 0x00000049, 0x000001e9 }, | ||
| 1134 | { 0x00009a40, 0x00000089, 0x00000029 }, | ||
| 1135 | { 0x00009a44, 0x00000170, 0x00000069 }, | ||
| 1136 | { 0x00009a48, 0x000001b0, 0x00000190 }, | ||
| 1137 | { 0x00009a4c, 0x000001f0, 0x000001d0 }, | ||
| 1138 | { 0x00009a50, 0x00000030, 0x00000010 }, | ||
| 1139 | { 0x00009a54, 0x00000070, 0x00000050 }, | ||
| 1140 | { 0x00009a58, 0x00000191, 0x00000090 }, | ||
| 1141 | { 0x00009a5c, 0x000001d1, 0x00000151 }, | ||
| 1142 | { 0x00009a60, 0x00000011, 0x00000191 }, | ||
| 1143 | { 0x00009a64, 0x00000051, 0x000001d1 }, | ||
| 1144 | { 0x00009a68, 0x00000091, 0x00000011 }, | ||
| 1145 | { 0x00009a6c, 0x000001b8, 0x00000051 }, | ||
| 1146 | { 0x00009a70, 0x000001f8, 0x00000198 }, | ||
| 1147 | { 0x00009a74, 0x00000038, 0x000001d8 }, | ||
| 1148 | { 0x00009a78, 0x00000078, 0x00000018 }, | ||
| 1149 | { 0x00009a7c, 0x00000199, 0x00000058 }, | ||
| 1150 | { 0x00009a80, 0x000001d9, 0x00000098 }, | ||
| 1151 | { 0x00009a84, 0x00000019, 0x00000159 }, | ||
| 1152 | { 0x00009a88, 0x00000059, 0x00000199 }, | ||
| 1153 | { 0x00009a8c, 0x00000099, 0x000001d9 }, | ||
| 1154 | { 0x00009a90, 0x000000d9, 0x00000019 }, | ||
| 1155 | { 0x00009a94, 0x000000f9, 0x00000059 }, | ||
| 1156 | { 0x00009a98, 0x000000f9, 0x00000099 }, | ||
| 1157 | { 0x00009a9c, 0x000000f9, 0x000000d9 }, | ||
| 1158 | { 0x00009aa0, 0x000000f9, 0x000000f9 }, | ||
| 1159 | { 0x00009aa4, 0x000000f9, 0x000000f9 }, | ||
| 1160 | { 0x00009aa8, 0x000000f9, 0x000000f9 }, | ||
| 1161 | { 0x00009aac, 0x000000f9, 0x000000f9 }, | ||
| 1162 | { 0x00009ab0, 0x000000f9, 0x000000f9 }, | ||
| 1163 | { 0x00009ab4, 0x000000f9, 0x000000f9 }, | ||
| 1164 | { 0x00009ab8, 0x000000f9, 0x000000f9 }, | ||
| 1165 | { 0x00009abc, 0x000000f9, 0x000000f9 }, | ||
| 1166 | { 0x00009ac0, 0x000000f9, 0x000000f9 }, | ||
| 1167 | { 0x00009ac4, 0x000000f9, 0x000000f9 }, | ||
| 1168 | { 0x00009ac8, 0x000000f9, 0x000000f9 }, | ||
| 1169 | { 0x00009acc, 0x000000f9, 0x000000f9 }, | ||
| 1170 | { 0x00009ad0, 0x000000f9, 0x000000f9 }, | ||
| 1171 | { 0x00009ad4, 0x000000f9, 0x000000f9 }, | ||
| 1172 | { 0x00009ad8, 0x000000f9, 0x000000f9 }, | ||
| 1173 | { 0x00009adc, 0x000000f9, 0x000000f9 }, | ||
| 1174 | { 0x00009ae0, 0x000000f9, 0x000000f9 }, | ||
| 1175 | { 0x00009ae4, 0x000000f9, 0x000000f9 }, | ||
| 1176 | { 0x00009ae8, 0x000000f9, 0x000000f9 }, | ||
| 1177 | { 0x00009aec, 0x000000f9, 0x000000f9 }, | ||
| 1178 | { 0x00009af0, 0x000000f9, 0x000000f9 }, | ||
| 1179 | { 0x00009af4, 0x000000f9, 0x000000f9 }, | ||
| 1180 | { 0x00009af8, 0x000000f9, 0x000000f9 }, | ||
| 1181 | { 0x00009afc, 0x000000f9, 0x000000f9 }, | ||
| 1182 | }; | ||
| 1183 | |||
| 1184 | static const u32 ar5416Bank1[][2] = { | ||
| 1185 | { 0x000098b0, 0x02108421}, | ||
| 1186 | { 0x000098ec, 0x00000008}, | ||
| 1187 | }; | ||
| 1188 | |||
| 1189 | static const u32 ar5416Bank2[][2] = { | ||
| 1190 | { 0x000098b0, 0x0e73ff17}, | ||
| 1191 | { 0x000098e0, 0x00000420}, | ||
| 1192 | }; | ||
| 1193 | |||
| 1194 | static const u32 ar5416Bank3[][3] = { | ||
| 1195 | { 0x000098f0, 0x01400018, 0x01c00018 }, | ||
| 1196 | }; | ||
| 1197 | |||
| 1198 | static const u32 ar5416Bank6[][3] = { | ||
| 1199 | |||
| 1200 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1201 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1202 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1203 | { 0x0000989c, 0x00e00000, 0x00e00000 }, | ||
| 1204 | { 0x0000989c, 0x005e0000, 0x005e0000 }, | ||
| 1205 | { 0x0000989c, 0x00120000, 0x00120000 }, | ||
| 1206 | { 0x0000989c, 0x00620000, 0x00620000 }, | ||
| 1207 | { 0x0000989c, 0x00020000, 0x00020000 }, | ||
| 1208 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1209 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1210 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1211 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1212 | { 0x0000989c, 0x005f0000, 0x005f0000 }, | ||
| 1213 | { 0x0000989c, 0x00870000, 0x00870000 }, | ||
| 1214 | { 0x0000989c, 0x00f90000, 0x00f90000 }, | ||
| 1215 | { 0x0000989c, 0x007b0000, 0x007b0000 }, | ||
| 1216 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1217 | { 0x0000989c, 0x00f50000, 0x00f50000 }, | ||
| 1218 | { 0x0000989c, 0x00dc0000, 0x00dc0000 }, | ||
| 1219 | { 0x0000989c, 0x00110000, 0x00110000 }, | ||
| 1220 | { 0x0000989c, 0x006100a8, 0x006100a8 }, | ||
| 1221 | { 0x0000989c, 0x004210a2, 0x004210a2 }, | ||
| 1222 | { 0x0000989c, 0x0014000f, 0x0014000f }, | ||
| 1223 | { 0x0000989c, 0x00c40002, 0x00c40002 }, | ||
| 1224 | { 0x0000989c, 0x003000f2, 0x003000f2 }, | ||
| 1225 | { 0x0000989c, 0x00440016, 0x00440016 }, | ||
| 1226 | { 0x0000989c, 0x00410040, 0x00410040 }, | ||
| 1227 | { 0x0000989c, 0x000180d6, 0x000180d6 }, | ||
| 1228 | { 0x0000989c, 0x0000c0aa, 0x0000c0aa }, | ||
| 1229 | { 0x0000989c, 0x000000b1, 0x000000b1 }, | ||
| 1230 | { 0x0000989c, 0x00002000, 0x00002000 }, | ||
| 1231 | { 0x0000989c, 0x000000d4, 0x000000d4 }, | ||
| 1232 | { 0x000098d0, 0x0000000f, 0x0010000f }, | ||
| 1233 | }; | ||
| 1234 | |||
| 1235 | |||
| 1236 | static const u32 ar5416Bank6TPC[][3] = { | ||
| 1237 | |||
| 1238 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1239 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1240 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1241 | { 0x0000989c, 0x00e00000, 0x00e00000 }, | ||
| 1242 | { 0x0000989c, 0x005e0000, 0x005e0000 }, | ||
| 1243 | { 0x0000989c, 0x00120000, 0x00120000 }, | ||
| 1244 | { 0x0000989c, 0x00620000, 0x00620000 }, | ||
| 1245 | { 0x0000989c, 0x00020000, 0x00020000 }, | ||
| 1246 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1247 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1248 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1249 | { 0x0000989c, 0x40ff0000, 0x40ff0000 }, | ||
| 1250 | { 0x0000989c, 0x005f0000, 0x005f0000 }, | ||
| 1251 | { 0x0000989c, 0x00870000, 0x00870000 }, | ||
| 1252 | { 0x0000989c, 0x00f90000, 0x00f90000 }, | ||
| 1253 | { 0x0000989c, 0x007b0000, 0x007b0000 }, | ||
| 1254 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1255 | { 0x0000989c, 0x00f50000, 0x00f50000 }, | ||
| 1256 | { 0x0000989c, 0x00dc0000, 0x00dc0000 }, | ||
| 1257 | { 0x0000989c, 0x00110000, 0x00110000 }, | ||
| 1258 | { 0x0000989c, 0x006100a8, 0x006100a8 }, | ||
| 1259 | { 0x0000989c, 0x00423022, 0x00423022 }, | ||
| 1260 | { 0x0000989c, 0x2014008f, 0x2014008f }, | ||
| 1261 | { 0x0000989c, 0x00c40002, 0x00c40002 }, | ||
| 1262 | { 0x0000989c, 0x003000f2, 0x003000f2 }, | ||
| 1263 | { 0x0000989c, 0x00440016, 0x00440016 }, | ||
| 1264 | { 0x0000989c, 0x00410040, 0x00410040 }, | ||
| 1265 | { 0x0000989c, 0x0001805e, 0x0001805e }, | ||
| 1266 | { 0x0000989c, 0x0000c0ab, 0x0000c0ab }, | ||
| 1267 | { 0x0000989c, 0x000000e1, 0x000000e1 }, | ||
| 1268 | { 0x0000989c, 0x00007080, 0x00007080 }, | ||
| 1269 | { 0x0000989c, 0x000000d4, 0x000000d4 }, | ||
| 1270 | { 0x000098d0, 0x0000000f, 0x0010000f }, | ||
| 1271 | }; | ||
| 1272 | |||
| 1273 | static const u32 ar5416Bank7[][2] = { | ||
| 1274 | { 0x0000989c, 0x00000500 }, | ||
| 1275 | { 0x0000989c, 0x00000800 }, | ||
| 1276 | { 0x000098cc, 0x0000000e }, | ||
| 1277 | }; | ||
| 1278 | |||
| 1279 | static const u32 ar5416Addac[][2] = { | ||
| 1280 | {0x0000989c, 0x00000000 }, | ||
| 1281 | {0x0000989c, 0x00000000 }, | ||
| 1282 | {0x0000989c, 0x00000000 }, | ||
| 1283 | {0x0000989c, 0x00000000 }, | ||
| 1284 | {0x0000989c, 0x00000000 }, | ||
| 1285 | {0x0000989c, 0x00000000 }, | ||
| 1286 | {0x0000989c, 0x00000000 }, | ||
| 1287 | {0x0000989c, 0x00000010 }, | ||
| 1288 | {0x0000989c, 0x00000000 }, | ||
| 1289 | {0x0000989c, 0x00000000 }, | ||
| 1290 | {0x0000989c, 0x00000000 }, | ||
| 1291 | {0x0000989c, 0x00000000 }, | ||
| 1292 | {0x0000989c, 0x00000000 }, | ||
| 1293 | {0x0000989c, 0x00000000 }, | ||
| 1294 | {0x0000989c, 0x00000000 }, | ||
| 1295 | {0x0000989c, 0x00000000 }, | ||
| 1296 | {0x0000989c, 0x00000000 }, | ||
| 1297 | {0x0000989c, 0x00000000 }, | ||
| 1298 | {0x0000989c, 0x00000000 }, | ||
| 1299 | {0x0000989c, 0x00000000 }, | ||
| 1300 | {0x0000989c, 0x00000000 }, | ||
| 1301 | {0x0000989c, 0x000000c0 }, | ||
| 1302 | {0x0000989c, 0x00000015 }, | ||
| 1303 | {0x0000989c, 0x00000000 }, | ||
| 1304 | {0x0000989c, 0x00000000 }, | ||
| 1305 | {0x0000989c, 0x00000000 }, | ||
| 1306 | {0x0000989c, 0x00000000 }, | ||
| 1307 | {0x0000989c, 0x00000000 }, | ||
| 1308 | {0x0000989c, 0x00000000 }, | ||
| 1309 | {0x0000989c, 0x00000000 }, | ||
| 1310 | {0x0000989c, 0x00000000 }, | ||
| 1311 | {0x000098cc, 0x00000000 }, | ||
| 1312 | }; | ||
| 1313 | |||
| 1314 | |||
| 1315 | static const u32 ar5416Modes_9160[][6] = { | ||
| 1316 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | ||
| 1317 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | ||
| 1318 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | ||
| 1319 | { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, | ||
| 1320 | { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, | ||
| 1321 | { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf }, | ||
| 1322 | { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, | ||
| 1323 | { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, | ||
| 1324 | { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 1325 | { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, | ||
| 1326 | { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 1327 | { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, | ||
| 1328 | { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 }, | ||
| 1329 | { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 1330 | { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 1331 | { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, | ||
| 1332 | { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 }, | ||
| 1333 | { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, | ||
| 1334 | { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e }, | ||
| 1335 | { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 }, | ||
| 1336 | { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, | ||
| 1337 | { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 }, | ||
| 1338 | { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, | ||
| 1339 | { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 }, | ||
| 1340 | { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, | ||
| 1341 | { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d }, | ||
| 1342 | { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 }, | ||
| 1343 | { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 }, | ||
| 1344 | { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 }, | ||
| 1345 | { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 }, | ||
| 1346 | { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 }, | ||
| 1347 | { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 }, | ||
| 1348 | { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, | ||
| 1349 | { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, | ||
| 1350 | { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 }, | ||
| 1351 | { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, | ||
| 1352 | { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, | ||
| 1353 | { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 1354 | { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 1355 | { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 }, | ||
| 1356 | { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 }, | ||
| 1357 | { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 1358 | { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 1359 | { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 }, | ||
| 1360 | { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, | ||
| 1361 | { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, | ||
| 1362 | { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa }, | ||
| 1363 | { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 }, | ||
| 1364 | { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 }, | ||
| 1365 | { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 }, | ||
| 1366 | { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b }, | ||
| 1367 | { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b }, | ||
| 1368 | { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a }, | ||
| 1369 | { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf }, | ||
| 1370 | { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f }, | ||
| 1371 | { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f }, | ||
| 1372 | { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f }, | ||
| 1373 | { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 1374 | { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 1375 | { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 1376 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 1377 | }; | ||
| 1378 | |||
| 1379 | static const u32 ar5416Common_9160[][2] = { | ||
| 1380 | { 0x0000000c, 0x00000000 }, | ||
| 1381 | { 0x00000030, 0x00020015 }, | ||
| 1382 | { 0x00000034, 0x00000005 }, | ||
| 1383 | { 0x00000040, 0x00000000 }, | ||
| 1384 | { 0x00000044, 0x00000008 }, | ||
| 1385 | { 0x00000048, 0x00000008 }, | ||
| 1386 | { 0x0000004c, 0x00000010 }, | ||
| 1387 | { 0x00000050, 0x00000000 }, | ||
| 1388 | { 0x00000054, 0x0000001f }, | ||
| 1389 | { 0x00000800, 0x00000000 }, | ||
| 1390 | { 0x00000804, 0x00000000 }, | ||
| 1391 | { 0x00000808, 0x00000000 }, | ||
| 1392 | { 0x0000080c, 0x00000000 }, | ||
| 1393 | { 0x00000810, 0x00000000 }, | ||
| 1394 | { 0x00000814, 0x00000000 }, | ||
| 1395 | { 0x00000818, 0x00000000 }, | ||
| 1396 | { 0x0000081c, 0x00000000 }, | ||
| 1397 | { 0x00000820, 0x00000000 }, | ||
| 1398 | { 0x00000824, 0x00000000 }, | ||
| 1399 | { 0x00001040, 0x002ffc0f }, | ||
| 1400 | { 0x00001044, 0x002ffc0f }, | ||
| 1401 | { 0x00001048, 0x002ffc0f }, | ||
| 1402 | { 0x0000104c, 0x002ffc0f }, | ||
| 1403 | { 0x00001050, 0x002ffc0f }, | ||
| 1404 | { 0x00001054, 0x002ffc0f }, | ||
| 1405 | { 0x00001058, 0x002ffc0f }, | ||
| 1406 | { 0x0000105c, 0x002ffc0f }, | ||
| 1407 | { 0x00001060, 0x002ffc0f }, | ||
| 1408 | { 0x00001064, 0x002ffc0f }, | ||
| 1409 | { 0x00001230, 0x00000000 }, | ||
| 1410 | { 0x00001270, 0x00000000 }, | ||
| 1411 | { 0x00001038, 0x00000000 }, | ||
| 1412 | { 0x00001078, 0x00000000 }, | ||
| 1413 | { 0x000010b8, 0x00000000 }, | ||
| 1414 | { 0x000010f8, 0x00000000 }, | ||
| 1415 | { 0x00001138, 0x00000000 }, | ||
| 1416 | { 0x00001178, 0x00000000 }, | ||
| 1417 | { 0x000011b8, 0x00000000 }, | ||
| 1418 | { 0x000011f8, 0x00000000 }, | ||
| 1419 | { 0x00001238, 0x00000000 }, | ||
| 1420 | { 0x00001278, 0x00000000 }, | ||
| 1421 | { 0x000012b8, 0x00000000 }, | ||
| 1422 | { 0x000012f8, 0x00000000 }, | ||
| 1423 | { 0x00001338, 0x00000000 }, | ||
| 1424 | { 0x00001378, 0x00000000 }, | ||
| 1425 | { 0x000013b8, 0x00000000 }, | ||
| 1426 | { 0x000013f8, 0x00000000 }, | ||
| 1427 | { 0x00001438, 0x00000000 }, | ||
| 1428 | { 0x00001478, 0x00000000 }, | ||
| 1429 | { 0x000014b8, 0x00000000 }, | ||
| 1430 | { 0x000014f8, 0x00000000 }, | ||
| 1431 | { 0x00001538, 0x00000000 }, | ||
| 1432 | { 0x00001578, 0x00000000 }, | ||
| 1433 | { 0x000015b8, 0x00000000 }, | ||
| 1434 | { 0x000015f8, 0x00000000 }, | ||
| 1435 | { 0x00001638, 0x00000000 }, | ||
| 1436 | { 0x00001678, 0x00000000 }, | ||
| 1437 | { 0x000016b8, 0x00000000 }, | ||
| 1438 | { 0x000016f8, 0x00000000 }, | ||
| 1439 | { 0x00001738, 0x00000000 }, | ||
| 1440 | { 0x00001778, 0x00000000 }, | ||
| 1441 | { 0x000017b8, 0x00000000 }, | ||
| 1442 | { 0x000017f8, 0x00000000 }, | ||
| 1443 | { 0x0000103c, 0x00000000 }, | ||
| 1444 | { 0x0000107c, 0x00000000 }, | ||
| 1445 | { 0x000010bc, 0x00000000 }, | ||
| 1446 | { 0x000010fc, 0x00000000 }, | ||
| 1447 | { 0x0000113c, 0x00000000 }, | ||
| 1448 | { 0x0000117c, 0x00000000 }, | ||
| 1449 | { 0x000011bc, 0x00000000 }, | ||
| 1450 | { 0x000011fc, 0x00000000 }, | ||
| 1451 | { 0x0000123c, 0x00000000 }, | ||
| 1452 | { 0x0000127c, 0x00000000 }, | ||
| 1453 | { 0x000012bc, 0x00000000 }, | ||
| 1454 | { 0x000012fc, 0x00000000 }, | ||
| 1455 | { 0x0000133c, 0x00000000 }, | ||
| 1456 | { 0x0000137c, 0x00000000 }, | ||
| 1457 | { 0x000013bc, 0x00000000 }, | ||
| 1458 | { 0x000013fc, 0x00000000 }, | ||
| 1459 | { 0x0000143c, 0x00000000 }, | ||
| 1460 | { 0x0000147c, 0x00000000 }, | ||
| 1461 | { 0x00004030, 0x00000002 }, | ||
| 1462 | { 0x0000403c, 0x00000002 }, | ||
| 1463 | { 0x00007010, 0x00000020 }, | ||
| 1464 | { 0x00007038, 0x000004c2 }, | ||
| 1465 | { 0x00008004, 0x00000000 }, | ||
| 1466 | { 0x00008008, 0x00000000 }, | ||
| 1467 | { 0x0000800c, 0x00000000 }, | ||
| 1468 | { 0x00008018, 0x00000700 }, | ||
| 1469 | { 0x00008020, 0x00000000 }, | ||
| 1470 | { 0x00008038, 0x00000000 }, | ||
| 1471 | { 0x0000803c, 0x00000000 }, | ||
| 1472 | { 0x00008048, 0x40000000 }, | ||
| 1473 | { 0x00008054, 0x00000000 }, | ||
| 1474 | { 0x00008058, 0x00000000 }, | ||
| 1475 | { 0x0000805c, 0x000fc78f }, | ||
| 1476 | { 0x00008060, 0x0000000f }, | ||
| 1477 | { 0x00008064, 0x00000000 }, | ||
| 1478 | { 0x000080c0, 0x2a82301a }, | ||
| 1479 | { 0x000080c4, 0x05dc01e0 }, | ||
| 1480 | { 0x000080c8, 0x1f402710 }, | ||
| 1481 | { 0x000080cc, 0x01f40000 }, | ||
| 1482 | { 0x000080d0, 0x00001e00 }, | ||
| 1483 | { 0x000080d4, 0x00000000 }, | ||
| 1484 | { 0x000080d8, 0x00400000 }, | ||
| 1485 | { 0x000080e0, 0xffffffff }, | ||
| 1486 | { 0x000080e4, 0x0000ffff }, | ||
| 1487 | { 0x000080e8, 0x003f3f3f }, | ||
| 1488 | { 0x000080ec, 0x00000000 }, | ||
| 1489 | { 0x000080f0, 0x00000000 }, | ||
| 1490 | { 0x000080f4, 0x00000000 }, | ||
| 1491 | { 0x000080f8, 0x00000000 }, | ||
| 1492 | { 0x000080fc, 0x00020000 }, | ||
| 1493 | { 0x00008100, 0x00020000 }, | ||
| 1494 | { 0x00008104, 0x00000001 }, | ||
| 1495 | { 0x00008108, 0x00000052 }, | ||
| 1496 | { 0x0000810c, 0x00000000 }, | ||
| 1497 | { 0x00008110, 0x00000168 }, | ||
| 1498 | { 0x00008118, 0x000100aa }, | ||
| 1499 | { 0x0000811c, 0x00003210 }, | ||
| 1500 | { 0x00008120, 0x08f04800 }, | ||
| 1501 | { 0x00008124, 0x00000000 }, | ||
| 1502 | { 0x00008128, 0x00000000 }, | ||
| 1503 | { 0x0000812c, 0x00000000 }, | ||
| 1504 | { 0x00008130, 0x00000000 }, | ||
| 1505 | { 0x00008134, 0x00000000 }, | ||
| 1506 | { 0x00008138, 0x00000000 }, | ||
| 1507 | { 0x0000813c, 0x00000000 }, | ||
| 1508 | { 0x00008144, 0x00000000 }, | ||
| 1509 | { 0x00008168, 0x00000000 }, | ||
| 1510 | { 0x0000816c, 0x00000000 }, | ||
| 1511 | { 0x00008170, 0x32143320 }, | ||
| 1512 | { 0x00008174, 0xfaa4fa50 }, | ||
| 1513 | { 0x00008178, 0x00000100 }, | ||
| 1514 | { 0x0000817c, 0x00000000 }, | ||
| 1515 | { 0x000081c4, 0x00000000 }, | ||
| 1516 | { 0x000081d0, 0x00003210 }, | ||
| 1517 | { 0x000081ec, 0x00000000 }, | ||
| 1518 | { 0x000081f0, 0x00000000 }, | ||
| 1519 | { 0x000081f4, 0x00000000 }, | ||
| 1520 | { 0x000081f8, 0x00000000 }, | ||
| 1521 | { 0x000081fc, 0x00000000 }, | ||
| 1522 | { 0x00008200, 0x00000000 }, | ||
| 1523 | { 0x00008204, 0x00000000 }, | ||
| 1524 | { 0x00008208, 0x00000000 }, | ||
| 1525 | { 0x0000820c, 0x00000000 }, | ||
| 1526 | { 0x00008210, 0x00000000 }, | ||
| 1527 | { 0x00008214, 0x00000000 }, | ||
| 1528 | { 0x00008218, 0x00000000 }, | ||
| 1529 | { 0x0000821c, 0x00000000 }, | ||
| 1530 | { 0x00008220, 0x00000000 }, | ||
| 1531 | { 0x00008224, 0x00000000 }, | ||
| 1532 | { 0x00008228, 0x00000000 }, | ||
| 1533 | { 0x0000822c, 0x00000000 }, | ||
| 1534 | { 0x00008230, 0x00000000 }, | ||
| 1535 | { 0x00008234, 0x00000000 }, | ||
| 1536 | { 0x00008238, 0x00000000 }, | ||
| 1537 | { 0x0000823c, 0x00000000 }, | ||
| 1538 | { 0x00008240, 0x00100000 }, | ||
| 1539 | { 0x00008244, 0x0010f400 }, | ||
| 1540 | { 0x00008248, 0x00000100 }, | ||
| 1541 | { 0x0000824c, 0x0001e800 }, | ||
| 1542 | { 0x00008250, 0x00000000 }, | ||
| 1543 | { 0x00008254, 0x00000000 }, | ||
| 1544 | { 0x00008258, 0x00000000 }, | ||
| 1545 | { 0x0000825c, 0x400000ff }, | ||
| 1546 | { 0x00008260, 0x00080922 }, | ||
| 1547 | { 0x00008270, 0x00000000 }, | ||
| 1548 | { 0x00008274, 0x40000000 }, | ||
| 1549 | { 0x00008278, 0x003e4180 }, | ||
| 1550 | { 0x0000827c, 0x00000000 }, | ||
| 1551 | { 0x00008284, 0x0000002c }, | ||
| 1552 | { 0x00008288, 0x0000002c }, | ||
| 1553 | { 0x0000828c, 0x00000000 }, | ||
| 1554 | { 0x00008294, 0x00000000 }, | ||
| 1555 | { 0x00008298, 0x00000000 }, | ||
| 1556 | { 0x00008300, 0x00000000 }, | ||
| 1557 | { 0x00008304, 0x00000000 }, | ||
| 1558 | { 0x00008308, 0x00000000 }, | ||
| 1559 | { 0x0000830c, 0x00000000 }, | ||
| 1560 | { 0x00008310, 0x00000000 }, | ||
| 1561 | { 0x00008314, 0x00000000 }, | ||
| 1562 | { 0x00008318, 0x00000000 }, | ||
| 1563 | { 0x00008328, 0x00000000 }, | ||
| 1564 | { 0x0000832c, 0x00000007 }, | ||
| 1565 | { 0x00008330, 0x00000302 }, | ||
| 1566 | { 0x00008334, 0x00000e00 }, | ||
| 1567 | { 0x00008338, 0x00000000 }, | ||
| 1568 | { 0x0000833c, 0x00000000 }, | ||
| 1569 | { 0x00008340, 0x000107ff }, | ||
| 1570 | { 0x00009808, 0x00000000 }, | ||
| 1571 | { 0x0000980c, 0xad848e19 }, | ||
| 1572 | { 0x00009810, 0x7d14e000 }, | ||
| 1573 | { 0x00009814, 0x9c0a9f6b }, | ||
| 1574 | { 0x0000981c, 0x00000000 }, | ||
| 1575 | { 0x0000982c, 0x0000a000 }, | ||
| 1576 | { 0x00009830, 0x00000000 }, | ||
| 1577 | { 0x0000983c, 0x00200400 }, | ||
| 1578 | { 0x00009840, 0x206a01ae }, | ||
| 1579 | { 0x0000984c, 0x1284233c }, | ||
| 1580 | { 0x00009854, 0x00000859 }, | ||
| 1581 | { 0x00009900, 0x00000000 }, | ||
| 1582 | { 0x00009904, 0x00000000 }, | ||
| 1583 | { 0x00009908, 0x00000000 }, | ||
| 1584 | { 0x0000990c, 0x00000000 }, | ||
| 1585 | { 0x0000991c, 0x10000fff }, | ||
| 1586 | { 0x00009920, 0x05100000 }, | ||
| 1587 | { 0x0000a920, 0x05100000 }, | ||
| 1588 | { 0x0000b920, 0x05100000 }, | ||
| 1589 | { 0x00009928, 0x00000001 }, | ||
| 1590 | { 0x0000992c, 0x00000004 }, | ||
| 1591 | { 0x00009934, 0x1e1f2022 }, | ||
| 1592 | { 0x00009938, 0x0a0b0c0d }, | ||
| 1593 | { 0x0000993c, 0x00000000 }, | ||
| 1594 | { 0x00009948, 0x9280b212 }, | ||
| 1595 | { 0x0000994c, 0x00020028 }, | ||
| 1596 | { 0x00009954, 0x5f3ca3de }, | ||
| 1597 | { 0x00009958, 0x2108ecff }, | ||
| 1598 | { 0x00009940, 0x00750604 }, | ||
| 1599 | { 0x0000c95c, 0x004b6a8e }, | ||
| 1600 | { 0x0000c968, 0x000003ce }, | ||
| 1601 | { 0x00009970, 0x190fb515 }, | ||
| 1602 | { 0x00009974, 0x00000000 }, | ||
| 1603 | { 0x00009978, 0x00000001 }, | ||
| 1604 | { 0x0000997c, 0x00000000 }, | ||
| 1605 | { 0x00009980, 0x00000000 }, | ||
| 1606 | { 0x00009984, 0x00000000 }, | ||
| 1607 | { 0x00009988, 0x00000000 }, | ||
| 1608 | { 0x0000998c, 0x00000000 }, | ||
| 1609 | { 0x00009990, 0x00000000 }, | ||
| 1610 | { 0x00009994, 0x00000000 }, | ||
| 1611 | { 0x00009998, 0x00000000 }, | ||
| 1612 | { 0x0000999c, 0x00000000 }, | ||
| 1613 | { 0x000099a0, 0x00000000 }, | ||
| 1614 | { 0x000099a4, 0x00000001 }, | ||
| 1615 | { 0x000099a8, 0x201fff00 }, | ||
| 1616 | { 0x000099ac, 0x006f0000 }, | ||
| 1617 | { 0x000099b0, 0x03051000 }, | ||
| 1618 | { 0x000099dc, 0x00000000 }, | ||
| 1619 | { 0x000099e0, 0x00000200 }, | ||
| 1620 | { 0x000099e4, 0xaaaaaaaa }, | ||
| 1621 | { 0x000099e8, 0x3c466478 }, | ||
| 1622 | { 0x000099ec, 0x0cc80caa }, | ||
| 1623 | { 0x000099fc, 0x00001042 }, | ||
| 1624 | { 0x00009b00, 0x00000000 }, | ||
| 1625 | { 0x00009b04, 0x00000001 }, | ||
| 1626 | { 0x00009b08, 0x00000002 }, | ||
| 1627 | { 0x00009b0c, 0x00000003 }, | ||
| 1628 | { 0x00009b10, 0x00000004 }, | ||
| 1629 | { 0x00009b14, 0x00000005 }, | ||
| 1630 | { 0x00009b18, 0x00000008 }, | ||
| 1631 | { 0x00009b1c, 0x00000009 }, | ||
| 1632 | { 0x00009b20, 0x0000000a }, | ||
| 1633 | { 0x00009b24, 0x0000000b }, | ||
| 1634 | { 0x00009b28, 0x0000000c }, | ||
| 1635 | { 0x00009b2c, 0x0000000d }, | ||
| 1636 | { 0x00009b30, 0x00000010 }, | ||
| 1637 | { 0x00009b34, 0x00000011 }, | ||
| 1638 | { 0x00009b38, 0x00000012 }, | ||
| 1639 | { 0x00009b3c, 0x00000013 }, | ||
| 1640 | { 0x00009b40, 0x00000014 }, | ||
| 1641 | { 0x00009b44, 0x00000015 }, | ||
| 1642 | { 0x00009b48, 0x00000018 }, | ||
| 1643 | { 0x00009b4c, 0x00000019 }, | ||
| 1644 | { 0x00009b50, 0x0000001a }, | ||
| 1645 | { 0x00009b54, 0x0000001b }, | ||
| 1646 | { 0x00009b58, 0x0000001c }, | ||
| 1647 | { 0x00009b5c, 0x0000001d }, | ||
| 1648 | { 0x00009b60, 0x00000020 }, | ||
| 1649 | { 0x00009b64, 0x00000021 }, | ||
| 1650 | { 0x00009b68, 0x00000022 }, | ||
| 1651 | { 0x00009b6c, 0x00000023 }, | ||
| 1652 | { 0x00009b70, 0x00000024 }, | ||
| 1653 | { 0x00009b74, 0x00000025 }, | ||
| 1654 | { 0x00009b78, 0x00000028 }, | ||
| 1655 | { 0x00009b7c, 0x00000029 }, | ||
| 1656 | { 0x00009b80, 0x0000002a }, | ||
| 1657 | { 0x00009b84, 0x0000002b }, | ||
| 1658 | { 0x00009b88, 0x0000002c }, | ||
| 1659 | { 0x00009b8c, 0x0000002d }, | ||
| 1660 | { 0x00009b90, 0x00000030 }, | ||
| 1661 | { 0x00009b94, 0x00000031 }, | ||
| 1662 | { 0x00009b98, 0x00000032 }, | ||
| 1663 | { 0x00009b9c, 0x00000033 }, | ||
| 1664 | { 0x00009ba0, 0x00000034 }, | ||
| 1665 | { 0x00009ba4, 0x00000035 }, | ||
| 1666 | { 0x00009ba8, 0x00000035 }, | ||
| 1667 | { 0x00009bac, 0x00000035 }, | ||
| 1668 | { 0x00009bb0, 0x00000035 }, | ||
| 1669 | { 0x00009bb4, 0x00000035 }, | ||
| 1670 | { 0x00009bb8, 0x00000035 }, | ||
| 1671 | { 0x00009bbc, 0x00000035 }, | ||
| 1672 | { 0x00009bc0, 0x00000035 }, | ||
| 1673 | { 0x00009bc4, 0x00000035 }, | ||
| 1674 | { 0x00009bc8, 0x00000035 }, | ||
| 1675 | { 0x00009bcc, 0x00000035 }, | ||
| 1676 | { 0x00009bd0, 0x00000035 }, | ||
| 1677 | { 0x00009bd4, 0x00000035 }, | ||
| 1678 | { 0x00009bd8, 0x00000035 }, | ||
| 1679 | { 0x00009bdc, 0x00000035 }, | ||
| 1680 | { 0x00009be0, 0x00000035 }, | ||
| 1681 | { 0x00009be4, 0x00000035 }, | ||
| 1682 | { 0x00009be8, 0x00000035 }, | ||
| 1683 | { 0x00009bec, 0x00000035 }, | ||
| 1684 | { 0x00009bf0, 0x00000035 }, | ||
| 1685 | { 0x00009bf4, 0x00000035 }, | ||
| 1686 | { 0x00009bf8, 0x00000010 }, | ||
| 1687 | { 0x00009bfc, 0x0000001a }, | ||
| 1688 | { 0x0000a210, 0x40806333 }, | ||
| 1689 | { 0x0000a214, 0x00106c10 }, | ||
| 1690 | { 0x0000a218, 0x009c4060 }, | ||
| 1691 | { 0x0000a220, 0x018830c6 }, | ||
| 1692 | { 0x0000a224, 0x00000400 }, | ||
| 1693 | { 0x0000a228, 0x001a0bb5 }, | ||
| 1694 | { 0x0000a22c, 0x00000000 }, | ||
| 1695 | { 0x0000a234, 0x20202020 }, | ||
| 1696 | { 0x0000a238, 0x20202020 }, | ||
| 1697 | { 0x0000a23c, 0x13c889af }, | ||
| 1698 | { 0x0000a240, 0x38490a20 }, | ||
| 1699 | { 0x0000a244, 0x00007bb6 }, | ||
| 1700 | { 0x0000a248, 0x0fff3ffc }, | ||
| 1701 | { 0x0000a24c, 0x00000001 }, | ||
| 1702 | { 0x0000a250, 0x0000a000 }, | ||
| 1703 | { 0x0000a254, 0x00000000 }, | ||
| 1704 | { 0x0000a258, 0x0cc75380 }, | ||
| 1705 | { 0x0000a25c, 0x0f0f0f01 }, | ||
| 1706 | { 0x0000a260, 0xdfa91f01 }, | ||
| 1707 | { 0x0000a268, 0x00000001 }, | ||
| 1708 | { 0x0000a26c, 0x0ebae9c6 }, | ||
| 1709 | { 0x0000b26c, 0x0ebae9c6 }, | ||
| 1710 | { 0x0000c26c, 0x0ebae9c6 }, | ||
| 1711 | { 0x0000d270, 0x00820820 }, | ||
| 1712 | { 0x0000a278, 0x1ce739ce }, | ||
| 1713 | { 0x0000a27c, 0x050701ce }, | ||
| 1714 | { 0x0000a338, 0x00000000 }, | ||
| 1715 | { 0x0000a33c, 0x00000000 }, | ||
| 1716 | { 0x0000a340, 0x00000000 }, | ||
| 1717 | { 0x0000a344, 0x00000000 }, | ||
| 1718 | { 0x0000a348, 0x3fffffff }, | ||
| 1719 | { 0x0000a34c, 0x3fffffff }, | ||
| 1720 | { 0x0000a350, 0x3fffffff }, | ||
| 1721 | { 0x0000a354, 0x0003ffff }, | ||
| 1722 | { 0x0000a358, 0x79a8aa33 }, | ||
| 1723 | { 0x0000d35c, 0x07ffffef }, | ||
| 1724 | { 0x0000d360, 0x0fffffe7 }, | ||
| 1725 | { 0x0000d364, 0x17ffffe5 }, | ||
| 1726 | { 0x0000d368, 0x1fffffe4 }, | ||
| 1727 | { 0x0000d36c, 0x37ffffe3 }, | ||
| 1728 | { 0x0000d370, 0x3fffffe3 }, | ||
| 1729 | { 0x0000d374, 0x57ffffe3 }, | ||
| 1730 | { 0x0000d378, 0x5fffffe2 }, | ||
| 1731 | { 0x0000d37c, 0x7fffffe2 }, | ||
| 1732 | { 0x0000d380, 0x7f3c7bba }, | ||
| 1733 | { 0x0000d384, 0xf3307ff0 }, | ||
| 1734 | { 0x0000a388, 0x0c000000 }, | ||
| 1735 | { 0x0000a38c, 0x20202020 }, | ||
| 1736 | { 0x0000a390, 0x20202020 }, | ||
| 1737 | { 0x0000a394, 0x1ce739ce }, | ||
| 1738 | { 0x0000a398, 0x000001ce }, | ||
| 1739 | { 0x0000a39c, 0x00000001 }, | ||
| 1740 | { 0x0000a3a0, 0x00000000 }, | ||
| 1741 | { 0x0000a3a4, 0x00000000 }, | ||
| 1742 | { 0x0000a3a8, 0x00000000 }, | ||
| 1743 | { 0x0000a3ac, 0x00000000 }, | ||
| 1744 | { 0x0000a3b0, 0x00000000 }, | ||
| 1745 | { 0x0000a3b4, 0x00000000 }, | ||
| 1746 | { 0x0000a3b8, 0x00000000 }, | ||
| 1747 | { 0x0000a3bc, 0x00000000 }, | ||
| 1748 | { 0x0000a3c0, 0x00000000 }, | ||
| 1749 | { 0x0000a3c4, 0x00000000 }, | ||
| 1750 | { 0x0000a3c8, 0x00000246 }, | ||
| 1751 | { 0x0000a3cc, 0x20202020 }, | ||
| 1752 | { 0x0000a3d0, 0x20202020 }, | ||
| 1753 | { 0x0000a3d4, 0x20202020 }, | ||
| 1754 | { 0x0000a3dc, 0x1ce739ce }, | ||
| 1755 | { 0x0000a3e0, 0x000001ce }, | ||
| 1756 | }; | ||
| 1757 | |||
| 1758 | static const u32 ar5416Bank0_9160[][2] = { | ||
| 1759 | { 0x000098b0, 0x1e5795e5 }, | ||
| 1760 | { 0x000098e0, 0x02008020 }, | ||
| 1761 | }; | ||
| 1762 | |||
| 1763 | static const u32 ar5416BB_RfGain_9160[][3] = { | ||
| 1764 | { 0x00009a00, 0x00000000, 0x00000000 }, | ||
| 1765 | { 0x00009a04, 0x00000040, 0x00000040 }, | ||
| 1766 | { 0x00009a08, 0x00000080, 0x00000080 }, | ||
| 1767 | { 0x00009a0c, 0x000001a1, 0x00000141 }, | ||
| 1768 | { 0x00009a10, 0x000001e1, 0x00000181 }, | ||
| 1769 | { 0x00009a14, 0x00000021, 0x000001c1 }, | ||
| 1770 | { 0x00009a18, 0x00000061, 0x00000001 }, | ||
| 1771 | { 0x00009a1c, 0x00000168, 0x00000041 }, | ||
| 1772 | { 0x00009a20, 0x000001a8, 0x000001a8 }, | ||
| 1773 | { 0x00009a24, 0x000001e8, 0x000001e8 }, | ||
| 1774 | { 0x00009a28, 0x00000028, 0x00000028 }, | ||
| 1775 | { 0x00009a2c, 0x00000068, 0x00000068 }, | ||
| 1776 | { 0x00009a30, 0x00000189, 0x000000a8 }, | ||
| 1777 | { 0x00009a34, 0x000001c9, 0x00000169 }, | ||
| 1778 | { 0x00009a38, 0x00000009, 0x000001a9 }, | ||
| 1779 | { 0x00009a3c, 0x00000049, 0x000001e9 }, | ||
| 1780 | { 0x00009a40, 0x00000089, 0x00000029 }, | ||
| 1781 | { 0x00009a44, 0x00000170, 0x00000069 }, | ||
| 1782 | { 0x00009a48, 0x000001b0, 0x00000190 }, | ||
| 1783 | { 0x00009a4c, 0x000001f0, 0x000001d0 }, | ||
| 1784 | { 0x00009a50, 0x00000030, 0x00000010 }, | ||
| 1785 | { 0x00009a54, 0x00000070, 0x00000050 }, | ||
| 1786 | { 0x00009a58, 0x00000191, 0x00000090 }, | ||
| 1787 | { 0x00009a5c, 0x000001d1, 0x00000151 }, | ||
| 1788 | { 0x00009a60, 0x00000011, 0x00000191 }, | ||
| 1789 | { 0x00009a64, 0x00000051, 0x000001d1 }, | ||
| 1790 | { 0x00009a68, 0x00000091, 0x00000011 }, | ||
| 1791 | { 0x00009a6c, 0x000001b8, 0x00000051 }, | ||
| 1792 | { 0x00009a70, 0x000001f8, 0x00000198 }, | ||
| 1793 | { 0x00009a74, 0x00000038, 0x000001d8 }, | ||
| 1794 | { 0x00009a78, 0x00000078, 0x00000018 }, | ||
| 1795 | { 0x00009a7c, 0x00000199, 0x00000058 }, | ||
| 1796 | { 0x00009a80, 0x000001d9, 0x00000098 }, | ||
| 1797 | { 0x00009a84, 0x00000019, 0x00000159 }, | ||
| 1798 | { 0x00009a88, 0x00000059, 0x00000199 }, | ||
| 1799 | { 0x00009a8c, 0x00000099, 0x000001d9 }, | ||
| 1800 | { 0x00009a90, 0x000000d9, 0x00000019 }, | ||
| 1801 | { 0x00009a94, 0x000000f9, 0x00000059 }, | ||
| 1802 | { 0x00009a98, 0x000000f9, 0x00000099 }, | ||
| 1803 | { 0x00009a9c, 0x000000f9, 0x000000d9 }, | ||
| 1804 | { 0x00009aa0, 0x000000f9, 0x000000f9 }, | ||
| 1805 | { 0x00009aa4, 0x000000f9, 0x000000f9 }, | ||
| 1806 | { 0x00009aa8, 0x000000f9, 0x000000f9 }, | ||
| 1807 | { 0x00009aac, 0x000000f9, 0x000000f9 }, | ||
| 1808 | { 0x00009ab0, 0x000000f9, 0x000000f9 }, | ||
| 1809 | { 0x00009ab4, 0x000000f9, 0x000000f9 }, | ||
| 1810 | { 0x00009ab8, 0x000000f9, 0x000000f9 }, | ||
| 1811 | { 0x00009abc, 0x000000f9, 0x000000f9 }, | ||
| 1812 | { 0x00009ac0, 0x000000f9, 0x000000f9 }, | ||
| 1813 | { 0x00009ac4, 0x000000f9, 0x000000f9 }, | ||
| 1814 | { 0x00009ac8, 0x000000f9, 0x000000f9 }, | ||
| 1815 | { 0x00009acc, 0x000000f9, 0x000000f9 }, | ||
| 1816 | { 0x00009ad0, 0x000000f9, 0x000000f9 }, | ||
| 1817 | { 0x00009ad4, 0x000000f9, 0x000000f9 }, | ||
| 1818 | { 0x00009ad8, 0x000000f9, 0x000000f9 }, | ||
| 1819 | { 0x00009adc, 0x000000f9, 0x000000f9 }, | ||
| 1820 | { 0x00009ae0, 0x000000f9, 0x000000f9 }, | ||
| 1821 | { 0x00009ae4, 0x000000f9, 0x000000f9 }, | ||
| 1822 | { 0x00009ae8, 0x000000f9, 0x000000f9 }, | ||
| 1823 | { 0x00009aec, 0x000000f9, 0x000000f9 }, | ||
| 1824 | { 0x00009af0, 0x000000f9, 0x000000f9 }, | ||
| 1825 | { 0x00009af4, 0x000000f9, 0x000000f9 }, | ||
| 1826 | { 0x00009af8, 0x000000f9, 0x000000f9 }, | ||
| 1827 | { 0x00009afc, 0x000000f9, 0x000000f9 }, | ||
| 1828 | }; | ||
| 1829 | |||
| 1830 | static const u32 ar5416Bank1_9160[][2] = { | ||
| 1831 | { 0x000098b0, 0x02108421 }, | ||
| 1832 | { 0x000098ec, 0x00000008 }, | ||
| 1833 | }; | ||
| 1834 | |||
| 1835 | static const u32 ar5416Bank2_9160[][2] = { | ||
| 1836 | { 0x000098b0, 0x0e73ff17 }, | ||
| 1837 | { 0x000098e0, 0x00000420 }, | ||
| 1838 | }; | ||
| 1839 | |||
| 1840 | static const u32 ar5416Bank3_9160[][3] = { | ||
| 1841 | { 0x000098f0, 0x01400018, 0x01c00018 }, | ||
| 1842 | }; | ||
| 1843 | |||
| 1844 | static const u32 ar5416Bank6_9160[][3] = { | ||
| 1845 | |||
| 1846 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1847 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1848 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1849 | { 0x0000989c, 0x00e00000, 0x00e00000 }, | ||
| 1850 | { 0x0000989c, 0x005e0000, 0x005e0000 }, | ||
| 1851 | { 0x0000989c, 0x00120000, 0x00120000 }, | ||
| 1852 | { 0x0000989c, 0x00620000, 0x00620000 }, | ||
| 1853 | { 0x0000989c, 0x00020000, 0x00020000 }, | ||
| 1854 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1855 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1856 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1857 | { 0x0000989c, 0x40ff0000, 0x40ff0000 }, | ||
| 1858 | { 0x0000989c, 0x005f0000, 0x005f0000 }, | ||
| 1859 | { 0x0000989c, 0x00870000, 0x00870000 }, | ||
| 1860 | { 0x0000989c, 0x00f90000, 0x00f90000 }, | ||
| 1861 | { 0x0000989c, 0x007b0000, 0x007b0000 }, | ||
| 1862 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1863 | { 0x0000989c, 0x00f50000, 0x00f50000 }, | ||
| 1864 | { 0x0000989c, 0x00dc0000, 0x00dc0000 }, | ||
| 1865 | { 0x0000989c, 0x00110000, 0x00110000 }, | ||
| 1866 | { 0x0000989c, 0x006100a8, 0x006100a8 }, | ||
| 1867 | { 0x0000989c, 0x004210a2, 0x004210a2 }, | ||
| 1868 | { 0x0000989c, 0x0014008f, 0x0014008f }, | ||
| 1869 | { 0x0000989c, 0x00c40003, 0x00c40003 }, | ||
| 1870 | { 0x0000989c, 0x003000f2, 0x003000f2 }, | ||
| 1871 | { 0x0000989c, 0x00440016, 0x00440016 }, | ||
| 1872 | { 0x0000989c, 0x00410040, 0x00410040 }, | ||
| 1873 | { 0x0000989c, 0x0001805e, 0x0001805e }, | ||
| 1874 | { 0x0000989c, 0x0000c0ab, 0x0000c0ab }, | ||
| 1875 | { 0x0000989c, 0x000000f1, 0x000000f1 }, | ||
| 1876 | { 0x0000989c, 0x00002081, 0x00002081 }, | ||
| 1877 | { 0x0000989c, 0x000000d4, 0x000000d4 }, | ||
| 1878 | { 0x000098d0, 0x0000000f, 0x0010000f }, | ||
| 1879 | }; | ||
| 1880 | |||
| 1881 | static const u32 ar5416Bank6TPC_9160[][3] = { | ||
| 1882 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1883 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1884 | { 0x0000989c, 0x00000000, 0x00000000 }, | ||
| 1885 | { 0x0000989c, 0x00e00000, 0x00e00000 }, | ||
| 1886 | { 0x0000989c, 0x005e0000, 0x005e0000 }, | ||
| 1887 | { 0x0000989c, 0x00120000, 0x00120000 }, | ||
| 1888 | { 0x0000989c, 0x00620000, 0x00620000 }, | ||
| 1889 | { 0x0000989c, 0x00020000, 0x00020000 }, | ||
| 1890 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1891 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1892 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1893 | { 0x0000989c, 0x40ff0000, 0x40ff0000 }, | ||
| 1894 | { 0x0000989c, 0x005f0000, 0x005f0000 }, | ||
| 1895 | { 0x0000989c, 0x00870000, 0x00870000 }, | ||
| 1896 | { 0x0000989c, 0x00f90000, 0x00f90000 }, | ||
| 1897 | { 0x0000989c, 0x007b0000, 0x007b0000 }, | ||
| 1898 | { 0x0000989c, 0x00ff0000, 0x00ff0000 }, | ||
| 1899 | { 0x0000989c, 0x00f50000, 0x00f50000 }, | ||
| 1900 | { 0x0000989c, 0x00dc0000, 0x00dc0000 }, | ||
| 1901 | { 0x0000989c, 0x00110000, 0x00110000 }, | ||
| 1902 | { 0x0000989c, 0x006100a8, 0x006100a8 }, | ||
| 1903 | { 0x0000989c, 0x00423022, 0x00423022 }, | ||
| 1904 | { 0x0000989c, 0x2014008f, 0x2014008f }, | ||
| 1905 | { 0x0000989c, 0x00c40002, 0x00c40002 }, | ||
| 1906 | { 0x0000989c, 0x003000f2, 0x003000f2 }, | ||
| 1907 | { 0x0000989c, 0x00440016, 0x00440016 }, | ||
| 1908 | { 0x0000989c, 0x00410040, 0x00410040 }, | ||
| 1909 | { 0x0000989c, 0x0001805e, 0x0001805e }, | ||
| 1910 | { 0x0000989c, 0x0000c0ab, 0x0000c0ab }, | ||
| 1911 | { 0x0000989c, 0x000000e1, 0x000000e1 }, | ||
| 1912 | { 0x0000989c, 0x00007080, 0x00007080 }, | ||
| 1913 | { 0x0000989c, 0x000000d4, 0x000000d4 }, | ||
| 1914 | { 0x000098d0, 0x0000000f, 0x0010000f }, | ||
| 1915 | }; | ||
| 1916 | |||
| 1917 | static const u32 ar5416Bank7_9160[][2] = { | ||
| 1918 | { 0x0000989c, 0x00000500 }, | ||
| 1919 | { 0x0000989c, 0x00000800 }, | ||
| 1920 | { 0x000098cc, 0x0000000e }, | ||
| 1921 | }; | ||
| 1922 | |||
| 1923 | |||
| 1924 | static u32 ar5416Addac_9160[][2] = { | ||
| 1925 | {0x0000989c, 0x00000000 }, | ||
| 1926 | {0x0000989c, 0x00000000 }, | ||
| 1927 | {0x0000989c, 0x00000000 }, | ||
| 1928 | {0x0000989c, 0x00000000 }, | ||
| 1929 | {0x0000989c, 0x00000000 }, | ||
| 1930 | {0x0000989c, 0x00000000 }, | ||
| 1931 | {0x0000989c, 0x000000c0 }, | ||
| 1932 | {0x0000989c, 0x00000018 }, | ||
| 1933 | {0x0000989c, 0x00000004 }, | ||
| 1934 | {0x0000989c, 0x00000000 }, | ||
| 1935 | {0x0000989c, 0x00000000 }, | ||
| 1936 | {0x0000989c, 0x00000000 }, | ||
| 1937 | {0x0000989c, 0x00000000 }, | ||
| 1938 | {0x0000989c, 0x00000000 }, | ||
| 1939 | {0x0000989c, 0x00000000 }, | ||
| 1940 | {0x0000989c, 0x00000000 }, | ||
| 1941 | {0x0000989c, 0x00000000 }, | ||
| 1942 | {0x0000989c, 0x00000000 }, | ||
| 1943 | {0x0000989c, 0x00000000 }, | ||
| 1944 | {0x0000989c, 0x00000000 }, | ||
| 1945 | {0x0000989c, 0x00000000 }, | ||
| 1946 | {0x0000989c, 0x000000c0 }, | ||
| 1947 | {0x0000989c, 0x00000019 }, | ||
| 1948 | {0x0000989c, 0x00000004 }, | ||
| 1949 | {0x0000989c, 0x00000000 }, | ||
| 1950 | {0x0000989c, 0x00000000 }, | ||
| 1951 | {0x0000989c, 0x00000000 }, | ||
| 1952 | {0x0000989c, 0x00000004 }, | ||
| 1953 | {0x0000989c, 0x00000003 }, | ||
| 1954 | {0x0000989c, 0x00000008 }, | ||
| 1955 | {0x0000989c, 0x00000000 }, | ||
| 1956 | {0x000098cc, 0x00000000 }, | ||
| 1957 | }; | ||
| 1958 | |||
| 1959 | |||
| 1960 | static u32 ar5416Addac_91601_1[][2] = { | ||
| 1961 | {0x0000989c, 0x00000000 }, | ||
| 1962 | {0x0000989c, 0x00000000 }, | ||
| 1963 | {0x0000989c, 0x00000000 }, | ||
| 1964 | {0x0000989c, 0x00000000 }, | ||
| 1965 | {0x0000989c, 0x00000000 }, | ||
| 1966 | {0x0000989c, 0x00000000 }, | ||
| 1967 | {0x0000989c, 0x000000c0 }, | ||
| 1968 | {0x0000989c, 0x00000018 }, | ||
| 1969 | {0x0000989c, 0x00000004 }, | ||
| 1970 | {0x0000989c, 0x00000000 }, | ||
| 1971 | {0x0000989c, 0x00000000 }, | ||
| 1972 | {0x0000989c, 0x00000000 }, | ||
| 1973 | {0x0000989c, 0x00000000 }, | ||
| 1974 | {0x0000989c, 0x00000000 }, | ||
| 1975 | {0x0000989c, 0x00000000 }, | ||
| 1976 | {0x0000989c, 0x00000000 }, | ||
| 1977 | {0x0000989c, 0x00000000 }, | ||
| 1978 | {0x0000989c, 0x00000000 }, | ||
| 1979 | {0x0000989c, 0x00000000 }, | ||
| 1980 | {0x0000989c, 0x00000000 }, | ||
| 1981 | {0x0000989c, 0x00000000 }, | ||
| 1982 | {0x0000989c, 0x000000c0 }, | ||
| 1983 | {0x0000989c, 0x00000019 }, | ||
| 1984 | {0x0000989c, 0x00000004 }, | ||
| 1985 | {0x0000989c, 0x00000000 }, | ||
| 1986 | {0x0000989c, 0x00000000 }, | ||
| 1987 | {0x0000989c, 0x00000000 }, | ||
| 1988 | {0x0000989c, 0x00000000 }, | ||
| 1989 | {0x0000989c, 0x00000000 }, | ||
| 1990 | {0x0000989c, 0x00000000 }, | ||
| 1991 | {0x0000989c, 0x00000000 }, | ||
| 1992 | {0x000098cc, 0x00000000 }, | ||
| 1993 | }; | ||
| 1994 | |||
| 1995 | |||
| 1996 | |||
| 1997 | static const u32 ar9280Modes_9280[][6] = { | ||
| 1998 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | ||
| 1999 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | ||
| 2000 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | ||
| 2001 | { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, | ||
| 2002 | { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 }, | ||
| 2003 | { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f }, | ||
| 2004 | { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, | ||
| 2005 | { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, | ||
| 2006 | { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 2007 | { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, | ||
| 2008 | { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 2009 | { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, | ||
| 2010 | { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 }, | ||
| 2011 | { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 }, | ||
| 2012 | { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 }, | ||
| 2013 | { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 }, | ||
| 2014 | { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, | ||
| 2015 | { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e }, | ||
| 2016 | { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 }, | ||
| 2017 | { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, | ||
| 2018 | { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 }, | ||
| 2019 | { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, | ||
| 2020 | { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 }, | ||
| 2021 | { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, | ||
| 2022 | { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d }, | ||
| 2023 | { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 }, | ||
| 2024 | { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, | ||
| 2025 | { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, | ||
| 2026 | { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 }, | ||
| 2027 | { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a }, | ||
| 2028 | { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, | ||
| 2029 | { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, | ||
| 2030 | { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, | ||
| 2031 | { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c }, | ||
| 2032 | { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, | ||
| 2033 | { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, | ||
| 2034 | { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2035 | { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2036 | { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 }, | ||
| 2037 | { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 }, | ||
| 2038 | { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 }, | ||
| 2039 | { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 }, | ||
| 2040 | { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c }, | ||
| 2041 | { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 }, | ||
| 2042 | { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 }, | ||
| 2043 | { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 }, | ||
| 2044 | { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac }, | ||
| 2045 | { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 }, | ||
| 2046 | { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 }, | ||
| 2047 | { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 }, | ||
| 2048 | { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 }, | ||
| 2049 | { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 }, | ||
| 2050 | { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 }, | ||
| 2051 | { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 }, | ||
| 2052 | { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 }, | ||
| 2053 | { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac }, | ||
| 2054 | { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 }, | ||
| 2055 | { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 }, | ||
| 2056 | { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 }, | ||
| 2057 | { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 }, | ||
| 2058 | { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 }, | ||
| 2059 | { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad }, | ||
| 2060 | { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 }, | ||
| 2061 | { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 }, | ||
| 2062 | { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c }, | ||
| 2063 | { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 }, | ||
| 2064 | { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 }, | ||
| 2065 | { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 }, | ||
| 2066 | { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 }, | ||
| 2067 | { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 }, | ||
| 2068 | { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 }, | ||
| 2069 | { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 }, | ||
| 2070 | { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 }, | ||
| 2071 | { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c }, | ||
| 2072 | { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 }, | ||
| 2073 | { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 }, | ||
| 2074 | { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 }, | ||
| 2075 | { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 }, | ||
| 2076 | { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 }, | ||
| 2077 | { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c }, | ||
| 2078 | { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 }, | ||
| 2079 | { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 }, | ||
| 2080 | { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 }, | ||
| 2081 | { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 }, | ||
| 2082 | { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 }, | ||
| 2083 | { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c }, | ||
| 2084 | { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 }, | ||
| 2085 | { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 }, | ||
| 2086 | { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 }, | ||
| 2087 | { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c }, | ||
| 2088 | { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 }, | ||
| 2089 | { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 }, | ||
| 2090 | { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 }, | ||
| 2091 | { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 }, | ||
| 2092 | { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c }, | ||
| 2093 | { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 }, | ||
| 2094 | { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c }, | ||
| 2095 | { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 }, | ||
| 2096 | { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 }, | ||
| 2097 | { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 }, | ||
| 2098 | { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 }, | ||
| 2099 | { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 }, | ||
| 2100 | { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 }, | ||
| 2101 | { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 }, | ||
| 2102 | { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 }, | ||
| 2103 | { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 }, | ||
| 2104 | { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 }, | ||
| 2105 | { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 }, | ||
| 2106 | { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 }, | ||
| 2107 | { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c }, | ||
| 2108 | { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 }, | ||
| 2109 | { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 }, | ||
| 2110 | { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 }, | ||
| 2111 | { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 }, | ||
| 2112 | { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 }, | ||
| 2113 | { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 }, | ||
| 2114 | { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 }, | ||
| 2115 | { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 }, | ||
| 2116 | { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad }, | ||
| 2117 | { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 }, | ||
| 2118 | { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 }, | ||
| 2119 | { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 }, | ||
| 2120 | { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 }, | ||
| 2121 | { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 }, | ||
| 2122 | { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 }, | ||
| 2123 | { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 }, | ||
| 2124 | { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 }, | ||
| 2125 | { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 }, | ||
| 2126 | { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca }, | ||
| 2127 | { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce }, | ||
| 2128 | { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 }, | ||
| 2129 | { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 }, | ||
| 2130 | { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 }, | ||
| 2131 | { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 }, | ||
| 2132 | { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb }, | ||
| 2133 | { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf }, | ||
| 2134 | { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 }, | ||
| 2135 | { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2136 | { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2137 | { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2138 | { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2139 | { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2140 | { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2141 | { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2142 | { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2143 | { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2144 | { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2145 | { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2146 | { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2147 | { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2148 | { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2149 | { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2150 | { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2151 | { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2152 | { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2153 | { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2154 | { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2155 | { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2156 | { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2157 | { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2158 | { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2159 | { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2160 | { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2161 | { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2162 | { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2163 | { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2164 | { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 }, | ||
| 2165 | { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 }, | ||
| 2166 | { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 }, | ||
| 2167 | { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 }, | ||
| 2168 | { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, | ||
| 2169 | { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, | ||
| 2170 | { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 }, | ||
| 2171 | { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2172 | { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 }, | ||
| 2173 | { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 }, | ||
| 2174 | { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b }, | ||
| 2175 | { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 }, | ||
| 2176 | { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 }, | ||
| 2177 | { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a }, | ||
| 2178 | { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 }, | ||
| 2179 | { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 }, | ||
| 2180 | { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b }, | ||
| 2181 | { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 }, | ||
| 2182 | { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 }, | ||
| 2183 | { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a }, | ||
| 2184 | { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 }, | ||
| 2185 | { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b }, | ||
| 2186 | { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 }, | ||
| 2187 | { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 }, | ||
| 2188 | { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a }, | ||
| 2189 | { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 }, | ||
| 2190 | { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a }, | ||
| 2191 | { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 }, | ||
| 2192 | { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 }, | ||
| 2193 | { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c }, | ||
| 2194 | { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 }, | ||
| 2195 | { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 }, | ||
| 2196 | { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 }, | ||
| 2197 | }; | ||
| 2198 | |||
| 2199 | static const u32 ar9280Common_9280[][2] = { | ||
| 2200 | { 0x0000000c, 0x00000000 }, | ||
| 2201 | { 0x00000030, 0x00020015 }, | ||
| 2202 | { 0x00000034, 0x00000005 }, | ||
| 2203 | { 0x00000040, 0x00000000 }, | ||
| 2204 | { 0x00000044, 0x00000008 }, | ||
| 2205 | { 0x00000048, 0x00000008 }, | ||
| 2206 | { 0x0000004c, 0x00000010 }, | ||
| 2207 | { 0x00000050, 0x00000000 }, | ||
| 2208 | { 0x00000054, 0x0000001f }, | ||
| 2209 | { 0x00000800, 0x00000000 }, | ||
| 2210 | { 0x00000804, 0x00000000 }, | ||
| 2211 | { 0x00000808, 0x00000000 }, | ||
| 2212 | { 0x0000080c, 0x00000000 }, | ||
| 2213 | { 0x00000810, 0x00000000 }, | ||
| 2214 | { 0x00000814, 0x00000000 }, | ||
| 2215 | { 0x00000818, 0x00000000 }, | ||
| 2216 | { 0x0000081c, 0x00000000 }, | ||
| 2217 | { 0x00000820, 0x00000000 }, | ||
| 2218 | { 0x00000824, 0x00000000 }, | ||
| 2219 | { 0x00001040, 0x002ffc0f }, | ||
| 2220 | { 0x00001044, 0x002ffc0f }, | ||
| 2221 | { 0x00001048, 0x002ffc0f }, | ||
| 2222 | { 0x0000104c, 0x002ffc0f }, | ||
| 2223 | { 0x00001050, 0x002ffc0f }, | ||
| 2224 | { 0x00001054, 0x002ffc0f }, | ||
| 2225 | { 0x00001058, 0x002ffc0f }, | ||
| 2226 | { 0x0000105c, 0x002ffc0f }, | ||
| 2227 | { 0x00001060, 0x002ffc0f }, | ||
| 2228 | { 0x00001064, 0x002ffc0f }, | ||
| 2229 | { 0x00001230, 0x00000000 }, | ||
| 2230 | { 0x00001270, 0x00000000 }, | ||
| 2231 | { 0x00001038, 0x00000000 }, | ||
| 2232 | { 0x00001078, 0x00000000 }, | ||
| 2233 | { 0x000010b8, 0x00000000 }, | ||
| 2234 | { 0x000010f8, 0x00000000 }, | ||
| 2235 | { 0x00001138, 0x00000000 }, | ||
| 2236 | { 0x00001178, 0x00000000 }, | ||
| 2237 | { 0x000011b8, 0x00000000 }, | ||
| 2238 | { 0x000011f8, 0x00000000 }, | ||
| 2239 | { 0x00001238, 0x00000000 }, | ||
| 2240 | { 0x00001278, 0x00000000 }, | ||
| 2241 | { 0x000012b8, 0x00000000 }, | ||
| 2242 | { 0x000012f8, 0x00000000 }, | ||
| 2243 | { 0x00001338, 0x00000000 }, | ||
| 2244 | { 0x00001378, 0x00000000 }, | ||
| 2245 | { 0x000013b8, 0x00000000 }, | ||
| 2246 | { 0x000013f8, 0x00000000 }, | ||
| 2247 | { 0x00001438, 0x00000000 }, | ||
| 2248 | { 0x00001478, 0x00000000 }, | ||
| 2249 | { 0x000014b8, 0x00000000 }, | ||
| 2250 | { 0x000014f8, 0x00000000 }, | ||
| 2251 | { 0x00001538, 0x00000000 }, | ||
| 2252 | { 0x00001578, 0x00000000 }, | ||
| 2253 | { 0x000015b8, 0x00000000 }, | ||
| 2254 | { 0x000015f8, 0x00000000 }, | ||
| 2255 | { 0x00001638, 0x00000000 }, | ||
| 2256 | { 0x00001678, 0x00000000 }, | ||
| 2257 | { 0x000016b8, 0x00000000 }, | ||
| 2258 | { 0x000016f8, 0x00000000 }, | ||
| 2259 | { 0x00001738, 0x00000000 }, | ||
| 2260 | { 0x00001778, 0x00000000 }, | ||
| 2261 | { 0x000017b8, 0x00000000 }, | ||
| 2262 | { 0x000017f8, 0x00000000 }, | ||
| 2263 | { 0x0000103c, 0x00000000 }, | ||
| 2264 | { 0x0000107c, 0x00000000 }, | ||
| 2265 | { 0x000010bc, 0x00000000 }, | ||
| 2266 | { 0x000010fc, 0x00000000 }, | ||
| 2267 | { 0x0000113c, 0x00000000 }, | ||
| 2268 | { 0x0000117c, 0x00000000 }, | ||
| 2269 | { 0x000011bc, 0x00000000 }, | ||
| 2270 | { 0x000011fc, 0x00000000 }, | ||
| 2271 | { 0x0000123c, 0x00000000 }, | ||
| 2272 | { 0x0000127c, 0x00000000 }, | ||
| 2273 | { 0x000012bc, 0x00000000 }, | ||
| 2274 | { 0x000012fc, 0x00000000 }, | ||
| 2275 | { 0x0000133c, 0x00000000 }, | ||
| 2276 | { 0x0000137c, 0x00000000 }, | ||
| 2277 | { 0x000013bc, 0x00000000 }, | ||
| 2278 | { 0x000013fc, 0x00000000 }, | ||
| 2279 | { 0x0000143c, 0x00000000 }, | ||
| 2280 | { 0x0000147c, 0x00000000 }, | ||
| 2281 | { 0x00004030, 0x00000002 }, | ||
| 2282 | { 0x0000403c, 0x00000002 }, | ||
| 2283 | { 0x00004024, 0x0000001f }, | ||
| 2284 | { 0x00007010, 0x00000033 }, | ||
| 2285 | { 0x00007038, 0x000004c2 }, | ||
| 2286 | { 0x00008004, 0x00000000 }, | ||
| 2287 | { 0x00008008, 0x00000000 }, | ||
| 2288 | { 0x0000800c, 0x00000000 }, | ||
| 2289 | { 0x00008018, 0x00000700 }, | ||
| 2290 | { 0x00008020, 0x00000000 }, | ||
| 2291 | { 0x00008038, 0x00000000 }, | ||
| 2292 | { 0x0000803c, 0x00000000 }, | ||
| 2293 | { 0x00008048, 0x40000000 }, | ||
| 2294 | { 0x00008054, 0x00000000 }, | ||
| 2295 | { 0x00008058, 0x00000000 }, | ||
| 2296 | { 0x0000805c, 0x000fc78f }, | ||
| 2297 | { 0x00008060, 0x0000000f }, | ||
| 2298 | { 0x00008064, 0x00000000 }, | ||
| 2299 | { 0x00008070, 0x00000000 }, | ||
| 2300 | { 0x000080c0, 0x2a82301a }, | ||
| 2301 | { 0x000080c4, 0x05dc01e0 }, | ||
| 2302 | { 0x000080c8, 0x1f402710 }, | ||
| 2303 | { 0x000080cc, 0x01f40000 }, | ||
| 2304 | { 0x000080d0, 0x00001e00 }, | ||
| 2305 | { 0x000080d4, 0x00000000 }, | ||
| 2306 | { 0x000080d8, 0x00400000 }, | ||
| 2307 | { 0x000080e0, 0xffffffff }, | ||
| 2308 | { 0x000080e4, 0x0000ffff }, | ||
| 2309 | { 0x000080e8, 0x003f3f3f }, | ||
| 2310 | { 0x000080ec, 0x00000000 }, | ||
| 2311 | { 0x000080f0, 0x00000000 }, | ||
| 2312 | { 0x000080f4, 0x00000000 }, | ||
| 2313 | { 0x000080f8, 0x00000000 }, | ||
| 2314 | { 0x000080fc, 0x00020000 }, | ||
| 2315 | { 0x00008100, 0x00020000 }, | ||
| 2316 | { 0x00008104, 0x00000001 }, | ||
| 2317 | { 0x00008108, 0x00000052 }, | ||
| 2318 | { 0x0000810c, 0x00000000 }, | ||
| 2319 | { 0x00008110, 0x00000168 }, | ||
| 2320 | { 0x00008118, 0x000100aa }, | ||
| 2321 | { 0x0000811c, 0x00003210 }, | ||
| 2322 | { 0x00008120, 0x08f04800 }, | ||
| 2323 | { 0x00008124, 0x00000000 }, | ||
| 2324 | { 0x00008128, 0x00000000 }, | ||
| 2325 | { 0x0000812c, 0x00000000 }, | ||
| 2326 | { 0x00008130, 0x00000000 }, | ||
| 2327 | { 0x00008134, 0x00000000 }, | ||
| 2328 | { 0x00008138, 0x00000000 }, | ||
| 2329 | { 0x0000813c, 0x00000000 }, | ||
| 2330 | { 0x00008144, 0x00000000 }, | ||
| 2331 | { 0x00008168, 0x00000000 }, | ||
| 2332 | { 0x0000816c, 0x00000000 }, | ||
| 2333 | { 0x00008170, 0x32143320 }, | ||
| 2334 | { 0x00008174, 0xfaa4fa50 }, | ||
| 2335 | { 0x00008178, 0x00000100 }, | ||
| 2336 | { 0x0000817c, 0x00000000 }, | ||
| 2337 | { 0x000081c4, 0x00000000 }, | ||
| 2338 | { 0x000081d0, 0x00003210 }, | ||
| 2339 | { 0x000081ec, 0x00000000 }, | ||
| 2340 | { 0x000081f0, 0x00000000 }, | ||
| 2341 | { 0x000081f4, 0x00000000 }, | ||
| 2342 | { 0x000081f8, 0x00000000 }, | ||
| 2343 | { 0x000081fc, 0x00000000 }, | ||
| 2344 | { 0x00008200, 0x00000000 }, | ||
| 2345 | { 0x00008204, 0x00000000 }, | ||
| 2346 | { 0x00008208, 0x00000000 }, | ||
| 2347 | { 0x0000820c, 0x00000000 }, | ||
| 2348 | { 0x00008210, 0x00000000 }, | ||
| 2349 | { 0x00008214, 0x00000000 }, | ||
| 2350 | { 0x00008218, 0x00000000 }, | ||
| 2351 | { 0x0000821c, 0x00000000 }, | ||
| 2352 | { 0x00008220, 0x00000000 }, | ||
| 2353 | { 0x00008224, 0x00000000 }, | ||
| 2354 | { 0x00008228, 0x00000000 }, | ||
| 2355 | { 0x0000822c, 0x00000000 }, | ||
| 2356 | { 0x00008230, 0x00000000 }, | ||
| 2357 | { 0x00008234, 0x00000000 }, | ||
| 2358 | { 0x00008238, 0x00000000 }, | ||
| 2359 | { 0x0000823c, 0x00000000 }, | ||
| 2360 | { 0x00008240, 0x00100000 }, | ||
| 2361 | { 0x00008244, 0x0010f400 }, | ||
| 2362 | { 0x00008248, 0x00000100 }, | ||
| 2363 | { 0x0000824c, 0x0001e800 }, | ||
| 2364 | { 0x00008250, 0x00000000 }, | ||
| 2365 | { 0x00008254, 0x00000000 }, | ||
| 2366 | { 0x00008258, 0x00000000 }, | ||
| 2367 | { 0x0000825c, 0x400000ff }, | ||
| 2368 | { 0x00008260, 0x00080922 }, | ||
| 2369 | { 0x00008270, 0x00000000 }, | ||
| 2370 | { 0x00008274, 0x40000000 }, | ||
| 2371 | { 0x00008278, 0x003e4180 }, | ||
| 2372 | { 0x0000827c, 0x00000000 }, | ||
| 2373 | { 0x00008284, 0x0000002c }, | ||
| 2374 | { 0x00008288, 0x0000002c }, | ||
| 2375 | { 0x0000828c, 0x00000000 }, | ||
| 2376 | { 0x00008294, 0x00000000 }, | ||
| 2377 | { 0x00008298, 0x00000000 }, | ||
| 2378 | { 0x00008300, 0x00000000 }, | ||
| 2379 | { 0x00008304, 0x00000000 }, | ||
| 2380 | { 0x00008308, 0x00000000 }, | ||
| 2381 | { 0x0000830c, 0x00000000 }, | ||
| 2382 | { 0x00008310, 0x00000000 }, | ||
| 2383 | { 0x00008314, 0x00000000 }, | ||
| 2384 | { 0x00008318, 0x00000000 }, | ||
| 2385 | { 0x00008328, 0x00000000 }, | ||
| 2386 | { 0x0000832c, 0x00000007 }, | ||
| 2387 | { 0x00008330, 0x00000302 }, | ||
| 2388 | { 0x00008334, 0x00000e00 }, | ||
| 2389 | { 0x00008338, 0x00000000 }, | ||
| 2390 | { 0x0000833c, 0x00000000 }, | ||
| 2391 | { 0x00008340, 0x000107ff }, | ||
| 2392 | { 0x00008344, 0x00000000 }, | ||
| 2393 | { 0x00009808, 0x00000000 }, | ||
| 2394 | { 0x0000980c, 0xaf268e30 }, | ||
| 2395 | { 0x00009810, 0xfd14e000 }, | ||
| 2396 | { 0x00009814, 0x9c0a9f6b }, | ||
| 2397 | { 0x0000981c, 0x00000000 }, | ||
| 2398 | { 0x0000982c, 0x0000a000 }, | ||
| 2399 | { 0x00009830, 0x00000000 }, | ||
| 2400 | { 0x0000983c, 0x00200400 }, | ||
| 2401 | { 0x00009840, 0x206a01ae }, | ||
| 2402 | { 0x0000984c, 0x0040233c }, | ||
| 2403 | { 0x0000a84c, 0x0040233c }, | ||
| 2404 | { 0x00009854, 0x00000044 }, | ||
| 2405 | { 0x00009900, 0x00000000 }, | ||
| 2406 | { 0x00009904, 0x00000000 }, | ||
| 2407 | { 0x00009908, 0x00000000 }, | ||
| 2408 | { 0x0000990c, 0x00000000 }, | ||
| 2409 | { 0x0000991c, 0x10000fff }, | ||
| 2410 | { 0x00009920, 0x04900000 }, | ||
| 2411 | { 0x0000a920, 0x04900000 }, | ||
| 2412 | { 0x00009928, 0x00000001 }, | ||
| 2413 | { 0x0000992c, 0x00000004 }, | ||
| 2414 | { 0x00009934, 0x1e1f2022 }, | ||
| 2415 | { 0x00009938, 0x0a0b0c0d }, | ||
| 2416 | { 0x0000993c, 0x00000000 }, | ||
| 2417 | { 0x00009948, 0x9280c00a }, | ||
| 2418 | { 0x0000994c, 0x00020028 }, | ||
| 2419 | { 0x00009954, 0xe250a51e }, | ||
| 2420 | { 0x00009958, 0x3388ffff }, | ||
| 2421 | { 0x00009940, 0x00781204 }, | ||
| 2422 | { 0x0000c95c, 0x004b6a8e }, | ||
| 2423 | { 0x0000c968, 0x000003ce }, | ||
| 2424 | { 0x00009970, 0x190fb514 }, | ||
| 2425 | { 0x00009974, 0x00000000 }, | ||
| 2426 | { 0x00009978, 0x00000001 }, | ||
| 2427 | { 0x0000997c, 0x00000000 }, | ||
| 2428 | { 0x00009980, 0x00000000 }, | ||
| 2429 | { 0x00009984, 0x00000000 }, | ||
| 2430 | { 0x00009988, 0x00000000 }, | ||
| 2431 | { 0x0000998c, 0x00000000 }, | ||
| 2432 | { 0x00009990, 0x00000000 }, | ||
| 2433 | { 0x00009994, 0x00000000 }, | ||
| 2434 | { 0x00009998, 0x00000000 }, | ||
| 2435 | { 0x0000999c, 0x00000000 }, | ||
| 2436 | { 0x000099a0, 0x00000000 }, | ||
| 2437 | { 0x000099a4, 0x00000001 }, | ||
| 2438 | { 0x000099a8, 0x201fff00 }, | ||
| 2439 | { 0x000099ac, 0x006f00c4 }, | ||
| 2440 | { 0x000099b0, 0x03051000 }, | ||
| 2441 | { 0x000099b4, 0x00000820 }, | ||
| 2442 | { 0x000099dc, 0x00000000 }, | ||
| 2443 | { 0x000099e0, 0x00000000 }, | ||
| 2444 | { 0x000099e4, 0xaaaaaaaa }, | ||
| 2445 | { 0x000099e8, 0x3c466478 }, | ||
| 2446 | { 0x000099ec, 0x0cc80caa }, | ||
| 2447 | { 0x000099fc, 0x00001042 }, | ||
| 2448 | { 0x0000a210, 0x4080a333 }, | ||
| 2449 | { 0x0000a214, 0x40206c10 }, | ||
| 2450 | { 0x0000a218, 0x009c4060 }, | ||
| 2451 | { 0x0000a220, 0x01834061 }, | ||
| 2452 | { 0x0000a224, 0x00000400 }, | ||
| 2453 | { 0x0000a228, 0x000003b5 }, | ||
| 2454 | { 0x0000a22c, 0x23277200 }, | ||
| 2455 | { 0x0000a234, 0x20202020 }, | ||
| 2456 | { 0x0000a238, 0x20202020 }, | ||
| 2457 | { 0x0000a23c, 0x13c889af }, | ||
| 2458 | { 0x0000a240, 0x38490a20 }, | ||
| 2459 | { 0x0000a244, 0x00007bb6 }, | ||
| 2460 | { 0x0000a248, 0x0fff3ffc }, | ||
| 2461 | { 0x0000a24c, 0x00000001 }, | ||
| 2462 | { 0x0000a250, 0x001da000 }, | ||
| 2463 | { 0x0000a254, 0x00000000 }, | ||
| 2464 | { 0x0000a258, 0x0cdbd380 }, | ||
| 2465 | { 0x0000a25c, 0x0f0f0f01 }, | ||
| 2466 | { 0x0000a260, 0xdfa91f01 }, | ||
| 2467 | { 0x0000a268, 0x00000000 }, | ||
| 2468 | { 0x0000a26c, 0x0ebae9c6 }, | ||
| 2469 | { 0x0000b26c, 0x0ebae9c6 }, | ||
| 2470 | { 0x0000d270, 0x00820820 }, | ||
| 2471 | { 0x0000a278, 0x1ce739ce }, | ||
| 2472 | { 0x0000a27c, 0x050701ce }, | ||
| 2473 | { 0x0000a358, 0x7999aa0f }, | ||
| 2474 | { 0x0000d35c, 0x07ffffef }, | ||
| 2475 | { 0x0000d360, 0x0fffffe7 }, | ||
| 2476 | { 0x0000d364, 0x17ffffe5 }, | ||
| 2477 | { 0x0000d368, 0x1fffffe4 }, | ||
| 2478 | { 0x0000d36c, 0x37ffffe3 }, | ||
| 2479 | { 0x0000d370, 0x3fffffe3 }, | ||
| 2480 | { 0x0000d374, 0x57ffffe3 }, | ||
| 2481 | { 0x0000d378, 0x5fffffe2 }, | ||
| 2482 | { 0x0000d37c, 0x7fffffe2 }, | ||
| 2483 | { 0x0000d380, 0x7f3c7bba }, | ||
| 2484 | { 0x0000d384, 0xf3307ff0 }, | ||
| 2485 | { 0x0000a388, 0x0c000000 }, | ||
| 2486 | { 0x0000a38c, 0x20202020 }, | ||
| 2487 | { 0x0000a390, 0x20202020 }, | ||
| 2488 | { 0x0000a394, 0x1ce739ce }, | ||
| 2489 | { 0x0000a398, 0x000001ce }, | ||
| 2490 | { 0x0000a39c, 0x00000001 }, | ||
| 2491 | { 0x0000a3a0, 0x00000000 }, | ||
| 2492 | { 0x0000a3a4, 0x00000000 }, | ||
| 2493 | { 0x0000a3a8, 0x00000000 }, | ||
| 2494 | { 0x0000a3ac, 0x00000000 }, | ||
| 2495 | { 0x0000a3b0, 0x00000000 }, | ||
| 2496 | { 0x0000a3b4, 0x00000000 }, | ||
| 2497 | { 0x0000a3b8, 0x00000000 }, | ||
| 2498 | { 0x0000a3bc, 0x00000000 }, | ||
| 2499 | { 0x0000a3c0, 0x00000000 }, | ||
| 2500 | { 0x0000a3c4, 0x00000000 }, | ||
| 2501 | { 0x0000a3c8, 0x00000246 }, | ||
| 2502 | { 0x0000a3cc, 0x20202020 }, | ||
| 2503 | { 0x0000a3d0, 0x20202020 }, | ||
| 2504 | { 0x0000a3d4, 0x20202020 }, | ||
| 2505 | { 0x0000a3dc, 0x1ce739ce }, | ||
| 2506 | { 0x0000a3e0, 0x000001ce }, | ||
| 2507 | { 0x0000a3e4, 0x00000000 }, | ||
| 2508 | { 0x0000a3e8, 0x18c43433 }, | ||
| 2509 | { 0x0000a3ec, 0x00f38081 }, | ||
| 2510 | { 0x00007800, 0x00040000 }, | ||
| 2511 | { 0x00007804, 0xdb005012 }, | ||
| 2512 | { 0x00007808, 0x04924914 }, | ||
| 2513 | { 0x0000780c, 0x21084210 }, | ||
| 2514 | { 0x00007810, 0x6d801300 }, | ||
| 2515 | { 0x00007814, 0x0019beff }, | ||
| 2516 | { 0x00007818, 0x07e40000 }, | ||
| 2517 | { 0x0000781c, 0x00492000 }, | ||
| 2518 | { 0x00007820, 0x92492480 }, | ||
| 2519 | { 0x00007824, 0x00040000 }, | ||
| 2520 | { 0x00007828, 0xdb005012 }, | ||
| 2521 | { 0x0000782c, 0x04924914 }, | ||
| 2522 | { 0x00007830, 0x21084210 }, | ||
| 2523 | { 0x00007834, 0x6d801300 }, | ||
| 2524 | { 0x00007838, 0x0019beff }, | ||
| 2525 | { 0x0000783c, 0x07e40000 }, | ||
| 2526 | { 0x00007840, 0x00492000 }, | ||
| 2527 | { 0x00007844, 0x92492480 }, | ||
| 2528 | { 0x00007848, 0x00120000 }, | ||
| 2529 | { 0x00007850, 0x54214514 }, | ||
| 2530 | { 0x00007858, 0x92592692 }, | ||
| 2531 | { 0x00007860, 0x52802000 }, | ||
| 2532 | { 0x00007864, 0x0a8e370e }, | ||
| 2533 | { 0x00007868, 0xc0102850 }, | ||
| 2534 | { 0x0000786c, 0x812d4000 }, | ||
| 2535 | { 0x00007874, 0x001b6db0 }, | ||
| 2536 | { 0x00007878, 0x00376b63 }, | ||
| 2537 | { 0x0000787c, 0x06db6db6 }, | ||
| 2538 | { 0x00007880, 0x006d8000 }, | ||
| 2539 | { 0x00007884, 0xffeffffe }, | ||
| 2540 | { 0x00007888, 0xffeffffe }, | ||
| 2541 | { 0x00007890, 0x00060aeb }, | ||
| 2542 | { 0x00007894, 0x5a108000 }, | ||
| 2543 | { 0x00007898, 0x2a850160 }, | ||
| 2544 | }; | ||
| 2545 | |||
| 2546 | |||
| 2547 | |||
| 2548 | |||
| 2549 | static const u32 ar9280Modes_9280_2[][6] = { | ||
| 2550 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | ||
| 2551 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | ||
| 2552 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | ||
| 2553 | { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 }, | ||
| 2554 | { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, | ||
| 2555 | { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f }, | ||
| 2556 | { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, | ||
| 2557 | { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, | ||
| 2558 | { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, | ||
| 2559 | { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 2560 | { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, | ||
| 2561 | { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, | ||
| 2562 | { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, | ||
| 2563 | { 0x00009840, 0x206a012e, 0x206a012e, 0x206a022e, 0x206a022e, 0x206a022e }, | ||
| 2564 | { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 }, | ||
| 2565 | { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 }, | ||
| 2566 | { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 }, | ||
| 2567 | { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 }, | ||
| 2568 | { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e }, | ||
| 2569 | { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e }, | ||
| 2570 | { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 }, | ||
| 2571 | { 0x0000c864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, | ||
| 2572 | { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, | ||
| 2573 | { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, | ||
| 2574 | { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 }, | ||
| 2575 | { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, | ||
| 2576 | { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d }, | ||
| 2577 | { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 }, | ||
| 2578 | { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, | ||
| 2579 | { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, | ||
| 2580 | { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 }, | ||
| 2581 | { 0x0000c9b8, 0x0000000f, 0x0000000f, 0x0000001c, 0x0000001c, 0x0000001c }, | ||
| 2582 | { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, | ||
| 2583 | { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, | ||
| 2584 | { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, | ||
| 2585 | { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 }, | ||
| 2586 | { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, | ||
| 2587 | { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, | ||
| 2588 | { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2589 | { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2590 | { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 }, | ||
| 2591 | { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 }, | ||
| 2592 | { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 }, | ||
| 2593 | { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 }, | ||
| 2594 | { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c }, | ||
| 2595 | { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 }, | ||
| 2596 | { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 }, | ||
| 2597 | { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 }, | ||
| 2598 | { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c }, | ||
| 2599 | { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 }, | ||
| 2600 | { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 }, | ||
| 2601 | { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 }, | ||
| 2602 | { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c }, | ||
| 2603 | { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 }, | ||
| 2604 | { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 }, | ||
| 2605 | { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 }, | ||
| 2606 | { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c }, | ||
| 2607 | { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 }, | ||
| 2608 | { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 }, | ||
| 2609 | { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 }, | ||
| 2610 | { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 }, | ||
| 2611 | { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 }, | ||
| 2612 | { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c }, | ||
| 2613 | { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 }, | ||
| 2614 | { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 }, | ||
| 2615 | { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 }, | ||
| 2616 | { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c }, | ||
| 2617 | { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 }, | ||
| 2618 | { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 }, | ||
| 2619 | { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 }, | ||
| 2620 | { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 }, | ||
| 2621 | { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 }, | ||
| 2622 | { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 }, | ||
| 2623 | { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 }, | ||
| 2624 | { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 }, | ||
| 2625 | { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c }, | ||
| 2626 | { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 }, | ||
| 2627 | { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 }, | ||
| 2628 | { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 }, | ||
| 2629 | { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 }, | ||
| 2630 | { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 }, | ||
| 2631 | { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c }, | ||
| 2632 | { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 }, | ||
| 2633 | { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 }, | ||
| 2634 | { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 }, | ||
| 2635 | { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 }, | ||
| 2636 | { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 }, | ||
| 2637 | { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c }, | ||
| 2638 | { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 }, | ||
| 2639 | { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 }, | ||
| 2640 | { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 }, | ||
| 2641 | { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c }, | ||
| 2642 | { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 }, | ||
| 2643 | { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 }, | ||
| 2644 | { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 }, | ||
| 2645 | { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 }, | ||
| 2646 | { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c }, | ||
| 2647 | { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 }, | ||
| 2648 | { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c }, | ||
| 2649 | { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 }, | ||
| 2650 | { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 }, | ||
| 2651 | { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 }, | ||
| 2652 | { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 }, | ||
| 2653 | { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 }, | ||
| 2654 | { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 }, | ||
| 2655 | { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 }, | ||
| 2656 | { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 }, | ||
| 2657 | { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 }, | ||
| 2658 | { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 }, | ||
| 2659 | { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 }, | ||
| 2660 | { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 }, | ||
| 2661 | { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c }, | ||
| 2662 | { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 }, | ||
| 2663 | { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 }, | ||
| 2664 | { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 }, | ||
| 2665 | { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 }, | ||
| 2666 | { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 }, | ||
| 2667 | { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 }, | ||
| 2668 | { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 }, | ||
| 2669 | { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 }, | ||
| 2670 | { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad }, | ||
| 2671 | { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 }, | ||
| 2672 | { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 }, | ||
| 2673 | { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 }, | ||
| 2674 | { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 }, | ||
| 2675 | { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 }, | ||
| 2676 | { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 }, | ||
| 2677 | { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 }, | ||
| 2678 | { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 }, | ||
| 2679 | { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 }, | ||
| 2680 | { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca }, | ||
| 2681 | { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce }, | ||
| 2682 | { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 }, | ||
| 2683 | { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 }, | ||
| 2684 | { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 }, | ||
| 2685 | { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 }, | ||
| 2686 | { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb }, | ||
| 2687 | { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf }, | ||
| 2688 | { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 }, | ||
| 2689 | { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2690 | { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2691 | { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2692 | { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2693 | { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2694 | { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2695 | { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2696 | { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2697 | { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2698 | { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2699 | { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2700 | { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2701 | { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2702 | { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2703 | { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2704 | { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2705 | { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2706 | { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2707 | { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2708 | { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2709 | { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2710 | { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2711 | { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2712 | { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2713 | { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2714 | { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2715 | { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2716 | { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2717 | { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db }, | ||
| 2718 | { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 }, | ||
| 2719 | { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 }, | ||
| 2720 | { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 }, | ||
| 2721 | { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 }, | ||
| 2722 | { 0x0000a21c, 0x1463800a, 0x1463800a, 0x1463800a, 0x1463800a, 0x1463800a }, | ||
| 2723 | { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, | ||
| 2724 | { 0x0000a250, 0x001ff000, 0x001ff000, 0x001da000, 0x001da000, 0x001da000 }, | ||
| 2725 | { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 }, | ||
| 2726 | { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2727 | { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 }, | ||
| 2728 | { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 }, | ||
| 2729 | { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b }, | ||
| 2730 | { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 }, | ||
| 2731 | { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 }, | ||
| 2732 | { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a }, | ||
| 2733 | { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 }, | ||
| 2734 | { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 }, | ||
| 2735 | { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b }, | ||
| 2736 | { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 }, | ||
| 2737 | { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 }, | ||
| 2738 | { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a }, | ||
| 2739 | { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 }, | ||
| 2740 | { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b }, | ||
| 2741 | { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 }, | ||
| 2742 | { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 }, | ||
| 2743 | { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a }, | ||
| 2744 | { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 }, | ||
| 2745 | { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a }, | ||
| 2746 | { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 }, | ||
| 2747 | { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 }, | ||
| 2748 | { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, | ||
| 2749 | { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | ||
| 2750 | { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 }, | ||
| 2751 | }; | ||
| 2752 | |||
| 2753 | static const u32 ar9280Common_9280_2[][2] = { | ||
| 2754 | { 0x0000000c, 0x00000000 }, | ||
| 2755 | { 0x00000030, 0x00020015 }, | ||
| 2756 | { 0x00000034, 0x00000005 }, | ||
| 2757 | { 0x00000040, 0x00000000 }, | ||
| 2758 | { 0x00000044, 0x00000008 }, | ||
| 2759 | { 0x00000048, 0x00000008 }, | ||
| 2760 | { 0x0000004c, 0x00000010 }, | ||
| 2761 | { 0x00000050, 0x00000000 }, | ||
| 2762 | { 0x00000054, 0x0000001f }, | ||
| 2763 | { 0x00000800, 0x00000000 }, | ||
| 2764 | { 0x00000804, 0x00000000 }, | ||
| 2765 | { 0x00000808, 0x00000000 }, | ||
| 2766 | { 0x0000080c, 0x00000000 }, | ||
| 2767 | { 0x00000810, 0x00000000 }, | ||
| 2768 | { 0x00000814, 0x00000000 }, | ||
| 2769 | { 0x00000818, 0x00000000 }, | ||
| 2770 | { 0x0000081c, 0x00000000 }, | ||
| 2771 | { 0x00000820, 0x00000000 }, | ||
| 2772 | { 0x00000824, 0x00000000 }, | ||
| 2773 | { 0x00001040, 0x002ffc0f }, | ||
| 2774 | { 0x00001044, 0x002ffc0f }, | ||
| 2775 | { 0x00001048, 0x002ffc0f }, | ||
| 2776 | { 0x0000104c, 0x002ffc0f }, | ||
| 2777 | { 0x00001050, 0x002ffc0f }, | ||
| 2778 | { 0x00001054, 0x002ffc0f }, | ||
| 2779 | { 0x00001058, 0x002ffc0f }, | ||
| 2780 | { 0x0000105c, 0x002ffc0f }, | ||
| 2781 | { 0x00001060, 0x002ffc0f }, | ||
| 2782 | { 0x00001064, 0x002ffc0f }, | ||
| 2783 | { 0x00001230, 0x00000000 }, | ||
| 2784 | { 0x00001270, 0x00000000 }, | ||
| 2785 | { 0x00001038, 0x00000000 }, | ||
| 2786 | { 0x00001078, 0x00000000 }, | ||
| 2787 | { 0x000010b8, 0x00000000 }, | ||
| 2788 | { 0x000010f8, 0x00000000 }, | ||
| 2789 | { 0x00001138, 0x00000000 }, | ||
| 2790 | { 0x00001178, 0x00000000 }, | ||
| 2791 | { 0x000011b8, 0x00000000 }, | ||
| 2792 | { 0x000011f8, 0x00000000 }, | ||
| 2793 | { 0x00001238, 0x00000000 }, | ||
| 2794 | { 0x00001278, 0x00000000 }, | ||
| 2795 | { 0x000012b8, 0x00000000 }, | ||
| 2796 | { 0x000012f8, 0x00000000 }, | ||
| 2797 | { 0x00001338, 0x00000000 }, | ||
| 2798 | { 0x00001378, 0x00000000 }, | ||
| 2799 | { 0x000013b8, 0x00000000 }, | ||
| 2800 | { 0x000013f8, 0x00000000 }, | ||
| 2801 | { 0x00001438, 0x00000000 }, | ||
| 2802 | { 0x00001478, 0x00000000 }, | ||
| 2803 | { 0x000014b8, 0x00000000 }, | ||
| 2804 | { 0x000014f8, 0x00000000 }, | ||
| 2805 | { 0x00001538, 0x00000000 }, | ||
| 2806 | { 0x00001578, 0x00000000 }, | ||
| 2807 | { 0x000015b8, 0x00000000 }, | ||
| 2808 | { 0x000015f8, 0x00000000 }, | ||
| 2809 | { 0x00001638, 0x00000000 }, | ||
| 2810 | { 0x00001678, 0x00000000 }, | ||
| 2811 | { 0x000016b8, 0x00000000 }, | ||
| 2812 | { 0x000016f8, 0x00000000 }, | ||
| 2813 | { 0x00001738, 0x00000000 }, | ||
| 2814 | { 0x00001778, 0x00000000 }, | ||
| 2815 | { 0x000017b8, 0x00000000 }, | ||
| 2816 | { 0x000017f8, 0x00000000 }, | ||
| 2817 | { 0x0000103c, 0x00000000 }, | ||
| 2818 | { 0x0000107c, 0x00000000 }, | ||
| 2819 | { 0x000010bc, 0x00000000 }, | ||
| 2820 | { 0x000010fc, 0x00000000 }, | ||
| 2821 | { 0x0000113c, 0x00000000 }, | ||
| 2822 | { 0x0000117c, 0x00000000 }, | ||
| 2823 | { 0x000011bc, 0x00000000 }, | ||
| 2824 | { 0x000011fc, 0x00000000 }, | ||
| 2825 | { 0x0000123c, 0x00000000 }, | ||
| 2826 | { 0x0000127c, 0x00000000 }, | ||
| 2827 | { 0x000012bc, 0x00000000 }, | ||
| 2828 | { 0x000012fc, 0x00000000 }, | ||
| 2829 | { 0x0000133c, 0x00000000 }, | ||
| 2830 | { 0x0000137c, 0x00000000 }, | ||
| 2831 | { 0x000013bc, 0x00000000 }, | ||
| 2832 | { 0x000013fc, 0x00000000 }, | ||
| 2833 | { 0x0000143c, 0x00000000 }, | ||
| 2834 | { 0x0000147c, 0x00000000 }, | ||
| 2835 | { 0x00004030, 0x00000002 }, | ||
| 2836 | { 0x0000403c, 0x00000002 }, | ||
| 2837 | { 0x00004024, 0x0000001f }, | ||
| 2838 | { 0x00004060, 0x00000000 }, | ||
| 2839 | { 0x00004064, 0x00000000 }, | ||
| 2840 | { 0x00007010, 0x00000033 }, | ||
| 2841 | { 0x00007034, 0x00000002 }, | ||
| 2842 | { 0x00007038, 0x000004c2 }, | ||
| 2843 | { 0x00008004, 0x00000000 }, | ||
| 2844 | { 0x00008008, 0x00000000 }, | ||
| 2845 | { 0x0000800c, 0x00000000 }, | ||
| 2846 | { 0x00008018, 0x00000700 }, | ||
| 2847 | { 0x00008020, 0x00000000 }, | ||
| 2848 | { 0x00008038, 0x00000000 }, | ||
| 2849 | { 0x0000803c, 0x00000000 }, | ||
| 2850 | { 0x00008048, 0x40000000 }, | ||
| 2851 | { 0x00008054, 0x00000000 }, | ||
| 2852 | { 0x00008058, 0x00000000 }, | ||
| 2853 | { 0x0000805c, 0x000fc78f }, | ||
| 2854 | { 0x00008060, 0x0000000f }, | ||
| 2855 | { 0x00008064, 0x00000000 }, | ||
| 2856 | { 0x00008070, 0x00000000 }, | ||
| 2857 | { 0x000080c0, 0x2a80001a }, | ||
| 2858 | { 0x000080c4, 0x05dc01e0 }, | ||
| 2859 | { 0x000080c8, 0x1f402710 }, | ||
| 2860 | { 0x000080cc, 0x01f40000 }, | ||
| 2861 | { 0x000080d0, 0x00001e00 }, | ||
| 2862 | { 0x000080d4, 0x00000000 }, | ||
| 2863 | { 0x000080d8, 0x00400000 }, | ||
| 2864 | { 0x000080e0, 0xffffffff }, | ||
| 2865 | { 0x000080e4, 0x0000ffff }, | ||
| 2866 | { 0x000080e8, 0x003f3f3f }, | ||
| 2867 | { 0x000080ec, 0x00000000 }, | ||
| 2868 | { 0x000080f0, 0x00000000 }, | ||
| 2869 | { 0x000080f4, 0x00000000 }, | ||
| 2870 | { 0x000080f8, 0x00000000 }, | ||
| 2871 | { 0x000080fc, 0x00020000 }, | ||
| 2872 | { 0x00008100, 0x00020000 }, | ||
| 2873 | { 0x00008104, 0x00000001 }, | ||
| 2874 | { 0x00008108, 0x00000052 }, | ||
| 2875 | { 0x0000810c, 0x00000000 }, | ||
| 2876 | { 0x00008110, 0x00000168 }, | ||
| 2877 | { 0x00008118, 0x000100aa }, | ||
| 2878 | { 0x0000811c, 0x00003210 }, | ||
| 2879 | { 0x00008120, 0x08f04800 }, | ||
| 2880 | { 0x00008124, 0x00000000 }, | ||
| 2881 | { 0x00008128, 0x00000000 }, | ||
| 2882 | { 0x0000812c, 0x00000000 }, | ||
| 2883 | { 0x00008130, 0x00000000 }, | ||
| 2884 | { 0x00008134, 0x00000000 }, | ||
| 2885 | { 0x00008138, 0x00000000 }, | ||
| 2886 | { 0x0000813c, 0x00000000 }, | ||
| 2887 | { 0x00008144, 0x00000000 }, | ||
| 2888 | { 0x00008168, 0x00000000 }, | ||
| 2889 | { 0x0000816c, 0x00000000 }, | ||
| 2890 | { 0x00008170, 0x32143320 }, | ||
| 2891 | { 0x00008174, 0xfaa4fa50 }, | ||
| 2892 | { 0x00008178, 0x00000100 }, | ||
| 2893 | { 0x0000817c, 0x00000000 }, | ||
| 2894 | { 0x000081c0, 0x00000000 }, | ||
| 2895 | { 0x000081d0, 0x00003210 }, | ||
| 2896 | { 0x000081ec, 0x00000000 }, | ||
| 2897 | { 0x000081f0, 0x00000000 }, | ||
| 2898 | { 0x000081f4, 0x00000000 }, | ||
| 2899 | { 0x000081f8, 0x00000000 }, | ||
| 2900 | { 0x000081fc, 0x00000000 }, | ||
| 2901 | { 0x00008200, 0x00000000 }, | ||
| 2902 | { 0x00008204, 0x00000000 }, | ||
| 2903 | { 0x00008208, 0x00000000 }, | ||
| 2904 | { 0x0000820c, 0x00000000 }, | ||
| 2905 | { 0x00008210, 0x00000000 }, | ||
| 2906 | { 0x00008214, 0x00000000 }, | ||
| 2907 | { 0x00008218, 0x00000000 }, | ||
| 2908 | { 0x0000821c, 0x00000000 }, | ||
| 2909 | { 0x00008220, 0x00000000 }, | ||
| 2910 | { 0x00008224, 0x00000000 }, | ||
| 2911 | { 0x00008228, 0x00000000 }, | ||
| 2912 | { 0x0000822c, 0x00000000 }, | ||
| 2913 | { 0x00008230, 0x00000000 }, | ||
| 2914 | { 0x00008234, 0x00000000 }, | ||
| 2915 | { 0x00008238, 0x00000000 }, | ||
| 2916 | { 0x0000823c, 0x00000000 }, | ||
| 2917 | { 0x00008240, 0x00100000 }, | ||
| 2918 | { 0x00008244, 0x0010f400 }, | ||
| 2919 | { 0x00008248, 0x00000100 }, | ||
| 2920 | { 0x0000824c, 0x0001e800 }, | ||
| 2921 | { 0x00008250, 0x00000000 }, | ||
| 2922 | { 0x00008254, 0x00000000 }, | ||
| 2923 | { 0x00008258, 0x00000000 }, | ||
| 2924 | { 0x0000825c, 0x400000ff }, | ||
| 2925 | { 0x00008260, 0x00080922 }, | ||
| 2926 | { 0x00008270, 0x00000000 }, | ||
| 2927 | { 0x00008274, 0x40000000 }, | ||
| 2928 | { 0x00008278, 0x003e4180 }, | ||
| 2929 | { 0x0000827c, 0x00000000 }, | ||
| 2930 | { 0x00008284, 0x0000002c }, | ||
| 2931 | { 0x00008288, 0x0000002c }, | ||
| 2932 | { 0x0000828c, 0x00000000 }, | ||
| 2933 | { 0x00008294, 0x00000000 }, | ||
| 2934 | { 0x00008298, 0x00000000 }, | ||
| 2935 | { 0x0000829c, 0x00000000 }, | ||
| 2936 | { 0x00008300, 0x00000040 }, | ||
| 2937 | { 0x00008314, 0x00000000 }, | ||
| 2938 | { 0x00008328, 0x00000000 }, | ||
| 2939 | { 0x0000832c, 0x00000007 }, | ||
| 2940 | { 0x00008330, 0x00000302 }, | ||
| 2941 | { 0x00008334, 0x00000e00 }, | ||
| 2942 | { 0x00008338, 0x00000000 }, | ||
| 2943 | { 0x0000833c, 0x00000000 }, | ||
| 2944 | { 0x00008340, 0x000107ff }, | ||
| 2945 | { 0x00008344, 0x00581043 }, | ||
| 2946 | { 0x00009808, 0x00000000 }, | ||
| 2947 | { 0x0000980c, 0xafa68e30 }, | ||
| 2948 | { 0x00009810, 0xfd14e000 }, | ||
| 2949 | { 0x00009814, 0x9c0a9f6b }, | ||
| 2950 | { 0x0000981c, 0x00000000 }, | ||
| 2951 | { 0x0000982c, 0x0000a000 }, | ||
| 2952 | { 0x00009830, 0x00000000 }, | ||
| 2953 | { 0x0000983c, 0x00200400 }, | ||
| 2954 | { 0x0000984c, 0x0040233c }, | ||
| 2955 | { 0x0000a84c, 0x0040233c }, | ||
| 2956 | { 0x00009854, 0x00000044 }, | ||
| 2957 | { 0x00009900, 0x00000000 }, | ||
| 2958 | { 0x00009904, 0x00000000 }, | ||
| 2959 | { 0x00009908, 0x00000000 }, | ||
| 2960 | { 0x0000990c, 0x00000000 }, | ||
| 2961 | { 0x00009910, 0x01002310 }, | ||
| 2962 | { 0x0000991c, 0x10000fff }, | ||
| 2963 | { 0x00009920, 0x04900000 }, | ||
| 2964 | { 0x0000a920, 0x04900000 }, | ||
| 2965 | { 0x00009928, 0x00000001 }, | ||
| 2966 | { 0x0000992c, 0x00000004 }, | ||
| 2967 | { 0x00009934, 0x1e1f2022 }, | ||
| 2968 | { 0x00009938, 0x0a0b0c0d }, | ||
| 2969 | { 0x0000993c, 0x00000000 }, | ||
| 2970 | { 0x00009948, 0x9280c00a }, | ||
| 2971 | { 0x0000994c, 0x00020028 }, | ||
| 2972 | { 0x00009954, 0x5f3ca3de }, | ||
| 2973 | { 0x00009958, 0x2108ecff }, | ||
| 2974 | { 0x00009940, 0x14750604 }, | ||
| 2975 | { 0x0000c95c, 0x004b6a8e }, | ||
| 2976 | { 0x0000c968, 0x000003ce }, | ||
| 2977 | { 0x00009970, 0x190fb515 }, | ||
| 2978 | { 0x00009974, 0x00000000 }, | ||
| 2979 | { 0x00009978, 0x00000001 }, | ||
| 2980 | { 0x0000997c, 0x00000000 }, | ||
| 2981 | { 0x00009980, 0x00000000 }, | ||
| 2982 | { 0x00009984, 0x00000000 }, | ||
| 2983 | { 0x00009988, 0x00000000 }, | ||
| 2984 | { 0x0000998c, 0x00000000 }, | ||
| 2985 | { 0x00009990, 0x00000000 }, | ||
| 2986 | { 0x00009994, 0x00000000 }, | ||
| 2987 | { 0x00009998, 0x00000000 }, | ||
| 2988 | { 0x0000999c, 0x00000000 }, | ||
| 2989 | { 0x000099a0, 0x00000000 }, | ||
| 2990 | { 0x000099a4, 0x00000001 }, | ||
| 2991 | { 0x000099a8, 0x201fff00 }, | ||
| 2992 | { 0x000099ac, 0x006f0000 }, | ||
| 2993 | { 0x000099b0, 0x03051000 }, | ||
| 2994 | { 0x000099b4, 0x00000820 }, | ||
| 2995 | { 0x000099dc, 0x00000000 }, | ||
| 2996 | { 0x000099e0, 0x00000000 }, | ||
| 2997 | { 0x000099e4, 0xaaaaaaaa }, | ||
| 2998 | { 0x000099e8, 0x3c466478 }, | ||
| 2999 | { 0x000099ec, 0x0cc80caa }, | ||
| 3000 | { 0x000099f0, 0x00000000 }, | ||
| 3001 | { 0x000099fc, 0x00001042 }, | ||
| 3002 | { 0x0000a210, 0x4080a333 }, | ||
| 3003 | { 0x0000a214, 0x40206c10 }, | ||
| 3004 | { 0x0000a218, 0x009c4060 }, | ||
| 3005 | { 0x0000a220, 0x01834061 }, | ||
| 3006 | { 0x0000a224, 0x00000400 }, | ||
| 3007 | { 0x0000a228, 0x000003b5 }, | ||
| 3008 | { 0x0000a22c, 0x233f71c0 }, | ||
| 3009 | { 0x0000a234, 0x20202020 }, | ||
| 3010 | { 0x0000a238, 0x20202020 }, | ||
| 3011 | { 0x0000a23c, 0x13c88000 }, | ||
| 3012 | { 0x0000a240, 0x38490a20 }, | ||
| 3013 | { 0x0000a244, 0x00007bb6 }, | ||
| 3014 | { 0x0000a248, 0x0fff3ffc }, | ||
| 3015 | { 0x0000a24c, 0x00000000 }, | ||
| 3016 | { 0x0000a254, 0x00000000 }, | ||
| 3017 | { 0x0000a258, 0x0cdbd380 }, | ||
| 3018 | { 0x0000a25c, 0x0f0f0f01 }, | ||
| 3019 | { 0x0000a260, 0xdfa91f01 }, | ||
| 3020 | { 0x0000a268, 0x00000000 }, | ||
| 3021 | { 0x0000a26c, 0x0ebae9c6 }, | ||
| 3022 | { 0x0000b26c, 0x0ebae9c6 }, | ||
| 3023 | { 0x0000d270, 0x00820820 }, | ||
| 3024 | { 0x0000a278, 0x1ce739ce }, | ||
| 3025 | { 0x0000a27c, 0x050701ce }, | ||
| 3026 | { 0x0000d35c, 0x07ffffef }, | ||
| 3027 | { 0x0000d360, 0x0fffffe7 }, | ||
| 3028 | { 0x0000d364, 0x17ffffe5 }, | ||
| 3029 | { 0x0000d368, 0x1fffffe4 }, | ||
| 3030 | { 0x0000d36c, 0x37ffffe3 }, | ||
| 3031 | { 0x0000d370, 0x3fffffe3 }, | ||
| 3032 | { 0x0000d374, 0x57ffffe3 }, | ||
| 3033 | { 0x0000d378, 0x5fffffe2 }, | ||
| 3034 | { 0x0000d37c, 0x7fffffe2 }, | ||
| 3035 | { 0x0000d380, 0x7f3c7bba }, | ||
| 3036 | { 0x0000d384, 0xf3307ff0 }, | ||
| 3037 | { 0x0000a388, 0x0c000000 }, | ||
| 3038 | { 0x0000a38c, 0x20202020 }, | ||
| 3039 | { 0x0000a390, 0x20202020 }, | ||
| 3040 | { 0x0000a394, 0x1ce739ce }, | ||
| 3041 | { 0x0000a398, 0x000001ce }, | ||
| 3042 | { 0x0000a39c, 0x00000001 }, | ||
| 3043 | { 0x0000a3a0, 0x00000000 }, | ||
| 3044 | { 0x0000a3a4, 0x00000000 }, | ||
| 3045 | { 0x0000a3a8, 0x00000000 }, | ||
| 3046 | { 0x0000a3ac, 0x00000000 }, | ||
| 3047 | { 0x0000a3b0, 0x00000000 }, | ||
| 3048 | { 0x0000a3b4, 0x00000000 }, | ||
| 3049 | { 0x0000a3b8, 0x00000000 }, | ||
| 3050 | { 0x0000a3bc, 0x00000000 }, | ||
| 3051 | { 0x0000a3c0, 0x00000000 }, | ||
| 3052 | { 0x0000a3c4, 0x00000000 }, | ||
| 3053 | { 0x0000a3c8, 0x00000246 }, | ||
| 3054 | { 0x0000a3cc, 0x20202020 }, | ||
| 3055 | { 0x0000a3d0, 0x20202020 }, | ||
| 3056 | { 0x0000a3d4, 0x20202020 }, | ||
| 3057 | { 0x0000a3dc, 0x1ce739ce }, | ||
| 3058 | { 0x0000a3e0, 0x000001ce }, | ||
| 3059 | { 0x0000a3e4, 0x00000000 }, | ||
| 3060 | { 0x0000a3e8, 0x18c43433 }, | ||
| 3061 | { 0x0000a3ec, 0x00f70081 }, | ||
| 3062 | { 0x00007800, 0x00040000 }, | ||
| 3063 | { 0x00007804, 0xdb005012 }, | ||
| 3064 | { 0x00007808, 0x04924914 }, | ||
| 3065 | { 0x0000780c, 0x21084210 }, | ||
| 3066 | { 0x00007810, 0x6d801300 }, | ||
| 3067 | { 0x00007814, 0x0019beff }, | ||
| 3068 | { 0x00007818, 0x07e41000 }, | ||
| 3069 | { 0x0000781c, 0x00392000 }, | ||
| 3070 | { 0x00007820, 0x92592480 }, | ||
| 3071 | { 0x00007824, 0x00040000 }, | ||
| 3072 | { 0x00007828, 0xdb005012 }, | ||
| 3073 | { 0x0000782c, 0x04924914 }, | ||
| 3074 | { 0x00007830, 0x21084210 }, | ||
| 3075 | { 0x00007834, 0x6d801300 }, | ||
| 3076 | { 0x00007838, 0x0019beff }, | ||
| 3077 | { 0x0000783c, 0x07e40000 }, | ||
| 3078 | { 0x00007840, 0x00392000 }, | ||
| 3079 | { 0x00007844, 0x92592480 }, | ||
| 3080 | { 0x00007848, 0x00100000 }, | ||
| 3081 | { 0x0000784c, 0x773f0567 }, | ||
| 3082 | { 0x00007850, 0x54214514 }, | ||
| 3083 | { 0x00007854, 0x12035828 }, | ||
| 3084 | { 0x00007858, 0x9259269a }, | ||
| 3085 | { 0x00007860, 0x52802000 }, | ||
| 3086 | { 0x00007864, 0x0a8e370e }, | ||
| 3087 | { 0x00007868, 0xc0102850 }, | ||
| 3088 | { 0x0000786c, 0x812d4000 }, | ||
| 3089 | { 0x00007870, 0x807ec400 }, | ||
| 3090 | { 0x00007874, 0x001b6db0 }, | ||
| 3091 | { 0x00007878, 0x00376b63 }, | ||
| 3092 | { 0x0000787c, 0x06db6db6 }, | ||
| 3093 | { 0x00007880, 0x006d8000 }, | ||
| 3094 | { 0x00007884, 0xffeffffe }, | ||
| 3095 | { 0x00007888, 0xffeffffe }, | ||
| 3096 | { 0x0000788c, 0x00010000 }, | ||
| 3097 | { 0x00007890, 0x02060aeb }, | ||
| 3098 | { 0x00007898, 0x2a850160 }, | ||
| 3099 | }; | ||
| 3100 | |||
| 3101 | static const u32 ar9280Modes_fast_clock_9280_2[][3] = { | ||
| 3102 | { 0x00001030, 0x00000268, 0x000004d0 }, | ||
| 3103 | { 0x00001070, 0x0000018c, 0x00000318 }, | ||
| 3104 | { 0x000010b0, 0x00000fd0, 0x00001fa0 }, | ||
| 3105 | { 0x00008014, 0x044c044c, 0x08980898 }, | ||
| 3106 | { 0x0000801c, 0x148ec02b, 0x148ec057 }, | ||
| 3107 | { 0x00008318, 0x000044c0, 0x00008980 }, | ||
| 3108 | { 0x00009820, 0x02020200, 0x02020200 }, | ||
| 3109 | { 0x00009824, 0x00000f0f, 0x00000f0f }, | ||
| 3110 | { 0x00009828, 0x0b020001, 0x0b020001 }, | ||
| 3111 | { 0x00009834, 0x00000f0f, 0x00000f0f }, | ||
| 3112 | { 0x00009844, 0x03721821, 0x03721821 }, | ||
| 3113 | { 0x00009914, 0x00000898, 0x00000898 }, | ||
| 3114 | { 0x00009918, 0x0000000b, 0x00000016 }, | ||
| 3115 | { 0x00009944, 0xdfbc1210, 0xdfbc1210 }, | ||
| 3116 | }; | ||
| 3117 | |||
| 3118 | |||
| 3119 | |||
| 3120 | static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = { | ||
| 3121 | {0x00004040, 0x9248fd00 }, | ||
| 3122 | {0x00004040, 0x24924924 }, | ||
| 3123 | {0x00004040, 0xa8000019 }, | ||
| 3124 | {0x00004040, 0x13160820 }, | ||
| 3125 | {0x00004040, 0xe5980560 }, | ||
| 3126 | {0x00004040, 0x401dcffc }, | ||
| 3127 | {0x00004040, 0x1aaabe40 }, | ||
| 3128 | {0x00004040, 0xbe105554 }, | ||
| 3129 | {0x00004040, 0x00043007 }, | ||
| 3130 | {0x00004044, 0x00000000 }, | ||
| 3131 | }; | ||
| 3132 | |||
| 3133 | |||
| 3134 | |||
| 3135 | static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = { | ||
| 3136 | {0x00004040, 0x9248fd00 }, | ||
| 3137 | {0x00004040, 0x24924924 }, | ||
| 3138 | {0x00004040, 0xa8000019 }, | ||
| 3139 | {0x00004040, 0x13160820 }, | ||
| 3140 | {0x00004040, 0xe5980560 }, | ||
| 3141 | {0x00004040, 0x401dcffd }, | ||
| 3142 | {0x00004040, 0x1aaabe40 }, | ||
| 3143 | {0x00004040, 0xbe105554 }, | ||
| 3144 | {0x00004040, 0x00043007 }, | ||
| 3145 | {0x00004044, 0x00000000 }, | ||
| 3146 | }; | ||
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c new file mode 100644 index 000000000000..2888778040e4 --- /dev/null +++ b/drivers/net/wireless/ath9k/main.c | |||
| @@ -0,0 +1,1470 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* mac80211 and PCI callbacks */ | ||
| 18 | |||
| 19 | #include <linux/nl80211.h> | ||
| 20 | #include "core.h" | ||
| 21 | |||
| 22 | #define ATH_PCI_VERSION "0.1" | ||
| 23 | |||
| 24 | #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 | ||
| 25 | #define IEEE80211_ACTION_CAT_HT 7 | ||
| 26 | #define IEEE80211_ACTION_HT_TXCHWIDTH 0 | ||
| 27 | |||
| 28 | static char *dev_info = "ath9k"; | ||
| 29 | |||
| 30 | MODULE_AUTHOR("Atheros Communications"); | ||
| 31 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | ||
| 32 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | ||
| 33 | MODULE_LICENSE("Dual BSD/GPL"); | ||
| 34 | |||
| 35 | static struct pci_device_id ath_pci_id_table[] __devinitdata = { | ||
| 36 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ | ||
| 37 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | ||
| 38 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | ||
| 39 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | ||
| 40 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | ||
| 41 | { 0 } | ||
| 42 | }; | ||
| 43 | |||
| 44 | static int ath_get_channel(struct ath_softc *sc, | ||
| 45 | struct ieee80211_channel *chan) | ||
| 46 | { | ||
| 47 | int i; | ||
| 48 | |||
| 49 | for (i = 0; i < sc->sc_ah->ah_nchan; i++) { | ||
| 50 | if (sc->sc_ah->ah_channels[i].channel == chan->center_freq) | ||
| 51 | return i; | ||
| 52 | } | ||
| 53 | |||
| 54 | return -1; | ||
| 55 | } | ||
| 56 | |||
| 57 | static u32 ath_get_extchanmode(struct ath_softc *sc, | ||
| 58 | struct ieee80211_channel *chan) | ||
| 59 | { | ||
| 60 | u32 chanmode = 0; | ||
| 61 | u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset; | ||
| 62 | enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width; | ||
| 63 | |||
| 64 | switch (chan->band) { | ||
| 65 | case IEEE80211_BAND_2GHZ: | ||
| 66 | if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) && | ||
| 67 | (tx_chan_width == ATH9K_HT_MACMODE_20)) | ||
| 68 | chanmode = CHANNEL_G_HT20; | ||
| 69 | if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) && | ||
| 70 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) | ||
| 71 | chanmode = CHANNEL_G_HT40PLUS; | ||
| 72 | if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) && | ||
| 73 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) | ||
| 74 | chanmode = CHANNEL_G_HT40MINUS; | ||
| 75 | break; | ||
| 76 | case IEEE80211_BAND_5GHZ: | ||
| 77 | if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) && | ||
| 78 | (tx_chan_width == ATH9K_HT_MACMODE_20)) | ||
| 79 | chanmode = CHANNEL_A_HT20; | ||
| 80 | if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) && | ||
| 81 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) | ||
| 82 | chanmode = CHANNEL_A_HT40PLUS; | ||
| 83 | if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) && | ||
| 84 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) | ||
| 85 | chanmode = CHANNEL_A_HT40MINUS; | ||
| 86 | break; | ||
| 87 | default: | ||
| 88 | break; | ||
| 89 | } | ||
| 90 | |||
| 91 | return chanmode; | ||
| 92 | } | ||
| 93 | |||
| 94 | |||
| 95 | static int ath_setkey_tkip(struct ath_softc *sc, | ||
| 96 | struct ieee80211_key_conf *key, | ||
| 97 | struct ath9k_keyval *hk, | ||
| 98 | const u8 *addr) | ||
| 99 | { | ||
| 100 | u8 *key_rxmic = NULL; | ||
| 101 | u8 *key_txmic = NULL; | ||
| 102 | |||
| 103 | key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; | ||
| 104 | key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | ||
| 105 | |||
| 106 | if (addr == NULL) { | ||
| 107 | /* Group key installation */ | ||
| 108 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | ||
| 109 | return ath_keyset(sc, key->keyidx, hk, addr); | ||
| 110 | } | ||
| 111 | if (!sc->sc_splitmic) { | ||
| 112 | /* | ||
| 113 | * data key goes at first index, | ||
| 114 | * the hal handles the MIC keys at index+64. | ||
| 115 | */ | ||
| 116 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | ||
| 117 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | ||
| 118 | return ath_keyset(sc, key->keyidx, hk, addr); | ||
| 119 | } | ||
| 120 | /* | ||
| 121 | * TX key goes at first index, RX key at +32. | ||
| 122 | * The hal handles the MIC keys at index+64. | ||
| 123 | */ | ||
| 124 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | ||
| 125 | if (!ath_keyset(sc, key->keyidx, hk, NULL)) { | ||
| 126 | /* Txmic entry failed. No need to proceed further */ | ||
| 127 | DPRINTF(sc, ATH_DBG_KEYCACHE, | ||
| 128 | "%s Setting TX MIC Key Failed\n", __func__); | ||
| 129 | return 0; | ||
| 130 | } | ||
| 131 | |||
| 132 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | ||
| 133 | /* XXX delete tx key on failure? */ | ||
| 134 | return ath_keyset(sc, key->keyidx+32, hk, addr); | ||
| 135 | } | ||
| 136 | |||
| 137 | static int ath_key_config(struct ath_softc *sc, | ||
| 138 | const u8 *addr, | ||
| 139 | struct ieee80211_key_conf *key) | ||
| 140 | { | ||
| 141 | struct ieee80211_vif *vif; | ||
| 142 | struct ath9k_keyval hk; | ||
| 143 | const u8 *mac = NULL; | ||
| 144 | int ret = 0; | ||
| 145 | enum ieee80211_if_types opmode; | ||
| 146 | |||
| 147 | memset(&hk, 0, sizeof(hk)); | ||
| 148 | |||
| 149 | switch (key->alg) { | ||
| 150 | case ALG_WEP: | ||
| 151 | hk.kv_type = ATH9K_CIPHER_WEP; | ||
| 152 | break; | ||
| 153 | case ALG_TKIP: | ||
| 154 | hk.kv_type = ATH9K_CIPHER_TKIP; | ||
| 155 | break; | ||
| 156 | case ALG_CCMP: | ||
| 157 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | ||
| 158 | break; | ||
| 159 | default: | ||
| 160 | return -EINVAL; | ||
| 161 | } | ||
| 162 | |||
| 163 | hk.kv_len = key->keylen; | ||
| 164 | memcpy(hk.kv_val, key->key, key->keylen); | ||
| 165 | |||
| 166 | if (!sc->sc_vaps[0]) | ||
| 167 | return -EIO; | ||
| 168 | |||
| 169 | vif = sc->sc_vaps[0]->av_if_data; | ||
| 170 | opmode = vif->type; | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Strategy: | ||
| 174 | * For _M_STA mc tx, we will not setup a key at all since we never | ||
| 175 | * tx mc. | ||
| 176 | * _M_STA mc rx, we will use the keyID. | ||
| 177 | * for _M_IBSS mc tx, we will use the keyID, and no macaddr. | ||
| 178 | * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the | ||
| 179 | * peer node. BUT we will plumb a cleartext key so that we can do | ||
| 180 | * perSta default key table lookup in software. | ||
| 181 | */ | ||
| 182 | if (is_broadcast_ether_addr(addr)) { | ||
| 183 | switch (opmode) { | ||
| 184 | case IEEE80211_IF_TYPE_STA: | ||
| 185 | /* default key: could be group WPA key | ||
| 186 | * or could be static WEP key */ | ||
| 187 | mac = NULL; | ||
| 188 | break; | ||
| 189 | case IEEE80211_IF_TYPE_IBSS: | ||
| 190 | break; | ||
| 191 | case IEEE80211_IF_TYPE_AP: | ||
| 192 | break; | ||
| 193 | default: | ||
| 194 | ASSERT(0); | ||
| 195 | break; | ||
| 196 | } | ||
| 197 | } else { | ||
| 198 | mac = addr; | ||
| 199 | } | ||
| 200 | |||
| 201 | if (key->alg == ALG_TKIP) | ||
| 202 | ret = ath_setkey_tkip(sc, key, &hk, mac); | ||
| 203 | else | ||
| 204 | ret = ath_keyset(sc, key->keyidx, &hk, mac); | ||
| 205 | |||
| 206 | if (!ret) | ||
| 207 | return -EIO; | ||
| 208 | |||
| 209 | sc->sc_keytype = hk.kv_type; | ||
| 210 | return 0; | ||
| 211 | } | ||
| 212 | |||
| 213 | static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) | ||
| 214 | { | ||
| 215 | #define ATH_MAX_NUM_KEYS 4 | ||
| 216 | int freeslot; | ||
| 217 | |||
| 218 | freeslot = (key->keyidx >= ATH_MAX_NUM_KEYS) ? 1 : 0; | ||
| 219 | ath_key_reset(sc, key->keyidx, freeslot); | ||
| 220 | #undef ATH_MAX_NUM_KEYS | ||
| 221 | } | ||
| 222 | |||
| 223 | static void setup_ht_cap(struct ieee80211_ht_info *ht_info) | ||
| 224 | { | ||
| 225 | /* Until mac80211 includes these fields */ | ||
| 226 | |||
| 227 | #define IEEE80211_HT_CAP_DSSSCCK40 0x1000 | ||
| 228 | #define IEEE80211_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */ | ||
| 229 | #define IEEE80211_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */ | ||
| 230 | |||
| 231 | ht_info->ht_supported = 1; | ||
| 232 | ht_info->cap = (u16)IEEE80211_HT_CAP_SUP_WIDTH | ||
| 233 | |(u16)IEEE80211_HT_CAP_MIMO_PS | ||
| 234 | |(u16)IEEE80211_HT_CAP_SGI_40 | ||
| 235 | |(u16)IEEE80211_HT_CAP_DSSSCCK40; | ||
| 236 | |||
| 237 | ht_info->ampdu_factor = IEEE80211_HT_CAP_MAXRXAMPDU_65536; | ||
| 238 | ht_info->ampdu_density = IEEE80211_HT_CAP_MPDUDENSITY_8; | ||
| 239 | /* setup supported mcs set */ | ||
| 240 | memset(ht_info->supp_mcs_set, 0, 16); | ||
| 241 | ht_info->supp_mcs_set[0] = 0xff; | ||
| 242 | ht_info->supp_mcs_set[1] = 0xff; | ||
| 243 | ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED; | ||
| 244 | } | ||
| 245 | |||
| 246 | static int ath_rate2idx(struct ath_softc *sc, int rate) | ||
| 247 | { | ||
| 248 | int i = 0, cur_band, n_rates; | ||
| 249 | struct ieee80211_hw *hw = sc->hw; | ||
| 250 | |||
| 251 | cur_band = hw->conf.channel->band; | ||
| 252 | n_rates = sc->sbands[cur_band].n_bitrates; | ||
| 253 | |||
| 254 | for (i = 0; i < n_rates; i++) { | ||
| 255 | if (sc->sbands[cur_band].bitrates[i].bitrate == rate) | ||
| 256 | break; | ||
| 257 | } | ||
| 258 | |||
| 259 | /* | ||
| 260 | * NB:mac80211 validates rx rate index against the supported legacy rate | ||
| 261 | * index only (should be done against ht rates also), return the highest | ||
| 262 | * legacy rate index for rx rate which does not match any one of the | ||
| 263 | * supported basic and extended rates to make mac80211 happy. | ||
| 264 | * The following hack will be cleaned up once the issue with | ||
| 265 | * the rx rate index validation in mac80211 is fixed. | ||
| 266 | */ | ||
| 267 | if (i == n_rates) | ||
| 268 | return n_rates - 1; | ||
| 269 | return i; | ||
| 270 | } | ||
| 271 | |||
| 272 | static void ath9k_rx_prepare(struct ath_softc *sc, | ||
| 273 | struct sk_buff *skb, | ||
| 274 | struct ath_recv_status *status, | ||
| 275 | struct ieee80211_rx_status *rx_status) | ||
| 276 | { | ||
| 277 | struct ieee80211_hw *hw = sc->hw; | ||
| 278 | struct ieee80211_channel *curchan = hw->conf.channel; | ||
| 279 | |||
| 280 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | ||
| 281 | |||
| 282 | rx_status->mactime = status->tsf; | ||
| 283 | rx_status->band = curchan->band; | ||
| 284 | rx_status->freq = curchan->center_freq; | ||
| 285 | rx_status->noise = ATH_DEFAULT_NOISE_FLOOR; | ||
| 286 | rx_status->signal = rx_status->noise + status->rssi; | ||
| 287 | rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100)); | ||
| 288 | rx_status->antenna = status->antenna; | ||
| 289 | rx_status->qual = status->rssi * 100 / 64; | ||
| 290 | |||
| 291 | if (status->flags & ATH_RX_MIC_ERROR) | ||
| 292 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | ||
| 293 | if (status->flags & ATH_RX_FCS_ERROR) | ||
| 294 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | ||
| 295 | |||
| 296 | rx_status->flag |= RX_FLAG_TSFT; | ||
| 297 | } | ||
| 298 | |||
| 299 | static u8 parse_mpdudensity(u8 mpdudensity) | ||
| 300 | { | ||
| 301 | /* | ||
| 302 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | ||
| 303 | * 0 for no restriction | ||
| 304 | * 1 for 1/4 us | ||
| 305 | * 2 for 1/2 us | ||
| 306 | * 3 for 1 us | ||
| 307 | * 4 for 2 us | ||
| 308 | * 5 for 4 us | ||
| 309 | * 6 for 8 us | ||
| 310 | * 7 for 16 us | ||
| 311 | */ | ||
| 312 | switch (mpdudensity) { | ||
| 313 | case 0: | ||
| 314 | return 0; | ||
| 315 | case 1: | ||
| 316 | case 2: | ||
| 317 | case 3: | ||
| 318 | /* Our lower layer calculations limit our precision to | ||
| 319 | 1 microsecond */ | ||
| 320 | return 1; | ||
| 321 | case 4: | ||
| 322 | return 2; | ||
| 323 | case 5: | ||
| 324 | return 4; | ||
| 325 | case 6: | ||
| 326 | return 8; | ||
| 327 | case 7: | ||
| 328 | return 16; | ||
| 329 | default: | ||
| 330 | return 0; | ||
| 331 | } | ||
| 332 | } | ||
| 333 | |||
| 334 | static int ath9k_start(struct ieee80211_hw *hw) | ||
| 335 | { | ||
| 336 | struct ath_softc *sc = hw->priv; | ||
| 337 | struct ieee80211_channel *curchan = hw->conf.channel; | ||
| 338 | int error = 0, pos; | ||
| 339 | |||
| 340 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with " | ||
| 341 | "initial channel: %d MHz\n", __func__, curchan->center_freq); | ||
| 342 | |||
| 343 | /* setup initial channel */ | ||
| 344 | |||
| 345 | pos = ath_get_channel(sc, curchan); | ||
| 346 | if (pos == -1) { | ||
| 347 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__); | ||
| 348 | return -EINVAL; | ||
| 349 | } | ||
| 350 | |||
| 351 | sc->sc_ah->ah_channels[pos].chanmode = | ||
| 352 | (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A; | ||
| 353 | |||
| 354 | /* open ath_dev */ | ||
| 355 | error = ath_open(sc, &sc->sc_ah->ah_channels[pos]); | ||
| 356 | if (error) { | ||
| 357 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 358 | "%s: Unable to complete ath_open\n", __func__); | ||
| 359 | return error; | ||
| 360 | } | ||
| 361 | |||
| 362 | ieee80211_wake_queues(hw); | ||
| 363 | return 0; | ||
| 364 | } | ||
| 365 | |||
| 366 | static int ath9k_tx(struct ieee80211_hw *hw, | ||
| 367 | struct sk_buff *skb) | ||
| 368 | { | ||
| 369 | struct ath_softc *sc = hw->priv; | ||
| 370 | int hdrlen, padsize; | ||
| 371 | |||
| 372 | /* Add the padding after the header if this is not already done */ | ||
| 373 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | ||
| 374 | if (hdrlen & 3) { | ||
| 375 | padsize = hdrlen % 4; | ||
| 376 | if (skb_headroom(skb) < padsize) | ||
| 377 | return -1; | ||
| 378 | skb_push(skb, padsize); | ||
| 379 | memmove(skb->data, skb->data + padsize, hdrlen); | ||
| 380 | } | ||
| 381 | |||
| 382 | DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n", | ||
| 383 | __func__, | ||
| 384 | skb); | ||
| 385 | |||
| 386 | if (ath_tx_start(sc, skb) != 0) { | ||
| 387 | DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__); | ||
| 388 | dev_kfree_skb_any(skb); | ||
| 389 | /* FIXME: Check for proper return value from ATH_DEV */ | ||
| 390 | return 0; | ||
| 391 | } | ||
| 392 | |||
| 393 | return 0; | ||
| 394 | } | ||
| 395 | |||
| 396 | static void ath9k_stop(struct ieee80211_hw *hw) | ||
| 397 | { | ||
| 398 | struct ath_softc *sc = hw->priv; | ||
| 399 | int error; | ||
| 400 | |||
| 401 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__); | ||
| 402 | |||
| 403 | error = ath_suspend(sc); | ||
| 404 | if (error) | ||
| 405 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 406 | "%s: Device is no longer present\n", __func__); | ||
| 407 | |||
| 408 | ieee80211_stop_queues(hw); | ||
| 409 | } | ||
| 410 | |||
| 411 | static int ath9k_add_interface(struct ieee80211_hw *hw, | ||
| 412 | struct ieee80211_if_init_conf *conf) | ||
| 413 | { | ||
| 414 | struct ath_softc *sc = hw->priv; | ||
| 415 | int error, ic_opmode = 0; | ||
| 416 | |||
| 417 | /* Support only vap for now */ | ||
| 418 | |||
| 419 | if (sc->sc_nvaps) | ||
| 420 | return -ENOBUFS; | ||
| 421 | |||
| 422 | switch (conf->type) { | ||
| 423 | case IEEE80211_IF_TYPE_STA: | ||
| 424 | ic_opmode = ATH9K_M_STA; | ||
| 425 | break; | ||
| 426 | case IEEE80211_IF_TYPE_IBSS: | ||
| 427 | ic_opmode = ATH9K_M_IBSS; | ||
| 428 | break; | ||
| 429 | default: | ||
| 430 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 431 | "%s: Only STA and IBSS are supported currently\n", | ||
| 432 | __func__); | ||
| 433 | return -EOPNOTSUPP; | ||
| 434 | } | ||
| 435 | |||
| 436 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n", | ||
| 437 | __func__, | ||
| 438 | ic_opmode); | ||
| 439 | |||
| 440 | error = ath_vap_attach(sc, 0, conf->vif, ic_opmode); | ||
| 441 | if (error) { | ||
| 442 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 443 | "%s: Unable to attach vap, error: %d\n", | ||
| 444 | __func__, error); | ||
| 445 | return error; | ||
| 446 | } | ||
| 447 | |||
| 448 | return 0; | ||
| 449 | } | ||
| 450 | |||
| 451 | static void ath9k_remove_interface(struct ieee80211_hw *hw, | ||
| 452 | struct ieee80211_if_init_conf *conf) | ||
| 453 | { | ||
| 454 | struct ath_softc *sc = hw->priv; | ||
| 455 | struct ath_vap *avp; | ||
| 456 | int error; | ||
| 457 | |||
| 458 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__); | ||
| 459 | |||
| 460 | avp = sc->sc_vaps[0]; | ||
| 461 | if (avp == NULL) { | ||
| 462 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n", | ||
| 463 | __func__); | ||
| 464 | return; | ||
| 465 | } | ||
| 466 | |||
| 467 | #ifdef CONFIG_SLOW_ANT_DIV | ||
| 468 | ath_slow_ant_div_stop(&sc->sc_antdiv); | ||
| 469 | #endif | ||
| 470 | |||
| 471 | /* Update ratectrl */ | ||
| 472 | ath_rate_newstate(sc, avp); | ||
| 473 | |||
| 474 | /* Reclaim beacon resources */ | ||
| 475 | if (sc->sc_opmode == ATH9K_M_HOSTAP || sc->sc_opmode == ATH9K_M_IBSS) { | ||
| 476 | ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); | ||
| 477 | ath_beacon_return(sc, avp); | ||
| 478 | } | ||
| 479 | |||
| 480 | /* Set interrupt mask */ | ||
| 481 | sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); | ||
| 482 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL); | ||
| 483 | sc->sc_beacons = 0; | ||
| 484 | |||
| 485 | error = ath_vap_detach(sc, 0); | ||
| 486 | if (error) | ||
| 487 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 488 | "%s: Unable to detach vap, error: %d\n", | ||
| 489 | __func__, error); | ||
| 490 | } | ||
| 491 | |||
| 492 | static int ath9k_config(struct ieee80211_hw *hw, | ||
| 493 | struct ieee80211_conf *conf) | ||
| 494 | { | ||
| 495 | struct ath_softc *sc = hw->priv; | ||
| 496 | struct ieee80211_channel *curchan = hw->conf.channel; | ||
| 497 | int pos; | ||
| 498 | |||
| 499 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n", | ||
| 500 | __func__, | ||
| 501 | curchan->center_freq); | ||
| 502 | |||
| 503 | pos = ath_get_channel(sc, curchan); | ||
| 504 | if (pos == -1) { | ||
| 505 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__); | ||
| 506 | return -EINVAL; | ||
| 507 | } | ||
| 508 | |||
| 509 | sc->sc_ah->ah_channels[pos].chanmode = | ||
| 510 | (curchan->band == IEEE80211_BAND_2GHZ) ? | ||
| 511 | CHANNEL_G : CHANNEL_A; | ||
| 512 | |||
| 513 | if (sc->sc_curaid && hw->conf.ht_conf.ht_supported) | ||
| 514 | sc->sc_ah->ah_channels[pos].chanmode = | ||
| 515 | ath_get_extchanmode(sc, curchan); | ||
| 516 | |||
| 517 | sc->sc_config.txpowlimit = 2 * conf->power_level; | ||
| 518 | |||
| 519 | /* set h/w channel */ | ||
| 520 | if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) | ||
| 521 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n", | ||
| 522 | __func__); | ||
| 523 | |||
| 524 | return 0; | ||
| 525 | } | ||
| 526 | |||
| 527 | static int ath9k_config_interface(struct ieee80211_hw *hw, | ||
| 528 | struct ieee80211_vif *vif, | ||
| 529 | struct ieee80211_if_conf *conf) | ||
| 530 | { | ||
| 531 | struct ath_softc *sc = hw->priv; | ||
| 532 | struct ath_vap *avp; | ||
| 533 | u32 rfilt = 0; | ||
| 534 | int error, i; | ||
| 535 | DECLARE_MAC_BUF(mac); | ||
| 536 | |||
| 537 | avp = sc->sc_vaps[0]; | ||
| 538 | if (avp == NULL) { | ||
| 539 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n", | ||
| 540 | __func__); | ||
| 541 | return -EINVAL; | ||
| 542 | } | ||
| 543 | |||
| 544 | if ((conf->changed & IEEE80211_IFCC_BSSID) && | ||
| 545 | !is_zero_ether_addr(conf->bssid)) { | ||
| 546 | switch (vif->type) { | ||
| 547 | case IEEE80211_IF_TYPE_STA: | ||
| 548 | case IEEE80211_IF_TYPE_IBSS: | ||
| 549 | /* Update ratectrl about the new state */ | ||
| 550 | ath_rate_newstate(sc, avp); | ||
| 551 | |||
| 552 | /* Set rx filter */ | ||
| 553 | rfilt = ath_calcrxfilter(sc); | ||
| 554 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | ||
| 555 | |||
| 556 | /* Set BSSID */ | ||
| 557 | memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN); | ||
| 558 | sc->sc_curaid = 0; | ||
| 559 | ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, | ||
| 560 | sc->sc_curaid); | ||
| 561 | |||
| 562 | /* Set aggregation protection mode parameters */ | ||
| 563 | sc->sc_config.ath_aggr_prot = 0; | ||
| 564 | |||
| 565 | /* | ||
| 566 | * Reset our TSF so that its value is lower than the | ||
| 567 | * beacon that we are trying to catch. | ||
| 568 | * Only then hw will update its TSF register with the | ||
| 569 | * new beacon. Reset the TSF before setting the BSSID | ||
| 570 | * to avoid allowing in any frames that would update | ||
| 571 | * our TSF only to have us clear it | ||
| 572 | * immediately thereafter. | ||
| 573 | */ | ||
| 574 | ath9k_hw_reset_tsf(sc->sc_ah); | ||
| 575 | |||
| 576 | /* Disable BMISS interrupt when we're not associated */ | ||
| 577 | ath9k_hw_set_interrupts(sc->sc_ah, | ||
| 578 | sc->sc_imask & | ||
| 579 | ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS)); | ||
| 580 | sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); | ||
| 581 | |||
| 582 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 583 | "%s: RX filter 0x%x bssid %s aid 0x%x\n", | ||
| 584 | __func__, rfilt, | ||
| 585 | print_mac(mac, sc->sc_curbssid), sc->sc_curaid); | ||
| 586 | |||
| 587 | /* need to reconfigure the beacon */ | ||
| 588 | sc->sc_beacons = 0; | ||
| 589 | |||
| 590 | break; | ||
| 591 | default: | ||
| 592 | break; | ||
| 593 | } | ||
| 594 | } | ||
| 595 | |||
| 596 | if ((conf->changed & IEEE80211_IFCC_BEACON) && | ||
| 597 | (vif->type == IEEE80211_IF_TYPE_IBSS)) { | ||
| 598 | /* | ||
| 599 | * Allocate and setup the beacon frame. | ||
| 600 | * | ||
| 601 | * Stop any previous beacon DMA. This may be | ||
| 602 | * necessary, for example, when an ibss merge | ||
| 603 | * causes reconfiguration; we may be called | ||
| 604 | * with beacon transmission active. | ||
| 605 | */ | ||
| 606 | ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); | ||
| 607 | |||
| 608 | error = ath_beacon_alloc(sc, 0); | ||
| 609 | if (error != 0) | ||
| 610 | return error; | ||
| 611 | |||
| 612 | ath_beacon_sync(sc, 0); | ||
| 613 | } | ||
| 614 | |||
| 615 | /* Check for WLAN_CAPABILITY_PRIVACY ? */ | ||
| 616 | if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) { | ||
| 617 | for (i = 0; i < IEEE80211_WEP_NKID; i++) | ||
| 618 | if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) | ||
| 619 | ath9k_hw_keysetmac(sc->sc_ah, | ||
| 620 | (u16)i, | ||
| 621 | sc->sc_curbssid); | ||
| 622 | } | ||
| 623 | |||
| 624 | /* Only legacy IBSS for now */ | ||
| 625 | if (vif->type == IEEE80211_IF_TYPE_IBSS) | ||
| 626 | ath_update_chainmask(sc, 0); | ||
| 627 | |||
| 628 | return 0; | ||
| 629 | } | ||
| 630 | |||
| 631 | #define SUPPORTED_FILTERS \ | ||
| 632 | (FIF_PROMISC_IN_BSS | \ | ||
| 633 | FIF_ALLMULTI | \ | ||
| 634 | FIF_CONTROL | \ | ||
| 635 | FIF_OTHER_BSS | \ | ||
| 636 | FIF_BCN_PRBRESP_PROMISC | \ | ||
| 637 | FIF_FCSFAIL) | ||
| 638 | |||
| 639 | /* Accept unicast, bcast and mcast frames */ | ||
| 640 | |||
| 641 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | ||
| 642 | unsigned int changed_flags, | ||
| 643 | unsigned int *total_flags, | ||
| 644 | int mc_count, | ||
| 645 | struct dev_mc_list *mclist) | ||
| 646 | { | ||
| 647 | struct ath_softc *sc = hw->priv; | ||
| 648 | |||
| 649 | changed_flags &= SUPPORTED_FILTERS; | ||
| 650 | *total_flags &= SUPPORTED_FILTERS; | ||
| 651 | |||
| 652 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { | ||
| 653 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | ||
| 654 | ath_scan_start(sc); | ||
| 655 | else | ||
| 656 | ath_scan_end(sc); | ||
| 657 | } | ||
| 658 | } | ||
| 659 | |||
| 660 | static void ath9k_sta_notify(struct ieee80211_hw *hw, | ||
| 661 | struct ieee80211_vif *vif, | ||
| 662 | enum sta_notify_cmd cmd, | ||
| 663 | const u8 *addr) | ||
| 664 | { | ||
| 665 | struct ath_softc *sc = hw->priv; | ||
| 666 | struct ath_node *an; | ||
| 667 | unsigned long flags; | ||
| 668 | DECLARE_MAC_BUF(mac); | ||
| 669 | |||
| 670 | spin_lock_irqsave(&sc->node_lock, flags); | ||
| 671 | an = ath_node_find(sc, (u8 *) addr); | ||
| 672 | spin_unlock_irqrestore(&sc->node_lock, flags); | ||
| 673 | |||
| 674 | switch (cmd) { | ||
| 675 | case STA_NOTIFY_ADD: | ||
| 676 | spin_lock_irqsave(&sc->node_lock, flags); | ||
| 677 | if (!an) { | ||
| 678 | ath_node_attach(sc, (u8 *)addr, 0); | ||
| 679 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n", | ||
| 680 | __func__, | ||
| 681 | print_mac(mac, addr)); | ||
| 682 | } else { | ||
| 683 | ath_node_get(sc, (u8 *)addr); | ||
| 684 | } | ||
| 685 | spin_unlock_irqrestore(&sc->node_lock, flags); | ||
| 686 | break; | ||
| 687 | case STA_NOTIFY_REMOVE: | ||
| 688 | if (!an) | ||
| 689 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 690 | "%s: Removal of a non-existent node\n", | ||
| 691 | __func__); | ||
| 692 | else { | ||
| 693 | ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT); | ||
| 694 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n", | ||
| 695 | __func__, | ||
| 696 | print_mac(mac, addr)); | ||
| 697 | } | ||
| 698 | break; | ||
| 699 | default: | ||
| 700 | break; | ||
| 701 | } | ||
| 702 | } | ||
| 703 | |||
| 704 | static int ath9k_conf_tx(struct ieee80211_hw *hw, | ||
| 705 | u16 queue, | ||
| 706 | const struct ieee80211_tx_queue_params *params) | ||
| 707 | { | ||
| 708 | struct ath_softc *sc = hw->priv; | ||
| 709 | struct ath9k_tx_queue_info qi; | ||
| 710 | int ret = 0, qnum; | ||
| 711 | |||
| 712 | if (queue >= WME_NUM_AC) | ||
| 713 | return 0; | ||
| 714 | |||
| 715 | qi.tqi_aifs = params->aifs; | ||
| 716 | qi.tqi_cwmin = params->cw_min; | ||
| 717 | qi.tqi_cwmax = params->cw_max; | ||
| 718 | qi.tqi_burstTime = params->txop; | ||
| 719 | qnum = ath_get_hal_qnum(queue, sc); | ||
| 720 | |||
| 721 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 722 | "%s: Configure tx [queue/halq] [%d/%d], " | ||
| 723 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | ||
| 724 | __func__, | ||
| 725 | queue, | ||
| 726 | qnum, | ||
| 727 | params->aifs, | ||
| 728 | params->cw_min, | ||
| 729 | params->cw_max, | ||
| 730 | params->txop); | ||
| 731 | |||
| 732 | ret = ath_txq_update(sc, qnum, &qi); | ||
| 733 | if (ret) | ||
| 734 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 735 | "%s: TXQ Update failed\n", __func__); | ||
| 736 | |||
| 737 | return ret; | ||
| 738 | } | ||
| 739 | |||
| 740 | static int ath9k_set_key(struct ieee80211_hw *hw, | ||
| 741 | enum set_key_cmd cmd, | ||
| 742 | const u8 *local_addr, | ||
| 743 | const u8 *addr, | ||
| 744 | struct ieee80211_key_conf *key) | ||
| 745 | { | ||
| 746 | struct ath_softc *sc = hw->priv; | ||
| 747 | int ret = 0; | ||
| 748 | |||
| 749 | DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__); | ||
| 750 | |||
| 751 | switch (cmd) { | ||
| 752 | case SET_KEY: | ||
| 753 | ret = ath_key_config(sc, addr, key); | ||
| 754 | if (!ret) { | ||
| 755 | set_bit(key->keyidx, sc->sc_keymap); | ||
| 756 | key->hw_key_idx = key->keyidx; | ||
| 757 | /* push IV and Michael MIC generation to stack */ | ||
| 758 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | ||
| 759 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | ||
| 760 | } | ||
| 761 | break; | ||
| 762 | case DISABLE_KEY: | ||
| 763 | ath_key_delete(sc, key); | ||
| 764 | clear_bit(key->keyidx, sc->sc_keymap); | ||
| 765 | sc->sc_keytype = ATH9K_CIPHER_CLR; | ||
| 766 | break; | ||
| 767 | default: | ||
| 768 | ret = -EINVAL; | ||
| 769 | } | ||
| 770 | |||
| 771 | return ret; | ||
| 772 | } | ||
| 773 | |||
| 774 | static void ath9k_ht_conf(struct ath_softc *sc, | ||
| 775 | struct ieee80211_bss_conf *bss_conf) | ||
| 776 | { | ||
| 777 | #define IEEE80211_HT_CAP_40MHZ_INTOLERANT BIT(14) | ||
| 778 | struct ath_ht_info *ht_info = &sc->sc_ht_info; | ||
| 779 | |||
| 780 | if (bss_conf->assoc_ht) { | ||
| 781 | ht_info->ext_chan_offset = | ||
| 782 | bss_conf->ht_bss_conf->bss_cap & | ||
| 783 | IEEE80211_HT_IE_CHA_SEC_OFFSET; | ||
| 784 | |||
| 785 | if (!(bss_conf->ht_conf->cap & | ||
| 786 | IEEE80211_HT_CAP_40MHZ_INTOLERANT) && | ||
| 787 | (bss_conf->ht_bss_conf->bss_cap & | ||
| 788 | IEEE80211_HT_IE_CHA_WIDTH)) | ||
| 789 | ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040; | ||
| 790 | else | ||
| 791 | ht_info->tx_chan_width = ATH9K_HT_MACMODE_20; | ||
| 792 | |||
| 793 | ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width); | ||
| 794 | ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR + | ||
| 795 | bss_conf->ht_conf->ampdu_factor); | ||
| 796 | ht_info->mpdudensity = | ||
| 797 | parse_mpdudensity(bss_conf->ht_conf->ampdu_density); | ||
| 798 | |||
| 799 | } | ||
| 800 | |||
| 801 | #undef IEEE80211_HT_CAP_40MHZ_INTOLERANT | ||
| 802 | } | ||
| 803 | |||
| 804 | static void ath9k_bss_assoc_info(struct ath_softc *sc, | ||
| 805 | struct ieee80211_bss_conf *bss_conf) | ||
| 806 | { | ||
| 807 | struct ieee80211_hw *hw = sc->hw; | ||
| 808 | struct ieee80211_channel *curchan = hw->conf.channel; | ||
| 809 | struct ath_vap *avp; | ||
| 810 | int pos; | ||
| 811 | DECLARE_MAC_BUF(mac); | ||
| 812 | |||
| 813 | if (bss_conf->assoc) { | ||
| 814 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n", | ||
| 815 | __func__, | ||
| 816 | bss_conf->aid); | ||
| 817 | |||
| 818 | avp = sc->sc_vaps[0]; | ||
| 819 | if (avp == NULL) { | ||
| 820 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n", | ||
| 821 | __func__); | ||
| 822 | return; | ||
| 823 | } | ||
| 824 | |||
| 825 | /* New association, store aid */ | ||
| 826 | if (avp->av_opmode == ATH9K_M_STA) { | ||
| 827 | sc->sc_curaid = bss_conf->aid; | ||
| 828 | ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, | ||
| 829 | sc->sc_curaid); | ||
| 830 | } | ||
| 831 | |||
| 832 | /* Configure the beacon */ | ||
| 833 | ath_beacon_config(sc, 0); | ||
| 834 | sc->sc_beacons = 1; | ||
| 835 | |||
| 836 | /* Reset rssi stats */ | ||
| 837 | sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; | ||
| 838 | sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; | ||
| 839 | sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; | ||
| 840 | sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; | ||
| 841 | |||
| 842 | /* Update chainmask */ | ||
| 843 | ath_update_chainmask(sc, bss_conf->assoc_ht); | ||
| 844 | |||
| 845 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 846 | "%s: bssid %s aid 0x%x\n", | ||
| 847 | __func__, | ||
| 848 | print_mac(mac, sc->sc_curbssid), sc->sc_curaid); | ||
| 849 | |||
| 850 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n", | ||
| 851 | __func__, | ||
| 852 | curchan->center_freq); | ||
| 853 | |||
| 854 | pos = ath_get_channel(sc, curchan); | ||
| 855 | if (pos == -1) { | ||
| 856 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 857 | "%s: Invalid channel\n", __func__); | ||
| 858 | return; | ||
| 859 | } | ||
| 860 | |||
| 861 | if (hw->conf.ht_conf.ht_supported) | ||
| 862 | sc->sc_ah->ah_channels[pos].chanmode = | ||
| 863 | ath_get_extchanmode(sc, curchan); | ||
| 864 | else | ||
| 865 | sc->sc_ah->ah_channels[pos].chanmode = | ||
| 866 | (curchan->band == IEEE80211_BAND_2GHZ) ? | ||
| 867 | CHANNEL_G : CHANNEL_A; | ||
| 868 | |||
| 869 | /* set h/w channel */ | ||
| 870 | if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) | ||
| 871 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 872 | "%s: Unable to set channel\n", | ||
| 873 | __func__); | ||
| 874 | |||
| 875 | ath_rate_newstate(sc, avp); | ||
| 876 | /* Update ratectrl about the new state */ | ||
| 877 | ath_rc_node_update(hw, avp->rc_node); | ||
| 878 | } else { | ||
| 879 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 880 | "%s: Bss Info DISSOC\n", __func__); | ||
| 881 | sc->sc_curaid = 0; | ||
| 882 | } | ||
| 883 | } | ||
| 884 | |||
| 885 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | ||
| 886 | struct ieee80211_vif *vif, | ||
| 887 | struct ieee80211_bss_conf *bss_conf, | ||
| 888 | u32 changed) | ||
| 889 | { | ||
| 890 | struct ath_softc *sc = hw->priv; | ||
| 891 | |||
| 892 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { | ||
| 893 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n", | ||
| 894 | __func__, | ||
| 895 | bss_conf->use_short_preamble); | ||
| 896 | if (bss_conf->use_short_preamble) | ||
| 897 | sc->sc_flags |= ATH_PREAMBLE_SHORT; | ||
| 898 | else | ||
| 899 | sc->sc_flags &= ~ATH_PREAMBLE_SHORT; | ||
| 900 | } | ||
| 901 | |||
| 902 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { | ||
| 903 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n", | ||
| 904 | __func__, | ||
| 905 | bss_conf->use_cts_prot); | ||
| 906 | if (bss_conf->use_cts_prot && | ||
| 907 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | ||
| 908 | sc->sc_flags |= ATH_PROTECT_ENABLE; | ||
| 909 | else | ||
| 910 | sc->sc_flags &= ~ATH_PROTECT_ENABLE; | ||
| 911 | } | ||
| 912 | |||
| 913 | if (changed & BSS_CHANGED_HT) { | ||
| 914 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n", | ||
| 915 | __func__, | ||
| 916 | bss_conf->assoc_ht); | ||
| 917 | ath9k_ht_conf(sc, bss_conf); | ||
| 918 | } | ||
| 919 | |||
| 920 | if (changed & BSS_CHANGED_ASSOC) { | ||
| 921 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n", | ||
| 922 | __func__, | ||
| 923 | bss_conf->assoc); | ||
| 924 | ath9k_bss_assoc_info(sc, bss_conf); | ||
| 925 | } | ||
| 926 | } | ||
| 927 | |||
| 928 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) | ||
| 929 | { | ||
| 930 | u64 tsf; | ||
| 931 | struct ath_softc *sc = hw->priv; | ||
| 932 | struct ath_hal *ah = sc->sc_ah; | ||
| 933 | |||
| 934 | tsf = ath9k_hw_gettsf64(ah); | ||
| 935 | |||
| 936 | return tsf; | ||
| 937 | } | ||
| 938 | |||
| 939 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) | ||
| 940 | { | ||
| 941 | struct ath_softc *sc = hw->priv; | ||
| 942 | struct ath_hal *ah = sc->sc_ah; | ||
| 943 | |||
| 944 | ath9k_hw_reset_tsf(ah); | ||
| 945 | } | ||
| 946 | |||
| 947 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, | ||
| 948 | enum ieee80211_ampdu_mlme_action action, | ||
| 949 | const u8 *addr, | ||
| 950 | u16 tid, | ||
| 951 | u16 *ssn) | ||
| 952 | { | ||
| 953 | struct ath_softc *sc = hw->priv; | ||
| 954 | int ret = 0; | ||
| 955 | |||
| 956 | switch (action) { | ||
| 957 | case IEEE80211_AMPDU_RX_START: | ||
| 958 | ret = ath_rx_aggr_start(sc, addr, tid, ssn); | ||
| 959 | if (ret < 0) | ||
| 960 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 961 | "%s: Unable to start RX aggregation\n", | ||
| 962 | __func__); | ||
| 963 | break; | ||
| 964 | case IEEE80211_AMPDU_RX_STOP: | ||
| 965 | ret = ath_rx_aggr_stop(sc, addr, tid); | ||
| 966 | if (ret < 0) | ||
| 967 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 968 | "%s: Unable to stop RX aggregation\n", | ||
| 969 | __func__); | ||
| 970 | break; | ||
| 971 | case IEEE80211_AMPDU_TX_START: | ||
| 972 | ret = ath_tx_aggr_start(sc, addr, tid, ssn); | ||
| 973 | if (ret < 0) | ||
| 974 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 975 | "%s: Unable to start TX aggregation\n", | ||
| 976 | __func__); | ||
| 977 | else | ||
| 978 | ieee80211_start_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid); | ||
| 979 | break; | ||
| 980 | case IEEE80211_AMPDU_TX_STOP: | ||
| 981 | ret = ath_tx_aggr_stop(sc, addr, tid); | ||
| 982 | if (ret < 0) | ||
| 983 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 984 | "%s: Unable to stop TX aggregation\n", | ||
| 985 | __func__); | ||
| 986 | |||
| 987 | ieee80211_stop_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid); | ||
| 988 | break; | ||
| 989 | default: | ||
| 990 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 991 | "%s: Unknown AMPDU action\n", __func__); | ||
| 992 | } | ||
| 993 | |||
| 994 | return ret; | ||
| 995 | } | ||
| 996 | |||
| 997 | static struct ieee80211_ops ath9k_ops = { | ||
| 998 | .tx = ath9k_tx, | ||
| 999 | .start = ath9k_start, | ||
| 1000 | .stop = ath9k_stop, | ||
| 1001 | .add_interface = ath9k_add_interface, | ||
| 1002 | .remove_interface = ath9k_remove_interface, | ||
| 1003 | .config = ath9k_config, | ||
| 1004 | .config_interface = ath9k_config_interface, | ||
| 1005 | .configure_filter = ath9k_configure_filter, | ||
| 1006 | .get_stats = NULL, | ||
| 1007 | .sta_notify = ath9k_sta_notify, | ||
| 1008 | .conf_tx = ath9k_conf_tx, | ||
| 1009 | .get_tx_stats = NULL, | ||
| 1010 | .bss_info_changed = ath9k_bss_info_changed, | ||
| 1011 | .set_tim = NULL, | ||
| 1012 | .set_key = ath9k_set_key, | ||
| 1013 | .hw_scan = NULL, | ||
| 1014 | .get_tkip_seq = NULL, | ||
| 1015 | .set_rts_threshold = NULL, | ||
| 1016 | .set_frag_threshold = NULL, | ||
| 1017 | .set_retry_limit = NULL, | ||
| 1018 | .get_tsf = ath9k_get_tsf, | ||
| 1019 | .reset_tsf = ath9k_reset_tsf, | ||
| 1020 | .tx_last_beacon = NULL, | ||
| 1021 | .ampdu_action = ath9k_ampdu_action | ||
| 1022 | }; | ||
| 1023 | |||
| 1024 | void ath_get_beaconconfig(struct ath_softc *sc, | ||
| 1025 | int if_id, | ||
| 1026 | struct ath_beacon_config *conf) | ||
| 1027 | { | ||
| 1028 | struct ieee80211_hw *hw = sc->hw; | ||
| 1029 | |||
| 1030 | /* fill in beacon config data */ | ||
| 1031 | |||
| 1032 | conf->beacon_interval = hw->conf.beacon_int; | ||
| 1033 | conf->listen_interval = 100; | ||
| 1034 | conf->dtim_count = 1; | ||
| 1035 | conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval; | ||
| 1036 | } | ||
| 1037 | |||
| 1038 | int ath_update_beacon(struct ath_softc *sc, | ||
| 1039 | int if_id, | ||
| 1040 | struct ath_beacon_offset *bo, | ||
| 1041 | struct sk_buff *skb, | ||
| 1042 | int mcast) | ||
| 1043 | { | ||
| 1044 | return 0; | ||
| 1045 | } | ||
| 1046 | |||
| 1047 | void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | ||
| 1048 | struct ath_xmit_status *tx_status, struct ath_node *an) | ||
| 1049 | { | ||
| 1050 | struct ieee80211_hw *hw = sc->hw; | ||
| 1051 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 1052 | |||
| 1053 | DPRINTF(sc, ATH_DBG_XMIT, | ||
| 1054 | "%s: TX complete: skb: %p\n", __func__, skb); | ||
| 1055 | |||
| 1056 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || | ||
| 1057 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | ||
| 1058 | /* free driver's private data area of tx_info */ | ||
| 1059 | if (tx_info->driver_data[0] != NULL) | ||
| 1060 | kfree(tx_info->driver_data[0]); | ||
| 1061 | tx_info->driver_data[0] = NULL; | ||
| 1062 | } | ||
| 1063 | |||
| 1064 | if (tx_status->flags & ATH_TX_BAR) { | ||
| 1065 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | ||
| 1066 | tx_status->flags &= ~ATH_TX_BAR; | ||
| 1067 | } | ||
| 1068 | if (tx_status->flags) | ||
| 1069 | tx_info->status.excessive_retries = 1; | ||
| 1070 | |||
| 1071 | tx_info->status.retry_count = tx_status->retries; | ||
| 1072 | |||
| 1073 | ieee80211_tx_status(hw, skb); | ||
| 1074 | if (an) | ||
| 1075 | ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE); | ||
| 1076 | } | ||
| 1077 | |||
| 1078 | int ath__rx_indicate(struct ath_softc *sc, | ||
| 1079 | struct sk_buff *skb, | ||
| 1080 | struct ath_recv_status *status, | ||
| 1081 | u16 keyix) | ||
| 1082 | { | ||
| 1083 | struct ieee80211_hw *hw = sc->hw; | ||
| 1084 | struct ath_node *an = NULL; | ||
| 1085 | struct ieee80211_rx_status rx_status; | ||
| 1086 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | ||
| 1087 | int hdrlen = ieee80211_get_hdrlen_from_skb(skb); | ||
| 1088 | int padsize; | ||
| 1089 | enum ATH_RX_TYPE st; | ||
| 1090 | |||
| 1091 | /* see if any padding is done by the hw and remove it */ | ||
| 1092 | if (hdrlen & 3) { | ||
| 1093 | padsize = hdrlen % 4; | ||
| 1094 | memmove(skb->data + padsize, skb->data, hdrlen); | ||
| 1095 | skb_pull(skb, padsize); | ||
| 1096 | } | ||
| 1097 | |||
| 1098 | /* remove FCS before passing up to protocol stack */ | ||
| 1099 | skb_trim(skb, (skb->len - FCS_LEN)); | ||
| 1100 | |||
| 1101 | /* Prepare rx status */ | ||
| 1102 | ath9k_rx_prepare(sc, skb, status, &rx_status); | ||
| 1103 | |||
| 1104 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && | ||
| 1105 | !(status->flags & ATH_RX_DECRYPT_ERROR)) { | ||
| 1106 | rx_status.flag |= RX_FLAG_DECRYPTED; | ||
| 1107 | } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) | ||
| 1108 | && !(status->flags & ATH_RX_DECRYPT_ERROR) | ||
| 1109 | && skb->len >= hdrlen + 4) { | ||
| 1110 | keyix = skb->data[hdrlen + 3] >> 6; | ||
| 1111 | |||
| 1112 | if (test_bit(keyix, sc->sc_keymap)) | ||
| 1113 | rx_status.flag |= RX_FLAG_DECRYPTED; | ||
| 1114 | } | ||
| 1115 | |||
| 1116 | spin_lock_bh(&sc->node_lock); | ||
| 1117 | an = ath_node_find(sc, hdr->addr2); | ||
| 1118 | spin_unlock_bh(&sc->node_lock); | ||
| 1119 | |||
| 1120 | if (an) { | ||
| 1121 | ath_rx_input(sc, an, | ||
| 1122 | hw->conf.ht_conf.ht_supported, | ||
| 1123 | skb, status, &st); | ||
| 1124 | } | ||
| 1125 | if (!an || (st != ATH_RX_CONSUMED)) | ||
| 1126 | __ieee80211_rx(hw, skb, &rx_status); | ||
| 1127 | |||
| 1128 | return 0; | ||
| 1129 | } | ||
| 1130 | |||
| 1131 | int ath_rx_subframe(struct ath_node *an, | ||
| 1132 | struct sk_buff *skb, | ||
| 1133 | struct ath_recv_status *status) | ||
| 1134 | { | ||
| 1135 | struct ath_softc *sc = an->an_sc; | ||
| 1136 | struct ieee80211_hw *hw = sc->hw; | ||
| 1137 | struct ieee80211_rx_status rx_status; | ||
| 1138 | |||
| 1139 | /* Prepare rx status */ | ||
| 1140 | ath9k_rx_prepare(sc, skb, status, &rx_status); | ||
| 1141 | if (!(status->flags & ATH_RX_DECRYPT_ERROR)) | ||
| 1142 | rx_status.flag |= RX_FLAG_DECRYPTED; | ||
| 1143 | |||
| 1144 | __ieee80211_rx(hw, skb, &rx_status); | ||
| 1145 | |||
| 1146 | return 0; | ||
| 1147 | } | ||
| 1148 | |||
| 1149 | enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc) | ||
| 1150 | { | ||
| 1151 | return sc->sc_ht_info.tx_chan_width; | ||
| 1152 | } | ||
| 1153 | |||
| 1154 | static int ath_detach(struct ath_softc *sc) | ||
| 1155 | { | ||
| 1156 | struct ieee80211_hw *hw = sc->hw; | ||
| 1157 | |||
| 1158 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__); | ||
| 1159 | |||
| 1160 | /* Unregister hw */ | ||
| 1161 | |||
| 1162 | ieee80211_unregister_hw(hw); | ||
| 1163 | |||
| 1164 | /* unregister Rate control */ | ||
| 1165 | ath_rate_control_unregister(); | ||
| 1166 | |||
| 1167 | /* tx/rx cleanup */ | ||
| 1168 | |||
| 1169 | ath_rx_cleanup(sc); | ||
| 1170 | ath_tx_cleanup(sc); | ||
| 1171 | |||
| 1172 | /* Deinit */ | ||
| 1173 | |||
| 1174 | ath_deinit(sc); | ||
| 1175 | |||
| 1176 | return 0; | ||
| 1177 | } | ||
| 1178 | |||
| 1179 | static int ath_attach(u16 devid, | ||
| 1180 | struct ath_softc *sc) | ||
| 1181 | { | ||
| 1182 | struct ieee80211_hw *hw = sc->hw; | ||
| 1183 | int error = 0; | ||
| 1184 | |||
| 1185 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__); | ||
| 1186 | |||
| 1187 | error = ath_init(devid, sc); | ||
| 1188 | if (error != 0) | ||
| 1189 | return error; | ||
| 1190 | |||
| 1191 | /* Init nodes */ | ||
| 1192 | |||
| 1193 | INIT_LIST_HEAD(&sc->node_list); | ||
| 1194 | spin_lock_init(&sc->node_lock); | ||
| 1195 | |||
| 1196 | /* get mac address from hardware and set in mac80211 */ | ||
| 1197 | |||
| 1198 | SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr); | ||
| 1199 | |||
| 1200 | /* setup channels and rates */ | ||
| 1201 | |||
| 1202 | sc->sbands[IEEE80211_BAND_2GHZ].channels = | ||
| 1203 | sc->channels[IEEE80211_BAND_2GHZ]; | ||
| 1204 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = | ||
| 1205 | sc->rates[IEEE80211_BAND_2GHZ]; | ||
| 1206 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | ||
| 1207 | |||
| 1208 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) | ||
| 1209 | /* Setup HT capabilities for 2.4Ghz*/ | ||
| 1210 | setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info); | ||
| 1211 | |||
| 1212 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | ||
| 1213 | &sc->sbands[IEEE80211_BAND_2GHZ]; | ||
| 1214 | |||
| 1215 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { | ||
| 1216 | sc->sbands[IEEE80211_BAND_5GHZ].channels = | ||
| 1217 | sc->channels[IEEE80211_BAND_5GHZ]; | ||
| 1218 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | ||
| 1219 | sc->rates[IEEE80211_BAND_5GHZ]; | ||
| 1220 | sc->sbands[IEEE80211_BAND_5GHZ].band = | ||
| 1221 | IEEE80211_BAND_5GHZ; | ||
| 1222 | |||
| 1223 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) | ||
| 1224 | /* Setup HT capabilities for 5Ghz*/ | ||
| 1225 | setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info); | ||
| 1226 | |||
| 1227 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | ||
| 1228 | &sc->sbands[IEEE80211_BAND_5GHZ]; | ||
| 1229 | } | ||
| 1230 | |||
| 1231 | /* FIXME: Have to figure out proper hw init values later */ | ||
| 1232 | |||
| 1233 | hw->queues = 4; | ||
| 1234 | hw->ampdu_queues = 1; | ||
| 1235 | |||
| 1236 | /* Register rate control */ | ||
| 1237 | hw->rate_control_algorithm = "ath9k_rate_control"; | ||
| 1238 | error = ath_rate_control_register(); | ||
| 1239 | if (error != 0) { | ||
| 1240 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1241 | "%s: Unable to register rate control " | ||
| 1242 | "algorithm:%d\n", __func__, error); | ||
| 1243 | ath_rate_control_unregister(); | ||
| 1244 | goto bad; | ||
| 1245 | } | ||
| 1246 | |||
| 1247 | error = ieee80211_register_hw(hw); | ||
| 1248 | if (error != 0) { | ||
| 1249 | ath_rate_control_unregister(); | ||
| 1250 | goto bad; | ||
| 1251 | } | ||
| 1252 | |||
| 1253 | /* initialize tx/rx engine */ | ||
| 1254 | |||
| 1255 | error = ath_tx_init(sc, ATH_TXBUF); | ||
| 1256 | if (error != 0) | ||
| 1257 | goto bad1; | ||
| 1258 | |||
| 1259 | error = ath_rx_init(sc, ATH_RXBUF); | ||
| 1260 | if (error != 0) | ||
| 1261 | goto bad1; | ||
| 1262 | |||
| 1263 | return 0; | ||
| 1264 | bad1: | ||
| 1265 | ath_detach(sc); | ||
| 1266 | bad: | ||
| 1267 | return error; | ||
| 1268 | } | ||
| 1269 | |||
| 1270 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | ||
| 1271 | { | ||
| 1272 | void __iomem *mem; | ||
| 1273 | struct ath_softc *sc; | ||
| 1274 | struct ieee80211_hw *hw; | ||
| 1275 | const char *athname; | ||
| 1276 | u8 csz; | ||
| 1277 | u32 val; | ||
| 1278 | int ret = 0; | ||
| 1279 | |||
| 1280 | if (pci_enable_device(pdev)) | ||
| 1281 | return -EIO; | ||
| 1282 | |||
| 1283 | /* XXX 32-bit addressing only */ | ||
| 1284 | if (pci_set_dma_mask(pdev, 0xffffffff)) { | ||
| 1285 | printk(KERN_ERR "ath_pci: 32-bit DMA not available\n"); | ||
| 1286 | ret = -ENODEV; | ||
| 1287 | goto bad; | ||
| 1288 | } | ||
| 1289 | |||
| 1290 | /* | ||
| 1291 | * Cache line size is used to size and align various | ||
| 1292 | * structures used to communicate with the hardware. | ||
| 1293 | */ | ||
| 1294 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | ||
| 1295 | if (csz == 0) { | ||
| 1296 | /* | ||
| 1297 | * Linux 2.4.18 (at least) writes the cache line size | ||
| 1298 | * register as a 16-bit wide register which is wrong. | ||
| 1299 | * We must have this setup properly for rx buffer | ||
| 1300 | * DMA to work so force a reasonable value here if it | ||
| 1301 | * comes up zero. | ||
| 1302 | */ | ||
| 1303 | csz = L1_CACHE_BYTES / sizeof(u32); | ||
| 1304 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | ||
| 1305 | } | ||
| 1306 | /* | ||
| 1307 | * The default setting of latency timer yields poor results, | ||
| 1308 | * set it to the value used by other systems. It may be worth | ||
| 1309 | * tweaking this setting more. | ||
| 1310 | */ | ||
| 1311 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | ||
| 1312 | |||
| 1313 | pci_set_master(pdev); | ||
| 1314 | |||
| 1315 | /* | ||
| 1316 | * Disable the RETRY_TIMEOUT register (0x41) to keep | ||
| 1317 | * PCI Tx retries from interfering with C3 CPU state. | ||
| 1318 | */ | ||
| 1319 | pci_read_config_dword(pdev, 0x40, &val); | ||
| 1320 | if ((val & 0x0000ff00) != 0) | ||
| 1321 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | ||
| 1322 | |||
| 1323 | ret = pci_request_region(pdev, 0, "ath9k"); | ||
| 1324 | if (ret) { | ||
| 1325 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | ||
| 1326 | ret = -ENODEV; | ||
| 1327 | goto bad; | ||
| 1328 | } | ||
| 1329 | |||
| 1330 | mem = pci_iomap(pdev, 0, 0); | ||
| 1331 | if (!mem) { | ||
| 1332 | printk(KERN_ERR "PCI memory map error\n") ; | ||
| 1333 | ret = -EIO; | ||
| 1334 | goto bad1; | ||
| 1335 | } | ||
| 1336 | |||
| 1337 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); | ||
| 1338 | if (hw == NULL) { | ||
| 1339 | printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n"); | ||
| 1340 | goto bad2; | ||
| 1341 | } | ||
| 1342 | |||
| 1343 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | ||
| 1344 | IEEE80211_HW_NOISE_DBM; | ||
| 1345 | |||
| 1346 | SET_IEEE80211_DEV(hw, &pdev->dev); | ||
| 1347 | pci_set_drvdata(pdev, hw); | ||
| 1348 | |||
| 1349 | sc = hw->priv; | ||
| 1350 | sc->hw = hw; | ||
| 1351 | sc->pdev = pdev; | ||
| 1352 | sc->mem = mem; | ||
| 1353 | |||
| 1354 | if (ath_attach(id->device, sc) != 0) { | ||
| 1355 | ret = -ENODEV; | ||
| 1356 | goto bad3; | ||
| 1357 | } | ||
| 1358 | |||
| 1359 | /* setup interrupt service routine */ | ||
| 1360 | |||
| 1361 | if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) { | ||
| 1362 | printk(KERN_ERR "%s: request_irq failed\n", | ||
| 1363 | wiphy_name(hw->wiphy)); | ||
| 1364 | ret = -EIO; | ||
| 1365 | goto bad4; | ||
| 1366 | } | ||
| 1367 | |||
| 1368 | athname = ath9k_hw_probe(id->vendor, id->device); | ||
| 1369 | |||
| 1370 | printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n", | ||
| 1371 | wiphy_name(hw->wiphy), | ||
| 1372 | athname ? athname : "Atheros ???", | ||
| 1373 | (unsigned long)mem, pdev->irq); | ||
| 1374 | |||
| 1375 | return 0; | ||
| 1376 | bad4: | ||
| 1377 | ath_detach(sc); | ||
| 1378 | bad3: | ||
| 1379 | ieee80211_free_hw(hw); | ||
| 1380 | bad2: | ||
| 1381 | pci_iounmap(pdev, mem); | ||
| 1382 | bad1: | ||
| 1383 | pci_release_region(pdev, 0); | ||
| 1384 | bad: | ||
| 1385 | pci_disable_device(pdev); | ||
| 1386 | return ret; | ||
| 1387 | } | ||
| 1388 | |||
| 1389 | static void ath_pci_remove(struct pci_dev *pdev) | ||
| 1390 | { | ||
| 1391 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | ||
| 1392 | struct ath_softc *sc = hw->priv; | ||
| 1393 | |||
| 1394 | if (pdev->irq) | ||
| 1395 | free_irq(pdev->irq, sc); | ||
| 1396 | ath_detach(sc); | ||
| 1397 | pci_iounmap(pdev, sc->mem); | ||
| 1398 | pci_release_region(pdev, 0); | ||
| 1399 | pci_disable_device(pdev); | ||
| 1400 | ieee80211_free_hw(hw); | ||
| 1401 | } | ||
| 1402 | |||
| 1403 | #ifdef CONFIG_PM | ||
| 1404 | |||
| 1405 | static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) | ||
| 1406 | { | ||
| 1407 | pci_save_state(pdev); | ||
| 1408 | pci_disable_device(pdev); | ||
| 1409 | pci_set_power_state(pdev, 3); | ||
| 1410 | |||
| 1411 | return 0; | ||
| 1412 | } | ||
| 1413 | |||
| 1414 | static int ath_pci_resume(struct pci_dev *pdev) | ||
| 1415 | { | ||
| 1416 | u32 val; | ||
| 1417 | int err; | ||
| 1418 | |||
| 1419 | err = pci_enable_device(pdev); | ||
| 1420 | if (err) | ||
| 1421 | return err; | ||
| 1422 | pci_restore_state(pdev); | ||
| 1423 | /* | ||
| 1424 | * Suspend/Resume resets the PCI configuration space, so we have to | ||
| 1425 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | ||
| 1426 | * PCI Tx retries from interfering with C3 CPU state | ||
| 1427 | */ | ||
| 1428 | pci_read_config_dword(pdev, 0x40, &val); | ||
| 1429 | if ((val & 0x0000ff00) != 0) | ||
| 1430 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | ||
| 1431 | |||
| 1432 | return 0; | ||
| 1433 | } | ||
| 1434 | |||
| 1435 | #endif /* CONFIG_PM */ | ||
| 1436 | |||
| 1437 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | ||
| 1438 | |||
| 1439 | static struct pci_driver ath_pci_driver = { | ||
| 1440 | .name = "ath9k", | ||
| 1441 | .id_table = ath_pci_id_table, | ||
| 1442 | .probe = ath_pci_probe, | ||
| 1443 | .remove = ath_pci_remove, | ||
| 1444 | #ifdef CONFIG_PM | ||
| 1445 | .suspend = ath_pci_suspend, | ||
| 1446 | .resume = ath_pci_resume, | ||
| 1447 | #endif /* CONFIG_PM */ | ||
| 1448 | }; | ||
| 1449 | |||
| 1450 | static int __init init_ath_pci(void) | ||
| 1451 | { | ||
| 1452 | printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION); | ||
| 1453 | |||
| 1454 | if (pci_register_driver(&ath_pci_driver) < 0) { | ||
| 1455 | printk(KERN_ERR | ||
| 1456 | "ath_pci: No devices found, driver not installed.\n"); | ||
| 1457 | pci_unregister_driver(&ath_pci_driver); | ||
| 1458 | return -ENODEV; | ||
| 1459 | } | ||
| 1460 | |||
| 1461 | return 0; | ||
| 1462 | } | ||
| 1463 | module_init(init_ath_pci); | ||
| 1464 | |||
| 1465 | static void __exit exit_ath_pci(void) | ||
| 1466 | { | ||
| 1467 | pci_unregister_driver(&ath_pci_driver); | ||
| 1468 | printk(KERN_INFO "%s: driver unloaded\n", dev_info); | ||
| 1469 | } | ||
| 1470 | module_exit(exit_ath_pci); | ||
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c new file mode 100644 index 000000000000..eb9121fdfd38 --- /dev/null +++ b/drivers/net/wireless/ath9k/phy.c | |||
| @@ -0,0 +1,436 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "core.h" | ||
| 18 | #include "hw.h" | ||
| 19 | #include "reg.h" | ||
| 20 | #include "phy.h" | ||
| 21 | |||
| 22 | void | ||
| 23 | ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, | ||
| 24 | int regWrites) | ||
| 25 | { | ||
| 26 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 27 | |||
| 28 | REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites); | ||
| 29 | } | ||
| 30 | |||
| 31 | bool | ||
| 32 | ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) | ||
| 33 | { | ||
| 34 | u32 channelSel = 0; | ||
| 35 | u32 bModeSynth = 0; | ||
| 36 | u32 aModeRefSel = 0; | ||
| 37 | u32 reg32 = 0; | ||
| 38 | u16 freq; | ||
| 39 | struct chan_centers centers; | ||
| 40 | |||
| 41 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 42 | freq = centers.synth_center; | ||
| 43 | |||
| 44 | if (freq < 4800) { | ||
| 45 | u32 txctl; | ||
| 46 | |||
| 47 | if (((freq - 2192) % 5) == 0) { | ||
| 48 | channelSel = ((freq - 672) * 2 - 3040) / 10; | ||
| 49 | bModeSynth = 0; | ||
| 50 | } else if (((freq - 2224) % 5) == 0) { | ||
| 51 | channelSel = ((freq - 704) * 2 - 3040) / 10; | ||
| 52 | bModeSynth = 1; | ||
| 53 | } else { | ||
| 54 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 55 | "%s: invalid channel %u MHz\n", __func__, | ||
| 56 | freq); | ||
| 57 | return false; | ||
| 58 | } | ||
| 59 | |||
| 60 | channelSel = (channelSel << 2) & 0xff; | ||
| 61 | channelSel = ath9k_hw_reverse_bits(channelSel, 8); | ||
| 62 | |||
| 63 | txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); | ||
| 64 | if (freq == 2484) { | ||
| 65 | |||
| 66 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | ||
| 67 | txctl | AR_PHY_CCK_TX_CTRL_JAPAN); | ||
| 68 | } else { | ||
| 69 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | ||
| 70 | txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); | ||
| 71 | } | ||
| 72 | |||
| 73 | } else if ((freq % 20) == 0 && freq >= 5120) { | ||
| 74 | channelSel = | ||
| 75 | ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); | ||
| 76 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | ||
| 77 | } else if ((freq % 10) == 0) { | ||
| 78 | channelSel = | ||
| 79 | ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); | ||
| 80 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) | ||
| 81 | aModeRefSel = ath9k_hw_reverse_bits(2, 2); | ||
| 82 | else | ||
| 83 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | ||
| 84 | } else if ((freq % 5) == 0) { | ||
| 85 | channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); | ||
| 86 | aModeRefSel = ath9k_hw_reverse_bits(1, 2); | ||
| 87 | } else { | ||
| 88 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, | ||
| 89 | "%s: invalid channel %u MHz\n", __func__, freq); | ||
| 90 | return false; | ||
| 91 | } | ||
| 92 | |||
| 93 | reg32 = | ||
| 94 | (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | | ||
| 95 | (1 << 5) | 0x1; | ||
| 96 | |||
| 97 | REG_WRITE(ah, AR_PHY(0x37), reg32); | ||
| 98 | |||
| 99 | ah->ah_curchan = chan; | ||
| 100 | |||
| 101 | AH5416(ah)->ah_curchanRadIndex = -1; | ||
| 102 | |||
| 103 | return true; | ||
| 104 | } | ||
| 105 | |||
| 106 | bool | ||
| 107 | ath9k_hw_ar9280_set_channel(struct ath_hal *ah, | ||
| 108 | struct ath9k_channel *chan) | ||
| 109 | { | ||
| 110 | u16 bMode, fracMode, aModeRefSel = 0; | ||
| 111 | u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; | ||
| 112 | struct chan_centers centers; | ||
| 113 | u32 refDivA = 24; | ||
| 114 | |||
| 115 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
| 116 | freq = centers.synth_center; | ||
| 117 | |||
| 118 | reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); | ||
| 119 | reg32 &= 0xc0000000; | ||
| 120 | |||
| 121 | if (freq < 4800) { | ||
| 122 | u32 txctl; | ||
| 123 | |||
| 124 | bMode = 1; | ||
| 125 | fracMode = 1; | ||
| 126 | aModeRefSel = 0; | ||
| 127 | channelSel = (freq * 0x10000) / 15; | ||
| 128 | |||
| 129 | txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); | ||
| 130 | if (freq == 2484) { | ||
| 131 | |||
| 132 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | ||
| 133 | txctl | AR_PHY_CCK_TX_CTRL_JAPAN); | ||
| 134 | } else { | ||
| 135 | REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, | ||
| 136 | txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); | ||
| 137 | } | ||
| 138 | } else { | ||
| 139 | bMode = 0; | ||
| 140 | fracMode = 0; | ||
| 141 | |||
| 142 | if ((freq % 20) == 0) { | ||
| 143 | aModeRefSel = 3; | ||
| 144 | } else if ((freq % 10) == 0) { | ||
| 145 | aModeRefSel = 2; | ||
| 146 | } else { | ||
| 147 | aModeRefSel = 0; | ||
| 148 | |||
| 149 | fracMode = 1; | ||
| 150 | refDivA = 1; | ||
| 151 | channelSel = (freq * 0x8000) / 15; | ||
| 152 | |||
| 153 | REG_RMW_FIELD(ah, AR_AN_SYNTH9, | ||
| 154 | AR_AN_SYNTH9_REFDIVA, refDivA); | ||
| 155 | } | ||
| 156 | if (!fracMode) { | ||
| 157 | ndiv = (freq * (refDivA >> aModeRefSel)) / 60; | ||
| 158 | channelSel = ndiv & 0x1ff; | ||
| 159 | channelFrac = (ndiv & 0xfffffe00) * 2; | ||
| 160 | channelSel = (channelSel << 17) | channelFrac; | ||
| 161 | } | ||
| 162 | } | ||
| 163 | |||
| 164 | reg32 = reg32 | | ||
| 165 | (bMode << 29) | | ||
| 166 | (fracMode << 28) | (aModeRefSel << 26) | (channelSel); | ||
| 167 | |||
| 168 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | ||
| 169 | |||
| 170 | ah->ah_curchan = chan; | ||
| 171 | |||
| 172 | AH5416(ah)->ah_curchanRadIndex = -1; | ||
| 173 | |||
| 174 | return true; | ||
| 175 | } | ||
| 176 | |||
| 177 | static void | ||
| 178 | ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, | ||
| 179 | u32 numBits, u32 firstBit, | ||
| 180 | u32 column) | ||
| 181 | { | ||
| 182 | u32 tmp32, mask, arrayEntry, lastBit; | ||
| 183 | int32_t bitPosition, bitsLeft; | ||
| 184 | |||
| 185 | tmp32 = ath9k_hw_reverse_bits(reg32, numBits); | ||
| 186 | arrayEntry = (firstBit - 1) / 8; | ||
| 187 | bitPosition = (firstBit - 1) % 8; | ||
| 188 | bitsLeft = numBits; | ||
| 189 | while (bitsLeft > 0) { | ||
| 190 | lastBit = (bitPosition + bitsLeft > 8) ? | ||
| 191 | 8 : bitPosition + bitsLeft; | ||
| 192 | mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << | ||
| 193 | (column * 8); | ||
| 194 | rfBuf[arrayEntry] &= ~mask; | ||
| 195 | rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << | ||
| 196 | (column * 8)) & mask; | ||
| 197 | bitsLeft -= 8 - bitPosition; | ||
| 198 | tmp32 = tmp32 >> (8 - bitPosition); | ||
| 199 | bitPosition = 0; | ||
| 200 | arrayEntry++; | ||
| 201 | } | ||
| 202 | } | ||
| 203 | |||
| 204 | bool | ||
| 205 | ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, | ||
| 206 | u16 modesIndex) | ||
| 207 | { | ||
| 208 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 209 | |||
| 210 | u32 eepMinorRev; | ||
| 211 | u32 ob5GHz = 0, db5GHz = 0; | ||
| 212 | u32 ob2GHz = 0, db2GHz = 0; | ||
| 213 | int regWrites = 0; | ||
| 214 | |||
| 215 | if (AR_SREV_9280_10_OR_LATER(ah)) | ||
| 216 | return true; | ||
| 217 | |||
| 218 | eepMinorRev = ath9k_hw_get_eeprom(ahp, EEP_MINOR_REV); | ||
| 219 | |||
| 220 | RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1); | ||
| 221 | |||
| 222 | RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1); | ||
| 223 | |||
| 224 | RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1); | ||
| 225 | |||
| 226 | RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3, | ||
| 227 | modesIndex); | ||
| 228 | { | ||
| 229 | int i; | ||
| 230 | for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) { | ||
| 231 | ahp->ah_analogBank6Data[i] = | ||
| 232 | INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex); | ||
| 233 | } | ||
| 234 | } | ||
| 235 | |||
| 236 | if (eepMinorRev >= 2) { | ||
| 237 | if (IS_CHAN_2GHZ(chan)) { | ||
| 238 | ob2GHz = ath9k_hw_get_eeprom(ahp, EEP_OB_2); | ||
| 239 | db2GHz = ath9k_hw_get_eeprom(ahp, EEP_DB_2); | ||
| 240 | ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, | ||
| 241 | ob2GHz, 3, 197, 0); | ||
| 242 | ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, | ||
| 243 | db2GHz, 3, 194, 0); | ||
| 244 | } else { | ||
| 245 | ob5GHz = ath9k_hw_get_eeprom(ahp, EEP_OB_5); | ||
| 246 | db5GHz = ath9k_hw_get_eeprom(ahp, EEP_DB_5); | ||
| 247 | ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, | ||
| 248 | ob5GHz, 3, 203, 0); | ||
| 249 | ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, | ||
| 250 | db5GHz, 3, 200, 0); | ||
| 251 | } | ||
| 252 | } | ||
| 253 | |||
| 254 | RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1); | ||
| 255 | |||
| 256 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data, | ||
| 257 | regWrites); | ||
| 258 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data, | ||
| 259 | regWrites); | ||
| 260 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data, | ||
| 261 | regWrites); | ||
| 262 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data, | ||
| 263 | regWrites); | ||
| 264 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data, | ||
| 265 | regWrites); | ||
| 266 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data, | ||
| 267 | regWrites); | ||
| 268 | |||
| 269 | return true; | ||
| 270 | } | ||
| 271 | |||
| 272 | void | ||
| 273 | ath9k_hw_rfdetach(struct ath_hal *ah) | ||
| 274 | { | ||
| 275 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 276 | |||
| 277 | if (ahp->ah_analogBank0Data != NULL) { | ||
| 278 | kfree(ahp->ah_analogBank0Data); | ||
| 279 | ahp->ah_analogBank0Data = NULL; | ||
| 280 | } | ||
| 281 | if (ahp->ah_analogBank1Data != NULL) { | ||
| 282 | kfree(ahp->ah_analogBank1Data); | ||
| 283 | ahp->ah_analogBank1Data = NULL; | ||
| 284 | } | ||
| 285 | if (ahp->ah_analogBank2Data != NULL) { | ||
| 286 | kfree(ahp->ah_analogBank2Data); | ||
| 287 | ahp->ah_analogBank2Data = NULL; | ||
| 288 | } | ||
| 289 | if (ahp->ah_analogBank3Data != NULL) { | ||
| 290 | kfree(ahp->ah_analogBank3Data); | ||
| 291 | ahp->ah_analogBank3Data = NULL; | ||
| 292 | } | ||
| 293 | if (ahp->ah_analogBank6Data != NULL) { | ||
| 294 | kfree(ahp->ah_analogBank6Data); | ||
| 295 | ahp->ah_analogBank6Data = NULL; | ||
| 296 | } | ||
| 297 | if (ahp->ah_analogBank6TPCData != NULL) { | ||
| 298 | kfree(ahp->ah_analogBank6TPCData); | ||
| 299 | ahp->ah_analogBank6TPCData = NULL; | ||
| 300 | } | ||
| 301 | if (ahp->ah_analogBank7Data != NULL) { | ||
| 302 | kfree(ahp->ah_analogBank7Data); | ||
| 303 | ahp->ah_analogBank7Data = NULL; | ||
| 304 | } | ||
| 305 | if (ahp->ah_addac5416_21 != NULL) { | ||
| 306 | kfree(ahp->ah_addac5416_21); | ||
| 307 | ahp->ah_addac5416_21 = NULL; | ||
| 308 | } | ||
| 309 | if (ahp->ah_bank6Temp != NULL) { | ||
| 310 | kfree(ahp->ah_bank6Temp); | ||
| 311 | ahp->ah_bank6Temp = NULL; | ||
| 312 | } | ||
| 313 | } | ||
| 314 | |||
| 315 | bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) | ||
| 316 | { | ||
| 317 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 318 | |||
| 319 | if (!AR_SREV_9280_10_OR_LATER(ah)) { | ||
| 320 | |||
| 321 | ahp->ah_analogBank0Data = | ||
| 322 | kzalloc((sizeof(u32) * | ||
| 323 | ahp->ah_iniBank0.ia_rows), GFP_KERNEL); | ||
| 324 | ahp->ah_analogBank1Data = | ||
| 325 | kzalloc((sizeof(u32) * | ||
| 326 | ahp->ah_iniBank1.ia_rows), GFP_KERNEL); | ||
| 327 | ahp->ah_analogBank2Data = | ||
| 328 | kzalloc((sizeof(u32) * | ||
| 329 | ahp->ah_iniBank2.ia_rows), GFP_KERNEL); | ||
| 330 | ahp->ah_analogBank3Data = | ||
| 331 | kzalloc((sizeof(u32) * | ||
| 332 | ahp->ah_iniBank3.ia_rows), GFP_KERNEL); | ||
| 333 | ahp->ah_analogBank6Data = | ||
| 334 | kzalloc((sizeof(u32) * | ||
| 335 | ahp->ah_iniBank6.ia_rows), GFP_KERNEL); | ||
| 336 | ahp->ah_analogBank6TPCData = | ||
| 337 | kzalloc((sizeof(u32) * | ||
| 338 | ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL); | ||
| 339 | ahp->ah_analogBank7Data = | ||
| 340 | kzalloc((sizeof(u32) * | ||
| 341 | ahp->ah_iniBank7.ia_rows), GFP_KERNEL); | ||
| 342 | |||
| 343 | if (ahp->ah_analogBank0Data == NULL | ||
| 344 | || ahp->ah_analogBank1Data == NULL | ||
| 345 | || ahp->ah_analogBank2Data == NULL | ||
| 346 | || ahp->ah_analogBank3Data == NULL | ||
| 347 | || ahp->ah_analogBank6Data == NULL | ||
| 348 | || ahp->ah_analogBank6TPCData == NULL | ||
| 349 | || ahp->ah_analogBank7Data == NULL) { | ||
| 350 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | ||
| 351 | "%s: cannot allocate RF banks\n", | ||
| 352 | __func__); | ||
| 353 | *status = -ENOMEM; | ||
| 354 | return false; | ||
| 355 | } | ||
| 356 | |||
| 357 | ahp->ah_addac5416_21 = | ||
| 358 | kzalloc((sizeof(u32) * | ||
| 359 | ahp->ah_iniAddac.ia_rows * | ||
| 360 | ahp->ah_iniAddac.ia_columns), GFP_KERNEL); | ||
| 361 | if (ahp->ah_addac5416_21 == NULL) { | ||
| 362 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | ||
| 363 | "%s: cannot allocate ah_addac5416_21\n", | ||
| 364 | __func__); | ||
| 365 | *status = -ENOMEM; | ||
| 366 | return false; | ||
| 367 | } | ||
| 368 | |||
| 369 | ahp->ah_bank6Temp = | ||
| 370 | kzalloc((sizeof(u32) * | ||
| 371 | ahp->ah_iniBank6.ia_rows), GFP_KERNEL); | ||
| 372 | if (ahp->ah_bank6Temp == NULL) { | ||
| 373 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | ||
| 374 | "%s: cannot allocate ah_bank6Temp\n", | ||
| 375 | __func__); | ||
| 376 | *status = -ENOMEM; | ||
| 377 | return false; | ||
| 378 | } | ||
| 379 | } | ||
| 380 | |||
| 381 | return true; | ||
| 382 | } | ||
| 383 | |||
| 384 | void | ||
| 385 | ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) | ||
| 386 | { | ||
| 387 | int i, regWrites = 0; | ||
| 388 | struct ath_hal_5416 *ahp = AH5416(ah); | ||
| 389 | u32 bank6SelMask; | ||
| 390 | u32 *bank6Temp = ahp->ah_bank6Temp; | ||
| 391 | |||
| 392 | switch (ahp->ah_diversityControl) { | ||
| 393 | case ATH9K_ANT_FIXED_A: | ||
| 394 | bank6SelMask = | ||
| 395 | (ahp-> | ||
| 396 | ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : | ||
| 397 | REDUCE_CHAIN_1; | ||
| 398 | break; | ||
| 399 | case ATH9K_ANT_FIXED_B: | ||
| 400 | bank6SelMask = | ||
| 401 | (ahp-> | ||
| 402 | ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : | ||
| 403 | REDUCE_CHAIN_0; | ||
| 404 | break; | ||
| 405 | case ATH9K_ANT_VARIABLE: | ||
| 406 | return; | ||
| 407 | break; | ||
| 408 | default: | ||
| 409 | return; | ||
| 410 | break; | ||
| 411 | } | ||
| 412 | |||
| 413 | for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++) | ||
| 414 | bank6Temp[i] = ahp->ah_analogBank6Data[i]; | ||
| 415 | |||
| 416 | REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); | ||
| 417 | |||
| 418 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0); | ||
| 419 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0); | ||
| 420 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0); | ||
| 421 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0); | ||
| 422 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0); | ||
| 423 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0); | ||
| 424 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0); | ||
| 425 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); | ||
| 426 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); | ||
| 427 | |||
| 428 | REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites); | ||
| 429 | |||
| 430 | REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); | ||
| 431 | #ifdef ALTER_SWITCH | ||
| 432 | REG_WRITE(ah, PHY_SWITCH_CHAIN_0, | ||
| 433 | (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38) | ||
| 434 | | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38)); | ||
| 435 | #endif | ||
| 436 | } | ||
diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h new file mode 100644 index 000000000000..0cd399a5344a --- /dev/null +++ b/drivers/net/wireless/ath9k/phy.h | |||
| @@ -0,0 +1,543 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef PHY_H | ||
| 18 | #define PHY_H | ||
| 19 | |||
| 20 | bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah, | ||
| 21 | struct ath9k_channel | ||
| 22 | *chan); | ||
| 23 | bool ath9k_hw_set_channel(struct ath_hal *ah, | ||
| 24 | struct ath9k_channel *chan); | ||
| 25 | void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, | ||
| 26 | u32 freqIndex, int regWrites); | ||
| 27 | bool ath9k_hw_set_rf_regs(struct ath_hal *ah, | ||
| 28 | struct ath9k_channel *chan, | ||
| 29 | u16 modesIndex); | ||
| 30 | void ath9k_hw_decrease_chain_power(struct ath_hal *ah, | ||
| 31 | struct ath9k_channel *chan); | ||
| 32 | bool ath9k_hw_init_rf(struct ath_hal *ah, | ||
| 33 | int *status); | ||
| 34 | |||
| 35 | #define AR_PHY_BASE 0x9800 | ||
| 36 | #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) | ||
| 37 | |||
| 38 | #define AR_PHY_TEST 0x9800 | ||
| 39 | #define PHY_AGC_CLR 0x10000000 | ||
| 40 | #define RFSILENT_BB 0x00002000 | ||
| 41 | |||
| 42 | #define AR_PHY_TURBO 0x9804 | ||
| 43 | #define AR_PHY_FC_TURBO_MODE 0x00000001 | ||
| 44 | #define AR_PHY_FC_TURBO_SHORT 0x00000002 | ||
| 45 | #define AR_PHY_FC_DYN2040_EN 0x00000004 | ||
| 46 | #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 | ||
| 47 | #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 | ||
| 48 | #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 | ||
| 49 | #define AR_PHY_FC_HT_EN 0x00000040 | ||
| 50 | #define AR_PHY_FC_SHORT_GI_40 0x00000080 | ||
| 51 | #define AR_PHY_FC_WALSH 0x00000100 | ||
| 52 | #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 | ||
| 53 | |||
| 54 | #define AR_PHY_TIMING2 0x9810 | ||
| 55 | #define AR_PHY_TIMING3 0x9814 | ||
| 56 | #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 | ||
| 57 | #define AR_PHY_TIMING3_DSC_MAN_S 17 | ||
| 58 | #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 | ||
| 59 | #define AR_PHY_TIMING3_DSC_EXP_S 13 | ||
| 60 | |||
| 61 | #define AR_PHY_CHIP_ID 0x9818 | ||
| 62 | #define AR_PHY_CHIP_ID_REV_0 0x80 | ||
| 63 | #define AR_PHY_CHIP_ID_REV_1 0x81 | ||
| 64 | #define AR_PHY_CHIP_ID_9160_REV_0 0xb0 | ||
| 65 | |||
| 66 | #define AR_PHY_ACTIVE 0x981C | ||
| 67 | #define AR_PHY_ACTIVE_EN 0x00000001 | ||
| 68 | #define AR_PHY_ACTIVE_DIS 0x00000000 | ||
| 69 | |||
| 70 | #define AR_PHY_RF_CTL2 0x9824 | ||
| 71 | #define AR_PHY_TX_END_DATA_START 0x000000FF | ||
| 72 | #define AR_PHY_TX_END_DATA_START_S 0 | ||
| 73 | #define AR_PHY_TX_END_PA_ON 0x0000FF00 | ||
| 74 | #define AR_PHY_TX_END_PA_ON_S 8 | ||
| 75 | |||
| 76 | #define AR_PHY_RF_CTL3 0x9828 | ||
| 77 | #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 | ||
| 78 | #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 | ||
| 79 | |||
| 80 | #define AR_PHY_ADC_CTL 0x982C | ||
| 81 | #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 | ||
| 82 | #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 | ||
| 83 | #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 | ||
| 84 | #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 | ||
| 85 | #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 | ||
| 86 | #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 | ||
| 87 | #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 | ||
| 88 | |||
| 89 | #define AR_PHY_ADC_SERIAL_CTL 0x9830 | ||
| 90 | #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 | ||
| 91 | #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 | ||
| 92 | |||
| 93 | #define AR_PHY_RF_CTL4 0x9834 | ||
| 94 | #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 | ||
| 95 | #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 | ||
| 96 | #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 | ||
| 97 | #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 | ||
| 98 | #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 | ||
| 99 | #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 | ||
| 100 | #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF | ||
| 101 | #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 | ||
| 102 | |||
| 103 | #define AR_PHY_SETTLING 0x9844 | ||
| 104 | #define AR_PHY_SETTLING_SWITCH 0x00003F80 | ||
| 105 | #define AR_PHY_SETTLING_SWITCH_S 7 | ||
| 106 | |||
| 107 | #define AR_PHY_RXGAIN 0x9848 | ||
| 108 | #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 | ||
| 109 | #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 | ||
| 110 | #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 | ||
| 111 | #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 | ||
| 112 | #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 | ||
| 113 | #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 | ||
| 114 | #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 | ||
| 115 | #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 | ||
| 116 | |||
| 117 | #define AR_PHY_DESIRED_SZ 0x9850 | ||
| 118 | #define AR_PHY_DESIRED_SZ_ADC 0x000000FF | ||
| 119 | #define AR_PHY_DESIRED_SZ_ADC_S 0 | ||
| 120 | #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 | ||
| 121 | #define AR_PHY_DESIRED_SZ_PGA_S 8 | ||
| 122 | #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 | ||
| 123 | #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 | ||
| 124 | |||
| 125 | #define AR_PHY_FIND_SIG 0x9858 | ||
| 126 | #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 | ||
| 127 | #define AR_PHY_FIND_SIG_FIRSTEP_S 12 | ||
| 128 | #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 | ||
| 129 | #define AR_PHY_FIND_SIG_FIRPWR_S 18 | ||
| 130 | |||
| 131 | #define AR_PHY_AGC_CTL1 0x985C | ||
| 132 | #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 | ||
| 133 | #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 | ||
| 134 | #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 | ||
| 135 | #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 | ||
| 136 | |||
| 137 | #define AR_PHY_AGC_CONTROL 0x9860 | ||
| 138 | #define AR_PHY_AGC_CONTROL_CAL 0x00000001 | ||
| 139 | #define AR_PHY_AGC_CONTROL_NF 0x00000002 | ||
| 140 | #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 | ||
| 141 | #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 | ||
| 142 | #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 | ||
| 143 | |||
| 144 | #define AR_PHY_CCA 0x9864 | ||
| 145 | #define AR_PHY_MINCCA_PWR 0x0FF80000 | ||
| 146 | #define AR_PHY_MINCCA_PWR_S 19 | ||
| 147 | #define AR_PHY_CCA_THRESH62 0x0007F000 | ||
| 148 | #define AR_PHY_CCA_THRESH62_S 12 | ||
| 149 | #define AR9280_PHY_MINCCA_PWR 0x1FF00000 | ||
| 150 | #define AR9280_PHY_MINCCA_PWR_S 20 | ||
| 151 | #define AR9280_PHY_CCA_THRESH62 0x000FF000 | ||
| 152 | #define AR9280_PHY_CCA_THRESH62_S 12 | ||
| 153 | |||
| 154 | #define AR_PHY_SFCORR_LOW 0x986C | ||
| 155 | #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 | ||
| 156 | #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 | ||
| 157 | #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 | ||
| 158 | #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 | ||
| 159 | #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 | ||
| 160 | #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 | ||
| 161 | #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 | ||
| 162 | |||
| 163 | #define AR_PHY_SFCORR 0x9868 | ||
| 164 | #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F | ||
| 165 | #define AR_PHY_SFCORR_M2COUNT_THR_S 0 | ||
| 166 | #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 | ||
| 167 | #define AR_PHY_SFCORR_M1_THRESH_S 17 | ||
| 168 | #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 | ||
| 169 | #define AR_PHY_SFCORR_M2_THRESH_S 24 | ||
| 170 | |||
| 171 | #define AR_PHY_SLEEP_CTR_CONTROL 0x9870 | ||
| 172 | #define AR_PHY_SLEEP_CTR_LIMIT 0x9874 | ||
| 173 | #define AR_PHY_SYNTH_CONTROL 0x9874 | ||
| 174 | #define AR_PHY_SLEEP_SCAL 0x9878 | ||
| 175 | |||
| 176 | #define AR_PHY_PLL_CTL 0x987c | ||
| 177 | #define AR_PHY_PLL_CTL_40 0xaa | ||
| 178 | #define AR_PHY_PLL_CTL_40_5413 0x04 | ||
| 179 | #define AR_PHY_PLL_CTL_44 0xab | ||
| 180 | #define AR_PHY_PLL_CTL_44_2133 0xeb | ||
| 181 | #define AR_PHY_PLL_CTL_40_2133 0xea | ||
| 182 | |||
| 183 | #define AR_PHY_RX_DELAY 0x9914 | ||
| 184 | #define AR_PHY_SEARCH_START_DELAY 0x9918 | ||
| 185 | #define AR_PHY_RX_DELAY_DELAY 0x00003FFF | ||
| 186 | |||
| 187 | #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) | ||
| 188 | #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F | ||
| 189 | #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 | ||
| 190 | #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 | ||
| 191 | #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 | ||
| 192 | #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 | ||
| 193 | #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 | ||
| 194 | #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 | ||
| 195 | #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 | ||
| 196 | |||
| 197 | #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 | ||
| 198 | #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 | ||
| 199 | #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 | ||
| 200 | #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 | ||
| 201 | |||
| 202 | #define AR_PHY_TIMING5 0x9924 | ||
| 203 | #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE | ||
| 204 | #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 | ||
| 205 | |||
| 206 | #define AR_PHY_POWER_TX_RATE1 0x9934 | ||
| 207 | #define AR_PHY_POWER_TX_RATE2 0x9938 | ||
| 208 | #define AR_PHY_POWER_TX_RATE_MAX 0x993c | ||
| 209 | #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 | ||
| 210 | |||
| 211 | #define AR_PHY_FRAME_CTL 0x9944 | ||
| 212 | #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 | ||
| 213 | #define AR_PHY_FRAME_CTL_TX_CLIP_S 3 | ||
| 214 | |||
| 215 | #define AR_PHY_TXPWRADJ 0x994C | ||
| 216 | #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 | ||
| 217 | #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 | ||
| 218 | #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 | ||
| 219 | #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 | ||
| 220 | |||
| 221 | #define AR_PHY_RADAR_EXT 0x9940 | ||
| 222 | #define AR_PHY_RADAR_EXT_ENA 0x00004000 | ||
| 223 | |||
| 224 | #define AR_PHY_RADAR_0 0x9954 | ||
| 225 | #define AR_PHY_RADAR_0_ENA 0x00000001 | ||
| 226 | #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 | ||
| 227 | #define AR_PHY_RADAR_0_INBAND 0x0000003e | ||
| 228 | #define AR_PHY_RADAR_0_INBAND_S 1 | ||
| 229 | #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 | ||
| 230 | #define AR_PHY_RADAR_0_PRSSI_S 6 | ||
| 231 | #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 | ||
| 232 | #define AR_PHY_RADAR_0_HEIGHT_S 12 | ||
| 233 | #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 | ||
| 234 | #define AR_PHY_RADAR_0_RRSSI_S 18 | ||
| 235 | #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 | ||
| 236 | #define AR_PHY_RADAR_0_FIRPWR_S 24 | ||
| 237 | |||
| 238 | #define AR_PHY_RADAR_1 0x9958 | ||
| 239 | #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 | ||
| 240 | #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 | ||
| 241 | #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 | ||
| 242 | #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 | ||
| 243 | #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 | ||
| 244 | #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 | ||
| 245 | #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 | ||
| 246 | #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 | ||
| 247 | #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 | ||
| 248 | #define AR_PHY_RADAR_1_MAXLEN 0x000000FF | ||
| 249 | #define AR_PHY_RADAR_1_MAXLEN_S 0 | ||
| 250 | |||
| 251 | #define AR_PHY_SWITCH_CHAIN_0 0x9960 | ||
| 252 | #define AR_PHY_SWITCH_COM 0x9964 | ||
| 253 | |||
| 254 | #define AR_PHY_SIGMA_DELTA 0x996C | ||
| 255 | #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 | ||
| 256 | #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 | ||
| 257 | #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 | ||
| 258 | #define AR_PHY_SIGMA_DELTA_FILT2_S 3 | ||
| 259 | #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 | ||
| 260 | #define AR_PHY_SIGMA_DELTA_FILT1_S 8 | ||
| 261 | #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 | ||
| 262 | #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 | ||
| 263 | |||
| 264 | #define AR_PHY_RESTART 0x9970 | ||
| 265 | #define AR_PHY_RESTART_DIV_GC 0x001C0000 | ||
| 266 | #define AR_PHY_RESTART_DIV_GC_S 18 | ||
| 267 | |||
| 268 | #define AR_PHY_RFBUS_REQ 0x997C | ||
| 269 | #define AR_PHY_RFBUS_REQ_EN 0x00000001 | ||
| 270 | |||
| 271 | #define AR_PHY_TIMING7 0x9980 | ||
| 272 | #define AR_PHY_TIMING8 0x9984 | ||
| 273 | #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF | ||
| 274 | #define AR_PHY_TIMING8_PILOT_MASK_2_S 0 | ||
| 275 | |||
| 276 | #define AR_PHY_BIN_MASK2_1 0x9988 | ||
| 277 | #define AR_PHY_BIN_MASK2_2 0x998c | ||
| 278 | #define AR_PHY_BIN_MASK2_3 0x9990 | ||
| 279 | #define AR_PHY_BIN_MASK2_4 0x9994 | ||
| 280 | |||
| 281 | #define AR_PHY_BIN_MASK_1 0x9900 | ||
| 282 | #define AR_PHY_BIN_MASK_2 0x9904 | ||
| 283 | #define AR_PHY_BIN_MASK_3 0x9908 | ||
| 284 | |||
| 285 | #define AR_PHY_MASK_CTL 0x990c | ||
| 286 | |||
| 287 | #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF | ||
| 288 | #define AR_PHY_BIN_MASK2_4_MASK_4_S 0 | ||
| 289 | |||
| 290 | #define AR_PHY_TIMING9 0x9998 | ||
| 291 | #define AR_PHY_TIMING10 0x999c | ||
| 292 | #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF | ||
| 293 | #define AR_PHY_TIMING10_PILOT_MASK_2_S 0 | ||
| 294 | |||
| 295 | #define AR_PHY_TIMING11 0x99a0 | ||
| 296 | #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF | ||
| 297 | #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 | ||
| 298 | #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 | ||
| 299 | #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 | ||
| 300 | #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 | ||
| 301 | #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 | ||
| 302 | |||
| 303 | #define AR_PHY_RX_CHAINMASK 0x99a4 | ||
| 304 | #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) | ||
| 305 | #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 | ||
| 306 | #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 | ||
| 307 | #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac | ||
| 308 | |||
| 309 | #define AR_PHY_EXT_CCA0 0x99b8 | ||
| 310 | #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF | ||
| 311 | #define AR_PHY_EXT_CCA0_THRESH62_S 0 | ||
| 312 | |||
| 313 | #define AR_PHY_EXT_CCA 0x99bc | ||
| 314 | #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 | ||
| 315 | #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 | ||
| 316 | #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 | ||
| 317 | #define AR_PHY_EXT_CCA_THRESH62_S 16 | ||
| 318 | #define AR_PHY_EXT_MINCCA_PWR 0xFF800000 | ||
| 319 | #define AR_PHY_EXT_MINCCA_PWR_S 23 | ||
| 320 | #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 | ||
| 321 | #define AR9280_PHY_EXT_MINCCA_PWR_S 16 | ||
| 322 | |||
| 323 | #define AR_PHY_SFCORR_EXT 0x99c0 | ||
| 324 | #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F | ||
| 325 | #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 | ||
| 326 | #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 | ||
| 327 | #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 | ||
| 328 | #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 | ||
| 329 | #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 | ||
| 330 | #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 | ||
| 331 | #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 | ||
| 332 | #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 | ||
| 333 | |||
| 334 | #define AR_PHY_HALFGI 0x99D0 | ||
| 335 | #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 | ||
| 336 | #define AR_PHY_HALFGI_DSC_MAN_S 4 | ||
| 337 | #define AR_PHY_HALFGI_DSC_EXP 0x0000000F | ||
| 338 | #define AR_PHY_HALFGI_DSC_EXP_S 0 | ||
| 339 | |||
| 340 | #define AR_PHY_CHAN_INFO_MEMORY 0x99DC | ||
| 341 | #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 | ||
| 342 | |||
| 343 | #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 | ||
| 344 | |||
| 345 | #define AR_PHY_M_SLEEP 0x99f0 | ||
| 346 | #define AR_PHY_REFCLKDLY 0x99f4 | ||
| 347 | #define AR_PHY_REFCLKPD 0x99f8 | ||
| 348 | |||
| 349 | #define AR_PHY_CALMODE 0x99f0 | ||
| 350 | |||
| 351 | #define AR_PHY_CALMODE_IQ 0x00000000 | ||
| 352 | #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 | ||
| 353 | #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 | ||
| 354 | #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 | ||
| 355 | |||
| 356 | #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) | ||
| 357 | #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) | ||
| 358 | #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) | ||
| 359 | #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) | ||
| 360 | |||
| 361 | #define AR_PHY_CURRENT_RSSI 0x9c1c | ||
| 362 | #define AR9280_PHY_CURRENT_RSSI 0x9c3c | ||
| 363 | |||
| 364 | #define AR_PHY_RFBUS_GRANT 0x9C20 | ||
| 365 | #define AR_PHY_RFBUS_GRANT_EN 0x00000001 | ||
| 366 | |||
| 367 | #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4 | ||
| 368 | #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 | ||
| 369 | |||
| 370 | #define AR_PHY_CHAN_INFO_GAIN 0x9CFC | ||
| 371 | |||
| 372 | #define AR_PHY_MODE 0xA200 | ||
| 373 | #define AR_PHY_MODE_AR2133 0x08 | ||
| 374 | #define AR_PHY_MODE_AR5111 0x00 | ||
| 375 | #define AR_PHY_MODE_AR5112 0x08 | ||
| 376 | #define AR_PHY_MODE_DYNAMIC 0x04 | ||
| 377 | #define AR_PHY_MODE_RF2GHZ 0x02 | ||
| 378 | #define AR_PHY_MODE_RF5GHZ 0x00 | ||
| 379 | #define AR_PHY_MODE_CCK 0x01 | ||
| 380 | #define AR_PHY_MODE_OFDM 0x00 | ||
| 381 | #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 | ||
| 382 | |||
| 383 | #define AR_PHY_CCK_TX_CTRL 0xA204 | ||
| 384 | #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 | ||
| 385 | |||
| 386 | #define AR_PHY_CCK_DETECT 0xA208 | ||
| 387 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F | ||
| 388 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 | ||
| 389 | /* [12:6] settling time for antenna switch */ | ||
| 390 | #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 | ||
| 391 | #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 | ||
| 392 | #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 | ||
| 393 | |||
| 394 | #define AR_PHY_GAIN_2GHZ 0xA20C | ||
| 395 | #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 | ||
| 396 | #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 | ||
| 397 | #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 | ||
| 398 | #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 | ||
| 399 | #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F | ||
| 400 | #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 | ||
| 401 | |||
| 402 | #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 | ||
| 403 | #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 | ||
| 404 | #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 | ||
| 405 | #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 | ||
| 406 | #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 | ||
| 407 | #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 | ||
| 408 | #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F | ||
| 409 | #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 | ||
| 410 | |||
| 411 | #define AR_PHY_CCK_RXCTRL4 0xA21C | ||
| 412 | #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 | ||
| 413 | #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 | ||
| 414 | |||
| 415 | #define AR_PHY_DAG_CTRLCCK 0xA228 | ||
| 416 | #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 | ||
| 417 | #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 | ||
| 418 | #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 | ||
| 419 | |||
| 420 | #define AR_PHY_FORCE_CLKEN_CCK 0xA22C | ||
| 421 | #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 | ||
| 422 | |||
| 423 | #define AR_PHY_POWER_TX_RATE3 0xA234 | ||
| 424 | #define AR_PHY_POWER_TX_RATE4 0xA238 | ||
| 425 | |||
| 426 | #define AR_PHY_SCRM_SEQ_XR 0xA23C | ||
| 427 | #define AR_PHY_HEADER_DETECT_XR 0xA240 | ||
| 428 | #define AR_PHY_CHIRP_DETECTED_XR 0xA244 | ||
| 429 | #define AR_PHY_BLUETOOTH 0xA254 | ||
| 430 | |||
| 431 | #define AR_PHY_TPCRG1 0xA258 | ||
| 432 | #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 | ||
| 433 | #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 | ||
| 434 | |||
| 435 | #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 | ||
| 436 | #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 | ||
| 437 | #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 | ||
| 438 | #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 | ||
| 439 | #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 | ||
| 440 | #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 | ||
| 441 | |||
| 442 | #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 | ||
| 443 | #define AR_PHY_MASK2_M_31_45 0xa3a4 | ||
| 444 | #define AR_PHY_MASK2_M_16_30 0xa3a8 | ||
| 445 | #define AR_PHY_MASK2_M_00_15 0xa3ac | ||
| 446 | #define AR_PHY_MASK2_P_15_01 0xa3b8 | ||
| 447 | #define AR_PHY_MASK2_P_30_16 0xa3bc | ||
| 448 | #define AR_PHY_MASK2_P_45_31 0xa3c0 | ||
| 449 | #define AR_PHY_MASK2_P_61_45 0xa3c4 | ||
| 450 | #define AR_PHY_SPUR_REG 0x994c | ||
| 451 | |||
| 452 | #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) | ||
| 453 | #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 | ||
| 454 | |||
| 455 | #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 | ||
| 456 | #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) | ||
| 457 | #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 | ||
| 458 | #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 | ||
| 459 | #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F | ||
| 460 | #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 | ||
| 461 | |||
| 462 | #define AR_PHY_PILOT_MASK_01_30 0xa3b0 | ||
| 463 | #define AR_PHY_PILOT_MASK_31_60 0xa3b4 | ||
| 464 | |||
| 465 | #define AR_PHY_CHANNEL_MASK_01_30 0x99d4 | ||
| 466 | #define AR_PHY_CHANNEL_MASK_31_60 0x99d8 | ||
| 467 | |||
| 468 | #define AR_PHY_ANALOG_SWAP 0xa268 | ||
| 469 | #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 | ||
| 470 | |||
| 471 | #define AR_PHY_TPCRG5 0xA26C | ||
| 472 | #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F | ||
| 473 | #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 | ||
| 474 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 | ||
| 475 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 | ||
| 476 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 | ||
| 477 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 | ||
| 478 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 | ||
| 479 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 | ||
| 480 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 | ||
| 481 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 | ||
| 482 | |||
| 483 | #define AR_PHY_POWER_TX_RATE5 0xA38C | ||
| 484 | #define AR_PHY_POWER_TX_RATE6 0xA390 | ||
| 485 | |||
| 486 | #define AR_PHY_CAL_CHAINMASK 0xA39C | ||
| 487 | |||
| 488 | #define AR_PHY_POWER_TX_SUB 0xA3C8 | ||
| 489 | #define AR_PHY_POWER_TX_RATE7 0xA3CC | ||
| 490 | #define AR_PHY_POWER_TX_RATE8 0xA3D0 | ||
| 491 | #define AR_PHY_POWER_TX_RATE9 0xA3D4 | ||
| 492 | |||
| 493 | #define AR_PHY_XPA_CFG 0xA3D8 | ||
| 494 | #define AR_PHY_FORCE_XPA_CFG 0x000000001 | ||
| 495 | #define AR_PHY_FORCE_XPA_CFG_S 0 | ||
| 496 | |||
| 497 | #define AR_PHY_CH1_CCA 0xa864 | ||
| 498 | #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 | ||
| 499 | #define AR_PHY_CH1_MINCCA_PWR_S 19 | ||
| 500 | #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 | ||
| 501 | #define AR9280_PHY_CH1_MINCCA_PWR_S 20 | ||
| 502 | |||
| 503 | #define AR_PHY_CH2_CCA 0xb864 | ||
| 504 | #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 | ||
| 505 | #define AR_PHY_CH2_MINCCA_PWR_S 19 | ||
| 506 | |||
| 507 | #define AR_PHY_CH1_EXT_CCA 0xa9bc | ||
| 508 | #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 | ||
| 509 | #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 | ||
| 510 | #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 | ||
| 511 | #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 | ||
| 512 | |||
| 513 | #define AR_PHY_CH2_EXT_CCA 0xb9bc | ||
| 514 | #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 | ||
| 515 | #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 | ||
| 516 | |||
| 517 | #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ | ||
| 518 | int r; \ | ||
| 519 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | ||
| 520 | REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \ | ||
| 521 | DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, \ | ||
| 522 | "RF 0x%x V 0x%x\n", \ | ||
| 523 | INI_RA((iniarray), r, 0), (regData)[r]); \ | ||
| 524 | DO_DELAY(regWr); \ | ||
| 525 | } \ | ||
| 526 | } while (0) | ||
| 527 | |||
| 528 | #define ATH9K_KEY_XOR 0xaa | ||
| 529 | |||
| 530 | #define ATH9K_IS_MIC_ENABLED(ah) \ | ||
| 531 | (AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) | ||
| 532 | |||
| 533 | #define ANTSWAP_AB 0x0001 | ||
| 534 | #define REDUCE_CHAIN_0 0x00000050 | ||
| 535 | #define REDUCE_CHAIN_1 0x00000051 | ||
| 536 | |||
| 537 | #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ | ||
| 538 | int i; \ | ||
| 539 | for (i = 0; i < (_iniarray)->ia_rows; i++) \ | ||
| 540 | (_bank)[i] = INI_RA((_iniarray), i, _col);; \ | ||
| 541 | } while (0) | ||
| 542 | |||
| 543 | #endif | ||
diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c new file mode 100644 index 000000000000..73c460ad355f --- /dev/null +++ b/drivers/net/wireless/ath9k/rc.c | |||
| @@ -0,0 +1,2126 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2004 Video54 Technologies, Inc. | ||
| 3 | * Copyright (c) 2004-2008 Atheros Communications, Inc. | ||
| 4 | * | ||
| 5 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 6 | * purpose with or without fee is hereby granted, provided that the above | ||
| 7 | * copyright notice and this permission notice appear in all copies. | ||
| 8 | * | ||
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 16 | */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Atheros rate control algorithm | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include "core.h" | ||
| 23 | #include "../net/mac80211/rate.h" | ||
| 24 | |||
| 25 | static u32 tx_triglevel_max; | ||
| 26 | |||
| 27 | static struct ath_rate_table ar5416_11na_ratetable = { | ||
| 28 | 42, | ||
| 29 | { | ||
| 30 | { TRUE, TRUE, WLAN_PHY_OFDM, 6000, /* 6 Mb */ | ||
| 31 | 5400, 0x0b, 0x00, 12, | ||
| 32 | 0, 2, 1, 0, 0, 0, 0, 0 }, | ||
| 33 | { TRUE, TRUE, WLAN_PHY_OFDM, 9000, /* 9 Mb */ | ||
| 34 | 7800, 0x0f, 0x00, 18, | ||
| 35 | 0, 3, 1, 1, 1, 1, 1, 0 }, | ||
| 36 | { TRUE, TRUE, WLAN_PHY_OFDM, 12000, /* 12 Mb */ | ||
| 37 | 10000, 0x0a, 0x00, 24, | ||
| 38 | 2, 4, 2, 2, 2, 2, 2, 0 }, | ||
| 39 | { TRUE, TRUE, WLAN_PHY_OFDM, 18000, /* 18 Mb */ | ||
| 40 | 13900, 0x0e, 0x00, 36, | ||
| 41 | 2, 6, 2, 3, 3, 3, 3, 0 }, | ||
| 42 | { TRUE, TRUE, WLAN_PHY_OFDM, 24000, /* 24 Mb */ | ||
| 43 | 17300, 0x09, 0x00, 48, | ||
| 44 | 4, 10, 3, 4, 4, 4, 4, 0 }, | ||
| 45 | { TRUE, TRUE, WLAN_PHY_OFDM, 36000, /* 36 Mb */ | ||
| 46 | 23000, 0x0d, 0x00, 72, | ||
| 47 | 4, 14, 3, 5, 5, 5, 5, 0 }, | ||
| 48 | { TRUE, TRUE, WLAN_PHY_OFDM, 48000, /* 48 Mb */ | ||
| 49 | 27400, 0x08, 0x00, 96, | ||
| 50 | 4, 20, 3, 6, 6, 6, 6, 0 }, | ||
| 51 | { TRUE, TRUE, WLAN_PHY_OFDM, 54000, /* 54 Mb */ | ||
| 52 | 29300, 0x0c, 0x00, 108, | ||
| 53 | 4, 23, 3, 7, 7, 7, 7, 0 }, | ||
| 54 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 6500, /* 6.5 Mb */ | ||
| 55 | 6400, 0x80, 0x00, 0, | ||
| 56 | 0, 2, 3, 8, 24, 8, 24, 3216 }, | ||
| 57 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 13000, /* 13 Mb */ | ||
| 58 | 12700, 0x81, 0x00, 1, | ||
| 59 | 2, 4, 3, 9, 25, 9, 25, 6434 }, | ||
| 60 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 19500, /* 19.5 Mb */ | ||
| 61 | 18800, 0x82, 0x00, 2, | ||
| 62 | 2, 6, 3, 10, 26, 10, 26, 9650 }, | ||
| 63 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 26000, /* 26 Mb */ | ||
| 64 | 25000, 0x83, 0x00, 3, | ||
| 65 | 4, 10, 3, 11, 27, 11, 27, 12868 }, | ||
| 66 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 39000, /* 39 Mb */ | ||
| 67 | 36700, 0x84, 0x00, 4, | ||
| 68 | 4, 14, 3, 12, 28, 12, 28, 19304 }, | ||
| 69 | { FALSE, TRUE_20, WLAN_PHY_HT_20_SS, 52000, /* 52 Mb */ | ||
| 70 | 48100, 0x85, 0x00, 5, | ||
| 71 | 4, 20, 3, 13, 29, 13, 29, 25740 }, | ||
| 72 | { FALSE, TRUE_20, WLAN_PHY_HT_20_SS, 58500, /* 58.5 Mb */ | ||
| 73 | 53500, 0x86, 0x00, 6, | ||
| 74 | 4, 23, 3, 14, 30, 14, 30, 28956 }, | ||
| 75 | { FALSE, TRUE_20, WLAN_PHY_HT_20_SS, 65000, /* 65 Mb */ | ||
| 76 | 59000, 0x87, 0x00, 7, | ||
| 77 | 4, 25, 3, 15, 31, 15, 32, 32180 }, | ||
| 78 | { FALSE, FALSE, WLAN_PHY_HT_20_DS, 13000, /* 13 Mb */ | ||
| 79 | 12700, 0x88, 0x00, | ||
| 80 | 8, 0, 2, 3, 16, 33, 16, 33, 6430 }, | ||
| 81 | { FALSE, FALSE, WLAN_PHY_HT_20_DS, 26000, /* 26 Mb */ | ||
| 82 | 24800, 0x89, 0x00, 9, | ||
| 83 | 2, 4, 3, 17, 34, 17, 34, 12860 }, | ||
| 84 | { FALSE, FALSE, WLAN_PHY_HT_20_DS, 39000, /* 39 Mb */ | ||
| 85 | 36600, 0x8a, 0x00, 10, | ||
| 86 | 2, 6, 3, 18, 35, 18, 35, 19300 }, | ||
| 87 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 52000, /* 52 Mb */ | ||
| 88 | 48100, 0x8b, 0x00, 11, | ||
| 89 | 4, 10, 3, 19, 36, 19, 36, 25736 }, | ||
| 90 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 78000, /* 78 Mb */ | ||
| 91 | 69500, 0x8c, 0x00, 12, | ||
| 92 | 4, 14, 3, 20, 37, 20, 37, 38600 }, | ||
| 93 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 104000, /* 104 Mb */ | ||
| 94 | 89500, 0x8d, 0x00, 13, | ||
| 95 | 4, 20, 3, 21, 38, 21, 38, 51472 }, | ||
| 96 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 117000, /* 117 Mb */ | ||
| 97 | 98900, 0x8e, 0x00, 14, | ||
| 98 | 4, 23, 3, 22, 39, 22, 39, 57890 }, | ||
| 99 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 130000, /* 130 Mb */ | ||
| 100 | 108300, 0x8f, 0x00, 15, | ||
| 101 | 4, 25, 3, 23, 40, 23, 41, 64320 }, | ||
| 102 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 13500, /* 13.5 Mb */ | ||
| 103 | 13200, 0x80, 0x00, 0, | ||
| 104 | 0, 2, 3, 8, 24, 24, 24, 6684 }, | ||
| 105 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 27500, /* 27.0 Mb */ | ||
| 106 | 25900, 0x81, 0x00, 1, | ||
| 107 | 2, 4, 3, 9, 25, 25, 25, 13368 }, | ||
| 108 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 40500, /* 40.5 Mb */ | ||
| 109 | 38600, 0x82, 0x00, 2, | ||
| 110 | 2, 6, 3, 10, 26, 26, 26, 20052 }, | ||
| 111 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 54000, /* 54 Mb */ | ||
| 112 | 49800, 0x83, 0x00, 3, | ||
| 113 | 4, 10, 3, 11, 27, 27, 27, 26738 }, | ||
| 114 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 81500, /* 81 Mb */ | ||
| 115 | 72200, 0x84, 0x00, 4, | ||
| 116 | 4, 14, 3, 12, 28, 28, 28, 40104 }, | ||
| 117 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS, 108000, /* 108 Mb */ | ||
| 118 | 92900, 0x85, 0x00, 5, | ||
| 119 | 4, 20, 3, 13, 29, 29, 29, 53476 }, | ||
| 120 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS, 121500, /* 121.5 Mb */ | ||
| 121 | 102700, 0x86, 0x00, 6, | ||
| 122 | 4, 23, 3, 14, 30, 30, 30, 60156 }, | ||
| 123 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS, 135000, /* 135 Mb */ | ||
| 124 | 112000, 0x87, 0x00, 7, | ||
| 125 | 4, 25, 3, 15, 31, 32, 32, 66840 }, | ||
| 126 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI, 150000, /* 150 Mb */ | ||
| 127 | 122000, 0x87, 0x00, 7, | ||
| 128 | 4, 25, 3, 15, 31, 32, 32, 74200 }, | ||
| 129 | { FALSE, FALSE, WLAN_PHY_HT_40_DS, 27000, /* 27 Mb */ | ||
| 130 | 25800, 0x88, 0x00, 8, | ||
| 131 | 0, 2, 3, 16, 33, 33, 33, 13360 }, | ||
| 132 | { FALSE, FALSE, WLAN_PHY_HT_40_DS, 54000, /* 54 Mb */ | ||
| 133 | 49800, 0x89, 0x00, 9, | ||
| 134 | 2, 4, 3, 17, 34, 34, 34, 26720 }, | ||
| 135 | { FALSE, FALSE, WLAN_PHY_HT_40_DS, 81000, /* 81 Mb */ | ||
| 136 | 71900, 0x8a, 0x00, 10, | ||
| 137 | 2, 6, 3, 18, 35, 35, 35, 40080 }, | ||
| 138 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 108000, /* 108 Mb */ | ||
| 139 | 92500, 0x8b, 0x00, 11, | ||
| 140 | 4, 10, 3, 19, 36, 36, 36, 53440 }, | ||
| 141 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 162000, /* 162 Mb */ | ||
| 142 | 130300, 0x8c, 0x00, 12, | ||
| 143 | 4, 14, 3, 20, 37, 37, 37, 80160 }, | ||
| 144 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 216000, /* 216 Mb */ | ||
| 145 | 162800, 0x8d, 0x00, 13, | ||
| 146 | 4, 20, 3, 21, 38, 38, 38, 106880 }, | ||
| 147 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 243000, /* 243 Mb */ | ||
| 148 | 178200, 0x8e, 0x00, 14, | ||
| 149 | 4, 23, 3, 22, 39, 39, 39, 120240 }, | ||
| 150 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 270000, /* 270 Mb */ | ||
| 151 | 192100, 0x8f, 0x00, 15, | ||
| 152 | 4, 25, 3, 23, 40, 41, 41, 133600 }, | ||
| 153 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS_HGI, 300000, /* 300 Mb */ | ||
| 154 | 207000, 0x8f, 0x00, 15, | ||
| 155 | 4, 25, 3, 23, 40, 41, 41, 148400 }, | ||
| 156 | }, | ||
| 157 | 50, /* probe interval */ | ||
| 158 | 50, /* rssi reduce interval */ | ||
| 159 | WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ | ||
| 160 | }; | ||
| 161 | |||
| 162 | /* TRUE_ALL - valid for 20/40/Legacy, | ||
| 163 | * TRUE - Legacy only, | ||
| 164 | * TRUE_20 - HT 20 only, | ||
| 165 | * TRUE_40 - HT 40 only */ | ||
| 166 | |||
| 167 | /* 4ms frame limit not used for NG mode. The values filled | ||
| 168 | * for HT are the 64K max aggregate limit */ | ||
| 169 | |||
| 170 | static struct ath_rate_table ar5416_11ng_ratetable = { | ||
| 171 | 46, | ||
| 172 | { | ||
| 173 | { TRUE_ALL, TRUE_ALL, WLAN_PHY_CCK, 1000, /* 1 Mb */ | ||
| 174 | 900, 0x1b, 0x00, 2, | ||
| 175 | 0, 0, 1, 0, 0, 0, 0, 0 }, | ||
| 176 | { TRUE_ALL, TRUE_ALL, WLAN_PHY_CCK, 2000, /* 2 Mb */ | ||
| 177 | 1900, 0x1a, 0x04, 4, | ||
| 178 | 1, 1, 1, 1, 1, 1, 1, 0 }, | ||
| 179 | { TRUE_ALL, TRUE_ALL, WLAN_PHY_CCK, 5500, /* 5.5 Mb */ | ||
| 180 | 4900, 0x19, 0x04, 11, | ||
| 181 | 2, 2, 2, 2, 2, 2, 2, 0 }, | ||
| 182 | { TRUE_ALL, TRUE_ALL, WLAN_PHY_CCK, 11000, /* 11 Mb */ | ||
| 183 | 8100, 0x18, 0x04, 22, | ||
| 184 | 3, 3, 2, 3, 3, 3, 3, 0 }, | ||
| 185 | { FALSE, FALSE, WLAN_PHY_OFDM, 6000, /* 6 Mb */ | ||
| 186 | 5400, 0x0b, 0x00, 12, | ||
| 187 | 4, 2, 1, 4, 4, 4, 4, 0 }, | ||
| 188 | { FALSE, FALSE, WLAN_PHY_OFDM, 9000, /* 9 Mb */ | ||
| 189 | 7800, 0x0f, 0x00, 18, | ||
| 190 | 4, 3, 1, 5, 5, 5, 5, 0 }, | ||
| 191 | { TRUE, TRUE, WLAN_PHY_OFDM, 12000, /* 12 Mb */ | ||
| 192 | 10100, 0x0a, 0x00, 24, | ||
| 193 | 6, 4, 1, 6, 6, 6, 6, 0 }, | ||
| 194 | { TRUE, TRUE, WLAN_PHY_OFDM, 18000, /* 18 Mb */ | ||
| 195 | 14100, 0x0e, 0x00, 36, | ||
| 196 | 6, 6, 2, 7, 7, 7, 7, 0 }, | ||
| 197 | { TRUE, TRUE, WLAN_PHY_OFDM, 24000, /* 24 Mb */ | ||
| 198 | 17700, 0x09, 0x00, 48, | ||
| 199 | 8, 10, 3, 8, 8, 8, 8, 0 }, | ||
| 200 | { TRUE, TRUE, WLAN_PHY_OFDM, 36000, /* 36 Mb */ | ||
| 201 | 23700, 0x0d, 0x00, 72, | ||
| 202 | 8, 14, 3, 9, 9, 9, 9, 0 }, | ||
| 203 | { TRUE, TRUE, WLAN_PHY_OFDM, 48000, /* 48 Mb */ | ||
| 204 | 27400, 0x08, 0x00, 96, | ||
| 205 | 8, 20, 3, 10, 10, 10, 10, 0 }, | ||
| 206 | { TRUE, TRUE, WLAN_PHY_OFDM, 54000, /* 54 Mb */ | ||
| 207 | 30900, 0x0c, 0x00, 108, | ||
| 208 | 8, 23, 3, 11, 11, 11, 11, 0 }, | ||
| 209 | { FALSE, FALSE, WLAN_PHY_HT_20_SS, 6500, /* 6.5 Mb */ | ||
| 210 | 6400, 0x80, 0x00, 0, | ||
| 211 | 4, 2, 3, 12, 28, 12, 28, 3216 }, | ||
| 212 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 13000, /* 13 Mb */ | ||
| 213 | 12700, 0x81, 0x00, 1, | ||
| 214 | 6, 4, 3, 13, 29, 13, 29, 6434 }, | ||
| 215 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 19500, /* 19.5 Mb */ | ||
| 216 | 18800, 0x82, 0x00, 2, | ||
| 217 | 6, 6, 3, 14, 30, 14, 30, 9650 }, | ||
| 218 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 26000, /* 26 Mb */ | ||
| 219 | 25000, 0x83, 0x00, 3, | ||
| 220 | 8, 10, 3, 15, 31, 15, 31, 12868 }, | ||
| 221 | { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 39000, /* 39 Mb */ | ||
| 222 | 36700, 0x84, 0x00, 4, | ||
| 223 | 8, 14, 3, 16, 32, 16, 32, 19304 }, | ||
| 224 | { FALSE, TRUE_20, WLAN_PHY_HT_20_SS, 52000, /* 52 Mb */ | ||
| 225 | 48100, 0x85, 0x00, 5, | ||
| 226 | 8, 20, 3, 17, 33, 17, 33, 25740 }, | ||
| 227 | { FALSE, TRUE_20, WLAN_PHY_HT_20_SS, 58500, /* 58.5 Mb */ | ||
| 228 | 53500, 0x86, 0x00, 6, | ||
| 229 | 8, 23, 3, 18, 34, 18, 34, 28956 }, | ||
| 230 | { FALSE, TRUE_20, WLAN_PHY_HT_20_SS, 65000, /* 65 Mb */ | ||
| 231 | 59000, 0x87, 0x00, 7, | ||
| 232 | 8, 25, 3, 19, 35, 19, 36, 32180 }, | ||
| 233 | { FALSE, FALSE, WLAN_PHY_HT_20_DS, 13000, /* 13 Mb */ | ||
| 234 | 12700, 0x88, 0x00, 8, | ||
| 235 | 4, 2, 3, 20, 37, 20, 37, 6430 }, | ||
| 236 | { FALSE, FALSE, WLAN_PHY_HT_20_DS, 26000, /* 26 Mb */ | ||
| 237 | 24800, 0x89, 0x00, 9, | ||
| 238 | 6, 4, 3, 21, 38, 21, 38, 12860 }, | ||
| 239 | { FALSE, FALSE, WLAN_PHY_HT_20_DS, 39000, /* 39 Mb */ | ||
| 240 | 36600, 0x8a, 0x00, 10, | ||
| 241 | 6, 6, 3, 22, 39, 22, 39, 19300 }, | ||
| 242 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 52000, /* 52 Mb */ | ||
| 243 | 48100, 0x8b, 0x00, 11, | ||
| 244 | 8, 10, 3, 23, 40, 23, 40, 25736 }, | ||
| 245 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 78000, /* 78 Mb */ | ||
| 246 | 69500, 0x8c, 0x00, 12, | ||
| 247 | 8, 14, 3, 24, 41, 24, 41, 38600 }, | ||
| 248 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 104000, /* 104 Mb */ | ||
| 249 | 89500, 0x8d, 0x00, 13, | ||
| 250 | 8, 20, 3, 25, 42, 25, 42, 51472 }, | ||
| 251 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 117000, /* 117 Mb */ | ||
| 252 | 98900, 0x8e, 0x00, 14, | ||
| 253 | 8, 23, 3, 26, 43, 26, 44, 57890 }, | ||
| 254 | { TRUE_20, FALSE, WLAN_PHY_HT_20_DS, 130000, /* 130 Mb */ | ||
| 255 | 108300, 0x8f, 0x00, 15, | ||
| 256 | 8, 25, 3, 27, 44, 27, 45, 64320 }, | ||
| 257 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 13500, /* 13.5 Mb */ | ||
| 258 | 13200, 0x80, 0x00, 0, | ||
| 259 | 8, 2, 3, 12, 28, 28, 28, 6684 }, | ||
| 260 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 27500, /* 27.0 Mb */ | ||
| 261 | 25900, 0x81, 0x00, 1, | ||
| 262 | 8, 4, 3, 13, 29, 29, 29, 13368 }, | ||
| 263 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 40500, /* 40.5 Mb */ | ||
| 264 | 38600, 0x82, 0x00, 2, | ||
| 265 | 8, 6, 3, 14, 30, 30, 30, 20052 }, | ||
| 266 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 54000, /* 54 Mb */ | ||
| 267 | 49800, 0x83, 0x00, 3, | ||
| 268 | 8, 10, 3, 15, 31, 31, 31, 26738 }, | ||
| 269 | { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS, 81500, /* 81 Mb */ | ||
| 270 | 72200, 0x84, 0x00, 4, | ||
| 271 | 8, 14, 3, 16, 32, 32, 32, 40104 }, | ||
| 272 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS, 108000, /* 108 Mb */ | ||
| 273 | 92900, 0x85, 0x00, 5, | ||
| 274 | 8, 20, 3, 17, 33, 33, 33, 53476 }, | ||
| 275 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS, 121500, /* 121.5 Mb */ | ||
| 276 | 102700, 0x86, 0x00, 6, | ||
| 277 | 8, 23, 3, 18, 34, 34, 34, 60156 }, | ||
| 278 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS, 135000, /* 135 Mb */ | ||
| 279 | 112000, 0x87, 0x00, 7, | ||
| 280 | 8, 23, 3, 19, 35, 36, 36, 66840 }, | ||
| 281 | { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI, 150000, /* 150 Mb */ | ||
| 282 | 122000, 0x87, 0x00, 7, | ||
| 283 | 8, 25, 3, 19, 35, 36, 36, 74200 }, | ||
| 284 | { FALSE, FALSE, WLAN_PHY_HT_40_DS, 27000, /* 27 Mb */ | ||
| 285 | 25800, 0x88, 0x00, 8, | ||
| 286 | 8, 2, 3, 20, 37, 37, 37, 13360 }, | ||
| 287 | { FALSE, FALSE, WLAN_PHY_HT_40_DS, 54000, /* 54 Mb */ | ||
| 288 | 49800, 0x89, 0x00, 9, | ||
| 289 | 8, 4, 3, 21, 38, 38, 38, 26720 }, | ||
| 290 | { FALSE, FALSE, WLAN_PHY_HT_40_DS, 81000, /* 81 Mb */ | ||
| 291 | 71900, 0x8a, 0x00, 10, | ||
| 292 | 8, 6, 3, 22, 39, 39, 39, 40080 }, | ||
| 293 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 108000, /* 108 Mb */ | ||
| 294 | 92500, 0x8b, 0x00, 11, | ||
| 295 | 8, 10, 3, 23, 40, 40, 40, 53440 }, | ||
| 296 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 162000, /* 162 Mb */ | ||
| 297 | 130300, 0x8c, 0x00, 12, | ||
| 298 | 8, 14, 3, 24, 41, 41, 41, 80160 }, | ||
| 299 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 216000, /* 216 Mb */ | ||
| 300 | 162800, 0x8d, 0x00, 13, | ||
| 301 | 8, 20, 3, 25, 42, 42, 42, 106880 }, | ||
| 302 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 243000, /* 243 Mb */ | ||
| 303 | 178200, 0x8e, 0x00, 14, | ||
| 304 | 8, 23, 3, 26, 43, 43, 43, 120240 }, | ||
| 305 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS, 270000, /* 270 Mb */ | ||
| 306 | 192100, 0x8f, 0x00, 15, | ||
| 307 | 8, 23, 3, 27, 44, 45, 45, 133600 }, | ||
| 308 | { TRUE_40, FALSE, WLAN_PHY_HT_40_DS_HGI, 300000, /* 300 Mb */ | ||
| 309 | 207000, 0x8f, 0x00, 15, | ||
| 310 | 8, 25, 3, 27, 44, 45, 45, 148400 }, | ||
| 311 | }, | ||
| 312 | 50, /* probe interval */ | ||
| 313 | 50, /* rssi reduce interval */ | ||
| 314 | WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ | ||
| 315 | }; | ||
| 316 | |||
| 317 | static struct ath_rate_table ar5416_11a_ratetable = { | ||
| 318 | 8, | ||
| 319 | { | ||
| 320 | { TRUE, TRUE, WLAN_PHY_OFDM, 6000, /* 6 Mb */ | ||
| 321 | 5400, 0x0b, 0x00, (0x80|12), | ||
| 322 | 0, 2, 1, 0, 0 }, | ||
| 323 | { TRUE, TRUE, WLAN_PHY_OFDM, 9000, /* 9 Mb */ | ||
| 324 | 7800, 0x0f, 0x00, 18, | ||
| 325 | 0, 3, 1, 1, 0 }, | ||
| 326 | { TRUE, TRUE, WLAN_PHY_OFDM, 12000, /* 12 Mb */ | ||
| 327 | 10000, 0x0a, 0x00, (0x80|24), | ||
| 328 | 2, 4, 2, 2, 0 }, | ||
| 329 | { TRUE, TRUE, WLAN_PHY_OFDM, 18000, /* 18 Mb */ | ||
| 330 | 13900, 0x0e, 0x00, 36, | ||
| 331 | 2, 6, 2, 3, 0 }, | ||
| 332 | { TRUE, TRUE, WLAN_PHY_OFDM, 24000, /* 24 Mb */ | ||
| 333 | 17300, 0x09, 0x00, (0x80|48), | ||
| 334 | 4, 10, 3, 4, 0 }, | ||
| 335 | { TRUE, TRUE, WLAN_PHY_OFDM, 36000, /* 36 Mb */ | ||
| 336 | 23000, 0x0d, 0x00, 72, | ||
| 337 | 4, 14, 3, 5, 0 }, | ||
| 338 | { TRUE, TRUE, WLAN_PHY_OFDM, 48000, /* 48 Mb */ | ||
| 339 | 27400, 0x08, 0x00, 96, | ||
| 340 | 4, 19, 3, 6, 0 }, | ||
| 341 | { TRUE, TRUE, WLAN_PHY_OFDM, 54000, /* 54 Mb */ | ||
| 342 | 29300, 0x0c, 0x00, 108, | ||
| 343 | 4, 23, 3, 7, 0 }, | ||
| 344 | }, | ||
| 345 | 50, /* probe interval */ | ||
| 346 | 50, /* rssi reduce interval */ | ||
| 347 | 0, /* Phy rates allowed initially */ | ||
| 348 | }; | ||
| 349 | |||
| 350 | static struct ath_rate_table ar5416_11a_ratetable_Half = { | ||
| 351 | 8, | ||
| 352 | { | ||
| 353 | { TRUE, TRUE, WLAN_PHY_OFDM, 3000, /* 6 Mb */ | ||
| 354 | 2700, 0x0b, 0x00, (0x80|6), | ||
| 355 | 0, 2, 1, 0, 0}, | ||
| 356 | { TRUE, TRUE, WLAN_PHY_OFDM, 4500, /* 9 Mb */ | ||
| 357 | 3900, 0x0f, 0x00, 9, | ||
| 358 | 0, 3, 1, 1, 0 }, | ||
| 359 | { TRUE, TRUE, WLAN_PHY_OFDM, 6000, /* 12 Mb */ | ||
| 360 | 5000, 0x0a, 0x00, (0x80|12), | ||
| 361 | 2, 4, 2, 2, 0 }, | ||
| 362 | { TRUE, TRUE, WLAN_PHY_OFDM, 9000, /* 18 Mb */ | ||
| 363 | 6950, 0x0e, 0x00, 18, | ||
| 364 | 2, 6, 2, 3, 0 }, | ||
| 365 | { TRUE, TRUE, WLAN_PHY_OFDM, 12000, /* 24 Mb */ | ||
| 366 | 8650, 0x09, 0x00, (0x80|24), | ||
| 367 | 4, 10, 3, 4, 0 }, | ||
| 368 | { TRUE, TRUE, WLAN_PHY_OFDM, 18000, /* 36 Mb */ | ||
| 369 | 11500, 0x0d, 0x00, 36, | ||
| 370 | 4, 14, 3, 5, 0 }, | ||
| 371 | { TRUE, TRUE, WLAN_PHY_OFDM, 24000, /* 48 Mb */ | ||
| 372 | 13700, 0x08, 0x00, 48, | ||
| 373 | 4, 19, 3, 6, 0 }, | ||
| 374 | { TRUE, TRUE, WLAN_PHY_OFDM, 27000, /* 54 Mb */ | ||
| 375 | 14650, 0x0c, 0x00, 54, | ||
| 376 | 4, 23, 3, 7, 0 }, | ||
| 377 | }, | ||
| 378 | 50, /* probe interval */ | ||
| 379 | 50, /* rssi reduce interval */ | ||
| 380 | 0, /* Phy rates allowed initially */ | ||
| 381 | }; | ||
| 382 | |||
| 383 | static struct ath_rate_table ar5416_11a_ratetable_Quarter = { | ||
| 384 | 8, | ||
| 385 | { | ||
| 386 | { TRUE, TRUE, WLAN_PHY_OFDM, 1500, /* 6 Mb */ | ||
| 387 | 1350, 0x0b, 0x00, (0x80|3), | ||
| 388 | 0, 2, 1, 0, 0 }, | ||
| 389 | { TRUE, TRUE, WLAN_PHY_OFDM, 2250, /* 9 Mb */ | ||
| 390 | 1950, 0x0f, 0x00, 4, | ||
| 391 | 0, 3, 1, 1, 0 }, | ||
| 392 | { TRUE, TRUE, WLAN_PHY_OFDM, 3000, /* 12 Mb */ | ||
| 393 | 2500, 0x0a, 0x00, (0x80|6), | ||
| 394 | 2, 4, 2, 2, 0 }, | ||
| 395 | { TRUE, TRUE, WLAN_PHY_OFDM, 4500, /* 18 Mb */ | ||
| 396 | 3475, 0x0e, 0x00, 9, | ||
| 397 | 2, 6, 2, 3, 0 }, | ||
| 398 | { TRUE, TRUE, WLAN_PHY_OFDM, 6000, /* 25 Mb */ | ||
| 399 | 4325, 0x09, 0x00, (0x80|12), | ||
| 400 | 4, 10, 3, 4, 0 }, | ||
| 401 | { TRUE, TRUE, WLAN_PHY_OFDM, 9000, /* 36 Mb */ | ||
| 402 | 5750, 0x0d, 0x00, 18, | ||
| 403 | 4, 14, 3, 5, 0 }, | ||
| 404 | { TRUE, TRUE, WLAN_PHY_OFDM, 12000, /* 48 Mb */ | ||
| 405 | 6850, 0x08, 0x00, 24, | ||
| 406 | 4, 19, 3, 6, 0 }, | ||
| 407 | { TRUE, TRUE, WLAN_PHY_OFDM, 13500, /* 54 Mb */ | ||
| 408 | 7325, 0x0c, 0x00, 27, | ||
| 409 | 4, 23, 3, 7, 0 }, | ||
| 410 | }, | ||
| 411 | 50, /* probe interval */ | ||
| 412 | 50, /* rssi reduce interval */ | ||
| 413 | 0, /* Phy rates allowed initially */ | ||
| 414 | }; | ||
| 415 | |||
| 416 | static struct ath_rate_table ar5416_11g_ratetable = { | ||
| 417 | 12, | ||
| 418 | { | ||
| 419 | { TRUE, TRUE, WLAN_PHY_CCK, 1000, /* 1 Mb */ | ||
| 420 | 900, 0x1b, 0x00, 2, | ||
| 421 | 0, 0, 1, 0, 0 }, | ||
| 422 | { TRUE, TRUE, WLAN_PHY_CCK, 2000, /* 2 Mb */ | ||
| 423 | 1900, 0x1a, 0x04, 4, | ||
| 424 | 1, 1, 1, 1, 0 }, | ||
| 425 | { TRUE, TRUE, WLAN_PHY_CCK, 5500, /* 5.5 Mb */ | ||
| 426 | 4900, 0x19, 0x04, 11, | ||
| 427 | 2, 2, 2, 2, 0 }, | ||
| 428 | { TRUE, TRUE, WLAN_PHY_CCK, 11000, /* 11 Mb */ | ||
| 429 | 8100, 0x18, 0x04, 22, | ||
| 430 | 3, 3, 2, 3, 0 }, | ||
| 431 | { FALSE, FALSE, WLAN_PHY_OFDM, 6000, /* 6 Mb */ | ||
| 432 | 5400, 0x0b, 0x00, 12, | ||
| 433 | 4, 2, 1, 4, 0 }, | ||
| 434 | { FALSE, FALSE, WLAN_PHY_OFDM, 9000, /* 9 Mb */ | ||
| 435 | 7800, 0x0f, 0x00, 18, | ||
| 436 | 4, 3, 1, 5, 0 }, | ||
| 437 | { TRUE, TRUE, WLAN_PHY_OFDM, 12000, /* 12 Mb */ | ||
| 438 | 10000, 0x0a, 0x00, 24, | ||
| 439 | 6, 4, 1, 6, 0 }, | ||
| 440 | { TRUE, TRUE, WLAN_PHY_OFDM, 18000, /* 18 Mb */ | ||
| 441 | 13900, 0x0e, 0x00, 36, | ||
| 442 | 6, 6, 2, 7, 0 }, | ||
| 443 | { TRUE, TRUE, WLAN_PHY_OFDM, 24000, /* 24 Mb */ | ||
| 444 | 17300, 0x09, 0x00, 48, | ||
| 445 | 8, 10, 3, 8, 0 }, | ||
| 446 | { TRUE, TRUE, WLAN_PHY_OFDM, 36000, /* 36 Mb */ | ||
| 447 | 23000, 0x0d, 0x00, 72, | ||
| 448 | 8, 14, 3, 9, 0 }, | ||
| 449 | { TRUE, TRUE, WLAN_PHY_OFDM, 48000, /* 48 Mb */ | ||
| 450 | 27400, 0x08, 0x00, 96, | ||
| 451 | 8, 19, 3, 10, 0 }, | ||
| 452 | { TRUE, TRUE, WLAN_PHY_OFDM, 54000, /* 54 Mb */ | ||
| 453 | 29300, 0x0c, 0x00, 108, | ||
| 454 | 8, 23, 3, 11, 0 }, | ||
| 455 | }, | ||
| 456 | 50, /* probe interval */ | ||
| 457 | 50, /* rssi reduce interval */ | ||
| 458 | 0, /* Phy rates allowed initially */ | ||
| 459 | }; | ||
| 460 | |||
| 461 | static struct ath_rate_table ar5416_11b_ratetable = { | ||
| 462 | 4, | ||
| 463 | { | ||
| 464 | { TRUE, TRUE, WLAN_PHY_CCK, 1000, /* 1 Mb */ | ||
| 465 | 900, 0x1b, 0x00, (0x80|2), | ||
| 466 | 0, 0, 1, 0, 0 }, | ||
| 467 | { TRUE, TRUE, WLAN_PHY_CCK, 2000, /* 2 Mb */ | ||
| 468 | 1800, 0x1a, 0x04, (0x80|4), | ||
| 469 | 1, 1, 1, 1, 0 }, | ||
| 470 | { TRUE, TRUE, WLAN_PHY_CCK, 5500, /* 5.5 Mb */ | ||
| 471 | 4300, 0x19, 0x04, (0x80|11), | ||
| 472 | 1, 2, 2, 2, 0 }, | ||
| 473 | { TRUE, TRUE, WLAN_PHY_CCK, 11000, /* 11 Mb */ | ||
| 474 | 7100, 0x18, 0x04, (0x80|22), | ||
| 475 | 1, 4, 100, 3, 0 }, | ||
| 476 | }, | ||
| 477 | 100, /* probe interval */ | ||
| 478 | 100, /* rssi reduce interval */ | ||
| 479 | 0, /* Phy rates allowed initially */ | ||
| 480 | }; | ||
| 481 | |||
| 482 | static void ar5416_attach_ratetables(struct ath_rate_softc *sc) | ||
| 483 | { | ||
| 484 | /* | ||
| 485 | * Attach rate tables. | ||
| 486 | */ | ||
| 487 | sc->hw_rate_table[ATH9K_MODE_11B] = &ar5416_11b_ratetable; | ||
| 488 | sc->hw_rate_table[ATH9K_MODE_11A] = &ar5416_11a_ratetable; | ||
| 489 | sc->hw_rate_table[ATH9K_MODE_11G] = &ar5416_11g_ratetable; | ||
| 490 | |||
| 491 | sc->hw_rate_table[ATH9K_MODE_11NA_HT20] = &ar5416_11na_ratetable; | ||
| 492 | sc->hw_rate_table[ATH9K_MODE_11NG_HT20] = &ar5416_11ng_ratetable; | ||
| 493 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS] = | ||
| 494 | &ar5416_11na_ratetable; | ||
| 495 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS] = | ||
| 496 | &ar5416_11na_ratetable; | ||
| 497 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS] = | ||
| 498 | &ar5416_11ng_ratetable; | ||
| 499 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS] = | ||
| 500 | &ar5416_11ng_ratetable; | ||
| 501 | } | ||
| 502 | |||
| 503 | static void ar5416_setquarter_ratetable(struct ath_rate_softc *sc) | ||
| 504 | { | ||
| 505 | sc->hw_rate_table[ATH9K_MODE_11A] = &ar5416_11a_ratetable_Quarter; | ||
| 506 | return; | ||
| 507 | } | ||
| 508 | |||
| 509 | static void ar5416_sethalf_ratetable(struct ath_rate_softc *sc) | ||
| 510 | { | ||
| 511 | sc->hw_rate_table[ATH9K_MODE_11A] = &ar5416_11a_ratetable_Half; | ||
| 512 | return; | ||
| 513 | } | ||
| 514 | |||
| 515 | static void ar5416_setfull_ratetable(struct ath_rate_softc *sc) | ||
| 516 | { | ||
| 517 | sc->hw_rate_table[ATH9K_MODE_11A] = &ar5416_11a_ratetable; | ||
| 518 | return; | ||
| 519 | } | ||
| 520 | |||
| 521 | /* | ||
| 522 | * Return the median of three numbers | ||
| 523 | */ | ||
| 524 | static inline int8_t median(int8_t a, int8_t b, int8_t c) | ||
| 525 | { | ||
| 526 | if (a >= b) { | ||
| 527 | if (b >= c) | ||
| 528 | return b; | ||
| 529 | else if (a > c) | ||
| 530 | return c; | ||
| 531 | else | ||
| 532 | return a; | ||
| 533 | } else { | ||
| 534 | if (a >= c) | ||
| 535 | return a; | ||
| 536 | else if (b >= c) | ||
| 537 | return c; | ||
| 538 | else | ||
| 539 | return b; | ||
| 540 | } | ||
| 541 | } | ||
| 542 | |||
| 543 | static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table, | ||
| 544 | struct ath_tx_ratectrl *rate_ctrl) | ||
| 545 | { | ||
| 546 | u8 i, j, idx, idx_next; | ||
| 547 | |||
| 548 | for (i = rate_ctrl->max_valid_rate - 1; i > 0; i--) { | ||
| 549 | for (j = 0; j <= i-1; j++) { | ||
| 550 | idx = rate_ctrl->valid_rate_index[j]; | ||
| 551 | idx_next = rate_ctrl->valid_rate_index[j+1]; | ||
| 552 | |||
| 553 | if (rate_table->info[idx].ratekbps > | ||
| 554 | rate_table->info[idx_next].ratekbps) { | ||
| 555 | rate_ctrl->valid_rate_index[j] = idx_next; | ||
| 556 | rate_ctrl->valid_rate_index[j+1] = idx; | ||
| 557 | } | ||
| 558 | } | ||
| 559 | } | ||
| 560 | } | ||
| 561 | |||
| 562 | /* Access functions for valid_txrate_mask */ | ||
| 563 | |||
| 564 | static void ath_rc_init_valid_txmask(struct ath_tx_ratectrl *rate_ctrl) | ||
| 565 | { | ||
| 566 | u8 i; | ||
| 567 | |||
| 568 | for (i = 0; i < rate_ctrl->rate_table_size; i++) | ||
| 569 | rate_ctrl->valid_rate_index[i] = FALSE; | ||
| 570 | } | ||
| 571 | |||
| 572 | static inline void ath_rc_set_valid_txmask(struct ath_tx_ratectrl *rate_ctrl, | ||
| 573 | u8 index, int valid_tx_rate) | ||
| 574 | { | ||
| 575 | ASSERT(index <= rate_ctrl->rate_table_size); | ||
| 576 | rate_ctrl->valid_rate_index[index] = valid_tx_rate ? TRUE : FALSE; | ||
| 577 | } | ||
| 578 | |||
| 579 | static inline int ath_rc_isvalid_txmask(struct ath_tx_ratectrl *rate_ctrl, | ||
| 580 | u8 index) | ||
| 581 | { | ||
| 582 | ASSERT(index <= rate_ctrl->rate_table_size); | ||
| 583 | return rate_ctrl->valid_rate_index[index]; | ||
| 584 | } | ||
| 585 | |||
| 586 | /* Iterators for valid_txrate_mask */ | ||
| 587 | static inline int | ||
| 588 | ath_rc_get_nextvalid_txrate(const struct ath_rate_table *rate_table, | ||
| 589 | struct ath_tx_ratectrl *rate_ctrl, | ||
| 590 | u8 cur_valid_txrate, | ||
| 591 | u8 *next_idx) | ||
| 592 | { | ||
| 593 | u8 i; | ||
| 594 | |||
| 595 | for (i = 0; i < rate_ctrl->max_valid_rate - 1; i++) { | ||
| 596 | if (rate_ctrl->valid_rate_index[i] == cur_valid_txrate) { | ||
| 597 | *next_idx = rate_ctrl->valid_rate_index[i+1]; | ||
| 598 | return TRUE; | ||
| 599 | } | ||
| 600 | } | ||
| 601 | |||
| 602 | /* No more valid rates */ | ||
| 603 | *next_idx = 0; | ||
| 604 | return FALSE; | ||
| 605 | } | ||
| 606 | |||
| 607 | /* Return true only for single stream */ | ||
| 608 | |||
| 609 | static int ath_rc_valid_phyrate(u32 phy, u32 capflag, int ignore_cw) | ||
| 610 | { | ||
| 611 | if (WLAN_RC_PHY_HT(phy) & !(capflag & WLAN_RC_HT_FLAG)) | ||
| 612 | return FALSE; | ||
| 613 | if (WLAN_RC_PHY_DS(phy) && !(capflag & WLAN_RC_DS_FLAG)) | ||
| 614 | return FALSE; | ||
| 615 | if (WLAN_RC_PHY_SGI(phy) && !(capflag & WLAN_RC_SGI_FLAG)) | ||
| 616 | return FALSE; | ||
| 617 | if (!ignore_cw && WLAN_RC_PHY_HT(phy)) | ||
| 618 | if (WLAN_RC_PHY_40(phy) && !(capflag & WLAN_RC_40_FLAG)) | ||
| 619 | return FALSE; | ||
| 620 | if (!WLAN_RC_PHY_40(phy) && (capflag & WLAN_RC_40_FLAG)) | ||
| 621 | return FALSE; | ||
| 622 | return TRUE; | ||
| 623 | } | ||
| 624 | |||
| 625 | static inline int | ||
| 626 | ath_rc_get_nextlowervalid_txrate(const struct ath_rate_table *rate_table, | ||
| 627 | struct ath_tx_ratectrl *rate_ctrl, | ||
| 628 | u8 cur_valid_txrate, u8 *next_idx) | ||
| 629 | { | ||
| 630 | int8_t i; | ||
| 631 | |||
| 632 | for (i = 1; i < rate_ctrl->max_valid_rate ; i++) { | ||
| 633 | if (rate_ctrl->valid_rate_index[i] == cur_valid_txrate) { | ||
| 634 | *next_idx = rate_ctrl->valid_rate_index[i-1]; | ||
| 635 | return TRUE; | ||
| 636 | } | ||
| 637 | } | ||
| 638 | return FALSE; | ||
| 639 | } | ||
| 640 | |||
| 641 | /* | ||
| 642 | * Initialize the Valid Rate Index from valid entries in Rate Table | ||
| 643 | */ | ||
| 644 | static u8 | ||
| 645 | ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv, | ||
| 646 | const struct ath_rate_table *rate_table, | ||
| 647 | u32 capflag) | ||
| 648 | { | ||
| 649 | struct ath_tx_ratectrl *rate_ctrl; | ||
| 650 | u8 i, hi = 0; | ||
| 651 | u32 valid; | ||
| 652 | |||
| 653 | rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 654 | for (i = 0; i < rate_table->rate_cnt; i++) { | ||
| 655 | valid = (ath_rc_priv->single_stream ? | ||
| 656 | rate_table->info[i].valid_single_stream : | ||
| 657 | rate_table->info[i].valid); | ||
| 658 | if (valid == TRUE) { | ||
| 659 | u32 phy = rate_table->info[i].phy; | ||
| 660 | u8 valid_rate_count = 0; | ||
| 661 | |||
| 662 | if (!ath_rc_valid_phyrate(phy, capflag, FALSE)) | ||
| 663 | continue; | ||
| 664 | |||
| 665 | valid_rate_count = rate_ctrl->valid_phy_ratecnt[phy]; | ||
| 666 | |||
| 667 | rate_ctrl->valid_phy_rateidx[phy][valid_rate_count] = i; | ||
| 668 | rate_ctrl->valid_phy_ratecnt[phy] += 1; | ||
| 669 | ath_rc_set_valid_txmask(rate_ctrl, i, TRUE); | ||
| 670 | hi = A_MAX(hi, i); | ||
| 671 | } | ||
| 672 | } | ||
| 673 | return hi; | ||
| 674 | } | ||
| 675 | |||
| 676 | /* | ||
| 677 | * Initialize the Valid Rate Index from Rate Set | ||
| 678 | */ | ||
| 679 | static u8 | ||
| 680 | ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv, | ||
| 681 | const struct ath_rate_table *rate_table, | ||
| 682 | struct ath_rateset *rateset, | ||
| 683 | u32 capflag) | ||
| 684 | { | ||
| 685 | /* XXX: Clean me up and make identation friendly */ | ||
| 686 | u8 i, j, hi = 0; | ||
| 687 | struct ath_tx_ratectrl *rate_ctrl = | ||
| 688 | (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 689 | |||
| 690 | /* Use intersection of working rates and valid rates */ | ||
| 691 | for (i = 0; i < rateset->rs_nrates; i++) { | ||
| 692 | for (j = 0; j < rate_table->rate_cnt; j++) { | ||
| 693 | u32 phy = rate_table->info[j].phy; | ||
| 694 | u32 valid = (ath_rc_priv->single_stream ? | ||
| 695 | rate_table->info[j].valid_single_stream : | ||
| 696 | rate_table->info[j].valid); | ||
| 697 | |||
| 698 | /* We allow a rate only if its valid and the | ||
| 699 | * capflag matches one of the validity | ||
| 700 | * (TRUE/TRUE_20/TRUE_40) flags */ | ||
| 701 | |||
| 702 | /* XXX: catch the negative of this branch | ||
| 703 | * first and then continue */ | ||
| 704 | if (((rateset->rs_rates[i] & 0x7F) == | ||
| 705 | (rate_table->info[j].dot11rate & 0x7F)) && | ||
| 706 | ((valid & WLAN_RC_CAP_MODE(capflag)) == | ||
| 707 | WLAN_RC_CAP_MODE(capflag)) && | ||
| 708 | !WLAN_RC_PHY_HT(phy)) { | ||
| 709 | |||
| 710 | u8 valid_rate_count = 0; | ||
| 711 | |||
| 712 | if (!ath_rc_valid_phyrate(phy, capflag, FALSE)) | ||
| 713 | continue; | ||
| 714 | |||
| 715 | valid_rate_count = | ||
| 716 | rate_ctrl->valid_phy_ratecnt[phy]; | ||
| 717 | |||
| 718 | rate_ctrl->valid_phy_rateidx[phy] | ||
| 719 | [valid_rate_count] = j; | ||
| 720 | rate_ctrl->valid_phy_ratecnt[phy] += 1; | ||
| 721 | ath_rc_set_valid_txmask(rate_ctrl, j, TRUE); | ||
| 722 | hi = A_MAX(hi, j); | ||
| 723 | } | ||
| 724 | } | ||
| 725 | } | ||
| 726 | return hi; | ||
| 727 | } | ||
| 728 | |||
| 729 | static u8 | ||
| 730 | ath_rc_sib_setvalid_htrates(struct ath_rate_node *ath_rc_priv, | ||
| 731 | const struct ath_rate_table *rate_table, | ||
| 732 | u8 *mcs_set, u32 capflag) | ||
| 733 | { | ||
| 734 | u8 i, j, hi = 0; | ||
| 735 | struct ath_tx_ratectrl *rate_ctrl = | ||
| 736 | (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 737 | |||
| 738 | /* Use intersection of working rates and valid rates */ | ||
| 739 | for (i = 0; i < ((struct ath_rateset *)mcs_set)->rs_nrates; i++) { | ||
| 740 | for (j = 0; j < rate_table->rate_cnt; j++) { | ||
| 741 | u32 phy = rate_table->info[j].phy; | ||
| 742 | u32 valid = (ath_rc_priv->single_stream ? | ||
| 743 | rate_table->info[j].valid_single_stream : | ||
| 744 | rate_table->info[j].valid); | ||
| 745 | |||
| 746 | if (((((struct ath_rateset *) | ||
| 747 | mcs_set)->rs_rates[i] & 0x7F) != | ||
| 748 | (rate_table->info[j].dot11rate & 0x7F)) || | ||
| 749 | !WLAN_RC_PHY_HT(phy) || | ||
| 750 | !WLAN_RC_PHY_HT_VALID(valid, capflag)) | ||
| 751 | continue; | ||
| 752 | |||
| 753 | if (!ath_rc_valid_phyrate(phy, capflag, FALSE)) | ||
| 754 | continue; | ||
| 755 | |||
| 756 | rate_ctrl->valid_phy_rateidx[phy] | ||
| 757 | [rate_ctrl->valid_phy_ratecnt[phy]] = j; | ||
| 758 | rate_ctrl->valid_phy_ratecnt[phy] += 1; | ||
| 759 | ath_rc_set_valid_txmask(rate_ctrl, j, TRUE); | ||
| 760 | hi = A_MAX(hi, j); | ||
| 761 | } | ||
| 762 | } | ||
| 763 | return hi; | ||
| 764 | } | ||
| 765 | |||
| 766 | /* | ||
| 767 | * Attach to a device instance. Setup the public definition | ||
| 768 | * of how much per-node space we need and setup the private | ||
| 769 | * phy tables that have rate control parameters. | ||
| 770 | */ | ||
| 771 | struct ath_rate_softc *ath_rate_attach(struct ath_hal *ah) | ||
| 772 | { | ||
| 773 | struct ath_rate_softc *asc; | ||
| 774 | |||
| 775 | /* we are only in user context so we can sleep for memory */ | ||
| 776 | asc = kzalloc(sizeof(struct ath_rate_softc), GFP_KERNEL); | ||
| 777 | if (asc == NULL) | ||
| 778 | return NULL; | ||
| 779 | |||
| 780 | ar5416_attach_ratetables(asc); | ||
| 781 | |||
| 782 | /* Save Maximum TX Trigger Level (used for 11n) */ | ||
| 783 | tx_triglevel_max = ah->ah_caps.tx_triglevel_max; | ||
| 784 | /* return alias for ath_rate_softc * */ | ||
| 785 | return asc; | ||
| 786 | } | ||
| 787 | |||
| 788 | static struct ath_rate_node *ath_rate_node_alloc(struct ath_vap *avp, | ||
| 789 | struct ath_rate_softc *rsc, | ||
| 790 | gfp_t gfp) | ||
| 791 | { | ||
| 792 | struct ath_rate_node *anode; | ||
| 793 | |||
| 794 | anode = kzalloc(sizeof(struct ath_rate_node), gfp); | ||
| 795 | if (anode == NULL) | ||
| 796 | return NULL; | ||
| 797 | |||
| 798 | anode->avp = avp; | ||
| 799 | anode->asc = rsc; | ||
| 800 | avp->rc_node = anode; | ||
| 801 | |||
| 802 | return anode; | ||
| 803 | } | ||
| 804 | |||
| 805 | static void ath_rate_node_free(struct ath_rate_node *anode) | ||
| 806 | { | ||
| 807 | if (anode != NULL) | ||
| 808 | kfree(anode); | ||
| 809 | } | ||
| 810 | |||
| 811 | void ath_rate_detach(struct ath_rate_softc *asc) | ||
| 812 | { | ||
| 813 | if (asc != NULL) | ||
| 814 | kfree(asc); | ||
| 815 | } | ||
| 816 | |||
| 817 | u8 ath_rate_findrateix(struct ath_softc *sc, | ||
| 818 | u8 dot11rate) | ||
| 819 | { | ||
| 820 | const struct ath_rate_table *ratetable; | ||
| 821 | struct ath_rate_softc *rsc = sc->sc_rc; | ||
| 822 | int i; | ||
| 823 | |||
| 824 | ratetable = rsc->hw_rate_table[sc->sc_curmode]; | ||
| 825 | |||
| 826 | if (WARN_ON(!ratetable)) | ||
| 827 | return 0; | ||
| 828 | |||
| 829 | for (i = 0; i < ratetable->rate_cnt; i++) { | ||
| 830 | if ((ratetable->info[i].dot11rate & 0x7f) == (dot11rate & 0x7f)) | ||
| 831 | return i; | ||
| 832 | } | ||
| 833 | |||
| 834 | return 0; | ||
| 835 | } | ||
| 836 | |||
| 837 | /* | ||
| 838 | * Update rate-control state on a device state change. When | ||
| 839 | * operating as a station this includes associate/reassociate | ||
| 840 | * with an AP. Otherwise this gets called, for example, when | ||
| 841 | * the we transition to run state when operating as an AP. | ||
| 842 | */ | ||
| 843 | void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp) | ||
| 844 | { | ||
| 845 | struct ath_rate_softc *asc = sc->sc_rc; | ||
| 846 | |||
| 847 | /* For half and quarter rate channles use different | ||
| 848 | * rate tables | ||
| 849 | */ | ||
| 850 | if (sc->sc_curchan.channelFlags & CHANNEL_HALF) | ||
| 851 | ar5416_sethalf_ratetable(asc); | ||
| 852 | else if (sc->sc_curchan.channelFlags & CHANNEL_QUARTER) | ||
| 853 | ar5416_setquarter_ratetable(asc); | ||
| 854 | else /* full rate */ | ||
| 855 | ar5416_setfull_ratetable(asc); | ||
| 856 | |||
| 857 | if (avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE) { | ||
| 858 | asc->fixedrix = | ||
| 859 | sc->sc_rixmap[avp->av_config.av_fixed_rateset & 0xff]; | ||
| 860 | /* NB: check the fixed rate exists */ | ||
| 861 | if (asc->fixedrix == 0xff) | ||
| 862 | asc->fixedrix = IEEE80211_FIXED_RATE_NONE; | ||
| 863 | } else { | ||
| 864 | asc->fixedrix = IEEE80211_FIXED_RATE_NONE; | ||
| 865 | } | ||
| 866 | } | ||
| 867 | |||
| 868 | static u8 ath_rc_ratefind_ht(struct ath_softc *sc, | ||
| 869 | struct ath_rate_node *ath_rc_priv, | ||
| 870 | const struct ath_rate_table *rate_table, | ||
| 871 | int probe_allowed, int *is_probing, | ||
| 872 | int is_retry) | ||
| 873 | { | ||
| 874 | u32 dt, best_thruput, this_thruput, now_msec; | ||
| 875 | u8 rate, next_rate, best_rate, maxindex, minindex; | ||
| 876 | int8_t rssi_last, rssi_reduce = 0, index = 0; | ||
| 877 | struct ath_tx_ratectrl *rate_ctrl = NULL; | ||
| 878 | |||
| 879 | rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv ? | ||
| 880 | (ath_rc_priv) : NULL); | ||
| 881 | |||
| 882 | *is_probing = FALSE; | ||
| 883 | |||
| 884 | rssi_last = median(rate_ctrl->rssi_last, | ||
| 885 | rate_ctrl->rssi_last_prev, | ||
| 886 | rate_ctrl->rssi_last_prev2); | ||
| 887 | |||
| 888 | /* | ||
| 889 | * Age (reduce) last ack rssi based on how old it is. | ||
| 890 | * The bizarre numbers are so the delta is 160msec, | ||
| 891 | * meaning we divide by 16. | ||
| 892 | * 0msec <= dt <= 25msec: don't derate | ||
| 893 | * 25msec <= dt <= 185msec: derate linearly from 0 to 10dB | ||
| 894 | * 185msec <= dt: derate by 10dB | ||
| 895 | */ | ||
| 896 | |||
| 897 | now_msec = jiffies_to_msecs(jiffies); | ||
| 898 | dt = now_msec - rate_ctrl->rssi_time; | ||
| 899 | |||
| 900 | if (dt >= 185) | ||
| 901 | rssi_reduce = 10; | ||
| 902 | else if (dt >= 25) | ||
| 903 | rssi_reduce = (u8)((dt - 25) >> 4); | ||
| 904 | |||
| 905 | /* Now reduce rssi_last by rssi_reduce */ | ||
| 906 | if (rssi_last < rssi_reduce) | ||
| 907 | rssi_last = 0; | ||
| 908 | else | ||
| 909 | rssi_last -= rssi_reduce; | ||
| 910 | |||
| 911 | /* | ||
| 912 | * Now look up the rate in the rssi table and return it. | ||
| 913 | * If no rates match then we return 0 (lowest rate) | ||
| 914 | */ | ||
| 915 | |||
| 916 | best_thruput = 0; | ||
| 917 | maxindex = rate_ctrl->max_valid_rate-1; | ||
| 918 | |||
| 919 | minindex = 0; | ||
| 920 | best_rate = minindex; | ||
| 921 | |||
| 922 | /* | ||
| 923 | * Try the higher rate first. It will reduce memory moving time | ||
| 924 | * if we have very good channel characteristics. | ||
| 925 | */ | ||
| 926 | for (index = maxindex; index >= minindex ; index--) { | ||
| 927 | u8 per_thres; | ||
| 928 | |||
| 929 | rate = rate_ctrl->valid_rate_index[index]; | ||
| 930 | if (rate > rate_ctrl->rate_max_phy) | ||
| 931 | continue; | ||
| 932 | |||
| 933 | /* | ||
| 934 | * For TCP the average collision rate is around 11%, | ||
| 935 | * so we ignore PERs less than this. This is to | ||
| 936 | * prevent the rate we are currently using (whose | ||
| 937 | * PER might be in the 10-15 range because of TCP | ||
| 938 | * collisions) looking worse than the next lower | ||
| 939 | * rate whose PER has decayed close to 0. If we | ||
| 940 | * used to next lower rate, its PER would grow to | ||
| 941 | * 10-15 and we would be worse off then staying | ||
| 942 | * at the current rate. | ||
| 943 | */ | ||
| 944 | per_thres = rate_ctrl->state[rate].per; | ||
| 945 | if (per_thres < 12) | ||
| 946 | per_thres = 12; | ||
| 947 | |||
| 948 | this_thruput = rate_table->info[rate].user_ratekbps * | ||
| 949 | (100 - per_thres); | ||
| 950 | |||
| 951 | if (best_thruput <= this_thruput) { | ||
| 952 | best_thruput = this_thruput; | ||
| 953 | best_rate = rate; | ||
| 954 | } | ||
| 955 | } | ||
| 956 | |||
| 957 | rate = best_rate; | ||
| 958 | |||
| 959 | /* if we are retrying for more than half the number | ||
| 960 | * of max retries, use the min rate for the next retry | ||
| 961 | */ | ||
| 962 | if (is_retry) | ||
| 963 | rate = rate_ctrl->valid_rate_index[minindex]; | ||
| 964 | |||
| 965 | rate_ctrl->rssi_last_lookup = rssi_last; | ||
| 966 | |||
| 967 | /* | ||
| 968 | * Must check the actual rate (ratekbps) to account for | ||
| 969 | * non-monoticity of 11g's rate table | ||
| 970 | */ | ||
| 971 | |||
| 972 | if (rate >= rate_ctrl->rate_max_phy && probe_allowed) { | ||
| 973 | rate = rate_ctrl->rate_max_phy; | ||
| 974 | |||
| 975 | /* Probe the next allowed phy state */ | ||
| 976 | /* FIXME:XXXX Check to make sure ratMax is checked properly */ | ||
| 977 | if (ath_rc_get_nextvalid_txrate(rate_table, | ||
| 978 | rate_ctrl, rate, &next_rate) && | ||
| 979 | (now_msec - rate_ctrl->probe_time > | ||
| 980 | rate_table->probe_interval) && | ||
| 981 | (rate_ctrl->hw_maxretry_pktcnt >= 1)) { | ||
| 982 | rate = next_rate; | ||
| 983 | rate_ctrl->probe_rate = rate; | ||
| 984 | rate_ctrl->probe_time = now_msec; | ||
| 985 | rate_ctrl->hw_maxretry_pktcnt = 0; | ||
| 986 | *is_probing = TRUE; | ||
| 987 | } | ||
| 988 | } | ||
| 989 | |||
| 990 | /* | ||
| 991 | * Make sure rate is not higher than the allowed maximum. | ||
| 992 | * We should also enforce the min, but I suspect the min is | ||
| 993 | * normally 1 rather than 0 because of the rate 9 vs 6 issue | ||
| 994 | * in the old code. | ||
| 995 | */ | ||
| 996 | if (rate > (rate_ctrl->rate_table_size - 1)) | ||
| 997 | rate = rate_ctrl->rate_table_size - 1; | ||
| 998 | |||
| 999 | ASSERT((rate_table->info[rate].valid && !ath_rc_priv->single_stream) || | ||
| 1000 | (rate_table->info[rate].valid_single_stream && | ||
| 1001 | ath_rc_priv->single_stream)); | ||
| 1002 | |||
| 1003 | return rate; | ||
| 1004 | } | ||
| 1005 | |||
| 1006 | static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table , | ||
| 1007 | struct ath_rc_series *series, | ||
| 1008 | u8 tries, | ||
| 1009 | u8 rix, | ||
| 1010 | int rtsctsenable) | ||
| 1011 | { | ||
| 1012 | series->tries = tries; | ||
| 1013 | series->flags = (rtsctsenable ? ATH_RC_RTSCTS_FLAG : 0) | | ||
| 1014 | (WLAN_RC_PHY_DS(rate_table->info[rix].phy) ? | ||
| 1015 | ATH_RC_DS_FLAG : 0) | | ||
| 1016 | (WLAN_RC_PHY_40(rate_table->info[rix].phy) ? | ||
| 1017 | ATH_RC_CW40_FLAG : 0) | | ||
| 1018 | (WLAN_RC_PHY_SGI(rate_table->info[rix].phy) ? | ||
| 1019 | ATH_RC_SGI_FLAG : 0); | ||
| 1020 | |||
| 1021 | series->rix = rate_table->info[rix].base_index; | ||
| 1022 | series->max_4ms_framelen = rate_table->info[rix].max_4ms_framelen; | ||
| 1023 | } | ||
| 1024 | |||
| 1025 | static u8 ath_rc_rate_getidx(struct ath_softc *sc, | ||
| 1026 | struct ath_rate_node *ath_rc_priv, | ||
| 1027 | const struct ath_rate_table *rate_table, | ||
| 1028 | u8 rix, u16 stepdown, | ||
| 1029 | u16 min_rate) | ||
| 1030 | { | ||
| 1031 | u32 j; | ||
| 1032 | u8 nextindex; | ||
| 1033 | struct ath_tx_ratectrl *rate_ctrl = | ||
| 1034 | (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 1035 | |||
| 1036 | if (min_rate) { | ||
| 1037 | for (j = RATE_TABLE_SIZE; j > 0; j--) { | ||
| 1038 | if (ath_rc_get_nextlowervalid_txrate(rate_table, | ||
| 1039 | rate_ctrl, rix, &nextindex)) | ||
| 1040 | rix = nextindex; | ||
| 1041 | else | ||
| 1042 | break; | ||
| 1043 | } | ||
| 1044 | } else { | ||
| 1045 | for (j = stepdown; j > 0; j--) { | ||
| 1046 | if (ath_rc_get_nextlowervalid_txrate(rate_table, | ||
| 1047 | rate_ctrl, rix, &nextindex)) | ||
| 1048 | rix = nextindex; | ||
| 1049 | else | ||
| 1050 | break; | ||
| 1051 | } | ||
| 1052 | } | ||
| 1053 | return rix; | ||
| 1054 | } | ||
| 1055 | |||
| 1056 | static void ath_rc_ratefind(struct ath_softc *sc, | ||
| 1057 | struct ath_rate_node *ath_rc_priv, | ||
| 1058 | int num_tries, int num_rates, unsigned int rcflag, | ||
| 1059 | struct ath_rc_series series[], int *is_probe, | ||
| 1060 | int is_retry) | ||
| 1061 | { | ||
| 1062 | u8 try_per_rate = 0, i = 0, rix, nrix; | ||
| 1063 | struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc; | ||
| 1064 | struct ath_rate_table *rate_table; | ||
| 1065 | |||
| 1066 | rate_table = | ||
| 1067 | (struct ath_rate_table *)asc->hw_rate_table[sc->sc_curmode]; | ||
| 1068 | rix = ath_rc_ratefind_ht(sc, ath_rc_priv, rate_table, | ||
| 1069 | (rcflag & ATH_RC_PROBE_ALLOWED) ? 1 : 0, | ||
| 1070 | is_probe, is_retry); | ||
| 1071 | nrix = rix; | ||
| 1072 | |||
| 1073 | if ((rcflag & ATH_RC_PROBE_ALLOWED) && (*is_probe)) { | ||
| 1074 | /* set one try for probe rates. For the | ||
| 1075 | * probes don't enable rts */ | ||
| 1076 | ath_rc_rate_set_series(rate_table, | ||
| 1077 | &series[i++], 1, nrix, FALSE); | ||
| 1078 | |||
| 1079 | try_per_rate = (num_tries/num_rates); | ||
| 1080 | /* Get the next tried/allowed rate. No RTS for the next series | ||
| 1081 | * after the probe rate | ||
| 1082 | */ | ||
| 1083 | nrix = ath_rc_rate_getidx(sc, | ||
| 1084 | ath_rc_priv, rate_table, nrix, 1, FALSE); | ||
| 1085 | ath_rc_rate_set_series(rate_table, | ||
| 1086 | &series[i++], try_per_rate, nrix, 0); | ||
| 1087 | } else { | ||
| 1088 | try_per_rate = (num_tries/num_rates); | ||
| 1089 | /* Set the choosen rate. No RTS for first series entry. */ | ||
| 1090 | ath_rc_rate_set_series(rate_table, | ||
| 1091 | &series[i++], try_per_rate, nrix, FALSE); | ||
| 1092 | } | ||
| 1093 | |||
| 1094 | /* Fill in the other rates for multirate retry */ | ||
| 1095 | for ( ; i < num_rates; i++) { | ||
| 1096 | u8 try_num; | ||
| 1097 | u8 min_rate; | ||
| 1098 | |||
| 1099 | try_num = ((i + 1) == num_rates) ? | ||
| 1100 | num_tries - (try_per_rate * i) : try_per_rate ; | ||
| 1101 | min_rate = (((i + 1) == num_rates) && | ||
| 1102 | (rcflag & ATH_RC_MINRATE_LASTRATE)) ? 1 : 0; | ||
| 1103 | |||
| 1104 | nrix = ath_rc_rate_getidx(sc, ath_rc_priv, | ||
| 1105 | rate_table, nrix, 1, min_rate); | ||
| 1106 | /* All other rates in the series have RTS enabled */ | ||
| 1107 | ath_rc_rate_set_series(rate_table, | ||
| 1108 | &series[i], try_num, nrix, TRUE); | ||
| 1109 | } | ||
| 1110 | |||
| 1111 | /* | ||
| 1112 | * NB:Change rate series to enable aggregation when operating | ||
| 1113 | * at lower MCS rates. When first rate in series is MCS2 | ||
| 1114 | * in HT40 @ 2.4GHz, series should look like: | ||
| 1115 | * | ||
| 1116 | * {MCS2, MCS1, MCS0, MCS0}. | ||
| 1117 | * | ||
| 1118 | * When first rate in series is MCS3 in HT20 @ 2.4GHz, series should | ||
| 1119 | * look like: | ||
| 1120 | * | ||
| 1121 | * {MCS3, MCS2, MCS1, MCS1} | ||
| 1122 | * | ||
| 1123 | * So, set fourth rate in series to be same as third one for | ||
| 1124 | * above conditions. | ||
| 1125 | */ | ||
| 1126 | if ((sc->sc_curmode == ATH9K_MODE_11NG_HT20) || | ||
| 1127 | (sc->sc_curmode == ATH9K_MODE_11NG_HT40PLUS) || | ||
| 1128 | (sc->sc_curmode == ATH9K_MODE_11NG_HT40MINUS)) { | ||
| 1129 | u8 dot11rate = rate_table->info[rix].dot11rate; | ||
| 1130 | u8 phy = rate_table->info[rix].phy; | ||
| 1131 | if (i == 4 && | ||
| 1132 | ((dot11rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) || | ||
| 1133 | (dot11rate == 3 && phy == WLAN_RC_PHY_HT_20_SS))) { | ||
| 1134 | series[3].rix = series[2].rix; | ||
| 1135 | series[3].flags = series[2].flags; | ||
| 1136 | series[3].max_4ms_framelen = series[2].max_4ms_framelen; | ||
| 1137 | } | ||
| 1138 | } | ||
| 1139 | } | ||
| 1140 | |||
| 1141 | /* | ||
| 1142 | * Return the Tx rate series. | ||
| 1143 | */ | ||
| 1144 | void ath_rate_findrate(struct ath_softc *sc, | ||
| 1145 | struct ath_rate_node *ath_rc_priv, | ||
| 1146 | int num_tries, | ||
| 1147 | int num_rates, | ||
| 1148 | unsigned int rcflag, | ||
| 1149 | struct ath_rc_series series[], | ||
| 1150 | int *is_probe, | ||
| 1151 | int is_retry) | ||
| 1152 | { | ||
| 1153 | struct ath_vap *avp = ath_rc_priv->avp; | ||
| 1154 | |||
| 1155 | DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); | ||
| 1156 | if (!num_rates || !num_tries) | ||
| 1157 | return; | ||
| 1158 | |||
| 1159 | if (avp->av_config.av_fixed_rateset == IEEE80211_FIXED_RATE_NONE) { | ||
| 1160 | ath_rc_ratefind(sc, ath_rc_priv, num_tries, num_rates, | ||
| 1161 | rcflag, series, is_probe, is_retry); | ||
| 1162 | } else { | ||
| 1163 | /* Fixed rate */ | ||
| 1164 | int idx; | ||
| 1165 | u8 flags; | ||
| 1166 | u32 rix; | ||
| 1167 | struct ath_rate_softc *asc = ath_rc_priv->asc; | ||
| 1168 | struct ath_rate_table *rate_table; | ||
| 1169 | |||
| 1170 | rate_table = (struct ath_rate_table *) | ||
| 1171 | asc->hw_rate_table[sc->sc_curmode]; | ||
| 1172 | |||
| 1173 | for (idx = 0; idx < 4; idx++) { | ||
| 1174 | unsigned int mcs; | ||
| 1175 | u8 series_rix = 0; | ||
| 1176 | |||
| 1177 | series[idx].tries = | ||
| 1178 | IEEE80211_RATE_IDX_ENTRY( | ||
| 1179 | avp->av_config.av_fixed_retryset, idx); | ||
| 1180 | |||
| 1181 | mcs = IEEE80211_RATE_IDX_ENTRY( | ||
| 1182 | avp->av_config.av_fixed_rateset, idx); | ||
| 1183 | |||
| 1184 | if (idx == 3 && (mcs & 0xf0) == 0x70) | ||
| 1185 | mcs = (mcs & ~0xf0)|0x80; | ||
| 1186 | |||
| 1187 | if (!(mcs & 0x80)) | ||
| 1188 | flags = 0; | ||
| 1189 | else | ||
| 1190 | flags = ((ath_rc_priv->ht_cap & | ||
| 1191 | WLAN_RC_DS_FLAG) ? | ||
| 1192 | ATH_RC_DS_FLAG : 0) | | ||
| 1193 | ((ath_rc_priv->ht_cap & | ||
| 1194 | WLAN_RC_40_FLAG) ? | ||
| 1195 | ATH_RC_CW40_FLAG : 0) | | ||
| 1196 | ((ath_rc_priv->ht_cap & | ||
| 1197 | WLAN_RC_SGI_FLAG) ? | ||
| 1198 | ((ath_rc_priv->ht_cap & | ||
| 1199 | WLAN_RC_40_FLAG) ? | ||
| 1200 | ATH_RC_SGI_FLAG : 0) : 0); | ||
| 1201 | |||
| 1202 | series[idx].rix = sc->sc_rixmap[mcs]; | ||
| 1203 | series_rix = series[idx].rix; | ||
| 1204 | |||
| 1205 | /* XXX: Give me some cleanup love */ | ||
| 1206 | if ((flags & ATH_RC_CW40_FLAG) && | ||
| 1207 | (flags & ATH_RC_SGI_FLAG)) | ||
| 1208 | rix = rate_table->info[series_rix].ht_index; | ||
| 1209 | else if (flags & ATH_RC_SGI_FLAG) | ||
| 1210 | rix = rate_table->info[series_rix].sgi_index; | ||
| 1211 | else if (flags & ATH_RC_CW40_FLAG) | ||
| 1212 | rix = rate_table->info[series_rix].cw40index; | ||
| 1213 | else | ||
| 1214 | rix = rate_table->info[series_rix].base_index; | ||
| 1215 | series[idx].max_4ms_framelen = | ||
| 1216 | rate_table->info[rix].max_4ms_framelen; | ||
| 1217 | series[idx].flags = flags; | ||
| 1218 | } | ||
| 1219 | } | ||
| 1220 | } | ||
| 1221 | |||
| 1222 | static void ath_rc_update_ht(struct ath_softc *sc, | ||
| 1223 | struct ath_rate_node *ath_rc_priv, | ||
| 1224 | struct ath_tx_info_priv *info_priv, | ||
| 1225 | int tx_rate, int xretries, int retries) | ||
| 1226 | { | ||
| 1227 | struct ath_tx_ratectrl *rate_ctrl; | ||
| 1228 | u32 now_msec = jiffies_to_msecs(jiffies); | ||
| 1229 | int state_change = FALSE, rate, count; | ||
| 1230 | u8 last_per; | ||
| 1231 | struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc; | ||
| 1232 | struct ath_rate_table *rate_table = | ||
| 1233 | (struct ath_rate_table *)asc->hw_rate_table[sc->sc_curmode]; | ||
| 1234 | |||
| 1235 | static u32 nretry_to_per_lookup[10] = { | ||
| 1236 | 100 * 0 / 1, | ||
| 1237 | 100 * 1 / 4, | ||
| 1238 | 100 * 1 / 2, | ||
| 1239 | 100 * 3 / 4, | ||
| 1240 | 100 * 4 / 5, | ||
| 1241 | 100 * 5 / 6, | ||
| 1242 | 100 * 6 / 7, | ||
| 1243 | 100 * 7 / 8, | ||
| 1244 | 100 * 8 / 9, | ||
| 1245 | 100 * 9 / 10 | ||
| 1246 | }; | ||
| 1247 | |||
| 1248 | if (!ath_rc_priv) | ||
| 1249 | return; | ||
| 1250 | |||
| 1251 | rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 1252 | |||
| 1253 | ASSERT(tx_rate >= 0); | ||
| 1254 | if (tx_rate < 0) | ||
| 1255 | return; | ||
| 1256 | |||
| 1257 | /* To compensate for some imbalance between ctrl and ext. channel */ | ||
| 1258 | |||
| 1259 | if (WLAN_RC_PHY_40(rate_table->info[tx_rate].phy)) | ||
| 1260 | info_priv->tx.ts_rssi = | ||
| 1261 | info_priv->tx.ts_rssi < 3 ? 0 : | ||
| 1262 | info_priv->tx.ts_rssi - 3; | ||
| 1263 | |||
| 1264 | last_per = rate_ctrl->state[tx_rate].per; | ||
| 1265 | |||
| 1266 | if (xretries) { | ||
| 1267 | /* Update the PER. */ | ||
| 1268 | if (xretries == 1) { | ||
| 1269 | rate_ctrl->state[tx_rate].per += 30; | ||
| 1270 | if (rate_ctrl->state[tx_rate].per > 100) | ||
| 1271 | rate_ctrl->state[tx_rate].per = 100; | ||
| 1272 | } else { | ||
| 1273 | /* xretries == 2 */ | ||
| 1274 | count = sizeof(nretry_to_per_lookup) / | ||
| 1275 | sizeof(nretry_to_per_lookup[0]); | ||
| 1276 | if (retries >= count) | ||
| 1277 | retries = count - 1; | ||
| 1278 | /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ | ||
| 1279 | rate_ctrl->state[tx_rate].per = | ||
| 1280 | (u8)(rate_ctrl->state[tx_rate].per - | ||
| 1281 | (rate_ctrl->state[tx_rate].per >> 3) + | ||
| 1282 | ((100) >> 3)); | ||
| 1283 | } | ||
| 1284 | |||
| 1285 | /* xretries == 1 or 2 */ | ||
| 1286 | |||
| 1287 | if (rate_ctrl->probe_rate == tx_rate) | ||
| 1288 | rate_ctrl->probe_rate = 0; | ||
| 1289 | |||
| 1290 | } else { /* xretries == 0 */ | ||
| 1291 | /* Update the PER. */ | ||
| 1292 | /* Make sure it doesn't index out of array's bounds. */ | ||
| 1293 | count = sizeof(nretry_to_per_lookup) / | ||
| 1294 | sizeof(nretry_to_per_lookup[0]); | ||
| 1295 | if (retries >= count) | ||
| 1296 | retries = count - 1; | ||
| 1297 | if (info_priv->n_bad_frames) { | ||
| 1298 | /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ | ||
| 1299 | /* | ||
| 1300 | * Assuming that n_frames is not 0. The current PER | ||
| 1301 | * from the retries is 100 * retries / (retries+1), | ||
| 1302 | * since the first retries attempts failed, and the | ||
| 1303 | * next one worked. For the one that worked, | ||
| 1304 | * n_bad_frames subframes out of n_frames wored, | ||
| 1305 | * so the PER for that part is | ||
| 1306 | * 100 * n_bad_frames / n_frames, and it contributes | ||
| 1307 | * 100 * n_bad_frames / (n_frames * (retries+1)) to | ||
| 1308 | * the above PER. The expression below is a | ||
| 1309 | * simplified version of the sum of these two terms. | ||
| 1310 | */ | ||
| 1311 | if (info_priv->n_frames > 0) | ||
| 1312 | rate_ctrl->state[tx_rate].per | ||
| 1313 | = (u8) | ||
| 1314 | (rate_ctrl->state[tx_rate].per - | ||
| 1315 | (rate_ctrl->state[tx_rate].per >> 3) + | ||
| 1316 | ((100*(retries*info_priv->n_frames + | ||
| 1317 | info_priv->n_bad_frames) / | ||
| 1318 | (info_priv->n_frames * | ||
| 1319 | (retries+1))) >> 3)); | ||
| 1320 | } else { | ||
| 1321 | /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ | ||
| 1322 | |||
| 1323 | rate_ctrl->state[tx_rate].per = (u8) | ||
| 1324 | (rate_ctrl->state[tx_rate].per - | ||
| 1325 | (rate_ctrl->state[tx_rate].per >> 3) + | ||
| 1326 | (nretry_to_per_lookup[retries] >> 3)); | ||
| 1327 | } | ||
| 1328 | |||
| 1329 | rate_ctrl->rssi_last_prev2 = rate_ctrl->rssi_last_prev; | ||
| 1330 | rate_ctrl->rssi_last_prev = rate_ctrl->rssi_last; | ||
| 1331 | rate_ctrl->rssi_last = info_priv->tx.ts_rssi; | ||
| 1332 | rate_ctrl->rssi_time = now_msec; | ||
| 1333 | |||
| 1334 | /* | ||
| 1335 | * If we got at most one retry then increase the max rate if | ||
| 1336 | * this was a probe. Otherwise, ignore the probe. | ||
| 1337 | */ | ||
| 1338 | |||
| 1339 | if (rate_ctrl->probe_rate && rate_ctrl->probe_rate == tx_rate) { | ||
| 1340 | if (retries > 0 || 2 * info_priv->n_bad_frames > | ||
| 1341 | info_priv->n_frames) { | ||
| 1342 | /* | ||
| 1343 | * Since we probed with just a single attempt, | ||
| 1344 | * any retries means the probe failed. Also, | ||
| 1345 | * if the attempt worked, but more than half | ||
| 1346 | * the subframes were bad then also consider | ||
| 1347 | * the probe a failure. | ||
| 1348 | */ | ||
| 1349 | rate_ctrl->probe_rate = 0; | ||
| 1350 | } else { | ||
| 1351 | u8 probe_rate = 0; | ||
| 1352 | |||
| 1353 | rate_ctrl->rate_max_phy = rate_ctrl->probe_rate; | ||
| 1354 | probe_rate = rate_ctrl->probe_rate; | ||
| 1355 | |||
| 1356 | if (rate_ctrl->state[probe_rate].per > 30) | ||
| 1357 | rate_ctrl->state[probe_rate].per = 20; | ||
| 1358 | |||
| 1359 | rate_ctrl->probe_rate = 0; | ||
| 1360 | |||
| 1361 | /* | ||
| 1362 | * Since this probe succeeded, we allow the next | ||
| 1363 | * probe twice as soon. This allows the maxRate | ||
| 1364 | * to move up faster if the probes are | ||
| 1365 | * succesful. | ||
| 1366 | */ | ||
| 1367 | rate_ctrl->probe_time = now_msec - | ||
| 1368 | rate_table->probe_interval / 2; | ||
| 1369 | } | ||
| 1370 | } | ||
| 1371 | |||
| 1372 | if (retries > 0) { | ||
| 1373 | /* | ||
| 1374 | * Don't update anything. We don't know if | ||
| 1375 | * this was because of collisions or poor signal. | ||
| 1376 | * | ||
| 1377 | * Later: if rssi_ack is close to | ||
| 1378 | * rate_ctrl->state[txRate].rssi_thres and we see lots | ||
| 1379 | * of retries, then we could increase | ||
| 1380 | * rate_ctrl->state[txRate].rssi_thres. | ||
| 1381 | */ | ||
| 1382 | rate_ctrl->hw_maxretry_pktcnt = 0; | ||
| 1383 | } else { | ||
| 1384 | /* | ||
| 1385 | * It worked with no retries. First ignore bogus (small) | ||
| 1386 | * rssi_ack values. | ||
| 1387 | */ | ||
| 1388 | if (tx_rate == rate_ctrl->rate_max_phy && | ||
| 1389 | rate_ctrl->hw_maxretry_pktcnt < 255) { | ||
| 1390 | rate_ctrl->hw_maxretry_pktcnt++; | ||
| 1391 | } | ||
| 1392 | |||
| 1393 | if (info_priv->tx.ts_rssi >= | ||
| 1394 | rate_table->info[tx_rate].rssi_ack_validmin) { | ||
| 1395 | /* Average the rssi */ | ||
| 1396 | if (tx_rate != rate_ctrl->rssi_sum_rate) { | ||
| 1397 | rate_ctrl->rssi_sum_rate = tx_rate; | ||
| 1398 | rate_ctrl->rssi_sum = | ||
| 1399 | rate_ctrl->rssi_sum_cnt = 0; | ||
| 1400 | } | ||
| 1401 | |||
| 1402 | rate_ctrl->rssi_sum += info_priv->tx.ts_rssi; | ||
| 1403 | rate_ctrl->rssi_sum_cnt++; | ||
| 1404 | |||
| 1405 | if (rate_ctrl->rssi_sum_cnt > 4) { | ||
| 1406 | int32_t rssi_ackAvg = | ||
| 1407 | (rate_ctrl->rssi_sum + 2) / 4; | ||
| 1408 | int8_t rssi_thres = | ||
| 1409 | rate_ctrl->state[tx_rate]. | ||
| 1410 | rssi_thres; | ||
| 1411 | int8_t rssi_ack_vmin = | ||
| 1412 | rate_table->info[tx_rate]. | ||
| 1413 | rssi_ack_validmin; | ||
| 1414 | |||
| 1415 | rate_ctrl->rssi_sum = | ||
| 1416 | rate_ctrl->rssi_sum_cnt = 0; | ||
| 1417 | |||
| 1418 | /* Now reduce the current | ||
| 1419 | * rssi threshold. */ | ||
| 1420 | if ((rssi_ackAvg < rssi_thres + 2) && | ||
| 1421 | (rssi_thres > rssi_ack_vmin)) { | ||
| 1422 | rate_ctrl->state[tx_rate]. | ||
| 1423 | rssi_thres--; | ||
| 1424 | } | ||
| 1425 | |||
| 1426 | state_change = TRUE; | ||
| 1427 | } | ||
| 1428 | } | ||
| 1429 | } | ||
| 1430 | } | ||
| 1431 | |||
| 1432 | /* For all cases */ | ||
| 1433 | |||
| 1434 | /* | ||
| 1435 | * If this rate looks bad (high PER) then stop using it for | ||
| 1436 | * a while (except if we are probing). | ||
| 1437 | */ | ||
| 1438 | if (rate_ctrl->state[tx_rate].per >= 55 && tx_rate > 0 && | ||
| 1439 | rate_table->info[tx_rate].ratekbps <= | ||
| 1440 | rate_table->info[rate_ctrl->rate_max_phy].ratekbps) { | ||
| 1441 | ath_rc_get_nextlowervalid_txrate(rate_table, rate_ctrl, | ||
| 1442 | (u8) tx_rate, &rate_ctrl->rate_max_phy); | ||
| 1443 | |||
| 1444 | /* Don't probe for a little while. */ | ||
| 1445 | rate_ctrl->probe_time = now_msec; | ||
| 1446 | } | ||
| 1447 | |||
| 1448 | if (state_change) { | ||
| 1449 | /* | ||
| 1450 | * Make sure the rates above this have higher rssi thresholds. | ||
| 1451 | * (Note: Monotonicity is kept within the OFDM rates and | ||
| 1452 | * within the CCK rates. However, no adjustment is | ||
| 1453 | * made to keep the rssi thresholds monotonically | ||
| 1454 | * increasing between the CCK and OFDM rates.) | ||
| 1455 | */ | ||
| 1456 | for (rate = tx_rate; rate < | ||
| 1457 | rate_ctrl->rate_table_size - 1; rate++) { | ||
| 1458 | if (rate_table->info[rate+1].phy != | ||
| 1459 | rate_table->info[tx_rate].phy) | ||
| 1460 | break; | ||
| 1461 | |||
| 1462 | if (rate_ctrl->state[rate].rssi_thres + | ||
| 1463 | rate_table->info[rate].rssi_ack_deltamin > | ||
| 1464 | rate_ctrl->state[rate+1].rssi_thres) { | ||
| 1465 | rate_ctrl->state[rate+1].rssi_thres = | ||
| 1466 | rate_ctrl->state[rate]. | ||
| 1467 | rssi_thres + | ||
| 1468 | rate_table->info[rate]. | ||
| 1469 | rssi_ack_deltamin; | ||
| 1470 | } | ||
| 1471 | } | ||
| 1472 | |||
| 1473 | /* Make sure the rates below this have lower rssi thresholds. */ | ||
| 1474 | for (rate = tx_rate - 1; rate >= 0; rate--) { | ||
| 1475 | if (rate_table->info[rate].phy != | ||
| 1476 | rate_table->info[tx_rate].phy) | ||
| 1477 | break; | ||
| 1478 | |||
| 1479 | if (rate_ctrl->state[rate].rssi_thres + | ||
| 1480 | rate_table->info[rate].rssi_ack_deltamin > | ||
| 1481 | rate_ctrl->state[rate+1].rssi_thres) { | ||
| 1482 | if (rate_ctrl->state[rate+1].rssi_thres < | ||
| 1483 | rate_table->info[rate]. | ||
| 1484 | rssi_ack_deltamin) | ||
| 1485 | rate_ctrl->state[rate].rssi_thres = 0; | ||
| 1486 | else { | ||
| 1487 | rate_ctrl->state[rate].rssi_thres = | ||
| 1488 | rate_ctrl->state[rate+1]. | ||
| 1489 | rssi_thres - | ||
| 1490 | rate_table->info[rate]. | ||
| 1491 | rssi_ack_deltamin; | ||
| 1492 | } | ||
| 1493 | |||
| 1494 | if (rate_ctrl->state[rate].rssi_thres < | ||
| 1495 | rate_table->info[rate]. | ||
| 1496 | rssi_ack_validmin) { | ||
| 1497 | rate_ctrl->state[rate].rssi_thres = | ||
| 1498 | rate_table->info[rate]. | ||
| 1499 | rssi_ack_validmin; | ||
| 1500 | } | ||
| 1501 | } | ||
| 1502 | } | ||
| 1503 | } | ||
| 1504 | |||
| 1505 | /* Make sure the rates below this have lower PER */ | ||
| 1506 | /* Monotonicity is kept only for rates below the current rate. */ | ||
| 1507 | if (rate_ctrl->state[tx_rate].per < last_per) { | ||
| 1508 | for (rate = tx_rate - 1; rate >= 0; rate--) { | ||
| 1509 | if (rate_table->info[rate].phy != | ||
| 1510 | rate_table->info[tx_rate].phy) | ||
| 1511 | break; | ||
| 1512 | |||
| 1513 | if (rate_ctrl->state[rate].per > | ||
| 1514 | rate_ctrl->state[rate+1].per) { | ||
| 1515 | rate_ctrl->state[rate].per = | ||
| 1516 | rate_ctrl->state[rate+1].per; | ||
| 1517 | } | ||
| 1518 | } | ||
| 1519 | } | ||
| 1520 | |||
| 1521 | /* Maintain monotonicity for rates above the current rate */ | ||
| 1522 | for (rate = tx_rate; rate < rate_ctrl->rate_table_size - 1; rate++) { | ||
| 1523 | if (rate_ctrl->state[rate+1].per < rate_ctrl->state[rate].per) | ||
| 1524 | rate_ctrl->state[rate+1].per = | ||
| 1525 | rate_ctrl->state[rate].per; | ||
| 1526 | } | ||
| 1527 | |||
| 1528 | /* Every so often, we reduce the thresholds and | ||
| 1529 | * PER (different for CCK and OFDM). */ | ||
| 1530 | if (now_msec - rate_ctrl->rssi_down_time >= | ||
| 1531 | rate_table->rssi_reduce_interval) { | ||
| 1532 | |||
| 1533 | for (rate = 0; rate < rate_ctrl->rate_table_size; rate++) { | ||
| 1534 | if (rate_ctrl->state[rate].rssi_thres > | ||
| 1535 | rate_table->info[rate].rssi_ack_validmin) | ||
| 1536 | rate_ctrl->state[rate].rssi_thres -= 1; | ||
| 1537 | } | ||
| 1538 | rate_ctrl->rssi_down_time = now_msec; | ||
| 1539 | } | ||
| 1540 | |||
| 1541 | /* Every so often, we reduce the thresholds | ||
| 1542 | * and PER (different for CCK and OFDM). */ | ||
| 1543 | if (now_msec - rate_ctrl->per_down_time >= | ||
| 1544 | rate_table->rssi_reduce_interval) { | ||
| 1545 | for (rate = 0; rate < rate_ctrl->rate_table_size; rate++) { | ||
| 1546 | rate_ctrl->state[rate].per = | ||
| 1547 | 7 * rate_ctrl->state[rate].per / 8; | ||
| 1548 | } | ||
| 1549 | |||
| 1550 | rate_ctrl->per_down_time = now_msec; | ||
| 1551 | } | ||
| 1552 | } | ||
| 1553 | |||
| 1554 | /* | ||
| 1555 | * This routine is called in rate control callback tx_status() to give | ||
| 1556 | * the status of previous frames. | ||
| 1557 | */ | ||
| 1558 | static void ath_rc_update(struct ath_softc *sc, | ||
| 1559 | struct ath_rate_node *ath_rc_priv, | ||
| 1560 | struct ath_tx_info_priv *info_priv, int final_ts_idx, | ||
| 1561 | int xretries, int long_retry) | ||
| 1562 | { | ||
| 1563 | struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc; | ||
| 1564 | struct ath_rate_table *rate_table; | ||
| 1565 | struct ath_tx_ratectrl *rate_ctrl; | ||
| 1566 | struct ath_rc_series rcs[4]; | ||
| 1567 | u8 flags; | ||
| 1568 | u32 series = 0, rix; | ||
| 1569 | |||
| 1570 | memcpy(rcs, info_priv->rcs, 4 * sizeof(rcs[0])); | ||
| 1571 | rate_table = (struct ath_rate_table *) | ||
| 1572 | asc->hw_rate_table[sc->sc_curmode]; | ||
| 1573 | rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 1574 | ASSERT(rcs[0].tries != 0); | ||
| 1575 | |||
| 1576 | /* | ||
| 1577 | * If the first rate is not the final index, there | ||
| 1578 | * are intermediate rate failures to be processed. | ||
| 1579 | */ | ||
| 1580 | if (final_ts_idx != 0) { | ||
| 1581 | /* Process intermediate rates that failed.*/ | ||
| 1582 | for (series = 0; series < final_ts_idx ; series++) { | ||
| 1583 | if (rcs[series].tries != 0) { | ||
| 1584 | flags = rcs[series].flags; | ||
| 1585 | /* If HT40 and we have switched mode from | ||
| 1586 | * 40 to 20 => don't update */ | ||
| 1587 | if ((flags & ATH_RC_CW40_FLAG) && | ||
| 1588 | (rate_ctrl->rc_phy_mode != | ||
| 1589 | (flags & ATH_RC_CW40_FLAG))) | ||
| 1590 | return; | ||
| 1591 | if ((flags & ATH_RC_CW40_FLAG) && | ||
| 1592 | (flags & ATH_RC_SGI_FLAG)) | ||
| 1593 | rix = rate_table->info[ | ||
| 1594 | rcs[series].rix].ht_index; | ||
| 1595 | else if (flags & ATH_RC_SGI_FLAG) | ||
| 1596 | rix = rate_table->info[ | ||
| 1597 | rcs[series].rix].sgi_index; | ||
| 1598 | else if (flags & ATH_RC_CW40_FLAG) | ||
| 1599 | rix = rate_table->info[ | ||
| 1600 | rcs[series].rix].cw40index; | ||
| 1601 | else | ||
| 1602 | rix = rate_table->info[ | ||
| 1603 | rcs[series].rix].base_index; | ||
| 1604 | ath_rc_update_ht(sc, ath_rc_priv, | ||
| 1605 | info_priv, rix, | ||
| 1606 | xretries ? 1 : 2, | ||
| 1607 | rcs[series].tries); | ||
| 1608 | } | ||
| 1609 | } | ||
| 1610 | } else { | ||
| 1611 | /* | ||
| 1612 | * Handle the special case of MIMO PS burst, where the second | ||
| 1613 | * aggregate is sent out with only one rate and one try. | ||
| 1614 | * Treating it as an excessive retry penalizes the rate | ||
| 1615 | * inordinately. | ||
| 1616 | */ | ||
| 1617 | if (rcs[0].tries == 1 && xretries == 1) | ||
| 1618 | xretries = 2; | ||
| 1619 | } | ||
| 1620 | |||
| 1621 | flags = rcs[series].flags; | ||
| 1622 | /* If HT40 and we have switched mode from 40 to 20 => don't update */ | ||
| 1623 | if ((flags & ATH_RC_CW40_FLAG) && | ||
| 1624 | (rate_ctrl->rc_phy_mode != (flags & ATH_RC_CW40_FLAG))) | ||
| 1625 | return; | ||
| 1626 | |||
| 1627 | if ((flags & ATH_RC_CW40_FLAG) && (flags & ATH_RC_SGI_FLAG)) | ||
| 1628 | rix = rate_table->info[rcs[series].rix].ht_index; | ||
| 1629 | else if (flags & ATH_RC_SGI_FLAG) | ||
| 1630 | rix = rate_table->info[rcs[series].rix].sgi_index; | ||
| 1631 | else if (flags & ATH_RC_CW40_FLAG) | ||
| 1632 | rix = rate_table->info[rcs[series].rix].cw40index; | ||
| 1633 | else | ||
| 1634 | rix = rate_table->info[rcs[series].rix].base_index; | ||
| 1635 | |||
| 1636 | ath_rc_update_ht(sc, ath_rc_priv, info_priv, rix, | ||
| 1637 | xretries, long_retry); | ||
| 1638 | } | ||
| 1639 | |||
| 1640 | |||
| 1641 | /* | ||
| 1642 | * Process a tx descriptor for a completed transmit (success or failure). | ||
| 1643 | */ | ||
| 1644 | static void ath_rate_tx_complete(struct ath_softc *sc, | ||
| 1645 | struct ath_node *an, | ||
| 1646 | struct ath_rate_node *rc_priv, | ||
| 1647 | struct ath_tx_info_priv *info_priv) | ||
| 1648 | { | ||
| 1649 | int final_ts_idx = info_priv->tx.ts_rateindex; | ||
| 1650 | int tx_status = 0, is_underrun = 0; | ||
| 1651 | struct ath_vap *avp; | ||
| 1652 | |||
| 1653 | avp = rc_priv->avp; | ||
| 1654 | if ((avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE) | ||
| 1655 | || info_priv->tx.ts_status & ATH9K_TXERR_FILT) | ||
| 1656 | return; | ||
| 1657 | |||
| 1658 | if (info_priv->tx.ts_rssi > 0) { | ||
| 1659 | ATH_RSSI_LPF(an->an_chainmask_sel.tx_avgrssi, | ||
| 1660 | info_priv->tx.ts_rssi); | ||
| 1661 | } | ||
| 1662 | |||
| 1663 | /* | ||
| 1664 | * If underrun error is seen assume it as an excessive retry only | ||
| 1665 | * if prefetch trigger level have reached the max (0x3f for 5416) | ||
| 1666 | * Adjust the long retry as if the frame was tried ATH_11N_TXMAXTRY | ||
| 1667 | * times. This affects how ratectrl updates PER for the failed rate. | ||
| 1668 | */ | ||
| 1669 | if (info_priv->tx.ts_flags & | ||
| 1670 | (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && | ||
| 1671 | ((sc->sc_ah->ah_txTrigLevel) >= tx_triglevel_max)) { | ||
| 1672 | tx_status = 1; | ||
| 1673 | is_underrun = 1; | ||
| 1674 | } | ||
| 1675 | |||
| 1676 | if ((info_priv->tx.ts_status & ATH9K_TXERR_XRETRY) || | ||
| 1677 | (info_priv->tx.ts_status & ATH9K_TXERR_FIFO)) | ||
| 1678 | tx_status = 1; | ||
| 1679 | |||
| 1680 | ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status, | ||
| 1681 | (is_underrun) ? ATH_11N_TXMAXTRY : | ||
| 1682 | info_priv->tx.ts_longretry); | ||
| 1683 | } | ||
| 1684 | |||
| 1685 | |||
| 1686 | /* | ||
| 1687 | * Update the SIB's rate control information | ||
| 1688 | * | ||
| 1689 | * This should be called when the supported rates change | ||
| 1690 | * (e.g. SME operation, wireless mode change) | ||
| 1691 | * | ||
| 1692 | * It will determine which rates are valid for use. | ||
| 1693 | */ | ||
| 1694 | static void ath_rc_sib_update(struct ath_softc *sc, | ||
| 1695 | struct ath_rate_node *ath_rc_priv, | ||
| 1696 | u32 capflag, int keep_state, | ||
| 1697 | struct ath_rateset *negotiated_rates, | ||
| 1698 | struct ath_rateset *negotiated_htrates) | ||
| 1699 | { | ||
| 1700 | struct ath_rate_table *rate_table = NULL; | ||
| 1701 | struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc; | ||
| 1702 | struct ath_rateset *rateset = negotiated_rates; | ||
| 1703 | u8 *ht_mcs = (u8 *)negotiated_htrates; | ||
| 1704 | struct ath_tx_ratectrl *rate_ctrl = (struct ath_tx_ratectrl *) | ||
| 1705 | (ath_rc_priv); | ||
| 1706 | u8 i, j, k, hi = 0, hthi = 0; | ||
| 1707 | |||
| 1708 | rate_table = (struct ath_rate_table *) | ||
| 1709 | asc->hw_rate_table[sc->sc_curmode]; | ||
| 1710 | |||
| 1711 | /* Initial rate table size. Will change depending | ||
| 1712 | * on the working rate set */ | ||
| 1713 | rate_ctrl->rate_table_size = MAX_TX_RATE_TBL; | ||
| 1714 | |||
| 1715 | /* Initialize thresholds according to the global rate table */ | ||
| 1716 | for (i = 0 ; (i < rate_ctrl->rate_table_size) && (!keep_state); i++) { | ||
| 1717 | rate_ctrl->state[i].rssi_thres = | ||
| 1718 | rate_table->info[i].rssi_ack_validmin; | ||
| 1719 | rate_ctrl->state[i].per = 0; | ||
| 1720 | } | ||
| 1721 | |||
| 1722 | /* Determine the valid rates */ | ||
| 1723 | ath_rc_init_valid_txmask(rate_ctrl); | ||
| 1724 | |||
| 1725 | for (i = 0; i < WLAN_RC_PHY_MAX; i++) { | ||
| 1726 | for (j = 0; j < MAX_TX_RATE_PHY; j++) | ||
| 1727 | rate_ctrl->valid_phy_rateidx[i][j] = 0; | ||
| 1728 | rate_ctrl->valid_phy_ratecnt[i] = 0; | ||
| 1729 | } | ||
| 1730 | rate_ctrl->rc_phy_mode = (capflag & WLAN_RC_40_FLAG); | ||
| 1731 | |||
| 1732 | /* Set stream capability */ | ||
| 1733 | ath_rc_priv->single_stream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; | ||
| 1734 | |||
| 1735 | if (!rateset->rs_nrates) { | ||
| 1736 | /* No working rate, just initialize valid rates */ | ||
| 1737 | hi = ath_rc_sib_init_validrates(ath_rc_priv, rate_table, | ||
| 1738 | capflag); | ||
| 1739 | } else { | ||
| 1740 | /* Use intersection of working rates and valid rates */ | ||
| 1741 | hi = ath_rc_sib_setvalid_rates(ath_rc_priv, rate_table, | ||
| 1742 | rateset, capflag); | ||
| 1743 | if (capflag & WLAN_RC_HT_FLAG) { | ||
| 1744 | hthi = ath_rc_sib_setvalid_htrates(ath_rc_priv, | ||
| 1745 | rate_table, | ||
| 1746 | ht_mcs, | ||
| 1747 | capflag); | ||
| 1748 | } | ||
| 1749 | hi = A_MAX(hi, hthi); | ||
| 1750 | } | ||
| 1751 | |||
| 1752 | rate_ctrl->rate_table_size = hi + 1; | ||
| 1753 | rate_ctrl->rate_max_phy = 0; | ||
| 1754 | ASSERT(rate_ctrl->rate_table_size <= MAX_TX_RATE_TBL); | ||
| 1755 | |||
| 1756 | for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) { | ||
| 1757 | for (j = 0; j < rate_ctrl->valid_phy_ratecnt[i]; j++) { | ||
| 1758 | rate_ctrl->valid_rate_index[k++] = | ||
| 1759 | rate_ctrl->valid_phy_rateidx[i][j]; | ||
| 1760 | } | ||
| 1761 | |||
| 1762 | if (!ath_rc_valid_phyrate(i, rate_table->initial_ratemax, TRUE) | ||
| 1763 | || !rate_ctrl->valid_phy_ratecnt[i]) | ||
| 1764 | continue; | ||
| 1765 | |||
| 1766 | rate_ctrl->rate_max_phy = rate_ctrl->valid_phy_rateidx[i][j-1]; | ||
| 1767 | } | ||
| 1768 | ASSERT(rate_ctrl->rate_table_size <= MAX_TX_RATE_TBL); | ||
| 1769 | ASSERT(k <= MAX_TX_RATE_TBL); | ||
| 1770 | |||
| 1771 | rate_ctrl->max_valid_rate = k; | ||
| 1772 | /* | ||
| 1773 | * Some third party vendors don't send the supported rate series in | ||
| 1774 | * order. So sorting to make sure its in order, otherwise our RateFind | ||
| 1775 | * Algo will select wrong rates | ||
| 1776 | */ | ||
| 1777 | ath_rc_sort_validrates(rate_table, rate_ctrl); | ||
| 1778 | rate_ctrl->rate_max_phy = rate_ctrl->valid_rate_index[k-4]; | ||
| 1779 | } | ||
| 1780 | |||
| 1781 | /* | ||
| 1782 | * Update rate-control state on station associate/reassociate. | ||
| 1783 | */ | ||
| 1784 | static int ath_rate_newassoc(struct ath_softc *sc, | ||
| 1785 | struct ath_rate_node *ath_rc_priv, | ||
| 1786 | unsigned int capflag, | ||
| 1787 | struct ath_rateset *negotiated_rates, | ||
| 1788 | struct ath_rateset *negotiated_htrates) | ||
| 1789 | { | ||
| 1790 | |||
| 1791 | |||
| 1792 | ath_rc_priv->ht_cap = | ||
| 1793 | ((capflag & ATH_RC_DS_FLAG) ? WLAN_RC_DS_FLAG : 0) | | ||
| 1794 | ((capflag & ATH_RC_SGI_FLAG) ? WLAN_RC_SGI_FLAG : 0) | | ||
| 1795 | ((capflag & ATH_RC_HT_FLAG) ? WLAN_RC_HT_FLAG : 0) | | ||
| 1796 | ((capflag & ATH_RC_CW40_FLAG) ? WLAN_RC_40_FLAG : 0); | ||
| 1797 | |||
| 1798 | ath_rc_sib_update(sc, ath_rc_priv, ath_rc_priv->ht_cap, 0, | ||
| 1799 | negotiated_rates, negotiated_htrates); | ||
| 1800 | |||
| 1801 | return 0; | ||
| 1802 | } | ||
| 1803 | |||
| 1804 | /* | ||
| 1805 | * This routine is called to initialize the rate control parameters | ||
| 1806 | * in the SIB. It is called initially during system initialization | ||
| 1807 | * or when a station is associated with the AP. | ||
| 1808 | */ | ||
| 1809 | static void ath_rc_sib_init(struct ath_rate_node *ath_rc_priv) | ||
| 1810 | { | ||
| 1811 | struct ath_tx_ratectrl *rate_ctrl; | ||
| 1812 | |||
| 1813 | rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv); | ||
| 1814 | rate_ctrl->rssi_down_time = jiffies_to_msecs(jiffies); | ||
| 1815 | } | ||
| 1816 | |||
| 1817 | |||
| 1818 | static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta) | ||
| 1819 | |||
| 1820 | { | ||
| 1821 | struct ieee80211_supported_band *sband; | ||
| 1822 | struct ieee80211_hw *hw = local_to_hw(local); | ||
| 1823 | struct ath_softc *sc = hw->priv; | ||
| 1824 | struct ath_rate_node *rc_priv = sta->rate_ctrl_priv; | ||
| 1825 | int i, j = 0; | ||
| 1826 | |||
| 1827 | DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); | ||
| 1828 | sband = local->hw.wiphy->bands[local->hw.conf.channel->band]; | ||
| 1829 | for (i = 0; i < sband->n_bitrates; i++) { | ||
| 1830 | if (sta->supp_rates[local->hw.conf.channel->band] & BIT(i)) { | ||
| 1831 | rc_priv->neg_rates.rs_rates[j] | ||
| 1832 | = (sband->bitrates[i].bitrate * 2) / 10; | ||
| 1833 | j++; | ||
| 1834 | } | ||
| 1835 | } | ||
| 1836 | rc_priv->neg_rates.rs_nrates = j; | ||
| 1837 | } | ||
| 1838 | |||
| 1839 | void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv) | ||
| 1840 | { | ||
| 1841 | struct ath_softc *sc = hw->priv; | ||
| 1842 | u32 capflag = 0; | ||
| 1843 | |||
| 1844 | if (hw->conf.ht_conf.ht_supported) { | ||
| 1845 | capflag |= ATH_RC_HT_FLAG | ATH_RC_DS_FLAG; | ||
| 1846 | if (sc->sc_ht_info.tx_chan_width == ATH9K_HT_MACMODE_2040) | ||
| 1847 | capflag |= ATH_RC_CW40_FLAG; | ||
| 1848 | } | ||
| 1849 | |||
| 1850 | ath_rate_newassoc(sc, rc_priv, capflag, | ||
| 1851 | &rc_priv->neg_rates, | ||
| 1852 | &rc_priv->neg_ht_rates); | ||
| 1853 | |||
| 1854 | } | ||
| 1855 | |||
| 1856 | /* Rate Control callbacks */ | ||
| 1857 | static void ath_tx_status(void *priv, struct net_device *dev, | ||
| 1858 | struct sk_buff *skb) | ||
| 1859 | { | ||
| 1860 | struct ath_softc *sc = priv; | ||
| 1861 | struct ath_tx_info_priv *tx_info_priv; | ||
| 1862 | struct ath_node *an; | ||
| 1863 | struct sta_info *sta; | ||
| 1864 | struct ieee80211_local *local; | ||
| 1865 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 1866 | struct ieee80211_hdr *hdr; | ||
| 1867 | __le16 fc; | ||
| 1868 | |||
| 1869 | local = hw_to_local(sc->hw); | ||
| 1870 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 1871 | fc = hdr->frame_control; | ||
| 1872 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 1873 | |||
| 1874 | spin_lock_bh(&sc->node_lock); | ||
| 1875 | an = ath_node_find(sc, hdr->addr1); | ||
| 1876 | spin_unlock_bh(&sc->node_lock); | ||
| 1877 | |||
| 1878 | sta = sta_info_get(local, hdr->addr1); | ||
| 1879 | if (!an || !sta || !ieee80211_is_data(fc)) { | ||
| 1880 | if (tx_info->driver_data[0] != NULL) { | ||
| 1881 | kfree(tx_info->driver_data[0]); | ||
| 1882 | tx_info->driver_data[0] = NULL; | ||
| 1883 | } | ||
| 1884 | return; | ||
| 1885 | } | ||
| 1886 | if (tx_info->driver_data[0] != NULL) { | ||
| 1887 | ath_rate_tx_complete(sc, an, sta->rate_ctrl_priv, tx_info_priv); | ||
| 1888 | kfree(tx_info->driver_data[0]); | ||
| 1889 | tx_info->driver_data[0] = NULL; | ||
| 1890 | } | ||
| 1891 | } | ||
| 1892 | |||
| 1893 | static void ath_tx_aggr_resp(struct ath_softc *sc, | ||
| 1894 | struct sta_info *sta, | ||
| 1895 | struct ath_node *an, | ||
| 1896 | u8 tidno) | ||
| 1897 | { | ||
| 1898 | struct ieee80211_hw *hw = sc->hw; | ||
| 1899 | struct ieee80211_local *local; | ||
| 1900 | struct ath_atx_tid *txtid; | ||
| 1901 | struct ieee80211_supported_band *sband; | ||
| 1902 | u16 buffersize = 0; | ||
| 1903 | int state; | ||
| 1904 | DECLARE_MAC_BUF(mac); | ||
| 1905 | |||
| 1906 | if (!sc->sc_txaggr) | ||
| 1907 | return; | ||
| 1908 | |||
| 1909 | txtid = ATH_AN_2_TID(an, tidno); | ||
| 1910 | if (!txtid->paused) | ||
| 1911 | return; | ||
| 1912 | |||
| 1913 | local = hw_to_local(sc->hw); | ||
| 1914 | sband = hw->wiphy->bands[hw->conf.channel->band]; | ||
| 1915 | buffersize = IEEE80211_MIN_AMPDU_BUF << | ||
| 1916 | sband->ht_info.ampdu_factor; /* FIXME */ | ||
| 1917 | state = sta->ampdu_mlme.tid_state_tx[tidno]; | ||
| 1918 | |||
| 1919 | if (state & HT_ADDBA_RECEIVED_MSK) { | ||
| 1920 | txtid->addba_exchangecomplete = 1; | ||
| 1921 | txtid->addba_exchangeinprogress = 0; | ||
| 1922 | txtid->baw_size = buffersize; | ||
| 1923 | |||
| 1924 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1925 | "%s: Resuming tid, buffersize: %d\n", | ||
| 1926 | __func__, | ||
| 1927 | buffersize); | ||
| 1928 | |||
| 1929 | ath_tx_resume_tid(sc, txtid); | ||
| 1930 | } | ||
| 1931 | } | ||
| 1932 | |||
| 1933 | static void ath_get_rate(void *priv, struct net_device *dev, | ||
| 1934 | struct ieee80211_supported_band *sband, | ||
| 1935 | struct sk_buff *skb, | ||
| 1936 | struct rate_selection *sel) | ||
| 1937 | { | ||
| 1938 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | ||
| 1939 | struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr); | ||
| 1940 | struct sta_info *sta; | ||
| 1941 | struct ath_softc *sc = (struct ath_softc *)priv; | ||
| 1942 | struct ieee80211_hw *hw = sc->hw; | ||
| 1943 | struct ath_tx_info_priv *tx_info_priv; | ||
| 1944 | struct ath_rate_node *ath_rc_priv; | ||
| 1945 | struct ath_node *an; | ||
| 1946 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 1947 | int is_probe, chk, ret; | ||
| 1948 | s8 lowest_idx; | ||
| 1949 | __le16 fc = hdr->frame_control; | ||
| 1950 | u8 *qc, tid; | ||
| 1951 | DECLARE_MAC_BUF(mac); | ||
| 1952 | |||
| 1953 | DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__); | ||
| 1954 | |||
| 1955 | /* allocate driver private area of tx_info */ | ||
| 1956 | tx_info->driver_data[0] = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); | ||
| 1957 | ASSERT(tx_info->driver_data[0] != NULL); | ||
| 1958 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 1959 | |||
| 1960 | sta = sta_info_get(local, hdr->addr1); | ||
| 1961 | lowest_idx = rate_lowest_index(local, sband, sta); | ||
| 1962 | tx_info_priv->min_rate = (sband->bitrates[lowest_idx].bitrate * 2) / 10; | ||
| 1963 | /* lowest rate for management and multicast/broadcast frames */ | ||
| 1964 | if (!ieee80211_is_data(fc) || | ||
| 1965 | is_multicast_ether_addr(hdr->addr1) || !sta) { | ||
| 1966 | sel->rate_idx = lowest_idx; | ||
| 1967 | return; | ||
| 1968 | } | ||
| 1969 | |||
| 1970 | ath_rc_priv = sta->rate_ctrl_priv; | ||
| 1971 | |||
| 1972 | /* Find tx rate for unicast frames */ | ||
| 1973 | ath_rate_findrate(sc, ath_rc_priv, | ||
| 1974 | ATH_11N_TXMAXTRY, 4, | ||
| 1975 | ATH_RC_PROBE_ALLOWED, | ||
| 1976 | tx_info_priv->rcs, | ||
| 1977 | &is_probe, | ||
| 1978 | false); | ||
| 1979 | if (is_probe) | ||
| 1980 | sel->probe_idx = ((struct ath_tx_ratectrl *) | ||
| 1981 | sta->rate_ctrl_priv)->probe_rate; | ||
| 1982 | |||
| 1983 | /* Ratecontrol sometimes returns invalid rate index */ | ||
| 1984 | if (tx_info_priv->rcs[0].rix != 0xff) | ||
| 1985 | ath_rc_priv->prev_data_rix = tx_info_priv->rcs[0].rix; | ||
| 1986 | else | ||
| 1987 | tx_info_priv->rcs[0].rix = ath_rc_priv->prev_data_rix; | ||
| 1988 | |||
| 1989 | sel->rate_idx = tx_info_priv->rcs[0].rix; | ||
| 1990 | |||
| 1991 | /* Check if aggregation has to be enabled for this tid */ | ||
| 1992 | |||
| 1993 | if (hw->conf.ht_conf.ht_supported) { | ||
| 1994 | if (ieee80211_is_data_qos(fc)) { | ||
| 1995 | qc = ieee80211_get_qos_ctl(hdr); | ||
| 1996 | tid = qc[0] & 0xf; | ||
| 1997 | |||
| 1998 | spin_lock_bh(&sc->node_lock); | ||
| 1999 | an = ath_node_find(sc, hdr->addr1); | ||
| 2000 | spin_unlock_bh(&sc->node_lock); | ||
| 2001 | |||
| 2002 | if (!an) { | ||
| 2003 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 2004 | "%s: Node not found to " | ||
| 2005 | "init/chk TX aggr\n", __func__); | ||
| 2006 | return; | ||
| 2007 | } | ||
| 2008 | |||
| 2009 | chk = ath_tx_aggr_check(sc, an, tid); | ||
| 2010 | if (chk == AGGR_REQUIRED) { | ||
| 2011 | ret = ieee80211_start_tx_ba_session(hw, | ||
| 2012 | hdr->addr1, tid); | ||
| 2013 | if (ret) | ||
| 2014 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 2015 | "%s: Unable to start tx " | ||
| 2016 | "aggr for: %s\n", | ||
| 2017 | __func__, | ||
| 2018 | print_mac(mac, hdr->addr1)); | ||
| 2019 | else | ||
| 2020 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 2021 | "%s: Started tx aggr for: %s\n", | ||
| 2022 | __func__, | ||
| 2023 | print_mac(mac, hdr->addr1)); | ||
| 2024 | } else if (chk == AGGR_EXCHANGE_PROGRESS) | ||
| 2025 | ath_tx_aggr_resp(sc, sta, an, tid); | ||
| 2026 | } | ||
| 2027 | } | ||
| 2028 | } | ||
| 2029 | |||
| 2030 | static void ath_rate_init(void *priv, void *priv_sta, | ||
| 2031 | struct ieee80211_local *local, | ||
| 2032 | struct sta_info *sta) | ||
| 2033 | { | ||
| 2034 | struct ieee80211_supported_band *sband; | ||
| 2035 | struct ieee80211_hw *hw = local_to_hw(local); | ||
| 2036 | struct ieee80211_conf *conf = &local->hw.conf; | ||
| 2037 | struct ath_softc *sc = hw->priv; | ||
| 2038 | int i, j = 0; | ||
| 2039 | |||
| 2040 | DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__); | ||
| 2041 | |||
| 2042 | sband = local->hw.wiphy->bands[local->hw.conf.channel->band]; | ||
| 2043 | sta->txrate_idx = rate_lowest_index(local, sband, sta); | ||
| 2044 | |||
| 2045 | ath_setup_rates(local, sta); | ||
| 2046 | if (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) { | ||
| 2047 | for (i = 0; i < MCS_SET_SIZE; i++) { | ||
| 2048 | if (conf->ht_conf.supp_mcs_set[i/8] & (1<<(i%8))) | ||
| 2049 | ((struct ath_rate_node *) | ||
| 2050 | priv_sta)->neg_ht_rates.rs_rates[j++] = i; | ||
| 2051 | if (j == ATH_RATE_MAX) | ||
| 2052 | break; | ||
| 2053 | } | ||
| 2054 | ((struct ath_rate_node *)priv_sta)->neg_ht_rates.rs_nrates = j; | ||
| 2055 | } | ||
| 2056 | ath_rc_node_update(hw, priv_sta); | ||
| 2057 | } | ||
| 2058 | |||
| 2059 | static void ath_rate_clear(void *priv) | ||
| 2060 | { | ||
| 2061 | return; | ||
| 2062 | } | ||
| 2063 | |||
| 2064 | static void *ath_rate_alloc(struct ieee80211_local *local) | ||
| 2065 | { | ||
| 2066 | struct ieee80211_hw *hw = local_to_hw(local); | ||
| 2067 | struct ath_softc *sc = hw->priv; | ||
| 2068 | |||
| 2069 | DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); | ||
| 2070 | return local->hw.priv; | ||
| 2071 | } | ||
| 2072 | |||
| 2073 | static void ath_rate_free(void *priv) | ||
| 2074 | { | ||
| 2075 | return; | ||
| 2076 | } | ||
| 2077 | |||
| 2078 | static void *ath_rate_alloc_sta(void *priv, gfp_t gfp) | ||
| 2079 | { | ||
| 2080 | struct ath_softc *sc = priv; | ||
| 2081 | struct ath_vap *avp = sc->sc_vaps[0]; | ||
| 2082 | struct ath_rate_node *rate_priv; | ||
| 2083 | |||
| 2084 | DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); | ||
| 2085 | rate_priv = ath_rate_node_alloc(avp, sc->sc_rc, gfp); | ||
| 2086 | if (!rate_priv) { | ||
| 2087 | DPRINTF(sc, ATH_DBG_FATAL, "%s:Unable to allocate" | ||
| 2088 | "private rate control structure", __func__); | ||
| 2089 | return NULL; | ||
| 2090 | } | ||
| 2091 | ath_rc_sib_init(rate_priv); | ||
| 2092 | return rate_priv; | ||
| 2093 | } | ||
| 2094 | |||
| 2095 | static void ath_rate_free_sta(void *priv, void *priv_sta) | ||
| 2096 | { | ||
| 2097 | struct ath_rate_node *rate_priv = priv_sta; | ||
| 2098 | struct ath_softc *sc = priv; | ||
| 2099 | |||
| 2100 | DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); | ||
| 2101 | ath_rate_node_free(rate_priv); | ||
| 2102 | } | ||
| 2103 | |||
| 2104 | static struct rate_control_ops ath_rate_ops = { | ||
| 2105 | .module = NULL, | ||
| 2106 | .name = "ath9k_rate_control", | ||
| 2107 | .tx_status = ath_tx_status, | ||
| 2108 | .get_rate = ath_get_rate, | ||
| 2109 | .rate_init = ath_rate_init, | ||
| 2110 | .clear = ath_rate_clear, | ||
| 2111 | .alloc = ath_rate_alloc, | ||
| 2112 | .free = ath_rate_free, | ||
| 2113 | .alloc_sta = ath_rate_alloc_sta, | ||
| 2114 | .free_sta = ath_rate_free_sta | ||
| 2115 | }; | ||
| 2116 | |||
| 2117 | int ath_rate_control_register(void) | ||
| 2118 | { | ||
| 2119 | return ieee80211_rate_control_register(&ath_rate_ops); | ||
| 2120 | } | ||
| 2121 | |||
| 2122 | void ath_rate_control_unregister(void) | ||
| 2123 | { | ||
| 2124 | ieee80211_rate_control_unregister(&ath_rate_ops); | ||
| 2125 | } | ||
| 2126 | |||
diff --git a/drivers/net/wireless/ath9k/rc.h b/drivers/net/wireless/ath9k/rc.h new file mode 100644 index 000000000000..71aef9c75232 --- /dev/null +++ b/drivers/net/wireless/ath9k/rc.h | |||
| @@ -0,0 +1,316 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2004 Sam Leffler, Errno Consulting | ||
| 3 | * Copyright (c) 2004 Video54 Technologies, Inc. | ||
| 4 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 5 | * | ||
| 6 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 7 | * purpose with or without fee is hereby granted, provided that the above | ||
| 8 | * copyright notice and this permission notice appear in all copies. | ||
| 9 | * | ||
| 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef RC_H | ||
| 20 | #define RC_H | ||
| 21 | |||
| 22 | #include "ath9k.h" | ||
| 23 | /* | ||
| 24 | * Interface definitions for transmit rate control modules for the | ||
| 25 | * Atheros driver. | ||
| 26 | * | ||
| 27 | * A rate control module is responsible for choosing the transmit rate | ||
| 28 | * for each data frame. Management+control frames are always sent at | ||
| 29 | * a fixed rate. | ||
| 30 | * | ||
| 31 | * Only one module may be present at a time; the driver references | ||
| 32 | * rate control interfaces by symbol name. If multiple modules are | ||
| 33 | * to be supported we'll need to switch to a registration-based scheme | ||
| 34 | * as is currently done, for example, for authentication modules. | ||
| 35 | * | ||
| 36 | * An instance of the rate control module is attached to each device | ||
| 37 | * at attach time and detached when the device is destroyed. The module | ||
| 38 | * may associate data with each device and each node (station). Both | ||
| 39 | * sets of storage are opaque except for the size of the per-node storage | ||
| 40 | * which must be provided when the module is attached. | ||
| 41 | * | ||
| 42 | * The rate control module is notified for each state transition and | ||
| 43 | * station association/reassociation. Otherwise it is queried for a | ||
| 44 | * rate for each outgoing frame and provided status from each transmitted | ||
| 45 | * frame. Any ancillary processing is the responsibility of the module | ||
| 46 | * (e.g. if periodic processing is required then the module should setup | ||
| 47 | * it's own timer). | ||
| 48 | * | ||
| 49 | * In addition to the transmit rate for each frame the module must also | ||
| 50 | * indicate the number of attempts to make at the specified rate. If this | ||
| 51 | * number is != ATH_TXMAXTRY then an additional callback is made to setup | ||
| 52 | * additional transmit state. The rate control code is assumed to write | ||
| 53 | * this additional data directly to the transmit descriptor. | ||
| 54 | */ | ||
| 55 | |||
| 56 | struct ath_softc; | ||
| 57 | |||
| 58 | #define TRUE 1 | ||
| 59 | #define FALSE 0 | ||
| 60 | |||
| 61 | #define ATH_RATE_MAX 30 | ||
| 62 | #define MCS_SET_SIZE 128 | ||
| 63 | |||
| 64 | enum ieee80211_fixed_rate_mode { | ||
| 65 | IEEE80211_FIXED_RATE_NONE = 0, | ||
| 66 | IEEE80211_FIXED_RATE_MCS = 1 /* HT rates */ | ||
| 67 | }; | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Use the hal os glue code to get ms time | ||
| 71 | */ | ||
| 72 | #define IEEE80211_RATE_IDX_ENTRY(val, idx) (((val&(0xff<<(idx*8)))>>(idx*8))) | ||
| 73 | |||
| 74 | #define SHORT_PRE 1 | ||
| 75 | #define LONG_PRE 0 | ||
| 76 | |||
| 77 | #define WLAN_PHY_HT_20_SS WLAN_RC_PHY_HT_20_SS | ||
| 78 | #define WLAN_PHY_HT_20_DS WLAN_RC_PHY_HT_20_DS | ||
| 79 | #define WLAN_PHY_HT_20_DS_HGI WLAN_RC_PHY_HT_20_DS_HGI | ||
| 80 | #define WLAN_PHY_HT_40_SS WLAN_RC_PHY_HT_40_SS | ||
| 81 | #define WLAN_PHY_HT_40_SS_HGI WLAN_RC_PHY_HT_40_SS_HGI | ||
| 82 | #define WLAN_PHY_HT_40_DS WLAN_RC_PHY_HT_40_DS | ||
| 83 | #define WLAN_PHY_HT_40_DS_HGI WLAN_RC_PHY_HT_40_DS_HGI | ||
| 84 | |||
| 85 | #define WLAN_PHY_OFDM PHY_OFDM | ||
| 86 | #define WLAN_PHY_CCK PHY_CCK | ||
| 87 | |||
| 88 | #define TRUE_20 0x2 | ||
| 89 | #define TRUE_40 0x4 | ||
| 90 | #define TRUE_2040 (TRUE_20|TRUE_40) | ||
| 91 | #define TRUE_ALL (TRUE_2040|TRUE) | ||
| 92 | |||
| 93 | enum { | ||
| 94 | WLAN_RC_PHY_HT_20_SS = 4, | ||
| 95 | WLAN_RC_PHY_HT_20_DS, | ||
| 96 | WLAN_RC_PHY_HT_40_SS, | ||
| 97 | WLAN_RC_PHY_HT_40_DS, | ||
| 98 | WLAN_RC_PHY_HT_20_SS_HGI, | ||
| 99 | WLAN_RC_PHY_HT_20_DS_HGI, | ||
| 100 | WLAN_RC_PHY_HT_40_SS_HGI, | ||
| 101 | WLAN_RC_PHY_HT_40_DS_HGI, | ||
| 102 | WLAN_RC_PHY_MAX | ||
| 103 | }; | ||
| 104 | |||
| 105 | #define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \ | ||
| 106 | || (_phy == WLAN_RC_PHY_HT_40_DS) \ | ||
| 107 | || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ | ||
| 108 | || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) | ||
| 109 | #define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \ | ||
| 110 | || (_phy == WLAN_RC_PHY_HT_40_DS) \ | ||
| 111 | || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ | ||
| 112 | || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) | ||
| 113 | #define WLAN_RC_PHY_SGI(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS_HGI) \ | ||
| 114 | || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ | ||
| 115 | || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ | ||
| 116 | || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) | ||
| 117 | |||
| 118 | #define WLAN_RC_PHY_HT(_phy) (_phy >= WLAN_RC_PHY_HT_20_SS) | ||
| 119 | |||
| 120 | /* Returns the capflag mode */ | ||
| 121 | #define WLAN_RC_CAP_MODE(capflag) (((capflag & WLAN_RC_HT_FLAG) ? \ | ||
| 122 | (capflag & WLAN_RC_40_FLAG) ? TRUE_40 : TRUE_20 : TRUE)) | ||
| 123 | |||
| 124 | /* Return TRUE if flag supports HT20 && client supports HT20 or | ||
| 125 | * return TRUE if flag supports HT40 && client supports HT40. | ||
| 126 | * This is used becos some rates overlap between HT20/HT40. | ||
| 127 | */ | ||
| 128 | |||
| 129 | #define WLAN_RC_PHY_HT_VALID(flag, capflag) (((flag & TRUE_20) && !(capflag \ | ||
| 130 | & WLAN_RC_40_FLAG)) || ((flag & TRUE_40) && \ | ||
| 131 | (capflag & WLAN_RC_40_FLAG))) | ||
| 132 | |||
| 133 | #define WLAN_RC_DS_FLAG (0x01) | ||
| 134 | #define WLAN_RC_40_FLAG (0x02) | ||
| 135 | #define WLAN_RC_SGI_FLAG (0x04) | ||
| 136 | #define WLAN_RC_HT_FLAG (0x08) | ||
| 137 | |||
| 138 | /* Index into the rate table */ | ||
| 139 | #define INIT_RATE_MAX_20 23 | ||
| 140 | #define INIT_RATE_MAX_40 40 | ||
| 141 | |||
| 142 | #define RATE_TABLE_SIZE 64 | ||
| 143 | |||
| 144 | /* XXX: Convert to kdoc */ | ||
| 145 | struct ath_rate_table { | ||
| 146 | int rate_cnt; | ||
| 147 | struct { | ||
| 148 | int valid; /* Valid for use in rate control */ | ||
| 149 | int valid_single_stream;/* Valid for use in rate control | ||
| 150 | for single stream operation */ | ||
| 151 | u8 phy; /* CCK/OFDM/TURBO/XR */ | ||
| 152 | u32 ratekbps; /* Rate in Kbits per second */ | ||
| 153 | u32 user_ratekbps; /* User rate in KBits per second */ | ||
| 154 | u8 ratecode; /* rate that goes into | ||
| 155 | hw descriptors */ | ||
| 156 | u8 short_preamble; /* Mask for enabling short preamble | ||
| 157 | in rate code for CCK */ | ||
| 158 | u8 dot11rate; /* Value that goes into supported | ||
| 159 | rates info element of MLME */ | ||
| 160 | u8 ctrl_rate; /* Index of next lower basic rate, | ||
| 161 | used for duration computation */ | ||
| 162 | int8_t rssi_ack_validmin; /* Rate control related */ | ||
| 163 | int8_t rssi_ack_deltamin; /* Rate control related */ | ||
| 164 | u8 base_index; /* base rate index */ | ||
| 165 | u8 cw40index; /* 40cap rate index */ | ||
| 166 | u8 sgi_index; /* shortgi rate index */ | ||
| 167 | u8 ht_index; /* shortgi rate index */ | ||
| 168 | u32 max_4ms_framelen; /* Maximum frame length(bytes) | ||
| 169 | for 4ms tx duration */ | ||
| 170 | } info[RATE_TABLE_SIZE]; | ||
| 171 | u32 probe_interval; /* interval for ratectrl to | ||
| 172 | probe for other rates */ | ||
| 173 | u32 rssi_reduce_interval; /* interval for ratectrl | ||
| 174 | to reduce RSSI */ | ||
| 175 | u8 initial_ratemax; /* the initial ratemax value used | ||
| 176 | in ath_rc_sib_update() */ | ||
| 177 | }; | ||
| 178 | |||
| 179 | #define ATH_RC_PROBE_ALLOWED 0x00000001 | ||
| 180 | #define ATH_RC_MINRATE_LASTRATE 0x00000002 | ||
| 181 | #define ATH_RC_SHORT_PREAMBLE 0x00000004 | ||
| 182 | |||
| 183 | struct ath_rc_series { | ||
| 184 | u8 rix; | ||
| 185 | u8 tries; | ||
| 186 | u8 flags; | ||
| 187 | u32 max_4ms_framelen; | ||
| 188 | }; | ||
| 189 | |||
| 190 | /* rcs_flags definition */ | ||
| 191 | #define ATH_RC_DS_FLAG 0x01 | ||
| 192 | #define ATH_RC_CW40_FLAG 0x02 /* CW 40 */ | ||
| 193 | #define ATH_RC_SGI_FLAG 0x04 /* Short Guard Interval */ | ||
| 194 | #define ATH_RC_HT_FLAG 0x08 /* HT */ | ||
| 195 | #define ATH_RC_RTSCTS_FLAG 0x10 /* RTS-CTS */ | ||
| 196 | |||
| 197 | /* | ||
| 198 | * State structures for new rate adaptation code | ||
| 199 | */ | ||
| 200 | #define MAX_TX_RATE_TBL 64 | ||
| 201 | #define MAX_TX_RATE_PHY 48 | ||
| 202 | |||
| 203 | struct ath_tx_ratectrl_state { | ||
| 204 | int8_t rssi_thres; /* required rssi for this rate (dB) */ | ||
| 205 | u8 per; /* recent estimate of packet error rate (%) */ | ||
| 206 | }; | ||
| 207 | |||
| 208 | struct ath_tx_ratectrl { | ||
| 209 | struct ath_tx_ratectrl_state state[MAX_TX_RATE_TBL]; /* state */ | ||
| 210 | int8_t rssi_last; /* last ack rssi */ | ||
| 211 | int8_t rssi_last_lookup; /* last ack rssi used for lookup */ | ||
| 212 | int8_t rssi_last_prev; /* previous last ack rssi */ | ||
| 213 | int8_t rssi_last_prev2; /* 2nd previous last ack rssi */ | ||
| 214 | int32_t rssi_sum_cnt; /* count of rssi_sum for averaging */ | ||
| 215 | int32_t rssi_sum_rate; /* rate that we are averaging */ | ||
| 216 | int32_t rssi_sum; /* running sum of rssi for averaging */ | ||
| 217 | u32 valid_txrate_mask; /* mask of valid rates */ | ||
| 218 | u8 rate_table_size; /* rate table size */ | ||
| 219 | u8 rate_max; /* max rate that has recently worked */ | ||
| 220 | u8 probe_rate; /* rate we are probing at */ | ||
| 221 | u32 rssi_time; /* msec timestamp for last ack rssi */ | ||
| 222 | u32 rssi_down_time; /* msec timestamp for last down step */ | ||
| 223 | u32 probe_time; /* msec timestamp for last probe */ | ||
| 224 | u8 hw_maxretry_pktcnt; /* num packets since we got | ||
| 225 | HW max retry error */ | ||
| 226 | u8 max_valid_rate; /* maximum number of valid rate */ | ||
| 227 | u8 valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */ | ||
| 228 | u32 per_down_time; /* msec timstamp for last | ||
| 229 | PER down step */ | ||
| 230 | |||
| 231 | /* 11n state */ | ||
| 232 | u8 valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */ | ||
| 233 | u8 valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL]; | ||
| 234 | u8 rc_phy_mode; | ||
| 235 | u8 rate_max_phy; /* Phy index for the max rate */ | ||
| 236 | u32 rate_max_lastused; /* msec timstamp of when we | ||
| 237 | last used rateMaxPhy */ | ||
| 238 | u32 probe_interval; /* interval for ratectrl to probe | ||
| 239 | for other rates */ | ||
| 240 | }; | ||
| 241 | |||
| 242 | struct ath_rateset { | ||
| 243 | u8 rs_nrates; | ||
| 244 | u8 rs_rates[ATH_RATE_MAX]; | ||
| 245 | }; | ||
| 246 | |||
| 247 | /* per-device state */ | ||
| 248 | struct ath_rate_softc { | ||
| 249 | /* phy tables that contain rate control data */ | ||
| 250 | const void *hw_rate_table[ATH9K_MODE_MAX]; | ||
| 251 | int fixedrix; /* -1 or index of fixed rate */ | ||
| 252 | }; | ||
| 253 | |||
| 254 | /* per-node state */ | ||
| 255 | struct ath_rate_node { | ||
| 256 | struct ath_tx_ratectrl tx_ratectrl; /* rate control state proper */ | ||
| 257 | u32 prev_data_rix; /* rate idx of last data frame */ | ||
| 258 | |||
| 259 | /* map of rate ix -> negotiated rate set ix */ | ||
| 260 | u8 rixmap[MAX_TX_RATE_TBL]; | ||
| 261 | |||
| 262 | /* map of ht rate ix -> negotiated rate set ix */ | ||
| 263 | u8 ht_rixmap[MAX_TX_RATE_TBL]; | ||
| 264 | |||
| 265 | u8 ht_cap; /* ht capabilities */ | ||
| 266 | u8 ant_tx; /* current transmit antenna */ | ||
| 267 | |||
| 268 | u8 single_stream; /* When TRUE, only single | ||
| 269 | stream Tx possible */ | ||
| 270 | struct ath_rateset neg_rates; /* Negotiated rates */ | ||
| 271 | struct ath_rateset neg_ht_rates; /* Negotiated HT rates */ | ||
| 272 | struct ath_rate_softc *asc; /* back pointer to atheros softc */ | ||
| 273 | struct ath_vap *avp; /* back pointer to vap */ | ||
| 274 | }; | ||
| 275 | |||
| 276 | /* Driver data of ieee80211_tx_info */ | ||
| 277 | struct ath_tx_info_priv { | ||
| 278 | struct ath_rc_series rcs[4]; | ||
| 279 | struct ath_tx_status tx; | ||
| 280 | int n_frames; | ||
| 281 | int n_bad_frames; | ||
| 282 | u8 min_rate; | ||
| 283 | }; | ||
| 284 | |||
| 285 | /* | ||
| 286 | * Attach/detach a rate control module. | ||
| 287 | */ | ||
| 288 | struct ath_rate_softc *ath_rate_attach(struct ath_hal *ah); | ||
| 289 | void ath_rate_detach(struct ath_rate_softc *asc); | ||
| 290 | |||
| 291 | /* | ||
| 292 | * Update/reset rate control state for 802.11 state transitions. | ||
| 293 | * Important mostly as the analog to ath_rate_newassoc when operating | ||
| 294 | * in station mode. | ||
| 295 | */ | ||
| 296 | void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv); | ||
| 297 | void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp); | ||
| 298 | |||
| 299 | /* | ||
| 300 | * Return the tx rate series. | ||
| 301 | */ | ||
| 302 | void ath_rate_findrate(struct ath_softc *sc, struct ath_rate_node *ath_rc_priv, | ||
| 303 | int num_tries, int num_rates, | ||
| 304 | unsigned int rcflag, struct ath_rc_series[], | ||
| 305 | int *is_probe, int isretry); | ||
| 306 | /* | ||
| 307 | * Return rate index for given Dot11 Rate. | ||
| 308 | */ | ||
| 309 | u8 ath_rate_findrateix(struct ath_softc *sc, | ||
| 310 | u8 dot11_rate); | ||
| 311 | |||
| 312 | /* Routines to register/unregister rate control algorithm */ | ||
| 313 | int ath_rate_control_register(void); | ||
| 314 | void ath_rate_control_unregister(void); | ||
| 315 | |||
| 316 | #endif /* RC_H */ | ||
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c new file mode 100644 index 000000000000..2fe806175c01 --- /dev/null +++ b/drivers/net/wireless/ath9k/recv.c | |||
| @@ -0,0 +1,1318 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Implementation of receive path. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include "core.h" | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Setup and link descriptors. | ||
| 25 | * | ||
| 26 | * 11N: we can no longer afford to self link the last descriptor. | ||
| 27 | * MAC acknowledges BA status as long as it copies frames to host | ||
| 28 | * buffer (or rx fifo). This can incorrectly acknowledge packets | ||
| 29 | * to a sender if last desc is self-linked. | ||
| 30 | * | ||
| 31 | * NOTE: Caller should hold the rxbuf lock. | ||
| 32 | */ | ||
| 33 | |||
| 34 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) | ||
| 35 | { | ||
| 36 | struct ath_hal *ah = sc->sc_ah; | ||
| 37 | struct ath_desc *ds; | ||
| 38 | struct sk_buff *skb; | ||
| 39 | |||
| 40 | ATH_RXBUF_RESET(bf); | ||
| 41 | |||
| 42 | ds = bf->bf_desc; | ||
| 43 | ds->ds_link = 0; /* link to null */ | ||
| 44 | ds->ds_data = bf->bf_buf_addr; | ||
| 45 | |||
| 46 | /* XXX For RADAR? | ||
| 47 | * virtual addr of the beginning of the buffer. */ | ||
| 48 | skb = bf->bf_mpdu; | ||
| 49 | ASSERT(skb != NULL); | ||
| 50 | ds->ds_vdata = skb->data; | ||
| 51 | |||
| 52 | /* setup rx descriptors */ | ||
| 53 | ath9k_hw_setuprxdesc(ah, | ||
| 54 | ds, | ||
| 55 | skb_tailroom(skb), /* buffer size */ | ||
| 56 | 0); | ||
| 57 | |||
| 58 | if (sc->sc_rxlink == NULL) | ||
| 59 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); | ||
| 60 | else | ||
| 61 | *sc->sc_rxlink = bf->bf_daddr; | ||
| 62 | |||
| 63 | sc->sc_rxlink = &ds->ds_link; | ||
| 64 | ath9k_hw_rxena(ah); | ||
| 65 | } | ||
| 66 | |||
| 67 | /* Process received BAR frame */ | ||
| 68 | |||
| 69 | static int ath_bar_rx(struct ath_softc *sc, | ||
| 70 | struct ath_node *an, | ||
| 71 | struct sk_buff *skb) | ||
| 72 | { | ||
| 73 | struct ieee80211_bar *bar; | ||
| 74 | struct ath_arx_tid *rxtid; | ||
| 75 | struct sk_buff *tskb; | ||
| 76 | struct ath_recv_status *rx_status; | ||
| 77 | int tidno, index, cindex; | ||
| 78 | u16 seqno; | ||
| 79 | |||
| 80 | /* look at BAR contents */ | ||
| 81 | |||
| 82 | bar = (struct ieee80211_bar *)skb->data; | ||
| 83 | tidno = (le16_to_cpu(bar->control) & IEEE80211_BAR_CTL_TID_M) | ||
| 84 | >> IEEE80211_BAR_CTL_TID_S; | ||
| 85 | seqno = le16_to_cpu(bar->start_seq_num) >> IEEE80211_SEQ_SEQ_SHIFT; | ||
| 86 | |||
| 87 | /* process BAR - indicate all pending RX frames till the BAR seqno */ | ||
| 88 | |||
| 89 | rxtid = &an->an_aggr.rx.tid[tidno]; | ||
| 90 | |||
| 91 | spin_lock_bh(&rxtid->tidlock); | ||
| 92 | |||
| 93 | /* get relative index */ | ||
| 94 | |||
| 95 | index = ATH_BA_INDEX(rxtid->seq_next, seqno); | ||
| 96 | |||
| 97 | /* drop BAR if old sequence (index is too large) */ | ||
| 98 | |||
| 99 | if ((index > rxtid->baw_size) && | ||
| 100 | (index > (IEEE80211_SEQ_MAX - (rxtid->baw_size << 2)))) | ||
| 101 | /* discard frame, ieee layer may not treat frame as a dup */ | ||
| 102 | goto unlock_and_free; | ||
| 103 | |||
| 104 | /* complete receive processing for all pending frames upto BAR seqno */ | ||
| 105 | |||
| 106 | cindex = (rxtid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | ||
| 107 | while ((rxtid->baw_head != rxtid->baw_tail) && | ||
| 108 | (rxtid->baw_head != cindex)) { | ||
| 109 | tskb = rxtid->rxbuf[rxtid->baw_head].rx_wbuf; | ||
| 110 | rx_status = &rxtid->rxbuf[rxtid->baw_head].rx_status; | ||
| 111 | rxtid->rxbuf[rxtid->baw_head].rx_wbuf = NULL; | ||
| 112 | |||
| 113 | if (tskb != NULL) | ||
| 114 | ath_rx_subframe(an, tskb, rx_status); | ||
| 115 | |||
| 116 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 117 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 118 | } | ||
| 119 | |||
| 120 | /* ... and indicate rest of the frames in-order */ | ||
| 121 | |||
| 122 | while (rxtid->baw_head != rxtid->baw_tail && | ||
| 123 | rxtid->rxbuf[rxtid->baw_head].rx_wbuf != NULL) { | ||
| 124 | tskb = rxtid->rxbuf[rxtid->baw_head].rx_wbuf; | ||
| 125 | rx_status = &rxtid->rxbuf[rxtid->baw_head].rx_status; | ||
| 126 | rxtid->rxbuf[rxtid->baw_head].rx_wbuf = NULL; | ||
| 127 | |||
| 128 | ath_rx_subframe(an, tskb, rx_status); | ||
| 129 | |||
| 130 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 131 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 132 | } | ||
| 133 | |||
| 134 | unlock_and_free: | ||
| 135 | spin_unlock_bh(&rxtid->tidlock); | ||
| 136 | /* free bar itself */ | ||
| 137 | dev_kfree_skb(skb); | ||
| 138 | return IEEE80211_FTYPE_CTL; | ||
| 139 | } | ||
| 140 | |||
| 141 | /* Function to handle a subframe of aggregation when HT is enabled */ | ||
| 142 | |||
| 143 | static int ath_ampdu_input(struct ath_softc *sc, | ||
| 144 | struct ath_node *an, | ||
| 145 | struct sk_buff *skb, | ||
| 146 | struct ath_recv_status *rx_status) | ||
| 147 | { | ||
| 148 | struct ieee80211_hdr *hdr; | ||
| 149 | struct ath_arx_tid *rxtid; | ||
| 150 | struct ath_rxbuf *rxbuf; | ||
| 151 | u8 type, subtype; | ||
| 152 | u16 rxseq; | ||
| 153 | int tid = 0, index, cindex, rxdiff; | ||
| 154 | __le16 fc; | ||
| 155 | u8 *qc; | ||
| 156 | |||
| 157 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 158 | fc = hdr->frame_control; | ||
| 159 | |||
| 160 | /* collect stats of frames with non-zero version */ | ||
| 161 | |||
| 162 | if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_VERS) != 0) { | ||
| 163 | dev_kfree_skb(skb); | ||
| 164 | return -1; | ||
| 165 | } | ||
| 166 | |||
| 167 | type = le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_FTYPE; | ||
| 168 | subtype = le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_STYPE; | ||
| 169 | |||
| 170 | if (ieee80211_is_back_req(fc)) | ||
| 171 | return ath_bar_rx(sc, an, skb); | ||
| 172 | |||
| 173 | /* special aggregate processing only for qos unicast data frames */ | ||
| 174 | |||
| 175 | if (!ieee80211_is_data(fc) || | ||
| 176 | !ieee80211_is_data_qos(fc) || | ||
| 177 | is_multicast_ether_addr(hdr->addr1)) | ||
| 178 | return ath_rx_subframe(an, skb, rx_status); | ||
| 179 | |||
| 180 | /* lookup rx tid state */ | ||
| 181 | |||
| 182 | if (ieee80211_is_data_qos(fc)) { | ||
| 183 | qc = ieee80211_get_qos_ctl(hdr); | ||
| 184 | tid = qc[0] & 0xf; | ||
| 185 | } | ||
| 186 | |||
| 187 | if (sc->sc_opmode == ATH9K_M_STA) { | ||
| 188 | /* Drop the frame not belonging to me. */ | ||
| 189 | if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) { | ||
| 190 | dev_kfree_skb(skb); | ||
| 191 | return -1; | ||
| 192 | } | ||
| 193 | } | ||
| 194 | |||
| 195 | rxtid = &an->an_aggr.rx.tid[tid]; | ||
| 196 | |||
| 197 | spin_lock(&rxtid->tidlock); | ||
| 198 | |||
| 199 | rxdiff = (rxtid->baw_tail - rxtid->baw_head) & | ||
| 200 | (ATH_TID_MAX_BUFS - 1); | ||
| 201 | |||
| 202 | /* | ||
| 203 | * If the ADDBA exchange has not been completed by the source, | ||
| 204 | * process via legacy path (i.e. no reordering buffer is needed) | ||
| 205 | */ | ||
| 206 | if (!rxtid->addba_exchangecomplete) { | ||
| 207 | spin_unlock(&rxtid->tidlock); | ||
| 208 | return ath_rx_subframe(an, skb, rx_status); | ||
| 209 | } | ||
| 210 | |||
| 211 | /* extract sequence number from recvd frame */ | ||
| 212 | |||
| 213 | rxseq = le16_to_cpu(hdr->seq_ctrl) >> IEEE80211_SEQ_SEQ_SHIFT; | ||
| 214 | |||
| 215 | if (rxtid->seq_reset) { | ||
| 216 | rxtid->seq_reset = 0; | ||
| 217 | rxtid->seq_next = rxseq; | ||
| 218 | } | ||
| 219 | |||
| 220 | index = ATH_BA_INDEX(rxtid->seq_next, rxseq); | ||
| 221 | |||
| 222 | /* drop frame if old sequence (index is too large) */ | ||
| 223 | |||
| 224 | if (index > (IEEE80211_SEQ_MAX - (rxtid->baw_size << 2))) { | ||
| 225 | /* discard frame, ieee layer may not treat frame as a dup */ | ||
| 226 | spin_unlock(&rxtid->tidlock); | ||
| 227 | dev_kfree_skb(skb); | ||
| 228 | return IEEE80211_FTYPE_DATA; | ||
| 229 | } | ||
| 230 | |||
| 231 | /* sequence number is beyond block-ack window */ | ||
| 232 | |||
| 233 | if (index >= rxtid->baw_size) { | ||
| 234 | |||
| 235 | /* complete receive processing for all pending frames */ | ||
| 236 | |||
| 237 | while (index >= rxtid->baw_size) { | ||
| 238 | |||
| 239 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | ||
| 240 | |||
| 241 | if (rxbuf->rx_wbuf != NULL) { | ||
| 242 | ath_rx_subframe(an, rxbuf->rx_wbuf, | ||
| 243 | &rxbuf->rx_status); | ||
| 244 | rxbuf->rx_wbuf = NULL; | ||
| 245 | } | ||
| 246 | |||
| 247 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 248 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 249 | |||
| 250 | index--; | ||
| 251 | } | ||
| 252 | } | ||
| 253 | |||
| 254 | /* add buffer to the recv ba window */ | ||
| 255 | |||
| 256 | cindex = (rxtid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | ||
| 257 | rxbuf = rxtid->rxbuf + cindex; | ||
| 258 | |||
| 259 | if (rxbuf->rx_wbuf != NULL) { | ||
| 260 | spin_unlock(&rxtid->tidlock); | ||
| 261 | /* duplicate frame */ | ||
| 262 | dev_kfree_skb(skb); | ||
| 263 | return IEEE80211_FTYPE_DATA; | ||
| 264 | } | ||
| 265 | |||
| 266 | rxbuf->rx_wbuf = skb; | ||
| 267 | rxbuf->rx_time = get_timestamp(); | ||
| 268 | rxbuf->rx_status = *rx_status; | ||
| 269 | |||
| 270 | /* advance tail if sequence received is newer | ||
| 271 | * than any received so far */ | ||
| 272 | |||
| 273 | if (index >= rxdiff) { | ||
| 274 | rxtid->baw_tail = cindex; | ||
| 275 | INCR(rxtid->baw_tail, ATH_TID_MAX_BUFS); | ||
| 276 | } | ||
| 277 | |||
| 278 | /* indicate all in-order received frames */ | ||
| 279 | |||
| 280 | while (rxtid->baw_head != rxtid->baw_tail) { | ||
| 281 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | ||
| 282 | if (!rxbuf->rx_wbuf) | ||
| 283 | break; | ||
| 284 | |||
| 285 | ath_rx_subframe(an, rxbuf->rx_wbuf, &rxbuf->rx_status); | ||
| 286 | rxbuf->rx_wbuf = NULL; | ||
| 287 | |||
| 288 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 289 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 290 | } | ||
| 291 | |||
| 292 | /* | ||
| 293 | * start a timer to flush all received frames if there are pending | ||
| 294 | * receive frames | ||
| 295 | */ | ||
| 296 | if (rxtid->baw_head != rxtid->baw_tail) | ||
| 297 | mod_timer(&rxtid->timer, ATH_RX_TIMEOUT); | ||
| 298 | else | ||
| 299 | del_timer_sync(&rxtid->timer); | ||
| 300 | |||
| 301 | spin_unlock(&rxtid->tidlock); | ||
| 302 | return IEEE80211_FTYPE_DATA; | ||
| 303 | } | ||
| 304 | |||
| 305 | /* Timer to flush all received sub-frames */ | ||
| 306 | |||
| 307 | static void ath_rx_timer(unsigned long data) | ||
| 308 | { | ||
| 309 | struct ath_arx_tid *rxtid = (struct ath_arx_tid *)data; | ||
| 310 | struct ath_node *an = rxtid->an; | ||
| 311 | struct ath_rxbuf *rxbuf; | ||
| 312 | int nosched; | ||
| 313 | |||
| 314 | spin_lock_bh(&rxtid->tidlock); | ||
| 315 | while (rxtid->baw_head != rxtid->baw_tail) { | ||
| 316 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | ||
| 317 | if (!rxbuf->rx_wbuf) { | ||
| 318 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 319 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 320 | continue; | ||
| 321 | } | ||
| 322 | |||
| 323 | /* | ||
| 324 | * Stop if the next one is a very recent frame. | ||
| 325 | * | ||
| 326 | * Call get_timestamp in every iteration to protect against the | ||
| 327 | * case in which a new frame is received while we are executing | ||
| 328 | * this function. Using a timestamp obtained before entering | ||
| 329 | * the loop could lead to a very large time interval | ||
| 330 | * (a negative value typecast to unsigned), breaking the | ||
| 331 | * function's logic. | ||
| 332 | */ | ||
| 333 | if ((get_timestamp() - rxbuf->rx_time) < | ||
| 334 | (ATH_RX_TIMEOUT * HZ / 1000)) | ||
| 335 | break; | ||
| 336 | |||
| 337 | ath_rx_subframe(an, rxbuf->rx_wbuf, | ||
| 338 | &rxbuf->rx_status); | ||
| 339 | rxbuf->rx_wbuf = NULL; | ||
| 340 | |||
| 341 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 342 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 343 | } | ||
| 344 | |||
| 345 | /* | ||
| 346 | * start a timer to flush all received frames if there are pending | ||
| 347 | * receive frames | ||
| 348 | */ | ||
| 349 | if (rxtid->baw_head != rxtid->baw_tail) | ||
| 350 | nosched = 0; | ||
| 351 | else | ||
| 352 | nosched = 1; /* no need to re-arm the timer again */ | ||
| 353 | |||
| 354 | spin_unlock_bh(&rxtid->tidlock); | ||
| 355 | } | ||
| 356 | |||
| 357 | /* Free all pending sub-frames in the re-ordering buffer */ | ||
| 358 | |||
| 359 | static void ath_rx_flush_tid(struct ath_softc *sc, | ||
| 360 | struct ath_arx_tid *rxtid, int drop) | ||
| 361 | { | ||
| 362 | struct ath_rxbuf *rxbuf; | ||
| 363 | |||
| 364 | spin_lock_bh(&rxtid->tidlock); | ||
| 365 | while (rxtid->baw_head != rxtid->baw_tail) { | ||
| 366 | rxbuf = rxtid->rxbuf + rxtid->baw_head; | ||
| 367 | if (!rxbuf->rx_wbuf) { | ||
| 368 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 369 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 370 | continue; | ||
| 371 | } | ||
| 372 | |||
| 373 | if (drop) | ||
| 374 | dev_kfree_skb(rxbuf->rx_wbuf); | ||
| 375 | else | ||
| 376 | ath_rx_subframe(rxtid->an, | ||
| 377 | rxbuf->rx_wbuf, | ||
| 378 | &rxbuf->rx_status); | ||
| 379 | |||
| 380 | rxbuf->rx_wbuf = NULL; | ||
| 381 | |||
| 382 | INCR(rxtid->baw_head, ATH_TID_MAX_BUFS); | ||
| 383 | INCR(rxtid->seq_next, IEEE80211_SEQ_MAX); | ||
| 384 | } | ||
| 385 | spin_unlock_bh(&rxtid->tidlock); | ||
| 386 | } | ||
| 387 | |||
| 388 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, | ||
| 389 | u32 len) | ||
| 390 | { | ||
| 391 | struct sk_buff *skb; | ||
| 392 | u32 off; | ||
| 393 | |||
| 394 | /* | ||
| 395 | * Cache-line-align. This is important (for the | ||
| 396 | * 5210 at least) as not doing so causes bogus data | ||
| 397 | * in rx'd frames. | ||
| 398 | */ | ||
| 399 | |||
| 400 | skb = dev_alloc_skb(len + sc->sc_cachelsz - 1); | ||
| 401 | if (skb != NULL) { | ||
| 402 | off = ((unsigned long) skb->data) % sc->sc_cachelsz; | ||
| 403 | if (off != 0) | ||
| 404 | skb_reserve(skb, sc->sc_cachelsz - off); | ||
| 405 | } else { | ||
| 406 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 407 | "%s: skbuff alloc of size %u failed\n", | ||
| 408 | __func__, len); | ||
| 409 | return NULL; | ||
| 410 | } | ||
| 411 | |||
| 412 | return skb; | ||
| 413 | } | ||
| 414 | |||
| 415 | static void ath_rx_requeue(struct ath_softc *sc, struct sk_buff *skb) | ||
| 416 | { | ||
| 417 | struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf; | ||
| 418 | |||
| 419 | ASSERT(bf != NULL); | ||
| 420 | |||
| 421 | spin_lock_bh(&sc->sc_rxbuflock); | ||
| 422 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | ||
| 423 | /* | ||
| 424 | * This buffer is still held for hw acess. | ||
| 425 | * Mark it as free to be re-queued it later. | ||
| 426 | */ | ||
| 427 | bf->bf_status |= ATH_BUFSTATUS_FREE; | ||
| 428 | } else { | ||
| 429 | /* XXX: we probably never enter here, remove after | ||
| 430 | * verification */ | ||
| 431 | list_add_tail(&bf->list, &sc->sc_rxbuf); | ||
| 432 | ath_rx_buf_link(sc, bf); | ||
| 433 | } | ||
| 434 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 435 | } | ||
| 436 | |||
| 437 | /* | ||
| 438 | * The skb indicated to upper stack won't be returned to us. | ||
| 439 | * So we have to allocate a new one and queue it by ourselves. | ||
| 440 | */ | ||
| 441 | static int ath_rx_indicate(struct ath_softc *sc, | ||
| 442 | struct sk_buff *skb, | ||
| 443 | struct ath_recv_status *status, | ||
| 444 | u16 keyix) | ||
| 445 | { | ||
| 446 | struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf; | ||
| 447 | struct sk_buff *nskb; | ||
| 448 | int type; | ||
| 449 | |||
| 450 | /* indicate frame to the stack, which will free the old skb. */ | ||
| 451 | type = ath__rx_indicate(sc, skb, status, keyix); | ||
| 452 | |||
| 453 | /* allocate a new skb and queue it to for H/W processing */ | ||
| 454 | nskb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); | ||
| 455 | if (nskb != NULL) { | ||
| 456 | bf->bf_mpdu = nskb; | ||
| 457 | bf->bf_buf_addr = ath_skb_map_single(sc, | ||
| 458 | nskb, | ||
| 459 | PCI_DMA_FROMDEVICE, | ||
| 460 | /* XXX: Remove get_dma_mem_context() */ | ||
| 461 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 462 | ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf; | ||
| 463 | |||
| 464 | /* queue the new wbuf to H/W */ | ||
| 465 | ath_rx_requeue(sc, nskb); | ||
| 466 | } | ||
| 467 | |||
| 468 | return type; | ||
| 469 | } | ||
| 470 | |||
| 471 | static void ath_opmode_init(struct ath_softc *sc) | ||
| 472 | { | ||
| 473 | struct ath_hal *ah = sc->sc_ah; | ||
| 474 | u32 rfilt, mfilt[2]; | ||
| 475 | |||
| 476 | /* configure rx filter */ | ||
| 477 | rfilt = ath_calcrxfilter(sc); | ||
| 478 | ath9k_hw_setrxfilter(ah, rfilt); | ||
| 479 | |||
| 480 | /* configure bssid mask */ | ||
| 481 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) | ||
| 482 | ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); | ||
| 483 | |||
| 484 | /* configure operational mode */ | ||
| 485 | ath9k_hw_setopmode(ah); | ||
| 486 | |||
| 487 | /* Handle any link-level address change. */ | ||
| 488 | ath9k_hw_setmac(ah, sc->sc_myaddr); | ||
| 489 | |||
| 490 | /* calculate and install multicast filter */ | ||
| 491 | mfilt[0] = mfilt[1] = ~0; | ||
| 492 | |||
| 493 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); | ||
| 494 | DPRINTF(sc, ATH_DBG_CONFIG , | ||
| 495 | "%s: RX filter 0x%x, MC filter %08x:%08x\n", | ||
| 496 | __func__, rfilt, mfilt[0], mfilt[1]); | ||
| 497 | } | ||
| 498 | |||
| 499 | int ath_rx_init(struct ath_softc *sc, int nbufs) | ||
| 500 | { | ||
| 501 | struct sk_buff *skb; | ||
| 502 | struct ath_buf *bf; | ||
| 503 | int error = 0; | ||
| 504 | |||
| 505 | do { | ||
| 506 | spin_lock_init(&sc->sc_rxflushlock); | ||
| 507 | sc->sc_rxflush = 0; | ||
| 508 | spin_lock_init(&sc->sc_rxbuflock); | ||
| 509 | |||
| 510 | /* | ||
| 511 | * Cisco's VPN software requires that drivers be able to | ||
| 512 | * receive encapsulated frames that are larger than the MTU. | ||
| 513 | * Since we can't be sure how large a frame we'll get, setup | ||
| 514 | * to handle the larges on possible. | ||
| 515 | */ | ||
| 516 | sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN, | ||
| 517 | min(sc->sc_cachelsz, | ||
| 518 | (u16)64)); | ||
| 519 | |||
| 520 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n", | ||
| 521 | __func__, sc->sc_cachelsz, sc->sc_rxbufsize); | ||
| 522 | |||
| 523 | /* Initialize rx descriptors */ | ||
| 524 | |||
| 525 | error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, | ||
| 526 | "rx", nbufs, 1); | ||
| 527 | if (error != 0) { | ||
| 528 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 529 | "%s: failed to allocate rx descriptors: %d\n", | ||
| 530 | __func__, error); | ||
| 531 | break; | ||
| 532 | } | ||
| 533 | |||
| 534 | /* Pre-allocate a wbuf for each rx buffer */ | ||
| 535 | |||
| 536 | list_for_each_entry(bf, &sc->sc_rxbuf, list) { | ||
| 537 | skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); | ||
| 538 | if (skb == NULL) { | ||
| 539 | error = -ENOMEM; | ||
| 540 | break; | ||
| 541 | } | ||
| 542 | |||
| 543 | bf->bf_mpdu = skb; | ||
| 544 | bf->bf_buf_addr = | ||
| 545 | ath_skb_map_single(sc, skb, PCI_DMA_FROMDEVICE, | ||
| 546 | get_dma_mem_context(bf, bf_dmacontext)); | ||
| 547 | ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf; | ||
| 548 | } | ||
| 549 | sc->sc_rxlink = NULL; | ||
| 550 | |||
| 551 | } while (0); | ||
| 552 | |||
| 553 | if (error) | ||
| 554 | ath_rx_cleanup(sc); | ||
| 555 | |||
| 556 | return error; | ||
| 557 | } | ||
| 558 | |||
| 559 | /* Reclaim all rx queue resources */ | ||
| 560 | |||
| 561 | void ath_rx_cleanup(struct ath_softc *sc) | ||
| 562 | { | ||
| 563 | struct sk_buff *skb; | ||
| 564 | struct ath_buf *bf; | ||
| 565 | |||
| 566 | list_for_each_entry(bf, &sc->sc_rxbuf, list) { | ||
| 567 | skb = bf->bf_mpdu; | ||
| 568 | if (skb) | ||
| 569 | dev_kfree_skb(skb); | ||
| 570 | } | ||
| 571 | |||
| 572 | /* cleanup rx descriptors */ | ||
| 573 | |||
| 574 | if (sc->sc_rxdma.dd_desc_len != 0) | ||
| 575 | ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); | ||
| 576 | } | ||
| 577 | |||
| 578 | /* | ||
| 579 | * Calculate the receive filter according to the | ||
| 580 | * operating mode and state: | ||
| 581 | * | ||
| 582 | * o always accept unicast, broadcast, and multicast traffic | ||
| 583 | * o maintain current state of phy error reception (the hal | ||
| 584 | * may enable phy error frames for noise immunity work) | ||
| 585 | * o probe request frames are accepted only when operating in | ||
| 586 | * hostap, adhoc, or monitor modes | ||
| 587 | * o enable promiscuous mode according to the interface state | ||
| 588 | * o accept beacons: | ||
| 589 | * - when operating in adhoc mode so the 802.11 layer creates | ||
| 590 | * node table entries for peers, | ||
| 591 | * - when operating in station mode for collecting rssi data when | ||
| 592 | * the station is otherwise quiet, or | ||
| 593 | * - when operating as a repeater so we see repeater-sta beacons | ||
| 594 | * - when scanning | ||
| 595 | */ | ||
| 596 | |||
| 597 | u32 ath_calcrxfilter(struct ath_softc *sc) | ||
| 598 | { | ||
| 599 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | ||
| 600 | u32 rfilt; | ||
| 601 | |||
| 602 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | ||
| 603 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | ||
| 604 | | ATH9K_RX_FILTER_MCAST; | ||
| 605 | |||
| 606 | /* If not a STA, enable processing of Probe Requests */ | ||
| 607 | if (sc->sc_opmode != ATH9K_M_STA) | ||
| 608 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; | ||
| 609 | |||
| 610 | /* Can't set HOSTAP into promiscous mode */ | ||
| 611 | if (sc->sc_opmode == ATH9K_M_MONITOR) { | ||
| 612 | rfilt |= ATH9K_RX_FILTER_PROM; | ||
| 613 | /* ??? To prevent from sending ACK */ | ||
| 614 | rfilt &= ~ATH9K_RX_FILTER_UCAST; | ||
| 615 | } | ||
| 616 | |||
| 617 | if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS || | ||
| 618 | sc->sc_scanning) | ||
| 619 | rfilt |= ATH9K_RX_FILTER_BEACON; | ||
| 620 | |||
| 621 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames | ||
| 622 | & beacon frames */ | ||
| 623 | if (sc->sc_opmode == ATH9K_M_HOSTAP) | ||
| 624 | rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); | ||
| 625 | return rfilt; | ||
| 626 | #undef RX_FILTER_PRESERVE | ||
| 627 | } | ||
| 628 | |||
| 629 | /* Enable the receive h/w following a reset. */ | ||
| 630 | |||
| 631 | int ath_startrecv(struct ath_softc *sc) | ||
| 632 | { | ||
| 633 | struct ath_hal *ah = sc->sc_ah; | ||
| 634 | struct ath_buf *bf, *tbf; | ||
| 635 | |||
| 636 | spin_lock_bh(&sc->sc_rxbuflock); | ||
| 637 | if (list_empty(&sc->sc_rxbuf)) | ||
| 638 | goto start_recv; | ||
| 639 | |||
| 640 | sc->sc_rxlink = NULL; | ||
| 641 | list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) { | ||
| 642 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | ||
| 643 | /* restarting h/w, no need for holding descriptors */ | ||
| 644 | bf->bf_status &= ~ATH_BUFSTATUS_STALE; | ||
| 645 | /* | ||
| 646 | * Upper layer may not be done with the frame yet so | ||
| 647 | * we can't just re-queue it to hardware. Remove it | ||
| 648 | * from h/w queue. It'll be re-queued when upper layer | ||
| 649 | * returns the frame and ath_rx_requeue_mpdu is called. | ||
| 650 | */ | ||
| 651 | if (!(bf->bf_status & ATH_BUFSTATUS_FREE)) { | ||
| 652 | list_del(&bf->list); | ||
| 653 | continue; | ||
| 654 | } | ||
| 655 | } | ||
| 656 | /* chain descriptors */ | ||
| 657 | ath_rx_buf_link(sc, bf); | ||
| 658 | } | ||
| 659 | |||
| 660 | /* We could have deleted elements so the list may be empty now */ | ||
| 661 | if (list_empty(&sc->sc_rxbuf)) | ||
| 662 | goto start_recv; | ||
| 663 | |||
| 664 | bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); | ||
| 665 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); | ||
| 666 | ath9k_hw_rxena(ah); /* enable recv descriptors */ | ||
| 667 | |||
| 668 | start_recv: | ||
| 669 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 670 | ath_opmode_init(sc); /* set filters, etc. */ | ||
| 671 | ath9k_hw_startpcureceive(ah); /* re-enable PCU/DMA engine */ | ||
| 672 | return 0; | ||
| 673 | } | ||
| 674 | |||
| 675 | /* Disable the receive h/w in preparation for a reset. */ | ||
| 676 | |||
| 677 | bool ath_stoprecv(struct ath_softc *sc) | ||
| 678 | { | ||
| 679 | struct ath_hal *ah = sc->sc_ah; | ||
| 680 | u64 tsf; | ||
| 681 | bool stopped; | ||
| 682 | |||
| 683 | ath9k_hw_stoppcurecv(ah); /* disable PCU */ | ||
| 684 | ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */ | ||
| 685 | stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */ | ||
| 686 | mdelay(3); /* 3ms is long enough for 1 frame */ | ||
| 687 | tsf = ath9k_hw_gettsf64(ah); | ||
| 688 | sc->sc_rxlink = NULL; /* just in case */ | ||
| 689 | return stopped; | ||
| 690 | } | ||
| 691 | |||
| 692 | /* Flush receive queue */ | ||
| 693 | |||
| 694 | void ath_flushrecv(struct ath_softc *sc) | ||
| 695 | { | ||
| 696 | /* | ||
| 697 | * ath_rx_tasklet may be used to handle rx interrupt and flush receive | ||
| 698 | * queue at the same time. Use a lock to serialize the access of rx | ||
| 699 | * queue. | ||
| 700 | * ath_rx_tasklet cannot hold the spinlock while indicating packets. | ||
| 701 | * Instead, do not claim the spinlock but check for a flush in | ||
| 702 | * progress (see references to sc_rxflush) | ||
| 703 | */ | ||
| 704 | spin_lock_bh(&sc->sc_rxflushlock); | ||
| 705 | sc->sc_rxflush = 1; | ||
| 706 | |||
| 707 | ath_rx_tasklet(sc, 1); | ||
| 708 | |||
| 709 | sc->sc_rxflush = 0; | ||
| 710 | spin_unlock_bh(&sc->sc_rxflushlock); | ||
| 711 | } | ||
| 712 | |||
| 713 | /* Process an individual frame */ | ||
| 714 | |||
| 715 | int ath_rx_input(struct ath_softc *sc, | ||
| 716 | struct ath_node *an, | ||
| 717 | int is_ampdu, | ||
| 718 | struct sk_buff *skb, | ||
| 719 | struct ath_recv_status *rx_status, | ||
| 720 | enum ATH_RX_TYPE *status) | ||
| 721 | { | ||
| 722 | if (is_ampdu && sc->sc_rxaggr) { | ||
| 723 | *status = ATH_RX_CONSUMED; | ||
| 724 | return ath_ampdu_input(sc, an, skb, rx_status); | ||
| 725 | } else { | ||
| 726 | *status = ATH_RX_NON_CONSUMED; | ||
| 727 | return -1; | ||
| 728 | } | ||
| 729 | } | ||
| 730 | |||
| 731 | /* Process receive queue, as well as LED, etc. */ | ||
| 732 | |||
| 733 | int ath_rx_tasklet(struct ath_softc *sc, int flush) | ||
| 734 | { | ||
| 735 | #define PA2DESC(_sc, _pa) \ | ||
| 736 | ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ | ||
| 737 | ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) | ||
| 738 | |||
| 739 | struct ath_buf *bf, *bf_held = NULL; | ||
| 740 | struct ath_desc *ds; | ||
| 741 | struct ieee80211_hdr *hdr; | ||
| 742 | struct sk_buff *skb = NULL; | ||
| 743 | struct ath_recv_status rx_status; | ||
| 744 | struct ath_hal *ah = sc->sc_ah; | ||
| 745 | int type, rx_processed = 0; | ||
| 746 | u32 phyerr; | ||
| 747 | u8 chainreset = 0; | ||
| 748 | int retval; | ||
| 749 | __le16 fc; | ||
| 750 | |||
| 751 | do { | ||
| 752 | /* If handling rx interrupt and flush is in progress => exit */ | ||
| 753 | if (sc->sc_rxflush && (flush == 0)) | ||
| 754 | break; | ||
| 755 | |||
| 756 | spin_lock_bh(&sc->sc_rxbuflock); | ||
| 757 | if (list_empty(&sc->sc_rxbuf)) { | ||
| 758 | sc->sc_rxlink = NULL; | ||
| 759 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 760 | break; | ||
| 761 | } | ||
| 762 | |||
| 763 | bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); | ||
| 764 | |||
| 765 | /* | ||
| 766 | * There is a race condition that BH gets scheduled after sw | ||
| 767 | * writes RxE and before hw re-load the last descriptor to get | ||
| 768 | * the newly chained one. Software must keep the last DONE | ||
| 769 | * descriptor as a holding descriptor - software does so by | ||
| 770 | * marking it with the STALE flag. | ||
| 771 | */ | ||
| 772 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | ||
| 773 | bf_held = bf; | ||
| 774 | if (list_is_last(&bf_held->list, &sc->sc_rxbuf)) { | ||
| 775 | /* | ||
| 776 | * The holding descriptor is the last | ||
| 777 | * descriptor in queue. It's safe to | ||
| 778 | * remove the last holding descriptor | ||
| 779 | * in BH context. | ||
| 780 | */ | ||
| 781 | list_del(&bf_held->list); | ||
| 782 | bf_held->bf_status &= ~ATH_BUFSTATUS_STALE; | ||
| 783 | sc->sc_rxlink = NULL; | ||
| 784 | |||
| 785 | if (bf_held->bf_status & ATH_BUFSTATUS_FREE) { | ||
| 786 | list_add_tail(&bf_held->list, | ||
| 787 | &sc->sc_rxbuf); | ||
| 788 | ath_rx_buf_link(sc, bf_held); | ||
| 789 | } | ||
| 790 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 791 | break; | ||
| 792 | } | ||
| 793 | bf = list_entry(bf->list.next, struct ath_buf, list); | ||
| 794 | } | ||
| 795 | |||
| 796 | ds = bf->bf_desc; | ||
| 797 | ++rx_processed; | ||
| 798 | |||
| 799 | /* | ||
| 800 | * Must provide the virtual address of the current | ||
| 801 | * descriptor, the physical address, and the virtual | ||
| 802 | * address of the next descriptor in the h/w chain. | ||
| 803 | * This allows the HAL to look ahead to see if the | ||
| 804 | * hardware is done with a descriptor by checking the | ||
| 805 | * done bit in the following descriptor and the address | ||
| 806 | * of the current descriptor the DMA engine is working | ||
| 807 | * on. All this is necessary because of our use of | ||
| 808 | * a self-linked list to avoid rx overruns. | ||
| 809 | */ | ||
| 810 | retval = ath9k_hw_rxprocdesc(ah, | ||
| 811 | ds, | ||
| 812 | bf->bf_daddr, | ||
| 813 | PA2DESC(sc, ds->ds_link), | ||
| 814 | 0); | ||
| 815 | if (retval == -EINPROGRESS) { | ||
| 816 | struct ath_buf *tbf; | ||
| 817 | struct ath_desc *tds; | ||
| 818 | |||
| 819 | if (list_is_last(&bf->list, &sc->sc_rxbuf)) { | ||
| 820 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 821 | break; | ||
| 822 | } | ||
| 823 | |||
| 824 | tbf = list_entry(bf->list.next, struct ath_buf, list); | ||
| 825 | |||
| 826 | /* | ||
| 827 | * On some hardware the descriptor status words could | ||
| 828 | * get corrupted, including the done bit. Because of | ||
| 829 | * this, check if the next descriptor's done bit is | ||
| 830 | * set or not. | ||
| 831 | * | ||
| 832 | * If the next descriptor's done bit is set, the current | ||
| 833 | * descriptor has been corrupted. Force s/w to discard | ||
| 834 | * this descriptor and continue... | ||
| 835 | */ | ||
| 836 | |||
| 837 | tds = tbf->bf_desc; | ||
| 838 | retval = ath9k_hw_rxprocdesc(ah, | ||
| 839 | tds, tbf->bf_daddr, | ||
| 840 | PA2DESC(sc, tds->ds_link), 0); | ||
| 841 | if (retval == -EINPROGRESS) { | ||
| 842 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 843 | break; | ||
| 844 | } | ||
| 845 | } | ||
| 846 | |||
| 847 | /* XXX: we do not support frames spanning | ||
| 848 | * multiple descriptors */ | ||
| 849 | bf->bf_status |= ATH_BUFSTATUS_DONE; | ||
| 850 | |||
| 851 | skb = bf->bf_mpdu; | ||
| 852 | if (skb == NULL) { /* XXX ??? can this happen */ | ||
| 853 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 854 | continue; | ||
| 855 | } | ||
| 856 | /* | ||
| 857 | * Now we know it's a completed frame, we can indicate the | ||
| 858 | * frame. Remove the previous holding descriptor and leave | ||
| 859 | * this one in the queue as the new holding descriptor. | ||
| 860 | */ | ||
| 861 | if (bf_held) { | ||
| 862 | list_del(&bf_held->list); | ||
| 863 | bf_held->bf_status &= ~ATH_BUFSTATUS_STALE; | ||
| 864 | if (bf_held->bf_status & ATH_BUFSTATUS_FREE) { | ||
| 865 | list_add_tail(&bf_held->list, &sc->sc_rxbuf); | ||
| 866 | /* try to requeue this descriptor */ | ||
| 867 | ath_rx_buf_link(sc, bf_held); | ||
| 868 | } | ||
| 869 | } | ||
| 870 | |||
| 871 | bf->bf_status |= ATH_BUFSTATUS_STALE; | ||
| 872 | bf_held = bf; | ||
| 873 | /* | ||
| 874 | * Release the lock here in case ieee80211_input() return | ||
| 875 | * the frame immediately by calling ath_rx_mpdu_requeue(). | ||
| 876 | */ | ||
| 877 | spin_unlock_bh(&sc->sc_rxbuflock); | ||
| 878 | |||
| 879 | if (flush) { | ||
| 880 | /* | ||
| 881 | * If we're asked to flush receive queue, directly | ||
| 882 | * chain it back at the queue without processing it. | ||
| 883 | */ | ||
| 884 | goto rx_next; | ||
| 885 | } | ||
| 886 | |||
| 887 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 888 | fc = hdr->frame_control; | ||
| 889 | memzero(&rx_status, sizeof(struct ath_recv_status)); | ||
| 890 | |||
| 891 | if (ds->ds_rxstat.rs_more) { | ||
| 892 | /* | ||
| 893 | * Frame spans multiple descriptors; this | ||
| 894 | * cannot happen yet as we don't support | ||
| 895 | * jumbograms. If not in monitor mode, | ||
| 896 | * discard the frame. | ||
| 897 | */ | ||
| 898 | #ifndef ERROR_FRAMES | ||
| 899 | /* | ||
| 900 | * Enable this if you want to see | ||
| 901 | * error frames in Monitor mode. | ||
| 902 | */ | ||
| 903 | if (sc->sc_opmode != ATH9K_M_MONITOR) | ||
| 904 | goto rx_next; | ||
| 905 | #endif | ||
| 906 | /* fall thru for monitor mode handling... */ | ||
| 907 | } else if (ds->ds_rxstat.rs_status != 0) { | ||
| 908 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | ||
| 909 | rx_status.flags |= ATH_RX_FCS_ERROR; | ||
| 910 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) { | ||
| 911 | phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; | ||
| 912 | goto rx_next; | ||
| 913 | } | ||
| 914 | |||
| 915 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { | ||
| 916 | /* | ||
| 917 | * Decrypt error. We only mark packet status | ||
| 918 | * here and always push up the frame up to let | ||
| 919 | * mac80211 handle the actual error case, be | ||
| 920 | * it no decryption key or real decryption | ||
| 921 | * error. This let us keep statistics there. | ||
| 922 | */ | ||
| 923 | rx_status.flags |= ATH_RX_DECRYPT_ERROR; | ||
| 924 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | ||
| 925 | /* | ||
| 926 | * Demic error. We only mark frame status here | ||
| 927 | * and always push up the frame up to let | ||
| 928 | * mac80211 handle the actual error case. This | ||
| 929 | * let us keep statistics there. Hardware may | ||
| 930 | * post a false-positive MIC error. | ||
| 931 | */ | ||
| 932 | if (ieee80211_is_ctl(fc)) | ||
| 933 | /* | ||
| 934 | * Sometimes, we get invalid | ||
| 935 | * MIC failures on valid control frames. | ||
| 936 | * Remove these mic errors. | ||
| 937 | */ | ||
| 938 | ds->ds_rxstat.rs_status &= | ||
| 939 | ~ATH9K_RXERR_MIC; | ||
| 940 | else | ||
| 941 | rx_status.flags |= ATH_RX_MIC_ERROR; | ||
| 942 | } | ||
| 943 | /* | ||
| 944 | * Reject error frames with the exception of | ||
| 945 | * decryption and MIC failures. For monitor mode, | ||
| 946 | * we also ignore the CRC error. | ||
| 947 | */ | ||
| 948 | if (sc->sc_opmode == ATH9K_M_MONITOR) { | ||
| 949 | if (ds->ds_rxstat.rs_status & | ||
| 950 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | ||
| 951 | ATH9K_RXERR_CRC)) | ||
| 952 | goto rx_next; | ||
| 953 | } else { | ||
| 954 | if (ds->ds_rxstat.rs_status & | ||
| 955 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | ||
| 956 | goto rx_next; | ||
| 957 | } | ||
| 958 | } | ||
| 959 | } | ||
| 960 | /* | ||
| 961 | * The status portion of the descriptor could get corrupted. | ||
| 962 | */ | ||
| 963 | if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen) | ||
| 964 | goto rx_next; | ||
| 965 | /* | ||
| 966 | * Sync and unmap the frame. At this point we're | ||
| 967 | * committed to passing the sk_buff somewhere so | ||
| 968 | * clear buf_skb; this means a new sk_buff must be | ||
| 969 | * allocated when the rx descriptor is setup again | ||
| 970 | * to receive another frame. | ||
| 971 | */ | ||
| 972 | skb_put(skb, ds->ds_rxstat.rs_datalen); | ||
| 973 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | ||
| 974 | rx_status.tsf = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | ||
| 975 | rx_status.rateieee = | ||
| 976 | sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate; | ||
| 977 | rx_status.rateKbps = | ||
| 978 | sc->sc_hwmap[ds->ds_rxstat.rs_rate].rateKbps; | ||
| 979 | rx_status.ratecode = ds->ds_rxstat.rs_rate; | ||
| 980 | |||
| 981 | /* HT rate */ | ||
| 982 | if (rx_status.ratecode & 0x80) { | ||
| 983 | /* TODO - add table to avoid division */ | ||
| 984 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) { | ||
| 985 | rx_status.flags |= ATH_RX_40MHZ; | ||
| 986 | rx_status.rateKbps = | ||
| 987 | (rx_status.rateKbps * 27) / 13; | ||
| 988 | } | ||
| 989 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) | ||
| 990 | rx_status.rateKbps = | ||
| 991 | (rx_status.rateKbps * 10) / 9; | ||
| 992 | else | ||
| 993 | rx_status.flags |= ATH_RX_SHORT_GI; | ||
| 994 | } | ||
| 995 | |||
| 996 | /* sc->sc_noise_floor is only available when the station | ||
| 997 | attaches to an AP, so we use a default value | ||
| 998 | if we are not yet attached. */ | ||
| 999 | |||
| 1000 | /* XXX we should use either sc->sc_noise_floor or | ||
| 1001 | * ath_hal_getChanNoise(ah, &sc->sc_curchan) | ||
| 1002 | * to calculate the noise floor. | ||
| 1003 | * However, the value returned by ath_hal_getChanNoise | ||
| 1004 | * seems to be incorrect (-31dBm on the last test), | ||
| 1005 | * so we will use a hard-coded value until we | ||
| 1006 | * figure out what is going on. | ||
| 1007 | */ | ||
| 1008 | rx_status.abs_rssi = | ||
| 1009 | ds->ds_rxstat.rs_rssi + ATH_DEFAULT_NOISE_FLOOR; | ||
| 1010 | |||
| 1011 | pci_dma_sync_single_for_cpu(sc->pdev, | ||
| 1012 | bf->bf_buf_addr, | ||
| 1013 | skb_tailroom(skb), | ||
| 1014 | PCI_DMA_FROMDEVICE); | ||
| 1015 | pci_unmap_single(sc->pdev, | ||
| 1016 | bf->bf_buf_addr, | ||
| 1017 | sc->sc_rxbufsize, | ||
| 1018 | PCI_DMA_FROMDEVICE); | ||
| 1019 | |||
| 1020 | /* XXX: Ah! make me more readable, use a helper */ | ||
| 1021 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { | ||
| 1022 | if (ds->ds_rxstat.rs_moreaggr == 0) { | ||
| 1023 | rx_status.rssictl[0] = | ||
| 1024 | ds->ds_rxstat.rs_rssi_ctl0; | ||
| 1025 | rx_status.rssictl[1] = | ||
| 1026 | ds->ds_rxstat.rs_rssi_ctl1; | ||
| 1027 | rx_status.rssictl[2] = | ||
| 1028 | ds->ds_rxstat.rs_rssi_ctl2; | ||
| 1029 | rx_status.rssi = ds->ds_rxstat.rs_rssi; | ||
| 1030 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) { | ||
| 1031 | rx_status.rssiextn[0] = | ||
| 1032 | ds->ds_rxstat.rs_rssi_ext0; | ||
| 1033 | rx_status.rssiextn[1] = | ||
| 1034 | ds->ds_rxstat.rs_rssi_ext1; | ||
| 1035 | rx_status.rssiextn[2] = | ||
| 1036 | ds->ds_rxstat.rs_rssi_ext2; | ||
| 1037 | rx_status.flags |= | ||
| 1038 | ATH_RX_RSSI_EXTN_VALID; | ||
| 1039 | } | ||
| 1040 | rx_status.flags |= ATH_RX_RSSI_VALID | | ||
| 1041 | ATH_RX_CHAIN_RSSI_VALID; | ||
| 1042 | } | ||
| 1043 | } else { | ||
| 1044 | /* | ||
| 1045 | * Need to insert the "combined" rssi into the | ||
| 1046 | * status structure for upper layer processing | ||
| 1047 | */ | ||
| 1048 | rx_status.rssi = ds->ds_rxstat.rs_rssi; | ||
| 1049 | rx_status.flags |= ATH_RX_RSSI_VALID; | ||
| 1050 | } | ||
| 1051 | |||
| 1052 | /* Pass frames up to the stack. */ | ||
| 1053 | |||
| 1054 | type = ath_rx_indicate(sc, skb, | ||
| 1055 | &rx_status, ds->ds_rxstat.rs_keyix); | ||
| 1056 | |||
| 1057 | /* | ||
| 1058 | * change the default rx antenna if rx diversity chooses the | ||
| 1059 | * other antenna 3 times in a row. | ||
| 1060 | */ | ||
| 1061 | if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { | ||
| 1062 | if (++sc->sc_rxotherant >= 3) | ||
| 1063 | ath_setdefantenna(sc, | ||
| 1064 | ds->ds_rxstat.rs_antenna); | ||
| 1065 | } else { | ||
| 1066 | sc->sc_rxotherant = 0; | ||
| 1067 | } | ||
| 1068 | |||
| 1069 | #ifdef CONFIG_SLOW_ANT_DIV | ||
| 1070 | if ((rx_status.flags & ATH_RX_RSSI_VALID) && | ||
| 1071 | ieee80211_is_beacon(fc)) { | ||
| 1072 | ath_slow_ant_div(&sc->sc_antdiv, hdr, &ds->ds_rxstat); | ||
| 1073 | } | ||
| 1074 | #endif | ||
| 1075 | /* | ||
| 1076 | * For frames successfully indicated, the buffer will be | ||
| 1077 | * returned to us by upper layers by calling | ||
| 1078 | * ath_rx_mpdu_requeue, either synchronusly or asynchronously. | ||
| 1079 | * So we don't want to do it here in this loop. | ||
| 1080 | */ | ||
| 1081 | continue; | ||
| 1082 | |||
| 1083 | rx_next: | ||
| 1084 | bf->bf_status |= ATH_BUFSTATUS_FREE; | ||
| 1085 | } while (TRUE); | ||
| 1086 | |||
| 1087 | if (chainreset) { | ||
| 1088 | DPRINTF(sc, ATH_DBG_CONFIG, | ||
| 1089 | "%s: Reset rx chain mask. " | ||
| 1090 | "Do internal reset\n", __func__); | ||
| 1091 | ASSERT(flush == 0); | ||
| 1092 | ath_internal_reset(sc); | ||
| 1093 | } | ||
| 1094 | |||
| 1095 | return 0; | ||
| 1096 | #undef PA2DESC | ||
| 1097 | } | ||
| 1098 | |||
| 1099 | /* Process ADDBA request in per-TID data structure */ | ||
| 1100 | |||
| 1101 | int ath_rx_aggr_start(struct ath_softc *sc, | ||
| 1102 | const u8 *addr, | ||
| 1103 | u16 tid, | ||
| 1104 | u16 *ssn) | ||
| 1105 | { | ||
| 1106 | struct ath_arx_tid *rxtid; | ||
| 1107 | struct ath_node *an; | ||
| 1108 | struct ieee80211_hw *hw = sc->hw; | ||
| 1109 | struct ieee80211_supported_band *sband; | ||
| 1110 | u16 buffersize = 0; | ||
| 1111 | |||
| 1112 | spin_lock_bh(&sc->node_lock); | ||
| 1113 | an = ath_node_find(sc, (u8 *) addr); | ||
| 1114 | spin_unlock_bh(&sc->node_lock); | ||
| 1115 | |||
| 1116 | if (!an) { | ||
| 1117 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1118 | "%s: Node not found to initialize RX aggregation\n", | ||
| 1119 | __func__); | ||
| 1120 | return -1; | ||
| 1121 | } | ||
| 1122 | |||
| 1123 | sband = hw->wiphy->bands[hw->conf.channel->band]; | ||
| 1124 | buffersize = IEEE80211_MIN_AMPDU_BUF << | ||
| 1125 | sband->ht_info.ampdu_factor; /* FIXME */ | ||
| 1126 | |||
| 1127 | rxtid = &an->an_aggr.rx.tid[tid]; | ||
| 1128 | |||
| 1129 | spin_lock_bh(&rxtid->tidlock); | ||
| 1130 | if (sc->sc_rxaggr) { | ||
| 1131 | /* Allow aggregation reception | ||
| 1132 | * Adjust rx BA window size. Peer might indicate a | ||
| 1133 | * zero buffer size for a _dont_care_ condition. | ||
| 1134 | */ | ||
| 1135 | if (buffersize) | ||
| 1136 | rxtid->baw_size = min(buffersize, rxtid->baw_size); | ||
| 1137 | |||
| 1138 | /* set rx sequence number */ | ||
| 1139 | rxtid->seq_next = *ssn; | ||
| 1140 | |||
| 1141 | /* Allocate the receive buffers for this TID */ | ||
| 1142 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1143 | "%s: Allcating rxbuffer for TID %d\n", __func__, tid); | ||
| 1144 | |||
| 1145 | if (rxtid->rxbuf == NULL) { | ||
| 1146 | /* | ||
| 1147 | * If the rxbuff is not NULL at this point, we *probably* | ||
| 1148 | * already allocated the buffer on a previous ADDBA, | ||
| 1149 | * and this is a subsequent ADDBA that got through. | ||
| 1150 | * Don't allocate, but use the value in the pointer, | ||
| 1151 | * we zero it out when we de-allocate. | ||
| 1152 | */ | ||
| 1153 | rxtid->rxbuf = kmalloc(ATH_TID_MAX_BUFS * | ||
| 1154 | sizeof(struct ath_rxbuf), GFP_ATOMIC); | ||
| 1155 | } | ||
| 1156 | if (rxtid->rxbuf == NULL) { | ||
| 1157 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1158 | "%s: Unable to allocate RX buffer, " | ||
| 1159 | "refusing ADDBA\n", __func__); | ||
| 1160 | } else { | ||
| 1161 | /* Ensure the memory is zeroed out (all internal | ||
| 1162 | * pointers are null) */ | ||
| 1163 | memzero(rxtid->rxbuf, ATH_TID_MAX_BUFS * | ||
| 1164 | sizeof(struct ath_rxbuf)); | ||
| 1165 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1166 | "%s: Allocated @%p\n", __func__, rxtid->rxbuf); | ||
| 1167 | |||
| 1168 | /* Allow aggregation reception */ | ||
| 1169 | rxtid->addba_exchangecomplete = 1; | ||
| 1170 | } | ||
| 1171 | } | ||
| 1172 | spin_unlock_bh(&rxtid->tidlock); | ||
| 1173 | |||
| 1174 | return 0; | ||
| 1175 | } | ||
| 1176 | |||
| 1177 | /* Process DELBA */ | ||
| 1178 | |||
| 1179 | int ath_rx_aggr_stop(struct ath_softc *sc, | ||
| 1180 | const u8 *addr, | ||
| 1181 | u16 tid) | ||
| 1182 | { | ||
| 1183 | struct ath_node *an; | ||
| 1184 | |||
| 1185 | spin_lock_bh(&sc->node_lock); | ||
| 1186 | an = ath_node_find(sc, (u8 *) addr); | ||
| 1187 | spin_unlock_bh(&sc->node_lock); | ||
| 1188 | |||
| 1189 | if (!an) { | ||
| 1190 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1191 | "%s: RX aggr stop for non-existent node\n", __func__); | ||
| 1192 | return -1; | ||
| 1193 | } | ||
| 1194 | |||
| 1195 | ath_rx_aggr_teardown(sc, an, tid); | ||
| 1196 | return 0; | ||
| 1197 | } | ||
| 1198 | |||
| 1199 | /* Rx aggregation tear down */ | ||
| 1200 | |||
| 1201 | void ath_rx_aggr_teardown(struct ath_softc *sc, | ||
| 1202 | struct ath_node *an, u8 tid) | ||
| 1203 | { | ||
| 1204 | struct ath_arx_tid *rxtid = &an->an_aggr.rx.tid[tid]; | ||
| 1205 | |||
| 1206 | if (!rxtid->addba_exchangecomplete) | ||
| 1207 | return; | ||
| 1208 | |||
| 1209 | del_timer_sync(&rxtid->timer); | ||
| 1210 | ath_rx_flush_tid(sc, rxtid, 0); | ||
| 1211 | rxtid->addba_exchangecomplete = 0; | ||
| 1212 | |||
| 1213 | /* De-allocate the receive buffer array allocated when addba started */ | ||
| 1214 | |||
| 1215 | if (rxtid->rxbuf) { | ||
| 1216 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 1217 | "%s: Deallocating TID %d rxbuff @%p\n", | ||
| 1218 | __func__, tid, rxtid->rxbuf); | ||
| 1219 | kfree(rxtid->rxbuf); | ||
| 1220 | |||
| 1221 | /* Set pointer to null to avoid reuse*/ | ||
| 1222 | rxtid->rxbuf = NULL; | ||
| 1223 | } | ||
| 1224 | } | ||
| 1225 | |||
| 1226 | /* Initialize per-node receive state */ | ||
| 1227 | |||
| 1228 | void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an) | ||
| 1229 | { | ||
| 1230 | if (sc->sc_rxaggr) { | ||
| 1231 | struct ath_arx_tid *rxtid; | ||
| 1232 | int tidno; | ||
| 1233 | |||
| 1234 | /* Init per tid rx state */ | ||
| 1235 | for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno]; | ||
| 1236 | tidno < WME_NUM_TID; | ||
| 1237 | tidno++, rxtid++) { | ||
| 1238 | rxtid->an = an; | ||
| 1239 | rxtid->seq_reset = 1; | ||
| 1240 | rxtid->seq_next = 0; | ||
| 1241 | rxtid->baw_size = WME_MAX_BA; | ||
| 1242 | rxtid->baw_head = rxtid->baw_tail = 0; | ||
| 1243 | |||
| 1244 | /* | ||
| 1245 | * Ensure the buffer pointer is null at this point | ||
| 1246 | * (needs to be allocated when addba is received) | ||
| 1247 | */ | ||
| 1248 | |||
| 1249 | rxtid->rxbuf = NULL; | ||
| 1250 | setup_timer(&rxtid->timer, ath_rx_timer, | ||
| 1251 | (unsigned long)rxtid); | ||
| 1252 | spin_lock_init(&rxtid->tidlock); | ||
| 1253 | |||
| 1254 | /* ADDBA state */ | ||
| 1255 | rxtid->addba_exchangecomplete = 0; | ||
| 1256 | } | ||
| 1257 | } | ||
| 1258 | } | ||
| 1259 | |||
| 1260 | void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an) | ||
| 1261 | { | ||
| 1262 | if (sc->sc_rxaggr) { | ||
| 1263 | struct ath_arx_tid *rxtid; | ||
| 1264 | int tidno, i; | ||
| 1265 | |||
| 1266 | /* Init per tid rx state */ | ||
| 1267 | for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno]; | ||
| 1268 | tidno < WME_NUM_TID; | ||
| 1269 | tidno++, rxtid++) { | ||
| 1270 | |||
| 1271 | if (!rxtid->addba_exchangecomplete) | ||
| 1272 | continue; | ||
| 1273 | |||
| 1274 | /* must cancel timer first */ | ||
| 1275 | del_timer_sync(&rxtid->timer); | ||
| 1276 | |||
| 1277 | /* drop any pending sub-frames */ | ||
| 1278 | ath_rx_flush_tid(sc, rxtid, 1); | ||
| 1279 | |||
| 1280 | for (i = 0; i < ATH_TID_MAX_BUFS; i++) | ||
| 1281 | ASSERT(rxtid->rxbuf[i].rx_wbuf == NULL); | ||
| 1282 | |||
| 1283 | rxtid->addba_exchangecomplete = 0; | ||
| 1284 | } | ||
| 1285 | } | ||
| 1286 | |||
| 1287 | } | ||
| 1288 | |||
| 1289 | /* Cleanup per-node receive state */ | ||
| 1290 | |||
| 1291 | void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an) | ||
| 1292 | { | ||
| 1293 | ath_rx_node_cleanup(sc, an); | ||
| 1294 | } | ||
| 1295 | |||
| 1296 | dma_addr_t ath_skb_map_single(struct ath_softc *sc, | ||
| 1297 | struct sk_buff *skb, | ||
| 1298 | int direction, | ||
| 1299 | dma_addr_t *pa) | ||
| 1300 | { | ||
| 1301 | /* | ||
| 1302 | * NB: do NOT use skb->len, which is 0 on initialization. | ||
| 1303 | * Use skb's entire data area instead. | ||
| 1304 | */ | ||
| 1305 | *pa = pci_map_single(sc->pdev, skb->data, | ||
| 1306 | skb_end_pointer(skb) - skb->head, direction); | ||
| 1307 | return *pa; | ||
| 1308 | } | ||
| 1309 | |||
| 1310 | void ath_skb_unmap_single(struct ath_softc *sc, | ||
| 1311 | struct sk_buff *skb, | ||
| 1312 | int direction, | ||
| 1313 | dma_addr_t *pa) | ||
| 1314 | { | ||
| 1315 | /* Unmap skb's entire data area */ | ||
| 1316 | pci_unmap_single(sc->pdev, *pa, | ||
| 1317 | skb_end_pointer(skb) - skb->head, direction); | ||
| 1318 | } | ||
diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h new file mode 100644 index 000000000000..42b0890a4685 --- /dev/null +++ b/drivers/net/wireless/ath9k/reg.h | |||
| @@ -0,0 +1,1385 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_H | ||
| 18 | #define REG_H | ||
| 19 | |||
| 20 | #define AR_CR 0x0008 | ||
| 21 | #define AR_CR_RXE 0x00000004 | ||
| 22 | #define AR_CR_RXD 0x00000020 | ||
| 23 | #define AR_CR_SWI 0x00000040 | ||
| 24 | |||
| 25 | #define AR_RXDP 0x000C | ||
| 26 | |||
| 27 | #define AR_CFG 0x0014 | ||
| 28 | #define AR_CFG_SWTD 0x00000001 | ||
| 29 | #define AR_CFG_SWTB 0x00000002 | ||
| 30 | #define AR_CFG_SWRD 0x00000004 | ||
| 31 | #define AR_CFG_SWRB 0x00000008 | ||
| 32 | #define AR_CFG_SWRG 0x00000010 | ||
| 33 | #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 | ||
| 34 | #define AR_CFG_PHOK 0x00000100 | ||
| 35 | #define AR_CFG_CLK_GATE_DIS 0x00000400 | ||
| 36 | #define AR_CFG_EEBS 0x00000200 | ||
| 37 | #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 | ||
| 38 | #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 | ||
| 39 | |||
| 40 | #define AR_MIRT 0x0020 | ||
| 41 | #define AR_MIRT_VAL 0x0000ffff | ||
| 42 | #define AR_MIRT_VAL_S 16 | ||
| 43 | |||
| 44 | #define AR_IER 0x0024 | ||
| 45 | #define AR_IER_ENABLE 0x00000001 | ||
| 46 | #define AR_IER_DISABLE 0x00000000 | ||
| 47 | |||
| 48 | #define AR_TIMT 0x0028 | ||
| 49 | #define AR_TIMT_LAST 0x0000ffff | ||
| 50 | #define AR_TIMT_LAST_S 0 | ||
| 51 | #define AR_TIMT_FIRST 0xffff0000 | ||
| 52 | #define AR_TIMT_FIRST_S 16 | ||
| 53 | |||
| 54 | #define AR_RIMT 0x002C | ||
| 55 | #define AR_RIMT_LAST 0x0000ffff | ||
| 56 | #define AR_RIMT_LAST_S 0 | ||
| 57 | #define AR_RIMT_FIRST 0xffff0000 | ||
| 58 | #define AR_RIMT_FIRST_S 16 | ||
| 59 | |||
| 60 | #define AR_DMASIZE_4B 0x00000000 | ||
| 61 | #define AR_DMASIZE_8B 0x00000001 | ||
| 62 | #define AR_DMASIZE_16B 0x00000002 | ||
| 63 | #define AR_DMASIZE_32B 0x00000003 | ||
| 64 | #define AR_DMASIZE_64B 0x00000004 | ||
| 65 | #define AR_DMASIZE_128B 0x00000005 | ||
| 66 | #define AR_DMASIZE_256B 0x00000006 | ||
| 67 | #define AR_DMASIZE_512B 0x00000007 | ||
| 68 | |||
| 69 | #define AR_TXCFG 0x0030 | ||
| 70 | #define AR_TXCFG_DMASZ_MASK 0x00000003 | ||
| 71 | #define AR_TXCFG_DMASZ_4B 0 | ||
| 72 | #define AR_TXCFG_DMASZ_8B 1 | ||
| 73 | #define AR_TXCFG_DMASZ_16B 2 | ||
| 74 | #define AR_TXCFG_DMASZ_32B 3 | ||
| 75 | #define AR_TXCFG_DMASZ_64B 4 | ||
| 76 | #define AR_TXCFG_DMASZ_128B 5 | ||
| 77 | #define AR_TXCFG_DMASZ_256B 6 | ||
| 78 | #define AR_TXCFG_DMASZ_512B 7 | ||
| 79 | #define AR_FTRIG 0x000003F0 | ||
| 80 | #define AR_FTRIG_S 4 | ||
| 81 | #define AR_FTRIG_IMMED 0x00000000 | ||
| 82 | #define AR_FTRIG_64B 0x00000010 | ||
| 83 | #define AR_FTRIG_128B 0x00000020 | ||
| 84 | #define AR_FTRIG_192B 0x00000030 | ||
| 85 | #define AR_FTRIG_256B 0x00000040 | ||
| 86 | #define AR_FTRIG_512B 0x00000080 | ||
| 87 | #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 | ||
| 88 | |||
| 89 | #define AR_RXCFG 0x0034 | ||
| 90 | #define AR_RXCFG_CHIRP 0x00000008 | ||
| 91 | #define AR_RXCFG_ZLFDMA 0x00000010 | ||
| 92 | #define AR_RXCFG_DMASZ_MASK 0x00000007 | ||
| 93 | #define AR_RXCFG_DMASZ_4B 0 | ||
| 94 | #define AR_RXCFG_DMASZ_8B 1 | ||
| 95 | #define AR_RXCFG_DMASZ_16B 2 | ||
| 96 | #define AR_RXCFG_DMASZ_32B 3 | ||
| 97 | #define AR_RXCFG_DMASZ_64B 4 | ||
| 98 | #define AR_RXCFG_DMASZ_128B 5 | ||
| 99 | #define AR_RXCFG_DMASZ_256B 6 | ||
| 100 | #define AR_RXCFG_DMASZ_512B 7 | ||
| 101 | |||
| 102 | #define AR_MIBC 0x0040 | ||
| 103 | #define AR_MIBC_COW 0x00000001 | ||
| 104 | #define AR_MIBC_FMC 0x00000002 | ||
| 105 | #define AR_MIBC_CMC 0x00000004 | ||
| 106 | #define AR_MIBC_MCS 0x00000008 | ||
| 107 | |||
| 108 | #define AR_TOPS 0x0044 | ||
| 109 | #define AR_TOPS_MASK 0x0000FFFF | ||
| 110 | |||
| 111 | #define AR_RXNPTO 0x0048 | ||
| 112 | #define AR_RXNPTO_MASK 0x000003FF | ||
| 113 | |||
| 114 | #define AR_TXNPTO 0x004C | ||
| 115 | #define AR_TXNPTO_MASK 0x000003FF | ||
| 116 | #define AR_TXNPTO_QCU_MASK 0x000FFC00 | ||
| 117 | |||
| 118 | #define AR_RPGTO 0x0050 | ||
| 119 | #define AR_RPGTO_MASK 0x000003FF | ||
| 120 | |||
| 121 | #define AR_RPCNT 0x0054 | ||
| 122 | #define AR_RPCNT_MASK 0x0000001F | ||
| 123 | |||
| 124 | #define AR_MACMISC 0x0058 | ||
| 125 | #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 | ||
| 126 | #define AR_MACMISC_DMA_OBS 0x000001E0 | ||
| 127 | #define AR_MACMISC_DMA_OBS_S 5 | ||
| 128 | #define AR_MACMISC_DMA_OBS_LINE_0 0 | ||
| 129 | #define AR_MACMISC_DMA_OBS_LINE_1 1 | ||
| 130 | #define AR_MACMISC_DMA_OBS_LINE_2 2 | ||
| 131 | #define AR_MACMISC_DMA_OBS_LINE_3 3 | ||
| 132 | #define AR_MACMISC_DMA_OBS_LINE_4 4 | ||
| 133 | #define AR_MACMISC_DMA_OBS_LINE_5 5 | ||
| 134 | #define AR_MACMISC_DMA_OBS_LINE_6 6 | ||
| 135 | #define AR_MACMISC_DMA_OBS_LINE_7 7 | ||
| 136 | #define AR_MACMISC_DMA_OBS_LINE_8 8 | ||
| 137 | #define AR_MACMISC_MISC_OBS 0x00000E00 | ||
| 138 | #define AR_MACMISC_MISC_OBS_S 9 | ||
| 139 | #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 | ||
| 140 | #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 | ||
| 141 | #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 | ||
| 142 | #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 | ||
| 143 | #define AR_MACMISC_MISC_OBS_BUS_1 1 | ||
| 144 | |||
| 145 | #define AR_GTXTO 0x0064 | ||
| 146 | #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF | ||
| 147 | #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 | ||
| 148 | #define AR_GTXTO_TIMEOUT_LIMIT_S 16 | ||
| 149 | |||
| 150 | #define AR_GTTM 0x0068 | ||
| 151 | #define AR_GTTM_USEC 0x00000001 | ||
| 152 | #define AR_GTTM_IGNORE_IDLE 0x00000002 | ||
| 153 | #define AR_GTTM_RESET_IDLE 0x00000004 | ||
| 154 | #define AR_GTTM_CST_USEC 0x00000008 | ||
| 155 | |||
| 156 | #define AR_CST 0x006C | ||
| 157 | #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF | ||
| 158 | #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 | ||
| 159 | #define AR_CST_TIMEOUT_LIMIT_S 16 | ||
| 160 | |||
| 161 | #define AR_SREV_VERSION_9100 0x014 | ||
| 162 | |||
| 163 | #define AR_SREV_5416_V20_OR_LATER(_ah) \ | ||
| 164 | (AR_SREV_9100((_ah)) || AR_SREV_5416_20_OR_LATER(_ah)) | ||
| 165 | #define AR_SREV_5416_V22_OR_LATER(_ah) \ | ||
| 166 | (AR_SREV_9100((_ah)) || AR_SREV_5416_22_OR_LATER(_ah)) | ||
| 167 | |||
| 168 | #define AR_ISR 0x0080 | ||
| 169 | #define AR_ISR_RXOK 0x00000001 | ||
| 170 | #define AR_ISR_RXDESC 0x00000002 | ||
| 171 | #define AR_ISR_RXERR 0x00000004 | ||
| 172 | #define AR_ISR_RXNOPKT 0x00000008 | ||
| 173 | #define AR_ISR_RXEOL 0x00000010 | ||
| 174 | #define AR_ISR_RXORN 0x00000020 | ||
| 175 | #define AR_ISR_TXOK 0x00000040 | ||
| 176 | #define AR_ISR_TXDESC 0x00000080 | ||
| 177 | #define AR_ISR_TXERR 0x00000100 | ||
| 178 | #define AR_ISR_TXNOPKT 0x00000200 | ||
| 179 | #define AR_ISR_TXEOL 0x00000400 | ||
| 180 | #define AR_ISR_TXURN 0x00000800 | ||
| 181 | #define AR_ISR_MIB 0x00001000 | ||
| 182 | #define AR_ISR_SWI 0x00002000 | ||
| 183 | #define AR_ISR_RXPHY 0x00004000 | ||
| 184 | #define AR_ISR_RXKCM 0x00008000 | ||
| 185 | #define AR_ISR_SWBA 0x00010000 | ||
| 186 | #define AR_ISR_BRSSI 0x00020000 | ||
| 187 | #define AR_ISR_BMISS 0x00040000 | ||
| 188 | #define AR_ISR_BNR 0x00100000 | ||
| 189 | #define AR_ISR_RXCHIRP 0x00200000 | ||
| 190 | #define AR_ISR_BCNMISC 0x00800000 | ||
| 191 | #define AR_ISR_TIM 0x00800000 | ||
| 192 | #define AR_ISR_QCBROVF 0x02000000 | ||
| 193 | #define AR_ISR_QCBRURN 0x04000000 | ||
| 194 | #define AR_ISR_QTRIG 0x08000000 | ||
| 195 | #define AR_ISR_GENTMR 0x10000000 | ||
| 196 | |||
| 197 | #define AR_ISR_TXMINTR 0x00080000 | ||
| 198 | #define AR_ISR_RXMINTR 0x01000000 | ||
| 199 | #define AR_ISR_TXINTM 0x40000000 | ||
| 200 | #define AR_ISR_RXINTM 0x80000000 | ||
| 201 | |||
| 202 | #define AR_ISR_S0 0x0084 | ||
| 203 | #define AR_ISR_S0_QCU_TXOK 0x000003FF | ||
| 204 | #define AR_ISR_S0_QCU_TXOK_S 0 | ||
| 205 | #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 | ||
| 206 | #define AR_ISR_S0_QCU_TXDESC_S 16 | ||
| 207 | |||
| 208 | #define AR_ISR_S1 0x0088 | ||
| 209 | #define AR_ISR_S1_QCU_TXERR 0x000003FF | ||
| 210 | #define AR_ISR_S1_QCU_TXERR_S 0 | ||
| 211 | #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 | ||
| 212 | #define AR_ISR_S1_QCU_TXEOL_S 16 | ||
| 213 | |||
| 214 | #define AR_ISR_S2 0x008c | ||
| 215 | #define AR_ISR_S2_QCU_TXURN 0x000003FF | ||
| 216 | #define AR_ISR_S2_CST 0x00400000 | ||
| 217 | #define AR_ISR_S2_GTT 0x00800000 | ||
| 218 | #define AR_ISR_S2_TIM 0x01000000 | ||
| 219 | #define AR_ISR_S2_CABEND 0x02000000 | ||
| 220 | #define AR_ISR_S2_DTIMSYNC 0x04000000 | ||
| 221 | #define AR_ISR_S2_BCNTO 0x08000000 | ||
| 222 | #define AR_ISR_S2_CABTO 0x10000000 | ||
| 223 | #define AR_ISR_S2_DTIM 0x20000000 | ||
| 224 | #define AR_ISR_S2_TSFOOR 0x40000000 | ||
| 225 | #define AR_ISR_S2_TBTT_TIME 0x80000000 | ||
| 226 | |||
| 227 | #define AR_ISR_S3 0x0090 | ||
| 228 | #define AR_ISR_S3_QCU_QCBROVF 0x000003FF | ||
| 229 | #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 | ||
| 230 | |||
| 231 | #define AR_ISR_S4 0x0094 | ||
| 232 | #define AR_ISR_S4_QCU_QTRIG 0x000003FF | ||
| 233 | #define AR_ISR_S4_RESV0 0xFFFFFC00 | ||
| 234 | |||
| 235 | #define AR_ISR_S5 0x0098 | ||
| 236 | #define AR_ISR_S5_TIMER_TRIG 0x000000FF | ||
| 237 | #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 | ||
| 238 | #define AR_ISR_S5_TIM_TIMER 0x00000010 | ||
| 239 | #define AR_ISR_S5_DTIM_TIMER 0x00000020 | ||
| 240 | #define AR_ISR_S5_S 0x00d8 | ||
| 241 | #define AR_IMR_S5 0x00b8 | ||
| 242 | #define AR_IMR_S5_TIM_TIMER 0x00000010 | ||
| 243 | #define AR_IMR_S5_DTIM_TIMER 0x00000020 | ||
| 244 | |||
| 245 | |||
| 246 | #define AR_IMR 0x00a0 | ||
| 247 | #define AR_IMR_RXOK 0x00000001 | ||
| 248 | #define AR_IMR_RXDESC 0x00000002 | ||
| 249 | #define AR_IMR_RXERR 0x00000004 | ||
| 250 | #define AR_IMR_RXNOPKT 0x00000008 | ||
| 251 | #define AR_IMR_RXEOL 0x00000010 | ||
| 252 | #define AR_IMR_RXORN 0x00000020 | ||
| 253 | #define AR_IMR_TXOK 0x00000040 | ||
| 254 | #define AR_IMR_TXDESC 0x00000080 | ||
| 255 | #define AR_IMR_TXERR 0x00000100 | ||
| 256 | #define AR_IMR_TXNOPKT 0x00000200 | ||
| 257 | #define AR_IMR_TXEOL 0x00000400 | ||
| 258 | #define AR_IMR_TXURN 0x00000800 | ||
| 259 | #define AR_IMR_MIB 0x00001000 | ||
| 260 | #define AR_IMR_SWI 0x00002000 | ||
| 261 | #define AR_IMR_RXPHY 0x00004000 | ||
| 262 | #define AR_IMR_RXKCM 0x00008000 | ||
| 263 | #define AR_IMR_SWBA 0x00010000 | ||
| 264 | #define AR_IMR_BRSSI 0x00020000 | ||
| 265 | #define AR_IMR_BMISS 0x00040000 | ||
| 266 | #define AR_IMR_BNR 0x00100000 | ||
| 267 | #define AR_IMR_RXCHIRP 0x00200000 | ||
| 268 | #define AR_IMR_BCNMISC 0x00800000 | ||
| 269 | #define AR_IMR_TIM 0x00800000 | ||
| 270 | #define AR_IMR_QCBROVF 0x02000000 | ||
| 271 | #define AR_IMR_QCBRURN 0x04000000 | ||
| 272 | #define AR_IMR_QTRIG 0x08000000 | ||
| 273 | #define AR_IMR_GENTMR 0x10000000 | ||
| 274 | |||
| 275 | #define AR_IMR_TXMINTR 0x00080000 | ||
| 276 | #define AR_IMR_RXMINTR 0x01000000 | ||
| 277 | #define AR_IMR_TXINTM 0x40000000 | ||
| 278 | #define AR_IMR_RXINTM 0x80000000 | ||
| 279 | |||
| 280 | #define AR_IMR_S0 0x00a4 | ||
| 281 | #define AR_IMR_S0_QCU_TXOK 0x000003FF | ||
| 282 | #define AR_IMR_S0_QCU_TXOK_S 0 | ||
| 283 | #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 | ||
| 284 | #define AR_IMR_S0_QCU_TXDESC_S 16 | ||
| 285 | |||
| 286 | #define AR_IMR_S1 0x00a8 | ||
| 287 | #define AR_IMR_S1_QCU_TXERR 0x000003FF | ||
| 288 | #define AR_IMR_S1_QCU_TXERR_S 0 | ||
| 289 | #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 | ||
| 290 | #define AR_IMR_S1_QCU_TXEOL_S 16 | ||
| 291 | |||
| 292 | #define AR_IMR_S2 0x00ac | ||
| 293 | #define AR_IMR_S2_QCU_TXURN 0x000003FF | ||
| 294 | #define AR_IMR_S2_QCU_TXURN_S 0 | ||
| 295 | #define AR_IMR_S2_CST 0x00400000 | ||
| 296 | #define AR_IMR_S2_GTT 0x00800000 | ||
| 297 | #define AR_IMR_S2_TIM 0x01000000 | ||
| 298 | #define AR_IMR_S2_CABEND 0x02000000 | ||
| 299 | #define AR_IMR_S2_DTIMSYNC 0x04000000 | ||
| 300 | #define AR_IMR_S2_BCNTO 0x08000000 | ||
| 301 | #define AR_IMR_S2_CABTO 0x10000000 | ||
| 302 | #define AR_IMR_S2_DTIM 0x20000000 | ||
| 303 | #define AR_IMR_S2_TSFOOR 0x40000000 | ||
| 304 | |||
| 305 | #define AR_IMR_S3 0x00b0 | ||
| 306 | #define AR_IMR_S3_QCU_QCBROVF 0x000003FF | ||
| 307 | #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 | ||
| 308 | #define AR_IMR_S3_QCU_QCBRURN_S 16 | ||
| 309 | |||
| 310 | #define AR_IMR_S4 0x00b4 | ||
| 311 | #define AR_IMR_S4_QCU_QTRIG 0x000003FF | ||
| 312 | #define AR_IMR_S4_RESV0 0xFFFFFC00 | ||
| 313 | |||
| 314 | #define AR_IMR_S5 0x00b8 | ||
| 315 | #define AR_IMR_S5_TIMER_TRIG 0x000000FF | ||
| 316 | #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 | ||
| 317 | |||
| 318 | |||
| 319 | #define AR_ISR_RAC 0x00c0 | ||
| 320 | #define AR_ISR_S0_S 0x00c4 | ||
| 321 | #define AR_ISR_S0_QCU_TXOK 0x000003FF | ||
| 322 | #define AR_ISR_S0_QCU_TXOK_S 0 | ||
| 323 | #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 | ||
| 324 | #define AR_ISR_S0_QCU_TXDESC_S 16 | ||
| 325 | |||
| 326 | #define AR_ISR_S1_S 0x00c8 | ||
| 327 | #define AR_ISR_S1_QCU_TXERR 0x000003FF | ||
| 328 | #define AR_ISR_S1_QCU_TXERR_S 0 | ||
| 329 | #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 | ||
| 330 | #define AR_ISR_S1_QCU_TXEOL_S 16 | ||
| 331 | |||
| 332 | #define AR_ISR_S2_S 0x00cc | ||
| 333 | #define AR_ISR_S3_S 0x00d0 | ||
| 334 | #define AR_ISR_S4_S 0x00d4 | ||
| 335 | #define AR_ISR_S5_S 0x00d8 | ||
| 336 | #define AR_DMADBG_0 0x00e0 | ||
| 337 | #define AR_DMADBG_1 0x00e4 | ||
| 338 | #define AR_DMADBG_2 0x00e8 | ||
| 339 | #define AR_DMADBG_3 0x00ec | ||
| 340 | #define AR_DMADBG_4 0x00f0 | ||
| 341 | #define AR_DMADBG_5 0x00f4 | ||
| 342 | #define AR_DMADBG_6 0x00f8 | ||
| 343 | #define AR_DMADBG_7 0x00fc | ||
| 344 | |||
| 345 | #define AR_NUM_QCU 10 | ||
| 346 | #define AR_QCU_0 0x0001 | ||
| 347 | #define AR_QCU_1 0x0002 | ||
| 348 | #define AR_QCU_2 0x0004 | ||
| 349 | #define AR_QCU_3 0x0008 | ||
| 350 | #define AR_QCU_4 0x0010 | ||
| 351 | #define AR_QCU_5 0x0020 | ||
| 352 | #define AR_QCU_6 0x0040 | ||
| 353 | #define AR_QCU_7 0x0080 | ||
| 354 | #define AR_QCU_8 0x0100 | ||
| 355 | #define AR_QCU_9 0x0200 | ||
| 356 | |||
| 357 | #define AR_Q0_TXDP 0x0800 | ||
| 358 | #define AR_Q1_TXDP 0x0804 | ||
| 359 | #define AR_Q2_TXDP 0x0808 | ||
| 360 | #define AR_Q3_TXDP 0x080c | ||
| 361 | #define AR_Q4_TXDP 0x0810 | ||
| 362 | #define AR_Q5_TXDP 0x0814 | ||
| 363 | #define AR_Q6_TXDP 0x0818 | ||
| 364 | #define AR_Q7_TXDP 0x081c | ||
| 365 | #define AR_Q8_TXDP 0x0820 | ||
| 366 | #define AR_Q9_TXDP 0x0824 | ||
| 367 | #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) | ||
| 368 | |||
| 369 | #define AR_Q_TXE 0x0840 | ||
| 370 | #define AR_Q_TXE_M 0x000003FF | ||
| 371 | |||
| 372 | #define AR_Q_TXD 0x0880 | ||
| 373 | #define AR_Q_TXD_M 0x000003FF | ||
| 374 | |||
| 375 | #define AR_Q0_CBRCFG 0x08c0 | ||
| 376 | #define AR_Q1_CBRCFG 0x08c4 | ||
| 377 | #define AR_Q2_CBRCFG 0x08c8 | ||
| 378 | #define AR_Q3_CBRCFG 0x08cc | ||
| 379 | #define AR_Q4_CBRCFG 0x08d0 | ||
| 380 | #define AR_Q5_CBRCFG 0x08d4 | ||
| 381 | #define AR_Q6_CBRCFG 0x08d8 | ||
| 382 | #define AR_Q7_CBRCFG 0x08dc | ||
| 383 | #define AR_Q8_CBRCFG 0x08e0 | ||
| 384 | #define AR_Q9_CBRCFG 0x08e4 | ||
| 385 | #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) | ||
| 386 | #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF | ||
| 387 | #define AR_Q_CBRCFG_INTERVAL_S 0 | ||
| 388 | #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 | ||
| 389 | #define AR_Q_CBRCFG_OVF_THRESH_S 24 | ||
| 390 | |||
| 391 | #define AR_Q0_RDYTIMECFG 0x0900 | ||
| 392 | #define AR_Q1_RDYTIMECFG 0x0904 | ||
| 393 | #define AR_Q2_RDYTIMECFG 0x0908 | ||
| 394 | #define AR_Q3_RDYTIMECFG 0x090c | ||
| 395 | #define AR_Q4_RDYTIMECFG 0x0910 | ||
| 396 | #define AR_Q5_RDYTIMECFG 0x0914 | ||
| 397 | #define AR_Q6_RDYTIMECFG 0x0918 | ||
| 398 | #define AR_Q7_RDYTIMECFG 0x091c | ||
| 399 | #define AR_Q8_RDYTIMECFG 0x0920 | ||
| 400 | #define AR_Q9_RDYTIMECFG 0x0924 | ||
| 401 | #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) | ||
| 402 | #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF | ||
| 403 | #define AR_Q_RDYTIMECFG_DURATION_S 0 | ||
| 404 | #define AR_Q_RDYTIMECFG_EN 0x01000000 | ||
| 405 | |||
| 406 | #define AR_Q_ONESHOTARM_SC 0x0940 | ||
| 407 | #define AR_Q_ONESHOTARM_SC_M 0x000003FF | ||
| 408 | #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 | ||
| 409 | |||
| 410 | #define AR_Q_ONESHOTARM_CC 0x0980 | ||
| 411 | #define AR_Q_ONESHOTARM_CC_M 0x000003FF | ||
| 412 | #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 | ||
| 413 | |||
| 414 | #define AR_Q0_MISC 0x09c0 | ||
| 415 | #define AR_Q1_MISC 0x09c4 | ||
| 416 | #define AR_Q2_MISC 0x09c8 | ||
| 417 | #define AR_Q3_MISC 0x09cc | ||
| 418 | #define AR_Q4_MISC 0x09d0 | ||
| 419 | #define AR_Q5_MISC 0x09d4 | ||
| 420 | #define AR_Q6_MISC 0x09d8 | ||
| 421 | #define AR_Q7_MISC 0x09dc | ||
| 422 | #define AR_Q8_MISC 0x09e0 | ||
| 423 | #define AR_Q9_MISC 0x09e4 | ||
| 424 | #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) | ||
| 425 | #define AR_Q_MISC_FSP 0x0000000F | ||
| 426 | #define AR_Q_MISC_FSP_ASAP 0 | ||
| 427 | #define AR_Q_MISC_FSP_CBR 1 | ||
| 428 | #define AR_Q_MISC_FSP_DBA_GATED 2 | ||
| 429 | #define AR_Q_MISC_FSP_TIM_GATED 3 | ||
| 430 | #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 | ||
| 431 | #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 | ||
| 432 | #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 | ||
| 433 | #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 | ||
| 434 | #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 | ||
| 435 | #define AR_Q_MISC_BEACON_USE 0x00000080 | ||
| 436 | #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 | ||
| 437 | #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 | ||
| 438 | #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 | ||
| 439 | #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 | ||
| 440 | #define AR_Q_MISC_RESV0 0xFFFFF000 | ||
| 441 | |||
| 442 | #define AR_Q0_STS 0x0a00 | ||
| 443 | #define AR_Q1_STS 0x0a04 | ||
| 444 | #define AR_Q2_STS 0x0a08 | ||
| 445 | #define AR_Q3_STS 0x0a0c | ||
| 446 | #define AR_Q4_STS 0x0a10 | ||
| 447 | #define AR_Q5_STS 0x0a14 | ||
| 448 | #define AR_Q6_STS 0x0a18 | ||
| 449 | #define AR_Q7_STS 0x0a1c | ||
| 450 | #define AR_Q8_STS 0x0a20 | ||
| 451 | #define AR_Q9_STS 0x0a24 | ||
| 452 | #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) | ||
| 453 | #define AR_Q_STS_PEND_FR_CNT 0x00000003 | ||
| 454 | #define AR_Q_STS_RESV0 0x000000FC | ||
| 455 | #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 | ||
| 456 | #define AR_Q_STS_RESV1 0xFFFF0000 | ||
| 457 | |||
| 458 | #define AR_Q_RDYTIMESHDN 0x0a40 | ||
| 459 | #define AR_Q_RDYTIMESHDN_M 0x000003FF | ||
| 460 | |||
| 461 | |||
| 462 | #define AR_NUM_DCU 10 | ||
| 463 | #define AR_DCU_0 0x0001 | ||
| 464 | #define AR_DCU_1 0x0002 | ||
| 465 | #define AR_DCU_2 0x0004 | ||
| 466 | #define AR_DCU_3 0x0008 | ||
| 467 | #define AR_DCU_4 0x0010 | ||
| 468 | #define AR_DCU_5 0x0020 | ||
| 469 | #define AR_DCU_6 0x0040 | ||
| 470 | #define AR_DCU_7 0x0080 | ||
| 471 | #define AR_DCU_8 0x0100 | ||
| 472 | #define AR_DCU_9 0x0200 | ||
| 473 | |||
| 474 | #define AR_D0_QCUMASK 0x1000 | ||
| 475 | #define AR_D1_QCUMASK 0x1004 | ||
| 476 | #define AR_D2_QCUMASK 0x1008 | ||
| 477 | #define AR_D3_QCUMASK 0x100c | ||
| 478 | #define AR_D4_QCUMASK 0x1010 | ||
| 479 | #define AR_D5_QCUMASK 0x1014 | ||
| 480 | #define AR_D6_QCUMASK 0x1018 | ||
| 481 | #define AR_D7_QCUMASK 0x101c | ||
| 482 | #define AR_D8_QCUMASK 0x1020 | ||
| 483 | #define AR_D9_QCUMASK 0x1024 | ||
| 484 | #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) | ||
| 485 | #define AR_D_QCUMASK 0x000003FF | ||
| 486 | #define AR_D_QCUMASK_RESV0 0xFFFFFC00 | ||
| 487 | |||
| 488 | #define AR_D_TXBLK_CMD 0x1038 | ||
| 489 | #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) | ||
| 490 | |||
| 491 | #define AR_D0_LCL_IFS 0x1040 | ||
| 492 | #define AR_D1_LCL_IFS 0x1044 | ||
| 493 | #define AR_D2_LCL_IFS 0x1048 | ||
| 494 | #define AR_D3_LCL_IFS 0x104c | ||
| 495 | #define AR_D4_LCL_IFS 0x1050 | ||
| 496 | #define AR_D5_LCL_IFS 0x1054 | ||
| 497 | #define AR_D6_LCL_IFS 0x1058 | ||
| 498 | #define AR_D7_LCL_IFS 0x105c | ||
| 499 | #define AR_D8_LCL_IFS 0x1060 | ||
| 500 | #define AR_D9_LCL_IFS 0x1064 | ||
| 501 | #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) | ||
| 502 | #define AR_D_LCL_IFS_CWMIN 0x000003FF | ||
| 503 | #define AR_D_LCL_IFS_CWMIN_S 0 | ||
| 504 | #define AR_D_LCL_IFS_CWMAX 0x000FFC00 | ||
| 505 | #define AR_D_LCL_IFS_CWMAX_S 10 | ||
| 506 | #define AR_D_LCL_IFS_AIFS 0x0FF00000 | ||
| 507 | #define AR_D_LCL_IFS_AIFS_S 20 | ||
| 508 | |||
| 509 | #define AR_D_LCL_IFS_RESV0 0xF0000000 | ||
| 510 | |||
| 511 | #define AR_D0_RETRY_LIMIT 0x1080 | ||
| 512 | #define AR_D1_RETRY_LIMIT 0x1084 | ||
| 513 | #define AR_D2_RETRY_LIMIT 0x1088 | ||
| 514 | #define AR_D3_RETRY_LIMIT 0x108c | ||
| 515 | #define AR_D4_RETRY_LIMIT 0x1090 | ||
| 516 | #define AR_D5_RETRY_LIMIT 0x1094 | ||
| 517 | #define AR_D6_RETRY_LIMIT 0x1098 | ||
| 518 | #define AR_D7_RETRY_LIMIT 0x109c | ||
| 519 | #define AR_D8_RETRY_LIMIT 0x10a0 | ||
| 520 | #define AR_D9_RETRY_LIMIT 0x10a4 | ||
| 521 | #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) | ||
| 522 | #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F | ||
| 523 | #define AR_D_RETRY_LIMIT_FR_SH_S 0 | ||
| 524 | #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 | ||
| 525 | #define AR_D_RETRY_LIMIT_STA_SH_S 8 | ||
| 526 | #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 | ||
| 527 | #define AR_D_RETRY_LIMIT_STA_LG_S 14 | ||
| 528 | #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 | ||
| 529 | |||
| 530 | #define AR_D0_CHNTIME 0x10c0 | ||
| 531 | #define AR_D1_CHNTIME 0x10c4 | ||
| 532 | #define AR_D2_CHNTIME 0x10c8 | ||
| 533 | #define AR_D3_CHNTIME 0x10cc | ||
| 534 | #define AR_D4_CHNTIME 0x10d0 | ||
| 535 | #define AR_D5_CHNTIME 0x10d4 | ||
| 536 | #define AR_D6_CHNTIME 0x10d8 | ||
| 537 | #define AR_D7_CHNTIME 0x10dc | ||
| 538 | #define AR_D8_CHNTIME 0x10e0 | ||
| 539 | #define AR_D9_CHNTIME 0x10e4 | ||
| 540 | #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) | ||
| 541 | #define AR_D_CHNTIME_DUR 0x000FFFFF | ||
| 542 | #define AR_D_CHNTIME_DUR_S 0 | ||
| 543 | #define AR_D_CHNTIME_EN 0x00100000 | ||
| 544 | #define AR_D_CHNTIME_RESV0 0xFFE00000 | ||
| 545 | |||
| 546 | #define AR_D0_MISC 0x1100 | ||
| 547 | #define AR_D1_MISC 0x1104 | ||
| 548 | #define AR_D2_MISC 0x1108 | ||
| 549 | #define AR_D3_MISC 0x110c | ||
| 550 | #define AR_D4_MISC 0x1110 | ||
| 551 | #define AR_D5_MISC 0x1114 | ||
| 552 | #define AR_D6_MISC 0x1118 | ||
| 553 | #define AR_D7_MISC 0x111c | ||
| 554 | #define AR_D8_MISC 0x1120 | ||
| 555 | #define AR_D9_MISC 0x1124 | ||
| 556 | #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) | ||
| 557 | #define AR_D_MISC_BKOFF_THRESH 0x0000003F | ||
| 558 | #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 | ||
| 559 | #define AR_D_MISC_CW_RESET_EN 0x00000080 | ||
| 560 | #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 | ||
| 561 | #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 | ||
| 562 | #define AR_D_MISC_CW_BKOFF_EN 0x00001000 | ||
| 563 | #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 | ||
| 564 | #define AR_D_MISC_VIR_COL_HANDLING_S 14 | ||
| 565 | #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 | ||
| 566 | #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 | ||
| 567 | #define AR_D_MISC_BEACON_USE 0x00010000 | ||
| 568 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 | ||
| 569 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 | ||
| 570 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 | ||
| 571 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 | ||
| 572 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 | ||
| 573 | #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 | ||
| 574 | #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 | ||
| 575 | #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 | ||
| 576 | #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 | ||
| 577 | #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 | ||
| 578 | #define AR_D_MISC_RESV0 0xFF000000 | ||
| 579 | |||
| 580 | #define AR_D_SEQNUM 0x1140 | ||
| 581 | |||
| 582 | #define AR_D_GBL_IFS_SIFS 0x1030 | ||
| 583 | #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF | ||
| 584 | #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF | ||
| 585 | |||
| 586 | #define AR_D_TXBLK_BASE 0x1038 | ||
| 587 | #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF | ||
| 588 | #define AR_D_TXBLK_WRITE_BITMASK_S 0 | ||
| 589 | #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 | ||
| 590 | #define AR_D_TXBLK_WRITE_SLICE_S 16 | ||
| 591 | #define AR_D_TXBLK_WRITE_DCU 0x00F00000 | ||
| 592 | #define AR_D_TXBLK_WRITE_DCU_S 20 | ||
| 593 | #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 | ||
| 594 | #define AR_D_TXBLK_WRITE_COMMAND_S 24 | ||
| 595 | |||
| 596 | #define AR_D_GBL_IFS_SLOT 0x1070 | ||
| 597 | #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF | ||
| 598 | #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 | ||
| 599 | |||
| 600 | #define AR_D_GBL_IFS_EIFS 0x10b0 | ||
| 601 | #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF | ||
| 602 | #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 | ||
| 603 | |||
| 604 | #define AR_D_GBL_IFS_MISC 0x10f0 | ||
| 605 | #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 | ||
| 606 | #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 | ||
| 607 | #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 | ||
| 608 | #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 | ||
| 609 | #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 | ||
| 610 | #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 | ||
| 611 | #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 | ||
| 612 | #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 | ||
| 613 | |||
| 614 | #define AR_D_FPCTL 0x1230 | ||
| 615 | #define AR_D_FPCTL_DCU 0x0000000F | ||
| 616 | #define AR_D_FPCTL_DCU_S 0 | ||
| 617 | #define AR_D_FPCTL_PREFETCH_EN 0x00000010 | ||
| 618 | #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 | ||
| 619 | #define AR_D_FPCTL_BURST_PREFETCH_S 5 | ||
| 620 | |||
| 621 | #define AR_D_TXPSE 0x1270 | ||
| 622 | #define AR_D_TXPSE_CTRL 0x000003FF | ||
| 623 | #define AR_D_TXPSE_RESV0 0x0000FC00 | ||
| 624 | #define AR_D_TXPSE_STATUS 0x00010000 | ||
| 625 | #define AR_D_TXPSE_RESV1 0xFFFE0000 | ||
| 626 | |||
| 627 | #define AR_D_TXSLOTMASK 0x12f0 | ||
| 628 | #define AR_D_TXSLOTMASK_NUM 0x0000000F | ||
| 629 | |||
| 630 | #define AR_CFG_LED 0x1f04 | ||
| 631 | #define AR_CFG_SCLK_RATE_IND 0x00000003 | ||
| 632 | #define AR_CFG_SCLK_RATE_IND_S 0 | ||
| 633 | #define AR_CFG_SCLK_32MHZ 0x00000000 | ||
| 634 | #define AR_CFG_SCLK_4MHZ 0x00000001 | ||
| 635 | #define AR_CFG_SCLK_1MHZ 0x00000002 | ||
| 636 | #define AR_CFG_SCLK_32KHZ 0x00000003 | ||
| 637 | #define AR_CFG_LED_BLINK_SLOW 0x00000008 | ||
| 638 | #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 | ||
| 639 | #define AR_CFG_LED_MODE_SEL 0x00000380 | ||
| 640 | #define AR_CFG_LED_MODE_SEL_S 7 | ||
| 641 | #define AR_CFG_LED_POWER 0x00000280 | ||
| 642 | #define AR_CFG_LED_POWER_S 7 | ||
| 643 | #define AR_CFG_LED_NETWORK 0x00000300 | ||
| 644 | #define AR_CFG_LED_NETWORK_S 7 | ||
| 645 | #define AR_CFG_LED_MODE_PROP 0x0 | ||
| 646 | #define AR_CFG_LED_MODE_RPROP 0x1 | ||
| 647 | #define AR_CFG_LED_MODE_SPLIT 0x2 | ||
| 648 | #define AR_CFG_LED_MODE_RAND 0x3 | ||
| 649 | #define AR_CFG_LED_MODE_POWER_OFF 0x4 | ||
| 650 | #define AR_CFG_LED_MODE_POWER_ON 0x5 | ||
| 651 | #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 | ||
| 652 | #define AR_CFG_LED_MODE_NETWORK_ON 0x6 | ||
| 653 | #define AR_CFG_LED_ASSOC_CTL 0x00000c00 | ||
| 654 | #define AR_CFG_LED_ASSOC_CTL_S 10 | ||
| 655 | #define AR_CFG_LED_ASSOC_NONE 0x0 | ||
| 656 | #define AR_CFG_LED_ASSOC_ACTIVE 0x1 | ||
| 657 | #define AR_CFG_LED_ASSOC_PENDING 0x2 | ||
| 658 | |||
| 659 | #define AR_CFG_LED_BLINK_SLOW 0x00000008 | ||
| 660 | #define AR_CFG_LED_BLINK_SLOW_S 3 | ||
| 661 | |||
| 662 | #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 | ||
| 663 | #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 | ||
| 664 | |||
| 665 | #define AR_MAC_SLEEP 0x1f00 | ||
| 666 | #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 | ||
| 667 | #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 | ||
| 668 | |||
| 669 | #define AR_RC 0x4000 | ||
| 670 | #define AR_RC_AHB 0x00000001 | ||
| 671 | #define AR_RC_APB 0x00000002 | ||
| 672 | #define AR_RC_HOSTIF 0x00000100 | ||
| 673 | |||
| 674 | #define AR_WA 0x4004 | ||
| 675 | |||
| 676 | #define AR_PM_STATE 0x4008 | ||
| 677 | #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 | ||
| 678 | |||
| 679 | #define AR_HOST_TIMEOUT 0x4018 | ||
| 680 | #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF | ||
| 681 | #define AR_HOST_TIMEOUT_APB_CNTR_S 0 | ||
| 682 | #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 | ||
| 683 | #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 | ||
| 684 | |||
| 685 | #define AR_EEPROM 0x401c | ||
| 686 | #define AR_EEPROM_ABSENT 0x00000100 | ||
| 687 | #define AR_EEPROM_CORRUPT 0x00000200 | ||
| 688 | #define AR_EEPROM_PROT_MASK 0x03FFFC00 | ||
| 689 | #define AR_EEPROM_PROT_MASK_S 10 | ||
| 690 | |||
| 691 | #define EEPROM_PROTECT_RP_0_31 0x0001 | ||
| 692 | #define EEPROM_PROTECT_WP_0_31 0x0002 | ||
| 693 | #define EEPROM_PROTECT_RP_32_63 0x0004 | ||
| 694 | #define EEPROM_PROTECT_WP_32_63 0x0008 | ||
| 695 | #define EEPROM_PROTECT_RP_64_127 0x0010 | ||
| 696 | #define EEPROM_PROTECT_WP_64_127 0x0020 | ||
| 697 | #define EEPROM_PROTECT_RP_128_191 0x0040 | ||
| 698 | #define EEPROM_PROTECT_WP_128_191 0x0080 | ||
| 699 | #define EEPROM_PROTECT_RP_192_255 0x0100 | ||
| 700 | #define EEPROM_PROTECT_WP_192_255 0x0200 | ||
| 701 | #define EEPROM_PROTECT_RP_256_511 0x0400 | ||
| 702 | #define EEPROM_PROTECT_WP_256_511 0x0800 | ||
| 703 | #define EEPROM_PROTECT_RP_512_1023 0x1000 | ||
| 704 | #define EEPROM_PROTECT_WP_512_1023 0x2000 | ||
| 705 | #define EEPROM_PROTECT_RP_1024_2047 0x4000 | ||
| 706 | #define EEPROM_PROTECT_WP_1024_2047 0x8000 | ||
| 707 | |||
| 708 | #define AR_SREV \ | ||
| 709 | ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) | ||
| 710 | |||
| 711 | #define AR_SREV_ID \ | ||
| 712 | ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) | ||
| 713 | #define AR_SREV_VERSION 0x000000F0 | ||
| 714 | #define AR_SREV_VERSION_S 4 | ||
| 715 | #define AR_SREV_REVISION 0x00000007 | ||
| 716 | |||
| 717 | #define AR_SREV_ID2 0xFFFFFFFF | ||
| 718 | #define AR_SREV_VERSION2 0xFFFC0000 | ||
| 719 | #define AR_SREV_VERSION2_S 18 | ||
| 720 | #define AR_SREV_TYPE2 0x0003F000 | ||
| 721 | #define AR_SREV_TYPE2_S 12 | ||
| 722 | #define AR_SREV_TYPE2_CHAIN 0x00001000 | ||
| 723 | #define AR_SREV_TYPE2_HOST_MODE 0x00002000 | ||
| 724 | #define AR_SREV_REVISION2 0x00000F00 | ||
| 725 | #define AR_SREV_REVISION2_S 8 | ||
| 726 | |||
| 727 | #define AR_SREV_VERSION_5416_PCI 0xD | ||
| 728 | #define AR_SREV_VERSION_5416_PCIE 0xC | ||
| 729 | #define AR_SREV_REVISION_5416_10 0 | ||
| 730 | #define AR_SREV_REVISION_5416_20 1 | ||
| 731 | #define AR_SREV_REVISION_5416_22 2 | ||
| 732 | #define AR_SREV_VERSION_9160 0x40 | ||
| 733 | #define AR_SREV_REVISION_9160_10 0 | ||
| 734 | #define AR_SREV_REVISION_9160_11 1 | ||
| 735 | #define AR_SREV_VERSION_9280 0x80 | ||
| 736 | #define AR_SREV_REVISION_9280_10 0 | ||
| 737 | #define AR_SREV_REVISION_9280_20 1 | ||
| 738 | #define AR_SREV_REVISION_9280_21 2 | ||
| 739 | #define AR_SREV_VERSION_9285 0xC0 | ||
| 740 | #define AR_SREV_REVISION_9285_10 0 | ||
| 741 | |||
| 742 | #define AR_SREV_9100_OR_LATER(_ah) \ | ||
| 743 | (((_ah)->ah_macVersion >= AR_SREV_VERSION_5416_PCIE)) | ||
| 744 | #define AR_SREV_5416_20_OR_LATER(_ah) \ | ||
| 745 | (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160) || \ | ||
| 746 | ((_ah)->ah_macRev >= AR_SREV_REVISION_5416_20)) | ||
| 747 | #define AR_SREV_5416_22_OR_LATER(_ah) \ | ||
| 748 | (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160) || \ | ||
| 749 | ((_ah)->ah_macRev >= AR_SREV_REVISION_5416_22)) | ||
| 750 | #define AR_SREV_9160(_ah) \ | ||
| 751 | (((_ah)->ah_macVersion == AR_SREV_VERSION_9160)) | ||
| 752 | #define AR_SREV_9160_10_OR_LATER(_ah) \ | ||
| 753 | (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160)) | ||
| 754 | #define AR_SREV_9160_11(_ah) \ | ||
| 755 | (AR_SREV_9160(_ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9160_11)) | ||
| 756 | #define AR_SREV_9280(_ah) \ | ||
| 757 | (((_ah)->ah_macVersion == AR_SREV_VERSION_9280)) | ||
| 758 | #define AR_SREV_9280_10_OR_LATER(_ah) \ | ||
| 759 | (((_ah)->ah_macVersion >= AR_SREV_VERSION_9280)) | ||
| 760 | #define AR_SREV_9280_20(_ah) \ | ||
| 761 | (((_ah)->ah_macVersion == AR_SREV_VERSION_9280) && \ | ||
| 762 | ((_ah)->ah_macRev >= AR_SREV_REVISION_9280_20)) | ||
| 763 | #define AR_SREV_9280_20_OR_LATER(_ah) \ | ||
| 764 | (((_ah)->ah_macVersion > AR_SREV_VERSION_9280) || \ | ||
| 765 | (((_ah)->ah_macVersion == AR_SREV_VERSION_9280) && \ | ||
| 766 | ((_ah)->ah_macRev >= AR_SREV_REVISION_9280_20))) | ||
| 767 | |||
| 768 | #define AR_SREV_9285(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_9285)) | ||
| 769 | #define AR_SREV_9285_10_OR_LATER(_ah) \ | ||
| 770 | (((_ah)->ah_macVersion >= AR_SREV_VERSION_9285)) | ||
| 771 | |||
| 772 | #define AR_RADIO_SREV_MAJOR 0xf0 | ||
| 773 | #define AR_RAD5133_SREV_MAJOR 0xc0 | ||
| 774 | #define AR_RAD2133_SREV_MAJOR 0xd0 | ||
| 775 | #define AR_RAD5122_SREV_MAJOR 0xe0 | ||
| 776 | #define AR_RAD2122_SREV_MAJOR 0xf0 | ||
| 777 | |||
| 778 | #define AR_AHB_MODE 0x4024 | ||
| 779 | #define AR_AHB_EXACT_WR_EN 0x00000000 | ||
| 780 | #define AR_AHB_BUF_WR_EN 0x00000001 | ||
| 781 | #define AR_AHB_EXACT_RD_EN 0x00000000 | ||
| 782 | #define AR_AHB_CACHELINE_RD_EN 0x00000002 | ||
| 783 | #define AR_AHB_PREFETCH_RD_EN 0x00000004 | ||
| 784 | #define AR_AHB_PAGE_SIZE_1K 0x00000000 | ||
| 785 | #define AR_AHB_PAGE_SIZE_2K 0x00000008 | ||
| 786 | #define AR_AHB_PAGE_SIZE_4K 0x00000010 | ||
| 787 | |||
| 788 | #define AR_INTR_RTC_IRQ 0x00000001 | ||
| 789 | #define AR_INTR_MAC_IRQ 0x00000002 | ||
| 790 | #define AR_INTR_EEP_PROT_ACCESS 0x00000004 | ||
| 791 | #define AR_INTR_MAC_AWAKE 0x00020000 | ||
| 792 | #define AR_INTR_MAC_ASLEEP 0x00040000 | ||
| 793 | #define AR_INTR_SPURIOUS 0xFFFFFFFF | ||
| 794 | |||
| 795 | |||
| 796 | #define AR_INTR_SYNC_CAUSE_CLR 0x4028 | ||
| 797 | |||
| 798 | #define AR_INTR_SYNC_CAUSE 0x4028 | ||
| 799 | |||
| 800 | #define AR_INTR_SYNC_ENABLE 0x402c | ||
| 801 | #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 | ||
| 802 | #define AR_INTR_SYNC_ENABLE_GPIO_S 18 | ||
| 803 | |||
| 804 | enum { | ||
| 805 | AR_INTR_SYNC_RTC_IRQ = 0x00000001, | ||
| 806 | AR_INTR_SYNC_MAC_IRQ = 0x00000002, | ||
| 807 | AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, | ||
| 808 | AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, | ||
| 809 | AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, | ||
| 810 | AR_INTR_SYNC_HOST1_FATAL = 0x00000020, | ||
| 811 | AR_INTR_SYNC_HOST1_PERR = 0x00000040, | ||
| 812 | AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, | ||
| 813 | AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, | ||
| 814 | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, | ||
| 815 | AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, | ||
| 816 | AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, | ||
| 817 | AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, | ||
| 818 | AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, | ||
| 819 | AR_INTR_SYNC_PM_ACCESS = 0x00004000, | ||
| 820 | AR_INTR_SYNC_MAC_AWAKE = 0x00008000, | ||
| 821 | AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, | ||
| 822 | AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, | ||
| 823 | AR_INTR_SYNC_ALL = 0x0003FFFF, | ||
| 824 | |||
| 825 | |||
| 826 | AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | | ||
| 827 | AR_INTR_SYNC_HOST1_PERR | | ||
| 828 | AR_INTR_SYNC_RADM_CPL_EP | | ||
| 829 | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | | ||
| 830 | AR_INTR_SYNC_RADM_CPL_TLP_ABORT | | ||
| 831 | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | | ||
| 832 | AR_INTR_SYNC_RADM_CPL_TIMEOUT | | ||
| 833 | AR_INTR_SYNC_LOCAL_TIMEOUT | | ||
| 834 | AR_INTR_SYNC_MAC_SLEEP_ACCESS), | ||
| 835 | |||
| 836 | AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, | ||
| 837 | |||
| 838 | }; | ||
| 839 | |||
| 840 | #define AR_INTR_ASYNC_MASK 0x4030 | ||
| 841 | #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 | ||
| 842 | #define AR_INTR_ASYNC_MASK_GPIO_S 18 | ||
| 843 | |||
| 844 | #define AR_INTR_SYNC_MASK 0x4034 | ||
| 845 | #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 | ||
| 846 | #define AR_INTR_SYNC_MASK_GPIO_S 18 | ||
| 847 | |||
| 848 | #define AR_INTR_ASYNC_CAUSE_CLR 0x4038 | ||
| 849 | #define AR_INTR_ASYNC_CAUSE 0x4038 | ||
| 850 | |||
| 851 | #define AR_INTR_ASYNC_ENABLE 0x403c | ||
| 852 | #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 | ||
| 853 | #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 | ||
| 854 | |||
| 855 | #define AR_PCIE_SERDES 0x4040 | ||
| 856 | #define AR_PCIE_SERDES2 0x4044 | ||
| 857 | #define AR_PCIE_PM_CTRL 0x4014 | ||
| 858 | #define AR_PCIE_PM_CTRL_ENA 0x00080000 | ||
| 859 | |||
| 860 | #define AR_NUM_GPIO 14 | ||
| 861 | #define AR928X_NUM_GPIO 10 | ||
| 862 | |||
| 863 | #define AR_GPIO_IN_OUT 0x4048 | ||
| 864 | #define AR_GPIO_IN_VAL 0x0FFFC000 | ||
| 865 | #define AR_GPIO_IN_VAL_S 14 | ||
| 866 | #define AR928X_GPIO_IN_VAL 0x000FFC00 | ||
| 867 | #define AR928X_GPIO_IN_VAL_S 10 | ||
| 868 | |||
| 869 | #define AR_GPIO_OE_OUT 0x404c | ||
| 870 | #define AR_GPIO_OE_OUT_DRV 0x3 | ||
| 871 | #define AR_GPIO_OE_OUT_DRV_NO 0x0 | ||
| 872 | #define AR_GPIO_OE_OUT_DRV_LOW 0x1 | ||
| 873 | #define AR_GPIO_OE_OUT_DRV_HI 0x2 | ||
| 874 | #define AR_GPIO_OE_OUT_DRV_ALL 0x3 | ||
| 875 | |||
| 876 | #define AR_GPIO_INTR_POL 0x4050 | ||
| 877 | #define AR_GPIO_INTR_POL_VAL 0x00001FFF | ||
| 878 | #define AR_GPIO_INTR_POL_VAL_S 0 | ||
| 879 | |||
| 880 | #define AR_GPIO_INPUT_EN_VAL 0x4054 | ||
| 881 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 | ||
| 882 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 | ||
| 883 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 | ||
| 884 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 | ||
| 885 | #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 | ||
| 886 | #define AR_GPIO_JTAG_DISABLE 0x00020000 | ||
| 887 | |||
| 888 | #define AR_GPIO_INPUT_MUX1 0x4058 | ||
| 889 | |||
| 890 | #define AR_GPIO_INPUT_MUX2 0x405c | ||
| 891 | #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f | ||
| 892 | #define AR_GPIO_INPUT_MUX2_CLK25_S 0 | ||
| 893 | #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 | ||
| 894 | #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 | ||
| 895 | #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 | ||
| 896 | #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 | ||
| 897 | |||
| 898 | #define AR_GPIO_OUTPUT_MUX1 0x4060 | ||
| 899 | #define AR_GPIO_OUTPUT_MUX2 0x4064 | ||
| 900 | #define AR_GPIO_OUTPUT_MUX3 0x4068 | ||
| 901 | |||
| 902 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 | ||
| 903 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | ||
| 904 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | ||
| 905 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 | ||
| 906 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | ||
| 907 | |||
| 908 | #define AR_INPUT_STATE 0x406c | ||
| 909 | |||
| 910 | #define AR_EEPROM_STATUS_DATA 0x407c | ||
| 911 | #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff | ||
| 912 | #define AR_EEPROM_STATUS_DATA_VAL_S 0 | ||
| 913 | #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 | ||
| 914 | #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 | ||
| 915 | #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 | ||
| 916 | #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 | ||
| 917 | |||
| 918 | #define AR_OBS 0x4080 | ||
| 919 | |||
| 920 | #define AR_PCIE_MSI 0x4094 | ||
| 921 | #define AR_PCIE_MSI_ENABLE 0x00000001 | ||
| 922 | |||
| 923 | |||
| 924 | #define AR_RTC_9160_PLL_DIV 0x000003ff | ||
| 925 | #define AR_RTC_9160_PLL_DIV_S 0 | ||
| 926 | #define AR_RTC_9160_PLL_REFDIV 0x00003C00 | ||
| 927 | #define AR_RTC_9160_PLL_REFDIV_S 10 | ||
| 928 | #define AR_RTC_9160_PLL_CLKSEL 0x0000C000 | ||
| 929 | #define AR_RTC_9160_PLL_CLKSEL_S 14 | ||
| 930 | |||
| 931 | #define AR_RTC_BASE 0x00020000 | ||
| 932 | #define AR_RTC_RC \ | ||
| 933 | (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000 | ||
| 934 | #define AR_RTC_RC_M 0x00000003 | ||
| 935 | #define AR_RTC_RC_MAC_WARM 0x00000001 | ||
| 936 | #define AR_RTC_RC_MAC_COLD 0x00000002 | ||
| 937 | #define AR_RTC_RC_COLD_RESET 0x00000004 | ||
| 938 | #define AR_RTC_RC_WARM_RESET 0x00000008 | ||
| 939 | |||
| 940 | #define AR_RTC_PLL_CONTROL \ | ||
| 941 | (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014 | ||
| 942 | |||
| 943 | #define AR_RTC_PLL_DIV 0x0000001f | ||
| 944 | #define AR_RTC_PLL_DIV_S 0 | ||
| 945 | #define AR_RTC_PLL_DIV2 0x00000020 | ||
| 946 | #define AR_RTC_PLL_REFDIV_5 0x000000c0 | ||
| 947 | #define AR_RTC_PLL_CLKSEL 0x00000300 | ||
| 948 | #define AR_RTC_PLL_CLKSEL_S 8 | ||
| 949 | |||
| 950 | |||
| 951 | |||
| 952 | #define AR_RTC_RESET \ | ||
| 953 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) | ||
| 954 | #define AR_RTC_RESET_EN (0x00000001) | ||
| 955 | |||
| 956 | #define AR_RTC_STATUS \ | ||
| 957 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) | ||
| 958 | |||
| 959 | #define AR_RTC_STATUS_M \ | ||
| 960 | ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f) | ||
| 961 | |||
| 962 | #define AR_RTC_PM_STATUS_M 0x0000000f | ||
| 963 | |||
| 964 | #define AR_RTC_STATUS_SHUTDOWN 0x00000001 | ||
| 965 | #define AR_RTC_STATUS_ON 0x00000002 | ||
| 966 | #define AR_RTC_STATUS_SLEEP 0x00000004 | ||
| 967 | #define AR_RTC_STATUS_WAKEUP 0x00000008 | ||
| 968 | |||
| 969 | #define AR_RTC_SLEEP_CLK \ | ||
| 970 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) | ||
| 971 | #define AR_RTC_FORCE_DERIVED_CLK 0x2 | ||
| 972 | |||
| 973 | #define AR_RTC_FORCE_WAKE \ | ||
| 974 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) | ||
| 975 | #define AR_RTC_FORCE_WAKE_EN 0x00000001 | ||
| 976 | #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 | ||
| 977 | |||
| 978 | |||
| 979 | #define AR_RTC_INTR_CAUSE \ | ||
| 980 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) | ||
| 981 | |||
| 982 | #define AR_RTC_INTR_ENABLE \ | ||
| 983 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) | ||
| 984 | |||
| 985 | #define AR_RTC_INTR_MASK \ | ||
| 986 | ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) | ||
| 987 | |||
| 988 | #define AR_SEQ_MASK 0x8060 | ||
| 989 | |||
| 990 | #define AR_AN_RF2G1_CH0 0x7810 | ||
| 991 | #define AR_AN_RF2G1_CH0_OB 0x03800000 | ||
| 992 | #define AR_AN_RF2G1_CH0_OB_S 23 | ||
| 993 | #define AR_AN_RF2G1_CH0_DB 0x1C000000 | ||
| 994 | #define AR_AN_RF2G1_CH0_DB_S 26 | ||
| 995 | |||
| 996 | #define AR_AN_RF5G1_CH0 0x7818 | ||
| 997 | #define AR_AN_RF5G1_CH0_OB5 0x00070000 | ||
| 998 | #define AR_AN_RF5G1_CH0_OB5_S 16 | ||
| 999 | #define AR_AN_RF5G1_CH0_DB5 0x00380000 | ||
| 1000 | #define AR_AN_RF5G1_CH0_DB5_S 19 | ||
| 1001 | |||
| 1002 | #define AR_AN_RF2G1_CH1 0x7834 | ||
| 1003 | #define AR_AN_RF2G1_CH1_OB 0x03800000 | ||
| 1004 | #define AR_AN_RF2G1_CH1_OB_S 23 | ||
| 1005 | #define AR_AN_RF2G1_CH1_DB 0x1C000000 | ||
| 1006 | #define AR_AN_RF2G1_CH1_DB_S 26 | ||
| 1007 | |||
| 1008 | #define AR_AN_RF5G1_CH1 0x783C | ||
| 1009 | #define AR_AN_RF5G1_CH1_OB5 0x00070000 | ||
| 1010 | #define AR_AN_RF5G1_CH1_OB5_S 16 | ||
| 1011 | #define AR_AN_RF5G1_CH1_DB5 0x00380000 | ||
| 1012 | #define AR_AN_RF5G1_CH1_DB5_S 19 | ||
| 1013 | |||
| 1014 | #define AR_AN_TOP2 0x7894 | ||
| 1015 | #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 | ||
| 1016 | #define AR_AN_TOP2_XPABIAS_LVL_S 30 | ||
| 1017 | #define AR_AN_TOP2_LOCALBIAS 0x00200000 | ||
| 1018 | #define AR_AN_TOP2_LOCALBIAS_S 21 | ||
| 1019 | #define AR_AN_TOP2_PWDCLKIND 0x00400000 | ||
| 1020 | #define AR_AN_TOP2_PWDCLKIND_S 22 | ||
| 1021 | |||
| 1022 | #define AR_AN_SYNTH9 0x7868 | ||
| 1023 | #define AR_AN_SYNTH9_REFDIVA 0xf8000000 | ||
| 1024 | #define AR_AN_SYNTH9_REFDIVA_S 27 | ||
| 1025 | |||
| 1026 | #define AR_STA_ID0 0x8000 | ||
| 1027 | #define AR_STA_ID1 0x8004 | ||
| 1028 | #define AR_STA_ID1_SADH_MASK 0x0000FFFF | ||
| 1029 | #define AR_STA_ID1_STA_AP 0x00010000 | ||
| 1030 | #define AR_STA_ID1_ADHOC 0x00020000 | ||
| 1031 | #define AR_STA_ID1_PWR_SAV 0x00040000 | ||
| 1032 | #define AR_STA_ID1_KSRCHDIS 0x00080000 | ||
| 1033 | #define AR_STA_ID1_PCF 0x00100000 | ||
| 1034 | #define AR_STA_ID1_USE_DEFANT 0x00200000 | ||
| 1035 | #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 | ||
| 1036 | #define AR_STA_ID1_RTS_USE_DEF 0x00800000 | ||
| 1037 | #define AR_STA_ID1_ACKCTS_6MB 0x01000000 | ||
| 1038 | #define AR_STA_ID1_BASE_RATE_11B 0x02000000 | ||
| 1039 | #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 | ||
| 1040 | #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 | ||
| 1041 | #define AR_STA_ID1_KSRCH_MODE 0x10000000 | ||
| 1042 | #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 | ||
| 1043 | #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 | ||
| 1044 | #define AR_STA_ID1_MCAST_KSRCH 0x80000000 | ||
| 1045 | |||
| 1046 | #define AR_BSS_ID0 0x8008 | ||
| 1047 | #define AR_BSS_ID1 0x800C | ||
| 1048 | #define AR_BSS_ID1_U16 0x0000FFFF | ||
| 1049 | #define AR_BSS_ID1_AID 0x07FF0000 | ||
| 1050 | #define AR_BSS_ID1_AID_S 16 | ||
| 1051 | |||
| 1052 | #define AR_BCN_RSSI_AVE 0x8010 | ||
| 1053 | #define AR_BCN_RSSI_AVE_MASK 0x00000FFF | ||
| 1054 | |||
| 1055 | #define AR_TIME_OUT 0x8014 | ||
| 1056 | #define AR_TIME_OUT_ACK 0x00003FFF | ||
| 1057 | #define AR_TIME_OUT_ACK_S 0 | ||
| 1058 | #define AR_TIME_OUT_CTS 0x3FFF0000 | ||
| 1059 | #define AR_TIME_OUT_CTS_S 16 | ||
| 1060 | |||
| 1061 | #define AR_RSSI_THR 0x8018 | ||
| 1062 | #define AR_RSSI_THR_MASK 0x000000FF | ||
| 1063 | #define AR_RSSI_THR_BM_THR 0x0000FF00 | ||
| 1064 | #define AR_RSSI_THR_BM_THR_S 8 | ||
| 1065 | #define AR_RSSI_BCN_WEIGHT 0x1F000000 | ||
| 1066 | #define AR_RSSI_BCN_WEIGHT_S 24 | ||
| 1067 | #define AR_RSSI_BCN_RSSI_RST 0x20000000 | ||
| 1068 | |||
| 1069 | #define AR_USEC 0x801c | ||
| 1070 | #define AR_USEC_USEC 0x0000007F | ||
| 1071 | #define AR_USEC_TX_LAT 0x007FC000 | ||
| 1072 | #define AR_USEC_TX_LAT_S 14 | ||
| 1073 | #define AR_USEC_RX_LAT 0x1F800000 | ||
| 1074 | #define AR_USEC_RX_LAT_S 23 | ||
| 1075 | |||
| 1076 | #define AR_RESET_TSF 0x8020 | ||
| 1077 | #define AR_RESET_TSF_ONCE 0x01000000 | ||
| 1078 | |||
| 1079 | #define AR_MAX_CFP_DUR 0x8038 | ||
| 1080 | #define AR_CFP_VAL 0x0000FFFF | ||
| 1081 | |||
| 1082 | #define AR_RX_FILTER 0x803C | ||
| 1083 | #define AR_RX_FILTER_ALL 0x00000000 | ||
| 1084 | #define AR_RX_UCAST 0x00000001 | ||
| 1085 | #define AR_RX_MCAST 0x00000002 | ||
| 1086 | #define AR_RX_BCAST 0x00000004 | ||
| 1087 | #define AR_RX_CONTROL 0x00000008 | ||
| 1088 | #define AR_RX_BEACON 0x00000010 | ||
| 1089 | #define AR_RX_PROM 0x00000020 | ||
| 1090 | #define AR_RX_PROBE_REQ 0x00000080 | ||
| 1091 | #define AR_RX_MY_BEACON 0x00000200 | ||
| 1092 | #define AR_RX_COMPR_BAR 0x00000400 | ||
| 1093 | #define AR_RX_COMPR_BA 0x00000800 | ||
| 1094 | #define AR_RX_UNCOM_BA_BAR 0x00001000 | ||
| 1095 | |||
| 1096 | #define AR_MCAST_FIL0 0x8040 | ||
| 1097 | #define AR_MCAST_FIL1 0x8044 | ||
| 1098 | |||
| 1099 | #define AR_DIAG_SW 0x8048 | ||
| 1100 | #define AR_DIAG_CACHE_ACK 0x00000001 | ||
| 1101 | #define AR_DIAG_ACK_DIS 0x00000002 | ||
| 1102 | #define AR_DIAG_CTS_DIS 0x00000004 | ||
| 1103 | #define AR_DIAG_ENCRYPT_DIS 0x00000008 | ||
| 1104 | #define AR_DIAG_DECRYPT_DIS 0x00000010 | ||
| 1105 | #define AR_DIAG_RX_DIS 0x00000020 | ||
| 1106 | #define AR_DIAG_LOOP_BACK 0x00000040 | ||
| 1107 | #define AR_DIAG_CORR_FCS 0x00000080 | ||
| 1108 | #define AR_DIAG_CHAN_INFO 0x00000100 | ||
| 1109 | #define AR_DIAG_SCRAM_SEED 0x0001FE00 | ||
| 1110 | #define AR_DIAG_SCRAM_SEED_S 8 | ||
| 1111 | #define AR_DIAG_FRAME_NV0 0x00020000 | ||
| 1112 | #define AR_DIAG_OBS_PT_SEL1 0x000C0000 | ||
| 1113 | #define AR_DIAG_OBS_PT_SEL1_S 18 | ||
| 1114 | #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 | ||
| 1115 | #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 | ||
| 1116 | #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 | ||
| 1117 | #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 | ||
| 1118 | #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 | ||
| 1119 | #define AR_DIAG_RX_ABORT 0x02000000 | ||
| 1120 | #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 | ||
| 1121 | #define AR_DIAG_OBS_PT_SEL2 0x08000000 | ||
| 1122 | #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 | ||
| 1123 | #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 | ||
| 1124 | |||
| 1125 | #define AR_TSF_L32 0x804c | ||
| 1126 | #define AR_TSF_U32 0x8050 | ||
| 1127 | |||
| 1128 | #define AR_TST_ADDAC 0x8054 | ||
| 1129 | #define AR_DEF_ANTENNA 0x8058 | ||
| 1130 | |||
| 1131 | #define AR_AES_MUTE_MASK0 0x805c | ||
| 1132 | #define AR_AES_MUTE_MASK0_FC 0x0000FFFF | ||
| 1133 | #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 | ||
| 1134 | #define AR_AES_MUTE_MASK0_QOS_S 16 | ||
| 1135 | |||
| 1136 | #define AR_AES_MUTE_MASK1 0x8060 | ||
| 1137 | #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF | ||
| 1138 | |||
| 1139 | #define AR_GATED_CLKS 0x8064 | ||
| 1140 | #define AR_GATED_CLKS_TX 0x00000002 | ||
| 1141 | #define AR_GATED_CLKS_RX 0x00000004 | ||
| 1142 | #define AR_GATED_CLKS_REG 0x00000008 | ||
| 1143 | |||
| 1144 | #define AR_OBS_BUS_CTRL 0x8068 | ||
| 1145 | #define AR_OBS_BUS_SEL_1 0x00040000 | ||
| 1146 | #define AR_OBS_BUS_SEL_2 0x00080000 | ||
| 1147 | #define AR_OBS_BUS_SEL_3 0x000C0000 | ||
| 1148 | #define AR_OBS_BUS_SEL_4 0x08040000 | ||
| 1149 | #define AR_OBS_BUS_SEL_5 0x08080000 | ||
| 1150 | |||
| 1151 | #define AR_OBS_BUS_1 0x806c | ||
| 1152 | #define AR_OBS_BUS_1_PCU 0x00000001 | ||
| 1153 | #define AR_OBS_BUS_1_RX_END 0x00000002 | ||
| 1154 | #define AR_OBS_BUS_1_RX_WEP 0x00000004 | ||
| 1155 | #define AR_OBS_BUS_1_RX_BEACON 0x00000008 | ||
| 1156 | #define AR_OBS_BUS_1_RX_FILTER 0x00000010 | ||
| 1157 | #define AR_OBS_BUS_1_TX_HCF 0x00000020 | ||
| 1158 | #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 | ||
| 1159 | #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 | ||
| 1160 | #define AR_OBS_BUS_1_TX_HOLD 0x00000100 | ||
| 1161 | #define AR_OBS_BUS_1_TX_FRAME 0x00000200 | ||
| 1162 | #define AR_OBS_BUS_1_RX_FRAME 0x00000400 | ||
| 1163 | #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 | ||
| 1164 | #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 | ||
| 1165 | #define AR_OBS_BUS_1_WEP_STATE_S 12 | ||
| 1166 | #define AR_OBS_BUS_1_RX_STATE 0x01F00000 | ||
| 1167 | #define AR_OBS_BUS_1_RX_STATE_S 20 | ||
| 1168 | #define AR_OBS_BUS_1_TX_STATE 0x7E000000 | ||
| 1169 | #define AR_OBS_BUS_1_TX_STATE_S 25 | ||
| 1170 | |||
| 1171 | #define AR_LAST_TSTP 0x8080 | ||
| 1172 | #define AR_NAV 0x8084 | ||
| 1173 | #define AR_RTS_OK 0x8088 | ||
| 1174 | #define AR_RTS_FAIL 0x808c | ||
| 1175 | #define AR_ACK_FAIL 0x8090 | ||
| 1176 | #define AR_FCS_FAIL 0x8094 | ||
| 1177 | #define AR_BEACON_CNT 0x8098 | ||
| 1178 | |||
| 1179 | #define AR_SLEEP1 0x80d4 | ||
| 1180 | #define AR_SLEEP1_ASSUME_DTIM 0x00080000 | ||
| 1181 | #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 | ||
| 1182 | #define AR_SLEEP1_CAB_TIMEOUT_S 21 | ||
| 1183 | |||
| 1184 | #define AR_SLEEP2 0x80d8 | ||
| 1185 | #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 | ||
| 1186 | #define AR_SLEEP2_BEACON_TIMEOUT_S 21 | ||
| 1187 | |||
| 1188 | #define AR_BSSMSKL 0x80e0 | ||
| 1189 | #define AR_BSSMSKU 0x80e4 | ||
| 1190 | |||
| 1191 | #define AR_TPC 0x80e8 | ||
| 1192 | #define AR_TPC_ACK 0x0000003f | ||
| 1193 | #define AR_TPC_ACK_S 0x00 | ||
| 1194 | #define AR_TPC_CTS 0x00003f00 | ||
| 1195 | #define AR_TPC_CTS_S 0x08 | ||
| 1196 | #define AR_TPC_CHIRP 0x003f0000 | ||
| 1197 | #define AR_TPC_CHIRP_S 0x16 | ||
| 1198 | |||
| 1199 | #define AR_TFCNT 0x80ec | ||
| 1200 | #define AR_RFCNT 0x80f0 | ||
| 1201 | #define AR_RCCNT 0x80f4 | ||
| 1202 | #define AR_CCCNT 0x80f8 | ||
| 1203 | |||
| 1204 | #define AR_QUIET1 0x80fc | ||
| 1205 | #define AR_QUIET1_NEXT_QUIET_S 0 | ||
| 1206 | #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff | ||
| 1207 | #define AR_QUIET1_QUIET_ENABLE 0x00010000 | ||
| 1208 | #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 | ||
| 1209 | #define AR_QUIET2 0x8100 | ||
| 1210 | #define AR_QUIET2_QUIET_PERIOD_S 0 | ||
| 1211 | #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff | ||
| 1212 | #define AR_QUIET2_QUIET_DUR_S 16 | ||
| 1213 | #define AR_QUIET2_QUIET_DUR 0xffff0000 | ||
| 1214 | |||
| 1215 | #define AR_TSF_PARM 0x8104 | ||
| 1216 | #define AR_TSF_INCREMENT_M 0x000000ff | ||
| 1217 | #define AR_TSF_INCREMENT_S 0x00 | ||
| 1218 | |||
| 1219 | #define AR_QOS_NO_ACK 0x8108 | ||
| 1220 | #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f | ||
| 1221 | #define AR_QOS_NO_ACK_TWO_BIT_S 0 | ||
| 1222 | #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 | ||
| 1223 | #define AR_QOS_NO_ACK_BIT_OFF_S 4 | ||
| 1224 | #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 | ||
| 1225 | #define AR_QOS_NO_ACK_BYTE_OFF_S 7 | ||
| 1226 | |||
| 1227 | #define AR_PHY_ERR 0x810c | ||
| 1228 | |||
| 1229 | #define AR_PHY_ERR_DCHIRP 0x00000008 | ||
| 1230 | #define AR_PHY_ERR_RADAR 0x00000020 | ||
| 1231 | #define AR_PHY_ERR_OFDM_TIMING 0x00020000 | ||
| 1232 | #define AR_PHY_ERR_CCK_TIMING 0x02000000 | ||
| 1233 | |||
| 1234 | #define AR_RXFIFO_CFG 0x8114 | ||
| 1235 | |||
| 1236 | |||
| 1237 | #define AR_MIC_QOS_CONTROL 0x8118 | ||
| 1238 | #define AR_MIC_QOS_SELECT 0x811c | ||
| 1239 | |||
| 1240 | #define AR_PCU_MISC 0x8120 | ||
| 1241 | #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 | ||
| 1242 | #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 | ||
| 1243 | #define AR_PCU_TX_ADD_TSF 0x00000008 | ||
| 1244 | #define AR_PCU_CCK_SIFS_MODE 0x00000010 | ||
| 1245 | #define AR_PCU_RX_ANT_UPDT 0x00000800 | ||
| 1246 | #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 | ||
| 1247 | #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 | ||
| 1248 | #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 | ||
| 1249 | #define AR_PCU_FORCE_QUIET_COLL 0x00040000 | ||
| 1250 | #define AR_PCU_TBTT_PROTECT 0x00200000 | ||
| 1251 | #define AR_PCU_CLEAR_VMF 0x01000000 | ||
| 1252 | #define AR_PCU_CLEAR_BA_VALID 0x04000000 | ||
| 1253 | |||
| 1254 | |||
| 1255 | #define AR_FILT_OFDM 0x8124 | ||
| 1256 | #define AR_FILT_OFDM_COUNT 0x00FFFFFF | ||
| 1257 | |||
| 1258 | #define AR_FILT_CCK 0x8128 | ||
| 1259 | #define AR_FILT_CCK_COUNT 0x00FFFFFF | ||
| 1260 | |||
| 1261 | #define AR_PHY_ERR_1 0x812c | ||
| 1262 | #define AR_PHY_ERR_1_COUNT 0x00FFFFFF | ||
| 1263 | #define AR_PHY_ERR_MASK_1 0x8130 | ||
| 1264 | |||
| 1265 | #define AR_PHY_ERR_2 0x8134 | ||
| 1266 | #define AR_PHY_ERR_2_COUNT 0x00FFFFFF | ||
| 1267 | #define AR_PHY_ERR_MASK_2 0x8138 | ||
| 1268 | |||
| 1269 | #define AR_PHY_COUNTMAX (3 << 22) | ||
| 1270 | #define AR_MIBCNT_INTRMASK (3 << 22) | ||
| 1271 | |||
| 1272 | #define AR_TSF_THRESHOLD 0x813c | ||
| 1273 | #define AR_TSF_THRESHOLD_VAL 0x0000FFFF | ||
| 1274 | |||
| 1275 | #define AR_PHY_ERR_EIFS_MASK 8144 | ||
| 1276 | |||
| 1277 | #define AR_PHY_ERR_3 0x8168 | ||
| 1278 | #define AR_PHY_ERR_3_COUNT 0x00FFFFFF | ||
| 1279 | #define AR_PHY_ERR_MASK_3 0x816c | ||
| 1280 | |||
| 1281 | #define AR_TXSIFS 0x81d0 | ||
| 1282 | #define AR_TXSIFS_TIME 0x000000FF | ||
| 1283 | #define AR_TXSIFS_TX_LATENCY 0x00000F00 | ||
| 1284 | #define AR_TXSIFS_TX_LATENCY_S 8 | ||
| 1285 | #define AR_TXSIFS_ACK_SHIFT 0x00007000 | ||
| 1286 | #define AR_TXSIFS_ACK_SHIFT_S 12 | ||
| 1287 | |||
| 1288 | #define AR_TXOP_X 0x81ec | ||
| 1289 | #define AR_TXOP_X_VAL 0x000000FF | ||
| 1290 | |||
| 1291 | |||
| 1292 | #define AR_TXOP_0_3 0x81f0 | ||
| 1293 | #define AR_TXOP_4_7 0x81f4 | ||
| 1294 | #define AR_TXOP_8_11 0x81f8 | ||
| 1295 | #define AR_TXOP_12_15 0x81fc | ||
| 1296 | |||
| 1297 | |||
| 1298 | #define AR_NEXT_TBTT_TIMER 0x8200 | ||
| 1299 | #define AR_NEXT_DMA_BEACON_ALERT 0x8204 | ||
| 1300 | #define AR_NEXT_SWBA 0x8208 | ||
| 1301 | #define AR_NEXT_CFP 0x8208 | ||
| 1302 | #define AR_NEXT_HCF 0x820C | ||
| 1303 | #define AR_NEXT_TIM 0x8210 | ||
| 1304 | #define AR_NEXT_DTIM 0x8214 | ||
| 1305 | #define AR_NEXT_QUIET_TIMER 0x8218 | ||
| 1306 | #define AR_NEXT_NDP_TIMER 0x821C | ||
| 1307 | |||
| 1308 | #define AR_BEACON_PERIOD 0x8220 | ||
| 1309 | #define AR_DMA_BEACON_PERIOD 0x8224 | ||
| 1310 | #define AR_SWBA_PERIOD 0x8228 | ||
| 1311 | #define AR_HCF_PERIOD 0x822C | ||
| 1312 | #define AR_TIM_PERIOD 0x8230 | ||
| 1313 | #define AR_DTIM_PERIOD 0x8234 | ||
| 1314 | #define AR_QUIET_PERIOD 0x8238 | ||
| 1315 | #define AR_NDP_PERIOD 0x823C | ||
| 1316 | |||
| 1317 | #define AR_TIMER_MODE 0x8240 | ||
| 1318 | #define AR_TBTT_TIMER_EN 0x00000001 | ||
| 1319 | #define AR_DBA_TIMER_EN 0x00000002 | ||
| 1320 | #define AR_SWBA_TIMER_EN 0x00000004 | ||
| 1321 | #define AR_HCF_TIMER_EN 0x00000008 | ||
| 1322 | #define AR_TIM_TIMER_EN 0x00000010 | ||
| 1323 | #define AR_DTIM_TIMER_EN 0x00000020 | ||
| 1324 | #define AR_QUIET_TIMER_EN 0x00000040 | ||
| 1325 | #define AR_NDP_TIMER_EN 0x00000080 | ||
| 1326 | #define AR_TIMER_OVERFLOW_INDEX 0x00000700 | ||
| 1327 | #define AR_TIMER_OVERFLOW_INDEX_S 8 | ||
| 1328 | #define AR_TIMER_THRESH 0xFFFFF000 | ||
| 1329 | #define AR_TIMER_THRESH_S 12 | ||
| 1330 | |||
| 1331 | #define AR_SLP32_MODE 0x8244 | ||
| 1332 | #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF | ||
| 1333 | #define AR_SLP32_ENA 0x00100000 | ||
| 1334 | #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 | ||
| 1335 | |||
| 1336 | #define AR_SLP32_WAKE 0x8248 | ||
| 1337 | #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF | ||
| 1338 | |||
| 1339 | #define AR_SLP32_INC 0x824c | ||
| 1340 | #define AR_SLP32_TST_INC 0x000FFFFF | ||
| 1341 | |||
| 1342 | #define AR_SLP_CNT 0x8250 | ||
| 1343 | #define AR_SLP_CYCLE_CNT 0x8254 | ||
| 1344 | |||
| 1345 | #define AR_SLP_MIB_CTRL 0x8258 | ||
| 1346 | #define AR_SLP_MIB_CLEAR 0x00000001 | ||
| 1347 | #define AR_SLP_MIB_PENDING 0x00000002 | ||
| 1348 | |||
| 1349 | #define AR_2040_MODE 0x8318 | ||
| 1350 | #define AR_2040_JOINED_RX_CLEAR 0x00000001 | ||
| 1351 | |||
| 1352 | |||
| 1353 | #define AR_EXTRCCNT 0x8328 | ||
| 1354 | |||
| 1355 | #define AR_SELFGEN_MASK 0x832c | ||
| 1356 | |||
| 1357 | #define AR_PCU_TXBUF_CTRL 0x8340 | ||
| 1358 | #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF | ||
| 1359 | #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 | ||
| 1360 | #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 | ||
| 1361 | |||
| 1362 | #define AR_KEYTABLE_0 0x8800 | ||
| 1363 | #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) | ||
| 1364 | #define AR_KEY_CACHE_SIZE 128 | ||
| 1365 | #define AR_RSVD_KEYTABLE_ENTRIES 4 | ||
| 1366 | #define AR_KEY_TYPE 0x00000007 | ||
| 1367 | #define AR_KEYTABLE_TYPE_40 0x00000000 | ||
| 1368 | #define AR_KEYTABLE_TYPE_104 0x00000001 | ||
| 1369 | #define AR_KEYTABLE_TYPE_128 0x00000003 | ||
| 1370 | #define AR_KEYTABLE_TYPE_TKIP 0x00000004 | ||
| 1371 | #define AR_KEYTABLE_TYPE_AES 0x00000005 | ||
| 1372 | #define AR_KEYTABLE_TYPE_CCM 0x00000006 | ||
| 1373 | #define AR_KEYTABLE_TYPE_CLR 0x00000007 | ||
| 1374 | #define AR_KEYTABLE_ANT 0x00000008 | ||
| 1375 | #define AR_KEYTABLE_VALID 0x00008000 | ||
| 1376 | #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) | ||
| 1377 | #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) | ||
| 1378 | #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) | ||
| 1379 | #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) | ||
| 1380 | #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) | ||
| 1381 | #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) | ||
| 1382 | #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) | ||
| 1383 | #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) | ||
| 1384 | |||
| 1385 | #endif | ||
diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c new file mode 100644 index 000000000000..62e28887ccd3 --- /dev/null +++ b/drivers/net/wireless/ath9k/regd.c | |||
| @@ -0,0 +1,1026 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/slab.h> | ||
| 19 | #include "core.h" | ||
| 20 | #include "hw.h" | ||
| 21 | #include "regd.h" | ||
| 22 | #include "regd_common.h" | ||
| 23 | |||
| 24 | static int ath9k_regd_chansort(const void *a, const void *b) | ||
| 25 | { | ||
| 26 | const struct ath9k_channel *ca = a; | ||
| 27 | const struct ath9k_channel *cb = b; | ||
| 28 | |||
| 29 | return (ca->channel == cb->channel) ? | ||
| 30 | (ca->channelFlags & CHAN_FLAGS) - | ||
| 31 | (cb->channelFlags & CHAN_FLAGS) : ca->channel - cb->channel; | ||
| 32 | } | ||
| 33 | |||
| 34 | static void | ||
| 35 | ath9k_regd_sort(void *a, u32 n, u32 size, ath_hal_cmp_t *cmp) | ||
| 36 | { | ||
| 37 | u8 *aa = a; | ||
| 38 | u8 *ai, *t; | ||
| 39 | |||
| 40 | for (ai = aa + size; --n >= 1; ai += size) | ||
| 41 | for (t = ai; t > aa; t -= size) { | ||
| 42 | u8 *u = t - size; | ||
| 43 | if (cmp(u, t) <= 0) | ||
| 44 | break; | ||
| 45 | swap(u, t, size); | ||
| 46 | } | ||
| 47 | } | ||
| 48 | |||
| 49 | static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah) | ||
| 50 | { | ||
| 51 | return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG; | ||
| 52 | } | ||
| 53 | |||
| 54 | static bool ath9k_regd_is_chan_bm_zero(u64 *bitmask) | ||
| 55 | { | ||
| 56 | int i; | ||
| 57 | |||
| 58 | for (i = 0; i < BMLEN; i++) { | ||
| 59 | if (bitmask[i] != 0) | ||
| 60 | return false; | ||
| 61 | } | ||
| 62 | return true; | ||
| 63 | } | ||
| 64 | |||
| 65 | static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah) | ||
| 66 | { | ||
| 67 | u16 rd = ath9k_regd_get_eepromRD(ah); | ||
| 68 | int i; | ||
| 69 | |||
| 70 | if (rd & COUNTRY_ERD_FLAG) { | ||
| 71 | u16 cc = rd & ~COUNTRY_ERD_FLAG; | ||
| 72 | for (i = 0; i < ARRAY_SIZE(allCountries); i++) | ||
| 73 | if (allCountries[i].countryCode == cc) | ||
| 74 | return true; | ||
| 75 | } else { | ||
| 76 | for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) | ||
| 77 | if (regDomainPairs[i].regDmnEnum == rd) | ||
| 78 | return true; | ||
| 79 | } | ||
| 80 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 81 | "%s: invalid regulatory domain/country code 0x%x\n", | ||
| 82 | __func__, rd); | ||
| 83 | return false; | ||
| 84 | } | ||
| 85 | |||
| 86 | static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah) | ||
| 87 | { | ||
| 88 | u32 regcap; | ||
| 89 | |||
| 90 | regcap = ah->ah_caps.reg_cap; | ||
| 91 | |||
| 92 | if (regcap & AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND) | ||
| 93 | return true; | ||
| 94 | else | ||
| 95 | return false; | ||
| 96 | } | ||
| 97 | |||
| 98 | static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah, | ||
| 99 | u16 cc) | ||
| 100 | { | ||
| 101 | u16 rd; | ||
| 102 | int i; | ||
| 103 | |||
| 104 | if (cc == CTRY_DEFAULT) | ||
| 105 | return true; | ||
| 106 | if (cc == CTRY_DEBUG) | ||
| 107 | return true; | ||
| 108 | |||
| 109 | rd = ath9k_regd_get_eepromRD(ah); | ||
| 110 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: EEPROM regdomain 0x%x\n", | ||
| 111 | __func__, rd); | ||
| 112 | |||
| 113 | if (rd & COUNTRY_ERD_FLAG) { | ||
| 114 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 115 | "%s: EEPROM setting is country code %u\n", | ||
| 116 | __func__, rd & ~COUNTRY_ERD_FLAG); | ||
| 117 | return cc == (rd & ~COUNTRY_ERD_FLAG); | ||
| 118 | } | ||
| 119 | |||
| 120 | for (i = 0; i < ARRAY_SIZE(allCountries); i++) { | ||
| 121 | if (cc == allCountries[i].countryCode) { | ||
| 122 | #ifdef AH_SUPPORT_11D | ||
| 123 | if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX) | ||
| 124 | return true; | ||
| 125 | #endif | ||
| 126 | if (allCountries[i].regDmnEnum == rd || | ||
| 127 | rd == DEBUG_REG_DMN || rd == NO_ENUMRD) | ||
| 128 | return true; | ||
| 129 | } | ||
| 130 | } | ||
| 131 | return false; | ||
| 132 | } | ||
| 133 | |||
| 134 | static void | ||
| 135 | ath9k_regd_get_wmodes_nreg(struct ath_hal *ah, | ||
| 136 | struct country_code_to_enum_rd *country, | ||
| 137 | struct regDomain *rd5GHz, | ||
| 138 | unsigned long *modes_allowed) | ||
| 139 | { | ||
| 140 | bitmap_copy(modes_allowed, ah->ah_caps.wireless_modes, ATH9K_MODE_MAX); | ||
| 141 | |||
| 142 | if (test_bit(ATH9K_MODE_11G, ah->ah_caps.wireless_modes) && | ||
| 143 | (!country->allow11g)) | ||
| 144 | clear_bit(ATH9K_MODE_11G, modes_allowed); | ||
| 145 | |||
| 146 | if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes) && | ||
| 147 | (ath9k_regd_is_chan_bm_zero(rd5GHz->chan11a))) | ||
| 148 | clear_bit(ATH9K_MODE_11A, modes_allowed); | ||
| 149 | |||
| 150 | if (test_bit(ATH9K_MODE_11NG_HT20, ah->ah_caps.wireless_modes) | ||
| 151 | && (!country->allow11ng20)) | ||
| 152 | clear_bit(ATH9K_MODE_11NG_HT20, modes_allowed); | ||
| 153 | |||
| 154 | if (test_bit(ATH9K_MODE_11NA_HT20, ah->ah_caps.wireless_modes) | ||
| 155 | && (!country->allow11na20)) | ||
| 156 | clear_bit(ATH9K_MODE_11NA_HT20, modes_allowed); | ||
| 157 | |||
| 158 | if (test_bit(ATH9K_MODE_11NG_HT40PLUS, ah->ah_caps.wireless_modes) && | ||
| 159 | (!country->allow11ng40)) | ||
| 160 | clear_bit(ATH9K_MODE_11NG_HT40PLUS, modes_allowed); | ||
| 161 | |||
| 162 | if (test_bit(ATH9K_MODE_11NG_HT40MINUS, ah->ah_caps.wireless_modes) && | ||
| 163 | (!country->allow11ng40)) | ||
| 164 | clear_bit(ATH9K_MODE_11NG_HT40MINUS, modes_allowed); | ||
| 165 | |||
| 166 | if (test_bit(ATH9K_MODE_11NA_HT40PLUS, ah->ah_caps.wireless_modes) && | ||
| 167 | (!country->allow11na40)) | ||
| 168 | clear_bit(ATH9K_MODE_11NA_HT40PLUS, modes_allowed); | ||
| 169 | |||
| 170 | if (test_bit(ATH9K_MODE_11NA_HT40MINUS, ah->ah_caps.wireless_modes) && | ||
| 171 | (!country->allow11na40)) | ||
| 172 | clear_bit(ATH9K_MODE_11NA_HT40MINUS, modes_allowed); | ||
| 173 | } | ||
| 174 | |||
| 175 | bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah) | ||
| 176 | { | ||
| 177 | u16 rd; | ||
| 178 | |||
| 179 | rd = ath9k_regd_get_eepromRD(ah); | ||
| 180 | |||
| 181 | switch (rd) { | ||
| 182 | case FCC4_FCCA: | ||
| 183 | case (CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG): | ||
| 184 | return true; | ||
| 185 | case DEBUG_REG_DMN: | ||
| 186 | case NO_ENUMRD: | ||
| 187 | if (ah->ah_countryCode == CTRY_UNITED_STATES_FCC49) | ||
| 188 | return true; | ||
| 189 | break; | ||
| 190 | } | ||
| 191 | return false; | ||
| 192 | } | ||
| 193 | |||
| 194 | static struct country_code_to_enum_rd* | ||
| 195 | ath9k_regd_find_country(u16 countryCode) | ||
| 196 | { | ||
| 197 | int i; | ||
| 198 | |||
| 199 | for (i = 0; i < ARRAY_SIZE(allCountries); i++) { | ||
| 200 | if (allCountries[i].countryCode == countryCode) | ||
| 201 | return &allCountries[i]; | ||
| 202 | } | ||
| 203 | return NULL; | ||
| 204 | } | ||
| 205 | |||
| 206 | static u16 ath9k_regd_get_default_country(struct ath_hal *ah) | ||
| 207 | { | ||
| 208 | u16 rd; | ||
| 209 | int i; | ||
| 210 | |||
| 211 | rd = ath9k_regd_get_eepromRD(ah); | ||
| 212 | if (rd & COUNTRY_ERD_FLAG) { | ||
| 213 | struct country_code_to_enum_rd *country = NULL; | ||
| 214 | u16 cc = rd & ~COUNTRY_ERD_FLAG; | ||
| 215 | |||
| 216 | country = ath9k_regd_find_country(cc); | ||
| 217 | if (country != NULL) | ||
| 218 | return cc; | ||
| 219 | } | ||
| 220 | |||
| 221 | for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) | ||
| 222 | if (regDomainPairs[i].regDmnEnum == rd) { | ||
| 223 | if (regDomainPairs[i].singleCC != 0) | ||
| 224 | return regDomainPairs[i].singleCC; | ||
| 225 | else | ||
| 226 | i = ARRAY_SIZE(regDomainPairs); | ||
| 227 | } | ||
| 228 | return CTRY_DEFAULT; | ||
| 229 | } | ||
| 230 | |||
| 231 | static bool ath9k_regd_is_valid_reg_domain(int regDmn, | ||
| 232 | struct regDomain *rd) | ||
| 233 | { | ||
| 234 | int i; | ||
| 235 | |||
| 236 | for (i = 0; i < ARRAY_SIZE(regDomains); i++) { | ||
| 237 | if (regDomains[i].regDmnEnum == regDmn) { | ||
| 238 | if (rd != NULL) { | ||
| 239 | memcpy(rd, ®Domains[i], | ||
| 240 | sizeof(struct regDomain)); | ||
| 241 | } | ||
| 242 | return true; | ||
| 243 | } | ||
| 244 | } | ||
| 245 | return false; | ||
| 246 | } | ||
| 247 | |||
| 248 | static bool ath9k_regd_is_valid_reg_domainPair(int regDmnPair) | ||
| 249 | { | ||
| 250 | int i; | ||
| 251 | |||
| 252 | if (regDmnPair == NO_ENUMRD) | ||
| 253 | return false; | ||
| 254 | for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) { | ||
| 255 | if (regDomainPairs[i].regDmnEnum == regDmnPair) | ||
| 256 | return true; | ||
| 257 | } | ||
| 258 | return false; | ||
| 259 | } | ||
| 260 | |||
| 261 | static bool | ||
| 262 | ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn, | ||
| 263 | u16 channelFlag, struct regDomain *rd) | ||
| 264 | { | ||
| 265 | int i, found; | ||
| 266 | u64 flags = NO_REQ; | ||
| 267 | struct reg_dmn_pair_mapping *regPair = NULL; | ||
| 268 | int regOrg; | ||
| 269 | |||
| 270 | regOrg = regDmn; | ||
| 271 | if (regDmn == CTRY_DEFAULT) { | ||
| 272 | u16 rdnum; | ||
| 273 | rdnum = ath9k_regd_get_eepromRD(ah); | ||
| 274 | |||
| 275 | if (!(rdnum & COUNTRY_ERD_FLAG)) { | ||
| 276 | if (ath9k_regd_is_valid_reg_domain(rdnum, NULL) || | ||
| 277 | ath9k_regd_is_valid_reg_domainPair(rdnum)) { | ||
| 278 | regDmn = rdnum; | ||
| 279 | } | ||
| 280 | } | ||
| 281 | } | ||
| 282 | |||
| 283 | if ((regDmn & MULTI_DOMAIN_MASK) == 0) { | ||
| 284 | for (i = 0, found = 0; | ||
| 285 | (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) { | ||
| 286 | if (regDomainPairs[i].regDmnEnum == regDmn) { | ||
| 287 | regPair = ®DomainPairs[i]; | ||
| 288 | found = 1; | ||
| 289 | } | ||
| 290 | } | ||
| 291 | if (!found) { | ||
| 292 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 293 | "%s: Failed to find reg domain pair %u\n", | ||
| 294 | __func__, regDmn); | ||
| 295 | return false; | ||
| 296 | } | ||
| 297 | if (!(channelFlag & CHANNEL_2GHZ)) { | ||
| 298 | regDmn = regPair->regDmn5GHz; | ||
| 299 | flags = regPair->flags5GHz; | ||
| 300 | } | ||
| 301 | if (channelFlag & CHANNEL_2GHZ) { | ||
| 302 | regDmn = regPair->regDmn2GHz; | ||
| 303 | flags = regPair->flags2GHz; | ||
| 304 | } | ||
| 305 | } | ||
| 306 | |||
| 307 | found = ath9k_regd_is_valid_reg_domain(regDmn, rd); | ||
| 308 | if (!found) { | ||
| 309 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 310 | "%s: Failed to find unitary reg domain %u\n", | ||
| 311 | __func__, regDmn); | ||
| 312 | return false; | ||
| 313 | } else { | ||
| 314 | rd->pscan &= regPair->pscanMask; | ||
| 315 | if (((regOrg & MULTI_DOMAIN_MASK) == 0) && | ||
| 316 | (flags != NO_REQ)) { | ||
| 317 | rd->flags = flags; | ||
| 318 | } | ||
| 319 | |||
| 320 | rd->flags &= (channelFlag & CHANNEL_2GHZ) ? | ||
| 321 | REG_DOMAIN_2GHZ_MASK : REG_DOMAIN_5GHZ_MASK; | ||
| 322 | return true; | ||
| 323 | } | ||
| 324 | } | ||
| 325 | |||
| 326 | static bool ath9k_regd_is_bit_set(int bit, u64 *bitmask) | ||
| 327 | { | ||
| 328 | int byteOffset, bitnum; | ||
| 329 | u64 val; | ||
| 330 | |||
| 331 | byteOffset = bit / 64; | ||
| 332 | bitnum = bit - byteOffset * 64; | ||
| 333 | val = ((u64) 1) << bitnum; | ||
| 334 | if (bitmask[byteOffset] & val) | ||
| 335 | return true; | ||
| 336 | else | ||
| 337 | return false; | ||
| 338 | } | ||
| 339 | |||
| 340 | static void | ||
| 341 | ath9k_regd_add_reg_classid(u8 *regclassids, u32 maxregids, | ||
| 342 | u32 *nregids, u8 regclassid) | ||
| 343 | { | ||
| 344 | int i; | ||
| 345 | |||
| 346 | if (regclassid == 0) | ||
| 347 | return; | ||
| 348 | |||
| 349 | for (i = 0; i < maxregids; i++) { | ||
| 350 | if (regclassids[i] == regclassid) | ||
| 351 | return; | ||
| 352 | if (regclassids[i] == 0) | ||
| 353 | break; | ||
| 354 | } | ||
| 355 | |||
| 356 | if (i == maxregids) | ||
| 357 | return; | ||
| 358 | else { | ||
| 359 | regclassids[i] = regclassid; | ||
| 360 | *nregids += 1; | ||
| 361 | } | ||
| 362 | |||
| 363 | return; | ||
| 364 | } | ||
| 365 | |||
| 366 | static bool | ||
| 367 | ath9k_regd_get_eeprom_reg_ext_bits(struct ath_hal *ah, | ||
| 368 | enum reg_ext_bitmap bit) | ||
| 369 | { | ||
| 370 | return (ah->ah_currentRDExt & (1 << bit)) ? true : false; | ||
| 371 | } | ||
| 372 | |||
| 373 | #ifdef ATH_NF_PER_CHAN | ||
| 374 | |||
| 375 | static void ath9k_regd_init_rf_buffer(struct ath9k_channel *ichans, | ||
| 376 | int nchans) | ||
| 377 | { | ||
| 378 | int i, j, next; | ||
| 379 | |||
| 380 | for (next = 0; next < nchans; next++) { | ||
| 381 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
| 382 | ichans[next].nfCalHist[i].currIndex = 0; | ||
| 383 | ichans[next].nfCalHist[i].privNF = | ||
| 384 | AR_PHY_CCA_MAX_GOOD_VALUE; | ||
| 385 | ichans[next].nfCalHist[i].invalidNFcount = | ||
| 386 | AR_PHY_CCA_FILTERWINDOW_LENGTH; | ||
| 387 | for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) { | ||
| 388 | ichans[next].nfCalHist[i].nfCalBuffer[j] = | ||
| 389 | AR_PHY_CCA_MAX_GOOD_VALUE; | ||
| 390 | } | ||
| 391 | } | ||
| 392 | } | ||
| 393 | } | ||
| 394 | #endif | ||
| 395 | |||
| 396 | static int ath9k_regd_is_chan_present(struct ath_hal *ah, | ||
| 397 | u16 c) | ||
| 398 | { | ||
| 399 | int i; | ||
| 400 | |||
| 401 | for (i = 0; i < 150; i++) { | ||
| 402 | if (!ah->ah_channels[i].channel) | ||
| 403 | return -1; | ||
| 404 | else if (ah->ah_channels[i].channel == c) | ||
| 405 | return i; | ||
| 406 | } | ||
| 407 | |||
| 408 | return -1; | ||
| 409 | } | ||
| 410 | |||
| 411 | static bool | ||
| 412 | ath9k_regd_add_channel(struct ath_hal *ah, | ||
| 413 | u16 c, | ||
| 414 | u16 c_lo, | ||
| 415 | u16 c_hi, | ||
| 416 | u16 maxChan, | ||
| 417 | u8 ctl, | ||
| 418 | int pos, | ||
| 419 | struct regDomain rd5GHz, | ||
| 420 | struct RegDmnFreqBand *fband, | ||
| 421 | struct regDomain *rd, | ||
| 422 | const struct cmode *cm, | ||
| 423 | struct ath9k_channel *ichans, | ||
| 424 | bool enableExtendedChannels) | ||
| 425 | { | ||
| 426 | struct ath9k_channel *chan; | ||
| 427 | int ret; | ||
| 428 | u32 channelFlags = 0; | ||
| 429 | u8 privFlags = 0; | ||
| 430 | |||
| 431 | if (!(c_lo <= c && c <= c_hi)) { | ||
| 432 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 433 | "%s: c %u out of range [%u..%u]\n", | ||
| 434 | __func__, c, c_lo, c_hi); | ||
| 435 | return false; | ||
| 436 | } | ||
| 437 | if ((fband->channelBW == CHANNEL_HALF_BW) && | ||
| 438 | !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) { | ||
| 439 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 440 | "%s: Skipping %u half rate channel\n", | ||
| 441 | __func__, c); | ||
| 442 | return false; | ||
| 443 | } | ||
| 444 | |||
| 445 | if ((fband->channelBW == CHANNEL_QUARTER_BW) && | ||
| 446 | !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) { | ||
| 447 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 448 | "%s: Skipping %u quarter rate channel\n", | ||
| 449 | __func__, c); | ||
| 450 | return false; | ||
| 451 | } | ||
| 452 | |||
| 453 | if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) { | ||
| 454 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 455 | "%s: c %u > maxChan %u\n", | ||
| 456 | __func__, c, maxChan); | ||
| 457 | return false; | ||
| 458 | } | ||
| 459 | |||
| 460 | if ((fband->usePassScan & IS_ECM_CHAN) && !enableExtendedChannels) { | ||
| 461 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 462 | "Skipping ecm channel\n"); | ||
| 463 | return false; | ||
| 464 | } | ||
| 465 | |||
| 466 | if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == ATH9K_M_HOSTAP)) { | ||
| 467 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 468 | "Skipping HOSTAP channel\n"); | ||
| 469 | return false; | ||
| 470 | } | ||
| 471 | |||
| 472 | if (IS_HT40_MODE(cm->mode) && | ||
| 473 | !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_FCC_DFS_HT40)) && | ||
| 474 | (fband->useDfs) && | ||
| 475 | (rd->conformanceTestLimit != MKK)) { | ||
| 476 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 477 | "Skipping HT40 channel (en_fcc_dfs_ht40 = 0)\n"); | ||
| 478 | return false; | ||
| 479 | } | ||
| 480 | |||
| 481 | if (IS_HT40_MODE(cm->mode) && | ||
| 482 | !(ath9k_regd_get_eeprom_reg_ext_bits(ah, | ||
| 483 | REG_EXT_JAPAN_NONDFS_HT40)) && | ||
| 484 | !(fband->useDfs) && (rd->conformanceTestLimit == MKK)) { | ||
| 485 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 486 | "Skipping HT40 channel (en_jap_ht40 = 0)\n"); | ||
| 487 | return false; | ||
| 488 | } | ||
| 489 | |||
| 490 | if (IS_HT40_MODE(cm->mode) && | ||
| 491 | !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_JAPAN_DFS_HT40)) && | ||
| 492 | (fband->useDfs) && | ||
| 493 | (rd->conformanceTestLimit == MKK)) { | ||
| 494 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 495 | "Skipping HT40 channel (en_jap_dfs_ht40 = 0)\n"); | ||
| 496 | return false; | ||
| 497 | } | ||
| 498 | |||
| 499 | /* Calculate channel flags */ | ||
| 500 | |||
| 501 | channelFlags = cm->flags; | ||
| 502 | |||
| 503 | switch (fband->channelBW) { | ||
| 504 | case CHANNEL_HALF_BW: | ||
| 505 | channelFlags |= CHANNEL_HALF; | ||
| 506 | break; | ||
| 507 | case CHANNEL_QUARTER_BW: | ||
| 508 | channelFlags |= CHANNEL_QUARTER; | ||
| 509 | break; | ||
| 510 | } | ||
| 511 | |||
| 512 | if (fband->usePassScan & rd->pscan) | ||
| 513 | channelFlags |= CHANNEL_PASSIVE; | ||
| 514 | else | ||
| 515 | channelFlags &= ~CHANNEL_PASSIVE; | ||
| 516 | if (fband->useDfs & rd->dfsMask) | ||
| 517 | privFlags = CHANNEL_DFS; | ||
| 518 | else | ||
| 519 | privFlags = 0; | ||
| 520 | if (rd->flags & LIMIT_FRAME_4MS) | ||
| 521 | privFlags |= CHANNEL_4MS_LIMIT; | ||
| 522 | if (privFlags & CHANNEL_DFS) | ||
| 523 | privFlags |= CHANNEL_DISALLOW_ADHOC; | ||
| 524 | if (rd->flags & ADHOC_PER_11D) | ||
| 525 | privFlags |= CHANNEL_PER_11D_ADHOC; | ||
| 526 | |||
| 527 | if (channelFlags & CHANNEL_PASSIVE) { | ||
| 528 | if ((c < 2412) || (c > 2462)) { | ||
| 529 | if (rd5GHz.regDmnEnum == MKK1 || | ||
| 530 | rd5GHz.regDmnEnum == MKK2) { | ||
| 531 | u32 regcap = ah->ah_caps.reg_cap; | ||
| 532 | if (!(regcap & | ||
| 533 | (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | ||
| 534 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | ||
| 535 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) && | ||
| 536 | isUNII1OddChan(c)) { | ||
| 537 | channelFlags &= ~CHANNEL_PASSIVE; | ||
| 538 | } else { | ||
| 539 | privFlags |= CHANNEL_DISALLOW_ADHOC; | ||
| 540 | } | ||
| 541 | } else { | ||
| 542 | privFlags |= CHANNEL_DISALLOW_ADHOC; | ||
| 543 | } | ||
| 544 | } | ||
| 545 | } | ||
| 546 | |||
| 547 | if ((cm->mode == ATH9K_MODE_11A) || | ||
| 548 | (cm->mode == ATH9K_MODE_11NA_HT20) || | ||
| 549 | (cm->mode == ATH9K_MODE_11NA_HT40PLUS) || | ||
| 550 | (cm->mode == ATH9K_MODE_11NA_HT40MINUS)) { | ||
| 551 | if (rd->flags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A)) | ||
| 552 | privFlags |= CHANNEL_DISALLOW_ADHOC; | ||
| 553 | } | ||
| 554 | |||
| 555 | /* Fill in channel details */ | ||
| 556 | |||
| 557 | ret = ath9k_regd_is_chan_present(ah, c); | ||
| 558 | if (ret == -1) { | ||
| 559 | chan = &ah->ah_channels[pos]; | ||
| 560 | chan->channel = c; | ||
| 561 | chan->maxRegTxPower = fband->powerDfs; | ||
| 562 | chan->antennaMax = fband->antennaMax; | ||
| 563 | chan->regDmnFlags = rd->flags; | ||
| 564 | chan->maxTxPower = AR5416_MAX_RATE_POWER; | ||
| 565 | chan->minTxPower = AR5416_MAX_RATE_POWER; | ||
| 566 | chan->channelFlags = channelFlags; | ||
| 567 | chan->privFlags = privFlags; | ||
| 568 | } else { | ||
| 569 | chan = &ah->ah_channels[ret]; | ||
| 570 | chan->channelFlags |= channelFlags; | ||
| 571 | chan->privFlags |= privFlags; | ||
| 572 | } | ||
| 573 | |||
| 574 | /* Set CTLs */ | ||
| 575 | |||
| 576 | if ((cm->flags & CHANNEL_ALL) == CHANNEL_A) | ||
| 577 | chan->conformanceTestLimit[0] = ctl; | ||
| 578 | else if ((cm->flags & CHANNEL_ALL) == CHANNEL_B) | ||
| 579 | chan->conformanceTestLimit[1] = ctl; | ||
| 580 | else if ((cm->flags & CHANNEL_ALL) == CHANNEL_G) | ||
| 581 | chan->conformanceTestLimit[2] = ctl; | ||
| 582 | |||
| 583 | return (ret == -1) ? true : false; | ||
| 584 | } | ||
| 585 | |||
| 586 | static bool ath9k_regd_japan_check(struct ath_hal *ah, | ||
| 587 | int b, | ||
| 588 | struct regDomain *rd5GHz) | ||
| 589 | { | ||
| 590 | bool skipband = false; | ||
| 591 | int i; | ||
| 592 | u32 regcap; | ||
| 593 | |||
| 594 | for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) { | ||
| 595 | if (j_bandcheck[i].freqbandbit == b) { | ||
| 596 | regcap = ah->ah_caps.reg_cap; | ||
| 597 | if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) { | ||
| 598 | skipband = true; | ||
| 599 | } else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) || | ||
| 600 | (regcap & AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) { | ||
| 601 | rd5GHz->dfsMask |= DFS_MKK4; | ||
| 602 | rd5GHz->pscan |= PSCAN_MKK3; | ||
| 603 | } | ||
| 604 | break; | ||
| 605 | } | ||
| 606 | } | ||
| 607 | |||
| 608 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 609 | "%s: Skipping %d freq band\n", | ||
| 610 | __func__, j_bandcheck[i].freqbandbit); | ||
| 611 | |||
| 612 | return skipband; | ||
| 613 | } | ||
| 614 | |||
| 615 | bool | ||
| 616 | ath9k_regd_init_channels(struct ath_hal *ah, | ||
| 617 | u32 maxchans, | ||
| 618 | u32 *nchans, u8 *regclassids, | ||
| 619 | u32 maxregids, u32 *nregids, u16 cc, | ||
| 620 | bool enableOutdoor, | ||
| 621 | bool enableExtendedChannels) | ||
| 622 | { | ||
| 623 | u16 maxChan = 7000; | ||
| 624 | struct country_code_to_enum_rd *country = NULL; | ||
| 625 | struct regDomain rd5GHz, rd2GHz; | ||
| 626 | const struct cmode *cm; | ||
| 627 | struct ath9k_channel *ichans = &ah->ah_channels[0]; | ||
| 628 | int next = 0, b; | ||
| 629 | u8 ctl; | ||
| 630 | int regdmn; | ||
| 631 | u16 chanSep; | ||
| 632 | unsigned long *modes_avail; | ||
| 633 | DECLARE_BITMAP(modes_allowed, ATH9K_MODE_MAX); | ||
| 634 | |||
| 635 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u %s %s\n", | ||
| 636 | __func__, cc, | ||
| 637 | enableOutdoor ? "Enable outdoor" : "", | ||
| 638 | enableExtendedChannels ? "Enable ecm" : ""); | ||
| 639 | |||
| 640 | if (!ath9k_regd_is_ccode_valid(ah, cc)) { | ||
| 641 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 642 | "%s: invalid country code %d\n", __func__, cc); | ||
| 643 | return false; | ||
| 644 | } | ||
| 645 | |||
| 646 | if (!ath9k_regd_is_eeprom_valid(ah)) { | ||
| 647 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 648 | "%s: invalid EEPROM contents\n", __func__); | ||
| 649 | return false; | ||
| 650 | } | ||
| 651 | |||
| 652 | ah->ah_countryCode = ath9k_regd_get_default_country(ah); | ||
| 653 | |||
| 654 | if (ah->ah_countryCode == CTRY_DEFAULT) { | ||
| 655 | ah->ah_countryCode = cc & COUNTRY_CODE_MASK; | ||
| 656 | if ((ah->ah_countryCode == CTRY_DEFAULT) && | ||
| 657 | (ath9k_regd_get_eepromRD(ah) == CTRY_DEFAULT)) { | ||
| 658 | ah->ah_countryCode = CTRY_UNITED_STATES; | ||
| 659 | } | ||
| 660 | } | ||
| 661 | |||
| 662 | #ifdef AH_SUPPORT_11D | ||
| 663 | if (ah->ah_countryCode == CTRY_DEFAULT) { | ||
| 664 | regdmn = ath9k_regd_get_eepromRD(ah); | ||
| 665 | country = NULL; | ||
| 666 | } else { | ||
| 667 | #endif | ||
| 668 | country = ath9k_regd_find_country(ah->ah_countryCode); | ||
| 669 | if (country == NULL) { | ||
| 670 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 671 | "Country is NULL!!!!, cc= %d\n", | ||
| 672 | ah->ah_countryCode); | ||
| 673 | return false; | ||
| 674 | } else { | ||
| 675 | regdmn = country->regDmnEnum; | ||
| 676 | #ifdef AH_SUPPORT_11D | ||
| 677 | if (((ath9k_regd_get_eepromRD(ah) & | ||
| 678 | WORLD_SKU_MASK) == WORLD_SKU_PREFIX) && | ||
| 679 | (cc == CTRY_UNITED_STATES)) { | ||
| 680 | if (!isWwrSKU_NoMidband(ah) | ||
| 681 | && ath9k_regd_is_fcc_midband_supported(ah)) | ||
| 682 | regdmn = FCC3_FCCA; | ||
| 683 | else | ||
| 684 | regdmn = FCC1_FCCA; | ||
| 685 | } | ||
| 686 | #endif | ||
| 687 | } | ||
| 688 | #ifdef AH_SUPPORT_11D | ||
| 689 | } | ||
| 690 | #endif | ||
| 691 | if (!ath9k_regd_get_wmode_regdomain(ah, | ||
| 692 | regdmn, | ||
| 693 | ~CHANNEL_2GHZ, | ||
| 694 | &rd5GHz)) { | ||
| 695 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 696 | "%s: couldn't find unitary " | ||
| 697 | "5GHz reg domain for country %u\n", | ||
| 698 | __func__, ah->ah_countryCode); | ||
| 699 | return false; | ||
| 700 | } | ||
| 701 | if (!ath9k_regd_get_wmode_regdomain(ah, | ||
| 702 | regdmn, | ||
| 703 | CHANNEL_2GHZ, | ||
| 704 | &rd2GHz)) { | ||
| 705 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 706 | "%s: couldn't find unitary 2GHz " | ||
| 707 | "reg domain for country %u\n", | ||
| 708 | __func__, ah->ah_countryCode); | ||
| 709 | return false; | ||
| 710 | } | ||
| 711 | |||
| 712 | if (!isWwrSKU(ah) && ((rd5GHz.regDmnEnum == FCC1) || | ||
| 713 | (rd5GHz.regDmnEnum == FCC2))) { | ||
| 714 | if (ath9k_regd_is_fcc_midband_supported(ah)) { | ||
| 715 | if (!ath9k_regd_get_wmode_regdomain(ah, | ||
| 716 | FCC3_FCCA, | ||
| 717 | ~CHANNEL_2GHZ, | ||
| 718 | &rd5GHz)) { | ||
| 719 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 720 | "%s: couldn't find unitary 5GHz " | ||
| 721 | "reg domain for country %u\n", | ||
| 722 | __func__, ah->ah_countryCode); | ||
| 723 | return false; | ||
| 724 | } | ||
| 725 | } | ||
| 726 | } | ||
| 727 | |||
| 728 | if (country == NULL) { | ||
| 729 | modes_avail = ah->ah_caps.wireless_modes; | ||
| 730 | } else { | ||
| 731 | ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz, modes_allowed); | ||
| 732 | modes_avail = modes_allowed; | ||
| 733 | |||
| 734 | if (!enableOutdoor) | ||
| 735 | maxChan = country->outdoorChanStart; | ||
| 736 | } | ||
| 737 | |||
| 738 | next = 0; | ||
| 739 | |||
| 740 | if (maxchans > ARRAY_SIZE(ah->ah_channels)) | ||
| 741 | maxchans = ARRAY_SIZE(ah->ah_channels); | ||
| 742 | |||
| 743 | for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) { | ||
| 744 | u16 c, c_hi, c_lo; | ||
| 745 | u64 *channelBM = NULL; | ||
| 746 | struct regDomain *rd = NULL; | ||
| 747 | struct RegDmnFreqBand *fband = NULL, *freqs; | ||
| 748 | int8_t low_adj = 0, hi_adj = 0; | ||
| 749 | |||
| 750 | if (!test_bit(cm->mode, modes_avail)) { | ||
| 751 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 752 | "%s: !avail mode %d flags 0x%x\n", | ||
| 753 | __func__, cm->mode, cm->flags); | ||
| 754 | continue; | ||
| 755 | } | ||
| 756 | if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) { | ||
| 757 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 758 | "%s: channels 0x%x not supported " | ||
| 759 | "by hardware\n", | ||
| 760 | __func__, cm->flags); | ||
| 761 | continue; | ||
| 762 | } | ||
| 763 | |||
| 764 | switch (cm->mode) { | ||
| 765 | case ATH9K_MODE_11A: | ||
| 766 | case ATH9K_MODE_11NA_HT20: | ||
| 767 | case ATH9K_MODE_11NA_HT40PLUS: | ||
| 768 | case ATH9K_MODE_11NA_HT40MINUS: | ||
| 769 | rd = &rd5GHz; | ||
| 770 | channelBM = rd->chan11a; | ||
| 771 | freqs = ®Dmn5GhzFreq[0]; | ||
| 772 | ctl = rd->conformanceTestLimit; | ||
| 773 | break; | ||
| 774 | case ATH9K_MODE_11B: | ||
| 775 | rd = &rd2GHz; | ||
| 776 | channelBM = rd->chan11b; | ||
| 777 | freqs = ®Dmn2GhzFreq[0]; | ||
| 778 | ctl = rd->conformanceTestLimit | CTL_11B; | ||
| 779 | break; | ||
| 780 | case ATH9K_MODE_11G: | ||
| 781 | case ATH9K_MODE_11NG_HT20: | ||
| 782 | case ATH9K_MODE_11NG_HT40PLUS: | ||
| 783 | case ATH9K_MODE_11NG_HT40MINUS: | ||
| 784 | rd = &rd2GHz; | ||
| 785 | channelBM = rd->chan11g; | ||
| 786 | freqs = ®Dmn2Ghz11gFreq[0]; | ||
| 787 | ctl = rd->conformanceTestLimit | CTL_11G; | ||
| 788 | break; | ||
| 789 | default: | ||
| 790 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 791 | "%s: Unknown HAL mode 0x%x\n", __func__, | ||
| 792 | cm->mode); | ||
| 793 | continue; | ||
| 794 | } | ||
| 795 | |||
| 796 | if (ath9k_regd_is_chan_bm_zero(channelBM)) | ||
| 797 | continue; | ||
| 798 | |||
| 799 | if ((cm->mode == ATH9K_MODE_11NA_HT40PLUS) || | ||
| 800 | (cm->mode == ATH9K_MODE_11NG_HT40PLUS)) { | ||
| 801 | hi_adj = -20; | ||
| 802 | } | ||
| 803 | |||
| 804 | if ((cm->mode == ATH9K_MODE_11NA_HT40MINUS) || | ||
| 805 | (cm->mode == ATH9K_MODE_11NG_HT40MINUS)) { | ||
| 806 | low_adj = 20; | ||
| 807 | } | ||
| 808 | |||
| 809 | /* XXX: Add a helper here instead */ | ||
| 810 | for (b = 0; b < 64 * BMLEN; b++) { | ||
| 811 | if (ath9k_regd_is_bit_set(b, channelBM)) { | ||
| 812 | fband = &freqs[b]; | ||
| 813 | if (rd5GHz.regDmnEnum == MKK1 | ||
| 814 | || rd5GHz.regDmnEnum == MKK2) { | ||
| 815 | if (ath9k_regd_japan_check(ah, | ||
| 816 | b, | ||
| 817 | &rd5GHz)) | ||
| 818 | continue; | ||
| 819 | } | ||
| 820 | |||
| 821 | ath9k_regd_add_reg_classid(regclassids, | ||
| 822 | maxregids, | ||
| 823 | nregids, | ||
| 824 | fband-> | ||
| 825 | regClassId); | ||
| 826 | |||
| 827 | if (IS_HT40_MODE(cm->mode) && (rd == &rd5GHz)) { | ||
| 828 | chanSep = 40; | ||
| 829 | if (fband->lowChannel == 5280) | ||
| 830 | low_adj += 20; | ||
| 831 | |||
| 832 | if (fband->lowChannel == 5170) | ||
| 833 | continue; | ||
| 834 | } else | ||
| 835 | chanSep = fband->channelSep; | ||
| 836 | |||
| 837 | for (c = fband->lowChannel + low_adj; | ||
| 838 | ((c <= (fband->highChannel + hi_adj)) && | ||
| 839 | (c >= (fband->lowChannel + low_adj))); | ||
| 840 | c += chanSep) { | ||
| 841 | if (next >= maxchans) { | ||
| 842 | DPRINTF(ah->ah_sc, | ||
| 843 | ATH_DBG_REGULATORY, | ||
| 844 | "%s: too many channels " | ||
| 845 | "for channel table\n", | ||
| 846 | __func__); | ||
| 847 | goto done; | ||
| 848 | } | ||
| 849 | if (ath9k_regd_add_channel(ah, | ||
| 850 | c, c_lo, c_hi, | ||
| 851 | maxChan, ctl, | ||
| 852 | next, | ||
| 853 | rd5GHz, | ||
| 854 | fband, rd, cm, | ||
| 855 | ichans, | ||
| 856 | enableExtendedChannels)) | ||
| 857 | next++; | ||
| 858 | } | ||
| 859 | if (IS_HT40_MODE(cm->mode) && | ||
| 860 | (fband->lowChannel == 5280)) { | ||
| 861 | low_adj -= 20; | ||
| 862 | } | ||
| 863 | } | ||
| 864 | } | ||
| 865 | } | ||
| 866 | done: | ||
| 867 | if (next != 0) { | ||
| 868 | int i; | ||
| 869 | |||
| 870 | if (next > ARRAY_SIZE(ah->ah_channels)) { | ||
| 871 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 872 | "%s: too many channels %u; truncating to %u\n", | ||
| 873 | __func__, next, | ||
| 874 | (int) ARRAY_SIZE(ah->ah_channels)); | ||
| 875 | next = ARRAY_SIZE(ah->ah_channels); | ||
| 876 | } | ||
| 877 | #ifdef ATH_NF_PER_CHAN | ||
| 878 | ath9k_regd_init_rf_buffer(ichans, next); | ||
| 879 | #endif | ||
| 880 | ath9k_regd_sort(ichans, next, | ||
| 881 | sizeof(struct ath9k_channel), | ||
| 882 | ath9k_regd_chansort); | ||
| 883 | |||
| 884 | ah->ah_nchan = next; | ||
| 885 | |||
| 886 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Channel list:\n"); | ||
| 887 | for (i = 0; i < next; i++) { | ||
| 888 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 889 | "chan: %d flags: 0x%x\n", | ||
| 890 | ah->ah_channels[i].channel, | ||
| 891 | ah->ah_channels[i].channelFlags); | ||
| 892 | } | ||
| 893 | } | ||
| 894 | *nchans = next; | ||
| 895 | |||
| 896 | ah->ah_countryCode = ah->ah_countryCode; | ||
| 897 | |||
| 898 | ah->ah_currentRDInUse = regdmn; | ||
| 899 | ah->ah_currentRD5G = rd5GHz.regDmnEnum; | ||
| 900 | ah->ah_currentRD2G = rd2GHz.regDmnEnum; | ||
| 901 | if (country == NULL) { | ||
| 902 | ah->ah_iso[0] = 0; | ||
| 903 | ah->ah_iso[1] = 0; | ||
| 904 | } else { | ||
| 905 | ah->ah_iso[0] = country->isoName[0]; | ||
| 906 | ah->ah_iso[1] = country->isoName[1]; | ||
| 907 | } | ||
| 908 | |||
| 909 | return next != 0; | ||
| 910 | } | ||
| 911 | |||
| 912 | struct ath9k_channel* | ||
| 913 | ath9k_regd_check_channel(struct ath_hal *ah, | ||
| 914 | const struct ath9k_channel *c) | ||
| 915 | { | ||
| 916 | struct ath9k_channel *base, *cc; | ||
| 917 | |||
| 918 | int flags = c->channelFlags & CHAN_FLAGS; | ||
| 919 | int n, lim; | ||
| 920 | |||
| 921 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 922 | "%s: channel %u/0x%x (0x%x) requested\n", __func__, | ||
| 923 | c->channel, c->channelFlags, flags); | ||
| 924 | |||
| 925 | cc = ah->ah_curchan; | ||
| 926 | if (cc != NULL && cc->channel == c->channel && | ||
| 927 | (cc->channelFlags & CHAN_FLAGS) == flags) { | ||
| 928 | if ((cc->privFlags & CHANNEL_INTERFERENCE) && | ||
| 929 | (cc->privFlags & CHANNEL_DFS)) | ||
| 930 | return NULL; | ||
| 931 | else | ||
| 932 | return cc; | ||
| 933 | } | ||
| 934 | |||
| 935 | base = ah->ah_channels; | ||
| 936 | n = ah->ah_nchan; | ||
| 937 | |||
| 938 | for (lim = n; lim != 0; lim >>= 1) { | ||
| 939 | int d; | ||
| 940 | cc = &base[lim >> 1]; | ||
| 941 | d = c->channel - cc->channel; | ||
| 942 | if (d == 0) { | ||
| 943 | if ((cc->channelFlags & CHAN_FLAGS) == flags) { | ||
| 944 | if ((cc->privFlags & CHANNEL_INTERFERENCE) && | ||
| 945 | (cc->privFlags & CHANNEL_DFS)) | ||
| 946 | return NULL; | ||
| 947 | else | ||
| 948 | return cc; | ||
| 949 | } | ||
| 950 | d = flags - (cc->channelFlags & CHAN_FLAGS); | ||
| 951 | } | ||
| 952 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, | ||
| 953 | "%s: channel %u/0x%x d %d\n", __func__, | ||
| 954 | cc->channel, cc->channelFlags, d); | ||
| 955 | if (d > 0) { | ||
| 956 | base = cc + 1; | ||
| 957 | lim--; | ||
| 958 | } | ||
| 959 | } | ||
| 960 | DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: no match for %u/0x%x\n", | ||
| 961 | __func__, c->channel, c->channelFlags); | ||
| 962 | return NULL; | ||
| 963 | } | ||
| 964 | |||
| 965 | u32 | ||
| 966 | ath9k_regd_get_antenna_allowed(struct ath_hal *ah, | ||
| 967 | struct ath9k_channel *chan) | ||
| 968 | { | ||
| 969 | struct ath9k_channel *ichan = NULL; | ||
| 970 | |||
| 971 | ichan = ath9k_regd_check_channel(ah, chan); | ||
| 972 | if (!ichan) | ||
| 973 | return 0; | ||
| 974 | |||
| 975 | return ichan->antennaMax; | ||
| 976 | } | ||
| 977 | |||
| 978 | u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) | ||
| 979 | { | ||
| 980 | u32 ctl = NO_CTL; | ||
| 981 | struct ath9k_channel *ichan; | ||
| 982 | |||
| 983 | if (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) { | ||
| 984 | if (IS_CHAN_B(chan)) | ||
| 985 | ctl = SD_NO_CTL | CTL_11B; | ||
| 986 | else if (IS_CHAN_G(chan)) | ||
| 987 | ctl = SD_NO_CTL | CTL_11G; | ||
| 988 | else | ||
| 989 | ctl = SD_NO_CTL | CTL_11A; | ||
| 990 | } else { | ||
| 991 | ichan = ath9k_regd_check_channel(ah, chan); | ||
| 992 | if (ichan != NULL) { | ||
| 993 | /* FIXME */ | ||
| 994 | if (IS_CHAN_A(ichan)) | ||
| 995 | ctl = ichan->conformanceTestLimit[0]; | ||
| 996 | else if (IS_CHAN_B(ichan)) | ||
| 997 | ctl = ichan->conformanceTestLimit[1]; | ||
| 998 | else if (IS_CHAN_G(ichan)) | ||
| 999 | ctl = ichan->conformanceTestLimit[2]; | ||
| 1000 | |||
| 1001 | if (IS_CHAN_G(chan) && (ctl & 0xf) == CTL_11B) | ||
| 1002 | ctl = (ctl & ~0xf) | CTL_11G; | ||
| 1003 | } | ||
| 1004 | } | ||
| 1005 | return ctl; | ||
| 1006 | } | ||
| 1007 | |||
| 1008 | void ath9k_regd_get_current_country(struct ath_hal *ah, | ||
| 1009 | struct ath9k_country_entry *ctry) | ||
| 1010 | { | ||
| 1011 | u16 rd = ath9k_regd_get_eepromRD(ah); | ||
| 1012 | |||
| 1013 | ctry->isMultidomain = false; | ||
| 1014 | if (rd == CTRY_DEFAULT) | ||
| 1015 | ctry->isMultidomain = true; | ||
| 1016 | else if (!(rd & COUNTRY_ERD_FLAG)) | ||
| 1017 | ctry->isMultidomain = isWwrSKU(ah); | ||
| 1018 | |||
| 1019 | ctry->countryCode = ah->ah_countryCode; | ||
| 1020 | ctry->regDmnEnum = ah->ah_currentRD; | ||
| 1021 | ctry->regDmn5G = ah->ah_currentRD5G; | ||
| 1022 | ctry->regDmn2G = ah->ah_currentRD2G; | ||
| 1023 | ctry->iso[0] = ah->ah_iso[0]; | ||
| 1024 | ctry->iso[1] = ah->ah_iso[1]; | ||
| 1025 | ctry->iso[2] = ah->ah_iso[2]; | ||
| 1026 | } | ||
diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h new file mode 100644 index 000000000000..0ecd344fbd98 --- /dev/null +++ b/drivers/net/wireless/ath9k/regd.h | |||
| @@ -0,0 +1,412 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REGD_H | ||
| 18 | #define REGD_H | ||
| 19 | |||
| 20 | #include "ath9k.h" | ||
| 21 | |||
| 22 | #define BMLEN 2 | ||
| 23 | #define BMZERO {(u64) 0, (u64) 0} | ||
| 24 | |||
| 25 | #define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \ | ||
| 26 | {((((_fa >= 0) && (_fa < 64)) ? \ | ||
| 27 | (((u64) 1) << _fa) : (u64) 0) | \ | ||
| 28 | (((_fb >= 0) && (_fb < 64)) ? \ | ||
| 29 | (((u64) 1) << _fb) : (u64) 0) | \ | ||
| 30 | (((_fc >= 0) && (_fc < 64)) ? \ | ||
| 31 | (((u64) 1) << _fc) : (u64) 0) | \ | ||
| 32 | (((_fd >= 0) && (_fd < 64)) ? \ | ||
| 33 | (((u64) 1) << _fd) : (u64) 0) | \ | ||
| 34 | (((_fe >= 0) && (_fe < 64)) ? \ | ||
| 35 | (((u64) 1) << _fe) : (u64) 0) | \ | ||
| 36 | (((_ff >= 0) && (_ff < 64)) ? \ | ||
| 37 | (((u64) 1) << _ff) : (u64) 0) | \ | ||
| 38 | (((_fg >= 0) && (_fg < 64)) ? \ | ||
| 39 | (((u64) 1) << _fg) : (u64) 0) | \ | ||
| 40 | (((_fh >= 0) && (_fh < 64)) ? \ | ||
| 41 | (((u64) 1) << _fh) : (u64) 0) | \ | ||
| 42 | (((_fi >= 0) && (_fi < 64)) ? \ | ||
| 43 | (((u64) 1) << _fi) : (u64) 0) | \ | ||
| 44 | (((_fj >= 0) && (_fj < 64)) ? \ | ||
| 45 | (((u64) 1) << _fj) : (u64) 0) | \ | ||
| 46 | (((_fk >= 0) && (_fk < 64)) ? \ | ||
| 47 | (((u64) 1) << _fk) : (u64) 0) | \ | ||
| 48 | (((_fl >= 0) && (_fl < 64)) ? \ | ||
| 49 | (((u64) 1) << _fl) : (u64) 0) | \ | ||
| 50 | ((((_fa > 63) && (_fa < 128)) ? \ | ||
| 51 | (((u64) 1) << (_fa - 64)) : (u64) 0) | \ | ||
| 52 | (((_fb > 63) && (_fb < 128)) ? \ | ||
| 53 | (((u64) 1) << (_fb - 64)) : (u64) 0) | \ | ||
| 54 | (((_fc > 63) && (_fc < 128)) ? \ | ||
| 55 | (((u64) 1) << (_fc - 64)) : (u64) 0) | \ | ||
| 56 | (((_fd > 63) && (_fd < 128)) ? \ | ||
| 57 | (((u64) 1) << (_fd - 64)) : (u64) 0) | \ | ||
| 58 | (((_fe > 63) && (_fe < 128)) ? \ | ||
| 59 | (((u64) 1) << (_fe - 64)) : (u64) 0) | \ | ||
| 60 | (((_ff > 63) && (_ff < 128)) ? \ | ||
| 61 | (((u64) 1) << (_ff - 64)) : (u64) 0) | \ | ||
| 62 | (((_fg > 63) && (_fg < 128)) ? \ | ||
| 63 | (((u64) 1) << (_fg - 64)) : (u64) 0) | \ | ||
| 64 | (((_fh > 63) && (_fh < 128)) ? \ | ||
| 65 | (((u64) 1) << (_fh - 64)) : (u64) 0) | \ | ||
| 66 | (((_fi > 63) && (_fi < 128)) ? \ | ||
| 67 | (((u64) 1) << (_fi - 64)) : (u64) 0) | \ | ||
| 68 | (((_fj > 63) && (_fj < 128)) ? \ | ||
| 69 | (((u64) 1) << (_fj - 64)) : (u64) 0) | \ | ||
| 70 | (((_fk > 63) && (_fk < 128)) ? \ | ||
| 71 | (((u64) 1) << (_fk - 64)) : (u64) 0) | \ | ||
| 72 | (((_fl > 63) && (_fl < 128)) ? \ | ||
| 73 | (((u64) 1) << (_fl - 64)) : (u64) 0)))} | ||
| 74 | |||
| 75 | #define DEF_REGDMN FCC1_FCCA | ||
| 76 | #define DEF_DMN_5 FCC1 | ||
| 77 | #define DEF_DMN_2 FCCA | ||
| 78 | #define COUNTRY_ERD_FLAG 0x8000 | ||
| 79 | #define WORLDWIDE_ROAMING_FLAG 0x4000 | ||
| 80 | #define SUPER_DOMAIN_MASK 0x0fff | ||
| 81 | #define COUNTRY_CODE_MASK 0x3fff | ||
| 82 | #define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT) | ||
| 83 | #define CHANNEL_14 (2484) | ||
| 84 | #define IS_11G_CH14(_ch,_cf) \ | ||
| 85 | (((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G)) | ||
| 86 | |||
| 87 | #define NO_PSCAN 0x0ULL | ||
| 88 | #define PSCAN_FCC 0x0000000000000001ULL | ||
| 89 | #define PSCAN_FCC_T 0x0000000000000002ULL | ||
| 90 | #define PSCAN_ETSI 0x0000000000000004ULL | ||
| 91 | #define PSCAN_MKK1 0x0000000000000008ULL | ||
| 92 | #define PSCAN_MKK2 0x0000000000000010ULL | ||
| 93 | #define PSCAN_MKKA 0x0000000000000020ULL | ||
| 94 | #define PSCAN_MKKA_G 0x0000000000000040ULL | ||
| 95 | #define PSCAN_ETSIA 0x0000000000000080ULL | ||
| 96 | #define PSCAN_ETSIB 0x0000000000000100ULL | ||
| 97 | #define PSCAN_ETSIC 0x0000000000000200ULL | ||
| 98 | #define PSCAN_WWR 0x0000000000000400ULL | ||
| 99 | #define PSCAN_MKKA1 0x0000000000000800ULL | ||
| 100 | #define PSCAN_MKKA1_G 0x0000000000001000ULL | ||
| 101 | #define PSCAN_MKKA2 0x0000000000002000ULL | ||
| 102 | #define PSCAN_MKKA2_G 0x0000000000004000ULL | ||
| 103 | #define PSCAN_MKK3 0x0000000000008000ULL | ||
| 104 | #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL | ||
| 105 | #define IS_ECM_CHAN 0x8000000000000000ULL | ||
| 106 | |||
| 107 | #define isWwrSKU(_ah) \ | ||
| 108 | (((ath9k_regd_get_eepromRD((_ah)) & WORLD_SKU_MASK) == \ | ||
| 109 | WORLD_SKU_PREFIX) || \ | ||
| 110 | (ath9k_regd_get_eepromRD(_ah) == WORLD)) | ||
| 111 | |||
| 112 | #define isWwrSKU_NoMidband(_ah) \ | ||
| 113 | ((ath9k_regd_get_eepromRD((_ah)) == WOR3_WORLD) || \ | ||
| 114 | (ath9k_regd_get_eepromRD(_ah) == WOR4_WORLD) || \ | ||
| 115 | (ath9k_regd_get_eepromRD(_ah) == WOR5_ETSIC)) | ||
| 116 | |||
| 117 | #define isUNII1OddChan(ch) \ | ||
| 118 | ((ch == 5170) || (ch == 5190) || (ch == 5210) || (ch == 5230)) | ||
| 119 | |||
| 120 | #define IS_HT40_MODE(_mode) \ | ||
| 121 | (((_mode == ATH9K_MODE_11NA_HT40PLUS || \ | ||
| 122 | _mode == ATH9K_MODE_11NG_HT40PLUS || \ | ||
| 123 | _mode == ATH9K_MODE_11NA_HT40MINUS || \ | ||
| 124 | _mode == ATH9K_MODE_11NG_HT40MINUS) ? true : false)) | ||
| 125 | |||
| 126 | #define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) | ||
| 127 | |||
| 128 | #define swap(_a, _b, _size) { \ | ||
| 129 | u8 *s = _b; \ | ||
| 130 | int i = _size; \ | ||
| 131 | do { \ | ||
| 132 | u8 tmp = *_a; \ | ||
| 133 | *_a++ = *s; \ | ||
| 134 | *s++ = tmp; \ | ||
| 135 | } while (--i); \ | ||
| 136 | _a -= _size; \ | ||
| 137 | } | ||
| 138 | |||
| 139 | |||
| 140 | #define HALF_MAXCHANBW 10 | ||
| 141 | |||
| 142 | #define MULTI_DOMAIN_MASK 0xFF00 | ||
| 143 | |||
| 144 | #define WORLD_SKU_MASK 0x00F0 | ||
| 145 | #define WORLD_SKU_PREFIX 0x0060 | ||
| 146 | |||
| 147 | #define CHANNEL_HALF_BW 10 | ||
| 148 | #define CHANNEL_QUARTER_BW 5 | ||
| 149 | |||
| 150 | typedef int ath_hal_cmp_t(const void *, const void *); | ||
| 151 | |||
| 152 | struct reg_dmn_pair_mapping { | ||
| 153 | u16 regDmnEnum; | ||
| 154 | u16 regDmn5GHz; | ||
| 155 | u16 regDmn2GHz; | ||
| 156 | u32 flags5GHz; | ||
| 157 | u32 flags2GHz; | ||
| 158 | u64 pscanMask; | ||
| 159 | u16 singleCC; | ||
| 160 | }; | ||
| 161 | |||
| 162 | struct ccmap { | ||
| 163 | char isoName[3]; | ||
| 164 | u16 countryCode; | ||
| 165 | }; | ||
| 166 | |||
| 167 | struct country_code_to_enum_rd { | ||
| 168 | u16 countryCode; | ||
| 169 | u16 regDmnEnum; | ||
| 170 | const char *isoName; | ||
| 171 | const char *name; | ||
| 172 | bool allow11g; | ||
| 173 | bool allow11aTurbo; | ||
| 174 | bool allow11gTurbo; | ||
| 175 | bool allow11ng20; | ||
| 176 | bool allow11ng40; | ||
| 177 | bool allow11na20; | ||
| 178 | bool allow11na40; | ||
| 179 | u16 outdoorChanStart; | ||
| 180 | }; | ||
| 181 | |||
| 182 | struct RegDmnFreqBand { | ||
| 183 | u16 lowChannel; | ||
| 184 | u16 highChannel; | ||
| 185 | u8 powerDfs; | ||
| 186 | u8 antennaMax; | ||
| 187 | u8 channelBW; | ||
| 188 | u8 channelSep; | ||
| 189 | u64 useDfs; | ||
| 190 | u64 usePassScan; | ||
| 191 | u8 regClassId; | ||
| 192 | }; | ||
| 193 | |||
| 194 | struct regDomain { | ||
| 195 | u16 regDmnEnum; | ||
| 196 | u8 conformanceTestLimit; | ||
| 197 | u64 dfsMask; | ||
| 198 | u64 pscan; | ||
| 199 | u32 flags; | ||
| 200 | u64 chan11a[BMLEN]; | ||
| 201 | u64 chan11a_turbo[BMLEN]; | ||
| 202 | u64 chan11a_dyn_turbo[BMLEN]; | ||
| 203 | u64 chan11b[BMLEN]; | ||
| 204 | u64 chan11g[BMLEN]; | ||
| 205 | u64 chan11g_turbo[BMLEN]; | ||
| 206 | }; | ||
| 207 | |||
| 208 | struct cmode { | ||
| 209 | u32 mode; | ||
| 210 | u32 flags; | ||
| 211 | }; | ||
| 212 | |||
| 213 | #define YES true | ||
| 214 | #define NO false | ||
| 215 | |||
| 216 | struct japan_bandcheck { | ||
| 217 | u16 freqbandbit; | ||
| 218 | u32 eepromflagtocheck; | ||
| 219 | }; | ||
| 220 | |||
| 221 | struct common_mode_power { | ||
| 222 | u16 lchan; | ||
| 223 | u16 hchan; | ||
| 224 | u8 pwrlvl; | ||
| 225 | }; | ||
| 226 | |||
| 227 | enum CountryCode { | ||
| 228 | CTRY_ALBANIA = 8, | ||
| 229 | CTRY_ALGERIA = 12, | ||
| 230 | CTRY_ARGENTINA = 32, | ||
| 231 | CTRY_ARMENIA = 51, | ||
| 232 | CTRY_AUSTRALIA = 36, | ||
| 233 | CTRY_AUSTRIA = 40, | ||
| 234 | CTRY_AZERBAIJAN = 31, | ||
| 235 | CTRY_BAHRAIN = 48, | ||
| 236 | CTRY_BELARUS = 112, | ||
| 237 | CTRY_BELGIUM = 56, | ||
| 238 | CTRY_BELIZE = 84, | ||
| 239 | CTRY_BOLIVIA = 68, | ||
| 240 | CTRY_BOSNIA_HERZ = 70, | ||
| 241 | CTRY_BRAZIL = 76, | ||
| 242 | CTRY_BRUNEI_DARUSSALAM = 96, | ||
| 243 | CTRY_BULGARIA = 100, | ||
| 244 | CTRY_CANADA = 124, | ||
| 245 | CTRY_CHILE = 152, | ||
| 246 | CTRY_CHINA = 156, | ||
| 247 | CTRY_COLOMBIA = 170, | ||
| 248 | CTRY_COSTA_RICA = 188, | ||
| 249 | CTRY_CROATIA = 191, | ||
| 250 | CTRY_CYPRUS = 196, | ||
| 251 | CTRY_CZECH = 203, | ||
| 252 | CTRY_DENMARK = 208, | ||
| 253 | CTRY_DOMINICAN_REPUBLIC = 214, | ||
| 254 | CTRY_ECUADOR = 218, | ||
| 255 | CTRY_EGYPT = 818, | ||
| 256 | CTRY_EL_SALVADOR = 222, | ||
| 257 | CTRY_ESTONIA = 233, | ||
| 258 | CTRY_FAEROE_ISLANDS = 234, | ||
| 259 | CTRY_FINLAND = 246, | ||
| 260 | CTRY_FRANCE = 250, | ||
| 261 | CTRY_GEORGIA = 268, | ||
| 262 | CTRY_GERMANY = 276, | ||
| 263 | CTRY_GREECE = 300, | ||
| 264 | CTRY_GUATEMALA = 320, | ||
| 265 | CTRY_HONDURAS = 340, | ||
| 266 | CTRY_HONG_KONG = 344, | ||
| 267 | CTRY_HUNGARY = 348, | ||
| 268 | CTRY_ICELAND = 352, | ||
| 269 | CTRY_INDIA = 356, | ||
| 270 | CTRY_INDONESIA = 360, | ||
| 271 | CTRY_IRAN = 364, | ||
| 272 | CTRY_IRAQ = 368, | ||
| 273 | CTRY_IRELAND = 372, | ||
| 274 | CTRY_ISRAEL = 376, | ||
| 275 | CTRY_ITALY = 380, | ||
| 276 | CTRY_JAMAICA = 388, | ||
| 277 | CTRY_JAPAN = 392, | ||
| 278 | CTRY_JORDAN = 400, | ||
| 279 | CTRY_KAZAKHSTAN = 398, | ||
| 280 | CTRY_KENYA = 404, | ||
| 281 | CTRY_KOREA_NORTH = 408, | ||
| 282 | CTRY_KOREA_ROC = 410, | ||
| 283 | CTRY_KOREA_ROC2 = 411, | ||
| 284 | CTRY_KOREA_ROC3 = 412, | ||
| 285 | CTRY_KUWAIT = 414, | ||
| 286 | CTRY_LATVIA = 428, | ||
| 287 | CTRY_LEBANON = 422, | ||
| 288 | CTRY_LIBYA = 434, | ||
| 289 | CTRY_LIECHTENSTEIN = 438, | ||
| 290 | CTRY_LITHUANIA = 440, | ||
| 291 | CTRY_LUXEMBOURG = 442, | ||
| 292 | CTRY_MACAU = 446, | ||
| 293 | CTRY_MACEDONIA = 807, | ||
| 294 | CTRY_MALAYSIA = 458, | ||
| 295 | CTRY_MALTA = 470, | ||
| 296 | CTRY_MEXICO = 484, | ||
| 297 | CTRY_MONACO = 492, | ||
| 298 | CTRY_MOROCCO = 504, | ||
| 299 | CTRY_NEPAL = 524, | ||
| 300 | CTRY_NETHERLANDS = 528, | ||
| 301 | CTRY_NETHERLANDS_ANTILLES = 530, | ||
| 302 | CTRY_NEW_ZEALAND = 554, | ||
| 303 | CTRY_NICARAGUA = 558, | ||
| 304 | CTRY_NORWAY = 578, | ||
| 305 | CTRY_OMAN = 512, | ||
| 306 | CTRY_PAKISTAN = 586, | ||
| 307 | CTRY_PANAMA = 591, | ||
| 308 | CTRY_PAPUA_NEW_GUINEA = 598, | ||
| 309 | CTRY_PARAGUAY = 600, | ||
| 310 | CTRY_PERU = 604, | ||
| 311 | CTRY_PHILIPPINES = 608, | ||
| 312 | CTRY_POLAND = 616, | ||
| 313 | CTRY_PORTUGAL = 620, | ||
| 314 | CTRY_PUERTO_RICO = 630, | ||
| 315 | CTRY_QATAR = 634, | ||
| 316 | CTRY_ROMANIA = 642, | ||
| 317 | CTRY_RUSSIA = 643, | ||
| 318 | CTRY_SAUDI_ARABIA = 682, | ||
| 319 | CTRY_SERBIA_MONTENEGRO = 891, | ||
| 320 | CTRY_SINGAPORE = 702, | ||
| 321 | CTRY_SLOVAKIA = 703, | ||
| 322 | CTRY_SLOVENIA = 705, | ||
| 323 | CTRY_SOUTH_AFRICA = 710, | ||
| 324 | CTRY_SPAIN = 724, | ||
| 325 | CTRY_SRI_LANKA = 144, | ||
| 326 | CTRY_SWEDEN = 752, | ||
| 327 | CTRY_SWITZERLAND = 756, | ||
| 328 | CTRY_SYRIA = 760, | ||
| 329 | CTRY_TAIWAN = 158, | ||
| 330 | CTRY_THAILAND = 764, | ||
| 331 | CTRY_TRINIDAD_Y_TOBAGO = 780, | ||
| 332 | CTRY_TUNISIA = 788, | ||
| 333 | CTRY_TURKEY = 792, | ||
| 334 | CTRY_UAE = 784, | ||
| 335 | CTRY_UKRAINE = 804, | ||
| 336 | CTRY_UNITED_KINGDOM = 826, | ||
| 337 | CTRY_UNITED_STATES = 840, | ||
| 338 | CTRY_UNITED_STATES_FCC49 = 842, | ||
| 339 | CTRY_URUGUAY = 858, | ||
| 340 | CTRY_UZBEKISTAN = 860, | ||
| 341 | CTRY_VENEZUELA = 862, | ||
| 342 | CTRY_VIET_NAM = 704, | ||
| 343 | CTRY_YEMEN = 887, | ||
| 344 | CTRY_ZIMBABWE = 716, | ||
| 345 | CTRY_JAPAN1 = 393, | ||
| 346 | CTRY_JAPAN2 = 394, | ||
| 347 | CTRY_JAPAN3 = 395, | ||
| 348 | CTRY_JAPAN4 = 396, | ||
| 349 | CTRY_JAPAN5 = 397, | ||
| 350 | CTRY_JAPAN6 = 4006, | ||
| 351 | CTRY_JAPAN7 = 4007, | ||
| 352 | CTRY_JAPAN8 = 4008, | ||
| 353 | CTRY_JAPAN9 = 4009, | ||
| 354 | CTRY_JAPAN10 = 4010, | ||
| 355 | CTRY_JAPAN11 = 4011, | ||
| 356 | CTRY_JAPAN12 = 4012, | ||
| 357 | CTRY_JAPAN13 = 4013, | ||
| 358 | CTRY_JAPAN14 = 4014, | ||
| 359 | CTRY_JAPAN15 = 4015, | ||
| 360 | CTRY_JAPAN16 = 4016, | ||
| 361 | CTRY_JAPAN17 = 4017, | ||
| 362 | CTRY_JAPAN18 = 4018, | ||
| 363 | CTRY_JAPAN19 = 4019, | ||
| 364 | CTRY_JAPAN20 = 4020, | ||
| 365 | CTRY_JAPAN21 = 4021, | ||
| 366 | CTRY_JAPAN22 = 4022, | ||
| 367 | CTRY_JAPAN23 = 4023, | ||
| 368 | CTRY_JAPAN24 = 4024, | ||
| 369 | CTRY_JAPAN25 = 4025, | ||
| 370 | CTRY_JAPAN26 = 4026, | ||
| 371 | CTRY_JAPAN27 = 4027, | ||
| 372 | CTRY_JAPAN28 = 4028, | ||
| 373 | CTRY_JAPAN29 = 4029, | ||
| 374 | CTRY_JAPAN30 = 4030, | ||
| 375 | CTRY_JAPAN31 = 4031, | ||
| 376 | CTRY_JAPAN32 = 4032, | ||
| 377 | CTRY_JAPAN33 = 4033, | ||
| 378 | CTRY_JAPAN34 = 4034, | ||
| 379 | CTRY_JAPAN35 = 4035, | ||
| 380 | CTRY_JAPAN36 = 4036, | ||
| 381 | CTRY_JAPAN37 = 4037, | ||
| 382 | CTRY_JAPAN38 = 4038, | ||
| 383 | CTRY_JAPAN39 = 4039, | ||
| 384 | CTRY_JAPAN40 = 4040, | ||
| 385 | CTRY_JAPAN41 = 4041, | ||
| 386 | CTRY_JAPAN42 = 4042, | ||
| 387 | CTRY_JAPAN43 = 4043, | ||
| 388 | CTRY_JAPAN44 = 4044, | ||
| 389 | CTRY_JAPAN45 = 4045, | ||
| 390 | CTRY_JAPAN46 = 4046, | ||
| 391 | CTRY_JAPAN47 = 4047, | ||
| 392 | CTRY_JAPAN48 = 4048, | ||
| 393 | CTRY_JAPAN49 = 4049, | ||
| 394 | CTRY_JAPAN50 = 4050, | ||
| 395 | CTRY_JAPAN51 = 4051, | ||
| 396 | CTRY_JAPAN52 = 4052, | ||
| 397 | CTRY_JAPAN53 = 4053, | ||
| 398 | CTRY_JAPAN54 = 4054, | ||
| 399 | CTRY_JAPAN55 = 4055, | ||
| 400 | CTRY_JAPAN56 = 4056, | ||
| 401 | CTRY_JAPAN57 = 4057, | ||
| 402 | CTRY_JAPAN58 = 4058, | ||
| 403 | CTRY_JAPAN59 = 4059, | ||
| 404 | CTRY_AUSTRALIA2 = 5000, | ||
| 405 | CTRY_CANADA2 = 5001, | ||
| 406 | CTRY_BELGIUM2 = 5002 | ||
| 407 | }; | ||
| 408 | |||
| 409 | void ath9k_regd_get_current_country(struct ath_hal *ah, | ||
| 410 | struct ath9k_country_entry *ctry); | ||
| 411 | |||
| 412 | #endif | ||
diff --git a/drivers/net/wireless/ath9k/regd_common.h b/drivers/net/wireless/ath9k/regd_common.h new file mode 100644 index 000000000000..9112c030b1e8 --- /dev/null +++ b/drivers/net/wireless/ath9k/regd_common.h | |||
| @@ -0,0 +1,1915 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REGD_COMMON_H | ||
| 18 | #define REGD_COMMON_H | ||
| 19 | |||
| 20 | enum EnumRd { | ||
| 21 | NO_ENUMRD = 0x00, | ||
| 22 | NULL1_WORLD = 0x03, | ||
| 23 | NULL1_ETSIB = 0x07, | ||
| 24 | NULL1_ETSIC = 0x08, | ||
| 25 | FCC1_FCCA = 0x10, | ||
| 26 | FCC1_WORLD = 0x11, | ||
| 27 | FCC4_FCCA = 0x12, | ||
| 28 | FCC5_FCCA = 0x13, | ||
| 29 | FCC6_FCCA = 0x14, | ||
| 30 | |||
| 31 | FCC2_FCCA = 0x20, | ||
| 32 | FCC2_WORLD = 0x21, | ||
| 33 | FCC2_ETSIC = 0x22, | ||
| 34 | FCC6_WORLD = 0x23, | ||
| 35 | FRANCE_RES = 0x31, | ||
| 36 | FCC3_FCCA = 0x3A, | ||
| 37 | FCC3_WORLD = 0x3B, | ||
| 38 | |||
| 39 | ETSI1_WORLD = 0x37, | ||
| 40 | ETSI3_ETSIA = 0x32, | ||
| 41 | ETSI2_WORLD = 0x35, | ||
| 42 | ETSI3_WORLD = 0x36, | ||
| 43 | ETSI4_WORLD = 0x30, | ||
| 44 | ETSI4_ETSIC = 0x38, | ||
| 45 | ETSI5_WORLD = 0x39, | ||
| 46 | ETSI6_WORLD = 0x34, | ||
| 47 | ETSI_RESERVED = 0x33, | ||
| 48 | |||
| 49 | MKK1_MKKA = 0x40, | ||
| 50 | MKK1_MKKB = 0x41, | ||
| 51 | APL4_WORLD = 0x42, | ||
| 52 | MKK2_MKKA = 0x43, | ||
| 53 | APL_RESERVED = 0x44, | ||
| 54 | APL2_WORLD = 0x45, | ||
| 55 | APL2_APLC = 0x46, | ||
| 56 | APL3_WORLD = 0x47, | ||
| 57 | MKK1_FCCA = 0x48, | ||
| 58 | APL2_APLD = 0x49, | ||
| 59 | MKK1_MKKA1 = 0x4A, | ||
| 60 | MKK1_MKKA2 = 0x4B, | ||
| 61 | MKK1_MKKC = 0x4C, | ||
| 62 | |||
| 63 | APL3_FCCA = 0x50, | ||
| 64 | APL1_WORLD = 0x52, | ||
| 65 | APL1_FCCA = 0x53, | ||
| 66 | APL1_APLA = 0x54, | ||
| 67 | APL1_ETSIC = 0x55, | ||
| 68 | APL2_ETSIC = 0x56, | ||
| 69 | APL5_WORLD = 0x58, | ||
| 70 | APL6_WORLD = 0x5B, | ||
| 71 | APL7_FCCA = 0x5C, | ||
| 72 | APL8_WORLD = 0x5D, | ||
| 73 | APL9_WORLD = 0x5E, | ||
| 74 | |||
| 75 | WOR0_WORLD = 0x60, | ||
| 76 | WOR1_WORLD = 0x61, | ||
| 77 | WOR2_WORLD = 0x62, | ||
| 78 | WOR3_WORLD = 0x63, | ||
| 79 | WOR4_WORLD = 0x64, | ||
| 80 | WOR5_ETSIC = 0x65, | ||
| 81 | |||
| 82 | WOR01_WORLD = 0x66, | ||
| 83 | WOR02_WORLD = 0x67, | ||
| 84 | EU1_WORLD = 0x68, | ||
| 85 | |||
| 86 | WOR9_WORLD = 0x69, | ||
| 87 | WORA_WORLD = 0x6A, | ||
| 88 | WORB_WORLD = 0x6B, | ||
| 89 | |||
| 90 | MKK3_MKKB = 0x80, | ||
| 91 | MKK3_MKKA2 = 0x81, | ||
| 92 | MKK3_MKKC = 0x82, | ||
| 93 | |||
| 94 | MKK4_MKKB = 0x83, | ||
| 95 | MKK4_MKKA2 = 0x84, | ||
| 96 | MKK4_MKKC = 0x85, | ||
| 97 | |||
| 98 | MKK5_MKKB = 0x86, | ||
| 99 | MKK5_MKKA2 = 0x87, | ||
| 100 | MKK5_MKKC = 0x88, | ||
| 101 | |||
| 102 | MKK6_MKKB = 0x89, | ||
| 103 | MKK6_MKKA2 = 0x8A, | ||
| 104 | MKK6_MKKC = 0x8B, | ||
| 105 | |||
| 106 | MKK7_MKKB = 0x8C, | ||
| 107 | MKK7_MKKA2 = 0x8D, | ||
| 108 | MKK7_MKKC = 0x8E, | ||
| 109 | |||
| 110 | MKK8_MKKB = 0x8F, | ||
| 111 | MKK8_MKKA2 = 0x90, | ||
| 112 | MKK8_MKKC = 0x91, | ||
| 113 | |||
| 114 | MKK14_MKKA1 = 0x92, | ||
| 115 | MKK15_MKKA1 = 0x93, | ||
| 116 | |||
| 117 | MKK10_FCCA = 0xD0, | ||
| 118 | MKK10_MKKA1 = 0xD1, | ||
| 119 | MKK10_MKKC = 0xD2, | ||
| 120 | MKK10_MKKA2 = 0xD3, | ||
| 121 | |||
| 122 | MKK11_MKKA = 0xD4, | ||
| 123 | MKK11_FCCA = 0xD5, | ||
| 124 | MKK11_MKKA1 = 0xD6, | ||
| 125 | MKK11_MKKC = 0xD7, | ||
| 126 | MKK11_MKKA2 = 0xD8, | ||
| 127 | |||
| 128 | MKK12_MKKA = 0xD9, | ||
| 129 | MKK12_FCCA = 0xDA, | ||
| 130 | MKK12_MKKA1 = 0xDB, | ||
| 131 | MKK12_MKKC = 0xDC, | ||
| 132 | MKK12_MKKA2 = 0xDD, | ||
| 133 | |||
| 134 | MKK13_MKKB = 0xDE, | ||
| 135 | |||
| 136 | MKK3_MKKA = 0xF0, | ||
| 137 | MKK3_MKKA1 = 0xF1, | ||
| 138 | MKK3_FCCA = 0xF2, | ||
| 139 | MKK4_MKKA = 0xF3, | ||
| 140 | MKK4_MKKA1 = 0xF4, | ||
| 141 | MKK4_FCCA = 0xF5, | ||
| 142 | MKK9_MKKA = 0xF6, | ||
| 143 | MKK10_MKKA = 0xF7, | ||
| 144 | MKK6_MKKA1 = 0xF8, | ||
| 145 | MKK6_FCCA = 0xF9, | ||
| 146 | MKK7_MKKA1 = 0xFA, | ||
| 147 | MKK7_FCCA = 0xFB, | ||
| 148 | MKK9_FCCA = 0xFC, | ||
| 149 | MKK9_MKKA1 = 0xFD, | ||
| 150 | MKK9_MKKC = 0xFE, | ||
| 151 | MKK9_MKKA2 = 0xFF, | ||
| 152 | |||
| 153 | APL1 = 0x0150, | ||
| 154 | APL2 = 0x0250, | ||
| 155 | APL3 = 0x0350, | ||
| 156 | APL4 = 0x0450, | ||
| 157 | APL5 = 0x0550, | ||
| 158 | APL6 = 0x0650, | ||
| 159 | APL7 = 0x0750, | ||
| 160 | APL8 = 0x0850, | ||
| 161 | APL9 = 0x0950, | ||
| 162 | APL10 = 0x1050, | ||
| 163 | |||
| 164 | ETSI1 = 0x0130, | ||
| 165 | ETSI2 = 0x0230, | ||
| 166 | ETSI3 = 0x0330, | ||
| 167 | ETSI4 = 0x0430, | ||
| 168 | ETSI5 = 0x0530, | ||
| 169 | ETSI6 = 0x0630, | ||
| 170 | ETSIA = 0x0A30, | ||
| 171 | ETSIB = 0x0B30, | ||
| 172 | ETSIC = 0x0C30, | ||
| 173 | |||
| 174 | FCC1 = 0x0110, | ||
| 175 | FCC2 = 0x0120, | ||
| 176 | FCC3 = 0x0160, | ||
| 177 | FCC4 = 0x0165, | ||
| 178 | FCC5 = 0x0510, | ||
| 179 | FCC6 = 0x0610, | ||
| 180 | FCCA = 0x0A10, | ||
| 181 | |||
| 182 | APLD = 0x0D50, | ||
| 183 | |||
| 184 | MKK1 = 0x0140, | ||
| 185 | MKK2 = 0x0240, | ||
| 186 | MKK3 = 0x0340, | ||
| 187 | MKK4 = 0x0440, | ||
| 188 | MKK5 = 0x0540, | ||
| 189 | MKK6 = 0x0640, | ||
| 190 | MKK7 = 0x0740, | ||
| 191 | MKK8 = 0x0840, | ||
| 192 | MKK9 = 0x0940, | ||
| 193 | MKK10 = 0x0B40, | ||
| 194 | MKK11 = 0x1140, | ||
| 195 | MKK12 = 0x1240, | ||
| 196 | MKK13 = 0x0C40, | ||
| 197 | MKK14 = 0x1440, | ||
| 198 | MKK15 = 0x1540, | ||
| 199 | MKKA = 0x0A40, | ||
| 200 | MKKC = 0x0A50, | ||
| 201 | |||
| 202 | NULL1 = 0x0198, | ||
| 203 | WORLD = 0x0199, | ||
| 204 | DEBUG_REG_DMN = 0x01ff, | ||
| 205 | }; | ||
| 206 | |||
| 207 | enum { | ||
| 208 | FCC = 0x10, | ||
| 209 | MKK = 0x40, | ||
| 210 | ETSI = 0x30, | ||
| 211 | }; | ||
| 212 | |||
| 213 | enum { | ||
| 214 | NO_REQ = 0x00000000, | ||
| 215 | DISALLOW_ADHOC_11A = 0x00000001, | ||
| 216 | DISALLOW_ADHOC_11A_TURB = 0x00000002, | ||
| 217 | NEED_NFC = 0x00000004, | ||
| 218 | |||
| 219 | ADHOC_PER_11D = 0x00000008, | ||
| 220 | ADHOC_NO_11A = 0x00000010, | ||
| 221 | |||
| 222 | PUBLIC_SAFETY_DOMAIN = 0x00000020, | ||
| 223 | LIMIT_FRAME_4MS = 0x00000040, | ||
| 224 | |||
| 225 | NO_HOSTAP = 0x00000080, | ||
| 226 | |||
| 227 | REQ_MASK = 0x000000FF, | ||
| 228 | }; | ||
| 229 | |||
| 230 | #define REG_DOMAIN_2GHZ_MASK (REQ_MASK & \ | ||
| 231 | (!(ADHOC_NO_11A | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB))) | ||
| 232 | #define REG_DOMAIN_5GHZ_MASK REQ_MASK | ||
| 233 | |||
| 234 | static struct reg_dmn_pair_mapping regDomainPairs[] = { | ||
| 235 | {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, | ||
| 236 | PSCAN_DEFER, 0}, | ||
| 237 | {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 238 | {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 239 | {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 240 | |||
| 241 | {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 242 | {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 243 | {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 244 | {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 245 | {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 246 | {FCC4_FCCA, FCC4, FCCA, | ||
| 247 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 248 | 0}, | ||
| 249 | {FCC5_FCCA, FCC5, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 250 | {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 251 | {FCC6_WORLD, FCC6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 252 | |||
| 253 | {ETSI1_WORLD, ETSI1, WORLD, | ||
| 254 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 255 | 0}, | ||
| 256 | {ETSI2_WORLD, ETSI2, WORLD, | ||
| 257 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 258 | 0}, | ||
| 259 | {ETSI3_WORLD, ETSI3, WORLD, | ||
| 260 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 261 | 0}, | ||
| 262 | {ETSI4_WORLD, ETSI4, WORLD, | ||
| 263 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 264 | 0}, | ||
| 265 | {ETSI5_WORLD, ETSI5, WORLD, | ||
| 266 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 267 | 0}, | ||
| 268 | {ETSI6_WORLD, ETSI6, WORLD, | ||
| 269 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 270 | 0}, | ||
| 271 | |||
| 272 | {ETSI3_ETSIA, ETSI3, WORLD, | ||
| 273 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 274 | 0}, | ||
| 275 | {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 276 | |||
| 277 | {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 278 | {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 279 | {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 280 | {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 281 | {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 282 | {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 283 | {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 284 | {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 285 | {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 286 | {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 287 | |||
| 288 | {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 289 | {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 290 | {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 291 | {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER,}, | ||
| 292 | |||
| 293 | {MKK1_MKKA, MKK1, MKKA, | ||
| 294 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 295 | PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN}, | ||
| 296 | {MKK1_MKKB, MKK1, MKKA, | ||
| 297 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 298 | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 299 | CTRY_JAPAN1}, | ||
| 300 | {MKK1_FCCA, MKK1, FCCA, | ||
| 301 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 302 | PSCAN_MKK1, CTRY_JAPAN2}, | ||
| 303 | {MKK1_MKKA1, MKK1, MKKA, | ||
| 304 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 305 | PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4}, | ||
| 306 | {MKK1_MKKA2, MKK1, MKKA, | ||
| 307 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 308 | PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5}, | ||
| 309 | {MKK1_MKKC, MKK1, MKKC, | ||
| 310 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 311 | PSCAN_MKK1, CTRY_JAPAN6}, | ||
| 312 | |||
| 313 | {MKK2_MKKA, MKK2, MKKA, | ||
| 314 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 315 | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 316 | CTRY_JAPAN3}, | ||
| 317 | |||
| 318 | {MKK3_MKKA, MKK3, MKKA, | ||
| 319 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 320 | PSCAN_MKKA, CTRY_JAPAN25}, | ||
| 321 | {MKK3_MKKB, MKK3, MKKA, | ||
| 322 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 323 | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 324 | CTRY_JAPAN7}, | ||
| 325 | {MKK3_MKKA1, MKK3, MKKA, | ||
| 326 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 327 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN26}, | ||
| 328 | {MKK3_MKKA2, MKK3, MKKA, | ||
| 329 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 330 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8}, | ||
| 331 | {MKK3_MKKC, MKK3, MKKC, | ||
| 332 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 333 | NO_PSCAN, CTRY_JAPAN9}, | ||
| 334 | {MKK3_FCCA, MKK3, FCCA, | ||
| 335 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 336 | NO_PSCAN, CTRY_JAPAN27}, | ||
| 337 | |||
| 338 | {MKK4_MKKA, MKK4, MKKA, | ||
| 339 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 340 | PSCAN_MKK3, CTRY_JAPAN36}, | ||
| 341 | {MKK4_MKKB, MKK4, MKKA, | ||
| 342 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 343 | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 344 | CTRY_JAPAN10}, | ||
| 345 | {MKK4_MKKA1, MKK4, MKKA, | ||
| 346 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 347 | PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN28}, | ||
| 348 | {MKK4_MKKA2, MKK4, MKKA, | ||
| 349 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 350 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11}, | ||
| 351 | {MKK4_MKKC, MKK4, MKKC, | ||
| 352 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 353 | PSCAN_MKK3, CTRY_JAPAN12}, | ||
| 354 | {MKK4_FCCA, MKK4, FCCA, | ||
| 355 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 356 | PSCAN_MKK3, CTRY_JAPAN29}, | ||
| 357 | |||
| 358 | {MKK5_MKKB, MKK5, MKKA, | ||
| 359 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 360 | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 361 | CTRY_JAPAN13}, | ||
| 362 | {MKK5_MKKA2, MKK5, MKKA, | ||
| 363 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 364 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14}, | ||
| 365 | {MKK5_MKKC, MKK5, MKKC, | ||
| 366 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 367 | PSCAN_MKK3, CTRY_JAPAN15}, | ||
| 368 | |||
| 369 | {MKK6_MKKB, MKK6, MKKA, | ||
| 370 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 371 | PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16}, | ||
| 372 | {MKK6_MKKA1, MKK6, MKKA, | ||
| 373 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 374 | PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN30}, | ||
| 375 | {MKK6_MKKA2, MKK6, MKKA, | ||
| 376 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 377 | PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17}, | ||
| 378 | {MKK6_MKKC, MKK6, MKKC, | ||
| 379 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 380 | PSCAN_MKK1, CTRY_JAPAN18}, | ||
| 381 | {MKK6_FCCA, MKK6, FCCA, | ||
| 382 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 383 | NO_PSCAN, CTRY_JAPAN31}, | ||
| 384 | |||
| 385 | {MKK7_MKKB, MKK7, MKKA, | ||
| 386 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 387 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 388 | CTRY_JAPAN19}, | ||
| 389 | {MKK7_MKKA1, MKK7, MKKA, | ||
| 390 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 391 | PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN32}, | ||
| 392 | {MKK7_MKKA2, MKK7, MKKA, | ||
| 393 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 394 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, | ||
| 395 | CTRY_JAPAN20}, | ||
| 396 | {MKK7_MKKC, MKK7, MKKC, | ||
| 397 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 398 | PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21}, | ||
| 399 | {MKK7_FCCA, MKK7, FCCA, | ||
| 400 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 401 | PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN33}, | ||
| 402 | |||
| 403 | {MKK8_MKKB, MKK8, MKKA, | ||
| 404 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 405 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 406 | CTRY_JAPAN22}, | ||
| 407 | {MKK8_MKKA2, MKK8, MKKA, | ||
| 408 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 409 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, | ||
| 410 | CTRY_JAPAN23}, | ||
| 411 | {MKK8_MKKC, MKK8, MKKC, | ||
| 412 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 413 | PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN24}, | ||
| 414 | |||
| 415 | {MKK9_MKKA, MKK9, MKKA, | ||
| 416 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 417 | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 418 | PSCAN_MKK2 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 419 | CTRY_JAPAN34}, | ||
| 420 | {MKK9_FCCA, MKK9, FCCA, | ||
| 421 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 422 | NO_PSCAN, CTRY_JAPAN37}, | ||
| 423 | {MKK9_MKKA1, MKK9, MKKA, | ||
| 424 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 425 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN38}, | ||
| 426 | {MKK9_MKKA2, MKK9, MKKA, | ||
| 427 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 428 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN40}, | ||
| 429 | {MKK9_MKKC, MKK9, MKKC, | ||
| 430 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 431 | NO_PSCAN, CTRY_JAPAN39}, | ||
| 432 | |||
| 433 | {MKK10_MKKA, MKK10, MKKA, | ||
| 434 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 435 | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKK3, CTRY_JAPAN35}, | ||
| 436 | {MKK10_FCCA, MKK10, FCCA, | ||
| 437 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 438 | NO_PSCAN, CTRY_JAPAN41}, | ||
| 439 | {MKK10_MKKA1, MKK10, MKKA, | ||
| 440 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 441 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN42}, | ||
| 442 | {MKK10_MKKA2, MKK10, MKKA, | ||
| 443 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 444 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN44}, | ||
| 445 | {MKK10_MKKC, MKK10, MKKC, | ||
| 446 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 447 | NO_PSCAN, CTRY_JAPAN43}, | ||
| 448 | |||
| 449 | {MKK11_MKKA, MKK11, MKKA, | ||
| 450 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 451 | PSCAN_MKK3, CTRY_JAPAN45}, | ||
| 452 | {MKK11_FCCA, MKK11, FCCA, | ||
| 453 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 454 | PSCAN_MKK3, CTRY_JAPAN46}, | ||
| 455 | {MKK11_MKKA1, MKK11, MKKA, | ||
| 456 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 457 | PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN47}, | ||
| 458 | {MKK11_MKKA2, MKK11, MKKA, | ||
| 459 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 460 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN49}, | ||
| 461 | {MKK11_MKKC, MKK11, MKKC, | ||
| 462 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 463 | PSCAN_MKK3, CTRY_JAPAN48}, | ||
| 464 | |||
| 465 | {MKK12_MKKA, MKK12, MKKA, | ||
| 466 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 467 | PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN50}, | ||
| 468 | {MKK12_FCCA, MKK12, FCCA, | ||
| 469 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 470 | PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN51}, | ||
| 471 | {MKK12_MKKA1, MKK12, MKKA, | ||
| 472 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 473 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, | ||
| 474 | CTRY_JAPAN52}, | ||
| 475 | {MKK12_MKKA2, MKK12, MKKA, | ||
| 476 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 477 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, | ||
| 478 | CTRY_JAPAN54}, | ||
| 479 | {MKK12_MKKC, MKK12, MKKC, | ||
| 480 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 481 | PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN53}, | ||
| 482 | |||
| 483 | {MKK13_MKKB, MKK13, MKKA, | ||
| 484 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | | ||
| 485 | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 486 | PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, | ||
| 487 | CTRY_JAPAN57}, | ||
| 488 | |||
| 489 | {MKK14_MKKA1, MKK14, MKKA, | ||
| 490 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 491 | PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN58}, | ||
| 492 | {MKK15_MKKA1, MKK15, MKKA, | ||
| 493 | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, | ||
| 494 | PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN59}, | ||
| 495 | |||
| 496 | {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, | ||
| 497 | 0}, | ||
| 498 | {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, | ||
| 499 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 500 | 0}, | ||
| 501 | {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, | ||
| 502 | NO_REQ, PSCAN_DEFER, 0}, | ||
| 503 | {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, | ||
| 504 | 0}, | ||
| 505 | {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, | ||
| 506 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 507 | 0}, | ||
| 508 | {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, | ||
| 509 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 510 | 0}, | ||
| 511 | {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, | ||
| 512 | PSCAN_DEFER, 0}, | ||
| 513 | {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, | ||
| 514 | PSCAN_DEFER, 0}, | ||
| 515 | {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, | ||
| 516 | {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, | ||
| 517 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 518 | 0}, | ||
| 519 | {WORA_WORLD, WORA_WORLD, WORA_WORLD, | ||
| 520 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 521 | 0}, | ||
| 522 | {WORB_WORLD, WORB_WORLD, WORB_WORLD, | ||
| 523 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, | ||
| 524 | 0}, | ||
| 525 | }; | ||
| 526 | |||
| 527 | #define NO_INTERSECT_REQ 0xFFFFFFFF | ||
| 528 | #define NO_UNION_REQ 0 | ||
| 529 | |||
| 530 | static struct country_code_to_enum_rd allCountries[] = { | ||
| 531 | {CTRY_DEBUG, NO_ENUMRD, "DB", "DEBUG", YES, YES, YES, YES, YES, | ||
| 532 | YES, YES, 7000}, | ||
| 533 | {CTRY_DEFAULT, DEF_REGDMN, "NA", "NO_COUNTRY_SET", YES, YES, YES, | ||
| 534 | YES, YES, YES, YES, 7000}, | ||
| 535 | {CTRY_ALBANIA, NULL1_WORLD, "AL", "ALBANIA", YES, NO, YES, YES, NO, | ||
| 536 | NO, NO, 7000}, | ||
| 537 | {CTRY_ALGERIA, NULL1_WORLD, "DZ", "ALGERIA", YES, NO, YES, YES, NO, | ||
| 538 | NO, NO, 7000}, | ||
| 539 | {CTRY_ARGENTINA, APL3_WORLD, "AR", "ARGENTINA", YES, NO, NO, YES, | ||
| 540 | NO, YES, NO, 7000}, | ||
| 541 | {CTRY_ARMENIA, ETSI4_WORLD, "AM", "ARMENIA", YES, NO, YES, YES, | ||
| 542 | YES, NO, NO, 7000}, | ||
| 543 | {CTRY_AUSTRALIA, FCC2_WORLD, "AU", "AUSTRALIA", YES, YES, YES, YES, | ||
| 544 | YES, YES, YES, 7000}, | ||
| 545 | {CTRY_AUSTRALIA2, FCC6_WORLD, "AU", "AUSTRALIA2", YES, YES, YES, | ||
| 546 | YES, YES, YES, YES, 7000}, | ||
| 547 | {CTRY_AUSTRIA, ETSI1_WORLD, "AT", "AUSTRIA", YES, NO, YES, YES, | ||
| 548 | YES, YES, YES, 7000}, | ||
| 549 | {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", "AZERBAIJAN", YES, YES, YES, | ||
| 550 | YES, YES, YES, YES, 7000}, | ||
| 551 | {CTRY_BAHRAIN, APL6_WORLD, "BH", "BAHRAIN", YES, NO, YES, YES, YES, | ||
| 552 | YES, NO, 7000}, | ||
| 553 | {CTRY_BELARUS, ETSI1_WORLD, "BY", "BELARUS", YES, NO, YES, YES, | ||
| 554 | YES, YES, YES, 7000}, | ||
| 555 | {CTRY_BELGIUM, ETSI1_WORLD, "BE", "BELGIUM", YES, NO, YES, YES, | ||
| 556 | YES, YES, YES, 7000}, | ||
| 557 | {CTRY_BELGIUM2, ETSI4_WORLD, "BL", "BELGIUM", YES, NO, YES, YES, | ||
| 558 | YES, YES, YES, 7000}, | ||
| 559 | {CTRY_BELIZE, APL1_ETSIC, "BZ", "BELIZE", YES, YES, YES, YES, YES, | ||
| 560 | YES, YES, 7000}, | ||
| 561 | {CTRY_BOLIVIA, APL1_ETSIC, "BO", "BOLVIA", YES, YES, YES, YES, YES, | ||
| 562 | YES, YES, 7000}, | ||
| 563 | {CTRY_BOSNIA_HERZ, ETSI1_WORLD, "BA", "BOSNIA_HERZGOWINA", YES, NO, | ||
| 564 | YES, YES, YES, YES, NO, 7000}, | ||
| 565 | {CTRY_BRAZIL, FCC3_WORLD, "BR", "BRAZIL", YES, NO, NO, YES, NO, | ||
| 566 | YES, NO, 7000}, | ||
| 567 | {CTRY_BRUNEI_DARUSSALAM, APL1_WORLD, "BN", "BRUNEI DARUSSALAM", | ||
| 568 | YES, YES, YES, YES, YES, YES, YES, 7000}, | ||
| 569 | {CTRY_BULGARIA, ETSI6_WORLD, "BG", "BULGARIA", YES, NO, YES, YES, | ||
| 570 | YES, YES, YES, 7000}, | ||
| 571 | {CTRY_CANADA, FCC2_FCCA, "CA", "CANADA", YES, YES, YES, YES, YES, | ||
| 572 | YES, YES, 7000}, | ||
| 573 | {CTRY_CANADA2, FCC6_FCCA, "CA", "CANADA2", YES, YES, YES, YES, YES, | ||
| 574 | YES, YES, 7000}, | ||
| 575 | {CTRY_CHILE, APL6_WORLD, "CL", "CHILE", YES, YES, YES, YES, YES, | ||
| 576 | YES, YES, 7000}, | ||
| 577 | {CTRY_CHINA, APL1_WORLD, "CN", "CHINA", YES, YES, YES, YES, YES, | ||
| 578 | YES, YES, 7000}, | ||
| 579 | {CTRY_COLOMBIA, FCC1_FCCA, "CO", "COLOMBIA", YES, NO, YES, YES, | ||
| 580 | YES, YES, NO, 7000}, | ||
| 581 | {CTRY_COSTA_RICA, FCC1_WORLD, "CR", "COSTA RICA", YES, NO, YES, | ||
| 582 | YES, YES, YES, NO, 7000}, | ||
| 583 | {CTRY_CROATIA, ETSI3_WORLD, "HR", "CROATIA", YES, NO, YES, YES, | ||
| 584 | YES, YES, NO, 7000}, | ||
| 585 | {CTRY_CYPRUS, ETSI1_WORLD, "CY", "CYPRUS", YES, YES, YES, YES, YES, | ||
| 586 | YES, YES, 7000}, | ||
| 587 | {CTRY_CZECH, ETSI3_WORLD, "CZ", "CZECH REPUBLIC", YES, NO, YES, | ||
| 588 | YES, YES, YES, YES, 7000}, | ||
| 589 | {CTRY_DENMARK, ETSI1_WORLD, "DK", "DENMARK", YES, NO, YES, YES, | ||
| 590 | YES, YES, YES, 7000}, | ||
| 591 | {CTRY_DOMINICAN_REPUBLIC, FCC1_FCCA, "DO", "DOMINICAN REPUBLIC", | ||
| 592 | YES, YES, YES, YES, YES, YES, YES, 7000}, | ||
| 593 | {CTRY_ECUADOR, FCC1_WORLD, "EC", "ECUADOR", YES, NO, NO, YES, YES, | ||
| 594 | YES, NO, 7000}, | ||
| 595 | {CTRY_EGYPT, ETSI3_WORLD, "EG", "EGYPT", YES, NO, YES, YES, YES, | ||
| 596 | YES, NO, 7000}, | ||
| 597 | {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", "EL SALVADOR", YES, NO, YES, | ||
| 598 | YES, YES, YES, NO, 7000}, | ||
| 599 | {CTRY_ESTONIA, ETSI1_WORLD, "EE", "ESTONIA", YES, NO, YES, YES, | ||
| 600 | YES, YES, YES, 7000}, | ||
| 601 | {CTRY_FINLAND, ETSI1_WORLD, "FI", "FINLAND", YES, NO, YES, YES, | ||
| 602 | YES, YES, YES, 7000}, | ||
| 603 | {CTRY_FRANCE, ETSI1_WORLD, "FR", "FRANCE", YES, NO, YES, YES, YES, | ||
| 604 | YES, YES, 7000}, | ||
| 605 | {CTRY_GEORGIA, ETSI4_WORLD, "GE", "GEORGIA", YES, YES, YES, YES, | ||
| 606 | YES, YES, YES, 7000}, | ||
| 607 | {CTRY_GERMANY, ETSI1_WORLD, "DE", "GERMANY", YES, NO, YES, YES, | ||
| 608 | YES, YES, YES, 7000}, | ||
| 609 | {CTRY_GREECE, ETSI1_WORLD, "GR", "GREECE", YES, NO, YES, YES, YES, | ||
| 610 | YES, YES, 7000}, | ||
| 611 | {CTRY_GUATEMALA, FCC1_FCCA, "GT", "GUATEMALA", YES, YES, YES, YES, | ||
| 612 | YES, YES, YES, 7000}, | ||
| 613 | {CTRY_HONDURAS, NULL1_WORLD, "HN", "HONDURAS", YES, NO, YES, YES, | ||
| 614 | YES, NO, NO, 7000}, | ||
| 615 | {CTRY_HONG_KONG, FCC2_WORLD, "HK", "HONG KONG", YES, YES, YES, YES, | ||
| 616 | YES, YES, YES, 7000}, | ||
| 617 | {CTRY_HUNGARY, ETSI1_WORLD, "HU", "HUNGARY", YES, NO, YES, YES, | ||
| 618 | YES, YES, YES, 7000}, | ||
| 619 | {CTRY_ICELAND, ETSI1_WORLD, "IS", "ICELAND", YES, NO, YES, YES, | ||
| 620 | YES, YES, YES, 7000}, | ||
| 621 | {CTRY_INDIA, APL6_WORLD, "IN", "INDIA", YES, NO, YES, YES, YES, | ||
| 622 | YES, NO, 7000}, | ||
| 623 | {CTRY_INDONESIA, APL1_WORLD, "ID", "INDONESIA", YES, NO, YES, YES, | ||
| 624 | YES, YES, NO, 7000}, | ||
| 625 | {CTRY_IRAN, APL1_WORLD, "IR", "IRAN", YES, YES, YES, YES, YES, YES, | ||
| 626 | YES, 7000}, | ||
| 627 | {CTRY_IRELAND, ETSI1_WORLD, "IE", "IRELAND", YES, NO, YES, YES, | ||
| 628 | YES, YES, YES, 7000}, | ||
| 629 | {CTRY_ISRAEL, NULL1_WORLD, "IL", "ISRAEL", YES, NO, YES, YES, YES, | ||
| 630 | NO, NO, 7000}, | ||
| 631 | {CTRY_ITALY, ETSI1_WORLD, "IT", "ITALY", YES, NO, YES, YES, YES, | ||
| 632 | YES, YES, 7000}, | ||
| 633 | {CTRY_JAMAICA, ETSI1_WORLD, "JM", "JAMAICA", YES, NO, YES, YES, | ||
| 634 | YES, YES, YES, 7000}, | ||
| 635 | |||
| 636 | {CTRY_JAPAN, MKK1_MKKA, "JP", "JAPAN", YES, NO, NO, YES, YES, YES, | ||
| 637 | YES, 7000}, | ||
| 638 | {CTRY_JAPAN1, MKK1_MKKB, "JP", "JAPAN1", YES, NO, NO, YES, YES, | ||
| 639 | YES, YES, 7000}, | ||
| 640 | {CTRY_JAPAN2, MKK1_FCCA, "JP", "JAPAN2", YES, NO, NO, YES, YES, | ||
| 641 | YES, YES, 7000}, | ||
| 642 | {CTRY_JAPAN3, MKK2_MKKA, "JP", "JAPAN3", YES, NO, NO, YES, YES, | ||
| 643 | YES, YES, 7000}, | ||
| 644 | {CTRY_JAPAN4, MKK1_MKKA1, "JP", "JAPAN4", YES, NO, NO, YES, YES, | ||
| 645 | YES, YES, 7000}, | ||
| 646 | {CTRY_JAPAN5, MKK1_MKKA2, "JP", "JAPAN5", YES, NO, NO, YES, YES, | ||
| 647 | YES, YES, 7000}, | ||
| 648 | {CTRY_JAPAN6, MKK1_MKKC, "JP", "JAPAN6", YES, NO, NO, YES, YES, | ||
| 649 | YES, YES, 7000}, | ||
| 650 | |||
| 651 | {CTRY_JAPAN7, MKK3_MKKB, "JP", "JAPAN7", YES, NO, NO, YES, YES, | ||
| 652 | YES, YES, 7000}, | ||
| 653 | {CTRY_JAPAN8, MKK3_MKKA2, "JP", "JAPAN8", YES, NO, NO, YES, YES, | ||
| 654 | YES, YES, 7000}, | ||
| 655 | {CTRY_JAPAN9, MKK3_MKKC, "JP", "JAPAN9", YES, NO, NO, YES, YES, | ||
| 656 | YES, YES, 7000}, | ||
| 657 | |||
| 658 | {CTRY_JAPAN10, MKK4_MKKB, "JP", "JAPAN10", YES, NO, NO, YES, YES, | ||
| 659 | YES, YES, 7000}, | ||
| 660 | {CTRY_JAPAN11, MKK4_MKKA2, "JP", "JAPAN11", YES, NO, NO, YES, YES, | ||
| 661 | YES, YES, 7000}, | ||
| 662 | {CTRY_JAPAN12, MKK4_MKKC, "JP", "JAPAN12", YES, NO, NO, YES, YES, | ||
| 663 | YES, YES, 7000}, | ||
| 664 | |||
| 665 | {CTRY_JAPAN13, MKK5_MKKB, "JP", "JAPAN13", YES, NO, NO, YES, YES, | ||
| 666 | YES, YES, 7000}, | ||
| 667 | {CTRY_JAPAN14, MKK5_MKKA2, "JP", "JAPAN14", YES, NO, NO, YES, YES, | ||
| 668 | YES, YES, 7000}, | ||
| 669 | {CTRY_JAPAN15, MKK5_MKKC, "JP", "JAPAN15", YES, NO, NO, YES, YES, | ||
| 670 | YES, YES, 7000}, | ||
| 671 | |||
| 672 | {CTRY_JAPAN16, MKK6_MKKB, "JP", "JAPAN16", YES, NO, NO, YES, YES, | ||
| 673 | YES, YES, 7000}, | ||
| 674 | {CTRY_JAPAN17, MKK6_MKKA2, "JP", "JAPAN17", YES, NO, NO, YES, YES, | ||
| 675 | YES, YES, 7000}, | ||
| 676 | {CTRY_JAPAN18, MKK6_MKKC, "JP", "JAPAN18", YES, NO, NO, YES, YES, | ||
| 677 | YES, YES, 7000}, | ||
| 678 | |||
| 679 | {CTRY_JAPAN19, MKK7_MKKB, "JP", "JAPAN19", YES, NO, NO, YES, YES, | ||
| 680 | YES, YES, 7000}, | ||
| 681 | {CTRY_JAPAN20, MKK7_MKKA2, "JP", "JAPAN20", YES, NO, NO, YES, YES, | ||
| 682 | YES, YES, 7000}, | ||
| 683 | {CTRY_JAPAN21, MKK7_MKKC, "JP", "JAPAN21", YES, NO, NO, YES, YES, | ||
| 684 | YES, YES, 7000}, | ||
| 685 | |||
| 686 | {CTRY_JAPAN22, MKK8_MKKB, "JP", "JAPAN22", YES, NO, NO, YES, YES, | ||
| 687 | YES, YES, 7000}, | ||
| 688 | {CTRY_JAPAN23, MKK8_MKKA2, "JP", "JAPAN23", YES, NO, NO, YES, YES, | ||
| 689 | YES, YES, 7000}, | ||
| 690 | {CTRY_JAPAN24, MKK8_MKKC, "JP", "JAPAN24", YES, NO, NO, YES, YES, | ||
| 691 | YES, YES, 7000}, | ||
| 692 | |||
| 693 | {CTRY_JAPAN25, MKK3_MKKA, "JP", "JAPAN25", YES, NO, NO, YES, YES, | ||
| 694 | YES, YES, 7000}, | ||
| 695 | {CTRY_JAPAN26, MKK3_MKKA1, "JP", "JAPAN26", YES, NO, NO, YES, YES, | ||
| 696 | YES, YES, 7000}, | ||
| 697 | {CTRY_JAPAN27, MKK3_FCCA, "JP", "JAPAN27", YES, NO, NO, YES, YES, | ||
| 698 | YES, YES, 7000}, | ||
| 699 | {CTRY_JAPAN28, MKK4_MKKA1, "JP", "JAPAN28", YES, NO, NO, YES, YES, | ||
| 700 | YES, YES, 7000}, | ||
| 701 | {CTRY_JAPAN29, MKK4_FCCA, "JP", "JAPAN29", YES, NO, NO, YES, YES, | ||
| 702 | YES, YES, 7000}, | ||
| 703 | {CTRY_JAPAN30, MKK6_MKKA1, "JP", "JAPAN30", YES, NO, NO, YES, YES, | ||
| 704 | YES, YES, 7000}, | ||
| 705 | {CTRY_JAPAN31, MKK6_FCCA, "JP", "JAPAN31", YES, NO, NO, YES, YES, | ||
| 706 | YES, YES, 7000}, | ||
| 707 | {CTRY_JAPAN32, MKK7_MKKA1, "JP", "JAPAN32", YES, NO, NO, YES, YES, | ||
| 708 | YES, YES, 7000}, | ||
| 709 | {CTRY_JAPAN33, MKK7_FCCA, "JP", "JAPAN33", YES, NO, NO, YES, YES, | ||
| 710 | YES, YES, 7000}, | ||
| 711 | {CTRY_JAPAN34, MKK9_MKKA, "JP", "JAPAN34", YES, NO, NO, YES, YES, | ||
| 712 | YES, YES, 7000}, | ||
| 713 | {CTRY_JAPAN35, MKK10_MKKA, "JP", "JAPAN35", YES, NO, NO, YES, YES, | ||
| 714 | YES, YES, 7000}, | ||
| 715 | {CTRY_JAPAN36, MKK4_MKKA, "JP", "JAPAN36", YES, NO, NO, YES, YES, | ||
| 716 | YES, YES, 7000}, | ||
| 717 | {CTRY_JAPAN37, MKK9_FCCA, "JP", "JAPAN37", YES, NO, NO, YES, YES, | ||
| 718 | YES, YES, 7000}, | ||
| 719 | {CTRY_JAPAN38, MKK9_MKKA1, "JP", "JAPAN38", YES, NO, NO, YES, YES, | ||
| 720 | YES, YES, 7000}, | ||
| 721 | {CTRY_JAPAN39, MKK9_MKKC, "JP", "JAPAN39", YES, NO, NO, YES, YES, | ||
| 722 | YES, YES, 7000}, | ||
| 723 | {CTRY_JAPAN40, MKK9_MKKA2, "JP", "JAPAN40", YES, NO, NO, YES, YES, | ||
| 724 | YES, YES, 7000}, | ||
| 725 | {CTRY_JAPAN41, MKK10_FCCA, "JP", "JAPAN41", YES, NO, NO, YES, YES, | ||
| 726 | YES, YES, 7000}, | ||
| 727 | {CTRY_JAPAN42, MKK10_MKKA1, "JP", "JAPAN42", YES, NO, NO, YES, YES, | ||
| 728 | YES, YES, 7000}, | ||
| 729 | {CTRY_JAPAN43, MKK10_MKKC, "JP", "JAPAN43", YES, NO, NO, YES, YES, | ||
| 730 | YES, YES, 7000}, | ||
| 731 | {CTRY_JAPAN44, MKK10_MKKA2, "JP", "JAPAN44", YES, NO, NO, YES, YES, | ||
| 732 | YES, YES, 7000}, | ||
| 733 | {CTRY_JAPAN45, MKK11_MKKA, "JP", "JAPAN45", YES, NO, NO, YES, YES, | ||
| 734 | YES, YES, 7000}, | ||
| 735 | {CTRY_JAPAN46, MKK11_FCCA, "JP", "JAPAN46", YES, NO, NO, YES, YES, | ||
| 736 | YES, YES, 7000}, | ||
| 737 | {CTRY_JAPAN47, MKK11_MKKA1, "JP", "JAPAN47", YES, NO, NO, YES, YES, | ||
| 738 | YES, YES, 7000}, | ||
| 739 | {CTRY_JAPAN48, MKK11_MKKC, "JP", "JAPAN48", YES, NO, NO, YES, YES, | ||
| 740 | YES, YES, 7000}, | ||
| 741 | {CTRY_JAPAN49, MKK11_MKKA2, "JP", "JAPAN49", YES, NO, NO, YES, YES, | ||
| 742 | YES, YES, 7000}, | ||
| 743 | {CTRY_JAPAN50, MKK12_MKKA, "JP", "JAPAN50", YES, NO, NO, YES, YES, | ||
| 744 | YES, YES, 7000}, | ||
| 745 | {CTRY_JAPAN51, MKK12_FCCA, "JP", "JAPAN51", YES, NO, NO, YES, YES, | ||
| 746 | YES, YES, 7000}, | ||
| 747 | {CTRY_JAPAN52, MKK12_MKKA1, "JP", "JAPAN52", YES, NO, NO, YES, YES, | ||
| 748 | YES, YES, 7000}, | ||
| 749 | {CTRY_JAPAN53, MKK12_MKKC, "JP", "JAPAN53", YES, NO, NO, YES, YES, | ||
| 750 | YES, YES, 7000}, | ||
| 751 | {CTRY_JAPAN54, MKK12_MKKA2, "JP", "JAPAN54", YES, NO, NO, YES, YES, | ||
| 752 | YES, YES, 7000}, | ||
| 753 | |||
| 754 | {CTRY_JAPAN57, MKK13_MKKB, "JP", "JAPAN57", YES, NO, NO, YES, YES, | ||
| 755 | YES, YES, 7000}, | ||
| 756 | {CTRY_JAPAN58, MKK14_MKKA1, "JP", "JAPAN58", YES, NO, NO, YES, YES, | ||
| 757 | YES, YES, 7000}, | ||
| 758 | {CTRY_JAPAN59, MKK15_MKKA1, "JP", "JAPAN59", YES, NO, NO, YES, YES, | ||
| 759 | YES, YES, 7000}, | ||
| 760 | |||
| 761 | {CTRY_JORDAN, ETSI2_WORLD, "JO", "JORDAN", YES, NO, YES, YES, YES, | ||
| 762 | YES, NO, 7000}, | ||
| 763 | {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", "KAZAKHSTAN", YES, NO, YES, | ||
| 764 | YES, YES, NO, NO, 7000}, | ||
| 765 | {CTRY_KOREA_NORTH, APL9_WORLD, "KP", "NORTH KOREA", YES, NO, NO, | ||
| 766 | YES, YES, YES, YES, 7000}, | ||
| 767 | {CTRY_KOREA_ROC, APL9_WORLD, "KR", "KOREA REPUBLIC", YES, NO, NO, | ||
| 768 | YES, NO, YES, NO, 7000}, | ||
| 769 | {CTRY_KOREA_ROC2, APL2_WORLD, "K2", "KOREA REPUBLIC2", YES, NO, NO, | ||
| 770 | YES, NO, YES, NO, 7000}, | ||
| 771 | {CTRY_KOREA_ROC3, APL9_WORLD, "K3", "KOREA REPUBLIC3", YES, NO, NO, | ||
| 772 | YES, NO, YES, NO, 7000}, | ||
| 773 | {CTRY_KUWAIT, NULL1_WORLD, "KW", "KUWAIT", YES, NO, YES, YES, YES, | ||
| 774 | NO, NO, 7000}, | ||
| 775 | {CTRY_LATVIA, ETSI1_WORLD, "LV", "LATVIA", YES, NO, YES, YES, YES, | ||
| 776 | YES, YES, 7000}, | ||
| 777 | {CTRY_LEBANON, NULL1_WORLD, "LB", "LEBANON", YES, NO, YES, YES, | ||
| 778 | YES, NO, NO, 7000}, | ||
| 779 | {CTRY_LIECHTENSTEIN, ETSI1_WORLD, "LI", "LIECHTENSTEIN", YES, NO, | ||
| 780 | YES, YES, YES, YES, YES, 7000}, | ||
| 781 | {CTRY_LITHUANIA, ETSI1_WORLD, "LT", "LITHUANIA", YES, NO, YES, YES, | ||
| 782 | YES, YES, YES, 7000}, | ||
| 783 | {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", "LUXEMBOURG", YES, NO, YES, | ||
| 784 | YES, YES, YES, YES, 7000}, | ||
| 785 | {CTRY_MACAU, FCC2_WORLD, "MO", "MACAU", YES, YES, YES, YES, YES, | ||
| 786 | YES, YES, 7000}, | ||
| 787 | {CTRY_MACEDONIA, NULL1_WORLD, "MK", "MACEDONIA", YES, NO, YES, YES, | ||
| 788 | YES, NO, NO, 7000}, | ||
| 789 | {CTRY_MALAYSIA, APL8_WORLD, "MY", "MALAYSIA", YES, NO, NO, YES, NO, | ||
| 790 | YES, NO, 7000}, | ||
| 791 | {CTRY_MALTA, ETSI1_WORLD, "MT", "MALTA", YES, NO, YES, YES, YES, | ||
| 792 | YES, YES, 7000}, | ||
| 793 | {CTRY_MEXICO, FCC1_FCCA, "MX", "MEXICO", YES, YES, YES, YES, YES, | ||
| 794 | YES, YES, 7000}, | ||
| 795 | {CTRY_MONACO, ETSI4_WORLD, "MC", "MONACO", YES, YES, YES, YES, YES, | ||
| 796 | YES, YES, 7000}, | ||
| 797 | {CTRY_MOROCCO, NULL1_WORLD, "MA", "MOROCCO", YES, NO, YES, YES, | ||
| 798 | YES, NO, NO, 7000}, | ||
| 799 | {CTRY_NEPAL, APL1_WORLD, "NP", "NEPAL", YES, NO, YES, YES, YES, | ||
| 800 | YES, YES, 7000}, | ||
| 801 | {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", "NETHERLANDS", YES, NO, YES, | ||
| 802 | YES, YES, YES, YES, 7000}, | ||
| 803 | {CTRY_NETHERLANDS_ANTILLES, ETSI1_WORLD, "AN", | ||
| 804 | "NETHERLANDS-ANTILLES", YES, NO, YES, YES, YES, YES, YES, 7000}, | ||
| 805 | {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", "NEW ZEALAND", YES, NO, YES, | ||
| 806 | YES, YES, YES, NO, 7000}, | ||
| 807 | {CTRY_NORWAY, ETSI1_WORLD, "NO", "NORWAY", YES, NO, YES, YES, YES, | ||
| 808 | YES, YES, 7000}, | ||
| 809 | {CTRY_OMAN, APL6_WORLD, "OM", "OMAN", YES, NO, YES, YES, YES, YES, | ||
| 810 | NO, 7000}, | ||
| 811 | {CTRY_PAKISTAN, NULL1_WORLD, "PK", "PAKISTAN", YES, NO, YES, YES, | ||
| 812 | YES, NO, NO, 7000}, | ||
| 813 | {CTRY_PANAMA, FCC1_FCCA, "PA", "PANAMA", YES, YES, YES, YES, YES, | ||
| 814 | YES, YES, 7000}, | ||
| 815 | {CTRY_PAPUA_NEW_GUINEA, FCC1_WORLD, "PG", "PAPUA NEW GUINEA", YES, | ||
| 816 | YES, YES, YES, YES, YES, YES, 7000}, | ||
| 817 | {CTRY_PERU, APL1_WORLD, "PE", "PERU", YES, NO, YES, YES, YES, YES, | ||
| 818 | NO, 7000}, | ||
| 819 | {CTRY_PHILIPPINES, APL1_WORLD, "PH", "PHILIPPINES", YES, YES, YES, | ||
| 820 | YES, YES, YES, YES, 7000}, | ||
| 821 | {CTRY_POLAND, ETSI1_WORLD, "PL", "POLAND", YES, NO, YES, YES, YES, | ||
| 822 | YES, YES, 7000}, | ||
| 823 | {CTRY_PORTUGAL, ETSI1_WORLD, "PT", "PORTUGAL", YES, NO, YES, YES, | ||
| 824 | YES, YES, YES, 7000}, | ||
| 825 | {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", "PUERTO RICO", YES, YES, YES, | ||
| 826 | YES, YES, YES, YES, 7000}, | ||
| 827 | {CTRY_QATAR, NULL1_WORLD, "QA", "QATAR", YES, NO, YES, YES, YES, | ||
| 828 | NO, NO, 7000}, | ||
| 829 | {CTRY_ROMANIA, NULL1_WORLD, "RO", "ROMANIA", YES, NO, YES, YES, | ||
| 830 | YES, NO, NO, 7000}, | ||
| 831 | {CTRY_RUSSIA, NULL1_WORLD, "RU", "RUSSIA", YES, NO, YES, YES, YES, | ||
| 832 | NO, NO, 7000}, | ||
| 833 | {CTRY_SAUDI_ARABIA, NULL1_WORLD, "SA", "SAUDI ARABIA", YES, NO, | ||
| 834 | YES, YES, YES, NO, NO, 7000}, | ||
| 835 | {CTRY_SERBIA_MONTENEGRO, ETSI1_WORLD, "CS", "SERBIA & MONTENEGRO", | ||
| 836 | YES, NO, YES, YES, YES, YES, YES, 7000}, | ||
| 837 | {CTRY_SINGAPORE, APL6_WORLD, "SG", "SINGAPORE", YES, YES, YES, YES, | ||
| 838 | YES, YES, YES, 7000}, | ||
| 839 | {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", "SLOVAK REPUBLIC", YES, NO, YES, | ||
| 840 | YES, YES, YES, YES, 7000}, | ||
| 841 | {CTRY_SLOVENIA, ETSI1_WORLD, "SI", "SLOVENIA", YES, NO, YES, YES, | ||
| 842 | YES, YES, YES, 7000}, | ||
| 843 | {CTRY_SOUTH_AFRICA, FCC3_WORLD, "ZA", "SOUTH AFRICA", YES, NO, YES, | ||
| 844 | YES, YES, YES, NO, 7000}, | ||
| 845 | {CTRY_SPAIN, ETSI1_WORLD, "ES", "SPAIN", YES, NO, YES, YES, YES, | ||
| 846 | YES, YES, 7000}, | ||
| 847 | {CTRY_SRI_LANKA, FCC3_WORLD, "LK", "SRI LANKA", YES, NO, YES, YES, | ||
| 848 | YES, YES, NO, 7000}, | ||
| 849 | {CTRY_SWEDEN, ETSI1_WORLD, "SE", "SWEDEN", YES, NO, YES, YES, YES, | ||
| 850 | YES, YES, 7000}, | ||
| 851 | {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", "SWITZERLAND", YES, NO, YES, | ||
| 852 | YES, YES, YES, YES, 7000}, | ||
| 853 | {CTRY_SYRIA, NULL1_WORLD, "SY", "SYRIA", YES, NO, YES, YES, YES, | ||
| 854 | NO, NO, 7000}, | ||
| 855 | {CTRY_TAIWAN, APL3_FCCA, "TW", "TAIWAN", YES, YES, YES, YES, YES, | ||
| 856 | YES, YES, 7000}, | ||
| 857 | {CTRY_THAILAND, NULL1_WORLD, "TH", "THAILAND", YES, NO, YES, YES, | ||
| 858 | YES, NO, NO, 7000}, | ||
| 859 | {CTRY_TRINIDAD_Y_TOBAGO, ETSI4_WORLD, "TT", "TRINIDAD & TOBAGO", | ||
| 860 | YES, NO, YES, YES, YES, YES, NO, 7000}, | ||
| 861 | {CTRY_TUNISIA, ETSI3_WORLD, "TN", "TUNISIA", YES, NO, YES, YES, | ||
| 862 | YES, YES, NO, 7000}, | ||
| 863 | {CTRY_TURKEY, ETSI3_WORLD, "TR", "TURKEY", YES, NO, YES, YES, YES, | ||
| 864 | YES, NO, 7000}, | ||
| 865 | {CTRY_UKRAINE, NULL1_WORLD, "UA", "UKRAINE", YES, NO, YES, YES, | ||
| 866 | YES, NO, NO, 7000}, | ||
| 867 | {CTRY_UAE, NULL1_WORLD, "AE", "UNITED ARAB EMIRATES", YES, NO, YES, | ||
| 868 | YES, YES, NO, NO, 7000}, | ||
| 869 | {CTRY_UNITED_KINGDOM, ETSI1_WORLD, "GB", "UNITED KINGDOM", YES, NO, | ||
| 870 | YES, YES, YES, YES, YES, 7000}, | ||
| 871 | {CTRY_UNITED_STATES, FCC3_FCCA, "US", "UNITED STATES", YES, YES, | ||
| 872 | YES, YES, YES, YES, YES, 5825}, | ||
| 873 | {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS", | ||
| 874 | "UNITED STATES (PUBLIC SAFETY)", YES, YES, YES, YES, YES, YES, | ||
| 875 | YES, 7000}, | ||
| 876 | {CTRY_URUGUAY, APL2_WORLD, "UY", "URUGUAY", YES, NO, YES, YES, YES, | ||
| 877 | YES, NO, 7000}, | ||
| 878 | {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", "UZBEKISTAN", YES, YES, YES, | ||
| 879 | YES, YES, YES, YES, 7000}, | ||
| 880 | {CTRY_VENEZUELA, APL2_ETSIC, "VE", "VENEZUELA", YES, NO, YES, YES, | ||
| 881 | YES, YES, NO, 7000}, | ||
| 882 | {CTRY_VIET_NAM, NULL1_WORLD, "VN", "VIET NAM", YES, NO, YES, YES, | ||
| 883 | YES, NO, NO, 7000}, | ||
| 884 | {CTRY_YEMEN, NULL1_WORLD, "YE", "YEMEN", YES, NO, YES, YES, YES, | ||
| 885 | NO, NO, 7000}, | ||
| 886 | {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", "ZIMBABWE", YES, NO, YES, YES, | ||
| 887 | YES, NO, NO, 7000} | ||
| 888 | }; | ||
| 889 | |||
| 890 | enum { | ||
| 891 | NO_DFS = 0x0000000000000000ULL, | ||
| 892 | DFS_FCC3 = 0x0000000000000001ULL, | ||
| 893 | DFS_ETSI = 0x0000000000000002ULL, | ||
| 894 | DFS_MKK4 = 0x0000000000000004ULL, | ||
| 895 | }; | ||
| 896 | |||
| 897 | enum { | ||
| 898 | F1_4915_4925, | ||
| 899 | F1_4935_4945, | ||
| 900 | F1_4920_4980, | ||
| 901 | F1_4942_4987, | ||
| 902 | F1_4945_4985, | ||
| 903 | F1_4950_4980, | ||
| 904 | F1_5035_5040, | ||
| 905 | F1_5040_5080, | ||
| 906 | F1_5055_5055, | ||
| 907 | |||
| 908 | F1_5120_5240, | ||
| 909 | |||
| 910 | F1_5170_5230, | ||
| 911 | F2_5170_5230, | ||
| 912 | |||
| 913 | F1_5180_5240, | ||
| 914 | F2_5180_5240, | ||
| 915 | F3_5180_5240, | ||
| 916 | F4_5180_5240, | ||
| 917 | F5_5180_5240, | ||
| 918 | F6_5180_5240, | ||
| 919 | F7_5180_5240, | ||
| 920 | F8_5180_5240, | ||
| 921 | |||
| 922 | F1_5180_5320, | ||
| 923 | |||
| 924 | F1_5240_5280, | ||
| 925 | |||
| 926 | F1_5260_5280, | ||
| 927 | |||
| 928 | F1_5260_5320, | ||
| 929 | F2_5260_5320, | ||
| 930 | F3_5260_5320, | ||
| 931 | F4_5260_5320, | ||
| 932 | F5_5260_5320, | ||
| 933 | F6_5260_5320, | ||
| 934 | |||
| 935 | F1_5260_5700, | ||
| 936 | |||
| 937 | F1_5280_5320, | ||
| 938 | |||
| 939 | F1_5500_5580, | ||
| 940 | |||
| 941 | F1_5500_5620, | ||
| 942 | |||
| 943 | F1_5500_5700, | ||
| 944 | F2_5500_5700, | ||
| 945 | F3_5500_5700, | ||
| 946 | F4_5500_5700, | ||
| 947 | F5_5500_5700, | ||
| 948 | |||
| 949 | F1_5660_5700, | ||
| 950 | |||
| 951 | F1_5745_5805, | ||
| 952 | F2_5745_5805, | ||
| 953 | F3_5745_5805, | ||
| 954 | |||
| 955 | F1_5745_5825, | ||
| 956 | F2_5745_5825, | ||
| 957 | F3_5745_5825, | ||
| 958 | F4_5745_5825, | ||
| 959 | F5_5745_5825, | ||
| 960 | F6_5745_5825, | ||
| 961 | |||
| 962 | W1_4920_4980, | ||
| 963 | W1_5040_5080, | ||
| 964 | W1_5170_5230, | ||
| 965 | W1_5180_5240, | ||
| 966 | W1_5260_5320, | ||
| 967 | W1_5745_5825, | ||
| 968 | W1_5500_5700, | ||
| 969 | A_DEMO_ALL_CHANNELS | ||
| 970 | }; | ||
| 971 | |||
| 972 | static struct RegDmnFreqBand regDmn5GhzFreq[] = { | ||
| 973 | {4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16}, | ||
| 974 | {4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16}, | ||
| 975 | {4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7}, | ||
| 976 | {4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC, 0}, | ||
| 977 | {4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC, 0}, | ||
| 978 | {4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC, 0}, | ||
| 979 | {5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, | ||
| 980 | {5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2}, | ||
| 981 | {5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, | ||
| 982 | |||
| 983 | {5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 984 | |||
| 985 | {5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1}, | ||
| 986 | {5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1}, | ||
| 987 | |||
| 988 | {5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 989 | {5180, 5240, 17, 6, 20, 20, NO_DFS, NO_PSCAN, 1}, | ||
| 990 | {5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 991 | {5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 992 | {5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 993 | {5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0}, | ||
| 994 | {5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK3, 0}, | ||
| 995 | {5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 996 | |||
| 997 | {5180, 5320, 20, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0}, | ||
| 998 | |||
| 999 | {5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 1000 | |||
| 1001 | {5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, | ||
| 1002 | PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 1003 | |||
| 1004 | {5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, | ||
| 1005 | PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 1006 | |||
| 1007 | {5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, | ||
| 1008 | PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3, 0}, | ||
| 1009 | |||
| 1010 | |||
| 1011 | {5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, | ||
| 1012 | PSCAN_FCC | PSCAN_ETSI, 2}, | ||
| 1013 | {5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2}, | ||
| 1014 | {5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0}, | ||
| 1015 | {5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1016 | |||
| 1017 | {5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0}, | ||
| 1018 | |||
| 1019 | {5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0}, | ||
| 1020 | |||
| 1021 | {5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, | ||
| 1022 | |||
| 1023 | {5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0}, | ||
| 1024 | |||
| 1025 | {5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4}, | ||
| 1026 | {5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, | ||
| 1027 | PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 1028 | {5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, | ||
| 1029 | PSCAN_FCC | PSCAN_ETSI, 0}, | ||
| 1030 | {5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, | ||
| 1031 | PSCAN_MKK3 | PSCAN_FCC, 0}, | ||
| 1032 | {5500, 5700, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0}, | ||
| 1033 | |||
| 1034 | {5660, 5700, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, | ||
| 1035 | |||
| 1036 | {5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1037 | {5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1038 | {5745, 5805, 30, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0}, | ||
| 1039 | {5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1040 | {5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1041 | {5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1042 | {5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1043 | {5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3}, | ||
| 1044 | {5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1045 | |||
| 1046 | |||
| 1047 | {4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, | ||
| 1048 | {5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, | ||
| 1049 | {5170, 5230, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, | ||
| 1050 | {5180, 5240, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, | ||
| 1051 | {5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, | ||
| 1052 | {5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, | ||
| 1053 | {5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, | ||
| 1054 | {4920, 6100, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, | ||
| 1055 | }; | ||
| 1056 | |||
| 1057 | enum { | ||
| 1058 | T1_5130_5650, | ||
| 1059 | T1_5150_5670, | ||
| 1060 | |||
| 1061 | T1_5200_5200, | ||
| 1062 | T2_5200_5200, | ||
| 1063 | T3_5200_5200, | ||
| 1064 | T4_5200_5200, | ||
| 1065 | T5_5200_5200, | ||
| 1066 | T6_5200_5200, | ||
| 1067 | T7_5200_5200, | ||
| 1068 | T8_5200_5200, | ||
| 1069 | |||
| 1070 | T1_5200_5280, | ||
| 1071 | T2_5200_5280, | ||
| 1072 | T3_5200_5280, | ||
| 1073 | T4_5200_5280, | ||
| 1074 | T5_5200_5280, | ||
| 1075 | T6_5200_5280, | ||
| 1076 | |||
| 1077 | T1_5200_5240, | ||
| 1078 | T1_5210_5210, | ||
| 1079 | T2_5210_5210, | ||
| 1080 | T3_5210_5210, | ||
| 1081 | T4_5210_5210, | ||
| 1082 | T5_5210_5210, | ||
| 1083 | T6_5210_5210, | ||
| 1084 | T7_5210_5210, | ||
| 1085 | T8_5210_5210, | ||
| 1086 | T9_5210_5210, | ||
| 1087 | T10_5210_5210, | ||
| 1088 | T1_5240_5240, | ||
| 1089 | |||
| 1090 | T1_5210_5250, | ||
| 1091 | T1_5210_5290, | ||
| 1092 | T2_5210_5290, | ||
| 1093 | T3_5210_5290, | ||
| 1094 | |||
| 1095 | T1_5280_5280, | ||
| 1096 | T2_5280_5280, | ||
| 1097 | T1_5290_5290, | ||
| 1098 | T2_5290_5290, | ||
| 1099 | T3_5290_5290, | ||
| 1100 | T1_5250_5290, | ||
| 1101 | T2_5250_5290, | ||
| 1102 | T3_5250_5290, | ||
| 1103 | T4_5250_5290, | ||
| 1104 | |||
| 1105 | T1_5540_5660, | ||
| 1106 | T2_5540_5660, | ||
| 1107 | T3_5540_5660, | ||
| 1108 | T1_5760_5800, | ||
| 1109 | T2_5760_5800, | ||
| 1110 | T3_5760_5800, | ||
| 1111 | T4_5760_5800, | ||
| 1112 | T5_5760_5800, | ||
| 1113 | T6_5760_5800, | ||
| 1114 | T7_5760_5800, | ||
| 1115 | |||
| 1116 | T1_5765_5805, | ||
| 1117 | T2_5765_5805, | ||
| 1118 | T3_5765_5805, | ||
| 1119 | T4_5765_5805, | ||
| 1120 | T5_5765_5805, | ||
| 1121 | T6_5765_5805, | ||
| 1122 | T7_5765_5805, | ||
| 1123 | T8_5765_5805, | ||
| 1124 | T9_5765_5805, | ||
| 1125 | |||
| 1126 | WT1_5210_5250, | ||
| 1127 | WT1_5290_5290, | ||
| 1128 | WT1_5540_5660, | ||
| 1129 | WT1_5760_5800, | ||
| 1130 | }; | ||
| 1131 | |||
| 1132 | enum { | ||
| 1133 | F1_2312_2372, | ||
| 1134 | F2_2312_2372, | ||
| 1135 | |||
| 1136 | F1_2412_2472, | ||
| 1137 | F2_2412_2472, | ||
| 1138 | F3_2412_2472, | ||
| 1139 | |||
| 1140 | F1_2412_2462, | ||
| 1141 | F2_2412_2462, | ||
| 1142 | |||
| 1143 | F1_2432_2442, | ||
| 1144 | |||
| 1145 | F1_2457_2472, | ||
| 1146 | |||
| 1147 | F1_2467_2472, | ||
| 1148 | |||
| 1149 | F1_2484_2484, | ||
| 1150 | F2_2484_2484, | ||
| 1151 | |||
| 1152 | F1_2512_2732, | ||
| 1153 | |||
| 1154 | W1_2312_2372, | ||
| 1155 | W1_2412_2412, | ||
| 1156 | W1_2417_2432, | ||
| 1157 | W1_2437_2442, | ||
| 1158 | W1_2447_2457, | ||
| 1159 | W1_2462_2462, | ||
| 1160 | W1_2467_2467, | ||
| 1161 | W2_2467_2467, | ||
| 1162 | W1_2472_2472, | ||
| 1163 | W2_2472_2472, | ||
| 1164 | W1_2484_2484, | ||
| 1165 | W2_2484_2484, | ||
| 1166 | }; | ||
| 1167 | |||
| 1168 | static struct RegDmnFreqBand regDmn2GhzFreq[] = { | ||
| 1169 | {2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1170 | {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1171 | |||
| 1172 | {2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1173 | {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0}, | ||
| 1174 | {2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1175 | |||
| 1176 | {2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1177 | {2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0}, | ||
| 1178 | |||
| 1179 | {2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1180 | |||
| 1181 | {2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1182 | |||
| 1183 | {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0}, | ||
| 1184 | |||
| 1185 | {2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1186 | {2484, 2484, 20, 0, 20, 5, NO_DFS, | ||
| 1187 | PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0}, | ||
| 1188 | |||
| 1189 | {2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1190 | |||
| 1191 | {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1192 | {2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1193 | {2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1194 | {2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1195 | {2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1196 | {2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1197 | {2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, | ||
| 1198 | {2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, | ||
| 1199 | {2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, | ||
| 1200 | {2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, | ||
| 1201 | {2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, | ||
| 1202 | {2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, | ||
| 1203 | }; | ||
| 1204 | |||
| 1205 | enum { | ||
| 1206 | G1_2312_2372, | ||
| 1207 | G2_2312_2372, | ||
| 1208 | |||
| 1209 | G1_2412_2472, | ||
| 1210 | G2_2412_2472, | ||
| 1211 | G3_2412_2472, | ||
| 1212 | |||
| 1213 | G1_2412_2462, | ||
| 1214 | G2_2412_2462, | ||
| 1215 | |||
| 1216 | G1_2432_2442, | ||
| 1217 | |||
| 1218 | G1_2457_2472, | ||
| 1219 | |||
| 1220 | G1_2512_2732, | ||
| 1221 | |||
| 1222 | G1_2467_2472, | ||
| 1223 | |||
| 1224 | WG1_2312_2372, | ||
| 1225 | WG1_2412_2462, | ||
| 1226 | WG1_2467_2472, | ||
| 1227 | WG2_2467_2472, | ||
| 1228 | G_DEMO_ALL_CHANNELS | ||
| 1229 | }; | ||
| 1230 | |||
| 1231 | static struct RegDmnFreqBand regDmn2Ghz11gFreq[] = { | ||
| 1232 | {2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1233 | {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1234 | |||
| 1235 | {2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1236 | {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0}, | ||
| 1237 | {2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1238 | |||
| 1239 | {2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1240 | {2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0}, | ||
| 1241 | |||
| 1242 | {2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1243 | |||
| 1244 | {2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1245 | |||
| 1246 | {2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1247 | |||
| 1248 | {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0}, | ||
| 1249 | |||
| 1250 | {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1251 | {2412, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1252 | {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, | ||
| 1253 | {2467, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, | ||
| 1254 | {2312, 2732, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, | ||
| 1255 | }; | ||
| 1256 | |||
| 1257 | enum { | ||
| 1258 | T1_2312_2372, | ||
| 1259 | T1_2437_2437, | ||
| 1260 | T2_2437_2437, | ||
| 1261 | T3_2437_2437, | ||
| 1262 | T1_2512_2732 | ||
| 1263 | }; | ||
| 1264 | |||
| 1265 | static struct regDomain regDomains[] = { | ||
| 1266 | |||
| 1267 | {DEBUG_REG_DMN, FCC, DFS_FCC3, NO_PSCAN, NO_REQ, | ||
| 1268 | BM(A_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1269 | -1), | ||
| 1270 | BM(T1_5130_5650, T1_5150_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1271 | -1), | ||
| 1272 | BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, -1, -1, | ||
| 1273 | -1, -1, -1, -1, -1, -1), | ||
| 1274 | BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, -1, -1, | ||
| 1275 | -1, -1, -1, -1, -1, -1), | ||
| 1276 | BM(G_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1277 | -1), | ||
| 1278 | BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, -1, -1, -1, -1, -1, | ||
| 1279 | -1, -1, -1, -1)}, | ||
| 1280 | |||
| 1281 | {APL1, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1282 | BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1283 | BM(T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1284 | BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1285 | BMZERO, | ||
| 1286 | BMZERO, | ||
| 1287 | BMZERO}, | ||
| 1288 | |||
| 1289 | {APL2, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1290 | BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1291 | BM(T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1292 | BM(T2_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1293 | BMZERO, | ||
| 1294 | BMZERO, | ||
| 1295 | BMZERO}, | ||
| 1296 | |||
| 1297 | {APL3, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1298 | BM(F1_5280_5320, F2_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1299 | -1), | ||
| 1300 | BM(T1_5290_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1301 | -1), | ||
| 1302 | BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1303 | BMZERO, | ||
| 1304 | BMZERO, | ||
| 1305 | BMZERO}, | ||
| 1306 | |||
| 1307 | {APL4, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1308 | BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1309 | -1), | ||
| 1310 | BM(T1_5210_5210, T3_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1311 | -1), | ||
| 1312 | BM(T1_5200_5200, T3_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1313 | -1), | ||
| 1314 | BMZERO, | ||
| 1315 | BMZERO, | ||
| 1316 | BMZERO}, | ||
| 1317 | |||
| 1318 | {APL5, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1319 | BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1320 | BM(T4_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1321 | BM(T4_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1322 | BMZERO, | ||
| 1323 | BMZERO, | ||
| 1324 | BMZERO}, | ||
| 1325 | |||
| 1326 | {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC, NO_REQ, | ||
| 1327 | BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1, | ||
| 1328 | -1, -1, -1, -1), | ||
| 1329 | BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1, | ||
| 1330 | -1, -1, -1, -1), | ||
| 1331 | BM(T1_5200_5280, T5_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1332 | -1), | ||
| 1333 | BMZERO, | ||
| 1334 | BMZERO, | ||
| 1335 | BMZERO}, | ||
| 1336 | |||
| 1337 | {APL7, ETSI, DFS_ETSI, PSCAN_ETSI, NO_REQ, | ||
| 1338 | BM(F1_5280_5320, F5_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1, | ||
| 1339 | -1, -1, -1, -1), | ||
| 1340 | BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1341 | -1), | ||
| 1342 | BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1343 | -1), | ||
| 1344 | BMZERO, | ||
| 1345 | BMZERO, | ||
| 1346 | BMZERO}, | ||
| 1347 | |||
| 1348 | {APL8, ETSI, NO_DFS, NO_PSCAN, | ||
| 1349 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1350 | BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1351 | -1), | ||
| 1352 | BM(T2_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1353 | -1), | ||
| 1354 | BM(T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1355 | -1), | ||
| 1356 | BMZERO, | ||
| 1357 | BMZERO, | ||
| 1358 | BMZERO}, | ||
| 1359 | |||
| 1360 | {APL9, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1361 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1362 | BM(F1_5180_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, -1, -1, | ||
| 1363 | -1, -1, -1, -1), | ||
| 1364 | BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1365 | -1), | ||
| 1366 | BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1367 | -1), | ||
| 1368 | BMZERO, | ||
| 1369 | BMZERO, | ||
| 1370 | BMZERO}, | ||
| 1371 | |||
| 1372 | {APL10, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1373 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1374 | BM(F1_5180_5320, F5_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1, | ||
| 1375 | -1, -1, -1, -1), | ||
| 1376 | BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1377 | -1), | ||
| 1378 | BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1379 | -1), | ||
| 1380 | BMZERO, | ||
| 1381 | BMZERO, | ||
| 1382 | BMZERO}, | ||
| 1383 | |||
| 1384 | {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1385 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1386 | BM(F4_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1, | ||
| 1387 | -1, -1, -1, -1), | ||
| 1388 | BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1389 | BM(T2_5200_5280, T2_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1390 | -1), | ||
| 1391 | BMZERO, | ||
| 1392 | BMZERO, | ||
| 1393 | BMZERO}, | ||
| 1394 | |||
| 1395 | {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1396 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1397 | BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1398 | BM(T3_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1399 | BM(T2_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1400 | BMZERO, | ||
| 1401 | BMZERO, | ||
| 1402 | BMZERO}, | ||
| 1403 | |||
| 1404 | {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1405 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1406 | BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1407 | -1), | ||
| 1408 | BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1409 | BM(T2_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1410 | BMZERO, | ||
| 1411 | BMZERO, | ||
| 1412 | BMZERO}, | ||
| 1413 | |||
| 1414 | {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1415 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1416 | BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1417 | -1), | ||
| 1418 | BM(T2_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1419 | BM(T3_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1420 | BMZERO, | ||
| 1421 | BMZERO, | ||
| 1422 | BMZERO}, | ||
| 1423 | |||
| 1424 | {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1425 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1426 | BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1427 | BM(T4_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1428 | BM(T3_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1429 | BMZERO, | ||
| 1430 | BMZERO, | ||
| 1431 | BMZERO}, | ||
| 1432 | |||
| 1433 | {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI, | ||
| 1434 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1435 | BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1, | ||
| 1436 | -1, -1, -1, -1), | ||
| 1437 | BM(T1_5210_5250, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1438 | BM(T4_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1439 | BMZERO, | ||
| 1440 | BMZERO, | ||
| 1441 | BMZERO}, | ||
| 1442 | |||
| 1443 | {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1444 | BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1, | ||
| 1445 | -1, -1, -1, -1), | ||
| 1446 | BM(T6_5210_5210, T2_5250_5290, T6_5760_5800, -1, -1, -1, -1, -1, | ||
| 1447 | -1, -1, -1, -1), | ||
| 1448 | BM(T1_5200_5240, T2_5280_5280, T7_5765_5805, -1, -1, -1, -1, -1, | ||
| 1449 | -1, -1, -1, -1), | ||
| 1450 | BMZERO, | ||
| 1451 | BMZERO, | ||
| 1452 | BMZERO}, | ||
| 1453 | |||
| 1454 | {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1455 | BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1, | ||
| 1456 | -1, -1, -1, -1), | ||
| 1457 | BM(T7_5210_5210, T3_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, | ||
| 1458 | -1, -1, -1, -1), | ||
| 1459 | BM(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805, -1, -1, | ||
| 1460 | -1, -1, -1, -1, -1, -1), | ||
| 1461 | BMZERO, | ||
| 1462 | BMZERO, | ||
| 1463 | BMZERO}, | ||
| 1464 | |||
| 1465 | {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, | ||
| 1466 | BM(F2_5180_5240, F3_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1, | ||
| 1467 | -1, -1, -1, -1, -1, -1), | ||
| 1468 | BM(T6_5210_5210, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1469 | -1), | ||
| 1470 | BM(T4_5200_5200, T8_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1471 | -1), | ||
| 1472 | BMZERO, | ||
| 1473 | BMZERO, | ||
| 1474 | BMZERO}, | ||
| 1475 | |||
| 1476 | {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, | ||
| 1477 | BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1, | ||
| 1478 | -1, -1, -1, -1), | ||
| 1479 | BM(T8_5210_5210, T4_5250_5290, T7_5760_5800, -1, -1, -1, -1, -1, | ||
| 1480 | -1, -1, -1, -1), | ||
| 1481 | BM(T1_5200_5240, T1_5280_5280, T9_5765_5805, -1, -1, -1, -1, -1, | ||
| 1482 | -1, -1, -1, -1), | ||
| 1483 | BMZERO, | ||
| 1484 | BMZERO, | ||
| 1485 | BMZERO}, | ||
| 1486 | |||
| 1487 | {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1488 | BM(F2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1489 | -1), | ||
| 1490 | BM(T6_5210_5210, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1491 | -1), | ||
| 1492 | BM(T8_5200_5200, T7_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1493 | -1), | ||
| 1494 | BMZERO, | ||
| 1495 | BMZERO, | ||
| 1496 | BMZERO}, | ||
| 1497 | |||
| 1498 | {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ, | ||
| 1499 | BM(F8_5180_5240, F5_5260_5320, F1_5500_5580, F1_5660_5700, | ||
| 1500 | F6_5745_5825, -1, -1, -1, -1, -1, -1, -1), | ||
| 1501 | BM(T7_5210_5210, T3_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, | ||
| 1502 | -1, -1, -1, -1), | ||
| 1503 | BM(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805, -1, -1, | ||
| 1504 | -1, -1, -1, -1, -1, -1), | ||
| 1505 | BMZERO, | ||
| 1506 | BMZERO, | ||
| 1507 | BMZERO}, | ||
| 1508 | |||
| 1509 | {MKK1, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, | ||
| 1510 | BM(F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, | ||
| 1511 | -1, -1, -1, -1, -1, -1), | ||
| 1512 | BM(T7_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1513 | BM(T5_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1514 | BMZERO, | ||
| 1515 | BMZERO, | ||
| 1516 | BMZERO}, | ||
| 1517 | |||
| 1518 | {MKK2, MKK, NO_DFS, PSCAN_MKK2, DISALLOW_ADHOC_11A_TURB, | ||
| 1519 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1520 | F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240, | ||
| 1521 | F2_5260_5320, F4_5500_5700, -1, -1), | ||
| 1522 | BM(T7_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1523 | BM(T5_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1524 | BMZERO, | ||
| 1525 | BMZERO, | ||
| 1526 | BMZERO}, | ||
| 1527 | |||
| 1528 | |||
| 1529 | {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, | ||
| 1530 | BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1531 | BM(T9_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1532 | BM(T1_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1533 | BMZERO, | ||
| 1534 | BMZERO, | ||
| 1535 | BMZERO}, | ||
| 1536 | |||
| 1537 | |||
| 1538 | {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, | ||
| 1539 | BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1540 | -1), | ||
| 1541 | BM(T10_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1542 | BM(T6_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1543 | BMZERO, | ||
| 1544 | BMZERO, | ||
| 1545 | BMZERO}, | ||
| 1546 | |||
| 1547 | |||
| 1548 | {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, | ||
| 1549 | BM(F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, | ||
| 1550 | -1, -1, -1, -1), | ||
| 1551 | BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1552 | BM(T5_5200_5280, T3_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1553 | -1), | ||
| 1554 | BMZERO, | ||
| 1555 | BMZERO, | ||
| 1556 | BMZERO}, | ||
| 1557 | |||
| 1558 | |||
| 1559 | {MKK6, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, | ||
| 1560 | BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1561 | -1), | ||
| 1562 | BM(T3_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1563 | BM(T6_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1564 | BMZERO, | ||
| 1565 | BMZERO, | ||
| 1566 | BMZERO}, | ||
| 1567 | |||
| 1568 | |||
| 1569 | {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, | ||
| 1570 | DISALLOW_ADHOC_11A_TURB, | ||
| 1571 | BM(F1_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, | ||
| 1572 | -1, -1, -1, -1), | ||
| 1573 | BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1574 | BM(T5_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1575 | BMZERO, | ||
| 1576 | BMZERO, | ||
| 1577 | BMZERO}, | ||
| 1578 | |||
| 1579 | |||
| 1580 | {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, | ||
| 1581 | DISALLOW_ADHOC_11A_TURB, | ||
| 1582 | BM(F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, | ||
| 1583 | -1, -1, -1, -1, -1, -1), | ||
| 1584 | BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1585 | BM(T5_5200_5280, T3_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1586 | -1), | ||
| 1587 | BMZERO, | ||
| 1588 | BMZERO, | ||
| 1589 | BMZERO}, | ||
| 1590 | |||
| 1591 | |||
| 1592 | {MKK9, MKK, NO_DFS, PSCAN_MKK2 | PSCAN_MKK3, | ||
| 1593 | DISALLOW_ADHOC_11A_TURB, | ||
| 1594 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1595 | F1_5055_5055, F1_5040_5080, F4_5180_5240, -1, -1, -1, -1, -1), | ||
| 1596 | BM(T9_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1597 | BM(T1_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1598 | BMZERO, | ||
| 1599 | BMZERO, | ||
| 1600 | BMZERO}, | ||
| 1601 | |||
| 1602 | |||
| 1603 | {MKK10, MKK, DFS_MKK4, PSCAN_MKK2 | PSCAN_MKK3, | ||
| 1604 | DISALLOW_ADHOC_11A_TURB, | ||
| 1605 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1606 | F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, -1, -1, | ||
| 1607 | -1, -1), | ||
| 1608 | BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1609 | BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1610 | BMZERO, | ||
| 1611 | BMZERO, | ||
| 1612 | BMZERO}, | ||
| 1613 | |||
| 1614 | |||
| 1615 | {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, | ||
| 1616 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1617 | F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, | ||
| 1618 | F4_5500_5700, -1, -1, -1), | ||
| 1619 | BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1620 | BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1621 | BMZERO, | ||
| 1622 | BMZERO, | ||
| 1623 | BMZERO}, | ||
| 1624 | |||
| 1625 | |||
| 1626 | {MKK12, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, | ||
| 1627 | DISALLOW_ADHOC_11A_TURB, | ||
| 1628 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1629 | F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240, | ||
| 1630 | F2_5260_5320, F4_5500_5700, -1, -1), | ||
| 1631 | BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1632 | BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1633 | BMZERO, | ||
| 1634 | BMZERO, | ||
| 1635 | BMZERO}, | ||
| 1636 | |||
| 1637 | |||
| 1638 | {MKK13, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, | ||
| 1639 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1640 | BM(F1_5170_5230, F7_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, | ||
| 1641 | -1, -1, -1, -1, -1, -1), | ||
| 1642 | BMZERO, | ||
| 1643 | BMZERO, | ||
| 1644 | BMZERO, | ||
| 1645 | BMZERO, | ||
| 1646 | BMZERO}, | ||
| 1647 | |||
| 1648 | |||
| 1649 | {MKK14, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, | ||
| 1650 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1651 | F1_5040_5080, F1_5055_5055, F1_5170_5230, F4_5180_5240, -1, -1, | ||
| 1652 | -1, -1), | ||
| 1653 | BMZERO, | ||
| 1654 | BMZERO, | ||
| 1655 | BMZERO, | ||
| 1656 | BMZERO, | ||
| 1657 | BMZERO}, | ||
| 1658 | |||
| 1659 | |||
| 1660 | {MKK15, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, | ||
| 1661 | BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, | ||
| 1662 | F1_5040_5080, F1_5055_5055, F1_5170_5230, F4_5180_5240, | ||
| 1663 | F2_5260_5320, -1, -1, -1), | ||
| 1664 | BMZERO, | ||
| 1665 | BMZERO, | ||
| 1666 | BMZERO, | ||
| 1667 | BMZERO, | ||
| 1668 | BMZERO}, | ||
| 1669 | |||
| 1670 | |||
| 1671 | {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1672 | BMZERO, | ||
| 1673 | BMZERO, | ||
| 1674 | BMZERO, | ||
| 1675 | BM(F2_2312_2372, F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1676 | -1), | ||
| 1677 | BM(G2_2312_2372, G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1678 | -1), | ||
| 1679 | BMZERO}, | ||
| 1680 | |||
| 1681 | {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA, | ||
| 1682 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1683 | BMZERO, | ||
| 1684 | BMZERO, | ||
| 1685 | BMZERO, | ||
| 1686 | BM(F1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1687 | BM(G1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1688 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1689 | |||
| 1690 | {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB, | ||
| 1691 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1692 | BMZERO, | ||
| 1693 | BMZERO, | ||
| 1694 | BMZERO, | ||
| 1695 | BM(F1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1696 | BM(G1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1697 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1698 | |||
| 1699 | {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC, | ||
| 1700 | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, | ||
| 1701 | BMZERO, | ||
| 1702 | BMZERO, | ||
| 1703 | BMZERO, | ||
| 1704 | BM(F3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1705 | BM(G3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1706 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1707 | |||
| 1708 | {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1709 | BMZERO, | ||
| 1710 | BMZERO, | ||
| 1711 | BMZERO, | ||
| 1712 | BM(F1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1713 | BM(G1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1714 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1715 | |||
| 1716 | {MKKA, MKK, NO_DFS, | ||
| 1717 | PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G | | ||
| 1718 | PSCAN_MKKA2 | PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB, | ||
| 1719 | BMZERO, | ||
| 1720 | BMZERO, | ||
| 1721 | BMZERO, | ||
| 1722 | BM(F2_2412_2462, F1_2467_2472, F2_2484_2484, -1, -1, -1, -1, -1, | ||
| 1723 | -1, -1, -1, -1), | ||
| 1724 | BM(G2_2412_2462, G1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1725 | -1), | ||
| 1726 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1727 | |||
| 1728 | {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1729 | BMZERO, | ||
| 1730 | BMZERO, | ||
| 1731 | BMZERO, | ||
| 1732 | BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1733 | BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1734 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1735 | |||
| 1736 | {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1737 | BMZERO, | ||
| 1738 | BMZERO, | ||
| 1739 | BMZERO, | ||
| 1740 | BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1741 | BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1742 | BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1743 | |||
| 1744 | {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, | ||
| 1745 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, | ||
| 1746 | W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), | ||
| 1747 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1748 | -1, -1, -1, -1, -1), | ||
| 1749 | BMZERO, | ||
| 1750 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1751 | W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, | ||
| 1752 | -1, -1), | ||
| 1753 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1754 | -1, -1), | ||
| 1755 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1756 | |||
| 1757 | {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, | ||
| 1758 | ADHOC_PER_11D, | ||
| 1759 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, | ||
| 1760 | W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), | ||
| 1761 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1762 | -1, -1, -1, -1, -1), | ||
| 1763 | BMZERO, | ||
| 1764 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, | ||
| 1765 | W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), | ||
| 1766 | BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1767 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1768 | |||
| 1769 | {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, | ||
| 1770 | ADHOC_PER_11D, | ||
| 1771 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, | ||
| 1772 | W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), | ||
| 1773 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1774 | -1, -1, -1, -1, -1), | ||
| 1775 | BMZERO, | ||
| 1776 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1777 | W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), | ||
| 1778 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1779 | -1, -1), | ||
| 1780 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1781 | |||
| 1782 | {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, | ||
| 1783 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, | ||
| 1784 | W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), | ||
| 1785 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1786 | -1, -1, -1, -1, -1), | ||
| 1787 | BMZERO, | ||
| 1788 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, | ||
| 1789 | W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1), | ||
| 1790 | BM(WG1_2412_2462, WG2_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1791 | -1, -1), | ||
| 1792 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1793 | |||
| 1794 | {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1795 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, | ||
| 1796 | W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), | ||
| 1797 | BMZERO, | ||
| 1798 | BMZERO, | ||
| 1799 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1800 | W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, | ||
| 1801 | -1, -1), | ||
| 1802 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1803 | -1, -1), | ||
| 1804 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1805 | |||
| 1806 | {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1807 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, | ||
| 1808 | W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), | ||
| 1809 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1810 | -1, -1, -1, -1, -1), | ||
| 1811 | BMZERO, | ||
| 1812 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1813 | W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, | ||
| 1814 | -1, -1), | ||
| 1815 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1816 | -1, -1), | ||
| 1817 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1818 | |||
| 1819 | {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, | ||
| 1820 | BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1, | ||
| 1821 | -1, -1, -1, -1, -1, -1), | ||
| 1822 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1823 | -1, -1, -1, -1, -1), | ||
| 1824 | BMZERO, | ||
| 1825 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1826 | W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), | ||
| 1827 | BM(WG1_2412_2462, WG2_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1828 | -1, -1), | ||
| 1829 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1830 | |||
| 1831 | {WOR4_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1832 | BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, -1, -1, -1, -1, -1, | ||
| 1833 | -1, -1, -1, -1), | ||
| 1834 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1835 | -1, -1, -1, -1, -1), | ||
| 1836 | BMZERO, | ||
| 1837 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, | ||
| 1838 | W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), | ||
| 1839 | BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1840 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1841 | |||
| 1842 | {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1843 | BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, -1, -1, -1, -1, -1, | ||
| 1844 | -1, -1, -1, -1), | ||
| 1845 | BMZERO, | ||
| 1846 | BMZERO, | ||
| 1847 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1848 | W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), | ||
| 1849 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1850 | -1, -1), | ||
| 1851 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1852 | |||
| 1853 | {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1854 | BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, | ||
| 1855 | -1, -1, -1, -1, -1, -1), | ||
| 1856 | BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, | ||
| 1857 | -1, -1, -1, -1, -1), | ||
| 1858 | BMZERO, | ||
| 1859 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, | ||
| 1860 | W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), | ||
| 1861 | BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), | ||
| 1862 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1863 | |||
| 1864 | {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1865 | BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, | ||
| 1866 | -1, -1, -1, -1, -1, -1), | ||
| 1867 | BMZERO, | ||
| 1868 | BMZERO, | ||
| 1869 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1870 | W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), | ||
| 1871 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1872 | -1, -1), | ||
| 1873 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1874 | |||
| 1875 | {WORB_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, | ||
| 1876 | BM(W1_5260_5320, W1_5180_5240, W1_5500_5700, -1, -1, -1, -1, -1, | ||
| 1877 | -1, -1, -1, -1), | ||
| 1878 | BMZERO, | ||
| 1879 | BMZERO, | ||
| 1880 | BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, | ||
| 1881 | W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), | ||
| 1882 | BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, | ||
| 1883 | -1, -1), | ||
| 1884 | BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, | ||
| 1885 | |||
| 1886 | {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, | ||
| 1887 | BMZERO, | ||
| 1888 | BMZERO, | ||
| 1889 | BMZERO, | ||
| 1890 | BMZERO, | ||
| 1891 | BMZERO, | ||
| 1892 | BMZERO} | ||
| 1893 | }; | ||
| 1894 | |||
| 1895 | static const struct cmode modes[] = { | ||
| 1896 | {ATH9K_MODE_11A, CHANNEL_A}, | ||
| 1897 | {ATH9K_MODE_11B, CHANNEL_B}, | ||
| 1898 | {ATH9K_MODE_11G, CHANNEL_G}, | ||
| 1899 | {ATH9K_MODE_11NG_HT20, CHANNEL_G_HT20}, | ||
| 1900 | {ATH9K_MODE_11NG_HT40PLUS, CHANNEL_G_HT40PLUS}, | ||
| 1901 | {ATH9K_MODE_11NG_HT40MINUS, CHANNEL_G_HT40MINUS}, | ||
| 1902 | {ATH9K_MODE_11NA_HT20, CHANNEL_A_HT20}, | ||
| 1903 | {ATH9K_MODE_11NA_HT40PLUS, CHANNEL_A_HT40PLUS}, | ||
| 1904 | {ATH9K_MODE_11NA_HT40MINUS, CHANNEL_A_HT40MINUS}, | ||
| 1905 | }; | ||
| 1906 | |||
| 1907 | static struct japan_bandcheck j_bandcheck[] = { | ||
| 1908 | {F1_5170_5230, AR_EEPROM_EEREGCAP_EN_KK_U1_ODD}, | ||
| 1909 | {F4_5180_5240, AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN}, | ||
| 1910 | {F2_5260_5320, AR_EEPROM_EEREGCAP_EN_KK_U2}, | ||
| 1911 | {F4_5500_5700, AR_EEPROM_EEREGCAP_EN_KK_MIDBAND} | ||
| 1912 | }; | ||
| 1913 | |||
| 1914 | |||
| 1915 | #endif | ||
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c new file mode 100644 index 000000000000..157f830ee6b8 --- /dev/null +++ b/drivers/net/wireless/ath9k/xmit.c | |||
| @@ -0,0 +1,2871 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2008 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Implementation of transmit path. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include "core.h" | ||
| 22 | |||
| 23 | #define BITS_PER_BYTE 8 | ||
| 24 | #define OFDM_PLCP_BITS 22 | ||
| 25 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | ||
| 26 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | ||
| 27 | #define L_STF 8 | ||
| 28 | #define L_LTF 8 | ||
| 29 | #define L_SIG 4 | ||
| 30 | #define HT_SIG 8 | ||
| 31 | #define HT_STF 4 | ||
| 32 | #define HT_LTF(_ns) (4 * (_ns)) | ||
| 33 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | ||
| 34 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | ||
| 35 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | ||
| 36 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | ||
| 37 | |||
| 38 | #define OFDM_SIFS_TIME 16 | ||
| 39 | |||
| 40 | static u32 bits_per_symbol[][2] = { | ||
| 41 | /* 20MHz 40MHz */ | ||
| 42 | { 26, 54 }, /* 0: BPSK */ | ||
| 43 | { 52, 108 }, /* 1: QPSK 1/2 */ | ||
| 44 | { 78, 162 }, /* 2: QPSK 3/4 */ | ||
| 45 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | ||
| 46 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | ||
| 47 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | ||
| 48 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | ||
| 49 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | ||
| 50 | { 52, 108 }, /* 8: BPSK */ | ||
| 51 | { 104, 216 }, /* 9: QPSK 1/2 */ | ||
| 52 | { 156, 324 }, /* 10: QPSK 3/4 */ | ||
| 53 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | ||
| 54 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | ||
| 55 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | ||
| 56 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | ||
| 57 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | ||
| 58 | }; | ||
| 59 | |||
| 60 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Insert a chain of ath_buf (descriptors) on a multicast txq | ||
| 64 | * but do NOT start tx DMA on this queue. | ||
| 65 | * NB: must be called with txq lock held | ||
| 66 | */ | ||
| 67 | |||
| 68 | static void ath_tx_mcastqaddbuf(struct ath_softc *sc, | ||
| 69 | struct ath_txq *txq, | ||
| 70 | struct list_head *head) | ||
| 71 | { | ||
| 72 | struct ath_hal *ah = sc->sc_ah; | ||
| 73 | struct ath_buf *bf; | ||
| 74 | |||
| 75 | if (list_empty(head)) | ||
| 76 | return; | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Insert the frame on the outbound list and | ||
| 80 | * pass it on to the hardware. | ||
| 81 | */ | ||
| 82 | bf = list_first_entry(head, struct ath_buf, list); | ||
| 83 | |||
| 84 | /* | ||
| 85 | * The CAB queue is started from the SWBA handler since | ||
| 86 | * frames only go out on DTIM and to avoid possible races. | ||
| 87 | */ | ||
| 88 | ath9k_hw_set_interrupts(ah, 0); | ||
| 89 | |||
| 90 | /* | ||
| 91 | * If there is anything in the mcastq, we want to set | ||
| 92 | * the "more data" bit in the last item in the queue to | ||
| 93 | * indicate that there is "more data". It makes sense to add | ||
| 94 | * it here since you are *always* going to have | ||
| 95 | * more data when adding to this queue, no matter where | ||
| 96 | * you call from. | ||
| 97 | */ | ||
| 98 | |||
| 99 | if (txq->axq_depth) { | ||
| 100 | struct ath_buf *lbf; | ||
| 101 | struct ieee80211_hdr *hdr; | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Add the "more data flag" to the last frame | ||
| 105 | */ | ||
| 106 | |||
| 107 | lbf = list_entry(txq->axq_q.prev, struct ath_buf, list); | ||
| 108 | hdr = (struct ieee80211_hdr *) | ||
| 109 | ((struct sk_buff *)(lbf->bf_mpdu))->data; | ||
| 110 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); | ||
| 111 | } | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Now, concat the frame onto the queue | ||
| 115 | */ | ||
| 116 | list_splice_tail_init(head, &txq->axq_q); | ||
| 117 | txq->axq_depth++; | ||
| 118 | txq->axq_totalqueued++; | ||
| 119 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | ||
| 120 | |||
| 121 | DPRINTF(sc, ATH_DBG_QUEUE, | ||
| 122 | "%s: txq depth = %d\n", __func__, txq->axq_depth); | ||
| 123 | if (txq->axq_link != NULL) { | ||
| 124 | *txq->axq_link = bf->bf_daddr; | ||
| 125 | DPRINTF(sc, ATH_DBG_XMIT, | ||
| 126 | "%s: link[%u](%p)=%llx (%p)\n", | ||
| 127 | __func__, | ||
| 128 | txq->axq_qnum, txq->axq_link, | ||
| 129 | ito64(bf->bf_daddr), bf->bf_desc); | ||
| 130 | } | ||
| 131 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | ||
| 132 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | ||
| 133 | } | ||
| 134 | |||
| 135 | /* | ||
| 136 | * Insert a chain of ath_buf (descriptors) on a txq and | ||
| 137 | * assume the descriptors are already chained together by caller. | ||
| 138 | * NB: must be called with txq lock held | ||
| 139 | */ | ||
| 140 | |||
| 141 | static void ath_tx_txqaddbuf(struct ath_softc *sc, | ||
| 142 | struct ath_txq *txq, struct list_head *head) | ||
| 143 | { | ||
| 144 | struct ath_hal *ah = sc->sc_ah; | ||
| 145 | struct ath_buf *bf; | ||
| 146 | /* | ||
| 147 | * Insert the frame on the outbound list and | ||
| 148 | * pass it on to the hardware. | ||
| 149 | */ | ||
| 150 | |||
| 151 | if (list_empty(head)) | ||
| 152 | return; | ||
| 153 | |||
| 154 | bf = list_first_entry(head, struct ath_buf, list); | ||
| 155 | |||
| 156 | list_splice_tail_init(head, &txq->axq_q); | ||
| 157 | txq->axq_depth++; | ||
| 158 | txq->axq_totalqueued++; | ||
| 159 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | ||
| 160 | |||
| 161 | DPRINTF(sc, ATH_DBG_QUEUE, | ||
| 162 | "%s: txq depth = %d\n", __func__, txq->axq_depth); | ||
| 163 | |||
| 164 | if (txq->axq_link == NULL) { | ||
| 165 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | ||
| 166 | DPRINTF(sc, ATH_DBG_XMIT, | ||
| 167 | "%s: TXDP[%u] = %llx (%p)\n", | ||
| 168 | __func__, txq->axq_qnum, | ||
| 169 | ito64(bf->bf_daddr), bf->bf_desc); | ||
| 170 | } else { | ||
| 171 | *txq->axq_link = bf->bf_daddr; | ||
| 172 | DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n", | ||
| 173 | __func__, | ||
| 174 | txq->axq_qnum, txq->axq_link, | ||
| 175 | ito64(bf->bf_daddr), bf->bf_desc); | ||
| 176 | } | ||
| 177 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | ||
| 178 | ath9k_hw_txstart(ah, txq->axq_qnum); | ||
| 179 | } | ||
| 180 | |||
| 181 | /* Get transmit rate index using rate in Kbps */ | ||
| 182 | |||
| 183 | static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate) | ||
| 184 | { | ||
| 185 | int i; | ||
| 186 | int ndx = 0; | ||
| 187 | |||
| 188 | for (i = 0; i < rt->rateCount; i++) { | ||
| 189 | if (rt->info[i].rateKbps == rate) { | ||
| 190 | ndx = i; | ||
| 191 | break; | ||
| 192 | } | ||
| 193 | } | ||
| 194 | |||
| 195 | return ndx; | ||
| 196 | } | ||
| 197 | |||
| 198 | /* Check if it's okay to send out aggregates */ | ||
| 199 | |||
| 200 | static int ath_aggr_query(struct ath_softc *sc, | ||
| 201 | struct ath_node *an, u8 tidno) | ||
| 202 | { | ||
| 203 | struct ath_atx_tid *tid; | ||
| 204 | tid = ATH_AN_2_TID(an, tidno); | ||
| 205 | |||
| 206 | if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress) | ||
| 207 | return 1; | ||
| 208 | else | ||
| 209 | return 0; | ||
| 210 | } | ||
| 211 | |||
| 212 | static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr) | ||
| 213 | { | ||
| 214 | enum ath9k_pkt_type htype; | ||
| 215 | __le16 fc; | ||
| 216 | |||
| 217 | fc = hdr->frame_control; | ||
| 218 | |||
| 219 | /* Calculate Atheros packet type from IEEE80211 packet header */ | ||
| 220 | |||
| 221 | if (ieee80211_is_beacon(fc)) | ||
| 222 | htype = ATH9K_PKT_TYPE_BEACON; | ||
| 223 | else if (ieee80211_is_probe_resp(fc)) | ||
| 224 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | ||
| 225 | else if (ieee80211_is_atim(fc)) | ||
| 226 | htype = ATH9K_PKT_TYPE_ATIM; | ||
| 227 | else if (ieee80211_is_pspoll(fc)) | ||
| 228 | htype = ATH9K_PKT_TYPE_PSPOLL; | ||
| 229 | else | ||
| 230 | htype = ATH9K_PKT_TYPE_NORMAL; | ||
| 231 | |||
| 232 | return htype; | ||
| 233 | } | ||
| 234 | |||
| 235 | static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl) | ||
| 236 | { | ||
| 237 | struct ieee80211_hdr *hdr; | ||
| 238 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 239 | struct ath_tx_info_priv *tx_info_priv; | ||
| 240 | __le16 fc; | ||
| 241 | |||
| 242 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 243 | fc = hdr->frame_control; | ||
| 244 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 245 | |||
| 246 | if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) { | ||
| 247 | txctl->use_minrate = 1; | ||
| 248 | txctl->min_rate = tx_info_priv->min_rate; | ||
| 249 | } else if (ieee80211_is_data(fc)) { | ||
| 250 | if (ieee80211_is_nullfunc(fc) || | ||
| 251 | /* Port Access Entity (IEEE 802.1X) */ | ||
| 252 | (skb->protocol == cpu_to_be16(0x888E))) { | ||
| 253 | txctl->use_minrate = 1; | ||
| 254 | txctl->min_rate = tx_info_priv->min_rate; | ||
| 255 | } | ||
| 256 | if (is_multicast_ether_addr(hdr->addr1)) | ||
| 257 | txctl->mcast_rate = tx_info_priv->min_rate; | ||
| 258 | } | ||
| 259 | |||
| 260 | } | ||
| 261 | |||
| 262 | /* This function will setup additional txctl information, mostly rate stuff */ | ||
| 263 | /* FIXME: seqno, ps */ | ||
| 264 | static int ath_tx_prepare(struct ath_softc *sc, | ||
| 265 | struct sk_buff *skb, | ||
| 266 | struct ath_tx_control *txctl) | ||
| 267 | { | ||
| 268 | struct ieee80211_hw *hw = sc->hw; | ||
| 269 | struct ieee80211_hdr *hdr; | ||
| 270 | struct ath_rc_series *rcs; | ||
| 271 | struct ath_txq *txq = NULL; | ||
| 272 | const struct ath9k_rate_table *rt; | ||
| 273 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 274 | struct ath_tx_info_priv *tx_info_priv; | ||
| 275 | int hdrlen; | ||
| 276 | u8 rix, antenna; | ||
| 277 | __le16 fc; | ||
| 278 | u8 *qc; | ||
| 279 | |||
| 280 | memset(txctl, 0, sizeof(struct ath_tx_control)); | ||
| 281 | |||
| 282 | txctl->dev = sc; | ||
| 283 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 284 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | ||
| 285 | fc = hdr->frame_control; | ||
| 286 | |||
| 287 | rt = sc->sc_currates; | ||
| 288 | BUG_ON(!rt); | ||
| 289 | |||
| 290 | /* Fill misc fields */ | ||
| 291 | |||
| 292 | spin_lock_bh(&sc->node_lock); | ||
| 293 | txctl->an = ath_node_get(sc, hdr->addr1); | ||
| 294 | /* create a temp node, if the node is not there already */ | ||
| 295 | if (!txctl->an) | ||
| 296 | txctl->an = ath_node_attach(sc, hdr->addr1, 0); | ||
| 297 | spin_unlock_bh(&sc->node_lock); | ||
| 298 | |||
| 299 | if (ieee80211_is_data_qos(fc)) { | ||
| 300 | qc = ieee80211_get_qos_ctl(hdr); | ||
| 301 | txctl->tidno = qc[0] & 0xf; | ||
| 302 | } | ||
| 303 | |||
| 304 | txctl->if_id = 0; | ||
| 305 | txctl->nextfraglen = 0; | ||
| 306 | txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3); | ||
| 307 | txctl->txpower = MAX_RATE_POWER; /* FIXME */ | ||
| 308 | |||
| 309 | /* Fill Key related fields */ | ||
| 310 | |||
| 311 | txctl->keytype = ATH9K_KEY_TYPE_CLEAR; | ||
| 312 | txctl->keyix = ATH9K_TXKEYIX_INVALID; | ||
| 313 | |||
| 314 | if (tx_info->control.hw_key) { | ||
| 315 | txctl->keyix = tx_info->control.hw_key->hw_key_idx; | ||
| 316 | txctl->frmlen += tx_info->control.icv_len; | ||
| 317 | |||
| 318 | if (sc->sc_keytype == ATH9K_CIPHER_WEP) | ||
| 319 | txctl->keytype = ATH9K_KEY_TYPE_WEP; | ||
| 320 | else if (sc->sc_keytype == ATH9K_CIPHER_TKIP) | ||
| 321 | txctl->keytype = ATH9K_KEY_TYPE_TKIP; | ||
| 322 | else if (sc->sc_keytype == ATH9K_CIPHER_AES_CCM) | ||
| 323 | txctl->keytype = ATH9K_KEY_TYPE_AES; | ||
| 324 | } | ||
| 325 | |||
| 326 | /* Fill packet type */ | ||
| 327 | |||
| 328 | txctl->atype = get_hal_packet_type(hdr); | ||
| 329 | |||
| 330 | /* Fill qnum */ | ||
| 331 | |||
| 332 | txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); | ||
| 333 | txq = &sc->sc_txq[txctl->qnum]; | ||
| 334 | spin_lock_bh(&txq->axq_lock); | ||
| 335 | |||
| 336 | /* Try to avoid running out of descriptors */ | ||
| 337 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | ||
| 338 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 339 | "%s: TX queue: %d is full, depth: %d\n", | ||
| 340 | __func__, | ||
| 341 | txctl->qnum, | ||
| 342 | txq->axq_depth); | ||
| 343 | ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); | ||
| 344 | txq->stopped = 1; | ||
| 345 | spin_unlock_bh(&txq->axq_lock); | ||
| 346 | return -1; | ||
| 347 | } | ||
| 348 | |||
| 349 | spin_unlock_bh(&txq->axq_lock); | ||
| 350 | |||
| 351 | /* Fill rate */ | ||
| 352 | |||
| 353 | fill_min_rates(skb, txctl); | ||
| 354 | |||
| 355 | /* Fill flags */ | ||
| 356 | |||
| 357 | txctl->flags = ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | ||
| 358 | |||
| 359 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | ||
| 360 | tx_info->flags |= ATH9K_TXDESC_NOACK; | ||
| 361 | if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) | ||
| 362 | tx_info->flags |= ATH9K_TXDESC_RTSENA; | ||
| 363 | |||
| 364 | /* | ||
| 365 | * Setup for rate calculations. | ||
| 366 | */ | ||
| 367 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 368 | rcs = tx_info_priv->rcs; | ||
| 369 | |||
| 370 | if (ieee80211_is_data(fc) && !txctl->use_minrate) { | ||
| 371 | |||
| 372 | /* Enable HT only for DATA frames and not for EAPOL */ | ||
| 373 | txctl->ht = (hw->conf.ht_conf.ht_supported && | ||
| 374 | (tx_info->flags & IEEE80211_TX_CTL_AMPDU)); | ||
| 375 | |||
| 376 | if (is_multicast_ether_addr(hdr->addr1)) { | ||
| 377 | rcs[0].rix = (u8) | ||
| 378 | ath_tx_findindex(rt, txctl->mcast_rate); | ||
| 379 | |||
| 380 | /* | ||
| 381 | * mcast packets are not re-tried. | ||
| 382 | */ | ||
| 383 | rcs[0].tries = 1; | ||
| 384 | } | ||
| 385 | /* For HT capable stations, we save tidno for later use. | ||
| 386 | * We also override seqno set by upper layer with the one | ||
| 387 | * in tx aggregation state. | ||
| 388 | * | ||
| 389 | * First, the fragmentation stat is determined. | ||
| 390 | * If fragmentation is on, the sequence number is | ||
| 391 | * not overridden, since it has been | ||
| 392 | * incremented by the fragmentation routine. | ||
| 393 | */ | ||
| 394 | if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) && | ||
| 395 | txctl->ht && sc->sc_txaggr) { | ||
| 396 | struct ath_atx_tid *tid; | ||
| 397 | |||
| 398 | tid = ATH_AN_2_TID(txctl->an, txctl->tidno); | ||
| 399 | |||
| 400 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | ||
| 401 | IEEE80211_SEQ_SEQ_SHIFT); | ||
| 402 | txctl->seqno = tid->seq_next; | ||
| 403 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | ||
| 404 | } | ||
| 405 | } else { | ||
| 406 | /* for management and control frames, | ||
| 407 | * or for NULL and EAPOL frames */ | ||
| 408 | if (txctl->min_rate) | ||
| 409 | rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate); | ||
| 410 | else | ||
| 411 | rcs[0].rix = 0; | ||
| 412 | rcs[0].tries = ATH_MGT_TXMAXTRY; | ||
| 413 | } | ||
| 414 | rix = rcs[0].rix; | ||
| 415 | |||
| 416 | /* | ||
| 417 | * Calculate duration. This logically belongs in the 802.11 | ||
| 418 | * layer but it lacks sufficient information to calculate it. | ||
| 419 | */ | ||
| 420 | if ((txctl->flags & ATH9K_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) { | ||
| 421 | u16 dur; | ||
| 422 | /* | ||
| 423 | * XXX not right with fragmentation. | ||
| 424 | */ | ||
| 425 | if (sc->sc_flags & ATH_PREAMBLE_SHORT) | ||
| 426 | dur = rt->info[rix].spAckDuration; | ||
| 427 | else | ||
| 428 | dur = rt->info[rix].lpAckDuration; | ||
| 429 | |||
| 430 | if (le16_to_cpu(hdr->frame_control) & | ||
| 431 | IEEE80211_FCTL_MOREFRAGS) { | ||
| 432 | dur += dur; /* Add additional 'SIFS + ACK' */ | ||
| 433 | |||
| 434 | /* | ||
| 435 | ** Compute size of next fragment in order to compute | ||
| 436 | ** durations needed to update NAV. | ||
| 437 | ** The last fragment uses the ACK duration only. | ||
| 438 | ** Add time for next fragment. | ||
| 439 | */ | ||
| 440 | dur += ath9k_hw_computetxtime(sc->sc_ah, rt, | ||
| 441 | txctl->nextfraglen, | ||
| 442 | rix, sc->sc_flags & ATH_PREAMBLE_SHORT); | ||
| 443 | } | ||
| 444 | |||
| 445 | if (ieee80211_has_morefrags(fc) || | ||
| 446 | (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) { | ||
| 447 | /* | ||
| 448 | ** Force hardware to use computed duration for next | ||
| 449 | ** fragment by disabling multi-rate retry, which | ||
| 450 | ** updates duration based on the multi-rate | ||
| 451 | ** duration table. | ||
| 452 | */ | ||
| 453 | rcs[1].tries = rcs[2].tries = rcs[3].tries = 0; | ||
| 454 | rcs[1].rix = rcs[2].rix = rcs[3].rix = 0; | ||
| 455 | /* reset tries but keep rate index */ | ||
| 456 | rcs[0].tries = ATH_TXMAXTRY; | ||
| 457 | } | ||
| 458 | |||
| 459 | hdr->duration_id = cpu_to_le16(dur); | ||
| 460 | } | ||
| 461 | |||
| 462 | /* | ||
| 463 | * Determine if a tx interrupt should be generated for | ||
| 464 | * this descriptor. We take a tx interrupt to reap | ||
| 465 | * descriptors when the h/w hits an EOL condition or | ||
| 466 | * when the descriptor is specifically marked to generate | ||
| 467 | * an interrupt. We periodically mark descriptors in this | ||
| 468 | * way to insure timely replenishing of the supply needed | ||
| 469 | * for sending frames. Defering interrupts reduces system | ||
| 470 | * load and potentially allows more concurrent work to be | ||
| 471 | * done but if done to aggressively can cause senders to | ||
| 472 | * backup. | ||
| 473 | * | ||
| 474 | * NB: use >= to deal with sc_txintrperiod changing | ||
| 475 | * dynamically through sysctl. | ||
| 476 | */ | ||
| 477 | spin_lock_bh(&txq->axq_lock); | ||
| 478 | if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) { | ||
| 479 | txctl->flags |= ATH9K_TXDESC_INTREQ; | ||
| 480 | txq->axq_intrcnt = 0; | ||
| 481 | } | ||
| 482 | spin_unlock_bh(&txq->axq_lock); | ||
| 483 | |||
| 484 | if (is_multicast_ether_addr(hdr->addr1)) { | ||
| 485 | antenna = sc->sc_mcastantenna + 1; | ||
| 486 | sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1; | ||
| 487 | } else | ||
| 488 | antenna = sc->sc_txantenna; | ||
| 489 | |||
| 490 | #ifdef USE_LEGACY_HAL | ||
| 491 | txctl->antenna = antenna; | ||
| 492 | #endif | ||
| 493 | return 0; | ||
| 494 | } | ||
| 495 | |||
| 496 | /* To complete a chain of buffers associated a frame */ | ||
| 497 | |||
| 498 | static void ath_tx_complete_buf(struct ath_softc *sc, | ||
| 499 | struct ath_buf *bf, | ||
| 500 | struct list_head *bf_q, | ||
| 501 | int txok, int sendbar) | ||
| 502 | { | ||
| 503 | struct sk_buff *skb = bf->bf_mpdu; | ||
| 504 | struct ath_xmit_status tx_status; | ||
| 505 | dma_addr_t *pa; | ||
| 506 | |||
| 507 | /* | ||
| 508 | * Set retry information. | ||
| 509 | * NB: Don't use the information in the descriptor, because the frame | ||
| 510 | * could be software retried. | ||
| 511 | */ | ||
| 512 | tx_status.retries = bf->bf_retries; | ||
| 513 | tx_status.flags = 0; | ||
| 514 | |||
| 515 | if (sendbar) | ||
| 516 | tx_status.flags = ATH_TX_BAR; | ||
| 517 | |||
| 518 | if (!txok) { | ||
| 519 | tx_status.flags |= ATH_TX_ERROR; | ||
| 520 | |||
| 521 | if (bf->bf_isxretried) | ||
| 522 | tx_status.flags |= ATH_TX_XRETRY; | ||
| 523 | } | ||
| 524 | /* Unmap this frame */ | ||
| 525 | pa = get_dma_mem_context(bf, bf_dmacontext); | ||
| 526 | pci_unmap_single(sc->pdev, | ||
| 527 | *pa, | ||
| 528 | skb->len, | ||
| 529 | PCI_DMA_TODEVICE); | ||
| 530 | /* complete this frame */ | ||
| 531 | ath_tx_complete(sc, skb, &tx_status, bf->bf_node); | ||
| 532 | |||
| 533 | /* | ||
| 534 | * Return the list of ath_buf of this mpdu to free queue | ||
| 535 | */ | ||
| 536 | spin_lock_bh(&sc->sc_txbuflock); | ||
| 537 | list_splice_tail_init(bf_q, &sc->sc_txbuf); | ||
| 538 | spin_unlock_bh(&sc->sc_txbuflock); | ||
| 539 | } | ||
| 540 | |||
| 541 | /* | ||
| 542 | * queue up a dest/ac pair for tx scheduling | ||
| 543 | * NB: must be called with txq lock held | ||
| 544 | */ | ||
| 545 | |||
| 546 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) | ||
| 547 | { | ||
| 548 | struct ath_atx_ac *ac = tid->ac; | ||
| 549 | |||
| 550 | /* | ||
| 551 | * if tid is paused, hold off | ||
| 552 | */ | ||
| 553 | if (tid->paused) | ||
| 554 | return; | ||
| 555 | |||
| 556 | /* | ||
| 557 | * add tid to ac atmost once | ||
| 558 | */ | ||
| 559 | if (tid->sched) | ||
| 560 | return; | ||
| 561 | |||
| 562 | tid->sched = true; | ||
| 563 | list_add_tail(&tid->list, &ac->tid_q); | ||
| 564 | |||
| 565 | /* | ||
| 566 | * add node ac to txq atmost once | ||
| 567 | */ | ||
| 568 | if (ac->sched) | ||
| 569 | return; | ||
| 570 | |||
| 571 | ac->sched = true; | ||
| 572 | list_add_tail(&ac->list, &txq->axq_acq); | ||
| 573 | } | ||
| 574 | |||
| 575 | /* pause a tid */ | ||
| 576 | |||
| 577 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) | ||
| 578 | { | ||
| 579 | struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; | ||
| 580 | |||
| 581 | spin_lock_bh(&txq->axq_lock); | ||
| 582 | |||
| 583 | tid->paused++; | ||
| 584 | |||
| 585 | spin_unlock_bh(&txq->axq_lock); | ||
| 586 | } | ||
| 587 | |||
| 588 | /* resume a tid and schedule aggregate */ | ||
| 589 | |||
| 590 | void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) | ||
| 591 | { | ||
| 592 | struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; | ||
| 593 | |||
| 594 | ASSERT(tid->paused > 0); | ||
| 595 | spin_lock_bh(&txq->axq_lock); | ||
| 596 | |||
| 597 | tid->paused--; | ||
| 598 | |||
| 599 | if (tid->paused > 0) | ||
| 600 | goto unlock; | ||
| 601 | |||
| 602 | if (list_empty(&tid->buf_q)) | ||
| 603 | goto unlock; | ||
| 604 | |||
| 605 | /* | ||
| 606 | * Add this TID to scheduler and try to send out aggregates | ||
| 607 | */ | ||
| 608 | ath_tx_queue_tid(txq, tid); | ||
| 609 | ath_txq_schedule(sc, txq); | ||
| 610 | unlock: | ||
| 611 | spin_unlock_bh(&txq->axq_lock); | ||
| 612 | } | ||
| 613 | |||
| 614 | /* Compute the number of bad frames */ | ||
| 615 | |||
| 616 | static int ath_tx_num_badfrms(struct ath_softc *sc, | ||
| 617 | struct ath_buf *bf, int txok) | ||
| 618 | { | ||
| 619 | struct ath_node *an = bf->bf_node; | ||
| 620 | int isnodegone = (an->an_flags & ATH_NODE_CLEAN); | ||
| 621 | struct ath_buf *bf_last = bf->bf_lastbf; | ||
| 622 | struct ath_desc *ds = bf_last->bf_desc; | ||
| 623 | u16 seq_st = 0; | ||
| 624 | u32 ba[WME_BA_BMP_SIZE >> 5]; | ||
| 625 | int ba_index; | ||
| 626 | int nbad = 0; | ||
| 627 | int isaggr = 0; | ||
| 628 | |||
| 629 | if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) | ||
| 630 | return 0; | ||
| 631 | |||
| 632 | isaggr = bf->bf_isaggr; | ||
| 633 | if (isaggr) { | ||
| 634 | seq_st = ATH_DS_BA_SEQ(ds); | ||
| 635 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | ||
| 636 | } | ||
| 637 | |||
| 638 | while (bf) { | ||
| 639 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | ||
| 640 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | ||
| 641 | nbad++; | ||
| 642 | |||
| 643 | bf = bf->bf_next; | ||
| 644 | } | ||
| 645 | |||
| 646 | return nbad; | ||
| 647 | } | ||
| 648 | |||
| 649 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) | ||
| 650 | { | ||
| 651 | struct sk_buff *skb; | ||
| 652 | struct ieee80211_hdr *hdr; | ||
| 653 | |||
| 654 | bf->bf_isretried = 1; | ||
| 655 | bf->bf_retries++; | ||
| 656 | |||
| 657 | skb = bf->bf_mpdu; | ||
| 658 | hdr = (struct ieee80211_hdr *)skb->data; | ||
| 659 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | ||
| 660 | } | ||
| 661 | |||
| 662 | /* Update block ack window */ | ||
| 663 | |||
| 664 | static void ath_tx_update_baw(struct ath_softc *sc, | ||
| 665 | struct ath_atx_tid *tid, int seqno) | ||
| 666 | { | ||
| 667 | int index, cindex; | ||
| 668 | |||
| 669 | index = ATH_BA_INDEX(tid->seq_start, seqno); | ||
| 670 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | ||
| 671 | |||
| 672 | tid->tx_buf[cindex] = NULL; | ||
| 673 | |||
| 674 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { | ||
| 675 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | ||
| 676 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | ||
| 677 | } | ||
| 678 | } | ||
| 679 | |||
| 680 | /* | ||
| 681 | * ath_pkt_dur - compute packet duration (NB: not NAV) | ||
| 682 | * | ||
| 683 | * rix - rate index | ||
| 684 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | ||
| 685 | * width - 0 for 20 MHz, 1 for 40 MHz | ||
| 686 | * half_gi - to use 4us v/s 3.6 us for symbol time | ||
| 687 | */ | ||
| 688 | |||
| 689 | static u32 ath_pkt_duration(struct ath_softc *sc, | ||
| 690 | u8 rix, | ||
| 691 | struct ath_buf *bf, | ||
| 692 | int width, | ||
| 693 | int half_gi, | ||
| 694 | bool shortPreamble) | ||
| 695 | { | ||
| 696 | const struct ath9k_rate_table *rt = sc->sc_currates; | ||
| 697 | u32 nbits, nsymbits, duration, nsymbols; | ||
| 698 | u8 rc; | ||
| 699 | int streams, pktlen; | ||
| 700 | |||
| 701 | pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_frmlen; | ||
| 702 | rc = rt->info[rix].rateCode; | ||
| 703 | |||
| 704 | /* | ||
| 705 | * for legacy rates, use old function to compute packet duration | ||
| 706 | */ | ||
| 707 | if (!IS_HT_RATE(rc)) | ||
| 708 | return ath9k_hw_computetxtime(sc->sc_ah, | ||
| 709 | rt, | ||
| 710 | pktlen, | ||
| 711 | rix, | ||
| 712 | shortPreamble); | ||
| 713 | /* | ||
| 714 | * find number of symbols: PLCP + data | ||
| 715 | */ | ||
| 716 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | ||
| 717 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | ||
| 718 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | ||
| 719 | |||
| 720 | if (!half_gi) | ||
| 721 | duration = SYMBOL_TIME(nsymbols); | ||
| 722 | else | ||
| 723 | duration = SYMBOL_TIME_HALFGI(nsymbols); | ||
| 724 | |||
| 725 | /* | ||
| 726 | * addup duration for legacy/ht training and signal fields | ||
| 727 | */ | ||
| 728 | streams = HT_RC_2_STREAMS(rc); | ||
| 729 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | ||
| 730 | return duration; | ||
| 731 | } | ||
| 732 | |||
| 733 | /* Rate module function to set rate related fields in tx descriptor */ | ||
| 734 | |||
| 735 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | ||
| 736 | { | ||
| 737 | struct ath_hal *ah = sc->sc_ah; | ||
| 738 | const struct ath9k_rate_table *rt; | ||
| 739 | struct ath_desc *ds = bf->bf_desc; | ||
| 740 | struct ath_desc *lastds = bf->bf_lastbf->bf_desc; | ||
| 741 | struct ath9k_11n_rate_series series[4]; | ||
| 742 | int i, flags, rtsctsena = 0, dynamic_mimops = 0; | ||
| 743 | u32 ctsduration = 0; | ||
| 744 | u8 rix = 0, cix, ctsrate = 0; | ||
| 745 | u32 aggr_limit_with_rts = sc->sc_rtsaggrlimit; | ||
| 746 | struct ath_node *an = (struct ath_node *) bf->bf_node; | ||
| 747 | |||
| 748 | /* | ||
| 749 | * get the cix for the lowest valid rix. | ||
| 750 | */ | ||
| 751 | rt = sc->sc_currates; | ||
| 752 | for (i = 4; i--;) { | ||
| 753 | if (bf->bf_rcs[i].tries) { | ||
| 754 | rix = bf->bf_rcs[i].rix; | ||
| 755 | break; | ||
| 756 | } | ||
| 757 | } | ||
| 758 | flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)); | ||
| 759 | cix = rt->info[rix].controlRate; | ||
| 760 | |||
| 761 | /* | ||
| 762 | * If 802.11g protection is enabled, determine whether | ||
| 763 | * to use RTS/CTS or just CTS. Note that this is only | ||
| 764 | * done for OFDM/HT unicast frames. | ||
| 765 | */ | ||
| 766 | if (sc->sc_protmode != PROT_M_NONE && | ||
| 767 | (rt->info[rix].phy == PHY_OFDM || | ||
| 768 | rt->info[rix].phy == PHY_HT) && | ||
| 769 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | ||
| 770 | if (sc->sc_protmode == PROT_M_RTSCTS) | ||
| 771 | flags = ATH9K_TXDESC_RTSENA; | ||
| 772 | else if (sc->sc_protmode == PROT_M_CTSONLY) | ||
| 773 | flags = ATH9K_TXDESC_CTSENA; | ||
| 774 | |||
| 775 | cix = rt->info[sc->sc_protrix].controlRate; | ||
| 776 | rtsctsena = 1; | ||
| 777 | } | ||
| 778 | |||
| 779 | /* For 11n, the default behavior is to enable RTS for | ||
| 780 | * hw retried frames. We enable the global flag here and | ||
| 781 | * let rate series flags determine which rates will actually | ||
| 782 | * use RTS. | ||
| 783 | */ | ||
| 784 | if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf->bf_isdata) { | ||
| 785 | BUG_ON(!an); | ||
| 786 | /* | ||
| 787 | * 802.11g protection not needed, use our default behavior | ||
| 788 | */ | ||
| 789 | if (!rtsctsena) | ||
| 790 | flags = ATH9K_TXDESC_RTSENA; | ||
| 791 | /* | ||
| 792 | * For dynamic MIMO PS, RTS needs to precede the first aggregate | ||
| 793 | * and the second aggregate should have any protection at all. | ||
| 794 | */ | ||
| 795 | if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) { | ||
| 796 | if (!bf->bf_aggrburst) { | ||
| 797 | flags = ATH9K_TXDESC_RTSENA; | ||
| 798 | dynamic_mimops = 1; | ||
| 799 | } else { | ||
| 800 | flags = 0; | ||
| 801 | } | ||
| 802 | } | ||
| 803 | } | ||
| 804 | |||
| 805 | /* | ||
| 806 | * Set protection if aggregate protection on | ||
| 807 | */ | ||
| 808 | if (sc->sc_config.ath_aggr_prot && | ||
| 809 | (!bf->bf_isaggr || (bf->bf_isaggr && bf->bf_al < 8192))) { | ||
| 810 | flags = ATH9K_TXDESC_RTSENA; | ||
| 811 | cix = rt->info[sc->sc_protrix].controlRate; | ||
| 812 | rtsctsena = 1; | ||
| 813 | } | ||
| 814 | |||
| 815 | /* | ||
| 816 | * For AR5416 - RTS cannot be followed by a frame larger than 8K. | ||
| 817 | */ | ||
| 818 | if (bf->bf_isaggr && (bf->bf_al > aggr_limit_with_rts)) { | ||
| 819 | /* | ||
| 820 | * Ensure that in the case of SM Dynamic power save | ||
| 821 | * while we are bursting the second aggregate the | ||
| 822 | * RTS is cleared. | ||
| 823 | */ | ||
| 824 | flags &= ~(ATH9K_TXDESC_RTSENA); | ||
| 825 | } | ||
| 826 | |||
| 827 | /* | ||
| 828 | * CTS transmit rate is derived from the transmit rate | ||
| 829 | * by looking in the h/w rate table. We must also factor | ||
| 830 | * in whether or not a short preamble is to be used. | ||
| 831 | */ | ||
| 832 | /* NB: cix is set above where RTS/CTS is enabled */ | ||
| 833 | BUG_ON(cix == 0xff); | ||
| 834 | ctsrate = rt->info[cix].rateCode | | ||
| 835 | (bf->bf_shpreamble ? rt->info[cix].shortPreamble : 0); | ||
| 836 | |||
| 837 | /* | ||
| 838 | * Setup HAL rate series | ||
| 839 | */ | ||
| 840 | memzero(series, sizeof(struct ath9k_11n_rate_series) * 4); | ||
| 841 | |||
| 842 | for (i = 0; i < 4; i++) { | ||
| 843 | if (!bf->bf_rcs[i].tries) | ||
| 844 | continue; | ||
| 845 | |||
| 846 | rix = bf->bf_rcs[i].rix; | ||
| 847 | |||
| 848 | series[i].Rate = rt->info[rix].rateCode | | ||
| 849 | (bf->bf_shpreamble ? rt->info[rix].shortPreamble : 0); | ||
| 850 | |||
| 851 | series[i].Tries = bf->bf_rcs[i].tries; | ||
| 852 | |||
| 853 | series[i].RateFlags = ( | ||
| 854 | (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ? | ||
| 855 | ATH9K_RATESERIES_RTS_CTS : 0) | | ||
| 856 | ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ? | ||
| 857 | ATH9K_RATESERIES_2040 : 0) | | ||
| 858 | ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ? | ||
| 859 | ATH9K_RATESERIES_HALFGI : 0); | ||
| 860 | |||
| 861 | series[i].PktDuration = ath_pkt_duration( | ||
| 862 | sc, rix, bf, | ||
| 863 | (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0, | ||
| 864 | (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG), | ||
| 865 | bf->bf_shpreamble); | ||
| 866 | |||
| 867 | if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) && | ||
| 868 | (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) { | ||
| 869 | /* | ||
| 870 | * When sending to an HT node that has enabled static | ||
| 871 | * SM/MIMO power save, send at single stream rates but | ||
| 872 | * use maximum allowed transmit chains per user, | ||
| 873 | * hardware, regulatory, or country limits for | ||
| 874 | * better range. | ||
| 875 | */ | ||
| 876 | series[i].ChSel = sc->sc_tx_chainmask; | ||
| 877 | } else { | ||
| 878 | if (bf->bf_ht) | ||
| 879 | series[i].ChSel = | ||
| 880 | ath_chainmask_sel_logic(sc, an); | ||
| 881 | else | ||
| 882 | series[i].ChSel = sc->sc_tx_chainmask; | ||
| 883 | } | ||
| 884 | |||
| 885 | if (rtsctsena) | ||
| 886 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | ||
| 887 | |||
| 888 | /* | ||
| 889 | * Set RTS for all rates if node is in dynamic powersave | ||
| 890 | * mode and we are using dual stream rates. | ||
| 891 | */ | ||
| 892 | if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)) | ||
| 893 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | ||
| 894 | } | ||
| 895 | |||
| 896 | /* | ||
| 897 | * For non-HT devices, calculate RTS/CTS duration in software | ||
| 898 | * and disable multi-rate retry. | ||
| 899 | */ | ||
| 900 | if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) { | ||
| 901 | /* | ||
| 902 | * Compute the transmit duration based on the frame | ||
| 903 | * size and the size of an ACK frame. We call into the | ||
| 904 | * HAL to do the computation since it depends on the | ||
| 905 | * characteristics of the actual PHY being used. | ||
| 906 | * | ||
| 907 | * NB: CTS is assumed the same size as an ACK so we can | ||
| 908 | * use the precalculated ACK durations. | ||
| 909 | */ | ||
| 910 | if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */ | ||
| 911 | ctsduration += bf->bf_shpreamble ? | ||
| 912 | rt->info[cix].spAckDuration : | ||
| 913 | rt->info[cix].lpAckDuration; | ||
| 914 | } | ||
| 915 | |||
| 916 | ctsduration += series[0].PktDuration; | ||
| 917 | |||
| 918 | if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */ | ||
| 919 | ctsduration += bf->bf_shpreamble ? | ||
| 920 | rt->info[rix].spAckDuration : | ||
| 921 | rt->info[rix].lpAckDuration; | ||
| 922 | } | ||
| 923 | |||
| 924 | /* | ||
| 925 | * Disable multi-rate retry when using RTS/CTS by clearing | ||
| 926 | * series 1, 2 and 3. | ||
| 927 | */ | ||
| 928 | memzero(&series[1], sizeof(struct ath9k_11n_rate_series) * 3); | ||
| 929 | } | ||
| 930 | |||
| 931 | /* | ||
| 932 | * set dur_update_en for l-sig computation except for PS-Poll frames | ||
| 933 | */ | ||
| 934 | ath9k_hw_set11n_ratescenario(ah, ds, lastds, | ||
| 935 | !bf->bf_ispspoll, | ||
| 936 | ctsrate, | ||
| 937 | ctsduration, | ||
| 938 | series, 4, flags); | ||
| 939 | if (sc->sc_config.ath_aggr_prot && flags) | ||
| 940 | ath9k_hw_set11n_burstduration(ah, ds, 8192); | ||
| 941 | } | ||
| 942 | |||
| 943 | /* | ||
| 944 | * Function to send a normal HT (non-AMPDU) frame | ||
| 945 | * NB: must be called with txq lock held | ||
| 946 | */ | ||
| 947 | |||
| 948 | static int ath_tx_send_normal(struct ath_softc *sc, | ||
| 949 | struct ath_txq *txq, | ||
| 950 | struct ath_atx_tid *tid, | ||
| 951 | struct list_head *bf_head) | ||
| 952 | { | ||
| 953 | struct ath_buf *bf; | ||
| 954 | struct sk_buff *skb; | ||
| 955 | struct ieee80211_tx_info *tx_info; | ||
| 956 | struct ath_tx_info_priv *tx_info_priv; | ||
| 957 | |||
| 958 | BUG_ON(list_empty(bf_head)); | ||
| 959 | |||
| 960 | bf = list_first_entry(bf_head, struct ath_buf, list); | ||
| 961 | bf->bf_isampdu = 0; /* regular HT frame */ | ||
| 962 | |||
| 963 | skb = (struct sk_buff *)bf->bf_mpdu; | ||
| 964 | tx_info = IEEE80211_SKB_CB(skb); | ||
| 965 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 966 | memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0])); | ||
| 967 | |||
| 968 | /* update starting sequence number for subsequent ADDBA request */ | ||
| 969 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | ||
| 970 | |||
| 971 | /* Queue to h/w without aggregation */ | ||
| 972 | bf->bf_nframes = 1; | ||
| 973 | bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */ | ||
| 974 | ath_buf_set_rate(sc, bf); | ||
| 975 | ath_tx_txqaddbuf(sc, txq, bf_head); | ||
| 976 | |||
| 977 | return 0; | ||
| 978 | } | ||
| 979 | |||
| 980 | /* flush tid's software queue and send frames as non-ampdu's */ | ||
| 981 | |||
| 982 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) | ||
| 983 | { | ||
| 984 | struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; | ||
| 985 | struct ath_buf *bf; | ||
| 986 | struct list_head bf_head; | ||
| 987 | INIT_LIST_HEAD(&bf_head); | ||
| 988 | |||
| 989 | ASSERT(tid->paused > 0); | ||
| 990 | spin_lock_bh(&txq->axq_lock); | ||
| 991 | |||
| 992 | tid->paused--; | ||
| 993 | |||
| 994 | if (tid->paused > 0) { | ||
| 995 | spin_unlock_bh(&txq->axq_lock); | ||
| 996 | return; | ||
| 997 | } | ||
| 998 | |||
| 999 | while (!list_empty(&tid->buf_q)) { | ||
| 1000 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | ||
| 1001 | ASSERT(!bf->bf_isretried); | ||
| 1002 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | ||
| 1003 | ath_tx_send_normal(sc, txq, tid, &bf_head); | ||
| 1004 | } | ||
| 1005 | |||
| 1006 | spin_unlock_bh(&txq->axq_lock); | ||
| 1007 | } | ||
| 1008 | |||
| 1009 | /* Completion routine of an aggregate */ | ||
| 1010 | |||
| 1011 | static void ath_tx_complete_aggr_rifs(struct ath_softc *sc, | ||
| 1012 | struct ath_txq *txq, | ||
| 1013 | struct ath_buf *bf, | ||
| 1014 | struct list_head *bf_q, | ||
| 1015 | int txok) | ||
| 1016 | { | ||
| 1017 | struct ath_node *an = bf->bf_node; | ||
| 1018 | struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno); | ||
| 1019 | struct ath_buf *bf_last = bf->bf_lastbf; | ||
| 1020 | struct ath_desc *ds = bf_last->bf_desc; | ||
| 1021 | struct ath_buf *bf_next, *bf_lastq = NULL; | ||
| 1022 | struct list_head bf_head, bf_pending; | ||
| 1023 | u16 seq_st = 0; | ||
| 1024 | u32 ba[WME_BA_BMP_SIZE >> 5]; | ||
| 1025 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0; | ||
| 1026 | int isnodegone = (an->an_flags & ATH_NODE_CLEAN); | ||
| 1027 | |||
| 1028 | isaggr = bf->bf_isaggr; | ||
| 1029 | if (isaggr) { | ||
| 1030 | if (txok) { | ||
| 1031 | if (ATH_DS_TX_BA(ds)) { | ||
| 1032 | /* | ||
| 1033 | * extract starting sequence and | ||
| 1034 | * block-ack bitmap | ||
| 1035 | */ | ||
| 1036 | seq_st = ATH_DS_BA_SEQ(ds); | ||
| 1037 | memcpy(ba, | ||
| 1038 | ATH_DS_BA_BITMAP(ds), | ||
| 1039 | WME_BA_BMP_SIZE >> 3); | ||
| 1040 | } else { | ||
| 1041 | memzero(ba, WME_BA_BMP_SIZE >> 3); | ||
| 1042 | |||
| 1043 | /* | ||
| 1044 | * AR5416 can become deaf/mute when BA | ||
| 1045 | * issue happens. Chip needs to be reset. | ||
| 1046 | * But AP code may have sychronization issues | ||
| 1047 | * when perform internal reset in this routine. | ||
| 1048 | * Only enable reset in STA mode for now. | ||
| 1049 | */ | ||
| 1050 | if (sc->sc_opmode == ATH9K_M_STA) | ||
| 1051 | needreset = 1; | ||
| 1052 | } | ||
| 1053 | } else { | ||
| 1054 | memzero(ba, WME_BA_BMP_SIZE >> 3); | ||
| 1055 | } | ||
| 1056 | } | ||
| 1057 | |||
| 1058 | INIT_LIST_HEAD(&bf_pending); | ||
| 1059 | INIT_LIST_HEAD(&bf_head); | ||
| 1060 | |||
| 1061 | while (bf) { | ||
| 1062 | txfail = txpending = 0; | ||
| 1063 | bf_next = bf->bf_next; | ||
| 1064 | |||
| 1065 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { | ||
| 1066 | /* transmit completion, subframe is | ||
| 1067 | * acked by block ack */ | ||
| 1068 | } else if (!isaggr && txok) { | ||
| 1069 | /* transmit completion */ | ||
| 1070 | } else { | ||
| 1071 | |||
| 1072 | if (!tid->cleanup_inprogress && !isnodegone && | ||
| 1073 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | ||
| 1074 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | ||
| 1075 | ath_tx_set_retry(sc, bf); | ||
| 1076 | txpending = 1; | ||
| 1077 | } else { | ||
| 1078 | bf->bf_isxretried = 1; | ||
| 1079 | txfail = 1; | ||
| 1080 | sendbar = 1; | ||
| 1081 | } | ||
| 1082 | } else { | ||
| 1083 | /* | ||
| 1084 | * cleanup in progress, just fail | ||
| 1085 | * the un-acked sub-frames | ||
| 1086 | */ | ||
| 1087 | txfail = 1; | ||
| 1088 | } | ||
| 1089 | } | ||
| 1090 | /* | ||
| 1091 | * Remove ath_buf's of this sub-frame from aggregate queue. | ||
| 1092 | */ | ||
| 1093 | if (bf_next == NULL) { /* last subframe in the aggregate */ | ||
| 1094 | ASSERT(bf->bf_lastfrm == bf_last); | ||
| 1095 | |||
| 1096 | /* | ||
| 1097 | * The last descriptor of the last sub frame could be | ||
| 1098 | * a holding descriptor for h/w. If that's the case, | ||
| 1099 | * bf->bf_lastfrm won't be in the bf_q. | ||
| 1100 | * Make sure we handle bf_q properly here. | ||
| 1101 | */ | ||
| 1102 | |||
| 1103 | if (!list_empty(bf_q)) { | ||
| 1104 | bf_lastq = list_entry(bf_q->prev, | ||
| 1105 | struct ath_buf, list); | ||
| 1106 | list_cut_position(&bf_head, | ||
| 1107 | bf_q, &bf_lastq->list); | ||
| 1108 | } else { | ||
| 1109 | /* | ||
| 1110 | * XXX: if the last subframe only has one | ||
| 1111 | * descriptor which is also being used as | ||
| 1112 | * a holding descriptor. Then the ath_buf | ||
| 1113 | * is not in the bf_q at all. | ||
| 1114 | */ | ||
| 1115 | INIT_LIST_HEAD(&bf_head); | ||
| 1116 | } | ||
| 1117 | } else { | ||
| 1118 | ASSERT(!list_empty(bf_q)); | ||
| 1119 | list_cut_position(&bf_head, | ||
| 1120 | bf_q, &bf->bf_lastfrm->list); | ||
| 1121 | } | ||
| 1122 | |||
| 1123 | if (!txpending) { | ||
| 1124 | /* | ||
| 1125 | * complete the acked-ones/xretried ones; update | ||
| 1126 | * block-ack window | ||
| 1127 | */ | ||
| 1128 | spin_lock_bh(&txq->axq_lock); | ||
| 1129 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | ||
| 1130 | spin_unlock_bh(&txq->axq_lock); | ||
| 1131 | |||
| 1132 | /* complete this sub-frame */ | ||
| 1133 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); | ||
| 1134 | } else { | ||
| 1135 | /* | ||
| 1136 | * retry the un-acked ones | ||
| 1137 | */ | ||
| 1138 | /* | ||
| 1139 | * XXX: if the last descriptor is holding descriptor, | ||
| 1140 | * in order to requeue the frame to software queue, we | ||
| 1141 | * need to allocate a new descriptor and | ||
| 1142 | * copy the content of holding descriptor to it. | ||
| 1143 | */ | ||
| 1144 | if (bf->bf_next == NULL && | ||
| 1145 | bf_last->bf_status & ATH_BUFSTATUS_STALE) { | ||
| 1146 | struct ath_buf *tbf; | ||
| 1147 | |||
| 1148 | /* allocate new descriptor */ | ||
| 1149 | spin_lock_bh(&sc->sc_txbuflock); | ||
| 1150 | ASSERT(!list_empty((&sc->sc_txbuf))); | ||
| 1151 | tbf = list_first_entry(&sc->sc_txbuf, | ||
| 1152 | struct ath_buf, list); | ||
| 1153 | list_del(&tbf->list); | ||
| 1154 | spin_unlock_bh(&sc->sc_txbuflock); | ||
| 1155 | |||
| 1156 | ATH_TXBUF_RESET(tbf); | ||
| 1157 | |||
| 1158 | /* copy descriptor content */ | ||
| 1159 | tbf->bf_mpdu = bf_last->bf_mpdu; | ||
| 1160 | tbf->bf_node = bf_last->bf_node; | ||
| 1161 | tbf->bf_buf_addr = bf_last->bf_buf_addr; | ||
| 1162 | *(tbf->bf_desc) = *(bf_last->bf_desc); | ||
| 1163 | |||
| 1164 | /* link it to the frame */ | ||
| 1165 | if (bf_lastq) { | ||
| 1166 | bf_lastq->bf_desc->ds_link = | ||
| 1167 | tbf->bf_daddr; | ||
| 1168 | bf->bf_lastfrm = tbf; | ||
| 1169 | ath9k_hw_cleartxdesc(sc->sc_ah, | ||
| 1170 | bf->bf_lastfrm->bf_desc); | ||
| 1171 | } else { | ||
| 1172 | tbf->bf_state = bf_last->bf_state; | ||
| 1173 | tbf->bf_lastfrm = tbf; | ||
| 1174 | ath9k_hw_cleartxdesc(sc->sc_ah, | ||
| 1175 | tbf->bf_lastfrm->bf_desc); | ||
| 1176 | |||
| 1177 | /* copy the DMA context */ | ||
| 1178 | copy_dma_mem_context( | ||
| 1179 | get_dma_mem_context(tbf, | ||
| 1180 | bf_dmacontext), | ||
| 1181 | get_dma_mem_context(bf_last, | ||
| 1182 | bf_dmacontext)); | ||
| 1183 | } | ||
| 1184 | list_add_tail(&tbf->list, &bf_head); | ||
| 1185 | } else { | ||
| 1186 | /* | ||
| 1187 | * Clear descriptor status words for | ||
| 1188 | * software retry | ||
| 1189 | */ | ||
| 1190 | ath9k_hw_cleartxdesc(sc->sc_ah, | ||
| 1191 | bf->bf_lastfrm->bf_desc); | ||
| 1192 | } | ||
| 1193 | |||
| 1194 | /* | ||
| 1195 | * Put this buffer to the temporary pending | ||
| 1196 | * queue to retain ordering | ||
| 1197 | */ | ||
| 1198 | list_splice_tail_init(&bf_head, &bf_pending); | ||
| 1199 | } | ||
| 1200 | |||
| 1201 | bf = bf_next; | ||
| 1202 | } | ||
| 1203 | |||
| 1204 | /* | ||
| 1205 | * node is already gone. no more assocication | ||
| 1206 | * with the node. the node might have been freed | ||
| 1207 | * any node acces can result in panic.note tid | ||
| 1208 | * is part of the node. | ||
| 1209 | */ | ||
| 1210 | if (isnodegone) | ||
| 1211 | return; | ||
| 1212 | |||
| 1213 | if (tid->cleanup_inprogress) { | ||
| 1214 | /* check to see if we're done with cleaning the h/w queue */ | ||
| 1215 | spin_lock_bh(&txq->axq_lock); | ||
| 1216 | |||
| 1217 | if (tid->baw_head == tid->baw_tail) { | ||
| 1218 | tid->addba_exchangecomplete = 0; | ||
| 1219 | tid->addba_exchangeattempts = 0; | ||
| 1220 | spin_unlock_bh(&txq->axq_lock); | ||
| 1221 | |||
| 1222 | tid->cleanup_inprogress = false; | ||
| 1223 | |||
| 1224 | /* send buffered frames as singles */ | ||
| 1225 | ath_tx_flush_tid(sc, tid); | ||
| 1226 | } else | ||
| 1227 | spin_unlock_bh(&txq->axq_lock); | ||
| 1228 | |||
| 1229 | return; | ||
| 1230 | } | ||
| 1231 | |||
| 1232 | /* | ||
| 1233 | * prepend un-acked frames to the beginning of the pending frame queue | ||
| 1234 | */ | ||
| 1235 | if (!list_empty(&bf_pending)) { | ||
| 1236 | spin_lock_bh(&txq->axq_lock); | ||
| 1237 | /* Note: we _prepend_, we _do_not_ at to | ||
| 1238 | * the end of the queue ! */ | ||
| 1239 | list_splice(&bf_pending, &tid->buf_q); | ||
| 1240 | ath_tx_queue_tid(txq, tid); | ||
| 1241 | spin_unlock_bh(&txq->axq_lock); | ||
| 1242 | } | ||
| 1243 | |||
| 1244 | if (needreset) | ||
| 1245 | ath_internal_reset(sc); | ||
| 1246 | |||
| 1247 | return; | ||
| 1248 | } | ||
| 1249 | |||
| 1250 | /* Process completed xmit descriptors from the specified queue */ | ||
| 1251 | |||
| 1252 | static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) | ||
| 1253 | { | ||
| 1254 | struct ath_hal *ah = sc->sc_ah; | ||
| 1255 | struct ath_buf *bf, *lastbf, *bf_held = NULL; | ||
| 1256 | struct list_head bf_head; | ||
| 1257 | struct ath_desc *ds, *tmp_ds; | ||
| 1258 | struct sk_buff *skb; | ||
| 1259 | struct ieee80211_tx_info *tx_info; | ||
| 1260 | struct ath_tx_info_priv *tx_info_priv; | ||
| 1261 | int nacked, txok, nbad = 0, isrifs = 0; | ||
| 1262 | int status; | ||
| 1263 | |||
| 1264 | DPRINTF(sc, ATH_DBG_QUEUE, | ||
| 1265 | "%s: tx queue %d (%x), link %p\n", __func__, | ||
| 1266 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | ||
| 1267 | txq->axq_link); | ||
| 1268 | |||
| 1269 | nacked = 0; | ||
| 1270 | for (;;) { | ||
| 1271 | spin_lock_bh(&txq->axq_lock); | ||
| 1272 | txq->axq_intrcnt = 0; /* reset periodic desc intr count */ | ||
| 1273 | if (list_empty(&txq->axq_q)) { | ||
| 1274 | txq->axq_link = NULL; | ||
| 1275 | txq->axq_linkbuf = NULL; | ||
| 1276 | spin_unlock_bh(&txq->axq_lock); | ||
| 1277 | break; | ||
| 1278 | } | ||
| 1279 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); | ||
| 1280 | |||
| 1281 | /* | ||
| 1282 | * There is a race condition that a BH gets scheduled | ||
| 1283 | * after sw writes TxE and before hw re-load the last | ||
| 1284 | * descriptor to get the newly chained one. | ||
| 1285 | * Software must keep the last DONE descriptor as a | ||
| 1286 | * holding descriptor - software does so by marking | ||
| 1287 | * it with the STALE flag. | ||
| 1288 | */ | ||
| 1289 | bf_held = NULL; | ||
| 1290 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | ||
| 1291 | bf_held = bf; | ||
| 1292 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | ||
| 1293 | /* FIXME: | ||
| 1294 | * The holding descriptor is the last | ||
| 1295 | * descriptor in queue. It's safe to remove | ||
| 1296 | * the last holding descriptor in BH context. | ||
| 1297 | */ | ||
| 1298 | spin_unlock_bh(&txq->axq_lock); | ||
| 1299 | break; | ||
| 1300 | } else { | ||
| 1301 | /* Lets work with the next buffer now */ | ||
| 1302 | bf = list_entry(bf_held->list.next, | ||
| 1303 | struct ath_buf, list); | ||
| 1304 | } | ||
| 1305 | } | ||
| 1306 | |||
| 1307 | lastbf = bf->bf_lastbf; | ||
| 1308 | ds = lastbf->bf_desc; /* NB: last decriptor */ | ||
| 1309 | |||
| 1310 | status = ath9k_hw_txprocdesc(ah, ds); | ||
| 1311 | if (status == -EINPROGRESS) { | ||
| 1312 | spin_unlock_bh(&txq->axq_lock); | ||
| 1313 | break; | ||
| 1314 | } | ||
| 1315 | if (bf->bf_desc == txq->axq_lastdsWithCTS) | ||
| 1316 | txq->axq_lastdsWithCTS = NULL; | ||
| 1317 | if (ds == txq->axq_gatingds) | ||
| 1318 | txq->axq_gatingds = NULL; | ||
| 1319 | |||
| 1320 | /* | ||
| 1321 | * Remove ath_buf's of the same transmit unit from txq, | ||
| 1322 | * however leave the last descriptor back as the holding | ||
| 1323 | * descriptor for hw. | ||
| 1324 | */ | ||
| 1325 | lastbf->bf_status |= ATH_BUFSTATUS_STALE; | ||
| 1326 | INIT_LIST_HEAD(&bf_head); | ||
| 1327 | |||
| 1328 | if (!list_is_singular(&lastbf->list)) | ||
| 1329 | list_cut_position(&bf_head, | ||
| 1330 | &txq->axq_q, lastbf->list.prev); | ||
| 1331 | |||
| 1332 | txq->axq_depth--; | ||
| 1333 | |||
| 1334 | if (bf->bf_isaggr) | ||
| 1335 | txq->axq_aggr_depth--; | ||
| 1336 | |||
| 1337 | txok = (ds->ds_txstat.ts_status == 0); | ||
| 1338 | |||
| 1339 | spin_unlock_bh(&txq->axq_lock); | ||
| 1340 | |||
| 1341 | if (bf_held) { | ||
| 1342 | list_del(&bf_held->list); | ||
| 1343 | spin_lock_bh(&sc->sc_txbuflock); | ||
| 1344 | list_add_tail(&bf_held->list, &sc->sc_txbuf); | ||
| 1345 | spin_unlock_bh(&sc->sc_txbuflock); | ||
| 1346 | } | ||
| 1347 | |||
| 1348 | if (!bf->bf_isampdu) { | ||
| 1349 | /* | ||
| 1350 | * This frame is sent out as a single frame. | ||
| 1351 | * Use hardware retry status for this frame. | ||
| 1352 | */ | ||
| 1353 | bf->bf_retries = ds->ds_txstat.ts_longretry; | ||
| 1354 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | ||
| 1355 | bf->bf_isxretried = 1; | ||
| 1356 | nbad = 0; | ||
| 1357 | } else { | ||
| 1358 | nbad = ath_tx_num_badfrms(sc, bf, txok); | ||
| 1359 | } | ||
| 1360 | skb = bf->bf_mpdu; | ||
| 1361 | tx_info = IEEE80211_SKB_CB(skb); | ||
| 1362 | tx_info_priv = (struct ath_tx_info_priv *) | ||
| 1363 | tx_info->driver_data[0]; | ||
| 1364 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) | ||
| 1365 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | ||
| 1366 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && | ||
| 1367 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | ||
| 1368 | if (ds->ds_txstat.ts_status == 0) | ||
| 1369 | nacked++; | ||
| 1370 | |||
| 1371 | if (bf->bf_isdata) { | ||
| 1372 | if (isrifs) | ||
| 1373 | tmp_ds = bf->bf_rifslast->bf_desc; | ||
| 1374 | else | ||
| 1375 | tmp_ds = ds; | ||
| 1376 | memcpy(&tx_info_priv->tx, | ||
| 1377 | &tmp_ds->ds_txstat, | ||
| 1378 | sizeof(tx_info_priv->tx)); | ||
| 1379 | tx_info_priv->n_frames = bf->bf_nframes; | ||
| 1380 | tx_info_priv->n_bad_frames = nbad; | ||
| 1381 | } | ||
| 1382 | } | ||
| 1383 | |||
| 1384 | /* | ||
| 1385 | * Complete this transmit unit | ||
| 1386 | */ | ||
| 1387 | if (bf->bf_isampdu) | ||
| 1388 | ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok); | ||
| 1389 | else | ||
| 1390 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | ||
| 1391 | |||
| 1392 | /* Wake up mac80211 queue */ | ||
| 1393 | |||
| 1394 | spin_lock_bh(&txq->axq_lock); | ||
| 1395 | if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <= | ||
| 1396 | (ATH_TXBUF - 20)) { | ||
| 1397 | int qnum; | ||
| 1398 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); | ||
| 1399 | if (qnum != -1) { | ||
| 1400 | ieee80211_wake_queue(sc->hw, qnum); | ||
| 1401 | txq->stopped = 0; | ||
| 1402 | } | ||
| 1403 | |||
| 1404 | } | ||
| 1405 | |||
| 1406 | /* | ||
| 1407 | * schedule any pending packets if aggregation is enabled | ||
| 1408 | */ | ||
| 1409 | if (sc->sc_txaggr) | ||
| 1410 | ath_txq_schedule(sc, txq); | ||
| 1411 | spin_unlock_bh(&txq->axq_lock); | ||
| 1412 | } | ||
| 1413 | return nacked; | ||
| 1414 | } | ||
| 1415 | |||
| 1416 | static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) | ||
| 1417 | { | ||
| 1418 | struct ath_hal *ah = sc->sc_ah; | ||
| 1419 | |||
| 1420 | (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum); | ||
| 1421 | DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n", | ||
| 1422 | __func__, txq->axq_qnum, | ||
| 1423 | ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link); | ||
| 1424 | } | ||
| 1425 | |||
| 1426 | /* Drain only the data queues */ | ||
| 1427 | |||
| 1428 | static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx) | ||
| 1429 | { | ||
| 1430 | struct ath_hal *ah = sc->sc_ah; | ||
| 1431 | int i; | ||
| 1432 | int npend = 0; | ||
| 1433 | enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc); | ||
| 1434 | |||
| 1435 | /* XXX return value */ | ||
| 1436 | if (!sc->sc_invalid) { | ||
| 1437 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | ||
| 1438 | if (ATH_TXQ_SETUP(sc, i)) { | ||
| 1439 | ath_tx_stopdma(sc, &sc->sc_txq[i]); | ||
| 1440 | |||
| 1441 | /* The TxDMA may not really be stopped. | ||
| 1442 | * Double check the hal tx pending count */ | ||
| 1443 | npend += ath9k_hw_numtxpending(ah, | ||
| 1444 | sc->sc_txq[i].axq_qnum); | ||
| 1445 | } | ||
| 1446 | } | ||
| 1447 | } | ||
| 1448 | |||
| 1449 | if (npend) { | ||
| 1450 | int status; | ||
| 1451 | |||
| 1452 | /* TxDMA not stopped, reset the hal */ | ||
| 1453 | DPRINTF(sc, ATH_DBG_XMIT, | ||
| 1454 | "%s: Unable to stop TxDMA. Reset HAL!\n", __func__); | ||
| 1455 | |||
| 1456 | spin_lock_bh(&sc->sc_resetlock); | ||
| 1457 | if (!ath9k_hw_reset(ah, sc->sc_opmode, | ||
| 1458 | &sc->sc_curchan, ht_macmode, | ||
| 1459 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, | ||
| 1460 | sc->sc_ht_extprotspacing, true, &status)) { | ||
| 1461 | |||
| 1462 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 1463 | "%s: unable to reset hardware; hal status %u\n", | ||
| 1464 | __func__, | ||
| 1465 | status); | ||
| 1466 | } | ||
| 1467 | spin_unlock_bh(&sc->sc_resetlock); | ||
| 1468 | } | ||
| 1469 | |||
| 1470 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | ||
| 1471 | if (ATH_TXQ_SETUP(sc, i)) | ||
| 1472 | ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx); | ||
| 1473 | } | ||
| 1474 | } | ||
| 1475 | |||
| 1476 | /* Add a sub-frame to block ack window */ | ||
| 1477 | |||
| 1478 | static void ath_tx_addto_baw(struct ath_softc *sc, | ||
| 1479 | struct ath_atx_tid *tid, | ||
| 1480 | struct ath_buf *bf) | ||
| 1481 | { | ||
| 1482 | int index, cindex; | ||
| 1483 | |||
| 1484 | if (bf->bf_isretried) | ||
| 1485 | return; | ||
| 1486 | |||
| 1487 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); | ||
| 1488 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | ||
| 1489 | |||
| 1490 | ASSERT(tid->tx_buf[cindex] == NULL); | ||
| 1491 | tid->tx_buf[cindex] = bf; | ||
| 1492 | |||
| 1493 | if (index >= ((tid->baw_tail - tid->baw_head) & | ||
| 1494 | (ATH_TID_MAX_BUFS - 1))) { | ||
| 1495 | tid->baw_tail = cindex; | ||
| 1496 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | ||
| 1497 | } | ||
| 1498 | } | ||
| 1499 | |||
| 1500 | /* | ||
| 1501 | * Function to send an A-MPDU | ||
| 1502 | * NB: must be called with txq lock held | ||
| 1503 | */ | ||
| 1504 | |||
| 1505 | static int ath_tx_send_ampdu(struct ath_softc *sc, | ||
| 1506 | struct ath_txq *txq, | ||
| 1507 | struct ath_atx_tid *tid, | ||
| 1508 | struct list_head *bf_head, | ||
| 1509 | struct ath_tx_control *txctl) | ||
| 1510 | { | ||
| 1511 | struct ath_buf *bf; | ||
| 1512 | struct sk_buff *skb; | ||
| 1513 | struct ieee80211_tx_info *tx_info; | ||
| 1514 | struct ath_tx_info_priv *tx_info_priv; | ||
| 1515 | |||
| 1516 | BUG_ON(list_empty(bf_head)); | ||
| 1517 | |||
| 1518 | bf = list_first_entry(bf_head, struct ath_buf, list); | ||
| 1519 | bf->bf_isampdu = 1; | ||
| 1520 | bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */ | ||
| 1521 | bf->bf_tidno = txctl->tidno; | ||
| 1522 | |||
| 1523 | /* | ||
| 1524 | * Do not queue to h/w when any of the following conditions is true: | ||
| 1525 | * - there are pending frames in software queue | ||
| 1526 | * - the TID is currently paused for ADDBA/BAR request | ||
| 1527 | * - seqno is not within block-ack window | ||
| 1528 | * - h/w queue depth exceeds low water mark | ||
| 1529 | */ | ||
| 1530 | if (!list_empty(&tid->buf_q) || tid->paused || | ||
| 1531 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | ||
| 1532 | txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | ||
| 1533 | /* | ||
| 1534 | * Add this frame to software queue for scheduling later | ||
| 1535 | * for aggregation. | ||
| 1536 | */ | ||
| 1537 | list_splice_tail_init(bf_head, &tid->buf_q); | ||
| 1538 | ath_tx_queue_tid(txq, tid); | ||
| 1539 | return 0; | ||
| 1540 | } | ||
| 1541 | |||
| 1542 | skb = (struct sk_buff *)bf->bf_mpdu; | ||
| 1543 | tx_info = IEEE80211_SKB_CB(skb); | ||
| 1544 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 1545 | memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0])); | ||
| 1546 | |||
| 1547 | /* Add sub-frame to BAW */ | ||
| 1548 | ath_tx_addto_baw(sc, tid, bf); | ||
| 1549 | |||
| 1550 | /* Queue to h/w without aggregation */ | ||
| 1551 | bf->bf_nframes = 1; | ||
| 1552 | bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */ | ||
| 1553 | ath_buf_set_rate(sc, bf); | ||
| 1554 | ath_tx_txqaddbuf(sc, txq, bf_head); | ||
| 1555 | return 0; | ||
| 1556 | } | ||
| 1557 | |||
| 1558 | /* | ||
| 1559 | * looks up the rate | ||
| 1560 | * returns aggr limit based on lowest of the rates | ||
| 1561 | */ | ||
| 1562 | |||
| 1563 | static u32 ath_lookup_rate(struct ath_softc *sc, | ||
| 1564 | struct ath_buf *bf) | ||
| 1565 | { | ||
| 1566 | const struct ath9k_rate_table *rt = sc->sc_currates; | ||
| 1567 | struct sk_buff *skb; | ||
| 1568 | struct ieee80211_tx_info *tx_info; | ||
| 1569 | struct ath_tx_info_priv *tx_info_priv; | ||
| 1570 | u32 max_4ms_framelen, frame_length; | ||
| 1571 | u16 aggr_limit, legacy = 0, maxampdu; | ||
| 1572 | int i; | ||
| 1573 | |||
| 1574 | |||
| 1575 | skb = (struct sk_buff *)bf->bf_mpdu; | ||
| 1576 | tx_info = IEEE80211_SKB_CB(skb); | ||
| 1577 | tx_info_priv = (struct ath_tx_info_priv *) | ||
| 1578 | tx_info->driver_data[0]; | ||
| 1579 | memcpy(bf->bf_rcs, | ||
| 1580 | tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0])); | ||
| 1581 | |||
| 1582 | /* | ||
| 1583 | * Find the lowest frame length among the rate series that will have a | ||
| 1584 | * 4ms transmit duration. | ||
| 1585 | * TODO - TXOP limit needs to be considered. | ||
| 1586 | */ | ||
| 1587 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | ||
| 1588 | |||
| 1589 | for (i = 0; i < 4; i++) { | ||
| 1590 | if (bf->bf_rcs[i].tries) { | ||
| 1591 | frame_length = bf->bf_rcs[i].max_4ms_framelen; | ||
| 1592 | |||
| 1593 | if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) { | ||
| 1594 | legacy = 1; | ||
| 1595 | break; | ||
| 1596 | } | ||
| 1597 | |||
| 1598 | max_4ms_framelen = min(max_4ms_framelen, frame_length); | ||
| 1599 | } | ||
| 1600 | } | ||
| 1601 | |||
| 1602 | /* | ||
| 1603 | * limit aggregate size by the minimum rate if rate selected is | ||
| 1604 | * not a probe rate, if rate selected is a probe rate then | ||
| 1605 | * avoid aggregation of this packet. | ||
| 1606 | */ | ||
| 1607 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) | ||
| 1608 | return 0; | ||
| 1609 | |||
| 1610 | aggr_limit = min(max_4ms_framelen, | ||
| 1611 | (u32)ATH_AMPDU_LIMIT_DEFAULT); | ||
| 1612 | |||
| 1613 | /* | ||
| 1614 | * h/w can accept aggregates upto 16 bit lengths (65535). | ||
| 1615 | * The IE, however can hold upto 65536, which shows up here | ||
| 1616 | * as zero. Ignore 65536 since we are constrained by hw. | ||
| 1617 | */ | ||
| 1618 | maxampdu = sc->sc_ht_info.maxampdu; | ||
| 1619 | if (maxampdu) | ||
| 1620 | aggr_limit = min(aggr_limit, maxampdu); | ||
| 1621 | |||
| 1622 | return aggr_limit; | ||
| 1623 | } | ||
| 1624 | |||
| 1625 | /* | ||
| 1626 | * returns the number of delimiters to be added to | ||
| 1627 | * meet the minimum required mpdudensity. | ||
| 1628 | * caller should make sure that the rate is HT rate . | ||
| 1629 | */ | ||
| 1630 | |||
| 1631 | static int ath_compute_num_delims(struct ath_softc *sc, | ||
| 1632 | struct ath_buf *bf, | ||
| 1633 | u16 frmlen) | ||
| 1634 | { | ||
| 1635 | const struct ath9k_rate_table *rt = sc->sc_currates; | ||
| 1636 | u32 nsymbits, nsymbols, mpdudensity; | ||
| 1637 | u16 minlen; | ||
| 1638 | u8 rc, flags, rix; | ||
| 1639 | int width, half_gi, ndelim, mindelim; | ||
| 1640 | |||
| 1641 | /* Select standard number of delimiters based on frame length alone */ | ||
| 1642 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | ||
| 1643 | |||
| 1644 | /* | ||
| 1645 | * If encryption enabled, hardware requires some more padding between | ||
| 1646 | * subframes. | ||
| 1647 | * TODO - this could be improved to be dependent on the rate. | ||
| 1648 | * The hardware can keep up at lower rates, but not higher rates | ||
| 1649 | */ | ||
| 1650 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) | ||
| 1651 | ndelim += ATH_AGGR_ENCRYPTDELIM; | ||
| 1652 | |||
| 1653 | /* | ||
| 1654 | * Convert desired mpdu density from microeconds to bytes based | ||
| 1655 | * on highest rate in rate series (i.e. first rate) to determine | ||
| 1656 | * required minimum length for subframe. Take into account | ||
| 1657 | * whether high rate is 20 or 40Mhz and half or full GI. | ||
| 1658 | */ | ||
| 1659 | mpdudensity = sc->sc_ht_info.mpdudensity; | ||
| 1660 | |||
| 1661 | /* | ||
| 1662 | * If there is no mpdu density restriction, no further calculation | ||
| 1663 | * is needed. | ||
| 1664 | */ | ||
| 1665 | if (mpdudensity == 0) | ||
| 1666 | return ndelim; | ||
| 1667 | |||
| 1668 | rix = bf->bf_rcs[0].rix; | ||
| 1669 | flags = bf->bf_rcs[0].flags; | ||
| 1670 | rc = rt->info[rix].rateCode; | ||
| 1671 | width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0; | ||
| 1672 | half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0; | ||
| 1673 | |||
| 1674 | if (half_gi) | ||
| 1675 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | ||
| 1676 | else | ||
| 1677 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | ||
| 1678 | |||
| 1679 | if (nsymbols == 0) | ||
| 1680 | nsymbols = 1; | ||
| 1681 | |||
| 1682 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | ||
| 1683 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | ||
| 1684 | |||
| 1685 | /* Is frame shorter than required minimum length? */ | ||
| 1686 | if (frmlen < minlen) { | ||
| 1687 | /* Get the minimum number of delimiters required. */ | ||
| 1688 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; | ||
| 1689 | ndelim = max(mindelim, ndelim); | ||
| 1690 | } | ||
| 1691 | |||
| 1692 | return ndelim; | ||
| 1693 | } | ||
| 1694 | |||
| 1695 | /* | ||
| 1696 | * For aggregation from software buffer queue. | ||
| 1697 | * NB: must be called with txq lock held | ||
| 1698 | */ | ||
| 1699 | |||
| 1700 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, | ||
| 1701 | struct ath_atx_tid *tid, | ||
| 1702 | struct list_head *bf_q, | ||
| 1703 | struct ath_buf **bf_last, | ||
| 1704 | struct aggr_rifs_param *param, | ||
| 1705 | int *prev_frames) | ||
| 1706 | { | ||
| 1707 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) | ||
| 1708 | struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL; | ||
| 1709 | struct list_head bf_head; | ||
| 1710 | int rl = 0, nframes = 0, ndelim; | ||
| 1711 | u16 aggr_limit = 0, al = 0, bpad = 0, | ||
| 1712 | al_delta, h_baw = tid->baw_size / 2; | ||
| 1713 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | ||
| 1714 | int prev_al = 0, is_ds_rate = 0; | ||
| 1715 | INIT_LIST_HEAD(&bf_head); | ||
| 1716 | |||
| 1717 | BUG_ON(list_empty(&tid->buf_q)); | ||
| 1718 | |||
| 1719 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); | ||
| 1720 | |||
| 1721 | do { | ||
| 1722 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | ||
| 1723 | |||
| 1724 | /* | ||
| 1725 | * do not step over block-ack window | ||
| 1726 | */ | ||
| 1727 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { | ||
| 1728 | status = ATH_AGGR_BAW_CLOSED; | ||
| 1729 | break; | ||
| 1730 | } | ||
| 1731 | |||
| 1732 | if (!rl) { | ||
| 1733 | aggr_limit = ath_lookup_rate(sc, bf); | ||
| 1734 | rl = 1; | ||
| 1735 | /* | ||
| 1736 | * Is rate dual stream | ||
| 1737 | */ | ||
| 1738 | is_ds_rate = | ||
| 1739 | (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0; | ||
| 1740 | } | ||
| 1741 | |||
| 1742 | /* | ||
| 1743 | * do not exceed aggregation limit | ||
| 1744 | */ | ||
| 1745 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; | ||
| 1746 | |||
| 1747 | if (nframes && (aggr_limit < | ||
| 1748 | (al + bpad + al_delta + prev_al))) { | ||
| 1749 | status = ATH_AGGR_LIMITED; | ||
| 1750 | break; | ||
| 1751 | } | ||
| 1752 | |||
| 1753 | /* | ||
| 1754 | * do not exceed subframe limit | ||
| 1755 | */ | ||
| 1756 | if ((nframes + *prev_frames) >= | ||
| 1757 | min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | ||
| 1758 | status = ATH_AGGR_LIMITED; | ||
| 1759 | break; | ||
| 1760 | } | ||
| 1761 | |||
| 1762 | /* | ||
| 1763 | * add padding for previous frame to aggregation length | ||
| 1764 | */ | ||
| 1765 | al += bpad + al_delta; | ||
| 1766 | |||
| 1767 | /* | ||
| 1768 | * Get the delimiters needed to meet the MPDU | ||
| 1769 | * density for this node. | ||
| 1770 | */ | ||
| 1771 | ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_frmlen); | ||
| 1772 | |||
| 1773 | bpad = PADBYTES(al_delta) + (ndelim << 2); | ||
| 1774 | |||
| 1775 | bf->bf_next = NULL; | ||
| 1776 | bf->bf_lastfrm->bf_desc->ds_link = 0; | ||
| 1777 | |||
| 1778 | /* | ||
| 1779 | * this packet is part of an aggregate | ||
| 1780 | * - remove all descriptors belonging to this frame from | ||
| 1781 | * software queue | ||
| 1782 | * - add it to block ack window | ||
| 1783 | * - set up descriptors for aggregation | ||
| 1784 | */ | ||
| 1785 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | ||
| 1786 | ath_tx_addto_baw(sc, tid, bf); | ||
| 1787 | |||
| 1788 | list_for_each_entry(tbf, &bf_head, list) { | ||
| 1789 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, | ||
| 1790 | tbf->bf_desc, ndelim); | ||
| 1791 | } | ||
| 1792 | |||
| 1793 | /* | ||
| 1794 | * link buffers of this frame to the aggregate | ||
| 1795 | */ | ||
| 1796 | list_splice_tail_init(&bf_head, bf_q); | ||
| 1797 | nframes++; | ||
| 1798 | |||
| 1799 | if (bf_prev) { | ||
| 1800 | bf_prev->bf_next = bf; | ||
| 1801 | bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr; | ||
| 1802 | } | ||
| 1803 | bf_prev = bf; | ||
| 1804 | |||
| 1805 | #ifdef AGGR_NOSHORT | ||
| 1806 | /* | ||
| 1807 | * terminate aggregation on a small packet boundary | ||
| 1808 | */ | ||
| 1809 | if (bf->bf_frmlen < ATH_AGGR_MINPLEN) { | ||
| 1810 | status = ATH_AGGR_SHORTPKT; | ||
| 1811 | break; | ||
| 1812 | } | ||
| 1813 | #endif | ||
| 1814 | } while (!list_empty(&tid->buf_q)); | ||
| 1815 | |||
| 1816 | bf_first->bf_al = al; | ||
| 1817 | bf_first->bf_nframes = nframes; | ||
| 1818 | *bf_last = bf_prev; | ||
| 1819 | return status; | ||
| 1820 | #undef PADBYTES | ||
| 1821 | } | ||
| 1822 | |||
| 1823 | /* | ||
| 1824 | * process pending frames possibly doing a-mpdu aggregation | ||
| 1825 | * NB: must be called with txq lock held | ||
| 1826 | */ | ||
| 1827 | |||
| 1828 | static void ath_tx_sched_aggr(struct ath_softc *sc, | ||
| 1829 | struct ath_txq *txq, struct ath_atx_tid *tid) | ||
| 1830 | { | ||
| 1831 | struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL; | ||
| 1832 | enum ATH_AGGR_STATUS status; | ||
| 1833 | struct list_head bf_q; | ||
| 1834 | struct aggr_rifs_param param = {0, 0, 0, 0, NULL}; | ||
| 1835 | int prev_frames = 0; | ||
| 1836 | |||
| 1837 | do { | ||
| 1838 | if (list_empty(&tid->buf_q)) | ||
| 1839 | return; | ||
| 1840 | |||
| 1841 | INIT_LIST_HEAD(&bf_q); | ||
| 1842 | |||
| 1843 | status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, ¶m, | ||
| 1844 | &prev_frames); | ||
| 1845 | |||
| 1846 | /* | ||
| 1847 | * no frames picked up to be aggregated; block-ack | ||
| 1848 | * window is not open | ||
| 1849 | */ | ||
| 1850 | if (list_empty(&bf_q)) | ||
| 1851 | break; | ||
| 1852 | |||
| 1853 | bf = list_first_entry(&bf_q, struct ath_buf, list); | ||
| 1854 | bf_last = list_entry(bf_q.prev, struct ath_buf, list); | ||
| 1855 | bf->bf_lastbf = bf_last; | ||
| 1856 | |||
| 1857 | /* | ||
| 1858 | * if only one frame, send as non-aggregate | ||
| 1859 | */ | ||
| 1860 | if (bf->bf_nframes == 1) { | ||
| 1861 | ASSERT(bf->bf_lastfrm == bf_last); | ||
| 1862 | |||
| 1863 | bf->bf_isaggr = 0; | ||
| 1864 | /* | ||
| 1865 | * clear aggr bits for every descriptor | ||
| 1866 | * XXX TODO: is there a way to optimize it? | ||
| 1867 | */ | ||
| 1868 | list_for_each_entry(tbf, &bf_q, list) { | ||
| 1869 | ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc); | ||
| 1870 | } | ||
| 1871 | |||
| 1872 | ath_buf_set_rate(sc, bf); | ||
| 1873 | ath_tx_txqaddbuf(sc, txq, &bf_q); | ||
| 1874 | continue; | ||
| 1875 | } | ||
| 1876 | |||
| 1877 | /* | ||
| 1878 | * setup first desc with rate and aggr info | ||
| 1879 | */ | ||
| 1880 | bf->bf_isaggr = 1; | ||
| 1881 | ath_buf_set_rate(sc, bf); | ||
| 1882 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | ||
| 1883 | |||
| 1884 | /* | ||
| 1885 | * anchor last frame of aggregate correctly | ||
| 1886 | */ | ||
| 1887 | ASSERT(bf_lastaggr); | ||
| 1888 | ASSERT(bf_lastaggr->bf_lastfrm == bf_last); | ||
| 1889 | tbf = bf_lastaggr; | ||
| 1890 | ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc); | ||
| 1891 | |||
| 1892 | /* XXX: We don't enter into this loop, consider removing this */ | ||
| 1893 | while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) { | ||
| 1894 | tbf = list_entry(tbf->list.next, struct ath_buf, list); | ||
| 1895 | ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc); | ||
| 1896 | } | ||
| 1897 | |||
| 1898 | txq->axq_aggr_depth++; | ||
| 1899 | |||
| 1900 | /* | ||
| 1901 | * Normal aggregate, queue to hardware | ||
| 1902 | */ | ||
| 1903 | ath_tx_txqaddbuf(sc, txq, &bf_q); | ||
| 1904 | |||
| 1905 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && | ||
| 1906 | status != ATH_AGGR_BAW_CLOSED); | ||
| 1907 | } | ||
| 1908 | |||
| 1909 | /* Called with txq lock held */ | ||
| 1910 | |||
| 1911 | static void ath_tid_drain(struct ath_softc *sc, | ||
| 1912 | struct ath_txq *txq, | ||
| 1913 | struct ath_atx_tid *tid, | ||
| 1914 | bool bh_flag) | ||
| 1915 | { | ||
| 1916 | struct ath_buf *bf; | ||
| 1917 | struct list_head bf_head; | ||
| 1918 | INIT_LIST_HEAD(&bf_head); | ||
| 1919 | |||
| 1920 | for (;;) { | ||
| 1921 | if (list_empty(&tid->buf_q)) | ||
| 1922 | break; | ||
| 1923 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | ||
| 1924 | |||
| 1925 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | ||
| 1926 | |||
| 1927 | /* update baw for software retried frame */ | ||
| 1928 | if (bf->bf_isretried) | ||
| 1929 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | ||
| 1930 | |||
| 1931 | /* | ||
| 1932 | * do not indicate packets while holding txq spinlock. | ||
| 1933 | * unlock is intentional here | ||
| 1934 | */ | ||
| 1935 | if (likely(bh_flag)) | ||
| 1936 | spin_unlock_bh(&txq->axq_lock); | ||
| 1937 | else | ||
| 1938 | spin_unlock(&txq->axq_lock); | ||
| 1939 | |||
| 1940 | /* complete this sub-frame */ | ||
| 1941 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | ||
| 1942 | |||
| 1943 | if (likely(bh_flag)) | ||
| 1944 | spin_lock_bh(&txq->axq_lock); | ||
| 1945 | else | ||
| 1946 | spin_lock(&txq->axq_lock); | ||
| 1947 | } | ||
| 1948 | |||
| 1949 | /* | ||
| 1950 | * TODO: For frame(s) that are in the retry state, we will reuse the | ||
| 1951 | * sequence number(s) without setting the retry bit. The | ||
| 1952 | * alternative is to give up on these and BAR the receiver's window | ||
| 1953 | * forward. | ||
| 1954 | */ | ||
| 1955 | tid->seq_next = tid->seq_start; | ||
| 1956 | tid->baw_tail = tid->baw_head; | ||
| 1957 | } | ||
| 1958 | |||
| 1959 | /* | ||
| 1960 | * Drain all pending buffers | ||
| 1961 | * NB: must be called with txq lock held | ||
| 1962 | */ | ||
| 1963 | |||
| 1964 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, | ||
| 1965 | struct ath_txq *txq, | ||
| 1966 | bool bh_flag) | ||
| 1967 | { | ||
| 1968 | struct ath_atx_ac *ac, *ac_tmp; | ||
| 1969 | struct ath_atx_tid *tid, *tid_tmp; | ||
| 1970 | |||
| 1971 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { | ||
| 1972 | list_del(&ac->list); | ||
| 1973 | ac->sched = false; | ||
| 1974 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | ||
| 1975 | list_del(&tid->list); | ||
| 1976 | tid->sched = false; | ||
| 1977 | ath_tid_drain(sc, txq, tid, bh_flag); | ||
| 1978 | } | ||
| 1979 | } | ||
| 1980 | } | ||
| 1981 | |||
| 1982 | static int ath_tx_start_dma(struct ath_softc *sc, | ||
| 1983 | struct sk_buff *skb, | ||
| 1984 | struct scatterlist *sg, | ||
| 1985 | u32 n_sg, | ||
| 1986 | struct ath_tx_control *txctl) | ||
| 1987 | { | ||
| 1988 | struct ath_node *an = txctl->an; | ||
| 1989 | struct ath_buf *bf = NULL; | ||
| 1990 | struct list_head bf_head; | ||
| 1991 | struct ath_desc *ds; | ||
| 1992 | struct ath_hal *ah = sc->sc_ah; | ||
| 1993 | struct ath_txq *txq = &sc->sc_txq[txctl->qnum]; | ||
| 1994 | struct ath_tx_info_priv *tx_info_priv; | ||
| 1995 | struct ath_rc_series *rcs; | ||
| 1996 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | ||
| 1997 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | ||
| 1998 | __le16 fc = hdr->frame_control; | ||
| 1999 | |||
| 2000 | /* For each sglist entry, allocate an ath_buf for DMA */ | ||
| 2001 | INIT_LIST_HEAD(&bf_head); | ||
| 2002 | spin_lock_bh(&sc->sc_txbuflock); | ||
| 2003 | if (unlikely(list_empty(&sc->sc_txbuf))) { | ||
| 2004 | spin_unlock_bh(&sc->sc_txbuflock); | ||
| 2005 | return -ENOMEM; | ||
| 2006 | } | ||
| 2007 | |||
| 2008 | bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list); | ||
| 2009 | list_del(&bf->list); | ||
| 2010 | spin_unlock_bh(&sc->sc_txbuflock); | ||
| 2011 | |||
| 2012 | list_add_tail(&bf->list, &bf_head); | ||
| 2013 | |||
| 2014 | /* set up this buffer */ | ||
| 2015 | ATH_TXBUF_RESET(bf); | ||
| 2016 | bf->bf_frmlen = txctl->frmlen; | ||
| 2017 | bf->bf_isdata = ieee80211_is_data(fc); | ||
| 2018 | bf->bf_isbar = ieee80211_is_back_req(fc); | ||
| 2019 | bf->bf_ispspoll = ieee80211_is_pspoll(fc); | ||
| 2020 | bf->bf_flags = txctl->flags; | ||
| 2021 | bf->bf_shpreamble = sc->sc_flags & ATH_PREAMBLE_SHORT; | ||
| 2022 | bf->bf_keytype = txctl->keytype; | ||
| 2023 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0]; | ||
| 2024 | rcs = tx_info_priv->rcs; | ||
| 2025 | bf->bf_rcs[0] = rcs[0]; | ||
| 2026 | bf->bf_rcs[1] = rcs[1]; | ||
| 2027 | bf->bf_rcs[2] = rcs[2]; | ||
| 2028 | bf->bf_rcs[3] = rcs[3]; | ||
| 2029 | bf->bf_node = an; | ||
| 2030 | bf->bf_mpdu = skb; | ||
| 2031 | bf->bf_buf_addr = sg_dma_address(sg); | ||
| 2032 | |||
| 2033 | /* setup descriptor */ | ||
| 2034 | ds = bf->bf_desc; | ||
| 2035 | ds->ds_link = 0; | ||
| 2036 | ds->ds_data = bf->bf_buf_addr; | ||
| 2037 | |||
| 2038 | /* | ||
| 2039 | * Save the DMA context in the first ath_buf | ||
| 2040 | */ | ||
| 2041 | copy_dma_mem_context(get_dma_mem_context(bf, bf_dmacontext), | ||
| 2042 | get_dma_mem_context(txctl, dmacontext)); | ||
| 2043 | |||
| 2044 | /* | ||
| 2045 | * Formulate first tx descriptor with tx controls. | ||
| 2046 | */ | ||
| 2047 | ath9k_hw_set11n_txdesc(ah, | ||
| 2048 | ds, | ||
| 2049 | bf->bf_frmlen, /* frame length */ | ||
| 2050 | txctl->atype, /* Atheros packet type */ | ||
| 2051 | min(txctl->txpower, (u16)60), /* txpower */ | ||
| 2052 | txctl->keyix, /* key cache index */ | ||
| 2053 | txctl->keytype, /* key type */ | ||
| 2054 | txctl->flags); /* flags */ | ||
| 2055 | ath9k_hw_filltxdesc(ah, | ||
| 2056 | ds, | ||
| 2057 | sg_dma_len(sg), /* segment length */ | ||
| 2058 | true, /* first segment */ | ||
| 2059 | (n_sg == 1) ? true : false, /* last segment */ | ||
| 2060 | ds); /* first descriptor */ | ||
| 2061 | |||
| 2062 | bf->bf_lastfrm = bf; | ||
| 2063 | bf->bf_ht = txctl->ht; | ||
| 2064 | |||
| 2065 | spin_lock_bh(&txq->axq_lock); | ||
| 2066 | |||
| 2067 | if (txctl->ht && sc->sc_txaggr) { | ||
| 2068 | struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno); | ||
| 2069 | if (ath_aggr_query(sc, an, txctl->tidno)) { | ||
| 2070 | /* | ||
| 2071 | * Try aggregation if it's a unicast data frame | ||
| 2072 | * and the destination is HT capable. | ||
| 2073 | */ | ||
| 2074 | ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl); | ||
| 2075 | } else { | ||
| 2076 | /* | ||
| 2077 | * Send this frame as regular when ADDBA exchange | ||
| 2078 | * is neither complete nor pending. | ||
| 2079 | */ | ||
| 2080 | ath_tx_send_normal(sc, txq, tid, &bf_head); | ||
| 2081 | } | ||
| 2082 | } else { | ||
| 2083 | bf->bf_lastbf = bf; | ||
| 2084 | bf->bf_nframes = 1; | ||
| 2085 | ath_buf_set_rate(sc, bf); | ||
| 2086 | |||
| 2087 | if (ieee80211_is_back_req(fc)) { | ||
| 2088 | /* This is required for resuming tid | ||
| 2089 | * during BAR completion */ | ||
| 2090 | bf->bf_tidno = txctl->tidno; | ||
| 2091 | } | ||
| 2092 | |||
| 2093 | if (is_multicast_ether_addr(hdr->addr1)) { | ||
| 2094 | struct ath_vap *avp = sc->sc_vaps[txctl->if_id]; | ||
| 2095 | |||
| 2096 | /* | ||
| 2097 | * When servicing one or more stations in power-save | ||
| 2098 | * mode (or) if there is some mcast data waiting on | ||
| 2099 | * mcast queue (to prevent out of order delivery of | ||
| 2100 | * mcast,bcast packets) multicast frames must be | ||
| 2101 | * buffered until after the beacon. We use the private | ||
| 2102 | * mcast queue for that. | ||
| 2103 | */ | ||
| 2104 | /* XXX? more bit in 802.11 frame header */ | ||
| 2105 | spin_lock_bh(&avp->av_mcastq.axq_lock); | ||
| 2106 | if (txctl->ps || avp->av_mcastq.axq_depth) | ||
| 2107 | ath_tx_mcastqaddbuf(sc, | ||
| 2108 | &avp->av_mcastq, &bf_head); | ||
| 2109 | else | ||
| 2110 | ath_tx_txqaddbuf(sc, txq, &bf_head); | ||
| 2111 | spin_unlock_bh(&avp->av_mcastq.axq_lock); | ||
| 2112 | } else | ||
| 2113 | ath_tx_txqaddbuf(sc, txq, &bf_head); | ||
| 2114 | } | ||
| 2115 | spin_unlock_bh(&txq->axq_lock); | ||
| 2116 | return 0; | ||
| 2117 | } | ||
| 2118 | |||
| 2119 | static void xmit_map_sg(struct ath_softc *sc, | ||
| 2120 | struct sk_buff *skb, | ||
| 2121 | dma_addr_t *pa, | ||
| 2122 | struct ath_tx_control *txctl) | ||
| 2123 | { | ||
| 2124 | struct ath_xmit_status tx_status; | ||
| 2125 | struct ath_atx_tid *tid; | ||
| 2126 | struct scatterlist sg; | ||
| 2127 | |||
| 2128 | *pa = pci_map_single(sc->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); | ||
| 2129 | |||
| 2130 | /* setup S/G list */ | ||
| 2131 | memset(&sg, 0, sizeof(struct scatterlist)); | ||
| 2132 | sg_dma_address(&sg) = *pa; | ||
| 2133 | sg_dma_len(&sg) = skb->len; | ||
| 2134 | |||
| 2135 | if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) { | ||
| 2136 | /* | ||
| 2137 | * We have to do drop frame here. | ||
| 2138 | */ | ||
| 2139 | pci_unmap_single(sc->pdev, *pa, skb->len, PCI_DMA_TODEVICE); | ||
| 2140 | |||
| 2141 | tx_status.retries = 0; | ||
| 2142 | tx_status.flags = ATH_TX_ERROR; | ||
| 2143 | |||
| 2144 | if (txctl->ht && sc->sc_txaggr) { | ||
| 2145 | /* Reclaim the seqno. */ | ||
| 2146 | tid = ATH_AN_2_TID((struct ath_node *) | ||
| 2147 | txctl->an, txctl->tidno); | ||
| 2148 | DECR(tid->seq_next, IEEE80211_SEQ_MAX); | ||
| 2149 | } | ||
| 2150 | ath_tx_complete(sc, skb, &tx_status, txctl->an); | ||
| 2151 | } | ||
| 2152 | } | ||
| 2153 | |||
| 2154 | /* Initialize TX queue and h/w */ | ||
| 2155 | |||
| 2156 | int ath_tx_init(struct ath_softc *sc, int nbufs) | ||
| 2157 | { | ||
| 2158 | int error = 0; | ||
| 2159 | |||
| 2160 | do { | ||
| 2161 | spin_lock_init(&sc->sc_txbuflock); | ||
| 2162 | |||
| 2163 | /* Setup tx descriptors */ | ||
| 2164 | error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, | ||
| 2165 | "tx", nbufs * ATH_FRAG_PER_MSDU, ATH_TXDESC); | ||
| 2166 | if (error != 0) { | ||
| 2167 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 2168 | "%s: failed to allocate tx descriptors: %d\n", | ||
| 2169 | __func__, error); | ||
| 2170 | break; | ||
| 2171 | } | ||
| 2172 | |||
| 2173 | /* XXX allocate beacon state together with vap */ | ||
| 2174 | error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, | ||
| 2175 | "beacon", ATH_BCBUF, 1); | ||
| 2176 | if (error != 0) { | ||
| 2177 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 2178 | "%s: failed to allocate " | ||
| 2179 | "beacon descripotrs: %d\n", | ||
| 2180 | __func__, error); | ||
| 2181 | break; | ||
| 2182 | } | ||
| 2183 | |||
| 2184 | } while (0); | ||
| 2185 | |||
| 2186 | if (error != 0) | ||
| 2187 | ath_tx_cleanup(sc); | ||
| 2188 | |||
| 2189 | return error; | ||
| 2190 | } | ||
| 2191 | |||
| 2192 | /* Reclaim all tx queue resources */ | ||
| 2193 | |||
| 2194 | int ath_tx_cleanup(struct ath_softc *sc) | ||
| 2195 | { | ||
| 2196 | /* cleanup beacon descriptors */ | ||
| 2197 | if (sc->sc_bdma.dd_desc_len != 0) | ||
| 2198 | ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); | ||
| 2199 | |||
| 2200 | /* cleanup tx descriptors */ | ||
| 2201 | if (sc->sc_txdma.dd_desc_len != 0) | ||
| 2202 | ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); | ||
| 2203 | |||
| 2204 | return 0; | ||
| 2205 | } | ||
| 2206 | |||
| 2207 | /* Setup a h/w transmit queue */ | ||
| 2208 | |||
| 2209 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) | ||
| 2210 | { | ||
| 2211 | struct ath_hal *ah = sc->sc_ah; | ||
| 2212 | struct ath9k_tx_queue_info qi; | ||
| 2213 | int qnum; | ||
| 2214 | |||
| 2215 | memzero(&qi, sizeof(qi)); | ||
| 2216 | qi.tqi_subtype = subtype; | ||
| 2217 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | ||
| 2218 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | ||
| 2219 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | ||
| 2220 | qi.tqi_physCompBuf = 0; | ||
| 2221 | |||
| 2222 | /* | ||
| 2223 | * Enable interrupts only for EOL and DESC conditions. | ||
| 2224 | * We mark tx descriptors to receive a DESC interrupt | ||
| 2225 | * when a tx queue gets deep; otherwise waiting for the | ||
| 2226 | * EOL to reap descriptors. Note that this is done to | ||
| 2227 | * reduce interrupt load and this only defers reaping | ||
| 2228 | * descriptors, never transmitting frames. Aside from | ||
| 2229 | * reducing interrupts this also permits more concurrency. | ||
| 2230 | * The only potential downside is if the tx queue backs | ||
| 2231 | * up in which case the top half of the kernel may backup | ||
| 2232 | * due to a lack of tx descriptors. | ||
| 2233 | * | ||
| 2234 | * The UAPSD queue is an exception, since we take a desc- | ||
| 2235 | * based intr on the EOSP frames. | ||
| 2236 | */ | ||
| 2237 | if (qtype == ATH9K_TX_QUEUE_UAPSD) | ||
| 2238 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | ||
| 2239 | else | ||
| 2240 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | ||
| 2241 | TXQ_FLAG_TXDESCINT_ENABLE; | ||
| 2242 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | ||
| 2243 | if (qnum == -1) { | ||
| 2244 | /* | ||
| 2245 | * NB: don't print a message, this happens | ||
| 2246 | * normally on parts with too few tx queues | ||
| 2247 | */ | ||
| 2248 | return NULL; | ||
| 2249 | } | ||
| 2250 | if (qnum >= ARRAY_SIZE(sc->sc_txq)) { | ||
| 2251 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 2252 | "%s: hal qnum %u out of range, max %u!\n", | ||
| 2253 | __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq)); | ||
| 2254 | ath9k_hw_releasetxqueue(ah, qnum); | ||
| 2255 | return NULL; | ||
| 2256 | } | ||
| 2257 | if (!ATH_TXQ_SETUP(sc, qnum)) { | ||
| 2258 | struct ath_txq *txq = &sc->sc_txq[qnum]; | ||
| 2259 | |||
| 2260 | txq->axq_qnum = qnum; | ||
| 2261 | txq->axq_link = NULL; | ||
| 2262 | INIT_LIST_HEAD(&txq->axq_q); | ||
| 2263 | INIT_LIST_HEAD(&txq->axq_acq); | ||
| 2264 | spin_lock_init(&txq->axq_lock); | ||
| 2265 | txq->axq_depth = 0; | ||
| 2266 | txq->axq_aggr_depth = 0; | ||
| 2267 | txq->axq_totalqueued = 0; | ||
| 2268 | txq->axq_intrcnt = 0; | ||
| 2269 | txq->axq_linkbuf = NULL; | ||
| 2270 | sc->sc_txqsetup |= 1<<qnum; | ||
| 2271 | } | ||
| 2272 | return &sc->sc_txq[qnum]; | ||
| 2273 | } | ||
| 2274 | |||
| 2275 | /* Reclaim resources for a setup queue */ | ||
| 2276 | |||
| 2277 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) | ||
| 2278 | { | ||
| 2279 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); | ||
| 2280 | sc->sc_txqsetup &= ~(1<<txq->axq_qnum); | ||
| 2281 | } | ||
| 2282 | |||
| 2283 | /* | ||
| 2284 | * Setup a hardware data transmit queue for the specified | ||
| 2285 | * access control. The hal may not support all requested | ||
| 2286 | * queues in which case it will return a reference to a | ||
| 2287 | * previously setup queue. We record the mapping from ac's | ||
| 2288 | * to h/w queues for use by ath_tx_start and also track | ||
| 2289 | * the set of h/w queues being used to optimize work in the | ||
| 2290 | * transmit interrupt handler and related routines. | ||
| 2291 | */ | ||
| 2292 | |||
| 2293 | int ath_tx_setup(struct ath_softc *sc, int haltype) | ||
| 2294 | { | ||
| 2295 | struct ath_txq *txq; | ||
| 2296 | |||
| 2297 | if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { | ||
| 2298 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 2299 | "%s: HAL AC %u out of range, max %zu!\n", | ||
| 2300 | __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q)); | ||
| 2301 | return 0; | ||
| 2302 | } | ||
| 2303 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | ||
| 2304 | if (txq != NULL) { | ||
| 2305 | sc->sc_haltype2q[haltype] = txq->axq_qnum; | ||
| 2306 | return 1; | ||
| 2307 | } else | ||
| 2308 | return 0; | ||
| 2309 | } | ||
| 2310 | |||
| 2311 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) | ||
| 2312 | { | ||
| 2313 | int qnum; | ||
| 2314 | |||
| 2315 | switch (qtype) { | ||
| 2316 | case ATH9K_TX_QUEUE_DATA: | ||
| 2317 | if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { | ||
| 2318 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 2319 | "%s: HAL AC %u out of range, max %zu!\n", | ||
| 2320 | __func__, | ||
| 2321 | haltype, ARRAY_SIZE(sc->sc_haltype2q)); | ||
| 2322 | return -1; | ||
| 2323 | } | ||
| 2324 | qnum = sc->sc_haltype2q[haltype]; | ||
| 2325 | break; | ||
| 2326 | case ATH9K_TX_QUEUE_BEACON: | ||
| 2327 | qnum = sc->sc_bhalq; | ||
| 2328 | break; | ||
| 2329 | case ATH9K_TX_QUEUE_CAB: | ||
| 2330 | qnum = sc->sc_cabq->axq_qnum; | ||
| 2331 | break; | ||
| 2332 | default: | ||
| 2333 | qnum = -1; | ||
| 2334 | } | ||
| 2335 | return qnum; | ||
| 2336 | } | ||
| 2337 | |||
| 2338 | /* Update parameters for a transmit queue */ | ||
| 2339 | |||
| 2340 | int ath_txq_update(struct ath_softc *sc, int qnum, | ||
| 2341 | struct ath9k_tx_queue_info *qinfo) | ||
| 2342 | { | ||
| 2343 | struct ath_hal *ah = sc->sc_ah; | ||
| 2344 | int error = 0; | ||
| 2345 | struct ath9k_tx_queue_info qi; | ||
| 2346 | |||
| 2347 | if (qnum == sc->sc_bhalq) { | ||
| 2348 | /* | ||
| 2349 | * XXX: for beacon queue, we just save the parameter. | ||
| 2350 | * It will be picked up by ath_beaconq_config when | ||
| 2351 | * it's necessary. | ||
| 2352 | */ | ||
| 2353 | sc->sc_beacon_qi = *qinfo; | ||
| 2354 | return 0; | ||
| 2355 | } | ||
| 2356 | |||
| 2357 | ASSERT(sc->sc_txq[qnum].axq_qnum == qnum); | ||
| 2358 | |||
| 2359 | ath9k_hw_get_txq_props(ah, qnum, &qi); | ||
| 2360 | qi.tqi_aifs = qinfo->tqi_aifs; | ||
| 2361 | qi.tqi_cwmin = qinfo->tqi_cwmin; | ||
| 2362 | qi.tqi_cwmax = qinfo->tqi_cwmax; | ||
| 2363 | qi.tqi_burstTime = qinfo->tqi_burstTime; | ||
| 2364 | qi.tqi_readyTime = qinfo->tqi_readyTime; | ||
| 2365 | |||
| 2366 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | ||
| 2367 | DPRINTF(sc, ATH_DBG_FATAL, | ||
| 2368 | "%s: unable to update hardware queue %u!\n", | ||
| 2369 | __func__, qnum); | ||
| 2370 | error = -EIO; | ||
| 2371 | } else { | ||
| 2372 | ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */ | ||
| 2373 | } | ||
| 2374 | |||
| 2375 | return error; | ||
| 2376 | } | ||
| 2377 | |||
| 2378 | int ath_cabq_update(struct ath_softc *sc) | ||
| 2379 | { | ||
| 2380 | struct ath9k_tx_queue_info qi; | ||
| 2381 | int qnum = sc->sc_cabq->axq_qnum; | ||
| 2382 | struct ath_beacon_config conf; | ||
| 2383 | |||
| 2384 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); | ||
| 2385 | /* | ||
| 2386 | * Ensure the readytime % is within the bounds. | ||
| 2387 | */ | ||
| 2388 | if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) | ||
| 2389 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | ||
| 2390 | else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | ||
| 2391 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | ||
| 2392 | |||
| 2393 | ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf); | ||
| 2394 | qi.tqi_readyTime = | ||
| 2395 | (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100; | ||
| 2396 | ath_txq_update(sc, qnum, &qi); | ||
| 2397 | |||
| 2398 | return 0; | ||
| 2399 | } | ||
| 2400 | |||
| 2401 | int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb) | ||
| 2402 | { | ||
| 2403 | struct ath_tx_control txctl; | ||
| 2404 | int error = 0; | ||
| 2405 | |||
| 2406 | error = ath_tx_prepare(sc, skb, &txctl); | ||
| 2407 | if (error == 0) | ||
| 2408 | /* | ||
| 2409 | * Start DMA mapping. | ||
| 2410 | * ath_tx_start_dma() will be called either synchronously | ||
| 2411 | * or asynchrounsly once DMA is complete. | ||
| 2412 | */ | ||
| 2413 | xmit_map_sg(sc, skb, | ||
| 2414 | get_dma_mem_context(&txctl, dmacontext), | ||
| 2415 | &txctl); | ||
| 2416 | else | ||
| 2417 | ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE); | ||
| 2418 | |||
| 2419 | /* failed packets will be dropped by the caller */ | ||
| 2420 | return error; | ||
| 2421 | } | ||
| 2422 | |||
| 2423 | /* Deferred processing of transmit interrupt */ | ||
| 2424 | |||
| 2425 | void ath_tx_tasklet(struct ath_softc *sc) | ||
| 2426 | { | ||
| 2427 | u64 tsf = ath9k_hw_gettsf64(sc->sc_ah); | ||
| 2428 | int i, nacked = 0; | ||
| 2429 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | ||
| 2430 | |||
| 2431 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); | ||
| 2432 | |||
| 2433 | /* | ||
| 2434 | * Process each active queue. | ||
| 2435 | */ | ||
| 2436 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | ||
| 2437 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | ||
| 2438 | nacked += ath_tx_processq(sc, &sc->sc_txq[i]); | ||
| 2439 | } | ||
| 2440 | if (nacked) | ||
| 2441 | sc->sc_lastrx = tsf; | ||
| 2442 | } | ||
| 2443 | |||
| 2444 | void ath_tx_draintxq(struct ath_softc *sc, | ||
| 2445 | struct ath_txq *txq, bool retry_tx) | ||
| 2446 | { | ||
| 2447 | struct ath_buf *bf, *lastbf; | ||
| 2448 | struct list_head bf_head; | ||
| 2449 | |||
| 2450 | INIT_LIST_HEAD(&bf_head); | ||
| 2451 | |||
| 2452 | /* | ||
| 2453 | * NB: this assumes output has been stopped and | ||
| 2454 | * we do not need to block ath_tx_tasklet | ||
| 2455 | */ | ||
| 2456 | for (;;) { | ||
| 2457 | spin_lock_bh(&txq->axq_lock); | ||
| 2458 | |||
| 2459 | if (list_empty(&txq->axq_q)) { | ||
| 2460 | txq->axq_link = NULL; | ||
| 2461 | txq->axq_linkbuf = NULL; | ||
| 2462 | spin_unlock_bh(&txq->axq_lock); | ||
| 2463 | break; | ||
| 2464 | } | ||
| 2465 | |||
| 2466 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); | ||
| 2467 | |||
| 2468 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | ||
| 2469 | list_del(&bf->list); | ||
| 2470 | spin_unlock_bh(&txq->axq_lock); | ||
| 2471 | |||
| 2472 | spin_lock_bh(&sc->sc_txbuflock); | ||
| 2473 | list_add_tail(&bf->list, &sc->sc_txbuf); | ||
| 2474 | spin_unlock_bh(&sc->sc_txbuflock); | ||
| 2475 | continue; | ||
| 2476 | } | ||
| 2477 | |||
| 2478 | lastbf = bf->bf_lastbf; | ||
| 2479 | if (!retry_tx) | ||
| 2480 | lastbf->bf_desc->ds_txstat.ts_flags = | ||
| 2481 | ATH9K_TX_SW_ABORTED; | ||
| 2482 | |||
| 2483 | /* remove ath_buf's of the same mpdu from txq */ | ||
| 2484 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | ||
| 2485 | txq->axq_depth--; | ||
| 2486 | |||
| 2487 | spin_unlock_bh(&txq->axq_lock); | ||
| 2488 | |||
| 2489 | if (bf->bf_isampdu) | ||
| 2490 | ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0); | ||
| 2491 | else | ||
| 2492 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | ||
| 2493 | } | ||
| 2494 | |||
| 2495 | /* flush any pending frames if aggregation is enabled */ | ||
| 2496 | if (sc->sc_txaggr) { | ||
| 2497 | if (!retry_tx) { | ||
| 2498 | spin_lock_bh(&txq->axq_lock); | ||
| 2499 | ath_txq_drain_pending_buffers(sc, txq, | ||
| 2500 | ATH9K_BH_STATUS_CHANGE); | ||
| 2501 | spin_unlock_bh(&txq->axq_lock); | ||
| 2502 | } | ||
| 2503 | } | ||
| 2504 | } | ||
| 2505 | |||
| 2506 | /* Drain the transmit queues and reclaim resources */ | ||
| 2507 | |||
| 2508 | void ath_draintxq(struct ath_softc *sc, bool retry_tx) | ||
| 2509 | { | ||
| 2510 | /* stop beacon queue. The beacon will be freed when | ||
| 2511 | * we go to INIT state */ | ||
| 2512 | if (!sc->sc_invalid) { | ||
| 2513 | (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); | ||
| 2514 | DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__, | ||
| 2515 | ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq)); | ||
| 2516 | } | ||
| 2517 | |||
| 2518 | ath_drain_txdataq(sc, retry_tx); | ||
| 2519 | } | ||
| 2520 | |||
| 2521 | u32 ath_txq_depth(struct ath_softc *sc, int qnum) | ||
| 2522 | { | ||
| 2523 | return sc->sc_txq[qnum].axq_depth; | ||
| 2524 | } | ||
| 2525 | |||
| 2526 | u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum) | ||
| 2527 | { | ||
| 2528 | return sc->sc_txq[qnum].axq_aggr_depth; | ||
| 2529 | } | ||
| 2530 | |||
| 2531 | /* Check if an ADDBA is required. A valid node must be passed. */ | ||
| 2532 | enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc, | ||
| 2533 | struct ath_node *an, | ||
| 2534 | u8 tidno) | ||
| 2535 | { | ||
| 2536 | struct ath_atx_tid *txtid; | ||
| 2537 | DECLARE_MAC_BUF(mac); | ||
| 2538 | |||
| 2539 | if (!sc->sc_txaggr) | ||
| 2540 | return AGGR_NOT_REQUIRED; | ||
| 2541 | |||
| 2542 | /* ADDBA exchange must be completed before sending aggregates */ | ||
| 2543 | txtid = ATH_AN_2_TID(an, tidno); | ||
| 2544 | |||
| 2545 | if (txtid->addba_exchangecomplete) | ||
| 2546 | return AGGR_EXCHANGE_DONE; | ||
| 2547 | |||
| 2548 | if (txtid->cleanup_inprogress) | ||
| 2549 | return AGGR_CLEANUP_PROGRESS; | ||
| 2550 | |||
| 2551 | if (txtid->addba_exchangeinprogress) | ||
| 2552 | return AGGR_EXCHANGE_PROGRESS; | ||
| 2553 | |||
| 2554 | if (!txtid->addba_exchangecomplete) { | ||
| 2555 | if (!txtid->addba_exchangeinprogress && | ||
| 2556 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | ||
| 2557 | txtid->addba_exchangeattempts++; | ||
| 2558 | return AGGR_REQUIRED; | ||
| 2559 | } | ||
| 2560 | } | ||
| 2561 | |||
| 2562 | return AGGR_NOT_REQUIRED; | ||
| 2563 | } | ||
| 2564 | |||
| 2565 | /* Start TX aggregation */ | ||
| 2566 | |||
| 2567 | int ath_tx_aggr_start(struct ath_softc *sc, | ||
| 2568 | const u8 *addr, | ||
| 2569 | u16 tid, | ||
| 2570 | u16 *ssn) | ||
| 2571 | { | ||
| 2572 | struct ath_atx_tid *txtid; | ||
| 2573 | struct ath_node *an; | ||
| 2574 | |||
| 2575 | spin_lock_bh(&sc->node_lock); | ||
| 2576 | an = ath_node_find(sc, (u8 *) addr); | ||
| 2577 | spin_unlock_bh(&sc->node_lock); | ||
| 2578 | |||
| 2579 | if (!an) { | ||
| 2580 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 2581 | "%s: Node not found to initialize " | ||
| 2582 | "TX aggregation\n", __func__); | ||
| 2583 | return -1; | ||
| 2584 | } | ||
| 2585 | |||
| 2586 | if (sc->sc_txaggr) { | ||
| 2587 | txtid = ATH_AN_2_TID(an, tid); | ||
| 2588 | txtid->addba_exchangeinprogress = 1; | ||
| 2589 | ath_tx_pause_tid(sc, txtid); | ||
| 2590 | } | ||
| 2591 | |||
| 2592 | return 0; | ||
| 2593 | } | ||
| 2594 | |||
| 2595 | /* Stop tx aggregation */ | ||
| 2596 | |||
| 2597 | int ath_tx_aggr_stop(struct ath_softc *sc, | ||
| 2598 | const u8 *addr, | ||
| 2599 | u16 tid) | ||
| 2600 | { | ||
| 2601 | struct ath_node *an; | ||
| 2602 | |||
| 2603 | spin_lock_bh(&sc->node_lock); | ||
| 2604 | an = ath_node_find(sc, (u8 *) addr); | ||
| 2605 | spin_unlock_bh(&sc->node_lock); | ||
| 2606 | |||
| 2607 | if (!an) { | ||
| 2608 | DPRINTF(sc, ATH_DBG_AGGR, | ||
| 2609 | "%s: TX aggr stop for non-existent node\n", __func__); | ||
| 2610 | return -1; | ||
| 2611 | } | ||
| 2612 | |||
| 2613 | ath_tx_aggr_teardown(sc, an, tid); | ||
| 2614 | return 0; | ||
| 2615 | } | ||
| 2616 | |||
| 2617 | /* | ||
| 2618 | * Performs transmit side cleanup when TID changes from aggregated to | ||
| 2619 | * unaggregated. | ||
| 2620 | * - Pause the TID and mark cleanup in progress | ||
| 2621 | * - Discard all retry frames from the s/w queue. | ||
| 2622 | */ | ||
| 2623 | |||
| 2624 | void ath_tx_aggr_teardown(struct ath_softc *sc, | ||
| 2625 | struct ath_node *an, u8 tid) | ||
| 2626 | { | ||
| 2627 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | ||
| 2628 | struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum]; | ||
| 2629 | struct ath_buf *bf; | ||
| 2630 | struct list_head bf_head; | ||
| 2631 | INIT_LIST_HEAD(&bf_head); | ||
| 2632 | |||
| 2633 | DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__); | ||
| 2634 | |||
| 2635 | if (txtid->cleanup_inprogress) /* cleanup is in progress */ | ||
| 2636 | return; | ||
| 2637 | |||
| 2638 | if (!txtid->addba_exchangecomplete) { | ||
| 2639 | txtid->addba_exchangeattempts = 0; | ||
| 2640 | return; | ||
| 2641 | } | ||
| 2642 | |||
| 2643 | /* TID must be paused first */ | ||
| 2644 | ath_tx_pause_tid(sc, txtid); | ||
| 2645 | |||
| 2646 | /* drop all software retried frames and mark this TID */ | ||
| 2647 | spin_lock_bh(&txq->axq_lock); | ||
| 2648 | while (!list_empty(&txtid->buf_q)) { | ||
| 2649 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | ||
| 2650 | if (!bf->bf_isretried) { | ||
| 2651 | /* | ||
| 2652 | * NB: it's based on the assumption that | ||
| 2653 | * software retried frame will always stay | ||
| 2654 | * at the head of software queue. | ||
| 2655 | */ | ||
| 2656 | break; | ||
| 2657 | } | ||
| 2658 | list_cut_position(&bf_head, | ||
| 2659 | &txtid->buf_q, &bf->bf_lastfrm->list); | ||
| 2660 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); | ||
| 2661 | |||
| 2662 | /* complete this sub-frame */ | ||
| 2663 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | ||
| 2664 | } | ||
| 2665 | |||
| 2666 | if (txtid->baw_head != txtid->baw_tail) { | ||
| 2667 | spin_unlock_bh(&txq->axq_lock); | ||
| 2668 | txtid->cleanup_inprogress = true; | ||
| 2669 | } else { | ||
| 2670 | txtid->addba_exchangecomplete = 0; | ||
| 2671 | txtid->addba_exchangeattempts = 0; | ||
| 2672 | spin_unlock_bh(&txq->axq_lock); | ||
| 2673 | ath_tx_flush_tid(sc, txtid); | ||
| 2674 | } | ||
| 2675 | } | ||
| 2676 | |||
| 2677 | /* | ||
| 2678 | * Tx scheduling logic | ||
| 2679 | * NB: must be called with txq lock held | ||
| 2680 | */ | ||
| 2681 | |||
| 2682 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) | ||
| 2683 | { | ||
| 2684 | struct ath_atx_ac *ac; | ||
| 2685 | struct ath_atx_tid *tid; | ||
| 2686 | |||
| 2687 | /* nothing to schedule */ | ||
| 2688 | if (list_empty(&txq->axq_acq)) | ||
| 2689 | return; | ||
| 2690 | /* | ||
| 2691 | * get the first node/ac pair on the queue | ||
| 2692 | */ | ||
| 2693 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); | ||
| 2694 | list_del(&ac->list); | ||
| 2695 | ac->sched = false; | ||
| 2696 | |||
| 2697 | /* | ||
| 2698 | * process a single tid per destination | ||
| 2699 | */ | ||
| 2700 | do { | ||
| 2701 | /* nothing to schedule */ | ||
| 2702 | if (list_empty(&ac->tid_q)) | ||
| 2703 | return; | ||
| 2704 | |||
| 2705 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); | ||
| 2706 | list_del(&tid->list); | ||
| 2707 | tid->sched = false; | ||
| 2708 | |||
| 2709 | if (tid->paused) /* check next tid to keep h/w busy */ | ||
| 2710 | continue; | ||
| 2711 | |||
| 2712 | if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) || | ||
| 2713 | ((txq->axq_depth % 2) == 0)) { | ||
| 2714 | ath_tx_sched_aggr(sc, txq, tid); | ||
| 2715 | } | ||
| 2716 | |||
| 2717 | /* | ||
| 2718 | * add tid to round-robin queue if more frames | ||
| 2719 | * are pending for the tid | ||
| 2720 | */ | ||
| 2721 | if (!list_empty(&tid->buf_q)) | ||
| 2722 | ath_tx_queue_tid(txq, tid); | ||
| 2723 | |||
| 2724 | /* only schedule one TID at a time */ | ||
| 2725 | break; | ||
| 2726 | } while (!list_empty(&ac->tid_q)); | ||
| 2727 | |||
| 2728 | /* | ||
| 2729 | * schedule AC if more TIDs need processing | ||
| 2730 | */ | ||
| 2731 | if (!list_empty(&ac->tid_q)) { | ||
| 2732 | /* | ||
| 2733 | * add dest ac to txq if not already added | ||
| 2734 | */ | ||
| 2735 | if (!ac->sched) { | ||
| 2736 | ac->sched = true; | ||
| 2737 | list_add_tail(&ac->list, &txq->axq_acq); | ||
| 2738 | } | ||
| 2739 | } | ||
| 2740 | } | ||
| 2741 | |||
| 2742 | /* Initialize per-node transmit state */ | ||
| 2743 | |||
| 2744 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | ||
| 2745 | { | ||
| 2746 | if (sc->sc_txaggr) { | ||
| 2747 | struct ath_atx_tid *tid; | ||
| 2748 | struct ath_atx_ac *ac; | ||
| 2749 | int tidno, acno; | ||
| 2750 | |||
| 2751 | sc->sc_ht_info.maxampdu = ATH_AMPDU_LIMIT_DEFAULT; | ||
| 2752 | |||
| 2753 | /* | ||
| 2754 | * Init per tid tx state | ||
| 2755 | */ | ||
| 2756 | for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno]; | ||
| 2757 | tidno < WME_NUM_TID; | ||
| 2758 | tidno++, tid++) { | ||
| 2759 | tid->an = an; | ||
| 2760 | tid->tidno = tidno; | ||
| 2761 | tid->seq_start = tid->seq_next = 0; | ||
| 2762 | tid->baw_size = WME_MAX_BA; | ||
| 2763 | tid->baw_head = tid->baw_tail = 0; | ||
| 2764 | tid->sched = false; | ||
| 2765 | tid->paused = false; | ||
| 2766 | tid->cleanup_inprogress = false; | ||
| 2767 | INIT_LIST_HEAD(&tid->buf_q); | ||
| 2768 | |||
| 2769 | acno = TID_TO_WME_AC(tidno); | ||
| 2770 | tid->ac = &an->an_aggr.tx.ac[acno]; | ||
| 2771 | |||
| 2772 | /* ADDBA state */ | ||
| 2773 | tid->addba_exchangecomplete = 0; | ||
| 2774 | tid->addba_exchangeinprogress = 0; | ||
| 2775 | tid->addba_exchangeattempts = 0; | ||
| 2776 | } | ||
| 2777 | |||
| 2778 | /* | ||
| 2779 | * Init per ac tx state | ||
| 2780 | */ | ||
| 2781 | for (acno = 0, ac = &an->an_aggr.tx.ac[acno]; | ||
| 2782 | acno < WME_NUM_AC; acno++, ac++) { | ||
| 2783 | ac->sched = false; | ||
| 2784 | INIT_LIST_HEAD(&ac->tid_q); | ||
| 2785 | |||
| 2786 | switch (acno) { | ||
| 2787 | case WME_AC_BE: | ||
| 2788 | ac->qnum = ath_tx_get_qnum(sc, | ||
| 2789 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | ||
| 2790 | break; | ||
| 2791 | case WME_AC_BK: | ||
| 2792 | ac->qnum = ath_tx_get_qnum(sc, | ||
| 2793 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | ||
| 2794 | break; | ||
| 2795 | case WME_AC_VI: | ||
| 2796 | ac->qnum = ath_tx_get_qnum(sc, | ||
| 2797 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | ||
| 2798 | break; | ||
| 2799 | case WME_AC_VO: | ||
| 2800 | ac->qnum = ath_tx_get_qnum(sc, | ||
| 2801 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | ||
| 2802 | break; | ||
| 2803 | } | ||
| 2804 | } | ||
| 2805 | } | ||
| 2806 | } | ||
| 2807 | |||
| 2808 | /* Cleanupthe pending buffers for the node. */ | ||
| 2809 | |||
| 2810 | void ath_tx_node_cleanup(struct ath_softc *sc, | ||
| 2811 | struct ath_node *an, bool bh_flag) | ||
| 2812 | { | ||
| 2813 | int i; | ||
| 2814 | struct ath_atx_ac *ac, *ac_tmp; | ||
| 2815 | struct ath_atx_tid *tid, *tid_tmp; | ||
| 2816 | struct ath_txq *txq; | ||
| 2817 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | ||
| 2818 | if (ATH_TXQ_SETUP(sc, i)) { | ||
| 2819 | txq = &sc->sc_txq[i]; | ||
| 2820 | |||
| 2821 | if (likely(bh_flag)) | ||
| 2822 | spin_lock_bh(&txq->axq_lock); | ||
| 2823 | else | ||
| 2824 | spin_lock(&txq->axq_lock); | ||
| 2825 | |||
| 2826 | list_for_each_entry_safe(ac, | ||
| 2827 | ac_tmp, &txq->axq_acq, list) { | ||
| 2828 | tid = list_first_entry(&ac->tid_q, | ||
| 2829 | struct ath_atx_tid, list); | ||
| 2830 | if (tid && tid->an != an) | ||
| 2831 | continue; | ||
| 2832 | list_del(&ac->list); | ||
| 2833 | ac->sched = false; | ||
| 2834 | |||
| 2835 | list_for_each_entry_safe(tid, | ||
| 2836 | tid_tmp, &ac->tid_q, list) { | ||
| 2837 | list_del(&tid->list); | ||
| 2838 | tid->sched = false; | ||
| 2839 | ath_tid_drain(sc, txq, tid, bh_flag); | ||
| 2840 | tid->addba_exchangecomplete = 0; | ||
| 2841 | tid->addba_exchangeattempts = 0; | ||
| 2842 | tid->cleanup_inprogress = false; | ||
| 2843 | } | ||
| 2844 | } | ||
| 2845 | |||
| 2846 | if (likely(bh_flag)) | ||
| 2847 | spin_unlock_bh(&txq->axq_lock); | ||
| 2848 | else | ||
| 2849 | spin_unlock(&txq->axq_lock); | ||
| 2850 | } | ||
| 2851 | } | ||
| 2852 | } | ||
| 2853 | |||
| 2854 | /* Cleanup per node transmit state */ | ||
| 2855 | |||
| 2856 | void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an) | ||
| 2857 | { | ||
| 2858 | if (sc->sc_txaggr) { | ||
| 2859 | struct ath_atx_tid *tid; | ||
| 2860 | int tidno, i; | ||
| 2861 | |||
| 2862 | /* Init per tid rx state */ | ||
| 2863 | for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno]; | ||
| 2864 | tidno < WME_NUM_TID; | ||
| 2865 | tidno++, tid++) { | ||
| 2866 | |||
| 2867 | for (i = 0; i < ATH_TID_MAX_BUFS; i++) | ||
| 2868 | ASSERT(tid->tx_buf[i] == NULL); | ||
| 2869 | } | ||
| 2870 | } | ||
| 2871 | } | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index b8407d5704a1..ed09e48b1b61 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
| @@ -2719,7 +2719,7 @@ static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
| 2719 | { | 2719 | { |
| 2720 | struct iwl_priv *priv = hw->priv; | 2720 | struct iwl_priv *priv = hw->priv; |
| 2721 | 2721 | ||
| 2722 | IWL_DEBUG_MAC80211("enter\n"); | 2722 | IWL_DEBUG_MACDUMP("enter\n"); |
| 2723 | 2723 | ||
| 2724 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | 2724 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { |
| 2725 | IWL_DEBUG_MAC80211("leave - monitor\n"); | 2725 | IWL_DEBUG_MAC80211("leave - monitor\n"); |
| @@ -2733,7 +2733,7 @@ static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
| 2733 | if (iwl_tx_skb(priv, skb)) | 2733 | if (iwl_tx_skb(priv, skb)) |
| 2734 | dev_kfree_skb_any(skb); | 2734 | dev_kfree_skb_any(skb); |
| 2735 | 2735 | ||
| 2736 | IWL_DEBUG_MAC80211("leave\n"); | 2736 | IWL_DEBUG_MACDUMP("leave\n"); |
| 2737 | return 0; | 2737 | return 0; |
| 2738 | } | 2738 | } |
| 2739 | 2739 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-debug.h b/drivers/net/wireless/iwlwifi/iwl-debug.h index b4ffd33ef98c..d2daa174df22 100644 --- a/drivers/net/wireless/iwlwifi/iwl-debug.h +++ b/drivers/net/wireless/iwlwifi/iwl-debug.h | |||
| @@ -114,7 +114,7 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv) | |||
| 114 | #define IWL_DL_MAC80211 (1 << 1) | 114 | #define IWL_DL_MAC80211 (1 << 1) |
| 115 | #define IWL_DL_HOST_COMMAND (1 << 2) | 115 | #define IWL_DL_HOST_COMMAND (1 << 2) |
| 116 | #define IWL_DL_STATE (1 << 3) | 116 | #define IWL_DL_STATE (1 << 3) |
| 117 | 117 | #define IWL_DL_MACDUMP (1 << 4) | |
| 118 | #define IWL_DL_RADIO (1 << 7) | 118 | #define IWL_DL_RADIO (1 << 7) |
| 119 | #define IWL_DL_POWER (1 << 8) | 119 | #define IWL_DL_POWER (1 << 8) |
| 120 | #define IWL_DL_TEMP (1 << 9) | 120 | #define IWL_DL_TEMP (1 << 9) |
| @@ -154,6 +154,7 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv) | |||
| 154 | #define IWL_DEBUG_INFO(f, a...) IWL_DEBUG(IWL_DL_INFO, f, ## a) | 154 | #define IWL_DEBUG_INFO(f, a...) IWL_DEBUG(IWL_DL_INFO, f, ## a) |
| 155 | 155 | ||
| 156 | #define IWL_DEBUG_MAC80211(f, a...) IWL_DEBUG(IWL_DL_MAC80211, f, ## a) | 156 | #define IWL_DEBUG_MAC80211(f, a...) IWL_DEBUG(IWL_DL_MAC80211, f, ## a) |
| 157 | #define IWL_DEBUG_MACDUMP(f, a...) IWL_DEBUG(IWL_DL_MACDUMP, f, ## a) | ||
| 157 | #define IWL_DEBUG_TEMP(f, a...) IWL_DEBUG(IWL_DL_TEMP, f, ## a) | 158 | #define IWL_DEBUG_TEMP(f, a...) IWL_DEBUG(IWL_DL_TEMP, f, ## a) |
| 158 | #define IWL_DEBUG_SCAN(f, a...) IWL_DEBUG(IWL_DL_SCAN, f, ## a) | 159 | #define IWL_DEBUG_SCAN(f, a...) IWL_DEBUG(IWL_DL_SCAN, f, ## a) |
| 159 | #define IWL_DEBUG_RX(f, a...) IWL_DEBUG(IWL_DL_RX, f, ## a) | 160 | #define IWL_DEBUG_RX(f, a...) IWL_DEBUG(IWL_DL_RX, f, ## a) |
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c index aa98c76d8195..4108c7c8f00f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-tx.c +++ b/drivers/net/wireless/iwlwifi/iwl-tx.c | |||
| @@ -764,20 +764,19 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
| 764 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | 764 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 765 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | 765 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 766 | struct iwl_tfd_frame *tfd; | 766 | struct iwl_tfd_frame *tfd; |
| 767 | u32 *control_flags; | 767 | struct iwl_tx_queue *txq; |
| 768 | int txq_id = skb_get_queue_mapping(skb); | 768 | struct iwl_queue *q; |
| 769 | struct iwl_tx_queue *txq = NULL; | 769 | struct iwl_cmd *out_cmd; |
| 770 | struct iwl_queue *q = NULL; | 770 | struct iwl_tx_cmd *tx_cmd; |
| 771 | int swq_id, txq_id; | ||
| 771 | dma_addr_t phys_addr; | 772 | dma_addr_t phys_addr; |
| 772 | dma_addr_t txcmd_phys; | 773 | dma_addr_t txcmd_phys; |
| 773 | dma_addr_t scratch_phys; | 774 | dma_addr_t scratch_phys; |
| 774 | struct iwl_cmd *out_cmd = NULL; | ||
| 775 | struct iwl_tx_cmd *tx_cmd; | ||
| 776 | u16 len, idx, len_org; | 775 | u16 len, idx, len_org; |
| 777 | u16 seq_number = 0; | 776 | u16 seq_number = 0; |
| 778 | u8 id, hdr_len, unicast; | ||
| 779 | u8 sta_id; | ||
| 780 | __le16 fc; | 777 | __le16 fc; |
| 778 | u8 hdr_len, unicast; | ||
| 779 | u8 sta_id; | ||
| 781 | u8 wait_write_ptr = 0; | 780 | u8 wait_write_ptr = 0; |
| 782 | u8 tid = 0; | 781 | u8 tid = 0; |
| 783 | u8 *qc = NULL; | 782 | u8 *qc = NULL; |
| @@ -802,7 +801,6 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
| 802 | } | 801 | } |
| 803 | 802 | ||
| 804 | unicast = !is_multicast_ether_addr(hdr->addr1); | 803 | unicast = !is_multicast_ether_addr(hdr->addr1); |
| 805 | id = 0; | ||
| 806 | 804 | ||
| 807 | fc = hdr->frame_control; | 805 | fc = hdr->frame_control; |
| 808 | 806 | ||
| @@ -840,14 +838,16 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
| 840 | 838 | ||
| 841 | IWL_DEBUG_TX("station Id %d\n", sta_id); | 839 | IWL_DEBUG_TX("station Id %d\n", sta_id); |
| 842 | 840 | ||
| 841 | swq_id = skb_get_queue_mapping(skb); | ||
| 842 | txq_id = swq_id; | ||
| 843 | if (ieee80211_is_data_qos(fc)) { | 843 | if (ieee80211_is_data_qos(fc)) { |
| 844 | qc = ieee80211_get_qos_ctl(hdr); | 844 | qc = ieee80211_get_qos_ctl(hdr); |
| 845 | tid = qc[0] & 0xf; | 845 | tid = qc[0] & 0xf; |
| 846 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | 846 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
| 847 | IEEE80211_SCTL_SEQ; | 847 | seq_number &= IEEE80211_SCTL_SEQ; |
| 848 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | 848 | hdr->seq_ctrl = hdr->seq_ctrl & |
| 849 | (hdr->seq_ctrl & | 849 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG); |
| 850 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | 850 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
| 851 | seq_number += 0x10; | 851 | seq_number += 0x10; |
| 852 | /* aggregation is on for this <sta,tid> */ | 852 | /* aggregation is on for this <sta,tid> */ |
| 853 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | 853 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
| @@ -864,7 +864,6 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
| 864 | /* Set up first empty TFD within this queue's circular TFD buffer */ | 864 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
| 865 | tfd = &txq->bd[q->write_ptr]; | 865 | tfd = &txq->bd[q->write_ptr]; |
| 866 | memset(tfd, 0, sizeof(*tfd)); | 866 | memset(tfd, 0, sizeof(*tfd)); |
| 867 | control_flags = (u32 *) tfd; | ||
| 868 | idx = get_cmd_index(q, q->write_ptr, 0); | 867 | idx = get_cmd_index(q, q->write_ptr, 0); |
| 869 | 868 | ||
| 870 | /* Set up driver data for this TFD */ | 869 | /* Set up driver data for this TFD */ |
| @@ -983,8 +982,7 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
| 983 | iwl_txq_update_write_ptr(priv, txq); | 982 | iwl_txq_update_write_ptr(priv, txq); |
| 984 | spin_unlock_irqrestore(&priv->lock, flags); | 983 | spin_unlock_irqrestore(&priv->lock, flags); |
| 985 | } else { | 984 | } else { |
| 986 | ieee80211_stop_queue(priv->hw, | 985 | ieee80211_stop_queue(priv->hw, swq_id); |
| 987 | skb_get_queue_mapping(skb)); | ||
| 988 | } | 986 | } |
| 989 | } | 987 | } |
| 990 | 988 | ||
| @@ -1013,13 +1011,12 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |||
| 1013 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | 1011 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
| 1014 | struct iwl_queue *q = &txq->q; | 1012 | struct iwl_queue *q = &txq->q; |
| 1015 | struct iwl_tfd_frame *tfd; | 1013 | struct iwl_tfd_frame *tfd; |
| 1016 | u32 *control_flags; | ||
| 1017 | struct iwl_cmd *out_cmd; | 1014 | struct iwl_cmd *out_cmd; |
| 1018 | u32 idx; | ||
| 1019 | u16 fix_size; | ||
| 1020 | dma_addr_t phys_addr; | 1015 | dma_addr_t phys_addr; |
| 1021 | int len, ret; | ||
| 1022 | unsigned long flags; | 1016 | unsigned long flags; |
| 1017 | int len, ret; | ||
| 1018 | u32 idx; | ||
| 1019 | u16 fix_size; | ||
| 1023 | 1020 | ||
| 1024 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | 1021 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); |
| 1025 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | 1022 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); |
| @@ -1045,7 +1042,6 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |||
| 1045 | tfd = &txq->bd[q->write_ptr]; | 1042 | tfd = &txq->bd[q->write_ptr]; |
| 1046 | memset(tfd, 0, sizeof(*tfd)); | 1043 | memset(tfd, 0, sizeof(*tfd)); |
| 1047 | 1044 | ||
| 1048 | control_flags = (u32 *) tfd; | ||
| 1049 | 1045 | ||
| 1050 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); | 1046 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
| 1051 | out_cmd = txq->cmd[idx]; | 1047 | out_cmd = txq->cmd[idx]; |
diff --git a/drivers/net/wireless/orinoco.c b/drivers/net/wireless/orinoco.c index b047306bf386..1ebcafe7ca5f 100644 --- a/drivers/net/wireless/orinoco.c +++ b/drivers/net/wireless/orinoco.c | |||
| @@ -1998,13 +1998,6 @@ __orinoco_set_multicast_list(struct net_device *dev) | |||
| 1998 | else | 1998 | else |
| 1999 | priv->mc_count = mc_count; | 1999 | priv->mc_count = mc_count; |
| 2000 | } | 2000 | } |
| 2001 | |||
| 2002 | /* Since we can set the promiscuous flag when it wasn't asked | ||
| 2003 | for, make sure the net_device knows about it. */ | ||
| 2004 | if (priv->promiscuous) | ||
| 2005 | dev->flags |= IFF_PROMISC; | ||
| 2006 | else | ||
| 2007 | dev->flags &= ~IFF_PROMISC; | ||
| 2008 | } | 2001 | } |
| 2009 | 2002 | ||
| 2010 | /* This must be called from user context, without locks held - use | 2003 | /* This must be called from user context, without locks held - use |
diff --git a/drivers/net/wireless/p54/p54.h b/drivers/net/wireless/p54/p54.h index cac9a515b82d..4801a363507b 100644 --- a/drivers/net/wireless/p54/p54.h +++ b/drivers/net/wireless/p54/p54.h | |||
| @@ -52,6 +52,7 @@ struct p54_common { | |||
| 52 | int (*open)(struct ieee80211_hw *dev); | 52 | int (*open)(struct ieee80211_hw *dev); |
| 53 | void (*stop)(struct ieee80211_hw *dev); | 53 | void (*stop)(struct ieee80211_hw *dev); |
| 54 | int mode; | 54 | int mode; |
| 55 | u16 seqno; | ||
| 55 | struct mutex conf_mutex; | 56 | struct mutex conf_mutex; |
| 56 | u8 mac_addr[ETH_ALEN]; | 57 | u8 mac_addr[ETH_ALEN]; |
| 57 | u8 bssid[ETH_ALEN]; | 58 | u8 bssid[ETH_ALEN]; |
diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c index 4da89ea9b561..83cd85e1f847 100644 --- a/drivers/net/wireless/p54/p54common.c +++ b/drivers/net/wireless/p54/p54common.c | |||
| @@ -553,6 +553,7 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb) | |||
| 553 | struct ieee80211_tx_queue_stats *current_queue; | 553 | struct ieee80211_tx_queue_stats *current_queue; |
| 554 | struct p54_common *priv = dev->priv; | 554 | struct p54_common *priv = dev->priv; |
| 555 | struct p54_control_hdr *hdr; | 555 | struct p54_control_hdr *hdr; |
| 556 | struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data; | ||
| 556 | struct p54_tx_control_allocdata *txhdr; | 557 | struct p54_tx_control_allocdata *txhdr; |
| 557 | size_t padding, len; | 558 | size_t padding, len; |
| 558 | u8 rate; | 559 | u8 rate; |
| @@ -605,6 +606,19 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb) | |||
| 605 | if (padding) | 606 | if (padding) |
| 606 | txhdr->align[0] = padding; | 607 | txhdr->align[0] = padding; |
| 607 | 608 | ||
| 609 | /* FIXME: The sequence that follows is needed for this driver to | ||
| 610 | * work with mac80211 since "mac80211: fix TX sequence numbers". | ||
| 611 | * As with the temporary code in rt2x00, changes will be needed | ||
| 612 | * to get proper sequence numbers on beacons. In addition, this | ||
| 613 | * patch places the sequence number in the hardware state, which | ||
| 614 | * limits us to a single virtual state. | ||
| 615 | */ | ||
| 616 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | ||
| 617 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | ||
| 618 | priv->seqno += 0x10; | ||
| 619 | ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | ||
| 620 | ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno); | ||
| 621 | } | ||
| 608 | /* modifies skb->cb and with it info, so must be last! */ | 622 | /* modifies skb->cb and with it info, so must be last! */ |
| 609 | p54_assign_address(dev, skb, hdr, skb->len); | 623 | p54_assign_address(dev, skb, hdr, skb->len); |
| 610 | 624 | ||
| @@ -803,8 +817,8 @@ static void p54_set_vdcf(struct ieee80211_hw *dev) | |||
| 803 | 817 | ||
| 804 | if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) { | 818 | if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) { |
| 805 | vdcf->slottime = 9; | 819 | vdcf->slottime = 9; |
| 806 | vdcf->magic1 = 0x00; | 820 | vdcf->magic1 = 0x10; |
| 807 | vdcf->magic2 = 0x10; | 821 | vdcf->magic2 = 0x00; |
| 808 | } else { | 822 | } else { |
| 809 | vdcf->slottime = 20; | 823 | vdcf->slottime = 20; |
| 810 | vdcf->magic1 = 0x0a; | 824 | vdcf->magic1 = 0x0a; |
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c index bd422fd6a894..d06507388635 100644 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c | |||
| @@ -203,23 +203,43 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw, | |||
| 203 | !test_bit(DEVICE_STARTED, &rt2x00dev->flags)) | 203 | !test_bit(DEVICE_STARTED, &rt2x00dev->flags)) |
| 204 | return -ENODEV; | 204 | return -ENODEV; |
| 205 | 205 | ||
| 206 | /* | 206 | switch (conf->type) { |
| 207 | * We don't support mixed combinations of sta and ap virtual | 207 | case IEEE80211_IF_TYPE_AP: |
| 208 | * interfaces. We can only add this interface when the rival | 208 | /* |
| 209 | * interface count is 0. | 209 | * We don't support mixed combinations of |
| 210 | */ | 210 | * sta and ap interfaces. |
| 211 | if ((conf->type == IEEE80211_IF_TYPE_AP && rt2x00dev->intf_sta_count) || | 211 | */ |
| 212 | (conf->type != IEEE80211_IF_TYPE_AP && rt2x00dev->intf_ap_count)) | 212 | if (rt2x00dev->intf_sta_count) |
| 213 | return -ENOBUFS; | 213 | return -ENOBUFS; |
| 214 | 214 | ||
| 215 | /* | 215 | /* |
| 216 | * Check if we exceeded the maximum amount of supported interfaces. | 216 | * Check if we exceeded the maximum amount |
| 217 | */ | 217 | * of supported interfaces. |
| 218 | if ((conf->type == IEEE80211_IF_TYPE_AP && | 218 | */ |
| 219 | rt2x00dev->intf_ap_count >= rt2x00dev->ops->max_ap_intf) || | 219 | if (rt2x00dev->intf_ap_count >= rt2x00dev->ops->max_ap_intf) |
| 220 | (conf->type != IEEE80211_IF_TYPE_AP && | 220 | return -ENOBUFS; |
| 221 | rt2x00dev->intf_sta_count >= rt2x00dev->ops->max_sta_intf)) | 221 | |
| 222 | return -ENOBUFS; | 222 | break; |
| 223 | case IEEE80211_IF_TYPE_STA: | ||
| 224 | case IEEE80211_IF_TYPE_IBSS: | ||
| 225 | /* | ||
| 226 | * We don't support mixed combinations of | ||
| 227 | * sta and ap interfaces. | ||
| 228 | */ | ||
| 229 | if (rt2x00dev->intf_ap_count) | ||
| 230 | return -ENOBUFS; | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Check if we exceeded the maximum amount | ||
| 234 | * of supported interfaces. | ||
| 235 | */ | ||
| 236 | if (rt2x00dev->intf_sta_count >= rt2x00dev->ops->max_sta_intf) | ||
| 237 | return -ENOBUFS; | ||
| 238 | |||
| 239 | break; | ||
| 240 | default: | ||
| 241 | return -EINVAL; | ||
| 242 | } | ||
| 223 | 243 | ||
| 224 | /* | 244 | /* |
| 225 | * Loop through all beacon queues to find a free | 245 | * Loop through all beacon queues to find a free |
diff --git a/drivers/net/wireless/wavelan.c b/drivers/net/wireless/wavelan.c index 49ae97003952..136220b5ca81 100644 --- a/drivers/net/wireless/wavelan.c +++ b/drivers/net/wireless/wavelan.c | |||
| @@ -1409,9 +1409,6 @@ static void wavelan_set_multicast_list(struct net_device * dev) | |||
| 1409 | lp->mc_count = 0; | 1409 | lp->mc_count = 0; |
| 1410 | 1410 | ||
| 1411 | wv_82586_reconfig(dev); | 1411 | wv_82586_reconfig(dev); |
| 1412 | |||
| 1413 | /* Tell the kernel that we are doing a really bad job. */ | ||
| 1414 | dev->flags |= IFF_PROMISC; | ||
| 1415 | } | 1412 | } |
| 1416 | } else | 1413 | } else |
| 1417 | /* Are there multicast addresses to send? */ | 1414 | /* Are there multicast addresses to send? */ |
diff --git a/drivers/net/wireless/wavelan_cs.c b/drivers/net/wireless/wavelan_cs.c index b584c0ecc62d..00a3559e5aa4 100644 --- a/drivers/net/wireless/wavelan_cs.c +++ b/drivers/net/wireless/wavelan_cs.c | |||
| @@ -1412,9 +1412,6 @@ wavelan_set_multicast_list(struct net_device * dev) | |||
| 1412 | lp->mc_count = 0; | 1412 | lp->mc_count = 0; |
| 1413 | 1413 | ||
| 1414 | wv_82593_reconfig(dev); | 1414 | wv_82593_reconfig(dev); |
| 1415 | |||
| 1416 | /* Tell the kernel that we are doing a really bad job... */ | ||
| 1417 | dev->flags |= IFF_PROMISC; | ||
| 1418 | } | 1415 | } |
| 1419 | } | 1416 | } |
| 1420 | else | 1417 | else |
| @@ -1433,9 +1430,6 @@ wavelan_set_multicast_list(struct net_device * dev) | |||
| 1433 | lp->mc_count = 0; | 1430 | lp->mc_count = 0; |
| 1434 | 1431 | ||
| 1435 | wv_82593_reconfig(dev); | 1432 | wv_82593_reconfig(dev); |
| 1436 | |||
| 1437 | /* Tell the kernel that we are doing a really bad job... */ | ||
| 1438 | dev->flags |= IFF_ALLMULTI; | ||
| 1439 | } | 1433 | } |
| 1440 | } | 1434 | } |
| 1441 | else | 1435 | else |
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c index 902bbe788215..c749bdba214c 100644 --- a/drivers/net/xen-netfront.c +++ b/drivers/net/xen-netfront.c | |||
| @@ -329,7 +329,7 @@ static int xennet_open(struct net_device *dev) | |||
| 329 | } | 329 | } |
| 330 | spin_unlock_bh(&np->rx_lock); | 330 | spin_unlock_bh(&np->rx_lock); |
| 331 | 331 | ||
| 332 | xennet_maybe_wake_tx(dev); | 332 | netif_start_queue(dev); |
| 333 | 333 | ||
| 334 | return 0; | 334 | return 0; |
| 335 | } | 335 | } |
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 2622b6596d7c..3712b925b315 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c | |||
| @@ -932,7 +932,7 @@ static struct ehci_qh *qh_append_tds ( | |||
| 932 | 932 | ||
| 933 | list_del (&qtd->qtd_list); | 933 | list_del (&qtd->qtd_list); |
| 934 | list_add (&dummy->qtd_list, qtd_list); | 934 | list_add (&dummy->qtd_list, qtd_list); |
| 935 | __list_splice (qtd_list, qh->qtd_list.prev); | 935 | list_splice_tail(qtd_list, &qh->qtd_list); |
| 936 | 936 | ||
| 937 | ehci_qtd_init(ehci, qtd, qtd->qtd_dma); | 937 | ehci_qtd_init(ehci, qtd, qtd->qtd_dma); |
| 938 | qh->dummy = qtd; | 938 | qh->dummy = qtd; |
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 48399e134c0d..32b9fe153641 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig | |||
| @@ -463,7 +463,7 @@ config PC87413_WDT | |||
| 463 | module will be called pc87413_wdt. | 463 | module will be called pc87413_wdt. |
| 464 | 464 | ||
| 465 | Most people will say N. | 465 | Most people will say N. |
| 466 | 466 | ||
| 467 | config 60XX_WDT | 467 | config 60XX_WDT |
| 468 | tristate "SBC-60XX Watchdog Timer" | 468 | tristate "SBC-60XX Watchdog Timer" |
| 469 | depends on X86 | 469 | depends on X86 |
| @@ -695,9 +695,17 @@ config 8xx_WDT | |||
| 695 | tristate "MPC8xx Watchdog Timer" | 695 | tristate "MPC8xx Watchdog Timer" |
| 696 | depends on 8xx | 696 | depends on 8xx |
| 697 | 697 | ||
| 698 | config 83xx_WDT | 698 | config 8xxx_WDT |
| 699 | tristate "MPC83xx Watchdog Timer" | 699 | tristate "MPC8xxx Platform Watchdog Timer" |
| 700 | depends on PPC_83xx | 700 | depends on PPC_8xx || PPC_83xx || PPC_86xx |
| 701 | help | ||
| 702 | This driver is for a SoC level watchdog that exists on some | ||
| 703 | Freescale PowerPC processors. So far this driver supports: | ||
| 704 | - MPC8xx watchdogs | ||
| 705 | - MPC83xx watchdogs | ||
| 706 | - MPC86xx watchdogs | ||
| 707 | |||
| 708 | For BookE processors (MPC85xx) use the BOOKE_WDT driver instead. | ||
| 701 | 709 | ||
| 702 | config MV64X60_WDT | 710 | config MV64X60_WDT |
| 703 | tristate "MV64X60 (Marvell Discovery) Watchdog Timer" | 711 | tristate "MV64X60 (Marvell Discovery) Watchdog Timer" |
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index edd305a64e63..049c91895699 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile | |||
| @@ -92,7 +92,7 @@ obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc_epx_c3.o | |||
| 92 | 92 | ||
| 93 | # MIPS Architecture | 93 | # MIPS Architecture |
| 94 | obj-$(CONFIG_INDYDOG) += indydog.o | 94 | obj-$(CONFIG_INDYDOG) += indydog.o |
| 95 | obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o | 95 | obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o |
| 96 | obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o | 96 | obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o |
| 97 | obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o | 97 | obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o |
| 98 | obj-$(CONFIG_AR7_WDT) += ar7_wdt.o | 98 | obj-$(CONFIG_AR7_WDT) += ar7_wdt.o |
| @@ -103,7 +103,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o | |||
| 103 | # POWERPC Architecture | 103 | # POWERPC Architecture |
| 104 | obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o | 104 | obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o |
| 105 | obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o | 105 | obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o |
| 106 | obj-$(CONFIG_83xx_WDT) += mpc83xx_wdt.o | 106 | obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o |
| 107 | obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o | 107 | obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o |
| 108 | obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o | 108 | obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o |
| 109 | 109 | ||
diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 85269c365a10..6e46a551395c 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c | |||
| @@ -58,39 +58,45 @@ | |||
| 58 | #include <linux/types.h> /* For standard types (like size_t) */ | 58 | #include <linux/types.h> /* For standard types (like size_t) */ |
| 59 | #include <linux/errno.h> /* For the -ENODEV/... values */ | 59 | #include <linux/errno.h> /* For the -ENODEV/... values */ |
| 60 | #include <linux/kernel.h> /* For printk/panic/... */ | 60 | #include <linux/kernel.h> /* For printk/panic/... */ |
| 61 | #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */ | 61 | #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV |
| 62 | (WATCHDOG_MINOR) */ | ||
| 62 | #include <linux/watchdog.h> /* For the watchdog specific items */ | 63 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
| 63 | #include <linux/fs.h> /* For file operations */ | 64 | #include <linux/fs.h> /* For file operations */ |
| 64 | #include <linux/ioport.h> /* For io-port access */ | 65 | #include <linux/ioport.h> /* For io-port access */ |
| 65 | #include <linux/platform_device.h> /* For platform_driver framework */ | 66 | #include <linux/platform_device.h> /* For platform_driver framework */ |
| 66 | #include <linux/init.h> /* For __init/__exit/... */ | 67 | #include <linux/init.h> /* For __init/__exit/... */ |
| 67 | 68 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ | |
| 68 | #include <asm/uaccess.h> /* For copy_to_user/put_user/... */ | 69 | #include <linux/io.h> /* For inb/outb/... */ |
| 69 | #include <asm/io.h> /* For inb/outb/... */ | ||
| 70 | 70 | ||
| 71 | /* Module information */ | 71 | /* Module information */ |
| 72 | #define DRV_NAME "acquirewdt" | 72 | #define DRV_NAME "acquirewdt" |
| 73 | #define PFX DRV_NAME ": " | 73 | #define PFX DRV_NAME ": " |
| 74 | #define WATCHDOG_NAME "Acquire WDT" | 74 | #define WATCHDOG_NAME "Acquire WDT" |
| 75 | #define WATCHDOG_HEARTBEAT 0 /* There is no way to see what the correct time-out period is */ | 75 | /* There is no way to see what the correct time-out period is */ |
| 76 | #define WATCHDOG_HEARTBEAT 0 | ||
| 76 | 77 | ||
| 77 | /* internal variables */ | 78 | /* internal variables */ |
| 78 | static struct platform_device *acq_platform_device; /* the watchdog platform device */ | 79 | /* the watchdog platform device */ |
| 80 | static struct platform_device *acq_platform_device; | ||
| 79 | static unsigned long acq_is_open; | 81 | static unsigned long acq_is_open; |
| 80 | static char expect_close; | 82 | static char expect_close; |
| 81 | 83 | ||
| 82 | /* module parameters */ | 84 | /* module parameters */ |
| 83 | static int wdt_stop = 0x43; /* You must set this - there is no sane way to probe for this board. */ | 85 | /* You must set this - there is no sane way to probe for this board. */ |
| 86 | static int wdt_stop = 0x43; | ||
| 84 | module_param(wdt_stop, int, 0); | 87 | module_param(wdt_stop, int, 0); |
| 85 | MODULE_PARM_DESC(wdt_stop, "Acquire WDT 'stop' io port (default 0x43)"); | 88 | MODULE_PARM_DESC(wdt_stop, "Acquire WDT 'stop' io port (default 0x43)"); |
| 86 | 89 | ||
| 87 | static int wdt_start = 0x443; /* You must set this - there is no sane way to probe for this board. */ | 90 | /* You must set this - there is no sane way to probe for this board. */ |
| 91 | static int wdt_start = 0x443; | ||
| 88 | module_param(wdt_start, int, 0); | 92 | module_param(wdt_start, int, 0); |
| 89 | MODULE_PARM_DESC(wdt_start, "Acquire WDT 'start' io port (default 0x443)"); | 93 | MODULE_PARM_DESC(wdt_start, "Acquire WDT 'start' io port (default 0x443)"); |
| 90 | 94 | ||
| 91 | static int nowayout = WATCHDOG_NOWAYOUT; | 95 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 92 | module_param(nowayout, int, 0); | 96 | module_param(nowayout, int, 0); |
| 93 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 97 | MODULE_PARM_DESC(nowayout, |
| 98 | "Watchdog cannot be stopped once started (default=" | ||
| 99 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 94 | 100 | ||
| 95 | /* | 101 | /* |
| 96 | * Watchdog Operations | 102 | * Watchdog Operations |
| @@ -112,18 +118,18 @@ static void acq_stop(void) | |||
| 112 | * /dev/watchdog handling | 118 | * /dev/watchdog handling |
| 113 | */ | 119 | */ |
| 114 | 120 | ||
| 115 | static ssize_t acq_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | 121 | static ssize_t acq_write(struct file *file, const char __user *buf, |
| 122 | size_t count, loff_t *ppos) | ||
| 116 | { | 123 | { |
| 117 | /* See if we got the magic character 'V' and reload the timer */ | 124 | /* See if we got the magic character 'V' and reload the timer */ |
| 118 | if(count) { | 125 | if (count) { |
| 119 | if (!nowayout) { | 126 | if (!nowayout) { |
| 120 | size_t i; | 127 | size_t i; |
| 121 | |||
| 122 | /* note: just in case someone wrote the magic character | 128 | /* note: just in case someone wrote the magic character |
| 123 | * five months ago... */ | 129 | five months ago... */ |
| 124 | expect_close = 0; | 130 | expect_close = 0; |
| 125 | 131 | /* scan to see whether or not we got the | |
| 126 | /* scan to see whether or not we got the magic character */ | 132 | magic character */ |
| 127 | for (i = 0; i != count; i++) { | 133 | for (i = 0; i != count; i++) { |
| 128 | char c; | 134 | char c; |
| 129 | if (get_user(c, buf + i)) | 135 | if (get_user(c, buf + i)) |
| @@ -132,64 +138,55 @@ static ssize_t acq_write(struct file *file, const char __user *buf, size_t count | |||
| 132 | expect_close = 42; | 138 | expect_close = 42; |
| 133 | } | 139 | } |
| 134 | } | 140 | } |
| 135 | 141 | /* Well, anyhow someone wrote to us, we should | |
| 136 | /* Well, anyhow someone wrote to us, we should return that favour */ | 142 | return that favour */ |
| 137 | acq_keepalive(); | 143 | acq_keepalive(); |
| 138 | } | 144 | } |
| 139 | return count; | 145 | return count; |
| 140 | } | 146 | } |
| 141 | 147 | ||
| 142 | static int acq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 148 | static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 143 | unsigned long arg) | ||
| 144 | { | 149 | { |
| 145 | int options, retval = -EINVAL; | 150 | int options, retval = -EINVAL; |
| 146 | void __user *argp = (void __user *)arg; | 151 | void __user *argp = (void __user *)arg; |
| 147 | int __user *p = argp; | 152 | int __user *p = argp; |
| 148 | static struct watchdog_info ident = | 153 | static struct watchdog_info ident = { |
| 149 | { | ||
| 150 | .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | 154 | .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, |
| 151 | .firmware_version = 1, | 155 | .firmware_version = 1, |
| 152 | .identity = WATCHDOG_NAME, | 156 | .identity = WATCHDOG_NAME, |
| 153 | }; | 157 | }; |
| 154 | 158 | ||
| 155 | switch(cmd) | 159 | switch (cmd) { |
| 156 | { | ||
| 157 | case WDIOC_GETSUPPORT: | 160 | case WDIOC_GETSUPPORT: |
| 158 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | 161 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 159 | 162 | ||
| 160 | case WDIOC_GETSTATUS: | 163 | case WDIOC_GETSTATUS: |
| 161 | case WDIOC_GETBOOTSTATUS: | 164 | case WDIOC_GETBOOTSTATUS: |
| 162 | return put_user(0, p); | 165 | return put_user(0, p); |
| 163 | |||
| 164 | case WDIOC_KEEPALIVE: | ||
| 165 | acq_keepalive(); | ||
| 166 | return 0; | ||
| 167 | |||
| 168 | case WDIOC_GETTIMEOUT: | ||
| 169 | return put_user(WATCHDOG_HEARTBEAT, p); | ||
| 170 | 166 | ||
| 171 | case WDIOC_SETOPTIONS: | 167 | case WDIOC_SETOPTIONS: |
| 172 | { | 168 | { |
| 173 | if (get_user(options, p)) | 169 | if (get_user(options, p)) |
| 174 | return -EFAULT; | 170 | return -EFAULT; |
| 175 | 171 | if (options & WDIOS_DISABLECARD) { | |
| 176 | if (options & WDIOS_DISABLECARD) | 172 | acq_stop(); |
| 177 | { | 173 | retval = 0; |
| 178 | acq_stop(); | 174 | } |
| 179 | retval = 0; | 175 | if (options & WDIOS_ENABLECARD) { |
| 180 | } | 176 | acq_keepalive(); |
| 181 | 177 | retval = 0; | |
| 182 | if (options & WDIOS_ENABLECARD) | 178 | } |
| 183 | { | 179 | return retval; |
| 184 | acq_keepalive(); | ||
| 185 | retval = 0; | ||
| 186 | } | ||
| 187 | |||
| 188 | return retval; | ||
| 189 | } | 180 | } |
| 181 | case WDIOC_KEEPALIVE: | ||
| 182 | acq_keepalive(); | ||
| 183 | return 0; | ||
| 184 | |||
| 185 | case WDIOC_GETTIMEOUT: | ||
| 186 | return put_user(WATCHDOG_HEARTBEAT, p); | ||
| 190 | 187 | ||
| 191 | default: | 188 | default: |
| 192 | return -ENOTTY; | 189 | return -ENOTTY; |
| 193 | } | 190 | } |
| 194 | } | 191 | } |
| 195 | 192 | ||
| @@ -211,7 +208,8 @@ static int acq_close(struct inode *inode, struct file *file) | |||
| 211 | if (expect_close == 42) { | 208 | if (expect_close == 42) { |
| 212 | acq_stop(); | 209 | acq_stop(); |
| 213 | } else { | 210 | } else { |
| 214 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 211 | printk(KERN_CRIT PFX |
| 212 | "Unexpected close, not stopping watchdog!\n"); | ||
| 215 | acq_keepalive(); | 213 | acq_keepalive(); |
| 216 | } | 214 | } |
| 217 | clear_bit(0, &acq_is_open); | 215 | clear_bit(0, &acq_is_open); |
| @@ -227,7 +225,7 @@ static const struct file_operations acq_fops = { | |||
| 227 | .owner = THIS_MODULE, | 225 | .owner = THIS_MODULE, |
| 228 | .llseek = no_llseek, | 226 | .llseek = no_llseek, |
| 229 | .write = acq_write, | 227 | .write = acq_write, |
| 230 | .ioctl = acq_ioctl, | 228 | .unlocked_ioctl = acq_ioctl, |
| 231 | .open = acq_open, | 229 | .open = acq_open, |
| 232 | .release = acq_close, | 230 | .release = acq_close, |
| 233 | }; | 231 | }; |
| @@ -248,32 +246,29 @@ static int __devinit acq_probe(struct platform_device *dev) | |||
| 248 | 246 | ||
| 249 | if (wdt_stop != wdt_start) { | 247 | if (wdt_stop != wdt_start) { |
| 250 | if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) { | 248 | if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) { |
| 251 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 249 | printk(KERN_ERR PFX |
| 252 | wdt_stop); | 250 | "I/O address 0x%04x already in use\n", wdt_stop); |
| 253 | ret = -EIO; | 251 | ret = -EIO; |
| 254 | goto out; | 252 | goto out; |
| 255 | } | 253 | } |
| 256 | } | 254 | } |
| 257 | 255 | ||
| 258 | if (!request_region(wdt_start, 1, WATCHDOG_NAME)) { | 256 | if (!request_region(wdt_start, 1, WATCHDOG_NAME)) { |
| 259 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 257 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 260 | wdt_start); | 258 | wdt_start); |
| 261 | ret = -EIO; | 259 | ret = -EIO; |
| 262 | goto unreg_stop; | 260 | goto unreg_stop; |
| 263 | } | 261 | } |
| 264 | |||
| 265 | ret = misc_register(&acq_miscdev); | 262 | ret = misc_register(&acq_miscdev); |
| 266 | if (ret != 0) { | 263 | if (ret != 0) { |
| 267 | printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 264 | printk(KERN_ERR PFX |
| 268 | WATCHDOG_MINOR, ret); | 265 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 266 | WATCHDOG_MINOR, ret); | ||
| 269 | goto unreg_regions; | 267 | goto unreg_regions; |
| 270 | } | 268 | } |
| 271 | 269 | printk(KERN_INFO PFX "initialized. (nowayout=%d)\n", nowayout); | |
| 272 | printk (KERN_INFO PFX "initialized. (nowayout=%d)\n", | ||
| 273 | nowayout); | ||
| 274 | 270 | ||
| 275 | return 0; | 271 | return 0; |
| 276 | |||
| 277 | unreg_regions: | 272 | unreg_regions: |
| 278 | release_region(wdt_start, 1); | 273 | release_region(wdt_start, 1); |
| 279 | unreg_stop: | 274 | unreg_stop: |
| @@ -286,9 +281,9 @@ out: | |||
| 286 | static int __devexit acq_remove(struct platform_device *dev) | 281 | static int __devexit acq_remove(struct platform_device *dev) |
| 287 | { | 282 | { |
| 288 | misc_deregister(&acq_miscdev); | 283 | misc_deregister(&acq_miscdev); |
| 289 | release_region(wdt_start,1); | 284 | release_region(wdt_start, 1); |
| 290 | if(wdt_stop != wdt_start) | 285 | if (wdt_stop != wdt_start) |
| 291 | release_region(wdt_stop,1); | 286 | release_region(wdt_stop, 1); |
| 292 | 287 | ||
| 293 | return 0; | 288 | return 0; |
| 294 | } | 289 | } |
| @@ -313,18 +308,19 @@ static int __init acq_init(void) | |||
| 313 | { | 308 | { |
| 314 | int err; | 309 | int err; |
| 315 | 310 | ||
| 316 | printk(KERN_INFO "WDT driver for Acquire single board computer initialising.\n"); | 311 | printk(KERN_INFO |
| 312 | "WDT driver for Acquire single board computer initialising.\n"); | ||
| 317 | 313 | ||
| 318 | err = platform_driver_register(&acquirewdt_driver); | 314 | err = platform_driver_register(&acquirewdt_driver); |
| 319 | if (err) | 315 | if (err) |
| 320 | return err; | 316 | return err; |
| 321 | 317 | ||
| 322 | acq_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); | 318 | acq_platform_device = platform_device_register_simple(DRV_NAME, |
| 319 | -1, NULL, 0); | ||
| 323 | if (IS_ERR(acq_platform_device)) { | 320 | if (IS_ERR(acq_platform_device)) { |
| 324 | err = PTR_ERR(acq_platform_device); | 321 | err = PTR_ERR(acq_platform_device); |
| 325 | goto unreg_platform_driver; | 322 | goto unreg_platform_driver; |
| 326 | } | 323 | } |
| 327 | |||
| 328 | return 0; | 324 | return 0; |
| 329 | 325 | ||
| 330 | unreg_platform_driver: | 326 | unreg_platform_driver: |
diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index 8121cc247343..a5110f93a755 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c | |||
| @@ -37,9 +37,9 @@ | |||
| 37 | #include <linux/ioport.h> | 37 | #include <linux/ioport.h> |
| 38 | #include <linux/platform_device.h> | 38 | #include <linux/platform_device.h> |
| 39 | #include <linux/init.h> | 39 | #include <linux/init.h> |
| 40 | #include <linux/io.h> | ||
| 41 | #include <linux/uaccess.h> | ||
| 40 | 42 | ||
| 41 | #include <asm/io.h> | ||
| 42 | #include <asm/uaccess.h> | ||
| 43 | #include <asm/system.h> | 43 | #include <asm/system.h> |
| 44 | 44 | ||
| 45 | #define DRV_NAME "advantechwdt" | 45 | #define DRV_NAME "advantechwdt" |
| @@ -47,7 +47,8 @@ | |||
| 47 | #define WATCHDOG_NAME "Advantech WDT" | 47 | #define WATCHDOG_NAME "Advantech WDT" |
| 48 | #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */ | 48 | #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */ |
| 49 | 49 | ||
| 50 | static struct platform_device *advwdt_platform_device; /* the watchdog platform device */ | 50 | /* the watchdog platform device */ |
| 51 | static struct platform_device *advwdt_platform_device; | ||
| 51 | static unsigned long advwdt_is_open; | 52 | static unsigned long advwdt_is_open; |
| 52 | static char adv_expect_close; | 53 | static char adv_expect_close; |
| 53 | 54 | ||
| @@ -72,35 +73,35 @@ MODULE_PARM_DESC(wdt_start, "Advantech WDT 'start' io port (default 0x443)"); | |||
| 72 | 73 | ||
| 73 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ | 74 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ |
| 74 | module_param(timeout, int, 0); | 75 | module_param(timeout, int, 0); |
| 75 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=63, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | 76 | MODULE_PARM_DESC(timeout, |
| 77 | "Watchdog timeout in seconds. 1<= timeout <=63, default=" | ||
| 78 | __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | ||
| 76 | 79 | ||
| 77 | static int nowayout = WATCHDOG_NOWAYOUT; | 80 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 78 | module_param(nowayout, int, 0); | 81 | module_param(nowayout, int, 0); |
| 79 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 82 | MODULE_PARM_DESC(nowayout, |
| 83 | "Watchdog cannot be stopped once started (default=" | ||
| 84 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 80 | 85 | ||
| 81 | /* | 86 | /* |
| 82 | * Watchdog Operations | 87 | * Watchdog Operations |
| 83 | */ | 88 | */ |
| 84 | 89 | ||
| 85 | static void | 90 | static void advwdt_ping(void) |
| 86 | advwdt_ping(void) | ||
| 87 | { | 91 | { |
| 88 | /* Write a watchdog value */ | 92 | /* Write a watchdog value */ |
| 89 | outb_p(timeout, wdt_start); | 93 | outb_p(timeout, wdt_start); |
| 90 | } | 94 | } |
| 91 | 95 | ||
| 92 | static void | 96 | static void advwdt_disable(void) |
| 93 | advwdt_disable(void) | ||
| 94 | { | 97 | { |
| 95 | inb_p(wdt_stop); | 98 | inb_p(wdt_stop); |
| 96 | } | 99 | } |
| 97 | 100 | ||
| 98 | static int | 101 | static int advwdt_set_heartbeat(int t) |
| 99 | advwdt_set_heartbeat(int t) | ||
| 100 | { | 102 | { |
| 101 | if ((t < 1) || (t > 63)) | 103 | if (t < 1 || t > 63) |
| 102 | return -EINVAL; | 104 | return -EINVAL; |
| 103 | |||
| 104 | timeout = t; | 105 | timeout = t; |
| 105 | return 0; | 106 | return 0; |
| 106 | } | 107 | } |
| @@ -109,8 +110,8 @@ advwdt_set_heartbeat(int t) | |||
| 109 | * /dev/watchdog handling | 110 | * /dev/watchdog handling |
| 110 | */ | 111 | */ |
| 111 | 112 | ||
| 112 | static ssize_t | 113 | static ssize_t advwdt_write(struct file *file, const char __user *buf, |
| 113 | advwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | 114 | size_t count, loff_t *ppos) |
| 114 | { | 115 | { |
| 115 | if (count) { | 116 | if (count) { |
| 116 | if (!nowayout) { | 117 | if (!nowayout) { |
| @@ -120,7 +121,7 @@ advwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *pp | |||
| 120 | 121 | ||
| 121 | for (i = 0; i != count; i++) { | 122 | for (i = 0; i != count; i++) { |
| 122 | char c; | 123 | char c; |
| 123 | if (get_user(c, buf+i)) | 124 | if (get_user(c, buf + i)) |
| 124 | return -EFAULT; | 125 | return -EFAULT; |
| 125 | if (c == 'V') | 126 | if (c == 'V') |
| 126 | adv_expect_close = 42; | 127 | adv_expect_close = 42; |
| @@ -131,9 +132,7 @@ advwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *pp | |||
| 131 | return count; | 132 | return count; |
| 132 | } | 133 | } |
| 133 | 134 | ||
| 134 | static int | 135 | static long advwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 135 | advwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | ||
| 136 | unsigned long arg) | ||
| 137 | { | 136 | { |
| 138 | int new_timeout; | 137 | int new_timeout; |
| 139 | void __user *argp = (void __user *)arg; | 138 | void __user *argp = (void __user *)arg; |
| @@ -146,57 +145,50 @@ advwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 146 | 145 | ||
| 147 | switch (cmd) { | 146 | switch (cmd) { |
| 148 | case WDIOC_GETSUPPORT: | 147 | case WDIOC_GETSUPPORT: |
| 149 | if (copy_to_user(argp, &ident, sizeof(ident))) | 148 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 150 | return -EFAULT; | 149 | return -EFAULT; |
| 151 | break; | 150 | break; |
| 152 | 151 | ||
| 153 | case WDIOC_GETSTATUS: | 152 | case WDIOC_GETSTATUS: |
| 154 | case WDIOC_GETBOOTSTATUS: | 153 | case WDIOC_GETBOOTSTATUS: |
| 155 | return put_user(0, p); | 154 | return put_user(0, p); |
| 156 | |||
| 157 | case WDIOC_KEEPALIVE: | ||
| 158 | advwdt_ping(); | ||
| 159 | break; | ||
| 160 | |||
| 161 | case WDIOC_SETTIMEOUT: | ||
| 162 | if (get_user(new_timeout, p)) | ||
| 163 | return -EFAULT; | ||
| 164 | if (advwdt_set_heartbeat(new_timeout)) | ||
| 165 | return -EINVAL; | ||
| 166 | advwdt_ping(); | ||
| 167 | /* Fall */ | ||
| 168 | |||
| 169 | case WDIOC_GETTIMEOUT: | ||
| 170 | return put_user(timeout, p); | ||
| 171 | 155 | ||
| 172 | case WDIOC_SETOPTIONS: | 156 | case WDIOC_SETOPTIONS: |
| 173 | { | 157 | { |
| 174 | int options, retval = -EINVAL; | 158 | int options, retval = -EINVAL; |
| 175 | |||
| 176 | if (get_user(options, p)) | ||
| 177 | return -EFAULT; | ||
| 178 | |||
| 179 | if (options & WDIOS_DISABLECARD) { | ||
| 180 | advwdt_disable(); | ||
| 181 | retval = 0; | ||
| 182 | } | ||
| 183 | 159 | ||
| 184 | if (options & WDIOS_ENABLECARD) { | 160 | if (get_user(options, p)) |
| 185 | advwdt_ping(); | 161 | return -EFAULT; |
| 186 | retval = 0; | 162 | if (options & WDIOS_DISABLECARD) { |
| 187 | } | 163 | advwdt_disable(); |
| 188 | 164 | retval = 0; | |
| 189 | return retval; | 165 | } |
| 166 | if (options & WDIOS_ENABLECARD) { | ||
| 167 | advwdt_ping(); | ||
| 168 | retval = 0; | ||
| 169 | } | ||
| 170 | return retval; | ||
| 190 | } | 171 | } |
| 172 | case WDIOC_KEEPALIVE: | ||
| 173 | advwdt_ping(); | ||
| 174 | break; | ||
| 191 | 175 | ||
| 176 | case WDIOC_SETTIMEOUT: | ||
| 177 | if (get_user(new_timeout, p)) | ||
| 178 | return -EFAULT; | ||
| 179 | if (advwdt_set_heartbeat(new_timeout)) | ||
| 180 | return -EINVAL; | ||
| 181 | advwdt_ping(); | ||
| 182 | /* Fall */ | ||
| 183 | case WDIOC_GETTIMEOUT: | ||
| 184 | return put_user(timeout, p); | ||
| 192 | default: | 185 | default: |
| 193 | return -ENOTTY; | 186 | return -ENOTTY; |
| 194 | } | 187 | } |
| 195 | return 0; | 188 | return 0; |
| 196 | } | 189 | } |
| 197 | 190 | ||
| 198 | static int | 191 | static int advwdt_open(struct inode *inode, struct file *file) |
| 199 | advwdt_open(struct inode *inode, struct file *file) | ||
| 200 | { | 192 | { |
| 201 | if (test_and_set_bit(0, &advwdt_is_open)) | 193 | if (test_and_set_bit(0, &advwdt_is_open)) |
| 202 | return -EBUSY; | 194 | return -EBUSY; |
| @@ -208,13 +200,13 @@ advwdt_open(struct inode *inode, struct file *file) | |||
| 208 | return nonseekable_open(inode, file); | 200 | return nonseekable_open(inode, file); |
| 209 | } | 201 | } |
| 210 | 202 | ||
| 211 | static int | 203 | static int advwdt_close(struct inode *inode, struct file *file) |
| 212 | advwdt_close(struct inode *inode, struct file *file) | ||
| 213 | { | 204 | { |
| 214 | if (adv_expect_close == 42) { | 205 | if (adv_expect_close == 42) { |
| 215 | advwdt_disable(); | 206 | advwdt_disable(); |
| 216 | } else { | 207 | } else { |
| 217 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 208 | printk(KERN_CRIT PFX |
| 209 | "Unexpected close, not stopping watchdog!\n"); | ||
| 218 | advwdt_ping(); | 210 | advwdt_ping(); |
| 219 | } | 211 | } |
| 220 | clear_bit(0, &advwdt_is_open); | 212 | clear_bit(0, &advwdt_is_open); |
| @@ -230,7 +222,7 @@ static const struct file_operations advwdt_fops = { | |||
| 230 | .owner = THIS_MODULE, | 222 | .owner = THIS_MODULE, |
| 231 | .llseek = no_llseek, | 223 | .llseek = no_llseek, |
| 232 | .write = advwdt_write, | 224 | .write = advwdt_write, |
| 233 | .ioctl = advwdt_ioctl, | 225 | .unlocked_ioctl = advwdt_ioctl, |
| 234 | .open = advwdt_open, | 226 | .open = advwdt_open, |
| 235 | .release = advwdt_close, | 227 | .release = advwdt_close, |
| 236 | }; | 228 | }; |
| @@ -245,23 +237,24 @@ static struct miscdevice advwdt_miscdev = { | |||
| 245 | * Init & exit routines | 237 | * Init & exit routines |
| 246 | */ | 238 | */ |
| 247 | 239 | ||
| 248 | static int __devinit | 240 | static int __devinit advwdt_probe(struct platform_device *dev) |
| 249 | advwdt_probe(struct platform_device *dev) | ||
| 250 | { | 241 | { |
| 251 | int ret; | 242 | int ret; |
| 252 | 243 | ||
| 253 | if (wdt_stop != wdt_start) { | 244 | if (wdt_stop != wdt_start) { |
| 254 | if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) { | 245 | if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) { |
| 255 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 246 | printk(KERN_ERR PFX |
| 256 | wdt_stop); | 247 | "I/O address 0x%04x already in use\n", |
| 248 | wdt_stop); | ||
| 257 | ret = -EIO; | 249 | ret = -EIO; |
| 258 | goto out; | 250 | goto out; |
| 259 | } | 251 | } |
| 260 | } | 252 | } |
| 261 | 253 | ||
| 262 | if (!request_region(wdt_start, 1, WATCHDOG_NAME)) { | 254 | if (!request_region(wdt_start, 1, WATCHDOG_NAME)) { |
| 263 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 255 | printk(KERN_ERR PFX |
| 264 | wdt_start); | 256 | "I/O address 0x%04x already in use\n", |
| 257 | wdt_start); | ||
| 265 | ret = -EIO; | 258 | ret = -EIO; |
| 266 | goto unreg_stop; | 259 | goto unreg_stop; |
| 267 | } | 260 | } |
| @@ -269,20 +262,19 @@ advwdt_probe(struct platform_device *dev) | |||
| 269 | /* Check that the heartbeat value is within it's range ; if not reset to the default */ | 262 | /* Check that the heartbeat value is within it's range ; if not reset to the default */ |
| 270 | if (advwdt_set_heartbeat(timeout)) { | 263 | if (advwdt_set_heartbeat(timeout)) { |
| 271 | advwdt_set_heartbeat(WATCHDOG_TIMEOUT); | 264 | advwdt_set_heartbeat(WATCHDOG_TIMEOUT); |
| 272 | printk (KERN_INFO PFX "timeout value must be 1<=x<=63, using %d\n", | 265 | printk(KERN_INFO PFX |
| 273 | timeout); | 266 | "timeout value must be 1<=x<=63, using %d\n", timeout); |
| 274 | } | 267 | } |
| 275 | 268 | ||
| 276 | ret = misc_register(&advwdt_miscdev); | 269 | ret = misc_register(&advwdt_miscdev); |
| 277 | if (ret != 0) { | 270 | if (ret != 0) { |
| 278 | printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 271 | printk(KERN_ERR PFX |
| 279 | WATCHDOG_MINOR, ret); | 272 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 273 | WATCHDOG_MINOR, ret); | ||
| 280 | goto unreg_regions; | 274 | goto unreg_regions; |
| 281 | } | 275 | } |
| 282 | 276 | printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", | |
| 283 | printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", | ||
| 284 | timeout, nowayout); | 277 | timeout, nowayout); |
| 285 | |||
| 286 | out: | 278 | out: |
| 287 | return ret; | 279 | return ret; |
| 288 | unreg_regions: | 280 | unreg_regions: |
| @@ -293,19 +285,17 @@ unreg_stop: | |||
| 293 | goto out; | 285 | goto out; |
| 294 | } | 286 | } |
| 295 | 287 | ||
| 296 | static int __devexit | 288 | static int __devexit advwdt_remove(struct platform_device *dev) |
| 297 | advwdt_remove(struct platform_device *dev) | ||
| 298 | { | 289 | { |
| 299 | misc_deregister(&advwdt_miscdev); | 290 | misc_deregister(&advwdt_miscdev); |
| 300 | release_region(wdt_start,1); | 291 | release_region(wdt_start, 1); |
| 301 | if(wdt_stop != wdt_start) | 292 | if (wdt_stop != wdt_start) |
| 302 | release_region(wdt_stop,1); | 293 | release_region(wdt_stop, 1); |
| 303 | 294 | ||
| 304 | return 0; | 295 | return 0; |
| 305 | } | 296 | } |
| 306 | 297 | ||
| 307 | static void | 298 | static void advwdt_shutdown(struct platform_device *dev) |
| 308 | advwdt_shutdown(struct platform_device *dev) | ||
| 309 | { | 299 | { |
| 310 | /* Turn the WDT off if we have a soft shutdown */ | 300 | /* Turn the WDT off if we have a soft shutdown */ |
| 311 | advwdt_disable(); | 301 | advwdt_disable(); |
| @@ -321,18 +311,19 @@ static struct platform_driver advwdt_driver = { | |||
| 321 | }, | 311 | }, |
| 322 | }; | 312 | }; |
| 323 | 313 | ||
| 324 | static int __init | 314 | static int __init advwdt_init(void) |
| 325 | advwdt_init(void) | ||
| 326 | { | 315 | { |
| 327 | int err; | 316 | int err; |
| 328 | 317 | ||
| 329 | printk(KERN_INFO "WDT driver for Advantech single board computer initialising.\n"); | 318 | printk(KERN_INFO |
| 319 | "WDT driver for Advantech single board computer initialising.\n"); | ||
| 330 | 320 | ||
| 331 | err = platform_driver_register(&advwdt_driver); | 321 | err = platform_driver_register(&advwdt_driver); |
| 332 | if (err) | 322 | if (err) |
| 333 | return err; | 323 | return err; |
| 334 | 324 | ||
| 335 | advwdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); | 325 | advwdt_platform_device = platform_device_register_simple(DRV_NAME, |
| 326 | -1, NULL, 0); | ||
| 336 | if (IS_ERR(advwdt_platform_device)) { | 327 | if (IS_ERR(advwdt_platform_device)) { |
| 337 | err = PTR_ERR(advwdt_platform_device); | 328 | err = PTR_ERR(advwdt_platform_device); |
| 338 | goto unreg_platform_driver; | 329 | goto unreg_platform_driver; |
| @@ -345,8 +336,7 @@ unreg_platform_driver: | |||
| 345 | return err; | 336 | return err; |
| 346 | } | 337 | } |
| 347 | 338 | ||
| 348 | static void __exit | 339 | static void __exit advwdt_exit(void) |
| 349 | advwdt_exit(void) | ||
| 350 | { | 340 | { |
| 351 | platform_device_unregister(advwdt_platform_device); | 341 | platform_device_unregister(advwdt_platform_device); |
| 352 | platform_driver_unregister(&advwdt_driver); | 342 | platform_driver_unregister(&advwdt_driver); |
diff --git a/drivers/watchdog/alim1535_wdt.c b/drivers/watchdog/alim1535_wdt.c index 2b1fbdb2fcf7..2a7690ecf97d 100644 --- a/drivers/watchdog/alim1535_wdt.c +++ b/drivers/watchdog/alim1535_wdt.c | |||
| @@ -18,9 +18,8 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/fs.h> | 19 | #include <linux/fs.h> |
| 20 | #include <linux/pci.h> | 20 | #include <linux/pci.h> |
| 21 | 21 | #include <linux/uaccess.h> | |
| 22 | #include <asm/uaccess.h> | 22 | #include <linux/io.h> |
| 23 | #include <asm/io.h> | ||
| 24 | 23 | ||
| 25 | #define WATCHDOG_NAME "ALi_M1535" | 24 | #define WATCHDOG_NAME "ALi_M1535" |
| 26 | #define PFX WATCHDOG_NAME ": " | 25 | #define PFX WATCHDOG_NAME ": " |
| @@ -30,17 +29,21 @@ | |||
| 30 | static unsigned long ali_is_open; | 29 | static unsigned long ali_is_open; |
| 31 | static char ali_expect_release; | 30 | static char ali_expect_release; |
| 32 | static struct pci_dev *ali_pci; | 31 | static struct pci_dev *ali_pci; |
| 33 | static u32 ali_timeout_bits; /* stores the computed timeout */ | 32 | static u32 ali_timeout_bits; /* stores the computed timeout */ |
| 34 | static DEFINE_SPINLOCK(ali_lock); /* Guards the hardware */ | 33 | static DEFINE_SPINLOCK(ali_lock); /* Guards the hardware */ |
| 35 | 34 | ||
| 36 | /* module parameters */ | 35 | /* module parameters */ |
| 37 | static int timeout = WATCHDOG_TIMEOUT; | 36 | static int timeout = WATCHDOG_TIMEOUT; |
| 38 | module_param(timeout, int, 0); | 37 | module_param(timeout, int, 0); |
| 39 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (0<timeout<18000, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 38 | MODULE_PARM_DESC(timeout, |
| 39 | "Watchdog timeout in seconds. (0 < timeout < 18000, default=" | ||
| 40 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 40 | 41 | ||
| 41 | static int nowayout = WATCHDOG_NOWAYOUT; | 42 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 42 | module_param(nowayout, int, 0); | 43 | module_param(nowayout, int, 0); |
| 43 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 44 | MODULE_PARM_DESC(nowayout, |
| 45 | "Watchdog cannot be stopped once started (default=" | ||
| 46 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 44 | 47 | ||
| 45 | /* | 48 | /* |
| 46 | * ali_start - start watchdog countdown | 49 | * ali_start - start watchdog countdown |
| @@ -103,15 +106,16 @@ static void ali_keepalive(void) | |||
| 103 | 106 | ||
| 104 | static int ali_settimer(int t) | 107 | static int ali_settimer(int t) |
| 105 | { | 108 | { |
| 106 | if(t < 0) | 109 | if (t < 0) |
| 107 | return -EINVAL; | 110 | return -EINVAL; |
| 108 | else if(t < 60) | 111 | else if (t < 60) |
| 109 | ali_timeout_bits = t|(1<<6); | 112 | ali_timeout_bits = t|(1<<6); |
| 110 | else if(t < 3600) | 113 | else if (t < 3600) |
| 111 | ali_timeout_bits = (t/60)|(1<<7); | 114 | ali_timeout_bits = (t/60)|(1<<7); |
| 112 | else if(t < 18000) | 115 | else if (t < 18000) |
| 113 | ali_timeout_bits = (t/300)|(1<<6)|(1<<7); | 116 | ali_timeout_bits = (t/300)|(1<<6)|(1<<7); |
| 114 | else return -EINVAL; | 117 | else |
| 118 | return -EINVAL; | ||
| 115 | 119 | ||
| 116 | timeout = t; | 120 | timeout = t; |
| 117 | return 0; | 121 | return 0; |
| @@ -134,21 +138,22 @@ static int ali_settimer(int t) | |||
| 134 | */ | 138 | */ |
| 135 | 139 | ||
| 136 | static ssize_t ali_write(struct file *file, const char __user *data, | 140 | static ssize_t ali_write(struct file *file, const char __user *data, |
| 137 | size_t len, loff_t * ppos) | 141 | size_t len, loff_t *ppos) |
| 138 | { | 142 | { |
| 139 | /* See if we got the magic character 'V' and reload the timer */ | 143 | /* See if we got the magic character 'V' and reload the timer */ |
| 140 | if (len) { | 144 | if (len) { |
| 141 | if (!nowayout) { | 145 | if (!nowayout) { |
| 142 | size_t i; | 146 | size_t i; |
| 143 | 147 | ||
| 144 | /* note: just in case someone wrote the magic character | 148 | /* note: just in case someone wrote the |
| 145 | * five months ago... */ | 149 | magic character five months ago... */ |
| 146 | ali_expect_release = 0; | 150 | ali_expect_release = 0; |
| 147 | 151 | ||
| 148 | /* scan to see whether or not we got the magic character */ | 152 | /* scan to see whether or not we got |
| 153 | the magic character */ | ||
| 149 | for (i = 0; i != len; i++) { | 154 | for (i = 0; i != len; i++) { |
| 150 | char c; | 155 | char c; |
| 151 | if(get_user(c, data+i)) | 156 | if (get_user(c, data + i)) |
| 152 | return -EFAULT; | 157 | return -EFAULT; |
| 153 | if (c == 'V') | 158 | if (c == 'V') |
| 154 | ali_expect_release = 42; | 159 | ali_expect_release = 42; |
| @@ -163,7 +168,6 @@ static ssize_t ali_write(struct file *file, const char __user *data, | |||
| 163 | 168 | ||
| 164 | /* | 169 | /* |
| 165 | * ali_ioctl - handle watchdog ioctls | 170 | * ali_ioctl - handle watchdog ioctls |
| 166 | * @inode: VFS inode | ||
| 167 | * @file: VFS file pointer | 171 | * @file: VFS file pointer |
| 168 | * @cmd: ioctl number | 172 | * @cmd: ioctl number |
| 169 | * @arg: arguments to the ioctl | 173 | * @arg: arguments to the ioctl |
| @@ -172,8 +176,7 @@ static ssize_t ali_write(struct file *file, const char __user *data, | |||
| 172 | * we want an extension to enable irq ack monitoring and the like | 176 | * we want an extension to enable irq ack monitoring and the like |
| 173 | */ | 177 | */ |
| 174 | 178 | ||
| 175 | static int ali_ioctl(struct inode *inode, struct file *file, | 179 | static long ali_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 176 | unsigned int cmd, unsigned long arg) | ||
| 177 | { | 180 | { |
| 178 | void __user *argp = (void __user *)arg; | 181 | void __user *argp = (void __user *)arg; |
| 179 | int __user *p = argp; | 182 | int __user *p = argp; |
| @@ -186,57 +189,45 @@ static int ali_ioctl(struct inode *inode, struct file *file, | |||
| 186 | }; | 189 | }; |
| 187 | 190 | ||
| 188 | switch (cmd) { | 191 | switch (cmd) { |
| 189 | case WDIOC_GETSUPPORT: | 192 | case WDIOC_GETSUPPORT: |
| 190 | return copy_to_user(argp, &ident, | 193 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 191 | sizeof (ident)) ? -EFAULT : 0; | 194 | |
| 192 | 195 | case WDIOC_GETSTATUS: | |
| 193 | case WDIOC_GETSTATUS: | 196 | case WDIOC_GETBOOTSTATUS: |
| 194 | case WDIOC_GETBOOTSTATUS: | 197 | return put_user(0, p); |
| 195 | return put_user(0, p); | 198 | case WDIOC_SETOPTIONS: |
| 196 | 199 | { | |
| 197 | case WDIOC_KEEPALIVE: | 200 | int new_options, retval = -EINVAL; |
| 198 | ali_keepalive(); | 201 | |
| 199 | return 0; | 202 | if (get_user(new_options, p)) |
| 200 | 203 | return -EFAULT; | |
| 201 | case WDIOC_SETOPTIONS: | 204 | if (new_options & WDIOS_DISABLECARD) { |
| 202 | { | 205 | ali_stop(); |
| 203 | int new_options, retval = -EINVAL; | 206 | retval = 0; |
| 204 | |||
| 205 | if (get_user (new_options, p)) | ||
| 206 | return -EFAULT; | ||
| 207 | |||
| 208 | if (new_options & WDIOS_DISABLECARD) { | ||
| 209 | ali_stop(); | ||
| 210 | retval = 0; | ||
| 211 | } | ||
| 212 | |||
| 213 | if (new_options & WDIOS_ENABLECARD) { | ||
| 214 | ali_start(); | ||
| 215 | retval = 0; | ||
| 216 | } | ||
| 217 | |||
| 218 | return retval; | ||
| 219 | } | 207 | } |
| 220 | 208 | if (new_options & WDIOS_ENABLECARD) { | |
| 221 | case WDIOC_SETTIMEOUT: | 209 | ali_start(); |
| 222 | { | 210 | retval = 0; |
| 223 | int new_timeout; | ||
| 224 | |||
| 225 | if (get_user(new_timeout, p)) | ||
| 226 | return -EFAULT; | ||
| 227 | |||
| 228 | if (ali_settimer(new_timeout)) | ||
| 229 | return -EINVAL; | ||
| 230 | |||
| 231 | ali_keepalive(); | ||
| 232 | /* Fall */ | ||
| 233 | } | 211 | } |
| 234 | 212 | return retval; | |
| 235 | case WDIOC_GETTIMEOUT: | 213 | } |
| 236 | return put_user(timeout, p); | 214 | case WDIOC_KEEPALIVE: |
| 237 | 215 | ali_keepalive(); | |
| 238 | default: | 216 | return 0; |
| 239 | return -ENOTTY; | 217 | case WDIOC_SETTIMEOUT: |
| 218 | { | ||
| 219 | int new_timeout; | ||
| 220 | if (get_user(new_timeout, p)) | ||
| 221 | return -EFAULT; | ||
| 222 | if (ali_settimer(new_timeout)) | ||
| 223 | return -EINVAL; | ||
| 224 | ali_keepalive(); | ||
| 225 | /* Fall */ | ||
| 226 | } | ||
| 227 | case WDIOC_GETTIMEOUT: | ||
| 228 | return put_user(timeout, p); | ||
| 229 | default: | ||
| 230 | return -ENOTTY; | ||
| 240 | } | 231 | } |
| 241 | } | 232 | } |
| 242 | 233 | ||
| @@ -274,10 +265,11 @@ static int ali_release(struct inode *inode, struct file *file) | |||
| 274 | /* | 265 | /* |
| 275 | * Shut off the timer. | 266 | * Shut off the timer. |
| 276 | */ | 267 | */ |
| 277 | if (ali_expect_release == 42) { | 268 | if (ali_expect_release == 42) |
| 278 | ali_stop(); | 269 | ali_stop(); |
| 279 | } else { | 270 | else { |
| 280 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 271 | printk(KERN_CRIT PFX |
| 272 | "Unexpected close, not stopping watchdog!\n"); | ||
| 281 | ali_keepalive(); | 273 | ali_keepalive(); |
| 282 | } | 274 | } |
| 283 | clear_bit(0, &ali_is_open); | 275 | clear_bit(0, &ali_is_open); |
| @@ -292,13 +284,11 @@ static int ali_release(struct inode *inode, struct file *file) | |||
| 292 | */ | 284 | */ |
| 293 | 285 | ||
| 294 | 286 | ||
| 295 | static int ali_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 287 | static int ali_notify_sys(struct notifier_block *this, |
| 288 | unsigned long code, void *unused) | ||
| 296 | { | 289 | { |
| 297 | if (code==SYS_DOWN || code==SYS_HALT) { | 290 | if (code == SYS_DOWN || code == SYS_HALT) |
| 298 | /* Turn the WDT off */ | 291 | ali_stop(); /* Turn the WDT off */ |
| 299 | ali_stop(); | ||
| 300 | } | ||
| 301 | |||
| 302 | return NOTIFY_DONE; | 292 | return NOTIFY_DONE; |
| 303 | } | 293 | } |
| 304 | 294 | ||
| @@ -340,10 +330,10 @@ static int __init ali_find_watchdog(void) | |||
| 340 | 330 | ||
| 341 | /* Check for the a 7101 PMU */ | 331 | /* Check for the a 7101 PMU */ |
| 342 | pdev = pci_get_device(PCI_VENDOR_ID_AL, 0x7101, NULL); | 332 | pdev = pci_get_device(PCI_VENDOR_ID_AL, 0x7101, NULL); |
| 343 | if(pdev == NULL) | 333 | if (pdev == NULL) |
| 344 | return -ENODEV; | 334 | return -ENODEV; |
| 345 | 335 | ||
| 346 | if(pci_enable_device(pdev)) { | 336 | if (pci_enable_device(pdev)) { |
| 347 | pci_dev_put(pdev); | 337 | pci_dev_put(pdev); |
| 348 | return -EIO; | 338 | return -EIO; |
| 349 | } | 339 | } |
| @@ -355,9 +345,12 @@ static int __init ali_find_watchdog(void) | |||
| 355 | */ | 345 | */ |
| 356 | pci_read_config_dword(pdev, 0xCC, &wdog); | 346 | pci_read_config_dword(pdev, 0xCC, &wdog); |
| 357 | 347 | ||
| 358 | wdog &= ~0x3F; /* Timer bits */ | 348 | /* Timer bits */ |
| 359 | wdog &= ~((1<<27)|(1<<26)|(1<<25)|(1<<24)); /* Issued events */ | 349 | wdog &= ~0x3F; |
| 360 | wdog &= ~((1<<16)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)); /* No monitor bits */ | 350 | /* Issued events */ |
| 351 | wdog &= ~((1<<27)|(1<<26)|(1<<25)|(1<<24)); | ||
| 352 | /* No monitor bits */ | ||
| 353 | wdog &= ~((1<<16)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)); | ||
| 361 | 354 | ||
| 362 | pci_write_config_dword(pdev, 0xCC, wdog); | 355 | pci_write_config_dword(pdev, 0xCC, wdog); |
| 363 | 356 | ||
| @@ -369,12 +362,12 @@ static int __init ali_find_watchdog(void) | |||
| 369 | */ | 362 | */ |
| 370 | 363 | ||
| 371 | static const struct file_operations ali_fops = { | 364 | static const struct file_operations ali_fops = { |
| 372 | .owner = THIS_MODULE, | 365 | .owner = THIS_MODULE, |
| 373 | .llseek = no_llseek, | 366 | .llseek = no_llseek, |
| 374 | .write = ali_write, | 367 | .write = ali_write, |
| 375 | .ioctl = ali_ioctl, | 368 | .unlocked_ioctl = ali_ioctl, |
| 376 | .open = ali_open, | 369 | .open = ali_open, |
| 377 | .release = ali_release, | 370 | .release = ali_release, |
| 378 | }; | 371 | }; |
| 379 | 372 | ||
| 380 | static struct miscdevice ali_miscdev = { | 373 | static struct miscdevice ali_miscdev = { |
| @@ -399,15 +392,16 @@ static int __init watchdog_init(void) | |||
| 399 | int ret; | 392 | int ret; |
| 400 | 393 | ||
| 401 | /* Check whether or not the hardware watchdog is there */ | 394 | /* Check whether or not the hardware watchdog is there */ |
| 402 | if (ali_find_watchdog() != 0) { | 395 | if (ali_find_watchdog() != 0) |
| 403 | return -ENODEV; | 396 | return -ENODEV; |
| 404 | } | ||
| 405 | 397 | ||
| 406 | /* Check that the timeout value is within it's range ; if not reset to the default */ | 398 | /* Check that the timeout value is within it's range; |
| 399 | if not reset to the default */ | ||
| 407 | if (timeout < 1 || timeout >= 18000) { | 400 | if (timeout < 1 || timeout >= 18000) { |
| 408 | timeout = WATCHDOG_TIMEOUT; | 401 | timeout = WATCHDOG_TIMEOUT; |
| 409 | printk(KERN_INFO PFX "timeout value must be 0<timeout<18000, using %d\n", | 402 | printk(KERN_INFO PFX |
| 410 | timeout); | 403 | "timeout value must be 0 < timeout < 18000, using %d\n", |
| 404 | timeout); | ||
| 411 | } | 405 | } |
| 412 | 406 | ||
| 413 | /* Calculate the watchdog's timeout */ | 407 | /* Calculate the watchdog's timeout */ |
| @@ -415,15 +409,16 @@ static int __init watchdog_init(void) | |||
| 415 | 409 | ||
| 416 | ret = register_reboot_notifier(&ali_notifier); | 410 | ret = register_reboot_notifier(&ali_notifier); |
| 417 | if (ret != 0) { | 411 | if (ret != 0) { |
| 418 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 412 | printk(KERN_ERR PFX |
| 419 | ret); | 413 | "cannot register reboot notifier (err=%d)\n", ret); |
| 420 | goto out; | 414 | goto out; |
| 421 | } | 415 | } |
| 422 | 416 | ||
| 423 | ret = misc_register(&ali_miscdev); | 417 | ret = misc_register(&ali_miscdev); |
| 424 | if (ret != 0) { | 418 | if (ret != 0) { |
| 425 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 419 | printk(KERN_ERR PFX |
| 426 | WATCHDOG_MINOR, ret); | 420 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 421 | WATCHDOG_MINOR, ret); | ||
| 427 | goto unreg_reboot; | 422 | goto unreg_reboot; |
| 428 | } | 423 | } |
| 429 | 424 | ||
diff --git a/drivers/watchdog/alim7101_wdt.c b/drivers/watchdog/alim7101_wdt.c index 238273c98656..a045ef869439 100644 --- a/drivers/watchdog/alim7101_wdt.c +++ b/drivers/watchdog/alim7101_wdt.c | |||
| @@ -31,9 +31,9 @@ | |||
| 31 | #include <linux/init.h> | 31 | #include <linux/init.h> |
| 32 | #include <linux/fs.h> | 32 | #include <linux/fs.h> |
| 33 | #include <linux/pci.h> | 33 | #include <linux/pci.h> |
| 34 | #include <linux/io.h> | ||
| 35 | #include <linux/uaccess.h> | ||
| 34 | 36 | ||
| 35 | #include <asm/io.h> | ||
| 36 | #include <asm/uaccess.h> | ||
| 37 | #include <asm/system.h> | 37 | #include <asm/system.h> |
| 38 | 38 | ||
| 39 | #define OUR_NAME "alim7101_wdt" | 39 | #define OUR_NAME "alim7101_wdt" |
| @@ -60,13 +60,17 @@ | |||
| 60 | */ | 60 | */ |
| 61 | 61 | ||
| 62 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ | 62 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ |
| 63 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ | 63 | /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ |
| 64 | static int timeout = WATCHDOG_TIMEOUT; | ||
| 64 | module_param(timeout, int, 0); | 65 | module_param(timeout, int, 0); |
| 65 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 66 | MODULE_PARM_DESC(timeout, |
| 67 | "Watchdog timeout in seconds. (1<=timeout<=3600, default=" | ||
| 68 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 66 | 69 | ||
| 67 | static int use_gpio = 0; /* Use the pic (for a1d revision alim7101) */ | 70 | static int use_gpio; /* Use the pic (for a1d revision alim7101) */ |
| 68 | module_param(use_gpio, int, 0); | 71 | module_param(use_gpio, int, 0); |
| 69 | MODULE_PARM_DESC(use_gpio, "Use the gpio watchdog. (required by old cobalt boards)"); | 72 | MODULE_PARM_DESC(use_gpio, |
| 73 | "Use the gpio watchdog (required by old cobalt boards)."); | ||
| 70 | 74 | ||
| 71 | static void wdt_timer_ping(unsigned long); | 75 | static void wdt_timer_ping(unsigned long); |
| 72 | static DEFINE_TIMER(timer, wdt_timer_ping, 0, 1); | 76 | static DEFINE_TIMER(timer, wdt_timer_ping, 0, 1); |
| @@ -77,8 +81,9 @@ static struct pci_dev *alim7101_pmu; | |||
| 77 | 81 | ||
| 78 | static int nowayout = WATCHDOG_NOWAYOUT; | 82 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 79 | module_param(nowayout, int, 0); | 83 | module_param(nowayout, int, 0); |
| 80 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | 84 | MODULE_PARM_DESC(nowayout, |
| 81 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 85 | "Watchdog cannot be stopped once started (default=" |
| 86 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 82 | 87 | ||
| 83 | /* | 88 | /* |
| 84 | * Whack the dog | 89 | * Whack the dog |
| @@ -89,23 +94,26 @@ static void wdt_timer_ping(unsigned long data) | |||
| 89 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL | 94 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL |
| 90 | * we agree to ping the WDT | 95 | * we agree to ping the WDT |
| 91 | */ | 96 | */ |
| 92 | char tmp; | 97 | char tmp; |
| 93 | 98 | ||
| 94 | if(time_before(jiffies, next_heartbeat)) | 99 | if (time_before(jiffies, next_heartbeat)) { |
| 95 | { | ||
| 96 | /* Ping the WDT (this is actually a disarm/arm sequence) */ | 100 | /* Ping the WDT (this is actually a disarm/arm sequence) */ |
| 97 | pci_read_config_byte(alim7101_pmu, 0x92, &tmp); | 101 | pci_read_config_byte(alim7101_pmu, 0x92, &tmp); |
| 98 | pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); | 102 | pci_write_config_byte(alim7101_pmu, |
| 99 | pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp | ALI_WDT_ARM)); | 103 | ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); |
| 104 | pci_write_config_byte(alim7101_pmu, | ||
| 105 | ALI_7101_WDT, (tmp | ALI_WDT_ARM)); | ||
| 100 | if (use_gpio) { | 106 | if (use_gpio) { |
| 101 | pci_read_config_byte(alim7101_pmu, ALI_7101_GPIO_O, &tmp); | 107 | pci_read_config_byte(alim7101_pmu, |
| 102 | pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp | 108 | ALI_7101_GPIO_O, &tmp); |
| 103 | | 0x20); | 109 | pci_write_config_byte(alim7101_pmu, |
| 104 | pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp | 110 | ALI_7101_GPIO_O, tmp | 0x20); |
| 105 | & ~0x20); | 111 | pci_write_config_byte(alim7101_pmu, |
| 112 | ALI_7101_GPIO_O, tmp & ~0x20); | ||
| 106 | } | 113 | } |
| 107 | } else { | 114 | } else { |
| 108 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); | 115 | printk(KERN_WARNING PFX |
| 116 | "Heartbeat lost! Will not ping the watchdog\n"); | ||
| 109 | } | 117 | } |
| 110 | /* Re-set the timer interval */ | 118 | /* Re-set the timer interval */ |
| 111 | mod_timer(&timer, jiffies + WDT_INTERVAL); | 119 | mod_timer(&timer, jiffies + WDT_INTERVAL); |
| @@ -117,21 +125,27 @@ static void wdt_timer_ping(unsigned long data) | |||
| 117 | 125 | ||
| 118 | static void wdt_change(int writeval) | 126 | static void wdt_change(int writeval) |
| 119 | { | 127 | { |
| 120 | char tmp; | 128 | char tmp; |
| 121 | 129 | ||
| 122 | pci_read_config_byte(alim7101_pmu, ALI_7101_WDT, &tmp); | 130 | pci_read_config_byte(alim7101_pmu, ALI_7101_WDT, &tmp); |
| 123 | if (writeval == WDT_ENABLE) { | 131 | if (writeval == WDT_ENABLE) { |
| 124 | pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp | ALI_WDT_ARM)); | 132 | pci_write_config_byte(alim7101_pmu, |
| 133 | ALI_7101_WDT, (tmp | ALI_WDT_ARM)); | ||
| 125 | if (use_gpio) { | 134 | if (use_gpio) { |
| 126 | pci_read_config_byte(alim7101_pmu, ALI_7101_GPIO_O, &tmp); | 135 | pci_read_config_byte(alim7101_pmu, |
| 127 | pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp & ~0x20); | 136 | ALI_7101_GPIO_O, &tmp); |
| 137 | pci_write_config_byte(alim7101_pmu, | ||
| 138 | ALI_7101_GPIO_O, tmp & ~0x20); | ||
| 128 | } | 139 | } |
| 129 | 140 | ||
| 130 | } else { | 141 | } else { |
| 131 | pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); | 142 | pci_write_config_byte(alim7101_pmu, |
| 143 | ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); | ||
| 132 | if (use_gpio) { | 144 | if (use_gpio) { |
| 133 | pci_read_config_byte(alim7101_pmu, ALI_7101_GPIO_O, &tmp); | 145 | pci_read_config_byte(alim7101_pmu, |
| 134 | pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp | 0x20); | 146 | ALI_7101_GPIO_O, &tmp); |
| 147 | pci_write_config_byte(alim7101_pmu, | ||
| 148 | ALI_7101_GPIO_O, tmp | 0x20); | ||
| 135 | } | 149 | } |
| 136 | } | 150 | } |
| 137 | } | 151 | } |
| @@ -169,10 +183,11 @@ static void wdt_keepalive(void) | |||
| 169 | * /dev/watchdog handling | 183 | * /dev/watchdog handling |
| 170 | */ | 184 | */ |
| 171 | 185 | ||
| 172 | static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) | 186 | static ssize_t fop_write(struct file *file, const char __user *buf, |
| 187 | size_t count, loff_t *ppos) | ||
| 173 | { | 188 | { |
| 174 | /* See if we got the magic character 'V' and reload the timer */ | 189 | /* See if we got the magic character 'V' and reload the timer */ |
| 175 | if(count) { | 190 | if (count) { |
| 176 | if (!nowayout) { | 191 | if (!nowayout) { |
| 177 | size_t ofs; | 192 | size_t ofs; |
| 178 | 193 | ||
| @@ -183,7 +198,7 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou | |||
| 183 | /* now scan */ | 198 | /* now scan */ |
| 184 | for (ofs = 0; ofs != count; ofs++) { | 199 | for (ofs = 0; ofs != count; ofs++) { |
| 185 | char c; | 200 | char c; |
| 186 | if (get_user(c, buf+ofs)) | 201 | if (get_user(c, buf + ofs)) |
| 187 | return -EFAULT; | 202 | return -EFAULT; |
| 188 | if (c == 'V') | 203 | if (c == 'V') |
| 189 | wdt_expect_close = 42; | 204 | wdt_expect_close = 42; |
| @@ -195,119 +210,116 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou | |||
| 195 | return count; | 210 | return count; |
| 196 | } | 211 | } |
| 197 | 212 | ||
| 198 | static int fop_open(struct inode * inode, struct file * file) | 213 | static int fop_open(struct inode *inode, struct file *file) |
| 199 | { | 214 | { |
| 200 | /* Just in case we're already talking to someone... */ | 215 | /* Just in case we're already talking to someone... */ |
| 201 | if(test_and_set_bit(0, &wdt_is_open)) | 216 | if (test_and_set_bit(0, &wdt_is_open)) |
| 202 | return -EBUSY; | 217 | return -EBUSY; |
| 203 | /* Good, fire up the show */ | 218 | /* Good, fire up the show */ |
| 204 | wdt_startup(); | 219 | wdt_startup(); |
| 205 | return nonseekable_open(inode, file); | 220 | return nonseekable_open(inode, file); |
| 206 | } | 221 | } |
| 207 | 222 | ||
| 208 | static int fop_close(struct inode * inode, struct file * file) | 223 | static int fop_close(struct inode *inode, struct file *file) |
| 209 | { | 224 | { |
| 210 | if(wdt_expect_close == 42) | 225 | if (wdt_expect_close == 42) |
| 211 | wdt_turnoff(); | 226 | wdt_turnoff(); |
| 212 | else { | 227 | else { |
| 213 | /* wim: shouldn't there be a: del_timer(&timer); */ | 228 | /* wim: shouldn't there be a: del_timer(&timer); */ |
| 214 | printk(KERN_CRIT PFX "device file closed unexpectedly. Will not stop the WDT!\n"); | 229 | printk(KERN_CRIT PFX |
| 230 | "device file closed unexpectedly. Will not stop the WDT!\n"); | ||
| 215 | } | 231 | } |
| 216 | clear_bit(0, &wdt_is_open); | 232 | clear_bit(0, &wdt_is_open); |
| 217 | wdt_expect_close = 0; | 233 | wdt_expect_close = 0; |
| 218 | return 0; | 234 | return 0; |
| 219 | } | 235 | } |
| 220 | 236 | ||
| 221 | static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | 237 | static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 222 | { | 238 | { |
| 223 | void __user *argp = (void __user *)arg; | 239 | void __user *argp = (void __user *)arg; |
| 224 | int __user *p = argp; | 240 | int __user *p = argp; |
| 225 | static struct watchdog_info ident = | 241 | static struct watchdog_info ident = { |
| 226 | { | 242 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
| 227 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 243 | | WDIOF_MAGICCLOSE, |
| 228 | .firmware_version = 1, | 244 | .firmware_version = 1, |
| 229 | .identity = "ALiM7101", | 245 | .identity = "ALiM7101", |
| 230 | }; | 246 | }; |
| 231 | 247 | ||
| 232 | switch(cmd) | 248 | switch (cmd) { |
| 249 | case WDIOC_GETSUPPORT: | ||
| 250 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 251 | case WDIOC_GETSTATUS: | ||
| 252 | case WDIOC_GETBOOTSTATUS: | ||
| 253 | return put_user(0, p); | ||
| 254 | case WDIOC_SETOPTIONS: | ||
| 233 | { | 255 | { |
| 234 | case WDIOC_GETSUPPORT: | 256 | int new_options, retval = -EINVAL; |
| 235 | return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; | ||
| 236 | case WDIOC_GETSTATUS: | ||
| 237 | case WDIOC_GETBOOTSTATUS: | ||
| 238 | return put_user(0, p); | ||
| 239 | case WDIOC_KEEPALIVE: | ||
| 240 | wdt_keepalive(); | ||
| 241 | return 0; | ||
| 242 | case WDIOC_SETOPTIONS: | ||
| 243 | { | ||
| 244 | int new_options, retval = -EINVAL; | ||
| 245 | |||
| 246 | if(get_user(new_options, p)) | ||
| 247 | return -EFAULT; | ||
| 248 | |||
| 249 | if(new_options & WDIOS_DISABLECARD) { | ||
| 250 | wdt_turnoff(); | ||
| 251 | retval = 0; | ||
| 252 | } | ||
| 253 | 257 | ||
| 254 | if(new_options & WDIOS_ENABLECARD) { | 258 | if (get_user(new_options, p)) |
| 255 | wdt_startup(); | 259 | return -EFAULT; |
| 256 | retval = 0; | 260 | if (new_options & WDIOS_DISABLECARD) { |
| 257 | } | 261 | wdt_turnoff(); |
| 258 | 262 | retval = 0; | |
| 259 | return retval; | ||
| 260 | } | 263 | } |
| 261 | case WDIOC_SETTIMEOUT: | 264 | if (new_options & WDIOS_ENABLECARD) { |
| 262 | { | 265 | wdt_startup(); |
| 263 | int new_timeout; | 266 | retval = 0; |
| 264 | |||
| 265 | if(get_user(new_timeout, p)) | ||
| 266 | return -EFAULT; | ||
| 267 | |||
| 268 | if(new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */ | ||
| 269 | return -EINVAL; | ||
| 270 | |||
| 271 | timeout = new_timeout; | ||
| 272 | wdt_keepalive(); | ||
| 273 | /* Fall through */ | ||
| 274 | } | 267 | } |
| 275 | case WDIOC_GETTIMEOUT: | 268 | return retval; |
| 276 | return put_user(timeout, p); | 269 | } |
| 277 | default: | 270 | case WDIOC_KEEPALIVE: |
| 278 | return -ENOTTY; | 271 | wdt_keepalive(); |
| 272 | return 0; | ||
| 273 | case WDIOC_SETTIMEOUT: | ||
| 274 | { | ||
| 275 | int new_timeout; | ||
| 276 | |||
| 277 | if (get_user(new_timeout, p)) | ||
| 278 | return -EFAULT; | ||
| 279 | /* arbitrary upper limit */ | ||
| 280 | if (new_timeout < 1 || new_timeout > 3600) | ||
| 281 | return -EINVAL; | ||
| 282 | timeout = new_timeout; | ||
| 283 | wdt_keepalive(); | ||
| 284 | /* Fall through */ | ||
| 285 | } | ||
| 286 | case WDIOC_GETTIMEOUT: | ||
| 287 | return put_user(timeout, p); | ||
| 288 | default: | ||
| 289 | return -ENOTTY; | ||
| 279 | } | 290 | } |
| 280 | } | 291 | } |
| 281 | 292 | ||
| 282 | static const struct file_operations wdt_fops = { | 293 | static const struct file_operations wdt_fops = { |
| 283 | .owner= THIS_MODULE, | 294 | .owner = THIS_MODULE, |
| 284 | .llseek= no_llseek, | 295 | .llseek = no_llseek, |
| 285 | .write= fop_write, | 296 | .write = fop_write, |
| 286 | .open= fop_open, | 297 | .open = fop_open, |
| 287 | .release= fop_close, | 298 | .release = fop_close, |
| 288 | .ioctl= fop_ioctl, | 299 | .unlocked_ioctl = fop_ioctl, |
| 289 | }; | 300 | }; |
| 290 | 301 | ||
| 291 | static struct miscdevice wdt_miscdev = { | 302 | static struct miscdevice wdt_miscdev = { |
| 292 | .minor=WATCHDOG_MINOR, | 303 | .minor = WATCHDOG_MINOR, |
| 293 | .name="watchdog", | 304 | .name = "watchdog", |
| 294 | .fops=&wdt_fops, | 305 | .fops = &wdt_fops, |
| 295 | }; | 306 | }; |
| 296 | 307 | ||
| 297 | /* | 308 | /* |
| 298 | * Notifier for system down | 309 | * Notifier for system down |
| 299 | */ | 310 | */ |
| 300 | 311 | ||
| 301 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 312 | static int wdt_notify_sys(struct notifier_block *this, |
| 313 | unsigned long code, void *unused) | ||
| 302 | { | 314 | { |
| 303 | if (code==SYS_DOWN || code==SYS_HALT) | 315 | if (code == SYS_DOWN || code == SYS_HALT) |
| 304 | wdt_turnoff(); | 316 | wdt_turnoff(); |
| 305 | 317 | ||
| 306 | if (code==SYS_RESTART) { | 318 | if (code == SYS_RESTART) { |
| 307 | /* | 319 | /* |
| 308 | * Cobalt devices have no way of rebooting themselves other than | 320 | * Cobalt devices have no way of rebooting themselves other |
| 309 | * getting the watchdog to pull reset, so we restart the watchdog on | 321 | * than getting the watchdog to pull reset, so we restart the |
| 310 | * reboot with no heartbeat | 322 | * watchdog on reboot with no heartbeat |
| 311 | */ | 323 | */ |
| 312 | wdt_change(WDT_ENABLE); | 324 | wdt_change(WDT_ENABLE); |
| 313 | printk(KERN_INFO PFX "Watchdog timer is now enabled with no heartbeat - should reboot in ~1 second.\n"); | 325 | printk(KERN_INFO PFX "Watchdog timer is now enabled with no heartbeat - should reboot in ~1 second.\n"); |
| @@ -320,8 +332,7 @@ static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void | |||
| 320 | * turn the timebomb registers off. | 332 | * turn the timebomb registers off. |
| 321 | */ | 333 | */ |
| 322 | 334 | ||
| 323 | static struct notifier_block wdt_notifier= | 335 | static struct notifier_block wdt_notifier = { |
| 324 | { | ||
| 325 | .notifier_call = wdt_notify_sys, | 336 | .notifier_call = wdt_notify_sys, |
| 326 | }; | 337 | }; |
| 327 | 338 | ||
| @@ -354,7 +365,8 @@ static int __init alim7101_wdt_init(void) | |||
| 354 | ali1543_south = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, | 365 | ali1543_south = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, |
| 355 | NULL); | 366 | NULL); |
| 356 | if (!ali1543_south) { | 367 | if (!ali1543_south) { |
| 357 | printk(KERN_INFO PFX "ALi 1543 South-Bridge not present - WDT not set\n"); | 368 | printk(KERN_INFO PFX |
| 369 | "ALi 1543 South-Bridge not present - WDT not set\n"); | ||
| 358 | goto err_out; | 370 | goto err_out; |
| 359 | } | 371 | } |
| 360 | pci_read_config_byte(ali1543_south, 0x5e, &tmp); | 372 | pci_read_config_byte(ali1543_south, 0x5e, &tmp); |
| @@ -363,24 +375,25 @@ static int __init alim7101_wdt_init(void) | |||
| 363 | if (!use_gpio) { | 375 | if (!use_gpio) { |
| 364 | printk(KERN_INFO PFX "Detected old alim7101 revision 'a1d'. If this is a cobalt board, set the 'use_gpio' module parameter.\n"); | 376 | printk(KERN_INFO PFX "Detected old alim7101 revision 'a1d'. If this is a cobalt board, set the 'use_gpio' module parameter.\n"); |
| 365 | goto err_out; | 377 | goto err_out; |
| 366 | } | 378 | } |
| 367 | nowayout = 1; | 379 | nowayout = 1; |
| 368 | } else if ((tmp & 0x1e) != 0x12 && (tmp & 0x1e) != 0x00) { | 380 | } else if ((tmp & 0x1e) != 0x12 && (tmp & 0x1e) != 0x00) { |
| 369 | printk(KERN_INFO PFX "ALi 1543 South-Bridge does not have the correct revision number (???1001?) - WDT not set\n"); | 381 | printk(KERN_INFO PFX "ALi 1543 South-Bridge does not have the correct revision number (???1001?) - WDT not set\n"); |
| 370 | goto err_out; | 382 | goto err_out; |
| 371 | } | 383 | } |
| 372 | 384 | ||
| 373 | if(timeout < 1 || timeout > 3600) /* arbitrary upper limit */ | 385 | if (timeout < 1 || timeout > 3600) { |
| 374 | { | 386 | /* arbitrary upper limit */ |
| 375 | timeout = WATCHDOG_TIMEOUT; | 387 | timeout = WATCHDOG_TIMEOUT; |
| 376 | printk(KERN_INFO PFX "timeout value must be 1<=x<=3600, using %d\n", | 388 | printk(KERN_INFO PFX |
| 377 | timeout); | 389 | "timeout value must be 1 <= x <= 3600, using %d\n", |
| 390 | timeout); | ||
| 378 | } | 391 | } |
| 379 | 392 | ||
| 380 | rc = register_reboot_notifier(&wdt_notifier); | 393 | rc = register_reboot_notifier(&wdt_notifier); |
| 381 | if (rc) { | 394 | if (rc) { |
| 382 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 395 | printk(KERN_ERR PFX |
| 383 | rc); | 396 | "cannot register reboot notifier (err=%d)\n", rc); |
| 384 | goto err_out; | 397 | goto err_out; |
| 385 | } | 398 | } |
| 386 | 399 | ||
| @@ -391,9 +404,8 @@ static int __init alim7101_wdt_init(void) | |||
| 391 | goto err_out_reboot; | 404 | goto err_out_reboot; |
| 392 | } | 405 | } |
| 393 | 406 | ||
| 394 | if (nowayout) { | 407 | if (nowayout) |
| 395 | __module_get(THIS_MODULE); | 408 | __module_get(THIS_MODULE); |
| 396 | } | ||
| 397 | 409 | ||
| 398 | printk(KERN_INFO PFX "WDT driver for ALi M7101 initialised. timeout=%d sec (nowayout=%d)\n", | 410 | printk(KERN_INFO PFX "WDT driver for ALi M7101 initialised. timeout=%d sec (nowayout=%d)\n", |
| 399 | timeout, nowayout); | 411 | timeout, nowayout); |
diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index ef7b0d67095e..55dcbfe2bb72 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c | |||
| @@ -213,7 +213,7 @@ static int ar7_wdt_notify_sys(struct notifier_block *this, | |||
| 213 | } | 213 | } |
| 214 | 214 | ||
| 215 | static struct notifier_block ar7_wdt_notifier = { | 215 | static struct notifier_block ar7_wdt_notifier = { |
| 216 | .notifier_call = ar7_wdt_notify_sys | 216 | .notifier_call = ar7_wdt_notify_sys, |
| 217 | }; | 217 | }; |
| 218 | 218 | ||
| 219 | static ssize_t ar7_wdt_write(struct file *file, const char *data, | 219 | static ssize_t ar7_wdt_write(struct file *file, const char *data, |
| @@ -230,7 +230,7 @@ static ssize_t ar7_wdt_write(struct file *file, const char *data, | |||
| 230 | expect_close = 0; | 230 | expect_close = 0; |
| 231 | for (i = 0; i < len; ++i) { | 231 | for (i = 0; i < len; ++i) { |
| 232 | char c; | 232 | char c; |
| 233 | if (get_user(c, data+i)) | 233 | if (get_user(c, data + i)) |
| 234 | return -EFAULT; | 234 | return -EFAULT; |
| 235 | if (c == 'V') | 235 | if (c == 'V') |
| 236 | expect_close = 1; | 236 | expect_close = 1; |
| @@ -251,8 +251,6 @@ static long ar7_wdt_ioctl(struct file *file, | |||
| 251 | int new_margin; | 251 | int new_margin; |
| 252 | 252 | ||
| 253 | switch (cmd) { | 253 | switch (cmd) { |
| 254 | default: | ||
| 255 | return -ENOTTY; | ||
| 256 | case WDIOC_GETSUPPORT: | 254 | case WDIOC_GETSUPPORT: |
| 257 | if (copy_to_user((struct watchdog_info *)arg, &ident, | 255 | if (copy_to_user((struct watchdog_info *)arg, &ident, |
| 258 | sizeof(ident))) | 256 | sizeof(ident))) |
| @@ -281,6 +279,8 @@ static long ar7_wdt_ioctl(struct file *file, | |||
| 281 | if (put_user(margin, (int *)arg)) | 279 | if (put_user(margin, (int *)arg)) |
| 282 | return -EFAULT; | 280 | return -EFAULT; |
| 283 | return 0; | 281 | return 0; |
| 282 | default: | ||
| 283 | return -ENOTTY; | ||
| 284 | } | 284 | } |
| 285 | } | 285 | } |
| 286 | 286 | ||
diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c index ae0fca5e8749..e8ae638e5804 100644 --- a/drivers/watchdog/at32ap700x_wdt.c +++ b/drivers/watchdog/at32ap700x_wdt.c | |||
| @@ -212,8 +212,8 @@ static struct watchdog_info at32_wdt_info = { | |||
| 212 | /* | 212 | /* |
| 213 | * Handle commands from user-space. | 213 | * Handle commands from user-space. |
| 214 | */ | 214 | */ |
| 215 | static int at32_wdt_ioctl(struct inode *inode, struct file *file, | 215 | static long at32_wdt_ioctl(struct file *file, |
| 216 | unsigned int cmd, unsigned long arg) | 216 | unsigned int cmd, unsigned long arg) |
| 217 | { | 217 | { |
| 218 | int ret = -ENOTTY; | 218 | int ret = -ENOTTY; |
| 219 | int time; | 219 | int time; |
| @@ -221,27 +221,10 @@ static int at32_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 221 | int __user *p = argp; | 221 | int __user *p = argp; |
| 222 | 222 | ||
| 223 | switch (cmd) { | 223 | switch (cmd) { |
| 224 | case WDIOC_KEEPALIVE: | ||
| 225 | at32_wdt_pat(); | ||
| 226 | ret = 0; | ||
| 227 | break; | ||
| 228 | case WDIOC_GETSUPPORT: | 224 | case WDIOC_GETSUPPORT: |
| 229 | ret = copy_to_user(argp, &at32_wdt_info, | 225 | ret = copy_to_user(argp, &at32_wdt_info, |
| 230 | sizeof(at32_wdt_info)) ? -EFAULT : 0; | 226 | sizeof(at32_wdt_info)) ? -EFAULT : 0; |
| 231 | break; | 227 | break; |
| 232 | case WDIOC_SETTIMEOUT: | ||
| 233 | ret = get_user(time, p); | ||
| 234 | if (ret) | ||
| 235 | break; | ||
| 236 | ret = at32_wdt_settimeout(time); | ||
| 237 | if (ret) | ||
| 238 | break; | ||
| 239 | /* Enable new time value */ | ||
| 240 | at32_wdt_start(); | ||
| 241 | /* fall through */ | ||
| 242 | case WDIOC_GETTIMEOUT: | ||
| 243 | ret = put_user(wdt->timeout, p); | ||
| 244 | break; | ||
| 245 | case WDIOC_GETSTATUS: | 228 | case WDIOC_GETSTATUS: |
| 246 | ret = put_user(0, p); | 229 | ret = put_user(0, p); |
| 247 | break; | 230 | break; |
| @@ -258,6 +241,23 @@ static int at32_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 258 | at32_wdt_start(); | 241 | at32_wdt_start(); |
| 259 | ret = 0; | 242 | ret = 0; |
| 260 | break; | 243 | break; |
| 244 | case WDIOC_KEEPALIVE: | ||
| 245 | at32_wdt_pat(); | ||
| 246 | ret = 0; | ||
| 247 | break; | ||
| 248 | case WDIOC_SETTIMEOUT: | ||
| 249 | ret = get_user(time, p); | ||
| 250 | if (ret) | ||
| 251 | break; | ||
| 252 | ret = at32_wdt_settimeout(time); | ||
| 253 | if (ret) | ||
| 254 | break; | ||
| 255 | /* Enable new time value */ | ||
| 256 | at32_wdt_start(); | ||
| 257 | /* fall through */ | ||
| 258 | case WDIOC_GETTIMEOUT: | ||
| 259 | ret = put_user(wdt->timeout, p); | ||
| 260 | break; | ||
| 261 | } | 261 | } |
| 262 | 262 | ||
| 263 | return ret; | 263 | return ret; |
| @@ -283,7 +283,7 @@ static ssize_t at32_wdt_write(struct file *file, const char __user *data, | |||
| 283 | */ | 283 | */ |
| 284 | for (i = 0; i != len; i++) { | 284 | for (i = 0; i != len; i++) { |
| 285 | char c; | 285 | char c; |
| 286 | if (get_user(c, data+i)) | 286 | if (get_user(c, data + i)) |
| 287 | return -EFAULT; | 287 | return -EFAULT; |
| 288 | if (c == 'V') | 288 | if (c == 'V') |
| 289 | expect_release = 42; | 289 | expect_release = 42; |
| @@ -298,7 +298,7 @@ static ssize_t at32_wdt_write(struct file *file, const char __user *data, | |||
| 298 | static const struct file_operations at32_wdt_fops = { | 298 | static const struct file_operations at32_wdt_fops = { |
| 299 | .owner = THIS_MODULE, | 299 | .owner = THIS_MODULE, |
| 300 | .llseek = no_llseek, | 300 | .llseek = no_llseek, |
| 301 | .ioctl = at32_wdt_ioctl, | 301 | .unlocked_ioctl = at32_wdt_ioctl, |
| 302 | .open = at32_wdt_open, | 302 | .open = at32_wdt_open, |
| 303 | .release = at32_wdt_close, | 303 | .release = at32_wdt_close, |
| 304 | .write = at32_wdt_write, | 304 | .write = at32_wdt_write, |
| @@ -391,7 +391,6 @@ static int __exit at32_wdt_remove(struct platform_device *pdev) | |||
| 391 | wdt = NULL; | 391 | wdt = NULL; |
| 392 | platform_set_drvdata(pdev, NULL); | 392 | platform_set_drvdata(pdev, NULL); |
| 393 | } | 393 | } |
| 394 | |||
| 395 | return 0; | 394 | return 0; |
| 396 | } | 395 | } |
| 397 | 396 | ||
diff --git a/drivers/watchdog/at91rm9200_wdt.c b/drivers/watchdog/at91rm9200_wdt.c index bf872aa2b9f3..bacd867dd22e 100644 --- a/drivers/watchdog/at91rm9200_wdt.c +++ b/drivers/watchdog/at91rm9200_wdt.c | |||
| @@ -20,10 +20,9 @@ | |||
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/types.h> | 21 | #include <linux/types.h> |
| 22 | #include <linux/watchdog.h> | 22 | #include <linux/watchdog.h> |
| 23 | #include <asm/uaccess.h> | 23 | #include <linux/uaccess.h> |
| 24 | #include <mach/at91_st.h> | 24 | #include <mach/at91_st.h> |
| 25 | 25 | ||
| 26 | |||
| 27 | #define WDT_DEFAULT_TIME 5 /* seconds */ | 26 | #define WDT_DEFAULT_TIME 5 /* seconds */ |
| 28 | #define WDT_MAX_TIME 256 /* seconds */ | 27 | #define WDT_MAX_TIME 256 /* seconds */ |
| 29 | 28 | ||
| @@ -31,11 +30,14 @@ static int wdt_time = WDT_DEFAULT_TIME; | |||
| 31 | static int nowayout = WATCHDOG_NOWAYOUT; | 30 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 32 | 31 | ||
| 33 | module_param(wdt_time, int, 0); | 32 | module_param(wdt_time, int, 0); |
| 34 | MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="__MODULE_STRING(WDT_DEFAULT_TIME) ")"); | 33 | MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default=" |
| 34 | __MODULE_STRING(WDT_DEFAULT_TIME) ")"); | ||
| 35 | 35 | ||
| 36 | #ifdef CONFIG_WATCHDOG_NOWAYOUT | 36 | #ifdef CONFIG_WATCHDOG_NOWAYOUT |
| 37 | module_param(nowayout, int, 0); | 37 | module_param(nowayout, int, 0); |
| 38 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 38 | MODULE_PARM_DESC(nowayout, |
| 39 | "Watchdog cannot be stopped once started (default=" | ||
| 40 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 39 | #endif | 41 | #endif |
| 40 | 42 | ||
| 41 | 43 | ||
| @@ -46,7 +48,7 @@ static unsigned long at91wdt_busy; | |||
| 46 | /* | 48 | /* |
| 47 | * Disable the watchdog. | 49 | * Disable the watchdog. |
| 48 | */ | 50 | */ |
| 49 | static void inline at91_wdt_stop(void) | 51 | static inline void at91_wdt_stop(void) |
| 50 | { | 52 | { |
| 51 | at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN); | 53 | at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN); |
| 52 | } | 54 | } |
| @@ -54,16 +56,17 @@ static void inline at91_wdt_stop(void) | |||
| 54 | /* | 56 | /* |
| 55 | * Enable and reset the watchdog. | 57 | * Enable and reset the watchdog. |
| 56 | */ | 58 | */ |
| 57 | static void inline at91_wdt_start(void) | 59 | static inline void at91_wdt_start(void) |
| 58 | { | 60 | { |
| 59 | at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN | (((65536 * wdt_time) >> 8) & AT91_ST_WDV)); | 61 | at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN | |
| 62 | (((65536 * wdt_time) >> 8) & AT91_ST_WDV)); | ||
| 60 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); | 63 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); |
| 61 | } | 64 | } |
| 62 | 65 | ||
| 63 | /* | 66 | /* |
| 64 | * Reload the watchdog timer. (ie, pat the watchdog) | 67 | * Reload the watchdog timer. (ie, pat the watchdog) |
| 65 | */ | 68 | */ |
| 66 | static void inline at91_wdt_reload(void) | 69 | static inline void at91_wdt_reload(void) |
| 67 | { | 70 | { |
| 68 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); | 71 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); |
| 69 | } | 72 | } |
| @@ -89,8 +92,9 @@ static int at91_wdt_open(struct inode *inode, struct file *file) | |||
| 89 | */ | 92 | */ |
| 90 | static int at91_wdt_close(struct inode *inode, struct file *file) | 93 | static int at91_wdt_close(struct inode *inode, struct file *file) |
| 91 | { | 94 | { |
| 95 | /* Disable the watchdog when file is closed */ | ||
| 92 | if (!nowayout) | 96 | if (!nowayout) |
| 93 | at91_wdt_stop(); /* Disable the watchdog when file is closed */ | 97 | at91_wdt_stop(); |
| 94 | 98 | ||
| 95 | clear_bit(0, &at91wdt_busy); | 99 | clear_bit(0, &at91wdt_busy); |
| 96 | return 0; | 100 | return 0; |
| @@ -110,7 +114,8 @@ static int at91_wdt_settimeout(int new_time) | |||
| 110 | if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) | 114 | if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) |
| 111 | return -EINVAL; | 115 | return -EINVAL; |
| 112 | 116 | ||
| 113 | /* Set new watchdog time. It will be used when at91_wdt_start() is called. */ | 117 | /* Set new watchdog time. It will be used when |
| 118 | at91_wdt_start() is called. */ | ||
| 114 | wdt_time = new_time; | 119 | wdt_time = new_time; |
| 115 | return 0; | 120 | return 0; |
| 116 | } | 121 | } |
| @@ -123,60 +128,52 @@ static struct watchdog_info at91_wdt_info = { | |||
| 123 | /* | 128 | /* |
| 124 | * Handle commands from user-space. | 129 | * Handle commands from user-space. |
| 125 | */ | 130 | */ |
| 126 | static int at91_wdt_ioctl(struct inode *inode, struct file *file, | 131 | static long at91_wdt_ioct(struct file *file, |
| 127 | unsigned int cmd, unsigned long arg) | 132 | unsigned int cmd, unsigned long arg) |
| 128 | { | 133 | { |
| 129 | void __user *argp = (void __user *)arg; | 134 | void __user *argp = (void __user *)arg; |
| 130 | int __user *p = argp; | 135 | int __user *p = argp; |
| 131 | int new_value; | 136 | int new_value; |
| 132 | 137 | ||
| 133 | switch(cmd) { | 138 | switch (cmd) { |
| 134 | case WDIOC_KEEPALIVE: | 139 | case WDIOC_GETSUPPORT: |
| 135 | at91_wdt_reload(); /* pat the watchdog */ | 140 | return copy_to_user(argp, &at91_wdt_info, |
| 136 | return 0; | 141 | sizeof(at91_wdt_info)) ? -EFAULT : 0; |
| 137 | 142 | case WDIOC_GETSTATUS: | |
| 138 | case WDIOC_GETSUPPORT: | 143 | case WDIOC_GETBOOTSTATUS: |
| 139 | return copy_to_user(argp, &at91_wdt_info, sizeof(at91_wdt_info)) ? -EFAULT : 0; | 144 | return put_user(0, p); |
| 140 | 145 | case WDIOC_SETOPTIONS: | |
| 141 | case WDIOC_SETTIMEOUT: | 146 | if (get_user(new_value, p)) |
| 142 | if (get_user(new_value, p)) | 147 | return -EFAULT; |
| 143 | return -EFAULT; | 148 | if (new_value & WDIOS_DISABLECARD) |
| 144 | 149 | at91_wdt_stop(); | |
| 145 | if (at91_wdt_settimeout(new_value)) | 150 | if (new_value & WDIOS_ENABLECARD) |
| 146 | return -EINVAL; | ||
| 147 | |||
| 148 | /* Enable new time value */ | ||
| 149 | at91_wdt_start(); | 151 | at91_wdt_start(); |
| 150 | 152 | return 0; | |
| 151 | /* Return current value */ | 153 | case WDIOC_KEEPALIVE: |
| 152 | return put_user(wdt_time, p); | 154 | at91_wdt_reload(); /* pat the watchdog */ |
| 153 | 155 | return 0; | |
| 154 | case WDIOC_GETTIMEOUT: | 156 | case WDIOC_SETTIMEOUT: |
| 155 | return put_user(wdt_time, p); | 157 | if (get_user(new_value, p)) |
| 156 | 158 | return -EFAULT; | |
| 157 | case WDIOC_GETSTATUS: | 159 | if (at91_wdt_settimeout(new_value)) |
| 158 | case WDIOC_GETBOOTSTATUS: | 160 | return -EINVAL; |
| 159 | return put_user(0, p); | 161 | /* Enable new time value */ |
| 160 | 162 | at91_wdt_start(); | |
| 161 | case WDIOC_SETOPTIONS: | 163 | /* Return current value */ |
| 162 | if (get_user(new_value, p)) | 164 | return put_user(wdt_time, p); |
| 163 | return -EFAULT; | 165 | case WDIOC_GETTIMEOUT: |
| 164 | 166 | return put_user(wdt_time, p); | |
| 165 | if (new_value & WDIOS_DISABLECARD) | 167 | default: |
| 166 | at91_wdt_stop(); | 168 | return -ENOTTY; |
| 167 | if (new_value & WDIOS_ENABLECARD) | ||
| 168 | at91_wdt_start(); | ||
| 169 | return 0; | ||
| 170 | |||
| 171 | default: | ||
| 172 | return -ENOTTY; | ||
| 173 | } | 169 | } |
| 174 | } | 170 | } |
| 175 | 171 | ||
| 176 | /* | 172 | /* |
| 177 | * Pat the watchdog whenever device is written to. | 173 | * Pat the watchdog whenever device is written to. |
| 178 | */ | 174 | */ |
| 179 | static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) | 175 | static ssize_t at91_wdt_write(struct file *file, const char *data, |
| 176 | size_t len, loff_t *ppos) | ||
| 180 | { | 177 | { |
| 181 | at91_wdt_reload(); /* pat the watchdog */ | 178 | at91_wdt_reload(); /* pat the watchdog */ |
| 182 | return len; | 179 | return len; |
| @@ -187,7 +184,7 @@ static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len, l | |||
| 187 | static const struct file_operations at91wdt_fops = { | 184 | static const struct file_operations at91wdt_fops = { |
| 188 | .owner = THIS_MODULE, | 185 | .owner = THIS_MODULE, |
| 189 | .llseek = no_llseek, | 186 | .llseek = no_llseek, |
| 190 | .ioctl = at91_wdt_ioctl, | 187 | .unlocked_ioctl = at91_wdt_ioctl, |
| 191 | .open = at91_wdt_open, | 188 | .open = at91_wdt_open, |
| 192 | .release = at91_wdt_close, | 189 | .release = at91_wdt_close, |
| 193 | .write = at91_wdt_write, | 190 | .write = at91_wdt_write, |
| @@ -211,7 +208,8 @@ static int __init at91wdt_probe(struct platform_device *pdev) | |||
| 211 | if (res) | 208 | if (res) |
| 212 | return res; | 209 | return res; |
| 213 | 210 | ||
| 214 | printk("AT91 Watchdog Timer enabled (%d seconds%s)\n", wdt_time, nowayout ? ", nowayout" : ""); | 211 | printk(KERN_INFO "AT91 Watchdog Timer enabled (%d seconds%s)\n", |
| 212 | wdt_time, nowayout ? ", nowayout" : ""); | ||
| 215 | return 0; | 213 | return 0; |
| 216 | } | 214 | } |
| 217 | 215 | ||
| @@ -265,7 +263,8 @@ static struct platform_driver at91wdt_driver = { | |||
| 265 | 263 | ||
| 266 | static int __init at91_wdt_init(void) | 264 | static int __init at91_wdt_init(void) |
| 267 | { | 265 | { |
| 268 | /* Check that the heartbeat value is within range; if not reset to the default */ | 266 | /* Check that the heartbeat value is within range; |
| 267 | if not reset to the default */ | ||
| 269 | if (at91_wdt_settimeout(wdt_time)) { | 268 | if (at91_wdt_settimeout(wdt_time)) { |
| 270 | at91_wdt_settimeout(WDT_DEFAULT_TIME); | 269 | at91_wdt_settimeout(WDT_DEFAULT_TIME); |
| 271 | pr_info("at91_wdt: wdt_time value must be 1 <= wdt_time <= 256, using %d\n", wdt_time); | 270 | pr_info("at91_wdt: wdt_time value must be 1 <= wdt_time <= 256, using %d\n", wdt_time); |
diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 03b3e3d91e7c..31b42253054e 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c | |||
| @@ -24,8 +24,8 @@ | |||
| 24 | #include <linux/reboot.h> | 24 | #include <linux/reboot.h> |
| 25 | #include <linux/init.h> | 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/uaccess.h> | ||
| 27 | #include <asm/blackfin.h> | 28 | #include <asm/blackfin.h> |
| 28 | #include <asm/uaccess.h> | ||
| 29 | 29 | ||
| 30 | #define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args) | 30 | #define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args) |
| 31 | #define stampit() stamp("here i am") | 31 | #define stampit() stamp("here i am") |
| @@ -148,7 +148,8 @@ static int bfin_wdt_set_timeout(unsigned long t) | |||
| 148 | int run = bfin_wdt_running(); | 148 | int run = bfin_wdt_running(); |
| 149 | bfin_wdt_stop(); | 149 | bfin_wdt_stop(); |
| 150 | bfin_write_WDOG_CNT(cnt); | 150 | bfin_write_WDOG_CNT(cnt); |
| 151 | if (run) bfin_wdt_start(); | 151 | if (run) |
| 152 | bfin_wdt_start(); | ||
| 152 | } | 153 | } |
| 153 | spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); | 154 | spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); |
| 154 | 155 | ||
| @@ -191,16 +192,15 @@ static int bfin_wdt_release(struct inode *inode, struct file *file) | |||
| 191 | { | 192 | { |
| 192 | stampit(); | 193 | stampit(); |
| 193 | 194 | ||
| 194 | if (expect_close == 42) { | 195 | if (expect_close == 42) |
| 195 | bfin_wdt_stop(); | 196 | bfin_wdt_stop(); |
| 196 | } else { | 197 | else { |
| 197 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 198 | printk(KERN_CRIT PFX |
| 199 | "Unexpected close, not stopping watchdog!\n"); | ||
| 198 | bfin_wdt_keepalive(); | 200 | bfin_wdt_keepalive(); |
| 199 | } | 201 | } |
| 200 | |||
| 201 | expect_close = 0; | 202 | expect_close = 0; |
| 202 | clear_bit(0, &open_check); | 203 | clear_bit(0, &open_check); |
| 203 | |||
| 204 | return 0; | 204 | return 0; |
| 205 | } | 205 | } |
| 206 | 206 | ||
| @@ -214,7 +214,7 @@ static int bfin_wdt_release(struct inode *inode, struct file *file) | |||
| 214 | * Pings the watchdog on write. | 214 | * Pings the watchdog on write. |
| 215 | */ | 215 | */ |
| 216 | static ssize_t bfin_wdt_write(struct file *file, const char __user *data, | 216 | static ssize_t bfin_wdt_write(struct file *file, const char __user *data, |
| 217 | size_t len, loff_t *ppos) | 217 | size_t len, loff_t *ppos) |
| 218 | { | 218 | { |
| 219 | stampit(); | 219 | stampit(); |
| 220 | 220 | ||
| @@ -241,7 +241,6 @@ static ssize_t bfin_wdt_write(struct file *file, const char __user *data, | |||
| 241 | 241 | ||
| 242 | /** | 242 | /** |
| 243 | * bfin_wdt_ioctl - Query Device | 243 | * bfin_wdt_ioctl - Query Device |
| 244 | * @inode: inode of device | ||
| 245 | * @file: file handle of device | 244 | * @file: file handle of device |
| 246 | * @cmd: watchdog command | 245 | * @cmd: watchdog command |
| 247 | * @arg: argument | 246 | * @arg: argument |
| @@ -249,8 +248,8 @@ static ssize_t bfin_wdt_write(struct file *file, const char __user *data, | |||
| 249 | * Query basic information from the device or ping it, as outlined by the | 248 | * Query basic information from the device or ping it, as outlined by the |
| 250 | * watchdog API. | 249 | * watchdog API. |
| 251 | */ | 250 | */ |
| 252 | static int bfin_wdt_ioctl(struct inode *inode, struct file *file, | 251 | static long bfin_wdt_ioctl(struct file *file, |
| 253 | unsigned int cmd, unsigned long arg) | 252 | unsigned int cmd, unsigned long arg) |
| 254 | { | 253 | { |
| 255 | void __user *argp = (void __user *)arg; | 254 | void __user *argp = (void __user *)arg; |
| 256 | int __user *p = argp; | 255 | int __user *p = argp; |
| @@ -258,59 +257,49 @@ static int bfin_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 258 | stampit(); | 257 | stampit(); |
| 259 | 258 | ||
| 260 | switch (cmd) { | 259 | switch (cmd) { |
| 261 | default: | 260 | case WDIOC_GETSUPPORT: |
| 262 | return -ENOTTY; | 261 | if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info))) |
| 263 | 262 | return -EFAULT; | |
| 264 | case WDIOC_GETSUPPORT: | 263 | else |
| 265 | if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info))) | ||
| 266 | return -EFAULT; | ||
| 267 | else | ||
| 268 | return 0; | ||
| 269 | |||
| 270 | case WDIOC_GETSTATUS: | ||
| 271 | case WDIOC_GETBOOTSTATUS: | ||
| 272 | return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p); | ||
| 273 | |||
| 274 | case WDIOC_KEEPALIVE: | ||
| 275 | bfin_wdt_keepalive(); | ||
| 276 | return 0; | 264 | return 0; |
| 277 | 265 | case WDIOC_GETSTATUS: | |
| 278 | case WDIOC_SETTIMEOUT: { | 266 | case WDIOC_GETBOOTSTATUS: |
| 279 | int new_timeout; | 267 | return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p); |
| 280 | 268 | case WDIOC_SETOPTIONS: { | |
| 281 | if (get_user(new_timeout, p)) | 269 | unsigned long flags; |
| 282 | return -EFAULT; | 270 | int options, ret = -EINVAL; |
| 283 | 271 | ||
| 284 | if (bfin_wdt_set_timeout(new_timeout)) | 272 | if (get_user(options, p)) |
| 285 | return -EINVAL; | 273 | return -EFAULT; |
| 274 | |||
| 275 | spin_lock_irqsave(&bfin_wdt_spinlock, flags); | ||
| 276 | if (options & WDIOS_DISABLECARD) { | ||
| 277 | bfin_wdt_stop(); | ||
| 278 | ret = 0; | ||
| 286 | } | 279 | } |
| 287 | /* Fall */ | 280 | if (options & WDIOS_ENABLECARD) { |
| 288 | case WDIOC_GETTIMEOUT: | 281 | bfin_wdt_start(); |
| 289 | return put_user(timeout, p); | 282 | ret = 0; |
| 290 | |||
| 291 | case WDIOC_SETOPTIONS: { | ||
| 292 | unsigned long flags; | ||
| 293 | int options, ret = -EINVAL; | ||
| 294 | |||
| 295 | if (get_user(options, p)) | ||
| 296 | return -EFAULT; | ||
| 297 | |||
| 298 | spin_lock_irqsave(&bfin_wdt_spinlock, flags); | ||
| 299 | |||
| 300 | if (options & WDIOS_DISABLECARD) { | ||
| 301 | bfin_wdt_stop(); | ||
| 302 | ret = 0; | ||
| 303 | } | ||
| 304 | |||
| 305 | if (options & WDIOS_ENABLECARD) { | ||
| 306 | bfin_wdt_start(); | ||
| 307 | ret = 0; | ||
| 308 | } | ||
| 309 | |||
| 310 | spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); | ||
| 311 | |||
| 312 | return ret; | ||
| 313 | } | 283 | } |
| 284 | spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); | ||
| 285 | return ret; | ||
| 286 | } | ||
| 287 | case WDIOC_KEEPALIVE: | ||
| 288 | bfin_wdt_keepalive(); | ||
| 289 | return 0; | ||
| 290 | case WDIOC_SETTIMEOUT: { | ||
| 291 | int new_timeout; | ||
| 292 | |||
| 293 | if (get_user(new_timeout, p)) | ||
| 294 | return -EFAULT; | ||
| 295 | if (bfin_wdt_set_timeout(new_timeout)) | ||
| 296 | return -EINVAL; | ||
| 297 | } | ||
| 298 | /* Fall */ | ||
| 299 | case WDIOC_GETTIMEOUT: | ||
| 300 | return put_user(timeout, p); | ||
| 301 | default: | ||
| 302 | return -ENOTTY; | ||
| 314 | } | 303 | } |
| 315 | } | 304 | } |
| 316 | 305 | ||
| @@ -323,8 +312,8 @@ static int bfin_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 323 | * Handles specific events, such as turning off the watchdog during a | 312 | * Handles specific events, such as turning off the watchdog during a |
| 324 | * shutdown event. | 313 | * shutdown event. |
| 325 | */ | 314 | */ |
| 326 | static int bfin_wdt_notify_sys(struct notifier_block *this, unsigned long code, | 315 | static int bfin_wdt_notify_sys(struct notifier_block *this, |
| 327 | void *unused) | 316 | unsigned long code, void *unused) |
| 328 | { | 317 | { |
| 329 | stampit(); | 318 | stampit(); |
| 330 | 319 | ||
| @@ -379,12 +368,12 @@ static int bfin_wdt_resume(struct platform_device *pdev) | |||
| 379 | #endif | 368 | #endif |
| 380 | 369 | ||
| 381 | static const struct file_operations bfin_wdt_fops = { | 370 | static const struct file_operations bfin_wdt_fops = { |
| 382 | .owner = THIS_MODULE, | 371 | .owner = THIS_MODULE, |
| 383 | .llseek = no_llseek, | 372 | .llseek = no_llseek, |
| 384 | .write = bfin_wdt_write, | 373 | .write = bfin_wdt_write, |
| 385 | .ioctl = bfin_wdt_ioctl, | 374 | .unlocked_ioctl = bfin_wdt_ioctl, |
| 386 | .open = bfin_wdt_open, | 375 | .open = bfin_wdt_open, |
| 387 | .release = bfin_wdt_release, | 376 | .release = bfin_wdt_release, |
| 388 | }; | 377 | }; |
| 389 | 378 | ||
| 390 | static struct miscdevice bfin_wdt_miscdev = { | 379 | static struct miscdevice bfin_wdt_miscdev = { |
| @@ -396,8 +385,8 @@ static struct miscdevice bfin_wdt_miscdev = { | |||
| 396 | static struct watchdog_info bfin_wdt_info = { | 385 | static struct watchdog_info bfin_wdt_info = { |
| 397 | .identity = "Blackfin Watchdog", | 386 | .identity = "Blackfin Watchdog", |
| 398 | .options = WDIOF_SETTIMEOUT | | 387 | .options = WDIOF_SETTIMEOUT | |
| 399 | WDIOF_KEEPALIVEPING | | 388 | WDIOF_KEEPALIVEPING | |
| 400 | WDIOF_MAGICCLOSE, | 389 | WDIOF_MAGICCLOSE, |
| 401 | }; | 390 | }; |
| 402 | 391 | ||
| 403 | static struct notifier_block bfin_wdt_notifier = { | 392 | static struct notifier_block bfin_wdt_notifier = { |
| @@ -416,14 +405,16 @@ static int __devinit bfin_wdt_probe(struct platform_device *pdev) | |||
| 416 | 405 | ||
| 417 | ret = register_reboot_notifier(&bfin_wdt_notifier); | 406 | ret = register_reboot_notifier(&bfin_wdt_notifier); |
| 418 | if (ret) { | 407 | if (ret) { |
| 419 | pr_devinit(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", ret); | 408 | pr_devinit(KERN_ERR PFX |
| 409 | "cannot register reboot notifier (err=%d)\n", ret); | ||
| 420 | return ret; | 410 | return ret; |
| 421 | } | 411 | } |
| 422 | 412 | ||
| 423 | ret = misc_register(&bfin_wdt_miscdev); | 413 | ret = misc_register(&bfin_wdt_miscdev); |
| 424 | if (ret) { | 414 | if (ret) { |
| 425 | pr_devinit(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 415 | pr_devinit(KERN_ERR PFX |
| 426 | WATCHDOG_MINOR, ret); | 416 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 417 | WATCHDOG_MINOR, ret); | ||
| 427 | unregister_reboot_notifier(&bfin_wdt_notifier); | 418 | unregister_reboot_notifier(&bfin_wdt_notifier); |
| 428 | return ret; | 419 | return ret; |
| 429 | } | 420 | } |
| @@ -516,7 +507,11 @@ MODULE_LICENSE("GPL"); | |||
| 516 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | 507 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
| 517 | 508 | ||
| 518 | module_param(timeout, uint, 0); | 509 | module_param(timeout, uint, 0); |
| 519 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 510 | MODULE_PARM_DESC(timeout, |
| 511 | "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=" | ||
| 512 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 520 | 513 | ||
| 521 | module_param(nowayout, int, 0); | 514 | module_param(nowayout, int, 0); |
| 522 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 515 | MODULE_PARM_DESC(nowayout, |
| 516 | "Watchdog cannot be stopped once started (default=" | ||
| 517 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index 770824458d45..c3b78a76f173 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c | |||
| @@ -18,9 +18,9 @@ | |||
| 18 | #include <linux/miscdevice.h> | 18 | #include <linux/miscdevice.h> |
| 19 | #include <linux/notifier.h> | 19 | #include <linux/notifier.h> |
| 20 | #include <linux/watchdog.h> | 20 | #include <linux/watchdog.h> |
| 21 | #include <linux/uaccess.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/reg_booke.h> | 23 | #include <asm/reg_booke.h> |
| 23 | #include <asm/uaccess.h> | ||
| 24 | #include <asm/system.h> | 24 | #include <asm/system.h> |
| 25 | 25 | ||
| 26 | /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. | 26 | /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. |
| @@ -32,7 +32,7 @@ | |||
| 32 | */ | 32 | */ |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_FSL_BOOKE | 34 | #ifdef CONFIG_FSL_BOOKE |
| 35 | #define WDT_PERIOD_DEFAULT 63 /* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */ | 35 | #define WDT_PERIOD_DEFAULT 63 /* Ex. wdt_period=28 bus=333Mhz,reset=~40sec */ |
| 36 | #else | 36 | #else |
| 37 | #define WDT_PERIOD_DEFAULT 3 /* Refer to the PPC40x and PPC4xx manuals */ | 37 | #define WDT_PERIOD_DEFAULT 3 /* Refer to the PPC40x and PPC4xx manuals */ |
| 38 | #endif /* for timing information */ | 38 | #endif /* for timing information */ |
| @@ -82,16 +82,15 @@ static struct watchdog_info ident = { | |||
| 82 | .identity = "PowerPC Book-E Watchdog", | 82 | .identity = "PowerPC Book-E Watchdog", |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | static int booke_wdt_ioctl(struct inode *inode, struct file *file, | 85 | static long booke_wdt_ioctl(struct file *file, |
| 86 | unsigned int cmd, unsigned long arg) | 86 | unsigned int cmd, unsigned long arg) |
| 87 | { | 87 | { |
| 88 | u32 tmp = 0; | 88 | u32 tmp = 0; |
| 89 | u32 __user *p = (u32 __user *)arg; | 89 | u32 __user *p = (u32 __user *)arg; |
| 90 | 90 | ||
| 91 | switch (cmd) { | 91 | switch (cmd) { |
| 92 | case WDIOC_GETSUPPORT: | 92 | case WDIOC_GETSUPPORT: |
| 93 | if (copy_to_user((struct watchdog_info __user *)arg, &ident, | 93 | if (copy_to_user(arg, &ident, sizeof(struct watchdog_info))) |
| 94 | sizeof(struct watchdog_info))) | ||
| 95 | return -EFAULT; | 94 | return -EFAULT; |
| 96 | case WDIOC_GETSTATUS: | 95 | case WDIOC_GETSTATUS: |
| 97 | return put_user(ident.options, p); | 96 | return put_user(ident.options, p); |
| @@ -100,16 +99,6 @@ static int booke_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 100 | tmp = mfspr(SPRN_TSR) & TSR_WRS(3); | 99 | tmp = mfspr(SPRN_TSR) & TSR_WRS(3); |
| 101 | /* returns 1 if last reset was caused by the WDT */ | 100 | /* returns 1 if last reset was caused by the WDT */ |
| 102 | return (tmp ? 1 : 0); | 101 | return (tmp ? 1 : 0); |
| 103 | case WDIOC_KEEPALIVE: | ||
| 104 | booke_wdt_ping(); | ||
| 105 | return 0; | ||
| 106 | case WDIOC_SETTIMEOUT: | ||
| 107 | if (get_user(booke_wdt_period, p)) | ||
| 108 | return -EFAULT; | ||
| 109 | mtspr(SPRN_TCR, (mfspr(SPRN_TCR)&~WDTP(0))|WDTP(booke_wdt_period)); | ||
| 110 | return 0; | ||
| 111 | case WDIOC_GETTIMEOUT: | ||
| 112 | return put_user(booke_wdt_period, p); | ||
| 113 | case WDIOC_SETOPTIONS: | 102 | case WDIOC_SETOPTIONS: |
| 114 | if (get_user(tmp, p)) | 103 | if (get_user(tmp, p)) |
| 115 | return -EINVAL; | 104 | return -EINVAL; |
| @@ -119,6 +108,17 @@ static int booke_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 119 | } else | 108 | } else |
| 120 | return -EINVAL; | 109 | return -EINVAL; |
| 121 | return 0; | 110 | return 0; |
| 111 | case WDIOC_KEEPALIVE: | ||
| 112 | booke_wdt_ping(); | ||
| 113 | return 0; | ||
| 114 | case WDIOC_SETTIMEOUT: | ||
| 115 | if (get_user(booke_wdt_period, p)) | ||
| 116 | return -EFAULT; | ||
| 117 | mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WDTP(0)) | | ||
| 118 | WDTP(booke_wdt_period)); | ||
| 119 | return 0; | ||
| 120 | case WDIOC_GETTIMEOUT: | ||
| 121 | return put_user(booke_wdt_period, p); | ||
| 122 | default: | 122 | default: |
| 123 | return -ENOTTY; | 123 | return -ENOTTY; |
| 124 | } | 124 | } |
| @@ -132,8 +132,9 @@ static int booke_wdt_open(struct inode *inode, struct file *file) | |||
| 132 | if (booke_wdt_enabled == 0) { | 132 | if (booke_wdt_enabled == 0) { |
| 133 | booke_wdt_enabled = 1; | 133 | booke_wdt_enabled = 1; |
| 134 | on_each_cpu(__booke_wdt_enable, NULL, 0); | 134 | on_each_cpu(__booke_wdt_enable, NULL, 0); |
| 135 | printk(KERN_INFO "PowerPC Book-E Watchdog Timer Enabled " | 135 | printk(KERN_INFO |
| 136 | "(wdt_period=%d)\n", booke_wdt_period); | 136 | "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n", |
| 137 | booke_wdt_period); | ||
| 137 | } | 138 | } |
| 138 | spin_unlock(&booke_wdt_lock); | 139 | spin_unlock(&booke_wdt_lock); |
| 139 | 140 | ||
| @@ -144,7 +145,7 @@ static const struct file_operations booke_wdt_fops = { | |||
| 144 | .owner = THIS_MODULE, | 145 | .owner = THIS_MODULE, |
| 145 | .llseek = no_llseek, | 146 | .llseek = no_llseek, |
| 146 | .write = booke_wdt_write, | 147 | .write = booke_wdt_write, |
| 147 | .ioctl = booke_wdt_ioctl, | 148 | .unlocked_ioctl = booke_wdt_ioctl, |
| 148 | .open = booke_wdt_open, | 149 | .open = booke_wdt_open, |
| 149 | }; | 150 | }; |
| 150 | 151 | ||
| @@ -175,8 +176,9 @@ static int __init booke_wdt_init(void) | |||
| 175 | 176 | ||
| 176 | spin_lock(&booke_wdt_lock); | 177 | spin_lock(&booke_wdt_lock); |
| 177 | if (booke_wdt_enabled == 1) { | 178 | if (booke_wdt_enabled == 1) { |
| 178 | printk(KERN_INFO "PowerPC Book-E Watchdog Timer Enabled " | 179 | printk(KERN_INFO |
| 179 | "(wdt_period=%d)\n", booke_wdt_period); | 180 | "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n", |
| 181 | booke_wdt_period); | ||
| 180 | on_each_cpu(__booke_wdt_enable, NULL, 0); | 182 | on_each_cpu(__booke_wdt_enable, NULL, 0); |
| 181 | } | 183 | } |
| 182 | spin_unlock(&booke_wdt_lock); | 184 | spin_unlock(&booke_wdt_lock); |
diff --git a/drivers/watchdog/cpu5wdt.c b/drivers/watchdog/cpu5wdt.c index df72f90123df..71f6d7eec9a8 100644 --- a/drivers/watchdog/cpu5wdt.c +++ b/drivers/watchdog/cpu5wdt.c | |||
| @@ -30,16 +30,16 @@ | |||
| 30 | #include <linux/timer.h> | 30 | #include <linux/timer.h> |
| 31 | #include <linux/completion.h> | 31 | #include <linux/completion.h> |
| 32 | #include <linux/jiffies.h> | 32 | #include <linux/jiffies.h> |
| 33 | #include <asm/io.h> | 33 | #include <linux/io.h> |
| 34 | #include <asm/uaccess.h> | 34 | #include <linux/uaccess.h> |
| 35 | |||
| 36 | #include <linux/watchdog.h> | 35 | #include <linux/watchdog.h> |
| 37 | 36 | ||
| 38 | /* adjustable parameters */ | 37 | /* adjustable parameters */ |
| 39 | 38 | ||
| 40 | static int verbose = 0; | 39 | static int verbose; |
| 41 | static int port = 0x91; | 40 | static int port = 0x91; |
| 42 | static int ticks = 10000; | 41 | static int ticks = 10000; |
| 42 | static spinlock_t cpu5wdt_lock; | ||
| 43 | 43 | ||
| 44 | #define PFX "cpu5wdt: " | 44 | #define PFX "cpu5wdt: " |
| 45 | 45 | ||
| @@ -70,12 +70,13 @@ static struct { | |||
| 70 | 70 | ||
| 71 | static void cpu5wdt_trigger(unsigned long unused) | 71 | static void cpu5wdt_trigger(unsigned long unused) |
| 72 | { | 72 | { |
| 73 | if ( verbose > 2 ) | 73 | if (verbose > 2) |
| 74 | printk(KERN_DEBUG PFX "trigger at %i ticks\n", ticks); | 74 | printk(KERN_DEBUG PFX "trigger at %i ticks\n", ticks); |
| 75 | 75 | ||
| 76 | if( cpu5wdt_device.running ) | 76 | if (cpu5wdt_device.running) |
| 77 | ticks--; | 77 | ticks--; |
| 78 | 78 | ||
| 79 | spin_lock(&cpu5wdt_lock); | ||
| 79 | /* keep watchdog alive */ | 80 | /* keep watchdog alive */ |
| 80 | outb(1, port + CPU5WDT_TRIGGER_REG); | 81 | outb(1, port + CPU5WDT_TRIGGER_REG); |
| 81 | 82 | ||
| @@ -86,6 +87,7 @@ static void cpu5wdt_trigger(unsigned long unused) | |||
| 86 | /* ticks doesn't matter anyway */ | 87 | /* ticks doesn't matter anyway */ |
| 87 | complete(&cpu5wdt_device.stop); | 88 | complete(&cpu5wdt_device.stop); |
| 88 | } | 89 | } |
| 90 | spin_unlock(&cpu5wdt_lock); | ||
| 89 | 91 | ||
| 90 | } | 92 | } |
| 91 | 93 | ||
| @@ -93,14 +95,17 @@ static void cpu5wdt_reset(void) | |||
| 93 | { | 95 | { |
| 94 | ticks = cpu5wdt_device.default_ticks; | 96 | ticks = cpu5wdt_device.default_ticks; |
| 95 | 97 | ||
| 96 | if ( verbose ) | 98 | if (verbose) |
| 97 | printk(KERN_DEBUG PFX "reset (%i ticks)\n", (int) ticks); | 99 | printk(KERN_DEBUG PFX "reset (%i ticks)\n", (int) ticks); |
| 98 | 100 | ||
| 99 | } | 101 | } |
| 100 | 102 | ||
| 101 | static void cpu5wdt_start(void) | 103 | static void cpu5wdt_start(void) |
| 102 | { | 104 | { |
| 103 | if ( !cpu5wdt_device.queue ) { | 105 | unsigned long flags; |
| 106 | |||
| 107 | spin_lock_irqsave(&cpu5wdt_lock, flags); | ||
| 108 | if (!cpu5wdt_device.queue) { | ||
| 104 | cpu5wdt_device.queue = 1; | 109 | cpu5wdt_device.queue = 1; |
| 105 | outb(0, port + CPU5WDT_TIME_A_REG); | 110 | outb(0, port + CPU5WDT_TIME_A_REG); |
| 106 | outb(0, port + CPU5WDT_TIME_B_REG); | 111 | outb(0, port + CPU5WDT_TIME_B_REG); |
| @@ -111,18 +116,20 @@ static void cpu5wdt_start(void) | |||
| 111 | } | 116 | } |
| 112 | /* if process dies, counter is not decremented */ | 117 | /* if process dies, counter is not decremented */ |
| 113 | cpu5wdt_device.running++; | 118 | cpu5wdt_device.running++; |
| 119 | spin_unlock_irqrestore(&cpu5wdt_lock, flags); | ||
| 114 | } | 120 | } |
| 115 | 121 | ||
| 116 | static int cpu5wdt_stop(void) | 122 | static int cpu5wdt_stop(void) |
| 117 | { | 123 | { |
| 118 | if ( cpu5wdt_device.running ) | 124 | unsigned long flags; |
| 119 | cpu5wdt_device.running = 0; | ||
| 120 | 125 | ||
| 126 | spin_lock_irqsave(&cpu5wdt_lock, flags); | ||
| 127 | if (cpu5wdt_device.running) | ||
| 128 | cpu5wdt_device.running = 0; | ||
| 121 | ticks = cpu5wdt_device.default_ticks; | 129 | ticks = cpu5wdt_device.default_ticks; |
| 122 | 130 | spin_unlock_irqrestore(&cpu5wdt_lock, flags); | |
| 123 | if ( verbose ) | 131 | if (verbose) |
| 124 | printk(KERN_CRIT PFX "stop not possible\n"); | 132 | printk(KERN_CRIT PFX "stop not possible\n"); |
| 125 | |||
| 126 | return -EIO; | 133 | return -EIO; |
| 127 | } | 134 | } |
| 128 | 135 | ||
| @@ -130,9 +137,8 @@ static int cpu5wdt_stop(void) | |||
| 130 | 137 | ||
| 131 | static int cpu5wdt_open(struct inode *inode, struct file *file) | 138 | static int cpu5wdt_open(struct inode *inode, struct file *file) |
| 132 | { | 139 | { |
| 133 | if ( test_and_set_bit(0, &cpu5wdt_device.inuse) ) | 140 | if (test_and_set_bit(0, &cpu5wdt_device.inuse)) |
| 134 | return -EBUSY; | 141 | return -EBUSY; |
| 135 | |||
| 136 | return nonseekable_open(inode, file); | 142 | return nonseekable_open(inode, file); |
| 137 | } | 143 | } |
| 138 | 144 | ||
| @@ -142,67 +148,58 @@ static int cpu5wdt_release(struct inode *inode, struct file *file) | |||
| 142 | return 0; | 148 | return 0; |
| 143 | } | 149 | } |
| 144 | 150 | ||
| 145 | static int cpu5wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | 151 | static long cpu5wdt_ioctl(struct file *file, unsigned int cmd, |
| 152 | unsigned long arg) | ||
| 146 | { | 153 | { |
| 147 | void __user *argp = (void __user *)arg; | 154 | void __user *argp = (void __user *)arg; |
| 155 | int __user *p = argp; | ||
| 148 | unsigned int value; | 156 | unsigned int value; |
| 149 | static struct watchdog_info ident = | 157 | static struct watchdog_info ident = { |
| 150 | { | ||
| 151 | .options = WDIOF_CARDRESET, | 158 | .options = WDIOF_CARDRESET, |
| 152 | .identity = "CPU5 WDT", | 159 | .identity = "CPU5 WDT", |
| 153 | }; | 160 | }; |
| 154 | 161 | ||
| 155 | switch(cmd) { | 162 | switch (cmd) { |
| 156 | case WDIOC_KEEPALIVE: | 163 | case WDIOC_GETSUPPORT: |
| 157 | cpu5wdt_reset(); | 164 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 158 | break; | 165 | return -EFAULT; |
| 159 | case WDIOC_GETSTATUS: | 166 | break; |
| 160 | value = inb(port + CPU5WDT_STATUS_REG); | 167 | case WDIOC_GETSTATUS: |
| 161 | value = (value >> 2) & 1; | 168 | value = inb(port + CPU5WDT_STATUS_REG); |
| 162 | if ( copy_to_user(argp, &value, sizeof(int)) ) | 169 | value = (value >> 2) & 1; |
| 163 | return -EFAULT; | 170 | return put_user(value, p); |
| 164 | break; | 171 | case WDIOC_GETBOOTSTATUS: |
| 165 | case WDIOC_GETBOOTSTATUS: | 172 | return put_user(0, p); |
| 166 | if ( copy_to_user(argp, &value, sizeof(int)) ) | 173 | case WDIOC_SETOPTIONS: |
| 167 | return -EFAULT; | 174 | if (get_user(value, p)) |
| 168 | break; | 175 | return -EFAULT; |
| 169 | case WDIOC_GETSUPPORT: | 176 | if (value & WDIOS_ENABLECARD) |
| 170 | if ( copy_to_user(argp, &ident, sizeof(ident)) ) | 177 | cpu5wdt_start(); |
| 171 | return -EFAULT; | 178 | if (value & WDIOS_DISABLECARD) |
| 172 | break; | 179 | cpu5wdt_stop(); |
| 173 | case WDIOC_SETOPTIONS: | 180 | break; |
| 174 | if ( copy_from_user(&value, argp, sizeof(int)) ) | 181 | case WDIOC_KEEPALIVE: |
| 175 | return -EFAULT; | 182 | cpu5wdt_reset(); |
| 176 | switch(value) { | 183 | break; |
| 177 | case WDIOS_ENABLECARD: | 184 | default: |
| 178 | cpu5wdt_start(); | 185 | return -ENOTTY; |
| 179 | break; | ||
| 180 | case WDIOS_DISABLECARD: | ||
| 181 | return cpu5wdt_stop(); | ||
| 182 | default: | ||
| 183 | return -EINVAL; | ||
| 184 | } | ||
| 185 | break; | ||
| 186 | default: | ||
| 187 | return -ENOTTY; | ||
| 188 | } | 186 | } |
| 189 | return 0; | 187 | return 0; |
| 190 | } | 188 | } |
| 191 | 189 | ||
| 192 | static ssize_t cpu5wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | 190 | static ssize_t cpu5wdt_write(struct file *file, const char __user *buf, |
| 191 | size_t count, loff_t *ppos) | ||
| 193 | { | 192 | { |
| 194 | if ( !count ) | 193 | if (!count) |
| 195 | return -EIO; | 194 | return -EIO; |
| 196 | |||
| 197 | cpu5wdt_reset(); | 195 | cpu5wdt_reset(); |
| 198 | |||
| 199 | return count; | 196 | return count; |
| 200 | } | 197 | } |
| 201 | 198 | ||
| 202 | static const struct file_operations cpu5wdt_fops = { | 199 | static const struct file_operations cpu5wdt_fops = { |
| 203 | .owner = THIS_MODULE, | 200 | .owner = THIS_MODULE, |
| 204 | .llseek = no_llseek, | 201 | .llseek = no_llseek, |
| 205 | .ioctl = cpu5wdt_ioctl, | 202 | .unlocked_ioctl = cpu5wdt_ioctl, |
| 206 | .open = cpu5wdt_open, | 203 | .open = cpu5wdt_open, |
| 207 | .write = cpu5wdt_write, | 204 | .write = cpu5wdt_write, |
| 208 | .release = cpu5wdt_release, | 205 | .release = cpu5wdt_release, |
| @@ -221,37 +218,36 @@ static int __devinit cpu5wdt_init(void) | |||
| 221 | unsigned int val; | 218 | unsigned int val; |
| 222 | int err; | 219 | int err; |
| 223 | 220 | ||
| 224 | if ( verbose ) | 221 | if (verbose) |
| 225 | printk(KERN_DEBUG PFX "port=0x%x, verbose=%i\n", port, verbose); | 222 | printk(KERN_DEBUG PFX |
| 223 | "port=0x%x, verbose=%i\n", port, verbose); | ||
| 226 | 224 | ||
| 227 | if ( !request_region(port, CPU5WDT_EXTENT, PFX) ) { | 225 | init_completion(&cpu5wdt_device.stop); |
| 226 | spin_lock_init(&cpu5wdt_lock); | ||
| 227 | cpu5wdt_device.queue = 0; | ||
| 228 | setup_timer(&cpu5wdt_device.timer, cpu5wdt_trigger, 0); | ||
| 229 | cpu5wdt_device.default_ticks = ticks; | ||
| 230 | |||
| 231 | if (!request_region(port, CPU5WDT_EXTENT, PFX)) { | ||
| 228 | printk(KERN_ERR PFX "request_region failed\n"); | 232 | printk(KERN_ERR PFX "request_region failed\n"); |
| 229 | err = -EBUSY; | 233 | err = -EBUSY; |
| 230 | goto no_port; | 234 | goto no_port; |
| 231 | } | 235 | } |
| 232 | 236 | ||
| 233 | if ( (err = misc_register(&cpu5wdt_misc)) < 0 ) { | ||
| 234 | printk(KERN_ERR PFX "misc_register failed\n"); | ||
| 235 | goto no_misc; | ||
| 236 | } | ||
| 237 | |||
| 238 | /* watchdog reboot? */ | 237 | /* watchdog reboot? */ |
| 239 | val = inb(port + CPU5WDT_STATUS_REG); | 238 | val = inb(port + CPU5WDT_STATUS_REG); |
| 240 | val = (val >> 2) & 1; | 239 | val = (val >> 2) & 1; |
| 241 | if ( !val ) | 240 | if (!val) |
| 242 | printk(KERN_INFO PFX "sorry, was my fault\n"); | 241 | printk(KERN_INFO PFX "sorry, was my fault\n"); |
| 243 | 242 | ||
| 244 | init_completion(&cpu5wdt_device.stop); | 243 | err = misc_register(&cpu5wdt_misc); |
| 245 | cpu5wdt_device.queue = 0; | 244 | if (err < 0) { |
| 246 | 245 | printk(KERN_ERR PFX "misc_register failed\n"); | |
| 247 | clear_bit(0, &cpu5wdt_device.inuse); | 246 | goto no_misc; |
| 248 | 247 | } | |
| 249 | setup_timer(&cpu5wdt_device.timer, cpu5wdt_trigger, 0); | ||
| 250 | 248 | ||
| 251 | cpu5wdt_device.default_ticks = ticks; | ||
| 252 | 249 | ||
| 253 | printk(KERN_INFO PFX "init success\n"); | 250 | printk(KERN_INFO PFX "init success\n"); |
| 254 | |||
| 255 | return 0; | 251 | return 0; |
| 256 | 252 | ||
| 257 | no_misc: | 253 | no_misc: |
| @@ -267,7 +263,7 @@ static int __devinit cpu5wdt_init_module(void) | |||
| 267 | 263 | ||
| 268 | static void __devexit cpu5wdt_exit(void) | 264 | static void __devexit cpu5wdt_exit(void) |
| 269 | { | 265 | { |
| 270 | if ( cpu5wdt_device.queue ) { | 266 | if (cpu5wdt_device.queue) { |
| 271 | cpu5wdt_device.queue = 0; | 267 | cpu5wdt_device.queue = 0; |
| 272 | wait_for_completion(&cpu5wdt_device.stop); | 268 | wait_for_completion(&cpu5wdt_device.stop); |
| 273 | } | 269 | } |
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 003dffe5cb19..2e1360286732 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c | |||
| @@ -22,10 +22,9 @@ | |||
| 22 | #include <linux/bitops.h> | 22 | #include <linux/bitops.h> |
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/spinlock.h> | 24 | #include <linux/spinlock.h> |
| 25 | 25 | #include <linux/uaccess.h> | |
| 26 | #include <linux/io.h> | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <asm/uaccess.h> | ||
| 28 | #include <asm/io.h> | ||
| 29 | 28 | ||
| 30 | #define MODULE_NAME "DAVINCI-WDT: " | 29 | #define MODULE_NAME "DAVINCI-WDT: " |
| 31 | 30 | ||
| @@ -143,9 +142,8 @@ static struct watchdog_info ident = { | |||
| 143 | .identity = "DaVinci Watchdog", | 142 | .identity = "DaVinci Watchdog", |
| 144 | }; | 143 | }; |
| 145 | 144 | ||
| 146 | static int | 145 | static long davinci_wdt_ioctl(struct file *file, |
| 147 | davinci_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 146 | unsigned int cmd, unsigned long arg) |
| 148 | unsigned long arg) | ||
| 149 | { | 147 | { |
| 150 | int ret = -ENOTTY; | 148 | int ret = -ENOTTY; |
| 151 | 149 | ||
| @@ -160,14 +158,14 @@ davinci_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 160 | ret = put_user(0, (int *)arg); | 158 | ret = put_user(0, (int *)arg); |
| 161 | break; | 159 | break; |
| 162 | 160 | ||
| 163 | case WDIOC_GETTIMEOUT: | ||
| 164 | ret = put_user(heartbeat, (int *)arg); | ||
| 165 | break; | ||
| 166 | |||
| 167 | case WDIOC_KEEPALIVE: | 161 | case WDIOC_KEEPALIVE: |
| 168 | wdt_service(); | 162 | wdt_service(); |
| 169 | ret = 0; | 163 | ret = 0; |
| 170 | break; | 164 | break; |
| 165 | |||
| 166 | case WDIOC_GETTIMEOUT: | ||
| 167 | ret = put_user(heartbeat, (int *)arg); | ||
| 168 | break; | ||
| 171 | } | 169 | } |
| 172 | return ret; | 170 | return ret; |
| 173 | } | 171 | } |
| @@ -184,7 +182,7 @@ static const struct file_operations davinci_wdt_fops = { | |||
| 184 | .owner = THIS_MODULE, | 182 | .owner = THIS_MODULE, |
| 185 | .llseek = no_llseek, | 183 | .llseek = no_llseek, |
| 186 | .write = davinci_wdt_write, | 184 | .write = davinci_wdt_write, |
| 187 | .ioctl = davinci_wdt_ioctl, | 185 | .unlocked_ioctl = davinci_wdt_ioctl, |
| 188 | .open = davinci_wdt_open, | 186 | .open = davinci_wdt_open, |
| 189 | .release = davinci_wdt_release, | 187 | .release = davinci_wdt_release, |
| 190 | }; | 188 | }; |
diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index af8ef14c0e4c..e9f950ff86ea 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c | |||
| @@ -28,9 +28,8 @@ | |||
| 28 | #include <linux/miscdevice.h> | 28 | #include <linux/miscdevice.h> |
| 29 | #include <linux/watchdog.h> | 29 | #include <linux/watchdog.h> |
| 30 | #include <linux/timer.h> | 30 | #include <linux/timer.h> |
| 31 | 31 | #include <linux/uaccess.h> | |
| 32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 33 | #include <asm/uaccess.h> | ||
| 34 | 33 | ||
| 35 | #define WDT_VERSION "0.3" | 34 | #define WDT_VERSION "0.3" |
| 36 | #define PFX "ep93xx_wdt: " | 35 | #define PFX "ep93xx_wdt: " |
| @@ -136,9 +135,8 @@ static struct watchdog_info ident = { | |||
| 136 | .identity = "EP93xx Watchdog", | 135 | .identity = "EP93xx Watchdog", |
| 137 | }; | 136 | }; |
| 138 | 137 | ||
| 139 | static int | 138 | static long ep93xx_wdt_ioctl(struct file *file, |
| 140 | ep93xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 139 | unsigned int cmd, unsigned long arg) |
| 141 | unsigned long arg) | ||
| 142 | { | 140 | { |
| 143 | int ret = -ENOTTY; | 141 | int ret = -ENOTTY; |
| 144 | 142 | ||
| @@ -156,15 +154,15 @@ ep93xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 156 | ret = put_user(boot_status, (int __user *)arg); | 154 | ret = put_user(boot_status, (int __user *)arg); |
| 157 | break; | 155 | break; |
| 158 | 156 | ||
| 159 | case WDIOC_GETTIMEOUT: | ||
| 160 | /* actually, it is 0.250 seconds.... */ | ||
| 161 | ret = put_user(1, (int __user *)arg); | ||
| 162 | break; | ||
| 163 | |||
| 164 | case WDIOC_KEEPALIVE: | 157 | case WDIOC_KEEPALIVE: |
| 165 | wdt_keepalive(); | 158 | wdt_keepalive(); |
| 166 | ret = 0; | 159 | ret = 0; |
| 167 | break; | 160 | break; |
| 161 | |||
| 162 | case WDIOC_GETTIMEOUT: | ||
| 163 | /* actually, it is 0.250 seconds.... */ | ||
| 164 | ret = put_user(1, (int __user *)arg); | ||
| 165 | break; | ||
| 168 | } | 166 | } |
| 169 | return ret; | 167 | return ret; |
| 170 | } | 168 | } |
| @@ -174,8 +172,8 @@ static int ep93xx_wdt_release(struct inode *inode, struct file *file) | |||
| 174 | if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) | 172 | if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) |
| 175 | wdt_shutdown(); | 173 | wdt_shutdown(); |
| 176 | else | 174 | else |
| 177 | printk(KERN_CRIT PFX "Device closed unexpectedly - " | 175 | printk(KERN_CRIT PFX |
| 178 | "timer will not stop\n"); | 176 | "Device closed unexpectedly - timer will not stop\n"); |
| 179 | 177 | ||
| 180 | clear_bit(WDT_IN_USE, &wdt_status); | 178 | clear_bit(WDT_IN_USE, &wdt_status); |
| 181 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 179 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| @@ -186,7 +184,7 @@ static int ep93xx_wdt_release(struct inode *inode, struct file *file) | |||
| 186 | static const struct file_operations ep93xx_wdt_fops = { | 184 | static const struct file_operations ep93xx_wdt_fops = { |
| 187 | .owner = THIS_MODULE, | 185 | .owner = THIS_MODULE, |
| 188 | .write = ep93xx_wdt_write, | 186 | .write = ep93xx_wdt_write, |
| 189 | .ioctl = ep93xx_wdt_ioctl, | 187 | .unlocked_ioctl = ep93xx_wdt_ioctl, |
| 190 | .open = ep93xx_wdt_open, | 188 | .open = ep93xx_wdt_open, |
| 191 | .release = ep93xx_wdt_release, | 189 | .release = ep93xx_wdt_release, |
| 192 | }; | 190 | }; |
| @@ -243,7 +241,9 @@ module_param(nowayout, int, 0); | |||
| 243 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); | 241 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); |
| 244 | 242 | ||
| 245 | module_param(timeout, int, 0); | 243 | module_param(timeout, int, 0); |
| 246 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 244 | MODULE_PARM_DESC(timeout, |
| 245 | "Watchdog timeout in seconds. (1<=timeout<=3600, default=" | ||
| 246 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 247 | 247 | ||
| 248 | MODULE_AUTHOR("Ray Lehtiniemi <rayl@mail.com>," | 248 | MODULE_AUTHOR("Ray Lehtiniemi <rayl@mail.com>," |
| 249 | "Alessandro Zummo <a.zummo@towertech.it>"); | 249 | "Alessandro Zummo <a.zummo@towertech.it>"); |
diff --git a/drivers/watchdog/eurotechwdt.c b/drivers/watchdog/eurotechwdt.c index b14e9d1f164d..bbd14e34319f 100644 --- a/drivers/watchdog/eurotechwdt.c +++ b/drivers/watchdog/eurotechwdt.c | |||
| @@ -56,14 +56,15 @@ | |||
| 56 | #include <linux/notifier.h> | 56 | #include <linux/notifier.h> |
| 57 | #include <linux/reboot.h> | 57 | #include <linux/reboot.h> |
| 58 | #include <linux/init.h> | 58 | #include <linux/init.h> |
| 59 | #include <linux/io.h> | ||
| 60 | #include <linux/uaccess.h> | ||
| 59 | 61 | ||
| 60 | #include <asm/io.h> | ||
| 61 | #include <asm/uaccess.h> | ||
| 62 | #include <asm/system.h> | 62 | #include <asm/system.h> |
| 63 | 63 | ||
| 64 | static unsigned long eurwdt_is_open; | 64 | static unsigned long eurwdt_is_open; |
| 65 | static int eurwdt_timeout; | 65 | static int eurwdt_timeout; |
| 66 | static char eur_expect_close; | 66 | static char eur_expect_close; |
| 67 | static spinlock_t eurwdt_lock; | ||
| 67 | 68 | ||
| 68 | /* | 69 | /* |
| 69 | * You must set these - there is no sane way to probe for this board. | 70 | * You must set these - there is no sane way to probe for this board. |
| @@ -78,7 +79,9 @@ static char *ev = "int"; | |||
| 78 | 79 | ||
| 79 | static int nowayout = WATCHDOG_NOWAYOUT; | 80 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 80 | module_param(nowayout, int, 0); | 81 | module_param(nowayout, int, 0); |
| 81 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 82 | MODULE_PARM_DESC(nowayout, |
| 83 | "Watchdog cannot be stopped once started (default=" | ||
| 84 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 82 | 85 | ||
| 83 | /* | 86 | /* |
| 84 | * Some symbolic names | 87 | * Some symbolic names |
| @@ -137,7 +140,8 @@ static void eurwdt_activate_timer(void) | |||
| 137 | { | 140 | { |
| 138 | eurwdt_disable_timer(); | 141 | eurwdt_disable_timer(); |
| 139 | eurwdt_write_reg(WDT_CTRL_REG, 0x01); /* activate the WDT */ | 142 | eurwdt_write_reg(WDT_CTRL_REG, 0x01); /* activate the WDT */ |
| 140 | eurwdt_write_reg(WDT_OUTPIN_CFG, !strcmp("int", ev) ? WDT_EVENT_INT : WDT_EVENT_REBOOT); | 143 | eurwdt_write_reg(WDT_OUTPIN_CFG, |
| 144 | !strcmp("int", ev) ? WDT_EVENT_INT : WDT_EVENT_REBOOT); | ||
| 141 | 145 | ||
| 142 | /* Setting interrupt line */ | 146 | /* Setting interrupt line */ |
| 143 | if (irq == 2 || irq > 15 || irq < 0) { | 147 | if (irq == 2 || irq > 15 || irq < 0) { |
| @@ -206,21 +210,21 @@ size_t count, loff_t *ppos) | |||
| 206 | 210 | ||
| 207 | for (i = 0; i != count; i++) { | 211 | for (i = 0; i != count; i++) { |
| 208 | char c; | 212 | char c; |
| 209 | if(get_user(c, buf+i)) | 213 | if (get_user(c, buf + i)) |
| 210 | return -EFAULT; | 214 | return -EFAULT; |
| 211 | if (c == 'V') | 215 | if (c == 'V') |
| 212 | eur_expect_close = 42; | 216 | eur_expect_close = 42; |
| 213 | } | 217 | } |
| 214 | } | 218 | } |
| 219 | spin_lock(&eurwdt_lock); | ||
| 215 | eurwdt_ping(); /* the default timeout */ | 220 | eurwdt_ping(); /* the default timeout */ |
| 221 | spin_unlock(&eurwdt_lock); | ||
| 216 | } | 222 | } |
| 217 | |||
| 218 | return count; | 223 | return count; |
| 219 | } | 224 | } |
| 220 | 225 | ||
| 221 | /** | 226 | /** |
| 222 | * eurwdt_ioctl: | 227 | * eurwdt_ioctl: |
| 223 | * @inode: inode of the device | ||
| 224 | * @file: file handle to the device | 228 | * @file: file handle to the device |
| 225 | * @cmd: watchdog command | 229 | * @cmd: watchdog command |
| 226 | * @arg: argument pointer | 230 | * @arg: argument pointer |
| @@ -229,13 +233,14 @@ size_t count, loff_t *ppos) | |||
| 229 | * according to their available features. | 233 | * according to their available features. |
| 230 | */ | 234 | */ |
| 231 | 235 | ||
| 232 | static int eurwdt_ioctl(struct inode *inode, struct file *file, | 236 | static long eurwdt_ioctl(struct file *file, |
| 233 | unsigned int cmd, unsigned long arg) | 237 | unsigned int cmd, unsigned long arg) |
| 234 | { | 238 | { |
| 235 | void __user *argp = (void __user *)arg; | 239 | void __user *argp = (void __user *)arg; |
| 236 | int __user *p = argp; | 240 | int __user *p = argp; |
| 237 | static struct watchdog_info ident = { | 241 | static struct watchdog_info ident = { |
| 238 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 242 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
| 243 | | WDIOF_MAGICCLOSE, | ||
| 239 | .firmware_version = 1, | 244 | .firmware_version = 1, |
| 240 | .identity = "WDT Eurotech CPU-1220/1410", | 245 | .identity = "WDT Eurotech CPU-1220/1410", |
| 241 | }; | 246 | }; |
| @@ -243,10 +248,7 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, | |||
| 243 | int time; | 248 | int time; |
| 244 | int options, retval = -EINVAL; | 249 | int options, retval = -EINVAL; |
| 245 | 250 | ||
| 246 | switch(cmd) { | 251 | switch (cmd) { |
| 247 | default: | ||
| 248 | return -ENOTTY; | ||
| 249 | |||
| 250 | case WDIOC_GETSUPPORT: | 252 | case WDIOC_GETSUPPORT: |
| 251 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | 253 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 252 | 254 | ||
| @@ -254,8 +256,26 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, | |||
| 254 | case WDIOC_GETBOOTSTATUS: | 256 | case WDIOC_GETBOOTSTATUS: |
| 255 | return put_user(0, p); | 257 | return put_user(0, p); |
| 256 | 258 | ||
| 259 | case WDIOC_SETOPTIONS: | ||
| 260 | if (get_user(options, p)) | ||
| 261 | return -EFAULT; | ||
| 262 | spin_lock(&eurwdt_lock); | ||
| 263 | if (options & WDIOS_DISABLECARD) { | ||
| 264 | eurwdt_disable_timer(); | ||
| 265 | retval = 0; | ||
| 266 | } | ||
| 267 | if (options & WDIOS_ENABLECARD) { | ||
| 268 | eurwdt_activate_timer(); | ||
| 269 | eurwdt_ping(); | ||
| 270 | retval = 0; | ||
| 271 | } | ||
| 272 | spin_unlock(&eurwdt_lock); | ||
| 273 | return retval; | ||
| 274 | |||
| 257 | case WDIOC_KEEPALIVE: | 275 | case WDIOC_KEEPALIVE: |
| 276 | spin_lock(&eurwdt_lock); | ||
| 258 | eurwdt_ping(); | 277 | eurwdt_ping(); |
| 278 | spin_unlock(&eurwdt_lock); | ||
| 259 | return 0; | 279 | return 0; |
| 260 | 280 | ||
| 261 | case WDIOC_SETTIMEOUT: | 281 | case WDIOC_SETTIMEOUT: |
| @@ -266,26 +286,17 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, | |||
| 266 | if (time < 0 || time > 255) | 286 | if (time < 0 || time > 255) |
| 267 | return -EINVAL; | 287 | return -EINVAL; |
| 268 | 288 | ||
| 289 | spin_lock(&eurwdt_lock); | ||
| 269 | eurwdt_timeout = time; | 290 | eurwdt_timeout = time; |
| 270 | eurwdt_set_timeout(time); | 291 | eurwdt_set_timeout(time); |
| 292 | spin_unlock(&eurwdt_lock); | ||
| 271 | /* Fall */ | 293 | /* Fall */ |
| 272 | 294 | ||
| 273 | case WDIOC_GETTIMEOUT: | 295 | case WDIOC_GETTIMEOUT: |
| 274 | return put_user(eurwdt_timeout, p); | 296 | return put_user(eurwdt_timeout, p); |
| 275 | 297 | ||
| 276 | case WDIOC_SETOPTIONS: | 298 | default: |
| 277 | if (get_user(options, p)) | 299 | return -ENOTTY; |
| 278 | return -EFAULT; | ||
| 279 | if (options & WDIOS_DISABLECARD) { | ||
| 280 | eurwdt_disable_timer(); | ||
| 281 | retval = 0; | ||
| 282 | } | ||
| 283 | if (options & WDIOS_ENABLECARD) { | ||
| 284 | eurwdt_activate_timer(); | ||
| 285 | eurwdt_ping(); | ||
| 286 | retval = 0; | ||
| 287 | } | ||
| 288 | return retval; | ||
| 289 | } | 300 | } |
| 290 | } | 301 | } |
| 291 | 302 | ||
| @@ -322,10 +333,11 @@ static int eurwdt_open(struct inode *inode, struct file *file) | |||
| 322 | 333 | ||
| 323 | static int eurwdt_release(struct inode *inode, struct file *file) | 334 | static int eurwdt_release(struct inode *inode, struct file *file) |
| 324 | { | 335 | { |
| 325 | if (eur_expect_close == 42) { | 336 | if (eur_expect_close == 42) |
| 326 | eurwdt_disable_timer(); | 337 | eurwdt_disable_timer(); |
| 327 | } else { | 338 | else { |
| 328 | printk(KERN_CRIT "eurwdt: Unexpected close, not stopping watchdog!\n"); | 339 | printk(KERN_CRIT |
| 340 | "eurwdt: Unexpected close, not stopping watchdog!\n"); | ||
| 329 | eurwdt_ping(); | 341 | eurwdt_ping(); |
| 330 | } | 342 | } |
| 331 | clear_bit(0, &eurwdt_is_open); | 343 | clear_bit(0, &eurwdt_is_open); |
| @@ -348,10 +360,8 @@ static int eurwdt_release(struct inode *inode, struct file *file) | |||
| 348 | static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code, | 360 | static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 349 | void *unused) | 361 | void *unused) |
| 350 | { | 362 | { |
| 351 | if (code == SYS_DOWN || code == SYS_HALT) { | 363 | if (code == SYS_DOWN || code == SYS_HALT) |
| 352 | /* Turn the card off */ | 364 | eurwdt_disable_timer(); /* Turn the card off */ |
| 353 | eurwdt_disable_timer(); | ||
| 354 | } | ||
| 355 | 365 | ||
| 356 | return NOTIFY_DONE; | 366 | return NOTIFY_DONE; |
| 357 | } | 367 | } |
| @@ -362,11 +372,11 @@ static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code, | |||
| 362 | 372 | ||
| 363 | 373 | ||
| 364 | static const struct file_operations eurwdt_fops = { | 374 | static const struct file_operations eurwdt_fops = { |
| 365 | .owner = THIS_MODULE, | 375 | .owner = THIS_MODULE, |
| 366 | .llseek = no_llseek, | 376 | .llseek = no_llseek, |
| 367 | .write = eurwdt_write, | 377 | .write = eurwdt_write, |
| 368 | .ioctl = eurwdt_ioctl, | 378 | .unlocked_ioctl = eurwdt_ioctl, |
| 369 | .open = eurwdt_open, | 379 | .open = eurwdt_open, |
| 370 | .release = eurwdt_release, | 380 | .release = eurwdt_release, |
| 371 | }; | 381 | }; |
| 372 | 382 | ||
| @@ -419,7 +429,7 @@ static int __init eurwdt_init(void) | |||
| 419 | int ret; | 429 | int ret; |
| 420 | 430 | ||
| 421 | ret = request_irq(irq, eurwdt_interrupt, IRQF_DISABLED, "eurwdt", NULL); | 431 | ret = request_irq(irq, eurwdt_interrupt, IRQF_DISABLED, "eurwdt", NULL); |
| 422 | if(ret) { | 432 | if (ret) { |
| 423 | printk(KERN_ERR "eurwdt: IRQ %d is not free.\n", irq); | 433 | printk(KERN_ERR "eurwdt: IRQ %d is not free.\n", irq); |
| 424 | goto out; | 434 | goto out; |
| 425 | } | 435 | } |
| @@ -432,10 +442,13 @@ static int __init eurwdt_init(void) | |||
| 432 | 442 | ||
| 433 | ret = register_reboot_notifier(&eurwdt_notifier); | 443 | ret = register_reboot_notifier(&eurwdt_notifier); |
| 434 | if (ret) { | 444 | if (ret) { |
| 435 | printk(KERN_ERR "eurwdt: can't register reboot notifier (err=%d)\n", ret); | 445 | printk(KERN_ERR |
| 446 | "eurwdt: can't register reboot notifier (err=%d)\n", ret); | ||
| 436 | goto outreg; | 447 | goto outreg; |
| 437 | } | 448 | } |
| 438 | 449 | ||
| 450 | spin_lock_init(&eurwdt_lock); | ||
| 451 | |||
| 439 | ret = misc_register(&eurwdt_miscdev); | 452 | ret = misc_register(&eurwdt_miscdev); |
| 440 | if (ret) { | 453 | if (ret) { |
| 441 | printk(KERN_ERR "eurwdt: can't misc_register on minor=%d\n", | 454 | printk(KERN_ERR "eurwdt: can't misc_register on minor=%d\n", |
diff --git a/drivers/watchdog/geodewdt.c b/drivers/watchdog/geodewdt.c index 30d09cbbad94..614a5c7017b6 100644 --- a/drivers/watchdog/geodewdt.c +++ b/drivers/watchdog/geodewdt.c | |||
| @@ -17,8 +17,8 @@ | |||
| 17 | #include <linux/fs.h> | 17 | #include <linux/fs.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/reboot.h> | 19 | #include <linux/reboot.h> |
| 20 | #include <linux/uaccess.h> | ||
| 20 | 21 | ||
| 21 | #include <asm/uaccess.h> | ||
| 22 | #include <asm/geode.h> | 22 | #include <asm/geode.h> |
| 23 | 23 | ||
| 24 | #define GEODEWDT_HZ 500 | 24 | #define GEODEWDT_HZ 500 |
| @@ -77,27 +77,24 @@ static int geodewdt_set_heartbeat(int val) | |||
| 77 | return 0; | 77 | return 0; |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | static int | 80 | static int geodewdt_open(struct inode *inode, struct file *file) |
| 81 | geodewdt_open(struct inode *inode, struct file *file) | ||
| 82 | { | 81 | { |
| 83 | if (test_and_set_bit(WDT_FLAGS_OPEN, &wdt_flags)) | 82 | if (test_and_set_bit(WDT_FLAGS_OPEN, &wdt_flags)) |
| 84 | return -EBUSY; | 83 | return -EBUSY; |
| 85 | 84 | ||
| 86 | if (!test_and_clear_bit(WDT_FLAGS_ORPHAN, &wdt_flags)) | 85 | if (!test_and_clear_bit(WDT_FLAGS_ORPHAN, &wdt_flags)) |
| 87 | __module_get(THIS_MODULE); | 86 | __module_get(THIS_MODULE); |
| 88 | 87 | ||
| 89 | geodewdt_ping(); | 88 | geodewdt_ping(); |
| 90 | return nonseekable_open(inode, file); | 89 | return nonseekable_open(inode, file); |
| 91 | } | 90 | } |
| 92 | 91 | ||
| 93 | static int | 92 | static int geodewdt_release(struct inode *inode, struct file *file) |
| 94 | geodewdt_release(struct inode *inode, struct file *file) | ||
| 95 | { | 93 | { |
| 96 | if (safe_close) { | 94 | if (safe_close) { |
| 97 | geodewdt_disable(); | 95 | geodewdt_disable(); |
| 98 | module_put(THIS_MODULE); | 96 | module_put(THIS_MODULE); |
| 99 | } | 97 | } else { |
| 100 | else { | ||
| 101 | printk(KERN_CRIT "Unexpected close - watchdog is not stopping.\n"); | 98 | printk(KERN_CRIT "Unexpected close - watchdog is not stopping.\n"); |
| 102 | geodewdt_ping(); | 99 | geodewdt_ping(); |
| 103 | 100 | ||
| @@ -109,11 +106,10 @@ geodewdt_release(struct inode *inode, struct file *file) | |||
| 109 | return 0; | 106 | return 0; |
| 110 | } | 107 | } |
| 111 | 108 | ||
| 112 | static ssize_t | 109 | static ssize_t geodewdt_write(struct file *file, const char __user *data, |
| 113 | geodewdt_write(struct file *file, const char __user *data, size_t len, | 110 | size_t len, loff_t *ppos) |
| 114 | loff_t *ppos) | ||
| 115 | { | 111 | { |
| 116 | if(len) { | 112 | if (len) { |
| 117 | if (!nowayout) { | 113 | if (!nowayout) { |
| 118 | size_t i; | 114 | size_t i; |
| 119 | safe_close = 0; | 115 | safe_close = 0; |
| @@ -134,9 +130,8 @@ geodewdt_write(struct file *file, const char __user *data, size_t len, | |||
| 134 | return len; | 130 | return len; |
| 135 | } | 131 | } |
| 136 | 132 | ||
| 137 | static int | 133 | static int geodewdt_ioctl(struct inode *inode, struct file *file, |
| 138 | geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 134 | unsigned int cmd, unsigned long arg) |
| 139 | unsigned long arg) | ||
| 140 | { | 135 | { |
| 141 | void __user *argp = (void __user *)arg; | 136 | void __user *argp = (void __user *)arg; |
| 142 | int __user *p = argp; | 137 | int __user *p = argp; |
| @@ -147,9 +142,9 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 147 | | WDIOF_MAGICCLOSE, | 142 | | WDIOF_MAGICCLOSE, |
| 148 | .firmware_version = 1, | 143 | .firmware_version = 1, |
| 149 | .identity = WATCHDOG_NAME, | 144 | .identity = WATCHDOG_NAME, |
| 150 | }; | 145 | }; |
| 151 | 146 | ||
| 152 | switch(cmd) { | 147 | switch (cmd) { |
| 153 | case WDIOC_GETSUPPORT: | 148 | case WDIOC_GETSUPPORT: |
| 154 | return copy_to_user(argp, &ident, | 149 | return copy_to_user(argp, &ident, |
| 155 | sizeof(ident)) ? -EFAULT : 0; | 150 | sizeof(ident)) ? -EFAULT : 0; |
| @@ -159,22 +154,6 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 159 | case WDIOC_GETBOOTSTATUS: | 154 | case WDIOC_GETBOOTSTATUS: |
| 160 | return put_user(0, p); | 155 | return put_user(0, p); |
| 161 | 156 | ||
| 162 | case WDIOC_KEEPALIVE: | ||
| 163 | geodewdt_ping(); | ||
| 164 | return 0; | ||
| 165 | |||
| 166 | case WDIOC_SETTIMEOUT: | ||
| 167 | if (get_user(interval, p)) | ||
| 168 | return -EFAULT; | ||
| 169 | |||
| 170 | if (geodewdt_set_heartbeat(interval)) | ||
| 171 | return -EINVAL; | ||
| 172 | |||
| 173 | /* Fall through */ | ||
| 174 | |||
| 175 | case WDIOC_GETTIMEOUT: | ||
| 176 | return put_user(timeout, p); | ||
| 177 | |||
| 178 | case WDIOC_SETOPTIONS: | 157 | case WDIOC_SETOPTIONS: |
| 179 | { | 158 | { |
| 180 | int options, ret = -EINVAL; | 159 | int options, ret = -EINVAL; |
| @@ -194,6 +173,20 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 194 | 173 | ||
| 195 | return ret; | 174 | return ret; |
| 196 | } | 175 | } |
| 176 | case WDIOC_KEEPALIVE: | ||
| 177 | geodewdt_ping(); | ||
| 178 | return 0; | ||
| 179 | |||
| 180 | case WDIOC_SETTIMEOUT: | ||
| 181 | if (get_user(interval, p)) | ||
| 182 | return -EFAULT; | ||
| 183 | |||
| 184 | if (geodewdt_set_heartbeat(interval)) | ||
| 185 | return -EINVAL; | ||
| 186 | /* Fall through */ | ||
| 187 | case WDIOC_GETTIMEOUT: | ||
| 188 | return put_user(timeout, p); | ||
| 189 | |||
| 197 | default: | 190 | default: |
| 198 | return -ENOTTY; | 191 | return -ENOTTY; |
| 199 | } | 192 | } |
| @@ -202,22 +195,21 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 202 | } | 195 | } |
| 203 | 196 | ||
| 204 | static const struct file_operations geodewdt_fops = { | 197 | static const struct file_operations geodewdt_fops = { |
| 205 | .owner = THIS_MODULE, | 198 | .owner = THIS_MODULE, |
| 206 | .llseek = no_llseek, | 199 | .llseek = no_llseek, |
| 207 | .write = geodewdt_write, | 200 | .write = geodewdt_write, |
| 208 | .ioctl = geodewdt_ioctl, | 201 | .ioctl = geodewdt_ioctl, |
| 209 | .open = geodewdt_open, | 202 | .open = geodewdt_open, |
| 210 | .release = geodewdt_release, | 203 | .release = geodewdt_release, |
| 211 | }; | 204 | }; |
| 212 | 205 | ||
| 213 | static struct miscdevice geodewdt_miscdev = { | 206 | static struct miscdevice geodewdt_miscdev = { |
| 214 | .minor = WATCHDOG_MINOR, | 207 | .minor = WATCHDOG_MINOR, |
| 215 | .name = "watchdog", | 208 | .name = "watchdog", |
| 216 | .fops = &geodewdt_fops | 209 | .fops = &geodewdt_fops, |
| 217 | }; | 210 | }; |
| 218 | 211 | ||
| 219 | static int __devinit | 212 | static int __devinit geodewdt_probe(struct platform_device *dev) |
| 220 | geodewdt_probe(struct platform_device *dev) | ||
| 221 | { | 213 | { |
| 222 | int ret, timer; | 214 | int ret, timer; |
| 223 | 215 | ||
| @@ -248,15 +240,13 @@ geodewdt_probe(struct platform_device *dev) | |||
| 248 | return ret; | 240 | return ret; |
| 249 | } | 241 | } |
| 250 | 242 | ||
| 251 | static int __devexit | 243 | static int __devexit geodewdt_remove(struct platform_device *dev) |
| 252 | geodewdt_remove(struct platform_device *dev) | ||
| 253 | { | 244 | { |
| 254 | misc_deregister(&geodewdt_miscdev); | 245 | misc_deregister(&geodewdt_miscdev); |
| 255 | return 0; | 246 | return 0; |
| 256 | } | 247 | } |
| 257 | 248 | ||
| 258 | static void | 249 | static void geodewdt_shutdown(struct platform_device *dev) |
| 259 | geodewdt_shutdown(struct platform_device *dev) | ||
| 260 | { | 250 | { |
| 261 | geodewdt_disable(); | 251 | geodewdt_disable(); |
| 262 | } | 252 | } |
| @@ -271,8 +261,7 @@ static struct platform_driver geodewdt_driver = { | |||
| 271 | }, | 261 | }, |
| 272 | }; | 262 | }; |
| 273 | 263 | ||
| 274 | static int __init | 264 | static int __init geodewdt_init(void) |
| 275 | geodewdt_init(void) | ||
| 276 | { | 265 | { |
| 277 | int ret; | 266 | int ret; |
| 278 | 267 | ||
| @@ -292,8 +281,7 @@ err: | |||
| 292 | return ret; | 281 | return ret; |
| 293 | } | 282 | } |
| 294 | 283 | ||
| 295 | static void __exit | 284 | static void __exit geodewdt_exit(void) |
| 296 | geodewdt_exit(void) | ||
| 297 | { | 285 | { |
| 298 | platform_device_unregister(geodewdt_platform_device); | 286 | platform_device_unregister(geodewdt_platform_device); |
| 299 | platform_driver_unregister(&geodewdt_driver); | 287 | platform_driver_unregister(&geodewdt_driver); |
diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index ccd6c530782d..d039d5f2fd1c 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c | |||
| @@ -39,9 +39,7 @@ | |||
| 39 | #include <linux/string.h> | 39 | #include <linux/string.h> |
| 40 | #include <linux/bootmem.h> | 40 | #include <linux/bootmem.h> |
| 41 | #include <linux/slab.h> | 41 | #include <linux/slab.h> |
| 42 | #include <asm/dmi.h> | ||
| 43 | #include <asm/desc.h> | 42 | #include <asm/desc.h> |
| 44 | #include <asm/kdebug.h> | ||
| 45 | 43 | ||
| 46 | #define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */ | 44 | #define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */ |
| 47 | #define CRU_BIOS_SIGNATURE_VALUE 0x55524324 | 45 | #define CRU_BIOS_SIGNATURE_VALUE 0x55524324 |
| @@ -407,7 +405,7 @@ static int __devinit detect_cru_service(void) | |||
| 407 | dmi_walk(dmi_find_cru); | 405 | dmi_walk(dmi_find_cru); |
| 408 | 406 | ||
| 409 | /* if cru_rom_addr has been set then we found a CRU service */ | 407 | /* if cru_rom_addr has been set then we found a CRU service */ |
| 410 | return ((cru_rom_addr != NULL)? 0: -ENODEV); | 408 | return ((cru_rom_addr != NULL) ? 0: -ENODEV); |
| 411 | } | 409 | } |
| 412 | 410 | ||
| 413 | /* ------------------------------------------------------------------------- */ | 411 | /* ------------------------------------------------------------------------- */ |
| @@ -535,7 +533,7 @@ static ssize_t hpwdt_write(struct file *file, const char __user *data, | |||
| 535 | /* scan to see whether or not we got the magic char. */ | 533 | /* scan to see whether or not we got the magic char. */ |
| 536 | for (i = 0; i != len; i++) { | 534 | for (i = 0; i != len; i++) { |
| 537 | char c; | 535 | char c; |
| 538 | if (get_user(c, data+i)) | 536 | if (get_user(c, data + i)) |
| 539 | return -EFAULT; | 537 | return -EFAULT; |
| 540 | if (c == 'V') | 538 | if (c == 'V') |
| 541 | expect_release = 42; | 539 | expect_release = 42; |
diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index ca44fd9b19bb..c13383f7fcb9 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c | |||
| @@ -9,18 +9,18 @@ | |||
| 9 | * as published by the Free Software Foundation; either version | 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. | 10 | * 2 of the License, or (at your option) any later version. |
| 11 | * | 11 | * |
| 12 | * based on i810-tco.c which is in turn based on softdog.c | 12 | * based on i810-tco.c which is in turn based on softdog.c |
| 13 | * | 13 | * |
| 14 | * The timer is implemented in the following I/O controller hubs: | 14 | * The timer is implemented in the following I/O controller hubs: |
| 15 | * (See the intel documentation on http://developer.intel.com.) | 15 | * (See the intel documentation on http://developer.intel.com.) |
| 16 | * 6300ESB chip : document number 300641-003 | 16 | * 6300ESB chip : document number 300641-003 |
| 17 | * | 17 | * |
| 18 | * 2004YYZZ Ross Biro | 18 | * 2004YYZZ Ross Biro |
| 19 | * Initial version 0.01 | 19 | * Initial version 0.01 |
| 20 | * 2004YYZZ Ross Biro | 20 | * 2004YYZZ Ross Biro |
| 21 | * Version 0.02 | 21 | * Version 0.02 |
| 22 | * 20050210 David Härdeman <david@2gen.com> | 22 | * 20050210 David Härdeman <david@2gen.com> |
| 23 | * Ported driver to kernel 2.6 | 23 | * Ported driver to kernel 2.6 |
| 24 | */ | 24 | */ |
| 25 | 25 | ||
| 26 | /* | 26 | /* |
| @@ -38,9 +38,8 @@ | |||
| 38 | #include <linux/init.h> | 38 | #include <linux/init.h> |
| 39 | #include <linux/pci.h> | 39 | #include <linux/pci.h> |
| 40 | #include <linux/ioport.h> | 40 | #include <linux/ioport.h> |
| 41 | 41 | #include <linux/uaccess.h> | |
| 42 | #include <asm/uaccess.h> | 42 | #include <linux/io.h> |
| 43 | #include <asm/io.h> | ||
| 44 | 43 | ||
| 45 | /* Module and version information */ | 44 | /* Module and version information */ |
| 46 | #define ESB_VERSION "0.03" | 45 | #define ESB_VERSION "0.03" |
| @@ -59,17 +58,17 @@ | |||
| 59 | #define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */ | 58 | #define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */ |
| 60 | 59 | ||
| 61 | /* Lock register bits */ | 60 | /* Lock register bits */ |
| 62 | #define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */ | 61 | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ |
| 63 | #define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */ | 62 | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ |
| 64 | #define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */ | 63 | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ |
| 65 | 64 | ||
| 66 | /* Config register bits */ | 65 | /* Config register bits */ |
| 67 | #define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */ | 66 | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ |
| 68 | #define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */ | 67 | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ |
| 69 | #define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */ | 68 | #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ |
| 70 | 69 | ||
| 71 | /* Reload register bits */ | 70 | /* Reload register bits */ |
| 72 | #define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */ | 71 | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ |
| 73 | 72 | ||
| 74 | /* Magic constants */ | 73 | /* Magic constants */ |
| 75 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ | 74 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ |
| @@ -84,14 +83,20 @@ static unsigned short triggered; /* The status of the watchdog upon boot */ | |||
| 84 | static char esb_expect_close; | 83 | static char esb_expect_close; |
| 85 | 84 | ||
| 86 | /* module parameters */ | 85 | /* module parameters */ |
| 87 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat (1<heartbeat<2*1023) */ | 86 | /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */ |
| 87 | #define WATCHDOG_HEARTBEAT 30 | ||
| 88 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ | 88 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ |
| 89 | |||
| 89 | module_param(heartbeat, int, 0); | 90 | module_param(heartbeat, int, 0); |
| 90 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (1<heartbeat<2046, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | 91 | MODULE_PARM_DESC(heartbeat, |
| 92 | "Watchdog heartbeat in seconds. (1<heartbeat<2046, default=" | ||
| 93 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | ||
| 91 | 94 | ||
| 92 | static int nowayout = WATCHDOG_NOWAYOUT; | 95 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 93 | module_param(nowayout, int, 0); | 96 | module_param(nowayout, int, 0); |
| 94 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 97 | MODULE_PARM_DESC(nowayout, |
| 98 | "Watchdog cannot be stopped once started (default=" | ||
| 99 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 95 | 100 | ||
| 96 | /* | 101 | /* |
| 97 | * Some i6300ESB specific functions | 102 | * Some i6300ESB specific functions |
| @@ -103,9 +108,10 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" _ | |||
| 103 | * reload register. After this the appropriate registers can be written | 108 | * reload register. After this the appropriate registers can be written |
| 104 | * to once before they need to be unlocked again. | 109 | * to once before they need to be unlocked again. |
| 105 | */ | 110 | */ |
| 106 | static inline void esb_unlock_registers(void) { | 111 | static inline void esb_unlock_registers(void) |
| 107 | writeb(ESB_UNLOCK1, ESB_RELOAD_REG); | 112 | { |
| 108 | writeb(ESB_UNLOCK2, ESB_RELOAD_REG); | 113 | writeb(ESB_UNLOCK1, ESB_RELOAD_REG); |
| 114 | writeb(ESB_UNLOCK2, ESB_RELOAD_REG); | ||
| 109 | } | 115 | } |
| 110 | 116 | ||
| 111 | static void esb_timer_start(void) | 117 | static void esb_timer_start(void) |
| @@ -114,8 +120,7 @@ static void esb_timer_start(void) | |||
| 114 | 120 | ||
| 115 | /* Enable or Enable + Lock? */ | 121 | /* Enable or Enable + Lock? */ |
| 116 | val = 0x02 | (nowayout ? 0x01 : 0x00); | 122 | val = 0x02 | (nowayout ? 0x01 : 0x00); |
| 117 | 123 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, val); | |
| 118 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, val); | ||
| 119 | } | 124 | } |
| 120 | 125 | ||
| 121 | static int esb_timer_stop(void) | 126 | static int esb_timer_stop(void) |
| @@ -140,7 +145,7 @@ static void esb_timer_keepalive(void) | |||
| 140 | spin_lock(&esb_lock); | 145 | spin_lock(&esb_lock); |
| 141 | esb_unlock_registers(); | 146 | esb_unlock_registers(); |
| 142 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); | 147 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
| 143 | /* FIXME: Do we need to flush anything here? */ | 148 | /* FIXME: Do we need to flush anything here? */ |
| 144 | spin_unlock(&esb_lock); | 149 | spin_unlock(&esb_lock); |
| 145 | } | 150 | } |
| 146 | 151 | ||
| @@ -165,9 +170,9 @@ static int esb_timer_set_heartbeat(int time) | |||
| 165 | 170 | ||
| 166 | /* Write timer 2 */ | 171 | /* Write timer 2 */ |
| 167 | esb_unlock_registers(); | 172 | esb_unlock_registers(); |
| 168 | writel(val, ESB_TIMER2_REG); | 173 | writel(val, ESB_TIMER2_REG); |
| 169 | 174 | ||
| 170 | /* Reload */ | 175 | /* Reload */ |
| 171 | esb_unlock_registers(); | 176 | esb_unlock_registers(); |
| 172 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); | 177 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
| 173 | 178 | ||
| @@ -179,54 +184,55 @@ static int esb_timer_set_heartbeat(int time) | |||
| 179 | return 0; | 184 | return 0; |
| 180 | } | 185 | } |
| 181 | 186 | ||
| 182 | static int esb_timer_read (void) | 187 | static int esb_timer_read(void) |
| 183 | { | 188 | { |
| 184 | u32 count; | 189 | u32 count; |
| 185 | 190 | ||
| 186 | /* This isn't documented, and doesn't take into | 191 | /* This isn't documented, and doesn't take into |
| 187 | * acount which stage is running, but it looks | 192 | * acount which stage is running, but it looks |
| 188 | * like a 20 bit count down, so we might as well report it. | 193 | * like a 20 bit count down, so we might as well report it. |
| 189 | */ | 194 | */ |
| 190 | pci_read_config_dword(esb_pci, 0x64, &count); | 195 | pci_read_config_dword(esb_pci, 0x64, &count); |
| 191 | return (int)count; | 196 | return (int)count; |
| 192 | } | 197 | } |
| 193 | 198 | ||
| 194 | /* | 199 | /* |
| 195 | * /dev/watchdog handling | 200 | * /dev/watchdog handling |
| 196 | */ | 201 | */ |
| 197 | 202 | ||
| 198 | static int esb_open (struct inode *inode, struct file *file) | 203 | static int esb_open(struct inode *inode, struct file *file) |
| 199 | { | 204 | { |
| 200 | /* /dev/watchdog can only be opened once */ | 205 | /* /dev/watchdog can only be opened once */ |
| 201 | if (test_and_set_bit(0, &timer_alive)) | 206 | if (test_and_set_bit(0, &timer_alive)) |
| 202 | return -EBUSY; | 207 | return -EBUSY; |
| 203 | 208 | ||
| 204 | /* Reload and activate timer */ | 209 | /* Reload and activate timer */ |
| 205 | esb_timer_keepalive (); | 210 | esb_timer_keepalive(); |
| 206 | esb_timer_start (); | 211 | esb_timer_start(); |
| 207 | 212 | ||
| 208 | return nonseekable_open(inode, file); | 213 | return nonseekable_open(inode, file); |
| 209 | } | 214 | } |
| 210 | 215 | ||
| 211 | static int esb_release (struct inode *inode, struct file *file) | 216 | static int esb_release(struct inode *inode, struct file *file) |
| 212 | { | 217 | { |
| 213 | /* Shut off the timer. */ | 218 | /* Shut off the timer. */ |
| 214 | if (esb_expect_close == 42) { | 219 | if (esb_expect_close == 42) |
| 215 | esb_timer_stop (); | 220 | esb_timer_stop(); |
| 216 | } else { | 221 | else { |
| 217 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 222 | printk(KERN_CRIT PFX |
| 218 | esb_timer_keepalive (); | 223 | "Unexpected close, not stopping watchdog!\n"); |
| 219 | } | 224 | esb_timer_keepalive(); |
| 220 | clear_bit(0, &timer_alive); | 225 | } |
| 221 | esb_expect_close = 0; | 226 | clear_bit(0, &timer_alive); |
| 222 | return 0; | 227 | esb_expect_close = 0; |
| 228 | return 0; | ||
| 223 | } | 229 | } |
| 224 | 230 | ||
| 225 | static ssize_t esb_write (struct file *file, const char __user *data, | 231 | static ssize_t esb_write(struct file *file, const char __user *data, |
| 226 | size_t len, loff_t * ppos) | 232 | size_t len, loff_t *ppos) |
| 227 | { | 233 | { |
| 228 | /* See if we got the magic character 'V' and reload the timer */ | 234 | /* See if we got the magic character 'V' and reload the timer */ |
| 229 | if (len) { | 235 | if (len) { |
| 230 | if (!nowayout) { | 236 | if (!nowayout) { |
| 231 | size_t i; | 237 | size_t i; |
| 232 | 238 | ||
| @@ -237,7 +243,7 @@ static ssize_t esb_write (struct file *file, const char __user *data, | |||
| 237 | /* scan to see whether or not we got the magic character */ | 243 | /* scan to see whether or not we got the magic character */ |
| 238 | for (i = 0; i != len; i++) { | 244 | for (i = 0; i != len; i++) { |
| 239 | char c; | 245 | char c; |
| 240 | if(get_user(c, data+i)) | 246 | if (get_user(c, data + i)) |
| 241 | return -EFAULT; | 247 | return -EFAULT; |
| 242 | if (c == 'V') | 248 | if (c == 'V') |
| 243 | esb_expect_close = 42; | 249 | esb_expect_close = 42; |
| @@ -245,92 +251,84 @@ static ssize_t esb_write (struct file *file, const char __user *data, | |||
| 245 | } | 251 | } |
| 246 | 252 | ||
| 247 | /* someone wrote to us, we should reload the timer */ | 253 | /* someone wrote to us, we should reload the timer */ |
| 248 | esb_timer_keepalive (); | 254 | esb_timer_keepalive(); |
| 249 | } | 255 | } |
| 250 | return len; | 256 | return len; |
| 251 | } | 257 | } |
| 252 | 258 | ||
| 253 | static int esb_ioctl (struct inode *inode, struct file *file, | 259 | static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 254 | unsigned int cmd, unsigned long arg) | ||
| 255 | { | 260 | { |
| 256 | int new_options, retval = -EINVAL; | 261 | int new_options, retval = -EINVAL; |
| 257 | int new_heartbeat; | 262 | int new_heartbeat; |
| 258 | void __user *argp = (void __user *)arg; | 263 | void __user *argp = (void __user *)arg; |
| 259 | int __user *p = argp; | 264 | int __user *p = argp; |
| 260 | static struct watchdog_info ident = { | 265 | static struct watchdog_info ident = { |
| 261 | .options = WDIOF_SETTIMEOUT | | 266 | .options = WDIOF_SETTIMEOUT | |
| 262 | WDIOF_KEEPALIVEPING | | 267 | WDIOF_KEEPALIVEPING | |
| 263 | WDIOF_MAGICCLOSE, | 268 | WDIOF_MAGICCLOSE, |
| 264 | .firmware_version = 0, | 269 | .firmware_version = 0, |
| 265 | .identity = ESB_MODULE_NAME, | 270 | .identity = ESB_MODULE_NAME, |
| 266 | }; | 271 | }; |
| 267 | 272 | ||
| 268 | switch (cmd) { | 273 | switch (cmd) { |
| 269 | case WDIOC_GETSUPPORT: | 274 | case WDIOC_GETSUPPORT: |
| 270 | return copy_to_user(argp, &ident, | 275 | return copy_to_user(argp, &ident, |
| 271 | sizeof (ident)) ? -EFAULT : 0; | 276 | sizeof(ident)) ? -EFAULT : 0; |
| 272 | |||
| 273 | case WDIOC_GETSTATUS: | ||
| 274 | return put_user (esb_timer_read(), p); | ||
| 275 | |||
| 276 | case WDIOC_GETBOOTSTATUS: | ||
| 277 | return put_user (triggered, p); | ||
| 278 | 277 | ||
| 279 | case WDIOC_KEEPALIVE: | 278 | case WDIOC_GETSTATUS: |
| 280 | esb_timer_keepalive (); | 279 | return put_user(esb_timer_read(), p); |
| 281 | return 0; | ||
| 282 | 280 | ||
| 283 | case WDIOC_SETOPTIONS: | 281 | case WDIOC_GETBOOTSTATUS: |
| 284 | { | 282 | return put_user(triggered, p); |
| 285 | if (get_user (new_options, p)) | ||
| 286 | return -EFAULT; | ||
| 287 | 283 | ||
| 288 | if (new_options & WDIOS_DISABLECARD) { | 284 | case WDIOC_SETOPTIONS: |
| 289 | esb_timer_stop (); | 285 | { |
| 290 | retval = 0; | 286 | if (get_user(new_options, p)) |
| 291 | } | 287 | return -EFAULT; |
| 292 | 288 | ||
| 293 | if (new_options & WDIOS_ENABLECARD) { | 289 | if (new_options & WDIOS_DISABLECARD) { |
| 294 | esb_timer_keepalive (); | 290 | esb_timer_stop(); |
| 295 | esb_timer_start (); | 291 | retval = 0; |
| 296 | retval = 0; | 292 | } |
| 297 | } | ||
| 298 | |||
| 299 | return retval; | ||
| 300 | } | ||
| 301 | |||
| 302 | case WDIOC_SETTIMEOUT: | ||
| 303 | { | ||
| 304 | if (get_user(new_heartbeat, p)) | ||
| 305 | return -EFAULT; | ||
| 306 | |||
| 307 | if (esb_timer_set_heartbeat(new_heartbeat)) | ||
| 308 | return -EINVAL; | ||
| 309 | |||
| 310 | esb_timer_keepalive (); | ||
| 311 | /* Fall */ | ||
| 312 | } | ||
| 313 | |||
| 314 | case WDIOC_GETTIMEOUT: | ||
| 315 | return put_user(heartbeat, p); | ||
| 316 | 293 | ||
| 317 | default: | 294 | if (new_options & WDIOS_ENABLECARD) { |
| 318 | return -ENOTTY; | 295 | esb_timer_keepalive(); |
| 319 | } | 296 | esb_timer_start(); |
| 297 | retval = 0; | ||
| 298 | } | ||
| 299 | return retval; | ||
| 300 | } | ||
| 301 | case WDIOC_KEEPALIVE: | ||
| 302 | esb_timer_keepalive(); | ||
| 303 | return 0; | ||
| 304 | |||
| 305 | case WDIOC_SETTIMEOUT: | ||
| 306 | { | ||
| 307 | if (get_user(new_heartbeat, p)) | ||
| 308 | return -EFAULT; | ||
| 309 | if (esb_timer_set_heartbeat(new_heartbeat)) | ||
| 310 | return -EINVAL; | ||
| 311 | esb_timer_keepalive(); | ||
| 312 | /* Fall */ | ||
| 313 | } | ||
| 314 | case WDIOC_GETTIMEOUT: | ||
| 315 | return put_user(heartbeat, p); | ||
| 316 | default: | ||
| 317 | return -ENOTTY; | ||
| 318 | } | ||
| 320 | } | 319 | } |
| 321 | 320 | ||
| 322 | /* | 321 | /* |
| 323 | * Notify system | 322 | * Notify system |
| 324 | */ | 323 | */ |
| 325 | 324 | ||
| 326 | static int esb_notify_sys (struct notifier_block *this, unsigned long code, void *unused) | 325 | static int esb_notify_sys(struct notifier_block *this, |
| 326 | unsigned long code, void *unused) | ||
| 327 | { | 327 | { |
| 328 | if (code==SYS_DOWN || code==SYS_HALT) { | 328 | if (code == SYS_DOWN || code == SYS_HALT) |
| 329 | /* Turn the WDT off */ | 329 | esb_timer_stop(); /* Turn the WDT off */ |
| 330 | esb_timer_stop (); | ||
| 331 | } | ||
| 332 | 330 | ||
| 333 | return NOTIFY_DONE; | 331 | return NOTIFY_DONE; |
| 334 | } | 332 | } |
| 335 | 333 | ||
| 336 | /* | 334 | /* |
| @@ -338,22 +336,22 @@ static int esb_notify_sys (struct notifier_block *this, unsigned long code, void | |||
| 338 | */ | 336 | */ |
| 339 | 337 | ||
| 340 | static const struct file_operations esb_fops = { | 338 | static const struct file_operations esb_fops = { |
| 341 | .owner = THIS_MODULE, | 339 | .owner = THIS_MODULE, |
| 342 | .llseek = no_llseek, | 340 | .llseek = no_llseek, |
| 343 | .write = esb_write, | 341 | .write = esb_write, |
| 344 | .ioctl = esb_ioctl, | 342 | .unlocked_ioctl = esb_ioctl, |
| 345 | .open = esb_open, | 343 | .open = esb_open, |
| 346 | .release = esb_release, | 344 | .release = esb_release, |
| 347 | }; | 345 | }; |
| 348 | 346 | ||
| 349 | static struct miscdevice esb_miscdev = { | 347 | static struct miscdevice esb_miscdev = { |
| 350 | .minor = WATCHDOG_MINOR, | 348 | .minor = WATCHDOG_MINOR, |
| 351 | .name = "watchdog", | 349 | .name = "watchdog", |
| 352 | .fops = &esb_fops, | 350 | .fops = &esb_fops, |
| 353 | }; | 351 | }; |
| 354 | 352 | ||
| 355 | static struct notifier_block esb_notifier = { | 353 | static struct notifier_block esb_notifier = { |
| 356 | .notifier_call = esb_notify_sys, | 354 | .notifier_call = esb_notify_sys, |
| 357 | }; | 355 | }; |
| 358 | 356 | ||
| 359 | /* | 357 | /* |
| @@ -365,50 +363,44 @@ static struct notifier_block esb_notifier = { | |||
| 365 | * want to register another driver on the same PCI id. | 363 | * want to register another driver on the same PCI id. |
| 366 | */ | 364 | */ |
| 367 | static struct pci_device_id esb_pci_tbl[] = { | 365 | static struct pci_device_id esb_pci_tbl[] = { |
| 368 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), }, | 366 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), }, |
| 369 | { 0, }, /* End of list */ | 367 | { 0, }, /* End of list */ |
| 370 | }; | 368 | }; |
| 371 | MODULE_DEVICE_TABLE (pci, esb_pci_tbl); | 369 | MODULE_DEVICE_TABLE(pci, esb_pci_tbl); |
| 372 | 370 | ||
| 373 | /* | 371 | /* |
| 374 | * Init & exit routines | 372 | * Init & exit routines |
| 375 | */ | 373 | */ |
| 376 | 374 | ||
| 377 | static unsigned char __init esb_getdevice (void) | 375 | static unsigned char __init esb_getdevice(void) |
| 378 | { | 376 | { |
| 379 | u8 val1; | 377 | u8 val1; |
| 380 | unsigned short val2; | 378 | unsigned short val2; |
| 379 | /* | ||
| 380 | * Find the PCI device | ||
| 381 | */ | ||
| 381 | 382 | ||
| 382 | struct pci_dev *dev = NULL; | 383 | esb_pci = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 383 | /* | 384 | PCI_DEVICE_ID_INTEL_ESB_9, NULL); |
| 384 | * Find the PCI device | ||
| 385 | */ | ||
| 386 | |||
| 387 | for_each_pci_dev(dev) { | ||
| 388 | if (pci_match_id(esb_pci_tbl, dev)) { | ||
| 389 | esb_pci = dev; | ||
| 390 | break; | ||
| 391 | } | ||
| 392 | } | ||
| 393 | 385 | ||
| 394 | if (esb_pci) { | 386 | if (esb_pci) { |
| 395 | if (pci_enable_device(esb_pci)) { | 387 | if (pci_enable_device(esb_pci)) { |
| 396 | printk (KERN_ERR PFX "failed to enable device\n"); | 388 | printk(KERN_ERR PFX "failed to enable device\n"); |
| 397 | goto err_devput; | 389 | goto err_devput; |
| 398 | } | 390 | } |
| 399 | 391 | ||
| 400 | if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) { | 392 | if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) { |
| 401 | printk (KERN_ERR PFX "failed to request region\n"); | 393 | printk(KERN_ERR PFX "failed to request region\n"); |
| 402 | goto err_disable; | 394 | goto err_disable; |
| 403 | } | 395 | } |
| 404 | 396 | ||
| 405 | BASEADDR = ioremap(pci_resource_start(esb_pci, 0), | 397 | BASEADDR = ioremap(pci_resource_start(esb_pci, 0), |
| 406 | pci_resource_len(esb_pci, 0)); | 398 | pci_resource_len(esb_pci, 0)); |
| 407 | if (BASEADDR == NULL) { | 399 | if (BASEADDR == NULL) { |
| 408 | /* Something's wrong here, BASEADDR has to be set */ | 400 | /* Something's wrong here, BASEADDR has to be set */ |
| 409 | printk (KERN_ERR PFX "failed to get BASEADDR\n"); | 401 | printk(KERN_ERR PFX "failed to get BASEADDR\n"); |
| 410 | goto err_release; | 402 | goto err_release; |
| 411 | } | 403 | } |
| 412 | 404 | ||
| 413 | /* | 405 | /* |
| 414 | * The watchdog has two timers, it can be setup so that the | 406 | * The watchdog has two timers, it can be setup so that the |
| @@ -425,7 +417,7 @@ static unsigned char __init esb_getdevice (void) | |||
| 425 | /* Check that the WDT isn't already locked */ | 417 | /* Check that the WDT isn't already locked */ |
| 426 | pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1); | 418 | pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1); |
| 427 | if (val1 & ESB_WDT_LOCK) | 419 | if (val1 & ESB_WDT_LOCK) |
| 428 | printk (KERN_WARNING PFX "nowayout already set\n"); | 420 | printk(KERN_WARNING PFX "nowayout already set\n"); |
| 429 | 421 | ||
| 430 | /* Set the timer to watchdog mode and disable it for now */ | 422 | /* Set the timer to watchdog mode and disable it for now */ |
| 431 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00); | 423 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00); |
| @@ -452,44 +444,44 @@ err_devput: | |||
| 452 | return 0; | 444 | return 0; |
| 453 | } | 445 | } |
| 454 | 446 | ||
| 455 | static int __init watchdog_init (void) | 447 | static int __init watchdog_init(void) |
| 456 | { | 448 | { |
| 457 | int ret; | 449 | int ret; |
| 458 | 450 | ||
| 459 | /* Check whether or not the hardware watchdog is there */ | 451 | /* Check whether or not the hardware watchdog is there */ |
| 460 | if (!esb_getdevice () || esb_pci == NULL) | 452 | if (!esb_getdevice() || esb_pci == NULL) |
| 461 | return -ENODEV; | 453 | return -ENODEV; |
| 462 | 454 | ||
| 463 | /* Check that the heartbeat value is within it's range ; if not reset to the default */ | 455 | /* Check that the heartbeat value is within it's range; |
| 464 | if (esb_timer_set_heartbeat (heartbeat)) { | 456 | if not reset to the default */ |
| 465 | esb_timer_set_heartbeat (WATCHDOG_HEARTBEAT); | 457 | if (esb_timer_set_heartbeat(heartbeat)) { |
| 466 | printk(KERN_INFO PFX "heartbeat value must be 1<heartbeat<2046, using %d\n", | 458 | esb_timer_set_heartbeat(WATCHDOG_HEARTBEAT); |
| 467 | heartbeat); | 459 | printk(KERN_INFO PFX |
| 468 | } | 460 | "heartbeat value must be 1<heartbeat<2046, using %d\n", |
| 469 | 461 | heartbeat); | |
| 470 | ret = register_reboot_notifier(&esb_notifier); | 462 | } |
| 471 | if (ret != 0) { | 463 | ret = register_reboot_notifier(&esb_notifier); |
| 472 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 464 | if (ret != 0) { |
| 473 | ret); | 465 | printk(KERN_ERR PFX |
| 474 | goto err_unmap; | 466 | "cannot register reboot notifier (err=%d)\n", ret); |
| 475 | } | 467 | goto err_unmap; |
| 476 | 468 | } | |
| 477 | ret = misc_register(&esb_miscdev); | ||
| 478 | if (ret != 0) { | ||
| 479 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | ||
| 480 | WATCHDOG_MINOR, ret); | ||
| 481 | goto err_notifier; | ||
| 482 | } | ||
| 483 | |||
| 484 | esb_timer_stop (); | ||
| 485 | |||
| 486 | printk (KERN_INFO PFX "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", | ||
| 487 | BASEADDR, heartbeat, nowayout); | ||
| 488 | 469 | ||
| 489 | return 0; | 470 | ret = misc_register(&esb_miscdev); |
| 471 | if (ret != 0) { | ||
| 472 | printk(KERN_ERR PFX | ||
| 473 | "cannot register miscdev on minor=%d (err=%d)\n", | ||
| 474 | WATCHDOG_MINOR, ret); | ||
| 475 | goto err_notifier; | ||
| 476 | } | ||
| 477 | esb_timer_stop(); | ||
| 478 | printk(KERN_INFO PFX | ||
| 479 | "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", | ||
| 480 | BASEADDR, heartbeat, nowayout); | ||
| 481 | return 0; | ||
| 490 | 482 | ||
| 491 | err_notifier: | 483 | err_notifier: |
| 492 | unregister_reboot_notifier(&esb_notifier); | 484 | unregister_reboot_notifier(&esb_notifier); |
| 493 | err_unmap: | 485 | err_unmap: |
| 494 | iounmap(BASEADDR); | 486 | iounmap(BASEADDR); |
| 495 | /* err_release: */ | 487 | /* err_release: */ |
| @@ -498,18 +490,18 @@ err_unmap: | |||
| 498 | pci_disable_device(esb_pci); | 490 | pci_disable_device(esb_pci); |
| 499 | /* err_devput: */ | 491 | /* err_devput: */ |
| 500 | pci_dev_put(esb_pci); | 492 | pci_dev_put(esb_pci); |
| 501 | return ret; | 493 | return ret; |
| 502 | } | 494 | } |
| 503 | 495 | ||
| 504 | static void __exit watchdog_cleanup (void) | 496 | static void __exit watchdog_cleanup(void) |
| 505 | { | 497 | { |
| 506 | /* Stop the timer before we leave */ | 498 | /* Stop the timer before we leave */ |
| 507 | if (!nowayout) | 499 | if (!nowayout) |
| 508 | esb_timer_stop (); | 500 | esb_timer_stop(); |
| 509 | 501 | ||
| 510 | /* Deregister */ | 502 | /* Deregister */ |
| 511 | misc_deregister(&esb_miscdev); | 503 | misc_deregister(&esb_miscdev); |
| 512 | unregister_reboot_notifier(&esb_notifier); | 504 | unregister_reboot_notifier(&esb_notifier); |
| 513 | iounmap(BASEADDR); | 505 | iounmap(BASEADDR); |
| 514 | pci_release_region(esb_pci, 0); | 506 | pci_release_region(esb_pci, 0); |
| 515 | pci_disable_device(esb_pci); | 507 | pci_disable_device(esb_pci); |
diff --git a/drivers/watchdog/iTCO_vendor.h b/drivers/watchdog/iTCO_vendor.h new file mode 100644 index 000000000000..9e27e6422f66 --- /dev/null +++ b/drivers/watchdog/iTCO_vendor.h | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | /* iTCO Vendor Specific Support hooks */ | ||
| 2 | #ifdef CONFIG_ITCO_VENDOR_SUPPORT | ||
| 3 | extern void iTCO_vendor_pre_start(unsigned long, unsigned int); | ||
| 4 | extern void iTCO_vendor_pre_stop(unsigned long); | ||
| 5 | extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int); | ||
| 6 | extern void iTCO_vendor_pre_set_heartbeat(unsigned int); | ||
| 7 | extern int iTCO_vendor_check_noreboot_on(void); | ||
| 8 | #else | ||
| 9 | #define iTCO_vendor_pre_start(acpibase, heartbeat) {} | ||
| 10 | #define iTCO_vendor_pre_stop(acpibase) {} | ||
| 11 | #define iTCO_vendor_pre_keepalive(acpibase, heartbeat) {} | ||
| 12 | #define iTCO_vendor_pre_set_heartbeat(heartbeat) {} | ||
| 13 | #define iTCO_vendor_check_noreboot_on() 1 | ||
| 14 | /* 1=check noreboot; 0=don't check */ | ||
| 15 | #endif | ||
diff --git a/drivers/watchdog/iTCO_vendor_support.c b/drivers/watchdog/iTCO_vendor_support.c index cafc465f2ae3..ca344a85eb95 100644 --- a/drivers/watchdog/iTCO_vendor_support.c +++ b/drivers/watchdog/iTCO_vendor_support.c | |||
| @@ -18,9 +18,9 @@ | |||
| 18 | */ | 18 | */ |
| 19 | 19 | ||
| 20 | /* Module and version information */ | 20 | /* Module and version information */ |
| 21 | #define DRV_NAME "iTCO_vendor_support" | 21 | #define DRV_NAME "iTCO_vendor_support" |
| 22 | #define DRV_VERSION "1.01" | 22 | #define DRV_VERSION "1.01" |
| 23 | #define DRV_RELDATE "11-Nov-2006" | 23 | #define DRV_RELDATE "11-Nov-2006" |
| 24 | #define PFX DRV_NAME ": " | 24 | #define PFX DRV_NAME ": " |
| 25 | 25 | ||
| 26 | /* Includes */ | 26 | /* Includes */ |
| @@ -31,19 +31,22 @@ | |||
| 31 | #include <linux/kernel.h> /* For printk/panic/... */ | 31 | #include <linux/kernel.h> /* For printk/panic/... */ |
| 32 | #include <linux/init.h> /* For __init/__exit/... */ | 32 | #include <linux/init.h> /* For __init/__exit/... */ |
| 33 | #include <linux/ioport.h> /* For io-port access */ | 33 | #include <linux/ioport.h> /* For io-port access */ |
| 34 | #include <linux/io.h> /* For inb/outb/... */ | ||
| 34 | 35 | ||
| 35 | #include <asm/io.h> /* For inb/outb/... */ | 36 | #include "iTCO_vendor.h" |
| 36 | 37 | ||
| 37 | /* iTCO defines */ | 38 | /* iTCO defines */ |
| 38 | #define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */ | 39 | #define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */ |
| 39 | #define TCOBASE acpibase + 0x60 /* TCO base address */ | 40 | #define TCOBASE acpibase + 0x60 /* TCO base address */ |
| 40 | #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ | 41 | #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ |
| 41 | 42 | ||
| 42 | /* List of vendor support modes */ | 43 | /* List of vendor support modes */ |
| 43 | #define SUPERMICRO_OLD_BOARD 1 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ | 44 | /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ |
| 44 | #define SUPERMICRO_NEW_BOARD 2 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ | 45 | #define SUPERMICRO_OLD_BOARD 1 |
| 46 | /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ | ||
| 47 | #define SUPERMICRO_NEW_BOARD 2 | ||
| 45 | 48 | ||
| 46 | static int vendorsupport = 0; | 49 | static int vendorsupport; |
| 47 | module_param(vendorsupport, int, 0); | 50 | module_param(vendorsupport, int, 0); |
| 48 | MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+"); | 51 | MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+"); |
| 49 | 52 | ||
| @@ -143,34 +146,35 @@ static void supermicro_old_pre_keepalive(unsigned long acpibase) | |||
| 143 | */ | 146 | */ |
| 144 | 147 | ||
| 145 | /* I/O Port's */ | 148 | /* I/O Port's */ |
| 146 | #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ | 149 | #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ |
| 147 | #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ | 150 | #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ |
| 148 | 151 | ||
| 149 | /* Control Register's */ | 152 | /* Control Register's */ |
| 150 | #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ | 153 | #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ |
| 151 | #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ | 154 | #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ |
| 152 | 155 | ||
| 153 | #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ | 156 | #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ |
| 154 | 157 | ||
| 155 | #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ | 158 | #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ |
| 156 | 159 | ||
| 157 | #define SM_ENDWATCH 0xAA /* Watchdog lock control page */ | 160 | #define SM_ENDWATCH 0xAA /* Watchdog lock control page */ |
| 158 | 161 | ||
| 159 | #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ | 162 | #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ |
| 160 | /* (Bit 3: 0 = seconds, 1 = minutes */ | 163 | /* (Bit 3: 0 = seconds, 1 = minutes */ |
| 161 | 164 | ||
| 162 | #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ | 165 | #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ |
| 163 | 166 | ||
| 164 | #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ | 167 | #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ |
| 165 | /* Bit 6: timer is reset by kbd interrupt */ | 168 | /* Bit 6: timer is reset by kbd interrupt */ |
| 166 | /* Bit 7: timer is reset by mouse interrupt */ | 169 | /* Bit 7: timer is reset by mouse interrupt */ |
| 167 | 170 | ||
| 168 | static void supermicro_new_unlock_watchdog(void) | 171 | static void supermicro_new_unlock_watchdog(void) |
| 169 | { | 172 | { |
| 170 | outb(SM_WATCHPAGE, SM_REGINDEX); /* Write 0x87 to port 0x2e twice */ | 173 | /* Write 0x87 to port 0x2e twice */ |
| 171 | outb(SM_WATCHPAGE, SM_REGINDEX); | 174 | outb(SM_WATCHPAGE, SM_REGINDEX); |
| 172 | 175 | outb(SM_WATCHPAGE, SM_REGINDEX); | |
| 173 | outb(SM_CTLPAGESW, SM_REGINDEX); /* Switch to watchdog control page */ | 176 | /* Switch to watchdog control page */ |
| 177 | outb(SM_CTLPAGESW, SM_REGINDEX); | ||
| 174 | outb(SM_CTLPAGE, SM_DATAIO); | 178 | outb(SM_CTLPAGE, SM_DATAIO); |
| 175 | } | 179 | } |
| 176 | 180 | ||
| @@ -192,7 +196,7 @@ static void supermicro_new_pre_start(unsigned int heartbeat) | |||
| 192 | outb(val, SM_DATAIO); | 196 | outb(val, SM_DATAIO); |
| 193 | 197 | ||
| 194 | /* Write heartbeat interval to WDOG */ | 198 | /* Write heartbeat interval to WDOG */ |
| 195 | outb (SM_WATCHTIMER, SM_REGINDEX); | 199 | outb(SM_WATCHTIMER, SM_REGINDEX); |
| 196 | outb((heartbeat & 255), SM_DATAIO); | 200 | outb((heartbeat & 255), SM_DATAIO); |
| 197 | 201 | ||
| 198 | /* Make sure keyboard/mouse interrupts don't interfere */ | 202 | /* Make sure keyboard/mouse interrupts don't interfere */ |
| @@ -277,7 +281,7 @@ EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat); | |||
| 277 | 281 | ||
| 278 | int iTCO_vendor_check_noreboot_on(void) | 282 | int iTCO_vendor_check_noreboot_on(void) |
| 279 | { | 283 | { |
| 280 | switch(vendorsupport) { | 284 | switch (vendorsupport) { |
| 281 | case SUPERMICRO_OLD_BOARD: | 285 | case SUPERMICRO_OLD_BOARD: |
| 282 | return 0; | 286 | return 0; |
| 283 | default: | 287 | default: |
| @@ -288,13 +292,13 @@ EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on); | |||
| 288 | 292 | ||
| 289 | static int __init iTCO_vendor_init_module(void) | 293 | static int __init iTCO_vendor_init_module(void) |
| 290 | { | 294 | { |
| 291 | printk (KERN_INFO PFX "vendor-support=%d\n", vendorsupport); | 295 | printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport); |
| 292 | return 0; | 296 | return 0; |
| 293 | } | 297 | } |
| 294 | 298 | ||
| 295 | static void __exit iTCO_vendor_exit_module(void) | 299 | static void __exit iTCO_vendor_exit_module(void) |
| 296 | { | 300 | { |
| 297 | printk (KERN_INFO PFX "Module Unloaded\n"); | 301 | printk(KERN_INFO PFX "Module Unloaded\n"); |
| 298 | } | 302 | } |
| 299 | 303 | ||
| 300 | module_init(iTCO_vendor_init_module); | 304 | module_init(iTCO_vendor_init_module); |
diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index 95ba985bd341..bfb93bc2ca9f 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c | |||
| @@ -55,9 +55,9 @@ | |||
| 55 | */ | 55 | */ |
| 56 | 56 | ||
| 57 | /* Module and version information */ | 57 | /* Module and version information */ |
| 58 | #define DRV_NAME "iTCO_wdt" | 58 | #define DRV_NAME "iTCO_wdt" |
| 59 | #define DRV_VERSION "1.03" | 59 | #define DRV_VERSION "1.03" |
| 60 | #define DRV_RELDATE "30-Apr-2008" | 60 | #define DRV_RELDATE "30-Apr-2008" |
| 61 | #define PFX DRV_NAME ": " | 61 | #define PFX DRV_NAME ": " |
| 62 | 62 | ||
| 63 | /* Includes */ | 63 | /* Includes */ |
| @@ -66,7 +66,8 @@ | |||
| 66 | #include <linux/types.h> /* For standard types (like size_t) */ | 66 | #include <linux/types.h> /* For standard types (like size_t) */ |
| 67 | #include <linux/errno.h> /* For the -ENODEV/... values */ | 67 | #include <linux/errno.h> /* For the -ENODEV/... values */ |
| 68 | #include <linux/kernel.h> /* For printk/panic/... */ | 68 | #include <linux/kernel.h> /* For printk/panic/... */ |
| 69 | #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */ | 69 | #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV |
| 70 | (WATCHDOG_MINOR) */ | ||
| 70 | #include <linux/watchdog.h> /* For the watchdog specific items */ | 71 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
| 71 | #include <linux/init.h> /* For __init/__exit/... */ | 72 | #include <linux/init.h> /* For __init/__exit/... */ |
| 72 | #include <linux/fs.h> /* For file operations */ | 73 | #include <linux/fs.h> /* For file operations */ |
| @@ -74,9 +75,10 @@ | |||
| 74 | #include <linux/pci.h> /* For pci functions */ | 75 | #include <linux/pci.h> /* For pci functions */ |
| 75 | #include <linux/ioport.h> /* For io-port access */ | 76 | #include <linux/ioport.h> /* For io-port access */ |
| 76 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | 77 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ |
| 78 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ | ||
| 79 | #include <linux/io.h> /* For inb/outb/... */ | ||
| 77 | 80 | ||
| 78 | #include <asm/uaccess.h> /* For copy_to_user/put_user/... */ | 81 | #include "iTCO_vendor.h" |
| 79 | #include <asm/io.h> /* For inb/outb/... */ | ||
| 80 | 82 | ||
| 81 | /* TCO related info */ | 83 | /* TCO related info */ |
| 82 | enum iTCO_chipsets { | 84 | enum iTCO_chipsets { |
| @@ -105,7 +107,7 @@ enum iTCO_chipsets { | |||
| 105 | TCO_ICH9, /* ICH9 */ | 107 | TCO_ICH9, /* ICH9 */ |
| 106 | TCO_ICH9R, /* ICH9R */ | 108 | TCO_ICH9R, /* ICH9R */ |
| 107 | TCO_ICH9DH, /* ICH9DH */ | 109 | TCO_ICH9DH, /* ICH9DH */ |
| 108 | TCO_ICH9DO, /* ICH9DO */ | 110 | TCO_ICH9DO, /* ICH9DO */ |
| 109 | TCO_631XESB, /* 631xESB/632xESB */ | 111 | TCO_631XESB, /* 631xESB/632xESB */ |
| 110 | }; | 112 | }; |
| 111 | 113 | ||
| @@ -140,7 +142,7 @@ static struct { | |||
| 140 | {"ICH9DH", 2}, | 142 | {"ICH9DH", 2}, |
| 141 | {"ICH9DO", 2}, | 143 | {"ICH9DO", 2}, |
| 142 | {"631xESB/632xESB", 2}, | 144 | {"631xESB/632xESB", 2}, |
| 143 | {NULL,0} | 145 | {NULL, 0} |
| 144 | }; | 146 | }; |
| 145 | 147 | ||
| 146 | #define ITCO_PCI_DEVICE(dev, data) \ | 148 | #define ITCO_PCI_DEVICE(dev, data) \ |
| @@ -159,32 +161,32 @@ static struct { | |||
| 159 | * functions that probably will be registered by other drivers. | 161 | * functions that probably will be registered by other drivers. |
| 160 | */ | 162 | */ |
| 161 | static struct pci_device_id iTCO_wdt_pci_tbl[] = { | 163 | static struct pci_device_id iTCO_wdt_pci_tbl[] = { |
| 162 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH )}, | 164 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)}, |
| 163 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0 )}, | 165 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)}, |
| 164 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2 )}, | 166 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)}, |
| 165 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M )}, | 167 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)}, |
| 166 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3 )}, | 168 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)}, |
| 167 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M )}, | 169 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)}, |
| 168 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4 )}, | 170 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)}, |
| 169 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M )}, | 171 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)}, |
| 170 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH )}, | 172 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)}, |
| 171 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5 )}, | 173 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)}, |
| 172 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)}, | 174 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)}, |
| 173 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6 )}, | 175 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)}, |
| 174 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M )}, | 176 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)}, |
| 175 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W )}, | 177 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)}, |
| 176 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7 )}, | 178 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, |
| 177 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M )}, | 179 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, |
| 178 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, | 180 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, |
| 179 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8 )}, | 181 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, |
| 180 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME )}, | 182 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, |
| 181 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH )}, | 183 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, |
| 182 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO )}, | 184 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, |
| 183 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M )}, | 185 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, |
| 184 | { ITCO_PCI_DEVICE(0x2918, TCO_ICH9 )}, | 186 | { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, |
| 185 | { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R )}, | 187 | { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, |
| 186 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH )}, | 188 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, |
| 187 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO )}, | 189 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, |
| 188 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, | 190 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, |
| 189 | { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, | 191 | { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, |
| 190 | { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, | 192 | { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, |
| @@ -203,13 +205,15 @@ static struct pci_device_id iTCO_wdt_pci_tbl[] = { | |||
| 203 | { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, | 205 | { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, |
| 204 | { 0, }, /* End of list */ | 206 | { 0, }, /* End of list */ |
| 205 | }; | 207 | }; |
| 206 | MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl); | 208 | MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl); |
| 207 | 209 | ||
| 208 | /* Address definitions for the TCO */ | 210 | /* Address definitions for the TCO */ |
| 209 | #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */ | 211 | /* TCO base address */ |
| 210 | #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */ | 212 | #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 |
| 213 | /* SMI Control and Enable Register */ | ||
| 214 | #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 | ||
| 211 | 215 | ||
| 212 | #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */ | 216 | #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */ |
| 213 | #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */ | 217 | #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */ |
| 214 | #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ | 218 | #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ |
| 215 | #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ | 219 | #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ |
| @@ -222,15 +226,21 @@ MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl); | |||
| 222 | /* internal variables */ | 226 | /* internal variables */ |
| 223 | static unsigned long is_active; | 227 | static unsigned long is_active; |
| 224 | static char expect_release; | 228 | static char expect_release; |
| 225 | static struct { /* this is private data for the iTCO_wdt device */ | 229 | static struct { /* this is private data for the iTCO_wdt device */ |
| 226 | unsigned int iTCO_version; /* TCO version/generation */ | 230 | /* TCO version/generation */ |
| 227 | unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ | 231 | unsigned int iTCO_version; |
| 228 | unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */ | 232 | /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ |
| 229 | spinlock_t io_lock; /* the lock for io operations */ | 233 | unsigned long ACPIBASE; |
| 230 | struct pci_dev *pdev; /* the PCI-device */ | 234 | /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/ |
| 235 | unsigned long __iomem *gcs; | ||
| 236 | /* the lock for io operations */ | ||
| 237 | spinlock_t io_lock; | ||
| 238 | /* the PCI-device */ | ||
| 239 | struct pci_dev *pdev; | ||
| 231 | } iTCO_wdt_private; | 240 | } iTCO_wdt_private; |
| 232 | 241 | ||
| 233 | static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */ | 242 | /* the watchdog platform device */ |
| 243 | static struct platform_device *iTCO_wdt_platform_device; | ||
| 234 | 244 | ||
| 235 | /* module parameters */ | 245 | /* module parameters */ |
| 236 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ | 246 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ |
| @@ -240,22 +250,9 @@ MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO | |||
| 240 | 250 | ||
| 241 | static int nowayout = WATCHDOG_NOWAYOUT; | 251 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 242 | module_param(nowayout, int, 0); | 252 | module_param(nowayout, int, 0); |
| 243 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 253 | MODULE_PARM_DESC(nowayout, |
| 244 | 254 | "Watchdog cannot be stopped once started (default=" | |
| 245 | /* iTCO Vendor Specific Support hooks */ | 255 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 246 | #ifdef CONFIG_ITCO_VENDOR_SUPPORT | ||
| 247 | extern void iTCO_vendor_pre_start(unsigned long, unsigned int); | ||
| 248 | extern void iTCO_vendor_pre_stop(unsigned long); | ||
| 249 | extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int); | ||
| 250 | extern void iTCO_vendor_pre_set_heartbeat(unsigned int); | ||
| 251 | extern int iTCO_vendor_check_noreboot_on(void); | ||
| 252 | #else | ||
| 253 | #define iTCO_vendor_pre_start(acpibase, heartbeat) {} | ||
| 254 | #define iTCO_vendor_pre_stop(acpibase) {} | ||
| 255 | #define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {} | ||
| 256 | #define iTCO_vendor_pre_set_heartbeat(heartbeat) {} | ||
| 257 | #define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */ | ||
| 258 | #endif | ||
| 259 | 256 | ||
| 260 | /* | 257 | /* |
| 261 | * Some TCO specific functions | 258 | * Some TCO specific functions |
| @@ -369,11 +366,10 @@ static int iTCO_wdt_keepalive(void) | |||
| 369 | iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat); | 366 | iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat); |
| 370 | 367 | ||
| 371 | /* Reload the timer by writing to the TCO Timer Counter register */ | 368 | /* Reload the timer by writing to the TCO Timer Counter register */ |
| 372 | if (iTCO_wdt_private.iTCO_version == 2) { | 369 | if (iTCO_wdt_private.iTCO_version == 2) |
| 373 | outw(0x01, TCO_RLD); | 370 | outw(0x01, TCO_RLD); |
| 374 | } else if (iTCO_wdt_private.iTCO_version == 1) { | 371 | else if (iTCO_wdt_private.iTCO_version == 1) |
| 375 | outb(0x01, TCO_RLD); | 372 | outb(0x01, TCO_RLD); |
| 376 | } | ||
| 377 | 373 | ||
| 378 | spin_unlock(&iTCO_wdt_private.io_lock); | 374 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 379 | return 0; | 375 | return 0; |
| @@ -425,7 +421,7 @@ static int iTCO_wdt_set_heartbeat(int t) | |||
| 425 | return 0; | 421 | return 0; |
| 426 | } | 422 | } |
| 427 | 423 | ||
| 428 | static int iTCO_wdt_get_timeleft (int *time_left) | 424 | static int iTCO_wdt_get_timeleft(int *time_left) |
| 429 | { | 425 | { |
| 430 | unsigned int val16; | 426 | unsigned int val16; |
| 431 | unsigned char val8; | 427 | unsigned char val8; |
| @@ -454,7 +450,7 @@ static int iTCO_wdt_get_timeleft (int *time_left) | |||
| 454 | * /dev/watchdog handling | 450 | * /dev/watchdog handling |
| 455 | */ | 451 | */ |
| 456 | 452 | ||
| 457 | static int iTCO_wdt_open (struct inode *inode, struct file *file) | 453 | static int iTCO_wdt_open(struct inode *inode, struct file *file) |
| 458 | { | 454 | { |
| 459 | /* /dev/watchdog can only be opened once */ | 455 | /* /dev/watchdog can only be opened once */ |
| 460 | if (test_and_set_bit(0, &is_active)) | 456 | if (test_and_set_bit(0, &is_active)) |
| @@ -468,7 +464,7 @@ static int iTCO_wdt_open (struct inode *inode, struct file *file) | |||
| 468 | return nonseekable_open(inode, file); | 464 | return nonseekable_open(inode, file); |
| 469 | } | 465 | } |
| 470 | 466 | ||
| 471 | static int iTCO_wdt_release (struct inode *inode, struct file *file) | 467 | static int iTCO_wdt_release(struct inode *inode, struct file *file) |
| 472 | { | 468 | { |
| 473 | /* | 469 | /* |
| 474 | * Shut off the timer. | 470 | * Shut off the timer. |
| @@ -476,7 +472,8 @@ static int iTCO_wdt_release (struct inode *inode, struct file *file) | |||
| 476 | if (expect_release == 42) { | 472 | if (expect_release == 42) { |
| 477 | iTCO_wdt_stop(); | 473 | iTCO_wdt_stop(); |
| 478 | } else { | 474 | } else { |
| 479 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 475 | printk(KERN_CRIT PFX |
| 476 | "Unexpected close, not stopping watchdog!\n"); | ||
| 480 | iTCO_wdt_keepalive(); | 477 | iTCO_wdt_keepalive(); |
| 481 | } | 478 | } |
| 482 | clear_bit(0, &is_active); | 479 | clear_bit(0, &is_active); |
| @@ -484,22 +481,23 @@ static int iTCO_wdt_release (struct inode *inode, struct file *file) | |||
| 484 | return 0; | 481 | return 0; |
| 485 | } | 482 | } |
| 486 | 483 | ||
| 487 | static ssize_t iTCO_wdt_write (struct file *file, const char __user *data, | 484 | static ssize_t iTCO_wdt_write(struct file *file, const char __user *data, |
| 488 | size_t len, loff_t * ppos) | 485 | size_t len, loff_t *ppos) |
| 489 | { | 486 | { |
| 490 | /* See if we got the magic character 'V' and reload the timer */ | 487 | /* See if we got the magic character 'V' and reload the timer */ |
| 491 | if (len) { | 488 | if (len) { |
| 492 | if (!nowayout) { | 489 | if (!nowayout) { |
| 493 | size_t i; | 490 | size_t i; |
| 494 | 491 | ||
| 495 | /* note: just in case someone wrote the magic character | 492 | /* note: just in case someone wrote the magic |
| 496 | * five months ago... */ | 493 | character five months ago... */ |
| 497 | expect_release = 0; | 494 | expect_release = 0; |
| 498 | 495 | ||
| 499 | /* scan to see whether or not we got the magic character */ | 496 | /* scan to see whether or not we got the |
| 497 | magic character */ | ||
| 500 | for (i = 0; i != len; i++) { | 498 | for (i = 0; i != len; i++) { |
| 501 | char c; | 499 | char c; |
| 502 | if (get_user(c, data+i)) | 500 | if (get_user(c, data + i)) |
| 503 | return -EFAULT; | 501 | return -EFAULT; |
| 504 | if (c == 'V') | 502 | if (c == 'V') |
| 505 | expect_release = 42; | 503 | expect_release = 42; |
| @@ -512,8 +510,8 @@ static ssize_t iTCO_wdt_write (struct file *file, const char __user *data, | |||
| 512 | return len; | 510 | return len; |
| 513 | } | 511 | } |
| 514 | 512 | ||
| 515 | static int iTCO_wdt_ioctl (struct inode *inode, struct file *file, | 513 | static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd, |
| 516 | unsigned int cmd, unsigned long arg) | 514 | unsigned long arg) |
| 517 | { | 515 | { |
| 518 | int new_options, retval = -EINVAL; | 516 | int new_options, retval = -EINVAL; |
| 519 | int new_heartbeat; | 517 | int new_heartbeat; |
| @@ -528,64 +526,52 @@ static int iTCO_wdt_ioctl (struct inode *inode, struct file *file, | |||
| 528 | }; | 526 | }; |
| 529 | 527 | ||
| 530 | switch (cmd) { | 528 | switch (cmd) { |
| 531 | case WDIOC_GETSUPPORT: | 529 | case WDIOC_GETSUPPORT: |
| 532 | return copy_to_user(argp, &ident, | 530 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 533 | sizeof (ident)) ? -EFAULT : 0; | 531 | case WDIOC_GETSTATUS: |
| 534 | 532 | case WDIOC_GETBOOTSTATUS: | |
| 535 | case WDIOC_GETSTATUS: | 533 | return put_user(0, p); |
| 536 | case WDIOC_GETBOOTSTATUS: | 534 | |
| 537 | return put_user(0, p); | 535 | case WDIOC_SETOPTIONS: |
| 538 | 536 | { | |
| 539 | case WDIOC_KEEPALIVE: | 537 | if (get_user(new_options, p)) |
| 540 | iTCO_wdt_keepalive(); | 538 | return -EFAULT; |
| 541 | return 0; | 539 | |
| 542 | 540 | if (new_options & WDIOS_DISABLECARD) { | |
| 543 | case WDIOC_SETOPTIONS: | 541 | iTCO_wdt_stop(); |
| 544 | { | 542 | retval = 0; |
| 545 | if (get_user(new_options, p)) | ||
| 546 | return -EFAULT; | ||
| 547 | |||
| 548 | if (new_options & WDIOS_DISABLECARD) { | ||
| 549 | iTCO_wdt_stop(); | ||
| 550 | retval = 0; | ||
| 551 | } | ||
| 552 | |||
| 553 | if (new_options & WDIOS_ENABLECARD) { | ||
| 554 | iTCO_wdt_keepalive(); | ||
| 555 | iTCO_wdt_start(); | ||
| 556 | retval = 0; | ||
| 557 | } | ||
| 558 | |||
| 559 | return retval; | ||
| 560 | } | 543 | } |
| 561 | 544 | if (new_options & WDIOS_ENABLECARD) { | |
| 562 | case WDIOC_SETTIMEOUT: | ||
| 563 | { | ||
| 564 | if (get_user(new_heartbeat, p)) | ||
| 565 | return -EFAULT; | ||
| 566 | |||
| 567 | if (iTCO_wdt_set_heartbeat(new_heartbeat)) | ||
| 568 | return -EINVAL; | ||
| 569 | |||
| 570 | iTCO_wdt_keepalive(); | 545 | iTCO_wdt_keepalive(); |
| 571 | /* Fall */ | 546 | iTCO_wdt_start(); |
| 572 | } | 547 | retval = 0; |
| 573 | |||
| 574 | case WDIOC_GETTIMEOUT: | ||
| 575 | return put_user(heartbeat, p); | ||
| 576 | |||
| 577 | case WDIOC_GETTIMELEFT: | ||
| 578 | { | ||
| 579 | int time_left; | ||
| 580 | |||
| 581 | if (iTCO_wdt_get_timeleft(&time_left)) | ||
| 582 | return -EINVAL; | ||
| 583 | |||
| 584 | return put_user(time_left, p); | ||
| 585 | } | 548 | } |
| 549 | return retval; | ||
| 550 | } | ||
| 551 | case WDIOC_KEEPALIVE: | ||
| 552 | iTCO_wdt_keepalive(); | ||
| 553 | return 0; | ||
| 586 | 554 | ||
| 587 | default: | 555 | case WDIOC_SETTIMEOUT: |
| 588 | return -ENOTTY; | 556 | { |
| 557 | if (get_user(new_heartbeat, p)) | ||
| 558 | return -EFAULT; | ||
| 559 | if (iTCO_wdt_set_heartbeat(new_heartbeat)) | ||
| 560 | return -EINVAL; | ||
| 561 | iTCO_wdt_keepalive(); | ||
| 562 | /* Fall */ | ||
| 563 | } | ||
| 564 | case WDIOC_GETTIMEOUT: | ||
| 565 | return put_user(heartbeat, p); | ||
| 566 | case WDIOC_GETTIMELEFT: | ||
| 567 | { | ||
| 568 | int time_left; | ||
| 569 | if (iTCO_wdt_get_timeleft(&time_left)) | ||
| 570 | return -EINVAL; | ||
| 571 | return put_user(time_left, p); | ||
| 572 | } | ||
| 573 | default: | ||
| 574 | return -ENOTTY; | ||
| 589 | } | 575 | } |
| 590 | } | 576 | } |
| 591 | 577 | ||
| @@ -594,12 +580,12 @@ static int iTCO_wdt_ioctl (struct inode *inode, struct file *file, | |||
| 594 | */ | 580 | */ |
| 595 | 581 | ||
| 596 | static const struct file_operations iTCO_wdt_fops = { | 582 | static const struct file_operations iTCO_wdt_fops = { |
| 597 | .owner = THIS_MODULE, | 583 | .owner = THIS_MODULE, |
| 598 | .llseek = no_llseek, | 584 | .llseek = no_llseek, |
| 599 | .write = iTCO_wdt_write, | 585 | .write = iTCO_wdt_write, |
| 600 | .ioctl = iTCO_wdt_ioctl, | 586 | .unlocked_ioctl = iTCO_wdt_ioctl, |
| 601 | .open = iTCO_wdt_open, | 587 | .open = iTCO_wdt_open, |
| 602 | .release = iTCO_wdt_release, | 588 | .release = iTCO_wdt_release, |
| 603 | }; | 589 | }; |
| 604 | 590 | ||
| 605 | static struct miscdevice iTCO_wdt_miscdev = { | 591 | static struct miscdevice iTCO_wdt_miscdev = { |
| @@ -612,7 +598,8 @@ static struct miscdevice iTCO_wdt_miscdev = { | |||
| 612 | * Init & exit routines | 598 | * Init & exit routines |
| 613 | */ | 599 | */ |
| 614 | 600 | ||
| 615 | static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev) | 601 | static int __devinit iTCO_wdt_init(struct pci_dev *pdev, |
| 602 | const struct pci_device_id *ent, struct platform_device *dev) | ||
| 616 | { | 603 | { |
| 617 | int ret; | 604 | int ret; |
| 618 | u32 base_address; | 605 | u32 base_address; |
| @@ -632,17 +619,19 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device | |||
| 632 | pci_dev_put(pdev); | 619 | pci_dev_put(pdev); |
| 633 | return -ENODEV; | 620 | return -ENODEV; |
| 634 | } | 621 | } |
| 635 | iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version; | 622 | iTCO_wdt_private.iTCO_version = |
| 623 | iTCO_chipset_info[ent->driver_data].iTCO_version; | ||
| 636 | iTCO_wdt_private.ACPIBASE = base_address; | 624 | iTCO_wdt_private.ACPIBASE = base_address; |
| 637 | iTCO_wdt_private.pdev = pdev; | 625 | iTCO_wdt_private.pdev = pdev; |
| 638 | 626 | ||
| 639 | /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */ | 627 | /* Get the Memory-Mapped GCS register, we need it for the |
| 640 | /* To get access to it you have to read RCBA from PCI Config space 0xf0 | 628 | NO_REBOOT flag (TCO v2). To get access to it you have to |
| 641 | and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */ | 629 | read RCBA from PCI Config space 0xf0 and use it as base. |
| 630 | GCS = RCBA + ICH6_GCS(0x3410). */ | ||
| 642 | if (iTCO_wdt_private.iTCO_version == 2) { | 631 | if (iTCO_wdt_private.iTCO_version == 2) { |
| 643 | pci_read_config_dword(pdev, 0xf0, &base_address); | 632 | pci_read_config_dword(pdev, 0xf0, &base_address); |
| 644 | RCBA = base_address & 0xffffc000; | 633 | RCBA = base_address & 0xffffc000; |
| 645 | iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4); | 634 | iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4); |
| 646 | } | 635 | } |
| 647 | 636 | ||
| 648 | /* Check chipset's NO_REBOOT bit */ | 637 | /* Check chipset's NO_REBOOT bit */ |
| @@ -657,8 +646,8 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device | |||
| 657 | 646 | ||
| 658 | /* Set the TCO_EN bit in SMI_EN register */ | 647 | /* Set the TCO_EN bit in SMI_EN register */ |
| 659 | if (!request_region(SMI_EN, 4, "iTCO_wdt")) { | 648 | if (!request_region(SMI_EN, 4, "iTCO_wdt")) { |
| 660 | printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", | 649 | printk(KERN_ERR PFX |
| 661 | SMI_EN ); | 650 | "I/O address 0x%04lx already in use\n", SMI_EN); |
| 662 | ret = -EIO; | 651 | ret = -EIO; |
| 663 | goto out; | 652 | goto out; |
| 664 | } | 653 | } |
| @@ -667,18 +656,20 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device | |||
| 667 | outl(val32, SMI_EN); | 656 | outl(val32, SMI_EN); |
| 668 | release_region(SMI_EN, 4); | 657 | release_region(SMI_EN, 4); |
| 669 | 658 | ||
| 670 | /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */ | 659 | /* The TCO I/O registers reside in a 32-byte range pointed to |
| 671 | if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) { | 660 | by the TCOBASE value */ |
| 672 | printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n", | 661 | if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) { |
| 662 | printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", | ||
| 673 | TCOBASE); | 663 | TCOBASE); |
| 674 | ret = -EIO; | 664 | ret = -EIO; |
| 675 | goto out; | 665 | goto out; |
| 676 | } | 666 | } |
| 677 | 667 | ||
| 678 | printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", | 668 | printk(KERN_INFO PFX |
| 679 | iTCO_chipset_info[ent->driver_data].name, | 669 | "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", |
| 680 | iTCO_chipset_info[ent->driver_data].iTCO_version, | 670 | iTCO_chipset_info[ent->driver_data].name, |
| 681 | TCOBASE); | 671 | iTCO_chipset_info[ent->driver_data].iTCO_version, |
| 672 | TCOBASE); | ||
| 682 | 673 | ||
| 683 | /* Clear out the (probably old) status */ | 674 | /* Clear out the (probably old) status */ |
| 684 | outb(0, TCO1_STS); | 675 | outb(0, TCO1_STS); |
| @@ -687,27 +678,29 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device | |||
| 687 | /* Make sure the watchdog is not running */ | 678 | /* Make sure the watchdog is not running */ |
| 688 | iTCO_wdt_stop(); | 679 | iTCO_wdt_stop(); |
| 689 | 680 | ||
| 690 | /* Check that the heartbeat value is within it's range ; if not reset to the default */ | 681 | /* Check that the heartbeat value is within it's range; |
| 682 | if not reset to the default */ | ||
| 691 | if (iTCO_wdt_set_heartbeat(heartbeat)) { | 683 | if (iTCO_wdt_set_heartbeat(heartbeat)) { |
| 692 | iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT); | 684 | iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT); |
| 693 | printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n", | 685 | printk(KERN_INFO PFX "heartbeat value must be 2 < heartbeat < 39 (TCO v1) or 613 (TCO v2), using %d\n", |
| 694 | heartbeat); | 686 | heartbeat); |
| 695 | } | 687 | } |
| 696 | 688 | ||
| 697 | ret = misc_register(&iTCO_wdt_miscdev); | 689 | ret = misc_register(&iTCO_wdt_miscdev); |
| 698 | if (ret != 0) { | 690 | if (ret != 0) { |
| 699 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 691 | printk(KERN_ERR PFX |
| 700 | WATCHDOG_MINOR, ret); | 692 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 693 | WATCHDOG_MINOR, ret); | ||
| 701 | goto unreg_region; | 694 | goto unreg_region; |
| 702 | } | 695 | } |
| 703 | 696 | ||
| 704 | printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", | 697 | printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", |
| 705 | heartbeat, nowayout); | 698 | heartbeat, nowayout); |
| 706 | 699 | ||
| 707 | return 0; | 700 | return 0; |
| 708 | 701 | ||
| 709 | unreg_region: | 702 | unreg_region: |
| 710 | release_region (TCOBASE, 0x20); | 703 | release_region(TCOBASE, 0x20); |
| 711 | out: | 704 | out: |
| 712 | if (iTCO_wdt_private.iTCO_version == 2) | 705 | if (iTCO_wdt_private.iTCO_version == 2) |
| 713 | iounmap(iTCO_wdt_private.gcs); | 706 | iounmap(iTCO_wdt_private.gcs); |
| @@ -796,7 +789,8 @@ static int __init iTCO_wdt_init_module(void) | |||
| 796 | if (err) | 789 | if (err) |
| 797 | return err; | 790 | return err; |
| 798 | 791 | ||
| 799 | iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); | 792 | iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, |
| 793 | -1, NULL, 0); | ||
| 800 | if (IS_ERR(iTCO_wdt_platform_device)) { | 794 | if (IS_ERR(iTCO_wdt_platform_device)) { |
| 801 | err = PTR_ERR(iTCO_wdt_platform_device); | 795 | err = PTR_ERR(iTCO_wdt_platform_device); |
| 802 | goto unreg_platform_driver; | 796 | goto unreg_platform_driver; |
diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 4b89f401691a..05a28106e8eb 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c | |||
| @@ -41,9 +41,9 @@ | |||
| 41 | #include <linux/spinlock.h> | 41 | #include <linux/spinlock.h> |
| 42 | #include <linux/moduleparam.h> | 42 | #include <linux/moduleparam.h> |
| 43 | #include <linux/platform_device.h> | 43 | #include <linux/platform_device.h> |
| 44 | #include <linux/io.h> | ||
| 45 | #include <linux/uaccess.h> | ||
| 44 | 46 | ||
| 45 | #include <asm/io.h> | ||
| 46 | #include <asm/uaccess.h> | ||
| 47 | #include <asm/system.h> | 47 | #include <asm/system.h> |
| 48 | 48 | ||
| 49 | static struct platform_device *ibwdt_platform_device; | 49 | static struct platform_device *ibwdt_platform_device; |
| @@ -120,15 +120,16 @@ static int wd_margin = WD_TIMO; | |||
| 120 | 120 | ||
| 121 | static int nowayout = WATCHDOG_NOWAYOUT; | 121 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 122 | module_param(nowayout, int, 0); | 122 | module_param(nowayout, int, 0); |
| 123 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 123 | MODULE_PARM_DESC(nowayout, |
| 124 | "Watchdog cannot be stopped once started (default=" | ||
| 125 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 124 | 126 | ||
| 125 | 127 | ||
| 126 | /* | 128 | /* |
| 127 | * Watchdog Operations | 129 | * Watchdog Operations |
| 128 | */ | 130 | */ |
| 129 | 131 | ||
| 130 | static void | 132 | static void ibwdt_ping(void) |
| 131 | ibwdt_ping(void) | ||
| 132 | { | 133 | { |
| 133 | spin_lock(&ibwdt_lock); | 134 | spin_lock(&ibwdt_lock); |
| 134 | 135 | ||
| @@ -138,16 +139,14 @@ ibwdt_ping(void) | |||
| 138 | spin_unlock(&ibwdt_lock); | 139 | spin_unlock(&ibwdt_lock); |
| 139 | } | 140 | } |
| 140 | 141 | ||
| 141 | static void | 142 | static void ibwdt_disable(void) |
| 142 | ibwdt_disable(void) | ||
| 143 | { | 143 | { |
| 144 | spin_lock(&ibwdt_lock); | 144 | spin_lock(&ibwdt_lock); |
| 145 | outb_p(0, WDT_STOP); | 145 | outb_p(0, WDT_STOP); |
| 146 | spin_unlock(&ibwdt_lock); | 146 | spin_unlock(&ibwdt_lock); |
| 147 | } | 147 | } |
| 148 | 148 | ||
| 149 | static int | 149 | static int ibwdt_set_heartbeat(int t) |
| 150 | ibwdt_set_heartbeat(int t) | ||
| 151 | { | 150 | { |
| 152 | int i; | 151 | int i; |
| 153 | 152 | ||
| @@ -165,8 +164,8 @@ ibwdt_set_heartbeat(int t) | |||
| 165 | * /dev/watchdog handling | 164 | * /dev/watchdog handling |
| 166 | */ | 165 | */ |
| 167 | 166 | ||
| 168 | static ssize_t | 167 | static ssize_t ibwdt_write(struct file *file, const char __user *buf, |
| 169 | ibwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | 168 | size_t count, loff_t *ppos) |
| 170 | { | 169 | { |
| 171 | if (count) { | 170 | if (count) { |
| 172 | if (!nowayout) { | 171 | if (!nowayout) { |
| @@ -188,77 +187,71 @@ ibwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppo | |||
| 188 | return count; | 187 | return count; |
| 189 | } | 188 | } |
| 190 | 189 | ||
| 191 | static int | 190 | static long ibwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 192 | ibwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | ||
| 193 | unsigned long arg) | ||
| 194 | { | 191 | { |
| 195 | int new_margin; | 192 | int new_margin; |
| 196 | void __user *argp = (void __user *)arg; | 193 | void __user *argp = (void __user *)arg; |
| 197 | int __user *p = argp; | 194 | int __user *p = argp; |
| 198 | 195 | ||
| 199 | static struct watchdog_info ident = { | 196 | static struct watchdog_info ident = { |
| 200 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 197 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
| 198 | | WDIOF_MAGICCLOSE, | ||
| 201 | .firmware_version = 1, | 199 | .firmware_version = 1, |
| 202 | .identity = "IB700 WDT", | 200 | .identity = "IB700 WDT", |
| 203 | }; | 201 | }; |
| 204 | 202 | ||
| 205 | switch (cmd) { | 203 | switch (cmd) { |
| 206 | case WDIOC_GETSUPPORT: | 204 | case WDIOC_GETSUPPORT: |
| 207 | if (copy_to_user(argp, &ident, sizeof(ident))) | 205 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 208 | return -EFAULT; | 206 | return -EFAULT; |
| 209 | break; | 207 | break; |
| 210 | 208 | ||
| 211 | case WDIOC_GETSTATUS: | 209 | case WDIOC_GETSTATUS: |
| 212 | case WDIOC_GETBOOTSTATUS: | 210 | case WDIOC_GETBOOTSTATUS: |
| 213 | return put_user(0, p); | 211 | return put_user(0, p); |
| 214 | |||
| 215 | case WDIOC_KEEPALIVE: | ||
| 216 | ibwdt_ping(); | ||
| 217 | break; | ||
| 218 | |||
| 219 | case WDIOC_SETTIMEOUT: | ||
| 220 | if (get_user(new_margin, p)) | ||
| 221 | return -EFAULT; | ||
| 222 | if (ibwdt_set_heartbeat(new_margin)) | ||
| 223 | return -EINVAL; | ||
| 224 | ibwdt_ping(); | ||
| 225 | /* Fall */ | ||
| 226 | |||
| 227 | case WDIOC_GETTIMEOUT: | ||
| 228 | return put_user(wd_times[wd_margin], p); | ||
| 229 | 212 | ||
| 230 | case WDIOC_SETOPTIONS: | 213 | case WDIOC_SETOPTIONS: |
| 231 | { | 214 | { |
| 232 | int options, retval = -EINVAL; | 215 | int options, retval = -EINVAL; |
| 233 | 216 | ||
| 234 | if (get_user(options, p)) | 217 | if (get_user(options, p)) |
| 235 | return -EFAULT; | 218 | return -EFAULT; |
| 236 | 219 | ||
| 237 | if (options & WDIOS_DISABLECARD) { | 220 | if (options & WDIOS_DISABLECARD) { |
| 238 | ibwdt_disable(); | 221 | ibwdt_disable(); |
| 239 | retval = 0; | 222 | retval = 0; |
| 240 | } | 223 | } |
| 224 | if (options & WDIOS_ENABLECARD) { | ||
| 225 | ibwdt_ping(); | ||
| 226 | retval = 0; | ||
| 227 | } | ||
| 228 | return retval; | ||
| 229 | } | ||
| 230 | case WDIOC_KEEPALIVE: | ||
| 231 | ibwdt_ping(); | ||
| 232 | break; | ||
| 241 | 233 | ||
| 242 | if (options & WDIOS_ENABLECARD) { | 234 | case WDIOC_SETTIMEOUT: |
| 243 | ibwdt_ping(); | 235 | if (get_user(new_margin, p)) |
| 244 | retval = 0; | 236 | return -EFAULT; |
| 245 | } | 237 | if (ibwdt_set_heartbeat(new_margin)) |
| 238 | return -EINVAL; | ||
| 239 | ibwdt_ping(); | ||
| 240 | /* Fall */ | ||
| 246 | 241 | ||
| 247 | return retval; | 242 | case WDIOC_GETTIMEOUT: |
| 248 | } | 243 | return put_user(wd_times[wd_margin], p); |
| 249 | 244 | ||
| 250 | default: | 245 | default: |
| 251 | return -ENOTTY; | 246 | return -ENOTTY; |
| 252 | } | 247 | } |
| 253 | return 0; | 248 | return 0; |
| 254 | } | 249 | } |
| 255 | 250 | ||
| 256 | static int | 251 | static int ibwdt_open(struct inode *inode, struct file *file) |
| 257 | ibwdt_open(struct inode *inode, struct file *file) | ||
| 258 | { | 252 | { |
| 259 | if (test_and_set_bit(0, &ibwdt_is_open)) { | 253 | if (test_and_set_bit(0, &ibwdt_is_open)) |
| 260 | return -EBUSY; | 254 | return -EBUSY; |
| 261 | } | ||
| 262 | if (nowayout) | 255 | if (nowayout) |
| 263 | __module_get(THIS_MODULE); | 256 | __module_get(THIS_MODULE); |
| 264 | 257 | ||
| @@ -267,13 +260,13 @@ ibwdt_open(struct inode *inode, struct file *file) | |||
| 267 | return nonseekable_open(inode, file); | 260 | return nonseekable_open(inode, file); |
| 268 | } | 261 | } |
| 269 | 262 | ||
| 270 | static int | 263 | static int ibwdt_close(struct inode *inode, struct file *file) |
| 271 | ibwdt_close(struct inode *inode, struct file *file) | ||
| 272 | { | 264 | { |
| 273 | if (expect_close == 42) { | 265 | if (expect_close == 42) { |
| 274 | ibwdt_disable(); | 266 | ibwdt_disable(); |
| 275 | } else { | 267 | } else { |
| 276 | printk(KERN_CRIT PFX "WDT device closed unexpectedly. WDT will not stop!\n"); | 268 | printk(KERN_CRIT PFX |
| 269 | "WDT device closed unexpectedly. WDT will not stop!\n"); | ||
| 277 | ibwdt_ping(); | 270 | ibwdt_ping(); |
| 278 | } | 271 | } |
| 279 | clear_bit(0, &ibwdt_is_open); | 272 | clear_bit(0, &ibwdt_is_open); |
| @@ -289,7 +282,7 @@ static const struct file_operations ibwdt_fops = { | |||
| 289 | .owner = THIS_MODULE, | 282 | .owner = THIS_MODULE, |
| 290 | .llseek = no_llseek, | 283 | .llseek = no_llseek, |
| 291 | .write = ibwdt_write, | 284 | .write = ibwdt_write, |
| 292 | .ioctl = ibwdt_ioctl, | 285 | .unlocked_ioctl = ibwdt_ioctl, |
| 293 | .open = ibwdt_open, | 286 | .open = ibwdt_open, |
| 294 | .release = ibwdt_close, | 287 | .release = ibwdt_close, |
| 295 | }; | 288 | }; |
| @@ -310,21 +303,23 @@ static int __devinit ibwdt_probe(struct platform_device *dev) | |||
| 310 | 303 | ||
| 311 | #if WDT_START != WDT_STOP | 304 | #if WDT_START != WDT_STOP |
| 312 | if (!request_region(WDT_STOP, 1, "IB700 WDT")) { | 305 | if (!request_region(WDT_STOP, 1, "IB700 WDT")) { |
| 313 | printk (KERN_ERR PFX "STOP method I/O %X is not available.\n", WDT_STOP); | 306 | printk(KERN_ERR PFX "STOP method I/O %X is not available.\n", |
| 307 | WDT_STOP); | ||
| 314 | res = -EIO; | 308 | res = -EIO; |
| 315 | goto out_nostopreg; | 309 | goto out_nostopreg; |
| 316 | } | 310 | } |
| 317 | #endif | 311 | #endif |
| 318 | 312 | ||
| 319 | if (!request_region(WDT_START, 1, "IB700 WDT")) { | 313 | if (!request_region(WDT_START, 1, "IB700 WDT")) { |
| 320 | printk (KERN_ERR PFX "START method I/O %X is not available.\n", WDT_START); | 314 | printk(KERN_ERR PFX "START method I/O %X is not available.\n", |
| 315 | WDT_START); | ||
| 321 | res = -EIO; | 316 | res = -EIO; |
| 322 | goto out_nostartreg; | 317 | goto out_nostartreg; |
| 323 | } | 318 | } |
| 324 | 319 | ||
| 325 | res = misc_register(&ibwdt_miscdev); | 320 | res = misc_register(&ibwdt_miscdev); |
| 326 | if (res) { | 321 | if (res) { |
| 327 | printk (KERN_ERR PFX "failed to register misc device\n"); | 322 | printk(KERN_ERR PFX "failed to register misc device\n"); |
| 328 | goto out_nomisc; | 323 | goto out_nomisc; |
| 329 | } | 324 | } |
| 330 | return 0; | 325 | return 0; |
| @@ -342,9 +337,9 @@ out_nostopreg: | |||
| 342 | static int __devexit ibwdt_remove(struct platform_device *dev) | 337 | static int __devexit ibwdt_remove(struct platform_device *dev) |
| 343 | { | 338 | { |
| 344 | misc_deregister(&ibwdt_miscdev); | 339 | misc_deregister(&ibwdt_miscdev); |
| 345 | release_region(WDT_START,1); | 340 | release_region(WDT_START, 1); |
| 346 | #if WDT_START != WDT_STOP | 341 | #if WDT_START != WDT_STOP |
| 347 | release_region(WDT_STOP,1); | 342 | release_region(WDT_STOP, 1); |
| 348 | #endif | 343 | #endif |
| 349 | return 0; | 344 | return 0; |
| 350 | } | 345 | } |
| @@ -369,13 +364,15 @@ static int __init ibwdt_init(void) | |||
| 369 | { | 364 | { |
| 370 | int err; | 365 | int err; |
| 371 | 366 | ||
| 372 | printk(KERN_INFO PFX "WDT driver for IB700 single board computer initialising.\n"); | 367 | printk(KERN_INFO PFX |
| 368 | "WDT driver for IB700 single board computer initialising.\n"); | ||
| 373 | 369 | ||
| 374 | err = platform_driver_register(&ibwdt_driver); | 370 | err = platform_driver_register(&ibwdt_driver); |
| 375 | if (err) | 371 | if (err) |
| 376 | return err; | 372 | return err; |
| 377 | 373 | ||
| 378 | ibwdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); | 374 | ibwdt_platform_device = platform_device_register_simple(DRV_NAME, |
| 375 | -1, NULL, 0); | ||
| 379 | if (IS_ERR(ibwdt_platform_device)) { | 376 | if (IS_ERR(ibwdt_platform_device)) { |
| 380 | err = PTR_ERR(ibwdt_platform_device); | 377 | err = PTR_ERR(ibwdt_platform_device); |
| 381 | goto unreg_platform_driver; | 378 | goto unreg_platform_driver; |
diff --git a/drivers/watchdog/ibmasr.c b/drivers/watchdog/ibmasr.c index 94155f6136c2..b82405cfb4cd 100644 --- a/drivers/watchdog/ibmasr.c +++ b/drivers/watchdog/ibmasr.c | |||
| @@ -19,9 +19,8 @@ | |||
| 19 | #include <linux/miscdevice.h> | 19 | #include <linux/miscdevice.h> |
| 20 | #include <linux/watchdog.h> | 20 | #include <linux/watchdog.h> |
| 21 | #include <linux/dmi.h> | 21 | #include <linux/dmi.h> |
| 22 | 22 | #include <linux/io.h> | |
| 23 | #include <asm/io.h> | 23 | #include <linux/uaccess.h> |
| 24 | #include <asm/uaccess.h> | ||
| 25 | 24 | ||
| 26 | 25 | ||
| 27 | enum { | 26 | enum { |
| @@ -70,10 +69,13 @@ static char asr_expect_close; | |||
| 70 | static unsigned int asr_type, asr_base, asr_length; | 69 | static unsigned int asr_type, asr_base, asr_length; |
| 71 | static unsigned int asr_read_addr, asr_write_addr; | 70 | static unsigned int asr_read_addr, asr_write_addr; |
| 72 | static unsigned char asr_toggle_mask, asr_disable_mask; | 71 | static unsigned char asr_toggle_mask, asr_disable_mask; |
| 72 | static spinlock_t asr_lock; | ||
| 73 | 73 | ||
| 74 | static void asr_toggle(void) | 74 | static void __asr_toggle(void) |
| 75 | { | 75 | { |
| 76 | unsigned char reg = inb(asr_read_addr); | 76 | unsigned char reg; |
| 77 | |||
| 78 | reg = inb(asr_read_addr); | ||
| 77 | 79 | ||
| 78 | outb(reg & ~asr_toggle_mask, asr_write_addr); | 80 | outb(reg & ~asr_toggle_mask, asr_write_addr); |
| 79 | reg = inb(asr_read_addr); | 81 | reg = inb(asr_read_addr); |
| @@ -83,12 +85,21 @@ static void asr_toggle(void) | |||
| 83 | 85 | ||
| 84 | outb(reg & ~asr_toggle_mask, asr_write_addr); | 86 | outb(reg & ~asr_toggle_mask, asr_write_addr); |
| 85 | reg = inb(asr_read_addr); | 87 | reg = inb(asr_read_addr); |
| 88 | spin_unlock(&asr_lock); | ||
| 89 | } | ||
| 90 | |||
| 91 | static void asr_toggle(void) | ||
| 92 | { | ||
| 93 | spin_lock(&asr_lock); | ||
| 94 | __asr_toggle(); | ||
| 95 | spin_unlock(&asr_lock); | ||
| 86 | } | 96 | } |
| 87 | 97 | ||
| 88 | static void asr_enable(void) | 98 | static void asr_enable(void) |
| 89 | { | 99 | { |
| 90 | unsigned char reg; | 100 | unsigned char reg; |
| 91 | 101 | ||
| 102 | spin_lock(&asr_lock); | ||
| 92 | if (asr_type == ASMTYPE_TOPAZ) { | 103 | if (asr_type == ASMTYPE_TOPAZ) { |
| 93 | /* asr_write_addr == asr_read_addr */ | 104 | /* asr_write_addr == asr_read_addr */ |
| 94 | reg = inb(asr_read_addr); | 105 | reg = inb(asr_read_addr); |
| @@ -99,17 +110,21 @@ static void asr_enable(void) | |||
| 99 | * First make sure the hardware timer is reset by toggling | 110 | * First make sure the hardware timer is reset by toggling |
| 100 | * ASR hardware timer line. | 111 | * ASR hardware timer line. |
| 101 | */ | 112 | */ |
| 102 | asr_toggle(); | 113 | __asr_toggle(); |
| 103 | 114 | ||
| 104 | reg = inb(asr_read_addr); | 115 | reg = inb(asr_read_addr); |
| 105 | outb(reg & ~asr_disable_mask, asr_write_addr); | 116 | outb(reg & ~asr_disable_mask, asr_write_addr); |
| 106 | } | 117 | } |
| 107 | reg = inb(asr_read_addr); | 118 | reg = inb(asr_read_addr); |
| 119 | spin_unlock(&asr_lock); | ||
| 108 | } | 120 | } |
| 109 | 121 | ||
| 110 | static void asr_disable(void) | 122 | static void asr_disable(void) |
| 111 | { | 123 | { |
| 112 | unsigned char reg = inb(asr_read_addr); | 124 | unsigned char reg; |
| 125 | |||
| 126 | spin_lock(&asr_lock); | ||
| 127 | reg = inb(asr_read_addr); | ||
| 113 | 128 | ||
| 114 | if (asr_type == ASMTYPE_TOPAZ) | 129 | if (asr_type == ASMTYPE_TOPAZ) |
| 115 | /* asr_write_addr == asr_read_addr */ | 130 | /* asr_write_addr == asr_read_addr */ |
| @@ -122,6 +137,7 @@ static void asr_disable(void) | |||
| 122 | outb(reg | asr_disable_mask, asr_write_addr); | 137 | outb(reg | asr_disable_mask, asr_write_addr); |
| 123 | } | 138 | } |
| 124 | reg = inb(asr_read_addr); | 139 | reg = inb(asr_read_addr); |
| 140 | spin_unlock(&asr_lock); | ||
| 125 | } | 141 | } |
| 126 | 142 | ||
| 127 | static int __init asr_get_base_address(void) | 143 | static int __init asr_get_base_address(void) |
| @@ -133,7 +149,8 @@ static int __init asr_get_base_address(void) | |||
| 133 | 149 | ||
| 134 | switch (asr_type) { | 150 | switch (asr_type) { |
| 135 | case ASMTYPE_TOPAZ: | 151 | case ASMTYPE_TOPAZ: |
| 136 | /* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E and 0x2F) */ | 152 | /* SELECT SuperIO CHIP FOR QUERYING |
| 153 | (WRITE 0x07 TO BOTH 0x2E and 0x2F) */ | ||
| 137 | outb(0x07, 0x2e); | 154 | outb(0x07, 0x2e); |
| 138 | outb(0x07, 0x2f); | 155 | outb(0x07, 0x2f); |
| 139 | 156 | ||
| @@ -154,14 +171,26 @@ static int __init asr_get_base_address(void) | |||
| 154 | 171 | ||
| 155 | case ASMTYPE_JASPER: | 172 | case ASMTYPE_JASPER: |
| 156 | type = "Jaspers "; | 173 | type = "Jaspers "; |
| 157 | 174 | #if 0 | |
| 158 | /* FIXME: need to use pci_config_lock here, but it's not exported */ | 175 | u32 r; |
| 176 | /* Suggested fix */ | ||
| 177 | pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0)); | ||
| 178 | if (pdev == NULL) | ||
| 179 | return -ENODEV; | ||
| 180 | pci_read_config_dword(pdev, 0x58, &r); | ||
| 181 | asr_base = r & 0xFFFE; | ||
| 182 | pci_dev_put(pdev); | ||
| 183 | #else | ||
| 184 | /* FIXME: need to use pci_config_lock here, | ||
| 185 | but it's not exported */ | ||
| 159 | 186 | ||
| 160 | /* spin_lock_irqsave(&pci_config_lock, flags);*/ | 187 | /* spin_lock_irqsave(&pci_config_lock, flags);*/ |
| 161 | 188 | ||
| 162 | /* Select the SuperIO chip in the PCI I/O port register */ | 189 | /* Select the SuperIO chip in the PCI I/O port register */ |
| 163 | outl(0x8000f858, 0xcf8); | 190 | outl(0x8000f858, 0xcf8); |
| 164 | 191 | ||
| 192 | /* BUS 0, Slot 1F, fnc 0, offset 58 */ | ||
| 193 | |||
| 165 | /* | 194 | /* |
| 166 | * Read the base address for the SuperIO chip. | 195 | * Read the base address for the SuperIO chip. |
| 167 | * Only the lower 16 bits are valid, but the address is word | 196 | * Only the lower 16 bits are valid, but the address is word |
| @@ -170,7 +199,7 @@ static int __init asr_get_base_address(void) | |||
| 170 | asr_base = inl(0xcfc) & 0xfffe; | 199 | asr_base = inl(0xcfc) & 0xfffe; |
| 171 | 200 | ||
| 172 | /* spin_unlock_irqrestore(&pci_config_lock, flags);*/ | 201 | /* spin_unlock_irqrestore(&pci_config_lock, flags);*/ |
| 173 | 202 | #endif | |
| 174 | asr_read_addr = asr_write_addr = | 203 | asr_read_addr = asr_write_addr = |
| 175 | asr_base + JASPER_ASR_REG_OFFSET; | 204 | asr_base + JASPER_ASR_REG_OFFSET; |
| 176 | asr_toggle_mask = JASPER_ASR_TOGGLE_MASK; | 205 | asr_toggle_mask = JASPER_ASR_TOGGLE_MASK; |
| @@ -241,66 +270,57 @@ static ssize_t asr_write(struct file *file, const char __user *buf, | |||
| 241 | return count; | 270 | return count; |
| 242 | } | 271 | } |
| 243 | 272 | ||
| 244 | static int asr_ioctl(struct inode *inode, struct file *file, | 273 | static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 245 | unsigned int cmd, unsigned long arg) | ||
| 246 | { | 274 | { |
| 247 | static const struct watchdog_info ident = { | 275 | static const struct watchdog_info ident = { |
| 248 | .options = WDIOF_KEEPALIVEPING | | 276 | .options = WDIOF_KEEPALIVEPING | |
| 249 | WDIOF_MAGICCLOSE, | 277 | WDIOF_MAGICCLOSE, |
| 250 | .identity = "IBM ASR" | 278 | .identity = "IBM ASR", |
| 251 | }; | 279 | }; |
| 252 | void __user *argp = (void __user *)arg; | 280 | void __user *argp = (void __user *)arg; |
| 253 | int __user *p = argp; | 281 | int __user *p = argp; |
| 254 | int heartbeat; | 282 | int heartbeat; |
| 255 | 283 | ||
| 256 | switch (cmd) { | 284 | switch (cmd) { |
| 257 | case WDIOC_GETSUPPORT: | 285 | case WDIOC_GETSUPPORT: |
| 258 | return copy_to_user(argp, &ident, sizeof(ident)) ? | 286 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 259 | -EFAULT : 0; | 287 | case WDIOC_GETSTATUS: |
| 260 | 288 | case WDIOC_GETBOOTSTATUS: | |
| 261 | case WDIOC_GETSTATUS: | 289 | return put_user(0, p); |
| 262 | case WDIOC_GETBOOTSTATUS: | 290 | case WDIOC_SETOPTIONS: |
| 263 | return put_user(0, p); | 291 | { |
| 264 | 292 | int new_options, retval = -EINVAL; | |
| 265 | case WDIOC_KEEPALIVE: | 293 | if (get_user(new_options, p)) |
| 294 | return -EFAULT; | ||
| 295 | if (new_options & WDIOS_DISABLECARD) { | ||
| 296 | asr_disable(); | ||
| 297 | retval = 0; | ||
| 298 | } | ||
| 299 | if (new_options & WDIOS_ENABLECARD) { | ||
| 300 | asr_enable(); | ||
| 266 | asr_toggle(); | 301 | asr_toggle(); |
| 267 | return 0; | 302 | retval = 0; |
| 268 | |||
| 269 | /* | ||
| 270 | * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT | ||
| 271 | * and WDIOC_GETTIMEOUT always returns 256. | ||
| 272 | */ | ||
| 273 | case WDIOC_GETTIMEOUT: | ||
| 274 | heartbeat = 256; | ||
| 275 | return put_user(heartbeat, p); | ||
| 276 | |||
| 277 | case WDIOC_SETOPTIONS: { | ||
| 278 | int new_options, retval = -EINVAL; | ||
| 279 | |||
| 280 | if (get_user(new_options, p)) | ||
| 281 | return -EFAULT; | ||
| 282 | |||
| 283 | if (new_options & WDIOS_DISABLECARD) { | ||
| 284 | asr_disable(); | ||
| 285 | retval = 0; | ||
| 286 | } | ||
| 287 | |||
| 288 | if (new_options & WDIOS_ENABLECARD) { | ||
| 289 | asr_enable(); | ||
| 290 | asr_toggle(); | ||
| 291 | retval = 0; | ||
| 292 | } | ||
| 293 | |||
| 294 | return retval; | ||
| 295 | } | 303 | } |
| 304 | return retval; | ||
| 305 | } | ||
| 306 | case WDIOC_KEEPALIVE: | ||
| 307 | asr_toggle(); | ||
| 308 | return 0; | ||
| 309 | /* | ||
| 310 | * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT | ||
| 311 | * and WDIOC_GETTIMEOUT always returns 256. | ||
| 312 | */ | ||
| 313 | case WDIOC_GETTIMEOUT: | ||
| 314 | heartbeat = 256; | ||
| 315 | return put_user(heartbeat, p); | ||
| 316 | default: | ||
| 317 | return -ENOTTY; | ||
| 296 | } | 318 | } |
| 297 | |||
| 298 | return -ENOTTY; | ||
| 299 | } | 319 | } |
| 300 | 320 | ||
| 301 | static int asr_open(struct inode *inode, struct file *file) | 321 | static int asr_open(struct inode *inode, struct file *file) |
| 302 | { | 322 | { |
| 303 | if(test_and_set_bit(0, &asr_is_open)) | 323 | if (test_and_set_bit(0, &asr_is_open)) |
| 304 | return -EBUSY; | 324 | return -EBUSY; |
| 305 | 325 | ||
| 306 | asr_toggle(); | 326 | asr_toggle(); |
| @@ -314,7 +334,8 @@ static int asr_release(struct inode *inode, struct file *file) | |||
| 314 | if (asr_expect_close == 42) | 334 | if (asr_expect_close == 42) |
| 315 | asr_disable(); | 335 | asr_disable(); |
| 316 | else { | 336 | else { |
| 317 | printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n"); | 337 | printk(KERN_CRIT PFX |
| 338 | "unexpected close, not stopping watchdog!\n"); | ||
| 318 | asr_toggle(); | 339 | asr_toggle(); |
| 319 | } | 340 | } |
| 320 | clear_bit(0, &asr_is_open); | 341 | clear_bit(0, &asr_is_open); |
| @@ -323,12 +344,12 @@ static int asr_release(struct inode *inode, struct file *file) | |||
| 323 | } | 344 | } |
| 324 | 345 | ||
| 325 | static const struct file_operations asr_fops = { | 346 | static const struct file_operations asr_fops = { |
| 326 | .owner = THIS_MODULE, | 347 | .owner = THIS_MODULE, |
| 327 | .llseek = no_llseek, | 348 | .llseek = no_llseek, |
| 328 | .write = asr_write, | 349 | .write = asr_write, |
| 329 | .ioctl = asr_ioctl, | 350 | .unlocked_ioctl = asr_ioctl, |
| 330 | .open = asr_open, | 351 | .open = asr_open, |
| 331 | .release = asr_release, | 352 | .release = asr_release, |
| 332 | }; | 353 | }; |
| 333 | 354 | ||
| 334 | static struct miscdevice asr_miscdev = { | 355 | static struct miscdevice asr_miscdev = { |
| @@ -367,6 +388,8 @@ static int __init ibmasr_init(void) | |||
| 367 | if (!asr_type) | 388 | if (!asr_type) |
| 368 | return -ENODEV; | 389 | return -ENODEV; |
| 369 | 390 | ||
| 391 | spin_lock_init(&asr_lock); | ||
| 392 | |||
| 370 | rc = asr_get_base_address(); | 393 | rc = asr_get_base_address(); |
| 371 | if (rc) | 394 | if (rc) |
| 372 | return rc; | 395 | return rc; |
| @@ -395,7 +418,9 @@ module_init(ibmasr_init); | |||
| 395 | module_exit(ibmasr_exit); | 418 | module_exit(ibmasr_exit); |
| 396 | 419 | ||
| 397 | module_param(nowayout, int, 0); | 420 | module_param(nowayout, int, 0); |
| 398 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 421 | MODULE_PARM_DESC(nowayout, |
| 422 | "Watchdog cannot be stopped once started (default=" | ||
| 423 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 399 | 424 | ||
| 400 | MODULE_DESCRIPTION("IBM Automatic Server Restart driver"); | 425 | MODULE_DESCRIPTION("IBM Automatic Server Restart driver"); |
| 401 | MODULE_AUTHOR("Andrey Panin"); | 426 | MODULE_AUTHOR("Andrey Panin"); |
diff --git a/drivers/watchdog/indydog.c b/drivers/watchdog/indydog.c index 788245bdaa7f..73c9e7992feb 100644 --- a/drivers/watchdog/indydog.c +++ b/drivers/watchdog/indydog.c | |||
| @@ -1,7 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * IndyDog 0.3 A Hardware Watchdog Device for SGI IP22 | 2 | * IndyDog 0.3 A Hardware Watchdog Device for SGI IP22 |
| 3 | * | 3 | * |
| 4 | * (c) Copyright 2002 Guido Guenther <agx@sigxcpu.org>, All Rights Reserved. | 4 | * (c) Copyright 2002 Guido Guenther <agx@sigxcpu.org>, |
| 5 | * All Rights Reserved. | ||
| 5 | * | 6 | * |
| 6 | * This program is free software; you can redistribute it and/or | 7 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License | 8 | * modify it under the terms of the GNU General Public License |
| @@ -22,32 +23,42 @@ | |||
| 22 | #include <linux/notifier.h> | 23 | #include <linux/notifier.h> |
| 23 | #include <linux/reboot.h> | 24 | #include <linux/reboot.h> |
| 24 | #include <linux/init.h> | 25 | #include <linux/init.h> |
| 25 | #include <asm/uaccess.h> | 26 | #include <linux/uaccess.h> |
| 26 | #include <asm/sgi/mc.h> | 27 | #include <asm/sgi/mc.h> |
| 27 | 28 | ||
| 28 | #define PFX "indydog: " | 29 | #define PFX "indydog: " |
| 29 | static int indydog_alive; | 30 | static unsigned long indydog_alive; |
| 31 | static spinlock_t indydog_lock; | ||
| 30 | 32 | ||
| 31 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ | 33 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ |
| 32 | 34 | ||
| 33 | static int nowayout = WATCHDOG_NOWAYOUT; | 35 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 34 | module_param(nowayout, int, 0); | 36 | module_param(nowayout, int, 0); |
| 35 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 37 | MODULE_PARM_DESC(nowayout, |
| 38 | "Watchdog cannot be stopped once started (default=" | ||
| 39 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 36 | 40 | ||
| 37 | static void indydog_start(void) | 41 | static void indydog_start(void) |
| 38 | { | 42 | { |
| 39 | u32 mc_ctrl0 = sgimc->cpuctrl0; | 43 | u32 mc_ctrl0; |
| 40 | 44 | ||
| 45 | spin_lock(&indydog_lock); | ||
| 46 | mc_ctrl0 = sgimc->cpuctrl0; | ||
| 41 | mc_ctrl0 = sgimc->cpuctrl0 | SGIMC_CCTRL0_WDOG; | 47 | mc_ctrl0 = sgimc->cpuctrl0 | SGIMC_CCTRL0_WDOG; |
| 42 | sgimc->cpuctrl0 = mc_ctrl0; | 48 | sgimc->cpuctrl0 = mc_ctrl0; |
| 49 | spin_unlock(&indydog_lock); | ||
| 43 | } | 50 | } |
| 44 | 51 | ||
| 45 | static void indydog_stop(void) | 52 | static void indydog_stop(void) |
| 46 | { | 53 | { |
| 47 | u32 mc_ctrl0 = sgimc->cpuctrl0; | 54 | u32 mc_ctrl0; |
| 48 | 55 | ||
| 56 | spin_lock(&indydog_lock); | ||
| 57 | |||
| 58 | mc_ctrl0 = sgimc->cpuctrl0; | ||
| 49 | mc_ctrl0 &= ~SGIMC_CCTRL0_WDOG; | 59 | mc_ctrl0 &= ~SGIMC_CCTRL0_WDOG; |
| 50 | sgimc->cpuctrl0 = mc_ctrl0; | 60 | sgimc->cpuctrl0 = mc_ctrl0; |
| 61 | spin_unlock(&indydog_lock); | ||
| 51 | 62 | ||
| 52 | printk(KERN_INFO PFX "Stopped watchdog timer.\n"); | 63 | printk(KERN_INFO PFX "Stopped watchdog timer.\n"); |
| 53 | } | 64 | } |
| @@ -62,7 +73,7 @@ static void indydog_ping(void) | |||
| 62 | */ | 73 | */ |
| 63 | static int indydog_open(struct inode *inode, struct file *file) | 74 | static int indydog_open(struct inode *inode, struct file *file) |
| 64 | { | 75 | { |
| 65 | if (indydog_alive) | 76 | if (test_and_set_bit(0, &indydog_alive)) |
| 66 | return -EBUSY; | 77 | return -EBUSY; |
| 67 | 78 | ||
| 68 | if (nowayout) | 79 | if (nowayout) |
| @@ -84,23 +95,21 @@ static int indydog_release(struct inode *inode, struct file *file) | |||
| 84 | * Lock it in if it's a module and we defined ...NOWAYOUT */ | 95 | * Lock it in if it's a module and we defined ...NOWAYOUT */ |
| 85 | if (!nowayout) | 96 | if (!nowayout) |
| 86 | indydog_stop(); /* Turn the WDT off */ | 97 | indydog_stop(); /* Turn the WDT off */ |
| 87 | 98 | clear_bit(0, &indydog_alive); | |
| 88 | indydog_alive = 0; | ||
| 89 | |||
| 90 | return 0; | 99 | return 0; |
| 91 | } | 100 | } |
| 92 | 101 | ||
| 93 | static ssize_t indydog_write(struct file *file, const char *data, size_t len, loff_t *ppos) | 102 | static ssize_t indydog_write(struct file *file, const char *data, |
| 103 | size_t len, loff_t *ppos) | ||
| 94 | { | 104 | { |
| 95 | /* Refresh the timer. */ | 105 | /* Refresh the timer. */ |
| 96 | if (len) { | 106 | if (len) |
| 97 | indydog_ping(); | 107 | indydog_ping(); |
| 98 | } | ||
| 99 | return len; | 108 | return len; |
| 100 | } | 109 | } |
| 101 | 110 | ||
| 102 | static int indydog_ioctl(struct inode *inode, struct file *file, | 111 | static long indydog_ioctl(struct file *file, unsigned int cmd, |
| 103 | unsigned int cmd, unsigned long arg) | 112 | unsigned long arg) |
| 104 | { | 113 | { |
| 105 | int options, retval = -EINVAL; | 114 | int options, retval = -EINVAL; |
| 106 | static struct watchdog_info ident = { | 115 | static struct watchdog_info ident = { |
| @@ -111,42 +120,40 @@ static int indydog_ioctl(struct inode *inode, struct file *file, | |||
| 111 | }; | 120 | }; |
| 112 | 121 | ||
| 113 | switch (cmd) { | 122 | switch (cmd) { |
| 114 | default: | 123 | case WDIOC_GETSUPPORT: |
| 115 | return -ENOTTY; | 124 | if (copy_to_user((struct watchdog_info *)arg, |
| 116 | case WDIOC_GETSUPPORT: | 125 | &ident, sizeof(ident))) |
| 117 | if (copy_to_user((struct watchdog_info *)arg, | 126 | return -EFAULT; |
| 118 | &ident, sizeof(ident))) | 127 | return 0; |
| 119 | return -EFAULT; | 128 | case WDIOC_GETSTATUS: |
| 120 | return 0; | 129 | case WDIOC_GETBOOTSTATUS: |
| 121 | case WDIOC_GETSTATUS: | 130 | return put_user(0, (int *)arg); |
| 122 | case WDIOC_GETBOOTSTATUS: | 131 | case WDIOC_SETOPTIONS: |
| 123 | return put_user(0,(int *)arg); | 132 | { |
| 124 | case WDIOC_KEEPALIVE: | 133 | if (get_user(options, (int *)arg)) |
| 125 | indydog_ping(); | 134 | return -EFAULT; |
| 126 | return 0; | 135 | if (options & WDIOS_DISABLECARD) { |
| 127 | case WDIOC_GETTIMEOUT: | 136 | indydog_stop(); |
| 128 | return put_user(WATCHDOG_TIMEOUT,(int *)arg); | 137 | retval = 0; |
| 129 | case WDIOC_SETOPTIONS: | ||
| 130 | { | ||
| 131 | if (get_user(options, (int *)arg)) | ||
| 132 | return -EFAULT; | ||
| 133 | |||
| 134 | if (options & WDIOS_DISABLECARD) { | ||
| 135 | indydog_stop(); | ||
| 136 | retval = 0; | ||
| 137 | } | ||
| 138 | |||
| 139 | if (options & WDIOS_ENABLECARD) { | ||
| 140 | indydog_start(); | ||
| 141 | retval = 0; | ||
| 142 | } | ||
| 143 | |||
| 144 | return retval; | ||
| 145 | } | 138 | } |
| 139 | if (options & WDIOS_ENABLECARD) { | ||
| 140 | indydog_start(); | ||
| 141 | retval = 0; | ||
| 142 | } | ||
| 143 | return retval; | ||
| 144 | } | ||
| 145 | case WDIOC_KEEPALIVE: | ||
| 146 | indydog_ping(); | ||
| 147 | return 0; | ||
| 148 | case WDIOC_GETTIMEOUT: | ||
| 149 | return put_user(WATCHDOG_TIMEOUT, (int *)arg); | ||
| 150 | default: | ||
| 151 | return -ENOTTY; | ||
| 146 | } | 152 | } |
| 147 | } | 153 | } |
| 148 | 154 | ||
| 149 | static int indydog_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 155 | static int indydog_notify_sys(struct notifier_block *this, |
| 156 | unsigned long code, void *unused) | ||
| 150 | { | 157 | { |
| 151 | if (code == SYS_DOWN || code == SYS_HALT) | 158 | if (code == SYS_DOWN || code == SYS_HALT) |
| 152 | indydog_stop(); /* Turn the WDT off */ | 159 | indydog_stop(); /* Turn the WDT off */ |
| @@ -158,7 +165,7 @@ static const struct file_operations indydog_fops = { | |||
| 158 | .owner = THIS_MODULE, | 165 | .owner = THIS_MODULE, |
| 159 | .llseek = no_llseek, | 166 | .llseek = no_llseek, |
| 160 | .write = indydog_write, | 167 | .write = indydog_write, |
| 161 | .ioctl = indydog_ioctl, | 168 | .unlocked_ioctl = indydog_ioctl, |
| 162 | .open = indydog_open, | 169 | .open = indydog_open, |
| 163 | .release = indydog_release, | 170 | .release = indydog_release, |
| 164 | }; | 171 | }; |
| @@ -180,17 +187,20 @@ static int __init watchdog_init(void) | |||
| 180 | { | 187 | { |
| 181 | int ret; | 188 | int ret; |
| 182 | 189 | ||
| 190 | spin_lock_init(&indydog_lock); | ||
| 191 | |||
| 183 | ret = register_reboot_notifier(&indydog_notifier); | 192 | ret = register_reboot_notifier(&indydog_notifier); |
| 184 | if (ret) { | 193 | if (ret) { |
| 185 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 194 | printk(KERN_ERR PFX |
| 186 | ret); | 195 | "cannot register reboot notifier (err=%d)\n", ret); |
| 187 | return ret; | 196 | return ret; |
| 188 | } | 197 | } |
| 189 | 198 | ||
| 190 | ret = misc_register(&indydog_miscdev); | 199 | ret = misc_register(&indydog_miscdev); |
| 191 | if (ret) { | 200 | if (ret) { |
| 192 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 201 | printk(KERN_ERR PFX |
| 193 | WATCHDOG_MINOR, ret); | 202 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 203 | WATCHDOG_MINOR, ret); | ||
| 194 | unregister_reboot_notifier(&indydog_notifier); | 204 | unregister_reboot_notifier(&indydog_notifier); |
| 195 | return ret; | 205 | return ret; |
| 196 | } | 206 | } |
diff --git a/drivers/watchdog/iop_wdt.c b/drivers/watchdog/iop_wdt.c index 1946dd06d815..96eb2cbe5874 100644 --- a/drivers/watchdog/iop_wdt.c +++ b/drivers/watchdog/iop_wdt.c | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | static int nowayout = WATCHDOG_NOWAYOUT; | 37 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 38 | static unsigned long wdt_status; | 38 | static unsigned long wdt_status; |
| 39 | static unsigned long boot_status; | 39 | static unsigned long boot_status; |
| 40 | static spinlock_t wdt_lock; | ||
| 40 | 41 | ||
| 41 | #define WDT_IN_USE 0 | 42 | #define WDT_IN_USE 0 |
| 42 | #define WDT_OK_TO_CLOSE 1 | 43 | #define WDT_OK_TO_CLOSE 1 |
| @@ -68,8 +69,10 @@ static void wdt_enable(void) | |||
| 68 | /* Arm and enable the Timer to starting counting down from 0xFFFF.FFFF | 69 | /* Arm and enable the Timer to starting counting down from 0xFFFF.FFFF |
| 69 | * Takes approx. 10.7s to timeout | 70 | * Takes approx. 10.7s to timeout |
| 70 | */ | 71 | */ |
| 72 | spin_lock(&wdt_lock); | ||
| 71 | write_wdtcr(IOP_WDTCR_EN_ARM); | 73 | write_wdtcr(IOP_WDTCR_EN_ARM); |
| 72 | write_wdtcr(IOP_WDTCR_EN); | 74 | write_wdtcr(IOP_WDTCR_EN); |
| 75 | spin_unlock(&wdt_lock); | ||
| 73 | } | 76 | } |
| 74 | 77 | ||
| 75 | /* returns 0 if the timer was successfully disabled */ | 78 | /* returns 0 if the timer was successfully disabled */ |
| @@ -77,9 +80,11 @@ static int wdt_disable(void) | |||
| 77 | { | 80 | { |
| 78 | /* Stop Counting */ | 81 | /* Stop Counting */ |
| 79 | if (wdt_supports_disable()) { | 82 | if (wdt_supports_disable()) { |
| 83 | spin_lock(&wdt_lock); | ||
| 80 | write_wdtcr(IOP_WDTCR_DIS_ARM); | 84 | write_wdtcr(IOP_WDTCR_DIS_ARM); |
| 81 | write_wdtcr(IOP_WDTCR_DIS); | 85 | write_wdtcr(IOP_WDTCR_DIS); |
| 82 | clear_bit(WDT_ENABLED, &wdt_status); | 86 | clear_bit(WDT_ENABLED, &wdt_status); |
| 87 | spin_unlock(&wdt_lock); | ||
| 83 | printk(KERN_INFO "WATCHDOG: Disabled\n"); | 88 | printk(KERN_INFO "WATCHDOG: Disabled\n"); |
| 84 | return 0; | 89 | return 0; |
| 85 | } else | 90 | } else |
| @@ -92,16 +97,12 @@ static int iop_wdt_open(struct inode *inode, struct file *file) | |||
| 92 | return -EBUSY; | 97 | return -EBUSY; |
| 93 | 98 | ||
| 94 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 99 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| 95 | |||
| 96 | wdt_enable(); | 100 | wdt_enable(); |
| 97 | |||
| 98 | set_bit(WDT_ENABLED, &wdt_status); | 101 | set_bit(WDT_ENABLED, &wdt_status); |
| 99 | |||
| 100 | return nonseekable_open(inode, file); | 102 | return nonseekable_open(inode, file); |
| 101 | } | 103 | } |
| 102 | 104 | ||
| 103 | static ssize_t | 105 | static ssize_t iop_wdt_write(struct file *file, const char *data, size_t len, |
| 104 | iop_wdt_write(struct file *file, const char *data, size_t len, | ||
| 105 | loff_t *ppos) | 106 | loff_t *ppos) |
| 106 | { | 107 | { |
| 107 | if (len) { | 108 | if (len) { |
| @@ -121,46 +122,35 @@ iop_wdt_write(struct file *file, const char *data, size_t len, | |||
| 121 | } | 122 | } |
| 122 | wdt_enable(); | 123 | wdt_enable(); |
| 123 | } | 124 | } |
| 124 | |||
| 125 | return len; | 125 | return len; |
| 126 | } | 126 | } |
| 127 | 127 | ||
| 128 | static struct watchdog_info ident = { | 128 | static const struct watchdog_info ident = { |
| 129 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, | 129 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
| 130 | .identity = "iop watchdog", | 130 | .identity = "iop watchdog", |
| 131 | }; | 131 | }; |
| 132 | 132 | ||
| 133 | static int | 133 | static long iop_wdt_ioctl(struct file *file, |
| 134 | iop_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 134 | unsigned int cmd, unsigned long arg) |
| 135 | unsigned long arg) | ||
| 136 | { | 135 | { |
| 137 | int options; | 136 | int options; |
| 138 | int ret = -ENOTTY; | 137 | int ret = -ENOTTY; |
| 138 | int __user *argp = (int __user *)arg; | ||
| 139 | 139 | ||
| 140 | switch (cmd) { | 140 | switch (cmd) { |
| 141 | case WDIOC_GETSUPPORT: | 141 | case WDIOC_GETSUPPORT: |
| 142 | if (copy_to_user | 142 | if (copy_to_user(argp, &ident, sizeof ident)) |
| 143 | ((struct watchdog_info *)arg, &ident, sizeof ident)) | ||
| 144 | ret = -EFAULT; | 143 | ret = -EFAULT; |
| 145 | else | 144 | else |
| 146 | ret = 0; | 145 | ret = 0; |
| 147 | break; | 146 | break; |
| 148 | 147 | ||
| 149 | case WDIOC_GETSTATUS: | 148 | case WDIOC_GETSTATUS: |
| 150 | ret = put_user(0, (int *)arg); | 149 | ret = put_user(0, argp); |
| 151 | break; | 150 | break; |
| 152 | 151 | ||
| 153 | case WDIOC_GETBOOTSTATUS: | 152 | case WDIOC_GETBOOTSTATUS: |
| 154 | ret = put_user(boot_status, (int *)arg); | 153 | ret = put_user(boot_status, argp); |
| 155 | break; | ||
| 156 | |||
| 157 | case WDIOC_GETTIMEOUT: | ||
| 158 | ret = put_user(iop_watchdog_timeout(), (int *)arg); | ||
| 159 | break; | ||
| 160 | |||
| 161 | case WDIOC_KEEPALIVE: | ||
| 162 | wdt_enable(); | ||
| 163 | ret = 0; | ||
| 164 | break; | 154 | break; |
| 165 | 155 | ||
| 166 | case WDIOC_SETOPTIONS: | 156 | case WDIOC_SETOPTIONS: |
| @@ -177,14 +167,21 @@ iop_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 177 | } else | 167 | } else |
| 178 | ret = 0; | 168 | ret = 0; |
| 179 | } | 169 | } |
| 180 | |||
| 181 | if (options & WDIOS_ENABLECARD) { | 170 | if (options & WDIOS_ENABLECARD) { |
| 182 | wdt_enable(); | 171 | wdt_enable(); |
| 183 | ret = 0; | 172 | ret = 0; |
| 184 | } | 173 | } |
| 185 | break; | 174 | break; |
| 186 | } | ||
| 187 | 175 | ||
| 176 | case WDIOC_KEEPALIVE: | ||
| 177 | wdt_enable(); | ||
| 178 | ret = 0; | ||
| 179 | break; | ||
| 180 | |||
| 181 | case WDIOC_GETTIMEOUT: | ||
| 182 | ret = put_user(iop_watchdog_timeout(), argp); | ||
| 183 | break; | ||
| 184 | } | ||
| 188 | return ret; | 185 | return ret; |
| 189 | } | 186 | } |
| 190 | 187 | ||
| @@ -214,7 +211,7 @@ static const struct file_operations iop_wdt_fops = { | |||
| 214 | .owner = THIS_MODULE, | 211 | .owner = THIS_MODULE, |
| 215 | .llseek = no_llseek, | 212 | .llseek = no_llseek, |
| 216 | .write = iop_wdt_write, | 213 | .write = iop_wdt_write, |
| 217 | .ioctl = iop_wdt_ioctl, | 214 | .unlocked_ioctl = iop_wdt_ioctl, |
| 218 | .open = iop_wdt_open, | 215 | .open = iop_wdt_open, |
| 219 | .release = iop_wdt_release, | 216 | .release = iop_wdt_release, |
| 220 | }; | 217 | }; |
| @@ -229,10 +226,8 @@ static int __init iop_wdt_init(void) | |||
| 229 | { | 226 | { |
| 230 | int ret; | 227 | int ret; |
| 231 | 228 | ||
| 232 | ret = misc_register(&iop_wdt_miscdev); | 229 | spin_lock_init(&wdt_lock); |
| 233 | if (ret == 0) | 230 | |
| 234 | printk("iop watchdog timer: timeout %lu sec\n", | ||
| 235 | iop_watchdog_timeout()); | ||
| 236 | 231 | ||
| 237 | /* check if the reset was caused by the watchdog timer */ | 232 | /* check if the reset was caused by the watchdog timer */ |
| 238 | boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0; | 233 | boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0; |
| @@ -242,6 +237,13 @@ static int __init iop_wdt_init(void) | |||
| 242 | */ | 237 | */ |
| 243 | write_wdtsr(IOP13XX_WDTCR_IB_RESET); | 238 | write_wdtsr(IOP13XX_WDTCR_IB_RESET); |
| 244 | 239 | ||
| 240 | /* Register after we have the device set up so we cannot race | ||
| 241 | with an open */ | ||
| 242 | ret = misc_register(&iop_wdt_miscdev); | ||
| 243 | if (ret == 0) | ||
| 244 | printk(KERN_INFO "iop watchdog timer: timeout %lu sec\n", | ||
| 245 | iop_watchdog_timeout()); | ||
| 246 | |||
| 245 | return ret; | 247 | return ret; |
| 246 | } | 248 | } |
| 247 | 249 | ||
diff --git a/drivers/watchdog/it8712f_wdt.c b/drivers/watchdog/it8712f_wdt.c index 51bfd5721833..2270ee07c01b 100644 --- a/drivers/watchdog/it8712f_wdt.c +++ b/drivers/watchdog/it8712f_wdt.c | |||
| @@ -221,7 +221,7 @@ static ssize_t it8712f_wdt_write(struct file *file, const char __user *data, | |||
| 221 | expect_close = 0; | 221 | expect_close = 0; |
| 222 | for (i = 0; i < len; ++i) { | 222 | for (i = 0; i < len; ++i) { |
| 223 | char c; | 223 | char c; |
| 224 | if (get_user(c, data+i)) | 224 | if (get_user(c, data + i)) |
| 225 | return -EFAULT; | 225 | return -EFAULT; |
| 226 | if (c == 'V') | 226 | if (c == 'V') |
| 227 | expect_close = 42; | 227 | expect_close = 42; |
| @@ -244,8 +244,6 @@ static long it8712f_wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 244 | int value; | 244 | int value; |
| 245 | 245 | ||
| 246 | switch (cmd) { | 246 | switch (cmd) { |
| 247 | default: | ||
| 248 | return -ENOTTY; | ||
| 249 | case WDIOC_GETSUPPORT: | 247 | case WDIOC_GETSUPPORT: |
| 250 | if (copy_to_user(argp, &ident, sizeof(ident))) | 248 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 251 | return -EFAULT; | 249 | return -EFAULT; |
| @@ -284,6 +282,8 @@ static long it8712f_wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 284 | if (put_user(margin, p)) | 282 | if (put_user(margin, p)) |
| 285 | return -EFAULT; | 283 | return -EFAULT; |
| 286 | return 0; | 284 | return 0; |
| 285 | default: | ||
| 286 | return -ENOTTY; | ||
| 287 | } | 287 | } |
| 288 | } | 288 | } |
| 289 | 289 | ||
diff --git a/drivers/watchdog/ixp2000_wdt.c b/drivers/watchdog/ixp2000_wdt.c index 4226dae7d260..4f4b35a20d84 100644 --- a/drivers/watchdog/ixp2000_wdt.c +++ b/drivers/watchdog/ixp2000_wdt.c | |||
| @@ -25,42 +25,44 @@ | |||
| 25 | #include <linux/watchdog.h> | 25 | #include <linux/watchdog.h> |
| 26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 27 | #include <linux/bitops.h> | 27 | #include <linux/bitops.h> |
| 28 | 28 | #include <linux/uaccess.h> | |
| 29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 30 | #include <asm/uaccess.h> | ||
| 31 | 30 | ||
| 32 | static int nowayout = WATCHDOG_NOWAYOUT; | 31 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 33 | static unsigned int heartbeat = 60; /* (secs) Default is 1 minute */ | 32 | static unsigned int heartbeat = 60; /* (secs) Default is 1 minute */ |
| 34 | static unsigned long wdt_status; | 33 | static unsigned long wdt_status; |
| 34 | static spinlock_t wdt_lock; | ||
| 35 | 35 | ||
| 36 | #define WDT_IN_USE 0 | 36 | #define WDT_IN_USE 0 |
| 37 | #define WDT_OK_TO_CLOSE 1 | 37 | #define WDT_OK_TO_CLOSE 1 |
| 38 | 38 | ||
| 39 | static unsigned long wdt_tick_rate; | 39 | static unsigned long wdt_tick_rate; |
| 40 | 40 | ||
| 41 | static void | 41 | static void wdt_enable(void) |
| 42 | wdt_enable(void) | ||
| 43 | { | 42 | { |
| 43 | spin_lock(&wdt_lock); | ||
| 44 | ixp2000_reg_write(IXP2000_RESET0, *(IXP2000_RESET0) | WDT_RESET_ENABLE); | 44 | ixp2000_reg_write(IXP2000_RESET0, *(IXP2000_RESET0) | WDT_RESET_ENABLE); |
| 45 | ixp2000_reg_write(IXP2000_TWDE, WDT_ENABLE); | 45 | ixp2000_reg_write(IXP2000_TWDE, WDT_ENABLE); |
| 46 | ixp2000_reg_write(IXP2000_T4_CLD, heartbeat * wdt_tick_rate); | 46 | ixp2000_reg_write(IXP2000_T4_CLD, heartbeat * wdt_tick_rate); |
| 47 | ixp2000_reg_write(IXP2000_T4_CTL, TIMER_DIVIDER_256 | TIMER_ENABLE); | 47 | ixp2000_reg_write(IXP2000_T4_CTL, TIMER_DIVIDER_256 | TIMER_ENABLE); |
| 48 | spin_unlock(&wdt_lock); | ||
| 48 | } | 49 | } |
| 49 | 50 | ||
| 50 | static void | 51 | static void wdt_disable(void) |
| 51 | wdt_disable(void) | ||
| 52 | { | 52 | { |
| 53 | spin_lock(&wdt_lock); | ||
| 53 | ixp2000_reg_write(IXP2000_T4_CTL, 0); | 54 | ixp2000_reg_write(IXP2000_T4_CTL, 0); |
| 55 | spin_unlock(&wdt_lock); | ||
| 54 | } | 56 | } |
| 55 | 57 | ||
| 56 | static void | 58 | static void wdt_keepalive(void) |
| 57 | wdt_keepalive(void) | ||
| 58 | { | 59 | { |
| 60 | spin_lock(&wdt_lock); | ||
| 59 | ixp2000_reg_write(IXP2000_T4_CLD, heartbeat * wdt_tick_rate); | 61 | ixp2000_reg_write(IXP2000_T4_CLD, heartbeat * wdt_tick_rate); |
| 62 | spin_unlock(&wdt_lock); | ||
| 60 | } | 63 | } |
| 61 | 64 | ||
| 62 | static int | 65 | static int ixp2000_wdt_open(struct inode *inode, struct file *file) |
| 63 | ixp2000_wdt_open(struct inode *inode, struct file *file) | ||
| 64 | { | 66 | { |
| 65 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) | 67 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) |
| 66 | return -EBUSY; | 68 | return -EBUSY; |
| @@ -72,8 +74,8 @@ ixp2000_wdt_open(struct inode *inode, struct file *file) | |||
| 72 | return nonseekable_open(inode, file); | 74 | return nonseekable_open(inode, file); |
| 73 | } | 75 | } |
| 74 | 76 | ||
| 75 | static ssize_t | 77 | static ssize_t ixp2000_wdt_write(struct file *file, const char *data, |
| 76 | ixp2000_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) | 78 | size_t len, loff_t *ppos) |
| 77 | { | 79 | { |
| 78 | if (len) { | 80 | if (len) { |
| 79 | if (!nowayout) { | 81 | if (!nowayout) { |
| @@ -103,9 +105,8 @@ static struct watchdog_info ident = { | |||
| 103 | .identity = "IXP2000 Watchdog", | 105 | .identity = "IXP2000 Watchdog", |
| 104 | }; | 106 | }; |
| 105 | 107 | ||
| 106 | static int | 108 | static long ixp2000_wdt_ioctl(struct file *file, unsigned int cmd, |
| 107 | ixp2000_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 109 | unsigned long arg) |
| 108 | unsigned long arg) | ||
| 109 | { | 110 | { |
| 110 | int ret = -ENOTTY; | 111 | int ret = -ENOTTY; |
| 111 | int time; | 112 | int time; |
| @@ -124,6 +125,11 @@ ixp2000_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 124 | ret = put_user(0, (int *)arg); | 125 | ret = put_user(0, (int *)arg); |
| 125 | break; | 126 | break; |
| 126 | 127 | ||
| 128 | case WDIOC_KEEPALIVE: | ||
| 129 | wdt_enable(); | ||
| 130 | ret = 0; | ||
| 131 | break; | ||
| 132 | |||
| 127 | case WDIOC_SETTIMEOUT: | 133 | case WDIOC_SETTIMEOUT: |
| 128 | ret = get_user(time, (int *)arg); | 134 | ret = get_user(time, (int *)arg); |
| 129 | if (ret) | 135 | if (ret) |
| @@ -141,26 +147,18 @@ ixp2000_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 141 | case WDIOC_GETTIMEOUT: | 147 | case WDIOC_GETTIMEOUT: |
| 142 | ret = put_user(heartbeat, (int *)arg); | 148 | ret = put_user(heartbeat, (int *)arg); |
| 143 | break; | 149 | break; |
| 144 | |||
| 145 | case WDIOC_KEEPALIVE: | ||
| 146 | wdt_enable(); | ||
| 147 | ret = 0; | ||
| 148 | break; | ||
| 149 | } | 150 | } |
| 150 | 151 | ||
| 151 | return ret; | 152 | return ret; |
| 152 | } | 153 | } |
| 153 | 154 | ||
| 154 | static int | 155 | static int ixp2000_wdt_release(struct inode *inode, struct file *file) |
| 155 | ixp2000_wdt_release(struct inode *inode, struct file *file) | ||
| 156 | { | 156 | { |
| 157 | if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) { | 157 | if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) |
| 158 | wdt_disable(); | 158 | wdt_disable(); |
| 159 | } else { | 159 | else |
| 160 | printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - " | 160 | printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - " |
| 161 | "timer will not stop\n"); | 161 | "timer will not stop\n"); |
| 162 | } | ||
| 163 | |||
| 164 | clear_bit(WDT_IN_USE, &wdt_status); | 162 | clear_bit(WDT_IN_USE, &wdt_status); |
| 165 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 163 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| 166 | 164 | ||
| @@ -168,18 +166,16 @@ ixp2000_wdt_release(struct inode *inode, struct file *file) | |||
| 168 | } | 166 | } |
| 169 | 167 | ||
| 170 | 168 | ||
| 171 | static const struct file_operations ixp2000_wdt_fops = | 169 | static const struct file_operations ixp2000_wdt_fops = { |
| 172 | { | ||
| 173 | .owner = THIS_MODULE, | 170 | .owner = THIS_MODULE, |
| 174 | .llseek = no_llseek, | 171 | .llseek = no_llseek, |
| 175 | .write = ixp2000_wdt_write, | 172 | .write = ixp2000_wdt_write, |
| 176 | .ioctl = ixp2000_wdt_ioctl, | 173 | .unlocked_ioctl = ixp2000_wdt_ioctl, |
| 177 | .open = ixp2000_wdt_open, | 174 | .open = ixp2000_wdt_open, |
| 178 | .release = ixp2000_wdt_release, | 175 | .release = ixp2000_wdt_release, |
| 179 | }; | 176 | }; |
| 180 | 177 | ||
| 181 | static struct miscdevice ixp2000_wdt_miscdev = | 178 | static struct miscdevice ixp2000_wdt_miscdev = { |
| 182 | { | ||
| 183 | .minor = WATCHDOG_MINOR, | 179 | .minor = WATCHDOG_MINOR, |
| 184 | .name = "watchdog", | 180 | .name = "watchdog", |
| 185 | .fops = &ixp2000_wdt_fops, | 181 | .fops = &ixp2000_wdt_fops, |
| @@ -191,9 +187,8 @@ static int __init ixp2000_wdt_init(void) | |||
| 191 | printk(KERN_INFO "Unable to use IXP2000 watchdog due to IXP2800 erratum #25.\n"); | 187 | printk(KERN_INFO "Unable to use IXP2000 watchdog due to IXP2800 erratum #25.\n"); |
| 192 | return -EIO; | 188 | return -EIO; |
| 193 | } | 189 | } |
| 194 | |||
| 195 | wdt_tick_rate = (*IXP2000_T1_CLD * HZ) / 256; | 190 | wdt_tick_rate = (*IXP2000_T1_CLD * HZ) / 256; |
| 196 | 191 | spin_lock_init(&wdt_lock); | |
| 197 | return misc_register(&ixp2000_wdt_miscdev); | 192 | return misc_register(&ixp2000_wdt_miscdev); |
| 198 | } | 193 | } |
| 199 | 194 | ||
diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c index 2313fad0dbb1..41264a5f1731 100644 --- a/drivers/watchdog/ixp4xx_wdt.c +++ b/drivers/watchdog/ixp4xx_wdt.c | |||
| @@ -22,48 +22,47 @@ | |||
| 22 | #include <linux/watchdog.h> | 22 | #include <linux/watchdog.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/bitops.h> | 24 | #include <linux/bitops.h> |
| 25 | 25 | #include <linux/uaccess.h> | |
| 26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 27 | #include <asm/uaccess.h> | ||
| 28 | 27 | ||
| 29 | static int nowayout = WATCHDOG_NOWAYOUT; | 28 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 30 | static int heartbeat = 60; /* (secs) Default is 1 minute */ | 29 | static int heartbeat = 60; /* (secs) Default is 1 minute */ |
| 31 | static unsigned long wdt_status; | 30 | static unsigned long wdt_status; |
| 32 | static unsigned long boot_status; | 31 | static unsigned long boot_status; |
| 32 | static spin_lock_t wdt_lock; | ||
| 33 | 33 | ||
| 34 | #define WDT_TICK_RATE (IXP4XX_PERIPHERAL_BUS_CLOCK * 1000000UL) | 34 | #define WDT_TICK_RATE (IXP4XX_PERIPHERAL_BUS_CLOCK * 1000000UL) |
| 35 | 35 | ||
| 36 | #define WDT_IN_USE 0 | 36 | #define WDT_IN_USE 0 |
| 37 | #define WDT_OK_TO_CLOSE 1 | 37 | #define WDT_OK_TO_CLOSE 1 |
| 38 | 38 | ||
| 39 | static void | 39 | static void wdt_enable(void) |
| 40 | wdt_enable(void) | ||
| 41 | { | 40 | { |
| 41 | spin_lock(&wdt_lock); | ||
| 42 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; | 42 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; |
| 43 | *IXP4XX_OSWE = 0; | 43 | *IXP4XX_OSWE = 0; |
| 44 | *IXP4XX_OSWT = WDT_TICK_RATE * heartbeat; | 44 | *IXP4XX_OSWT = WDT_TICK_RATE * heartbeat; |
| 45 | *IXP4XX_OSWE = IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE; | 45 | *IXP4XX_OSWE = IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE; |
| 46 | *IXP4XX_OSWK = 0; | 46 | *IXP4XX_OSWK = 0; |
| 47 | spin_unlock(&wdt_lock); | ||
| 47 | } | 48 | } |
| 48 | 49 | ||
| 49 | static void | 50 | static void wdt_disable(void) |
| 50 | wdt_disable(void) | ||
| 51 | { | 51 | { |
| 52 | spin_lock(&wdt_lock); | ||
| 52 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; | 53 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; |
| 53 | *IXP4XX_OSWE = 0; | 54 | *IXP4XX_OSWE = 0; |
| 54 | *IXP4XX_OSWK = 0; | 55 | *IXP4XX_OSWK = 0; |
| 56 | spin_unlock(&wdt_lock); | ||
| 55 | } | 57 | } |
| 56 | 58 | ||
| 57 | static int | 59 | static int ixp4xx_wdt_open(struct inode *inode, struct file *file) |
| 58 | ixp4xx_wdt_open(struct inode *inode, struct file *file) | ||
| 59 | { | 60 | { |
| 60 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) | 61 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) |
| 61 | return -EBUSY; | 62 | return -EBUSY; |
| 62 | 63 | ||
| 63 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 64 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| 64 | |||
| 65 | wdt_enable(); | 65 | wdt_enable(); |
| 66 | |||
| 67 | return nonseekable_open(inode, file); | 66 | return nonseekable_open(inode, file); |
| 68 | } | 67 | } |
| 69 | 68 | ||
| @@ -87,7 +86,6 @@ ixp4xx_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) | |||
| 87 | } | 86 | } |
| 88 | wdt_enable(); | 87 | wdt_enable(); |
| 89 | } | 88 | } |
| 90 | |||
| 91 | return len; | 89 | return len; |
| 92 | } | 90 | } |
| 93 | 91 | ||
| @@ -98,9 +96,8 @@ static struct watchdog_info ident = { | |||
| 98 | }; | 96 | }; |
| 99 | 97 | ||
| 100 | 98 | ||
| 101 | static int | 99 | static long ixp4xx_wdt_ioctl(struct file *file, unsigned int cmd, |
| 102 | ixp4xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 100 | unsigned long arg) |
| 103 | unsigned long arg) | ||
| 104 | { | 101 | { |
| 105 | int ret = -ENOTTY; | 102 | int ret = -ENOTTY; |
| 106 | int time; | 103 | int time; |
| @@ -119,6 +116,11 @@ ixp4xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 119 | ret = put_user(boot_status, (int *)arg); | 116 | ret = put_user(boot_status, (int *)arg); |
| 120 | break; | 117 | break; |
| 121 | 118 | ||
| 119 | case WDIOC_KEEPALIVE: | ||
| 120 | wdt_enable(); | ||
| 121 | ret = 0; | ||
| 122 | break; | ||
| 123 | |||
| 122 | case WDIOC_SETTIMEOUT: | 124 | case WDIOC_SETTIMEOUT: |
| 123 | ret = get_user(time, (int *)arg); | 125 | ret = get_user(time, (int *)arg); |
| 124 | if (ret) | 126 | if (ret) |
| @@ -136,25 +138,17 @@ ixp4xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 136 | case WDIOC_GETTIMEOUT: | 138 | case WDIOC_GETTIMEOUT: |
| 137 | ret = put_user(heartbeat, (int *)arg); | 139 | ret = put_user(heartbeat, (int *)arg); |
| 138 | break; | 140 | break; |
| 139 | |||
| 140 | case WDIOC_KEEPALIVE: | ||
| 141 | wdt_enable(); | ||
| 142 | ret = 0; | ||
| 143 | break; | ||
| 144 | } | 141 | } |
| 145 | return ret; | 142 | return ret; |
| 146 | } | 143 | } |
| 147 | 144 | ||
| 148 | static int | 145 | static int ixp4xx_wdt_release(struct inode *inode, struct file *file) |
| 149 | ixp4xx_wdt_release(struct inode *inode, struct file *file) | ||
| 150 | { | 146 | { |
| 151 | if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) { | 147 | if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) |
| 152 | wdt_disable(); | 148 | wdt_disable(); |
| 153 | } else { | 149 | else |
| 154 | printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - " | 150 | printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - " |
| 155 | "timer will not stop\n"); | 151 | "timer will not stop\n"); |
| 156 | } | ||
| 157 | |||
| 158 | clear_bit(WDT_IN_USE, &wdt_status); | 152 | clear_bit(WDT_IN_USE, &wdt_status); |
| 159 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 153 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| 160 | 154 | ||
| @@ -162,18 +156,16 @@ ixp4xx_wdt_release(struct inode *inode, struct file *file) | |||
| 162 | } | 156 | } |
| 163 | 157 | ||
| 164 | 158 | ||
| 165 | static const struct file_operations ixp4xx_wdt_fops = | 159 | static const struct file_operations ixp4xx_wdt_fops = { |
| 166 | { | ||
| 167 | .owner = THIS_MODULE, | 160 | .owner = THIS_MODULE, |
| 168 | .llseek = no_llseek, | 161 | .llseek = no_llseek, |
| 169 | .write = ixp4xx_wdt_write, | 162 | .write = ixp4xx_wdt_write, |
| 170 | .ioctl = ixp4xx_wdt_ioctl, | 163 | .unlocked_ioctl = ixp4xx_wdt_ioctl, |
| 171 | .open = ixp4xx_wdt_open, | 164 | .open = ixp4xx_wdt_open, |
| 172 | .release = ixp4xx_wdt_release, | 165 | .release = ixp4xx_wdt_release, |
| 173 | }; | 166 | }; |
| 174 | 167 | ||
| 175 | static struct miscdevice ixp4xx_wdt_miscdev = | 168 | static struct miscdevice ixp4xx_wdt_miscdev = { |
| 176 | { | ||
| 177 | .minor = WATCHDOG_MINOR, | 169 | .minor = WATCHDOG_MINOR, |
| 178 | .name = "watchdog", | 170 | .name = "watchdog", |
| 179 | .fops = &ixp4xx_wdt_fops, | 171 | .fops = &ixp4xx_wdt_fops, |
| @@ -186,19 +178,18 @@ static int __init ixp4xx_wdt_init(void) | |||
| 186 | 178 | ||
| 187 | asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); | 179 | asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); |
| 188 | if (!(processor_id & 0xf) && !cpu_is_ixp46x()) { | 180 | if (!(processor_id & 0xf) && !cpu_is_ixp46x()) { |
| 189 | printk("IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected - " | 181 | printk(KERN_ERR "IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected" |
| 190 | "watchdog disabled\n"); | 182 | " - watchdog disabled\n"); |
| 191 | 183 | ||
| 192 | return -ENODEV; | 184 | return -ENODEV; |
| 193 | } | 185 | } |
| 194 | 186 | spin_lock_init(&wdt_lock); | |
| 195 | ret = misc_register(&ixp4xx_wdt_miscdev); | ||
| 196 | if (ret == 0) | ||
| 197 | printk("IXP4xx Watchdog Timer: heartbeat %d sec\n", heartbeat); | ||
| 198 | |||
| 199 | boot_status = (*IXP4XX_OSST & IXP4XX_OSST_TIMER_WARM_RESET) ? | 187 | boot_status = (*IXP4XX_OSST & IXP4XX_OSST_TIMER_WARM_RESET) ? |
| 200 | WDIOF_CARDRESET : 0; | 188 | WDIOF_CARDRESET : 0; |
| 201 | 189 | ret = misc_register(&ixp4xx_wdt_miscdev); | |
| 190 | if (ret == 0) | ||
| 191 | printk(KERN_INFO "IXP4xx Watchdog Timer: heartbeat %d sec\n", | ||
| 192 | heartbeat); | ||
| 202 | return ret; | 193 | return ret; |
| 203 | } | 194 | } |
| 204 | 195 | ||
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c index d21a6407fe21..0b798fdaa378 100644 --- a/drivers/watchdog/ks8695_wdt.c +++ b/drivers/watchdog/ks8695_wdt.c | |||
| @@ -19,11 +19,10 @@ | |||
| 19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/types.h> | 20 | #include <linux/types.h> |
| 21 | #include <linux/watchdog.h> | 21 | #include <linux/watchdog.h> |
| 22 | #include <asm/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <asm/uaccess.h> | 23 | #include <linux/uaccess.h> |
| 24 | #include <mach/regs-timer.h> | 24 | #include <mach/regs-timer.h> |
| 25 | 25 | ||
| 26 | |||
| 27 | #define WDT_DEFAULT_TIME 5 /* seconds */ | 26 | #define WDT_DEFAULT_TIME 5 /* seconds */ |
| 28 | #define WDT_MAX_TIME 171 /* seconds */ | 27 | #define WDT_MAX_TIME 171 /* seconds */ |
| 29 | 28 | ||
| @@ -31,38 +30,44 @@ static int wdt_time = WDT_DEFAULT_TIME; | |||
| 31 | static int nowayout = WATCHDOG_NOWAYOUT; | 30 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 32 | 31 | ||
| 33 | module_param(wdt_time, int, 0); | 32 | module_param(wdt_time, int, 0); |
| 34 | MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="__MODULE_STRING(WDT_DEFAULT_TIME) ")"); | 33 | MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default=" |
| 34 | __MODULE_STRING(WDT_DEFAULT_TIME) ")"); | ||
| 35 | 35 | ||
| 36 | #ifdef CONFIG_WATCHDOG_NOWAYOUT | 36 | #ifdef CONFIG_WATCHDOG_NOWAYOUT |
| 37 | module_param(nowayout, int, 0); | 37 | module_param(nowayout, int, 0); |
| 38 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 38 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
| 39 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 39 | #endif | 40 | #endif |
| 40 | 41 | ||
| 41 | 42 | ||
| 42 | static unsigned long ks8695wdt_busy; | 43 | static unsigned long ks8695wdt_busy; |
| 44 | static spinlock_t ks8695_lock; | ||
| 43 | 45 | ||
| 44 | /* ......................................................................... */ | 46 | /* ......................................................................... */ |
| 45 | 47 | ||
| 46 | /* | 48 | /* |
| 47 | * Disable the watchdog. | 49 | * Disable the watchdog. |
| 48 | */ | 50 | */ |
| 49 | static void inline ks8695_wdt_stop(void) | 51 | static inline void ks8695_wdt_stop(void) |
| 50 | { | 52 | { |
| 51 | unsigned long tmcon; | 53 | unsigned long tmcon; |
| 52 | 54 | ||
| 55 | spin_lock(&ks8695_lock); | ||
| 53 | /* disable timer0 */ | 56 | /* disable timer0 */ |
| 54 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | 57 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); |
| 55 | __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | 58 | __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); |
| 59 | spin_unlock(&ks8695_lock); | ||
| 56 | } | 60 | } |
| 57 | 61 | ||
| 58 | /* | 62 | /* |
| 59 | * Enable and reset the watchdog. | 63 | * Enable and reset the watchdog. |
| 60 | */ | 64 | */ |
| 61 | static void inline ks8695_wdt_start(void) | 65 | static inline void ks8695_wdt_start(void) |
| 62 | { | 66 | { |
| 63 | unsigned long tmcon; | 67 | unsigned long tmcon; |
| 64 | unsigned long tval = wdt_time * CLOCK_TICK_RATE; | 68 | unsigned long tval = wdt_time * CLOCK_TICK_RATE; |
| 65 | 69 | ||
| 70 | spin_lock(&ks8695_lock); | ||
| 66 | /* disable timer0 */ | 71 | /* disable timer0 */ |
| 67 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | 72 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); |
| 68 | __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | 73 | __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); |
| @@ -73,19 +78,22 @@ static void inline ks8695_wdt_start(void) | |||
| 73 | /* re-enable timer0 */ | 78 | /* re-enable timer0 */ |
| 74 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | 79 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); |
| 75 | __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | 80 | __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); |
| 81 | spin_unlock(&ks8695_lock); | ||
| 76 | } | 82 | } |
| 77 | 83 | ||
| 78 | /* | 84 | /* |
| 79 | * Reload the watchdog timer. (ie, pat the watchdog) | 85 | * Reload the watchdog timer. (ie, pat the watchdog) |
| 80 | */ | 86 | */ |
| 81 | static void inline ks8695_wdt_reload(void) | 87 | static inline void ks8695_wdt_reload(void) |
| 82 | { | 88 | { |
| 83 | unsigned long tmcon; | 89 | unsigned long tmcon; |
| 84 | 90 | ||
| 91 | spin_lock(&ks8695_lock); | ||
| 85 | /* disable, then re-enable timer0 */ | 92 | /* disable, then re-enable timer0 */ |
| 86 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | 93 | tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); |
| 87 | __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | 94 | __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); |
| 88 | __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | 95 | __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); |
| 96 | spin_unlock(&ks8695_lock); | ||
| 89 | } | 97 | } |
| 90 | 98 | ||
| 91 | /* | 99 | /* |
| @@ -102,7 +110,8 @@ static int ks8695_wdt_settimeout(int new_time) | |||
| 102 | if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) | 110 | if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) |
| 103 | return -EINVAL; | 111 | return -EINVAL; |
| 104 | 112 | ||
| 105 | /* Set new watchdog time. It will be used when ks8695_wdt_start() is called. */ | 113 | /* Set new watchdog time. It will be used when |
| 114 | ks8695_wdt_start() is called. */ | ||
| 106 | wdt_time = new_time; | 115 | wdt_time = new_time; |
| 107 | return 0; | 116 | return 0; |
| 108 | } | 117 | } |
| @@ -128,9 +137,9 @@ static int ks8695_wdt_open(struct inode *inode, struct file *file) | |||
| 128 | */ | 137 | */ |
| 129 | static int ks8695_wdt_close(struct inode *inode, struct file *file) | 138 | static int ks8695_wdt_close(struct inode *inode, struct file *file) |
| 130 | { | 139 | { |
| 140 | /* Disable the watchdog when file is closed */ | ||
| 131 | if (!nowayout) | 141 | if (!nowayout) |
| 132 | ks8695_wdt_stop(); /* Disable the watchdog when file is closed */ | 142 | ks8695_wdt_stop(); |
| 133 | |||
| 134 | clear_bit(0, &ks8695wdt_busy); | 143 | clear_bit(0, &ks8695wdt_busy); |
| 135 | return 0; | 144 | return 0; |
| 136 | } | 145 | } |
| @@ -143,60 +152,52 @@ static struct watchdog_info ks8695_wdt_info = { | |||
| 143 | /* | 152 | /* |
| 144 | * Handle commands from user-space. | 153 | * Handle commands from user-space. |
| 145 | */ | 154 | */ |
| 146 | static int ks8695_wdt_ioctl(struct inode *inode, struct file *file, | 155 | static long ks8695_wdt_ioctl(struct file *file, unsigned int cmd, |
| 147 | unsigned int cmd, unsigned long arg) | 156 | unsigned long arg) |
| 148 | { | 157 | { |
| 149 | void __user *argp = (void __user *)arg; | 158 | void __user *argp = (void __user *)arg; |
| 150 | int __user *p = argp; | 159 | int __user *p = argp; |
| 151 | int new_value; | 160 | int new_value; |
| 152 | 161 | ||
| 153 | switch(cmd) { | 162 | switch (cmd) { |
| 154 | case WDIOC_KEEPALIVE: | 163 | case WDIOC_GETSUPPORT: |
| 155 | ks8695_wdt_reload(); /* pat the watchdog */ | 164 | return copy_to_user(argp, &ks8695_wdt_info, |
| 156 | return 0; | 165 | sizeof(ks8695_wdt_info)) ? -EFAULT : 0; |
| 157 | 166 | case WDIOC_GETSTATUS: | |
| 158 | case WDIOC_GETSUPPORT: | 167 | case WDIOC_GETBOOTSTATUS: |
| 159 | return copy_to_user(argp, &ks8695_wdt_info, sizeof(ks8695_wdt_info)) ? -EFAULT : 0; | 168 | return put_user(0, p); |
| 160 | 169 | case WDIOC_SETOPTIONS: | |
| 161 | case WDIOC_SETTIMEOUT: | 170 | if (get_user(new_value, p)) |
| 162 | if (get_user(new_value, p)) | 171 | return -EFAULT; |
| 163 | return -EFAULT; | 172 | if (new_value & WDIOS_DISABLECARD) |
| 164 | 173 | ks8695_wdt_stop(); | |
| 165 | if (ks8695_wdt_settimeout(new_value)) | 174 | if (new_value & WDIOS_ENABLECARD) |
| 166 | return -EINVAL; | ||
| 167 | |||
| 168 | /* Enable new time value */ | ||
| 169 | ks8695_wdt_start(); | 175 | ks8695_wdt_start(); |
| 170 | 176 | return 0; | |
| 171 | /* Return current value */ | 177 | case WDIOC_KEEPALIVE: |
| 172 | return put_user(wdt_time, p); | 178 | ks8695_wdt_reload(); /* pat the watchdog */ |
| 173 | 179 | return 0; | |
| 174 | case WDIOC_GETTIMEOUT: | 180 | case WDIOC_SETTIMEOUT: |
| 175 | return put_user(wdt_time, p); | 181 | if (get_user(new_value, p)) |
| 176 | 182 | return -EFAULT; | |
| 177 | case WDIOC_GETSTATUS: | 183 | if (ks8695_wdt_settimeout(new_value)) |
| 178 | case WDIOC_GETBOOTSTATUS: | 184 | return -EINVAL; |
| 179 | return put_user(0, p); | 185 | /* Enable new time value */ |
| 180 | 186 | ks8695_wdt_start(); | |
| 181 | case WDIOC_SETOPTIONS: | 187 | /* Return current value */ |
| 182 | if (get_user(new_value, p)) | 188 | return put_user(wdt_time, p); |
| 183 | return -EFAULT; | 189 | case WDIOC_GETTIMEOUT: |
| 184 | 190 | return put_user(wdt_time, p); | |
| 185 | if (new_value & WDIOS_DISABLECARD) | 191 | default: |
| 186 | ks8695_wdt_stop(); | 192 | return -ENOTTY; |
| 187 | if (new_value & WDIOS_ENABLECARD) | ||
| 188 | ks8695_wdt_start(); | ||
| 189 | return 0; | ||
| 190 | |||
| 191 | default: | ||
| 192 | return -ENOTTY; | ||
| 193 | } | 193 | } |
| 194 | } | 194 | } |
| 195 | 195 | ||
| 196 | /* | 196 | /* |
| 197 | * Pat the watchdog whenever device is written to. | 197 | * Pat the watchdog whenever device is written to. |
| 198 | */ | 198 | */ |
| 199 | static ssize_t ks8695_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) | 199 | static ssize_t ks8695_wdt_write(struct file *file, const char *data, |
| 200 | size_t len, loff_t *ppos) | ||
| 200 | { | 201 | { |
| 201 | ks8695_wdt_reload(); /* pat the watchdog */ | 202 | ks8695_wdt_reload(); /* pat the watchdog */ |
| 202 | return len; | 203 | return len; |
| @@ -207,7 +208,7 @@ static ssize_t ks8695_wdt_write(struct file *file, const char *data, size_t len, | |||
| 207 | static const struct file_operations ks8695wdt_fops = { | 208 | static const struct file_operations ks8695wdt_fops = { |
| 208 | .owner = THIS_MODULE, | 209 | .owner = THIS_MODULE, |
| 209 | .llseek = no_llseek, | 210 | .llseek = no_llseek, |
| 210 | .ioctl = ks8695_wdt_ioctl, | 211 | .unlocked_ioctl = ks8695_wdt_ioctl, |
| 211 | .open = ks8695_wdt_open, | 212 | .open = ks8695_wdt_open, |
| 212 | .release = ks8695_wdt_close, | 213 | .release = ks8695_wdt_close, |
| 213 | .write = ks8695_wdt_write, | 214 | .write = ks8695_wdt_write, |
| @@ -231,7 +232,8 @@ static int __init ks8695wdt_probe(struct platform_device *pdev) | |||
| 231 | if (res) | 232 | if (res) |
| 232 | return res; | 233 | return res; |
| 233 | 234 | ||
| 234 | printk("KS8695 Watchdog Timer enabled (%d seconds%s)\n", wdt_time, nowayout ? ", nowayout" : ""); | 235 | printk(KERN_INFO "KS8695 Watchdog Timer enabled (%d seconds%s)\n", |
| 236 | wdt_time, nowayout ? ", nowayout" : ""); | ||
| 235 | return 0; | 237 | return 0; |
| 236 | } | 238 | } |
| 237 | 239 | ||
| @@ -285,12 +287,14 @@ static struct platform_driver ks8695wdt_driver = { | |||
| 285 | 287 | ||
| 286 | static int __init ks8695_wdt_init(void) | 288 | static int __init ks8695_wdt_init(void) |
| 287 | { | 289 | { |
| 288 | /* Check that the heartbeat value is within range; if not reset to the default */ | 290 | spin_lock_init(&ks8695_lock); |
| 291 | /* Check that the heartbeat value is within range; | ||
| 292 | if not reset to the default */ | ||
| 289 | if (ks8695_wdt_settimeout(wdt_time)) { | 293 | if (ks8695_wdt_settimeout(wdt_time)) { |
| 290 | ks8695_wdt_settimeout(WDT_DEFAULT_TIME); | 294 | ks8695_wdt_settimeout(WDT_DEFAULT_TIME); |
| 291 | pr_info("ks8695_wdt: wdt_time value must be 1 <= wdt_time <= %i, using %d\n", wdt_time, WDT_MAX_TIME); | 295 | pr_info("ks8695_wdt: wdt_time value must be 1 <= wdt_time <= %i, using %d\n", |
| 296 | wdt_time, WDT_MAX_TIME); | ||
| 292 | } | 297 | } |
| 293 | |||
| 294 | return platform_driver_register(&ks8695wdt_driver); | 298 | return platform_driver_register(&ks8695wdt_driver); |
| 295 | } | 299 | } |
| 296 | 300 | ||
diff --git a/drivers/watchdog/machzwd.c b/drivers/watchdog/machzwd.c index 6905135a776c..2dfc27559bf7 100644 --- a/drivers/watchdog/machzwd.c +++ b/drivers/watchdog/machzwd.c | |||
| @@ -40,9 +40,9 @@ | |||
| 40 | #include <linux/notifier.h> | 40 | #include <linux/notifier.h> |
| 41 | #include <linux/reboot.h> | 41 | #include <linux/reboot.h> |
| 42 | #include <linux/init.h> | 42 | #include <linux/init.h> |
| 43 | #include <linux/io.h> | ||
| 44 | #include <linux/uaccess.h> | ||
| 43 | 45 | ||
| 44 | #include <asm/io.h> | ||
| 45 | #include <asm/uaccess.h> | ||
| 46 | #include <asm/system.h> | 46 | #include <asm/system.h> |
| 47 | 47 | ||
| 48 | /* ports */ | 48 | /* ports */ |
| @@ -95,7 +95,9 @@ MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |||
| 95 | 95 | ||
| 96 | static int nowayout = WATCHDOG_NOWAYOUT; | 96 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 97 | module_param(nowayout, int, 0); | 97 | module_param(nowayout, int, 0); |
| 98 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 98 | MODULE_PARM_DESC(nowayout, |
| 99 | "Watchdog cannot be stopped once started (default=" | ||
| 100 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 99 | 101 | ||
| 100 | #define PFX "machzwd" | 102 | #define PFX "machzwd" |
| 101 | 103 | ||
| @@ -114,7 +116,7 @@ static struct watchdog_info zf_info = { | |||
| 114 | * 3 = GEN_SCI | 116 | * 3 = GEN_SCI |
| 115 | * defaults to GEN_RESET (0) | 117 | * defaults to GEN_RESET (0) |
| 116 | */ | 118 | */ |
| 117 | static int action = 0; | 119 | static int action; |
| 118 | module_param(action, int, 0); | 120 | module_param(action, int, 0); |
| 119 | MODULE_PARM_DESC(action, "after watchdog resets, generate: 0 = RESET(*) 1 = SMI 2 = NMI 3 = SCI"); | 121 | MODULE_PARM_DESC(action, "after watchdog resets, generate: 0 = RESET(*) 1 = SMI 2 = NMI 3 = SCI"); |
| 120 | 122 | ||
| @@ -123,10 +125,9 @@ static void zf_ping(unsigned long data); | |||
| 123 | static int zf_action = GEN_RESET; | 125 | static int zf_action = GEN_RESET; |
| 124 | static unsigned long zf_is_open; | 126 | static unsigned long zf_is_open; |
| 125 | static char zf_expect_close; | 127 | static char zf_expect_close; |
| 126 | static DEFINE_SPINLOCK(zf_lock); | ||
| 127 | static DEFINE_SPINLOCK(zf_port_lock); | 128 | static DEFINE_SPINLOCK(zf_port_lock); |
| 128 | static DEFINE_TIMER(zf_timer, zf_ping, 0, 0); | 129 | static DEFINE_TIMER(zf_timer, zf_ping, 0, 0); |
| 129 | static unsigned long next_heartbeat = 0; | 130 | static unsigned long next_heartbeat; |
| 130 | 131 | ||
| 131 | 132 | ||
| 132 | /* timeout for user land heart beat (10 seconds) */ | 133 | /* timeout for user land heart beat (10 seconds) */ |
| @@ -171,13 +172,13 @@ static inline void zf_set_control(unsigned short new) | |||
| 171 | 172 | ||
| 172 | static inline void zf_set_timer(unsigned short new, unsigned char n) | 173 | static inline void zf_set_timer(unsigned short new, unsigned char n) |
| 173 | { | 174 | { |
| 174 | switch(n){ | 175 | switch (n) { |
| 175 | case WD1: | 176 | case WD1: |
| 176 | zf_writew(COUNTER_1, new); | 177 | zf_writew(COUNTER_1, new); |
| 177 | case WD2: | 178 | case WD2: |
| 178 | zf_writeb(COUNTER_2, new > 0xff ? 0xff : new); | 179 | zf_writeb(COUNTER_2, new > 0xff ? 0xff : new); |
| 179 | default: | 180 | default: |
| 180 | return; | 181 | return; |
| 181 | } | 182 | } |
| 182 | } | 183 | } |
| 183 | 184 | ||
| @@ -241,10 +242,8 @@ static void zf_ping(unsigned long data) | |||
| 241 | 242 | ||
| 242 | zf_writeb(COUNTER_2, 0xff); | 243 | zf_writeb(COUNTER_2, 0xff); |
| 243 | 244 | ||
| 244 | if(time_before(jiffies, next_heartbeat)){ | 245 | if (time_before(jiffies, next_heartbeat)) { |
| 245 | |||
| 246 | dprintk("time_before: %ld\n", next_heartbeat - jiffies); | 246 | dprintk("time_before: %ld\n", next_heartbeat - jiffies); |
| 247 | |||
| 248 | /* | 247 | /* |
| 249 | * reset event is activated by transition from 0 to 1 on | 248 | * reset event is activated by transition from 0 to 1 on |
| 250 | * RESET_WD1 bit and we assume that it is already zero... | 249 | * RESET_WD1 bit and we assume that it is already zero... |
| @@ -261,24 +260,21 @@ static void zf_ping(unsigned long data) | |||
| 261 | spin_unlock_irqrestore(&zf_port_lock, flags); | 260 | spin_unlock_irqrestore(&zf_port_lock, flags); |
| 262 | 261 | ||
| 263 | mod_timer(&zf_timer, jiffies + ZF_HW_TIMEO); | 262 | mod_timer(&zf_timer, jiffies + ZF_HW_TIMEO); |
| 264 | }else{ | 263 | } else |
| 265 | printk(KERN_CRIT PFX ": I will reset your machine\n"); | 264 | printk(KERN_CRIT PFX ": I will reset your machine\n"); |
| 266 | } | ||
| 267 | } | 265 | } |
| 268 | 266 | ||
| 269 | static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, | 267 | static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, |
| 270 | loff_t *ppos) | 268 | loff_t *ppos) |
| 271 | { | 269 | { |
| 272 | /* See if we got the magic character */ | 270 | /* See if we got the magic character */ |
| 273 | if(count){ | 271 | if (count) { |
| 274 | |||
| 275 | /* | 272 | /* |
| 276 | * no need to check for close confirmation | 273 | * no need to check for close confirmation |
| 277 | * no way to disable watchdog ;) | 274 | * no way to disable watchdog ;) |
| 278 | */ | 275 | */ |
| 279 | if (!nowayout) { | 276 | if (!nowayout) { |
| 280 | size_t ofs; | 277 | size_t ofs; |
| 281 | |||
| 282 | /* | 278 | /* |
| 283 | * note: just in case someone wrote the magic character | 279 | * note: just in case someone wrote the magic character |
| 284 | * five months ago... | 280 | * five months ago... |
| @@ -286,11 +282,11 @@ static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, | |||
| 286 | zf_expect_close = 0; | 282 | zf_expect_close = 0; |
| 287 | 283 | ||
| 288 | /* now scan */ | 284 | /* now scan */ |
| 289 | for (ofs = 0; ofs != count; ofs++){ | 285 | for (ofs = 0; ofs != count; ofs++) { |
| 290 | char c; | 286 | char c; |
| 291 | if (get_user(c, buf + ofs)) | 287 | if (get_user(c, buf + ofs)) |
| 292 | return -EFAULT; | 288 | return -EFAULT; |
| 293 | if (c == 'V'){ | 289 | if (c == 'V') { |
| 294 | zf_expect_close = 42; | 290 | zf_expect_close = 42; |
| 295 | dprintk("zf_expect_close = 42\n"); | 291 | dprintk("zf_expect_close = 42\n"); |
| 296 | } | 292 | } |
| @@ -303,14 +299,11 @@ static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, | |||
| 303 | */ | 299 | */ |
| 304 | next_heartbeat = jiffies + ZF_USER_TIMEO; | 300 | next_heartbeat = jiffies + ZF_USER_TIMEO; |
| 305 | dprintk("user ping at %ld\n", jiffies); | 301 | dprintk("user ping at %ld\n", jiffies); |
| 306 | |||
| 307 | } | 302 | } |
| 308 | |||
| 309 | return count; | 303 | return count; |
| 310 | } | 304 | } |
| 311 | 305 | ||
| 312 | static int zf_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 306 | static long zf_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 313 | unsigned long arg) | ||
| 314 | { | 307 | { |
| 315 | void __user *argp = (void __user *)arg; | 308 | void __user *argp = (void __user *)arg; |
| 316 | int __user *p = argp; | 309 | int __user *p = argp; |
| @@ -319,55 +312,38 @@ static int zf_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 319 | if (copy_to_user(argp, &zf_info, sizeof(zf_info))) | 312 | if (copy_to_user(argp, &zf_info, sizeof(zf_info))) |
| 320 | return -EFAULT; | 313 | return -EFAULT; |
| 321 | break; | 314 | break; |
| 322 | |||
| 323 | case WDIOC_GETSTATUS: | 315 | case WDIOC_GETSTATUS: |
| 324 | case WDIOC_GETBOOTSTATUS: | 316 | case WDIOC_GETBOOTSTATUS: |
| 325 | return put_user(0, p); | 317 | return put_user(0, p); |
| 326 | |||
| 327 | case WDIOC_KEEPALIVE: | 318 | case WDIOC_KEEPALIVE: |
| 328 | zf_ping(0); | 319 | zf_ping(0); |
| 329 | break; | 320 | break; |
| 330 | |||
| 331 | default: | 321 | default: |
| 332 | return -ENOTTY; | 322 | return -ENOTTY; |
| 333 | } | 323 | } |
| 334 | |||
| 335 | return 0; | 324 | return 0; |
| 336 | } | 325 | } |
| 337 | 326 | ||
| 338 | static int zf_open(struct inode *inode, struct file *file) | 327 | static int zf_open(struct inode *inode, struct file *file) |
| 339 | { | 328 | { |
| 340 | spin_lock(&zf_lock); | 329 | if (test_and_set_bit(0, &zf_is_open)) |
| 341 | if(test_and_set_bit(0, &zf_is_open)) { | ||
| 342 | spin_unlock(&zf_lock); | ||
| 343 | return -EBUSY; | 330 | return -EBUSY; |
| 344 | } | ||
| 345 | |||
| 346 | if (nowayout) | 331 | if (nowayout) |
| 347 | __module_get(THIS_MODULE); | 332 | __module_get(THIS_MODULE); |
| 348 | |||
| 349 | spin_unlock(&zf_lock); | ||
| 350 | |||
| 351 | zf_timer_on(); | 333 | zf_timer_on(); |
| 352 | |||
| 353 | return nonseekable_open(inode, file); | 334 | return nonseekable_open(inode, file); |
| 354 | } | 335 | } |
| 355 | 336 | ||
| 356 | static int zf_close(struct inode *inode, struct file *file) | 337 | static int zf_close(struct inode *inode, struct file *file) |
| 357 | { | 338 | { |
| 358 | if(zf_expect_close == 42){ | 339 | if (zf_expect_close == 42) |
| 359 | zf_timer_off(); | 340 | zf_timer_off(); |
| 360 | } else { | 341 | else { |
| 361 | del_timer(&zf_timer); | 342 | del_timer(&zf_timer); |
| 362 | printk(KERN_ERR PFX ": device file closed unexpectedly. Will not stop the WDT!\n"); | 343 | printk(KERN_ERR PFX ": device file closed unexpectedly. Will not stop the WDT!\n"); |
| 363 | } | 344 | } |
| 364 | |||
| 365 | spin_lock(&zf_lock); | ||
| 366 | clear_bit(0, &zf_is_open); | 345 | clear_bit(0, &zf_is_open); |
| 367 | spin_unlock(&zf_lock); | ||
| 368 | |||
| 369 | zf_expect_close = 0; | 346 | zf_expect_close = 0; |
| 370 | |||
| 371 | return 0; | 347 | return 0; |
| 372 | } | 348 | } |
| 373 | 349 | ||
| @@ -378,23 +354,18 @@ static int zf_close(struct inode *inode, struct file *file) | |||
| 378 | static int zf_notify_sys(struct notifier_block *this, unsigned long code, | 354 | static int zf_notify_sys(struct notifier_block *this, unsigned long code, |
| 379 | void *unused) | 355 | void *unused) |
| 380 | { | 356 | { |
| 381 | if(code == SYS_DOWN || code == SYS_HALT){ | 357 | if (code == SYS_DOWN || code == SYS_HALT) |
| 382 | zf_timer_off(); | 358 | zf_timer_off(); |
| 383 | } | ||
| 384 | |||
| 385 | return NOTIFY_DONE; | 359 | return NOTIFY_DONE; |
| 386 | } | 360 | } |
| 387 | 361 | ||
| 388 | |||
| 389 | |||
| 390 | |||
| 391 | static const struct file_operations zf_fops = { | 362 | static const struct file_operations zf_fops = { |
| 392 | .owner = THIS_MODULE, | 363 | .owner = THIS_MODULE, |
| 393 | .llseek = no_llseek, | 364 | .llseek = no_llseek, |
| 394 | .write = zf_write, | 365 | .write = zf_write, |
| 395 | .ioctl = zf_ioctl, | 366 | .unlocked_ioctl = zf_ioctl, |
| 396 | .open = zf_open, | 367 | .open = zf_open, |
| 397 | .release = zf_close, | 368 | .release = zf_close, |
| 398 | }; | 369 | }; |
| 399 | 370 | ||
| 400 | static struct miscdevice zf_miscdev = { | 371 | static struct miscdevice zf_miscdev = { |
| @@ -402,7 +373,7 @@ static struct miscdevice zf_miscdev = { | |||
| 402 | .name = "watchdog", | 373 | .name = "watchdog", |
| 403 | .fops = &zf_fops, | 374 | .fops = &zf_fops, |
| 404 | }; | 375 | }; |
| 405 | 376 | ||
| 406 | 377 | ||
| 407 | /* | 378 | /* |
| 408 | * The device needs to learn about soft shutdowns in order to | 379 | * The device needs to learn about soft shutdowns in order to |
| @@ -423,22 +394,23 @@ static int __init zf_init(void) | |||
| 423 | { | 394 | { |
| 424 | int ret; | 395 | int ret; |
| 425 | 396 | ||
| 426 | printk(KERN_INFO PFX ": MachZ ZF-Logic Watchdog driver initializing.\n"); | 397 | printk(KERN_INFO PFX |
| 398 | ": MachZ ZF-Logic Watchdog driver initializing.\n"); | ||
| 427 | 399 | ||
| 428 | ret = zf_get_ZFL_version(); | 400 | ret = zf_get_ZFL_version(); |
| 429 | if ((!ret) || (ret == 0xffff)) { | 401 | if (!ret || ret == 0xffff) { |
| 430 | printk(KERN_WARNING PFX ": no ZF-Logic found\n"); | 402 | printk(KERN_WARNING PFX ": no ZF-Logic found\n"); |
| 431 | return -ENODEV; | 403 | return -ENODEV; |
| 432 | } | 404 | } |
| 433 | 405 | ||
| 434 | if((action <= 3) && (action >= 0)){ | 406 | if (action <= 3 && action >= 0) |
| 435 | zf_action = zf_action>>action; | 407 | zf_action = zf_action >> action; |
| 436 | } else | 408 | else |
| 437 | action = 0; | 409 | action = 0; |
| 438 | 410 | ||
| 439 | zf_show_action(action); | 411 | zf_show_action(action); |
| 440 | 412 | ||
| 441 | if(!request_region(ZF_IOBASE, 3, "MachZ ZFL WDT")){ | 413 | if (!request_region(ZF_IOBASE, 3, "MachZ ZFL WDT")) { |
| 442 | printk(KERN_ERR "cannot reserve I/O ports at %d\n", | 414 | printk(KERN_ERR "cannot reserve I/O ports at %d\n", |
| 443 | ZF_IOBASE); | 415 | ZF_IOBASE); |
| 444 | ret = -EBUSY; | 416 | ret = -EBUSY; |
| @@ -446,14 +418,14 @@ static int __init zf_init(void) | |||
| 446 | } | 418 | } |
| 447 | 419 | ||
| 448 | ret = register_reboot_notifier(&zf_notifier); | 420 | ret = register_reboot_notifier(&zf_notifier); |
| 449 | if(ret){ | 421 | if (ret) { |
| 450 | printk(KERN_ERR "can't register reboot notifier (err=%d)\n", | 422 | printk(KERN_ERR "can't register reboot notifier (err=%d)\n", |
| 451 | ret); | 423 | ret); |
| 452 | goto no_reboot; | 424 | goto no_reboot; |
| 453 | } | 425 | } |
| 454 | 426 | ||
| 455 | ret = misc_register(&zf_miscdev); | 427 | ret = misc_register(&zf_miscdev); |
| 456 | if (ret){ | 428 | if (ret) { |
| 457 | printk(KERN_ERR "can't misc_register on minor=%d\n", | 429 | printk(KERN_ERR "can't misc_register on minor=%d\n", |
| 458 | WATCHDOG_MINOR); | 430 | WATCHDOG_MINOR); |
| 459 | goto no_misc; | 431 | goto no_misc; |
diff --git a/drivers/watchdog/mixcomwd.c b/drivers/watchdog/mixcomwd.c index 1adf1d56027d..407b025cb104 100644 --- a/drivers/watchdog/mixcomwd.c +++ b/drivers/watchdog/mixcomwd.c | |||
| @@ -29,7 +29,8 @@ | |||
| 29 | * - support for one more type board | 29 | * - support for one more type board |
| 30 | * | 30 | * |
| 31 | * Version 0.5 (2001/12/14) Matt Domsch <Matt_Domsch@dell.com> | 31 | * Version 0.5 (2001/12/14) Matt Domsch <Matt_Domsch@dell.com> |
| 32 | * - added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT | 32 | * - added nowayout module option to override |
| 33 | * CONFIG_WATCHDOG_NOWAYOUT | ||
| 33 | * | 34 | * |
| 34 | * Version 0.6 (2002/04/12): Rob Radez <rob@osinvestor.com> | 35 | * Version 0.6 (2002/04/12): Rob Radez <rob@osinvestor.com> |
| 35 | * - make mixcomwd_opened unsigned, | 36 | * - make mixcomwd_opened unsigned, |
| @@ -53,8 +54,8 @@ | |||
| 53 | #include <linux/init.h> | 54 | #include <linux/init.h> |
| 54 | #include <linux/jiffies.h> | 55 | #include <linux/jiffies.h> |
| 55 | #include <linux/timer.h> | 56 | #include <linux/timer.h> |
| 56 | #include <asm/uaccess.h> | 57 | #include <linux/uaccess.h> |
| 57 | #include <asm/io.h> | 58 | #include <linux/io.h> |
| 58 | 59 | ||
| 59 | /* | 60 | /* |
| 60 | * We have two types of cards that can be probed: | 61 | * We have two types of cards that can be probed: |
| @@ -108,18 +109,19 @@ static char expect_close; | |||
| 108 | 109 | ||
| 109 | static int nowayout = WATCHDOG_NOWAYOUT; | 110 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 110 | module_param(nowayout, int, 0); | 111 | module_param(nowayout, int, 0); |
| 111 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 112 | MODULE_PARM_DESC(nowayout, |
| 113 | "Watchdog cannot be stopped once started (default=" | ||
| 114 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 112 | 115 | ||
| 113 | static void mixcomwd_ping(void) | 116 | static void mixcomwd_ping(void) |
| 114 | { | 117 | { |
| 115 | outb_p(55,watchdog_port); | 118 | outb_p(55, watchdog_port); |
| 116 | return; | 119 | return; |
| 117 | } | 120 | } |
| 118 | 121 | ||
| 119 | static void mixcomwd_timerfun(unsigned long d) | 122 | static void mixcomwd_timerfun(unsigned long d) |
| 120 | { | 123 | { |
| 121 | mixcomwd_ping(); | 124 | mixcomwd_ping(); |
| 122 | |||
| 123 | mod_timer(&mixcomwd_timer, jiffies + 5 * HZ); | 125 | mod_timer(&mixcomwd_timer, jiffies + 5 * HZ); |
| 124 | } | 126 | } |
| 125 | 127 | ||
| @@ -129,22 +131,22 @@ static void mixcomwd_timerfun(unsigned long d) | |||
| 129 | 131 | ||
| 130 | static int mixcomwd_open(struct inode *inode, struct file *file) | 132 | static int mixcomwd_open(struct inode *inode, struct file *file) |
| 131 | { | 133 | { |
| 132 | if(test_and_set_bit(0,&mixcomwd_opened)) { | 134 | if (test_and_set_bit(0, &mixcomwd_opened)) |
| 133 | return -EBUSY; | 135 | return -EBUSY; |
| 134 | } | 136 | |
| 135 | mixcomwd_ping(); | 137 | mixcomwd_ping(); |
| 136 | 138 | ||
| 137 | if (nowayout) { | 139 | if (nowayout) |
| 138 | /* | 140 | /* |
| 139 | * fops_get() code via open() has already done | 141 | * fops_get() code via open() has already done |
| 140 | * a try_module_get() so it is safe to do the | 142 | * a try_module_get() so it is safe to do the |
| 141 | * __module_get(). | 143 | * __module_get(). |
| 142 | */ | 144 | */ |
| 143 | __module_get(THIS_MODULE); | 145 | __module_get(THIS_MODULE); |
| 144 | } else { | 146 | else { |
| 145 | if(mixcomwd_timer_alive) { | 147 | if (mixcomwd_timer_alive) { |
| 146 | del_timer(&mixcomwd_timer); | 148 | del_timer(&mixcomwd_timer); |
| 147 | mixcomwd_timer_alive=0; | 149 | mixcomwd_timer_alive = 0; |
| 148 | } | 150 | } |
| 149 | } | 151 | } |
| 150 | return nonseekable_open(inode, file); | 152 | return nonseekable_open(inode, file); |
| @@ -153,26 +155,27 @@ static int mixcomwd_open(struct inode *inode, struct file *file) | |||
| 153 | static int mixcomwd_release(struct inode *inode, struct file *file) | 155 | static int mixcomwd_release(struct inode *inode, struct file *file) |
| 154 | { | 156 | { |
| 155 | if (expect_close == 42) { | 157 | if (expect_close == 42) { |
| 156 | if(mixcomwd_timer_alive) { | 158 | if (mixcomwd_timer_alive) { |
| 157 | printk(KERN_ERR PFX "release called while internal timer alive"); | 159 | printk(KERN_ERR PFX |
| 160 | "release called while internal timer alive"); | ||
| 158 | return -EBUSY; | 161 | return -EBUSY; |
| 159 | } | 162 | } |
| 160 | mixcomwd_timer_alive=1; | 163 | mixcomwd_timer_alive = 1; |
| 161 | mod_timer(&mixcomwd_timer, jiffies + 5 * HZ); | 164 | mod_timer(&mixcomwd_timer, jiffies + 5 * HZ); |
| 162 | } else { | 165 | } else |
| 163 | printk(KERN_CRIT PFX "WDT device closed unexpectedly. WDT will not stop!\n"); | 166 | printk(KERN_CRIT PFX |
| 164 | } | 167 | "WDT device closed unexpectedly. WDT will not stop!\n"); |
| 165 | 168 | ||
| 166 | clear_bit(0,&mixcomwd_opened); | 169 | clear_bit(0, &mixcomwd_opened); |
| 167 | expect_close=0; | 170 | expect_close = 0; |
| 168 | return 0; | 171 | return 0; |
| 169 | } | 172 | } |
| 170 | 173 | ||
| 171 | 174 | ||
| 172 | static ssize_t mixcomwd_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) | 175 | static ssize_t mixcomwd_write(struct file *file, const char __user *data, |
| 176 | size_t len, loff_t *ppos) | ||
| 173 | { | 177 | { |
| 174 | if(len) | 178 | if (len) { |
| 175 | { | ||
| 176 | if (!nowayout) { | 179 | if (!nowayout) { |
| 177 | size_t i; | 180 | size_t i; |
| 178 | 181 | ||
| @@ -192,8 +195,8 @@ static ssize_t mixcomwd_write(struct file *file, const char __user *data, size_t | |||
| 192 | return len; | 195 | return len; |
| 193 | } | 196 | } |
| 194 | 197 | ||
| 195 | static int mixcomwd_ioctl(struct inode *inode, struct file *file, | 198 | static long mixcomwd_ioctl(struct file *file, |
| 196 | unsigned int cmd, unsigned long arg) | 199 | unsigned int cmd, unsigned long arg) |
| 197 | { | 200 | { |
| 198 | void __user *argp = (void __user *)arg; | 201 | void __user *argp = (void __user *)arg; |
| 199 | int __user *p = argp; | 202 | int __user *p = argp; |
| @@ -204,32 +207,23 @@ static int mixcomwd_ioctl(struct inode *inode, struct file *file, | |||
| 204 | .identity = "MixCOM watchdog", | 207 | .identity = "MixCOM watchdog", |
| 205 | }; | 208 | }; |
| 206 | 209 | ||
| 207 | switch(cmd) | 210 | switch (cmd) { |
| 208 | { | 211 | case WDIOC_GETSUPPORT: |
| 209 | case WDIOC_GETSTATUS: | 212 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 210 | status=mixcomwd_opened; | 213 | return -EFAULT; |
| 211 | if (!nowayout) { | 214 | break; |
| 212 | status|=mixcomwd_timer_alive; | 215 | case WDIOC_GETSTATUS: |
| 213 | } | 216 | status = mixcomwd_opened; |
| 214 | if (copy_to_user(p, &status, sizeof(int))) { | 217 | if (!nowayout) |
| 215 | return -EFAULT; | 218 | status |= mixcomwd_timer_alive; |
| 216 | } | 219 | return put_user(status, p); |
| 217 | break; | 220 | case WDIOC_GETBOOTSTATUS: |
| 218 | case WDIOC_GETBOOTSTATUS: | 221 | return put_user(0, p); |
| 219 | if (copy_to_user(p, &status, sizeof(int))) { | 222 | case WDIOC_KEEPALIVE: |
| 220 | return -EFAULT; | 223 | mixcomwd_ping(); |
| 221 | } | 224 | break; |
| 222 | break; | 225 | default: |
| 223 | case WDIOC_GETSUPPORT: | 226 | return -ENOTTY; |
| 224 | if (copy_to_user(argp, &ident, sizeof(ident))) { | ||
| 225 | return -EFAULT; | ||
| 226 | } | ||
| 227 | break; | ||
| 228 | case WDIOC_KEEPALIVE: | ||
| 229 | mixcomwd_ping(); | ||
| 230 | break; | ||
| 231 | default: | ||
| 232 | return -ENOTTY; | ||
| 233 | } | 227 | } |
| 234 | return 0; | 228 | return 0; |
| 235 | } | 229 | } |
| @@ -238,7 +232,7 @@ static const struct file_operations mixcomwd_fops = { | |||
| 238 | .owner = THIS_MODULE, | 232 | .owner = THIS_MODULE, |
| 239 | .llseek = no_llseek, | 233 | .llseek = no_llseek, |
| 240 | .write = mixcomwd_write, | 234 | .write = mixcomwd_write, |
| 241 | .ioctl = mixcomwd_ioctl, | 235 | .unlocked_ioctl = mixcomwd_ioctl, |
| 242 | .open = mixcomwd_open, | 236 | .open = mixcomwd_open, |
| 243 | .release = mixcomwd_release, | 237 | .release = mixcomwd_release, |
| 244 | }; | 238 | }; |
| @@ -253,15 +247,14 @@ static int __init checkcard(int port, int card_id) | |||
| 253 | { | 247 | { |
| 254 | int id; | 248 | int id; |
| 255 | 249 | ||
| 256 | if (!request_region(port, 1, "MixCOM watchdog")) { | 250 | if (!request_region(port, 1, "MixCOM watchdog")) |
| 257 | return 0; | 251 | return 0; |
| 258 | } | ||
| 259 | 252 | ||
| 260 | id=inb_p(port); | 253 | id = inb_p(port); |
| 261 | if (card_id==MIXCOM_ID) | 254 | if (card_id == MIXCOM_ID) |
| 262 | id &= 0x3f; | 255 | id &= 0x3f; |
| 263 | 256 | ||
| 264 | if (id!=card_id) { | 257 | if (id != card_id) { |
| 265 | release_region(port, 1); | 258 | release_region(port, 1); |
| 266 | return 0; | 259 | return 0; |
| 267 | } | 260 | } |
| @@ -270,9 +263,7 @@ static int __init checkcard(int port, int card_id) | |||
| 270 | 263 | ||
| 271 | static int __init mixcomwd_init(void) | 264 | static int __init mixcomwd_init(void) |
| 272 | { | 265 | { |
| 273 | int i; | 266 | int i, ret, found = 0; |
| 274 | int ret; | ||
| 275 | int found=0; | ||
| 276 | 267 | ||
| 277 | for (i = 0; !found && mixcomwd_io_info[i].ioport != 0; i++) { | 268 | for (i = 0; !found && mixcomwd_io_info[i].ioport != 0; i++) { |
| 278 | if (checkcard(mixcomwd_io_info[i].ioport, | 269 | if (checkcard(mixcomwd_io_info[i].ioport, |
| @@ -283,20 +274,22 @@ static int __init mixcomwd_init(void) | |||
| 283 | } | 274 | } |
| 284 | 275 | ||
| 285 | if (!found) { | 276 | if (!found) { |
| 286 | printk(KERN_ERR PFX "No card detected, or port not available.\n"); | 277 | printk(KERN_ERR PFX |
| 278 | "No card detected, or port not available.\n"); | ||
| 287 | return -ENODEV; | 279 | return -ENODEV; |
| 288 | } | 280 | } |
| 289 | 281 | ||
| 290 | ret = misc_register(&mixcomwd_miscdev); | 282 | ret = misc_register(&mixcomwd_miscdev); |
| 291 | if (ret) | 283 | if (ret) { |
| 292 | { | 284 | printk(KERN_ERR PFX |
| 293 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 285 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 294 | WATCHDOG_MINOR, ret); | 286 | WATCHDOG_MINOR, ret); |
| 295 | goto error_misc_register_watchdog; | 287 | goto error_misc_register_watchdog; |
| 296 | } | 288 | } |
| 297 | 289 | ||
| 298 | printk(KERN_INFO "MixCOM watchdog driver v%s, watchdog port at 0x%3x\n", | 290 | printk(KERN_INFO |
| 299 | VERSION, watchdog_port); | 291 | "MixCOM watchdog driver v%s, watchdog port at 0x%3x\n", |
| 292 | VERSION, watchdog_port); | ||
| 300 | 293 | ||
| 301 | return 0; | 294 | return 0; |
| 302 | 295 | ||
| @@ -309,15 +302,15 @@ error_misc_register_watchdog: | |||
| 309 | static void __exit mixcomwd_exit(void) | 302 | static void __exit mixcomwd_exit(void) |
| 310 | { | 303 | { |
| 311 | if (!nowayout) { | 304 | if (!nowayout) { |
| 312 | if(mixcomwd_timer_alive) { | 305 | if (mixcomwd_timer_alive) { |
| 313 | printk(KERN_WARNING PFX "I quit now, hardware will" | 306 | printk(KERN_WARNING PFX "I quit now, hardware will" |
| 314 | " probably reboot!\n"); | 307 | " probably reboot!\n"); |
| 315 | del_timer_sync(&mixcomwd_timer); | 308 | del_timer_sync(&mixcomwd_timer); |
| 316 | mixcomwd_timer_alive=0; | 309 | mixcomwd_timer_alive = 0; |
| 317 | } | 310 | } |
| 318 | } | 311 | } |
| 319 | misc_deregister(&mixcomwd_miscdev); | 312 | misc_deregister(&mixcomwd_miscdev); |
| 320 | release_region(watchdog_port,1); | 313 | release_region(watchdog_port, 1); |
| 321 | } | 314 | } |
| 322 | 315 | ||
| 323 | module_init(mixcomwd_init); | 316 | module_init(mixcomwd_init); |
diff --git a/drivers/watchdog/mpc5200_wdt.c b/drivers/watchdog/mpc5200_wdt.c index 77c1c2ae2cc2..db91892558f2 100644 --- a/drivers/watchdog/mpc5200_wdt.c +++ b/drivers/watchdog/mpc5200_wdt.c | |||
| @@ -5,7 +5,7 @@ | |||
| 5 | #include <linux/io.h> | 5 | #include <linux/io.h> |
| 6 | #include <linux/spinlock.h> | 6 | #include <linux/spinlock.h> |
| 7 | #include <linux/of_platform.h> | 7 | #include <linux/of_platform.h> |
| 8 | #include <asm/uaccess.h> | 8 | #include <linux/uaccess.h> |
| 9 | #include <asm/mpc52xx.h> | 9 | #include <asm/mpc52xx.h> |
| 10 | 10 | ||
| 11 | 11 | ||
| @@ -57,7 +57,8 @@ static int mpc5200_wdt_start(struct mpc5200_wdt *wdt) | |||
| 57 | /* set timeout, with maximum prescaler */ | 57 | /* set timeout, with maximum prescaler */ |
| 58 | out_be32(&wdt->regs->count, 0x0 | wdt->count); | 58 | out_be32(&wdt->regs->count, 0x0 | wdt->count); |
| 59 | /* enable watchdog */ | 59 | /* enable watchdog */ |
| 60 | out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT | GPT_MODE_MS_TIMER); | 60 | out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT | |
| 61 | GPT_MODE_MS_TIMER); | ||
| 61 | spin_unlock(&wdt->io_lock); | 62 | spin_unlock(&wdt->io_lock); |
| 62 | 63 | ||
| 63 | return 0; | 64 | return 0; |
| @@ -66,7 +67,8 @@ static int mpc5200_wdt_ping(struct mpc5200_wdt *wdt) | |||
| 66 | { | 67 | { |
| 67 | spin_lock(&wdt->io_lock); | 68 | spin_lock(&wdt->io_lock); |
| 68 | /* writing A5 to OCPW resets the watchdog */ | 69 | /* writing A5 to OCPW resets the watchdog */ |
| 69 | out_be32(&wdt->regs->mode, 0xA5000000 | (0xffffff & in_be32(&wdt->regs->mode))); | 70 | out_be32(&wdt->regs->mode, 0xA5000000 | |
| 71 | (0xffffff & in_be32(&wdt->regs->mode))); | ||
| 70 | spin_unlock(&wdt->io_lock); | 72 | spin_unlock(&wdt->io_lock); |
| 71 | return 0; | 73 | return 0; |
| 72 | } | 74 | } |
| @@ -92,8 +94,8 @@ static struct watchdog_info mpc5200_wdt_info = { | |||
| 92 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | 94 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
| 93 | .identity = "mpc5200 watchdog on GPT0", | 95 | .identity = "mpc5200 watchdog on GPT0", |
| 94 | }; | 96 | }; |
| 95 | static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file, | 97 | static long mpc5200_wdt_ioctl(struct file *file, unsigned int cmd, |
| 96 | unsigned int cmd, unsigned long arg) | 98 | unsigned long arg) |
| 97 | { | 99 | { |
| 98 | struct mpc5200_wdt *wdt = file->private_data; | 100 | struct mpc5200_wdt *wdt = file->private_data; |
| 99 | int __user *data = (int __user *)arg; | 101 | int __user *data = (int __user *)arg; |
| @@ -103,7 +105,7 @@ static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 103 | switch (cmd) { | 105 | switch (cmd) { |
| 104 | case WDIOC_GETSUPPORT: | 106 | case WDIOC_GETSUPPORT: |
| 105 | ret = copy_to_user(data, &mpc5200_wdt_info, | 107 | ret = copy_to_user(data, &mpc5200_wdt_info, |
| 106 | sizeof(mpc5200_wdt_info)); | 108 | sizeof(mpc5200_wdt_info)); |
| 107 | if (ret) | 109 | if (ret) |
| 108 | ret = -EFAULT; | 110 | ret = -EFAULT; |
| 109 | break; | 111 | break; |
| @@ -135,6 +137,7 @@ static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 135 | } | 137 | } |
| 136 | return ret; | 138 | return ret; |
| 137 | } | 139 | } |
| 140 | |||
| 138 | static int mpc5200_wdt_open(struct inode *inode, struct file *file) | 141 | static int mpc5200_wdt_open(struct inode *inode, struct file *file) |
| 139 | { | 142 | { |
| 140 | /* /dev/watchdog can only be opened once */ | 143 | /* /dev/watchdog can only be opened once */ |
| @@ -161,13 +164,14 @@ static int mpc5200_wdt_release(struct inode *inode, struct file *file) | |||
| 161 | static const struct file_operations mpc5200_wdt_fops = { | 164 | static const struct file_operations mpc5200_wdt_fops = { |
| 162 | .owner = THIS_MODULE, | 165 | .owner = THIS_MODULE, |
| 163 | .write = mpc5200_wdt_write, | 166 | .write = mpc5200_wdt_write, |
| 164 | .ioctl = mpc5200_wdt_ioctl, | 167 | .unlocked_ioctl = mpc5200_wdt_ioctl, |
| 165 | .open = mpc5200_wdt_open, | 168 | .open = mpc5200_wdt_open, |
| 166 | .release = mpc5200_wdt_release, | 169 | .release = mpc5200_wdt_release, |
| 167 | }; | 170 | }; |
| 168 | 171 | ||
| 169 | /* module operations */ | 172 | /* module operations */ |
| 170 | static int mpc5200_wdt_probe(struct of_device *op, const struct of_device_id *match) | 173 | static int mpc5200_wdt_probe(struct of_device *op, |
| 174 | const struct of_device_id *match) | ||
| 171 | { | 175 | { |
| 172 | struct mpc5200_wdt *wdt; | 176 | struct mpc5200_wdt *wdt; |
| 173 | int err; | 177 | int err; |
| @@ -215,9 +219,9 @@ static int mpc5200_wdt_probe(struct of_device *op, const struct of_device_id *ma | |||
| 215 | return 0; | 219 | return 0; |
| 216 | 220 | ||
| 217 | iounmap(wdt->regs); | 221 | iounmap(wdt->regs); |
| 218 | out_release: | 222 | out_release: |
| 219 | release_mem_region(wdt->mem.start, size); | 223 | release_mem_region(wdt->mem.start, size); |
| 220 | out_free: | 224 | out_free: |
| 221 | kfree(wdt); | 225 | kfree(wdt); |
| 222 | return err; | 226 | return err; |
| 223 | } | 227 | } |
diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c deleted file mode 100644 index b16c5cd972eb..000000000000 --- a/drivers/watchdog/mpc83xx_wdt.c +++ /dev/null | |||
| @@ -1,230 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * mpc83xx_wdt.c - MPC83xx watchdog userspace interface | ||
| 3 | * | ||
| 4 | * Authors: Dave Updegraff <dave@cray.org> | ||
| 5 | * Kumar Gala <galak@kernel.crashing.org> | ||
| 6 | * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org> | ||
| 7 | * ..and from sc520_wdt | ||
| 8 | * | ||
| 9 | * Note: it appears that you can only actually ENABLE or DISABLE the thing | ||
| 10 | * once after POR. Once enabled, you cannot disable, and vice versa. | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify it | ||
| 13 | * under the terms of the GNU General Public License as published by the | ||
| 14 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 15 | * option) any later version. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/fs.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/miscdevice.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/module.h> | ||
| 24 | #include <linux/watchdog.h> | ||
| 25 | #include <asm/io.h> | ||
| 26 | #include <asm/uaccess.h> | ||
| 27 | |||
| 28 | struct mpc83xx_wdt { | ||
| 29 | __be32 res0; | ||
| 30 | __be32 swcrr; /* System watchdog control register */ | ||
| 31 | #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ | ||
| 32 | #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ | ||
| 33 | #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ | ||
| 34 | #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ | ||
| 35 | __be32 swcnr; /* System watchdog count register */ | ||
| 36 | u8 res1[2]; | ||
| 37 | __be16 swsrr; /* System watchdog service register */ | ||
| 38 | u8 res2[0xF0]; | ||
| 39 | }; | ||
| 40 | |||
| 41 | static struct mpc83xx_wdt __iomem *wd_base; | ||
| 42 | |||
| 43 | static u16 timeout = 0xffff; | ||
| 44 | module_param(timeout, ushort, 0); | ||
| 45 | MODULE_PARM_DESC(timeout, "Watchdog timeout in ticks. (0<timeout<65536, default=65535"); | ||
| 46 | |||
| 47 | static int reset = 1; | ||
| 48 | module_param(reset, bool, 0); | ||
| 49 | MODULE_PARM_DESC(reset, "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset"); | ||
| 50 | |||
| 51 | /* | ||
| 52 | * We always prescale, but if someone really doesn't want to they can set this | ||
| 53 | * to 0 | ||
| 54 | */ | ||
| 55 | static int prescale = 1; | ||
| 56 | static unsigned int timeout_sec; | ||
| 57 | |||
| 58 | static unsigned long wdt_is_open; | ||
| 59 | static DEFINE_SPINLOCK(wdt_spinlock); | ||
| 60 | |||
| 61 | static void mpc83xx_wdt_keepalive(void) | ||
| 62 | { | ||
| 63 | /* Ping the WDT */ | ||
| 64 | spin_lock(&wdt_spinlock); | ||
| 65 | out_be16(&wd_base->swsrr, 0x556c); | ||
| 66 | out_be16(&wd_base->swsrr, 0xaa39); | ||
| 67 | spin_unlock(&wdt_spinlock); | ||
| 68 | } | ||
| 69 | |||
| 70 | static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf, | ||
| 71 | size_t count, loff_t *ppos) | ||
| 72 | { | ||
| 73 | if (count) | ||
| 74 | mpc83xx_wdt_keepalive(); | ||
| 75 | return count; | ||
| 76 | } | ||
| 77 | |||
| 78 | static int mpc83xx_wdt_open(struct inode *inode, struct file *file) | ||
| 79 | { | ||
| 80 | u32 tmp = SWCRR_SWEN; | ||
| 81 | if (test_and_set_bit(0, &wdt_is_open)) | ||
| 82 | return -EBUSY; | ||
| 83 | |||
| 84 | /* Once we start the watchdog we can't stop it */ | ||
| 85 | __module_get(THIS_MODULE); | ||
| 86 | |||
| 87 | /* Good, fire up the show */ | ||
| 88 | if (prescale) | ||
| 89 | tmp |= SWCRR_SWPR; | ||
| 90 | if (reset) | ||
| 91 | tmp |= SWCRR_SWRI; | ||
| 92 | |||
| 93 | tmp |= timeout << 16; | ||
| 94 | |||
| 95 | out_be32(&wd_base->swcrr, tmp); | ||
| 96 | |||
| 97 | return nonseekable_open(inode, file); | ||
| 98 | } | ||
| 99 | |||
| 100 | static int mpc83xx_wdt_release(struct inode *inode, struct file *file) | ||
| 101 | { | ||
| 102 | printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n"); | ||
| 103 | mpc83xx_wdt_keepalive(); | ||
| 104 | clear_bit(0, &wdt_is_open); | ||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static int mpc83xx_wdt_ioctl(struct inode *inode, struct file *file, | ||
| 109 | unsigned int cmd, unsigned long arg) | ||
| 110 | { | ||
| 111 | void __user *argp = (void __user *)arg; | ||
| 112 | int __user *p = argp; | ||
| 113 | static struct watchdog_info ident = { | ||
| 114 | .options = WDIOF_KEEPALIVEPING, | ||
| 115 | .firmware_version = 1, | ||
| 116 | .identity = "MPC83xx", | ||
| 117 | }; | ||
| 118 | |||
| 119 | switch (cmd) { | ||
| 120 | case WDIOC_GETSUPPORT: | ||
| 121 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 122 | case WDIOC_GETSTATUS: | ||
| 123 | case WDIOC_GETBOOTSTATUS: | ||
| 124 | return put_user(0, p); | ||
| 125 | case WDIOC_KEEPALIVE: | ||
| 126 | mpc83xx_wdt_keepalive(); | ||
| 127 | return 0; | ||
| 128 | case WDIOC_GETTIMEOUT: | ||
| 129 | return put_user(timeout_sec, p); | ||
| 130 | default: | ||
| 131 | return -ENOTTY; | ||
| 132 | } | ||
| 133 | } | ||
| 134 | |||
| 135 | static const struct file_operations mpc83xx_wdt_fops = { | ||
| 136 | .owner = THIS_MODULE, | ||
| 137 | .llseek = no_llseek, | ||
| 138 | .write = mpc83xx_wdt_write, | ||
| 139 | .ioctl = mpc83xx_wdt_ioctl, | ||
| 140 | .open = mpc83xx_wdt_open, | ||
| 141 | .release = mpc83xx_wdt_release, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static struct miscdevice mpc83xx_wdt_miscdev = { | ||
| 145 | .minor = WATCHDOG_MINOR, | ||
| 146 | .name = "watchdog", | ||
| 147 | .fops = &mpc83xx_wdt_fops, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static int __devinit mpc83xx_wdt_probe(struct platform_device *dev) | ||
| 151 | { | ||
| 152 | struct resource *r; | ||
| 153 | int ret; | ||
| 154 | unsigned int *freq = dev->dev.platform_data; | ||
| 155 | |||
| 156 | /* get a pointer to the register memory */ | ||
| 157 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); | ||
| 158 | |||
| 159 | if (!r) { | ||
| 160 | ret = -ENODEV; | ||
| 161 | goto err_out; | ||
| 162 | } | ||
| 163 | |||
| 164 | wd_base = ioremap(r->start, sizeof (struct mpc83xx_wdt)); | ||
| 165 | |||
| 166 | if (wd_base == NULL) { | ||
| 167 | ret = -ENOMEM; | ||
| 168 | goto err_out; | ||
| 169 | } | ||
| 170 | |||
| 171 | ret = misc_register(&mpc83xx_wdt_miscdev); | ||
| 172 | if (ret) { | ||
| 173 | printk(KERN_ERR "cannot register miscdev on minor=%d " | ||
| 174 | "(err=%d)\n", | ||
| 175 | WATCHDOG_MINOR, ret); | ||
| 176 | goto err_unmap; | ||
| 177 | } | ||
| 178 | |||
| 179 | /* Calculate the timeout in seconds */ | ||
| 180 | if (prescale) | ||
| 181 | timeout_sec = (timeout * 0x10000) / (*freq); | ||
| 182 | else | ||
| 183 | timeout_sec = timeout / (*freq); | ||
| 184 | |||
| 185 | printk(KERN_INFO "WDT driver for MPC83xx initialized. " | ||
| 186 | "mode:%s timeout=%d (%d seconds)\n", | ||
| 187 | reset ? "reset":"interrupt", timeout, timeout_sec); | ||
| 188 | return 0; | ||
| 189 | |||
| 190 | err_unmap: | ||
| 191 | iounmap(wd_base); | ||
| 192 | err_out: | ||
| 193 | return ret; | ||
| 194 | } | ||
| 195 | |||
| 196 | static int __devexit mpc83xx_wdt_remove(struct platform_device *dev) | ||
| 197 | { | ||
| 198 | misc_deregister(&mpc83xx_wdt_miscdev); | ||
| 199 | iounmap(wd_base); | ||
| 200 | |||
| 201 | return 0; | ||
| 202 | } | ||
| 203 | |||
| 204 | static struct platform_driver mpc83xx_wdt_driver = { | ||
| 205 | .probe = mpc83xx_wdt_probe, | ||
| 206 | .remove = __devexit_p(mpc83xx_wdt_remove), | ||
| 207 | .driver = { | ||
| 208 | .name = "mpc83xx_wdt", | ||
| 209 | .owner = THIS_MODULE, | ||
| 210 | }, | ||
| 211 | }; | ||
| 212 | |||
| 213 | static int __init mpc83xx_wdt_init(void) | ||
| 214 | { | ||
| 215 | return platform_driver_register(&mpc83xx_wdt_driver); | ||
| 216 | } | ||
| 217 | |||
| 218 | static void __exit mpc83xx_wdt_exit(void) | ||
| 219 | { | ||
| 220 | platform_driver_unregister(&mpc83xx_wdt_driver); | ||
| 221 | } | ||
| 222 | |||
| 223 | module_init(mpc83xx_wdt_init); | ||
| 224 | module_exit(mpc83xx_wdt_exit); | ||
| 225 | |||
| 226 | MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); | ||
| 227 | MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx uProcessor"); | ||
| 228 | MODULE_LICENSE("GPL"); | ||
| 229 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | ||
| 230 | MODULE_ALIAS("platform:mpc83xx_wdt"); | ||
diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c index 85b5734403a5..1336425acf20 100644 --- a/drivers/watchdog/mpc8xx_wdt.c +++ b/drivers/watchdog/mpc8xx_wdt.c | |||
| @@ -16,36 +16,35 @@ | |||
| 16 | #include <linux/module.h> | 16 | #include <linux/module.h> |
| 17 | #include <linux/watchdog.h> | 17 | #include <linux/watchdog.h> |
| 18 | #include <asm/8xx_immap.h> | 18 | #include <asm/8xx_immap.h> |
| 19 | #include <asm/uaccess.h> | 19 | #include <linux/uaccess.h> |
| 20 | #include <asm/io.h> | 20 | #include <linux/io.h> |
| 21 | #include <syslib/m8xx_wdt.h> | 21 | #include <syslib/m8xx_wdt.h> |
| 22 | 22 | ||
| 23 | static unsigned long wdt_opened; | 23 | static unsigned long wdt_opened; |
| 24 | static int wdt_status; | 24 | static int wdt_status; |
| 25 | static spinlock_t wdt_lock; | ||
| 25 | 26 | ||
| 26 | static void mpc8xx_wdt_handler_disable(void) | 27 | static void mpc8xx_wdt_handler_disable(void) |
| 27 | { | 28 | { |
| 28 | volatile uint __iomem *piscr; | 29 | volatile uint __iomem *piscr; |
| 29 | piscr = (uint *)&((immap_t*)IMAP_ADDR)->im_sit.sit_piscr; | 30 | piscr = (uint *)&((immap_t *)IMAP_ADDR)->im_sit.sit_piscr; |
| 30 | 31 | ||
| 31 | if (!m8xx_has_internal_rtc) | 32 | if (!m8xx_has_internal_rtc) |
| 32 | m8xx_wdt_stop_timer(); | 33 | m8xx_wdt_stop_timer(); |
| 33 | else | 34 | else |
| 34 | out_be32(piscr, in_be32(piscr) & ~(PISCR_PIE | PISCR_PTE)); | 35 | out_be32(piscr, in_be32(piscr) & ~(PISCR_PIE | PISCR_PTE)); |
| 35 | |||
| 36 | printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler deactivated\n"); | 36 | printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler deactivated\n"); |
| 37 | } | 37 | } |
| 38 | 38 | ||
| 39 | static void mpc8xx_wdt_handler_enable(void) | 39 | static void mpc8xx_wdt_handler_enable(void) |
| 40 | { | 40 | { |
| 41 | volatile uint __iomem *piscr; | 41 | volatile uint __iomem *piscr; |
| 42 | piscr = (uint *)&((immap_t*)IMAP_ADDR)->im_sit.sit_piscr; | 42 | piscr = (uint *)&((immap_t *)IMAP_ADDR)->im_sit.sit_piscr; |
| 43 | 43 | ||
| 44 | if (!m8xx_has_internal_rtc) | 44 | if (!m8xx_has_internal_rtc) |
| 45 | m8xx_wdt_install_timer(); | 45 | m8xx_wdt_install_timer(); |
| 46 | else | 46 | else |
| 47 | out_be32(piscr, in_be32(piscr) | PISCR_PIE | PISCR_PTE); | 47 | out_be32(piscr, in_be32(piscr) | PISCR_PIE | PISCR_PTE); |
| 48 | |||
| 49 | printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler activated\n"); | 48 | printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler activated\n"); |
| 50 | } | 49 | } |
| 51 | 50 | ||
| @@ -53,37 +52,34 @@ static int mpc8xx_wdt_open(struct inode *inode, struct file *file) | |||
| 53 | { | 52 | { |
| 54 | if (test_and_set_bit(0, &wdt_opened)) | 53 | if (test_and_set_bit(0, &wdt_opened)) |
| 55 | return -EBUSY; | 54 | return -EBUSY; |
| 56 | |||
| 57 | m8xx_wdt_reset(); | 55 | m8xx_wdt_reset(); |
| 58 | mpc8xx_wdt_handler_disable(); | 56 | mpc8xx_wdt_handler_disable(); |
| 59 | |||
| 60 | return nonseekable_open(inode, file); | 57 | return nonseekable_open(inode, file); |
| 61 | } | 58 | } |
| 62 | 59 | ||
| 63 | static int mpc8xx_wdt_release(struct inode *inode, struct file *file) | 60 | static int mpc8xx_wdt_release(struct inode *inode, struct file *file) |
| 64 | { | 61 | { |
| 65 | m8xx_wdt_reset(); | 62 | m8xx_wdt_reset(); |
| 66 | |||
| 67 | #if !defined(CONFIG_WATCHDOG_NOWAYOUT) | 63 | #if !defined(CONFIG_WATCHDOG_NOWAYOUT) |
| 68 | mpc8xx_wdt_handler_enable(); | 64 | mpc8xx_wdt_handler_enable(); |
| 69 | #endif | 65 | #endif |
| 70 | |||
| 71 | clear_bit(0, &wdt_opened); | 66 | clear_bit(0, &wdt_opened); |
| 72 | |||
| 73 | return 0; | 67 | return 0; |
| 74 | } | 68 | } |
| 75 | 69 | ||
| 76 | static ssize_t mpc8xx_wdt_write(struct file *file, const char *data, size_t len, | 70 | static ssize_t mpc8xx_wdt_write(struct file *file, const char *data, |
| 77 | loff_t * ppos) | 71 | size_t len, loff_t *ppos) |
| 78 | { | 72 | { |
| 79 | if (len) | 73 | if (len) { |
| 74 | spin_lock(&wdt_lock); | ||
| 80 | m8xx_wdt_reset(); | 75 | m8xx_wdt_reset(); |
| 81 | 76 | spin_unlock(&wdt_lock); | |
| 77 | } | ||
| 82 | return len; | 78 | return len; |
| 83 | } | 79 | } |
| 84 | 80 | ||
| 85 | static int mpc8xx_wdt_ioctl(struct inode *inode, struct file *file, | 81 | static long mpc8xx_wdt_ioctl(struct file *file, |
| 86 | unsigned int cmd, unsigned long arg) | 82 | unsigned int cmd, unsigned long arg) |
| 87 | { | 83 | { |
| 88 | int timeout; | 84 | int timeout; |
| 89 | static struct watchdog_info info = { | 85 | static struct watchdog_info info = { |
| @@ -112,15 +108,19 @@ static int mpc8xx_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 112 | return -EOPNOTSUPP; | 108 | return -EOPNOTSUPP; |
| 113 | 109 | ||
| 114 | case WDIOC_KEEPALIVE: | 110 | case WDIOC_KEEPALIVE: |
| 111 | spin_lock(&wdt_lock); | ||
| 115 | m8xx_wdt_reset(); | 112 | m8xx_wdt_reset(); |
| 116 | wdt_status |= WDIOF_KEEPALIVEPING; | 113 | wdt_status |= WDIOF_KEEPALIVEPING; |
| 114 | spin_unlock(&wdt_lock); | ||
| 117 | break; | 115 | break; |
| 118 | 116 | ||
| 119 | case WDIOC_SETTIMEOUT: | 117 | case WDIOC_SETTIMEOUT: |
| 120 | return -EOPNOTSUPP; | 118 | return -EOPNOTSUPP; |
| 121 | 119 | ||
| 122 | case WDIOC_GETTIMEOUT: | 120 | case WDIOC_GETTIMEOUT: |
| 121 | spin_lock(&wdt_lock); | ||
| 123 | timeout = m8xx_wdt_get_timeout(); | 122 | timeout = m8xx_wdt_get_timeout(); |
| 123 | spin_unlock(&wdt_lock); | ||
| 124 | if (put_user(timeout, (int *)arg)) | 124 | if (put_user(timeout, (int *)arg)) |
| 125 | return -EFAULT; | 125 | return -EFAULT; |
| 126 | break; | 126 | break; |
| @@ -136,7 +136,7 @@ static const struct file_operations mpc8xx_wdt_fops = { | |||
| 136 | .owner = THIS_MODULE, | 136 | .owner = THIS_MODULE, |
| 137 | .llseek = no_llseek, | 137 | .llseek = no_llseek, |
| 138 | .write = mpc8xx_wdt_write, | 138 | .write = mpc8xx_wdt_write, |
| 139 | .ioctl = mpc8xx_wdt_ioctl, | 139 | .unlocked_ioctl = mpc8xx_wdt_ioctl, |
| 140 | .open = mpc8xx_wdt_open, | 140 | .open = mpc8xx_wdt_open, |
| 141 | .release = mpc8xx_wdt_release, | 141 | .release = mpc8xx_wdt_release, |
| 142 | }; | 142 | }; |
| @@ -149,6 +149,7 @@ static struct miscdevice mpc8xx_wdt_miscdev = { | |||
| 149 | 149 | ||
| 150 | static int __init mpc8xx_wdt_init(void) | 150 | static int __init mpc8xx_wdt_init(void) |
| 151 | { | 151 | { |
| 152 | spin_lock_init(&wdt_lock); | ||
| 152 | return misc_register(&mpc8xx_wdt_miscdev); | 153 | return misc_register(&mpc8xx_wdt_miscdev); |
| 153 | } | 154 | } |
| 154 | 155 | ||
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c new file mode 100644 index 000000000000..f2094960e662 --- /dev/null +++ b/drivers/watchdog/mpc8xxx_wdt.c | |||
| @@ -0,0 +1,316 @@ | |||
| 1 | /* | ||
| 2 | * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface | ||
| 3 | * | ||
| 4 | * Authors: Dave Updegraff <dave@cray.org> | ||
| 5 | * Kumar Gala <galak@kernel.crashing.org> | ||
| 6 | * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org> | ||
| 7 | * ..and from sc520_wdt | ||
| 8 | * Copyright (c) 2008 MontaVista Software, Inc. | ||
| 9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | ||
| 10 | * | ||
| 11 | * Note: it appears that you can only actually ENABLE or DISABLE the thing | ||
| 12 | * once after POR. Once enabled, you cannot disable, and vice versa. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify it | ||
| 15 | * under the terms of the GNU General Public License as published by the | ||
| 16 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 17 | * option) any later version. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/fs.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/timer.h> | ||
| 24 | #include <linux/miscdevice.h> | ||
| 25 | #include <linux/of_platform.h> | ||
| 26 | #include <linux/module.h> | ||
| 27 | #include <linux/watchdog.h> | ||
| 28 | #include <linux/io.h> | ||
| 29 | #include <linux/uaccess.h> | ||
| 30 | #include <sysdev/fsl_soc.h> | ||
| 31 | |||
| 32 | struct mpc8xxx_wdt { | ||
| 33 | __be32 res0; | ||
| 34 | __be32 swcrr; /* System watchdog control register */ | ||
| 35 | #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ | ||
| 36 | #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ | ||
| 37 | #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ | ||
| 38 | #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ | ||
| 39 | __be32 swcnr; /* System watchdog count register */ | ||
| 40 | u8 res1[2]; | ||
| 41 | __be16 swsrr; /* System watchdog service register */ | ||
| 42 | u8 res2[0xF0]; | ||
| 43 | }; | ||
| 44 | |||
| 45 | struct mpc8xxx_wdt_type { | ||
| 46 | int prescaler; | ||
| 47 | bool hw_enabled; | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct mpc8xxx_wdt __iomem *wd_base; | ||
| 51 | |||
| 52 | static u16 timeout = 0xffff; | ||
| 53 | module_param(timeout, ushort, 0); | ||
| 54 | MODULE_PARM_DESC(timeout, | ||
| 55 | "Watchdog timeout in ticks. (0<timeout<65536, default=65535"); | ||
| 56 | |||
| 57 | static int reset = 1; | ||
| 58 | module_param(reset, bool, 0); | ||
| 59 | MODULE_PARM_DESC(reset, | ||
| 60 | "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset"); | ||
| 61 | |||
| 62 | static int nowayout = WATCHDOG_NOWAYOUT; | ||
| 63 | module_param(nowayout, int, 0); | ||
| 64 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " | ||
| 65 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 66 | |||
| 67 | /* | ||
| 68 | * We always prescale, but if someone really doesn't want to they can set this | ||
| 69 | * to 0 | ||
| 70 | */ | ||
| 71 | static int prescale = 1; | ||
| 72 | static unsigned int timeout_sec; | ||
| 73 | |||
| 74 | static unsigned long wdt_is_open; | ||
| 75 | static DEFINE_SPINLOCK(wdt_spinlock); | ||
| 76 | |||
| 77 | static void mpc8xxx_wdt_keepalive(void) | ||
| 78 | { | ||
| 79 | /* Ping the WDT */ | ||
| 80 | spin_lock(&wdt_spinlock); | ||
| 81 | out_be16(&wd_base->swsrr, 0x556c); | ||
| 82 | out_be16(&wd_base->swsrr, 0xaa39); | ||
| 83 | spin_unlock(&wdt_spinlock); | ||
| 84 | } | ||
| 85 | |||
| 86 | static void mpc8xxx_wdt_timer_ping(unsigned long arg); | ||
| 87 | static DEFINE_TIMER(wdt_timer, mpc8xxx_wdt_timer_ping, 0, 0); | ||
| 88 | |||
| 89 | static void mpc8xxx_wdt_timer_ping(unsigned long arg) | ||
| 90 | { | ||
| 91 | mpc8xxx_wdt_keepalive(); | ||
| 92 | /* We're pinging it twice faster than needed, just to be sure. */ | ||
| 93 | mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2); | ||
| 94 | } | ||
| 95 | |||
| 96 | static void mpc8xxx_wdt_pr_warn(const char *msg) | ||
| 97 | { | ||
| 98 | pr_crit("mpc8xxx_wdt: %s, expect the %s soon!\n", msg, | ||
| 99 | reset ? "reset" : "machine check exception"); | ||
| 100 | } | ||
| 101 | |||
| 102 | static ssize_t mpc8xxx_wdt_write(struct file *file, const char __user *buf, | ||
| 103 | size_t count, loff_t *ppos) | ||
| 104 | { | ||
| 105 | if (count) | ||
| 106 | mpc8xxx_wdt_keepalive(); | ||
| 107 | return count; | ||
| 108 | } | ||
| 109 | |||
| 110 | static int mpc8xxx_wdt_open(struct inode *inode, struct file *file) | ||
| 111 | { | ||
| 112 | u32 tmp = SWCRR_SWEN; | ||
| 113 | if (test_and_set_bit(0, &wdt_is_open)) | ||
| 114 | return -EBUSY; | ||
| 115 | |||
| 116 | /* Once we start the watchdog we can't stop it */ | ||
| 117 | if (nowayout) | ||
| 118 | __module_get(THIS_MODULE); | ||
| 119 | |||
| 120 | /* Good, fire up the show */ | ||
| 121 | if (prescale) | ||
| 122 | tmp |= SWCRR_SWPR; | ||
| 123 | if (reset) | ||
| 124 | tmp |= SWCRR_SWRI; | ||
| 125 | |||
| 126 | tmp |= timeout << 16; | ||
| 127 | |||
| 128 | out_be32(&wd_base->swcrr, tmp); | ||
| 129 | |||
| 130 | del_timer_sync(&wdt_timer); | ||
| 131 | |||
| 132 | return nonseekable_open(inode, file); | ||
| 133 | } | ||
| 134 | |||
| 135 | static int mpc8xxx_wdt_release(struct inode *inode, struct file *file) | ||
| 136 | { | ||
| 137 | if (!nowayout) | ||
| 138 | mpc8xxx_wdt_timer_ping(0); | ||
| 139 | else | ||
| 140 | mpc8xxx_wdt_pr_warn("watchdog closed"); | ||
| 141 | clear_bit(0, &wdt_is_open); | ||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | static long mpc8xxx_wdt_ioctl(struct file *file, unsigned int cmd, | ||
| 146 | unsigned long arg) | ||
| 147 | { | ||
| 148 | void __user *argp = (void __user *)arg; | ||
| 149 | int __user *p = argp; | ||
| 150 | static struct watchdog_info ident = { | ||
| 151 | .options = WDIOF_KEEPALIVEPING, | ||
| 152 | .firmware_version = 1, | ||
| 153 | .identity = "MPC8xxx", | ||
| 154 | }; | ||
| 155 | |||
| 156 | switch (cmd) { | ||
| 157 | case WDIOC_GETSUPPORT: | ||
| 158 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 159 | case WDIOC_GETSTATUS: | ||
| 160 | case WDIOC_GETBOOTSTATUS: | ||
| 161 | return put_user(0, p); | ||
| 162 | case WDIOC_KEEPALIVE: | ||
| 163 | mpc8xxx_wdt_keepalive(); | ||
| 164 | return 0; | ||
| 165 | case WDIOC_GETTIMEOUT: | ||
| 166 | return put_user(timeout_sec, p); | ||
| 167 | default: | ||
| 168 | return -ENOTTY; | ||
| 169 | } | ||
| 170 | } | ||
| 171 | |||
| 172 | static const struct file_operations mpc8xxx_wdt_fops = { | ||
| 173 | .owner = THIS_MODULE, | ||
| 174 | .llseek = no_llseek, | ||
| 175 | .write = mpc8xxx_wdt_write, | ||
| 176 | .unlocked_ioctl = mpc8xxx_wdt_ioctl, | ||
| 177 | .open = mpc8xxx_wdt_open, | ||
| 178 | .release = mpc8xxx_wdt_release, | ||
| 179 | }; | ||
| 180 | |||
| 181 | static struct miscdevice mpc8xxx_wdt_miscdev = { | ||
| 182 | .minor = WATCHDOG_MINOR, | ||
| 183 | .name = "watchdog", | ||
| 184 | .fops = &mpc8xxx_wdt_fops, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static int __devinit mpc8xxx_wdt_probe(struct of_device *ofdev, | ||
| 188 | const struct of_device_id *match) | ||
| 189 | { | ||
| 190 | int ret; | ||
| 191 | struct device_node *np = ofdev->node; | ||
| 192 | struct mpc8xxx_wdt_type *wdt_type = match->data; | ||
| 193 | u32 freq = fsl_get_sys_freq(); | ||
| 194 | bool enabled; | ||
| 195 | |||
| 196 | if (!freq || freq == -1) | ||
| 197 | return -EINVAL; | ||
| 198 | |||
| 199 | wd_base = of_iomap(np, 0); | ||
| 200 | if (!wd_base) | ||
| 201 | return -ENOMEM; | ||
| 202 | |||
| 203 | enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN; | ||
| 204 | if (!enabled && wdt_type->hw_enabled) { | ||
| 205 | pr_info("mpc8xxx_wdt: could not be enabled in software\n"); | ||
| 206 | ret = -ENOSYS; | ||
| 207 | goto err_unmap; | ||
| 208 | } | ||
| 209 | |||
| 210 | /* Calculate the timeout in seconds */ | ||
| 211 | if (prescale) | ||
| 212 | timeout_sec = (timeout * wdt_type->prescaler) / freq; | ||
| 213 | else | ||
| 214 | timeout_sec = timeout / freq; | ||
| 215 | |||
| 216 | pr_info("WDT driver for MPC8xxx initialized. mode:%s timeout=%d " | ||
| 217 | "(%d seconds)\n", reset ? "reset" : "interrupt", timeout, | ||
| 218 | timeout_sec); | ||
| 219 | |||
| 220 | /* | ||
| 221 | * If the watchdog was previously enabled or we're running on | ||
| 222 | * MPC8xxx, we should ping the wdt from the kernel until the | ||
| 223 | * userspace handles it. | ||
| 224 | */ | ||
| 225 | if (enabled) | ||
| 226 | mpc8xxx_wdt_timer_ping(0); | ||
| 227 | return 0; | ||
| 228 | err_unmap: | ||
| 229 | iounmap(wd_base); | ||
| 230 | wd_base = NULL; | ||
| 231 | return ret; | ||
| 232 | } | ||
| 233 | |||
| 234 | static int __devexit mpc8xxx_wdt_remove(struct of_device *ofdev) | ||
| 235 | { | ||
| 236 | mpc8xxx_wdt_pr_warn("watchdog removed"); | ||
| 237 | del_timer_sync(&wdt_timer); | ||
| 238 | misc_deregister(&mpc8xxx_wdt_miscdev); | ||
| 239 | iounmap(wd_base); | ||
| 240 | |||
| 241 | return 0; | ||
| 242 | } | ||
| 243 | |||
| 244 | static const struct of_device_id mpc8xxx_wdt_match[] = { | ||
| 245 | { | ||
| 246 | .compatible = "mpc83xx_wdt", | ||
| 247 | .data = &(struct mpc8xxx_wdt_type) { | ||
| 248 | .prescaler = 0x10000, | ||
| 249 | }, | ||
| 250 | }, | ||
| 251 | { | ||
| 252 | .compatible = "fsl,mpc8610-wdt", | ||
| 253 | .data = &(struct mpc8xxx_wdt_type) { | ||
| 254 | .prescaler = 0x10000, | ||
| 255 | .hw_enabled = true, | ||
| 256 | }, | ||
| 257 | }, | ||
| 258 | { | ||
| 259 | .compatible = "fsl,mpc823-wdt", | ||
| 260 | .data = &(struct mpc8xxx_wdt_type) { | ||
| 261 | .prescaler = 0x800, | ||
| 262 | }, | ||
| 263 | }, | ||
| 264 | {}, | ||
| 265 | }; | ||
| 266 | MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match); | ||
| 267 | |||
| 268 | static struct of_platform_driver mpc8xxx_wdt_driver = { | ||
| 269 | .match_table = mpc8xxx_wdt_match, | ||
| 270 | .probe = mpc8xxx_wdt_probe, | ||
| 271 | .remove = __devexit_p(mpc8xxx_wdt_remove), | ||
| 272 | .driver = { | ||
| 273 | .name = "mpc8xxx_wdt", | ||
| 274 | .owner = THIS_MODULE, | ||
| 275 | }, | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* | ||
| 279 | * We do wdt initialization in two steps: arch_initcall probes the wdt | ||
| 280 | * very early to start pinging the watchdog (misc devices are not yet | ||
| 281 | * available), and later module_init() just registers the misc device. | ||
| 282 | */ | ||
| 283 | static int __init mpc8xxx_wdt_init_late(void) | ||
| 284 | { | ||
| 285 | int ret; | ||
| 286 | |||
| 287 | if (!wd_base) | ||
| 288 | return -ENODEV; | ||
| 289 | |||
| 290 | ret = misc_register(&mpc8xxx_wdt_miscdev); | ||
| 291 | if (ret) { | ||
| 292 | pr_err("cannot register miscdev on minor=%d (err=%d)\n", | ||
| 293 | WATCHDOG_MINOR, ret); | ||
| 294 | return ret; | ||
| 295 | } | ||
| 296 | return 0; | ||
| 297 | } | ||
| 298 | module_init(mpc8xxx_wdt_init_late); | ||
| 299 | |||
| 300 | static int __init mpc8xxx_wdt_init(void) | ||
| 301 | { | ||
| 302 | return of_register_platform_driver(&mpc8xxx_wdt_driver); | ||
| 303 | } | ||
| 304 | arch_initcall(mpc8xxx_wdt_init); | ||
| 305 | |||
| 306 | static void __exit mpc8xxx_wdt_exit(void) | ||
| 307 | { | ||
| 308 | of_unregister_platform_driver(&mpc8xxx_wdt_driver); | ||
| 309 | } | ||
| 310 | module_exit(mpc8xxx_wdt_exit); | ||
| 311 | |||
| 312 | MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); | ||
| 313 | MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx " | ||
| 314 | "uProcessors"); | ||
| 315 | MODULE_LICENSE("GPL"); | ||
| 316 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | ||
diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index 009573b81496..2a9bfa81f9d6 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c | |||
| @@ -29,9 +29,9 @@ | |||
| 29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
| 30 | #include <linux/interrupt.h> | 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/uaccess.h> | ||
| 32 | 33 | ||
| 33 | #include <asm/hardware/arm_twd.h> | 34 | #include <asm/hardware/arm_twd.h> |
| 34 | #include <asm/uaccess.h> | ||
| 35 | 35 | ||
| 36 | struct mpcore_wdt { | 36 | struct mpcore_wdt { |
| 37 | unsigned long timer_alive; | 37 | unsigned long timer_alive; |
| @@ -43,17 +43,20 @@ struct mpcore_wdt { | |||
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | static struct platform_device *mpcore_wdt_dev; | 45 | static struct platform_device *mpcore_wdt_dev; |
| 46 | |||
| 47 | extern unsigned int mpcore_timer_rate; | 46 | extern unsigned int mpcore_timer_rate; |
| 48 | 47 | ||
| 49 | #define TIMER_MARGIN 60 | 48 | #define TIMER_MARGIN 60 |
| 50 | static int mpcore_margin = TIMER_MARGIN; | 49 | static int mpcore_margin = TIMER_MARGIN; |
| 51 | module_param(mpcore_margin, int, 0); | 50 | module_param(mpcore_margin, int, 0); |
| 52 | MODULE_PARM_DESC(mpcore_margin, "MPcore timer margin in seconds. (0<mpcore_margin<65536, default=" __MODULE_STRING(TIMER_MARGIN) ")"); | 51 | MODULE_PARM_DESC(mpcore_margin, |
| 52 | "MPcore timer margin in seconds. (0 < mpcore_margin < 65536, default=" | ||
| 53 | __MODULE_STRING(TIMER_MARGIN) ")"); | ||
| 53 | 54 | ||
| 54 | static int nowayout = WATCHDOG_NOWAYOUT; | 55 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 55 | module_param(nowayout, int, 0); | 56 | module_param(nowayout, int, 0); |
| 56 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 57 | MODULE_PARM_DESC(nowayout, |
| 58 | "Watchdog cannot be stopped once started (default=" | ||
| 59 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 57 | 60 | ||
| 58 | #define ONLY_TESTING 0 | 61 | #define ONLY_TESTING 0 |
| 59 | static int mpcore_noboot = ONLY_TESTING; | 62 | static int mpcore_noboot = ONLY_TESTING; |
| @@ -70,14 +73,12 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg) | |||
| 70 | 73 | ||
| 71 | /* Check it really was our interrupt */ | 74 | /* Check it really was our interrupt */ |
| 72 | if (readl(wdt->base + TWD_WDOG_INTSTAT)) { | 75 | if (readl(wdt->base + TWD_WDOG_INTSTAT)) { |
| 73 | dev_printk(KERN_CRIT, wdt->dev, "Triggered - Reboot ignored.\n"); | 76 | dev_printk(KERN_CRIT, wdt->dev, |
| 74 | 77 | "Triggered - Reboot ignored.\n"); | |
| 75 | /* Clear the interrupt on the watchdog */ | 78 | /* Clear the interrupt on the watchdog */ |
| 76 | writel(1, wdt->base + TWD_WDOG_INTSTAT); | 79 | writel(1, wdt->base + TWD_WDOG_INTSTAT); |
| 77 | |||
| 78 | return IRQ_HANDLED; | 80 | return IRQ_HANDLED; |
| 79 | } | 81 | } |
| 80 | |||
| 81 | return IRQ_NONE; | 82 | return IRQ_NONE; |
| 82 | } | 83 | } |
| 83 | 84 | ||
| @@ -96,22 +97,26 @@ static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt) | |||
| 96 | count = (mpcore_timer_rate / 256) * mpcore_margin; | 97 | count = (mpcore_timer_rate / 256) * mpcore_margin; |
| 97 | 98 | ||
| 98 | /* Reload the counter */ | 99 | /* Reload the counter */ |
| 100 | spin_lock(&wdt_lock); | ||
| 99 | writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); | 101 | writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); |
| 100 | |||
| 101 | wdt->perturb = wdt->perturb ? 0 : 1; | 102 | wdt->perturb = wdt->perturb ? 0 : 1; |
| 103 | spin_unlock(&wdt_lock); | ||
| 102 | } | 104 | } |
| 103 | 105 | ||
| 104 | static void mpcore_wdt_stop(struct mpcore_wdt *wdt) | 106 | static void mpcore_wdt_stop(struct mpcore_wdt *wdt) |
| 105 | { | 107 | { |
| 108 | spin_lock(&wdt_lock); | ||
| 106 | writel(0x12345678, wdt->base + TWD_WDOG_DISABLE); | 109 | writel(0x12345678, wdt->base + TWD_WDOG_DISABLE); |
| 107 | writel(0x87654321, wdt->base + TWD_WDOG_DISABLE); | 110 | writel(0x87654321, wdt->base + TWD_WDOG_DISABLE); |
| 108 | writel(0x0, wdt->base + TWD_WDOG_CONTROL); | 111 | writel(0x0, wdt->base + TWD_WDOG_CONTROL); |
| 112 | spin_unlock(&wdt_lock); | ||
| 109 | } | 113 | } |
| 110 | 114 | ||
| 111 | static void mpcore_wdt_start(struct mpcore_wdt *wdt) | 115 | static void mpcore_wdt_start(struct mpcore_wdt *wdt) |
| 112 | { | 116 | { |
| 113 | dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n"); | 117 | dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n"); |
| 114 | 118 | ||
| 119 | spin_lock(&wdt_lock); | ||
| 115 | /* This loads the count register but does NOT start the count yet */ | 120 | /* This loads the count register but does NOT start the count yet */ |
| 116 | mpcore_wdt_keepalive(wdt); | 121 | mpcore_wdt_keepalive(wdt); |
| 117 | 122 | ||
| @@ -122,6 +127,7 @@ static void mpcore_wdt_start(struct mpcore_wdt *wdt) | |||
| 122 | /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ | 127 | /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ |
| 123 | writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); | 128 | writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); |
| 124 | } | 129 | } |
| 130 | spin_unlock(&wdt_lock); | ||
| 125 | } | 131 | } |
| 126 | 132 | ||
| 127 | static int mpcore_wdt_set_heartbeat(int t) | 133 | static int mpcore_wdt_set_heartbeat(int t) |
| @@ -164,10 +170,11 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file) | |||
| 164 | * Shut off the timer. | 170 | * Shut off the timer. |
| 165 | * Lock it in if it's a module and we set nowayout | 171 | * Lock it in if it's a module and we set nowayout |
| 166 | */ | 172 | */ |
| 167 | if (wdt->expect_close == 42) { | 173 | if (wdt->expect_close == 42) |
| 168 | mpcore_wdt_stop(wdt); | 174 | mpcore_wdt_stop(wdt); |
| 169 | } else { | 175 | else { |
| 170 | dev_printk(KERN_CRIT, wdt->dev, "unexpected close, not stopping watchdog!\n"); | 176 | dev_printk(KERN_CRIT, wdt->dev, |
| 177 | "unexpected close, not stopping watchdog!\n"); | ||
| 171 | mpcore_wdt_keepalive(wdt); | 178 | mpcore_wdt_keepalive(wdt); |
| 172 | } | 179 | } |
| 173 | clear_bit(0, &wdt->timer_alive); | 180 | clear_bit(0, &wdt->timer_alive); |
| @@ -175,7 +182,8 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file) | |||
| 175 | return 0; | 182 | return 0; |
| 176 | } | 183 | } |
| 177 | 184 | ||
| 178 | static ssize_t mpcore_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) | 185 | static ssize_t mpcore_wdt_write(struct file *file, const char *data, |
| 186 | size_t len, loff_t *ppos) | ||
| 179 | { | 187 | { |
| 180 | struct mpcore_wdt *wdt = file->private_data; | 188 | struct mpcore_wdt *wdt = file->private_data; |
| 181 | 189 | ||
| @@ -210,8 +218,8 @@ static struct watchdog_info ident = { | |||
| 210 | .identity = "MPcore Watchdog", | 218 | .identity = "MPcore Watchdog", |
| 211 | }; | 219 | }; |
| 212 | 220 | ||
| 213 | static int mpcore_wdt_ioctl(struct inode *inode, struct file *file, | 221 | static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd, |
| 214 | unsigned int cmd, unsigned long arg) | 222 | unsigned long arg) |
| 215 | { | 223 | { |
| 216 | struct mpcore_wdt *wdt = file->private_data; | 224 | struct mpcore_wdt *wdt = file->private_data; |
| 217 | int ret; | 225 | int ret; |
| @@ -235,6 +243,12 @@ static int mpcore_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 235 | ret = 0; | 243 | ret = 0; |
| 236 | break; | 244 | break; |
| 237 | 245 | ||
| 246 | case WDIOC_GETSTATUS: | ||
| 247 | case WDIOC_GETBOOTSTATUS: | ||
| 248 | uarg.i = 0; | ||
| 249 | ret = 0; | ||
| 250 | break; | ||
| 251 | |||
| 238 | case WDIOC_SETOPTIONS: | 252 | case WDIOC_SETOPTIONS: |
| 239 | ret = -EINVAL; | 253 | ret = -EINVAL; |
| 240 | if (uarg.i & WDIOS_DISABLECARD) { | 254 | if (uarg.i & WDIOS_DISABLECARD) { |
| @@ -247,12 +261,6 @@ static int mpcore_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 247 | } | 261 | } |
| 248 | break; | 262 | break; |
| 249 | 263 | ||
| 250 | case WDIOC_GETSTATUS: | ||
| 251 | case WDIOC_GETBOOTSTATUS: | ||
| 252 | uarg.i = 0; | ||
| 253 | ret = 0; | ||
| 254 | break; | ||
| 255 | |||
| 256 | case WDIOC_KEEPALIVE: | 264 | case WDIOC_KEEPALIVE: |
| 257 | mpcore_wdt_keepalive(wdt); | 265 | mpcore_wdt_keepalive(wdt); |
| 258 | ret = 0; | 266 | ret = 0; |
| @@ -301,7 +309,7 @@ static const struct file_operations mpcore_wdt_fops = { | |||
| 301 | .owner = THIS_MODULE, | 309 | .owner = THIS_MODULE, |
| 302 | .llseek = no_llseek, | 310 | .llseek = no_llseek, |
| 303 | .write = mpcore_wdt_write, | 311 | .write = mpcore_wdt_write, |
| 304 | .ioctl = mpcore_wdt_ioctl, | 312 | .unlocked_ioctl = mpcore_wdt_ioctl, |
| 305 | .open = mpcore_wdt_open, | 313 | .open = mpcore_wdt_open, |
| 306 | .release = mpcore_wdt_release, | 314 | .release = mpcore_wdt_release, |
| 307 | }; | 315 | }; |
| @@ -349,14 +357,17 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev) | |||
| 349 | mpcore_wdt_miscdev.parent = &dev->dev; | 357 | mpcore_wdt_miscdev.parent = &dev->dev; |
| 350 | ret = misc_register(&mpcore_wdt_miscdev); | 358 | ret = misc_register(&mpcore_wdt_miscdev); |
| 351 | if (ret) { | 359 | if (ret) { |
| 352 | dev_printk(KERN_ERR, _dev, "cannot register miscdev on minor=%d (err=%d)\n", | 360 | dev_printk(KERN_ERR, _dev, |
| 353 | WATCHDOG_MINOR, ret); | 361 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 362 | WATCHDOG_MINOR, ret); | ||
| 354 | goto err_misc; | 363 | goto err_misc; |
| 355 | } | 364 | } |
| 356 | 365 | ||
| 357 | ret = request_irq(wdt->irq, mpcore_wdt_fire, IRQF_DISABLED, "mpcore_wdt", wdt); | 366 | ret = request_irq(wdt->irq, mpcore_wdt_fire, IRQF_DISABLED, |
| 367 | "mpcore_wdt", wdt); | ||
| 358 | if (ret) { | 368 | if (ret) { |
| 359 | dev_printk(KERN_ERR, _dev, "cannot register IRQ%d for watchdog\n", wdt->irq); | 369 | dev_printk(KERN_ERR, _dev, |
| 370 | "cannot register IRQ%d for watchdog\n", wdt->irq); | ||
| 360 | goto err_irq; | 371 | goto err_irq; |
| 361 | } | 372 | } |
| 362 | 373 | ||
| @@ -366,13 +377,13 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev) | |||
| 366 | 377 | ||
| 367 | return 0; | 378 | return 0; |
| 368 | 379 | ||
| 369 | err_irq: | 380 | err_irq: |
| 370 | misc_deregister(&mpcore_wdt_miscdev); | 381 | misc_deregister(&mpcore_wdt_miscdev); |
| 371 | err_misc: | 382 | err_misc: |
| 372 | iounmap(wdt->base); | 383 | iounmap(wdt->base); |
| 373 | err_free: | 384 | err_free: |
| 374 | kfree(wdt); | 385 | kfree(wdt); |
| 375 | err_out: | 386 | err_out: |
| 376 | return ret; | 387 | return ret; |
| 377 | } | 388 | } |
| 378 | 389 | ||
| @@ -415,7 +426,7 @@ static int __init mpcore_wdt_init(void) | |||
| 415 | */ | 426 | */ |
| 416 | if (mpcore_wdt_set_heartbeat(mpcore_margin)) { | 427 | if (mpcore_wdt_set_heartbeat(mpcore_margin)) { |
| 417 | mpcore_wdt_set_heartbeat(TIMER_MARGIN); | 428 | mpcore_wdt_set_heartbeat(TIMER_MARGIN); |
| 418 | printk(KERN_INFO "mpcore_margin value must be 0<mpcore_margin<65536, using %d\n", | 429 | printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n", |
| 419 | TIMER_MARGIN); | 430 | TIMER_MARGIN); |
| 420 | } | 431 | } |
| 421 | 432 | ||
diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index a8e67383784e..b4b7b0a4c119 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c | |||
| @@ -1,7 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Driver for the MTX-1 Watchdog. | 2 | * Driver for the MTX-1 Watchdog. |
| 3 | * | 3 | * |
| 4 | * (C) Copyright 2005 4G Systems <info@4g-systems.biz>, All Rights Reserved. | 4 | * (C) Copyright 2005 4G Systems <info@4g-systems.biz>, |
| 5 | * All Rights Reserved. | ||
| 5 | * http://www.4g-systems.biz | 6 | * http://www.4g-systems.biz |
| 6 | * | 7 | * |
| 7 | * (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org> | 8 | * (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org> |
| @@ -46,12 +47,11 @@ | |||
| 46 | #include <linux/jiffies.h> | 47 | #include <linux/jiffies.h> |
| 47 | #include <linux/watchdog.h> | 48 | #include <linux/watchdog.h> |
| 48 | #include <linux/platform_device.h> | 49 | #include <linux/platform_device.h> |
| 49 | 50 | #include <linux/io.h> | |
| 50 | #include <asm/io.h> | 51 | #include <linux/uaccess.h> |
| 51 | #include <asm/uaccess.h> | 52 | #include <linux/gpio.h> |
| 52 | 53 | ||
| 53 | #include <asm/mach-au1x00/au1000.h> | 54 | #include <asm/mach-au1x00/au1000.h> |
| 54 | #include <asm/gpio.h> | ||
| 55 | 55 | ||
| 56 | #define MTX1_WDT_INTERVAL (5 * HZ) | 56 | #define MTX1_WDT_INTERVAL (5 * HZ) |
| 57 | 57 | ||
| @@ -59,6 +59,7 @@ static int ticks = 100 * HZ; | |||
| 59 | 59 | ||
| 60 | static struct { | 60 | static struct { |
| 61 | struct completion stop; | 61 | struct completion stop; |
| 62 | spinlock_t lock; | ||
| 62 | int running; | 63 | int running; |
| 63 | struct timer_list timer; | 64 | struct timer_list timer; |
| 64 | int queue; | 65 | int queue; |
| @@ -71,6 +72,7 @@ static void mtx1_wdt_trigger(unsigned long unused) | |||
| 71 | { | 72 | { |
| 72 | u32 tmp; | 73 | u32 tmp; |
| 73 | 74 | ||
| 75 | spin_lock(&mtx1_wdt_device.lock); | ||
| 74 | if (mtx1_wdt_device.running) | 76 | if (mtx1_wdt_device.running) |
| 75 | ticks--; | 77 | ticks--; |
| 76 | /* | 78 | /* |
| @@ -79,13 +81,13 @@ static void mtx1_wdt_trigger(unsigned long unused) | |||
| 79 | tmp = au_readl(GPIO2_DIR); | 81 | tmp = au_readl(GPIO2_DIR); |
| 80 | tmp = (tmp & ~(1 << mtx1_wdt_device.gpio)) | | 82 | tmp = (tmp & ~(1 << mtx1_wdt_device.gpio)) | |
| 81 | ((~tmp) & (1 << mtx1_wdt_device.gpio)); | 83 | ((~tmp) & (1 << mtx1_wdt_device.gpio)); |
| 82 | au_writel (tmp, GPIO2_DIR); | 84 | au_writel(tmp, GPIO2_DIR); |
| 83 | 85 | ||
| 84 | if (mtx1_wdt_device.queue && ticks) | 86 | if (mtx1_wdt_device.queue && ticks) |
| 85 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); | 87 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); |
| 86 | else { | 88 | else |
| 87 | complete(&mtx1_wdt_device.stop); | 89 | complete(&mtx1_wdt_device.stop); |
| 88 | } | 90 | spin_unlock(&mtx1_wdt_device.lock); |
| 89 | } | 91 | } |
| 90 | 92 | ||
| 91 | static void mtx1_wdt_reset(void) | 93 | static void mtx1_wdt_reset(void) |
| @@ -96,23 +98,25 @@ static void mtx1_wdt_reset(void) | |||
| 96 | 98 | ||
| 97 | static void mtx1_wdt_start(void) | 99 | static void mtx1_wdt_start(void) |
| 98 | { | 100 | { |
| 101 | spin_lock_irqsave(&mtx1_wdt_device.lock, flags); | ||
| 99 | if (!mtx1_wdt_device.queue) { | 102 | if (!mtx1_wdt_device.queue) { |
| 100 | mtx1_wdt_device.queue = 1; | 103 | mtx1_wdt_device.queue = 1; |
| 101 | gpio_set_value(mtx1_wdt_device.gpio, 1); | 104 | gpio_set_value(mtx1_wdt_device.gpio, 1); |
| 102 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); | 105 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); |
| 103 | } | 106 | } |
| 104 | mtx1_wdt_device.running++; | 107 | mtx1_wdt_device.running++; |
| 108 | spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); | ||
| 105 | } | 109 | } |
| 106 | 110 | ||
| 107 | static int mtx1_wdt_stop(void) | 111 | static int mtx1_wdt_stop(void) |
| 108 | { | 112 | { |
| 113 | spin_lock_irqsave(&mtx1_wdt_device.lock, flags); | ||
| 109 | if (mtx1_wdt_device.queue) { | 114 | if (mtx1_wdt_device.queue) { |
| 110 | mtx1_wdt_device.queue = 0; | 115 | mtx1_wdt_device.queue = 0; |
| 111 | gpio_set_value(mtx1_wdt_device.gpio, 0); | 116 | gpio_set_value(mtx1_wdt_device.gpio, 0); |
| 112 | } | 117 | } |
| 113 | |||
| 114 | ticks = mtx1_wdt_device.default_ticks; | 118 | ticks = mtx1_wdt_device.default_ticks; |
| 115 | 119 | spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); | |
| 116 | return 0; | 120 | return 0; |
| 117 | } | 121 | } |
| 118 | 122 | ||
| @@ -122,7 +126,6 @@ static int mtx1_wdt_open(struct inode *inode, struct file *file) | |||
| 122 | { | 126 | { |
| 123 | if (test_and_set_bit(0, &mtx1_wdt_device.inuse)) | 127 | if (test_and_set_bit(0, &mtx1_wdt_device.inuse)) |
| 124 | return -EBUSY; | 128 | return -EBUSY; |
| 125 | |||
| 126 | return nonseekable_open(inode, file); | 129 | return nonseekable_open(inode, file); |
| 127 | } | 130 | } |
| 128 | 131 | ||
| @@ -133,54 +136,51 @@ static int mtx1_wdt_release(struct inode *inode, struct file *file) | |||
| 133 | return 0; | 136 | return 0; |
| 134 | } | 137 | } |
| 135 | 138 | ||
| 136 | static int mtx1_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | 139 | static long mtx1_wdt_ioctl(struct file *file, unsigned int cmd, |
| 140 | unsigned long arg) | ||
| 137 | { | 141 | { |
| 138 | void __user *argp = (void __user *)arg; | 142 | void __user *argp = (void __user *)arg; |
| 143 | int __user *p = (int __user *)argp; | ||
| 139 | unsigned int value; | 144 | unsigned int value; |
| 140 | static struct watchdog_info ident = | 145 | static const struct watchdog_info ident = { |
| 141 | { | ||
| 142 | .options = WDIOF_CARDRESET, | 146 | .options = WDIOF_CARDRESET, |
| 143 | .identity = "MTX-1 WDT", | 147 | .identity = "MTX-1 WDT", |
| 144 | }; | 148 | }; |
| 145 | 149 | ||
| 146 | switch(cmd) { | 150 | switch (cmd) { |
| 147 | case WDIOC_KEEPALIVE: | 151 | case WDIOC_GETSUPPORT: |
| 148 | mtx1_wdt_reset(); | 152 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 149 | break; | 153 | return -EFAULT; |
| 150 | case WDIOC_GETSTATUS: | 154 | break; |
| 151 | case WDIOC_GETBOOTSTATUS: | 155 | case WDIOC_GETSTATUS: |
| 152 | if ( copy_to_user(argp, &value, sizeof(int)) ) | 156 | case WDIOC_GETBOOTSTATUS: |
| 153 | return -EFAULT; | 157 | put_user(0, p); |
| 154 | break; | 158 | break; |
| 155 | case WDIOC_GETSUPPORT: | 159 | case WDIOC_SETOPTIONS: |
| 156 | if ( copy_to_user(argp, &ident, sizeof(ident)) ) | 160 | if (get_user(value, p)) |
| 157 | return -EFAULT; | 161 | return -EFAULT; |
| 158 | break; | 162 | if (value & WDIOS_ENABLECARD) |
| 159 | case WDIOC_SETOPTIONS: | 163 | mtx1_wdt_start(); |
| 160 | if ( copy_from_user(&value, argp, sizeof(int)) ) | 164 | else if (value & WDIOS_DISABLECARD) |
| 161 | return -EFAULT; | 165 | mtx1_wdt_stop(); |
| 162 | switch(value) { | 166 | else |
| 163 | case WDIOS_ENABLECARD: | 167 | return -EINVAL; |
| 164 | mtx1_wdt_start(); | 168 | return 0; |
| 165 | break; | 169 | case WDIOC_KEEPALIVE: |
| 166 | case WDIOS_DISABLECARD: | 170 | mtx1_wdt_reset(); |
| 167 | return mtx1_wdt_stop(); | 171 | break; |
| 168 | default: | 172 | default: |
| 169 | return -EINVAL; | 173 | return -ENOTTY; |
| 170 | } | ||
| 171 | break; | ||
| 172 | default: | ||
| 173 | return -ENOTTY; | ||
| 174 | } | 174 | } |
| 175 | return 0; | 175 | return 0; |
| 176 | } | 176 | } |
| 177 | 177 | ||
| 178 | 178 | ||
| 179 | static ssize_t mtx1_wdt_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | 179 | static ssize_t mtx1_wdt_write(struct file *file, const char *buf, |
| 180 | size_t count, loff_t *ppos) | ||
| 180 | { | 181 | { |
| 181 | if (!count) | 182 | if (!count) |
| 182 | return -EIO; | 183 | return -EIO; |
| 183 | |||
| 184 | mtx1_wdt_reset(); | 184 | mtx1_wdt_reset(); |
| 185 | return count; | 185 | return count; |
| 186 | } | 186 | } |
| @@ -188,17 +188,17 @@ static ssize_t mtx1_wdt_write(struct file *file, const char *buf, size_t count, | |||
| 188 | static const struct file_operations mtx1_wdt_fops = { | 188 | static const struct file_operations mtx1_wdt_fops = { |
| 189 | .owner = THIS_MODULE, | 189 | .owner = THIS_MODULE, |
| 190 | .llseek = no_llseek, | 190 | .llseek = no_llseek, |
| 191 | .ioctl = mtx1_wdt_ioctl, | 191 | .unlocked_ioctl = mtx1_wdt_ioctl, |
| 192 | .open = mtx1_wdt_open, | 192 | .open = mtx1_wdt_open, |
| 193 | .write = mtx1_wdt_write, | 193 | .write = mtx1_wdt_write, |
| 194 | .release = mtx1_wdt_release | 194 | .release = mtx1_wdt_release, |
| 195 | }; | 195 | }; |
| 196 | 196 | ||
| 197 | 197 | ||
| 198 | static struct miscdevice mtx1_wdt_misc = { | 198 | static struct miscdevice mtx1_wdt_misc = { |
| 199 | .minor = WATCHDOG_MINOR, | 199 | .minor = WATCHDOG_MINOR, |
| 200 | .name = "watchdog", | 200 | .name = "watchdog", |
| 201 | .fops = &mtx1_wdt_fops | 201 | .fops = &mtx1_wdt_fops, |
| 202 | }; | 202 | }; |
| 203 | 203 | ||
| 204 | 204 | ||
| @@ -208,29 +208,26 @@ static int mtx1_wdt_probe(struct platform_device *pdev) | |||
| 208 | 208 | ||
| 209 | mtx1_wdt_device.gpio = pdev->resource[0].start; | 209 | mtx1_wdt_device.gpio = pdev->resource[0].start; |
| 210 | 210 | ||
| 211 | if ((ret = misc_register(&mtx1_wdt_misc)) < 0) { | 211 | spin_lock_init(&mtx1_wdt_device.lock); |
| 212 | printk(KERN_ERR " mtx-1_wdt : failed to register\n"); | ||
| 213 | return ret; | ||
| 214 | } | ||
| 215 | |||
| 216 | init_completion(&mtx1_wdt_device.stop); | 212 | init_completion(&mtx1_wdt_device.stop); |
| 217 | mtx1_wdt_device.queue = 0; | 213 | mtx1_wdt_device.queue = 0; |
| 218 | |||
| 219 | clear_bit(0, &mtx1_wdt_device.inuse); | 214 | clear_bit(0, &mtx1_wdt_device.inuse); |
| 220 | |||
| 221 | setup_timer(&mtx1_wdt_device.timer, mtx1_wdt_trigger, 0L); | 215 | setup_timer(&mtx1_wdt_device.timer, mtx1_wdt_trigger, 0L); |
| 222 | |||
| 223 | mtx1_wdt_device.default_ticks = ticks; | 216 | mtx1_wdt_device.default_ticks = ticks; |
| 224 | 217 | ||
| 218 | ret = misc_register(&mtx1_wdt_misc); | ||
| 219 | if (ret < 0) { | ||
| 220 | printk(KERN_ERR " mtx-1_wdt : failed to register\n"); | ||
| 221 | return ret; | ||
| 222 | } | ||
| 225 | mtx1_wdt_start(); | 223 | mtx1_wdt_start(); |
| 226 | |||
| 227 | printk(KERN_INFO "MTX-1 Watchdog driver\n"); | 224 | printk(KERN_INFO "MTX-1 Watchdog driver\n"); |
| 228 | |||
| 229 | return 0; | 225 | return 0; |
| 230 | } | 226 | } |
| 231 | 227 | ||
| 232 | static int mtx1_wdt_remove(struct platform_device *pdev) | 228 | static int mtx1_wdt_remove(struct platform_device *pdev) |
| 233 | { | 229 | { |
| 230 | /* FIXME: do we need to lock this test ? */ | ||
| 234 | if (mtx1_wdt_device.queue) { | 231 | if (mtx1_wdt_device.queue) { |
| 235 | mtx1_wdt_device.queue = 0; | 232 | mtx1_wdt_device.queue = 0; |
| 236 | wait_for_completion(&mtx1_wdt_device.stop); | 233 | wait_for_completion(&mtx1_wdt_device.stop); |
diff --git a/drivers/watchdog/mv64x60_wdt.c b/drivers/watchdog/mv64x60_wdt.c index b59ca3273967..acf589dc057c 100644 --- a/drivers/watchdog/mv64x60_wdt.c +++ b/drivers/watchdog/mv64x60_wdt.c | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * and services the watchdog. | 8 | * and services the watchdog. |
| 9 | * | 9 | * |
| 10 | * Derived from mpc8xx_wdt.c, with the following copyright. | 10 | * Derived from mpc8xx_wdt.c, with the following copyright. |
| 11 | * | 11 | * |
| 12 | * 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under | 12 | * 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under |
| 13 | * the terms of the GNU General Public License version 2. This program | 13 | * the terms of the GNU General Public License version 2. This program |
| 14 | * is licensed "as is" without any warranty of any kind, whether express | 14 | * is licensed "as is" without any warranty of any kind, whether express |
| @@ -22,10 +22,9 @@ | |||
| 22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
| 23 | #include <linux/watchdog.h> | 23 | #include <linux/watchdog.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | |||
| 26 | #include <linux/mv643xx.h> | 25 | #include <linux/mv643xx.h> |
| 27 | #include <asm/uaccess.h> | 26 | #include <linux/uaccess.h> |
| 28 | #include <asm/io.h> | 27 | #include <linux/io.h> |
| 29 | 28 | ||
| 30 | #define MV64x60_WDT_WDC_OFFSET 0 | 29 | #define MV64x60_WDT_WDC_OFFSET 0 |
| 31 | 30 | ||
| @@ -61,7 +60,9 @@ static DEFINE_SPINLOCK(mv64x60_wdt_spinlock); | |||
| 61 | 60 | ||
| 62 | static int nowayout = WATCHDOG_NOWAYOUT; | 61 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 63 | module_param(nowayout, int, 0); | 62 | module_param(nowayout, int, 0); |
| 64 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 63 | MODULE_PARM_DESC(nowayout, |
| 64 | "Watchdog cannot be stopped once started (default=" | ||
| 65 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 65 | 66 | ||
| 66 | static int mv64x60_wdt_toggle_wdc(int enabled_predicate, int field_shift) | 67 | static int mv64x60_wdt_toggle_wdc(int enabled_predicate, int field_shift) |
| 67 | { | 68 | { |
| @@ -150,7 +151,7 @@ static int mv64x60_wdt_release(struct inode *inode, struct file *file) | |||
| 150 | } | 151 | } |
| 151 | 152 | ||
| 152 | static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, | 153 | static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, |
| 153 | size_t len, loff_t * ppos) | 154 | size_t len, loff_t *ppos) |
| 154 | { | 155 | { |
| 155 | if (len) { | 156 | if (len) { |
| 156 | if (!nowayout) { | 157 | if (!nowayout) { |
| @@ -160,7 +161,7 @@ static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, | |||
| 160 | 161 | ||
| 161 | for (i = 0; i != len; i++) { | 162 | for (i = 0; i != len; i++) { |
| 162 | char c; | 163 | char c; |
| 163 | if(get_user(c, data + i)) | 164 | if (get_user(c, data + i)) |
| 164 | return -EFAULT; | 165 | return -EFAULT; |
| 165 | if (c == 'V') | 166 | if (c == 'V') |
| 166 | expect_close = 42; | 167 | expect_close = 42; |
| @@ -172,8 +173,8 @@ static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, | |||
| 172 | return len; | 173 | return len; |
| 173 | } | 174 | } |
| 174 | 175 | ||
| 175 | static int mv64x60_wdt_ioctl(struct inode *inode, struct file *file, | 176 | static long mv64x60_wdt_ioctl(struct file *file, |
| 176 | unsigned int cmd, unsigned long arg) | 177 | unsigned int cmd, unsigned long arg) |
| 177 | { | 178 | { |
| 178 | int timeout; | 179 | int timeout; |
| 179 | int options; | 180 | int options; |
| @@ -240,7 +241,7 @@ static const struct file_operations mv64x60_wdt_fops = { | |||
| 240 | .owner = THIS_MODULE, | 241 | .owner = THIS_MODULE, |
| 241 | .llseek = no_llseek, | 242 | .llseek = no_llseek, |
| 242 | .write = mv64x60_wdt_write, | 243 | .write = mv64x60_wdt_write, |
| 243 | .ioctl = mv64x60_wdt_ioctl, | 244 | .unlocked_ioctl = mv64x60_wdt_ioctl, |
| 244 | .open = mv64x60_wdt_open, | 245 | .open = mv64x60_wdt_open, |
| 245 | .release = mv64x60_wdt_release, | 246 | .release = mv64x60_wdt_release, |
| 246 | }; | 247 | }; |
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 74a10d50607b..3a11dadfd8e7 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c | |||
| @@ -40,11 +40,9 @@ | |||
| 40 | #include <linux/moduleparam.h> | 40 | #include <linux/moduleparam.h> |
| 41 | #include <linux/clk.h> | 41 | #include <linux/clk.h> |
| 42 | #include <linux/bitops.h> | 42 | #include <linux/bitops.h> |
| 43 | 43 | #include <linux/io.h> | |
| 44 | #include <asm/io.h> | 44 | #include <linux/uaccess.h> |
| 45 | #include <asm/uaccess.h> | ||
| 46 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
| 47 | |||
| 48 | #include <mach/prcm.h> | 46 | #include <mach/prcm.h> |
| 49 | 47 | ||
| 50 | #include "omap_wdt.h" | 48 | #include "omap_wdt.h" |
| @@ -54,11 +52,12 @@ module_param(timer_margin, uint, 0); | |||
| 54 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | 52 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); |
| 55 | 53 | ||
| 56 | static int omap_wdt_users; | 54 | static int omap_wdt_users; |
| 57 | static struct clk *armwdt_ck = NULL; | 55 | static struct clk *armwdt_ck; |
| 58 | static struct clk *mpu_wdt_ick = NULL; | 56 | static struct clk *mpu_wdt_ick; |
| 59 | static struct clk *mpu_wdt_fck = NULL; | 57 | static struct clk *mpu_wdt_fck; |
| 60 | 58 | ||
| 61 | static unsigned int wdt_trgr_pattern = 0x1234; | 59 | static unsigned int wdt_trgr_pattern = 0x1234; |
| 60 | static spinlock_t wdt_lock; | ||
| 62 | 61 | ||
| 63 | static void omap_wdt_ping(void) | 62 | static void omap_wdt_ping(void) |
| 64 | { | 63 | { |
| @@ -174,30 +173,29 @@ static int omap_wdt_release(struct inode *inode, struct file *file) | |||
| 174 | return 0; | 173 | return 0; |
| 175 | } | 174 | } |
| 176 | 175 | ||
| 177 | static ssize_t | 176 | static ssize_t omap_wdt_write(struct file *file, const char __user *data, |
| 178 | omap_wdt_write(struct file *file, const char __user *data, | ||
| 179 | size_t len, loff_t *ppos) | 177 | size_t len, loff_t *ppos) |
| 180 | { | 178 | { |
| 181 | /* Refresh LOAD_TIME. */ | 179 | /* Refresh LOAD_TIME. */ |
| 182 | if (len) | 180 | if (len) { |
| 181 | spin_lock(&wdt_lock); | ||
| 183 | omap_wdt_ping(); | 182 | omap_wdt_ping(); |
| 183 | spin_unlock(&wdt_lock); | ||
| 184 | } | ||
| 184 | return len; | 185 | return len; |
| 185 | } | 186 | } |
| 186 | 187 | ||
| 187 | static int | 188 | static long omap_wdt_ioctl(struct file *file, unsigned int cmd, |
| 188 | omap_wdt_ioctl(struct inode *inode, struct file *file, | 189 | unsigned long arg) |
| 189 | unsigned int cmd, unsigned long arg) | ||
| 190 | { | 190 | { |
| 191 | int new_margin; | 191 | int new_margin; |
| 192 | static struct watchdog_info ident = { | 192 | static const struct watchdog_info ident = { |
| 193 | .identity = "OMAP Watchdog", | 193 | .identity = "OMAP Watchdog", |
| 194 | .options = WDIOF_SETTIMEOUT, | 194 | .options = WDIOF_SETTIMEOUT, |
| 195 | .firmware_version = 0, | 195 | .firmware_version = 0, |
| 196 | }; | 196 | }; |
| 197 | 197 | ||
| 198 | switch (cmd) { | 198 | switch (cmd) { |
| 199 | default: | ||
| 200 | return -ENOTTY; | ||
| 201 | case WDIOC_GETSUPPORT: | 199 | case WDIOC_GETSUPPORT: |
| 202 | return copy_to_user((struct watchdog_info __user *)arg, &ident, | 200 | return copy_to_user((struct watchdog_info __user *)arg, &ident, |
| 203 | sizeof(ident)); | 201 | sizeof(ident)); |
| @@ -211,28 +209,34 @@ omap_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 211 | return put_user(omap_prcm_get_reset_sources(), | 209 | return put_user(omap_prcm_get_reset_sources(), |
| 212 | (int __user *)arg); | 210 | (int __user *)arg); |
| 213 | case WDIOC_KEEPALIVE: | 211 | case WDIOC_KEEPALIVE: |
| 212 | spin_lock(&wdt_lock); | ||
| 214 | omap_wdt_ping(); | 213 | omap_wdt_ping(); |
| 214 | spin_unlock(&wdt_lock); | ||
| 215 | return 0; | 215 | return 0; |
| 216 | case WDIOC_SETTIMEOUT: | 216 | case WDIOC_SETTIMEOUT: |
| 217 | if (get_user(new_margin, (int __user *)arg)) | 217 | if (get_user(new_margin, (int __user *)arg)) |
| 218 | return -EFAULT; | 218 | return -EFAULT; |
| 219 | omap_wdt_adjust_timeout(new_margin); | 219 | omap_wdt_adjust_timeout(new_margin); |
| 220 | 220 | ||
| 221 | spin_lock(&wdt_lock); | ||
| 221 | omap_wdt_disable(); | 222 | omap_wdt_disable(); |
| 222 | omap_wdt_set_timeout(); | 223 | omap_wdt_set_timeout(); |
| 223 | omap_wdt_enable(); | 224 | omap_wdt_enable(); |
| 224 | 225 | ||
| 225 | omap_wdt_ping(); | 226 | omap_wdt_ping(); |
| 227 | spin_unlock(&wdt_lock); | ||
| 226 | /* Fall */ | 228 | /* Fall */ |
| 227 | case WDIOC_GETTIMEOUT: | 229 | case WDIOC_GETTIMEOUT: |
| 228 | return put_user(timer_margin, (int __user *)arg); | 230 | return put_user(timer_margin, (int __user *)arg); |
| 231 | default: | ||
| 232 | return -ENOTTY; | ||
| 229 | } | 233 | } |
| 230 | } | 234 | } |
| 231 | 235 | ||
| 232 | static const struct file_operations omap_wdt_fops = { | 236 | static const struct file_operations omap_wdt_fops = { |
| 233 | .owner = THIS_MODULE, | 237 | .owner = THIS_MODULE, |
| 234 | .write = omap_wdt_write, | 238 | .write = omap_wdt_write, |
| 235 | .ioctl = omap_wdt_ioctl, | 239 | .unlocked_ioctl = omap_wdt_ioctl, |
| 236 | .open = omap_wdt_open, | 240 | .open = omap_wdt_open, |
| 237 | .release = omap_wdt_release, | 241 | .release = omap_wdt_release, |
| 238 | }; | 242 | }; |
| @@ -240,7 +244,7 @@ static const struct file_operations omap_wdt_fops = { | |||
| 240 | static struct miscdevice omap_wdt_miscdev = { | 244 | static struct miscdevice omap_wdt_miscdev = { |
| 241 | .minor = WATCHDOG_MINOR, | 245 | .minor = WATCHDOG_MINOR, |
| 242 | .name = "watchdog", | 246 | .name = "watchdog", |
| 243 | .fops = &omap_wdt_fops | 247 | .fops = &omap_wdt_fops, |
| 244 | }; | 248 | }; |
| 245 | 249 | ||
| 246 | static int __init omap_wdt_probe(struct platform_device *pdev) | 250 | static int __init omap_wdt_probe(struct platform_device *pdev) |
| @@ -373,6 +377,7 @@ static struct platform_driver omap_wdt_driver = { | |||
| 373 | 377 | ||
| 374 | static int __init omap_wdt_init(void) | 378 | static int __init omap_wdt_init(void) |
| 375 | { | 379 | { |
| 380 | spin_lock_init(&wdt_lock); | ||
| 376 | return platform_driver_register(&omap_wdt_driver); | 381 | return platform_driver_register(&omap_wdt_driver); |
| 377 | } | 382 | } |
| 378 | 383 | ||
diff --git a/drivers/watchdog/pc87413_wdt.c b/drivers/watchdog/pc87413_wdt.c index 15e4f8887a9e..e91ada72da1d 100644 --- a/drivers/watchdog/pc87413_wdt.c +++ b/drivers/watchdog/pc87413_wdt.c | |||
| @@ -31,14 +31,14 @@ | |||
| 31 | #include <linux/spinlock.h> | 31 | #include <linux/spinlock.h> |
| 32 | #include <linux/moduleparam.h> | 32 | #include <linux/moduleparam.h> |
| 33 | #include <linux/version.h> | 33 | #include <linux/version.h> |
| 34 | #include <linux/io.h> | ||
| 35 | #include <linux/uaccess.h> | ||
| 34 | 36 | ||
| 35 | #include <asm/io.h> | ||
| 36 | #include <asm/uaccess.h> | ||
| 37 | #include <asm/system.h> | 37 | #include <asm/system.h> |
| 38 | 38 | ||
| 39 | /* #define DEBUG 1 */ | 39 | /* #define DEBUG 1 */ |
| 40 | 40 | ||
| 41 | #define DEFAULT_TIMEOUT 1 /* 1 minute */ | 41 | #define DEFAULT_TIMEOUT 1 /* 1 minute */ |
| 42 | #define MAX_TIMEOUT 255 | 42 | #define MAX_TIMEOUT 255 |
| 43 | 43 | ||
| 44 | #define VERSION "1.1" | 44 | #define VERSION "1.1" |
| @@ -46,22 +46,22 @@ | |||
| 46 | #define PFX MODNAME ": " | 46 | #define PFX MODNAME ": " |
| 47 | #define DPFX MODNAME " - DEBUG: " | 47 | #define DPFX MODNAME " - DEBUG: " |
| 48 | 48 | ||
| 49 | #define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */ | 49 | #define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */ |
| 50 | #define WDT_DATA_IO_PORT (WDT_INDEX_IO_PORT+1) | 50 | #define WDT_DATA_IO_PORT (WDT_INDEX_IO_PORT+1) |
| 51 | #define SWC_LDN 0x04 | 51 | #define SWC_LDN 0x04 |
| 52 | #define SIOCFG2 0x22 /* Serial IO register */ | 52 | #define SIOCFG2 0x22 /* Serial IO register */ |
| 53 | #define WDCTL 0x10 /* Watchdog-Timer-Controll-Register */ | 53 | #define WDCTL 0x10 /* Watchdog-Timer-Controll-Register */ |
| 54 | #define WDTO 0x11 /* Watchdog timeout register */ | 54 | #define WDTO 0x11 /* Watchdog timeout register */ |
| 55 | #define WDCFG 0x12 /* Watchdog config register */ | 55 | #define WDCFG 0x12 /* Watchdog config register */ |
| 56 | 56 | ||
| 57 | static int io = 0x2E; /* Address used on Portwell Boards */ | 57 | static int io = 0x2E; /* Address used on Portwell Boards */ |
| 58 | 58 | ||
| 59 | static int timeout = DEFAULT_TIMEOUT; /* timeout value */ | 59 | static int timeout = DEFAULT_TIMEOUT; /* timeout value */ |
| 60 | static unsigned long timer_enabled = 0; /* is the timer enabled? */ | 60 | static unsigned long timer_enabled; /* is the timer enabled? */ |
| 61 | 61 | ||
| 62 | static char expect_close; /* is the close expected? */ | 62 | static char expect_close; /* is the close expected? */ |
| 63 | 63 | ||
| 64 | static DEFINE_SPINLOCK(io_lock);/* to guard the watchdog from io races */ | 64 | static DEFINE_SPINLOCK(io_lock); /* to guard us from io races */ |
| 65 | 65 | ||
| 66 | static int nowayout = WATCHDOG_NOWAYOUT; | 66 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 67 | 67 | ||
| @@ -69,7 +69,7 @@ static int nowayout = WATCHDOG_NOWAYOUT; | |||
| 69 | 69 | ||
| 70 | /* Select pins for Watchdog output */ | 70 | /* Select pins for Watchdog output */ |
| 71 | 71 | ||
| 72 | static inline void pc87413_select_wdt_out (void) | 72 | static inline void pc87413_select_wdt_out(void) |
| 73 | { | 73 | { |
| 74 | unsigned int cr_data = 0; | 74 | unsigned int cr_data = 0; |
| 75 | 75 | ||
| @@ -77,7 +77,7 @@ static inline void pc87413_select_wdt_out (void) | |||
| 77 | 77 | ||
| 78 | outb_p(SIOCFG2, WDT_INDEX_IO_PORT); | 78 | outb_p(SIOCFG2, WDT_INDEX_IO_PORT); |
| 79 | 79 | ||
| 80 | cr_data = inb (WDT_DATA_IO_PORT); | 80 | cr_data = inb(WDT_DATA_IO_PORT); |
| 81 | 81 | ||
| 82 | cr_data |= 0x80; /* Set Bit7 to 1*/ | 82 | cr_data |= 0x80; /* Set Bit7 to 1*/ |
| 83 | outb_p(SIOCFG2, WDT_INDEX_IO_PORT); | 83 | outb_p(SIOCFG2, WDT_INDEX_IO_PORT); |
| @@ -85,8 +85,9 @@ static inline void pc87413_select_wdt_out (void) | |||
| 85 | outb_p(cr_data, WDT_DATA_IO_PORT); | 85 | outb_p(cr_data, WDT_DATA_IO_PORT); |
| 86 | 86 | ||
| 87 | #ifdef DEBUG | 87 | #ifdef DEBUG |
| 88 | printk(KERN_INFO DPFX "Select multiple pin,pin55,as WDT output:" | 88 | printk(KERN_INFO DPFX |
| 89 | " Bit7 to 1: %d\n", cr_data); | 89 | "Select multiple pin,pin55,as WDT output: Bit7 to 1: %d\n", |
| 90 | cr_data); | ||
| 90 | #endif | 91 | #endif |
| 91 | } | 92 | } |
| 92 | 93 | ||
| @@ -94,18 +95,18 @@ static inline void pc87413_select_wdt_out (void) | |||
| 94 | 95 | ||
| 95 | static inline void pc87413_enable_swc(void) | 96 | static inline void pc87413_enable_swc(void) |
| 96 | { | 97 | { |
| 97 | unsigned int cr_data=0; | 98 | unsigned int cr_data = 0; |
| 98 | 99 | ||
| 99 | /* Step 2: Enable SWC functions */ | 100 | /* Step 2: Enable SWC functions */ |
| 100 | 101 | ||
| 101 | outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */ | 102 | outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */ |
| 102 | outb_p(SWC_LDN, WDT_DATA_IO_PORT); | 103 | outb_p(SWC_LDN, WDT_DATA_IO_PORT); |
| 103 | 104 | ||
| 104 | outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */ | 105 | outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */ |
| 105 | cr_data = inb(WDT_DATA_IO_PORT); | 106 | cr_data = inb(WDT_DATA_IO_PORT); |
| 106 | cr_data |= 0x01; /* Set Bit0 to 1 */ | 107 | cr_data |= 0x01; /* Set Bit0 to 1 */ |
| 107 | outb_p(0x30, WDT_INDEX_IO_PORT); | 108 | outb_p(0x30, WDT_INDEX_IO_PORT); |
| 108 | outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */ | 109 | outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */ |
| 109 | 110 | ||
| 110 | #ifdef DEBUG | 111 | #ifdef DEBUG |
| 111 | printk(KERN_INFO DPFX "pc87413 - Enable SWC functions\n"); | 112 | printk(KERN_INFO DPFX "pc87413 - Enable SWC functions\n"); |
| @@ -121,20 +122,19 @@ static inline unsigned int pc87413_get_swc_base(void) | |||
| 121 | 122 | ||
| 122 | /* Step 3: Read SWC I/O Base Address */ | 123 | /* Step 3: Read SWC I/O Base Address */ |
| 123 | 124 | ||
| 124 | outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */ | 125 | outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */ |
| 125 | addr_h = inb(WDT_DATA_IO_PORT); | 126 | addr_h = inb(WDT_DATA_IO_PORT); |
| 126 | 127 | ||
| 127 | outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */ | 128 | outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */ |
| 128 | 129 | ||
| 129 | addr_l = inb(WDT_DATA_IO_PORT); | 130 | addr_l = inb(WDT_DATA_IO_PORT); |
| 130 | 131 | ||
| 131 | swc_base_addr = (addr_h << 8) + addr_l; | 132 | swc_base_addr = (addr_h << 8) + addr_l; |
| 132 | |||
| 133 | #ifdef DEBUG | 133 | #ifdef DEBUG |
| 134 | printk(KERN_INFO DPFX "Read SWC I/O Base Address: low %d, high %d," | 134 | printk(KERN_INFO DPFX |
| 135 | " res %d\n", addr_l, addr_h, swc_base_addr); | 135 | "Read SWC I/O Base Address: low %d, high %d, res %d\n", |
| 136 | addr_l, addr_h, swc_base_addr); | ||
| 136 | #endif | 137 | #endif |
| 137 | |||
| 138 | return swc_base_addr; | 138 | return swc_base_addr; |
| 139 | } | 139 | } |
| 140 | 140 | ||
| @@ -143,9 +143,7 @@ static inline unsigned int pc87413_get_swc_base(void) | |||
| 143 | static inline void pc87413_swc_bank3(unsigned int swc_base_addr) | 143 | static inline void pc87413_swc_bank3(unsigned int swc_base_addr) |
| 144 | { | 144 | { |
| 145 | /* Step 4: Select Bank3 of SWC */ | 145 | /* Step 4: Select Bank3 of SWC */ |
| 146 | |||
| 147 | outb_p(inb(swc_base_addr + 0x0f) | 0x03, swc_base_addr + 0x0f); | 146 | outb_p(inb(swc_base_addr + 0x0f) | 0x03, swc_base_addr + 0x0f); |
| 148 | |||
| 149 | #ifdef DEBUG | 147 | #ifdef DEBUG |
| 150 | printk(KERN_INFO DPFX "Select Bank3 of SWC\n"); | 148 | printk(KERN_INFO DPFX "Select Bank3 of SWC\n"); |
| 151 | #endif | 149 | #endif |
| @@ -157,9 +155,7 @@ static inline void pc87413_programm_wdto(unsigned int swc_base_addr, | |||
| 157 | char pc87413_time) | 155 | char pc87413_time) |
| 158 | { | 156 | { |
| 159 | /* Step 5: Programm WDTO, Twd. */ | 157 | /* Step 5: Programm WDTO, Twd. */ |
| 160 | |||
| 161 | outb_p(pc87413_time, swc_base_addr + WDTO); | 158 | outb_p(pc87413_time, swc_base_addr + WDTO); |
| 162 | |||
| 163 | #ifdef DEBUG | 159 | #ifdef DEBUG |
| 164 | printk(KERN_INFO DPFX "Set WDTO to %d minutes\n", pc87413_time); | 160 | printk(KERN_INFO DPFX "Set WDTO to %d minutes\n", pc87413_time); |
| 165 | #endif | 161 | #endif |
| @@ -170,9 +166,7 @@ static inline void pc87413_programm_wdto(unsigned int swc_base_addr, | |||
| 170 | static inline void pc87413_enable_wden(unsigned int swc_base_addr) | 166 | static inline void pc87413_enable_wden(unsigned int swc_base_addr) |
| 171 | { | 167 | { |
| 172 | /* Step 6: Enable WDEN */ | 168 | /* Step 6: Enable WDEN */ |
| 173 | 169 | outb_p(inb(swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL); | |
| 174 | outb_p(inb (swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL); | ||
| 175 | |||
| 176 | #ifdef DEBUG | 170 | #ifdef DEBUG |
| 177 | printk(KERN_INFO DPFX "Enable WDEN\n"); | 171 | printk(KERN_INFO DPFX "Enable WDEN\n"); |
| 178 | #endif | 172 | #endif |
| @@ -182,9 +176,7 @@ static inline void pc87413_enable_wden(unsigned int swc_base_addr) | |||
| 182 | static inline void pc87413_enable_sw_wd_tren(unsigned int swc_base_addr) | 176 | static inline void pc87413_enable_sw_wd_tren(unsigned int swc_base_addr) |
| 183 | { | 177 | { |
| 184 | /* Enable SW_WD_TREN */ | 178 | /* Enable SW_WD_TREN */ |
| 185 | 179 | outb_p(inb(swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG); | |
| 186 | outb_p(inb (swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG); | ||
| 187 | |||
| 188 | #ifdef DEBUG | 180 | #ifdef DEBUG |
| 189 | printk(KERN_INFO DPFX "Enable SW_WD_TREN\n"); | 181 | printk(KERN_INFO DPFX "Enable SW_WD_TREN\n"); |
| 190 | #endif | 182 | #endif |
| @@ -195,9 +187,7 @@ static inline void pc87413_enable_sw_wd_tren(unsigned int swc_base_addr) | |||
| 195 | static inline void pc87413_disable_sw_wd_tren(unsigned int swc_base_addr) | 187 | static inline void pc87413_disable_sw_wd_tren(unsigned int swc_base_addr) |
| 196 | { | 188 | { |
| 197 | /* Disable SW_WD_TREN */ | 189 | /* Disable SW_WD_TREN */ |
| 198 | 190 | outb_p(inb(swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG); | |
| 199 | outb_p(inb (swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG); | ||
| 200 | |||
| 201 | #ifdef DEBUG | 191 | #ifdef DEBUG |
| 202 | printk(KERN_INFO DPFX "pc87413 - Disable SW_WD_TREN\n"); | 192 | printk(KERN_INFO DPFX "pc87413 - Disable SW_WD_TREN\n"); |
| 203 | #endif | 193 | #endif |
| @@ -208,9 +198,7 @@ static inline void pc87413_disable_sw_wd_tren(unsigned int swc_base_addr) | |||
| 208 | static inline void pc87413_enable_sw_wd_trg(unsigned int swc_base_addr) | 198 | static inline void pc87413_enable_sw_wd_trg(unsigned int swc_base_addr) |
| 209 | { | 199 | { |
| 210 | /* Enable SW_WD_TRG */ | 200 | /* Enable SW_WD_TRG */ |
| 211 | 201 | outb_p(inb(swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL); | |
| 212 | outb_p(inb (swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL); | ||
| 213 | |||
| 214 | #ifdef DEBUG | 202 | #ifdef DEBUG |
| 215 | printk(KERN_INFO DPFX "pc87413 - Enable SW_WD_TRG\n"); | 203 | printk(KERN_INFO DPFX "pc87413 - Enable SW_WD_TRG\n"); |
| 216 | #endif | 204 | #endif |
| @@ -221,9 +209,7 @@ static inline void pc87413_enable_sw_wd_trg(unsigned int swc_base_addr) | |||
| 221 | static inline void pc87413_disable_sw_wd_trg(unsigned int swc_base_addr) | 209 | static inline void pc87413_disable_sw_wd_trg(unsigned int swc_base_addr) |
| 222 | { | 210 | { |
| 223 | /* Disable SW_WD_TRG */ | 211 | /* Disable SW_WD_TRG */ |
| 224 | 212 | outb_p(inb(swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL); | |
| 225 | outb_p(inb (swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL); | ||
| 226 | |||
| 227 | #ifdef DEBUG | 213 | #ifdef DEBUG |
| 228 | printk(KERN_INFO DPFX "Disable SW_WD_TRG\n"); | 214 | printk(KERN_INFO DPFX "Disable SW_WD_TRG\n"); |
| 229 | #endif | 215 | #endif |
| @@ -314,8 +300,8 @@ static int pc87413_open(struct inode *inode, struct file *file) | |||
| 314 | /* Reload and activate timer */ | 300 | /* Reload and activate timer */ |
| 315 | pc87413_refresh(); | 301 | pc87413_refresh(); |
| 316 | 302 | ||
| 317 | printk(KERN_INFO MODNAME "Watchdog enabled. Timeout set to" | 303 | printk(KERN_INFO MODNAME |
| 318 | " %d minute(s).\n", timeout); | 304 | "Watchdog enabled. Timeout set to %d minute(s).\n", timeout); |
| 319 | 305 | ||
| 320 | return nonseekable_open(inode, file); | 306 | return nonseekable_open(inode, file); |
| 321 | } | 307 | } |
| @@ -338,17 +324,15 @@ static int pc87413_release(struct inode *inode, struct file *file) | |||
| 338 | 324 | ||
| 339 | if (expect_close == 42) { | 325 | if (expect_close == 42) { |
| 340 | pc87413_disable(); | 326 | pc87413_disable(); |
| 341 | printk(KERN_INFO MODNAME "Watchdog disabled," | 327 | printk(KERN_INFO MODNAME |
| 342 | " sleeping again...\n"); | 328 | "Watchdog disabled, sleeping again...\n"); |
| 343 | } else { | 329 | } else { |
| 344 | printk(KERN_CRIT MODNAME "Unexpected close, not stopping" | 330 | printk(KERN_CRIT MODNAME |
| 345 | " watchdog!\n"); | 331 | "Unexpected close, not stopping watchdog!\n"); |
| 346 | pc87413_refresh(); | 332 | pc87413_refresh(); |
| 347 | } | 333 | } |
| 348 | |||
| 349 | clear_bit(0, &timer_enabled); | 334 | clear_bit(0, &timer_enabled); |
| 350 | expect_close = 0; | 335 | expect_close = 0; |
| 351 | |||
| 352 | return 0; | 336 | return 0; |
| 353 | } | 337 | } |
| 354 | 338 | ||
| @@ -386,10 +370,11 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, | |||
| 386 | /* reset expect flag */ | 370 | /* reset expect flag */ |
| 387 | expect_close = 0; | 371 | expect_close = 0; |
| 388 | 372 | ||
| 389 | /* scan to see whether or not we got the magic character */ | 373 | /* scan to see whether or not we got the |
| 374 | magic character */ | ||
| 390 | for (i = 0; i != len; i++) { | 375 | for (i = 0; i != len; i++) { |
| 391 | char c; | 376 | char c; |
| 392 | if (get_user(c, data+i)) | 377 | if (get_user(c, data + i)) |
| 393 | return -EFAULT; | 378 | return -EFAULT; |
| 394 | if (c == 'V') | 379 | if (c == 'V') |
| 395 | expect_close = 42; | 380 | expect_close = 42; |
| @@ -404,7 +389,6 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, | |||
| 404 | 389 | ||
| 405 | /** | 390 | /** |
| 406 | * pc87413_ioctl: | 391 | * pc87413_ioctl: |
| 407 | * @inode: inode of the device | ||
| 408 | * @file: file handle to the device | 392 | * @file: file handle to the device |
| 409 | * @cmd: watchdog command | 393 | * @cmd: watchdog command |
| 410 | * @arg: argument pointer | 394 | * @arg: argument pointer |
| @@ -414,8 +398,8 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, | |||
| 414 | * querying capabilities and current status. | 398 | * querying capabilities and current status. |
| 415 | */ | 399 | */ |
| 416 | 400 | ||
| 417 | static int pc87413_ioctl(struct inode *inode, struct file *file, | 401 | static long pc87413_ioctl(struct file *file, unsigned int cmd, |
| 418 | unsigned int cmd, unsigned long arg) | 402 | unsigned long arg) |
| 419 | { | 403 | { |
| 420 | int new_timeout; | 404 | int new_timeout; |
| 421 | 405 | ||
| @@ -426,75 +410,58 @@ static int pc87413_ioctl(struct inode *inode, struct file *file, | |||
| 426 | 410 | ||
| 427 | static struct watchdog_info ident = { | 411 | static struct watchdog_info ident = { |
| 428 | .options = WDIOF_KEEPALIVEPING | | 412 | .options = WDIOF_KEEPALIVEPING | |
| 429 | WDIOF_SETTIMEOUT | | 413 | WDIOF_SETTIMEOUT | |
| 430 | WDIOF_MAGICCLOSE, | 414 | WDIOF_MAGICCLOSE, |
| 431 | .firmware_version = 1, | 415 | .firmware_version = 1, |
| 432 | .identity = "PC87413(HF/F) watchdog" | 416 | .identity = "PC87413(HF/F) watchdog", |
| 433 | }; | 417 | }; |
| 434 | 418 | ||
| 435 | uarg.i = (int __user *)arg; | 419 | uarg.i = (int __user *)arg; |
| 436 | 420 | ||
| 437 | switch(cmd) { | 421 | switch (cmd) { |
| 438 | default: | 422 | case WDIOC_GETSUPPORT: |
| 439 | return -ENOTTY; | 423 | return copy_to_user(uarg.ident, &ident, |
| 440 | 424 | sizeof(ident)) ? -EFAULT : 0; | |
| 441 | case WDIOC_GETSUPPORT: | 425 | case WDIOC_GETSTATUS: |
| 442 | return copy_to_user(uarg.ident, &ident, | 426 | return put_user(pc87413_status(), uarg.i); |
| 443 | sizeof(ident)) ? -EFAULT : 0; | 427 | case WDIOC_GETBOOTSTATUS: |
| 444 | 428 | return put_user(0, uarg.i); | |
| 445 | case WDIOC_GETSTATUS: | 429 | case WDIOC_SETOPTIONS: |
| 446 | return put_user(pc87413_status(), uarg.i); | 430 | { |
| 447 | 431 | int options, retval = -EINVAL; | |
| 448 | case WDIOC_GETBOOTSTATUS: | 432 | if (get_user(options, uarg.i)) |
| 449 | return put_user(0, uarg.i); | 433 | return -EFAULT; |
| 450 | 434 | if (options & WDIOS_DISABLECARD) { | |
| 451 | case WDIOC_KEEPALIVE: | 435 | pc87413_disable(); |
| 452 | pc87413_refresh(); | 436 | retval = 0; |
| 437 | } | ||
| 438 | if (options & WDIOS_ENABLECARD) { | ||
| 439 | pc87413_enable(); | ||
| 440 | retval = 0; | ||
| 441 | } | ||
| 442 | return retval; | ||
| 443 | } | ||
| 444 | case WDIOC_KEEPALIVE: | ||
| 445 | pc87413_refresh(); | ||
| 453 | #ifdef DEBUG | 446 | #ifdef DEBUG |
| 454 | printk(KERN_INFO DPFX "keepalive\n"); | 447 | printk(KERN_INFO DPFX "keepalive\n"); |
| 455 | #endif | 448 | #endif |
| 456 | return 0; | 449 | return 0; |
| 457 | 450 | case WDIOC_SETTIMEOUT: | |
| 458 | case WDIOC_SETTIMEOUT: | 451 | if (get_user(new_timeout, uarg.i)) |
| 459 | if (get_user(new_timeout, uarg.i)) | 452 | return -EFAULT; |
| 460 | return -EFAULT; | 453 | /* the API states this is given in secs */ |
| 461 | 454 | new_timeout /= 60; | |
| 462 | // the API states this is given in secs | 455 | if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) |
| 463 | new_timeout /= 60; | 456 | return -EINVAL; |
| 464 | 457 | timeout = new_timeout; | |
| 465 | if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) | 458 | pc87413_refresh(); |
| 466 | return -EINVAL; | 459 | /* fall through and return the new timeout... */ |
| 467 | 460 | case WDIOC_GETTIMEOUT: | |
| 468 | timeout = new_timeout; | 461 | new_timeout = timeout * 60; |
| 469 | pc87413_refresh(); | 462 | return put_user(new_timeout, uarg.i); |
| 470 | 463 | default: | |
| 471 | // fall through and return the new timeout... | 464 | return -ENOTTY; |
| 472 | |||
| 473 | case WDIOC_GETTIMEOUT: | ||
| 474 | |||
| 475 | new_timeout = timeout * 60; | ||
| 476 | |||
| 477 | return put_user(new_timeout, uarg.i); | ||
| 478 | |||
| 479 | case WDIOC_SETOPTIONS: | ||
| 480 | { | ||
| 481 | int options, retval = -EINVAL; | ||
| 482 | |||
| 483 | if (get_user(options, uarg.i)) | ||
| 484 | return -EFAULT; | ||
| 485 | |||
| 486 | if (options & WDIOS_DISABLECARD) { | ||
| 487 | pc87413_disable(); | ||
| 488 | retval = 0; | ||
| 489 | } | ||
| 490 | |||
| 491 | if (options & WDIOS_ENABLECARD) { | ||
| 492 | pc87413_enable(); | ||
| 493 | retval = 0; | ||
| 494 | } | ||
| 495 | |||
| 496 | return retval; | ||
| 497 | } | ||
| 498 | } | 465 | } |
| 499 | } | 466 | } |
| 500 | 467 | ||
| @@ -517,10 +484,8 @@ static int pc87413_notify_sys(struct notifier_block *this, | |||
| 517 | void *unused) | 484 | void *unused) |
| 518 | { | 485 | { |
| 519 | if (code == SYS_DOWN || code == SYS_HALT) | 486 | if (code == SYS_DOWN || code == SYS_HALT) |
| 520 | { | ||
| 521 | /* Turn the card off */ | 487 | /* Turn the card off */ |
| 522 | pc87413_disable(); | 488 | pc87413_disable(); |
| 523 | } | ||
| 524 | return NOTIFY_DONE; | 489 | return NOTIFY_DONE; |
| 525 | } | 490 | } |
| 526 | 491 | ||
| @@ -530,21 +495,19 @@ static const struct file_operations pc87413_fops = { | |||
| 530 | .owner = THIS_MODULE, | 495 | .owner = THIS_MODULE, |
| 531 | .llseek = no_llseek, | 496 | .llseek = no_llseek, |
| 532 | .write = pc87413_write, | 497 | .write = pc87413_write, |
| 533 | .ioctl = pc87413_ioctl, | 498 | .unlocked_ioctl = pc87413_ioctl, |
| 534 | .open = pc87413_open, | 499 | .open = pc87413_open, |
| 535 | .release = pc87413_release, | 500 | .release = pc87413_release, |
| 536 | }; | 501 | }; |
| 537 | 502 | ||
| 538 | static struct notifier_block pc87413_notifier = | 503 | static struct notifier_block pc87413_notifier = { |
| 539 | { | ||
| 540 | .notifier_call = pc87413_notify_sys, | 504 | .notifier_call = pc87413_notify_sys, |
| 541 | }; | 505 | }; |
| 542 | 506 | ||
| 543 | static struct miscdevice pc87413_miscdev= | 507 | static struct miscdevice pc87413_miscdev = { |
| 544 | { | ||
| 545 | .minor = WATCHDOG_MINOR, | 508 | .minor = WATCHDOG_MINOR, |
| 546 | .name = "watchdog", | 509 | .name = "watchdog", |
| 547 | .fops = &pc87413_fops | 510 | .fops = &pc87413_fops, |
| 548 | }; | 511 | }; |
| 549 | 512 | ||
| 550 | /* -- Module init functions -------------------------------------*/ | 513 | /* -- Module init functions -------------------------------------*/ |
| @@ -561,29 +524,26 @@ static int __init pc87413_init(void) | |||
| 561 | { | 524 | { |
| 562 | int ret; | 525 | int ret; |
| 563 | 526 | ||
| 564 | printk(KERN_INFO PFX "Version " VERSION " at io 0x%X\n", WDT_INDEX_IO_PORT); | 527 | printk(KERN_INFO PFX "Version " VERSION " at io 0x%X\n", |
| 528 | WDT_INDEX_IO_PORT); | ||
| 565 | 529 | ||
| 566 | /* request_region(io, 2, "pc87413"); */ | 530 | /* request_region(io, 2, "pc87413"); */ |
| 567 | 531 | ||
| 568 | ret = register_reboot_notifier(&pc87413_notifier); | 532 | ret = register_reboot_notifier(&pc87413_notifier); |
| 569 | if (ret != 0) { | 533 | if (ret != 0) { |
| 570 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 534 | printk(KERN_ERR PFX |
| 571 | ret); | 535 | "cannot register reboot notifier (err=%d)\n", ret); |
| 572 | } | 536 | } |
| 573 | 537 | ||
| 574 | ret = misc_register(&pc87413_miscdev); | 538 | ret = misc_register(&pc87413_miscdev); |
| 575 | |||
| 576 | if (ret != 0) { | 539 | if (ret != 0) { |
| 577 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 540 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", |
| 578 | WATCHDOG_MINOR, ret); | 541 | WATCHDOG_MINOR, ret); |
| 579 | unregister_reboot_notifier(&pc87413_notifier); | 542 | unregister_reboot_notifier(&pc87413_notifier); |
| 580 | return ret; | 543 | return ret; |
| 581 | } | 544 | } |
| 582 | |||
| 583 | printk(KERN_INFO PFX "initialized. timeout=%d min \n", timeout); | 545 | printk(KERN_INFO PFX "initialized. timeout=%d min \n", timeout); |
| 584 | |||
| 585 | pc87413_enable(); | 546 | pc87413_enable(); |
| 586 | |||
| 587 | return 0; | 547 | return 0; |
| 588 | } | 548 | } |
| 589 | 549 | ||
| @@ -600,17 +560,16 @@ static int __init pc87413_init(void) | |||
| 600 | static void __exit pc87413_exit(void) | 560 | static void __exit pc87413_exit(void) |
| 601 | { | 561 | { |
| 602 | /* Stop the timer before we leave */ | 562 | /* Stop the timer before we leave */ |
| 603 | if (!nowayout) | 563 | if (!nowayout) { |
| 604 | { | ||
| 605 | pc87413_disable(); | 564 | pc87413_disable(); |
| 606 | printk(KERN_INFO MODNAME "Watchdog disabled.\n"); | 565 | printk(KERN_INFO MODNAME "Watchdog disabled.\n"); |
| 607 | } | 566 | } |
| 608 | 567 | ||
| 609 | misc_deregister(&pc87413_miscdev); | 568 | misc_deregister(&pc87413_miscdev); |
| 610 | unregister_reboot_notifier(&pc87413_notifier); | 569 | unregister_reboot_notifier(&pc87413_notifier); |
| 611 | /* release_region(io,2); */ | 570 | /* release_region(io, 2); */ |
| 612 | 571 | ||
| 613 | printk(MODNAME " watchdog component driver removed.\n"); | 572 | printk(KERN_INFO MODNAME " watchdog component driver removed.\n"); |
| 614 | } | 573 | } |
| 615 | 574 | ||
| 616 | module_init(pc87413_init); | 575 | module_init(pc87413_init); |
| @@ -626,8 +585,12 @@ module_param(io, int, 0); | |||
| 626 | MODULE_PARM_DESC(io, MODNAME " I/O port (default: " __MODULE_STRING(io) ")."); | 585 | MODULE_PARM_DESC(io, MODNAME " I/O port (default: " __MODULE_STRING(io) ")."); |
| 627 | 586 | ||
| 628 | module_param(timeout, int, 0); | 587 | module_param(timeout, int, 0); |
| 629 | MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes (default=" __MODULE_STRING(timeout) ")."); | 588 | MODULE_PARM_DESC(timeout, |
| 589 | "Watchdog timeout in minutes (default=" | ||
| 590 | __MODULE_STRING(timeout) ")."); | ||
| 630 | 591 | ||
| 631 | module_param(nowayout, int, 0); | 592 | module_param(nowayout, int, 0); |
| 632 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 593 | MODULE_PARM_DESC(nowayout, |
| 594 | "Watchdog cannot be stopped once started (default=" | ||
| 595 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 633 | 596 | ||
diff --git a/drivers/watchdog/pcwd.c b/drivers/watchdog/pcwd.c index 7b41434fac8c..3b0ddc7fcf3f 100644 --- a/drivers/watchdog/pcwd.c +++ b/drivers/watchdog/pcwd.c | |||
| @@ -40,13 +40,15 @@ | |||
| 40 | * fairly useless proc entry. | 40 | * fairly useless proc entry. |
| 41 | * 990610 removed said useless proc code for the merge <alan> | 41 | * 990610 removed said useless proc code for the merge <alan> |
| 42 | * 000403 Removed last traces of proc code. <davej> | 42 | * 000403 Removed last traces of proc code. <davej> |
| 43 | * 011214 Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT <Matt_Domsch@dell.com> | 43 | * 011214 Added nowayout module option to override |
| 44 | * CONFIG_WATCHDOG_NOWAYOUT <Matt_Domsch@dell.com> | ||
| 44 | * Added timeout module option to override default | 45 | * Added timeout module option to override default |
| 45 | */ | 46 | */ |
| 46 | 47 | ||
| 47 | /* | 48 | /* |
| 48 | * A bells and whistles driver is available from http://www.pcwd.de/ | 49 | * A bells and whistles driver is available from http://www.pcwd.de/ |
| 49 | * More info available at http://www.berkprod.com/ or http://www.pcwatchdog.com/ | 50 | * More info available at http://www.berkprod.com/ or |
| 51 | * http://www.pcwatchdog.com/ | ||
| 50 | */ | 52 | */ |
| 51 | 53 | ||
| 52 | #include <linux/module.h> /* For module specific items */ | 54 | #include <linux/module.h> /* For module specific items */ |
| @@ -65,9 +67,8 @@ | |||
| 65 | #include <linux/isa.h> /* For isa devices */ | 67 | #include <linux/isa.h> /* For isa devices */ |
| 66 | #include <linux/ioport.h> /* For io-port access */ | 68 | #include <linux/ioport.h> /* For io-port access */ |
| 67 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | 69 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ |
| 68 | 70 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ | |
| 69 | #include <asm/uaccess.h> /* For copy_to_user/put_user/... */ | 71 | #include <linux/io.h> /* For inb/outb/... */ |
| 70 | #include <asm/io.h> /* For inb/outb/... */ | ||
| 71 | 72 | ||
| 72 | /* Module and version information */ | 73 | /* Module and version information */ |
| 73 | #define WATCHDOG_VERSION "1.20" | 74 | #define WATCHDOG_VERSION "1.20" |
| @@ -111,14 +112,16 @@ static int pcwd_ioports[] = { 0x270, 0x350, 0x370, 0x000 }; | |||
| 111 | #define WD_REVC_WTRP 0x01 /* Watchdog Trip status */ | 112 | #define WD_REVC_WTRP 0x01 /* Watchdog Trip status */ |
| 112 | #define WD_REVC_HRBT 0x02 /* Watchdog Heartbeat */ | 113 | #define WD_REVC_HRBT 0x02 /* Watchdog Heartbeat */ |
| 113 | #define WD_REVC_TTRP 0x04 /* Temperature Trip status */ | 114 | #define WD_REVC_TTRP 0x04 /* Temperature Trip status */ |
| 114 | #define WD_REVC_RL2A 0x08 /* Relay 2 activated by on-board processor */ | 115 | #define WD_REVC_RL2A 0x08 /* Relay 2 activated by |
| 116 | on-board processor */ | ||
| 115 | #define WD_REVC_RL1A 0x10 /* Relay 1 active */ | 117 | #define WD_REVC_RL1A 0x10 /* Relay 1 active */ |
| 116 | #define WD_REVC_R2DS 0x40 /* Relay 2 disable */ | 118 | #define WD_REVC_R2DS 0x40 /* Relay 2 disable */ |
| 117 | #define WD_REVC_RLY2 0x80 /* Relay 2 activated? */ | 119 | #define WD_REVC_RLY2 0x80 /* Relay 2 activated? */ |
| 118 | /* Port 2 : Control Status #2 */ | 120 | /* Port 2 : Control Status #2 */ |
| 119 | #define WD_WDIS 0x10 /* Watchdog Disabled */ | 121 | #define WD_WDIS 0x10 /* Watchdog Disabled */ |
| 120 | #define WD_ENTP 0x20 /* Watchdog Enable Temperature Trip */ | 122 | #define WD_ENTP 0x20 /* Watchdog Enable Temperature Trip */ |
| 121 | #define WD_SSEL 0x40 /* Watchdog Switch Select (1:SW1 <-> 0:SW2) */ | 123 | #define WD_SSEL 0x40 /* Watchdog Switch Select |
| 124 | (1:SW1 <-> 0:SW2) */ | ||
| 122 | #define WD_WCMD 0x80 /* Watchdog Command Mode */ | 125 | #define WD_WCMD 0x80 /* Watchdog Command Mode */ |
| 123 | 126 | ||
| 124 | /* max. time we give an ISA watchdog card to process a command */ | 127 | /* max. time we give an ISA watchdog card to process a command */ |
| @@ -142,7 +145,7 @@ static int pcwd_ioports[] = { 0x270, 0x350, 0x370, 0x000 }; | |||
| 142 | #define CMD_ISA_RESET_RELAYS 0x0D | 145 | #define CMD_ISA_RESET_RELAYS 0x0D |
| 143 | 146 | ||
| 144 | /* Watchdog's Dip Switch heartbeat values */ | 147 | /* Watchdog's Dip Switch heartbeat values */ |
| 145 | static const int heartbeat_tbl [] = { | 148 | static const int heartbeat_tbl[] = { |
| 146 | 20, /* OFF-OFF-OFF = 20 Sec */ | 149 | 20, /* OFF-OFF-OFF = 20 Sec */ |
| 147 | 40, /* OFF-OFF-ON = 40 Sec */ | 150 | 40, /* OFF-OFF-ON = 40 Sec */ |
| 148 | 60, /* OFF-ON-OFF = 1 Min */ | 151 | 60, /* OFF-ON-OFF = 1 Min */ |
| @@ -168,11 +171,15 @@ static int cards_found; | |||
| 168 | static atomic_t open_allowed = ATOMIC_INIT(1); | 171 | static atomic_t open_allowed = ATOMIC_INIT(1); |
| 169 | static char expect_close; | 172 | static char expect_close; |
| 170 | static int temp_panic; | 173 | static int temp_panic; |
| 171 | static struct { /* this is private data for each ISA-PC watchdog card */ | 174 | |
| 175 | /* this is private data for each ISA-PC watchdog card */ | ||
| 176 | static struct { | ||
| 172 | char fw_ver_str[6]; /* The cards firmware version */ | 177 | char fw_ver_str[6]; /* The cards firmware version */ |
| 173 | int revision; /* The card's revision */ | 178 | int revision; /* The card's revision */ |
| 174 | int supports_temp; /* Wether or not the card has a temperature device */ | 179 | int supports_temp; /* Whether or not the card has |
| 175 | int command_mode; /* Wether or not the card is in command mode */ | 180 | a temperature device */ |
| 181 | int command_mode; /* Whether or not the card is in | ||
| 182 | command mode */ | ||
| 176 | int boot_status; /* The card's boot status */ | 183 | int boot_status; /* The card's boot status */ |
| 177 | int io_addr; /* The cards I/O address */ | 184 | int io_addr; /* The cards I/O address */ |
| 178 | spinlock_t io_lock; /* the lock for io operations */ | 185 | spinlock_t io_lock; /* the lock for io operations */ |
| @@ -186,16 +193,20 @@ static struct { /* this is private data for each ISA-PC watchdog card */ | |||
| 186 | #define DEBUG 2 /* print fancy stuff too */ | 193 | #define DEBUG 2 /* print fancy stuff too */ |
| 187 | static int debug = QUIET; | 194 | static int debug = QUIET; |
| 188 | module_param(debug, int, 0); | 195 | module_param(debug, int, 0); |
| 189 | MODULE_PARM_DESC(debug, "Debug level: 0=Quiet, 1=Verbose, 2=Debug (default=0)"); | 196 | MODULE_PARM_DESC(debug, |
| 197 | "Debug level: 0=Quiet, 1=Verbose, 2=Debug (default=0)"); | ||
| 190 | 198 | ||
| 191 | #define WATCHDOG_HEARTBEAT 0 /* default heartbeat = delay-time from dip-switches */ | 199 | /* default heartbeat = delay-time from dip-switches */ |
| 200 | #define WATCHDOG_HEARTBEAT 0 | ||
| 192 | static int heartbeat = WATCHDOG_HEARTBEAT; | 201 | static int heartbeat = WATCHDOG_HEARTBEAT; |
| 193 | module_param(heartbeat, int, 0); | 202 | module_param(heartbeat, int, 0); |
| 194 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<=heartbeat<=7200 or 0=delay-time from dip-switches, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | 203 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2 <= heartbeat <= 7200 or 0=delay-time from dip-switches, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); |
| 195 | 204 | ||
| 196 | static int nowayout = WATCHDOG_NOWAYOUT; | 205 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 197 | module_param(nowayout, int, 0); | 206 | module_param(nowayout, int, 0); |
| 198 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 207 | MODULE_PARM_DESC(nowayout, |
| 208 | "Watchdog cannot be stopped once started (default=" | ||
| 209 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 199 | 210 | ||
| 200 | /* | 211 | /* |
| 201 | * Internal functions | 212 | * Internal functions |
| @@ -224,7 +235,7 @@ static int send_isa_command(int cmd) | |||
| 224 | if (port0 == last_port0) | 235 | if (port0 == last_port0) |
| 225 | break; /* Data is stable */ | 236 | break; /* Data is stable */ |
| 226 | 237 | ||
| 227 | udelay (250); | 238 | udelay(250); |
| 228 | } | 239 | } |
| 229 | 240 | ||
| 230 | if (debug >= DEBUG) | 241 | if (debug >= DEBUG) |
| @@ -236,7 +247,7 @@ static int send_isa_command(int cmd) | |||
| 236 | 247 | ||
| 237 | static int set_command_mode(void) | 248 | static int set_command_mode(void) |
| 238 | { | 249 | { |
| 239 | int i, found=0, count=0; | 250 | int i, found = 0, count = 0; |
| 240 | 251 | ||
| 241 | /* Set the card into command mode */ | 252 | /* Set the card into command mode */ |
| 242 | spin_lock(&pcwd_private.io_lock); | 253 | spin_lock(&pcwd_private.io_lock); |
| @@ -261,7 +272,7 @@ static int set_command_mode(void) | |||
| 261 | printk(KERN_DEBUG PFX "command_mode=%d\n", | 272 | printk(KERN_DEBUG PFX "command_mode=%d\n", |
| 262 | pcwd_private.command_mode); | 273 | pcwd_private.command_mode); |
| 263 | 274 | ||
| 264 | return(found); | 275 | return found; |
| 265 | } | 276 | } |
| 266 | 277 | ||
| 267 | static void unset_command_mode(void) | 278 | static void unset_command_mode(void) |
| @@ -296,7 +307,8 @@ static inline void pcwd_get_firmware(void) | |||
| 296 | ten = send_isa_command(CMD_ISA_VERSION_TENTH); | 307 | ten = send_isa_command(CMD_ISA_VERSION_TENTH); |
| 297 | hund = send_isa_command(CMD_ISA_VERSION_HUNDRETH); | 308 | hund = send_isa_command(CMD_ISA_VERSION_HUNDRETH); |
| 298 | minor = send_isa_command(CMD_ISA_VERSION_MINOR); | 309 | minor = send_isa_command(CMD_ISA_VERSION_MINOR); |
| 299 | sprintf(pcwd_private.fw_ver_str, "%c.%c%c%c", one, ten, hund, minor); | 310 | sprintf(pcwd_private.fw_ver_str, "%c.%c%c%c", |
| 311 | one, ten, hund, minor); | ||
| 300 | } | 312 | } |
| 301 | unset_command_mode(); | 313 | unset_command_mode(); |
| 302 | 314 | ||
| @@ -305,7 +317,7 @@ static inline void pcwd_get_firmware(void) | |||
| 305 | 317 | ||
| 306 | static inline int pcwd_get_option_switches(void) | 318 | static inline int pcwd_get_option_switches(void) |
| 307 | { | 319 | { |
| 308 | int option_switches=0; | 320 | int option_switches = 0; |
| 309 | 321 | ||
| 310 | if (set_command_mode()) { | 322 | if (set_command_mode()) { |
| 311 | /* Get switch settings */ | 323 | /* Get switch settings */ |
| @@ -313,7 +325,7 @@ static inline int pcwd_get_option_switches(void) | |||
| 313 | } | 325 | } |
| 314 | 326 | ||
| 315 | unset_command_mode(); | 327 | unset_command_mode(); |
| 316 | return(option_switches); | 328 | return option_switches; |
| 317 | } | 329 | } |
| 318 | 330 | ||
| 319 | static void pcwd_show_card_info(void) | 331 | static void pcwd_show_card_info(void) |
| @@ -322,7 +334,9 @@ static void pcwd_show_card_info(void) | |||
| 322 | 334 | ||
| 323 | /* Get some extra info from the hardware (in command/debug/diag mode) */ | 335 | /* Get some extra info from the hardware (in command/debug/diag mode) */ |
| 324 | if (pcwd_private.revision == PCWD_REVISION_A) | 336 | if (pcwd_private.revision == PCWD_REVISION_A) |
| 325 | printk(KERN_INFO PFX "ISA-PC Watchdog (REV.A) detected at port 0x%04x\n", pcwd_private.io_addr); | 337 | printk(KERN_INFO PFX |
| 338 | "ISA-PC Watchdog (REV.A) detected at port 0x%04x\n", | ||
| 339 | pcwd_private.io_addr); | ||
| 326 | else if (pcwd_private.revision == PCWD_REVISION_C) { | 340 | else if (pcwd_private.revision == PCWD_REVISION_C) { |
| 327 | pcwd_get_firmware(); | 341 | pcwd_get_firmware(); |
| 328 | printk(KERN_INFO PFX "ISA-PC Watchdog (REV.C) detected at port 0x%04x (Firmware version: %s)\n", | 342 | printk(KERN_INFO PFX "ISA-PC Watchdog (REV.C) detected at port 0x%04x (Firmware version: %s)\n", |
| @@ -347,12 +361,15 @@ static void pcwd_show_card_info(void) | |||
| 347 | printk(KERN_INFO PFX "Previous reboot was caused by the card\n"); | 361 | printk(KERN_INFO PFX "Previous reboot was caused by the card\n"); |
| 348 | 362 | ||
| 349 | if (pcwd_private.boot_status & WDIOF_OVERHEAT) { | 363 | if (pcwd_private.boot_status & WDIOF_OVERHEAT) { |
| 350 | printk(KERN_EMERG PFX "Card senses a CPU Overheat. Panicking!\n"); | 364 | printk(KERN_EMERG PFX |
| 351 | printk(KERN_EMERG PFX "CPU Overheat\n"); | 365 | "Card senses a CPU Overheat. Panicking!\n"); |
| 366 | printk(KERN_EMERG PFX | ||
| 367 | "CPU Overheat\n"); | ||
| 352 | } | 368 | } |
| 353 | 369 | ||
| 354 | if (pcwd_private.boot_status == 0) | 370 | if (pcwd_private.boot_status == 0) |
| 355 | printk(KERN_INFO PFX "No previous trip detected - Cold boot or reset\n"); | 371 | printk(KERN_INFO PFX |
| 372 | "No previous trip detected - Cold boot or reset\n"); | ||
| 356 | } | 373 | } |
| 357 | 374 | ||
| 358 | static void pcwd_timer_ping(unsigned long data) | 375 | static void pcwd_timer_ping(unsigned long data) |
| @@ -361,11 +378,12 @@ static void pcwd_timer_ping(unsigned long data) | |||
| 361 | 378 | ||
| 362 | /* If we got a heartbeat pulse within the WDT_INTERVAL | 379 | /* If we got a heartbeat pulse within the WDT_INTERVAL |
| 363 | * we agree to ping the WDT */ | 380 | * we agree to ping the WDT */ |
| 364 | if(time_before(jiffies, pcwd_private.next_heartbeat)) { | 381 | if (time_before(jiffies, pcwd_private.next_heartbeat)) { |
| 365 | /* Ping the watchdog */ | 382 | /* Ping the watchdog */ |
| 366 | spin_lock(&pcwd_private.io_lock); | 383 | spin_lock(&pcwd_private.io_lock); |
| 367 | if (pcwd_private.revision == PCWD_REVISION_A) { | 384 | if (pcwd_private.revision == PCWD_REVISION_A) { |
| 368 | /* Rev A cards are reset by setting the WD_WDRST bit in register 1 */ | 385 | /* Rev A cards are reset by setting the |
| 386 | WD_WDRST bit in register 1 */ | ||
| 369 | wdrst_stat = inb_p(pcwd_private.io_addr); | 387 | wdrst_stat = inb_p(pcwd_private.io_addr); |
| 370 | wdrst_stat &= 0x0F; | 388 | wdrst_stat &= 0x0F; |
| 371 | wdrst_stat |= WD_WDRST; | 389 | wdrst_stat |= WD_WDRST; |
| @@ -381,7 +399,8 @@ static void pcwd_timer_ping(unsigned long data) | |||
| 381 | 399 | ||
| 382 | spin_unlock(&pcwd_private.io_lock); | 400 | spin_unlock(&pcwd_private.io_lock); |
| 383 | } else { | 401 | } else { |
| 384 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); | 402 | printk(KERN_WARNING PFX |
| 403 | "Heartbeat lost! Will not ping the watchdog\n"); | ||
| 385 | } | 404 | } |
| 386 | } | 405 | } |
| 387 | 406 | ||
| @@ -454,7 +473,7 @@ static int pcwd_keepalive(void) | |||
| 454 | 473 | ||
| 455 | static int pcwd_set_heartbeat(int t) | 474 | static int pcwd_set_heartbeat(int t) |
| 456 | { | 475 | { |
| 457 | if ((t < 2) || (t > 7200)) /* arbitrary upper limit */ | 476 | if (t < 2 || t > 7200) /* arbitrary upper limit */ |
| 458 | return -EINVAL; | 477 | return -EINVAL; |
| 459 | 478 | ||
| 460 | heartbeat = t; | 479 | heartbeat = t; |
| @@ -470,7 +489,7 @@ static int pcwd_get_status(int *status) | |||
| 470 | { | 489 | { |
| 471 | int control_status; | 490 | int control_status; |
| 472 | 491 | ||
| 473 | *status=0; | 492 | *status = 0; |
| 474 | spin_lock(&pcwd_private.io_lock); | 493 | spin_lock(&pcwd_private.io_lock); |
| 475 | if (pcwd_private.revision == PCWD_REVISION_A) | 494 | if (pcwd_private.revision == PCWD_REVISION_A) |
| 476 | /* Rev A cards return status information from | 495 | /* Rev A cards return status information from |
| @@ -494,9 +513,9 @@ static int pcwd_get_status(int *status) | |||
| 494 | if (control_status & WD_T110) { | 513 | if (control_status & WD_T110) { |
| 495 | *status |= WDIOF_OVERHEAT; | 514 | *status |= WDIOF_OVERHEAT; |
| 496 | if (temp_panic) { | 515 | if (temp_panic) { |
| 497 | printk(KERN_INFO PFX "Temperature overheat trip!\n"); | 516 | printk(KERN_INFO PFX |
| 517 | "Temperature overheat trip!\n"); | ||
| 498 | kernel_power_off(); | 518 | kernel_power_off(); |
| 499 | /* or should we just do a: panic(PFX "Temperature overheat trip!\n"); */ | ||
| 500 | } | 519 | } |
| 501 | } | 520 | } |
| 502 | } else { | 521 | } else { |
| @@ -506,9 +525,9 @@ static int pcwd_get_status(int *status) | |||
| 506 | if (control_status & WD_REVC_TTRP) { | 525 | if (control_status & WD_REVC_TTRP) { |
| 507 | *status |= WDIOF_OVERHEAT; | 526 | *status |= WDIOF_OVERHEAT; |
| 508 | if (temp_panic) { | 527 | if (temp_panic) { |
| 509 | printk(KERN_INFO PFX "Temperature overheat trip!\n"); | 528 | printk(KERN_INFO PFX |
| 529 | "Temperature overheat trip!\n"); | ||
| 510 | kernel_power_off(); | 530 | kernel_power_off(); |
| 511 | /* or should we just do a: panic(PFX "Temperature overheat trip!\n"); */ | ||
| 512 | } | 531 | } |
| 513 | } | 532 | } |
| 514 | } | 533 | } |
| @@ -524,18 +543,21 @@ static int pcwd_clear_status(void) | |||
| 524 | spin_lock(&pcwd_private.io_lock); | 543 | spin_lock(&pcwd_private.io_lock); |
| 525 | 544 | ||
| 526 | if (debug >= VERBOSE) | 545 | if (debug >= VERBOSE) |
| 527 | printk(KERN_INFO PFX "clearing watchdog trip status\n"); | 546 | printk(KERN_INFO PFX |
| 547 | "clearing watchdog trip status\n"); | ||
| 528 | 548 | ||
| 529 | control_status = inb_p(pcwd_private.io_addr + 1); | 549 | control_status = inb_p(pcwd_private.io_addr + 1); |
| 530 | 550 | ||
| 531 | if (debug >= DEBUG) { | 551 | if (debug >= DEBUG) { |
| 532 | printk(KERN_DEBUG PFX "status was: 0x%02x\n", control_status); | 552 | printk(KERN_DEBUG PFX "status was: 0x%02x\n", |
| 553 | control_status); | ||
| 533 | printk(KERN_DEBUG PFX "sending: 0x%02x\n", | 554 | printk(KERN_DEBUG PFX "sending: 0x%02x\n", |
| 534 | (control_status & WD_REVC_R2DS)); | 555 | (control_status & WD_REVC_R2DS)); |
| 535 | } | 556 | } |
| 536 | 557 | ||
| 537 | /* clear reset status & Keep Relay 2 disable state as it is */ | 558 | /* clear reset status & Keep Relay 2 disable state as it is */ |
| 538 | outb_p((control_status & WD_REVC_R2DS), pcwd_private.io_addr + 1); | 559 | outb_p((control_status & WD_REVC_R2DS), |
| 560 | pcwd_private.io_addr + 1); | ||
| 539 | 561 | ||
| 540 | spin_unlock(&pcwd_private.io_lock); | 562 | spin_unlock(&pcwd_private.io_lock); |
| 541 | } | 563 | } |
| @@ -572,8 +594,7 @@ static int pcwd_get_temperature(int *temperature) | |||
| 572 | * /dev/watchdog handling | 594 | * /dev/watchdog handling |
| 573 | */ | 595 | */ |
| 574 | 596 | ||
| 575 | static int pcwd_ioctl(struct inode *inode, struct file *file, | 597 | static long pcwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 576 | unsigned int cmd, unsigned long arg) | ||
| 577 | { | 598 | { |
| 578 | int rv; | 599 | int rv; |
| 579 | int status; | 600 | int status; |
| @@ -590,12 +611,9 @@ static int pcwd_ioctl(struct inode *inode, struct file *file, | |||
| 590 | .identity = "PCWD", | 611 | .identity = "PCWD", |
| 591 | }; | 612 | }; |
| 592 | 613 | ||
| 593 | switch(cmd) { | 614 | switch (cmd) { |
| 594 | default: | ||
| 595 | return -ENOTTY; | ||
| 596 | |||
| 597 | case WDIOC_GETSUPPORT: | 615 | case WDIOC_GETSUPPORT: |
| 598 | if(copy_to_user(argp, &ident, sizeof(ident))) | 616 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 599 | return -EFAULT; | 617 | return -EFAULT; |
| 600 | return 0; | 618 | return 0; |
| 601 | 619 | ||
| @@ -613,25 +631,22 @@ static int pcwd_ioctl(struct inode *inode, struct file *file, | |||
| 613 | return put_user(temperature, argp); | 631 | return put_user(temperature, argp); |
| 614 | 632 | ||
| 615 | case WDIOC_SETOPTIONS: | 633 | case WDIOC_SETOPTIONS: |
| 616 | if (pcwd_private.revision == PCWD_REVISION_C) | 634 | if (pcwd_private.revision == PCWD_REVISION_C) { |
| 617 | { | 635 | if (get_user(rv, argp)) |
| 618 | if(copy_from_user(&rv, argp, sizeof(int))) | ||
| 619 | return -EFAULT; | 636 | return -EFAULT; |
| 620 | 637 | ||
| 621 | if (rv & WDIOS_DISABLECARD) | 638 | if (rv & WDIOS_DISABLECARD) { |
| 622 | { | 639 | status = pcwd_stop(); |
| 623 | return pcwd_stop(); | 640 | if (status < 0) |
| 641 | return status; | ||
| 624 | } | 642 | } |
| 625 | 643 | if (rv & WDIOS_ENABLECARD) { | |
| 626 | if (rv & WDIOS_ENABLECARD) | 644 | status = pcwd_start(); |
| 627 | { | 645 | if (status < 0) |
| 628 | return pcwd_start(); | 646 | return status; |
| 629 | } | 647 | } |
| 630 | |||
| 631 | if (rv & WDIOS_TEMPPANIC) | 648 | if (rv & WDIOS_TEMPPANIC) |
| 632 | { | ||
| 633 | temp_panic = 1; | 649 | temp_panic = 1; |
| 634 | } | ||
| 635 | } | 650 | } |
| 636 | return -EINVAL; | 651 | return -EINVAL; |
| 637 | 652 | ||
| @@ -651,6 +666,9 @@ static int pcwd_ioctl(struct inode *inode, struct file *file, | |||
| 651 | 666 | ||
| 652 | case WDIOC_GETTIMEOUT: | 667 | case WDIOC_GETTIMEOUT: |
| 653 | return put_user(heartbeat, argp); | 668 | return put_user(heartbeat, argp); |
| 669 | |||
| 670 | default: | ||
| 671 | return -ENOTTY; | ||
| 654 | } | 672 | } |
| 655 | 673 | ||
| 656 | return 0; | 674 | return 0; |
| @@ -682,16 +700,10 @@ static ssize_t pcwd_write(struct file *file, const char __user *buf, size_t len, | |||
| 682 | 700 | ||
| 683 | static int pcwd_open(struct inode *inode, struct file *file) | 701 | static int pcwd_open(struct inode *inode, struct file *file) |
| 684 | { | 702 | { |
| 685 | if (!atomic_dec_and_test(&open_allowed) ) { | 703 | if (test_and_set_bit(0, &open_allowed)) |
| 686 | if (debug >= VERBOSE) | ||
| 687 | printk(KERN_ERR PFX "Attempt to open already opened device.\n"); | ||
| 688 | atomic_inc( &open_allowed ); | ||
| 689 | return -EBUSY; | 704 | return -EBUSY; |
| 690 | } | ||
| 691 | |||
| 692 | if (nowayout) | 705 | if (nowayout) |
| 693 | __module_get(THIS_MODULE); | 706 | __module_get(THIS_MODULE); |
| 694 | |||
| 695 | /* Activate */ | 707 | /* Activate */ |
| 696 | pcwd_start(); | 708 | pcwd_start(); |
| 697 | pcwd_keepalive(); | 709 | pcwd_keepalive(); |
| @@ -700,14 +712,15 @@ static int pcwd_open(struct inode *inode, struct file *file) | |||
| 700 | 712 | ||
| 701 | static int pcwd_close(struct inode *inode, struct file *file) | 713 | static int pcwd_close(struct inode *inode, struct file *file) |
| 702 | { | 714 | { |
| 703 | if (expect_close == 42) { | 715 | if (expect_close == 42) |
| 704 | pcwd_stop(); | 716 | pcwd_stop(); |
| 705 | } else { | 717 | else { |
| 706 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 718 | printk(KERN_CRIT PFX |
| 719 | "Unexpected close, not stopping watchdog!\n"); | ||
| 707 | pcwd_keepalive(); | 720 | pcwd_keepalive(); |
| 708 | } | 721 | } |
| 709 | expect_close = 0; | 722 | expect_close = 0; |
| 710 | atomic_inc( &open_allowed ); | 723 | clear_bit(0, &open_allowed); |
| 711 | return 0; | 724 | return 0; |
| 712 | } | 725 | } |
| 713 | 726 | ||
| @@ -750,7 +763,7 @@ static const struct file_operations pcwd_fops = { | |||
| 750 | .owner = THIS_MODULE, | 763 | .owner = THIS_MODULE, |
| 751 | .llseek = no_llseek, | 764 | .llseek = no_llseek, |
| 752 | .write = pcwd_write, | 765 | .write = pcwd_write, |
| 753 | .ioctl = pcwd_ioctl, | 766 | .unlocked_ioctl = pcwd_ioctl, |
| 754 | .open = pcwd_open, | 767 | .open = pcwd_open, |
| 755 | .release = pcwd_close, | 768 | .release = pcwd_close, |
| 756 | }; | 769 | }; |
| @@ -788,7 +801,7 @@ static inline int get_revision(void) | |||
| 788 | * presumes a floating bus reads as 0xff. */ | 801 | * presumes a floating bus reads as 0xff. */ |
| 789 | if ((inb(pcwd_private.io_addr + 2) == 0xFF) || | 802 | if ((inb(pcwd_private.io_addr + 2) == 0xFF) || |
| 790 | (inb(pcwd_private.io_addr + 3) == 0xFF)) | 803 | (inb(pcwd_private.io_addr + 3) == 0xFF)) |
| 791 | r=PCWD_REVISION_A; | 804 | r = PCWD_REVISION_A; |
| 792 | spin_unlock(&pcwd_private.io_lock); | 805 | spin_unlock(&pcwd_private.io_lock); |
| 793 | 806 | ||
| 794 | return r; | 807 | return r; |
| @@ -803,7 +816,7 @@ static inline int get_revision(void) | |||
| 803 | */ | 816 | */ |
| 804 | static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) | 817 | static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) |
| 805 | { | 818 | { |
| 806 | int base_addr=pcwd_ioports[id]; | 819 | int base_addr = pcwd_ioports[id]; |
| 807 | int port0, last_port0; /* Reg 0, in case it's REV A */ | 820 | int port0, last_port0; /* Reg 0, in case it's REV A */ |
| 808 | int port1, last_port1; /* Register 1 for REV C cards */ | 821 | int port1, last_port1; /* Register 1 for REV C cards */ |
| 809 | int i; | 822 | int i; |
| @@ -813,7 +826,7 @@ static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) | |||
| 813 | printk(KERN_DEBUG PFX "pcwd_isa_match id=%d\n", | 826 | printk(KERN_DEBUG PFX "pcwd_isa_match id=%d\n", |
| 814 | id); | 827 | id); |
| 815 | 828 | ||
| 816 | if (!request_region (base_addr, 4, "PCWD")) { | 829 | if (!request_region(base_addr, 4, "PCWD")) { |
| 817 | printk(KERN_INFO PFX "Port 0x%04x unavailable\n", base_addr); | 830 | printk(KERN_INFO PFX "Port 0x%04x unavailable\n", base_addr); |
| 818 | return 0; | 831 | return 0; |
| 819 | } | 832 | } |
| @@ -842,7 +855,7 @@ static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) | |||
| 842 | } | 855 | } |
| 843 | } | 856 | } |
| 844 | } | 857 | } |
| 845 | release_region (base_addr, 4); | 858 | release_region(base_addr, 4); |
| 846 | 859 | ||
| 847 | return retval; | 860 | return retval; |
| 848 | } | 861 | } |
| @@ -857,7 +870,8 @@ static int __devinit pcwd_isa_probe(struct device *dev, unsigned int id) | |||
| 857 | 870 | ||
| 858 | cards_found++; | 871 | cards_found++; |
| 859 | if (cards_found == 1) | 872 | if (cards_found == 1) |
| 860 | printk(KERN_INFO PFX "v%s Ken Hollis (kenji@bitgate.com)\n", WD_VER); | 873 | printk(KERN_INFO PFX "v%s Ken Hollis (kenji@bitgate.com)\n", |
| 874 | WD_VER); | ||
| 861 | 875 | ||
| 862 | if (cards_found > 1) { | 876 | if (cards_found > 1) { |
| 863 | printk(KERN_ERR PFX "This driver only supports 1 device\n"); | 877 | printk(KERN_ERR PFX "This driver only supports 1 device\n"); |
| @@ -875,10 +889,11 @@ static int __devinit pcwd_isa_probe(struct device *dev, unsigned int id) | |||
| 875 | /* Check card's revision */ | 889 | /* Check card's revision */ |
| 876 | pcwd_private.revision = get_revision(); | 890 | pcwd_private.revision = get_revision(); |
| 877 | 891 | ||
| 878 | if (!request_region(pcwd_private.io_addr, (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4, "PCWD")) { | 892 | if (!request_region(pcwd_private.io_addr, |
| 893 | (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4, "PCWD")) { | ||
| 879 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 894 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 880 | pcwd_private.io_addr); | 895 | pcwd_private.io_addr); |
| 881 | ret=-EIO; | 896 | ret = -EIO; |
| 882 | goto error_request_region; | 897 | goto error_request_region; |
| 883 | } | 898 | } |
| 884 | 899 | ||
| @@ -908,26 +923,30 @@ static int __devinit pcwd_isa_probe(struct device *dev, unsigned int id) | |||
| 908 | if (heartbeat == 0) | 923 | if (heartbeat == 0) |
| 909 | heartbeat = heartbeat_tbl[(pcwd_get_option_switches() & 0x07)]; | 924 | heartbeat = heartbeat_tbl[(pcwd_get_option_switches() & 0x07)]; |
| 910 | 925 | ||
| 911 | /* Check that the heartbeat value is within it's range ; if not reset to the default */ | 926 | /* Check that the heartbeat value is within it's range; |
| 927 | if not reset to the default */ | ||
| 912 | if (pcwd_set_heartbeat(heartbeat)) { | 928 | if (pcwd_set_heartbeat(heartbeat)) { |
| 913 | pcwd_set_heartbeat(WATCHDOG_HEARTBEAT); | 929 | pcwd_set_heartbeat(WATCHDOG_HEARTBEAT); |
| 914 | printk(KERN_INFO PFX "heartbeat value must be 2<=heartbeat<=7200, using %d\n", | 930 | printk(KERN_INFO PFX |
| 915 | WATCHDOG_HEARTBEAT); | 931 | "heartbeat value must be 2 <= heartbeat <= 7200, using %d\n", |
| 932 | WATCHDOG_HEARTBEAT); | ||
| 916 | } | 933 | } |
| 917 | 934 | ||
| 918 | if (pcwd_private.supports_temp) { | 935 | if (pcwd_private.supports_temp) { |
| 919 | ret = misc_register(&temp_miscdev); | 936 | ret = misc_register(&temp_miscdev); |
| 920 | if (ret) { | 937 | if (ret) { |
| 921 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 938 | printk(KERN_ERR PFX |
| 922 | TEMP_MINOR, ret); | 939 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 940 | TEMP_MINOR, ret); | ||
| 923 | goto error_misc_register_temp; | 941 | goto error_misc_register_temp; |
| 924 | } | 942 | } |
| 925 | } | 943 | } |
| 926 | 944 | ||
| 927 | ret = misc_register(&pcwd_miscdev); | 945 | ret = misc_register(&pcwd_miscdev); |
| 928 | if (ret) { | 946 | if (ret) { |
| 929 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 947 | printk(KERN_ERR PFX |
| 930 | WATCHDOG_MINOR, ret); | 948 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 949 | WATCHDOG_MINOR, ret); | ||
| 931 | goto error_misc_register_watchdog; | 950 | goto error_misc_register_watchdog; |
| 932 | } | 951 | } |
| 933 | 952 | ||
| @@ -940,7 +959,8 @@ error_misc_register_watchdog: | |||
| 940 | if (pcwd_private.supports_temp) | 959 | if (pcwd_private.supports_temp) |
| 941 | misc_deregister(&temp_miscdev); | 960 | misc_deregister(&temp_miscdev); |
| 942 | error_misc_register_temp: | 961 | error_misc_register_temp: |
| 943 | release_region(pcwd_private.io_addr, (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); | 962 | release_region(pcwd_private.io_addr, |
| 963 | (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); | ||
| 944 | error_request_region: | 964 | error_request_region: |
| 945 | pcwd_private.io_addr = 0x0000; | 965 | pcwd_private.io_addr = 0x0000; |
| 946 | cards_found--; | 966 | cards_found--; |
| @@ -964,7 +984,8 @@ static int __devexit pcwd_isa_remove(struct device *dev, unsigned int id) | |||
| 964 | misc_deregister(&pcwd_miscdev); | 984 | misc_deregister(&pcwd_miscdev); |
| 965 | if (pcwd_private.supports_temp) | 985 | if (pcwd_private.supports_temp) |
| 966 | misc_deregister(&temp_miscdev); | 986 | misc_deregister(&temp_miscdev); |
| 967 | release_region(pcwd_private.io_addr, (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); | 987 | release_region(pcwd_private.io_addr, |
| 988 | (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); | ||
| 968 | pcwd_private.io_addr = 0x0000; | 989 | pcwd_private.io_addr = 0x0000; |
| 969 | cards_found--; | 990 | cards_found--; |
| 970 | 991 | ||
diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 61a89e959642..90eb1d4271d7 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c | |||
| @@ -46,9 +46,8 @@ | |||
| 46 | #include <linux/pci.h> /* For pci functions */ | 46 | #include <linux/pci.h> /* For pci functions */ |
| 47 | #include <linux/ioport.h> /* For io-port access */ | 47 | #include <linux/ioport.h> /* For io-port access */ |
| 48 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | 48 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ |
| 49 | 49 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ | |
| 50 | #include <asm/uaccess.h> /* For copy_to_user/put_user/... */ | 50 | #include <linux/io.h> /* For inb/outb/... */ |
| 51 | #include <asm/io.h> /* For inb/outb/... */ | ||
| 52 | 51 | ||
| 53 | /* Module and version information */ | 52 | /* Module and version information */ |
| 54 | #define WATCHDOG_VERSION "1.03" | 53 | #define WATCHDOG_VERSION "1.03" |
| @@ -97,7 +96,7 @@ | |||
| 97 | #define CMD_GET_CLEAR_RESET_COUNT 0x84 | 96 | #define CMD_GET_CLEAR_RESET_COUNT 0x84 |
| 98 | 97 | ||
| 99 | /* Watchdog's Dip Switch heartbeat values */ | 98 | /* Watchdog's Dip Switch heartbeat values */ |
| 100 | static const int heartbeat_tbl [] = { | 99 | static const int heartbeat_tbl[] = { |
| 101 | 5, /* OFF-OFF-OFF = 5 Sec */ | 100 | 5, /* OFF-OFF-OFF = 5 Sec */ |
| 102 | 10, /* OFF-OFF-ON = 10 Sec */ | 101 | 10, /* OFF-OFF-ON = 10 Sec */ |
| 103 | 30, /* OFF-ON-OFF = 30 Sec */ | 102 | 30, /* OFF-ON-OFF = 30 Sec */ |
| @@ -220,11 +219,10 @@ static void pcipcwd_show_card_info(void) | |||
| 220 | int option_switches; | 219 | int option_switches; |
| 221 | 220 | ||
| 222 | got_fw_rev = send_command(CMD_GET_FIRMWARE_VERSION, &fw_rev_major, &fw_rev_minor); | 221 | got_fw_rev = send_command(CMD_GET_FIRMWARE_VERSION, &fw_rev_major, &fw_rev_minor); |
| 223 | if (got_fw_rev) { | 222 | if (got_fw_rev) |
| 224 | sprintf(fw_ver_str, "%u.%02u", fw_rev_major, fw_rev_minor); | 223 | sprintf(fw_ver_str, "%u.%02u", fw_rev_major, fw_rev_minor); |
| 225 | } else { | 224 | else |
| 226 | sprintf(fw_ver_str, "<card no answer>"); | 225 | sprintf(fw_ver_str, "<card no answer>"); |
| 227 | } | ||
| 228 | 226 | ||
| 229 | /* Get switch settings */ | 227 | /* Get switch settings */ |
| 230 | option_switches = pcipcwd_get_option_switches(); | 228 | option_switches = pcipcwd_get_option_switches(); |
| @@ -331,7 +329,7 @@ static int pcipcwd_get_status(int *status) | |||
| 331 | { | 329 | { |
| 332 | int control_status; | 330 | int control_status; |
| 333 | 331 | ||
| 334 | *status=0; | 332 | *status = 0; |
| 335 | control_status = inb_p(pcipcwd_private.io_addr + 1); | 333 | control_status = inb_p(pcipcwd_private.io_addr + 1); |
| 336 | if (control_status & WD_PCI_WTRP) | 334 | if (control_status & WD_PCI_WTRP) |
| 337 | *status |= WDIOF_CARDRESET; | 335 | *status |= WDIOF_CARDRESET; |
| @@ -369,8 +367,8 @@ static int pcipcwd_clear_status(void) | |||
| 369 | outb_p((control_status & WD_PCI_R2DS) | WD_PCI_WTRP, pcipcwd_private.io_addr + 1); | 367 | outb_p((control_status & WD_PCI_R2DS) | WD_PCI_WTRP, pcipcwd_private.io_addr + 1); |
| 370 | 368 | ||
| 371 | /* clear reset counter */ | 369 | /* clear reset counter */ |
| 372 | msb=0; | 370 | msb = 0; |
| 373 | reset_counter=0xff; | 371 | reset_counter = 0xff; |
| 374 | send_command(CMD_GET_CLEAR_RESET_COUNT, &msb, &reset_counter); | 372 | send_command(CMD_GET_CLEAR_RESET_COUNT, &msb, &reset_counter); |
| 375 | 373 | ||
| 376 | if (debug >= DEBUG) { | 374 | if (debug >= DEBUG) { |
| @@ -442,7 +440,7 @@ static ssize_t pcipcwd_write(struct file *file, const char __user *data, | |||
| 442 | /* scan to see whether or not we got the magic character */ | 440 | /* scan to see whether or not we got the magic character */ |
| 443 | for (i = 0; i != len; i++) { | 441 | for (i = 0; i != len; i++) { |
| 444 | char c; | 442 | char c; |
| 445 | if(get_user(c, data+i)) | 443 | if (get_user(c, data + i)) |
| 446 | return -EFAULT; | 444 | return -EFAULT; |
| 447 | if (c == 'V') | 445 | if (c == 'V') |
| 448 | expect_release = 42; | 446 | expect_release = 42; |
| @@ -455,8 +453,8 @@ static ssize_t pcipcwd_write(struct file *file, const char __user *data, | |||
| 455 | return len; | 453 | return len; |
| 456 | } | 454 | } |
| 457 | 455 | ||
| 458 | static int pcipcwd_ioctl(struct inode *inode, struct file *file, | 456 | static long pcipcwd_ioctl(struct file *file, unsigned int cmd, |
| 459 | unsigned int cmd, unsigned long arg) | 457 | unsigned long arg) |
| 460 | { | 458 | { |
| 461 | void __user *argp = (void __user *)arg; | 459 | void __user *argp = (void __user *)arg; |
| 462 | int __user *p = argp; | 460 | int __user *p = argp; |
| @@ -471,92 +469,89 @@ static int pcipcwd_ioctl(struct inode *inode, struct file *file, | |||
| 471 | }; | 469 | }; |
| 472 | 470 | ||
| 473 | switch (cmd) { | 471 | switch (cmd) { |
| 474 | case WDIOC_GETSUPPORT: | 472 | case WDIOC_GETSUPPORT: |
| 475 | return copy_to_user(argp, &ident, | 473 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 476 | sizeof (ident)) ? -EFAULT : 0; | 474 | |
| 475 | case WDIOC_GETSTATUS: | ||
| 476 | { | ||
| 477 | int status; | ||
| 478 | pcipcwd_get_status(&status); | ||
| 479 | return put_user(status, p); | ||
| 480 | } | ||
| 477 | 481 | ||
| 478 | case WDIOC_GETSTATUS: | 482 | case WDIOC_GETBOOTSTATUS: |
| 479 | { | 483 | return put_user(pcipcwd_private.boot_status, p); |
| 480 | int status; | ||
| 481 | 484 | ||
| 482 | pcipcwd_get_status(&status); | 485 | case WDIOC_GETTEMP: |
| 486 | { | ||
| 487 | int temperature; | ||
| 483 | 488 | ||
| 484 | return put_user(status, p); | 489 | if (pcipcwd_get_temperature(&temperature)) |
| 485 | } | 490 | return -EFAULT; |
| 486 | 491 | ||
| 487 | case WDIOC_GETBOOTSTATUS: | 492 | return put_user(temperature, p); |
| 488 | return put_user(pcipcwd_private.boot_status, p); | 493 | } |
| 489 | 494 | ||
| 490 | case WDIOC_GETTEMP: | 495 | case WDIOC_SETOPTIONS: |
| 491 | { | 496 | { |
| 492 | int temperature; | 497 | int new_options, retval = -EINVAL; |
| 493 | 498 | ||
| 494 | if (pcipcwd_get_temperature(&temperature)) | 499 | if (get_user(new_options, p)) |
| 495 | return -EFAULT; | 500 | return -EFAULT; |
| 496 | 501 | ||
| 497 | return put_user(temperature, p); | 502 | if (new_options & WDIOS_DISABLECARD) { |
| 503 | if (pcipcwd_stop()) | ||
| 504 | return -EIO; | ||
| 505 | retval = 0; | ||
| 498 | } | 506 | } |
| 499 | 507 | ||
| 500 | case WDIOC_KEEPALIVE: | 508 | if (new_options & WDIOS_ENABLECARD) { |
| 501 | pcipcwd_keepalive(); | 509 | if (pcipcwd_start()) |
| 502 | return 0; | 510 | return -EIO; |
| 503 | 511 | retval = 0; | |
| 504 | case WDIOC_SETOPTIONS: | 512 | } |
| 505 | { | ||
| 506 | int new_options, retval = -EINVAL; | ||
| 507 | |||
| 508 | if (get_user (new_options, p)) | ||
| 509 | return -EFAULT; | ||
| 510 | |||
| 511 | if (new_options & WDIOS_DISABLECARD) { | ||
| 512 | if (pcipcwd_stop()) | ||
| 513 | return -EIO; | ||
| 514 | retval = 0; | ||
| 515 | } | ||
| 516 | 513 | ||
| 517 | if (new_options & WDIOS_ENABLECARD) { | 514 | if (new_options & WDIOS_TEMPPANIC) { |
| 518 | if (pcipcwd_start()) | 515 | temp_panic = 1; |
| 519 | return -EIO; | 516 | retval = 0; |
| 520 | retval = 0; | 517 | } |
| 521 | } | ||
| 522 | 518 | ||
| 523 | if (new_options & WDIOS_TEMPPANIC) { | 519 | return retval; |
| 524 | temp_panic = 1; | 520 | } |
| 525 | retval = 0; | ||
| 526 | } | ||
| 527 | 521 | ||
| 528 | return retval; | 522 | case WDIOC_KEEPALIVE: |
| 529 | } | 523 | pcipcwd_keepalive(); |
| 524 | return 0; | ||
| 530 | 525 | ||
| 531 | case WDIOC_SETTIMEOUT: | 526 | case WDIOC_SETTIMEOUT: |
| 532 | { | 527 | { |
| 533 | int new_heartbeat; | 528 | int new_heartbeat; |
| 534 | 529 | ||
| 535 | if (get_user(new_heartbeat, p)) | 530 | if (get_user(new_heartbeat, p)) |
| 536 | return -EFAULT; | 531 | return -EFAULT; |
| 537 | 532 | ||
| 538 | if (pcipcwd_set_heartbeat(new_heartbeat)) | 533 | if (pcipcwd_set_heartbeat(new_heartbeat)) |
| 539 | return -EINVAL; | 534 | return -EINVAL; |
| 540 | 535 | ||
| 541 | pcipcwd_keepalive(); | 536 | pcipcwd_keepalive(); |
| 542 | /* Fall */ | 537 | /* Fall */ |
| 543 | } | 538 | } |
| 544 | 539 | ||
| 545 | case WDIOC_GETTIMEOUT: | 540 | case WDIOC_GETTIMEOUT: |
| 546 | return put_user(heartbeat, p); | 541 | return put_user(heartbeat, p); |
| 547 | 542 | ||
| 548 | case WDIOC_GETTIMELEFT: | 543 | case WDIOC_GETTIMELEFT: |
| 549 | { | 544 | { |
| 550 | int time_left; | 545 | int time_left; |
| 551 | 546 | ||
| 552 | if (pcipcwd_get_timeleft(&time_left)) | 547 | if (pcipcwd_get_timeleft(&time_left)) |
| 553 | return -EFAULT; | 548 | return -EFAULT; |
| 554 | 549 | ||
| 555 | return put_user(time_left, p); | 550 | return put_user(time_left, p); |
| 556 | } | 551 | } |
| 557 | 552 | ||
| 558 | default: | 553 | default: |
| 559 | return -ENOTTY; | 554 | return -ENOTTY; |
| 560 | } | 555 | } |
| 561 | } | 556 | } |
| 562 | 557 | ||
| @@ -603,7 +598,7 @@ static ssize_t pcipcwd_temp_read(struct file *file, char __user *data, | |||
| 603 | if (pcipcwd_get_temperature(&temperature)) | 598 | if (pcipcwd_get_temperature(&temperature)) |
| 604 | return -EFAULT; | 599 | return -EFAULT; |
| 605 | 600 | ||
| 606 | if (copy_to_user (data, &temperature, 1)) | 601 | if (copy_to_user(data, &temperature, 1)) |
| 607 | return -EFAULT; | 602 | return -EFAULT; |
| 608 | 603 | ||
| 609 | return 1; | 604 | return 1; |
| @@ -628,10 +623,8 @@ static int pcipcwd_temp_release(struct inode *inode, struct file *file) | |||
| 628 | 623 | ||
| 629 | static int pcipcwd_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 624 | static int pcipcwd_notify_sys(struct notifier_block *this, unsigned long code, void *unused) |
| 630 | { | 625 | { |
| 631 | if (code==SYS_DOWN || code==SYS_HALT) { | 626 | if (code == SYS_DOWN || code == SYS_HALT) |
| 632 | /* Turn the WDT off */ | 627 | pcipcwd_stop(); /* Turn the WDT off */ |
| 633 | pcipcwd_stop(); | ||
| 634 | } | ||
| 635 | 628 | ||
| 636 | return NOTIFY_DONE; | 629 | return NOTIFY_DONE; |
| 637 | } | 630 | } |
| @@ -644,7 +637,7 @@ static const struct file_operations pcipcwd_fops = { | |||
| 644 | .owner = THIS_MODULE, | 637 | .owner = THIS_MODULE, |
| 645 | .llseek = no_llseek, | 638 | .llseek = no_llseek, |
| 646 | .write = pcipcwd_write, | 639 | .write = pcipcwd_write, |
| 647 | .ioctl = pcipcwd_ioctl, | 640 | .unlocked_ioctl = pcipcwd_ioctl, |
| 648 | .open = pcipcwd_open, | 641 | .open = pcipcwd_open, |
| 649 | .release = pcipcwd_release, | 642 | .release = pcipcwd_release, |
| 650 | }; | 643 | }; |
diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index bf443d077a1e..c1685c942de6 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c | |||
| @@ -40,8 +40,7 @@ | |||
| 40 | #include <linux/slab.h> /* For kmalloc, ... */ | 40 | #include <linux/slab.h> /* For kmalloc, ... */ |
| 41 | #include <linux/mutex.h> /* For mutex locking */ | 41 | #include <linux/mutex.h> /* For mutex locking */ |
| 42 | #include <linux/hid.h> /* For HID_REQ_SET_REPORT & HID_DT_REPORT */ | 42 | #include <linux/hid.h> /* For HID_REQ_SET_REPORT & HID_DT_REPORT */ |
| 43 | 43 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ | |
| 44 | #include <asm/uaccess.h> /* For copy_to_user/put_user/... */ | ||
| 45 | 44 | ||
| 46 | 45 | ||
| 47 | #ifdef CONFIG_USB_DEBUG | 46 | #ifdef CONFIG_USB_DEBUG |
| @@ -88,7 +87,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" _ | |||
| 88 | #define USB_PCWD_PRODUCT_ID 0x1140 | 87 | #define USB_PCWD_PRODUCT_ID 0x1140 |
| 89 | 88 | ||
| 90 | /* table of devices that work with this driver */ | 89 | /* table of devices that work with this driver */ |
| 91 | static struct usb_device_id usb_pcwd_table [] = { | 90 | static struct usb_device_id usb_pcwd_table[] = { |
| 92 | { USB_DEVICE(USB_PCWD_VENDOR_ID, USB_PCWD_PRODUCT_ID) }, | 91 | { USB_DEVICE(USB_PCWD_VENDOR_ID, USB_PCWD_PRODUCT_ID) }, |
| 93 | { } /* Terminating entry */ | 92 | { } /* Terminating entry */ |
| 94 | }; | 93 | }; |
| @@ -110,7 +109,7 @@ MODULE_DEVICE_TABLE (usb, usb_pcwd_table); | |||
| 110 | #define CMD_DISABLE_WATCHDOG CMD_ENABLE_WATCHDOG | 109 | #define CMD_DISABLE_WATCHDOG CMD_ENABLE_WATCHDOG |
| 111 | 110 | ||
| 112 | /* Watchdog's Dip Switch heartbeat values */ | 111 | /* Watchdog's Dip Switch heartbeat values */ |
| 113 | static const int heartbeat_tbl [] = { | 112 | static const int heartbeat_tbl[] = { |
| 114 | 5, /* OFF-OFF-OFF = 5 Sec */ | 113 | 5, /* OFF-OFF-OFF = 5 Sec */ |
| 115 | 10, /* OFF-OFF-ON = 10 Sec */ | 114 | 10, /* OFF-OFF-ON = 10 Sec */ |
| 116 | 30, /* OFF-ON-OFF = 30 Sec */ | 115 | 30, /* OFF-ON-OFF = 30 Sec */ |
| @@ -130,15 +129,15 @@ static char expect_release; | |||
| 130 | 129 | ||
| 131 | /* Structure to hold all of our device specific stuff */ | 130 | /* Structure to hold all of our device specific stuff */ |
| 132 | struct usb_pcwd_private { | 131 | struct usb_pcwd_private { |
| 133 | struct usb_device * udev; /* save off the usb device pointer */ | 132 | struct usb_device *udev; /* save off the usb device pointer */ |
| 134 | struct usb_interface * interface; /* the interface for this device */ | 133 | struct usb_interface *interface; /* the interface for this device */ |
| 135 | 134 | ||
| 136 | unsigned int interface_number; /* the interface number used for cmd's */ | 135 | unsigned int interface_number; /* the interface number used for cmd's */ |
| 137 | 136 | ||
| 138 | unsigned char * intr_buffer; /* the buffer to intr data */ | 137 | unsigned char *intr_buffer; /* the buffer to intr data */ |
| 139 | dma_addr_t intr_dma; /* the dma address for the intr buffer */ | 138 | dma_addr_t intr_dma; /* the dma address for the intr buffer */ |
| 140 | size_t intr_size; /* the size of the intr buffer */ | 139 | size_t intr_size; /* the size of the intr buffer */ |
| 141 | struct urb * intr_urb; /* the urb used for the intr pipe */ | 140 | struct urb *intr_urb; /* the urb used for the intr pipe */ |
| 142 | 141 | ||
| 143 | unsigned char cmd_command; /* The command that is reported back */ | 142 | unsigned char cmd_command; /* The command that is reported back */ |
| 144 | unsigned char cmd_data_msb; /* The data MSB that is reported back */ | 143 | unsigned char cmd_data_msb; /* The data MSB that is reported back */ |
| @@ -154,8 +153,8 @@ static struct usb_pcwd_private *usb_pcwd_device; | |||
| 154 | static DEFINE_MUTEX(disconnect_mutex); | 153 | static DEFINE_MUTEX(disconnect_mutex); |
| 155 | 154 | ||
| 156 | /* local function prototypes */ | 155 | /* local function prototypes */ |
| 157 | static int usb_pcwd_probe (struct usb_interface *interface, const struct usb_device_id *id); | 156 | static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_device_id *id); |
| 158 | static void usb_pcwd_disconnect (struct usb_interface *interface); | 157 | static void usb_pcwd_disconnect(struct usb_interface *interface); |
| 159 | 158 | ||
| 160 | /* usb specific object needed to register this driver with the usb subsystem */ | 159 | /* usb specific object needed to register this driver with the usb subsystem */ |
| 161 | static struct usb_driver usb_pcwd_driver = { | 160 | static struct usb_driver usb_pcwd_driver = { |
| @@ -195,10 +194,10 @@ static void usb_pcwd_intr_done(struct urb *urb) | |||
| 195 | usb_pcwd->cmd_data_lsb = data[2]; | 194 | usb_pcwd->cmd_data_lsb = data[2]; |
| 196 | 195 | ||
| 197 | /* notify anyone waiting that the cmd has finished */ | 196 | /* notify anyone waiting that the cmd has finished */ |
| 198 | atomic_set (&usb_pcwd->cmd_received, 1); | 197 | atomic_set(&usb_pcwd->cmd_received, 1); |
| 199 | 198 | ||
| 200 | resubmit: | 199 | resubmit: |
| 201 | retval = usb_submit_urb (urb, GFP_ATOMIC); | 200 | retval = usb_submit_urb(urb, GFP_ATOMIC); |
| 202 | if (retval) | 201 | if (retval) |
| 203 | printk(KERN_ERR PFX "can't resubmit intr, usb_submit_urb failed with result %d\n", | 202 | printk(KERN_ERR PFX "can't resubmit intr, usb_submit_urb failed with result %d\n", |
| 204 | retval); | 203 | retval); |
| @@ -224,7 +223,7 @@ static int usb_pcwd_send_command(struct usb_pcwd_private *usb_pcwd, unsigned cha | |||
| 224 | dbg("sending following data cmd=0x%02x msb=0x%02x lsb=0x%02x", | 223 | dbg("sending following data cmd=0x%02x msb=0x%02x lsb=0x%02x", |
| 225 | buf[0], buf[1], buf[2]); | 224 | buf[0], buf[1], buf[2]); |
| 226 | 225 | ||
| 227 | atomic_set (&usb_pcwd->cmd_received, 0); | 226 | atomic_set(&usb_pcwd->cmd_received, 0); |
| 228 | 227 | ||
| 229 | if (usb_control_msg(usb_pcwd->udev, usb_sndctrlpipe(usb_pcwd->udev, 0), | 228 | if (usb_control_msg(usb_pcwd->udev, usb_sndctrlpipe(usb_pcwd->udev, 0), |
| 230 | HID_REQ_SET_REPORT, HID_DT_REPORT, | 229 | HID_REQ_SET_REPORT, HID_DT_REPORT, |
| @@ -237,7 +236,7 @@ static int usb_pcwd_send_command(struct usb_pcwd_private *usb_pcwd, unsigned cha | |||
| 237 | got_response = 0; | 236 | got_response = 0; |
| 238 | for (count = 0; (count < USB_COMMAND_TIMEOUT) && (!got_response); count++) { | 237 | for (count = 0; (count < USB_COMMAND_TIMEOUT) && (!got_response); count++) { |
| 239 | mdelay(1); | 238 | mdelay(1); |
| 240 | if (atomic_read (&usb_pcwd->cmd_received)) | 239 | if (atomic_read(&usb_pcwd->cmd_received)) |
| 241 | got_response = 1; | 240 | got_response = 1; |
| 242 | } | 241 | } |
| 243 | 242 | ||
| @@ -356,7 +355,7 @@ static ssize_t usb_pcwd_write(struct file *file, const char __user *data, | |||
| 356 | /* scan to see whether or not we got the magic character */ | 355 | /* scan to see whether or not we got the magic character */ |
| 357 | for (i = 0; i != len; i++) { | 356 | for (i = 0; i != len; i++) { |
| 358 | char c; | 357 | char c; |
| 359 | if(get_user(c, data+i)) | 358 | if (get_user(c, data + i)) |
| 360 | return -EFAULT; | 359 | return -EFAULT; |
| 361 | if (c == 'V') | 360 | if (c == 'V') |
| 362 | expect_release = 42; | 361 | expect_release = 42; |
| @@ -369,8 +368,8 @@ static ssize_t usb_pcwd_write(struct file *file, const char __user *data, | |||
| 369 | return len; | 368 | return len; |
| 370 | } | 369 | } |
| 371 | 370 | ||
| 372 | static int usb_pcwd_ioctl(struct inode *inode, struct file *file, | 371 | static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, |
| 373 | unsigned int cmd, unsigned long arg) | 372 | unsigned long arg) |
| 374 | { | 373 | { |
| 375 | void __user *argp = (void __user *)arg; | 374 | void __user *argp = (void __user *)arg; |
| 376 | int __user *p = argp; | 375 | int __user *p = argp; |
| @@ -383,77 +382,76 @@ static int usb_pcwd_ioctl(struct inode *inode, struct file *file, | |||
| 383 | }; | 382 | }; |
| 384 | 383 | ||
| 385 | switch (cmd) { | 384 | switch (cmd) { |
| 386 | case WDIOC_GETSUPPORT: | 385 | case WDIOC_GETSUPPORT: |
| 387 | return copy_to_user(argp, &ident, | 386 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 388 | sizeof (ident)) ? -EFAULT : 0; | ||
| 389 | 387 | ||
| 390 | case WDIOC_GETSTATUS: | 388 | case WDIOC_GETSTATUS: |
| 391 | case WDIOC_GETBOOTSTATUS: | 389 | case WDIOC_GETBOOTSTATUS: |
| 392 | return put_user(0, p); | 390 | return put_user(0, p); |
| 393 | 391 | ||
| 394 | case WDIOC_GETTEMP: | 392 | case WDIOC_GETTEMP: |
| 395 | { | 393 | { |
| 396 | int temperature; | 394 | int temperature; |
| 397 | 395 | ||
| 398 | if (usb_pcwd_get_temperature(usb_pcwd_device, &temperature)) | 396 | if (usb_pcwd_get_temperature(usb_pcwd_device, &temperature)) |
| 399 | return -EFAULT; | 397 | return -EFAULT; |
| 400 | 398 | ||
| 401 | return put_user(temperature, p); | 399 | return put_user(temperature, p); |
| 402 | } | 400 | } |
| 403 | 401 | ||
| 404 | case WDIOC_KEEPALIVE: | 402 | case WDIOC_SETOPTIONS: |
| 405 | usb_pcwd_keepalive(usb_pcwd_device); | 403 | { |
| 406 | return 0; | 404 | int new_options, retval = -EINVAL; |
| 407 | 405 | ||
| 408 | case WDIOC_SETOPTIONS: | 406 | if (get_user(new_options, p)) |
| 409 | { | 407 | return -EFAULT; |
| 410 | int new_options, retval = -EINVAL; | ||
| 411 | 408 | ||
| 412 | if (get_user (new_options, p)) | 409 | if (new_options & WDIOS_DISABLECARD) { |
| 413 | return -EFAULT; | 410 | usb_pcwd_stop(usb_pcwd_device); |
| 411 | retval = 0; | ||
| 412 | } | ||
| 414 | 413 | ||
| 415 | if (new_options & WDIOS_DISABLECARD) { | 414 | if (new_options & WDIOS_ENABLECARD) { |
| 416 | usb_pcwd_stop(usb_pcwd_device); | 415 | usb_pcwd_start(usb_pcwd_device); |
| 417 | retval = 0; | 416 | retval = 0; |
| 418 | } | 417 | } |
| 419 | 418 | ||
| 420 | if (new_options & WDIOS_ENABLECARD) { | 419 | return retval; |
| 421 | usb_pcwd_start(usb_pcwd_device); | 420 | } |
| 422 | retval = 0; | ||
| 423 | } | ||
| 424 | 421 | ||
| 425 | return retval; | 422 | case WDIOC_KEEPALIVE: |
| 426 | } | 423 | usb_pcwd_keepalive(usb_pcwd_device); |
| 424 | return 0; | ||
| 427 | 425 | ||
| 428 | case WDIOC_SETTIMEOUT: | 426 | case WDIOC_SETTIMEOUT: |
| 429 | { | 427 | { |
| 430 | int new_heartbeat; | 428 | int new_heartbeat; |
| 431 | 429 | ||
| 432 | if (get_user(new_heartbeat, p)) | 430 | if (get_user(new_heartbeat, p)) |
| 433 | return -EFAULT; | 431 | return -EFAULT; |
| 434 | 432 | ||
| 435 | if (usb_pcwd_set_heartbeat(usb_pcwd_device, new_heartbeat)) | 433 | if (usb_pcwd_set_heartbeat(usb_pcwd_device, new_heartbeat)) |
| 436 | return -EINVAL; | 434 | return -EINVAL; |
| 437 | 435 | ||
| 438 | usb_pcwd_keepalive(usb_pcwd_device); | 436 | usb_pcwd_keepalive(usb_pcwd_device); |
| 439 | /* Fall */ | 437 | /* Fall */ |
| 440 | } | 438 | } |
| 441 | 439 | ||
| 442 | case WDIOC_GETTIMEOUT: | 440 | case WDIOC_GETTIMEOUT: |
| 443 | return put_user(heartbeat, p); | 441 | return put_user(heartbeat, p); |
| 444 | 442 | ||
| 445 | case WDIOC_GETTIMELEFT: | 443 | case WDIOC_GETTIMELEFT: |
| 446 | { | 444 | { |
| 447 | int time_left; | 445 | int time_left; |
| 448 | 446 | ||
| 449 | if (usb_pcwd_get_timeleft(usb_pcwd_device, &time_left)) | 447 | if (usb_pcwd_get_timeleft(usb_pcwd_device, &time_left)) |
| 450 | return -EFAULT; | 448 | return -EFAULT; |
| 451 | 449 | ||
| 452 | return put_user(time_left, p); | 450 | return put_user(time_left, p); |
| 453 | } | 451 | } |
| 454 | 452 | ||
| 455 | default: | 453 | default: |
| 456 | return -ENOTTY; | 454 | return -ENOTTY; |
| 457 | } | 455 | } |
| 458 | } | 456 | } |
| 459 | 457 | ||
| @@ -519,10 +517,8 @@ static int usb_pcwd_temperature_release(struct inode *inode, struct file *file) | |||
| 519 | 517 | ||
| 520 | static int usb_pcwd_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 518 | static int usb_pcwd_notify_sys(struct notifier_block *this, unsigned long code, void *unused) |
| 521 | { | 519 | { |
| 522 | if (code==SYS_DOWN || code==SYS_HALT) { | 520 | if (code == SYS_DOWN || code == SYS_HALT) |
| 523 | /* Turn the WDT off */ | 521 | usb_pcwd_stop(usb_pcwd_device); /* Turn the WDT off */ |
| 524 | usb_pcwd_stop(usb_pcwd_device); | ||
| 525 | } | ||
| 526 | 522 | ||
| 527 | return NOTIFY_DONE; | 523 | return NOTIFY_DONE; |
| 528 | } | 524 | } |
| @@ -535,7 +531,7 @@ static const struct file_operations usb_pcwd_fops = { | |||
| 535 | .owner = THIS_MODULE, | 531 | .owner = THIS_MODULE, |
| 536 | .llseek = no_llseek, | 532 | .llseek = no_llseek, |
| 537 | .write = usb_pcwd_write, | 533 | .write = usb_pcwd_write, |
| 538 | .ioctl = usb_pcwd_ioctl, | 534 | .unlocked_ioctl = usb_pcwd_ioctl, |
| 539 | .open = usb_pcwd_open, | 535 | .open = usb_pcwd_open, |
| 540 | .release = usb_pcwd_release, | 536 | .release = usb_pcwd_release, |
| 541 | }; | 537 | }; |
| @@ -567,13 +563,13 @@ static struct notifier_block usb_pcwd_notifier = { | |||
| 567 | /** | 563 | /** |
| 568 | * usb_pcwd_delete | 564 | * usb_pcwd_delete |
| 569 | */ | 565 | */ |
| 570 | static inline void usb_pcwd_delete (struct usb_pcwd_private *usb_pcwd) | 566 | static inline void usb_pcwd_delete(struct usb_pcwd_private *usb_pcwd) |
| 571 | { | 567 | { |
| 572 | usb_free_urb(usb_pcwd->intr_urb); | 568 | usb_free_urb(usb_pcwd->intr_urb); |
| 573 | if (usb_pcwd->intr_buffer != NULL) | 569 | if (usb_pcwd->intr_buffer != NULL) |
| 574 | usb_buffer_free(usb_pcwd->udev, usb_pcwd->intr_size, | 570 | usb_buffer_free(usb_pcwd->udev, usb_pcwd->intr_size, |
| 575 | usb_pcwd->intr_buffer, usb_pcwd->intr_dma); | 571 | usb_pcwd->intr_buffer, usb_pcwd->intr_dma); |
| 576 | kfree (usb_pcwd); | 572 | kfree(usb_pcwd); |
| 577 | } | 573 | } |
| 578 | 574 | ||
| 579 | /** | 575 | /** |
| @@ -626,7 +622,7 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi | |||
| 626 | maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); | 622 | maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); |
| 627 | 623 | ||
| 628 | /* allocate memory for our device and initialize it */ | 624 | /* allocate memory for our device and initialize it */ |
| 629 | usb_pcwd = kzalloc (sizeof(struct usb_pcwd_private), GFP_KERNEL); | 625 | usb_pcwd = kzalloc(sizeof(struct usb_pcwd_private), GFP_KERNEL); |
| 630 | if (usb_pcwd == NULL) { | 626 | if (usb_pcwd == NULL) { |
| 631 | printk(KERN_ERR PFX "Out of memory\n"); | 627 | printk(KERN_ERR PFX "Out of memory\n"); |
| 632 | goto error; | 628 | goto error; |
| @@ -641,7 +637,8 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi | |||
| 641 | usb_pcwd->intr_size = (le16_to_cpu(endpoint->wMaxPacketSize) > 8 ? le16_to_cpu(endpoint->wMaxPacketSize) : 8); | 637 | usb_pcwd->intr_size = (le16_to_cpu(endpoint->wMaxPacketSize) > 8 ? le16_to_cpu(endpoint->wMaxPacketSize) : 8); |
| 642 | 638 | ||
| 643 | /* set up the memory buffer's */ | 639 | /* set up the memory buffer's */ |
| 644 | if (!(usb_pcwd->intr_buffer = usb_buffer_alloc(udev, usb_pcwd->intr_size, GFP_ATOMIC, &usb_pcwd->intr_dma))) { | 640 | usb_pcwd->intr_buffer = usb_buffer_alloc(udev, usb_pcwd->intr_size, GFP_ATOMIC, &usb_pcwd->intr_dma); |
| 641 | if (!usb_pcwd->intr_buffer) { | ||
| 645 | printk(KERN_ERR PFX "Out of memory\n"); | 642 | printk(KERN_ERR PFX "Out of memory\n"); |
| 646 | goto error; | 643 | goto error; |
| 647 | } | 644 | } |
| @@ -675,11 +672,10 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi | |||
| 675 | 672 | ||
| 676 | /* Get the Firmware Version */ | 673 | /* Get the Firmware Version */ |
| 677 | got_fw_rev = usb_pcwd_send_command(usb_pcwd, CMD_GET_FIRMWARE_VERSION, &fw_rev_major, &fw_rev_minor); | 674 | got_fw_rev = usb_pcwd_send_command(usb_pcwd, CMD_GET_FIRMWARE_VERSION, &fw_rev_major, &fw_rev_minor); |
| 678 | if (got_fw_rev) { | 675 | if (got_fw_rev) |
| 679 | sprintf(fw_ver_str, "%u.%02u", fw_rev_major, fw_rev_minor); | 676 | sprintf(fw_ver_str, "%u.%02u", fw_rev_major, fw_rev_minor); |
| 680 | } else { | 677 | else |
| 681 | sprintf(fw_ver_str, "<card no answer>"); | 678 | sprintf(fw_ver_str, "<card no answer>"); |
| 682 | } | ||
| 683 | 679 | ||
| 684 | printk(KERN_INFO PFX "Found card (Firmware: %s) with temp option\n", | 680 | printk(KERN_INFO PFX "Found card (Firmware: %s) with temp option\n", |
| 685 | fw_ver_str); | 681 | fw_ver_str); |
| @@ -725,7 +721,7 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi | |||
| 725 | } | 721 | } |
| 726 | 722 | ||
| 727 | /* we can register the device now, as it is ready */ | 723 | /* we can register the device now, as it is ready */ |
| 728 | usb_set_intfdata (interface, usb_pcwd); | 724 | usb_set_intfdata(interface, usb_pcwd); |
| 729 | 725 | ||
| 730 | printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", | 726 | printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", |
| 731 | heartbeat, nowayout); | 727 | heartbeat, nowayout); |
| @@ -759,8 +755,8 @@ static void usb_pcwd_disconnect(struct usb_interface *interface) | |||
| 759 | /* prevent races with open() */ | 755 | /* prevent races with open() */ |
| 760 | mutex_lock(&disconnect_mutex); | 756 | mutex_lock(&disconnect_mutex); |
| 761 | 757 | ||
| 762 | usb_pcwd = usb_get_intfdata (interface); | 758 | usb_pcwd = usb_get_intfdata(interface); |
| 763 | usb_set_intfdata (interface, NULL); | 759 | usb_set_intfdata(interface, NULL); |
| 764 | 760 | ||
| 765 | mutex_lock(&usb_pcwd->mtx); | 761 | mutex_lock(&usb_pcwd->mtx); |
| 766 | 762 | ||
| @@ -820,5 +816,5 @@ static void __exit usb_pcwd_exit(void) | |||
| 820 | } | 816 | } |
| 821 | 817 | ||
| 822 | 818 | ||
| 823 | module_init (usb_pcwd_init); | 819 | module_init(usb_pcwd_init); |
| 824 | module_exit (usb_pcwd_exit); | 820 | module_exit(usb_pcwd_exit); |
diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index f431a0427eaa..0ed84162437b 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c | |||
| @@ -28,10 +28,9 @@ | |||
| 28 | #include <linux/platform_device.h> | 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/clk.h> | 29 | #include <linux/clk.h> |
| 30 | #include <linux/spinlock.h> | 30 | #include <linux/spinlock.h> |
| 31 | 31 | #include <linux/uaccess.h> | |
| 32 | #include <linux/io.h> | ||
| 32 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 33 | #include <asm/uaccess.h> | ||
| 34 | #include <asm/io.h> | ||
| 35 | 34 | ||
| 36 | #define MODULE_NAME "PNX4008-WDT: " | 35 | #define MODULE_NAME "PNX4008-WDT: " |
| 37 | 36 | ||
| @@ -144,9 +143,8 @@ static int pnx4008_wdt_open(struct inode *inode, struct file *file) | |||
| 144 | return nonseekable_open(inode, file); | 143 | return nonseekable_open(inode, file); |
| 145 | } | 144 | } |
| 146 | 145 | ||
| 147 | static ssize_t | 146 | static ssize_t pnx4008_wdt_write(struct file *file, const char *data, |
| 148 | pnx4008_wdt_write(struct file *file, const char *data, size_t len, | 147 | size_t len, loff_t *ppos) |
| 149 | loff_t * ppos) | ||
| 150 | { | 148 | { |
| 151 | if (len) { | 149 | if (len) { |
| 152 | if (!nowayout) { | 150 | if (!nowayout) { |
| @@ -169,15 +167,14 @@ pnx4008_wdt_write(struct file *file, const char *data, size_t len, | |||
| 169 | return len; | 167 | return len; |
| 170 | } | 168 | } |
| 171 | 169 | ||
| 172 | static struct watchdog_info ident = { | 170 | static const struct watchdog_info ident = { |
| 173 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | | 171 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | |
| 174 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | 172 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
| 175 | .identity = "PNX4008 Watchdog", | 173 | .identity = "PNX4008 Watchdog", |
| 176 | }; | 174 | }; |
| 177 | 175 | ||
| 178 | static int | 176 | static long pnx4008_wdt_ioctl(struct inode *inode, struct file *file, |
| 179 | pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 177 | unsigned int cmd, unsigned long arg) |
| 180 | unsigned long arg) | ||
| 181 | { | 178 | { |
| 182 | int ret = -ENOTTY; | 179 | int ret = -ENOTTY; |
| 183 | int time; | 180 | int time; |
| @@ -196,6 +193,11 @@ pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 196 | ret = put_user(boot_status, (int *)arg); | 193 | ret = put_user(boot_status, (int *)arg); |
| 197 | break; | 194 | break; |
| 198 | 195 | ||
| 196 | case WDIOC_KEEPALIVE: | ||
| 197 | wdt_enable(); | ||
| 198 | ret = 0; | ||
| 199 | break; | ||
| 200 | |||
| 199 | case WDIOC_SETTIMEOUT: | 201 | case WDIOC_SETTIMEOUT: |
| 200 | ret = get_user(time, (int *)arg); | 202 | ret = get_user(time, (int *)arg); |
| 201 | if (ret) | 203 | if (ret) |
| @@ -213,11 +215,6 @@ pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 213 | case WDIOC_GETTIMEOUT: | 215 | case WDIOC_GETTIMEOUT: |
| 214 | ret = put_user(heartbeat, (int *)arg); | 216 | ret = put_user(heartbeat, (int *)arg); |
| 215 | break; | 217 | break; |
| 216 | |||
| 217 | case WDIOC_KEEPALIVE: | ||
| 218 | wdt_enable(); | ||
| 219 | ret = 0; | ||
| 220 | break; | ||
| 221 | } | 218 | } |
| 222 | return ret; | 219 | return ret; |
| 223 | } | 220 | } |
| @@ -238,7 +235,7 @@ static const struct file_operations pnx4008_wdt_fops = { | |||
| 238 | .owner = THIS_MODULE, | 235 | .owner = THIS_MODULE, |
| 239 | .llseek = no_llseek, | 236 | .llseek = no_llseek, |
| 240 | .write = pnx4008_wdt_write, | 237 | .write = pnx4008_wdt_write, |
| 241 | .ioctl = pnx4008_wdt_ioctl, | 238 | .unlocked_ioctl = pnx4008_wdt_ioctl, |
| 242 | .open = pnx4008_wdt_open, | 239 | .open = pnx4008_wdt_open, |
| 243 | .release = pnx4008_wdt_release, | 240 | .release = pnx4008_wdt_release, |
| 244 | }; | 241 | }; |
diff --git a/drivers/watchdog/rm9k_wdt.c b/drivers/watchdog/rm9k_wdt.c index 5c921e471564..f1ae3729a19e 100644 --- a/drivers/watchdog/rm9k_wdt.c +++ b/drivers/watchdog/rm9k_wdt.c | |||
| @@ -29,10 +29,10 @@ | |||
| 29 | #include <linux/notifier.h> | 29 | #include <linux/notifier.h> |
| 30 | #include <linux/miscdevice.h> | 30 | #include <linux/miscdevice.h> |
| 31 | #include <linux/watchdog.h> | 31 | #include <linux/watchdog.h> |
| 32 | #include <asm/io.h> | 32 | #include <linux/io.h> |
| 33 | #include <linux/uaccess.h> | ||
| 33 | #include <asm/atomic.h> | 34 | #include <asm/atomic.h> |
| 34 | #include <asm/processor.h> | 35 | #include <asm/processor.h> |
| 35 | #include <asm/uaccess.h> | ||
| 36 | #include <asm/system.h> | 36 | #include <asm/system.h> |
| 37 | #include <asm/rm9k-ocd.h> | 37 | #include <asm/rm9k-ocd.h> |
| 38 | 38 | ||
| @@ -53,10 +53,12 @@ static void wdt_gpi_stop(void); | |||
| 53 | static void wdt_gpi_set_timeout(unsigned int); | 53 | static void wdt_gpi_set_timeout(unsigned int); |
| 54 | static int wdt_gpi_open(struct inode *, struct file *); | 54 | static int wdt_gpi_open(struct inode *, struct file *); |
| 55 | static int wdt_gpi_release(struct inode *, struct file *); | 55 | static int wdt_gpi_release(struct inode *, struct file *); |
| 56 | static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t, loff_t *); | 56 | static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t, |
| 57 | loff_t *); | ||
| 57 | static long wdt_gpi_ioctl(struct file *, unsigned int, unsigned long); | 58 | static long wdt_gpi_ioctl(struct file *, unsigned int, unsigned long); |
| 58 | static int wdt_gpi_notify(struct notifier_block *, unsigned long, void *); | 59 | static int wdt_gpi_notify(struct notifier_block *, unsigned long, void *); |
| 59 | static const struct resource *wdt_gpi_get_resource(struct platform_device *, const char *, unsigned int); | 60 | static const struct resource *wdt_gpi_get_resource(struct platform_device *, |
| 61 | const char *, unsigned int); | ||
| 60 | static int __init wdt_gpi_probe(struct device *); | 62 | static int __init wdt_gpi_probe(struct device *); |
| 61 | static int __exit wdt_gpi_remove(struct device *); | 63 | static int __exit wdt_gpi_remove(struct device *); |
| 62 | 64 | ||
| @@ -68,7 +70,7 @@ static int locked; | |||
| 68 | 70 | ||
| 69 | 71 | ||
| 70 | /* These are set from device resources */ | 72 | /* These are set from device resources */ |
| 71 | static void __iomem * wd_regs; | 73 | static void __iomem *wd_regs; |
| 72 | static unsigned int wd_irq, wd_ctr; | 74 | static unsigned int wd_irq, wd_ctr; |
| 73 | 75 | ||
| 74 | 76 | ||
| @@ -216,7 +218,8 @@ static int wdt_gpi_release(struct inode *inode, struct file *file) | |||
| 216 | if (expect_close) { | 218 | if (expect_close) { |
| 217 | wdt_gpi_stop(); | 219 | wdt_gpi_stop(); |
| 218 | free_irq(wd_irq, &miscdev); | 220 | free_irq(wd_irq, &miscdev); |
| 219 | printk(KERN_INFO "%s: watchdog stopped\n", wdt_gpi_name); | 221 | printk(KERN_INFO "%s: watchdog stopped\n", |
| 222 | wdt_gpi_name); | ||
| 220 | } else { | 223 | } else { |
| 221 | printk(KERN_CRIT "%s: unexpected close() -" | 224 | printk(KERN_CRIT "%s: unexpected close() -" |
| 222 | " watchdog left running\n", | 225 | " watchdog left running\n", |
| @@ -231,8 +234,8 @@ static int wdt_gpi_release(struct inode *inode, struct file *file) | |||
| 231 | return 0; | 234 | return 0; |
| 232 | } | 235 | } |
| 233 | 236 | ||
| 234 | static ssize_t | 237 | static ssize_t wdt_gpi_write(struct file *f, const char __user *d, size_t s, |
| 235 | wdt_gpi_write(struct file *f, const char __user *d, size_t s, loff_t *o) | 238 | loff_t *o) |
| 236 | { | 239 | { |
| 237 | char val; | 240 | char val; |
| 238 | 241 | ||
| @@ -241,8 +244,7 @@ wdt_gpi_write(struct file *f, const char __user *d, size_t s, loff_t *o) | |||
| 241 | return s ? 1 : 0; | 244 | return s ? 1 : 0; |
| 242 | } | 245 | } |
| 243 | 246 | ||
| 244 | static long | 247 | static long wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
| 245 | wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | ||
| 246 | { | 248 | { |
| 247 | long res = -ENOTTY; | 249 | long res = -ENOTTY; |
| 248 | const long size = _IOC_SIZE(cmd); | 250 | const long size = _IOC_SIZE(cmd); |
| @@ -271,7 +273,8 @@ wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |||
| 271 | case WDIOC_GETSUPPORT: | 273 | case WDIOC_GETSUPPORT: |
| 272 | wdinfo.options = nowayout ? | 274 | wdinfo.options = nowayout ? |
| 273 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING : | 275 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING : |
| 274 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE; | 276 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | |
| 277 | WDIOF_MAGICCLOSE; | ||
| 275 | res = __copy_to_user(argp, &wdinfo, size) ? -EFAULT : size; | 278 | res = __copy_to_user(argp, &wdinfo, size) ? -EFAULT : size; |
| 276 | break; | 279 | break; |
| 277 | 280 | ||
| @@ -322,8 +325,8 @@ wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |||
| 322 | 325 | ||
| 323 | 326 | ||
| 324 | /* Shutdown notifier */ | 327 | /* Shutdown notifier */ |
| 325 | static int | 328 | static int wdt_gpi_notify(struct notifier_block *this, unsigned long code, |
| 326 | wdt_gpi_notify(struct notifier_block *this, unsigned long code, void *unused) | 329 | void *unused) |
| 327 | { | 330 | { |
| 328 | if (code == SYS_DOWN || code == SYS_HALT) | 331 | if (code == SYS_DOWN || code == SYS_HALT) |
| 329 | wdt_gpi_stop(); | 332 | wdt_gpi_stop(); |
| @@ -333,9 +336,8 @@ wdt_gpi_notify(struct notifier_block *this, unsigned long code, void *unused) | |||
| 333 | 336 | ||
| 334 | 337 | ||
| 335 | /* Init & exit procedures */ | 338 | /* Init & exit procedures */ |
| 336 | static const struct resource * | 339 | static const struct resource *wdt_gpi_get_resource(struct platform_device *pdv, |
| 337 | wdt_gpi_get_resource(struct platform_device *pdv, const char *name, | 340 | const char *name, unsigned int type) |
| 338 | unsigned int type) | ||
| 339 | { | 341 | { |
| 340 | char buf[80]; | 342 | char buf[80]; |
| 341 | if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf) | 343 | if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf) |
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index f1fe800658f4..3da2b90d2fe6 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c | |||
| @@ -119,17 +119,6 @@ static void __s3c2410wdt_stop(void) | |||
| 119 | { | 119 | { |
| 120 | unsigned long wtcon; | 120 | unsigned long wtcon; |
| 121 | 121 | ||
| 122 | spin_lock(&wdt_lock); | ||
| 123 | wtcon = readl(wdt_base + S3C2410_WTCON); | ||
| 124 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); | ||
| 125 | writel(wtcon, wdt_base + S3C2410_WTCON); | ||
| 126 | spin_unlock(&wdt_lock); | ||
| 127 | } | ||
| 128 | |||
| 129 | static void __s3c2410wdt_stop(void) | ||
| 130 | { | ||
| 131 | unsigned long wtcon; | ||
| 132 | |||
| 133 | wtcon = readl(wdt_base + S3C2410_WTCON); | 122 | wtcon = readl(wdt_base + S3C2410_WTCON); |
| 134 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); | 123 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
| 135 | writel(wtcon, wdt_base + S3C2410_WTCON); | 124 | writel(wtcon, wdt_base + S3C2410_WTCON); |
| @@ -305,8 +294,6 @@ static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 305 | int new_margin; | 294 | int new_margin; |
| 306 | 295 | ||
| 307 | switch (cmd) { | 296 | switch (cmd) { |
| 308 | default: | ||
| 309 | return -ENOTTY; | ||
| 310 | case WDIOC_GETSUPPORT: | 297 | case WDIOC_GETSUPPORT: |
| 311 | return copy_to_user(argp, &s3c2410_wdt_ident, | 298 | return copy_to_user(argp, &s3c2410_wdt_ident, |
| 312 | sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; | 299 | sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; |
| @@ -325,6 +312,8 @@ static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 325 | return put_user(tmr_margin, p); | 312 | return put_user(tmr_margin, p); |
| 326 | case WDIOC_GETTIMEOUT: | 313 | case WDIOC_GETTIMEOUT: |
| 327 | return put_user(tmr_margin, p); | 314 | return put_user(tmr_margin, p); |
| 315 | default: | ||
| 316 | return -ENOTTY; | ||
| 328 | } | 317 | } |
| 329 | } | 318 | } |
| 330 | 319 | ||
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index 52a533c274fd..31a48437dc3d 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c | |||
| @@ -26,13 +26,14 @@ | |||
| 26 | #include <linux/watchdog.h> | 26 | #include <linux/watchdog.h> |
| 27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
| 28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 29 | #include <linux/uaccess.h> | ||
| 29 | 30 | ||
| 30 | #ifdef CONFIG_ARCH_PXA | 31 | #ifdef CONFIG_ARCH_PXA |
| 31 | #include <mach/pxa-regs.h> | 32 | #include <mach/pxa-regs.h> |
| 32 | #endif | 33 | #endif |
| 33 | 34 | ||
| 35 | #include <mach/reset.h> | ||
| 34 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 35 | #include <asm/uaccess.h> | ||
| 36 | 37 | ||
| 37 | #define OSCR_FREQ CLOCK_TICK_RATE | 38 | #define OSCR_FREQ CLOCK_TICK_RATE |
| 38 | 39 | ||
| @@ -45,7 +46,7 @@ static int boot_status; | |||
| 45 | */ | 46 | */ |
| 46 | static int sa1100dog_open(struct inode *inode, struct file *file) | 47 | static int sa1100dog_open(struct inode *inode, struct file *file) |
| 47 | { | 48 | { |
| 48 | if (test_and_set_bit(1,&sa1100wdt_users)) | 49 | if (test_and_set_bit(1, &sa1100wdt_users)) |
| 49 | return -EBUSY; | 50 | return -EBUSY; |
| 50 | 51 | ||
| 51 | /* Activate SA1100 Watchdog timer */ | 52 | /* Activate SA1100 Watchdog timer */ |
| @@ -66,28 +67,27 @@ static int sa1100dog_open(struct inode *inode, struct file *file) | |||
| 66 | static int sa1100dog_release(struct inode *inode, struct file *file) | 67 | static int sa1100dog_release(struct inode *inode, struct file *file) |
| 67 | { | 68 | { |
| 68 | printk(KERN_CRIT "WATCHDOG: Device closed - timer will not stop\n"); | 69 | printk(KERN_CRIT "WATCHDOG: Device closed - timer will not stop\n"); |
| 69 | |||
| 70 | clear_bit(1, &sa1100wdt_users); | 70 | clear_bit(1, &sa1100wdt_users); |
| 71 | |||
| 72 | return 0; | 71 | return 0; |
| 73 | } | 72 | } |
| 74 | 73 | ||
| 75 | static ssize_t sa1100dog_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) | 74 | static ssize_t sa1100dog_write(struct file *file, const char __user *data, |
| 75 | size_t len, loff_t *ppos) | ||
| 76 | { | 76 | { |
| 77 | if (len) | 77 | if (len) |
| 78 | /* Refresh OSMR3 timer. */ | 78 | /* Refresh OSMR3 timer. */ |
| 79 | OSMR3 = OSCR + pre_margin; | 79 | OSMR3 = OSCR + pre_margin; |
| 80 | |||
| 81 | return len; | 80 | return len; |
| 82 | } | 81 | } |
| 83 | 82 | ||
| 84 | static struct watchdog_info ident = { | 83 | static const struct watchdog_info ident = { |
| 85 | .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | 84 | .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT |
| 85 | | WDIOF_KEEPALIVEPING, | ||
| 86 | .identity = "SA1100/PXA255 Watchdog", | 86 | .identity = "SA1100/PXA255 Watchdog", |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | static int sa1100dog_ioctl(struct inode *inode, struct file *file, | 89 | static long sa1100dog_ioctl(struct file *file, unsigned int cmd, |
| 90 | unsigned int cmd, unsigned long arg) | 90 | unsigned long arg) |
| 91 | { | 91 | { |
| 92 | int ret = -ENOTTY; | 92 | int ret = -ENOTTY; |
| 93 | int time; | 93 | int time; |
| @@ -108,6 +108,11 @@ static int sa1100dog_ioctl(struct inode *inode, struct file *file, | |||
| 108 | ret = put_user(boot_status, p); | 108 | ret = put_user(boot_status, p); |
| 109 | break; | 109 | break; |
| 110 | 110 | ||
| 111 | case WDIOC_KEEPALIVE: | ||
| 112 | OSMR3 = OSCR + pre_margin; | ||
| 113 | ret = 0; | ||
| 114 | break; | ||
| 115 | |||
| 111 | case WDIOC_SETTIMEOUT: | 116 | case WDIOC_SETTIMEOUT: |
| 112 | ret = get_user(time, p); | 117 | ret = get_user(time, p); |
| 113 | if (ret) | 118 | if (ret) |
| @@ -125,27 +130,20 @@ static int sa1100dog_ioctl(struct inode *inode, struct file *file, | |||
| 125 | case WDIOC_GETTIMEOUT: | 130 | case WDIOC_GETTIMEOUT: |
| 126 | ret = put_user(pre_margin / OSCR_FREQ, p); | 131 | ret = put_user(pre_margin / OSCR_FREQ, p); |
| 127 | break; | 132 | break; |
| 128 | |||
| 129 | case WDIOC_KEEPALIVE: | ||
| 130 | OSMR3 = OSCR + pre_margin; | ||
| 131 | ret = 0; | ||
| 132 | break; | ||
| 133 | } | 133 | } |
| 134 | return ret; | 134 | return ret; |
| 135 | } | 135 | } |
| 136 | 136 | ||
| 137 | static const struct file_operations sa1100dog_fops = | 137 | static const struct file_operations sa1100dog_fops = { |
| 138 | { | ||
| 139 | .owner = THIS_MODULE, | 138 | .owner = THIS_MODULE, |
| 140 | .llseek = no_llseek, | 139 | .llseek = no_llseek, |
| 141 | .write = sa1100dog_write, | 140 | .write = sa1100dog_write, |
| 142 | .ioctl = sa1100dog_ioctl, | 141 | .unlocked_ioctl = sa1100dog_ioctl, |
| 143 | .open = sa1100dog_open, | 142 | .open = sa1100dog_open, |
| 144 | .release = sa1100dog_release, | 143 | .release = sa1100dog_release, |
| 145 | }; | 144 | }; |
| 146 | 145 | ||
| 147 | static struct miscdevice sa1100dog_miscdev = | 146 | static struct miscdevice sa1100dog_miscdev = { |
| 148 | { | ||
| 149 | .minor = WATCHDOG_MINOR, | 147 | .minor = WATCHDOG_MINOR, |
| 150 | .name = "watchdog", | 148 | .name = "watchdog", |
| 151 | .fops = &sa1100dog_fops, | 149 | .fops = &sa1100dog_fops, |
| @@ -162,13 +160,15 @@ static int __init sa1100dog_init(void) | |||
| 162 | * we suspend, RCSR will be cleared, and the watchdog | 160 | * we suspend, RCSR will be cleared, and the watchdog |
| 163 | * reset reason will be lost. | 161 | * reset reason will be lost. |
| 164 | */ | 162 | */ |
| 165 | boot_status = (RCSR & RCSR_WDR) ? WDIOF_CARDRESET : 0; | 163 | boot_status = (reset_status & RESET_STATUS_WATCHDOG) ? |
| 164 | WDIOF_CARDRESET : 0; | ||
| 166 | pre_margin = OSCR_FREQ * margin; | 165 | pre_margin = OSCR_FREQ * margin; |
| 167 | 166 | ||
| 168 | ret = misc_register(&sa1100dog_miscdev); | 167 | ret = misc_register(&sa1100dog_miscdev); |
| 169 | if (ret == 0) | 168 | if (ret == 0) |
| 170 | printk("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n", | 169 | printk(KERN_INFO |
| 171 | margin); | 170 | "SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n", |
| 171 | margin); | ||
| 172 | return ret; | 172 | return ret; |
| 173 | } | 173 | } |
| 174 | 174 | ||
diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index b94431433695..27e526a07c9a 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c | |||
| @@ -57,6 +57,7 @@ | |||
| 57 | #include <asm/sibyte/sb1250_int.h> | 57 | #include <asm/sibyte/sb1250_int.h> |
| 58 | #include <asm/sibyte/sb1250_scd.h> | 58 | #include <asm/sibyte/sb1250_scd.h> |
| 59 | 59 | ||
| 60 | static DEFINE_SPINLOCK(sbwd_lock); | ||
| 60 | 61 | ||
| 61 | /* | 62 | /* |
| 62 | * set the initial count value of a timer | 63 | * set the initial count value of a timer |
| @@ -65,8 +66,10 @@ | |||
| 65 | */ | 66 | */ |
| 66 | void sbwdog_set(char __iomem *wdog, unsigned long t) | 67 | void sbwdog_set(char __iomem *wdog, unsigned long t) |
| 67 | { | 68 | { |
| 69 | spin_lock(&sbwd_lock); | ||
| 68 | __raw_writeb(0, wdog - 0x10); | 70 | __raw_writeb(0, wdog - 0x10); |
| 69 | __raw_writeq(t & 0x7fffffUL, wdog); | 71 | __raw_writeq(t & 0x7fffffUL, wdog); |
| 72 | spin_unlock(&sbwd_lock); | ||
| 70 | } | 73 | } |
| 71 | 74 | ||
| 72 | /* | 75 | /* |
| @@ -77,7 +80,9 @@ void sbwdog_set(char __iomem *wdog, unsigned long t) | |||
| 77 | */ | 80 | */ |
| 78 | void sbwdog_pet(char __iomem *wdog) | 81 | void sbwdog_pet(char __iomem *wdog) |
| 79 | { | 82 | { |
| 83 | spin_lock(&sbwd_lock); | ||
| 80 | __raw_writeb(__raw_readb(wdog) | 1, wdog); | 84 | __raw_writeb(__raw_readb(wdog) | 1, wdog); |
| 85 | spin_unlock(&sbwd_lock); | ||
| 81 | } | 86 | } |
| 82 | 87 | ||
| 83 | static unsigned long sbwdog_gate; /* keeps it to one thread only */ | 88 | static unsigned long sbwdog_gate; /* keeps it to one thread only */ |
| @@ -86,8 +91,9 @@ static char __iomem *user_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_1)); | |||
| 86 | static unsigned long timeout = 0x7fffffUL; /* useconds: 8.3ish secs. */ | 91 | static unsigned long timeout = 0x7fffffUL; /* useconds: 8.3ish secs. */ |
| 87 | static int expect_close; | 92 | static int expect_close; |
| 88 | 93 | ||
| 89 | static struct watchdog_info ident = { | 94 | static const struct watchdog_info ident = { |
| 90 | .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | 95 | .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | |
| 96 | WDIOF_KEEPALIVEPING, | ||
| 91 | .identity = "SiByte Watchdog", | 97 | .identity = "SiByte Watchdog", |
| 92 | }; | 98 | }; |
| 93 | 99 | ||
| @@ -97,9 +103,8 @@ static struct watchdog_info ident = { | |||
| 97 | static int sbwdog_open(struct inode *inode, struct file *file) | 103 | static int sbwdog_open(struct inode *inode, struct file *file) |
| 98 | { | 104 | { |
| 99 | nonseekable_open(inode, file); | 105 | nonseekable_open(inode, file); |
| 100 | if (test_and_set_bit(0, &sbwdog_gate)) { | 106 | if (test_and_set_bit(0, &sbwdog_gate)) |
| 101 | return -EBUSY; | 107 | return -EBUSY; |
| 102 | } | ||
| 103 | __module_get(THIS_MODULE); | 108 | __module_get(THIS_MODULE); |
| 104 | 109 | ||
| 105 | /* | 110 | /* |
| @@ -120,8 +125,9 @@ static int sbwdog_release(struct inode *inode, struct file *file) | |||
| 120 | __raw_writeb(0, user_dog); | 125 | __raw_writeb(0, user_dog); |
| 121 | module_put(THIS_MODULE); | 126 | module_put(THIS_MODULE); |
| 122 | } else { | 127 | } else { |
| 123 | printk(KERN_CRIT "%s: Unexpected close, not stopping watchdog!\n", | 128 | printk(KERN_CRIT |
| 124 | ident.identity); | 129 | "%s: Unexpected close, not stopping watchdog!\n", |
| 130 | ident.identity); | ||
| 125 | sbwdog_pet(user_dog); | 131 | sbwdog_pet(user_dog); |
| 126 | } | 132 | } |
| 127 | clear_bit(0, &sbwdog_gate); | 133 | clear_bit(0, &sbwdog_gate); |
| @@ -147,12 +153,10 @@ static ssize_t sbwdog_write(struct file *file, const char __user *data, | |||
| 147 | for (i = 0; i != len; i++) { | 153 | for (i = 0; i != len; i++) { |
| 148 | char c; | 154 | char c; |
| 149 | 155 | ||
| 150 | if (get_user(c, data + i)) { | 156 | if (get_user(c, data + i)) |
| 151 | return -EFAULT; | 157 | return -EFAULT; |
| 152 | } | 158 | if (c == 'V') |
| 153 | if (c == 'V') { | ||
| 154 | expect_close = 42; | 159 | expect_close = 42; |
| 155 | } | ||
| 156 | } | 160 | } |
| 157 | sbwdog_pet(user_dog); | 161 | sbwdog_pet(user_dog); |
| 158 | } | 162 | } |
| @@ -160,8 +164,8 @@ static ssize_t sbwdog_write(struct file *file, const char __user *data, | |||
| 160 | return len; | 164 | return len; |
| 161 | } | 165 | } |
| 162 | 166 | ||
| 163 | static int sbwdog_ioctl(struct inode *inode, struct file *file, | 167 | static long sbwdog_ioctl(struct file *file, unsigned int cmd, |
| 164 | unsigned int cmd, unsigned long arg) | 168 | unsigned long arg) |
| 165 | { | 169 | { |
| 166 | int ret = -ENOTTY; | 170 | int ret = -ENOTTY; |
| 167 | unsigned long time; | 171 | unsigned long time; |
| @@ -178,11 +182,15 @@ static int sbwdog_ioctl(struct inode *inode, struct file *file, | |||
| 178 | ret = put_user(0, p); | 182 | ret = put_user(0, p); |
| 179 | break; | 183 | break; |
| 180 | 184 | ||
| 185 | case WDIOC_KEEPALIVE: | ||
| 186 | sbwdog_pet(user_dog); | ||
| 187 | ret = 0; | ||
| 188 | break; | ||
| 189 | |||
| 181 | case WDIOC_SETTIMEOUT: | 190 | case WDIOC_SETTIMEOUT: |
| 182 | ret = get_user(time, p); | 191 | ret = get_user(time, p); |
| 183 | if (ret) { | 192 | if (ret) |
| 184 | break; | 193 | break; |
| 185 | } | ||
| 186 | 194 | ||
| 187 | time *= 1000000; | 195 | time *= 1000000; |
| 188 | if (time > 0x7fffffUL) { | 196 | if (time > 0x7fffffUL) { |
| @@ -200,11 +208,6 @@ static int sbwdog_ioctl(struct inode *inode, struct file *file, | |||
| 200 | */ | 208 | */ |
| 201 | ret = put_user(__raw_readq(user_dog - 8) / 1000000, p); | 209 | ret = put_user(__raw_readq(user_dog - 8) / 1000000, p); |
| 202 | break; | 210 | break; |
| 203 | |||
| 204 | case WDIOC_KEEPALIVE: | ||
| 205 | sbwdog_pet(user_dog); | ||
| 206 | ret = 0; | ||
| 207 | break; | ||
| 208 | } | 211 | } |
| 209 | return ret; | 212 | return ret; |
| 210 | } | 213 | } |
| @@ -212,8 +215,8 @@ static int sbwdog_ioctl(struct inode *inode, struct file *file, | |||
| 212 | /* | 215 | /* |
| 213 | * Notifier for system down | 216 | * Notifier for system down |
| 214 | */ | 217 | */ |
| 215 | static int | 218 | static int sbwdog_notify_sys(struct notifier_block *this, unsigned long code, |
| 216 | sbwdog_notify_sys(struct notifier_block *this, unsigned long code, void *erf) | 219 | void *erf) |
| 217 | { | 220 | { |
| 218 | if (code == SYS_DOWN || code == SYS_HALT) { | 221 | if (code == SYS_DOWN || code == SYS_HALT) { |
| 219 | /* | 222 | /* |
| @@ -226,18 +229,16 @@ sbwdog_notify_sys(struct notifier_block *this, unsigned long code, void *erf) | |||
| 226 | return NOTIFY_DONE; | 229 | return NOTIFY_DONE; |
| 227 | } | 230 | } |
| 228 | 231 | ||
| 229 | static const struct file_operations sbwdog_fops = | 232 | static const struct file_operations sbwdog_fops = { |
| 230 | { | ||
| 231 | .owner = THIS_MODULE, | 233 | .owner = THIS_MODULE, |
| 232 | .llseek = no_llseek, | 234 | .llseek = no_llseek, |
| 233 | .write = sbwdog_write, | 235 | .write = sbwdog_write, |
| 234 | .ioctl = sbwdog_ioctl, | 236 | .unlocked_ioctl = sbwdog_ioctl, |
| 235 | .open = sbwdog_open, | 237 | .open = sbwdog_open, |
| 236 | .release = sbwdog_release, | 238 | .release = sbwdog_release, |
| 237 | }; | 239 | }; |
| 238 | 240 | ||
| 239 | static struct miscdevice sbwdog_miscdev = | 241 | static struct miscdevice sbwdog_miscdev = { |
| 240 | { | ||
| 241 | .minor = WATCHDOG_MINOR, | 242 | .minor = WATCHDOG_MINOR, |
| 242 | .name = "watchdog", | 243 | .name = "watchdog", |
| 243 | .fops = &sbwdog_fops, | 244 | .fops = &sbwdog_fops, |
| @@ -267,13 +268,12 @@ irqreturn_t sbwdog_interrupt(int irq, void *addr) | |||
| 267 | /* | 268 | /* |
| 268 | * if it's the second watchdog timer, it's for those users | 269 | * if it's the second watchdog timer, it's for those users |
| 269 | */ | 270 | */ |
| 270 | if (wd_cfg_reg == user_dog) { | 271 | if (wd_cfg_reg == user_dog) |
| 271 | printk(KERN_CRIT | 272 | printk(KERN_CRIT |
| 272 | "%s in danger of initiating system reset in %ld.%01ld seconds\n", | 273 | "%s in danger of initiating system reset in %ld.%01ld seconds\n", |
| 273 | ident.identity, wd_init / 1000000, (wd_init / 100000) % 10); | 274 | ident.identity, wd_init / 1000000, (wd_init / 100000) % 10); |
| 274 | } else { | 275 | else |
| 275 | cfg |= 1; | 276 | cfg |= 1; |
| 276 | } | ||
| 277 | 277 | ||
| 278 | __raw_writeb(cfg, wd_cfg_reg); | 278 | __raw_writeb(cfg, wd_cfg_reg); |
| 279 | 279 | ||
| @@ -289,28 +289,31 @@ static int __init sbwdog_init(void) | |||
| 289 | */ | 289 | */ |
| 290 | ret = register_reboot_notifier(&sbwdog_notifier); | 290 | ret = register_reboot_notifier(&sbwdog_notifier); |
| 291 | if (ret) { | 291 | if (ret) { |
| 292 | printk (KERN_ERR "%s: cannot register reboot notifier (err=%d)\n", | 292 | printk(KERN_ERR |
| 293 | ident.identity, ret); | 293 | "%s: cannot register reboot notifier (err=%d)\n", |
| 294 | ident.identity, ret); | ||
| 294 | return ret; | 295 | return ret; |
| 295 | } | 296 | } |
| 296 | 297 | ||
| 297 | /* | 298 | /* |
| 298 | * get the resources | 299 | * get the resources |
| 299 | */ | 300 | */ |
| 300 | ret = misc_register(&sbwdog_miscdev); | ||
| 301 | if (ret == 0) { | ||
| 302 | printk(KERN_INFO "%s: timeout is %ld.%ld secs\n", ident.identity, | ||
| 303 | timeout / 1000000, (timeout / 100000) % 10); | ||
| 304 | } | ||
| 305 | 301 | ||
| 306 | ret = request_irq(1, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, | 302 | ret = request_irq(1, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, |
| 307 | ident.identity, (void *)user_dog); | 303 | ident.identity, (void *)user_dog); |
| 308 | if (ret) { | 304 | if (ret) { |
| 309 | printk(KERN_ERR "%s: failed to request irq 1 - %d\n", ident.identity, | 305 | printk(KERN_ERR "%s: failed to request irq 1 - %d\n", |
| 310 | ret); | 306 | ident.identity, ret); |
| 311 | misc_deregister(&sbwdog_miscdev); | 307 | return ret; |
| 312 | } | 308 | } |
| 313 | 309 | ||
| 310 | ret = misc_register(&sbwdog_miscdev); | ||
| 311 | if (ret == 0) { | ||
| 312 | printk(KERN_INFO "%s: timeout is %ld.%ld secs\n", | ||
| 313 | ident.identity, | ||
| 314 | timeout / 1000000, (timeout / 100000) % 10); | ||
| 315 | } else | ||
| 316 | free_irq(1, (void *)user_dog); | ||
| 314 | return ret; | 317 | return ret; |
| 315 | } | 318 | } |
| 316 | 319 | ||
| @@ -327,7 +330,7 @@ MODULE_DESCRIPTION("SiByte Watchdog"); | |||
| 327 | 330 | ||
| 328 | module_param(timeout, ulong, 0); | 331 | module_param(timeout, ulong, 0); |
| 329 | MODULE_PARM_DESC(timeout, | 332 | MODULE_PARM_DESC(timeout, |
| 330 | "Watchdog timeout in microseconds (max/default 8388607 or 8.3ish secs)"); | 333 | "Watchdog timeout in microseconds (max/default 8388607 or 8.3ish secs)"); |
| 331 | 334 | ||
| 332 | MODULE_LICENSE("GPL"); | 335 | MODULE_LICENSE("GPL"); |
| 333 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | 336 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
| @@ -336,16 +339,15 @@ MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |||
| 336 | * example code that can be put in a platform code area to utilize the | 339 | * example code that can be put in a platform code area to utilize the |
| 337 | * first watchdog timer for the kernels own purpose. | 340 | * first watchdog timer for the kernels own purpose. |
| 338 | 341 | ||
| 339 | void | 342 | void platform_wd_setup(void) |
| 340 | platform_wd_setup(void) | ||
| 341 | { | 343 | { |
| 342 | int ret; | 344 | int ret; |
| 343 | 345 | ||
| 344 | ret = request_irq(0, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, | 346 | ret = request_irq(1, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, |
| 345 | "Kernel Watchdog", IOADDR(A_SCD_WDOG_CFG_0)); | 347 | "Kernel Watchdog", IOADDR(A_SCD_WDOG_CFG_0)); |
| 346 | if (ret) { | 348 | if (ret) { |
| 347 | printk(KERN_CRIT "Watchdog IRQ zero(0) failed to be requested - %d\n", | 349 | printk(KERN_CRIT |
| 348 | ret); | 350 | "Watchdog IRQ zero(0) failed to be requested - %d\n", ret); |
| 349 | } | 351 | } |
| 350 | } | 352 | } |
| 351 | 353 | ||
diff --git a/drivers/watchdog/sbc60xxwdt.c b/drivers/watchdog/sbc60xxwdt.c index ef76f01625e7..3266daaaecf8 100644 --- a/drivers/watchdog/sbc60xxwdt.c +++ b/drivers/watchdog/sbc60xxwdt.c | |||
| @@ -16,19 +16,23 @@ | |||
| 16 | * | 16 | * |
| 17 | * 12/4 - 2000 [Initial revision] | 17 | * 12/4 - 2000 [Initial revision] |
| 18 | * 25/4 - 2000 Added /dev/watchdog support | 18 | * 25/4 - 2000 Added /dev/watchdog support |
| 19 | * 09/5 - 2001 [smj@oro.net] fixed fop_write to "return 1" on success | 19 | * 09/5 - 2001 [smj@oro.net] fixed fop_write to "return 1" |
| 20 | * on success | ||
| 20 | * 12/4 - 2002 [rob@osinvestor.com] eliminate fop_read | 21 | * 12/4 - 2002 [rob@osinvestor.com] eliminate fop_read |
| 21 | * fix possible wdt_is_open race | 22 | * fix possible wdt_is_open race |
| 22 | * add CONFIG_WATCHDOG_NOWAYOUT support | 23 | * add CONFIG_WATCHDOG_NOWAYOUT support |
| 23 | * remove lock_kernel/unlock_kernel pairs | 24 | * remove lock_kernel/unlock_kernel pairs |
| 24 | * added KERN_* to printk's | 25 | * added KERN_* to printk's |
| 25 | * got rid of extraneous comments | 26 | * got rid of extraneous comments |
| 26 | * changed watchdog_info to correctly reflect what the driver offers | 27 | * changed watchdog_info to correctly reflect what |
| 27 | * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, WDIOC_SETTIMEOUT, | 28 | * the driver offers |
| 28 | * WDIOC_GETTIMEOUT, and WDIOC_SETOPTIONS ioctls | 29 | * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, |
| 30 | * WDIOC_SETTIMEOUT, WDIOC_GETTIMEOUT, and | ||
| 31 | * WDIOC_SETOPTIONS ioctls | ||
| 29 | * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces | 32 | * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces |
| 30 | * use module_param | 33 | * use module_param |
| 31 | * made timeout (the emulated heartbeat) a module_param | 34 | * made timeout (the emulated heartbeat) a |
| 35 | * module_param | ||
| 32 | * made the keepalive ping an internal subroutine | 36 | * made the keepalive ping an internal subroutine |
| 33 | * made wdt_stop and wdt_start module params | 37 | * made wdt_stop and wdt_start module params |
| 34 | * added extra printk's for startup problems | 38 | * added extra printk's for startup problems |
| @@ -56,9 +60,9 @@ | |||
| 56 | #include <linux/notifier.h> | 60 | #include <linux/notifier.h> |
| 57 | #include <linux/reboot.h> | 61 | #include <linux/reboot.h> |
| 58 | #include <linux/init.h> | 62 | #include <linux/init.h> |
| 63 | #include <linux/io.h> | ||
| 64 | #include <linux/uaccess.h> | ||
| 59 | 65 | ||
| 60 | #include <asm/io.h> | ||
| 61 | #include <asm/uaccess.h> | ||
| 62 | #include <asm/system.h> | 66 | #include <asm/system.h> |
| 63 | 67 | ||
| 64 | #define OUR_NAME "sbc60xxwdt" | 68 | #define OUR_NAME "sbc60xxwdt" |
| @@ -94,13 +98,18 @@ MODULE_PARM_DESC(wdt_start, "SBC60xx WDT 'start' io port (default 0x443)"); | |||
| 94 | */ | 98 | */ |
| 95 | 99 | ||
| 96 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ | 100 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ |
| 97 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ | 101 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds, multiplied by HZ to |
| 102 | get seconds to wait for a ping */ | ||
| 98 | module_param(timeout, int, 0); | 103 | module_param(timeout, int, 0); |
| 99 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 104 | MODULE_PARM_DESC(timeout, |
| 105 | "Watchdog timeout in seconds. (1<=timeout<=3600, default=" | ||
| 106 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 100 | 107 | ||
| 101 | static int nowayout = WATCHDOG_NOWAYOUT; | 108 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 102 | module_param(nowayout, int, 0); | 109 | module_param(nowayout, int, 0); |
| 103 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 110 | MODULE_PARM_DESC(nowayout, |
| 111 | "Watchdog cannot be stopped once started (default=" | ||
| 112 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 104 | 113 | ||
| 105 | static void wdt_timer_ping(unsigned long); | 114 | static void wdt_timer_ping(unsigned long); |
| 106 | static DEFINE_TIMER(timer, wdt_timer_ping, 0, 0); | 115 | static DEFINE_TIMER(timer, wdt_timer_ping, 0, 0); |
| @@ -117,15 +126,14 @@ static void wdt_timer_ping(unsigned long data) | |||
| 117 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL | 126 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL |
| 118 | * we agree to ping the WDT | 127 | * we agree to ping the WDT |
| 119 | */ | 128 | */ |
| 120 | if(time_before(jiffies, next_heartbeat)) | 129 | if (time_before(jiffies, next_heartbeat)) { |
| 121 | { | ||
| 122 | /* Ping the WDT by reading from wdt_start */ | 130 | /* Ping the WDT by reading from wdt_start */ |
| 123 | inb_p(wdt_start); | 131 | inb_p(wdt_start); |
| 124 | /* Re-set the timer interval */ | 132 | /* Re-set the timer interval */ |
| 125 | mod_timer(&timer, jiffies + WDT_INTERVAL); | 133 | mod_timer(&timer, jiffies + WDT_INTERVAL); |
| 126 | } else { | 134 | } else |
| 127 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); | 135 | printk(KERN_WARNING PFX |
| 128 | } | 136 | "Heartbeat lost! Will not ping the watchdog\n"); |
| 129 | } | 137 | } |
| 130 | 138 | ||
| 131 | /* | 139 | /* |
| @@ -159,40 +167,40 @@ static void wdt_keepalive(void) | |||
| 159 | * /dev/watchdog handling | 167 | * /dev/watchdog handling |
| 160 | */ | 168 | */ |
| 161 | 169 | ||
| 162 | static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) | 170 | static ssize_t fop_write(struct file *file, const char __user *buf, |
| 171 | size_t count, loff_t *ppos) | ||
| 163 | { | 172 | { |
| 164 | /* See if we got the magic character 'V' and reload the timer */ | 173 | /* See if we got the magic character 'V' and reload the timer */ |
| 165 | if(count) | 174 | if (count) { |
| 166 | { | 175 | if (!nowayout) { |
| 167 | if (!nowayout) | ||
| 168 | { | ||
| 169 | size_t ofs; | 176 | size_t ofs; |
| 170 | 177 | ||
| 171 | /* note: just in case someone wrote the magic character | 178 | /* note: just in case someone wrote the |
| 172 | * five months ago... */ | 179 | magic character five months ago... */ |
| 173 | wdt_expect_close = 0; | 180 | wdt_expect_close = 0; |
| 174 | 181 | ||
| 175 | /* scan to see whether or not we got the magic character */ | 182 | /* scan to see whether or not we got the |
| 176 | for(ofs = 0; ofs != count; ofs++) | 183 | magic character */ |
| 177 | { | 184 | for (ofs = 0; ofs != count; ofs++) { |
| 178 | char c; | 185 | char c; |
| 179 | if(get_user(c, buf+ofs)) | 186 | if (get_user(c, buf + ofs)) |
| 180 | return -EFAULT; | 187 | return -EFAULT; |
| 181 | if(c == 'V') | 188 | if (c == 'V') |
| 182 | wdt_expect_close = 42; | 189 | wdt_expect_close = 42; |
| 183 | } | 190 | } |
| 184 | } | 191 | } |
| 185 | 192 | ||
| 186 | /* Well, anyhow someone wrote to us, we should return that favour */ | 193 | /* Well, anyhow someone wrote to us, we should |
| 194 | return that favour */ | ||
| 187 | wdt_keepalive(); | 195 | wdt_keepalive(); |
| 188 | } | 196 | } |
| 189 | return count; | 197 | return count; |
| 190 | } | 198 | } |
| 191 | 199 | ||
| 192 | static int fop_open(struct inode * inode, struct file * file) | 200 | static int fop_open(struct inode *inode, struct file *file) |
| 193 | { | 201 | { |
| 194 | /* Just in case we're already talking to someone... */ | 202 | /* Just in case we're already talking to someone... */ |
| 195 | if(test_and_set_bit(0, &wdt_is_open)) | 203 | if (test_and_set_bit(0, &wdt_is_open)) |
| 196 | return -EBUSY; | 204 | return -EBUSY; |
| 197 | 205 | ||
| 198 | if (nowayout) | 206 | if (nowayout) |
| @@ -203,78 +211,72 @@ static int fop_open(struct inode * inode, struct file * file) | |||
| 203 | return nonseekable_open(inode, file); | 211 | return nonseekable_open(inode, file); |
| 204 | } | 212 | } |
| 205 | 213 | ||
| 206 | static int fop_close(struct inode * inode, struct file * file) | 214 | static int fop_close(struct inode *inode, struct file *file) |
| 207 | { | 215 | { |
| 208 | if(wdt_expect_close == 42) | 216 | if (wdt_expect_close == 42) |
| 209 | wdt_turnoff(); | 217 | wdt_turnoff(); |
| 210 | else { | 218 | else { |
| 211 | del_timer(&timer); | 219 | del_timer(&timer); |
| 212 | printk(KERN_CRIT PFX "device file closed unexpectedly. Will not stop the WDT!\n"); | 220 | printk(KERN_CRIT PFX |
| 221 | "device file closed unexpectedly. Will not stop the WDT!\n"); | ||
| 213 | } | 222 | } |
| 214 | clear_bit(0, &wdt_is_open); | 223 | clear_bit(0, &wdt_is_open); |
| 215 | wdt_expect_close = 0; | 224 | wdt_expect_close = 0; |
| 216 | return 0; | 225 | return 0; |
| 217 | } | 226 | } |
| 218 | 227 | ||
| 219 | static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 228 | static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 220 | unsigned long arg) | ||
| 221 | { | 229 | { |
| 222 | void __user *argp = (void __user *)arg; | 230 | void __user *argp = (void __user *)arg; |
| 223 | int __user *p = argp; | 231 | int __user *p = argp; |
| 224 | static struct watchdog_info ident= | 232 | static const struct watchdog_info ident = { |
| 225 | { | 233 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
| 226 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 234 | WDIOF_MAGICCLOSE, |
| 227 | .firmware_version = 1, | 235 | .firmware_version = 1, |
| 228 | .identity = "SBC60xx", | 236 | .identity = "SBC60xx", |
| 229 | }; | 237 | }; |
| 230 | 238 | ||
| 231 | switch(cmd) | 239 | switch (cmd) { |
| 240 | case WDIOC_GETSUPPORT: | ||
| 241 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 242 | case WDIOC_GETSTATUS: | ||
| 243 | case WDIOC_GETBOOTSTATUS: | ||
| 244 | return put_user(0, p); | ||
| 245 | case WDIOC_SETOPTIONS: | ||
| 232 | { | 246 | { |
| 233 | default: | 247 | int new_options, retval = -EINVAL; |
| 234 | return -ENOTTY; | 248 | if (get_user(new_options, p)) |
| 235 | case WDIOC_GETSUPPORT: | 249 | return -EFAULT; |
| 236 | return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; | 250 | if (new_options & WDIOS_DISABLECARD) { |
| 237 | case WDIOC_GETSTATUS: | 251 | wdt_turnoff(); |
| 238 | case WDIOC_GETBOOTSTATUS: | 252 | retval = 0; |
| 239 | return put_user(0, p); | ||
| 240 | case WDIOC_KEEPALIVE: | ||
| 241 | wdt_keepalive(); | ||
| 242 | return 0; | ||
| 243 | case WDIOC_SETOPTIONS: | ||
| 244 | { | ||
| 245 | int new_options, retval = -EINVAL; | ||
| 246 | |||
| 247 | if(get_user(new_options, p)) | ||
| 248 | return -EFAULT; | ||
| 249 | |||
| 250 | if(new_options & WDIOS_DISABLECARD) { | ||
| 251 | wdt_turnoff(); | ||
| 252 | retval = 0; | ||
| 253 | } | ||
| 254 | |||
| 255 | if(new_options & WDIOS_ENABLECARD) { | ||
| 256 | wdt_startup(); | ||
| 257 | retval = 0; | ||
| 258 | } | ||
| 259 | |||
| 260 | return retval; | ||
| 261 | } | 253 | } |
| 262 | case WDIOC_SETTIMEOUT: | 254 | if (new_options & WDIOS_ENABLECARD) { |
| 263 | { | 255 | wdt_startup(); |
| 264 | int new_timeout; | 256 | retval = 0; |
| 265 | |||
| 266 | if(get_user(new_timeout, p)) | ||
| 267 | return -EFAULT; | ||
| 268 | |||
| 269 | if(new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */ | ||
| 270 | return -EINVAL; | ||
| 271 | |||
| 272 | timeout = new_timeout; | ||
| 273 | wdt_keepalive(); | ||
| 274 | /* Fall through */ | ||
| 275 | } | 257 | } |
| 276 | case WDIOC_GETTIMEOUT: | 258 | return retval; |
| 277 | return put_user(timeout, p); | 259 | } |
| 260 | case WDIOC_KEEPALIVE: | ||
| 261 | wdt_keepalive(); | ||
| 262 | return 0; | ||
| 263 | case WDIOC_SETTIMEOUT: | ||
| 264 | { | ||
| 265 | int new_timeout; | ||
| 266 | if (get_user(new_timeout, p)) | ||
| 267 | return -EFAULT; | ||
| 268 | /* arbitrary upper limit */ | ||
| 269 | if (new_timeout < 1 || new_timeout > 3600) | ||
| 270 | return -EINVAL; | ||
| 271 | |||
| 272 | timeout = new_timeout; | ||
| 273 | wdt_keepalive(); | ||
| 274 | /* Fall through */ | ||
| 275 | } | ||
| 276 | case WDIOC_GETTIMEOUT: | ||
| 277 | return put_user(timeout, p); | ||
| 278 | default: | ||
| 279 | return -ENOTTY; | ||
| 278 | } | 280 | } |
| 279 | } | 281 | } |
| 280 | 282 | ||
| @@ -284,7 +286,7 @@ static const struct file_operations wdt_fops = { | |||
| 284 | .write = fop_write, | 286 | .write = fop_write, |
| 285 | .open = fop_open, | 287 | .open = fop_open, |
| 286 | .release = fop_close, | 288 | .release = fop_close, |
| 287 | .ioctl = fop_ioctl, | 289 | .unlocked_ioctl = fop_ioctl, |
| 288 | }; | 290 | }; |
| 289 | 291 | ||
| 290 | static struct miscdevice wdt_miscdev = { | 292 | static struct miscdevice wdt_miscdev = { |
| @@ -300,7 +302,7 @@ static struct miscdevice wdt_miscdev = { | |||
| 300 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | 302 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 301 | void *unused) | 303 | void *unused) |
| 302 | { | 304 | { |
| 303 | if(code==SYS_DOWN || code==SYS_HALT) | 305 | if (code == SYS_DOWN || code == SYS_HALT) |
| 304 | wdt_turnoff(); | 306 | wdt_turnoff(); |
| 305 | return NOTIFY_DONE; | 307 | return NOTIFY_DONE; |
| 306 | } | 308 | } |
| @@ -310,8 +312,7 @@ static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |||
| 310 | * turn the timebomb registers off. | 312 | * turn the timebomb registers off. |
| 311 | */ | 313 | */ |
| 312 | 314 | ||
| 313 | static struct notifier_block wdt_notifier= | 315 | static struct notifier_block wdt_notifier = { |
| 314 | { | ||
| 315 | .notifier_call = wdt_notify_sys, | 316 | .notifier_call = wdt_notify_sys, |
| 316 | }; | 317 | }; |
| 317 | 318 | ||
| @@ -324,23 +325,22 @@ static void __exit sbc60xxwdt_unload(void) | |||
| 324 | 325 | ||
| 325 | unregister_reboot_notifier(&wdt_notifier); | 326 | unregister_reboot_notifier(&wdt_notifier); |
| 326 | if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) | 327 | if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) |
| 327 | release_region(wdt_stop,1); | 328 | release_region(wdt_stop, 1); |
| 328 | release_region(wdt_start,1); | 329 | release_region(wdt_start, 1); |
| 329 | } | 330 | } |
| 330 | 331 | ||
| 331 | static int __init sbc60xxwdt_init(void) | 332 | static int __init sbc60xxwdt_init(void) |
| 332 | { | 333 | { |
| 333 | int rc = -EBUSY; | 334 | int rc = -EBUSY; |
| 334 | 335 | ||
| 335 | if(timeout < 1 || timeout > 3600) /* arbitrary upper limit */ | 336 | if (timeout < 1 || timeout > 3600) { /* arbitrary upper limit */ |
| 336 | { | ||
| 337 | timeout = WATCHDOG_TIMEOUT; | 337 | timeout = WATCHDOG_TIMEOUT; |
| 338 | printk(KERN_INFO PFX "timeout value must be 1<=x<=3600, using %d\n", | 338 | printk(KERN_INFO PFX |
| 339 | timeout); | 339 | "timeout value must be 1 <= x <= 3600, using %d\n", |
| 340 | } | 340 | timeout); |
| 341 | } | ||
| 341 | 342 | ||
| 342 | if (!request_region(wdt_start, 1, "SBC 60XX WDT")) | 343 | if (!request_region(wdt_start, 1, "SBC 60XX WDT")) { |
| 343 | { | ||
| 344 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 344 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 345 | wdt_start); | 345 | wdt_start); |
| 346 | rc = -EIO; | 346 | rc = -EIO; |
| @@ -348,33 +348,30 @@ static int __init sbc60xxwdt_init(void) | |||
| 348 | } | 348 | } |
| 349 | 349 | ||
| 350 | /* We cannot reserve 0x45 - the kernel already has! */ | 350 | /* We cannot reserve 0x45 - the kernel already has! */ |
| 351 | if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) | 351 | if (wdt_stop != 0x45 && wdt_stop != wdt_start) { |
| 352 | { | 352 | if (!request_region(wdt_stop, 1, "SBC 60XX WDT")) { |
| 353 | if (!request_region(wdt_stop, 1, "SBC 60XX WDT")) | 353 | printk(KERN_ERR PFX |
| 354 | { | 354 | "I/O address 0x%04x already in use\n", |
| 355 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 355 | wdt_stop); |
| 356 | wdt_stop); | ||
| 357 | rc = -EIO; | 356 | rc = -EIO; |
| 358 | goto err_out_region1; | 357 | goto err_out_region1; |
| 359 | } | 358 | } |
| 360 | } | 359 | } |
| 361 | 360 | ||
| 362 | rc = register_reboot_notifier(&wdt_notifier); | 361 | rc = register_reboot_notifier(&wdt_notifier); |
| 363 | if (rc) | 362 | if (rc) { |
| 364 | { | 363 | printk(KERN_ERR PFX |
| 365 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 364 | "cannot register reboot notifier (err=%d)\n", rc); |
| 366 | rc); | ||
| 367 | goto err_out_region2; | 365 | goto err_out_region2; |
| 368 | } | 366 | } |
| 369 | 367 | ||
| 370 | rc = misc_register(&wdt_miscdev); | 368 | rc = misc_register(&wdt_miscdev); |
| 371 | if (rc) | 369 | if (rc) { |
| 372 | { | 370 | printk(KERN_ERR PFX |
| 373 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 371 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 374 | wdt_miscdev.minor, rc); | 372 | wdt_miscdev.minor, rc); |
| 375 | goto err_out_reboot; | 373 | goto err_out_reboot; |
| 376 | } | 374 | } |
| 377 | |||
| 378 | printk(KERN_INFO PFX "WDT driver for 60XX single board computer initialised. timeout=%d sec (nowayout=%d)\n", | 375 | printk(KERN_INFO PFX "WDT driver for 60XX single board computer initialised. timeout=%d sec (nowayout=%d)\n", |
| 379 | timeout, nowayout); | 376 | timeout, nowayout); |
| 380 | 377 | ||
| @@ -383,10 +380,10 @@ static int __init sbc60xxwdt_init(void) | |||
| 383 | err_out_reboot: | 380 | err_out_reboot: |
| 384 | unregister_reboot_notifier(&wdt_notifier); | 381 | unregister_reboot_notifier(&wdt_notifier); |
| 385 | err_out_region2: | 382 | err_out_region2: |
| 386 | if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) | 383 | if (wdt_stop != 0x45 && wdt_stop != wdt_start) |
| 387 | release_region(wdt_stop,1); | 384 | release_region(wdt_stop, 1); |
| 388 | err_out_region1: | 385 | err_out_region1: |
| 389 | release_region(wdt_start,1); | 386 | release_region(wdt_start, 1); |
| 390 | err_out: | 387 | err_out: |
| 391 | return rc; | 388 | return rc; |
| 392 | } | 389 | } |
diff --git a/drivers/watchdog/sbc7240_wdt.c b/drivers/watchdog/sbc7240_wdt.c index 4c8cefbd8627..67ddeb1c830a 100644 --- a/drivers/watchdog/sbc7240_wdt.c +++ b/drivers/watchdog/sbc7240_wdt.c | |||
| @@ -27,10 +27,10 @@ | |||
| 27 | #include <linux/reboot.h> | 27 | #include <linux/reboot.h> |
| 28 | #include <linux/types.h> | 28 | #include <linux/types.h> |
| 29 | #include <linux/watchdog.h> | 29 | #include <linux/watchdog.h> |
| 30 | #include <linux/io.h> | ||
| 31 | #include <linux/uaccess.h> | ||
| 30 | #include <asm/atomic.h> | 32 | #include <asm/atomic.h> |
| 31 | #include <asm/io.h> | ||
| 32 | #include <asm/system.h> | 33 | #include <asm/system.h> |
| 33 | #include <asm/uaccess.h> | ||
| 34 | 34 | ||
| 35 | #define SBC7240_PREFIX "sbc7240_wdt: " | 35 | #define SBC7240_PREFIX "sbc7240_wdt: " |
| 36 | 36 | ||
| @@ -159,7 +159,7 @@ static int fop_close(struct inode *inode, struct file *file) | |||
| 159 | return 0; | 159 | return 0; |
| 160 | } | 160 | } |
| 161 | 161 | ||
| 162 | static struct watchdog_info ident = { | 162 | static const struct watchdog_info ident = { |
| 163 | .options = WDIOF_KEEPALIVEPING| | 163 | .options = WDIOF_KEEPALIVEPING| |
| 164 | WDIOF_SETTIMEOUT| | 164 | WDIOF_SETTIMEOUT| |
| 165 | WDIOF_MAGICCLOSE, | 165 | WDIOF_MAGICCLOSE, |
| @@ -168,50 +168,50 @@ static struct watchdog_info ident = { | |||
| 168 | }; | 168 | }; |
| 169 | 169 | ||
| 170 | 170 | ||
| 171 | static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 171 | static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 172 | unsigned long arg) | ||
| 173 | { | 172 | { |
| 174 | switch (cmd) { | 173 | switch (cmd) { |
| 175 | case WDIOC_GETSUPPORT: | 174 | case WDIOC_GETSUPPORT: |
| 176 | return copy_to_user | 175 | return copy_to_user((void __user *)arg, &ident, sizeof(ident)) |
| 177 | ((void __user *)arg, &ident, sizeof(ident)) | 176 | ? -EFAULT : 0; |
| 178 | ? -EFAULT : 0; | ||
| 179 | case WDIOC_GETSTATUS: | 177 | case WDIOC_GETSTATUS: |
| 180 | case WDIOC_GETBOOTSTATUS: | 178 | case WDIOC_GETBOOTSTATUS: |
| 181 | return put_user(0, (int __user *)arg); | 179 | return put_user(0, (int __user *)arg); |
| 182 | case WDIOC_KEEPALIVE: | 180 | case WDIOC_SETOPTIONS: |
| 183 | wdt_keepalive(); | 181 | { |
| 184 | return 0; | 182 | int options; |
| 185 | case WDIOC_SETOPTIONS:{ | 183 | int retval = -EINVAL; |
| 186 | int options; | ||
| 187 | int retval = -EINVAL; | ||
| 188 | 184 | ||
| 189 | if (get_user(options, (int __user *)arg)) | 185 | if (get_user(options, (int __user *)arg)) |
| 190 | return -EFAULT; | 186 | return -EFAULT; |
| 191 | 187 | ||
| 192 | if (options & WDIOS_DISABLECARD) { | 188 | if (options & WDIOS_DISABLECARD) { |
| 193 | wdt_disable(); | 189 | wdt_disable(); |
| 194 | retval = 0; | 190 | retval = 0; |
| 195 | } | 191 | } |
| 196 | |||
| 197 | if (options & WDIOS_ENABLECARD) { | ||
| 198 | wdt_enable(); | ||
| 199 | retval = 0; | ||
| 200 | } | ||
| 201 | 192 | ||
| 202 | return retval; | 193 | if (options & WDIOS_ENABLECARD) { |
| 194 | wdt_enable(); | ||
| 195 | retval = 0; | ||
| 203 | } | 196 | } |
| 204 | case WDIOC_SETTIMEOUT:{ | ||
| 205 | int new_timeout; | ||
| 206 | 197 | ||
| 207 | if (get_user(new_timeout, (int __user *)arg)) | 198 | return retval; |
| 208 | return -EFAULT; | 199 | } |
| 200 | case WDIOC_KEEPALIVE: | ||
| 201 | wdt_keepalive(); | ||
| 202 | return 0; | ||
| 203 | case WDIOC_SETTIMEOUT: | ||
| 204 | { | ||
| 205 | int new_timeout; | ||
| 209 | 206 | ||
| 210 | if (wdt_set_timeout(new_timeout)) | 207 | if (get_user(new_timeout, (int __user *)arg)) |
| 211 | return -EINVAL; | 208 | return -EFAULT; |
| 212 | 209 | ||
| 213 | /* Fall through */ | 210 | if (wdt_set_timeout(new_timeout)) |
| 214 | } | 211 | return -EINVAL; |
| 212 | |||
| 213 | /* Fall through */ | ||
| 214 | } | ||
| 215 | case WDIOC_GETTIMEOUT: | 215 | case WDIOC_GETTIMEOUT: |
| 216 | return put_user(timeout, (int __user *)arg); | 216 | return put_user(timeout, (int __user *)arg); |
| 217 | default: | 217 | default: |
| @@ -225,7 +225,7 @@ static const struct file_operations wdt_fops = { | |||
| 225 | .write = fop_write, | 225 | .write = fop_write, |
| 226 | .open = fop_open, | 226 | .open = fop_open, |
| 227 | .release = fop_close, | 227 | .release = fop_close, |
| 228 | .ioctl = fop_ioctl, | 228 | .unlocked_ioctl = fop_ioctl, |
| 229 | }; | 229 | }; |
| 230 | 230 | ||
| 231 | static struct miscdevice wdt_miscdev = { | 231 | static struct miscdevice wdt_miscdev = { |
diff --git a/drivers/watchdog/sbc8360.c b/drivers/watchdog/sbc8360.c index 2ee2677f3648..fd83dd052d8c 100644 --- a/drivers/watchdog/sbc8360.c +++ b/drivers/watchdog/sbc8360.c | |||
| @@ -48,13 +48,12 @@ | |||
| 48 | #include <linux/init.h> | 48 | #include <linux/init.h> |
| 49 | #include <linux/spinlock.h> | 49 | #include <linux/spinlock.h> |
| 50 | #include <linux/moduleparam.h> | 50 | #include <linux/moduleparam.h> |
| 51 | #include <linux/io.h> | ||
| 52 | #include <linux/uaccess.h> | ||
| 51 | 53 | ||
| 52 | #include <asm/io.h> | ||
| 53 | #include <asm/uaccess.h> | ||
| 54 | #include <asm/system.h> | 54 | #include <asm/system.h> |
| 55 | 55 | ||
| 56 | static unsigned long sbc8360_is_open; | 56 | static unsigned long sbc8360_is_open; |
| 57 | static DEFINE_SPINLOCK(sbc8360_lock); | ||
| 58 | static char expect_close; | 57 | static char expect_close; |
| 59 | 58 | ||
| 60 | #define PFX "sbc8360: " | 59 | #define PFX "sbc8360: " |
| @@ -204,7 +203,8 @@ module_param(timeout, int, 0); | |||
| 204 | MODULE_PARM_DESC(timeout, "Index into timeout table (0-63) (default=27 (60s))"); | 203 | MODULE_PARM_DESC(timeout, "Index into timeout table (0-63) (default=27 (60s))"); |
| 205 | module_param(nowayout, int, 0); | 204 | module_param(nowayout, int, 0); |
| 206 | MODULE_PARM_DESC(nowayout, | 205 | MODULE_PARM_DESC(nowayout, |
| 207 | "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 206 | "Watchdog cannot be stopped once started (default=" |
| 207 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 208 | 208 | ||
| 209 | /* | 209 | /* |
| 210 | * Kernel methods. | 210 | * Kernel methods. |
| @@ -231,9 +231,16 @@ static void sbc8360_ping(void) | |||
| 231 | outb(wd_margin, SBC8360_BASETIME); | 231 | outb(wd_margin, SBC8360_BASETIME); |
| 232 | } | 232 | } |
| 233 | 233 | ||
| 234 | /* stop watchdog */ | ||
| 235 | static void sbc8360_stop(void) | ||
| 236 | { | ||
| 237 | /* De-activate the watchdog */ | ||
| 238 | outb(0, SBC8360_ENABLE); | ||
| 239 | } | ||
| 240 | |||
| 234 | /* Userspace pings kernel driver, or requests clean close */ | 241 | /* Userspace pings kernel driver, or requests clean close */ |
| 235 | static ssize_t sbc8360_write(struct file *file, const char __user * buf, | 242 | static ssize_t sbc8360_write(struct file *file, const char __user *buf, |
| 236 | size_t count, loff_t * ppos) | 243 | size_t count, loff_t *ppos) |
| 237 | { | 244 | { |
| 238 | if (count) { | 245 | if (count) { |
| 239 | if (!nowayout) { | 246 | if (!nowayout) { |
| @@ -257,16 +264,12 @@ static ssize_t sbc8360_write(struct file *file, const char __user * buf, | |||
| 257 | 264 | ||
| 258 | static int sbc8360_open(struct inode *inode, struct file *file) | 265 | static int sbc8360_open(struct inode *inode, struct file *file) |
| 259 | { | 266 | { |
| 260 | spin_lock(&sbc8360_lock); | 267 | if (test_and_set_bit(0, &sbc8360_is_open)) |
| 261 | if (test_and_set_bit(0, &sbc8360_is_open)) { | ||
| 262 | spin_unlock(&sbc8360_lock); | ||
| 263 | return -EBUSY; | 268 | return -EBUSY; |
| 264 | } | ||
| 265 | if (nowayout) | 269 | if (nowayout) |
| 266 | __module_get(THIS_MODULE); | 270 | __module_get(THIS_MODULE); |
| 267 | 271 | ||
| 268 | /* Activate and ping once to start the countdown */ | 272 | /* Activate and ping once to start the countdown */ |
| 269 | spin_unlock(&sbc8360_lock); | ||
| 270 | sbc8360_activate(); | 273 | sbc8360_activate(); |
| 271 | sbc8360_ping(); | 274 | sbc8360_ping(); |
| 272 | return nonseekable_open(inode, file); | 275 | return nonseekable_open(inode, file); |
| @@ -274,16 +277,14 @@ static int sbc8360_open(struct inode *inode, struct file *file) | |||
| 274 | 277 | ||
| 275 | static int sbc8360_close(struct inode *inode, struct file *file) | 278 | static int sbc8360_close(struct inode *inode, struct file *file) |
| 276 | { | 279 | { |
| 277 | spin_lock(&sbc8360_lock); | ||
| 278 | if (expect_close == 42) | 280 | if (expect_close == 42) |
| 279 | outb(0, SBC8360_ENABLE); | 281 | sbc8360_stop(); |
| 280 | else | 282 | else |
| 281 | printk(KERN_CRIT PFX | 283 | printk(KERN_CRIT PFX |
| 282 | "SBC8360 device closed unexpectedly. SBC8360 will not stop!\n"); | 284 | "SBC8360 device closed unexpectedly. SBC8360 will not stop!\n"); |
| 283 | 285 | ||
| 284 | clear_bit(0, &sbc8360_is_open); | 286 | clear_bit(0, &sbc8360_is_open); |
| 285 | expect_close = 0; | 287 | expect_close = 0; |
| 286 | spin_unlock(&sbc8360_lock); | ||
| 287 | return 0; | 288 | return 0; |
| 288 | } | 289 | } |
| 289 | 290 | ||
| @@ -294,10 +295,9 @@ static int sbc8360_close(struct inode *inode, struct file *file) | |||
| 294 | static int sbc8360_notify_sys(struct notifier_block *this, unsigned long code, | 295 | static int sbc8360_notify_sys(struct notifier_block *this, unsigned long code, |
| 295 | void *unused) | 296 | void *unused) |
| 296 | { | 297 | { |
| 297 | if (code == SYS_DOWN || code == SYS_HALT) { | 298 | if (code == SYS_DOWN || code == SYS_HALT) |
| 298 | /* Disable the SBC8360 Watchdog */ | 299 | sbc8360_stop(); /* Disable the SBC8360 Watchdog */ |
| 299 | outb(0, SBC8360_ENABLE); | 300 | |
| 300 | } | ||
| 301 | return NOTIFY_DONE; | 301 | return NOTIFY_DONE; |
| 302 | } | 302 | } |
| 303 | 303 | ||
| @@ -382,13 +382,13 @@ static int __init sbc8360_init(void) | |||
| 382 | 382 | ||
| 383 | return 0; | 383 | return 0; |
| 384 | 384 | ||
| 385 | out_nomisc: | 385 | out_nomisc: |
| 386 | unregister_reboot_notifier(&sbc8360_notifier); | 386 | unregister_reboot_notifier(&sbc8360_notifier); |
| 387 | out_noreboot: | 387 | out_noreboot: |
| 388 | release_region(SBC8360_BASETIME, 1); | 388 | release_region(SBC8360_BASETIME, 1); |
| 389 | out_nobasetimereg: | 389 | out_nobasetimereg: |
| 390 | release_region(SBC8360_ENABLE, 1); | 390 | release_region(SBC8360_ENABLE, 1); |
| 391 | out: | 391 | out: |
| 392 | return res; | 392 | return res; |
| 393 | } | 393 | } |
| 394 | 394 | ||
diff --git a/drivers/watchdog/sbc_epx_c3.c b/drivers/watchdog/sbc_epx_c3.c index 82cbd8809a69..e5e470ca7759 100644 --- a/drivers/watchdog/sbc_epx_c3.c +++ b/drivers/watchdog/sbc_epx_c3.c | |||
| @@ -25,8 +25,8 @@ | |||
| 25 | #include <linux/reboot.h> | 25 | #include <linux/reboot.h> |
| 26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 27 | #include <linux/ioport.h> | 27 | #include <linux/ioport.h> |
| 28 | #include <asm/uaccess.h> | 28 | #include <linux/uaccess.h> |
| 29 | #include <asm/io.h> | 29 | #include <linux/io.h> |
| 30 | 30 | ||
| 31 | #define PFX "epx_c3: " | 31 | #define PFX "epx_c3: " |
| 32 | static int epx_c3_alive; | 32 | static int epx_c3_alive; |
| @@ -100,12 +100,12 @@ static ssize_t epx_c3_write(struct file *file, const char __user *data, | |||
| 100 | return len; | 100 | return len; |
| 101 | } | 101 | } |
| 102 | 102 | ||
| 103 | static int epx_c3_ioctl(struct inode *inode, struct file *file, | 103 | static long epx_c3_ioctl(struct file *file, unsigned int cmd, |
| 104 | unsigned int cmd, unsigned long arg) | 104 | unsigned long arg) |
| 105 | { | 105 | { |
| 106 | int options, retval = -EINVAL; | 106 | int options, retval = -EINVAL; |
| 107 | int __user *argp = (void __user *)arg; | 107 | int __user *argp = (void __user *)arg; |
| 108 | static struct watchdog_info ident = { | 108 | static const struct watchdog_info ident = { |
| 109 | .options = WDIOF_KEEPALIVEPING | | 109 | .options = WDIOF_KEEPALIVEPING | |
| 110 | WDIOF_MAGICCLOSE, | 110 | WDIOF_MAGICCLOSE, |
| 111 | .firmware_version = 0, | 111 | .firmware_version = 0, |
| @@ -120,11 +120,6 @@ static int epx_c3_ioctl(struct inode *inode, struct file *file, | |||
| 120 | case WDIOC_GETSTATUS: | 120 | case WDIOC_GETSTATUS: |
| 121 | case WDIOC_GETBOOTSTATUS: | 121 | case WDIOC_GETBOOTSTATUS: |
| 122 | return put_user(0, argp); | 122 | return put_user(0, argp); |
| 123 | case WDIOC_KEEPALIVE: | ||
| 124 | epx_c3_pet(); | ||
| 125 | return 0; | ||
| 126 | case WDIOC_GETTIMEOUT: | ||
| 127 | return put_user(WATCHDOG_TIMEOUT, argp); | ||
| 128 | case WDIOC_SETOPTIONS: | 123 | case WDIOC_SETOPTIONS: |
| 129 | if (get_user(options, argp)) | 124 | if (get_user(options, argp)) |
| 130 | return -EFAULT; | 125 | return -EFAULT; |
| @@ -140,6 +135,11 @@ static int epx_c3_ioctl(struct inode *inode, struct file *file, | |||
| 140 | } | 135 | } |
| 141 | 136 | ||
| 142 | return retval; | 137 | return retval; |
| 138 | case WDIOC_KEEPALIVE: | ||
| 139 | epx_c3_pet(); | ||
| 140 | return 0; | ||
| 141 | case WDIOC_GETTIMEOUT: | ||
| 142 | return put_user(WATCHDOG_TIMEOUT, argp); | ||
| 143 | default: | 143 | default: |
| 144 | return -ENOTTY; | 144 | return -ENOTTY; |
| 145 | } | 145 | } |
| @@ -158,7 +158,7 @@ static const struct file_operations epx_c3_fops = { | |||
| 158 | .owner = THIS_MODULE, | 158 | .owner = THIS_MODULE, |
| 159 | .llseek = no_llseek, | 159 | .llseek = no_llseek, |
| 160 | .write = epx_c3_write, | 160 | .write = epx_c3_write, |
| 161 | .ioctl = epx_c3_ioctl, | 161 | .unlocked_ioctl = epx_c3_ioctl, |
| 162 | .open = epx_c3_open, | 162 | .open = epx_c3_open, |
| 163 | .release = epx_c3_release, | 163 | .release = epx_c3_release, |
| 164 | }; | 164 | }; |
diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c index 621ebad56d86..23da3ccd832a 100644 --- a/drivers/watchdog/sc1200wdt.c +++ b/drivers/watchdog/sc1200wdt.c | |||
| @@ -196,7 +196,6 @@ static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 196 | }; | 196 | }; |
| 197 | 197 | ||
| 198 | switch (cmd) { | 198 | switch (cmd) { |
| 199 | |||
| 200 | case WDIOC_GETSUPPORT: | 199 | case WDIOC_GETSUPPORT: |
| 201 | if (copy_to_user(argp, &ident, sizeof ident)) | 200 | if (copy_to_user(argp, &ident, sizeof ident)) |
| 202 | return -EFAULT; | 201 | return -EFAULT; |
| @@ -208,24 +207,6 @@ static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 208 | case WDIOC_GETBOOTSTATUS: | 207 | case WDIOC_GETBOOTSTATUS: |
| 209 | return put_user(0, p); | 208 | return put_user(0, p); |
| 210 | 209 | ||
| 211 | case WDIOC_KEEPALIVE: | ||
| 212 | sc1200wdt_write_data(WDTO, timeout); | ||
| 213 | return 0; | ||
| 214 | |||
| 215 | case WDIOC_SETTIMEOUT: | ||
| 216 | if (get_user(new_timeout, p)) | ||
| 217 | return -EFAULT; | ||
| 218 | /* the API states this is given in secs */ | ||
| 219 | new_timeout /= 60; | ||
| 220 | if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) | ||
| 221 | return -EINVAL; | ||
| 222 | timeout = new_timeout; | ||
| 223 | sc1200wdt_write_data(WDTO, timeout); | ||
| 224 | /* fall through and return the new timeout */ | ||
| 225 | |||
| 226 | case WDIOC_GETTIMEOUT: | ||
| 227 | return put_user(timeout * 60, p); | ||
| 228 | |||
| 229 | case WDIOC_SETOPTIONS: | 210 | case WDIOC_SETOPTIONS: |
| 230 | { | 211 | { |
| 231 | int options, retval = -EINVAL; | 212 | int options, retval = -EINVAL; |
| @@ -245,6 +226,24 @@ static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 245 | 226 | ||
| 246 | return retval; | 227 | return retval; |
| 247 | } | 228 | } |
| 229 | case WDIOC_KEEPALIVE: | ||
| 230 | sc1200wdt_write_data(WDTO, timeout); | ||
| 231 | return 0; | ||
| 232 | |||
| 233 | case WDIOC_SETTIMEOUT: | ||
| 234 | if (get_user(new_timeout, p)) | ||
| 235 | return -EFAULT; | ||
| 236 | /* the API states this is given in secs */ | ||
| 237 | new_timeout /= 60; | ||
| 238 | if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) | ||
| 239 | return -EINVAL; | ||
| 240 | timeout = new_timeout; | ||
| 241 | sc1200wdt_write_data(WDTO, timeout); | ||
| 242 | /* fall through and return the new timeout */ | ||
| 243 | |||
| 244 | case WDIOC_GETTIMEOUT: | ||
| 245 | return put_user(timeout * 60, p); | ||
| 246 | |||
| 248 | default: | 247 | default: |
| 249 | return -ENOTTY; | 248 | return -ENOTTY; |
| 250 | } | 249 | } |
| @@ -280,7 +279,7 @@ static ssize_t sc1200wdt_write(struct file *file, const char __user *data, | |||
| 280 | for (i = 0; i != len; i++) { | 279 | for (i = 0; i != len; i++) { |
| 281 | char c; | 280 | char c; |
| 282 | 281 | ||
| 283 | if (get_user(c, data+i)) | 282 | if (get_user(c, data + i)) |
| 284 | return -EFAULT; | 283 | return -EFAULT; |
| 285 | if (c == 'V') | 284 | if (c == 'V') |
| 286 | expect_close = 42; | 285 | expect_close = 42; |
diff --git a/drivers/watchdog/sc520_wdt.c b/drivers/watchdog/sc520_wdt.c index 2847324a2be2..a2b6c1067ec5 100644 --- a/drivers/watchdog/sc520_wdt.c +++ b/drivers/watchdog/sc520_wdt.c | |||
| @@ -64,9 +64,9 @@ | |||
| 64 | #include <linux/reboot.h> | 64 | #include <linux/reboot.h> |
| 65 | #include <linux/init.h> | 65 | #include <linux/init.h> |
| 66 | #include <linux/jiffies.h> | 66 | #include <linux/jiffies.h> |
| 67 | #include <linux/io.h> | ||
| 68 | #include <linux/uaccess.h> | ||
| 67 | 69 | ||
| 68 | #include <asm/io.h> | ||
| 69 | #include <asm/uaccess.h> | ||
| 70 | #include <asm/system.h> | 70 | #include <asm/system.h> |
| 71 | 71 | ||
| 72 | #define OUR_NAME "sc520_wdt" | 72 | #define OUR_NAME "sc520_wdt" |
| @@ -91,13 +91,18 @@ | |||
| 91 | */ | 91 | */ |
| 92 | 92 | ||
| 93 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ | 93 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ |
| 94 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ | 94 | /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ |
| 95 | static int timeout = WATCHDOG_TIMEOUT; | ||
| 95 | module_param(timeout, int, 0); | 96 | module_param(timeout, int, 0); |
| 96 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 97 | MODULE_PARM_DESC(timeout, |
| 98 | "Watchdog timeout in seconds. (1 <= timeout <= 3600, default=" | ||
| 99 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 97 | 100 | ||
| 98 | static int nowayout = WATCHDOG_NOWAYOUT; | 101 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 99 | module_param(nowayout, int, 0); | 102 | module_param(nowayout, int, 0); |
| 100 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 103 | MODULE_PARM_DESC(nowayout, |
| 104 | "Watchdog cannot be stopped once started (default=" | ||
| 105 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 101 | 106 | ||
| 102 | /* | 107 | /* |
| 103 | * AMD Elan SC520 - Watchdog Timer Registers | 108 | * AMD Elan SC520 - Watchdog Timer Registers |
| @@ -136,8 +141,7 @@ static void wdt_timer_ping(unsigned long data) | |||
| 136 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL | 141 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL |
| 137 | * we agree to ping the WDT | 142 | * we agree to ping the WDT |
| 138 | */ | 143 | */ |
| 139 | if(time_before(jiffies, next_heartbeat)) | 144 | if (time_before(jiffies, next_heartbeat)) { |
| 140 | { | ||
| 141 | /* Ping the WDT */ | 145 | /* Ping the WDT */ |
| 142 | spin_lock(&wdt_spinlock); | 146 | spin_lock(&wdt_spinlock); |
| 143 | writew(0xAAAA, wdtmrctl); | 147 | writew(0xAAAA, wdtmrctl); |
| @@ -146,9 +150,9 @@ static void wdt_timer_ping(unsigned long data) | |||
| 146 | 150 | ||
| 147 | /* Re-set the timer interval */ | 151 | /* Re-set the timer interval */ |
| 148 | mod_timer(&timer, jiffies + WDT_INTERVAL); | 152 | mod_timer(&timer, jiffies + WDT_INTERVAL); |
| 149 | } else { | 153 | } else |
| 150 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); | 154 | printk(KERN_WARNING PFX |
| 151 | } | 155 | "Heartbeat lost! Will not ping the watchdog\n"); |
| 152 | } | 156 | } |
| 153 | 157 | ||
| 154 | /* | 158 | /* |
| @@ -162,7 +166,7 @@ static void wdt_config(int writeval) | |||
| 162 | 166 | ||
| 163 | /* buy some time (ping) */ | 167 | /* buy some time (ping) */ |
| 164 | spin_lock_irqsave(&wdt_spinlock, flags); | 168 | spin_lock_irqsave(&wdt_spinlock, flags); |
| 165 | dummy=readw(wdtmrctl); /* ensure write synchronization */ | 169 | dummy = readw(wdtmrctl); /* ensure write synchronization */ |
| 166 | writew(0xAAAA, wdtmrctl); | 170 | writew(0xAAAA, wdtmrctl); |
| 167 | writew(0x5555, wdtmrctl); | 171 | writew(0x5555, wdtmrctl); |
| 168 | /* unlock WDT = make WDT configuration register writable one time */ | 172 | /* unlock WDT = make WDT configuration register writable one time */ |
| @@ -219,10 +223,11 @@ static int wdt_set_heartbeat(int t) | |||
| 219 | * /dev/watchdog handling | 223 | * /dev/watchdog handling |
| 220 | */ | 224 | */ |
| 221 | 225 | ||
| 222 | static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) | 226 | static ssize_t fop_write(struct file *file, const char __user *buf, |
| 227 | size_t count, loff_t *ppos) | ||
| 223 | { | 228 | { |
| 224 | /* See if we got the magic character 'V' and reload the timer */ | 229 | /* See if we got the magic character 'V' and reload the timer */ |
| 225 | if(count) { | 230 | if (count) { |
| 226 | if (!nowayout) { | 231 | if (!nowayout) { |
| 227 | size_t ofs; | 232 | size_t ofs; |
| 228 | 233 | ||
| @@ -231,25 +236,26 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou | |||
| 231 | wdt_expect_close = 0; | 236 | wdt_expect_close = 0; |
| 232 | 237 | ||
| 233 | /* now scan */ | 238 | /* now scan */ |
| 234 | for(ofs = 0; ofs != count; ofs++) { | 239 | for (ofs = 0; ofs != count; ofs++) { |
| 235 | char c; | 240 | char c; |
| 236 | if (get_user(c, buf + ofs)) | 241 | if (get_user(c, buf + ofs)) |
| 237 | return -EFAULT; | 242 | return -EFAULT; |
| 238 | if(c == 'V') | 243 | if (c == 'V') |
| 239 | wdt_expect_close = 42; | 244 | wdt_expect_close = 42; |
| 240 | } | 245 | } |
| 241 | } | 246 | } |
| 242 | 247 | ||
| 243 | /* Well, anyhow someone wrote to us, we should return that favour */ | 248 | /* Well, anyhow someone wrote to us, we should |
| 249 | return that favour */ | ||
| 244 | wdt_keepalive(); | 250 | wdt_keepalive(); |
| 245 | } | 251 | } |
| 246 | return count; | 252 | return count; |
| 247 | } | 253 | } |
| 248 | 254 | ||
| 249 | static int fop_open(struct inode * inode, struct file * file) | 255 | static int fop_open(struct inode *inode, struct file *file) |
| 250 | { | 256 | { |
| 251 | /* Just in case we're already talking to someone... */ | 257 | /* Just in case we're already talking to someone... */ |
| 252 | if(test_and_set_bit(0, &wdt_is_open)) | 258 | if (test_and_set_bit(0, &wdt_is_open)) |
| 253 | return -EBUSY; | 259 | return -EBUSY; |
| 254 | if (nowayout) | 260 | if (nowayout) |
| 255 | __module_get(THIS_MODULE); | 261 | __module_get(THIS_MODULE); |
| @@ -259,12 +265,13 @@ static int fop_open(struct inode * inode, struct file * file) | |||
| 259 | return nonseekable_open(inode, file); | 265 | return nonseekable_open(inode, file); |
| 260 | } | 266 | } |
| 261 | 267 | ||
| 262 | static int fop_close(struct inode * inode, struct file * file) | 268 | static int fop_close(struct inode *inode, struct file *file) |
| 263 | { | 269 | { |
| 264 | if(wdt_expect_close == 42) { | 270 | if (wdt_expect_close == 42) |
| 265 | wdt_turnoff(); | 271 | wdt_turnoff(); |
| 266 | } else { | 272 | else { |
| 267 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 273 | printk(KERN_CRIT PFX |
| 274 | "Unexpected close, not stopping watchdog!\n"); | ||
| 268 | wdt_keepalive(); | 275 | wdt_keepalive(); |
| 269 | } | 276 | } |
| 270 | clear_bit(0, &wdt_is_open); | 277 | clear_bit(0, &wdt_is_open); |
| @@ -272,63 +279,62 @@ static int fop_close(struct inode * inode, struct file * file) | |||
| 272 | return 0; | 279 | return 0; |
| 273 | } | 280 | } |
| 274 | 281 | ||
| 275 | static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 282 | static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 276 | unsigned long arg) | ||
| 277 | { | 283 | { |
| 278 | void __user *argp = (void __user *)arg; | 284 | void __user *argp = (void __user *)arg; |
| 279 | int __user *p = argp; | 285 | int __user *p = argp; |
| 280 | static struct watchdog_info ident = { | 286 | static const struct watchdog_info ident = { |
| 281 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 287 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
| 288 | | WDIOF_MAGICCLOSE, | ||
| 282 | .firmware_version = 1, | 289 | .firmware_version = 1, |
| 283 | .identity = "SC520", | 290 | .identity = "SC520", |
| 284 | }; | 291 | }; |
| 285 | 292 | ||
| 286 | switch(cmd) | 293 | switch (cmd) { |
| 294 | case WDIOC_GETSUPPORT: | ||
| 295 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 296 | case WDIOC_GETSTATUS: | ||
| 297 | case WDIOC_GETBOOTSTATUS: | ||
| 298 | return put_user(0, p); | ||
| 299 | case WDIOC_SETOPTIONS: | ||
| 287 | { | 300 | { |
| 288 | default: | 301 | int new_options, retval = -EINVAL; |
| 289 | return -ENOTTY; | ||
| 290 | case WDIOC_GETSUPPORT: | ||
| 291 | return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; | ||
| 292 | case WDIOC_GETSTATUS: | ||
| 293 | case WDIOC_GETBOOTSTATUS: | ||
| 294 | return put_user(0, p); | ||
| 295 | case WDIOC_KEEPALIVE: | ||
| 296 | wdt_keepalive(); | ||
| 297 | return 0; | ||
| 298 | case WDIOC_SETOPTIONS: | ||
| 299 | { | ||
| 300 | int new_options, retval = -EINVAL; | ||
| 301 | |||
| 302 | if(get_user(new_options, p)) | ||
| 303 | return -EFAULT; | ||
| 304 | |||
| 305 | if(new_options & WDIOS_DISABLECARD) { | ||
| 306 | wdt_turnoff(); | ||
| 307 | retval = 0; | ||
| 308 | } | ||
| 309 | 302 | ||
| 310 | if(new_options & WDIOS_ENABLECARD) { | 303 | if (get_user(new_options, p)) |
| 311 | wdt_startup(); | 304 | return -EFAULT; |
| 312 | retval = 0; | ||
| 313 | } | ||
| 314 | 305 | ||
| 315 | return retval; | 306 | if (new_options & WDIOS_DISABLECARD) { |
| 307 | wdt_turnoff(); | ||
| 308 | retval = 0; | ||
| 316 | } | 309 | } |
| 317 | case WDIOC_SETTIMEOUT: | ||
| 318 | { | ||
| 319 | int new_timeout; | ||
| 320 | 310 | ||
| 321 | if(get_user(new_timeout, p)) | 311 | if (new_options & WDIOS_ENABLECARD) { |
| 322 | return -EFAULT; | 312 | wdt_startup(); |
| 313 | retval = 0; | ||
| 314 | } | ||
| 323 | 315 | ||
| 324 | if(wdt_set_heartbeat(new_timeout)) | 316 | return retval; |
| 325 | return -EINVAL; | 317 | } |
| 318 | case WDIOC_KEEPALIVE: | ||
| 319 | wdt_keepalive(); | ||
| 320 | return 0; | ||
| 321 | case WDIOC_SETTIMEOUT: | ||
| 322 | { | ||
| 323 | int new_timeout; | ||
| 326 | 324 | ||
| 327 | wdt_keepalive(); | 325 | if (get_user(new_timeout, p)) |
| 328 | /* Fall through */ | 326 | return -EFAULT; |
| 329 | } | 327 | |
| 330 | case WDIOC_GETTIMEOUT: | 328 | if (wdt_set_heartbeat(new_timeout)) |
| 331 | return put_user(timeout, p); | 329 | return -EINVAL; |
| 330 | |||
| 331 | wdt_keepalive(); | ||
| 332 | /* Fall through */ | ||
| 333 | } | ||
| 334 | case WDIOC_GETTIMEOUT: | ||
| 335 | return put_user(timeout, p); | ||
| 336 | default: | ||
| 337 | return -ENOTTY; | ||
| 332 | } | 338 | } |
| 333 | } | 339 | } |
| 334 | 340 | ||
| @@ -338,7 +344,7 @@ static const struct file_operations wdt_fops = { | |||
| 338 | .write = fop_write, | 344 | .write = fop_write, |
| 339 | .open = fop_open, | 345 | .open = fop_open, |
| 340 | .release = fop_close, | 346 | .release = fop_close, |
| 341 | .ioctl = fop_ioctl, | 347 | .unlocked_ioctl = fop_ioctl, |
| 342 | }; | 348 | }; |
| 343 | 349 | ||
| 344 | static struct miscdevice wdt_miscdev = { | 350 | static struct miscdevice wdt_miscdev = { |
| @@ -354,7 +360,7 @@ static struct miscdevice wdt_miscdev = { | |||
| 354 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | 360 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 355 | void *unused) | 361 | void *unused) |
| 356 | { | 362 | { |
| 357 | if(code==SYS_DOWN || code==SYS_HALT) | 363 | if (code == SYS_DOWN || code == SYS_HALT) |
| 358 | wdt_turnoff(); | 364 | wdt_turnoff(); |
| 359 | return NOTIFY_DONE; | 365 | return NOTIFY_DONE; |
| 360 | } | 366 | } |
| @@ -383,11 +389,13 @@ static int __init sc520_wdt_init(void) | |||
| 383 | { | 389 | { |
| 384 | int rc = -EBUSY; | 390 | int rc = -EBUSY; |
| 385 | 391 | ||
| 386 | /* Check that the timeout value is within it's range ; if not reset to the default */ | 392 | /* Check that the timeout value is within it's range ; |
| 393 | if not reset to the default */ | ||
| 387 | if (wdt_set_heartbeat(timeout)) { | 394 | if (wdt_set_heartbeat(timeout)) { |
| 388 | wdt_set_heartbeat(WATCHDOG_TIMEOUT); | 395 | wdt_set_heartbeat(WATCHDOG_TIMEOUT); |
| 389 | printk(KERN_INFO PFX "timeout value must be 1<=timeout<=3600, using %d\n", | 396 | printk(KERN_INFO PFX |
| 390 | WATCHDOG_TIMEOUT); | 397 | "timeout value must be 1 <= timeout <= 3600, using %d\n", |
| 398 | WATCHDOG_TIMEOUT); | ||
| 391 | } | 399 | } |
| 392 | 400 | ||
| 393 | wdtmrctl = ioremap((unsigned long)(MMCR_BASE + OFFS_WDTMRCTL), 2); | 401 | wdtmrctl = ioremap((unsigned long)(MMCR_BASE + OFFS_WDTMRCTL), 2); |
| @@ -399,20 +407,22 @@ static int __init sc520_wdt_init(void) | |||
| 399 | 407 | ||
| 400 | rc = register_reboot_notifier(&wdt_notifier); | 408 | rc = register_reboot_notifier(&wdt_notifier); |
| 401 | if (rc) { | 409 | if (rc) { |
| 402 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 410 | printk(KERN_ERR PFX |
| 403 | rc); | 411 | "cannot register reboot notifier (err=%d)\n", rc); |
| 404 | goto err_out_ioremap; | 412 | goto err_out_ioremap; |
| 405 | } | 413 | } |
| 406 | 414 | ||
| 407 | rc = misc_register(&wdt_miscdev); | 415 | rc = misc_register(&wdt_miscdev); |
| 408 | if (rc) { | 416 | if (rc) { |
| 409 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 417 | printk(KERN_ERR PFX |
| 410 | WATCHDOG_MINOR, rc); | 418 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 419 | WATCHDOG_MINOR, rc); | ||
| 411 | goto err_out_notifier; | 420 | goto err_out_notifier; |
| 412 | } | 421 | } |
| 413 | 422 | ||
| 414 | printk(KERN_INFO PFX "WDT driver for SC520 initialised. timeout=%d sec (nowayout=%d)\n", | 423 | printk(KERN_INFO PFX |
| 415 | timeout,nowayout); | 424 | "WDT driver for SC520 initialised. timeout=%d sec (nowayout=%d)\n", |
| 425 | timeout, nowayout); | ||
| 416 | 426 | ||
| 417 | return 0; | 427 | return 0; |
| 418 | 428 | ||
diff --git a/drivers/watchdog/scx200_wdt.c b/drivers/watchdog/scx200_wdt.c index d55882bca319..9e19a10a5bb9 100644 --- a/drivers/watchdog/scx200_wdt.c +++ b/drivers/watchdog/scx200_wdt.c | |||
| @@ -27,9 +27,8 @@ | |||
| 27 | #include <linux/fs.h> | 27 | #include <linux/fs.h> |
| 28 | #include <linux/ioport.h> | 28 | #include <linux/ioport.h> |
| 29 | #include <linux/scx200.h> | 29 | #include <linux/scx200.h> |
| 30 | 30 | #include <linux/uaccess.h> | |
| 31 | #include <asm/uaccess.h> | 31 | #include <linux/io.h> |
| 32 | #include <asm/io.h> | ||
| 33 | 32 | ||
| 34 | #define NAME "scx200_wdt" | 33 | #define NAME "scx200_wdt" |
| 35 | 34 | ||
| @@ -47,8 +46,9 @@ module_param(nowayout, int, 0); | |||
| 47 | MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); | 46 | MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); |
| 48 | 47 | ||
| 49 | static u16 wdto_restart; | 48 | static u16 wdto_restart; |
| 50 | static struct semaphore open_semaphore; | ||
| 51 | static char expect_close; | 49 | static char expect_close; |
| 50 | static unsigned long open_lock; | ||
| 51 | static DEFINE_SPINLOCK(scx_lock); | ||
| 52 | 52 | ||
| 53 | /* Bits of the WDCNFG register */ | 53 | /* Bits of the WDCNFG register */ |
| 54 | #define W_ENABLE 0x00fa /* Enable watchdog */ | 54 | #define W_ENABLE 0x00fa /* Enable watchdog */ |
| @@ -59,7 +59,9 @@ static char expect_close; | |||
| 59 | 59 | ||
| 60 | static void scx200_wdt_ping(void) | 60 | static void scx200_wdt_ping(void) |
| 61 | { | 61 | { |
| 62 | spin_lock(&scx_lock); | ||
| 62 | outw(wdto_restart, scx200_cb_base + SCx200_WDT_WDTO); | 63 | outw(wdto_restart, scx200_cb_base + SCx200_WDT_WDTO); |
| 64 | spin_unlock(&scx_lock); | ||
| 63 | } | 65 | } |
| 64 | 66 | ||
| 65 | static void scx200_wdt_update_margin(void) | 67 | static void scx200_wdt_update_margin(void) |
| @@ -73,9 +75,11 @@ static void scx200_wdt_enable(void) | |||
| 73 | printk(KERN_DEBUG NAME ": enabling watchdog timer, wdto_restart = %d\n", | 75 | printk(KERN_DEBUG NAME ": enabling watchdog timer, wdto_restart = %d\n", |
| 74 | wdto_restart); | 76 | wdto_restart); |
| 75 | 77 | ||
| 78 | spin_lock(&scx_lock); | ||
| 76 | outw(0, scx200_cb_base + SCx200_WDT_WDTO); | 79 | outw(0, scx200_cb_base + SCx200_WDT_WDTO); |
| 77 | outb(SCx200_WDT_WDSTS_WDOVF, scx200_cb_base + SCx200_WDT_WDSTS); | 80 | outb(SCx200_WDT_WDSTS_WDOVF, scx200_cb_base + SCx200_WDT_WDSTS); |
| 78 | outw(W_ENABLE, scx200_cb_base + SCx200_WDT_WDCNFG); | 81 | outw(W_ENABLE, scx200_cb_base + SCx200_WDT_WDCNFG); |
| 82 | spin_unlock(&scx_lock); | ||
| 79 | 83 | ||
| 80 | scx200_wdt_ping(); | 84 | scx200_wdt_ping(); |
| 81 | } | 85 | } |
| @@ -84,15 +88,17 @@ static void scx200_wdt_disable(void) | |||
| 84 | { | 88 | { |
| 85 | printk(KERN_DEBUG NAME ": disabling watchdog timer\n"); | 89 | printk(KERN_DEBUG NAME ": disabling watchdog timer\n"); |
| 86 | 90 | ||
| 91 | spin_lock(&scx_lock); | ||
| 87 | outw(0, scx200_cb_base + SCx200_WDT_WDTO); | 92 | outw(0, scx200_cb_base + SCx200_WDT_WDTO); |
| 88 | outb(SCx200_WDT_WDSTS_WDOVF, scx200_cb_base + SCx200_WDT_WDSTS); | 93 | outb(SCx200_WDT_WDSTS_WDOVF, scx200_cb_base + SCx200_WDT_WDSTS); |
| 89 | outw(W_DISABLE, scx200_cb_base + SCx200_WDT_WDCNFG); | 94 | outw(W_DISABLE, scx200_cb_base + SCx200_WDT_WDCNFG); |
| 95 | spin_unlock(&scx_lock); | ||
| 90 | } | 96 | } |
| 91 | 97 | ||
| 92 | static int scx200_wdt_open(struct inode *inode, struct file *file) | 98 | static int scx200_wdt_open(struct inode *inode, struct file *file) |
| 93 | { | 99 | { |
| 94 | /* only allow one at a time */ | 100 | /* only allow one at a time */ |
| 95 | if (down_trylock(&open_semaphore)) | 101 | if (test_and_set_bit(0, &open_lock)) |
| 96 | return -EBUSY; | 102 | return -EBUSY; |
| 97 | scx200_wdt_enable(); | 103 | scx200_wdt_enable(); |
| 98 | 104 | ||
| @@ -101,13 +107,12 @@ static int scx200_wdt_open(struct inode *inode, struct file *file) | |||
| 101 | 107 | ||
| 102 | static int scx200_wdt_release(struct inode *inode, struct file *file) | 108 | static int scx200_wdt_release(struct inode *inode, struct file *file) |
| 103 | { | 109 | { |
| 104 | if (expect_close != 42) { | 110 | if (expect_close != 42) |
| 105 | printk(KERN_WARNING NAME ": watchdog device closed unexpectedly, will not disable the watchdog timer\n"); | 111 | printk(KERN_WARNING NAME ": watchdog device closed unexpectedly, will not disable the watchdog timer\n"); |
| 106 | } else if (!nowayout) { | 112 | else if (!nowayout) |
| 107 | scx200_wdt_disable(); | 113 | scx200_wdt_disable(); |
| 108 | } | ||
| 109 | expect_close = 0; | 114 | expect_close = 0; |
| 110 | up(&open_semaphore); | 115 | clear_bit(0, &open_lock); |
| 111 | 116 | ||
| 112 | return 0; | 117 | return 0; |
| 113 | } | 118 | } |
| @@ -122,8 +127,7 @@ static int scx200_wdt_notify_sys(struct notifier_block *this, | |||
| 122 | return NOTIFY_DONE; | 127 | return NOTIFY_DONE; |
| 123 | } | 128 | } |
| 124 | 129 | ||
| 125 | static struct notifier_block scx200_wdt_notifier = | 130 | static struct notifier_block scx200_wdt_notifier = { |
| 126 | { | ||
| 127 | .notifier_call = scx200_wdt_notify_sys, | 131 | .notifier_call = scx200_wdt_notify_sys, |
| 128 | }; | 132 | }; |
| 129 | 133 | ||
| @@ -131,8 +135,7 @@ static ssize_t scx200_wdt_write(struct file *file, const char __user *data, | |||
| 131 | size_t len, loff_t *ppos) | 135 | size_t len, loff_t *ppos) |
| 132 | { | 136 | { |
| 133 | /* check for a magic close character */ | 137 | /* check for a magic close character */ |
| 134 | if (len) | 138 | if (len) { |
| 135 | { | ||
| 136 | size_t i; | 139 | size_t i; |
| 137 | 140 | ||
| 138 | scx200_wdt_ping(); | 141 | scx200_wdt_ping(); |
| @@ -140,7 +143,7 @@ static ssize_t scx200_wdt_write(struct file *file, const char __user *data, | |||
| 140 | expect_close = 0; | 143 | expect_close = 0; |
| 141 | for (i = 0; i < len; ++i) { | 144 | for (i = 0; i < len; ++i) { |
| 142 | char c; | 145 | char c; |
| 143 | if (get_user(c, data+i)) | 146 | if (get_user(c, data + i)) |
| 144 | return -EFAULT; | 147 | return -EFAULT; |
| 145 | if (c == 'V') | 148 | if (c == 'V') |
| 146 | expect_close = 42; | 149 | expect_close = 42; |
| @@ -152,23 +155,21 @@ static ssize_t scx200_wdt_write(struct file *file, const char __user *data, | |||
| 152 | return 0; | 155 | return 0; |
| 153 | } | 156 | } |
| 154 | 157 | ||
| 155 | static int scx200_wdt_ioctl(struct inode *inode, struct file *file, | 158 | static long scx200_wdt_ioctl(struct file *file, unsigned int cmd, |
| 156 | unsigned int cmd, unsigned long arg) | 159 | unsigned long arg) |
| 157 | { | 160 | { |
| 158 | void __user *argp = (void __user *)arg; | 161 | void __user *argp = (void __user *)arg; |
| 159 | int __user *p = argp; | 162 | int __user *p = argp; |
| 160 | static struct watchdog_info ident = { | 163 | static const struct watchdog_info ident = { |
| 161 | .identity = "NatSemi SCx200 Watchdog", | 164 | .identity = "NatSemi SCx200 Watchdog", |
| 162 | .firmware_version = 1, | 165 | .firmware_version = 1, |
| 163 | .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING), | 166 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
| 164 | }; | 167 | }; |
| 165 | int new_margin; | 168 | int new_margin; |
| 166 | 169 | ||
| 167 | switch (cmd) { | 170 | switch (cmd) { |
| 168 | default: | ||
| 169 | return -ENOTTY; | ||
| 170 | case WDIOC_GETSUPPORT: | 171 | case WDIOC_GETSUPPORT: |
| 171 | if(copy_to_user(argp, &ident, sizeof(ident))) | 172 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 172 | return -EFAULT; | 173 | return -EFAULT; |
| 173 | return 0; | 174 | return 0; |
| 174 | case WDIOC_GETSTATUS: | 175 | case WDIOC_GETSTATUS: |
| @@ -191,22 +192,24 @@ static int scx200_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 191 | if (put_user(margin, p)) | 192 | if (put_user(margin, p)) |
| 192 | return -EFAULT; | 193 | return -EFAULT; |
| 193 | return 0; | 194 | return 0; |
| 195 | default: | ||
| 196 | return -ENOTTY; | ||
| 194 | } | 197 | } |
| 195 | } | 198 | } |
| 196 | 199 | ||
| 197 | static const struct file_operations scx200_wdt_fops = { | 200 | static const struct file_operations scx200_wdt_fops = { |
| 198 | .owner = THIS_MODULE, | 201 | .owner = THIS_MODULE, |
| 199 | .llseek = no_llseek, | 202 | .llseek = no_llseek, |
| 200 | .write = scx200_wdt_write, | 203 | .write = scx200_wdt_write, |
| 201 | .ioctl = scx200_wdt_ioctl, | 204 | .unlocked_ioctl = scx200_wdt_ioctl, |
| 202 | .open = scx200_wdt_open, | 205 | .open = scx200_wdt_open, |
| 203 | .release = scx200_wdt_release, | 206 | .release = scx200_wdt_release, |
| 204 | }; | 207 | }; |
| 205 | 208 | ||
| 206 | static struct miscdevice scx200_wdt_miscdev = { | 209 | static struct miscdevice scx200_wdt_miscdev = { |
| 207 | .minor = WATCHDOG_MINOR, | 210 | .minor = WATCHDOG_MINOR, |
| 208 | .name = "watchdog", | 211 | .name = "watchdog", |
| 209 | .fops = &scx200_wdt_fops, | 212 | .fops = &scx200_wdt_fops, |
| 210 | }; | 213 | }; |
| 211 | 214 | ||
| 212 | static int __init scx200_wdt_init(void) | 215 | static int __init scx200_wdt_init(void) |
| @@ -229,8 +232,6 @@ static int __init scx200_wdt_init(void) | |||
| 229 | scx200_wdt_update_margin(); | 232 | scx200_wdt_update_margin(); |
| 230 | scx200_wdt_disable(); | 233 | scx200_wdt_disable(); |
| 231 | 234 | ||
| 232 | sema_init(&open_semaphore, 1); | ||
| 233 | |||
| 234 | r = register_reboot_notifier(&scx200_wdt_notifier); | 235 | r = register_reboot_notifier(&scx200_wdt_notifier); |
| 235 | if (r) { | 236 | if (r) { |
| 236 | printk(KERN_ERR NAME ": unable to register reboot notifier"); | 237 | printk(KERN_ERR NAME ": unable to register reboot notifier"); |
| @@ -263,7 +264,7 @@ module_exit(scx200_wdt_cleanup); | |||
| 263 | 264 | ||
| 264 | /* | 265 | /* |
| 265 | Local variables: | 266 | Local variables: |
| 266 | compile-command: "make -k -C ../.. SUBDIRS=drivers/char modules" | 267 | compile-command: "make -k -C ../.. SUBDIRS=drivers/char modules" |
| 267 | c-basic-offset: 8 | 268 | c-basic-offset: 8 |
| 268 | End: | 269 | End: |
| 269 | */ | 270 | */ |
diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 1277f7e9cc54..824125adf90a 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include <linux/ioport.h> | 28 | #include <linux/ioport.h> |
| 29 | #include <linux/fs.h> | 29 | #include <linux/fs.h> |
| 30 | #include <linux/mm.h> | 30 | #include <linux/mm.h> |
| 31 | #include <asm/io.h> | 31 | #include <linux/io.h> |
| 32 | #include <asm/uaccess.h> | 32 | #include <linux/uaccess.h> |
| 33 | #include <asm/watchdog.h> | 33 | #include <linux/watchdog.h> |
| 34 | 34 | ||
| 35 | #define PFX "shwdt: " | 35 | #define PFX "shwdt: " |
| 36 | 36 | ||
| @@ -72,6 +72,7 @@ static struct watchdog_info sh_wdt_info; | |||
| 72 | static char shwdt_expect_close; | 72 | static char shwdt_expect_close; |
| 73 | static DEFINE_TIMER(timer, sh_wdt_ping, 0, 0); | 73 | static DEFINE_TIMER(timer, sh_wdt_ping, 0, 0); |
| 74 | static unsigned long next_heartbeat; | 74 | static unsigned long next_heartbeat; |
| 75 | static DEFINE_SPINLOCK(shwdt_lock); | ||
| 75 | 76 | ||
| 76 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ | 77 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ |
| 77 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ | 78 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ |
| @@ -86,6 +87,9 @@ static int nowayout = WATCHDOG_NOWAYOUT; | |||
| 86 | static void sh_wdt_start(void) | 87 | static void sh_wdt_start(void) |
| 87 | { | 88 | { |
| 88 | __u8 csr; | 89 | __u8 csr; |
| 90 | unsigned long flags; | ||
| 91 | |||
| 92 | spin_lock_irqsave(&wdt_lock, flags); | ||
| 89 | 93 | ||
| 90 | next_heartbeat = jiffies + (heartbeat * HZ); | 94 | next_heartbeat = jiffies + (heartbeat * HZ); |
| 91 | mod_timer(&timer, next_ping_period(clock_division_ratio)); | 95 | mod_timer(&timer, next_ping_period(clock_division_ratio)); |
| @@ -123,6 +127,7 @@ static void sh_wdt_start(void) | |||
| 123 | csr &= ~RSTCSR_RSTS; | 127 | csr &= ~RSTCSR_RSTS; |
| 124 | sh_wdt_write_rstcsr(csr); | 128 | sh_wdt_write_rstcsr(csr); |
| 125 | #endif | 129 | #endif |
| 130 | spin_unlock_irqrestore(&wdt_lock, flags); | ||
| 126 | } | 131 | } |
| 127 | 132 | ||
| 128 | /** | 133 | /** |
| @@ -132,12 +137,16 @@ static void sh_wdt_start(void) | |||
| 132 | static void sh_wdt_stop(void) | 137 | static void sh_wdt_stop(void) |
| 133 | { | 138 | { |
| 134 | __u8 csr; | 139 | __u8 csr; |
| 140 | unsigned long flags; | ||
| 141 | |||
| 142 | spin_lock_irqsave(&wdt_lock, flags); | ||
| 135 | 143 | ||
| 136 | del_timer(&timer); | 144 | del_timer(&timer); |
| 137 | 145 | ||
| 138 | csr = sh_wdt_read_csr(); | 146 | csr = sh_wdt_read_csr(); |
| 139 | csr &= ~WTCSR_TME; | 147 | csr &= ~WTCSR_TME; |
| 140 | sh_wdt_write_csr(csr); | 148 | sh_wdt_write_csr(csr); |
| 149 | spin_unlock_irqrestore(&wdt_lock, flags); | ||
| 141 | } | 150 | } |
| 142 | 151 | ||
| 143 | /** | 152 | /** |
| @@ -146,7 +155,11 @@ static void sh_wdt_stop(void) | |||
| 146 | */ | 155 | */ |
| 147 | static inline void sh_wdt_keepalive(void) | 156 | static inline void sh_wdt_keepalive(void) |
| 148 | { | 157 | { |
| 158 | unsigned long flags; | ||
| 159 | |||
| 160 | spin_lock_irqsave(&wdt_lock, flags); | ||
| 149 | next_heartbeat = jiffies + (heartbeat * HZ); | 161 | next_heartbeat = jiffies + (heartbeat * HZ); |
| 162 | spin_unlock_irqrestore(&wdt_lock, flags); | ||
| 150 | } | 163 | } |
| 151 | 164 | ||
| 152 | /** | 165 | /** |
| @@ -155,10 +168,14 @@ static inline void sh_wdt_keepalive(void) | |||
| 155 | */ | 168 | */ |
| 156 | static int sh_wdt_set_heartbeat(int t) | 169 | static int sh_wdt_set_heartbeat(int t) |
| 157 | { | 170 | { |
| 158 | if (unlikely((t < 1) || (t > 3600))) /* arbitrary upper limit */ | 171 | unsigned long flags; |
| 172 | |||
| 173 | if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */ | ||
| 159 | return -EINVAL; | 174 | return -EINVAL; |
| 160 | 175 | ||
| 176 | spin_lock_irqsave(&wdt_lock, flags); | ||
| 161 | heartbeat = t; | 177 | heartbeat = t; |
| 178 | spin_unlock_irqrestore(&wdt_lock, flags); | ||
| 162 | return 0; | 179 | return 0; |
| 163 | } | 180 | } |
| 164 | 181 | ||
| @@ -170,6 +187,9 @@ static int sh_wdt_set_heartbeat(int t) | |||
| 170 | */ | 187 | */ |
| 171 | static void sh_wdt_ping(unsigned long data) | 188 | static void sh_wdt_ping(unsigned long data) |
| 172 | { | 189 | { |
| 190 | unsigned long flags; | ||
| 191 | |||
| 192 | spin_lock_irqsave(&wdt_lock, flags); | ||
| 173 | if (time_before(jiffies, next_heartbeat)) { | 193 | if (time_before(jiffies, next_heartbeat)) { |
| 174 | __u8 csr; | 194 | __u8 csr; |
| 175 | 195 | ||
| @@ -183,6 +203,7 @@ static void sh_wdt_ping(unsigned long data) | |||
| 183 | } else | 203 | } else |
| 184 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping " | 204 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping " |
| 185 | "the watchdog\n"); | 205 | "the watchdog\n"); |
| 206 | spin_unlock_irqrestore(&wdt_lock, flags); | ||
| 186 | } | 207 | } |
| 187 | 208 | ||
| 188 | /** | 209 | /** |
| @@ -310,7 +331,6 @@ static int sh_wdt_mmap(struct file *file, struct vm_area_struct *vma) | |||
| 310 | 331 | ||
| 311 | /** | 332 | /** |
| 312 | * sh_wdt_ioctl - Query Device | 333 | * sh_wdt_ioctl - Query Device |
| 313 | * @inode: inode of device | ||
| 314 | * @file: file handle of device | 334 | * @file: file handle of device |
| 315 | * @cmd: watchdog command | 335 | * @cmd: watchdog command |
| 316 | * @arg: argument | 336 | * @arg: argument |
| @@ -318,53 +338,51 @@ static int sh_wdt_mmap(struct file *file, struct vm_area_struct *vma) | |||
| 318 | * Query basic information from the device or ping it, as outlined by the | 338 | * Query basic information from the device or ping it, as outlined by the |
| 319 | * watchdog API. | 339 | * watchdog API. |
| 320 | */ | 340 | */ |
| 321 | static int sh_wdt_ioctl(struct inode *inode, struct file *file, | 341 | static long sh_wdt_ioctl(struct file *file, unsigned int cmd, |
| 322 | unsigned int cmd, unsigned long arg) | 342 | unsigned long arg) |
| 323 | { | 343 | { |
| 324 | int new_heartbeat; | 344 | int new_heartbeat; |
| 325 | int options, retval = -EINVAL; | 345 | int options, retval = -EINVAL; |
| 326 | 346 | ||
| 327 | switch (cmd) { | 347 | switch (cmd) { |
| 328 | case WDIOC_GETSUPPORT: | 348 | case WDIOC_GETSUPPORT: |
| 329 | return copy_to_user((struct watchdog_info *)arg, | 349 | return copy_to_user((struct watchdog_info *)arg, |
| 330 | &sh_wdt_info, | 350 | &sh_wdt_info, sizeof(sh_wdt_info)) ? -EFAULT : 0; |
| 331 | sizeof(sh_wdt_info)) ? -EFAULT : 0; | 351 | case WDIOC_GETSTATUS: |
| 332 | case WDIOC_GETSTATUS: | 352 | case WDIOC_GETBOOTSTATUS: |
| 333 | case WDIOC_GETBOOTSTATUS: | 353 | return put_user(0, (int *)arg); |
| 334 | return put_user(0, (int *)arg); | 354 | case WDIOC_SETOPTIONS: |
| 335 | case WDIOC_KEEPALIVE: | 355 | if (get_user(options, (int *)arg)) |
| 336 | sh_wdt_keepalive(); | 356 | return -EFAULT; |
| 337 | return 0; | 357 | |
| 338 | case WDIOC_SETTIMEOUT: | 358 | if (options & WDIOS_DISABLECARD) { |
| 339 | if (get_user(new_heartbeat, (int *)arg)) | 359 | sh_wdt_stop(); |
| 340 | return -EFAULT; | 360 | retval = 0; |
| 341 | 361 | } | |
| 342 | if (sh_wdt_set_heartbeat(new_heartbeat)) | ||
| 343 | return -EINVAL; | ||
| 344 | |||
| 345 | sh_wdt_keepalive(); | ||
| 346 | /* Fall */ | ||
| 347 | case WDIOC_GETTIMEOUT: | ||
| 348 | return put_user(heartbeat, (int *)arg); | ||
| 349 | case WDIOC_SETOPTIONS: | ||
| 350 | if (get_user(options, (int *)arg)) | ||
| 351 | return -EFAULT; | ||
| 352 | |||
| 353 | if (options & WDIOS_DISABLECARD) { | ||
| 354 | sh_wdt_stop(); | ||
| 355 | retval = 0; | ||
| 356 | } | ||
| 357 | 362 | ||
| 358 | if (options & WDIOS_ENABLECARD) { | 363 | if (options & WDIOS_ENABLECARD) { |
| 359 | sh_wdt_start(); | 364 | sh_wdt_start(); |
| 360 | retval = 0; | 365 | retval = 0; |
| 361 | } | 366 | } |
| 362 | 367 | ||
| 363 | return retval; | 368 | return retval; |
| 364 | default: | 369 | case WDIOC_KEEPALIVE: |
| 365 | return -ENOTTY; | 370 | sh_wdt_keepalive(); |
| 366 | } | 371 | return 0; |
| 372 | case WDIOC_SETTIMEOUT: | ||
| 373 | if (get_user(new_heartbeat, (int *)arg)) | ||
| 374 | return -EFAULT; | ||
| 375 | |||
| 376 | if (sh_wdt_set_heartbeat(new_heartbeat)) | ||
| 377 | return -EINVAL; | ||
| 367 | 378 | ||
| 379 | sh_wdt_keepalive(); | ||
| 380 | /* Fall */ | ||
| 381 | case WDIOC_GETTIMEOUT: | ||
| 382 | return put_user(heartbeat, (int *)arg); | ||
| 383 | default: | ||
| 384 | return -ENOTTY; | ||
| 385 | } | ||
| 368 | return 0; | 386 | return 0; |
| 369 | } | 387 | } |
| 370 | 388 | ||
| @@ -390,13 +408,13 @@ static const struct file_operations sh_wdt_fops = { | |||
| 390 | .owner = THIS_MODULE, | 408 | .owner = THIS_MODULE, |
| 391 | .llseek = no_llseek, | 409 | .llseek = no_llseek, |
| 392 | .write = sh_wdt_write, | 410 | .write = sh_wdt_write, |
| 393 | .ioctl = sh_wdt_ioctl, | 411 | .unlocked_ioctl = sh_wdt_ioctl, |
| 394 | .open = sh_wdt_open, | 412 | .open = sh_wdt_open, |
| 395 | .release = sh_wdt_close, | 413 | .release = sh_wdt_close, |
| 396 | .mmap = sh_wdt_mmap, | 414 | .mmap = sh_wdt_mmap, |
| 397 | }; | 415 | }; |
| 398 | 416 | ||
| 399 | static struct watchdog_info sh_wdt_info = { | 417 | static const struct watchdog_info sh_wdt_info = { |
| 400 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | | 418 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
| 401 | WDIOF_MAGICCLOSE, | 419 | WDIOF_MAGICCLOSE, |
| 402 | .firmware_version = 1, | 420 | .firmware_version = 1, |
| @@ -422,30 +440,33 @@ static int __init sh_wdt_init(void) | |||
| 422 | { | 440 | { |
| 423 | int rc; | 441 | int rc; |
| 424 | 442 | ||
| 425 | if ((clock_division_ratio < 0x5) || (clock_division_ratio > 0x7)) { | 443 | if (clock_division_ratio < 0x5 || clock_division_ratio > 0x7) { |
| 426 | clock_division_ratio = WTCSR_CKS_4096; | 444 | clock_division_ratio = WTCSR_CKS_4096; |
| 427 | printk(KERN_INFO PFX "clock_division_ratio value must " | 445 | printk(KERN_INFO PFX |
| 428 | "be 0x5<=x<=0x7, using %d\n", clock_division_ratio); | 446 | "clock_division_ratio value must be 0x5<=x<=0x7, using %d\n", |
| 447 | clock_division_ratio); | ||
| 429 | } | 448 | } |
| 430 | 449 | ||
| 431 | rc = sh_wdt_set_heartbeat(heartbeat); | 450 | rc = sh_wdt_set_heartbeat(heartbeat); |
| 432 | if (unlikely(rc)) { | 451 | if (unlikely(rc)) { |
| 433 | heartbeat = WATCHDOG_HEARTBEAT; | 452 | heartbeat = WATCHDOG_HEARTBEAT; |
| 434 | printk(KERN_INFO PFX "heartbeat value must " | 453 | printk(KERN_INFO PFX |
| 435 | "be 1<=x<=3600, using %d\n", heartbeat); | 454 | "heartbeat value must be 1<=x<=3600, using %d\n", |
| 455 | heartbeat); | ||
| 436 | } | 456 | } |
| 437 | 457 | ||
| 438 | rc = register_reboot_notifier(&sh_wdt_notifier); | 458 | rc = register_reboot_notifier(&sh_wdt_notifier); |
| 439 | if (unlikely(rc)) { | 459 | if (unlikely(rc)) { |
| 440 | printk(KERN_ERR PFX "Can't register reboot notifier (err=%d)\n", | 460 | printk(KERN_ERR PFX |
| 441 | rc); | 461 | "Can't register reboot notifier (err=%d)\n", rc); |
| 442 | return rc; | 462 | return rc; |
| 443 | } | 463 | } |
| 444 | 464 | ||
| 445 | rc = misc_register(&sh_wdt_miscdev); | 465 | rc = misc_register(&sh_wdt_miscdev); |
| 446 | if (unlikely(rc)) { | 466 | if (unlikely(rc)) { |
| 447 | printk(KERN_ERR PFX "Can't register miscdev on " | 467 | printk(KERN_ERR PFX |
| 448 | "minor=%d (err=%d)\n", sh_wdt_miscdev.minor, rc); | 468 | "Can't register miscdev on minor=%d (err=%d)\n", |
| 469 | sh_wdt_miscdev.minor, rc); | ||
| 449 | unregister_reboot_notifier(&sh_wdt_notifier); | 470 | unregister_reboot_notifier(&sh_wdt_notifier); |
| 450 | return rc; | 471 | return rc; |
| 451 | } | 472 | } |
| @@ -476,10 +497,14 @@ module_param(clock_division_ratio, int, 0); | |||
| 476 | MODULE_PARM_DESC(clock_division_ratio, "Clock division ratio. Valid ranges are from 0x5 (1.31ms) to 0x7 (5.25ms). (default=" __MODULE_STRING(clock_division_ratio) ")"); | 497 | MODULE_PARM_DESC(clock_division_ratio, "Clock division ratio. Valid ranges are from 0x5 (1.31ms) to 0x7 (5.25ms). (default=" __MODULE_STRING(clock_division_ratio) ")"); |
| 477 | 498 | ||
| 478 | module_param(heartbeat, int, 0); | 499 | module_param(heartbeat, int, 0); |
| 479 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (1<=heartbeat<=3600, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | 500 | MODULE_PARM_DESC(heartbeat, |
| 501 | "Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default=" | ||
| 502 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | ||
| 480 | 503 | ||
| 481 | module_param(nowayout, int, 0); | 504 | module_param(nowayout, int, 0); |
| 482 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 505 | MODULE_PARM_DESC(nowayout, |
| 506 | "Watchdog cannot be stopped once started (default=" | ||
| 507 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 483 | 508 | ||
| 484 | module_init(sh_wdt_init); | 509 | module_init(sh_wdt_init); |
| 485 | module_exit(sh_wdt_exit); | 510 | module_exit(sh_wdt_exit); |
diff --git a/drivers/watchdog/smsc37b787_wdt.c b/drivers/watchdog/smsc37b787_wdt.c index 5d2b5ba61414..988ff1d5b4be 100644 --- a/drivers/watchdog/smsc37b787_wdt.c +++ b/drivers/watchdog/smsc37b787_wdt.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | * History: | 18 | * History: |
| 19 | * 2003 - Created version 1.0 for Linux 2.4.x. | 19 | * 2003 - Created version 1.0 for Linux 2.4.x. |
| 20 | * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE | 20 | * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE |
| 21 | * features. Released version 1.1 | 21 | * features. Released version 1.1 |
| 22 | * | 22 | * |
| 23 | * Theory of operation: | 23 | * Theory of operation: |
| 24 | * | 24 | * |
| @@ -55,9 +55,9 @@ | |||
| 55 | #include <linux/reboot.h> | 55 | #include <linux/reboot.h> |
| 56 | #include <linux/init.h> | 56 | #include <linux/init.h> |
| 57 | #include <linux/spinlock.h> | 57 | #include <linux/spinlock.h> |
| 58 | #include <linux/io.h> | ||
| 59 | #include <linux/uaccess.h> | ||
| 58 | 60 | ||
| 59 | #include <asm/io.h> | ||
| 60 | #include <asm/uaccess.h> | ||
| 61 | #include <asm/system.h> | 61 | #include <asm/system.h> |
| 62 | 62 | ||
| 63 | /* enable support for minutes as units? */ | 63 | /* enable support for minutes as units? */ |
| @@ -71,15 +71,15 @@ | |||
| 71 | #define UNIT_MINUTE 1 | 71 | #define UNIT_MINUTE 1 |
| 72 | 72 | ||
| 73 | #define MODNAME "smsc37b787_wdt: " | 73 | #define MODNAME "smsc37b787_wdt: " |
| 74 | #define VERSION "1.1" | 74 | #define VERSION "1.1" |
| 75 | 75 | ||
| 76 | #define IOPORT 0x3F0 | 76 | #define IOPORT 0x3F0 |
| 77 | #define IOPORT_SIZE 2 | 77 | #define IOPORT_SIZE 2 |
| 78 | #define IODEV_NO 8 | 78 | #define IODEV_NO 8 |
| 79 | 79 | ||
| 80 | static int unit = UNIT_SECOND; /* timer's unit */ | 80 | static int unit = UNIT_SECOND; /* timer's unit */ |
| 81 | static int timeout = 60; /* timeout value: default is 60 "units" */ | 81 | static int timeout = 60; /* timeout value: default is 60 "units" */ |
| 82 | static unsigned long timer_enabled = 0; /* is the timer enabled? */ | 82 | static unsigned long timer_enabled; /* is the timer enabled? */ |
| 83 | 83 | ||
| 84 | static char expect_close; /* is the close expected? */ | 84 | static char expect_close; /* is the close expected? */ |
| 85 | 85 | ||
| @@ -93,114 +93,121 @@ static int nowayout = WATCHDOG_NOWAYOUT; | |||
| 93 | 93 | ||
| 94 | static inline void open_io_config(void) | 94 | static inline void open_io_config(void) |
| 95 | { | 95 | { |
| 96 | outb(0x55, IOPORT); | 96 | outb(0x55, IOPORT); |
| 97 | mdelay(1); | 97 | mdelay(1); |
| 98 | outb(0x55, IOPORT); | 98 | outb(0x55, IOPORT); |
| 99 | } | 99 | } |
| 100 | 100 | ||
| 101 | /* lock the IO chip */ | 101 | /* lock the IO chip */ |
| 102 | static inline void close_io_config(void) | 102 | static inline void close_io_config(void) |
| 103 | { | 103 | { |
| 104 | outb(0xAA, IOPORT); | 104 | outb(0xAA, IOPORT); |
| 105 | } | 105 | } |
| 106 | 106 | ||
| 107 | /* select the IO device */ | 107 | /* select the IO device */ |
| 108 | static inline void select_io_device(unsigned char devno) | 108 | static inline void select_io_device(unsigned char devno) |
| 109 | { | 109 | { |
| 110 | outb(0x07, IOPORT); | 110 | outb(0x07, IOPORT); |
| 111 | outb(devno, IOPORT+1); | 111 | outb(devno, IOPORT+1); |
| 112 | } | 112 | } |
| 113 | 113 | ||
| 114 | /* write to the control register */ | 114 | /* write to the control register */ |
| 115 | static inline void write_io_cr(unsigned char reg, unsigned char data) | 115 | static inline void write_io_cr(unsigned char reg, unsigned char data) |
| 116 | { | 116 | { |
| 117 | outb(reg, IOPORT); | 117 | outb(reg, IOPORT); |
| 118 | outb(data, IOPORT+1); | 118 | outb(data, IOPORT+1); |
| 119 | } | 119 | } |
| 120 | 120 | ||
| 121 | /* read from the control register */ | 121 | /* read from the control register */ |
| 122 | static inline char read_io_cr(unsigned char reg) | 122 | static inline char read_io_cr(unsigned char reg) |
| 123 | { | 123 | { |
| 124 | outb(reg, IOPORT); | 124 | outb(reg, IOPORT); |
| 125 | return inb(IOPORT+1); | 125 | return inb(IOPORT+1); |
| 126 | } | 126 | } |
| 127 | 127 | ||
| 128 | /* -- Medium level functions ------------------------------------*/ | 128 | /* -- Medium level functions ------------------------------------*/ |
| 129 | 129 | ||
| 130 | static inline void gpio_bit12(unsigned char reg) | 130 | static inline void gpio_bit12(unsigned char reg) |
| 131 | { | 131 | { |
| 132 | // -- General Purpose I/O Bit 1.2 -- | 132 | /* -- General Purpose I/O Bit 1.2 -- |
| 133 | // Bit 0, In/Out: 0 = Output, 1 = Input | 133 | * Bit 0, In/Out: 0 = Output, 1 = Input |
| 134 | // Bit 1, Polarity: 0 = No Invert, 1 = Invert | 134 | * Bit 1, Polarity: 0 = No Invert, 1 = Invert |
| 135 | // Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable | 135 | * Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable |
| 136 | // Bit 3/4, Function select: 00 = GPI/O, 01 = WDT, 10 = P17, | 136 | * Bit 3/4, Function select: 00 = GPI/O, 01 = WDT, 10 = P17, |
| 137 | // 11 = Either Edge Triggered Intr. 2 | 137 | * 11 = Either Edge Triggered Intr. 2 |
| 138 | // Bit 5/6 (Reserved) | 138 | * Bit 5/6 (Reserved) |
| 139 | // Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain | 139 | * Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain |
| 140 | write_io_cr(0xE2, reg); | 140 | */ |
| 141 | write_io_cr(0xE2, reg); | ||
| 141 | } | 142 | } |
| 142 | 143 | ||
| 143 | static inline void gpio_bit13(unsigned char reg) | 144 | static inline void gpio_bit13(unsigned char reg) |
| 144 | { | 145 | { |
| 145 | // -- General Purpose I/O Bit 1.3 -- | 146 | /* -- General Purpose I/O Bit 1.3 -- |
| 146 | // Bit 0, In/Out: 0 = Output, 1 = Input | 147 | * Bit 0, In/Out: 0 = Output, 1 = Input |
| 147 | // Bit 1, Polarity: 0 = No Invert, 1 = Invert | 148 | * Bit 1, Polarity: 0 = No Invert, 1 = Invert |
| 148 | // Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable | 149 | * Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable |
| 149 | // Bit 3, Function select: 0 = GPI/O, 1 = LED | 150 | * Bit 3, Function select: 0 = GPI/O, 1 = LED |
| 150 | // Bit 4-6 (Reserved) | 151 | * Bit 4-6 (Reserved) |
| 151 | // Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain | 152 | * Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain |
| 152 | write_io_cr(0xE3, reg); | 153 | */ |
| 154 | write_io_cr(0xE3, reg); | ||
| 153 | } | 155 | } |
| 154 | 156 | ||
| 155 | static inline void wdt_timer_units(unsigned char new_units) | 157 | static inline void wdt_timer_units(unsigned char new_units) |
| 156 | { | 158 | { |
| 157 | // -- Watchdog timer units -- | 159 | /* -- Watchdog timer units -- |
| 158 | // Bit 0-6 (Reserved) | 160 | * Bit 0-6 (Reserved) |
| 159 | // Bit 7, WDT Time-out Value Units Select | 161 | * Bit 7, WDT Time-out Value Units Select |
| 160 | // (0 = Minutes, 1 = Seconds) | 162 | * (0 = Minutes, 1 = Seconds) |
| 161 | write_io_cr(0xF1, new_units); | 163 | */ |
| 164 | write_io_cr(0xF1, new_units); | ||
| 162 | } | 165 | } |
| 163 | 166 | ||
| 164 | static inline void wdt_timeout_value(unsigned char new_timeout) | 167 | static inline void wdt_timeout_value(unsigned char new_timeout) |
| 165 | { | 168 | { |
| 166 | // -- Watchdog Timer Time-out Value -- | 169 | /* -- Watchdog Timer Time-out Value -- |
| 167 | // Bit 0-7 Binary coded units (0=Disabled, 1..255) | 170 | * Bit 0-7 Binary coded units (0=Disabled, 1..255) |
| 168 | write_io_cr(0xF2, new_timeout); | 171 | */ |
| 172 | write_io_cr(0xF2, new_timeout); | ||
| 169 | } | 173 | } |
| 170 | 174 | ||
| 171 | static inline void wdt_timer_conf(unsigned char conf) | 175 | static inline void wdt_timer_conf(unsigned char conf) |
| 172 | { | 176 | { |
| 173 | // -- Watchdog timer configuration -- | 177 | /* -- Watchdog timer configuration -- |
| 174 | // Bit 0 Joystick enable: 0* = No Reset, 1 = Reset WDT upon Gameport I/O | 178 | * Bit 0 Joystick enable: 0* = No Reset, 1 = Reset WDT upon |
| 175 | // Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr. | 179 | * Gameport I/O |
| 176 | // Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr. | 180 | * Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr. |
| 177 | // Bit 3 Reset the timer | 181 | * Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr |
| 178 | // (Wrong in SMsC documentation? Given as: PowerLED Timout Enabled) | 182 | * Bit 3 Reset the timer |
| 179 | // Bit 4-7 WDT Interrupt Mapping: (0000* = Disabled, | 183 | * (Wrong in SMsC documentation? Given as: PowerLED Timout |
| 180 | // 0001=IRQ1, 0010=(Invalid), 0011=IRQ3 to 1111=IRQ15) | 184 | * Enabled) |
| 181 | write_io_cr(0xF3, conf); | 185 | * Bit 4-7 WDT Interrupt Mapping: (0000* = Disabled, |
| 186 | * 0001=IRQ1, 0010=(Invalid), 0011=IRQ3 to 1111=IRQ15) | ||
| 187 | */ | ||
| 188 | write_io_cr(0xF3, conf); | ||
| 182 | } | 189 | } |
| 183 | 190 | ||
| 184 | static inline void wdt_timer_ctrl(unsigned char reg) | 191 | static inline void wdt_timer_ctrl(unsigned char reg) |
| 185 | { | 192 | { |
| 186 | // -- Watchdog timer control -- | 193 | /* -- Watchdog timer control -- |
| 187 | // Bit 0 Status Bit: 0 = Timer counting, 1 = Timeout occured | 194 | * Bit 0 Status Bit: 0 = Timer counting, 1 = Timeout occured |
| 188 | // Bit 1 Power LED Toggle: 0 = Disable Toggle, 1 = Toggle at 1 Hz | 195 | * Bit 1 Power LED Toggle: 0 = Disable Toggle, 1 = Toggle at 1 Hz |
| 189 | // Bit 2 Force Timeout: 1 = Forces WD timeout event (self-cleaning) | 196 | * Bit 2 Force Timeout: 1 = Forces WD timeout event (self-cleaning) |
| 190 | // Bit 3 P20 Force Timeout enabled: | 197 | * Bit 3 P20 Force Timeout enabled: |
| 191 | // 0 = P20 activity does not generate the WD timeout event | 198 | * 0 = P20 activity does not generate the WD timeout event |
| 192 | // 1 = P20 Allows rising edge of P20, from the keyboard | 199 | * 1 = P20 Allows rising edge of P20, from the keyboard |
| 193 | // controller, to force the WD timeout event. | 200 | * controller, to force the WD timeout event. |
| 194 | // Bit 4 (Reserved) | 201 | * Bit 4 (Reserved) |
| 195 | // -- Soft power management -- | 202 | * -- Soft power management -- |
| 196 | // Bit 5 Stop Counter: 1 = Stop software power down counter | 203 | * Bit 5 Stop Counter: 1 = Stop software power down counter |
| 197 | // set via register 0xB8, (self-cleaning) | 204 | * set via register 0xB8, (self-cleaning) |
| 198 | // (Upon read: 0 = Counter running, 1 = Counter stopped) | 205 | * (Upon read: 0 = Counter running, 1 = Counter stopped) |
| 199 | // Bit 6 Restart Counter: 1 = Restart software power down counter | 206 | * Bit 6 Restart Counter: 1 = Restart software power down counter |
| 200 | // set via register 0xB8, (self-cleaning) | 207 | * set via register 0xB8, (self-cleaning) |
| 201 | // Bit 7 SPOFF: 1 = Force software power down (self-cleaning) | 208 | * Bit 7 SPOFF: 1 = Force software power down (self-cleaning) |
| 202 | 209 | */ | |
| 203 | write_io_cr(0xF4, reg); | 210 | write_io_cr(0xF4, reg); |
| 204 | } | 211 | } |
| 205 | 212 | ||
| 206 | /* -- Higher level functions ------------------------------------*/ | 213 | /* -- Higher level functions ------------------------------------*/ |
| @@ -209,33 +216,34 @@ static inline void wdt_timer_ctrl(unsigned char reg) | |||
| 209 | 216 | ||
| 210 | static void wb_smsc_wdt_initialize(void) | 217 | static void wb_smsc_wdt_initialize(void) |
| 211 | { | 218 | { |
| 212 | unsigned char old; | 219 | unsigned char old; |
| 213 | 220 | ||
| 214 | spin_lock(&io_lock); | 221 | spin_lock(&io_lock); |
| 215 | open_io_config(); | 222 | open_io_config(); |
| 216 | select_io_device(IODEV_NO); | 223 | select_io_device(IODEV_NO); |
| 217 | 224 | ||
| 218 | // enable the watchdog | 225 | /* enable the watchdog */ |
| 219 | gpio_bit13(0x08); // Select pin 80 = LED not GPIO | 226 | gpio_bit13(0x08); /* Select pin 80 = LED not GPIO */ |
| 220 | gpio_bit12(0x0A); // Set pin 79 = WDT not GPIO/Output/Polarity=Invert | 227 | gpio_bit12(0x0A); /* Set pin 79 = WDT not |
| 228 | GPIO/Output/Polarity=Invert */ | ||
| 229 | /* disable the timeout */ | ||
| 230 | wdt_timeout_value(0); | ||
| 221 | 231 | ||
| 222 | // disable the timeout | 232 | /* reset control register */ |
| 223 | wdt_timeout_value(0); | 233 | wdt_timer_ctrl(0x00); |
| 224 | 234 | ||
| 225 | // reset control register | 235 | /* reset configuration register */ |
| 226 | wdt_timer_ctrl(0x00); | ||
| 227 | |||
| 228 | // reset configuration register | ||
| 229 | wdt_timer_conf(0x00); | 236 | wdt_timer_conf(0x00); |
| 230 | 237 | ||
| 231 | // read old (timer units) register | 238 | /* read old (timer units) register */ |
| 232 | old = read_io_cr(0xF1) & 0x7F; | 239 | old = read_io_cr(0xF1) & 0x7F; |
| 233 | if (unit == UNIT_SECOND) old |= 0x80; // set to seconds | 240 | if (unit == UNIT_SECOND) |
| 241 | old |= 0x80; /* set to seconds */ | ||
| 234 | 242 | ||
| 235 | // set the watchdog timer units | 243 | /* set the watchdog timer units */ |
| 236 | wdt_timer_units(old); | 244 | wdt_timer_units(old); |
| 237 | 245 | ||
| 238 | close_io_config(); | 246 | close_io_config(); |
| 239 | spin_unlock(&io_lock); | 247 | spin_unlock(&io_lock); |
| 240 | } | 248 | } |
| 241 | 249 | ||
| @@ -244,23 +252,23 @@ static void wb_smsc_wdt_initialize(void) | |||
| 244 | static void wb_smsc_wdt_shutdown(void) | 252 | static void wb_smsc_wdt_shutdown(void) |
| 245 | { | 253 | { |
| 246 | spin_lock(&io_lock); | 254 | spin_lock(&io_lock); |
| 247 | open_io_config(); | 255 | open_io_config(); |
| 248 | select_io_device(IODEV_NO); | 256 | select_io_device(IODEV_NO); |
| 249 | 257 | ||
| 250 | // disable the watchdog | 258 | /* disable the watchdog */ |
| 251 | gpio_bit13(0x09); | 259 | gpio_bit13(0x09); |
| 252 | gpio_bit12(0x09); | 260 | gpio_bit12(0x09); |
| 253 | 261 | ||
| 254 | // reset watchdog config register | 262 | /* reset watchdog config register */ |
| 255 | wdt_timer_conf(0x00); | 263 | wdt_timer_conf(0x00); |
| 256 | 264 | ||
| 257 | // reset watchdog control register | 265 | /* reset watchdog control register */ |
| 258 | wdt_timer_ctrl(0x00); | 266 | wdt_timer_ctrl(0x00); |
| 259 | 267 | ||
| 260 | // disable timeout | 268 | /* disable timeout */ |
| 261 | wdt_timeout_value(0x00); | 269 | wdt_timeout_value(0x00); |
| 262 | 270 | ||
| 263 | close_io_config(); | 271 | close_io_config(); |
| 264 | spin_unlock(&io_lock); | 272 | spin_unlock(&io_lock); |
| 265 | } | 273 | } |
| 266 | 274 | ||
| @@ -269,16 +277,16 @@ static void wb_smsc_wdt_shutdown(void) | |||
| 269 | static void wb_smsc_wdt_set_timeout(unsigned char new_timeout) | 277 | static void wb_smsc_wdt_set_timeout(unsigned char new_timeout) |
| 270 | { | 278 | { |
| 271 | spin_lock(&io_lock); | 279 | spin_lock(&io_lock); |
| 272 | open_io_config(); | 280 | open_io_config(); |
| 273 | select_io_device(IODEV_NO); | 281 | select_io_device(IODEV_NO); |
| 274 | 282 | ||
| 275 | // set Power LED to blink, if we enable the timeout | 283 | /* set Power LED to blink, if we enable the timeout */ |
| 276 | wdt_timer_ctrl((new_timeout == 0) ? 0x00 : 0x02); | 284 | wdt_timer_ctrl((new_timeout == 0) ? 0x00 : 0x02); |
| 277 | 285 | ||
| 278 | // set timeout value | 286 | /* set timeout value */ |
| 279 | wdt_timeout_value(new_timeout); | 287 | wdt_timeout_value(new_timeout); |
| 280 | 288 | ||
| 281 | close_io_config(); | 289 | close_io_config(); |
| 282 | spin_unlock(&io_lock); | 290 | spin_unlock(&io_lock); |
| 283 | } | 291 | } |
| 284 | 292 | ||
| @@ -286,32 +294,32 @@ static void wb_smsc_wdt_set_timeout(unsigned char new_timeout) | |||
| 286 | 294 | ||
| 287 | static unsigned char wb_smsc_wdt_get_timeout(void) | 295 | static unsigned char wb_smsc_wdt_get_timeout(void) |
| 288 | { | 296 | { |
| 289 | unsigned char set_timeout; | 297 | unsigned char set_timeout; |
| 290 | 298 | ||
| 291 | spin_lock(&io_lock); | 299 | spin_lock(&io_lock); |
| 292 | open_io_config(); | 300 | open_io_config(); |
| 293 | select_io_device(IODEV_NO); | 301 | select_io_device(IODEV_NO); |
| 294 | set_timeout = read_io_cr(0xF2); | 302 | set_timeout = read_io_cr(0xF2); |
| 295 | close_io_config(); | 303 | close_io_config(); |
| 296 | spin_unlock(&io_lock); | 304 | spin_unlock(&io_lock); |
| 297 | 305 | ||
| 298 | return set_timeout; | 306 | return set_timeout; |
| 299 | } | 307 | } |
| 300 | 308 | ||
| 301 | /* disable watchdog */ | 309 | /* disable watchdog */ |
| 302 | 310 | ||
| 303 | static void wb_smsc_wdt_disable(void) | 311 | static void wb_smsc_wdt_disable(void) |
| 304 | { | 312 | { |
| 305 | // set the timeout to 0 to disable the watchdog | 313 | /* set the timeout to 0 to disable the watchdog */ |
| 306 | wb_smsc_wdt_set_timeout(0); | 314 | wb_smsc_wdt_set_timeout(0); |
| 307 | } | 315 | } |
| 308 | 316 | ||
| 309 | /* enable watchdog by setting the current timeout */ | 317 | /* enable watchdog by setting the current timeout */ |
| 310 | 318 | ||
| 311 | static void wb_smsc_wdt_enable(void) | 319 | static void wb_smsc_wdt_enable(void) |
| 312 | { | 320 | { |
| 313 | // set the current timeout... | 321 | /* set the current timeout... */ |
| 314 | wb_smsc_wdt_set_timeout(timeout); | 322 | wb_smsc_wdt_set_timeout(timeout); |
| 315 | } | 323 | } |
| 316 | 324 | ||
| 317 | /* reset the timer */ | 325 | /* reset the timer */ |
| @@ -319,14 +327,14 @@ static void wb_smsc_wdt_enable(void) | |||
| 319 | static void wb_smsc_wdt_reset_timer(void) | 327 | static void wb_smsc_wdt_reset_timer(void) |
| 320 | { | 328 | { |
| 321 | spin_lock(&io_lock); | 329 | spin_lock(&io_lock); |
| 322 | open_io_config(); | 330 | open_io_config(); |
| 323 | select_io_device(IODEV_NO); | 331 | select_io_device(IODEV_NO); |
| 324 | 332 | ||
| 325 | // reset the timer | 333 | /* reset the timer */ |
| 326 | wdt_timeout_value(timeout); | 334 | wdt_timeout_value(timeout); |
| 327 | wdt_timer_conf(0x08); | 335 | wdt_timer_conf(0x08); |
| 328 | 336 | ||
| 329 | close_io_config(); | 337 | close_io_config(); |
| 330 | spin_unlock(&io_lock); | 338 | spin_unlock(&io_lock); |
| 331 | } | 339 | } |
| 332 | 340 | ||
| @@ -355,7 +363,9 @@ static int wb_smsc_wdt_open(struct inode *inode, struct file *file) | |||
| 355 | /* Reload and activate timer */ | 363 | /* Reload and activate timer */ |
| 356 | wb_smsc_wdt_enable(); | 364 | wb_smsc_wdt_enable(); |
| 357 | 365 | ||
| 358 | printk(KERN_INFO MODNAME "Watchdog enabled. Timeout set to %d %s.\n", timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); | 366 | printk(KERN_INFO MODNAME |
| 367 | "Watchdog enabled. Timeout set to %d %s.\n", | ||
| 368 | timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); | ||
| 359 | 369 | ||
| 360 | return nonseekable_open(inode, file); | 370 | return nonseekable_open(inode, file); |
| 361 | } | 371 | } |
| @@ -367,10 +377,12 @@ static int wb_smsc_wdt_release(struct inode *inode, struct file *file) | |||
| 367 | /* Shut off the timer. */ | 377 | /* Shut off the timer. */ |
| 368 | 378 | ||
| 369 | if (expect_close == 42) { | 379 | if (expect_close == 42) { |
| 370 | wb_smsc_wdt_disable(); | 380 | wb_smsc_wdt_disable(); |
| 371 | printk(KERN_INFO MODNAME "Watchdog disabled, sleeping again...\n"); | 381 | printk(KERN_INFO MODNAME |
| 382 | "Watchdog disabled, sleeping again...\n"); | ||
| 372 | } else { | 383 | } else { |
| 373 | printk(KERN_CRIT MODNAME "Unexpected close, not stopping watchdog!\n"); | 384 | printk(KERN_CRIT MODNAME |
| 385 | "Unexpected close, not stopping watchdog!\n"); | ||
| 374 | wb_smsc_wdt_reset_timer(); | 386 | wb_smsc_wdt_reset_timer(); |
| 375 | } | 387 | } |
| 376 | 388 | ||
| @@ -392,10 +404,11 @@ static ssize_t wb_smsc_wdt_write(struct file *file, const char __user *data, | |||
| 392 | /* reset expect flag */ | 404 | /* reset expect flag */ |
| 393 | expect_close = 0; | 405 | expect_close = 0; |
| 394 | 406 | ||
| 395 | /* scan to see whether or not we got the magic character */ | 407 | /* scan to see whether or not we got the |
| 408 | magic character */ | ||
| 396 | for (i = 0; i != len; i++) { | 409 | for (i = 0; i != len; i++) { |
| 397 | char c; | 410 | char c; |
| 398 | if (get_user(c, data+i)) | 411 | if (get_user(c, data + i)) |
| 399 | return -EFAULT; | 412 | return -EFAULT; |
| 400 | if (c == 'V') | 413 | if (c == 'V') |
| 401 | expect_close = 42; | 414 | expect_close = 42; |
| @@ -410,8 +423,8 @@ static ssize_t wb_smsc_wdt_write(struct file *file, const char __user *data, | |||
| 410 | 423 | ||
| 411 | /* ioctl => control interface */ | 424 | /* ioctl => control interface */ |
| 412 | 425 | ||
| 413 | static int wb_smsc_wdt_ioctl(struct inode *inode, struct file *file, | 426 | static long wb_smsc_wdt_ioctl(struct file *file, |
| 414 | unsigned int cmd, unsigned long arg) | 427 | unsigned int cmd, unsigned long arg) |
| 415 | { | 428 | { |
| 416 | int new_timeout; | 429 | int new_timeout; |
| 417 | 430 | ||
| @@ -420,89 +433,73 @@ static int wb_smsc_wdt_ioctl(struct inode *inode, struct file *file, | |||
| 420 | int __user *i; | 433 | int __user *i; |
| 421 | } uarg; | 434 | } uarg; |
| 422 | 435 | ||
| 423 | static struct watchdog_info ident = { | 436 | static const struct watchdog_info ident = { |
| 424 | .options = WDIOF_KEEPALIVEPING | | 437 | .options = WDIOF_KEEPALIVEPING | |
| 425 | WDIOF_SETTIMEOUT | | 438 | WDIOF_SETTIMEOUT | |
| 426 | WDIOF_MAGICCLOSE, | 439 | WDIOF_MAGICCLOSE, |
| 427 | .firmware_version = 0, | 440 | .firmware_version = 0, |
| 428 | .identity = "SMsC 37B787 Watchdog" | 441 | .identity = "SMsC 37B787 Watchdog", |
| 429 | }; | 442 | }; |
| 430 | 443 | ||
| 431 | uarg.i = (int __user *)arg; | 444 | uarg.i = (int __user *)arg; |
| 432 | 445 | ||
| 433 | switch (cmd) { | 446 | switch (cmd) { |
| 434 | default: | 447 | case WDIOC_GETSUPPORT: |
| 435 | return -ENOTTY; | 448 | return copy_to_user(uarg.ident, &ident, sizeof(ident)) |
| 436 | 449 | ? -EFAULT : 0; | |
| 437 | case WDIOC_GETSUPPORT: | 450 | case WDIOC_GETSTATUS: |
| 438 | return copy_to_user(uarg.ident, &ident, | 451 | return put_user(wb_smsc_wdt_status(), uarg.i); |
| 439 | sizeof(ident)) ? -EFAULT : 0; | 452 | case WDIOC_GETBOOTSTATUS: |
| 440 | 453 | return put_user(0, uarg.i); | |
| 441 | case WDIOC_GETSTATUS: | 454 | case WDIOC_SETOPTIONS: |
| 442 | return put_user(wb_smsc_wdt_status(), uarg.i); | 455 | { |
| 443 | 456 | int options, retval = -EINVAL; | |
| 444 | case WDIOC_GETBOOTSTATUS: | ||
| 445 | return put_user(0, uarg.i); | ||
| 446 | |||
| 447 | case WDIOC_KEEPALIVE: | ||
| 448 | wb_smsc_wdt_reset_timer(); | ||
| 449 | return 0; | ||
| 450 | |||
| 451 | case WDIOC_SETTIMEOUT: | ||
| 452 | if (get_user(new_timeout, uarg.i)) | ||
| 453 | return -EFAULT; | ||
| 454 | |||
| 455 | // the API states this is given in secs | ||
| 456 | if (unit == UNIT_MINUTE) | ||
| 457 | new_timeout /= 60; | ||
| 458 | |||
| 459 | if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) | ||
| 460 | return -EINVAL; | ||
| 461 | |||
| 462 | timeout = new_timeout; | ||
| 463 | wb_smsc_wdt_set_timeout(timeout); | ||
| 464 | |||
| 465 | // fall through and return the new timeout... | ||
| 466 | |||
| 467 | case WDIOC_GETTIMEOUT: | ||
| 468 | |||
| 469 | new_timeout = timeout; | ||
| 470 | |||
| 471 | if (unit == UNIT_MINUTE) | ||
| 472 | new_timeout *= 60; | ||
| 473 | |||
| 474 | return put_user(new_timeout, uarg.i); | ||
| 475 | |||
| 476 | case WDIOC_SETOPTIONS: | ||
| 477 | { | ||
| 478 | int options, retval = -EINVAL; | ||
| 479 | |||
| 480 | if (get_user(options, uarg.i)) | ||
| 481 | return -EFAULT; | ||
| 482 | |||
| 483 | if (options & WDIOS_DISABLECARD) { | ||
| 484 | wb_smsc_wdt_disable(); | ||
| 485 | retval = 0; | ||
| 486 | } | ||
| 487 | 457 | ||
| 488 | if (options & WDIOS_ENABLECARD) { | 458 | if (get_user(options, uarg.i)) |
| 489 | wb_smsc_wdt_enable(); | 459 | return -EFAULT; |
| 490 | retval = 0; | ||
| 491 | } | ||
| 492 | 460 | ||
| 493 | return retval; | 461 | if (options & WDIOS_DISABLECARD) { |
| 462 | wb_smsc_wdt_disable(); | ||
| 463 | retval = 0; | ||
| 464 | } | ||
| 465 | if (options & WDIOS_ENABLECARD) { | ||
| 466 | wb_smsc_wdt_enable(); | ||
| 467 | retval = 0; | ||
| 494 | } | 468 | } |
| 469 | return retval; | ||
| 470 | } | ||
| 471 | case WDIOC_KEEPALIVE: | ||
| 472 | wb_smsc_wdt_reset_timer(); | ||
| 473 | return 0; | ||
| 474 | case WDIOC_SETTIMEOUT: | ||
| 475 | if (get_user(new_timeout, uarg.i)) | ||
| 476 | return -EFAULT; | ||
| 477 | /* the API states this is given in secs */ | ||
| 478 | if (unit == UNIT_MINUTE) | ||
| 479 | new_timeout /= 60; | ||
| 480 | if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) | ||
| 481 | return -EINVAL; | ||
| 482 | timeout = new_timeout; | ||
| 483 | wb_smsc_wdt_set_timeout(timeout); | ||
| 484 | /* fall through and return the new timeout... */ | ||
| 485 | case WDIOC_GETTIMEOUT: | ||
| 486 | new_timeout = timeout; | ||
| 487 | if (unit == UNIT_MINUTE) | ||
| 488 | new_timeout *= 60; | ||
| 489 | return put_user(new_timeout, uarg.i); | ||
| 490 | default: | ||
| 491 | return -ENOTTY; | ||
| 495 | } | 492 | } |
| 496 | } | 493 | } |
| 497 | 494 | ||
| 498 | /* -- Notifier funtions -----------------------------------------*/ | 495 | /* -- Notifier funtions -----------------------------------------*/ |
| 499 | 496 | ||
| 500 | static int wb_smsc_wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 497 | static int wb_smsc_wdt_notify_sys(struct notifier_block *this, |
| 498 | unsigned long code, void *unused) | ||
| 501 | { | 499 | { |
| 502 | if (code == SYS_DOWN || code == SYS_HALT) | 500 | if (code == SYS_DOWN || code == SYS_HALT) { |
| 503 | { | 501 | /* set timeout to 0, to avoid possible race-condition */ |
| 504 | // set timeout to 0, to avoid possible race-condition | 502 | timeout = 0; |
| 505 | timeout = 0; | ||
| 506 | wb_smsc_wdt_disable(); | 503 | wb_smsc_wdt_disable(); |
| 507 | } | 504 | } |
| 508 | return NOTIFY_DONE; | 505 | return NOTIFY_DONE; |
| @@ -510,23 +507,20 @@ static int wb_smsc_wdt_notify_sys(struct notifier_block *this, unsigned long cod | |||
| 510 | 507 | ||
| 511 | /* -- Module's structures ---------------------------------------*/ | 508 | /* -- Module's structures ---------------------------------------*/ |
| 512 | 509 | ||
| 513 | static const struct file_operations wb_smsc_wdt_fops = | 510 | static const struct file_operations wb_smsc_wdt_fops = { |
| 514 | { | 511 | .owner = THIS_MODULE, |
| 515 | .owner = THIS_MODULE, | ||
| 516 | .llseek = no_llseek, | 512 | .llseek = no_llseek, |
| 517 | .write = wb_smsc_wdt_write, | 513 | .write = wb_smsc_wdt_write, |
| 518 | .ioctl = wb_smsc_wdt_ioctl, | 514 | .unlocked_ioctl = wb_smsc_wdt_ioctl, |
| 519 | .open = wb_smsc_wdt_open, | 515 | .open = wb_smsc_wdt_open, |
| 520 | .release = wb_smsc_wdt_release, | 516 | .release = wb_smsc_wdt_release, |
| 521 | }; | 517 | }; |
| 522 | 518 | ||
| 523 | static struct notifier_block wb_smsc_wdt_notifier = | 519 | static struct notifier_block wb_smsc_wdt_notifier = { |
| 524 | { | ||
| 525 | .notifier_call = wb_smsc_wdt_notify_sys, | 520 | .notifier_call = wb_smsc_wdt_notify_sys, |
| 526 | }; | 521 | }; |
| 527 | 522 | ||
| 528 | static struct miscdevice wb_smsc_wdt_miscdev = | 523 | static struct miscdevice wb_smsc_wdt_miscdev = { |
| 529 | { | ||
| 530 | .minor = WATCHDOG_MINOR, | 524 | .minor = WATCHDOG_MINOR, |
| 531 | .name = "watchdog", | 525 | .name = "watchdog", |
| 532 | .fops = &wb_smsc_wdt_fops, | 526 | .fops = &wb_smsc_wdt_fops, |
| @@ -540,39 +534,44 @@ static int __init wb_smsc_wdt_init(void) | |||
| 540 | { | 534 | { |
| 541 | int ret; | 535 | int ret; |
| 542 | 536 | ||
| 543 | printk("SMsC 37B787 watchdog component driver " VERSION " initialising...\n"); | 537 | printk(KERN_INFO "SMsC 37B787 watchdog component driver " |
| 538 | VERSION " initialising...\n"); | ||
| 544 | 539 | ||
| 545 | if (!request_region(IOPORT, IOPORT_SIZE, "SMsC 37B787 watchdog")) { | 540 | if (!request_region(IOPORT, IOPORT_SIZE, "SMsC 37B787 watchdog")) { |
| 546 | printk(KERN_ERR MODNAME "Unable to register IO port %#x\n", IOPORT); | 541 | printk(KERN_ERR MODNAME "Unable to register IO port %#x\n", |
| 542 | IOPORT); | ||
| 547 | ret = -EBUSY; | 543 | ret = -EBUSY; |
| 548 | goto out_pnp; | 544 | goto out_pnp; |
| 549 | } | 545 | } |
| 550 | 546 | ||
| 551 | // set new maximum, if it's too big | 547 | /* set new maximum, if it's too big */ |
| 552 | if (timeout > MAX_TIMEOUT) | 548 | if (timeout > MAX_TIMEOUT) |
| 553 | timeout = MAX_TIMEOUT; | 549 | timeout = MAX_TIMEOUT; |
| 554 | 550 | ||
| 555 | // init the watchdog timer | 551 | /* init the watchdog timer */ |
| 556 | wb_smsc_wdt_initialize(); | 552 | wb_smsc_wdt_initialize(); |
| 557 | 553 | ||
| 558 | ret = register_reboot_notifier(&wb_smsc_wdt_notifier); | 554 | ret = register_reboot_notifier(&wb_smsc_wdt_notifier); |
| 559 | if (ret) { | 555 | if (ret) { |
| 560 | printk(KERN_ERR MODNAME "Unable to register reboot notifier err = %d\n", ret); | 556 | printk(KERN_ERR MODNAME |
| 557 | "Unable to register reboot notifier err = %d\n", ret); | ||
| 561 | goto out_io; | 558 | goto out_io; |
| 562 | } | 559 | } |
| 563 | 560 | ||
| 564 | ret = misc_register(&wb_smsc_wdt_miscdev); | 561 | ret = misc_register(&wb_smsc_wdt_miscdev); |
| 565 | if (ret) { | 562 | if (ret) { |
| 566 | printk(KERN_ERR MODNAME "Unable to register miscdev on minor %d\n", WATCHDOG_MINOR); | 563 | printk(KERN_ERR MODNAME |
| 564 | "Unable to register miscdev on minor %d\n", | ||
| 565 | WATCHDOG_MINOR); | ||
| 567 | goto out_rbt; | 566 | goto out_rbt; |
| 568 | } | 567 | } |
| 569 | 568 | ||
| 570 | // output info | 569 | /* output info */ |
| 571 | printk(KERN_INFO MODNAME "Timeout set to %d %s.\n", timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); | 570 | printk(KERN_INFO MODNAME "Timeout set to %d %s.\n", |
| 572 | printk(KERN_INFO MODNAME "Watchdog initialized and sleeping (nowayout=%d)...\n", nowayout); | 571 | timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); |
| 573 | 572 | printk(KERN_INFO MODNAME | |
| 574 | // ret = 0 | 573 | "Watchdog initialized and sleeping (nowayout=%d)...\n", |
| 575 | 574 | nowayout); | |
| 576 | out_clean: | 575 | out_clean: |
| 577 | return ret; | 576 | return ret; |
| 578 | 577 | ||
| @@ -591,8 +590,7 @@ out_pnp: | |||
| 591 | static void __exit wb_smsc_wdt_exit(void) | 590 | static void __exit wb_smsc_wdt_exit(void) |
| 592 | { | 591 | { |
| 593 | /* Stop the timer before we leave */ | 592 | /* Stop the timer before we leave */ |
| 594 | if (!nowayout) | 593 | if (!nowayout) { |
| 595 | { | ||
| 596 | wb_smsc_wdt_shutdown(); | 594 | wb_smsc_wdt_shutdown(); |
| 597 | printk(KERN_INFO MODNAME "Watchdog disabled.\n"); | 595 | printk(KERN_INFO MODNAME "Watchdog disabled.\n"); |
| 598 | } | 596 | } |
| @@ -601,25 +599,29 @@ static void __exit wb_smsc_wdt_exit(void) | |||
| 601 | unregister_reboot_notifier(&wb_smsc_wdt_notifier); | 599 | unregister_reboot_notifier(&wb_smsc_wdt_notifier); |
| 602 | release_region(IOPORT, IOPORT_SIZE); | 600 | release_region(IOPORT, IOPORT_SIZE); |
| 603 | 601 | ||
| 604 | printk("SMsC 37B787 watchdog component driver removed.\n"); | 602 | printk(KERN_INFO "SMsC 37B787 watchdog component driver removed.\n"); |
| 605 | } | 603 | } |
| 606 | 604 | ||
| 607 | module_init(wb_smsc_wdt_init); | 605 | module_init(wb_smsc_wdt_init); |
| 608 | module_exit(wb_smsc_wdt_exit); | 606 | module_exit(wb_smsc_wdt_exit); |
| 609 | 607 | ||
| 610 | MODULE_AUTHOR("Sven Anders <anders@anduras.de>"); | 608 | MODULE_AUTHOR("Sven Anders <anders@anduras.de>"); |
| 611 | MODULE_DESCRIPTION("Driver for SMsC 37B787 watchdog component (Version " VERSION ")"); | 609 | MODULE_DESCRIPTION("Driver for SMsC 37B787 watchdog component (Version " |
| 610 | VERSION ")"); | ||
| 612 | MODULE_LICENSE("GPL"); | 611 | MODULE_LICENSE("GPL"); |
| 613 | 612 | ||
| 614 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | 613 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
| 615 | 614 | ||
| 616 | #ifdef SMSC_SUPPORT_MINUTES | 615 | #ifdef SMSC_SUPPORT_MINUTES |
| 617 | module_param(unit, int, 0); | 616 | module_param(unit, int, 0); |
| 618 | MODULE_PARM_DESC(unit, "set unit to use, 0=seconds or 1=minutes, default is 0"); | 617 | MODULE_PARM_DESC(unit, |
| 618 | "set unit to use, 0=seconds or 1=minutes, default is 0"); | ||
| 619 | #endif | 619 | #endif |
| 620 | 620 | ||
| 621 | module_param(timeout, int, 0); | 621 | module_param(timeout, int, 0); |
| 622 | MODULE_PARM_DESC(timeout, "range is 1-255 units, default is 60"); | 622 | MODULE_PARM_DESC(timeout, "range is 1-255 units, default is 60"); |
| 623 | 623 | ||
| 624 | module_param(nowayout, int, 0); | 624 | module_param(nowayout, int, 0); |
| 625 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 625 | MODULE_PARM_DESC(nowayout, |
| 626 | "Watchdog cannot be stopped once started (default=" | ||
| 627 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
diff --git a/drivers/watchdog/softdog.c b/drivers/watchdog/softdog.c index 9c3694909243..c650464c5c63 100644 --- a/drivers/watchdog/softdog.c +++ b/drivers/watchdog/softdog.c | |||
| @@ -47,19 +47,22 @@ | |||
| 47 | #include <linux/reboot.h> | 47 | #include <linux/reboot.h> |
| 48 | #include <linux/init.h> | 48 | #include <linux/init.h> |
| 49 | #include <linux/jiffies.h> | 49 | #include <linux/jiffies.h> |
| 50 | 50 | #include <linux/uaccess.h> | |
| 51 | #include <asm/uaccess.h> | ||
| 52 | 51 | ||
| 53 | #define PFX "SoftDog: " | 52 | #define PFX "SoftDog: " |
| 54 | 53 | ||
| 55 | #define TIMER_MARGIN 60 /* Default is 60 seconds */ | 54 | #define TIMER_MARGIN 60 /* Default is 60 seconds */ |
| 56 | static int soft_margin = TIMER_MARGIN; /* in seconds */ | 55 | static int soft_margin = TIMER_MARGIN; /* in seconds */ |
| 57 | module_param(soft_margin, int, 0); | 56 | module_param(soft_margin, int, 0); |
| 58 | MODULE_PARM_DESC(soft_margin, "Watchdog soft_margin in seconds. (0<soft_margin<65536, default=" __MODULE_STRING(TIMER_MARGIN) ")"); | 57 | MODULE_PARM_DESC(soft_margin, |
| 58 | "Watchdog soft_margin in seconds. (0 < soft_margin < 65536, default=" | ||
| 59 | __MODULE_STRING(TIMER_MARGIN) ")"); | ||
| 59 | 60 | ||
| 60 | static int nowayout = WATCHDOG_NOWAYOUT; | 61 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 61 | module_param(nowayout, int, 0); | 62 | module_param(nowayout, int, 0); |
| 62 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 63 | MODULE_PARM_DESC(nowayout, |
| 64 | "Watchdog cannot be stopped once started (default=" | ||
| 65 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 63 | 66 | ||
| 64 | #ifdef ONLY_TESTING | 67 | #ifdef ONLY_TESTING |
| 65 | static int soft_noboot = 1; | 68 | static int soft_noboot = 1; |
| @@ -93,8 +96,7 @@ static void watchdog_fire(unsigned long data) | |||
| 93 | 96 | ||
| 94 | if (soft_noboot) | 97 | if (soft_noboot) |
| 95 | printk(KERN_CRIT PFX "Triggered - Reboot ignored.\n"); | 98 | printk(KERN_CRIT PFX "Triggered - Reboot ignored.\n"); |
| 96 | else | 99 | else { |
| 97 | { | ||
| 98 | printk(KERN_CRIT PFX "Initiating system reboot.\n"); | 100 | printk(KERN_CRIT PFX "Initiating system reboot.\n"); |
| 99 | emergency_restart(); | 101 | emergency_restart(); |
| 100 | printk(KERN_CRIT PFX "Reboot didn't ?????\n"); | 102 | printk(KERN_CRIT PFX "Reboot didn't ?????\n"); |
| @@ -153,7 +155,8 @@ static int softdog_release(struct inode *inode, struct file *file) | |||
| 153 | softdog_stop(); | 155 | softdog_stop(); |
| 154 | module_put(THIS_MODULE); | 156 | module_put(THIS_MODULE); |
| 155 | } else { | 157 | } else { |
| 156 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 158 | printk(KERN_CRIT PFX |
| 159 | "Unexpected close, not stopping watchdog!\n"); | ||
| 157 | set_bit(0, &orphan_timer); | 160 | set_bit(0, &orphan_timer); |
| 158 | softdog_keepalive(); | 161 | softdog_keepalive(); |
| 159 | } | 162 | } |
| @@ -162,12 +165,13 @@ static int softdog_release(struct inode *inode, struct file *file) | |||
| 162 | return 0; | 165 | return 0; |
| 163 | } | 166 | } |
| 164 | 167 | ||
| 165 | static ssize_t softdog_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) | 168 | static ssize_t softdog_write(struct file *file, const char __user *data, |
| 169 | size_t len, loff_t *ppos) | ||
| 166 | { | 170 | { |
| 167 | /* | 171 | /* |
| 168 | * Refresh the timer. | 172 | * Refresh the timer. |
| 169 | */ | 173 | */ |
| 170 | if(len) { | 174 | if (len) { |
| 171 | if (!nowayout) { | 175 | if (!nowayout) { |
| 172 | size_t i; | 176 | size_t i; |
| 173 | 177 | ||
| @@ -188,13 +192,13 @@ static ssize_t softdog_write(struct file *file, const char __user *data, size_t | |||
| 188 | return len; | 192 | return len; |
| 189 | } | 193 | } |
| 190 | 194 | ||
| 191 | static int softdog_ioctl(struct inode *inode, struct file *file, | 195 | static long softdog_ioctl(struct file *file, unsigned int cmd, |
| 192 | unsigned int cmd, unsigned long arg) | 196 | unsigned long arg) |
| 193 | { | 197 | { |
| 194 | void __user *argp = (void __user *)arg; | 198 | void __user *argp = (void __user *)arg; |
| 195 | int __user *p = argp; | 199 | int __user *p = argp; |
| 196 | int new_margin; | 200 | int new_margin; |
| 197 | static struct watchdog_info ident = { | 201 | static const struct watchdog_info ident = { |
| 198 | .options = WDIOF_SETTIMEOUT | | 202 | .options = WDIOF_SETTIMEOUT | |
| 199 | WDIOF_KEEPALIVEPING | | 203 | WDIOF_KEEPALIVEPING | |
| 200 | WDIOF_MAGICCLOSE, | 204 | WDIOF_MAGICCLOSE, |
| @@ -202,26 +206,25 @@ static int softdog_ioctl(struct inode *inode, struct file *file, | |||
| 202 | .identity = "Software Watchdog", | 206 | .identity = "Software Watchdog", |
| 203 | }; | 207 | }; |
| 204 | switch (cmd) { | 208 | switch (cmd) { |
| 205 | default: | 209 | case WDIOC_GETSUPPORT: |
| 206 | return -ENOTTY; | 210 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 207 | case WDIOC_GETSUPPORT: | 211 | case WDIOC_GETSTATUS: |
| 208 | return copy_to_user(argp, &ident, | 212 | case WDIOC_GETBOOTSTATUS: |
| 209 | sizeof(ident)) ? -EFAULT : 0; | 213 | return put_user(0, p); |
| 210 | case WDIOC_GETSTATUS: | 214 | case WDIOC_KEEPALIVE: |
| 211 | case WDIOC_GETBOOTSTATUS: | 215 | softdog_keepalive(); |
| 212 | return put_user(0, p); | 216 | return 0; |
| 213 | case WDIOC_KEEPALIVE: | 217 | case WDIOC_SETTIMEOUT: |
| 214 | softdog_keepalive(); | 218 | if (get_user(new_margin, p)) |
| 215 | return 0; | 219 | return -EFAULT; |
| 216 | case WDIOC_SETTIMEOUT: | 220 | if (softdog_set_heartbeat(new_margin)) |
| 217 | if (get_user(new_margin, p)) | 221 | return -EINVAL; |
| 218 | return -EFAULT; | 222 | softdog_keepalive(); |
| 219 | if (softdog_set_heartbeat(new_margin)) | 223 | /* Fall */ |
| 220 | return -EINVAL; | 224 | case WDIOC_GETTIMEOUT: |
| 221 | softdog_keepalive(); | 225 | return put_user(soft_margin, p); |
| 222 | /* Fall */ | 226 | default: |
| 223 | case WDIOC_GETTIMEOUT: | 227 | return -ENOTTY; |
| 224 | return put_user(soft_margin, p); | ||
| 225 | } | 228 | } |
| 226 | } | 229 | } |
| 227 | 230 | ||
| @@ -232,10 +235,9 @@ static int softdog_ioctl(struct inode *inode, struct file *file, | |||
| 232 | static int softdog_notify_sys(struct notifier_block *this, unsigned long code, | 235 | static int softdog_notify_sys(struct notifier_block *this, unsigned long code, |
| 233 | void *unused) | 236 | void *unused) |
| 234 | { | 237 | { |
| 235 | if(code==SYS_DOWN || code==SYS_HALT) { | 238 | if (code == SYS_DOWN || code == SYS_HALT) |
| 236 | /* Turn the WDT off */ | 239 | /* Turn the WDT off */ |
| 237 | softdog_stop(); | 240 | softdog_stop(); |
| 238 | } | ||
| 239 | return NOTIFY_DONE; | 241 | return NOTIFY_DONE; |
| 240 | } | 242 | } |
| 241 | 243 | ||
| @@ -247,7 +249,7 @@ static const struct file_operations softdog_fops = { | |||
| 247 | .owner = THIS_MODULE, | 249 | .owner = THIS_MODULE, |
| 248 | .llseek = no_llseek, | 250 | .llseek = no_llseek, |
| 249 | .write = softdog_write, | 251 | .write = softdog_write, |
| 250 | .ioctl = softdog_ioctl, | 252 | .unlocked_ioctl = softdog_ioctl, |
| 251 | .open = softdog_open, | 253 | .open = softdog_open, |
| 252 | .release = softdog_release, | 254 | .release = softdog_release, |
| 253 | }; | 255 | }; |
| @@ -268,24 +270,27 @@ static int __init watchdog_init(void) | |||
| 268 | { | 270 | { |
| 269 | int ret; | 271 | int ret; |
| 270 | 272 | ||
| 271 | /* Check that the soft_margin value is within it's range ; if not reset to the default */ | 273 | /* Check that the soft_margin value is within it's range; |
| 274 | if not reset to the default */ | ||
| 272 | if (softdog_set_heartbeat(soft_margin)) { | 275 | if (softdog_set_heartbeat(soft_margin)) { |
| 273 | softdog_set_heartbeat(TIMER_MARGIN); | 276 | softdog_set_heartbeat(TIMER_MARGIN); |
| 274 | printk(KERN_INFO PFX "soft_margin value must be 0<soft_margin<65536, using %d\n", | 277 | printk(KERN_INFO PFX |
| 278 | "soft_margin must be 0 < soft_margin < 65536, using %d\n", | ||
| 275 | TIMER_MARGIN); | 279 | TIMER_MARGIN); |
| 276 | } | 280 | } |
| 277 | 281 | ||
| 278 | ret = register_reboot_notifier(&softdog_notifier); | 282 | ret = register_reboot_notifier(&softdog_notifier); |
| 279 | if (ret) { | 283 | if (ret) { |
| 280 | printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 284 | printk(KERN_ERR PFX |
| 281 | ret); | 285 | "cannot register reboot notifier (err=%d)\n", ret); |
| 282 | return ret; | 286 | return ret; |
| 283 | } | 287 | } |
| 284 | 288 | ||
| 285 | ret = misc_register(&softdog_miscdev); | 289 | ret = misc_register(&softdog_miscdev); |
| 286 | if (ret) { | 290 | if (ret) { |
| 287 | printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 291 | printk(KERN_ERR PFX |
| 288 | WATCHDOG_MINOR, ret); | 292 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 293 | WATCHDOG_MINOR, ret); | ||
| 289 | unregister_reboot_notifier(&softdog_notifier); | 294 | unregister_reboot_notifier(&softdog_notifier); |
| 290 | return ret; | 295 | return ret; |
| 291 | } | 296 | } |
diff --git a/drivers/watchdog/txx9wdt.c b/drivers/watchdog/txx9wdt.c index 57cefef27ce3..dbbc018a5f46 100644 --- a/drivers/watchdog/txx9wdt.c +++ b/drivers/watchdog/txx9wdt.c | |||
| @@ -45,27 +45,34 @@ static unsigned long txx9wdt_alive; | |||
| 45 | static int expect_close; | 45 | static int expect_close; |
| 46 | static struct txx9_tmr_reg __iomem *txx9wdt_reg; | 46 | static struct txx9_tmr_reg __iomem *txx9wdt_reg; |
| 47 | static struct clk *txx9_imclk; | 47 | static struct clk *txx9_imclk; |
| 48 | static DECLARE_LOCK(txx9_lock); | ||
| 48 | 49 | ||
| 49 | static void txx9wdt_ping(void) | 50 | static void txx9wdt_ping(void) |
| 50 | { | 51 | { |
| 52 | spin_lock(&txx9_lock); | ||
| 51 | __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); | 53 | __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); |
| 54 | spin_unlock(&txx9_lock); | ||
| 52 | } | 55 | } |
| 53 | 56 | ||
| 54 | static void txx9wdt_start(void) | 57 | static void txx9wdt_start(void) |
| 55 | { | 58 | { |
| 59 | spin_lock(&txx9_lock); | ||
| 56 | __raw_writel(WD_TIMER_CLK * timeout, &txx9wdt_reg->cpra); | 60 | __raw_writel(WD_TIMER_CLK * timeout, &txx9wdt_reg->cpra); |
| 57 | __raw_writel(WD_TIMER_CCD, &txx9wdt_reg->ccdr); | 61 | __raw_writel(WD_TIMER_CCD, &txx9wdt_reg->ccdr); |
| 58 | __raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */ | 62 | __raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */ |
| 59 | __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG, | 63 | __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG, |
| 60 | &txx9wdt_reg->tcr); | 64 | &txx9wdt_reg->tcr); |
| 61 | __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); | 65 | __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); |
| 66 | spin_unlock(&txx9_lock); | ||
| 62 | } | 67 | } |
| 63 | 68 | ||
| 64 | static void txx9wdt_stop(void) | 69 | static void txx9wdt_stop(void) |
| 65 | { | 70 | { |
| 71 | spin_lock(&txx9_lock); | ||
| 66 | __raw_writel(TXx9_TMWTMR_WDIS, &txx9wdt_reg->wtmr); | 72 | __raw_writel(TXx9_TMWTMR_WDIS, &txx9wdt_reg->wtmr); |
| 67 | __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, | 73 | __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, |
| 68 | &txx9wdt_reg->tcr); | 74 | &txx9wdt_reg->tcr); |
| 75 | spin_unlock(&txx9_lock); | ||
| 69 | } | 76 | } |
| 70 | 77 | ||
| 71 | static int txx9wdt_open(struct inode *inode, struct file *file) | 78 | static int txx9wdt_open(struct inode *inode, struct file *file) |
| @@ -120,13 +127,13 @@ static ssize_t txx9wdt_write(struct file *file, const char __user *data, | |||
| 120 | return len; | 127 | return len; |
| 121 | } | 128 | } |
| 122 | 129 | ||
| 123 | static int txx9wdt_ioctl(struct inode *inode, struct file *file, | 130 | static long txx9wdt_ioctl(struct file *file, unsigned int cmd, |
| 124 | unsigned int cmd, unsigned long arg) | 131 | unsigned long arg) |
| 125 | { | 132 | { |
| 126 | void __user *argp = (void __user *)arg; | 133 | void __user *argp = (void __user *)arg; |
| 127 | int __user *p = argp; | 134 | int __user *p = argp; |
| 128 | int new_timeout; | 135 | int new_timeout; |
| 129 | static struct watchdog_info ident = { | 136 | static const struct watchdog_info ident = { |
| 130 | .options = WDIOF_SETTIMEOUT | | 137 | .options = WDIOF_SETTIMEOUT | |
| 131 | WDIOF_KEEPALIVEPING | | 138 | WDIOF_KEEPALIVEPING | |
| 132 | WDIOF_MAGICCLOSE, | 139 | WDIOF_MAGICCLOSE, |
| @@ -135,8 +142,6 @@ static int txx9wdt_ioctl(struct inode *inode, struct file *file, | |||
| 135 | }; | 142 | }; |
| 136 | 143 | ||
| 137 | switch (cmd) { | 144 | switch (cmd) { |
| 138 | default: | ||
| 139 | return -ENOTTY; | ||
| 140 | case WDIOC_GETSUPPORT: | 145 | case WDIOC_GETSUPPORT: |
| 141 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | 146 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 142 | case WDIOC_GETSTATUS: | 147 | case WDIOC_GETSTATUS: |
| @@ -156,6 +161,8 @@ static int txx9wdt_ioctl(struct inode *inode, struct file *file, | |||
| 156 | /* Fall */ | 161 | /* Fall */ |
| 157 | case WDIOC_GETTIMEOUT: | 162 | case WDIOC_GETTIMEOUT: |
| 158 | return put_user(timeout, p); | 163 | return put_user(timeout, p); |
| 164 | default: | ||
| 165 | return -ENOTTY; | ||
| 159 | } | 166 | } |
| 160 | } | 167 | } |
| 161 | 168 | ||
| @@ -168,22 +175,22 @@ static int txx9wdt_notify_sys(struct notifier_block *this, unsigned long code, | |||
| 168 | } | 175 | } |
| 169 | 176 | ||
| 170 | static const struct file_operations txx9wdt_fops = { | 177 | static const struct file_operations txx9wdt_fops = { |
| 171 | .owner = THIS_MODULE, | 178 | .owner = THIS_MODULE, |
| 172 | .llseek = no_llseek, | 179 | .llseek = no_llseek, |
| 173 | .write = txx9wdt_write, | 180 | .write = txx9wdt_write, |
| 174 | .ioctl = txx9wdt_ioctl, | 181 | .unlocked_ioctl = txx9wdt_ioctl, |
| 175 | .open = txx9wdt_open, | 182 | .open = txx9wdt_open, |
| 176 | .release = txx9wdt_release, | 183 | .release = txx9wdt_release, |
| 177 | }; | 184 | }; |
| 178 | 185 | ||
| 179 | static struct miscdevice txx9wdt_miscdev = { | 186 | static struct miscdevice txx9wdt_miscdev = { |
| 180 | .minor = WATCHDOG_MINOR, | 187 | .minor = WATCHDOG_MINOR, |
| 181 | .name = "watchdog", | 188 | .name = "watchdog", |
| 182 | .fops = &txx9wdt_fops, | 189 | .fops = &txx9wdt_fops, |
| 183 | }; | 190 | }; |
| 184 | 191 | ||
| 185 | static struct notifier_block txx9wdt_notifier = { | 192 | static struct notifier_block txx9wdt_notifier = { |
| 186 | .notifier_call = txx9wdt_notify_sys | 193 | .notifier_call = txx9wdt_notify_sys, |
| 187 | }; | 194 | }; |
| 188 | 195 | ||
| 189 | static int __init txx9wdt_probe(struct platform_device *dev) | 196 | static int __init txx9wdt_probe(struct platform_device *dev) |
diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index 386492821fc2..69396adaa5c3 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c | |||
| @@ -37,9 +37,9 @@ | |||
| 37 | #include <linux/reboot.h> | 37 | #include <linux/reboot.h> |
| 38 | #include <linux/init.h> | 38 | #include <linux/init.h> |
| 39 | #include <linux/spinlock.h> | 39 | #include <linux/spinlock.h> |
| 40 | #include <linux/io.h> | ||
| 41 | #include <linux/uaccess.h> | ||
| 40 | 42 | ||
| 41 | #include <asm/io.h> | ||
| 42 | #include <asm/uaccess.h> | ||
| 43 | #include <asm/system.h> | 43 | #include <asm/system.h> |
| 44 | 44 | ||
| 45 | #define WATCHDOG_NAME "w83627hf/thf/hg WDT" | 45 | #define WATCHDOG_NAME "w83627hf/thf/hg WDT" |
| @@ -57,22 +57,26 @@ MODULE_PARM_DESC(wdt_io, "w83627hf/thf WDT io port (default 0x2E)"); | |||
| 57 | 57 | ||
| 58 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ | 58 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ |
| 59 | module_param(timeout, int, 0); | 59 | module_param(timeout, int, 0); |
| 60 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | 60 | MODULE_PARM_DESC(timeout, |
| 61 | "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" | ||
| 62 | __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | ||
| 61 | 63 | ||
| 62 | static int nowayout = WATCHDOG_NOWAYOUT; | 64 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 63 | module_param(nowayout, int, 0); | 65 | module_param(nowayout, int, 0); |
| 64 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 66 | MODULE_PARM_DESC(nowayout, |
| 67 | "Watchdog cannot be stopped once started (default=" | ||
| 68 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 65 | 69 | ||
| 66 | /* | 70 | /* |
| 67 | * Kernel methods. | 71 | * Kernel methods. |
| 68 | */ | 72 | */ |
| 69 | 73 | ||
| 70 | #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */ | 74 | #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */ |
| 71 | #define WDT_EFIR (wdt_io+0) /* Extended Function Index Register (same as EFER) */ | 75 | #define WDT_EFIR (wdt_io+0) /* Extended Function Index Register |
| 76 | (same as EFER) */ | ||
| 72 | #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */ | 77 | #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */ |
| 73 | 78 | ||
| 74 | static void | 79 | static void w83627hf_select_wd_register(void) |
| 75 | w83627hf_select_wd_register(void) | ||
| 76 | { | 80 | { |
| 77 | unsigned char c; | 81 | unsigned char c; |
| 78 | outb_p(0x87, WDT_EFER); /* Enter extended function mode */ | 82 | outb_p(0x87, WDT_EFER); /* Enter extended function mode */ |
| @@ -93,43 +97,45 @@ w83627hf_select_wd_register(void) | |||
| 93 | outb_p(0x01, WDT_EFDR); /* set bit 0 to activate GPIO2 */ | 97 | outb_p(0x01, WDT_EFDR); /* set bit 0 to activate GPIO2 */ |
| 94 | } | 98 | } |
| 95 | 99 | ||
| 96 | static void | 100 | static void w83627hf_unselect_wd_register(void) |
| 97 | w83627hf_unselect_wd_register(void) | ||
| 98 | { | 101 | { |
| 99 | outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ | 102 | outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ |
| 100 | } | 103 | } |
| 101 | 104 | ||
| 102 | /* tyan motherboards seem to set F5 to 0x4C ? | 105 | /* tyan motherboards seem to set F5 to 0x4C ? |
| 103 | * So explicitly init to appropriate value. */ | 106 | * So explicitly init to appropriate value. */ |
| 104 | static void | 107 | |
| 105 | w83627hf_init(void) | 108 | static void w83627hf_init(void) |
| 106 | { | 109 | { |
| 107 | unsigned char t; | 110 | unsigned char t; |
| 108 | 111 | ||
| 109 | w83627hf_select_wd_register(); | 112 | w83627hf_select_wd_register(); |
| 110 | 113 | ||
| 111 | outb_p(0xF6, WDT_EFER); /* Select CRF6 */ | 114 | outb_p(0xF6, WDT_EFER); /* Select CRF6 */ |
| 112 | t=inb_p(WDT_EFDR); /* read CRF6 */ | 115 | t = inb_p(WDT_EFDR); /* read CRF6 */ |
| 113 | if (t != 0) { | 116 | if (t != 0) { |
| 114 | printk (KERN_INFO PFX "Watchdog already running. Resetting timeout to %d sec\n", timeout); | 117 | printk(KERN_INFO PFX |
| 118 | "Watchdog already running. Resetting timeout to %d sec\n", | ||
| 119 | timeout); | ||
| 115 | outb_p(timeout, WDT_EFDR); /* Write back to CRF6 */ | 120 | outb_p(timeout, WDT_EFDR); /* Write back to CRF6 */ |
| 116 | } | 121 | } |
| 117 | 122 | ||
| 118 | outb_p(0xF5, WDT_EFER); /* Select CRF5 */ | 123 | outb_p(0xF5, WDT_EFER); /* Select CRF5 */ |
| 119 | t=inb_p(WDT_EFDR); /* read CRF5 */ | 124 | t = inb_p(WDT_EFDR); /* read CRF5 */ |
| 120 | t&=~0x0C; /* set second mode & disable keyboard turning off watchdog */ | 125 | t &= ~0x0C; /* set second mode & disable keyboard |
| 126 | turning off watchdog */ | ||
| 121 | outb_p(t, WDT_EFDR); /* Write back to CRF5 */ | 127 | outb_p(t, WDT_EFDR); /* Write back to CRF5 */ |
| 122 | 128 | ||
| 123 | outb_p(0xF7, WDT_EFER); /* Select CRF7 */ | 129 | outb_p(0xF7, WDT_EFER); /* Select CRF7 */ |
| 124 | t=inb_p(WDT_EFDR); /* read CRF7 */ | 130 | t = inb_p(WDT_EFDR); /* read CRF7 */ |
| 125 | t&=~0xC0; /* disable keyboard & mouse turning off watchdog */ | 131 | t &= ~0xC0; /* disable keyboard & mouse turning off |
| 132 | watchdog */ | ||
| 126 | outb_p(t, WDT_EFDR); /* Write back to CRF7 */ | 133 | outb_p(t, WDT_EFDR); /* Write back to CRF7 */ |
| 127 | 134 | ||
| 128 | w83627hf_unselect_wd_register(); | 135 | w83627hf_unselect_wd_register(); |
| 129 | } | 136 | } |
| 130 | 137 | ||
| 131 | static void | 138 | static void wdt_ctrl(int timeout) |
| 132 | wdt_ctrl(int timeout) | ||
| 133 | { | 139 | { |
| 134 | spin_lock(&io_lock); | 140 | spin_lock(&io_lock); |
| 135 | 141 | ||
| @@ -143,32 +149,28 @@ wdt_ctrl(int timeout) | |||
| 143 | spin_unlock(&io_lock); | 149 | spin_unlock(&io_lock); |
| 144 | } | 150 | } |
| 145 | 151 | ||
| 146 | static int | 152 | static int wdt_ping(void) |
| 147 | wdt_ping(void) | ||
| 148 | { | 153 | { |
| 149 | wdt_ctrl(timeout); | 154 | wdt_ctrl(timeout); |
| 150 | return 0; | 155 | return 0; |
| 151 | } | 156 | } |
| 152 | 157 | ||
| 153 | static int | 158 | static int wdt_disable(void) |
| 154 | wdt_disable(void) | ||
| 155 | { | 159 | { |
| 156 | wdt_ctrl(0); | 160 | wdt_ctrl(0); |
| 157 | return 0; | 161 | return 0; |
| 158 | } | 162 | } |
| 159 | 163 | ||
| 160 | static int | 164 | static int wdt_set_heartbeat(int t) |
| 161 | wdt_set_heartbeat(int t) | ||
| 162 | { | 165 | { |
| 163 | if ((t < 1) || (t > 255)) | 166 | if (t < 1 || t > 255) |
| 164 | return -EINVAL; | 167 | return -EINVAL; |
| 165 | |||
| 166 | timeout = t; | 168 | timeout = t; |
| 167 | return 0; | 169 | return 0; |
| 168 | } | 170 | } |
| 169 | 171 | ||
| 170 | static ssize_t | 172 | static ssize_t wdt_write(struct file *file, const char __user *buf, |
| 171 | wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | 173 | size_t count, loff_t *ppos) |
| 172 | { | 174 | { |
| 173 | if (count) { | 175 | if (count) { |
| 174 | if (!nowayout) { | 176 | if (!nowayout) { |
| @@ -178,7 +180,7 @@ wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | |||
| 178 | 180 | ||
| 179 | for (i = 0; i != count; i++) { | 181 | for (i = 0; i != count; i++) { |
| 180 | char c; | 182 | char c; |
| 181 | if (get_user(c, buf+i)) | 183 | if (get_user(c, buf + i)) |
| 182 | return -EFAULT; | 184 | return -EFAULT; |
| 183 | if (c == 'V') | 185 | if (c == 'V') |
| 184 | expect_close = 42; | 186 | expect_close = 42; |
| @@ -189,72 +191,61 @@ wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | |||
| 189 | return count; | 191 | return count; |
| 190 | } | 192 | } |
| 191 | 193 | ||
| 192 | static int | 194 | static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 193 | wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | ||
| 194 | unsigned long arg) | ||
| 195 | { | 195 | { |
| 196 | void __user *argp = (void __user *)arg; | 196 | void __user *argp = (void __user *)arg; |
| 197 | int __user *p = argp; | 197 | int __user *p = argp; |
| 198 | int new_timeout; | 198 | int new_timeout; |
| 199 | static struct watchdog_info ident = { | 199 | static struct watchdog_info ident = { |
| 200 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 200 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
| 201 | WDIOF_MAGICCLOSE, | ||
| 201 | .firmware_version = 1, | 202 | .firmware_version = 1, |
| 202 | .identity = "W83627HF WDT", | 203 | .identity = "W83627HF WDT", |
| 203 | }; | 204 | }; |
| 204 | 205 | ||
| 205 | switch (cmd) { | 206 | switch (cmd) { |
| 206 | case WDIOC_GETSUPPORT: | 207 | case WDIOC_GETSUPPORT: |
| 207 | if (copy_to_user(argp, &ident, sizeof(ident))) | 208 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 208 | return -EFAULT; | 209 | return -EFAULT; |
| 209 | break; | 210 | break; |
| 210 | |||
| 211 | case WDIOC_GETSTATUS: | 211 | case WDIOC_GETSTATUS: |
| 212 | case WDIOC_GETBOOTSTATUS: | 212 | case WDIOC_GETBOOTSTATUS: |
| 213 | return put_user(0, p); | 213 | return put_user(0, p); |
| 214 | |||
| 215 | case WDIOC_KEEPALIVE: | ||
| 216 | wdt_ping(); | ||
| 217 | break; | ||
| 218 | |||
| 219 | case WDIOC_SETTIMEOUT: | ||
| 220 | if (get_user(new_timeout, p)) | ||
| 221 | return -EFAULT; | ||
| 222 | if (wdt_set_heartbeat(new_timeout)) | ||
| 223 | return -EINVAL; | ||
| 224 | wdt_ping(); | ||
| 225 | /* Fall */ | ||
| 226 | |||
| 227 | case WDIOC_GETTIMEOUT: | ||
| 228 | return put_user(timeout, p); | ||
| 229 | |||
| 230 | case WDIOC_SETOPTIONS: | 214 | case WDIOC_SETOPTIONS: |
| 231 | { | 215 | { |
| 232 | int options, retval = -EINVAL; | 216 | int options, retval = -EINVAL; |
| 233 | |||
| 234 | if (get_user(options, p)) | ||
| 235 | return -EFAULT; | ||
| 236 | |||
| 237 | if (options & WDIOS_DISABLECARD) { | ||
| 238 | wdt_disable(); | ||
| 239 | retval = 0; | ||
| 240 | } | ||
| 241 | |||
| 242 | if (options & WDIOS_ENABLECARD) { | ||
| 243 | wdt_ping(); | ||
| 244 | retval = 0; | ||
| 245 | } | ||
| 246 | 217 | ||
| 247 | return retval; | 218 | if (get_user(options, p)) |
| 219 | return -EFAULT; | ||
| 220 | if (options & WDIOS_DISABLECARD) { | ||
| 221 | wdt_disable(); | ||
| 222 | retval = 0; | ||
| 223 | } | ||
| 224 | if (options & WDIOS_ENABLECARD) { | ||
| 225 | wdt_ping(); | ||
| 226 | retval = 0; | ||
| 227 | } | ||
| 228 | return retval; | ||
| 248 | } | 229 | } |
| 249 | 230 | case WDIOC_KEEPALIVE: | |
| 231 | wdt_ping(); | ||
| 232 | break; | ||
| 233 | case WDIOC_SETTIMEOUT: | ||
| 234 | if (get_user(new_timeout, p)) | ||
| 235 | return -EFAULT; | ||
| 236 | if (wdt_set_heartbeat(new_timeout)) | ||
| 237 | return -EINVAL; | ||
| 238 | wdt_ping(); | ||
| 239 | /* Fall */ | ||
| 240 | case WDIOC_GETTIMEOUT: | ||
| 241 | return put_user(timeout, p); | ||
| 250 | default: | 242 | default: |
| 251 | return -ENOTTY; | 243 | return -ENOTTY; |
| 252 | } | 244 | } |
| 253 | return 0; | 245 | return 0; |
| 254 | } | 246 | } |
| 255 | 247 | ||
| 256 | static int | 248 | static int wdt_open(struct inode *inode, struct file *file) |
| 257 | wdt_open(struct inode *inode, struct file *file) | ||
| 258 | { | 249 | { |
| 259 | if (test_and_set_bit(0, &wdt_is_open)) | 250 | if (test_and_set_bit(0, &wdt_is_open)) |
| 260 | return -EBUSY; | 251 | return -EBUSY; |
| @@ -266,13 +257,13 @@ wdt_open(struct inode *inode, struct file *file) | |||
| 266 | return nonseekable_open(inode, file); | 257 | return nonseekable_open(inode, file); |
| 267 | } | 258 | } |
| 268 | 259 | ||
| 269 | static int | 260 | static int wdt_close(struct inode *inode, struct file *file) |
| 270 | wdt_close(struct inode *inode, struct file *file) | ||
| 271 | { | 261 | { |
| 272 | if (expect_close == 42) { | 262 | if (expect_close == 42) |
| 273 | wdt_disable(); | 263 | wdt_disable(); |
| 274 | } else { | 264 | else { |
| 275 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 265 | printk(KERN_CRIT PFX |
| 266 | "Unexpected close, not stopping watchdog!\n"); | ||
| 276 | wdt_ping(); | 267 | wdt_ping(); |
| 277 | } | 268 | } |
| 278 | expect_close = 0; | 269 | expect_close = 0; |
| @@ -284,14 +275,12 @@ wdt_close(struct inode *inode, struct file *file) | |||
| 284 | * Notifier for system down | 275 | * Notifier for system down |
| 285 | */ | 276 | */ |
| 286 | 277 | ||
| 287 | static int | 278 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 288 | wdt_notify_sys(struct notifier_block *this, unsigned long code, | ||
| 289 | void *unused) | 279 | void *unused) |
| 290 | { | 280 | { |
| 291 | if (code == SYS_DOWN || code == SYS_HALT) { | 281 | if (code == SYS_DOWN || code == SYS_HALT) |
| 292 | /* Turn the WDT off */ | 282 | wdt_disable(); /* Turn the WDT off */ |
| 293 | wdt_disable(); | 283 | |
| 294 | } | ||
| 295 | return NOTIFY_DONE; | 284 | return NOTIFY_DONE; |
| 296 | } | 285 | } |
| 297 | 286 | ||
| @@ -303,7 +292,7 @@ static const struct file_operations wdt_fops = { | |||
| 303 | .owner = THIS_MODULE, | 292 | .owner = THIS_MODULE, |
| 304 | .llseek = no_llseek, | 293 | .llseek = no_llseek, |
| 305 | .write = wdt_write, | 294 | .write = wdt_write, |
| 306 | .ioctl = wdt_ioctl, | 295 | .unlocked_ioctl = wdt_ioctl, |
| 307 | .open = wdt_open, | 296 | .open = wdt_open, |
| 308 | .release = wdt_close, | 297 | .release = wdt_close, |
| 309 | }; | 298 | }; |
| @@ -323,8 +312,7 @@ static struct notifier_block wdt_notifier = { | |||
| 323 | .notifier_call = wdt_notify_sys, | 312 | .notifier_call = wdt_notify_sys, |
| 324 | }; | 313 | }; |
| 325 | 314 | ||
| 326 | static int __init | 315 | static int __init wdt_init(void) |
| 327 | wdt_init(void) | ||
| 328 | { | 316 | { |
| 329 | int ret; | 317 | int ret; |
| 330 | 318 | ||
| @@ -332,12 +320,13 @@ wdt_init(void) | |||
| 332 | 320 | ||
| 333 | if (wdt_set_heartbeat(timeout)) { | 321 | if (wdt_set_heartbeat(timeout)) { |
| 334 | wdt_set_heartbeat(WATCHDOG_TIMEOUT); | 322 | wdt_set_heartbeat(WATCHDOG_TIMEOUT); |
| 335 | printk (KERN_INFO PFX "timeout value must be 1<=timeout<=255, using %d\n", | 323 | printk(KERN_INFO PFX |
| 336 | WATCHDOG_TIMEOUT); | 324 | "timeout value must be 1 <= timeout <= 255, using %d\n", |
| 325 | WATCHDOG_TIMEOUT); | ||
| 337 | } | 326 | } |
| 338 | 327 | ||
| 339 | if (!request_region(wdt_io, 1, WATCHDOG_NAME)) { | 328 | if (!request_region(wdt_io, 1, WATCHDOG_NAME)) { |
| 340 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 329 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 341 | wdt_io); | 330 | wdt_io); |
| 342 | ret = -EIO; | 331 | ret = -EIO; |
| 343 | goto out; | 332 | goto out; |
| @@ -347,20 +336,22 @@ wdt_init(void) | |||
| 347 | 336 | ||
| 348 | ret = register_reboot_notifier(&wdt_notifier); | 337 | ret = register_reboot_notifier(&wdt_notifier); |
| 349 | if (ret != 0) { | 338 | if (ret != 0) { |
| 350 | printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 339 | printk(KERN_ERR PFX |
| 351 | ret); | 340 | "cannot register reboot notifier (err=%d)\n", ret); |
| 352 | goto unreg_regions; | 341 | goto unreg_regions; |
| 353 | } | 342 | } |
| 354 | 343 | ||
| 355 | ret = misc_register(&wdt_miscdev); | 344 | ret = misc_register(&wdt_miscdev); |
| 356 | if (ret != 0) { | 345 | if (ret != 0) { |
| 357 | printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 346 | printk(KERN_ERR PFX |
| 358 | WATCHDOG_MINOR, ret); | 347 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 348 | WATCHDOG_MINOR, ret); | ||
| 359 | goto unreg_reboot; | 349 | goto unreg_reboot; |
| 360 | } | 350 | } |
| 361 | 351 | ||
| 362 | printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", | 352 | printk(KERN_INFO PFX |
| 363 | timeout, nowayout); | 353 | "initialized. timeout=%d sec (nowayout=%d)\n", |
| 354 | timeout, nowayout); | ||
| 364 | 355 | ||
| 365 | out: | 356 | out: |
| 366 | return ret; | 357 | return ret; |
| @@ -371,12 +362,11 @@ unreg_regions: | |||
| 371 | goto out; | 362 | goto out; |
| 372 | } | 363 | } |
| 373 | 364 | ||
| 374 | static void __exit | 365 | static void __exit wdt_exit(void) |
| 375 | wdt_exit(void) | ||
| 376 | { | 366 | { |
| 377 | misc_deregister(&wdt_miscdev); | 367 | misc_deregister(&wdt_miscdev); |
| 378 | unregister_reboot_notifier(&wdt_notifier); | 368 | unregister_reboot_notifier(&wdt_notifier); |
| 379 | release_region(wdt_io,1); | 369 | release_region(wdt_io, 1); |
| 380 | } | 370 | } |
| 381 | 371 | ||
| 382 | module_init(wdt_init); | 372 | module_init(wdt_init); |
diff --git a/drivers/watchdog/w83697hf_wdt.c b/drivers/watchdog/w83697hf_wdt.c index 528b882420b6..445d30a01ed3 100644 --- a/drivers/watchdog/w83697hf_wdt.c +++ b/drivers/watchdog/w83697hf_wdt.c | |||
| @@ -36,9 +36,9 @@ | |||
| 36 | #include <linux/reboot.h> | 36 | #include <linux/reboot.h> |
| 37 | #include <linux/init.h> | 37 | #include <linux/init.h> |
| 38 | #include <linux/spinlock.h> | 38 | #include <linux/spinlock.h> |
| 39 | #include <linux/io.h> | ||
| 40 | #include <linux/uaccess.h> | ||
| 39 | 41 | ||
| 40 | #include <asm/io.h> | ||
| 41 | #include <asm/uaccess.h> | ||
| 42 | #include <asm/system.h> | 42 | #include <asm/system.h> |
| 43 | 43 | ||
| 44 | #define WATCHDOG_NAME "w83697hf/hg WDT" | 44 | #define WATCHDOG_NAME "w83697hf/hg WDT" |
| @@ -53,37 +53,43 @@ static DEFINE_SPINLOCK(io_lock); | |||
| 53 | /* You must set this - there is no sane way to probe for this board. */ | 53 | /* You must set this - there is no sane way to probe for this board. */ |
| 54 | static int wdt_io = 0x2e; | 54 | static int wdt_io = 0x2e; |
| 55 | module_param(wdt_io, int, 0); | 55 | module_param(wdt_io, int, 0); |
| 56 | MODULE_PARM_DESC(wdt_io, "w83697hf/hg WDT io port (default 0x2e, 0 = autodetect)"); | 56 | MODULE_PARM_DESC(wdt_io, |
| 57 | "w83697hf/hg WDT io port (default 0x2e, 0 = autodetect)"); | ||
| 57 | 58 | ||
| 58 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ | 59 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ |
| 59 | module_param(timeout, int, 0); | 60 | module_param(timeout, int, 0); |
| 60 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255 (default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 61 | MODULE_PARM_DESC(timeout, |
| 62 | "Watchdog timeout in seconds. 1<= timeout <=255 (default=" | ||
| 63 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 61 | 64 | ||
| 62 | static int nowayout = WATCHDOG_NOWAYOUT; | 65 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 63 | module_param(nowayout, int, 0); | 66 | module_param(nowayout, int, 0); |
| 64 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 67 | MODULE_PARM_DESC(nowayout, |
| 68 | "Watchdog cannot be stopped once started (default=" | ||
| 69 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 65 | 70 | ||
| 66 | static int early_disable = WATCHDOG_EARLY_DISABLE; | 71 | static int early_disable = WATCHDOG_EARLY_DISABLE; |
| 67 | module_param(early_disable, int, 0); | 72 | module_param(early_disable, int, 0); |
| 68 | MODULE_PARM_DESC(early_disable, "Watchdog gets disabled at boot time (default=" __MODULE_STRING(WATCHDOG_EARLY_DISABLE) ")"); | 73 | MODULE_PARM_DESC(early_disable, |
| 74 | "Watchdog gets disabled at boot time (default=" | ||
| 75 | __MODULE_STRING(WATCHDOG_EARLY_DISABLE) ")"); | ||
| 69 | 76 | ||
| 70 | /* | 77 | /* |
| 71 | * Kernel methods. | 78 | * Kernel methods. |
| 72 | */ | 79 | */ |
| 73 | 80 | ||
| 74 | #define W83697HF_EFER (wdt_io+0) /* Extended Function Enable Register */ | 81 | #define W83697HF_EFER (wdt_io + 0) /* Extended Function Enable Register */ |
| 75 | #define W83697HF_EFIR (wdt_io+0) /* Extended Function Index Register (same as EFER) */ | 82 | #define W83697HF_EFIR (wdt_io + 0) /* Extended Function Index Register |
| 76 | #define W83697HF_EFDR (wdt_io+1) /* Extended Function Data Register */ | 83 | (same as EFER) */ |
| 84 | #define W83697HF_EFDR (wdt_io + 1) /* Extended Function Data Register */ | ||
| 77 | 85 | ||
| 78 | static inline void | 86 | static inline void w83697hf_unlock(void) |
| 79 | w83697hf_unlock(void) | ||
| 80 | { | 87 | { |
| 81 | outb_p(0x87, W83697HF_EFER); /* Enter extended function mode */ | 88 | outb_p(0x87, W83697HF_EFER); /* Enter extended function mode */ |
| 82 | outb_p(0x87, W83697HF_EFER); /* Again according to manual */ | 89 | outb_p(0x87, W83697HF_EFER); /* Again according to manual */ |
| 83 | } | 90 | } |
| 84 | 91 | ||
| 85 | static inline void | 92 | static inline void w83697hf_lock(void) |
| 86 | w83697hf_lock(void) | ||
| 87 | { | 93 | { |
| 88 | outb_p(0xAA, W83697HF_EFER); /* Leave extended function mode */ | 94 | outb_p(0xAA, W83697HF_EFER); /* Leave extended function mode */ |
| 89 | } | 95 | } |
| @@ -93,41 +99,36 @@ w83697hf_lock(void) | |||
| 93 | * w83697hf_write_timeout() must be called with the device unlocked. | 99 | * w83697hf_write_timeout() must be called with the device unlocked. |
| 94 | */ | 100 | */ |
| 95 | 101 | ||
| 96 | static unsigned char | 102 | static unsigned char w83697hf_get_reg(unsigned char reg) |
| 97 | w83697hf_get_reg(unsigned char reg) | ||
| 98 | { | 103 | { |
| 99 | outb_p(reg, W83697HF_EFIR); | 104 | outb_p(reg, W83697HF_EFIR); |
| 100 | return inb_p(W83697HF_EFDR); | 105 | return inb_p(W83697HF_EFDR); |
| 101 | } | 106 | } |
| 102 | 107 | ||
| 103 | static void | 108 | static void w83697hf_set_reg(unsigned char reg, unsigned char data) |
| 104 | w83697hf_set_reg(unsigned char reg, unsigned char data) | ||
| 105 | { | 109 | { |
| 106 | outb_p(reg, W83697HF_EFIR); | 110 | outb_p(reg, W83697HF_EFIR); |
| 107 | outb_p(data, W83697HF_EFDR); | 111 | outb_p(data, W83697HF_EFDR); |
| 108 | } | 112 | } |
| 109 | 113 | ||
| 110 | static void | 114 | static void w83697hf_write_timeout(int timeout) |
| 111 | w83697hf_write_timeout(int timeout) | ||
| 112 | { | 115 | { |
| 113 | w83697hf_set_reg(0xF4, timeout); /* Write Timeout counter to CRF4 */ | 116 | /* Write Timeout counter to CRF4 */ |
| 117 | w83697hf_set_reg(0xF4, timeout); | ||
| 114 | } | 118 | } |
| 115 | 119 | ||
| 116 | static void | 120 | static void w83697hf_select_wdt(void) |
| 117 | w83697hf_select_wdt(void) | ||
| 118 | { | 121 | { |
| 119 | w83697hf_unlock(); | 122 | w83697hf_unlock(); |
| 120 | w83697hf_set_reg(0x07, 0x08); /* Switch to logic device 8 (GPIO2) */ | 123 | w83697hf_set_reg(0x07, 0x08); /* Switch to logic device 8 (GPIO2) */ |
| 121 | } | 124 | } |
| 122 | 125 | ||
| 123 | static inline void | 126 | static inline void w83697hf_deselect_wdt(void) |
| 124 | w83697hf_deselect_wdt(void) | ||
| 125 | { | 127 | { |
| 126 | w83697hf_lock(); | 128 | w83697hf_lock(); |
| 127 | } | 129 | } |
| 128 | 130 | ||
| 129 | static void | 131 | static void w83697hf_init(void) |
| 130 | w83697hf_init(void) | ||
| 131 | { | 132 | { |
| 132 | unsigned char bbuf; | 133 | unsigned char bbuf; |
| 133 | 134 | ||
| @@ -136,7 +137,9 @@ w83697hf_init(void) | |||
| 136 | bbuf = w83697hf_get_reg(0x29); | 137 | bbuf = w83697hf_get_reg(0x29); |
| 137 | bbuf &= ~0x60; | 138 | bbuf &= ~0x60; |
| 138 | bbuf |= 0x20; | 139 | bbuf |= 0x20; |
| 139 | w83697hf_set_reg(0x29, bbuf); /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ | 140 | |
| 141 | /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ | ||
| 142 | w83697hf_set_reg(0x29, bbuf); | ||
| 140 | 143 | ||
| 141 | bbuf = w83697hf_get_reg(0xF3); | 144 | bbuf = w83697hf_get_reg(0xF3); |
| 142 | bbuf &= ~0x04; | 145 | bbuf &= ~0x04; |
| @@ -145,8 +148,7 @@ w83697hf_init(void) | |||
| 145 | w83697hf_deselect_wdt(); | 148 | w83697hf_deselect_wdt(); |
| 146 | } | 149 | } |
| 147 | 150 | ||
| 148 | static void | 151 | static void wdt_ping(void) |
| 149 | wdt_ping(void) | ||
| 150 | { | 152 | { |
| 151 | spin_lock(&io_lock); | 153 | spin_lock(&io_lock); |
| 152 | w83697hf_select_wdt(); | 154 | w83697hf_select_wdt(); |
| @@ -157,8 +159,7 @@ wdt_ping(void) | |||
| 157 | spin_unlock(&io_lock); | 159 | spin_unlock(&io_lock); |
| 158 | } | 160 | } |
| 159 | 161 | ||
| 160 | static void | 162 | static void wdt_enable(void) |
| 161 | wdt_enable(void) | ||
| 162 | { | 163 | { |
| 163 | spin_lock(&io_lock); | 164 | spin_lock(&io_lock); |
| 164 | w83697hf_select_wdt(); | 165 | w83697hf_select_wdt(); |
| @@ -170,8 +171,7 @@ wdt_enable(void) | |||
| 170 | spin_unlock(&io_lock); | 171 | spin_unlock(&io_lock); |
| 171 | } | 172 | } |
| 172 | 173 | ||
| 173 | static void | 174 | static void wdt_disable(void) |
| 174 | wdt_disable(void) | ||
| 175 | { | 175 | { |
| 176 | spin_lock(&io_lock); | 176 | spin_lock(&io_lock); |
| 177 | w83697hf_select_wdt(); | 177 | w83697hf_select_wdt(); |
| @@ -183,8 +183,7 @@ wdt_disable(void) | |||
| 183 | spin_unlock(&io_lock); | 183 | spin_unlock(&io_lock); |
| 184 | } | 184 | } |
| 185 | 185 | ||
| 186 | static unsigned char | 186 | static unsigned char wdt_running(void) |
| 187 | wdt_running(void) | ||
| 188 | { | 187 | { |
| 189 | unsigned char t; | 188 | unsigned char t; |
| 190 | 189 | ||
| @@ -199,18 +198,17 @@ wdt_running(void) | |||
| 199 | return t; | 198 | return t; |
| 200 | } | 199 | } |
| 201 | 200 | ||
| 202 | static int | 201 | static int wdt_set_heartbeat(int t) |
| 203 | wdt_set_heartbeat(int t) | ||
| 204 | { | 202 | { |
| 205 | if ((t < 1) || (t > 255)) | 203 | if (t < 1 || t > 255) |
| 206 | return -EINVAL; | 204 | return -EINVAL; |
| 207 | 205 | ||
| 208 | timeout = t; | 206 | timeout = t; |
| 209 | return 0; | 207 | return 0; |
| 210 | } | 208 | } |
| 211 | 209 | ||
| 212 | static ssize_t | 210 | static ssize_t wdt_write(struct file *file, const char __user *buf, |
| 213 | wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | 211 | size_t count, loff_t *ppos) |
| 214 | { | 212 | { |
| 215 | if (count) { | 213 | if (count) { |
| 216 | if (!nowayout) { | 214 | if (!nowayout) { |
| @@ -220,7 +218,7 @@ wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | |||
| 220 | 218 | ||
| 221 | for (i = 0; i != count; i++) { | 219 | for (i = 0; i != count; i++) { |
| 222 | char c; | 220 | char c; |
| 223 | if (get_user(c, buf+i)) | 221 | if (get_user(c, buf + i)) |
| 224 | return -EFAULT; | 222 | return -EFAULT; |
| 225 | if (c == 'V') | 223 | if (c == 'V') |
| 226 | expect_close = 42; | 224 | expect_close = 42; |
| @@ -231,15 +229,14 @@ wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) | |||
| 231 | return count; | 229 | return count; |
| 232 | } | 230 | } |
| 233 | 231 | ||
| 234 | static int | 232 | static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 235 | wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | ||
| 236 | unsigned long arg) | ||
| 237 | { | 233 | { |
| 238 | void __user *argp = (void __user *)arg; | 234 | void __user *argp = (void __user *)arg; |
| 239 | int __user *p = argp; | 235 | int __user *p = argp; |
| 240 | int new_timeout; | 236 | int new_timeout; |
| 241 | static struct watchdog_info ident = { | 237 | static const struct watchdog_info ident = { |
| 242 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 238 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
| 239 | | WDIOF_MAGICCLOSE, | ||
| 243 | .firmware_version = 1, | 240 | .firmware_version = 1, |
| 244 | .identity = "W83697HF WDT", | 241 | .identity = "W83697HF WDT", |
| 245 | }; | 242 | }; |
| @@ -254,21 +251,6 @@ wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 254 | case WDIOC_GETBOOTSTATUS: | 251 | case WDIOC_GETBOOTSTATUS: |
| 255 | return put_user(0, p); | 252 | return put_user(0, p); |
| 256 | 253 | ||
| 257 | case WDIOC_KEEPALIVE: | ||
| 258 | wdt_ping(); | ||
| 259 | break; | ||
| 260 | |||
| 261 | case WDIOC_SETTIMEOUT: | ||
| 262 | if (get_user(new_timeout, p)) | ||
| 263 | return -EFAULT; | ||
| 264 | if (wdt_set_heartbeat(new_timeout)) | ||
| 265 | return -EINVAL; | ||
| 266 | wdt_ping(); | ||
| 267 | /* Fall */ | ||
| 268 | |||
| 269 | case WDIOC_GETTIMEOUT: | ||
| 270 | return put_user(timeout, p); | ||
| 271 | |||
| 272 | case WDIOC_SETOPTIONS: | 254 | case WDIOC_SETOPTIONS: |
| 273 | { | 255 | { |
| 274 | int options, retval = -EINVAL; | 256 | int options, retval = -EINVAL; |
| @@ -289,14 +271,28 @@ wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 289 | return retval; | 271 | return retval; |
| 290 | } | 272 | } |
| 291 | 273 | ||
| 274 | case WDIOC_KEEPALIVE: | ||
| 275 | wdt_ping(); | ||
| 276 | break; | ||
| 277 | |||
| 278 | case WDIOC_SETTIMEOUT: | ||
| 279 | if (get_user(new_timeout, p)) | ||
| 280 | return -EFAULT; | ||
| 281 | if (wdt_set_heartbeat(new_timeout)) | ||
| 282 | return -EINVAL; | ||
| 283 | wdt_ping(); | ||
| 284 | /* Fall */ | ||
| 285 | |||
| 286 | case WDIOC_GETTIMEOUT: | ||
| 287 | return put_user(timeout, p); | ||
| 288 | |||
| 292 | default: | 289 | default: |
| 293 | return -ENOTTY; | 290 | return -ENOTTY; |
| 294 | } | 291 | } |
| 295 | return 0; | 292 | return 0; |
| 296 | } | 293 | } |
| 297 | 294 | ||
| 298 | static int | 295 | static int wdt_open(struct inode *inode, struct file *file) |
| 299 | wdt_open(struct inode *inode, struct file *file) | ||
| 300 | { | 296 | { |
| 301 | if (test_and_set_bit(0, &wdt_is_open)) | 297 | if (test_and_set_bit(0, &wdt_is_open)) |
| 302 | return -EBUSY; | 298 | return -EBUSY; |
| @@ -308,13 +304,13 @@ wdt_open(struct inode *inode, struct file *file) | |||
| 308 | return nonseekable_open(inode, file); | 304 | return nonseekable_open(inode, file); |
| 309 | } | 305 | } |
| 310 | 306 | ||
| 311 | static int | 307 | static int wdt_close(struct inode *inode, struct file *file) |
| 312 | wdt_close(struct inode *inode, struct file *file) | ||
| 313 | { | 308 | { |
| 314 | if (expect_close == 42) { | 309 | if (expect_close == 42) |
| 315 | wdt_disable(); | 310 | wdt_disable(); |
| 316 | } else { | 311 | else { |
| 317 | printk (KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 312 | printk(KERN_CRIT PFX |
| 313 | "Unexpected close, not stopping watchdog!\n"); | ||
| 318 | wdt_ping(); | 314 | wdt_ping(); |
| 319 | } | 315 | } |
| 320 | expect_close = 0; | 316 | expect_close = 0; |
| @@ -326,14 +322,12 @@ wdt_close(struct inode *inode, struct file *file) | |||
| 326 | * Notifier for system down | 322 | * Notifier for system down |
| 327 | */ | 323 | */ |
| 328 | 324 | ||
| 329 | static int | 325 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 330 | wdt_notify_sys(struct notifier_block *this, unsigned long code, | ||
| 331 | void *unused) | 326 | void *unused) |
| 332 | { | 327 | { |
| 333 | if (code == SYS_DOWN || code == SYS_HALT) { | 328 | if (code == SYS_DOWN || code == SYS_HALT) |
| 334 | /* Turn the WDT off */ | 329 | wdt_disable(); /* Turn the WDT off */ |
| 335 | wdt_disable(); | 330 | |
| 336 | } | ||
| 337 | return NOTIFY_DONE; | 331 | return NOTIFY_DONE; |
| 338 | } | 332 | } |
| 339 | 333 | ||
| @@ -345,7 +339,7 @@ static const struct file_operations wdt_fops = { | |||
| 345 | .owner = THIS_MODULE, | 339 | .owner = THIS_MODULE, |
| 346 | .llseek = no_llseek, | 340 | .llseek = no_llseek, |
| 347 | .write = wdt_write, | 341 | .write = wdt_write, |
| 348 | .ioctl = wdt_ioctl, | 342 | .unlocked_ioctl = wdt_ioctl, |
| 349 | .open = wdt_open, | 343 | .open = wdt_open, |
| 350 | .release = wdt_close, | 344 | .release = wdt_close, |
| 351 | }; | 345 | }; |
| @@ -365,36 +359,38 @@ static struct notifier_block wdt_notifier = { | |||
| 365 | .notifier_call = wdt_notify_sys, | 359 | .notifier_call = wdt_notify_sys, |
| 366 | }; | 360 | }; |
| 367 | 361 | ||
| 368 | static int | 362 | static int w83697hf_check_wdt(void) |
| 369 | w83697hf_check_wdt(void) | ||
| 370 | { | 363 | { |
| 371 | if (!request_region(wdt_io, 2, WATCHDOG_NAME)) { | 364 | if (!request_region(wdt_io, 2, WATCHDOG_NAME)) { |
| 372 | printk (KERN_ERR PFX "I/O address 0x%x already in use\n", wdt_io); | 365 | printk(KERN_ERR PFX |
| 366 | "I/O address 0x%x already in use\n", wdt_io); | ||
| 373 | return -EIO; | 367 | return -EIO; |
| 374 | } | 368 | } |
| 375 | 369 | ||
| 376 | printk (KERN_DEBUG PFX "Looking for watchdog at address 0x%x\n", wdt_io); | 370 | printk(KERN_DEBUG PFX |
| 371 | "Looking for watchdog at address 0x%x\n", wdt_io); | ||
| 377 | w83697hf_unlock(); | 372 | w83697hf_unlock(); |
| 378 | if (w83697hf_get_reg(0x20) == 0x60) { | 373 | if (w83697hf_get_reg(0x20) == 0x60) { |
| 379 | printk (KERN_INFO PFX "watchdog found at address 0x%x\n", wdt_io); | 374 | printk(KERN_INFO PFX |
| 375 | "watchdog found at address 0x%x\n", wdt_io); | ||
| 380 | w83697hf_lock(); | 376 | w83697hf_lock(); |
| 381 | return 0; | 377 | return 0; |
| 382 | } | 378 | } |
| 383 | w83697hf_lock(); /* Reprotect in case it was a compatible device */ | 379 | /* Reprotect in case it was a compatible device */ |
| 380 | w83697hf_lock(); | ||
| 384 | 381 | ||
| 385 | printk (KERN_INFO PFX "watchdog not found at address 0x%x\n", wdt_io); | 382 | printk(KERN_INFO PFX "watchdog not found at address 0x%x\n", wdt_io); |
| 386 | release_region(wdt_io, 2); | 383 | release_region(wdt_io, 2); |
| 387 | return -EIO; | 384 | return -EIO; |
| 388 | } | 385 | } |
| 389 | 386 | ||
| 390 | static int w83697hf_ioports[] = { 0x2e, 0x4e, 0x00 }; | 387 | static int w83697hf_ioports[] = { 0x2e, 0x4e, 0x00 }; |
| 391 | 388 | ||
| 392 | static int __init | 389 | static int __init wdt_init(void) |
| 393 | wdt_init(void) | ||
| 394 | { | 390 | { |
| 395 | int ret, i, found = 0; | 391 | int ret, i, found = 0; |
| 396 | 392 | ||
| 397 | printk (KERN_INFO PFX "WDT driver for W83697HF/HG initializing\n"); | 393 | printk(KERN_INFO PFX "WDT driver for W83697HF/HG initializing\n"); |
| 398 | 394 | ||
| 399 | if (wdt_io == 0) { | 395 | if (wdt_io == 0) { |
| 400 | /* we will autodetect the W83697HF/HG watchdog */ | 396 | /* we will autodetect the W83697HF/HG watchdog */ |
| @@ -409,7 +405,7 @@ wdt_init(void) | |||
| 409 | } | 405 | } |
| 410 | 406 | ||
| 411 | if (!found) { | 407 | if (!found) { |
| 412 | printk (KERN_ERR PFX "No W83697HF/HG could be found\n"); | 408 | printk(KERN_ERR PFX "No W83697HF/HG could be found\n"); |
| 413 | ret = -EIO; | 409 | ret = -EIO; |
| 414 | goto out; | 410 | goto out; |
| 415 | } | 411 | } |
| @@ -417,31 +413,33 @@ wdt_init(void) | |||
| 417 | w83697hf_init(); | 413 | w83697hf_init(); |
| 418 | if (early_disable) { | 414 | if (early_disable) { |
| 419 | if (wdt_running()) | 415 | if (wdt_running()) |
| 420 | printk (KERN_WARNING PFX "Stopping previously enabled watchdog until userland kicks in\n"); | 416 | printk(KERN_WARNING PFX "Stopping previously enabled watchdog until userland kicks in\n"); |
| 421 | wdt_disable(); | 417 | wdt_disable(); |
| 422 | } | 418 | } |
| 423 | 419 | ||
| 424 | if (wdt_set_heartbeat(timeout)) { | 420 | if (wdt_set_heartbeat(timeout)) { |
| 425 | wdt_set_heartbeat(WATCHDOG_TIMEOUT); | 421 | wdt_set_heartbeat(WATCHDOG_TIMEOUT); |
| 426 | printk (KERN_INFO PFX "timeout value must be 1<=timeout<=255, using %d\n", | 422 | printk(KERN_INFO PFX |
| 427 | WATCHDOG_TIMEOUT); | 423 | "timeout value must be 1 <= timeout <= 255, using %d\n", |
| 424 | WATCHDOG_TIMEOUT); | ||
| 428 | } | 425 | } |
| 429 | 426 | ||
| 430 | ret = register_reboot_notifier(&wdt_notifier); | 427 | ret = register_reboot_notifier(&wdt_notifier); |
| 431 | if (ret != 0) { | 428 | if (ret != 0) { |
| 432 | printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 429 | printk(KERN_ERR PFX |
| 433 | ret); | 430 | "cannot register reboot notifier (err=%d)\n", ret); |
| 434 | goto unreg_regions; | 431 | goto unreg_regions; |
| 435 | } | 432 | } |
| 436 | 433 | ||
| 437 | ret = misc_register(&wdt_miscdev); | 434 | ret = misc_register(&wdt_miscdev); |
| 438 | if (ret != 0) { | 435 | if (ret != 0) { |
| 439 | printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 436 | printk(KERN_ERR PFX |
| 440 | WATCHDOG_MINOR, ret); | 437 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 438 | WATCHDOG_MINOR, ret); | ||
| 441 | goto unreg_reboot; | 439 | goto unreg_reboot; |
| 442 | } | 440 | } |
| 443 | 441 | ||
| 444 | printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", | 442 | printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", |
| 445 | timeout, nowayout); | 443 | timeout, nowayout); |
| 446 | 444 | ||
| 447 | out: | 445 | out: |
| @@ -453,8 +451,7 @@ unreg_regions: | |||
| 453 | goto out; | 451 | goto out; |
| 454 | } | 452 | } |
| 455 | 453 | ||
| 456 | static void __exit | 454 | static void __exit wdt_exit(void) |
| 457 | wdt_exit(void) | ||
| 458 | { | 455 | { |
| 459 | misc_deregister(&wdt_miscdev); | 456 | misc_deregister(&wdt_miscdev); |
| 460 | unregister_reboot_notifier(&wdt_notifier); | 457 | unregister_reboot_notifier(&wdt_notifier); |
diff --git a/drivers/watchdog/w83877f_wdt.c b/drivers/watchdog/w83877f_wdt.c index f510a3a595e6..24587d2060c4 100644 --- a/drivers/watchdog/w83877f_wdt.c +++ b/drivers/watchdog/w83877f_wdt.c | |||
| @@ -23,13 +23,16 @@ | |||
| 23 | * Added KERN_* tags to printks | 23 | * Added KERN_* tags to printks |
| 24 | * add CONFIG_WATCHDOG_NOWAYOUT support | 24 | * add CONFIG_WATCHDOG_NOWAYOUT support |
| 25 | * fix possible wdt_is_open race | 25 | * fix possible wdt_is_open race |
| 26 | * changed watchdog_info to correctly reflect what the driver offers | 26 | * changed watchdog_info to correctly reflect what |
| 27 | * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, WDIOC_SETTIMEOUT, | 27 | * the driver offers |
| 28 | * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, | ||
| 29 | * WDIOC_SETTIMEOUT, | ||
| 28 | * WDIOC_GETTIMEOUT, and WDIOC_SETOPTIONS ioctls | 30 | * WDIOC_GETTIMEOUT, and WDIOC_SETOPTIONS ioctls |
| 29 | * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces | 31 | * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces |
| 30 | * added extra printk's for startup problems | 32 | * added extra printk's for startup problems |
| 31 | * use module_param | 33 | * use module_param |
| 32 | * made timeout (the emulated heartbeat) a module_param | 34 | * made timeout (the emulated heartbeat) a |
| 35 | * module_param | ||
| 33 | * made the keepalive ping an internal subroutine | 36 | * made the keepalive ping an internal subroutine |
| 34 | * | 37 | * |
| 35 | * This WDT driver is different from most other Linux WDT | 38 | * This WDT driver is different from most other Linux WDT |
| @@ -51,8 +54,8 @@ | |||
| 51 | #include <linux/notifier.h> | 54 | #include <linux/notifier.h> |
| 52 | #include <linux/reboot.h> | 55 | #include <linux/reboot.h> |
| 53 | #include <linux/init.h> | 56 | #include <linux/init.h> |
| 54 | #include <asm/io.h> | 57 | #include <linux/io.h> |
| 55 | #include <asm/uaccess.h> | 58 | #include <linux/uaccess.h> |
| 56 | #include <asm/system.h> | 59 | #include <asm/system.h> |
| 57 | 60 | ||
| 58 | #define OUR_NAME "w83877f_wdt" | 61 | #define OUR_NAME "w83877f_wdt" |
| @@ -80,14 +83,19 @@ | |||
| 80 | */ | 83 | */ |
| 81 | 84 | ||
| 82 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ | 85 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ |
| 83 | static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ | 86 | /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ |
| 87 | static int timeout = WATCHDOG_TIMEOUT; | ||
| 84 | module_param(timeout, int, 0); | 88 | module_param(timeout, int, 0); |
| 85 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | 89 | MODULE_PARM_DESC(timeout, |
| 90 | "Watchdog timeout in seconds. (1<=timeout<=3600, default=" | ||
| 91 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | ||
| 86 | 92 | ||
| 87 | 93 | ||
| 88 | static int nowayout = WATCHDOG_NOWAYOUT; | 94 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 89 | module_param(nowayout, int, 0); | 95 | module_param(nowayout, int, 0); |
| 90 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 96 | MODULE_PARM_DESC(nowayout, |
| 97 | "Watchdog cannot be stopped once started (default=" | ||
| 98 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 91 | 99 | ||
| 92 | static void wdt_timer_ping(unsigned long); | 100 | static void wdt_timer_ping(unsigned long); |
| 93 | static DEFINE_TIMER(timer, wdt_timer_ping, 0, 0); | 101 | static DEFINE_TIMER(timer, wdt_timer_ping, 0, 0); |
| @@ -105,8 +113,7 @@ static void wdt_timer_ping(unsigned long data) | |||
| 105 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL | 113 | /* If we got a heartbeat pulse within the WDT_US_INTERVAL |
| 106 | * we agree to ping the WDT | 114 | * we agree to ping the WDT |
| 107 | */ | 115 | */ |
| 108 | if(time_before(jiffies, next_heartbeat)) | 116 | if (time_before(jiffies, next_heartbeat)) { |
| 109 | { | ||
| 110 | /* Ping the WDT */ | 117 | /* Ping the WDT */ |
| 111 | spin_lock(&wdt_spinlock); | 118 | spin_lock(&wdt_spinlock); |
| 112 | 119 | ||
| @@ -118,9 +125,9 @@ static void wdt_timer_ping(unsigned long data) | |||
| 118 | 125 | ||
| 119 | spin_unlock(&wdt_spinlock); | 126 | spin_unlock(&wdt_spinlock); |
| 120 | 127 | ||
| 121 | } else { | 128 | } else |
| 122 | printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); | 129 | printk(KERN_WARNING PFX |
| 123 | } | 130 | "Heartbeat lost! Will not ping the watchdog\n"); |
| 124 | } | 131 | } |
| 125 | 132 | ||
| 126 | /* | 133 | /* |
| @@ -181,22 +188,21 @@ static void wdt_keepalive(void) | |||
| 181 | * /dev/watchdog handling | 188 | * /dev/watchdog handling |
| 182 | */ | 189 | */ |
| 183 | 190 | ||
| 184 | static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) | 191 | static ssize_t fop_write(struct file *file, const char __user *buf, |
| 192 | size_t count, loff_t *ppos) | ||
| 185 | { | 193 | { |
| 186 | /* See if we got the magic character 'V' and reload the timer */ | 194 | /* See if we got the magic character 'V' and reload the timer */ |
| 187 | if(count) | 195 | if (count) { |
| 188 | { | 196 | if (!nowayout) { |
| 189 | if (!nowayout) | ||
| 190 | { | ||
| 191 | size_t ofs; | 197 | size_t ofs; |
| 192 | 198 | ||
| 193 | /* note: just in case someone wrote the magic character | 199 | /* note: just in case someone wrote the magic |
| 194 | * five months ago... */ | 200 | character five months ago... */ |
| 195 | wdt_expect_close = 0; | 201 | wdt_expect_close = 0; |
| 196 | 202 | ||
| 197 | /* scan to see whether or not we got the magic character */ | 203 | /* scan to see whether or not we got the |
| 198 | for(ofs = 0; ofs != count; ofs++) | 204 | magic character */ |
| 199 | { | 205 | for (ofs = 0; ofs != count; ofs++) { |
| 200 | char c; | 206 | char c; |
| 201 | if (get_user(c, buf + ofs)) | 207 | if (get_user(c, buf + ofs)) |
| 202 | return -EFAULT; | 208 | return -EFAULT; |
| @@ -211,10 +217,10 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou | |||
| 211 | return count; | 217 | return count; |
| 212 | } | 218 | } |
| 213 | 219 | ||
| 214 | static int fop_open(struct inode * inode, struct file * file) | 220 | static int fop_open(struct inode *inode, struct file *file) |
| 215 | { | 221 | { |
| 216 | /* Just in case we're already talking to someone... */ | 222 | /* Just in case we're already talking to someone... */ |
| 217 | if(test_and_set_bit(0, &wdt_is_open)) | 223 | if (test_and_set_bit(0, &wdt_is_open)) |
| 218 | return -EBUSY; | 224 | return -EBUSY; |
| 219 | 225 | ||
| 220 | /* Good, fire up the show */ | 226 | /* Good, fire up the show */ |
| @@ -222,78 +228,78 @@ static int fop_open(struct inode * inode, struct file * file) | |||
| 222 | return nonseekable_open(inode, file); | 228 | return nonseekable_open(inode, file); |
| 223 | } | 229 | } |
| 224 | 230 | ||
| 225 | static int fop_close(struct inode * inode, struct file * file) | 231 | static int fop_close(struct inode *inode, struct file *file) |
| 226 | { | 232 | { |
| 227 | if(wdt_expect_close == 42) | 233 | if (wdt_expect_close == 42) |
| 228 | wdt_turnoff(); | 234 | wdt_turnoff(); |
| 229 | else { | 235 | else { |
| 230 | del_timer(&timer); | 236 | del_timer(&timer); |
| 231 | printk(KERN_CRIT PFX "device file closed unexpectedly. Will not stop the WDT!\n"); | 237 | printk(KERN_CRIT PFX |
| 238 | "device file closed unexpectedly. Will not stop the WDT!\n"); | ||
| 232 | } | 239 | } |
| 233 | clear_bit(0, &wdt_is_open); | 240 | clear_bit(0, &wdt_is_open); |
| 234 | wdt_expect_close = 0; | 241 | wdt_expect_close = 0; |
| 235 | return 0; | 242 | return 0; |
| 236 | } | 243 | } |
| 237 | 244 | ||
| 238 | static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 245 | static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 239 | unsigned long arg) | ||
| 240 | { | 246 | { |
| 241 | void __user *argp = (void __user *)arg; | 247 | void __user *argp = (void __user *)arg; |
| 242 | int __user *p = argp; | 248 | int __user *p = argp; |
| 243 | static struct watchdog_info ident= | 249 | static const struct watchdog_info ident = { |
| 244 | { | 250 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
| 245 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 251 | | WDIOF_MAGICCLOSE, |
| 246 | .firmware_version = 1, | 252 | .firmware_version = 1, |
| 247 | .identity = "W83877F", | 253 | .identity = "W83877F", |
| 248 | }; | 254 | }; |
| 249 | 255 | ||
| 250 | switch(cmd) | 256 | switch (cmd) { |
| 257 | case WDIOC_GETSUPPORT: | ||
| 258 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 259 | case WDIOC_GETSTATUS: | ||
| 260 | case WDIOC_GETBOOTSTATUS: | ||
| 261 | return put_user(0, p); | ||
| 262 | case WDIOC_SETOPTIONS: | ||
| 251 | { | 263 | { |
| 252 | default: | 264 | int new_options, retval = -EINVAL; |
| 253 | return -ENOTTY; | ||
| 254 | case WDIOC_GETSUPPORT: | ||
| 255 | return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; | ||
| 256 | case WDIOC_GETSTATUS: | ||
| 257 | case WDIOC_GETBOOTSTATUS: | ||
| 258 | return put_user(0, p); | ||
| 259 | case WDIOC_KEEPALIVE: | ||
| 260 | wdt_keepalive(); | ||
| 261 | return 0; | ||
| 262 | case WDIOC_SETOPTIONS: | ||
| 263 | { | ||
| 264 | int new_options, retval = -EINVAL; | ||
| 265 | |||
| 266 | if(get_user(new_options, p)) | ||
| 267 | return -EFAULT; | ||
| 268 | |||
| 269 | if(new_options & WDIOS_DISABLECARD) { | ||
| 270 | wdt_turnoff(); | ||
| 271 | retval = 0; | ||
| 272 | } | ||
| 273 | 265 | ||
| 274 | if(new_options & WDIOS_ENABLECARD) { | 266 | if (get_user(new_options, p)) |
| 275 | wdt_startup(); | 267 | return -EFAULT; |
| 276 | retval = 0; | ||
| 277 | } | ||
| 278 | 268 | ||
| 279 | return retval; | 269 | if (new_options & WDIOS_DISABLECARD) { |
| 270 | wdt_turnoff(); | ||
| 271 | retval = 0; | ||
| 280 | } | 272 | } |
| 281 | case WDIOC_SETTIMEOUT: | ||
| 282 | { | ||
| 283 | int new_timeout; | ||
| 284 | 273 | ||
| 285 | if(get_user(new_timeout, p)) | 274 | if (new_options & WDIOS_ENABLECARD) { |
| 286 | return -EFAULT; | 275 | wdt_startup(); |
| 276 | retval = 0; | ||
| 277 | } | ||
| 287 | 278 | ||
| 288 | if(new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */ | 279 | return retval; |
| 289 | return -EINVAL; | 280 | } |
| 281 | case WDIOC_KEEPALIVE: | ||
| 282 | wdt_keepalive(); | ||
| 283 | return 0; | ||
| 284 | case WDIOC_SETTIMEOUT: | ||
| 285 | { | ||
| 286 | int new_timeout; | ||
| 290 | 287 | ||
| 291 | timeout = new_timeout; | 288 | if (get_user(new_timeout, p)) |
| 292 | wdt_keepalive(); | 289 | return -EFAULT; |
| 293 | /* Fall through */ | 290 | |
| 294 | } | 291 | /* arbitrary upper limit */ |
| 295 | case WDIOC_GETTIMEOUT: | 292 | if (new_timeout < 1 || new_timeout > 3600) |
| 296 | return put_user(timeout, p); | 293 | return -EINVAL; |
| 294 | |||
| 295 | timeout = new_timeout; | ||
| 296 | wdt_keepalive(); | ||
| 297 | /* Fall through */ | ||
| 298 | } | ||
| 299 | case WDIOC_GETTIMEOUT: | ||
| 300 | return put_user(timeout, p); | ||
| 301 | default: | ||
| 302 | return -ENOTTY; | ||
| 297 | } | 303 | } |
| 298 | } | 304 | } |
| 299 | 305 | ||
| @@ -303,7 +309,7 @@ static const struct file_operations wdt_fops = { | |||
| 303 | .write = fop_write, | 309 | .write = fop_write, |
| 304 | .open = fop_open, | 310 | .open = fop_open, |
| 305 | .release = fop_close, | 311 | .release = fop_close, |
| 306 | .ioctl = fop_ioctl, | 312 | .unlocked_ioctl = fop_ioctl, |
| 307 | }; | 313 | }; |
| 308 | 314 | ||
| 309 | static struct miscdevice wdt_miscdev = { | 315 | static struct miscdevice wdt_miscdev = { |
| @@ -319,7 +325,7 @@ static struct miscdevice wdt_miscdev = { | |||
| 319 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | 325 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 320 | void *unused) | 326 | void *unused) |
| 321 | { | 327 | { |
| 322 | if(code==SYS_DOWN || code==SYS_HALT) | 328 | if (code == SYS_DOWN || code == SYS_HALT) |
| 323 | wdt_turnoff(); | 329 | wdt_turnoff(); |
| 324 | return NOTIFY_DONE; | 330 | return NOTIFY_DONE; |
| 325 | } | 331 | } |
| @@ -329,8 +335,7 @@ static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |||
| 329 | * turn the timebomb registers off. | 335 | * turn the timebomb registers off. |
| 330 | */ | 336 | */ |
| 331 | 337 | ||
| 332 | static struct notifier_block wdt_notifier= | 338 | static struct notifier_block wdt_notifier = { |
| 333 | { | ||
| 334 | .notifier_call = wdt_notify_sys, | 339 | .notifier_call = wdt_notify_sys, |
| 335 | }; | 340 | }; |
| 336 | 341 | ||
| @@ -342,31 +347,29 @@ static void __exit w83877f_wdt_unload(void) | |||
| 342 | misc_deregister(&wdt_miscdev); | 347 | misc_deregister(&wdt_miscdev); |
| 343 | 348 | ||
| 344 | unregister_reboot_notifier(&wdt_notifier); | 349 | unregister_reboot_notifier(&wdt_notifier); |
| 345 | release_region(WDT_PING,1); | 350 | release_region(WDT_PING, 1); |
| 346 | release_region(ENABLE_W83877F_PORT,2); | 351 | release_region(ENABLE_W83877F_PORT, 2); |
| 347 | } | 352 | } |
| 348 | 353 | ||
| 349 | static int __init w83877f_wdt_init(void) | 354 | static int __init w83877f_wdt_init(void) |
| 350 | { | 355 | { |
| 351 | int rc = -EBUSY; | 356 | int rc = -EBUSY; |
| 352 | 357 | ||
| 353 | if(timeout < 1 || timeout > 3600) /* arbitrary upper limit */ | 358 | if (timeout < 1 || timeout > 3600) { /* arbitrary upper limit */ |
| 354 | { | ||
| 355 | timeout = WATCHDOG_TIMEOUT; | 359 | timeout = WATCHDOG_TIMEOUT; |
| 356 | printk(KERN_INFO PFX "timeout value must be 1<=x<=3600, using %d\n", | 360 | printk(KERN_INFO PFX |
| 357 | timeout); | 361 | "timeout value must be 1 <= x <= 3600, using %d\n", |
| 362 | timeout); | ||
| 358 | } | 363 | } |
| 359 | 364 | ||
| 360 | if (!request_region(ENABLE_W83877F_PORT, 2, "W83877F WDT")) | 365 | if (!request_region(ENABLE_W83877F_PORT, 2, "W83877F WDT")) { |
| 361 | { | ||
| 362 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 366 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 363 | ENABLE_W83877F_PORT); | 367 | ENABLE_W83877F_PORT); |
| 364 | rc = -EIO; | 368 | rc = -EIO; |
| 365 | goto err_out; | 369 | goto err_out; |
| 366 | } | 370 | } |
| 367 | 371 | ||
| 368 | if (!request_region(WDT_PING, 1, "W8387FF WDT")) | 372 | if (!request_region(WDT_PING, 1, "W8387FF WDT")) { |
| 369 | { | ||
| 370 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 373 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 371 | WDT_PING); | 374 | WDT_PING); |
| 372 | rc = -EIO; | 375 | rc = -EIO; |
| @@ -374,22 +377,22 @@ static int __init w83877f_wdt_init(void) | |||
| 374 | } | 377 | } |
| 375 | 378 | ||
| 376 | rc = register_reboot_notifier(&wdt_notifier); | 379 | rc = register_reboot_notifier(&wdt_notifier); |
| 377 | if (rc) | 380 | if (rc) { |
| 378 | { | 381 | printk(KERN_ERR PFX |
| 379 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 382 | "cannot register reboot notifier (err=%d)\n", rc); |
| 380 | rc); | ||
| 381 | goto err_out_region2; | 383 | goto err_out_region2; |
| 382 | } | 384 | } |
| 383 | 385 | ||
| 384 | rc = misc_register(&wdt_miscdev); | 386 | rc = misc_register(&wdt_miscdev); |
| 385 | if (rc) | 387 | if (rc) { |
| 386 | { | 388 | printk(KERN_ERR PFX |
| 387 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 389 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 388 | wdt_miscdev.minor, rc); | 390 | wdt_miscdev.minor, rc); |
| 389 | goto err_out_reboot; | 391 | goto err_out_reboot; |
| 390 | } | 392 | } |
| 391 | 393 | ||
| 392 | printk(KERN_INFO PFX "WDT driver for W83877F initialised. timeout=%d sec (nowayout=%d)\n", | 394 | printk(KERN_INFO PFX |
| 395 | "WDT driver for W83877F initialised. timeout=%d sec (nowayout=%d)\n", | ||
| 393 | timeout, nowayout); | 396 | timeout, nowayout); |
| 394 | 397 | ||
| 395 | return 0; | 398 | return 0; |
| @@ -397,9 +400,9 @@ static int __init w83877f_wdt_init(void) | |||
| 397 | err_out_reboot: | 400 | err_out_reboot: |
| 398 | unregister_reboot_notifier(&wdt_notifier); | 401 | unregister_reboot_notifier(&wdt_notifier); |
| 399 | err_out_region2: | 402 | err_out_region2: |
| 400 | release_region(WDT_PING,1); | 403 | release_region(WDT_PING, 1); |
| 401 | err_out_region1: | 404 | err_out_region1: |
| 402 | release_region(ENABLE_W83877F_PORT,2); | 405 | release_region(ENABLE_W83877F_PORT, 2); |
| 403 | err_out: | 406 | err_out: |
| 404 | return rc; | 407 | return rc; |
| 405 | } | 408 | } |
diff --git a/drivers/watchdog/w83977f_wdt.c b/drivers/watchdog/w83977f_wdt.c index b209bcd7f789..2525da5080ca 100644 --- a/drivers/watchdog/w83977f_wdt.c +++ b/drivers/watchdog/w83977f_wdt.c | |||
| @@ -26,10 +26,10 @@ | |||
| 26 | #include <linux/watchdog.h> | 26 | #include <linux/watchdog.h> |
| 27 | #include <linux/notifier.h> | 27 | #include <linux/notifier.h> |
| 28 | #include <linux/reboot.h> | 28 | #include <linux/reboot.h> |
| 29 | #include <linux/uaccess.h> | ||
| 30 | #include <linux/io.h> | ||
| 29 | 31 | ||
| 30 | #include <asm/io.h> | ||
| 31 | #include <asm/system.h> | 32 | #include <asm/system.h> |
| 32 | #include <asm/uaccess.h> | ||
| 33 | 33 | ||
| 34 | #define WATCHDOG_VERSION "1.00" | 34 | #define WATCHDOG_VERSION "1.00" |
| 35 | #define WATCHDOG_NAME "W83977F WDT" | 35 | #define WATCHDOG_NAME "W83977F WDT" |
| @@ -53,13 +53,17 @@ static char expect_close; | |||
| 53 | static DEFINE_SPINLOCK(spinlock); | 53 | static DEFINE_SPINLOCK(spinlock); |
| 54 | 54 | ||
| 55 | module_param(timeout, int, 0); | 55 | module_param(timeout, int, 0); |
| 56 | MODULE_PARM_DESC(timeout,"Watchdog timeout in seconds (15..7635), default=" __MODULE_STRING(DEFAULT_TIMEOUT) ")"); | 56 | MODULE_PARM_DESC(timeout, |
| 57 | "Watchdog timeout in seconds (15..7635), default=" | ||
| 58 | __MODULE_STRING(DEFAULT_TIMEOUT) ")"); | ||
| 57 | module_param(testmode, int, 0); | 59 | module_param(testmode, int, 0); |
| 58 | MODULE_PARM_DESC(testmode,"Watchdog testmode (1 = no reboot), default=0"); | 60 | MODULE_PARM_DESC(testmode, "Watchdog testmode (1 = no reboot), default=0"); |
| 59 | 61 | ||
| 60 | static int nowayout = WATCHDOG_NOWAYOUT; | 62 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 61 | module_param(nowayout, int, 0); | 63 | module_param(nowayout, int, 0); |
| 62 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 64 | MODULE_PARM_DESC(nowayout, |
| 65 | "Watchdog cannot be stopped once started (default=" | ||
| 66 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 63 | 67 | ||
| 64 | /* | 68 | /* |
| 65 | * Start the watchdog | 69 | * Start the watchdog |
| @@ -72,8 +76,8 @@ static int wdt_start(void) | |||
| 72 | spin_lock_irqsave(&spinlock, flags); | 76 | spin_lock_irqsave(&spinlock, flags); |
| 73 | 77 | ||
| 74 | /* Unlock the SuperIO chip */ | 78 | /* Unlock the SuperIO chip */ |
| 75 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 79 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 76 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 80 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 77 | 81 | ||
| 78 | /* | 82 | /* |
| 79 | * Select device Aux2 (device=8) to set watchdog regs F2, F3 and F4. | 83 | * Select device Aux2 (device=8) to set watchdog regs F2, F3 and F4. |
| @@ -81,50 +85,49 @@ static int wdt_start(void) | |||
| 81 | * F3 is set to enable watchdog LED blink at timeout. | 85 | * F3 is set to enable watchdog LED blink at timeout. |
| 82 | * F4 is used to just clear the TIMEOUT'ed state (bit 0). | 86 | * F4 is used to just clear the TIMEOUT'ed state (bit 0). |
| 83 | */ | 87 | */ |
| 84 | outb_p(DEVICE_REGISTER,IO_INDEX_PORT); | 88 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 85 | outb_p(0x08,IO_DATA_PORT); | 89 | outb_p(0x08, IO_DATA_PORT); |
| 86 | outb_p(0xF2,IO_INDEX_PORT); | 90 | outb_p(0xF2, IO_INDEX_PORT); |
| 87 | outb_p(timeoutW,IO_DATA_PORT); | 91 | outb_p(timeoutW, IO_DATA_PORT); |
| 88 | outb_p(0xF3,IO_INDEX_PORT); | 92 | outb_p(0xF3, IO_INDEX_PORT); |
| 89 | outb_p(0x08,IO_DATA_PORT); | 93 | outb_p(0x08, IO_DATA_PORT); |
| 90 | outb_p(0xF4,IO_INDEX_PORT); | 94 | outb_p(0xF4, IO_INDEX_PORT); |
| 91 | outb_p(0x00,IO_DATA_PORT); | 95 | outb_p(0x00, IO_DATA_PORT); |
| 92 | 96 | ||
| 93 | /* Set device Aux2 active */ | 97 | /* Set device Aux2 active */ |
| 94 | outb_p(0x30,IO_INDEX_PORT); | 98 | outb_p(0x30, IO_INDEX_PORT); |
| 95 | outb_p(0x01,IO_DATA_PORT); | 99 | outb_p(0x01, IO_DATA_PORT); |
| 96 | 100 | ||
| 97 | /* | 101 | /* |
| 98 | * Select device Aux1 (dev=7) to set GP16 as the watchdog output | 102 | * Select device Aux1 (dev=7) to set GP16 as the watchdog output |
| 99 | * (in reg E6) and GP13 as the watchdog LED output (in reg E3). | 103 | * (in reg E6) and GP13 as the watchdog LED output (in reg E3). |
| 100 | * Map GP16 at pin 119. | 104 | * Map GP16 at pin 119. |
| 101 | * In test mode watch the bit 0 on F4 to indicate "triggered" or | 105 | * In test mode watch the bit 0 on F4 to indicate "triggered" or |
| 102 | * check watchdog LED on SBC. | 106 | * check watchdog LED on SBC. |
| 103 | */ | 107 | */ |
| 104 | outb_p(DEVICE_REGISTER,IO_INDEX_PORT); | 108 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 105 | outb_p(0x07,IO_DATA_PORT); | 109 | outb_p(0x07, IO_DATA_PORT); |
| 106 | if (!testmode) | 110 | if (!testmode) { |
| 107 | { | ||
| 108 | unsigned pin_map; | 111 | unsigned pin_map; |
| 109 | 112 | ||
| 110 | outb_p(0xE6,IO_INDEX_PORT); | 113 | outb_p(0xE6, IO_INDEX_PORT); |
| 111 | outb_p(0x0A,IO_DATA_PORT); | 114 | outb_p(0x0A, IO_DATA_PORT); |
| 112 | outb_p(0x2C,IO_INDEX_PORT); | 115 | outb_p(0x2C, IO_INDEX_PORT); |
| 113 | pin_map = inb_p(IO_DATA_PORT); | 116 | pin_map = inb_p(IO_DATA_PORT); |
| 114 | pin_map |= 0x10; | 117 | pin_map |= 0x10; |
| 115 | pin_map &= ~(0x20); | 118 | pin_map &= ~(0x20); |
| 116 | outb_p(0x2C,IO_INDEX_PORT); | 119 | outb_p(0x2C, IO_INDEX_PORT); |
| 117 | outb_p(pin_map,IO_DATA_PORT); | 120 | outb_p(pin_map, IO_DATA_PORT); |
| 118 | } | 121 | } |
| 119 | outb_p(0xE3,IO_INDEX_PORT); | 122 | outb_p(0xE3, IO_INDEX_PORT); |
| 120 | outb_p(0x08,IO_DATA_PORT); | 123 | outb_p(0x08, IO_DATA_PORT); |
| 121 | 124 | ||
| 122 | /* Set device Aux1 active */ | 125 | /* Set device Aux1 active */ |
| 123 | outb_p(0x30,IO_INDEX_PORT); | 126 | outb_p(0x30, IO_INDEX_PORT); |
| 124 | outb_p(0x01,IO_DATA_PORT); | 127 | outb_p(0x01, IO_DATA_PORT); |
| 125 | 128 | ||
| 126 | /* Lock the SuperIO chip */ | 129 | /* Lock the SuperIO chip */ |
| 127 | outb_p(LOCK_DATA,IO_INDEX_PORT); | 130 | outb_p(LOCK_DATA, IO_INDEX_PORT); |
| 128 | 131 | ||
| 129 | spin_unlock_irqrestore(&spinlock, flags); | 132 | spin_unlock_irqrestore(&spinlock, flags); |
| 130 | 133 | ||
| @@ -144,42 +147,41 @@ static int wdt_stop(void) | |||
| 144 | spin_lock_irqsave(&spinlock, flags); | 147 | spin_lock_irqsave(&spinlock, flags); |
| 145 | 148 | ||
| 146 | /* Unlock the SuperIO chip */ | 149 | /* Unlock the SuperIO chip */ |
| 147 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 150 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 148 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 151 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 149 | 152 | ||
| 150 | /* | 153 | /* |
| 151 | * Select device Aux2 (device=8) to set watchdog regs F2, F3 and F4. | 154 | * Select device Aux2 (device=8) to set watchdog regs F2, F3 and F4. |
| 152 | * F2 is reset to its default value (watchdog timer disabled). | 155 | * F2 is reset to its default value (watchdog timer disabled). |
| 153 | * F3 is reset to its default state. | 156 | * F3 is reset to its default state. |
| 154 | * F4 clears the TIMEOUT'ed state (bit 0) - back to default. | 157 | * F4 clears the TIMEOUT'ed state (bit 0) - back to default. |
| 155 | */ | 158 | */ |
| 156 | outb_p(DEVICE_REGISTER,IO_INDEX_PORT); | 159 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 157 | outb_p(0x08,IO_DATA_PORT); | 160 | outb_p(0x08, IO_DATA_PORT); |
| 158 | outb_p(0xF2,IO_INDEX_PORT); | 161 | outb_p(0xF2, IO_INDEX_PORT); |
| 159 | outb_p(0xFF,IO_DATA_PORT); | 162 | outb_p(0xFF, IO_DATA_PORT); |
| 160 | outb_p(0xF3,IO_INDEX_PORT); | 163 | outb_p(0xF3, IO_INDEX_PORT); |
| 161 | outb_p(0x00,IO_DATA_PORT); | 164 | outb_p(0x00, IO_DATA_PORT); |
| 162 | outb_p(0xF4,IO_INDEX_PORT); | 165 | outb_p(0xF4, IO_INDEX_PORT); |
| 163 | outb_p(0x00,IO_DATA_PORT); | 166 | outb_p(0x00, IO_DATA_PORT); |
| 164 | outb_p(0xF2,IO_INDEX_PORT); | 167 | outb_p(0xF2, IO_INDEX_PORT); |
| 165 | outb_p(0x00,IO_DATA_PORT); | 168 | outb_p(0x00, IO_DATA_PORT); |
| 166 | 169 | ||
| 167 | /* | 170 | /* |
| 168 | * Select device Aux1 (dev=7) to set GP16 (in reg E6) and | 171 | * Select device Aux1 (dev=7) to set GP16 (in reg E6) and |
| 169 | * Gp13 (in reg E3) as inputs. | 172 | * Gp13 (in reg E3) as inputs. |
| 170 | */ | 173 | */ |
| 171 | outb_p(DEVICE_REGISTER,IO_INDEX_PORT); | 174 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 172 | outb_p(0x07,IO_DATA_PORT); | 175 | outb_p(0x07, IO_DATA_PORT); |
| 173 | if (!testmode) | 176 | if (!testmode) { |
| 174 | { | 177 | outb_p(0xE6, IO_INDEX_PORT); |
| 175 | outb_p(0xE6,IO_INDEX_PORT); | 178 | outb_p(0x01, IO_DATA_PORT); |
| 176 | outb_p(0x01,IO_DATA_PORT); | ||
| 177 | } | 179 | } |
| 178 | outb_p(0xE3,IO_INDEX_PORT); | 180 | outb_p(0xE3, IO_INDEX_PORT); |
| 179 | outb_p(0x01,IO_DATA_PORT); | 181 | outb_p(0x01, IO_DATA_PORT); |
| 180 | 182 | ||
| 181 | /* Lock the SuperIO chip */ | 183 | /* Lock the SuperIO chip */ |
| 182 | outb_p(LOCK_DATA,IO_INDEX_PORT); | 184 | outb_p(LOCK_DATA, IO_INDEX_PORT); |
| 183 | 185 | ||
| 184 | spin_unlock_irqrestore(&spinlock, flags); | 186 | spin_unlock_irqrestore(&spinlock, flags); |
| 185 | 187 | ||
| @@ -200,17 +202,17 @@ static int wdt_keepalive(void) | |||
| 200 | spin_lock_irqsave(&spinlock, flags); | 202 | spin_lock_irqsave(&spinlock, flags); |
| 201 | 203 | ||
| 202 | /* Unlock the SuperIO chip */ | 204 | /* Unlock the SuperIO chip */ |
| 203 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 205 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 204 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 206 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 205 | 207 | ||
| 206 | /* Select device Aux2 (device=8) to kick watchdog reg F2 */ | 208 | /* Select device Aux2 (device=8) to kick watchdog reg F2 */ |
| 207 | outb_p(DEVICE_REGISTER,IO_INDEX_PORT); | 209 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 208 | outb_p(0x08,IO_DATA_PORT); | 210 | outb_p(0x08, IO_DATA_PORT); |
| 209 | outb_p(0xF2,IO_INDEX_PORT); | 211 | outb_p(0xF2, IO_INDEX_PORT); |
| 210 | outb_p(timeoutW,IO_DATA_PORT); | 212 | outb_p(timeoutW, IO_DATA_PORT); |
| 211 | 213 | ||
| 212 | /* Lock the SuperIO chip */ | 214 | /* Lock the SuperIO chip */ |
| 213 | outb_p(LOCK_DATA,IO_INDEX_PORT); | 215 | outb_p(LOCK_DATA, IO_INDEX_PORT); |
| 214 | 216 | ||
| 215 | spin_unlock_irqrestore(&spinlock, flags); | 217 | spin_unlock_irqrestore(&spinlock, flags); |
| 216 | 218 | ||
| @@ -227,7 +229,7 @@ static int wdt_set_timeout(int t) | |||
| 227 | 229 | ||
| 228 | /* | 230 | /* |
| 229 | * Convert seconds to watchdog counter time units, rounding up. | 231 | * Convert seconds to watchdog counter time units, rounding up. |
| 230 | * On PCM-5335 watchdog units are 30 seconds/step with 15 sec startup | 232 | * On PCM-5335 watchdog units are 30 seconds/step with 15 sec startup |
| 231 | * value. This information is supplied in the PCM-5335 manual and was | 233 | * value. This information is supplied in the PCM-5335 manual and was |
| 232 | * checked by me on a real board. This is a bit strange because W83977f | 234 | * checked by me on a real board. This is a bit strange because W83977f |
| 233 | * datasheet says counter unit is in minutes! | 235 | * datasheet says counter unit is in minutes! |
| @@ -241,7 +243,7 @@ static int wdt_set_timeout(int t) | |||
| 241 | return -EINVAL; | 243 | return -EINVAL; |
| 242 | 244 | ||
| 243 | /* | 245 | /* |
| 244 | * timeout is the timeout in seconds, | 246 | * timeout is the timeout in seconds, |
| 245 | * timeoutW is the timeout in watchdog counter units. | 247 | * timeoutW is the timeout in watchdog counter units. |
| 246 | */ | 248 | */ |
| 247 | timeoutW = tmrval; | 249 | timeoutW = tmrval; |
| @@ -261,17 +263,17 @@ static int wdt_get_status(int *status) | |||
| 261 | spin_lock_irqsave(&spinlock, flags); | 263 | spin_lock_irqsave(&spinlock, flags); |
| 262 | 264 | ||
| 263 | /* Unlock the SuperIO chip */ | 265 | /* Unlock the SuperIO chip */ |
| 264 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 266 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 265 | outb_p(UNLOCK_DATA,IO_INDEX_PORT); | 267 | outb_p(UNLOCK_DATA, IO_INDEX_PORT); |
| 266 | 268 | ||
| 267 | /* Select device Aux2 (device=8) to read watchdog reg F4 */ | 269 | /* Select device Aux2 (device=8) to read watchdog reg F4 */ |
| 268 | outb_p(DEVICE_REGISTER,IO_INDEX_PORT); | 270 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 269 | outb_p(0x08,IO_DATA_PORT); | 271 | outb_p(0x08, IO_DATA_PORT); |
| 270 | outb_p(0xF4,IO_INDEX_PORT); | 272 | outb_p(0xF4, IO_INDEX_PORT); |
| 271 | new_status = inb_p(IO_DATA_PORT); | 273 | new_status = inb_p(IO_DATA_PORT); |
| 272 | 274 | ||
| 273 | /* Lock the SuperIO chip */ | 275 | /* Lock the SuperIO chip */ |
| 274 | outb_p(LOCK_DATA,IO_INDEX_PORT); | 276 | outb_p(LOCK_DATA, IO_INDEX_PORT); |
| 275 | 277 | ||
| 276 | spin_unlock_irqrestore(&spinlock, flags); | 278 | spin_unlock_irqrestore(&spinlock, flags); |
| 277 | 279 | ||
| @@ -290,7 +292,7 @@ static int wdt_get_status(int *status) | |||
| 290 | static int wdt_open(struct inode *inode, struct file *file) | 292 | static int wdt_open(struct inode *inode, struct file *file) |
| 291 | { | 293 | { |
| 292 | /* If the watchdog is alive we don't need to start it again */ | 294 | /* If the watchdog is alive we don't need to start it again */ |
| 293 | if( test_and_set_bit(0, &timer_alive) ) | 295 | if (test_and_set_bit(0, &timer_alive)) |
| 294 | return -EBUSY; | 296 | return -EBUSY; |
| 295 | 297 | ||
| 296 | if (nowayout) | 298 | if (nowayout) |
| @@ -306,13 +308,13 @@ static int wdt_release(struct inode *inode, struct file *file) | |||
| 306 | * Shut off the timer. | 308 | * Shut off the timer. |
| 307 | * Lock it in if it's a module and we set nowayout | 309 | * Lock it in if it's a module and we set nowayout |
| 308 | */ | 310 | */ |
| 309 | if (expect_close == 42) | 311 | if (expect_close == 42) { |
| 310 | { | ||
| 311 | wdt_stop(); | 312 | wdt_stop(); |
| 312 | clear_bit(0, &timer_alive); | 313 | clear_bit(0, &timer_alive); |
| 313 | } else { | 314 | } else { |
| 314 | wdt_keepalive(); | 315 | wdt_keepalive(); |
| 315 | printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n"); | 316 | printk(KERN_CRIT PFX |
| 317 | "unexpected close, not stopping watchdog!\n"); | ||
| 316 | } | 318 | } |
| 317 | expect_close = 0; | 319 | expect_close = 0; |
| 318 | return 0; | 320 | return 0; |
| @@ -333,24 +335,22 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, | |||
| 333 | size_t count, loff_t *ppos) | 335 | size_t count, loff_t *ppos) |
| 334 | { | 336 | { |
| 335 | /* See if we got the magic character 'V' and reload the timer */ | 337 | /* See if we got the magic character 'V' and reload the timer */ |
| 336 | if(count) | 338 | if (count) { |
| 337 | { | 339 | if (!nowayout) { |
| 338 | if (!nowayout) | ||
| 339 | { | ||
| 340 | size_t ofs; | 340 | size_t ofs; |
| 341 | 341 | ||
| 342 | /* note: just in case someone wrote the magic character long ago */ | 342 | /* note: just in case someone wrote the |
| 343 | magic character long ago */ | ||
| 343 | expect_close = 0; | 344 | expect_close = 0; |
| 344 | 345 | ||
| 345 | /* scan to see whether or not we got the magic character */ | 346 | /* scan to see whether or not we got the |
| 346 | for(ofs = 0; ofs != count; ofs++) | 347 | magic character */ |
| 347 | { | 348 | for (ofs = 0; ofs != count; ofs++) { |
| 348 | char c; | 349 | char c; |
| 349 | if (get_user(c, buf + ofs)) | 350 | if (get_user(c, buf + ofs)) |
| 350 | return -EFAULT; | 351 | return -EFAULT; |
| 351 | if (c == 'V') { | 352 | if (c == 'V') |
| 352 | expect_close = 42; | 353 | expect_close = 42; |
| 353 | } | ||
| 354 | } | 354 | } |
| 355 | } | 355 | } |
| 356 | 356 | ||
| @@ -377,8 +377,7 @@ static struct watchdog_info ident = { | |||
| 377 | .identity = WATCHDOG_NAME, | 377 | .identity = WATCHDOG_NAME, |
| 378 | }; | 378 | }; |
| 379 | 379 | ||
| 380 | static int wdt_ioctl(struct inode *inode, struct file *file, | 380 | static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 381 | unsigned int cmd, unsigned long arg) | ||
| 382 | { | 381 | { |
| 383 | int status; | 382 | int status; |
| 384 | int new_options, retval = -EINVAL; | 383 | int new_options, retval = -EINVAL; |
| @@ -390,13 +389,10 @@ static int wdt_ioctl(struct inode *inode, struct file *file, | |||
| 390 | 389 | ||
| 391 | uarg.i = (int __user *)arg; | 390 | uarg.i = (int __user *)arg; |
| 392 | 391 | ||
| 393 | switch(cmd) | 392 | switch (cmd) { |
| 394 | { | ||
| 395 | default: | ||
| 396 | return -ENOTTY; | ||
| 397 | |||
| 398 | case WDIOC_GETSUPPORT: | 393 | case WDIOC_GETSUPPORT: |
| 399 | return copy_to_user(uarg.ident, &ident, sizeof(ident)) ? -EFAULT : 0; | 394 | return copy_to_user(uarg.ident, &ident, |
| 395 | sizeof(ident)) ? -EFAULT : 0; | ||
| 400 | 396 | ||
| 401 | case WDIOC_GETSTATUS: | 397 | case WDIOC_GETSTATUS: |
| 402 | wdt_get_status(&status); | 398 | wdt_get_status(&status); |
| @@ -405,12 +401,8 @@ static int wdt_ioctl(struct inode *inode, struct file *file, | |||
| 405 | case WDIOC_GETBOOTSTATUS: | 401 | case WDIOC_GETBOOTSTATUS: |
| 406 | return put_user(0, uarg.i); | 402 | return put_user(0, uarg.i); |
| 407 | 403 | ||
| 408 | case WDIOC_KEEPALIVE: | ||
| 409 | wdt_keepalive(); | ||
| 410 | return 0; | ||
| 411 | |||
| 412 | case WDIOC_SETOPTIONS: | 404 | case WDIOC_SETOPTIONS: |
| 413 | if (get_user (new_options, uarg.i)) | 405 | if (get_user(new_options, uarg.i)) |
| 414 | return -EFAULT; | 406 | return -EFAULT; |
| 415 | 407 | ||
| 416 | if (new_options & WDIOS_DISABLECARD) { | 408 | if (new_options & WDIOS_DISABLECARD) { |
| @@ -425,6 +417,10 @@ static int wdt_ioctl(struct inode *inode, struct file *file, | |||
| 425 | 417 | ||
| 426 | return retval; | 418 | return retval; |
| 427 | 419 | ||
| 420 | case WDIOC_KEEPALIVE: | ||
| 421 | wdt_keepalive(); | ||
| 422 | return 0; | ||
| 423 | |||
| 428 | case WDIOC_SETTIMEOUT: | 424 | case WDIOC_SETTIMEOUT: |
| 429 | if (get_user(new_timeout, uarg.i)) | 425 | if (get_user(new_timeout, uarg.i)) |
| 430 | return -EFAULT; | 426 | return -EFAULT; |
| @@ -438,29 +434,30 @@ static int wdt_ioctl(struct inode *inode, struct file *file, | |||
| 438 | case WDIOC_GETTIMEOUT: | 434 | case WDIOC_GETTIMEOUT: |
| 439 | return put_user(timeout, uarg.i); | 435 | return put_user(timeout, uarg.i); |
| 440 | 436 | ||
| 437 | default: | ||
| 438 | return -ENOTTY; | ||
| 439 | |||
| 441 | } | 440 | } |
| 442 | } | 441 | } |
| 443 | 442 | ||
| 444 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | 443 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 445 | void *unused) | 444 | void *unused) |
| 446 | { | 445 | { |
| 447 | if (code==SYS_DOWN || code==SYS_HALT) | 446 | if (code == SYS_DOWN || code == SYS_HALT) |
| 448 | wdt_stop(); | 447 | wdt_stop(); |
| 449 | return NOTIFY_DONE; | 448 | return NOTIFY_DONE; |
| 450 | } | 449 | } |
| 451 | 450 | ||
| 452 | static const struct file_operations wdt_fops= | 451 | static const struct file_operations wdt_fops = { |
| 453 | { | ||
| 454 | .owner = THIS_MODULE, | 452 | .owner = THIS_MODULE, |
| 455 | .llseek = no_llseek, | 453 | .llseek = no_llseek, |
| 456 | .write = wdt_write, | 454 | .write = wdt_write, |
| 457 | .ioctl = wdt_ioctl, | 455 | .unlocked_ioctl = wdt_ioctl, |
| 458 | .open = wdt_open, | 456 | .open = wdt_open, |
| 459 | .release = wdt_release, | 457 | .release = wdt_release, |
| 460 | }; | 458 | }; |
| 461 | 459 | ||
| 462 | static struct miscdevice wdt_miscdev= | 460 | static struct miscdevice wdt_miscdev = { |
| 463 | { | ||
| 464 | .minor = WATCHDOG_MINOR, | 461 | .minor = WATCHDOG_MINOR, |
| 465 | .name = "watchdog", | 462 | .name = "watchdog", |
| 466 | .fops = &wdt_fops, | 463 | .fops = &wdt_fops, |
| @@ -474,20 +471,20 @@ static int __init w83977f_wdt_init(void) | |||
| 474 | { | 471 | { |
| 475 | int rc; | 472 | int rc; |
| 476 | 473 | ||
| 477 | printk(KERN_INFO PFX DRIVER_VERSION); | 474 | printk(KERN_INFO PFX DRIVER_VERSION); |
| 478 | 475 | ||
| 479 | /* | 476 | /* |
| 480 | * Check that the timeout value is within it's range ; | 477 | * Check that the timeout value is within it's range; |
| 481 | * if not reset to the default | 478 | * if not reset to the default |
| 482 | */ | 479 | */ |
| 483 | if (wdt_set_timeout(timeout)) { | 480 | if (wdt_set_timeout(timeout)) { |
| 484 | wdt_set_timeout(DEFAULT_TIMEOUT); | 481 | wdt_set_timeout(DEFAULT_TIMEOUT); |
| 485 | printk(KERN_INFO PFX "timeout value must be 15<=timeout<=7635, using %d\n", | 482 | printk(KERN_INFO PFX |
| 486 | DEFAULT_TIMEOUT); | 483 | "timeout value must be 15 <= timeout <= 7635, using %d\n", |
| 484 | DEFAULT_TIMEOUT); | ||
| 487 | } | 485 | } |
| 488 | 486 | ||
| 489 | if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) | 487 | if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) { |
| 490 | { | ||
| 491 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 488 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 492 | IO_INDEX_PORT); | 489 | IO_INDEX_PORT); |
| 493 | rc = -EIO; | 490 | rc = -EIO; |
| @@ -495,30 +492,30 @@ static int __init w83977f_wdt_init(void) | |||
| 495 | } | 492 | } |
| 496 | 493 | ||
| 497 | rc = register_reboot_notifier(&wdt_notifier); | 494 | rc = register_reboot_notifier(&wdt_notifier); |
| 498 | if (rc) | 495 | if (rc) { |
| 499 | { | 496 | printk(KERN_ERR PFX |
| 500 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 497 | "cannot register reboot notifier (err=%d)\n", rc); |
| 501 | rc); | ||
| 502 | goto err_out_region; | 498 | goto err_out_region; |
| 503 | } | 499 | } |
| 504 | 500 | ||
| 505 | rc = misc_register(&wdt_miscdev); | 501 | rc = misc_register(&wdt_miscdev); |
| 506 | if (rc) | 502 | if (rc) { |
| 507 | { | 503 | printk(KERN_ERR PFX |
| 508 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 504 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 509 | wdt_miscdev.minor, rc); | 505 | wdt_miscdev.minor, rc); |
| 510 | goto err_out_reboot; | 506 | goto err_out_reboot; |
| 511 | } | 507 | } |
| 512 | 508 | ||
| 513 | printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d testmode=%d)\n", | 509 | printk(KERN_INFO PFX |
| 514 | timeout, nowayout, testmode); | 510 | "initialized. timeout=%d sec (nowayout=%d testmode=%d)\n", |
| 511 | timeout, nowayout, testmode); | ||
| 515 | 512 | ||
| 516 | return 0; | 513 | return 0; |
| 517 | 514 | ||
| 518 | err_out_reboot: | 515 | err_out_reboot: |
| 519 | unregister_reboot_notifier(&wdt_notifier); | 516 | unregister_reboot_notifier(&wdt_notifier); |
| 520 | err_out_region: | 517 | err_out_region: |
| 521 | release_region(IO_INDEX_PORT,2); | 518 | release_region(IO_INDEX_PORT, 2); |
| 522 | err_out: | 519 | err_out: |
| 523 | return rc; | 520 | return rc; |
| 524 | } | 521 | } |
| @@ -528,7 +525,7 @@ static void __exit w83977f_wdt_exit(void) | |||
| 528 | wdt_stop(); | 525 | wdt_stop(); |
| 529 | misc_deregister(&wdt_miscdev); | 526 | misc_deregister(&wdt_miscdev); |
| 530 | unregister_reboot_notifier(&wdt_notifier); | 527 | unregister_reboot_notifier(&wdt_notifier); |
| 531 | release_region(IO_INDEX_PORT,2); | 528 | release_region(IO_INDEX_PORT, 2); |
| 532 | } | 529 | } |
| 533 | 530 | ||
| 534 | module_init(w83977f_wdt_init); | 531 | module_init(w83977f_wdt_init); |
diff --git a/drivers/watchdog/wafer5823wdt.c b/drivers/watchdog/wafer5823wdt.c index 9e368091f799..68377ae171ff 100644 --- a/drivers/watchdog/wafer5823wdt.c +++ b/drivers/watchdog/wafer5823wdt.c | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * ICP Wafer 5823 Single Board Computer WDT driver | 2 | * ICP Wafer 5823 Single Board Computer WDT driver |
| 3 | * http://www.icpamerica.com/wafer_5823.php | 3 | * http://www.icpamerica.com/wafer_5823.php |
| 4 | * May also work on other similar models | 4 | * May also work on other similar models |
| 5 | * | 5 | * |
| 6 | * (c) Copyright 2002 Justin Cormack <justin@street-vision.com> | 6 | * (c) Copyright 2002 Justin Cormack <justin@street-vision.com> |
| 7 | * | 7 | * |
| 8 | * Release 0.02 | 8 | * Release 0.02 |
| 9 | * | 9 | * |
| 10 | * Based on advantechwdt.c which is based on wdt.c. | 10 | * Based on advantechwdt.c which is based on wdt.c. |
| 11 | * Original copyright messages: | 11 | * Original copyright messages: |
| @@ -36,8 +36,8 @@ | |||
| 36 | #include <linux/reboot.h> | 36 | #include <linux/reboot.h> |
| 37 | #include <linux/init.h> | 37 | #include <linux/init.h> |
| 38 | #include <linux/spinlock.h> | 38 | #include <linux/spinlock.h> |
| 39 | #include <asm/io.h> | 39 | #include <linux/io.h> |
| 40 | #include <asm/uaccess.h> | 40 | #include <linux/uaccess.h> |
| 41 | 41 | ||
| 42 | #define WATCHDOG_NAME "Wafer 5823 WDT" | 42 | #define WATCHDOG_NAME "Wafer 5823 WDT" |
| 43 | #define PFX WATCHDOG_NAME ": " | 43 | #define PFX WATCHDOG_NAME ": " |
| @@ -50,10 +50,10 @@ static DEFINE_SPINLOCK(wafwdt_lock); | |||
| 50 | /* | 50 | /* |
| 51 | * You must set these - there is no sane way to probe for this board. | 51 | * You must set these - there is no sane way to probe for this board. |
| 52 | * | 52 | * |
| 53 | * To enable, write the timeout value in seconds (1 to 255) to I/O | 53 | * To enable, write the timeout value in seconds (1 to 255) to I/O |
| 54 | * port WDT_START, then read the port to start the watchdog. To pat | 54 | * port WDT_START, then read the port to start the watchdog. To pat |
| 55 | * the dog, read port WDT_STOP to stop the timer, then read WDT_START | 55 | * the dog, read port WDT_STOP to stop the timer, then read WDT_START |
| 56 | * to restart it again. | 56 | * to restart it again. |
| 57 | */ | 57 | */ |
| 58 | 58 | ||
| 59 | static int wdt_stop = 0x843; | 59 | static int wdt_stop = 0x843; |
| @@ -61,11 +61,15 @@ static int wdt_start = 0x443; | |||
| 61 | 61 | ||
| 62 | static int timeout = WD_TIMO; /* in seconds */ | 62 | static int timeout = WD_TIMO; /* in seconds */ |
| 63 | module_param(timeout, int, 0); | 63 | module_param(timeout, int, 0); |
| 64 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255, default=" __MODULE_STRING(WD_TIMO) "."); | 64 | MODULE_PARM_DESC(timeout, |
| 65 | "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" | ||
| 66 | __MODULE_STRING(WD_TIMO) "."); | ||
| 65 | 67 | ||
| 66 | static int nowayout = WATCHDOG_NOWAYOUT; | 68 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 67 | module_param(nowayout, int, 0); | 69 | module_param(nowayout, int, 0); |
| 68 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 70 | MODULE_PARM_DESC(nowayout, |
| 71 | "Watchdog cannot be stopped once started (default=" | ||
| 72 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 69 | 73 | ||
| 70 | static void wafwdt_ping(void) | 74 | static void wafwdt_ping(void) |
| 71 | { | 75 | { |
| @@ -83,14 +87,14 @@ static void wafwdt_start(void) | |||
| 83 | inb_p(wdt_start); | 87 | inb_p(wdt_start); |
| 84 | } | 88 | } |
| 85 | 89 | ||
| 86 | static void | 90 | static void wafwdt_stop(void) |
| 87 | wafwdt_stop(void) | ||
| 88 | { | 91 | { |
| 89 | /* stop watchdog */ | 92 | /* stop watchdog */ |
| 90 | inb_p(wdt_stop); | 93 | inb_p(wdt_stop); |
| 91 | } | 94 | } |
| 92 | 95 | ||
| 93 | static ssize_t wafwdt_write(struct file *file, const char __user *buf, size_t count, loff_t * ppos) | 96 | static ssize_t wafwdt_write(struct file *file, const char __user *buf, |
| 97 | size_t count, loff_t *ppos) | ||
| 94 | { | 98 | { |
| 95 | /* See if we got the magic character 'V' and reload the timer */ | 99 | /* See if we got the magic character 'V' and reload the timer */ |
| 96 | if (count) { | 100 | if (count) { |
| @@ -100,7 +104,8 @@ static ssize_t wafwdt_write(struct file *file, const char __user *buf, size_t co | |||
| 100 | /* In case it was set long ago */ | 104 | /* In case it was set long ago */ |
| 101 | expect_close = 0; | 105 | expect_close = 0; |
| 102 | 106 | ||
| 103 | /* scan to see whether or not we got the magic character */ | 107 | /* scan to see whether or not we got the magic |
| 108 | character */ | ||
| 104 | for (i = 0; i != count; i++) { | 109 | for (i = 0; i != count; i++) { |
| 105 | char c; | 110 | char c; |
| 106 | if (get_user(c, buf + i)) | 111 | if (get_user(c, buf + i)) |
| @@ -109,27 +114,29 @@ static ssize_t wafwdt_write(struct file *file, const char __user *buf, size_t co | |||
| 109 | expect_close = 42; | 114 | expect_close = 42; |
| 110 | } | 115 | } |
| 111 | } | 116 | } |
| 112 | /* Well, anyhow someone wrote to us, we should return that favour */ | 117 | /* Well, anyhow someone wrote to us, we should |
| 118 | return that favour */ | ||
| 113 | wafwdt_ping(); | 119 | wafwdt_ping(); |
| 114 | } | 120 | } |
| 115 | return count; | 121 | return count; |
| 116 | } | 122 | } |
| 117 | 123 | ||
| 118 | static int wafwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 124 | static long wafwdt_ioctl(struct file *file, unsigned int cmd, |
| 119 | unsigned long arg) | 125 | unsigned long arg) |
| 120 | { | 126 | { |
| 121 | int new_timeout; | 127 | int new_timeout; |
| 122 | void __user *argp = (void __user *)arg; | 128 | void __user *argp = (void __user *)arg; |
| 123 | int __user *p = argp; | 129 | int __user *p = argp; |
| 124 | static struct watchdog_info ident = { | 130 | static const struct watchdog_info ident = { |
| 125 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | 131 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
| 132 | WDIOF_MAGICCLOSE, | ||
| 126 | .firmware_version = 1, | 133 | .firmware_version = 1, |
| 127 | .identity = "Wafer 5823 WDT", | 134 | .identity = "Wafer 5823 WDT", |
| 128 | }; | 135 | }; |
| 129 | 136 | ||
| 130 | switch (cmd) { | 137 | switch (cmd) { |
| 131 | case WDIOC_GETSUPPORT: | 138 | case WDIOC_GETSUPPORT: |
| 132 | if (copy_to_user(argp, &ident, sizeof (ident))) | 139 | if (copy_to_user(argp, &ident, sizeof(ident))) |
| 133 | return -EFAULT; | 140 | return -EFAULT; |
| 134 | break; | 141 | break; |
| 135 | 142 | ||
| @@ -137,22 +144,6 @@ static int wafwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd | |||
| 137 | case WDIOC_GETBOOTSTATUS: | 144 | case WDIOC_GETBOOTSTATUS: |
| 138 | return put_user(0, p); | 145 | return put_user(0, p); |
| 139 | 146 | ||
| 140 | case WDIOC_KEEPALIVE: | ||
| 141 | wafwdt_ping(); | ||
| 142 | break; | ||
| 143 | |||
| 144 | case WDIOC_SETTIMEOUT: | ||
| 145 | if (get_user(new_timeout, p)) | ||
| 146 | return -EFAULT; | ||
| 147 | if ((new_timeout < 1) || (new_timeout > 255)) | ||
| 148 | return -EINVAL; | ||
| 149 | timeout = new_timeout; | ||
| 150 | wafwdt_stop(); | ||
| 151 | wafwdt_start(); | ||
| 152 | /* Fall */ | ||
| 153 | case WDIOC_GETTIMEOUT: | ||
| 154 | return put_user(timeout, p); | ||
| 155 | |||
| 156 | case WDIOC_SETOPTIONS: | 147 | case WDIOC_SETOPTIONS: |
| 157 | { | 148 | { |
| 158 | int options, retval = -EINVAL; | 149 | int options, retval = -EINVAL; |
| @@ -173,6 +164,22 @@ static int wafwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd | |||
| 173 | return retval; | 164 | return retval; |
| 174 | } | 165 | } |
| 175 | 166 | ||
| 167 | case WDIOC_KEEPALIVE: | ||
| 168 | wafwdt_ping(); | ||
| 169 | break; | ||
| 170 | |||
| 171 | case WDIOC_SETTIMEOUT: | ||
| 172 | if (get_user(new_timeout, p)) | ||
| 173 | return -EFAULT; | ||
| 174 | if ((new_timeout < 1) || (new_timeout > 255)) | ||
| 175 | return -EINVAL; | ||
| 176 | timeout = new_timeout; | ||
| 177 | wafwdt_stop(); | ||
| 178 | wafwdt_start(); | ||
| 179 | /* Fall */ | ||
| 180 | case WDIOC_GETTIMEOUT: | ||
| 181 | return put_user(timeout, p); | ||
| 182 | |||
| 176 | default: | 183 | default: |
| 177 | return -ENOTTY; | 184 | return -ENOTTY; |
| 178 | } | 185 | } |
| @@ -191,13 +198,13 @@ static int wafwdt_open(struct inode *inode, struct file *file) | |||
| 191 | return nonseekable_open(inode, file); | 198 | return nonseekable_open(inode, file); |
| 192 | } | 199 | } |
| 193 | 200 | ||
| 194 | static int | 201 | static int wafwdt_close(struct inode *inode, struct file *file) |
| 195 | wafwdt_close(struct inode *inode, struct file *file) | ||
| 196 | { | 202 | { |
| 197 | if (expect_close == 42) { | 203 | if (expect_close == 42) |
| 198 | wafwdt_stop(); | 204 | wafwdt_stop(); |
| 199 | } else { | 205 | else { |
| 200 | printk(KERN_CRIT PFX "WDT device closed unexpectedly. WDT will not stop!\n"); | 206 | printk(KERN_CRIT PFX |
| 207 | "WDT device closed unexpectedly. WDT will not stop!\n"); | ||
| 201 | wafwdt_ping(); | 208 | wafwdt_ping(); |
| 202 | } | 209 | } |
| 203 | clear_bit(0, &wafwdt_is_open); | 210 | clear_bit(0, &wafwdt_is_open); |
| @@ -209,12 +216,11 @@ wafwdt_close(struct inode *inode, struct file *file) | |||
| 209 | * Notifier for system down | 216 | * Notifier for system down |
| 210 | */ | 217 | */ |
| 211 | 218 | ||
| 212 | static int wafwdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) | 219 | static int wafwdt_notify_sys(struct notifier_block *this, unsigned long code, |
| 220 | void *unused) | ||
| 213 | { | 221 | { |
| 214 | if (code == SYS_DOWN || code == SYS_HALT) { | 222 | if (code == SYS_DOWN || code == SYS_HALT) |
| 215 | /* Turn the WDT off */ | ||
| 216 | wafwdt_stop(); | 223 | wafwdt_stop(); |
| 217 | } | ||
| 218 | return NOTIFY_DONE; | 224 | return NOTIFY_DONE; |
| 219 | } | 225 | } |
| 220 | 226 | ||
| @@ -226,7 +232,7 @@ static const struct file_operations wafwdt_fops = { | |||
| 226 | .owner = THIS_MODULE, | 232 | .owner = THIS_MODULE, |
| 227 | .llseek = no_llseek, | 233 | .llseek = no_llseek, |
| 228 | .write = wafwdt_write, | 234 | .write = wafwdt_write, |
| 229 | .ioctl = wafwdt_ioctl, | 235 | .unlocked_ioctl = wafwdt_ioctl, |
| 230 | .open = wafwdt_open, | 236 | .open = wafwdt_open, |
| 231 | .release = wafwdt_close, | 237 | .release = wafwdt_close, |
| 232 | }; | 238 | }; |
| @@ -250,25 +256,28 @@ static int __init wafwdt_init(void) | |||
| 250 | { | 256 | { |
| 251 | int ret; | 257 | int ret; |
| 252 | 258 | ||
| 253 | printk(KERN_INFO "WDT driver for Wafer 5823 single board computer initialising.\n"); | 259 | printk(KERN_INFO |
| 260 | "WDT driver for Wafer 5823 single board computer initialising.\n"); | ||
| 254 | 261 | ||
| 255 | if (timeout < 1 || timeout > 255) { | 262 | if (timeout < 1 || timeout > 255) { |
| 256 | timeout = WD_TIMO; | 263 | timeout = WD_TIMO; |
| 257 | printk (KERN_INFO PFX "timeout value must be 1<=x<=255, using %d\n", | 264 | printk(KERN_INFO PFX |
| 258 | timeout); | 265 | "timeout value must be 1 <= x <= 255, using %d\n", |
| 266 | timeout); | ||
| 259 | } | 267 | } |
| 260 | 268 | ||
| 261 | if (wdt_stop != wdt_start) { | 269 | if (wdt_stop != wdt_start) { |
| 262 | if(!request_region(wdt_stop, 1, "Wafer 5823 WDT")) { | 270 | if (!request_region(wdt_stop, 1, "Wafer 5823 WDT")) { |
| 263 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 271 | printk(KERN_ERR PFX |
| 264 | wdt_stop); | 272 | "I/O address 0x%04x already in use\n", |
| 273 | wdt_stop); | ||
| 265 | ret = -EIO; | 274 | ret = -EIO; |
| 266 | goto error; | 275 | goto error; |
| 267 | } | 276 | } |
| 268 | } | 277 | } |
| 269 | 278 | ||
| 270 | if(!request_region(wdt_start, 1, "Wafer 5823 WDT")) { | 279 | if (!request_region(wdt_start, 1, "Wafer 5823 WDT")) { |
| 271 | printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", | 280 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", |
| 272 | wdt_start); | 281 | wdt_start); |
| 273 | ret = -EIO; | 282 | ret = -EIO; |
| 274 | goto error2; | 283 | goto error2; |
| @@ -276,19 +285,20 @@ static int __init wafwdt_init(void) | |||
| 276 | 285 | ||
| 277 | ret = register_reboot_notifier(&wafwdt_notifier); | 286 | ret = register_reboot_notifier(&wafwdt_notifier); |
| 278 | if (ret != 0) { | 287 | if (ret != 0) { |
| 279 | printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 288 | printk(KERN_ERR PFX |
| 280 | ret); | 289 | "cannot register reboot notifier (err=%d)\n", ret); |
| 281 | goto error3; | 290 | goto error3; |
| 282 | } | 291 | } |
| 283 | 292 | ||
| 284 | ret = misc_register(&wafwdt_miscdev); | 293 | ret = misc_register(&wafwdt_miscdev); |
| 285 | if (ret != 0) { | 294 | if (ret != 0) { |
| 286 | printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 295 | printk(KERN_ERR PFX |
| 287 | WATCHDOG_MINOR, ret); | 296 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 297 | WATCHDOG_MINOR, ret); | ||
| 288 | goto error4; | 298 | goto error4; |
| 289 | } | 299 | } |
| 290 | 300 | ||
| 291 | printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", | 301 | printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", |
| 292 | timeout, nowayout); | 302 | timeout, nowayout); |
| 293 | 303 | ||
| 294 | return ret; | 304 | return ret; |
| @@ -307,7 +317,7 @@ static void __exit wafwdt_exit(void) | |||
| 307 | { | 317 | { |
| 308 | misc_deregister(&wafwdt_miscdev); | 318 | misc_deregister(&wafwdt_miscdev); |
| 309 | unregister_reboot_notifier(&wafwdt_notifier); | 319 | unregister_reboot_notifier(&wafwdt_notifier); |
| 310 | if(wdt_stop != wdt_start) | 320 | if (wdt_stop != wdt_start) |
| 311 | release_region(wdt_stop, 1); | 321 | release_region(wdt_stop, 1); |
| 312 | release_region(wdt_start, 1); | 322 | release_region(wdt_start, 1); |
| 313 | } | 323 | } |
diff --git a/drivers/watchdog/wd501p.h b/drivers/watchdog/wd501p.h index a4504f40394d..db34853c28ae 100644 --- a/drivers/watchdog/wd501p.h +++ b/drivers/watchdog/wd501p.h | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | * http://www.cymru.net | 12 | * http://www.cymru.net |
| 13 | * | 13 | * |
| 14 | * This driver is provided under the GNU General Public License, incorporated | 14 | * This driver is provided under the GNU General Public License, incorporated |
| 15 | * herein by reference. The driver is provided without warranty or | 15 | * herein by reference. The driver is provided without warranty or |
| 16 | * support. | 16 | * support. |
| 17 | * | 17 | * |
| 18 | * Release 0.04. | 18 | * Release 0.04. |
diff --git a/drivers/watchdog/wdrtas.c b/drivers/watchdog/wdrtas.c index 1d64e277567d..5d3b1a8e28b0 100644 --- a/drivers/watchdog/wdrtas.c +++ b/drivers/watchdog/wdrtas.c | |||
| @@ -35,9 +35,9 @@ | |||
| 35 | #include <linux/reboot.h> | 35 | #include <linux/reboot.h> |
| 36 | #include <linux/types.h> | 36 | #include <linux/types.h> |
| 37 | #include <linux/watchdog.h> | 37 | #include <linux/watchdog.h> |
| 38 | #include <linux/uaccess.h> | ||
| 38 | 39 | ||
| 39 | #include <asm/rtas.h> | 40 | #include <asm/rtas.h> |
| 40 | #include <asm/uaccess.h> | ||
| 41 | 41 | ||
| 42 | #define WDRTAS_MAGIC_CHAR 42 | 42 | #define WDRTAS_MAGIC_CHAR 42 |
| 43 | #define WDRTAS_SUPPORTED_MASK (WDIOF_SETTIMEOUT | \ | 43 | #define WDRTAS_SUPPORTED_MASK (WDIOF_SETTIMEOUT | \ |
| @@ -56,7 +56,7 @@ static int wdrtas_nowayout = 0; | |||
| 56 | #endif | 56 | #endif |
| 57 | 57 | ||
| 58 | static atomic_t wdrtas_miscdev_open = ATOMIC_INIT(0); | 58 | static atomic_t wdrtas_miscdev_open = ATOMIC_INIT(0); |
| 59 | static char wdrtas_expect_close = 0; | 59 | static char wdrtas_expect_close; |
| 60 | 60 | ||
| 61 | static int wdrtas_interval; | 61 | static int wdrtas_interval; |
| 62 | 62 | ||
| @@ -86,8 +86,8 @@ static char wdrtas_logbuffer[WDRTAS_LOGBUFFER_LEN]; | |||
| 86 | * RTAS function set-indicator (surveillance). The unit of interval is | 86 | * RTAS function set-indicator (surveillance). The unit of interval is |
| 87 | * seconds. | 87 | * seconds. |
| 88 | */ | 88 | */ |
| 89 | static int | 89 | |
| 90 | wdrtas_set_interval(int interval) | 90 | static int wdrtas_set_interval(int interval) |
| 91 | { | 91 | { |
| 92 | long result; | 92 | long result; |
| 93 | static int print_msg = 10; | 93 | static int print_msg = 10; |
| @@ -97,7 +97,7 @@ wdrtas_set_interval(int interval) | |||
| 97 | 97 | ||
| 98 | result = rtas_call(wdrtas_token_set_indicator, 3, 1, NULL, | 98 | result = rtas_call(wdrtas_token_set_indicator, 3, 1, NULL, |
| 99 | WDRTAS_SURVEILLANCE_IND, 0, interval); | 99 | WDRTAS_SURVEILLANCE_IND, 0, interval); |
| 100 | if ( (result < 0) && (print_msg) ) { | 100 | if (result < 0 && print_msg) { |
| 101 | printk(KERN_ERR "wdrtas: setting the watchdog to %i " | 101 | printk(KERN_ERR "wdrtas: setting the watchdog to %i " |
| 102 | "timeout failed: %li\n", interval, result); | 102 | "timeout failed: %li\n", interval, result); |
| 103 | print_msg--; | 103 | print_msg--; |
| @@ -116,16 +116,14 @@ wdrtas_set_interval(int interval) | |||
| 116 | * as reported by the RTAS function ibm,get-system-parameter. The unit | 116 | * as reported by the RTAS function ibm,get-system-parameter. The unit |
| 117 | * of the return value is seconds. | 117 | * of the return value is seconds. |
| 118 | */ | 118 | */ |
| 119 | static int | 119 | static int wdrtas_get_interval(int fallback_value) |
| 120 | wdrtas_get_interval(int fallback_value) | ||
| 121 | { | 120 | { |
| 122 | long result; | 121 | long result; |
| 123 | char value[4]; | 122 | char value[4]; |
| 124 | 123 | ||
| 125 | result = rtas_call(wdrtas_token_get_sp, 3, 1, NULL, | 124 | result = rtas_call(wdrtas_token_get_sp, 3, 1, NULL, |
| 126 | WDRTAS_SP_SPI, (void *)__pa(&value), 4); | 125 | WDRTAS_SP_SPI, (void *)__pa(&value), 4); |
| 127 | if ( (value[0] != 0) || (value[1] != 2) || (value[3] != 0) || | 126 | if (value[0] != 0 || value[1] != 2 || value[3] != 0 || result < 0) { |
| 128 | (result < 0) ) { | ||
| 129 | printk(KERN_WARNING "wdrtas: could not get sp_spi watchdog " | 127 | printk(KERN_WARNING "wdrtas: could not get sp_spi watchdog " |
| 130 | "timeout (%li). Continuing\n", result); | 128 | "timeout (%li). Continuing\n", result); |
| 131 | return fallback_value; | 129 | return fallback_value; |
| @@ -141,8 +139,7 @@ wdrtas_get_interval(int fallback_value) | |||
| 141 | * wdrtas_timer_start starts the watchdog by calling the RTAS function | 139 | * wdrtas_timer_start starts the watchdog by calling the RTAS function |
| 142 | * set-interval (surveillance) | 140 | * set-interval (surveillance) |
| 143 | */ | 141 | */ |
| 144 | static void | 142 | static void wdrtas_timer_start(void) |
| 145 | wdrtas_timer_start(void) | ||
| 146 | { | 143 | { |
| 147 | wdrtas_set_interval(wdrtas_interval); | 144 | wdrtas_set_interval(wdrtas_interval); |
| 148 | } | 145 | } |
| @@ -153,8 +150,7 @@ wdrtas_timer_start(void) | |||
| 153 | * wdrtas_timer_stop stops the watchdog timer by calling the RTAS function | 150 | * wdrtas_timer_stop stops the watchdog timer by calling the RTAS function |
| 154 | * set-interval (surveillance) | 151 | * set-interval (surveillance) |
| 155 | */ | 152 | */ |
| 156 | static void | 153 | static void wdrtas_timer_stop(void) |
| 157 | wdrtas_timer_stop(void) | ||
| 158 | { | 154 | { |
| 159 | wdrtas_set_interval(0); | 155 | wdrtas_set_interval(0); |
| 160 | } | 156 | } |
| @@ -165,8 +161,7 @@ wdrtas_timer_stop(void) | |||
| 165 | * wdrtas_log_scanned_event prints a message to the log buffer dumping | 161 | * wdrtas_log_scanned_event prints a message to the log buffer dumping |
| 166 | * the results of the last event-scan call | 162 | * the results of the last event-scan call |
| 167 | */ | 163 | */ |
| 168 | static void | 164 | static void wdrtas_log_scanned_event(void) |
| 169 | wdrtas_log_scanned_event(void) | ||
| 170 | { | 165 | { |
| 171 | int i; | 166 | int i; |
| 172 | 167 | ||
| @@ -175,13 +170,13 @@ wdrtas_log_scanned_event(void) | |||
| 175 | "%02x %02x %02x %02x %02x %02x %02x %02x " | 170 | "%02x %02x %02x %02x %02x %02x %02x %02x " |
| 176 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", | 171 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", |
| 177 | (i / 16) + 1, (WDRTAS_LOGBUFFER_LEN / 16), | 172 | (i / 16) + 1, (WDRTAS_LOGBUFFER_LEN / 16), |
| 178 | wdrtas_logbuffer[i + 0], wdrtas_logbuffer[i + 1], | 173 | wdrtas_logbuffer[i + 0], wdrtas_logbuffer[i + 1], |
| 179 | wdrtas_logbuffer[i + 2], wdrtas_logbuffer[i + 3], | 174 | wdrtas_logbuffer[i + 2], wdrtas_logbuffer[i + 3], |
| 180 | wdrtas_logbuffer[i + 4], wdrtas_logbuffer[i + 5], | 175 | wdrtas_logbuffer[i + 4], wdrtas_logbuffer[i + 5], |
| 181 | wdrtas_logbuffer[i + 6], wdrtas_logbuffer[i + 7], | 176 | wdrtas_logbuffer[i + 6], wdrtas_logbuffer[i + 7], |
| 182 | wdrtas_logbuffer[i + 8], wdrtas_logbuffer[i + 9], | 177 | wdrtas_logbuffer[i + 8], wdrtas_logbuffer[i + 9], |
| 183 | wdrtas_logbuffer[i + 10], wdrtas_logbuffer[i + 11], | 178 | wdrtas_logbuffer[i + 10], wdrtas_logbuffer[i + 11], |
| 184 | wdrtas_logbuffer[i + 12], wdrtas_logbuffer[i + 13], | 179 | wdrtas_logbuffer[i + 12], wdrtas_logbuffer[i + 13], |
| 185 | wdrtas_logbuffer[i + 14], wdrtas_logbuffer[i + 15]); | 180 | wdrtas_logbuffer[i + 14], wdrtas_logbuffer[i + 15]); |
| 186 | } | 181 | } |
| 187 | 182 | ||
| @@ -192,8 +187,7 @@ wdrtas_log_scanned_event(void) | |||
| 192 | * RTAS function event-scan and repeats these calls as long as there are | 187 | * RTAS function event-scan and repeats these calls as long as there are |
| 193 | * events available. All events will be dumped. | 188 | * events available. All events will be dumped. |
| 194 | */ | 189 | */ |
| 195 | static void | 190 | static void wdrtas_timer_keepalive(void) |
| 196 | wdrtas_timer_keepalive(void) | ||
| 197 | { | 191 | { |
| 198 | long result; | 192 | long result; |
| 199 | 193 | ||
| @@ -218,8 +212,7 @@ wdrtas_timer_keepalive(void) | |||
| 218 | * wdrtas_get_temperature returns the current temperature in Fahrenheit. It | 212 | * wdrtas_get_temperature returns the current temperature in Fahrenheit. It |
| 219 | * uses the RTAS call get-sensor-state, token 3 to do so | 213 | * uses the RTAS call get-sensor-state, token 3 to do so |
| 220 | */ | 214 | */ |
| 221 | static int | 215 | static int wdrtas_get_temperature(void) |
| 222 | wdrtas_get_temperature(void) | ||
| 223 | { | 216 | { |
| 224 | long result; | 217 | long result; |
| 225 | int temperature = 0; | 218 | int temperature = 0; |
| @@ -243,8 +236,7 @@ wdrtas_get_temperature(void) | |||
| 243 | * returns a bitmask of defines WDIOF_... as defined in | 236 | * returns a bitmask of defines WDIOF_... as defined in |
| 244 | * include/linux/watchdog.h | 237 | * include/linux/watchdog.h |
| 245 | */ | 238 | */ |
| 246 | static int | 239 | static int wdrtas_get_status(void) |
| 247 | wdrtas_get_status(void) | ||
| 248 | { | 240 | { |
| 249 | return 0; /* TODO */ | 241 | return 0; /* TODO */ |
| 250 | } | 242 | } |
| @@ -255,8 +247,7 @@ wdrtas_get_status(void) | |||
| 255 | * returns a bitmask of defines WDIOF_... as defined in | 247 | * returns a bitmask of defines WDIOF_... as defined in |
| 256 | * include/linux/watchdog.h, indicating why the watchdog rebooted the system | 248 | * include/linux/watchdog.h, indicating why the watchdog rebooted the system |
| 257 | */ | 249 | */ |
| 258 | static int | 250 | static int wdrtas_get_boot_status(void) |
| 259 | wdrtas_get_boot_status(void) | ||
| 260 | { | 251 | { |
| 261 | return 0; /* TODO */ | 252 | return 0; /* TODO */ |
| 262 | } | 253 | } |
| @@ -276,8 +267,7 @@ wdrtas_get_boot_status(void) | |||
| 276 | * character 'V'. This character allows the watchdog device to be closed | 267 | * character 'V'. This character allows the watchdog device to be closed |
| 277 | * properly. | 268 | * properly. |
| 278 | */ | 269 | */ |
| 279 | static ssize_t | 270 | static ssize_t wdrtas_write(struct file *file, const char __user *buf, |
| 280 | wdrtas_write(struct file *file, const char __user *buf, | ||
| 281 | size_t len, loff_t *ppos) | 271 | size_t len, loff_t *ppos) |
| 282 | { | 272 | { |
| 283 | int i; | 273 | int i; |
| @@ -306,7 +296,6 @@ out: | |||
| 306 | 296 | ||
| 307 | /** | 297 | /** |
| 308 | * wdrtas_ioctl - ioctl function for the watchdog device | 298 | * wdrtas_ioctl - ioctl function for the watchdog device |
| 309 | * @inode: inode structure | ||
| 310 | * @file: file structure | 299 | * @file: file structure |
| 311 | * @cmd: command for ioctl | 300 | * @cmd: command for ioctl |
| 312 | * @arg: argument pointer | 301 | * @arg: argument pointer |
| @@ -315,16 +304,16 @@ out: | |||
| 315 | * | 304 | * |
| 316 | * wdrtas_ioctl implements the watchdog API ioctls | 305 | * wdrtas_ioctl implements the watchdog API ioctls |
| 317 | */ | 306 | */ |
| 318 | static int | 307 | |
| 319 | wdrtas_ioctl(struct inode *inode, struct file *file, | 308 | static long wdrtas_ioctl(struct file *file, unsigned int cmd, |
| 320 | unsigned int cmd, unsigned long arg) | 309 | unsigned long arg) |
| 321 | { | 310 | { |
| 322 | int __user *argp = (void __user *)arg; | 311 | int __user *argp = (void __user *)arg; |
| 323 | int i; | 312 | int i; |
| 324 | static struct watchdog_info wdinfo = { | 313 | static struct watchdog_info wdinfo = { |
| 325 | .options = WDRTAS_SUPPORTED_MASK, | 314 | .options = WDRTAS_SUPPORTED_MASK, |
| 326 | .firmware_version = 0, | 315 | .firmware_version = 0, |
| 327 | .identity = "wdrtas" | 316 | .identity = "wdrtas", |
| 328 | }; | 317 | }; |
| 329 | 318 | ||
| 330 | switch (cmd) { | 319 | switch (cmd) { |
| @@ -357,9 +346,9 @@ wdrtas_ioctl(struct inode *inode, struct file *file, | |||
| 357 | wdrtas_timer_keepalive(); | 346 | wdrtas_timer_keepalive(); |
| 358 | wdrtas_timer_start(); | 347 | wdrtas_timer_start(); |
| 359 | } | 348 | } |
| 349 | /* not implemented. Done by H8 | ||
| 360 | if (i & WDIOS_TEMPPANIC) { | 350 | if (i & WDIOS_TEMPPANIC) { |
| 361 | /* not implemented. Done by H8 */ | 351 | } */ |
| 362 | } | ||
| 363 | return 0; | 352 | return 0; |
| 364 | 353 | ||
| 365 | case WDIOC_KEEPALIVE: | 354 | case WDIOC_KEEPALIVE: |
| @@ -399,8 +388,7 @@ wdrtas_ioctl(struct inode *inode, struct file *file, | |||
| 399 | * | 388 | * |
| 400 | * function called when watchdog device is opened | 389 | * function called when watchdog device is opened |
| 401 | */ | 390 | */ |
| 402 | static int | 391 | static int wdrtas_open(struct inode *inode, struct file *file) |
| 403 | wdrtas_open(struct inode *inode, struct file *file) | ||
| 404 | { | 392 | { |
| 405 | /* only open once */ | 393 | /* only open once */ |
| 406 | if (atomic_inc_return(&wdrtas_miscdev_open) > 1) { | 394 | if (atomic_inc_return(&wdrtas_miscdev_open) > 1) { |
| @@ -423,8 +411,7 @@ wdrtas_open(struct inode *inode, struct file *file) | |||
| 423 | * | 411 | * |
| 424 | * close function. Always succeeds | 412 | * close function. Always succeeds |
| 425 | */ | 413 | */ |
| 426 | static int | 414 | static int wdrtas_close(struct inode *inode, struct file *file) |
| 427 | wdrtas_close(struct inode *inode, struct file *file) | ||
| 428 | { | 415 | { |
| 429 | /* only stop watchdog, if this was announced using 'V' before */ | 416 | /* only stop watchdog, if this was announced using 'V' before */ |
| 430 | if (wdrtas_expect_close == WDRTAS_MAGIC_CHAR) | 417 | if (wdrtas_expect_close == WDRTAS_MAGIC_CHAR) |
| @@ -453,8 +440,7 @@ wdrtas_close(struct inode *inode, struct file *file) | |||
| 453 | * wdrtas_temp_read gives the temperature to the users by copying this | 440 | * wdrtas_temp_read gives the temperature to the users by copying this |
| 454 | * value as one byte into the user space buffer. The unit is Fahrenheit... | 441 | * value as one byte into the user space buffer. The unit is Fahrenheit... |
| 455 | */ | 442 | */ |
| 456 | static ssize_t | 443 | static ssize_t wdrtas_temp_read(struct file *file, char __user *buf, |
| 457 | wdrtas_temp_read(struct file *file, char __user *buf, | ||
| 458 | size_t count, loff_t *ppos) | 444 | size_t count, loff_t *ppos) |
| 459 | { | 445 | { |
| 460 | int temperature = 0; | 446 | int temperature = 0; |
| @@ -478,8 +464,7 @@ wdrtas_temp_read(struct file *file, char __user *buf, | |||
| 478 | * | 464 | * |
| 479 | * function called when temperature device is opened | 465 | * function called when temperature device is opened |
| 480 | */ | 466 | */ |
| 481 | static int | 467 | static int wdrtas_temp_open(struct inode *inode, struct file *file) |
| 482 | wdrtas_temp_open(struct inode *inode, struct file *file) | ||
| 483 | { | 468 | { |
| 484 | return nonseekable_open(inode, file); | 469 | return nonseekable_open(inode, file); |
| 485 | } | 470 | } |
| @@ -493,8 +478,7 @@ wdrtas_temp_open(struct inode *inode, struct file *file) | |||
| 493 | * | 478 | * |
| 494 | * close function. Always succeeds | 479 | * close function. Always succeeds |
| 495 | */ | 480 | */ |
| 496 | static int | 481 | static int wdrtas_temp_close(struct inode *inode, struct file *file) |
| 497 | wdrtas_temp_close(struct inode *inode, struct file *file) | ||
| 498 | { | 482 | { |
| 499 | return 0; | 483 | return 0; |
| 500 | } | 484 | } |
| @@ -509,10 +493,10 @@ wdrtas_temp_close(struct inode *inode, struct file *file) | |||
| 509 | * | 493 | * |
| 510 | * wdrtas_reboot stops the watchdog in case of a reboot | 494 | * wdrtas_reboot stops the watchdog in case of a reboot |
| 511 | */ | 495 | */ |
| 512 | static int | 496 | static int wdrtas_reboot(struct notifier_block *this, |
| 513 | wdrtas_reboot(struct notifier_block *this, unsigned long code, void *ptr) | 497 | unsigned long code, void *ptr) |
| 514 | { | 498 | { |
| 515 | if ( (code==SYS_DOWN) || (code==SYS_HALT) ) | 499 | if (code == SYS_DOWN || code == SYS_HALT) |
| 516 | wdrtas_timer_stop(); | 500 | wdrtas_timer_stop(); |
| 517 | 501 | ||
| 518 | return NOTIFY_DONE; | 502 | return NOTIFY_DONE; |
| @@ -524,7 +508,7 @@ static const struct file_operations wdrtas_fops = { | |||
| 524 | .owner = THIS_MODULE, | 508 | .owner = THIS_MODULE, |
| 525 | .llseek = no_llseek, | 509 | .llseek = no_llseek, |
| 526 | .write = wdrtas_write, | 510 | .write = wdrtas_write, |
| 527 | .ioctl = wdrtas_ioctl, | 511 | .unlocked_ioctl = wdrtas_ioctl, |
| 528 | .open = wdrtas_open, | 512 | .open = wdrtas_open, |
| 529 | .release = wdrtas_close, | 513 | .release = wdrtas_close, |
| 530 | }; | 514 | }; |
| @@ -562,8 +546,7 @@ static struct notifier_block wdrtas_notifier = { | |||
| 562 | * this watchdog driver. It tolerates, if "get-sensor-state" and | 546 | * this watchdog driver. It tolerates, if "get-sensor-state" and |
| 563 | * "ibm,get-system-parameter" are not available. | 547 | * "ibm,get-system-parameter" are not available. |
| 564 | */ | 548 | */ |
| 565 | static int | 549 | static int wdrtas_get_tokens(void) |
| 566 | wdrtas_get_tokens(void) | ||
| 567 | { | 550 | { |
| 568 | wdrtas_token_get_sensor_state = rtas_token("get-sensor-state"); | 551 | wdrtas_token_get_sensor_state = rtas_token("get-sensor-state"); |
| 569 | if (wdrtas_token_get_sensor_state == RTAS_UNKNOWN_SERVICE) { | 552 | if (wdrtas_token_get_sensor_state == RTAS_UNKNOWN_SERVICE) { |
| @@ -603,8 +586,7 @@ wdrtas_get_tokens(void) | |||
| 603 | * wdrtas_register_devs unregisters the watchdog and temperature watchdog | 586 | * wdrtas_register_devs unregisters the watchdog and temperature watchdog |
| 604 | * misc devs | 587 | * misc devs |
| 605 | */ | 588 | */ |
| 606 | static void | 589 | static void wdrtas_unregister_devs(void) |
| 607 | wdrtas_unregister_devs(void) | ||
| 608 | { | 590 | { |
| 609 | misc_deregister(&wdrtas_miscdev); | 591 | misc_deregister(&wdrtas_miscdev); |
| 610 | if (wdrtas_token_get_sensor_state != RTAS_UNKNOWN_SERVICE) | 592 | if (wdrtas_token_get_sensor_state != RTAS_UNKNOWN_SERVICE) |
| @@ -619,8 +601,7 @@ wdrtas_unregister_devs(void) | |||
| 619 | * wdrtas_register_devs registers the watchdog and temperature watchdog | 601 | * wdrtas_register_devs registers the watchdog and temperature watchdog |
| 620 | * misc devs | 602 | * misc devs |
| 621 | */ | 603 | */ |
| 622 | static int | 604 | static int wdrtas_register_devs(void) |
| 623 | wdrtas_register_devs(void) | ||
| 624 | { | 605 | { |
| 625 | int result; | 606 | int result; |
| 626 | 607 | ||
| @@ -651,8 +632,7 @@ wdrtas_register_devs(void) | |||
| 651 | * | 632 | * |
| 652 | * registers the file handlers and the reboot notifier | 633 | * registers the file handlers and the reboot notifier |
| 653 | */ | 634 | */ |
| 654 | static int __init | 635 | static int __init wdrtas_init(void) |
| 655 | wdrtas_init(void) | ||
| 656 | { | 636 | { |
| 657 | if (wdrtas_get_tokens()) | 637 | if (wdrtas_get_tokens()) |
| 658 | return -ENODEV; | 638 | return -ENODEV; |
| @@ -680,8 +660,7 @@ wdrtas_init(void) | |||
| 680 | * | 660 | * |
| 681 | * unregisters the file handlers and the reboot notifier | 661 | * unregisters the file handlers and the reboot notifier |
| 682 | */ | 662 | */ |
| 683 | static void __exit | 663 | static void __exit wdrtas_exit(void) |
| 684 | wdrtas_exit(void) | ||
| 685 | { | 664 | { |
| 686 | if (!wdrtas_nowayout) | 665 | if (!wdrtas_nowayout) |
| 687 | wdrtas_timer_stop(); | 666 | wdrtas_timer_stop(); |
diff --git a/drivers/watchdog/wdt.c b/drivers/watchdog/wdt.c index 53a6b18bcb9a..deeebb2b13ea 100644 --- a/drivers/watchdog/wdt.c +++ b/drivers/watchdog/wdt.c | |||
| @@ -373,8 +373,6 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
| 373 | #endif /* CONFIG_WDT_501 */ | 373 | #endif /* CONFIG_WDT_501 */ |
| 374 | 374 | ||
| 375 | switch (cmd) { | 375 | switch (cmd) { |
| 376 | default: | ||
| 377 | return -ENOTTY; | ||
| 378 | case WDIOC_GETSUPPORT: | 376 | case WDIOC_GETSUPPORT: |
| 379 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | 377 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 380 | case WDIOC_GETSTATUS: | 378 | case WDIOC_GETSTATUS: |
| @@ -394,6 +392,8 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
| 394 | /* Fall */ | 392 | /* Fall */ |
| 395 | case WDIOC_GETTIMEOUT: | 393 | case WDIOC_GETTIMEOUT: |
| 396 | return put_user(heartbeat, p); | 394 | return put_user(heartbeat, p); |
| 395 | default: | ||
| 396 | return -ENOTTY; | ||
| 397 | } | 397 | } |
| 398 | } | 398 | } |
| 399 | 399 | ||
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c index 94e2d91c9ac9..c8d7f1b2df02 100644 --- a/drivers/watchdog/wdt285.c +++ b/drivers/watchdog/wdt285.c | |||
| @@ -26,10 +26,10 @@ | |||
| 26 | #include <linux/reboot.h> | 26 | #include <linux/reboot.h> |
| 27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
| 28 | #include <linux/interrupt.h> | 28 | #include <linux/interrupt.h> |
| 29 | 29 | #include <linux/uaccess.h> | |
| 30 | #include <asm/irq.h> | 30 | #include <linux/irq.h> |
| 31 | #include <asm/uaccess.h> | ||
| 32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 32 | |||
| 33 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| 34 | #include <asm/hardware/dec21285.h> | 34 | #include <asm/hardware/dec21285.h> |
| 35 | 35 | ||
| @@ -115,8 +115,8 @@ static int watchdog_release(struct inode *inode, struct file *file) | |||
| 115 | return 0; | 115 | return 0; |
| 116 | } | 116 | } |
| 117 | 117 | ||
| 118 | static ssize_t | 118 | static ssize_t watchdog_write(struct file *file, const char *data, |
| 119 | watchdog_write(struct file *file, const char *data, size_t len, loff_t *ppos) | 119 | size_t len, loff_t *ppos) |
| 120 | { | 120 | { |
| 121 | /* | 121 | /* |
| 122 | * Refresh the timer. | 122 | * Refresh the timer. |
| @@ -127,19 +127,18 @@ watchdog_write(struct file *file, const char *data, size_t len, loff_t *ppos) | |||
| 127 | return len; | 127 | return len; |
| 128 | } | 128 | } |
| 129 | 129 | ||
| 130 | static struct watchdog_info ident = { | 130 | static const struct watchdog_info ident = { |
| 131 | .options = WDIOF_SETTIMEOUT, | 131 | .options = WDIOF_SETTIMEOUT, |
| 132 | .identity = "Footbridge Watchdog", | 132 | .identity = "Footbridge Watchdog", |
| 133 | }; | 133 | }; |
| 134 | 134 | ||
| 135 | static int | 135 | static long watchdog_ioctl(struct file *file, unsigned int cmd, |
| 136 | watchdog_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | 136 | unsigned long arg) |
| 137 | unsigned long arg) | ||
| 138 | { | 137 | { |
| 139 | unsigned int new_margin; | 138 | unsigned int new_margin; |
| 140 | int ret = -ENOTTY; | 139 | int ret = -ENOTTY; |
| 141 | 140 | ||
| 142 | switch(cmd) { | 141 | switch (cmd) { |
| 143 | case WDIOC_GETSUPPORT: | 142 | case WDIOC_GETSUPPORT: |
| 144 | ret = 0; | 143 | ret = 0; |
| 145 | if (copy_to_user((void *)arg, &ident, sizeof(ident))) | 144 | if (copy_to_user((void *)arg, &ident, sizeof(ident))) |
| @@ -148,7 +147,7 @@ watchdog_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |||
| 148 | 147 | ||
| 149 | case WDIOC_GETSTATUS: | 148 | case WDIOC_GETSTATUS: |
| 150 | case WDIOC_GETBOOTSTATUS: | 149 | case WDIOC_GETBOOTSTATUS: |
| 151 | ret = put_user(0,(int *)arg); | 150 | ret = put_user(0, (int *)arg); |
| 152 | break; | 151 | break; |
| 153 | 152 | ||
| 154 | case WDIOC_KEEPALIVE: | 153 | case WDIOC_KEEPALIVE: |
| @@ -182,7 +181,7 @@ static const struct file_operations watchdog_fops = { | |||
| 182 | .owner = THIS_MODULE, | 181 | .owner = THIS_MODULE, |
| 183 | .llseek = no_llseek, | 182 | .llseek = no_llseek, |
| 184 | .write = watchdog_write, | 183 | .write = watchdog_write, |
| 185 | .ioctl = watchdog_ioctl, | 184 | .unlocked_ioctl = watchdog_ioctl, |
| 186 | .open = watchdog_open, | 185 | .open = watchdog_open, |
| 187 | .release = watchdog_release, | 186 | .release = watchdog_release, |
| 188 | }; | 187 | }; |
| @@ -204,11 +203,13 @@ static int __init footbridge_watchdog_init(void) | |||
| 204 | if (retval < 0) | 203 | if (retval < 0) |
| 205 | return retval; | 204 | return retval; |
| 206 | 205 | ||
| 207 | printk("Footbridge Watchdog Timer: 0.01, timer margin: %d sec\n", | 206 | printk(KERN_INFO |
| 208 | soft_margin); | 207 | "Footbridge Watchdog Timer: 0.01, timer margin: %d sec\n", |
| 208 | soft_margin); | ||
| 209 | 209 | ||
| 210 | if (machine_is_cats()) | 210 | if (machine_is_cats()) |
| 211 | printk("Warning: Watchdog reset may not work on this machine.\n"); | 211 | printk(KERN_WARN |
| 212 | "Warning: Watchdog reset may not work on this machine.\n"); | ||
| 212 | return 0; | 213 | return 0; |
| 213 | } | 214 | } |
| 214 | 215 | ||
| @@ -223,7 +224,7 @@ MODULE_LICENSE("GPL"); | |||
| 223 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | 224 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
| 224 | 225 | ||
| 225 | module_param(soft_margin, int, 0); | 226 | module_param(soft_margin, int, 0); |
| 226 | MODULE_PARM_DESC(soft_margin,"Watchdog timeout in seconds"); | 227 | MODULE_PARM_DESC(soft_margin, "Watchdog timeout in seconds"); |
| 227 | 228 | ||
| 228 | module_init(footbridge_watchdog_init); | 229 | module_init(footbridge_watchdog_init); |
| 229 | module_exit(footbridge_watchdog_exit); | 230 | module_exit(footbridge_watchdog_exit); |
diff --git a/drivers/watchdog/wdt977.c b/drivers/watchdog/wdt977.c index fb4b876c9fda..60e28d49ff52 100644 --- a/drivers/watchdog/wdt977.c +++ b/drivers/watchdog/wdt977.c | |||
| @@ -19,7 +19,8 @@ | |||
| 19 | * 07-Jul-2003 Daniele Bellucci: Audit return code of misc_register in | 19 | * 07-Jul-2003 Daniele Bellucci: Audit return code of misc_register in |
| 20 | * nwwatchdog_init. | 20 | * nwwatchdog_init. |
| 21 | * 25-Oct-2005 Woody Suwalski: Convert addresses to #defs, add spinlocks | 21 | * 25-Oct-2005 Woody Suwalski: Convert addresses to #defs, add spinlocks |
| 22 | * remove limitiation to be used on Netwinders only | 22 | * remove limitiation to be used on |
| 23 | * Netwinders only | ||
| 23 | */ | 24 | */ |
| 24 | 25 | ||
| 25 | #include <linux/module.h> | 26 | #include <linux/module.h> |
| @@ -33,11 +34,11 @@ | |||
| 33 | #include <linux/watchdog.h> | 34 | #include <linux/watchdog.h> |
| 34 | #include <linux/notifier.h> | 35 | #include <linux/notifier.h> |
| 35 | #include <linux/reboot.h> | 36 | #include <linux/reboot.h> |
| 37 | #include <linux/io.h> | ||
| 38 | #include <linux/uaccess.h> | ||
| 36 | 39 | ||
| 37 | #include <asm/io.h> | ||
| 38 | #include <asm/system.h> | 40 | #include <asm/system.h> |
| 39 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
| 40 | #include <asm/uaccess.h> | ||
| 41 | 42 | ||
| 42 | #define WATCHDOG_VERSION "0.04" | 43 | #define WATCHDOG_VERSION "0.04" |
| 43 | #define WATCHDOG_NAME "Wdt977" | 44 | #define WATCHDOG_NAME "Wdt977" |
| @@ -45,7 +46,7 @@ | |||
| 45 | #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" | 46 | #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" |
| 46 | 47 | ||
| 47 | #define IO_INDEX_PORT 0x370 /* on some systems it can be 0x3F0 */ | 48 | #define IO_INDEX_PORT 0x370 /* on some systems it can be 0x3F0 */ |
| 48 | #define IO_DATA_PORT (IO_INDEX_PORT+1) | 49 | #define IO_DATA_PORT (IO_INDEX_PORT + 1) |
| 49 | 50 | ||
| 50 | #define UNLOCK_DATA 0x87 | 51 | #define UNLOCK_DATA 0x87 |
| 51 | #define LOCK_DATA 0xAA | 52 | #define LOCK_DATA 0xAA |
| @@ -62,13 +63,16 @@ static char expect_close; | |||
| 62 | static DEFINE_SPINLOCK(spinlock); | 63 | static DEFINE_SPINLOCK(spinlock); |
| 63 | 64 | ||
| 64 | module_param(timeout, int, 0); | 65 | module_param(timeout, int, 0); |
| 65 | MODULE_PARM_DESC(timeout,"Watchdog timeout in seconds (60..15300), default=" __MODULE_STRING(DEFAULT_TIMEOUT) ")"); | 66 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (60..15300), default=" |
| 67 | __MODULE_STRING(DEFAULT_TIMEOUT) ")"); | ||
| 66 | module_param(testmode, int, 0); | 68 | module_param(testmode, int, 0); |
| 67 | MODULE_PARM_DESC(testmode,"Watchdog testmode (1 = no reboot), default=0"); | 69 | MODULE_PARM_DESC(testmode, "Watchdog testmode (1 = no reboot), default=0"); |
| 68 | 70 | ||
| 69 | static int nowayout = WATCHDOG_NOWAYOUT; | 71 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 70 | module_param(nowayout, int, 0); | 72 | module_param(nowayout, int, 0); |
| 71 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 73 | MODULE_PARM_DESC(nowayout, |
| 74 | "Watchdog cannot be stopped once started (default=" | ||
| 75 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 72 | 76 | ||
| 73 | /* | 77 | /* |
| 74 | * Start the watchdog | 78 | * Start the watchdog |
| @@ -95,14 +99,16 @@ static int wdt977_start(void) | |||
| 95 | outb_p(0xF2, IO_INDEX_PORT); | 99 | outb_p(0xF2, IO_INDEX_PORT); |
| 96 | outb_p(timeoutM, IO_DATA_PORT); | 100 | outb_p(timeoutM, IO_DATA_PORT); |
| 97 | outb_p(0xF3, IO_INDEX_PORT); | 101 | outb_p(0xF3, IO_INDEX_PORT); |
| 98 | outb_p(0x00, IO_DATA_PORT); /* another setting is 0E for kbd/mouse/LED */ | 102 | outb_p(0x00, IO_DATA_PORT); /* another setting is 0E for |
| 103 | kbd/mouse/LED */ | ||
| 99 | outb_p(0xF4, IO_INDEX_PORT); | 104 | outb_p(0xF4, IO_INDEX_PORT); |
| 100 | outb_p(0x00, IO_DATA_PORT); | 105 | outb_p(0x00, IO_DATA_PORT); |
| 101 | 106 | ||
| 102 | /* at last select device Aux1 (dev=7) and set GP16 as a watchdog output */ | 107 | /* At last select device Aux1 (dev=7) and set GP16 as a |
| 103 | /* in test mode watch the bit 1 on F4 to indicate "triggered" */ | 108 | * watchdog output. In test mode watch the bit 1 on F4 to |
| 104 | if (!testmode) | 109 | * indicate "triggered" |
| 105 | { | 110 | */ |
| 111 | if (!testmode) { | ||
| 106 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); | 112 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 107 | outb_p(0x07, IO_DATA_PORT); | 113 | outb_p(0x07, IO_DATA_PORT); |
| 108 | outb_p(0xE6, IO_INDEX_PORT); | 114 | outb_p(0xE6, IO_INDEX_PORT); |
| @@ -147,7 +153,8 @@ static int wdt977_stop(void) | |||
| 147 | outb_p(0xF2, IO_INDEX_PORT); | 153 | outb_p(0xF2, IO_INDEX_PORT); |
| 148 | outb_p(0x00, IO_DATA_PORT); | 154 | outb_p(0x00, IO_DATA_PORT); |
| 149 | 155 | ||
| 150 | /* at last select device Aux1 (dev=7) and set GP16 as a watchdog output */ | 156 | /* at last select device Aux1 (dev=7) and set |
| 157 | GP16 as a watchdog output */ | ||
| 151 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); | 158 | outb_p(DEVICE_REGISTER, IO_INDEX_PORT); |
| 152 | outb_p(0x07, IO_DATA_PORT); | 159 | outb_p(0x07, IO_DATA_PORT); |
| 153 | outb_p(0xE6, IO_INDEX_PORT); | 160 | outb_p(0xE6, IO_INDEX_PORT); |
| @@ -202,16 +209,18 @@ static int wdt977_set_timeout(int t) | |||
| 202 | tmrval = (t + 59) / 60; | 209 | tmrval = (t + 59) / 60; |
| 203 | 210 | ||
| 204 | if (machine_is_netwinder()) { | 211 | if (machine_is_netwinder()) { |
| 205 | /* we have a hw bug somewhere, so each 977 minute is actually only 30sec | 212 | /* we have a hw bug somewhere, so each 977 minute is actually |
| 206 | * this limits the max timeout to half of device max of 255 minutes... | 213 | * only 30sec. This limits the max timeout to half of device |
| 214 | * max of 255 minutes... | ||
| 207 | */ | 215 | */ |
| 208 | tmrval += tmrval; | 216 | tmrval += tmrval; |
| 209 | } | 217 | } |
| 210 | 218 | ||
| 211 | if ((tmrval < 1) || (tmrval > 255)) | 219 | if (tmrval < 1 || tmrval > 255) |
| 212 | return -EINVAL; | 220 | return -EINVAL; |
| 213 | 221 | ||
| 214 | /* timeout is the timeout in seconds, timeoutM is the timeout in minutes) */ | 222 | /* timeout is the timeout in seconds, timeoutM is |
| 223 | the timeout in minutes) */ | ||
| 215 | timeout = t; | 224 | timeout = t; |
| 216 | timeoutM = tmrval; | 225 | timeoutM = tmrval; |
| 217 | return 0; | 226 | return 0; |
| @@ -243,7 +252,7 @@ static int wdt977_get_status(int *status) | |||
| 243 | 252 | ||
| 244 | spin_unlock_irqrestore(&spinlock, flags); | 253 | spin_unlock_irqrestore(&spinlock, flags); |
| 245 | 254 | ||
| 246 | *status=0; | 255 | *status = 0; |
| 247 | if (new_status & 1) | 256 | if (new_status & 1) |
| 248 | *status |= WDIOF_CARDRESET; | 257 | *status |= WDIOF_CARDRESET; |
| 249 | 258 | ||
| @@ -258,7 +267,7 @@ static int wdt977_get_status(int *status) | |||
| 258 | static int wdt977_open(struct inode *inode, struct file *file) | 267 | static int wdt977_open(struct inode *inode, struct file *file) |
| 259 | { | 268 | { |
| 260 | /* If the watchdog is alive we don't need to start it again */ | 269 | /* If the watchdog is alive we don't need to start it again */ |
| 261 | if( test_and_set_bit(0,&timer_alive) ) | 270 | if (test_and_set_bit(0, &timer_alive)) |
| 262 | return -EBUSY; | 271 | return -EBUSY; |
| 263 | 272 | ||
| 264 | if (nowayout) | 273 | if (nowayout) |
| @@ -274,13 +283,13 @@ static int wdt977_release(struct inode *inode, struct file *file) | |||
| 274 | * Shut off the timer. | 283 | * Shut off the timer. |
| 275 | * Lock it in if it's a module and we set nowayout | 284 | * Lock it in if it's a module and we set nowayout |
| 276 | */ | 285 | */ |
| 277 | if (expect_close == 42) | 286 | if (expect_close == 42) { |
| 278 | { | ||
| 279 | wdt977_stop(); | 287 | wdt977_stop(); |
| 280 | clear_bit(0,&timer_alive); | 288 | clear_bit(0, &timer_alive); |
| 281 | } else { | 289 | } else { |
| 282 | wdt977_keepalive(); | 290 | wdt977_keepalive(); |
| 283 | printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); | 291 | printk(KERN_CRIT PFX |
| 292 | "Unexpected close, not stopping watchdog!\n"); | ||
| 284 | } | 293 | } |
| 285 | expect_close = 0; | 294 | expect_close = 0; |
| 286 | return 0; | 295 | return 0; |
| @@ -301,17 +310,14 @@ static int wdt977_release(struct inode *inode, struct file *file) | |||
| 301 | static ssize_t wdt977_write(struct file *file, const char __user *buf, | 310 | static ssize_t wdt977_write(struct file *file, const char __user *buf, |
| 302 | size_t count, loff_t *ppos) | 311 | size_t count, loff_t *ppos) |
| 303 | { | 312 | { |
| 304 | if (count) | 313 | if (count) { |
| 305 | { | 314 | if (!nowayout) { |
| 306 | if (!nowayout) | ||
| 307 | { | ||
| 308 | size_t i; | 315 | size_t i; |
| 309 | 316 | ||
| 310 | /* In case it was set long ago */ | 317 | /* In case it was set long ago */ |
| 311 | expect_close = 0; | 318 | expect_close = 0; |
| 312 | 319 | ||
| 313 | for (i = 0; i != count; i++) | 320 | for (i = 0; i != count; i++) { |
| 314 | { | ||
| 315 | char c; | 321 | char c; |
| 316 | if (get_user(c, buf + i)) | 322 | if (get_user(c, buf + i)) |
| 317 | return -EFAULT; | 323 | return -EFAULT; |
| @@ -326,6 +332,14 @@ static ssize_t wdt977_write(struct file *file, const char __user *buf, | |||
| 326 | return count; | 332 | return count; |
| 327 | } | 333 | } |
| 328 | 334 | ||
| 335 | static const struct watchdog_info ident = { | ||
| 336 | .options = WDIOF_SETTIMEOUT | | ||
| 337 | WDIOF_MAGICCLOSE | | ||
| 338 | WDIOF_KEEPALIVEPING, | ||
| 339 | .firmware_version = 1, | ||
| 340 | .identity = WATCHDOG_NAME, | ||
| 341 | }; | ||
| 342 | |||
| 329 | /* | 343 | /* |
| 330 | * wdt977_ioctl: | 344 | * wdt977_ioctl: |
| 331 | * @inode: inode of the device | 345 | * @inode: inode of the device |
| @@ -337,16 +351,8 @@ static ssize_t wdt977_write(struct file *file, const char __user *buf, | |||
| 337 | * according to their available features. | 351 | * according to their available features. |
| 338 | */ | 352 | */ |
| 339 | 353 | ||
| 340 | static struct watchdog_info ident = { | 354 | static long wdt977_ioctl(struct file *file, unsigned int cmd, |
| 341 | .options = WDIOF_SETTIMEOUT | | 355 | unsigned long arg) |
| 342 | WDIOF_MAGICCLOSE | | ||
| 343 | WDIOF_KEEPALIVEPING, | ||
| 344 | .firmware_version = 1, | ||
| 345 | .identity = WATCHDOG_NAME, | ||
| 346 | }; | ||
| 347 | |||
| 348 | static int wdt977_ioctl(struct inode *inode, struct file *file, | ||
| 349 | unsigned int cmd, unsigned long arg) | ||
| 350 | { | 356 | { |
| 351 | int status; | 357 | int status; |
| 352 | int new_options, retval = -EINVAL; | 358 | int new_options, retval = -EINVAL; |
| @@ -358,11 +364,7 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, | |||
| 358 | 364 | ||
| 359 | uarg.i = (int __user *)arg; | 365 | uarg.i = (int __user *)arg; |
| 360 | 366 | ||
| 361 | switch(cmd) | 367 | switch (cmd) { |
| 362 | { | ||
| 363 | default: | ||
| 364 | return -ENOTTY; | ||
| 365 | |||
| 366 | case WDIOC_GETSUPPORT: | 368 | case WDIOC_GETSUPPORT: |
| 367 | return copy_to_user(uarg.ident, &ident, | 369 | return copy_to_user(uarg.ident, &ident, |
| 368 | sizeof(ident)) ? -EFAULT : 0; | 370 | sizeof(ident)) ? -EFAULT : 0; |
| @@ -374,12 +376,8 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, | |||
| 374 | case WDIOC_GETBOOTSTATUS: | 376 | case WDIOC_GETBOOTSTATUS: |
| 375 | return put_user(0, uarg.i); | 377 | return put_user(0, uarg.i); |
| 376 | 378 | ||
| 377 | case WDIOC_KEEPALIVE: | ||
| 378 | wdt977_keepalive(); | ||
| 379 | return 0; | ||
| 380 | |||
| 381 | case WDIOC_SETOPTIONS: | 379 | case WDIOC_SETOPTIONS: |
| 382 | if (get_user (new_options, uarg.i)) | 380 | if (get_user(new_options, uarg.i)) |
| 383 | return -EFAULT; | 381 | return -EFAULT; |
| 384 | 382 | ||
| 385 | if (new_options & WDIOS_DISABLECARD) { | 383 | if (new_options & WDIOS_DISABLECARD) { |
| @@ -394,6 +392,10 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, | |||
| 394 | 392 | ||
| 395 | return retval; | 393 | return retval; |
| 396 | 394 | ||
| 395 | case WDIOC_KEEPALIVE: | ||
| 396 | wdt977_keepalive(); | ||
| 397 | return 0; | ||
| 398 | |||
| 397 | case WDIOC_SETTIMEOUT: | 399 | case WDIOC_SETTIMEOUT: |
| 398 | if (get_user(new_timeout, uarg.i)) | 400 | if (get_user(new_timeout, uarg.i)) |
| 399 | return -EFAULT; | 401 | return -EFAULT; |
| @@ -407,29 +409,30 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, | |||
| 407 | case WDIOC_GETTIMEOUT: | 409 | case WDIOC_GETTIMEOUT: |
| 408 | return put_user(timeout, uarg.i); | 410 | return put_user(timeout, uarg.i); |
| 409 | 411 | ||
| 412 | default: | ||
| 413 | return -ENOTTY; | ||
| 414 | |||
| 410 | } | 415 | } |
| 411 | } | 416 | } |
| 412 | 417 | ||
| 413 | static int wdt977_notify_sys(struct notifier_block *this, unsigned long code, | 418 | static int wdt977_notify_sys(struct notifier_block *this, unsigned long code, |
| 414 | void *unused) | 419 | void *unused) |
| 415 | { | 420 | { |
| 416 | if(code==SYS_DOWN || code==SYS_HALT) | 421 | if (code == SYS_DOWN || code == SYS_HALT) |
| 417 | wdt977_stop(); | 422 | wdt977_stop(); |
| 418 | return NOTIFY_DONE; | 423 | return NOTIFY_DONE; |
| 419 | } | 424 | } |
| 420 | 425 | ||
| 421 | static const struct file_operations wdt977_fops= | 426 | static const struct file_operations wdt977_fops = { |
| 422 | { | ||
| 423 | .owner = THIS_MODULE, | 427 | .owner = THIS_MODULE, |
| 424 | .llseek = no_llseek, | 428 | .llseek = no_llseek, |
| 425 | .write = wdt977_write, | 429 | .write = wdt977_write, |
| 426 | .ioctl = wdt977_ioctl, | 430 | .unlocked_ioctl = wdt977_ioctl, |
| 427 | .open = wdt977_open, | 431 | .open = wdt977_open, |
| 428 | .release = wdt977_release, | 432 | .release = wdt977_release, |
| 429 | }; | 433 | }; |
| 430 | 434 | ||
| 431 | static struct miscdevice wdt977_miscdev= | 435 | static struct miscdevice wdt977_miscdev = { |
| 432 | { | ||
| 433 | .minor = WATCHDOG_MINOR, | 436 | .minor = WATCHDOG_MINOR, |
| 434 | .name = "watchdog", | 437 | .name = "watchdog", |
| 435 | .fops = &wdt977_fops, | 438 | .fops = &wdt977_fops, |
| @@ -443,51 +446,48 @@ static int __init wd977_init(void) | |||
| 443 | { | 446 | { |
| 444 | int rc; | 447 | int rc; |
| 445 | 448 | ||
| 446 | //if (!machine_is_netwinder()) | ||
| 447 | // return -ENODEV; | ||
| 448 | |||
| 449 | printk(KERN_INFO PFX DRIVER_VERSION); | 449 | printk(KERN_INFO PFX DRIVER_VERSION); |
| 450 | 450 | ||
| 451 | /* Check that the timeout value is within it's range ; if not reset to the default */ | 451 | /* Check that the timeout value is within its range; |
| 452 | if (wdt977_set_timeout(timeout)) | 452 | if not reset to the default */ |
| 453 | { | 453 | if (wdt977_set_timeout(timeout)) { |
| 454 | wdt977_set_timeout(DEFAULT_TIMEOUT); | 454 | wdt977_set_timeout(DEFAULT_TIMEOUT); |
| 455 | printk(KERN_INFO PFX "timeout value must be 60<timeout<15300, using %d\n", | 455 | printk(KERN_INFO PFX |
| 456 | DEFAULT_TIMEOUT); | 456 | "timeout value must be 60 < timeout < 15300, using %d\n", |
| 457 | DEFAULT_TIMEOUT); | ||
| 457 | } | 458 | } |
| 458 | 459 | ||
| 459 | /* on Netwinder the IOports are already reserved by | 460 | /* on Netwinder the IOports are already reserved by |
| 460 | * arch/arm/mach-footbridge/netwinder-hw.c | 461 | * arch/arm/mach-footbridge/netwinder-hw.c |
| 461 | */ | 462 | */ |
| 462 | if (!machine_is_netwinder()) | 463 | if (!machine_is_netwinder()) { |
| 463 | { | 464 | if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) { |
| 464 | if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) | 465 | printk(KERN_ERR PFX |
| 465 | { | 466 | "I/O address 0x%04x already in use\n", |
| 466 | printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", | 467 | IO_INDEX_PORT); |
| 467 | IO_INDEX_PORT); | ||
| 468 | rc = -EIO; | 468 | rc = -EIO; |
| 469 | goto err_out; | 469 | goto err_out; |
| 470 | } | 470 | } |
| 471 | } | 471 | } |
| 472 | 472 | ||
| 473 | rc = register_reboot_notifier(&wdt977_notifier); | 473 | rc = register_reboot_notifier(&wdt977_notifier); |
| 474 | if (rc) | 474 | if (rc) { |
| 475 | { | 475 | printk(KERN_ERR PFX |
| 476 | printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", | 476 | "cannot register reboot notifier (err=%d)\n", rc); |
| 477 | rc); | ||
| 478 | goto err_out_region; | 477 | goto err_out_region; |
| 479 | } | 478 | } |
| 480 | 479 | ||
| 481 | rc = misc_register(&wdt977_miscdev); | 480 | rc = misc_register(&wdt977_miscdev); |
| 482 | if (rc) | 481 | if (rc) { |
| 483 | { | 482 | printk(KERN_ERR PFX |
| 484 | printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", | 483 | "cannot register miscdev on minor=%d (err=%d)\n", |
| 485 | wdt977_miscdev.minor, rc); | 484 | wdt977_miscdev.minor, rc); |
| 486 | goto err_out_reboot; | 485 | goto err_out_reboot; |
| 487 | } | 486 | } |
| 488 | 487 | ||
| 489 | printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d, testmode=%i)\n", | 488 | printk(KERN_INFO PFX |
| 490 | timeout, nowayout, testmode); | 489 | "initialized. timeout=%d sec (nowayout=%d, testmode=%i)\n", |
| 490 | timeout, nowayout, testmode); | ||
| 491 | 491 | ||
| 492 | return 0; | 492 | return 0; |
| 493 | 493 | ||
| @@ -495,7 +495,7 @@ err_out_reboot: | |||
| 495 | unregister_reboot_notifier(&wdt977_notifier); | 495 | unregister_reboot_notifier(&wdt977_notifier); |
| 496 | err_out_region: | 496 | err_out_region: |
| 497 | if (!machine_is_netwinder()) | 497 | if (!machine_is_netwinder()) |
| 498 | release_region(IO_INDEX_PORT,2); | 498 | release_region(IO_INDEX_PORT, 2); |
| 499 | err_out: | 499 | err_out: |
| 500 | return rc; | 500 | return rc; |
| 501 | } | 501 | } |
| @@ -505,7 +505,7 @@ static void __exit wd977_exit(void) | |||
| 505 | wdt977_stop(); | 505 | wdt977_stop(); |
| 506 | misc_deregister(&wdt977_miscdev); | 506 | misc_deregister(&wdt977_miscdev); |
| 507 | unregister_reboot_notifier(&wdt977_notifier); | 507 | unregister_reboot_notifier(&wdt977_notifier); |
| 508 | release_region(IO_INDEX_PORT,2); | 508 | release_region(IO_INDEX_PORT, 2); |
| 509 | } | 509 | } |
| 510 | 510 | ||
| 511 | module_init(wd977_init); | 511 | module_init(wd977_init); |
diff --git a/drivers/watchdog/wdt_pci.c b/drivers/watchdog/wdt_pci.c index 5d922fd6eafc..ed02bdb38c09 100644 --- a/drivers/watchdog/wdt_pci.c +++ b/drivers/watchdog/wdt_pci.c | |||
| @@ -381,7 +381,7 @@ static ssize_t wdtpci_write(struct file *file, const char __user *buf, | |||
| 381 | 381 | ||
| 382 | for (i = 0; i != count; i++) { | 382 | for (i = 0; i != count; i++) { |
| 383 | char c; | 383 | char c; |
| 384 | if (get_user(c, buf+i)) | 384 | if (get_user(c, buf + i)) |
| 385 | return -EFAULT; | 385 | return -EFAULT; |
| 386 | if (c == 'V') | 386 | if (c == 'V') |
| 387 | expect_close = 42; | 387 | expect_close = 42; |
| @@ -428,8 +428,6 @@ static long wdtpci_ioctl(struct file *file, unsigned int cmd, | |||
| 428 | #endif /* CONFIG_WDT_501_PCI */ | 428 | #endif /* CONFIG_WDT_501_PCI */ |
| 429 | 429 | ||
| 430 | switch (cmd) { | 430 | switch (cmd) { |
| 431 | default: | ||
| 432 | return -ENOTTY; | ||
| 433 | case WDIOC_GETSUPPORT: | 431 | case WDIOC_GETSUPPORT: |
| 434 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | 432 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
| 435 | case WDIOC_GETSTATUS: | 433 | case WDIOC_GETSTATUS: |
| @@ -449,7 +447,9 @@ static long wdtpci_ioctl(struct file *file, unsigned int cmd, | |||
| 449 | /* Fall */ | 447 | /* Fall */ |
| 450 | case WDIOC_GETTIMEOUT: | 448 | case WDIOC_GETTIMEOUT: |
| 451 | return put_user(heartbeat, p); | 449 | return put_user(heartbeat, p); |
| 452 | } | 450 | default: |
| 451 | return -ENOTTY; | ||
| 452 | } | ||
| 453 | } | 453 | } |
| 454 | 454 | ||
| 455 | /** | 455 | /** |
| @@ -77,11 +77,8 @@ struct bio_vec *bvec_alloc_bs(gfp_t gfp_mask, int nr, unsigned long *idx, struct | |||
| 77 | */ | 77 | */ |
| 78 | 78 | ||
| 79 | bvl = mempool_alloc(bs->bvec_pools[*idx], gfp_mask); | 79 | bvl = mempool_alloc(bs->bvec_pools[*idx], gfp_mask); |
| 80 | if (bvl) { | 80 | if (bvl) |
| 81 | struct biovec_slab *bp = bvec_slabs + *idx; | 81 | memset(bvl, 0, bvec_nr_vecs(*idx) * sizeof(struct bio_vec)); |
| 82 | |||
| 83 | memset(bvl, 0, bp->nr_vecs * sizeof(struct bio_vec)); | ||
| 84 | } | ||
| 85 | 82 | ||
| 86 | return bvl; | 83 | return bvl; |
| 87 | } | 84 | } |
| @@ -149,7 +146,7 @@ struct bio *bio_alloc_bioset(gfp_t gfp_mask, int nr_iovecs, struct bio_set *bs) | |||
| 149 | goto out; | 146 | goto out; |
| 150 | } | 147 | } |
| 151 | bio->bi_flags |= idx << BIO_POOL_OFFSET; | 148 | bio->bi_flags |= idx << BIO_POOL_OFFSET; |
| 152 | bio->bi_max_vecs = bvec_slabs[idx].nr_vecs; | 149 | bio->bi_max_vecs = bvec_nr_vecs(idx); |
| 153 | } | 150 | } |
| 154 | bio->bi_io_vec = bvl; | 151 | bio->bi_io_vec = bvl; |
| 155 | } | 152 | } |
diff --git a/fs/cifs/CHANGES b/fs/cifs/CHANGES index 1f3465201fdf..f5d0083e09fa 100644 --- a/fs/cifs/CHANGES +++ b/fs/cifs/CHANGES | |||
| @@ -1,3 +1,11 @@ | |||
| 1 | Version 1.54 | ||
| 2 | ------------ | ||
| 3 | Fix premature write failure on congested networks (we would give up | ||
| 4 | on EAGAIN from the socket too quickly on large writes). | ||
| 5 | Cifs_mkdir and cifs_create now respect the setgid bit on parent dir. | ||
| 6 | Fix endian problems in acl (mode from/to cifs acl) on bigendian | ||
| 7 | architectures. | ||
| 8 | |||
| 1 | Version 1.53 | 9 | Version 1.53 |
| 2 | ------------ | 10 | ------------ |
| 3 | DFS support added (Microsoft Distributed File System client support needed | 11 | DFS support added (Microsoft Distributed File System client support needed |
diff --git a/fs/cifs/asn1.c b/fs/cifs/asn1.c index 6bb440b257b0..5fabd2caf93c 100644 --- a/fs/cifs/asn1.c +++ b/fs/cifs/asn1.c | |||
| @@ -483,6 +483,7 @@ decode_negTokenInit(unsigned char *security_blob, int length, | |||
| 483 | 483 | ||
| 484 | asn1_open(&ctx, security_blob, length); | 484 | asn1_open(&ctx, security_blob, length); |
| 485 | 485 | ||
| 486 | /* GSSAPI header */ | ||
| 486 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 487 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 487 | cFYI(1, ("Error decoding negTokenInit header")); | 488 | cFYI(1, ("Error decoding negTokenInit header")); |
| 488 | return 0; | 489 | return 0; |
| @@ -490,153 +491,142 @@ decode_negTokenInit(unsigned char *security_blob, int length, | |||
| 490 | || (tag != ASN1_EOC)) { | 491 | || (tag != ASN1_EOC)) { |
| 491 | cFYI(1, ("cls = %d con = %d tag = %d", cls, con, tag)); | 492 | cFYI(1, ("cls = %d con = %d tag = %d", cls, con, tag)); |
| 492 | return 0; | 493 | return 0; |
| 493 | } else { | 494 | } |
| 494 | /* remember to free obj->oid */ | ||
| 495 | rc = asn1_header_decode(&ctx, &end, &cls, &con, &tag); | ||
| 496 | if (rc) { | ||
| 497 | if ((tag == ASN1_OJI) && (con == ASN1_PRI)) { | ||
| 498 | rc = asn1_oid_decode(&ctx, end, &oid, &oidlen); | ||
| 499 | if (rc) { | ||
| 500 | rc = compare_oid(oid, oidlen, | ||
| 501 | SPNEGO_OID, | ||
| 502 | SPNEGO_OID_LEN); | ||
| 503 | kfree(oid); | ||
| 504 | } | ||
| 505 | } else | ||
| 506 | rc = 0; | ||
| 507 | } | ||
| 508 | 495 | ||
| 509 | if (!rc) { | 496 | /* Check for SPNEGO OID -- remember to free obj->oid */ |
| 510 | cFYI(1, ("Error decoding negTokenInit header")); | 497 | rc = asn1_header_decode(&ctx, &end, &cls, &con, &tag); |
| 511 | return 0; | 498 | if (rc) { |
| 512 | } | 499 | if ((tag == ASN1_OJI) && (con == ASN1_PRI) && |
| 500 | (cls == ASN1_UNI)) { | ||
| 501 | rc = asn1_oid_decode(&ctx, end, &oid, &oidlen); | ||
| 502 | if (rc) { | ||
| 503 | rc = compare_oid(oid, oidlen, SPNEGO_OID, | ||
| 504 | SPNEGO_OID_LEN); | ||
| 505 | kfree(oid); | ||
| 506 | } | ||
| 507 | } else | ||
| 508 | rc = 0; | ||
| 509 | } | ||
| 513 | 510 | ||
| 514 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 511 | /* SPNEGO OID not present or garbled -- bail out */ |
| 515 | cFYI(1, ("Error decoding negTokenInit")); | 512 | if (!rc) { |
| 516 | return 0; | 513 | cFYI(1, ("Error decoding negTokenInit header")); |
| 517 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON) | 514 | return 0; |
| 518 | || (tag != ASN1_EOC)) { | 515 | } |
| 519 | cFYI(1, | ||
| 520 | ("cls = %d con = %d tag = %d end = %p (%d) exit 0", | ||
| 521 | cls, con, tag, end, *end)); | ||
| 522 | return 0; | ||
| 523 | } | ||
| 524 | 516 | ||
| 525 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 517 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 526 | cFYI(1, ("Error decoding negTokenInit")); | 518 | cFYI(1, ("Error decoding negTokenInit")); |
| 527 | return 0; | 519 | return 0; |
| 528 | } else if ((cls != ASN1_UNI) || (con != ASN1_CON) | 520 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON) |
| 529 | || (tag != ASN1_SEQ)) { | 521 | || (tag != ASN1_EOC)) { |
| 530 | cFYI(1, | 522 | cFYI(1, |
| 531 | ("cls = %d con = %d tag = %d end = %p (%d) exit 1", | 523 | ("cls = %d con = %d tag = %d end = %p (%d) exit 0", |
| 532 | cls, con, tag, end, *end)); | 524 | cls, con, tag, end, *end)); |
| 533 | return 0; | 525 | return 0; |
| 534 | } | 526 | } |
| 535 | 527 | ||
| 536 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 528 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 537 | cFYI(1, ("Error decoding 2nd part of negTokenInit")); | 529 | cFYI(1, ("Error decoding negTokenInit")); |
| 538 | return 0; | 530 | return 0; |
| 539 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON) | 531 | } else if ((cls != ASN1_UNI) || (con != ASN1_CON) |
| 540 | || (tag != ASN1_EOC)) { | 532 | || (tag != ASN1_SEQ)) { |
| 541 | cFYI(1, | 533 | cFYI(1, |
| 542 | ("cls = %d con = %d tag = %d end = %p (%d) exit 0", | 534 | ("cls = %d con = %d tag = %d end = %p (%d) exit 1", |
| 543 | cls, con, tag, end, *end)); | 535 | cls, con, tag, end, *end)); |
| 544 | return 0; | 536 | return 0; |
| 545 | } | 537 | } |
| 546 | 538 | ||
| 547 | if (asn1_header_decode | 539 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 548 | (&ctx, &sequence_end, &cls, &con, &tag) == 0) { | 540 | cFYI(1, ("Error decoding 2nd part of negTokenInit")); |
| 549 | cFYI(1, ("Error decoding 2nd part of negTokenInit")); | 541 | return 0; |
| 550 | return 0; | 542 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON) |
| 551 | } else if ((cls != ASN1_UNI) || (con != ASN1_CON) | 543 | || (tag != ASN1_EOC)) { |
| 552 | || (tag != ASN1_SEQ)) { | 544 | cFYI(1, |
| 553 | cFYI(1, | 545 | ("cls = %d con = %d tag = %d end = %p (%d) exit 0", |
| 554 | ("cls = %d con = %d tag = %d end = %p (%d) exit 1", | 546 | cls, con, tag, end, *end)); |
| 555 | cls, con, tag, end, *end)); | 547 | return 0; |
| 556 | return 0; | 548 | } |
| 557 | } | ||
| 558 | 549 | ||
| 559 | while (!asn1_eoc_decode(&ctx, sequence_end)) { | 550 | if (asn1_header_decode |
| 560 | rc = asn1_header_decode(&ctx, &end, &cls, &con, &tag); | 551 | (&ctx, &sequence_end, &cls, &con, &tag) == 0) { |
| 561 | if (!rc) { | 552 | cFYI(1, ("Error decoding 2nd part of negTokenInit")); |
| 562 | cFYI(1, | 553 | return 0; |
| 563 | ("Error decoding negTokenInit hdr exit2")); | 554 | } else if ((cls != ASN1_UNI) || (con != ASN1_CON) |
| 564 | return 0; | 555 | || (tag != ASN1_SEQ)) { |
| 565 | } | 556 | cFYI(1, |
| 566 | if ((tag == ASN1_OJI) && (con == ASN1_PRI)) { | 557 | ("cls = %d con = %d tag = %d end = %p (%d) exit 1", |
| 567 | if (asn1_oid_decode(&ctx, end, &oid, &oidlen)) { | 558 | cls, con, tag, end, *end)); |
| 568 | 559 | return 0; | |
| 569 | cFYI(1, | 560 | } |
| 570 | ("OID len = %d oid = 0x%lx 0x%lx " | ||
| 571 | "0x%lx 0x%lx", | ||
| 572 | oidlen, *oid, *(oid + 1), | ||
| 573 | *(oid + 2), *(oid + 3))); | ||
| 574 | |||
| 575 | if (compare_oid(oid, oidlen, | ||
| 576 | MSKRB5_OID, | ||
| 577 | MSKRB5_OID_LEN)) | ||
| 578 | use_kerberos = true; | ||
| 579 | else if (compare_oid(oid, oidlen, | ||
| 580 | KRB5_OID, | ||
| 581 | KRB5_OID_LEN)) | ||
| 582 | use_kerberos = true; | ||
| 583 | else if (compare_oid(oid, oidlen, | ||
| 584 | NTLMSSP_OID, | ||
| 585 | NTLMSSP_OID_LEN)) | ||
| 586 | use_ntlmssp = true; | ||
| 587 | |||
| 588 | kfree(oid); | ||
| 589 | } | ||
| 590 | } else { | ||
| 591 | cFYI(1, ("Should be an oid what is going on?")); | ||
| 592 | } | ||
| 593 | } | ||
| 594 | 561 | ||
| 595 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 562 | while (!asn1_eoc_decode(&ctx, sequence_end)) { |
| 596 | cFYI(1, | 563 | rc = asn1_header_decode(&ctx, &end, &cls, &con, &tag); |
| 597 | ("Error decoding last part negTokenInit exit3")); | 564 | if (!rc) { |
| 598 | return 0; | ||
| 599 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON)) { | ||
| 600 | /* tag = 3 indicating mechListMIC */ | ||
| 601 | cFYI(1, | 565 | cFYI(1, |
| 602 | ("Exit 4 cls = %d con = %d tag = %d end = %p (%d)", | 566 | ("Error decoding negTokenInit hdr exit2")); |
| 603 | cls, con, tag, end, *end)); | ||
| 604 | return 0; | 567 | return 0; |
| 605 | } | 568 | } |
| 606 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 569 | if ((tag == ASN1_OJI) && (con == ASN1_PRI)) { |
| 607 | cFYI(1, | 570 | if (asn1_oid_decode(&ctx, end, &oid, &oidlen)) { |
| 608 | ("Error decoding last part negTokenInit exit5")); | 571 | |
| 609 | return 0; | 572 | cFYI(1, ("OID len = %d oid = 0x%lx 0x%lx " |
| 610 | } else if ((cls != ASN1_UNI) || (con != ASN1_CON) | 573 | "0x%lx 0x%lx", oidlen, *oid, |
| 611 | || (tag != ASN1_SEQ)) { | 574 | *(oid + 1), *(oid + 2), *(oid + 3))); |
| 612 | cFYI(1, ("cls = %d con = %d tag = %d end = %p (%d)", | 575 | |
| 613 | cls, con, tag, end, *end)); | 576 | if (compare_oid(oid, oidlen, MSKRB5_OID, |
| 577 | MSKRB5_OID_LEN)) | ||
| 578 | use_kerberos = true; | ||
| 579 | else if (compare_oid(oid, oidlen, KRB5_OID, | ||
| 580 | KRB5_OID_LEN)) | ||
| 581 | use_kerberos = true; | ||
| 582 | else if (compare_oid(oid, oidlen, NTLMSSP_OID, | ||
| 583 | NTLMSSP_OID_LEN)) | ||
| 584 | use_ntlmssp = true; | ||
| 585 | |||
| 586 | kfree(oid); | ||
| 587 | } | ||
| 588 | } else { | ||
| 589 | cFYI(1, ("Should be an oid what is going on?")); | ||
| 614 | } | 590 | } |
| 591 | } | ||
| 615 | 592 | ||
| 616 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 593 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 617 | cFYI(1, | 594 | cFYI(1, ("Error decoding last part negTokenInit exit3")); |
| 618 | ("Error decoding last part negTokenInit exit 7")); | 595 | return 0; |
| 619 | return 0; | 596 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON)) { |
| 620 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON)) { | 597 | /* tag = 3 indicating mechListMIC */ |
| 621 | cFYI(1, | 598 | cFYI(1, ("Exit 4 cls = %d con = %d tag = %d end = %p (%d)", |
| 622 | ("Exit 8 cls = %d con = %d tag = %d end = %p (%d)", | 599 | cls, con, tag, end, *end)); |
| 623 | cls, con, tag, end, *end)); | 600 | return 0; |
| 624 | return 0; | 601 | } |
| 625 | } | 602 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 626 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | 603 | cFYI(1, ("Error decoding last part negTokenInit exit5")); |
| 627 | cFYI(1, | 604 | return 0; |
| 628 | ("Error decoding last part negTokenInit exit9")); | 605 | } else if ((cls != ASN1_UNI) || (con != ASN1_CON) |
| 629 | return 0; | 606 | || (tag != ASN1_SEQ)) { |
| 630 | } else if ((cls != ASN1_UNI) || (con != ASN1_PRI) | 607 | cFYI(1, ("cls = %d con = %d tag = %d end = %p (%d)", |
| 631 | || (tag != ASN1_GENSTR)) { | 608 | cls, con, tag, end, *end)); |
| 632 | cFYI(1, | 609 | } |
| 633 | ("Exit10 cls = %d con = %d tag = %d end = %p (%d)", | 610 | |
| 634 | cls, con, tag, end, *end)); | 611 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { |
| 635 | return 0; | 612 | cFYI(1, ("Error decoding last part negTokenInit exit 7")); |
| 636 | } | 613 | return 0; |
| 637 | cFYI(1, ("Need to call asn1_octets_decode() function for %s", | 614 | } else if ((cls != ASN1_CTX) || (con != ASN1_CON)) { |
| 638 | ctx.pointer)); /* is this UTF-8 or ASCII? */ | 615 | cFYI(1, ("Exit 8 cls = %d con = %d tag = %d end = %p (%d)", |
| 616 | cls, con, tag, end, *end)); | ||
| 617 | return 0; | ||
| 618 | } | ||
| 619 | if (asn1_header_decode(&ctx, &end, &cls, &con, &tag) == 0) { | ||
| 620 | cFYI(1, ("Error decoding last part negTokenInit exit9")); | ||
| 621 | return 0; | ||
| 622 | } else if ((cls != ASN1_UNI) || (con != ASN1_PRI) | ||
| 623 | || (tag != ASN1_GENSTR)) { | ||
| 624 | cFYI(1, ("Exit10 cls = %d con = %d tag = %d end = %p (%d)", | ||
| 625 | cls, con, tag, end, *end)); | ||
| 626 | return 0; | ||
| 639 | } | 627 | } |
| 628 | cFYI(1, ("Need to call asn1_octets_decode() function for %s", | ||
| 629 | ctx.pointer)); /* is this UTF-8 or ASCII? */ | ||
| 640 | 630 | ||
| 641 | if (use_kerberos) | 631 | if (use_kerberos) |
| 642 | *secType = Kerberos; | 632 | *secType = Kerberos; |
diff --git a/fs/cifs/cifs_debug.c b/fs/cifs/cifs_debug.c index 688a2d42153f..69a12aae91d3 100644 --- a/fs/cifs/cifs_debug.c +++ b/fs/cifs/cifs_debug.c | |||
| @@ -79,27 +79,25 @@ void cifs_dump_mids(struct TCP_Server_Info *server) | |||
| 79 | spin_lock(&GlobalMid_Lock); | 79 | spin_lock(&GlobalMid_Lock); |
| 80 | list_for_each(tmp, &server->pending_mid_q) { | 80 | list_for_each(tmp, &server->pending_mid_q) { |
| 81 | mid_entry = list_entry(tmp, struct mid_q_entry, qhead); | 81 | mid_entry = list_entry(tmp, struct mid_q_entry, qhead); |
| 82 | if (mid_entry) { | 82 | cERROR(1, ("State: %d Cmd: %d Pid: %d Tsk: %p Mid %d", |
| 83 | cERROR(1, ("State: %d Cmd: %d Pid: %d Tsk: %p Mid %d", | 83 | mid_entry->midState, |
| 84 | mid_entry->midState, | 84 | (int)mid_entry->command, |
| 85 | (int)mid_entry->command, | 85 | mid_entry->pid, |
| 86 | mid_entry->pid, | 86 | mid_entry->tsk, |
| 87 | mid_entry->tsk, | 87 | mid_entry->mid)); |
| 88 | mid_entry->mid)); | ||
| 89 | #ifdef CONFIG_CIFS_STATS2 | 88 | #ifdef CONFIG_CIFS_STATS2 |
| 90 | cERROR(1, ("IsLarge: %d buf: %p time rcv: %ld now: %ld", | 89 | cERROR(1, ("IsLarge: %d buf: %p time rcv: %ld now: %ld", |
| 91 | mid_entry->largeBuf, | 90 | mid_entry->largeBuf, |
| 92 | mid_entry->resp_buf, | 91 | mid_entry->resp_buf, |
| 93 | mid_entry->when_received, | 92 | mid_entry->when_received, |
| 94 | jiffies)); | 93 | jiffies)); |
| 95 | #endif /* STATS2 */ | 94 | #endif /* STATS2 */ |
| 96 | cERROR(1, ("IsMult: %d IsEnd: %d", mid_entry->multiRsp, | 95 | cERROR(1, ("IsMult: %d IsEnd: %d", mid_entry->multiRsp, |
| 97 | mid_entry->multiEnd)); | 96 | mid_entry->multiEnd)); |
| 98 | if (mid_entry->resp_buf) { | 97 | if (mid_entry->resp_buf) { |
| 99 | cifs_dump_detail(mid_entry->resp_buf); | 98 | cifs_dump_detail(mid_entry->resp_buf); |
| 100 | cifs_dump_mem("existing buf: ", | 99 | cifs_dump_mem("existing buf: ", |
| 101 | mid_entry->resp_buf, 62); | 100 | mid_entry->resp_buf, 62); |
| 102 | } | ||
| 103 | } | 101 | } |
| 104 | } | 102 | } |
| 105 | spin_unlock(&GlobalMid_Lock); | 103 | spin_unlock(&GlobalMid_Lock); |
| @@ -163,16 +161,13 @@ static int cifs_debug_data_proc_show(struct seq_file *m, void *v) | |||
| 163 | mid_entry = list_entry(tmp1, struct | 161 | mid_entry = list_entry(tmp1, struct |
| 164 | mid_q_entry, | 162 | mid_q_entry, |
| 165 | qhead); | 163 | qhead); |
| 166 | if (mid_entry) { | 164 | seq_printf(m, "State: %d com: %d pid:" |
| 167 | seq_printf(m, | 165 | " %d tsk: %p mid %d\n", |
| 168 | "State: %d com: %d pid:" | 166 | mid_entry->midState, |
| 169 | " %d tsk: %p mid %d\n", | 167 | (int)mid_entry->command, |
| 170 | mid_entry->midState, | 168 | mid_entry->pid, |
| 171 | (int)mid_entry->command, | 169 | mid_entry->tsk, |
| 172 | mid_entry->pid, | 170 | mid_entry->mid); |
| 173 | mid_entry->tsk, | ||
| 174 | mid_entry->mid); | ||
| 175 | } | ||
| 176 | } | 171 | } |
| 177 | spin_unlock(&GlobalMid_Lock); | 172 | spin_unlock(&GlobalMid_Lock); |
| 178 | } | 173 | } |
diff --git a/fs/cifs/cifs_spnego.c b/fs/cifs/cifs_spnego.c index 7013aaff6aed..2434ab0e8791 100644 --- a/fs/cifs/cifs_spnego.c +++ b/fs/cifs/cifs_spnego.c | |||
| @@ -66,8 +66,8 @@ struct key_type cifs_spnego_key_type = { | |||
| 66 | .describe = user_describe, | 66 | .describe = user_describe, |
| 67 | }; | 67 | }; |
| 68 | 68 | ||
| 69 | #define MAX_VER_STR_LEN 9 /* length of longest version string e.g. | 69 | #define MAX_VER_STR_LEN 8 /* length of longest version string e.g. |
| 70 | strlen(";ver=0xFF") */ | 70 | strlen("ver=0xFF") */ |
| 71 | #define MAX_MECH_STR_LEN 13 /* length of longest security mechanism name, eg | 71 | #define MAX_MECH_STR_LEN 13 /* length of longest security mechanism name, eg |
| 72 | in future could have strlen(";sec=ntlmsspi") */ | 72 | in future could have strlen(";sec=ntlmsspi") */ |
| 73 | #define MAX_IPV6_ADDR_LEN 42 /* eg FEDC:BA98:7654:3210:FEDC:BA98:7654:3210/60 */ | 73 | #define MAX_IPV6_ADDR_LEN 42 /* eg FEDC:BA98:7654:3210:FEDC:BA98:7654:3210/60 */ |
| @@ -81,11 +81,15 @@ cifs_get_spnego_key(struct cifsSesInfo *sesInfo) | |||
| 81 | struct key *spnego_key; | 81 | struct key *spnego_key; |
| 82 | const char *hostname = server->hostname; | 82 | const char *hostname = server->hostname; |
| 83 | 83 | ||
| 84 | /* BB: come up with better scheme for determining length */ | 84 | /* length of fields (with semicolons): ver=0xyz ip4=ipaddress |
| 85 | /* length of fields (with semicolons): ver=0xyz ipv4= ipaddress host= | 85 | host=hostname sec=mechanism uid=0xFF user=username */ |
| 86 | hostname sec=mechanism uid=0x uid */ | 86 | desc_len = MAX_VER_STR_LEN + |
| 87 | desc_len = MAX_VER_STR_LEN + 5 + MAX_IPV6_ADDR_LEN + 1 + 6 + | 87 | 6 /* len of "host=" */ + strlen(hostname) + |
| 88 | strlen(hostname) + MAX_MECH_STR_LEN + 8 + (sizeof(uid_t) * 2); | 88 | 5 /* len of ";ipv4=" */ + MAX_IPV6_ADDR_LEN + |
| 89 | MAX_MECH_STR_LEN + | ||
| 90 | 7 /* len of ";uid=0x" */ + (sizeof(uid_t) * 2) + | ||
| 91 | 6 /* len of ";user=" */ + strlen(sesInfo->userName) + 1; | ||
| 92 | |||
| 89 | spnego_key = ERR_PTR(-ENOMEM); | 93 | spnego_key = ERR_PTR(-ENOMEM); |
| 90 | description = kzalloc(desc_len, GFP_KERNEL); | 94 | description = kzalloc(desc_len, GFP_KERNEL); |
| 91 | if (description == NULL) | 95 | if (description == NULL) |
diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 1ec7076f7b24..e8da4ee761b5 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c | |||
| @@ -930,36 +930,34 @@ static int cifs_oplock_thread(void *dummyarg) | |||
| 930 | schedule_timeout(39*HZ); | 930 | schedule_timeout(39*HZ); |
| 931 | } else { | 931 | } else { |
| 932 | oplock_item = list_entry(GlobalOplock_Q.next, | 932 | oplock_item = list_entry(GlobalOplock_Q.next, |
| 933 | struct oplock_q_entry, qhead); | 933 | struct oplock_q_entry, qhead); |
| 934 | if (oplock_item) { | 934 | cFYI(1, ("found oplock item to write out")); |
| 935 | cFYI(1, ("found oplock item to write out")); | 935 | pTcon = oplock_item->tcon; |
| 936 | pTcon = oplock_item->tcon; | 936 | inode = oplock_item->pinode; |
| 937 | inode = oplock_item->pinode; | 937 | netfid = oplock_item->netfid; |
| 938 | netfid = oplock_item->netfid; | 938 | spin_unlock(&GlobalMid_Lock); |
| 939 | spin_unlock(&GlobalMid_Lock); | 939 | DeleteOplockQEntry(oplock_item); |
| 940 | DeleteOplockQEntry(oplock_item); | 940 | /* can not grab inode sem here since it would |
| 941 | /* can not grab inode sem here since it would | ||
| 942 | deadlock when oplock received on delete | 941 | deadlock when oplock received on delete |
| 943 | since vfs_unlink holds the i_mutex across | 942 | since vfs_unlink holds the i_mutex across |
| 944 | the call */ | 943 | the call */ |
| 945 | /* mutex_lock(&inode->i_mutex);*/ | 944 | /* mutex_lock(&inode->i_mutex);*/ |
| 946 | if (S_ISREG(inode->i_mode)) { | 945 | if (S_ISREG(inode->i_mode)) { |
| 947 | rc = | 946 | rc = filemap_fdatawrite(inode->i_mapping); |
| 948 | filemap_fdatawrite(inode->i_mapping); | 947 | if (CIFS_I(inode)->clientCanCacheRead == 0) { |
| 949 | if (CIFS_I(inode)->clientCanCacheRead | 948 | waitrc = filemap_fdatawait( |
| 950 | == 0) { | 949 | inode->i_mapping); |
| 951 | waitrc = filemap_fdatawait(inode->i_mapping); | 950 | invalidate_remote_inode(inode); |
| 952 | invalidate_remote_inode(inode); | 951 | } |
| 953 | } | 952 | if (rc == 0) |
| 954 | if (rc == 0) | 953 | rc = waitrc; |
| 955 | rc = waitrc; | 954 | } else |
| 956 | } else | 955 | rc = 0; |
| 957 | rc = 0; | 956 | /* mutex_unlock(&inode->i_mutex);*/ |
| 958 | /* mutex_unlock(&inode->i_mutex);*/ | 957 | if (rc) |
| 959 | if (rc) | 958 | CIFS_I(inode)->write_behind_rc = rc; |
| 960 | CIFS_I(inode)->write_behind_rc = rc; | 959 | cFYI(1, ("Oplock flush inode %p rc %d", |
| 961 | cFYI(1, ("Oplock flush inode %p rc %d", | 960 | inode, rc)); |
| 962 | inode, rc)); | ||
| 963 | 961 | ||
| 964 | /* releasing stale oplock after recent reconnect | 962 | /* releasing stale oplock after recent reconnect |
| 965 | of smb session using a now incorrect file | 963 | of smb session using a now incorrect file |
| @@ -967,15 +965,13 @@ static int cifs_oplock_thread(void *dummyarg) | |||
| 967 | not bother sending an oplock release if session | 965 | not bother sending an oplock release if session |
| 968 | to server still is disconnected since oplock | 966 | to server still is disconnected since oplock |
| 969 | already released by the server in that case */ | 967 | already released by the server in that case */ |
| 970 | if (pTcon->tidStatus != CifsNeedReconnect) { | 968 | if (pTcon->tidStatus != CifsNeedReconnect) { |
| 971 | rc = CIFSSMBLock(0, pTcon, netfid, | 969 | rc = CIFSSMBLock(0, pTcon, netfid, |
| 972 | 0 /* len */ , 0 /* offset */, 0, | 970 | 0 /* len */ , 0 /* offset */, 0, |
| 973 | 0, LOCKING_ANDX_OPLOCK_RELEASE, | 971 | 0, LOCKING_ANDX_OPLOCK_RELEASE, |
| 974 | false /* wait flag */); | 972 | false /* wait flag */); |
| 975 | cFYI(1, ("Oplock release rc = %d", rc)); | 973 | cFYI(1, ("Oplock release rc = %d", rc)); |
| 976 | } | 974 | } |
| 977 | } else | ||
| 978 | spin_unlock(&GlobalMid_Lock); | ||
| 979 | set_current_state(TASK_INTERRUPTIBLE); | 975 | set_current_state(TASK_INTERRUPTIBLE); |
| 980 | schedule_timeout(1); /* yield in case q were corrupt */ | 976 | schedule_timeout(1); /* yield in case q were corrupt */ |
| 981 | } | 977 | } |
| @@ -1001,8 +997,7 @@ static int cifs_dnotify_thread(void *dummyarg) | |||
| 1001 | list_for_each(tmp, &GlobalSMBSessionList) { | 997 | list_for_each(tmp, &GlobalSMBSessionList) { |
| 1002 | ses = list_entry(tmp, struct cifsSesInfo, | 998 | ses = list_entry(tmp, struct cifsSesInfo, |
| 1003 | cifsSessionList); | 999 | cifsSessionList); |
| 1004 | if (ses && ses->server && | 1000 | if (ses->server && atomic_read(&ses->server->inFlight)) |
| 1005 | atomic_read(&ses->server->inFlight)) | ||
| 1006 | wake_up_all(&ses->server->response_q); | 1001 | wake_up_all(&ses->server->response_q); |
| 1007 | } | 1002 | } |
| 1008 | read_unlock(&GlobalSMBSeslock); | 1003 | read_unlock(&GlobalSMBSeslock); |
diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index 25a6cbd15529..135c965c4137 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h | |||
| @@ -101,5 +101,5 @@ extern long cifs_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); | |||
| 101 | extern const struct export_operations cifs_export_ops; | 101 | extern const struct export_operations cifs_export_ops; |
| 102 | #endif /* EXPERIMENTAL */ | 102 | #endif /* EXPERIMENTAL */ |
| 103 | 103 | ||
| 104 | #define CIFS_VERSION "1.53" | 104 | #define CIFS_VERSION "1.54" |
| 105 | #endif /* _CIFSFS_H */ | 105 | #endif /* _CIFSFS_H */ |
diff --git a/fs/cifs/cifspdu.h b/fs/cifs/cifspdu.h index 409abce12732..d2a073edd1b8 100644 --- a/fs/cifs/cifspdu.h +++ b/fs/cifs/cifspdu.h | |||
| @@ -262,7 +262,7 @@ | |||
| 262 | */ | 262 | */ |
| 263 | #define CIFS_NO_HANDLE 0xFFFF | 263 | #define CIFS_NO_HANDLE 0xFFFF |
| 264 | 264 | ||
| 265 | #define NO_CHANGE_64 cpu_to_le64(0xFFFFFFFFFFFFFFFFULL) | 265 | #define NO_CHANGE_64 0xFFFFFFFFFFFFFFFFULL |
| 266 | #define NO_CHANGE_32 0xFFFFFFFFUL | 266 | #define NO_CHANGE_32 0xFFFFFFFFUL |
| 267 | 267 | ||
| 268 | /* IPC$ in ASCII */ | 268 | /* IPC$ in ASCII */ |
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h index b9f5e935f821..a729d083e6f4 100644 --- a/fs/cifs/cifsproto.h +++ b/fs/cifs/cifsproto.h | |||
| @@ -172,12 +172,13 @@ extern int CIFSSMBQFSUnixInfo(const int xid, struct cifsTconInfo *tcon); | |||
| 172 | extern int CIFSSMBQFSPosixInfo(const int xid, struct cifsTconInfo *tcon, | 172 | extern int CIFSSMBQFSPosixInfo(const int xid, struct cifsTconInfo *tcon, |
| 173 | struct kstatfs *FSData); | 173 | struct kstatfs *FSData); |
| 174 | 174 | ||
| 175 | extern int CIFSSMBSetTimes(const int xid, struct cifsTconInfo *tcon, | 175 | extern int CIFSSMBSetPathInfo(const int xid, struct cifsTconInfo *tcon, |
| 176 | const char *fileName, const FILE_BASIC_INFO *data, | 176 | const char *fileName, const FILE_BASIC_INFO *data, |
| 177 | const struct nls_table *nls_codepage, | 177 | const struct nls_table *nls_codepage, |
| 178 | int remap_special_chars); | 178 | int remap_special_chars); |
| 179 | extern int CIFSSMBSetFileTimes(const int xid, struct cifsTconInfo *tcon, | 179 | extern int CIFSSMBSetFileInfo(const int xid, struct cifsTconInfo *tcon, |
| 180 | const FILE_BASIC_INFO *data, __u16 fid); | 180 | const FILE_BASIC_INFO *data, __u16 fid, |
| 181 | __u32 pid_of_opener); | ||
| 181 | #if 0 | 182 | #if 0 |
| 182 | extern int CIFSSMBSetAttrLegacy(int xid, struct cifsTconInfo *tcon, | 183 | extern int CIFSSMBSetAttrLegacy(int xid, struct cifsTconInfo *tcon, |
| 183 | char *fileName, __u16 dos_attributes, | 184 | char *fileName, __u16 dos_attributes, |
| @@ -191,9 +192,20 @@ extern int CIFSSMBSetEOF(const int xid, struct cifsTconInfo *tcon, | |||
| 191 | extern int CIFSSMBSetFileSize(const int xid, struct cifsTconInfo *tcon, | 192 | extern int CIFSSMBSetFileSize(const int xid, struct cifsTconInfo *tcon, |
| 192 | __u64 size, __u16 fileHandle, __u32 opener_pid, | 193 | __u64 size, __u16 fileHandle, __u32 opener_pid, |
| 193 | bool AllocSizeFlag); | 194 | bool AllocSizeFlag); |
| 194 | extern int CIFSSMBUnixSetPerms(const int xid, struct cifsTconInfo *pTcon, | 195 | |
| 195 | char *full_path, __u64 mode, __u64 uid, | 196 | struct cifs_unix_set_info_args { |
| 196 | __u64 gid, dev_t dev, | 197 | __u64 ctime; |
| 198 | __u64 atime; | ||
| 199 | __u64 mtime; | ||
| 200 | __u64 mode; | ||
| 201 | __u64 uid; | ||
| 202 | __u64 gid; | ||
| 203 | dev_t device; | ||
| 204 | }; | ||
| 205 | |||
| 206 | extern int CIFSSMBUnixSetInfo(const int xid, struct cifsTconInfo *pTcon, | ||
| 207 | char *fileName, | ||
| 208 | const struct cifs_unix_set_info_args *args, | ||
| 197 | const struct nls_table *nls_codepage, | 209 | const struct nls_table *nls_codepage, |
| 198 | int remap_special_chars); | 210 | int remap_special_chars); |
| 199 | 211 | ||
diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c index c621ffa2ca90..994de7c90474 100644 --- a/fs/cifs/cifssmb.c +++ b/fs/cifs/cifssmb.c | |||
| @@ -128,8 +128,7 @@ static void mark_open_files_invalid(struct cifsTconInfo *pTcon) | |||
| 128 | write_lock(&GlobalSMBSeslock); | 128 | write_lock(&GlobalSMBSeslock); |
| 129 | list_for_each_safe(tmp, tmp1, &pTcon->openFileList) { | 129 | list_for_each_safe(tmp, tmp1, &pTcon->openFileList) { |
| 130 | open_file = list_entry(tmp, struct cifsFileInfo, tlist); | 130 | open_file = list_entry(tmp, struct cifsFileInfo, tlist); |
| 131 | if (open_file) | 131 | open_file->invalidHandle = true; |
| 132 | open_file->invalidHandle = true; | ||
| 133 | } | 132 | } |
| 134 | write_unlock(&GlobalSMBSeslock); | 133 | write_unlock(&GlobalSMBSeslock); |
| 135 | /* BB Add call to invalidate_inodes(sb) for all superblocks mounted | 134 | /* BB Add call to invalidate_inodes(sb) for all superblocks mounted |
| @@ -4816,8 +4815,8 @@ CIFSSMBSetFileSize(const int xid, struct cifsTconInfo *tcon, __u64 size, | |||
| 4816 | time and resort to the original setpathinfo level which takes the ancient | 4815 | time and resort to the original setpathinfo level which takes the ancient |
| 4817 | DOS time format with 2 second granularity */ | 4816 | DOS time format with 2 second granularity */ |
| 4818 | int | 4817 | int |
| 4819 | CIFSSMBSetFileTimes(const int xid, struct cifsTconInfo *tcon, | 4818 | CIFSSMBSetFileInfo(const int xid, struct cifsTconInfo *tcon, |
| 4820 | const FILE_BASIC_INFO *data, __u16 fid) | 4819 | const FILE_BASIC_INFO *data, __u16 fid, __u32 pid_of_opener) |
| 4821 | { | 4820 | { |
| 4822 | struct smb_com_transaction2_sfi_req *pSMB = NULL; | 4821 | struct smb_com_transaction2_sfi_req *pSMB = NULL; |
| 4823 | char *data_offset; | 4822 | char *data_offset; |
| @@ -4830,11 +4829,8 @@ CIFSSMBSetFileTimes(const int xid, struct cifsTconInfo *tcon, | |||
| 4830 | if (rc) | 4829 | if (rc) |
| 4831 | return rc; | 4830 | return rc; |
| 4832 | 4831 | ||
| 4833 | /* At this point there is no need to override the current pid | 4832 | pSMB->hdr.Pid = cpu_to_le16((__u16)pid_of_opener); |
| 4834 | with the pid of the opener, but that could change if we someday | 4833 | pSMB->hdr.PidHigh = cpu_to_le16((__u16)(pid_of_opener >> 16)); |
| 4835 | use an existing handle (rather than opening one on the fly) */ | ||
| 4836 | /* pSMB->hdr.Pid = cpu_to_le16((__u16)pid_of_opener); | ||
| 4837 | pSMB->hdr.PidHigh = cpu_to_le16((__u16)(pid_of_opener >> 16));*/ | ||
| 4838 | 4834 | ||
| 4839 | params = 6; | 4835 | params = 6; |
| 4840 | pSMB->MaxSetupCount = 0; | 4836 | pSMB->MaxSetupCount = 0; |
| @@ -4882,9 +4878,9 @@ CIFSSMBSetFileTimes(const int xid, struct cifsTconInfo *tcon, | |||
| 4882 | 4878 | ||
| 4883 | 4879 | ||
| 4884 | int | 4880 | int |
| 4885 | CIFSSMBSetTimes(const int xid, struct cifsTconInfo *tcon, const char *fileName, | 4881 | CIFSSMBSetPathInfo(const int xid, struct cifsTconInfo *tcon, |
| 4886 | const FILE_BASIC_INFO *data, | 4882 | const char *fileName, const FILE_BASIC_INFO *data, |
| 4887 | const struct nls_table *nls_codepage, int remap) | 4883 | const struct nls_table *nls_codepage, int remap) |
| 4888 | { | 4884 | { |
| 4889 | TRANSACTION2_SPI_REQ *pSMB = NULL; | 4885 | TRANSACTION2_SPI_REQ *pSMB = NULL; |
| 4890 | TRANSACTION2_SPI_RSP *pSMBr = NULL; | 4886 | TRANSACTION2_SPI_RSP *pSMBr = NULL; |
| @@ -5013,10 +5009,9 @@ SetAttrLgcyRetry: | |||
| 5013 | #endif /* temporarily unneeded SetAttr legacy function */ | 5009 | #endif /* temporarily unneeded SetAttr legacy function */ |
| 5014 | 5010 | ||
| 5015 | int | 5011 | int |
| 5016 | CIFSSMBUnixSetPerms(const int xid, struct cifsTconInfo *tcon, | 5012 | CIFSSMBUnixSetInfo(const int xid, struct cifsTconInfo *tcon, char *fileName, |
| 5017 | char *fileName, __u64 mode, __u64 uid, __u64 gid, | 5013 | const struct cifs_unix_set_info_args *args, |
| 5018 | dev_t device, const struct nls_table *nls_codepage, | 5014 | const struct nls_table *nls_codepage, int remap) |
| 5019 | int remap) | ||
| 5020 | { | 5015 | { |
| 5021 | TRANSACTION2_SPI_REQ *pSMB = NULL; | 5016 | TRANSACTION2_SPI_REQ *pSMB = NULL; |
| 5022 | TRANSACTION2_SPI_RSP *pSMBr = NULL; | 5017 | TRANSACTION2_SPI_RSP *pSMBr = NULL; |
| @@ -5025,6 +5020,7 @@ CIFSSMBUnixSetPerms(const int xid, struct cifsTconInfo *tcon, | |||
| 5025 | int bytes_returned = 0; | 5020 | int bytes_returned = 0; |
| 5026 | FILE_UNIX_BASIC_INFO *data_offset; | 5021 | FILE_UNIX_BASIC_INFO *data_offset; |
| 5027 | __u16 params, param_offset, offset, count, byte_count; | 5022 | __u16 params, param_offset, offset, count, byte_count; |
| 5023 | __u64 mode = args->mode; | ||
| 5028 | 5024 | ||
| 5029 | cFYI(1, ("In SetUID/GID/Mode")); | 5025 | cFYI(1, ("In SetUID/GID/Mode")); |
| 5030 | setPermsRetry: | 5026 | setPermsRetry: |
| @@ -5080,16 +5076,16 @@ setPermsRetry: | |||
| 5080 | set file size and do not want to truncate file size to zero | 5076 | set file size and do not want to truncate file size to zero |
| 5081 | accidently as happened on one Samba server beta by putting | 5077 | accidently as happened on one Samba server beta by putting |
| 5082 | zero instead of -1 here */ | 5078 | zero instead of -1 here */ |
| 5083 | data_offset->EndOfFile = NO_CHANGE_64; | 5079 | data_offset->EndOfFile = cpu_to_le64(NO_CHANGE_64); |
| 5084 | data_offset->NumOfBytes = NO_CHANGE_64; | 5080 | data_offset->NumOfBytes = cpu_to_le64(NO_CHANGE_64); |
| 5085 | data_offset->LastStatusChange = NO_CHANGE_64; | 5081 | data_offset->LastStatusChange = cpu_to_le64(args->ctime); |
| 5086 | data_offset->LastAccessTime = NO_CHANGE_64; | 5082 | data_offset->LastAccessTime = cpu_to_le64(args->atime); |
| 5087 | data_offset->LastModificationTime = NO_CHANGE_64; | 5083 | data_offset->LastModificationTime = cpu_to_le64(args->mtime); |
| 5088 | data_offset->Uid = cpu_to_le64(uid); | 5084 | data_offset->Uid = cpu_to_le64(args->uid); |
| 5089 | data_offset->Gid = cpu_to_le64(gid); | 5085 | data_offset->Gid = cpu_to_le64(args->gid); |
| 5090 | /* better to leave device as zero when it is */ | 5086 | /* better to leave device as zero when it is */ |
| 5091 | data_offset->DevMajor = cpu_to_le64(MAJOR(device)); | 5087 | data_offset->DevMajor = cpu_to_le64(MAJOR(args->device)); |
| 5092 | data_offset->DevMinor = cpu_to_le64(MINOR(device)); | 5088 | data_offset->DevMinor = cpu_to_le64(MINOR(args->device)); |
| 5093 | data_offset->Permissions = cpu_to_le64(mode); | 5089 | data_offset->Permissions = cpu_to_le64(mode); |
| 5094 | 5090 | ||
| 5095 | if (S_ISREG(mode)) | 5091 | if (S_ISREG(mode)) |
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c index b51d5777cde6..0711db65afe8 100644 --- a/fs/cifs/connect.c +++ b/fs/cifs/connect.c | |||
| @@ -151,7 +151,7 @@ cifs_reconnect(struct TCP_Server_Info *server) | |||
| 151 | } | 151 | } |
| 152 | list_for_each(tmp, &GlobalTreeConnectionList) { | 152 | list_for_each(tmp, &GlobalTreeConnectionList) { |
| 153 | tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); | 153 | tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); |
| 154 | if ((tcon) && (tcon->ses) && (tcon->ses->server == server)) | 154 | if ((tcon->ses) && (tcon->ses->server == server)) |
| 155 | tcon->tidStatus = CifsNeedReconnect; | 155 | tcon->tidStatus = CifsNeedReconnect; |
| 156 | } | 156 | } |
| 157 | read_unlock(&GlobalSMBSeslock); | 157 | read_unlock(&GlobalSMBSeslock); |
| @@ -173,14 +173,12 @@ cifs_reconnect(struct TCP_Server_Info *server) | |||
| 173 | mid_entry = list_entry(tmp, struct | 173 | mid_entry = list_entry(tmp, struct |
| 174 | mid_q_entry, | 174 | mid_q_entry, |
| 175 | qhead); | 175 | qhead); |
| 176 | if (mid_entry) { | 176 | if (mid_entry->midState == MID_REQUEST_SUBMITTED) { |
| 177 | if (mid_entry->midState == MID_REQUEST_SUBMITTED) { | ||
| 178 | /* Mark other intransit requests as needing | 177 | /* Mark other intransit requests as needing |
| 179 | retry so we do not immediately mark the | 178 | retry so we do not immediately mark the |
| 180 | session bad again (ie after we reconnect | 179 | session bad again (ie after we reconnect |
| 181 | below) as they timeout too */ | 180 | below) as they timeout too */ |
| 182 | mid_entry->midState = MID_RETRY_NEEDED; | 181 | mid_entry->midState = MID_RETRY_NEEDED; |
| 183 | } | ||
| 184 | } | 182 | } |
| 185 | } | 183 | } |
| 186 | spin_unlock(&GlobalMid_Lock); | 184 | spin_unlock(&GlobalMid_Lock); |
| @@ -351,11 +349,9 @@ cifs_demultiplex_thread(struct TCP_Server_Info *server) | |||
| 351 | 349 | ||
| 352 | current->flags |= PF_MEMALLOC; | 350 | current->flags |= PF_MEMALLOC; |
| 353 | cFYI(1, ("Demultiplex PID: %d", task_pid_nr(current))); | 351 | cFYI(1, ("Demultiplex PID: %d", task_pid_nr(current))); |
| 354 | write_lock(&GlobalSMBSeslock); | 352 | |
| 355 | atomic_inc(&tcpSesAllocCount); | 353 | length = atomic_inc_return(&tcpSesAllocCount); |
| 356 | length = tcpSesAllocCount.counter; | 354 | if (length > 1) |
| 357 | write_unlock(&GlobalSMBSeslock); | ||
| 358 | if (length > 1) | ||
| 359 | mempool_resize(cifs_req_poolp, length + cifs_min_rcv, | 355 | mempool_resize(cifs_req_poolp, length + cifs_min_rcv, |
| 360 | GFP_KERNEL); | 356 | GFP_KERNEL); |
| 361 | 357 | ||
| @@ -745,14 +741,11 @@ multi_t2_fnd: | |||
| 745 | coming home not much else we can do but free the memory */ | 741 | coming home not much else we can do but free the memory */ |
| 746 | } | 742 | } |
| 747 | 743 | ||
| 748 | write_lock(&GlobalSMBSeslock); | ||
| 749 | atomic_dec(&tcpSesAllocCount); | ||
| 750 | length = tcpSesAllocCount.counter; | ||
| 751 | |||
| 752 | /* last chance to mark ses pointers invalid | 744 | /* last chance to mark ses pointers invalid |
| 753 | if there are any pointing to this (e.g | 745 | if there are any pointing to this (e.g |
| 754 | if a crazy root user tried to kill cifsd | 746 | if a crazy root user tried to kill cifsd |
| 755 | kernel thread explicitly this might happen) */ | 747 | kernel thread explicitly this might happen) */ |
| 748 | write_lock(&GlobalSMBSeslock); | ||
| 756 | list_for_each(tmp, &GlobalSMBSessionList) { | 749 | list_for_each(tmp, &GlobalSMBSessionList) { |
| 757 | ses = list_entry(tmp, struct cifsSesInfo, | 750 | ses = list_entry(tmp, struct cifsSesInfo, |
| 758 | cifsSessionList); | 751 | cifsSessionList); |
| @@ -763,6 +756,8 @@ multi_t2_fnd: | |||
| 763 | 756 | ||
| 764 | kfree(server->hostname); | 757 | kfree(server->hostname); |
| 765 | kfree(server); | 758 | kfree(server); |
| 759 | |||
| 760 | length = atomic_dec_return(&tcpSesAllocCount); | ||
| 766 | if (length > 0) | 761 | if (length > 0) |
| 767 | mempool_resize(cifs_req_poolp, length + cifs_min_rcv, | 762 | mempool_resize(cifs_req_poolp, length + cifs_min_rcv, |
| 768 | GFP_KERNEL); | 763 | GFP_KERNEL); |
| @@ -3623,97 +3618,91 @@ int cifs_setup_session(unsigned int xid, struct cifsSesInfo *pSesInfo, | |||
| 3623 | } | 3618 | } |
| 3624 | first_time = 1; | 3619 | first_time = 1; |
| 3625 | } | 3620 | } |
| 3626 | if (!rc) { | 3621 | |
| 3627 | pSesInfo->flags = 0; | 3622 | if (rc) |
| 3628 | pSesInfo->capabilities = pSesInfo->server->capabilities; | 3623 | goto ss_err_exit; |
| 3629 | if (linuxExtEnabled == 0) | 3624 | |
| 3630 | pSesInfo->capabilities &= (~CAP_UNIX); | 3625 | pSesInfo->flags = 0; |
| 3626 | pSesInfo->capabilities = pSesInfo->server->capabilities; | ||
| 3627 | if (linuxExtEnabled == 0) | ||
| 3628 | pSesInfo->capabilities &= (~CAP_UNIX); | ||
| 3631 | /* pSesInfo->sequence_number = 0;*/ | 3629 | /* pSesInfo->sequence_number = 0;*/ |
| 3632 | cFYI(1, | 3630 | cFYI(1, ("Security Mode: 0x%x Capabilities: 0x%x TimeAdjust: %d", |
| 3633 | ("Security Mode: 0x%x Capabilities: 0x%x TimeAdjust: %d", | 3631 | pSesInfo->server->secMode, |
| 3634 | pSesInfo->server->secMode, | 3632 | pSesInfo->server->capabilities, |
| 3635 | pSesInfo->server->capabilities, | 3633 | pSesInfo->server->timeAdj)); |
| 3636 | pSesInfo->server->timeAdj)); | 3634 | if (experimEnabled < 2) |
| 3637 | if (experimEnabled < 2) | 3635 | rc = CIFS_SessSetup(xid, pSesInfo, first_time, nls_info); |
| 3638 | rc = CIFS_SessSetup(xid, pSesInfo, | 3636 | else if (extended_security |
| 3639 | first_time, nls_info); | 3637 | && (pSesInfo->capabilities & CAP_EXTENDED_SECURITY) |
| 3640 | else if (extended_security | 3638 | && (pSesInfo->server->secType == NTLMSSP)) { |
| 3641 | && (pSesInfo->capabilities | 3639 | rc = -EOPNOTSUPP; |
| 3642 | & CAP_EXTENDED_SECURITY) | 3640 | } else if (extended_security |
| 3643 | && (pSesInfo->server->secType == NTLMSSP)) { | 3641 | && (pSesInfo->capabilities & CAP_EXTENDED_SECURITY) |
| 3644 | rc = -EOPNOTSUPP; | 3642 | && (pSesInfo->server->secType == RawNTLMSSP)) { |
| 3645 | } else if (extended_security | 3643 | cFYI(1, ("NTLMSSP sesssetup")); |
| 3646 | && (pSesInfo->capabilities & CAP_EXTENDED_SECURITY) | 3644 | rc = CIFSNTLMSSPNegotiateSessSetup(xid, pSesInfo, &ntlmv2_flag, |
| 3647 | && (pSesInfo->server->secType == RawNTLMSSP)) { | 3645 | nls_info); |
| 3648 | cFYI(1, ("NTLMSSP sesssetup")); | 3646 | if (!rc) { |
| 3649 | rc = CIFSNTLMSSPNegotiateSessSetup(xid, | 3647 | if (ntlmv2_flag) { |
| 3650 | pSesInfo, | 3648 | char *v2_response; |
| 3651 | &ntlmv2_flag, | 3649 | cFYI(1, ("more secure NTLM ver2 hash")); |
| 3652 | nls_info); | 3650 | if (CalcNTLMv2_partial_mac_key(pSesInfo, |
| 3653 | if (!rc) { | 3651 | nls_info)) { |
| 3654 | if (ntlmv2_flag) { | 3652 | rc = -ENOMEM; |
| 3655 | char *v2_response; | 3653 | goto ss_err_exit; |
| 3656 | cFYI(1, ("more secure NTLM ver2 hash")); | 3654 | } else |
| 3657 | if (CalcNTLMv2_partial_mac_key(pSesInfo, | 3655 | v2_response = kmalloc(16 + 64 /* blob*/, |
| 3658 | nls_info)) { | 3656 | GFP_KERNEL); |
| 3659 | rc = -ENOMEM; | 3657 | if (v2_response) { |
| 3660 | goto ss_err_exit; | 3658 | CalcNTLMv2_response(pSesInfo, |
| 3661 | } else | 3659 | v2_response); |
| 3662 | v2_response = kmalloc(16 + 64 /* blob */, GFP_KERNEL); | 3660 | /* if (first_time) |
| 3663 | if (v2_response) { | 3661 | cifs_calculate_ntlmv2_mac_key */ |
| 3664 | CalcNTLMv2_response(pSesInfo, | 3662 | kfree(v2_response); |
| 3665 | v2_response); | ||
| 3666 | /* if (first_time) | ||
| 3667 | cifs_calculate_ntlmv2_mac_key( | ||
| 3668 | pSesInfo->server->mac_signing_key, | ||
| 3669 | response, ntlm_session_key,*/ | ||
| 3670 | kfree(v2_response); | ||
| 3671 | /* BB Put dummy sig in SessSetup PDU? */ | 3663 | /* BB Put dummy sig in SessSetup PDU? */ |
| 3672 | } else { | ||
| 3673 | rc = -ENOMEM; | ||
| 3674 | goto ss_err_exit; | ||
| 3675 | } | ||
| 3676 | |||
| 3677 | } else { | 3664 | } else { |
| 3678 | SMBNTencrypt(pSesInfo->password, | 3665 | rc = -ENOMEM; |
| 3679 | pSesInfo->server->cryptKey, | 3666 | goto ss_err_exit; |
| 3680 | ntlm_session_key); | ||
| 3681 | |||
| 3682 | if (first_time) | ||
| 3683 | cifs_calculate_mac_key( | ||
| 3684 | &pSesInfo->server->mac_signing_key, | ||
| 3685 | ntlm_session_key, | ||
| 3686 | pSesInfo->password); | ||
| 3687 | } | 3667 | } |
| 3668 | |||
| 3669 | } else { | ||
| 3670 | SMBNTencrypt(pSesInfo->password, | ||
| 3671 | pSesInfo->server->cryptKey, | ||
| 3672 | ntlm_session_key); | ||
| 3673 | |||
| 3674 | if (first_time) | ||
| 3675 | cifs_calculate_mac_key( | ||
| 3676 | &pSesInfo->server->mac_signing_key, | ||
| 3677 | ntlm_session_key, | ||
| 3678 | pSesInfo->password); | ||
| 3679 | } | ||
| 3688 | /* for better security the weaker lanman hash not sent | 3680 | /* for better security the weaker lanman hash not sent |
| 3689 | in AuthSessSetup so we no longer calculate it */ | 3681 | in AuthSessSetup so we no longer calculate it */ |
| 3690 | 3682 | ||
| 3691 | rc = CIFSNTLMSSPAuthSessSetup(xid, | 3683 | rc = CIFSNTLMSSPAuthSessSetup(xid, pSesInfo, |
| 3692 | pSesInfo, | 3684 | ntlm_session_key, |
| 3693 | ntlm_session_key, | 3685 | ntlmv2_flag, |
| 3694 | ntlmv2_flag, | 3686 | nls_info); |
| 3695 | nls_info); | 3687 | } |
| 3696 | } | 3688 | } else { /* old style NTLM 0.12 session setup */ |
| 3697 | } else { /* old style NTLM 0.12 session setup */ | 3689 | SMBNTencrypt(pSesInfo->password, pSesInfo->server->cryptKey, |
| 3698 | SMBNTencrypt(pSesInfo->password, | 3690 | ntlm_session_key); |
| 3699 | pSesInfo->server->cryptKey, | ||
| 3700 | ntlm_session_key); | ||
| 3701 | 3691 | ||
| 3702 | if (first_time) | 3692 | if (first_time) |
| 3703 | cifs_calculate_mac_key( | 3693 | cifs_calculate_mac_key( |
| 3704 | &pSesInfo->server->mac_signing_key, | 3694 | &pSesInfo->server->mac_signing_key, |
| 3705 | ntlm_session_key, pSesInfo->password); | 3695 | ntlm_session_key, pSesInfo->password); |
| 3706 | 3696 | ||
| 3707 | rc = CIFSSessSetup(xid, pSesInfo, | 3697 | rc = CIFSSessSetup(xid, pSesInfo, ntlm_session_key, nls_info); |
| 3708 | ntlm_session_key, nls_info); | 3698 | } |
| 3709 | } | 3699 | if (rc) { |
| 3710 | if (rc) { | 3700 | cERROR(1, ("Send error in SessSetup = %d", rc)); |
| 3711 | cERROR(1, ("Send error in SessSetup = %d", rc)); | 3701 | } else { |
| 3712 | } else { | 3702 | cFYI(1, ("CIFS Session Established successfully")); |
| 3713 | cFYI(1, ("CIFS Session Established successfully")); | ||
| 3714 | pSesInfo->status = CifsGood; | 3703 | pSesInfo->status = CifsGood; |
| 3715 | } | ||
| 3716 | } | 3704 | } |
| 3705 | |||
| 3717 | ss_err_exit: | 3706 | ss_err_exit: |
| 3718 | return rc; | 3707 | return rc; |
| 3719 | } | 3708 | } |
diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c index fb69c1fa85c9..e962e75e6f7b 100644 --- a/fs/cifs/dir.c +++ b/fs/cifs/dir.c | |||
| @@ -226,23 +226,28 @@ cifs_create(struct inode *inode, struct dentry *direntry, int mode, | |||
| 226 | /* If Open reported that we actually created a file | 226 | /* If Open reported that we actually created a file |
| 227 | then we now have to set the mode if possible */ | 227 | then we now have to set the mode if possible */ |
| 228 | if ((pTcon->unix_ext) && (oplock & CIFS_CREATE_ACTION)) { | 228 | if ((pTcon->unix_ext) && (oplock & CIFS_CREATE_ACTION)) { |
| 229 | struct cifs_unix_set_info_args args = { | ||
| 230 | .mode = mode, | ||
| 231 | .ctime = NO_CHANGE_64, | ||
| 232 | .atime = NO_CHANGE_64, | ||
| 233 | .mtime = NO_CHANGE_64, | ||
| 234 | .device = 0, | ||
| 235 | }; | ||
| 236 | |||
| 229 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID) { | 237 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID) { |
| 230 | CIFSSMBUnixSetPerms(xid, pTcon, full_path, mode, | 238 | args.uid = (__u64) current->fsuid; |
| 231 | (__u64)current->fsuid, | 239 | if (inode->i_mode & S_ISGID) |
| 232 | (__u64)current->fsgid, | 240 | args.gid = (__u64) inode->i_gid; |
| 233 | 0 /* dev */, | 241 | else |
| 234 | cifs_sb->local_nls, | 242 | args.gid = (__u64) current->fsgid; |
| 235 | cifs_sb->mnt_cifs_flags & | ||
| 236 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 237 | } else { | 243 | } else { |
| 238 | CIFSSMBUnixSetPerms(xid, pTcon, full_path, mode, | 244 | args.uid = NO_CHANGE_64; |
| 239 | (__u64)-1, | 245 | args.gid = NO_CHANGE_64; |
| 240 | (__u64)-1, | ||
| 241 | 0 /* dev */, | ||
| 242 | cifs_sb->local_nls, | ||
| 243 | cifs_sb->mnt_cifs_flags & | ||
| 244 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 245 | } | 246 | } |
| 247 | CIFSSMBUnixSetInfo(xid, pTcon, full_path, &args, | ||
| 248 | cifs_sb->local_nls, | ||
| 249 | cifs_sb->mnt_cifs_flags & | ||
| 250 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 246 | } else { | 251 | } else { |
| 247 | /* BB implement mode setting via Windows security | 252 | /* BB implement mode setting via Windows security |
| 248 | descriptors e.g. */ | 253 | descriptors e.g. */ |
| @@ -267,7 +272,12 @@ cifs_create(struct inode *inode, struct dentry *direntry, int mode, | |||
| 267 | (cifs_sb->mnt_cifs_flags & | 272 | (cifs_sb->mnt_cifs_flags & |
| 268 | CIFS_MOUNT_SET_UID)) { | 273 | CIFS_MOUNT_SET_UID)) { |
| 269 | newinode->i_uid = current->fsuid; | 274 | newinode->i_uid = current->fsuid; |
| 270 | newinode->i_gid = current->fsgid; | 275 | if (inode->i_mode & S_ISGID) |
| 276 | newinode->i_gid = | ||
| 277 | inode->i_gid; | ||
| 278 | else | ||
| 279 | newinode->i_gid = | ||
| 280 | current->fsgid; | ||
| 271 | } | 281 | } |
| 272 | } | 282 | } |
| 273 | } | 283 | } |
| @@ -357,21 +367,24 @@ int cifs_mknod(struct inode *inode, struct dentry *direntry, int mode, | |||
| 357 | if (full_path == NULL) | 367 | if (full_path == NULL) |
| 358 | rc = -ENOMEM; | 368 | rc = -ENOMEM; |
| 359 | else if (pTcon->unix_ext) { | 369 | else if (pTcon->unix_ext) { |
| 360 | mode &= ~current->fs->umask; | 370 | struct cifs_unix_set_info_args args = { |
| 371 | .mode = mode & ~current->fs->umask, | ||
| 372 | .ctime = NO_CHANGE_64, | ||
| 373 | .atime = NO_CHANGE_64, | ||
| 374 | .mtime = NO_CHANGE_64, | ||
| 375 | .device = device_number, | ||
| 376 | }; | ||
| 361 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID) { | 377 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID) { |
| 362 | rc = CIFSSMBUnixSetPerms(xid, pTcon, full_path, | 378 | args.uid = (__u64) current->fsuid; |
| 363 | mode, (__u64)current->fsuid, | 379 | args.gid = (__u64) current->fsgid; |
| 364 | (__u64)current->fsgid, | ||
| 365 | device_number, cifs_sb->local_nls, | ||
| 366 | cifs_sb->mnt_cifs_flags & | ||
| 367 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 368 | } else { | 380 | } else { |
| 369 | rc = CIFSSMBUnixSetPerms(xid, pTcon, | 381 | args.uid = NO_CHANGE_64; |
| 370 | full_path, mode, (__u64)-1, (__u64)-1, | 382 | args.gid = NO_CHANGE_64; |
| 371 | device_number, cifs_sb->local_nls, | ||
| 372 | cifs_sb->mnt_cifs_flags & | ||
| 373 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 374 | } | 383 | } |
| 384 | rc = CIFSSMBUnixSetInfo(xid, pTcon, full_path, | ||
| 385 | &args, cifs_sb->local_nls, | ||
| 386 | cifs_sb->mnt_cifs_flags & | ||
| 387 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 375 | 388 | ||
| 376 | if (!rc) { | 389 | if (!rc) { |
| 377 | rc = cifs_get_inode_info_unix(&newinode, full_path, | 390 | rc = cifs_get_inode_info_unix(&newinode, full_path, |
diff --git a/fs/cifs/file.c b/fs/cifs/file.c index e692c42f24b5..ff14d14903a0 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c | |||
| @@ -310,18 +310,19 @@ int cifs_open(struct inode *inode, struct file *file) | |||
| 310 | /* time to set mode which we can not set earlier due to | 310 | /* time to set mode which we can not set earlier due to |
| 311 | problems creating new read-only files */ | 311 | problems creating new read-only files */ |
| 312 | if (pTcon->unix_ext) { | 312 | if (pTcon->unix_ext) { |
| 313 | CIFSSMBUnixSetPerms(xid, pTcon, full_path, | 313 | struct cifs_unix_set_info_args args = { |
| 314 | inode->i_mode, | 314 | .mode = inode->i_mode, |
| 315 | (__u64)-1, (__u64)-1, 0 /* dev */, | 315 | .uid = NO_CHANGE_64, |
| 316 | .gid = NO_CHANGE_64, | ||
| 317 | .ctime = NO_CHANGE_64, | ||
| 318 | .atime = NO_CHANGE_64, | ||
| 319 | .mtime = NO_CHANGE_64, | ||
| 320 | .device = 0, | ||
| 321 | }; | ||
| 322 | CIFSSMBUnixSetInfo(xid, pTcon, full_path, &args, | ||
| 316 | cifs_sb->local_nls, | 323 | cifs_sb->local_nls, |
| 317 | cifs_sb->mnt_cifs_flags & | 324 | cifs_sb->mnt_cifs_flags & |
| 318 | CIFS_MOUNT_MAP_SPECIAL_CHR); | 325 | CIFS_MOUNT_MAP_SPECIAL_CHR); |
| 319 | } else { | ||
| 320 | /* BB implement via Windows security descriptors eg | ||
| 321 | CIFSSMBWinSetPerms(xid, pTcon, full_path, mode, | ||
| 322 | -1, -1, local_nls); | ||
| 323 | in the meantime could set r/o dos attribute when | ||
| 324 | perms are eg: mode & 0222 == 0 */ | ||
| 325 | } | 326 | } |
| 326 | } | 327 | } |
| 327 | 328 | ||
diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index 46e54d39461d..28a22092d450 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c | |||
| @@ -737,7 +737,7 @@ psx_del_no_retry: | |||
| 737 | /* ATTRS set to normal clears r/o bit */ | 737 | /* ATTRS set to normal clears r/o bit */ |
| 738 | pinfo_buf->Attributes = cpu_to_le32(ATTR_NORMAL); | 738 | pinfo_buf->Attributes = cpu_to_le32(ATTR_NORMAL); |
| 739 | if (!(pTcon->ses->flags & CIFS_SES_NT4)) | 739 | if (!(pTcon->ses->flags & CIFS_SES_NT4)) |
| 740 | rc = CIFSSMBSetTimes(xid, pTcon, full_path, | 740 | rc = CIFSSMBSetPathInfo(xid, pTcon, full_path, |
| 741 | pinfo_buf, | 741 | pinfo_buf, |
| 742 | cifs_sb->local_nls, | 742 | cifs_sb->local_nls, |
| 743 | cifs_sb->mnt_cifs_flags & | 743 | cifs_sb->mnt_cifs_flags & |
| @@ -767,9 +767,10 @@ psx_del_no_retry: | |||
| 767 | cifs_sb->mnt_cifs_flags & | 767 | cifs_sb->mnt_cifs_flags & |
| 768 | CIFS_MOUNT_MAP_SPECIAL_CHR); | 768 | CIFS_MOUNT_MAP_SPECIAL_CHR); |
| 769 | if (rc == 0) { | 769 | if (rc == 0) { |
| 770 | rc = CIFSSMBSetFileTimes(xid, pTcon, | 770 | rc = CIFSSMBSetFileInfo(xid, pTcon, |
| 771 | pinfo_buf, | 771 | pinfo_buf, |
| 772 | netfid); | 772 | netfid, |
| 773 | current->tgid); | ||
| 773 | CIFSSMBClose(xid, pTcon, netfid); | 774 | CIFSSMBClose(xid, pTcon, netfid); |
| 774 | } | 775 | } |
| 775 | } | 776 | } |
| @@ -984,32 +985,41 @@ mkdir_get_info: | |||
| 984 | * failed to get it from the server or was set bogus */ | 985 | * failed to get it from the server or was set bogus */ |
| 985 | if ((direntry->d_inode) && (direntry->d_inode->i_nlink < 2)) | 986 | if ((direntry->d_inode) && (direntry->d_inode->i_nlink < 2)) |
| 986 | direntry->d_inode->i_nlink = 2; | 987 | direntry->d_inode->i_nlink = 2; |
| 988 | |||
| 987 | mode &= ~current->fs->umask; | 989 | mode &= ~current->fs->umask; |
| 990 | /* must turn on setgid bit if parent dir has it */ | ||
| 991 | if (inode->i_mode & S_ISGID) | ||
| 992 | mode |= S_ISGID; | ||
| 993 | |||
| 988 | if (pTcon->unix_ext) { | 994 | if (pTcon->unix_ext) { |
| 995 | struct cifs_unix_set_info_args args = { | ||
| 996 | .mode = mode, | ||
| 997 | .ctime = NO_CHANGE_64, | ||
| 998 | .atime = NO_CHANGE_64, | ||
| 999 | .mtime = NO_CHANGE_64, | ||
| 1000 | .device = 0, | ||
| 1001 | }; | ||
| 989 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID) { | 1002 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID) { |
| 990 | CIFSSMBUnixSetPerms(xid, pTcon, full_path, | 1003 | args.uid = (__u64)current->fsuid; |
| 991 | mode, | 1004 | if (inode->i_mode & S_ISGID) |
| 992 | (__u64)current->fsuid, | 1005 | args.gid = (__u64)inode->i_gid; |
| 993 | (__u64)current->fsgid, | 1006 | else |
| 994 | 0 /* dev_t */, | 1007 | args.gid = (__u64)current->fsgid; |
| 995 | cifs_sb->local_nls, | ||
| 996 | cifs_sb->mnt_cifs_flags & | ||
| 997 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 998 | } else { | 1008 | } else { |
| 999 | CIFSSMBUnixSetPerms(xid, pTcon, full_path, | 1009 | args.uid = NO_CHANGE_64; |
| 1000 | mode, (__u64)-1, | 1010 | args.gid = NO_CHANGE_64; |
| 1001 | (__u64)-1, 0 /* dev_t */, | ||
| 1002 | cifs_sb->local_nls, | ||
| 1003 | cifs_sb->mnt_cifs_flags & | ||
| 1004 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1005 | } | 1011 | } |
| 1012 | CIFSSMBUnixSetInfo(xid, pTcon, full_path, &args, | ||
| 1013 | cifs_sb->local_nls, | ||
| 1014 | cifs_sb->mnt_cifs_flags & | ||
| 1015 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1006 | } else { | 1016 | } else { |
| 1007 | if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_CIFS_ACL) && | 1017 | if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_CIFS_ACL) && |
| 1008 | (mode & S_IWUGO) == 0) { | 1018 | (mode & S_IWUGO) == 0) { |
| 1009 | FILE_BASIC_INFO pInfo; | 1019 | FILE_BASIC_INFO pInfo; |
| 1010 | memset(&pInfo, 0, sizeof(pInfo)); | 1020 | memset(&pInfo, 0, sizeof(pInfo)); |
| 1011 | pInfo.Attributes = cpu_to_le32(ATTR_READONLY); | 1021 | pInfo.Attributes = cpu_to_le32(ATTR_READONLY); |
| 1012 | CIFSSMBSetTimes(xid, pTcon, full_path, | 1022 | CIFSSMBSetPathInfo(xid, pTcon, full_path, |
| 1013 | &pInfo, cifs_sb->local_nls, | 1023 | &pInfo, cifs_sb->local_nls, |
| 1014 | cifs_sb->mnt_cifs_flags & | 1024 | cifs_sb->mnt_cifs_flags & |
| 1015 | CIFS_MOUNT_MAP_SPECIAL_CHR); | 1025 | CIFS_MOUNT_MAP_SPECIAL_CHR); |
| @@ -1024,8 +1034,12 @@ mkdir_get_info: | |||
| 1024 | CIFS_MOUNT_SET_UID) { | 1034 | CIFS_MOUNT_SET_UID) { |
| 1025 | direntry->d_inode->i_uid = | 1035 | direntry->d_inode->i_uid = |
| 1026 | current->fsuid; | 1036 | current->fsuid; |
| 1027 | direntry->d_inode->i_gid = | 1037 | if (inode->i_mode & S_ISGID) |
| 1028 | current->fsgid; | 1038 | direntry->d_inode->i_gid = |
| 1039 | inode->i_gid; | ||
| 1040 | else | ||
| 1041 | direntry->d_inode->i_gid = | ||
| 1042 | current->fsgid; | ||
| 1029 | } | 1043 | } |
| 1030 | } | 1044 | } |
| 1031 | } | 1045 | } |
| @@ -1310,10 +1324,11 @@ int cifs_revalidate(struct dentry *direntry) | |||
| 1310 | /* if (S_ISDIR(direntry->d_inode->i_mode)) | 1324 | /* if (S_ISDIR(direntry->d_inode->i_mode)) |
| 1311 | shrink_dcache_parent(direntry); */ | 1325 | shrink_dcache_parent(direntry); */ |
| 1312 | if (S_ISREG(direntry->d_inode->i_mode)) { | 1326 | if (S_ISREG(direntry->d_inode->i_mode)) { |
| 1313 | if (direntry->d_inode->i_mapping) | 1327 | if (direntry->d_inode->i_mapping) { |
| 1314 | wbrc = filemap_fdatawait(direntry->d_inode->i_mapping); | 1328 | wbrc = filemap_fdatawait(direntry->d_inode->i_mapping); |
| 1315 | if (wbrc) | 1329 | if (wbrc) |
| 1316 | CIFS_I(direntry->d_inode)->write_behind_rc = wbrc; | 1330 | CIFS_I(direntry->d_inode)->write_behind_rc = wbrc; |
| 1331 | } | ||
| 1317 | /* may eventually have to do this for open files too */ | 1332 | /* may eventually have to do this for open files too */ |
| 1318 | if (list_empty(&(cifsInode->openFileList))) { | 1333 | if (list_empty(&(cifsInode->openFileList))) { |
| 1319 | /* changed on server - flush read ahead pages */ | 1334 | /* changed on server - flush read ahead pages */ |
| @@ -1489,30 +1504,228 @@ cifs_set_file_size(struct inode *inode, struct iattr *attrs, | |||
| 1489 | return rc; | 1504 | return rc; |
| 1490 | } | 1505 | } |
| 1491 | 1506 | ||
| 1492 | int cifs_setattr(struct dentry *direntry, struct iattr *attrs) | 1507 | static int |
| 1508 | cifs_set_file_info(struct inode *inode, struct iattr *attrs, int xid, | ||
| 1509 | char *full_path, __u32 dosattr) | ||
| 1510 | { | ||
| 1511 | int rc; | ||
| 1512 | int oplock = 0; | ||
| 1513 | __u16 netfid; | ||
| 1514 | __u32 netpid; | ||
| 1515 | bool set_time = false; | ||
| 1516 | struct cifsFileInfo *open_file; | ||
| 1517 | struct cifsInodeInfo *cifsInode = CIFS_I(inode); | ||
| 1518 | struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); | ||
| 1519 | struct cifsTconInfo *pTcon = cifs_sb->tcon; | ||
| 1520 | FILE_BASIC_INFO info_buf; | ||
| 1521 | |||
| 1522 | if (attrs->ia_valid & ATTR_ATIME) { | ||
| 1523 | set_time = true; | ||
| 1524 | info_buf.LastAccessTime = | ||
| 1525 | cpu_to_le64(cifs_UnixTimeToNT(attrs->ia_atime)); | ||
| 1526 | } else | ||
| 1527 | info_buf.LastAccessTime = 0; | ||
| 1528 | |||
| 1529 | if (attrs->ia_valid & ATTR_MTIME) { | ||
| 1530 | set_time = true; | ||
| 1531 | info_buf.LastWriteTime = | ||
| 1532 | cpu_to_le64(cifs_UnixTimeToNT(attrs->ia_mtime)); | ||
| 1533 | } else | ||
| 1534 | info_buf.LastWriteTime = 0; | ||
| 1535 | |||
| 1536 | /* | ||
| 1537 | * Samba throws this field away, but windows may actually use it. | ||
| 1538 | * Do not set ctime unless other time stamps are changed explicitly | ||
| 1539 | * (i.e. by utimes()) since we would then have a mix of client and | ||
| 1540 | * server times. | ||
| 1541 | */ | ||
| 1542 | if (set_time && (attrs->ia_valid & ATTR_CTIME)) { | ||
| 1543 | cFYI(1, ("CIFS - CTIME changed")); | ||
| 1544 | info_buf.ChangeTime = | ||
| 1545 | cpu_to_le64(cifs_UnixTimeToNT(attrs->ia_ctime)); | ||
| 1546 | } else | ||
| 1547 | info_buf.ChangeTime = 0; | ||
| 1548 | |||
| 1549 | info_buf.CreationTime = 0; /* don't change */ | ||
| 1550 | info_buf.Attributes = cpu_to_le32(dosattr); | ||
| 1551 | |||
| 1552 | /* | ||
| 1553 | * If the file is already open for write, just use that fileid | ||
| 1554 | */ | ||
| 1555 | open_file = find_writable_file(cifsInode); | ||
| 1556 | if (open_file) { | ||
| 1557 | netfid = open_file->netfid; | ||
| 1558 | netpid = open_file->pid; | ||
| 1559 | goto set_via_filehandle; | ||
| 1560 | } | ||
| 1561 | |||
| 1562 | /* | ||
| 1563 | * NT4 apparently returns success on this call, but it doesn't | ||
| 1564 | * really work. | ||
| 1565 | */ | ||
| 1566 | if (!(pTcon->ses->flags & CIFS_SES_NT4)) { | ||
| 1567 | rc = CIFSSMBSetPathInfo(xid, pTcon, full_path, | ||
| 1568 | &info_buf, cifs_sb->local_nls, | ||
| 1569 | cifs_sb->mnt_cifs_flags & | ||
| 1570 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1571 | if (rc != -EOPNOTSUPP && rc != -EINVAL) | ||
| 1572 | goto out; | ||
| 1573 | } | ||
| 1574 | |||
| 1575 | cFYI(1, ("calling SetFileInfo since SetPathInfo for " | ||
| 1576 | "times not supported by this server")); | ||
| 1577 | rc = CIFSSMBOpen(xid, pTcon, full_path, FILE_OPEN, | ||
| 1578 | SYNCHRONIZE | FILE_WRITE_ATTRIBUTES, | ||
| 1579 | CREATE_NOT_DIR, &netfid, &oplock, | ||
| 1580 | NULL, cifs_sb->local_nls, | ||
| 1581 | cifs_sb->mnt_cifs_flags & | ||
| 1582 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1583 | |||
| 1584 | if (rc != 0) { | ||
| 1585 | if (rc == -EIO) | ||
| 1586 | rc = -EINVAL; | ||
| 1587 | goto out; | ||
| 1588 | } | ||
| 1589 | |||
| 1590 | netpid = current->tgid; | ||
| 1591 | |||
| 1592 | set_via_filehandle: | ||
| 1593 | rc = CIFSSMBSetFileInfo(xid, pTcon, &info_buf, netfid, netpid); | ||
| 1594 | if (open_file == NULL) | ||
| 1595 | CIFSSMBClose(xid, pTcon, netfid); | ||
| 1596 | else | ||
| 1597 | atomic_dec(&open_file->wrtPending); | ||
| 1598 | out: | ||
| 1599 | return rc; | ||
| 1600 | } | ||
| 1601 | |||
| 1602 | static int | ||
| 1603 | cifs_setattr_unix(struct dentry *direntry, struct iattr *attrs) | ||
| 1493 | { | 1604 | { |
| 1605 | int rc; | ||
| 1494 | int xid; | 1606 | int xid; |
| 1495 | struct cifs_sb_info *cifs_sb; | ||
| 1496 | struct cifsTconInfo *pTcon; | ||
| 1497 | char *full_path = NULL; | 1607 | char *full_path = NULL; |
| 1498 | int rc = -EACCES; | ||
| 1499 | FILE_BASIC_INFO time_buf; | ||
| 1500 | bool set_time = false; | ||
| 1501 | bool set_dosattr = false; | ||
| 1502 | __u64 mode = 0xFFFFFFFFFFFFFFFFULL; | ||
| 1503 | __u64 uid = 0xFFFFFFFFFFFFFFFFULL; | ||
| 1504 | __u64 gid = 0xFFFFFFFFFFFFFFFFULL; | ||
| 1505 | struct cifsInodeInfo *cifsInode; | ||
| 1506 | struct inode *inode = direntry->d_inode; | 1608 | struct inode *inode = direntry->d_inode; |
| 1609 | struct cifsInodeInfo *cifsInode = CIFS_I(inode); | ||
| 1610 | struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); | ||
| 1611 | struct cifsTconInfo *pTcon = cifs_sb->tcon; | ||
| 1612 | struct cifs_unix_set_info_args *args = NULL; | ||
| 1613 | |||
| 1614 | cFYI(1, ("setattr_unix on file %s attrs->ia_valid=0x%x", | ||
| 1615 | direntry->d_name.name, attrs->ia_valid)); | ||
| 1616 | |||
| 1617 | xid = GetXid(); | ||
| 1618 | |||
| 1619 | if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_PERM) == 0) { | ||
| 1620 | /* check if we have permission to change attrs */ | ||
| 1621 | rc = inode_change_ok(inode, attrs); | ||
| 1622 | if (rc < 0) | ||
| 1623 | goto out; | ||
| 1624 | else | ||
| 1625 | rc = 0; | ||
| 1626 | } | ||
| 1627 | |||
| 1628 | full_path = build_path_from_dentry(direntry); | ||
| 1629 | if (full_path == NULL) { | ||
| 1630 | rc = -ENOMEM; | ||
| 1631 | goto out; | ||
| 1632 | } | ||
| 1633 | |||
| 1634 | if ((attrs->ia_valid & ATTR_MTIME) || (attrs->ia_valid & ATTR_SIZE)) { | ||
| 1635 | /* | ||
| 1636 | Flush data before changing file size or changing the last | ||
| 1637 | write time of the file on the server. If the | ||
| 1638 | flush returns error, store it to report later and continue. | ||
| 1639 | BB: This should be smarter. Why bother flushing pages that | ||
| 1640 | will be truncated anyway? Also, should we error out here if | ||
| 1641 | the flush returns error? | ||
| 1642 | */ | ||
| 1643 | rc = filemap_write_and_wait(inode->i_mapping); | ||
| 1644 | if (rc != 0) { | ||
| 1645 | cifsInode->write_behind_rc = rc; | ||
| 1646 | rc = 0; | ||
| 1647 | } | ||
| 1648 | } | ||
| 1649 | |||
| 1650 | if (attrs->ia_valid & ATTR_SIZE) { | ||
| 1651 | rc = cifs_set_file_size(inode, attrs, xid, full_path); | ||
| 1652 | if (rc != 0) | ||
| 1653 | goto out; | ||
| 1654 | } | ||
| 1655 | |||
| 1656 | /* skip mode change if it's just for clearing setuid/setgid */ | ||
| 1657 | if (attrs->ia_valid & (ATTR_KILL_SUID|ATTR_KILL_SGID)) | ||
| 1658 | attrs->ia_valid &= ~ATTR_MODE; | ||
| 1659 | |||
| 1660 | args = kmalloc(sizeof(*args), GFP_KERNEL); | ||
| 1661 | if (args == NULL) { | ||
| 1662 | rc = -ENOMEM; | ||
| 1663 | goto out; | ||
| 1664 | } | ||
| 1665 | |||
| 1666 | /* set up the struct */ | ||
| 1667 | if (attrs->ia_valid & ATTR_MODE) | ||
| 1668 | args->mode = attrs->ia_mode; | ||
| 1669 | else | ||
| 1670 | args->mode = NO_CHANGE_64; | ||
| 1671 | |||
| 1672 | if (attrs->ia_valid & ATTR_UID) | ||
| 1673 | args->uid = attrs->ia_uid; | ||
| 1674 | else | ||
| 1675 | args->uid = NO_CHANGE_64; | ||
| 1676 | |||
| 1677 | if (attrs->ia_valid & ATTR_GID) | ||
| 1678 | args->gid = attrs->ia_gid; | ||
| 1679 | else | ||
| 1680 | args->gid = NO_CHANGE_64; | ||
| 1681 | |||
| 1682 | if (attrs->ia_valid & ATTR_ATIME) | ||
| 1683 | args->atime = cifs_UnixTimeToNT(attrs->ia_atime); | ||
| 1684 | else | ||
| 1685 | args->atime = NO_CHANGE_64; | ||
| 1686 | |||
| 1687 | if (attrs->ia_valid & ATTR_MTIME) | ||
| 1688 | args->mtime = cifs_UnixTimeToNT(attrs->ia_mtime); | ||
| 1689 | else | ||
| 1690 | args->mtime = NO_CHANGE_64; | ||
| 1691 | |||
| 1692 | if (attrs->ia_valid & ATTR_CTIME) | ||
| 1693 | args->ctime = cifs_UnixTimeToNT(attrs->ia_ctime); | ||
| 1694 | else | ||
| 1695 | args->ctime = NO_CHANGE_64; | ||
| 1696 | |||
| 1697 | args->device = 0; | ||
| 1698 | rc = CIFSSMBUnixSetInfo(xid, pTcon, full_path, args, | ||
| 1699 | cifs_sb->local_nls, | ||
| 1700 | cifs_sb->mnt_cifs_flags & | ||
| 1701 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1702 | |||
| 1703 | if (!rc) | ||
| 1704 | rc = inode_setattr(inode, attrs); | ||
| 1705 | out: | ||
| 1706 | kfree(args); | ||
| 1707 | kfree(full_path); | ||
| 1708 | FreeXid(xid); | ||
| 1709 | return rc; | ||
| 1710 | } | ||
| 1711 | |||
| 1712 | static int | ||
| 1713 | cifs_setattr_nounix(struct dentry *direntry, struct iattr *attrs) | ||
| 1714 | { | ||
| 1715 | int xid; | ||
| 1716 | struct inode *inode = direntry->d_inode; | ||
| 1717 | struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); | ||
| 1718 | struct cifsInodeInfo *cifsInode = CIFS_I(inode); | ||
| 1719 | char *full_path = NULL; | ||
| 1720 | int rc = -EACCES; | ||
| 1721 | __u32 dosattr = 0; | ||
| 1722 | __u64 mode = NO_CHANGE_64; | ||
| 1507 | 1723 | ||
| 1508 | xid = GetXid(); | 1724 | xid = GetXid(); |
| 1509 | 1725 | ||
| 1510 | cFYI(1, ("setattr on file %s attrs->iavalid 0x%x", | 1726 | cFYI(1, ("setattr on file %s attrs->iavalid 0x%x", |
| 1511 | direntry->d_name.name, attrs->ia_valid)); | 1727 | direntry->d_name.name, attrs->ia_valid)); |
| 1512 | 1728 | ||
| 1513 | cifs_sb = CIFS_SB(inode->i_sb); | ||
| 1514 | pTcon = cifs_sb->tcon; | ||
| 1515 | |||
| 1516 | if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_PERM) == 0) { | 1729 | if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_PERM) == 0) { |
| 1517 | /* check if we have permission to change attrs */ | 1730 | /* check if we have permission to change attrs */ |
| 1518 | rc = inode_change_ok(inode, attrs); | 1731 | rc = inode_change_ok(inode, attrs); |
| @@ -1528,7 +1741,6 @@ int cifs_setattr(struct dentry *direntry, struct iattr *attrs) | |||
| 1528 | FreeXid(xid); | 1741 | FreeXid(xid); |
| 1529 | return -ENOMEM; | 1742 | return -ENOMEM; |
| 1530 | } | 1743 | } |
| 1531 | cifsInode = CIFS_I(inode); | ||
| 1532 | 1744 | ||
| 1533 | if ((attrs->ia_valid & ATTR_MTIME) || (attrs->ia_valid & ATTR_SIZE)) { | 1745 | if ((attrs->ia_valid & ATTR_MTIME) || (attrs->ia_valid & ATTR_SIZE)) { |
| 1534 | /* | 1746 | /* |
| @@ -1559,21 +1771,8 @@ int cifs_setattr(struct dentry *direntry, struct iattr *attrs) | |||
| 1559 | * CIFSACL support + proper Windows to Unix idmapping, we may be | 1771 | * CIFSACL support + proper Windows to Unix idmapping, we may be |
| 1560 | * able to support this in the future. | 1772 | * able to support this in the future. |
| 1561 | */ | 1773 | */ |
| 1562 | if (!pTcon->unix_ext && | 1774 | if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID)) |
| 1563 | !(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_SET_UID)) { | ||
| 1564 | attrs->ia_valid &= ~(ATTR_UID | ATTR_GID); | 1775 | attrs->ia_valid &= ~(ATTR_UID | ATTR_GID); |
| 1565 | } else { | ||
| 1566 | if (attrs->ia_valid & ATTR_UID) { | ||
| 1567 | cFYI(1, ("UID changed to %d", attrs->ia_uid)); | ||
| 1568 | uid = attrs->ia_uid; | ||
| 1569 | } | ||
| 1570 | if (attrs->ia_valid & ATTR_GID) { | ||
| 1571 | cFYI(1, ("GID changed to %d", attrs->ia_gid)); | ||
| 1572 | gid = attrs->ia_gid; | ||
| 1573 | } | ||
| 1574 | } | ||
| 1575 | |||
| 1576 | time_buf.Attributes = 0; | ||
| 1577 | 1776 | ||
| 1578 | /* skip mode change if it's just for clearing setuid/setgid */ | 1777 | /* skip mode change if it's just for clearing setuid/setgid */ |
| 1579 | if (attrs->ia_valid & (ATTR_KILL_SUID|ATTR_KILL_SGID)) | 1778 | if (attrs->ia_valid & (ATTR_KILL_SUID|ATTR_KILL_SGID)) |
| @@ -1584,13 +1783,7 @@ int cifs_setattr(struct dentry *direntry, struct iattr *attrs) | |||
| 1584 | mode = attrs->ia_mode; | 1783 | mode = attrs->ia_mode; |
| 1585 | } | 1784 | } |
| 1586 | 1785 | ||
| 1587 | if ((pTcon->unix_ext) | 1786 | if (attrs->ia_valid & ATTR_MODE) { |
| 1588 | && (attrs->ia_valid & (ATTR_MODE | ATTR_GID | ATTR_UID))) | ||
| 1589 | rc = CIFSSMBUnixSetPerms(xid, pTcon, full_path, mode, uid, gid, | ||
| 1590 | 0 /* dev_t */, cifs_sb->local_nls, | ||
| 1591 | cifs_sb->mnt_cifs_flags & | ||
| 1592 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1593 | else if (attrs->ia_valid & ATTR_MODE) { | ||
| 1594 | rc = 0; | 1787 | rc = 0; |
| 1595 | #ifdef CONFIG_CIFS_EXPERIMENTAL | 1788 | #ifdef CONFIG_CIFS_EXPERIMENTAL |
| 1596 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_CIFS_ACL) | 1789 | if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_CIFS_ACL) |
| @@ -1599,24 +1792,19 @@ int cifs_setattr(struct dentry *direntry, struct iattr *attrs) | |||
| 1599 | #endif | 1792 | #endif |
| 1600 | if (((mode & S_IWUGO) == 0) && | 1793 | if (((mode & S_IWUGO) == 0) && |
| 1601 | (cifsInode->cifsAttrs & ATTR_READONLY) == 0) { | 1794 | (cifsInode->cifsAttrs & ATTR_READONLY) == 0) { |
| 1602 | set_dosattr = true; | 1795 | |
| 1603 | time_buf.Attributes = cpu_to_le32(cifsInode->cifsAttrs | | 1796 | dosattr = cifsInode->cifsAttrs | ATTR_READONLY; |
| 1604 | ATTR_READONLY); | 1797 | |
| 1605 | /* fix up mode if we're not using dynperm */ | 1798 | /* fix up mode if we're not using dynperm */ |
| 1606 | if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_DYNPERM) == 0) | 1799 | if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_DYNPERM) == 0) |
| 1607 | attrs->ia_mode = inode->i_mode & ~S_IWUGO; | 1800 | attrs->ia_mode = inode->i_mode & ~S_IWUGO; |
| 1608 | } else if ((mode & S_IWUGO) && | 1801 | } else if ((mode & S_IWUGO) && |
| 1609 | (cifsInode->cifsAttrs & ATTR_READONLY)) { | 1802 | (cifsInode->cifsAttrs & ATTR_READONLY)) { |
| 1610 | /* If file is readonly on server, we would | 1803 | |
| 1611 | not be able to write to it - so if any write | 1804 | dosattr = cifsInode->cifsAttrs & ~ATTR_READONLY; |
| 1612 | bit is enabled for user or group or other we | 1805 | /* Attributes of 0 are ignored */ |
| 1613 | need to at least try to remove r/o dos attr */ | 1806 | if (dosattr == 0) |
| 1614 | set_dosattr = true; | 1807 | dosattr |= ATTR_NORMAL; |
| 1615 | time_buf.Attributes = cpu_to_le32(cifsInode->cifsAttrs & | ||
| 1616 | (~ATTR_READONLY)); | ||
| 1617 | /* Windows ignores set to zero */ | ||
| 1618 | if (time_buf.Attributes == 0) | ||
| 1619 | time_buf.Attributes |= cpu_to_le32(ATTR_NORMAL); | ||
| 1620 | 1808 | ||
| 1621 | /* reset local inode permissions to normal */ | 1809 | /* reset local inode permissions to normal */ |
| 1622 | if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_DYNPERM)) { | 1810 | if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_DYNPERM)) { |
| @@ -1634,82 +1822,18 @@ int cifs_setattr(struct dentry *direntry, struct iattr *attrs) | |||
| 1634 | } | 1822 | } |
| 1635 | } | 1823 | } |
| 1636 | 1824 | ||
| 1637 | if (attrs->ia_valid & ATTR_ATIME) { | 1825 | if (attrs->ia_valid & (ATTR_MTIME|ATTR_ATIME|ATTR_CTIME) || |
| 1638 | set_time = true; | 1826 | ((attrs->ia_valid & ATTR_MODE) && dosattr)) { |
| 1639 | time_buf.LastAccessTime = | 1827 | rc = cifs_set_file_info(inode, attrs, xid, full_path, dosattr); |
| 1640 | cpu_to_le64(cifs_UnixTimeToNT(attrs->ia_atime)); | 1828 | /* BB: check for rc = -EOPNOTSUPP and switch to legacy mode */ |
| 1641 | } else | ||
| 1642 | time_buf.LastAccessTime = 0; | ||
| 1643 | |||
| 1644 | if (attrs->ia_valid & ATTR_MTIME) { | ||
| 1645 | set_time = true; | ||
| 1646 | time_buf.LastWriteTime = | ||
| 1647 | cpu_to_le64(cifs_UnixTimeToNT(attrs->ia_mtime)); | ||
| 1648 | } else | ||
| 1649 | time_buf.LastWriteTime = 0; | ||
| 1650 | /* Do not set ctime explicitly unless other time | ||
| 1651 | stamps are changed explicitly (i.e. by utime() | ||
| 1652 | since we would then have a mix of client and | ||
| 1653 | server times */ | ||
| 1654 | 1829 | ||
| 1655 | if (set_time && (attrs->ia_valid & ATTR_CTIME)) { | ||
| 1656 | set_time = true; | ||
| 1657 | /* Although Samba throws this field away | ||
| 1658 | it may be useful to Windows - but we do | ||
| 1659 | not want to set ctime unless some other | ||
| 1660 | timestamp is changing */ | ||
| 1661 | cFYI(1, ("CIFS - CTIME changed")); | ||
| 1662 | time_buf.ChangeTime = | ||
| 1663 | cpu_to_le64(cifs_UnixTimeToNT(attrs->ia_ctime)); | ||
| 1664 | } else | ||
| 1665 | time_buf.ChangeTime = 0; | ||
| 1666 | |||
| 1667 | if (set_time || set_dosattr) { | ||
| 1668 | time_buf.CreationTime = 0; /* do not change */ | ||
| 1669 | /* In the future we should experiment - try setting timestamps | ||
| 1670 | via Handle (SetFileInfo) instead of by path */ | ||
| 1671 | if (!(pTcon->ses->flags & CIFS_SES_NT4)) | ||
| 1672 | rc = CIFSSMBSetTimes(xid, pTcon, full_path, &time_buf, | ||
| 1673 | cifs_sb->local_nls, | ||
| 1674 | cifs_sb->mnt_cifs_flags & | ||
| 1675 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1676 | else | ||
| 1677 | rc = -EOPNOTSUPP; | ||
| 1678 | |||
| 1679 | if (rc == -EOPNOTSUPP) { | ||
| 1680 | int oplock = 0; | ||
| 1681 | __u16 netfid; | ||
| 1682 | |||
| 1683 | cFYI(1, ("calling SetFileInfo since SetPathInfo for " | ||
| 1684 | "times not supported by this server")); | ||
| 1685 | /* BB we could scan to see if we already have it open | ||
| 1686 | and pass in pid of opener to function */ | ||
| 1687 | rc = CIFSSMBOpen(xid, pTcon, full_path, FILE_OPEN, | ||
| 1688 | SYNCHRONIZE | FILE_WRITE_ATTRIBUTES, | ||
| 1689 | CREATE_NOT_DIR, &netfid, &oplock, | ||
| 1690 | NULL, cifs_sb->local_nls, | ||
| 1691 | cifs_sb->mnt_cifs_flags & | ||
| 1692 | CIFS_MOUNT_MAP_SPECIAL_CHR); | ||
| 1693 | if (rc == 0) { | ||
| 1694 | rc = CIFSSMBSetFileTimes(xid, pTcon, &time_buf, | ||
| 1695 | netfid); | ||
| 1696 | CIFSSMBClose(xid, pTcon, netfid); | ||
| 1697 | } else { | ||
| 1698 | /* BB For even older servers we could convert time_buf | ||
| 1699 | into old DOS style which uses two second | ||
| 1700 | granularity */ | ||
| 1701 | |||
| 1702 | /* rc = CIFSSMBSetTimesLegacy(xid, pTcon, full_path, | ||
| 1703 | &time_buf, cifs_sb->local_nls); */ | ||
| 1704 | } | ||
| 1705 | } | ||
| 1706 | /* Even if error on time set, no sense failing the call if | 1830 | /* Even if error on time set, no sense failing the call if |
| 1707 | the server would set the time to a reasonable value anyway, | 1831 | the server would set the time to a reasonable value anyway, |
| 1708 | and this check ensures that we are not being called from | 1832 | and this check ensures that we are not being called from |
| 1709 | sys_utimes in which case we ought to fail the call back to | 1833 | sys_utimes in which case we ought to fail the call back to |
| 1710 | the user when the server rejects the call */ | 1834 | the user when the server rejects the call */ |
| 1711 | if ((rc) && (attrs->ia_valid & | 1835 | if ((rc) && (attrs->ia_valid & |
| 1712 | (ATTR_MODE | ATTR_GID | ATTR_UID | ATTR_SIZE))) | 1836 | (ATTR_MODE | ATTR_GID | ATTR_UID | ATTR_SIZE))) |
| 1713 | rc = 0; | 1837 | rc = 0; |
| 1714 | } | 1838 | } |
| 1715 | 1839 | ||
| @@ -1723,6 +1847,21 @@ cifs_setattr_exit: | |||
| 1723 | return rc; | 1847 | return rc; |
| 1724 | } | 1848 | } |
| 1725 | 1849 | ||
| 1850 | int | ||
| 1851 | cifs_setattr(struct dentry *direntry, struct iattr *attrs) | ||
| 1852 | { | ||
| 1853 | struct inode *inode = direntry->d_inode; | ||
| 1854 | struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb); | ||
| 1855 | struct cifsTconInfo *pTcon = cifs_sb->tcon; | ||
| 1856 | |||
| 1857 | if (pTcon->unix_ext) | ||
| 1858 | return cifs_setattr_unix(direntry, attrs); | ||
| 1859 | |||
| 1860 | return cifs_setattr_nounix(direntry, attrs); | ||
| 1861 | |||
| 1862 | /* BB: add cifs_setattr_legacy for really old servers */ | ||
| 1863 | } | ||
| 1864 | |||
| 1726 | #if 0 | 1865 | #if 0 |
| 1727 | void cifs_delete_inode(struct inode *inode) | 1866 | void cifs_delete_inode(struct inode *inode) |
| 1728 | { | 1867 | { |
diff --git a/fs/cifs/transport.c b/fs/cifs/transport.c index 000ac509c98a..e286db9f5ee2 100644 --- a/fs/cifs/transport.c +++ b/fs/cifs/transport.c | |||
| @@ -265,6 +265,7 @@ smb_send2(struct socket *ssocket, struct kvec *iov, int n_vec, | |||
| 265 | cFYI(1, ("Sending smb: total_len %d", total_len)); | 265 | cFYI(1, ("Sending smb: total_len %d", total_len)); |
| 266 | dump_smb(smb_buffer, len); | 266 | dump_smb(smb_buffer, len); |
| 267 | 267 | ||
| 268 | i = 0; | ||
| 268 | while (total_len) { | 269 | while (total_len) { |
| 269 | rc = kernel_sendmsg(ssocket, &smb_msg, &iov[first_vec], | 270 | rc = kernel_sendmsg(ssocket, &smb_msg, &iov[first_vec], |
| 270 | n_vec - first_vec, total_len); | 271 | n_vec - first_vec, total_len); |
diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index eef1629806f5..2e51adac65de 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c | |||
| @@ -851,7 +851,7 @@ struct nfsd4_operation { | |||
| 851 | 851 | ||
| 852 | static struct nfsd4_operation nfsd4_ops[]; | 852 | static struct nfsd4_operation nfsd4_ops[]; |
| 853 | 853 | ||
| 854 | static inline char *nfsd4_op_name(unsigned opnum); | 854 | static const char *nfsd4_op_name(unsigned opnum); |
| 855 | 855 | ||
| 856 | /* | 856 | /* |
| 857 | * COMPOUND call. | 857 | * COMPOUND call. |
| @@ -1116,8 +1116,7 @@ static struct nfsd4_operation nfsd4_ops[OP_RELEASE_LOCKOWNER+1] = { | |||
| 1116 | }, | 1116 | }, |
| 1117 | }; | 1117 | }; |
| 1118 | 1118 | ||
| 1119 | static inline char * | 1119 | static const char *nfsd4_op_name(unsigned opnum) |
| 1120 | nfsd4_op_name(unsigned opnum) | ||
| 1121 | { | 1120 | { |
| 1122 | if (opnum < ARRAY_SIZE(nfsd4_ops)) | 1121 | if (opnum < ARRAY_SIZE(nfsd4_ops)) |
| 1123 | return nfsd4_ops[opnum].op_name; | 1122 | return nfsd4_ops[opnum].op_name; |
diff --git a/include/linux/dm9000.h b/include/linux/dm9000.h index fc82446b6425..c30879cf93bc 100644 --- a/include/linux/dm9000.h +++ b/include/linux/dm9000.h | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | 27 | ||
| 28 | struct dm9000_plat_data { | 28 | struct dm9000_plat_data { |
| 29 | unsigned int flags; | 29 | unsigned int flags; |
| 30 | unsigned char dev_addr[6]; | ||
| 30 | 31 | ||
| 31 | /* allow replacement IO routines */ | 32 | /* allow replacement IO routines */ |
| 32 | 33 | ||
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 8bb5e87df365..b4b038b89ee6 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h | |||
| @@ -27,9 +27,24 @@ struct ethtool_cmd { | |||
| 27 | __u8 autoneg; /* Enable or disable autonegotiation */ | 27 | __u8 autoneg; /* Enable or disable autonegotiation */ |
| 28 | __u32 maxtxpkt; /* Tx pkts before generating tx int */ | 28 | __u32 maxtxpkt; /* Tx pkts before generating tx int */ |
| 29 | __u32 maxrxpkt; /* Rx pkts before generating rx int */ | 29 | __u32 maxrxpkt; /* Rx pkts before generating rx int */ |
| 30 | __u32 reserved[4]; | 30 | __u16 speed_hi; |
| 31 | __u16 reserved2; | ||
| 32 | __u32 reserved[3]; | ||
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 35 | static inline void ethtool_cmd_speed_set(struct ethtool_cmd *ep, | ||
| 36 | __u32 speed) | ||
| 37 | { | ||
| 38 | |||
| 39 | ep->speed = (__u16)speed; | ||
| 40 | ep->speed_hi = (__u16)(speed >> 16); | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep) | ||
| 44 | { | ||
| 45 | return (ep->speed_hi << 16) | ep->speed; | ||
| 46 | } | ||
| 47 | |||
| 33 | #define ETHTOOL_BUSINFO_LEN 32 | 48 | #define ETHTOOL_BUSINFO_LEN 32 |
| 34 | /* these strings are set to whatever the driver author decides... */ | 49 | /* these strings are set to whatever the driver author decides... */ |
| 35 | struct ethtool_drvinfo { | 50 | struct ethtool_drvinfo { |
diff --git a/include/linux/i2c-pnx.h b/include/linux/i2c-pnx.h index e6e9c814da61..f13255e06406 100644 --- a/include/linux/i2c-pnx.h +++ b/include/linux/i2c-pnx.h | |||
| @@ -12,7 +12,9 @@ | |||
| 12 | #ifndef __I2C_PNX_H__ | 12 | #ifndef __I2C_PNX_H__ |
| 13 | #define __I2C_PNX_H__ | 13 | #define __I2C_PNX_H__ |
| 14 | 14 | ||
| 15 | #include <asm/arch/i2c.h> | 15 | #include <linux/pm.h> |
| 16 | |||
| 17 | struct platform_device; | ||
| 16 | 18 | ||
| 17 | struct i2c_pnx_mif { | 19 | struct i2c_pnx_mif { |
| 18 | int ret; /* Return value */ | 20 | int ret; /* Return value */ |
diff --git a/include/linux/list.h b/include/linux/list.h index 453916bc0412..db35ef02e745 100644 --- a/include/linux/list.h +++ b/include/linux/list.h | |||
| @@ -214,22 +214,62 @@ static inline int list_is_singular(const struct list_head *head) | |||
| 214 | return !list_empty(head) && (head->next == head->prev); | 214 | return !list_empty(head) && (head->next == head->prev); |
| 215 | } | 215 | } |
| 216 | 216 | ||
| 217 | static inline void __list_cut_position(struct list_head *list, | ||
| 218 | struct list_head *head, struct list_head *entry) | ||
| 219 | { | ||
| 220 | struct list_head *new_first = entry->next; | ||
| 221 | list->next = head->next; | ||
| 222 | list->next->prev = list; | ||
| 223 | list->prev = entry; | ||
| 224 | entry->next = list; | ||
| 225 | head->next = new_first; | ||
| 226 | new_first->prev = head; | ||
| 227 | } | ||
| 228 | |||
| 229 | /** | ||
| 230 | * list_cut_position - cut a list into two | ||
| 231 | * @list: a new list to add all removed entries | ||
| 232 | * @head: a list with entries | ||
| 233 | * @entry: an entry within head, could be the head itself | ||
| 234 | * and if so we won't cut the list | ||
| 235 | * | ||
| 236 | * This helper moves the initial part of @head, up to and | ||
| 237 | * including @entry, from @head to @list. You should | ||
| 238 | * pass on @entry an element you know is on @head. @list | ||
| 239 | * should be an empty list or a list you do not care about | ||
| 240 | * losing its data. | ||
| 241 | * | ||
| 242 | */ | ||
| 243 | static inline void list_cut_position(struct list_head *list, | ||
| 244 | struct list_head *head, struct list_head *entry) | ||
| 245 | { | ||
| 246 | if (list_empty(head)) | ||
| 247 | return; | ||
| 248 | if (list_is_singular(head) && | ||
| 249 | (head->next != entry && head != entry)) | ||
| 250 | return; | ||
| 251 | if (entry == head) | ||
| 252 | INIT_LIST_HEAD(list); | ||
| 253 | else | ||
| 254 | __list_cut_position(list, head, entry); | ||
| 255 | } | ||
| 256 | |||
| 217 | static inline void __list_splice(const struct list_head *list, | 257 | static inline void __list_splice(const struct list_head *list, |
| 218 | struct list_head *head) | 258 | struct list_head *prev, |
| 259 | struct list_head *next) | ||
| 219 | { | 260 | { |
| 220 | struct list_head *first = list->next; | 261 | struct list_head *first = list->next; |
| 221 | struct list_head *last = list->prev; | 262 | struct list_head *last = list->prev; |
| 222 | struct list_head *at = head->next; | ||
| 223 | 263 | ||
| 224 | first->prev = head; | 264 | first->prev = prev; |
| 225 | head->next = first; | 265 | prev->next = first; |
| 226 | 266 | ||
| 227 | last->next = at; | 267 | last->next = next; |
| 228 | at->prev = last; | 268 | next->prev = last; |
| 229 | } | 269 | } |
| 230 | 270 | ||
| 231 | /** | 271 | /** |
| 232 | * list_splice - join two lists | 272 | * list_splice - join two lists, this is designed for stacks |
| 233 | * @list: the new list to add. | 273 | * @list: the new list to add. |
| 234 | * @head: the place to add it in the first list. | 274 | * @head: the place to add it in the first list. |
| 235 | */ | 275 | */ |
| @@ -237,7 +277,19 @@ static inline void list_splice(const struct list_head *list, | |||
| 237 | struct list_head *head) | 277 | struct list_head *head) |
| 238 | { | 278 | { |
| 239 | if (!list_empty(list)) | 279 | if (!list_empty(list)) |
| 240 | __list_splice(list, head); | 280 | __list_splice(list, head, head->next); |
| 281 | } | ||
| 282 | |||
| 283 | /** | ||
| 284 | * list_splice_tail - join two lists, each list being a queue | ||
| 285 | * @list: the new list to add. | ||
| 286 | * @head: the place to add it in the first list. | ||
| 287 | */ | ||
| 288 | static inline void list_splice_tail(struct list_head *list, | ||
| 289 | struct list_head *head) | ||
| 290 | { | ||
| 291 | if (!list_empty(list)) | ||
| 292 | __list_splice(list, head->prev, head); | ||
| 241 | } | 293 | } |
| 242 | 294 | ||
| 243 | /** | 295 | /** |
| @@ -251,7 +303,24 @@ static inline void list_splice_init(struct list_head *list, | |||
| 251 | struct list_head *head) | 303 | struct list_head *head) |
| 252 | { | 304 | { |
| 253 | if (!list_empty(list)) { | 305 | if (!list_empty(list)) { |
| 254 | __list_splice(list, head); | 306 | __list_splice(list, head, head->next); |
| 307 | INIT_LIST_HEAD(list); | ||
| 308 | } | ||
| 309 | } | ||
| 310 | |||
| 311 | /** | ||
| 312 | * list_splice_tail_init - join two lists and reinitialise the emptied list | ||
| 313 | * @list: the new list to add. | ||
| 314 | * @head: the place to add it in the first list. | ||
| 315 | * | ||
| 316 | * Each of the lists is a queue. | ||
| 317 | * The list at @list is reinitialised | ||
| 318 | */ | ||
| 319 | static inline void list_splice_tail_init(struct list_head *list, | ||
| 320 | struct list_head *head) | ||
| 321 | { | ||
| 322 | if (!list_empty(list)) { | ||
| 323 | __list_splice(list, head->prev, head); | ||
| 255 | INIT_LIST_HEAD(list); | 324 | INIT_LIST_HEAD(list); |
| 256 | } | 325 | } |
| 257 | } | 326 | } |
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h index 071cf96cf01f..6f65b2c8bb89 100644 --- a/include/linux/mlx4/cq.h +++ b/include/linux/mlx4/cq.h | |||
| @@ -39,17 +39,18 @@ | |||
| 39 | #include <linux/mlx4/doorbell.h> | 39 | #include <linux/mlx4/doorbell.h> |
| 40 | 40 | ||
| 41 | struct mlx4_cqe { | 41 | struct mlx4_cqe { |
| 42 | __be32 my_qpn; | 42 | __be32 vlan_my_qpn; |
| 43 | __be32 immed_rss_invalid; | 43 | __be32 immed_rss_invalid; |
| 44 | __be32 g_mlpath_rqpn; | 44 | __be32 g_mlpath_rqpn; |
| 45 | u8 sl; | 45 | __be16 sl_vid; |
| 46 | u8 reserved1; | ||
| 47 | __be16 rlid; | 46 | __be16 rlid; |
| 48 | __be32 ipoib_status; | 47 | __be16 status; |
| 48 | u8 ipv6_ext_mask; | ||
| 49 | u8 badfcs_enc; | ||
| 49 | __be32 byte_cnt; | 50 | __be32 byte_cnt; |
| 50 | __be16 wqe_index; | 51 | __be16 wqe_index; |
| 51 | __be16 checksum; | 52 | __be16 checksum; |
| 52 | u8 reserved2[3]; | 53 | u8 reserved[3]; |
| 53 | u8 owner_sr_opcode; | 54 | u8 owner_sr_opcode; |
| 54 | }; | 55 | }; |
| 55 | 56 | ||
| @@ -64,6 +65,11 @@ struct mlx4_err_cqe { | |||
| 64 | }; | 65 | }; |
| 65 | 66 | ||
| 66 | enum { | 67 | enum { |
| 68 | MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, | ||
| 69 | MLX4_CQE_QPN_MASK = 0xffffff, | ||
| 70 | }; | ||
| 71 | |||
| 72 | enum { | ||
| 67 | MLX4_CQE_OWNER_MASK = 0x80, | 73 | MLX4_CQE_OWNER_MASK = 0x80, |
| 68 | MLX4_CQE_IS_SEND_MASK = 0x40, | 74 | MLX4_CQE_IS_SEND_MASK = 0x40, |
| 69 | MLX4_CQE_OPCODE_MASK = 0x1f | 75 | MLX4_CQE_OPCODE_MASK = 0x1f |
| @@ -86,13 +92,19 @@ enum { | |||
| 86 | }; | 92 | }; |
| 87 | 93 | ||
| 88 | enum { | 94 | enum { |
| 89 | MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22, | 95 | MLX4_CQE_STATUS_IPV4 = 1 << 6, |
| 90 | MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23, | 96 | MLX4_CQE_STATUS_IPV4F = 1 << 7, |
| 91 | MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24, | 97 | MLX4_CQE_STATUS_IPV6 = 1 << 8, |
| 92 | MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25, | 98 | MLX4_CQE_STATUS_IPV4OPT = 1 << 9, |
| 93 | MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26, | 99 | MLX4_CQE_STATUS_TCP = 1 << 10, |
| 94 | MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27, | 100 | MLX4_CQE_STATUS_UDP = 1 << 11, |
| 95 | MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28, | 101 | MLX4_CQE_STATUS_IPOK = 1 << 12, |
| 102 | }; | ||
| 103 | |||
| 104 | enum { | ||
| 105 | MLX4_CQE_LLC = 1, | ||
| 106 | MLX4_CQE_SNAP = 1 << 1, | ||
| 107 | MLX4_CQE_BAD_FCS = 1 << 4, | ||
| 96 | }; | 108 | }; |
| 97 | 109 | ||
| 98 | static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, | 110 | static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, |
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index fd31756e1a00..ea7416c901d1 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h | |||
| @@ -172,7 +172,7 @@ static inline void ptrace_init_task(struct task_struct *child, bool ptrace) | |||
| 172 | child->ptrace = 0; | 172 | child->ptrace = 0; |
| 173 | if (unlikely(ptrace)) { | 173 | if (unlikely(ptrace)) { |
| 174 | child->ptrace = current->ptrace; | 174 | child->ptrace = current->ptrace; |
| 175 | __ptrace_link(child, current->parent); | 175 | ptrace_link(child, current->parent); |
| 176 | } | 176 | } |
| 177 | } | 177 | } |
| 178 | 178 | ||
diff --git a/include/linux/tracehook.h b/include/linux/tracehook.h index ab3ef7aefa95..b48d81969574 100644 --- a/include/linux/tracehook.h +++ b/include/linux/tracehook.h | |||
| @@ -280,7 +280,7 @@ static inline void tracehook_report_clone(int trace, struct pt_regs *regs, | |||
| 280 | unsigned long clone_flags, | 280 | unsigned long clone_flags, |
| 281 | pid_t pid, struct task_struct *child) | 281 | pid_t pid, struct task_struct *child) |
| 282 | { | 282 | { |
| 283 | if (unlikely(trace)) { | 283 | if (unlikely(trace) || unlikely(clone_flags & CLONE_PTRACE)) { |
| 284 | /* | 284 | /* |
| 285 | * The child starts up with an immediate SIGSTOP. | 285 | * The child starts up with an immediate SIGSTOP. |
| 286 | */ | 286 | */ |
diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h index 1de98f150e99..d548de326722 100644 --- a/include/media/soc_camera.h +++ b/include/media/soc_camera.h | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | #include <linux/videodev2.h> | 15 | #include <linux/videodev2.h> |
| 16 | #include <media/videobuf-core.h> | 16 | #include <media/videobuf-core.h> |
| 17 | #include <linux/pm.h> | ||
| 17 | 18 | ||
| 18 | struct soc_camera_device { | 19 | struct soc_camera_device { |
| 19 | struct list_head list; | 20 | struct list_head list; |
| @@ -63,6 +64,8 @@ struct soc_camera_host_ops { | |||
| 63 | struct module *owner; | 64 | struct module *owner; |
| 64 | int (*add)(struct soc_camera_device *); | 65 | int (*add)(struct soc_camera_device *); |
| 65 | void (*remove)(struct soc_camera_device *); | 66 | void (*remove)(struct soc_camera_device *); |
| 67 | int (*suspend)(struct soc_camera_device *, pm_message_t state); | ||
| 68 | int (*resume)(struct soc_camera_device *); | ||
| 66 | int (*set_fmt_cap)(struct soc_camera_device *, __u32, | 69 | int (*set_fmt_cap)(struct soc_camera_device *, __u32, |
| 67 | struct v4l2_rect *); | 70 | struct v4l2_rect *); |
| 68 | int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *); | 71 | int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *); |
| @@ -111,6 +114,8 @@ struct soc_camera_ops { | |||
| 111 | struct module *owner; | 114 | struct module *owner; |
| 112 | int (*probe)(struct soc_camera_device *); | 115 | int (*probe)(struct soc_camera_device *); |
| 113 | void (*remove)(struct soc_camera_device *); | 116 | void (*remove)(struct soc_camera_device *); |
| 117 | int (*suspend)(struct soc_camera_device *, pm_message_t state); | ||
| 118 | int (*resume)(struct soc_camera_device *); | ||
| 114 | int (*init)(struct soc_camera_device *); | 119 | int (*init)(struct soc_camera_device *); |
| 115 | int (*release)(struct soc_camera_device *); | 120 | int (*release)(struct soc_camera_device *); |
| 116 | int (*start_capture)(struct soc_camera_device *); | 121 | int (*start_capture)(struct soc_camera_device *); |
diff --git a/include/net/request_sock.h b/include/net/request_sock.h index 8d6e991ef4df..cac811e51f6d 100644 --- a/include/net/request_sock.h +++ b/include/net/request_sock.h | |||
| @@ -33,7 +33,7 @@ struct request_sock_ops { | |||
| 33 | struct kmem_cache *slab; | 33 | struct kmem_cache *slab; |
| 34 | int (*rtx_syn_ack)(struct sock *sk, | 34 | int (*rtx_syn_ack)(struct sock *sk, |
| 35 | struct request_sock *req); | 35 | struct request_sock *req); |
| 36 | void (*send_ack)(struct sk_buff *skb, | 36 | void (*send_ack)(struct sock *sk, struct sk_buff *skb, |
| 37 | struct request_sock *req); | 37 | struct request_sock *req); |
| 38 | void (*send_reset)(struct sock *sk, | 38 | void (*send_reset)(struct sock *sk, |
| 39 | struct sk_buff *skb); | 39 | struct sk_buff *skb); |
diff --git a/include/net/syncppp.h b/include/net/syncppp.h index e43f4070d892..9e306f7f579a 100644 --- a/include/net/syncppp.h +++ b/include/net/syncppp.h | |||
| @@ -43,8 +43,6 @@ struct sppp | |||
| 43 | u32 pp_rseq; /* remote sequence number */ | 43 | u32 pp_rseq; /* remote sequence number */ |
| 44 | struct slcp lcp; /* LCP params */ | 44 | struct slcp lcp; /* LCP params */ |
| 45 | struct sipcp ipcp; /* IPCP params */ | 45 | struct sipcp ipcp; /* IPCP params */ |
| 46 | u32 ibytes,obytes; /* Bytes in/out */ | ||
| 47 | u32 ipkts,opkts; /* Packets in/out */ | ||
| 48 | struct timer_list pp_timer; | 46 | struct timer_list pp_timer; |
| 49 | struct net_device *pp_if; | 47 | struct net_device *pp_if; |
| 50 | char pp_link_state; /* Link status */ | 48 | char pp_link_state; /* Link status */ |
diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h index df7faf09d66f..c6b2962315b3 100644 --- a/include/rdma/rdma_cm.h +++ b/include/rdma/rdma_cm.h | |||
| @@ -71,12 +71,8 @@ enum rdma_port_space { | |||
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| 73 | struct rdma_addr { | 73 | struct rdma_addr { |
| 74 | struct sockaddr src_addr; | 74 | struct sockaddr_storage src_addr; |
| 75 | u8 src_pad[sizeof(struct sockaddr_in6) - | 75 | struct sockaddr_storage dst_addr; |
| 76 | sizeof(struct sockaddr)]; | ||
| 77 | struct sockaddr dst_addr; | ||
| 78 | u8 dst_pad[sizeof(struct sockaddr_in6) - | ||
| 79 | sizeof(struct sockaddr)]; | ||
| 80 | struct rdma_dev_addr dev_addr; | 76 | struct rdma_dev_addr dev_addr; |
| 81 | }; | 77 | }; |
| 82 | 78 | ||
diff --git a/mm/hugetlb.c b/mm/hugetlb.c index 28a2980ee435..757ca983fd99 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #include <linux/mutex.h> | 17 | #include <linux/mutex.h> |
| 18 | #include <linux/bootmem.h> | 18 | #include <linux/bootmem.h> |
| 19 | #include <linux/sysfs.h> | 19 | #include <linux/sysfs.h> |
| 20 | #include <asm/io.h> | 20 | |
| 21 | #include <asm/page.h> | 21 | #include <asm/page.h> |
| 22 | #include <asm/pgtable.h> | 22 | #include <asm/pgtable.h> |
| 23 | #include <asm/io.h> | 23 | #include <asm/io.h> |
diff --git a/net/bluetooth/bnep/core.c b/net/bluetooth/bnep/core.c index 021172c0e666..12bba6207a8d 100644 --- a/net/bluetooth/bnep/core.c +++ b/net/bluetooth/bnep/core.c | |||
| @@ -57,7 +57,10 @@ | |||
| 57 | #define BT_DBG(D...) | 57 | #define BT_DBG(D...) |
| 58 | #endif | 58 | #endif |
| 59 | 59 | ||
| 60 | #define VERSION "1.2" | 60 | #define VERSION "1.3" |
| 61 | |||
| 62 | static int compress_src = 1; | ||
| 63 | static int compress_dst = 1; | ||
| 61 | 64 | ||
| 62 | static LIST_HEAD(bnep_session_list); | 65 | static LIST_HEAD(bnep_session_list); |
| 63 | static DECLARE_RWSEM(bnep_session_sem); | 66 | static DECLARE_RWSEM(bnep_session_sem); |
| @@ -418,10 +421,10 @@ static inline int bnep_tx_frame(struct bnep_session *s, struct sk_buff *skb) | |||
| 418 | iv[il++] = (struct kvec) { &type, 1 }; | 421 | iv[il++] = (struct kvec) { &type, 1 }; |
| 419 | len++; | 422 | len++; |
| 420 | 423 | ||
| 421 | if (!compare_ether_addr(eh->h_dest, s->eh.h_source)) | 424 | if (compress_src && !compare_ether_addr(eh->h_dest, s->eh.h_source)) |
| 422 | type |= 0x01; | 425 | type |= 0x01; |
| 423 | 426 | ||
| 424 | if (!compare_ether_addr(eh->h_source, s->eh.h_dest)) | 427 | if (compress_dst && !compare_ether_addr(eh->h_source, s->eh.h_dest)) |
| 425 | type |= 0x02; | 428 | type |= 0x02; |
| 426 | 429 | ||
| 427 | if (type) | 430 | if (type) |
| @@ -727,6 +730,12 @@ static void __exit bnep_exit(void) | |||
| 727 | module_init(bnep_init); | 730 | module_init(bnep_init); |
| 728 | module_exit(bnep_exit); | 731 | module_exit(bnep_exit); |
| 729 | 732 | ||
| 733 | module_param(compress_src, bool, 0644); | ||
| 734 | MODULE_PARM_DESC(compress_src, "Compress sources headers"); | ||
| 735 | |||
| 736 | module_param(compress_dst, bool, 0644); | ||
| 737 | MODULE_PARM_DESC(compress_dst, "Compress destination headers"); | ||
| 738 | |||
| 730 | MODULE_AUTHOR("David Libault <david.libault@inventel.fr>, Maxim Krasnyansky <maxk@qualcomm.com>"); | 739 | MODULE_AUTHOR("David Libault <david.libault@inventel.fr>, Maxim Krasnyansky <maxk@qualcomm.com>"); |
| 731 | MODULE_DESCRIPTION("Bluetooth BNEP ver " VERSION); | 740 | MODULE_DESCRIPTION("Bluetooth BNEP ver " VERSION); |
| 732 | MODULE_VERSION(VERSION); | 741 | MODULE_VERSION(VERSION); |
diff --git a/net/core/dev.c b/net/core/dev.c index 01993ad74e76..600bb23c4c2e 100644 --- a/net/core/dev.c +++ b/net/core/dev.c | |||
| @@ -1939,22 +1939,6 @@ int netif_rx_ni(struct sk_buff *skb) | |||
| 1939 | 1939 | ||
| 1940 | EXPORT_SYMBOL(netif_rx_ni); | 1940 | EXPORT_SYMBOL(netif_rx_ni); |
| 1941 | 1941 | ||
| 1942 | static inline struct net_device *skb_bond(struct sk_buff *skb) | ||
| 1943 | { | ||
| 1944 | struct net_device *dev = skb->dev; | ||
| 1945 | |||
| 1946 | if (dev->master) { | ||
| 1947 | if (skb_bond_should_drop(skb)) { | ||
| 1948 | kfree_skb(skb); | ||
| 1949 | return NULL; | ||
| 1950 | } | ||
| 1951 | skb->dev = dev->master; | ||
| 1952 | } | ||
| 1953 | |||
| 1954 | return dev; | ||
| 1955 | } | ||
| 1956 | |||
| 1957 | |||
| 1958 | static void net_tx_action(struct softirq_action *h) | 1942 | static void net_tx_action(struct softirq_action *h) |
| 1959 | { | 1943 | { |
| 1960 | struct softnet_data *sd = &__get_cpu_var(softnet_data); | 1944 | struct softnet_data *sd = &__get_cpu_var(softnet_data); |
| @@ -2181,6 +2165,7 @@ int netif_receive_skb(struct sk_buff *skb) | |||
| 2181 | { | 2165 | { |
| 2182 | struct packet_type *ptype, *pt_prev; | 2166 | struct packet_type *ptype, *pt_prev; |
| 2183 | struct net_device *orig_dev; | 2167 | struct net_device *orig_dev; |
| 2168 | struct net_device *null_or_orig; | ||
| 2184 | int ret = NET_RX_DROP; | 2169 | int ret = NET_RX_DROP; |
| 2185 | __be16 type; | 2170 | __be16 type; |
| 2186 | 2171 | ||
| @@ -2194,10 +2179,14 @@ int netif_receive_skb(struct sk_buff *skb) | |||
| 2194 | if (!skb->iif) | 2179 | if (!skb->iif) |
| 2195 | skb->iif = skb->dev->ifindex; | 2180 | skb->iif = skb->dev->ifindex; |
| 2196 | 2181 | ||
| 2197 | orig_dev = skb_bond(skb); | 2182 | null_or_orig = NULL; |
| 2198 | 2183 | orig_dev = skb->dev; | |
| 2199 | if (!orig_dev) | 2184 | if (orig_dev->master) { |
| 2200 | return NET_RX_DROP; | 2185 | if (skb_bond_should_drop(skb)) |
| 2186 | null_or_orig = orig_dev; /* deliver only exact match */ | ||
| 2187 | else | ||
| 2188 | skb->dev = orig_dev->master; | ||
| 2189 | } | ||
| 2201 | 2190 | ||
| 2202 | __get_cpu_var(netdev_rx_stat).total++; | 2191 | __get_cpu_var(netdev_rx_stat).total++; |
| 2203 | 2192 | ||
| @@ -2221,7 +2210,8 @@ int netif_receive_skb(struct sk_buff *skb) | |||
| 2221 | #endif | 2210 | #endif |
| 2222 | 2211 | ||
| 2223 | list_for_each_entry_rcu(ptype, &ptype_all, list) { | 2212 | list_for_each_entry_rcu(ptype, &ptype_all, list) { |
| 2224 | if (!ptype->dev || ptype->dev == skb->dev) { | 2213 | if (ptype->dev == null_or_orig || ptype->dev == skb->dev || |
| 2214 | ptype->dev == orig_dev) { | ||
| 2225 | if (pt_prev) | 2215 | if (pt_prev) |
| 2226 | ret = deliver_skb(skb, pt_prev, orig_dev); | 2216 | ret = deliver_skb(skb, pt_prev, orig_dev); |
| 2227 | pt_prev = ptype; | 2217 | pt_prev = ptype; |
| @@ -2246,7 +2236,8 @@ ncls: | |||
| 2246 | list_for_each_entry_rcu(ptype, | 2236 | list_for_each_entry_rcu(ptype, |
| 2247 | &ptype_base[ntohs(type) & PTYPE_HASH_MASK], list) { | 2237 | &ptype_base[ntohs(type) & PTYPE_HASH_MASK], list) { |
| 2248 | if (ptype->type == type && | 2238 | if (ptype->type == type && |
| 2249 | (!ptype->dev || ptype->dev == skb->dev)) { | 2239 | (ptype->dev == null_or_orig || ptype->dev == skb->dev || |
| 2240 | ptype->dev == orig_dev)) { | ||
| 2250 | if (pt_prev) | 2241 | if (pt_prev) |
| 2251 | ret = deliver_skb(skb, pt_prev, orig_dev); | 2242 | ret = deliver_skb(skb, pt_prev, orig_dev); |
| 2252 | pt_prev = ptype; | 2243 | pt_prev = ptype; |
diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 2498cdaf8cbe..526236453908 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c | |||
| @@ -168,7 +168,7 @@ | |||
| 168 | #include <asm/div64.h> /* do_div */ | 168 | #include <asm/div64.h> /* do_div */ |
| 169 | #include <asm/timex.h> | 169 | #include <asm/timex.h> |
| 170 | 170 | ||
| 171 | #define VERSION "pktgen v2.69: Packet Generator for packet performance testing.\n" | 171 | #define VERSION "pktgen v2.70: Packet Generator for packet performance testing.\n" |
| 172 | 172 | ||
| 173 | #define IP_NAME_SZ 32 | 173 | #define IP_NAME_SZ 32 |
| 174 | #define MAX_MPLS_LABELS 16 /* This is the max label stack depth */ | 174 | #define MAX_MPLS_LABELS 16 /* This is the max label stack depth */ |
| @@ -189,6 +189,7 @@ | |||
| 189 | #define F_FLOW_SEQ (1<<11) /* Sequential flows */ | 189 | #define F_FLOW_SEQ (1<<11) /* Sequential flows */ |
| 190 | #define F_IPSEC_ON (1<<12) /* ipsec on for flows */ | 190 | #define F_IPSEC_ON (1<<12) /* ipsec on for flows */ |
| 191 | #define F_QUEUE_MAP_RND (1<<13) /* queue map Random */ | 191 | #define F_QUEUE_MAP_RND (1<<13) /* queue map Random */ |
| 192 | #define F_QUEUE_MAP_CPU (1<<14) /* queue map mirrors smp_processor_id() */ | ||
| 192 | 193 | ||
| 193 | /* Thread control flag bits */ | 194 | /* Thread control flag bits */ |
| 194 | #define T_TERMINATE (1<<0) | 195 | #define T_TERMINATE (1<<0) |
| @@ -621,6 +622,9 @@ static int pktgen_if_show(struct seq_file *seq, void *v) | |||
| 621 | if (pkt_dev->flags & F_QUEUE_MAP_RND) | 622 | if (pkt_dev->flags & F_QUEUE_MAP_RND) |
| 622 | seq_printf(seq, "QUEUE_MAP_RND "); | 623 | seq_printf(seq, "QUEUE_MAP_RND "); |
| 623 | 624 | ||
| 625 | if (pkt_dev->flags & F_QUEUE_MAP_CPU) | ||
| 626 | seq_printf(seq, "QUEUE_MAP_CPU "); | ||
| 627 | |||
| 624 | if (pkt_dev->cflows) { | 628 | if (pkt_dev->cflows) { |
| 625 | if (pkt_dev->flags & F_FLOW_SEQ) | 629 | if (pkt_dev->flags & F_FLOW_SEQ) |
| 626 | seq_printf(seq, "FLOW_SEQ "); /*in sequence flows*/ | 630 | seq_printf(seq, "FLOW_SEQ "); /*in sequence flows*/ |
| @@ -1134,6 +1138,12 @@ static ssize_t pktgen_if_write(struct file *file, | |||
| 1134 | 1138 | ||
| 1135 | else if (strcmp(f, "!QUEUE_MAP_RND") == 0) | 1139 | else if (strcmp(f, "!QUEUE_MAP_RND") == 0) |
| 1136 | pkt_dev->flags &= ~F_QUEUE_MAP_RND; | 1140 | pkt_dev->flags &= ~F_QUEUE_MAP_RND; |
| 1141 | |||
| 1142 | else if (strcmp(f, "QUEUE_MAP_CPU") == 0) | ||
| 1143 | pkt_dev->flags |= F_QUEUE_MAP_CPU; | ||
| 1144 | |||
| 1145 | else if (strcmp(f, "!QUEUE_MAP_CPU") == 0) | ||
| 1146 | pkt_dev->flags &= ~F_QUEUE_MAP_CPU; | ||
| 1137 | #ifdef CONFIG_XFRM | 1147 | #ifdef CONFIG_XFRM |
| 1138 | else if (strcmp(f, "IPSEC") == 0) | 1148 | else if (strcmp(f, "IPSEC") == 0) |
| 1139 | pkt_dev->flags |= F_IPSEC_ON; | 1149 | pkt_dev->flags |= F_IPSEC_ON; |
| @@ -1895,6 +1905,23 @@ static int pktgen_device_event(struct notifier_block *unused, | |||
| 1895 | return NOTIFY_DONE; | 1905 | return NOTIFY_DONE; |
| 1896 | } | 1906 | } |
| 1897 | 1907 | ||
| 1908 | static struct net_device *pktgen_dev_get_by_name(struct pktgen_dev *pkt_dev, const char *ifname) | ||
| 1909 | { | ||
| 1910 | char b[IFNAMSIZ+5]; | ||
| 1911 | int i = 0; | ||
| 1912 | |||
| 1913 | for(i=0; ifname[i] != '@'; i++) { | ||
| 1914 | if(i == IFNAMSIZ) | ||
| 1915 | break; | ||
| 1916 | |||
| 1917 | b[i] = ifname[i]; | ||
| 1918 | } | ||
| 1919 | b[i] = 0; | ||
| 1920 | |||
| 1921 | return dev_get_by_name(&init_net, b); | ||
| 1922 | } | ||
| 1923 | |||
| 1924 | |||
| 1898 | /* Associate pktgen_dev with a device. */ | 1925 | /* Associate pktgen_dev with a device. */ |
| 1899 | 1926 | ||
| 1900 | static int pktgen_setup_dev(struct pktgen_dev *pkt_dev, const char *ifname) | 1927 | static int pktgen_setup_dev(struct pktgen_dev *pkt_dev, const char *ifname) |
| @@ -1908,7 +1935,7 @@ static int pktgen_setup_dev(struct pktgen_dev *pkt_dev, const char *ifname) | |||
| 1908 | pkt_dev->odev = NULL; | 1935 | pkt_dev->odev = NULL; |
| 1909 | } | 1936 | } |
| 1910 | 1937 | ||
| 1911 | odev = dev_get_by_name(&init_net, ifname); | 1938 | odev = pktgen_dev_get_by_name(pkt_dev, ifname); |
| 1912 | if (!odev) { | 1939 | if (!odev) { |
| 1913 | printk(KERN_ERR "pktgen: no such netdevice: \"%s\"\n", ifname); | 1940 | printk(KERN_ERR "pktgen: no such netdevice: \"%s\"\n", ifname); |
| 1914 | return -ENODEV; | 1941 | return -ENODEV; |
| @@ -2129,7 +2156,11 @@ static void get_ipsec_sa(struct pktgen_dev *pkt_dev, int flow) | |||
| 2129 | #endif | 2156 | #endif |
| 2130 | static void set_cur_queue_map(struct pktgen_dev *pkt_dev) | 2157 | static void set_cur_queue_map(struct pktgen_dev *pkt_dev) |
| 2131 | { | 2158 | { |
| 2132 | if (pkt_dev->queue_map_min < pkt_dev->queue_map_max) { | 2159 | |
| 2160 | if (pkt_dev->flags & F_QUEUE_MAP_CPU) | ||
| 2161 | pkt_dev->cur_queue_map = smp_processor_id(); | ||
| 2162 | |||
| 2163 | else if (pkt_dev->queue_map_min < pkt_dev->queue_map_max) { | ||
| 2133 | __u16 t; | 2164 | __u16 t; |
| 2134 | if (pkt_dev->flags & F_QUEUE_MAP_RND) { | 2165 | if (pkt_dev->flags & F_QUEUE_MAP_RND) { |
| 2135 | t = random32() % | 2166 | t = random32() % |
diff --git a/net/dccp/dccp.h b/net/dccp/dccp.h index 1c2e3ec2eb57..b4bc6e095a0e 100644 --- a/net/dccp/dccp.h +++ b/net/dccp/dccp.h | |||
| @@ -229,7 +229,8 @@ extern void dccp_v4_send_check(struct sock *sk, int len, struct sk_buff *skb); | |||
| 229 | extern int dccp_retransmit_skb(struct sock *sk); | 229 | extern int dccp_retransmit_skb(struct sock *sk); |
| 230 | 230 | ||
| 231 | extern void dccp_send_ack(struct sock *sk); | 231 | extern void dccp_send_ack(struct sock *sk); |
| 232 | extern void dccp_reqsk_send_ack(struct sk_buff *sk, struct request_sock *rsk); | 232 | extern void dccp_reqsk_send_ack(struct sock *sk, struct sk_buff *skb, |
| 233 | struct request_sock *rsk); | ||
| 233 | 234 | ||
| 234 | extern void dccp_send_sync(struct sock *sk, const u64 seq, | 235 | extern void dccp_send_sync(struct sock *sk, const u64 seq, |
| 235 | const enum dccp_pkt_type pkt_type); | 236 | const enum dccp_pkt_type pkt_type); |
diff --git a/net/dccp/minisocks.c b/net/dccp/minisocks.c index 66dca5bba858..b2804e2d1b8c 100644 --- a/net/dccp/minisocks.c +++ b/net/dccp/minisocks.c | |||
| @@ -296,7 +296,8 @@ int dccp_child_process(struct sock *parent, struct sock *child, | |||
| 296 | 296 | ||
| 297 | EXPORT_SYMBOL_GPL(dccp_child_process); | 297 | EXPORT_SYMBOL_GPL(dccp_child_process); |
| 298 | 298 | ||
| 299 | void dccp_reqsk_send_ack(struct sk_buff *skb, struct request_sock *rsk) | 299 | void dccp_reqsk_send_ack(struct sock *sk, struct sk_buff *skb, |
| 300 | struct request_sock *rsk) | ||
| 300 | { | 301 | { |
| 301 | DCCP_BUG("DCCP-ACK packets are never sent in LISTEN/RESPOND state"); | 302 | DCCP_BUG("DCCP-ACK packets are never sent in LISTEN/RESPOND state"); |
| 302 | } | 303 | } |
diff --git a/net/ipv4/esp4.c b/net/ipv4/esp4.c index 4e73e5708e70..21515d4c49eb 100644 --- a/net/ipv4/esp4.c +++ b/net/ipv4/esp4.c | |||
| @@ -575,7 +575,7 @@ static int esp_init_state(struct xfrm_state *x) | |||
| 575 | crypto_aead_ivsize(aead); | 575 | crypto_aead_ivsize(aead); |
| 576 | if (x->props.mode == XFRM_MODE_TUNNEL) | 576 | if (x->props.mode == XFRM_MODE_TUNNEL) |
| 577 | x->props.header_len += sizeof(struct iphdr); | 577 | x->props.header_len += sizeof(struct iphdr); |
| 578 | else if (x->props.mode == XFRM_MODE_BEET) | 578 | else if (x->props.mode == XFRM_MODE_BEET && x->sel.family != AF_INET6) |
| 579 | x->props.header_len += IPV4_BEET_PHMAXLEN; | 579 | x->props.header_len += IPV4_BEET_PHMAXLEN; |
| 580 | if (x->encap) { | 580 | if (x->encap) { |
| 581 | struct xfrm_encap_tmpl *encap = x->encap; | 581 | struct xfrm_encap_tmpl *encap = x->encap; |
diff --git a/net/ipv4/route.c b/net/ipv4/route.c index 1bfa078ddbd0..16fc6f454a31 100644 --- a/net/ipv4/route.c +++ b/net/ipv4/route.c | |||
| @@ -1509,14 +1509,14 @@ unsigned short ip_rt_frag_needed(struct net *net, struct iphdr *iph, | |||
| 1509 | 1509 | ||
| 1510 | /* BSD 4.2 compatibility hack :-( */ | 1510 | /* BSD 4.2 compatibility hack :-( */ |
| 1511 | if (mtu == 0 && | 1511 | if (mtu == 0 && |
| 1512 | old_mtu >= dst_metric(&rth->u.dst, RTAX_MTU) && | 1512 | old_mtu >= dst_mtu(&rth->u.dst) && |
| 1513 | old_mtu >= 68 + (iph->ihl << 2)) | 1513 | old_mtu >= 68 + (iph->ihl << 2)) |
| 1514 | old_mtu -= iph->ihl << 2; | 1514 | old_mtu -= iph->ihl << 2; |
| 1515 | 1515 | ||
| 1516 | mtu = guess_mtu(old_mtu); | 1516 | mtu = guess_mtu(old_mtu); |
| 1517 | } | 1517 | } |
| 1518 | if (mtu <= dst_metric(&rth->u.dst, RTAX_MTU)) { | 1518 | if (mtu <= dst_mtu(&rth->u.dst)) { |
| 1519 | if (mtu < dst_metric(&rth->u.dst, RTAX_MTU)) { | 1519 | if (mtu < dst_mtu(&rth->u.dst)) { |
| 1520 | dst_confirm(&rth->u.dst); | 1520 | dst_confirm(&rth->u.dst); |
| 1521 | if (mtu < ip_rt_min_pmtu) { | 1521 | if (mtu < ip_rt_min_pmtu) { |
| 1522 | mtu = ip_rt_min_pmtu; | 1522 | mtu = ip_rt_min_pmtu; |
| @@ -1538,7 +1538,7 @@ unsigned short ip_rt_frag_needed(struct net *net, struct iphdr *iph, | |||
| 1538 | 1538 | ||
| 1539 | static void ip_rt_update_pmtu(struct dst_entry *dst, u32 mtu) | 1539 | static void ip_rt_update_pmtu(struct dst_entry *dst, u32 mtu) |
| 1540 | { | 1540 | { |
| 1541 | if (dst_metric(dst, RTAX_MTU) > mtu && mtu >= 68 && | 1541 | if (dst_mtu(dst) > mtu && mtu >= 68 && |
| 1542 | !(dst_metric_locked(dst, RTAX_MTU))) { | 1542 | !(dst_metric_locked(dst, RTAX_MTU))) { |
| 1543 | if (mtu < ip_rt_min_pmtu) { | 1543 | if (mtu < ip_rt_min_pmtu) { |
| 1544 | mtu = ip_rt_min_pmtu; | 1544 | mtu = ip_rt_min_pmtu; |
| @@ -1667,7 +1667,7 @@ static void rt_set_nexthop(struct rtable *rt, struct fib_result *res, u32 itag) | |||
| 1667 | 1667 | ||
| 1668 | if (dst_metric(&rt->u.dst, RTAX_HOPLIMIT) == 0) | 1668 | if (dst_metric(&rt->u.dst, RTAX_HOPLIMIT) == 0) |
| 1669 | rt->u.dst.metrics[RTAX_HOPLIMIT-1] = sysctl_ip_default_ttl; | 1669 | rt->u.dst.metrics[RTAX_HOPLIMIT-1] = sysctl_ip_default_ttl; |
| 1670 | if (dst_metric(&rt->u.dst, RTAX_MTU) > IP_MAX_MTU) | 1670 | if (dst_mtu(&rt->u.dst) > IP_MAX_MTU) |
| 1671 | rt->u.dst.metrics[RTAX_MTU-1] = IP_MAX_MTU; | 1671 | rt->u.dst.metrics[RTAX_MTU-1] = IP_MAX_MTU; |
| 1672 | if (dst_metric(&rt->u.dst, RTAX_ADVMSS) == 0) | 1672 | if (dst_metric(&rt->u.dst, RTAX_ADVMSS) == 0) |
| 1673 | rt->u.dst.metrics[RTAX_ADVMSS-1] = max_t(unsigned int, rt->u.dst.dev->mtu - 40, | 1673 | rt->u.dst.metrics[RTAX_ADVMSS-1] = max_t(unsigned int, rt->u.dst.dev->mtu - 40, |
| @@ -3223,9 +3223,7 @@ int __init ip_rt_init(void) | |||
| 3223 | */ | 3223 | */ |
| 3224 | void __init ip_static_sysctl_init(void) | 3224 | void __init ip_static_sysctl_init(void) |
| 3225 | { | 3225 | { |
| 3226 | #ifdef CONFIG_SYSCTL | ||
| 3227 | register_sysctl_paths(ipv4_route_path, ipv4_route_table); | 3226 | register_sysctl_paths(ipv4_route_path, ipv4_route_table); |
| 3228 | #endif | ||
| 3229 | } | 3227 | } |
| 3230 | #endif | 3228 | #endif |
| 3231 | 3229 | ||
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 91a8cfddf1c4..44c1e934824b 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c | |||
| @@ -687,14 +687,14 @@ static void tcp_v4_timewait_ack(struct sock *sk, struct sk_buff *skb) | |||
| 687 | inet_twsk_put(tw); | 687 | inet_twsk_put(tw); |
| 688 | } | 688 | } |
| 689 | 689 | ||
| 690 | static void tcp_v4_reqsk_send_ack(struct sk_buff *skb, | 690 | static void tcp_v4_reqsk_send_ack(struct sock *sk, struct sk_buff *skb, |
| 691 | struct request_sock *req) | 691 | struct request_sock *req) |
| 692 | { | 692 | { |
| 693 | tcp_v4_send_ack(skb, tcp_rsk(req)->snt_isn + 1, | 693 | tcp_v4_send_ack(skb, tcp_rsk(req)->snt_isn + 1, |
| 694 | tcp_rsk(req)->rcv_isn + 1, req->rcv_wnd, | 694 | tcp_rsk(req)->rcv_isn + 1, req->rcv_wnd, |
| 695 | req->ts_recent, | 695 | req->ts_recent, |
| 696 | 0, | 696 | 0, |
| 697 | tcp_v4_md5_do_lookup(skb->sk, ip_hdr(skb)->daddr)); | 697 | tcp_v4_md5_do_lookup(sk, ip_hdr(skb)->daddr)); |
| 698 | } | 698 | } |
| 699 | 699 | ||
| 700 | /* | 700 | /* |
diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c index 204c42162660..f976fc57892c 100644 --- a/net/ipv4/tcp_minisocks.c +++ b/net/ipv4/tcp_minisocks.c | |||
| @@ -609,7 +609,7 @@ struct sock *tcp_check_req(struct sock *sk,struct sk_buff *skb, | |||
| 609 | tcp_rsk(req)->rcv_isn + 1, tcp_rsk(req)->rcv_isn + 1 + req->rcv_wnd)) { | 609 | tcp_rsk(req)->rcv_isn + 1, tcp_rsk(req)->rcv_isn + 1 + req->rcv_wnd)) { |
| 610 | /* Out of window: send ACK and drop. */ | 610 | /* Out of window: send ACK and drop. */ |
| 611 | if (!(flg & TCP_FLAG_RST)) | 611 | if (!(flg & TCP_FLAG_RST)) |
| 612 | req->rsk_ops->send_ack(skb, req); | 612 | req->rsk_ops->send_ack(sk, skb, req); |
| 613 | if (paws_reject) | 613 | if (paws_reject) |
| 614 | NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_PAWSESTABREJECTED); | 614 | NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_PAWSESTABREJECTED); |
| 615 | return NULL; | 615 | return NULL; |
| @@ -618,89 +618,87 @@ struct sock *tcp_check_req(struct sock *sk,struct sk_buff *skb, | |||
| 618 | /* In sequence, PAWS is OK. */ | 618 | /* In sequence, PAWS is OK. */ |
| 619 | 619 | ||
| 620 | if (tmp_opt.saw_tstamp && !after(TCP_SKB_CB(skb)->seq, tcp_rsk(req)->rcv_isn + 1)) | 620 | if (tmp_opt.saw_tstamp && !after(TCP_SKB_CB(skb)->seq, tcp_rsk(req)->rcv_isn + 1)) |
| 621 | req->ts_recent = tmp_opt.rcv_tsval; | 621 | req->ts_recent = tmp_opt.rcv_tsval; |
| 622 | 622 | ||
| 623 | if (TCP_SKB_CB(skb)->seq == tcp_rsk(req)->rcv_isn) { | 623 | if (TCP_SKB_CB(skb)->seq == tcp_rsk(req)->rcv_isn) { |
| 624 | /* Truncate SYN, it is out of window starting | 624 | /* Truncate SYN, it is out of window starting |
| 625 | at tcp_rsk(req)->rcv_isn + 1. */ | 625 | at tcp_rsk(req)->rcv_isn + 1. */ |
| 626 | flg &= ~TCP_FLAG_SYN; | 626 | flg &= ~TCP_FLAG_SYN; |
| 627 | } | 627 | } |
| 628 | 628 | ||
| 629 | /* RFC793: "second check the RST bit" and | 629 | /* RFC793: "second check the RST bit" and |
| 630 | * "fourth, check the SYN bit" | 630 | * "fourth, check the SYN bit" |
| 631 | */ | 631 | */ |
| 632 | if (flg & (TCP_FLAG_RST|TCP_FLAG_SYN)) { | 632 | if (flg & (TCP_FLAG_RST|TCP_FLAG_SYN)) { |
| 633 | TCP_INC_STATS_BH(sock_net(sk), TCP_MIB_ATTEMPTFAILS); | 633 | TCP_INC_STATS_BH(sock_net(sk), TCP_MIB_ATTEMPTFAILS); |
| 634 | goto embryonic_reset; | 634 | goto embryonic_reset; |
| 635 | } | 635 | } |
| 636 | 636 | ||
| 637 | /* ACK sequence verified above, just make sure ACK is | 637 | /* ACK sequence verified above, just make sure ACK is |
| 638 | * set. If ACK not set, just silently drop the packet. | 638 | * set. If ACK not set, just silently drop the packet. |
| 639 | */ | 639 | */ |
| 640 | if (!(flg & TCP_FLAG_ACK)) | 640 | if (!(flg & TCP_FLAG_ACK)) |
| 641 | return NULL; | 641 | return NULL; |
| 642 | |||
| 643 | /* If TCP_DEFER_ACCEPT is set, drop bare ACK. */ | ||
| 644 | if (inet_csk(sk)->icsk_accept_queue.rskq_defer_accept && | ||
| 645 | TCP_SKB_CB(skb)->end_seq == tcp_rsk(req)->rcv_isn + 1) { | ||
| 646 | inet_rsk(req)->acked = 1; | ||
| 647 | return NULL; | ||
| 648 | } | ||
| 649 | 642 | ||
| 650 | /* OK, ACK is valid, create big socket and | 643 | /* If TCP_DEFER_ACCEPT is set, drop bare ACK. */ |
| 651 | * feed this segment to it. It will repeat all | 644 | if (inet_csk(sk)->icsk_accept_queue.rskq_defer_accept && |
| 652 | * the tests. THIS SEGMENT MUST MOVE SOCKET TO | 645 | TCP_SKB_CB(skb)->end_seq == tcp_rsk(req)->rcv_isn + 1) { |
| 653 | * ESTABLISHED STATE. If it will be dropped after | 646 | inet_rsk(req)->acked = 1; |
| 654 | * socket is created, wait for troubles. | 647 | return NULL; |
| 655 | */ | 648 | } |
| 656 | child = inet_csk(sk)->icsk_af_ops->syn_recv_sock(sk, skb, | 649 | |
| 657 | req, NULL); | 650 | /* OK, ACK is valid, create big socket and |
| 658 | if (child == NULL) | 651 | * feed this segment to it. It will repeat all |
| 659 | goto listen_overflow; | 652 | * the tests. THIS SEGMENT MUST MOVE SOCKET TO |
| 653 | * ESTABLISHED STATE. If it will be dropped after | ||
| 654 | * socket is created, wait for troubles. | ||
| 655 | */ | ||
| 656 | child = inet_csk(sk)->icsk_af_ops->syn_recv_sock(sk, skb, req, NULL); | ||
| 657 | if (child == NULL) | ||
| 658 | goto listen_overflow; | ||
| 660 | #ifdef CONFIG_TCP_MD5SIG | 659 | #ifdef CONFIG_TCP_MD5SIG |
| 661 | else { | 660 | else { |
| 662 | /* Copy over the MD5 key from the original socket */ | 661 | /* Copy over the MD5 key from the original socket */ |
| 663 | struct tcp_md5sig_key *key; | 662 | struct tcp_md5sig_key *key; |
| 664 | struct tcp_sock *tp = tcp_sk(sk); | 663 | struct tcp_sock *tp = tcp_sk(sk); |
| 665 | key = tp->af_specific->md5_lookup(sk, child); | 664 | key = tp->af_specific->md5_lookup(sk, child); |
| 666 | if (key != NULL) { | 665 | if (key != NULL) { |
| 667 | /* | 666 | /* |
| 668 | * We're using one, so create a matching key on the | 667 | * We're using one, so create a matching key on the |
| 669 | * newsk structure. If we fail to get memory then we | 668 | * newsk structure. If we fail to get memory then we |
| 670 | * end up not copying the key across. Shucks. | 669 | * end up not copying the key across. Shucks. |
| 671 | */ | 670 | */ |
| 672 | char *newkey = kmemdup(key->key, key->keylen, | 671 | char *newkey = kmemdup(key->key, key->keylen, |
| 673 | GFP_ATOMIC); | 672 | GFP_ATOMIC); |
| 674 | if (newkey) { | 673 | if (newkey) { |
| 675 | if (!tcp_alloc_md5sig_pool()) | 674 | if (!tcp_alloc_md5sig_pool()) |
| 676 | BUG(); | 675 | BUG(); |
| 677 | tp->af_specific->md5_add(child, child, | 676 | tp->af_specific->md5_add(child, child, newkey, |
| 678 | newkey, | 677 | key->keylen); |
| 679 | key->keylen); | ||
| 680 | } | ||
| 681 | } | 678 | } |
| 682 | } | 679 | } |
| 680 | } | ||
| 683 | #endif | 681 | #endif |
| 684 | 682 | ||
| 685 | inet_csk_reqsk_queue_unlink(sk, req, prev); | 683 | inet_csk_reqsk_queue_unlink(sk, req, prev); |
| 686 | inet_csk_reqsk_queue_removed(sk, req); | 684 | inet_csk_reqsk_queue_removed(sk, req); |
| 687 | 685 | ||
| 688 | inet_csk_reqsk_queue_add(sk, req, child); | 686 | inet_csk_reqsk_queue_add(sk, req, child); |
| 689 | return child; | 687 | return child; |
| 690 | 688 | ||
| 691 | listen_overflow: | 689 | listen_overflow: |
| 692 | if (!sysctl_tcp_abort_on_overflow) { | 690 | if (!sysctl_tcp_abort_on_overflow) { |
| 693 | inet_rsk(req)->acked = 1; | 691 | inet_rsk(req)->acked = 1; |
| 694 | return NULL; | 692 | return NULL; |
| 695 | } | 693 | } |
| 696 | 694 | ||
| 697 | embryonic_reset: | 695 | embryonic_reset: |
| 698 | NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_EMBRYONICRSTS); | 696 | NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_EMBRYONICRSTS); |
| 699 | if (!(flg & TCP_FLAG_RST)) | 697 | if (!(flg & TCP_FLAG_RST)) |
| 700 | req->rsk_ops->send_reset(sk, skb); | 698 | req->rsk_ops->send_reset(sk, skb); |
| 701 | 699 | ||
| 702 | inet_csk_reqsk_queue_drop(sk, req, prev); | 700 | inet_csk_reqsk_queue_drop(sk, req, prev); |
| 703 | return NULL; | 701 | return NULL; |
| 704 | } | 702 | } |
| 705 | 703 | ||
| 706 | /* | 704 | /* |
diff --git a/net/ipv4/xfrm4_mode_beet.c b/net/ipv4/xfrm4_mode_beet.c index 9c798abce736..63418185f524 100644 --- a/net/ipv4/xfrm4_mode_beet.c +++ b/net/ipv4/xfrm4_mode_beet.c | |||
| @@ -47,8 +47,10 @@ static int xfrm4_beet_output(struct xfrm_state *x, struct sk_buff *skb) | |||
| 47 | if (unlikely(optlen)) | 47 | if (unlikely(optlen)) |
| 48 | hdrlen += IPV4_BEET_PHMAXLEN - (optlen & 4); | 48 | hdrlen += IPV4_BEET_PHMAXLEN - (optlen & 4); |
| 49 | 49 | ||
| 50 | skb_set_network_header(skb, IPV4_BEET_PHMAXLEN - x->props.header_len - | 50 | skb_set_network_header(skb, -x->props.header_len - |
| 51 | hdrlen); | 51 | hdrlen + (XFRM_MODE_SKB_CB(skb)->ihl - sizeof(*top_iph))); |
| 52 | if (x->sel.family != AF_INET6) | ||
| 53 | skb->network_header += IPV4_BEET_PHMAXLEN; | ||
| 52 | skb->mac_header = skb->network_header + | 54 | skb->mac_header = skb->network_header + |
| 53 | offsetof(struct iphdr, protocol); | 55 | offsetof(struct iphdr, protocol); |
| 54 | skb->transport_header = skb->network_header + sizeof(*top_iph); | 56 | skb->transport_header = skb->network_header + sizeof(*top_iph); |
diff --git a/net/ipv6/esp6.c b/net/ipv6/esp6.c index c6bb4c6d24b3..b181b08fb761 100644 --- a/net/ipv6/esp6.c +++ b/net/ipv6/esp6.c | |||
| @@ -521,6 +521,10 @@ static int esp6_init_state(struct xfrm_state *x) | |||
| 521 | crypto_aead_ivsize(aead); | 521 | crypto_aead_ivsize(aead); |
| 522 | switch (x->props.mode) { | 522 | switch (x->props.mode) { |
| 523 | case XFRM_MODE_BEET: | 523 | case XFRM_MODE_BEET: |
| 524 | if (x->sel.family != AF_INET6) | ||
| 525 | x->props.header_len += IPV4_BEET_PHMAXLEN + | ||
| 526 | (sizeof(struct ipv6hdr) - sizeof(struct iphdr)); | ||
| 527 | break; | ||
| 524 | case XFRM_MODE_TRANSPORT: | 528 | case XFRM_MODE_TRANSPORT: |
| 525 | break; | 529 | break; |
| 526 | case XFRM_MODE_TUNNEL: | 530 | case XFRM_MODE_TUNNEL: |
diff --git a/net/ipv6/route.c b/net/ipv6/route.c index 86540b24b27c..5a3e87e4b18f 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c | |||
| @@ -1249,7 +1249,7 @@ install_route: | |||
| 1249 | 1249 | ||
| 1250 | if (dst_metric(&rt->u.dst, RTAX_HOPLIMIT) == 0) | 1250 | if (dst_metric(&rt->u.dst, RTAX_HOPLIMIT) == 0) |
| 1251 | rt->u.dst.metrics[RTAX_HOPLIMIT-1] = -1; | 1251 | rt->u.dst.metrics[RTAX_HOPLIMIT-1] = -1; |
| 1252 | if (!dst_metric(&rt->u.dst, RTAX_MTU)) | 1252 | if (!dst_mtu(&rt->u.dst)) |
| 1253 | rt->u.dst.metrics[RTAX_MTU-1] = ipv6_get_mtu(dev); | 1253 | rt->u.dst.metrics[RTAX_MTU-1] = ipv6_get_mtu(dev); |
| 1254 | if (!dst_metric(&rt->u.dst, RTAX_ADVMSS)) | 1254 | if (!dst_metric(&rt->u.dst, RTAX_ADVMSS)) |
| 1255 | rt->u.dst.metrics[RTAX_ADVMSS-1] = ipv6_advmss(net, dst_mtu(&rt->u.dst)); | 1255 | rt->u.dst.metrics[RTAX_ADVMSS-1] = ipv6_advmss(net, dst_mtu(&rt->u.dst)); |
diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index 78185a409212..5b90b369ccb2 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c | |||
| @@ -69,7 +69,8 @@ | |||
| 69 | #include <linux/scatterlist.h> | 69 | #include <linux/scatterlist.h> |
| 70 | 70 | ||
| 71 | static void tcp_v6_send_reset(struct sock *sk, struct sk_buff *skb); | 71 | static void tcp_v6_send_reset(struct sock *sk, struct sk_buff *skb); |
| 72 | static void tcp_v6_reqsk_send_ack(struct sk_buff *skb, struct request_sock *req); | 72 | static void tcp_v6_reqsk_send_ack(struct sock *sk, struct sk_buff *skb, |
| 73 | struct request_sock *req); | ||
| 73 | 74 | ||
| 74 | static int tcp_v6_do_rcv(struct sock *sk, struct sk_buff *skb); | 75 | static int tcp_v6_do_rcv(struct sock *sk, struct sk_buff *skb); |
| 75 | 76 | ||
| @@ -1138,10 +1139,11 @@ static void tcp_v6_timewait_ack(struct sock *sk, struct sk_buff *skb) | |||
| 1138 | inet_twsk_put(tw); | 1139 | inet_twsk_put(tw); |
| 1139 | } | 1140 | } |
| 1140 | 1141 | ||
| 1141 | static void tcp_v6_reqsk_send_ack(struct sk_buff *skb, struct request_sock *req) | 1142 | static void tcp_v6_reqsk_send_ack(struct sock *sk, struct sk_buff *skb, |
| 1143 | struct request_sock *req) | ||
| 1142 | { | 1144 | { |
| 1143 | tcp_v6_send_ack(skb, tcp_rsk(req)->snt_isn + 1, tcp_rsk(req)->rcv_isn + 1, req->rcv_wnd, req->ts_recent, | 1145 | tcp_v6_send_ack(skb, tcp_rsk(req)->snt_isn + 1, tcp_rsk(req)->rcv_isn + 1, req->rcv_wnd, req->ts_recent, |
| 1144 | tcp_v6_md5_do_lookup(skb->sk, &ipv6_hdr(skb)->daddr)); | 1146 | tcp_v6_md5_do_lookup(sk, &ipv6_hdr(skb)->daddr)); |
| 1145 | } | 1147 | } |
| 1146 | 1148 | ||
| 1147 | 1149 | ||
diff --git a/net/ipv6/xfrm6_mode_beet.c b/net/ipv6/xfrm6_mode_beet.c index d6ce400f585f..bbd48b101bae 100644 --- a/net/ipv6/xfrm6_mode_beet.c +++ b/net/ipv6/xfrm6_mode_beet.c | |||
| @@ -40,16 +40,39 @@ static void xfrm6_beet_make_header(struct sk_buff *skb) | |||
| 40 | static int xfrm6_beet_output(struct xfrm_state *x, struct sk_buff *skb) | 40 | static int xfrm6_beet_output(struct xfrm_state *x, struct sk_buff *skb) |
| 41 | { | 41 | { |
| 42 | struct ipv6hdr *top_iph; | 42 | struct ipv6hdr *top_iph; |
| 43 | 43 | struct ip_beet_phdr *ph; | |
| 44 | skb_set_network_header(skb, -x->props.header_len); | 44 | struct iphdr *iphv4; |
| 45 | int optlen, hdr_len; | ||
| 46 | |||
| 47 | iphv4 = ip_hdr(skb); | ||
| 48 | hdr_len = 0; | ||
| 49 | optlen = XFRM_MODE_SKB_CB(skb)->optlen; | ||
| 50 | if (unlikely(optlen)) | ||
| 51 | hdr_len += IPV4_BEET_PHMAXLEN - (optlen & 4); | ||
| 52 | |||
| 53 | skb_set_network_header(skb, -x->props.header_len - hdr_len); | ||
| 54 | if (x->sel.family != AF_INET6) | ||
| 55 | skb->network_header += IPV4_BEET_PHMAXLEN; | ||
| 45 | skb->mac_header = skb->network_header + | 56 | skb->mac_header = skb->network_header + |
| 46 | offsetof(struct ipv6hdr, nexthdr); | 57 | offsetof(struct ipv6hdr, nexthdr); |
| 47 | skb->transport_header = skb->network_header + sizeof(*top_iph); | 58 | skb->transport_header = skb->network_header + sizeof(*top_iph); |
| 48 | __skb_pull(skb, XFRM_MODE_SKB_CB(skb)->ihl); | 59 | ph = (struct ip_beet_phdr *)__skb_pull(skb, XFRM_MODE_SKB_CB(skb)->ihl-hdr_len); |
| 49 | 60 | ||
| 50 | xfrm6_beet_make_header(skb); | 61 | xfrm6_beet_make_header(skb); |
| 51 | 62 | ||
| 52 | top_iph = ipv6_hdr(skb); | 63 | top_iph = ipv6_hdr(skb); |
| 64 | if (unlikely(optlen)) { | ||
| 65 | |||
| 66 | BUG_ON(optlen < 0); | ||
| 67 | |||
| 68 | ph->padlen = 4 - (optlen & 4); | ||
| 69 | ph->hdrlen = optlen / 8; | ||
| 70 | ph->nexthdr = top_iph->nexthdr; | ||
| 71 | if (ph->padlen) | ||
| 72 | memset(ph + 1, IPOPT_NOP, ph->padlen); | ||
| 73 | |||
| 74 | top_iph->nexthdr = IPPROTO_BEETPH; | ||
| 75 | } | ||
| 53 | 76 | ||
| 54 | ipv6_addr_copy(&top_iph->saddr, (struct in6_addr *)&x->props.saddr); | 77 | ipv6_addr_copy(&top_iph->saddr, (struct in6_addr *)&x->props.saddr); |
| 55 | ipv6_addr_copy(&top_iph->daddr, (struct in6_addr *)&x->id.daddr); | 78 | ipv6_addr_copy(&top_iph->daddr, (struct in6_addr *)&x->id.daddr); |
diff --git a/net/mac80211/main.c b/net/mac80211/main.c index 0c02c471bca2..aa5a191598c9 100644 --- a/net/mac80211/main.c +++ b/net/mac80211/main.c | |||
| @@ -245,10 +245,13 @@ static int ieee80211_open(struct net_device *dev) | |||
| 245 | case IEEE80211_IF_TYPE_AP: | 245 | case IEEE80211_IF_TYPE_AP: |
| 246 | sdata->bss = &sdata->u.ap; | 246 | sdata->bss = &sdata->u.ap; |
| 247 | break; | 247 | break; |
| 248 | case IEEE80211_IF_TYPE_MESH_POINT: | ||
| 249 | /* mesh ifaces must set allmulti to forward mcast traffic */ | ||
| 250 | atomic_inc(&local->iff_allmultis); | ||
| 251 | break; | ||
| 248 | case IEEE80211_IF_TYPE_STA: | 252 | case IEEE80211_IF_TYPE_STA: |
| 249 | case IEEE80211_IF_TYPE_MNTR: | 253 | case IEEE80211_IF_TYPE_MNTR: |
| 250 | case IEEE80211_IF_TYPE_IBSS: | 254 | case IEEE80211_IF_TYPE_IBSS: |
| 251 | case IEEE80211_IF_TYPE_MESH_POINT: | ||
| 252 | /* no special treatment */ | 255 | /* no special treatment */ |
| 253 | break; | 256 | break; |
| 254 | case IEEE80211_IF_TYPE_INVALID: | 257 | case IEEE80211_IF_TYPE_INVALID: |
| @@ -495,6 +498,9 @@ static int ieee80211_stop(struct net_device *dev) | |||
| 495 | netif_addr_unlock_bh(local->mdev); | 498 | netif_addr_unlock_bh(local->mdev); |
| 496 | break; | 499 | break; |
| 497 | case IEEE80211_IF_TYPE_MESH_POINT: | 500 | case IEEE80211_IF_TYPE_MESH_POINT: |
| 501 | /* allmulti is always set on mesh ifaces */ | ||
| 502 | atomic_dec(&local->iff_allmultis); | ||
| 503 | /* fall through */ | ||
| 498 | case IEEE80211_IF_TYPE_STA: | 504 | case IEEE80211_IF_TYPE_STA: |
| 499 | case IEEE80211_IF_TYPE_IBSS: | 505 | case IEEE80211_IF_TYPE_IBSS: |
| 500 | sdata->u.sta.state = IEEE80211_DISABLED; | 506 | sdata->u.sta.state = IEEE80211_DISABLED; |
diff --git a/net/mac80211/mesh.h b/net/mac80211/mesh.h index 669eafafe497..7495fbb0d211 100644 --- a/net/mac80211/mesh.h +++ b/net/mac80211/mesh.h | |||
| @@ -214,8 +214,7 @@ void ieee80211s_stop(void); | |||
| 214 | void ieee80211_mesh_init_sdata(struct ieee80211_sub_if_data *sdata); | 214 | void ieee80211_mesh_init_sdata(struct ieee80211_sub_if_data *sdata); |
| 215 | 215 | ||
| 216 | /* Mesh paths */ | 216 | /* Mesh paths */ |
| 217 | int mesh_nexthop_lookup(u8 *next_hop, struct sk_buff *skb, | 217 | int mesh_nexthop_lookup(struct sk_buff *skb, struct net_device *dev); |
| 218 | struct net_device *dev); | ||
| 219 | void mesh_path_start_discovery(struct net_device *dev); | 218 | void mesh_path_start_discovery(struct net_device *dev); |
| 220 | struct mesh_path *mesh_path_lookup(u8 *dst, struct net_device *dev); | 219 | struct mesh_path *mesh_path_lookup(u8 *dst, struct net_device *dev); |
| 221 | struct mesh_path *mesh_path_lookup_by_idx(int idx, struct net_device *dev); | 220 | struct mesh_path *mesh_path_lookup_by_idx(int idx, struct net_device *dev); |
| @@ -286,6 +285,4 @@ static inline void mesh_path_activate(struct mesh_path *mpath) | |||
| 286 | #define mesh_allocated 0 | 285 | #define mesh_allocated 0 |
| 287 | #endif | 286 | #endif |
| 288 | 287 | ||
| 289 | #define MESH_PREQ(skb) (skb->cb + 30) | ||
| 290 | |||
| 291 | #endif /* IEEE80211S_H */ | 288 | #endif /* IEEE80211S_H */ |
diff --git a/net/mac80211/mesh_hwmp.c b/net/mac80211/mesh_hwmp.c index 7fa149e230e6..08aca446ca01 100644 --- a/net/mac80211/mesh_hwmp.c +++ b/net/mac80211/mesh_hwmp.c | |||
| @@ -758,29 +758,30 @@ enddiscovery: | |||
| 758 | /** | 758 | /** |
| 759 | * ieee80211s_lookup_nexthop - put the appropriate next hop on a mesh frame | 759 | * ieee80211s_lookup_nexthop - put the appropriate next hop on a mesh frame |
| 760 | * | 760 | * |
| 761 | * @next_hop: output argument for next hop address | 761 | * @skb: 802.11 frame to be sent |
| 762 | * @skb: frame to be sent | ||
| 763 | * @dev: network device the frame will be sent through | 762 | * @dev: network device the frame will be sent through |
| 763 | * @fwd_frame: true if this frame was originally from a different host | ||
| 764 | * | 764 | * |
| 765 | * Returns: 0 if the next hop was found. Nonzero otherwise. If no next hop is | 765 | * Returns: 0 if the next hop was found. Nonzero otherwise. If no next hop is |
| 766 | * found, the function will start a path discovery and queue the frame so it is | 766 | * found, the function will start a path discovery and queue the frame so it is |
| 767 | * sent when the path is resolved. This means the caller must not free the skb | 767 | * sent when the path is resolved. This means the caller must not free the skb |
| 768 | * in this case. | 768 | * in this case. |
| 769 | */ | 769 | */ |
| 770 | int mesh_nexthop_lookup(u8 *next_hop, struct sk_buff *skb, | 770 | int mesh_nexthop_lookup(struct sk_buff *skb, struct net_device *dev) |
| 771 | struct net_device *dev) | ||
| 772 | { | 771 | { |
| 773 | struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); | 772 | struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); |
| 774 | struct sk_buff *skb_to_free = NULL; | 773 | struct sk_buff *skb_to_free = NULL; |
| 775 | struct mesh_path *mpath; | 774 | struct mesh_path *mpath; |
| 775 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | ||
| 776 | u8 *dst_addr = hdr->addr3; | ||
| 776 | int err = 0; | 777 | int err = 0; |
| 777 | 778 | ||
| 778 | rcu_read_lock(); | 779 | rcu_read_lock(); |
| 779 | mpath = mesh_path_lookup(skb->data, dev); | 780 | mpath = mesh_path_lookup(dst_addr, dev); |
| 780 | 781 | ||
| 781 | if (!mpath) { | 782 | if (!mpath) { |
| 782 | mesh_path_add(skb->data, dev); | 783 | mesh_path_add(dst_addr, dev); |
| 783 | mpath = mesh_path_lookup(skb->data, dev); | 784 | mpath = mesh_path_lookup(dst_addr, dev); |
| 784 | if (!mpath) { | 785 | if (!mpath) { |
| 785 | dev_kfree_skb(skb); | 786 | dev_kfree_skb(skb); |
| 786 | sdata->u.sta.mshstats.dropped_frames_no_route++; | 787 | sdata->u.sta.mshstats.dropped_frames_no_route++; |
| @@ -792,13 +793,13 @@ int mesh_nexthop_lookup(u8 *next_hop, struct sk_buff *skb, | |||
| 792 | if (mpath->flags & MESH_PATH_ACTIVE) { | 793 | if (mpath->flags & MESH_PATH_ACTIVE) { |
| 793 | if (time_after(jiffies, mpath->exp_time - | 794 | if (time_after(jiffies, mpath->exp_time - |
| 794 | msecs_to_jiffies(sdata->u.sta.mshcfg.path_refresh_time)) | 795 | msecs_to_jiffies(sdata->u.sta.mshcfg.path_refresh_time)) |
| 795 | && skb->pkt_type != PACKET_OTHERHOST | 796 | && !memcmp(dev->dev_addr, hdr->addr4, ETH_ALEN) |
| 796 | && !(mpath->flags & MESH_PATH_RESOLVING) | 797 | && !(mpath->flags & MESH_PATH_RESOLVING) |
| 797 | && !(mpath->flags & MESH_PATH_FIXED)) { | 798 | && !(mpath->flags & MESH_PATH_FIXED)) { |
| 798 | mesh_queue_preq(mpath, | 799 | mesh_queue_preq(mpath, |
| 799 | PREQ_Q_F_START | PREQ_Q_F_REFRESH); | 800 | PREQ_Q_F_START | PREQ_Q_F_REFRESH); |
| 800 | } | 801 | } |
| 801 | memcpy(next_hop, mpath->next_hop->addr, | 802 | memcpy(hdr->addr1, mpath->next_hop->addr, |
| 802 | ETH_ALEN); | 803 | ETH_ALEN); |
| 803 | } else { | 804 | } else { |
| 804 | if (!(mpath->flags & MESH_PATH_RESOLVING)) { | 805 | if (!(mpath->flags & MESH_PATH_RESOLVING)) { |
diff --git a/net/mac80211/mesh_pathtbl.c b/net/mac80211/mesh_pathtbl.c index 5f88a2e6ee50..838ee60492ad 100644 --- a/net/mac80211/mesh_pathtbl.c +++ b/net/mac80211/mesh_pathtbl.c | |||
| @@ -388,18 +388,15 @@ void mesh_path_tx_pending(struct mesh_path *mpath) | |||
| 388 | void mesh_path_discard_frame(struct sk_buff *skb, struct net_device *dev) | 388 | void mesh_path_discard_frame(struct sk_buff *skb, struct net_device *dev) |
| 389 | { | 389 | { |
| 390 | struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); | 390 | struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); |
| 391 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | ||
| 391 | struct mesh_path *mpath; | 392 | struct mesh_path *mpath; |
| 392 | u32 dsn = 0; | 393 | u32 dsn = 0; |
| 393 | 394 | ||
| 394 | if (skb->pkt_type == PACKET_OTHERHOST) { | 395 | if (memcmp(hdr->addr4, dev->dev_addr, ETH_ALEN) != 0) { |
| 395 | struct ieee80211s_hdr *prev_meshhdr; | ||
| 396 | int mshhdrlen; | ||
| 397 | u8 *ra, *da; | 396 | u8 *ra, *da; |
| 398 | 397 | ||
| 399 | prev_meshhdr = ((struct ieee80211s_hdr *)skb->cb); | 398 | da = hdr->addr3; |
| 400 | mshhdrlen = ieee80211_get_mesh_hdrlen(prev_meshhdr); | 399 | ra = hdr->addr2; |
| 401 | da = skb->data; | ||
| 402 | ra = MESH_PREQ(skb); | ||
| 403 | mpath = mesh_path_lookup(da, dev); | 400 | mpath = mesh_path_lookup(da, dev); |
| 404 | if (mpath) | 401 | if (mpath) |
| 405 | dsn = ++mpath->dsn; | 402 | dsn = ++mpath->dsn; |
diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c index 6d9ae67c27ca..6db854505193 100644 --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c | |||
| @@ -1109,20 +1109,9 @@ ieee80211_data_to_8023(struct ieee80211_rx_data *rx) | |||
| 1109 | 1109 | ||
| 1110 | hdrlen = ieee80211_get_hdrlen(fc); | 1110 | hdrlen = ieee80211_get_hdrlen(fc); |
| 1111 | 1111 | ||
| 1112 | if (ieee80211_vif_is_mesh(&sdata->vif)) { | 1112 | if (ieee80211_vif_is_mesh(&sdata->vif)) |
| 1113 | int meshhdrlen = ieee80211_get_mesh_hdrlen( | 1113 | hdrlen += ieee80211_get_mesh_hdrlen( |
| 1114 | (struct ieee80211s_hdr *) (skb->data + hdrlen)); | 1114 | (struct ieee80211s_hdr *) (skb->data + hdrlen)); |
| 1115 | /* Copy on cb: | ||
| 1116 | * - mesh header: to be used for mesh forwarding | ||
| 1117 | * decision. It will also be used as mesh header template at | ||
| 1118 | * tx.c:ieee80211_subif_start_xmit() if interface | ||
| 1119 | * type is mesh and skb->pkt_type == PACKET_OTHERHOST | ||
| 1120 | * - ta: to be used if a RERR needs to be sent. | ||
| 1121 | */ | ||
| 1122 | memcpy(skb->cb, skb->data + hdrlen, meshhdrlen); | ||
| 1123 | memcpy(MESH_PREQ(skb), hdr->addr2, ETH_ALEN); | ||
| 1124 | hdrlen += meshhdrlen; | ||
| 1125 | } | ||
| 1126 | 1115 | ||
| 1127 | /* convert IEEE 802.11 header + possible LLC headers into Ethernet | 1116 | /* convert IEEE 802.11 header + possible LLC headers into Ethernet |
| 1128 | * header | 1117 | * header |
| @@ -1269,38 +1258,6 @@ ieee80211_deliver_skb(struct ieee80211_rx_data *rx) | |||
| 1269 | } | 1258 | } |
| 1270 | } | 1259 | } |
| 1271 | 1260 | ||
| 1272 | /* Mesh forwarding */ | ||
| 1273 | if (ieee80211_vif_is_mesh(&sdata->vif)) { | ||
| 1274 | u8 *mesh_ttl = &((struct ieee80211s_hdr *)skb->cb)->ttl; | ||
| 1275 | (*mesh_ttl)--; | ||
| 1276 | |||
| 1277 | if (is_multicast_ether_addr(skb->data)) { | ||
| 1278 | if (*mesh_ttl > 0) { | ||
| 1279 | xmit_skb = skb_copy(skb, GFP_ATOMIC); | ||
| 1280 | if (xmit_skb) | ||
| 1281 | xmit_skb->pkt_type = PACKET_OTHERHOST; | ||
| 1282 | else if (net_ratelimit()) | ||
| 1283 | printk(KERN_DEBUG "%s: failed to clone " | ||
| 1284 | "multicast frame\n", dev->name); | ||
| 1285 | } else | ||
| 1286 | IEEE80211_IFSTA_MESH_CTR_INC(&sdata->u.sta, | ||
| 1287 | dropped_frames_ttl); | ||
| 1288 | } else if (skb->pkt_type != PACKET_OTHERHOST && | ||
| 1289 | compare_ether_addr(dev->dev_addr, skb->data) != 0) { | ||
| 1290 | if (*mesh_ttl == 0) { | ||
| 1291 | IEEE80211_IFSTA_MESH_CTR_INC(&sdata->u.sta, | ||
| 1292 | dropped_frames_ttl); | ||
| 1293 | dev_kfree_skb(skb); | ||
| 1294 | skb = NULL; | ||
| 1295 | } else { | ||
| 1296 | xmit_skb = skb; | ||
| 1297 | xmit_skb->pkt_type = PACKET_OTHERHOST; | ||
| 1298 | if (!(dev->flags & IFF_PROMISC)) | ||
| 1299 | skb = NULL; | ||
| 1300 | } | ||
| 1301 | } | ||
| 1302 | } | ||
| 1303 | |||
| 1304 | if (skb) { | 1261 | if (skb) { |
| 1305 | /* deliver to local stack */ | 1262 | /* deliver to local stack */ |
| 1306 | skb->protocol = eth_type_trans(skb, dev); | 1263 | skb->protocol = eth_type_trans(skb, dev); |
| @@ -1431,6 +1388,63 @@ ieee80211_rx_h_amsdu(struct ieee80211_rx_data *rx) | |||
| 1431 | } | 1388 | } |
| 1432 | 1389 | ||
| 1433 | static ieee80211_rx_result debug_noinline | 1390 | static ieee80211_rx_result debug_noinline |
| 1391 | ieee80211_rx_h_mesh_fwding(struct ieee80211_rx_data *rx) | ||
| 1392 | { | ||
| 1393 | struct ieee80211_hdr *hdr; | ||
| 1394 | struct ieee80211s_hdr *mesh_hdr; | ||
| 1395 | unsigned int hdrlen; | ||
| 1396 | struct sk_buff *skb = rx->skb, *fwd_skb; | ||
| 1397 | |||
| 1398 | hdr = (struct ieee80211_hdr *) skb->data; | ||
| 1399 | hdrlen = ieee80211_hdrlen(hdr->frame_control); | ||
| 1400 | mesh_hdr = (struct ieee80211s_hdr *) (skb->data + hdrlen); | ||
| 1401 | |||
| 1402 | if (!ieee80211_is_data(hdr->frame_control)) | ||
| 1403 | return RX_CONTINUE; | ||
| 1404 | |||
| 1405 | if (!mesh_hdr->ttl) | ||
| 1406 | /* illegal frame */ | ||
| 1407 | return RX_DROP_MONITOR; | ||
| 1408 | |||
| 1409 | if (compare_ether_addr(rx->dev->dev_addr, hdr->addr3) == 0) | ||
| 1410 | return RX_CONTINUE; | ||
| 1411 | |||
| 1412 | mesh_hdr->ttl--; | ||
| 1413 | |||
| 1414 | if (rx->flags & IEEE80211_RX_RA_MATCH) { | ||
| 1415 | if (!mesh_hdr->ttl) | ||
| 1416 | IEEE80211_IFSTA_MESH_CTR_INC(&rx->sdata->u.sta, | ||
| 1417 | dropped_frames_ttl); | ||
| 1418 | else { | ||
| 1419 | struct ieee80211_hdr *fwd_hdr; | ||
| 1420 | fwd_skb = skb_copy(skb, GFP_ATOMIC); | ||
| 1421 | |||
| 1422 | if (!fwd_skb && net_ratelimit()) | ||
| 1423 | printk(KERN_DEBUG "%s: failed to clone mesh frame\n", | ||
| 1424 | rx->dev->name); | ||
| 1425 | |||
| 1426 | fwd_hdr = (struct ieee80211_hdr *) fwd_skb->data; | ||
| 1427 | /* | ||
| 1428 | * Save TA to addr1 to send TA a path error if a | ||
| 1429 | * suitable next hop is not found | ||
| 1430 | */ | ||
| 1431 | memcpy(fwd_hdr->addr1, fwd_hdr->addr2, ETH_ALEN); | ||
| 1432 | memcpy(fwd_hdr->addr2, rx->dev->dev_addr, ETH_ALEN); | ||
| 1433 | fwd_skb->dev = rx->local->mdev; | ||
| 1434 | fwd_skb->iif = rx->dev->ifindex; | ||
| 1435 | dev_queue_xmit(fwd_skb); | ||
| 1436 | } | ||
| 1437 | } | ||
| 1438 | |||
| 1439 | if (is_multicast_ether_addr(hdr->addr3) || | ||
| 1440 | rx->dev->flags & IFF_PROMISC) | ||
| 1441 | return RX_CONTINUE; | ||
| 1442 | else | ||
| 1443 | return RX_DROP_MONITOR; | ||
| 1444 | } | ||
| 1445 | |||
| 1446 | |||
| 1447 | static ieee80211_rx_result debug_noinline | ||
| 1434 | ieee80211_rx_h_data(struct ieee80211_rx_data *rx) | 1448 | ieee80211_rx_h_data(struct ieee80211_rx_data *rx) |
| 1435 | { | 1449 | { |
| 1436 | struct net_device *dev = rx->dev; | 1450 | struct net_device *dev = rx->dev; |
| @@ -1663,10 +1677,12 @@ static void ieee80211_invoke_rx_handlers(struct ieee80211_sub_if_data *sdata, | |||
| 1663 | rx->sdata = sdata; | 1677 | rx->sdata = sdata; |
| 1664 | rx->dev = sdata->dev; | 1678 | rx->dev = sdata->dev; |
| 1665 | 1679 | ||
| 1666 | #define CALL_RXH(rxh) \ | 1680 | #define CALL_RXH(rxh) \ |
| 1667 | res = rxh(rx); \ | 1681 | do { \ |
| 1668 | if (res != RX_CONTINUE) \ | 1682 | res = rxh(rx); \ |
| 1669 | goto rxh_done; | 1683 | if (res != RX_CONTINUE) \ |
| 1684 | goto rxh_done; \ | ||
| 1685 | } while (0); | ||
| 1670 | 1686 | ||
| 1671 | CALL_RXH(ieee80211_rx_h_passive_scan) | 1687 | CALL_RXH(ieee80211_rx_h_passive_scan) |
| 1672 | CALL_RXH(ieee80211_rx_h_check) | 1688 | CALL_RXH(ieee80211_rx_h_check) |
| @@ -1678,6 +1694,8 @@ static void ieee80211_invoke_rx_handlers(struct ieee80211_sub_if_data *sdata, | |||
| 1678 | /* must be after MMIC verify so header is counted in MPDU mic */ | 1694 | /* must be after MMIC verify so header is counted in MPDU mic */ |
| 1679 | CALL_RXH(ieee80211_rx_h_remove_qos_control) | 1695 | CALL_RXH(ieee80211_rx_h_remove_qos_control) |
| 1680 | CALL_RXH(ieee80211_rx_h_amsdu) | 1696 | CALL_RXH(ieee80211_rx_h_amsdu) |
| 1697 | if (ieee80211_vif_is_mesh(&sdata->vif)) | ||
| 1698 | CALL_RXH(ieee80211_rx_h_mesh_fwding); | ||
| 1681 | CALL_RXH(ieee80211_rx_h_data) | 1699 | CALL_RXH(ieee80211_rx_h_data) |
| 1682 | CALL_RXH(ieee80211_rx_h_ctrl) | 1700 | CALL_RXH(ieee80211_rx_h_ctrl) |
| 1683 | CALL_RXH(ieee80211_rx_h_mgmt) | 1701 | CALL_RXH(ieee80211_rx_h_mgmt) |
diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 771ec68b848d..4788f7b91f49 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c | |||
| @@ -1301,6 +1301,7 @@ int ieee80211_master_start_xmit(struct sk_buff *skb, | |||
| 1301 | struct net_device *dev) | 1301 | struct net_device *dev) |
| 1302 | { | 1302 | { |
| 1303 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | 1303 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 1304 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | ||
| 1304 | struct net_device *odev = NULL; | 1305 | struct net_device *odev = NULL; |
| 1305 | struct ieee80211_sub_if_data *osdata; | 1306 | struct ieee80211_sub_if_data *osdata; |
| 1306 | int headroom; | 1307 | int headroom; |
| @@ -1328,6 +1329,20 @@ int ieee80211_master_start_xmit(struct sk_buff *skb, | |||
| 1328 | 1329 | ||
| 1329 | osdata = IEEE80211_DEV_TO_SUB_IF(odev); | 1330 | osdata = IEEE80211_DEV_TO_SUB_IF(odev); |
| 1330 | 1331 | ||
| 1332 | if (ieee80211_vif_is_mesh(&osdata->vif) && | ||
| 1333 | ieee80211_is_data(hdr->frame_control)) { | ||
| 1334 | if (ieee80211_is_data(hdr->frame_control)) { | ||
| 1335 | if (is_multicast_ether_addr(hdr->addr3)) | ||
| 1336 | memcpy(hdr->addr1, hdr->addr3, ETH_ALEN); | ||
| 1337 | else | ||
| 1338 | if (mesh_nexthop_lookup(skb, odev)) | ||
| 1339 | return 0; | ||
| 1340 | if (memcmp(odev->dev_addr, hdr->addr4, ETH_ALEN) != 0) | ||
| 1341 | IEEE80211_IFSTA_MESH_CTR_INC(&osdata->u.sta, | ||
| 1342 | fwded_frames); | ||
| 1343 | } | ||
| 1344 | } | ||
| 1345 | |||
| 1331 | may_encrypt = !skb->do_not_encrypt; | 1346 | may_encrypt = !skb->do_not_encrypt; |
| 1332 | 1347 | ||
| 1333 | headroom = osdata->local->tx_headroom; | 1348 | headroom = osdata->local->tx_headroom; |
| @@ -1472,30 +1487,17 @@ int ieee80211_subif_start_xmit(struct sk_buff *skb, | |||
| 1472 | case IEEE80211_IF_TYPE_MESH_POINT: | 1487 | case IEEE80211_IF_TYPE_MESH_POINT: |
| 1473 | fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS); | 1488 | fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS); |
| 1474 | /* RA TA DA SA */ | 1489 | /* RA TA DA SA */ |
| 1475 | if (is_multicast_ether_addr(skb->data)) | 1490 | memset(hdr.addr1, 0, ETH_ALEN); |
| 1476 | memcpy(hdr.addr1, skb->data, ETH_ALEN); | ||
| 1477 | else if (mesh_nexthop_lookup(hdr.addr1, skb, dev)) | ||
| 1478 | return 0; | ||
| 1479 | memcpy(hdr.addr2, dev->dev_addr, ETH_ALEN); | 1491 | memcpy(hdr.addr2, dev->dev_addr, ETH_ALEN); |
| 1480 | memcpy(hdr.addr3, skb->data, ETH_ALEN); | 1492 | memcpy(hdr.addr3, skb->data, ETH_ALEN); |
| 1481 | memcpy(hdr.addr4, skb->data + ETH_ALEN, ETH_ALEN); | 1493 | memcpy(hdr.addr4, skb->data + ETH_ALEN, ETH_ALEN); |
| 1482 | if (skb->pkt_type == PACKET_OTHERHOST) { | 1494 | if (!sdata->u.sta.mshcfg.dot11MeshTTL) { |
| 1483 | /* Forwarded frame, keep mesh ttl and seqnum */ | 1495 | /* Do not send frames with mesh_ttl == 0 */ |
| 1484 | struct ieee80211s_hdr *prev_meshhdr; | 1496 | sdata->u.sta.mshstats.dropped_frames_ttl++; |
| 1485 | prev_meshhdr = ((struct ieee80211s_hdr *)skb->cb); | 1497 | ret = 0; |
| 1486 | meshhdrlen = ieee80211_get_mesh_hdrlen(prev_meshhdr); | 1498 | goto fail; |
| 1487 | memcpy(&mesh_hdr, prev_meshhdr, meshhdrlen); | ||
| 1488 | sdata->u.sta.mshstats.fwded_frames++; | ||
| 1489 | } else { | ||
| 1490 | if (!sdata->u.sta.mshcfg.dot11MeshTTL) { | ||
| 1491 | /* Do not send frames with mesh_ttl == 0 */ | ||
| 1492 | sdata->u.sta.mshstats.dropped_frames_ttl++; | ||
| 1493 | ret = 0; | ||
| 1494 | goto fail; | ||
| 1495 | } | ||
| 1496 | meshhdrlen = ieee80211_new_mesh_header(&mesh_hdr, | ||
| 1497 | sdata); | ||
| 1498 | } | 1499 | } |
| 1500 | meshhdrlen = ieee80211_new_mesh_header(&mesh_hdr, sdata); | ||
| 1499 | hdrlen = 30; | 1501 | hdrlen = 30; |
| 1500 | break; | 1502 | break; |
| 1501 | #endif | 1503 | #endif |
| @@ -1543,7 +1545,8 @@ int ieee80211_subif_start_xmit(struct sk_buff *skb, | |||
| 1543 | * Drop unicast frames to unauthorised stations unless they are | 1545 | * Drop unicast frames to unauthorised stations unless they are |
| 1544 | * EAPOL frames from the local station. | 1546 | * EAPOL frames from the local station. |
| 1545 | */ | 1547 | */ |
| 1546 | if (unlikely(!is_multicast_ether_addr(hdr.addr1) && | 1548 | if (!ieee80211_vif_is_mesh(&sdata->vif) && |
| 1549 | unlikely(!is_multicast_ether_addr(hdr.addr1) && | ||
| 1547 | !(sta_flags & WLAN_STA_AUTHORIZED) && | 1550 | !(sta_flags & WLAN_STA_AUTHORIZED) && |
| 1548 | !(ethertype == ETH_P_PAE && | 1551 | !(ethertype == ETH_P_PAE && |
| 1549 | compare_ether_addr(dev->dev_addr, | 1552 | compare_ether_addr(dev->dev_addr, |
diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index c519d090bdb9..9d1830da8e84 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c | |||
| @@ -1032,10 +1032,10 @@ void nf_conntrack_cleanup(void) | |||
| 1032 | nf_ct_free_hashtable(nf_conntrack_hash, nf_conntrack_vmalloc, | 1032 | nf_ct_free_hashtable(nf_conntrack_hash, nf_conntrack_vmalloc, |
| 1033 | nf_conntrack_htable_size); | 1033 | nf_conntrack_htable_size); |
| 1034 | 1034 | ||
| 1035 | nf_conntrack_proto_fini(); | ||
| 1036 | nf_conntrack_helper_fini(); | ||
| 1037 | nf_conntrack_expect_fini(); | ||
| 1038 | nf_conntrack_acct_fini(); | 1035 | nf_conntrack_acct_fini(); |
| 1036 | nf_conntrack_expect_fini(); | ||
| 1037 | nf_conntrack_helper_fini(); | ||
| 1038 | nf_conntrack_proto_fini(); | ||
| 1039 | } | 1039 | } |
| 1040 | 1040 | ||
| 1041 | struct hlist_head *nf_ct_alloc_hashtable(unsigned int *sizep, int *vmalloced) | 1041 | struct hlist_head *nf_ct_alloc_hashtable(unsigned int *sizep, int *vmalloced) |
diff --git a/net/netfilter/nf_conntrack_standalone.c b/net/netfilter/nf_conntrack_standalone.c index 869ef9349d0f..8509db14670b 100644 --- a/net/netfilter/nf_conntrack_standalone.c +++ b/net/netfilter/nf_conntrack_standalone.c | |||
| @@ -324,6 +324,7 @@ static int log_invalid_proto_min = 0; | |||
| 324 | static int log_invalid_proto_max = 255; | 324 | static int log_invalid_proto_max = 255; |
| 325 | 325 | ||
| 326 | static struct ctl_table_header *nf_ct_sysctl_header; | 326 | static struct ctl_table_header *nf_ct_sysctl_header; |
| 327 | static struct ctl_table_header *nf_ct_netfilter_header; | ||
| 327 | 328 | ||
| 328 | static ctl_table nf_ct_sysctl_table[] = { | 329 | static ctl_table nf_ct_sysctl_table[] = { |
| 329 | { | 330 | { |
| @@ -384,12 +385,6 @@ static ctl_table nf_ct_sysctl_table[] = { | |||
| 384 | 385 | ||
| 385 | static ctl_table nf_ct_netfilter_table[] = { | 386 | static ctl_table nf_ct_netfilter_table[] = { |
| 386 | { | 387 | { |
| 387 | .ctl_name = NET_NETFILTER, | ||
| 388 | .procname = "netfilter", | ||
| 389 | .mode = 0555, | ||
| 390 | .child = nf_ct_sysctl_table, | ||
| 391 | }, | ||
| 392 | { | ||
| 393 | .ctl_name = NET_NF_CONNTRACK_MAX, | 388 | .ctl_name = NET_NF_CONNTRACK_MAX, |
| 394 | .procname = "nf_conntrack_max", | 389 | .procname = "nf_conntrack_max", |
| 395 | .data = &nf_conntrack_max, | 390 | .data = &nf_conntrack_max, |
| @@ -409,18 +404,29 @@ EXPORT_SYMBOL_GPL(nf_ct_log_invalid); | |||
| 409 | 404 | ||
| 410 | static int nf_conntrack_standalone_init_sysctl(void) | 405 | static int nf_conntrack_standalone_init_sysctl(void) |
| 411 | { | 406 | { |
| 412 | nf_ct_sysctl_header = | 407 | nf_ct_netfilter_header = |
| 413 | register_sysctl_paths(nf_ct_path, nf_ct_netfilter_table); | 408 | register_sysctl_paths(nf_ct_path, nf_ct_netfilter_table); |
| 414 | if (nf_ct_sysctl_header == NULL) { | 409 | if (!nf_ct_netfilter_header) |
| 415 | printk("nf_conntrack: can't register to sysctl.\n"); | 410 | goto out; |
| 416 | return -ENOMEM; | 411 | |
| 417 | } | 412 | nf_ct_sysctl_header = |
| 413 | register_sysctl_paths(nf_net_netfilter_sysctl_path, | ||
| 414 | nf_ct_sysctl_table); | ||
| 415 | if (!nf_ct_sysctl_header) | ||
| 416 | goto out_unregister_netfilter; | ||
| 417 | |||
| 418 | return 0; | 418 | return 0; |
| 419 | 419 | ||
| 420 | out_unregister_netfilter: | ||
| 421 | unregister_sysctl_table(nf_ct_netfilter_header); | ||
| 422 | out: | ||
| 423 | printk("nf_conntrack: can't register to sysctl.\n"); | ||
| 424 | return -ENOMEM; | ||
| 420 | } | 425 | } |
| 421 | 426 | ||
| 422 | static void nf_conntrack_standalone_fini_sysctl(void) | 427 | static void nf_conntrack_standalone_fini_sysctl(void) |
| 423 | { | 428 | { |
| 429 | unregister_sysctl_table(nf_ct_netfilter_header); | ||
| 424 | unregister_sysctl_table(nf_ct_sysctl_header); | 430 | unregister_sysctl_table(nf_ct_sysctl_header); |
| 425 | } | 431 | } |
| 426 | #else | 432 | #else |
diff --git a/net/sched/act_api.c b/net/sched/act_api.c index d308c19aa3f9..26c7e1f9a350 100644 --- a/net/sched/act_api.c +++ b/net/sched/act_api.c | |||
| @@ -205,10 +205,9 @@ struct tcf_common *tcf_hash_check(u32 index, struct tc_action *a, int bind, | |||
| 205 | { | 205 | { |
| 206 | struct tcf_common *p = NULL; | 206 | struct tcf_common *p = NULL; |
| 207 | if (index && (p = tcf_hash_lookup(index, hinfo)) != NULL) { | 207 | if (index && (p = tcf_hash_lookup(index, hinfo)) != NULL) { |
| 208 | if (bind) { | 208 | if (bind) |
| 209 | p->tcfc_bindcnt++; | 209 | p->tcfc_bindcnt++; |
| 210 | p->tcfc_refcnt++; | 210 | p->tcfc_refcnt++; |
| 211 | } | ||
| 212 | a->priv = p; | 211 | a->priv = p; |
| 213 | } | 212 | } |
| 214 | return p; | 213 | return p; |
diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 4840aff47256..ba1d121f3127 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c | |||
| @@ -189,7 +189,7 @@ struct Qdisc *qdisc_lookup(struct net_device *dev, u32 handle) | |||
| 189 | 189 | ||
| 190 | for (i = 0; i < dev->num_tx_queues; i++) { | 190 | for (i = 0; i < dev->num_tx_queues; i++) { |
| 191 | struct netdev_queue *txq = netdev_get_tx_queue(dev, i); | 191 | struct netdev_queue *txq = netdev_get_tx_queue(dev, i); |
| 192 | struct Qdisc *q, *txq_root = txq->qdisc; | 192 | struct Qdisc *q, *txq_root = txq->qdisc_sleeping; |
| 193 | 193 | ||
| 194 | if (!(txq_root->flags & TCQ_F_BUILTIN) && | 194 | if (!(txq_root->flags & TCQ_F_BUILTIN) && |
| 195 | txq_root->handle == handle) | 195 | txq_root->handle == handle) |
| @@ -792,8 +792,8 @@ qdisc_create(struct net_device *dev, struct netdev_queue *dev_queue, | |||
| 792 | goto err_out3; | 792 | goto err_out3; |
| 793 | } | 793 | } |
| 794 | } | 794 | } |
| 795 | if (parent && !(sch->flags & TCQ_F_INGRESS)) | 795 | if ((parent != TC_H_ROOT) && !(sch->flags & TCQ_F_INGRESS)) |
| 796 | list_add_tail(&sch->list, &dev_queue->qdisc->list); | 796 | list_add_tail(&sch->list, &dev_queue->qdisc_sleeping->list); |
| 797 | 797 | ||
| 798 | return sch; | 798 | return sch; |
| 799 | } | 799 | } |
| @@ -1236,11 +1236,11 @@ static int tc_dump_qdisc(struct sk_buff *skb, struct netlink_callback *cb) | |||
| 1236 | q_idx = 0; | 1236 | q_idx = 0; |
| 1237 | 1237 | ||
| 1238 | dev_queue = netdev_get_tx_queue(dev, 0); | 1238 | dev_queue = netdev_get_tx_queue(dev, 0); |
| 1239 | if (tc_dump_qdisc_root(dev_queue->qdisc, skb, cb, &q_idx, s_q_idx) < 0) | 1239 | if (tc_dump_qdisc_root(dev_queue->qdisc_sleeping, skb, cb, &q_idx, s_q_idx) < 0) |
| 1240 | goto done; | 1240 | goto done; |
| 1241 | 1241 | ||
| 1242 | dev_queue = &dev->rx_queue; | 1242 | dev_queue = &dev->rx_queue; |
| 1243 | if (tc_dump_qdisc_root(dev_queue->qdisc, skb, cb, &q_idx, s_q_idx) < 0) | 1243 | if (tc_dump_qdisc_root(dev_queue->qdisc_sleeping, skb, cb, &q_idx, s_q_idx) < 0) |
| 1244 | goto done; | 1244 | goto done; |
| 1245 | 1245 | ||
| 1246 | cont: | 1246 | cont: |
diff --git a/net/wanrouter/wanmain.c b/net/wanrouter/wanmain.c index b210a88d0960..7f07152bc109 100644 --- a/net/wanrouter/wanmain.c +++ b/net/wanrouter/wanmain.c | |||
| @@ -57,7 +57,6 @@ | |||
| 57 | #include <linux/vmalloc.h> /* vmalloc, vfree */ | 57 | #include <linux/vmalloc.h> /* vmalloc, vfree */ |
| 58 | #include <asm/uaccess.h> /* copy_to/from_user */ | 58 | #include <asm/uaccess.h> /* copy_to/from_user */ |
| 59 | #include <linux/init.h> /* __initfunc et al. */ | 59 | #include <linux/init.h> /* __initfunc et al. */ |
| 60 | #include <net/syncppp.h> | ||
| 61 | 60 | ||
| 62 | #define KMEM_SAFETYZONE 8 | 61 | #define KMEM_SAFETYZONE 8 |
| 63 | 62 | ||
| @@ -567,9 +566,6 @@ static int wanrouter_device_new_if(struct wan_device *wandev, | |||
| 567 | { | 566 | { |
| 568 | wanif_conf_t *cnf; | 567 | wanif_conf_t *cnf; |
| 569 | struct net_device *dev = NULL; | 568 | struct net_device *dev = NULL; |
| 570 | #ifdef CONFIG_WANPIPE_MULTPPP | ||
| 571 | struct ppp_device *pppdev=NULL; | ||
| 572 | #endif | ||
| 573 | int err; | 569 | int err; |
| 574 | 570 | ||
| 575 | if ((wandev->state == WAN_UNCONFIGURED) || (wandev->new_if == NULL)) | 571 | if ((wandev->state == WAN_UNCONFIGURED) || (wandev->new_if == NULL)) |
| @@ -588,25 +584,10 @@ static int wanrouter_device_new_if(struct wan_device *wandev, | |||
| 588 | goto out; | 584 | goto out; |
| 589 | 585 | ||
| 590 | if (cnf->config_id == WANCONFIG_MPPP) { | 586 | if (cnf->config_id == WANCONFIG_MPPP) { |
| 591 | #ifdef CONFIG_WANPIPE_MULTPPP | ||
| 592 | pppdev = kzalloc(sizeof(struct ppp_device), GFP_KERNEL); | ||
| 593 | err = -ENOBUFS; | ||
| 594 | if (pppdev == NULL) | ||
| 595 | goto out; | ||
| 596 | pppdev->dev = kzalloc(sizeof(struct net_device), GFP_KERNEL); | ||
| 597 | if (pppdev->dev == NULL) { | ||
| 598 | kfree(pppdev); | ||
| 599 | err = -ENOBUFS; | ||
| 600 | goto out; | ||
| 601 | } | ||
| 602 | err = wandev->new_if(wandev, (struct net_device *)pppdev, cnf); | ||
| 603 | dev = pppdev->dev; | ||
| 604 | #else | ||
| 605 | printk(KERN_INFO "%s: Wanpipe Mulit-Port PPP support has not been compiled in!\n", | 587 | printk(KERN_INFO "%s: Wanpipe Mulit-Port PPP support has not been compiled in!\n", |
| 606 | wandev->name); | 588 | wandev->name); |
| 607 | err = -EPROTONOSUPPORT; | 589 | err = -EPROTONOSUPPORT; |
| 608 | goto out; | 590 | goto out; |
| 609 | #endif | ||
| 610 | } else { | 591 | } else { |
| 611 | dev = kzalloc(sizeof(struct net_device), GFP_KERNEL); | 592 | dev = kzalloc(sizeof(struct net_device), GFP_KERNEL); |
| 612 | err = -ENOBUFS; | 593 | err = -ENOBUFS; |
| @@ -661,17 +642,9 @@ static int wanrouter_device_new_if(struct wan_device *wandev, | |||
| 661 | kfree(dev->priv); | 642 | kfree(dev->priv); |
| 662 | dev->priv = NULL; | 643 | dev->priv = NULL; |
| 663 | 644 | ||
| 664 | #ifdef CONFIG_WANPIPE_MULTPPP | ||
| 665 | if (cnf->config_id == WANCONFIG_MPPP) | ||
| 666 | kfree(pppdev); | ||
| 667 | else | ||
| 668 | kfree(dev); | ||
| 669 | #else | ||
| 670 | /* Sync PPP is disabled */ | 645 | /* Sync PPP is disabled */ |
| 671 | if (cnf->config_id != WANCONFIG_MPPP) | 646 | if (cnf->config_id != WANCONFIG_MPPP) |
| 672 | kfree(dev); | 647 | kfree(dev); |
| 673 | #endif | ||
| 674 | |||
| 675 | out: | 648 | out: |
| 676 | kfree(cnf); | 649 | kfree(cnf); |
| 677 | return err; | 650 | return err; |
diff --git a/sound/soc/fsl/fsl_dma.c b/sound/soc/fsl/fsl_dma.c index 7ceea2bba1f5..d2d3da9729f2 100644 --- a/sound/soc/fsl/fsl_dma.c +++ b/sound/soc/fsl/fsl_dma.c | |||
| @@ -327,14 +327,75 @@ static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, | |||
| 327 | * fsl_dma_open: open a new substream. | 327 | * fsl_dma_open: open a new substream. |
| 328 | * | 328 | * |
| 329 | * Each substream has its own DMA buffer. | 329 | * Each substream has its own DMA buffer. |
| 330 | * | ||
| 331 | * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link | ||
| 332 | * descriptors that ping-pong from one period to the next. For example, if | ||
| 333 | * there are six periods and two link descriptors, this is how they look | ||
| 334 | * before playback starts: | ||
| 335 | * | ||
| 336 | * The last link descriptor | ||
| 337 | * ____________ points back to the first | ||
| 338 | * | | | ||
| 339 | * V | | ||
| 340 | * ___ ___ | | ||
| 341 | * | |->| |->| | ||
| 342 | * |___| |___| | ||
| 343 | * | | | ||
| 344 | * | | | ||
| 345 | * V V | ||
| 346 | * _________________________________________ | ||
| 347 | * | | | | | | | The DMA buffer is | ||
| 348 | * | | | | | | | divided into 6 parts | ||
| 349 | * |______|______|______|______|______|______| | ||
| 350 | * | ||
| 351 | * and here's how they look after the first period is finished playing: | ||
| 352 | * | ||
| 353 | * ____________ | ||
| 354 | * | | | ||
| 355 | * V | | ||
| 356 | * ___ ___ | | ||
| 357 | * | |->| |->| | ||
| 358 | * |___| |___| | ||
| 359 | * | | | ||
| 360 | * |______________ | ||
| 361 | * | | | ||
| 362 | * V V | ||
| 363 | * _________________________________________ | ||
| 364 | * | | | | | | | | ||
| 365 | * | | | | | | | | ||
| 366 | * |______|______|______|______|______|______| | ||
| 367 | * | ||
| 368 | * The first link descriptor now points to the third period. The DMA | ||
| 369 | * controller is currently playing the second period. When it finishes, it | ||
| 370 | * will jump back to the first descriptor and play the third period. | ||
| 371 | * | ||
| 372 | * There are four reasons we do this: | ||
| 373 | * | ||
| 374 | * 1. The only way to get the DMA controller to automatically restart the | ||
| 375 | * transfer when it gets to the end of the buffer is to use chaining | ||
| 376 | * mode. Basic direct mode doesn't offer that feature. | ||
| 377 | * 2. We need to receive an interrupt at the end of every period. The DMA | ||
| 378 | * controller can generate an interrupt at the end of every link transfer | ||
| 379 | * (aka segment). Making each period into a DMA segment will give us the | ||
| 380 | * interrupts we need. | ||
| 381 | * 3. By creating only two link descriptors, regardless of the number of | ||
| 382 | * periods, we do not need to reallocate the link descriptors if the | ||
| 383 | * number of periods changes. | ||
| 384 | * 4. All of the audio data is still stored in a single, contiguous DMA | ||
| 385 | * buffer, which is what ALSA expects. We're just dividing it into | ||
| 386 | * contiguous parts, and creating a link descriptor for each one. | ||
| 330 | */ | 387 | */ |
| 331 | static int fsl_dma_open(struct snd_pcm_substream *substream) | 388 | static int fsl_dma_open(struct snd_pcm_substream *substream) |
| 332 | { | 389 | { |
| 333 | struct snd_pcm_runtime *runtime = substream->runtime; | 390 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 334 | struct fsl_dma_private *dma_private; | 391 | struct fsl_dma_private *dma_private; |
| 392 | struct ccsr_dma_channel __iomem *dma_channel; | ||
| 335 | dma_addr_t ld_buf_phys; | 393 | dma_addr_t ld_buf_phys; |
| 394 | u64 temp_link; /* Pointer to next link descriptor */ | ||
| 395 | u32 mr; | ||
| 336 | unsigned int channel; | 396 | unsigned int channel; |
| 337 | int ret = 0; | 397 | int ret = 0; |
| 398 | unsigned int i; | ||
| 338 | 399 | ||
| 339 | /* | 400 | /* |
| 340 | * Reject any DMA buffer whose size is not a multiple of the period | 401 | * Reject any DMA buffer whose size is not a multiple of the period |
| @@ -395,68 +456,74 @@ static int fsl_dma_open(struct snd_pcm_substream *substream) | |||
| 395 | snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); | 456 | snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); |
| 396 | runtime->private_data = dma_private; | 457 | runtime->private_data = dma_private; |
| 397 | 458 | ||
| 459 | /* Program the fixed DMA controller parameters */ | ||
| 460 | |||
| 461 | dma_channel = dma_private->dma_channel; | ||
| 462 | |||
| 463 | temp_link = dma_private->ld_buf_phys + | ||
| 464 | sizeof(struct fsl_dma_link_descriptor); | ||
| 465 | |||
| 466 | for (i = 0; i < NUM_DMA_LINKS; i++) { | ||
| 467 | struct fsl_dma_link_descriptor *link = &dma_private->link[i]; | ||
| 468 | |||
| 469 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); | ||
| 470 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); | ||
| 471 | link->next = cpu_to_be64(temp_link); | ||
| 472 | |||
| 473 | temp_link += sizeof(struct fsl_dma_link_descriptor); | ||
| 474 | } | ||
| 475 | /* The last link descriptor points to the first */ | ||
| 476 | dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); | ||
| 477 | |||
| 478 | /* Tell the DMA controller where the first link descriptor is */ | ||
| 479 | out_be32(&dma_channel->clndar, | ||
| 480 | CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); | ||
| 481 | out_be32(&dma_channel->eclndar, | ||
| 482 | CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); | ||
| 483 | |||
| 484 | /* The manual says the BCR must be clear before enabling EMP */ | ||
| 485 | out_be32(&dma_channel->bcr, 0); | ||
| 486 | |||
| 487 | /* | ||
| 488 | * Program the mode register for interrupts, external master control, | ||
| 489 | * and source/destination hold. Also clear the Channel Abort bit. | ||
| 490 | */ | ||
| 491 | mr = in_be32(&dma_channel->mr) & | ||
| 492 | ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); | ||
| 493 | |||
| 494 | /* | ||
| 495 | * We want External Master Start and External Master Pause enabled, | ||
| 496 | * because the SSI is controlling the DMA controller. We want the DMA | ||
| 497 | * controller to be set up in advance, and then we signal only the SSI | ||
| 498 | * to start transferring. | ||
| 499 | * | ||
| 500 | * We want End-Of-Segment Interrupts enabled, because this will generate | ||
| 501 | * an interrupt at the end of each segment (each link descriptor | ||
| 502 | * represents one segment). Each DMA segment is the same thing as an | ||
| 503 | * ALSA period, so this is how we get an interrupt at the end of every | ||
| 504 | * period. | ||
| 505 | * | ||
| 506 | * We want Error Interrupt enabled, so that we can get an error if | ||
| 507 | * the DMA controller is mis-programmed somehow. | ||
| 508 | */ | ||
| 509 | mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | | ||
| 510 | CCSR_DMA_MR_EMS_EN; | ||
| 511 | |||
| 512 | /* For playback, we want the destination address to be held. For | ||
| 513 | capture, set the source address to be held. */ | ||
| 514 | mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? | ||
| 515 | CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; | ||
| 516 | |||
| 517 | out_be32(&dma_channel->mr, mr); | ||
| 518 | |||
| 398 | return 0; | 519 | return 0; |
| 399 | } | 520 | } |
| 400 | 521 | ||
| 401 | /** | 522 | /** |
| 402 | * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors. | 523 | * fsl_dma_hw_params: continue initializing the DMA links |
| 403 | * | ||
| 404 | * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link | ||
| 405 | * descriptors that ping-pong from one period to the next. For example, if | ||
| 406 | * there are six periods and two link descriptors, this is how they look | ||
| 407 | * before playback starts: | ||
| 408 | * | ||
| 409 | * The last link descriptor | ||
| 410 | * ____________ points back to the first | ||
| 411 | * | | | ||
| 412 | * V | | ||
| 413 | * ___ ___ | | ||
| 414 | * | |->| |->| | ||
| 415 | * |___| |___| | ||
| 416 | * | | | ||
| 417 | * | | | ||
| 418 | * V V | ||
| 419 | * _________________________________________ | ||
| 420 | * | | | | | | | The DMA buffer is | ||
| 421 | * | | | | | | | divided into 6 parts | ||
| 422 | * |______|______|______|______|______|______| | ||
| 423 | * | ||
| 424 | * and here's how they look after the first period is finished playing: | ||
| 425 | * | ||
| 426 | * ____________ | ||
| 427 | * | | | ||
| 428 | * V | | ||
| 429 | * ___ ___ | | ||
| 430 | * | |->| |->| | ||
| 431 | * |___| |___| | ||
| 432 | * | | | ||
| 433 | * |______________ | ||
| 434 | * | | | ||
| 435 | * V V | ||
| 436 | * _________________________________________ | ||
| 437 | * | | | | | | | | ||
| 438 | * | | | | | | | | ||
| 439 | * |______|______|______|______|______|______| | ||
| 440 | * | 524 | * |
| 441 | * The first link descriptor now points to the third period. The DMA | 525 | * This function obtains hardware parameters about the opened stream and |
| 442 | * controller is currently playing the second period. When it finishes, it | 526 | * programs the DMA controller accordingly. |
| 443 | * will jump back to the first descriptor and play the third period. | ||
| 444 | * | ||
| 445 | * There are four reasons we do this: | ||
| 446 | * | ||
| 447 | * 1. The only way to get the DMA controller to automatically restart the | ||
| 448 | * transfer when it gets to the end of the buffer is to use chaining | ||
| 449 | * mode. Basic direct mode doesn't offer that feature. | ||
| 450 | * 2. We need to receive an interrupt at the end of every period. The DMA | ||
| 451 | * controller can generate an interrupt at the end of every link transfer | ||
| 452 | * (aka segment). Making each period into a DMA segment will give us the | ||
| 453 | * interrupts we need. | ||
| 454 | * 3. By creating only two link descriptors, regardless of the number of | ||
| 455 | * periods, we do not need to reallocate the link descriptors if the | ||
| 456 | * number of periods changes. | ||
| 457 | * 4. All of the audio data is still stored in a single, contiguous DMA | ||
| 458 | * buffer, which is what ALSA expects. We're just dividing it into | ||
| 459 | * contiguous parts, and creating a link descriptor for each one. | ||
| 460 | * | 527 | * |
| 461 | * Note that due to a quirk of the SSI's STX register, the target address | 528 | * Note that due to a quirk of the SSI's STX register, the target address |
| 462 | * for the DMA operations depends on the sample size. So we don't program | 529 | * for the DMA operations depends on the sample size. So we don't program |
| @@ -468,11 +535,8 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, | |||
| 468 | { | 535 | { |
| 469 | struct snd_pcm_runtime *runtime = substream->runtime; | 536 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 470 | struct fsl_dma_private *dma_private = runtime->private_data; | 537 | struct fsl_dma_private *dma_private = runtime->private_data; |
| 471 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; | ||
| 472 | 538 | ||
| 473 | dma_addr_t temp_addr; /* Pointer to next period */ | 539 | dma_addr_t temp_addr; /* Pointer to next period */ |
| 474 | u64 temp_link; /* Pointer to next link descriptor */ | ||
| 475 | u32 mr; /* Temporary variable for MR register */ | ||
| 476 | 540 | ||
| 477 | unsigned int i; | 541 | unsigned int i; |
| 478 | 542 | ||
| @@ -490,8 +554,6 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, | |||
| 490 | dma_private->dma_buf_next = dma_private->dma_buf_phys; | 554 | dma_private->dma_buf_next = dma_private->dma_buf_phys; |
| 491 | 555 | ||
| 492 | /* | 556 | /* |
| 493 | * Initialize each link descriptor. | ||
| 494 | * | ||
| 495 | * The actual address in STX0 (destination for playback, source for | 557 | * The actual address in STX0 (destination for playback, source for |
| 496 | * capture) is based on the sample size, but we don't know the sample | 558 | * capture) is based on the sample size, but we don't know the sample |
| 497 | * size in this function, so we'll have to adjust that later. See | 559 | * size in this function, so we'll have to adjust that later. See |
| @@ -507,16 +569,11 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, | |||
| 507 | * buffer itself. | 569 | * buffer itself. |
| 508 | */ | 570 | */ |
| 509 | temp_addr = substream->dma_buffer.addr; | 571 | temp_addr = substream->dma_buffer.addr; |
| 510 | temp_link = dma_private->ld_buf_phys + | ||
| 511 | sizeof(struct fsl_dma_link_descriptor); | ||
| 512 | 572 | ||
| 513 | for (i = 0; i < NUM_DMA_LINKS; i++) { | 573 | for (i = 0; i < NUM_DMA_LINKS; i++) { |
| 514 | struct fsl_dma_link_descriptor *link = &dma_private->link[i]; | 574 | struct fsl_dma_link_descriptor *link = &dma_private->link[i]; |
| 515 | 575 | ||
| 516 | link->count = cpu_to_be32(period_size); | 576 | link->count = cpu_to_be32(period_size); |
| 517 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); | ||
| 518 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); | ||
| 519 | link->next = cpu_to_be64(temp_link); | ||
| 520 | 577 | ||
| 521 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 578 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 522 | link->source_addr = cpu_to_be32(temp_addr); | 579 | link->source_addr = cpu_to_be32(temp_addr); |
| @@ -524,51 +581,7 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, | |||
| 524 | link->dest_addr = cpu_to_be32(temp_addr); | 581 | link->dest_addr = cpu_to_be32(temp_addr); |
| 525 | 582 | ||
| 526 | temp_addr += period_size; | 583 | temp_addr += period_size; |
| 527 | temp_link += sizeof(struct fsl_dma_link_descriptor); | ||
| 528 | } | 584 | } |
| 529 | /* The last link descriptor points to the first */ | ||
| 530 | dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); | ||
| 531 | |||
| 532 | /* Tell the DMA controller where the first link descriptor is */ | ||
| 533 | out_be32(&dma_channel->clndar, | ||
| 534 | CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); | ||
| 535 | out_be32(&dma_channel->eclndar, | ||
| 536 | CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); | ||
| 537 | |||
| 538 | /* The manual says the BCR must be clear before enabling EMP */ | ||
| 539 | out_be32(&dma_channel->bcr, 0); | ||
| 540 | |||
| 541 | /* | ||
| 542 | * Program the mode register for interrupts, external master control, | ||
| 543 | * and source/destination hold. Also clear the Channel Abort bit. | ||
| 544 | */ | ||
| 545 | mr = in_be32(&dma_channel->mr) & | ||
| 546 | ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); | ||
| 547 | |||
| 548 | /* | ||
| 549 | * We want External Master Start and External Master Pause enabled, | ||
| 550 | * because the SSI is controlling the DMA controller. We want the DMA | ||
| 551 | * controller to be set up in advance, and then we signal only the SSI | ||
| 552 | * to start transfering. | ||
| 553 | * | ||
| 554 | * We want End-Of-Segment Interrupts enabled, because this will generate | ||
| 555 | * an interrupt at the end of each segment (each link descriptor | ||
| 556 | * represents one segment). Each DMA segment is the same thing as an | ||
| 557 | * ALSA period, so this is how we get an interrupt at the end of every | ||
| 558 | * period. | ||
| 559 | * | ||
| 560 | * We want Error Interrupt enabled, so that we can get an error if | ||
| 561 | * the DMA controller is mis-programmed somehow. | ||
| 562 | */ | ||
| 563 | mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | | ||
| 564 | CCSR_DMA_MR_EMS_EN; | ||
| 565 | |||
| 566 | /* For playback, we want the destination address to be held. For | ||
| 567 | capture, set the source address to be held. */ | ||
| 568 | mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? | ||
| 569 | CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; | ||
| 570 | |||
| 571 | out_be32(&dma_channel->mr, mr); | ||
| 572 | 585 | ||
| 573 | return 0; | 586 | return 0; |
| 574 | } | 587 | } |