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-rw-r--r--drivers/gpu/drm/drm_cache.c2
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c23
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c38
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h44
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c19
-rw-r--r--drivers/gpu/drm/i915/i915_gem_dmabuf.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c6
-rw-r--r--drivers/gpu/drm/i915/i915_gem_stolen.c69
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c222
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h116
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c16
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c50
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1173
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c418
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h138
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c3
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c43
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c41
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c42
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c99
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c69
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c243
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c14
-rw-r--r--include/drm/drm_fb_helper.h4
-rw-r--r--include/linux/scatterlist.h28
-rw-r--r--lib/scatterlist.c4
28 files changed, 1848 insertions, 1086 deletions
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index bc8edbeca3fd..bb8f58012189 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -109,7 +109,7 @@ drm_clflush_sg(struct sg_table *st)
109 109
110 mb(); 110 mb();
111 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) 111 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
112 drm_clflush_page(sg_iter.page); 112 drm_clflush_page(sg_page_iter_page(&sg_iter));
113 mb(); 113 mb();
114 114
115 return; 115 return;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 59d6b9bf204b..6764dce44e84 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1398,7 +1398,7 @@ static void drm_setup_crtcs(struct drm_fb_helper *fb_helper)
1398 struct drm_mode_set *modeset; 1398 struct drm_mode_set *modeset;
1399 bool *enabled; 1399 bool *enabled;
1400 int width, height; 1400 int width, height;
1401 int i, ret; 1401 int i;
1402 1402
1403 DRM_DEBUG_KMS("\n"); 1403 DRM_DEBUG_KMS("\n");
1404 1404
@@ -1419,16 +1419,23 @@ static void drm_setup_crtcs(struct drm_fb_helper *fb_helper)
1419 1419
1420 drm_enable_connectors(fb_helper, enabled); 1420 drm_enable_connectors(fb_helper, enabled);
1421 1421
1422 ret = drm_target_cloned(fb_helper, modes, enabled, width, height); 1422 if (!(fb_helper->funcs->initial_config &&
1423 if (!ret) { 1423 fb_helper->funcs->initial_config(fb_helper, crtcs, modes,
1424 ret = drm_target_preferred(fb_helper, modes, enabled, width, height); 1424 enabled, width, height))) {
1425 if (!ret) 1425 memset(modes, 0, dev->mode_config.num_connector*sizeof(modes[0]));
1426 memset(crtcs, 0, dev->mode_config.num_connector*sizeof(crtcs[0]));
1427
1428 if (!drm_target_cloned(fb_helper,
1429 modes, enabled, width, height) &&
1430 !drm_target_preferred(fb_helper,
1431 modes, enabled, width, height))
1426 DRM_ERROR("Unable to find initial modes\n"); 1432 DRM_ERROR("Unable to find initial modes\n");
1427 }
1428 1433
1429 DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n", width, height); 1434 DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n",
1435 width, height);
1430 1436
1431 drm_pick_crtcs(fb_helper, crtcs, modes, 0, width, height); 1437 drm_pick_crtcs(fb_helper, crtcs, modes, 0, width, height);
1438 }
1432 1439
1433 /* need to set the modesets up here for use later */ 1440 /* need to set the modesets up here for use later */
1434 /* fill out the connector<->crtc mappings into the modesets */ 1441 /* fill out the connector<->crtc mappings into the modesets */
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e9497f..4be58e3b8e4f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1630 mutex_init(&dev_priv->rps.hw_lock); 1630 mutex_init(&dev_priv->rps.hw_lock);
1631 mutex_init(&dev_priv->modeset_restore_lock); 1631 mutex_init(&dev_priv->modeset_restore_lock);
1632 1632
1633 dev_priv->num_plane = 1;
1634 if (IS_VALLEYVIEW(dev))
1635 dev_priv->num_plane = 2;
1636
1633 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); 1637 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1634 if (ret) 1638 if (ret)
1635 goto out_gem_unload; 1639 goto out_gem_unload;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0614aff23e76..3b4b9c09a20b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -463,6 +463,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
463static int i915_drm_freeze(struct drm_device *dev) 463static int i915_drm_freeze(struct drm_device *dev)
464{ 464{
465 struct drm_i915_private *dev_priv = dev->dev_private; 465 struct drm_i915_private *dev_priv = dev->dev_private;
466 struct drm_crtc *crtc;
466 467
467 /* ignore lid events during suspend */ 468 /* ignore lid events during suspend */
468 mutex_lock(&dev_priv->modeset_restore_lock); 469 mutex_lock(&dev_priv->modeset_restore_lock);
@@ -486,10 +487,14 @@ static int i915_drm_freeze(struct drm_device *dev)
486 487
487 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 488 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
488 489
489 intel_modeset_disable(dev);
490
491 drm_irq_uninstall(dev); 490 drm_irq_uninstall(dev);
492 dev_priv->enable_hotplug_processing = false; 491 dev_priv->enable_hotplug_processing = false;
492 /*
493 * Disable CRTCs directly since we want to preserve sw state
494 * for _thaw.
495 */
496 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
497 dev_priv->display.crtc_disable(crtc);
493 } 498 }
494 499
495 i915_save_state(dev); 500 i915_save_state(dev);
@@ -545,6 +550,24 @@ void intel_console_resume(struct work_struct *work)
545 console_unlock(); 550 console_unlock();
546} 551}
547 552
553static void intel_resume_hotplug(struct drm_device *dev)
554{
555 struct drm_mode_config *mode_config = &dev->mode_config;
556 struct intel_encoder *encoder;
557
558 mutex_lock(&mode_config->mutex);
559 DRM_DEBUG_KMS("running encoder hotplug functions\n");
560
561 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
562 if (encoder->hot_plug)
563 encoder->hot_plug(encoder);
564
565 mutex_unlock(&mode_config->mutex);
566
567 /* Just fire off a uevent and let userspace tell us what to do */
568 drm_helper_hpd_irq_event(dev);
569}
570
548static int __i915_drm_thaw(struct drm_device *dev) 571static int __i915_drm_thaw(struct drm_device *dev)
549{ 572{
550 struct drm_i915_private *dev_priv = dev->dev_private; 573 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -567,7 +590,10 @@ static int __i915_drm_thaw(struct drm_device *dev)
567 drm_irq_install(dev); 590 drm_irq_install(dev);
568 591
569 intel_modeset_init_hw(dev); 592 intel_modeset_init_hw(dev);
570 intel_modeset_setup_hw_state(dev, false); 593
594 drm_modeset_lock_all(dev);
595 intel_modeset_setup_hw_state(dev, true);
596 drm_modeset_unlock_all(dev);
571 597
572 /* 598 /*
573 * ... but also need to make sure that hotplug processing 599 * ... but also need to make sure that hotplug processing
@@ -577,6 +603,8 @@ static int __i915_drm_thaw(struct drm_device *dev)
577 * */ 603 * */
578 intel_hpd_init(dev); 604 intel_hpd_init(dev);
579 dev_priv->enable_hotplug_processing = true; 605 dev_priv->enable_hotplug_processing = true;
606 /* Config may have changed between suspend and resume */
607 intel_resume_hotplug(dev);
580 } 608 }
581 609
582 intel_opregion_init(dev); 610 intel_opregion_init(dev);
@@ -721,6 +749,7 @@ static int ironlake_do_reset(struct drm_device *dev)
721 int ret; 749 int ret;
722 750
723 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); 751 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
752 gdrst &= ~GRDOM_MASK;
724 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 753 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
725 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); 754 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
726 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); 755 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
@@ -729,6 +758,7 @@ static int ironlake_do_reset(struct drm_device *dev)
729 758
730 /* We can't reset render&media without also resetting display ... */ 759 /* We can't reset render&media without also resetting display ... */
731 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); 760 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
761 gdrst &= ~GRDOM_MASK;
732 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 762 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
733 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); 763 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
734 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); 764 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
@@ -792,7 +822,7 @@ int intel_gpu_reset(struct drm_device *dev)
792 822
793 /* Also reset the gpu hangman. */ 823 /* Also reset the gpu hangman. */
794 if (dev_priv->gpu_error.stop_rings) { 824 if (dev_priv->gpu_error.stop_rings) {
795 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); 825 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
796 dev_priv->gpu_error.stop_rings = 0; 826 dev_priv->gpu_error.stop_rings = 0;
797 if (ret == -ENODEV) { 827 if (ret == -ENODEV) {
798 DRM_ERROR("Reset not implemented, but ignoring " 828 DRM_ERROR("Reset not implemented, but ignoring "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 625cccf5a4d1..44fca0b69473 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -86,6 +86,19 @@ enum port {
86}; 86};
87#define port_name(p) ((p) + 'A') 87#define port_name(p) ((p) + 'A')
88 88
89enum hpd_pin {
90 HPD_NONE = 0,
91 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
92 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
93 HPD_CRT,
94 HPD_SDVO_B,
95 HPD_SDVO_C,
96 HPD_PORT_B,
97 HPD_PORT_C,
98 HPD_PORT_D,
99 HPD_NUM_PINS
100};
101
89#define I915_GEM_GPU_DOMAINS \ 102#define I915_GEM_GPU_DOMAINS \
90 (I915_GEM_DOMAIN_RENDER | \ 103 (I915_GEM_DOMAIN_RENDER | \
91 I915_GEM_DOMAIN_SAMPLER | \ 104 I915_GEM_DOMAIN_SAMPLER | \
@@ -271,6 +284,9 @@ struct drm_i915_error_state {
271 struct intel_display_error_state *display; 284 struct intel_display_error_state *display;
272}; 285};
273 286
287struct intel_crtc_config;
288struct intel_crtc;
289
274struct drm_i915_display_funcs { 290struct drm_i915_display_funcs {
275 bool (*fbc_enabled)(struct drm_device *dev); 291 bool (*fbc_enabled)(struct drm_device *dev);
276 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 292 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
@@ -283,9 +299,11 @@ struct drm_i915_display_funcs {
283 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 299 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
284 struct drm_display_mode *mode); 300 struct drm_display_mode *mode);
285 void (*modeset_global_resources)(struct drm_device *dev); 301 void (*modeset_global_resources)(struct drm_device *dev);
302 /* Returns the active state of the crtc, and if the crtc is active,
303 * fills out the pipe-config with the hw state. */
304 bool (*get_pipe_config)(struct intel_crtc *,
305 struct intel_crtc_config *);
286 int (*crtc_mode_set)(struct drm_crtc *crtc, 306 int (*crtc_mode_set)(struct drm_crtc *crtc,
287 struct drm_display_mode *mode,
288 struct drm_display_mode *adjusted_mode,
289 int x, int y, 307 int x, int y,
290 struct drm_framebuffer *old_fb); 308 struct drm_framebuffer *old_fb);
291 void (*crtc_enable)(struct drm_crtc *crtc); 309 void (*crtc_enable)(struct drm_crtc *crtc);
@@ -909,11 +927,11 @@ typedef struct drm_i915_private {
909 u32 irq_mask; 927 u32 irq_mask;
910 u32 gt_irq_mask; 928 u32 gt_irq_mask;
911 929
912 u32 hotplug_supported_mask;
913 struct work_struct hotplug_work; 930 struct work_struct hotplug_work;
914 bool enable_hotplug_processing; 931 bool enable_hotplug_processing;
915 932
916 int num_pch_pll; 933 int num_pch_pll;
934 int num_plane;
917 935
918 unsigned long cfb_size; 936 unsigned long cfb_size;
919 unsigned int cfb_fb; 937 unsigned int cfb_fb;
@@ -927,9 +945,14 @@ typedef struct drm_i915_private {
927 struct intel_overlay *overlay; 945 struct intel_overlay *overlay;
928 unsigned int sprite_scaling_enabled; 946 unsigned int sprite_scaling_enabled;
929 947
948 /* backlight */
949 struct {
950 int level;
951 bool enabled;
952 struct backlight_device *device;
953 } backlight;
954
930 /* LVDS info */ 955 /* LVDS info */
931 int backlight_level; /* restore backlight to this value */
932 bool backlight_enabled;
933 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 956 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
934 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 957 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
935 958
@@ -1031,8 +1054,6 @@ typedef struct drm_i915_private {
1031 */ 1054 */
1032 struct work_struct console_resume_work; 1055 struct work_struct console_resume_work;
1033 1056
1034 struct backlight_device *backlight;
1035
1036 struct drm_property *broadcast_rgb_property; 1057 struct drm_property *broadcast_rgb_property;
1037 struct drm_property *force_audio_property; 1058 struct drm_property *force_audio_property;
1038 1059
@@ -1532,7 +1553,7 @@ static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *
1532 struct sg_page_iter sg_iter; 1553 struct sg_page_iter sg_iter;
1533 1554
1534 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 1555 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1535 return sg_iter.page; 1556 return sg_page_iter_page(&sg_iter);
1536 1557
1537 return NULL; 1558 return NULL;
1538} 1559}
@@ -1713,6 +1734,11 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1713void i915_gem_cleanup_stolen(struct drm_device *dev); 1734void i915_gem_cleanup_stolen(struct drm_device *dev);
1714struct drm_i915_gem_object * 1735struct drm_i915_gem_object *
1715i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 1736i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1737struct drm_i915_gem_object *
1738i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1739 u32 stolen_offset,
1740 u32 gtt_offset,
1741 u32 size);
1716void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 1742void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1717 1743
1718/* i915_gem_tiling.c */ 1744/* i915_gem_tiling.c */
@@ -1843,6 +1869,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1843 1869
1844int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1870int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1845int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1871int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1872int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1873int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1846 1874
1847#define __i915_read(x, y) \ 1875#define __i915_read(x, y) \
1848 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1876 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8a2cbee491a2..911bd40ef513 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -442,7 +442,7 @@ i915_gem_shmem_pread(struct drm_device *dev,
442 442
443 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 443 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
444 offset >> PAGE_SHIFT) { 444 offset >> PAGE_SHIFT) {
445 struct page *page = sg_iter.page; 445 struct page *page = sg_page_iter_page(&sg_iter);
446 446
447 if (remain <= 0) 447 if (remain <= 0)
448 break; 448 break;
@@ -765,7 +765,7 @@ i915_gem_shmem_pwrite(struct drm_device *dev,
765 765
766 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 766 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
767 offset >> PAGE_SHIFT) { 767 offset >> PAGE_SHIFT) {
768 struct page *page = sg_iter.page; 768 struct page *page = sg_page_iter_page(&sg_iter);
769 int partial_cacheline_write; 769 int partial_cacheline_write;
770 770
771 if (remain <= 0) 771 if (remain <= 0)
@@ -1647,7 +1647,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1647 obj->dirty = 0; 1647 obj->dirty = 0;
1648 1648
1649 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { 1649 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1650 struct page *page = sg_iter.page; 1650 struct page *page = sg_page_iter_page(&sg_iter);
1651 1651
1652 if (obj->dirty) 1652 if (obj->dirty)
1653 set_page_dirty(page); 1653 set_page_dirty(page);
@@ -1827,7 +1827,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1827err_pages: 1827err_pages:
1828 sg_mark_end(sg); 1828 sg_mark_end(sg);
1829 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) 1829 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1830 page_cache_release(sg_iter.page); 1830 page_cache_release(sg_page_iter_page(&sg_iter));
1831 sg_free_table(st); 1831 sg_free_table(st);
1832 kfree(st); 1832 kfree(st);
1833 return PTR_ERR(page); 1833 return PTR_ERR(page);
@@ -2128,11 +2128,11 @@ static void i915_gem_reset_fences(struct drm_device *dev)
2128 for (i = 0; i < dev_priv->num_fence_regs; i++) { 2128 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2129 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; 2129 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2130 2130
2131 i915_gem_write_fence(dev, i, NULL);
2132
2133 if (reg->obj) 2131 if (reg->obj)
2134 i915_gem_object_fence_lost(reg->obj); 2132 i915_gem_object_fence_lost(reg->obj);
2135 2133
2134 i915_gem_write_fence(dev, i, NULL);
2135
2136 reg->pin_count = 0; 2136 reg->pin_count = 0;
2137 reg->obj = NULL; 2137 reg->obj = NULL;
2138 INIT_LIST_HEAD(&reg->lru_list); 2138 INIT_LIST_HEAD(&reg->lru_list);
@@ -2722,6 +2722,7 @@ int
2722i915_gem_object_put_fence(struct drm_i915_gem_object *obj) 2722i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2723{ 2723{
2724 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2724 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2725 struct drm_i915_fence_reg *fence;
2725 int ret; 2726 int ret;
2726 2727
2727 ret = i915_gem_object_wait_fence(obj); 2728 ret = i915_gem_object_wait_fence(obj);
@@ -2731,10 +2732,10 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2731 if (obj->fence_reg == I915_FENCE_REG_NONE) 2732 if (obj->fence_reg == I915_FENCE_REG_NONE)
2732 return 0; 2733 return 0;
2733 2734
2734 i915_gem_object_update_fence(obj, 2735 fence = &dev_priv->fence_regs[obj->fence_reg];
2735 &dev_priv->fence_regs[obj->fence_reg], 2736
2736 false);
2737 i915_gem_object_fence_lost(obj); 2737 i915_gem_object_fence_lost(obj);
2738 i915_gem_object_update_fence(obj, fence, false);
2738 2739
2739 return 0; 2740 return 0;
2740} 2741}
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 898615d2d5e2..c6dfc1466e3a 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -130,7 +130,7 @@ static void *i915_gem_dmabuf_vmap(struct dma_buf *dma_buf)
130 130
131 i = 0; 131 i = 0;
132 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0); 132 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0);
133 pages[i++] = sg_iter.page; 133 pages[i++] = sg_page_iter_page(&sg_iter);
134 134
135 obj->dma_buf_vmapping = vmap(pages, i, 0, PAGE_KERNEL); 135 obj->dma_buf_vmapping = vmap(pages, i, 0, PAGE_KERNEL);
136 drm_free_large(pages); 136 drm_free_large(pages);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4cbae7bbb833..24a23b31b55f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -123,8 +123,7 @@ static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
123 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { 123 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
124 dma_addr_t page_addr; 124 dma_addr_t page_addr;
125 125
126 page_addr = sg_dma_address(sg_iter.sg) + 126 page_addr = sg_page_iter_dma_address(&sg_iter);
127 (sg_iter.sg_pgoffset << PAGE_SHIFT);
128 pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr, 127 pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
129 cache_level); 128 cache_level);
130 if (++act_pte == I915_PPGTT_PT_ENTRIES) { 129 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
@@ -424,8 +423,7 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev,
424 dma_addr_t addr; 423 dma_addr_t addr;
425 424
426 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 425 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
427 addr = sg_dma_address(sg_iter.sg) + 426 addr = sg_page_iter_dma_address(&sg_iter);
428 (sg_iter.sg_pgoffset << PAGE_SHIFT);
429 iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]); 427 iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
430 i++; 428 i++;
431 } 429 }
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index efaaba5c4194..130d1db27e28 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -222,8 +222,8 @@ i915_pages_create_for_stolen(struct drm_device *dev,
222 } 222 }
223 223
224 sg = st->sgl; 224 sg = st->sgl;
225 /* we set the dummy page here only to make for_each_sg_page work */ 225 sg->offset = offset;
226 sg_set_page(sg, dev_priv->gtt.scratch_page, size, offset); 226 sg->length = size;
227 227
228 sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset; 228 sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset;
229 sg_dma_len(sg) = size; 229 sg_dma_len(sg) = size;
@@ -312,6 +312,71 @@ i915_gem_object_create_stolen(struct drm_device *dev, u32 size)
312 return NULL; 312 return NULL;
313} 313}
314 314
315struct drm_i915_gem_object *
316i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
317 u32 stolen_offset,
318 u32 gtt_offset,
319 u32 size)
320{
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 struct drm_i915_gem_object *obj;
323 struct drm_mm_node *stolen;
324
325 if (dev_priv->mm.stolen_base == 0)
326 return NULL;
327
328 DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x\n",
329 stolen_offset, gtt_offset, size);
330
331 /* KISS and expect everything to be page-aligned */
332 BUG_ON(stolen_offset & 4095);
333 BUG_ON(gtt_offset & 4095);
334 BUG_ON(size & 4095);
335
336 if (WARN_ON(size == 0))
337 return NULL;
338
339 stolen = drm_mm_create_block(&dev_priv->mm.stolen,
340 stolen_offset, size,
341 false);
342 if (stolen == NULL) {
343 DRM_DEBUG_KMS("failed to allocate stolen space\n");
344 return NULL;
345 }
346
347 obj = _i915_gem_object_create_stolen(dev, stolen);
348 if (obj == NULL) {
349 DRM_DEBUG_KMS("failed to allocate stolen object\n");
350 drm_mm_put_block(stolen);
351 return NULL;
352 }
353
354 /* To simplify the initialisation sequence between KMS and GTT,
355 * we allow construction of the stolen object prior to
356 * setting up the GTT space. The actual reservation will occur
357 * later.
358 */
359 if (drm_mm_initialized(&dev_priv->mm.gtt_space)) {
360 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
361 gtt_offset, size,
362 false);
363 if (obj->gtt_space == NULL) {
364 DRM_DEBUG_KMS("failed to allocate stolen GTT space\n");
365 drm_gem_object_unreference(&obj->base);
366 return NULL;
367 }
368 } else
369 obj->gtt_space = I915_GTT_RESERVED;
370
371 obj->gtt_offset = gtt_offset;
372 obj->has_global_gtt_mapping = 1;
373
374 list_add_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
375 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
376
377 return obj;
378}
379
315void 380void
316i915_gem_object_release_stolen(struct drm_i915_gem_object *obj) 381i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
317{ 382{
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index f799708bcb85..c807eb93755b 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -481,7 +481,7 @@ i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
481 481
482 i = 0; 482 i = 0;
483 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { 483 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
484 struct page *page = sg_iter.page; 484 struct page *page = sg_page_iter_page(&sg_iter);
485 char new_bit_17 = page_to_phys(page) >> 17; 485 char new_bit_17 = page_to_phys(page) >> 17;
486 if ((new_bit_17 & 0x1) != 486 if ((new_bit_17 & 0x1) !=
487 (test_bit(i, obj->bit_17) != 0)) { 487 (test_bit(i, obj->bit_17) != 0)) {
@@ -511,7 +511,7 @@ i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
511 511
512 i = 0; 512 i = 0;
513 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { 513 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
514 if (page_to_phys(sg_iter.page) & (1 << 17)) 514 if (page_to_phys(sg_page_iter_page(&sg_iter)) & (1 << 17))
515 __set_bit(i, obj->bit_17); 515 __set_bit(i, obj->bit_17);
516 else 516 else
517 __clear_bit(i, obj->bit_17); 517 __clear_bit(i, obj->bit_17);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5fc178e1e515..4c5bdd037388 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -36,6 +36,60 @@
36#include "i915_trace.h" 36#include "i915_trace.h"
37#include "intel_drv.h" 37#include "intel_drv.h"
38 38
39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
73static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
82static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
91
92
39/* For display hotplug interrupt */ 93/* For display hotplug interrupt */
40static void 94static void
41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 95ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
@@ -47,7 +101,7 @@ ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
47 } 101 }
48} 102}
49 103
50static inline void 104static void
51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 105ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
52{ 106{
53 if ((dev_priv->irq_mask & mask) != mask) { 107 if ((dev_priv->irq_mask & mask) != mask) {
@@ -599,7 +653,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
599 653
600 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 654 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
601 hotplug_status); 655 hotplug_status);
602 if (hotplug_status & dev_priv->hotplug_supported_mask) 656 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
603 queue_work(dev_priv->wq, 657 queue_work(dev_priv->wq,
604 &dev_priv->hotplug_work); 658 &dev_priv->hotplug_work);
605 659
@@ -1387,8 +1441,9 @@ static void i915_capture_error_state(struct drm_device *dev)
1387 else if (INTEL_INFO(dev)->gen == 6) 1441 else if (INTEL_INFO(dev)->gen == 6)
1388 error->forcewake = I915_READ(FORCEWAKE); 1442 error->forcewake = I915_READ(FORCEWAKE);
1389 1443
1390 for_each_pipe(pipe) 1444 if (!HAS_PCH_SPLIT(dev))
1391 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1445 for_each_pipe(pipe)
1446 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1392 1447
1393 if (INTEL_INFO(dev)->gen >= 6) { 1448 if (INTEL_INFO(dev)->gen >= 6) {
1394 error->error = I915_READ(ERROR_GEN6); 1449 error->error = I915_READ(ERROR_GEN6);
@@ -1974,7 +2029,13 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
1974 2029
1975 /* south display irq */ 2030 /* south display irq */
1976 I915_WRITE(SDEIMR, 0xffffffff); 2031 I915_WRITE(SDEIMR, 0xffffffff);
1977 I915_WRITE(SDEIER, 0x0); 2032 /*
2033 * SDEIER is also touched by the interrupt handler to work around missed
2034 * PCH interrupts. Hence we can't update it after the interrupt handler
2035 * is enabled - instead we unconditionally enable all PCH interrupt
2036 * sources here, but then only unmask them as needed with SDEIMR.
2037 */
2038 I915_WRITE(SDEIER, 0xffffffff);
1978 POSTING_READ(SDEIER); 2039 POSTING_READ(SDEIER);
1979} 2040}
1980 2041
@@ -2010,18 +2071,30 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
2010 POSTING_READ(VLV_IER); 2071 POSTING_READ(VLV_IER);
2011} 2072}
2012 2073
2013/* 2074static void ibx_hpd_irq_setup(struct drm_device *dev)
2014 * Enable digital hotplug on the PCH, and configure the DP short pulse
2015 * duration to 2ms (which is the minimum in the Display Port spec)
2016 *
2017 * This register is the same on all known PCH chips.
2018 */
2019
2020static void ibx_enable_hotplug(struct drm_device *dev)
2021{ 2075{
2022 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2076 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2023 u32 hotplug; 2077 struct drm_mode_config *mode_config = &dev->mode_config;
2078 struct intel_encoder *intel_encoder;
2079 u32 mask = ~I915_READ(SDEIMR);
2080 u32 hotplug;
2081
2082 if (HAS_PCH_IBX(dev)) {
2083 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2084 mask |= hpd_ibx[intel_encoder->hpd_pin];
2085 } else {
2086 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2087 mask |= hpd_cpt[intel_encoder->hpd_pin];
2088 }
2089
2090 I915_WRITE(SDEIMR, ~mask);
2024 2091
2092 /*
2093 * Enable digital hotplug on the PCH, and configure the DP short pulse
2094 * duration to 2ms (which is the minimum in the Display Port spec)
2095 *
2096 * This register is the same on all known PCH chips.
2097 */
2025 hotplug = I915_READ(PCH_PORT_HOTPLUG); 2098 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2026 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 2099 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2027 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 2100 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
@@ -2036,20 +2109,11 @@ static void ibx_irq_postinstall(struct drm_device *dev)
2036 u32 mask; 2109 u32 mask;
2037 2110
2038 if (HAS_PCH_IBX(dev)) 2111 if (HAS_PCH_IBX(dev))
2039 mask = SDE_HOTPLUG_MASK | 2112 mask = SDE_GMBUS | SDE_AUX_MASK;
2040 SDE_GMBUS |
2041 SDE_AUX_MASK;
2042 else 2113 else
2043 mask = SDE_HOTPLUG_MASK_CPT | 2114 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2044 SDE_GMBUS_CPT |
2045 SDE_AUX_MASK_CPT;
2046
2047 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2115 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2048 I915_WRITE(SDEIMR, ~mask); 2116 I915_WRITE(SDEIMR, ~mask);
2049 I915_WRITE(SDEIER, mask);
2050 POSTING_READ(SDEIER);
2051
2052 ibx_enable_hotplug(dev);
2053} 2117}
2054 2118
2055static int ironlake_irq_postinstall(struct drm_device *dev) 2119static int ironlake_irq_postinstall(struct drm_device *dev)
@@ -2203,30 +2267,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
2203 return 0; 2267 return 0;
2204} 2268}
2205 2269
2206static void valleyview_hpd_irq_setup(struct drm_device *dev)
2207{
2208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2209 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2210
2211 /* Note HDMI and DP share bits */
2212 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2213 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2214 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2215 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2216 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2217 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2218 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2219 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2220 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2221 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2222 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2223 hotplug_en |= CRT_HOTPLUG_INT_EN;
2224 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2225 }
2226
2227 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2228}
2229
2230static void valleyview_irq_uninstall(struct drm_device *dev) 2270static void valleyview_irq_uninstall(struct drm_device *dev)
2231{ 2271{
2232 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2272 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2487,35 +2527,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
2487 return 0; 2527 return 0;
2488} 2528}
2489 2529
2490static void i915_hpd_irq_setup(struct drm_device *dev)
2491{
2492 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2493 u32 hotplug_en;
2494
2495 if (I915_HAS_HOTPLUG(dev)) {
2496 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2497
2498 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2499 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2500 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2501 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2502 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2503 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2504 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2505 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2506 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2507 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2508 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2509 hotplug_en |= CRT_HOTPLUG_INT_EN;
2510 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2511 }
2512
2513 /* Ignore TV since it's buggy */
2514
2515 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2516 }
2517}
2518
2519/* 2530/*
2520 * Returns true when a page flip has completed. 2531 * Returns true when a page flip has completed.
2521 */ 2532 */
@@ -2599,7 +2610,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
2599 2610
2600 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2611 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2601 hotplug_status); 2612 hotplug_status);
2602 if (hotplug_status & dev_priv->hotplug_supported_mask) 2613 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
2603 queue_work(dev_priv->wq, 2614 queue_work(dev_priv->wq,
2604 &dev_priv->hotplug_work); 2615 &dev_priv->hotplug_work);
2605 2616
@@ -2745,45 +2756,32 @@ static int i965_irq_postinstall(struct drm_device *dev)
2745 return 0; 2756 return 0;
2746} 2757}
2747 2758
2748static void i965_hpd_irq_setup(struct drm_device *dev) 2759static void i915_hpd_irq_setup(struct drm_device *dev)
2749{ 2760{
2750 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2762 struct drm_mode_config *mode_config = &dev->mode_config;
2763 struct intel_encoder *encoder;
2751 u32 hotplug_en; 2764 u32 hotplug_en;
2752 2765
2753 /* Note HDMI and DP share hotplug bits */ 2766 if (I915_HAS_HOTPLUG(dev)) {
2754 hotplug_en = 0; 2767 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2755 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) 2768 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2756 hotplug_en |= PORTB_HOTPLUG_INT_EN; 2769 /* Note HDMI and DP share hotplug bits */
2757 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) 2770 /* enable bits are the same for all generations */
2758 hotplug_en |= PORTC_HOTPLUG_INT_EN; 2771 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
2759 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) 2772 hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
2760 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2761 if (IS_G4X(dev)) {
2762 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2763 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2764 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2765 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2766 } else {
2767 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2768 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2769 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2770 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2771 }
2772 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2773 hotplug_en |= CRT_HOTPLUG_INT_EN;
2774
2775 /* Programming the CRT detection parameters tends 2773 /* Programming the CRT detection parameters tends
2776 to generate a spurious hotplug event about three 2774 to generate a spurious hotplug event about three
2777 seconds later. So just do it once. 2775 seconds later. So just do it once.
2778 */ 2776 */
2779 if (IS_G4X(dev)) 2777 if (IS_G4X(dev))
2780 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 2778 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2779 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2781 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2780 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2782 }
2783 2781
2784 /* Ignore TV since it's buggy */ 2782 /* Ignore TV since it's buggy */
2785 2783 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2786 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2784 }
2787} 2785}
2788 2786
2789static irqreturn_t i965_irq_handler(int irq, void *arg) 2787static irqreturn_t i965_irq_handler(int irq, void *arg)
@@ -2845,7 +2843,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
2845 2843
2846 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2844 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2847 hotplug_status); 2845 hotplug_status);
2848 if (hotplug_status & dev_priv->hotplug_supported_mask) 2846 if (hotplug_status & (IS_G4X(dev) ?
2847 HOTPLUG_INT_STATUS_G4X :
2848 HOTPLUG_INT_STATUS_I965))
2849 queue_work(dev_priv->wq, 2849 queue_work(dev_priv->wq,
2850 &dev_priv->hotplug_work); 2850 &dev_priv->hotplug_work);
2851 2851
@@ -2958,7 +2958,7 @@ void intel_irq_init(struct drm_device *dev)
2958 dev->driver->irq_uninstall = valleyview_irq_uninstall; 2958 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2959 dev->driver->enable_vblank = valleyview_enable_vblank; 2959 dev->driver->enable_vblank = valleyview_enable_vblank;
2960 dev->driver->disable_vblank = valleyview_disable_vblank; 2960 dev->driver->disable_vblank = valleyview_disable_vblank;
2961 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup; 2961 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2962 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 2962 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2963 /* Share pre & uninstall handlers with ILK/SNB */ 2963 /* Share pre & uninstall handlers with ILK/SNB */
2964 dev->driver->irq_handler = ivybridge_irq_handler; 2964 dev->driver->irq_handler = ivybridge_irq_handler;
@@ -2967,6 +2967,7 @@ void intel_irq_init(struct drm_device *dev)
2967 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2967 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2968 dev->driver->enable_vblank = ivybridge_enable_vblank; 2968 dev->driver->enable_vblank = ivybridge_enable_vblank;
2969 dev->driver->disable_vblank = ivybridge_disable_vblank; 2969 dev->driver->disable_vblank = ivybridge_disable_vblank;
2970 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2970 } else if (HAS_PCH_SPLIT(dev)) { 2971 } else if (HAS_PCH_SPLIT(dev)) {
2971 dev->driver->irq_handler = ironlake_irq_handler; 2972 dev->driver->irq_handler = ironlake_irq_handler;
2972 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2973 dev->driver->irq_preinstall = ironlake_irq_preinstall;
@@ -2974,6 +2975,7 @@ void intel_irq_init(struct drm_device *dev)
2974 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2975 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2975 dev->driver->enable_vblank = ironlake_enable_vblank; 2976 dev->driver->enable_vblank = ironlake_enable_vblank;
2976 dev->driver->disable_vblank = ironlake_disable_vblank; 2977 dev->driver->disable_vblank = ironlake_disable_vblank;
2978 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2977 } else { 2979 } else {
2978 if (INTEL_INFO(dev)->gen == 2) { 2980 if (INTEL_INFO(dev)->gen == 2) {
2979 dev->driver->irq_preinstall = i8xx_irq_preinstall; 2981 dev->driver->irq_preinstall = i8xx_irq_preinstall;
@@ -2991,7 +2993,7 @@ void intel_irq_init(struct drm_device *dev)
2991 dev->driver->irq_postinstall = i965_irq_postinstall; 2993 dev->driver->irq_postinstall = i965_irq_postinstall;
2992 dev->driver->irq_uninstall = i965_irq_uninstall; 2994 dev->driver->irq_uninstall = i965_irq_uninstall;
2993 dev->driver->irq_handler = i965_irq_handler; 2995 dev->driver->irq_handler = i965_irq_handler;
2994 dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup; 2996 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2995 } 2997 }
2996 dev->driver->enable_vblank = i915_enable_vblank; 2998 dev->driver->enable_vblank = i915_enable_vblank;
2997 dev->driver->disable_vblank = i915_disable_vblank; 2999 dev->driver->disable_vblank = i915_disable_vblank;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bceca1159137..058686c0dbbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -91,6 +91,7 @@
91#define GRDOM_FULL (0<<2) 91#define GRDOM_FULL (0<<2)
92#define GRDOM_RENDER (1<<2) 92#define GRDOM_RENDER (1<<2)
93#define GRDOM_MEDIA (3<<2) 93#define GRDOM_MEDIA (3<<2)
94#define GRDOM_MASK (3<<2)
94#define GRDOM_RESET_ENABLE (1<<0) 95#define GRDOM_RESET_ENABLE (1<<0)
95 96
96#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 97#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
@@ -1642,6 +1643,12 @@
1642#define SDVOC_HOTPLUG_INT_EN (1 << 25) 1643#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1643#define TV_HOTPLUG_INT_EN (1 << 18) 1644#define TV_HOTPLUG_INT_EN (1 << 18)
1644#define CRT_HOTPLUG_INT_EN (1 << 9) 1645#define CRT_HOTPLUG_INT_EN (1 << 9)
1646#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
1647 PORTC_HOTPLUG_INT_EN | \
1648 PORTD_HOTPLUG_INT_EN | \
1649 SDVOC_HOTPLUG_INT_EN | \
1650 SDVOB_HOTPLUG_INT_EN | \
1651 CRT_HOTPLUG_INT_EN)
1645#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1652#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1646#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1653#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1647/* must use period 64 on GM45 according to docs */ 1654/* must use period 64 on GM45 according to docs */
@@ -1680,6 +1687,26 @@
1680#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1687#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1681#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1688#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1682#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1689#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1690#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
1691 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1692 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1693 PORTB_HOTPLUG_INT_STATUS | \
1694 PORTC_HOTPLUG_INT_STATUS | \
1695 PORTD_HOTPLUG_INT_STATUS)
1696
1697#define HOTPLUG_INT_STATUS_I965 (CRT_HOTPLUG_INT_STATUS | \
1698 SDVOB_HOTPLUG_INT_STATUS_I965 | \
1699 SDVOC_HOTPLUG_INT_STATUS_I965 | \
1700 PORTB_HOTPLUG_INT_STATUS | \
1701 PORTC_HOTPLUG_INT_STATUS | \
1702 PORTD_HOTPLUG_INT_STATUS)
1703
1704#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
1705 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1706 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1707 PORTB_HOTPLUG_INT_STATUS | \
1708 PORTC_HOTPLUG_INT_STATUS | \
1709 PORTD_HOTPLUG_INT_STATUS)
1683 1710
1684/* SDVO and HDMI port control. 1711/* SDVO and HDMI port control.
1685 * The same register may be used for SDVO or HDMI */ 1712 * The same register may be used for SDVO or HDMI */
@@ -3261,6 +3288,63 @@
3261#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 3288#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3262#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 3289#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3263 3290
3291#define _SPACNTR 0x72180
3292#define SP_ENABLE (1<<31)
3293#define SP_GEAMMA_ENABLE (1<<30)
3294#define SP_PIXFORMAT_MASK (0xf<<26)
3295#define SP_FORMAT_YUV422 (0<<26)
3296#define SP_FORMAT_BGR565 (5<<26)
3297#define SP_FORMAT_BGRX8888 (6<<26)
3298#define SP_FORMAT_BGRA8888 (7<<26)
3299#define SP_FORMAT_RGBX1010102 (8<<26)
3300#define SP_FORMAT_RGBA1010102 (9<<26)
3301#define SP_FORMAT_RGBX8888 (0xe<<26)
3302#define SP_FORMAT_RGBA8888 (0xf<<26)
3303#define SP_SOURCE_KEY (1<<22)
3304#define SP_YUV_BYTE_ORDER_MASK (3<<16)
3305#define SP_YUV_ORDER_YUYV (0<<16)
3306#define SP_YUV_ORDER_UYVY (1<<16)
3307#define SP_YUV_ORDER_YVYU (2<<16)
3308#define SP_YUV_ORDER_VYUY (3<<16)
3309#define SP_TILED (1<<10)
3310#define _SPALINOFF 0x72184
3311#define _SPASTRIDE 0x72188
3312#define _SPAPOS 0x7218c
3313#define _SPASIZE 0x72190
3314#define _SPAKEYMINVAL 0x72194
3315#define _SPAKEYMSK 0x72198
3316#define _SPASURF 0x7219c
3317#define _SPAKEYMAXVAL 0x721a0
3318#define _SPATILEOFF 0x721a4
3319#define _SPACONSTALPHA 0x721a8
3320#define _SPAGAMC 0x721f4
3321
3322#define _SPBCNTR 0x72280
3323#define _SPBLINOFF 0x72284
3324#define _SPBSTRIDE 0x72288
3325#define _SPBPOS 0x7228c
3326#define _SPBSIZE 0x72290
3327#define _SPBKEYMINVAL 0x72294
3328#define _SPBKEYMSK 0x72298
3329#define _SPBSURF 0x7229c
3330#define _SPBKEYMAXVAL 0x722a0
3331#define _SPBTILEOFF 0x722a4
3332#define _SPBCONSTALPHA 0x722a8
3333#define _SPBGAMC 0x722f4
3334
3335#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3336#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3337#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3338#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3339#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3340#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3341#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3342#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3343#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3344#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3345#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3346#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3347
3264/* VBIOS regs */ 3348/* VBIOS regs */
3265#define VGACNTRL 0x71400 3349#define VGACNTRL 0x71400
3266# define VGA_DISP_DISABLE (1 << 31) 3350# define VGA_DISP_DISABLE (1 << 31)
@@ -3536,7 +3620,11 @@
3536#define SDE_PORTC_HOTPLUG (1 << 9) 3620#define SDE_PORTC_HOTPLUG (1 << 9)
3537#define SDE_PORTB_HOTPLUG (1 << 8) 3621#define SDE_PORTB_HOTPLUG (1 << 8)
3538#define SDE_SDVOB_HOTPLUG (1 << 6) 3622#define SDE_SDVOB_HOTPLUG (1 << 6)
3539#define SDE_HOTPLUG_MASK (0xf << 8) 3623#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
3624 SDE_SDVOB_HOTPLUG | \
3625 SDE_PORTB_HOTPLUG | \
3626 SDE_PORTC_HOTPLUG | \
3627 SDE_PORTD_HOTPLUG)
3540#define SDE_TRANSB_CRC_DONE (1 << 5) 3628#define SDE_TRANSB_CRC_DONE (1 << 5)
3541#define SDE_TRANSB_CRC_ERR (1 << 4) 3629#define SDE_TRANSB_CRC_ERR (1 << 4)
3542#define SDE_TRANSB_FIFO_UNDER (1 << 3) 3630#define SDE_TRANSB_FIFO_UNDER (1 << 3)
@@ -3559,7 +3647,9 @@
3559#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3647#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3560#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3648#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3561#define SDE_CRT_HOTPLUG_CPT (1 << 19) 3649#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3650#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
3562#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3651#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3652 SDE_SDVOB_HOTPLUG_CPT | \
3563 SDE_PORTD_HOTPLUG_CPT | \ 3653 SDE_PORTD_HOTPLUG_CPT | \
3564 SDE_PORTC_HOTPLUG_CPT | \ 3654 SDE_PORTC_HOTPLUG_CPT | \
3565 SDE_PORTB_HOTPLUG_CPT) 3655 SDE_PORTB_HOTPLUG_CPT)
@@ -4022,6 +4112,15 @@
4022#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 4112#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4023#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 4113#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
4024 4114
4115#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4116#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4117#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4118 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4119#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4120 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4121#define VLV_PIPE_PP_DIVISOR(pipe) \
4122 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4123
4025#define PCH_PP_STATUS 0xc7200 4124#define PCH_PP_STATUS 0xc7200
4026#define PCH_PP_CONTROL 0xc7204 4125#define PCH_PP_CONTROL 0xc7204
4027#define PANEL_UNLOCK_REGS (0xabcd << 16) 4126#define PANEL_UNLOCK_REGS (0xabcd << 16)
@@ -4190,6 +4289,7 @@
4190#define GEN6_RPNSWREQ 0xA008 4289#define GEN6_RPNSWREQ 0xA008
4191#define GEN6_TURBO_DISABLE (1<<31) 4290#define GEN6_TURBO_DISABLE (1<<31)
4192#define GEN6_FREQUENCY(x) ((x)<<25) 4291#define GEN6_FREQUENCY(x) ((x)<<25)
4292#define HSW_FREQUENCY(x) ((x)<<24)
4193#define GEN6_OFFSET(x) ((x)<<19) 4293#define GEN6_OFFSET(x) ((x)<<19)
4194#define GEN6_AGGRESSIVE_TURBO (0<<15) 4294#define GEN6_AGGRESSIVE_TURBO (0<<15)
4195#define GEN6_RC_VIDEO_FREQ 0xA00C 4295#define GEN6_RC_VIDEO_FREQ 0xA00C
@@ -4281,6 +4381,20 @@
4281#define GEN6_PCODE_DATA 0x138128 4381#define GEN6_PCODE_DATA 0x138128
4282#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 4382#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
4283 4383
4384#define VLV_IOSF_DOORBELL_REQ 0x182100
4385#define IOSF_DEVFN_SHIFT 24
4386#define IOSF_OPCODE_SHIFT 16
4387#define IOSF_PORT_SHIFT 8
4388#define IOSF_BYTE_ENABLES_SHIFT 4
4389#define IOSF_BAR_SHIFT 1
4390#define IOSF_SB_BUSY (1<<0)
4391#define IOSF_PORT_PUNIT 0x4
4392#define VLV_IOSF_DATA 0x182104
4393#define VLV_IOSF_ADDR 0x182108
4394
4395#define PUNIT_OPCODE_REG_READ 6
4396#define PUNIT_OPCODE_REG_WRITE 7
4397
4284#define GEN6_GT_CORE_STATUS 0x138060 4398#define GEN6_GT_CORE_STATUS 0x138060
4285#define GEN6_CORE_CPD_STATE_MASK (7<<4) 4399#define GEN6_CORE_CPD_STATE_MASK (7<<4)
4286#define GEN6_RCn_MASK 7 4400#define GEN6_RCn_MASK 7
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1ce45a0a2d3e..1d8d63aff444 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -199,10 +199,14 @@ static int intel_crt_mode_valid(struct drm_connector *connector,
199 return MODE_OK; 199 return MODE_OK;
200} 200}
201 201
202static bool intel_crt_mode_fixup(struct drm_encoder *encoder, 202static bool intel_crt_compute_config(struct intel_encoder *encoder,
203 const struct drm_display_mode *mode, 203 struct intel_crtc_config *pipe_config)
204 struct drm_display_mode *adjusted_mode)
205{ 204{
205 struct drm_device *dev = encoder->base.dev;
206
207 if (HAS_PCH_SPLIT(dev))
208 pipe_config->has_pch_encoder = true;
209
206 return true; 210 return true;
207} 211}
208 212
@@ -676,7 +680,6 @@ static void intel_crt_reset(struct drm_connector *connector)
676 */ 680 */
677 681
678static const struct drm_encoder_helper_funcs crt_encoder_funcs = { 682static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
679 .mode_fixup = intel_crt_mode_fixup,
680 .mode_set = intel_crt_mode_set, 683 .mode_set = intel_crt_mode_set,
681}; 684};
682 685
@@ -768,8 +771,11 @@ void intel_crt_init(struct drm_device *dev)
768 else 771 else
769 crt->adpa_reg = ADPA; 772 crt->adpa_reg = ADPA;
770 773
774 crt->base.compute_config = intel_crt_compute_config;
771 crt->base.disable = intel_disable_crt; 775 crt->base.disable = intel_disable_crt;
772 crt->base.enable = intel_enable_crt; 776 crt->base.enable = intel_enable_crt;
777 if (I915_HAS_HOTPLUG(dev))
778 crt->base.hpd_pin = HPD_CRT;
773 if (HAS_DDI(dev)) 779 if (HAS_DDI(dev))
774 crt->base.get_hw_state = intel_ddi_get_hw_state; 780 crt->base.get_hw_state = intel_ddi_get_hw_state;
775 else 781 else
@@ -791,8 +797,6 @@ void intel_crt_init(struct drm_device *dev)
791 */ 797 */
792 crt->force_hotplug_required = 0; 798 crt->force_hotplug_required = 0;
793 799
794 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
795
796 /* 800 /*
797 * TODO: find a proper way to discover whether we need to set the the 801 * TODO: find a proper way to discover whether we need to set the the
798 * polarity and link reversal bits or not, instead of relying on the 802 * polarity and link reversal bits or not, instead of relying on the
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index bfcc58ffecbb..22524cb6903b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -898,6 +898,9 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
898 plls->spll_refcount++; 898 plls->spll_refcount++;
899 reg = SPLL_CTL; 899 reg = SPLL_CTL;
900 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; 900 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
901 } else {
902 DRM_ERROR("SPLL already in use\n");
903 return false;
901 } 904 }
902 905
903 WARN(I915_READ(reg) & SPLL_PLL_ENABLE, 906 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
@@ -928,7 +931,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
928 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 931 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
929 932
930 temp = TRANS_MSA_SYNC_CLK; 933 temp = TRANS_MSA_SYNC_CLK;
931 switch (intel_crtc->bpp) { 934 switch (intel_crtc->config.pipe_bpp) {
932 case 18: 935 case 18:
933 temp |= TRANS_MSA_6_BPC; 936 temp |= TRANS_MSA_6_BPC;
934 break; 937 break;
@@ -942,15 +945,13 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
942 temp |= TRANS_MSA_12_BPC; 945 temp |= TRANS_MSA_12_BPC;
943 break; 946 break;
944 default: 947 default:
945 temp |= TRANS_MSA_8_BPC; 948 BUG();
946 WARN(1, "%d bpp unsupported by DDI function\n",
947 intel_crtc->bpp);
948 } 949 }
949 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 950 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
950 } 951 }
951} 952}
952 953
953void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) 954void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
954{ 955{
955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
956 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 957 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
@@ -966,7 +967,7 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
966 temp = TRANS_DDI_FUNC_ENABLE; 967 temp = TRANS_DDI_FUNC_ENABLE;
967 temp |= TRANS_DDI_SELECT_PORT(port); 968 temp |= TRANS_DDI_SELECT_PORT(port);
968 969
969 switch (intel_crtc->bpp) { 970 switch (intel_crtc->config.pipe_bpp) {
970 case 18: 971 case 18:
971 temp |= TRANS_DDI_BPC_6; 972 temp |= TRANS_DDI_BPC_6;
972 break; 973 break;
@@ -980,8 +981,7 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
980 temp |= TRANS_DDI_BPC_12; 981 temp |= TRANS_DDI_BPC_12;
981 break; 982 break;
982 default: 983 default:
983 WARN(1, "%d bpp unsupported by transcoder DDI function\n", 984 BUG();
984 intel_crtc->bpp);
985 } 985 }
986 986
987 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 987 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
@@ -1150,14 +1150,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1150 1150
1151 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); 1151 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
1152 1152
1153 return true; 1153 return false;
1154} 1154}
1155 1155
1156static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, 1156static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1157 enum pipe pipe) 1157 enum pipe pipe)
1158{ 1158{
1159 uint32_t temp, ret; 1159 uint32_t temp, ret;
1160 enum port port; 1160 enum port port = I915_MAX_PORTS;
1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe); 1162 pipe);
1163 int i; 1163 int i;
@@ -1173,10 +1173,16 @@ static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1173 port = i; 1173 port = i;
1174 } 1174 }
1175 1175
1176 ret = I915_READ(PORT_CLK_SEL(port)); 1176 if (port == I915_MAX_PORTS) {
1177 1177 WARN(1, "Pipe %c enabled on an unknown port\n",
1178 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", 1178 pipe_name(pipe));
1179 pipe_name(pipe), port_name(port), ret); 1179 ret = PORT_CLK_SEL_NONE;
1180 } else {
1181 ret = I915_READ(PORT_CLK_SEL(port));
1182 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1183 "0x%08x\n", pipe_name(pipe), port_name(port),
1184 ret);
1185 }
1180 1186
1181 return ret; 1187 return ret;
1182} 1188}
@@ -1467,19 +1473,17 @@ static void intel_ddi_destroy(struct drm_encoder *encoder)
1467 intel_dp_encoder_destroy(encoder); 1473 intel_dp_encoder_destroy(encoder);
1468} 1474}
1469 1475
1470static bool intel_ddi_mode_fixup(struct drm_encoder *encoder, 1476static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1471 const struct drm_display_mode *mode, 1477 struct intel_crtc_config *pipe_config)
1472 struct drm_display_mode *adjusted_mode)
1473{ 1478{
1474 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1479 int type = encoder->type;
1475 int type = intel_encoder->type;
1476 1480
1477 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n"); 1481 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1478 1482
1479 if (type == INTEL_OUTPUT_HDMI) 1483 if (type == INTEL_OUTPUT_HDMI)
1480 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode); 1484 return intel_hdmi_compute_config(encoder, pipe_config);
1481 else 1485 else
1482 return intel_dp_mode_fixup(encoder, mode, adjusted_mode); 1486 return intel_dp_compute_config(encoder, pipe_config);
1483} 1487}
1484 1488
1485static const struct drm_encoder_funcs intel_ddi_funcs = { 1489static const struct drm_encoder_funcs intel_ddi_funcs = {
@@ -1487,7 +1491,6 @@ static const struct drm_encoder_funcs intel_ddi_funcs = {
1487}; 1491};
1488 1492
1489static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = { 1493static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1490 .mode_fixup = intel_ddi_mode_fixup,
1491 .mode_set = intel_ddi_mode_set, 1494 .mode_set = intel_ddi_mode_set,
1492}; 1495};
1493 1496
@@ -1527,6 +1530,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
1527 DRM_MODE_ENCODER_TMDS); 1530 DRM_MODE_ENCODER_TMDS);
1528 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs); 1531 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1529 1532
1533 intel_encoder->compute_config = intel_ddi_compute_config;
1530 intel_encoder->enable = intel_enable_ddi; 1534 intel_encoder->enable = intel_enable_ddi;
1531 intel_encoder->pre_enable = intel_ddi_pre_enable; 1535 intel_encoder->pre_enable = intel_ddi_pre_enable;
1532 intel_encoder->disable = intel_disable_ddi; 1536 intel_encoder->disable = intel_disable_ddi;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 14bfbed81b48..b7005640144c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1288,6 +1288,25 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1288 } 1288 }
1289} 1289}
1290 1290
1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{ 1311{
1293 u32 val; 1312 u32 val;
@@ -1872,6 +1891,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1872 * or we might hang the display. 1891 * or we might hang the display.
1873 */ 1892 */
1874 assert_planes_disabled(dev_priv, pipe); 1893 assert_planes_disabled(dev_priv, pipe);
1894 assert_sprites_disabled(dev_priv, pipe);
1875 1895
1876 /* Don't disable pipe A or pipe A PLLs if needed */ 1896 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
@@ -1950,6 +1970,15 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
1950 intel_wait_for_vblank(dev_priv->dev, pipe); 1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1951} 1971}
1952 1972
1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
1953int 1982int
1954intel_pin_and_fence_fb_obj(struct drm_device *dev, 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
1955 struct drm_i915_gem_object *obj, 1984 struct drm_i915_gem_object *obj,
@@ -1980,6 +2009,14 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
1980 BUG(); 2009 BUG();
1981 } 2010 }
1982 2011
2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
1983 dev_priv->mm.interruptible = false; 2020 dev_priv->mm.interruptible = false;
1984 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1985 if (ret) 2022 if (ret)
@@ -2096,8 +2133,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2096 dspcntr |= DISPPLANE_RGBX101010; 2133 dspcntr |= DISPPLANE_RGBX101010;
2097 break; 2134 break;
2098 default: 2135 default:
2099 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); 2136 BUG();
2100 return -EINVAL;
2101 } 2137 }
2102 2138
2103 if (INTEL_INFO(dev)->gen >= 4) { 2139 if (INTEL_INFO(dev)->gen >= 4) {
@@ -2190,8 +2226,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
2190 dspcntr |= DISPPLANE_RGBX101010; 2226 dspcntr |= DISPPLANE_RGBX101010;
2191 break; 2227 break;
2192 default: 2228 default:
2193 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); 2229 BUG();
2194 return -EINVAL;
2195 } 2230 }
2196 2231
2197 if (obj->tiling_mode != I915_TILING_NONE) 2232 if (obj->tiling_mode != I915_TILING_NONE)
@@ -2960,32 +2995,6 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2960 mutex_unlock(&dev->struct_mutex); 2995 mutex_unlock(&dev->struct_mutex);
2961} 2996}
2962 2997
2963static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2964{
2965 struct drm_device *dev = crtc->dev;
2966 struct intel_encoder *intel_encoder;
2967
2968 /*
2969 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2970 * must be driven by its own crtc; no sharing is possible.
2971 */
2972 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2973 switch (intel_encoder->type) {
2974 case INTEL_OUTPUT_EDP:
2975 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2976 return false;
2977 continue;
2978 }
2979 }
2980
2981 return true;
2982}
2983
2984static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2985{
2986 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2987}
2988
2989/* Program iCLKIP clock to the desired frequency */ 2998/* Program iCLKIP clock to the desired frequency */
2990static void lpt_program_iclkip(struct drm_crtc *crtc) 2999static void lpt_program_iclkip(struct drm_crtc *crtc)
2991{ 3000{
@@ -3321,7 +3330,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3321 int pipe = intel_crtc->pipe; 3330 int pipe = intel_crtc->pipe;
3322 int plane = intel_crtc->plane; 3331 int plane = intel_crtc->plane;
3323 u32 temp; 3332 u32 temp;
3324 bool is_pch_port;
3325 3333
3326 WARN_ON(!crtc->enabled); 3334 WARN_ON(!crtc->enabled);
3327 3335
@@ -3337,9 +3345,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3337 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); 3345 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3338 } 3346 }
3339 3347
3340 is_pch_port = ironlake_crtc_driving_pch(crtc);
3341 3348
3342 if (is_pch_port) { 3349 if (intel_crtc->config.has_pch_encoder) {
3343 /* Note: FDI PLL enabling _must_ be done before we enable the 3350 /* Note: FDI PLL enabling _must_ be done before we enable the
3344 * cpu pipes, hence this is separate from all the other fdi/pch 3351 * cpu pipes, hence this is separate from all the other fdi/pch
3345 * enabling. */ 3352 * enabling. */
@@ -3376,10 +3383,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3376 */ 3383 */
3377 intel_crtc_load_lut(crtc); 3384 intel_crtc_load_lut(crtc);
3378 3385
3379 intel_enable_pipe(dev_priv, pipe, is_pch_port); 3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
3380 intel_enable_plane(dev_priv, plane, pipe); 3388 intel_enable_plane(dev_priv, plane, pipe);
3381 3389
3382 if (is_pch_port) 3390 if (intel_crtc->config.has_pch_encoder)
3383 ironlake_pch_enable(crtc); 3391 ironlake_pch_enable(crtc);
3384 3392
3385 mutex_lock(&dev->struct_mutex); 3393 mutex_lock(&dev->struct_mutex);
@@ -3413,7 +3421,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3413 struct intel_encoder *encoder; 3421 struct intel_encoder *encoder;
3414 int pipe = intel_crtc->pipe; 3422 int pipe = intel_crtc->pipe;
3415 int plane = intel_crtc->plane; 3423 int plane = intel_crtc->plane;
3416 bool is_pch_port;
3417 3424
3418 WARN_ON(!crtc->enabled); 3425 WARN_ON(!crtc->enabled);
3419 3426
@@ -3423,9 +3430,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3423 intel_crtc->active = true; 3430 intel_crtc->active = true;
3424 intel_update_watermarks(dev); 3431 intel_update_watermarks(dev);
3425 3432
3426 is_pch_port = haswell_crtc_driving_pch(crtc); 3433 if (intel_crtc->config.has_pch_encoder)
3427
3428 if (is_pch_port)
3429 dev_priv->display.fdi_link_train(crtc); 3434 dev_priv->display.fdi_link_train(crtc);
3430 3435
3431 for_each_encoder_on_crtc(dev, crtc, encoder) 3436 for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3454,12 +3459,13 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3454 intel_crtc_load_lut(crtc); 3459 intel_crtc_load_lut(crtc);
3455 3460
3456 intel_ddi_set_pipe_settings(crtc); 3461 intel_ddi_set_pipe_settings(crtc);
3457 intel_ddi_enable_pipe_func(crtc); 3462 intel_ddi_enable_transcoder_func(crtc);
3458 3463
3459 intel_enable_pipe(dev_priv, pipe, is_pch_port); 3464 intel_enable_pipe(dev_priv, pipe,
3465 intel_crtc->config.has_pch_encoder);
3460 intel_enable_plane(dev_priv, plane, pipe); 3466 intel_enable_plane(dev_priv, plane, pipe);
3461 3467
3462 if (is_pch_port) 3468 if (intel_crtc->config.has_pch_encoder)
3463 lpt_pch_enable(crtc); 3469 lpt_pch_enable(crtc);
3464 3470
3465 mutex_lock(&dev->struct_mutex); 3471 mutex_lock(&dev->struct_mutex);
@@ -3571,13 +3577,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3571 int pipe = intel_crtc->pipe; 3577 int pipe = intel_crtc->pipe;
3572 int plane = intel_crtc->plane; 3578 int plane = intel_crtc->plane;
3573 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 3579 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3574 bool is_pch_port;
3575 3580
3576 if (!intel_crtc->active) 3581 if (!intel_crtc->active)
3577 return; 3582 return;
3578 3583
3579 is_pch_port = haswell_crtc_driving_pch(crtc);
3580
3581 for_each_encoder_on_crtc(dev, crtc, encoder) 3584 for_each_encoder_on_crtc(dev, crtc, encoder)
3582 encoder->disable(encoder); 3585 encoder->disable(encoder);
3583 3586
@@ -3604,7 +3607,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3604 if (encoder->post_disable) 3607 if (encoder->post_disable)
3605 encoder->post_disable(encoder); 3608 encoder->post_disable(encoder);
3606 3609
3607 if (is_pch_port) { 3610 if (intel_crtc->config.has_pch_encoder) {
3608 lpt_disable_pch_transcoder(dev_priv); 3611 lpt_disable_pch_transcoder(dev_priv);
3609 intel_ddi_fdi_disable(crtc); 3612 intel_ddi_fdi_disable(crtc);
3610 } 3613 }
@@ -3954,22 +3957,23 @@ bool intel_connector_get_hw_state(struct intel_connector *connector)
3954 return encoder->get_hw_state(encoder, &pipe); 3957 return encoder->get_hw_state(encoder, &pipe);
3955} 3958}
3956 3959
3957static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 3960static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3958 const struct drm_display_mode *mode, 3961 struct intel_crtc_config *pipe_config)
3959 struct drm_display_mode *adjusted_mode)
3960{ 3962{
3961 struct drm_device *dev = crtc->dev; 3963 struct drm_device *dev = crtc->dev;
3964 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3962 3965
3963 if (HAS_PCH_SPLIT(dev)) { 3966 if (HAS_PCH_SPLIT(dev)) {
3964 /* FDI link clock is fixed at 2.7G */ 3967 /* FDI link clock is fixed at 2.7G */
3965 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 3968 if (pipe_config->requested_mode.clock * 3
3969 > IRONLAKE_FDI_FREQ * 4)
3966 return false; 3970 return false;
3967 } 3971 }
3968 3972
3969 /* All interlaced capable intel hw wants timings in frames. Note though 3973 /* All interlaced capable intel hw wants timings in frames. Note though
3970 * that intel_lvds_mode_fixup does some funny tricks with the crtc 3974 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3971 * timings, so we need to be careful not to clobber these.*/ 3975 * timings, so we need to be careful not to clobber these.*/
3972 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) 3976 if (!pipe_config->timings_set)
3973 drm_mode_set_crtcinfo(adjusted_mode, 0); 3977 drm_mode_set_crtcinfo(adjusted_mode, 0);
3974 3978
3975 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes 3979 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
@@ -3979,6 +3983,14 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3979 adjusted_mode->hsync_start == adjusted_mode->hdisplay) 3983 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3980 return false; 3984 return false;
3981 3985
3986 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3987 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3988 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3989 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3990 * for lvds. */
3991 pipe_config->pipe_bpp = 8*3;
3992 }
3993
3982 return true; 3994 return true;
3983} 3995}
3984 3996
@@ -4082,142 +4094,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4082 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 4094 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4083} 4095}
4084 4096
4085/**
4086 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4087 * @crtc: CRTC structure
4088 * @mode: requested mode
4089 *
4090 * A pipe may be connected to one or more outputs. Based on the depth of the
4091 * attached framebuffer, choose a good color depth to use on the pipe.
4092 *
4093 * If possible, match the pipe depth to the fb depth. In some cases, this
4094 * isn't ideal, because the connected output supports a lesser or restricted
4095 * set of depths. Resolve that here:
4096 * LVDS typically supports only 6bpc, so clamp down in that case
4097 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4098 * Displays may support a restricted set as well, check EDID and clamp as
4099 * appropriate.
4100 * DP may want to dither down to 6bpc to fit larger modes
4101 *
4102 * RETURNS:
4103 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4104 * true if they don't match).
4105 */
4106static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4107 struct drm_framebuffer *fb,
4108 unsigned int *pipe_bpp,
4109 struct drm_display_mode *mode)
4110{
4111 struct drm_device *dev = crtc->dev;
4112 struct drm_i915_private *dev_priv = dev->dev_private;
4113 struct drm_connector *connector;
4114 struct intel_encoder *intel_encoder;
4115 unsigned int display_bpc = UINT_MAX, bpc;
4116
4117 /* Walk the encoders & connectors on this crtc, get min bpc */
4118 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4119
4120 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4121 unsigned int lvds_bpc;
4122
4123 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4124 LVDS_A3_POWER_UP)
4125 lvds_bpc = 8;
4126 else
4127 lvds_bpc = 6;
4128
4129 if (lvds_bpc < display_bpc) {
4130 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4131 display_bpc = lvds_bpc;
4132 }
4133 continue;
4134 }
4135
4136 /* Not one of the known troublemakers, check the EDID */
4137 list_for_each_entry(connector, &dev->mode_config.connector_list,
4138 head) {
4139 if (connector->encoder != &intel_encoder->base)
4140 continue;
4141
4142 /* Don't use an invalid EDID bpc value */
4143 if (connector->display_info.bpc &&
4144 connector->display_info.bpc < display_bpc) {
4145 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4146 display_bpc = connector->display_info.bpc;
4147 }
4148 }
4149
4150 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4151 /* Use VBT settings if we have an eDP panel */
4152 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4153
4154 if (edp_bpc && edp_bpc < display_bpc) {
4155 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4156 display_bpc = edp_bpc;
4157 }
4158 continue;
4159 }
4160
4161 /*
4162 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4163 * through, clamp it down. (Note: >12bpc will be caught below.)
4164 */
4165 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4166 if (display_bpc > 8 && display_bpc < 12) {
4167 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4168 display_bpc = 12;
4169 } else {
4170 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4171 display_bpc = 8;
4172 }
4173 }
4174 }
4175
4176 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4177 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4178 display_bpc = 6;
4179 }
4180
4181 /*
4182 * We could just drive the pipe at the highest bpc all the time and
4183 * enable dithering as needed, but that costs bandwidth. So choose
4184 * the minimum value that expresses the full color range of the fb but
4185 * also stays within the max display bpc discovered above.
4186 */
4187
4188 switch (fb->depth) {
4189 case 8:
4190 bpc = 8; /* since we go through a colormap */
4191 break;
4192 case 15:
4193 case 16:
4194 bpc = 6; /* min is 18bpp */
4195 break;
4196 case 24:
4197 bpc = 8;
4198 break;
4199 case 30:
4200 bpc = 10;
4201 break;
4202 case 48:
4203 bpc = 12;
4204 break;
4205 default:
4206 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4207 bpc = min((unsigned int)8, display_bpc);
4208 break;
4209 }
4210
4211 display_bpc = min(display_bpc, bpc);
4212
4213 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4214 bpc, display_bpc);
4215
4216 *pipe_bpp = display_bpc * 3;
4217
4218 return display_bpc != bpc;
4219}
4220
4221static int vlv_get_refclk(struct drm_crtc *crtc) 4097static int vlv_get_refclk(struct drm_crtc *crtc)
4222{ 4098{
4223 struct drm_device *dev = crtc->dev; 4099 struct drm_device *dev = crtc->dev;
@@ -4262,37 +4138,38 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4262 return refclk; 4138 return refclk;
4263} 4139}
4264 4140
4265static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, 4141static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4266 intel_clock_t *clock)
4267{ 4142{
4143 unsigned dotclock = crtc->config.adjusted_mode.clock;
4144 struct dpll *clock = &crtc->config.dpll;
4145
4268 /* SDVO TV has fixed PLL values depend on its clock range, 4146 /* SDVO TV has fixed PLL values depend on its clock range,
4269 this mirrors vbios setting. */ 4147 this mirrors vbios setting. */
4270 if (adjusted_mode->clock >= 100000 4148 if (dotclock >= 100000 && dotclock < 140500) {
4271 && adjusted_mode->clock < 140500) {
4272 clock->p1 = 2; 4149 clock->p1 = 2;
4273 clock->p2 = 10; 4150 clock->p2 = 10;
4274 clock->n = 3; 4151 clock->n = 3;
4275 clock->m1 = 16; 4152 clock->m1 = 16;
4276 clock->m2 = 8; 4153 clock->m2 = 8;
4277 } else if (adjusted_mode->clock >= 140500 4154 } else if (dotclock >= 140500 && dotclock <= 200000) {
4278 && adjusted_mode->clock <= 200000) {
4279 clock->p1 = 1; 4155 clock->p1 = 1;
4280 clock->p2 = 10; 4156 clock->p2 = 10;
4281 clock->n = 6; 4157 clock->n = 6;
4282 clock->m1 = 12; 4158 clock->m1 = 12;
4283 clock->m2 = 8; 4159 clock->m2 = 8;
4284 } 4160 }
4161
4162 crtc->config.clock_set = true;
4285} 4163}
4286 4164
4287static void i9xx_update_pll_dividers(struct drm_crtc *crtc, 4165static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4288 intel_clock_t *clock,
4289 intel_clock_t *reduced_clock) 4166 intel_clock_t *reduced_clock)
4290{ 4167{
4291 struct drm_device *dev = crtc->dev; 4168 struct drm_device *dev = crtc->base.dev;
4292 struct drm_i915_private *dev_priv = dev->dev_private; 4169 struct drm_i915_private *dev_priv = dev->dev_private;
4293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4170 int pipe = crtc->pipe;
4294 int pipe = intel_crtc->pipe;
4295 u32 fp, fp2 = 0; 4171 u32 fp, fp2 = 0;
4172 struct dpll *clock = &crtc->config.dpll;
4296 4173
4297 if (IS_PINEVIEW(dev)) { 4174 if (IS_PINEVIEW(dev)) {
4298 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 4175 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
@@ -4308,26 +4185,29 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4308 4185
4309 I915_WRITE(FP0(pipe), fp); 4186 I915_WRITE(FP0(pipe), fp);
4310 4187
4311 intel_crtc->lowfreq_avail = false; 4188 crtc->lowfreq_avail = false;
4312 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4189 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4313 reduced_clock && i915_powersave) { 4190 reduced_clock && i915_powersave) {
4314 I915_WRITE(FP1(pipe), fp2); 4191 I915_WRITE(FP1(pipe), fp2);
4315 intel_crtc->lowfreq_avail = true; 4192 crtc->lowfreq_avail = true;
4316 } else { 4193 } else {
4317 I915_WRITE(FP1(pipe), fp); 4194 I915_WRITE(FP1(pipe), fp);
4318 } 4195 }
4319} 4196}
4320 4197
4321static void vlv_update_pll(struct drm_crtc *crtc, 4198static void intel_dp_set_m_n(struct intel_crtc *crtc)
4322 struct drm_display_mode *mode,
4323 struct drm_display_mode *adjusted_mode,
4324 intel_clock_t *clock, intel_clock_t *reduced_clock,
4325 int num_connectors)
4326{ 4199{
4327 struct drm_device *dev = crtc->dev; 4200 if (crtc->config.has_pch_encoder)
4201 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4202 else
4203 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4204}
4205
4206static void vlv_update_pll(struct intel_crtc *crtc)
4207{
4208 struct drm_device *dev = crtc->base.dev;
4328 struct drm_i915_private *dev_priv = dev->dev_private; 4209 struct drm_i915_private *dev_priv = dev->dev_private;
4329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4210 int pipe = crtc->pipe;
4330 int pipe = intel_crtc->pipe;
4331 u32 dpll, mdiv, pdiv; 4211 u32 dpll, mdiv, pdiv;
4332 u32 bestn, bestm1, bestm2, bestp1, bestp2; 4212 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4333 bool is_sdvo; 4213 bool is_sdvo;
@@ -4335,8 +4215,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
4335 4215
4336 mutex_lock(&dev_priv->dpio_lock); 4216 mutex_lock(&dev_priv->dpio_lock);
4337 4217
4338 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || 4218 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4339 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); 4219 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4340 4220
4341 dpll = DPLL_VGA_MODE_DIS; 4221 dpll = DPLL_VGA_MODE_DIS;
4342 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; 4222 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
@@ -4346,11 +4226,11 @@ static void vlv_update_pll(struct drm_crtc *crtc,
4346 I915_WRITE(DPLL(pipe), dpll); 4226 I915_WRITE(DPLL(pipe), dpll);
4347 POSTING_READ(DPLL(pipe)); 4227 POSTING_READ(DPLL(pipe));
4348 4228
4349 bestn = clock->n; 4229 bestn = crtc->config.dpll.n;
4350 bestm1 = clock->m1; 4230 bestm1 = crtc->config.dpll.m1;
4351 bestm2 = clock->m2; 4231 bestm2 = crtc->config.dpll.m2;
4352 bestp1 = clock->p1; 4232 bestp1 = crtc->config.dpll.p1;
4353 bestp2 = clock->p2; 4233 bestp2 = crtc->config.dpll.p2;
4354 4234
4355 /* 4235 /*
4356 * In Valleyview PLL and program lane counter registers are exposed 4236 * In Valleyview PLL and program lane counter registers are exposed
@@ -4382,8 +4262,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
4382 4262
4383 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); 4263 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4384 4264
4385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 4265 if (crtc->config.has_dp_encoder)
4386 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4266 intel_dp_set_m_n(crtc);
4387 4267
4388 I915_WRITE(DPLL(pipe), dpll); 4268 I915_WRITE(DPLL(pipe), dpll);
4389 4269
@@ -4393,26 +4273,25 @@ static void vlv_update_pll(struct drm_crtc *crtc,
4393 4273
4394 temp = 0; 4274 temp = 0;
4395 if (is_sdvo) { 4275 if (is_sdvo) {
4396 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 4276 temp = 0;
4397 if (temp > 1) 4277 if (crtc->config.pixel_multiplier > 1) {
4398 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 4278 temp = (crtc->config.pixel_multiplier - 1)
4399 else 4279 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4400 temp = 0; 4280 }
4401 } 4281 }
4402 I915_WRITE(DPLL_MD(pipe), temp); 4282 I915_WRITE(DPLL_MD(pipe), temp);
4403 POSTING_READ(DPLL_MD(pipe)); 4283 POSTING_READ(DPLL_MD(pipe));
4404 4284
4405 /* Now program lane control registers */ 4285 /* Now program lane control registers */
4406 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) 4286 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4407 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 4287 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
4408 {
4409 temp = 0x1000C4; 4288 temp = 0x1000C4;
4410 if(pipe == 1) 4289 if(pipe == 1)
4411 temp |= (1 << 21); 4290 temp |= (1 << 21);
4412 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); 4291 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4413 } 4292 }
4414 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP)) 4293
4415 { 4294 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
4416 temp = 0x1000C4; 4295 temp = 0x1000C4;
4417 if(pipe == 1) 4296 if(pipe == 1)
4418 temp |= (1 << 21); 4297 temp |= (1 << 21);
@@ -4422,40 +4301,39 @@ static void vlv_update_pll(struct drm_crtc *crtc,
4422 mutex_unlock(&dev_priv->dpio_lock); 4301 mutex_unlock(&dev_priv->dpio_lock);
4423} 4302}
4424 4303
4425static void i9xx_update_pll(struct drm_crtc *crtc, 4304static void i9xx_update_pll(struct intel_crtc *crtc,
4426 struct drm_display_mode *mode, 4305 intel_clock_t *reduced_clock,
4427 struct drm_display_mode *adjusted_mode,
4428 intel_clock_t *clock, intel_clock_t *reduced_clock,
4429 int num_connectors) 4306 int num_connectors)
4430{ 4307{
4431 struct drm_device *dev = crtc->dev; 4308 struct drm_device *dev = crtc->base.dev;
4432 struct drm_i915_private *dev_priv = dev->dev_private; 4309 struct drm_i915_private *dev_priv = dev->dev_private;
4433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4434 struct intel_encoder *encoder; 4310 struct intel_encoder *encoder;
4435 int pipe = intel_crtc->pipe; 4311 int pipe = crtc->pipe;
4436 u32 dpll; 4312 u32 dpll;
4437 bool is_sdvo; 4313 bool is_sdvo;
4314 struct dpll *clock = &crtc->config.dpll;
4438 4315
4439 i9xx_update_pll_dividers(crtc, clock, reduced_clock); 4316 i9xx_update_pll_dividers(crtc, reduced_clock);
4440 4317
4441 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || 4318 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4442 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); 4319 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4443 4320
4444 dpll = DPLL_VGA_MODE_DIS; 4321 dpll = DPLL_VGA_MODE_DIS;
4445 4322
4446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 4323 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4447 dpll |= DPLLB_MODE_LVDS; 4324 dpll |= DPLLB_MODE_LVDS;
4448 else 4325 else
4449 dpll |= DPLLB_MODE_DAC_SERIAL; 4326 dpll |= DPLLB_MODE_DAC_SERIAL;
4327
4450 if (is_sdvo) { 4328 if (is_sdvo) {
4451 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4329 if ((crtc->config.pixel_multiplier > 1) &&
4452 if (pixel_multiplier > 1) { 4330 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4453 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 4331 dpll |= (crtc->config.pixel_multiplier - 1)
4454 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 4332 << SDVO_MULTIPLIER_SHIFT_HIRES;
4455 } 4333 }
4456 dpll |= DPLL_DVO_HIGH_SPEED; 4334 dpll |= DPLL_DVO_HIGH_SPEED;
4457 } 4335 }
4458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 4336 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4459 dpll |= DPLL_DVO_HIGH_SPEED; 4337 dpll |= DPLL_DVO_HIGH_SPEED;
4460 4338
4461 /* compute bitmask from p1 value */ 4339 /* compute bitmask from p1 value */
@@ -4483,13 +4361,13 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
4483 if (INTEL_INFO(dev)->gen >= 4) 4361 if (INTEL_INFO(dev)->gen >= 4)
4484 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 4362 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4485 4363
4486 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) 4364 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4487 dpll |= PLL_REF_INPUT_TVCLKINBC; 4365 dpll |= PLL_REF_INPUT_TVCLKINBC;
4488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) 4366 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4489 /* XXX: just matching BIOS for now */ 4367 /* XXX: just matching BIOS for now */
4490 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4368 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4491 dpll |= 3; 4369 dpll |= 3;
4492 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4370 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4493 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4371 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4494 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4372 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4495 else 4373 else
@@ -4500,12 +4378,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
4500 POSTING_READ(DPLL(pipe)); 4378 POSTING_READ(DPLL(pipe));
4501 udelay(150); 4379 udelay(150);
4502 4380
4503 for_each_encoder_on_crtc(dev, crtc, encoder) 4381 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4504 if (encoder->pre_pll_enable) 4382 if (encoder->pre_pll_enable)
4505 encoder->pre_pll_enable(encoder); 4383 encoder->pre_pll_enable(encoder);
4506 4384
4507 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 4385 if (crtc->config.has_dp_encoder)
4508 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4386 intel_dp_set_m_n(crtc);
4509 4387
4510 I915_WRITE(DPLL(pipe), dpll); 4388 I915_WRITE(DPLL(pipe), dpll);
4511 4389
@@ -4516,11 +4394,11 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
4516 if (INTEL_INFO(dev)->gen >= 4) { 4394 if (INTEL_INFO(dev)->gen >= 4) {
4517 u32 temp = 0; 4395 u32 temp = 0;
4518 if (is_sdvo) { 4396 if (is_sdvo) {
4519 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 4397 temp = 0;
4520 if (temp > 1) 4398 if (crtc->config.pixel_multiplier > 1) {
4521 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 4399 temp = (crtc->config.pixel_multiplier - 1)
4522 else 4400 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4523 temp = 0; 4401 }
4524 } 4402 }
4525 I915_WRITE(DPLL_MD(pipe), temp); 4403 I915_WRITE(DPLL_MD(pipe), temp);
4526 } else { 4404 } else {
@@ -4533,23 +4411,23 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
4533 } 4411 }
4534} 4412}
4535 4413
4536static void i8xx_update_pll(struct drm_crtc *crtc, 4414static void i8xx_update_pll(struct intel_crtc *crtc,
4537 struct drm_display_mode *adjusted_mode, 4415 struct drm_display_mode *adjusted_mode,
4538 intel_clock_t *clock, intel_clock_t *reduced_clock, 4416 intel_clock_t *reduced_clock,
4539 int num_connectors) 4417 int num_connectors)
4540{ 4418{
4541 struct drm_device *dev = crtc->dev; 4419 struct drm_device *dev = crtc->base.dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private; 4420 struct drm_i915_private *dev_priv = dev->dev_private;
4543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4544 struct intel_encoder *encoder; 4421 struct intel_encoder *encoder;
4545 int pipe = intel_crtc->pipe; 4422 int pipe = crtc->pipe;
4546 u32 dpll; 4423 u32 dpll;
4424 struct dpll *clock = &crtc->config.dpll;
4547 4425
4548 i9xx_update_pll_dividers(crtc, clock, reduced_clock); 4426 i9xx_update_pll_dividers(crtc, reduced_clock);
4549 4427
4550 dpll = DPLL_VGA_MODE_DIS; 4428 dpll = DPLL_VGA_MODE_DIS;
4551 4429
4552 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 4430 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4431 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4554 } else { 4432 } else {
4555 if (clock->p1 == 2) 4433 if (clock->p1 == 2)
@@ -4560,7 +4438,7 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
4560 dpll |= PLL_P2_DIVIDE_BY_4; 4438 dpll |= PLL_P2_DIVIDE_BY_4;
4561 } 4439 }
4562 4440
4563 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4441 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4564 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4442 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4565 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4443 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4566 else 4444 else
@@ -4571,7 +4449,7 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
4571 POSTING_READ(DPLL(pipe)); 4449 POSTING_READ(DPLL(pipe));
4572 udelay(150); 4450 udelay(150);
4573 4451
4574 for_each_encoder_on_crtc(dev, crtc, encoder) 4452 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4575 if (encoder->pre_pll_enable) 4453 if (encoder->pre_pll_enable)
4576 encoder->pre_pll_enable(encoder); 4454 encoder->pre_pll_enable(encoder);
4577 4455
@@ -4647,22 +4525,92 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4647 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4525 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4648} 4526}
4649 4527
4528static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4529{
4530 struct drm_device *dev = intel_crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 uint32_t pipeconf;
4533
4534 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4535
4536 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4537 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4538 * core speed.
4539 *
4540 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4541 * pipe == 0 check?
4542 */
4543 if (intel_crtc->config.requested_mode.clock >
4544 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4545 pipeconf |= PIPECONF_DOUBLE_WIDE;
4546 else
4547 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4548 }
4549
4550 /* default to 8bpc */
4551 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4552 if (intel_crtc->config.has_dp_encoder) {
4553 if (intel_crtc->config.dither) {
4554 pipeconf |= PIPECONF_6BPC |
4555 PIPECONF_DITHER_EN |
4556 PIPECONF_DITHER_TYPE_SP;
4557 }
4558 }
4559
4560 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4561 INTEL_OUTPUT_EDP)) {
4562 if (intel_crtc->config.dither) {
4563 pipeconf |= PIPECONF_6BPC |
4564 PIPECONF_ENABLE |
4565 I965_PIPECONF_ACTIVE;
4566 }
4567 }
4568
4569 if (HAS_PIPE_CXSR(dev)) {
4570 if (intel_crtc->lowfreq_avail) {
4571 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4572 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4573 } else {
4574 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4575 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4576 }
4577 }
4578
4579 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4580 if (!IS_GEN2(dev) &&
4581 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4582 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4583 else
4584 pipeconf |= PIPECONF_PROGRESSIVE;
4585
4586 if (IS_VALLEYVIEW(dev)) {
4587 if (intel_crtc->config.limited_color_range)
4588 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4589 else
4590 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4591 }
4592
4593 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4594 POSTING_READ(PIPECONF(intel_crtc->pipe));
4595}
4596
4650static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 4597static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4651 struct drm_display_mode *mode,
4652 struct drm_display_mode *adjusted_mode,
4653 int x, int y, 4598 int x, int y,
4654 struct drm_framebuffer *fb) 4599 struct drm_framebuffer *fb)
4655{ 4600{
4656 struct drm_device *dev = crtc->dev; 4601 struct drm_device *dev = crtc->dev;
4657 struct drm_i915_private *dev_priv = dev->dev_private; 4602 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604 struct drm_display_mode *adjusted_mode =
4605 &intel_crtc->config.adjusted_mode;
4606 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4659 int pipe = intel_crtc->pipe; 4607 int pipe = intel_crtc->pipe;
4660 int plane = intel_crtc->plane; 4608 int plane = intel_crtc->plane;
4661 int refclk, num_connectors = 0; 4609 int refclk, num_connectors = 0;
4662 intel_clock_t clock, reduced_clock; 4610 intel_clock_t clock, reduced_clock;
4663 u32 dspcntr, pipeconf; 4611 u32 dspcntr;
4664 bool ok, has_reduced_clock = false, is_sdvo = false; 4612 bool ok, has_reduced_clock = false, is_sdvo = false;
4665 bool is_lvds = false, is_tv = false, is_dp = false; 4613 bool is_lvds = false, is_tv = false;
4666 struct intel_encoder *encoder; 4614 struct intel_encoder *encoder;
4667 const intel_limit_t *limit; 4615 const intel_limit_t *limit;
4668 int ret; 4616 int ret;
@@ -4681,9 +4629,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4681 case INTEL_OUTPUT_TVOUT: 4629 case INTEL_OUTPUT_TVOUT:
4682 is_tv = true; 4630 is_tv = true;
4683 break; 4631 break;
4684 case INTEL_OUTPUT_DISPLAYPORT:
4685 is_dp = true;
4686 break;
4687 } 4632 }
4688 4633
4689 num_connectors++; 4634 num_connectors++;
@@ -4720,26 +4665,29 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4720 &clock, 4665 &clock,
4721 &reduced_clock); 4666 &reduced_clock);
4722 } 4667 }
4668 /* Compat-code for transition, will disappear. */
4669 if (!intel_crtc->config.clock_set) {
4670 intel_crtc->config.dpll.n = clock.n;
4671 intel_crtc->config.dpll.m1 = clock.m1;
4672 intel_crtc->config.dpll.m2 = clock.m2;
4673 intel_crtc->config.dpll.p1 = clock.p1;
4674 intel_crtc->config.dpll.p2 = clock.p2;
4675 }
4723 4676
4724 if (is_sdvo && is_tv) 4677 if (is_sdvo && is_tv)
4725 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); 4678 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4726 4679
4727 if (IS_GEN2(dev)) 4680 if (IS_GEN2(dev))
4728 i8xx_update_pll(crtc, adjusted_mode, &clock, 4681 i8xx_update_pll(intel_crtc, adjusted_mode,
4729 has_reduced_clock ? &reduced_clock : NULL, 4682 has_reduced_clock ? &reduced_clock : NULL,
4730 num_connectors); 4683 num_connectors);
4731 else if (IS_VALLEYVIEW(dev)) 4684 else if (IS_VALLEYVIEW(dev))
4732 vlv_update_pll(crtc, mode, adjusted_mode, &clock, 4685 vlv_update_pll(intel_crtc);
4733 has_reduced_clock ? &reduced_clock : NULL,
4734 num_connectors);
4735 else 4686 else
4736 i9xx_update_pll(crtc, mode, adjusted_mode, &clock, 4687 i9xx_update_pll(intel_crtc,
4737 has_reduced_clock ? &reduced_clock : NULL, 4688 has_reduced_clock ? &reduced_clock : NULL,
4738 num_connectors); 4689 num_connectors);
4739 4690
4740 /* setup pipeconf */
4741 pipeconf = I915_READ(PIPECONF(pipe));
4742
4743 /* Set up the display plane register */ 4691 /* Set up the display plane register */
4744 dspcntr = DISPPLANE_GAMMA_ENABLE; 4692 dspcntr = DISPPLANE_GAMMA_ENABLE;
4745 4693
@@ -4750,58 +4698,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4750 dspcntr |= DISPPLANE_SEL_PIPE_B; 4698 dspcntr |= DISPPLANE_SEL_PIPE_B;
4751 } 4699 }
4752 4700
4753 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4754 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4755 * core speed.
4756 *
4757 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4758 * pipe == 0 check?
4759 */
4760 if (mode->clock >
4761 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4762 pipeconf |= PIPECONF_DOUBLE_WIDE;
4763 else
4764 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4765 }
4766
4767 /* default to 8bpc */
4768 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4769 if (is_dp) {
4770 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4771 pipeconf |= PIPECONF_6BPC |
4772 PIPECONF_DITHER_EN |
4773 PIPECONF_DITHER_TYPE_SP;
4774 }
4775 }
4776
4777 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4778 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4779 pipeconf |= PIPECONF_6BPC |
4780 PIPECONF_ENABLE |
4781 I965_PIPECONF_ACTIVE;
4782 }
4783 }
4784
4785 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4701 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4786 drm_mode_debug_printmodeline(mode); 4702 drm_mode_debug_printmodeline(mode);
4787 4703
4788 if (HAS_PIPE_CXSR(dev)) {
4789 if (intel_crtc->lowfreq_avail) {
4790 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4791 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4792 } else {
4793 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4794 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4795 }
4796 }
4797
4798 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4799 if (!IS_GEN2(dev) &&
4800 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4801 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4802 else
4803 pipeconf |= PIPECONF_PROGRESSIVE;
4804
4805 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 4704 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4806 4705
4807 /* pipesrc and dspsize control the size that is scaled from, 4706 /* pipesrc and dspsize control the size that is scaled from,
@@ -4812,8 +4711,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4812 (mode->hdisplay - 1)); 4711 (mode->hdisplay - 1));
4813 I915_WRITE(DSPPOS(plane), 0); 4712 I915_WRITE(DSPPOS(plane), 0);
4814 4713
4815 I915_WRITE(PIPECONF(pipe), pipeconf); 4714 i9xx_set_pipeconf(intel_crtc);
4816 POSTING_READ(PIPECONF(pipe)); 4715
4817 intel_enable_pipe(dev_priv, pipe, false); 4716 intel_enable_pipe(dev_priv, pipe, false);
4818 4717
4819 intel_wait_for_vblank(dev, pipe); 4718 intel_wait_for_vblank(dev, pipe);
@@ -4828,12 +4727,26 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4828 return ret; 4727 return ret;
4829} 4728}
4830 4729
4730static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4731 struct intel_crtc_config *pipe_config)
4732{
4733 struct drm_device *dev = crtc->base.dev;
4734 struct drm_i915_private *dev_priv = dev->dev_private;
4735 uint32_t tmp;
4736
4737 tmp = I915_READ(PIPECONF(crtc->pipe));
4738 if (!(tmp & PIPECONF_ENABLE))
4739 return false;
4740
4741 return true;
4742}
4743
4831static void ironlake_init_pch_refclk(struct drm_device *dev) 4744static void ironlake_init_pch_refclk(struct drm_device *dev)
4832{ 4745{
4833 struct drm_i915_private *dev_priv = dev->dev_private; 4746 struct drm_i915_private *dev_priv = dev->dev_private;
4834 struct drm_mode_config *mode_config = &dev->mode_config; 4747 struct drm_mode_config *mode_config = &dev->mode_config;
4835 struct intel_encoder *encoder; 4748 struct intel_encoder *encoder;
4836 u32 temp; 4749 u32 val, final;
4837 bool has_lvds = false; 4750 bool has_lvds = false;
4838 bool has_cpu_edp = false; 4751 bool has_cpu_edp = false;
4839 bool has_pch_edp = false; 4752 bool has_pch_edp = false;
@@ -4876,70 +4789,109 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
4876 * PCH B stepping, previous chipset stepping should be 4789 * PCH B stepping, previous chipset stepping should be
4877 * ignoring this setting. 4790 * ignoring this setting.
4878 */ 4791 */
4879 temp = I915_READ(PCH_DREF_CONTROL); 4792 val = I915_READ(PCH_DREF_CONTROL);
4793
4794 /* As we must carefully and slowly disable/enable each source in turn,
4795 * compute the final state we want first and check if we need to
4796 * make any changes at all.
4797 */
4798 final = val;
4799 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4800 if (has_ck505)
4801 final |= DREF_NONSPREAD_CK505_ENABLE;
4802 else
4803 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4804
4805 final &= ~DREF_SSC_SOURCE_MASK;
4806 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4807 final &= ~DREF_SSC1_ENABLE;
4808
4809 if (has_panel) {
4810 final |= DREF_SSC_SOURCE_ENABLE;
4811
4812 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4813 final |= DREF_SSC1_ENABLE;
4814
4815 if (has_cpu_edp) {
4816 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4817 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4818 else
4819 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4820 } else
4821 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4822 } else {
4823 final |= DREF_SSC_SOURCE_DISABLE;
4824 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4825 }
4826
4827 if (final == val)
4828 return;
4829
4880 /* Always enable nonspread source */ 4830 /* Always enable nonspread source */
4881 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 4831 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4882 4832
4883 if (has_ck505) 4833 if (has_ck505)
4884 temp |= DREF_NONSPREAD_CK505_ENABLE; 4834 val |= DREF_NONSPREAD_CK505_ENABLE;
4885 else 4835 else
4886 temp |= DREF_NONSPREAD_SOURCE_ENABLE; 4836 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4887 4837
4888 if (has_panel) { 4838 if (has_panel) {
4889 temp &= ~DREF_SSC_SOURCE_MASK; 4839 val &= ~DREF_SSC_SOURCE_MASK;
4890 temp |= DREF_SSC_SOURCE_ENABLE; 4840 val |= DREF_SSC_SOURCE_ENABLE;
4891 4841
4892 /* SSC must be turned on before enabling the CPU output */ 4842 /* SSC must be turned on before enabling the CPU output */
4893 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 4843 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4894 DRM_DEBUG_KMS("Using SSC on panel\n"); 4844 DRM_DEBUG_KMS("Using SSC on panel\n");
4895 temp |= DREF_SSC1_ENABLE; 4845 val |= DREF_SSC1_ENABLE;
4896 } else 4846 } else
4897 temp &= ~DREF_SSC1_ENABLE; 4847 val &= ~DREF_SSC1_ENABLE;
4898 4848
4899 /* Get SSC going before enabling the outputs */ 4849 /* Get SSC going before enabling the outputs */
4900 I915_WRITE(PCH_DREF_CONTROL, temp); 4850 I915_WRITE(PCH_DREF_CONTROL, val);
4901 POSTING_READ(PCH_DREF_CONTROL); 4851 POSTING_READ(PCH_DREF_CONTROL);
4902 udelay(200); 4852 udelay(200);
4903 4853
4904 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4854 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4905 4855
4906 /* Enable CPU source on CPU attached eDP */ 4856 /* Enable CPU source on CPU attached eDP */
4907 if (has_cpu_edp) { 4857 if (has_cpu_edp) {
4908 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 4858 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4909 DRM_DEBUG_KMS("Using SSC on eDP\n"); 4859 DRM_DEBUG_KMS("Using SSC on eDP\n");
4910 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 4860 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4911 } 4861 }
4912 else 4862 else
4913 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 4863 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4914 } else 4864 } else
4915 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4865 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4916 4866
4917 I915_WRITE(PCH_DREF_CONTROL, temp); 4867 I915_WRITE(PCH_DREF_CONTROL, val);
4918 POSTING_READ(PCH_DREF_CONTROL); 4868 POSTING_READ(PCH_DREF_CONTROL);
4919 udelay(200); 4869 udelay(200);
4920 } else { 4870 } else {
4921 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 4871 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4922 4872
4923 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4873 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4924 4874
4925 /* Turn off CPU output */ 4875 /* Turn off CPU output */
4926 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4876 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4927 4877
4928 I915_WRITE(PCH_DREF_CONTROL, temp); 4878 I915_WRITE(PCH_DREF_CONTROL, val);
4929 POSTING_READ(PCH_DREF_CONTROL); 4879 POSTING_READ(PCH_DREF_CONTROL);
4930 udelay(200); 4880 udelay(200);
4931 4881
4932 /* Turn off the SSC source */ 4882 /* Turn off the SSC source */
4933 temp &= ~DREF_SSC_SOURCE_MASK; 4883 val &= ~DREF_SSC_SOURCE_MASK;
4934 temp |= DREF_SSC_SOURCE_DISABLE; 4884 val |= DREF_SSC_SOURCE_DISABLE;
4935 4885
4936 /* Turn off SSC1 */ 4886 /* Turn off SSC1 */
4937 temp &= ~ DREF_SSC1_ENABLE; 4887 val &= ~DREF_SSC1_ENABLE;
4938 4888
4939 I915_WRITE(PCH_DREF_CONTROL, temp); 4889 I915_WRITE(PCH_DREF_CONTROL, val);
4940 POSTING_READ(PCH_DREF_CONTROL); 4890 POSTING_READ(PCH_DREF_CONTROL);
4941 udelay(200); 4891 udelay(200);
4942 } 4892 }
4893
4894 BUG_ON(val != final);
4943} 4895}
4944 4896
4945/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ 4897/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
@@ -5164,7 +5116,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5164 val = I915_READ(PIPECONF(pipe)); 5116 val = I915_READ(PIPECONF(pipe));
5165 5117
5166 val &= ~PIPECONF_BPC_MASK; 5118 val &= ~PIPECONF_BPC_MASK;
5167 switch (intel_crtc->bpp) { 5119 switch (intel_crtc->config.pipe_bpp) {
5168 case 18: 5120 case 18:
5169 val |= PIPECONF_6BPC; 5121 val |= PIPECONF_6BPC;
5170 break; 5122 break;
@@ -5192,7 +5144,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5192 else 5144 else
5193 val |= PIPECONF_PROGRESSIVE; 5145 val |= PIPECONF_PROGRESSIVE;
5194 5146
5195 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5147 if (intel_crtc->config.limited_color_range)
5196 val |= PIPECONF_COLOR_RANGE_SELECT; 5148 val |= PIPECONF_COLOR_RANGE_SELECT;
5197 else 5149 else
5198 val &= ~PIPECONF_COLOR_RANGE_SELECT; 5150 val &= ~PIPECONF_COLOR_RANGE_SELECT;
@@ -5208,8 +5160,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5208 * is supported, but eventually this should handle various 5160 * is supported, but eventually this should handle various
5209 * RGB<->YCbCr scenarios as well. 5161 * RGB<->YCbCr scenarios as well.
5210 */ 5162 */
5211static void intel_set_pipe_csc(struct drm_crtc *crtc, 5163static void intel_set_pipe_csc(struct drm_crtc *crtc)
5212 const struct drm_display_mode *adjusted_mode)
5213{ 5164{
5214 struct drm_device *dev = crtc->dev; 5165 struct drm_device *dev = crtc->dev;
5215 struct drm_i915_private *dev_priv = dev->dev_private; 5166 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5224,7 +5175,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc,
5224 * consideration. 5175 * consideration.
5225 */ 5176 */
5226 5177
5227 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5178 if (intel_crtc->config.limited_color_range)
5228 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ 5179 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5229 5180
5230 /* 5181 /*
@@ -5248,7 +5199,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc,
5248 if (INTEL_INFO(dev)->gen > 6) { 5199 if (INTEL_INFO(dev)->gen > 6) {
5249 uint16_t postoff = 0; 5200 uint16_t postoff = 0;
5250 5201
5251 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5202 if (intel_crtc->config.limited_color_range)
5252 postoff = (16 * (1 << 13) / 255) & 0x1fff; 5203 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5253 5204
5254 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 5205 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
@@ -5259,7 +5210,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc,
5259 } else { 5210 } else {
5260 uint32_t mode = CSC_MODE_YUV_TO_RGB; 5211 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5261 5212
5262 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5213 if (intel_crtc->config.limited_color_range)
5263 mode |= CSC_BLACK_SCREEN_OFFSET; 5214 mode |= CSC_BLACK_SCREEN_OFFSET;
5264 5215
5265 I915_WRITE(PIPE_CSC_MODE(pipe), mode); 5216 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
@@ -5349,7 +5300,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5349 } 5300 }
5350 5301
5351 if (is_sdvo && is_tv) 5302 if (is_sdvo && is_tv)
5352 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); 5303 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5353 5304
5354 return true; 5305 return true;
5355} 5306}
@@ -5447,77 +5398,77 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5447 return bps / (link_bw * 8) + 1; 5398 return bps / (link_bw * 8) + 1;
5448} 5399}
5449 5400
5450static void ironlake_set_m_n(struct drm_crtc *crtc, 5401void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5451 struct drm_display_mode *mode, 5402 struct intel_link_m_n *m_n)
5452 struct drm_display_mode *adjusted_mode)
5453{ 5403{
5454 struct drm_device *dev = crtc->dev; 5404 struct drm_device *dev = crtc->base.dev;
5455 struct drm_i915_private *dev_priv = dev->dev_private; 5405 struct drm_i915_private *dev_priv = dev->dev_private;
5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5406 int pipe = crtc->pipe;
5457 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5458 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5459 struct intel_link_m_n m_n = {0};
5460 int target_clock, pixel_multiplier, lane, link_bw;
5461 bool is_dp = false, is_cpu_edp = false;
5462 5407
5463 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5408 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5464 switch (intel_encoder->type) { 5409 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5465 case INTEL_OUTPUT_DISPLAYPORT: 5410 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5466 is_dp = true; 5411 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5467 break; 5412}
5468 case INTEL_OUTPUT_EDP:
5469 is_dp = true;
5470 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5471 is_cpu_edp = true;
5472 edp_encoder = intel_encoder;
5473 break;
5474 }
5475 }
5476 5413
5477 /* FDI link */ 5414void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5478 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 5415 struct intel_link_m_n *m_n)
5479 lane = 0; 5416{
5480 /* CPU eDP doesn't require FDI link, so just set DP M/N 5417 struct drm_device *dev = crtc->base.dev;
5481 according to current link config */ 5418 struct drm_i915_private *dev_priv = dev->dev_private;
5482 if (is_cpu_edp) { 5419 int pipe = crtc->pipe;
5483 intel_edp_link_config(edp_encoder, &lane, &link_bw); 5420 enum transcoder transcoder = crtc->cpu_transcoder;
5421
5422 if (INTEL_INFO(dev)->gen >= 5) {
5423 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5424 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5425 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5426 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5484 } else { 5427 } else {
5485 /* FDI is a binary signal running at ~2.7GHz, encoding 5428 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5486 * each output octet as 10 bits. The actual frequency 5429 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5487 * is stored as a divider into a 100MHz clock, and the 5430 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5488 * mode pixel clock is stored in units of 1KHz. 5431 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5489 * Hence the bw of each lane in terms of the mode signal
5490 * is:
5491 */
5492 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5493 } 5432 }
5433}
5434
5435static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5436{
5437 struct drm_device *dev = crtc->dev;
5438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439 struct drm_display_mode *adjusted_mode =
5440 &intel_crtc->config.adjusted_mode;
5441 struct intel_link_m_n m_n = {0};
5442 int target_clock, lane, link_bw;
5443
5444 /* FDI is a binary signal running at ~2.7GHz, encoding
5445 * each output octet as 10 bits. The actual frequency
5446 * is stored as a divider into a 100MHz clock, and the
5447 * mode pixel clock is stored in units of 1KHz.
5448 * Hence the bw of each lane in terms of the mode signal
5449 * is:
5450 */
5451 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5494 5452
5495 /* [e]DP over FDI requires target mode clock instead of link clock. */ 5453 if (intel_crtc->config.pixel_target_clock)
5496 if (edp_encoder) 5454 target_clock = intel_crtc->config.pixel_target_clock;
5497 target_clock = intel_edp_target_clock(edp_encoder, mode);
5498 else if (is_dp)
5499 target_clock = mode->clock;
5500 else 5455 else
5501 target_clock = adjusted_mode->clock; 5456 target_clock = adjusted_mode->clock;
5502 5457
5503 if (!lane) 5458 lane = ironlake_get_lanes_required(target_clock, link_bw,
5504 lane = ironlake_get_lanes_required(target_clock, link_bw, 5459 intel_crtc->config.pipe_bpp);
5505 intel_crtc->bpp);
5506 5460
5507 intel_crtc->fdi_lanes = lane; 5461 intel_crtc->fdi_lanes = lane;
5508 5462
5509 if (pixel_multiplier > 1) 5463 if (intel_crtc->config.pixel_multiplier > 1)
5510 link_bw *= pixel_multiplier; 5464 link_bw *= intel_crtc->config.pixel_multiplier;
5511 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n); 5465 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5466 link_bw, &m_n);
5512 5467
5513 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); 5468 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5514 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5515 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5516 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5517} 5469}
5518 5470
5519static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 5471static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5520 struct drm_display_mode *adjusted_mode,
5521 intel_clock_t *clock, u32 fp) 5472 intel_clock_t *clock, u32 fp)
5522{ 5473{
5523 struct drm_crtc *crtc = &intel_crtc->base; 5474 struct drm_crtc *crtc = &intel_crtc->base;
@@ -5525,9 +5476,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5525 struct drm_i915_private *dev_priv = dev->dev_private; 5476 struct drm_i915_private *dev_priv = dev->dev_private;
5526 struct intel_encoder *intel_encoder; 5477 struct intel_encoder *intel_encoder;
5527 uint32_t dpll; 5478 uint32_t dpll;
5528 int factor, pixel_multiplier, num_connectors = 0; 5479 int factor, num_connectors = 0;
5529 bool is_lvds = false, is_sdvo = false, is_tv = false; 5480 bool is_lvds = false, is_sdvo = false, is_tv = false;
5530 bool is_dp = false, is_cpu_edp = false;
5531 5481
5532 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5482 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5533 switch (intel_encoder->type) { 5483 switch (intel_encoder->type) {
@@ -5543,14 +5493,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5543 case INTEL_OUTPUT_TVOUT: 5493 case INTEL_OUTPUT_TVOUT:
5544 is_tv = true; 5494 is_tv = true;
5545 break; 5495 break;
5546 case INTEL_OUTPUT_DISPLAYPORT:
5547 is_dp = true;
5548 break;
5549 case INTEL_OUTPUT_EDP:
5550 is_dp = true;
5551 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5552 is_cpu_edp = true;
5553 break;
5554 } 5496 }
5555 5497
5556 num_connectors++; 5498 num_connectors++;
@@ -5576,13 +5518,14 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5576 else 5518 else
5577 dpll |= DPLLB_MODE_DAC_SERIAL; 5519 dpll |= DPLLB_MODE_DAC_SERIAL;
5578 if (is_sdvo) { 5520 if (is_sdvo) {
5579 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 5521 if (intel_crtc->config.pixel_multiplier > 1) {
5580 if (pixel_multiplier > 1) { 5522 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5581 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 5523 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5582 } 5524 }
5583 dpll |= DPLL_DVO_HIGH_SPEED; 5525 dpll |= DPLL_DVO_HIGH_SPEED;
5584 } 5526 }
5585 if (is_dp && !is_cpu_edp) 5527 if (intel_crtc->config.has_dp_encoder &&
5528 intel_crtc->config.has_pch_encoder)
5586 dpll |= DPLL_DVO_HIGH_SPEED; 5529 dpll |= DPLL_DVO_HIGH_SPEED;
5587 5530
5588 /* compute bitmask from p1 value */ 5531 /* compute bitmask from p1 value */
@@ -5620,21 +5563,22 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5620} 5563}
5621 5564
5622static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 5565static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5623 struct drm_display_mode *mode,
5624 struct drm_display_mode *adjusted_mode,
5625 int x, int y, 5566 int x, int y,
5626 struct drm_framebuffer *fb) 5567 struct drm_framebuffer *fb)
5627{ 5568{
5628 struct drm_device *dev = crtc->dev; 5569 struct drm_device *dev = crtc->dev;
5629 struct drm_i915_private *dev_priv = dev->dev_private; 5570 struct drm_i915_private *dev_priv = dev->dev_private;
5630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5572 struct drm_display_mode *adjusted_mode =
5573 &intel_crtc->config.adjusted_mode;
5574 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5631 int pipe = intel_crtc->pipe; 5575 int pipe = intel_crtc->pipe;
5632 int plane = intel_crtc->plane; 5576 int plane = intel_crtc->plane;
5633 int num_connectors = 0; 5577 int num_connectors = 0;
5634 intel_clock_t clock, reduced_clock; 5578 intel_clock_t clock, reduced_clock;
5635 u32 dpll, fp = 0, fp2 = 0; 5579 u32 dpll, fp = 0, fp2 = 0;
5636 bool ok, has_reduced_clock = false; 5580 bool ok, has_reduced_clock = false;
5637 bool is_lvds = false, is_dp = false, is_cpu_edp = false; 5581 bool is_lvds = false;
5638 struct intel_encoder *encoder; 5582 struct intel_encoder *encoder;
5639 int ret; 5583 int ret;
5640 bool dither, fdi_config_ok; 5584 bool dither, fdi_config_ok;
@@ -5644,14 +5588,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5644 case INTEL_OUTPUT_LVDS: 5588 case INTEL_OUTPUT_LVDS:
5645 is_lvds = true; 5589 is_lvds = true;
5646 break; 5590 break;
5647 case INTEL_OUTPUT_DISPLAYPORT:
5648 is_dp = true;
5649 break;
5650 case INTEL_OUTPUT_EDP:
5651 is_dp = true;
5652 if (!intel_encoder_is_pch_edp(&encoder->base))
5653 is_cpu_edp = true;
5654 break;
5655 } 5591 }
5656 5592
5657 num_connectors++; 5593 num_connectors++;
@@ -5660,19 +5596,28 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5660 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 5596 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5661 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 5597 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5662 5598
5599 intel_crtc->cpu_transcoder = pipe;
5600
5663 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, 5601 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5664 &has_reduced_clock, &reduced_clock); 5602 &has_reduced_clock, &reduced_clock);
5665 if (!ok) { 5603 if (!ok) {
5666 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 5604 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5667 return -EINVAL; 5605 return -EINVAL;
5668 } 5606 }
5607 /* Compat-code for transition, will disappear. */
5608 if (!intel_crtc->config.clock_set) {
5609 intel_crtc->config.dpll.n = clock.n;
5610 intel_crtc->config.dpll.m1 = clock.m1;
5611 intel_crtc->config.dpll.m2 = clock.m2;
5612 intel_crtc->config.dpll.p1 = clock.p1;
5613 intel_crtc->config.dpll.p2 = clock.p2;
5614 }
5669 5615
5670 /* Ensure that the cursor is valid for the new mode before changing... */ 5616 /* Ensure that the cursor is valid for the new mode before changing... */
5671 intel_crtc_update_cursor(crtc, true); 5617 intel_crtc_update_cursor(crtc, true);
5672 5618
5673 /* determine panel color depth */ 5619 /* determine panel color depth */
5674 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, 5620 dither = intel_crtc->config.dither;
5675 adjusted_mode);
5676 if (is_lvds && dev_priv->lvds_dither) 5621 if (is_lvds && dev_priv->lvds_dither)
5677 dither = true; 5622 dither = true;
5678 5623
@@ -5681,13 +5626,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5681 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | 5626 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5682 reduced_clock.m2; 5627 reduced_clock.m2;
5683 5628
5684 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp); 5629 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5685 5630
5686 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5631 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5687 drm_mode_debug_printmodeline(mode); 5632 drm_mode_debug_printmodeline(mode);
5688 5633
5689 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5634 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5690 if (!is_cpu_edp) { 5635 if (intel_crtc->config.has_pch_encoder) {
5691 struct intel_pch_pll *pll; 5636 struct intel_pch_pll *pll;
5692 5637
5693 pll = intel_get_pch_pll(intel_crtc, dpll, fp); 5638 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
@@ -5699,8 +5644,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5699 } else 5644 } else
5700 intel_put_pch_pll(intel_crtc); 5645 intel_put_pch_pll(intel_crtc);
5701 5646
5702 if (is_dp && !is_cpu_edp) 5647 if (intel_crtc->config.has_dp_encoder)
5703 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5648 intel_dp_set_m_n(intel_crtc);
5704 5649
5705 for_each_encoder_on_crtc(dev, crtc, encoder) 5650 for_each_encoder_on_crtc(dev, crtc, encoder)
5706 if (encoder->pre_pll_enable) 5651 if (encoder->pre_pll_enable)
@@ -5735,7 +5680,9 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5735 5680
5736 /* Note, this also computes intel_crtc->fdi_lanes which is used below in 5681 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5737 * ironlake_check_fdi_lanes. */ 5682 * ironlake_check_fdi_lanes. */
5738 ironlake_set_m_n(crtc, mode, adjusted_mode); 5683 intel_crtc->fdi_lanes = 0;
5684 if (intel_crtc->config.has_pch_encoder)
5685 ironlake_fdi_set_m_n(crtc);
5739 5686
5740 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); 5687 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5741 5688
@@ -5756,6 +5703,23 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5756 return fdi_config_ok ? ret : -EINVAL; 5703 return fdi_config_ok ? ret : -EINVAL;
5757} 5704}
5758 5705
5706static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5707 struct intel_crtc_config *pipe_config)
5708{
5709 struct drm_device *dev = crtc->base.dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 uint32_t tmp;
5712
5713 tmp = I915_READ(PIPECONF(crtc->pipe));
5714 if (!(tmp & PIPECONF_ENABLE))
5715 return false;
5716
5717 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5718 pipe_config->has_pch_encoder = true;
5719
5720 return true;
5721}
5722
5759static void haswell_modeset_global_resources(struct drm_device *dev) 5723static void haswell_modeset_global_resources(struct drm_device *dev)
5760{ 5724{
5761 struct drm_i915_private *dev_priv = dev->dev_private; 5725 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5786,29 +5750,26 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
5786} 5750}
5787 5751
5788static int haswell_crtc_mode_set(struct drm_crtc *crtc, 5752static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5789 struct drm_display_mode *mode,
5790 struct drm_display_mode *adjusted_mode,
5791 int x, int y, 5753 int x, int y,
5792 struct drm_framebuffer *fb) 5754 struct drm_framebuffer *fb)
5793{ 5755{
5794 struct drm_device *dev = crtc->dev; 5756 struct drm_device *dev = crtc->dev;
5795 struct drm_i915_private *dev_priv = dev->dev_private; 5757 struct drm_i915_private *dev_priv = dev->dev_private;
5796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5759 struct drm_display_mode *adjusted_mode =
5760 &intel_crtc->config.adjusted_mode;
5761 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5797 int pipe = intel_crtc->pipe; 5762 int pipe = intel_crtc->pipe;
5798 int plane = intel_crtc->plane; 5763 int plane = intel_crtc->plane;
5799 int num_connectors = 0; 5764 int num_connectors = 0;
5800 bool is_dp = false, is_cpu_edp = false; 5765 bool is_cpu_edp = false;
5801 struct intel_encoder *encoder; 5766 struct intel_encoder *encoder;
5802 int ret; 5767 int ret;
5803 bool dither; 5768 bool dither;
5804 5769
5805 for_each_encoder_on_crtc(dev, crtc, encoder) { 5770 for_each_encoder_on_crtc(dev, crtc, encoder) {
5806 switch (encoder->type) { 5771 switch (encoder->type) {
5807 case INTEL_OUTPUT_DISPLAYPORT:
5808 is_dp = true;
5809 break;
5810 case INTEL_OUTPUT_EDP: 5772 case INTEL_OUTPUT_EDP:
5811 is_dp = true;
5812 if (!intel_encoder_is_pch_edp(&encoder->base)) 5773 if (!intel_encoder_is_pch_edp(&encoder->base))
5813 is_cpu_edp = true; 5774 is_cpu_edp = true;
5814 break; 5775 break;
@@ -5841,25 +5802,24 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5841 intel_crtc_update_cursor(crtc, true); 5802 intel_crtc_update_cursor(crtc, true);
5842 5803
5843 /* determine panel color depth */ 5804 /* determine panel color depth */
5844 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, 5805 dither = intel_crtc->config.dither;
5845 adjusted_mode);
5846 5806
5847 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5807 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5848 drm_mode_debug_printmodeline(mode); 5808 drm_mode_debug_printmodeline(mode);
5849 5809
5850 if (is_dp && !is_cpu_edp) 5810 if (intel_crtc->config.has_dp_encoder)
5851 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5811 intel_dp_set_m_n(intel_crtc);
5852 5812
5853 intel_crtc->lowfreq_avail = false; 5813 intel_crtc->lowfreq_avail = false;
5854 5814
5855 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5815 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5856 5816
5857 if (!is_dp || is_cpu_edp) 5817 if (intel_crtc->config.has_pch_encoder)
5858 ironlake_set_m_n(crtc, mode, adjusted_mode); 5818 ironlake_fdi_set_m_n(crtc);
5859 5819
5860 haswell_set_pipeconf(crtc, adjusted_mode, dither); 5820 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5861 5821
5862 intel_set_pipe_csc(crtc, adjusted_mode); 5822 intel_set_pipe_csc(crtc);
5863 5823
5864 /* Set up the display plane register */ 5824 /* Set up the display plane register */
5865 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); 5825 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
@@ -5874,9 +5834,32 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5874 return ret; 5834 return ret;
5875} 5835}
5876 5836
5837static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5838 struct intel_crtc_config *pipe_config)
5839{
5840 struct drm_device *dev = crtc->base.dev;
5841 struct drm_i915_private *dev_priv = dev->dev_private;
5842 uint32_t tmp;
5843
5844 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
5845 if (!(tmp & PIPECONF_ENABLE))
5846 return false;
5847
5848 /*
5849 * aswell has only FDI/PCH transcoder A. It is which is connected to
5850 * DDI E. So just check whether this pipe is wired to DDI E and whether
5851 * the PCH transcoder is on.
5852 */
5853 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5854 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5855 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5856 pipe_config->has_pch_encoder = true;
5857
5858
5859 return true;
5860}
5861
5877static int intel_crtc_mode_set(struct drm_crtc *crtc, 5862static int intel_crtc_mode_set(struct drm_crtc *crtc,
5878 struct drm_display_mode *mode,
5879 struct drm_display_mode *adjusted_mode,
5880 int x, int y, 5863 int x, int y,
5881 struct drm_framebuffer *fb) 5864 struct drm_framebuffer *fb)
5882{ 5865{
@@ -5885,13 +5868,16 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5885 struct drm_encoder_helper_funcs *encoder_funcs; 5868 struct drm_encoder_helper_funcs *encoder_funcs;
5886 struct intel_encoder *encoder; 5869 struct intel_encoder *encoder;
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5871 struct drm_display_mode *adjusted_mode =
5872 &intel_crtc->config.adjusted_mode;
5873 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5888 int pipe = intel_crtc->pipe; 5874 int pipe = intel_crtc->pipe;
5889 int ret; 5875 int ret;
5890 5876
5891 drm_vblank_pre_modeset(dev, pipe); 5877 drm_vblank_pre_modeset(dev, pipe);
5892 5878
5893 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, 5879 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5894 x, y, fb); 5880
5895 drm_vblank_post_modeset(dev, pipe); 5881 drm_vblank_post_modeset(dev, pipe);
5896 5882
5897 if (ret != 0) 5883 if (ret != 0)
@@ -5902,8 +5888,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5902 encoder->base.base.id, 5888 encoder->base.base.id,
5903 drm_get_encoder_name(&encoder->base), 5889 drm_get_encoder_name(&encoder->base),
5904 mode->base.id, mode->name); 5890 mode->base.id, mode->name);
5905 encoder_funcs = encoder->base.helper_private; 5891 if (encoder->mode_set) {
5906 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); 5892 encoder->mode_set(encoder);
5893 } else {
5894 encoder_funcs = encoder->base.helper_private;
5895 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5896 }
5907 } 5897 }
5908 5898
5909 return 0; 5899 return 0;
@@ -6371,13 +6361,24 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6371 /* we only need to pin inside GTT if cursor is non-phy */ 6361 /* we only need to pin inside GTT if cursor is non-phy */
6372 mutex_lock(&dev->struct_mutex); 6362 mutex_lock(&dev->struct_mutex);
6373 if (!dev_priv->info->cursor_needs_physical) { 6363 if (!dev_priv->info->cursor_needs_physical) {
6364 unsigned alignment;
6365
6374 if (obj->tiling_mode) { 6366 if (obj->tiling_mode) {
6375 DRM_ERROR("cursor cannot be tiled\n"); 6367 DRM_ERROR("cursor cannot be tiled\n");
6376 ret = -EINVAL; 6368 ret = -EINVAL;
6377 goto fail_locked; 6369 goto fail_locked;
6378 } 6370 }
6379 6371
6380 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); 6372 /* Note that the w/a also requires 2 PTE of padding following
6373 * the bo. We currently fill all unused PTE with the shadow
6374 * page and so we should always have valid PTE following the
6375 * cursor preventing the VT-d warning.
6376 */
6377 alignment = 0;
6378 if (need_vtd_wa(dev))
6379 alignment = 64*1024;
6380
6381 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6381 if (ret) { 6382 if (ret) {
6382 DRM_ERROR("failed to move cursor bo into the GTT\n"); 6383 DRM_ERROR("failed to move cursor bo into the GTT\n");
6383 goto fail_locked; 6384 goto fail_locked;
@@ -7502,19 +7503,93 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
7502 } 7503 }
7503} 7504}
7504 7505
7505static struct drm_display_mode * 7506static int
7506intel_modeset_adjusted_mode(struct drm_crtc *crtc, 7507pipe_config_set_bpp(struct drm_crtc *crtc,
7507 struct drm_display_mode *mode) 7508 struct drm_framebuffer *fb,
7509 struct intel_crtc_config *pipe_config)
7510{
7511 struct drm_device *dev = crtc->dev;
7512 struct drm_connector *connector;
7513 int bpp;
7514
7515 switch (fb->pixel_format) {
7516 case DRM_FORMAT_C8:
7517 bpp = 8*3; /* since we go through a colormap */
7518 break;
7519 case DRM_FORMAT_XRGB1555:
7520 case DRM_FORMAT_ARGB1555:
7521 /* checked in intel_framebuffer_init already */
7522 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7523 return -EINVAL;
7524 case DRM_FORMAT_RGB565:
7525 bpp = 6*3; /* min is 18bpp */
7526 break;
7527 case DRM_FORMAT_XBGR8888:
7528 case DRM_FORMAT_ABGR8888:
7529 /* checked in intel_framebuffer_init already */
7530 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7531 return -EINVAL;
7532 case DRM_FORMAT_XRGB8888:
7533 case DRM_FORMAT_ARGB8888:
7534 bpp = 8*3;
7535 break;
7536 case DRM_FORMAT_XRGB2101010:
7537 case DRM_FORMAT_ARGB2101010:
7538 case DRM_FORMAT_XBGR2101010:
7539 case DRM_FORMAT_ABGR2101010:
7540 /* checked in intel_framebuffer_init already */
7541 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7542 return -EINVAL;
7543 bpp = 10*3;
7544 break;
7545 /* TODO: gen4+ supports 16 bpc floating point, too. */
7546 default:
7547 DRM_DEBUG_KMS("unsupported depth\n");
7548 return -EINVAL;
7549 }
7550
7551 pipe_config->pipe_bpp = bpp;
7552
7553 /* Clamp display bpp to EDID value */
7554 list_for_each_entry(connector, &dev->mode_config.connector_list,
7555 head) {
7556 if (connector->encoder && connector->encoder->crtc != crtc)
7557 continue;
7558
7559 /* Don't use an invalid EDID bpc value */
7560 if (connector->display_info.bpc &&
7561 connector->display_info.bpc * 3 < bpp) {
7562 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7563 bpp, connector->display_info.bpc*3);
7564 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7565 }
7566 }
7567
7568 return bpp;
7569}
7570
7571static struct intel_crtc_config *
7572intel_modeset_pipe_config(struct drm_crtc *crtc,
7573 struct drm_framebuffer *fb,
7574 struct drm_display_mode *mode)
7508{ 7575{
7509 struct drm_device *dev = crtc->dev; 7576 struct drm_device *dev = crtc->dev;
7510 struct drm_display_mode *adjusted_mode;
7511 struct drm_encoder_helper_funcs *encoder_funcs; 7577 struct drm_encoder_helper_funcs *encoder_funcs;
7512 struct intel_encoder *encoder; 7578 struct intel_encoder *encoder;
7579 struct intel_crtc_config *pipe_config;
7580 int plane_bpp;
7513 7581
7514 adjusted_mode = drm_mode_duplicate(dev, mode); 7582 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7515 if (!adjusted_mode) 7583 if (!pipe_config)
7516 return ERR_PTR(-ENOMEM); 7584 return ERR_PTR(-ENOMEM);
7517 7585
7586 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7587 drm_mode_copy(&pipe_config->requested_mode, mode);
7588
7589 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7590 if (plane_bpp < 0)
7591 goto fail;
7592
7518 /* Pass our mode to the connectors and the CRTC to give them a chance to 7593 /* Pass our mode to the connectors and the CRTC to give them a chance to
7519 * adjust it according to limitations or connector properties, and also 7594 * adjust it according to limitations or connector properties, and also
7520 * a chance to reject the mode entirely. 7595 * a chance to reject the mode entirely.
@@ -7524,23 +7599,38 @@ intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7524 7599
7525 if (&encoder->new_crtc->base != crtc) 7600 if (&encoder->new_crtc->base != crtc)
7526 continue; 7601 continue;
7602
7603 if (encoder->compute_config) {
7604 if (!(encoder->compute_config(encoder, pipe_config))) {
7605 DRM_DEBUG_KMS("Encoder config failure\n");
7606 goto fail;
7607 }
7608
7609 continue;
7610 }
7611
7527 encoder_funcs = encoder->base.helper_private; 7612 encoder_funcs = encoder->base.helper_private;
7528 if (!(encoder_funcs->mode_fixup(&encoder->base, mode, 7613 if (!(encoder_funcs->mode_fixup(&encoder->base,
7529 adjusted_mode))) { 7614 &pipe_config->requested_mode,
7615 &pipe_config->adjusted_mode))) {
7530 DRM_DEBUG_KMS("Encoder fixup failed\n"); 7616 DRM_DEBUG_KMS("Encoder fixup failed\n");
7531 goto fail; 7617 goto fail;
7532 } 7618 }
7533 } 7619 }
7534 7620
7535 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { 7621 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7536 DRM_DEBUG_KMS("CRTC fixup failed\n"); 7622 DRM_DEBUG_KMS("CRTC fixup failed\n");
7537 goto fail; 7623 goto fail;
7538 } 7624 }
7539 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); 7625 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7540 7626
7541 return adjusted_mode; 7627 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7628 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7629 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7630
7631 return pipe_config;
7542fail: 7632fail:
7543 drm_mode_destroy(dev, adjusted_mode); 7633 kfree(pipe_config);
7544 return ERR_PTR(-EINVAL); 7634 return ERR_PTR(-EINVAL);
7545} 7635}
7546 7636
@@ -7702,12 +7792,29 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7702 base.head) \ 7792 base.head) \
7703 if (mask & (1 <<(intel_crtc)->pipe)) \ 7793 if (mask & (1 <<(intel_crtc)->pipe)) \
7704 7794
7795static bool
7796intel_pipe_config_compare(struct intel_crtc_config *current_config,
7797 struct intel_crtc_config *pipe_config)
7798{
7799 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7800 DRM_ERROR("mismatch in has_pch_encoder "
7801 "(expected %i, found %i)\n",
7802 current_config->has_pch_encoder,
7803 pipe_config->has_pch_encoder);
7804 return false;
7805 }
7806
7807 return true;
7808}
7809
7705void 7810void
7706intel_modeset_check_state(struct drm_device *dev) 7811intel_modeset_check_state(struct drm_device *dev)
7707{ 7812{
7813 drm_i915_private_t *dev_priv = dev->dev_private;
7708 struct intel_crtc *crtc; 7814 struct intel_crtc *crtc;
7709 struct intel_encoder *encoder; 7815 struct intel_encoder *encoder;
7710 struct intel_connector *connector; 7816 struct intel_connector *connector;
7817 struct intel_crtc_config pipe_config;
7711 7818
7712 list_for_each_entry(connector, &dev->mode_config.connector_list, 7819 list_for_each_entry(connector, &dev->mode_config.connector_list,
7713 base.head) { 7820 base.head) {
@@ -7796,7 +7903,16 @@ intel_modeset_check_state(struct drm_device *dev)
7796 "crtc's computed enabled state doesn't match tracked enabled state " 7903 "crtc's computed enabled state doesn't match tracked enabled state "
7797 "(expected %i, found %i)\n", enabled, crtc->base.enabled); 7904 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7798 7905
7799 assert_pipe(dev->dev_private, crtc->pipe, crtc->active); 7906 memset(&pipe_config, 0, sizeof(pipe_config));
7907 active = dev_priv->display.get_pipe_config(crtc,
7908 &pipe_config);
7909 WARN(crtc->active != active,
7910 "crtc active state doesn't match with hw state "
7911 "(expected %i, found %i)\n", crtc->active, active);
7912
7913 WARN(active &&
7914 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7915 "pipe state doesn't match!\n");
7800 } 7916 }
7801} 7917}
7802 7918
@@ -7806,7 +7922,8 @@ int intel_set_mode(struct drm_crtc *crtc,
7806{ 7922{
7807 struct drm_device *dev = crtc->dev; 7923 struct drm_device *dev = crtc->dev;
7808 drm_i915_private_t *dev_priv = dev->dev_private; 7924 drm_i915_private_t *dev_priv = dev->dev_private;
7809 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode; 7925 struct drm_display_mode *saved_mode, *saved_hwmode;
7926 struct intel_crtc_config *pipe_config = NULL;
7810 struct intel_crtc *intel_crtc; 7927 struct intel_crtc *intel_crtc;
7811 unsigned disable_pipes, prepare_pipes, modeset_pipes; 7928 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7812 int ret = 0; 7929 int ret = 0;
@@ -7819,12 +7936,6 @@ int intel_set_mode(struct drm_crtc *crtc,
7819 intel_modeset_affected_pipes(crtc, &modeset_pipes, 7936 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7820 &prepare_pipes, &disable_pipes); 7937 &prepare_pipes, &disable_pipes);
7821 7938
7822 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7823 modeset_pipes, prepare_pipes, disable_pipes);
7824
7825 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7826 intel_crtc_disable(&intel_crtc->base);
7827
7828 *saved_hwmode = crtc->hwmode; 7939 *saved_hwmode = crtc->hwmode;
7829 *saved_mode = crtc->mode; 7940 *saved_mode = crtc->mode;
7830 7941
@@ -7833,15 +7944,22 @@ int intel_set_mode(struct drm_crtc *crtc,
7833 * Hence simply check whether any bit is set in modeset_pipes in all the 7944 * Hence simply check whether any bit is set in modeset_pipes in all the
7834 * pieces of code that are not yet converted to deal with mutliple crtcs 7945 * pieces of code that are not yet converted to deal with mutliple crtcs
7835 * changing their mode at the same time. */ 7946 * changing their mode at the same time. */
7836 adjusted_mode = NULL;
7837 if (modeset_pipes) { 7947 if (modeset_pipes) {
7838 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); 7948 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7839 if (IS_ERR(adjusted_mode)) { 7949 if (IS_ERR(pipe_config)) {
7840 ret = PTR_ERR(adjusted_mode); 7950 ret = PTR_ERR(pipe_config);
7951 pipe_config = NULL;
7952
7841 goto out; 7953 goto out;
7842 } 7954 }
7843 } 7955 }
7844 7956
7957 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7958 modeset_pipes, prepare_pipes, disable_pipes);
7959
7960 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7961 intel_crtc_disable(&intel_crtc->base);
7962
7845 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { 7963 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7846 if (intel_crtc->base.enabled) 7964 if (intel_crtc->base.enabled)
7847 dev_priv->display.crtc_disable(&intel_crtc->base); 7965 dev_priv->display.crtc_disable(&intel_crtc->base);
@@ -7850,8 +7968,12 @@ int intel_set_mode(struct drm_crtc *crtc,
7850 /* crtc->mode is already used by the ->mode_set callbacks, hence we need 7968 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7851 * to set it here already despite that we pass it down the callchain. 7969 * to set it here already despite that we pass it down the callchain.
7852 */ 7970 */
7853 if (modeset_pipes) 7971 if (modeset_pipes) {
7854 crtc->mode = *mode; 7972 crtc->mode = *mode;
7973 /* mode_set/enable/disable functions rely on a correct pipe
7974 * config. */
7975 to_intel_crtc(crtc)->config = *pipe_config;
7976 }
7855 7977
7856 /* Only after disabling all output pipelines that will be changed can we 7978 /* Only after disabling all output pipelines that will be changed can we
7857 * update the the output configuration. */ 7979 * update the the output configuration. */
@@ -7865,7 +7987,6 @@ int intel_set_mode(struct drm_crtc *crtc,
7865 */ 7987 */
7866 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { 7988 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7867 ret = intel_crtc_mode_set(&intel_crtc->base, 7989 ret = intel_crtc_mode_set(&intel_crtc->base,
7868 mode, adjusted_mode,
7869 x, y, fb); 7990 x, y, fb);
7870 if (ret) 7991 if (ret)
7871 goto done; 7992 goto done;
@@ -7877,7 +7998,7 @@ int intel_set_mode(struct drm_crtc *crtc,
7877 7998
7878 if (modeset_pipes) { 7999 if (modeset_pipes) {
7879 /* Store real post-adjustment hardware mode. */ 8000 /* Store real post-adjustment hardware mode. */
7880 crtc->hwmode = *adjusted_mode; 8001 crtc->hwmode = pipe_config->adjusted_mode;
7881 8002
7882 /* Calculate and store various constants which 8003 /* Calculate and store various constants which
7883 * are later needed by vblank and swap-completion 8004 * are later needed by vblank and swap-completion
@@ -7888,7 +8009,6 @@ int intel_set_mode(struct drm_crtc *crtc,
7888 8009
7889 /* FIXME: add subpixel order */ 8010 /* FIXME: add subpixel order */
7890done: 8011done:
7891 drm_mode_destroy(dev, adjusted_mode);
7892 if (ret && crtc->enabled) { 8012 if (ret && crtc->enabled) {
7893 crtc->hwmode = *saved_hwmode; 8013 crtc->hwmode = *saved_hwmode;
7894 crtc->mode = *saved_mode; 8014 crtc->mode = *saved_mode;
@@ -7897,6 +8017,7 @@ done:
7897 } 8017 }
7898 8018
7899out: 8019out:
8020 kfree(pipe_config);
7900 kfree(saved_mode); 8021 kfree(saved_mode);
7901 return ret; 8022 return ret;
7902} 8023}
@@ -7988,10 +8109,8 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7988 config->mode_changed = true; 8109 config->mode_changed = true;
7989 } else if (set->fb == NULL) { 8110 } else if (set->fb == NULL) {
7990 config->mode_changed = true; 8111 config->mode_changed = true;
7991 } else if (set->fb->depth != set->crtc->fb->depth) { 8112 } else if (set->fb->pixel_format !=
7992 config->mode_changed = true; 8113 set->crtc->fb->pixel_format) {
7993 } else if (set->fb->bits_per_pixel !=
7994 set->crtc->fb->bits_per_pixel) {
7995 config->mode_changed = true; 8114 config->mode_changed = true;
7996 } else 8115 } else
7997 config->fb_changed = true; 8116 config->fb_changed = true;
@@ -8263,8 +8382,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
8263 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 8382 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8264 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 8383 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8265 8384
8266 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8267
8268 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 8385 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8269} 8386}
8270 8387
@@ -8601,18 +8718,21 @@ static void intel_init_display(struct drm_device *dev)
8601 struct drm_i915_private *dev_priv = dev->dev_private; 8718 struct drm_i915_private *dev_priv = dev->dev_private;
8602 8719
8603 if (HAS_DDI(dev)) { 8720 if (HAS_DDI(dev)) {
8721 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8604 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; 8722 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8605 dev_priv->display.crtc_enable = haswell_crtc_enable; 8723 dev_priv->display.crtc_enable = haswell_crtc_enable;
8606 dev_priv->display.crtc_disable = haswell_crtc_disable; 8724 dev_priv->display.crtc_disable = haswell_crtc_disable;
8607 dev_priv->display.off = haswell_crtc_off; 8725 dev_priv->display.off = haswell_crtc_off;
8608 dev_priv->display.update_plane = ironlake_update_plane; 8726 dev_priv->display.update_plane = ironlake_update_plane;
8609 } else if (HAS_PCH_SPLIT(dev)) { 8727 } else if (HAS_PCH_SPLIT(dev)) {
8728 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8610 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 8729 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8611 dev_priv->display.crtc_enable = ironlake_crtc_enable; 8730 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8612 dev_priv->display.crtc_disable = ironlake_crtc_disable; 8731 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8613 dev_priv->display.off = ironlake_crtc_off; 8732 dev_priv->display.off = ironlake_crtc_off;
8614 dev_priv->display.update_plane = ironlake_update_plane; 8733 dev_priv->display.update_plane = ironlake_update_plane;
8615 } else { 8734 } else {
8735 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8616 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 8736 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8617 dev_priv->display.crtc_enable = i9xx_crtc_enable; 8737 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8618 dev_priv->display.crtc_disable = i9xx_crtc_disable; 8738 dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -8855,7 +8975,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
8855void intel_modeset_init(struct drm_device *dev) 8975void intel_modeset_init(struct drm_device *dev)
8856{ 8976{
8857 struct drm_i915_private *dev_priv = dev->dev_private; 8977 struct drm_i915_private *dev_priv = dev->dev_private;
8858 int i, ret; 8978 int i, j, ret;
8859 8979
8860 drm_mode_config_init(dev); 8980 drm_mode_config_init(dev);
8861 8981
@@ -8891,9 +9011,12 @@ void intel_modeset_init(struct drm_device *dev)
8891 9011
8892 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { 9012 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8893 intel_crtc_init(dev, i); 9013 intel_crtc_init(dev, i);
8894 ret = intel_plane_init(dev, i); 9014 for (j = 0; j < dev_priv->num_plane; j++) {
8895 if (ret) 9015 ret = intel_plane_init(dev, i, j);
8896 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); 9016 if (ret)
9017 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9018 i, j, ret);
9019 }
8897 } 9020 }
8898 9021
8899 intel_cpu_pll_init(dev); 9022 intel_cpu_pll_init(dev);
@@ -9106,6 +9229,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
9106 struct drm_i915_private *dev_priv = dev->dev_private; 9229 struct drm_i915_private *dev_priv = dev->dev_private;
9107 enum pipe pipe; 9230 enum pipe pipe;
9108 u32 tmp; 9231 u32 tmp;
9232 struct drm_plane *plane;
9109 struct intel_crtc *crtc; 9233 struct intel_crtc *crtc;
9110 struct intel_encoder *encoder; 9234 struct intel_encoder *encoder;
9111 struct intel_connector *connector; 9235 struct intel_connector *connector;
@@ -9125,6 +9249,13 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
9125 case TRANS_DDI_EDP_INPUT_C_ONOFF: 9249 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9126 pipe = PIPE_C; 9250 pipe = PIPE_C;
9127 break; 9251 break;
9252 default:
9253 /* A bogus value has been programmed, disable
9254 * the transcoder */
9255 WARN(1, "Bogus eDP source %08x\n", tmp);
9256 intel_ddi_disable_transcoder_func(dev_priv,
9257 TRANSCODER_EDP);
9258 goto setup_pipes;
9128 } 9259 }
9129 9260
9130 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9261 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
@@ -9135,14 +9266,12 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
9135 } 9266 }
9136 } 9267 }
9137 9268
9138 for_each_pipe(pipe) { 9269setup_pipes:
9139 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9270 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9140 9271 base.head) {
9141 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); 9272 memset(&crtc->config, 0, sizeof(crtc->config));
9142 if (tmp & PIPECONF_ENABLE) 9273 crtc->active = dev_priv->display.get_pipe_config(crtc,
9143 crtc->active = true; 9274 &crtc->config);
9144 else
9145 crtc->active = false;
9146 9275
9147 crtc->base.enabled = crtc->active; 9276 crtc->base.enabled = crtc->active;
9148 9277
@@ -9202,8 +9331,12 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
9202 9331
9203 if (force_restore) { 9332 if (force_restore) {
9204 for_each_pipe(pipe) { 9333 for_each_pipe(pipe) {
9205 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]); 9334 struct drm_crtc *crtc =
9335 dev_priv->pipe_to_crtc_mapping[pipe];
9336 intel_crtc_restore_mode(crtc);
9206 } 9337 }
9338 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9339 intel_plane_restore(plane);
9207 9340
9208 i915_redisable_vga(dev); 9341 i915_redisable_vga(dev);
9209 } else { 9342 } else {
@@ -9364,9 +9497,10 @@ intel_display_capture_error_state(struct drm_device *dev)
9364 9497
9365 error->plane[i].control = I915_READ(DSPCNTR(i)); 9498 error->plane[i].control = I915_READ(DSPCNTR(i));
9366 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 9499 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9367 if (INTEL_INFO(dev)->gen <= 3) 9500 if (INTEL_INFO(dev)->gen <= 3) {
9368 error->plane[i].size = I915_READ(DSPSIZE(i)); 9501 error->plane[i].size = I915_READ(DSPSIZE(i));
9369 error->plane[i].pos = I915_READ(DSPPOS(i)); 9502 error->plane[i].pos = I915_READ(DSPPOS(i));
9503 }
9370 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) 9504 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9371 error->plane[i].addr = I915_READ(DSPADDR(i)); 9505 error->plane[i].addr = I915_READ(DSPADDR(i));
9372 if (INTEL_INFO(dev)->gen >= 4) { 9506 if (INTEL_INFO(dev)->gen >= 4) {
@@ -9409,10 +9543,11 @@ intel_display_print_error_state(struct seq_file *m,
9409 seq_printf(m, "Plane [%d]:\n", i); 9543 seq_printf(m, "Plane [%d]:\n", i);
9410 seq_printf(m, " CNTR: %08x\n", error->plane[i].control); 9544 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9411 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 9545 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9412 if (INTEL_INFO(dev)->gen <= 3) 9546 if (INTEL_INFO(dev)->gen <= 3) {
9413 seq_printf(m, " SIZE: %08x\n", error->plane[i].size); 9547 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9414 seq_printf(m, " POS: %08x\n", error->plane[i].pos); 9548 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9415 if (!IS_HASWELL(dev)) 9549 }
9550 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9416 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); 9551 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9417 if (INTEL_INFO(dev)->gen >= 4) { 9552 if (INTEL_INFO(dev)->gen >= 4) {
9418 seq_printf(m, " SURF: %08x\n", error->plane[i].surface); 9553 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fe111f1aadb3..b30e82b98439 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -109,29 +109,6 @@ bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
109 109
110static void intel_dp_link_down(struct intel_dp *intel_dp); 110static void intel_dp_link_down(struct intel_dp *intel_dp);
111 111
112void
113intel_edp_link_config(struct intel_encoder *intel_encoder,
114 int *lane_num, int *link_bw)
115{
116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
117
118 *lane_num = intel_dp->lane_count;
119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
120}
121
122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
127 struct intel_connector *intel_connector = intel_dp->attached_connector;
128
129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
131 else
132 return mode->clock;
133}
134
135static int 112static int
136intel_dp_max_link_bw(struct intel_dp *intel_dp) 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
137{ 114{
@@ -177,34 +154,6 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
177 return (max_link_clock * max_lanes * 8) / 10; 154 return (max_link_clock * max_lanes * 8) / 10;
178} 155}
179 156
180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
183 bool adjust_mode)
184{
185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
198 if (adjust_mode)
199 mode->private_flags
200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
208static int 157static int
209intel_dp_mode_valid(struct drm_connector *connector, 158intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode) 159 struct drm_display_mode *mode)
@@ -212,6 +161,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
212 struct intel_dp *intel_dp = intel_attached_dp(connector); 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
213 struct intel_connector *intel_connector = to_intel_connector(connector); 162 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
215 166
216 if (is_edp(intel_dp) && fixed_mode) { 167 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay) 168 if (mode->hdisplay > fixed_mode->hdisplay)
@@ -219,9 +170,17 @@ intel_dp_mode_valid(struct drm_connector *connector,
219 170
220 if (mode->vdisplay > fixed_mode->vdisplay) 171 if (mode->vdisplay > fixed_mode->vdisplay)
221 return MODE_PANEL; 172 return MODE_PANEL;
173
174 target_clock = fixed_mode->clock;
222 } 175 }
223 176
224 if (!intel_dp_adjust_dithering(intel_dp, mode, false)) 177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
225 return MODE_CLOCK_HIGH; 184 return MODE_CLOCK_HIGH;
226 185
227 if (mode->clock < 10000) 186 if (mode->clock < 10000)
@@ -294,16 +253,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{ 253{
295 struct drm_device *dev = intel_dp_to_dev(intel_dp); 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296 struct drm_i915_private *dev_priv = dev->dev_private; 255 struct drm_i915_private *dev_priv = dev->dev_private;
256 u32 pp_stat_reg;
297 257
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; 258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
299} 260}
300 261
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{ 263{
303 struct drm_device *dev = intel_dp_to_dev(intel_dp); 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
304 struct drm_i915_private *dev_priv = dev->dev_private; 265 struct drm_i915_private *dev_priv = dev->dev_private;
266 u32 pp_ctrl_reg;
305 267
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; 268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
307} 270}
308 271
309static void 272static void
@@ -311,14 +274,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
311{ 274{
312 struct drm_device *dev = intel_dp_to_dev(intel_dp); 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
313 struct drm_i915_private *dev_priv = dev->dev_private; 276 struct drm_i915_private *dev_priv = dev->dev_private;
277 u32 pp_stat_reg, pp_ctrl_reg;
314 278
315 if (!is_edp(intel_dp)) 279 if (!is_edp(intel_dp))
316 return; 280 return;
281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
318 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
320 I915_READ(PCH_PP_STATUS), 288 I915_READ(pp_stat_reg),
321 I915_READ(PCH_PP_CONTROL)); 289 I915_READ(pp_ctrl_reg));
322 } 290 }
323} 291}
324 292
@@ -689,18 +657,26 @@ intel_dp_i2c_init(struct intel_dp *intel_dp,
689} 657}
690 658
691bool 659bool
692intel_dp_mode_fixup(struct drm_encoder *encoder, 660intel_dp_compute_config(struct intel_encoder *encoder,
693 const struct drm_display_mode *mode, 661 struct intel_crtc_config *pipe_config)
694 struct drm_display_mode *adjusted_mode)
695{ 662{
696 struct drm_device *dev = encoder->dev; 663 struct drm_device *dev = encoder->base.dev;
697 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 664 struct drm_i915_private *dev_priv = dev->dev_private;
665 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
666 struct drm_display_mode *mode = &pipe_config->requested_mode;
667 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
698 struct intel_connector *intel_connector = intel_dp->attached_connector; 668 struct intel_connector *intel_connector = intel_dp->attached_connector;
699 int lane_count, clock; 669 int lane_count, clock;
700 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 670 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
701 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 671 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
702 int bpp, mode_rate; 672 int bpp, mode_rate;
703 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 673 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
674 int target_clock, link_avail, link_clock;
675
676 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
677 pipe_config->has_pch_encoder = true;
678
679 pipe_config->has_dp_encoder = true;
704 680
705 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 681 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
706 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 682 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
@@ -709,6 +685,8 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
709 intel_connector->panel.fitting_mode, 685 intel_connector->panel.fitting_mode,
710 mode, adjusted_mode); 686 mode, adjusted_mode);
711 } 687 }
688 /* We need to take the panel's fixed mode into account. */
689 target_clock = adjusted_mode->clock;
712 690
713 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 691 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
714 return false; 692 return false;
@@ -717,11 +695,28 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
717 "max bw %02x pixel clock %iKHz\n", 695 "max bw %02x pixel clock %iKHz\n",
718 max_lane_count, bws[max_clock], adjusted_mode->clock); 696 max_lane_count, bws[max_clock], adjusted_mode->clock);
719 697
720 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) 698 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
721 return false; 699 * bpc in between. */
700 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
701 for (; bpp >= 6*3; bpp -= 2*3) {
702 mode_rate = intel_dp_link_required(target_clock, bpp);
703
704 for (clock = 0; clock <= max_clock; clock++) {
705 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
706 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
707 link_avail = intel_dp_max_data_rate(link_clock,
708 lane_count);
709
710 if (mode_rate <= link_avail) {
711 goto found;
712 }
713 }
714 }
715 }
722 716
723 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; 717 return false;
724 718
719found:
725 if (intel_dp->color_range_auto) { 720 if (intel_dp->color_range_auto) {
726 /* 721 /*
727 * See: 722 * See:
@@ -735,104 +730,38 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
735 } 730 }
736 731
737 if (intel_dp->color_range) 732 if (intel_dp->color_range)
738 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; 733 pipe_config->limited_color_range = true;
739
740 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
741
742 for (clock = 0; clock <= max_clock; clock++) {
743 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
744 int link_bw_clock =
745 drm_dp_bw_code_to_link_rate(bws[clock]);
746 int link_avail = intel_dp_max_data_rate(link_bw_clock,
747 lane_count);
748
749 if (mode_rate <= link_avail) {
750 intel_dp->link_bw = bws[clock];
751 intel_dp->lane_count = lane_count;
752 adjusted_mode->clock = link_bw_clock;
753 DRM_DEBUG_KMS("DP link bw %02x lane "
754 "count %d clock %d bpp %d\n",
755 intel_dp->link_bw, intel_dp->lane_count,
756 adjusted_mode->clock, bpp);
757 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
758 mode_rate, link_avail);
759 return true;
760 }
761 }
762 }
763 734
764 return false; 735 intel_dp->link_bw = bws[clock];
765} 736 intel_dp->lane_count = lane_count;
737 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
738 pipe_config->pixel_target_clock = target_clock;
766 739
767void 740 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
768intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 741 intel_dp->link_bw, intel_dp->lane_count,
769 struct drm_display_mode *adjusted_mode) 742 adjusted_mode->clock, bpp);
770{ 743 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
771 struct drm_device *dev = crtc->dev; 744 mode_rate, link_avail);
772 struct intel_encoder *intel_encoder;
773 struct intel_dp *intel_dp;
774 struct drm_i915_private *dev_priv = dev->dev_private;
775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
776 int lane_count = 4;
777 struct intel_link_m_n m_n;
778 int pipe = intel_crtc->pipe;
779 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
780 int target_clock;
781
782 /*
783 * Find the lane count in the intel_encoder private
784 */
785 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
786 intel_dp = enc_to_intel_dp(&intel_encoder->base);
787 745
788 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 746 intel_link_compute_m_n(bpp, lane_count,
789 intel_encoder->type == INTEL_OUTPUT_EDP) 747 target_clock, adjusted_mode->clock,
790 { 748 &pipe_config->dp_m_n);
791 lane_count = intel_dp->lane_count;
792 break;
793 }
794 }
795
796 target_clock = mode->clock;
797 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
798 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
799 target_clock = intel_edp_target_clock(intel_encoder,
800 mode);
801 break;
802 }
803 }
804 749
805 /* 750 /*
806 * Compute the GMCH and Link ratios. The '3' here is 751 * XXX: We have a strange regression where using the vbt edp bpp value
807 * the number of bytes_per_pixel post-LUT, which we always 752 * for the link bw computation results in black screens, the panel only
808 * set up for 8-bits of R/G/B, or 3 bytes total. 753 * works when we do the computation at the usual 24bpp (but still
754 * requires us to use 18bpp). Until that's fully debugged, stay
755 * bug-for-bug compatible with the old code.
809 */ 756 */
810 intel_link_compute_m_n(intel_crtc->bpp, lane_count, 757 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
811 target_clock, adjusted_mode->clock, &m_n); 758 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
812 759 bpp, dev_priv->edp.bpp);
813 if (HAS_DDI(dev)) { 760 bpp = min_t(int, bpp, dev_priv->edp.bpp);
814 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
815 TU_SIZE(m_n.tu) | m_n.gmch_m);
816 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
817 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
818 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
819 } else if (HAS_PCH_SPLIT(dev)) {
820 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
821 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
822 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
823 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
824 } else if (IS_VALLEYVIEW(dev)) {
825 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
826 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
827 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
828 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
829 } else {
830 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
831 TU_SIZE(m_n.tu) | m_n.gmch_m);
832 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
833 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
834 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
835 } 761 }
762 pipe_config->pipe_bpp = bpp;
763
764 return true;
836} 765}
837 766
838void intel_dp_init_link_config(struct intel_dp *intel_dp) 767void intel_dp_init_link_config(struct intel_dp *intel_dp)
@@ -951,7 +880,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
951 else 880 else
952 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 881 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
953 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 882 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
954 if (!HAS_PCH_SPLIT(dev)) 883 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
955 intel_dp->DP |= intel_dp->color_range; 884 intel_dp->DP |= intel_dp->color_range;
956 885
957 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 886 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -966,7 +895,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
966 if (intel_crtc->pipe == 1) 895 if (intel_crtc->pipe == 1)
967 intel_dp->DP |= DP_PIPEB_SELECT; 896 intel_dp->DP |= DP_PIPEB_SELECT;
968 897
969 if (is_cpu_edp(intel_dp)) { 898 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
970 /* don't miss out required setting for eDP */ 899 /* don't miss out required setting for eDP */
971 if (adjusted_mode->clock < 200000) 900 if (adjusted_mode->clock < 200000)
972 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 901 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
@@ -996,16 +925,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
996{ 925{
997 struct drm_device *dev = intel_dp_to_dev(intel_dp); 926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
998 struct drm_i915_private *dev_priv = dev->dev_private; 927 struct drm_i915_private *dev_priv = dev->dev_private;
928 u32 pp_stat_reg, pp_ctrl_reg;
929
930 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
931 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
999 932
1000 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 933 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1001 mask, value, 934 mask, value,
1002 I915_READ(PCH_PP_STATUS), 935 I915_READ(pp_stat_reg),
1003 I915_READ(PCH_PP_CONTROL)); 936 I915_READ(pp_ctrl_reg));
1004 937
1005 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { 938 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1006 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 939 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1007 I915_READ(PCH_PP_STATUS), 940 I915_READ(pp_stat_reg),
1008 I915_READ(PCH_PP_CONTROL)); 941 I915_READ(pp_ctrl_reg));
1009 } 942 }
1010} 943}
1011 944
@@ -1032,9 +965,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1032 * is locked 965 * is locked
1033 */ 966 */
1034 967
1035static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) 968static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1036{ 969{
1037 u32 control = I915_READ(PCH_PP_CONTROL); 970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
971 struct drm_i915_private *dev_priv = dev->dev_private;
972 u32 control;
973 u32 pp_ctrl_reg;
974
975 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
976 control = I915_READ(pp_ctrl_reg);
1038 977
1039 control &= ~PANEL_UNLOCK_MASK; 978 control &= ~PANEL_UNLOCK_MASK;
1040 control |= PANEL_UNLOCK_REGS; 979 control |= PANEL_UNLOCK_REGS;
@@ -1046,6 +985,7 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1046 struct drm_device *dev = intel_dp_to_dev(intel_dp); 985 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1047 struct drm_i915_private *dev_priv = dev->dev_private; 986 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 pp; 987 u32 pp;
988 u32 pp_stat_reg, pp_ctrl_reg;
1049 989
1050 if (!is_edp(intel_dp)) 990 if (!is_edp(intel_dp))
1051 return; 991 return;
@@ -1064,13 +1004,16 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1064 if (!ironlake_edp_have_panel_power(intel_dp)) 1004 if (!ironlake_edp_have_panel_power(intel_dp))
1065 ironlake_wait_panel_power_cycle(intel_dp); 1005 ironlake_wait_panel_power_cycle(intel_dp);
1066 1006
1067 pp = ironlake_get_pp_control(dev_priv); 1007 pp = ironlake_get_pp_control(intel_dp);
1068 pp |= EDP_FORCE_VDD; 1008 pp |= EDP_FORCE_VDD;
1069 I915_WRITE(PCH_PP_CONTROL, pp);
1070 POSTING_READ(PCH_PP_CONTROL);
1071 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1072 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1073 1009
1010 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1011 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1012
1013 I915_WRITE(pp_ctrl_reg, pp);
1014 POSTING_READ(pp_ctrl_reg);
1015 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1016 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1074 /* 1017 /*
1075 * If the panel wasn't on, delay before accessing aux channel 1018 * If the panel wasn't on, delay before accessing aux channel
1076 */ 1019 */
@@ -1085,19 +1028,23 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1085 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1086 struct drm_i915_private *dev_priv = dev->dev_private; 1029 struct drm_i915_private *dev_priv = dev->dev_private;
1087 u32 pp; 1030 u32 pp;
1031 u32 pp_stat_reg, pp_ctrl_reg;
1088 1032
1089 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1033 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1090 1034
1091 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1035 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1092 pp = ironlake_get_pp_control(dev_priv); 1036 pp = ironlake_get_pp_control(intel_dp);
1093 pp &= ~EDP_FORCE_VDD; 1037 pp &= ~EDP_FORCE_VDD;
1094 I915_WRITE(PCH_PP_CONTROL, pp);
1095 POSTING_READ(PCH_PP_CONTROL);
1096 1038
1097 /* Make sure sequencer is idle before allowing subsequent activity */ 1039 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1098 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1040 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1099 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1041
1042 I915_WRITE(pp_ctrl_reg, pp);
1043 POSTING_READ(pp_ctrl_reg);
1100 1044
1045 /* Make sure sequencer is idle before allowing subsequent activity */
1046 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1047 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1101 msleep(intel_dp->panel_power_down_delay); 1048 msleep(intel_dp->panel_power_down_delay);
1102 } 1049 }
1103} 1050}
@@ -1141,6 +1088,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1141 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1088 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1142 struct drm_i915_private *dev_priv = dev->dev_private; 1089 struct drm_i915_private *dev_priv = dev->dev_private;
1143 u32 pp; 1090 u32 pp;
1091 u32 pp_ctrl_reg;
1144 1092
1145 if (!is_edp(intel_dp)) 1093 if (!is_edp(intel_dp))
1146 return; 1094 return;
@@ -1154,7 +1102,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1154 1102
1155 ironlake_wait_panel_power_cycle(intel_dp); 1103 ironlake_wait_panel_power_cycle(intel_dp);
1156 1104
1157 pp = ironlake_get_pp_control(dev_priv); 1105 pp = ironlake_get_pp_control(intel_dp);
1158 if (IS_GEN5(dev)) { 1106 if (IS_GEN5(dev)) {
1159 /* ILK workaround: disable reset around power sequence */ 1107 /* ILK workaround: disable reset around power sequence */
1160 pp &= ~PANEL_POWER_RESET; 1108 pp &= ~PANEL_POWER_RESET;
@@ -1166,8 +1114,10 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1166 if (!IS_GEN5(dev)) 1114 if (!IS_GEN5(dev))
1167 pp |= PANEL_POWER_RESET; 1115 pp |= PANEL_POWER_RESET;
1168 1116
1169 I915_WRITE(PCH_PP_CONTROL, pp); 1117 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1170 POSTING_READ(PCH_PP_CONTROL); 1118
1119 I915_WRITE(pp_ctrl_reg, pp);
1120 POSTING_READ(pp_ctrl_reg);
1171 1121
1172 ironlake_wait_panel_on(intel_dp); 1122 ironlake_wait_panel_on(intel_dp);
1173 1123
@@ -1183,6 +1133,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1183 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1184 struct drm_i915_private *dev_priv = dev->dev_private; 1134 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 pp; 1135 u32 pp;
1136 u32 pp_ctrl_reg;
1186 1137
1187 if (!is_edp(intel_dp)) 1138 if (!is_edp(intel_dp))
1188 return; 1139 return;
@@ -1191,12 +1142,15 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1191 1142
1192 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1143 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1193 1144
1194 pp = ironlake_get_pp_control(dev_priv); 1145 pp = ironlake_get_pp_control(intel_dp);
1195 /* We need to switch off panel power _and_ force vdd, for otherwise some 1146 /* We need to switch off panel power _and_ force vdd, for otherwise some
1196 * panels get very unhappy and cease to work. */ 1147 * panels get very unhappy and cease to work. */
1197 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1148 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1198 I915_WRITE(PCH_PP_CONTROL, pp); 1149
1199 POSTING_READ(PCH_PP_CONTROL); 1150 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1151
1152 I915_WRITE(pp_ctrl_reg, pp);
1153 POSTING_READ(pp_ctrl_reg);
1200 1154
1201 intel_dp->want_panel_vdd = false; 1155 intel_dp->want_panel_vdd = false;
1202 1156
@@ -1210,6 +1164,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1210 struct drm_i915_private *dev_priv = dev->dev_private; 1164 struct drm_i915_private *dev_priv = dev->dev_private;
1211 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; 1165 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1212 u32 pp; 1166 u32 pp;
1167 u32 pp_ctrl_reg;
1213 1168
1214 if (!is_edp(intel_dp)) 1169 if (!is_edp(intel_dp))
1215 return; 1170 return;
@@ -1222,10 +1177,13 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1222 * allowing it to appear. 1177 * allowing it to appear.
1223 */ 1178 */
1224 msleep(intel_dp->backlight_on_delay); 1179 msleep(intel_dp->backlight_on_delay);
1225 pp = ironlake_get_pp_control(dev_priv); 1180 pp = ironlake_get_pp_control(intel_dp);
1226 pp |= EDP_BLC_ENABLE; 1181 pp |= EDP_BLC_ENABLE;
1227 I915_WRITE(PCH_PP_CONTROL, pp); 1182
1228 POSTING_READ(PCH_PP_CONTROL); 1183 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1184
1185 I915_WRITE(pp_ctrl_reg, pp);
1186 POSTING_READ(pp_ctrl_reg);
1229 1187
1230 intel_panel_enable_backlight(dev, pipe); 1188 intel_panel_enable_backlight(dev, pipe);
1231} 1189}
@@ -1235,6 +1193,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1235 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1193 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1236 struct drm_i915_private *dev_priv = dev->dev_private; 1194 struct drm_i915_private *dev_priv = dev->dev_private;
1237 u32 pp; 1195 u32 pp;
1196 u32 pp_ctrl_reg;
1238 1197
1239 if (!is_edp(intel_dp)) 1198 if (!is_edp(intel_dp))
1240 return; 1199 return;
@@ -1242,10 +1201,13 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1242 intel_panel_disable_backlight(dev); 1201 intel_panel_disable_backlight(dev);
1243 1202
1244 DRM_DEBUG_KMS("\n"); 1203 DRM_DEBUG_KMS("\n");
1245 pp = ironlake_get_pp_control(dev_priv); 1204 pp = ironlake_get_pp_control(intel_dp);
1246 pp &= ~EDP_BLC_ENABLE; 1205 pp &= ~EDP_BLC_ENABLE;
1247 I915_WRITE(PCH_PP_CONTROL, pp); 1206
1248 POSTING_READ(PCH_PP_CONTROL); 1207 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1208
1209 I915_WRITE(pp_ctrl_reg, pp);
1210 POSTING_READ(pp_ctrl_reg);
1249 msleep(intel_dp->backlight_off_delay); 1211 msleep(intel_dp->backlight_off_delay);
1250} 1212}
1251 1213
@@ -1398,10 +1360,12 @@ static void intel_disable_dp(struct intel_encoder *encoder)
1398static void intel_post_disable_dp(struct intel_encoder *encoder) 1360static void intel_post_disable_dp(struct intel_encoder *encoder)
1399{ 1361{
1400 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1363 struct drm_device *dev = encoder->base.dev;
1401 1364
1402 if (is_cpu_edp(intel_dp)) { 1365 if (is_cpu_edp(intel_dp)) {
1403 intel_dp_link_down(intel_dp); 1366 intel_dp_link_down(intel_dp);
1404 ironlake_edp_pll_off(intel_dp); 1367 if (!IS_VALLEYVIEW(dev))
1368 ironlake_edp_pll_off(intel_dp);
1405 } 1369 }
1406} 1370}
1407 1371
@@ -1427,8 +1391,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
1427static void intel_pre_enable_dp(struct intel_encoder *encoder) 1391static void intel_pre_enable_dp(struct intel_encoder *encoder)
1428{ 1392{
1429 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1394 struct drm_device *dev = encoder->base.dev;
1430 1395
1431 if (is_cpu_edp(intel_dp)) 1396 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1432 ironlake_edp_pll_on(intel_dp); 1397 ironlake_edp_pll_on(intel_dp);
1433} 1398}
1434 1399
@@ -2540,7 +2505,6 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2540} 2505}
2541 2506
2542static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 2507static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2543 .mode_fixup = intel_dp_mode_fixup,
2544 .mode_set = intel_dp_mode_set, 2508 .mode_set = intel_dp_mode_set,
2545}; 2509};
2546 2510
@@ -2636,15 +2600,28 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2636 struct drm_i915_private *dev_priv = dev->dev_private; 2600 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct edp_power_seq cur, vbt, spec, final; 2601 struct edp_power_seq cur, vbt, spec, final;
2638 u32 pp_on, pp_off, pp_div, pp; 2602 u32 pp_on, pp_off, pp_div, pp;
2603 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2604
2605 if (HAS_PCH_SPLIT(dev)) {
2606 pp_control_reg = PCH_PP_CONTROL;
2607 pp_on_reg = PCH_PP_ON_DELAYS;
2608 pp_off_reg = PCH_PP_OFF_DELAYS;
2609 pp_div_reg = PCH_PP_DIVISOR;
2610 } else {
2611 pp_control_reg = PIPEA_PP_CONTROL;
2612 pp_on_reg = PIPEA_PP_ON_DELAYS;
2613 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2614 pp_div_reg = PIPEA_PP_DIVISOR;
2615 }
2639 2616
2640 /* Workaround: Need to write PP_CONTROL with the unlock key as 2617 /* Workaround: Need to write PP_CONTROL with the unlock key as
2641 * the very first thing. */ 2618 * the very first thing. */
2642 pp = ironlake_get_pp_control(dev_priv); 2619 pp = ironlake_get_pp_control(intel_dp);
2643 I915_WRITE(PCH_PP_CONTROL, pp); 2620 I915_WRITE(pp_control_reg, pp);
2644 2621
2645 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2622 pp_on = I915_READ(pp_on_reg);
2646 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2623 pp_off = I915_READ(pp_off_reg);
2647 pp_div = I915_READ(PCH_PP_DIVISOR); 2624 pp_div = I915_READ(pp_div_reg);
2648 2625
2649 /* Pull timing values out of registers */ 2626 /* Pull timing values out of registers */
2650 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 2627 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
@@ -2719,7 +2696,22 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2719 struct edp_power_seq *seq) 2696 struct edp_power_seq *seq)
2720{ 2697{
2721 struct drm_i915_private *dev_priv = dev->dev_private; 2698 struct drm_i915_private *dev_priv = dev->dev_private;
2722 u32 pp_on, pp_off, pp_div; 2699 u32 pp_on, pp_off, pp_div, port_sel = 0;
2700 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2701 int pp_on_reg, pp_off_reg, pp_div_reg;
2702
2703 if (HAS_PCH_SPLIT(dev)) {
2704 pp_on_reg = PCH_PP_ON_DELAYS;
2705 pp_off_reg = PCH_PP_OFF_DELAYS;
2706 pp_div_reg = PCH_PP_DIVISOR;
2707 } else {
2708 pp_on_reg = PIPEA_PP_ON_DELAYS;
2709 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2710 pp_div_reg = PIPEA_PP_DIVISOR;
2711 }
2712
2713 if (IS_VALLEYVIEW(dev))
2714 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2723 2715
2724 /* And finally store the new values in the power sequencer. */ 2716 /* And finally store the new values in the power sequencer. */
2725 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 2717 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
@@ -2728,8 +2720,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2728 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 2720 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2729 /* Compute the divisor for the pp clock, simply match the Bspec 2721 /* Compute the divisor for the pp clock, simply match the Bspec
2730 * formula. */ 2722 * formula. */
2731 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) 2723 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2732 << PP_REFERENCE_DIVIDER_SHIFT;
2733 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 2724 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2734 << PANEL_POWER_CYCLE_DELAY_SHIFT); 2725 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2735 2726
@@ -2737,19 +2728,21 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2737 * power sequencer any more. */ 2728 * power sequencer any more. */
2738 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 2729 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2739 if (is_cpu_edp(intel_dp)) 2730 if (is_cpu_edp(intel_dp))
2740 pp_on |= PANEL_POWER_PORT_DP_A; 2731 port_sel = PANEL_POWER_PORT_DP_A;
2741 else 2732 else
2742 pp_on |= PANEL_POWER_PORT_DP_D; 2733 port_sel = PANEL_POWER_PORT_DP_D;
2743 } 2734 }
2744 2735
2745 I915_WRITE(PCH_PP_ON_DELAYS, pp_on); 2736 pp_on |= port_sel;
2746 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off); 2737
2747 I915_WRITE(PCH_PP_DIVISOR, pp_div); 2738 I915_WRITE(pp_on_reg, pp_on);
2739 I915_WRITE(pp_off_reg, pp_off);
2740 I915_WRITE(pp_div_reg, pp_div);
2748 2741
2749 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 2742 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2750 I915_READ(PCH_PP_ON_DELAYS), 2743 I915_READ(pp_on_reg),
2751 I915_READ(PCH_PP_OFF_DELAYS), 2744 I915_READ(pp_off_reg),
2752 I915_READ(PCH_PP_DIVISOR)); 2745 I915_READ(pp_div_reg));
2753} 2746}
2754 2747
2755void 2748void
@@ -2834,23 +2827,23 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2834 /* Set up the DDC bus. */ 2827 /* Set up the DDC bus. */
2835 switch (port) { 2828 switch (port) {
2836 case PORT_A: 2829 case PORT_A:
2830 intel_encoder->hpd_pin = HPD_PORT_A;
2837 name = "DPDDC-A"; 2831 name = "DPDDC-A";
2838 break; 2832 break;
2839 case PORT_B: 2833 case PORT_B:
2840 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; 2834 intel_encoder->hpd_pin = HPD_PORT_B;
2841 name = "DPDDC-B"; 2835 name = "DPDDC-B";
2842 break; 2836 break;
2843 case PORT_C: 2837 case PORT_C:
2844 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; 2838 intel_encoder->hpd_pin = HPD_PORT_C;
2845 name = "DPDDC-C"; 2839 name = "DPDDC-C";
2846 break; 2840 break;
2847 case PORT_D: 2841 case PORT_D:
2848 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; 2842 intel_encoder->hpd_pin = HPD_PORT_D;
2849 name = "DPDDC-D"; 2843 name = "DPDDC-D";
2850 break; 2844 break;
2851 default: 2845 default:
2852 WARN(1, "Invalid port %c\n", port_name(port)); 2846 BUG();
2853 break;
2854 } 2847 }
2855 2848
2856 if (is_edp(intel_dp)) 2849 if (is_edp(intel_dp))
@@ -2960,6 +2953,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2960 DRM_MODE_ENCODER_TMDS); 2953 DRM_MODE_ENCODER_TMDS);
2961 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 2954 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2962 2955
2956 intel_encoder->compute_config = intel_dp_compute_config;
2963 intel_encoder->enable = intel_enable_dp; 2957 intel_encoder->enable = intel_enable_dp;
2964 intel_encoder->pre_enable = intel_pre_enable_dp; 2958 intel_encoder->pre_enable = intel_pre_enable_dp;
2965 intel_encoder->disable = intel_disable_dp; 2959 intel_encoder->disable = intel_disable_dp;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e6f84d0db037..d7bd031dd642 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -33,12 +33,21 @@
33#include <drm/drm_fb_helper.h> 33#include <drm/drm_fb_helper.h>
34#include <drm/drm_dp_helper.h> 34#include <drm/drm_dp_helper.h>
35 35
36/**
37 * _wait_for - magic (register) wait macro
38 *
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
43 */
36#define _wait_for(COND, MS, W) ({ \ 44#define _wait_for(COND, MS, W) ({ \
37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
38 int ret__ = 0; \ 46 int ret__ = 0; \
39 while (!(COND)) { \ 47 while (!(COND)) { \
40 if (time_after(jiffies, timeout__)) { \ 48 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \ 49 if (!(COND)) \
50 ret__ = -ETIMEDOUT; \
42 break; \ 51 break; \
43 } \ 52 } \
44 if (W && drm_can_sleep()) { \ 53 if (W && drm_can_sleep()) { \
@@ -50,21 +59,10 @@
50 ret__; \ 59 ret__; \
51}) 60})
52 61
53#define wait_for_atomic_us(COND, US) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
64})
65
66#define wait_for(COND, MS) _wait_for(COND, MS, 1) 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64#define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
68 66
69#define KHz(x) (1000*x) 67#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x) 68#define MHz(x) KHz(1000*x)
@@ -101,34 +99,6 @@
101#define INTEL_DVO_CHIP_TMDS 2 99#define INTEL_DVO_CHIP_TMDS 2
102#define INTEL_DVO_CHIP_TVOUT 4 100#define INTEL_DVO_CHIP_TVOUT 4
103 101
104/* drm_display_mode->private_flags */
105#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
107#define INTEL_MODE_DP_FORCE_6BPC (0x10)
108/* This flag must be set by the encoder's mode_fixup if it changes the crtc
109 * timings in the mode to prevent the crtc fixup from overwriting them.
110 * Currently only lvds needs that. */
111#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
112/*
113 * Set when limited 16-235 (as opposed to full 0-255) RGB color range is
114 * to be used.
115 */
116#define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
117
118static inline void
119intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
120 int multiplier)
121{
122 mode->clock *= multiplier;
123 mode->private_flags |= multiplier;
124}
125
126static inline int
127intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
128{
129 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
130}
131
132struct intel_framebuffer { 102struct intel_framebuffer {
133 struct drm_framebuffer base; 103 struct drm_framebuffer base;
134 struct drm_i915_gem_object *obj; 104 struct drm_i915_gem_object *obj;
@@ -158,9 +128,12 @@ struct intel_encoder {
158 bool cloneable; 128 bool cloneable;
159 bool connectors_active; 129 bool connectors_active;
160 void (*hot_plug)(struct intel_encoder *); 130 void (*hot_plug)(struct intel_encoder *);
131 bool (*compute_config)(struct intel_encoder *,
132 struct intel_crtc_config *);
161 void (*pre_pll_enable)(struct intel_encoder *); 133 void (*pre_pll_enable)(struct intel_encoder *);
162 void (*pre_enable)(struct intel_encoder *); 134 void (*pre_enable)(struct intel_encoder *);
163 void (*enable)(struct intel_encoder *); 135 void (*enable)(struct intel_encoder *);
136 void (*mode_set)(struct intel_encoder *intel_encoder);
164 void (*disable)(struct intel_encoder *); 137 void (*disable)(struct intel_encoder *);
165 void (*post_disable)(struct intel_encoder *); 138 void (*post_disable)(struct intel_encoder *);
166 /* Read out the current hw state of this connector, returning true if 139 /* Read out the current hw state of this connector, returning true if
@@ -168,6 +141,7 @@ struct intel_encoder {
168 * it is connected to in the pipe parameter. */ 141 * it is connected to in the pipe parameter. */
169 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
170 int crtc_mask; 143 int crtc_mask;
144 enum hpd_pin hpd_pin;
171}; 145};
172 146
173struct intel_panel { 147struct intel_panel {
@@ -199,6 +173,51 @@ struct intel_connector {
199 struct edid *edid; 173 struct edid *edid;
200}; 174};
201 175
176struct intel_crtc_config {
177 struct drm_display_mode requested_mode;
178 struct drm_display_mode adjusted_mode;
179 /* This flag must be set by the encoder's compute_config callback if it
180 * changes the crtc timings in the mode to prevent the crtc fixup from
181 * overwriting them. Currently only lvds needs that. */
182 bool timings_set;
183 /* Whether to set up the PCH/FDI. Note that we never allow sharing
184 * between pch encoders and cpu encoders. */
185 bool has_pch_encoder;
186
187 /*
188 * Use reduced/limited/broadcast rbg range, compressing from the full
189 * range fed into the crtcs.
190 */
191 bool limited_color_range;
192
193 /* DP has a bunch of special case unfortunately, so mark the pipe
194 * accordingly. */
195 bool has_dp_encoder;
196 bool dither;
197
198 /* Controls for the clock computation, to override various stages. */
199 bool clock_set;
200
201 /* Settings for the intel dpll used on pretty much everything but
202 * haswell. */
203 struct dpll {
204 unsigned n;
205 unsigned m1, m2;
206 unsigned p1, p2;
207 } dpll;
208
209 int pipe_bpp;
210 struct intel_link_m_n dp_m_n;
211 /**
212 * This is currently used by DP and HDMI encoders since those can have a
213 * target pixel clock != the port link clock (which is currently stored
214 * in adjusted_mode->clock).
215 */
216 int pixel_target_clock;
217 /* Used by SDVO (and if we ever fix it, HDMI). */
218 unsigned pixel_multiplier;
219};
220
202struct intel_crtc { 221struct intel_crtc {
203 struct drm_crtc base; 222 struct drm_crtc base;
204 enum pipe pipe; 223 enum pipe pipe;
@@ -230,7 +249,8 @@ struct intel_crtc {
230 int16_t cursor_x, cursor_y; 249 int16_t cursor_x, cursor_y;
231 int16_t cursor_width, cursor_height; 250 int16_t cursor_width, cursor_height;
232 bool cursor_visible; 251 bool cursor_visible;
233 unsigned int bpp; 252
253 struct intel_crtc_config config;
234 254
235 /* We can share PLLs across outputs if the timings match */ 255 /* We can share PLLs across outputs if the timings match */
236 struct intel_pch_pll *pch_pll; 256 struct intel_pch_pll *pch_pll;
@@ -242,11 +262,16 @@ struct intel_crtc {
242 262
243struct intel_plane { 263struct intel_plane {
244 struct drm_plane base; 264 struct drm_plane base;
265 int plane;
245 enum pipe pipe; 266 enum pipe pipe;
246 struct drm_i915_gem_object *obj; 267 struct drm_i915_gem_object *obj;
247 bool can_scale; 268 bool can_scale;
248 int max_downscale; 269 int max_downscale;
249 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 270 u32 lut_r[1024], lut_g[1024], lut_b[1024];
271 int crtc_x, crtc_y;
272 unsigned int crtc_w, crtc_h;
273 uint32_t src_x, src_y;
274 uint32_t src_w, src_h;
250 void (*update_plane)(struct drm_plane *plane, 275 void (*update_plane)(struct drm_plane *plane,
251 struct drm_framebuffer *fb, 276 struct drm_framebuffer *fb,
252 struct drm_i915_gem_object *obj, 277 struct drm_i915_gem_object *obj,
@@ -448,9 +473,8 @@ extern void intel_hdmi_init(struct drm_device *dev,
448extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 473extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
449 struct intel_connector *intel_connector); 474 struct intel_connector *intel_connector);
450extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 475extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
451extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 476extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
452 const struct drm_display_mode *mode, 477 struct intel_crtc_config *pipe_config);
453 struct drm_display_mode *adjusted_mode);
454extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); 478extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
455extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, 479extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
456 bool is_sdvob); 480 bool is_sdvob);
@@ -465,18 +489,14 @@ extern void intel_dp_init(struct drm_device *dev, int output_reg,
465 enum port port); 489 enum port port);
466extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 490extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
467 struct intel_connector *intel_connector); 491 struct intel_connector *intel_connector);
468void
469intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
470 struct drm_display_mode *adjusted_mode);
471extern void intel_dp_init_link_config(struct intel_dp *intel_dp); 492extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
472extern void intel_dp_start_link_train(struct intel_dp *intel_dp); 493extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
473extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); 494extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
474extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 495extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
475extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); 496extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
476extern void intel_dp_check_link_status(struct intel_dp *intel_dp); 497extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
477extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, 498extern bool intel_dp_compute_config(struct intel_encoder *encoder,
478 const struct drm_display_mode *mode, 499 struct intel_crtc_config *pipe_config);
479 struct drm_display_mode *adjusted_mode);
480extern bool intel_dpd_is_edp(struct drm_device *dev); 500extern bool intel_dpd_is_edp(struct drm_device *dev);
481extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); 501extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
482extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); 502extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
@@ -484,11 +504,8 @@ extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
484extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); 504extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
485extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 505extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
486extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 506extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
487extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
488extern int intel_edp_target_clock(struct intel_encoder *,
489 struct drm_display_mode *mode);
490extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 507extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
491extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); 508extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
492extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, 509extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
493 enum plane plane); 510 enum plane plane);
494 511
@@ -532,6 +549,7 @@ extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
532extern void intel_connector_dpms(struct drm_connector *, int mode); 549extern void intel_connector_dpms(struct drm_connector *, int mode);
533extern bool intel_connector_get_hw_state(struct intel_connector *connector); 550extern bool intel_connector_get_hw_state(struct intel_connector *connector);
534extern void intel_modeset_check_state(struct drm_device *dev); 551extern void intel_modeset_check_state(struct drm_device *dev);
552extern void intel_plane_restore(struct drm_plane *plane);
535 553
536 554
537static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 555static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
@@ -637,6 +655,10 @@ extern void intel_init_clock_gating(struct drm_device *dev);
637extern void intel_write_eld(struct drm_encoder *encoder, 655extern void intel_write_eld(struct drm_encoder *encoder,
638 struct drm_display_mode *mode); 656 struct drm_display_mode *mode);
639extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); 657extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
658extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
659 struct intel_link_m_n *m_n);
660extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
661 struct intel_link_m_n *m_n);
640extern void intel_prepare_ddi(struct drm_device *dev); 662extern void intel_prepare_ddi(struct drm_device *dev);
641extern void hsw_fdi_link_train(struct drm_crtc *crtc); 663extern void hsw_fdi_link_train(struct drm_crtc *crtc);
642extern void intel_ddi_init(struct drm_device *dev, enum port port); 664extern void intel_ddi_init(struct drm_device *dev, enum port port);
@@ -682,7 +704,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
682 enum pipe *pipe); 704 enum pipe *pipe);
683extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 705extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
684extern void intel_ddi_pll_init(struct drm_device *dev); 706extern void intel_ddi_pll_init(struct drm_device *dev);
685extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); 707extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
686extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 708extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
687 enum transcoder cpu_transcoder); 709 enum transcoder cpu_transcoder);
688extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 710extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index f203418b6f05..8d81c929b7b5 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -150,6 +150,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
150 } 150 }
151 info->screen_size = size; 151 info->screen_size = size;
152 152
153 /* This driver doesn't need a VT switch to restore the mode on resume */
154 info->skip_vt_switch = true;
155
153 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); 156 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
154 drm_fb_helper_fill_var(info, &ifbdev->helper, sizes->fb_width, sizes->fb_height); 157 drm_fb_helper_fill_var(info, &ifbdev->helper, sizes->fb_width, sizes->fb_height);
155 158
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2474b1b6de61..ee4a8da8311e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -333,6 +333,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
333 struct drm_display_mode *adjusted_mode) 333 struct drm_display_mode *adjusted_mode)
334{ 334{
335 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 335 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
336 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
336 struct dip_infoframe avi_if = { 337 struct dip_infoframe avi_if = {
337 .type = DIP_TYPE_AVI, 338 .type = DIP_TYPE_AVI,
338 .ver = DIP_VERSION_AVI, 339 .ver = DIP_VERSION_AVI,
@@ -343,7 +344,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
343 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; 344 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
344 345
345 if (intel_hdmi->rgb_quant_range_selectable) { 346 if (intel_hdmi->rgb_quant_range_selectable) {
346 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 347 if (intel_crtc->config.limited_color_range)
347 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; 348 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
348 else 349 else
349 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; 350 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
@@ -601,14 +602,14 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
601 u32 hdmi_val; 602 u32 hdmi_val;
602 603
603 hdmi_val = SDVO_ENCODING_HDMI; 604 hdmi_val = SDVO_ENCODING_HDMI;
604 if (!HAS_PCH_SPLIT(dev)) 605 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
605 hdmi_val |= intel_hdmi->color_range; 606 hdmi_val |= intel_hdmi->color_range;
606 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 607 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
607 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 608 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
608 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 609 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
609 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 610 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
610 611
611 if (intel_crtc->bpp > 24) 612 if (intel_crtc->config.pipe_bpp > 24)
612 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 613 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
613 else 614 else
614 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 615 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
@@ -768,11 +769,12 @@ static int intel_hdmi_mode_valid(struct drm_connector *connector,
768 return MODE_OK; 769 return MODE_OK;
769} 770}
770 771
771bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 772bool intel_hdmi_compute_config(struct intel_encoder *encoder,
772 const struct drm_display_mode *mode, 773 struct intel_crtc_config *pipe_config)
773 struct drm_display_mode *adjusted_mode)
774{ 774{
775 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 775 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
776 struct drm_device *dev = encoder->base.dev;
777 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
776 778
777 if (intel_hdmi->color_range_auto) { 779 if (intel_hdmi->color_range_auto) {
778 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 780 /* See CEA-861-E - 5.1 Default Encoding Parameters */
@@ -784,7 +786,23 @@ bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
784 } 786 }
785 787
786 if (intel_hdmi->color_range) 788 if (intel_hdmi->color_range)
787 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; 789 pipe_config->limited_color_range = true;
790
791 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
792 pipe_config->has_pch_encoder = true;
793
794 /*
795 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
796 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
797 * outputs.
798 */
799 if (pipe_config->pipe_bpp > 8*3 && HAS_PCH_SPLIT(dev)) {
800 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
801 pipe_config->pipe_bpp = 12*3;
802 } else {
803 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
804 pipe_config->pipe_bpp = 8*3;
805 }
788 806
789 return true; 807 return true;
790} 808}
@@ -937,7 +955,6 @@ static void intel_hdmi_destroy(struct drm_connector *connector)
937} 955}
938 956
939static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 957static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
940 .mode_fixup = intel_hdmi_mode_fixup,
941 .mode_set = intel_hdmi_mode_set, 958 .mode_set = intel_hdmi_mode_set,
942}; 959};
943 960
@@ -988,17 +1005,18 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
988 switch (port) { 1005 switch (port) {
989 case PORT_B: 1006 case PORT_B:
990 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 1007 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
991 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; 1008 intel_encoder->hpd_pin = HPD_PORT_B;
992 break; 1009 break;
993 case PORT_C: 1010 case PORT_C:
994 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 1011 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
995 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; 1012 intel_encoder->hpd_pin = HPD_PORT_C;
996 break; 1013 break;
997 case PORT_D: 1014 case PORT_D:
998 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 1015 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
999 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; 1016 intel_encoder->hpd_pin = HPD_PORT_D;
1000 break; 1017 break;
1001 case PORT_A: 1018 case PORT_A:
1019 intel_encoder->hpd_pin = HPD_PORT_A;
1002 /* Internal port only for eDP. */ 1020 /* Internal port only for eDP. */
1003 default: 1021 default:
1004 BUG(); 1022 BUG();
@@ -1065,6 +1083,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1065 DRM_MODE_ENCODER_TMDS); 1083 DRM_MODE_ENCODER_TMDS);
1066 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 1084 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1067 1085
1086 intel_encoder->compute_config = intel_hdmi_compute_config;
1068 intel_encoder->enable = intel_enable_hdmi; 1087 intel_encoder->enable = intel_enable_hdmi;
1069 intel_encoder->disable = intel_disable_hdmi; 1088 intel_encoder->disable = intel_disable_hdmi;
1070 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1089 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 6ff145f97e90..ca2d903c19bb 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -261,8 +261,6 @@ centre_horizontally(struct drm_display_mode *mode,
261 261
262 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; 262 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
263 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; 263 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
264
265 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
266} 264}
267 265
268static void 266static void
@@ -284,8 +282,6 @@ centre_vertically(struct drm_display_mode *mode,
284 282
285 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; 283 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
286 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; 284 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
287
288 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
289} 285}
290 286
291static inline u32 panel_fitter_scaling(u32 source, u32 target) 287static inline u32 panel_fitter_scaling(u32 source, u32 target)
@@ -301,17 +297,20 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
301 return (FACTOR * ratio + FACTOR/2) / FACTOR; 297 return (FACTOR * ratio + FACTOR/2) / FACTOR;
302} 298}
303 299
304static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, 300static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
305 const struct drm_display_mode *mode, 301 struct intel_crtc_config *pipe_config)
306 struct drm_display_mode *adjusted_mode)
307{ 302{
308 struct drm_device *dev = encoder->dev; 303 struct drm_device *dev = intel_encoder->base.dev;
309 struct drm_i915_private *dev_priv = dev->dev_private; 304 struct drm_i915_private *dev_priv = dev->dev_private;
310 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 305 struct intel_lvds_encoder *lvds_encoder =
306 to_lvds_encoder(&intel_encoder->base);
311 struct intel_connector *intel_connector = 307 struct intel_connector *intel_connector =
312 &lvds_encoder->attached_connector->base; 308 &lvds_encoder->attached_connector->base;
309 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
310 struct drm_display_mode *mode = &pipe_config->requested_mode;
313 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; 311 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
314 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 312 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
313 unsigned int lvds_bpp;
315 int pipe; 314 int pipe;
316 315
317 /* Should never happen!! */ 316 /* Should never happen!! */
@@ -323,6 +322,17 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
323 if (intel_encoder_check_is_cloned(&lvds_encoder->base)) 322 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
324 return false; 323 return false;
325 324
325 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
326 LVDS_A3_POWER_UP)
327 lvds_bpp = 8*3;
328 else
329 lvds_bpp = 6*3;
330
331 if (lvds_bpp != pipe_config->pipe_bpp) {
332 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
333 pipe_config->pipe_bpp, lvds_bpp);
334 pipe_config->pipe_bpp = lvds_bpp;
335 }
326 /* 336 /*
327 * We have timings from the BIOS for the panel, put them in 337 * We have timings from the BIOS for the panel, put them in
328 * to the adjusted mode. The CRTC will be set up for this mode, 338 * to the adjusted mode. The CRTC will be set up for this mode,
@@ -333,6 +343,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
333 adjusted_mode); 343 adjusted_mode);
334 344
335 if (HAS_PCH_SPLIT(dev)) { 345 if (HAS_PCH_SPLIT(dev)) {
346 pipe_config->has_pch_encoder = true;
347
336 intel_pch_panel_fitting(dev, 348 intel_pch_panel_fitting(dev,
337 intel_connector->panel.fitting_mode, 349 intel_connector->panel.fitting_mode,
338 mode, adjusted_mode); 350 mode, adjusted_mode);
@@ -359,6 +371,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
359 I915_WRITE(BCLRPAT(pipe), 0); 371 I915_WRITE(BCLRPAT(pipe), 0);
360 372
361 drm_mode_set_crtcinfo(adjusted_mode, 0); 373 drm_mode_set_crtcinfo(adjusted_mode, 0);
374 pipe_config->timings_set = true;
362 375
363 switch (intel_connector->panel.fitting_mode) { 376 switch (intel_connector->panel.fitting_mode) {
364 case DRM_MODE_SCALE_CENTER: 377 case DRM_MODE_SCALE_CENTER:
@@ -661,7 +674,6 @@ static int intel_lvds_set_property(struct drm_connector *connector,
661} 674}
662 675
663static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { 676static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
664 .mode_fixup = intel_lvds_mode_fixup,
665 .mode_set = intel_lvds_mode_set, 677 .mode_set = intel_lvds_mode_set,
666}; 678};
667 679
@@ -850,6 +862,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
850 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 862 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
851 }, 863 },
852 }, 864 },
865 {
866 .callback = intel_no_lvds_dmi_callback,
867 .ident = "Fujitsu Esprimo Q900",
868 .matches = {
869 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
870 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
871 },
872 },
853 873
854 { } /* terminating entry */ 874 { } /* terminating entry */
855}; 875};
@@ -1105,6 +1125,7 @@ bool intel_lvds_init(struct drm_device *dev)
1105 intel_encoder->enable = intel_enable_lvds; 1125 intel_encoder->enable = intel_enable_lvds;
1106 intel_encoder->pre_enable = intel_pre_enable_lvds; 1126 intel_encoder->pre_enable = intel_pre_enable_lvds;
1107 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; 1127 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
1128 intel_encoder->compute_config = intel_lvds_compute_config;
1108 intel_encoder->disable = intel_disable_lvds; 1129 intel_encoder->disable = intel_disable_lvds;
1109 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1130 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1110 intel_connector->get_hw_state = intel_connector_get_hw_state; 1131 intel_connector->get_hw_state = intel_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 888fe29537b9..7874cecc2863 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -286,8 +286,11 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level)
286{ 286{
287 struct drm_i915_private *dev_priv = dev->dev_private; 287 struct drm_i915_private *dev_priv = dev->dev_private;
288 288
289 dev_priv->backlight_level = level; 289 dev_priv->backlight.level = level;
290 if (dev_priv->backlight_enabled) 290 if (dev_priv->backlight.device)
291 dev_priv->backlight.device->props.brightness = level;
292
293 if (dev_priv->backlight.enabled)
291 intel_panel_actually_set_backlight(dev, level); 294 intel_panel_actually_set_backlight(dev, level);
292} 295}
293 296
@@ -295,7 +298,7 @@ void intel_panel_disable_backlight(struct drm_device *dev)
295{ 298{
296 struct drm_i915_private *dev_priv = dev->dev_private; 299 struct drm_i915_private *dev_priv = dev->dev_private;
297 300
298 dev_priv->backlight_enabled = false; 301 dev_priv->backlight.enabled = false;
299 intel_panel_actually_set_backlight(dev, 0); 302 intel_panel_actually_set_backlight(dev, 0);
300 303
301 if (INTEL_INFO(dev)->gen >= 4) { 304 if (INTEL_INFO(dev)->gen >= 4) {
@@ -318,8 +321,12 @@ void intel_panel_enable_backlight(struct drm_device *dev,
318{ 321{
319 struct drm_i915_private *dev_priv = dev->dev_private; 322 struct drm_i915_private *dev_priv = dev->dev_private;
320 323
321 if (dev_priv->backlight_level == 0) 324 if (dev_priv->backlight.level == 0) {
322 dev_priv->backlight_level = intel_panel_get_max_backlight(dev); 325 dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
326 if (dev_priv->backlight.device)
327 dev_priv->backlight.device->props.brightness =
328 dev_priv->backlight.level;
329 }
323 330
324 if (INTEL_INFO(dev)->gen >= 4) { 331 if (INTEL_INFO(dev)->gen >= 4) {
325 uint32_t reg, tmp; 332 uint32_t reg, tmp;
@@ -360,16 +367,16 @@ set_level:
360 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these 367 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
361 * registers are set. 368 * registers are set.
362 */ 369 */
363 dev_priv->backlight_enabled = true; 370 dev_priv->backlight.enabled = true;
364 intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); 371 intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
365} 372}
366 373
367static void intel_panel_init_backlight(struct drm_device *dev) 374static void intel_panel_init_backlight(struct drm_device *dev)
368{ 375{
369 struct drm_i915_private *dev_priv = dev->dev_private; 376 struct drm_i915_private *dev_priv = dev->dev_private;
370 377
371 dev_priv->backlight_level = intel_panel_get_backlight(dev); 378 dev_priv->backlight.level = intel_panel_get_backlight(dev);
372 dev_priv->backlight_enabled = dev_priv->backlight_level != 0; 379 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
373} 380}
374 381
375enum drm_connector_status 382enum drm_connector_status
@@ -405,8 +412,7 @@ static int intel_panel_update_status(struct backlight_device *bd)
405static int intel_panel_get_brightness(struct backlight_device *bd) 412static int intel_panel_get_brightness(struct backlight_device *bd)
406{ 413{
407 struct drm_device *dev = bl_get_data(bd); 414 struct drm_device *dev = bl_get_data(bd);
408 struct drm_i915_private *dev_priv = dev->dev_private; 415 return intel_panel_get_backlight(dev);
409 return dev_priv->backlight_level;
410} 416}
411 417
412static const struct backlight_ops intel_panel_bl_ops = { 418static const struct backlight_ops intel_panel_bl_ops = {
@@ -424,31 +430,31 @@ int intel_panel_setup_backlight(struct drm_connector *connector)
424 430
425 memset(&props, 0, sizeof(props)); 431 memset(&props, 0, sizeof(props));
426 props.type = BACKLIGHT_RAW; 432 props.type = BACKLIGHT_RAW;
433 props.brightness = dev_priv->backlight.level;
427 props.max_brightness = _intel_panel_get_max_backlight(dev); 434 props.max_brightness = _intel_panel_get_max_backlight(dev);
428 if (props.max_brightness == 0) { 435 if (props.max_brightness == 0) {
429 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n"); 436 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
430 return -ENODEV; 437 return -ENODEV;
431 } 438 }
432 dev_priv->backlight = 439 dev_priv->backlight.device =
433 backlight_device_register("intel_backlight", 440 backlight_device_register("intel_backlight",
434 &connector->kdev, dev, 441 &connector->kdev, dev,
435 &intel_panel_bl_ops, &props); 442 &intel_panel_bl_ops, &props);
436 443
437 if (IS_ERR(dev_priv->backlight)) { 444 if (IS_ERR(dev_priv->backlight.device)) {
438 DRM_ERROR("Failed to register backlight: %ld\n", 445 DRM_ERROR("Failed to register backlight: %ld\n",
439 PTR_ERR(dev_priv->backlight)); 446 PTR_ERR(dev_priv->backlight.device));
440 dev_priv->backlight = NULL; 447 dev_priv->backlight.device = NULL;
441 return -ENODEV; 448 return -ENODEV;
442 } 449 }
443 dev_priv->backlight->props.brightness = intel_panel_get_backlight(dev);
444 return 0; 450 return 0;
445} 451}
446 452
447void intel_panel_destroy_backlight(struct drm_device *dev) 453void intel_panel_destroy_backlight(struct drm_device *dev)
448{ 454{
449 struct drm_i915_private *dev_priv = dev->dev_private; 455 struct drm_i915_private *dev_priv = dev->dev_private;
450 if (dev_priv->backlight) 456 if (dev_priv->backlight.device)
451 backlight_device_unregister(dev_priv->backlight); 457 backlight_device_unregister(dev_priv->backlight.device);
452} 458}
453#else 459#else
454int intel_panel_setup_backlight(struct drm_connector *connector) 460int intel_panel_setup_backlight(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2de6da683de2..13a0666a53b4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2460,10 +2460,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
2460 if (val == dev_priv->rps.cur_delay) 2460 if (val == dev_priv->rps.cur_delay)
2461 return; 2461 return;
2462 2462
2463 I915_WRITE(GEN6_RPNSWREQ, 2463 if (IS_HASWELL(dev))
2464 GEN6_FREQUENCY(val) | 2464 I915_WRITE(GEN6_RPNSWREQ,
2465 GEN6_OFFSET(0) | 2465 HSW_FREQUENCY(val));
2466 GEN6_AGGRESSIVE_TURBO); 2466 else
2467 I915_WRITE(GEN6_RPNSWREQ,
2468 GEN6_FREQUENCY(val) |
2469 GEN6_OFFSET(0) |
2470 GEN6_AGGRESSIVE_TURBO);
2467 2471
2468 /* Make sure we continue to get interrupts 2472 /* Make sure we continue to get interrupts
2469 * until we hit the minimum or maximum frequencies. 2473 * until we hit the minimum or maximum frequencies.
@@ -2601,12 +2605,19 @@ static void gen6_enable_rps(struct drm_device *dev)
2601 GEN6_RC_CTL_EI_MODE(1) | 2605 GEN6_RC_CTL_EI_MODE(1) |
2602 GEN6_RC_CTL_HW_ENABLE); 2606 GEN6_RC_CTL_HW_ENABLE);
2603 2607
2604 I915_WRITE(GEN6_RPNSWREQ, 2608 if (IS_HASWELL(dev)) {
2605 GEN6_FREQUENCY(10) | 2609 I915_WRITE(GEN6_RPNSWREQ,
2606 GEN6_OFFSET(0) | 2610 HSW_FREQUENCY(10));
2607 GEN6_AGGRESSIVE_TURBO); 2611 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2608 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2612 HSW_FREQUENCY(12));
2609 GEN6_FREQUENCY(12)); 2613 } else {
2614 I915_WRITE(GEN6_RPNSWREQ,
2615 GEN6_FREQUENCY(10) |
2616 GEN6_OFFSET(0) |
2617 GEN6_AGGRESSIVE_TURBO);
2618 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2619 GEN6_FREQUENCY(12));
2620 }
2610 2621
2611 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 2622 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2612 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 2623 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
@@ -2628,7 +2639,7 @@ static void gen6_enable_rps(struct drm_device *dev)
2628 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); 2639 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2629 2640
2630 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 2641 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2631 if (!ret) { 2642 if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
2632 pcu_mbox = 0; 2643 pcu_mbox = 0;
2633 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 2644 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2634 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 2645 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
@@ -3975,19 +3986,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
3975 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3986 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3976 3987
3977 /* 3988 /*
3978 * On ValleyView, the GUnit needs to signal the GT
3979 * when flip and other events complete. So enable
3980 * all the GUnit->GT interrupts here
3981 */
3982 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3983 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3984 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3985 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3986 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3987 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3988 PLANEA_FLIPDONE_INT_EN);
3989
3990 /*
3991 * WaDisableVLVClockGating_VBIIssue 3989 * WaDisableVLVClockGating_VBIIssue
3992 * Disable clock gating on th GCFG unit to prevent a delay 3990 * Disable clock gating on th GCFG unit to prevent a delay
3993 * in the reporting of vblank events. 3991 * in the reporting of vblank events.
@@ -4528,3 +4526,56 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4528 4526
4529 return 0; 4527 return 0;
4530} 4528}
4529
4530static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
4531 u8 addr, u32 *val)
4532{
4533 u32 cmd, devfn, port, be, bar;
4534
4535 bar = 0;
4536 be = 0xf;
4537 port = IOSF_PORT_PUNIT;
4538 devfn = PCI_DEVFN(2, 0);
4539
4540 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4541 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4542 (bar << IOSF_BAR_SHIFT);
4543
4544 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4545
4546 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4547 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4548 opcode == PUNIT_OPCODE_REG_READ ?
4549 "read" : "write");
4550 return -EAGAIN;
4551 }
4552
4553 I915_WRITE(VLV_IOSF_ADDR, addr);
4554 if (opcode == PUNIT_OPCODE_REG_WRITE)
4555 I915_WRITE(VLV_IOSF_DATA, *val);
4556 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4557
4558 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4559 500)) {
4560 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4561 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4562 addr);
4563 return -ETIMEDOUT;
4564 }
4565
4566 if (opcode == PUNIT_OPCODE_REG_READ)
4567 *val = I915_READ(VLV_IOSF_DATA);
4568 I915_WRITE(VLV_IOSF_DATA, 0);
4569
4570 return 0;
4571}
4572
4573int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4574{
4575 return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val);
4576}
4577
4578int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4579{
4580 return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val);
4581}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 678c47cac72b..298dc85ec32c 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -788,7 +788,6 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
788 v_sync_offset = mode->vsync_start - mode->vdisplay; 788 v_sync_offset = mode->vsync_start - mode->vdisplay;
789 789
790 mode_clock = mode->clock; 790 mode_clock = mode->clock;
791 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
792 mode_clock /= 10; 791 mode_clock /= 10;
793 dtd->part1.clock = mode_clock; 792 dtd->part1.clock = mode_clock;
794 793
@@ -957,9 +956,10 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
957 .len = DIP_LEN_AVI, 956 .len = DIP_LEN_AVI,
958 }; 957 };
959 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; 958 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
959 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
960 960
961 if (intel_sdvo->rgb_quant_range_selectable) { 961 if (intel_sdvo->rgb_quant_range_selectable) {
962 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 962 if (intel_crtc->config.limited_color_range)
963 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; 963 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
964 else 964 else
965 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; 965 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
@@ -1041,12 +1041,18 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1041 return true; 1041 return true;
1042} 1042}
1043 1043
1044static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, 1044static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1045 const struct drm_display_mode *mode, 1045 struct intel_crtc_config *pipe_config)
1046 struct drm_display_mode *adjusted_mode)
1047{ 1046{
1048 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); 1047 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1049 int multiplier; 1048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1049 struct drm_display_mode *mode = &pipe_config->requested_mode;
1050
1051 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1052 pipe_config->pipe_bpp = 8*3;
1053
1054 if (HAS_PCH_SPLIT(encoder->base.dev))
1055 pipe_config->has_pch_encoder = true;
1050 1056
1051 /* We need to construct preferred input timings based on our 1057 /* We need to construct preferred input timings based on our
1052 * output timings. To do that, we have to set the output 1058 * output timings. To do that, we have to set the output
@@ -1073,8 +1079,9 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1073 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1074 * SDVO device will factor out the multiplier during mode_set. 1080 * SDVO device will factor out the multiplier during mode_set.
1075 */ 1081 */
1076 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); 1082 pipe_config->pixel_multiplier =
1077 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); 1083 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1084 adjusted_mode->clock *= pipe_config->pixel_multiplier;
1078 1085
1079 if (intel_sdvo->color_range_auto) { 1086 if (intel_sdvo->color_range_auto) {
1080 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1087 /* See CEA-861-E - 5.1 Default Encoding Parameters */
@@ -1088,24 +1095,24 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1088 } 1095 }
1089 1096
1090 if (intel_sdvo->color_range) 1097 if (intel_sdvo->color_range)
1091 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; 1098 pipe_config->limited_color_range = true;
1092 1099
1093 return true; 1100 return true;
1094} 1101}
1095 1102
1096static void intel_sdvo_mode_set(struct drm_encoder *encoder, 1103static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
1097 struct drm_display_mode *mode,
1098 struct drm_display_mode *adjusted_mode)
1099{ 1104{
1100 struct drm_device *dev = encoder->dev; 1105 struct drm_device *dev = intel_encoder->base.dev;
1101 struct drm_i915_private *dev_priv = dev->dev_private; 1106 struct drm_i915_private *dev_priv = dev->dev_private;
1102 struct drm_crtc *crtc = encoder->crtc; 1107 struct drm_crtc *crtc = intel_encoder->base.crtc;
1103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1104 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); 1109 struct drm_display_mode *adjusted_mode =
1110 &intel_crtc->config.adjusted_mode;
1111 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1112 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
1105 u32 sdvox; 1113 u32 sdvox;
1106 struct intel_sdvo_in_out_map in_out; 1114 struct intel_sdvo_in_out_map in_out;
1107 struct intel_sdvo_dtd input_dtd, output_dtd; 1115 struct intel_sdvo_dtd input_dtd, output_dtd;
1108 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1109 int rate; 1116 int rate;
1110 1117
1111 if (!mode) 1118 if (!mode)
@@ -1165,7 +1172,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1165 DRM_INFO("Setting input timings on %s failed\n", 1172 DRM_INFO("Setting input timings on %s failed\n",
1166 SDVO_NAME(intel_sdvo)); 1173 SDVO_NAME(intel_sdvo));
1167 1174
1168 switch (pixel_multiplier) { 1175 switch (intel_crtc->config.pixel_multiplier) {
1169 default: 1176 default:
1170 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1177 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1171 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1178 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
@@ -1209,7 +1216,8 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1209 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1216 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1210 /* done in crtc_mode_set as it lives inside the dpll register */ 1217 /* done in crtc_mode_set as it lives inside the dpll register */
1211 } else { 1218 } else {
1212 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; 1219 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1220 << SDVO_PORT_MULTIPLY_SHIFT;
1213 } 1221 }
1214 1222
1215 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1223 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
@@ -1223,8 +1231,12 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1223 struct intel_sdvo_connector *intel_sdvo_connector = 1231 struct intel_sdvo_connector *intel_sdvo_connector =
1224 to_intel_sdvo_connector(&connector->base); 1232 to_intel_sdvo_connector(&connector->base);
1225 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1233 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1234 struct drm_i915_private *dev_priv = intel_sdvo->base.base.dev->dev_private;
1226 u16 active_outputs; 1235 u16 active_outputs;
1227 1236
1237 if (!(I915_READ(intel_sdvo->sdvo_reg) & SDVO_ENABLE))
1238 return false;
1239
1228 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1240 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1229 1241
1230 if (active_outputs & intel_sdvo_connector->output_flag) 1242 if (active_outputs & intel_sdvo_connector->output_flag)
@@ -2040,11 +2052,6 @@ done:
2040#undef CHECK_PROPERTY 2052#undef CHECK_PROPERTY
2041} 2053}
2042 2054
2043static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2044 .mode_fixup = intel_sdvo_mode_fixup,
2045 .mode_set = intel_sdvo_mode_set,
2046};
2047
2048static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2055static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2049 .dpms = intel_sdvo_dpms, 2056 .dpms = intel_sdvo_dpms,
2050 .detect = intel_sdvo_detect, 2057 .detect = intel_sdvo_detect,
@@ -2779,9 +2786,15 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2779 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; 2786 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2780 } 2787 }
2781 2788
2782 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); 2789 /* Only enable the hotplug irq if we need it, to work around noisy
2790 * hotplug lines.
2791 */
2792 if (intel_sdvo->hotplug_active)
2793 intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
2783 2794
2795 intel_encoder->compute_config = intel_sdvo_compute_config;
2784 intel_encoder->disable = intel_disable_sdvo; 2796 intel_encoder->disable = intel_disable_sdvo;
2797 intel_encoder->mode_set = intel_sdvo_mode_set;
2785 intel_encoder->enable = intel_enable_sdvo; 2798 intel_encoder->enable = intel_enable_sdvo;
2786 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 2799 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
2787 2800
@@ -2807,12 +2820,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2807 */ 2820 */
2808 intel_sdvo->base.cloneable = false; 2821 intel_sdvo->base.cloneable = false;
2809 2822
2810 /* Only enable the hotplug irq if we need it, to work around noisy
2811 * hotplug lines.
2812 */
2813 if (intel_sdvo->hotplug_active)
2814 dev_priv->hotplug_supported_mask |= hotplug_mask;
2815
2816 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 2823 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2817 2824
2818 /* Set the input timing to the screen. Assume always input 0. */ 2825 /* Set the input timing to the screen. Assume always input 0. */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1b6eb76beb7c..c7d25c5dd4e6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -37,6 +37,174 @@
37#include "i915_drv.h" 37#include "i915_drv.h"
38 38
39static void 39static void
40vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
41 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
42 unsigned int crtc_w, unsigned int crtc_h,
43 uint32_t x, uint32_t y,
44 uint32_t src_w, uint32_t src_h)
45{
46 struct drm_device *dev = dplane->dev;
47 struct drm_i915_private *dev_priv = dev->dev_private;
48 struct intel_plane *intel_plane = to_intel_plane(dplane);
49 int pipe = intel_plane->pipe;
50 int plane = intel_plane->plane;
51 u32 sprctl;
52 unsigned long sprsurf_offset, linear_offset;
53 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
54
55 sprctl = I915_READ(SPCNTR(pipe, plane));
56
57 /* Mask out pixel format bits in case we change it */
58 sprctl &= ~SP_PIXFORMAT_MASK;
59 sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
60 sprctl &= ~SP_TILED;
61
62 switch (fb->pixel_format) {
63 case DRM_FORMAT_YUYV:
64 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
65 break;
66 case DRM_FORMAT_YVYU:
67 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
68 break;
69 case DRM_FORMAT_UYVY:
70 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
71 break;
72 case DRM_FORMAT_VYUY:
73 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
74 break;
75 case DRM_FORMAT_RGB565:
76 sprctl |= SP_FORMAT_BGR565;
77 break;
78 case DRM_FORMAT_XRGB8888:
79 sprctl |= SP_FORMAT_BGRX8888;
80 break;
81 case DRM_FORMAT_ARGB8888:
82 sprctl |= SP_FORMAT_BGRA8888;
83 break;
84 case DRM_FORMAT_XBGR2101010:
85 sprctl |= SP_FORMAT_RGBX1010102;
86 break;
87 case DRM_FORMAT_ABGR2101010:
88 sprctl |= SP_FORMAT_RGBA1010102;
89 break;
90 case DRM_FORMAT_XBGR8888:
91 sprctl |= SP_FORMAT_RGBX8888;
92 break;
93 case DRM_FORMAT_ABGR8888:
94 sprctl |= SP_FORMAT_RGBA8888;
95 break;
96 default:
97 /*
98 * If we get here one of the upper layers failed to filter
99 * out the unsupported plane formats
100 */
101 BUG();
102 break;
103 }
104
105 if (obj->tiling_mode != I915_TILING_NONE)
106 sprctl |= SP_TILED;
107
108 sprctl |= SP_ENABLE;
109
110 /* Sizes are 0 based */
111 src_w--;
112 src_h--;
113 crtc_w--;
114 crtc_h--;
115
116 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
117
118 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
119 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
120
121 linear_offset = y * fb->pitches[0] + x * pixel_size;
122 sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
123 obj->tiling_mode,
124 pixel_size,
125 fb->pitches[0]);
126 linear_offset -= sprsurf_offset;
127
128 if (obj->tiling_mode != I915_TILING_NONE)
129 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
130 else
131 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
132
133 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
134 I915_WRITE(SPCNTR(pipe, plane), sprctl);
135 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
136 sprsurf_offset);
137 POSTING_READ(SPSURF(pipe, plane));
138}
139
140static void
141vlv_disable_plane(struct drm_plane *dplane)
142{
143 struct drm_device *dev = dplane->dev;
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 struct intel_plane *intel_plane = to_intel_plane(dplane);
146 int pipe = intel_plane->pipe;
147 int plane = intel_plane->plane;
148
149 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
150 ~SP_ENABLE);
151 /* Activate double buffered register update */
152 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
153 POSTING_READ(SPSURF(pipe, plane));
154}
155
156static int
157vlv_update_colorkey(struct drm_plane *dplane,
158 struct drm_intel_sprite_colorkey *key)
159{
160 struct drm_device *dev = dplane->dev;
161 struct drm_i915_private *dev_priv = dev->dev_private;
162 struct intel_plane *intel_plane = to_intel_plane(dplane);
163 int pipe = intel_plane->pipe;
164 int plane = intel_plane->plane;
165 u32 sprctl;
166
167 if (key->flags & I915_SET_COLORKEY_DESTINATION)
168 return -EINVAL;
169
170 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
171 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
172 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
173
174 sprctl = I915_READ(SPCNTR(pipe, plane));
175 sprctl &= ~SP_SOURCE_KEY;
176 if (key->flags & I915_SET_COLORKEY_SOURCE)
177 sprctl |= SP_SOURCE_KEY;
178 I915_WRITE(SPCNTR(pipe, plane), sprctl);
179
180 POSTING_READ(SPKEYMSK(pipe, plane));
181
182 return 0;
183}
184
185static void
186vlv_get_colorkey(struct drm_plane *dplane,
187 struct drm_intel_sprite_colorkey *key)
188{
189 struct drm_device *dev = dplane->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct intel_plane *intel_plane = to_intel_plane(dplane);
192 int pipe = intel_plane->pipe;
193 int plane = intel_plane->plane;
194 u32 sprctl;
195
196 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
197 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
198 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
199
200 sprctl = I915_READ(SPCNTR(pipe, plane));
201 if (sprctl & SP_SOURCE_KEY)
202 key->flags = I915_SET_COLORKEY_SOURCE;
203 else
204 key->flags = I915_SET_COLORKEY_NONE;
205}
206
207static void
40ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 208ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
41 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, 209 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
42 unsigned int crtc_w, unsigned int crtc_h, 210 unsigned int crtc_w, unsigned int crtc_h,
@@ -441,6 +609,15 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
441 609
442 old_obj = intel_plane->obj; 610 old_obj = intel_plane->obj;
443 611
612 intel_plane->crtc_x = crtc_x;
613 intel_plane->crtc_y = crtc_y;
614 intel_plane->crtc_w = crtc_w;
615 intel_plane->crtc_h = crtc_h;
616 intel_plane->src_x = src_x;
617 intel_plane->src_y = src_y;
618 intel_plane->src_w = src_w;
619 intel_plane->src_h = src_h;
620
444 src_w = src_w >> 16; 621 src_w = src_w >> 16;
445 src_h = src_h >> 16; 622 src_h = src_h >> 16;
446 623
@@ -513,6 +690,11 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
513 690
514 mutex_lock(&dev->struct_mutex); 691 mutex_lock(&dev->struct_mutex);
515 692
693 /* Note that this will apply the VT-d workaround for scanouts,
694 * which is more restrictive than required for sprites. (The
695 * primary plane requires 256KiB alignment with 64 PTE padding,
696 * the sprite planes only require 128KiB alignment and 32 PTE padding.
697 */
516 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); 698 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
517 if (ret) 699 if (ret)
518 goto out_unlock; 700 goto out_unlock;
@@ -568,6 +750,8 @@ intel_disable_plane(struct drm_plane *plane)
568 if (!intel_plane->obj) 750 if (!intel_plane->obj)
569 goto out; 751 goto out;
570 752
753 intel_wait_for_vblank(dev, intel_plane->pipe);
754
571 mutex_lock(&dev->struct_mutex); 755 mutex_lock(&dev->struct_mutex);
572 intel_unpin_fb_obj(intel_plane->obj); 756 intel_unpin_fb_obj(intel_plane->obj);
573 intel_plane->obj = NULL; 757 intel_plane->obj = NULL;
@@ -647,6 +831,20 @@ out_unlock:
647 return ret; 831 return ret;
648} 832}
649 833
834void intel_plane_restore(struct drm_plane *plane)
835{
836 struct intel_plane *intel_plane = to_intel_plane(plane);
837
838 if (!plane->crtc || !plane->fb)
839 return;
840
841 intel_update_plane(plane, plane->crtc, plane->fb,
842 intel_plane->crtc_x, intel_plane->crtc_y,
843 intel_plane->crtc_w, intel_plane->crtc_h,
844 intel_plane->src_x, intel_plane->src_y,
845 intel_plane->src_w, intel_plane->src_h);
846}
847
650static const struct drm_plane_funcs intel_plane_funcs = { 848static const struct drm_plane_funcs intel_plane_funcs = {
651 .update_plane = intel_update_plane, 849 .update_plane = intel_update_plane,
652 .disable_plane = intel_disable_plane, 850 .disable_plane = intel_disable_plane,
@@ -670,8 +868,22 @@ static uint32_t snb_plane_formats[] = {
670 DRM_FORMAT_VYUY, 868 DRM_FORMAT_VYUY,
671}; 869};
672 870
871static uint32_t vlv_plane_formats[] = {
872 DRM_FORMAT_RGB565,
873 DRM_FORMAT_ABGR8888,
874 DRM_FORMAT_ARGB8888,
875 DRM_FORMAT_XBGR8888,
876 DRM_FORMAT_XRGB8888,
877 DRM_FORMAT_XBGR2101010,
878 DRM_FORMAT_ABGR2101010,
879 DRM_FORMAT_YUYV,
880 DRM_FORMAT_YVYU,
881 DRM_FORMAT_UYVY,
882 DRM_FORMAT_VYUY,
883};
884
673int 885int
674intel_plane_init(struct drm_device *dev, enum pipe pipe) 886intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
675{ 887{
676 struct intel_plane *intel_plane; 888 struct intel_plane *intel_plane;
677 unsigned long possible_crtcs; 889 unsigned long possible_crtcs;
@@ -710,14 +922,26 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
710 intel_plane->can_scale = false; 922 intel_plane->can_scale = false;
711 else 923 else
712 intel_plane->can_scale = true; 924 intel_plane->can_scale = true;
713 intel_plane->max_downscale = 2; 925
714 intel_plane->update_plane = ivb_update_plane; 926 if (IS_VALLEYVIEW(dev)) {
715 intel_plane->disable_plane = ivb_disable_plane; 927 intel_plane->max_downscale = 1;
716 intel_plane->update_colorkey = ivb_update_colorkey; 928 intel_plane->update_plane = vlv_update_plane;
717 intel_plane->get_colorkey = ivb_get_colorkey; 929 intel_plane->disable_plane = vlv_disable_plane;
718 930 intel_plane->update_colorkey = vlv_update_colorkey;
719 plane_formats = snb_plane_formats; 931 intel_plane->get_colorkey = vlv_get_colorkey;
720 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 932
933 plane_formats = vlv_plane_formats;
934 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
935 } else {
936 intel_plane->max_downscale = 2;
937 intel_plane->update_plane = ivb_update_plane;
938 intel_plane->disable_plane = ivb_disable_plane;
939 intel_plane->update_colorkey = ivb_update_colorkey;
940 intel_plane->get_colorkey = ivb_get_colorkey;
941
942 plane_formats = snb_plane_formats;
943 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
944 }
721 break; 945 break;
722 946
723 default: 947 default:
@@ -726,6 +950,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
726 } 950 }
727 951
728 intel_plane->pipe = pipe; 952 intel_plane->pipe = pipe;
953 intel_plane->plane = plane;
729 possible_crtcs = (1 << pipe); 954 possible_crtcs = (1 << pipe);
730 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, 955 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
731 &intel_plane_funcs, 956 &intel_plane_funcs,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index d808421c1c80..66737265200f 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -905,11 +905,10 @@ intel_tv_mode_valid(struct drm_connector *connector,
905 905
906 906
907static bool 907static bool
908intel_tv_mode_fixup(struct drm_encoder *encoder, 908intel_tv_compute_config(struct intel_encoder *encoder,
909 const struct drm_display_mode *mode, 909 struct intel_crtc_config *pipe_config)
910 struct drm_display_mode *adjusted_mode)
911{ 910{
912 struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 911 struct intel_tv *intel_tv = enc_to_intel_tv(&encoder->base);
913 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 912 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
914 913
915 if (!tv_mode) 914 if (!tv_mode)
@@ -918,7 +917,10 @@ intel_tv_mode_fixup(struct drm_encoder *encoder,
918 if (intel_encoder_check_is_cloned(&intel_tv->base)) 917 if (intel_encoder_check_is_cloned(&intel_tv->base))
919 return false; 918 return false;
920 919
921 adjusted_mode->clock = tv_mode->clock; 920 pipe_config->adjusted_mode.clock = tv_mode->clock;
921 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
922 pipe_config->pipe_bpp = 8*3;
923
922 return true; 924 return true;
923} 925}
924 926
@@ -1485,7 +1487,6 @@ out:
1485} 1487}
1486 1488
1487static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = { 1489static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = {
1488 .mode_fixup = intel_tv_mode_fixup,
1489 .mode_set = intel_tv_mode_set, 1490 .mode_set = intel_tv_mode_set,
1490}; 1491};
1491 1492
@@ -1620,6 +1621,7 @@ intel_tv_init(struct drm_device *dev)
1620 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs, 1621 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1621 DRM_MODE_ENCODER_TVDAC); 1622 DRM_MODE_ENCODER_TVDAC);
1622 1623
1624 intel_encoder->compute_config = intel_tv_compute_config;
1623 intel_encoder->enable = intel_enable_tv; 1625 intel_encoder->enable = intel_enable_tv;
1624 intel_encoder->disable = intel_disable_tv; 1626 intel_encoder->disable = intel_disable_tv;
1625 intel_encoder->get_hw_state = intel_tv_get_hw_state; 1627 intel_encoder->get_hw_state = intel_tv_get_hw_state;
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index 6fb519f5cce0..8230b46fdd73 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -68,6 +68,10 @@ struct drm_fb_helper_funcs {
68 68
69 int (*fb_probe)(struct drm_fb_helper *helper, 69 int (*fb_probe)(struct drm_fb_helper *helper,
70 struct drm_fb_helper_surface_size *sizes); 70 struct drm_fb_helper_surface_size *sizes);
71 bool (*initial_config)(struct drm_fb_helper *fb_helper,
72 struct drm_fb_helper_crtc **crtcs,
73 struct drm_display_mode **modes,
74 bool *enabled, int width, int height);
71}; 75};
72 76
73struct drm_fb_helper_connector { 77struct drm_fb_helper_connector {
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 2d8bdaef9611..e96b9546c4c6 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -235,13 +235,13 @@ size_t sg_copy_to_buffer(struct scatterlist *sgl, unsigned int nents,
235 * sg page iterator 235 * sg page iterator
236 * 236 *
237 * Iterates over sg entries page-by-page. On each successful iteration, 237 * Iterates over sg entries page-by-page. On each successful iteration,
238 * @piter->page points to the current page, @piter->sg to the sg holding this 238 * you can call sg_page_iter_page(@piter) and sg_page_iter_dma_address(@piter)
239 * page and @piter->sg_pgoffset to the page's page offset within the sg. The 239 * to get the current page and its dma address. @piter->sg will point to the
240 * iteration will stop either when a maximum number of sg entries was reached 240 * sg holding this page and @piter->sg_pgoffset to the page's page offset
241 * or a terminating sg (sg_last(sg) == true) was reached. 241 * within the sg. The iteration will stop either when a maximum number of sg
242 * entries was reached or a terminating sg (sg_last(sg) == true) was reached.
242 */ 243 */
243struct sg_page_iter { 244struct sg_page_iter {
244 struct page *page; /* current page */
245 struct scatterlist *sg; /* sg holding the page */ 245 struct scatterlist *sg; /* sg holding the page */
246 unsigned int sg_pgoffset; /* page offset within the sg */ 246 unsigned int sg_pgoffset; /* page offset within the sg */
247 247
@@ -255,6 +255,24 @@ bool __sg_page_iter_next(struct sg_page_iter *piter);
255void __sg_page_iter_start(struct sg_page_iter *piter, 255void __sg_page_iter_start(struct sg_page_iter *piter,
256 struct scatterlist *sglist, unsigned int nents, 256 struct scatterlist *sglist, unsigned int nents,
257 unsigned long pgoffset); 257 unsigned long pgoffset);
258/**
259 * sg_page_iter_page - get the current page held by the page iterator
260 * @piter: page iterator holding the page
261 */
262static inline struct page *sg_page_iter_page(struct sg_page_iter *piter)
263{
264 return nth_page(sg_page(piter->sg), piter->sg_pgoffset);
265}
266
267/**
268 * sg_page_iter_dma_address - get the dma address of the current page held by
269 * the page iterator.
270 * @piter: page iterator holding the page
271 */
272static inline dma_addr_t sg_page_iter_dma_address(struct sg_page_iter *piter)
273{
274 return sg_dma_address(piter->sg) + (piter->sg_pgoffset << PAGE_SHIFT);
275}
258 276
259/** 277/**
260 * for_each_sg_page - iterate over the pages of the given sg list 278 * for_each_sg_page - iterate over the pages of the given sg list
diff --git a/lib/scatterlist.c b/lib/scatterlist.c
index b83c144d731f..a1cf8cae60e7 100644
--- a/lib/scatterlist.c
+++ b/lib/scatterlist.c
@@ -401,7 +401,6 @@ void __sg_page_iter_start(struct sg_page_iter *piter,
401 piter->__pg_advance = 0; 401 piter->__pg_advance = 0;
402 piter->__nents = nents; 402 piter->__nents = nents;
403 403
404 piter->page = NULL;
405 piter->sg = sglist; 404 piter->sg = sglist;
406 piter->sg_pgoffset = pgoffset; 405 piter->sg_pgoffset = pgoffset;
407} 406}
@@ -426,7 +425,6 @@ bool __sg_page_iter_next(struct sg_page_iter *piter)
426 if (!--piter->__nents || !piter->sg) 425 if (!--piter->__nents || !piter->sg)
427 return false; 426 return false;
428 } 427 }
429 piter->page = nth_page(sg_page(piter->sg), piter->sg_pgoffset);
430 428
431 return true; 429 return true;
432} 430}
@@ -496,7 +494,7 @@ bool sg_miter_next(struct sg_mapping_iter *miter)
496 miter->__remaining = min_t(unsigned long, miter->__remaining, 494 miter->__remaining = min_t(unsigned long, miter->__remaining,
497 PAGE_SIZE - miter->__offset); 495 PAGE_SIZE - miter->__offset);
498 } 496 }
499 miter->page = miter->piter.page; 497 miter->page = sg_page_iter_page(&miter->piter);
500 miter->consumed = miter->length = miter->__remaining; 498 miter->consumed = miter->length = miter->__remaining;
501 499
502 if (miter->__flags & SG_MITER_ATOMIC) 500 if (miter->__flags & SG_MITER_ATOMIC)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 07:26:44 -0400