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-rw-r--r--arch/x86/kernel/acpi/cstate.c4
-rw-r--r--drivers/idle/intel_idle.c204
-rw-r--r--tools/power/x86/turbostat/turbostat.8127
-rw-r--r--tools/power/x86/turbostat/turbostat.c240
4 files changed, 362 insertions, 213 deletions
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index e69182fd01cf..4b28159e0421 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -87,7 +87,9 @@ static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
87 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK; 87 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
88 88
89 retval = 0; 89 retval = 0;
90 if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) { 90 /* If the HW does not support any sub-states in this C-state */
91 if (num_cstate_subtype == 0) {
92 pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", cx->address, edx_part);
91 retval = -1; 93 retval = -1;
92 goto out; 94 goto out;
93 } 95 }
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 8e1939f564f4..9ddbf550bafa 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -196,6 +196,53 @@ static struct cpuidle_state snb_cstates[] = {
196 .enter = NULL } 196 .enter = NULL }
197}; 197};
198 198
199static struct cpuidle_state byt_cstates[] = {
200 {
201 .name = "C1-BYT",
202 .desc = "MWAIT 0x00",
203 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
204 .exit_latency = 1,
205 .target_residency = 1,
206 .enter = &intel_idle },
207 {
208 .name = "C1E-BYT",
209 .desc = "MWAIT 0x01",
210 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
211 .exit_latency = 15,
212 .target_residency = 30,
213 .enter = &intel_idle },
214 {
215 .name = "C6N-BYT",
216 .desc = "MWAIT 0x58",
217 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
218 .exit_latency = 40,
219 .target_residency = 275,
220 .enter = &intel_idle },
221 {
222 .name = "C6S-BYT",
223 .desc = "MWAIT 0x52",
224 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
225 .exit_latency = 140,
226 .target_residency = 560,
227 .enter = &intel_idle },
228 {
229 .name = "C7-BYT",
230 .desc = "MWAIT 0x60",
231 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
232 .exit_latency = 1200,
233 .target_residency = 1500,
234 .enter = &intel_idle },
235 {
236 .name = "C7S-BYT",
237 .desc = "MWAIT 0x64",
238 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
239 .exit_latency = 10000,
240 .target_residency = 20000,
241 .enter = &intel_idle },
242 {
243 .enter = NULL }
244};
245
199static struct cpuidle_state ivb_cstates[] = { 246static struct cpuidle_state ivb_cstates[] = {
200 { 247 {
201 .name = "C1-IVB", 248 .name = "C1-IVB",
@@ -236,6 +283,105 @@ static struct cpuidle_state ivb_cstates[] = {
236 .enter = NULL } 283 .enter = NULL }
237}; 284};
238 285
286static struct cpuidle_state ivt_cstates[] = {
287 {
288 .name = "C1-IVT",
289 .desc = "MWAIT 0x00",
290 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
291 .exit_latency = 1,
292 .target_residency = 1,
293 .enter = &intel_idle },
294 {
295 .name = "C1E-IVT",
296 .desc = "MWAIT 0x01",
297 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
298 .exit_latency = 10,
299 .target_residency = 80,
300 .enter = &intel_idle },
301 {
302 .name = "C3-IVT",
303 .desc = "MWAIT 0x10",
304 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
305 .exit_latency = 59,
306 .target_residency = 156,
307 .enter = &intel_idle },
308 {
309 .name = "C6-IVT",
310 .desc = "MWAIT 0x20",
311 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
312 .exit_latency = 82,
313 .target_residency = 300,
314 .enter = &intel_idle },
315 {
316 .enter = NULL }
317};
318
319static struct cpuidle_state ivt_cstates_4s[] = {
320 {
321 .name = "C1-IVT-4S",
322 .desc = "MWAIT 0x00",
323 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
324 .exit_latency = 1,
325 .target_residency = 1,
326 .enter = &intel_idle },
327 {
328 .name = "C1E-IVT-4S",
329 .desc = "MWAIT 0x01",
330 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
331 .exit_latency = 10,
332 .target_residency = 250,
333 .enter = &intel_idle },
334 {
335 .name = "C3-IVT-4S",
336 .desc = "MWAIT 0x10",
337 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
338 .exit_latency = 59,
339 .target_residency = 300,
340 .enter = &intel_idle },
341 {
342 .name = "C6-IVT-4S",
343 .desc = "MWAIT 0x20",
344 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
345 .exit_latency = 84,
346 .target_residency = 400,
347 .enter = &intel_idle },
348 {
349 .enter = NULL }
350};
351
352static struct cpuidle_state ivt_cstates_8s[] = {
353 {
354 .name = "C1-IVT-8S",
355 .desc = "MWAIT 0x00",
356 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
357 .exit_latency = 1,
358 .target_residency = 1,
359 .enter = &intel_idle },
360 {
361 .name = "C1E-IVT-8S",
362 .desc = "MWAIT 0x01",
363 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
364 .exit_latency = 10,
365 .target_residency = 500,
366 .enter = &intel_idle },
367 {
368 .name = "C3-IVT-8S",
369 .desc = "MWAIT 0x10",
370 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
371 .exit_latency = 59,
372 .target_residency = 600,
373 .enter = &intel_idle },
374 {
375 .name = "C6-IVT-8S",
376 .desc = "MWAIT 0x20",
377 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
378 .exit_latency = 88,
379 .target_residency = 700,
380 .enter = &intel_idle },
381 {
382 .enter = NULL }
383};
384
239static struct cpuidle_state hsw_cstates[] = { 385static struct cpuidle_state hsw_cstates[] = {
240 { 386 {
241 .name = "C1-HSW", 387 .name = "C1-HSW",
@@ -464,11 +610,21 @@ static const struct idle_cpu idle_cpu_snb = {
464 .disable_promotion_to_c1e = true, 610 .disable_promotion_to_c1e = true,
465}; 611};
466 612
613static const struct idle_cpu idle_cpu_byt = {
614 .state_table = byt_cstates,
615 .disable_promotion_to_c1e = true,
616};
617
467static const struct idle_cpu idle_cpu_ivb = { 618static const struct idle_cpu idle_cpu_ivb = {
468 .state_table = ivb_cstates, 619 .state_table = ivb_cstates,
469 .disable_promotion_to_c1e = true, 620 .disable_promotion_to_c1e = true,
470}; 621};
471 622
623static const struct idle_cpu idle_cpu_ivt = {
624 .state_table = ivt_cstates,
625 .disable_promotion_to_c1e = true,
626};
627
472static const struct idle_cpu idle_cpu_hsw = { 628static const struct idle_cpu idle_cpu_hsw = {
473 .state_table = hsw_cstates, 629 .state_table = hsw_cstates,
474 .disable_promotion_to_c1e = true, 630 .disable_promotion_to_c1e = true,
@@ -494,8 +650,10 @@ static const struct x86_cpu_id intel_idle_ids[] = {
494 ICPU(0x2f, idle_cpu_nehalem), 650 ICPU(0x2f, idle_cpu_nehalem),
495 ICPU(0x2a, idle_cpu_snb), 651 ICPU(0x2a, idle_cpu_snb),
496 ICPU(0x2d, idle_cpu_snb), 652 ICPU(0x2d, idle_cpu_snb),
653 ICPU(0x36, idle_cpu_atom),
654 ICPU(0x37, idle_cpu_byt),
497 ICPU(0x3a, idle_cpu_ivb), 655 ICPU(0x3a, idle_cpu_ivb),
498 ICPU(0x3e, idle_cpu_ivb), 656 ICPU(0x3e, idle_cpu_ivt),
499 ICPU(0x3c, idle_cpu_hsw), 657 ICPU(0x3c, idle_cpu_hsw),
500 ICPU(0x3f, idle_cpu_hsw), 658 ICPU(0x3f, idle_cpu_hsw),
501 ICPU(0x45, idle_cpu_hsw), 659 ICPU(0x45, idle_cpu_hsw),
@@ -572,6 +730,39 @@ static void intel_idle_cpuidle_devices_uninit(void)
572 free_percpu(intel_idle_cpuidle_devices); 730 free_percpu(intel_idle_cpuidle_devices);
573 return; 731 return;
574} 732}
733
734/*
735 * intel_idle_state_table_update()
736 *
737 * Update the default state_table for this CPU-id
738 *
739 * Currently used to access tuned IVT multi-socket targets
740 * Assumption: num_sockets == (max_package_num + 1)
741 */
742void intel_idle_state_table_update(void)
743{
744 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
745 if (boot_cpu_data.x86_model == 0x3e) { /* IVT */
746 int cpu, package_num, num_sockets = 1;
747
748 for_each_online_cpu(cpu) {
749 package_num = topology_physical_package_id(cpu);
750 if (package_num + 1 > num_sockets) {
751 num_sockets = package_num + 1;
752
753 if (num_sockets > 4)
754 cpuidle_state_table = ivt_cstates_8s;
755 return;
756 }
757 }
758
759 if (num_sockets > 2)
760 cpuidle_state_table = ivt_cstates_4s;
761 /* else, 1 and 2 socket systems use default ivt_cstates */
762 }
763 return;
764}
765
575/* 766/*
576 * intel_idle_cpuidle_driver_init() 767 * intel_idle_cpuidle_driver_init()
577 * allocate, initialize cpuidle_states 768 * allocate, initialize cpuidle_states
@@ -581,10 +772,12 @@ static int __init intel_idle_cpuidle_driver_init(void)
581 int cstate; 772 int cstate;
582 struct cpuidle_driver *drv = &intel_idle_driver; 773 struct cpuidle_driver *drv = &intel_idle_driver;
583 774
775 intel_idle_state_table_update();
776
584 drv->state_count = 1; 777 drv->state_count = 1;
585 778
586 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { 779 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
587 int num_substates, mwait_hint, mwait_cstate, mwait_substate; 780 int num_substates, mwait_hint, mwait_cstate;
588 781
589 if (cpuidle_state_table[cstate].enter == NULL) 782 if (cpuidle_state_table[cstate].enter == NULL)
590 break; 783 break;
@@ -597,14 +790,13 @@ static int __init intel_idle_cpuidle_driver_init(void)
597 790
598 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); 791 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
599 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); 792 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
600 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
601 793
602 /* does the state exist in CPUID.MWAIT? */ 794 /* number of sub-states for this state in CPUID.MWAIT */
603 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) 795 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
604 & MWAIT_SUBSTATE_MASK; 796 & MWAIT_SUBSTATE_MASK;
605 797
606 /* if sub-state in table is not enumerated by CPUID */ 798 /* if NO sub-states for this state in CPUID, skip it */
607 if ((mwait_substate + 1) > num_substates) 799 if (num_substates == 0)
608 continue; 800 continue;
609 801
610 if (((mwait_cstate + 1) > 2) && 802 if (((mwait_cstate + 1) > 2) &&
diff --git a/tools/power/x86/turbostat/turbostat.8 b/tools/power/x86/turbostat/turbostat.8
index b4ddb748356c..56bfb523c5bb 100644
--- a/tools/power/x86/turbostat/turbostat.8
+++ b/tools/power/x86/turbostat/turbostat.8
@@ -47,21 +47,22 @@ displays the statistics gathered since it was forked.
47.PP 47.PP
48.SH FIELD DESCRIPTIONS 48.SH FIELD DESCRIPTIONS
49.nf 49.nf
50\fBpk\fP processor package number. 50\fBPackage\fP processor package number.
51\fBcor\fP processor core number. 51\fBCore\fP processor core number.
52\fBCPU\fP Linux CPU (logical processor) number. 52\fBCPU\fP Linux CPU (logical processor) number.
53Note that multiple CPUs per core indicate support for Intel(R) Hyper-Threading Technology. 53Note that multiple CPUs per core indicate support for Intel(R) Hyper-Threading Technology.
54\fB%c0\fP percent of the interval that the CPU retired instructions. 54\fBAVG_MHz\fP number of cycles executed divided by time elapsed.
55\fBGHz\fP average clock rate while the CPU was in c0 state. 55\fB%Buzy\fP percent of the interval that the CPU retired instructions, aka. % of time in "C0" state.
56\fBTSC\fP average GHz that the TSC ran during the entire interval. 56\fBBzy_MHz\fP average clock rate while the CPU was busy (in "c0" state).
57\fB%c1, %c3, %c6, %c7\fP show the percentage residency in hardware core idle states. 57\fBTSC_MHz\fP average MHz that the TSC ran during the entire interval.
58\fBCTMP\fP Degrees Celsius reported by the per-core Digital Thermal Sensor. 58\fBCPU%c1, CPU%c3, CPU%c6, CPU%c7\fP show the percentage residency in hardware core idle states.
59\fBPTMP\fP Degrees Celsius reported by the per-package Package Thermal Monitor. 59\fBCoreTmp\fP Degrees Celsius reported by the per-core Digital Thermal Sensor.
60\fB%pc2, %pc3, %pc6, %pc7\fP percentage residency in hardware package idle states. 60\fBPkgTtmp\fP Degrees Celsius reported by the per-package Package Thermal Monitor.
61\fBPkg_W\fP Watts consumed by the whole package. 61\fBPkg%pc2, Pkg%pc3, Pkg%pc6, Pkg%pc7\fP percentage residency in hardware package idle states.
62\fBCor_W\fP Watts consumed by the core part of the package. 62\fBPkgWatt\fP Watts consumed by the whole package.
63\fBGFX_W\fP Watts consumed by the Graphics part of the package -- available only on client processors. 63\fBCorWatt\fP Watts consumed by the core part of the package.
64\fBRAM_W\fP Watts consumed by the DRAM DIMMS -- available only on server processors. 64\fBGFXWatt\fP Watts consumed by the Graphics part of the package -- available only on client processors.
65\fBRAMWatt\fP Watts consumed by the DRAM DIMMS -- available only on server processors.
65\fBPKG_%\fP percent of the interval that RAPL throttling was active on the Package. 66\fBPKG_%\fP percent of the interval that RAPL throttling was active on the Package.
66\fBRAM_%\fP percent of the interval that RAPL throttling was active on DRAM. 67\fBRAM_%\fP percent of the interval that RAPL throttling was active on DRAM.
67.fi 68.fi
@@ -78,29 +79,17 @@ For Watts columns, the summary is a system total.
78Subsequent rows show per-CPU statistics. 79Subsequent rows show per-CPU statistics.
79 80
80.nf 81.nf
81[root@sandy]# ./turbostat 82[root@ivy]# ./turbostat
82cor CPU %c0 GHz TSC %c1 %c3 %c6 %c7 CTMP PTMP %pc2 %pc3 %pc6 %pc7 Pkg_W Cor_W GFX_W 83 Core CPU Avg_MHz %Busy Bzy_MHz TSC_MHz SMI CPU%c1 CPU%c3 CPU%c6 CPU%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
83 0.06 0.80 2.29 0.11 0.00 0.00 99.83 47 40 0.26 0.01 0.44 98.78 3.49 0.12 0.14 84 - - 6 0.36 1596 3492 0 0.59 0.01 99.04 0.00 23 24 23.82 0.01 72.47 0.00 6.40 1.01 0.00
84 0 0 0.07 0.80 2.29 0.07 0.00 0.00 99.86 40 40 0.26 0.01 0.44 98.78 3.49 0.12 0.14 85 0 0 9 0.58 1596 3492 0 0.28 0.01 99.13 0.00 23 24 23.82 0.01 72.47 0.00 6.40 1.01 0.00
85 0 4 0.03 0.80 2.29 0.12 86 0 4 1 0.07 1596 3492 0 0.79
86 1 1 0.04 0.80 2.29 0.25 0.01 0.00 99.71 40 87 1 1 10 0.65 1596 3492 0 0.59 0.00 98.76 0.00 23
87 1 5 0.16 0.80 2.29 0.13 88 1 5 5 0.28 1596 3492 0 0.95
88 2 2 0.05 0.80 2.29 0.06 0.01 0.00 99.88 40 89 2 2 10 0.66 1596 3492 0 0.41 0.01 98.92 0.00 23
89 2 6 0.03 0.80 2.29 0.08 90 2 6 2 0.10 1597 3492 0 0.97
90 3 3 0.05 0.80 2.29 0.08 0.00 0.00 99.87 47 91 3 3 3 0.20 1596 3492 0 0.44 0.00 99.37 0.00 23
91 3 7 0.04 0.84 2.29 0.09 92 3 7 5 0.31 1596 3492 0 0.33
92.fi
93.SH SUMMARY EXAMPLE
94The "-s" option prints the column headers just once,
95and then the one line system summary for each sample interval.
96
97.nf
98[root@wsm]# turbostat -S
99 %c0 GHz TSC %c1 %c3 %c6 CTMP %pc3 %pc6
100 1.40 2.81 3.38 10.78 43.47 44.35 42 13.67 2.09
101 1.34 2.90 3.38 11.48 58.96 28.23 41 19.89 0.15
102 1.55 2.72 3.38 26.73 37.66 34.07 42 2.53 2.80
103 1.37 2.83 3.38 16.95 60.05 21.63 42 5.76 0.20
104.fi 93.fi
105.SH VERBOSE EXAMPLE 94.SH VERBOSE EXAMPLE
106The "-v" option adds verbosity to the output: 95The "-v" option adds verbosity to the output:
@@ -154,55 +143,35 @@ eg. Here a cycle soaker is run on 1 CPU (see %c0) for a few seconds
154until ^C while the other CPUs are mostly idle: 143until ^C while the other CPUs are mostly idle:
155 144
156.nf 145.nf
157[root@x980 lenb]# ./turbostat cat /dev/zero > /dev/null 146root@ivy: turbostat cat /dev/zero > /dev/null
158^C 147^C
159cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6 148 Core CPU Avg_MHz %Busy Bzy_MHz TSC_MHz SMI CPU%c1 CPU%c3 CPU%c6 CPU%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
160 8.86 3.61 3.38 15.06 31.19 44.89 0.00 0.00 149 - - 496 12.75 3886 3492 0 13.16 0.04 74.04 0.00 36 36 0.00 0.00 0.00 0.00 23.15 17.65 0.00
161 0 0 1.46 3.22 3.38 16.84 29.48 52.22 0.00 0.00 150 0 0 22 0.57 3830 3492 0 0.83 0.02 98.59 0.00 27 36 0.00 0.00 0.00 0.00 23.15 17.65 0.00
162 0 6 0.21 3.06 3.38 18.09 151 0 4 9 0.24 3829 3492 0 1.15
163 1 2 0.53 3.33 3.38 2.80 46.40 50.27 152 1 1 4 0.09 3783 3492 0 99.91 0.00 0.00 0.00 36
164 1 8 0.89 3.47 3.38 2.44 153 1 5 3880 99.82 3888 3492 0 0.18
165 2 4 1.36 3.43 3.38 9.04 23.71 65.89 154 2 2 17 0.44 3813 3492 0 0.77 0.04 98.75 0.00 28
166 2 10 0.18 2.86 3.38 10.22 155 2 6 12 0.32 3823 3492 0 0.89
167 8 1 0.04 2.87 3.38 99.96 0.01 0.00 156 3 3 16 0.43 3844 3492 0 0.63 0.11 98.84 0.00 30
168 8 7 99.72 3.63 3.38 0.27 157 3 7 4 0.11 3827 3492 0 0.94
169 9 3 0.31 3.21 3.38 7.64 56.55 35.50 15830.372243 sec
170 9 9 0.08 2.95 3.38 7.88 159
171 10 5 1.42 3.43 3.38 2.14 30.99 65.44
172 10 11 0.16 2.88 3.38 3.40
173.fi 160.fi
174Above the cycle soaker drives cpu7 up its 3.6 GHz turbo limit 161Above the cycle soaker drives cpu5 up its 3.8 GHz turbo limit
175while the other processors are generally in various states of idle. 162while the other processors are generally in various states of idle.
176 163
177Note that cpu1 and cpu7 are HT siblings within core8. 164Note that cpu1 and cpu5 are HT siblings within core1.
178As cpu7 is very busy, it prevents its sibling, cpu1, 165As cpu5 is very busy, it prevents its sibling, cpu1,
179from entering a c-state deeper than c1. 166from entering a c-state deeper than c1.
180 167
181Note that turbostat reports average GHz of 3.63, while 168Note that the Avg_MHz column reflects the total number of cycles executed
182the arithmetic average of the GHz column above is lower. 169divided by the measurement interval. If the %Busy column is 100%,
183This is a weighted average, where the weight is %c0. ie. it is the total number of 170then the processor was running at that speed the entire interval.
184un-halted cycles elapsed per time divided by the number of CPUs. 171The Avg_MHz multiplied by the %Busy results in the Bzy_MHz --
185.SH SMI COUNTING EXAMPLE 172which is the average frequency while the processor was executing --
186On Intel Nehalem and newer processors, MSR 0x34 is a System Management Mode Interrupt (SMI) counter. 173not including any non-busy idle time.
187This counter is shown by default under the "SMI" column. 174
188.nf
189[root@x980 ~]# turbostat
190cor CPU %c0 GHz TSC SMI %c1 %c3 %c6 CTMP %pc3 %pc6
191 0.11 1.91 3.38 0 1.84 0.26 97.79 29 0.82 83.87
192 0 0 0.40 1.63 3.38 0 10.27 0.12 89.20 20 0.82 83.88
193 0 6 0.06 1.63 3.38 0 10.61
194 1 2 0.37 2.63 3.38 0 0.02 0.10 99.51 22
195 1 8 0.01 1.62 3.38 0 0.39
196 2 4 0.07 1.62 3.38 0 0.04 0.07 99.82 23
197 2 10 0.02 1.62 3.38 0 0.09
198 8 1 0.23 1.64 3.38 0 0.10 1.07 98.60 24
199 8 7 0.02 1.64 3.38 0 0.31
200 9 3 0.03 1.62 3.38 0 0.03 0.05 99.89 29
201 9 9 0.02 1.62 3.38 0 0.05
202 10 5 0.07 1.62 3.38 0 0.08 0.12 99.73 27
203 10 11 0.03 1.62 3.38 0 0.13
204^C
205.fi
206.SH NOTES 175.SH NOTES
207 176
208.B "turbostat " 177.B "turbostat "
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 77eb130168da..7c9d8e71eb9e 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -56,7 +56,7 @@ unsigned int do_slm_cstates;
56unsigned int use_c1_residency_msr; 56unsigned int use_c1_residency_msr;
57unsigned int has_aperf; 57unsigned int has_aperf;
58unsigned int has_epb; 58unsigned int has_epb;
59unsigned int units = 1000000000; /* Ghz etc */ 59unsigned int units = 1000000; /* MHz etc */
60unsigned int genuine_intel; 60unsigned int genuine_intel;
61unsigned int has_invariant_tsc; 61unsigned int has_invariant_tsc;
62unsigned int do_nehalem_platform_info; 62unsigned int do_nehalem_platform_info;
@@ -264,88 +264,93 @@ int get_msr(int cpu, off_t offset, unsigned long long *msr)
264 return 0; 264 return 0;
265} 265}
266 266
267/*
268 * Example Format w/ field column widths:
269 *
270 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz SMI %Busy CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
271 * 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567
272 */
273
267void print_header(void) 274void print_header(void)
268{ 275{
269 if (show_pkg) 276 if (show_pkg)
270 outp += sprintf(outp, "pk"); 277 outp += sprintf(outp, "Package ");
271 if (show_pkg)
272 outp += sprintf(outp, " ");
273 if (show_core) 278 if (show_core)
274 outp += sprintf(outp, "cor"); 279 outp += sprintf(outp, " Core ");
275 if (show_cpu) 280 if (show_cpu)
276 outp += sprintf(outp, " CPU"); 281 outp += sprintf(outp, " CPU ");
277 if (show_pkg || show_core || show_cpu) 282 if (has_aperf)
278 outp += sprintf(outp, " "); 283 outp += sprintf(outp, "Avg_MHz ");
279 if (do_nhm_cstates) 284 if (do_nhm_cstates)
280 outp += sprintf(outp, " %%c0"); 285 outp += sprintf(outp, " %%Busy ");
281 if (has_aperf) 286 if (has_aperf)
282 outp += sprintf(outp, " GHz"); 287 outp += sprintf(outp, "Bzy_MHz ");
283 outp += sprintf(outp, " TSC"); 288 outp += sprintf(outp, "TSC_MHz ");
284 if (do_smi) 289 if (do_smi)
285 outp += sprintf(outp, " SMI"); 290 outp += sprintf(outp, " SMI ");
286 if (extra_delta_offset32) 291 if (extra_delta_offset32)
287 outp += sprintf(outp, " count 0x%03X", extra_delta_offset32); 292 outp += sprintf(outp, " count 0x%03X ", extra_delta_offset32);
288 if (extra_delta_offset64) 293 if (extra_delta_offset64)
289 outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64); 294 outp += sprintf(outp, " COUNT 0x%03X ", extra_delta_offset64);
290 if (extra_msr_offset32) 295 if (extra_msr_offset32)
291 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32); 296 outp += sprintf(outp, " MSR 0x%03X ", extra_msr_offset32);
292 if (extra_msr_offset64) 297 if (extra_msr_offset64)
293 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64); 298 outp += sprintf(outp, " MSR 0x%03X ", extra_msr_offset64);
294 if (do_nhm_cstates) 299 if (do_nhm_cstates)
295 outp += sprintf(outp, " %%c1"); 300 outp += sprintf(outp, " CPU%%c1 ");
296 if (do_nhm_cstates && !do_slm_cstates) 301 if (do_nhm_cstates && !do_slm_cstates)
297 outp += sprintf(outp, " %%c3"); 302 outp += sprintf(outp, " CPU%%c3 ");
298 if (do_nhm_cstates) 303 if (do_nhm_cstates)
299 outp += sprintf(outp, " %%c6"); 304 outp += sprintf(outp, " CPU%%c6 ");
300 if (do_snb_cstates) 305 if (do_snb_cstates)
301 outp += sprintf(outp, " %%c7"); 306 outp += sprintf(outp, " CPU%%c7 ");
302 307
303 if (do_dts) 308 if (do_dts)
304 outp += sprintf(outp, " CTMP"); 309 outp += sprintf(outp, "CoreTmp ");
305 if (do_ptm) 310 if (do_ptm)
306 outp += sprintf(outp, " PTMP"); 311 outp += sprintf(outp, " PkgTmp ");
307 312
308 if (do_snb_cstates) 313 if (do_snb_cstates)
309 outp += sprintf(outp, " %%pc2"); 314 outp += sprintf(outp, "Pkg%%pc2 ");
310 if (do_nhm_cstates && !do_slm_cstates) 315 if (do_nhm_cstates && !do_slm_cstates)
311 outp += sprintf(outp, " %%pc3"); 316 outp += sprintf(outp, "Pkg%%pc3 ");
312 if (do_nhm_cstates && !do_slm_cstates) 317 if (do_nhm_cstates && !do_slm_cstates)
313 outp += sprintf(outp, " %%pc6"); 318 outp += sprintf(outp, "Pkg%%pc6 ");
314 if (do_snb_cstates) 319 if (do_snb_cstates)
315 outp += sprintf(outp, " %%pc7"); 320 outp += sprintf(outp, "Pkg%%pc7 ");
316 if (do_c8_c9_c10) { 321 if (do_c8_c9_c10) {
317 outp += sprintf(outp, " %%pc8"); 322 outp += sprintf(outp, "Pkg%%pc8 ");
318 outp += sprintf(outp, " %%pc9"); 323 outp += sprintf(outp, "Pkg%%pc9 ");
319 outp += sprintf(outp, " %%pc10"); 324 outp += sprintf(outp, "Pk%%pc10 ");
320 } 325 }
321 326
322 if (do_rapl && !rapl_joules) { 327 if (do_rapl && !rapl_joules) {
323 if (do_rapl & RAPL_PKG) 328 if (do_rapl & RAPL_PKG)
324 outp += sprintf(outp, " Pkg_W"); 329 outp += sprintf(outp, "PkgWatt ");
325 if (do_rapl & RAPL_CORES) 330 if (do_rapl & RAPL_CORES)
326 outp += sprintf(outp, " Cor_W"); 331 outp += sprintf(outp, "CorWatt ");
327 if (do_rapl & RAPL_GFX) 332 if (do_rapl & RAPL_GFX)
328 outp += sprintf(outp, " GFX_W"); 333 outp += sprintf(outp, "GFXWatt ");
329 if (do_rapl & RAPL_DRAM) 334 if (do_rapl & RAPL_DRAM)
330 outp += sprintf(outp, " RAM_W"); 335 outp += sprintf(outp, "RAMWatt ");
331 if (do_rapl & RAPL_PKG_PERF_STATUS) 336 if (do_rapl & RAPL_PKG_PERF_STATUS)
332 outp += sprintf(outp, " PKG_%%"); 337 outp += sprintf(outp, " PKG_%% ");
333 if (do_rapl & RAPL_DRAM_PERF_STATUS) 338 if (do_rapl & RAPL_DRAM_PERF_STATUS)
334 outp += sprintf(outp, " RAM_%%"); 339 outp += sprintf(outp, " RAM_%% ");
335 } else { 340 } else {
336 if (do_rapl & RAPL_PKG) 341 if (do_rapl & RAPL_PKG)
337 outp += sprintf(outp, " Pkg_J"); 342 outp += sprintf(outp, " Pkg_J ");
338 if (do_rapl & RAPL_CORES) 343 if (do_rapl & RAPL_CORES)
339 outp += sprintf(outp, " Cor_J"); 344 outp += sprintf(outp, " Cor_J ");
340 if (do_rapl & RAPL_GFX) 345 if (do_rapl & RAPL_GFX)
341 outp += sprintf(outp, " GFX_J"); 346 outp += sprintf(outp, " GFX_J ");
342 if (do_rapl & RAPL_DRAM) 347 if (do_rapl & RAPL_DRAM)
343 outp += sprintf(outp, " RAM_W"); 348 outp += sprintf(outp, " RAM_W ");
344 if (do_rapl & RAPL_PKG_PERF_STATUS) 349 if (do_rapl & RAPL_PKG_PERF_STATUS)
345 outp += sprintf(outp, " PKG_%%"); 350 outp += sprintf(outp, " PKG_%% ");
346 if (do_rapl & RAPL_DRAM_PERF_STATUS) 351 if (do_rapl & RAPL_DRAM_PERF_STATUS)
347 outp += sprintf(outp, " RAM_%%"); 352 outp += sprintf(outp, " RAM_%% ");
348 outp += sprintf(outp, " time"); 353 outp += sprintf(outp, " time ");
349 354
350 } 355 }
351 outp += sprintf(outp, "\n"); 356 outp += sprintf(outp, "\n");
@@ -410,25 +415,12 @@ int dump_counters(struct thread_data *t, struct core_data *c,
410 415
411/* 416/*
412 * column formatting convention & formats 417 * column formatting convention & formats
413 * package: "pk" 2 columns %2d
414 * core: "cor" 3 columns %3d
415 * CPU: "CPU" 3 columns %3d
416 * Pkg_W: %6.2
417 * Cor_W: %6.2
418 * GFX_W: %5.2
419 * RAM_W: %5.2
420 * GHz: "GHz" 3 columns %3.2
421 * TSC: "TSC" 3 columns %3.2
422 * SMI: "SMI" 4 columns %4d
423 * percentage " %pc3" %6.2
424 * Perf Status percentage: %5.2
425 * "CTMP" 4 columns %4d
426 */ 418 */
427int format_counters(struct thread_data *t, struct core_data *c, 419int format_counters(struct thread_data *t, struct core_data *c,
428 struct pkg_data *p) 420 struct pkg_data *p)
429{ 421{
430 double interval_float; 422 double interval_float;
431 char *fmt5, *fmt6; 423 char *fmt8;
432 424
433 /* if showing only 1st thread in core and this isn't one, bail out */ 425 /* if showing only 1st thread in core and this isn't one, bail out */
434 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 426 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
@@ -443,65 +435,52 @@ int format_counters(struct thread_data *t, struct core_data *c,
443 /* topo columns, print blanks on 1st (average) line */ 435 /* topo columns, print blanks on 1st (average) line */
444 if (t == &average.threads) { 436 if (t == &average.threads) {
445 if (show_pkg) 437 if (show_pkg)
446 outp += sprintf(outp, " "); 438 outp += sprintf(outp, " -");
447 if (show_pkg && show_core)
448 outp += sprintf(outp, " ");
449 if (show_core) 439 if (show_core)
450 outp += sprintf(outp, " "); 440 outp += sprintf(outp, " -");
451 if (show_cpu) 441 if (show_cpu)
452 outp += sprintf(outp, " " " "); 442 outp += sprintf(outp, " -");
453 } else { 443 } else {
454 if (show_pkg) { 444 if (show_pkg) {
455 if (p) 445 if (p)
456 outp += sprintf(outp, "%2d", p->package_id); 446 outp += sprintf(outp, "%8d", p->package_id);
457 else 447 else
458 outp += sprintf(outp, " "); 448 outp += sprintf(outp, " -");
459 } 449 }
460 if (show_pkg && show_core)
461 outp += sprintf(outp, " ");
462 if (show_core) { 450 if (show_core) {
463 if (c) 451 if (c)
464 outp += sprintf(outp, "%3d", c->core_id); 452 outp += sprintf(outp, "%8d", c->core_id);
465 else 453 else
466 outp += sprintf(outp, " "); 454 outp += sprintf(outp, " -");
467 } 455 }
468 if (show_cpu) 456 if (show_cpu)
469 outp += sprintf(outp, " %3d", t->cpu_id); 457 outp += sprintf(outp, "%8d", t->cpu_id);
470 } 458 }
459
460 /* AvgMHz */
461 if (has_aperf)
462 outp += sprintf(outp, "%8.0f",
463 1.0 / units * t->aperf / interval_float);
464
471 /* %c0 */ 465 /* %c0 */
472 if (do_nhm_cstates) { 466 if (do_nhm_cstates) {
473 if (show_pkg || show_core || show_cpu)
474 outp += sprintf(outp, " ");
475 if (!skip_c0) 467 if (!skip_c0)
476 outp += sprintf(outp, "%6.2f", 100.0 * t->mperf/t->tsc); 468 outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc);
477 else 469 else
478 outp += sprintf(outp, " ****"); 470 outp += sprintf(outp, "********");
479 } 471 }
480 472
481 /* GHz */ 473 /* BzyMHz */
482 if (has_aperf) { 474 if (has_aperf)
483 if (!aperf_mperf_unstable) { 475 outp += sprintf(outp, "%8.0f",
484 outp += sprintf(outp, " %3.2f", 476 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
485 1.0 * t->tsc / units * t->aperf /
486 t->mperf / interval_float);
487 } else {
488 if (t->aperf > t->tsc || t->mperf > t->tsc) {
489 outp += sprintf(outp, " ***");
490 } else {
491 outp += sprintf(outp, "%3.1f*",
492 1.0 * t->tsc /
493 units * t->aperf /
494 t->mperf / interval_float);
495 }
496 }
497 }
498 477
499 /* TSC */ 478 /* TSC */
500 outp += sprintf(outp, "%5.2f", 1.0 * t->tsc/units/interval_float); 479 outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float);
501 480
502 /* SMI */ 481 /* SMI */
503 if (do_smi) 482 if (do_smi)
504 outp += sprintf(outp, "%4d", t->smi_count); 483 outp += sprintf(outp, "%8d", t->smi_count);
505 484
506 /* delta */ 485 /* delta */
507 if (extra_delta_offset32) 486 if (extra_delta_offset32)
@@ -520,9 +499,9 @@ int format_counters(struct thread_data *t, struct core_data *c,
520 499
521 if (do_nhm_cstates) { 500 if (do_nhm_cstates) {
522 if (!skip_c1) 501 if (!skip_c1)
523 outp += sprintf(outp, " %6.2f", 100.0 * t->c1/t->tsc); 502 outp += sprintf(outp, "%8.2f", 100.0 * t->c1/t->tsc);
524 else 503 else
525 outp += sprintf(outp, " ****"); 504 outp += sprintf(outp, "********");
526 } 505 }
527 506
528 /* print per-core data only for 1st thread in core */ 507 /* print per-core data only for 1st thread in core */
@@ -530,79 +509,76 @@ int format_counters(struct thread_data *t, struct core_data *c,
530 goto done; 509 goto done;
531 510
532 if (do_nhm_cstates && !do_slm_cstates) 511 if (do_nhm_cstates && !do_slm_cstates)
533 outp += sprintf(outp, " %6.2f", 100.0 * c->c3/t->tsc); 512 outp += sprintf(outp, "%8.2f", 100.0 * c->c3/t->tsc);
534 if (do_nhm_cstates) 513 if (do_nhm_cstates)
535 outp += sprintf(outp, " %6.2f", 100.0 * c->c6/t->tsc); 514 outp += sprintf(outp, "%8.2f", 100.0 * c->c6/t->tsc);
536 if (do_snb_cstates) 515 if (do_snb_cstates)
537 outp += sprintf(outp, " %6.2f", 100.0 * c->c7/t->tsc); 516 outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc);
538 517
539 if (do_dts) 518 if (do_dts)
540 outp += sprintf(outp, " %4d", c->core_temp_c); 519 outp += sprintf(outp, "%8d", c->core_temp_c);
541 520
542 /* print per-package data only for 1st core in package */ 521 /* print per-package data only for 1st core in package */
543 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 522 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
544 goto done; 523 goto done;
545 524
546 if (do_ptm) 525 if (do_ptm)
547 outp += sprintf(outp, " %4d", p->pkg_temp_c); 526 outp += sprintf(outp, "%8d", p->pkg_temp_c);
548 527
549 if (do_snb_cstates) 528 if (do_snb_cstates)
550 outp += sprintf(outp, " %6.2f", 100.0 * p->pc2/t->tsc); 529 outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc);
551 if (do_nhm_cstates && !do_slm_cstates) 530 if (do_nhm_cstates && !do_slm_cstates)
552 outp += sprintf(outp, " %6.2f", 100.0 * p->pc3/t->tsc); 531 outp += sprintf(outp, "%8.2f", 100.0 * p->pc3/t->tsc);
553 if (do_nhm_cstates && !do_slm_cstates) 532 if (do_nhm_cstates && !do_slm_cstates)
554 outp += sprintf(outp, " %6.2f", 100.0 * p->pc6/t->tsc); 533 outp += sprintf(outp, "%8.2f", 100.0 * p->pc6/t->tsc);
555 if (do_snb_cstates) 534 if (do_snb_cstates)
556 outp += sprintf(outp, " %6.2f", 100.0 * p->pc7/t->tsc); 535 outp += sprintf(outp, "%8.2f", 100.0 * p->pc7/t->tsc);
557 if (do_c8_c9_c10) { 536 if (do_c8_c9_c10) {
558 outp += sprintf(outp, " %6.2f", 100.0 * p->pc8/t->tsc); 537 outp += sprintf(outp, "%8.2f", 100.0 * p->pc8/t->tsc);
559 outp += sprintf(outp, " %6.2f", 100.0 * p->pc9/t->tsc); 538 outp += sprintf(outp, "%8.2f", 100.0 * p->pc9/t->tsc);
560 outp += sprintf(outp, " %6.2f", 100.0 * p->pc10/t->tsc); 539 outp += sprintf(outp, "%8.2f", 100.0 * p->pc10/t->tsc);
561 } 540 }
562 541
563 /* 542 /*
564 * If measurement interval exceeds minimum RAPL Joule Counter range, 543 * If measurement interval exceeds minimum RAPL Joule Counter range,
565 * indicate that results are suspect by printing "**" in fraction place. 544 * indicate that results are suspect by printing "**" in fraction place.
566 */ 545 */
567 if (interval_float < rapl_joule_counter_range) { 546 if (interval_float < rapl_joule_counter_range)
568 fmt5 = " %5.2f"; 547 fmt8 = "%8.2f";
569 fmt6 = " %6.2f"; 548 else
570 } else { 549 fmt8 = " %6.0f**";
571 fmt5 = " %3.0f**";
572 fmt6 = " %4.0f**";
573 }
574 550
575 if (do_rapl && !rapl_joules) { 551 if (do_rapl && !rapl_joules) {
576 if (do_rapl & RAPL_PKG) 552 if (do_rapl & RAPL_PKG)
577 outp += sprintf(outp, fmt6, p->energy_pkg * rapl_energy_units / interval_float); 553 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
578 if (do_rapl & RAPL_CORES) 554 if (do_rapl & RAPL_CORES)
579 outp += sprintf(outp, fmt6, p->energy_cores * rapl_energy_units / interval_float); 555 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
580 if (do_rapl & RAPL_GFX) 556 if (do_rapl & RAPL_GFX)
581 outp += sprintf(outp, fmt5, p->energy_gfx * rapl_energy_units / interval_float); 557 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
582 if (do_rapl & RAPL_DRAM) 558 if (do_rapl & RAPL_DRAM)
583 outp += sprintf(outp, fmt5, p->energy_dram * rapl_energy_units / interval_float); 559 outp += sprintf(outp, fmt8, p->energy_dram * rapl_energy_units / interval_float);
584 if (do_rapl & RAPL_PKG_PERF_STATUS) 560 if (do_rapl & RAPL_PKG_PERF_STATUS)
585 outp += sprintf(outp, fmt5, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 561 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
586 if (do_rapl & RAPL_DRAM_PERF_STATUS) 562 if (do_rapl & RAPL_DRAM_PERF_STATUS)
587 outp += sprintf(outp, fmt5, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 563 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
588 } else { 564 } else {
589 if (do_rapl & RAPL_PKG) 565 if (do_rapl & RAPL_PKG)
590 outp += sprintf(outp, fmt6, 566 outp += sprintf(outp, fmt8,
591 p->energy_pkg * rapl_energy_units); 567 p->energy_pkg * rapl_energy_units);
592 if (do_rapl & RAPL_CORES) 568 if (do_rapl & RAPL_CORES)
593 outp += sprintf(outp, fmt6, 569 outp += sprintf(outp, fmt8,
594 p->energy_cores * rapl_energy_units); 570 p->energy_cores * rapl_energy_units);
595 if (do_rapl & RAPL_GFX) 571 if (do_rapl & RAPL_GFX)
596 outp += sprintf(outp, fmt5, 572 outp += sprintf(outp, fmt8,
597 p->energy_gfx * rapl_energy_units); 573 p->energy_gfx * rapl_energy_units);
598 if (do_rapl & RAPL_DRAM) 574 if (do_rapl & RAPL_DRAM)
599 outp += sprintf(outp, fmt5, 575 outp += sprintf(outp, fmt8,
600 p->energy_dram * rapl_energy_units); 576 p->energy_dram * rapl_energy_units);
601 if (do_rapl & RAPL_PKG_PERF_STATUS) 577 if (do_rapl & RAPL_PKG_PERF_STATUS)
602 outp += sprintf(outp, fmt5, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 578 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
603 if (do_rapl & RAPL_DRAM_PERF_STATUS) 579 if (do_rapl & RAPL_DRAM_PERF_STATUS)
604 outp += sprintf(outp, fmt5, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 580 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
605 outp += sprintf(outp, fmt5, interval_float); 581 outp += sprintf(outp, fmt8, interval_float);
606 582
607 } 583 }
608done: 584done:
@@ -1516,6 +1492,9 @@ int has_nehalem_turbo_ratio_limit(unsigned int family, unsigned int model)
1516 case 0x46: /* HSW */ 1492 case 0x46: /* HSW */
1517 case 0x37: /* BYT */ 1493 case 0x37: /* BYT */
1518 case 0x4D: /* AVN */ 1494 case 0x4D: /* AVN */
1495 case 0x3D: /* BDW */
1496 case 0x4F: /* BDX */
1497 case 0x56: /* BDX-DE */
1519 return 1; 1498 return 1;
1520 case 0x2E: /* Nehalem-EX Xeon - Beckton */ 1499 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1521 case 0x2F: /* Westmere-EX Xeon - Eagleton */ 1500 case 0x2F: /* Westmere-EX Xeon - Eagleton */
@@ -1629,9 +1608,12 @@ void rapl_probe(unsigned int family, unsigned int model)
1629 case 0x3C: /* HSW */ 1608 case 0x3C: /* HSW */
1630 case 0x45: /* HSW */ 1609 case 0x45: /* HSW */
1631 case 0x46: /* HSW */ 1610 case 0x46: /* HSW */
1611 case 0x3D: /* BDW */
1632 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 1612 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
1633 break; 1613 break;
1634 case 0x3F: /* HSX */ 1614 case 0x3F: /* HSX */
1615 case 0x4F: /* BDX */
1616 case 0x56: /* BDX-DE */
1635 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 1617 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
1636 break; 1618 break;
1637 case 0x2D: 1619 case 0x2D:
@@ -1875,6 +1857,9 @@ int is_snb(unsigned int family, unsigned int model)
1875 case 0x3F: /* HSW */ 1857 case 0x3F: /* HSW */
1876 case 0x45: /* HSW */ 1858 case 0x45: /* HSW */
1877 case 0x46: /* HSW */ 1859 case 0x46: /* HSW */
1860 case 0x3D: /* BDW */
1861 case 0x4F: /* BDX */
1862 case 0x56: /* BDX-DE */
1878 return 1; 1863 return 1;
1879 } 1864 }
1880 return 0; 1865 return 0;
@@ -1886,7 +1871,8 @@ int has_c8_c9_c10(unsigned int family, unsigned int model)
1886 return 0; 1871 return 0;
1887 1872
1888 switch (model) { 1873 switch (model) {
1889 case 0x45: 1874 case 0x45: /* HSW */
1875 case 0x3D: /* BDW */
1890 return 1; 1876 return 1;
1891 } 1877 }
1892 return 0; 1878 return 0;
@@ -2455,7 +2441,7 @@ int main(int argc, char **argv)
2455 cmdline(argc, argv); 2441 cmdline(argc, argv);
2456 2442
2457 if (verbose) 2443 if (verbose)
2458 fprintf(stderr, "turbostat v3.6 Dec 2, 2013" 2444 fprintf(stderr, "turbostat v3.7 Feb 6, 2014"
2459 " - Len Brown <lenb@kernel.org>\n"); 2445 " - Len Brown <lenb@kernel.org>\n");
2460 2446
2461 turbostat_init(); 2447 turbostat_init();
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 04:10:38 -0500