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-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c24
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c30
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c46
3 files changed, 70 insertions, 30 deletions
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 74768d6c245b..d82d5369e36d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -316,8 +316,16 @@ static struct resource sdhi0_resources[] = {
316 .flags = IORESOURCE_MEM, 316 .flags = IORESOURCE_MEM,
317 }, 317 },
318 [1] = { 318 [1] = {
319 .start = evt2irq(0x0e00) /* SDHI0 */, 319 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
320 .flags = IORESOURCE_IRQ, 320 .flags = IORESOURCE_IRQ,
321 },
322 [2] = {
323 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
324 .flags = IORESOURCE_IRQ,
325 },
326 [3] = {
327 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
328 .flags = IORESOURCE_IRQ,
321 }, 329 },
322}; 330};
323 331
@@ -349,8 +357,16 @@ static struct resource sdhi1_resources[] = {
349 .flags = IORESOURCE_MEM, 357 .flags = IORESOURCE_MEM,
350 }, 358 },
351 [1] = { 359 [1] = {
352 .start = evt2irq(0x0e80), 360 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
353 .flags = IORESOURCE_IRQ, 361 .flags = IORESOURCE_IRQ,
362 },
363 [2] = {
364 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
365 .flags = IORESOURCE_IRQ,
366 },
367 [3] = {
368 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
369 .flags = IORESOURCE_IRQ,
354 }, 370 },
355}; 371};
356 372
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index d94fd0c427a8..ca5b35bd2466 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -684,7 +684,15 @@ static struct resource sdhi0_resources[] = {
684 .flags = IORESOURCE_MEM, 684 .flags = IORESOURCE_MEM,
685 }, 685 },
686 [1] = { 686 [1] = {
687 .start = evt2irq(0x0e00) /* SDHI0 */, 687 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
688 .flags = IORESOURCE_IRQ,
689 },
690 [2] = {
691 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
692 .flags = IORESOURCE_IRQ,
693 },
694 [3] = {
695 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
688 .flags = IORESOURCE_IRQ, 696 .flags = IORESOURCE_IRQ,
689 }, 697 },
690}; 698};
@@ -719,7 +727,15 @@ static struct resource sdhi1_resources[] = {
719 .flags = IORESOURCE_MEM, 727 .flags = IORESOURCE_MEM,
720 }, 728 },
721 [1] = { 729 [1] = {
722 .start = evt2irq(0x0e80), 730 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
731 .flags = IORESOURCE_IRQ,
732 },
733 [2] = {
734 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
735 .flags = IORESOURCE_IRQ,
736 },
737 [3] = {
738 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
723 .flags = IORESOURCE_IRQ, 739 .flags = IORESOURCE_IRQ,
724 }, 740 },
725}; 741};
@@ -762,7 +778,15 @@ static struct resource sdhi2_resources[] = {
762 .flags = IORESOURCE_MEM, 778 .flags = IORESOURCE_MEM,
763 }, 779 },
764 [1] = { 780 [1] = {
765 .start = evt2irq(0x1200), 781 .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
782 .flags = IORESOURCE_IRQ,
783 },
784 [2] = {
785 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
786 .flags = IORESOURCE_IRQ,
787 },
788 [3] = {
789 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
766 .flags = IORESOURCE_IRQ, 790 .flags = IORESOURCE_IRQ,
767 }, 791 },
768}; 792};
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 7a4960f9c1e3..3b28743c77eb 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -27,8 +27,6 @@
27 27
28enum { 28enum {
29 UNUSED_INTCA = 0, 29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
32 30
33 /* interrupt sources INTCA */ 31 /* interrupt sources INTCA */
34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -49,14 +47,14 @@ enum {
49 MSIOF2, MSIOF1, 47 MSIOF2, MSIOF1,
50 SCIFA4, SCIFA5, SCIFB, 48 SCIFA4, SCIFA5, SCIFB,
51 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 49 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
52 SDHI0, 50 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
53 SDHI1, 51 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
54 IRREM, 52 IRREM,
55 IRDA, 53 IRDA,
56 TPU0, 54 TPU0,
57 TTI20, 55 TTI20,
58 DDM, 56 DDM,
59 SDHI2, 57 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
60 RWDT0, 58 RWDT0,
61 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, 59 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
62 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, 60 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
@@ -84,7 +82,7 @@ enum {
84 82
85 /* interrupt groups INTCA */ 83 /* interrupt groups INTCA */
86 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, 84 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
87 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1 85 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
88}; 86};
89 87
90static struct intc_vect intca_vectors[] __initdata = { 88static struct intc_vect intca_vectors[] __initdata = {
@@ -125,17 +123,17 @@ static struct intc_vect intca_vectors[] __initdata = {
125 INTC_VECT(SCIFB, 0x0d60), 123 INTC_VECT(SCIFB, 0x0d60),
126 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 124 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
127 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 125 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
128 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20), 126 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
129 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60), 127 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
130 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0), 128 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
131 INTC_VECT(SDHI1, 0x0ec0), 129 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
132 INTC_VECT(IRREM, 0x0f60), 130 INTC_VECT(IRREM, 0x0f60),
133 INTC_VECT(IRDA, 0x0480), 131 INTC_VECT(IRDA, 0x0480),
134 INTC_VECT(TPU0, 0x04a0), 132 INTC_VECT(TPU0, 0x04a0),
135 INTC_VECT(TTI20, 0x1100), 133 INTC_VECT(TTI20, 0x1100),
136 INTC_VECT(DDM, 0x1140), 134 INTC_VECT(DDM, 0x1140),
137 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220), 135 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
138 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260), 136 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
139 INTC_VECT(RWDT0, 0x1280), 137 INTC_VECT(RWDT0, 0x1280),
140 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), 138 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
141 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), 139 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
@@ -195,6 +193,12 @@ static struct intc_group intca_groups[] __initdata = {
195 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 193 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
196 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 194 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
197 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 195 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
196 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
197 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
198 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
199 SDHI1_SDHI1I2),
200 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
201 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
198 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), 202 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
199}; 203};
200 204
@@ -230,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
230 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 234 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
231 0, 0, MSIOF2, 0 } }, 235 0, 0, MSIOF2, 0 } },
232 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
233 { DISABLED, ENABLED, ENABLED, ENABLED, 237 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
234 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
235 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
236 { 0, ENABLED, ENABLED, ENABLED, 240 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
237 TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, 241 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
238 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
239 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -248,7 +252,7 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
248 { 0, 0, TPU0, 0, 252 { 0, 0, TPU0, 0,
249 0, 0, 0, 0 } }, 253 0, 0, 0, 0 } },
250 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 254 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
251 { DISABLED, DISABLED, ENABLED, ENABLED, 255 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
252 0, CMT3, 0, RWDT0 } }, 256 0, CMT3, 0, RWDT0 } },
253 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ 257 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
254 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, 258 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
@@ -354,14 +358,10 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
354 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 358 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
355}; 359};
356 360
357static struct intc_desc intca_desc __initdata = { 361static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
358 .name = "sh7372-intca", 362 intca_vectors, intca_groups,
359 .force_enable = ENABLED, 363 intca_mask_registers, intca_prio_registers,
360 .force_disable = DISABLED, 364 intca_sense_registers, intca_ack_registers);
361 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
362 intca_mask_registers, intca_prio_registers,
363 intca_sense_registers, intca_ack_registers),
364};
365 365
366enum { 366enum {
367 UNUSED_INTCS = 0, 367 UNUSED_INTCS = 0,