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-rw-r--r--arch/blackfin/Kconfig32
-rw-r--r--arch/blackfin/include/asm/time.h1
-rw-r--r--arch/blackfin/kernel/time-ts.c222
-rw-r--r--arch/blackfin/kernel/time.c10
-rw-r--r--arch/blackfin/mach-bf518/Kconfig1
-rw-r--r--arch/blackfin/mach-bf527/Kconfig1
-rw-r--r--arch/blackfin/mach-bf533/Kconfig1
-rw-r--r--arch/blackfin/mach-bf537/Kconfig1
-rw-r--r--arch/blackfin/mach-bf538/Kconfig1
-rw-r--r--arch/blackfin/mach-bf548/Kconfig1
-rw-r--r--arch/blackfin/mach-bf561/Kconfig1
-rw-r--r--arch/blackfin/mach-bf561/smp.c2
-rw-r--r--arch/blackfin/mach-common/ints-priority.c23
-rw-r--r--arch/blackfin/mach-common/smp.c5
14 files changed, 228 insertions, 74 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index cea2bfd64a56..c04e7a4836f2 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -241,12 +241,6 @@ config IRQ_PER_CPU
241 depends on SMP 241 depends on SMP
242 default y 242 default y
243 243
244config TICK_SOURCE_SYSTMR0
245 bool
246 select BFIN_GPTIMERS
247 depends on SMP
248 default y
249
250config BF_REV_MIN 244config BF_REV_MIN
251 int 245 int
252 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) 246 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
@@ -607,7 +601,6 @@ source kernel/Kconfig.hz
607 601
608config GENERIC_TIME 602config GENERIC_TIME
609 bool "Generic time" 603 bool "Generic time"
610 depends on !SMP
611 default y 604 default y
612 605
613config GENERIC_CLOCKEVENTS 606config GENERIC_CLOCKEVENTS
@@ -615,12 +608,26 @@ config GENERIC_CLOCKEVENTS
615 depends on GENERIC_TIME 608 depends on GENERIC_TIME
616 default y 609 default y
617 610
611choice
612 prompt "Kernel Tick Source"
613 depends on GENERIC_CLOCKEVENTS
614 default TICKSOURCE_CORETMR
615
616config TICKSOURCE_GPTMR0
617 bool "Gptimer0 (SCLK domain)"
618 select BFIN_GPTIMERS
619 depends on !IPIPE
620
621config TICKSOURCE_CORETMR
622 bool "Core timer (CCLK domain)"
623
624endchoice
625
618config CYCLES_CLOCKSOURCE 626config CYCLES_CLOCKSOURCE
619 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" 627 bool "Use 'CYCLES' as a clocksource"
620 depends on EXPERIMENTAL
621 depends on GENERIC_CLOCKEVENTS 628 depends on GENERIC_CLOCKEVENTS
622 depends on !BFIN_SCRATCH_REG_CYCLES 629 depends on !BFIN_SCRATCH_REG_CYCLES
623 default n 630 depends on !SMP
624 help 631 help
625 If you say Y here, you will enable support for using the 'cycles' 632 If you say Y here, you will enable support for using the 'cycles'
626 registers as a clock source. Doing so means you will be unable to 633 registers as a clock source. Doing so means you will be unable to
@@ -628,6 +635,11 @@ config CYCLES_CLOCKSOURCE
628 still be able to read it (such as for performance monitoring), but 635 still be able to read it (such as for performance monitoring), but
629 writing the registers will most likely crash the kernel. 636 writing the registers will most likely crash the kernel.
630 637
638config GPTMR0_CLOCKSOURCE
639 bool "Use GPTimer0 as a clocksource (higher rating)"
640 depends on GENERIC_CLOCKEVENTS
641 depends on !TICKSOURCE_GPTMR0
642
631source kernel/time/Kconfig 643source kernel/time/Kconfig
632 644
633comment "Misc" 645comment "Misc"
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
index ddc43ce38533..589e937ed1eb 100644
--- a/arch/blackfin/include/asm/time.h
+++ b/arch/blackfin/include/asm/time.h
@@ -37,4 +37,5 @@ extern unsigned long long __bfin_cycles_off;
37extern unsigned int __bfin_cycles_mod; 37extern unsigned int __bfin_cycles_mod;
38#endif 38#endif
39 39
40extern void __init setup_core_timer(void);
40#endif 41#endif
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index 27646121280a..0791eba40d9f 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -20,8 +20,9 @@
20 20
21#include <asm/blackfin.h> 21#include <asm/blackfin.h>
22#include <asm/time.h> 22#include <asm/time.h>
23#include <asm/gptimers.h>
23 24
24#ifdef CONFIG_CYCLES_CLOCKSOURCE 25#if defined(CONFIG_CYCLES_CLOCKSOURCE)
25 26
26/* Accelerators for sched_clock() 27/* Accelerators for sched_clock()
27 * convert from cycles(64bits) => nanoseconds (64bits) 28 * convert from cycles(64bits) => nanoseconds (64bits)
@@ -58,15 +59,15 @@ static inline unsigned long long cycles_2_ns(cycle_t cyc)
58 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; 59 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
59} 60}
60 61
61static cycle_t read_cycles(struct clocksource *cs) 62static cycle_t bfin_read_cycles(struct clocksource *cs)
62{ 63{
63 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); 64 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
64} 65}
65 66
66static struct clocksource clocksource_bfin = { 67static struct clocksource bfin_cs_cycles = {
67 .name = "bfin_cycles", 68 .name = "bfin_cs_cycles",
68 .rating = 350, 69 .rating = 350,
69 .read = read_cycles, 70 .read = bfin_read_cycles,
70 .mask = CLOCKSOURCE_MASK(64), 71 .mask = CLOCKSOURCE_MASK(64),
71 .shift = 22, 72 .shift = 22,
72 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 73 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
@@ -74,53 +75,198 @@ static struct clocksource clocksource_bfin = {
74 75
75unsigned long long sched_clock(void) 76unsigned long long sched_clock(void)
76{ 77{
77 return cycles_2_ns(read_cycles(&clocksource_bfin)); 78 return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles));
78} 79}
79 80
80static int __init bfin_clocksource_init(void) 81static int __init bfin_cs_cycles_init(void)
81{ 82{
82 set_cyc2ns_scale(get_cclk() / 1000); 83 set_cyc2ns_scale(get_cclk() / 1000);
83 84
84 clocksource_bfin.mult = clocksource_hz2mult(get_cclk(), clocksource_bfin.shift); 85 bfin_cs_cycles.mult = \
86 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
85 87
86 if (clocksource_register(&clocksource_bfin)) 88 if (clocksource_register(&bfin_cs_cycles))
87 panic("failed to register clocksource"); 89 panic("failed to register clocksource");
88 90
89 return 0; 91 return 0;
90} 92}
93#else
94# define bfin_cs_cycles_init()
95#endif
96
97#ifdef CONFIG_GPTMR0_CLOCKSOURCE
98
99void __init setup_gptimer0(void)
100{
101 disable_gptimers(TIMER0bit);
102
103 set_gptimer_config(TIMER0_id, \
104 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
105 set_gptimer_period(TIMER0_id, -1);
106 set_gptimer_pwidth(TIMER0_id, -2);
107 SSYNC();
108 enable_gptimers(TIMER0bit);
109}
110
111static cycle_t bfin_read_gptimer0(void)
112{
113 return bfin_read_TIMER0_COUNTER();
114}
115
116static struct clocksource bfin_cs_gptimer0 = {
117 .name = "bfin_cs_gptimer0",
118 .rating = 400,
119 .read = bfin_read_gptimer0,
120 .mask = CLOCKSOURCE_MASK(32),
121 .shift = 22,
122 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
123};
124
125static int __init bfin_cs_gptimer0_init(void)
126{
127 setup_gptimer0();
91 128
129 bfin_cs_gptimer0.mult = \
130 clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
131
132 if (clocksource_register(&bfin_cs_gptimer0))
133 panic("failed to register clocksource");
134
135 return 0;
136}
92#else 137#else
93# define bfin_clocksource_init() 138# define bfin_cs_gptimer0_init()
94#endif 139#endif
95 140
141#ifdef CONFIG_CORE_TIMER_IRQ_L1
142__attribute__((l1_text))
143#endif
144irqreturn_t timer_interrupt(int irq, void *dev_id);
145
146static int bfin_timer_set_next_event(unsigned long, \
147 struct clock_event_device *);
148
149static void bfin_timer_set_mode(enum clock_event_mode, \
150 struct clock_event_device *);
151
152static struct clock_event_device clockevent_bfin = {
153#if defined(CONFIG_TICKSOURCE_GPTMR0)
154 .name = "bfin_gptimer0",
155 .rating = 300,
156 .irq = IRQ_TIMER0,
157#else
158 .name = "bfin_core_timer",
159 .rating = 350,
160 .irq = IRQ_CORETMR,
161#endif
162 .shift = 32,
163 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
164 .set_next_event = bfin_timer_set_next_event,
165 .set_mode = bfin_timer_set_mode,
166};
167
168static struct irqaction bfin_timer_irq = {
169#if defined(CONFIG_TICKSOURCE_GPTMR0)
170 .name = "Blackfin GPTimer0",
171#else
172 .name = "Blackfin CoreTimer",
173#endif
174 .flags = IRQF_DISABLED | IRQF_TIMER | \
175 IRQF_IRQPOLL | IRQF_PERCPU,
176 .handler = timer_interrupt,
177 .dev_id = &clockevent_bfin,
178};
179
180#if defined(CONFIG_TICKSOURCE_GPTMR0)
96static int bfin_timer_set_next_event(unsigned long cycles, 181static int bfin_timer_set_next_event(unsigned long cycles,
97 struct clock_event_device *evt) 182 struct clock_event_device *evt)
98{ 183{
184 disable_gptimers(TIMER0bit);
185
186 /* it starts counting three SCLK cycles after the TIMENx bit is set */
187 set_gptimer_pwidth(TIMER0_id, cycles - 3);
188 enable_gptimers(TIMER0bit);
189 return 0;
190}
191
192static void bfin_timer_set_mode(enum clock_event_mode mode,
193 struct clock_event_device *evt)
194{
195 switch (mode) {
196 case CLOCK_EVT_MODE_PERIODIC: {
197 set_gptimer_config(TIMER0_id, \
198 TIMER_OUT_DIS | TIMER_IRQ_ENA | \
199 TIMER_PERIOD_CNT | TIMER_MODE_PWM);
200 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
201 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
202 enable_gptimers(TIMER0bit);
203 break;
204 }
205 case CLOCK_EVT_MODE_ONESHOT:
206 disable_gptimers(TIMER0bit);
207 set_gptimer_config(TIMER0_id, \
208 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
209 set_gptimer_period(TIMER0_id, 0);
210 break;
211 case CLOCK_EVT_MODE_UNUSED:
212 case CLOCK_EVT_MODE_SHUTDOWN:
213 disable_gptimers(TIMER0bit);
214 break;
215 case CLOCK_EVT_MODE_RESUME:
216 break;
217 }
218}
219
220static void bfin_timer_ack(void)
221{
222 set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
223}
224
225static void __init bfin_timer_init(void)
226{
227 disable_gptimers(TIMER0bit);
228}
229
230static unsigned long __init bfin_clockevent_check(void)
231{
232 setup_irq(IRQ_TIMER0, &bfin_timer_irq);
233 return get_sclk();
234}
235
236#else /* CONFIG_TICKSOURCE_CORETMR */
237
238static int bfin_timer_set_next_event(unsigned long cycles,
239 struct clock_event_device *evt)
240{
241 bfin_write_TCNTL(TMPWR);
242 CSYNC();
99 bfin_write_TCOUNT(cycles); 243 bfin_write_TCOUNT(cycles);
100 CSYNC(); 244 CSYNC();
245 bfin_write_TCNTL(TMPWR | TMREN);
101 return 0; 246 return 0;
102} 247}
103 248
104static void bfin_timer_set_mode(enum clock_event_mode mode, 249static void bfin_timer_set_mode(enum clock_event_mode mode,
105 struct clock_event_device *evt) 250 struct clock_event_device *evt)
106{ 251{
107 switch (mode) { 252 switch (mode) {
108 case CLOCK_EVT_MODE_PERIODIC: { 253 case CLOCK_EVT_MODE_PERIODIC: {
109 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); 254 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
110 bfin_write_TCNTL(TMPWR); 255 bfin_write_TCNTL(TMPWR);
111 bfin_write_TSCALE(TIME_SCALE - 1);
112 CSYNC(); 256 CSYNC();
257 bfin_write_TSCALE(TIME_SCALE - 1);
113 bfin_write_TPERIOD(tcount); 258 bfin_write_TPERIOD(tcount);
114 bfin_write_TCOUNT(tcount); 259 bfin_write_TCOUNT(tcount);
115 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
116 CSYNC(); 260 CSYNC();
261 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
117 break; 262 break;
118 } 263 }
119 case CLOCK_EVT_MODE_ONESHOT: 264 case CLOCK_EVT_MODE_ONESHOT:
265 bfin_write_TCNTL(TMPWR);
266 CSYNC();
120 bfin_write_TSCALE(TIME_SCALE - 1); 267 bfin_write_TSCALE(TIME_SCALE - 1);
268 bfin_write_TPERIOD(0);
121 bfin_write_TCOUNT(0); 269 bfin_write_TCOUNT(0);
122 bfin_write_TCNTL(TMPWR | TMREN);
123 CSYNC();
124 break; 270 break;
125 case CLOCK_EVT_MODE_UNUSED: 271 case CLOCK_EVT_MODE_UNUSED:
126 case CLOCK_EVT_MODE_SHUTDOWN: 272 case CLOCK_EVT_MODE_SHUTDOWN:
@@ -132,6 +278,10 @@ static void bfin_timer_set_mode(enum clock_event_mode mode,
132 } 278 }
133} 279}
134 280
281static void bfin_timer_ack(void)
282{
283}
284
135static void __init bfin_timer_init(void) 285static void __init bfin_timer_init(void)
136{ 286{
137 /* power up the timer, but don't enable it just yet */ 287 /* power up the timer, but don't enable it just yet */
@@ -145,38 +295,32 @@ static void __init bfin_timer_init(void)
145 bfin_write_TPERIOD(0); 295 bfin_write_TPERIOD(0);
146 bfin_write_TCOUNT(0); 296 bfin_write_TCOUNT(0);
147 297
148 /* now enable the timer */
149 CSYNC(); 298 CSYNC();
150} 299}
151 300
301static unsigned long __init bfin_clockevent_check(void)
302{
303 setup_irq(IRQ_CORETMR, &bfin_timer_irq);
304 return get_cclk() / TIME_SCALE;
305}
306
307void __init setup_core_timer(void)
308{
309 bfin_timer_init();
310 bfin_timer_set_mode(CLOCK_EVT_MODE_PERIODIC, NULL);
311}
312#endif /* CONFIG_TICKSOURCE_GPTMR0 */
313
152/* 314/*
153 * timer_interrupt() needs to keep up the real-time clock, 315 * timer_interrupt() needs to keep up the real-time clock,
154 * as well as call the "do_timer()" routine every clocktick 316 * as well as call the "do_timer()" routine every clocktick
155 */ 317 */
156#ifdef CONFIG_CORE_TIMER_IRQ_L1
157__attribute__((l1_text))
158#endif
159irqreturn_t timer_interrupt(int irq, void *dev_id);
160
161static struct clock_event_device clockevent_bfin = {
162 .name = "bfin_core_timer",
163 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
164 .shift = 32,
165 .set_next_event = bfin_timer_set_next_event,
166 .set_mode = bfin_timer_set_mode,
167};
168
169static struct irqaction bfin_timer_irq = {
170 .name = "Blackfin Core Timer",
171 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
172 .handler = timer_interrupt,
173 .dev_id = &clockevent_bfin,
174};
175
176irqreturn_t timer_interrupt(int irq, void *dev_id) 318irqreturn_t timer_interrupt(int irq, void *dev_id)
177{ 319{
178 struct clock_event_device *evt = dev_id; 320 struct clock_event_device *evt = dev_id;
321 smp_mb();
179 evt->event_handler(evt); 322 evt->event_handler(evt);
323 bfin_timer_ack();
180 return IRQ_HANDLED; 324 return IRQ_HANDLED;
181} 325}
182 326
@@ -184,9 +328,8 @@ static int __init bfin_clockevent_init(void)
184{ 328{
185 unsigned long timer_clk; 329 unsigned long timer_clk;
186 330
187 timer_clk = get_cclk() / TIME_SCALE; 331 timer_clk = bfin_clockevent_check();
188 332
189 setup_irq(IRQ_CORETMR, &bfin_timer_irq);
190 bfin_timer_init(); 333 bfin_timer_init();
191 334
192 clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift); 335 clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift);
@@ -218,6 +361,7 @@ void __init time_init(void)
218 xtime.tv_nsec = 0; 361 xtime.tv_nsec = 0;
219 set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); 362 set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
220 363
221 bfin_clocksource_init(); 364 bfin_cs_cycles_init();
365 bfin_cs_gptimer0_init();
222 bfin_clockevent_init(); 366 bfin_clockevent_init();
223} 367}
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 1bbacfbd4c5d..daa02d45f03d 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -31,7 +31,7 @@ static struct irqaction bfin_timer_irq = {
31#endif 31#endif
32}; 32};
33 33
34#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 34#if defined(CONFIG_TICKSOURCE_GPTMR0) || defined(CONFIG_IPIPE)
35void __init setup_system_timer0(void) 35void __init setup_system_timer0(void)
36{ 36{
37 /* Power down the core timer, just to play safe. */ 37 /* Power down the core timer, just to play safe. */
@@ -74,7 +74,7 @@ void __init setup_core_timer(void)
74static void __init 74static void __init
75time_sched_init(irqreturn_t(*timer_routine) (int, void *)) 75time_sched_init(irqreturn_t(*timer_routine) (int, void *))
76{ 76{
77#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 77#if defined(CONFIG_TICKSOURCE_GPTMR0) || defined(CONFIG_IPIPE)
78 setup_system_timer0(); 78 setup_system_timer0();
79 bfin_timer_irq.handler = timer_routine; 79 bfin_timer_irq.handler = timer_routine;
80 setup_irq(IRQ_TIMER0, &bfin_timer_irq); 80 setup_irq(IRQ_TIMER0, &bfin_timer_irq);
@@ -94,7 +94,7 @@ static unsigned long gettimeoffset(void)
94 unsigned long offset; 94 unsigned long offset;
95 unsigned long clocks_per_jiffy; 95 unsigned long clocks_per_jiffy;
96 96
97#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 97#if defined(CONFIG_TICKSOURCE_GPTMR0) || defined(CONFIG_IPIPE)
98 clocks_per_jiffy = bfin_read_TIMER0_PERIOD(); 98 clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
99 offset = bfin_read_TIMER0_COUNTER() / \ 99 offset = bfin_read_TIMER0_COUNTER() / \
100 (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); 100 (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
@@ -133,7 +133,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
133 static long last_rtc_update; 133 static long last_rtc_update;
134 134
135 write_seqlock(&xtime_lock); 135 write_seqlock(&xtime_lock);
136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) 136#if defined(CONFIG_TICKSOURCE_GPTMR0) && !defined(CONFIG_IPIPE)
137 /* 137 /*
138 * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is 138 * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is
139 * enabled. 139 * enabled.
@@ -159,7 +159,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
159 /* Do it again in 60s. */ 159 /* Do it again in 60s. */
160 last_rtc_update = xtime.tv_sec - 600; 160 last_rtc_update = xtime.tv_sec - 600;
161 } 161 }
162#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) 162#if defined(CONFIG_TICKSOURCE_GPTMR0) && !defined(CONFIG_IPIPE)
163 set_gptimer_status(0, TIMER_STATUS_TIMIL0); 163 set_gptimer_status(0, TIMER_STATUS_TIMIL0);
164 } 164 }
165#endif 165#endif
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index f397ede006bf..4c76fefb7a3b 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -156,6 +156,7 @@ config IRQ_PORTH_INTB
156 default 11 156 default 11
157config IRQ_TIMER0 157config IRQ_TIMER0
158 int "IRQ_TIMER0" 158 int "IRQ_TIMER0"
159 default 7 if TICKSOURCE_GPTMR0
159 default 8 160 default 8
160config IRQ_TIMER1 161config IRQ_TIMER1
161 int "IRQ_TIMER1" 162 int "IRQ_TIMER1"
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 8438ec6d6679..848ac6f86823 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -170,6 +170,7 @@ config IRQ_PORTH_INTB
170 default 11 170 default 11
171config IRQ_TIMER0 171config IRQ_TIMER0
172 int "IRQ_TIMER0" 172 int "IRQ_TIMER0"
173 default 7 if TICKSOURCE_GPTMR0
173 default 8 174 default 8
174config IRQ_TIMER1 175config IRQ_TIMER1
175 int "IRQ_TIMER1" 176 int "IRQ_TIMER1"
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
index 14427de7d77f..4c572443147e 100644
--- a/arch/blackfin/mach-bf533/Kconfig
+++ b/arch/blackfin/mach-bf533/Kconfig
@@ -59,6 +59,7 @@ config DMA7_UARTTX
59 default 10 59 default 10
60config TIMER0 60config TIMER0
61 int "TIMER0" 61 int "TIMER0"
62 default 7 if TICKSOURCE_GPTMR0
62 default 8 63 default 8
63config TIMER1 64config TIMER1
64 int "TIMER1" 65 int "TIMER1"
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index bbc08fd4f122..d81224f9d723 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -66,6 +66,7 @@ config IRQ_MAC_TX
66 default 11 66 default 11
67config IRQ_TIMER0 67config IRQ_TIMER0
68 int "IRQ_TIMER0" 68 int "IRQ_TIMER0"
69 default 7 if TICKSOURCE_GPTMR0
69 default 8 70 default 8
70config IRQ_TIMER1 71config IRQ_TIMER1
71 int "IRQ_TIMER1" 72 int "IRQ_TIMER1"
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig
index f068c3523cdc..2d280f504ab0 100644
--- a/arch/blackfin/mach-bf538/Kconfig
+++ b/arch/blackfin/mach-bf538/Kconfig
@@ -57,6 +57,7 @@ config IRQ_UART0_TX
57 default 10 57 default 10
58config IRQ_TIMER0 58config IRQ_TIMER0
59 int "IRQ_TIMER0" 59 int "IRQ_TIMER0"
60 default 7 if TICKSOURCE_GPTMR0
60 default 8 61 default 8
61config IRQ_TIMER1 62config IRQ_TIMER1
62 int "IRQ_TIMER1" 63 int "IRQ_TIMER1"
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 8d24eaabe589..a09623dfd550 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -257,6 +257,7 @@ config IRQ_OTPSEC
257 default 11 257 default 11
258config IRQ_TIMER0 258config IRQ_TIMER0
259 int "IRQ_TIMER0" 259 int "IRQ_TIMER0"
260 default 7 if TICKSOURCE_GPTMR0
260 default 8 261 default 8
261config IRQ_TIMER1 262config IRQ_TIMER1
262 int "IRQ_TIMER1" 263 int "IRQ_TIMER1"
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
index 6965dd59af4c..cb9743641511 100644
--- a/arch/blackfin/mach-bf561/Kconfig
+++ b/arch/blackfin/mach-bf561/Kconfig
@@ -125,6 +125,7 @@ config IRQ_DMA2_11
125 default 9 125 default 9
126config IRQ_TIMER0 126config IRQ_TIMER0
127 int "TIMER 0 Interrupt" 127 int "TIMER 0 Interrupt"
128 default 7 if TICKSOURCE_GPTMR0
128 default 8 129 default 8
129config IRQ_TIMER1 130config IRQ_TIMER1
130 int "TIMER 1 Interrupt" 131 int "TIMER 1 Interrupt"
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 4ea13d2eb872..8c10701c251f 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -133,7 +133,7 @@ void __init platform_request_ipi(irq_handler_t handler)
133 int ret; 133 int ret;
134 134
135 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, 135 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
136 "SMP interrupt", handler); 136 "Supplemental Interrupt0", handler);
137 if (ret) 137 if (ret)
138 panic("Cannot request supplemental interrupt 0 for IPI service"); 138 panic("Cannot request supplemental interrupt 0 for IPI service");
139} 139}
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 389c5e8aa456..6e808612d170 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1052,7 +1052,7 @@ int __init init_arch_irq(void)
1052 set_irq_chained_handler(irq, bfin_demux_error_irq); 1052 set_irq_chained_handler(irq, bfin_demux_error_irq);
1053 break; 1053 break;
1054#endif 1054#endif
1055#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 1055#if defined(CONFIG_TICKSOURCE_GPTMR0)
1056 case IRQ_TIMER0: 1056 case IRQ_TIMER0:
1057 set_irq_handler(irq, handle_percpu_irq); 1057 set_irq_handler(irq, handle_percpu_irq);
1058 break; 1058 break;
@@ -1232,13 +1232,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1232 1232
1233 if (likely(vec == EVT_IVTMR_P)) { 1233 if (likely(vec == EVT_IVTMR_P)) {
1234 irq = IRQ_CORETMR; 1234 irq = IRQ_CORETMR;
1235 goto core_tick;
1236 }
1237
1238 SSYNC();
1239 1235
1236 } else {
1240#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 1237#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1241 {
1242 unsigned long sic_status[3]; 1238 unsigned long sic_status[3];
1243 1239
1244 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1240 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
@@ -1254,9 +1250,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1254 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) 1250 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1255 break; 1251 break;
1256 } 1252 }
1257 }
1258#else 1253#else
1259 {
1260 unsigned long sic_status; 1254 unsigned long sic_status;
1261 1255
1262 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 1256 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
@@ -1268,15 +1262,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1268 } else if (sic_status & ivg->isrflag) 1262 } else if (sic_status & ivg->isrflag)
1269 break; 1263 break;
1270 } 1264 }
1271 }
1272#endif 1265#endif
1273 1266
1274 irq = ivg->irqno; 1267 irq = ivg->irqno;
1268 }
1275 1269
1276 if (irq == IRQ_SYSTMR) { 1270 if (irq == IRQ_SYSTMR) {
1277#ifdef CONFIG_GENERIC_CLOCKEVENTS 1271#ifndef CONFIG_GENERIC_CLOCKEVENTS
1278core_tick:
1279#else
1280 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ 1272 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1281#endif 1273#endif
1282 /* This is basically what we need from the register frame. */ 1274 /* This is basically what we need from the register frame. */
@@ -1288,9 +1280,6 @@ core_tick:
1288 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; 1280 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1289 } 1281 }
1290 1282
1291#ifndef CONFIG_GENERIC_CLOCKEVENTS
1292core_tick:
1293#endif
1294 if (this_domain == ipipe_root_domain) { 1283 if (this_domain == ipipe_root_domain) {
1295 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); 1284 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1296 barrier(); 1285 barrier();
@@ -1308,7 +1297,7 @@ core_tick:
1308 } 1297 }
1309 } 1298 }
1310 1299
1311 return 0; 1300 return 0;
1312} 1301}
1313 1302
1314#endif /* CONFIG_IPIPE */ 1303#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 187c79e585a1..b6695957b065 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -43,6 +43,7 @@
43#include <asm/processor.h> 43#include <asm/processor.h>
44#include <asm/ptrace.h> 44#include <asm/ptrace.h>
45#include <asm/cpu.h> 45#include <asm/cpu.h>
46#include <asm/time.h>
46#include <linux/err.h> 47#include <linux/err.h>
47 48
48/* 49/*
@@ -356,7 +357,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
356 357
357static void __cpuinit setup_secondary(unsigned int cpu) 358static void __cpuinit setup_secondary(unsigned int cpu)
358{ 359{
359#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)) 360#if !defined(CONFIG_TICKSOURCE_GPTMR0)
360 struct irq_desc *timer_desc; 361 struct irq_desc *timer_desc;
361#endif 362#endif
362 unsigned long ilat; 363 unsigned long ilat;
@@ -377,7 +378,7 @@ static void __cpuinit setup_secondary(unsigned int cpu)
377 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 378 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
378 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 379 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
379 380
380#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 381#if defined(CONFIG_TICKSOURCE_GPTMR0)
381 /* Power down the core timer, just to play safe. */ 382 /* Power down the core timer, just to play safe. */
382 bfin_write_TCNTL(0); 383 bfin_write_TCNTL(0);
383 384
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 04:42:46 -0500