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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/mach-gemini/Makefile2
-rw-r--r--arch/arm/mach-gemini/common.h1
-rw-r--r--arch/arm/mach-gemini/gpio.c232
-rw-r--r--arch/arm/mach-gemini/include/mach/gpio.h25
-rw-r--r--arch/arm/mach-gemini/include/mach/irqs.h5
6 files changed, 265 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5686f4074dd0..5b0204083e0e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -278,6 +278,8 @@ config ARCH_EP93XX
278config ARCH_GEMINI 278config ARCH_GEMINI
279 bool "Cortina Systems Gemini" 279 bool "Cortina Systems Gemini"
280 select CPU_FA526 280 select CPU_FA526
281 select GENERIC_GPIO
282 select ARCH_REQUIRE_GPIOLIB
281 help 283 help
282 Support for the Cortina Systems Gemini family SoCs 284 Support for the Cortina Systems Gemini family SoCs
283 285
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index 133e2050685e..e2835cdb0d24 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -4,4 +4,4 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := irq.o mm.o time.o devices.o 7obj-y := irq.o mm.o time.o devices.o gpio.o
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
index 9c1afa1c5803..9392834a214f 100644
--- a/arch/arm/mach-gemini/common.h
+++ b/arch/arm/mach-gemini/common.h
@@ -17,6 +17,7 @@ struct mtd_partition;
17extern void gemini_map_io(void); 17extern void gemini_map_io(void);
18extern void gemini_init_irq(void); 18extern void gemini_init_irq(void);
19extern void gemini_timer_init(void); 19extern void gemini_timer_init(void);
20extern void gemini_gpio_init(void);
20 21
21/* Common platform devices registration functions */ 22/* Common platform devices registration functions */
22extern int platform_register_uart(void); 23extern int platform_register_uart(void);
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
new file mode 100644
index 000000000000..e7263854bc7b
--- /dev/null
+++ b/arch/arm/mach-gemini/gpio.c
@@ -0,0 +1,232 @@
1/*
2 * Gemini gpiochip and interrupt routines
3 *
4 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * Based on plat-mxc/gpio.c:
7 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
8 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/gpio.h>
21
22#include <mach/hardware.h>
23#include <mach/irqs.h>
24
25#define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
26
27/* GPIO registers definition */
28#define GPIO_DATA_OUT 0x0
29#define GPIO_DATA_IN 0x4
30#define GPIO_DIR 0x8
31#define GPIO_DATA_SET 0x10
32#define GPIO_DATA_CLR 0x14
33#define GPIO_PULL_EN 0x18
34#define GPIO_PULL_TYPE 0x1C
35#define GPIO_INT_EN 0x20
36#define GPIO_INT_STAT 0x24
37#define GPIO_INT_MASK 0x2C
38#define GPIO_INT_CLR 0x30
39#define GPIO_INT_TYPE 0x34
40#define GPIO_INT_BOTH_EDGE 0x38
41#define GPIO_INT_LEVEL 0x3C
42#define GPIO_DEBOUNCE_EN 0x40
43#define GPIO_DEBOUNCE_PRESCALE 0x44
44
45#define GPIO_PORT_NUM 3
46
47static void _set_gpio_irqenable(unsigned int base, unsigned int index,
48 int enable)
49{
50 unsigned int reg;
51
52 reg = __raw_readl(base + GPIO_INT_EN);
53 reg = (reg & (~(1 << index))) | (!!enable << index);
54 __raw_writel(reg, base + GPIO_INT_EN);
55}
56
57static void gpio_ack_irq(unsigned int irq)
58{
59 unsigned int gpio = irq_to_gpio(irq);
60 unsigned int base = GPIO_BASE(gpio / 32);
61
62 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
63}
64
65static void gpio_mask_irq(unsigned int irq)
66{
67 unsigned int gpio = irq_to_gpio(irq);
68 unsigned int base = GPIO_BASE(gpio / 32);
69
70 _set_gpio_irqenable(base, gpio % 32, 0);
71}
72
73static void gpio_unmask_irq(unsigned int irq)
74{
75 unsigned int gpio = irq_to_gpio(irq);
76 unsigned int base = GPIO_BASE(gpio / 32);
77
78 _set_gpio_irqenable(base, gpio % 32, 1);
79}
80
81static int gpio_set_irq_type(unsigned int irq, unsigned int type)
82{
83 unsigned int gpio = irq_to_gpio(irq);
84 unsigned int gpio_mask = 1 << (gpio % 32);
85 unsigned int base = GPIO_BASE(gpio / 32);
86 unsigned int reg_both, reg_level, reg_type;
87
88 reg_type = __raw_readl(base + GPIO_INT_TYPE);
89 reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE);
90 reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
91
92 switch (type) {
93 case IRQ_TYPE_EDGE_BOTH:
94 reg_type &= ~gpio_mask;
95 reg_both |= gpio_mask;
96 break;
97 case IRQ_TYPE_EDGE_RISING:
98 reg_type &= ~gpio_mask;
99 reg_both &= ~gpio_mask;
100 reg_level &= ~gpio_mask;
101 break;
102 case IRQ_TYPE_EDGE_FALLING:
103 reg_type &= ~gpio_mask;
104 reg_both &= ~gpio_mask;
105 reg_level |= gpio_mask;
106 break;
107 case IRQ_TYPE_LEVEL_HIGH:
108 reg_type |= gpio_mask;
109 reg_level &= ~gpio_mask;
110 break;
111 case IRQ_TYPE_LEVEL_LOW:
112 reg_type |= gpio_mask;
113 reg_level |= gpio_mask;
114 break;
115 default:
116 return -EINVAL;
117 }
118
119 __raw_writel(reg_type, base + GPIO_INT_TYPE);
120 __raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE);
121 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
122
123 gpio_ack_irq(irq);
124
125 return 0;
126}
127
128static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
129{
130 unsigned int gpio_irq_no, irq_stat;
131 unsigned int port = (unsigned int)get_irq_data(irq);
132
133 irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
134
135 gpio_irq_no = GPIO_IRQ_BASE + port * 32;
136 for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
137
138 if ((irq_stat & 1) == 0)
139 continue;
140
141 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
142 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
143 &irq_desc[gpio_irq_no]);
144 }
145}
146
147static struct irq_chip gpio_irq_chip = {
148 .name = "GPIO",
149 .ack = gpio_ack_irq,
150 .mask = gpio_mask_irq,
151 .unmask = gpio_unmask_irq,
152 .set_type = gpio_set_irq_type,
153};
154
155static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
156 int dir)
157{
158 unsigned int base = GPIO_BASE(offset / 32);
159 unsigned int reg;
160
161 reg = __raw_readl(base + GPIO_DIR);
162 if (dir)
163 reg |= 1 << (offset % 32);
164 else
165 reg &= ~(1 << (offset % 32));
166 __raw_writel(reg, base + GPIO_DIR);
167}
168
169static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
170{
171 unsigned int base = GPIO_BASE(offset / 32);
172
173 if (value)
174 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
175 else
176 __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR);
177}
178
179static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
180{
181 unsigned int base = GPIO_BASE(offset / 32);
182
183 return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
184}
185
186static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
187{
188 _set_gpio_direction(chip, offset, 0);
189 return 0;
190}
191
192static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
193 int value)
194{
195 _set_gpio_direction(chip, offset, 1);
196 gemini_gpio_set(chip, offset, value);
197 return 0;
198}
199
200static struct gpio_chip gemini_gpio_chip = {
201 .label = "Gemini",
202 .direction_input = gemini_gpio_direction_input,
203 .get = gemini_gpio_get,
204 .direction_output = gemini_gpio_direction_output,
205 .set = gemini_gpio_set,
206 .base = 0,
207 .ngpio = GPIO_PORT_NUM * 32,
208};
209
210void __init gemini_gpio_init(void)
211{
212 int i, j;
213
214 for (i = 0; i < GPIO_PORT_NUM; i++) {
215 /* disable, unmask and clear all interrupts */
216 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN);
217 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK);
218 __raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR);
219
220 for (j = GPIO_IRQ_BASE + i * 32;
221 j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
222 set_irq_chip(j, &gpio_irq_chip);
223 set_irq_handler(j, handle_edge_irq);
224 set_irq_flags(j, IRQF_VALID);
225 }
226
227 set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
228 set_irq_data(IRQ_GPIO(i), (void *)i);
229 }
230
231 BUG_ON(gpiochip_add(&gemini_gpio_chip));
232}
diff --git a/arch/arm/mach-gemini/include/mach/gpio.h b/arch/arm/mach-gemini/include/mach/gpio.h
new file mode 100644
index 000000000000..3bc2c70f2989
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/gpio.h
@@ -0,0 +1,25 @@
1/*
2 * Gemini gpiolib specific defines
3 *
4 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __MACH_GPIO_H__
13#define __MACH_GPIO_H__
14
15#include <mach/irqs.h>
16#include <asm-generic/gpio.h>
17
18#define gpio_get_value __gpio_get_value
19#define gpio_set_value __gpio_set_value
20#define gpio_cansleep __gpio_cansleep
21
22#define gpio_to_irq(x) ((x) + GPIO_IRQ_BASE)
23#define irq_to_gpio(x) ((x) - GPIO_IRQ_BASE)
24
25#endif /* __MACH_GPIO_H__ */
diff --git a/arch/arm/mach-gemini/include/mach/irqs.h b/arch/arm/mach-gemini/include/mach/irqs.h
index c7728ac458f3..06bc47e77e8b 100644
--- a/arch/arm/mach-gemini/include/mach/irqs.h
+++ b/arch/arm/mach-gemini/include/mach/irqs.h
@@ -43,8 +43,11 @@
43 43
44#define NORMAL_IRQ_NUM 32 44#define NORMAL_IRQ_NUM 32
45 45
46#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
47#define GPIO_IRQ_NUM (3 * 32)
48
46#define ARCH_TIMER_IRQ IRQ_TIMER2 49#define ARCH_TIMER_IRQ IRQ_TIMER2
47 50
48#define NR_IRQS NORMAL_IRQ_NUM 51#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
49 52
50#endif /* __MACH_IRQS_H__ */ 53#endif /* __MACH_IRQS_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 11:10:37 -0500