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-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt259
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi73
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi34
4 files changed, 69 insertions, 306 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index a2ac2d9ac71a..f5a5b19ed3b2 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -15,259 +15,12 @@ Required Properties:
15 15
16- #clock-cells: should be 1. 16- #clock-cells: should be 1.
17 17
18The following is the list of clocks generated by the controller. Each clock is 18Each clock is assigned an identifier and client nodes can use this identifier
19assigned an identifier and client nodes use this identifier to specify the 19to specify the clock which they consume.
20clock which they consume. Some of the clocks are available only on a particular
21Exynos4 SoC and this is specified where applicable.
22
23
24 [Core Clocks]
25
26 Clock ID SoC (if specific)
27 -----------------------------------------------
28
29 xxti 1
30 xusbxti 2
31 fin_pll 3
32 fout_apll 4
33 fout_mpll 5
34 fout_epll 6
35 fout_vpll 7
36 sclk_apll 8
37 sclk_mpll 9
38 sclk_epll 10
39 sclk_vpll 11
40 arm_clk 12
41 aclk200 13
42 aclk100 14
43 aclk160 15
44 aclk133 16
45 mout_mpll_user_t 17 Exynos4x12
46 mout_mpll_user_c 18 Exynos4x12
47 mout_core 19
48 mout_apll 20
49
50
51 [Clock Gate for Special Clocks]
52
53 Clock ID SoC (if specific)
54 -----------------------------------------------
55
56 sclk_fimc0 128
57 sclk_fimc1 129
58 sclk_fimc2 130
59 sclk_fimc3 131
60 sclk_cam0 132
61 sclk_cam1 133
62 sclk_csis0 134
63 sclk_csis1 135
64 sclk_hdmi 136
65 sclk_mixer 137
66 sclk_dac 138
67 sclk_pixel 139
68 sclk_fimd0 140
69 sclk_mdnie0 141 Exynos4412
70 sclk_mdnie_pwm0 12 142 Exynos4412
71 sclk_mipi0 143
72 sclk_audio0 144
73 sclk_mmc0 145
74 sclk_mmc1 146
75 sclk_mmc2 147
76 sclk_mmc3 148
77 sclk_mmc4 149
78 sclk_sata 150 Exynos4210
79 sclk_uart0 151
80 sclk_uart1 152
81 sclk_uart2 153
82 sclk_uart3 154
83 sclk_uart4 155
84 sclk_audio1 156
85 sclk_audio2 157
86 sclk_spdif 158
87 sclk_spi0 159
88 sclk_spi1 160
89 sclk_spi2 161
90 sclk_slimbus 162
91 sclk_fimd1 163 Exynos4210
92 sclk_mipi1 164 Exynos4210
93 sclk_pcm1 165
94 sclk_pcm2 166
95 sclk_i2s1 167
96 sclk_i2s2 168
97 sclk_mipihsi 169 Exynos4412
98 sclk_mfc 170
99 sclk_pcm0 171
100 sclk_g3d 172
101 sclk_pwm_isp 173 Exynos4x12
102 sclk_spi0_isp 174 Exynos4x12
103 sclk_spi1_isp 175 Exynos4x12
104 sclk_uart_isp 176 Exynos4x12
105 sclk_fimg2d 177
106
107 [Peripheral Clock Gates]
108
109 Clock ID SoC (if specific)
110 -----------------------------------------------
111
112 fimc0 256
113 fimc1 257
114 fimc2 258
115 fimc3 259
116 csis0 260
117 csis1 261
118 jpeg 262
119 smmu_fimc0 263
120 smmu_fimc1 264
121 smmu_fimc2 265
122 smmu_fimc3 266
123 smmu_jpeg 267
124 vp 268
125 mixer 269
126 tvenc 270 Exynos4210
127 hdmi 271
128 smmu_tv 272
129 mfc 273
130 smmu_mfcl 274
131 smmu_mfcr 275
132 g3d 276
133 g2d 277
134 rotator 278 Exynos4210
135 mdma 279 Exynos4210
136 smmu_g2d 280 Exynos4210
137 smmu_rotator 281 Exynos4210
138 smmu_mdma 282 Exynos4210
139 fimd0 283
140 mie0 284
141 mdnie0 285 Exynos4412
142 dsim0 286
143 smmu_fimd0 287
144 fimd1 288 Exynos4210
145 mie1 289 Exynos4210
146 dsim1 290 Exynos4210
147 smmu_fimd1 291 Exynos4210
148 pdma0 292
149 pdma1 293
150 pcie_phy 294
151 sata_phy 295 Exynos4210
152 tsi 296
153 sdmmc0 297
154 sdmmc1 298
155 sdmmc2 299
156 sdmmc3 300
157 sdmmc4 301
158 sata 302 Exynos4210
159 sromc 303
160 usb_host 304
161 usb_device 305
162 pcie 306
163 onenand 307
164 nfcon 308
165 smmu_pcie 309
166 gps 310
167 smmu_gps 311
168 uart0 312
169 uart1 313
170 uart2 314
171 uart3 315
172 uart4 316
173 i2c0 317
174 i2c1 318
175 i2c2 319
176 i2c3 320
177 i2c4 321
178 i2c5 322
179 i2c6 323
180 i2c7 324
181 i2c_hdmi 325
182 tsadc 326
183 spi0 327
184 spi1 328
185 spi2 329
186 i2s1 330
187 i2s2 331
188 pcm0 332
189 i2s0 333
190 pcm1 334
191 pcm2 335
192 pwm 336
193 slimbus 337
194 spdif 338
195 ac97 339
196 modemif 340
197 chipid 341
198 sysreg 342
199 hdmi_cec 343
200 mct 344
201 wdt 345
202 rtc 346
203 keyif 347
204 audss 348
205 mipi_hsi 349 Exynos4210
206 mdma2 350 Exynos4210
207 pixelasyncm0 351
208 pixelasyncm1 352
209 fimc_lite0 353 Exynos4x12
210 fimc_lite1 354 Exynos4x12
211 ppmuispx 355 Exynos4x12
212 ppmuispmx 356 Exynos4x12
213 fimc_isp 357 Exynos4x12
214 fimc_drc 358 Exynos4x12
215 fimc_fd 359 Exynos4x12
216 mcuisp 360 Exynos4x12
217 gicisp 361 Exynos4x12
218 smmu_isp 362 Exynos4x12
219 smmu_drc 363 Exynos4x12
220 smmu_fd 364 Exynos4x12
221 smmu_lite0 365 Exynos4x12
222 smmu_lite1 366 Exynos4x12
223 mcuctl_isp 367 Exynos4x12
224 mpwm_isp 368 Exynos4x12
225 i2c0_isp 369 Exynos4x12
226 i2c1_isp 370 Exynos4x12
227 mtcadc_isp 371 Exynos4x12
228 pwm_isp 372 Exynos4x12
229 wdt_isp 373 Exynos4x12
230 uart_isp 374 Exynos4x12
231 asyncaxim 375 Exynos4x12
232 smmu_ispcx 376 Exynos4x12
233 spi0_isp 377 Exynos4x12
234 spi1_isp 378 Exynos4x12
235 pwm_isp_sclk 379 Exynos4x12
236 spi0_isp_sclk 380 Exynos4x12
237 spi1_isp_sclk 381 Exynos4x12
238 uart_isp_sclk 382 Exynos4x12
239 tmu_apbif 383
240
241 [Mux Clocks]
242
243 Clock ID SoC (if specific)
244 -----------------------------------------------
245
246 mout_fimc0 384
247 mout_fimc1 385
248 mout_fimc2 386
249 mout_fimc3 387
250 mout_cam0 388
251 mout_cam1 389
252 mout_csis0 390
253 mout_csis1 391
254 mout_g3d0 392
255 mout_g3d1 393
256 mout_g3d 394
257 aclk400_mcuisp 395 Exynos4x12
258
259 [Div Clocks]
260
261 Clock ID SoC (if specific)
262 -----------------------------------------------
263
264 div_isp0 450 Exynos4x12
265 div_isp1 451 Exynos4x12
266 div_mcuisp0 452 Exynos4x12
267 div_mcuisp1 453 Exynos4x12
268 div_aclk200 454 Exynos4x12
269 div_aclk400_mcuisp 455 Exynos4x12
270 20
21All available clocks are defined as preprocessor macros in
22dt-bindings/clock/exynos4.h header and can be used in device
23tree sources.
271 24
272Example 1: An example of a clock controller node is listed below. 25Example 1: An example of a clock controller node is listed below.
273 26
@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
285 compatible = "samsung,exynos4210-uart"; 38 compatible = "samsung,exynos4210-uart";
286 reg = <0x13820000 0x100>; 39 reg = <0x13820000 0x100>;
287 interrupts = <0 54 0>; 40 interrupts = <0 54 0>;
288 clocks = <&clock 314>, <&clock 153>; 41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
289 clock-names = "uart", "clk_uart_baud0"; 42 clock-names = "uart", "clk_uart_baud0";
290 }; 43 };
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 08452e183b57..28b5ec79f339 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,6 +19,7 @@
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 */ 20 */
21 21
22#include <dt-bindings/clock/exynos4.h>
22#include "skeleton.dtsi" 23#include "skeleton.dtsi"
23 24
24/ { 25/ {
@@ -119,7 +120,7 @@
119 compatible = "samsung,exynos4210-fimc"; 120 compatible = "samsung,exynos4210-fimc";
120 reg = <0x11800000 0x1000>; 121 reg = <0x11800000 0x1000>;
121 interrupts = <0 84 0>; 122 interrupts = <0 84 0>;
122 clocks = <&clock 256>, <&clock 128>; 123 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
123 clock-names = "fimc", "sclk_fimc"; 124 clock-names = "fimc", "sclk_fimc";
124 samsung,power-domain = <&pd_cam>; 125 samsung,power-domain = <&pd_cam>;
125 samsung,sysreg = <&sys_reg>; 126 samsung,sysreg = <&sys_reg>;
@@ -130,7 +131,7 @@
130 compatible = "samsung,exynos4210-fimc"; 131 compatible = "samsung,exynos4210-fimc";
131 reg = <0x11810000 0x1000>; 132 reg = <0x11810000 0x1000>;
132 interrupts = <0 85 0>; 133 interrupts = <0 85 0>;
133 clocks = <&clock 257>, <&clock 129>; 134 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
134 clock-names = "fimc", "sclk_fimc"; 135 clock-names = "fimc", "sclk_fimc";
135 samsung,power-domain = <&pd_cam>; 136 samsung,power-domain = <&pd_cam>;
136 samsung,sysreg = <&sys_reg>; 137 samsung,sysreg = <&sys_reg>;
@@ -141,7 +142,7 @@
141 compatible = "samsung,exynos4210-fimc"; 142 compatible = "samsung,exynos4210-fimc";
142 reg = <0x11820000 0x1000>; 143 reg = <0x11820000 0x1000>;
143 interrupts = <0 86 0>; 144 interrupts = <0 86 0>;
144 clocks = <&clock 258>, <&clock 130>; 145 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
145 clock-names = "fimc", "sclk_fimc"; 146 clock-names = "fimc", "sclk_fimc";
146 samsung,power-domain = <&pd_cam>; 147 samsung,power-domain = <&pd_cam>;
147 samsung,sysreg = <&sys_reg>; 148 samsung,sysreg = <&sys_reg>;
@@ -152,7 +153,7 @@
152 compatible = "samsung,exynos4210-fimc"; 153 compatible = "samsung,exynos4210-fimc";
153 reg = <0x11830000 0x1000>; 154 reg = <0x11830000 0x1000>;
154 interrupts = <0 87 0>; 155 interrupts = <0 87 0>;
155 clocks = <&clock 259>, <&clock 131>; 156 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
156 clock-names = "fimc", "sclk_fimc"; 157 clock-names = "fimc", "sclk_fimc";
157 samsung,power-domain = <&pd_cam>; 158 samsung,power-domain = <&pd_cam>;
158 samsung,sysreg = <&sys_reg>; 159 samsung,sysreg = <&sys_reg>;
@@ -163,7 +164,7 @@
163 compatible = "samsung,exynos4210-csis"; 164 compatible = "samsung,exynos4210-csis";
164 reg = <0x11880000 0x4000>; 165 reg = <0x11880000 0x4000>;
165 interrupts = <0 78 0>; 166 interrupts = <0 78 0>;
166 clocks = <&clock 260>, <&clock 134>; 167 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
167 clock-names = "csis", "sclk_csis"; 168 clock-names = "csis", "sclk_csis";
168 bus-width = <4>; 169 bus-width = <4>;
169 samsung,power-domain = <&pd_cam>; 170 samsung,power-domain = <&pd_cam>;
@@ -178,7 +179,7 @@
178 compatible = "samsung,exynos4210-csis"; 179 compatible = "samsung,exynos4210-csis";
179 reg = <0x11890000 0x4000>; 180 reg = <0x11890000 0x4000>;
180 interrupts = <0 80 0>; 181 interrupts = <0 80 0>;
181 clocks = <&clock 261>, <&clock 135>; 182 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
182 clock-names = "csis", "sclk_csis"; 183 clock-names = "csis", "sclk_csis";
183 bus-width = <2>; 184 bus-width = <2>;
184 samsung,power-domain = <&pd_cam>; 185 samsung,power-domain = <&pd_cam>;
@@ -194,7 +195,7 @@
194 compatible = "samsung,s3c2410-wdt"; 195 compatible = "samsung,s3c2410-wdt";
195 reg = <0x10060000 0x100>; 196 reg = <0x10060000 0x100>;
196 interrupts = <0 43 0>; 197 interrupts = <0 43 0>;
197 clocks = <&clock 345>; 198 clocks = <&clock CLK_WDT>;
198 clock-names = "watchdog"; 199 clock-names = "watchdog";
199 status = "disabled"; 200 status = "disabled";
200 }; 201 };
@@ -203,7 +204,7 @@
203 compatible = "samsung,s3c6410-rtc"; 204 compatible = "samsung,s3c6410-rtc";
204 reg = <0x10070000 0x100>; 205 reg = <0x10070000 0x100>;
205 interrupts = <0 44 0>, <0 45 0>; 206 interrupts = <0 44 0>, <0 45 0>;
206 clocks = <&clock 346>; 207 clocks = <&clock CLK_RTC>;
207 clock-names = "rtc"; 208 clock-names = "rtc";
208 status = "disabled"; 209 status = "disabled";
209 }; 210 };
@@ -212,7 +213,7 @@
212 compatible = "samsung,s5pv210-keypad"; 213 compatible = "samsung,s5pv210-keypad";
213 reg = <0x100A0000 0x100>; 214 reg = <0x100A0000 0x100>;
214 interrupts = <0 109 0>; 215 interrupts = <0 109 0>;
215 clocks = <&clock 347>; 216 clocks = <&clock CLK_KEYIF>;
216 clock-names = "keypad"; 217 clock-names = "keypad";
217 status = "disabled"; 218 status = "disabled";
218 }; 219 };
@@ -221,7 +222,7 @@
221 compatible = "samsung,exynos4210-sdhci"; 222 compatible = "samsung,exynos4210-sdhci";
222 reg = <0x12510000 0x100>; 223 reg = <0x12510000 0x100>;
223 interrupts = <0 73 0>; 224 interrupts = <0 73 0>;
224 clocks = <&clock 297>, <&clock 145>; 225 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
225 clock-names = "hsmmc", "mmc_busclk.2"; 226 clock-names = "hsmmc", "mmc_busclk.2";
226 status = "disabled"; 227 status = "disabled";
227 }; 228 };
@@ -230,7 +231,7 @@
230 compatible = "samsung,exynos4210-sdhci"; 231 compatible = "samsung,exynos4210-sdhci";
231 reg = <0x12520000 0x100>; 232 reg = <0x12520000 0x100>;
232 interrupts = <0 74 0>; 233 interrupts = <0 74 0>;
233 clocks = <&clock 298>, <&clock 146>; 234 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
234 clock-names = "hsmmc", "mmc_busclk.2"; 235 clock-names = "hsmmc", "mmc_busclk.2";
235 status = "disabled"; 236 status = "disabled";
236 }; 237 };
@@ -239,7 +240,7 @@
239 compatible = "samsung,exynos4210-sdhci"; 240 compatible = "samsung,exynos4210-sdhci";
240 reg = <0x12530000 0x100>; 241 reg = <0x12530000 0x100>;
241 interrupts = <0 75 0>; 242 interrupts = <0 75 0>;
242 clocks = <&clock 299>, <&clock 147>; 243 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
243 clock-names = "hsmmc", "mmc_busclk.2"; 244 clock-names = "hsmmc", "mmc_busclk.2";
244 status = "disabled"; 245 status = "disabled";
245 }; 246 };
@@ -248,7 +249,7 @@
248 compatible = "samsung,exynos4210-sdhci"; 249 compatible = "samsung,exynos4210-sdhci";
249 reg = <0x12540000 0x100>; 250 reg = <0x12540000 0x100>;
250 interrupts = <0 76 0>; 251 interrupts = <0 76 0>;
251 clocks = <&clock 300>, <&clock 148>; 252 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
252 clock-names = "hsmmc", "mmc_busclk.2"; 253 clock-names = "hsmmc", "mmc_busclk.2";
253 status = "disabled"; 254 status = "disabled";
254 }; 255 };
@@ -257,7 +258,7 @@
257 compatible = "samsung,exynos4210-ehci"; 258 compatible = "samsung,exynos4210-ehci";
258 reg = <0x12580000 0x100>; 259 reg = <0x12580000 0x100>;
259 interrupts = <0 70 0>; 260 interrupts = <0 70 0>;
260 clocks = <&clock 304>; 261 clocks = <&clock CLK_USB_HOST>;
261 clock-names = "usbhost"; 262 clock-names = "usbhost";
262 status = "disabled"; 263 status = "disabled";
263 }; 264 };
@@ -266,7 +267,7 @@
266 compatible = "samsung,exynos4210-ohci"; 267 compatible = "samsung,exynos4210-ohci";
267 reg = <0x12590000 0x100>; 268 reg = <0x12590000 0x100>;
268 interrupts = <0 70 0>; 269 interrupts = <0 70 0>;
269 clocks = <&clock 304>; 270 clocks = <&clock CLK_USB_HOST>;
270 clock-names = "usbhost"; 271 clock-names = "usbhost";
271 status = "disabled"; 272 status = "disabled";
272 }; 273 };
@@ -276,7 +277,7 @@
276 reg = <0x13400000 0x10000>; 277 reg = <0x13400000 0x10000>;
277 interrupts = <0 94 0>; 278 interrupts = <0 94 0>;
278 samsung,power-domain = <&pd_mfc>; 279 samsung,power-domain = <&pd_mfc>;
279 clocks = <&clock 273>; 280 clocks = <&clock CLK_MFC>;
280 clock-names = "mfc"; 281 clock-names = "mfc";
281 status = "disabled"; 282 status = "disabled";
282 }; 283 };
@@ -285,7 +286,7 @@
285 compatible = "samsung,exynos4210-uart"; 286 compatible = "samsung,exynos4210-uart";
286 reg = <0x13800000 0x100>; 287 reg = <0x13800000 0x100>;
287 interrupts = <0 52 0>; 288 interrupts = <0 52 0>;
288 clocks = <&clock 312>, <&clock 151>; 289 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
289 clock-names = "uart", "clk_uart_baud0"; 290 clock-names = "uart", "clk_uart_baud0";
290 status = "disabled"; 291 status = "disabled";
291 }; 292 };
@@ -294,7 +295,7 @@
294 compatible = "samsung,exynos4210-uart"; 295 compatible = "samsung,exynos4210-uart";
295 reg = <0x13810000 0x100>; 296 reg = <0x13810000 0x100>;
296 interrupts = <0 53 0>; 297 interrupts = <0 53 0>;
297 clocks = <&clock 313>, <&clock 152>; 298 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
298 clock-names = "uart", "clk_uart_baud0"; 299 clock-names = "uart", "clk_uart_baud0";
299 status = "disabled"; 300 status = "disabled";
300 }; 301 };
@@ -303,7 +304,7 @@
303 compatible = "samsung,exynos4210-uart"; 304 compatible = "samsung,exynos4210-uart";
304 reg = <0x13820000 0x100>; 305 reg = <0x13820000 0x100>;
305 interrupts = <0 54 0>; 306 interrupts = <0 54 0>;
306 clocks = <&clock 314>, <&clock 153>; 307 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
307 clock-names = "uart", "clk_uart_baud0"; 308 clock-names = "uart", "clk_uart_baud0";
308 status = "disabled"; 309 status = "disabled";
309 }; 310 };
@@ -312,7 +313,7 @@
312 compatible = "samsung,exynos4210-uart"; 313 compatible = "samsung,exynos4210-uart";
313 reg = <0x13830000 0x100>; 314 reg = <0x13830000 0x100>;
314 interrupts = <0 55 0>; 315 interrupts = <0 55 0>;
315 clocks = <&clock 315>, <&clock 154>; 316 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
316 clock-names = "uart", "clk_uart_baud0"; 317 clock-names = "uart", "clk_uart_baud0";
317 status = "disabled"; 318 status = "disabled";
318 }; 319 };
@@ -323,7 +324,7 @@
323 compatible = "samsung,s3c2440-i2c"; 324 compatible = "samsung,s3c2440-i2c";
324 reg = <0x13860000 0x100>; 325 reg = <0x13860000 0x100>;
325 interrupts = <0 58 0>; 326 interrupts = <0 58 0>;
326 clocks = <&clock 317>; 327 clocks = <&clock CLK_I2C0>;
327 clock-names = "i2c"; 328 clock-names = "i2c";
328 pinctrl-names = "default"; 329 pinctrl-names = "default";
329 pinctrl-0 = <&i2c0_bus>; 330 pinctrl-0 = <&i2c0_bus>;
@@ -336,7 +337,7 @@
336 compatible = "samsung,s3c2440-i2c"; 337 compatible = "samsung,s3c2440-i2c";
337 reg = <0x13870000 0x100>; 338 reg = <0x13870000 0x100>;
338 interrupts = <0 59 0>; 339 interrupts = <0 59 0>;
339 clocks = <&clock 318>; 340 clocks = <&clock CLK_I2C1>;
340 clock-names = "i2c"; 341 clock-names = "i2c";
341 pinctrl-names = "default"; 342 pinctrl-names = "default";
342 pinctrl-0 = <&i2c1_bus>; 343 pinctrl-0 = <&i2c1_bus>;
@@ -349,7 +350,7 @@
349 compatible = "samsung,s3c2440-i2c"; 350 compatible = "samsung,s3c2440-i2c";
350 reg = <0x13880000 0x100>; 351 reg = <0x13880000 0x100>;
351 interrupts = <0 60 0>; 352 interrupts = <0 60 0>;
352 clocks = <&clock 319>; 353 clocks = <&clock CLK_I2C2>;
353 clock-names = "i2c"; 354 clock-names = "i2c";
354 status = "disabled"; 355 status = "disabled";
355 }; 356 };
@@ -360,7 +361,7 @@
360 compatible = "samsung,s3c2440-i2c"; 361 compatible = "samsung,s3c2440-i2c";
361 reg = <0x13890000 0x100>; 362 reg = <0x13890000 0x100>;
362 interrupts = <0 61 0>; 363 interrupts = <0 61 0>;
363 clocks = <&clock 320>; 364 clocks = <&clock CLK_I2C3>;
364 clock-names = "i2c"; 365 clock-names = "i2c";
365 status = "disabled"; 366 status = "disabled";
366 }; 367 };
@@ -371,7 +372,7 @@
371 compatible = "samsung,s3c2440-i2c"; 372 compatible = "samsung,s3c2440-i2c";
372 reg = <0x138A0000 0x100>; 373 reg = <0x138A0000 0x100>;
373 interrupts = <0 62 0>; 374 interrupts = <0 62 0>;
374 clocks = <&clock 321>; 375 clocks = <&clock CLK_I2C4>;
375 clock-names = "i2c"; 376 clock-names = "i2c";
376 status = "disabled"; 377 status = "disabled";
377 }; 378 };
@@ -382,7 +383,7 @@
382 compatible = "samsung,s3c2440-i2c"; 383 compatible = "samsung,s3c2440-i2c";
383 reg = <0x138B0000 0x100>; 384 reg = <0x138B0000 0x100>;
384 interrupts = <0 63 0>; 385 interrupts = <0 63 0>;
385 clocks = <&clock 322>; 386 clocks = <&clock CLK_I2C5>;
386 clock-names = "i2c"; 387 clock-names = "i2c";
387 status = "disabled"; 388 status = "disabled";
388 }; 389 };
@@ -393,7 +394,7 @@
393 compatible = "samsung,s3c2440-i2c"; 394 compatible = "samsung,s3c2440-i2c";
394 reg = <0x138C0000 0x100>; 395 reg = <0x138C0000 0x100>;
395 interrupts = <0 64 0>; 396 interrupts = <0 64 0>;
396 clocks = <&clock 323>; 397 clocks = <&clock CLK_I2C6>;
397 clock-names = "i2c"; 398 clock-names = "i2c";
398 status = "disabled"; 399 status = "disabled";
399 }; 400 };
@@ -404,7 +405,7 @@
404 compatible = "samsung,s3c2440-i2c"; 405 compatible = "samsung,s3c2440-i2c";
405 reg = <0x138D0000 0x100>; 406 reg = <0x138D0000 0x100>;
406 interrupts = <0 65 0>; 407 interrupts = <0 65 0>;
407 clocks = <&clock 324>; 408 clocks = <&clock CLK_I2C7>;
408 clock-names = "i2c"; 409 clock-names = "i2c";
409 status = "disabled"; 410 status = "disabled";
410 }; 411 };
@@ -417,7 +418,7 @@
417 dma-names = "tx", "rx"; 418 dma-names = "tx", "rx";
418 #address-cells = <1>; 419 #address-cells = <1>;
419 #size-cells = <0>; 420 #size-cells = <0>;
420 clocks = <&clock 327>, <&clock 159>; 421 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
421 clock-names = "spi", "spi_busclk0"; 422 clock-names = "spi", "spi_busclk0";
422 pinctrl-names = "default"; 423 pinctrl-names = "default";
423 pinctrl-0 = <&spi0_bus>; 424 pinctrl-0 = <&spi0_bus>;
@@ -432,7 +433,7 @@
432 dma-names = "tx", "rx"; 433 dma-names = "tx", "rx";
433 #address-cells = <1>; 434 #address-cells = <1>;
434 #size-cells = <0>; 435 #size-cells = <0>;
435 clocks = <&clock 328>, <&clock 160>; 436 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
436 clock-names = "spi", "spi_busclk0"; 437 clock-names = "spi", "spi_busclk0";
437 pinctrl-names = "default"; 438 pinctrl-names = "default";
438 pinctrl-0 = <&spi1_bus>; 439 pinctrl-0 = <&spi1_bus>;
@@ -447,7 +448,7 @@
447 dma-names = "tx", "rx"; 448 dma-names = "tx", "rx";
448 #address-cells = <1>; 449 #address-cells = <1>;
449 #size-cells = <0>; 450 #size-cells = <0>;
450 clocks = <&clock 329>, <&clock 161>; 451 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
451 clock-names = "spi", "spi_busclk0"; 452 clock-names = "spi", "spi_busclk0";
452 pinctrl-names = "default"; 453 pinctrl-names = "default";
453 pinctrl-0 = <&spi2_bus>; 454 pinctrl-0 = <&spi2_bus>;
@@ -458,7 +459,7 @@
458 compatible = "samsung,exynos4210-pwm"; 459 compatible = "samsung,exynos4210-pwm";
459 reg = <0x139D0000 0x1000>; 460 reg = <0x139D0000 0x1000>;
460 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 461 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
461 clocks = <&clock 336>; 462 clocks = <&clock CLK_PWM>;
462 clock-names = "timers"; 463 clock-names = "timers";
463 #pwm-cells = <2>; 464 #pwm-cells = <2>;
464 status = "disabled"; 465 status = "disabled";
@@ -475,7 +476,7 @@
475 compatible = "arm,pl330", "arm,primecell"; 476 compatible = "arm,pl330", "arm,primecell";
476 reg = <0x12680000 0x1000>; 477 reg = <0x12680000 0x1000>;
477 interrupts = <0 35 0>; 478 interrupts = <0 35 0>;
478 clocks = <&clock 292>; 479 clocks = <&clock CLK_PDMA0>;
479 clock-names = "apb_pclk"; 480 clock-names = "apb_pclk";
480 #dma-cells = <1>; 481 #dma-cells = <1>;
481 #dma-channels = <8>; 482 #dma-channels = <8>;
@@ -486,7 +487,7 @@
486 compatible = "arm,pl330", "arm,primecell"; 487 compatible = "arm,pl330", "arm,primecell";
487 reg = <0x12690000 0x1000>; 488 reg = <0x12690000 0x1000>;
488 interrupts = <0 36 0>; 489 interrupts = <0 36 0>;
489 clocks = <&clock 293>; 490 clocks = <&clock CLK_PDMA1>;
490 clock-names = "apb_pclk"; 491 clock-names = "apb_pclk";
491 #dma-cells = <1>; 492 #dma-cells = <1>;
492 #dma-channels = <8>; 493 #dma-channels = <8>;
@@ -497,7 +498,7 @@
497 compatible = "arm,pl330", "arm,primecell"; 498 compatible = "arm,pl330", "arm,primecell";
498 reg = <0x12850000 0x1000>; 499 reg = <0x12850000 0x1000>;
499 interrupts = <0 34 0>; 500 interrupts = <0 34 0>;
500 clocks = <&clock 279>; 501 clocks = <&clock CLK_MDMA>;
501 clock-names = "apb_pclk"; 502 clock-names = "apb_pclk";
502 #dma-cells = <1>; 503 #dma-cells = <1>;
503 #dma-channels = <8>; 504 #dma-channels = <8>;
@@ -511,7 +512,7 @@
511 reg = <0x11c00000 0x20000>; 512 reg = <0x11c00000 0x20000>;
512 interrupt-names = "fifo", "vsync", "lcd_sys"; 513 interrupt-names = "fifo", "vsync", "lcd_sys";
513 interrupts = <11 0>, <11 1>, <11 2>; 514 interrupts = <11 0>, <11 1>, <11 2>;
514 clocks = <&clock 140>, <&clock 283>; 515 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
515 clock-names = "sclk_fimd", "fimd"; 516 clock-names = "sclk_fimd", "fimd";
516 samsung,power-domain = <&pd_lcd0>; 517 samsung,power-domain = <&pd_lcd0>;
517 status = "disabled"; 518 status = "disabled";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 48ecd7a755ab..cb0e768dc6d4 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -53,7 +53,7 @@
53 reg = <0x10050000 0x800>; 53 reg = <0x10050000 0x800>;
54 interrupt-parent = <&mct_map>; 54 interrupt-parent = <&mct_map>;
55 interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 55 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
56 clocks = <&clock 3>, <&clock 344>; 56 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
57 clock-names = "fin_pll", "mct"; 57 clock-names = "fin_pll", "mct";
58 58
59 mct_map: mct-map { 59 mct_map: mct-map {
@@ -109,7 +109,7 @@
109 interrupt-parent = <&combiner>; 109 interrupt-parent = <&combiner>;
110 reg = <0x100C0000 0x100>; 110 reg = <0x100C0000 0x100>;
111 interrupts = <2 4>; 111 interrupts = <2 4>;
112 clocks = <&clock 383>; 112 clocks = <&clock CLK_TMU_APBIF>;
113 clock-names = "tmu_apbif"; 113 clock-names = "tmu_apbif";
114 status = "disabled"; 114 status = "disabled";
115 }; 115 };
@@ -118,13 +118,14 @@
118 compatible = "samsung,s5pv210-g2d"; 118 compatible = "samsung,s5pv210-g2d";
119 reg = <0x12800000 0x1000>; 119 reg = <0x12800000 0x1000>;
120 interrupts = <0 89 0>; 120 interrupts = <0 89 0>;
121 clocks = <&clock 177>, <&clock 277>; 121 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
122 clock-names = "sclk_fimg2d", "fimg2d"; 122 clock-names = "sclk_fimg2d", "fimg2d";
123 status = "disabled"; 123 status = "disabled";
124 }; 124 };
125 125
126 camera { 126 camera {
127 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; 127 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
128 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
128 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 129 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
129 130
130 fimc_0: fimc@11800000 { 131 fimc_0: fimc@11800000 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 5c412aa14738..e0eb6bb64c34 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -47,7 +47,7 @@
47 reg = <0x10050000 0x800>; 47 reg = <0x10050000 0x800>;
48 interrupt-parent = <&mct_map>; 48 interrupt-parent = <&mct_map>;
49 interrupts = <0>, <1>, <2>, <3>, <4>; 49 interrupts = <0>, <1>, <2>, <3>, <4>;
50 clocks = <&clock 3>, <&clock 344>; 50 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
51 clock-names = "fin_pll", "mct"; 51 clock-names = "fin_pll", "mct";
52 52
53 mct_map: mct-map { 53 mct_map: mct-map {
@@ -97,13 +97,14 @@
97 compatible = "samsung,exynos4212-g2d"; 97 compatible = "samsung,exynos4212-g2d";
98 reg = <0x10800000 0x1000>; 98 reg = <0x10800000 0x1000>;
99 interrupts = <0 89 0>; 99 interrupts = <0 89 0>;
100 clocks = <&clock 177>, <&clock 277>; 100 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
101 clock-names = "sclk_fimg2d", "fimg2d"; 101 clock-names = "sclk_fimg2d", "fimg2d";
102 status = "disabled"; 102 status = "disabled";
103 }; 103 };
104 104
105 camera { 105 camera {
106 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; 106 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
107 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
107 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 108 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
108 109
109 fimc_0: fimc@11800000 { 110 fimc_0: fimc@11800000 {
@@ -145,7 +146,7 @@
145 reg = <0x12390000 0x1000>; 146 reg = <0x12390000 0x1000>;
146 interrupts = <0 105 0>; 147 interrupts = <0 105 0>;
147 samsung,power-domain = <&pd_isp>; 148 samsung,power-domain = <&pd_isp>;
148 clocks = <&clock 353>; 149 clocks = <&clock CLK_FIMC_LITE0>;
149 clock-names = "flite"; 150 clock-names = "flite";
150 status = "disabled"; 151 status = "disabled";
151 }; 152 };
@@ -155,7 +156,7 @@
155 reg = <0x123A0000 0x1000>; 156 reg = <0x123A0000 0x1000>;
156 interrupts = <0 106 0>; 157 interrupts = <0 106 0>;
157 samsung,power-domain = <&pd_isp>; 158 samsung,power-domain = <&pd_isp>;
158 clocks = <&clock 354>; 159 clocks = <&clock CLK_FIMC_LITE1>;
159 clock-names = "flite"; 160 clock-names = "flite";
160 status = "disabled"; 161 status = "disabled";
161 }; 162 };
@@ -165,12 +166,19 @@
165 reg = <0x12000000 0x260000>; 166 reg = <0x12000000 0x260000>;
166 interrupts = <0 90 0>, <0 95 0>; 167 interrupts = <0 90 0>, <0 95 0>;
167 samsung,power-domain = <&pd_isp>; 168 samsung,power-domain = <&pd_isp>;
168 clocks = <&clock 353>, <&clock 354>, <&clock 355>, 169 clocks = <&clock CLK_FIMC_LITE0>,
169 <&clock 356>, <&clock 17>, <&clock 357>, 170 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
170 <&clock 358>, <&clock 359>, <&clock 360>, 171 <&clock CLK_PPMUISPMX>,
171 <&clock 450>,<&clock 451>, <&clock 452>, 172 <&clock CLK_MOUT_MPLL_USER_T>,
172 <&clock 453>, <&clock 176>, <&clock 13>, 173 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
173 <&clock 454>, <&clock 395>, <&clock 455>; 174 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
175 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
176 <&clock CLK_DIV_MCUISP0>,
177 <&clock CLK_DIV_MCUISP1>,
178 <&clock CLK_SCLK_UART_ISP>,
179 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
180 <&clock CLK_ACLK400_MCUISP>,
181 <&clock CLK_DIV_ACLK400_MCUISP>;
174 clock-names = "lite0", "lite1", "ppmuispx", 182 clock-names = "lite0", "lite1", "ppmuispx",
175 "ppmuispmx", "mpll", "isp", 183 "ppmuispmx", "mpll", "isp",
176 "drc", "fd", "mcuisp", 184 "drc", "fd", "mcuisp",
@@ -190,7 +198,7 @@
190 i2c1_isp: i2c-isp@12140000 { 198 i2c1_isp: i2c-isp@12140000 {
191 compatible = "samsung,exynos4212-i2c-isp"; 199 compatible = "samsung,exynos4212-i2c-isp";
192 reg = <0x12140000 0x100>; 200 reg = <0x12140000 0x100>;
193 clocks = <&clock 370>; 201 clocks = <&clock CLK_I2C1_ISP>;
194 clock-names = "i2c_isp"; 202 clock-names = "i2c_isp";
195 #address-cells = <1>; 203 #address-cells = <1>;
196 #size-cells = <0>; 204 #size-cells = <0>;
@@ -205,7 +213,7 @@
205 #address-cells = <1>; 213 #address-cells = <1>;
206 #size-cells = <0>; 214 #size-cells = <0>;
207 fifo-depth = <0x80>; 215 fifo-depth = <0x80>;
208 clocks = <&clock 301>, <&clock 149>; 216 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
209 clock-names = "biu", "ciu"; 217 clock-names = "biu", "ciu";
210 status = "disabled"; 218 status = "disabled";
211 }; 219 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 17:18:52 -0500