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-rw-r--r--drivers/clk/tegra/clk-tegra30.c1298
1 files changed, 403 insertions, 895 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c75db196728c..f7ebf2bacdd9 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -23,8 +23,9 @@
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/clk/tegra.h> 24#include <linux/clk/tegra.h>
25#include <linux/tegra-powergate.h> 25#include <linux/tegra-powergate.h>
26 26#include <dt-bindings/clock/tegra30-car.h>
27#include "clk.h" 27#include "clk.h"
28#include "clk-id.h"
28 29
29#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
30#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 31#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
@@ -100,88 +101,20 @@
100#define AUDIO_SYNC_CLK_I2S4 0x4b0 101#define AUDIO_SYNC_CLK_I2S4 0x4b0
101#define AUDIO_SYNC_CLK_SPDIF 0x4b4 102#define AUDIO_SYNC_CLK_SPDIF 0x4b4
102 103
103#define PMC_CLK_OUT_CNTRL 0x1a8
104
105#define CLK_SOURCE_I2S0 0x1d8
106#define CLK_SOURCE_I2S1 0x100
107#define CLK_SOURCE_I2S2 0x104
108#define CLK_SOURCE_I2S3 0x3bc
109#define CLK_SOURCE_I2S4 0x3c0
110#define CLK_SOURCE_SPDIF_OUT 0x108 104#define CLK_SOURCE_SPDIF_OUT 0x108
111#define CLK_SOURCE_SPDIF_IN 0x10c
112#define CLK_SOURCE_PWM 0x110
113#define CLK_SOURCE_D_AUDIO 0x3d0 105#define CLK_SOURCE_D_AUDIO 0x3d0
114#define CLK_SOURCE_DAM0 0x3d8 106#define CLK_SOURCE_DAM0 0x3d8
115#define CLK_SOURCE_DAM1 0x3dc 107#define CLK_SOURCE_DAM1 0x3dc
116#define CLK_SOURCE_DAM2 0x3e0 108#define CLK_SOURCE_DAM2 0x3e0
117#define CLK_SOURCE_HDA 0x428
118#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
119#define CLK_SOURCE_SBC1 0x134
120#define CLK_SOURCE_SBC2 0x118
121#define CLK_SOURCE_SBC3 0x11c
122#define CLK_SOURCE_SBC4 0x1b4
123#define CLK_SOURCE_SBC5 0x3c8
124#define CLK_SOURCE_SBC6 0x3cc
125#define CLK_SOURCE_SATA_OOB 0x420
126#define CLK_SOURCE_SATA 0x424
127#define CLK_SOURCE_NDFLASH 0x160
128#define CLK_SOURCE_NDSPEED 0x3f8
129#define CLK_SOURCE_VFIR 0x168
130#define CLK_SOURCE_SDMMC1 0x150
131#define CLK_SOURCE_SDMMC2 0x154
132#define CLK_SOURCE_SDMMC3 0x1bc
133#define CLK_SOURCE_SDMMC4 0x164
134#define CLK_SOURCE_VDE 0x1c8
135#define CLK_SOURCE_CSITE 0x1d4
136#define CLK_SOURCE_LA 0x1f8
137#define CLK_SOURCE_OWR 0x1cc
138#define CLK_SOURCE_NOR 0x1d0
139#define CLK_SOURCE_MIPI 0x174
140#define CLK_SOURCE_I2C1 0x124
141#define CLK_SOURCE_I2C2 0x198
142#define CLK_SOURCE_I2C3 0x1b8
143#define CLK_SOURCE_I2C4 0x3c4
144#define CLK_SOURCE_I2C5 0x128
145#define CLK_SOURCE_UARTA 0x178
146#define CLK_SOURCE_UARTB 0x17c
147#define CLK_SOURCE_UARTC 0x1a0
148#define CLK_SOURCE_UARTD 0x1c0
149#define CLK_SOURCE_UARTE 0x1c4
150#define CLK_SOURCE_VI 0x148
151#define CLK_SOURCE_VI_SENSOR 0x1a8
152#define CLK_SOURCE_3D 0x158
153#define CLK_SOURCE_3D2 0x3b0 109#define CLK_SOURCE_3D2 0x3b0
154#define CLK_SOURCE_2D 0x15c 110#define CLK_SOURCE_2D 0x15c
155#define CLK_SOURCE_EPP 0x16c
156#define CLK_SOURCE_MPE 0x170
157#define CLK_SOURCE_HOST1X 0x180
158#define CLK_SOURCE_CVE 0x140
159#define CLK_SOURCE_TVO 0x188
160#define CLK_SOURCE_DTV 0x1dc
161#define CLK_SOURCE_HDMI 0x18c 111#define CLK_SOURCE_HDMI 0x18c
162#define CLK_SOURCE_TVDAC 0x194
163#define CLK_SOURCE_DISP1 0x138
164#define CLK_SOURCE_DISP2 0x13c
165#define CLK_SOURCE_DSIB 0xd0 112#define CLK_SOURCE_DSIB 0xd0
166#define CLK_SOURCE_TSENSOR 0x3b8
167#define CLK_SOURCE_ACTMON 0x3e8
168#define CLK_SOURCE_EXTERN1 0x3ec
169#define CLK_SOURCE_EXTERN2 0x3f0
170#define CLK_SOURCE_EXTERN3 0x3f4
171#define CLK_SOURCE_I2CSLOW 0x3fc
172#define CLK_SOURCE_SE 0x42c 113#define CLK_SOURCE_SE 0x42c
173#define CLK_SOURCE_MSELECT 0x3b4
174#define CLK_SOURCE_EMC 0x19c 114#define CLK_SOURCE_EMC 0x19c
175 115
176#define AUDIO_SYNC_DOUBLER 0x49c 116#define AUDIO_SYNC_DOUBLER 0x49c
177 117
178#define PMC_CTRL 0
179#define PMC_CTRL_BLINK_ENB 7
180
181#define PMC_DPD_PADS_ORIDE 0x1c
182#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
183#define PMC_BLINK_TIMER 0x40
184
185#define UTMIP_PLL_CFG2 0x488 118#define UTMIP_PLL_CFG2 0x488
186#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 119#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
187#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 120#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
@@ -238,82 +171,36 @@ static void __iomem *clk_base;
238static void __iomem *pmc_base; 171static void __iomem *pmc_base;
239static unsigned long input_freq; 172static unsigned long input_freq;
240 173
241static DEFINE_SPINLOCK(clk_doubler_lock);
242static DEFINE_SPINLOCK(clk_out_lock);
243static DEFINE_SPINLOCK(pll_div_lock);
244static DEFINE_SPINLOCK(cml_lock); 174static DEFINE_SPINLOCK(cml_lock);
245static DEFINE_SPINLOCK(pll_d_lock); 175static DEFINE_SPINLOCK(pll_d_lock);
246static DEFINE_SPINLOCK(sysrate_lock);
247 176
248#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 177#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
249 _clk_num, _gate_flags, _clk_id) \ 178 _clk_num, _gate_flags, _clk_id) \
250 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 179 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
251 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 180 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
252 _clk_num, _gate_flags, _clk_id) 181 _clk_num, _gate_flags, _clk_id)
253 182
254#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 183#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
255 _clk_num, _gate_flags, _clk_id) \
256 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
257 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
258 _clk_num, \
259 _gate_flags, _clk_id)
260
261#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
262 _clk_num, _gate_flags, _clk_id) \ 184 _clk_num, _gate_flags, _clk_id) \
263 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 185 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
264 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 186 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
265 _clk_num, _gate_flags, _clk_id) 187 _clk_num, _gate_flags, _clk_id)
266 188
267#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 189#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
268 _clk_num, _gate_flags, _clk_id) \ 190 _clk_num, _gate_flags, _clk_id) \
269 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 191 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
270 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 192 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
271 TEGRA_DIVIDER_ROUND_UP, _clk_num, \ 193 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
272 _gate_flags, _clk_id) 194 _gate_flags, _clk_id)
273 195
274#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 196#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
275 _clk_num, _clk_id) \
276 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
277 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
278 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
279 0, _clk_id)
280
281#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
282 _mux_shift, _mux_width, _clk_num, \ 197 _mux_shift, _mux_width, _clk_num, \
283 _gate_flags, _clk_id) \ 198 _gate_flags, _clk_id) \
284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 199 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
285 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\ 200 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
286 _clk_num, _gate_flags, \ 201 _clk_num, _gate_flags, \
287 _clk_id) 202 _clk_id)
288 203
289/*
290 * IDs assigned here must be in sync with DT bindings definition
291 * for Tegra30 clocks.
292 */
293enum tegra30_clk {
294 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
295 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
296 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
297 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
298 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
299 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
300 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
301 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
302 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
303 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
304 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
305 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
306 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
307 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
308 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
309 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
310 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
311 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
312 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
313 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
314 hclk, pclk, clk_out_1_mux = 300, clk_max
315};
316
317static struct clk **clks; 204static struct clk **clks;
318 205
319/* 206/*
@@ -685,67 +572,295 @@ static struct tegra_clk_pll_params pll_e_params = {
685 .fixed_rate = 100000000, 572 .fixed_rate = 100000000,
686}; 573};
687 574
688static void tegra30_clk_measure_input_freq(void) 575static unsigned long tegra30_input_freq[] = {
689{ 576 [0] = 13000000,
690 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 577 [1] = 16800000,
691 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 578 [4] = 19200000,
692 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 579 [5] = 38400000,
693 580 [8] = 12000000,
694 switch (auto_clk_control) { 581 [9] = 48000000,
695 case OSC_CTRL_OSC_FREQ_12MHZ: 582 [12] = 260000000,
696 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 583};
697 input_freq = 12000000;
698 break;
699 case OSC_CTRL_OSC_FREQ_13MHZ:
700 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
701 input_freq = 13000000;
702 break;
703 case OSC_CTRL_OSC_FREQ_19_2MHZ:
704 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
705 input_freq = 19200000;
706 break;
707 case OSC_CTRL_OSC_FREQ_26MHZ:
708 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
709 input_freq = 26000000;
710 break;
711 case OSC_CTRL_OSC_FREQ_16_8MHZ:
712 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
713 input_freq = 16800000;
714 break;
715 case OSC_CTRL_OSC_FREQ_38_4MHZ:
716 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
717 input_freq = 38400000;
718 break;
719 case OSC_CTRL_OSC_FREQ_48MHZ:
720 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
721 input_freq = 48000000;
722 break;
723 default:
724 pr_err("Unexpected auto clock control value %d",
725 auto_clk_control);
726 BUG();
727 return;
728 }
729}
730 584
731static unsigned int tegra30_get_pll_ref_div(void) 585static struct tegra_devclk devclks[] __initdata = {
732{ 586 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
733 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 587 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
734 OSC_CTRL_PLL_REF_DIV_MASK; 588 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
735 589 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
736 switch (pll_ref_div) { 590 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
737 case OSC_CTRL_PLL_REF_DIV_1: 591 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
738 return 1; 592 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
739 case OSC_CTRL_PLL_REF_DIV_2: 593 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
740 return 2; 594 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
741 case OSC_CTRL_PLL_REF_DIV_4: 595 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
742 return 4; 596 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
743 default: 597 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
744 pr_err("Invalid pll ref divider %d", pll_ref_div); 598 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
745 BUG(); 599 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
746 } 600 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
747 return 0; 601 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
748} 602 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
603 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
604 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
605 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
606 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
607 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
608 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
609 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
610 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
611 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
612 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
613 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
614 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
615 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
616 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
617 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
618 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
619 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
620 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
621 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
622 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
623 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
624 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
625 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
626 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
627 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
628 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
629 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
630 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
631 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
632 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
633 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
634 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
635 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
636 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
637 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
638 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
639 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
640 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
641 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
642 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
643 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
644 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
645 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
646 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
647 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
648 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
649 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
650 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
651 { .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
652 { .con_id = "fuse", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE },
653 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
654 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
655 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
656 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
657 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
658 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
659 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
660 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
661 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
662 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
663 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
664 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
665 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
666 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
667 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
668 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
669 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
670 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
671 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
672 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
673 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
674 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
675 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
676 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
677 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
678 { .con_id = "hda2codec", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
679 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
680 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
681 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
682 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
683 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
684 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
685 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
686 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
687 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
688 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
689 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
690 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
691 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
692 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
693 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
694 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
695 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
696 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
697 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
698 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
699 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
700 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
701 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
702 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
703 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
704 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
705 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
706 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
707 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
708 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
709 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
710 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
711 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
712 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
713 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
714 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
715 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
716 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
717 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
718 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
719 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
720 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
721 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
722 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
723 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
724 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
725 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
726 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
727 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
728 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
729 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
730 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
731 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
732 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
733 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
734};
735
736static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
737 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
738 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
739 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
740 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
741 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
742 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
743 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
744 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
745 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
746 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
747 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
748 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
749 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
750 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
751 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
752 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
753 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
754 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
755 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
756 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
757 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
758 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
759 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
760 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
761 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
762 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
763 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
764 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
765 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
766 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
767 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
768 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
769 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
770 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
771 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
772 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
773 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
774 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
775 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
776 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
777 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
778 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
779 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
780 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
781 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
782 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
783 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
784 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
785 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
786 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
787 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
788 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
789 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
790 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
791 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
792 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
793 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
794 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
795 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
796 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
797 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
798 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
799 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
800 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
801 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
802 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
803 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
804 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
805 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
806 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
807 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
808 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
809 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
810 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
811 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
812 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
813 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
814 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
815 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
816 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
817 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
818 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
819 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
820 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
821 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
822 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
823 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
824 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
825 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
826 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
827 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
828 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
829 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
830 [tegra_clk_pwm] = { .dt_id = TEGRA30_CLK_PWM, .present = true },
831 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
832 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
833 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
834 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
835 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
836 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
837 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
838 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
839 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
840 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
841 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
842 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
843 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
844 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
845 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
846 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
847 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
848 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
849 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
850 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
851 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
852 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
853 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
854 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
855 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
856 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
857 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
858 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
859 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
860 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
861 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
862
863};
749 864
750static void tegra30_utmi_param_configure(void) 865static void tegra30_utmi_param_configure(void)
751{ 866{
@@ -809,8 +924,7 @@ static void __init tegra30_pll_init(void)
809 /* PLLC */ 924 /* PLLC */
810 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 925 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
811 &pll_c_params, NULL); 926 &pll_c_params, NULL);
812 clk_register_clkdev(clk, "pll_c", NULL); 927 clks[TEGRA30_CLK_PLL_C] = clk;
813 clks[pll_c] = clk;
814 928
815 /* PLLC_OUT1 */ 929 /* PLLC_OUT1 */
816 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 930 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
@@ -819,69 +933,13 @@ static void __init tegra30_pll_init(void)
819 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 933 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
820 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 934 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
821 0, NULL); 935 0, NULL);
822 clk_register_clkdev(clk, "pll_c_out1", NULL); 936 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
823 clks[pll_c_out1] = clk;
824
825 /* PLLP */
826 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
827 &pll_p_params, NULL);
828 clk_register_clkdev(clk, "pll_p", NULL);
829 clks[pll_p] = clk;
830
831 /* PLLP_OUT1 */
832 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
833 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
834 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
835 &pll_div_lock);
836 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
837 clk_base + PLLP_OUTA, 1, 0,
838 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
839 &pll_div_lock);
840 clk_register_clkdev(clk, "pll_p_out1", NULL);
841 clks[pll_p_out1] = clk;
842
843 /* PLLP_OUT2 */
844 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
845 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
846 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
847 &pll_div_lock);
848 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
849 clk_base + PLLP_OUTA, 17, 16,
850 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
851 &pll_div_lock);
852 clk_register_clkdev(clk, "pll_p_out2", NULL);
853 clks[pll_p_out2] = clk;
854
855 /* PLLP_OUT3 */
856 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
857 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
858 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
859 &pll_div_lock);
860 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
861 clk_base + PLLP_OUTB, 1, 0,
862 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
863 &pll_div_lock);
864 clk_register_clkdev(clk, "pll_p_out3", NULL);
865 clks[pll_p_out3] = clk;
866
867 /* PLLP_OUT4 */
868 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
869 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
870 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
871 &pll_div_lock);
872 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
873 clk_base + PLLP_OUTB, 17, 16,
874 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
875 &pll_div_lock);
876 clk_register_clkdev(clk, "pll_p_out4", NULL);
877 clks[pll_p_out4] = clk;
878 937
879 /* PLLM */ 938 /* PLLM */
880 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 939 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
881 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 940 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
882 &pll_m_params, NULL); 941 &pll_m_params, NULL);
883 clk_register_clkdev(clk, "pll_m", NULL); 942 clks[TEGRA30_CLK_PLL_M] = clk;
884 clks[pll_m] = clk;
885 943
886 /* PLLM_OUT1 */ 944 /* PLLM_OUT1 */
887 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 945 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -890,68 +948,44 @@ static void __init tegra30_pll_init(void)
890 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 948 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
891 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 949 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
892 CLK_SET_RATE_PARENT, 0, NULL); 950 CLK_SET_RATE_PARENT, 0, NULL);
893 clk_register_clkdev(clk, "pll_m_out1", NULL); 951 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
894 clks[pll_m_out1] = clk;
895 952
896 /* PLLX */ 953 /* PLLX */
897 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 954 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
898 &pll_x_params, NULL); 955 &pll_x_params, NULL);
899 clk_register_clkdev(clk, "pll_x", NULL); 956 clks[TEGRA30_CLK_PLL_X] = clk;
900 clks[pll_x] = clk;
901 957
902 /* PLLX_OUT0 */ 958 /* PLLX_OUT0 */
903 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 959 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
904 CLK_SET_RATE_PARENT, 1, 2); 960 CLK_SET_RATE_PARENT, 1, 2);
905 clk_register_clkdev(clk, "pll_x_out0", NULL); 961 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
906 clks[pll_x_out0] = clk;
907 962
908 /* PLLU */ 963 /* PLLU */
909 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 964 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
910 &pll_u_params, NULL); 965 &pll_u_params, NULL);
911 clk_register_clkdev(clk, "pll_u", NULL); 966 clks[TEGRA30_CLK_PLL_U] = clk;
912 clks[pll_u] = clk;
913 967
914 tegra30_utmi_param_configure(); 968 tegra30_utmi_param_configure();
915 969
916 /* PLLD */ 970 /* PLLD */
917 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 971 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
918 &pll_d_params, &pll_d_lock); 972 &pll_d_params, &pll_d_lock);
919 clk_register_clkdev(clk, "pll_d", NULL); 973 clks[TEGRA30_CLK_PLL_D] = clk;
920 clks[pll_d] = clk;
921 974
922 /* PLLD_OUT0 */ 975 /* PLLD_OUT0 */
923 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 976 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
924 CLK_SET_RATE_PARENT, 1, 2); 977 CLK_SET_RATE_PARENT, 1, 2);
925 clk_register_clkdev(clk, "pll_d_out0", NULL); 978 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
926 clks[pll_d_out0] = clk;
927 979
928 /* PLLD2 */ 980 /* PLLD2 */
929 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 981 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
930 &pll_d2_params, NULL); 982 &pll_d2_params, NULL);
931 clk_register_clkdev(clk, "pll_d2", NULL); 983 clks[TEGRA30_CLK_PLL_D2] = clk;
932 clks[pll_d2] = clk;
933 984
934 /* PLLD2_OUT0 */ 985 /* PLLD2_OUT0 */
935 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 986 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
936 CLK_SET_RATE_PARENT, 1, 2); 987 CLK_SET_RATE_PARENT, 1, 2);
937 clk_register_clkdev(clk, "pll_d2_out0", NULL); 988 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
938 clks[pll_d2_out0] = clk;
939
940 /* PLLA */
941 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
942 0, &pll_a_params, NULL);
943 clk_register_clkdev(clk, "pll_a", NULL);
944 clks[pll_a] = clk;
945
946 /* PLLA_OUT0 */
947 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
948 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
949 8, 8, 1, NULL);
950 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
951 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
952 CLK_SET_RATE_PARENT, 0, NULL);
953 clk_register_clkdev(clk, "pll_a_out0", NULL);
954 clks[pll_a_out0] = clk;
955 989
956 /* PLLE */ 990 /* PLLE */
957 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 991 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
@@ -960,256 +994,7 @@ static void __init tegra30_pll_init(void)
960 clk_base + PLLE_AUX, 2, 1, 0, NULL); 994 clk_base + PLLE_AUX, 2, 1, 0, NULL);
961 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 995 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
962 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); 996 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
963 clk_register_clkdev(clk, "pll_e", NULL); 997 clks[TEGRA30_CLK_PLL_E] = clk;
964 clks[pll_e] = clk;
965}
966
967static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
968 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
969static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
970 "clk_m_div4", "extern1", };
971static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
972 "clk_m_div4", "extern2", };
973static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
974 "clk_m_div4", "extern3", };
975
976static void __init tegra30_audio_clk_init(void)
977{
978 struct clk *clk;
979
980 /* spdif_in_sync */
981 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
982 24000000);
983 clk_register_clkdev(clk, "spdif_in_sync", NULL);
984 clks[spdif_in_sync] = clk;
985
986 /* i2s0_sync */
987 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
988 clk_register_clkdev(clk, "i2s0_sync", NULL);
989 clks[i2s0_sync] = clk;
990
991 /* i2s1_sync */
992 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
993 clk_register_clkdev(clk, "i2s1_sync", NULL);
994 clks[i2s1_sync] = clk;
995
996 /* i2s2_sync */
997 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
998 clk_register_clkdev(clk, "i2s2_sync", NULL);
999 clks[i2s2_sync] = clk;
1000
1001 /* i2s3_sync */
1002 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1003 clk_register_clkdev(clk, "i2s3_sync", NULL);
1004 clks[i2s3_sync] = clk;
1005
1006 /* i2s4_sync */
1007 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1008 clk_register_clkdev(clk, "i2s4_sync", NULL);
1009 clks[i2s4_sync] = clk;
1010
1011 /* vimclk_sync */
1012 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1013 clk_register_clkdev(clk, "vimclk_sync", NULL);
1014 clks[vimclk_sync] = clk;
1015
1016 /* audio0 */
1017 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1018 ARRAY_SIZE(mux_audio_sync_clk),
1019 CLK_SET_RATE_NO_REPARENT,
1020 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1021 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1022 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1023 CLK_GATE_SET_TO_DISABLE, NULL);
1024 clk_register_clkdev(clk, "audio0", NULL);
1025 clks[audio0] = clk;
1026
1027 /* audio1 */
1028 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1029 ARRAY_SIZE(mux_audio_sync_clk),
1030 CLK_SET_RATE_NO_REPARENT,
1031 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1032 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1033 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1034 CLK_GATE_SET_TO_DISABLE, NULL);
1035 clk_register_clkdev(clk, "audio1", NULL);
1036 clks[audio1] = clk;
1037
1038 /* audio2 */
1039 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1040 ARRAY_SIZE(mux_audio_sync_clk),
1041 CLK_SET_RATE_NO_REPARENT,
1042 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1043 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1044 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1045 CLK_GATE_SET_TO_DISABLE, NULL);
1046 clk_register_clkdev(clk, "audio2", NULL);
1047 clks[audio2] = clk;
1048
1049 /* audio3 */
1050 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1051 ARRAY_SIZE(mux_audio_sync_clk),
1052 CLK_SET_RATE_NO_REPARENT,
1053 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1054 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1055 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1056 CLK_GATE_SET_TO_DISABLE, NULL);
1057 clk_register_clkdev(clk, "audio3", NULL);
1058 clks[audio3] = clk;
1059
1060 /* audio4 */
1061 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1062 ARRAY_SIZE(mux_audio_sync_clk),
1063 CLK_SET_RATE_NO_REPARENT,
1064 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1065 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1066 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1067 CLK_GATE_SET_TO_DISABLE, NULL);
1068 clk_register_clkdev(clk, "audio4", NULL);
1069 clks[audio4] = clk;
1070
1071 /* spdif */
1072 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1073 ARRAY_SIZE(mux_audio_sync_clk),
1074 CLK_SET_RATE_NO_REPARENT,
1075 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1076 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1077 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1078 CLK_GATE_SET_TO_DISABLE, NULL);
1079 clk_register_clkdev(clk, "spdif", NULL);
1080 clks[spdif] = clk;
1081
1082 /* audio0_2x */
1083 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1084 CLK_SET_RATE_PARENT, 2, 1);
1085 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1086 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1087 &clk_doubler_lock);
1088 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1089 TEGRA_PERIPH_NO_RESET, clk_base,
1090 CLK_SET_RATE_PARENT, 113,
1091 periph_clk_enb_refcnt);
1092 clk_register_clkdev(clk, "audio0_2x", NULL);
1093 clks[audio0_2x] = clk;
1094
1095 /* audio1_2x */
1096 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1097 CLK_SET_RATE_PARENT, 2, 1);
1098 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1099 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1100 &clk_doubler_lock);
1101 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1102 TEGRA_PERIPH_NO_RESET, clk_base,
1103 CLK_SET_RATE_PARENT, 114,
1104 periph_clk_enb_refcnt);
1105 clk_register_clkdev(clk, "audio1_2x", NULL);
1106 clks[audio1_2x] = clk;
1107
1108 /* audio2_2x */
1109 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1110 CLK_SET_RATE_PARENT, 2, 1);
1111 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1112 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1113 &clk_doubler_lock);
1114 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1115 TEGRA_PERIPH_NO_RESET, clk_base,
1116 CLK_SET_RATE_PARENT, 115,
1117 periph_clk_enb_refcnt);
1118 clk_register_clkdev(clk, "audio2_2x", NULL);
1119 clks[audio2_2x] = clk;
1120
1121 /* audio3_2x */
1122 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1123 CLK_SET_RATE_PARENT, 2, 1);
1124 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1125 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1126 &clk_doubler_lock);
1127 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1128 TEGRA_PERIPH_NO_RESET, clk_base,
1129 CLK_SET_RATE_PARENT, 116,
1130 periph_clk_enb_refcnt);
1131 clk_register_clkdev(clk, "audio3_2x", NULL);
1132 clks[audio3_2x] = clk;
1133
1134 /* audio4_2x */
1135 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1136 CLK_SET_RATE_PARENT, 2, 1);
1137 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1138 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1139 &clk_doubler_lock);
1140 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1141 TEGRA_PERIPH_NO_RESET, clk_base,
1142 CLK_SET_RATE_PARENT, 117,
1143 periph_clk_enb_refcnt);
1144 clk_register_clkdev(clk, "audio4_2x", NULL);
1145 clks[audio4_2x] = clk;
1146
1147 /* spdif_2x */
1148 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1149 CLK_SET_RATE_PARENT, 2, 1);
1150 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1151 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1152 &clk_doubler_lock);
1153 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1154 TEGRA_PERIPH_NO_RESET, clk_base,
1155 CLK_SET_RATE_PARENT, 118,
1156 periph_clk_enb_refcnt);
1157 clk_register_clkdev(clk, "spdif_2x", NULL);
1158 clks[spdif_2x] = clk;
1159}
1160
1161static void __init tegra30_pmc_clk_init(void)
1162{
1163 struct clk *clk;
1164
1165 /* clk_out_1 */
1166 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1167 ARRAY_SIZE(clk_out1_parents),
1168 CLK_SET_RATE_NO_REPARENT,
1169 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1170 &clk_out_lock);
1171 clks[clk_out_1_mux] = clk;
1172 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1173 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1174 &clk_out_lock);
1175 clk_register_clkdev(clk, "extern1", "clk_out_1");
1176 clks[clk_out_1] = clk;
1177
1178 /* clk_out_2 */
1179 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1180 ARRAY_SIZE(clk_out2_parents),
1181 CLK_SET_RATE_NO_REPARENT,
1182 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1183 &clk_out_lock);
1184 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1185 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1186 &clk_out_lock);
1187 clk_register_clkdev(clk, "extern2", "clk_out_2");
1188 clks[clk_out_2] = clk;
1189
1190 /* clk_out_3 */
1191 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1192 ARRAY_SIZE(clk_out3_parents),
1193 CLK_SET_RATE_NO_REPARENT,
1194 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1195 &clk_out_lock);
1196 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1197 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1198 &clk_out_lock);
1199 clk_register_clkdev(clk, "extern3", "clk_out_3");
1200 clks[clk_out_3] = clk;
1201
1202 /* blink */
1203 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1204 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1205 pmc_base + PMC_DPD_PADS_ORIDE,
1206 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1207 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1208 pmc_base + PMC_CTRL,
1209 PMC_CTRL_BLINK_ENB, 0, NULL);
1210 clk_register_clkdev(clk, "blink", NULL);
1211 clks[blink] = clk;
1212
1213} 998}
1214 999
1215static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1000static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -1260,8 +1045,7 @@ static void __init tegra30_super_clk_init(void)
1260 CLK_SET_RATE_PARENT, 1045 CLK_SET_RATE_PARENT,
1261 clk_base + CCLKG_BURST_POLICY, 1046 clk_base + CCLKG_BURST_POLICY,
1262 0, 4, 0, 0, NULL); 1047 0, 4, 0, 0, NULL);
1263 clk_register_clkdev(clk, "cclk_g", NULL); 1048 clks[TEGRA30_CLK_CCLK_G] = clk;
1264 clks[cclk_g] = clk;
1265 1049
1266 /* 1050 /*
1267 * Clock input to cclk_lp divided from pll_p using 1051 * Clock input to cclk_lp divided from pll_p using
@@ -1297,8 +1081,7 @@ static void __init tegra30_super_clk_init(void)
1297 clk_base + CCLKLP_BURST_POLICY, 1081 clk_base + CCLKLP_BURST_POLICY,
1298 TEGRA_DIVIDER_2, 4, 8, 9, 1082 TEGRA_DIVIDER_2, 4, 8, 9,
1299 NULL); 1083 NULL);
1300 clk_register_clkdev(clk, "cclk_lp", NULL); 1084 clks[TEGRA30_CLK_CCLK_LP] = clk;
1301 clks[cclk_lp] = clk;
1302 1085
1303 /* SCLK */ 1086 /* SCLK */
1304 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1087 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
@@ -1306,142 +1089,42 @@ static void __init tegra30_super_clk_init(void)
1306 CLK_SET_RATE_PARENT, 1089 CLK_SET_RATE_PARENT,
1307 clk_base + SCLK_BURST_POLICY, 1090 clk_base + SCLK_BURST_POLICY,
1308 0, 4, 0, 0, NULL); 1091 0, 4, 0, 0, NULL);
1309 clk_register_clkdev(clk, "sclk", NULL); 1092 clks[TEGRA30_CLK_SCLK] = clk;
1310 clks[sclk] = clk;
1311
1312 /* HCLK */
1313 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1314 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1315 &sysrate_lock);
1316 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1317 clk_base + SYSTEM_CLK_RATE, 7,
1318 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1319 clk_register_clkdev(clk, "hclk", NULL);
1320 clks[hclk] = clk;
1321
1322 /* PCLK */
1323 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1324 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1325 &sysrate_lock);
1326 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1327 clk_base + SYSTEM_CLK_RATE, 3,
1328 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1329 clk_register_clkdev(clk, "pclk", NULL);
1330 clks[pclk] = clk;
1331 1093
1332 /* twd */ 1094 /* twd */
1333 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1095 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1334 CLK_SET_RATE_PARENT, 1, 2); 1096 CLK_SET_RATE_PARENT, 1, 2);
1335 clk_register_clkdev(clk, "twd", NULL); 1097 clks[TEGRA30_CLK_TWD] = clk;
1336 clks[twd] = clk; 1098
1099 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1337} 1100}
1338 1101
1339static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1102static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1340 "clk_m" }; 1103 "clk_m" };
1341static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1104static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1342static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1105static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1343static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1344 "clk_m" };
1345static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1346 "clk_m" };
1347static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1348 "clk_m" };
1349static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1350 "clk_m" };
1351static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1352 "clk_m" };
1353static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1106static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1354 "clk_m" }; 1107 "clk_m" };
1355static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1356static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1357 "clk_m" };
1358static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1359 "clk_32k" };
1360static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1108static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1361static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1362 "clk_m" };
1363static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1364static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1109static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1365 "pll_a_out0", "pll_c", 1110 "pll_a_out0", "pll_c",
1366 "pll_d2_out0", "clk_m" }; 1111 "pll_d2_out0", "clk_m" };
1367static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1368 "clk_32k", "pll_p",
1369 "clk_m", "pll_e" };
1370static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1112static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1371 "pll_d2_out0" }; 1113 "pll_d2_out0" };
1372 1114
1373static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1115static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1374 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, i2s0), 1116 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1375 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1), 1117 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1376 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2), 1118 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1377 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, i2s3), 1119 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1378 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, i2s4), 1120 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1379 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out), 1121 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1380 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in), 1122 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1381 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, d_audio), 1123 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1382 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, dam0),
1383 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, dam1),
1384 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, dam2),
1385 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, 0, hda),
1386 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, 0, hda2codec_2x),
1387 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1),
1388 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2),
1389 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3),
1390 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4),
1391 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, sbc5),
1392 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, sbc6),
1393 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, sata_oob),
1394 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, sata),
1395 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, ndflash),
1396 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, ndspeed),
1397 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir),
1398 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, csite),
1399 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, la),
1400 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr),
1401 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi),
1402 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tsensor),
1403 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, i2cslow),
1404 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde),
1405 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi),
1406 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp),
1407 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe),
1408 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x),
1409 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1410 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1411 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d),
1412 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, se),
1413 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, mselect),
1414 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor),
1415 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1),
1416 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2),
1417 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3),
1418 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4),
1419 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve),
1420 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo),
1421 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac),
1422 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, 0, actmon),
1423 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor),
1424 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1),
1425 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2),
1426 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3),
1427 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, TEGRA_PERIPH_ON_APB, i2c4),
1428 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, TEGRA_PERIPH_ON_APB, i2c5),
1429 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, uarta),
1430 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, uartb),
1431 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, uartc),
1432 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, uartd),
1433 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, uarte),
1434 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi),
1435 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, extern1),
1436 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, extern2),
1437 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, extern3),
1438 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, 0, pwm),
1439}; 1124};
1440 1125
1441static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1126static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1442 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, 0, disp1), 1127 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1443 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, 0, disp2),
1444 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, dsib),
1445}; 1128};
1446 1129
1447static void __init tegra30_periph_clk_init(void) 1130static void __init tegra30_periph_clk_init(void)
@@ -1450,158 +1133,25 @@ static void __init tegra30_periph_clk_init(void)
1450 struct clk *clk; 1133 struct clk *clk;
1451 int i; 1134 int i;
1452 1135
1453 /* apbdma */
1454 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1455 periph_clk_enb_refcnt);
1456 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1457 clks[apbdma] = clk;
1458
1459 /* rtc */
1460 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1461 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1462 clk_base, 0, 4, periph_clk_enb_refcnt);
1463 clk_register_clkdev(clk, NULL, "rtc-tegra");
1464 clks[rtc] = clk;
1465
1466 /* timer */
1467 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1468 5, periph_clk_enb_refcnt);
1469 clk_register_clkdev(clk, NULL, "timer");
1470 clks[timer] = clk;
1471
1472 /* kbc */
1473 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1474 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1475 clk_base, 0, 36, periph_clk_enb_refcnt);
1476 clk_register_clkdev(clk, NULL, "tegra-kbc");
1477 clks[kbc] = clk;
1478
1479 /* csus */
1480 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1481 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1482 clk_base, 0, 92, periph_clk_enb_refcnt);
1483 clk_register_clkdev(clk, "csus", "tengra_camera");
1484 clks[csus] = clk;
1485
1486 /* vcp */
1487 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1488 periph_clk_enb_refcnt);
1489 clk_register_clkdev(clk, "vcp", "tegra-avp");
1490 clks[vcp] = clk;
1491
1492 /* bsea */
1493 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1494 62, periph_clk_enb_refcnt);
1495 clk_register_clkdev(clk, "bsea", "tegra-avp");
1496 clks[bsea] = clk;
1497
1498 /* bsev */
1499 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1500 63, periph_clk_enb_refcnt);
1501 clk_register_clkdev(clk, "bsev", "tegra-aes");
1502 clks[bsev] = clk;
1503
1504 /* usbd */
1505 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1506 22, periph_clk_enb_refcnt);
1507 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1508 clks[usbd] = clk;
1509
1510 /* usb2 */
1511 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1512 58, periph_clk_enb_refcnt);
1513 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1514 clks[usb2] = clk;
1515
1516 /* usb3 */
1517 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1518 59, periph_clk_enb_refcnt);
1519 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1520 clks[usb3] = clk;
1521
1522 /* dsia */ 1136 /* dsia */
1523 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1137 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1524 0, 48, periph_clk_enb_refcnt); 1138 0, 48, periph_clk_enb_refcnt);
1525 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1139 clks[TEGRA30_CLK_DSIA] = clk;
1526 clks[dsia] = clk;
1527
1528 /* csi */
1529 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1530 0, 52, periph_clk_enb_refcnt);
1531 clk_register_clkdev(clk, "csi", "tegra_camera");
1532 clks[csi] = clk;
1533
1534 /* isp */
1535 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1536 periph_clk_enb_refcnt);
1537 clk_register_clkdev(clk, "isp", "tegra_camera");
1538 clks[isp] = clk;
1539 1140
1540 /* pcie */ 1141 /* pcie */
1541 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1142 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1542 70, periph_clk_enb_refcnt); 1143 70, periph_clk_enb_refcnt);
1543 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1144 clks[TEGRA30_CLK_PCIE] = clk;
1544 clks[pcie] = clk;
1545 1145
1546 /* afi */ 1146 /* afi */
1547 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1147 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1548 periph_clk_enb_refcnt); 1148 periph_clk_enb_refcnt);
1549 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1149 clks[TEGRA30_CLK_AFI] = clk;
1550 clks[afi] = clk;
1551 1150
1552 /* pciex */ 1151 /* pciex */
1553 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, 1152 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
1554 74, periph_clk_enb_refcnt); 1153 74, periph_clk_enb_refcnt);
1555 clk_register_clkdev(clk, "pciex", "tegra-pcie"); 1154 clks[TEGRA30_CLK_PCIEX] = clk;
1556 clks[pciex] = clk;
1557
1558 /* kfuse */
1559 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1560 TEGRA_PERIPH_ON_APB,
1561 clk_base, 0, 40, periph_clk_enb_refcnt);
1562 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1563 clks[kfuse] = clk;
1564
1565 /* fuse */
1566 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1567 TEGRA_PERIPH_ON_APB,
1568 clk_base, 0, 39, periph_clk_enb_refcnt);
1569 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1570 clks[fuse] = clk;
1571
1572 /* fuse_burn */
1573 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1574 TEGRA_PERIPH_ON_APB,
1575 clk_base, 0, 39, periph_clk_enb_refcnt);
1576 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1577 clks[fuse_burn] = clk;
1578
1579 /* apbif */
1580 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1581 clk_base, 0, 107, periph_clk_enb_refcnt);
1582 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1583 clks[apbif] = clk;
1584
1585 /* hda2hdmi */
1586 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1587 TEGRA_PERIPH_ON_APB,
1588 clk_base, 0, 128, periph_clk_enb_refcnt);
1589 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1590 clks[hda2hdmi] = clk;
1591
1592 /* sata_cold */
1593 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1594 TEGRA_PERIPH_ON_APB,
1595 clk_base, 0, 129, periph_clk_enb_refcnt);
1596 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1597 clks[sata_cold] = clk;
1598
1599 /* dtv */
1600 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1601 TEGRA_PERIPH_ON_APB,
1602 clk_base, 0, 79, periph_clk_enb_refcnt);
1603 clk_register_clkdev(clk, NULL, "dtv");
1604 clks[dtv] = clk;
1605 1155
1606 /* emc */ 1156 /* emc */
1607 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1157 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -1611,15 +1161,23 @@ static void __init tegra30_periph_clk_init(void)
1611 30, 2, 0, NULL); 1161 30, 2, 0, NULL);
1612 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1162 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1613 57, periph_clk_enb_refcnt); 1163 57, periph_clk_enb_refcnt);
1614 clk_register_clkdev(clk, "emc", NULL); 1164 clks[TEGRA30_CLK_EMC] = clk;
1615 clks[emc] = clk; 1165
1166 /* cml0 */
1167 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1168 0, 0, &cml_lock);
1169 clks[TEGRA30_CLK_CML0] = clk;
1170
1171 /* cml1 */
1172 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1173 1, 0, &cml_lock);
1174 clks[TEGRA30_CLK_CML1] = clk;
1616 1175
1617 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1176 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1618 data = &tegra_periph_clk_list[i]; 1177 data = &tegra_periph_clk_list[i];
1619 clk = tegra_clk_register_periph(data->name, data->p.parent_names, 1178 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1620 data->num_parents, &data->periph, 1179 data->num_parents, &data->periph,
1621 clk_base, data->offset, data->flags); 1180 clk_base, data->offset, data->flags);
1622 clk_register_clkdev(clk, data->con_id, data->dev_id);
1623 clks[data->clk_id] = clk; 1181 clks[data->clk_id] = clk;
1624 } 1182 }
1625 1183
@@ -1629,65 +1187,10 @@ static void __init tegra30_periph_clk_init(void)
1629 data->p.parent_names, 1187 data->p.parent_names,
1630 data->num_parents, &data->periph, 1188 data->num_parents, &data->periph,
1631 clk_base, data->offset); 1189 clk_base, data->offset);
1632 clk_register_clkdev(clk, data->con_id, data->dev_id);
1633 clks[data->clk_id] = clk; 1190 clks[data->clk_id] = clk;
1634 } 1191 }
1635}
1636
1637static void __init tegra30_fixed_clk_init(void)
1638{
1639 struct clk *clk;
1640
1641 /* clk_32k */
1642 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1643 32768);
1644 clk_register_clkdev(clk, "clk_32k", NULL);
1645 clks[clk_32k] = clk;
1646
1647 /* clk_m_div2 */
1648 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1649 CLK_SET_RATE_PARENT, 1, 2);
1650 clk_register_clkdev(clk, "clk_m_div2", NULL);
1651 clks[clk_m_div2] = clk;
1652
1653 /* clk_m_div4 */
1654 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1655 CLK_SET_RATE_PARENT, 1, 4);
1656 clk_register_clkdev(clk, "clk_m_div4", NULL);
1657 clks[clk_m_div4] = clk;
1658
1659 /* cml0 */
1660 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1661 0, 0, &cml_lock);
1662 clk_register_clkdev(clk, "cml0", NULL);
1663 clks[cml0] = clk;
1664 1192
1665 /* cml1 */ 1193 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1666 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1667 1, 0, &cml_lock);
1668 clk_register_clkdev(clk, "cml1", NULL);
1669 clks[cml1] = clk;
1670}
1671
1672static void __init tegra30_osc_clk_init(void)
1673{
1674 struct clk *clk;
1675 unsigned int pll_ref_div;
1676
1677 tegra30_clk_measure_input_freq();
1678
1679 /* clk_m */
1680 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1681 input_freq);
1682 clk_register_clkdev(clk, "clk_m", NULL);
1683 clks[clk_m] = clk;
1684
1685 /* pll_ref */
1686 pll_ref_div = tegra30_get_pll_ref_div();
1687 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1688 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1689 clk_register_clkdev(clk, "pll_ref", NULL);
1690 clks[pll_ref] = clk;
1691} 1194}
1692 1195
1693/* Tegra30 CPU clock and reset control functions */ 1196/* Tegra30 CPU clock and reset control functions */
@@ -1829,48 +1332,48 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1829}; 1332};
1830 1333
1831static struct tegra_clk_init_table init_table[] __initdata = { 1334static struct tegra_clk_init_table init_table[] __initdata = {
1832 {uarta, pll_p, 408000000, 0}, 1335 {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1833 {uartb, pll_p, 408000000, 0}, 1336 {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1834 {uartc, pll_p, 408000000, 0}, 1337 {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1835 {uartd, pll_p, 408000000, 0}, 1338 {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1836 {uarte, pll_p, 408000000, 0}, 1339 {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1837 {pll_a, clk_max, 564480000, 1}, 1340 {TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
1838 {pll_a_out0, clk_max, 11289600, 1}, 1341 {TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
1839 {extern1, pll_a_out0, 0, 1}, 1342 {TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
1840 {clk_out_1_mux, extern1, 0, 0}, 1343 {TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
1841 {clk_out_1, clk_max, 0, 1}, 1344 {TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
1842 {blink, clk_max, 0, 1}, 1345 {TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
1843 {i2s0, pll_a_out0, 11289600, 0}, 1346 {TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1844 {i2s1, pll_a_out0, 11289600, 0}, 1347 {TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1845 {i2s2, pll_a_out0, 11289600, 0}, 1348 {TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1846 {i2s3, pll_a_out0, 11289600, 0}, 1349 {TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1847 {i2s4, pll_a_out0, 11289600, 0}, 1350 {TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1848 {sdmmc1, pll_p, 48000000, 0}, 1351 {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1849 {sdmmc2, pll_p, 48000000, 0}, 1352 {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1850 {sdmmc3, pll_p, 48000000, 0}, 1353 {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1851 {pll_m, clk_max, 0, 1}, 1354 {TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
1852 {pclk, clk_max, 0, 1}, 1355 {TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
1853 {csite, clk_max, 0, 1}, 1356 {TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
1854 {emc, clk_max, 0, 1}, 1357 {TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
1855 {mselect, clk_max, 0, 1}, 1358 {TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
1856 {sbc1, pll_p, 100000000, 0}, 1359 {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1857 {sbc2, pll_p, 100000000, 0}, 1360 {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1858 {sbc3, pll_p, 100000000, 0}, 1361 {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1859 {sbc4, pll_p, 100000000, 0}, 1362 {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1860 {sbc5, pll_p, 100000000, 0}, 1363 {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1861 {sbc6, pll_p, 100000000, 0}, 1364 {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1862 {host1x, pll_c, 150000000, 0}, 1365 {TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
1863 {disp1, pll_p, 600000000, 0}, 1366 {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1864 {disp2, pll_p, 600000000, 0}, 1367 {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
1865 {twd, clk_max, 0, 1}, 1368 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1866 {gr2d, pll_c, 300000000, 0}, 1369 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1867 {gr3d, pll_c, 300000000, 0}, 1370 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1868 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1371 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1869}; 1372};
1870 1373
1871static void __init tegra30_clock_apply_init_table(void) 1374static void __init tegra30_clock_apply_init_table(void)
1872{ 1375{
1873 tegra_init_from_table(init_table, clks, clk_max); 1376 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1874} 1377}
1875 1378
1876/* 1379/*
@@ -1879,19 +1382,19 @@ static void __init tegra30_clock_apply_init_table(void)
1879 * table under two names. 1382 * table under two names.
1880 */ 1383 */
1881static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1384static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1882 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1385 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1883 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1386 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1884 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1387 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1885 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1388 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1886 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1389 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1887 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1390 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1888 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1391 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1889 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1392 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1890 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1393 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1891 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1394 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1892 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1395 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_PCIEX, "tegra_pcie", "pciex"),
1893 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1396 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1894 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 1397 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
1895}; 1398};
1896 1399
1897static const struct of_device_id pmc_match[] __initconst = { 1400static const struct of_device_id pmc_match[] __initconst = {
@@ -1921,21 +1424,26 @@ static void __init tegra30_clock_init(struct device_node *np)
1921 BUG(); 1424 BUG();
1922 } 1425 }
1923 1426
1924 clks = tegra_clk_init(clk_max, TEGRA30_CLK_PERIPH_BANKS); 1427 clks = tegra_clk_init(TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_PERIPH_BANKS);
1925 if (!clks) 1428 if (!clks)
1926 return; 1429 return;
1927 1430
1928 tegra30_osc_clk_init(); 1431 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1929 tegra30_fixed_clk_init(); 1432 ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0)
1433 return;
1434
1435
1436 tegra_fixed_clk_init(tegra30_clks);
1930 tegra30_pll_init(); 1437 tegra30_pll_init();
1931 tegra30_super_clk_init(); 1438 tegra30_super_clk_init();
1932 tegra30_periph_clk_init(); 1439 tegra30_periph_clk_init();
1933 tegra30_audio_clk_init(); 1440 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
1934 tegra30_pmc_clk_init(); 1441 tegra_pmc_clk_init(pmc_base, tegra30_clks);
1935 1442
1936 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1443 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1937 1444
1938 tegra_add_of_provider(np); 1445 tegra_add_of_provider(np);
1446 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1939 1447
1940 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1448 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1941 1449
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 13:26:21 -0400