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-rw-r--r--Documentation/devicetree/bindings/spi/efm32-spi.txt13
-rw-r--r--Documentation/devicetree/bindings/spi/qcom,spi-qup.txt6
-rw-r--r--Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt28
-rw-r--r--Documentation/devicetree/bindings/spi/spi-davinci.txt9
-rw-r--r--Documentation/devicetree/bindings/spi/spi-rockchip.txt37
-rw-r--r--Documentation/devicetree/bindings/spi/spi-samsung.txt26
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts2
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts2
-rw-r--r--drivers/spi/Kconfig16
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-adi-v3.c5
-rw-r--r--drivers/spi/spi-atmel.c22
-rw-r--r--drivers/spi/spi-au1550.c6
-rw-r--r--drivers/spi/spi-cadence.c37
-rw-r--r--drivers/spi/spi-clps711x.c2
-rw-r--r--drivers/spi/spi-davinci.c72
-rw-r--r--drivers/spi/spi-dw-mmio.c19
-rw-r--r--drivers/spi/spi-efm32.c8
-rw-r--r--drivers/spi/spi-falcon.c2
-rw-r--r--drivers/spi/spi-fsl-lib.c2
-rw-r--r--drivers/spi/spi-fsl-spi.c2
-rw-r--r--drivers/spi/spi-omap-100k.c2
-rw-r--r--drivers/spi/spi-omap-uwire.c11
-rw-r--r--drivers/spi/spi-omap2-mcspi.c14
-rw-r--r--drivers/spi/spi-orion.c78
-rw-r--r--drivers/spi/spi-pl022.c2
-rw-r--r--drivers/spi/spi-qup.c36
-rw-r--r--drivers/spi/spi-rockchip.c837
-rw-r--r--drivers/spi/spi-rspi.c45
-rw-r--r--drivers/spi/spi-s3c64xx.c54
-rw-r--r--drivers/spi/spi-sh-hspi.c2
-rw-r--r--drivers/spi/spi-sh-msiof.c527
-rw-r--r--drivers/spi/spi-sh.c15
-rw-r--r--drivers/spi/spi-topcliff-pch.c12
-rw-r--r--drivers/spi/spi-xilinx.c2
-rw-r--r--drivers/spi/spi.c12
-rw-r--r--include/linux/spi/sh_msiof.h2
38 files changed, 1725 insertions, 245 deletions
diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt
index 130cd17e3680..750e29aff9bc 100644
--- a/Documentation/devicetree/bindings/spi/efm32-spi.txt
+++ b/Documentation/devicetree/bindings/spi/efm32-spi.txt
@@ -10,11 +10,12 @@ Required properties:
10- cs-gpios: see spi-bus.txt 10- cs-gpios: see spi-bus.txt
11 11
12Recommended properties : 12Recommended properties :
13- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to 13- energymicro,location: Value to write to the ROUTE register's LOCATION
14 configure the pinmux for the device, see datasheet for values. 14 bitfield to configure the pinmux for the device, see
15 If "efm32,location" property is not provided, keeping what is 15 datasheet for values.
16 already configured in the hardware, so its either the reset 16 If this property is not provided, keeping what is
17 default 0 or whatever the bootloader did. 17 already configured in the hardware, so its either the
18 reset default 0 or whatever the bootloader did.
18 19
19Example: 20Example:
20 21
@@ -26,7 +27,7 @@ spi1: spi@0x4000c400 { /* USART1 */
26 interrupts = <15 16>; 27 interrupts = <15 16>;
27 clocks = <&cmu 20>; 28 clocks = <&cmu 20>;
28 cs-gpios = <&gpio 51 1>; // D3 29 cs-gpios = <&gpio 51 1>; // D3
29 efm32,location = <1>; 30 energymicro,location = <1>;
30 status = "ok"; 31 status = "ok";
31 32
32 ks8851@0 { 33 ks8851@0 {
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
index bee6ff204baf..e2c88df2cc15 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable
7data path from 4 bits to 32 bits and numerous protocol variants. 7data path from 4 bits to 32 bits and numerous protocol variants.
8 8
9Required properties: 9Required properties:
10- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1" 10- compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
14
11- reg: Should contain base register location and length 15- reg: Should contain base register location and length
12- interrupts: Interrupt number used by this controller 16- interrupts: Interrupt number used by this controller
13 17
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
new file mode 100644
index 000000000000..bd99193e87b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -0,0 +1,28 @@
1Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
2
3Required properties:
4- compatible : "snps,dw-apb-ssi"
5- reg : The register base for the controller.
6- interrupts : One interrupt, used by the controller.
7- #address-cells : <1>, as required by generic SPI binding.
8- #size-cells : <0>, also as required by generic SPI binding.
9
10Optional properties:
11- cs-gpios : Specifies the gpio pis to be used for chipselects.
12- num-cs : The number of chipselects. If omitted, this will default to 4.
13
14Child nodes as per the generic SPI binding.
15
16Example:
17
18 spi@fff00000 {
19 compatible = "snps,dw-apb-ssi";
20 reg = <0xfff00000 0x1000>;
21 interrupts = <0 154 4>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 num-cs = <2>;
25 cs-gpios = <&gpio0 13 0>,
26 <&gpio0 14 0>;
27 };
28
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt
index 6d0ac8d0ad9b..f80887bca0d6 100644
--- a/Documentation/devicetree/bindings/spi/spi-davinci.txt
+++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -8,7 +8,8 @@ Required properties:
8 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 8 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
9 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family 9 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
10- reg: Offset and length of SPI controller register space 10- reg: Offset and length of SPI controller register space
11- num-cs: Number of chip selects 11- num-cs: Number of chip selects. This includes internal as well as
12 GPIO chip selects.
12- ti,davinci-spi-intr-line: interrupt line used to connect the SPI 13- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
13 IP to the interrupt controller within the SoC. Possible values 14 IP to the interrupt controller within the SoC. Possible values
14 are 0 and 1. Manual says one of the two possible interrupt 15 are 0 and 1. Manual says one of the two possible interrupt
@@ -17,6 +18,12 @@ Required properties:
17- interrupts: interrupt number mapped to CPU. 18- interrupts: interrupt number mapped to CPU.
18- clocks: spi clk phandle 19- clocks: spi clk phandle
19 20
21Optional:
22- cs-gpios: gpio chip selects
23 For example to have 3 internal CS and 2 GPIO CS, user could define
24 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
25 where first three are internal CS and last two are GPIO CS.
26
20Example of a NOR flash slave device (n25q032) connected to DaVinci 27Example of a NOR flash slave device (n25q032) connected to DaVinci
21SPI controller device over the SPI bus. 28SPI controller device over the SPI bus.
22 29
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
new file mode 100644
index 000000000000..7bab35575817
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -0,0 +1,37 @@
1* Rockchip SPI Controller
2
3The Rockchip SPI controller is used to interface with various devices such as flash
4and display controllers using the SPI communication interface.
5
6Required Properties:
7
8- compatible: should be one of the following.
9 "rockchip,rk3066-spi" for rk3066.
10 "rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.
11 "rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.
12- reg: physical base address of the controller and length of memory mapped
13 region.
14- interrupts: The interrupt number to the cpu. The interrupt specifier format
15 depends on the interrupt controller.
16- clocks: Must contain an entry for each entry in clock-names.
17- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
18 the peripheral clock.
19- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
20 Documentation/devicetree/bindings/dma/dma.txt
21- dma-names: DMA request names should include "tx" and "rx" if present.
22- #address-cells: should be 1.
23- #size-cells: should be 0.
24
25Example:
26
27 spi0: spi@ff110000 {
28 compatible = "rockchip,rk3066-spi";
29 reg = <0xff110000 0x1000>;
30 dmas = <&pdma1 11>, <&pdma1 12>;
31 dma-names = "tx", "rx";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
36 clock-names = "spiclk", "apb_pclk";
37 };
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 86aa061f069f..792efbaedc54 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -18,14 +18,11 @@ Required SoC Specific Properties:
18- interrupts: The interrupt number to the cpu. The interrupt specifier format 18- interrupts: The interrupt number to the cpu. The interrupt specifier format
19 depends on the interrupt controller. 19 depends on the interrupt controller.
20 20
21[PRELIMINARY: the dma channel allocation will change once there are 21- dmas : Two or more DMA channel specifiers following the convention outlined
22official DMA bindings] 22 in bindings/dma/dma.txt
23 23
24- tx-dma-channel: The dma channel specifier for tx operations. The format of 24- dma-names: Names for the dma channels. There must be at least one channel
25 the dma specifier depends on the dma controller. 25 named "tx" for transmit and named "rx" for receive.
26
27- rx-dma-channel: The dma channel specifier for rx operations. The format of
28 the dma specifier depends on the dma controller.
29 26
30Required Board Specific Properties: 27Required Board Specific Properties:
31 28
@@ -42,15 +39,13 @@ Optional Board Specific Properties:
42- num-cs: Specifies the number of chip select lines supported. If 39- num-cs: Specifies the number of chip select lines supported. If
43 not specified, the default number of chip select lines is set to 1. 40 not specified, the default number of chip select lines is set to 1.
44 41
42- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
43
45SPI Controller specific data in SPI slave nodes: 44SPI Controller specific data in SPI slave nodes:
46 45
47- The spi slave nodes should provide the following information which is required 46- The spi slave nodes should provide the following information which is required
48 by the spi controller. 47 by the spi controller.
49 48
50 - cs-gpio: A gpio specifier that specifies the gpio line used as
51 the slave select line by the spi controller. The format of the gpio
52 specifier depends on the gpio controller.
53
54 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the 49 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
55 miso line (to account for any lag in the miso line). The following are the 50 miso line (to account for any lag in the miso line). The following are the
56 valid values. 51 valid values.
@@ -74,8 +69,11 @@ Example:
74 compatible = "samsung,exynos4210-spi"; 69 compatible = "samsung,exynos4210-spi";
75 reg = <0x12d20000 0x100>; 70 reg = <0x12d20000 0x100>;
76 interrupts = <0 66 0>; 71 interrupts = <0 66 0>;
77 tx-dma-channel = <&pdma0 5>; 72 dmas = <&pdma0 5
78 rx-dma-channel = <&pdma0 4>; 73 &pdma0 4>;
74 dma-names = "tx", "rx";
75 #address-cells = <1>;
76 #size-cells = <0>;
79 }; 77 };
80 78
81- Board Specific Portion: 79- Board Specific Portion:
@@ -85,6 +83,7 @@ Example:
85 #size-cells = <0>; 83 #size-cells = <0>;
86 pinctrl-names = "default"; 84 pinctrl-names = "default";
87 pinctrl-0 = <&spi0_bus>; 85 pinctrl-0 = <&spi0_bus>;
86 cs-gpios = <&gpa2 5 0>;
88 87
89 w25q80bw@0 { 88 w25q80bw@0 {
90 #address-cells = <1>; 89 #address-cells = <1>;
@@ -94,7 +93,6 @@ Example:
94 spi-max-frequency = <10000>; 93 spi-max-frequency = <10000>;
95 94
96 controller-data { 95 controller-data {
97 cs-gpio = <&gpa2 5 1 0 3>;
98 samsung,spi-feedback-delay = <0>; 96 samsung,spi-feedback-delay = <0>;
99 }; 97 };
100 98
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 636d16684750..676e6e0c8cf3 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -168,6 +168,7 @@
168 }; 168 };
169 169
170 spi_2: spi@13940000 { 170 spi_2: spi@13940000 {
171 cs-gpios = <&gpc1 2 0>;
171 status = "okay"; 172 status = "okay";
172 173
173 w25x80@0 { 174 w25x80@0 {
@@ -178,7 +179,6 @@
178 spi-max-frequency = <1000000>; 179 spi-max-frequency = <1000000>;
179 180
180 controller-data { 181 controller-data {
181 cs-gpio = <&gpc1 2 0>;
182 samsung,spi-feedback-delay = <0>; 182 samsung,spi-feedback-delay = <0>;
183 }; 183 };
184 184
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 77878447b312..11967f4561e0 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -589,6 +589,7 @@
589 spi_1: spi@13930000 { 589 spi_1: spi@13930000 {
590 pinctrl-names = "default"; 590 pinctrl-names = "default";
591 pinctrl-0 = <&spi1_bus>; 591 pinctrl-0 = <&spi1_bus>;
592 cs-gpios = <&gpb 5 0>;
592 status = "okay"; 593 status = "okay";
593 594
594 s5c73m3_spi: s5c73m3 { 595 s5c73m3_spi: s5c73m3 {
@@ -596,7 +597,6 @@
596 spi-max-frequency = <50000000>; 597 spi-max-frequency = <50000000>;
597 reg = <0>; 598 reg = <0>;
598 controller-data { 599 controller-data {
599 cs-gpio = <&gpb 5 0>;
600 samsung,spi-feedback-delay = <2>; 600 samsung,spi-feedback-delay = <2>;
601 }; 601 };
602 }; 602 };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a705d404..0c6433ae63ac 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -316,6 +316,7 @@
316 }; 316 };
317 317
318 spi_1: spi@12d30000 { 318 spi_1: spi@12d30000 {
319 cs-gpios = <&gpa2 5 0>;
319 status = "okay"; 320 status = "okay";
320 321
321 w25q80bw@0 { 322 w25q80bw@0 {
@@ -326,7 +327,6 @@
326 spi-max-frequency = <1000000>; 327 spi-max-frequency = <1000000>;
327 328
328 controller-data { 329 controller-data {
329 cs-gpio = <&gpa2 5 0>;
330 samsung,spi-feedback-delay = <0>; 330 samsung,spi-feedback-delay = <0>;
331 }; 331 };
332 332
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 213b5cbb9dcc..62e2242ad7e0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -382,9 +382,21 @@ config SPI_PXA2XX
382config SPI_PXA2XX_PCI 382config SPI_PXA2XX_PCI
383 def_tristate SPI_PXA2XX && PCI 383 def_tristate SPI_PXA2XX && PCI
384 384
385config SPI_ROCKCHIP
386 tristate "Rockchip SPI controller driver"
387 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
388 help
389 This selects a driver for Rockchip SPI controller.
390
391 If you say yes to this option, support will be included for
392 RK3066, RK3188 and RK3288 families of SPI controller.
393 Rockchip SPI controller support DMA transport and PIO mode.
394 The main usecase of this controller is to use spi flash as boot
395 device.
396
385config SPI_RSPI 397config SPI_RSPI
386 tristate "Renesas RSPI/QSPI controller" 398 tristate "Renesas RSPI/QSPI controller"
387 depends on (SUPERH && SH_DMAE_BASE) || ARCH_SHMOBILE 399 depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
388 help 400 help
389 SPI driver for Renesas RSPI and QSPI blocks. 401 SPI driver for Renesas RSPI and QSPI blocks.
390 402
@@ -434,7 +446,7 @@ config SPI_SC18IS602
434 446
435config SPI_SH_MSIOF 447config SPI_SH_MSIOF
436 tristate "SuperH MSIOF SPI controller" 448 tristate "SuperH MSIOF SPI controller"
437 depends on HAVE_CLK 449 depends on HAVE_CLK && HAS_DMA
438 depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST 450 depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
439 help 451 help
440 SPI driver for SuperH and SH Mobile MSIOF blocks. 452 SPI driver for SuperH and SH Mobile MSIOF blocks.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 929c9f5eac01..762da0741148 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -61,6 +61,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
61obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o 61obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
62obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o 62obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
63obj-$(CONFIG_SPI_QUP) += spi-qup.o 63obj-$(CONFIG_SPI_QUP) += spi-qup.o
64obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
64obj-$(CONFIG_SPI_RSPI) += spi-rspi.o 65obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
65obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o 66obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
66spi-s3c24xx-hw-y := spi-s3c24xx.o 67spi-s3c24xx-hw-y := spi-s3c24xx.o
diff --git a/drivers/spi/spi-adi-v3.c b/drivers/spi/spi-adi-v3.c
index dcb2287c7f8a..19ea8fb78cc7 100644
--- a/drivers/spi/spi-adi-v3.c
+++ b/drivers/spi/spi-adi-v3.c
@@ -660,10 +660,9 @@ static int adi_spi_setup(struct spi_device *spi)
660 struct adi_spi3_chip *chip_info = spi->controller_data; 660 struct adi_spi3_chip *chip_info = spi->controller_data;
661 661
662 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 662 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
663 if (!chip) { 663 if (!chip)
664 dev_err(&spi->dev, "can not allocate chip data\n");
665 return -ENOMEM; 664 return -ENOMEM;
666 } 665
667 if (chip_info) { 666 if (chip_info) {
668 if (chip_info->control & ~ctl_reg) { 667 if (chip_info->control & ~ctl_reg) {
669 dev_err(&spi->dev, 668 dev_err(&spi->dev,
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 92a6f0d93233..113c83f44b5c 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -597,21 +597,15 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
597 goto err_exit; 597 goto err_exit;
598 598
599 /* Send both scatterlists */ 599 /* Send both scatterlists */
600 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 600 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
601 &as->dma.sgrx, 601 DMA_FROM_DEVICE,
602 1, 602 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
603 DMA_FROM_DEVICE,
604 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
605 NULL);
606 if (!rxdesc) 603 if (!rxdesc)
607 goto err_dma; 604 goto err_dma;
608 605
609 txdesc = txchan->device->device_prep_slave_sg(txchan, 606 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
610 &as->dma.sgtx, 607 DMA_TO_DEVICE,
611 1, 608 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
612 DMA_TO_DEVICE,
613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
614 NULL);
615 if (!txdesc) 609 if (!txdesc)
616 goto err_dma; 610 goto err_dma;
617 611
@@ -1018,7 +1012,7 @@ static int atmel_spi_setup(struct spi_device *spi)
1018 csr |= SPI_BF(DLYBCT, 0); 1012 csr |= SPI_BF(DLYBCT, 0);
1019 1013
1020 /* chipselect must have been muxed as GPIO (e.g. in board setup) */ 1014 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1021 npcs_pin = (unsigned int)spi->controller_data; 1015 npcs_pin = (unsigned long)spi->controller_data;
1022 1016
1023 if (gpio_is_valid(spi->cs_gpio)) 1017 if (gpio_is_valid(spi->cs_gpio))
1024 npcs_pin = spi->cs_gpio; 1018 npcs_pin = spi->cs_gpio;
@@ -1253,7 +1247,7 @@ msg_done:
1253static void atmel_spi_cleanup(struct spi_device *spi) 1247static void atmel_spi_cleanup(struct spi_device *spi)
1254{ 1248{
1255 struct atmel_spi_device *asd = spi->controller_state; 1249 struct atmel_spi_device *asd = spi->controller_state;
1256 unsigned gpio = (unsigned) spi->controller_data; 1250 unsigned gpio = (unsigned long) spi->controller_data;
1257 1251
1258 if (!asd) 1252 if (!asd)
1259 return; 1253 return;
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index 67375a11d4bd..fb61464348a1 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -925,8 +925,7 @@ err_no_txdma:
925 iounmap((void __iomem *)hw->regs); 925 iounmap((void __iomem *)hw->regs);
926 926
927err_ioremap: 927err_ioremap:
928 release_resource(hw->ioarea); 928 release_mem_region(r->start, sizeof(psc_spi_t));
929 kfree(hw->ioarea);
930 929
931err_no_iores: 930err_no_iores:
932err_no_pdata: 931err_no_pdata:
@@ -946,8 +945,7 @@ static int au1550_spi_remove(struct platform_device *pdev)
946 spi_bitbang_stop(&hw->bitbang); 945 spi_bitbang_stop(&hw->bitbang);
947 free_irq(hw->irq, hw); 946 free_irq(hw->irq, hw);
948 iounmap((void __iomem *)hw->regs); 947 iounmap((void __iomem *)hw->regs);
949 release_resource(hw->ioarea); 948 release_mem_region(r->start, sizeof(psc_spi_t));
950 kfree(hw->ioarea);
951 949
952 if (hw->usedma) { 950 if (hw->usedma) {
953 au1550_spi_dma_rxtmp_free(hw); 951 au1550_spi_dma_rxtmp_free(hw);
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index bb758978465d..562ff83debd9 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -205,18 +205,30 @@ static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
205static void cdns_spi_config_clock_mode(struct spi_device *spi) 205static void cdns_spi_config_clock_mode(struct spi_device *spi)
206{ 206{
207 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 207 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
208 u32 ctrl_reg; 208 u32 ctrl_reg, new_ctrl_reg;
209 209
210 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET); 210 new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
211 211
212 /* Set the SPI clock phase and clock polarity */ 212 /* Set the SPI clock phase and clock polarity */
213 ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK); 213 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
214 if (spi->mode & SPI_CPHA) 214 if (spi->mode & SPI_CPHA)
215 ctrl_reg |= CDNS_SPI_CR_CPHA_MASK; 215 new_ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
216 if (spi->mode & SPI_CPOL) 216 if (spi->mode & SPI_CPOL)
217 ctrl_reg |= CDNS_SPI_CR_CPOL_MASK; 217 new_ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
218 218
219 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg); 219 if (new_ctrl_reg != ctrl_reg) {
220 /*
221 * Just writing the CR register does not seem to apply the clock
222 * setting changes. This is problematic when changing the clock
223 * polarity as it will cause the SPI slave to see spurious clock
224 * transitions. To workaround the issue toggle the ER register.
225 */
226 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
227 CDNS_SPI_ER_DISABLE_MASK);
228 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, new_ctrl_reg);
229 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
230 CDNS_SPI_ER_ENABLE_MASK);
231 }
220} 232}
221 233
222/** 234/**
@@ -370,6 +382,12 @@ static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
370 382
371 return status; 383 return status;
372} 384}
385static int cdns_prepare_message(struct spi_master *master,
386 struct spi_message *msg)
387{
388 cdns_spi_config_clock_mode(msg->spi);
389 return 0;
390}
373 391
374/** 392/**
375 * cdns_transfer_one - Initiates the SPI transfer 393 * cdns_transfer_one - Initiates the SPI transfer
@@ -416,8 +434,6 @@ static int cdns_prepare_transfer_hardware(struct spi_master *master)
416{ 434{
417 struct cdns_spi *xspi = spi_master_get_devdata(master); 435 struct cdns_spi *xspi = spi_master_get_devdata(master);
418 436
419 cdns_spi_config_clock_mode(master->cur_msg->spi);
420
421 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 437 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
422 CDNS_SPI_ER_ENABLE_MASK); 438 CDNS_SPI_ER_ENABLE_MASK);
423 439
@@ -532,6 +548,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
532 xspi->is_decoded_cs = 0; 548 xspi->is_decoded_cs = 0;
533 549
534 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; 550 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
551 master->prepare_message = cdns_prepare_message;
535 master->transfer_one = cdns_transfer_one; 552 master->transfer_one = cdns_transfer_one;
536 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; 553 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
537 master->set_cs = cdns_spi_chipselect; 554 master->set_cs = cdns_spi_chipselect;
@@ -647,7 +664,7 @@ static int __maybe_unused cdns_spi_resume(struct device *dev)
647static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend, 664static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
648 cdns_spi_resume); 665 cdns_spi_resume);
649 666
650static struct of_device_id cdns_spi_of_match[] = { 667static const struct of_device_id cdns_spi_of_match[] = {
651 { .compatible = "xlnx,zynq-spi-r1p6" }, 668 { .compatible = "xlnx,zynq-spi-r1p6" },
652 { .compatible = "cdns,spi-r1p6" }, 669 { .compatible = "cdns,spi-r1p6" },
653 { /* end of table */ } 670 { /* end of table */ }
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 4cd62f636547..ce538dad526b 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -184,8 +184,6 @@ static int spi_clps711x_probe(struct platform_device *pdev)
184 } 184 }
185 master->max_speed_hz = clk_get_rate(hw->spi_clk); 185 master->max_speed_hz = clk_get_rate(hw->spi_clk);
186 186
187 platform_set_drvdata(pdev, master);
188
189 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3"); 187 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
190 if (IS_ERR(hw->syscon)) { 188 if (IS_ERR(hw->syscon)) {
191 ret = PTR_ERR(hw->syscon); 189 ret = PTR_ERR(hw->syscon);
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 50f750989258..276a3884fb3c 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -30,6 +30,7 @@
30#include <linux/edma.h> 30#include <linux/edma.h>
31#include <linux/of.h> 31#include <linux/of.h>
32#include <linux/of_device.h> 32#include <linux/of_device.h>
33#include <linux/of_gpio.h>
33#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h> 35#include <linux/spi/spi_bitbang.h>
35#include <linux/slab.h> 36#include <linux/slab.h>
@@ -38,8 +39,6 @@
38 39
39#define SPI_NO_RESOURCE ((resource_size_t)-1) 40#define SPI_NO_RESOURCE ((resource_size_t)-1)
40 41
41#define SPI_MAX_CHIPSELECT 2
42
43#define CS_DEFAULT 0xFF 42#define CS_DEFAULT 0xFF
44 43
45#define SPIFMT_PHASE_MASK BIT(16) 44#define SPIFMT_PHASE_MASK BIT(16)
@@ -142,7 +141,7 @@ struct davinci_spi {
142 void (*get_rx)(u32 rx_data, struct davinci_spi *); 141 void (*get_rx)(u32 rx_data, struct davinci_spi *);
143 u32 (*get_tx)(struct davinci_spi *); 142 u32 (*get_tx)(struct davinci_spi *);
144 143
145 u8 bytes_per_word[SPI_MAX_CHIPSELECT]; 144 u8 *bytes_per_word;
146}; 145};
147 146
148static struct davinci_spi_config davinci_spi_default_cfg; 147static struct davinci_spi_config davinci_spi_default_cfg;
@@ -213,13 +212,16 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
213 u8 chip_sel = spi->chip_select; 212 u8 chip_sel = spi->chip_select;
214 u16 spidat1 = CS_DEFAULT; 213 u16 spidat1 = CS_DEFAULT;
215 bool gpio_chipsel = false; 214 bool gpio_chipsel = false;
215 int gpio;
216 216
217 dspi = spi_master_get_devdata(spi->master); 217 dspi = spi_master_get_devdata(spi->master);
218 pdata = &dspi->pdata; 218 pdata = &dspi->pdata;
219 219
220 if (pdata->chip_sel && chip_sel < pdata->num_chipselect && 220 if (spi->cs_gpio >= 0) {
221 pdata->chip_sel[chip_sel] != SPI_INTERN_CS) 221 /* SPI core parse and update master->cs_gpio */
222 gpio_chipsel = true; 222 gpio_chipsel = true;
223 gpio = spi->cs_gpio;
224 }
223 225
224 /* 226 /*
225 * Board specific chip select logic decides the polarity and cs 227 * Board specific chip select logic decides the polarity and cs
@@ -227,9 +229,9 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
227 */ 229 */
228 if (gpio_chipsel) { 230 if (gpio_chipsel) {
229 if (value == BITBANG_CS_ACTIVE) 231 if (value == BITBANG_CS_ACTIVE)
230 gpio_set_value(pdata->chip_sel[chip_sel], 0); 232 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH);
231 else 233 else
232 gpio_set_value(pdata->chip_sel[chip_sel], 1); 234 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH));
233 } else { 235 } else {
234 if (value == BITBANG_CS_ACTIVE) { 236 if (value == BITBANG_CS_ACTIVE) {
235 spidat1 |= SPIDAT1_CSHOLD_MASK; 237 spidat1 |= SPIDAT1_CSHOLD_MASK;
@@ -392,17 +394,40 @@ static int davinci_spi_setup(struct spi_device *spi)
392 int retval = 0; 394 int retval = 0;
393 struct davinci_spi *dspi; 395 struct davinci_spi *dspi;
394 struct davinci_spi_platform_data *pdata; 396 struct davinci_spi_platform_data *pdata;
397 struct spi_master *master = spi->master;
398 struct device_node *np = spi->dev.of_node;
399 bool internal_cs = true;
400 unsigned long flags = GPIOF_DIR_OUT;
395 401
396 dspi = spi_master_get_devdata(spi->master); 402 dspi = spi_master_get_devdata(spi->master);
397 pdata = &dspi->pdata; 403 pdata = &dspi->pdata;
398 404
405 flags |= (spi->mode & SPI_CS_HIGH) ? GPIOF_INIT_LOW : GPIOF_INIT_HIGH;
406
399 if (!(spi->mode & SPI_NO_CS)) { 407 if (!(spi->mode & SPI_NO_CS)) {
400 if ((pdata->chip_sel == NULL) || 408 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
401 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) 409 retval = gpio_request_one(spi->cs_gpio,
402 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 410 flags, dev_name(&spi->dev));
411 internal_cs = false;
412 } else if (pdata->chip_sel &&
413 spi->chip_select < pdata->num_chipselect &&
414 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
415 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
416 retval = gpio_request_one(spi->cs_gpio,
417 flags, dev_name(&spi->dev));
418 internal_cs = false;
419 }
420 }
403 421
422 if (retval) {
423 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
424 spi->cs_gpio, retval);
425 return retval;
404 } 426 }
405 427
428 if (internal_cs)
429 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
430
406 if (spi->mode & SPI_READY) 431 if (spi->mode & SPI_READY)
407 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 432 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
408 433
@@ -414,6 +439,12 @@ static int davinci_spi_setup(struct spi_device *spi)
414 return retval; 439 return retval;
415} 440}
416 441
442static void davinci_spi_cleanup(struct spi_device *spi)
443{
444 if (spi->cs_gpio >= 0)
445 gpio_free(spi->cs_gpio);
446}
447
417static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) 448static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
418{ 449{
419 struct device *sdev = dspi->bitbang.master->dev.parent; 450 struct device *sdev = dspi->bitbang.master->dev.parent;
@@ -812,6 +843,8 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
812 843
813 /* 844 /*
814 * default num_cs is 1 and all chipsel are internal to the chip 845 * default num_cs is 1 and all chipsel are internal to the chip
846 * indicated by chip_sel being NULL or cs_gpios being NULL or
847 * set to -ENOENT. num-cs includes internal as well as gpios.
815 * indicated by chip_sel being NULL. GPIO based CS is not 848 * indicated by chip_sel being NULL. GPIO based CS is not
816 * supported yet in DT bindings. 849 * supported yet in DT bindings.
817 */ 850 */
@@ -850,7 +883,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
850 struct resource *r; 883 struct resource *r;
851 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 884 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
852 resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 885 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
853 int i = 0, ret = 0; 886 int ret = 0;
854 u32 spipc0; 887 u32 spipc0;
855 888
856 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); 889 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
@@ -876,6 +909,14 @@ static int davinci_spi_probe(struct platform_device *pdev)
876 /* pdata in dspi is now updated and point pdata to that */ 909 /* pdata in dspi is now updated and point pdata to that */
877 pdata = &dspi->pdata; 910 pdata = &dspi->pdata;
878 911
912 dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
913 sizeof(*dspi->bytes_per_word) *
914 pdata->num_chipselect, GFP_KERNEL);
915 if (dspi->bytes_per_word == NULL) {
916 ret = -ENOMEM;
917 goto free_master;
918 }
919
879 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 920 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880 if (r == NULL) { 921 if (r == NULL) {
881 ret = -ENOENT; 922 ret = -ENOENT;
@@ -915,6 +956,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
915 master->num_chipselect = pdata->num_chipselect; 956 master->num_chipselect = pdata->num_chipselect;
916 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); 957 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
917 master->setup = davinci_spi_setup; 958 master->setup = davinci_spi_setup;
959 master->cleanup = davinci_spi_cleanup;
918 960
919 dspi->bitbang.chipselect = davinci_spi_chipselect; 961 dspi->bitbang.chipselect = davinci_spi_chipselect;
920 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; 962 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
@@ -962,14 +1004,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
962 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; 1004 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
963 iowrite32(spipc0, dspi->base + SPIPC0); 1005 iowrite32(spipc0, dspi->base + SPIPC0);
964 1006
965 /* initialize chip selects */
966 if (pdata->chip_sel) {
967 for (i = 0; i < pdata->num_chipselect; i++) {
968 if (pdata->chip_sel[i] != SPI_INTERN_CS)
969 gpio_direction_output(pdata->chip_sel[i], 1);
970 }
971 }
972
973 if (pdata->intr_line) 1007 if (pdata->intr_line)
974 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); 1008 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
975 else 1009 else
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index a5cba14ac3d2..21ce0e36fa00 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -16,7 +16,9 @@
16#include <linux/spi/spi.h> 16#include <linux/spi/spi.h>
17#include <linux/scatterlist.h> 17#include <linux/scatterlist.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/of.h>
19#include <linux/of_gpio.h> 20#include <linux/of_gpio.h>
21#include <linux/of_platform.h>
20 22
21#include "spi-dw.h" 23#include "spi-dw.h"
22 24
@@ -33,6 +35,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
33 struct dw_spi *dws; 35 struct dw_spi *dws;
34 struct resource *mem; 36 struct resource *mem;
35 int ret; 37 int ret;
38 int num_cs;
36 39
37 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio), 40 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
38 GFP_KERNEL); 41 GFP_KERNEL);
@@ -68,9 +71,16 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
68 return ret; 71 return ret;
69 72
70 dws->bus_num = pdev->id; 73 dws->bus_num = pdev->id;
71 dws->num_cs = 4; 74
72 dws->max_freq = clk_get_rate(dwsmmio->clk); 75 dws->max_freq = clk_get_rate(dwsmmio->clk);
73 76
77 num_cs = 4;
78
79 if (pdev->dev.of_node)
80 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
81
82 dws->num_cs = num_cs;
83
74 if (pdev->dev.of_node) { 84 if (pdev->dev.of_node) {
75 int i; 85 int i;
76 86
@@ -114,12 +124,19 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
114 return 0; 124 return 0;
115} 125}
116 126
127static const struct of_device_id dw_spi_mmio_of_match[] = {
128 { .compatible = "snps,dw-apb-ssi", },
129 { /* end of table */}
130};
131MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
132
117static struct platform_driver dw_spi_mmio_driver = { 133static struct platform_driver dw_spi_mmio_driver = {
118 .probe = dw_spi_mmio_probe, 134 .probe = dw_spi_mmio_probe,
119 .remove = dw_spi_mmio_remove, 135 .remove = dw_spi_mmio_remove,
120 .driver = { 136 .driver = {
121 .name = DRIVER_NAME, 137 .name = DRIVER_NAME,
122 .owner = THIS_MODULE, 138 .owner = THIS_MODULE,
139 .of_match_table = dw_spi_mmio_of_match,
123 }, 140 },
124}; 141};
125module_platform_driver(dw_spi_mmio_driver); 142module_platform_driver(dw_spi_mmio_driver);
diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c
index be44a3eeb5e8..6caeb1cac0f3 100644
--- a/drivers/spi/spi-efm32.c
+++ b/drivers/spi/spi-efm32.c
@@ -294,10 +294,16 @@ static void efm32_spi_probe_dt(struct platform_device *pdev,
294 u32 location; 294 u32 location;
295 int ret; 295 int ret;
296 296
297 ret = of_property_read_u32(np, "efm32,location", &location); 297 ret = of_property_read_u32(np, "energymicro,location", &location);
298
299 if (ret)
300 /* fall back to wrongly namespaced property */
301 ret = of_property_read_u32(np, "efm32,location", &location);
302
298 if (ret) 303 if (ret)
299 /* fall back to old and (wrongly) generic property "location" */ 304 /* fall back to old and (wrongly) generic property "location" */
300 ret = of_property_read_u32(np, "location", &location); 305 ret = of_property_read_u32(np, "location", &location);
306
301 if (!ret) { 307 if (!ret) {
302 dev_dbg(&pdev->dev, "using location %u\n", location); 308 dev_dbg(&pdev->dev, "using location %u\n", location);
303 } else { 309 } else {
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index ba441ad9a007..f73b3004d6d3 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -425,8 +425,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
425 master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer; 425 master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer;
426 master->dev.of_node = pdev->dev.of_node; 426 master->dev.of_node = pdev->dev.of_node;
427 427
428 platform_set_drvdata(pdev, priv);
429
430 ret = devm_spi_register_master(&pdev->dev, master); 428 ret = devm_spi_register_master(&pdev->dev, master);
431 if (ret) 429 if (ret)
432 spi_master_put(master); 430 spi_master_put(master);
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 95212ea96c8d..e0b773fc29cb 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -196,7 +196,7 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
196 196
197 pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL); 197 pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
198 if (!pinfo) 198 if (!pinfo)
199 return -ENOMEM; 199 return ret;
200 200
201 pdata = &pinfo->pdata; 201 pdata = &pinfo->pdata;
202 dev->platform_data = pdata; 202 dev->platform_data = pdata;
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 98ccd231bf00..9452f6740997 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -58,7 +58,7 @@ static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
58 .type = TYPE_GRLIB, 58 .type = TYPE_GRLIB,
59}; 59};
60 60
61static struct of_device_id of_fsl_spi_match[] = { 61static const struct of_device_id of_fsl_spi_match[] = {
62 { 62 {
63 .compatible = "fsl,spi", 63 .compatible = "fsl,spi",
64 .data = &of_fsl_spi_fsl_config, 64 .data = &of_fsl_spi_fsl_config,
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index e7ffcded4e14..5e91858f6f01 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -420,8 +420,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
420 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16); 420 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
421 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ; 421 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
422 422
423 platform_set_drvdata(pdev, master);
424
425 spi100k = spi_master_get_devdata(master); 423 spi100k = spi_master_get_devdata(master);
426 424
427 /* 425 /*
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 0f5a0aa3b871..8bca90a19dd1 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -41,14 +41,15 @@
41#include <linux/err.h> 41#include <linux/err.h>
42#include <linux/clk.h> 42#include <linux/clk.h>
43#include <linux/slab.h> 43#include <linux/slab.h>
44#include <linux/device.h>
44 45
45#include <linux/spi/spi.h> 46#include <linux/spi/spi.h>
46#include <linux/spi/spi_bitbang.h> 47#include <linux/spi/spi_bitbang.h>
47#include <linux/module.h> 48#include <linux/module.h>
49#include <linux/io.h>
48 50
49#include <asm/irq.h> 51#include <asm/irq.h>
50#include <mach/hardware.h> 52#include <mach/hardware.h>
51#include <asm/io.h>
52#include <asm/mach-types.h> 53#include <asm/mach-types.h>
53 54
54#include <mach/mux.h> 55#include <mach/mux.h>
@@ -447,7 +448,6 @@ static void uwire_off(struct uwire_spi *uwire)
447{ 448{
448 uwire_write_reg(UWIRE_SR3, 0); 449 uwire_write_reg(UWIRE_SR3, 0);
449 clk_disable(uwire->ck); 450 clk_disable(uwire->ck);
450 clk_put(uwire->ck);
451 spi_master_put(uwire->bitbang.master); 451 spi_master_put(uwire->bitbang.master);
452} 452}
453 453
@@ -463,7 +463,7 @@ static int uwire_probe(struct platform_device *pdev)
463 463
464 uwire = spi_master_get_devdata(master); 464 uwire = spi_master_get_devdata(master);
465 465
466 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE); 466 uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
467 if (!uwire_base) { 467 if (!uwire_base) {
468 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n"); 468 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
469 spi_master_put(master); 469 spi_master_put(master);
@@ -472,12 +472,11 @@ static int uwire_probe(struct platform_device *pdev)
472 472
473 platform_set_drvdata(pdev, uwire); 473 platform_set_drvdata(pdev, uwire);
474 474
475 uwire->ck = clk_get(&pdev->dev, "fck"); 475 uwire->ck = devm_clk_get(&pdev->dev, "fck");
476 if (IS_ERR(uwire->ck)) { 476 if (IS_ERR(uwire->ck)) {
477 status = PTR_ERR(uwire->ck); 477 status = PTR_ERR(uwire->ck);
478 dev_dbg(&pdev->dev, "no functional clock?\n"); 478 dev_dbg(&pdev->dev, "no functional clock?\n");
479 spi_master_put(master); 479 spi_master_put(master);
480 iounmap(uwire_base);
481 return status; 480 return status;
482 } 481 }
483 clk_enable(uwire->ck); 482 clk_enable(uwire->ck);
@@ -507,7 +506,6 @@ static int uwire_probe(struct platform_device *pdev)
507 status = spi_bitbang_start(&uwire->bitbang); 506 status = spi_bitbang_start(&uwire->bitbang);
508 if (status < 0) { 507 if (status < 0) {
509 uwire_off(uwire); 508 uwire_off(uwire);
510 iounmap(uwire_base);
511 } 509 }
512 return status; 510 return status;
513} 511}
@@ -520,7 +518,6 @@ static int uwire_remove(struct platform_device *pdev)
520 518
521 spi_bitbang_stop(&uwire->bitbang); 519 spi_bitbang_stop(&uwire->bitbang);
522 uwire_off(uwire); 520 uwire_off(uwire);
523 iounmap(uwire_base);
524 return 0; 521 return 0;
525} 522}
526 523
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 4dc77df38864..68441fa448de 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -149,6 +149,7 @@ struct omap2_mcspi_cs {
149 void __iomem *base; 149 void __iomem *base;
150 unsigned long phys; 150 unsigned long phys;
151 int word_len; 151 int word_len;
152 u16 mode;
152 struct list_head node; 153 struct list_head node;
153 /* Context save and restore shadow register */ 154 /* Context save and restore shadow register */
154 u32 chconf0, chctrl0; 155 u32 chconf0, chctrl0;
@@ -926,6 +927,8 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
926 927
927 mcspi_write_chconf0(spi, l); 928 mcspi_write_chconf0(spi, l);
928 929
930 cs->mode = spi->mode;
931
929 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 932 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
930 speed_hz, 933 speed_hz,
931 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 934 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
@@ -998,6 +1001,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
998 return -ENOMEM; 1001 return -ENOMEM;
999 cs->base = mcspi->base + spi->chip_select * 0x14; 1002 cs->base = mcspi->base + spi->chip_select * 0x14;
1000 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1003 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1004 cs->mode = 0;
1001 cs->chconf0 = 0; 1005 cs->chconf0 = 0;
1002 cs->chctrl0 = 0; 1006 cs->chctrl0 = 0;
1003 spi->controller_state = cs; 1007 spi->controller_state = cs;
@@ -1079,6 +1083,16 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1079 cs = spi->controller_state; 1083 cs = spi->controller_state;
1080 cd = spi->controller_data; 1084 cd = spi->controller_data;
1081 1085
1086 /*
1087 * The slave driver could have changed spi->mode in which case
1088 * it will be different from cs->mode (the current hardware setup).
1089 * If so, set par_override (even though its not a parity issue) so
1090 * omap2_mcspi_setup_transfer will be called to configure the hardware
1091 * with the correct mode on the first iteration of the loop below.
1092 */
1093 if (spi->mode != cs->mode)
1094 par_override = 1;
1095
1082 omap2_mcspi_set_enable(spi, 0); 1096 omap2_mcspi_set_enable(spi, 0);
1083 list_for_each_entry(t, &m->transfers, transfer_list) { 1097 list_for_each_entry(t, &m->transfers, transfer_list) {
1084 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { 1098 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index d018a4aac3a1..c4675fa8b645 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/spi/spi.h> 17#include <linux/spi/spi.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/pm_runtime.h>
19#include <linux/of.h> 20#include <linux/of.h>
20#include <linux/clk.h> 21#include <linux/clk.h>
21#include <linux/sizes.h> 22#include <linux/sizes.h>
@@ -23,6 +24,9 @@
23 24
24#define DRIVER_NAME "orion_spi" 25#define DRIVER_NAME "orion_spi"
25 26
27/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
28#define SPI_AUTOSUSPEND_TIMEOUT 200
29
26#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/ 30#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
27#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 31#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
28 32
@@ -277,7 +281,6 @@ out:
277 return xfer->len - count; 281 return xfer->len - count;
278} 282}
279 283
280
281static int orion_spi_transfer_one_message(struct spi_master *master, 284static int orion_spi_transfer_one_message(struct spi_master *master,
282 struct spi_message *m) 285 struct spi_message *m)
283{ 286{
@@ -346,8 +349,6 @@ static int orion_spi_probe(struct platform_device *pdev)
346 struct resource *r; 349 struct resource *r;
347 unsigned long tclk_hz; 350 unsigned long tclk_hz;
348 int status = 0; 351 int status = 0;
349 const u32 *iprop;
350 int size;
351 352
352 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 353 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
353 if (master == NULL) { 354 if (master == NULL) {
@@ -358,10 +359,10 @@ static int orion_spi_probe(struct platform_device *pdev)
358 if (pdev->id != -1) 359 if (pdev->id != -1)
359 master->bus_num = pdev->id; 360 master->bus_num = pdev->id;
360 if (pdev->dev.of_node) { 361 if (pdev->dev.of_node) {
361 iprop = of_get_property(pdev->dev.of_node, "cell-index", 362 u32 cell_index;
362 &size); 363 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
363 if (iprop && size == sizeof(*iprop)) 364 &cell_index))
364 master->bus_num = *iprop; 365 master->bus_num = cell_index;
365 } 366 }
366 367
367 /* we support only mode 0, and no options */ 368 /* we support only mode 0, and no options */
@@ -370,6 +371,7 @@ static int orion_spi_probe(struct platform_device *pdev)
370 master->transfer_one_message = orion_spi_transfer_one_message; 371 master->transfer_one_message = orion_spi_transfer_one_message;
371 master->num_chipselect = ORION_NUM_CHIPSELECTS; 372 master->num_chipselect = ORION_NUM_CHIPSELECTS;
372 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 373 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
374 master->auto_runtime_pm = true;
373 375
374 platform_set_drvdata(pdev, master); 376 platform_set_drvdata(pdev, master);
375 377
@@ -382,8 +384,10 @@ static int orion_spi_probe(struct platform_device *pdev)
382 goto out; 384 goto out;
383 } 385 }
384 386
385 clk_prepare(spi->clk); 387 status = clk_prepare_enable(spi->clk);
386 clk_enable(spi->clk); 388 if (status)
389 goto out;
390
387 tclk_hz = clk_get_rate(spi->clk); 391 tclk_hz = clk_get_rate(spi->clk);
388 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4); 392 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
389 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30); 393 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
@@ -395,16 +399,27 @@ static int orion_spi_probe(struct platform_device *pdev)
395 goto out_rel_clk; 399 goto out_rel_clk;
396 } 400 }
397 401
398 if (orion_spi_reset(spi) < 0) 402 pm_runtime_set_active(&pdev->dev);
399 goto out_rel_clk; 403 pm_runtime_use_autosuspend(&pdev->dev);
404 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
405 pm_runtime_enable(&pdev->dev);
406
407 status = orion_spi_reset(spi);
408 if (status < 0)
409 goto out_rel_pm;
410
411 pm_runtime_mark_last_busy(&pdev->dev);
412 pm_runtime_put_autosuspend(&pdev->dev);
400 413
401 master->dev.of_node = pdev->dev.of_node; 414 master->dev.of_node = pdev->dev.of_node;
402 status = devm_spi_register_master(&pdev->dev, master); 415 status = spi_register_master(master);
403 if (status < 0) 416 if (status < 0)
404 goto out_rel_clk; 417 goto out_rel_pm;
405 418
406 return status; 419 return status;
407 420
421out_rel_pm:
422 pm_runtime_disable(&pdev->dev);
408out_rel_clk: 423out_rel_clk:
409 clk_disable_unprepare(spi->clk); 424 clk_disable_unprepare(spi->clk);
410out: 425out:
@@ -415,19 +430,45 @@ out:
415 430
416static int orion_spi_remove(struct platform_device *pdev) 431static int orion_spi_remove(struct platform_device *pdev)
417{ 432{
418 struct spi_master *master; 433 struct spi_master *master = platform_get_drvdata(pdev);
419 struct orion_spi *spi; 434 struct orion_spi *spi = spi_master_get_devdata(master);
420
421 master = platform_get_drvdata(pdev);
422 spi = spi_master_get_devdata(master);
423 435
436 pm_runtime_get_sync(&pdev->dev);
424 clk_disable_unprepare(spi->clk); 437 clk_disable_unprepare(spi->clk);
425 438
439 spi_unregister_master(master);
440 pm_runtime_disable(&pdev->dev);
441
426 return 0; 442 return 0;
427} 443}
428 444
429MODULE_ALIAS("platform:" DRIVER_NAME); 445MODULE_ALIAS("platform:" DRIVER_NAME);
430 446
447#ifdef CONFIG_PM_RUNTIME
448static int orion_spi_runtime_suspend(struct device *dev)
449{
450 struct spi_master *master = dev_get_drvdata(dev);
451 struct orion_spi *spi = spi_master_get_devdata(master);
452
453 clk_disable_unprepare(spi->clk);
454 return 0;
455}
456
457static int orion_spi_runtime_resume(struct device *dev)
458{
459 struct spi_master *master = dev_get_drvdata(dev);
460 struct orion_spi *spi = spi_master_get_devdata(master);
461
462 return clk_prepare_enable(spi->clk);
463}
464#endif
465
466static const struct dev_pm_ops orion_spi_pm_ops = {
467 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
468 orion_spi_runtime_resume,
469 NULL)
470};
471
431static const struct of_device_id orion_spi_of_match_table[] = { 472static const struct of_device_id orion_spi_of_match_table[] = {
432 { .compatible = "marvell,orion-spi", }, 473 { .compatible = "marvell,orion-spi", },
433 {} 474 {}
@@ -438,6 +479,7 @@ static struct platform_driver orion_spi_driver = {
438 .driver = { 479 .driver = {
439 .name = DRIVER_NAME, 480 .name = DRIVER_NAME,
440 .owner = THIS_MODULE, 481 .owner = THIS_MODULE,
482 .pm = &orion_spi_pm_ops,
441 .of_match_table = of_match_ptr(orion_spi_of_match_table), 483 .of_match_table = of_match_ptr(orion_spi_of_match_table),
442 }, 484 },
443 .probe = orion_spi_probe, 485 .probe = orion_spi_probe,
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 66d2ae21e78e..1189cfd96477 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1417,7 +1417,7 @@ static void do_interrupt_dma_transfer(struct pl022 *pl022)
1417 * Default is to enable all interrupts except RX - 1417 * Default is to enable all interrupts except RX -
1418 * this will be enabled once TX is complete 1418 * this will be enabled once TX is complete
1419 */ 1419 */
1420 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1420 u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
1421 1421
1422 /* Enable target chip, if not already active */ 1422 /* Enable target chip, if not already active */
1423 if (!pl022->next_msg_cs_active) 1423 if (!pl022->next_msg_cs_active)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index c08da380cb23..9f83d2950748 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -142,6 +142,7 @@ struct spi_qup {
142 int w_size; /* bytes per SPI word */ 142 int w_size; /* bytes per SPI word */
143 int tx_bytes; 143 int tx_bytes;
144 int rx_bytes; 144 int rx_bytes;
145 int qup_v1;
145}; 146};
146 147
147 148
@@ -420,7 +421,9 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
420 config |= QUP_CONFIG_SPI_MODE; 421 config |= QUP_CONFIG_SPI_MODE;
421 writel_relaxed(config, controller->base + QUP_CONFIG); 422 writel_relaxed(config, controller->base + QUP_CONFIG);
422 423
423 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK); 424 /* only write to OPERATIONAL_MASK when register is present */
425 if (!controller->qup_v1)
426 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
424 return 0; 427 return 0;
425} 428}
426 429
@@ -486,7 +489,7 @@ static int spi_qup_probe(struct platform_device *pdev)
486 struct resource *res; 489 struct resource *res;
487 struct device *dev; 490 struct device *dev;
488 void __iomem *base; 491 void __iomem *base;
489 u32 data, max_freq, iomode; 492 u32 max_freq, iomode;
490 int ret, irq, size; 493 int ret, irq, size;
491 494
492 dev = &pdev->dev; 495 dev = &pdev->dev;
@@ -529,15 +532,6 @@ static int spi_qup_probe(struct platform_device *pdev)
529 return ret; 532 return ret;
530 } 533 }
531 534
532 data = readl_relaxed(base + QUP_HW_VERSION);
533
534 if (data < QUP_HW_VERSION_2_1_1) {
535 clk_disable_unprepare(cclk);
536 clk_disable_unprepare(iclk);
537 dev_err(dev, "v.%08x is not supported\n", data);
538 return -ENXIO;
539 }
540
541 master = spi_alloc_master(dev, sizeof(struct spi_qup)); 535 master = spi_alloc_master(dev, sizeof(struct spi_qup));
542 if (!master) { 536 if (!master) {
543 clk_disable_unprepare(cclk); 537 clk_disable_unprepare(cclk);
@@ -570,6 +564,10 @@ static int spi_qup_probe(struct platform_device *pdev)
570 controller->cclk = cclk; 564 controller->cclk = cclk;
571 controller->irq = irq; 565 controller->irq = irq;
572 566
567 /* set v1 flag if device is version 1 */
568 if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
569 controller->qup_v1 = 1;
570
573 spin_lock_init(&controller->lock); 571 spin_lock_init(&controller->lock);
574 init_completion(&controller->done); 572 init_completion(&controller->done);
575 573
@@ -593,8 +591,8 @@ static int spi_qup_probe(struct platform_device *pdev)
593 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); 591 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
594 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); 592 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
595 593
596 dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", 594 dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
597 data, controller->in_blk_sz, controller->in_fifo_sz, 595 controller->in_blk_sz, controller->in_fifo_sz,
598 controller->out_blk_sz, controller->out_fifo_sz); 596 controller->out_blk_sz, controller->out_fifo_sz);
599 597
600 writel_relaxed(1, base + QUP_SW_RESET); 598 writel_relaxed(1, base + QUP_SW_RESET);
@@ -607,10 +605,19 @@ static int spi_qup_probe(struct platform_device *pdev)
607 605
608 writel_relaxed(0, base + QUP_OPERATIONAL); 606 writel_relaxed(0, base + QUP_OPERATIONAL);
609 writel_relaxed(0, base + QUP_IO_M_MODES); 607 writel_relaxed(0, base + QUP_IO_M_MODES);
610 writel_relaxed(0, base + QUP_OPERATIONAL_MASK); 608
609 if (!controller->qup_v1)
610 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
611
611 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, 612 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
612 base + SPI_ERROR_FLAGS_EN); 613 base + SPI_ERROR_FLAGS_EN);
613 614
615 /* if earlier version of the QUP, disable INPUT_OVERRUN */
616 if (controller->qup_v1)
617 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
618 QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
619 base + QUP_ERROR_FLAGS_EN);
620
614 writel_relaxed(0, base + SPI_CONFIG); 621 writel_relaxed(0, base + SPI_CONFIG);
615 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); 622 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
616 623
@@ -732,6 +739,7 @@ static int spi_qup_remove(struct platform_device *pdev)
732} 739}
733 740
734static const struct of_device_id spi_qup_dt_match[] = { 741static const struct of_device_id spi_qup_dt_match[] = {
742 { .compatible = "qcom,spi-qup-v1.1.1", },
735 { .compatible = "qcom,spi-qup-v2.1.1", }, 743 { .compatible = "qcom,spi-qup-v2.1.1", },
736 { .compatible = "qcom,spi-qup-v2.2.1", }, 744 { .compatible = "qcom,spi-qup-v2.2.1", },
737 { } 745 { }
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
new file mode 100644
index 000000000000..c0743604b906
--- /dev/null
+++ b/drivers/spi/spi-rockchip.c
@@ -0,0 +1,837 @@
1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/spi/spi.h>
25#include <linux/scatterlist.h>
26#include <linux/of.h>
27#include <linux/pm_runtime.h>
28#include <linux/io.h>
29#include <linux/dmaengine.h>
30
31#define DRIVER_NAME "rockchip-spi"
32
33/* SPI register offsets */
34#define ROCKCHIP_SPI_CTRLR0 0x0000
35#define ROCKCHIP_SPI_CTRLR1 0x0004
36#define ROCKCHIP_SPI_SSIENR 0x0008
37#define ROCKCHIP_SPI_SER 0x000c
38#define ROCKCHIP_SPI_BAUDR 0x0010
39#define ROCKCHIP_SPI_TXFTLR 0x0014
40#define ROCKCHIP_SPI_RXFTLR 0x0018
41#define ROCKCHIP_SPI_TXFLR 0x001c
42#define ROCKCHIP_SPI_RXFLR 0x0020
43#define ROCKCHIP_SPI_SR 0x0024
44#define ROCKCHIP_SPI_IPR 0x0028
45#define ROCKCHIP_SPI_IMR 0x002c
46#define ROCKCHIP_SPI_ISR 0x0030
47#define ROCKCHIP_SPI_RISR 0x0034
48#define ROCKCHIP_SPI_ICR 0x0038
49#define ROCKCHIP_SPI_DMACR 0x003c
50#define ROCKCHIP_SPI_DMATDLR 0x0040
51#define ROCKCHIP_SPI_DMARDLR 0x0044
52#define ROCKCHIP_SPI_TXDR 0x0400
53#define ROCKCHIP_SPI_RXDR 0x0800
54
55/* Bit fields in CTRLR0 */
56#define CR0_DFS_OFFSET 0
57
58#define CR0_CFS_OFFSET 2
59
60#define CR0_SCPH_OFFSET 6
61
62#define CR0_SCPOL_OFFSET 7
63
64#define CR0_CSM_OFFSET 8
65#define CR0_CSM_KEEP 0x0
66/* ss_n be high for half sclk_out cycles */
67#define CR0_CSM_HALF 0X1
68/* ss_n be high for one sclk_out cycle */
69#define CR0_CSM_ONE 0x2
70
71/* ss_n to sclk_out delay */
72#define CR0_SSD_OFFSET 10
73/*
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
76 */
77#define CR0_SSD_HALF 0x0
78/*
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
81 */
82#define CR0_SSD_ONE 0x1
83
84#define CR0_EM_OFFSET 11
85#define CR0_EM_LITTLE 0x0
86#define CR0_EM_BIG 0x1
87
88#define CR0_FBM_OFFSET 12
89#define CR0_FBM_MSB 0x0
90#define CR0_FBM_LSB 0x1
91
92#define CR0_BHT_OFFSET 13
93#define CR0_BHT_16BIT 0x0
94#define CR0_BHT_8BIT 0x1
95
96#define CR0_RSD_OFFSET 14
97
98#define CR0_FRF_OFFSET 16
99#define CR0_FRF_SPI 0x0
100#define CR0_FRF_SSP 0x1
101#define CR0_FRF_MICROWIRE 0x2
102
103#define CR0_XFM_OFFSET 18
104#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105#define CR0_XFM_TR 0x0
106#define CR0_XFM_TO 0x1
107#define CR0_XFM_RO 0x2
108
109#define CR0_OPM_OFFSET 20
110#define CR0_OPM_MASTER 0x0
111#define CR0_OPM_SLAVE 0x1
112
113#define CR0_MTM_OFFSET 0x21
114
115/* Bit fields in SER, 2bit */
116#define SER_MASK 0x3
117
118/* Bit fields in SR, 5bit */
119#define SR_MASK 0x1f
120#define SR_BUSY (1 << 0)
121#define SR_TF_FULL (1 << 1)
122#define SR_TF_EMPTY (1 << 2)
123#define SR_RF_EMPTY (1 << 3)
124#define SR_RF_FULL (1 << 4)
125
126/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127#define INT_MASK 0x1f
128#define INT_TF_EMPTY (1 << 0)
129#define INT_TF_OVERFLOW (1 << 1)
130#define INT_RF_UNDERFLOW (1 << 2)
131#define INT_RF_OVERFLOW (1 << 3)
132#define INT_RF_FULL (1 << 4)
133
134/* Bit fields in ICR, 4bit */
135#define ICR_MASK 0x0f
136#define ICR_ALL (1 << 0)
137#define ICR_RF_UNDERFLOW (1 << 1)
138#define ICR_RF_OVERFLOW (1 << 2)
139#define ICR_TF_OVERFLOW (1 << 3)
140
141/* Bit fields in DMACR */
142#define RF_DMA_EN (1 << 0)
143#define TF_DMA_EN (1 << 1)
144
145#define RXBUSY (1 << 0)
146#define TXBUSY (1 << 1)
147
148enum rockchip_ssi_type {
149 SSI_MOTO_SPI = 0,
150 SSI_TI_SSP,
151 SSI_NS_MICROWIRE,
152};
153
154struct rockchip_spi_dma_data {
155 struct dma_chan *ch;
156 enum dma_transfer_direction direction;
157 dma_addr_t addr;
158};
159
160struct rockchip_spi {
161 struct device *dev;
162 struct spi_master *master;
163
164 struct clk *spiclk;
165 struct clk *apb_pclk;
166
167 void __iomem *regs;
168 /*depth of the FIFO buffer */
169 u32 fifo_len;
170 /* max bus freq supported */
171 u32 max_freq;
172 /* supported slave numbers */
173 enum rockchip_ssi_type type;
174
175 u16 mode;
176 u8 tmode;
177 u8 bpw;
178 u8 n_bytes;
179 unsigned len;
180 u32 speed;
181
182 const void *tx;
183 const void *tx_end;
184 void *rx;
185 void *rx_end;
186
187 u32 state;
188 /* protect state */
189 spinlock_t lock;
190
191 struct completion xfer_completion;
192
193 u32 use_dma;
194 struct sg_table tx_sg;
195 struct sg_table rx_sg;
196 struct rockchip_spi_dma_data dma_rx;
197 struct rockchip_spi_dma_data dma_tx;
198};
199
200static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
201{
202 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
203}
204
205static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
206{
207 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
208}
209
210static inline void flush_fifo(struct rockchip_spi *rs)
211{
212 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
213 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
214}
215
216static inline void wait_for_idle(struct rockchip_spi *rs)
217{
218 unsigned long timeout = jiffies + msecs_to_jiffies(5);
219
220 do {
221 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
222 return;
223 } while (time_before(jiffies, timeout));
224
225 dev_warn(rs->dev, "spi controller is in busy state!\n");
226}
227
228static u32 get_fifo_len(struct rockchip_spi *rs)
229{
230 u32 fifo;
231
232 for (fifo = 2; fifo < 32; fifo++) {
233 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
234 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
235 break;
236 }
237
238 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
239
240 return (fifo == 31) ? 0 : fifo;
241}
242
243static inline u32 tx_max(struct rockchip_spi *rs)
244{
245 u32 tx_left, tx_room;
246
247 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
248 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
249
250 return min(tx_left, tx_room);
251}
252
253static inline u32 rx_max(struct rockchip_spi *rs)
254{
255 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
256 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
257
258 return min(rx_left, rx_room);
259}
260
261static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
262{
263 u32 ser;
264 struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
265
266 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
267
268 /*
269 * drivers/spi/spi.c:
270 * static void spi_set_cs(struct spi_device *spi, bool enable)
271 * {
272 * if (spi->mode & SPI_CS_HIGH)
273 * enable = !enable;
274 *
275 * if (spi->cs_gpio >= 0)
276 * gpio_set_value(spi->cs_gpio, !enable);
277 * else if (spi->master->set_cs)
278 * spi->master->set_cs(spi, !enable);
279 * }
280 *
281 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
282 */
283 if (!enable)
284 ser |= 1 << spi->chip_select;
285 else
286 ser &= ~(1 << spi->chip_select);
287
288 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
289}
290
291static int rockchip_spi_prepare_message(struct spi_master *master,
292 struct spi_message *msg)
293{
294 struct rockchip_spi *rs = spi_master_get_devdata(master);
295 struct spi_device *spi = msg->spi;
296
297 rs->mode = spi->mode;
298
299 return 0;
300}
301
302static int rockchip_spi_unprepare_message(struct spi_master *master,
303 struct spi_message *msg)
304{
305 unsigned long flags;
306 struct rockchip_spi *rs = spi_master_get_devdata(master);
307
308 spin_lock_irqsave(&rs->lock, flags);
309
310 /*
311 * For DMA mode, we need terminate DMA channel and flush
312 * fifo for the next transfer if DMA thansfer timeout.
313 * unprepare_message() was called by core if transfer complete
314 * or timeout. Maybe it is reasonable for error handling here.
315 */
316 if (rs->use_dma) {
317 if (rs->state & RXBUSY) {
318 dmaengine_terminate_all(rs->dma_rx.ch);
319 flush_fifo(rs);
320 }
321
322 if (rs->state & TXBUSY)
323 dmaengine_terminate_all(rs->dma_tx.ch);
324 }
325
326 spin_unlock_irqrestore(&rs->lock, flags);
327
328 return 0;
329}
330
331static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
332{
333 u32 max = tx_max(rs);
334 u32 txw = 0;
335
336 while (max--) {
337 if (rs->n_bytes == 1)
338 txw = *(u8 *)(rs->tx);
339 else
340 txw = *(u16 *)(rs->tx);
341
342 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
343 rs->tx += rs->n_bytes;
344 }
345}
346
347static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
348{
349 u32 max = rx_max(rs);
350 u32 rxw;
351
352 while (max--) {
353 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
354 if (rs->n_bytes == 1)
355 *(u8 *)(rs->rx) = (u8)rxw;
356 else
357 *(u16 *)(rs->rx) = (u16)rxw;
358 rs->rx += rs->n_bytes;
359 }
360}
361
362static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
363{
364 int remain = 0;
365
366 do {
367 if (rs->tx) {
368 remain = rs->tx_end - rs->tx;
369 rockchip_spi_pio_writer(rs);
370 }
371
372 if (rs->rx) {
373 remain = rs->rx_end - rs->rx;
374 rockchip_spi_pio_reader(rs);
375 }
376
377 cpu_relax();
378 } while (remain);
379
380 /* If tx, wait until the FIFO data completely. */
381 if (rs->tx)
382 wait_for_idle(rs);
383
384 return 0;
385}
386
387static void rockchip_spi_dma_rxcb(void *data)
388{
389 unsigned long flags;
390 struct rockchip_spi *rs = data;
391
392 spin_lock_irqsave(&rs->lock, flags);
393
394 rs->state &= ~RXBUSY;
395 if (!(rs->state & TXBUSY))
396 spi_finalize_current_transfer(rs->master);
397
398 spin_unlock_irqrestore(&rs->lock, flags);
399}
400
401static void rockchip_spi_dma_txcb(void *data)
402{
403 unsigned long flags;
404 struct rockchip_spi *rs = data;
405
406 /* Wait until the FIFO data completely. */
407 wait_for_idle(rs);
408
409 spin_lock_irqsave(&rs->lock, flags);
410
411 rs->state &= ~TXBUSY;
412 if (!(rs->state & RXBUSY))
413 spi_finalize_current_transfer(rs->master);
414
415 spin_unlock_irqrestore(&rs->lock, flags);
416}
417
418static int rockchip_spi_dma_transfer(struct rockchip_spi *rs)
419{
420 unsigned long flags;
421 struct dma_slave_config rxconf, txconf;
422 struct dma_async_tx_descriptor *rxdesc, *txdesc;
423
424 spin_lock_irqsave(&rs->lock, flags);
425 rs->state &= ~RXBUSY;
426 rs->state &= ~TXBUSY;
427 spin_unlock_irqrestore(&rs->lock, flags);
428
429 if (rs->rx) {
430 rxconf.direction = rs->dma_rx.direction;
431 rxconf.src_addr = rs->dma_rx.addr;
432 rxconf.src_addr_width = rs->n_bytes;
433 rxconf.src_maxburst = rs->n_bytes;
434 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
435
436 rxdesc = dmaengine_prep_slave_sg(
437 rs->dma_rx.ch,
438 rs->rx_sg.sgl, rs->rx_sg.nents,
439 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
440
441 rxdesc->callback = rockchip_spi_dma_rxcb;
442 rxdesc->callback_param = rs;
443 }
444
445 if (rs->tx) {
446 txconf.direction = rs->dma_tx.direction;
447 txconf.dst_addr = rs->dma_tx.addr;
448 txconf.dst_addr_width = rs->n_bytes;
449 txconf.dst_maxburst = rs->n_bytes;
450 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
451
452 txdesc = dmaengine_prep_slave_sg(
453 rs->dma_tx.ch,
454 rs->tx_sg.sgl, rs->tx_sg.nents,
455 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
456
457 txdesc->callback = rockchip_spi_dma_txcb;
458 txdesc->callback_param = rs;
459 }
460
461 /* rx must be started before tx due to spi instinct */
462 if (rs->rx) {
463 spin_lock_irqsave(&rs->lock, flags);
464 rs->state |= RXBUSY;
465 spin_unlock_irqrestore(&rs->lock, flags);
466 dmaengine_submit(rxdesc);
467 dma_async_issue_pending(rs->dma_rx.ch);
468 }
469
470 if (rs->tx) {
471 spin_lock_irqsave(&rs->lock, flags);
472 rs->state |= TXBUSY;
473 spin_unlock_irqrestore(&rs->lock, flags);
474 dmaengine_submit(txdesc);
475 dma_async_issue_pending(rs->dma_tx.ch);
476 }
477
478 return 1;
479}
480
481static void rockchip_spi_config(struct rockchip_spi *rs)
482{
483 u32 div = 0;
484 u32 dmacr = 0;
485
486 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
487 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
488
489 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
490 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
491 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
492 cr0 |= (rs->type << CR0_FRF_OFFSET);
493
494 if (rs->use_dma) {
495 if (rs->tx)
496 dmacr |= TF_DMA_EN;
497 if (rs->rx)
498 dmacr |= RF_DMA_EN;
499 }
500
501 /* div doesn't support odd number */
502 div = rs->max_freq / rs->speed;
503 div = (div + 1) & 0xfffe;
504
505 spi_enable_chip(rs, 0);
506
507 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
508
509 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
510 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
511 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
512
513 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
514 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
515 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
516
517 spi_set_clk(rs, div);
518
519 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
520
521 spi_enable_chip(rs, 1);
522}
523
524static int rockchip_spi_transfer_one(
525 struct spi_master *master,
526 struct spi_device *spi,
527 struct spi_transfer *xfer)
528{
529 int ret = 0;
530 struct rockchip_spi *rs = spi_master_get_devdata(master);
531
532 WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
533
534 if (!xfer->tx_buf && !xfer->rx_buf) {
535 dev_err(rs->dev, "No buffer for transfer\n");
536 return -EINVAL;
537 }
538
539 rs->speed = xfer->speed_hz;
540 rs->bpw = xfer->bits_per_word;
541 rs->n_bytes = rs->bpw >> 3;
542
543 rs->tx = xfer->tx_buf;
544 rs->tx_end = rs->tx + xfer->len;
545 rs->rx = xfer->rx_buf;
546 rs->rx_end = rs->rx + xfer->len;
547 rs->len = xfer->len;
548
549 rs->tx_sg = xfer->tx_sg;
550 rs->rx_sg = xfer->rx_sg;
551
552 if (rs->tx && rs->rx)
553 rs->tmode = CR0_XFM_TR;
554 else if (rs->tx)
555 rs->tmode = CR0_XFM_TO;
556 else if (rs->rx)
557 rs->tmode = CR0_XFM_RO;
558
559 if (master->can_dma && master->can_dma(master, spi, xfer))
560 rs->use_dma = 1;
561 else
562 rs->use_dma = 0;
563
564 rockchip_spi_config(rs);
565
566 if (rs->use_dma)
567 ret = rockchip_spi_dma_transfer(rs);
568 else
569 ret = rockchip_spi_pio_transfer(rs);
570
571 return ret;
572}
573
574static bool rockchip_spi_can_dma(struct spi_master *master,
575 struct spi_device *spi,
576 struct spi_transfer *xfer)
577{
578 struct rockchip_spi *rs = spi_master_get_devdata(master);
579
580 return (xfer->len > rs->fifo_len);
581}
582
583static int rockchip_spi_probe(struct platform_device *pdev)
584{
585 int ret = 0;
586 struct rockchip_spi *rs;
587 struct spi_master *master;
588 struct resource *mem;
589
590 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
591 if (!master)
592 return -ENOMEM;
593
594 platform_set_drvdata(pdev, master);
595
596 rs = spi_master_get_devdata(master);
597 memset(rs, 0, sizeof(struct rockchip_spi));
598
599 /* Get basic io resource and map it */
600 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
601 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
602 if (IS_ERR(rs->regs)) {
603 ret = PTR_ERR(rs->regs);
604 goto err_ioremap_resource;
605 }
606
607 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
608 if (IS_ERR(rs->apb_pclk)) {
609 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
610 ret = PTR_ERR(rs->apb_pclk);
611 goto err_ioremap_resource;
612 }
613
614 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
615 if (IS_ERR(rs->spiclk)) {
616 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
617 ret = PTR_ERR(rs->spiclk);
618 goto err_ioremap_resource;
619 }
620
621 ret = clk_prepare_enable(rs->apb_pclk);
622 if (ret) {
623 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
624 goto err_ioremap_resource;
625 }
626
627 ret = clk_prepare_enable(rs->spiclk);
628 if (ret) {
629 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
630 goto err_spiclk_enable;
631 }
632
633 spi_enable_chip(rs, 0);
634
635 rs->type = SSI_MOTO_SPI;
636 rs->master = master;
637 rs->dev = &pdev->dev;
638 rs->max_freq = clk_get_rate(rs->spiclk);
639
640 rs->fifo_len = get_fifo_len(rs);
641 if (!rs->fifo_len) {
642 dev_err(&pdev->dev, "Failed to get fifo length\n");
643 ret = -EINVAL;
644 goto err_get_fifo_len;
645 }
646
647 spin_lock_init(&rs->lock);
648
649 pm_runtime_set_active(&pdev->dev);
650 pm_runtime_enable(&pdev->dev);
651
652 master->auto_runtime_pm = true;
653 master->bus_num = pdev->id;
654 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
655 master->num_chipselect = 2;
656 master->dev.of_node = pdev->dev.of_node;
657 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
658
659 master->set_cs = rockchip_spi_set_cs;
660 master->prepare_message = rockchip_spi_prepare_message;
661 master->unprepare_message = rockchip_spi_unprepare_message;
662 master->transfer_one = rockchip_spi_transfer_one;
663
664 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
665 if (!rs->dma_tx.ch)
666 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
667
668 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
669 if (!rs->dma_rx.ch) {
670 if (rs->dma_tx.ch) {
671 dma_release_channel(rs->dma_tx.ch);
672 rs->dma_tx.ch = NULL;
673 }
674 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
675 }
676
677 if (rs->dma_tx.ch && rs->dma_rx.ch) {
678 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
679 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
680 rs->dma_tx.direction = DMA_MEM_TO_DEV;
681 rs->dma_tx.direction = DMA_DEV_TO_MEM;
682
683 master->can_dma = rockchip_spi_can_dma;
684 master->dma_tx = rs->dma_tx.ch;
685 master->dma_rx = rs->dma_rx.ch;
686 }
687
688 ret = devm_spi_register_master(&pdev->dev, master);
689 if (ret) {
690 dev_err(&pdev->dev, "Failed to register master\n");
691 goto err_register_master;
692 }
693
694 return 0;
695
696err_register_master:
697 if (rs->dma_tx.ch)
698 dma_release_channel(rs->dma_tx.ch);
699 if (rs->dma_rx.ch)
700 dma_release_channel(rs->dma_rx.ch);
701err_get_fifo_len:
702 clk_disable_unprepare(rs->spiclk);
703err_spiclk_enable:
704 clk_disable_unprepare(rs->apb_pclk);
705err_ioremap_resource:
706 spi_master_put(master);
707
708 return ret;
709}
710
711static int rockchip_spi_remove(struct platform_device *pdev)
712{
713 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
714 struct rockchip_spi *rs = spi_master_get_devdata(master);
715
716 pm_runtime_disable(&pdev->dev);
717
718 clk_disable_unprepare(rs->spiclk);
719 clk_disable_unprepare(rs->apb_pclk);
720
721 if (rs->dma_tx.ch)
722 dma_release_channel(rs->dma_tx.ch);
723 if (rs->dma_rx.ch)
724 dma_release_channel(rs->dma_rx.ch);
725
726 spi_master_put(master);
727
728 return 0;
729}
730
731#ifdef CONFIG_PM_SLEEP
732static int rockchip_spi_suspend(struct device *dev)
733{
734 int ret = 0;
735 struct spi_master *master = dev_get_drvdata(dev);
736 struct rockchip_spi *rs = spi_master_get_devdata(master);
737
738 ret = spi_master_suspend(rs->master);
739 if (ret)
740 return ret;
741
742 if (!pm_runtime_suspended(dev)) {
743 clk_disable_unprepare(rs->spiclk);
744 clk_disable_unprepare(rs->apb_pclk);
745 }
746
747 return ret;
748}
749
750static int rockchip_spi_resume(struct device *dev)
751{
752 int ret = 0;
753 struct spi_master *master = dev_get_drvdata(dev);
754 struct rockchip_spi *rs = spi_master_get_devdata(master);
755
756 if (!pm_runtime_suspended(dev)) {
757 ret = clk_prepare_enable(rs->apb_pclk);
758 if (ret < 0)
759 return ret;
760
761 ret = clk_prepare_enable(rs->spiclk);
762 if (ret < 0) {
763 clk_disable_unprepare(rs->apb_pclk);
764 return ret;
765 }
766 }
767
768 ret = spi_master_resume(rs->master);
769 if (ret < 0) {
770 clk_disable_unprepare(rs->spiclk);
771 clk_disable_unprepare(rs->apb_pclk);
772 }
773
774 return ret;
775}
776#endif /* CONFIG_PM_SLEEP */
777
778#ifdef CONFIG_PM_RUNTIME
779static int rockchip_spi_runtime_suspend(struct device *dev)
780{
781 struct spi_master *master = dev_get_drvdata(dev);
782 struct rockchip_spi *rs = spi_master_get_devdata(master);
783
784 clk_disable_unprepare(rs->spiclk);
785 clk_disable_unprepare(rs->apb_pclk);
786
787 return 0;
788}
789
790static int rockchip_spi_runtime_resume(struct device *dev)
791{
792 int ret;
793 struct spi_master *master = dev_get_drvdata(dev);
794 struct rockchip_spi *rs = spi_master_get_devdata(master);
795
796 ret = clk_prepare_enable(rs->apb_pclk);
797 if (ret)
798 return ret;
799
800 ret = clk_prepare_enable(rs->spiclk);
801 if (ret)
802 clk_disable_unprepare(rs->apb_pclk);
803
804 return ret;
805}
806#endif /* CONFIG_PM_RUNTIME */
807
808static const struct dev_pm_ops rockchip_spi_pm = {
809 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
810 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
811 rockchip_spi_runtime_resume, NULL)
812};
813
814static const struct of_device_id rockchip_spi_dt_match[] = {
815 { .compatible = "rockchip,rk3066-spi", },
816 { .compatible = "rockchip,rk3188-spi", },
817 { .compatible = "rockchip,rk3288-spi", },
818 { },
819};
820MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
821
822static struct platform_driver rockchip_spi_driver = {
823 .driver = {
824 .name = DRIVER_NAME,
825 .owner = THIS_MODULE,
826 .pm = &rockchip_spi_pm,
827 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
828 },
829 .probe = rockchip_spi_probe,
830 .remove = rockchip_spi_remove,
831};
832
833module_platform_driver(rockchip_spi_driver);
834
835MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
836MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
837MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 10112745bb17..c850dfdfa9e3 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -477,7 +477,7 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
477 tx->sgl, tx->nents, DMA_TO_DEVICE, 477 tx->sgl, tx->nents, DMA_TO_DEVICE,
478 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 478 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
479 if (!desc_tx) 479 if (!desc_tx)
480 return -EIO; 480 goto no_dma;
481 481
482 irq_mask |= SPCR_SPTIE; 482 irq_mask |= SPCR_SPTIE;
483 } 483 }
@@ -486,7 +486,7 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
486 rx->sgl, rx->nents, DMA_FROM_DEVICE, 486 rx->sgl, rx->nents, DMA_FROM_DEVICE,
487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
488 if (!desc_rx) 488 if (!desc_rx)
489 return -EIO; 489 goto no_dma;
490 490
491 irq_mask |= SPCR_SPRIE; 491 irq_mask |= SPCR_SPRIE;
492 } 492 }
@@ -540,6 +540,12 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
540 enable_irq(rspi->rx_irq); 540 enable_irq(rspi->rx_irq);
541 541
542 return ret; 542 return ret;
543
544no_dma:
545 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
546 dev_driver_string(&rspi->master->dev),
547 dev_name(&rspi->master->dev));
548 return -EAGAIN;
543} 549}
544 550
545static void rspi_receive_init(const struct rspi_data *rspi) 551static void rspi_receive_init(const struct rspi_data *rspi)
@@ -593,8 +599,10 @@ static int rspi_common_transfer(struct rspi_data *rspi,
593 599
594 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 600 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
595 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ 601 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
596 return rspi_dma_transfer(rspi, &xfer->tx_sg, 602 ret = rspi_dma_transfer(rspi, &xfer->tx_sg,
597 xfer->rx_buf ? &xfer->rx_sg : NULL); 603 xfer->rx_buf ? &xfer->rx_sg : NULL);
604 if (ret != -EAGAIN)
605 return ret;
598 } 606 }
599 607
600 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); 608 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
@@ -630,7 +638,6 @@ static int rspi_rz_transfer_one(struct spi_master *master,
630 struct spi_transfer *xfer) 638 struct spi_transfer *xfer)
631{ 639{
632 struct rspi_data *rspi = spi_master_get_devdata(master); 640 struct rspi_data *rspi = spi_master_get_devdata(master);
633 int ret;
634 641
635 rspi_rz_receive_init(rspi); 642 rspi_rz_receive_init(rspi);
636 643
@@ -649,8 +656,11 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
649{ 656{
650 int ret; 657 int ret;
651 658
652 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) 659 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
653 return rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); 660 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
661 if (ret != -EAGAIN)
662 return ret;
663 }
654 664
655 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len); 665 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
656 if (ret < 0) 666 if (ret < 0)
@@ -664,8 +674,11 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
664 674
665static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) 675static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
666{ 676{
667 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) 677 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
668 return rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); 678 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
679 if (ret != -EAGAIN)
680 return ret;
681 }
669 682
670 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len); 683 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
671} 684}
@@ -927,19 +940,19 @@ static int rspi_request_dma(struct device *dev, struct spi_master *master,
927 return 0; 940 return 0;
928} 941}
929 942
930static void rspi_release_dma(struct rspi_data *rspi) 943static void rspi_release_dma(struct spi_master *master)
931{ 944{
932 if (rspi->master->dma_tx) 945 if (master->dma_tx)
933 dma_release_channel(rspi->master->dma_tx); 946 dma_release_channel(master->dma_tx);
934 if (rspi->master->dma_rx) 947 if (master->dma_rx)
935 dma_release_channel(rspi->master->dma_rx); 948 dma_release_channel(master->dma_rx);
936} 949}
937 950
938static int rspi_remove(struct platform_device *pdev) 951static int rspi_remove(struct platform_device *pdev)
939{ 952{
940 struct rspi_data *rspi = platform_get_drvdata(pdev); 953 struct rspi_data *rspi = platform_get_drvdata(pdev);
941 954
942 rspi_release_dma(rspi); 955 rspi_release_dma(rspi->master);
943 pm_runtime_disable(&pdev->dev); 956 pm_runtime_disable(&pdev->dev);
944 957
945 return 0; 958 return 0;
@@ -1141,7 +1154,7 @@ static int rspi_probe(struct platform_device *pdev)
1141 return 0; 1154 return 0;
1142 1155
1143error3: 1156error3:
1144 rspi_release_dma(rspi); 1157 rspi_release_dma(master);
1145error2: 1158error2:
1146 pm_runtime_disable(&pdev->dev); 1159 pm_runtime_disable(&pdev->dev);
1147error1: 1160error1:
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 75a56968b14c..1c36311935d7 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -197,7 +197,6 @@ struct s3c64xx_spi_driver_data {
197 struct s3c64xx_spi_dma_data tx_dma; 197 struct s3c64xx_spi_dma_data tx_dma;
198 struct s3c64xx_spi_port_config *port_conf; 198 struct s3c64xx_spi_port_config *port_conf;
199 unsigned int port_id; 199 unsigned int port_id;
200 bool cs_gpio;
201}; 200};
202 201
203static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 202static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
@@ -754,10 +753,8 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
754{ 753{
755 struct s3c64xx_spi_csinfo *cs; 754 struct s3c64xx_spi_csinfo *cs;
756 struct device_node *slave_np, *data_np = NULL; 755 struct device_node *slave_np, *data_np = NULL;
757 struct s3c64xx_spi_driver_data *sdd;
758 u32 fb_delay = 0; 756 u32 fb_delay = 0;
759 757
760 sdd = spi_master_get_devdata(spi->master);
761 slave_np = spi->dev.of_node; 758 slave_np = spi->dev.of_node;
762 if (!slave_np) { 759 if (!slave_np) {
763 dev_err(&spi->dev, "device node not found\n"); 760 dev_err(&spi->dev, "device node not found\n");
@@ -776,17 +773,6 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
776 return ERR_PTR(-ENOMEM); 773 return ERR_PTR(-ENOMEM);
777 } 774 }
778 775
779 /* The CS line is asserted/deasserted by the gpio pin */
780 if (sdd->cs_gpio)
781 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
782
783 if (!gpio_is_valid(cs->line)) {
784 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
785 kfree(cs);
786 of_node_put(data_np);
787 return ERR_PTR(-EINVAL);
788 }
789
790 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 776 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
791 cs->fb_delay = fb_delay; 777 cs->fb_delay = fb_delay;
792 of_node_put(data_np); 778 of_node_put(data_np);
@@ -807,9 +793,16 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
807 int err; 793 int err;
808 794
809 sdd = spi_master_get_devdata(spi->master); 795 sdd = spi_master_get_devdata(spi->master);
810 if (!cs && spi->dev.of_node) { 796 if (spi->dev.of_node) {
811 cs = s3c64xx_get_slave_ctrldata(spi); 797 cs = s3c64xx_get_slave_ctrldata(spi);
812 spi->controller_data = cs; 798 spi->controller_data = cs;
799 } else if (cs) {
800 /* On non-DT platforms the SPI core will set spi->cs_gpio
801 * to -ENOENT. The GPIO pin used to drive the chip select
802 * is defined by using platform data so spi->cs_gpio value
803 * has to be override to have the proper GPIO pin number.
804 */
805 spi->cs_gpio = cs->line;
813 } 806 }
814 807
815 if (IS_ERR_OR_NULL(cs)) { 808 if (IS_ERR_OR_NULL(cs)) {
@@ -818,18 +811,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
818 } 811 }
819 812
820 if (!spi_get_ctldata(spi)) { 813 if (!spi_get_ctldata(spi)) {
821 /* Request gpio only if cs line is asserted by gpio pins */ 814 if (gpio_is_valid(spi->cs_gpio)) {
822 if (sdd->cs_gpio) { 815 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
823 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, 816 dev_name(&spi->dev));
824 dev_name(&spi->dev));
825 if (err) { 817 if (err) {
826 dev_err(&spi->dev, 818 dev_err(&spi->dev,
827 "Failed to get /CS gpio [%d]: %d\n", 819 "Failed to get /CS gpio [%d]: %d\n",
828 cs->line, err); 820 spi->cs_gpio, err);
829 goto err_gpio_req; 821 goto err_gpio_req;
830 } 822 }
831
832 spi->cs_gpio = cs->line;
833 } 823 }
834 824
835 spi_set_ctldata(spi, cs); 825 spi_set_ctldata(spi, cs);
@@ -884,7 +874,8 @@ setup_exit:
884 /* setup() returns with device de-selected */ 874 /* setup() returns with device de-selected */
885 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 875 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
886 876
887 gpio_free(cs->line); 877 if (gpio_is_valid(spi->cs_gpio))
878 gpio_free(spi->cs_gpio);
888 spi_set_ctldata(spi, NULL); 879 spi_set_ctldata(spi, NULL);
889 880
890err_gpio_req: 881err_gpio_req:
@@ -897,14 +888,21 @@ err_gpio_req:
897static void s3c64xx_spi_cleanup(struct spi_device *spi) 888static void s3c64xx_spi_cleanup(struct spi_device *spi)
898{ 889{
899 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 890 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
900 struct s3c64xx_spi_driver_data *sdd;
901 891
902 sdd = spi_master_get_devdata(spi->master); 892 if (gpio_is_valid(spi->cs_gpio)) {
903 if (spi->cs_gpio) {
904 gpio_free(spi->cs_gpio); 893 gpio_free(spi->cs_gpio);
905 if (spi->dev.of_node) 894 if (spi->dev.of_node)
906 kfree(cs); 895 kfree(cs);
896 else {
897 /* On non-DT platforms, the SPI core sets
898 * spi->cs_gpio to -ENOENT and .setup()
899 * overrides it with the GPIO pin value
900 * passed using platform data.
901 */
902 spi->cs_gpio = -ENOENT;
903 }
907 } 904 }
905
908 spi_set_ctldata(spi, NULL); 906 spi_set_ctldata(spi, NULL);
909} 907}
910 908
@@ -1075,11 +1073,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
1075 sdd->cntrlr_info = sci; 1073 sdd->cntrlr_info = sci;
1076 sdd->pdev = pdev; 1074 sdd->pdev = pdev;
1077 sdd->sfr_start = mem_res->start; 1075 sdd->sfr_start = mem_res->start;
1078 sdd->cs_gpio = true;
1079 if (pdev->dev.of_node) { 1076 if (pdev->dev.of_node) {
1080 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1081 sdd->cs_gpio = false;
1082
1083 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1077 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1084 if (ret < 0) { 1078 if (ret < 0) {
1085 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1079 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index c8e795ef2e13..94b5faed21e2 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -304,7 +304,7 @@ static int hspi_remove(struct platform_device *pdev)
304 return 0; 304 return 0;
305} 305}
306 306
307static struct of_device_id hspi_of_match[] = { 307static const struct of_device_id hspi_of_match[] = {
308 { .compatible = "renesas,hspi", }, 308 { .compatible = "renesas,hspi", },
309 { /* sentinel */ } 309 { /* sentinel */ }
310}; 310};
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 45b09142afe2..2a4354dcd661 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -2,6 +2,7 @@
2 * SuperH MSIOF SPI Master Interface 2 * SuperH MSIOF SPI Master Interface
3 * 3 *
4 * Copyright (c) 2009 Magnus Damm 4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Glider bvba
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,6 +14,8 @@
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/completion.h> 15#include <linux/completion.h>
15#include <linux/delay.h> 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/dmaengine.h>
16#include <linux/err.h> 19#include <linux/err.h>
17#include <linux/gpio.h> 20#include <linux/gpio.h>
18#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -23,6 +26,7 @@
23#include <linux/of_device.h> 26#include <linux/of_device.h>
24#include <linux/platform_device.h> 27#include <linux/platform_device.h>
25#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
29#include <linux/sh_dma.h>
26 30
27#include <linux/spi/sh_msiof.h> 31#include <linux/spi/sh_msiof.h>
28#include <linux/spi/spi.h> 32#include <linux/spi/spi.h>
@@ -37,6 +41,7 @@ struct sh_msiof_chipdata {
37}; 41};
38 42
39struct sh_msiof_spi_priv { 43struct sh_msiof_spi_priv {
44 struct spi_master *master;
40 void __iomem *mapbase; 45 void __iomem *mapbase;
41 struct clk *clk; 46 struct clk *clk;
42 struct platform_device *pdev; 47 struct platform_device *pdev;
@@ -45,6 +50,10 @@ struct sh_msiof_spi_priv {
45 struct completion done; 50 struct completion done;
46 int tx_fifo_size; 51 int tx_fifo_size;
47 int rx_fifo_size; 52 int rx_fifo_size;
53 void *tx_dma_page;
54 void *rx_dma_page;
55 dma_addr_t tx_dma_addr;
56 dma_addr_t rx_dma_addr;
48}; 57};
49 58
50#define TMDR1 0x00 /* Transmit Mode Register 1 */ 59#define TMDR1 0x00 /* Transmit Mode Register 1 */
@@ -84,6 +93,8 @@ struct sh_msiof_spi_priv {
84#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 93#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
85#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ 94#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
86 95
96#define MAX_WDLEN 256U
97
87/* TSCR and RSCR */ 98/* TSCR and RSCR */
88#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ 99#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
89#define SCR_BRPS(i) (((i) - 1) << 8) 100#define SCR_BRPS(i) (((i) - 1) << 8)
@@ -113,9 +124,61 @@ struct sh_msiof_spi_priv {
113#define CTR_TXE 0x00000200 /* Transmit Enable */ 124#define CTR_TXE 0x00000200 /* Transmit Enable */
114#define CTR_RXE 0x00000100 /* Receive Enable */ 125#define CTR_RXE 0x00000100 /* Receive Enable */
115 126
116/* STR and IER */ 127/* FCTR */
128#define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
129#define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
130#define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
131#define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
132#define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
133#define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
134#define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
135#define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
136#define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
137#define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
138#define FCTR_TFUA_SHIFT 20
139#define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
140#define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
141#define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
142#define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
143#define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
144#define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
145#define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
146#define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
147#define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
148#define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
149#define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
150#define FCTR_RFUA_SHIFT 4
151#define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
152
153/* STR */
154#define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
155#define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
117#define STR_TEOF 0x00800000 /* Frame Transmission End */ 156#define STR_TEOF 0x00800000 /* Frame Transmission End */
157#define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
158#define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
159#define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
160#define STR_RFFUL 0x00002000 /* Receive FIFO Full */
161#define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
118#define STR_REOF 0x00000080 /* Frame Reception End */ 162#define STR_REOF 0x00000080 /* Frame Reception End */
163#define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
164#define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
165#define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
166
167/* IER */
168#define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
169#define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
170#define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
171#define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
172#define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
173#define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
174#define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
175#define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
176#define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
177#define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
178#define IER_REOFE 0x00000080 /* Frame Reception End Enable */
179#define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
180#define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
181#define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
119 182
120 183
121static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 184static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
@@ -230,8 +293,6 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
230 * 1 0 11 11 0 0 293 * 1 0 11 11 0 0
231 * 1 1 11 11 1 1 294 * 1 1 11 11 1 1
232 */ 295 */
233 sh_msiof_write(p, FCTR, 0);
234
235 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; 296 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
236 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 297 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
237 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 298 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
@@ -267,8 +328,6 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
267 328
268 if (rx_buf) 329 if (rx_buf)
269 sh_msiof_write(p, RMDR2, dr2); 330 sh_msiof_write(p, RMDR2, dr2);
270
271 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
272} 331}
273 332
274static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 333static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
@@ -457,6 +516,40 @@ static int sh_msiof_prepare_message(struct spi_master *master,
457 return 0; 516 return 0;
458} 517}
459 518
519static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
520{
521 int ret;
522
523 /* setup clock and rx/tx signals */
524 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
525 if (rx_buf && !ret)
526 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
527 if (!ret)
528 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
529
530 /* start by setting frame bit */
531 if (!ret)
532 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
533
534 return ret;
535}
536
537static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
538{
539 int ret;
540
541 /* shut down frame, rx/tx and clock signals */
542 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
543 if (!ret)
544 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
545 if (rx_buf && !ret)
546 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
547 if (!ret)
548 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
549
550 return ret;
551}
552
460static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 553static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
461 void (*tx_fifo)(struct sh_msiof_spi_priv *, 554 void (*tx_fifo)(struct sh_msiof_spi_priv *,
462 const void *, int, int), 555 const void *, int, int),
@@ -477,29 +570,32 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
477 /* the fifo contents need shifting */ 570 /* the fifo contents need shifting */
478 fifo_shift = 32 - bits; 571 fifo_shift = 32 - bits;
479 572
573 /* default FIFO watermarks for PIO */
574 sh_msiof_write(p, FCTR, 0);
575
480 /* setup msiof transfer mode registers */ 576 /* setup msiof transfer mode registers */
481 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 577 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
578 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
482 579
483 /* write tx fifo */ 580 /* write tx fifo */
484 if (tx_buf) 581 if (tx_buf)
485 tx_fifo(p, tx_buf, words, fifo_shift); 582 tx_fifo(p, tx_buf, words, fifo_shift);
486 583
487 /* setup clock and rx/tx signals */
488 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
489 if (rx_buf)
490 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
491 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
492
493 /* start by setting frame bit */
494 reinit_completion(&p->done); 584 reinit_completion(&p->done);
495 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); 585
586 ret = sh_msiof_spi_start(p, rx_buf);
496 if (ret) { 587 if (ret) {
497 dev_err(&p->pdev->dev, "failed to start hardware\n"); 588 dev_err(&p->pdev->dev, "failed to start hardware\n");
498 goto err; 589 goto stop_ier;
499 } 590 }
500 591
501 /* wait for tx fifo to be emptied / rx fifo to be filled */ 592 /* wait for tx fifo to be emptied / rx fifo to be filled */
502 wait_for_completion(&p->done); 593 ret = wait_for_completion_timeout(&p->done, HZ);
594 if (!ret) {
595 dev_err(&p->pdev->dev, "PIO timeout\n");
596 ret = -ETIMEDOUT;
597 goto stop_reset;
598 }
503 599
504 /* read rx fifo */ 600 /* read rx fifo */
505 if (rx_buf) 601 if (rx_buf)
@@ -508,41 +604,248 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
508 /* clear status bits */ 604 /* clear status bits */
509 sh_msiof_reset_str(p); 605 sh_msiof_reset_str(p);
510 606
511 /* shut down frame, rx/tx and clock signals */ 607 ret = sh_msiof_spi_stop(p, rx_buf);
512 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
513 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
514 if (rx_buf)
515 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
516 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
517 if (ret) { 608 if (ret) {
518 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 609 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
519 goto err; 610 return ret;
520 } 611 }
521 612
522 return words; 613 return words;
523 614
524 err: 615stop_reset:
616 sh_msiof_reset_str(p);
617 sh_msiof_spi_stop(p, rx_buf);
618stop_ier:
619 sh_msiof_write(p, IER, 0);
620 return ret;
621}
622
623static void sh_msiof_dma_complete(void *arg)
624{
625 struct sh_msiof_spi_priv *p = arg;
626
627 sh_msiof_write(p, IER, 0);
628 complete(&p->done);
629}
630
631static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
632 void *rx, unsigned int len)
633{
634 u32 ier_bits = 0;
635 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
636 dma_cookie_t cookie;
637 int ret;
638
639 if (tx) {
640 ier_bits |= IER_TDREQE | IER_TDMAE;
641 dma_sync_single_for_device(p->master->dma_tx->device->dev,
642 p->tx_dma_addr, len, DMA_TO_DEVICE);
643 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
644 p->tx_dma_addr, len, DMA_TO_DEVICE,
645 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
646 if (!desc_tx)
647 return -EAGAIN;
648 }
649
650 if (rx) {
651 ier_bits |= IER_RDREQE | IER_RDMAE;
652 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
653 p->rx_dma_addr, len, DMA_FROM_DEVICE,
654 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
655 if (!desc_rx)
656 return -EAGAIN;
657 }
658
659 /* 1 stage FIFO watermarks for DMA */
660 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
661
662 /* setup msiof transfer mode registers (32-bit words) */
663 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
664
665 sh_msiof_write(p, IER, ier_bits);
666
667 reinit_completion(&p->done);
668
669 if (rx) {
670 desc_rx->callback = sh_msiof_dma_complete;
671 desc_rx->callback_param = p;
672 cookie = dmaengine_submit(desc_rx);
673 if (dma_submit_error(cookie)) {
674 ret = cookie;
675 goto stop_ier;
676 }
677 dma_async_issue_pending(p->master->dma_rx);
678 }
679
680 if (tx) {
681 if (rx) {
682 /* No callback */
683 desc_tx->callback = NULL;
684 } else {
685 desc_tx->callback = sh_msiof_dma_complete;
686 desc_tx->callback_param = p;
687 }
688 cookie = dmaengine_submit(desc_tx);
689 if (dma_submit_error(cookie)) {
690 ret = cookie;
691 goto stop_rx;
692 }
693 dma_async_issue_pending(p->master->dma_tx);
694 }
695
696 ret = sh_msiof_spi_start(p, rx);
697 if (ret) {
698 dev_err(&p->pdev->dev, "failed to start hardware\n");
699 goto stop_tx;
700 }
701
702 /* wait for tx fifo to be emptied / rx fifo to be filled */
703 ret = wait_for_completion_timeout(&p->done, HZ);
704 if (!ret) {
705 dev_err(&p->pdev->dev, "DMA timeout\n");
706 ret = -ETIMEDOUT;
707 goto stop_reset;
708 }
709
710 /* clear status bits */
711 sh_msiof_reset_str(p);
712
713 ret = sh_msiof_spi_stop(p, rx);
714 if (ret) {
715 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
716 return ret;
717 }
718
719 if (rx)
720 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
721 p->rx_dma_addr, len,
722 DMA_FROM_DEVICE);
723
724 return 0;
725
726stop_reset:
727 sh_msiof_reset_str(p);
728 sh_msiof_spi_stop(p, rx);
729stop_tx:
730 if (tx)
731 dmaengine_terminate_all(p->master->dma_tx);
732stop_rx:
733 if (rx)
734 dmaengine_terminate_all(p->master->dma_rx);
735stop_ier:
525 sh_msiof_write(p, IER, 0); 736 sh_msiof_write(p, IER, 0);
526 return ret; 737 return ret;
527} 738}
528 739
740static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
741{
742 /* src or dst can be unaligned, but not both */
743 if ((unsigned long)src & 3) {
744 while (words--) {
745 *dst++ = swab32(get_unaligned(src));
746 src++;
747 }
748 } else if ((unsigned long)dst & 3) {
749 while (words--) {
750 put_unaligned(swab32(*src++), dst);
751 dst++;
752 }
753 } else {
754 while (words--)
755 *dst++ = swab32(*src++);
756 }
757}
758
759static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
760{
761 /* src or dst can be unaligned, but not both */
762 if ((unsigned long)src & 3) {
763 while (words--) {
764 *dst++ = swahw32(get_unaligned(src));
765 src++;
766 }
767 } else if ((unsigned long)dst & 3) {
768 while (words--) {
769 put_unaligned(swahw32(*src++), dst);
770 dst++;
771 }
772 } else {
773 while (words--)
774 *dst++ = swahw32(*src++);
775 }
776}
777
778static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
779{
780 memcpy(dst, src, words * 4);
781}
782
529static int sh_msiof_transfer_one(struct spi_master *master, 783static int sh_msiof_transfer_one(struct spi_master *master,
530 struct spi_device *spi, 784 struct spi_device *spi,
531 struct spi_transfer *t) 785 struct spi_transfer *t)
532{ 786{
533 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 787 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
788 void (*copy32)(u32 *, const u32 *, unsigned int);
534 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 789 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
535 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 790 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
536 int bits; 791 const void *tx_buf = t->tx_buf;
537 int bytes_per_word; 792 void *rx_buf = t->rx_buf;
538 int bytes_done; 793 unsigned int len = t->len;
539 int words; 794 unsigned int bits = t->bits_per_word;
795 unsigned int bytes_per_word;
796 unsigned int words;
540 int n; 797 int n;
541 bool swab; 798 bool swab;
799 int ret;
542 800
543 bits = t->bits_per_word; 801 /* setup clocks (clock already enabled in chipselect()) */
802 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
544 803
545 if (bits <= 8 && t->len > 15 && !(t->len & 3)) { 804 while (master->dma_tx && len > 15) {
805 /*
806 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
807 * words, with byte resp. word swapping.
808 */
809 unsigned int l = min(len, MAX_WDLEN * 4);
810
811 if (bits <= 8) {
812 if (l & 3)
813 break;
814 copy32 = copy_bswap32;
815 } else if (bits <= 16) {
816 if (l & 1)
817 break;
818 copy32 = copy_wswap32;
819 } else {
820 copy32 = copy_plain32;
821 }
822
823 if (tx_buf)
824 copy32(p->tx_dma_page, tx_buf, l / 4);
825
826 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
827 if (ret == -EAGAIN) {
828 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
829 dev_driver_string(&p->pdev->dev),
830 dev_name(&p->pdev->dev));
831 break;
832 }
833 if (ret)
834 return ret;
835
836 if (rx_buf) {
837 copy32(rx_buf, p->rx_dma_page, l / 4);
838 rx_buf += l;
839 }
840 if (tx_buf)
841 tx_buf += l;
842
843 len -= l;
844 if (!len)
845 return 0;
846 }
847
848 if (bits <= 8 && len > 15 && !(len & 3)) {
546 bits = 32; 849 bits = 32;
547 swab = true; 850 swab = true;
548 } else { 851 } else {
@@ -556,57 +859,52 @@ static int sh_msiof_transfer_one(struct spi_master *master,
556 rx_fifo = sh_msiof_spi_read_fifo_8; 859 rx_fifo = sh_msiof_spi_read_fifo_8;
557 } else if (bits <= 16) { 860 } else if (bits <= 16) {
558 bytes_per_word = 2; 861 bytes_per_word = 2;
559 if ((unsigned long)t->tx_buf & 0x01) 862 if ((unsigned long)tx_buf & 0x01)
560 tx_fifo = sh_msiof_spi_write_fifo_16u; 863 tx_fifo = sh_msiof_spi_write_fifo_16u;
561 else 864 else
562 tx_fifo = sh_msiof_spi_write_fifo_16; 865 tx_fifo = sh_msiof_spi_write_fifo_16;
563 866
564 if ((unsigned long)t->rx_buf & 0x01) 867 if ((unsigned long)rx_buf & 0x01)
565 rx_fifo = sh_msiof_spi_read_fifo_16u; 868 rx_fifo = sh_msiof_spi_read_fifo_16u;
566 else 869 else
567 rx_fifo = sh_msiof_spi_read_fifo_16; 870 rx_fifo = sh_msiof_spi_read_fifo_16;
568 } else if (swab) { 871 } else if (swab) {
569 bytes_per_word = 4; 872 bytes_per_word = 4;
570 if ((unsigned long)t->tx_buf & 0x03) 873 if ((unsigned long)tx_buf & 0x03)
571 tx_fifo = sh_msiof_spi_write_fifo_s32u; 874 tx_fifo = sh_msiof_spi_write_fifo_s32u;
572 else 875 else
573 tx_fifo = sh_msiof_spi_write_fifo_s32; 876 tx_fifo = sh_msiof_spi_write_fifo_s32;
574 877
575 if ((unsigned long)t->rx_buf & 0x03) 878 if ((unsigned long)rx_buf & 0x03)
576 rx_fifo = sh_msiof_spi_read_fifo_s32u; 879 rx_fifo = sh_msiof_spi_read_fifo_s32u;
577 else 880 else
578 rx_fifo = sh_msiof_spi_read_fifo_s32; 881 rx_fifo = sh_msiof_spi_read_fifo_s32;
579 } else { 882 } else {
580 bytes_per_word = 4; 883 bytes_per_word = 4;
581 if ((unsigned long)t->tx_buf & 0x03) 884 if ((unsigned long)tx_buf & 0x03)
582 tx_fifo = sh_msiof_spi_write_fifo_32u; 885 tx_fifo = sh_msiof_spi_write_fifo_32u;
583 else 886 else
584 tx_fifo = sh_msiof_spi_write_fifo_32; 887 tx_fifo = sh_msiof_spi_write_fifo_32;
585 888
586 if ((unsigned long)t->rx_buf & 0x03) 889 if ((unsigned long)rx_buf & 0x03)
587 rx_fifo = sh_msiof_spi_read_fifo_32u; 890 rx_fifo = sh_msiof_spi_read_fifo_32u;
588 else 891 else
589 rx_fifo = sh_msiof_spi_read_fifo_32; 892 rx_fifo = sh_msiof_spi_read_fifo_32;
590 } 893 }
591 894
592 /* setup clocks (clock already enabled in chipselect()) */
593 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
594
595 /* transfer in fifo sized chunks */ 895 /* transfer in fifo sized chunks */
596 words = t->len / bytes_per_word; 896 words = len / bytes_per_word;
597 bytes_done = 0; 897
598 898 while (words > 0) {
599 while (bytes_done < t->len) { 899 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
600 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
601 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
602 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
603 tx_buf,
604 rx_buf,
605 words, bits); 900 words, bits);
606 if (n < 0) 901 if (n < 0)
607 break; 902 return n;
608 903
609 bytes_done += n * bytes_per_word; 904 if (tx_buf)
905 tx_buf += n * bytes_per_word;
906 if (rx_buf)
907 rx_buf += n * bytes_per_word;
610 words -= n; 908 words -= n;
611 } 909 }
612 910
@@ -663,6 +961,128 @@ static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
663} 961}
664#endif 962#endif
665 963
964static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
965 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
966{
967 dma_cap_mask_t mask;
968 struct dma_chan *chan;
969 struct dma_slave_config cfg;
970 int ret;
971
972 dma_cap_zero(mask);
973 dma_cap_set(DMA_SLAVE, mask);
974
975 chan = dma_request_channel(mask, shdma_chan_filter,
976 (void *)(unsigned long)id);
977 if (!chan) {
978 dev_warn(dev, "dma_request_channel failed\n");
979 return NULL;
980 }
981
982 memset(&cfg, 0, sizeof(cfg));
983 cfg.slave_id = id;
984 cfg.direction = dir;
985 if (dir == DMA_MEM_TO_DEV)
986 cfg.dst_addr = port_addr;
987 else
988 cfg.src_addr = port_addr;
989
990 ret = dmaengine_slave_config(chan, &cfg);
991 if (ret) {
992 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
993 dma_release_channel(chan);
994 return NULL;
995 }
996
997 return chan;
998}
999
1000static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1001{
1002 struct platform_device *pdev = p->pdev;
1003 struct device *dev = &pdev->dev;
1004 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1005 const struct resource *res;
1006 struct spi_master *master;
1007 struct device *tx_dev, *rx_dev;
1008
1009 if (!info || !info->dma_tx_id || !info->dma_rx_id)
1010 return 0; /* The driver assumes no error */
1011
1012 /* The DMA engine uses the second register set, if present */
1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1014 if (!res)
1015 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1016
1017 master = p->master;
1018 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1019 info->dma_tx_id,
1020 res->start + TFDR);
1021 if (!master->dma_tx)
1022 return -ENODEV;
1023
1024 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1025 info->dma_rx_id,
1026 res->start + RFDR);
1027 if (!master->dma_rx)
1028 goto free_tx_chan;
1029
1030 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1031 if (!p->tx_dma_page)
1032 goto free_rx_chan;
1033
1034 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1035 if (!p->rx_dma_page)
1036 goto free_tx_page;
1037
1038 tx_dev = master->dma_tx->device->dev;
1039 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1040 DMA_TO_DEVICE);
1041 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1042 goto free_rx_page;
1043
1044 rx_dev = master->dma_rx->device->dev;
1045 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1046 DMA_FROM_DEVICE);
1047 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1048 goto unmap_tx_page;
1049
1050 dev_info(dev, "DMA available");
1051 return 0;
1052
1053unmap_tx_page:
1054 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1055free_rx_page:
1056 free_page((unsigned long)p->rx_dma_page);
1057free_tx_page:
1058 free_page((unsigned long)p->tx_dma_page);
1059free_rx_chan:
1060 dma_release_channel(master->dma_rx);
1061free_tx_chan:
1062 dma_release_channel(master->dma_tx);
1063 master->dma_tx = NULL;
1064 return -ENODEV;
1065}
1066
1067static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1068{
1069 struct spi_master *master = p->master;
1070 struct device *dev;
1071
1072 if (!master->dma_tx)
1073 return;
1074
1075 dev = &p->pdev->dev;
1076 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1077 PAGE_SIZE, DMA_FROM_DEVICE);
1078 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1079 PAGE_SIZE, DMA_TO_DEVICE);
1080 free_page((unsigned long)p->rx_dma_page);
1081 free_page((unsigned long)p->tx_dma_page);
1082 dma_release_channel(master->dma_rx);
1083 dma_release_channel(master->dma_tx);
1084}
1085
666static int sh_msiof_spi_probe(struct platform_device *pdev) 1086static int sh_msiof_spi_probe(struct platform_device *pdev)
667{ 1087{
668 struct resource *r; 1088 struct resource *r;
@@ -681,6 +1101,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
681 p = spi_master_get_devdata(master); 1101 p = spi_master_get_devdata(master);
682 1102
683 platform_set_drvdata(pdev, p); 1103 platform_set_drvdata(pdev, p);
1104 p->master = master;
684 1105
685 of_id = of_match_device(sh_msiof_match, &pdev->dev); 1106 of_id = of_match_device(sh_msiof_match, &pdev->dev);
686 if (of_id) { 1107 if (of_id) {
@@ -751,6 +1172,10 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
751 master->auto_runtime_pm = true; 1172 master->auto_runtime_pm = true;
752 master->transfer_one = sh_msiof_transfer_one; 1173 master->transfer_one = sh_msiof_transfer_one;
753 1174
1175 ret = sh_msiof_request_dma(p);
1176 if (ret < 0)
1177 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1178
754 ret = devm_spi_register_master(&pdev->dev, master); 1179 ret = devm_spi_register_master(&pdev->dev, master);
755 if (ret < 0) { 1180 if (ret < 0) {
756 dev_err(&pdev->dev, "spi_register_master error.\n"); 1181 dev_err(&pdev->dev, "spi_register_master error.\n");
@@ -760,6 +1185,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
760 return 0; 1185 return 0;
761 1186
762 err2: 1187 err2:
1188 sh_msiof_release_dma(p);
763 pm_runtime_disable(&pdev->dev); 1189 pm_runtime_disable(&pdev->dev);
764 err1: 1190 err1:
765 spi_master_put(master); 1191 spi_master_put(master);
@@ -768,6 +1194,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
768 1194
769static int sh_msiof_spi_remove(struct platform_device *pdev) 1195static int sh_msiof_spi_remove(struct platform_device *pdev)
770{ 1196{
1197 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1198
1199 sh_msiof_release_dma(p);
771 pm_runtime_disable(&pdev->dev); 1200 pm_runtime_disable(&pdev->dev);
772 return 0; 1201 return 0;
773} 1202}
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index 03edf5ed0e9f..8e171a76049f 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -432,7 +432,6 @@ static int spi_sh_remove(struct platform_device *pdev)
432 spi_unregister_master(ss->master); 432 spi_unregister_master(ss->master);
433 destroy_workqueue(ss->workqueue); 433 destroy_workqueue(ss->workqueue);
434 free_irq(ss->irq, ss); 434 free_irq(ss->irq, ss);
435 iounmap(ss->addr);
436 435
437 return 0; 436 return 0;
438} 437}
@@ -480,7 +479,7 @@ static int spi_sh_probe(struct platform_device *pdev)
480 } 479 }
481 ss->irq = irq; 480 ss->irq = irq;
482 ss->master = master; 481 ss->master = master;
483 ss->addr = ioremap(res->start, resource_size(res)); 482 ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
484 if (ss->addr == NULL) { 483 if (ss->addr == NULL) {
485 dev_err(&pdev->dev, "ioremap error.\n"); 484 dev_err(&pdev->dev, "ioremap error.\n");
486 ret = -ENOMEM; 485 ret = -ENOMEM;
@@ -495,13 +494,13 @@ static int spi_sh_probe(struct platform_device *pdev)
495 if (ss->workqueue == NULL) { 494 if (ss->workqueue == NULL) {
496 dev_err(&pdev->dev, "create workqueue error\n"); 495 dev_err(&pdev->dev, "create workqueue error\n");
497 ret = -EBUSY; 496 ret = -EBUSY;
498 goto error2; 497 goto error1;
499 } 498 }
500 499
501 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss); 500 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
502 if (ret < 0) { 501 if (ret < 0) {
503 dev_err(&pdev->dev, "request_irq error\n"); 502 dev_err(&pdev->dev, "request_irq error\n");
504 goto error3; 503 goto error2;
505 } 504 }
506 505
507 master->num_chipselect = 2; 506 master->num_chipselect = 2;
@@ -513,17 +512,15 @@ static int spi_sh_probe(struct platform_device *pdev)
513 ret = spi_register_master(master); 512 ret = spi_register_master(master);
514 if (ret < 0) { 513 if (ret < 0) {
515 printk(KERN_ERR "spi_register_master error.\n"); 514 printk(KERN_ERR "spi_register_master error.\n");
516 goto error4; 515 goto error3;
517 } 516 }
518 517
519 return 0; 518 return 0;
520 519
521 error4:
522 free_irq(irq, ss);
523 error3: 520 error3:
524 destroy_workqueue(ss->workqueue); 521 free_irq(irq, ss);
525 error2: 522 error2:
526 iounmap(ss->addr); 523 destroy_workqueue(ss->workqueue);
527 error1: 524 error1:
528 spi_master_put(master); 525 spi_master_put(master);
529 526
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index f05abf89c067..0a87ec39f619 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -874,8 +874,8 @@ static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
874 dma_cap_set(DMA_SLAVE, mask); 874 dma_cap_set(DMA_SLAVE, mask);
875 875
876 /* Get DMA's dev information */ 876 /* Get DMA's dev information */
877 dma_dev = pci_get_bus_and_slot(data->board_dat->pdev->bus->number, 877 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
878 PCI_DEVFN(12, 0)); 878 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
879 879
880 /* Set Tx DMA */ 880 /* Set Tx DMA */
881 param = &dma->param_tx; 881 param = &dma->param_tx;
@@ -1047,8 +1047,8 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
1047 num, DMA_DEV_TO_MEM, 1047 num, DMA_DEV_TO_MEM,
1048 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1048 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049 if (!desc_rx) { 1049 if (!desc_rx) {
1050 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", 1050 dev_err(&data->master->dev,
1051 __func__); 1051 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1052 return; 1052 return;
1053 } 1053 }
1054 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); 1054 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
@@ -1106,8 +1106,8 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
1106 sg, num, DMA_MEM_TO_DEV, 1106 sg, num, DMA_MEM_TO_DEV,
1107 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1107 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1108 if (!desc_tx) { 1108 if (!desc_tx) {
1109 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", 1109 dev_err(&data->master->dev,
1110 __func__); 1110 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1111 return; 1111 return;
1112 } 1112 }
1113 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); 1113 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index a3b0b9944bf0..4d8efb16573d 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -369,7 +369,7 @@ static int xilinx_spi_probe(struct platform_device *pdev)
369 goto put_master; 369 goto put_master;
370 } 370 }
371 371
372 master->bus_num = pdev->dev.id; 372 master->bus_num = pdev->id;
373 master->num_chipselect = num_cs; 373 master->num_chipselect = num_cs;
374 master->dev.of_node = pdev->dev.of_node; 374 master->dev.of_node = pdev->dev.of_node;
375 375
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 22aa41cace82..e0531baf2782 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -350,14 +350,12 @@ static DEFINE_MUTEX(board_lock);
350struct spi_device *spi_alloc_device(struct spi_master *master) 350struct spi_device *spi_alloc_device(struct spi_master *master)
351{ 351{
352 struct spi_device *spi; 352 struct spi_device *spi;
353 struct device *dev = master->dev.parent;
354 353
355 if (!spi_master_get(master)) 354 if (!spi_master_get(master))
356 return NULL; 355 return NULL;
357 356
358 spi = kzalloc(sizeof(*spi), GFP_KERNEL); 357 spi = kzalloc(sizeof(*spi), GFP_KERNEL);
359 if (!spi) { 358 if (!spi) {
360 dev_err(dev, "cannot alloc spi_device\n");
361 spi_master_put(master); 359 spi_master_put(master);
362 return NULL; 360 return NULL;
363 } 361 }
@@ -624,6 +622,8 @@ static int spi_map_buf(struct spi_master *master, struct device *dev,
624 } 622 }
625 623
626 ret = dma_map_sg(dev, sgt->sgl, sgt->nents, dir); 624 ret = dma_map_sg(dev, sgt->sgl, sgt->nents, dir);
625 if (!ret)
626 ret = -ENOMEM;
627 if (ret < 0) { 627 if (ret < 0) {
628 sg_free_table(sgt); 628 sg_free_table(sgt);
629 return ret; 629 return ret;
@@ -652,8 +652,8 @@ static int __spi_map_msg(struct spi_master *master, struct spi_message *msg)
652 if (!master->can_dma) 652 if (!master->can_dma)
653 return 0; 653 return 0;
654 654
655 tx_dev = &master->dma_tx->dev->device; 655 tx_dev = master->dma_tx->device->dev;
656 rx_dev = &master->dma_rx->dev->device; 656 rx_dev = master->dma_rx->device->dev;
657 657
658 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 658 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
659 if (!master->can_dma(master, msg->spi, xfer)) 659 if (!master->can_dma(master, msg->spi, xfer))
@@ -692,8 +692,8 @@ static int spi_unmap_msg(struct spi_master *master, struct spi_message *msg)
692 if (!master->cur_msg_mapped || !master->can_dma) 692 if (!master->cur_msg_mapped || !master->can_dma)
693 return 0; 693 return 0;
694 694
695 tx_dev = &master->dma_tx->dev->device; 695 tx_dev = master->dma_tx->device->dev;
696 rx_dev = &master->dma_rx->dev->device; 696 rx_dev = master->dma_rx->device->dev;
697 697
698 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 698 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
699 if (!master->can_dma(master, msg->spi, xfer)) 699 if (!master->can_dma(master, msg->spi, xfer))
diff --git a/include/linux/spi/sh_msiof.h b/include/linux/spi/sh_msiof.h
index 2e8db3d2d2e5..88a14d81c49e 100644
--- a/include/linux/spi/sh_msiof.h
+++ b/include/linux/spi/sh_msiof.h
@@ -5,6 +5,8 @@ struct sh_msiof_spi_info {
5 int tx_fifo_override; 5 int tx_fifo_override;
6 int rx_fifo_override; 6 int rx_fifo_override;
7 u16 num_chipselect; 7 u16 num_chipselect;
8 unsigned int dma_tx_id;
9 unsigned int dma_rx_id;
8}; 10};
9 11
10#endif /* __SPI_SH_MSIOF_H__ */ 12#endif /* __SPI_SH_MSIOF_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 17:19:46 -0500