aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.c228
1 files changed, 0 insertions, 228 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
deleted file mode 100644
index a993f3d33f9b..000000000000
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ /dev/null
@@ -1,228 +0,0 @@
1/*
2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include "exynos_thermal_common.h"
24#include "exynos_tmu.h"
25
26struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
27 .tmu_data = {
28 {
29 .threshold = 80,
30 .trigger_levels[0] = 5,
31 .trigger_levels[1] = 20,
32 .trigger_levels[2] = 30,
33 .trigger_enable[0] = true,
34 .trigger_enable[1] = true,
35 .trigger_enable[2] = true,
36 .trigger_enable[3] = false,
37 .trigger_type[0] = THROTTLE_ACTIVE,
38 .trigger_type[1] = THROTTLE_ACTIVE,
39 .trigger_type[2] = SW_TRIP,
40 .max_trigger_level = 4,
41 .non_hw_trigger_levels = 3,
42 .gain = 15,
43 .reference_voltage = 7,
44 .cal_type = TYPE_ONE_POINT_TRIMMING,
45 .min_efuse_value = 40,
46 .max_efuse_value = 100,
47 .first_point_trim = 25,
48 .second_point_trim = 85,
49 .default_temp_offset = 50,
50 .type = SOC_ARCH_EXYNOS4210,
51 },
52 },
53 .tmu_count = 1,
54};
55
56#define EXYNOS3250_TMU_DATA \
57 .threshold_falling = 10, \
58 .trigger_levels[0] = 70, \
59 .trigger_levels[1] = 95, \
60 .trigger_levels[2] = 110, \
61 .trigger_levels[3] = 120, \
62 .trigger_enable[0] = true, \
63 .trigger_enable[1] = true, \
64 .trigger_enable[2] = true, \
65 .trigger_enable[3] = false, \
66 .trigger_type[0] = THROTTLE_ACTIVE, \
67 .trigger_type[1] = THROTTLE_ACTIVE, \
68 .trigger_type[2] = SW_TRIP, \
69 .trigger_type[3] = HW_TRIP, \
70 .max_trigger_level = 4, \
71 .non_hw_trigger_levels = 3, \
72 .gain = 8, \
73 .reference_voltage = 16, \
74 .noise_cancel_mode = 4, \
75 .cal_type = TYPE_TWO_POINT_TRIMMING, \
76 .efuse_value = 55, \
77 .min_efuse_value = 40, \
78 .max_efuse_value = 100, \
79 .first_point_trim = 25, \
80 .second_point_trim = 85, \
81 .default_temp_offset = 50
82
83struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
84 .tmu_data = {
85 {
86 EXYNOS3250_TMU_DATA,
87 .type = SOC_ARCH_EXYNOS3250,
88 },
89 },
90 .tmu_count = 1,
91};
92
93#define EXYNOS4412_TMU_DATA \
94 .threshold_falling = 10, \
95 .trigger_levels[0] = 70, \
96 .trigger_levels[1] = 95, \
97 .trigger_levels[2] = 110, \
98 .trigger_levels[3] = 120, \
99 .trigger_enable[0] = true, \
100 .trigger_enable[1] = true, \
101 .trigger_enable[2] = true, \
102 .trigger_enable[3] = false, \
103 .trigger_type[0] = THROTTLE_ACTIVE, \
104 .trigger_type[1] = THROTTLE_ACTIVE, \
105 .trigger_type[2] = SW_TRIP, \
106 .trigger_type[3] = HW_TRIP, \
107 .max_trigger_level = 4, \
108 .non_hw_trigger_levels = 3, \
109 .gain = 8, \
110 .reference_voltage = 16, \
111 .noise_cancel_mode = 4, \
112 .cal_type = TYPE_ONE_POINT_TRIMMING, \
113 .efuse_value = 55, \
114 .min_efuse_value = 40, \
115 .max_efuse_value = 100, \
116 .first_point_trim = 25, \
117 .second_point_trim = 85, \
118 .default_temp_offset = 50
119
120struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
121 .tmu_data = {
122 {
123 EXYNOS4412_TMU_DATA,
124 .type = SOC_ARCH_EXYNOS4412,
125 },
126 },
127 .tmu_count = 1,
128};
129
130struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
131 .tmu_data = {
132 {
133 EXYNOS4412_TMU_DATA,
134 .type = SOC_ARCH_EXYNOS5250,
135 },
136 },
137 .tmu_count = 1,
138};
139
140#define __EXYNOS5260_TMU_DATA \
141 .threshold_falling = 10, \
142 .trigger_levels[0] = 85, \
143 .trigger_levels[1] = 103, \
144 .trigger_levels[2] = 110, \
145 .trigger_levels[3] = 120, \
146 .trigger_enable[0] = true, \
147 .trigger_enable[1] = true, \
148 .trigger_enable[2] = true, \
149 .trigger_enable[3] = false, \
150 .trigger_type[0] = THROTTLE_ACTIVE, \
151 .trigger_type[1] = THROTTLE_ACTIVE, \
152 .trigger_type[2] = SW_TRIP, \
153 .trigger_type[3] = HW_TRIP, \
154 .max_trigger_level = 4, \
155 .non_hw_trigger_levels = 3, \
156 .gain = 8, \
157 .reference_voltage = 16, \
158 .noise_cancel_mode = 4, \
159 .cal_type = TYPE_ONE_POINT_TRIMMING, \
160 .efuse_value = 55, \
161 .min_efuse_value = 40, \
162 .max_efuse_value = 100, \
163 .first_point_trim = 25, \
164 .second_point_trim = 85, \
165 .default_temp_offset = 50,
166
167#define EXYNOS5260_TMU_DATA \
168 __EXYNOS5260_TMU_DATA \
169 .type = SOC_ARCH_EXYNOS5260
170
171struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
172 .tmu_data = {
173 { EXYNOS5260_TMU_DATA },
174 { EXYNOS5260_TMU_DATA },
175 { EXYNOS5260_TMU_DATA },
176 { EXYNOS5260_TMU_DATA },
177 { EXYNOS5260_TMU_DATA },
178 },
179 .tmu_count = 5,
180};
181
182#define EXYNOS5420_TMU_DATA \
183 __EXYNOS5260_TMU_DATA \
184 .type = SOC_ARCH_EXYNOS5420
185
186#define EXYNOS5420_TMU_DATA_SHARED \
187 __EXYNOS5260_TMU_DATA \
188 .type = SOC_ARCH_EXYNOS5420_TRIMINFO
189
190struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
191 .tmu_data = {
192 { EXYNOS5420_TMU_DATA },
193 { EXYNOS5420_TMU_DATA },
194 { EXYNOS5420_TMU_DATA_SHARED },
195 { EXYNOS5420_TMU_DATA_SHARED },
196 { EXYNOS5420_TMU_DATA_SHARED },
197 },
198 .tmu_count = 5,
199};
200
201#define EXYNOS5440_TMU_DATA \
202 .trigger_levels[0] = 100, \
203 .trigger_levels[4] = 105, \
204 .trigger_enable[0] = 1, \
205 .trigger_type[0] = SW_TRIP, \
206 .trigger_type[4] = HW_TRIP, \
207 .max_trigger_level = 5, \
208 .non_hw_trigger_levels = 1, \
209 .gain = 5, \
210 .reference_voltage = 16, \
211 .noise_cancel_mode = 4, \
212 .cal_type = TYPE_ONE_POINT_TRIMMING, \
213 .efuse_value = 0x5b2d, \
214 .min_efuse_value = 16, \
215 .max_efuse_value = 76, \
216 .first_point_trim = 25, \
217 .second_point_trim = 70, \
218 .default_temp_offset = 25, \
219 .type = SOC_ARCH_EXYNOS5440
220
221struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
222 .tmu_data = {
223 { EXYNOS5440_TMU_DATA } ,
224 { EXYNOS5440_TMU_DATA } ,
225 { EXYNOS5440_TMU_DATA } ,
226 },
227 .tmu_count = 3,
228};
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 00:25:40 -0500