diff options
135 files changed, 2032 insertions, 8382 deletions
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index 87a1e8fb6242..d9a372d06e77 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README | |||
| @@ -3,17 +3,22 @@ ARM Allwinner SoCs | |||
| 3 | 3 | ||
| 4 | This document lists all the ARM Allwinner SoCs that are currently | 4 | This document lists all the ARM Allwinner SoCs that are currently |
| 5 | supported in mainline by the Linux kernel. This document will also | 5 | supported in mainline by the Linux kernel. This document will also |
| 6 | provide links to documentation and or datasheet for these SoCs. | 6 | provide links to documentation and/or datasheet for these SoCs. |
| 7 | 7 | ||
| 8 | SunXi family | 8 | SunXi family |
| 9 | ------------ | 9 | ------------ |
| 10 | Linux kernel mach directory: arch/arm/mach-sunxi | ||
| 10 | 11 | ||
| 11 | Flavors: | 12 | Flavors: |
| 12 | Allwinner A10 (sun4i) | 13 | * ARM Cortex-A8 based SoCs |
| 13 | Datasheet : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf | 14 | - Allwinner A10 (sun4i) |
| 15 | + Datasheet | ||
| 16 | http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf | ||
| 17 | + User Manual | ||
| 18 | http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf | ||
| 14 | 19 | ||
| 15 | Allwinner A13 (sun5i) | 20 | - Allwinner A13 (sun5i) |
| 16 | Datasheet : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf | 21 | + Datasheet |
| 17 | 22 | http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf | |
| 18 | Core: Cortex A8 | 23 | + User Manual |
| 19 | Linux kernel mach directory: arch/arm/mach-sunxi \ No newline at end of file | 24 | http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf |
diff --git a/Documentation/devicetree/bindings/gpio/gpio-msm.txt b/Documentation/devicetree/bindings/gpio/gpio-msm.txt new file mode 100644 index 000000000000..ac20e68a004e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-msm.txt | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | MSM GPIO controller bindings | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: | ||
| 5 | - "qcom,msm-gpio" for MSM controllers | ||
| 6 | - #gpio-cells : Should be two. | ||
| 7 | - first cell is the pin number | ||
| 8 | - second cell is used to specify optional parameters (unused) | ||
| 9 | - gpio-controller : Marks the device node as a GPIO controller. | ||
| 10 | - #interrupt-cells : Should be 2. | ||
| 11 | - interrupt-controller: Mark the device node as an interrupt controller | ||
| 12 | - interrupts : Specify the TLMM summary interrupt number | ||
| 13 | - ngpio : Specify the number of MSM GPIOs | ||
| 14 | |||
| 15 | Example: | ||
| 16 | |||
| 17 | msmgpio: gpio@fd510000 { | ||
| 18 | compatible = "qcom,msm-gpio"; | ||
| 19 | gpio-controller; | ||
| 20 | #gpio-cells = <2>; | ||
| 21 | interrupt-controller; | ||
| 22 | #interrupt-cells = <2>; | ||
| 23 | reg = <0xfd510000 0x4000>; | ||
| 24 | interrupts = <0 208 0>; | ||
| 25 | ngpio = <150>; | ||
| 26 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index e7f4dc14eff2..57edb30dbbca 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | |||
| @@ -8,91 +8,8 @@ Required properties: | |||
| 8 | - #interrupt-cells : Specifies the number of cells needed to encode an | 8 | - #interrupt-cells : Specifies the number of cells needed to encode an |
| 9 | interrupt source. The value shall be 1. | 9 | interrupt source. The value shall be 1. |
| 10 | 10 | ||
| 11 | The interrupt sources are as follows: | 11 | For the valid interrupt sources for your SoC, see the documentation in |
| 12 | 12 | sunxi/<soc>.txt | |
| 13 | 0: ENMI | ||
| 14 | 1: UART0 | ||
| 15 | 2: UART1 | ||
| 16 | 3: UART2 | ||
| 17 | 4: UART3 | ||
| 18 | 5: IR0 | ||
| 19 | 6: IR1 | ||
| 20 | 7: I2C0 | ||
| 21 | 8: I2C1 | ||
| 22 | 9: I2C2 | ||
| 23 | 10: SPI0 | ||
| 24 | 11: SPI1 | ||
| 25 | 12: SPI2 | ||
| 26 | 13: SPDIF | ||
| 27 | 14: AC97 | ||
| 28 | 15: TS | ||
| 29 | 16: I2S | ||
| 30 | 17: UART4 | ||
| 31 | 18: UART5 | ||
| 32 | 19: UART6 | ||
| 33 | 20: UART7 | ||
| 34 | 21: KEYPAD | ||
| 35 | 22: TIMER0 | ||
| 36 | 23: TIMER1 | ||
| 37 | 24: TIMER2 | ||
| 38 | 25: TIMER3 | ||
| 39 | 26: CAN | ||
| 40 | 27: DMA | ||
| 41 | 28: PIO | ||
| 42 | 29: TOUCH_PANEL | ||
| 43 | 30: AUDIO_CODEC | ||
| 44 | 31: LRADC | ||
| 45 | 32: SDMC0 | ||
| 46 | 33: SDMC1 | ||
| 47 | 34: SDMC2 | ||
| 48 | 35: SDMC3 | ||
| 49 | 36: MEMSTICK | ||
| 50 | 37: NAND | ||
| 51 | 38: USB0 | ||
| 52 | 39: USB1 | ||
| 53 | 40: USB2 | ||
| 54 | 41: SCR | ||
| 55 | 42: CSI0 | ||
| 56 | 43: CSI1 | ||
| 57 | 44: LCDCTRL0 | ||
| 58 | 45: LCDCTRL1 | ||
| 59 | 46: MP | ||
| 60 | 47: DEFEBE0 | ||
| 61 | 48: DEFEBE1 | ||
| 62 | 49: PMU | ||
| 63 | 50: SPI3 | ||
| 64 | 51: TZASC | ||
| 65 | 52: PATA | ||
| 66 | 53: VE | ||
| 67 | 54: SS | ||
| 68 | 55: EMAC | ||
| 69 | 56: SATA | ||
| 70 | 57: GPS | ||
| 71 | 58: HDMI | ||
| 72 | 59: TVE | ||
| 73 | 60: ACE | ||
| 74 | 61: TVD | ||
| 75 | 62: PS2_0 | ||
| 76 | 63: PS2_1 | ||
| 77 | 64: USB3 | ||
| 78 | 65: USB4 | ||
| 79 | 66: PLE_PFM | ||
| 80 | 67: TIMER4 | ||
| 81 | 68: TIMER5 | ||
| 82 | 69: GPU_GP | ||
| 83 | 70: GPU_GPMMU | ||
| 84 | 71: GPU_PP0 | ||
| 85 | 72: GPU_PPMMU0 | ||
| 86 | 73: GPU_PMU | ||
| 87 | 74: GPU_RSV0 | ||
| 88 | 75: GPU_RSV1 | ||
| 89 | 76: GPU_RSV2 | ||
| 90 | 77: GPU_RSV3 | ||
| 91 | 78: GPU_RSV4 | ||
| 92 | 79: GPU_RSV5 | ||
| 93 | 80: GPU_RSV6 | ||
| 94 | 82: SYNC_TIMER0 | ||
| 95 | 83: SYNC_TIMER1 | ||
| 96 | 13 | ||
| 97 | Example: | 14 | Example: |
| 98 | 15 | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt new file mode 100644 index 000000000000..76b98c834499 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt | |||
| @@ -0,0 +1,89 @@ | |||
| 1 | Allwinner A10 (sun4i) interrupt sources | ||
| 2 | --------------------------------------- | ||
| 3 | |||
| 4 | The interrupt sources available for the Allwinner A10 SoC are the | ||
| 5 | following one: | ||
| 6 | |||
| 7 | 0: ENMI | ||
| 8 | 1: UART0 | ||
| 9 | 2: UART1 | ||
| 10 | 3: UART2 | ||
| 11 | 4: UART3 | ||
| 12 | 5: IR0 | ||
| 13 | 6: IR1 | ||
| 14 | 7: I2C0 | ||
| 15 | 8: I2C1 | ||
| 16 | 9: I2C2 | ||
| 17 | 10: SPI0 | ||
| 18 | 11: SPI1 | ||
| 19 | 12: SPI2 | ||
| 20 | 13: SPDIF | ||
| 21 | 14: AC97 | ||
| 22 | 15: TS | ||
| 23 | 16: I2S | ||
| 24 | 17: UART4 | ||
| 25 | 18: UART5 | ||
| 26 | 19: UART6 | ||
| 27 | 20: UART7 | ||
| 28 | 21: KEYPAD | ||
| 29 | 22: TIMER0 | ||
| 30 | 23: TIMER1 | ||
| 31 | 24: TIMER2 | ||
| 32 | 25: TIMER3 | ||
| 33 | 26: CAN | ||
| 34 | 27: DMA | ||
| 35 | 28: PIO | ||
| 36 | 29: TOUCH_PANEL | ||
| 37 | 30: AUDIO_CODEC | ||
| 38 | 31: LRADC | ||
| 39 | 32: MMC0 | ||
| 40 | 33: MMC1 | ||
| 41 | 34: MMC2 | ||
| 42 | 35: MMC3 | ||
| 43 | 36: MEMSTICK | ||
| 44 | 37: NAND | ||
| 45 | 38: USB0 | ||
| 46 | 39: USB1 | ||
| 47 | 40: USB2 | ||
| 48 | 41: SCR | ||
| 49 | 42: CSI0 | ||
| 50 | 43: CSI1 | ||
| 51 | 44: LCDCTRL0 | ||
| 52 | 45: LCDCTRL1 | ||
| 53 | 46: MP | ||
| 54 | 47: DEFEBE0 | ||
| 55 | 48: DEFEBE1 | ||
| 56 | 49: PMU | ||
| 57 | 50: SPI3 | ||
| 58 | 51: TZASC | ||
| 59 | 52: PATA | ||
| 60 | 53: VE | ||
| 61 | 54: SS | ||
| 62 | 55: EMAC | ||
| 63 | 56: SATA | ||
| 64 | 57: GPS | ||
| 65 | 58: HDMI | ||
| 66 | 59: TVE | ||
| 67 | 60: ACE | ||
| 68 | 61: TVD | ||
| 69 | 62: PS2_0 | ||
| 70 | 63: PS2_1 | ||
| 71 | 64: USB3 | ||
| 72 | 65: USB4 | ||
| 73 | 66: PLE_PFM | ||
| 74 | 67: TIMER4 | ||
| 75 | 68: TIMER5 | ||
| 76 | 69: GPU_GP | ||
| 77 | 70: GPU_GPMMU | ||
| 78 | 71: GPU_PP0 | ||
| 79 | 72: GPU_PPMMU0 | ||
| 80 | 73: GPU_PMU | ||
| 81 | 74: GPU_RSV0 | ||
| 82 | 75: GPU_RSV1 | ||
| 83 | 76: GPU_RSV2 | ||
| 84 | 77: GPU_RSV3 | ||
| 85 | 78: GPU_RSV4 | ||
| 86 | 79: GPU_RSV5 | ||
| 87 | 80: GPU_RSV6 | ||
| 88 | 82: SYNC_TIMER0 | ||
| 89 | 83: SYNC_TIMER1 | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt new file mode 100644 index 000000000000..2ec3b5ce1a0b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | Allwinner A13 (sun5i) interrupt sources | ||
| 2 | --------------------------------------- | ||
| 3 | |||
| 4 | The interrupt sources available for the Allwinner A13 SoC are the | ||
| 5 | following one: | ||
| 6 | |||
| 7 | 0: ENMI | ||
| 8 | 2: UART1 | ||
| 9 | 4: UART3 | ||
| 10 | 5: IR | ||
| 11 | 7: I2C0 | ||
| 12 | 8: I2C1 | ||
| 13 | 9: I2C2 | ||
| 14 | 10: SPI0 | ||
| 15 | 11: SPI1 | ||
| 16 | 12: SPI2 | ||
| 17 | 22: TIMER0 | ||
| 18 | 23: TIMER1 | ||
| 19 | 24: TIMER2 | ||
| 20 | 25: TIMER3 | ||
| 21 | 27: DMA | ||
| 22 | 28: PIO | ||
| 23 | 29: TOUCH_PANEL | ||
| 24 | 30: AUDIO_CODEC | ||
| 25 | 31: LRADC | ||
| 26 | 32: MMC0 | ||
| 27 | 33: MMC1 | ||
| 28 | 34: MMC2 | ||
| 29 | 37: NAND | ||
| 30 | 38: USB OTG | ||
| 31 | 39: USB EHCI | ||
| 32 | 40: USB OHCI | ||
| 33 | 42: CSI | ||
| 34 | 44: LCDCTRL | ||
| 35 | 47: DEFEBE | ||
| 36 | 49: PMU | ||
| 37 | 53: VE | ||
| 38 | 54: SS | ||
| 39 | 66: PLE_PFM | ||
| 40 | 67: TIMER4 | ||
| 41 | 68: TIMER5 | ||
| 42 | 69: GPU_GP | ||
| 43 | 70: GPU_GPMMU | ||
| 44 | 71: GPU_PP0 | ||
| 45 | 72: GPU_PPMMU0 | ||
| 46 | 73: GPU_PMU | ||
| 47 | 74: GPU_RSV0 | ||
| 48 | 75: GPU_RSV1 | ||
| 49 | 76: GPU_RSV2 | ||
| 50 | 77: GPU_RSV3 | ||
| 51 | 78: GPU_RSV4 | ||
| 52 | 79: GPU_RSV5 | ||
| 53 | 80: GPU_RSV6 | ||
| 54 | 82: SYNC_TIMER0 | ||
| 55 | 83: SYNC_TIMER1 | ||
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts index 29b9f15e7599..54cb5cf8604a 100644 --- a/arch/arm/boot/dts/aks-cdu.dts +++ b/arch/arm/boot/dts/aks-cdu.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | /dts-v1/; | 10 | /dts-v1/; |
| 11 | 11 | ||
| 12 | /include/ "ge863-pro3.dtsi" | 12 | #include "ge863-pro3.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | chosen { | 15 | chosen { |
| @@ -46,7 +46,7 @@ | |||
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | usb1: gadget@fffa4000 { | 48 | usb1: gadget@fffa4000 { |
| 49 | atmel,vbus-gpio = <&pioC 15 0>; | 49 | atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; |
| 50 | status = "okay"; | 50 | status = "okay"; |
| 51 | }; | 51 | }; |
| 52 | }; | 52 | }; |
| @@ -90,23 +90,23 @@ | |||
| 90 | compatible = "gpio-leds"; | 90 | compatible = "gpio-leds"; |
| 91 | 91 | ||
| 92 | red { | 92 | red { |
| 93 | gpios = <&pioC 10 0>; | 93 | gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; |
| 94 | linux,default-trigger = "none"; | 94 | linux,default-trigger = "none"; |
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | green { | 97 | green { |
| 98 | gpios = <&pioA 5 1>; | 98 | gpios = <&pioA 5 GPIO_ACTIVE_LOW>; |
| 99 | linux,default-trigger = "none"; | 99 | linux,default-trigger = "none"; |
| 100 | default-state = "on"; | 100 | default-state = "on"; |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | yellow { | 103 | yellow { |
| 104 | gpios = <&pioB 20 1>; | 104 | gpios = <&pioB 20 GPIO_ACTIVE_LOW>; |
| 105 | linux,default-trigger = "none"; | 105 | linux,default-trigger = "none"; |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | blue { | 108 | blue { |
| 109 | gpios = <&pioB 21 1>; | 109 | gpios = <&pioB 21 GPIO_ACTIVE_LOW>; |
| 110 | linux,default-trigger = "none"; | 110 | linux,default-trigger = "none"; |
| 111 | }; | 111 | }; |
| 112 | }; | 112 | }; |
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 8e1248f01fab..77aa1b0cf6a7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -394,7 +394,6 @@ | |||
| 394 | compatible = "ti,am3352-ocmcram"; | 394 | compatible = "ti,am3352-ocmcram"; |
| 395 | reg = <0x40300000 0x10000>; | 395 | reg = <0x40300000 0x10000>; |
| 396 | ti,hwmods = "ocmcram"; | 396 | ti,hwmods = "ocmcram"; |
| 397 | ti,no_idle_on_suspend; | ||
| 398 | }; | 397 | }; |
| 399 | 398 | ||
| 400 | wkup_m3: wkup_m3@44d00000 { | 399 | wkup_m3: wkup_m3@44d00000 { |
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 5160210f74da..3a1de9eb5111 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9260.dtsi" | 10 | #include "at91sam9260.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Somfy Animeo IP"; | 13 | model = "Somfy Animeo IP"; |
| @@ -123,7 +123,7 @@ | |||
| 123 | 123 | ||
| 124 | usb0: ohci@00500000 { | 124 | usb0: ohci@00500000 { |
| 125 | num-ports = <2>; | 125 | num-ports = <2>; |
| 126 | atmel,vbus-gpio = <&pioB 15 1>; | 126 | atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; |
| 127 | status = "okay"; | 127 | status = "okay"; |
| 128 | }; | 128 | }; |
| 129 | }; | 129 | }; |
| @@ -133,23 +133,23 @@ | |||
| 133 | 133 | ||
| 134 | power_green { | 134 | power_green { |
| 135 | label = "power_green"; | 135 | label = "power_green"; |
| 136 | gpios = <&pioC 17 0>; | 136 | gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; |
| 137 | linux,default-trigger = "heartbeat"; | 137 | linux,default-trigger = "heartbeat"; |
| 138 | }; | 138 | }; |
| 139 | 139 | ||
| 140 | power_red { | 140 | power_red { |
| 141 | label = "power_red"; | 141 | label = "power_red"; |
| 142 | gpios = <&pioA 2 0>; | 142 | gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; |
| 143 | }; | 143 | }; |
| 144 | 144 | ||
| 145 | tx_green { | 145 | tx_green { |
| 146 | label = "tx_green"; | 146 | label = "tx_green"; |
| 147 | gpios = <&pioC 19 0>; | 147 | gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; |
| 148 | }; | 148 | }; |
| 149 | 149 | ||
| 150 | tx_red { | 150 | tx_red { |
| 151 | label = "tx_red"; | 151 | label = "tx_red"; |
| 152 | gpios = <&pioC 18 0>; | 152 | gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; |
| 153 | }; | 153 | }; |
| 154 | }; | 154 | }; |
| 155 | 155 | ||
| @@ -160,21 +160,21 @@ | |||
| 160 | 160 | ||
| 161 | keyswitch_in { | 161 | keyswitch_in { |
| 162 | label = "keyswitch_in"; | 162 | label = "keyswitch_in"; |
| 163 | gpios = <&pioB 1 0>; | 163 | gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; |
| 164 | linux,code = <28>; | 164 | linux,code = <28>; |
| 165 | gpio-key,wakeup; | 165 | gpio-key,wakeup; |
| 166 | }; | 166 | }; |
| 167 | 167 | ||
| 168 | error_in { | 168 | error_in { |
| 169 | label = "error_in"; | 169 | label = "error_in"; |
| 170 | gpios = <&pioB 2 0>; | 170 | gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; |
| 171 | linux,code = <29>; | 171 | linux,code = <29>; |
| 172 | gpio-key,wakeup; | 172 | gpio-key,wakeup; |
| 173 | }; | 173 | }; |
| 174 | 174 | ||
| 175 | btn { | 175 | btn { |
| 176 | label = "btn"; | 176 | label = "btn"; |
| 177 | gpios = <&pioC 23 0>; | 177 | gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; |
| 178 | linux,code = <31>; | 178 | linux,code = <31>; |
| 179 | gpio-key,wakeup; | 179 | gpio-key,wakeup; |
| 180 | }; | 180 | }; |
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index c7aebba4e8e7..5ede7678f298 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9g25.dtsi" | 10 | #include "at91sam9g25.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Acme Systems Aria G25"; | 13 | model = "Acme Systems Aria G25"; |
| @@ -156,7 +156,7 @@ | |||
| 156 | /* little green LED in middle of Aria G25 module */ | 156 | /* little green LED in middle of Aria G25 module */ |
| 157 | aria_led { | 157 | aria_led { |
| 158 | label = "aria_led"; | 158 | label = "aria_led"; |
| 159 | gpios = <&pioB 8 0>; /* PB8 */ | 159 | gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ |
| 160 | linux,default-trigger = "heartbeat"; | 160 | linux,default-trigger = "heartbeat"; |
| 161 | }; | 161 | }; |
| 162 | 162 | ||
| @@ -164,7 +164,7 @@ | |||
| 164 | 164 | ||
| 165 | onewire@0 { | 165 | onewire@0 { |
| 166 | compatible = "w1-gpio"; | 166 | compatible = "w1-gpio"; |
| 167 | gpios = <&pioA 21 1>; | 167 | gpios = <&pioA 21 GPIO_ACTIVE_LOW>; |
| 168 | pinctrl-names = "default"; | 168 | pinctrl-names = "default"; |
| 169 | pinctrl-0 = <&pinctrl_w1_0>; | 169 | pinctrl-0 = <&pinctrl_w1_0>; |
| 170 | }; | 170 | }; |
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 5d3ed5aafc69..4aad0d9f5462 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi | |||
| @@ -10,7 +10,10 @@ | |||
| 10 | * Licensed under GPLv2 or later. | 10 | * Licensed under GPLv2 or later. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 14 | #include <dt-bindings/pinctrl/at91.h> | ||
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | 17 | ||
| 15 | / { | 18 | / { |
| 16 | model = "Atmel AT91RM9200 family SoC"; | 19 | model = "Atmel AT91RM9200 family SoC"; |
| @@ -77,25 +80,29 @@ | |||
| 77 | st: timer@fffffd00 { | 80 | st: timer@fffffd00 { |
| 78 | compatible = "atmel,at91rm9200-st"; | 81 | compatible = "atmel,at91rm9200-st"; |
| 79 | reg = <0xfffffd00 0x100>; | 82 | reg = <0xfffffd00 0x100>; |
| 80 | interrupts = <1 4 7>; | 83 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 81 | }; | 84 | }; |
| 82 | 85 | ||
| 83 | tcb0: timer@fffa0000 { | 86 | tcb0: timer@fffa0000 { |
| 84 | compatible = "atmel,at91rm9200-tcb"; | 87 | compatible = "atmel,at91rm9200-tcb"; |
| 85 | reg = <0xfffa0000 0x100>; | 88 | reg = <0xfffa0000 0x100>; |
| 86 | interrupts = <17 4 0 18 4 0 19 4 0>; | 89 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 |
| 90 | 18 IRQ_TYPE_LEVEL_HIGH 0 | ||
| 91 | 19 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 87 | }; | 92 | }; |
| 88 | 93 | ||
| 89 | tcb1: timer@fffa4000 { | 94 | tcb1: timer@fffa4000 { |
| 90 | compatible = "atmel,at91rm9200-tcb"; | 95 | compatible = "atmel,at91rm9200-tcb"; |
| 91 | reg = <0xfffa4000 0x100>; | 96 | reg = <0xfffa4000 0x100>; |
| 92 | interrupts = <20 4 0 21 4 0 22 4 0>; | 97 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 |
| 98 | 21 IRQ_TYPE_LEVEL_HIGH 0 | ||
| 99 | 22 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 93 | }; | 100 | }; |
| 94 | 101 | ||
| 95 | i2c0: i2c@fffb8000 { | 102 | i2c0: i2c@fffb8000 { |
| 96 | compatible = "atmel,at91rm9200-i2c"; | 103 | compatible = "atmel,at91rm9200-i2c"; |
| 97 | reg = <0xfffb8000 0x4000>; | 104 | reg = <0xfffb8000 0x4000>; |
| 98 | interrupts = <12 4 6>; | 105 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
| 99 | pinctrl-names = "default"; | 106 | pinctrl-names = "default"; |
| 100 | pinctrl-0 = <&pinctrl_twi>; | 107 | pinctrl-0 = <&pinctrl_twi>; |
| 101 | #address-cells = <1>; | 108 | #address-cells = <1>; |
| @@ -106,7 +113,7 @@ | |||
| 106 | mmc0: mmc@fffb4000 { | 113 | mmc0: mmc@fffb4000 { |
| 107 | compatible = "atmel,hsmci"; | 114 | compatible = "atmel,hsmci"; |
| 108 | reg = <0xfffb4000 0x4000>; | 115 | reg = <0xfffb4000 0x4000>; |
| 109 | interrupts = <10 4 0>; | 116 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; |
| 110 | #address-cells = <1>; | 117 | #address-cells = <1>; |
| 111 | #size-cells = <0>; | 118 | #size-cells = <0>; |
| 112 | status = "disabled"; | 119 | status = "disabled"; |
| @@ -115,7 +122,7 @@ | |||
| 115 | ssc0: ssc@fffd0000 { | 122 | ssc0: ssc@fffd0000 { |
| 116 | compatible = "atmel,at91rm9200-ssc"; | 123 | compatible = "atmel,at91rm9200-ssc"; |
| 117 | reg = <0xfffd0000 0x4000>; | 124 | reg = <0xfffd0000 0x4000>; |
| 118 | interrupts = <14 4 5>; | 125 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 119 | pinctrl-names = "default"; | 126 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 127 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 121 | status = "disable"; | 128 | status = "disable"; |
| @@ -124,7 +131,7 @@ | |||
| 124 | ssc1: ssc@fffd4000 { | 131 | ssc1: ssc@fffd4000 { |
| 125 | compatible = "atmel,at91rm9200-ssc"; | 132 | compatible = "atmel,at91rm9200-ssc"; |
| 126 | reg = <0xfffd4000 0x4000>; | 133 | reg = <0xfffd4000 0x4000>; |
| 127 | interrupts = <15 4 5>; | 134 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 128 | pinctrl-names = "default"; | 135 | pinctrl-names = "default"; |
| 129 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 136 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 130 | status = "disable"; | 137 | status = "disable"; |
| @@ -133,7 +140,7 @@ | |||
| 133 | ssc2: ssc@fffd8000 { | 140 | ssc2: ssc@fffd8000 { |
| 134 | compatible = "atmel,at91rm9200-ssc"; | 141 | compatible = "atmel,at91rm9200-ssc"; |
| 135 | reg = <0xfffd8000 0x4000>; | 142 | reg = <0xfffd8000 0x4000>; |
| 136 | interrupts = <16 4 5>; | 143 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 137 | pinctrl-names = "default"; | 144 | pinctrl-names = "default"; |
| 138 | pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; | 145 | pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; |
| 139 | status = "disable"; | 146 | status = "disable"; |
| @@ -142,7 +149,7 @@ | |||
| 142 | macb0: ethernet@fffbc000 { | 149 | macb0: ethernet@fffbc000 { |
| 143 | compatible = "cdns,at91rm9200-emac", "cdns,emac"; | 150 | compatible = "cdns,at91rm9200-emac", "cdns,emac"; |
| 144 | reg = <0xfffbc000 0x4000>; | 151 | reg = <0xfffbc000 0x4000>; |
| 145 | interrupts = <24 4 3>; | 152 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
| 146 | phy-mode = "rmii"; | 153 | phy-mode = "rmii"; |
| 147 | pinctrl-names = "default"; | 154 | pinctrl-names = "default"; |
| 148 | pinctrl-0 = <&pinctrl_macb_rmii>; | 155 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| @@ -167,234 +174,234 @@ | |||
| 167 | dbgu { | 174 | dbgu { |
| 168 | pinctrl_dbgu: dbgu-0 { | 175 | pinctrl_dbgu: dbgu-0 { |
| 169 | atmel,pins = | 176 | atmel,pins = |
| 170 | <0 30 0x1 0x0 /* PA30 periph A */ | 177 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */ |
| 171 | 0 31 0x1 0x1>; /* PA31 periph with pullup */ | 178 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */ |
| 172 | }; | 179 | }; |
| 173 | }; | 180 | }; |
| 174 | 181 | ||
| 175 | uart0 { | 182 | uart0 { |
| 176 | pinctrl_uart0: uart0-0 { | 183 | pinctrl_uart0: uart0-0 { |
| 177 | atmel,pins = | 184 | atmel,pins = |
| 178 | <0 17 0x1 0x0 /* PA17 periph A */ | 185 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 179 | 0 18 0x1 0x0>; /* PA18 periph A */ | 186 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ |
| 180 | }; | 187 | }; |
| 181 | 188 | ||
| 182 | pinctrl_uart0_rts: uart0_rts-0 { | 189 | pinctrl_uart0_rts: uart0_rts-0 { |
| 183 | atmel,pins = | 190 | atmel,pins = |
| 184 | <0 20 0x1 0x0>; /* PA20 periph A */ | 191 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ |
| 185 | }; | 192 | }; |
| 186 | 193 | ||
| 187 | pinctrl_uart0_cts: uart0_cts-0 { | 194 | pinctrl_uart0_cts: uart0_cts-0 { |
| 188 | atmel,pins = | 195 | atmel,pins = |
| 189 | <0 21 0x1 0x0>; /* PA21 periph A */ | 196 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ |
| 190 | }; | 197 | }; |
| 191 | }; | 198 | }; |
| 192 | 199 | ||
| 193 | uart1 { | 200 | uart1 { |
| 194 | pinctrl_uart1: uart1-0 { | 201 | pinctrl_uart1: uart1-0 { |
| 195 | atmel,pins = | 202 | atmel,pins = |
| 196 | <1 20 0x1 0x1 /* PB20 periph A with pullup */ | 203 | <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */ |
| 197 | 1 21 0x1 0x0>; /* PB21 periph A */ | 204 | AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ |
| 198 | }; | 205 | }; |
| 199 | 206 | ||
| 200 | pinctrl_uart1_rts: uart1_rts-0 { | 207 | pinctrl_uart1_rts: uart1_rts-0 { |
| 201 | atmel,pins = | 208 | atmel,pins = |
| 202 | <1 24 0x1 0x0>; /* PB24 periph A */ | 209 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ |
| 203 | }; | 210 | }; |
| 204 | 211 | ||
| 205 | pinctrl_uart1_cts: uart1_cts-0 { | 212 | pinctrl_uart1_cts: uart1_cts-0 { |
| 206 | atmel,pins = | 213 | atmel,pins = |
| 207 | <1 26 0x1 0x0>; /* PB26 periph A */ | 214 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ |
| 208 | }; | 215 | }; |
| 209 | 216 | ||
| 210 | pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { | 217 | pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { |
| 211 | atmel,pins = | 218 | atmel,pins = |
| 212 | <1 19 0x1 0x0 /* PB19 periph A */ | 219 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ |
| 213 | 1 25 0x1 0x0>; /* PB25 periph A */ | 220 | AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ |
| 214 | }; | 221 | }; |
| 215 | 222 | ||
| 216 | pinctrl_uart1_dcd: uart1_dcd-0 { | 223 | pinctrl_uart1_dcd: uart1_dcd-0 { |
| 217 | atmel,pins = | 224 | atmel,pins = |
| 218 | <1 23 0x1 0x0>; /* PB23 periph A */ | 225 | <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ |
| 219 | }; | 226 | }; |
| 220 | 227 | ||
| 221 | pinctrl_uart1_ri: uart1_ri-0 { | 228 | pinctrl_uart1_ri: uart1_ri-0 { |
| 222 | atmel,pins = | 229 | atmel,pins = |
| 223 | <1 18 0x1 0x0>; /* PB18 periph A */ | 230 | <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
| 224 | }; | 231 | }; |
| 225 | }; | 232 | }; |
| 226 | 233 | ||
| 227 | uart2 { | 234 | uart2 { |
| 228 | pinctrl_uart2: uart2-0 { | 235 | pinctrl_uart2: uart2-0 { |
| 229 | atmel,pins = | 236 | atmel,pins = |
| 230 | <0 22 0x1 0x0 /* PA22 periph A */ | 237 | <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */ |
| 231 | 0 23 0x1 0x1>; /* PA23 periph A with pullup */ | 238 | AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ |
| 232 | }; | 239 | }; |
| 233 | 240 | ||
| 234 | pinctrl_uart2_rts: uart2_rts-0 { | 241 | pinctrl_uart2_rts: uart2_rts-0 { |
| 235 | atmel,pins = | 242 | atmel,pins = |
| 236 | <0 30 0x2 0x0>; /* PA30 periph B */ | 243 | <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
| 237 | }; | 244 | }; |
| 238 | 245 | ||
| 239 | pinctrl_uart2_cts: uart2_cts-0 { | 246 | pinctrl_uart2_cts: uart2_cts-0 { |
| 240 | atmel,pins = | 247 | atmel,pins = |
| 241 | <0 31 0x2 0x0>; /* PA31 periph B */ | 248 | <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ |
| 242 | }; | 249 | }; |
| 243 | }; | 250 | }; |
| 244 | 251 | ||
| 245 | uart3 { | 252 | uart3 { |
| 246 | pinctrl_uart3: uart3-0 { | 253 | pinctrl_uart3: uart3-0 { |
| 247 | atmel,pins = | 254 | atmel,pins = |
| 248 | <0 5 0x2 0x1 /* PA5 periph B with pullup */ | 255 | <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ |
| 249 | 0 6 0x2 0x0>; /* PA6 periph B */ | 256 | AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */ |
| 250 | }; | 257 | }; |
| 251 | 258 | ||
| 252 | pinctrl_uart3_rts: uart3_rts-0 { | 259 | pinctrl_uart3_rts: uart3_rts-0 { |
| 253 | atmel,pins = | 260 | atmel,pins = |
| 254 | <1 0 0x2 0x0>; /* PB0 periph B */ | 261 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
| 255 | }; | 262 | }; |
| 256 | 263 | ||
| 257 | pinctrl_uart3_cts: uart3_cts-0 { | 264 | pinctrl_uart3_cts: uart3_cts-0 { |
| 258 | atmel,pins = | 265 | atmel,pins = |
| 259 | <1 1 0x2 0x0>; /* PB1 periph B */ | 266 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
| 260 | }; | 267 | }; |
| 261 | }; | 268 | }; |
| 262 | 269 | ||
| 263 | nand { | 270 | nand { |
| 264 | pinctrl_nand: nand-0 { | 271 | pinctrl_nand: nand-0 { |
| 265 | atmel,pins = | 272 | atmel,pins = |
| 266 | <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */ | 273 | <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ |
| 267 | 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */ | 274 | AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ |
| 268 | }; | 275 | }; |
| 269 | }; | 276 | }; |
| 270 | 277 | ||
| 271 | macb { | 278 | macb { |
| 272 | pinctrl_macb_rmii: macb_rmii-0 { | 279 | pinctrl_macb_rmii: macb_rmii-0 { |
| 273 | atmel,pins = | 280 | atmel,pins = |
| 274 | <0 7 0x1 0x0 /* PA7 periph A */ | 281 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ |
| 275 | 0 8 0x1 0x0 /* PA8 periph A */ | 282 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ |
| 276 | 0 9 0x1 0x0 /* PA9 periph A */ | 283 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 277 | 0 10 0x1 0x0 /* PA10 periph A */ | 284 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ |
| 278 | 0 11 0x1 0x0 /* PA11 periph A */ | 285 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ |
| 279 | 0 12 0x1 0x0 /* PA12 periph A */ | 286 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ |
| 280 | 0 13 0x1 0x0 /* PA13 periph A */ | 287 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ |
| 281 | 0 14 0x1 0x0 /* PA14 periph A */ | 288 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ |
| 282 | 0 15 0x1 0x0 /* PA15 periph A */ | 289 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ |
| 283 | 0 16 0x1 0x0>; /* PA16 periph A */ | 290 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ |
| 284 | }; | 291 | }; |
| 285 | 292 | ||
| 286 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | 293 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 287 | atmel,pins = | 294 | atmel,pins = |
| 288 | <1 12 0x2 0x0 /* PB12 periph B */ | 295 | <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ |
| 289 | 1 13 0x2 0x0 /* PB13 periph B */ | 296 | AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ |
| 290 | 1 14 0x2 0x0 /* PB14 periph B */ | 297 | AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ |
| 291 | 1 15 0x2 0x0 /* PB15 periph B */ | 298 | AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ |
| 292 | 1 16 0x2 0x0 /* PB16 periph B */ | 299 | AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ |
| 293 | 1 17 0x2 0x0 /* PB17 periph B */ | 300 | AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ |
| 294 | 1 18 0x2 0x0 /* PB18 periph B */ | 301 | AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ |
| 295 | 1 19 0x2 0x0>; /* PB19 periph B */ | 302 | AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ |
| 296 | }; | 303 | }; |
| 297 | }; | 304 | }; |
| 298 | 305 | ||
| 299 | mmc0 { | 306 | mmc0 { |
| 300 | pinctrl_mmc0_clk: mmc0_clk-0 { | 307 | pinctrl_mmc0_clk: mmc0_clk-0 { |
| 301 | atmel,pins = | 308 | atmel,pins = |
| 302 | <0 27 0x1 0x0>; /* PA27 periph A */ | 309 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ |
| 303 | }; | 310 | }; |
| 304 | 311 | ||
| 305 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { | 312 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { |
| 306 | atmel,pins = | 313 | atmel,pins = |
| 307 | <0 28 0x1 0x1 /* PA28 periph A with pullup */ | 314 | <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ |
| 308 | 0 29 0x1 0x1>; /* PA29 periph A with pullup */ | 315 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ |
| 309 | }; | 316 | }; |
| 310 | 317 | ||
| 311 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 318 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 312 | atmel,pins = | 319 | atmel,pins = |
| 313 | <1 3 0x2 0x1 /* PB3 periph B with pullup */ | 320 | <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ |
| 314 | 1 4 0x2 0x1 /* PB4 periph B with pullup */ | 321 | AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ |
| 315 | 1 5 0x2 0x1>; /* PB5 periph B with pullup */ | 322 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ |
| 316 | }; | 323 | }; |
| 317 | 324 | ||
| 318 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { | 325 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { |
| 319 | atmel,pins = | 326 | atmel,pins = |
| 320 | <0 8 0x2 0x1 /* PA8 periph B with pullup */ | 327 | <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ |
| 321 | 0 9 0x2 0x1>; /* PA9 periph B with pullup */ | 328 | AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ |
| 322 | }; | 329 | }; |
| 323 | 330 | ||
| 324 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { | 331 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { |
| 325 | atmel,pins = | 332 | atmel,pins = |
| 326 | <0 10 0x2 0x1 /* PA10 periph B with pullup */ | 333 | <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ |
| 327 | 0 11 0x2 0x1 /* PA11 periph B with pullup */ | 334 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ |
| 328 | 0 12 0x2 0x1>; /* PA12 periph B with pullup */ | 335 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ |
| 329 | }; | 336 | }; |
| 330 | }; | 337 | }; |
| 331 | 338 | ||
| 332 | ssc0 { | 339 | ssc0 { |
| 333 | pinctrl_ssc0_tx: ssc0_tx-0 { | 340 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 334 | atmel,pins = | 341 | atmel,pins = |
| 335 | <1 0 0x1 0x0 /* PB0 periph A */ | 342 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ |
| 336 | 1 1 0x1 0x0 /* PB1 periph A */ | 343 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ |
| 337 | 1 2 0x1 0x0>; /* PB2 periph A */ | 344 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ |
| 338 | }; | 345 | }; |
| 339 | 346 | ||
| 340 | pinctrl_ssc0_rx: ssc0_rx-0 { | 347 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 341 | atmel,pins = | 348 | atmel,pins = |
| 342 | <1 3 0x1 0x0 /* PB3 periph A */ | 349 | <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ |
| 343 | 1 4 0x1 0x0 /* PB4 periph A */ | 350 | AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ |
| 344 | 1 5 0x1 0x0>; /* PB5 periph A */ | 351 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ |
| 345 | }; | 352 | }; |
| 346 | }; | 353 | }; |
| 347 | 354 | ||
| 348 | ssc1 { | 355 | ssc1 { |
| 349 | pinctrl_ssc1_tx: ssc1_tx-0 { | 356 | pinctrl_ssc1_tx: ssc1_tx-0 { |
| 350 | atmel,pins = | 357 | atmel,pins = |
| 351 | <1 6 0x1 0x0 /* PB6 periph A */ | 358 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
| 352 | 1 7 0x1 0x0 /* PB7 periph A */ | 359 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ |
| 353 | 1 8 0x1 0x0>; /* PB8 periph A */ | 360 | AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ |
| 354 | }; | 361 | }; |
| 355 | 362 | ||
| 356 | pinctrl_ssc1_rx: ssc1_rx-0 { | 363 | pinctrl_ssc1_rx: ssc1_rx-0 { |
| 357 | atmel,pins = | 364 | atmel,pins = |
| 358 | <1 9 0x1 0x0 /* PB9 periph A */ | 365 | <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
| 359 | 1 10 0x1 0x0 /* PB10 periph A */ | 366 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ |
| 360 | 1 11 0x1 0x0>; /* PB11 periph A */ | 367 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ |
| 361 | }; | 368 | }; |
| 362 | }; | 369 | }; |
| 363 | 370 | ||
| 364 | ssc2 { | 371 | ssc2 { |
| 365 | pinctrl_ssc2_tx: ssc2_tx-0 { | 372 | pinctrl_ssc2_tx: ssc2_tx-0 { |
| 366 | atmel,pins = | 373 | atmel,pins = |
| 367 | <1 12 0x1 0x0 /* PB12 periph A */ | 374 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
| 368 | 1 13 0x1 0x0 /* PB13 periph A */ | 375 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ |
| 369 | 1 14 0x1 0x0>; /* PB14 periph A */ | 376 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ |
| 370 | }; | 377 | }; |
| 371 | 378 | ||
| 372 | pinctrl_ssc2_rx: ssc2_rx-0 { | 379 | pinctrl_ssc2_rx: ssc2_rx-0 { |
| 373 | atmel,pins = | 380 | atmel,pins = |
| 374 | <1 15 0x1 0x0 /* PB15 periph A */ | 381 | <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ |
| 375 | 1 16 0x1 0x0 /* PB16 periph A */ | 382 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ |
| 376 | 1 17 0x1 0x0>; /* PB17 periph A */ | 383 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ |
| 377 | }; | 384 | }; |
| 378 | }; | 385 | }; |
| 379 | 386 | ||
| 380 | twi { | 387 | twi { |
| 381 | pinctrl_twi: twi-0 { | 388 | pinctrl_twi: twi-0 { |
| 382 | atmel,pins = | 389 | atmel,pins = |
| 383 | <0 25 0x1 0x2 /* PA25 periph A with multi drive */ | 390 | <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ |
| 384 | 0 26 0x1 0x2>; /* PA26 periph A with multi drive */ | 391 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ |
| 385 | }; | 392 | }; |
| 386 | 393 | ||
| 387 | pinctrl_twi_gpio: twi_gpio-0 { | 394 | pinctrl_twi_gpio: twi_gpio-0 { |
| 388 | atmel,pins = | 395 | atmel,pins = |
| 389 | <0 25 0x0 0x2 /* PA25 GPIO with multi drive */ | 396 | <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ |
| 390 | 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */ | 397 | AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ |
| 391 | }; | 398 | }; |
| 392 | }; | 399 | }; |
| 393 | 400 | ||
| 394 | pioA: gpio@fffff400 { | 401 | pioA: gpio@fffff400 { |
| 395 | compatible = "atmel,at91rm9200-gpio"; | 402 | compatible = "atmel,at91rm9200-gpio"; |
| 396 | reg = <0xfffff400 0x200>; | 403 | reg = <0xfffff400 0x200>; |
| 397 | interrupts = <2 4 1>; | 404 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 398 | #gpio-cells = <2>; | 405 | #gpio-cells = <2>; |
| 399 | gpio-controller; | 406 | gpio-controller; |
| 400 | interrupt-controller; | 407 | interrupt-controller; |
| @@ -404,7 +411,7 @@ | |||
| 404 | pioB: gpio@fffff600 { | 411 | pioB: gpio@fffff600 { |
| 405 | compatible = "atmel,at91rm9200-gpio"; | 412 | compatible = "atmel,at91rm9200-gpio"; |
| 406 | reg = <0xfffff600 0x200>; | 413 | reg = <0xfffff600 0x200>; |
| 407 | interrupts = <3 4 1>; | 414 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 408 | #gpio-cells = <2>; | 415 | #gpio-cells = <2>; |
| 409 | gpio-controller; | 416 | gpio-controller; |
| 410 | interrupt-controller; | 417 | interrupt-controller; |
| @@ -414,7 +421,7 @@ | |||
| 414 | pioC: gpio@fffff800 { | 421 | pioC: gpio@fffff800 { |
| 415 | compatible = "atmel,at91rm9200-gpio"; | 422 | compatible = "atmel,at91rm9200-gpio"; |
| 416 | reg = <0xfffff800 0x200>; | 423 | reg = <0xfffff800 0x200>; |
| 417 | interrupts = <4 4 1>; | 424 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| 418 | #gpio-cells = <2>; | 425 | #gpio-cells = <2>; |
| 419 | gpio-controller; | 426 | gpio-controller; |
| 420 | interrupt-controller; | 427 | interrupt-controller; |
| @@ -424,7 +431,7 @@ | |||
| 424 | pioD: gpio@fffffa00 { | 431 | pioD: gpio@fffffa00 { |
| 425 | compatible = "atmel,at91rm9200-gpio"; | 432 | compatible = "atmel,at91rm9200-gpio"; |
| 426 | reg = <0xfffffa00 0x200>; | 433 | reg = <0xfffffa00 0x200>; |
| 427 | interrupts = <5 4 1>; | 434 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
| 428 | #gpio-cells = <2>; | 435 | #gpio-cells = <2>; |
| 429 | gpio-controller; | 436 | gpio-controller; |
| 430 | interrupt-controller; | 437 | interrupt-controller; |
| @@ -435,7 +442,7 @@ | |||
| 435 | dbgu: serial@fffff200 { | 442 | dbgu: serial@fffff200 { |
| 436 | compatible = "atmel,at91rm9200-usart"; | 443 | compatible = "atmel,at91rm9200-usart"; |
| 437 | reg = <0xfffff200 0x200>; | 444 | reg = <0xfffff200 0x200>; |
| 438 | interrupts = <1 4 7>; | 445 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 439 | pinctrl-names = "default"; | 446 | pinctrl-names = "default"; |
| 440 | pinctrl-0 = <&pinctrl_dbgu>; | 447 | pinctrl-0 = <&pinctrl_dbgu>; |
| 441 | status = "disabled"; | 448 | status = "disabled"; |
| @@ -444,7 +451,7 @@ | |||
| 444 | usart0: serial@fffc0000 { | 451 | usart0: serial@fffc0000 { |
| 445 | compatible = "atmel,at91rm9200-usart"; | 452 | compatible = "atmel,at91rm9200-usart"; |
| 446 | reg = <0xfffc0000 0x200>; | 453 | reg = <0xfffc0000 0x200>; |
| 447 | interrupts = <6 4 5>; | 454 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 448 | atmel,use-dma-rx; | 455 | atmel,use-dma-rx; |
| 449 | atmel,use-dma-tx; | 456 | atmel,use-dma-tx; |
| 450 | pinctrl-names = "default"; | 457 | pinctrl-names = "default"; |
| @@ -455,7 +462,7 @@ | |||
| 455 | usart1: serial@fffc4000 { | 462 | usart1: serial@fffc4000 { |
| 456 | compatible = "atmel,at91rm9200-usart"; | 463 | compatible = "atmel,at91rm9200-usart"; |
| 457 | reg = <0xfffc4000 0x200>; | 464 | reg = <0xfffc4000 0x200>; |
| 458 | interrupts = <7 4 5>; | 465 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 459 | atmel,use-dma-rx; | 466 | atmel,use-dma-rx; |
| 460 | atmel,use-dma-tx; | 467 | atmel,use-dma-tx; |
| 461 | pinctrl-names = "default"; | 468 | pinctrl-names = "default"; |
| @@ -466,7 +473,7 @@ | |||
| 466 | usart2: serial@fffc8000 { | 473 | usart2: serial@fffc8000 { |
| 467 | compatible = "atmel,at91rm9200-usart"; | 474 | compatible = "atmel,at91rm9200-usart"; |
| 468 | reg = <0xfffc8000 0x200>; | 475 | reg = <0xfffc8000 0x200>; |
| 469 | interrupts = <8 4 5>; | 476 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 470 | atmel,use-dma-rx; | 477 | atmel,use-dma-rx; |
| 471 | atmel,use-dma-tx; | 478 | atmel,use-dma-tx; |
| 472 | pinctrl-names = "default"; | 479 | pinctrl-names = "default"; |
| @@ -477,7 +484,7 @@ | |||
| 477 | usart3: serial@fffcc000 { | 484 | usart3: serial@fffcc000 { |
| 478 | compatible = "atmel,at91rm9200-usart"; | 485 | compatible = "atmel,at91rm9200-usart"; |
| 479 | reg = <0xfffcc000 0x200>; | 486 | reg = <0xfffcc000 0x200>; |
| 480 | interrupts = <23 4 5>; | 487 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; |
| 481 | atmel,use-dma-rx; | 488 | atmel,use-dma-rx; |
| 482 | atmel,use-dma-tx; | 489 | atmel,use-dma-tx; |
| 483 | pinctrl-names = "default"; | 490 | pinctrl-names = "default"; |
| @@ -488,7 +495,7 @@ | |||
| 488 | usb1: gadget@fffb0000 { | 495 | usb1: gadget@fffb0000 { |
| 489 | compatible = "atmel,at91rm9200-udc"; | 496 | compatible = "atmel,at91rm9200-udc"; |
| 490 | reg = <0xfffb0000 0x4000>; | 497 | reg = <0xfffb0000 0x4000>; |
| 491 | interrupts = <11 4 2>; | 498 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; |
| 492 | status = "disabled"; | 499 | status = "disabled"; |
| 493 | }; | 500 | }; |
| 494 | }; | 501 | }; |
| @@ -503,9 +510,9 @@ | |||
| 503 | pinctrl-names = "default"; | 510 | pinctrl-names = "default"; |
| 504 | pinctrl-0 = <&pinctrl_nand>; | 511 | pinctrl-0 = <&pinctrl_nand>; |
| 505 | nand-ecc-mode = "soft"; | 512 | nand-ecc-mode = "soft"; |
| 506 | gpios = <&pioC 2 0 | 513 | gpios = <&pioC 2 GPIO_ACTIVE_HIGH |
| 507 | 0 | 514 | 0 |
| 508 | &pioB 1 0 | 515 | &pioB 1 GPIO_ACTIVE_HIGH |
| 509 | >; | 516 | >; |
| 510 | status = "disabled"; | 517 | status = "disabled"; |
| 511 | }; | 518 | }; |
| @@ -513,15 +520,15 @@ | |||
| 513 | usb0: ohci@00300000 { | 520 | usb0: ohci@00300000 { |
| 514 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 521 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 515 | reg = <0x00300000 0x100000>; | 522 | reg = <0x00300000 0x100000>; |
| 516 | interrupts = <23 4 2>; | 523 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; |
| 517 | status = "disabled"; | 524 | status = "disabled"; |
| 518 | }; | 525 | }; |
| 519 | }; | 526 | }; |
| 520 | 527 | ||
| 521 | i2c@0 { | 528 | i2c@0 { |
| 522 | compatible = "i2c-gpio"; | 529 | compatible = "i2c-gpio"; |
| 523 | gpios = <&pioA 25 0 /* sda */ | 530 | gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ |
| 524 | &pioA 26 0 /* scl */ | 531 | &pioA 26 GPIO_ACTIVE_HIGH /* scl */ |
| 525 | >; | 532 | >; |
| 526 | i2c-gpio,sda-open-drain; | 533 | i2c-gpio,sda-open-drain; |
| 527 | i2c-gpio,scl-open-drain; | 534 | i2c-gpio,scl-open-drain; |
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e586d85f8e23..14058125d123 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2 only | 6 | * Licensed under GPLv2 only |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91rm9200.dtsi" | 9 | #include "at91rm9200.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91RM9200 evaluation kit"; | 12 | model = "Atmel AT91RM9200 evaluation kit"; |
| @@ -50,7 +50,7 @@ | |||
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | usb1: gadget@fffb0000 { | 52 | usb1: gadget@fffb0000 { |
| 53 | atmel,vbus-gpio = <&pioD 4 0>; | 53 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; |
| 54 | status = "okay"; | 54 | status = "okay"; |
| 55 | }; | 55 | }; |
| 56 | }; | 56 | }; |
| @@ -66,19 +66,19 @@ | |||
| 66 | 66 | ||
| 67 | ds2 { | 67 | ds2 { |
| 68 | label = "green"; | 68 | label = "green"; |
| 69 | gpios = <&pioB 0 0x1>; | 69 | gpios = <&pioB 0 GPIO_ACTIVE_LOW>; |
| 70 | linux,default-trigger = "mmc0"; | 70 | linux,default-trigger = "mmc0"; |
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| 73 | ds4 { | 73 | ds4 { |
| 74 | label = "yellow"; | 74 | label = "yellow"; |
| 75 | gpios = <&pioB 1 0x1>; | 75 | gpios = <&pioB 1 GPIO_ACTIVE_LOW>; |
| 76 | linux,default-trigger = "heartbeat"; | 76 | linux,default-trigger = "heartbeat"; |
| 77 | }; | 77 | }; |
| 78 | 78 | ||
| 79 | ds6 { | 79 | ds6 { |
| 80 | label = "red"; | 80 | label = "red"; |
| 81 | gpios = <&pioB 2 0x1>; | 81 | gpios = <&pioB 2 GPIO_ACTIVE_LOW>; |
| 82 | }; | 82 | }; |
| 83 | }; | 83 | }; |
| 84 | }; | 84 | }; |
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 84c4bef2d726..44851b977069 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi | |||
| @@ -8,7 +8,10 @@ | |||
| 8 | * Licensed under GPLv2 or later. | 8 | * Licensed under GPLv2 or later. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "skeleton.dtsi" | 11 | #include "skeleton.dtsi" |
| 12 | #include <dt-bindings/pinctrl/at91.h> | ||
| 13 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 14 | #include <dt-bindings/gpio/gpio.h> | ||
| 12 | 15 | ||
| 13 | / { | 16 | / { |
| 14 | model = "Atmel AT91SAM9260 family SoC"; | 17 | model = "Atmel AT91SAM9260 family SoC"; |
| @@ -84,19 +87,23 @@ | |||
| 84 | pit: timer@fffffd30 { | 87 | pit: timer@fffffd30 { |
| 85 | compatible = "atmel,at91sam9260-pit"; | 88 | compatible = "atmel,at91sam9260-pit"; |
| 86 | reg = <0xfffffd30 0xf>; | 89 | reg = <0xfffffd30 0xf>; |
| 87 | interrupts = <1 4 7>; | 90 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 88 | }; | 91 | }; |
| 89 | 92 | ||
| 90 | tcb0: timer@fffa0000 { | 93 | tcb0: timer@fffa0000 { |
| 91 | compatible = "atmel,at91rm9200-tcb"; | 94 | compatible = "atmel,at91rm9200-tcb"; |
| 92 | reg = <0xfffa0000 0x100>; | 95 | reg = <0xfffa0000 0x100>; |
| 93 | interrupts = <17 4 0 18 4 0 19 4 0>; | 96 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 |
| 97 | 18 IRQ_TYPE_LEVEL_HIGH 0 | ||
| 98 | 19 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 94 | }; | 99 | }; |
| 95 | 100 | ||
| 96 | tcb1: timer@fffdc000 { | 101 | tcb1: timer@fffdc000 { |
| 97 | compatible = "atmel,at91rm9200-tcb"; | 102 | compatible = "atmel,at91rm9200-tcb"; |
| 98 | reg = <0xfffdc000 0x100>; | 103 | reg = <0xfffdc000 0x100>; |
| 99 | interrupts = <26 4 0 27 4 0 28 4 0>; | 104 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 |
| 105 | 27 IRQ_TYPE_LEVEL_HIGH 0 | ||
| 106 | 28 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 100 | }; | 107 | }; |
| 101 | 108 | ||
| 102 | pinctrl@fffff400 { | 109 | pinctrl@fffff400 { |
| @@ -116,234 +123,234 @@ | |||
| 116 | dbgu { | 123 | dbgu { |
| 117 | pinctrl_dbgu: dbgu-0 { | 124 | pinctrl_dbgu: dbgu-0 { |
| 118 | atmel,pins = | 125 | atmel,pins = |
| 119 | <1 14 0x1 0x0 /* PB14 periph A */ | 126 | <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ |
| 120 | 1 15 0x1 0x1>; /* PB15 periph with pullup */ | 127 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ |
| 121 | }; | 128 | }; |
| 122 | }; | 129 | }; |
| 123 | 130 | ||
| 124 | usart0 { | 131 | usart0 { |
| 125 | pinctrl_usart0: usart0-0 { | 132 | pinctrl_usart0: usart0-0 { |
| 126 | atmel,pins = | 133 | atmel,pins = |
| 127 | <1 4 0x1 0x0 /* PB4 periph A */ | 134 | <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ |
| 128 | 1 5 0x1 0x0>; /* PB5 periph A */ | 135 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ |
| 129 | }; | 136 | }; |
| 130 | 137 | ||
| 131 | pinctrl_usart0_rts: usart0_rts-0 { | 138 | pinctrl_usart0_rts: usart0_rts-0 { |
| 132 | atmel,pins = | 139 | atmel,pins = |
| 133 | <1 26 0x1 0x0>; /* PB26 periph A */ | 140 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ |
| 134 | }; | 141 | }; |
| 135 | 142 | ||
| 136 | pinctrl_usart0_cts: usart0_cts-0 { | 143 | pinctrl_usart0_cts: usart0_cts-0 { |
| 137 | atmel,pins = | 144 | atmel,pins = |
| 138 | <1 27 0x1 0x0>; /* PB27 periph A */ | 145 | <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ |
| 139 | }; | 146 | }; |
| 140 | 147 | ||
| 141 | pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { | 148 | pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { |
| 142 | atmel,pins = | 149 | atmel,pins = |
| 143 | <1 24 0x1 0x0 /* PB24 periph A */ | 150 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ |
| 144 | 1 22 0x1 0x0>; /* PB22 periph A */ | 151 | AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ |
| 145 | }; | 152 | }; |
| 146 | 153 | ||
| 147 | pinctrl_usart0_dcd: usart0_dcd-0 { | 154 | pinctrl_usart0_dcd: usart0_dcd-0 { |
| 148 | atmel,pins = | 155 | atmel,pins = |
| 149 | <1 23 0x1 0x0>; /* PB23 periph A */ | 156 | <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ |
| 150 | }; | 157 | }; |
| 151 | 158 | ||
| 152 | pinctrl_usart0_ri: usart0_ri-0 { | 159 | pinctrl_usart0_ri: usart0_ri-0 { |
| 153 | atmel,pins = | 160 | atmel,pins = |
| 154 | <1 25 0x1 0x0>; /* PB25 periph A */ | 161 | <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ |
| 155 | }; | 162 | }; |
| 156 | }; | 163 | }; |
| 157 | 164 | ||
| 158 | usart1 { | 165 | usart1 { |
| 159 | pinctrl_usart1: usart1-0 { | 166 | pinctrl_usart1: usart1-0 { |
| 160 | atmel,pins = | 167 | atmel,pins = |
| 161 | <1 6 0x1 0x1 /* PB6 periph A with pullup */ | 168 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ |
| 162 | 1 7 0x1 0x0>; /* PB7 periph A */ | 169 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ |
| 163 | }; | 170 | }; |
| 164 | 171 | ||
| 165 | pinctrl_usart1_rts: usart1_rts-0 { | 172 | pinctrl_usart1_rts: usart1_rts-0 { |
| 166 | atmel,pins = | 173 | atmel,pins = |
| 167 | <1 28 0x1 0x0>; /* PB28 periph A */ | 174 | <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ |
| 168 | }; | 175 | }; |
| 169 | 176 | ||
| 170 | pinctrl_usart1_cts: usart1_cts-0 { | 177 | pinctrl_usart1_cts: usart1_cts-0 { |
| 171 | atmel,pins = | 178 | atmel,pins = |
| 172 | <1 29 0x1 0x0>; /* PB29 periph A */ | 179 | <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ |
| 173 | }; | 180 | }; |
| 174 | }; | 181 | }; |
| 175 | 182 | ||
| 176 | usart2 { | 183 | usart2 { |
| 177 | pinctrl_usart2: usart2-0 { | 184 | pinctrl_usart2: usart2-0 { |
| 178 | atmel,pins = | 185 | atmel,pins = |
| 179 | <1 8 0x1 0x1 /* PB8 periph A with pullup */ | 186 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ |
| 180 | 1 9 0x1 0x0>; /* PB9 periph A */ | 187 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ |
| 181 | }; | 188 | }; |
| 182 | 189 | ||
| 183 | pinctrl_usart2_rts: usart2_rts-0 { | 190 | pinctrl_usart2_rts: usart2_rts-0 { |
| 184 | atmel,pins = | 191 | atmel,pins = |
| 185 | <0 4 0x1 0x0>; /* PA4 periph A */ | 192 | <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ |
| 186 | }; | 193 | }; |
| 187 | 194 | ||
| 188 | pinctrl_usart2_cts: usart2_cts-0 { | 195 | pinctrl_usart2_cts: usart2_cts-0 { |
| 189 | atmel,pins = | 196 | atmel,pins = |
| 190 | <0 5 0x1 0x0>; /* PA5 periph A */ | 197 | <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ |
| 191 | }; | 198 | }; |
| 192 | }; | 199 | }; |
| 193 | 200 | ||
| 194 | usart3 { | 201 | usart3 { |
| 195 | pinctrl_usart3: usart3-0 { | 202 | pinctrl_usart3: usart3-0 { |
| 196 | atmel,pins = | 203 | atmel,pins = |
| 197 | <1 10 0x1 0x1 /* PB10 periph A with pullup */ | 204 | <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ |
| 198 | 1 11 0x1 0x0>; /* PB11 periph A */ | 205 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ |
| 199 | }; | 206 | }; |
| 200 | 207 | ||
| 201 | pinctrl_usart3_rts: usart3_rts-0 { | 208 | pinctrl_usart3_rts: usart3_rts-0 { |
| 202 | atmel,pins = | 209 | atmel,pins = |
| 203 | <2 8 0x2 0x0>; /* PC8 periph B */ | 210 | <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ |
| 204 | }; | 211 | }; |
| 205 | 212 | ||
| 206 | pinctrl_usart3_cts: usart3_cts-0 { | 213 | pinctrl_usart3_cts: usart3_cts-0 { |
| 207 | atmel,pins = | 214 | atmel,pins = |
| 208 | <2 10 0x2 0x0>; /* PC10 periph B */ | 215 | <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ |
| 209 | }; | 216 | }; |
| 210 | }; | 217 | }; |
| 211 | 218 | ||
| 212 | uart0 { | 219 | uart0 { |
| 213 | pinctrl_uart0: uart0-0 { | 220 | pinctrl_uart0: uart0-0 { |
| 214 | atmel,pins = | 221 | atmel,pins = |
| 215 | <0 31 0x2 0x1 /* PA31 periph B with pullup */ | 222 | <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ |
| 216 | 0 30 0x2 0x0>; /* PA30 periph B */ | 223 | AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
| 217 | }; | 224 | }; |
| 218 | }; | 225 | }; |
| 219 | 226 | ||
| 220 | uart1 { | 227 | uart1 { |
| 221 | pinctrl_uart1: uart1-0 { | 228 | pinctrl_uart1: uart1-0 { |
| 222 | atmel,pins = | 229 | atmel,pins = |
| 223 | <1 12 0x1 0x1 /* PB12 periph A with pullup */ | 230 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ |
| 224 | 1 13 0x1 0x0>; /* PB13 periph A */ | 231 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ |
| 225 | }; | 232 | }; |
| 226 | }; | 233 | }; |
| 227 | 234 | ||
| 228 | nand { | 235 | nand { |
| 229 | pinctrl_nand: nand-0 { | 236 | pinctrl_nand: nand-0 { |
| 230 | atmel,pins = | 237 | atmel,pins = |
| 231 | <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */ | 238 | <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ |
| 232 | 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ | 239 | AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ |
| 233 | }; | 240 | }; |
| 234 | }; | 241 | }; |
| 235 | 242 | ||
| 236 | macb { | 243 | macb { |
| 237 | pinctrl_macb_rmii: macb_rmii-0 { | 244 | pinctrl_macb_rmii: macb_rmii-0 { |
| 238 | atmel,pins = | 245 | atmel,pins = |
| 239 | <0 12 0x1 0x0 /* PA12 periph A */ | 246 | <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ |
| 240 | 0 13 0x1 0x0 /* PA13 periph A */ | 247 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ |
| 241 | 0 14 0x1 0x0 /* PA14 periph A */ | 248 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ |
| 242 | 0 15 0x1 0x0 /* PA15 periph A */ | 249 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ |
| 243 | 0 16 0x1 0x0 /* PA16 periph A */ | 250 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ |
| 244 | 0 17 0x1 0x0 /* PA17 periph A */ | 251 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 245 | 0 18 0x1 0x0 /* PA18 periph A */ | 252 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ |
| 246 | 0 19 0x1 0x0 /* PA19 periph A */ | 253 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ |
| 247 | 0 20 0x1 0x0 /* PA20 periph A */ | 254 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ |
| 248 | 0 21 0x1 0x0>; /* PA21 periph A */ | 255 | AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ |
| 249 | }; | 256 | }; |
| 250 | 257 | ||
| 251 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | 258 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 252 | atmel,pins = | 259 | atmel,pins = |
| 253 | <0 22 0x2 0x0 /* PA22 periph B */ | 260 | <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ |
| 254 | 0 23 0x2 0x0 /* PA23 periph B */ | 261 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ |
| 255 | 0 24 0x2 0x0 /* PA24 periph B */ | 262 | AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 256 | 0 25 0x2 0x0 /* PA25 periph B */ | 263 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 257 | 0 26 0x2 0x0 /* PA26 periph B */ | 264 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ |
| 258 | 0 27 0x2 0x0 /* PA27 periph B */ | 265 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 259 | 0 28 0x2 0x0 /* PA28 periph B */ | 266 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 260 | 0 29 0x2 0x0>; /* PA29 periph B */ | 267 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
| 261 | }; | 268 | }; |
| 262 | 269 | ||
| 263 | pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { | 270 | pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { |
| 264 | atmel,pins = | 271 | atmel,pins = |
| 265 | <0 10 0x2 0x0 /* PA10 periph B */ | 272 | <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ |
| 266 | 0 11 0x2 0x0 /* PA11 periph B */ | 273 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ |
| 267 | 0 22 0x2 0x0 /* PA22 periph B */ | 274 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ |
| 268 | 0 25 0x2 0x0 /* PA25 periph B */ | 275 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 269 | 0 26 0x2 0x0 /* PA26 periph B */ | 276 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ |
| 270 | 0 27 0x2 0x0 /* PA27 periph B */ | 277 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 271 | 0 28 0x2 0x0 /* PA28 periph B */ | 278 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 272 | 0 29 0x2 0x0>; /* PA29 periph B */ | 279 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
| 273 | }; | 280 | }; |
| 274 | }; | 281 | }; |
| 275 | 282 | ||
| 276 | mmc0 { | 283 | mmc0 { |
| 277 | pinctrl_mmc0_clk: mmc0_clk-0 { | 284 | pinctrl_mmc0_clk: mmc0_clk-0 { |
| 278 | atmel,pins = | 285 | atmel,pins = |
| 279 | <0 8 0x1 0x0>; /* PA8 periph A */ | 286 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ |
| 280 | }; | 287 | }; |
| 281 | 288 | ||
| 282 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { | 289 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { |
| 283 | atmel,pins = | 290 | atmel,pins = |
| 284 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | 291 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 285 | 0 6 0x1 0x1>; /* PA6 periph A with pullup */ | 292 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ |
| 286 | }; | 293 | }; |
| 287 | 294 | ||
| 288 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 295 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 289 | atmel,pins = | 296 | atmel,pins = |
| 290 | <0 9 0x1 0x1 /* PA9 periph A with pullup */ | 297 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ |
| 291 | 0 10 0x1 0x1 /* PA10 periph A with pullup */ | 298 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ |
| 292 | 0 11 0x1 0x1>; /* PA11 periph A with pullup */ | 299 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ |
| 293 | }; | 300 | }; |
| 294 | 301 | ||
| 295 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { | 302 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { |
| 296 | atmel,pins = | 303 | atmel,pins = |
| 297 | <0 1 0x2 0x1 /* PA1 periph B with pullup */ | 304 | <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ |
| 298 | 0 0 0x2 0x1>; /* PA0 periph B with pullup */ | 305 | AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ |
| 299 | }; | 306 | }; |
| 300 | 307 | ||
| 301 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { | 308 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { |
| 302 | atmel,pins = | 309 | atmel,pins = |
| 303 | <0 5 0x2 0x1 /* PA5 periph B with pullup */ | 310 | <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ |
| 304 | 0 4 0x2 0x1 /* PA4 periph B with pullup */ | 311 | AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ |
| 305 | 0 3 0x2 0x1>; /* PA3 periph B with pullup */ | 312 | AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ |
| 306 | }; | 313 | }; |
| 307 | }; | 314 | }; |
| 308 | 315 | ||
| 309 | ssc0 { | 316 | ssc0 { |
| 310 | pinctrl_ssc0_tx: ssc0_tx-0 { | 317 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 311 | atmel,pins = | 318 | atmel,pins = |
| 312 | <1 16 0x1 0x0 /* PB16 periph A */ | 319 | <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ |
| 313 | 1 17 0x1 0x0 /* PB17 periph A */ | 320 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ |
| 314 | 1 18 0x1 0x0>; /* PB18 periph A */ | 321 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
| 315 | }; | 322 | }; |
| 316 | 323 | ||
| 317 | pinctrl_ssc0_rx: ssc0_rx-0 { | 324 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 318 | atmel,pins = | 325 | atmel,pins = |
| 319 | <1 19 0x1 0x0 /* PB19 periph A */ | 326 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ |
| 320 | 1 20 0x1 0x0 /* PB20 periph A */ | 327 | AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ |
| 321 | 1 21 0x1 0x0>; /* PB21 periph A */ | 328 | AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ |
| 322 | }; | 329 | }; |
| 323 | }; | 330 | }; |
| 324 | 331 | ||
| 325 | spi0 { | 332 | spi0 { |
| 326 | pinctrl_spi0: spi0-0 { | 333 | pinctrl_spi0: spi0-0 { |
| 327 | atmel,pins = | 334 | atmel,pins = |
| 328 | <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */ | 335 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ |
| 329 | 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */ | 336 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ |
| 330 | 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */ | 337 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ |
| 331 | }; | 338 | }; |
| 332 | }; | 339 | }; |
| 333 | 340 | ||
| 334 | spi1 { | 341 | spi1 { |
| 335 | pinctrl_spi1: spi1-0 { | 342 | pinctrl_spi1: spi1-0 { |
| 336 | atmel,pins = | 343 | atmel,pins = |
| 337 | <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */ | 344 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ |
| 338 | 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */ | 345 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ |
| 339 | 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */ | 346 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ |
| 340 | }; | 347 | }; |
| 341 | }; | 348 | }; |
| 342 | 349 | ||
| 343 | pioA: gpio@fffff400 { | 350 | pioA: gpio@fffff400 { |
| 344 | compatible = "atmel,at91rm9200-gpio"; | 351 | compatible = "atmel,at91rm9200-gpio"; |
| 345 | reg = <0xfffff400 0x200>; | 352 | reg = <0xfffff400 0x200>; |
| 346 | interrupts = <2 4 1>; | 353 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 347 | #gpio-cells = <2>; | 354 | #gpio-cells = <2>; |
| 348 | gpio-controller; | 355 | gpio-controller; |
| 349 | interrupt-controller; | 356 | interrupt-controller; |
| @@ -353,7 +360,7 @@ | |||
| 353 | pioB: gpio@fffff600 { | 360 | pioB: gpio@fffff600 { |
| 354 | compatible = "atmel,at91rm9200-gpio"; | 361 | compatible = "atmel,at91rm9200-gpio"; |
| 355 | reg = <0xfffff600 0x200>; | 362 | reg = <0xfffff600 0x200>; |
| 356 | interrupts = <3 4 1>; | 363 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 357 | #gpio-cells = <2>; | 364 | #gpio-cells = <2>; |
| 358 | gpio-controller; | 365 | gpio-controller; |
| 359 | interrupt-controller; | 366 | interrupt-controller; |
| @@ -363,7 +370,7 @@ | |||
| 363 | pioC: gpio@fffff800 { | 370 | pioC: gpio@fffff800 { |
| 364 | compatible = "atmel,at91rm9200-gpio"; | 371 | compatible = "atmel,at91rm9200-gpio"; |
| 365 | reg = <0xfffff800 0x200>; | 372 | reg = <0xfffff800 0x200>; |
| 366 | interrupts = <4 4 1>; | 373 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| 367 | #gpio-cells = <2>; | 374 | #gpio-cells = <2>; |
| 368 | gpio-controller; | 375 | gpio-controller; |
| 369 | interrupt-controller; | 376 | interrupt-controller; |
| @@ -374,7 +381,7 @@ | |||
| 374 | dbgu: serial@fffff200 { | 381 | dbgu: serial@fffff200 { |
| 375 | compatible = "atmel,at91sam9260-usart"; | 382 | compatible = "atmel,at91sam9260-usart"; |
| 376 | reg = <0xfffff200 0x200>; | 383 | reg = <0xfffff200 0x200>; |
| 377 | interrupts = <1 4 7>; | 384 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 378 | pinctrl-names = "default"; | 385 | pinctrl-names = "default"; |
| 379 | pinctrl-0 = <&pinctrl_dbgu>; | 386 | pinctrl-0 = <&pinctrl_dbgu>; |
| 380 | status = "disabled"; | 387 | status = "disabled"; |
| @@ -383,7 +390,7 @@ | |||
| 383 | usart0: serial@fffb0000 { | 390 | usart0: serial@fffb0000 { |
| 384 | compatible = "atmel,at91sam9260-usart"; | 391 | compatible = "atmel,at91sam9260-usart"; |
| 385 | reg = <0xfffb0000 0x200>; | 392 | reg = <0xfffb0000 0x200>; |
| 386 | interrupts = <6 4 5>; | 393 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 387 | atmel,use-dma-rx; | 394 | atmel,use-dma-rx; |
| 388 | atmel,use-dma-tx; | 395 | atmel,use-dma-tx; |
| 389 | pinctrl-names = "default"; | 396 | pinctrl-names = "default"; |
| @@ -394,7 +401,7 @@ | |||
| 394 | usart1: serial@fffb4000 { | 401 | usart1: serial@fffb4000 { |
| 395 | compatible = "atmel,at91sam9260-usart"; | 402 | compatible = "atmel,at91sam9260-usart"; |
| 396 | reg = <0xfffb4000 0x200>; | 403 | reg = <0xfffb4000 0x200>; |
| 397 | interrupts = <7 4 5>; | 404 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 398 | atmel,use-dma-rx; | 405 | atmel,use-dma-rx; |
| 399 | atmel,use-dma-tx; | 406 | atmel,use-dma-tx; |
| 400 | pinctrl-names = "default"; | 407 | pinctrl-names = "default"; |
| @@ -405,7 +412,7 @@ | |||
| 405 | usart2: serial@fffb8000 { | 412 | usart2: serial@fffb8000 { |
| 406 | compatible = "atmel,at91sam9260-usart"; | 413 | compatible = "atmel,at91sam9260-usart"; |
| 407 | reg = <0xfffb8000 0x200>; | 414 | reg = <0xfffb8000 0x200>; |
| 408 | interrupts = <8 4 5>; | 415 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 409 | atmel,use-dma-rx; | 416 | atmel,use-dma-rx; |
| 410 | atmel,use-dma-tx; | 417 | atmel,use-dma-tx; |
| 411 | pinctrl-names = "default"; | 418 | pinctrl-names = "default"; |
| @@ -416,7 +423,7 @@ | |||
| 416 | usart3: serial@fffd0000 { | 423 | usart3: serial@fffd0000 { |
| 417 | compatible = "atmel,at91sam9260-usart"; | 424 | compatible = "atmel,at91sam9260-usart"; |
| 418 | reg = <0xfffd0000 0x200>; | 425 | reg = <0xfffd0000 0x200>; |
| 419 | interrupts = <23 4 5>; | 426 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; |
| 420 | atmel,use-dma-rx; | 427 | atmel,use-dma-rx; |
| 421 | atmel,use-dma-tx; | 428 | atmel,use-dma-tx; |
| 422 | pinctrl-names = "default"; | 429 | pinctrl-names = "default"; |
| @@ -427,7 +434,7 @@ | |||
| 427 | uart0: serial@fffd4000 { | 434 | uart0: serial@fffd4000 { |
| 428 | compatible = "atmel,at91sam9260-usart"; | 435 | compatible = "atmel,at91sam9260-usart"; |
| 429 | reg = <0xfffd4000 0x200>; | 436 | reg = <0xfffd4000 0x200>; |
| 430 | interrupts = <24 4 5>; | 437 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; |
| 431 | atmel,use-dma-rx; | 438 | atmel,use-dma-rx; |
| 432 | atmel,use-dma-tx; | 439 | atmel,use-dma-tx; |
| 433 | pinctrl-names = "default"; | 440 | pinctrl-names = "default"; |
| @@ -438,7 +445,7 @@ | |||
| 438 | uart1: serial@fffd8000 { | 445 | uart1: serial@fffd8000 { |
| 439 | compatible = "atmel,at91sam9260-usart"; | 446 | compatible = "atmel,at91sam9260-usart"; |
| 440 | reg = <0xfffd8000 0x200>; | 447 | reg = <0xfffd8000 0x200>; |
| 441 | interrupts = <25 4 5>; | 448 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; |
| 442 | atmel,use-dma-rx; | 449 | atmel,use-dma-rx; |
| 443 | atmel,use-dma-tx; | 450 | atmel,use-dma-tx; |
| 444 | pinctrl-names = "default"; | 451 | pinctrl-names = "default"; |
| @@ -449,7 +456,7 @@ | |||
| 449 | macb0: ethernet@fffc4000 { | 456 | macb0: ethernet@fffc4000 { |
| 450 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 457 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 451 | reg = <0xfffc4000 0x100>; | 458 | reg = <0xfffc4000 0x100>; |
| 452 | interrupts = <21 4 3>; | 459 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; |
| 453 | pinctrl-names = "default"; | 460 | pinctrl-names = "default"; |
| 454 | pinctrl-0 = <&pinctrl_macb_rmii>; | 461 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 455 | status = "disabled"; | 462 | status = "disabled"; |
| @@ -458,14 +465,14 @@ | |||
| 458 | usb1: gadget@fffa4000 { | 465 | usb1: gadget@fffa4000 { |
| 459 | compatible = "atmel,at91rm9200-udc"; | 466 | compatible = "atmel,at91rm9200-udc"; |
| 460 | reg = <0xfffa4000 0x4000>; | 467 | reg = <0xfffa4000 0x4000>; |
| 461 | interrupts = <10 4 2>; | 468 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; |
| 462 | status = "disabled"; | 469 | status = "disabled"; |
| 463 | }; | 470 | }; |
| 464 | 471 | ||
| 465 | i2c0: i2c@fffac000 { | 472 | i2c0: i2c@fffac000 { |
| 466 | compatible = "atmel,at91sam9260-i2c"; | 473 | compatible = "atmel,at91sam9260-i2c"; |
| 467 | reg = <0xfffac000 0x100>; | 474 | reg = <0xfffac000 0x100>; |
| 468 | interrupts = <11 4 6>; | 475 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
| 469 | #address-cells = <1>; | 476 | #address-cells = <1>; |
| 470 | #size-cells = <0>; | 477 | #size-cells = <0>; |
| 471 | status = "disabled"; | 478 | status = "disabled"; |
| @@ -474,7 +481,7 @@ | |||
| 474 | mmc0: mmc@fffa8000 { | 481 | mmc0: mmc@fffa8000 { |
| 475 | compatible = "atmel,hsmci"; | 482 | compatible = "atmel,hsmci"; |
| 476 | reg = <0xfffa8000 0x600>; | 483 | reg = <0xfffa8000 0x600>; |
| 477 | interrupts = <9 4 0>; | 484 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; |
| 478 | #address-cells = <1>; | 485 | #address-cells = <1>; |
| 479 | #size-cells = <0>; | 486 | #size-cells = <0>; |
| 480 | status = "disabled"; | 487 | status = "disabled"; |
| @@ -483,7 +490,7 @@ | |||
| 483 | ssc0: ssc@fffbc000 { | 490 | ssc0: ssc@fffbc000 { |
| 484 | compatible = "atmel,at91rm9200-ssc"; | 491 | compatible = "atmel,at91rm9200-ssc"; |
| 485 | reg = <0xfffbc000 0x4000>; | 492 | reg = <0xfffbc000 0x4000>; |
| 486 | interrupts = <14 4 5>; | 493 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 487 | pinctrl-names = "default"; | 494 | pinctrl-names = "default"; |
| 488 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 495 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 489 | status = "disabled"; | 496 | status = "disabled"; |
| @@ -494,7 +501,7 @@ | |||
| 494 | #size-cells = <0>; | 501 | #size-cells = <0>; |
| 495 | compatible = "atmel,at91rm9200-spi"; | 502 | compatible = "atmel,at91rm9200-spi"; |
| 496 | reg = <0xfffc8000 0x200>; | 503 | reg = <0xfffc8000 0x200>; |
| 497 | interrupts = <12 4 3>; | 504 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; |
| 498 | pinctrl-names = "default"; | 505 | pinctrl-names = "default"; |
| 499 | pinctrl-0 = <&pinctrl_spi0>; | 506 | pinctrl-0 = <&pinctrl_spi0>; |
| 500 | status = "disabled"; | 507 | status = "disabled"; |
| @@ -505,7 +512,7 @@ | |||
| 505 | #size-cells = <0>; | 512 | #size-cells = <0>; |
| 506 | compatible = "atmel,at91rm9200-spi"; | 513 | compatible = "atmel,at91rm9200-spi"; |
| 507 | reg = <0xfffcc000 0x200>; | 514 | reg = <0xfffcc000 0x200>; |
| 508 | interrupts = <13 4 3>; | 515 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 509 | pinctrl-names = "default"; | 516 | pinctrl-names = "default"; |
| 510 | pinctrl-0 = <&pinctrl_spi1>; | 517 | pinctrl-0 = <&pinctrl_spi1>; |
| 511 | status = "disabled"; | 518 | status = "disabled"; |
| @@ -514,7 +521,7 @@ | |||
| 514 | adc0: adc@fffe0000 { | 521 | adc0: adc@fffe0000 { |
| 515 | compatible = "atmel,at91sam9260-adc"; | 522 | compatible = "atmel,at91sam9260-adc"; |
| 516 | reg = <0xfffe0000 0x100>; | 523 | reg = <0xfffe0000 0x100>; |
| 517 | interrupts = <5 4 0>; | 524 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; |
| 518 | atmel,adc-use-external-triggers; | 525 | atmel,adc-use-external-triggers; |
| 519 | atmel,adc-channels-used = <0xf>; | 526 | atmel,adc-channels-used = <0xf>; |
| 520 | atmel,adc-vref = <3300>; | 527 | atmel,adc-vref = <3300>; |
| @@ -567,8 +574,8 @@ | |||
| 567 | atmel,nand-cmd-offset = <22>; | 574 | atmel,nand-cmd-offset = <22>; |
| 568 | pinctrl-names = "default"; | 575 | pinctrl-names = "default"; |
| 569 | pinctrl-0 = <&pinctrl_nand>; | 576 | pinctrl-0 = <&pinctrl_nand>; |
| 570 | gpios = <&pioC 13 0 | 577 | gpios = <&pioC 13 GPIO_ACTIVE_HIGH |
| 571 | &pioC 14 0 | 578 | &pioC 14 GPIO_ACTIVE_HIGH |
| 572 | 0 | 579 | 0 |
| 573 | >; | 580 | >; |
| 574 | status = "disabled"; | 581 | status = "disabled"; |
| @@ -577,15 +584,15 @@ | |||
| 577 | usb0: ohci@00500000 { | 584 | usb0: ohci@00500000 { |
| 578 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 585 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 579 | reg = <0x00500000 0x100000>; | 586 | reg = <0x00500000 0x100000>; |
| 580 | interrupts = <20 4 2>; | 587 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; |
| 581 | status = "disabled"; | 588 | status = "disabled"; |
| 582 | }; | 589 | }; |
| 583 | }; | 590 | }; |
| 584 | 591 | ||
| 585 | i2c@0 { | 592 | i2c@0 { |
| 586 | compatible = "i2c-gpio"; | 593 | compatible = "i2c-gpio"; |
| 587 | gpios = <&pioA 23 0 /* sda */ | 594 | gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ |
| 588 | &pioA 24 0 /* scl */ | 595 | &pioA 24 GPIO_ACTIVE_HIGH /* scl */ |
| 589 | >; | 596 | >; |
| 590 | i2c-gpio,sda-open-drain; | 597 | i2c-gpio,sda-open-drain; |
| 591 | i2c-gpio,scl-open-drain; | 598 | i2c-gpio,scl-open-drain; |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 94b58ab2cc08..d9cf51a01b60 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
| @@ -6,7 +6,10 @@ | |||
| 6 | * Licensed under GPLv2 only. | 6 | * Licensed under GPLv2 only. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "skeleton.dtsi" | 9 | #include "skeleton.dtsi" |
| 10 | #include <dt-bindings/pinctrl/at91.h> | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | #include <dt-bindings/gpio/gpio.h> | ||
| 10 | 13 | ||
| 11 | / { | 14 | / { |
| 12 | model = "Atmel AT91SAM9263 family SoC"; | 15 | model = "Atmel AT91SAM9263 family SoC"; |
| @@ -72,13 +75,13 @@ | |||
| 72 | pit: timer@fffffd30 { | 75 | pit: timer@fffffd30 { |
| 73 | compatible = "atmel,at91sam9260-pit"; | 76 | compatible = "atmel,at91sam9260-pit"; |
| 74 | reg = <0xfffffd30 0xf>; | 77 | reg = <0xfffffd30 0xf>; |
| 75 | interrupts = <1 4 7>; | 78 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 76 | }; | 79 | }; |
| 77 | 80 | ||
| 78 | tcb0: timer@fff7c000 { | 81 | tcb0: timer@fff7c000 { |
| 79 | compatible = "atmel,at91rm9200-tcb"; | 82 | compatible = "atmel,at91rm9200-tcb"; |
| 80 | reg = <0xfff7c000 0x100>; | 83 | reg = <0xfff7c000 0x100>; |
| 81 | interrupts = <19 4 0>; | 84 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 82 | }; | 85 | }; |
| 83 | 86 | ||
| 84 | rstc@fffffd00 { | 87 | rstc@fffffd00 { |
| @@ -110,221 +113,221 @@ | |||
| 110 | dbgu { | 113 | dbgu { |
| 111 | pinctrl_dbgu: dbgu-0 { | 114 | pinctrl_dbgu: dbgu-0 { |
| 112 | atmel,pins = | 115 | atmel,pins = |
| 113 | <2 30 0x1 0x0 /* PC30 periph A */ | 116 | <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */ |
| 114 | 2 31 0x1 0x1>; /* PC31 periph with pullup */ | 117 | AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */ |
| 115 | }; | 118 | }; |
| 116 | }; | 119 | }; |
| 117 | 120 | ||
| 118 | usart0 { | 121 | usart0 { |
| 119 | pinctrl_usart0: usart0-0 { | 122 | pinctrl_usart0: usart0-0 { |
| 120 | atmel,pins = | 123 | atmel,pins = |
| 121 | <0 26 0x1 0x1 /* PA26 periph A with pullup */ | 124 | <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */ |
| 122 | 0 27 0x1 0x0>; /* PA27 periph A */ | 125 | AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ |
| 123 | }; | 126 | }; |
| 124 | 127 | ||
| 125 | pinctrl_usart0_rts: usart0_rts-0 { | 128 | pinctrl_usart0_rts: usart0_rts-0 { |
| 126 | atmel,pins = | 129 | atmel,pins = |
| 127 | <0 28 0x1 0x0>; /* PA28 periph A */ | 130 | <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ |
| 128 | }; | 131 | }; |
| 129 | 132 | ||
| 130 | pinctrl_usart0_cts: usart0_cts-0 { | 133 | pinctrl_usart0_cts: usart0_cts-0 { |
| 131 | atmel,pins = | 134 | atmel,pins = |
| 132 | <0 29 0x1 0x0>; /* PA29 periph A */ | 135 | <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ |
| 133 | }; | 136 | }; |
| 134 | }; | 137 | }; |
| 135 | 138 | ||
| 136 | usart1 { | 139 | usart1 { |
| 137 | pinctrl_usart1: usart1-0 { | 140 | pinctrl_usart1: usart1-0 { |
| 138 | atmel,pins = | 141 | atmel,pins = |
| 139 | <3 0 0x1 0x1 /* PD0 periph A with pullup */ | 142 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */ |
| 140 | 3 1 0x1 0x0>; /* PD1 periph A */ | 143 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */ |
| 141 | }; | 144 | }; |
| 142 | 145 | ||
| 143 | pinctrl_usart1_rts: usart1_rts-0 { | 146 | pinctrl_usart1_rts: usart1_rts-0 { |
| 144 | atmel,pins = | 147 | atmel,pins = |
| 145 | <3 7 0x2 0x0>; /* PD7 periph B */ | 148 | <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ |
| 146 | }; | 149 | }; |
| 147 | 150 | ||
| 148 | pinctrl_usart1_cts: usart1_cts-0 { | 151 | pinctrl_usart1_cts: usart1_cts-0 { |
| 149 | atmel,pins = | 152 | atmel,pins = |
| 150 | <3 8 0x2 0x0>; /* PD8 periph B */ | 153 | <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ |
| 151 | }; | 154 | }; |
| 152 | }; | 155 | }; |
| 153 | 156 | ||
| 154 | usart2 { | 157 | usart2 { |
| 155 | pinctrl_usart2: usart2-0 { | 158 | pinctrl_usart2: usart2-0 { |
| 156 | atmel,pins = | 159 | atmel,pins = |
| 157 | <3 2 0x1 0x1 /* PD2 periph A with pullup */ | 160 | <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */ |
| 158 | 3 3 0x1 0x0>; /* PD3 periph A */ | 161 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */ |
| 159 | }; | 162 | }; |
| 160 | 163 | ||
| 161 | pinctrl_usart2_rts: usart2_rts-0 { | 164 | pinctrl_usart2_rts: usart2_rts-0 { |
| 162 | atmel,pins = | 165 | atmel,pins = |
| 163 | <3 5 0x2 0x0>; /* PD5 periph B */ | 166 | <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ |
| 164 | }; | 167 | }; |
| 165 | 168 | ||
| 166 | pinctrl_usart2_cts: usart2_cts-0 { | 169 | pinctrl_usart2_cts: usart2_cts-0 { |
| 167 | atmel,pins = | 170 | atmel,pins = |
| 168 | <4 6 0x2 0x0>; /* PD6 periph B */ | 171 | <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ |
| 169 | }; | 172 | }; |
| 170 | }; | 173 | }; |
| 171 | 174 | ||
| 172 | nand { | 175 | nand { |
| 173 | pinctrl_nand: nand-0 { | 176 | pinctrl_nand: nand-0 { |
| 174 | atmel,pins = | 177 | atmel,pins = |
| 175 | <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/ | 178 | <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/ |
| 176 | 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */ | 179 | AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */ |
| 177 | }; | 180 | }; |
| 178 | }; | 181 | }; |
| 179 | 182 | ||
| 180 | macb { | 183 | macb { |
| 181 | pinctrl_macb_rmii: macb_rmii-0 { | 184 | pinctrl_macb_rmii: macb_rmii-0 { |
| 182 | atmel,pins = | 185 | atmel,pins = |
| 183 | <2 25 0x2 0x0 /* PC25 periph B */ | 186 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ |
| 184 | 4 21 0x1 0x0 /* PE21 periph A */ | 187 | AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ |
| 185 | 4 23 0x1 0x0 /* PE23 periph A */ | 188 | AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ |
| 186 | 4 24 0x1 0x0 /* PE24 periph A */ | 189 | AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ |
| 187 | 4 25 0x1 0x0 /* PE25 periph A */ | 190 | AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ |
| 188 | 4 26 0x1 0x0 /* PE26 periph A */ | 191 | AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ |
| 189 | 4 27 0x1 0x0 /* PE27 periph A */ | 192 | AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ |
| 190 | 4 28 0x1 0x0 /* PE28 periph A */ | 193 | AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ |
| 191 | 4 29 0x1 0x0 /* PE29 periph A */ | 194 | AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ |
| 192 | 4 30 0x1 0x0>; /* PE30 periph A */ | 195 | AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ |
| 193 | }; | 196 | }; |
| 194 | 197 | ||
| 195 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | 198 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 196 | atmel,pins = | 199 | atmel,pins = |
| 197 | <2 20 0x2 0x0 /* PC20 periph B */ | 200 | <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ |
| 198 | 2 21 0x2 0x0 /* PC21 periph B */ | 201 | AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ |
| 199 | 2 22 0x2 0x0 /* PC22 periph B */ | 202 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ |
| 200 | 2 23 0x2 0x0 /* PC23 periph B */ | 203 | AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ |
| 201 | 2 24 0x2 0x0 /* PC24 periph B */ | 204 | AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ |
| 202 | 2 25 0x2 0x0 /* PC25 periph B */ | 205 | AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ |
| 203 | 2 27 0x2 0x0 /* PC27 periph B */ | 206 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ |
| 204 | 4 22 0x2 0x0>; /* PE22 periph B */ | 207 | AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ |
| 205 | }; | 208 | }; |
| 206 | }; | 209 | }; |
| 207 | 210 | ||
| 208 | mmc0 { | 211 | mmc0 { |
| 209 | pinctrl_mmc0_clk: mmc0_clk-0 { | 212 | pinctrl_mmc0_clk: mmc0_clk-0 { |
| 210 | atmel,pins = | 213 | atmel,pins = |
| 211 | <0 12 0x1 0x0>; /* PA12 periph A */ | 214 | <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ |
| 212 | }; | 215 | }; |
| 213 | 216 | ||
| 214 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { | 217 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { |
| 215 | atmel,pins = | 218 | atmel,pins = |
| 216 | <0 1 0x1 0x1 /* PA1 periph A with pullup */ | 219 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 217 | 0 0 0x1 0x1>; /* PA0 periph A with pullup */ | 220 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ |
| 218 | }; | 221 | }; |
| 219 | 222 | ||
| 220 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 223 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 221 | atmel,pins = | 224 | atmel,pins = |
| 222 | <0 3 0x1 0x1 /* PA3 periph A with pullup */ | 225 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ |
| 223 | 0 4 0x1 0x1 /* PA4 periph A with pullup */ | 226 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ |
| 224 | 0 5 0x1 0x1>; /* PA5 periph A with pullup */ | 227 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ |
| 225 | }; | 228 | }; |
| 226 | 229 | ||
| 227 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { | 230 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { |
| 228 | atmel,pins = | 231 | atmel,pins = |
| 229 | <0 16 0x1 0x1 /* PA16 periph A with pullup */ | 232 | <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 230 | 0 17 0x1 0x1>; /* PA17 periph A with pullup */ | 233 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ |
| 231 | }; | 234 | }; |
| 232 | 235 | ||
| 233 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { | 236 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { |
| 234 | atmel,pins = | 237 | atmel,pins = |
| 235 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | 238 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 236 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | 239 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 237 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | 240 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
| 238 | }; | 241 | }; |
| 239 | }; | 242 | }; |
| 240 | 243 | ||
| 241 | mmc1 { | 244 | mmc1 { |
| 242 | pinctrl_mmc1_clk: mmc1_clk-0 { | 245 | pinctrl_mmc1_clk: mmc1_clk-0 { |
| 243 | atmel,pins = | 246 | atmel,pins = |
| 244 | <0 6 0x1 0x0>; /* PA6 periph A */ | 247 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ |
| 245 | }; | 248 | }; |
| 246 | 249 | ||
| 247 | pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { | 250 | pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { |
| 248 | atmel,pins = | 251 | atmel,pins = |
| 249 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | 252 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 250 | 0 8 0x1 0x1>; /* PA8 periph A with pullup */ | 253 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ |
| 251 | }; | 254 | }; |
| 252 | 255 | ||
| 253 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | 256 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 254 | atmel,pins = | 257 | atmel,pins = |
| 255 | <0 9 0x1 0x1 /* PA9 periph A with pullup */ | 258 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ |
| 256 | 0 10 0x1 0x1 /* PA10 periph A with pullup */ | 259 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ |
| 257 | 0 11 0x1 0x1>; /* PA11 periph A with pullup */ | 260 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ |
| 258 | }; | 261 | }; |
| 259 | 262 | ||
| 260 | pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { | 263 | pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { |
| 261 | atmel,pins = | 264 | atmel,pins = |
| 262 | <0 21 0x1 0x1 /* PA21 periph A with pullup */ | 265 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ |
| 263 | 0 22 0x1 0x1>; /* PA22 periph A with pullup */ | 266 | AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ |
| 264 | }; | 267 | }; |
| 265 | 268 | ||
| 266 | pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { | 269 | pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { |
| 267 | atmel,pins = | 270 | atmel,pins = |
| 268 | <0 23 0x1 0x1 /* PA23 periph A with pullup */ | 271 | <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ |
| 269 | 0 24 0x1 0x1 /* PA24 periph A with pullup */ | 272 | AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ |
| 270 | 0 25 0x1 0x1>; /* PA25 periph A with pullup */ | 273 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ |
| 271 | }; | 274 | }; |
| 272 | }; | 275 | }; |
| 273 | 276 | ||
| 274 | ssc0 { | 277 | ssc0 { |
| 275 | pinctrl_ssc0_tx: ssc0_tx-0 { | 278 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 276 | atmel,pins = | 279 | atmel,pins = |
| 277 | <1 0 0x2 0x0 /* PB0 periph B */ | 280 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ |
| 278 | 1 1 0x2 0x0 /* PB1 periph B */ | 281 | AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ |
| 279 | 1 2 0x2 0x0>; /* PB2 periph B */ | 282 | AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ |
| 280 | }; | 283 | }; |
| 281 | 284 | ||
| 282 | pinctrl_ssc0_rx: ssc0_rx-0 { | 285 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 283 | atmel,pins = | 286 | atmel,pins = |
| 284 | <1 3 0x2 0x0 /* PB3 periph B */ | 287 | <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ |
| 285 | 1 4 0x2 0x0 /* PB4 periph B */ | 288 | AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ |
| 286 | 1 5 0x2 0x0>; /* PB5 periph B */ | 289 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ |
| 287 | }; | 290 | }; |
| 288 | }; | 291 | }; |
| 289 | 292 | ||
| 290 | ssc1 { | 293 | ssc1 { |
| 291 | pinctrl_ssc1_tx: ssc1_tx-0 { | 294 | pinctrl_ssc1_tx: ssc1_tx-0 { |
| 292 | atmel,pins = | 295 | atmel,pins = |
| 293 | <1 6 0x1 0x0 /* PB6 periph A */ | 296 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
| 294 | 1 7 0x1 0x0 /* PB7 periph A */ | 297 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ |
| 295 | 1 8 0x1 0x0>; /* PB8 periph A */ | 298 | AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ |
| 296 | }; | 299 | }; |
| 297 | 300 | ||
| 298 | pinctrl_ssc1_rx: ssc1_rx-0 { | 301 | pinctrl_ssc1_rx: ssc1_rx-0 { |
| 299 | atmel,pins = | 302 | atmel,pins = |
| 300 | <1 9 0x1 0x0 /* PB9 periph A */ | 303 | <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
| 301 | 1 10 0x1 0x0 /* PB10 periph A */ | 304 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ |
| 302 | 1 11 0x1 0x0>; /* PB11 periph A */ | 305 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ |
| 303 | }; | 306 | }; |
| 304 | }; | 307 | }; |
| 305 | 308 | ||
| 306 | spi0 { | 309 | spi0 { |
| 307 | pinctrl_spi0: spi0-0 { | 310 | pinctrl_spi0: spi0-0 { |
| 308 | atmel,pins = | 311 | atmel,pins = |
| 309 | <0 0 0x2 0x0 /* PA0 periph B SPI0_MISO pin */ | 312 | <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ |
| 310 | 0 1 0x2 0x0 /* PA1 periph B SPI0_MOSI pin */ | 313 | AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ |
| 311 | 0 2 0x2 0x0>; /* PA2 periph B SPI0_SPCK pin */ | 314 | AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ |
| 312 | }; | 315 | }; |
| 313 | }; | 316 | }; |
| 314 | 317 | ||
| 315 | spi1 { | 318 | spi1 { |
| 316 | pinctrl_spi1: spi1-0 { | 319 | pinctrl_spi1: spi1-0 { |
| 317 | atmel,pins = | 320 | atmel,pins = |
| 318 | <1 12 0x1 0x0 /* PB12 periph A SPI1_MISO pin */ | 321 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ |
| 319 | 1 13 0x1 0x0 /* PB13 periph A SPI1_MOSI pin */ | 322 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ |
| 320 | 1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */ | 323 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ |
| 321 | }; | 324 | }; |
| 322 | }; | 325 | }; |
| 323 | 326 | ||
| 324 | pioA: gpio@fffff200 { | 327 | pioA: gpio@fffff200 { |
| 325 | compatible = "atmel,at91rm9200-gpio"; | 328 | compatible = "atmel,at91rm9200-gpio"; |
| 326 | reg = <0xfffff200 0x200>; | 329 | reg = <0xfffff200 0x200>; |
| 327 | interrupts = <2 4 1>; | 330 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 328 | #gpio-cells = <2>; | 331 | #gpio-cells = <2>; |
| 329 | gpio-controller; | 332 | gpio-controller; |
| 330 | interrupt-controller; | 333 | interrupt-controller; |
| @@ -334,7 +337,7 @@ | |||
| 334 | pioB: gpio@fffff400 { | 337 | pioB: gpio@fffff400 { |
| 335 | compatible = "atmel,at91rm9200-gpio"; | 338 | compatible = "atmel,at91rm9200-gpio"; |
| 336 | reg = <0xfffff400 0x200>; | 339 | reg = <0xfffff400 0x200>; |
| 337 | interrupts = <3 4 1>; | 340 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 338 | #gpio-cells = <2>; | 341 | #gpio-cells = <2>; |
| 339 | gpio-controller; | 342 | gpio-controller; |
| 340 | interrupt-controller; | 343 | interrupt-controller; |
| @@ -344,7 +347,7 @@ | |||
| 344 | pioC: gpio@fffff600 { | 347 | pioC: gpio@fffff600 { |
| 345 | compatible = "atmel,at91rm9200-gpio"; | 348 | compatible = "atmel,at91rm9200-gpio"; |
| 346 | reg = <0xfffff600 0x200>; | 349 | reg = <0xfffff600 0x200>; |
| 347 | interrupts = <4 4 1>; | 350 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| 348 | #gpio-cells = <2>; | 351 | #gpio-cells = <2>; |
| 349 | gpio-controller; | 352 | gpio-controller; |
| 350 | interrupt-controller; | 353 | interrupt-controller; |
| @@ -354,7 +357,7 @@ | |||
| 354 | pioD: gpio@fffff800 { | 357 | pioD: gpio@fffff800 { |
| 355 | compatible = "atmel,at91rm9200-gpio"; | 358 | compatible = "atmel,at91rm9200-gpio"; |
| 356 | reg = <0xfffff800 0x200>; | 359 | reg = <0xfffff800 0x200>; |
| 357 | interrupts = <4 4 1>; | 360 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| 358 | #gpio-cells = <2>; | 361 | #gpio-cells = <2>; |
| 359 | gpio-controller; | 362 | gpio-controller; |
| 360 | interrupt-controller; | 363 | interrupt-controller; |
| @@ -364,7 +367,7 @@ | |||
| 364 | pioE: gpio@fffffa00 { | 367 | pioE: gpio@fffffa00 { |
| 365 | compatible = "atmel,at91rm9200-gpio"; | 368 | compatible = "atmel,at91rm9200-gpio"; |
| 366 | reg = <0xfffffa00 0x200>; | 369 | reg = <0xfffffa00 0x200>; |
| 367 | interrupts = <4 4 1>; | 370 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| 368 | #gpio-cells = <2>; | 371 | #gpio-cells = <2>; |
| 369 | gpio-controller; | 372 | gpio-controller; |
| 370 | interrupt-controller; | 373 | interrupt-controller; |
| @@ -375,7 +378,7 @@ | |||
| 375 | dbgu: serial@ffffee00 { | 378 | dbgu: serial@ffffee00 { |
| 376 | compatible = "atmel,at91sam9260-usart"; | 379 | compatible = "atmel,at91sam9260-usart"; |
| 377 | reg = <0xffffee00 0x200>; | 380 | reg = <0xffffee00 0x200>; |
| 378 | interrupts = <1 4 7>; | 381 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 379 | pinctrl-names = "default"; | 382 | pinctrl-names = "default"; |
| 380 | pinctrl-0 = <&pinctrl_dbgu>; | 383 | pinctrl-0 = <&pinctrl_dbgu>; |
| 381 | status = "disabled"; | 384 | status = "disabled"; |
| @@ -384,7 +387,7 @@ | |||
| 384 | usart0: serial@fff8c000 { | 387 | usart0: serial@fff8c000 { |
| 385 | compatible = "atmel,at91sam9260-usart"; | 388 | compatible = "atmel,at91sam9260-usart"; |
| 386 | reg = <0xfff8c000 0x200>; | 389 | reg = <0xfff8c000 0x200>; |
| 387 | interrupts = <7 4 5>; | 390 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 388 | atmel,use-dma-rx; | 391 | atmel,use-dma-rx; |
| 389 | atmel,use-dma-tx; | 392 | atmel,use-dma-tx; |
| 390 | pinctrl-names = "default"; | 393 | pinctrl-names = "default"; |
| @@ -395,7 +398,7 @@ | |||
| 395 | usart1: serial@fff90000 { | 398 | usart1: serial@fff90000 { |
| 396 | compatible = "atmel,at91sam9260-usart"; | 399 | compatible = "atmel,at91sam9260-usart"; |
| 397 | reg = <0xfff90000 0x200>; | 400 | reg = <0xfff90000 0x200>; |
| 398 | interrupts = <8 4 5>; | 401 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 399 | atmel,use-dma-rx; | 402 | atmel,use-dma-rx; |
| 400 | atmel,use-dma-tx; | 403 | atmel,use-dma-tx; |
| 401 | pinctrl-names = "default"; | 404 | pinctrl-names = "default"; |
| @@ -406,7 +409,7 @@ | |||
| 406 | usart2: serial@fff94000 { | 409 | usart2: serial@fff94000 { |
| 407 | compatible = "atmel,at91sam9260-usart"; | 410 | compatible = "atmel,at91sam9260-usart"; |
| 408 | reg = <0xfff94000 0x200>; | 411 | reg = <0xfff94000 0x200>; |
| 409 | interrupts = <9 4 5>; | 412 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; |
| 410 | atmel,use-dma-rx; | 413 | atmel,use-dma-rx; |
| 411 | atmel,use-dma-tx; | 414 | atmel,use-dma-tx; |
| 412 | pinctrl-names = "default"; | 415 | pinctrl-names = "default"; |
| @@ -417,7 +420,7 @@ | |||
| 417 | ssc0: ssc@fff98000 { | 420 | ssc0: ssc@fff98000 { |
| 418 | compatible = "atmel,at91rm9200-ssc"; | 421 | compatible = "atmel,at91rm9200-ssc"; |
| 419 | reg = <0xfff98000 0x4000>; | 422 | reg = <0xfff98000 0x4000>; |
| 420 | interrupts = <16 4 5>; | 423 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 421 | pinctrl-names = "default"; | 424 | pinctrl-names = "default"; |
| 422 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 425 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 423 | status = "disabled"; | 426 | status = "disabled"; |
| @@ -426,7 +429,7 @@ | |||
| 426 | ssc1: ssc@fff9c000 { | 429 | ssc1: ssc@fff9c000 { |
| 427 | compatible = "atmel,at91rm9200-ssc"; | 430 | compatible = "atmel,at91rm9200-ssc"; |
| 428 | reg = <0xfff9c000 0x4000>; | 431 | reg = <0xfff9c000 0x4000>; |
| 429 | interrupts = <17 4 5>; | 432 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
| 430 | pinctrl-names = "default"; | 433 | pinctrl-names = "default"; |
| 431 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 434 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 432 | status = "disabled"; | 435 | status = "disabled"; |
| @@ -435,7 +438,7 @@ | |||
| 435 | macb0: ethernet@fffbc000 { | 438 | macb0: ethernet@fffbc000 { |
| 436 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 439 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 437 | reg = <0xfffbc000 0x100>; | 440 | reg = <0xfffbc000 0x100>; |
| 438 | interrupts = <21 4 3>; | 441 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; |
| 439 | pinctrl-names = "default"; | 442 | pinctrl-names = "default"; |
| 440 | pinctrl-0 = <&pinctrl_macb_rmii>; | 443 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 441 | status = "disabled"; | 444 | status = "disabled"; |
| @@ -444,14 +447,14 @@ | |||
| 444 | usb1: gadget@fff78000 { | 447 | usb1: gadget@fff78000 { |
| 445 | compatible = "atmel,at91rm9200-udc"; | 448 | compatible = "atmel,at91rm9200-udc"; |
| 446 | reg = <0xfff78000 0x4000>; | 449 | reg = <0xfff78000 0x4000>; |
| 447 | interrupts = <24 4 2>; | 450 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; |
| 448 | status = "disabled"; | 451 | status = "disabled"; |
| 449 | }; | 452 | }; |
| 450 | 453 | ||
| 451 | i2c0: i2c@fff88000 { | 454 | i2c0: i2c@fff88000 { |
| 452 | compatible = "atmel,at91sam9263-i2c"; | 455 | compatible = "atmel,at91sam9263-i2c"; |
| 453 | reg = <0xfff88000 0x100>; | 456 | reg = <0xfff88000 0x100>; |
| 454 | interrupts = <13 4 6>; | 457 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
| 455 | #address-cells = <1>; | 458 | #address-cells = <1>; |
| 456 | #size-cells = <0>; | 459 | #size-cells = <0>; |
| 457 | status = "disabled"; | 460 | status = "disabled"; |
| @@ -460,7 +463,7 @@ | |||
| 460 | mmc0: mmc@fff80000 { | 463 | mmc0: mmc@fff80000 { |
| 461 | compatible = "atmel,hsmci"; | 464 | compatible = "atmel,hsmci"; |
| 462 | reg = <0xfff80000 0x600>; | 465 | reg = <0xfff80000 0x600>; |
| 463 | interrupts = <10 4 0>; | 466 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; |
| 464 | #address-cells = <1>; | 467 | #address-cells = <1>; |
| 465 | #size-cells = <0>; | 468 | #size-cells = <0>; |
| 466 | status = "disabled"; | 469 | status = "disabled"; |
| @@ -469,7 +472,7 @@ | |||
| 469 | mmc1: mmc@fff84000 { | 472 | mmc1: mmc@fff84000 { |
| 470 | compatible = "atmel,hsmci"; | 473 | compatible = "atmel,hsmci"; |
| 471 | reg = <0xfff84000 0x600>; | 474 | reg = <0xfff84000 0x600>; |
| 472 | interrupts = <11 4 0>; | 475 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
| 473 | #address-cells = <1>; | 476 | #address-cells = <1>; |
| 474 | #size-cells = <0>; | 477 | #size-cells = <0>; |
| 475 | status = "disabled"; | 478 | status = "disabled"; |
| @@ -486,7 +489,7 @@ | |||
| 486 | #size-cells = <0>; | 489 | #size-cells = <0>; |
| 487 | compatible = "atmel,at91rm9200-spi"; | 490 | compatible = "atmel,at91rm9200-spi"; |
| 488 | reg = <0xfffa4000 0x200>; | 491 | reg = <0xfffa4000 0x200>; |
| 489 | interrupts = <14 4 3>; | 492 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| 490 | pinctrl-names = "default"; | 493 | pinctrl-names = "default"; |
| 491 | pinctrl-0 = <&pinctrl_spi0>; | 494 | pinctrl-0 = <&pinctrl_spi0>; |
| 492 | status = "disabled"; | 495 | status = "disabled"; |
| @@ -497,7 +500,7 @@ | |||
| 497 | #size-cells = <0>; | 500 | #size-cells = <0>; |
| 498 | compatible = "atmel,at91rm9200-spi"; | 501 | compatible = "atmel,at91rm9200-spi"; |
| 499 | reg = <0xfffa8000 0x200>; | 502 | reg = <0xfffa8000 0x200>; |
| 500 | interrupts = <15 4 3>; | 503 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; |
| 501 | pinctrl-names = "default"; | 504 | pinctrl-names = "default"; |
| 502 | pinctrl-0 = <&pinctrl_spi1>; | 505 | pinctrl-0 = <&pinctrl_spi1>; |
| 503 | status = "disabled"; | 506 | status = "disabled"; |
| @@ -515,8 +518,8 @@ | |||
| 515 | atmel,nand-cmd-offset = <22>; | 518 | atmel,nand-cmd-offset = <22>; |
| 516 | pinctrl-names = "default"; | 519 | pinctrl-names = "default"; |
| 517 | pinctrl-0 = <&pinctrl_nand>; | 520 | pinctrl-0 = <&pinctrl_nand>; |
| 518 | gpios = <&pioA 22 0 | 521 | gpios = <&pioA 22 GPIO_ACTIVE_HIGH |
| 519 | &pioD 15 0 | 522 | &pioD 15 GPIO_ACTIVE_HIGH |
| 520 | 0 | 523 | 0 |
| 521 | >; | 524 | >; |
| 522 | status = "disabled"; | 525 | status = "disabled"; |
| @@ -525,15 +528,15 @@ | |||
| 525 | usb0: ohci@00a00000 { | 528 | usb0: ohci@00a00000 { |
| 526 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 529 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 527 | reg = <0x00a00000 0x100000>; | 530 | reg = <0x00a00000 0x100000>; |
| 528 | interrupts = <29 4 2>; | 531 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; |
| 529 | status = "disabled"; | 532 | status = "disabled"; |
| 530 | }; | 533 | }; |
| 531 | }; | 534 | }; |
| 532 | 535 | ||
| 533 | i2c@0 { | 536 | i2c@0 { |
| 534 | compatible = "i2c-gpio"; | 537 | compatible = "i2c-gpio"; |
| 535 | gpios = <&pioB 4 0 /* sda */ | 538 | gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ |
| 536 | &pioB 5 0 /* scl */ | 539 | &pioB 5 GPIO_ACTIVE_HIGH /* scl */ |
| 537 | >; | 540 | >; |
| 538 | i2c-gpio,sda-open-drain; | 541 | i2c-gpio,sda-open-drain; |
| 539 | i2c-gpio,scl-open-drain; | 542 | i2c-gpio,scl-open-drain; |
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 3b82d91e7fcc..eff1afb81304 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2 only | 6 | * Licensed under GPLv2 only |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9263.dtsi" | 9 | #include "at91sam9263.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel at91sam9263ek"; | 12 | model = "Atmel at91sam9263ek"; |
| @@ -51,7 +51,7 @@ | |||
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | usb1: gadget@fff78000 { | 53 | usb1: gadget@fff78000 { |
| 54 | atmel,vbus-gpio = <&pioA 25 0>; | 54 | atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; |
| 55 | status = "okay"; | 55 | status = "okay"; |
| 56 | }; | 56 | }; |
| 57 | 57 | ||
| @@ -65,8 +65,8 @@ | |||
| 65 | slot@0 { | 65 | slot@0 { |
| 66 | reg = <0>; | 66 | reg = <0>; |
| 67 | bus-width = <4>; | 67 | bus-width = <4>; |
| 68 | cd-gpios = <&pioE 18 0>; | 68 | cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; |
| 69 | wp-gpios = <&pioE 19 0>; | 69 | wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; |
| 70 | }; | 70 | }; |
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| @@ -74,8 +74,8 @@ | |||
| 74 | mmc0 { | 74 | mmc0 { |
| 75 | pinctrl_board_mmc0: mmc0-board { | 75 | pinctrl_board_mmc0: mmc0-board { |
| 76 | atmel,pins = | 76 | atmel,pins = |
| 77 | <5 18 0x0 0x5 /* PE18 gpio CD pin pull up and deglitch */ | 77 | <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PE18 gpio CD pin pull up and deglitch */ |
| 78 | 5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */ | 78 | AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */ |
| 79 | }; | 79 | }; |
| 80 | }; | 80 | }; |
| 81 | }; | 81 | }; |
| @@ -141,8 +141,8 @@ | |||
| 141 | usb0: ohci@00a00000 { | 141 | usb0: ohci@00a00000 { |
| 142 | num-ports = <2>; | 142 | num-ports = <2>; |
| 143 | status = "okay"; | 143 | status = "okay"; |
| 144 | atmel,vbus-gpio = <&pioA 24 0 | 144 | atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH |
| 145 | &pioA 21 0 | 145 | &pioA 21 GPIO_ACTIVE_HIGH |
| 146 | >; | 146 | >; |
| 147 | }; | 147 | }; |
| 148 | }; | 148 | }; |
| @@ -152,13 +152,13 @@ | |||
| 152 | 152 | ||
| 153 | d3 { | 153 | d3 { |
| 154 | label = "d3"; | 154 | label = "d3"; |
| 155 | gpios = <&pioB 7 0>; | 155 | gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; |
| 156 | linux,default-trigger = "heartbeat"; | 156 | linux,default-trigger = "heartbeat"; |
| 157 | }; | 157 | }; |
| 158 | 158 | ||
| 159 | d2 { | 159 | d2 { |
| 160 | label = "d2"; | 160 | label = "d2"; |
| 161 | gpios = <&pioC 29 1>; | 161 | gpios = <&pioC 29 GPIO_ACTIVE_LOW>; |
| 162 | linux,default-trigger = "nand-disk"; | 162 | linux,default-trigger = "nand-disk"; |
| 163 | }; | 163 | }; |
| 164 | }; | 164 | }; |
| @@ -168,14 +168,14 @@ | |||
| 168 | 168 | ||
| 169 | left_click { | 169 | left_click { |
| 170 | label = "left_click"; | 170 | label = "left_click"; |
| 171 | gpios = <&pioC 5 1>; | 171 | gpios = <&pioC 5 GPIO_ACTIVE_LOW>; |
| 172 | linux,code = <272>; | 172 | linux,code = <272>; |
| 173 | gpio-key,wakeup; | 173 | gpio-key,wakeup; |
| 174 | }; | 174 | }; |
| 175 | 175 | ||
| 176 | right_click { | 176 | right_click { |
| 177 | label = "right_click"; | 177 | label = "right_click"; |
| 178 | gpios = <&pioC 4 1>; | 178 | gpios = <&pioC 4 GPIO_ACTIVE_LOW>; |
| 179 | linux,code = <273>; | 179 | linux,code = <273>; |
| 180 | gpio-key,wakeup; | 180 | gpio-key,wakeup; |
| 181 | }; | 181 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index 28467fd6bf96..cfd7044616d7 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "at91sam9x5.dtsi" | 9 | #include "at91sam9x5.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G15 SoC"; | 12 | model = "Atmel AT91SAM9G15 SoC"; |
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts index 5427b2dba87e..26b0444b0f96 100644 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ b/arch/arm/boot/dts/at91sam9g15ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9g15.dtsi" | 10 | #include "at91sam9g15.dtsi" |
| 11 | /include/ "at91sam9x5ek.dtsi" | 11 | #include "at91sam9x5ek.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G15-EK"; | 14 | model = "Atmel AT91SAM9G15-EK"; |
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 75ce6e760016..b8e79466014f 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "at91sam9260.dtsi" | 9 | #include "at91sam9260.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G20 family SoC"; | 12 | model = "Atmel AT91SAM9G20 family SoC"; |
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts index e5324bf9d529..bbfd753112c9 100644 --- a/arch/arm/boot/dts/at91sam9g20ek.dts +++ b/arch/arm/boot/dts/at91sam9g20ek.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9g20ek_common.dtsi" | 9 | #include "at91sam9g20ek_common.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel at91sam9g20ek"; | 12 | model = "Atmel at91sam9g20ek"; |
| @@ -17,13 +17,13 @@ | |||
| 17 | 17 | ||
| 18 | ds1 { | 18 | ds1 { |
| 19 | label = "ds1"; | 19 | label = "ds1"; |
| 20 | gpios = <&pioA 9 0>; | 20 | gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; |
| 21 | linux,default-trigger = "heartbeat"; | 21 | linux,default-trigger = "heartbeat"; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | ds5 { | 24 | ds5 { |
| 25 | label = "ds5"; | 25 | label = "ds5"; |
| 26 | gpios = <&pioA 6 1>; | 26 | gpios = <&pioA 6 GPIO_ACTIVE_LOW>; |
| 27 | }; | 27 | }; |
| 28 | }; | 28 | }; |
| 29 | }; | 29 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts index 66467b113126..bdb799bad179 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9g20ek_common.dtsi" | 9 | #include "at91sam9g20ek_common.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel at91sam9g20ek 2 mmc"; | 12 | model = "Atmel at91sam9g20ek 2 mmc"; |
| @@ -23,7 +23,7 @@ | |||
| 23 | slot@0 { | 23 | slot@0 { |
| 24 | reg = <0>; | 24 | reg = <0>; |
| 25 | bus-width = <4>; | 25 | bus-width = <4>; |
| 26 | cd-gpios = <&pioC 2 0>; | 26 | cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; |
| 27 | }; | 27 | }; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| @@ -31,7 +31,7 @@ | |||
| 31 | mmc0_slot0 { | 31 | mmc0_slot0 { |
| 32 | pinctrl_board_mmc0_slot0: mmc0_slot0-board { | 32 | pinctrl_board_mmc0_slot0: mmc0_slot0-board { |
| 33 | atmel,pins = | 33 | atmel,pins = |
| 34 | <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */ | 34 | <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC2 gpio CD pin pull up and deglitch */ |
| 35 | }; | 35 | }; |
| 36 | }; | 36 | }; |
| 37 | }; | 37 | }; |
| @@ -43,13 +43,13 @@ | |||
| 43 | 43 | ||
| 44 | ds1 { | 44 | ds1 { |
| 45 | label = "ds1"; | 45 | label = "ds1"; |
| 46 | gpios = <&pioB 9 0>; | 46 | gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; |
| 47 | linux,default-trigger = "heartbeat"; | 47 | linux,default-trigger = "heartbeat"; |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | ds5 { | 50 | ds5 { |
| 51 | label = "ds5"; | 51 | label = "ds5"; |
| 52 | gpios = <&pioB 8 1>; | 52 | gpios = <&pioB 8 GPIO_ACTIVE_LOW>; |
| 53 | }; | 53 | }; |
| 54 | }; | 54 | }; |
| 55 | }; | 55 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 6a92c5baef8c..c7ffc32918f9 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi | |||
| @@ -5,7 +5,7 @@ | |||
| 5 | * | 5 | * |
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /include/ "at91sam9g20.dtsi" | 8 | #include "at91sam9g20.dtsi" |
| 9 | 9 | ||
| 10 | / { | 10 | / { |
| 11 | 11 | ||
| @@ -34,10 +34,17 @@ | |||
| 34 | board { | 34 | board { |
| 35 | pinctrl_pck0_as_mck: pck0_as_mck { | 35 | pinctrl_pck0_as_mck: pck0_as_mck { |
| 36 | atmel,pins = | 36 | atmel,pins = |
| 37 | <2 1 0x2 0x0>; /* PC1 periph B */ | 37 | <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | }; | 40 | }; |
| 41 | |||
| 42 | mmc0_slot1 { | ||
| 43 | pinctrl_board_mmc0_slot1: mmc0_slot1-board { | ||
| 44 | atmel,pins = | ||
| 45 | <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */ | ||
| 46 | }; | ||
| 47 | }; | ||
| 41 | }; | 48 | }; |
| 42 | 49 | ||
| 43 | dbgu: serial@fffff200 { | 50 | dbgu: serial@fffff200 { |
| @@ -65,7 +72,7 @@ | |||
| 65 | }; | 72 | }; |
| 66 | 73 | ||
| 67 | usb1: gadget@fffa4000 { | 74 | usb1: gadget@fffa4000 { |
| 68 | atmel,vbus-gpio = <&pioC 5 0>; | 75 | atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; |
| 69 | status = "okay"; | 76 | status = "okay"; |
| 70 | }; | 77 | }; |
| 71 | 78 | ||
| @@ -79,16 +86,7 @@ | |||
| 79 | slot@1 { | 86 | slot@1 { |
| 80 | reg = <1>; | 87 | reg = <1>; |
| 81 | bus-width = <4>; | 88 | bus-width = <4>; |
| 82 | cd-gpios = <&pioC 9 0>; | 89 | cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; |
| 83 | }; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pinctrl@fffff400 { | ||
| 87 | mmc0_slot1 { | ||
| 88 | pinctrl_board_mmc0_slot1: mmc0_slot1-board { | ||
| 89 | atmel,pins = | ||
| 90 | <2 9 0x0 0x5>; /* PC9 gpio CD pin pull up and deglitch */ | ||
| 91 | }; | ||
| 92 | }; | 90 | }; |
| 93 | }; | 91 | }; |
| 94 | 92 | ||
| @@ -180,14 +178,14 @@ | |||
| 180 | 178 | ||
| 181 | btn3 { | 179 | btn3 { |
| 182 | label = "Button 3"; | 180 | label = "Button 3"; |
| 183 | gpios = <&pioA 30 1>; | 181 | gpios = <&pioA 30 GPIO_ACTIVE_LOW>; |
| 184 | linux,code = <0x103>; | 182 | linux,code = <0x103>; |
| 185 | gpio-key,wakeup; | 183 | gpio-key,wakeup; |
| 186 | }; | 184 | }; |
| 187 | 185 | ||
| 188 | btn4 { | 186 | btn4 { |
| 189 | label = "Button 4"; | 187 | label = "Button 4"; |
| 190 | gpios = <&pioA 31 1>; | 188 | gpios = <&pioA 31 GPIO_ACTIVE_LOW>; |
| 191 | linux,code = <0x104>; | 189 | linux,code = <0x104>; |
| 192 | gpio-key,wakeup; | 190 | gpio-key,wakeup; |
| 193 | }; | 191 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 5fd32df03f25..b4ec6fe53fc7 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "at91sam9x5.dtsi" | 9 | #include "at91sam9x5.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G25 SoC"; | 12 | model = "Atmel AT91SAM9G25 SoC"; |
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index a1c511fecdc1..1e4c49c584d3 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9g25.dtsi" | 10 | #include "at91sam9g25.dtsi" |
| 11 | /include/ "at91sam9x5ek.dtsi" | 11 | #include "at91sam9x5ek.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G25-EK"; | 14 | model = "Atmel AT91SAM9G25-EK"; |
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index d6fa8af50724..bebf9f55614b 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "at91sam9x5.dtsi" | 9 | #include "at91sam9x5.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9G35 SoC"; | 12 | model = "Atmel AT91SAM9G35 SoC"; |
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts index 6f58ab8d21f5..641a9bf89ed1 100644 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ b/arch/arm/boot/dts/at91sam9g35ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9g35.dtsi" | 10 | #include "at91sam9g35.dtsi" |
| 11 | /include/ "at91sam9x5ek.dtsi" | 11 | #include "at91sam9x5ek.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9G35-EK"; | 14 | model = "Atmel AT91SAM9G35-EK"; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index bf18a735c37d..f0091af6c285 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -9,7 +9,10 @@ | |||
| 9 | * Licensed under GPLv2 or later. | 9 | * Licensed under GPLv2 or later. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include <dt-bindings/pinctrl/at91.h> | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | 16 | ||
| 14 | / { | 17 | / { |
| 15 | model = "Atmel AT91SAM9G45 family SoC"; | 18 | model = "Atmel AT91SAM9G45 family SoC"; |
| @@ -83,7 +86,7 @@ | |||
| 83 | pit: timer@fffffd30 { | 86 | pit: timer@fffffd30 { |
| 84 | compatible = "atmel,at91sam9260-pit"; | 87 | compatible = "atmel,at91sam9260-pit"; |
| 85 | reg = <0xfffffd30 0xf>; | 88 | reg = <0xfffffd30 0xf>; |
| 86 | interrupts = <1 4 7>; | 89 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 87 | }; | 90 | }; |
| 88 | 91 | ||
| 89 | 92 | ||
| @@ -95,19 +98,19 @@ | |||
| 95 | tcb0: timer@fff7c000 { | 98 | tcb0: timer@fff7c000 { |
| 96 | compatible = "atmel,at91rm9200-tcb"; | 99 | compatible = "atmel,at91rm9200-tcb"; |
| 97 | reg = <0xfff7c000 0x100>; | 100 | reg = <0xfff7c000 0x100>; |
| 98 | interrupts = <18 4 0>; | 101 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; |
| 99 | }; | 102 | }; |
| 100 | 103 | ||
| 101 | tcb1: timer@fffd4000 { | 104 | tcb1: timer@fffd4000 { |
| 102 | compatible = "atmel,at91rm9200-tcb"; | 105 | compatible = "atmel,at91rm9200-tcb"; |
| 103 | reg = <0xfffd4000 0x100>; | 106 | reg = <0xfffd4000 0x100>; |
| 104 | interrupts = <18 4 0>; | 107 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; |
| 105 | }; | 108 | }; |
| 106 | 109 | ||
| 107 | dma: dma-controller@ffffec00 { | 110 | dma: dma-controller@ffffec00 { |
| 108 | compatible = "atmel,at91sam9g45-dma"; | 111 | compatible = "atmel,at91sam9g45-dma"; |
| 109 | reg = <0xffffec00 0x200>; | 112 | reg = <0xffffec00 0x200>; |
| 110 | interrupts = <21 4 0>; | 113 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
| 111 | #dma-cells = <2>; | 114 | #dma-cells = <2>; |
| 112 | }; | 115 | }; |
| 113 | 116 | ||
| @@ -130,221 +133,221 @@ | |||
| 130 | dbgu { | 133 | dbgu { |
| 131 | pinctrl_dbgu: dbgu-0 { | 134 | pinctrl_dbgu: dbgu-0 { |
| 132 | atmel,pins = | 135 | atmel,pins = |
| 133 | <1 12 0x1 0x0 /* PB12 periph A */ | 136 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
| 134 | 1 13 0x1 0x0>; /* PB13 periph A */ | 137 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ |
| 135 | }; | 138 | }; |
| 136 | }; | 139 | }; |
| 137 | 140 | ||
| 138 | usart0 { | 141 | usart0 { |
| 139 | pinctrl_usart0: usart0-0 { | 142 | pinctrl_usart0: usart0-0 { |
| 140 | atmel,pins = | 143 | atmel,pins = |
| 141 | <1 19 0x1 0x1 /* PB19 periph A with pullup */ | 144 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ |
| 142 | 1 18 0x1 0x0>; /* PB18 periph A */ | 145 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
| 143 | }; | 146 | }; |
| 144 | 147 | ||
| 145 | pinctrl_usart0_rts: usart0_rts-0 { | 148 | pinctrl_usart0_rts: usart0_rts-0 { |
| 146 | atmel,pins = | 149 | atmel,pins = |
| 147 | <1 17 0x2 0x0>; /* PB17 periph B */ | 150 | <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ |
| 148 | }; | 151 | }; |
| 149 | 152 | ||
| 150 | pinctrl_usart0_cts: usart0_cts-0 { | 153 | pinctrl_usart0_cts: usart0_cts-0 { |
| 151 | atmel,pins = | 154 | atmel,pins = |
| 152 | <1 15 0x2 0x0>; /* PB15 periph B */ | 155 | <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ |
| 153 | }; | 156 | }; |
| 154 | }; | 157 | }; |
| 155 | 158 | ||
| 156 | uart1 { | 159 | uart1 { |
| 157 | pinctrl_usart1: usart1-0 { | 160 | pinctrl_usart1: usart1-0 { |
| 158 | atmel,pins = | 161 | atmel,pins = |
| 159 | <1 4 0x1 0x1 /* PB4 periph A with pullup */ | 162 | <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ |
| 160 | 1 5 0x1 0x0>; /* PB5 periph A */ | 163 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ |
| 161 | }; | 164 | }; |
| 162 | 165 | ||
| 163 | pinctrl_usart1_rts: usart1_rts-0 { | 166 | pinctrl_usart1_rts: usart1_rts-0 { |
| 164 | atmel,pins = | 167 | atmel,pins = |
| 165 | <3 16 0x1 0x0>; /* PD16 periph A */ | 168 | <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ |
| 166 | }; | 169 | }; |
| 167 | 170 | ||
| 168 | pinctrl_usart1_cts: usart1_cts-0 { | 171 | pinctrl_usart1_cts: usart1_cts-0 { |
| 169 | atmel,pins = | 172 | atmel,pins = |
| 170 | <3 17 0x1 0x0>; /* PD17 periph A */ | 173 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ |
| 171 | }; | 174 | }; |
| 172 | }; | 175 | }; |
| 173 | 176 | ||
| 174 | usart2 { | 177 | usart2 { |
| 175 | pinctrl_usart2: usart2-0 { | 178 | pinctrl_usart2: usart2-0 { |
| 176 | atmel,pins = | 179 | atmel,pins = |
| 177 | <1 6 0x1 0x1 /* PB6 periph A with pullup */ | 180 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ |
| 178 | 1 7 0x1 0x0>; /* PB7 periph A */ | 181 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ |
| 179 | }; | 182 | }; |
| 180 | 183 | ||
| 181 | pinctrl_usart2_rts: usart2_rts-0 { | 184 | pinctrl_usart2_rts: usart2_rts-0 { |
| 182 | atmel,pins = | 185 | atmel,pins = |
| 183 | <2 9 0x2 0x0>; /* PC9 periph B */ | 186 | <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ |
| 184 | }; | 187 | }; |
| 185 | 188 | ||
| 186 | pinctrl_usart2_cts: usart2_cts-0 { | 189 | pinctrl_usart2_cts: usart2_cts-0 { |
| 187 | atmel,pins = | 190 | atmel,pins = |
| 188 | <2 11 0x2 0x0>; /* PC11 periph B */ | 191 | <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ |
| 189 | }; | 192 | }; |
| 190 | }; | 193 | }; |
| 191 | 194 | ||
| 192 | usart3 { | 195 | usart3 { |
| 193 | pinctrl_usart3: usart3-0 { | 196 | pinctrl_usart3: usart3-0 { |
| 194 | atmel,pins = | 197 | atmel,pins = |
| 195 | <1 8 0x1 0x1 /* PB9 periph A with pullup */ | 198 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ |
| 196 | 1 9 0x1 0x0>; /* PB8 periph A */ | 199 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ |
| 197 | }; | 200 | }; |
| 198 | 201 | ||
| 199 | pinctrl_usart3_rts: usart3_rts-0 { | 202 | pinctrl_usart3_rts: usart3_rts-0 { |
| 200 | atmel,pins = | 203 | atmel,pins = |
| 201 | <0 23 0x2 0x0>; /* PA23 periph B */ | 204 | <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ |
| 202 | }; | 205 | }; |
| 203 | 206 | ||
| 204 | pinctrl_usart3_cts: usart3_cts-0 { | 207 | pinctrl_usart3_cts: usart3_cts-0 { |
| 205 | atmel,pins = | 208 | atmel,pins = |
| 206 | <0 24 0x2 0x0>; /* PA24 periph B */ | 209 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ |
| 207 | }; | 210 | }; |
| 208 | }; | 211 | }; |
| 209 | 212 | ||
| 210 | nand { | 213 | nand { |
| 211 | pinctrl_nand: nand-0 { | 214 | pinctrl_nand: nand-0 { |
| 212 | atmel,pins = | 215 | atmel,pins = |
| 213 | <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/ | 216 | <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/ |
| 214 | 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ | 217 | AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ |
| 215 | }; | 218 | }; |
| 216 | }; | 219 | }; |
| 217 | 220 | ||
| 218 | macb { | 221 | macb { |
| 219 | pinctrl_macb_rmii: macb_rmii-0 { | 222 | pinctrl_macb_rmii: macb_rmii-0 { |
| 220 | atmel,pins = | 223 | atmel,pins = |
| 221 | <0 10 0x1 0x0 /* PA10 periph A */ | 224 | <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ |
| 222 | 0 11 0x1 0x0 /* PA11 periph A */ | 225 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ |
| 223 | 0 12 0x1 0x0 /* PA12 periph A */ | 226 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ |
| 224 | 0 13 0x1 0x0 /* PA13 periph A */ | 227 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ |
| 225 | 0 14 0x1 0x0 /* PA14 periph A */ | 228 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ |
| 226 | 0 15 0x1 0x0 /* PA15 periph A */ | 229 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ |
| 227 | 0 16 0x1 0x0 /* PA16 periph A */ | 230 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ |
| 228 | 0 17 0x1 0x0 /* PA17 periph A */ | 231 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 229 | 0 18 0x1 0x0 /* PA18 periph A */ | 232 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ |
| 230 | 0 19 0x1 0x0>; /* PA19 periph A */ | 233 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ |
| 231 | }; | 234 | }; |
| 232 | 235 | ||
| 233 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | 236 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 234 | atmel,pins = | 237 | atmel,pins = |
| 235 | <0 6 0x2 0x0 /* PA6 periph B */ | 238 | <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ |
| 236 | 0 7 0x2 0x0 /* PA7 periph B */ | 239 | AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ |
| 237 | 0 8 0x2 0x0 /* PA8 periph B */ | 240 | AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ |
| 238 | 0 9 0x2 0x0 /* PA9 periph B */ | 241 | AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ |
| 239 | 0 27 0x2 0x0 /* PA27 periph B */ | 242 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 240 | 0 28 0x2 0x0 /* PA28 periph B */ | 243 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 241 | 0 29 0x2 0x0 /* PA29 periph B */ | 244 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ |
| 242 | 0 30 0x2 0x0>; /* PA30 periph B */ | 245 | AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
| 243 | }; | 246 | }; |
| 244 | }; | 247 | }; |
| 245 | 248 | ||
| 246 | mmc0 { | 249 | mmc0 { |
| 247 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | 250 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 248 | atmel,pins = | 251 | atmel,pins = |
| 249 | <0 0 0x1 0x0 /* PA0 periph A */ | 252 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ |
| 250 | 0 1 0x1 0x1 /* PA1 periph A with pullup */ | 253 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 251 | 0 2 0x1 0x1>; /* PA2 periph A with pullup */ | 254 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ |
| 252 | }; | 255 | }; |
| 253 | 256 | ||
| 254 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 257 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 255 | atmel,pins = | 258 | atmel,pins = |
| 256 | <0 3 0x1 0x1 /* PA3 periph A with pullup */ | 259 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ |
| 257 | 0 4 0x1 0x1 /* PA4 periph A with pullup */ | 260 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ |
| 258 | 0 5 0x1 0x1>; /* PA5 periph A with pullup */ | 261 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ |
| 259 | }; | 262 | }; |
| 260 | 263 | ||
| 261 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { | 264 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 262 | atmel,pins = | 265 | atmel,pins = |
| 263 | <0 6 0x1 0x1 /* PA6 periph A with pullup */ | 266 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 264 | 0 7 0x1 0x1 /* PA7 periph A with pullup */ | 267 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 265 | 0 8 0x1 0x1 /* PA8 periph A with pullup */ | 268 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 266 | 0 9 0x1 0x1>; /* PA9 periph A with pullup */ | 269 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ |
| 267 | }; | 270 | }; |
| 268 | }; | 271 | }; |
| 269 | 272 | ||
| 270 | mmc1 { | 273 | mmc1 { |
| 271 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | 274 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 272 | atmel,pins = | 275 | atmel,pins = |
| 273 | <0 31 0x1 0x0 /* PA31 periph A */ | 276 | <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ |
| 274 | 0 22 0x1 0x1 /* PA22 periph A with pullup */ | 277 | AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ |
| 275 | 0 23 0x1 0x1>; /* PA23 periph A with pullup */ | 278 | AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ |
| 276 | }; | 279 | }; |
| 277 | 280 | ||
| 278 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | 281 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 279 | atmel,pins = | 282 | atmel,pins = |
| 280 | <0 24 0x1 0x1 /* PA24 periph A with pullup */ | 283 | <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ |
| 281 | 0 25 0x1 0x1 /* PA25 periph A with pullup */ | 284 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ |
| 282 | 0 26 0x1 0x1>; /* PA26 periph A with pullup */ | 285 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ |
| 283 | }; | 286 | }; |
| 284 | 287 | ||
| 285 | pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { | 288 | pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { |
| 286 | atmel,pins = | 289 | atmel,pins = |
| 287 | <0 27 0x1 0x1 /* PA27 periph A with pullup */ | 290 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ |
| 288 | 0 28 0x1 0x1 /* PA28 periph A with pullup */ | 291 | AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ |
| 289 | 0 29 0x1 0x1 /* PA29 periph A with pullup */ | 292 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ |
| 290 | 0 20 0x1 0x1>; /* PA30 periph A with pullup */ | 293 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ |
| 291 | }; | 294 | }; |
| 292 | }; | 295 | }; |
| 293 | 296 | ||
| 294 | ssc0 { | 297 | ssc0 { |
| 295 | pinctrl_ssc0_tx: ssc0_tx-0 { | 298 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 296 | atmel,pins = | 299 | atmel,pins = |
| 297 | <3 0 0x1 0x0 /* PD0 periph A */ | 300 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ |
| 298 | 3 1 0x1 0x0 /* PD1 periph A */ | 301 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ |
| 299 | 3 2 0x1 0x0>; /* PD2 periph A */ | 302 | AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ |
| 300 | }; | 303 | }; |
| 301 | 304 | ||
| 302 | pinctrl_ssc0_rx: ssc0_rx-0 { | 305 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 303 | atmel,pins = | 306 | atmel,pins = |
| 304 | <3 3 0x1 0x0 /* PD3 periph A */ | 307 | <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ |
| 305 | 3 4 0x1 0x0 /* PD4 periph A */ | 308 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ |
| 306 | 3 5 0x1 0x0>; /* PD5 periph A */ | 309 | AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ |
| 307 | }; | 310 | }; |
| 308 | }; | 311 | }; |
| 309 | 312 | ||
| 310 | ssc1 { | 313 | ssc1 { |
| 311 | pinctrl_ssc1_tx: ssc1_tx-0 { | 314 | pinctrl_ssc1_tx: ssc1_tx-0 { |
| 312 | atmel,pins = | 315 | atmel,pins = |
| 313 | <3 10 0x1 0x0 /* PD10 periph A */ | 316 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ |
| 314 | 3 11 0x1 0x0 /* PD11 periph A */ | 317 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ |
| 315 | 3 12 0x1 0x0>; /* PD12 periph A */ | 318 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ |
| 316 | }; | 319 | }; |
| 317 | 320 | ||
| 318 | pinctrl_ssc1_rx: ssc1_rx-0 { | 321 | pinctrl_ssc1_rx: ssc1_rx-0 { |
| 319 | atmel,pins = | 322 | atmel,pins = |
| 320 | <3 13 0x1 0x0 /* PD13 periph A */ | 323 | <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ |
| 321 | 3 14 0x1 0x0 /* PD14 periph A */ | 324 | AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ |
| 322 | 3 15 0x1 0x0>; /* PD15 periph A */ | 325 | AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ |
| 323 | }; | 326 | }; |
| 324 | }; | 327 | }; |
| 325 | 328 | ||
| 326 | spi0 { | 329 | spi0 { |
| 327 | pinctrl_spi0: spi0-0 { | 330 | pinctrl_spi0: spi0-0 { |
| 328 | atmel,pins = | 331 | atmel,pins = |
| 329 | <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */ | 332 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ |
| 330 | 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */ | 333 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ |
| 331 | 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */ | 334 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ |
| 332 | }; | 335 | }; |
| 333 | }; | 336 | }; |
| 334 | 337 | ||
| 335 | spi1 { | 338 | spi1 { |
| 336 | pinctrl_spi1: spi1-0 { | 339 | pinctrl_spi1: spi1-0 { |
| 337 | atmel,pins = | 340 | atmel,pins = |
| 338 | <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */ | 341 | <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ |
| 339 | 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */ | 342 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ |
| 340 | 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */ | 343 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ |
| 341 | }; | 344 | }; |
| 342 | }; | 345 | }; |
| 343 | 346 | ||
| 344 | pioA: gpio@fffff200 { | 347 | pioA: gpio@fffff200 { |
| 345 | compatible = "atmel,at91rm9200-gpio"; | 348 | compatible = "atmel,at91rm9200-gpio"; |
| 346 | reg = <0xfffff200 0x200>; | 349 | reg = <0xfffff200 0x200>; |
| 347 | interrupts = <2 4 1>; | 350 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 348 | #gpio-cells = <2>; | 351 | #gpio-cells = <2>; |
| 349 | gpio-controller; | 352 | gpio-controller; |
| 350 | interrupt-controller; | 353 | interrupt-controller; |
| @@ -354,7 +357,7 @@ | |||
| 354 | pioB: gpio@fffff400 { | 357 | pioB: gpio@fffff400 { |
| 355 | compatible = "atmel,at91rm9200-gpio"; | 358 | compatible = "atmel,at91rm9200-gpio"; |
| 356 | reg = <0xfffff400 0x200>; | 359 | reg = <0xfffff400 0x200>; |
| 357 | interrupts = <3 4 1>; | 360 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 358 | #gpio-cells = <2>; | 361 | #gpio-cells = <2>; |
| 359 | gpio-controller; | 362 | gpio-controller; |
| 360 | interrupt-controller; | 363 | interrupt-controller; |
| @@ -364,7 +367,7 @@ | |||
| 364 | pioC: gpio@fffff600 { | 367 | pioC: gpio@fffff600 { |
| 365 | compatible = "atmel,at91rm9200-gpio"; | 368 | compatible = "atmel,at91rm9200-gpio"; |
| 366 | reg = <0xfffff600 0x200>; | 369 | reg = <0xfffff600 0x200>; |
| 367 | interrupts = <4 4 1>; | 370 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| 368 | #gpio-cells = <2>; | 371 | #gpio-cells = <2>; |
| 369 | gpio-controller; | 372 | gpio-controller; |
| 370 | interrupt-controller; | 373 | interrupt-controller; |
| @@ -374,7 +377,7 @@ | |||
| 374 | pioD: gpio@fffff800 { | 377 | pioD: gpio@fffff800 { |
| 375 | compatible = "atmel,at91rm9200-gpio"; | 378 | compatible = "atmel,at91rm9200-gpio"; |
| 376 | reg = <0xfffff800 0x200>; | 379 | reg = <0xfffff800 0x200>; |
| 377 | interrupts = <5 4 1>; | 380 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
| 378 | #gpio-cells = <2>; | 381 | #gpio-cells = <2>; |
| 379 | gpio-controller; | 382 | gpio-controller; |
| 380 | interrupt-controller; | 383 | interrupt-controller; |
| @@ -384,7 +387,7 @@ | |||
| 384 | pioE: gpio@fffffa00 { | 387 | pioE: gpio@fffffa00 { |
| 385 | compatible = "atmel,at91rm9200-gpio"; | 388 | compatible = "atmel,at91rm9200-gpio"; |
| 386 | reg = <0xfffffa00 0x200>; | 389 | reg = <0xfffffa00 0x200>; |
| 387 | interrupts = <5 4 1>; | 390 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
| 388 | #gpio-cells = <2>; | 391 | #gpio-cells = <2>; |
| 389 | gpio-controller; | 392 | gpio-controller; |
| 390 | interrupt-controller; | 393 | interrupt-controller; |
| @@ -395,7 +398,7 @@ | |||
| 395 | dbgu: serial@ffffee00 { | 398 | dbgu: serial@ffffee00 { |
| 396 | compatible = "atmel,at91sam9260-usart"; | 399 | compatible = "atmel,at91sam9260-usart"; |
| 397 | reg = <0xffffee00 0x200>; | 400 | reg = <0xffffee00 0x200>; |
| 398 | interrupts = <1 4 7>; | 401 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 399 | pinctrl-names = "default"; | 402 | pinctrl-names = "default"; |
| 400 | pinctrl-0 = <&pinctrl_dbgu>; | 403 | pinctrl-0 = <&pinctrl_dbgu>; |
| 401 | status = "disabled"; | 404 | status = "disabled"; |
| @@ -404,7 +407,7 @@ | |||
| 404 | usart0: serial@fff8c000 { | 407 | usart0: serial@fff8c000 { |
| 405 | compatible = "atmel,at91sam9260-usart"; | 408 | compatible = "atmel,at91sam9260-usart"; |
| 406 | reg = <0xfff8c000 0x200>; | 409 | reg = <0xfff8c000 0x200>; |
| 407 | interrupts = <7 4 5>; | 410 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 408 | atmel,use-dma-rx; | 411 | atmel,use-dma-rx; |
| 409 | atmel,use-dma-tx; | 412 | atmel,use-dma-tx; |
| 410 | pinctrl-names = "default"; | 413 | pinctrl-names = "default"; |
| @@ -415,7 +418,7 @@ | |||
| 415 | usart1: serial@fff90000 { | 418 | usart1: serial@fff90000 { |
| 416 | compatible = "atmel,at91sam9260-usart"; | 419 | compatible = "atmel,at91sam9260-usart"; |
| 417 | reg = <0xfff90000 0x200>; | 420 | reg = <0xfff90000 0x200>; |
| 418 | interrupts = <8 4 5>; | 421 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 419 | atmel,use-dma-rx; | 422 | atmel,use-dma-rx; |
| 420 | atmel,use-dma-tx; | 423 | atmel,use-dma-tx; |
| 421 | pinctrl-names = "default"; | 424 | pinctrl-names = "default"; |
| @@ -426,7 +429,7 @@ | |||
| 426 | usart2: serial@fff94000 { | 429 | usart2: serial@fff94000 { |
| 427 | compatible = "atmel,at91sam9260-usart"; | 430 | compatible = "atmel,at91sam9260-usart"; |
| 428 | reg = <0xfff94000 0x200>; | 431 | reg = <0xfff94000 0x200>; |
| 429 | interrupts = <9 4 5>; | 432 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; |
| 430 | atmel,use-dma-rx; | 433 | atmel,use-dma-rx; |
| 431 | atmel,use-dma-tx; | 434 | atmel,use-dma-tx; |
| 432 | pinctrl-names = "default"; | 435 | pinctrl-names = "default"; |
| @@ -437,7 +440,7 @@ | |||
| 437 | usart3: serial@fff98000 { | 440 | usart3: serial@fff98000 { |
| 438 | compatible = "atmel,at91sam9260-usart"; | 441 | compatible = "atmel,at91sam9260-usart"; |
| 439 | reg = <0xfff98000 0x200>; | 442 | reg = <0xfff98000 0x200>; |
| 440 | interrupts = <10 4 5>; | 443 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; |
| 441 | atmel,use-dma-rx; | 444 | atmel,use-dma-rx; |
| 442 | atmel,use-dma-tx; | 445 | atmel,use-dma-tx; |
| 443 | pinctrl-names = "default"; | 446 | pinctrl-names = "default"; |
| @@ -448,7 +451,7 @@ | |||
| 448 | macb0: ethernet@fffbc000 { | 451 | macb0: ethernet@fffbc000 { |
| 449 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 452 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 450 | reg = <0xfffbc000 0x100>; | 453 | reg = <0xfffbc000 0x100>; |
| 451 | interrupts = <25 4 3>; | 454 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
| 452 | pinctrl-names = "default"; | 455 | pinctrl-names = "default"; |
| 453 | pinctrl-0 = <&pinctrl_macb_rmii>; | 456 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 454 | status = "disabled"; | 457 | status = "disabled"; |
| @@ -457,7 +460,7 @@ | |||
| 457 | i2c0: i2c@fff84000 { | 460 | i2c0: i2c@fff84000 { |
| 458 | compatible = "atmel,at91sam9g10-i2c"; | 461 | compatible = "atmel,at91sam9g10-i2c"; |
| 459 | reg = <0xfff84000 0x100>; | 462 | reg = <0xfff84000 0x100>; |
| 460 | interrupts = <12 4 6>; | 463 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
| 461 | #address-cells = <1>; | 464 | #address-cells = <1>; |
| 462 | #size-cells = <0>; | 465 | #size-cells = <0>; |
| 463 | status = "disabled"; | 466 | status = "disabled"; |
| @@ -466,7 +469,7 @@ | |||
| 466 | i2c1: i2c@fff88000 { | 469 | i2c1: i2c@fff88000 { |
| 467 | compatible = "atmel,at91sam9g10-i2c"; | 470 | compatible = "atmel,at91sam9g10-i2c"; |
| 468 | reg = <0xfff88000 0x100>; | 471 | reg = <0xfff88000 0x100>; |
| 469 | interrupts = <13 4 6>; | 472 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
| 470 | #address-cells = <1>; | 473 | #address-cells = <1>; |
| 471 | #size-cells = <0>; | 474 | #size-cells = <0>; |
| 472 | status = "disabled"; | 475 | status = "disabled"; |
| @@ -475,7 +478,7 @@ | |||
| 475 | ssc0: ssc@fff9c000 { | 478 | ssc0: ssc@fff9c000 { |
| 476 | compatible = "atmel,at91sam9g45-ssc"; | 479 | compatible = "atmel,at91sam9g45-ssc"; |
| 477 | reg = <0xfff9c000 0x4000>; | 480 | reg = <0xfff9c000 0x4000>; |
| 478 | interrupts = <16 4 5>; | 481 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 479 | pinctrl-names = "default"; | 482 | pinctrl-names = "default"; |
| 480 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 483 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 481 | status = "disabled"; | 484 | status = "disabled"; |
| @@ -484,7 +487,7 @@ | |||
| 484 | ssc1: ssc@fffa0000 { | 487 | ssc1: ssc@fffa0000 { |
| 485 | compatible = "atmel,at91sam9g45-ssc"; | 488 | compatible = "atmel,at91sam9g45-ssc"; |
| 486 | reg = <0xfffa0000 0x4000>; | 489 | reg = <0xfffa0000 0x4000>; |
| 487 | interrupts = <17 4 5>; | 490 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
| 488 | pinctrl-names = "default"; | 491 | pinctrl-names = "default"; |
| 489 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 492 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 490 | status = "disabled"; | 493 | status = "disabled"; |
| @@ -493,7 +496,7 @@ | |||
| 493 | adc0: adc@fffb0000 { | 496 | adc0: adc@fffb0000 { |
| 494 | compatible = "atmel,at91sam9260-adc"; | 497 | compatible = "atmel,at91sam9260-adc"; |
| 495 | reg = <0xfffb0000 0x100>; | 498 | reg = <0xfffb0000 0x100>; |
| 496 | interrupts = <20 4 0>; | 499 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 497 | atmel,adc-use-external-triggers; | 500 | atmel,adc-use-external-triggers; |
| 498 | atmel,adc-channels-used = <0xff>; | 501 | atmel,adc-channels-used = <0xff>; |
| 499 | atmel,adc-vref = <3300>; | 502 | atmel,adc-vref = <3300>; |
| @@ -533,7 +536,7 @@ | |||
| 533 | mmc0: mmc@fff80000 { | 536 | mmc0: mmc@fff80000 { |
| 534 | compatible = "atmel,hsmci"; | 537 | compatible = "atmel,hsmci"; |
| 535 | reg = <0xfff80000 0x600>; | 538 | reg = <0xfff80000 0x600>; |
| 536 | interrupts = <11 4 0>; | 539 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
| 537 | dmas = <&dma 1 0>; | 540 | dmas = <&dma 1 0>; |
| 538 | dma-names = "rxtx"; | 541 | dma-names = "rxtx"; |
| 539 | #address-cells = <1>; | 542 | #address-cells = <1>; |
| @@ -544,7 +547,7 @@ | |||
| 544 | mmc1: mmc@fffd0000 { | 547 | mmc1: mmc@fffd0000 { |
| 545 | compatible = "atmel,hsmci"; | 548 | compatible = "atmel,hsmci"; |
| 546 | reg = <0xfffd0000 0x600>; | 549 | reg = <0xfffd0000 0x600>; |
| 547 | interrupts = <29 4 0>; | 550 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; |
| 548 | dmas = <&dma 1 13>; | 551 | dmas = <&dma 1 13>; |
| 549 | dma-names = "rxtx"; | 552 | dma-names = "rxtx"; |
| 550 | #address-cells = <1>; | 553 | #address-cells = <1>; |
| @@ -592,8 +595,8 @@ | |||
| 592 | atmel,nand-cmd-offset = <22>; | 595 | atmel,nand-cmd-offset = <22>; |
| 593 | pinctrl-names = "default"; | 596 | pinctrl-names = "default"; |
| 594 | pinctrl-0 = <&pinctrl_nand>; | 597 | pinctrl-0 = <&pinctrl_nand>; |
| 595 | gpios = <&pioC 8 0 | 598 | gpios = <&pioC 8 GPIO_ACTIVE_HIGH |
| 596 | &pioC 14 0 | 599 | &pioC 14 GPIO_ACTIVE_HIGH |
| 597 | 0 | 600 | 0 |
| 598 | >; | 601 | >; |
| 599 | status = "disabled"; | 602 | status = "disabled"; |
| @@ -602,22 +605,22 @@ | |||
| 602 | usb0: ohci@00700000 { | 605 | usb0: ohci@00700000 { |
| 603 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 606 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 604 | reg = <0x00700000 0x100000>; | 607 | reg = <0x00700000 0x100000>; |
| 605 | interrupts = <22 4 2>; | 608 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 606 | status = "disabled"; | 609 | status = "disabled"; |
| 607 | }; | 610 | }; |
| 608 | 611 | ||
| 609 | usb1: ehci@00800000 { | 612 | usb1: ehci@00800000 { |
| 610 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 613 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 611 | reg = <0x00800000 0x100000>; | 614 | reg = <0x00800000 0x100000>; |
| 612 | interrupts = <22 4 2>; | 615 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 613 | status = "disabled"; | 616 | status = "disabled"; |
| 614 | }; | 617 | }; |
| 615 | }; | 618 | }; |
| 616 | 619 | ||
| 617 | i2c@0 { | 620 | i2c@0 { |
| 618 | compatible = "i2c-gpio"; | 621 | compatible = "i2c-gpio"; |
| 619 | gpios = <&pioA 20 0 /* sda */ | 622 | gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ |
| 620 | &pioA 21 0 /* scl */ | 623 | &pioA 21 GPIO_ACTIVE_HIGH /* scl */ |
| 621 | >; | 624 | >; |
| 622 | i2c-gpio,sda-open-drain; | 625 | i2c-gpio,sda-open-drain; |
| 623 | i2c-gpio,scl-open-drain; | 626 | i2c-gpio,scl-open-drain; |
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 51d9251b5bbe..89c50d108d44 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9g45.dtsi" | 10 | #include "at91sam9g45.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Atmel AT91SAM9M10G45-EK"; | 13 | model = "Atmel AT91SAM9M10G45-EK"; |
| @@ -68,7 +68,7 @@ | |||
| 68 | slot@0 { | 68 | slot@0 { |
| 69 | reg = <0>; | 69 | reg = <0>; |
| 70 | bus-width = <4>; | 70 | bus-width = <4>; |
| 71 | cd-gpios = <&pioD 10 0>; | 71 | cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; |
| 72 | }; | 72 | }; |
| 73 | }; | 73 | }; |
| 74 | 74 | ||
| @@ -81,8 +81,8 @@ | |||
| 81 | slot@0 { | 81 | slot@0 { |
| 82 | reg = <0>; | 82 | reg = <0>; |
| 83 | bus-width = <4>; | 83 | bus-width = <4>; |
| 84 | cd-gpios = <&pioD 11 0>; | 84 | cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; |
| 85 | wp-gpios = <&pioD 29 0>; | 85 | wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; |
| 86 | }; | 86 | }; |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| @@ -90,15 +90,15 @@ | |||
| 90 | mmc0 { | 90 | mmc0 { |
| 91 | pinctrl_board_mmc0: mmc0-board { | 91 | pinctrl_board_mmc0: mmc0-board { |
| 92 | atmel,pins = | 92 | atmel,pins = |
| 93 | <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */ | 93 | <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */ |
| 94 | }; | 94 | }; |
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | mmc1 { | 97 | mmc1 { |
| 98 | pinctrl_board_mmc1: mmc1-board { | 98 | pinctrl_board_mmc1: mmc1-board { |
| 99 | atmel,pins = | 99 | atmel,pins = |
| 100 | <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */ | 100 | <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */ |
| 101 | 3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */ | 101 | AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ |
| 102 | }; | 102 | }; |
| 103 | }; | 103 | }; |
| 104 | }; | 104 | }; |
| @@ -139,8 +139,8 @@ | |||
| 139 | usb0: ohci@00700000 { | 139 | usb0: ohci@00700000 { |
| 140 | status = "okay"; | 140 | status = "okay"; |
| 141 | num-ports = <2>; | 141 | num-ports = <2>; |
| 142 | atmel,vbus-gpio = <&pioD 1 1 | 142 | atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW |
| 143 | &pioD 3 1>; | 143 | &pioD 3 GPIO_ACTIVE_LOW>; |
| 144 | }; | 144 | }; |
| 145 | 145 | ||
| 146 | usb1: ehci@00800000 { | 146 | usb1: ehci@00800000 { |
| @@ -153,19 +153,19 @@ | |||
| 153 | 153 | ||
| 154 | d8 { | 154 | d8 { |
| 155 | label = "d8"; | 155 | label = "d8"; |
| 156 | gpios = <&pioD 30 0>; | 156 | gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; |
| 157 | linux,default-trigger = "heartbeat"; | 157 | linux,default-trigger = "heartbeat"; |
| 158 | }; | 158 | }; |
| 159 | 159 | ||
| 160 | d6 { | 160 | d6 { |
| 161 | label = "d6"; | 161 | label = "d6"; |
| 162 | gpios = <&pioD 0 1>; | 162 | gpios = <&pioD 0 GPIO_ACTIVE_LOW>; |
| 163 | linux,default-trigger = "nand-disk"; | 163 | linux,default-trigger = "nand-disk"; |
| 164 | }; | 164 | }; |
| 165 | 165 | ||
| 166 | d7 { | 166 | d7 { |
| 167 | label = "d7"; | 167 | label = "d7"; |
| 168 | gpios = <&pioD 31 1>; | 168 | gpios = <&pioD 31 GPIO_ACTIVE_LOW>; |
| 169 | linux,default-trigger = "mmc0"; | 169 | linux,default-trigger = "mmc0"; |
| 170 | }; | 170 | }; |
| 171 | }; | 171 | }; |
| @@ -175,45 +175,45 @@ | |||
| 175 | 175 | ||
| 176 | left_click { | 176 | left_click { |
| 177 | label = "left_click"; | 177 | label = "left_click"; |
| 178 | gpios = <&pioB 6 1>; | 178 | gpios = <&pioB 6 GPIO_ACTIVE_LOW>; |
| 179 | linux,code = <272>; | 179 | linux,code = <272>; |
| 180 | gpio-key,wakeup; | 180 | gpio-key,wakeup; |
| 181 | }; | 181 | }; |
| 182 | 182 | ||
| 183 | right_click { | 183 | right_click { |
| 184 | label = "right_click"; | 184 | label = "right_click"; |
| 185 | gpios = <&pioB 7 1>; | 185 | gpios = <&pioB 7 GPIO_ACTIVE_LOW>; |
| 186 | linux,code = <273>; | 186 | linux,code = <273>; |
| 187 | gpio-key,wakeup; | 187 | gpio-key,wakeup; |
| 188 | }; | 188 | }; |
| 189 | 189 | ||
| 190 | left { | 190 | left { |
| 191 | label = "Joystick Left"; | 191 | label = "Joystick Left"; |
| 192 | gpios = <&pioB 14 1>; | 192 | gpios = <&pioB 14 GPIO_ACTIVE_LOW>; |
| 193 | linux,code = <105>; | 193 | linux,code = <105>; |
| 194 | }; | 194 | }; |
| 195 | 195 | ||
| 196 | right { | 196 | right { |
| 197 | label = "Joystick Right"; | 197 | label = "Joystick Right"; |
| 198 | gpios = <&pioB 15 1>; | 198 | gpios = <&pioB 15 GPIO_ACTIVE_LOW>; |
| 199 | linux,code = <106>; | 199 | linux,code = <106>; |
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | up { | 202 | up { |
| 203 | label = "Joystick Up"; | 203 | label = "Joystick Up"; |
| 204 | gpios = <&pioB 16 1>; | 204 | gpios = <&pioB 16 GPIO_ACTIVE_LOW>; |
| 205 | linux,code = <103>; | 205 | linux,code = <103>; |
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | down { | 208 | down { |
| 209 | label = "Joystick Down"; | 209 | label = "Joystick Down"; |
| 210 | gpios = <&pioB 17 1>; | 210 | gpios = <&pioB 17 GPIO_ACTIVE_LOW>; |
| 211 | linux,code = <108>; | 211 | linux,code = <108>; |
| 212 | }; | 212 | }; |
| 213 | 213 | ||
| 214 | enter { | 214 | enter { |
| 215 | label = "Joystick Press"; | 215 | label = "Joystick Press"; |
| 216 | gpios = <&pioB 18 1>; | 216 | gpios = <&pioB 18 GPIO_ACTIVE_LOW>; |
| 217 | linux,code = <28>; | 217 | linux,code = <28>; |
| 218 | }; | 218 | }; |
| 219 | }; | 219 | }; |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 8d25f889928e..d864f7a9d2e0 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -7,7 +7,10 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | /include/ "skeleton.dtsi" | 10 | #include "skeleton.dtsi" |
| 11 | #include <dt-bindings/pinctrl/at91.h> | ||
| 12 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 11 | 14 | ||
| 12 | / { | 15 | / { |
| 13 | model = "Atmel AT91SAM9N12 SoC"; | 16 | model = "Atmel AT91SAM9N12 SoC"; |
| @@ -78,7 +81,7 @@ | |||
| 78 | pit: timer@fffffe30 { | 81 | pit: timer@fffffe30 { |
| 79 | compatible = "atmel,at91sam9260-pit"; | 82 | compatible = "atmel,at91sam9260-pit"; |
| 80 | reg = <0xfffffe30 0xf>; | 83 | reg = <0xfffffe30 0xf>; |
| 81 | interrupts = <1 4 7>; | 84 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 82 | }; | 85 | }; |
| 83 | 86 | ||
| 84 | shdwc@fffffe10 { | 87 | shdwc@fffffe10 { |
| @@ -89,7 +92,7 @@ | |||
| 89 | mmc0: mmc@f0008000 { | 92 | mmc0: mmc@f0008000 { |
| 90 | compatible = "atmel,hsmci"; | 93 | compatible = "atmel,hsmci"; |
| 91 | reg = <0xf0008000 0x600>; | 94 | reg = <0xf0008000 0x600>; |
| 92 | interrupts = <12 4 0>; | 95 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| 93 | dmas = <&dma 1 0>; | 96 | dmas = <&dma 1 0>; |
| 94 | dma-names = "rxtx"; | 97 | dma-names = "rxtx"; |
| 95 | #address-cells = <1>; | 98 | #address-cells = <1>; |
| @@ -100,19 +103,19 @@ | |||
| 100 | tcb0: timer@f8008000 { | 103 | tcb0: timer@f8008000 { |
| 101 | compatible = "atmel,at91sam9x5-tcb"; | 104 | compatible = "atmel,at91sam9x5-tcb"; |
| 102 | reg = <0xf8008000 0x100>; | 105 | reg = <0xf8008000 0x100>; |
| 103 | interrupts = <17 4 0>; | 106 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 104 | }; | 107 | }; |
| 105 | 108 | ||
| 106 | tcb1: timer@f800c000 { | 109 | tcb1: timer@f800c000 { |
| 107 | compatible = "atmel,at91sam9x5-tcb"; | 110 | compatible = "atmel,at91sam9x5-tcb"; |
| 108 | reg = <0xf800c000 0x100>; | 111 | reg = <0xf800c000 0x100>; |
| 109 | interrupts = <17 4 0>; | 112 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 110 | }; | 113 | }; |
| 111 | 114 | ||
| 112 | dma: dma-controller@ffffec00 { | 115 | dma: dma-controller@ffffec00 { |
| 113 | compatible = "atmel,at91sam9g45-dma"; | 116 | compatible = "atmel,at91sam9g45-dma"; |
| 114 | reg = <0xffffec00 0x200>; | 117 | reg = <0xffffec00 0x200>; |
| 115 | interrupts = <20 4 0>; | 118 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 116 | #dma-cells = <2>; | 119 | #dma-cells = <2>; |
| 117 | }; | 120 | }; |
| 118 | 121 | ||
| @@ -134,159 +137,159 @@ | |||
| 134 | dbgu { | 137 | dbgu { |
| 135 | pinctrl_dbgu: dbgu-0 { | 138 | pinctrl_dbgu: dbgu-0 { |
| 136 | atmel,pins = | 139 | atmel,pins = |
| 137 | <0 9 0x1 0x0 /* PA9 periph A */ | 140 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 138 | 0 10 0x1 0x1>; /* PA10 periph with pullup */ | 141 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ |
| 139 | }; | 142 | }; |
| 140 | }; | 143 | }; |
| 141 | 144 | ||
| 142 | usart0 { | 145 | usart0 { |
| 143 | pinctrl_usart0: usart0-0 { | 146 | pinctrl_usart0: usart0-0 { |
| 144 | atmel,pins = | 147 | atmel,pins = |
| 145 | <0 1 0x1 0x1 /* PA1 periph A with pullup */ | 148 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 146 | 0 0 0x1 0x0>; /* PA0 periph A */ | 149 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ |
| 147 | }; | 150 | }; |
| 148 | 151 | ||
| 149 | pinctrl_usart0_rts: usart0_rts-0 { | 152 | pinctrl_usart0_rts: usart0_rts-0 { |
| 150 | atmel,pins = | 153 | atmel,pins = |
| 151 | <0 2 0x1 0x0>; /* PA2 periph A */ | 154 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
| 152 | }; | 155 | }; |
| 153 | 156 | ||
| 154 | pinctrl_usart0_cts: usart0_cts-0 { | 157 | pinctrl_usart0_cts: usart0_cts-0 { |
| 155 | atmel,pins = | 158 | atmel,pins = |
| 156 | <0 3 0x1 0x0>; /* PA3 periph A */ | 159 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
| 157 | }; | 160 | }; |
| 158 | }; | 161 | }; |
| 159 | 162 | ||
| 160 | usart1 { | 163 | usart1 { |
| 161 | pinctrl_usart1: usart1-0 { | 164 | pinctrl_usart1: usart1-0 { |
| 162 | atmel,pins = | 165 | atmel,pins = |
| 163 | <0 6 0x1 0x1 /* PA6 periph A with pullup */ | 166 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 164 | 0 5 0x1 0x0>; /* PA5 periph A */ | 167 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ |
| 165 | }; | 168 | }; |
| 166 | }; | 169 | }; |
| 167 | 170 | ||
| 168 | usart2 { | 171 | usart2 { |
| 169 | pinctrl_usart2: usart2-0 { | 172 | pinctrl_usart2: usart2-0 { |
| 170 | atmel,pins = | 173 | atmel,pins = |
| 171 | <0 8 0x1 0x1 /* PA8 periph A with pullup */ | 174 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 172 | 0 7 0x1 0x0>; /* PA7 periph A */ | 175 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ |
| 173 | }; | 176 | }; |
| 174 | 177 | ||
| 175 | pinctrl_usart2_rts: usart2_rts-0 { | 178 | pinctrl_usart2_rts: usart2_rts-0 { |
| 176 | atmel,pins = | 179 | atmel,pins = |
| 177 | <1 0 0x2 0x0>; /* PB0 periph B */ | 180 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
| 178 | }; | 181 | }; |
| 179 | 182 | ||
| 180 | pinctrl_usart2_cts: usart2_cts-0 { | 183 | pinctrl_usart2_cts: usart2_cts-0 { |
| 181 | atmel,pins = | 184 | atmel,pins = |
| 182 | <1 1 0x2 0x0>; /* PB1 periph B */ | 185 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
| 183 | }; | 186 | }; |
| 184 | }; | 187 | }; |
| 185 | 188 | ||
| 186 | usart3 { | 189 | usart3 { |
| 187 | pinctrl_usart3: usart3-0 { | 190 | pinctrl_usart3: usart3-0 { |
| 188 | atmel,pins = | 191 | atmel,pins = |
| 189 | <2 23 0x2 0x1 /* PC23 periph B with pullup */ | 192 | <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ |
| 190 | 2 22 0x2 0x0>; /* PC22 periph B */ | 193 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ |
| 191 | }; | 194 | }; |
| 192 | 195 | ||
| 193 | pinctrl_usart3_rts: usart3_rts-0 { | 196 | pinctrl_usart3_rts: usart3_rts-0 { |
| 194 | atmel,pins = | 197 | atmel,pins = |
| 195 | <2 24 0x2 0x0>; /* PC24 periph B */ | 198 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
| 196 | }; | 199 | }; |
| 197 | 200 | ||
| 198 | pinctrl_usart3_cts: usart3_cts-0 { | 201 | pinctrl_usart3_cts: usart3_cts-0 { |
| 199 | atmel,pins = | 202 | atmel,pins = |
| 200 | <2 25 0x2 0x0>; /* PC25 periph B */ | 203 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
| 201 | }; | 204 | }; |
| 202 | }; | 205 | }; |
| 203 | 206 | ||
| 204 | uart0 { | 207 | uart0 { |
| 205 | pinctrl_uart0: uart0-0 { | 208 | pinctrl_uart0: uart0-0 { |
| 206 | atmel,pins = | 209 | atmel,pins = |
| 207 | <2 9 0x3 0x1 /* PC9 periph C with pullup */ | 210 | <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ |
| 208 | 2 8 0x3 0x0>; /* PC8 periph C */ | 211 | AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ |
| 209 | }; | 212 | }; |
| 210 | }; | 213 | }; |
| 211 | 214 | ||
| 212 | uart1 { | 215 | uart1 { |
| 213 | pinctrl_uart1: uart1-0 { | 216 | pinctrl_uart1: uart1-0 { |
| 214 | atmel,pins = | 217 | atmel,pins = |
| 215 | <2 16 0x3 0x1 /* PC17 periph C with pullup */ | 218 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ |
| 216 | 2 17 0x3 0x0>; /* PC16 periph C */ | 219 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ |
| 217 | }; | 220 | }; |
| 218 | }; | 221 | }; |
| 219 | 222 | ||
| 220 | nand { | 223 | nand { |
| 221 | pinctrl_nand: nand-0 { | 224 | pinctrl_nand: nand-0 { |
| 222 | atmel,pins = | 225 | atmel,pins = |
| 223 | <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/ | 226 | <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ |
| 224 | 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */ | 227 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ |
| 225 | }; | 228 | }; |
| 226 | }; | 229 | }; |
| 227 | 230 | ||
| 228 | mmc0 { | 231 | mmc0 { |
| 229 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | 232 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 230 | atmel,pins = | 233 | atmel,pins = |
| 231 | <0 17 0x1 0x0 /* PA17 periph A */ | 234 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 232 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | 235 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 233 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | 236 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
| 234 | }; | 237 | }; |
| 235 | 238 | ||
| 236 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 239 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 237 | atmel,pins = | 240 | atmel,pins = |
| 238 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | 241 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 239 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | 242 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 240 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | 243 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
| 241 | }; | 244 | }; |
| 242 | 245 | ||
| 243 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { | 246 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 244 | atmel,pins = | 247 | atmel,pins = |
| 245 | <0 11 0x2 0x1 /* PA11 periph B with pullup */ | 248 | <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ |
| 246 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | 249 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| 247 | 0 13 0x2 0x1 /* PA13 periph B with pullup */ | 250 | AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ |
| 248 | 0 14 0x2 0x1>; /* PA14 periph B with pullup */ | 251 | AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ |
| 249 | }; | 252 | }; |
| 250 | }; | 253 | }; |
| 251 | 254 | ||
| 252 | ssc0 { | 255 | ssc0 { |
| 253 | pinctrl_ssc0_tx: ssc0_tx-0 { | 256 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 254 | atmel,pins = | 257 | atmel,pins = |
| 255 | <0 24 0x2 0x0 /* PA24 periph B */ | 258 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 256 | 0 25 0x2 0x0 /* PA25 periph B */ | 259 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 257 | 0 26 0x2 0x0>; /* PA26 periph B */ | 260 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
| 258 | }; | 261 | }; |
| 259 | 262 | ||
| 260 | pinctrl_ssc0_rx: ssc0_rx-0 { | 263 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 261 | atmel,pins = | 264 | atmel,pins = |
| 262 | <0 27 0x2 0x0 /* PA27 periph B */ | 265 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 263 | 0 28 0x2 0x0 /* PA28 periph B */ | 266 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 264 | 0 29 0x2 0x0>; /* PA29 periph B */ | 267 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
| 265 | }; | 268 | }; |
| 266 | }; | 269 | }; |
| 267 | 270 | ||
| 268 | spi0 { | 271 | spi0 { |
| 269 | pinctrl_spi0: spi0-0 { | 272 | pinctrl_spi0: spi0-0 { |
| 270 | atmel,pins = | 273 | atmel,pins = |
| 271 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | 274 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 272 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | 275 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| 273 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | 276 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
| 274 | }; | 277 | }; |
| 275 | }; | 278 | }; |
| 276 | 279 | ||
| 277 | spi1 { | 280 | spi1 { |
| 278 | pinctrl_spi1: spi1-0 { | 281 | pinctrl_spi1: spi1-0 { |
| 279 | atmel,pins = | 282 | atmel,pins = |
| 280 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | 283 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 281 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | 284 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| 282 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | 285 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
| 283 | }; | 286 | }; |
| 284 | }; | 287 | }; |
| 285 | 288 | ||
| 286 | pioA: gpio@fffff400 { | 289 | pioA: gpio@fffff400 { |
| 287 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 290 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 288 | reg = <0xfffff400 0x200>; | 291 | reg = <0xfffff400 0x200>; |
| 289 | interrupts = <2 4 1>; | 292 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 290 | #gpio-cells = <2>; | 293 | #gpio-cells = <2>; |
| 291 | gpio-controller; | 294 | gpio-controller; |
| 292 | interrupt-controller; | 295 | interrupt-controller; |
| @@ -296,7 +299,7 @@ | |||
| 296 | pioB: gpio@fffff600 { | 299 | pioB: gpio@fffff600 { |
| 297 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 300 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 298 | reg = <0xfffff600 0x200>; | 301 | reg = <0xfffff600 0x200>; |
| 299 | interrupts = <2 4 1>; | 302 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 300 | #gpio-cells = <2>; | 303 | #gpio-cells = <2>; |
| 301 | gpio-controller; | 304 | gpio-controller; |
| 302 | interrupt-controller; | 305 | interrupt-controller; |
| @@ -306,7 +309,7 @@ | |||
| 306 | pioC: gpio@fffff800 { | 309 | pioC: gpio@fffff800 { |
| 307 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 310 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 308 | reg = <0xfffff800 0x200>; | 311 | reg = <0xfffff800 0x200>; |
| 309 | interrupts = <3 4 1>; | 312 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 310 | #gpio-cells = <2>; | 313 | #gpio-cells = <2>; |
| 311 | gpio-controller; | 314 | gpio-controller; |
| 312 | interrupt-controller; | 315 | interrupt-controller; |
| @@ -316,7 +319,7 @@ | |||
| 316 | pioD: gpio@fffffa00 { | 319 | pioD: gpio@fffffa00 { |
| 317 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 320 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 318 | reg = <0xfffffa00 0x200>; | 321 | reg = <0xfffffa00 0x200>; |
| 319 | interrupts = <3 4 1>; | 322 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 320 | #gpio-cells = <2>; | 323 | #gpio-cells = <2>; |
| 321 | gpio-controller; | 324 | gpio-controller; |
| 322 | interrupt-controller; | 325 | interrupt-controller; |
| @@ -327,7 +330,7 @@ | |||
| 327 | dbgu: serial@fffff200 { | 330 | dbgu: serial@fffff200 { |
| 328 | compatible = "atmel,at91sam9260-usart"; | 331 | compatible = "atmel,at91sam9260-usart"; |
| 329 | reg = <0xfffff200 0x200>; | 332 | reg = <0xfffff200 0x200>; |
| 330 | interrupts = <1 4 7>; | 333 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 331 | pinctrl-names = "default"; | 334 | pinctrl-names = "default"; |
| 332 | pinctrl-0 = <&pinctrl_dbgu>; | 335 | pinctrl-0 = <&pinctrl_dbgu>; |
| 333 | status = "disabled"; | 336 | status = "disabled"; |
| @@ -336,7 +339,7 @@ | |||
| 336 | ssc0: ssc@f0010000 { | 339 | ssc0: ssc@f0010000 { |
| 337 | compatible = "atmel,at91sam9g45-ssc"; | 340 | compatible = "atmel,at91sam9g45-ssc"; |
| 338 | reg = <0xf0010000 0x4000>; | 341 | reg = <0xf0010000 0x4000>; |
| 339 | interrupts = <28 4 5>; | 342 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
| 340 | pinctrl-names = "default"; | 343 | pinctrl-names = "default"; |
| 341 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 344 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 342 | status = "disabled"; | 345 | status = "disabled"; |
| @@ -345,7 +348,7 @@ | |||
| 345 | usart0: serial@f801c000 { | 348 | usart0: serial@f801c000 { |
| 346 | compatible = "atmel,at91sam9260-usart"; | 349 | compatible = "atmel,at91sam9260-usart"; |
| 347 | reg = <0xf801c000 0x4000>; | 350 | reg = <0xf801c000 0x4000>; |
| 348 | interrupts = <5 4 5>; | 351 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| 349 | pinctrl-names = "default"; | 352 | pinctrl-names = "default"; |
| 350 | pinctrl-0 = <&pinctrl_usart0>; | 353 | pinctrl-0 = <&pinctrl_usart0>; |
| 351 | status = "disabled"; | 354 | status = "disabled"; |
| @@ -354,7 +357,7 @@ | |||
| 354 | usart1: serial@f8020000 { | 357 | usart1: serial@f8020000 { |
| 355 | compatible = "atmel,at91sam9260-usart"; | 358 | compatible = "atmel,at91sam9260-usart"; |
| 356 | reg = <0xf8020000 0x4000>; | 359 | reg = <0xf8020000 0x4000>; |
| 357 | interrupts = <6 4 5>; | 360 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 358 | pinctrl-names = "default"; | 361 | pinctrl-names = "default"; |
| 359 | pinctrl-0 = <&pinctrl_usart1>; | 362 | pinctrl-0 = <&pinctrl_usart1>; |
| 360 | status = "disabled"; | 363 | status = "disabled"; |
| @@ -363,7 +366,7 @@ | |||
| 363 | usart2: serial@f8024000 { | 366 | usart2: serial@f8024000 { |
| 364 | compatible = "atmel,at91sam9260-usart"; | 367 | compatible = "atmel,at91sam9260-usart"; |
| 365 | reg = <0xf8024000 0x4000>; | 368 | reg = <0xf8024000 0x4000>; |
| 366 | interrupts = <7 4 5>; | 369 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 367 | pinctrl-names = "default"; | 370 | pinctrl-names = "default"; |
| 368 | pinctrl-0 = <&pinctrl_usart2>; | 371 | pinctrl-0 = <&pinctrl_usart2>; |
| 369 | status = "disabled"; | 372 | status = "disabled"; |
| @@ -372,7 +375,7 @@ | |||
| 372 | usart3: serial@f8028000 { | 375 | usart3: serial@f8028000 { |
| 373 | compatible = "atmel,at91sam9260-usart"; | 376 | compatible = "atmel,at91sam9260-usart"; |
| 374 | reg = <0xf8028000 0x4000>; | 377 | reg = <0xf8028000 0x4000>; |
| 375 | interrupts = <8 4 5>; | 378 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 376 | pinctrl-names = "default"; | 379 | pinctrl-names = "default"; |
| 377 | pinctrl-0 = <&pinctrl_usart3>; | 380 | pinctrl-0 = <&pinctrl_usart3>; |
| 378 | status = "disabled"; | 381 | status = "disabled"; |
| @@ -381,7 +384,7 @@ | |||
| 381 | i2c0: i2c@f8010000 { | 384 | i2c0: i2c@f8010000 { |
| 382 | compatible = "atmel,at91sam9x5-i2c"; | 385 | compatible = "atmel,at91sam9x5-i2c"; |
| 383 | reg = <0xf8010000 0x100>; | 386 | reg = <0xf8010000 0x100>; |
| 384 | interrupts = <9 4 6>; | 387 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
| 385 | dmas = <&dma 1 13>, | 388 | dmas = <&dma 1 13>, |
| 386 | <&dma 1 14>; | 389 | <&dma 1 14>; |
| 387 | dma-names = "tx", "rx"; | 390 | dma-names = "tx", "rx"; |
| @@ -393,7 +396,7 @@ | |||
| 393 | i2c1: i2c@f8014000 { | 396 | i2c1: i2c@f8014000 { |
| 394 | compatible = "atmel,at91sam9x5-i2c"; | 397 | compatible = "atmel,at91sam9x5-i2c"; |
| 395 | reg = <0xf8014000 0x100>; | 398 | reg = <0xf8014000 0x100>; |
| 396 | interrupts = <10 4 6>; | 399 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
| 397 | dmas = <&dma 1 15>, | 400 | dmas = <&dma 1 15>, |
| 398 | <&dma 1 16>; | 401 | <&dma 1 16>; |
| 399 | dma-names = "tx", "rx"; | 402 | dma-names = "tx", "rx"; |
| @@ -407,7 +410,7 @@ | |||
| 407 | #size-cells = <0>; | 410 | #size-cells = <0>; |
| 408 | compatible = "atmel,at91rm9200-spi"; | 411 | compatible = "atmel,at91rm9200-spi"; |
| 409 | reg = <0xf0000000 0x100>; | 412 | reg = <0xf0000000 0x100>; |
| 410 | interrupts = <13 4 3>; | 413 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 411 | pinctrl-names = "default"; | 414 | pinctrl-names = "default"; |
| 412 | pinctrl-0 = <&pinctrl_spi0>; | 415 | pinctrl-0 = <&pinctrl_spi0>; |
| 413 | status = "disabled"; | 416 | status = "disabled"; |
| @@ -418,7 +421,7 @@ | |||
| 418 | #size-cells = <0>; | 421 | #size-cells = <0>; |
| 419 | compatible = "atmel,at91rm9200-spi"; | 422 | compatible = "atmel,at91rm9200-spi"; |
| 420 | reg = <0xf0004000 0x100>; | 423 | reg = <0xf0004000 0x100>; |
| 421 | interrupts = <14 4 3>; | 424 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| 422 | pinctrl-names = "default"; | 425 | pinctrl-names = "default"; |
| 423 | pinctrl-0 = <&pinctrl_spi1>; | 426 | pinctrl-0 = <&pinctrl_spi1>; |
| 424 | status = "disabled"; | 427 | status = "disabled"; |
| @@ -439,8 +442,8 @@ | |||
| 439 | atmel,nand-cmd-offset = <22>; | 442 | atmel,nand-cmd-offset = <22>; |
| 440 | pinctrl-names = "default"; | 443 | pinctrl-names = "default"; |
| 441 | pinctrl-0 = <&pinctrl_nand>; | 444 | pinctrl-0 = <&pinctrl_nand>; |
| 442 | gpios = <&pioD 5 0 | 445 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 443 | &pioD 4 0 | 446 | &pioD 4 GPIO_ACTIVE_HIGH |
| 444 | 0 | 447 | 0 |
| 445 | >; | 448 | >; |
| 446 | status = "disabled"; | 449 | status = "disabled"; |
| @@ -449,15 +452,15 @@ | |||
| 449 | usb0: ohci@00500000 { | 452 | usb0: ohci@00500000 { |
| 450 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 453 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 451 | reg = <0x00500000 0x00100000>; | 454 | reg = <0x00500000 0x00100000>; |
| 452 | interrupts = <22 4 2>; | 455 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 453 | status = "disabled"; | 456 | status = "disabled"; |
| 454 | }; | 457 | }; |
| 455 | }; | 458 | }; |
| 456 | 459 | ||
| 457 | i2c@0 { | 460 | i2c@0 { |
| 458 | compatible = "i2c-gpio"; | 461 | compatible = "i2c-gpio"; |
| 459 | gpios = <&pioA 30 0 /* sda */ | 462 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 460 | &pioA 31 0 /* scl */ | 463 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ |
| 461 | >; | 464 | >; |
| 462 | i2c-gpio,sda-open-drain; | 465 | i2c-gpio,sda-open-drain; |
| 463 | i2c-gpio,scl-open-drain; | 466 | i2c-gpio,scl-open-drain; |
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index d30e48bd1e9d..2e67cd5e47eb 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9n12.dtsi" | 10 | #include "at91sam9n12.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Atmel AT91SAM9N12-EK"; | 13 | model = "Atmel AT91SAM9N12-EK"; |
| @@ -55,7 +55,7 @@ | |||
| 55 | slot@0 { | 55 | slot@0 { |
| 56 | reg = <0>; | 56 | reg = <0>; |
| 57 | bus-width = <4>; | 57 | bus-width = <4>; |
| 58 | cd-gpios = <&pioA 7 0>; | 58 | cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; |
| 59 | }; | 59 | }; |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| @@ -63,7 +63,7 @@ | |||
| 63 | mmc0 { | 63 | mmc0 { |
| 64 | pinctrl_board_mmc0: mmc0-board { | 64 | pinctrl_board_mmc0: mmc0-board { |
| 65 | atmel,pins = | 65 | atmel,pins = |
| 66 | <0 7 0x0 0x5>; /* PA7 gpio CD pin pull up and deglitch */ | 66 | <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */ |
| 67 | }; | 67 | }; |
| 68 | }; | 68 | }; |
| 69 | }; | 69 | }; |
| @@ -95,19 +95,19 @@ | |||
| 95 | 95 | ||
| 96 | d8 { | 96 | d8 { |
| 97 | label = "d8"; | 97 | label = "d8"; |
| 98 | gpios = <&pioB 4 1>; | 98 | gpios = <&pioB 4 GPIO_ACTIVE_LOW>; |
| 99 | linux,default-trigger = "mmc0"; | 99 | linux,default-trigger = "mmc0"; |
| 100 | }; | 100 | }; |
| 101 | 101 | ||
| 102 | d9 { | 102 | d9 { |
| 103 | label = "d6"; | 103 | label = "d6"; |
| 104 | gpios = <&pioB 5 1>; | 104 | gpios = <&pioB 5 GPIO_ACTIVE_LOW>; |
| 105 | linux,default-trigger = "nand-disk"; | 105 | linux,default-trigger = "nand-disk"; |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | d10 { | 108 | d10 { |
| 109 | label = "d7"; | 109 | label = "d7"; |
| 110 | gpios = <&pioB 6 0>; | 110 | gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; |
| 111 | linux,default-trigger = "heartbeat"; | 111 | linux,default-trigger = "heartbeat"; |
| 112 | }; | 112 | }; |
| 113 | }; | 113 | }; |
| @@ -117,7 +117,7 @@ | |||
| 117 | 117 | ||
| 118 | enter { | 118 | enter { |
| 119 | label = "Enter"; | 119 | label = "Enter"; |
| 120 | gpios = <&pioB 4 1>; | 120 | gpios = <&pioB 4 GPIO_ACTIVE_LOW>; |
| 121 | linux,code = <28>; | 121 | linux,code = <28>; |
| 122 | gpio-key,wakeup; | 122 | gpio-key,wakeup; |
| 123 | }; | 123 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 9ac2bc2b4f07..49e94aba938f 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "at91sam9x5.dtsi" | 9 | #include "at91sam9x5.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9X25 SoC"; | 12 | model = "Atmel AT91SAM9X25 SoC"; |
| @@ -26,16 +26,16 @@ | |||
| 26 | macb1 { | 26 | macb1 { |
| 27 | pinctrl_macb1_rmii: macb1_rmii-0 { | 27 | pinctrl_macb1_rmii: macb1_rmii-0 { |
| 28 | atmel,pins = | 28 | atmel,pins = |
| 29 | <2 16 0x2 0x0 /* PC16 periph B */ | 29 | <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ |
| 30 | 2 18 0x2 0x0 /* PC18 periph B */ | 30 | AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ |
| 31 | 2 19 0x2 0x0 /* PC19 periph B */ | 31 | AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ |
| 32 | 2 20 0x2 0x0 /* PC20 periph B */ | 32 | AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ |
| 33 | 2 21 0x2 0x0 /* PC21 periph B */ | 33 | AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ |
| 34 | 2 27 0x2 0x0 /* PC27 periph B */ | 34 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ |
| 35 | 2 28 0x2 0x0 /* PC28 periph B */ | 35 | AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ |
| 36 | 2 29 0x2 0x0 /* PC29 periph B */ | 36 | AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ |
| 37 | 2 30 0x2 0x0 /* PC30 periph B */ | 37 | AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ |
| 38 | 2 31 0x2 0x0>; /* PC31 periph B */ | 38 | AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ |
| 39 | }; | 39 | }; |
| 40 | }; | 40 | }; |
| 41 | }; | 41 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 315250b4995e..494864836e83 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9x25.dtsi" | 10 | #include "at91sam9x25.dtsi" |
| 11 | /include/ "at91sam9x5ek.dtsi" | 11 | #include "at91sam9x5ek.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9X25-EK"; | 14 | model = "Atmel AT91SAM9X25-EK"; |
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index ba67d83d17ac..1a3d525a1f5d 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "at91sam9x5.dtsi" | 9 | #include "at91sam9x5.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9X35 SoC"; | 12 | model = "Atmel AT91SAM9X35 SoC"; |
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts index 6ad19a0d5424..343d32818ca3 100644 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ b/arch/arm/boot/dts/at91sam9x35ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "at91sam9x35.dtsi" | 10 | #include "at91sam9x35.dtsi" |
| 11 | /include/ "at91sam9x5ek.dtsi" | 11 | #include "at91sam9x5ek.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel AT91SAM9X35-EK"; | 14 | model = "Atmel AT91SAM9X35-EK"; |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 1145ac330fb7..af91599488e9 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -9,7 +9,10 @@ | |||
| 9 | * Licensed under GPLv2 or later. | 9 | * Licensed under GPLv2 or later. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include <dt-bindings/pinctrl/at91.h> | ||
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 15 | #include <dt-bindings/gpio/gpio.h> | ||
| 13 | 16 | ||
| 14 | / { | 17 | / { |
| 15 | model = "Atmel AT91SAM9x5 family SoC"; | 18 | model = "Atmel AT91SAM9x5 family SoC"; |
| @@ -85,32 +88,32 @@ | |||
| 85 | pit: timer@fffffe30 { | 88 | pit: timer@fffffe30 { |
| 86 | compatible = "atmel,at91sam9260-pit"; | 89 | compatible = "atmel,at91sam9260-pit"; |
| 87 | reg = <0xfffffe30 0xf>; | 90 | reg = <0xfffffe30 0xf>; |
| 88 | interrupts = <1 4 7>; | 91 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 89 | }; | 92 | }; |
| 90 | 93 | ||
| 91 | tcb0: timer@f8008000 { | 94 | tcb0: timer@f8008000 { |
| 92 | compatible = "atmel,at91sam9x5-tcb"; | 95 | compatible = "atmel,at91sam9x5-tcb"; |
| 93 | reg = <0xf8008000 0x100>; | 96 | reg = <0xf8008000 0x100>; |
| 94 | interrupts = <17 4 0>; | 97 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 95 | }; | 98 | }; |
| 96 | 99 | ||
| 97 | tcb1: timer@f800c000 { | 100 | tcb1: timer@f800c000 { |
| 98 | compatible = "atmel,at91sam9x5-tcb"; | 101 | compatible = "atmel,at91sam9x5-tcb"; |
| 99 | reg = <0xf800c000 0x100>; | 102 | reg = <0xf800c000 0x100>; |
| 100 | interrupts = <17 4 0>; | 103 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 101 | }; | 104 | }; |
| 102 | 105 | ||
| 103 | dma0: dma-controller@ffffec00 { | 106 | dma0: dma-controller@ffffec00 { |
| 104 | compatible = "atmel,at91sam9g45-dma"; | 107 | compatible = "atmel,at91sam9g45-dma"; |
| 105 | reg = <0xffffec00 0x200>; | 108 | reg = <0xffffec00 0x200>; |
| 106 | interrupts = <20 4 0>; | 109 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 107 | #dma-cells = <2>; | 110 | #dma-cells = <2>; |
| 108 | }; | 111 | }; |
| 109 | 112 | ||
| 110 | dma1: dma-controller@ffffee00 { | 113 | dma1: dma-controller@ffffee00 { |
| 111 | compatible = "atmel,at91sam9g45-dma"; | 114 | compatible = "atmel,at91sam9g45-dma"; |
| 112 | reg = <0xffffee00 0x200>; | 115 | reg = <0xffffee00 0x200>; |
| 113 | interrupts = <21 4 0>; | 116 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
| 114 | #dma-cells = <2>; | 117 | #dma-cells = <2>; |
| 115 | }; | 118 | }; |
| 116 | 119 | ||
| @@ -124,297 +127,297 @@ | |||
| 124 | dbgu { | 127 | dbgu { |
| 125 | pinctrl_dbgu: dbgu-0 { | 128 | pinctrl_dbgu: dbgu-0 { |
| 126 | atmel,pins = | 129 | atmel,pins = |
| 127 | <0 9 0x1 0x0 /* PA9 periph A */ | 130 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 128 | 0 10 0x1 0x1>; /* PA10 periph A with pullup */ | 131 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */ |
| 129 | }; | 132 | }; |
| 130 | }; | 133 | }; |
| 131 | 134 | ||
| 132 | usart0 { | 135 | usart0 { |
| 133 | pinctrl_usart0: usart0-0 { | 136 | pinctrl_usart0: usart0-0 { |
| 134 | atmel,pins = | 137 | atmel,pins = |
| 135 | <0 0 0x1 0x1 /* PA0 periph A with pullup */ | 138 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ |
| 136 | 0 1 0x1 0x0>; /* PA1 periph A */ | 139 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ |
| 137 | }; | 140 | }; |
| 138 | 141 | ||
| 139 | pinctrl_usart0_rts: usart0_rts-0 { | 142 | pinctrl_usart0_rts: usart0_rts-0 { |
| 140 | atmel,pins = | 143 | atmel,pins = |
| 141 | <0 2 0x1 0x0>; /* PA2 periph A */ | 144 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
| 142 | }; | 145 | }; |
| 143 | 146 | ||
| 144 | pinctrl_usart0_cts: usart0_cts-0 { | 147 | pinctrl_usart0_cts: usart0_cts-0 { |
| 145 | atmel,pins = | 148 | atmel,pins = |
| 146 | <0 3 0x1 0x0>; /* PA3 periph A */ | 149 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
| 147 | }; | 150 | }; |
| 148 | 151 | ||
| 149 | pinctrl_usart0_sck: usart0_sck-0 { | 152 | pinctrl_usart0_sck: usart0_sck-0 { |
| 150 | atmel,pins = | 153 | atmel,pins = |
| 151 | <0 4 0x1 0x0>; /* PA4 periph A */ | 154 | <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ |
| 152 | }; | 155 | }; |
| 153 | }; | 156 | }; |
| 154 | 157 | ||
| 155 | usart1 { | 158 | usart1 { |
| 156 | pinctrl_usart1: usart1-0 { | 159 | pinctrl_usart1: usart1-0 { |
| 157 | atmel,pins = | 160 | atmel,pins = |
| 158 | <0 5 0x1 0x1 /* PA5 periph A with pullup */ | 161 | <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ |
| 159 | 0 6 0x1 0x0>; /* PA6 periph A */ | 162 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ |
| 160 | }; | 163 | }; |
| 161 | 164 | ||
| 162 | pinctrl_usart1_rts: usart1_rts-0 { | 165 | pinctrl_usart1_rts: usart1_rts-0 { |
| 163 | atmel,pins = | 166 | atmel,pins = |
| 164 | <2 27 0x3 0x0>; /* PC27 periph C */ | 167 | <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ |
| 165 | }; | 168 | }; |
| 166 | 169 | ||
| 167 | pinctrl_usart1_cts: usart1_cts-0 { | 170 | pinctrl_usart1_cts: usart1_cts-0 { |
| 168 | atmel,pins = | 171 | atmel,pins = |
| 169 | <2 28 0x3 0x0>; /* PC28 periph C */ | 172 | <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ |
| 170 | }; | 173 | }; |
| 171 | 174 | ||
| 172 | pinctrl_usart1_sck: usart1_sck-0 { | 175 | pinctrl_usart1_sck: usart1_sck-0 { |
| 173 | atmel,pins = | 176 | atmel,pins = |
| 174 | <2 28 0x3 0x0>; /* PC29 periph C */ | 177 | <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ |
| 175 | }; | 178 | }; |
| 176 | }; | 179 | }; |
| 177 | 180 | ||
| 178 | usart2 { | 181 | usart2 { |
| 179 | pinctrl_usart2: usart2-0 { | 182 | pinctrl_usart2: usart2-0 { |
| 180 | atmel,pins = | 183 | atmel,pins = |
| 181 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | 184 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 182 | 0 8 0x1 0x0>; /* PA8 periph A */ | 185 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ |
| 183 | }; | 186 | }; |
| 184 | 187 | ||
| 185 | pinctrl_uart2_rts: uart2_rts-0 { | 188 | pinctrl_uart2_rts: uart2_rts-0 { |
| 186 | atmel,pins = | 189 | atmel,pins = |
| 187 | <1 0 0x2 0x0>; /* PB0 periph B */ | 190 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
| 188 | }; | 191 | }; |
| 189 | 192 | ||
| 190 | pinctrl_uart2_cts: uart2_cts-0 { | 193 | pinctrl_uart2_cts: uart2_cts-0 { |
| 191 | atmel,pins = | 194 | atmel,pins = |
| 192 | <1 1 0x2 0x0>; /* PB1 periph B */ | 195 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
| 193 | }; | 196 | }; |
| 194 | 197 | ||
| 195 | pinctrl_usart2_sck: usart2_sck-0 { | 198 | pinctrl_usart2_sck: usart2_sck-0 { |
| 196 | atmel,pins = | 199 | atmel,pins = |
| 197 | <1 2 0x2 0x0>; /* PB2 periph B */ | 200 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ |
| 198 | }; | 201 | }; |
| 199 | }; | 202 | }; |
| 200 | 203 | ||
| 201 | usart3 { | 204 | usart3 { |
| 202 | pinctrl_usart3: usart3-0 { | 205 | pinctrl_usart3: usart3-0 { |
| 203 | atmel,pins = | 206 | atmel,pins = |
| 204 | <2 22 0x2 0x1 /* PC22 periph B with pullup */ | 207 | <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ |
| 205 | 2 23 0x2 0x0>; /* PC23 periph B */ | 208 | AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ |
| 206 | }; | 209 | }; |
| 207 | 210 | ||
| 208 | pinctrl_usart3_rts: usart3_rts-0 { | 211 | pinctrl_usart3_rts: usart3_rts-0 { |
| 209 | atmel,pins = | 212 | atmel,pins = |
| 210 | <2 24 0x2 0x0>; /* PC24 periph B */ | 213 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
| 211 | }; | 214 | }; |
| 212 | 215 | ||
| 213 | pinctrl_usart3_cts: usart3_cts-0 { | 216 | pinctrl_usart3_cts: usart3_cts-0 { |
| 214 | atmel,pins = | 217 | atmel,pins = |
| 215 | <2 25 0x2 0x0>; /* PC25 periph B */ | 218 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
| 216 | }; | 219 | }; |
| 217 | 220 | ||
| 218 | pinctrl_usart3_sck: usart3_sck-0 { | 221 | pinctrl_usart3_sck: usart3_sck-0 { |
| 219 | atmel,pins = | 222 | atmel,pins = |
| 220 | <2 26 0x2 0x0>; /* PC26 periph B */ | 223 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ |
| 221 | }; | 224 | }; |
| 222 | }; | 225 | }; |
| 223 | 226 | ||
| 224 | uart0 { | 227 | uart0 { |
| 225 | pinctrl_uart0: uart0-0 { | 228 | pinctrl_uart0: uart0-0 { |
| 226 | atmel,pins = | 229 | atmel,pins = |
| 227 | <2 8 0x3 0x0 /* PC8 periph C */ | 230 | <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ |
| 228 | 2 9 0x3 0x1>; /* PC9 periph C with pullup */ | 231 | AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ |
| 229 | }; | 232 | }; |
| 230 | }; | 233 | }; |
| 231 | 234 | ||
| 232 | uart1 { | 235 | uart1 { |
| 233 | pinctrl_uart1: uart1-0 { | 236 | pinctrl_uart1: uart1-0 { |
| 234 | atmel,pins = | 237 | atmel,pins = |
| 235 | <2 16 0x3 0x0 /* PC16 periph C */ | 238 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ |
| 236 | 2 17 0x3 0x1>; /* PC17 periph C with pullup */ | 239 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ |
| 237 | }; | 240 | }; |
| 238 | }; | 241 | }; |
| 239 | 242 | ||
| 240 | nand { | 243 | nand { |
| 241 | pinctrl_nand: nand-0 { | 244 | pinctrl_nand: nand-0 { |
| 242 | atmel,pins = | 245 | atmel,pins = |
| 243 | <3 0 0x1 0x0 /* PD0 periph A Read Enable */ | 246 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ |
| 244 | 3 1 0x1 0x0 /* PD1 periph A Write Enable */ | 247 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ |
| 245 | 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ | 248 | AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ |
| 246 | 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ | 249 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ |
| 247 | 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ | 250 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ |
| 248 | 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ | 251 | AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ |
| 249 | 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ | 252 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ |
| 250 | 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ | 253 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ |
| 251 | 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ | 254 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ |
| 252 | 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ | 255 | AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ |
| 253 | 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ | 256 | AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ |
| 254 | 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ | 257 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ |
| 255 | 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ | 258 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ |
| 256 | 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ | 259 | AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ |
| 257 | }; | 260 | }; |
| 258 | 261 | ||
| 259 | pinctrl_nand_16bits: nand_16bits-0 { | 262 | pinctrl_nand_16bits: nand_16bits-0 { |
| 260 | atmel,pins = | 263 | atmel,pins = |
| 261 | <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ | 264 | <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ |
| 262 | 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ | 265 | AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ |
| 263 | 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ | 266 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ |
| 264 | 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ | 267 | AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ |
| 265 | 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ | 268 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ |
| 266 | 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ | 269 | AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ |
| 267 | 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ | 270 | AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ |
| 268 | 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ | 271 | AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ |
| 269 | }; | 272 | }; |
| 270 | }; | 273 | }; |
| 271 | 274 | ||
| 272 | macb0 { | 275 | macb0 { |
| 273 | pinctrl_macb0_rmii: macb0_rmii-0 { | 276 | pinctrl_macb0_rmii: macb0_rmii-0 { |
| 274 | atmel,pins = | 277 | atmel,pins = |
| 275 | <1 0 0x1 0x0 /* PB0 periph A */ | 278 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ |
| 276 | 1 1 0x1 0x0 /* PB1 periph A */ | 279 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ |
| 277 | 1 2 0x1 0x0 /* PB2 periph A */ | 280 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ |
| 278 | 1 3 0x1 0x0 /* PB3 periph A */ | 281 | AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ |
| 279 | 1 4 0x1 0x0 /* PB4 periph A */ | 282 | AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ |
| 280 | 1 5 0x1 0x0 /* PB5 periph A */ | 283 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ |
| 281 | 1 6 0x1 0x0 /* PB6 periph A */ | 284 | AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
| 282 | 1 7 0x1 0x0 /* PB7 periph A */ | 285 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ |
| 283 | 1 9 0x1 0x0 /* PB9 periph A */ | 286 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
| 284 | 1 10 0x1 0x0>; /* PB10 periph A */ | 287 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ |
| 285 | }; | 288 | }; |
| 286 | 289 | ||
| 287 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { | 290 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { |
| 288 | atmel,pins = | 291 | atmel,pins = |
| 289 | <1 8 0x1 0x0 /* PB8 periph A */ | 292 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ |
| 290 | 1 11 0x1 0x0 /* PB11 periph A */ | 293 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ |
| 291 | 1 12 0x1 0x0 /* PB12 periph A */ | 294 | AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
| 292 | 1 13 0x1 0x0 /* PB13 periph A */ | 295 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ |
| 293 | 1 14 0x1 0x0 /* PB14 periph A */ | 296 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ |
| 294 | 1 15 0x1 0x0 /* PB15 periph A */ | 297 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ |
| 295 | 1 16 0x1 0x0 /* PB16 periph A */ | 298 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ |
| 296 | 1 17 0x1 0x0>; /* PB17 periph A */ | 299 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ |
| 297 | }; | 300 | }; |
| 298 | }; | 301 | }; |
| 299 | 302 | ||
| 300 | mmc0 { | 303 | mmc0 { |
| 301 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | 304 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 302 | atmel,pins = | 305 | atmel,pins = |
| 303 | <0 17 0x1 0x0 /* PA17 periph A */ | 306 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 304 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | 307 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 305 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | 308 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
| 306 | }; | 309 | }; |
| 307 | 310 | ||
| 308 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 311 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 309 | atmel,pins = | 312 | atmel,pins = |
| 310 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | 313 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 311 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | 314 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 312 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | 315 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
| 313 | }; | 316 | }; |
| 314 | }; | 317 | }; |
| 315 | 318 | ||
| 316 | mmc1 { | 319 | mmc1 { |
| 317 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | 320 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 318 | atmel,pins = | 321 | atmel,pins = |
| 319 | <0 13 0x2 0x0 /* PA13 periph B */ | 322 | <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ |
| 320 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | 323 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| 321 | 0 11 0x2 0x1>; /* PA11 periph B with pullup */ | 324 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ |
| 322 | }; | 325 | }; |
| 323 | 326 | ||
| 324 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | 327 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 325 | atmel,pins = | 328 | atmel,pins = |
| 326 | <0 2 0x2 0x1 /* PA2 periph B with pullup */ | 329 | <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ |
| 327 | 0 3 0x2 0x1 /* PA3 periph B with pullup */ | 330 | AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ |
| 328 | 0 4 0x2 0x1>; /* PA4 periph B with pullup */ | 331 | AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ |
| 329 | }; | 332 | }; |
| 330 | }; | 333 | }; |
| 331 | 334 | ||
| 332 | ssc0 { | 335 | ssc0 { |
| 333 | pinctrl_ssc0_tx: ssc0_tx-0 { | 336 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 334 | atmel,pins = | 337 | atmel,pins = |
| 335 | <0 24 0x2 0x0 /* PA24 periph B */ | 338 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 336 | 0 25 0x2 0x0 /* PA25 periph B */ | 339 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 337 | 0 26 0x2 0x0>; /* PA26 periph B */ | 340 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
| 338 | }; | 341 | }; |
| 339 | 342 | ||
| 340 | pinctrl_ssc0_rx: ssc0_rx-0 { | 343 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 341 | atmel,pins = | 344 | atmel,pins = |
| 342 | <0 27 0x2 0x0 /* PA27 periph B */ | 345 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 343 | 0 28 0x2 0x0 /* PA28 periph B */ | 346 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 344 | 0 29 0x2 0x0>; /* PA29 periph B */ | 347 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
| 345 | }; | 348 | }; |
| 346 | }; | 349 | }; |
| 347 | 350 | ||
| 348 | spi0 { | 351 | spi0 { |
| 349 | pinctrl_spi0: spi0-0 { | 352 | pinctrl_spi0: spi0-0 { |
| 350 | atmel,pins = | 353 | atmel,pins = |
| 351 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | 354 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 352 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | 355 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| 353 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | 356 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
| 354 | }; | 357 | }; |
| 355 | }; | 358 | }; |
| 356 | 359 | ||
| 357 | spi1 { | 360 | spi1 { |
| 358 | pinctrl_spi1: spi1-0 { | 361 | pinctrl_spi1: spi1-0 { |
| 359 | atmel,pins = | 362 | atmel,pins = |
| 360 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | 363 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 361 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | 364 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| 362 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | 365 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
| 363 | }; | 366 | }; |
| 364 | }; | 367 | }; |
| 365 | 368 | ||
| 366 | i2c0 { | 369 | i2c0 { |
| 367 | pinctrl_i2c0: i2c0-0 { | 370 | pinctrl_i2c0: i2c0-0 { |
| 368 | atmel,pins = | 371 | atmel,pins = |
| 369 | <0 30 0x1 0x0 /* PA30 periph A I2C0 data */ | 372 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ |
| 370 | 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */ | 373 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ |
| 371 | }; | 374 | }; |
| 372 | }; | 375 | }; |
| 373 | 376 | ||
| 374 | i2c1 { | 377 | i2c1 { |
| 375 | pinctrl_i2c1: i2c1-0 { | 378 | pinctrl_i2c1: i2c1-0 { |
| 376 | atmel,pins = | 379 | atmel,pins = |
| 377 | <2 0 0x3 0x0 /* PC0 periph C I2C1 data */ | 380 | <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ |
| 378 | 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */ | 381 | AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ |
| 379 | }; | 382 | }; |
| 380 | }; | 383 | }; |
| 381 | 384 | ||
| 382 | i2c2 { | 385 | i2c2 { |
| 383 | pinctrl_i2c2: i2c2-0 { | 386 | pinctrl_i2c2: i2c2-0 { |
| 384 | atmel,pins = | 387 | atmel,pins = |
| 385 | <1 4 0x2 0x0 /* PB4 periph B I2C2 data */ | 388 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ |
| 386 | 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */ | 389 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ |
| 387 | }; | 390 | }; |
| 388 | }; | 391 | }; |
| 389 | 392 | ||
| 390 | i2c_gpio0 { | 393 | i2c_gpio0 { |
| 391 | pinctrl_i2c_gpio0: i2c_gpio0-0 { | 394 | pinctrl_i2c_gpio0: i2c_gpio0-0 { |
| 392 | atmel,pins = | 395 | atmel,pins = |
| 393 | <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */ | 396 | <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ |
| 394 | 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */ | 397 | AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ |
| 395 | }; | 398 | }; |
| 396 | }; | 399 | }; |
| 397 | 400 | ||
| 398 | i2c_gpio1 { | 401 | i2c_gpio1 { |
| 399 | pinctrl_i2c_gpio1: i2c_gpio1-0 { | 402 | pinctrl_i2c_gpio1: i2c_gpio1-0 { |
| 400 | atmel,pins = | 403 | atmel,pins = |
| 401 | <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */ | 404 | <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ |
| 402 | 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */ | 405 | AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ |
| 403 | }; | 406 | }; |
| 404 | }; | 407 | }; |
| 405 | 408 | ||
| 406 | i2c_gpio2 { | 409 | i2c_gpio2 { |
| 407 | pinctrl_i2c_gpio2: i2c_gpio2-0 { | 410 | pinctrl_i2c_gpio2: i2c_gpio2-0 { |
| 408 | atmel,pins = | 411 | atmel,pins = |
| 409 | <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */ | 412 | <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ |
| 410 | 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */ | 413 | AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ |
| 411 | }; | 414 | }; |
| 412 | }; | 415 | }; |
| 413 | 416 | ||
| 414 | pioA: gpio@fffff400 { | 417 | pioA: gpio@fffff400 { |
| 415 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 418 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 416 | reg = <0xfffff400 0x200>; | 419 | reg = <0xfffff400 0x200>; |
| 417 | interrupts = <2 4 1>; | 420 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 418 | #gpio-cells = <2>; | 421 | #gpio-cells = <2>; |
| 419 | gpio-controller; | 422 | gpio-controller; |
| 420 | interrupt-controller; | 423 | interrupt-controller; |
| @@ -424,7 +427,7 @@ | |||
| 424 | pioB: gpio@fffff600 { | 427 | pioB: gpio@fffff600 { |
| 425 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 428 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 426 | reg = <0xfffff600 0x200>; | 429 | reg = <0xfffff600 0x200>; |
| 427 | interrupts = <2 4 1>; | 430 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| 428 | #gpio-cells = <2>; | 431 | #gpio-cells = <2>; |
| 429 | gpio-controller; | 432 | gpio-controller; |
| 430 | #gpio-lines = <19>; | 433 | #gpio-lines = <19>; |
| @@ -435,7 +438,7 @@ | |||
| 435 | pioC: gpio@fffff800 { | 438 | pioC: gpio@fffff800 { |
| 436 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 439 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 437 | reg = <0xfffff800 0x200>; | 440 | reg = <0xfffff800 0x200>; |
| 438 | interrupts = <3 4 1>; | 441 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 439 | #gpio-cells = <2>; | 442 | #gpio-cells = <2>; |
| 440 | gpio-controller; | 443 | gpio-controller; |
| 441 | interrupt-controller; | 444 | interrupt-controller; |
| @@ -445,7 +448,7 @@ | |||
| 445 | pioD: gpio@fffffa00 { | 448 | pioD: gpio@fffffa00 { |
| 446 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 449 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 447 | reg = <0xfffffa00 0x200>; | 450 | reg = <0xfffffa00 0x200>; |
| 448 | interrupts = <3 4 1>; | 451 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| 449 | #gpio-cells = <2>; | 452 | #gpio-cells = <2>; |
| 450 | gpio-controller; | 453 | gpio-controller; |
| 451 | #gpio-lines = <22>; | 454 | #gpio-lines = <22>; |
| @@ -457,7 +460,7 @@ | |||
| 457 | ssc0: ssc@f0010000 { | 460 | ssc0: ssc@f0010000 { |
| 458 | compatible = "atmel,at91sam9g45-ssc"; | 461 | compatible = "atmel,at91sam9g45-ssc"; |
| 459 | reg = <0xf0010000 0x4000>; | 462 | reg = <0xf0010000 0x4000>; |
| 460 | interrupts = <28 4 5>; | 463 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
| 461 | pinctrl-names = "default"; | 464 | pinctrl-names = "default"; |
| 462 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 465 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 463 | status = "disabled"; | 466 | status = "disabled"; |
| @@ -466,7 +469,7 @@ | |||
| 466 | mmc0: mmc@f0008000 { | 469 | mmc0: mmc@f0008000 { |
| 467 | compatible = "atmel,hsmci"; | 470 | compatible = "atmel,hsmci"; |
| 468 | reg = <0xf0008000 0x600>; | 471 | reg = <0xf0008000 0x600>; |
| 469 | interrupts = <12 4 0>; | 472 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| 470 | dmas = <&dma0 1 0>; | 473 | dmas = <&dma0 1 0>; |
| 471 | dma-names = "rxtx"; | 474 | dma-names = "rxtx"; |
| 472 | #address-cells = <1>; | 475 | #address-cells = <1>; |
| @@ -477,7 +480,7 @@ | |||
| 477 | mmc1: mmc@f000c000 { | 480 | mmc1: mmc@f000c000 { |
| 478 | compatible = "atmel,hsmci"; | 481 | compatible = "atmel,hsmci"; |
| 479 | reg = <0xf000c000 0x600>; | 482 | reg = <0xf000c000 0x600>; |
| 480 | interrupts = <26 4 0>; | 483 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
| 481 | dmas = <&dma1 1 0>; | 484 | dmas = <&dma1 1 0>; |
| 482 | dma-names = "rxtx"; | 485 | dma-names = "rxtx"; |
| 483 | #address-cells = <1>; | 486 | #address-cells = <1>; |
| @@ -488,7 +491,7 @@ | |||
| 488 | dbgu: serial@fffff200 { | 491 | dbgu: serial@fffff200 { |
| 489 | compatible = "atmel,at91sam9260-usart"; | 492 | compatible = "atmel,at91sam9260-usart"; |
| 490 | reg = <0xfffff200 0x200>; | 493 | reg = <0xfffff200 0x200>; |
| 491 | interrupts = <1 4 7>; | 494 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 492 | pinctrl-names = "default"; | 495 | pinctrl-names = "default"; |
| 493 | pinctrl-0 = <&pinctrl_dbgu>; | 496 | pinctrl-0 = <&pinctrl_dbgu>; |
| 494 | status = "disabled"; | 497 | status = "disabled"; |
| @@ -497,7 +500,7 @@ | |||
| 497 | usart0: serial@f801c000 { | 500 | usart0: serial@f801c000 { |
| 498 | compatible = "atmel,at91sam9260-usart"; | 501 | compatible = "atmel,at91sam9260-usart"; |
| 499 | reg = <0xf801c000 0x200>; | 502 | reg = <0xf801c000 0x200>; |
| 500 | interrupts = <5 4 5>; | 503 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| 501 | pinctrl-names = "default"; | 504 | pinctrl-names = "default"; |
| 502 | pinctrl-0 = <&pinctrl_usart0>; | 505 | pinctrl-0 = <&pinctrl_usart0>; |
| 503 | status = "disabled"; | 506 | status = "disabled"; |
| @@ -506,7 +509,7 @@ | |||
| 506 | usart1: serial@f8020000 { | 509 | usart1: serial@f8020000 { |
| 507 | compatible = "atmel,at91sam9260-usart"; | 510 | compatible = "atmel,at91sam9260-usart"; |
| 508 | reg = <0xf8020000 0x200>; | 511 | reg = <0xf8020000 0x200>; |
| 509 | interrupts = <6 4 5>; | 512 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 510 | pinctrl-names = "default"; | 513 | pinctrl-names = "default"; |
| 511 | pinctrl-0 = <&pinctrl_usart1>; | 514 | pinctrl-0 = <&pinctrl_usart1>; |
| 512 | status = "disabled"; | 515 | status = "disabled"; |
| @@ -515,7 +518,7 @@ | |||
| 515 | usart2: serial@f8024000 { | 518 | usart2: serial@f8024000 { |
| 516 | compatible = "atmel,at91sam9260-usart"; | 519 | compatible = "atmel,at91sam9260-usart"; |
| 517 | reg = <0xf8024000 0x200>; | 520 | reg = <0xf8024000 0x200>; |
| 518 | interrupts = <7 4 5>; | 521 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 519 | pinctrl-names = "default"; | 522 | pinctrl-names = "default"; |
| 520 | pinctrl-0 = <&pinctrl_usart2>; | 523 | pinctrl-0 = <&pinctrl_usart2>; |
| 521 | status = "disabled"; | 524 | status = "disabled"; |
| @@ -524,7 +527,7 @@ | |||
| 524 | macb0: ethernet@f802c000 { | 527 | macb0: ethernet@f802c000 { |
| 525 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 528 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 526 | reg = <0xf802c000 0x100>; | 529 | reg = <0xf802c000 0x100>; |
| 527 | interrupts = <24 4 3>; | 530 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
| 528 | pinctrl-names = "default"; | 531 | pinctrl-names = "default"; |
| 529 | pinctrl-0 = <&pinctrl_macb0_rmii>; | 532 | pinctrl-0 = <&pinctrl_macb0_rmii>; |
| 530 | status = "disabled"; | 533 | status = "disabled"; |
| @@ -533,14 +536,14 @@ | |||
| 533 | macb1: ethernet@f8030000 { | 536 | macb1: ethernet@f8030000 { |
| 534 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 537 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 535 | reg = <0xf8030000 0x100>; | 538 | reg = <0xf8030000 0x100>; |
| 536 | interrupts = <27 4 3>; | 539 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; |
| 537 | status = "disabled"; | 540 | status = "disabled"; |
| 538 | }; | 541 | }; |
| 539 | 542 | ||
| 540 | i2c0: i2c@f8010000 { | 543 | i2c0: i2c@f8010000 { |
| 541 | compatible = "atmel,at91sam9x5-i2c"; | 544 | compatible = "atmel,at91sam9x5-i2c"; |
| 542 | reg = <0xf8010000 0x100>; | 545 | reg = <0xf8010000 0x100>; |
| 543 | interrupts = <9 4 6>; | 546 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
| 544 | dmas = <&dma0 1 7>, | 547 | dmas = <&dma0 1 7>, |
| 545 | <&dma0 1 8>; | 548 | <&dma0 1 8>; |
| 546 | dma-names = "tx", "rx"; | 549 | dma-names = "tx", "rx"; |
| @@ -554,7 +557,7 @@ | |||
| 554 | i2c1: i2c@f8014000 { | 557 | i2c1: i2c@f8014000 { |
| 555 | compatible = "atmel,at91sam9x5-i2c"; | 558 | compatible = "atmel,at91sam9x5-i2c"; |
| 556 | reg = <0xf8014000 0x100>; | 559 | reg = <0xf8014000 0x100>; |
| 557 | interrupts = <10 4 6>; | 560 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
| 558 | dmas = <&dma1 1 5>, | 561 | dmas = <&dma1 1 5>, |
| 559 | <&dma1 1 6>; | 562 | <&dma1 1 6>; |
| 560 | dma-names = "tx", "rx"; | 563 | dma-names = "tx", "rx"; |
| @@ -568,7 +571,7 @@ | |||
| 568 | i2c2: i2c@f8018000 { | 571 | i2c2: i2c@f8018000 { |
| 569 | compatible = "atmel,at91sam9x5-i2c"; | 572 | compatible = "atmel,at91sam9x5-i2c"; |
| 570 | reg = <0xf8018000 0x100>; | 573 | reg = <0xf8018000 0x100>; |
| 571 | interrupts = <11 4 6>; | 574 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
| 572 | dmas = <&dma0 1 9>, | 575 | dmas = <&dma0 1 9>, |
| 573 | <&dma0 1 10>; | 576 | <&dma0 1 10>; |
| 574 | dma-names = "tx", "rx"; | 577 | dma-names = "tx", "rx"; |
| @@ -582,7 +585,7 @@ | |||
| 582 | adc0: adc@f804c000 { | 585 | adc0: adc@f804c000 { |
| 583 | compatible = "atmel,at91sam9260-adc"; | 586 | compatible = "atmel,at91sam9260-adc"; |
| 584 | reg = <0xf804c000 0x100>; | 587 | reg = <0xf804c000 0x100>; |
| 585 | interrupts = <19 4 0>; | 588 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 586 | atmel,adc-use-external; | 589 | atmel,adc-use-external; |
| 587 | atmel,adc-channels-used = <0xffff>; | 590 | atmel,adc-channels-used = <0xffff>; |
| 588 | atmel,adc-vref = <3300>; | 591 | atmel,adc-vref = <3300>; |
| @@ -625,7 +628,7 @@ | |||
| 625 | #size-cells = <0>; | 628 | #size-cells = <0>; |
| 626 | compatible = "atmel,at91rm9200-spi"; | 629 | compatible = "atmel,at91rm9200-spi"; |
| 627 | reg = <0xf0000000 0x100>; | 630 | reg = <0xf0000000 0x100>; |
| 628 | interrupts = <13 4 3>; | 631 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 629 | pinctrl-names = "default"; | 632 | pinctrl-names = "default"; |
| 630 | pinctrl-0 = <&pinctrl_spi0>; | 633 | pinctrl-0 = <&pinctrl_spi0>; |
| 631 | status = "disabled"; | 634 | status = "disabled"; |
| @@ -636,7 +639,7 @@ | |||
| 636 | #size-cells = <0>; | 639 | #size-cells = <0>; |
| 637 | compatible = "atmel,at91rm9200-spi"; | 640 | compatible = "atmel,at91rm9200-spi"; |
| 638 | reg = <0xf0004000 0x100>; | 641 | reg = <0xf0004000 0x100>; |
| 639 | interrupts = <14 4 3>; | 642 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| 640 | pinctrl-names = "default"; | 643 | pinctrl-names = "default"; |
| 641 | pinctrl-0 = <&pinctrl_spi1>; | 644 | pinctrl-0 = <&pinctrl_spi1>; |
| 642 | status = "disabled"; | 645 | status = "disabled"; |
| @@ -645,7 +648,7 @@ | |||
| 645 | rtc@fffffeb0 { | 648 | rtc@fffffeb0 { |
| 646 | compatible = "atmel,at91rm9200-rtc"; | 649 | compatible = "atmel,at91rm9200-rtc"; |
| 647 | reg = <0xfffffeb0 0x40>; | 650 | reg = <0xfffffeb0 0x40>; |
| 648 | interrupts = <1 4 7>; | 651 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 649 | status = "disabled"; | 652 | status = "disabled"; |
| 650 | }; | 653 | }; |
| 651 | }; | 654 | }; |
| @@ -664,8 +667,8 @@ | |||
| 664 | atmel,nand-cmd-offset = <22>; | 667 | atmel,nand-cmd-offset = <22>; |
| 665 | pinctrl-names = "default"; | 668 | pinctrl-names = "default"; |
| 666 | pinctrl-0 = <&pinctrl_nand>; | 669 | pinctrl-0 = <&pinctrl_nand>; |
| 667 | gpios = <&pioD 5 0 | 670 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 668 | &pioD 4 0 | 671 | &pioD 4 GPIO_ACTIVE_HIGH |
| 669 | 0 | 672 | 0 |
| 670 | >; | 673 | >; |
| 671 | status = "disabled"; | 674 | status = "disabled"; |
| @@ -674,22 +677,22 @@ | |||
| 674 | usb0: ohci@00600000 { | 677 | usb0: ohci@00600000 { |
| 675 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 678 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 676 | reg = <0x00600000 0x100000>; | 679 | reg = <0x00600000 0x100000>; |
| 677 | interrupts = <22 4 2>; | 680 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 678 | status = "disabled"; | 681 | status = "disabled"; |
| 679 | }; | 682 | }; |
| 680 | 683 | ||
| 681 | usb1: ehci@00700000 { | 684 | usb1: ehci@00700000 { |
| 682 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 685 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 683 | reg = <0x00700000 0x100000>; | 686 | reg = <0x00700000 0x100000>; |
| 684 | interrupts = <22 4 2>; | 687 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 685 | status = "disabled"; | 688 | status = "disabled"; |
| 686 | }; | 689 | }; |
| 687 | }; | 690 | }; |
| 688 | 691 | ||
| 689 | i2c@0 { | 692 | i2c@0 { |
| 690 | compatible = "i2c-gpio"; | 693 | compatible = "i2c-gpio"; |
| 691 | gpios = <&pioA 30 0 /* sda */ | 694 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 692 | &pioA 31 0 /* scl */ | 695 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ |
| 693 | >; | 696 | >; |
| 694 | i2c-gpio,sda-open-drain; | 697 | i2c-gpio,sda-open-drain; |
| 695 | i2c-gpio,scl-open-drain; | 698 | i2c-gpio,scl-open-drain; |
| @@ -703,8 +706,8 @@ | |||
| 703 | 706 | ||
| 704 | i2c@1 { | 707 | i2c@1 { |
| 705 | compatible = "i2c-gpio"; | 708 | compatible = "i2c-gpio"; |
| 706 | gpios = <&pioC 0 0 /* sda */ | 709 | gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ |
| 707 | &pioC 1 0 /* scl */ | 710 | &pioC 1 GPIO_ACTIVE_HIGH /* scl */ |
| 708 | >; | 711 | >; |
| 709 | i2c-gpio,sda-open-drain; | 712 | i2c-gpio,sda-open-drain; |
| 710 | i2c-gpio,scl-open-drain; | 713 | i2c-gpio,scl-open-drain; |
| @@ -718,8 +721,8 @@ | |||
| 718 | 721 | ||
| 719 | i2c@2 { | 722 | i2c@2 { |
| 720 | compatible = "i2c-gpio"; | 723 | compatible = "i2c-gpio"; |
| 721 | gpios = <&pioB 4 0 /* sda */ | 724 | gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ |
| 722 | &pioB 5 0 /* scl */ | 725 | &pioB 5 GPIO_ACTIVE_HIGH /* scl */ |
| 723 | >; | 726 | >; |
| 724 | i2c-gpio,sda-open-drain; | 727 | i2c-gpio,sda-open-drain; |
| 725 | i2c-gpio,scl-open-drain; | 728 | i2c-gpio,scl-open-drain; |
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 347a74a857f6..4a5ee5cc115a 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | pinctrl@fffff400 { | 28 | pinctrl@fffff400 { |
| 29 | 1wire_cm { | 29 | 1wire_cm { |
| 30 | pinctrl_1wire_cm: 1wire_cm-0 { | 30 | pinctrl_1wire_cm: 1wire_cm-0 { |
| 31 | atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */ | 31 | atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */ |
| 32 | }; | 32 | }; |
| 33 | }; | 33 | }; |
| 34 | }; | 34 | }; |
| @@ -75,19 +75,19 @@ | |||
| 75 | 75 | ||
| 76 | pb18 { | 76 | pb18 { |
| 77 | label = "pb18"; | 77 | label = "pb18"; |
| 78 | gpios = <&pioB 18 1>; | 78 | gpios = <&pioB 18 GPIO_ACTIVE_LOW>; |
| 79 | linux,default-trigger = "heartbeat"; | 79 | linux,default-trigger = "heartbeat"; |
| 80 | }; | 80 | }; |
| 81 | 81 | ||
| 82 | pd21 { | 82 | pd21 { |
| 83 | label = "pd21"; | 83 | label = "pd21"; |
| 84 | gpios = <&pioD 21 0>; | 84 | gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; |
| 85 | }; | 85 | }; |
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | 1wire_cm { | 88 | 1wire_cm { |
| 89 | compatible = "w1-gpio"; | 89 | compatible = "w1-gpio"; |
| 90 | gpios = <&pioB 18 0>; | 90 | gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; |
| 91 | linux,open-drain; | 91 | linux,open-drain; |
| 92 | pinctrl-names = "default"; | 92 | pinctrl-names = "default"; |
| 93 | pinctrl-0 = <&pinctrl_1wire_cm>; | 93 | pinctrl-0 = <&pinctrl_1wire_cm>; |
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 1fa48d2bfd80..19c8ebb303f4 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * | 6 | * |
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /include/ "at91sam9x5cm.dtsi" | 9 | #include "at91sam9x5cm.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Atmel AT91SAM9X5-EK"; | 12 | model = "Atmel AT91SAM9X5-EK"; |
| @@ -27,7 +27,7 @@ | |||
| 27 | slot@0 { | 27 | slot@0 { |
| 28 | reg = <0>; | 28 | reg = <0>; |
| 29 | bus-width = <4>; | 29 | bus-width = <4>; |
| 30 | cd-gpios = <&pioD 15 0>; | 30 | cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; |
| 31 | }; | 31 | }; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| @@ -40,7 +40,7 @@ | |||
| 40 | slot@0 { | 40 | slot@0 { |
| 41 | reg = <0>; | 41 | reg = <0>; |
| 42 | bus-width = <4>; | 42 | bus-width = <4>; |
| 43 | cd-gpios = <&pioD 14 0>; | 43 | cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; |
| 44 | }; | 44 | }; |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| @@ -60,14 +60,14 @@ | |||
| 60 | mmc0 { | 60 | mmc0 { |
| 61 | pinctrl_board_mmc0: mmc0-board { | 61 | pinctrl_board_mmc0: mmc0-board { |
| 62 | atmel,pins = | 62 | atmel,pins = |
| 63 | <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */ | 63 | <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ |
| 64 | }; | 64 | }; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | mmc1 { | 67 | mmc1 { |
| 68 | pinctrl_board_mmc1: mmc1-board { | 68 | pinctrl_board_mmc1: mmc1-board { |
| 69 | atmel,pins = | 69 | atmel,pins = |
| 70 | <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */ | 70 | <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */ |
| 71 | }; | 71 | }; |
| 72 | }; | 72 | }; |
| 73 | }; | 73 | }; |
| @@ -86,8 +86,8 @@ | |||
| 86 | usb0: ohci@00600000 { | 86 | usb0: ohci@00600000 { |
| 87 | status = "okay"; | 87 | status = "okay"; |
| 88 | num-ports = <2>; | 88 | num-ports = <2>; |
| 89 | atmel,vbus-gpio = <&pioD 19 1 | 89 | atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW |
| 90 | &pioD 20 1 | 90 | &pioD 20 GPIO_ACTIVE_LOW |
| 91 | >; | 91 | >; |
| 92 | }; | 92 | }; |
| 93 | 93 | ||
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 1ea9d34460a4..143b6d25bc80 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9260.dtsi" | 9 | #include "at91sam9260.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Ethernut 5"; | 12 | model = "Ethernut 5"; |
| @@ -40,7 +40,7 @@ | |||
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | usb1: gadget@fffa4000 { | 42 | usb1: gadget@fffa4000 { |
| 43 | atmel,vbus-gpio = <&pioC 5 0>; | 43 | atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; |
| 44 | status = "okay"; | 44 | status = "okay"; |
| 45 | }; | 45 | }; |
| 46 | }; | 46 | }; |
| @@ -52,7 +52,7 @@ | |||
| 52 | status = "okay"; | 52 | status = "okay"; |
| 53 | 53 | ||
| 54 | gpios = <0 | 54 | gpios = <0 |
| 55 | &pioC 14 0 | 55 | &pioC 14 GPIO_ACTIVE_HIGH |
| 56 | 0 | 56 | 0 |
| 57 | >; | 57 | >; |
| 58 | 58 | ||
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index 96e50f569433..4d829685fdfb 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | /dts-v1/; | 10 | /dts-v1/; |
| 11 | 11 | ||
| 12 | /include/ "ge863-pro3.dtsi" | 12 | #include "ge863-pro3.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | model = "Telit EVK-PRO3 for Telit GE863-PRO3"; | 15 | model = "Telit EVK-PRO3 for Telit GE863-PRO3"; |
| @@ -31,7 +31,7 @@ | |||
| 31 | }; | 31 | }; |
| 32 | 32 | ||
| 33 | usb1: gadget@fffa4000 { | 33 | usb1: gadget@fffa4000 { |
| 34 | atmel,vbus-gpio = <&pioC 5 0>; | 34 | atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; |
| 35 | status = "okay"; | 35 | status = "okay"; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| @@ -50,4 +50,4 @@ | |||
| 50 | status = "okay"; | 50 | status = "okay"; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | }; \ No newline at end of file | 53 | }; |
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 17136fc7a516..230099bb31c8 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | /include/ "at91sam9260.dtsi" | 10 | #include "at91sam9260.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | clocks { | 13 | clocks { |
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts index b4dc3ed9a3ec..02df1914a47c 100644 --- a/arch/arm/boot/dts/kizbox.dts +++ b/arch/arm/boot/dts/kizbox.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9g20.dtsi" | 9 | #include "at91sam9g20.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | 12 | ||
| @@ -94,26 +94,26 @@ | |||
| 94 | 94 | ||
| 95 | led1g { | 95 | led1g { |
| 96 | label = "led1:green"; | 96 | label = "led1:green"; |
| 97 | gpios = <&pioB 0 1>; | 97 | gpios = <&pioB 0 GPIO_ACTIVE_LOW>; |
| 98 | linux,default-trigger = "none"; | 98 | linux,default-trigger = "none"; |
| 99 | }; | 99 | }; |
| 100 | 100 | ||
| 101 | led1r { | 101 | led1r { |
| 102 | label = "led1:red"; | 102 | label = "led1:red"; |
| 103 | gpios = <&pioB 1 1>; | 103 | gpios = <&pioB 1 GPIO_ACTIVE_LOW>; |
| 104 | linux,default-trigger = "none"; | 104 | linux,default-trigger = "none"; |
| 105 | }; | 105 | }; |
| 106 | 106 | ||
| 107 | led2g { | 107 | led2g { |
| 108 | label = "led2:green"; | 108 | label = "led2:green"; |
| 109 | gpios = <&pioB 2 1>; | 109 | gpios = <&pioB 2 GPIO_ACTIVE_LOW>; |
| 110 | linux,default-trigger = "none"; | 110 | linux,default-trigger = "none"; |
| 111 | default-state = "on"; | 111 | default-state = "on"; |
| 112 | }; | 112 | }; |
| 113 | 113 | ||
| 114 | led2r { | 114 | led2r { |
| 115 | label = "led2:red"; | 115 | label = "led2:red"; |
| 116 | gpios = <&pioB 3 1>; | 116 | gpios = <&pioB 3 GPIO_ACTIVE_LOW>; |
| 117 | linux,default-trigger = "none"; | 117 | linux,default-trigger = "none"; |
| 118 | }; | 118 | }; |
| 119 | }; | 119 | }; |
| @@ -125,16 +125,16 @@ | |||
| 125 | 125 | ||
| 126 | reset { | 126 | reset { |
| 127 | label = "reset"; | 127 | label = "reset"; |
| 128 | gpios = <&pioB 30 1>; | 128 | gpios = <&pioB 30 GPIO_ACTIVE_LOW>; |
| 129 | linux,code = <0x100>; | 129 | linux,code = <0x100>; |
| 130 | gpio-key,wakeup; | 130 | gpio-key,wakeup; |
| 131 | }; | 131 | }; |
| 132 | 132 | ||
| 133 | mode { | 133 | mode { |
| 134 | label = "mode"; | 134 | label = "mode"; |
| 135 | gpios = <&pioB 31 1>; | 135 | gpios = <&pioB 31 GPIO_ACTIVE_LOW>; |
| 136 | linux,code = <0x101>; | 136 | linux,code = <0x101>; |
| 137 | gpio-key,wakeup; | 137 | gpio-key,wakeup; |
| 138 | }; | 138 | }; |
| 139 | }; | 139 | }; |
| 140 | }; \ No newline at end of file | 140 | }; |
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index 317300875f34..ccf9ea242f72 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2 only | 6 | * Licensed under GPLv2 only |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91rm9200.dtsi" | 9 | #include "at91rm9200.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Phontech MPA 1600"; | 12 | model = "Phontech MPA 1600"; |
| @@ -62,7 +62,7 @@ | |||
| 62 | 62 | ||
| 63 | monitor_mute { | 63 | monitor_mute { |
| 64 | label = "Monitor mute"; | 64 | label = "Monitor mute"; |
| 65 | gpios = <&pioC 1 1>; | 65 | gpios = <&pioC 1 GPIO_ACTIVE_LOW>; |
| 66 | linux,code = <113>; | 66 | linux,code = <113>; |
| 67 | }; | 67 | }; |
| 68 | }; | 68 | }; |
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 9bf49b3826ea..cdc010e0f93e 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | < 0x02081000 0x1000 >; | 15 | < 0x02081000 0x1000 >; |
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | timer@2000004 { | 18 | timer@2000000 { |
| 19 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | 19 | compatible = "qcom,scss-timer", "qcom,msm-timer"; |
| 20 | interrupts = <1 0 0x301>, | 20 | interrupts = <1 0 0x301>, |
| 21 | <1 1 0x301>, | 21 | <1 1 0x301>, |
| @@ -26,7 +26,18 @@ | |||
| 26 | cpu-offset = <0x40000>; | 26 | cpu-offset = <0x40000>; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | serial@19c400000 { | 29 | msmgpio: gpio@800000 { |
| 30 | compatible = "qcom,msm-gpio"; | ||
| 31 | reg = <0x00800000 0x1000>; | ||
| 32 | gpio-controller; | ||
| 33 | #gpio-cells = <2>; | ||
| 34 | ngpio = <173>; | ||
| 35 | interrupts = <0 32 0x4>; | ||
| 36 | interrupt-controller; | ||
| 37 | #interrupt-cells = <2>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | serial@19c40000 { | ||
| 30 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; | 41 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; |
| 31 | reg = <0x19c40000 0x1000>, | 42 | reg = <0x19c40000 0x1000>, |
| 32 | <0x19c00000 0x1000>; | 43 | <0x19c00000 0x1000>; |
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index 2e4d87a125d6..db2060c46540 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts | |||
| @@ -26,7 +26,18 @@ | |||
| 26 | cpu-offset = <0x80000>; | 26 | cpu-offset = <0x80000>; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | serial@19c400000 { | 29 | msmgpio: gpio@fd510000 { |
| 30 | compatible = "qcom,msm-gpio"; | ||
| 31 | gpio-controller; | ||
| 32 | #gpio-cells = <2>; | ||
| 33 | ngpio = <150>; | ||
| 34 | interrupts = <0 32 0x4>; | ||
| 35 | interrupt-controller; | ||
| 36 | #interrupt-cells = <2>; | ||
| 37 | reg = <0xfd510000 0x4000>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | serial@16440000 { | ||
| 30 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; | 41 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; |
| 31 | reg = <0x16440000 0x1000>, | 42 | reg = <0x16440000 0x1000>, |
| 32 | <0x16400000 0x1000>; | 43 | <0x16400000 0x1000>; |
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 387fedb58988..33ffabe9c4c8 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9g45.dtsi" | 9 | #include "at91sam9g45.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Ronetix pm9g45"; | 12 | model = "Ronetix pm9g45"; |
| @@ -42,15 +42,15 @@ | |||
| 42 | board { | 42 | board { |
| 43 | pinctrl_board_nand: nand0-board { | 43 | pinctrl_board_nand: nand0-board { |
| 44 | atmel,pins = | 44 | atmel,pins = |
| 45 | <3 3 0x0 0x1 /* PD3 gpio RDY pin pull_up*/ | 45 | <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD3 gpio RDY pin pull_up*/ |
| 46 | 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ | 46 | AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ |
| 47 | }; | 47 | }; |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | mmc { | 50 | mmc { |
| 51 | pinctrl_board_mmc: mmc0-board { | 51 | pinctrl_board_mmc: mmc0-board { |
| 52 | atmel,pins = | 52 | atmel,pins = |
| 53 | <3 6 0x0 0x5>; /* PD6 gpio CD pin pull_up and deglitch */ | 53 | <AT91_PIOD 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD6 gpio CD pin pull_up and deglitch */ |
| 54 | }; | 54 | }; |
| 55 | }; | 55 | }; |
| 56 | }; | 56 | }; |
| @@ -64,7 +64,7 @@ | |||
| 64 | slot@0 { | 64 | slot@0 { |
| 65 | reg = <0>; | 65 | reg = <0>; |
| 66 | bus-width = <4>; | 66 | bus-width = <4>; |
| 67 | cd-gpios = <&pioD 6 0>; | 67 | cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; |
| 68 | }; | 68 | }; |
| 69 | }; | 69 | }; |
| 70 | 70 | ||
| @@ -81,8 +81,8 @@ | |||
| 81 | nand-on-flash-bbt; | 81 | nand-on-flash-bbt; |
| 82 | pinctrl-0 = <&pinctrl_board_nand>; | 82 | pinctrl-0 = <&pinctrl_board_nand>; |
| 83 | 83 | ||
| 84 | gpios = <&pioD 3 0 | 84 | gpios = <&pioD 3 GPIO_ACTIVE_HIGH |
| 85 | &pioC 14 0 | 85 | &pioC 14 GPIO_ACTIVE_HIGH |
| 86 | 0 | 86 | 0 |
| 87 | >; | 87 | >; |
| 88 | 88 | ||
| @@ -134,13 +134,13 @@ | |||
| 134 | 134 | ||
| 135 | led0 { | 135 | led0 { |
| 136 | label = "led0"; | 136 | label = "led0"; |
| 137 | gpios = <&pioD 0 1>; | 137 | gpios = <&pioD 0 GPIO_ACTIVE_LOW>; |
| 138 | linux,default-trigger = "nand-disk"; | 138 | linux,default-trigger = "nand-disk"; |
| 139 | }; | 139 | }; |
| 140 | 140 | ||
| 141 | led1 { | 141 | led1 { |
| 142 | label = "led1"; | 142 | label = "led1"; |
| 143 | gpios = <&pioD 31 0>; | 143 | gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; |
| 144 | linux,default-trigger = "heartbeat"; | 144 | linux,default-trigger = "heartbeat"; |
| 145 | }; | 145 | }; |
| 146 | }; | 146 | }; |
| @@ -152,13 +152,13 @@ | |||
| 152 | 152 | ||
| 153 | right { | 153 | right { |
| 154 | label = "SW4"; | 154 | label = "SW4"; |
| 155 | gpios = <&pioE 7 1>; | 155 | gpios = <&pioE 7 GPIO_ACTIVE_LOW>; |
| 156 | linux,code = <106>; | 156 | linux,code = <106>; |
| 157 | }; | 157 | }; |
| 158 | 158 | ||
| 159 | up { | 159 | up { |
| 160 | label = "SW3"; | 160 | label = "SW3"; |
| 161 | gpios = <&pioE 8 1>; | 161 | gpios = <&pioE 8 GPIO_ACTIVE_LOW>; |
| 162 | linux,code = <103>; | 162 | linux,code = <103>; |
| 163 | }; | 163 | }; |
| 164 | }; | 164 | }; |
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5000e0d42849..d5922935523f 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -8,7 +8,10 @@ | |||
| 8 | * Licensed under GPLv2 or later. | 8 | * Licensed under GPLv2 or later. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "skeleton.dtsi" | 11 | #include "skeleton.dtsi" |
| 12 | #include <dt-bindings/pinctrl/at91.h> | ||
| 13 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 14 | #include <dt-bindings/gpio/gpio.h> | ||
| 12 | 15 | ||
| 13 | / { | 16 | / { |
| 14 | model = "Atmel SAMA5D3 family SoC"; | 17 | model = "Atmel SAMA5D3 family SoC"; |
| @@ -59,7 +62,7 @@ | |||
| 59 | mmc0: mmc@f0000000 { | 62 | mmc0: mmc@f0000000 { |
| 60 | compatible = "atmel,hsmci"; | 63 | compatible = "atmel,hsmci"; |
| 61 | reg = <0xf0000000 0x600>; | 64 | reg = <0xf0000000 0x600>; |
| 62 | interrupts = <21 4 0>; | 65 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
| 63 | dmas = <&dma0 2 0>; | 66 | dmas = <&dma0 2 0>; |
| 64 | dma-names = "rxtx"; | 67 | dma-names = "rxtx"; |
| 65 | pinctrl-names = "default"; | 68 | pinctrl-names = "default"; |
| @@ -74,7 +77,7 @@ | |||
| 74 | #size-cells = <0>; | 77 | #size-cells = <0>; |
| 75 | compatible = "atmel,at91sam9x5-spi"; | 78 | compatible = "atmel,at91sam9x5-spi"; |
| 76 | reg = <0xf0004000 0x100>; | 79 | reg = <0xf0004000 0x100>; |
| 77 | interrupts = <24 4 3>; | 80 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
| 78 | pinctrl-names = "default"; | 81 | pinctrl-names = "default"; |
| 79 | pinctrl-0 = <&pinctrl_spi0>; | 82 | pinctrl-0 = <&pinctrl_spi0>; |
| 80 | status = "disabled"; | 83 | status = "disabled"; |
| @@ -83,7 +86,7 @@ | |||
| 83 | ssc0: ssc@f0008000 { | 86 | ssc0: ssc@f0008000 { |
| 84 | compatible = "atmel,at91sam9g45-ssc"; | 87 | compatible = "atmel,at91sam9g45-ssc"; |
| 85 | reg = <0xf0008000 0x4000>; | 88 | reg = <0xf0008000 0x4000>; |
| 86 | interrupts = <38 4 4>; | 89 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
| 87 | pinctrl-names = "default"; | 90 | pinctrl-names = "default"; |
| 88 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 91 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 89 | status = "disabled"; | 92 | status = "disabled"; |
| @@ -92,7 +95,7 @@ | |||
| 92 | can0: can@f000c000 { | 95 | can0: can@f000c000 { |
| 93 | compatible = "atmel,at91sam9x5-can"; | 96 | compatible = "atmel,at91sam9x5-can"; |
| 94 | reg = <0xf000c000 0x300>; | 97 | reg = <0xf000c000 0x300>; |
| 95 | interrupts = <40 4 3>; | 98 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; |
| 96 | pinctrl-names = "default"; | 99 | pinctrl-names = "default"; |
| 97 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | 100 | pinctrl-0 = <&pinctrl_can0_rx_tx>; |
| 98 | status = "disabled"; | 101 | status = "disabled"; |
| @@ -101,13 +104,13 @@ | |||
| 101 | tcb0: timer@f0010000 { | 104 | tcb0: timer@f0010000 { |
| 102 | compatible = "atmel,at91sam9x5-tcb"; | 105 | compatible = "atmel,at91sam9x5-tcb"; |
| 103 | reg = <0xf0010000 0x100>; | 106 | reg = <0xf0010000 0x100>; |
| 104 | interrupts = <26 4 0>; | 107 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
| 105 | }; | 108 | }; |
| 106 | 109 | ||
| 107 | i2c0: i2c@f0014000 { | 110 | i2c0: i2c@f0014000 { |
| 108 | compatible = "atmel,at91sam9x5-i2c"; | 111 | compatible = "atmel,at91sam9x5-i2c"; |
| 109 | reg = <0xf0014000 0x4000>; | 112 | reg = <0xf0014000 0x4000>; |
| 110 | interrupts = <18 4 6>; | 113 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; |
| 111 | dmas = <&dma0 2 7>, | 114 | dmas = <&dma0 2 7>, |
| 112 | <&dma0 2 8>; | 115 | <&dma0 2 8>; |
| 113 | dma-names = "tx", "rx"; | 116 | dma-names = "tx", "rx"; |
| @@ -121,7 +124,7 @@ | |||
| 121 | i2c1: i2c@f0018000 { | 124 | i2c1: i2c@f0018000 { |
| 122 | compatible = "atmel,at91sam9x5-i2c"; | 125 | compatible = "atmel,at91sam9x5-i2c"; |
| 123 | reg = <0xf0018000 0x4000>; | 126 | reg = <0xf0018000 0x4000>; |
| 124 | interrupts = <19 4 6>; | 127 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; |
| 125 | dmas = <&dma0 2 9>, | 128 | dmas = <&dma0 2 9>, |
| 126 | <&dma0 2 10>; | 129 | <&dma0 2 10>; |
| 127 | dma-names = "tx", "rx"; | 130 | dma-names = "tx", "rx"; |
| @@ -135,7 +138,7 @@ | |||
| 135 | usart0: serial@f001c000 { | 138 | usart0: serial@f001c000 { |
| 136 | compatible = "atmel,at91sam9260-usart"; | 139 | compatible = "atmel,at91sam9260-usart"; |
| 137 | reg = <0xf001c000 0x100>; | 140 | reg = <0xf001c000 0x100>; |
| 138 | interrupts = <12 4 5>; | 141 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; |
| 139 | pinctrl-names = "default"; | 142 | pinctrl-names = "default"; |
| 140 | pinctrl-0 = <&pinctrl_usart0>; | 143 | pinctrl-0 = <&pinctrl_usart0>; |
| 141 | status = "disabled"; | 144 | status = "disabled"; |
| @@ -144,7 +147,7 @@ | |||
| 144 | usart1: serial@f0020000 { | 147 | usart1: serial@f0020000 { |
| 145 | compatible = "atmel,at91sam9260-usart"; | 148 | compatible = "atmel,at91sam9260-usart"; |
| 146 | reg = <0xf0020000 0x100>; | 149 | reg = <0xf0020000 0x100>; |
| 147 | interrupts = <13 4 5>; | 150 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; |
| 148 | pinctrl-names = "default"; | 151 | pinctrl-names = "default"; |
| 149 | pinctrl-0 = <&pinctrl_usart1>; | 152 | pinctrl-0 = <&pinctrl_usart1>; |
| 150 | status = "disabled"; | 153 | status = "disabled"; |
| @@ -153,7 +156,7 @@ | |||
| 153 | macb0: ethernet@f0028000 { | 156 | macb0: ethernet@f0028000 { |
| 154 | compatible = "cdns,pc302-gem", "cdns,gem"; | 157 | compatible = "cdns,pc302-gem", "cdns,gem"; |
| 155 | reg = <0xf0028000 0x100>; | 158 | reg = <0xf0028000 0x100>; |
| 156 | interrupts = <34 4 3>; | 159 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; |
| 157 | pinctrl-names = "default"; | 160 | pinctrl-names = "default"; |
| 158 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | 161 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; |
| 159 | status = "disabled"; | 162 | status = "disabled"; |
| @@ -162,14 +165,14 @@ | |||
| 162 | isi: isi@f0034000 { | 165 | isi: isi@f0034000 { |
| 163 | compatible = "atmel,at91sam9g45-isi"; | 166 | compatible = "atmel,at91sam9g45-isi"; |
| 164 | reg = <0xf0034000 0x4000>; | 167 | reg = <0xf0034000 0x4000>; |
| 165 | interrupts = <37 4 5>; | 168 | interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; |
| 166 | status = "disabled"; | 169 | status = "disabled"; |
| 167 | }; | 170 | }; |
| 168 | 171 | ||
| 169 | mmc1: mmc@f8000000 { | 172 | mmc1: mmc@f8000000 { |
| 170 | compatible = "atmel,hsmci"; | 173 | compatible = "atmel,hsmci"; |
| 171 | reg = <0xf8000000 0x600>; | 174 | reg = <0xf8000000 0x600>; |
| 172 | interrupts = <22 4 0>; | 175 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; |
| 173 | dmas = <&dma1 2 0>; | 176 | dmas = <&dma1 2 0>; |
| 174 | dma-names = "rxtx"; | 177 | dma-names = "rxtx"; |
| 175 | pinctrl-names = "default"; | 178 | pinctrl-names = "default"; |
| @@ -182,7 +185,7 @@ | |||
| 182 | mmc2: mmc@f8004000 { | 185 | mmc2: mmc@f8004000 { |
| 183 | compatible = "atmel,hsmci"; | 186 | compatible = "atmel,hsmci"; |
| 184 | reg = <0xf8004000 0x600>; | 187 | reg = <0xf8004000 0x600>; |
| 185 | interrupts = <23 4 0>; | 188 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; |
| 186 | dmas = <&dma1 2 1>; | 189 | dmas = <&dma1 2 1>; |
| 187 | dma-names = "rxtx"; | 190 | dma-names = "rxtx"; |
| 188 | pinctrl-names = "default"; | 191 | pinctrl-names = "default"; |
| @@ -197,7 +200,7 @@ | |||
| 197 | #size-cells = <0>; | 200 | #size-cells = <0>; |
| 198 | compatible = "atmel,at91sam9x5-spi"; | 201 | compatible = "atmel,at91sam9x5-spi"; |
| 199 | reg = <0xf8008000 0x100>; | 202 | reg = <0xf8008000 0x100>; |
| 200 | interrupts = <25 4 3>; | 203 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
| 201 | pinctrl-names = "default"; | 204 | pinctrl-names = "default"; |
| 202 | pinctrl-0 = <&pinctrl_spi1>; | 205 | pinctrl-0 = <&pinctrl_spi1>; |
| 203 | status = "disabled"; | 206 | status = "disabled"; |
| @@ -206,7 +209,7 @@ | |||
| 206 | ssc1: ssc@f800c000 { | 209 | ssc1: ssc@f800c000 { |
| 207 | compatible = "atmel,at91sam9g45-ssc"; | 210 | compatible = "atmel,at91sam9g45-ssc"; |
| 208 | reg = <0xf800c000 0x4000>; | 211 | reg = <0xf800c000 0x4000>; |
| 209 | interrupts = <39 4 4>; | 212 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
| 210 | pinctrl-names = "default"; | 213 | pinctrl-names = "default"; |
| 211 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 214 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 212 | status = "disabled"; | 215 | status = "disabled"; |
| @@ -215,7 +218,7 @@ | |||
| 215 | can1: can@f8010000 { | 218 | can1: can@f8010000 { |
| 216 | compatible = "atmel,at91sam9x5-can"; | 219 | compatible = "atmel,at91sam9x5-can"; |
| 217 | reg = <0xf8010000 0x300>; | 220 | reg = <0xf8010000 0x300>; |
| 218 | interrupts = <41 4 3>; | 221 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; |
| 219 | pinctrl-names = "default"; | 222 | pinctrl-names = "default"; |
| 220 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | 223 | pinctrl-0 = <&pinctrl_can1_rx_tx>; |
| 221 | }; | 224 | }; |
| @@ -223,13 +226,13 @@ | |||
| 223 | tcb1: timer@f8014000 { | 226 | tcb1: timer@f8014000 { |
| 224 | compatible = "atmel,at91sam9x5-tcb"; | 227 | compatible = "atmel,at91sam9x5-tcb"; |
| 225 | reg = <0xf8014000 0x100>; | 228 | reg = <0xf8014000 0x100>; |
| 226 | interrupts = <27 4 0>; | 229 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; |
| 227 | }; | 230 | }; |
| 228 | 231 | ||
| 229 | adc0: adc@f8018000 { | 232 | adc0: adc@f8018000 { |
| 230 | compatible = "atmel,at91sam9260-adc"; | 233 | compatible = "atmel,at91sam9260-adc"; |
| 231 | reg = <0xf8018000 0x100>; | 234 | reg = <0xf8018000 0x100>; |
| 232 | interrupts = <29 4 5>; | 235 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
| 233 | pinctrl-names = "default"; | 236 | pinctrl-names = "default"; |
| 234 | pinctrl-0 = < | 237 | pinctrl-0 = < |
| 235 | &pinctrl_adc0_adtrg | 238 | &pinctrl_adc0_adtrg |
| @@ -283,7 +286,7 @@ | |||
| 283 | tsadcc: tsadcc@f8018000 { | 286 | tsadcc: tsadcc@f8018000 { |
| 284 | compatible = "atmel,at91sam9x5-tsadcc"; | 287 | compatible = "atmel,at91sam9x5-tsadcc"; |
| 285 | reg = <0xf8018000 0x4000>; | 288 | reg = <0xf8018000 0x4000>; |
| 286 | interrupts = <29 4 5>; | 289 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
| 287 | atmel,tsadcc_clock = <300000>; | 290 | atmel,tsadcc_clock = <300000>; |
| 288 | atmel,filtering_average = <0x03>; | 291 | atmel,filtering_average = <0x03>; |
| 289 | atmel,pendet_debounce = <0x08>; | 292 | atmel,pendet_debounce = <0x08>; |
| @@ -295,7 +298,7 @@ | |||
| 295 | i2c2: i2c@f801c000 { | 298 | i2c2: i2c@f801c000 { |
| 296 | compatible = "atmel,at91sam9x5-i2c"; | 299 | compatible = "atmel,at91sam9x5-i2c"; |
| 297 | reg = <0xf801c000 0x4000>; | 300 | reg = <0xf801c000 0x4000>; |
| 298 | interrupts = <20 4 6>; | 301 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; |
| 299 | dmas = <&dma1 2 11>, | 302 | dmas = <&dma1 2 11>, |
| 300 | <&dma1 2 12>; | 303 | <&dma1 2 12>; |
| 301 | dma-names = "tx", "rx"; | 304 | dma-names = "tx", "rx"; |
| @@ -307,7 +310,7 @@ | |||
| 307 | usart2: serial@f8020000 { | 310 | usart2: serial@f8020000 { |
| 308 | compatible = "atmel,at91sam9260-usart"; | 311 | compatible = "atmel,at91sam9260-usart"; |
| 309 | reg = <0xf8020000 0x100>; | 312 | reg = <0xf8020000 0x100>; |
| 310 | interrupts = <14 4 5>; | 313 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 311 | pinctrl-names = "default"; | 314 | pinctrl-names = "default"; |
| 312 | pinctrl-0 = <&pinctrl_usart2>; | 315 | pinctrl-0 = <&pinctrl_usart2>; |
| 313 | status = "disabled"; | 316 | status = "disabled"; |
| @@ -316,7 +319,7 @@ | |||
| 316 | usart3: serial@f8024000 { | 319 | usart3: serial@f8024000 { |
| 317 | compatible = "atmel,at91sam9260-usart"; | 320 | compatible = "atmel,at91sam9260-usart"; |
| 318 | reg = <0xf8024000 0x100>; | 321 | reg = <0xf8024000 0x100>; |
| 319 | interrupts = <15 4 5>; | 322 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 320 | pinctrl-names = "default"; | 323 | pinctrl-names = "default"; |
| 321 | pinctrl-0 = <&pinctrl_usart3>; | 324 | pinctrl-0 = <&pinctrl_usart3>; |
| 322 | status = "disabled"; | 325 | status = "disabled"; |
| @@ -325,7 +328,7 @@ | |||
| 325 | macb1: ethernet@f802c000 { | 328 | macb1: ethernet@f802c000 { |
| 326 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 329 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 327 | reg = <0xf802c000 0x100>; | 330 | reg = <0xf802c000 0x100>; |
| 328 | interrupts = <35 4 3>; | 331 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; |
| 329 | pinctrl-names = "default"; | 332 | pinctrl-names = "default"; |
| 330 | pinctrl-0 = <&pinctrl_macb1_rmii>; | 333 | pinctrl-0 = <&pinctrl_macb1_rmii>; |
| 331 | status = "disabled"; | 334 | status = "disabled"; |
| @@ -334,7 +337,7 @@ | |||
| 334 | sha@f8034000 { | 337 | sha@f8034000 { |
| 335 | compatible = "atmel,sam9g46-sha"; | 338 | compatible = "atmel,sam9g46-sha"; |
| 336 | reg = <0xf8034000 0x100>; | 339 | reg = <0xf8034000 0x100>; |
| 337 | interrupts = <42 4 0>; | 340 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; |
| 338 | }; | 341 | }; |
| 339 | 342 | ||
| 340 | aes@f8038000 { | 343 | aes@f8038000 { |
| @@ -346,20 +349,20 @@ | |||
| 346 | tdes@f803c000 { | 349 | tdes@f803c000 { |
| 347 | compatible = "atmel,sam9g46-tdes"; | 350 | compatible = "atmel,sam9g46-tdes"; |
| 348 | reg = <0xf803c000 0x100>; | 351 | reg = <0xf803c000 0x100>; |
| 349 | interrupts = <44 4 0>; | 352 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; |
| 350 | }; | 353 | }; |
| 351 | 354 | ||
| 352 | dma0: dma-controller@ffffe600 { | 355 | dma0: dma-controller@ffffe600 { |
| 353 | compatible = "atmel,at91sam9g45-dma"; | 356 | compatible = "atmel,at91sam9g45-dma"; |
| 354 | reg = <0xffffe600 0x200>; | 357 | reg = <0xffffe600 0x200>; |
| 355 | interrupts = <30 4 0>; | 358 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; |
| 356 | #dma-cells = <2>; | 359 | #dma-cells = <2>; |
| 357 | }; | 360 | }; |
| 358 | 361 | ||
| 359 | dma1: dma-controller@ffffe800 { | 362 | dma1: dma-controller@ffffe800 { |
| 360 | compatible = "atmel,at91sam9g45-dma"; | 363 | compatible = "atmel,at91sam9g45-dma"; |
| 361 | reg = <0xffffe800 0x200>; | 364 | reg = <0xffffe800 0x200>; |
| 362 | interrupts = <31 4 0>; | 365 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
| 363 | #dma-cells = <2>; | 366 | #dma-cells = <2>; |
| 364 | }; | 367 | }; |
| 365 | 368 | ||
| @@ -371,7 +374,7 @@ | |||
| 371 | dbgu: serial@ffffee00 { | 374 | dbgu: serial@ffffee00 { |
| 372 | compatible = "atmel,at91sam9260-usart"; | 375 | compatible = "atmel,at91sam9260-usart"; |
| 373 | reg = <0xffffee00 0x200>; | 376 | reg = <0xffffee00 0x200>; |
| 374 | interrupts = <2 4 7>; | 377 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; |
| 375 | pinctrl-names = "default"; | 378 | pinctrl-names = "default"; |
| 376 | pinctrl-0 = <&pinctrl_dbgu>; | 379 | pinctrl-0 = <&pinctrl_dbgu>; |
| 377 | status = "disabled"; | 380 | status = "disabled"; |
| @@ -403,202 +406,202 @@ | |||
| 403 | adc0 { | 406 | adc0 { |
| 404 | pinctrl_adc0_adtrg: adc0_adtrg { | 407 | pinctrl_adc0_adtrg: adc0_adtrg { |
| 405 | atmel,pins = | 408 | atmel,pins = |
| 406 | <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ | 409 | <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ |
| 407 | }; | 410 | }; |
| 408 | pinctrl_adc0_ad0: adc0_ad0 { | 411 | pinctrl_adc0_ad0: adc0_ad0 { |
| 409 | atmel,pins = | 412 | atmel,pins = |
| 410 | <3 20 0x1 0x0>; /* PD20 periph A AD0 */ | 413 | <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ |
| 411 | }; | 414 | }; |
| 412 | pinctrl_adc0_ad1: adc0_ad1 { | 415 | pinctrl_adc0_ad1: adc0_ad1 { |
| 413 | atmel,pins = | 416 | atmel,pins = |
| 414 | <3 21 0x1 0x0>; /* PD21 periph A AD1 */ | 417 | <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ |
| 415 | }; | 418 | }; |
| 416 | pinctrl_adc0_ad2: adc0_ad2 { | 419 | pinctrl_adc0_ad2: adc0_ad2 { |
| 417 | atmel,pins = | 420 | atmel,pins = |
| 418 | <3 22 0x1 0x0>; /* PD22 periph A AD2 */ | 421 | <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ |
| 419 | }; | 422 | }; |
| 420 | pinctrl_adc0_ad3: adc0_ad3 { | 423 | pinctrl_adc0_ad3: adc0_ad3 { |
| 421 | atmel,pins = | 424 | atmel,pins = |
| 422 | <3 23 0x1 0x0>; /* PD23 periph A AD3 */ | 425 | <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ |
| 423 | }; | 426 | }; |
| 424 | pinctrl_adc0_ad4: adc0_ad4 { | 427 | pinctrl_adc0_ad4: adc0_ad4 { |
| 425 | atmel,pins = | 428 | atmel,pins = |
| 426 | <3 24 0x1 0x0>; /* PD24 periph A AD4 */ | 429 | <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ |
| 427 | }; | 430 | }; |
| 428 | pinctrl_adc0_ad5: adc0_ad5 { | 431 | pinctrl_adc0_ad5: adc0_ad5 { |
| 429 | atmel,pins = | 432 | atmel,pins = |
| 430 | <3 25 0x1 0x0>; /* PD25 periph A AD5 */ | 433 | <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ |
| 431 | }; | 434 | }; |
| 432 | pinctrl_adc0_ad6: adc0_ad6 { | 435 | pinctrl_adc0_ad6: adc0_ad6 { |
| 433 | atmel,pins = | 436 | atmel,pins = |
| 434 | <3 26 0x1 0x0>; /* PD26 periph A AD6 */ | 437 | <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ |
| 435 | }; | 438 | }; |
| 436 | pinctrl_adc0_ad7: adc0_ad7 { | 439 | pinctrl_adc0_ad7: adc0_ad7 { |
| 437 | atmel,pins = | 440 | atmel,pins = |
| 438 | <3 27 0x1 0x0>; /* PD27 periph A AD7 */ | 441 | <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ |
| 439 | }; | 442 | }; |
| 440 | pinctrl_adc0_ad8: adc0_ad8 { | 443 | pinctrl_adc0_ad8: adc0_ad8 { |
| 441 | atmel,pins = | 444 | atmel,pins = |
| 442 | <3 28 0x1 0x0>; /* PD28 periph A AD8 */ | 445 | <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ |
| 443 | }; | 446 | }; |
| 444 | pinctrl_adc0_ad9: adc0_ad9 { | 447 | pinctrl_adc0_ad9: adc0_ad9 { |
| 445 | atmel,pins = | 448 | atmel,pins = |
| 446 | <3 29 0x1 0x0>; /* PD29 periph A AD9 */ | 449 | <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ |
| 447 | }; | 450 | }; |
| 448 | pinctrl_adc0_ad10: adc0_ad10 { | 451 | pinctrl_adc0_ad10: adc0_ad10 { |
| 449 | atmel,pins = | 452 | atmel,pins = |
| 450 | <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ | 453 | <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ |
| 451 | }; | 454 | }; |
| 452 | pinctrl_adc0_ad11: adc0_ad11 { | 455 | pinctrl_adc0_ad11: adc0_ad11 { |
| 453 | atmel,pins = | 456 | atmel,pins = |
| 454 | <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ | 457 | <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ |
| 455 | }; | 458 | }; |
| 456 | }; | 459 | }; |
| 457 | 460 | ||
| 458 | can0 { | 461 | can0 { |
| 459 | pinctrl_can0_rx_tx: can0_rx_tx { | 462 | pinctrl_can0_rx_tx: can0_rx_tx { |
| 460 | atmel,pins = | 463 | atmel,pins = |
| 461 | <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ | 464 | <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ |
| 462 | 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ | 465 | AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ |
| 463 | }; | 466 | }; |
| 464 | }; | 467 | }; |
| 465 | 468 | ||
| 466 | can1 { | 469 | can1 { |
| 467 | pinctrl_can1_rx_tx: can1_rx_tx { | 470 | pinctrl_can1_rx_tx: can1_rx_tx { |
| 468 | atmel,pins = | 471 | atmel,pins = |
| 469 | <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ | 472 | <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ |
| 470 | 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ | 473 | AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ |
| 471 | }; | 474 | }; |
| 472 | }; | 475 | }; |
| 473 | 476 | ||
| 474 | dbgu { | 477 | dbgu { |
| 475 | pinctrl_dbgu: dbgu-0 { | 478 | pinctrl_dbgu: dbgu-0 { |
| 476 | atmel,pins = | 479 | atmel,pins = |
| 477 | <1 30 0x1 0x0 /* PB30 periph A */ | 480 | <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ |
| 478 | 1 31 0x1 0x1>; /* PB31 periph A with pullup */ | 481 | AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ |
| 479 | }; | 482 | }; |
| 480 | }; | 483 | }; |
| 481 | 484 | ||
| 482 | i2c0 { | 485 | i2c0 { |
| 483 | pinctrl_i2c0: i2c0-0 { | 486 | pinctrl_i2c0: i2c0-0 { |
| 484 | atmel,pins = | 487 | atmel,pins = |
| 485 | <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ | 488 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ |
| 486 | 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | 489 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ |
| 487 | }; | 490 | }; |
| 488 | }; | 491 | }; |
| 489 | 492 | ||
| 490 | i2c1 { | 493 | i2c1 { |
| 491 | pinctrl_i2c1: i2c1-0 { | 494 | pinctrl_i2c1: i2c1-0 { |
| 492 | atmel,pins = | 495 | atmel,pins = |
| 493 | <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ | 496 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ |
| 494 | 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | 497 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ |
| 495 | }; | 498 | }; |
| 496 | }; | 499 | }; |
| 497 | 500 | ||
| 498 | isi { | 501 | isi { |
| 499 | pinctrl_isi: isi-0 { | 502 | pinctrl_isi: isi-0 { |
| 500 | atmel,pins = | 503 | atmel,pins = |
| 501 | <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ | 504 | <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ |
| 502 | 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | 505 | AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ |
| 503 | 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | 506 | AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ |
| 504 | 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | 507 | AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ |
| 505 | 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | 508 | AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ |
| 506 | 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | 509 | AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ |
| 507 | 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | 510 | AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ |
| 508 | 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | 511 | AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ |
| 509 | 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | 512 | AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ |
| 510 | 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | 513 | AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ |
| 511 | 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | 514 | AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ |
| 512 | 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | 515 | AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ |
| 513 | 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | 516 | AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ |
| 514 | }; | 517 | }; |
| 515 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | 518 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { |
| 516 | atmel,pins = | 519 | atmel,pins = |
| 517 | <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ | 520 | <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ |
| 518 | }; | 521 | }; |
| 519 | }; | 522 | }; |
| 520 | 523 | ||
| 521 | lcd { | 524 | lcd { |
| 522 | pinctrl_lcd: lcd-0 { | 525 | pinctrl_lcd: lcd-0 { |
| 523 | atmel,pins = | 526 | atmel,pins = |
| 524 | <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ | 527 | <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ |
| 525 | 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ | 528 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ |
| 526 | 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ | 529 | AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ |
| 527 | 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ | 530 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ |
| 528 | 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ | 531 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ |
| 529 | 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ | 532 | AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ |
| 530 | 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ | 533 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ |
| 531 | 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ | 534 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ |
| 532 | 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ | 535 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ |
| 533 | 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ | 536 | AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ |
| 534 | 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ | 537 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ |
| 535 | 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ | 538 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ |
| 536 | 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ | 539 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ |
| 537 | 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ | 540 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ |
| 538 | 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ | 541 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ |
| 539 | 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ | 542 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ |
| 540 | 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ | 543 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ |
| 541 | 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ | 544 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ |
| 542 | 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ | 545 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ |
| 543 | 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ | 546 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ |
| 544 | 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ | 547 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ |
| 545 | 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ | 548 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ |
| 546 | 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ | 549 | AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ |
| 547 | 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ | 550 | AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ |
| 548 | 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ | 551 | AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ |
| 549 | 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ | 552 | AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ |
| 550 | 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ | 553 | AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ |
| 551 | 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ | 554 | AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ |
| 552 | 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ | 555 | AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ |
| 553 | 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ | 556 | AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ |
| 554 | }; | 557 | }; |
| 555 | }; | 558 | }; |
| 556 | 559 | ||
| 557 | macb0 { | 560 | macb0 { |
| 558 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { | 561 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { |
| 559 | atmel,pins = | 562 | atmel,pins = |
| 560 | <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ | 563 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ |
| 561 | 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ | 564 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ |
| 562 | 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ | 565 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ |
| 563 | 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ | 566 | AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ |
| 564 | 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ | 567 | AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ |
| 565 | 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ | 568 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ |
| 566 | 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ | 569 | AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ |
| 567 | 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ | 570 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ |
| 568 | }; | 571 | }; |
| 569 | pinctrl_macb0_data_gmii: macb0_data_gmii { | 572 | pinctrl_macb0_data_gmii: macb0_data_gmii { |
| 570 | atmel,pins = | 573 | atmel,pins = |
| 571 | <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ | 574 | <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ |
| 572 | 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ | 575 | AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ |
| 573 | 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ | 576 | AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ |
| 574 | 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ | 577 | AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ |
| 575 | 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ | 578 | AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ |
| 576 | 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ | 579 | AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ |
| 577 | 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ | 580 | AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ |
| 578 | 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ | 581 | AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ |
| 579 | }; | 582 | }; |
| 580 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { | 583 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { |
| 581 | atmel,pins = | 584 | atmel,pins = |
| 582 | <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ | 585 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ |
| 583 | 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | 586 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ |
| 584 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | 587 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ |
| 585 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | 588 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ |
| 586 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | 589 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ |
| 587 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | 590 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ |
| 588 | 1 18 0x1 0x0>; /* PB18 periph A G125CK */ | 591 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ |
| 589 | }; | 592 | }; |
| 590 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { | 593 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { |
| 591 | atmel,pins = | 594 | atmel,pins = |
| 592 | <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | 595 | <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ |
| 593 | 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ | 596 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ |
| 594 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | 597 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ |
| 595 | 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ | 598 | AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ |
| 596 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | 599 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ |
| 597 | 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ | 600 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ |
| 598 | 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ | 601 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ |
| 599 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | 602 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ |
| 600 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | 603 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ |
| 601 | 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ | 604 | AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ |
| 602 | }; | 605 | }; |
| 603 | 606 | ||
| 604 | }; | 607 | }; |
| @@ -606,252 +609,251 @@ | |||
| 606 | macb1 { | 609 | macb1 { |
| 607 | pinctrl_macb1_rmii: macb1_rmii-0 { | 610 | pinctrl_macb1_rmii: macb1_rmii-0 { |
| 608 | atmel,pins = | 611 | atmel,pins = |
| 609 | <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ | 612 | <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ |
| 610 | 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ | 613 | AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ |
| 611 | 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ | 614 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ |
| 612 | 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ | 615 | AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ |
| 613 | 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ | 616 | AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ |
| 614 | 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ | 617 | AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ |
| 615 | 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ | 618 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ |
| 616 | 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ | 619 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ |
| 617 | 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ | 620 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ |
| 618 | 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ | 621 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ |
| 619 | }; | 622 | }; |
| 620 | }; | 623 | }; |
| 621 | 624 | ||
| 622 | mmc0 { | 625 | mmc0 { |
| 623 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | 626 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { |
| 624 | atmel,pins = | 627 | atmel,pins = |
| 625 | <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ | 628 | <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ |
| 626 | 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ | 629 | AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ |
| 627 | 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ | 630 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ |
| 628 | }; | 631 | }; |
| 629 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | 632 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { |
| 630 | atmel,pins = | 633 | atmel,pins = |
| 631 | <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ | 634 | <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ |
| 632 | 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ | 635 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ |
| 633 | 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ | 636 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ |
| 634 | }; | 637 | }; |
| 635 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | 638 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { |
| 636 | atmel,pins = | 639 | atmel,pins = |
| 637 | <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ | 640 | <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ |
| 638 | 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | 641 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ |
| 639 | 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | 642 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ |
| 640 | 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | 643 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ |
| 641 | }; | 644 | }; |
| 642 | }; | 645 | }; |
| 643 | 646 | ||
| 644 | mmc1 { | 647 | mmc1 { |
| 645 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | 648 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { |
| 646 | atmel,pins = | 649 | atmel,pins = |
| 647 | <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ | 650 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ |
| 648 | 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | 651 | AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ |
| 649 | 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | 652 | AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ |
| 650 | }; | 653 | }; |
| 651 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | 654 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { |
| 652 | atmel,pins = | 655 | atmel,pins = |
| 653 | <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ | 656 | <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ |
| 654 | 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | 657 | AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ |
| 655 | 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | 658 | AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ |
| 656 | }; | 659 | }; |
| 657 | }; | 660 | }; |
| 658 | 661 | ||
| 659 | mmc2 { | 662 | mmc2 { |
| 660 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { | 663 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { |
| 661 | atmel,pins = | 664 | atmel,pins = |
| 662 | <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ | 665 | <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ |
| 663 | 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ | 666 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ |
| 664 | 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ | 667 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ |
| 665 | }; | 668 | }; |
| 666 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { | 669 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { |
| 667 | atmel,pins = | 670 | atmel,pins = |
| 668 | <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ | 671 | <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ |
| 669 | 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ | 672 | AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ |
| 670 | 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ | 673 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ |
| 671 | }; | 674 | }; |
| 672 | }; | 675 | }; |
| 673 | 676 | ||
| 674 | nand0 { | 677 | nand0 { |
| 675 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | 678 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { |
| 676 | atmel,pins = | 679 | atmel,pins = |
| 677 | <4 21 0x1 0x1 /* PE21 periph A with pullup */ | 680 | <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ |
| 678 | 4 22 0x1 0x1>; /* PE22 periph A with pullup */ | 681 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ |
| 679 | }; | 682 | }; |
| 680 | }; | 683 | }; |
| 681 | 684 | ||
| 682 | pioA: gpio@fffff200 { | ||
| 683 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 684 | reg = <0xfffff200 0x100>; | ||
| 685 | interrupts = <6 4 1>; | ||
| 686 | #gpio-cells = <2>; | ||
| 687 | gpio-controller; | ||
| 688 | interrupt-controller; | ||
| 689 | #interrupt-cells = <2>; | ||
| 690 | }; | ||
| 691 | |||
| 692 | pioB: gpio@fffff400 { | ||
| 693 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 694 | reg = <0xfffff400 0x100>; | ||
| 695 | interrupts = <7 4 1>; | ||
| 696 | #gpio-cells = <2>; | ||
| 697 | gpio-controller; | ||
| 698 | interrupt-controller; | ||
| 699 | #interrupt-cells = <2>; | ||
| 700 | }; | ||
| 701 | |||
| 702 | pioC: gpio@fffff600 { | ||
| 703 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 704 | reg = <0xfffff600 0x100>; | ||
| 705 | interrupts = <8 4 1>; | ||
| 706 | #gpio-cells = <2>; | ||
| 707 | gpio-controller; | ||
| 708 | interrupt-controller; | ||
| 709 | #interrupt-cells = <2>; | ||
| 710 | }; | ||
| 711 | |||
| 712 | pioD: gpio@fffff800 { | ||
| 713 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 714 | reg = <0xfffff800 0x100>; | ||
| 715 | interrupts = <9 4 1>; | ||
| 716 | #gpio-cells = <2>; | ||
| 717 | gpio-controller; | ||
| 718 | interrupt-controller; | ||
| 719 | #interrupt-cells = <2>; | ||
| 720 | }; | ||
| 721 | |||
| 722 | pioE: gpio@fffffa00 { | ||
| 723 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 724 | reg = <0xfffffa00 0x100>; | ||
| 725 | interrupts = <10 4 1>; | ||
| 726 | #gpio-cells = <2>; | ||
| 727 | gpio-controller; | ||
| 728 | interrupt-controller; | ||
| 729 | #interrupt-cells = <2>; | ||
| 730 | }; | ||
| 731 | |||
| 732 | spi0 { | 685 | spi0 { |
| 733 | pinctrl_spi0: spi0-0 { | 686 | pinctrl_spi0: spi0-0 { |
| 734 | atmel,pins = | 687 | atmel,pins = |
| 735 | <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ | 688 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ |
| 736 | 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ | 689 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ |
| 737 | 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ | 690 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ |
| 738 | 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ | ||
| 739 | }; | 691 | }; |
| 740 | }; | 692 | }; |
| 741 | 693 | ||
| 742 | spi1 { | 694 | spi1 { |
| 743 | pinctrl_spi1: spi1-0 { | 695 | pinctrl_spi1: spi1-0 { |
| 744 | atmel,pins = | 696 | atmel,pins = |
| 745 | <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ | 697 | <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ |
| 746 | 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ | 698 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ |
| 747 | 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ | 699 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ |
| 748 | 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ | ||
| 749 | }; | 700 | }; |
| 750 | }; | 701 | }; |
| 751 | 702 | ||
| 752 | ssc0 { | 703 | ssc0 { |
| 753 | pinctrl_ssc0_tx: ssc0_tx { | 704 | pinctrl_ssc0_tx: ssc0_tx { |
| 754 | atmel,pins = | 705 | atmel,pins = |
| 755 | <2 16 0x1 0x0 /* PC16 periph A TK0 */ | 706 | <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ |
| 756 | 2 17 0x1 0x0 /* PC17 periph A TF0 */ | 707 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ |
| 757 | 2 18 0x1 0x0>; /* PC18 periph A TD0 */ | 708 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ |
| 758 | }; | 709 | }; |
| 759 | 710 | ||
| 760 | pinctrl_ssc0_rx: ssc0_rx { | 711 | pinctrl_ssc0_rx: ssc0_rx { |
| 761 | atmel,pins = | 712 | atmel,pins = |
| 762 | <2 19 0x1 0x0 /* PC19 periph A RK0 */ | 713 | <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ |
| 763 | 2 20 0x1 0x0 /* PC20 periph A RF0 */ | 714 | AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ |
| 764 | 2 21 0x1 0x0>; /* PC21 periph A RD0 */ | 715 | AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ |
| 765 | }; | 716 | }; |
| 766 | }; | 717 | }; |
| 767 | 718 | ||
| 768 | ssc1 { | 719 | ssc1 { |
| 769 | pinctrl_ssc1_tx: ssc1_tx { | 720 | pinctrl_ssc1_tx: ssc1_tx { |
| 770 | atmel,pins = | 721 | atmel,pins = |
| 771 | <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ | 722 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ |
| 772 | 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ | 723 | AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ |
| 773 | 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ | 724 | AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ |
| 774 | }; | 725 | }; |
| 775 | 726 | ||
| 776 | pinctrl_ssc1_rx: ssc1_rx { | 727 | pinctrl_ssc1_rx: ssc1_rx { |
| 777 | atmel,pins = | 728 | atmel,pins = |
| 778 | <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ | 729 | <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ |
| 779 | 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ | 730 | AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ |
| 780 | 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ | 731 | AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ |
| 781 | }; | 732 | }; |
| 782 | }; | 733 | }; |
| 783 | 734 | ||
| 784 | uart0 { | 735 | uart0 { |
| 785 | pinctrl_uart0: uart0-0 { | 736 | pinctrl_uart0: uart0-0 { |
| 786 | atmel,pins = | 737 | atmel,pins = |
| 787 | <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ | 738 | <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ |
| 788 | 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ | 739 | AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ |
| 789 | }; | 740 | }; |
| 790 | }; | 741 | }; |
| 791 | 742 | ||
| 792 | uart1 { | 743 | uart1 { |
| 793 | pinctrl_uart1: uart1-0 { | 744 | pinctrl_uart1: uart1-0 { |
| 794 | atmel,pins = | 745 | atmel,pins = |
| 795 | <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ | 746 | <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ |
| 796 | 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ | 747 | AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ |
| 797 | }; | 748 | }; |
| 798 | }; | 749 | }; |
| 799 | 750 | ||
| 800 | usart0 { | 751 | usart0 { |
| 801 | pinctrl_usart0: usart0-0 { | 752 | pinctrl_usart0: usart0-0 { |
| 802 | atmel,pins = | 753 | atmel,pins = |
| 803 | <3 17 0x1 0x0 /* PD17 periph A */ | 754 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ |
| 804 | 3 18 0x1 0x1>; /* PD18 periph A with pullup */ | 755 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ |
| 805 | }; | 756 | }; |
| 806 | 757 | ||
| 807 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | 758 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { |
| 808 | atmel,pins = | 759 | atmel,pins = |
| 809 | <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ | 760 | <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ |
| 810 | 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | 761 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ |
| 811 | }; | 762 | }; |
| 812 | }; | 763 | }; |
| 813 | 764 | ||
| 814 | usart1 { | 765 | usart1 { |
| 815 | pinctrl_usart1: usart1-0 { | 766 | pinctrl_usart1: usart1-0 { |
| 816 | atmel,pins = | 767 | atmel,pins = |
| 817 | <1 28 0x1 0x0 /* PB28 periph A */ | 768 | <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ |
| 818 | 1 29 0x1 0x1>; /* PB29 periph A with pullup */ | 769 | AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ |
| 819 | }; | 770 | }; |
| 820 | 771 | ||
| 821 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | 772 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { |
| 822 | atmel,pins = | 773 | atmel,pins = |
| 823 | <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ | 774 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ |
| 824 | 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ | 775 | AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ |
| 825 | }; | 776 | }; |
| 826 | }; | 777 | }; |
| 827 | 778 | ||
| 828 | usart2 { | 779 | usart2 { |
| 829 | pinctrl_usart2: usart2-0 { | 780 | pinctrl_usart2: usart2-0 { |
| 830 | atmel,pins = | 781 | atmel,pins = |
| 831 | <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ | 782 | <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ |
| 832 | 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ | 783 | AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ |
| 833 | }; | 784 | }; |
| 834 | 785 | ||
| 835 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | 786 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { |
| 836 | atmel,pins = | 787 | atmel,pins = |
| 837 | <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ | 788 | <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ |
| 838 | 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ | 789 | AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ |
| 839 | }; | 790 | }; |
| 840 | }; | 791 | }; |
| 841 | 792 | ||
| 842 | usart3 { | 793 | usart3 { |
| 843 | pinctrl_usart3: usart3-0 { | 794 | pinctrl_usart3: usart3-0 { |
| 844 | atmel,pins = | 795 | atmel,pins = |
| 845 | <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ | 796 | <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ |
| 846 | 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ | 797 | AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ |
| 847 | }; | 798 | }; |
| 848 | 799 | ||
| 849 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | 800 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { |
| 850 | atmel,pins = | 801 | atmel,pins = |
| 851 | <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ | 802 | <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ |
| 852 | 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ | 803 | AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ |
| 853 | }; | 804 | }; |
| 854 | }; | 805 | }; |
| 806 | |||
| 807 | |||
| 808 | pioA: gpio@fffff200 { | ||
| 809 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 810 | reg = <0xfffff200 0x100>; | ||
| 811 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; | ||
| 812 | #gpio-cells = <2>; | ||
| 813 | gpio-controller; | ||
| 814 | interrupt-controller; | ||
| 815 | #interrupt-cells = <2>; | ||
| 816 | }; | ||
| 817 | |||
| 818 | pioB: gpio@fffff400 { | ||
| 819 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 820 | reg = <0xfffff400 0x100>; | ||
| 821 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; | ||
| 822 | #gpio-cells = <2>; | ||
| 823 | gpio-controller; | ||
| 824 | interrupt-controller; | ||
| 825 | #interrupt-cells = <2>; | ||
| 826 | }; | ||
| 827 | |||
| 828 | pioC: gpio@fffff600 { | ||
| 829 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 830 | reg = <0xfffff600 0x100>; | ||
| 831 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; | ||
| 832 | #gpio-cells = <2>; | ||
| 833 | gpio-controller; | ||
| 834 | interrupt-controller; | ||
| 835 | #interrupt-cells = <2>; | ||
| 836 | }; | ||
| 837 | |||
| 838 | pioD: gpio@fffff800 { | ||
| 839 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 840 | reg = <0xfffff800 0x100>; | ||
| 841 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; | ||
| 842 | #gpio-cells = <2>; | ||
| 843 | gpio-controller; | ||
| 844 | interrupt-controller; | ||
| 845 | #interrupt-cells = <2>; | ||
| 846 | }; | ||
| 847 | |||
| 848 | pioE: gpio@fffffa00 { | ||
| 849 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 850 | reg = <0xfffffa00 0x100>; | ||
| 851 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; | ||
| 852 | #gpio-cells = <2>; | ||
| 853 | gpio-controller; | ||
| 854 | interrupt-controller; | ||
| 855 | #interrupt-cells = <2>; | ||
| 856 | }; | ||
| 855 | }; | 857 | }; |
| 856 | 858 | ||
| 857 | pmc: pmc@fffffc00 { | 859 | pmc: pmc@fffffc00 { |
| @@ -867,7 +869,7 @@ | |||
| 867 | pit: timer@fffffe30 { | 869 | pit: timer@fffffe30 { |
| 868 | compatible = "atmel,at91sam9260-pit"; | 870 | compatible = "atmel,at91sam9260-pit"; |
| 869 | reg = <0xfffffe30 0xf>; | 871 | reg = <0xfffffe30 0xf>; |
| 870 | interrupts = <3 4 5>; | 872 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
| 871 | }; | 873 | }; |
| 872 | 874 | ||
| 873 | watchdog@fffffe40 { | 875 | watchdog@fffffe40 { |
| @@ -879,7 +881,7 @@ | |||
| 879 | rtc@fffffeb0 { | 881 | rtc@fffffeb0 { |
| 880 | compatible = "atmel,at91rm9200-rtc"; | 882 | compatible = "atmel,at91rm9200-rtc"; |
| 881 | reg = <0xfffffeb0 0x30>; | 883 | reg = <0xfffffeb0 0x30>; |
| 882 | interrupts = <1 4 7>; | 884 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 883 | }; | 885 | }; |
| 884 | }; | 886 | }; |
| 885 | 887 | ||
| @@ -889,7 +891,7 @@ | |||
| 889 | compatible = "atmel,at91sam9rl-udc"; | 891 | compatible = "atmel,at91sam9rl-udc"; |
| 890 | reg = <0x00500000 0x100000 | 892 | reg = <0x00500000 0x100000 |
| 891 | 0xf8030000 0x4000>; | 893 | 0xf8030000 0x4000>; |
| 892 | interrupts = <33 4 2>; | 894 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; |
| 893 | status = "disabled"; | 895 | status = "disabled"; |
| 894 | 896 | ||
| 895 | ep0 { | 897 | ep0 { |
| @@ -1001,14 +1003,14 @@ | |||
| 1001 | usb1: ohci@00600000 { | 1003 | usb1: ohci@00600000 { |
| 1002 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 1004 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 1003 | reg = <0x00600000 0x100000>; | 1005 | reg = <0x00600000 0x100000>; |
| 1004 | interrupts = <32 4 2>; | 1006 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1005 | status = "disabled"; | 1007 | status = "disabled"; |
| 1006 | }; | 1008 | }; |
| 1007 | 1009 | ||
| 1008 | usb2: ehci@00700000 { | 1010 | usb2: ehci@00700000 { |
| 1009 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 1011 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 1010 | reg = <0x00700000 0x100000>; | 1012 | reg = <0x00700000 0x100000>; |
| 1011 | interrupts = <32 4 2>; | 1013 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1012 | status = "disabled"; | 1014 | status = "disabled"; |
| 1013 | }; | 1015 | }; |
| 1014 | 1016 | ||
| @@ -1024,7 +1026,7 @@ | |||
| 1024 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | 1026 | 0xffffc000 0x00000070 /* NFC HSMC regs */ |
| 1025 | 0x00200000 0x00100000 /* NFC SRAM banks */ | 1027 | 0x00200000 0x00100000 /* NFC SRAM banks */ |
| 1026 | >; | 1028 | >; |
| 1027 | interrupts = <5 4 6>; | 1029 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; |
| 1028 | atmel,nand-addr-offset = <21>; | 1030 | atmel,nand-addr-offset = <21>; |
| 1029 | atmel,nand-cmd-offset = <22>; | 1031 | atmel,nand-cmd-offset = <22>; |
| 1030 | pinctrl-names = "default"; | 1032 | pinctrl-names = "default"; |
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index fa5d216f1db7..027bac7510b6 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "sama5d3xmb.dtsi" | 10 | #include "sama5d3xmb.dtsi" |
| 11 | /include/ "sama5d3xdm.dtsi" | 11 | #include "sama5d3xdm.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel SAMA5D31-EK"; | 14 | model = "Atmel SAMA5D31-EK"; |
| @@ -41,7 +41,7 @@ | |||
| 41 | leds { | 41 | leds { |
| 42 | d3 { | 42 | d3 { |
| 43 | label = "d3"; | 43 | label = "d3"; |
| 44 | gpios = <&pioE 24 0>; | 44 | gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; |
| 45 | }; | 45 | }; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts index c38c9433d7a5..99bd0c8e0471 100644 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ b/arch/arm/boot/dts/sama5d33ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "sama5d3xmb.dtsi" | 10 | #include "sama5d3xmb.dtsi" |
| 11 | /include/ "sama5d3xdm.dtsi" | 11 | #include "sama5d3xdm.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel SAMA5D33-EK"; | 14 | model = "Atmel SAMA5D33-EK"; |
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 6bebfcdcb1d1..fb8ee11cf282 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "sama5d3xmb.dtsi" | 10 | #include "sama5d3xmb.dtsi" |
| 11 | /include/ "sama5d3xdm.dtsi" | 11 | #include "sama5d3xdm.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Atmel SAMA5D34-EK"; | 14 | model = "Atmel SAMA5D34-EK"; |
| @@ -51,7 +51,7 @@ | |||
| 51 | leds { | 51 | leds { |
| 52 | d3 { | 52 | d3 { |
| 53 | label = "d3"; | 53 | label = "d3"; |
| 54 | gpios = <&pioE 24 0>; | 54 | gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; |
| 55 | }; | 55 | }; |
| 56 | }; | 56 | }; |
| 57 | 57 | ||
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index a488fc4e9777..509a53d9cc7b 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | /include/ "sama5d3xmb.dtsi" | 10 | #include "sama5d3xmb.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Atmel SAMA5D35-EK"; | 13 | model = "Atmel SAMA5D35-EK"; |
| @@ -48,7 +48,7 @@ | |||
| 48 | 48 | ||
| 49 | pb_user1 { | 49 | pb_user1 { |
| 50 | label = "pb_user1"; | 50 | label = "pb_user1"; |
| 51 | gpios = <&pioE 27 0>; | 51 | gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; |
| 52 | linux,code = <0x100>; | 52 | linux,code = <0x100>; |
| 53 | gpio-key,wakeup; | 53 | gpio-key,wakeup; |
| 54 | }; | 54 | }; |
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index b336e7787cb3..1f8050813a54 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * | 6 | * |
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /include/ "sama5d3.dtsi" | 9 | #include "sama5d3.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; | 12 | compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; |
| @@ -89,7 +89,7 @@ | |||
| 89 | 89 | ||
| 90 | d2 { | 90 | d2 { |
| 91 | label = "d2"; | 91 | label = "d2"; |
| 92 | gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ | 92 | gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ |
| 93 | }; | 93 | }; |
| 94 | }; | 94 | }; |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 4b8830eb2060..1c296d6b2f2a 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
| @@ -33,7 +33,7 @@ | |||
| 33 | board { | 33 | board { |
| 34 | pinctrl_qt1070_irq: qt1070_irq { | 34 | pinctrl_qt1070_irq: qt1070_irq { |
| 35 | atmel,pins = | 35 | atmel,pins = |
| 36 | <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ | 36 | <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */ |
| 37 | }; | 37 | }; |
| 38 | }; | 38 | }; |
| 39 | }; | 39 | }; |
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 661d7ca9c309..8a9e05d8a4b8 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * | 6 | * |
| 7 | * Licensed under GPLv2 or later. | 7 | * Licensed under GPLv2 or later. |
| 8 | */ | 8 | */ |
| 9 | /include/ "sama5d3xcm.dtsi" | 9 | #include "sama5d3xcm.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | 12 | compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; |
| @@ -20,7 +20,7 @@ | |||
| 20 | slot@0 { | 20 | slot@0 { |
| 21 | reg = <0>; | 21 | reg = <0>; |
| 22 | bus-width = <4>; | 22 | bus-width = <4>; |
| 23 | cd-gpios = <&pioD 17 0>; | 23 | cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; |
| 24 | }; | 24 | }; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| @@ -62,7 +62,7 @@ | |||
| 62 | slot@0 { | 62 | slot@0 { |
| 63 | reg = <0>; | 63 | reg = <0>; |
| 64 | bus-width = <4>; | 64 | bus-width = <4>; |
| 65 | cd-gpios = <&pioD 18 0>; | 65 | cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; |
| 66 | }; | 66 | }; |
| 67 | }; | 67 | }; |
| 68 | 68 | ||
| @@ -87,32 +87,32 @@ | |||
| 87 | board { | 87 | board { |
| 88 | pinctrl_mmc0_cd: mmc0_cd { | 88 | pinctrl_mmc0_cd: mmc0_cd { |
| 89 | atmel,pins = | 89 | atmel,pins = |
| 90 | <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ | 90 | <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */ |
| 91 | }; | 91 | }; |
| 92 | 92 | ||
| 93 | pinctrl_mmc1_cd: mmc1_cd { | 93 | pinctrl_mmc1_cd: mmc1_cd { |
| 94 | atmel,pins = | 94 | atmel,pins = |
| 95 | <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ | 95 | <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */ |
| 96 | }; | 96 | }; |
| 97 | 97 | ||
| 98 | pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { | 98 | pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { |
| 99 | atmel,pins = | 99 | atmel,pins = |
| 100 | <3 30 0x2 0x0>; /* PD30 periph B */ | 100 | <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */ |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | pinctrl_isi_reset: isi_reset-0 { | 103 | pinctrl_isi_reset: isi_reset-0 { |
| 104 | atmel,pins = | 104 | atmel,pins = |
| 105 | <4 24 0x0 0x0>; /* PE24 gpio */ | 105 | <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */ |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | pinctrl_isi_power: isi_power-0 { | 108 | pinctrl_isi_power: isi_power-0 { |
| 109 | atmel,pins = | 109 | atmel,pins = |
| 110 | <4 29 0x0 0x0>; /* PE29 gpio */ | 110 | <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */ |
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | pinctrl_usba_vbus: usba_vbus { | 113 | pinctrl_usba_vbus: usba_vbus { |
| 114 | atmel,pins = | 114 | atmel,pins = |
| 115 | <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ | 115 | <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */ |
| 116 | }; | 116 | }; |
| 117 | }; | 117 | }; |
| 118 | }; | 118 | }; |
| @@ -127,7 +127,7 @@ | |||
| 127 | }; | 127 | }; |
| 128 | 128 | ||
| 129 | usb0: gadget@00500000 { | 129 | usb0: gadget@00500000 { |
| 130 | atmel,vbus-gpio = <&pioD 29 0>; | 130 | atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; |
| 131 | pinctrl-names = "default"; | 131 | pinctrl-names = "default"; |
| 132 | pinctrl-0 = <&pinctrl_usba_vbus>; | 132 | pinctrl-0 = <&pinctrl_usba_vbus>; |
| 133 | status = "okay"; | 133 | status = "okay"; |
| @@ -135,9 +135,9 @@ | |||
| 135 | 135 | ||
| 136 | usb1: ohci@00600000 { | 136 | usb1: ohci@00600000 { |
| 137 | num-ports = <3>; | 137 | num-ports = <3>; |
| 138 | atmel,vbus-gpio = <&pioD 25 0 | 138 | atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH |
| 139 | &pioD 26 1 | 139 | &pioD 26 GPIO_ACTIVE_LOW |
| 140 | &pioD 27 1 | 140 | &pioD 27 GPIO_ACTIVE_LOW |
| 141 | >; | 141 | >; |
| 142 | status = "okay"; | 142 | status = "okay"; |
| 143 | }; | 143 | }; |
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts index 367a16dcd5ef..dabe232216b4 100644 --- a/arch/arm/boot/dts/tny_a9260.dts +++ b/arch/arm/boot/dts/tny_a9260.dts | |||
| @@ -6,8 +6,8 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9260.dtsi" | 9 | #include "at91sam9260.dtsi" |
| 10 | /include/ "tny_a9260_common.dtsi" | 10 | #include "tny_a9260_common.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Calao TNY A9260"; | 13 | model = "Calao TNY A9260"; |
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index dee9c571306b..0751a6a979a8 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2 only | 6 | * Licensed under GPLv2 only |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9263.dtsi" | 9 | #include "at91sam9263.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Calao TNY A9263"; | 12 | model = "Calao TNY A9263"; |
| @@ -38,7 +38,7 @@ | |||
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | usb1: gadget@fff78000 { | 40 | usb1: gadget@fff78000 { |
| 41 | atmel,vbus-gpio = <&pioB 11 0>; | 41 | atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; |
| 42 | status = "okay"; | 42 | status = "okay"; |
| 43 | }; | 43 | }; |
| 44 | }; | 44 | }; |
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts index e1ab64c72dba..8456d70bb42b 100644 --- a/arch/arm/boot/dts/tny_a9g20.dts +++ b/arch/arm/boot/dts/tny_a9g20.dts | |||
| @@ -6,8 +6,8 @@ | |||
| 6 | * Licensed under GPLv2. | 6 | * Licensed under GPLv2. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9g20.dtsi" | 9 | #include "at91sam9g20.dtsi" |
| 10 | /include/ "tny_a9260_common.dtsi" | 10 | #include "tny_a9260_common.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Calao TNY A9G20"; | 13 | model = "Calao TNY A9G20"; |
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index 296216058c11..a604107eb474 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts | |||
| @@ -6,8 +6,8 @@ | |||
| 6 | * Licensed under GPLv2 or later. | 6 | * Licensed under GPLv2 or later. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9260.dtsi" | 9 | #include "at91sam9260.dtsi" |
| 10 | /include/ "usb_a9260_common.dtsi" | 10 | #include "usb_a9260_common.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Calao USB A9260"; | 13 | model = "Calao USB A9260"; |
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index e70d229baef5..285977682cf3 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi | |||
| @@ -30,7 +30,7 @@ | |||
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | usb1: gadget@fffa4000 { | 32 | usb1: gadget@fffa4000 { |
| 33 | atmel,vbus-gpio = <&pioC 5 0>; | 33 | atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; |
| 34 | status = "okay"; | 34 | status = "okay"; |
| 35 | }; | 35 | }; |
| 36 | }; | 36 | }; |
| @@ -93,7 +93,7 @@ | |||
| 93 | 93 | ||
| 94 | user_led { | 94 | user_led { |
| 95 | label = "user_led"; | 95 | label = "user_led"; |
| 96 | gpios = <&pioB 21 1>; | 96 | gpios = <&pioB 21 GPIO_ACTIVE_LOW>; |
| 97 | linux,default-trigger = "heartbeat"; | 97 | linux,default-trigger = "heartbeat"; |
| 98 | }; | 98 | }; |
| 99 | }; | 99 | }; |
| @@ -105,7 +105,7 @@ | |||
| 105 | 105 | ||
| 106 | user_pb { | 106 | user_pb { |
| 107 | label = "user_pb"; | 107 | label = "user_pb"; |
| 108 | gpios = <&pioB 10 1>; | 108 | gpios = <&pioB 10 GPIO_ACTIVE_LOW>; |
| 109 | linux,code = <28>; | 109 | linux,code = <28>; |
| 110 | gpio-key,wakeup; | 110 | gpio-key,wakeup; |
| 111 | }; | 111 | }; |
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 6fe05ccb6203..f8ec36cb036b 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under GPLv2 only | 6 | * Licensed under GPLv2 only |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9263.dtsi" | 9 | #include "at91sam9263.dtsi" |
| 10 | 10 | ||
| 11 | / { | 11 | / { |
| 12 | model = "Calao USB A9263"; | 12 | model = "Calao USB A9263"; |
| @@ -43,7 +43,7 @@ | |||
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | usb1: gadget@fff78000 { | 45 | usb1: gadget@fff78000 { |
| 46 | atmel,vbus-gpio = <&pioB 11 0>; | 46 | atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; |
| 47 | status = "okay"; | 47 | status = "okay"; |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| @@ -107,7 +107,7 @@ | |||
| 107 | 107 | ||
| 108 | user_led { | 108 | user_led { |
| 109 | label = "user_led"; | 109 | label = "user_led"; |
| 110 | gpios = <&pioB 21 0>; | 110 | gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; |
| 111 | linux,default-trigger = "heartbeat"; | 111 | linux,default-trigger = "heartbeat"; |
| 112 | }; | 112 | }; |
| 113 | }; | 113 | }; |
| @@ -119,7 +119,7 @@ | |||
| 119 | 119 | ||
| 120 | user_pb { | 120 | user_pb { |
| 121 | label = "user_pb"; | 121 | label = "user_pb"; |
| 122 | gpios = <&pioB 10 1>; | 122 | gpios = <&pioB 10 GPIO_ACTIVE_LOW>; |
| 123 | linux,code = <28>; | 123 | linux,code = <28>; |
| 124 | gpio-key,wakeup; | 124 | gpio-key,wakeup; |
| 125 | }; | 125 | }; |
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi index ad3eca17c436..5b0ffc1a0b24 100644 --- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi +++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi | |||
| @@ -28,39 +28,39 @@ | |||
| 28 | 28 | ||
| 29 | user_led1 { | 29 | user_led1 { |
| 30 | label = "user_led1"; | 30 | label = "user_led1"; |
| 31 | gpios = <&pioB 20 1>; | 31 | gpios = <&pioB 20 GPIO_ACTIVE_LOW>; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | /* | 34 | /* |
| 35 | * led already used by mother board but active as high | 35 | * led already used by mother board but active as high |
| 36 | * user_led2 { | 36 | * user_led2 { |
| 37 | * label = "user_led2"; | 37 | * label = "user_led2"; |
| 38 | * gpios = <&pioB 21 1>; | 38 | * gpios = <&pioB 21 GPIO_ACTIVE_LOW>; |
| 39 | * }; | 39 | * }; |
| 40 | */ | 40 | */ |
| 41 | user_led3 { | 41 | user_led3 { |
| 42 | label = "user_led3"; | 42 | label = "user_led3"; |
| 43 | gpios = <&pioB 22 1>; | 43 | gpios = <&pioB 22 GPIO_ACTIVE_LOW>; |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | user_led4 { | 46 | user_led4 { |
| 47 | label = "user_led4"; | 47 | label = "user_led4"; |
| 48 | gpios = <&pioB 23 1>; | 48 | gpios = <&pioB 23 GPIO_ACTIVE_LOW>; |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | red { | 51 | red { |
| 52 | label = "red"; | 52 | label = "red"; |
| 53 | gpios = <&pioB 24 1>; | 53 | gpios = <&pioB 24 GPIO_ACTIVE_LOW>; |
| 54 | }; | 54 | }; |
| 55 | 55 | ||
| 56 | orange { | 56 | orange { |
| 57 | label = "orange"; | 57 | label = "orange"; |
| 58 | gpios = <&pioB 30 1>; | 58 | gpios = <&pioB 30 GPIO_ACTIVE_LOW>; |
| 59 | }; | 59 | }; |
| 60 | 60 | ||
| 61 | green { | 61 | green { |
| 62 | label = "green"; | 62 | label = "green"; |
| 63 | gpios = <&pioB 31 1>; | 63 | gpios = <&pioB 31 GPIO_ACTIVE_LOW>; |
| 64 | }; | 64 | }; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| @@ -71,25 +71,25 @@ | |||
| 71 | 71 | ||
| 72 | user_pb1 { | 72 | user_pb1 { |
| 73 | label = "user_pb1"; | 73 | label = "user_pb1"; |
| 74 | gpios = <&pioB 25 1>; | 74 | gpios = <&pioB 25 GPIO_ACTIVE_LOW>; |
| 75 | linux,code = <0x100>; | 75 | linux,code = <0x100>; |
| 76 | }; | 76 | }; |
| 77 | 77 | ||
| 78 | user_pb2 { | 78 | user_pb2 { |
| 79 | label = "user_pb2"; | 79 | label = "user_pb2"; |
| 80 | gpios = <&pioB 13 1>; | 80 | gpios = <&pioB 13 GPIO_ACTIVE_LOW>; |
| 81 | linux,code = <0x101>; | 81 | linux,code = <0x101>; |
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | user_pb3 { | 84 | user_pb3 { |
| 85 | label = "user_pb3"; | 85 | label = "user_pb3"; |
| 86 | gpios = <&pioA 26 1>; | 86 | gpios = <&pioA 26 GPIO_ACTIVE_LOW>; |
| 87 | linux,code = <0x102>; | 87 | linux,code = <0x102>; |
| 88 | }; | 88 | }; |
| 89 | 89 | ||
| 90 | user_pb4 { | 90 | user_pb4 { |
| 91 | label = "user_pb4"; | 91 | label = "user_pb4"; |
| 92 | gpios = <&pioC 9 1>; | 92 | gpios = <&pioC 9 GPIO_ACTIVE_LOW>; |
| 93 | linux,code = <0x103>; | 93 | linux,code = <0x103>; |
| 94 | }; | 94 | }; |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts index 2dacb16ce4ae..c979c06cf697 100644 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ b/arch/arm/boot/dts/usb_a9g20.dts | |||
| @@ -6,8 +6,8 @@ | |||
| 6 | * Licensed under GPLv2 or later. | 6 | * Licensed under GPLv2 or later. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | /include/ "at91sam9g20.dtsi" | 9 | #include "at91sam9g20.dtsi" |
| 10 | /include/ "usb_a9260_common.dtsi" | 10 | #include "usb_a9260_common.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Calao USB A9G20"; | 13 | model = "Calao USB A9G20"; |
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 047f2a415309..a8800d361805 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 4 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| @@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | |||
| 25 | CONFIG_AT91_TIMER_HZ=128 | 24 | CONFIG_AT91_TIMER_HZ=128 |
| 26 | CONFIG_AEABI=y | 25 | CONFIG_AEABI=y |
| 27 | # CONFIG_OABI_COMPAT is not set | 26 | # CONFIG_OABI_COMPAT is not set |
| 28 | CONFIG_LEDS=y | ||
| 29 | CONFIG_LEDS_CPU=y | ||
| 30 | CONFIG_UACCESS_WITH_MEMCPY=y | 27 | CONFIG_UACCESS_WITH_MEMCPY=y |
| 31 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 28 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 32 | CONFIG_ZBOOT_ROM_BSS=0x0 | 29 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| @@ -42,6 +39,9 @@ CONFIG_UNIX=y | |||
| 42 | CONFIG_INET=y | 39 | CONFIG_INET=y |
| 43 | CONFIG_IP_MULTICAST=y | 40 | CONFIG_IP_MULTICAST=y |
| 44 | CONFIG_IP_PNP=y | 41 | CONFIG_IP_PNP=y |
| 42 | CONFIG_IP_PNP_DHCP=y | ||
| 43 | CONFIG_IP_PNP_BOOTP=y | ||
| 44 | CONFIG_IP_PNP_RARP=y | ||
| 45 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 45 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 46 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 46 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 47 | # CONFIG_INET_XFRM_MODE_BEET is not set | 47 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| @@ -51,7 +51,8 @@ CONFIG_IPV6=y | |||
| 51 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set | 51 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set |
| 52 | # CONFIG_INET6_XFRM_MODE_BEET is not set | 52 | # CONFIG_INET6_XFRM_MODE_BEET is not set |
| 53 | CONFIG_IPV6_SIT_6RD=y | 53 | CONFIG_IPV6_SIT_6RD=y |
| 54 | # CONFIG_WIRELESS is not set | 54 | CONFIG_CFG80211=y |
| 55 | CONFIG_MAC80211=y | ||
| 55 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 56 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 56 | CONFIG_DEVTMPFS=y | 57 | CONFIG_DEVTMPFS=y |
| 57 | CONFIG_DEVTMPFS_MOUNT=y | 58 | CONFIG_DEVTMPFS_MOUNT=y |
| @@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4 | |||
| 72 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 73 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 73 | CONFIG_ATMEL_PWM=y | 74 | CONFIG_ATMEL_PWM=y |
| 74 | CONFIG_ATMEL_TCLIB=y | 75 | CONFIG_ATMEL_TCLIB=y |
| 75 | CONFIG_EEPROM_93CX6=m | ||
| 76 | CONFIG_SCSI=y | 76 | CONFIG_SCSI=y |
| 77 | CONFIG_BLK_DEV_SD=y | 77 | CONFIG_BLK_DEV_SD=y |
| 78 | CONFIG_SCSI_MULTI_LUN=y | 78 | CONFIG_SCSI_MULTI_LUN=y |
| @@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y | |||
| 81 | CONFIG_MII=y | 81 | CONFIG_MII=y |
| 82 | CONFIG_MACB=y | 82 | CONFIG_MACB=y |
| 83 | # CONFIG_NET_VENDOR_BROADCOM is not set | 83 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 84 | # CONFIG_NET_VENDOR_CHELSIO is not set | ||
| 85 | # CONFIG_NET_VENDOR_FARADAY is not set | 84 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 86 | # CONFIG_NET_VENDOR_INTEL is not set | 85 | # CONFIG_NET_VENDOR_INTEL is not set |
| 87 | # CONFIG_NET_VENDOR_MARVELL is not set | 86 | # CONFIG_NET_VENDOR_MARVELL is not set |
| @@ -92,7 +91,23 @@ CONFIG_MACB=y | |||
| 92 | # CONFIG_NET_VENDOR_STMICRO is not set | 91 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 93 | CONFIG_DAVICOM_PHY=y | 92 | CONFIG_DAVICOM_PHY=y |
| 94 | CONFIG_MICREL_PHY=y | 93 | CONFIG_MICREL_PHY=y |
| 95 | # CONFIG_WLAN is not set | 94 | CONFIG_RTL8187=m |
| 95 | CONFIG_LIBERTAS=m | ||
| 96 | CONFIG_LIBERTAS_SDIO=m | ||
| 97 | CONFIG_LIBERTAS_SPI=m | ||
| 98 | CONFIG_RT2X00=m | ||
| 99 | CONFIG_RT2500USB=m | ||
| 100 | CONFIG_RT73USB=m | ||
| 101 | CONFIG_RT2800USB=m | ||
| 102 | CONFIG_RT2800USB_RT53XX=y | ||
| 103 | CONFIG_RT2800USB_RT55XX=y | ||
| 104 | CONFIG_RT2800USB_UNKNOWN=y | ||
| 105 | CONFIG_RTLWIFI=m | ||
| 106 | # CONFIG_RTLWIFI_DEBUG is not set | ||
| 107 | CONFIG_RTL8192CU=m | ||
| 108 | CONFIG_MWIFIEX=m | ||
| 109 | CONFIG_MWIFIEX_SDIO=m | ||
| 110 | CONFIG_MWIFIEX_USB=m | ||
| 96 | CONFIG_INPUT_POLLDEV=y | 111 | CONFIG_INPUT_POLLDEV=y |
| 97 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 112 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 98 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 | 113 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 |
| @@ -112,13 +127,11 @@ CONFIG_I2C=y | |||
| 112 | CONFIG_I2C_GPIO=y | 127 | CONFIG_I2C_GPIO=y |
| 113 | CONFIG_SPI=y | 128 | CONFIG_SPI=y |
| 114 | CONFIG_SPI_ATMEL=y | 129 | CONFIG_SPI_ATMEL=y |
| 115 | CONFIG_PINCTRL_AT91=y | ||
| 116 | # CONFIG_HWMON is not set | 130 | # CONFIG_HWMON is not set |
| 117 | CONFIG_WATCHDOG=y | 131 | CONFIG_WATCHDOG=y |
| 118 | CONFIG_AT91SAM9X_WATCHDOG=y | 132 | CONFIG_AT91SAM9X_WATCHDOG=y |
| 119 | CONFIG_SSB=m | 133 | CONFIG_SSB=m |
| 120 | CONFIG_FB=y | 134 | CONFIG_FB=y |
| 121 | CONFIG_FB_MODE_HELPERS=y | ||
| 122 | CONFIG_FB_ATMEL=y | 135 | CONFIG_FB_ATMEL=y |
| 123 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 136 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 124 | # CONFIG_LCD_CLASS_DEVICE is not set | 137 | # CONFIG_LCD_CLASS_DEVICE is not set |
| @@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y | |||
| 132 | CONFIG_FONT_ACORN_8x8=y | 145 | CONFIG_FONT_ACORN_8x8=y |
| 133 | CONFIG_FONT_MINI_4x6=y | 146 | CONFIG_FONT_MINI_4x6=y |
| 134 | CONFIG_LOGO=y | 147 | CONFIG_LOGO=y |
| 135 | # CONFIG_HID_SUPPORT is not set | ||
| 136 | CONFIG_USB=y | 148 | CONFIG_USB=y |
| 137 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 149 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 138 | CONFIG_USB_DEVICEFS=y | ||
| 139 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 140 | CONFIG_USB_EHCI_HCD=y | 150 | CONFIG_USB_EHCI_HCD=y |
| 141 | CONFIG_USB_OHCI_HCD=y | 151 | CONFIG_USB_OHCI_HCD=y |
| 142 | CONFIG_USB_ACM=y | 152 | CONFIG_USB_ACM=y |
| @@ -146,14 +156,9 @@ CONFIG_USB_SERIAL_GENERIC=y | |||
| 146 | CONFIG_USB_SERIAL_FTDI_SIO=y | 156 | CONFIG_USB_SERIAL_FTDI_SIO=y |
| 147 | CONFIG_USB_SERIAL_PL2303=y | 157 | CONFIG_USB_SERIAL_PL2303=y |
| 148 | CONFIG_USB_GADGET=y | 158 | CONFIG_USB_GADGET=y |
| 149 | CONFIG_USB_AT91=m | 159 | CONFIG_USB_AT91=y |
| 150 | CONFIG_USB_ATMEL_USBA=m | 160 | CONFIG_USB_ATMEL_USBA=y |
| 151 | CONFIG_USB_ETH=m | 161 | CONFIG_USB_G_SERIAL=y |
| 152 | CONFIG_USB_GADGETFS=m | ||
| 153 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 154 | CONFIG_USB_G_ACM_MS=m | ||
| 155 | CONFIG_USB_G_MULTI=m | ||
| 156 | CONFIG_USB_G_MULTI_CDC=y | ||
| 157 | CONFIG_MMC=y | 162 | CONFIG_MMC=y |
| 158 | CONFIG_MMC_ATMELMCI=y | 163 | CONFIG_MMC_ATMELMCI=y |
| 159 | CONFIG_NEW_LEDS=y | 164 | CONFIG_NEW_LEDS=y |
| @@ -168,16 +173,18 @@ CONFIG_RTC_DRV_AT91RM9200=y | |||
| 168 | CONFIG_RTC_DRV_AT91SAM9=y | 173 | CONFIG_RTC_DRV_AT91SAM9=y |
| 169 | CONFIG_DMADEVICES=y | 174 | CONFIG_DMADEVICES=y |
| 170 | # CONFIG_IOMMU_SUPPORT is not set | 175 | # CONFIG_IOMMU_SUPPORT is not set |
| 171 | CONFIG_EXT2_FS=y | 176 | CONFIG_EXT4_FS=y |
| 172 | CONFIG_FANOTIFY=y | 177 | CONFIG_FANOTIFY=y |
| 173 | CONFIG_VFAT_FS=y | 178 | CONFIG_VFAT_FS=y |
| 174 | CONFIG_TMPFS=y | 179 | CONFIG_TMPFS=y |
| 180 | CONFIG_UBIFS_FS=y | ||
| 181 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y | ||
| 175 | CONFIG_NFS_FS=y | 182 | CONFIG_NFS_FS=y |
| 176 | CONFIG_NFS_V3=y | ||
| 177 | CONFIG_ROOT_NFS=y | 183 | CONFIG_ROOT_NFS=y |
| 178 | CONFIG_NLS_CODEPAGE_437=y | 184 | CONFIG_NLS_CODEPAGE_437=y |
| 179 | CONFIG_NLS_CODEPAGE_850=y | 185 | CONFIG_NLS_CODEPAGE_850=y |
| 180 | CONFIG_NLS_ISO8859_1=y | 186 | CONFIG_NLS_ISO8859_1=y |
| 187 | CONFIG_NLS_UTF8=y | ||
| 181 | CONFIG_STRIP_ASM_SYMS=y | 188 | CONFIG_STRIP_ASM_SYMS=y |
| 182 | CONFIG_DEBUG_FS=y | 189 | CONFIG_DEBUG_FS=y |
| 183 | # CONFIG_SCHED_DEBUG is not set | 190 | # CONFIG_SCHED_DEBUG is not set |
| @@ -192,7 +199,7 @@ CONFIG_CRYPTO_ARC4=y | |||
| 192 | CONFIG_CRYPTO_USER_API_HASH=m | 199 | CONFIG_CRYPTO_USER_API_HASH=m |
| 193 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | 200 | CONFIG_CRYPTO_USER_API_SKCIPHER=m |
| 194 | # CONFIG_CRYPTO_HW is not set | 201 | # CONFIG_CRYPTO_HW is not set |
| 195 | CONFIG_CRC_CCITT=m | 202 | CONFIG_CRC_CCITT=y |
| 196 | CONFIG_CRC_ITU_T=m | 203 | CONFIG_CRC_ITU_T=y |
| 197 | CONFIG_CRC7=m | 204 | CONFIG_CRC7=m |
| 198 | CONFIG_AVERAGE=y | 205 | CONFIG_AVERAGE=y |
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index 4ae57a34a582..75502c4d222c 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig | |||
| @@ -1,10 +1,12 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 4 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_NO_HZ=y | ||
| 5 | CONFIG_HIGH_RES_TIMERS=y | ||
| 5 | CONFIG_IKCONFIG=y | 6 | CONFIG_IKCONFIG=y |
| 6 | CONFIG_IKCONFIG_PROC=y | 7 | CONFIG_IKCONFIG_PROC=y |
| 7 | CONFIG_LOG_BUF_SHIFT=14 | 8 | CONFIG_LOG_BUF_SHIFT=14 |
| 9 | CONFIG_USER_NS=y | ||
| 8 | CONFIG_BLK_DEV_INITRD=y | 10 | CONFIG_BLK_DEV_INITRD=y |
| 9 | CONFIG_MODULES=y | 11 | CONFIG_MODULES=y |
| 10 | CONFIG_MODULE_FORCE_LOAD=y | 12 | CONFIG_MODULE_FORCE_LOAD=y |
| @@ -16,7 +18,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y | |||
| 16 | CONFIG_ARCH_AT91=y | 18 | CONFIG_ARCH_AT91=y |
| 17 | CONFIG_ARCH_AT91RM9200=y | 19 | CONFIG_ARCH_AT91RM9200=y |
| 18 | CONFIG_MACH_ONEARM=y | 20 | CONFIG_MACH_ONEARM=y |
| 19 | CONFIG_ARCH_AT91RM9200DK=y | ||
| 20 | CONFIG_MACH_AT91RM9200EK=y | 21 | CONFIG_MACH_AT91RM9200EK=y |
| 21 | CONFIG_MACH_CSB337=y | 22 | CONFIG_MACH_CSB337=y |
| 22 | CONFIG_MACH_CSB637=y | 23 | CONFIG_MACH_CSB637=y |
| @@ -35,49 +36,37 @@ CONFIG_AT91_TIMER_HZ=100 | |||
| 35 | # CONFIG_ARM_THUMB is not set | 36 | # CONFIG_ARM_THUMB is not set |
| 36 | CONFIG_PCCARD=y | 37 | CONFIG_PCCARD=y |
| 37 | CONFIG_AT91_CF=y | 38 | CONFIG_AT91_CF=y |
| 38 | CONFIG_NO_HZ=y | ||
| 39 | CONFIG_HIGH_RES_TIMERS=y | ||
| 40 | CONFIG_PREEMPT=y | ||
| 41 | CONFIG_AEABI=y | 39 | CONFIG_AEABI=y |
| 42 | CONFIG_LEDS=y | 40 | # CONFIG_COMPACTION is not set |
| 43 | CONFIG_LEDS_CPU=y | ||
| 44 | CONFIG_ZBOOT_ROM_TEXT=0x10000000 | 41 | CONFIG_ZBOOT_ROM_TEXT=0x10000000 |
| 45 | CONFIG_ZBOOT_ROM_BSS=0x20040000 | 42 | CONFIG_ZBOOT_ROM_BSS=0x20040000 |
| 46 | CONFIG_KEXEC=y | 43 | CONFIG_KEXEC=y |
| 44 | CONFIG_AUTO_ZRELADDR=y | ||
| 47 | CONFIG_FPE_NWFPE=y | 45 | CONFIG_FPE_NWFPE=y |
| 48 | CONFIG_BINFMT_MISC=y | 46 | CONFIG_BINFMT_MISC=y |
| 49 | CONFIG_NET=y | 47 | CONFIG_NET=y |
| 50 | CONFIG_PACKET=y | 48 | CONFIG_PACKET=y |
| 51 | CONFIG_UNIX=y | 49 | CONFIG_UNIX=y |
| 52 | CONFIG_XFRM_USER=m | ||
| 53 | CONFIG_INET=y | 50 | CONFIG_INET=y |
| 54 | CONFIG_IP_MULTICAST=y | 51 | CONFIG_IP_MULTICAST=y |
| 55 | CONFIG_IP_PNP=y | 52 | CONFIG_IP_PNP=y |
| 56 | CONFIG_IP_PNP_DHCP=y | 53 | CONFIG_IP_PNP_DHCP=y |
| 57 | CONFIG_IP_PNP_BOOTP=y | 54 | CONFIG_IP_PNP_BOOTP=y |
| 58 | CONFIG_NET_IPIP=m | 55 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 59 | CONFIG_INET_AH=m | 56 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 60 | CONFIG_INET_ESP=m | 57 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 61 | CONFIG_INET_IPCOMP=m | 58 | # CONFIG_INET_DIAG is not set |
| 62 | CONFIG_INET_XFRM_MODE_TRANSPORT=m | 59 | CONFIG_IPV6=y |
| 63 | CONFIG_INET_XFRM_MODE_TUNNEL=m | ||
| 64 | CONFIG_INET_XFRM_MODE_BEET=m | ||
| 65 | CONFIG_IPV6_PRIVACY=y | 60 | CONFIG_IPV6_PRIVACY=y |
| 66 | CONFIG_IPV6_ROUTER_PREF=y | 61 | CONFIG_IPV6_ROUTER_PREF=y |
| 67 | CONFIG_IPV6_ROUTE_INFO=y | 62 | CONFIG_IPV6_ROUTE_INFO=y |
| 68 | CONFIG_INET6_AH=m | ||
| 69 | CONFIG_INET6_ESP=m | ||
| 70 | CONFIG_INET6_IPCOMP=m | ||
| 71 | CONFIG_IPV6_MIP6=m | ||
| 72 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | ||
| 73 | CONFIG_IPV6_TUNNEL=m | ||
| 74 | CONFIG_BRIDGE=m | ||
| 75 | CONFIG_VLAN_8021Q=m | ||
| 76 | CONFIG_BT=m | ||
| 77 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 63 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 64 | CONFIG_DEVTMPFS=y | ||
| 65 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 66 | # CONFIG_STANDALONE is not set | ||
| 67 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 78 | CONFIG_MTD=y | 68 | CONFIG_MTD=y |
| 79 | CONFIG_MTD_CMDLINE_PARTS=y | 69 | CONFIG_MTD_CMDLINE_PARTS=y |
| 80 | CONFIG_MTD_AFS_PARTS=y | ||
| 81 | CONFIG_MTD_CHAR=y | 70 | CONFIG_MTD_CHAR=y |
| 82 | CONFIG_MTD_BLOCK=y | 71 | CONFIG_MTD_BLOCK=y |
| 83 | CONFIG_MTD_CFI=y | 72 | CONFIG_MTD_CFI=y |
| @@ -94,55 +83,21 @@ CONFIG_MTD_NAND_PLATFORM=y | |||
| 94 | CONFIG_MTD_UBI=y | 83 | CONFIG_MTD_UBI=y |
| 95 | CONFIG_MTD_UBI_GLUEBI=y | 84 | CONFIG_MTD_UBI_GLUEBI=y |
| 96 | CONFIG_BLK_DEV_LOOP=y | 85 | CONFIG_BLK_DEV_LOOP=y |
| 97 | CONFIG_BLK_DEV_NBD=y | ||
| 98 | CONFIG_BLK_DEV_RAM=y | 86 | CONFIG_BLK_DEV_RAM=y |
| 99 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 87 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 100 | CONFIG_SCSI=y | ||
| 101 | CONFIG_BLK_DEV_SD=y | ||
| 102 | CONFIG_BLK_DEV_SR=m | ||
| 103 | CONFIG_BLK_DEV_SR_VENDOR=y | ||
| 104 | CONFIG_CHR_DEV_SG=m | ||
| 105 | CONFIG_SCSI_MULTI_LUN=y | ||
| 106 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 107 | CONFIG_NETDEVICES=y | 88 | CONFIG_NETDEVICES=y |
| 108 | CONFIG_TUN=m | 89 | CONFIG_MII=y |
| 109 | CONFIG_ARM_AT91_ETHER=y | 90 | CONFIG_ARM_AT91_ETHER=y |
| 110 | CONFIG_PHYLIB=y | ||
| 111 | CONFIG_DAVICOM_PHY=y | 91 | CONFIG_DAVICOM_PHY=y |
| 112 | CONFIG_SMSC_PHY=y | 92 | CONFIG_SMSC_PHY=y |
| 113 | CONFIG_MICREL_PHY=y | 93 | CONFIG_MICREL_PHY=y |
| 114 | CONFIG_PPP=y | 94 | # CONFIG_WLAN is not set |
| 115 | CONFIG_PPP_BSDCOMP=y | 95 | # CONFIG_INPUT_MOUSEDEV is not set |
| 116 | CONFIG_PPP_DEFLATE=y | ||
| 117 | CONFIG_PPP_FILTER=y | ||
| 118 | CONFIG_PPP_MPPE=m | ||
| 119 | CONFIG_PPP_MULTILINK=y | ||
| 120 | CONFIG_PPPOE=m | ||
| 121 | CONFIG_PPP_ASYNC=y | ||
| 122 | CONFIG_SLIP=m | ||
| 123 | CONFIG_SLIP_COMPRESSED=y | ||
| 124 | CONFIG_SLIP_SMART=y | ||
| 125 | CONFIG_SLIP_MODE_SLIP6=y | ||
| 126 | CONFIG_USB_CATC=m | ||
| 127 | CONFIG_USB_KAWETH=m | ||
| 128 | CONFIG_USB_PEGASUS=m | ||
| 129 | CONFIG_USB_RTL8150=m | ||
| 130 | CONFIG_USB_USBNET=m | ||
| 131 | CONFIG_USB_NET_DM9601=m | ||
| 132 | CONFIG_USB_NET_GL620A=m | ||
| 133 | CONFIG_USB_NET_PLUSB=m | ||
| 134 | CONFIG_USB_NET_RNDIS_HOST=m | ||
| 135 | CONFIG_USB_ALI_M5632=y | ||
| 136 | CONFIG_USB_AN2720=y | ||
| 137 | CONFIG_USB_EPSON2888=y | ||
| 138 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 139 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 | ||
| 140 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 | ||
| 141 | CONFIG_INPUT_EVDEV=y | 96 | CONFIG_INPUT_EVDEV=y |
| 142 | CONFIG_KEYBOARD_GPIO=y | 97 | CONFIG_KEYBOARD_GPIO=y |
| 143 | # CONFIG_INPUT_MOUSE is not set | 98 | # CONFIG_INPUT_MOUSE is not set |
| 144 | CONFIG_INPUT_TOUCHSCREEN=y | 99 | CONFIG_INPUT_TOUCHSCREEN=y |
| 145 | CONFIG_LEGACY_PTY_COUNT=32 | 100 | # CONFIG_LEGACY_PTYS is not set |
| 146 | CONFIG_SERIAL_ATMEL=y | 101 | CONFIG_SERIAL_ATMEL=y |
| 147 | CONFIG_SERIAL_ATMEL_CONSOLE=y | 102 | CONFIG_SERIAL_ATMEL_CONSOLE=y |
| 148 | CONFIG_HW_RANDOM=y | 103 | CONFIG_HW_RANDOM=y |
| @@ -151,38 +106,8 @@ CONFIG_I2C_CHARDEV=y | |||
| 151 | CONFIG_I2C_GPIO=y | 106 | CONFIG_I2C_GPIO=y |
| 152 | CONFIG_SPI=y | 107 | CONFIG_SPI=y |
| 153 | CONFIG_SPI_ATMEL=y | 108 | CONFIG_SPI_ATMEL=y |
| 154 | CONFIG_SPI_BITBANG=y | ||
| 155 | CONFIG_GPIO_SYSFS=y | 109 | CONFIG_GPIO_SYSFS=y |
| 156 | CONFIG_HWMON=m | 110 | # CONFIG_HWMON is not set |
| 157 | CONFIG_SENSORS_ADM1021=m | ||
| 158 | CONFIG_SENSORS_ADM1025=m | ||
| 159 | CONFIG_SENSORS_ADM1026=m | ||
| 160 | CONFIG_SENSORS_ADM1029=m | ||
| 161 | CONFIG_SENSORS_ADM1031=m | ||
| 162 | CONFIG_SENSORS_ADM9240=m | ||
| 163 | CONFIG_SENSORS_DS1621=m | ||
| 164 | CONFIG_SENSORS_GL518SM=m | ||
| 165 | CONFIG_SENSORS_GL520SM=m | ||
| 166 | CONFIG_SENSORS_IT87=m | ||
| 167 | CONFIG_SENSORS_LM63=m | ||
| 168 | CONFIG_SENSORS_LM73=m | ||
| 169 | CONFIG_SENSORS_LM75=m | ||
| 170 | CONFIG_SENSORS_LM77=m | ||
| 171 | CONFIG_SENSORS_LM78=m | ||
| 172 | CONFIG_SENSORS_LM80=m | ||
| 173 | CONFIG_SENSORS_LM83=m | ||
| 174 | CONFIG_SENSORS_LM85=m | ||
| 175 | CONFIG_SENSORS_LM87=m | ||
| 176 | CONFIG_SENSORS_LM90=m | ||
| 177 | CONFIG_SENSORS_LM92=m | ||
| 178 | CONFIG_SENSORS_MAX1619=m | ||
| 179 | CONFIG_SENSORS_PCF8591=m | ||
| 180 | CONFIG_SENSORS_SMSC47B397=m | ||
| 181 | CONFIG_SENSORS_W83781D=m | ||
| 182 | CONFIG_SENSORS_W83791D=m | ||
| 183 | CONFIG_SENSORS_W83792D=m | ||
| 184 | CONFIG_SENSORS_W83793=m | ||
| 185 | CONFIG_SENSORS_W83L785TS=m | ||
| 186 | CONFIG_WATCHDOG=y | 111 | CONFIG_WATCHDOG=y |
| 187 | CONFIG_WATCHDOG_NOWAYOUT=y | 112 | CONFIG_WATCHDOG_NOWAYOUT=y |
| 188 | CONFIG_AT91RM9200_WATCHDOG=y | 113 | CONFIG_AT91RM9200_WATCHDOG=y |
| @@ -194,43 +119,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y | |||
| 194 | CONFIG_LCD_CLASS_DEVICE=y | 119 | CONFIG_LCD_CLASS_DEVICE=y |
| 195 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 120 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 196 | # CONFIG_BACKLIGHT_GENERIC is not set | 121 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 197 | CONFIG_DISPLAY_SUPPORT=y | ||
| 198 | CONFIG_FRAMEBUFFER_CONSOLE=y | 122 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 199 | CONFIG_FONTS=y | 123 | CONFIG_FONTS=y |
| 200 | CONFIG_FONT_MINI_4x6=y | ||
| 201 | CONFIG_LOGO=y | 124 | CONFIG_LOGO=y |
| 202 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 203 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 204 | CONFIG_USB=y | 125 | CONFIG_USB=y |
| 205 | CONFIG_USB_DEVICEFS=y | ||
| 206 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 207 | CONFIG_USB_MON=y | ||
| 208 | CONFIG_USB_OHCI_HCD=y | 126 | CONFIG_USB_OHCI_HCD=y |
| 209 | CONFIG_USB_ACM=m | ||
| 210 | CONFIG_USB_PRINTER=m | ||
| 211 | CONFIG_USB_STORAGE=y | ||
| 212 | CONFIG_USB_SERIAL=y | ||
| 213 | CONFIG_USB_SERIAL_CONSOLE=y | ||
| 214 | CONFIG_USB_SERIAL_GENERIC=y | ||
| 215 | CONFIG_USB_SERIAL_FTDI_SIO=y | ||
| 216 | CONFIG_USB_SERIAL_KEYSPAN=y | ||
| 217 | CONFIG_USB_SERIAL_KEYSPAN_MPR=y | ||
| 218 | CONFIG_USB_SERIAL_KEYSPAN_USA28=y | ||
| 219 | CONFIG_USB_SERIAL_KEYSPAN_USA28X=y | ||
| 220 | CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y | ||
| 221 | CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y | ||
| 222 | CONFIG_USB_SERIAL_KEYSPAN_USA19=y | ||
| 223 | CONFIG_USB_SERIAL_KEYSPAN_USA18X=y | ||
| 224 | CONFIG_USB_SERIAL_KEYSPAN_USA19W=y | ||
| 225 | CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y | ||
| 226 | CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y | ||
| 227 | CONFIG_USB_SERIAL_KEYSPAN_USA49W=y | ||
| 228 | CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y | ||
| 229 | CONFIG_USB_SERIAL_MCT_U232=y | ||
| 230 | CONFIG_USB_SERIAL_PL2303=y | ||
| 231 | CONFIG_USB_GADGET=y | 127 | CONFIG_USB_GADGET=y |
| 232 | CONFIG_USB_ETH=m | 128 | CONFIG_USB_AT91=y |
| 233 | CONFIG_USB_MASS_STORAGE=m | 129 | CONFIG_USB_G_SERIAL=y |
| 234 | CONFIG_MMC=y | 130 | CONFIG_MMC=y |
| 235 | CONFIG_MMC_ATMELMCI=y | 131 | CONFIG_MMC_ATMELMCI=y |
| 236 | CONFIG_NEW_LEDS=y | 132 | CONFIG_NEW_LEDS=y |
| @@ -240,84 +136,27 @@ CONFIG_LEDS_TRIGGERS=y | |||
| 240 | CONFIG_LEDS_TRIGGER_TIMER=y | 136 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 241 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 137 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 242 | CONFIG_LEDS_TRIGGER_GPIO=y | 138 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 243 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 244 | CONFIG_RTC_CLASS=y | 139 | CONFIG_RTC_CLASS=y |
| 245 | # CONFIG_RTC_HCTOSYS is not set | ||
| 246 | CONFIG_RTC_DRV_DS1307=y | ||
| 247 | CONFIG_RTC_DRV_PCF8563=y | ||
| 248 | CONFIG_RTC_DRV_AT91RM9200=y | 140 | CONFIG_RTC_DRV_AT91RM9200=y |
| 249 | CONFIG_EXT2_FS=y | 141 | CONFIG_EXT4_FS=y |
| 250 | CONFIG_EXT2_FS_XATTR=y | ||
| 251 | CONFIG_EXT3_FS=y | ||
| 252 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 253 | CONFIG_REISERFS_FS=y | ||
| 254 | CONFIG_AUTOFS4_FS=y | 142 | CONFIG_AUTOFS4_FS=y |
| 255 | CONFIG_ISO9660_FS=y | ||
| 256 | CONFIG_JOLIET=y | ||
| 257 | CONFIG_ZISOFS=y | ||
| 258 | CONFIG_UDF_FS=y | ||
| 259 | CONFIG_MSDOS_FS=y | ||
| 260 | CONFIG_VFAT_FS=y | 143 | CONFIG_VFAT_FS=y |
| 261 | CONFIG_NTFS_FS=m | ||
| 262 | CONFIG_TMPFS=y | 144 | CONFIG_TMPFS=y |
| 263 | CONFIG_CONFIGFS_FS=y | 145 | CONFIG_UBIFS_FS=y |
| 264 | CONFIG_JFFS2_FS=y | 146 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y |
| 265 | CONFIG_JFFS2_SUMMARY=y | ||
| 266 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 267 | CONFIG_JFFS2_LZO=y | ||
| 268 | CONFIG_JFFS2_RUBIN=y | ||
| 269 | CONFIG_CRAMFS=y | ||
| 270 | CONFIG_MINIX_FS=y | ||
| 271 | CONFIG_NFS_FS=y | 147 | CONFIG_NFS_FS=y |
| 272 | CONFIG_NFS_V3=y | ||
| 273 | CONFIG_NFS_V3_ACL=y | ||
| 274 | CONFIG_NFS_V4=y | ||
| 275 | CONFIG_ROOT_NFS=y | 148 | CONFIG_ROOT_NFS=y |
| 276 | CONFIG_NFSD=y | ||
| 277 | CONFIG_CIFS=m | ||
| 278 | CONFIG_PARTITION_ADVANCED=y | ||
| 279 | CONFIG_MAC_PARTITION=y | ||
| 280 | CONFIG_NLS_CODEPAGE_437=y | 149 | CONFIG_NLS_CODEPAGE_437=y |
| 281 | CONFIG_NLS_CODEPAGE_737=m | 150 | CONFIG_NLS_CODEPAGE_850=y |
| 282 | CONFIG_NLS_CODEPAGE_775=m | ||
| 283 | CONFIG_NLS_CODEPAGE_850=m | ||
| 284 | CONFIG_NLS_CODEPAGE_852=m | ||
| 285 | CONFIG_NLS_CODEPAGE_855=m | ||
| 286 | CONFIG_NLS_CODEPAGE_857=m | ||
| 287 | CONFIG_NLS_CODEPAGE_860=m | ||
| 288 | CONFIG_NLS_CODEPAGE_861=m | ||
| 289 | CONFIG_NLS_CODEPAGE_862=m | ||
| 290 | CONFIG_NLS_CODEPAGE_863=m | ||
| 291 | CONFIG_NLS_CODEPAGE_864=m | ||
| 292 | CONFIG_NLS_CODEPAGE_865=m | ||
| 293 | CONFIG_NLS_CODEPAGE_866=m | ||
| 294 | CONFIG_NLS_CODEPAGE_869=m | ||
| 295 | CONFIG_NLS_CODEPAGE_936=m | ||
| 296 | CONFIG_NLS_CODEPAGE_950=m | ||
| 297 | CONFIG_NLS_CODEPAGE_932=m | ||
| 298 | CONFIG_NLS_CODEPAGE_949=m | ||
| 299 | CONFIG_NLS_CODEPAGE_874=m | ||
| 300 | CONFIG_NLS_ISO8859_8=m | ||
| 301 | CONFIG_NLS_CODEPAGE_1250=m | ||
| 302 | CONFIG_NLS_CODEPAGE_1251=m | ||
| 303 | CONFIG_NLS_ASCII=m | ||
| 304 | CONFIG_NLS_ISO8859_1=y | 151 | CONFIG_NLS_ISO8859_1=y |
| 305 | CONFIG_NLS_ISO8859_2=m | ||
| 306 | CONFIG_NLS_ISO8859_3=m | ||
| 307 | CONFIG_NLS_ISO8859_4=m | ||
| 308 | CONFIG_NLS_ISO8859_5=m | ||
| 309 | CONFIG_NLS_ISO8859_6=m | ||
| 310 | CONFIG_NLS_ISO8859_7=m | ||
| 311 | CONFIG_NLS_ISO8859_9=m | ||
| 312 | CONFIG_NLS_ISO8859_13=m | ||
| 313 | CONFIG_NLS_ISO8859_14=m | ||
| 314 | CONFIG_NLS_ISO8859_15=m | ||
| 315 | CONFIG_NLS_KOI8_R=m | ||
| 316 | CONFIG_NLS_KOI8_U=m | ||
| 317 | CONFIG_NLS_UTF8=y | 152 | CONFIG_NLS_UTF8=y |
| 318 | CONFIG_MAGIC_SYSRQ=y | 153 | CONFIG_MAGIC_SYSRQ=y |
| 319 | CONFIG_DEBUG_FS=y | 154 | CONFIG_DEBUG_FS=y |
| 320 | CONFIG_DEBUG_KERNEL=y | 155 | CONFIG_DEBUG_KERNEL=y |
| 321 | # CONFIG_FTRACE is not set | 156 | # CONFIG_FTRACE is not set |
| 157 | CONFIG_DEBUG_USER=y | ||
| 158 | CONFIG_DEBUG_LL=y | ||
| 159 | CONFIG_EARLY_PRINTK=y | ||
| 322 | CONFIG_CRYPTO_PCBC=y | 160 | CONFIG_CRYPTO_PCBC=y |
| 323 | CONFIG_CRYPTO_SHA1=y | 161 | CONFIG_CRYPTO_SHA1=y |
| 162 | CONFIG_XZ_DEC_ARMTHUMB=y | ||
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig index 892e8287ed73..f50c404f0d3f 100644 --- a/arch/arm/configs/at91sam9g20_defconfig +++ b/arch/arm/configs/at91sam9260_9g20_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 4 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| @@ -11,7 +10,15 @@ CONFIG_MODULE_UNLOAD=y | |||
| 11 | # CONFIG_IOSCHED_DEADLINE is not set | 10 | # CONFIG_IOSCHED_DEADLINE is not set |
| 12 | # CONFIG_IOSCHED_CFQ is not set | 11 | # CONFIG_IOSCHED_CFQ is not set |
| 13 | CONFIG_ARCH_AT91=y | 12 | CONFIG_ARCH_AT91=y |
| 14 | CONFIG_ARCH_AT91SAM9G20=y | 13 | CONFIG_ARCH_AT91SAM9260=y |
| 14 | CONFIG_MACH_AT91SAM9260EK=y | ||
| 15 | CONFIG_MACH_CAM60=y | ||
| 16 | CONFIG_MACH_SAM9_L9260=y | ||
| 17 | CONFIG_MACH_AFEB9260=y | ||
| 18 | CONFIG_MACH_USB_A9260=y | ||
| 19 | CONFIG_MACH_QIL_A9260=y | ||
| 20 | CONFIG_MACH_CPU9260=y | ||
| 21 | CONFIG_MACH_FLEXIBITY=y | ||
| 15 | CONFIG_MACH_AT91SAM9G20EK=y | 22 | CONFIG_MACH_AT91SAM9G20EK=y |
| 16 | CONFIG_MACH_AT91SAM9G20EK_2MMC=y | 23 | CONFIG_MACH_AT91SAM9G20EK_2MMC=y |
| 17 | CONFIG_MACH_CPU9G20=y | 24 | CONFIG_MACH_CPU9G20=y |
| @@ -20,10 +27,10 @@ CONFIG_MACH_PORTUXG20=y | |||
| 20 | CONFIG_MACH_STAMP9G20=y | 27 | CONFIG_MACH_STAMP9G20=y |
| 21 | CONFIG_MACH_PCONTROL_G20=y | 28 | CONFIG_MACH_PCONTROL_G20=y |
| 22 | CONFIG_MACH_GSIA18S=y | 29 | CONFIG_MACH_GSIA18S=y |
| 23 | CONFIG_MACH_USB_A9G20=y | ||
| 24 | CONFIG_MACH_SNAPPER_9260=y | 30 | CONFIG_MACH_SNAPPER_9260=y |
| 25 | CONFIG_MACH_AT91SAM9_DT=y | 31 | CONFIG_MACH_AT91SAM9_DT=y |
| 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 32 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 33 | CONFIG_AT91_SLOW_CLOCK=y | ||
| 27 | # CONFIG_ARM_THUMB is not set | 34 | # CONFIG_ARM_THUMB is not set |
| 28 | CONFIG_AEABI=y | 35 | CONFIG_AEABI=y |
| 29 | CONFIG_LEDS=y | 36 | CONFIG_LEDS=y |
| @@ -33,12 +40,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0 | |||
| 33 | CONFIG_ARM_APPENDED_DTB=y | 40 | CONFIG_ARM_APPENDED_DTB=y |
| 34 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 41 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 35 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" | 42 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" |
| 43 | CONFIG_AUTO_ZRELADDR=y | ||
| 36 | CONFIG_FPE_NWFPE=y | 44 | CONFIG_FPE_NWFPE=y |
| 37 | CONFIG_NET=y | 45 | CONFIG_NET=y |
| 38 | CONFIG_PACKET=y | 46 | CONFIG_PACKET=y |
| 39 | CONFIG_UNIX=y | 47 | CONFIG_UNIX=y |
| 40 | CONFIG_INET=y | 48 | CONFIG_INET=y |
| 41 | CONFIG_IP_PNP=y | 49 | CONFIG_IP_PNP=y |
| 50 | CONFIG_IP_PNP_DHCP=y | ||
| 42 | CONFIG_IP_PNP_BOOTP=y | 51 | CONFIG_IP_PNP_BOOTP=y |
| 43 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 52 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 44 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 53 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| @@ -46,8 +55,11 @@ CONFIG_IP_PNP_BOOTP=y | |||
| 46 | # CONFIG_INET_LRO is not set | 55 | # CONFIG_INET_LRO is not set |
| 47 | # CONFIG_IPV6 is not set | 56 | # CONFIG_IPV6 is not set |
| 48 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 57 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 58 | CONFIG_DEVTMPFS=y | ||
| 59 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 49 | CONFIG_MTD=y | 60 | CONFIG_MTD=y |
| 50 | CONFIG_MTD_CMDLINE_PARTS=y | 61 | CONFIG_MTD_CMDLINE_PARTS=y |
| 62 | CONFIG_MTD_OF_PARTS=y | ||
| 51 | CONFIG_MTD_CHAR=y | 63 | CONFIG_MTD_CHAR=y |
| 52 | CONFIG_MTD_BLOCK=y | 64 | CONFIG_MTD_BLOCK=y |
| 53 | CONFIG_MTD_DATAFLASH=y | 65 | CONFIG_MTD_DATAFLASH=y |
| @@ -56,6 +68,8 @@ CONFIG_MTD_NAND_ATMEL=y | |||
| 56 | CONFIG_BLK_DEV_LOOP=y | 68 | CONFIG_BLK_DEV_LOOP=y |
| 57 | CONFIG_BLK_DEV_RAM=y | 69 | CONFIG_BLK_DEV_RAM=y |
| 58 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 70 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 71 | CONFIG_MISC_DEVICES=y | ||
| 72 | CONFIG_EEPROM_AT25=y | ||
| 59 | CONFIG_SCSI=y | 73 | CONFIG_SCSI=y |
| 60 | CONFIG_BLK_DEV_SD=y | 74 | CONFIG_BLK_DEV_SD=y |
| 61 | CONFIG_SCSI_MULTI_LUN=y | 75 | CONFIG_SCSI_MULTI_LUN=y |
| @@ -63,23 +77,36 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 63 | CONFIG_NETDEVICES=y | 77 | CONFIG_NETDEVICES=y |
| 64 | CONFIG_MII=y | 78 | CONFIG_MII=y |
| 65 | CONFIG_MACB=y | 79 | CONFIG_MACB=y |
| 80 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
| 81 | # CONFIG_NET_VENDOR_CHELSIO is not set | ||
| 82 | # CONFIG_NET_VENDOR_FARADAY is not set | ||
| 83 | # CONFIG_NET_VENDOR_INTEL is not set | ||
| 84 | # CONFIG_NET_VENDOR_MARVELL is not set | ||
| 85 | # CONFIG_NET_VENDOR_MICREL is not set | ||
| 86 | # CONFIG_NET_VENDOR_MICROCHIP is not set | ||
| 87 | # CONFIG_NET_VENDOR_NATSEMI is not set | ||
| 88 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
| 89 | # CONFIG_NET_VENDOR_SMSC is not set | ||
| 90 | # CONFIG_NET_VENDOR_STMICRO is not set | ||
| 91 | CONFIG_SMSC_PHY=y | ||
| 66 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 92 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 67 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 | ||
| 68 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 | ||
| 69 | CONFIG_INPUT_EVDEV=y | ||
| 70 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 71 | CONFIG_KEYBOARD_GPIO=y | 93 | CONFIG_KEYBOARD_GPIO=y |
| 72 | # CONFIG_INPUT_MOUSE is not set | 94 | # CONFIG_INPUT_MOUSE is not set |
| 73 | CONFIG_LEGACY_PTY_COUNT=16 | 95 | # CONFIG_SERIO is not set |
| 74 | CONFIG_SERIAL_ATMEL=y | 96 | CONFIG_SERIAL_ATMEL=y |
| 75 | CONFIG_SERIAL_ATMEL_CONSOLE=y | 97 | CONFIG_SERIAL_ATMEL_CONSOLE=y |
| 76 | CONFIG_HW_RANDOM=y | 98 | CONFIG_HW_RANDOM=y |
| 77 | CONFIG_I2C=y | 99 | CONFIG_I2C=y |
| 100 | CONFIG_I2C_CHARDEV=y | ||
| 78 | CONFIG_I2C_GPIO=y | 101 | CONFIG_I2C_GPIO=y |
| 79 | CONFIG_SPI=y | 102 | CONFIG_SPI=y |
| 80 | CONFIG_SPI_ATMEL=y | 103 | CONFIG_SPI_ATMEL=y |
| 81 | CONFIG_SPI_SPIDEV=y | 104 | CONFIG_SPI_SPIDEV=y |
| 105 | CONFIG_GPIO_SYSFS=y | ||
| 82 | # CONFIG_HWMON is not set | 106 | # CONFIG_HWMON is not set |
| 107 | CONFIG_WATCHDOG=y | ||
| 108 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 109 | CONFIG_AT91SAM9X_WATCHDOG=y | ||
| 83 | CONFIG_SOUND=y | 110 | CONFIG_SOUND=y |
| 84 | CONFIG_SND=y | 111 | CONFIG_SND=y |
| 85 | CONFIG_SND_SEQUENCER=y | 112 | CONFIG_SND_SEQUENCER=y |
| @@ -94,12 +121,11 @@ CONFIG_USB_MON=y | |||
| 94 | CONFIG_USB_OHCI_HCD=y | 121 | CONFIG_USB_OHCI_HCD=y |
| 95 | CONFIG_USB_STORAGE=y | 122 | CONFIG_USB_STORAGE=y |
| 96 | CONFIG_USB_GADGET=y | 123 | CONFIG_USB_GADGET=y |
| 97 | CONFIG_USB_ZERO=m | 124 | CONFIG_USB_AT91=y |
| 98 | CONFIG_USB_GADGETFS=m | 125 | CONFIG_USB_G_SERIAL=y |
| 99 | CONFIG_USB_MASS_STORAGE=m | ||
| 100 | CONFIG_USB_G_SERIAL=m | ||
| 101 | CONFIG_MMC=y | 126 | CONFIG_MMC=y |
| 102 | CONFIG_MMC_ATMELMCI=m | 127 | CONFIG_MMC_ATMELMCI=y |
| 128 | CONFIG_MMC_SPI=y | ||
| 103 | CONFIG_NEW_LEDS=y | 129 | CONFIG_NEW_LEDS=y |
| 104 | CONFIG_LEDS_CLASS=y | 130 | CONFIG_LEDS_CLASS=y |
| 105 | CONFIG_LEDS_GPIO=y | 131 | CONFIG_LEDS_GPIO=y |
| @@ -109,15 +135,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y | |||
| 109 | CONFIG_RTC_CLASS=y | 135 | CONFIG_RTC_CLASS=y |
| 110 | CONFIG_RTC_DRV_RV3029C2=y | 136 | CONFIG_RTC_DRV_RV3029C2=y |
| 111 | CONFIG_RTC_DRV_AT91SAM9=y | 137 | CONFIG_RTC_DRV_AT91SAM9=y |
| 112 | CONFIG_EXT2_FS=y | 138 | CONFIG_EXT4_FS=y |
| 113 | CONFIG_MSDOS_FS=y | ||
| 114 | CONFIG_VFAT_FS=y | 139 | CONFIG_VFAT_FS=y |
| 115 | CONFIG_TMPFS=y | 140 | CONFIG_TMPFS=y |
| 116 | CONFIG_JFFS2_FS=y | 141 | CONFIG_UBIFS_FS=y |
| 117 | CONFIG_JFFS2_SUMMARY=y | 142 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y |
| 118 | CONFIG_CRAMFS=y | ||
| 119 | CONFIG_NFS_FS=y | 143 | CONFIG_NFS_FS=y |
| 120 | CONFIG_NFS_V3=y | ||
| 121 | CONFIG_ROOT_NFS=y | 144 | CONFIG_ROOT_NFS=y |
| 122 | CONFIG_NLS_CODEPAGE_437=y | 145 | CONFIG_NLS_CODEPAGE_437=y |
| 123 | CONFIG_NLS_CODEPAGE_850=y | 146 | CONFIG_NLS_CODEPAGE_850=y |
| @@ -125,3 +148,9 @@ CONFIG_NLS_ISO8859_1=y | |||
| 125 | CONFIG_NLS_ISO8859_15=y | 148 | CONFIG_NLS_ISO8859_15=y |
| 126 | CONFIG_NLS_UTF8=y | 149 | CONFIG_NLS_UTF8=y |
| 127 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 150 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 151 | CONFIG_DEBUG_KERNEL=y | ||
| 152 | CONFIG_DEBUG_INFO=y | ||
| 153 | # CONFIG_FTRACE is not set | ||
| 154 | CONFIG_DEBUG_LL=y | ||
| 155 | CONFIG_AT91_DEBUG_LL_DBGU0=y | ||
| 156 | CONFIG_EARLY_PRINTK=y | ||
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig deleted file mode 100644 index 05618eb694f8..000000000000 --- a/arch/arm/configs/at91sam9260_defconfig +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 3 | # CONFIG_SWAP is not set | ||
| 4 | CONFIG_SYSVIPC=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_BLK_DEV_INITRD=y | ||
| 7 | CONFIG_SLAB=y | ||
| 8 | CONFIG_MODULES=y | ||
| 9 | CONFIG_MODULE_UNLOAD=y | ||
| 10 | # CONFIG_BLK_DEV_BSG is not set | ||
| 11 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 12 | # CONFIG_IOSCHED_CFQ is not set | ||
| 13 | CONFIG_ARCH_AT91=y | ||
| 14 | CONFIG_ARCH_AT91SAM9260=y | ||
| 15 | CONFIG_ARCH_AT91SAM9260_SAM9XE=y | ||
| 16 | CONFIG_MACH_AT91SAM9260EK=y | ||
| 17 | CONFIG_MACH_CAM60=y | ||
| 18 | CONFIG_MACH_SAM9_L9260=y | ||
| 19 | CONFIG_MACH_AFEB9260=y | ||
| 20 | CONFIG_MACH_USB_A9260=y | ||
| 21 | CONFIG_MACH_QIL_A9260=y | ||
| 22 | CONFIG_MACH_CPU9260=y | ||
| 23 | CONFIG_MACH_FLEXIBITY=y | ||
| 24 | CONFIG_MACH_SNAPPER_9260=y | ||
| 25 | CONFIG_MACH_AT91SAM9_DT=y | ||
| 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | ||
| 27 | # CONFIG_ARM_THUMB is not set | ||
| 28 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 29 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 30 | CONFIG_ARM_APPENDED_DTB=y | ||
| 31 | CONFIG_ARM_ATAG_DTB_COMPAT=y | ||
| 32 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" | ||
| 33 | CONFIG_FPE_NWFPE=y | ||
| 34 | CONFIG_NET=y | ||
| 35 | CONFIG_PACKET=y | ||
| 36 | CONFIG_UNIX=y | ||
| 37 | CONFIG_INET=y | ||
| 38 | CONFIG_IP_PNP=y | ||
| 39 | CONFIG_IP_PNP_BOOTP=y | ||
| 40 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 41 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 42 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 43 | # CONFIG_INET_LRO is not set | ||
| 44 | # CONFIG_IPV6 is not set | ||
| 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 46 | CONFIG_BLK_DEV_RAM=y | ||
| 47 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 48 | CONFIG_SCSI=y | ||
| 49 | CONFIG_BLK_DEV_SD=y | ||
| 50 | CONFIG_SCSI_MULTI_LUN=y | ||
| 51 | CONFIG_NETDEVICES=y | ||
| 52 | CONFIG_MII=y | ||
| 53 | CONFIG_MACB=y | ||
| 54 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 55 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 56 | # CONFIG_INPUT_MOUSE is not set | ||
| 57 | # CONFIG_SERIO is not set | ||
| 58 | CONFIG_SERIAL_ATMEL=y | ||
| 59 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 60 | # CONFIG_HW_RANDOM is not set | ||
| 61 | CONFIG_I2C=y | ||
| 62 | CONFIG_I2C_CHARDEV=y | ||
| 63 | CONFIG_I2C_GPIO=y | ||
| 64 | # CONFIG_HWMON is not set | ||
| 65 | CONFIG_WATCHDOG=y | ||
| 66 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 67 | CONFIG_AT91SAM9X_WATCHDOG=y | ||
| 68 | # CONFIG_USB_HID is not set | ||
| 69 | CONFIG_USB=y | ||
| 70 | CONFIG_USB_DEVICEFS=y | ||
| 71 | CONFIG_USB_MON=y | ||
| 72 | CONFIG_USB_OHCI_HCD=y | ||
| 73 | CONFIG_USB_STORAGE=y | ||
| 74 | CONFIG_USB_STORAGE_DEBUG=y | ||
| 75 | CONFIG_USB_GADGET=y | ||
| 76 | CONFIG_USB_ZERO=m | ||
| 77 | CONFIG_USB_GADGETFS=m | ||
| 78 | CONFIG_USB_MASS_STORAGE=m | ||
| 79 | CONFIG_USB_G_SERIAL=m | ||
| 80 | CONFIG_RTC_CLASS=y | ||
| 81 | CONFIG_RTC_DRV_AT91SAM9=y | ||
| 82 | CONFIG_EXT2_FS=y | ||
| 83 | CONFIG_VFAT_FS=y | ||
| 84 | CONFIG_TMPFS=y | ||
| 85 | CONFIG_CRAMFS=y | ||
| 86 | CONFIG_NLS_CODEPAGE_437=y | ||
| 87 | CONFIG_NLS_CODEPAGE_850=y | ||
| 88 | CONFIG_NLS_ISO8859_1=y | ||
| 89 | CONFIG_DEBUG_KERNEL=y | ||
| 90 | CONFIG_DEBUG_USER=y | ||
| 91 | CONFIG_DEBUG_LL=y | ||
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig index c87beb973b37..9d35cd81c611 100644 --- a/arch/arm/configs/at91sam9261_defconfig +++ b/arch/arm/configs/at91sam9261_9g10_defconfig | |||
| @@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y | |||
| 17 | CONFIG_ARCH_AT91=y | 17 | CONFIG_ARCH_AT91=y |
| 18 | CONFIG_ARCH_AT91SAM9261=y | 18 | CONFIG_ARCH_AT91SAM9261=y |
| 19 | CONFIG_MACH_AT91SAM9261EK=y | 19 | CONFIG_MACH_AT91SAM9261EK=y |
| 20 | CONFIG_MACH_AT91SAM9G10EK=y | ||
| 20 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 21 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 21 | # CONFIG_ARM_THUMB is not set | 22 | # CONFIG_ARM_THUMB is not set |
| 22 | CONFIG_AEABI=y | 23 | CONFIG_AEABI=y |
| @@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y | |||
| 38 | # CONFIG_INET_LRO is not set | 39 | # CONFIG_INET_LRO is not set |
| 39 | # CONFIG_IPV6 is not set | 40 | # CONFIG_IPV6 is not set |
| 40 | CONFIG_CFG80211=y | 41 | CONFIG_CFG80211=y |
| 41 | CONFIG_LIB80211=y | ||
| 42 | CONFIG_MAC80211=y | 42 | CONFIG_MAC80211=y |
| 43 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 43 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 44 | CONFIG_DEVTMPFS=y | ||
| 45 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 44 | CONFIG_MTD=y | 46 | CONFIG_MTD=y |
| 45 | CONFIG_MTD_PARTITIONS=y | ||
| 46 | CONFIG_MTD_CMDLINE_PARTS=y | 47 | CONFIG_MTD_CMDLINE_PARTS=y |
| 47 | CONFIG_MTD_BLOCK=y | 48 | CONFIG_MTD_BLOCK=y |
| 48 | CONFIG_MTD_NAND=y | 49 | CONFIG_MTD_NAND=y |
| @@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y | |||
| 51 | CONFIG_MTD_UBI_GLUEBI=y | 52 | CONFIG_MTD_UBI_GLUEBI=y |
| 52 | CONFIG_BLK_DEV_RAM=y | 53 | CONFIG_BLK_DEV_RAM=y |
| 53 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 54 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 54 | CONFIG_MISC_DEVICES=y | ||
| 55 | CONFIG_ATMEL_TCLIB=y | 55 | CONFIG_ATMEL_TCLIB=y |
| 56 | CONFIG_ATMEL_SSC=y | 56 | CONFIG_ATMEL_SSC=y |
| 57 | CONFIG_SCSI=y | 57 | CONFIG_SCSI=y |
| 58 | CONFIG_BLK_DEV_SD=y | 58 | CONFIG_BLK_DEV_SD=y |
| 59 | CONFIG_SCSI_MULTI_LUN=y | 59 | CONFIG_SCSI_MULTI_LUN=y |
| 60 | CONFIG_NETDEVICES=y | 60 | CONFIG_NETDEVICES=y |
| 61 | CONFIG_NET_ETHERNET=y | ||
| 62 | CONFIG_DM9000=y | 61 | CONFIG_DM9000=y |
| 63 | # CONFIG_NETDEV_1000 is not set | ||
| 64 | # CONFIG_NETDEV_10000 is not set | ||
| 65 | CONFIG_USB_ZD1201=m | 62 | CONFIG_USB_ZD1201=m |
| 66 | CONFIG_RTL8187=m | 63 | CONFIG_RTL8187=m |
| 67 | CONFIG_LIBERTAS=m | 64 | CONFIG_LIBERTAS=m |
| @@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y | |||
| 118 | CONFIG_SND_USB_AUDIO=m | 115 | CONFIG_SND_USB_AUDIO=m |
| 119 | # CONFIG_USB_HID is not set | 116 | # CONFIG_USB_HID is not set |
| 120 | CONFIG_USB=y | 117 | CONFIG_USB=y |
| 121 | CONFIG_USB_DEVICEFS=y | ||
| 122 | CONFIG_USB_OHCI_HCD=y | 118 | CONFIG_USB_OHCI_HCD=y |
| 123 | CONFIG_USB_STORAGE=y | 119 | CONFIG_USB_STORAGE=y |
| 124 | CONFIG_USB_GADGET=y | 120 | CONFIG_USB_GADGET=y |
| 125 | CONFIG_USB_ZERO=m | 121 | CONFIG_USB_AT91=y |
| 126 | CONFIG_USB_ETH=m | 122 | CONFIG_USB_G_SERIAL=y |
| 127 | CONFIG_USB_GADGETFS=m | ||
| 128 | CONFIG_USB_MASS_STORAGE=m | ||
| 129 | CONFIG_USB_G_SERIAL=m | ||
| 130 | CONFIG_MMC=y | 123 | CONFIG_MMC=y |
| 131 | CONFIG_MMC_ATMELMCI=m | 124 | CONFIG_MMC_ATMELMCI=m |
| 132 | CONFIG_NEW_LEDS=y | 125 | CONFIG_NEW_LEDS=y |
| @@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y | |||
| 147 | CONFIG_SQUASHFS_LZO=y | 140 | CONFIG_SQUASHFS_LZO=y |
| 148 | CONFIG_SQUASHFS_XZ=y | 141 | CONFIG_SQUASHFS_XZ=y |
| 149 | CONFIG_NFS_FS=y | 142 | CONFIG_NFS_FS=y |
| 150 | CONFIG_NFS_V3=y | ||
| 151 | CONFIG_ROOT_NFS=y | 143 | CONFIG_ROOT_NFS=y |
| 152 | CONFIG_NLS_CODEPAGE_437=y | 144 | CONFIG_NLS_CODEPAGE_437=y |
| 153 | CONFIG_NLS_CODEPAGE_850=y | 145 | CONFIG_NLS_CODEPAGE_850=y |
| 154 | CONFIG_NLS_ISO8859_1=y | 146 | CONFIG_NLS_ISO8859_1=y |
| 155 | CONFIG_NLS_ISO8859_15=y | 147 | CONFIG_NLS_ISO8859_15=y |
| 156 | CONFIG_NLS_UTF8=y | 148 | CONFIG_NLS_UTF8=y |
| 157 | CONFIG_FTRACE=y | ||
| 158 | CONFIG_CRC_CCITT=m | 149 | CONFIG_CRC_CCITT=m |
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig index 36fed66bd4b5..9d72ab684829 100644 --- a/arch/arm/configs/at91sam9263_defconfig +++ b/arch/arm/configs/at91sam9263_defconfig | |||
| @@ -1,6 +1,4 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | CONFIG_KERNEL_LZMA=y | ||
| 4 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 5 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 6 | CONFIG_IKCONFIG=y | 4 | CONFIG_IKCONFIG=y |
| @@ -48,9 +46,11 @@ CONFIG_IP_PIMSM_V2=y | |||
| 48 | # CONFIG_INET_LRO is not set | 46 | # CONFIG_INET_LRO is not set |
| 49 | # CONFIG_INET_DIAG is not set | 47 | # CONFIG_INET_DIAG is not set |
| 50 | CONFIG_IPV6=y | 48 | CONFIG_IPV6=y |
| 49 | # CONFIG_WIRELESS is not set | ||
| 51 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 50 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 51 | CONFIG_DEVTMPFS=y | ||
| 52 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 52 | CONFIG_MTD=y | 53 | CONFIG_MTD=y |
| 53 | CONFIG_MTD_PARTITIONS=y | ||
| 54 | CONFIG_MTD_CMDLINE_PARTS=y | 54 | CONFIG_MTD_CMDLINE_PARTS=y |
| 55 | CONFIG_MTD_CHAR=y | 55 | CONFIG_MTD_CHAR=y |
| 56 | CONFIG_MTD_BLOCK=y | 56 | CONFIG_MTD_BLOCK=y |
| @@ -65,7 +65,6 @@ CONFIG_MTD_UBI_GLUEBI=y | |||
| 65 | CONFIG_BLK_DEV_LOOP=y | 65 | CONFIG_BLK_DEV_LOOP=y |
| 66 | CONFIG_BLK_DEV_RAM=y | 66 | CONFIG_BLK_DEV_RAM=y |
| 67 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 67 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 68 | CONFIG_MISC_DEVICES=y | ||
| 69 | CONFIG_ATMEL_PWM=y | 68 | CONFIG_ATMEL_PWM=y |
| 70 | CONFIG_ATMEL_TCLIB=y | 69 | CONFIG_ATMEL_TCLIB=y |
| 71 | CONFIG_SCSI=y | 70 | CONFIG_SCSI=y |
| @@ -73,23 +72,18 @@ CONFIG_BLK_DEV_SD=y | |||
| 73 | CONFIG_SCSI_MULTI_LUN=y | 72 | CONFIG_SCSI_MULTI_LUN=y |
| 74 | CONFIG_NETDEVICES=y | 73 | CONFIG_NETDEVICES=y |
| 75 | CONFIG_MII=y | 74 | CONFIG_MII=y |
| 76 | CONFIG_SMSC_PHY=y | ||
| 77 | CONFIG_NET_ETHERNET=y | ||
| 78 | CONFIG_MACB=y | 75 | CONFIG_MACB=y |
| 79 | # CONFIG_NETDEV_1000 is not set | 76 | CONFIG_SMSC_PHY=y |
| 80 | # CONFIG_NETDEV_10000 is not set | 77 | # CONFIG_WLAN is not set |
| 81 | CONFIG_USB_ZD1201=m | ||
| 82 | CONFIG_INPUT_POLLDEV=m | 78 | CONFIG_INPUT_POLLDEV=m |
| 83 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 79 | # CONFIG_INPUT_MOUSEDEV is not set |
| 84 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 | ||
| 85 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | ||
| 86 | CONFIG_INPUT_EVDEV=y | 80 | CONFIG_INPUT_EVDEV=y |
| 87 | # CONFIG_KEYBOARD_ATKBD is not set | 81 | # CONFIG_KEYBOARD_ATKBD is not set |
| 88 | CONFIG_KEYBOARD_GPIO=y | 82 | CONFIG_KEYBOARD_GPIO=y |
| 89 | # CONFIG_INPUT_MOUSE is not set | 83 | # CONFIG_INPUT_MOUSE is not set |
| 90 | CONFIG_INPUT_TOUCHSCREEN=y | 84 | CONFIG_INPUT_TOUCHSCREEN=y |
| 91 | CONFIG_TOUCHSCREEN_ADS7846=y | 85 | CONFIG_TOUCHSCREEN_ADS7846=y |
| 92 | CONFIG_LEGACY_PTY_COUNT=4 | 86 | # CONFIG_LEGACY_PTYS is not set |
| 93 | CONFIG_SERIAL_ATMEL=y | 87 | CONFIG_SERIAL_ATMEL=y |
| 94 | CONFIG_SERIAL_ATMEL_CONSOLE=y | 88 | CONFIG_SERIAL_ATMEL_CONSOLE=y |
| 95 | CONFIG_HW_RANDOM=y | 89 | CONFIG_HW_RANDOM=y |
| @@ -98,6 +92,7 @@ CONFIG_I2C_CHARDEV=y | |||
| 98 | CONFIG_I2C_GPIO=y | 92 | CONFIG_I2C_GPIO=y |
| 99 | CONFIG_SPI=y | 93 | CONFIG_SPI=y |
| 100 | CONFIG_SPI_ATMEL=y | 94 | CONFIG_SPI_ATMEL=y |
| 95 | CONFIG_GPIO_SYSFS=y | ||
| 101 | # CONFIG_HWMON is not set | 96 | # CONFIG_HWMON is not set |
| 102 | CONFIG_WATCHDOG=y | 97 | CONFIG_WATCHDOG=y |
| 103 | CONFIG_WATCHDOG_NOWAYOUT=y | 98 | CONFIG_WATCHDOG_NOWAYOUT=y |
| @@ -107,9 +102,9 @@ CONFIG_FB_ATMEL=y | |||
| 107 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 102 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 108 | CONFIG_LCD_CLASS_DEVICE=y | 103 | CONFIG_LCD_CLASS_DEVICE=y |
| 109 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 104 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 110 | CONFIG_BACKLIGHT_ATMEL_LCDC=y | ||
| 111 | CONFIG_FRAMEBUFFER_CONSOLE=y | 105 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 112 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | 106 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y |
| 107 | CONFIG_FONTS=y | ||
| 113 | CONFIG_LOGO=y | 108 | CONFIG_LOGO=y |
| 114 | CONFIG_SOUND=y | 109 | CONFIG_SOUND=y |
| 115 | CONFIG_SND=y | 110 | CONFIG_SND=y |
| @@ -124,16 +119,12 @@ CONFIG_SND_ATMEL_AC97C=y | |||
| 124 | # CONFIG_SND_SPI is not set | 119 | # CONFIG_SND_SPI is not set |
| 125 | CONFIG_SND_USB_AUDIO=m | 120 | CONFIG_SND_USB_AUDIO=m |
| 126 | CONFIG_USB=y | 121 | CONFIG_USB=y |
| 127 | CONFIG_USB_DEVICEFS=y | ||
| 128 | CONFIG_USB_MON=y | 122 | CONFIG_USB_MON=y |
| 129 | CONFIG_USB_OHCI_HCD=y | 123 | CONFIG_USB_OHCI_HCD=y |
| 130 | CONFIG_USB_STORAGE=y | 124 | CONFIG_USB_STORAGE=y |
| 131 | CONFIG_USB_GADGET=y | 125 | CONFIG_USB_GADGET=y |
| 132 | CONFIG_USB_ZERO=m | 126 | CONFIG_USB_ATMEL_USBA=y |
| 133 | CONFIG_USB_ETH=m | 127 | CONFIG_USB_G_SERIAL=y |
| 134 | CONFIG_USB_GADGETFS=m | ||
| 135 | CONFIG_USB_MASS_STORAGE=m | ||
| 136 | CONFIG_USB_G_SERIAL=m | ||
| 137 | CONFIG_MMC=y | 128 | CONFIG_MMC=y |
| 138 | CONFIG_SDIO_UART=m | 129 | CONFIG_SDIO_UART=m |
| 139 | CONFIG_MMC_ATMELMCI=m | 130 | CONFIG_MMC_ATMELMCI=m |
| @@ -145,22 +136,18 @@ CONFIG_LEDS_TRIGGERS=y | |||
| 145 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 136 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 146 | CONFIG_RTC_CLASS=y | 137 | CONFIG_RTC_CLASS=y |
| 147 | CONFIG_RTC_DRV_AT91SAM9=y | 138 | CONFIG_RTC_DRV_AT91SAM9=y |
| 148 | CONFIG_EXT2_FS=y | 139 | CONFIG_EXT4_FS=y |
| 149 | CONFIG_FUSE_FS=m | ||
| 150 | CONFIG_VFAT_FS=y | 140 | CONFIG_VFAT_FS=y |
| 151 | CONFIG_TMPFS=y | 141 | CONFIG_TMPFS=y |
| 152 | CONFIG_JFFS2_FS=y | ||
| 153 | CONFIG_UBIFS_FS=y | 142 | CONFIG_UBIFS_FS=y |
| 154 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y | 143 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y |
| 155 | CONFIG_CRAMFS=y | ||
| 156 | CONFIG_NFS_FS=y | 144 | CONFIG_NFS_FS=y |
| 157 | CONFIG_NFS_V3=y | ||
| 158 | CONFIG_NFS_V3_ACL=y | 145 | CONFIG_NFS_V3_ACL=y |
| 159 | CONFIG_NFS_V4=y | 146 | CONFIG_NFS_V4=y |
| 160 | CONFIG_ROOT_NFS=y | 147 | CONFIG_ROOT_NFS=y |
| 161 | CONFIG_NLS_CODEPAGE_437=y | 148 | CONFIG_NLS_CODEPAGE_437=y |
| 162 | CONFIG_NLS_CODEPAGE_850=y | 149 | CONFIG_NLS_CODEPAGE_850=y |
| 163 | CONFIG_NLS_ISO8859_1=y | 150 | CONFIG_NLS_ISO8859_1=y |
| 164 | CONFIG_FTRACE=y | 151 | CONFIG_NLS_UTF8=y |
| 165 | CONFIG_DEBUG_USER=y | 152 | CONFIG_DEBUG_USER=y |
| 166 | CONFIG_XZ_DEC=y | 153 | CONFIG_XZ_DEC=y |
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig index 18964cdacd68..08166cd4e7d6 100644 --- a/arch/arm/configs/at91sam9g45_defconfig +++ b/arch/arm/configs/at91sam9g45_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 4 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| @@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | |||
| 23 | CONFIG_AT91_SLOW_CLOCK=y | 22 | CONFIG_AT91_SLOW_CLOCK=y |
| 24 | CONFIG_AEABI=y | 23 | CONFIG_AEABI=y |
| 25 | # CONFIG_OABI_COMPAT is not set | 24 | # CONFIG_OABI_COMPAT is not set |
| 26 | CONFIG_LEDS=y | ||
| 27 | CONFIG_LEDS_CPU=y | ||
| 28 | CONFIG_UACCESS_WITH_MEMCPY=y | 25 | CONFIG_UACCESS_WITH_MEMCPY=y |
| 29 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 30 | CONFIG_ZBOOT_ROM_BSS=0x0 | 27 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| @@ -36,6 +33,9 @@ CONFIG_PACKET=y | |||
| 36 | CONFIG_UNIX=y | 33 | CONFIG_UNIX=y |
| 37 | CONFIG_INET=y | 34 | CONFIG_INET=y |
| 38 | CONFIG_IP_MULTICAST=y | 35 | CONFIG_IP_MULTICAST=y |
| 36 | CONFIG_IP_PNP=y | ||
| 37 | CONFIG_IP_PNP_DHCP=y | ||
| 38 | CONFIG_IP_PNP_BOOTP=y | ||
| 39 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 39 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 40 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 40 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 41 | # CONFIG_INET_XFRM_MODE_BEET is not set | 41 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| @@ -45,9 +45,6 @@ CONFIG_IPV6=y | |||
| 45 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set | 45 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set |
| 46 | # CONFIG_INET6_XFRM_MODE_BEET is not set | 46 | # CONFIG_INET6_XFRM_MODE_BEET is not set |
| 47 | CONFIG_IPV6_SIT_6RD=y | 47 | CONFIG_IPV6_SIT_6RD=y |
| 48 | CONFIG_CFG80211=y | ||
| 49 | CONFIG_LIB80211=y | ||
| 50 | CONFIG_MAC80211=y | ||
| 51 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 48 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 52 | CONFIG_DEVTMPFS=y | 49 | CONFIG_DEVTMPFS=y |
| 53 | CONFIG_DEVTMPFS_MOUNT=y | 50 | CONFIG_DEVTMPFS_MOUNT=y |
| @@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y | |||
| 61 | CONFIG_MTD_NAND=y | 58 | CONFIG_MTD_NAND=y |
| 62 | CONFIG_MTD_NAND_ATMEL=y | 59 | CONFIG_MTD_NAND_ATMEL=y |
| 63 | CONFIG_MTD_UBI=y | 60 | CONFIG_MTD_UBI=y |
| 61 | CONFIG_MTD_UBI_GLUEBI=y | ||
| 64 | CONFIG_BLK_DEV_LOOP=y | 62 | CONFIG_BLK_DEV_LOOP=y |
| 65 | CONFIG_BLK_DEV_RAM=y | 63 | CONFIG_BLK_DEV_RAM=y |
| 66 | CONFIG_BLK_DEV_RAM_COUNT=4 | 64 | CONFIG_BLK_DEV_RAM_COUNT=4 |
| 67 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 65 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 68 | CONFIG_MISC_DEVICES=y | ||
| 69 | CONFIG_ATMEL_PWM=y | 66 | CONFIG_ATMEL_PWM=y |
| 70 | CONFIG_ATMEL_TCLIB=y | 67 | CONFIG_ATMEL_TCLIB=y |
| 68 | CONFIG_ATMEL_SSC=y | ||
| 71 | CONFIG_SCSI=y | 69 | CONFIG_SCSI=y |
| 72 | CONFIG_BLK_DEV_SD=y | 70 | CONFIG_BLK_DEV_SD=y |
| 73 | CONFIG_SCSI_MULTI_LUN=y | 71 | CONFIG_SCSI_MULTI_LUN=y |
| @@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y | |||
| 76 | CONFIG_MII=y | 74 | CONFIG_MII=y |
| 77 | CONFIG_MACB=y | 75 | CONFIG_MACB=y |
| 78 | CONFIG_DAVICOM_PHY=y | 76 | CONFIG_DAVICOM_PHY=y |
| 79 | CONFIG_LIBERTAS_THINFIRM=m | 77 | # CONFIG_INPUT_MOUSEDEV is not set |
| 80 | CONFIG_LIBERTAS_THINFIRM_USB=m | ||
| 81 | CONFIG_AT76C50X_USB=m | ||
| 82 | CONFIG_USB_ZD1201=m | ||
| 83 | CONFIG_RTL8187=m | ||
| 84 | CONFIG_ATH_COMMON=m | ||
| 85 | CONFIG_ATH9K=m | ||
| 86 | CONFIG_CARL9170=m | ||
| 87 | CONFIG_B43=m | ||
| 88 | CONFIG_B43_PHY_N=y | ||
| 89 | CONFIG_LIBERTAS=m | ||
| 90 | CONFIG_LIBERTAS_USB=m | ||
| 91 | CONFIG_LIBERTAS_SDIO=m | ||
| 92 | CONFIG_LIBERTAS_SPI=m | ||
| 93 | CONFIG_RT2X00=m | ||
| 94 | CONFIG_RT2500USB=m | ||
| 95 | CONFIG_RT73USB=m | ||
| 96 | CONFIG_RT2800USB=m | ||
| 97 | CONFIG_RT2800USB_RT53XX=y | ||
| 98 | CONFIG_RT2800USB_UNKNOWN=y | ||
| 99 | CONFIG_RTL8192CU=m | ||
| 100 | CONFIG_WL1251=m | ||
| 101 | CONFIG_WL1251_SDIO=m | ||
| 102 | CONFIG_WL12XX_MENU=m | ||
| 103 | CONFIG_WL12XX=m | ||
| 104 | CONFIG_WL12XX_SDIO=m | ||
| 105 | CONFIG_ZD1211RW=m | ||
| 106 | CONFIG_MWIFIEX=m | ||
| 107 | CONFIG_MWIFIEX_SDIO=m | ||
| 108 | CONFIG_INPUT_POLLDEV=m | ||
| 109 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 110 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 | ||
| 111 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 | ||
| 112 | CONFIG_INPUT_JOYDEV=y | 78 | CONFIG_INPUT_JOYDEV=y |
| 113 | CONFIG_INPUT_EVDEV=y | 79 | CONFIG_INPUT_EVDEV=y |
| 114 | # CONFIG_KEYBOARD_ATKBD is not set | 80 | # CONFIG_KEYBOARD_ATKBD is not set |
| 115 | CONFIG_KEYBOARD_QT1070=m | 81 | CONFIG_KEYBOARD_QT1070=y |
| 116 | CONFIG_KEYBOARD_QT2160=m | 82 | CONFIG_KEYBOARD_QT2160=y |
| 117 | CONFIG_KEYBOARD_GPIO=y | 83 | CONFIG_KEYBOARD_GPIO=y |
| 118 | # CONFIG_INPUT_MOUSE is not set | 84 | # CONFIG_INPUT_MOUSE is not set |
| 119 | CONFIG_INPUT_TOUCHSCREEN=y | 85 | CONFIG_INPUT_TOUCHSCREEN=y |
| 120 | CONFIG_TOUCHSCREEN_ATMEL_MXT=m | 86 | CONFIG_TOUCHSCREEN_ATMEL_MXT=m |
| 121 | CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y | 87 | CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y |
| 122 | # CONFIG_SERIO is not set | 88 | # CONFIG_SERIO is not set |
| 123 | CONFIG_LEGACY_PTY_COUNT=4 | 89 | # CONFIG_LEGACY_PTYS is not set |
| 124 | CONFIG_SERIAL_ATMEL=y | 90 | CONFIG_SERIAL_ATMEL=y |
| 125 | CONFIG_SERIAL_ATMEL_CONSOLE=y | 91 | CONFIG_SERIAL_ATMEL_CONSOLE=y |
| 126 | CONFIG_HW_RANDOM=y | 92 | CONFIG_HW_RANDOM=y |
| 127 | CONFIG_I2C=y | 93 | CONFIG_I2C=y |
| 94 | CONFIG_I2C_CHARDEV=y | ||
| 128 | CONFIG_I2C_GPIO=y | 95 | CONFIG_I2C_GPIO=y |
| 129 | CONFIG_SPI=y | 96 | CONFIG_SPI=y |
| 130 | CONFIG_SPI_ATMEL=y | 97 | CONFIG_SPI_ATMEL=y |
| 131 | # CONFIG_HWMON is not set | 98 | # CONFIG_HWMON is not set |
| 132 | CONFIG_FB=y | 99 | CONFIG_FB=y |
| 133 | CONFIG_FB_ATMEL=y | 100 | CONFIG_FB_ATMEL=y |
| 134 | CONFIG_FB_UDL=m | ||
| 135 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 101 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 136 | # CONFIG_LCD_CLASS_DEVICE is not set | 102 | CONFIG_LCD_CLASS_DEVICE=y |
| 137 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 103 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 138 | CONFIG_BACKLIGHT_ATMEL_LCDC=y | 104 | CONFIG_BACKLIGHT_ATMEL_LCDC=y |
| 105 | CONFIG_BACKLIGHT_ATMEL_PWM=y | ||
| 139 | # CONFIG_BACKLIGHT_GENERIC is not set | 106 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 107 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 108 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 109 | CONFIG_FONTS=y | ||
| 110 | CONFIG_LOGO=y | ||
| 140 | CONFIG_SOUND=y | 111 | CONFIG_SOUND=y |
| 141 | CONFIG_SND=y | 112 | CONFIG_SND=y |
| 142 | CONFIG_SND_SEQUENCER=y | 113 | CONFIG_SND_SEQUENCER=y |
| @@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y | |||
| 148 | # CONFIG_SND_ARM is not set | 119 | # CONFIG_SND_ARM is not set |
| 149 | CONFIG_SND_ATMEL_AC97C=y | 120 | CONFIG_SND_ATMEL_AC97C=y |
| 150 | # CONFIG_SND_SPI is not set | 121 | # CONFIG_SND_SPI is not set |
| 151 | CONFIG_SND_USB_AUDIO=m | 122 | # CONFIG_SND_USB is not set |
| 152 | # CONFIG_USB_HID is not set | 123 | # CONFIG_USB_HID is not set |
| 153 | CONFIG_USB=y | 124 | CONFIG_USB=y |
| 154 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 125 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 155 | CONFIG_USB_DEVICEFS=y | ||
| 156 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 157 | CONFIG_USB_EHCI_HCD=y | 126 | CONFIG_USB_EHCI_HCD=y |
| 158 | CONFIG_USB_OHCI_HCD=y | 127 | CONFIG_USB_OHCI_HCD=y |
| 159 | CONFIG_USB_ACM=y | 128 | CONFIG_USB_ACM=y |
| 160 | CONFIG_USB_STORAGE=y | 129 | CONFIG_USB_STORAGE=y |
| 161 | CONFIG_USB_GADGET=y | 130 | CONFIG_USB_GADGET=y |
| 162 | CONFIG_USB_ATMEL_USBA=m | 131 | CONFIG_USB_ATMEL_USBA=y |
| 163 | CONFIG_USB_ZERO=m | 132 | CONFIG_USB_G_MULTI=y |
| 164 | CONFIG_USB_AUDIO=m | ||
| 165 | CONFIG_USB_ETH=m | ||
| 166 | CONFIG_USB_ETH_EEM=y | ||
| 167 | CONFIG_USB_MASS_STORAGE=m | ||
| 168 | CONFIG_USB_G_SERIAL=m | ||
| 169 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 170 | CONFIG_USB_G_MULTI=m | ||
| 171 | CONFIG_USB_G_MULTI_CDC=y | 133 | CONFIG_USB_G_MULTI_CDC=y |
| 172 | CONFIG_MMC=y | 134 | CONFIG_MMC=y |
| 173 | # CONFIG_MMC_BLOCK_BOUNCE is not set | 135 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 174 | CONFIG_SDIO_UART=m | ||
| 175 | CONFIG_MMC_ATMELMCI=y | 136 | CONFIG_MMC_ATMELMCI=y |
| 176 | CONFIG_LEDS_ATMEL_PWM=y | 137 | CONFIG_NEW_LEDS=y |
| 138 | CONFIG_LEDS_CLASS=y | ||
| 177 | CONFIG_LEDS_GPIO=y | 139 | CONFIG_LEDS_GPIO=y |
| 140 | CONFIG_LEDS_TRIGGERS=y | ||
| 178 | CONFIG_LEDS_TRIGGER_TIMER=y | 141 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 179 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 142 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 180 | CONFIG_LEDS_TRIGGER_GPIO=y | 143 | CONFIG_LEDS_TRIGGER_GPIO=y |
| @@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y | |||
| 184 | CONFIG_AT_HDMAC=y | 147 | CONFIG_AT_HDMAC=y |
| 185 | CONFIG_DMATEST=m | 148 | CONFIG_DMATEST=m |
| 186 | # CONFIG_IOMMU_SUPPORT is not set | 149 | # CONFIG_IOMMU_SUPPORT is not set |
| 187 | CONFIG_EXT2_FS=y | 150 | CONFIG_EXT4_FS=y |
| 188 | CONFIG_FANOTIFY=y | 151 | CONFIG_FANOTIFY=y |
| 189 | CONFIG_VFAT_FS=y | 152 | CONFIG_VFAT_FS=y |
| 190 | CONFIG_TMPFS=y | 153 | CONFIG_TMPFS=y |
| 191 | CONFIG_JFFS2_FS=y | 154 | CONFIG_UBIFS_FS=y |
| 192 | CONFIG_JFFS2_SUMMARY=y | 155 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y |
| 193 | CONFIG_CRAMFS=m | ||
| 194 | CONFIG_SQUASHFS=m | ||
| 195 | CONFIG_SQUASHFS_EMBEDDED=y | ||
| 196 | CONFIG_NFS_FS=y | 156 | CONFIG_NFS_FS=y |
| 197 | CONFIG_NFS_V3=y | 157 | CONFIG_ROOT_NFS=y |
| 198 | CONFIG_NLS_CODEPAGE_437=y | 158 | CONFIG_NLS_CODEPAGE_437=y |
| 199 | CONFIG_NLS_CODEPAGE_850=y | 159 | CONFIG_NLS_CODEPAGE_850=y |
| 200 | CONFIG_NLS_ISO8859_1=y | 160 | CONFIG_NLS_ISO8859_1=y |
| @@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y | |||
| 203 | CONFIG_DEBUG_MEMORY_INIT=y | 163 | CONFIG_DEBUG_MEMORY_INIT=y |
| 204 | # CONFIG_FTRACE is not set | 164 | # CONFIG_FTRACE is not set |
| 205 | CONFIG_DEBUG_USER=y | 165 | CONFIG_DEBUG_USER=y |
| 166 | CONFIG_DEBUG_LL=y | ||
| 167 | CONFIG_EARLY_PRINTK=y | ||
| 206 | CONFIG_CRYPTO_ECB=y | 168 | CONFIG_CRYPTO_ECB=y |
| 207 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 169 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 208 | CONFIG_CRYPTO_USER_API_HASH=m | 170 | CONFIG_CRYPTO_USER_API_HASH=m |
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 4d0dc3c16063..f6e78f83c3c3 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig | |||
| @@ -26,7 +26,9 @@ CONFIG_AEABI=y | |||
| 26 | CONFIG_UACCESS_WITH_MEMCPY=y | 26 | CONFIG_UACCESS_WITH_MEMCPY=y |
| 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 28 | CONFIG_ZBOOT_ROM_BSS=0x0 | 28 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 29 | CONFIG_ARM_APPENDED_DTB=y | ||
| 29 | CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" | 30 | CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" |
| 31 | CONFIG_KEXEC=y | ||
| 30 | CONFIG_AUTO_ZRELADDR=y | 32 | CONFIG_AUTO_ZRELADDR=y |
| 31 | CONFIG_VFP=y | 33 | CONFIG_VFP=y |
| 32 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 34 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| @@ -39,6 +41,9 @@ CONFIG_UNIX=y | |||
| 39 | CONFIG_INET=y | 41 | CONFIG_INET=y |
| 40 | CONFIG_IP_MULTICAST=y | 42 | CONFIG_IP_MULTICAST=y |
| 41 | CONFIG_IP_PNP=y | 43 | CONFIG_IP_PNP=y |
| 44 | CONFIG_IP_PNP_DHCP=y | ||
| 45 | CONFIG_IP_PNP_BOOTP=y | ||
| 46 | CONFIG_IP_PNP_RARP=y | ||
| 42 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 47 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 43 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 48 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 44 | # CONFIG_INET_XFRM_MODE_BEET is not set | 49 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| @@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y | |||
| 68 | CONFIG_MTD_NAND=y | 73 | CONFIG_MTD_NAND=y |
| 69 | CONFIG_MTD_NAND_ATMEL=y | 74 | CONFIG_MTD_NAND_ATMEL=y |
| 70 | CONFIG_MTD_UBI=y | 75 | CONFIG_MTD_UBI=y |
| 76 | CONFIG_MTD_UBI_GLUEBI=y | ||
| 77 | CONFIG_PROC_DEVICETREE=y | ||
| 71 | CONFIG_BLK_DEV_LOOP=y | 78 | CONFIG_BLK_DEV_LOOP=y |
| 72 | CONFIG_BLK_DEV_RAM=y | 79 | CONFIG_BLK_DEV_RAM=y |
| 73 | CONFIG_BLK_DEV_RAM_COUNT=4 | 80 | CONFIG_BLK_DEV_RAM_COUNT=4 |
| @@ -95,7 +102,19 @@ CONFIG_MACB=y | |||
| 95 | # CONFIG_NET_VENDOR_STMICRO is not set | 102 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 96 | # CONFIG_NET_VENDOR_WIZNET is not set | 103 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 97 | CONFIG_MICREL_PHY=y | 104 | CONFIG_MICREL_PHY=y |
| 98 | # CONFIG_WLAN is not set | 105 | CONFIG_LIBERTAS_THINFIRM=m |
| 106 | CONFIG_LIBERTAS_THINFIRM_USB=m | ||
| 107 | CONFIG_RTL8187=m | ||
| 108 | CONFIG_RT2X00=m | ||
| 109 | CONFIG_RT2500USB=m | ||
| 110 | CONFIG_RT73USB=m | ||
| 111 | CONFIG_RT2800USB=m | ||
| 112 | CONFIG_RT2800USB_RT53XX=y | ||
| 113 | CONFIG_RT2800USB_RT55XX=y | ||
| 114 | CONFIG_RT2800USB_UNKNOWN=y | ||
| 115 | CONFIG_MWIFIEX=m | ||
| 116 | CONFIG_MWIFIEX_SDIO=m | ||
| 117 | CONFIG_MWIFIEX_USB=m | ||
| 99 | # CONFIG_INPUT_MOUSEDEV is not set | 118 | # CONFIG_INPUT_MOUSEDEV is not set |
| 100 | CONFIG_INPUT_EVDEV=y | 119 | CONFIG_INPUT_EVDEV=y |
| 101 | # CONFIG_KEYBOARD_ATKBD is not set | 120 | # CONFIG_KEYBOARD_ATKBD is not set |
| @@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y | |||
| 133 | CONFIG_USB_OHCI_HCD=y | 152 | CONFIG_USB_OHCI_HCD=y |
| 134 | CONFIG_USB_ACM=y | 153 | CONFIG_USB_ACM=y |
| 135 | CONFIG_USB_STORAGE=y | 154 | CONFIG_USB_STORAGE=y |
| 155 | CONFIG_USB_SERIAL=y | ||
| 156 | CONFIG_USB_SERIAL_GENERIC=y | ||
| 157 | CONFIG_USB_SERIAL_FTDI_SIO=y | ||
| 158 | CONFIG_USB_SERIAL_PL2303=y | ||
| 136 | CONFIG_USB_GADGET=y | 159 | CONFIG_USB_GADGET=y |
| 137 | CONFIG_USB_AT91=y | 160 | CONFIG_USB_ATMEL_USBA=y |
| 138 | CONFIG_USB_MASS_STORAGE=m | 161 | CONFIG_USB_G_SERIAL=y |
| 139 | CONFIG_MMC=y | 162 | CONFIG_MMC=y |
| 140 | # CONFIG_MMC_BLOCK_BOUNCE is not set | 163 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 141 | CONFIG_MMC_ATMELMCI=y | 164 | CONFIG_MMC_ATMELMCI=y |
| @@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y | |||
| 151 | # CONFIG_IOMMU_SUPPORT is not set | 174 | # CONFIG_IOMMU_SUPPORT is not set |
| 152 | CONFIG_IIO=y | 175 | CONFIG_IIO=y |
| 153 | CONFIG_AT91_ADC=y | 176 | CONFIG_AT91_ADC=y |
| 154 | CONFIG_EXT2_FS=y | 177 | CONFIG_EXT4_FS=y |
| 155 | CONFIG_FANOTIFY=y | 178 | CONFIG_FANOTIFY=y |
| 156 | CONFIG_VFAT_FS=y | 179 | CONFIG_VFAT_FS=y |
| 157 | CONFIG_TMPFS=y | 180 | CONFIG_TMPFS=y |
| 158 | CONFIG_JFFS2_FS=y | ||
| 159 | CONFIG_JFFS2_SUMMARY=y | ||
| 160 | CONFIG_UBIFS_FS=y | 181 | CONFIG_UBIFS_FS=y |
| 182 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y | ||
| 161 | CONFIG_NFS_FS=y | 183 | CONFIG_NFS_FS=y |
| 162 | CONFIG_ROOT_NFS=y | 184 | CONFIG_ROOT_NFS=y |
| 163 | CONFIG_NLS_CODEPAGE_437=y | 185 | CONFIG_NLS_CODEPAGE_437=y |
| 164 | CONFIG_NLS_CODEPAGE_850=y | 186 | CONFIG_NLS_CODEPAGE_850=y |
| 165 | CONFIG_NLS_ISO8859_1=y | 187 | CONFIG_NLS_ISO8859_1=y |
| 188 | CONFIG_NLS_UTF8=y | ||
| 166 | CONFIG_STRIP_ASM_SYMS=y | 189 | CONFIG_STRIP_ASM_SYMS=y |
| 167 | CONFIG_DEBUG_FS=y | 190 | CONFIG_DEBUG_FS=y |
| 168 | # CONFIG_SCHED_DEBUG is not set | 191 | # CONFIG_SCHED_DEBUG is not set |
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 6c24985515a2..3a78bdcd0a43 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt | |||
| @@ -14,15 +14,11 @@ config ARCH_AT91RM9200 | |||
| 14 | select SOC_AT91RM9200 | 14 | select SOC_AT91RM9200 |
| 15 | 15 | ||
| 16 | config ARCH_AT91SAM9260 | 16 | config ARCH_AT91SAM9260 |
| 17 | bool "AT91SAM9260 or AT91SAM9XE" | 17 | bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" |
| 18 | select SOC_AT91SAM9260 | 18 | select SOC_AT91SAM9260 |
| 19 | 19 | ||
| 20 | config ARCH_AT91SAM9261 | 20 | config ARCH_AT91SAM9261 |
| 21 | bool "AT91SAM9261" | 21 | bool "AT91SAM9261 or AT91SAM9G10" |
| 22 | select SOC_AT91SAM9261 | ||
| 23 | |||
| 24 | config ARCH_AT91SAM9G10 | ||
| 25 | bool "AT91SAM9G10" | ||
| 26 | select SOC_AT91SAM9261 | 22 | select SOC_AT91SAM9261 |
| 27 | 23 | ||
| 28 | config ARCH_AT91SAM9263 | 24 | config ARCH_AT91SAM9263 |
| @@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL | |||
| 33 | bool "AT91SAM9RL" | 29 | bool "AT91SAM9RL" |
| 34 | select SOC_AT91SAM9RL | 30 | select SOC_AT91SAM9RL |
| 35 | 31 | ||
| 36 | config ARCH_AT91SAM9G20 | ||
| 37 | bool "AT91SAM9G20" | ||
| 38 | select SOC_AT91SAM9260 | ||
| 39 | |||
| 40 | config ARCH_AT91SAM9G45 | 32 | config ARCH_AT91SAM9G45 |
| 41 | bool "AT91SAM9G45" | 33 | bool "AT91SAM9G45" |
| 42 | select SOC_AT91SAM9G45 | 34 | select SOC_AT91SAM9G45 |
| @@ -50,6 +42,14 @@ config ARCH_AT91X40 | |||
| 50 | 42 | ||
| 51 | endchoice | 43 | endchoice |
| 52 | 44 | ||
| 45 | config ARCH_AT91SAM9G20 | ||
| 46 | bool | ||
| 47 | select ARCH_AT91SAM9260 | ||
| 48 | |||
| 49 | config ARCH_AT91SAM9G10 | ||
| 50 | bool | ||
| 51 | select ARCH_AT91SAM9261 | ||
| 52 | |||
| 53 | # ---------------------------------------------------------- | 53 | # ---------------------------------------------------------- |
| 54 | 54 | ||
| 55 | if ARCH_AT91RM9200 | 55 | if ARCH_AT91RM9200 |
| @@ -62,13 +62,6 @@ config MACH_ONEARM | |||
| 62 | Select this if you are using Ajeco's 1ARM Single Board Computer. | 62 | Select this if you are using Ajeco's 1ARM Single Board Computer. |
| 63 | <http://www.ajeco.fi/> | 63 | <http://www.ajeco.fi/> |
| 64 | 64 | ||
| 65 | config ARCH_AT91RM9200DK | ||
| 66 | bool "Atmel AT91RM9200-DK Development board" | ||
| 67 | select HAVE_AT91_DATAFLASH_CARD | ||
| 68 | help | ||
| 69 | Select this if you are using Atmel's AT91RM9200-DK Development board. | ||
| 70 | (Discontinued) | ||
| 71 | |||
| 72 | config MACH_AT91RM9200EK | 65 | config MACH_AT91RM9200EK |
| 73 | bool "Atmel AT91RM9200-EK Evaluation Kit" | 66 | bool "Atmel AT91RM9200-EK Evaluation Kit" |
| 74 | select HAVE_AT91_DATAFLASH_CARD | 67 | select HAVE_AT91_DATAFLASH_CARD |
| @@ -207,76 +200,6 @@ config MACH_FLEXIBITY | |||
| 207 | Select this if you are using Flexibity Connect board | 200 | Select this if you are using Flexibity Connect board |
| 208 | <http://www.flexibity.com> | 201 | <http://www.flexibity.com> |
| 209 | 202 | ||
| 210 | endif | ||
| 211 | |||
| 212 | # ---------------------------------------------------------- | ||
| 213 | |||
| 214 | if ARCH_AT91SAM9261 | ||
| 215 | |||
| 216 | comment "AT91SAM9261 Board Type" | ||
| 217 | |||
| 218 | config MACH_AT91SAM9261EK | ||
| 219 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | ||
| 220 | select HAVE_AT91_DATAFLASH_CARD | ||
| 221 | help | ||
| 222 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | ||
| 223 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | ||
| 224 | |||
| 225 | endif | ||
| 226 | |||
| 227 | # ---------------------------------------------------------- | ||
| 228 | |||
| 229 | if ARCH_AT91SAM9G10 | ||
| 230 | |||
| 231 | comment "AT91SAM9G10 Board Type" | ||
| 232 | |||
| 233 | config MACH_AT91SAM9G10EK | ||
| 234 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
| 235 | select HAVE_AT91_DATAFLASH_CARD | ||
| 236 | help | ||
| 237 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
| 238 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
| 239 | |||
| 240 | endif | ||
| 241 | |||
| 242 | # ---------------------------------------------------------- | ||
| 243 | |||
| 244 | if ARCH_AT91SAM9263 | ||
| 245 | |||
| 246 | comment "AT91SAM9263 Board Type" | ||
| 247 | |||
| 248 | config MACH_AT91SAM9263EK | ||
| 249 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | ||
| 250 | select HAVE_AT91_DATAFLASH_CARD | ||
| 251 | help | ||
| 252 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | ||
| 253 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | ||
| 254 | |||
| 255 | config MACH_USB_A9263 | ||
| 256 | bool "CALAO USB-A9263" | ||
| 257 | help | ||
| 258 | Select this if you are using a Calao Systems USB-A9263. | ||
| 259 | <http://www.calao-systems.com> | ||
| 260 | |||
| 261 | endif | ||
| 262 | |||
| 263 | # ---------------------------------------------------------- | ||
| 264 | |||
| 265 | if ARCH_AT91SAM9RL | ||
| 266 | |||
| 267 | comment "AT91SAM9RL Board Type" | ||
| 268 | |||
| 269 | config MACH_AT91SAM9RLEK | ||
| 270 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | ||
| 271 | help | ||
| 272 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | ||
| 273 | |||
| 274 | endif | ||
| 275 | |||
| 276 | # ---------------------------------------------------------- | ||
| 277 | |||
| 278 | if ARCH_AT91SAM9G20 | ||
| 279 | |||
| 280 | comment "AT91SAM9G20 Board Type" | 203 | comment "AT91SAM9G20 Board Type" |
| 281 | 204 | ||
| 282 | config MACH_AT91SAM9G20EK | 205 | config MACH_AT91SAM9G20EK |
| @@ -341,17 +264,70 @@ config MACH_USB_A9G20 | |||
| 341 | Select this if you are using a Calao Systems USB-A9G20. | 264 | Select this if you are using a Calao Systems USB-A9G20. |
| 342 | <http://www.calao-systems.com> | 265 | <http://www.calao-systems.com> |
| 343 | 266 | ||
| 267 | config MACH_SNAPPER_9260 | ||
| 268 | bool "Bluewater Systems Snapper 9260/9G20 module" | ||
| 269 | help | ||
| 270 | Select this if you are using the Bluewater Systems Snapper 9260 or | ||
| 271 | Snapper 9G20 modules. | ||
| 272 | <http://www.bluewatersys.com/> | ||
| 344 | endif | 273 | endif |
| 345 | 274 | ||
| 346 | if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) | 275 | # ---------------------------------------------------------- |
| 347 | comment "AT91SAM9260/AT91SAM9G20 boards" | 276 | |
| 277 | if ARCH_AT91SAM9261 | ||
| 278 | |||
| 279 | comment "AT91SAM9261 Board Type" | ||
| 280 | |||
| 281 | config MACH_AT91SAM9261EK | ||
| 282 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | ||
| 283 | select HAVE_AT91_DATAFLASH_CARD | ||
| 284 | help | ||
| 285 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | ||
| 286 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | ||
| 287 | |||
| 288 | comment "AT91SAM9G10 Board Type" | ||
| 289 | |||
| 290 | config MACH_AT91SAM9G10EK | ||
| 291 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
| 292 | select HAVE_AT91_DATAFLASH_CARD | ||
| 293 | help | ||
| 294 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
| 295 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
| 296 | |||
| 297 | endif | ||
| 298 | |||
| 299 | # ---------------------------------------------------------- | ||
| 300 | |||
| 301 | if ARCH_AT91SAM9263 | ||
| 302 | |||
| 303 | comment "AT91SAM9263 Board Type" | ||
| 304 | |||
| 305 | config MACH_AT91SAM9263EK | ||
| 306 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | ||
| 307 | select HAVE_AT91_DATAFLASH_CARD | ||
| 308 | help | ||
| 309 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | ||
| 310 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | ||
| 311 | |||
| 312 | config MACH_USB_A9263 | ||
| 313 | bool "CALAO USB-A9263" | ||
| 314 | help | ||
| 315 | Select this if you are using a Calao Systems USB-A9263. | ||
| 316 | <http://www.calao-systems.com> | ||
| 317 | |||
| 318 | endif | ||
| 319 | |||
| 320 | # ---------------------------------------------------------- | ||
| 321 | |||
| 322 | if ARCH_AT91SAM9RL | ||
| 323 | |||
| 324 | comment "AT91SAM9RL Board Type" | ||
| 325 | |||
| 326 | config MACH_AT91SAM9RLEK | ||
| 327 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | ||
| 328 | help | ||
| 329 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | ||
| 348 | 330 | ||
| 349 | config MACH_SNAPPER_9260 | ||
| 350 | bool "Bluewater Systems Snapper 9260/9G20 module" | ||
| 351 | help | ||
| 352 | Select this if you are using the Bluewater Systems Snapper 9260 or | ||
| 353 | Snapper 9G20 modules. | ||
| 354 | <http://www.bluewatersys.com/> | ||
| 355 | endif | 331 | endif |
| 356 | 332 | ||
| 357 | # ---------------------------------------------------------- | 333 | # ---------------------------------------------------------- |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 788562dccb43..07e89b4db7e7 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -27,16 +27,13 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o | |||
| 27 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o | 27 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o |
| 28 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o | 28 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o |
| 29 | obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o | 29 | obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o |
| 30 | obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261_devices.o | ||
| 31 | obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o | 30 | obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o |
| 32 | obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o | 31 | obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o |
| 33 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o | ||
| 34 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o | 32 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o |
| 35 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o | 33 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o |
| 36 | 34 | ||
| 37 | # AT91RM9200 board-specific support | 35 | # AT91RM9200 board-specific support |
| 38 | obj-$(CONFIG_MACH_ONEARM) += board-1arm.o | 36 | obj-$(CONFIG_MACH_ONEARM) += board-1arm.o |
| 39 | obj-$(CONFIG_ARCH_AT91RM9200DK) += board-rm9200dk.o | ||
| 40 | obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o | 37 | obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o |
| 41 | obj-$(CONFIG_MACH_CSB337) += board-csb337.o | 38 | obj-$(CONFIG_MACH_CSB337) += board-csb337.o |
| 42 | obj-$(CONFIG_MACH_CSB637) += board-csb637.o | 39 | obj-$(CONFIG_MACH_CSB637) += board-csb637.o |
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c deleted file mode 100644 index 690541b18cbc..000000000000 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ /dev/null | |||
| @@ -1,228 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91/board-rm9200dk.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 SAN People | ||
| 5 | * | ||
| 6 | * Epson S1D framebuffer glue code is: | ||
| 7 | * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/types.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/mm.h> | ||
| 28 | #include <linux/module.h> | ||
| 29 | #include <linux/platform_device.h> | ||
| 30 | #include <linux/spi/spi.h> | ||
| 31 | #include <linux/mtd/physmap.h> | ||
| 32 | |||
| 33 | #include <asm/setup.h> | ||
| 34 | #include <asm/mach-types.h> | ||
| 35 | #include <asm/irq.h> | ||
| 36 | |||
| 37 | #include <asm/mach/arch.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/irq.h> | ||
| 40 | |||
| 41 | #include <mach/hardware.h> | ||
| 42 | #include <mach/at91rm9200_mc.h> | ||
| 43 | #include <mach/at91_ramc.h> | ||
| 44 | |||
| 45 | #include "at91_aic.h" | ||
| 46 | #include "board.h" | ||
| 47 | #include "generic.h" | ||
| 48 | |||
| 49 | |||
| 50 | static void __init dk_init_early(void) | ||
| 51 | { | ||
| 52 | /* Initialize processor: 18.432 MHz crystal */ | ||
| 53 | at91_initialize(18432000); | ||
| 54 | } | ||
| 55 | |||
| 56 | static struct macb_platform_data __initdata dk_eth_data = { | ||
| 57 | .phy_irq_pin = AT91_PIN_PC4, | ||
| 58 | .is_rmii = 1, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct at91_usbh_data __initdata dk_usbh_data = { | ||
| 62 | .ports = 2, | ||
| 63 | .vbus_pin = {-EINVAL, -EINVAL}, | ||
| 64 | .overcurrent_pin= {-EINVAL, -EINVAL}, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct at91_udc_data __initdata dk_udc_data = { | ||
| 68 | .vbus_pin = AT91_PIN_PD4, | ||
| 69 | .pullup_pin = AT91_PIN_PD5, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct at91_cf_data __initdata dk_cf_data = { | ||
| 73 | .irq_pin = -EINVAL, | ||
| 74 | .det_pin = AT91_PIN_PB0, | ||
| 75 | .vcc_pin = -EINVAL, | ||
| 76 | .rst_pin = AT91_PIN_PC5, | ||
| 77 | }; | ||
| 78 | |||
| 79 | #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD | ||
| 80 | static struct mci_platform_data __initdata dk_mci0_data = { | ||
| 81 | .slot[0] = { | ||
| 82 | .bus_width = 4, | ||
| 83 | .detect_pin = -EINVAL, | ||
| 84 | .wp_pin = -EINVAL, | ||
| 85 | }, | ||
| 86 | }; | ||
| 87 | #endif | ||
| 88 | |||
| 89 | static struct spi_board_info dk_spi_devices[] = { | ||
| 90 | { /* DataFlash chip */ | ||
| 91 | .modalias = "mtd_dataflash", | ||
| 92 | .chip_select = 0, | ||
| 93 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 94 | }, | ||
| 95 | { /* UR6HCPS2-SP40 PS2-to-SPI adapter */ | ||
| 96 | .modalias = "ur6hcps2", | ||
| 97 | .chip_select = 1, | ||
| 98 | .max_speed_hz = 250 * 1000, | ||
| 99 | }, | ||
| 100 | { /* TLV1504 ADC, 4 channels, 10 bits; one is a temp sensor */ | ||
| 101 | .modalias = "tlv1504", | ||
| 102 | .chip_select = 2, | ||
| 103 | .max_speed_hz = 20 * 1000 * 1000, | ||
| 104 | }, | ||
| 105 | #ifdef CONFIG_MTD_AT91_DATAFLASH_CARD | ||
| 106 | { /* DataFlash card */ | ||
| 107 | .modalias = "mtd_dataflash", | ||
| 108 | .chip_select = 3, | ||
| 109 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 110 | } | ||
| 111 | #endif | ||
| 112 | }; | ||
| 113 | |||
| 114 | static struct i2c_board_info __initdata dk_i2c_devices[] = { | ||
| 115 | { | ||
| 116 | I2C_BOARD_INFO("ics1523", 0x26), | ||
| 117 | }, | ||
| 118 | { | ||
| 119 | I2C_BOARD_INFO("x9429", 0x28), | ||
| 120 | }, | ||
| 121 | { | ||
| 122 | I2C_BOARD_INFO("24c1024", 0x50), | ||
| 123 | } | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct mtd_partition __initdata dk_nand_partition[] = { | ||
| 127 | { | ||
| 128 | .name = "NAND Partition 1", | ||
| 129 | .offset = 0, | ||
| 130 | .size = MTDPART_SIZ_FULL, | ||
| 131 | }, | ||
| 132 | }; | ||
| 133 | |||
| 134 | static struct atmel_nand_data __initdata dk_nand_data = { | ||
| 135 | .ale = 22, | ||
| 136 | .cle = 21, | ||
| 137 | .det_pin = AT91_PIN_PB1, | ||
| 138 | .rdy_pin = AT91_PIN_PC2, | ||
| 139 | .enable_pin = -EINVAL, | ||
| 140 | .ecc_mode = NAND_ECC_SOFT, | ||
| 141 | .on_flash_bbt = 1, | ||
| 142 | .parts = dk_nand_partition, | ||
| 143 | .num_parts = ARRAY_SIZE(dk_nand_partition), | ||
| 144 | }; | ||
| 145 | |||
| 146 | #define DK_FLASH_BASE AT91_CHIPSELECT_0 | ||
| 147 | #define DK_FLASH_SIZE SZ_2M | ||
| 148 | |||
| 149 | static struct physmap_flash_data dk_flash_data = { | ||
| 150 | .width = 2, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct resource dk_flash_resource = { | ||
| 154 | .start = DK_FLASH_BASE, | ||
| 155 | .end = DK_FLASH_BASE + DK_FLASH_SIZE - 1, | ||
| 156 | .flags = IORESOURCE_MEM, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static struct platform_device dk_flash = { | ||
| 160 | .name = "physmap-flash", | ||
| 161 | .id = 0, | ||
| 162 | .dev = { | ||
| 163 | .platform_data = &dk_flash_data, | ||
| 164 | }, | ||
| 165 | .resource = &dk_flash_resource, | ||
| 166 | .num_resources = 1, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct gpio_led dk_leds[] = { | ||
| 170 | { | ||
| 171 | .name = "led0", | ||
| 172 | .gpio = AT91_PIN_PB2, | ||
| 173 | .active_low = 1, | ||
| 174 | .default_trigger = "heartbeat", | ||
| 175 | } | ||
| 176 | }; | ||
| 177 | |||
| 178 | static void __init dk_board_init(void) | ||
| 179 | { | ||
| 180 | /* Serial */ | ||
| 181 | /* DBGU on ttyS0. (Rx & Tx only) */ | ||
| 182 | at91_register_uart(0, 0, 0); | ||
| 183 | |||
| 184 | /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ | ||
| 185 | at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS | ||
| 186 | | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | ||
| 187 | | ATMEL_UART_RI); | ||
| 188 | at91_add_device_serial(); | ||
| 189 | /* Ethernet */ | ||
| 190 | at91_add_device_eth(&dk_eth_data); | ||
| 191 | /* USB Host */ | ||
| 192 | at91_add_device_usbh(&dk_usbh_data); | ||
| 193 | /* USB Device */ | ||
| 194 | at91_add_device_udc(&dk_udc_data); | ||
| 195 | at91_set_multi_drive(dk_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ | ||
| 196 | /* Compact Flash */ | ||
| 197 | at91_add_device_cf(&dk_cf_data); | ||
| 198 | /* I2C */ | ||
| 199 | at91_add_device_i2c(dk_i2c_devices, ARRAY_SIZE(dk_i2c_devices)); | ||
| 200 | /* SPI */ | ||
| 201 | at91_add_device_spi(dk_spi_devices, ARRAY_SIZE(dk_spi_devices)); | ||
| 202 | #ifdef CONFIG_MTD_AT91_DATAFLASH_CARD | ||
| 203 | /* DataFlash card */ | ||
| 204 | at91_set_gpio_output(AT91_PIN_PB7, 0); | ||
| 205 | #else | ||
| 206 | /* MMC */ | ||
| 207 | at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ | ||
| 208 | at91_add_device_mci(0, &dk_mci0_data); | ||
| 209 | #endif | ||
| 210 | /* NAND */ | ||
| 211 | at91_add_device_nand(&dk_nand_data); | ||
| 212 | /* NOR Flash */ | ||
| 213 | platform_device_register(&dk_flash); | ||
| 214 | /* LEDs */ | ||
| 215 | at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds)); | ||
| 216 | /* VGA */ | ||
| 217 | // dk_add_device_video(); | ||
| 218 | } | ||
| 219 | |||
| 220 | MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") | ||
| 221 | /* Maintainer: SAN People/Atmel */ | ||
| 222 | .init_time = at91rm9200_timer_init, | ||
| 223 | .map_io = at91_map_io, | ||
| 224 | .handle_irq = at91_aic_handle_irq, | ||
| 225 | .init_early = dk_init_early, | ||
| 226 | .init_irq = at91_init_irq_default, | ||
| 227 | .init_machine = dk_board_init, | ||
| 228 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index b446645c7727..d3437624ca4e 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
| @@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {} | |||
| 264 | */ | 264 | */ |
| 265 | static struct at73c213_board_info at73c213_data = { | 265 | static struct at73c213_board_info at73c213_data = { |
| 266 | .ssc_id = 1, | 266 | .ssc_id = 1, |
| 267 | #if defined(CONFIG_MACH_AT91SAM9261EK) | 267 | .shortname = "AT91SAM9261/9G10-EK external DAC", |
| 268 | .shortname = "AT91SAM9261-EK external DAC", | ||
| 269 | #else | ||
| 270 | .shortname = "AT91SAM9G10-EK external DAC", | ||
| 271 | #endif | ||
| 272 | }; | 268 | }; |
| 273 | 269 | ||
| 274 | #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) | 270 | #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) |
| @@ -412,9 +408,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
| 412 | .default_monspecs = &at91fb_default_stn_monspecs, | 408 | .default_monspecs = &at91fb_default_stn_monspecs, |
| 413 | .atmel_lcdfb_power_control = at91_lcdc_stn_power_control, | 409 | .atmel_lcdfb_power_control = at91_lcdc_stn_power_control, |
| 414 | .guard_time = 1, | 410 | .guard_time = 1, |
| 415 | #if defined(CONFIG_MACH_AT91SAM9G10EK) | ||
| 416 | .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, | ||
| 417 | #endif | ||
| 418 | }; | 411 | }; |
| 419 | 412 | ||
| 420 | #else | 413 | #else |
| @@ -468,9 +461,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
| 468 | .default_monspecs = &at91fb_default_tft_monspecs, | 461 | .default_monspecs = &at91fb_default_tft_monspecs, |
| 469 | .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, | 462 | .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, |
| 470 | .guard_time = 1, | 463 | .guard_time = 1, |
| 471 | #if defined(CONFIG_MACH_AT91SAM9G10EK) | ||
| 472 | .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, | ||
| 473 | #endif | ||
| 474 | }; | 464 | }; |
| 475 | #endif | 465 | #endif |
| 476 | 466 | ||
| @@ -574,6 +564,10 @@ static void __init ek_board_init(void) | |||
| 574 | /* DBGU on ttyS0. (Rx & Tx only) */ | 564 | /* DBGU on ttyS0. (Rx & Tx only) */ |
| 575 | at91_register_uart(0, 0, 0); | 565 | at91_register_uart(0, 0, 0); |
| 576 | at91_add_device_serial(); | 566 | at91_add_device_serial(); |
| 567 | |||
| 568 | if (cpu_is_at91sam9g10()) | ||
| 569 | ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; | ||
| 570 | |||
| 577 | /* USB Host */ | 571 | /* USB Host */ |
| 578 | at91_add_device_usbh(&ek_usbh_data); | 572 | at91_add_device_usbh(&ek_usbh_data); |
| 579 | /* USB Device */ | 573 | /* USB Device */ |
| @@ -606,11 +600,17 @@ static void __init ek_board_init(void) | |||
| 606 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | 600 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); |
| 607 | } | 601 | } |
| 608 | 602 | ||
| 609 | #if defined(CONFIG_MACH_AT91SAM9261EK) | ||
| 610 | MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") | 603 | MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") |
| 611 | #else | 604 | /* Maintainer: Atmel */ |
| 605 | .init_time = at91sam926x_pit_init, | ||
| 606 | .map_io = at91_map_io, | ||
| 607 | .handle_irq = at91_aic_handle_irq, | ||
| 608 | .init_early = ek_init_early, | ||
| 609 | .init_irq = at91_init_irq_default, | ||
| 610 | .init_machine = ek_board_init, | ||
| 611 | MACHINE_END | ||
| 612 | |||
| 612 | MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") | 613 | MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") |
| 613 | #endif | ||
| 614 | /* Maintainer: Atmel */ | 614 | /* Maintainer: Atmel */ |
| 615 | .init_time = at91sam926x_pit_init, | 615 | .init_time = at91sam926x_pit_init, |
| 616 | .map_io = at91_map_io, | 616 | .map_io = at91_map_io, |
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index e7df2dd43a40..dc5d6becd8c7 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c | |||
| @@ -176,7 +176,6 @@ static const char *highbank_match[] __initconst = { | |||
| 176 | 176 | ||
| 177 | DT_MACHINE_START(HIGHBANK, "Highbank") | 177 | DT_MACHINE_START(HIGHBANK, "Highbank") |
| 178 | .smp = smp_ops(highbank_smp_ops), | 178 | .smp = smp_ops(highbank_smp_ops), |
| 179 | .map_io = debug_ll_io_init, | ||
| 180 | .init_irq = highbank_init_irq, | 179 | .init_irq = highbank_init_irq, |
| 181 | .init_time = highbank_timer_init, | 180 | .init_time = highbank_timer_init, |
| 182 | .init_machine = highbank_init, | 181 | .init_machine = highbank_init, |
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index fceb093b9494..614e41e7881b 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig | |||
| @@ -48,9 +48,7 @@ config ARCH_MSM8X60 | |||
| 48 | select CPU_V7 | 48 | select CPU_V7 |
| 49 | select GPIO_MSM_V2 | 49 | select GPIO_MSM_V2 |
| 50 | select HAVE_SMP | 50 | select HAVE_SMP |
| 51 | select MSM_GPIOMUX | ||
| 52 | select MSM_SCM if SMP | 51 | select MSM_SCM if SMP |
| 53 | select MSM_V2_TLMM | ||
| 54 | select USE_OF | 52 | select USE_OF |
| 55 | 53 | ||
| 56 | config ARCH_MSM8960 | 54 | config ARCH_MSM8960 |
| @@ -58,9 +56,8 @@ config ARCH_MSM8960 | |||
| 58 | select ARM_GIC | 56 | select ARM_GIC |
| 59 | select CPU_V7 | 57 | select CPU_V7 |
| 60 | select HAVE_SMP | 58 | select HAVE_SMP |
| 61 | select MSM_GPIOMUX | 59 | select GPIO_MSM_V2 |
| 62 | select MSM_SCM if SMP | 60 | select MSM_SCM if SMP |
| 63 | select MSM_V2_TLMM | ||
| 64 | select USE_OF | 61 | select USE_OF |
| 65 | 62 | ||
| 66 | config MSM_HAS_DEBUG_UART_HS | 63 | config MSM_HAS_DEBUG_UART_HS |
| @@ -124,10 +121,10 @@ config MSM_SMD | |||
| 124 | bool | 121 | bool |
| 125 | 122 | ||
| 126 | config MSM_GPIOMUX | 123 | config MSM_GPIOMUX |
| 127 | bool | 124 | depends on !(ARCH_MSM8X60 || ARCH_MSM8960) |
| 128 | 125 | bool "MSM V1 TLMM GPIOMUX architecture" | |
| 129 | config MSM_V2_TLMM | 126 | help |
| 130 | bool | 127 | Support for MSM V1 TLMM GPIOMUX architecture. |
| 131 | 128 | ||
| 132 | config MSM_SCM | 129 | config MSM_SCM |
| 133 | bool | 130 | bool |
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 17519faf082f..1a26d04c9400 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile | |||
| @@ -27,7 +27,5 @@ obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o | |||
| 27 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o | 27 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o |
| 28 | obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o | 28 | obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o |
| 29 | obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o | 29 | obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o |
| 30 | 30 | obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o | |
| 31 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o | 31 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o |
| 32 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o | ||
| 33 | obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o | ||
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c index 7dcfc5300bbd..492f5cd87b0a 100644 --- a/arch/arm/mach-msm/board-dt-8660.c +++ b/arch/arm/mach-msm/board-dt-8660.c | |||
| @@ -11,7 +11,6 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/irqchip.h> | ||
| 15 | #include <linux/of.h> | 14 | #include <linux/of.h> |
| 16 | #include <linux/of_platform.h> | 15 | #include <linux/of_platform.h> |
| 17 | 16 | ||
| @@ -44,7 +43,6 @@ static const char *msm8x60_fluid_match[] __initdata = { | |||
| 44 | DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") | 43 | DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") |
| 45 | .smp = smp_ops(msm_smp_ops), | 44 | .smp = smp_ops(msm_smp_ops), |
| 46 | .map_io = msm_map_msm8x60_io, | 45 | .map_io = msm_map_msm8x60_io, |
| 47 | .init_irq = irqchip_init, | ||
| 48 | .init_machine = msm8x60_dt_init, | 46 | .init_machine = msm8x60_dt_init, |
| 49 | .init_late = msm8x60_init_late, | 47 | .init_late = msm8x60_init_late, |
| 50 | .init_time = msm_dt_timer_init, | 48 | .init_time = msm_dt_timer_init, |
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c index 73019363ffa4..bb5530957c4f 100644 --- a/arch/arm/mach-msm/board-dt-8960.c +++ b/arch/arm/mach-msm/board-dt-8960.c | |||
| @@ -11,7 +11,6 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/irqchip.h> | ||
| 15 | #include <linux/of_platform.h> | 14 | #include <linux/of_platform.h> |
| 16 | 15 | ||
| 17 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| @@ -31,7 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = { | |||
| 31 | DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") | 30 | DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") |
| 32 | .smp = smp_ops(msm_smp_ops), | 31 | .smp = smp_ops(msm_smp_ops), |
| 33 | .map_io = msm_map_msm8960_io, | 32 | .map_io = msm_map_msm8960_io, |
| 34 | .init_irq = irqchip_init, | ||
| 35 | .init_time = msm_dt_timer_init, | 33 | .init_time = msm_dt_timer_init, |
| 36 | .init_machine = msm_dt_init, | 34 | .init_machine = msm_dt_init, |
| 37 | .dt_compat = msm8960_dt_match, | 35 | .dt_compat = msm8960_dt_match, |
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c index 4886404d42f5..b0fbdf1cbdd1 100644 --- a/arch/arm/mach-msm/clock-debug.c +++ b/arch/arm/mach-msm/clock-debug.c | |||
| @@ -104,7 +104,7 @@ int __init clock_debug_add(struct clk *clock) | |||
| 104 | if (!debugfs_base) | 104 | if (!debugfs_base) |
| 105 | return -ENOMEM; | 105 | return -ENOMEM; |
| 106 | 106 | ||
| 107 | strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); | 107 | strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp)); |
| 108 | for (ptr = temp; *ptr; ptr++) | 108 | for (ptr = temp; *ptr; ptr++) |
| 109 | *ptr = tolower(*ptr); | 109 | *ptr = tolower(*ptr); |
| 110 | 110 | ||
diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h deleted file mode 100644 index a9bab53dddf4..000000000000 --- a/arch/arm/mach-msm/core.h +++ /dev/null | |||
| @@ -1,2 +0,0 @@ | |||
| 1 | extern struct smp_operations msm_smp_ops; | ||
| 2 | extern void msm_cpu_die(unsigned int cpu); | ||
diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c deleted file mode 100644 index 7b380b31bd0e..000000000000 --- a/arch/arm/mach-msm/gpiomux-8x60.c +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | */ | ||
| 17 | #include "gpiomux.h" | ||
| 18 | |||
| 19 | struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; | ||
diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c deleted file mode 100644 index 273396d2b127..000000000000 --- a/arch/arm/mach-msm/gpiomux-v2.c +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | */ | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <mach/msm_iomap.h> | ||
| 19 | #include "gpiomux.h" | ||
| 20 | |||
| 21 | void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val) | ||
| 22 | { | ||
| 23 | writel(val & ~GPIOMUX_CTL_MASK, | ||
| 24 | MSM_TLMM_BASE + 0x1000 + (0x10 * gpio)); | ||
| 25 | } | ||
diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h deleted file mode 100644 index 3bf10e7f0381..000000000000 --- a/arch/arm/mach-msm/gpiomux-v2.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | */ | ||
| 17 | #ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H | ||
| 18 | #define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H | ||
| 19 | |||
| 20 | #define GPIOMUX_NGPIOS 173 | ||
| 21 | |||
| 22 | typedef u16 gpiomux_config_t; | ||
| 23 | |||
| 24 | enum { | ||
| 25 | GPIOMUX_DRV_2MA = 0UL << 6, | ||
| 26 | GPIOMUX_DRV_4MA = 1UL << 6, | ||
| 27 | GPIOMUX_DRV_6MA = 2UL << 6, | ||
| 28 | GPIOMUX_DRV_8MA = 3UL << 6, | ||
| 29 | GPIOMUX_DRV_10MA = 4UL << 6, | ||
| 30 | GPIOMUX_DRV_12MA = 5UL << 6, | ||
| 31 | GPIOMUX_DRV_14MA = 6UL << 6, | ||
| 32 | GPIOMUX_DRV_16MA = 7UL << 6, | ||
| 33 | }; | ||
| 34 | |||
| 35 | enum { | ||
| 36 | GPIOMUX_FUNC_GPIO = 0UL << 2, | ||
| 37 | GPIOMUX_FUNC_1 = 1UL << 2, | ||
| 38 | GPIOMUX_FUNC_2 = 2UL << 2, | ||
| 39 | GPIOMUX_FUNC_3 = 3UL << 2, | ||
| 40 | GPIOMUX_FUNC_4 = 4UL << 2, | ||
| 41 | GPIOMUX_FUNC_5 = 5UL << 2, | ||
| 42 | GPIOMUX_FUNC_6 = 6UL << 2, | ||
| 43 | GPIOMUX_FUNC_7 = 7UL << 2, | ||
| 44 | GPIOMUX_FUNC_8 = 8UL << 2, | ||
| 45 | GPIOMUX_FUNC_9 = 9UL << 2, | ||
| 46 | GPIOMUX_FUNC_A = 10UL << 2, | ||
| 47 | GPIOMUX_FUNC_B = 11UL << 2, | ||
| 48 | GPIOMUX_FUNC_C = 12UL << 2, | ||
| 49 | GPIOMUX_FUNC_D = 13UL << 2, | ||
| 50 | GPIOMUX_FUNC_E = 14UL << 2, | ||
| 51 | GPIOMUX_FUNC_F = 15UL << 2, | ||
| 52 | }; | ||
| 53 | |||
| 54 | enum { | ||
| 55 | GPIOMUX_PULL_NONE = 0UL, | ||
| 56 | GPIOMUX_PULL_DOWN = 1UL, | ||
| 57 | GPIOMUX_PULL_KEEPER = 2UL, | ||
| 58 | GPIOMUX_PULL_UP = 3UL, | ||
| 59 | }; | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c index 53af21abd155..2b8e2d217082 100644 --- a/arch/arm/mach-msm/gpiomux.c +++ b/arch/arm/mach-msm/gpiomux.c | |||
| @@ -17,9 +17,24 @@ | |||
| 17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 18 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
| 19 | #include "gpiomux.h" | 19 | #include "gpiomux.h" |
| 20 | #include "proc_comm.h" | ||
| 20 | 21 | ||
| 21 | static DEFINE_SPINLOCK(gpiomux_lock); | 22 | static DEFINE_SPINLOCK(gpiomux_lock); |
| 22 | 23 | ||
| 24 | static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val) | ||
| 25 | { | ||
| 26 | unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) | | ||
| 27 | ((gpio & 0x3ff) << 4); | ||
| 28 | unsigned tlmm_disable = 0; | ||
| 29 | int rc; | ||
| 30 | |||
| 31 | rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, | ||
| 32 | &tlmm_config, &tlmm_disable); | ||
| 33 | if (rc) | ||
| 34 | pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n", | ||
| 35 | __func__, rc, tlmm_config, tlmm_disable); | ||
| 36 | } | ||
| 37 | |||
| 23 | int msm_gpiomux_write(unsigned gpio, | 38 | int msm_gpiomux_write(unsigned gpio, |
| 24 | gpiomux_config_t active, | 39 | gpiomux_config_t active, |
| 25 | gpiomux_config_t suspended) | 40 | gpiomux_config_t suspended) |
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h index 00459f6ee13c..8e82f41a8923 100644 --- a/arch/arm/mach-msm/gpiomux.h +++ b/arch/arm/mach-msm/gpiomux.h | |||
| @@ -20,12 +20,7 @@ | |||
| 20 | #include <linux/bitops.h> | 20 | #include <linux/bitops.h> |
| 21 | #include <linux/errno.h> | 21 | #include <linux/errno.h> |
| 22 | #include <mach/msm_gpiomux.h> | 22 | #include <mach/msm_gpiomux.h> |
| 23 | |||
| 24 | #if defined(CONFIG_MSM_V2_TLMM) | ||
| 25 | #include "gpiomux-v2.h" | ||
| 26 | #else | ||
| 27 | #include "gpiomux-v1.h" | 23 | #include "gpiomux-v1.h" |
| 28 | #endif | ||
| 29 | 24 | ||
| 30 | /** | 25 | /** |
| 31 | * struct msm_gpiomux_config: gpiomux settings for one gpio line. | 26 | * struct msm_gpiomux_config: gpiomux settings for one gpio line. |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index 9819a556acae..7bca8d7108d6 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h | |||
| @@ -32,13 +32,6 @@ | |||
| 32 | * | 32 | * |
| 33 | */ | 33 | */ |
| 34 | 34 | ||
| 35 | |||
| 36 | #define MSM8960_QGIC_DIST_PHYS 0x02000000 | ||
| 37 | #define MSM8960_QGIC_DIST_SIZE SZ_4K | ||
| 38 | |||
| 39 | #define MSM8960_QGIC_CPU_PHYS 0x02002000 | ||
| 40 | #define MSM8960_QGIC_CPU_SIZE SZ_4K | ||
| 41 | |||
| 42 | #define MSM8960_TMR_PHYS 0x0200A000 | 35 | #define MSM8960_TMR_PHYS 0x0200A000 |
| 43 | #define MSM8960_TMR_SIZE SZ_4K | 36 | #define MSM8960_TMR_SIZE SZ_4K |
| 44 | 37 | ||
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 199372e62def..75a7b62c1c74 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | |||
| @@ -35,12 +35,6 @@ | |||
| 35 | * | 35 | * |
| 36 | */ | 36 | */ |
| 37 | 37 | ||
| 38 | #define MSM8X60_QGIC_DIST_PHYS 0x02080000 | ||
| 39 | #define MSM8X60_QGIC_DIST_SIZE SZ_4K | ||
| 40 | |||
| 41 | #define MSM8X60_QGIC_CPU_PHYS 0x02081000 | ||
| 42 | #define MSM8X60_QGIC_CPU_SIZE SZ_4K | ||
| 43 | |||
| 44 | #define MSM_TLMM_BASE IOMEM(0xF0004000) | 38 | #define MSM_TLMM_BASE IOMEM(0xF0004000) |
| 45 | #define MSM_TLMM_PHYS 0x00800000 | 39 | #define MSM_TLMM_PHYS 0x00800000 |
| 46 | #define MSM_TLMM_SIZE SZ_16K | 40 | #define MSM_TLMM_SIZE SZ_16K |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 2ab7cf0919b3..c56e81ffdcde 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h | |||
| @@ -62,8 +62,6 @@ | |||
| 62 | 62 | ||
| 63 | /* Virtual addresses shared across all MSM targets. */ | 63 | /* Virtual addresses shared across all MSM targets. */ |
| 64 | #define MSM_CSR_BASE IOMEM(0xE0001000) | 64 | #define MSM_CSR_BASE IOMEM(0xE0001000) |
| 65 | #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) | ||
| 66 | #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) | ||
| 67 | #define MSM_TMR_BASE IOMEM(0xF0200000) | 65 | #define MSM_TMR_BASE IOMEM(0xF0200000) |
| 68 | #define MSM_TMR0_BASE IOMEM(0xF0201000) | 66 | #define MSM_TMR0_BASE IOMEM(0xF0201000) |
| 69 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | 67 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) |
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 123ef9cbce1b..efa113e4de86 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c | |||
| @@ -107,8 +107,6 @@ void __init msm_map_qsd8x50_io(void) | |||
| 107 | 107 | ||
| 108 | #ifdef CONFIG_ARCH_MSM8X60 | 108 | #ifdef CONFIG_ARCH_MSM8X60 |
| 109 | static struct map_desc msm8x60_io_desc[] __initdata = { | 109 | static struct map_desc msm8x60_io_desc[] __initdata = { |
| 110 | MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), | ||
| 111 | MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), | ||
| 112 | MSM_CHIP_DEVICE(TMR, MSM8X60), | 110 | MSM_CHIP_DEVICE(TMR, MSM8X60), |
| 113 | MSM_CHIP_DEVICE(TMR0, MSM8X60), | 111 | MSM_CHIP_DEVICE(TMR0, MSM8X60), |
| 114 | #ifdef CONFIG_DEBUG_MSM8660_UART | 112 | #ifdef CONFIG_DEBUG_MSM8660_UART |
| @@ -124,8 +122,6 @@ void __init msm_map_msm8x60_io(void) | |||
| 124 | 122 | ||
| 125 | #ifdef CONFIG_ARCH_MSM8960 | 123 | #ifdef CONFIG_ARCH_MSM8960 |
| 126 | static struct map_desc msm8960_io_desc[] __initdata = { | 124 | static struct map_desc msm8960_io_desc[] __initdata = { |
| 127 | MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), | ||
| 128 | MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), | ||
| 129 | MSM_CHIP_DEVICE(TMR, MSM8960), | 125 | MSM_CHIP_DEVICE(TMR, MSM8960), |
| 130 | MSM_CHIP_DEVICE(TMR0, MSM8960), | 126 | MSM_CHIP_DEVICE(TMR0, MSM8960), |
| 131 | #ifdef CONFIG_DEBUG_MSM8960_UART | 127 | #ifdef CONFIG_DEBUG_MSM8960_UART |
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 1c48890bb72b..cf8e357a0a02 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <linux/clk/mvebu.h> | 20 | #include <linux/clk/mvebu.h> |
| 21 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/mbus.h> | 22 | #include <linux/mbus.h> |
| 23 | #include <linux/irqchip.h> | ||
| 24 | #include <asm/hardware/cache-l2x0.h> | 23 | #include <asm/hardware/cache-l2x0.h> |
| 25 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| @@ -38,18 +37,18 @@ static struct map_desc armada_370_xp_io_desc[] __initdata = { | |||
| 38 | }, | 37 | }, |
| 39 | }; | 38 | }; |
| 40 | 39 | ||
| 41 | void __init armada_370_xp_map_io(void) | 40 | static void __init armada_370_xp_map_io(void) |
| 42 | { | 41 | { |
| 43 | iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); | 42 | iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); |
| 44 | } | 43 | } |
| 45 | 44 | ||
| 46 | void __init armada_370_xp_timer_and_clk_init(void) | 45 | static void __init armada_370_xp_timer_and_clk_init(void) |
| 47 | { | 46 | { |
| 48 | mvebu_clocks_init(); | 47 | mvebu_clocks_init(); |
| 49 | armada_370_xp_timer_init(); | 48 | armada_370_xp_timer_init(); |
| 50 | } | 49 | } |
| 51 | 50 | ||
| 52 | void __init armada_370_xp_init_early(void) | 51 | static void __init armada_370_xp_init_early(void) |
| 53 | { | 52 | { |
| 54 | char *mbus_soc_name; | 53 | char *mbus_soc_name; |
| 55 | 54 | ||
| @@ -89,7 +88,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") | |||
| 89 | .init_machine = armada_370_xp_dt_init, | 88 | .init_machine = armada_370_xp_dt_init, |
| 90 | .map_io = armada_370_xp_map_io, | 89 | .map_io = armada_370_xp_map_io, |
| 91 | .init_early = armada_370_xp_init_early, | 90 | .init_early = armada_370_xp_init_early, |
| 92 | .init_irq = irqchip_init, | ||
| 93 | .init_time = armada_370_xp_timer_and_clk_init, | 91 | .init_time = armada_370_xp_timer_and_clk_init, |
| 94 | .restart = mvebu_restart, | 92 | .restart = mvebu_restart, |
| 95 | .dt_compat = armada_370_xp_dt_compat, | 93 | .dt_compat = armada_370_xp_dt_compat, |
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 5b62b6489d4b..d67ecc1c8847 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
| @@ -434,7 +434,6 @@ static const char *mxs_dt_compat[] __initdata = { | |||
| 434 | }; | 434 | }; |
| 435 | 435 | ||
| 436 | DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") | 436 | DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") |
| 437 | .map_io = debug_ll_io_init, | ||
| 438 | .init_irq = irqchip_init, | 437 | .init_irq = irqchip_init, |
| 439 | .handle_irq = icoll_handle_irq, | 438 | .handle_irq = icoll_handle_irq, |
| 440 | .init_time = mxs_timer_init, | 439 | .init_time = mxs_timer_init, |
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 59f6ff5c9bae..46cce9baa129 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
| 26 | #include <linux/irq.h> | 26 | #include <linux/irq.h> |
| 27 | #include <linux/dma-mapping.h> | 27 | #include <linux/dma-mapping.h> |
| 28 | #include <linux/irqchip.h> | ||
| 29 | #include <linux/platform_data/clk-nomadik.h> | 28 | #include <linux/platform_data/clk-nomadik.h> |
| 30 | #include <linux/platform_data/pinctrl-nomadik.h> | 29 | #include <linux/platform_data/pinctrl-nomadik.h> |
| 31 | #include <linux/pinctrl/machine.h> | 30 | #include <linux/pinctrl/machine.h> |
| @@ -323,7 +322,6 @@ static const char * cpu8815_board_compat[] = { | |||
| 323 | 322 | ||
| 324 | DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815") | 323 | DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815") |
| 325 | .map_io = cpu8815_map_io, | 324 | .map_io = cpu8815_map_io, |
| 326 | .init_irq = irqchip_init, | ||
| 327 | .init_time = cpu8815_timer_init_of, | 325 | .init_time = cpu8815_timer_init_of, |
| 328 | .init_machine = cpu8815_init_of, | 326 | .init_machine = cpu8815_init_of, |
| 329 | .restart = cpu8815_restart, | 327 | .restart = cpu8815_restart, |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index f49cd51e162a..6903d47f6251 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -167,12 +167,6 @@ config OMAP_PACKAGE_CUS | |||
| 167 | config OMAP_PACKAGE_CBP | 167 | config OMAP_PACKAGE_CBP |
| 168 | bool | 168 | bool |
| 169 | 169 | ||
| 170 | config OMAP_PACKAGE_CBL | ||
| 171 | bool | ||
| 172 | |||
| 173 | config OMAP_PACKAGE_CBS | ||
| 174 | bool | ||
| 175 | |||
| 176 | comment "OMAP Board Type" | 170 | comment "OMAP Board Type" |
| 177 | depends on ARCH_OMAP2PLUS | 171 | depends on ARCH_OMAP2PLUS |
| 178 | 172 | ||
| @@ -378,22 +372,6 @@ config MACH_TI8148EVM | |||
| 378 | depends on SOC_TI81XX | 372 | depends on SOC_TI81XX |
| 379 | default y | 373 | default y |
| 380 | 374 | ||
| 381 | config MACH_OMAP_4430SDP | ||
| 382 | bool "OMAP 4430 SDP board" | ||
| 383 | default y | ||
| 384 | depends on ARCH_OMAP4 | ||
| 385 | select OMAP_PACKAGE_CBL | ||
| 386 | select OMAP_PACKAGE_CBS | ||
| 387 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
| 388 | |||
| 389 | config MACH_OMAP4_PANDA | ||
| 390 | bool "OMAP4 Panda Board" | ||
| 391 | default y | ||
| 392 | depends on ARCH_OMAP4 | ||
| 393 | select OMAP_PACKAGE_CBL | ||
| 394 | select OMAP_PACKAGE_CBS | ||
| 395 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
| 396 | |||
| 397 | config OMAP3_EMU | 375 | config OMAP3_EMU |
| 398 | bool "OMAP3 debugging peripherals" | 376 | bool "OMAP3 debugging peripherals" |
| 399 | depends on ARCH_OMAP3 | 377 | depends on ARCH_OMAP3 |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a4f1d2a78d98..add1d27a7d94 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -63,7 +63,6 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o | |||
| 63 | obj-$(CONFIG_SOC_OMAP2420) += mux2420.o | 63 | obj-$(CONFIG_SOC_OMAP2420) += mux2420.o |
| 64 | obj-$(CONFIG_SOC_OMAP2430) += mux2430.o | 64 | obj-$(CONFIG_SOC_OMAP2430) += mux2430.o |
| 65 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o | 65 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o |
| 66 | obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o | ||
| 67 | 66 | ||
| 68 | # SMS/SDRC | 67 | # SMS/SDRC |
| 69 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | 68 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o |
| @@ -250,8 +249,6 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o | |||
| 250 | obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o | 249 | obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o |
| 251 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o | 250 | obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o |
| 252 | obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o | 251 | obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o |
| 253 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o | ||
| 254 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o | ||
| 255 | 252 | ||
| 256 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 253 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
| 257 | 254 | ||
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c deleted file mode 100644 index 56a9a4f855c7..000000000000 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ /dev/null | |||
| @@ -1,765 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Board support file for OMAP4430 SDP. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments | ||
| 5 | * | ||
| 6 | * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 7 | * | ||
| 8 | * Based on mach-omap2/board-3430sdp.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | #include <linux/gpio.h> | ||
| 20 | #include <linux/usb/otg.h> | ||
| 21 | #include <linux/spi/spi.h> | ||
| 22 | #include <linux/i2c/twl.h> | ||
| 23 | #include <linux/mfd/twl6040.h> | ||
| 24 | #include <linux/gpio_keys.h> | ||
| 25 | #include <linux/regulator/machine.h> | ||
| 26 | #include <linux/regulator/fixed.h> | ||
| 27 | #include <linux/pwm.h> | ||
| 28 | #include <linux/leds.h> | ||
| 29 | #include <linux/leds_pwm.h> | ||
| 30 | #include <linux/pwm_backlight.h> | ||
| 31 | #include <linux/irqchip/arm-gic.h> | ||
| 32 | #include <linux/platform_data/omap4-keypad.h> | ||
| 33 | #include <linux/usb/musb.h> | ||
| 34 | #include <linux/usb/phy.h> | ||
| 35 | |||
| 36 | #include <asm/mach-types.h> | ||
| 37 | #include <asm/mach/arch.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | |||
| 40 | #include "common.h" | ||
| 41 | #include "omap4-keypad.h" | ||
| 42 | #include <linux/wl12xx.h> | ||
| 43 | #include <linux/platform_data/omap-abe-twl6040.h> | ||
| 44 | |||
| 45 | #include "soc.h" | ||
| 46 | #include "mux.h" | ||
| 47 | #include "mmc.h" | ||
| 48 | #include "hsmmc.h" | ||
| 49 | #include "control.h" | ||
| 50 | #include "common-board-devices.h" | ||
| 51 | #include "dss-common.h" | ||
| 52 | |||
| 53 | #define ETH_KS8851_IRQ 34 | ||
| 54 | #define ETH_KS8851_POWER_ON 48 | ||
| 55 | #define ETH_KS8851_QUART 138 | ||
| 56 | #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 | ||
| 57 | #define OMAP4_SFH7741_ENABLE_GPIO 188 | ||
| 58 | |||
| 59 | #define GPIO_WIFI_PMENA 54 | ||
| 60 | #define GPIO_WIFI_IRQ 53 | ||
| 61 | |||
| 62 | static const int sdp4430_keymap[] = { | ||
| 63 | KEY(0, 0, KEY_E), | ||
| 64 | KEY(0, 1, KEY_R), | ||
| 65 | KEY(0, 2, KEY_T), | ||
| 66 | KEY(0, 3, KEY_HOME), | ||
| 67 | KEY(0, 4, KEY_F5), | ||
| 68 | KEY(0, 5, KEY_UNKNOWN), | ||
| 69 | KEY(0, 6, KEY_I), | ||
| 70 | KEY(0, 7, KEY_LEFTSHIFT), | ||
| 71 | |||
| 72 | KEY(1, 0, KEY_D), | ||
| 73 | KEY(1, 1, KEY_F), | ||
| 74 | KEY(1, 2, KEY_G), | ||
| 75 | KEY(1, 3, KEY_SEND), | ||
| 76 | KEY(1, 4, KEY_F6), | ||
| 77 | KEY(1, 5, KEY_UNKNOWN), | ||
| 78 | KEY(1, 6, KEY_K), | ||
| 79 | KEY(1, 7, KEY_ENTER), | ||
| 80 | |||
| 81 | KEY(2, 0, KEY_X), | ||
| 82 | KEY(2, 1, KEY_C), | ||
| 83 | KEY(2, 2, KEY_V), | ||
| 84 | KEY(2, 3, KEY_END), | ||
| 85 | KEY(2, 4, KEY_F7), | ||
| 86 | KEY(2, 5, KEY_UNKNOWN), | ||
| 87 | KEY(2, 6, KEY_DOT), | ||
| 88 | KEY(2, 7, KEY_CAPSLOCK), | ||
| 89 | |||
| 90 | KEY(3, 0, KEY_Z), | ||
| 91 | KEY(3, 1, KEY_KPPLUS), | ||
| 92 | KEY(3, 2, KEY_B), | ||
| 93 | KEY(3, 3, KEY_F1), | ||
| 94 | KEY(3, 4, KEY_F8), | ||
| 95 | KEY(3, 5, KEY_UNKNOWN), | ||
| 96 | KEY(3, 6, KEY_O), | ||
| 97 | KEY(3, 7, KEY_SPACE), | ||
| 98 | |||
| 99 | KEY(4, 0, KEY_W), | ||
| 100 | KEY(4, 1, KEY_Y), | ||
| 101 | KEY(4, 2, KEY_U), | ||
| 102 | KEY(4, 3, KEY_F2), | ||
| 103 | KEY(4, 4, KEY_VOLUMEUP), | ||
| 104 | KEY(4, 5, KEY_UNKNOWN), | ||
| 105 | KEY(4, 6, KEY_L), | ||
| 106 | KEY(4, 7, KEY_LEFT), | ||
| 107 | |||
| 108 | KEY(5, 0, KEY_S), | ||
| 109 | KEY(5, 1, KEY_H), | ||
| 110 | KEY(5, 2, KEY_J), | ||
| 111 | KEY(5, 3, KEY_F3), | ||
| 112 | KEY(5, 4, KEY_F9), | ||
| 113 | KEY(5, 5, KEY_VOLUMEDOWN), | ||
| 114 | KEY(5, 6, KEY_M), | ||
| 115 | KEY(5, 7, KEY_RIGHT), | ||
| 116 | |||
| 117 | KEY(6, 0, KEY_Q), | ||
| 118 | KEY(6, 1, KEY_A), | ||
| 119 | KEY(6, 2, KEY_N), | ||
| 120 | KEY(6, 3, KEY_BACK), | ||
| 121 | KEY(6, 4, KEY_BACKSPACE), | ||
| 122 | KEY(6, 5, KEY_UNKNOWN), | ||
| 123 | KEY(6, 6, KEY_P), | ||
| 124 | KEY(6, 7, KEY_UP), | ||
| 125 | |||
| 126 | KEY(7, 0, KEY_PROG1), | ||
| 127 | KEY(7, 1, KEY_PROG2), | ||
| 128 | KEY(7, 2, KEY_PROG3), | ||
| 129 | KEY(7, 3, KEY_PROG4), | ||
| 130 | KEY(7, 4, KEY_F4), | ||
| 131 | KEY(7, 5, KEY_UNKNOWN), | ||
| 132 | KEY(7, 6, KEY_OK), | ||
| 133 | KEY(7, 7, KEY_DOWN), | ||
| 134 | }; | ||
| 135 | static struct omap_device_pad keypad_pads[] = { | ||
| 136 | { .name = "kpd_col1.kpd_col1", | ||
| 137 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 138 | }, | ||
| 139 | { .name = "kpd_col1.kpd_col1", | ||
| 140 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 141 | }, | ||
| 142 | { .name = "kpd_col2.kpd_col2", | ||
| 143 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 144 | }, | ||
| 145 | { .name = "kpd_col3.kpd_col3", | ||
| 146 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 147 | }, | ||
| 148 | { .name = "kpd_col4.kpd_col4", | ||
| 149 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 150 | }, | ||
| 151 | { .name = "kpd_col5.kpd_col5", | ||
| 152 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 153 | }, | ||
| 154 | { .name = "gpmc_a23.kpd_col7", | ||
| 155 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 156 | }, | ||
| 157 | { .name = "gpmc_a22.kpd_col6", | ||
| 158 | .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, | ||
| 159 | }, | ||
| 160 | { .name = "kpd_row0.kpd_row0", | ||
| 161 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 162 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 163 | }, | ||
| 164 | { .name = "kpd_row1.kpd_row1", | ||
| 165 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 166 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 167 | }, | ||
| 168 | { .name = "kpd_row2.kpd_row2", | ||
| 169 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 170 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 171 | }, | ||
| 172 | { .name = "kpd_row3.kpd_row3", | ||
| 173 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 174 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 175 | }, | ||
| 176 | { .name = "kpd_row4.kpd_row4", | ||
| 177 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 178 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 179 | }, | ||
| 180 | { .name = "kpd_row5.kpd_row5", | ||
| 181 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 182 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 183 | }, | ||
| 184 | { .name = "gpmc_a18.kpd_row6", | ||
| 185 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 186 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 187 | }, | ||
| 188 | { .name = "gpmc_a19.kpd_row7", | ||
| 189 | .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | | ||
| 190 | OMAP_MUX_MODE1 | OMAP_INPUT_EN, | ||
| 191 | }, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct matrix_keymap_data sdp4430_keymap_data = { | ||
| 195 | .keymap = sdp4430_keymap, | ||
| 196 | .keymap_size = ARRAY_SIZE(sdp4430_keymap), | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct omap4_keypad_platform_data sdp4430_keypad_data = { | ||
| 200 | .keymap_data = &sdp4430_keymap_data, | ||
| 201 | .rows = 8, | ||
| 202 | .cols = 8, | ||
| 203 | }; | ||
| 204 | |||
| 205 | static struct omap_board_data keypad_data = { | ||
| 206 | .id = 1, | ||
| 207 | .pads = keypad_pads, | ||
| 208 | .pads_cnt = ARRAY_SIZE(keypad_pads), | ||
| 209 | }; | ||
| 210 | |||
| 211 | static struct gpio_led sdp4430_gpio_leds[] = { | ||
| 212 | { | ||
| 213 | .name = "omap4:green:debug0", | ||
| 214 | .gpio = 61, | ||
| 215 | }, | ||
| 216 | { | ||
| 217 | .name = "omap4:green:debug1", | ||
| 218 | .gpio = 30, | ||
| 219 | }, | ||
| 220 | { | ||
| 221 | .name = "omap4:green:debug2", | ||
| 222 | .gpio = 7, | ||
| 223 | }, | ||
| 224 | { | ||
| 225 | .name = "omap4:green:debug3", | ||
| 226 | .gpio = 8, | ||
| 227 | }, | ||
| 228 | { | ||
| 229 | .name = "omap4:green:debug4", | ||
| 230 | .gpio = 50, | ||
| 231 | }, | ||
| 232 | { | ||
| 233 | .name = "omap4:blue:user", | ||
| 234 | .gpio = 169, | ||
| 235 | }, | ||
| 236 | { | ||
| 237 | .name = "omap4:red:user", | ||
| 238 | .gpio = 170, | ||
| 239 | }, | ||
| 240 | { | ||
| 241 | .name = "omap4:green:user", | ||
| 242 | .gpio = 139, | ||
| 243 | }, | ||
| 244 | |||
| 245 | }; | ||
| 246 | |||
| 247 | static struct gpio_keys_button sdp4430_gpio_keys[] = { | ||
| 248 | { | ||
| 249 | .desc = "Proximity Sensor", | ||
| 250 | .type = EV_SW, | ||
| 251 | .code = SW_FRONT_PROXIMITY, | ||
| 252 | .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO, | ||
| 253 | .active_low = 0, | ||
| 254 | } | ||
| 255 | }; | ||
| 256 | |||
| 257 | static struct gpio_led_platform_data sdp4430_led_data = { | ||
| 258 | .leds = sdp4430_gpio_leds, | ||
| 259 | .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), | ||
| 260 | }; | ||
| 261 | |||
| 262 | static struct pwm_lookup sdp4430_pwm_lookup[] = { | ||
| 263 | PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"), | ||
| 264 | PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL), | ||
| 265 | PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"), | ||
| 266 | }; | ||
| 267 | |||
| 268 | static struct led_pwm sdp4430_pwm_leds[] = { | ||
| 269 | { | ||
| 270 | .name = "omap4::keypad", | ||
| 271 | .max_brightness = 127, | ||
| 272 | .pwm_period_ns = 7812500, | ||
| 273 | }, | ||
| 274 | { | ||
| 275 | .name = "omap4:green:chrg", | ||
| 276 | .max_brightness = 255, | ||
| 277 | .pwm_period_ns = 7812500, | ||
| 278 | }, | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct led_pwm_platform_data sdp4430_pwm_data = { | ||
| 282 | .num_leds = ARRAY_SIZE(sdp4430_pwm_leds), | ||
| 283 | .leds = sdp4430_pwm_leds, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct platform_device sdp4430_leds_pwm = { | ||
| 287 | .name = "leds_pwm", | ||
| 288 | .id = -1, | ||
| 289 | .dev = { | ||
| 290 | .platform_data = &sdp4430_pwm_data, | ||
| 291 | }, | ||
| 292 | }; | ||
| 293 | |||
| 294 | /* Dummy regulator for pwm-backlight driver */ | ||
| 295 | static struct regulator_consumer_supply backlight_supply = | ||
| 296 | REGULATOR_SUPPLY("enable", "pwm-backlight"); | ||
| 297 | |||
| 298 | static struct platform_pwm_backlight_data sdp4430_backlight_data = { | ||
| 299 | .max_brightness = 127, | ||
| 300 | .dft_brightness = 127, | ||
| 301 | .pwm_period_ns = 7812500, | ||
| 302 | }; | ||
| 303 | |||
| 304 | static struct platform_device sdp4430_backlight_pwm = { | ||
| 305 | .name = "pwm-backlight", | ||
| 306 | .id = -1, | ||
| 307 | .dev = { | ||
| 308 | .platform_data = &sdp4430_backlight_data, | ||
| 309 | }, | ||
| 310 | }; | ||
| 311 | |||
| 312 | static int omap_prox_activate(struct device *dev) | ||
| 313 | { | ||
| 314 | gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); | ||
| 315 | return 0; | ||
| 316 | } | ||
| 317 | |||
| 318 | static void omap_prox_deactivate(struct device *dev) | ||
| 319 | { | ||
| 320 | gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0); | ||
| 321 | } | ||
| 322 | |||
| 323 | static struct gpio_keys_platform_data sdp4430_gpio_keys_data = { | ||
| 324 | .buttons = sdp4430_gpio_keys, | ||
| 325 | .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys), | ||
| 326 | .enable = omap_prox_activate, | ||
| 327 | .disable = omap_prox_deactivate, | ||
| 328 | }; | ||
| 329 | |||
| 330 | static struct platform_device sdp4430_gpio_keys_device = { | ||
| 331 | .name = "gpio-keys", | ||
| 332 | .id = -1, | ||
| 333 | .dev = { | ||
| 334 | .platform_data = &sdp4430_gpio_keys_data, | ||
| 335 | }, | ||
| 336 | }; | ||
| 337 | |||
| 338 | static struct platform_device sdp4430_leds_gpio = { | ||
| 339 | .name = "leds-gpio", | ||
| 340 | .id = -1, | ||
| 341 | .dev = { | ||
| 342 | .platform_data = &sdp4430_led_data, | ||
| 343 | }, | ||
| 344 | }; | ||
| 345 | static struct spi_board_info sdp4430_spi_board_info[] __initdata = { | ||
| 346 | { | ||
| 347 | .modalias = "ks8851", | ||
| 348 | .bus_num = 1, | ||
| 349 | .chip_select = 0, | ||
| 350 | .max_speed_hz = 24000000, | ||
| 351 | /* | ||
| 352 | * .irq is set to gpio_to_irq(ETH_KS8851_IRQ) | ||
| 353 | * in omap_4430sdp_init | ||
| 354 | */ | ||
| 355 | }, | ||
| 356 | }; | ||
| 357 | |||
| 358 | static struct gpio sdp4430_eth_gpios[] __initdata = { | ||
| 359 | { ETH_KS8851_POWER_ON, GPIOF_OUT_INIT_HIGH, "eth_power" }, | ||
| 360 | { ETH_KS8851_QUART, GPIOF_OUT_INIT_HIGH, "quart" }, | ||
| 361 | { ETH_KS8851_IRQ, GPIOF_IN, "eth_irq" }, | ||
| 362 | }; | ||
| 363 | |||
| 364 | static int __init omap_ethernet_init(void) | ||
| 365 | { | ||
| 366 | int status; | ||
| 367 | |||
| 368 | /* Request of GPIO lines */ | ||
| 369 | status = gpio_request_array(sdp4430_eth_gpios, | ||
| 370 | ARRAY_SIZE(sdp4430_eth_gpios)); | ||
| 371 | if (status) | ||
| 372 | pr_err("Cannot request ETH GPIOs\n"); | ||
| 373 | |||
| 374 | return status; | ||
| 375 | } | ||
| 376 | |||
| 377 | static struct regulator_consumer_supply sdp4430_vbat_supply[] = { | ||
| 378 | REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"), | ||
| 379 | REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"), | ||
| 380 | }; | ||
| 381 | |||
| 382 | static struct regulator_init_data sdp4430_vbat_data = { | ||
| 383 | .constraints = { | ||
| 384 | .always_on = 1, | ||
| 385 | }, | ||
| 386 | .num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply), | ||
| 387 | .consumer_supplies = sdp4430_vbat_supply, | ||
| 388 | }; | ||
| 389 | |||
| 390 | static struct fixed_voltage_config sdp4430_vbat_pdata = { | ||
| 391 | .supply_name = "VBAT", | ||
| 392 | .microvolts = 3750000, | ||
| 393 | .init_data = &sdp4430_vbat_data, | ||
| 394 | .gpio = -EINVAL, | ||
| 395 | }; | ||
| 396 | |||
| 397 | static struct platform_device sdp4430_vbat = { | ||
| 398 | .name = "reg-fixed-voltage", | ||
| 399 | .id = -1, | ||
| 400 | .dev = { | ||
| 401 | .platform_data = &sdp4430_vbat_pdata, | ||
| 402 | }, | ||
| 403 | }; | ||
| 404 | |||
| 405 | static struct platform_device sdp4430_dmic_codec = { | ||
| 406 | .name = "dmic-codec", | ||
| 407 | .id = -1, | ||
| 408 | }; | ||
| 409 | |||
| 410 | static struct platform_device sdp4430_hdmi_audio_codec = { | ||
| 411 | .name = "hdmi-audio-codec", | ||
| 412 | .id = -1, | ||
| 413 | }; | ||
| 414 | |||
| 415 | static struct omap_abe_twl6040_data sdp4430_abe_audio_data = { | ||
| 416 | .card_name = "SDP4430", | ||
| 417 | .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 418 | .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 419 | .has_ep = 1, | ||
| 420 | .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 421 | .has_vibra = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 422 | |||
| 423 | .has_dmic = 1, | ||
| 424 | .has_hsmic = 1, | ||
| 425 | .has_mainmic = 1, | ||
| 426 | .has_submic = 1, | ||
| 427 | .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 428 | |||
| 429 | .jack_detection = 1, | ||
| 430 | /* MCLK input is 38.4MHz */ | ||
| 431 | .mclk_freq = 38400000, | ||
| 432 | }; | ||
| 433 | |||
| 434 | static struct platform_device sdp4430_abe_audio = { | ||
| 435 | .name = "omap-abe-twl6040", | ||
| 436 | .id = -1, | ||
| 437 | .dev = { | ||
| 438 | .platform_data = &sdp4430_abe_audio_data, | ||
| 439 | }, | ||
| 440 | }; | ||
| 441 | |||
| 442 | static struct platform_device *sdp4430_devices[] __initdata = { | ||
| 443 | &sdp4430_gpio_keys_device, | ||
| 444 | &sdp4430_leds_gpio, | ||
| 445 | &sdp4430_leds_pwm, | ||
| 446 | &sdp4430_backlight_pwm, | ||
| 447 | &sdp4430_vbat, | ||
| 448 | &sdp4430_dmic_codec, | ||
| 449 | &sdp4430_abe_audio, | ||
| 450 | &sdp4430_hdmi_audio_codec, | ||
| 451 | }; | ||
| 452 | |||
| 453 | static struct omap_musb_board_data musb_board_data = { | ||
| 454 | .interface_type = MUSB_INTERFACE_UTMI, | ||
| 455 | .mode = MUSB_OTG, | ||
| 456 | .power = 100, | ||
| 457 | }; | ||
| 458 | |||
| 459 | static struct omap2_hsmmc_info mmc[] = { | ||
| 460 | { | ||
| 461 | .mmc = 2, | ||
| 462 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, | ||
| 463 | .gpio_cd = -EINVAL, | ||
| 464 | .gpio_wp = -EINVAL, | ||
| 465 | .nonremovable = true, | ||
| 466 | .ocr_mask = MMC_VDD_29_30, | ||
| 467 | .no_off_init = true, | ||
| 468 | }, | ||
| 469 | { | ||
| 470 | .mmc = 1, | ||
| 471 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, | ||
| 472 | .gpio_cd = -EINVAL, | ||
| 473 | .gpio_wp = -EINVAL, | ||
| 474 | }, | ||
| 475 | { | ||
| 476 | .mmc = 5, | ||
| 477 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, | ||
| 478 | .pm_caps = MMC_PM_KEEP_POWER, | ||
| 479 | .gpio_cd = -EINVAL, | ||
| 480 | .gpio_wp = -EINVAL, | ||
| 481 | .ocr_mask = MMC_VDD_165_195, | ||
| 482 | .nonremovable = true, | ||
| 483 | }, | ||
| 484 | {} /* Terminator */ | ||
| 485 | }; | ||
| 486 | |||
| 487 | static struct regulator_consumer_supply sdp4430_vaux_supply[] = { | ||
| 488 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), | ||
| 489 | }; | ||
| 490 | |||
| 491 | static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = { | ||
| 492 | .supply = "vmmc", | ||
| 493 | .dev_name = "omap_hsmmc.4", | ||
| 494 | }; | ||
| 495 | |||
| 496 | static struct regulator_init_data sdp4430_vmmc5 = { | ||
| 497 | .constraints = { | ||
| 498 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 499 | }, | ||
| 500 | .num_consumer_supplies = 1, | ||
| 501 | .consumer_supplies = &omap4_sdp4430_vmmc5_supply, | ||
| 502 | }; | ||
| 503 | |||
| 504 | static struct fixed_voltage_config sdp4430_vwlan = { | ||
| 505 | .supply_name = "vwl1271", | ||
| 506 | .microvolts = 1800000, /* 1.8V */ | ||
| 507 | .gpio = GPIO_WIFI_PMENA, | ||
| 508 | .startup_delay = 70000, /* 70msec */ | ||
| 509 | .enable_high = 1, | ||
| 510 | .enabled_at_boot = 0, | ||
| 511 | .init_data = &sdp4430_vmmc5, | ||
| 512 | }; | ||
| 513 | |||
| 514 | static struct platform_device omap_vwlan_device = { | ||
| 515 | .name = "reg-fixed-voltage", | ||
| 516 | .id = 1, | ||
| 517 | .dev = { | ||
| 518 | .platform_data = &sdp4430_vwlan, | ||
| 519 | }, | ||
| 520 | }; | ||
| 521 | |||
| 522 | static struct regulator_init_data sdp4430_vaux1 = { | ||
| 523 | .constraints = { | ||
| 524 | .min_uV = 1000000, | ||
| 525 | .max_uV = 3000000, | ||
| 526 | .apply_uV = true, | ||
| 527 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 528 | | REGULATOR_MODE_STANDBY, | ||
| 529 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 530 | | REGULATOR_CHANGE_MODE | ||
| 531 | | REGULATOR_CHANGE_STATUS, | ||
| 532 | }, | ||
| 533 | .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply), | ||
| 534 | .consumer_supplies = sdp4430_vaux_supply, | ||
| 535 | }; | ||
| 536 | |||
| 537 | static struct regulator_init_data sdp4430_vusim = { | ||
| 538 | .constraints = { | ||
| 539 | .min_uV = 1200000, | ||
| 540 | .max_uV = 2900000, | ||
| 541 | .apply_uV = true, | ||
| 542 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 543 | | REGULATOR_MODE_STANDBY, | ||
| 544 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 545 | | REGULATOR_CHANGE_MODE | ||
| 546 | | REGULATOR_CHANGE_STATUS, | ||
| 547 | }, | ||
| 548 | }; | ||
| 549 | |||
| 550 | static struct twl6040_codec_data twl6040_codec = { | ||
| 551 | /* single-step ramp for headset and handsfree */ | ||
| 552 | .hs_left_step = 0x0f, | ||
| 553 | .hs_right_step = 0x0f, | ||
| 554 | .hf_left_step = 0x1d, | ||
| 555 | .hf_right_step = 0x1d, | ||
| 556 | }; | ||
| 557 | |||
| 558 | static struct twl6040_vibra_data twl6040_vibra = { | ||
| 559 | .vibldrv_res = 8, | ||
| 560 | .vibrdrv_res = 3, | ||
| 561 | .viblmotor_res = 10, | ||
| 562 | .vibrmotor_res = 10, | ||
| 563 | .vddvibl_uV = 0, /* fixed volt supply - VBAT */ | ||
| 564 | .vddvibr_uV = 0, /* fixed volt supply - VBAT */ | ||
| 565 | }; | ||
| 566 | |||
| 567 | static struct twl6040_platform_data twl6040_data = { | ||
| 568 | .codec = &twl6040_codec, | ||
| 569 | .vibra = &twl6040_vibra, | ||
| 570 | .audpwron_gpio = 127, | ||
| 571 | }; | ||
| 572 | |||
| 573 | static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = { | ||
| 574 | { | ||
| 575 | I2C_BOARD_INFO("twl6040", 0x4b), | ||
| 576 | .irq = 119 + OMAP44XX_IRQ_GIC_START, | ||
| 577 | .platform_data = &twl6040_data, | ||
| 578 | }, | ||
| 579 | }; | ||
| 580 | |||
| 581 | static struct twl4030_platform_data sdp4430_twldata = { | ||
| 582 | /* Regulators */ | ||
| 583 | .vusim = &sdp4430_vusim, | ||
| 584 | .vaux1 = &sdp4430_vaux1, | ||
| 585 | }; | ||
| 586 | |||
| 587 | static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { | ||
| 588 | { | ||
| 589 | I2C_BOARD_INFO("tmp105", 0x48), | ||
| 590 | }, | ||
| 591 | { | ||
| 592 | I2C_BOARD_INFO("bh1780", 0x29), | ||
| 593 | }, | ||
| 594 | }; | ||
| 595 | static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { | ||
| 596 | { | ||
| 597 | I2C_BOARD_INFO("hmc5843", 0x1e), | ||
| 598 | }, | ||
| 599 | }; | ||
| 600 | static int __init omap4_i2c_init(void) | ||
| 601 | { | ||
| 602 | omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB, | ||
| 603 | TWL_COMMON_REGULATOR_VDAC | | ||
| 604 | TWL_COMMON_REGULATOR_VAUX2 | | ||
| 605 | TWL_COMMON_REGULATOR_VAUX3 | | ||
| 606 | TWL_COMMON_REGULATOR_VMMC | | ||
| 607 | TWL_COMMON_REGULATOR_VPP | | ||
| 608 | TWL_COMMON_REGULATOR_VANA | | ||
| 609 | TWL_COMMON_REGULATOR_VCXIO | | ||
| 610 | TWL_COMMON_REGULATOR_VUSB | | ||
| 611 | TWL_COMMON_REGULATOR_CLK32KG | | ||
| 612 | TWL_COMMON_REGULATOR_V1V8 | | ||
| 613 | TWL_COMMON_REGULATOR_V2V1); | ||
| 614 | omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo, | ||
| 615 | ARRAY_SIZE(sdp4430_i2c_1_boardinfo)); | ||
| 616 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 617 | omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, | ||
| 618 | ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); | ||
| 619 | omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, | ||
| 620 | ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); | ||
| 621 | return 0; | ||
| 622 | } | ||
| 623 | |||
| 624 | static void __init omap_sfh7741prox_init(void) | ||
| 625 | { | ||
| 626 | int error; | ||
| 627 | |||
| 628 | error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO, | ||
| 629 | GPIOF_OUT_INIT_LOW, "sfh7741"); | ||
| 630 | if (error < 0) | ||
| 631 | pr_err("%s:failed to request GPIO %d, error %d\n", | ||
| 632 | __func__, OMAP4_SFH7741_ENABLE_GPIO, error); | ||
| 633 | } | ||
| 634 | |||
| 635 | #ifdef CONFIG_OMAP_MUX | ||
| 636 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 637 | OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 638 | /* NIRQ2 for twl6040 */ | ||
| 639 | OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 | | ||
| 640 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), | ||
| 641 | /* GPIO_127 for twl6040 */ | ||
| 642 | OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), | ||
| 643 | /* McPDM */ | ||
| 644 | OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 645 | OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 646 | OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 647 | OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 648 | OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 649 | /* DMIC */ | ||
| 650 | OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | ||
| 651 | OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 652 | OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 653 | OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 654 | /* McBSP1 */ | ||
| 655 | OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 656 | OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 657 | OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | | ||
| 658 | OMAP_PULL_ENA), | ||
| 659 | OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 660 | /* McBSP2 */ | ||
| 661 | OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 662 | OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 663 | OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | | ||
| 664 | OMAP_PULL_ENA), | ||
| 665 | OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 666 | |||
| 667 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 668 | }; | ||
| 669 | |||
| 670 | #else | ||
| 671 | #define board_mux NULL | ||
| 672 | #endif | ||
| 673 | |||
| 674 | static void __init omap4_sdp4430_wifi_mux_init(void) | ||
| 675 | { | ||
| 676 | omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | | ||
| 677 | OMAP_PIN_OFF_WAKEUPENABLE); | ||
| 678 | omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT); | ||
| 679 | |||
| 680 | omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd", | ||
| 681 | OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); | ||
| 682 | omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk", | ||
| 683 | OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); | ||
| 684 | omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0", | ||
| 685 | OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); | ||
| 686 | omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1", | ||
| 687 | OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); | ||
| 688 | omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2", | ||
| 689 | OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); | ||
| 690 | omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3", | ||
| 691 | OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); | ||
| 692 | |||
| 693 | } | ||
| 694 | |||
| 695 | static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = { | ||
| 696 | .board_ref_clock = WL12XX_REFCLOCK_26, | ||
| 697 | .board_tcxo_clock = WL12XX_TCXOCLOCK_26, | ||
| 698 | }; | ||
| 699 | |||
| 700 | static void __init omap4_sdp4430_wifi_init(void) | ||
| 701 | { | ||
| 702 | int ret; | ||
| 703 | |||
| 704 | omap4_sdp4430_wifi_mux_init(); | ||
| 705 | omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ); | ||
| 706 | ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data); | ||
| 707 | if (ret) | ||
| 708 | pr_err("Error setting wl12xx data: %d\n", ret); | ||
| 709 | ret = platform_device_register(&omap_vwlan_device); | ||
| 710 | if (ret) | ||
| 711 | pr_err("Error registering wl12xx device: %d\n", ret); | ||
| 712 | } | ||
| 713 | |||
| 714 | static void __init omap_4430sdp_init(void) | ||
| 715 | { | ||
| 716 | int status; | ||
| 717 | int package = OMAP_PACKAGE_CBS; | ||
| 718 | |||
| 719 | if (omap_rev() == OMAP4430_REV_ES1_0) | ||
| 720 | package = OMAP_PACKAGE_CBL; | ||
| 721 | omap4_mux_init(board_mux, NULL, package); | ||
| 722 | |||
| 723 | omap4_i2c_init(); | ||
| 724 | omap_sfh7741prox_init(); | ||
| 725 | regulator_register_always_on(0, "backlight-enable", | ||
| 726 | &backlight_supply, 1, 0); | ||
| 727 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); | ||
| 728 | omap_serial_init(); | ||
| 729 | omap_sdrc_init(NULL, NULL); | ||
| 730 | omap4_sdp4430_wifi_init(); | ||
| 731 | omap4_twl6030_hsmmc_init(mmc); | ||
| 732 | |||
| 733 | usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto"); | ||
| 734 | usb_musb_init(&musb_board_data); | ||
| 735 | |||
| 736 | status = omap_ethernet_init(); | ||
| 737 | if (status) { | ||
| 738 | pr_err("Ethernet initialization failed: %d\n", status); | ||
| 739 | } else { | ||
| 740 | sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ); | ||
| 741 | spi_register_board_info(sdp4430_spi_board_info, | ||
| 742 | ARRAY_SIZE(sdp4430_spi_board_info)); | ||
| 743 | } | ||
| 744 | |||
| 745 | pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup)); | ||
| 746 | status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data); | ||
| 747 | if (status) | ||
| 748 | pr_err("Keypad initialization failed: %d\n", status); | ||
| 749 | |||
| 750 | omap_4430sdp_display_init(); | ||
| 751 | } | ||
| 752 | |||
| 753 | MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") | ||
| 754 | /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ | ||
| 755 | .atag_offset = 0x100, | ||
| 756 | .smp = smp_ops(omap4_smp_ops), | ||
| 757 | .reserve = omap_reserve, | ||
| 758 | .map_io = omap4_map_io, | ||
| 759 | .init_early = omap4430_init_early, | ||
| 760 | .init_irq = gic_init_irq, | ||
| 761 | .init_machine = omap_4430sdp_init, | ||
| 762 | .init_late = omap4430_init_late, | ||
| 763 | .init_time = omap4_local_timer_init, | ||
| 764 | .restart = omap44xx_restart, | ||
| 765 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c deleted file mode 100644 index 1e2c75eee912..000000000000 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ /dev/null | |||
| @@ -1,455 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Board support file for OMAP4430 based PandaBoard. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments | ||
| 5 | * | ||
| 6 | * Author: David Anders <x0132446@ti.com> | ||
| 7 | * | ||
| 8 | * Based on mach-omap2/board-4430sdp.c | ||
| 9 | * | ||
| 10 | * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 11 | * | ||
| 12 | * Based on mach-omap2/board-3430sdp.c | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | #include <linux/leds.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/usb/otg.h> | ||
| 27 | #include <linux/i2c/twl.h> | ||
| 28 | #include <linux/mfd/twl6040.h> | ||
| 29 | #include <linux/regulator/machine.h> | ||
| 30 | #include <linux/regulator/fixed.h> | ||
| 31 | #include <linux/ti_wilink_st.h> | ||
| 32 | #include <linux/usb/musb.h> | ||
| 33 | #include <linux/usb/phy.h> | ||
| 34 | #include <linux/usb/nop-usb-xceiv.h> | ||
| 35 | #include <linux/wl12xx.h> | ||
| 36 | #include <linux/irqchip/arm-gic.h> | ||
| 37 | #include <linux/platform_data/omap-abe-twl6040.h> | ||
| 38 | |||
| 39 | #include <asm/mach-types.h> | ||
| 40 | #include <asm/mach/arch.h> | ||
| 41 | #include <asm/mach/map.h> | ||
| 42 | |||
| 43 | #include "common.h" | ||
| 44 | #include "soc.h" | ||
| 45 | #include "mmc.h" | ||
| 46 | #include "hsmmc.h" | ||
| 47 | #include "control.h" | ||
| 48 | #include "mux.h" | ||
| 49 | #include "common-board-devices.h" | ||
| 50 | #include "dss-common.h" | ||
| 51 | |||
| 52 | #define GPIO_HUB_POWER 1 | ||
| 53 | #define GPIO_HUB_NRESET 62 | ||
| 54 | #define GPIO_WIFI_PMENA 43 | ||
| 55 | #define GPIO_WIFI_IRQ 53 | ||
| 56 | |||
| 57 | /* wl127x BT, FM, GPS connectivity chip */ | ||
| 58 | static struct ti_st_plat_data wilink_platform_data = { | ||
| 59 | .nshutdown_gpio = 46, | ||
| 60 | .dev_name = "/dev/ttyO1", | ||
| 61 | .flow_cntrl = 1, | ||
| 62 | .baud_rate = 3000000, | ||
| 63 | .chip_enable = NULL, | ||
| 64 | .suspend = NULL, | ||
| 65 | .resume = NULL, | ||
| 66 | }; | ||
| 67 | |||
| 68 | static struct platform_device wl1271_device = { | ||
| 69 | .name = "kim", | ||
| 70 | .id = -1, | ||
| 71 | .dev = { | ||
| 72 | .platform_data = &wilink_platform_data, | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static struct gpio_led gpio_leds[] = { | ||
| 77 | { | ||
| 78 | .name = "pandaboard::status1", | ||
| 79 | .default_trigger = "heartbeat", | ||
| 80 | .gpio = 7, | ||
| 81 | }, | ||
| 82 | { | ||
| 83 | .name = "pandaboard::status2", | ||
| 84 | .default_trigger = "mmc0", | ||
| 85 | .gpio = 8, | ||
| 86 | }, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 90 | .leds = gpio_leds, | ||
| 91 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 92 | }; | ||
| 93 | |||
| 94 | static struct platform_device leds_gpio = { | ||
| 95 | .name = "leds-gpio", | ||
| 96 | .id = -1, | ||
| 97 | .dev = { | ||
| 98 | .platform_data = &gpio_led_info, | ||
| 99 | }, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct omap_abe_twl6040_data panda_abe_audio_data = { | ||
| 103 | /* Audio out */ | ||
| 104 | .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 105 | /* HandsFree through expansion connector */ | ||
| 106 | .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 107 | /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */ | ||
| 108 | .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 109 | /* PandaBoard: FM RX, PandaBoardES: audio in */ | ||
| 110 | .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, | ||
| 111 | /* No jack detection. */ | ||
| 112 | .jack_detection = 0, | ||
| 113 | /* MCLK input is 38.4MHz */ | ||
| 114 | .mclk_freq = 38400000, | ||
| 115 | |||
| 116 | }; | ||
| 117 | |||
| 118 | static struct platform_device panda_abe_audio = { | ||
| 119 | .name = "omap-abe-twl6040", | ||
| 120 | .id = -1, | ||
| 121 | .dev = { | ||
| 122 | .platform_data = &panda_abe_audio_data, | ||
| 123 | }, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct platform_device panda_hdmi_audio_codec = { | ||
| 127 | .name = "hdmi-audio-codec", | ||
| 128 | .id = -1, | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct platform_device btwilink_device = { | ||
| 132 | .name = "btwilink", | ||
| 133 | .id = -1, | ||
| 134 | }; | ||
| 135 | |||
| 136 | /* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */ | ||
| 137 | static struct nop_usb_xceiv_platform_data hsusb1_phy_data = { | ||
| 138 | /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ | ||
| 139 | .clk_rate = 19200000, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct usbhs_phy_data phy_data[] __initdata = { | ||
| 143 | { | ||
| 144 | .port = 1, | ||
| 145 | .reset_gpio = GPIO_HUB_NRESET, | ||
| 146 | .vcc_gpio = GPIO_HUB_POWER, | ||
| 147 | .vcc_polarity = 1, | ||
| 148 | .platform_data = &hsusb1_phy_data, | ||
| 149 | }, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct platform_device *panda_devices[] __initdata = { | ||
| 153 | &leds_gpio, | ||
| 154 | &wl1271_device, | ||
| 155 | &panda_abe_audio, | ||
| 156 | &panda_hdmi_audio_codec, | ||
| 157 | &btwilink_device, | ||
| 158 | }; | ||
| 159 | |||
| 160 | static struct usbhs_omap_platform_data usbhs_bdata __initdata = { | ||
| 161 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static void __init omap4_ehci_init(void) | ||
| 165 | { | ||
| 166 | int ret; | ||
| 167 | |||
| 168 | /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ | ||
| 169 | ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL); | ||
| 170 | if (ret) | ||
| 171 | pr_err("Failed to add main_clk alias to auxclk3_ck\n"); | ||
| 172 | |||
| 173 | usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); | ||
| 174 | usbhs_init(&usbhs_bdata); | ||
| 175 | } | ||
| 176 | |||
| 177 | static struct omap_musb_board_data musb_board_data = { | ||
| 178 | .interface_type = MUSB_INTERFACE_UTMI, | ||
| 179 | .mode = MUSB_OTG, | ||
| 180 | .power = 100, | ||
| 181 | }; | ||
| 182 | |||
| 183 | static struct omap2_hsmmc_info mmc[] = { | ||
| 184 | { | ||
| 185 | .mmc = 1, | ||
| 186 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, | ||
| 187 | .gpio_wp = -EINVAL, | ||
| 188 | .gpio_cd = -EINVAL, | ||
| 189 | }, | ||
| 190 | { | ||
| 191 | .name = "wl1271", | ||
| 192 | .mmc = 5, | ||
| 193 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, | ||
| 194 | .gpio_wp = -EINVAL, | ||
| 195 | .gpio_cd = -EINVAL, | ||
| 196 | .ocr_mask = MMC_VDD_165_195, | ||
| 197 | .nonremovable = true, | ||
| 198 | }, | ||
| 199 | {} /* Terminator */ | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = { | ||
| 203 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"), | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct regulator_init_data panda_vmmc5 = { | ||
| 207 | .constraints = { | ||
| 208 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 209 | }, | ||
| 210 | .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply), | ||
| 211 | .consumer_supplies = omap4_panda_vmmc5_supply, | ||
| 212 | }; | ||
| 213 | |||
| 214 | static struct fixed_voltage_config panda_vwlan = { | ||
| 215 | .supply_name = "vwl1271", | ||
| 216 | .microvolts = 1800000, /* 1.8V */ | ||
| 217 | .gpio = GPIO_WIFI_PMENA, | ||
| 218 | .startup_delay = 70000, /* 70msec */ | ||
| 219 | .enable_high = 1, | ||
| 220 | .enabled_at_boot = 0, | ||
| 221 | .init_data = &panda_vmmc5, | ||
| 222 | }; | ||
| 223 | |||
| 224 | static struct platform_device omap_vwlan_device = { | ||
| 225 | .name = "reg-fixed-voltage", | ||
| 226 | .id = 1, | ||
| 227 | .dev = { | ||
| 228 | .platform_data = &panda_vwlan, | ||
| 229 | }, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static struct wl12xx_platform_data omap_panda_wlan_data __initdata = { | ||
| 233 | .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct twl6040_codec_data twl6040_codec = { | ||
| 237 | /* single-step ramp for headset and handsfree */ | ||
| 238 | .hs_left_step = 0x0f, | ||
| 239 | .hs_right_step = 0x0f, | ||
| 240 | .hf_left_step = 0x1d, | ||
| 241 | .hf_right_step = 0x1d, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static struct twl6040_platform_data twl6040_data = { | ||
| 245 | .codec = &twl6040_codec, | ||
| 246 | .audpwron_gpio = 127, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = { | ||
| 250 | { | ||
| 251 | I2C_BOARD_INFO("twl6040", 0x4b), | ||
| 252 | .irq = 119 + OMAP44XX_IRQ_GIC_START, | ||
| 253 | .platform_data = &twl6040_data, | ||
| 254 | }, | ||
| 255 | }; | ||
| 256 | |||
| 257 | /* Panda board uses the common PMIC configuration */ | ||
| 258 | static struct twl4030_platform_data omap4_panda_twldata; | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM | ||
| 262 | * is connected as I2C slave device, and can be accessed at address 0x50 | ||
| 263 | */ | ||
| 264 | static struct i2c_board_info __initdata panda_i2c_eeprom[] = { | ||
| 265 | { | ||
| 266 | I2C_BOARD_INFO("eeprom", 0x50), | ||
| 267 | }, | ||
| 268 | }; | ||
| 269 | |||
| 270 | static int __init omap4_panda_i2c_init(void) | ||
| 271 | { | ||
| 272 | omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB, | ||
| 273 | TWL_COMMON_REGULATOR_VDAC | | ||
| 274 | TWL_COMMON_REGULATOR_VAUX2 | | ||
| 275 | TWL_COMMON_REGULATOR_VAUX3 | | ||
| 276 | TWL_COMMON_REGULATOR_VMMC | | ||
| 277 | TWL_COMMON_REGULATOR_VPP | | ||
| 278 | TWL_COMMON_REGULATOR_VANA | | ||
| 279 | TWL_COMMON_REGULATOR_VCXIO | | ||
| 280 | TWL_COMMON_REGULATOR_VUSB | | ||
| 281 | TWL_COMMON_REGULATOR_CLK32KG | | ||
| 282 | TWL_COMMON_REGULATOR_V1V8 | | ||
| 283 | TWL_COMMON_REGULATOR_V2V1); | ||
| 284 | omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo, | ||
| 285 | ARRAY_SIZE(panda_i2c_1_boardinfo)); | ||
| 286 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 287 | /* | ||
| 288 | * Bus 3 is attached to the DVI port where devices like the pico DLP | ||
| 289 | * projector don't work reliably with 400kHz | ||
| 290 | */ | ||
| 291 | omap_register_i2c_bus(3, 100, panda_i2c_eeprom, | ||
| 292 | ARRAY_SIZE(panda_i2c_eeprom)); | ||
| 293 | omap_register_i2c_bus(4, 400, NULL, 0); | ||
| 294 | return 0; | ||
| 295 | } | ||
| 296 | |||
| 297 | #ifdef CONFIG_OMAP_MUX | ||
| 298 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 299 | /* WLAN IRQ - GPIO 53 */ | ||
| 300 | OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), | ||
| 301 | /* WLAN POWER ENABLE - GPIO 43 */ | ||
| 302 | OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), | ||
| 303 | /* WLAN SDIO: MMC5 CMD */ | ||
| 304 | OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 305 | /* WLAN SDIO: MMC5 CLK */ | ||
| 306 | OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 307 | /* WLAN SDIO: MMC5 DAT[0-3] */ | ||
| 308 | OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 309 | OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 310 | OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 311 | OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 312 | /* gpio 0 - TFP410 PD */ | ||
| 313 | OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3), | ||
| 314 | /* dispc2_data23 */ | ||
| 315 | OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 316 | /* dispc2_data22 */ | ||
| 317 | OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 318 | /* dispc2_data21 */ | ||
| 319 | OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 320 | /* dispc2_data20 */ | ||
| 321 | OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 322 | /* dispc2_data19 */ | ||
| 323 | OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 324 | /* dispc2_data18 */ | ||
| 325 | OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 326 | /* dispc2_data15 */ | ||
| 327 | OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 328 | /* dispc2_data14 */ | ||
| 329 | OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 330 | /* dispc2_data13 */ | ||
| 331 | OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 332 | /* dispc2_data12 */ | ||
| 333 | OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 334 | /* dispc2_data11 */ | ||
| 335 | OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 336 | /* dispc2_data10 */ | ||
| 337 | OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 338 | /* dispc2_data9 */ | ||
| 339 | OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 340 | /* dispc2_data16 */ | ||
| 341 | OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 342 | /* dispc2_data17 */ | ||
| 343 | OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 344 | /* dispc2_hsync */ | ||
| 345 | OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 346 | /* dispc2_pclk */ | ||
| 347 | OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 348 | /* dispc2_vsync */ | ||
| 349 | OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 350 | /* dispc2_de */ | ||
| 351 | OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 352 | /* dispc2_data8 */ | ||
| 353 | OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 354 | /* dispc2_data7 */ | ||
| 355 | OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 356 | /* dispc2_data6 */ | ||
| 357 | OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 358 | /* dispc2_data5 */ | ||
| 359 | OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 360 | /* dispc2_data4 */ | ||
| 361 | OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 362 | /* dispc2_data3 */ | ||
| 363 | OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 364 | /* dispc2_data2 */ | ||
| 365 | OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 366 | /* dispc2_data1 */ | ||
| 367 | OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 368 | /* dispc2_data0 */ | ||
| 369 | OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), | ||
| 370 | /* NIRQ2 for twl6040 */ | ||
| 371 | OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 | | ||
| 372 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), | ||
| 373 | /* GPIO_127 for twl6040 */ | ||
| 374 | OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), | ||
| 375 | /* McPDM */ | ||
| 376 | OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 377 | OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 378 | OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), | ||
| 379 | OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 380 | OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 381 | /* McBSP1 */ | ||
| 382 | OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 383 | OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | ||
| 384 | OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | | ||
| 385 | OMAP_PULL_ENA), | ||
| 386 | OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | ||
| 387 | |||
| 388 | /* UART2 - BT/FM/GPS shared transport */ | ||
| 389 | OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0), | ||
| 390 | OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), | ||
| 391 | OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0), | ||
| 392 | OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), | ||
| 393 | |||
| 394 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 395 | }; | ||
| 396 | |||
| 397 | #else | ||
| 398 | #define board_mux NULL | ||
| 399 | #endif | ||
| 400 | |||
| 401 | |||
| 402 | static void omap4_panda_init_rev(void) | ||
| 403 | { | ||
| 404 | if (cpu_is_omap443x()) { | ||
| 405 | /* PandaBoard 4430 */ | ||
| 406 | /* ASoC audio configuration */ | ||
| 407 | panda_abe_audio_data.card_name = "PandaBoard"; | ||
| 408 | panda_abe_audio_data.has_hsmic = 1; | ||
| 409 | } else { | ||
| 410 | /* PandaBoard ES */ | ||
| 411 | /* ASoC audio configuration */ | ||
| 412 | panda_abe_audio_data.card_name = "PandaBoardES"; | ||
| 413 | } | ||
| 414 | } | ||
| 415 | |||
| 416 | static void __init omap4_panda_init(void) | ||
| 417 | { | ||
| 418 | int package = OMAP_PACKAGE_CBS; | ||
| 419 | int ret; | ||
| 420 | |||
| 421 | if (omap_rev() == OMAP4430_REV_ES1_0) | ||
| 422 | package = OMAP_PACKAGE_CBL; | ||
| 423 | omap4_mux_init(board_mux, NULL, package); | ||
| 424 | |||
| 425 | omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ); | ||
| 426 | ret = wl12xx_set_platform_data(&omap_panda_wlan_data); | ||
| 427 | if (ret) | ||
| 428 | pr_err("error setting wl12xx data: %d\n", ret); | ||
| 429 | |||
| 430 | omap4_panda_init_rev(); | ||
| 431 | omap4_panda_i2c_init(); | ||
| 432 | platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); | ||
| 433 | platform_device_register(&omap_vwlan_device); | ||
| 434 | omap_serial_init(); | ||
| 435 | omap_sdrc_init(NULL, NULL); | ||
| 436 | omap4_twl6030_hsmmc_init(mmc); | ||
| 437 | omap4_ehci_init(); | ||
| 438 | usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto"); | ||
| 439 | usb_musb_init(&musb_board_data); | ||
| 440 | omap4_panda_display_init(); | ||
| 441 | } | ||
| 442 | |||
| 443 | MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") | ||
| 444 | /* Maintainer: David Anders - Texas Instruments Inc */ | ||
| 445 | .atag_offset = 0x100, | ||
| 446 | .smp = smp_ops(omap4_smp_ops), | ||
| 447 | .reserve = omap_reserve, | ||
| 448 | .map_io = omap4_map_io, | ||
| 449 | .init_early = omap4430_init_early, | ||
| 450 | .init_irq = gic_init_irq, | ||
| 451 | .init_machine = omap4_panda_init, | ||
| 452 | .init_late = omap4430_init_late, | ||
| 453 | .init_time = omap4_local_timer_init, | ||
| 454 | .restart = omap44xx_restart, | ||
| 455 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 4269fc145698..721da484d8ec 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -15,12 +15,12 @@ | |||
| 15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
| 16 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
| 17 | #include <linux/err.h> | 17 | #include <linux/err.h> |
| 18 | #include <linux/gpio.h> | ||
| 18 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
| 19 | #include <linux/of.h> | 20 | #include <linux/of.h> |
| 20 | #include <linux/pinctrl/machine.h> | 21 | #include <linux/pinctrl/machine.h> |
| 21 | #include <linux/platform_data/omap4-keypad.h> | 22 | #include <linux/platform_data/omap4-keypad.h> |
| 22 | #include <linux/platform_data/omap_ocp2scp.h> | 23 | #include <linux/wl12xx.h> |
| 23 | #include <linux/usb/omap_control_usb.h> | ||
| 24 | 24 | ||
| 25 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| @@ -253,49 +253,6 @@ static inline void omap_init_camera(void) | |||
| 253 | #endif | 253 | #endif |
| 254 | } | 254 | } |
| 255 | 255 | ||
| 256 | #if IS_ENABLED(CONFIG_OMAP_CONTROL_USB) | ||
| 257 | static struct omap_control_usb_platform_data omap4_control_usb_pdata = { | ||
| 258 | .type = 1, | ||
| 259 | }; | ||
| 260 | |||
| 261 | struct resource omap4_control_usb_res[] = { | ||
| 262 | { | ||
| 263 | .name = "control_dev_conf", | ||
| 264 | .start = 0x4a002300, | ||
| 265 | .end = 0x4a002303, | ||
| 266 | .flags = IORESOURCE_MEM, | ||
| 267 | }, | ||
| 268 | { | ||
| 269 | .name = "otghs_control", | ||
| 270 | .start = 0x4a00233c, | ||
| 271 | .end = 0x4a00233f, | ||
| 272 | .flags = IORESOURCE_MEM, | ||
| 273 | }, | ||
| 274 | }; | ||
| 275 | |||
| 276 | static struct platform_device omap4_control_usb = { | ||
| 277 | .name = "omap-control-usb", | ||
| 278 | .id = -1, | ||
| 279 | .dev = { | ||
| 280 | .platform_data = &omap4_control_usb_pdata, | ||
| 281 | }, | ||
| 282 | .num_resources = 2, | ||
| 283 | .resource = omap4_control_usb_res, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static inline void __init omap_init_control_usb(void) | ||
| 287 | { | ||
| 288 | if (!cpu_is_omap44xx()) | ||
| 289 | return; | ||
| 290 | |||
| 291 | if (platform_device_register(&omap4_control_usb)) | ||
| 292 | pr_err("Error registering omap_control_usb device\n"); | ||
| 293 | } | ||
| 294 | |||
| 295 | #else | ||
| 296 | static inline void omap_init_control_usb(void) { } | ||
| 297 | #endif /* CONFIG_OMAP_CONTROL_USB */ | ||
| 298 | |||
| 299 | int __init omap4_keyboard_init(struct omap4_keypad_platform_data | 256 | int __init omap4_keyboard_init(struct omap4_keypad_platform_data |
| 300 | *sdp4430_keypad_data, struct omap_board_data *bdata) | 257 | *sdp4430_keypad_data, struct omap_board_data *bdata) |
| 301 | { | 258 | { |
| @@ -557,80 +514,38 @@ static void omap_init_vout(void) | |||
| 557 | static inline void omap_init_vout(void) {} | 514 | static inline void omap_init_vout(void) {} |
| 558 | #endif | 515 | #endif |
| 559 | 516 | ||
| 560 | #if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE) | 517 | #if IS_ENABLED(CONFIG_WL12XX) |
| 561 | static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev) | ||
| 562 | { | ||
| 563 | int cnt = 0; | ||
| 564 | 518 | ||
| 565 | while (ocp2scp_dev->drv_name != NULL) { | 519 | static struct wl12xx_platform_data wl12xx __initdata; |
| 566 | cnt++; | ||
| 567 | ocp2scp_dev++; | ||
| 568 | } | ||
| 569 | 520 | ||
| 570 | return cnt; | 521 | void __init omap_init_wl12xx_of(void) |
| 571 | } | ||
| 572 | |||
| 573 | static void __init omap_init_ocp2scp(void) | ||
| 574 | { | 522 | { |
| 575 | struct omap_hwmod *oh; | 523 | int ret; |
| 576 | struct platform_device *pdev; | ||
| 577 | int bus_id = -1, dev_cnt = 0, i; | ||
| 578 | struct omap_ocp2scp_dev *ocp2scp_dev; | ||
| 579 | const char *oh_name, *name; | ||
| 580 | struct omap_ocp2scp_platform_data *pdata; | ||
| 581 | |||
| 582 | if (!cpu_is_omap44xx()) | ||
| 583 | return; | ||
| 584 | |||
| 585 | oh_name = "ocp2scp_usb_phy"; | ||
| 586 | name = "omap-ocp2scp"; | ||
| 587 | 524 | ||
| 588 | oh = omap_hwmod_lookup(oh_name); | 525 | if (!of_have_populated_dt()) |
| 589 | if (!oh) { | ||
| 590 | pr_err("%s: could not find omap_hwmod for %s\n", __func__, | ||
| 591 | oh_name); | ||
| 592 | return; | ||
| 593 | } | ||
| 594 | |||
| 595 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | ||
| 596 | if (!pdata) { | ||
| 597 | pr_err("%s: No memory for ocp2scp pdata\n", __func__); | ||
| 598 | return; | ||
| 599 | } | ||
| 600 | |||
| 601 | ocp2scp_dev = oh->dev_attr; | ||
| 602 | dev_cnt = count_ocp2scp_devices(ocp2scp_dev); | ||
| 603 | |||
| 604 | if (!dev_cnt) { | ||
| 605 | pr_err("%s: No devices connected to ocp2scp\n", __func__); | ||
| 606 | kfree(pdata); | ||
| 607 | return; | 526 | return; |
| 608 | } | ||
| 609 | 527 | ||
| 610 | pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *) | 528 | if (of_machine_is_compatible("ti,omap4-sdp")) { |
| 611 | * dev_cnt, GFP_KERNEL); | 529 | wl12xx.board_ref_clock = WL12XX_REFCLOCK_26; |
| 612 | if (!pdata->devices) { | 530 | wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26; |
| 613 | pr_err("%s: No memory for ocp2scp pdata devices\n", __func__); | 531 | wl12xx.irq = gpio_to_irq(53); |
| 614 | kfree(pdata); | 532 | } else if (of_machine_is_compatible("ti,omap4-panda")) { |
| 533 | wl12xx.board_ref_clock = WL12XX_REFCLOCK_38; | ||
| 534 | wl12xx.irq = gpio_to_irq(53); | ||
| 535 | } else { | ||
| 615 | return; | 536 | return; |
| 616 | } | 537 | } |
| 617 | 538 | ||
| 618 | for (i = 0; i < dev_cnt; i++, ocp2scp_dev++) | 539 | ret = wl12xx_set_platform_data(&wl12xx); |
| 619 | pdata->devices[i] = ocp2scp_dev; | 540 | if (ret) { |
| 620 | 541 | pr_err("error setting wl12xx data: %d\n", ret); | |
| 621 | pdata->dev_cnt = dev_cnt; | ||
| 622 | |||
| 623 | pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata)); | ||
| 624 | if (IS_ERR(pdev)) { | ||
| 625 | pr_err("Could not build omap_device for %s %s\n", | ||
| 626 | name, oh_name); | ||
| 627 | kfree(pdata->devices); | ||
| 628 | kfree(pdata); | ||
| 629 | return; | 542 | return; |
| 630 | } | 543 | } |
| 631 | } | 544 | } |
| 632 | #else | 545 | #else |
| 633 | static inline void omap_init_ocp2scp(void) { } | 546 | static inline void omap_init_wl12xx_of(void) |
| 547 | { | ||
| 548 | } | ||
| 634 | #endif | 549 | #endif |
| 635 | 550 | ||
| 636 | /*-------------------------------------------------------------------------*/ | 551 | /*-------------------------------------------------------------------------*/ |
| @@ -651,17 +566,18 @@ static int __init omap2_init_devices(void) | |||
| 651 | omap_init_mbox(); | 566 | omap_init_mbox(); |
| 652 | /* If dtb is there, the devices will be created dynamically */ | 567 | /* If dtb is there, the devices will be created dynamically */ |
| 653 | if (!of_have_populated_dt()) { | 568 | if (!of_have_populated_dt()) { |
| 654 | omap_init_control_usb(); | ||
| 655 | omap_init_dmic(); | 569 | omap_init_dmic(); |
| 656 | omap_init_mcpdm(); | 570 | omap_init_mcpdm(); |
| 657 | omap_init_mcspi(); | 571 | omap_init_mcspi(); |
| 658 | omap_init_sham(); | 572 | omap_init_sham(); |
| 659 | omap_init_aes(); | 573 | omap_init_aes(); |
| 574 | } else { | ||
| 575 | /* These can be removed when bindings are done */ | ||
| 576 | omap_init_wl12xx_of(); | ||
| 660 | } | 577 | } |
| 661 | omap_init_sti(); | 578 | omap_init_sti(); |
| 662 | omap_init_rng(); | 579 | omap_init_rng(); |
| 663 | omap_init_vout(); | 580 | omap_init_vout(); |
| 664 | omap_init_ocp2scp(); | ||
| 665 | 581 | ||
| 666 | return 0; | 582 | return 0; |
| 667 | } | 583 | } |
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 2ef1f8714fcf..07d4c7b35754 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c | |||
| @@ -29,7 +29,6 @@ | |||
| 29 | 29 | ||
| 30 | static u16 control_pbias_offset; | 30 | static u16 control_pbias_offset; |
| 31 | static u16 control_devconf1_offset; | 31 | static u16 control_devconf1_offset; |
| 32 | static u16 control_mmc1; | ||
| 33 | 32 | ||
| 34 | #define HSMMC_NAME_LEN 9 | 33 | #define HSMMC_NAME_LEN 9 |
| 35 | 34 | ||
| @@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, | |||
| 121 | } | 120 | } |
| 122 | } | 121 | } |
| 123 | 122 | ||
| 124 | static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, | ||
| 125 | int power_on, int vdd) | ||
| 126 | { | ||
| 127 | u32 reg; | ||
| 128 | |||
| 129 | /* | ||
| 130 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | ||
| 131 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both | ||
| 132 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | ||
| 133 | */ | ||
| 134 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | ||
| 135 | reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | ||
| 136 | OMAP4_MMC1_PWRDNZ_MASK | | ||
| 137 | OMAP4_MMC1_PBIASLITE_VMODE_MASK); | ||
| 138 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
| 139 | } | ||
| 140 | |||
| 141 | static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, | ||
| 142 | int power_on, int vdd) | ||
| 143 | { | ||
| 144 | u32 reg; | ||
| 145 | unsigned long timeout; | ||
| 146 | |||
| 147 | if (power_on) { | ||
| 148 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | ||
| 149 | reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; | ||
| 150 | if ((1 << vdd) <= MMC_VDD_165_195) | ||
| 151 | reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; | ||
| 152 | else | ||
| 153 | reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; | ||
| 154 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | ||
| 155 | OMAP4_MMC1_PWRDNZ_MASK); | ||
| 156 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
| 157 | |||
| 158 | timeout = jiffies + msecs_to_jiffies(5); | ||
| 159 | do { | ||
| 160 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | ||
| 161 | if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) | ||
| 162 | break; | ||
| 163 | usleep_range(100, 200); | ||
| 164 | } while (!time_after(jiffies, timeout)); | ||
| 165 | |||
| 166 | if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { | ||
| 167 | pr_err("Pbias Voltage is not same as LDO\n"); | ||
| 168 | /* Caution : On VMODE_ERROR Power Down MMC IO */ | ||
| 169 | reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); | ||
| 170 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
| 171 | } | ||
| 172 | } | ||
| 173 | } | ||
| 174 | |||
| 175 | static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) | 123 | static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) |
| 176 | { | 124 | { |
| 177 | u32 reg; | 125 | u32 reg; |
| @@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |||
| 317 | mmc->slots[0].pm_caps = c->pm_caps; | 265 | mmc->slots[0].pm_caps = c->pm_caps; |
| 318 | mmc->slots[0].internal_clock = !c->ext_clock; | 266 | mmc->slots[0].internal_clock = !c->ext_clock; |
| 319 | mmc->max_freq = c->max_freq; | 267 | mmc->max_freq = c->max_freq; |
| 320 | if (cpu_is_omap44xx()) | 268 | mmc->reg_offset = 0; |
| 321 | mmc->reg_offset = OMAP4_MMC_REG_OFFSET; | ||
| 322 | else | ||
| 323 | mmc->reg_offset = 0; | ||
| 324 | |||
| 325 | mmc->get_context_loss_count = hsmmc_get_context_loss; | 269 | mmc->get_context_loss_count = hsmmc_get_context_loss; |
| 326 | 270 | ||
| 327 | mmc->slots[0].switch_pin = c->gpio_cd; | 271 | mmc->slots[0].switch_pin = c->gpio_cd; |
| @@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |||
| 368 | if (!soc_is_am35xx()) | 312 | if (!soc_is_am35xx()) |
| 369 | mmc->slots[0].features |= HSMMC_HAS_PBIAS; | 313 | mmc->slots[0].features |= HSMMC_HAS_PBIAS; |
| 370 | 314 | ||
| 371 | if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) | ||
| 372 | mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | ||
| 373 | |||
| 374 | switch (c->mmc) { | 315 | switch (c->mmc) { |
| 375 | case 1: | 316 | case 1: |
| 376 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { | 317 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { |
| 377 | /* on-chip level shifting via PBIAS0/PBIAS1 */ | 318 | /* on-chip level shifting via PBIAS0/PBIAS1 */ |
| 378 | if (cpu_is_omap44xx()) { | 319 | mmc->slots[0].before_set_reg = |
| 379 | mmc->slots[0].before_set_reg = | 320 | omap_hsmmc1_before_set_reg; |
| 380 | omap4_hsmmc1_before_set_reg; | 321 | mmc->slots[0].after_set_reg = |
| 381 | mmc->slots[0].after_set_reg = | 322 | omap_hsmmc1_after_set_reg; |
| 382 | omap4_hsmmc1_after_set_reg; | ||
| 383 | } else { | ||
| 384 | mmc->slots[0].before_set_reg = | ||
| 385 | omap_hsmmc1_before_set_reg; | ||
| 386 | mmc->slots[0].after_set_reg = | ||
| 387 | omap_hsmmc1_after_set_reg; | ||
| 388 | } | ||
| 389 | } | 323 | } |
| 390 | 324 | ||
| 391 | if (soc_is_am35xx()) | 325 | if (soc_is_am35xx()) |
| @@ -563,34 +497,17 @@ free_mmc: | |||
| 563 | 497 | ||
| 564 | void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) | 498 | void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) |
| 565 | { | 499 | { |
| 566 | u32 reg; | ||
| 567 | |||
| 568 | if (omap_hsmmc_done) | 500 | if (omap_hsmmc_done) |
| 569 | return; | 501 | return; |
| 570 | 502 | ||
| 571 | omap_hsmmc_done = 1; | 503 | omap_hsmmc_done = 1; |
| 572 | 504 | ||
| 573 | if (!cpu_is_omap44xx()) { | 505 | if (cpu_is_omap2430()) { |
| 574 | if (cpu_is_omap2430()) { | 506 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; |
| 575 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | 507 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; |
| 576 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | ||
| 577 | } else { | ||
| 578 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | ||
| 579 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | ||
| 580 | } | ||
| 581 | } else { | 508 | } else { |
| 582 | control_pbias_offset = | 509 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; |
| 583 | OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; | 510 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; |
| 584 | control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; | ||
| 585 | reg = omap4_ctrl_pad_readl(control_mmc1); | ||
| 586 | reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | | ||
| 587 | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); | ||
| 588 | reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | | ||
| 589 | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); | ||
| 590 | reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | | ||
| 591 | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | | ||
| 592 | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); | ||
| 593 | omap4_ctrl_pad_writel(reg, control_mmc1); | ||
| 594 | } | 511 | } |
| 595 | 512 | ||
| 596 | for (; controllers->mmc; controllers++) | 513 | for (; controllers->mmc; controllers++) |
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index fdb22f14021f..5d2080ef7923 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h | |||
| @@ -10,7 +10,6 @@ | |||
| 10 | #include "mux2420.h" | 10 | #include "mux2420.h" |
| 11 | #include "mux2430.h" | 11 | #include "mux2430.h" |
| 12 | #include "mux34xx.h" | 12 | #include "mux34xx.h" |
| 13 | #include "mux44xx.h" | ||
| 14 | 13 | ||
| 15 | #define OMAP_MUX_TERMINATOR 0xffff | 14 | #define OMAP_MUX_TERMINATOR 0xffff |
| 16 | 15 | ||
| @@ -64,8 +63,6 @@ | |||
| 64 | 63 | ||
| 65 | /* Flags for omapX_mux_init */ | 64 | /* Flags for omapX_mux_init */ |
| 66 | #define OMAP_PACKAGE_MASK 0xffff | 65 | #define OMAP_PACKAGE_MASK 0xffff |
| 67 | #define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */ | ||
| 68 | #define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */ | ||
| 69 | #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ | 66 | #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ |
| 70 | #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ | 67 | #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ |
| 71 | #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ | 68 | #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ |
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c deleted file mode 100644 index f5a74daab2ff..000000000000 --- a/arch/arm/mach-omap2/mux44xx.c +++ /dev/null | |||
| @@ -1,1356 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx ES1.0 pin mux definition | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * | ||
| 8 | * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com> | ||
| 9 | * | ||
| 10 | * This file is automatically generated from the OMAP hardware databases. | ||
| 11 | * We respectfully ask that any modifications to this file be coordinated | ||
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 13 | * authors above to ensure that the autogeneration scripts are kept | ||
| 14 | * up-to-date with the file contents. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | |||
| 23 | #include "mux.h" | ||
| 24 | |||
| 25 | #ifdef CONFIG_OMAP_MUX | ||
| 26 | |||
| 27 | #define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 28 | { \ | ||
| 29 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 30 | .gpio = (g), \ | ||
| 31 | .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ | ||
| 32 | } | ||
| 33 | |||
| 34 | #else | ||
| 35 | |||
| 36 | #define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 37 | { \ | ||
| 38 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 39 | .gpio = (g), \ | ||
| 40 | } | ||
| 41 | |||
| 42 | #endif | ||
| 43 | |||
| 44 | #define _OMAP4_BALLENTRY(M0, bb, bt) \ | ||
| 45 | { \ | ||
| 46 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 47 | .balls = { bb, bt }, \ | ||
| 48 | } | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Superset of all mux modes for omap4 ES1.0 | ||
| 52 | */ | ||
| 53 | static struct omap_mux __initdata omap4_core_muxmodes[] = { | ||
| 54 | _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, | ||
| 55 | NULL, NULL, NULL, NULL), | ||
| 56 | _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, | ||
| 57 | NULL, NULL, NULL, NULL), | ||
| 58 | _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, | ||
| 59 | NULL, NULL, NULL, NULL), | ||
| 60 | _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, | ||
| 61 | NULL, NULL, NULL, NULL), | ||
| 62 | _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", | ||
| 63 | "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), | ||
| 64 | _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", | ||
| 65 | "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), | ||
| 66 | _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", | ||
| 67 | "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), | ||
| 68 | _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", | ||
| 69 | "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), | ||
| 70 | _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", | ||
| 71 | "gpio_32", NULL, NULL, NULL, NULL), | ||
| 72 | _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", | ||
| 73 | "gpio_33", NULL, NULL, NULL, NULL), | ||
| 74 | _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", | ||
| 75 | "gpio_34", NULL, NULL, NULL, NULL), | ||
| 76 | _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", | ||
| 77 | "gpio_35", NULL, NULL, NULL, NULL), | ||
| 78 | _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", | ||
| 79 | "gpio_36", NULL, NULL, NULL, NULL), | ||
| 80 | _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", | ||
| 81 | "gpio_37", NULL, NULL, NULL, NULL), | ||
| 82 | _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", | ||
| 83 | "gpio_38", NULL, NULL, NULL, NULL), | ||
| 84 | _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", | ||
| 85 | "gpio_39", NULL, NULL, NULL, NULL), | ||
| 86 | _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", | ||
| 87 | "gpio_40", "venc_656_data0", NULL, NULL, NULL), | ||
| 88 | _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", | ||
| 89 | "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), | ||
| 90 | _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", | ||
| 91 | "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), | ||
| 92 | _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", | ||
| 93 | "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), | ||
| 94 | _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", | ||
| 95 | "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), | ||
| 96 | _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", | ||
| 97 | "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), | ||
| 98 | _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", | ||
| 99 | "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), | ||
| 100 | _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", | ||
| 101 | "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), | ||
| 102 | _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0", | ||
| 103 | "gpio_48", NULL, NULL, NULL, "safe_mode"), | ||
| 104 | _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", | ||
| 105 | "gpio_49", NULL, NULL, NULL, "safe_mode"), | ||
| 106 | _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", | ||
| 107 | "sys_ndmareq0", NULL, NULL, NULL), | ||
| 108 | _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", | ||
| 109 | "gpio_51", NULL, NULL, NULL, "safe_mode"), | ||
| 110 | _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7", | ||
| 111 | "gpio_52", NULL, NULL, NULL, "safe_mode"), | ||
| 112 | _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", | ||
| 113 | "c2c_dataout4", "gpio_53", NULL, NULL, NULL, | ||
| 114 | "safe_mode"), | ||
| 115 | _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", | ||
| 116 | "sys_ndmareq1", NULL, NULL, NULL), | ||
| 117 | _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", | ||
| 118 | "sys_ndmareq2", NULL, NULL, NULL), | ||
| 119 | _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, | ||
| 120 | "gpio_56", "sys_ndmareq3", NULL, NULL, NULL), | ||
| 121 | _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, | ||
| 122 | NULL, NULL, NULL, NULL), | ||
| 123 | _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, | ||
| 124 | NULL, NULL, NULL, NULL), | ||
| 125 | _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, | ||
| 126 | "gpio_59", NULL, NULL, NULL, NULL), | ||
| 127 | _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", | ||
| 128 | "gpio_60", NULL, NULL, NULL, "safe_mode"), | ||
| 129 | _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, | ||
| 130 | "gpio_61", NULL, NULL, NULL, NULL), | ||
| 131 | _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", | ||
| 132 | "gpio_62", NULL, NULL, NULL, "safe_mode"), | ||
| 133 | _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen", | ||
| 134 | "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, | ||
| 135 | NULL, "safe_mode"), | ||
| 136 | _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0", | ||
| 137 | "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, | ||
| 138 | "safe_mode"), | ||
| 139 | _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1", | ||
| 140 | "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, | ||
| 141 | "safe_mode"), | ||
| 142 | _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0", | ||
| 143 | "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, | ||
| 144 | NULL, "safe_mode"), | ||
| 145 | _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1", | ||
| 146 | "c2c_dataout1", "gpio_104", NULL, NULL, NULL, | ||
| 147 | "safe_mode"), | ||
| 148 | _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, | ||
| 149 | NULL, NULL, "safe_mode"), | ||
| 150 | _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, | ||
| 151 | NULL, NULL, "safe_mode"), | ||
| 152 | _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, | ||
| 153 | "gpio_65", NULL, NULL, NULL, "safe_mode"), | ||
| 154 | _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, | ||
| 155 | "gpio_66", NULL, NULL, NULL, "safe_mode"), | ||
| 156 | _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, | ||
| 157 | NULL, NULL, "safe_mode"), | ||
| 158 | _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, | ||
| 159 | NULL, NULL, "safe_mode"), | ||
| 160 | _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, | ||
| 161 | NULL, NULL, "safe_mode"), | ||
| 162 | _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, | ||
| 163 | NULL, NULL, "safe_mode"), | ||
| 164 | _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, | ||
| 165 | NULL, NULL, "safe_mode"), | ||
| 166 | _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, | ||
| 167 | NULL, NULL, "safe_mode"), | ||
| 168 | _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, | ||
| 169 | NULL, NULL, "safe_mode"), | ||
| 170 | _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, | ||
| 171 | NULL, NULL, "safe_mode"), | ||
| 172 | _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, | ||
| 173 | NULL, NULL, "safe_mode"), | ||
| 174 | _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, | ||
| 175 | NULL, NULL, "safe_mode"), | ||
| 176 | _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, | ||
| 177 | NULL, NULL, "safe_mode"), | ||
| 178 | _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, | ||
| 179 | NULL, NULL, "safe_mode"), | ||
| 180 | _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, | ||
| 181 | NULL, NULL, "safe_mode"), | ||
| 182 | _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, | ||
| 183 | NULL, NULL, "safe_mode"), | ||
| 184 | _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", | ||
| 185 | NULL, NULL, NULL, "safe_mode"), | ||
| 186 | _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", | ||
| 187 | NULL, NULL, NULL, "safe_mode"), | ||
| 188 | _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, | ||
| 189 | "gpio_83", NULL, NULL, NULL, "safe_mode"), | ||
| 190 | _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", | ||
| 191 | "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", | ||
| 192 | NULL, "hw_dbg20", "safe_mode"), | ||
| 193 | _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", | ||
| 194 | "hsi1_cadata", "mcbsp4_clkr", "gpio_85", | ||
| 195 | "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", | ||
| 196 | "safe_mode"), | ||
| 197 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", | ||
| 198 | "hsi1_caflag", "mcbsp4_fsr", "gpio_86", | ||
| 199 | "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), | ||
| 200 | _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", | ||
| 201 | "hsi1_acready", "mcbsp4_fsx", "gpio_87", | ||
| 202 | "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", | ||
| 203 | "safe_mode"), | ||
| 204 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", | ||
| 205 | "hsi1_acwake", "mcbsp4_clkx", "gpio_88", | ||
| 206 | "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24", | ||
| 207 | "safe_mode"), | ||
| 208 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", | ||
| 209 | "hsi1_acdata", "mcbsp4_dx", "gpio_89", | ||
| 210 | "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25", | ||
| 211 | "safe_mode"), | ||
| 212 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", | ||
| 213 | "hsi1_acflag", "mcbsp4_dr", "gpio_90", | ||
| 214 | "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26", | ||
| 215 | "safe_mode"), | ||
| 216 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", | ||
| 217 | "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", | ||
| 218 | "usbb1_mm_txen", "hw_dbg27", "safe_mode"), | ||
| 219 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", | ||
| 220 | "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", | ||
| 221 | "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), | ||
| 222 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", | ||
| 223 | "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", | ||
| 224 | "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), | ||
| 225 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", | ||
| 226 | "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", | ||
| 227 | "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", | ||
| 228 | "safe_mode"), | ||
| 229 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", | ||
| 230 | "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", | ||
| 231 | "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", | ||
| 232 | "safe_mode"), | ||
| 233 | _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, | ||
| 234 | "gpio_96", NULL, NULL, NULL, "safe_mode"), | ||
| 235 | _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, | ||
| 236 | NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), | ||
| 237 | _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, | ||
| 238 | "gpio_98", NULL, NULL, NULL, "safe_mode"), | ||
| 239 | _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, | ||
| 240 | "gpio_99", NULL, NULL, NULL, "safe_mode"), | ||
| 241 | _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", | ||
| 242 | "gpio_100", NULL, NULL, NULL, "safe_mode"), | ||
| 243 | _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", | ||
| 244 | "gpio_101", NULL, NULL, NULL, "safe_mode"), | ||
| 245 | _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", | ||
| 246 | "gpio_102", NULL, NULL, NULL, "safe_mode"), | ||
| 247 | _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", | ||
| 248 | "gpio_103", NULL, NULL, NULL, "safe_mode"), | ||
| 249 | _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", | ||
| 250 | "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), | ||
| 251 | _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", | ||
| 252 | "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), | ||
| 253 | _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, | ||
| 254 | "gpio_106", NULL, NULL, NULL, "safe_mode"), | ||
| 255 | _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, | ||
| 256 | "gpio_107", NULL, NULL, NULL, "safe_mode"), | ||
| 257 | _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, | ||
| 258 | "gpio_108", NULL, NULL, NULL, "safe_mode"), | ||
| 259 | _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, | ||
| 260 | "gpio_109", NULL, NULL, NULL, "safe_mode"), | ||
| 261 | _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", | ||
| 262 | "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", | ||
| 263 | NULL, NULL, "safe_mode"), | ||
| 264 | _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", | ||
| 265 | "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, | ||
| 266 | NULL, "safe_mode"), | ||
| 267 | _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", | ||
| 268 | "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, | ||
| 269 | NULL, "safe_mode"), | ||
| 270 | _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", | ||
| 271 | "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, | ||
| 272 | NULL, "safe_mode"), | ||
| 273 | _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", | ||
| 274 | "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, | ||
| 275 | NULL, "safe_mode"), | ||
| 276 | _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", | ||
| 277 | "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, | ||
| 278 | NULL, "safe_mode"), | ||
| 279 | _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", | ||
| 280 | "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, | ||
| 281 | "safe_mode"), | ||
| 282 | _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", | ||
| 283 | "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, | ||
| 284 | "safe_mode"), | ||
| 285 | _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", | ||
| 286 | "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, | ||
| 287 | "safe_mode"), | ||
| 288 | _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", | ||
| 289 | "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, | ||
| 290 | "safe_mode"), | ||
| 291 | _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", | ||
| 292 | NULL, NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 293 | _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", | ||
| 294 | NULL, NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 295 | _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", | ||
| 296 | NULL, NULL, NULL, "safe_mode"), | ||
| 297 | _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, | ||
| 298 | "gpio_119", "usbb2_mm_txse0", NULL, NULL, | ||
| 299 | "safe_mode"), | ||
| 300 | _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, | ||
| 301 | "gpio_120", "usbb2_mm_txdat", NULL, NULL, | ||
| 302 | "safe_mode"), | ||
| 303 | _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", | ||
| 304 | NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"), | ||
| 305 | _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", | ||
| 306 | "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL, | ||
| 307 | "safe_mode"), | ||
| 308 | _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, | ||
| 309 | "gpio_123", NULL, NULL, NULL, "safe_mode"), | ||
| 310 | _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, | ||
| 311 | "gpio_124", NULL, NULL, NULL, "safe_mode"), | ||
| 312 | _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, | ||
| 313 | "gpio_125", NULL, NULL, NULL, "safe_mode"), | ||
| 314 | _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, | ||
| 315 | "gpio_126", NULL, NULL, NULL, "safe_mode"), | ||
| 316 | _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", | ||
| 317 | "gpio_127", NULL, NULL, NULL, "safe_mode"), | ||
| 318 | _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, | ||
| 319 | NULL, NULL), | ||
| 320 | _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, | ||
| 321 | NULL, NULL), | ||
| 322 | _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, | ||
| 323 | "gpio_128", NULL, NULL, NULL, "safe_mode"), | ||
| 324 | _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, | ||
| 325 | "gpio_129", NULL, NULL, NULL, "safe_mode"), | ||
| 326 | _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", | ||
| 327 | NULL, NULL, NULL, "safe_mode"), | ||
| 328 | _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", | ||
| 329 | NULL, NULL, NULL, "safe_mode"), | ||
| 330 | _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", | ||
| 331 | NULL, NULL, NULL, "safe_mode"), | ||
| 332 | _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", | ||
| 333 | NULL, NULL, NULL, "safe_mode"), | ||
| 334 | _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", | ||
| 335 | NULL, NULL, NULL, "safe_mode"), | ||
| 336 | _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, | ||
| 337 | "gpio_135", NULL, NULL, NULL, "safe_mode"), | ||
| 338 | _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, | ||
| 339 | "gpio_136", NULL, NULL, NULL, "safe_mode"), | ||
| 340 | _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", | ||
| 341 | NULL, NULL, NULL, "safe_mode"), | ||
| 342 | _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, | ||
| 343 | "gpio_138", NULL, NULL, NULL, "safe_mode"), | ||
| 344 | _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", | ||
| 345 | "slimbus2_clock", "gpio_139", NULL, NULL, NULL, | ||
| 346 | "safe_mode"), | ||
| 347 | _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", | ||
| 348 | "slimbus2_data", "gpio_140", NULL, NULL, NULL, | ||
| 349 | "safe_mode"), | ||
| 350 | _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", | ||
| 351 | NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), | ||
| 352 | _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, | ||
| 353 | "gpio_142", NULL, NULL, NULL, "safe_mode"), | ||
| 354 | _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", | ||
| 355 | "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, | ||
| 356 | NULL, "safe_mode"), | ||
| 357 | _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", | ||
| 358 | "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, | ||
| 359 | NULL, "safe_mode"), | ||
| 360 | _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", | ||
| 361 | "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL, | ||
| 362 | "safe_mode"), | ||
| 363 | _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", | ||
| 364 | "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL, | ||
| 365 | "safe_mode"), | ||
| 366 | _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", | ||
| 367 | "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL, | ||
| 368 | "safe_mode"), | ||
| 369 | _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, | ||
| 370 | "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL, | ||
| 371 | "safe_mode"), | ||
| 372 | _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, | ||
| 373 | "gpio_149", NULL, NULL, NULL, "safe_mode"), | ||
| 374 | _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, | ||
| 375 | "gpio_150", NULL, NULL, NULL, "safe_mode"), | ||
| 376 | _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL, | ||
| 377 | "gpio_151", NULL, NULL, NULL, "safe_mode"), | ||
| 378 | _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL, | ||
| 379 | "gpio_152", NULL, NULL, NULL, "safe_mode"), | ||
| 380 | _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL, | ||
| 381 | "gpio_153", NULL, NULL, NULL, "safe_mode"), | ||
| 382 | _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL, | ||
| 383 | "gpio_154", NULL, NULL, NULL, "safe_mode"), | ||
| 384 | _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL, | ||
| 385 | "gpio_155", NULL, NULL, NULL, "safe_mode"), | ||
| 386 | _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL, | ||
| 387 | "gpio_156", NULL, NULL, NULL, "safe_mode"), | ||
| 388 | _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", | ||
| 389 | "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", | ||
| 390 | "hsi2_cawake", NULL, NULL, "safe_mode"), | ||
| 391 | _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", | ||
| 392 | "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", | ||
| 393 | "hsi2_cadata", "dispc2_data23", NULL, "reserved"), | ||
| 394 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", | ||
| 395 | "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", | ||
| 396 | "hsi2_caflag", "dispc2_data22", NULL, "reserved"), | ||
| 397 | _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", | ||
| 398 | "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", | ||
| 399 | "hsi2_acready", "dispc2_data21", NULL, "reserved"), | ||
| 400 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", | ||
| 401 | "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", | ||
| 402 | "hsi2_acwake", "dispc2_data20", NULL, "reserved"), | ||
| 403 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", | ||
| 404 | "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", | ||
| 405 | "hsi2_acdata", "dispc2_data19", NULL, "reserved"), | ||
| 406 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", | ||
| 407 | "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", | ||
| 408 | "hsi2_acflag", "dispc2_data18", NULL, "reserved"), | ||
| 409 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", | ||
| 410 | "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", | ||
| 411 | "hsi2_caready", "dispc2_data15", NULL, "reserved"), | ||
| 412 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", | ||
| 413 | "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", | ||
| 414 | "mcspi3_somi", "dispc2_data14", NULL, "reserved"), | ||
| 415 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", | ||
| 416 | "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", | ||
| 417 | "mcspi3_cs0", "dispc2_data13", NULL, "reserved"), | ||
| 418 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", | ||
| 419 | "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", | ||
| 420 | "mcspi3_simo", "dispc2_data12", NULL, "reserved"), | ||
| 421 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", | ||
| 422 | "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", | ||
| 423 | "mcspi3_clk", "dispc2_data11", NULL, "reserved"), | ||
| 424 | _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, | ||
| 425 | "gpio_169", NULL, NULL, NULL, "safe_mode"), | ||
| 426 | _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, | ||
| 427 | NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), | ||
| 428 | _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL, | ||
| 429 | "gpio_171", NULL, NULL, NULL, "safe_mode"), | ||
| 430 | _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL, | ||
| 431 | "gpio_172", NULL, NULL, NULL, "safe_mode"), | ||
| 432 | _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL, | ||
| 433 | "gpio_173", NULL, NULL, NULL, "safe_mode"), | ||
| 434 | _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL, | ||
| 435 | "gpio_174", NULL, NULL, NULL, "safe_mode"), | ||
| 436 | _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL, | ||
| 437 | "gpio_0", NULL, NULL, NULL, "safe_mode"), | ||
| 438 | _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL, | ||
| 439 | "gpio_1", NULL, NULL, NULL, "safe_mode"), | ||
| 440 | _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL, | ||
| 441 | "gpi_175", NULL, NULL, NULL, "safe_mode"), | ||
| 442 | _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL, | ||
| 443 | "gpi_176", NULL, NULL, NULL, "safe_mode"), | ||
| 444 | _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL, | ||
| 445 | "gpi_177", NULL, NULL, NULL, "safe_mode"), | ||
| 446 | _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL, | ||
| 447 | "gpi_178", NULL, NULL, NULL, "safe_mode"), | ||
| 448 | _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL, | ||
| 449 | "gpi_2", NULL, NULL, NULL, "safe_mode"), | ||
| 450 | _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL, | ||
| 451 | "gpi_3", NULL, NULL, NULL, "safe_mode"), | ||
| 452 | _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, | ||
| 453 | NULL, NULL, NULL, NULL), | ||
| 454 | _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx", | ||
| 455 | "uart2_rx", "gpio_179", NULL, NULL, NULL, | ||
| 456 | "safe_mode"), | ||
| 457 | _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx", | ||
| 458 | "uart2_tx", "gpio_180", NULL, NULL, NULL, | ||
| 459 | "safe_mode"), | ||
| 460 | _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, | ||
| 461 | "gpio_181", NULL, NULL, NULL, "safe_mode"), | ||
| 462 | _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, | ||
| 463 | "gpio_182", NULL, NULL, NULL, "safe_mode"), | ||
| 464 | _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, | ||
| 465 | NULL, NULL, "safe_mode"), | ||
| 466 | _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", | ||
| 467 | NULL, NULL, NULL, "safe_mode"), | ||
| 468 | _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", | ||
| 469 | NULL, NULL, NULL, "safe_mode"), | ||
| 470 | _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", | ||
| 471 | NULL, NULL, NULL, "safe_mode"), | ||
| 472 | _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", | ||
| 473 | NULL, NULL, NULL, "safe_mode"), | ||
| 474 | _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", | ||
| 475 | NULL, NULL, NULL, "safe_mode"), | ||
| 476 | _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", | ||
| 477 | NULL, NULL, NULL, "safe_mode"), | ||
| 478 | _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", | ||
| 479 | NULL, NULL, NULL, "safe_mode"), | ||
| 480 | _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, | ||
| 481 | NULL, "hw_dbg0", "safe_mode"), | ||
| 482 | _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, | ||
| 483 | NULL, "hw_dbg1", "safe_mode"), | ||
| 484 | _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, | ||
| 485 | "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"), | ||
| 486 | _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, | ||
| 487 | "gpio_14", NULL, "dispc2_data10", "hw_dbg3", | ||
| 488 | "reserved"), | ||
| 489 | _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, | ||
| 490 | "gpio_15", NULL, "dispc2_data9", "hw_dbg4", | ||
| 491 | "reserved"), | ||
| 492 | _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, | ||
| 493 | "gpio_16", "rfbi_te_vsync0", "dispc2_data16", | ||
| 494 | "hw_dbg5", "reserved"), | ||
| 495 | _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", | ||
| 496 | "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", | ||
| 497 | "dispc2_data17", "hw_dbg6", "reserved"), | ||
| 498 | _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", | ||
| 499 | "uart3_rx_irrx", "gpio_18", "rfbi_cs0", | ||
| 500 | "dispc2_hsync", "hw_dbg7", "reserved"), | ||
| 501 | _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", | ||
| 502 | "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", | ||
| 503 | "hw_dbg8", "reserved"), | ||
| 504 | _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", | ||
| 505 | "uart3_cts_rctx", "gpio_20", "rfbi_we", | ||
| 506 | "dispc2_vsync", "hw_dbg9", "reserved"), | ||
| 507 | _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", | ||
| 508 | NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", | ||
| 509 | "reserved"), | ||
| 510 | _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", | ||
| 511 | NULL, "gpio_22", "rfbi_data8", "dispc2_data8", | ||
| 512 | "hw_dbg11", "reserved"), | ||
| 513 | _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", | ||
| 514 | NULL, "gpio_23", "rfbi_data7", "dispc2_data7", | ||
| 515 | "hw_dbg12", "reserved"), | ||
| 516 | _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", | ||
| 517 | NULL, "gpio_24", "rfbi_data6", "dispc2_data6", | ||
| 518 | "hw_dbg13", "reserved"), | ||
| 519 | _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", | ||
| 520 | "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", | ||
| 521 | "hw_dbg14", "reserved"), | ||
| 522 | _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", | ||
| 523 | NULL, "gpio_26", "rfbi_data4", "dispc2_data4", | ||
| 524 | "hw_dbg15", "reserved"), | ||
| 525 | _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", | ||
| 526 | "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", | ||
| 527 | "hw_dbg16", "reserved"), | ||
| 528 | _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", | ||
| 529 | "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", | ||
| 530 | "hw_dbg17", "reserved"), | ||
| 531 | _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", | ||
| 532 | "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", | ||
| 533 | "hw_dbg18", "reserved"), | ||
| 534 | _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", | ||
| 535 | "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", | ||
| 536 | "hw_dbg19", "reserved"), | ||
| 537 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 538 | }; | ||
| 539 | |||
| 540 | /* | ||
| 541 | * Balls for 44XX CBL package | ||
| 542 | * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), | ||
| 543 | * 0.40mm Ball Pitch (Bottom) | ||
| 544 | */ | ||
| 545 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
| 546 | && defined(CONFIG_OMAP_PACKAGE_CBL) | ||
| 547 | static struct omap_ball __initdata omap4_core_cbl_ball[] = { | ||
| 548 | _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), | ||
| 549 | _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), | ||
| 550 | _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), | ||
| 551 | _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), | ||
| 552 | _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), | ||
| 553 | _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), | ||
| 554 | _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), | ||
| 555 | _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), | ||
| 556 | _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), | ||
| 557 | _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), | ||
| 558 | _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), | ||
| 559 | _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), | ||
| 560 | _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), | ||
| 561 | _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), | ||
| 562 | _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), | ||
| 563 | _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), | ||
| 564 | _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), | ||
| 565 | _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), | ||
| 566 | _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), | ||
| 567 | _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), | ||
| 568 | _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), | ||
| 569 | _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), | ||
| 570 | _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), | ||
| 571 | _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), | ||
| 572 | _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), | ||
| 573 | _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), | ||
| 574 | _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), | ||
| 575 | _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), | ||
| 576 | _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), | ||
| 577 | _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), | ||
| 578 | _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), | ||
| 579 | _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), | ||
| 580 | _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), | ||
| 581 | _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), | ||
| 582 | _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), | ||
| 583 | _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), | ||
| 584 | _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), | ||
| 585 | _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), | ||
| 586 | _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), | ||
| 587 | _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL), | ||
| 588 | _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL), | ||
| 589 | _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL), | ||
| 590 | _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL), | ||
| 591 | _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL), | ||
| 592 | _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), | ||
| 593 | _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), | ||
| 594 | _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), | ||
| 595 | _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), | ||
| 596 | _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), | ||
| 597 | _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), | ||
| 598 | _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), | ||
| 599 | _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), | ||
| 600 | _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), | ||
| 601 | _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), | ||
| 602 | _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), | ||
| 603 | _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), | ||
| 604 | _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), | ||
| 605 | _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), | ||
| 606 | _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), | ||
| 607 | _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), | ||
| 608 | _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), | ||
| 609 | _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), | ||
| 610 | _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), | ||
| 611 | _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), | ||
| 612 | _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), | ||
| 613 | _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), | ||
| 614 | _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), | ||
| 615 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), | ||
| 616 | _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), | ||
| 617 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), | ||
| 618 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), | ||
| 619 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), | ||
| 620 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), | ||
| 621 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), | ||
| 622 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), | ||
| 623 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), | ||
| 624 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), | ||
| 625 | _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), | ||
| 626 | _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), | ||
| 627 | _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), | ||
| 628 | _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), | ||
| 629 | _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), | ||
| 630 | _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), | ||
| 631 | _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), | ||
| 632 | _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), | ||
| 633 | _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), | ||
| 634 | _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), | ||
| 635 | _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), | ||
| 636 | _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), | ||
| 637 | _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), | ||
| 638 | _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), | ||
| 639 | _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), | ||
| 640 | _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), | ||
| 641 | _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), | ||
| 642 | _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), | ||
| 643 | _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), | ||
| 644 | _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), | ||
| 645 | _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), | ||
| 646 | _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), | ||
| 647 | _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), | ||
| 648 | _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), | ||
| 649 | _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), | ||
| 650 | _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), | ||
| 651 | _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), | ||
| 652 | _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), | ||
| 653 | _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), | ||
| 654 | _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), | ||
| 655 | _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), | ||
| 656 | _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), | ||
| 657 | _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), | ||
| 658 | _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), | ||
| 659 | _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), | ||
| 660 | _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), | ||
| 661 | _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), | ||
| 662 | _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), | ||
| 663 | _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), | ||
| 664 | _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), | ||
| 665 | _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), | ||
| 666 | _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), | ||
| 667 | _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), | ||
| 668 | _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), | ||
| 669 | _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), | ||
| 670 | _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), | ||
| 671 | _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), | ||
| 672 | _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), | ||
| 673 | _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), | ||
| 674 | _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), | ||
| 675 | _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), | ||
| 676 | _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), | ||
| 677 | _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), | ||
| 678 | _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), | ||
| 679 | _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), | ||
| 680 | _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), | ||
| 681 | _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), | ||
| 682 | _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), | ||
| 683 | _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), | ||
| 684 | _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), | ||
| 685 | _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), | ||
| 686 | _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), | ||
| 687 | _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), | ||
| 688 | _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), | ||
| 689 | _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), | ||
| 690 | _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), | ||
| 691 | _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), | ||
| 692 | _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), | ||
| 693 | _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), | ||
| 694 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), | ||
| 695 | _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), | ||
| 696 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), | ||
| 697 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), | ||
| 698 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), | ||
| 699 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), | ||
| 700 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), | ||
| 701 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), | ||
| 702 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), | ||
| 703 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), | ||
| 704 | _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), | ||
| 705 | _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), | ||
| 706 | _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL), | ||
| 707 | _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL), | ||
| 708 | _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL), | ||
| 709 | _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL), | ||
| 710 | _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL), | ||
| 711 | _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL), | ||
| 712 | _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL), | ||
| 713 | _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL), | ||
| 714 | _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL), | ||
| 715 | _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL), | ||
| 716 | _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL), | ||
| 717 | _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL), | ||
| 718 | _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), | ||
| 719 | _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), | ||
| 720 | _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), | ||
| 721 | _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), | ||
| 722 | _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), | ||
| 723 | _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), | ||
| 724 | _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), | ||
| 725 | _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), | ||
| 726 | _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), | ||
| 727 | _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), | ||
| 728 | _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), | ||
| 729 | _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), | ||
| 730 | _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), | ||
| 731 | _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), | ||
| 732 | _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), | ||
| 733 | _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), | ||
| 734 | _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), | ||
| 735 | _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), | ||
| 736 | _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), | ||
| 737 | _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), | ||
| 738 | _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), | ||
| 739 | _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), | ||
| 740 | _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), | ||
| 741 | _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), | ||
| 742 | _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), | ||
| 743 | _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), | ||
| 744 | _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), | ||
| 745 | _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), | ||
| 746 | _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), | ||
| 747 | _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), | ||
| 748 | _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), | ||
| 749 | _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), | ||
| 750 | _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), | ||
| 751 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 752 | }; | ||
| 753 | #else | ||
| 754 | #define omap4_core_cbl_ball NULL | ||
| 755 | #endif | ||
| 756 | |||
| 757 | /* | ||
| 758 | * Signals different on ES2.0 compared to superset | ||
| 759 | */ | ||
| 760 | static struct omap_mux __initdata omap4_es2_core_subset[] = { | ||
| 761 | _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", | ||
| 762 | "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL), | ||
| 763 | _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", | ||
| 764 | "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL), | ||
| 765 | _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", | ||
| 766 | "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL), | ||
| 767 | _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", | ||
| 768 | "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL), | ||
| 769 | _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", | ||
| 770 | "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL), | ||
| 771 | _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", | ||
| 772 | "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL), | ||
| 773 | _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", | ||
| 774 | "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL), | ||
| 775 | _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", | ||
| 776 | "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL), | ||
| 777 | _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", | ||
| 778 | "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"), | ||
| 779 | _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0", | ||
| 780 | "gpio_48", NULL, NULL, NULL, "safe_mode"), | ||
| 781 | _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8", | ||
| 782 | "c2c_dataout7", "gpio_52", NULL, NULL, NULL, | ||
| 783 | "safe_mode"), | ||
| 784 | _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", | ||
| 785 | "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL), | ||
| 786 | _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, | ||
| 787 | "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL), | ||
| 788 | _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen", | ||
| 789 | "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, | ||
| 790 | NULL, "safe_mode"), | ||
| 791 | _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", | ||
| 792 | "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"), | ||
| 793 | _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", | ||
| 794 | "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"), | ||
| 795 | _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0", | ||
| 796 | "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, | ||
| 797 | NULL, "safe_mode"), | ||
| 798 | _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1", | ||
| 799 | "c2c_dataout1", "gpio_104", NULL, NULL, NULL, | ||
| 800 | "safe_mode"), | ||
| 801 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", | ||
| 802 | "hsi1_acwake", "mcbsp4_clkx", "gpio_88", | ||
| 803 | "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", | ||
| 804 | "safe_mode"), | ||
| 805 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", | ||
| 806 | "hsi1_acdata", "mcbsp4_dx", "gpio_89", | ||
| 807 | "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", | ||
| 808 | "safe_mode"), | ||
| 809 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", | ||
| 810 | "hsi1_acflag", "mcbsp4_dr", "gpio_90", | ||
| 811 | "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", | ||
| 812 | "safe_mode"), | ||
| 813 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", | ||
| 814 | "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", | ||
| 815 | "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"), | ||
| 816 | _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, | ||
| 817 | "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, | ||
| 818 | "safe_mode"), | ||
| 819 | _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, | ||
| 820 | "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, | ||
| 821 | "safe_mode"), | ||
| 822 | _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", | ||
| 823 | "abe_mcasp_axr", "gpio_121", NULL, | ||
| 824 | "dmtimer11_pwm_evt", NULL, "safe_mode"), | ||
| 825 | _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", | ||
| 826 | "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", | ||
| 827 | NULL, "safe_mode"), | ||
| 828 | _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", | ||
| 829 | "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", | ||
| 830 | NULL, "safe_mode"), | ||
| 831 | _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", | ||
| 832 | "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", | ||
| 833 | NULL, "safe_mode"), | ||
| 834 | _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", | ||
| 835 | "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", | ||
| 836 | NULL, "safe_mode"), | ||
| 837 | _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, | ||
| 838 | "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", | ||
| 839 | NULL, "safe_mode"), | ||
| 840 | _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, | ||
| 841 | "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"), | ||
| 842 | _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, | ||
| 843 | "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"), | ||
| 844 | _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", | ||
| 845 | "kpd_col6", "gpio_151", NULL, NULL, NULL, | ||
| 846 | "safe_mode"), | ||
| 847 | _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", | ||
| 848 | "kpd_col7", "gpio_152", NULL, NULL, NULL, | ||
| 849 | "safe_mode"), | ||
| 850 | _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", | ||
| 851 | "kpd_row6", "gpio_153", NULL, NULL, NULL, | ||
| 852 | "safe_mode"), | ||
| 853 | _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", | ||
| 854 | "kpd_row7", "gpio_154", NULL, NULL, NULL, | ||
| 855 | "safe_mode"), | ||
| 856 | _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8", | ||
| 857 | "gpio_155", NULL, NULL, NULL, "safe_mode"), | ||
| 858 | _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8", | ||
| 859 | "gpio_156", NULL, NULL, NULL, "safe_mode"), | ||
| 860 | _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", | ||
| 861 | "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", | ||
| 862 | "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"), | ||
| 863 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", | ||
| 864 | "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", | ||
| 865 | "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"), | ||
| 866 | _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", | ||
| 867 | "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", | ||
| 868 | "hsi2_acready", "dispc2_data21", NULL, "safe_mode"), | ||
| 869 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", | ||
| 870 | "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", | ||
| 871 | "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", | ||
| 872 | "safe_mode"), | ||
| 873 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", | ||
| 874 | "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", | ||
| 875 | "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", | ||
| 876 | "safe_mode"), | ||
| 877 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", | ||
| 878 | "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", | ||
| 879 | "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", | ||
| 880 | "safe_mode"), | ||
| 881 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", | ||
| 882 | "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", | ||
| 883 | "hsi2_caready", "dispc2_data15", "rfbi_data15", | ||
| 884 | "safe_mode"), | ||
| 885 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", | ||
| 886 | "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", | ||
| 887 | "mcspi3_somi", "dispc2_data14", "rfbi_data14", | ||
| 888 | "safe_mode"), | ||
| 889 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", | ||
| 890 | "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", | ||
| 891 | "mcspi3_cs0", "dispc2_data13", "rfbi_data13", | ||
| 892 | "safe_mode"), | ||
| 893 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", | ||
| 894 | "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", | ||
| 895 | "mcspi3_simo", "dispc2_data12", "rfbi_data12", | ||
| 896 | "safe_mode"), | ||
| 897 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", | ||
| 898 | "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", | ||
| 899 | "mcspi3_clk", "dispc2_data11", "rfbi_data11", | ||
| 900 | "safe_mode"), | ||
| 901 | _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL, | ||
| 902 | "gpio_171", NULL, NULL, NULL, "safe_mode"), | ||
| 903 | _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL, | ||
| 904 | "gpio_172", NULL, NULL, NULL, "safe_mode"), | ||
| 905 | _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL, | ||
| 906 | "gpio_173", NULL, NULL, NULL, "safe_mode"), | ||
| 907 | _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL, | ||
| 908 | "gpio_174", NULL, NULL, NULL, "safe_mode"), | ||
| 909 | _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", | ||
| 910 | NULL, NULL, NULL, "safe_mode"), | ||
| 911 | _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1", | ||
| 912 | NULL, NULL, NULL, "safe_mode"), | ||
| 913 | _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL, | ||
| 914 | "gpio_175", NULL, NULL, NULL, "safe_mode"), | ||
| 915 | _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL, | ||
| 916 | "gpio_176", NULL, NULL, NULL, "safe_mode"), | ||
| 917 | _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL, | ||
| 918 | "gpio_177", NULL, NULL, NULL, "safe_mode"), | ||
| 919 | _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL, | ||
| 920 | "gpio_178", NULL, NULL, NULL, "safe_mode"), | ||
| 921 | _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2", | ||
| 922 | NULL, NULL, NULL, "safe_mode"), | ||
| 923 | _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", | ||
| 924 | NULL, NULL, NULL, "safe_mode"), | ||
| 925 | _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx", | ||
| 926 | "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 927 | _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx", | ||
| 928 | "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 929 | _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, | ||
| 930 | "gpio_13", NULL, "dispc2_fid", "hw_dbg2", | ||
| 931 | "safe_mode"), | ||
| 932 | _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, | ||
| 933 | "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", | ||
| 934 | "safe_mode"), | ||
| 935 | _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, | ||
| 936 | "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", | ||
| 937 | "safe_mode"), | ||
| 938 | _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, | ||
| 939 | "gpio_16", "rfbi_te_vsync0", "dispc2_data16", | ||
| 940 | "hw_dbg5", "safe_mode"), | ||
| 941 | _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", | ||
| 942 | "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", | ||
| 943 | "dispc2_data17", "hw_dbg6", "safe_mode"), | ||
| 944 | _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", | ||
| 945 | "uart3_rx_irrx", "gpio_18", "rfbi_cs0", | ||
| 946 | "dispc2_hsync", "hw_dbg7", "safe_mode"), | ||
| 947 | _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", | ||
| 948 | "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", | ||
| 949 | "hw_dbg8", "safe_mode"), | ||
| 950 | _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", | ||
| 951 | "uart3_cts_rctx", "gpio_20", "rfbi_we", | ||
| 952 | "dispc2_vsync", "hw_dbg9", "safe_mode"), | ||
| 953 | _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", | ||
| 954 | NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", | ||
| 955 | "safe_mode"), | ||
| 956 | _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", | ||
| 957 | NULL, "gpio_22", "rfbi_data8", "dispc2_data8", | ||
| 958 | "hw_dbg11", "safe_mode"), | ||
| 959 | _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", | ||
| 960 | NULL, "gpio_23", "rfbi_data7", "dispc2_data7", | ||
| 961 | "hw_dbg12", "safe_mode"), | ||
| 962 | _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", | ||
| 963 | NULL, "gpio_24", "rfbi_data6", "dispc2_data6", | ||
| 964 | "hw_dbg13", "safe_mode"), | ||
| 965 | _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", | ||
| 966 | "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", | ||
| 967 | "hw_dbg14", "safe_mode"), | ||
| 968 | _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", | ||
| 969 | NULL, "gpio_26", "rfbi_data4", "dispc2_data4", | ||
| 970 | "hw_dbg15", "safe_mode"), | ||
| 971 | _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", | ||
| 972 | "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", | ||
| 973 | "hw_dbg16", "safe_mode"), | ||
| 974 | _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", | ||
| 975 | "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", | ||
| 976 | "hw_dbg17", "safe_mode"), | ||
| 977 | _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", | ||
| 978 | "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", | ||
| 979 | "hw_dbg18", "safe_mode"), | ||
| 980 | _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", | ||
| 981 | "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", | ||
| 982 | "hw_dbg19", "safe_mode"), | ||
| 983 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 984 | }; | ||
| 985 | |||
| 986 | /* | ||
| 987 | * Balls for 44XX CBS package | ||
| 988 | * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), | ||
| 989 | * 0.40mm Ball Pitch (Bottom) | ||
| 990 | */ | ||
| 991 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
| 992 | && defined(CONFIG_OMAP_PACKAGE_CBS) | ||
| 993 | static struct omap_ball __initdata omap4_core_cbs_ball[] = { | ||
| 994 | _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), | ||
| 995 | _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), | ||
| 996 | _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), | ||
| 997 | _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), | ||
| 998 | _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), | ||
| 999 | _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), | ||
| 1000 | _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), | ||
| 1001 | _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), | ||
| 1002 | _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), | ||
| 1003 | _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), | ||
| 1004 | _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), | ||
| 1005 | _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), | ||
| 1006 | _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), | ||
| 1007 | _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), | ||
| 1008 | _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), | ||
| 1009 | _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), | ||
| 1010 | _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), | ||
| 1011 | _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), | ||
| 1012 | _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), | ||
| 1013 | _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), | ||
| 1014 | _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), | ||
| 1015 | _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), | ||
| 1016 | _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), | ||
| 1017 | _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), | ||
| 1018 | _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), | ||
| 1019 | _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), | ||
| 1020 | _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), | ||
| 1021 | _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), | ||
| 1022 | _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), | ||
| 1023 | _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), | ||
| 1024 | _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), | ||
| 1025 | _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), | ||
| 1026 | _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), | ||
| 1027 | _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), | ||
| 1028 | _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), | ||
| 1029 | _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), | ||
| 1030 | _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), | ||
| 1031 | _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), | ||
| 1032 | _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), | ||
| 1033 | _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL), | ||
| 1034 | _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL), | ||
| 1035 | _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL), | ||
| 1036 | _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL), | ||
| 1037 | _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL), | ||
| 1038 | _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), | ||
| 1039 | _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), | ||
| 1040 | _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), | ||
| 1041 | _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), | ||
| 1042 | _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), | ||
| 1043 | _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), | ||
| 1044 | _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), | ||
| 1045 | _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), | ||
| 1046 | _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), | ||
| 1047 | _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), | ||
| 1048 | _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), | ||
| 1049 | _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), | ||
| 1050 | _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), | ||
| 1051 | _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), | ||
| 1052 | _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), | ||
| 1053 | _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), | ||
| 1054 | _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), | ||
| 1055 | _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), | ||
| 1056 | _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), | ||
| 1057 | _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), | ||
| 1058 | _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), | ||
| 1059 | _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), | ||
| 1060 | _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), | ||
| 1061 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), | ||
| 1062 | _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), | ||
| 1063 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), | ||
| 1064 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), | ||
| 1065 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), | ||
| 1066 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), | ||
| 1067 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), | ||
| 1068 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), | ||
| 1069 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), | ||
| 1070 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), | ||
| 1071 | _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), | ||
| 1072 | _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), | ||
| 1073 | _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), | ||
| 1074 | _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), | ||
| 1075 | _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), | ||
| 1076 | _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), | ||
| 1077 | _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), | ||
| 1078 | _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), | ||
| 1079 | _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), | ||
| 1080 | _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), | ||
| 1081 | _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), | ||
| 1082 | _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), | ||
| 1083 | _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), | ||
| 1084 | _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), | ||
| 1085 | _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), | ||
| 1086 | _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), | ||
| 1087 | _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), | ||
| 1088 | _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), | ||
| 1089 | _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), | ||
| 1090 | _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), | ||
| 1091 | _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), | ||
| 1092 | _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), | ||
| 1093 | _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), | ||
| 1094 | _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), | ||
| 1095 | _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), | ||
| 1096 | _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), | ||
| 1097 | _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), | ||
| 1098 | _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), | ||
| 1099 | _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), | ||
| 1100 | _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), | ||
| 1101 | _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), | ||
| 1102 | _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), | ||
| 1103 | _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), | ||
| 1104 | _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), | ||
| 1105 | _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), | ||
| 1106 | _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), | ||
| 1107 | _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), | ||
| 1108 | _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), | ||
| 1109 | _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), | ||
| 1110 | _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), | ||
| 1111 | _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), | ||
| 1112 | _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), | ||
| 1113 | _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), | ||
| 1114 | _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), | ||
| 1115 | _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), | ||
| 1116 | _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), | ||
| 1117 | _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), | ||
| 1118 | _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), | ||
| 1119 | _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), | ||
| 1120 | _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), | ||
| 1121 | _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), | ||
| 1122 | _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), | ||
| 1123 | _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), | ||
| 1124 | _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), | ||
| 1125 | _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), | ||
| 1126 | _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), | ||
| 1127 | _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), | ||
| 1128 | _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), | ||
| 1129 | _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), | ||
| 1130 | _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), | ||
| 1131 | _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), | ||
| 1132 | _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), | ||
| 1133 | _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), | ||
| 1134 | _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), | ||
| 1135 | _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), | ||
| 1136 | _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), | ||
| 1137 | _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), | ||
| 1138 | _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), | ||
| 1139 | _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), | ||
| 1140 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), | ||
| 1141 | _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), | ||
| 1142 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), | ||
| 1143 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), | ||
| 1144 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), | ||
| 1145 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), | ||
| 1146 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), | ||
| 1147 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), | ||
| 1148 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), | ||
| 1149 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), | ||
| 1150 | _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), | ||
| 1151 | _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), | ||
| 1152 | _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL), | ||
| 1153 | _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL), | ||
| 1154 | _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL), | ||
| 1155 | _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL), | ||
| 1156 | _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL), | ||
| 1157 | _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL), | ||
| 1158 | _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL), | ||
| 1159 | _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL), | ||
| 1160 | _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL), | ||
| 1161 | _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL), | ||
| 1162 | _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL), | ||
| 1163 | _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL), | ||
| 1164 | _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), | ||
| 1165 | _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), | ||
| 1166 | _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), | ||
| 1167 | _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), | ||
| 1168 | _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), | ||
| 1169 | _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), | ||
| 1170 | _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), | ||
| 1171 | _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), | ||
| 1172 | _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), | ||
| 1173 | _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), | ||
| 1174 | _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), | ||
| 1175 | _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), | ||
| 1176 | _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), | ||
| 1177 | _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), | ||
| 1178 | _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), | ||
| 1179 | _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), | ||
| 1180 | _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), | ||
| 1181 | _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), | ||
| 1182 | _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), | ||
| 1183 | _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), | ||
| 1184 | _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), | ||
| 1185 | _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), | ||
| 1186 | _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), | ||
| 1187 | _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), | ||
| 1188 | _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), | ||
| 1189 | _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), | ||
| 1190 | _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), | ||
| 1191 | _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), | ||
| 1192 | _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), | ||
| 1193 | _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), | ||
| 1194 | _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), | ||
| 1195 | _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), | ||
| 1196 | _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), | ||
| 1197 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1198 | }; | ||
| 1199 | #else | ||
| 1200 | #define omap4_core_cbs_ball NULL | ||
| 1201 | #endif | ||
| 1202 | |||
| 1203 | /* | ||
| 1204 | * Superset of all mux modes for omap4 | ||
| 1205 | */ | ||
| 1206 | static struct omap_mux __initdata omap4_wkup_muxmodes[] = { | ||
| 1207 | _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, | ||
| 1208 | NULL, NULL, "safe_mode"), | ||
| 1209 | _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, | ||
| 1210 | NULL, NULL, "safe_mode"), | ||
| 1211 | _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", | ||
| 1212 | NULL, NULL, NULL, "safe_mode"), | ||
| 1213 | _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, | ||
| 1214 | NULL, NULL, "safe_mode"), | ||
| 1215 | _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", | ||
| 1216 | NULL, NULL, NULL, "safe_mode"), | ||
| 1217 | _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, | ||
| 1218 | NULL, NULL), | ||
| 1219 | _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, | ||
| 1220 | NULL, NULL), | ||
| 1221 | _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, | ||
| 1222 | "c2c_wakereqin", NULL, NULL, NULL), | ||
| 1223 | _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, | ||
| 1224 | "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), | ||
| 1225 | _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, | ||
| 1226 | NULL, NULL, NULL, NULL), | ||
| 1227 | _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", | ||
| 1228 | "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, | ||
| 1229 | "safe_mode"), | ||
| 1230 | _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", | ||
| 1231 | "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, | ||
| 1232 | NULL, "safe_mode"), | ||
| 1233 | _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", | ||
| 1234 | "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", | ||
| 1235 | NULL, NULL, "safe_mode"), | ||
| 1236 | _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", | ||
| 1237 | NULL, "gpio_wk7", NULL, NULL, NULL, NULL), | ||
| 1238 | _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, | ||
| 1239 | "gpio_wk8", NULL, NULL, NULL, NULL), | ||
| 1240 | _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, | ||
| 1241 | NULL, NULL), | ||
| 1242 | _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, | ||
| 1243 | NULL, NULL, NULL, NULL), | ||
| 1244 | _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, | ||
| 1245 | NULL, NULL, NULL, NULL), | ||
| 1246 | _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, | ||
| 1247 | NULL, NULL, NULL), | ||
| 1248 | _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, | ||
| 1249 | NULL, "gpio_wk29", NULL, NULL, NULL, NULL), | ||
| 1250 | _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, | ||
| 1251 | "gpio_wk9", "c2c_wakereqout", NULL, NULL, | ||
| 1252 | "safe_mode"), | ||
| 1253 | _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, | ||
| 1254 | "gpio_wk10", NULL, NULL, NULL, "safe_mode"), | ||
| 1255 | _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, | ||
| 1256 | NULL, NULL, NULL), | ||
| 1257 | _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, | ||
| 1258 | NULL, "safe_mode"), | ||
| 1259 | _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, | ||
| 1260 | NULL, NULL, NULL), | ||
| 1261 | _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, | ||
| 1262 | NULL, NULL, NULL, "safe_mode"), | ||
| 1263 | _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, | ||
| 1264 | NULL, NULL), | ||
| 1265 | _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, | ||
| 1266 | NULL, NULL), | ||
| 1267 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1268 | }; | ||
| 1269 | |||
| 1270 | /* | ||
| 1271 | * Balls for 44XX CBL & CBS package - wakeup partition | ||
| 1272 | * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), | ||
| 1273 | * 0.40mm Ball Pitch (Bottom) | ||
| 1274 | */ | ||
| 1275 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
| 1276 | && defined(CONFIG_OMAP_PACKAGE_CBL) | ||
| 1277 | static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { | ||
| 1278 | _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), | ||
| 1279 | _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), | ||
| 1280 | _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), | ||
| 1281 | _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), | ||
| 1282 | _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), | ||
| 1283 | _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), | ||
| 1284 | _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), | ||
| 1285 | _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), | ||
| 1286 | _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), | ||
| 1287 | _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), | ||
| 1288 | _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL), | ||
| 1289 | _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL), | ||
| 1290 | _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL), | ||
| 1291 | _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL), | ||
| 1292 | _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL), | ||
| 1293 | _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL), | ||
| 1294 | _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL), | ||
| 1295 | _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL), | ||
| 1296 | _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL), | ||
| 1297 | _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL), | ||
| 1298 | _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL), | ||
| 1299 | _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL), | ||
| 1300 | _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL), | ||
| 1301 | _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL), | ||
| 1302 | _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL), | ||
| 1303 | _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL), | ||
| 1304 | _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL), | ||
| 1305 | _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL), | ||
| 1306 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1307 | }; | ||
| 1308 | #else | ||
| 1309 | #define omap4_wkup_cbl_cbs_ball NULL | ||
| 1310 | #endif | ||
| 1311 | |||
| 1312 | int __init omap4_mux_init(struct omap_board_mux *board_subset, | ||
| 1313 | struct omap_board_mux *board_wkup_subset, int flags) | ||
| 1314 | { | ||
| 1315 | struct omap_ball *package_balls_core; | ||
| 1316 | struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball; | ||
| 1317 | struct omap_mux *core_muxmodes; | ||
| 1318 | struct omap_mux *core_subset = NULL; | ||
| 1319 | int ret; | ||
| 1320 | |||
| 1321 | switch (flags & OMAP_PACKAGE_MASK) { | ||
| 1322 | case OMAP_PACKAGE_CBL: | ||
| 1323 | pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__); | ||
| 1324 | package_balls_core = omap4_core_cbl_ball; | ||
| 1325 | core_muxmodes = omap4_core_muxmodes; | ||
| 1326 | break; | ||
| 1327 | case OMAP_PACKAGE_CBS: | ||
| 1328 | pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__); | ||
| 1329 | package_balls_core = omap4_core_cbs_ball; | ||
| 1330 | core_muxmodes = omap4_core_muxmodes; | ||
| 1331 | core_subset = omap4_es2_core_subset; | ||
| 1332 | break; | ||
| 1333 | default: | ||
| 1334 | pr_err("%s: Unknown omap package, mux disabled\n", __func__); | ||
| 1335 | return -EINVAL; | ||
| 1336 | } | ||
| 1337 | |||
| 1338 | ret = omap_mux_init("core", | ||
| 1339 | OMAP_MUX_GPIO_IN_MODE3, | ||
| 1340 | OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE, | ||
| 1341 | OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE, | ||
| 1342 | core_muxmodes, core_subset, board_subset, | ||
| 1343 | package_balls_core); | ||
| 1344 | if (ret) | ||
| 1345 | return ret; | ||
| 1346 | |||
| 1347 | ret = omap_mux_init("wkup", | ||
| 1348 | OMAP_MUX_GPIO_IN_MODE3, | ||
| 1349 | OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE, | ||
| 1350 | OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE, | ||
| 1351 | omap4_wkup_muxmodes, NULL, board_wkup_subset, | ||
| 1352 | package_balls_wkup); | ||
| 1353 | |||
| 1354 | return ret; | ||
| 1355 | } | ||
| 1356 | |||
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h deleted file mode 100644 index c635026cd7e9..000000000000 --- a/arch/arm/mach-omap2/mux44xx.h +++ /dev/null | |||
| @@ -1,298 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx MUX registers and bitfields | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * | ||
| 8 | * This file is automatically generated from the OMAP hardware databases. | ||
| 9 | * We respectfully ask that any modifications to this file be coordinated | ||
| 10 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 11 | * authors above to ensure that the autogeneration scripts are kept | ||
| 12 | * up-to-date with the file contents. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H | ||
| 20 | #define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H | ||
| 21 | |||
| 22 | #define OMAP4_MUX(M0, mux_value) \ | ||
| 23 | { \ | ||
| 24 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 25 | .value = (mux_value), \ | ||
| 26 | } | ||
| 27 | |||
| 28 | /* ctrl_module_pad_core base address */ | ||
| 29 | #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000 | ||
| 30 | |||
| 31 | /* ctrl_module_pad_core registers offset */ | ||
| 32 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040 | ||
| 33 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042 | ||
| 34 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044 | ||
| 35 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046 | ||
| 36 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048 | ||
| 37 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a | ||
| 38 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c | ||
| 39 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e | ||
| 40 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050 | ||
| 41 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052 | ||
| 42 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054 | ||
| 43 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056 | ||
| 44 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058 | ||
| 45 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a | ||
| 46 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c | ||
| 47 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e | ||
| 48 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060 | ||
| 49 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062 | ||
| 50 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064 | ||
| 51 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066 | ||
| 52 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068 | ||
| 53 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a | ||
| 54 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c | ||
| 55 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e | ||
| 56 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070 | ||
| 57 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072 | ||
| 58 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074 | ||
| 59 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076 | ||
| 60 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078 | ||
| 61 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a | ||
| 62 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c | ||
| 63 | #define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e | ||
| 64 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080 | ||
| 65 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082 | ||
| 66 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084 | ||
| 67 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086 | ||
| 68 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088 | ||
| 69 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a | ||
| 70 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c | ||
| 71 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e | ||
| 72 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090 | ||
| 73 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092 | ||
| 74 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094 | ||
| 75 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096 | ||
| 76 | #define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098 | ||
| 77 | #define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a | ||
| 78 | #define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c | ||
| 79 | #define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e | ||
| 80 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0 | ||
| 81 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2 | ||
| 82 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4 | ||
| 83 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6 | ||
| 84 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8 | ||
| 85 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa | ||
| 86 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac | ||
| 87 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae | ||
| 88 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0 | ||
| 89 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2 | ||
| 90 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4 | ||
| 91 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6 | ||
| 92 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8 | ||
| 93 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba | ||
| 94 | #define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc | ||
| 95 | #define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be | ||
| 96 | #define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0 | ||
| 97 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2 | ||
| 98 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4 | ||
| 99 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6 | ||
| 100 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8 | ||
| 101 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca | ||
| 102 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc | ||
| 103 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce | ||
| 104 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0 | ||
| 105 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2 | ||
| 106 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4 | ||
| 107 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6 | ||
| 108 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8 | ||
| 109 | #define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da | ||
| 110 | #define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc | ||
| 111 | #define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de | ||
| 112 | #define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0 | ||
| 113 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2 | ||
| 114 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4 | ||
| 115 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6 | ||
| 116 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8 | ||
| 117 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea | ||
| 118 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec | ||
| 119 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee | ||
| 120 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0 | ||
| 121 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2 | ||
| 122 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4 | ||
| 123 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6 | ||
| 124 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8 | ||
| 125 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa | ||
| 126 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc | ||
| 127 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe | ||
| 128 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100 | ||
| 129 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102 | ||
| 130 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104 | ||
| 131 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106 | ||
| 132 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108 | ||
| 133 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a | ||
| 134 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c | ||
| 135 | #define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e | ||
| 136 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110 | ||
| 137 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112 | ||
| 138 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114 | ||
| 139 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116 | ||
| 140 | #define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118 | ||
| 141 | #define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a | ||
| 142 | #define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c | ||
| 143 | #define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e | ||
| 144 | #define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120 | ||
| 145 | #define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122 | ||
| 146 | #define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124 | ||
| 147 | #define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126 | ||
| 148 | #define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128 | ||
| 149 | #define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a | ||
| 150 | #define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c | ||
| 151 | #define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e | ||
| 152 | #define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130 | ||
| 153 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132 | ||
| 154 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134 | ||
| 155 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136 | ||
| 156 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138 | ||
| 157 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a | ||
| 158 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c | ||
| 159 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e | ||
| 160 | #define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140 | ||
| 161 | #define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142 | ||
| 162 | #define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144 | ||
| 163 | #define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146 | ||
| 164 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148 | ||
| 165 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a | ||
| 166 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c | ||
| 167 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e | ||
| 168 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150 | ||
| 169 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152 | ||
| 170 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154 | ||
| 171 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156 | ||
| 172 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158 | ||
| 173 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a | ||
| 174 | #define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c | ||
| 175 | #define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e | ||
| 176 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160 | ||
| 177 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162 | ||
| 178 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164 | ||
| 179 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166 | ||
| 180 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168 | ||
| 181 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a | ||
| 182 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c | ||
| 183 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e | ||
| 184 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170 | ||
| 185 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172 | ||
| 186 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174 | ||
| 187 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176 | ||
| 188 | #define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178 | ||
| 189 | #define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a | ||
| 190 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c | ||
| 191 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e | ||
| 192 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180 | ||
| 193 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182 | ||
| 194 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184 | ||
| 195 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186 | ||
| 196 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188 | ||
| 197 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a | ||
| 198 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c | ||
| 199 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e | ||
| 200 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190 | ||
| 201 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192 | ||
| 202 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194 | ||
| 203 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196 | ||
| 204 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198 | ||
| 205 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a | ||
| 206 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c | ||
| 207 | #define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e | ||
| 208 | #define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0 | ||
| 209 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2 | ||
| 210 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4 | ||
| 211 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6 | ||
| 212 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8 | ||
| 213 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa | ||
| 214 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac | ||
| 215 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae | ||
| 216 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0 | ||
| 217 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2 | ||
| 218 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4 | ||
| 219 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6 | ||
| 220 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8 | ||
| 221 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba | ||
| 222 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc | ||
| 223 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be | ||
| 224 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0 | ||
| 225 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2 | ||
| 226 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4 | ||
| 227 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6 | ||
| 228 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8 | ||
| 229 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca | ||
| 230 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc | ||
| 231 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce | ||
| 232 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0 | ||
| 233 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 | ||
| 234 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 | ||
| 235 | |||
| 236 | /* ES2.0 only */ | ||
| 237 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e | ||
| 238 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090 | ||
| 239 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092 | ||
| 240 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094 | ||
| 241 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096 | ||
| 242 | |||
| 243 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c | ||
| 244 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e | ||
| 245 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180 | ||
| 246 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182 | ||
| 247 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184 | ||
| 248 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186 | ||
| 249 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188 | ||
| 250 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a | ||
| 251 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c | ||
| 252 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e | ||
| 253 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190 | ||
| 254 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192 | ||
| 255 | |||
| 256 | |||
| 257 | #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ | ||
| 258 | (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ | ||
| 259 | - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) | ||
| 260 | |||
| 261 | /* ctrl_module_pad_wkup base address */ | ||
| 262 | #define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000 | ||
| 263 | |||
| 264 | /* ctrl_module_pad_wkup registers offset */ | ||
| 265 | #define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040 | ||
| 266 | #define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042 | ||
| 267 | #define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044 | ||
| 268 | #define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046 | ||
| 269 | #define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048 | ||
| 270 | #define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a | ||
| 271 | #define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c | ||
| 272 | #define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e | ||
| 273 | #define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050 | ||
| 274 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052 | ||
| 275 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054 | ||
| 276 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056 | ||
| 277 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058 | ||
| 278 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a | ||
| 279 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c | ||
| 280 | #define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e | ||
| 281 | #define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060 | ||
| 282 | #define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062 | ||
| 283 | #define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064 | ||
| 284 | #define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066 | ||
| 285 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068 | ||
| 286 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a | ||
| 287 | #define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c | ||
| 288 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e | ||
| 289 | #define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070 | ||
| 290 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072 | ||
| 291 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074 | ||
| 292 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076 | ||
| 293 | |||
| 294 | #define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \ | ||
| 295 | (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \ | ||
| 296 | - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2) | ||
| 297 | |||
| 298 | #endif | ||
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index e6d230700b2b..68be532f8688 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c | |||
| @@ -170,9 +170,6 @@ static int omap_device_build_from_dt(struct platform_device *pdev) | |||
| 170 | r->name = dev_name(&pdev->dev); | 170 | r->name = dev_name(&pdev->dev); |
| 171 | } | 171 | } |
| 172 | 172 | ||
| 173 | if (of_get_property(node, "ti,no_idle_on_suspend", NULL)) | ||
| 174 | omap_device_disable_idle_on_suspend(pdev); | ||
| 175 | |||
| 176 | pdev->dev.pm_domain = &omap_device_pm_domain; | 173 | pdev->dev.pm_domain = &omap_device_pm_domain; |
| 177 | 174 | ||
| 178 | odbfd_exit1: | 175 | odbfd_exit1: |
| @@ -621,8 +618,7 @@ static int _od_suspend_noirq(struct device *dev) | |||
| 621 | 618 | ||
| 622 | if (!ret && !pm_runtime_status_suspended(dev)) { | 619 | if (!ret && !pm_runtime_status_suspended(dev)) { |
| 623 | if (pm_generic_runtime_suspend(dev) == 0) { | 620 | if (pm_generic_runtime_suspend(dev) == 0) { |
| 624 | if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)) | 621 | omap_device_idle(pdev); |
| 625 | omap_device_idle(pdev); | ||
| 626 | od->flags |= OMAP_DEVICE_SUSPENDED; | 622 | od->flags |= OMAP_DEVICE_SUSPENDED; |
| 627 | } | 623 | } |
| 628 | } | 624 | } |
| @@ -638,8 +634,7 @@ static int _od_resume_noirq(struct device *dev) | |||
| 638 | if ((od->flags & OMAP_DEVICE_SUSPENDED) && | 634 | if ((od->flags & OMAP_DEVICE_SUSPENDED) && |
| 639 | !pm_runtime_status_suspended(dev)) { | 635 | !pm_runtime_status_suspended(dev)) { |
| 640 | od->flags &= ~OMAP_DEVICE_SUSPENDED; | 636 | od->flags &= ~OMAP_DEVICE_SUSPENDED; |
| 641 | if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)) | 637 | omap_device_enable(pdev); |
| 642 | omap_device_enable(pdev); | ||
| 643 | pm_generic_runtime_resume(dev); | 638 | pm_generic_runtime_resume(dev); |
| 644 | } | 639 | } |
| 645 | 640 | ||
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h index 044c31d50e5b..17ca1aec2710 100644 --- a/arch/arm/mach-omap2/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h | |||
| @@ -38,7 +38,6 @@ extern struct dev_pm_domain omap_device_pm_domain; | |||
| 38 | 38 | ||
| 39 | /* omap_device.flags values */ | 39 | /* omap_device.flags values */ |
| 40 | #define OMAP_DEVICE_SUSPENDED BIT(0) | 40 | #define OMAP_DEVICE_SUSPENDED BIT(0) |
| 41 | #define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1) | ||
| 42 | 41 | ||
| 43 | /** | 42 | /** |
| 44 | * struct omap_device - omap_device wrapper for platform_devices | 43 | * struct omap_device - omap_device wrapper for platform_devices |
| @@ -101,13 +100,4 @@ static inline struct omap_device *to_omap_device(struct platform_device *pdev) | |||
| 101 | { | 100 | { |
| 102 | return pdev ? pdev->archdata.od : NULL; | 101 | return pdev ? pdev->archdata.od : NULL; |
| 103 | } | 102 | } |
| 104 | |||
| 105 | static inline | ||
| 106 | void omap_device_disable_idle_on_suspend(struct platform_device *pdev) | ||
| 107 | { | ||
| 108 | struct omap_device *od = to_omap_device(pdev); | ||
| 109 | |||
| 110 | od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND; | ||
| 111 | } | ||
| 112 | |||
| 113 | #endif | 103 | #endif |
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 69337af748cc..3c7675a6a8f4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c | |||
| @@ -35,29 +35,6 @@ | |||
| 35 | */ | 35 | */ |
| 36 | 36 | ||
| 37 | /* | 37 | /* |
| 38 | * 'emif_fw' class | ||
| 39 | * instance(s): emif_fw | ||
| 40 | */ | ||
| 41 | static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = { | ||
| 42 | .name = "emif_fw", | ||
| 43 | }; | ||
| 44 | |||
| 45 | /* emif_fw */ | ||
| 46 | static struct omap_hwmod am33xx_emif_fw_hwmod = { | ||
| 47 | .name = "emif_fw", | ||
| 48 | .class = &am33xx_emif_fw_hwmod_class, | ||
| 49 | .clkdm_name = "l4fw_clkdm", | ||
| 50 | .main_clk = "l4fw_gclk", | ||
| 51 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
| 52 | .prcm = { | ||
| 53 | .omap4 = { | ||
| 54 | .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET, | ||
| 55 | .modulemode = MODULEMODE_SWCTRL, | ||
| 56 | }, | ||
| 57 | }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | /* | ||
| 61 | * 'emif' class | 38 | * 'emif' class |
| 62 | * instance(s): emif | 39 | * instance(s): emif |
| 63 | */ | 40 | */ |
| @@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = { | |||
| 70 | .sysc = &am33xx_emif_sysc, | 47 | .sysc = &am33xx_emif_sysc, |
| 71 | }; | 48 | }; |
| 72 | 49 | ||
| 73 | static struct omap_hwmod_irq_info am33xx_emif_irqs[] = { | ||
| 74 | { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, }, | ||
| 75 | { .irq = -1 }, | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* emif */ | 50 | /* emif */ |
| 79 | static struct omap_hwmod am33xx_emif_hwmod = { | 51 | static struct omap_hwmod am33xx_emif_hwmod = { |
| 80 | .name = "emif", | 52 | .name = "emif", |
| 81 | .class = &am33xx_emif_hwmod_class, | 53 | .class = &am33xx_emif_hwmod_class, |
| 82 | .clkdm_name = "l3_clkdm", | 54 | .clkdm_name = "l3_clkdm", |
| 83 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 55 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 84 | .mpu_irqs = am33xx_emif_irqs, | ||
| 85 | .main_clk = "dpll_ddr_m2_div2_ck", | 56 | .main_clk = "dpll_ddr_m2_div2_ck", |
| 86 | .prcm = { | 57 | .prcm = { |
| 87 | .omap4 = { | 58 | .omap4 = { |
| @@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = { | |||
| 99 | .name = "l3", | 70 | .name = "l3", |
| 100 | }; | 71 | }; |
| 101 | 72 | ||
| 102 | /* l3_main (l3_fast) */ | ||
| 103 | static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = { | ||
| 104 | { .name = "l3debug", .irq = 9 + OMAP_INTC_START, }, | ||
| 105 | { .name = "l3appint", .irq = 10 + OMAP_INTC_START, }, | ||
| 106 | { .irq = -1 }, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct omap_hwmod am33xx_l3_main_hwmod = { | 73 | static struct omap_hwmod am33xx_l3_main_hwmod = { |
| 110 | .name = "l3_main", | 74 | .name = "l3_main", |
| 111 | .class = &am33xx_l3_hwmod_class, | 75 | .class = &am33xx_l3_hwmod_class, |
| 112 | .clkdm_name = "l3_clkdm", | 76 | .clkdm_name = "l3_clkdm", |
| 113 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 77 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 114 | .mpu_irqs = am33xx_l3_main_irqs, | ||
| 115 | .main_clk = "l3_gclk", | 78 | .main_clk = "l3_gclk", |
| 116 | .prcm = { | 79 | .prcm = { |
| 117 | .omap4 = { | 80 | .omap4 = { |
| @@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = { | |||
| 196 | }, | 159 | }, |
| 197 | }; | 160 | }; |
| 198 | 161 | ||
| 199 | /* l4_fw */ | ||
| 200 | static struct omap_hwmod am33xx_l4_fw_hwmod = { | ||
| 201 | .name = "l4_fw", | ||
| 202 | .class = &am33xx_l4_hwmod_class, | ||
| 203 | .clkdm_name = "l4fw_clkdm", | ||
| 204 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
| 205 | .prcm = { | ||
| 206 | .omap4 = { | ||
| 207 | .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET, | ||
| 208 | .modulemode = MODULEMODE_SWCTRL, | ||
| 209 | }, | ||
| 210 | }, | ||
| 211 | }; | ||
| 212 | |||
| 213 | /* | 162 | /* |
| 214 | * 'mpu' class | 163 | * 'mpu' class |
| 215 | */ | 164 | */ |
| @@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | |||
| 217 | .name = "mpu", | 166 | .name = "mpu", |
| 218 | }; | 167 | }; |
| 219 | 168 | ||
| 220 | /* mpu */ | ||
| 221 | static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = { | ||
| 222 | { .name = "emuint", .irq = 0 + OMAP_INTC_START, }, | ||
| 223 | { .name = "commtx", .irq = 1 + OMAP_INTC_START, }, | ||
| 224 | { .name = "commrx", .irq = 2 + OMAP_INTC_START, }, | ||
| 225 | { .name = "bench", .irq = 3 + OMAP_INTC_START, }, | ||
| 226 | { .irq = -1 }, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static struct omap_hwmod am33xx_mpu_hwmod = { | 169 | static struct omap_hwmod am33xx_mpu_hwmod = { |
| 230 | .name = "mpu", | 170 | .name = "mpu", |
| 231 | .class = &am33xx_mpu_hwmod_class, | 171 | .class = &am33xx_mpu_hwmod_class, |
| 232 | .clkdm_name = "mpu_clkdm", | 172 | .clkdm_name = "mpu_clkdm", |
| 233 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 173 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 234 | .mpu_irqs = am33xx_mpu_irqs, | ||
| 235 | .main_clk = "dpll_mpu_m2_ck", | 174 | .main_clk = "dpll_mpu_m2_ck", |
| 236 | .prcm = { | 175 | .prcm = { |
| 237 | .omap4 = { | 176 | .omap4 = { |
| @@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | |||
| 253 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | 192 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, |
| 254 | }; | 193 | }; |
| 255 | 194 | ||
| 256 | static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = { | ||
| 257 | { .name = "txev", .irq = 78 + OMAP_INTC_START, }, | ||
| 258 | { .irq = -1 }, | ||
| 259 | }; | ||
| 260 | |||
| 261 | /* wkup_m3 */ | 195 | /* wkup_m3 */ |
| 262 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { | 196 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { |
| 263 | .name = "wkup_m3", | 197 | .name = "wkup_m3", |
| @@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { | |||
| 265 | .clkdm_name = "l4_wkup_aon_clkdm", | 199 | .clkdm_name = "l4_wkup_aon_clkdm", |
| 266 | /* Keep hardreset asserted */ | 200 | /* Keep hardreset asserted */ |
| 267 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, | 201 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, |
| 268 | .mpu_irqs = am33xx_wkup_m3_irqs, | ||
| 269 | .main_clk = "dpll_core_m4_div2_ck", | 202 | .main_clk = "dpll_core_m4_div2_ck", |
| 270 | .prcm = { | 203 | .prcm = { |
| 271 | .omap4 = { | 204 | .omap4 = { |
| @@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | |||
| 291 | { .name = "pruss", .rst_shift = 1 }, | 224 | { .name = "pruss", .rst_shift = 1 }, |
| 292 | }; | 225 | }; |
| 293 | 226 | ||
| 294 | static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = { | ||
| 295 | { .name = "evtout0", .irq = 20 + OMAP_INTC_START, }, | ||
| 296 | { .name = "evtout1", .irq = 21 + OMAP_INTC_START, }, | ||
| 297 | { .name = "evtout2", .irq = 22 + OMAP_INTC_START, }, | ||
| 298 | { .name = "evtout3", .irq = 23 + OMAP_INTC_START, }, | ||
| 299 | { .name = "evtout4", .irq = 24 + OMAP_INTC_START, }, | ||
| 300 | { .name = "evtout5", .irq = 25 + OMAP_INTC_START, }, | ||
| 301 | { .name = "evtout6", .irq = 26 + OMAP_INTC_START, }, | ||
| 302 | { .name = "evtout7", .irq = 27 + OMAP_INTC_START, }, | ||
| 303 | { .irq = -1 }, | ||
| 304 | }; | ||
| 305 | |||
| 306 | /* pru-icss */ | 227 | /* pru-icss */ |
| 307 | /* Pseudo hwmod for reset control purpose only */ | 228 | /* Pseudo hwmod for reset control purpose only */ |
| 308 | static struct omap_hwmod am33xx_pruss_hwmod = { | 229 | static struct omap_hwmod am33xx_pruss_hwmod = { |
| 309 | .name = "pruss", | 230 | .name = "pruss", |
| 310 | .class = &am33xx_pruss_hwmod_class, | 231 | .class = &am33xx_pruss_hwmod_class, |
| 311 | .clkdm_name = "pruss_ocp_clkdm", | 232 | .clkdm_name = "pruss_ocp_clkdm", |
| 312 | .mpu_irqs = am33xx_pruss_irqs, | ||
| 313 | .main_clk = "pruss_ocp_gclk", | 233 | .main_clk = "pruss_ocp_gclk", |
| 314 | .prcm = { | 234 | .prcm = { |
| 315 | .omap4 = { | 235 | .omap4 = { |
| @@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | |||
| 332 | { .name = "gfx", .rst_shift = 0 }, | 252 | { .name = "gfx", .rst_shift = 0 }, |
| 333 | }; | 253 | }; |
| 334 | 254 | ||
| 335 | static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { | ||
| 336 | { .name = "gfxint", .irq = 37 + OMAP_INTC_START, }, | ||
| 337 | { .irq = -1 }, | ||
| 338 | }; | ||
| 339 | |||
| 340 | static struct omap_hwmod am33xx_gfx_hwmod = { | 255 | static struct omap_hwmod am33xx_gfx_hwmod = { |
| 341 | .name = "gfx", | 256 | .name = "gfx", |
| 342 | .class = &am33xx_gfx_hwmod_class, | 257 | .class = &am33xx_gfx_hwmod_class, |
| 343 | .clkdm_name = "gfx_l3_clkdm", | 258 | .clkdm_name = "gfx_l3_clkdm", |
| 344 | .mpu_irqs = am33xx_gfx_irqs, | ||
| 345 | .main_clk = "gfx_fck_div_ck", | 259 | .main_clk = "gfx_fck_div_ck", |
| 346 | .prcm = { | 260 | .prcm = { |
| 347 | .omap4 = { | 261 | .omap4 = { |
| @@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { | |||
| 387 | .sysc = &am33xx_adc_tsc_sysc, | 301 | .sysc = &am33xx_adc_tsc_sysc, |
| 388 | }; | 302 | }; |
| 389 | 303 | ||
| 390 | static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = { | ||
| 391 | { .irq = 16 + OMAP_INTC_START, }, | ||
| 392 | { .irq = -1 }, | ||
| 393 | }; | ||
| 394 | |||
| 395 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { | 304 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { |
| 396 | .name = "adc_tsc", | 305 | .name = "adc_tsc", |
| 397 | .class = &am33xx_adc_tsc_hwmod_class, | 306 | .class = &am33xx_adc_tsc_hwmod_class, |
| 398 | .clkdm_name = "l4_wkup_clkdm", | 307 | .clkdm_name = "l4_wkup_clkdm", |
| 399 | .mpu_irqs = am33xx_adc_tsc_irqs, | ||
| 400 | .main_clk = "adc_tsc_fck", | 308 | .main_clk = "adc_tsc_fck", |
| 401 | .prcm = { | 309 | .prcm = { |
| 402 | .omap4 = { | 310 | .omap4 = { |
| @@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | |||
| 515 | .sysc = &am33xx_aes0_sysc, | 423 | .sysc = &am33xx_aes0_sysc, |
| 516 | }; | 424 | }; |
| 517 | 425 | ||
| 518 | static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { | ||
| 519 | { .irq = 103 + OMAP_INTC_START, }, | ||
| 520 | { .irq = -1 }, | ||
| 521 | }; | ||
| 522 | |||
| 523 | static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = { | ||
| 524 | { .name = "tx", .dma_req = 6, }, | ||
| 525 | { .name = "rx", .dma_req = 5, }, | ||
| 526 | { .dma_req = -1 } | ||
| 527 | }; | ||
| 528 | |||
| 529 | static struct omap_hwmod am33xx_aes0_hwmod = { | 426 | static struct omap_hwmod am33xx_aes0_hwmod = { |
| 530 | .name = "aes", | 427 | .name = "aes", |
| 531 | .class = &am33xx_aes0_hwmod_class, | 428 | .class = &am33xx_aes0_hwmod_class, |
| 532 | .clkdm_name = "l3_clkdm", | 429 | .clkdm_name = "l3_clkdm", |
| 533 | .mpu_irqs = am33xx_aes0_irqs, | ||
| 534 | .sdma_reqs = am33xx_aes0_edma_reqs, | ||
| 535 | .main_clk = "aes0_fck", | 430 | .main_clk = "aes0_fck", |
| 536 | .prcm = { | 431 | .prcm = { |
| 537 | .omap4 = { | 432 | .omap4 = { |
| @@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = { | |||
| 554 | .sysc = &am33xx_sha0_sysc, | 449 | .sysc = &am33xx_sha0_sysc, |
| 555 | }; | 450 | }; |
| 556 | 451 | ||
| 557 | static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { | ||
| 558 | { .irq = 109 + OMAP_INTC_START, }, | ||
| 559 | { .irq = -1 }, | ||
| 560 | }; | ||
| 561 | |||
| 562 | static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = { | ||
| 563 | { .name = "rx", .dma_req = 36, }, | ||
| 564 | { .dma_req = -1 } | ||
| 565 | }; | ||
| 566 | |||
| 567 | static struct omap_hwmod am33xx_sha0_hwmod = { | 452 | static struct omap_hwmod am33xx_sha0_hwmod = { |
| 568 | .name = "sham", | 453 | .name = "sham", |
| 569 | .class = &am33xx_sha0_hwmod_class, | 454 | .class = &am33xx_sha0_hwmod_class, |
| 570 | .clkdm_name = "l3_clkdm", | 455 | .clkdm_name = "l3_clkdm", |
| 571 | .mpu_irqs = am33xx_sha0_irqs, | ||
| 572 | .sdma_reqs = am33xx_sha0_edma_reqs, | ||
| 573 | .main_clk = "l3_gclk", | 456 | .main_clk = "l3_gclk", |
| 574 | .prcm = { | 457 | .prcm = { |
| 575 | .omap4 = { | 458 | .omap4 = { |
| @@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | |||
| 604 | }; | 487 | }; |
| 605 | 488 | ||
| 606 | /* smartreflex0 */ | 489 | /* smartreflex0 */ |
| 607 | static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = { | ||
| 608 | { .irq = 120 + OMAP_INTC_START, }, | ||
| 609 | { .irq = -1 }, | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { | 490 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { |
| 613 | .name = "smartreflex0", | 491 | .name = "smartreflex0", |
| 614 | .class = &am33xx_smartreflex_hwmod_class, | 492 | .class = &am33xx_smartreflex_hwmod_class, |
| 615 | .clkdm_name = "l4_wkup_clkdm", | 493 | .clkdm_name = "l4_wkup_clkdm", |
| 616 | .mpu_irqs = am33xx_smartreflex0_irqs, | ||
| 617 | .main_clk = "smartreflex0_fck", | 494 | .main_clk = "smartreflex0_fck", |
| 618 | .prcm = { | 495 | .prcm = { |
| 619 | .omap4 = { | 496 | .omap4 = { |
| @@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = { | |||
| 624 | }; | 501 | }; |
| 625 | 502 | ||
| 626 | /* smartreflex1 */ | 503 | /* smartreflex1 */ |
| 627 | static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = { | ||
| 628 | { .irq = 121 + OMAP_INTC_START, }, | ||
| 629 | { .irq = -1 }, | ||
| 630 | }; | ||
| 631 | |||
| 632 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { | 504 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { |
| 633 | .name = "smartreflex1", | 505 | .name = "smartreflex1", |
| 634 | .class = &am33xx_smartreflex_hwmod_class, | 506 | .class = &am33xx_smartreflex_hwmod_class, |
| 635 | .clkdm_name = "l4_wkup_clkdm", | 507 | .clkdm_name = "l4_wkup_clkdm", |
| 636 | .mpu_irqs = am33xx_smartreflex1_irqs, | ||
| 637 | .main_clk = "smartreflex1_fck", | 508 | .main_clk = "smartreflex1_fck", |
| 638 | .prcm = { | 509 | .prcm = { |
| 639 | .omap4 = { | 510 | .omap4 = { |
| @@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = { | |||
| 650 | .name = "control", | 521 | .name = "control", |
| 651 | }; | 522 | }; |
| 652 | 523 | ||
| 653 | static struct omap_hwmod_irq_info am33xx_control_irqs[] = { | ||
| 654 | { .irq = 8 + OMAP_INTC_START, }, | ||
| 655 | { .irq = -1 }, | ||
| 656 | }; | ||
| 657 | |||
| 658 | static struct omap_hwmod am33xx_control_hwmod = { | 524 | static struct omap_hwmod am33xx_control_hwmod = { |
| 659 | .name = "control", | 525 | .name = "control", |
| 660 | .class = &am33xx_control_hwmod_class, | 526 | .class = &am33xx_control_hwmod_class, |
| 661 | .clkdm_name = "l4_wkup_clkdm", | 527 | .clkdm_name = "l4_wkup_clkdm", |
| 662 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 528 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 663 | .mpu_irqs = am33xx_control_irqs, | ||
| 664 | .main_clk = "dpll_core_m4_div2_ck", | 529 | .main_clk = "dpll_core_m4_div2_ck", |
| 665 | .prcm = { | 530 | .prcm = { |
| 666 | .omap4 = { | 531 | .omap4 = { |
| @@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | |||
| 690 | .sysc = &am33xx_cpgmac_sysc, | 555 | .sysc = &am33xx_cpgmac_sysc, |
| 691 | }; | 556 | }; |
| 692 | 557 | ||
| 693 | static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = { | ||
| 694 | { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, }, | ||
| 695 | { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, }, | ||
| 696 | { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, }, | ||
| 697 | { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, }, | ||
| 698 | { .irq = -1 }, | ||
| 699 | }; | ||
| 700 | |||
| 701 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { | 558 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { |
| 702 | .name = "cpgmac0", | 559 | .name = "cpgmac0", |
| 703 | .class = &am33xx_cpgmac0_hwmod_class, | 560 | .class = &am33xx_cpgmac0_hwmod_class, |
| 704 | .clkdm_name = "cpsw_125mhz_clkdm", | 561 | .clkdm_name = "cpsw_125mhz_clkdm", |
| 705 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | 562 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
| 706 | .mpu_irqs = am33xx_cpgmac0_irqs, | ||
| 707 | .main_clk = "cpsw_125mhz_gclk", | 563 | .main_clk = "cpsw_125mhz_gclk", |
| 708 | .prcm = { | 564 | .prcm = { |
| 709 | .omap4 = { | 565 | .omap4 = { |
| @@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | |||
| 735 | }; | 591 | }; |
| 736 | 592 | ||
| 737 | /* dcan0 */ | 593 | /* dcan0 */ |
| 738 | static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = { | ||
| 739 | { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, }, | ||
| 740 | { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, }, | ||
| 741 | { .irq = -1 }, | ||
| 742 | }; | ||
| 743 | |||
| 744 | static struct omap_hwmod am33xx_dcan0_hwmod = { | 594 | static struct omap_hwmod am33xx_dcan0_hwmod = { |
| 745 | .name = "d_can0", | 595 | .name = "d_can0", |
| 746 | .class = &am33xx_dcan_hwmod_class, | 596 | .class = &am33xx_dcan_hwmod_class, |
| 747 | .clkdm_name = "l4ls_clkdm", | 597 | .clkdm_name = "l4ls_clkdm", |
| 748 | .mpu_irqs = am33xx_dcan0_irqs, | ||
| 749 | .main_clk = "dcan0_fck", | 598 | .main_clk = "dcan0_fck", |
| 750 | .prcm = { | 599 | .prcm = { |
| 751 | .omap4 = { | 600 | .omap4 = { |
| @@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = { | |||
| 756 | }; | 605 | }; |
| 757 | 606 | ||
| 758 | /* dcan1 */ | 607 | /* dcan1 */ |
| 759 | static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = { | ||
| 760 | { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, }, | ||
| 761 | { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, }, | ||
| 762 | { .irq = -1 }, | ||
| 763 | }; | ||
| 764 | static struct omap_hwmod am33xx_dcan1_hwmod = { | 608 | static struct omap_hwmod am33xx_dcan1_hwmod = { |
| 765 | .name = "d_can1", | 609 | .name = "d_can1", |
| 766 | .class = &am33xx_dcan_hwmod_class, | 610 | .class = &am33xx_dcan_hwmod_class, |
| 767 | .clkdm_name = "l4ls_clkdm", | 611 | .clkdm_name = "l4ls_clkdm", |
| 768 | .mpu_irqs = am33xx_dcan1_irqs, | ||
| 769 | .main_clk = "dcan1_fck", | 612 | .main_clk = "dcan1_fck", |
| 770 | .prcm = { | 613 | .prcm = { |
| 771 | .omap4 = { | 614 | .omap4 = { |
| @@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = { | |||
| 792 | .sysc = &am33xx_elm_sysc, | 635 | .sysc = &am33xx_elm_sysc, |
| 793 | }; | 636 | }; |
| 794 | 637 | ||
| 795 | static struct omap_hwmod_irq_info am33xx_elm_irqs[] = { | ||
| 796 | { .irq = 4 + OMAP_INTC_START, }, | ||
| 797 | { .irq = -1 }, | ||
| 798 | }; | ||
| 799 | |||
| 800 | static struct omap_hwmod am33xx_elm_hwmod = { | 638 | static struct omap_hwmod am33xx_elm_hwmod = { |
| 801 | .name = "elm", | 639 | .name = "elm", |
| 802 | .class = &am33xx_elm_hwmod_class, | 640 | .class = &am33xx_elm_hwmod_class, |
| 803 | .clkdm_name = "l4ls_clkdm", | 641 | .clkdm_name = "l4ls_clkdm", |
| 804 | .mpu_irqs = am33xx_elm_irqs, | ||
| 805 | .main_clk = "l4ls_gclk", | 642 | .main_clk = "l4ls_gclk", |
| 806 | .prcm = { | 643 | .prcm = { |
| 807 | .omap4 = { | 644 | .omap4 = { |
| @@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = { | |||
| 854 | }; | 691 | }; |
| 855 | 692 | ||
| 856 | /* ecap0 */ | 693 | /* ecap0 */ |
| 857 | static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { | ||
| 858 | { .irq = 31 + OMAP_INTC_START, }, | ||
| 859 | { .irq = -1 }, | ||
| 860 | }; | ||
| 861 | |||
| 862 | static struct omap_hwmod am33xx_ecap0_hwmod = { | 694 | static struct omap_hwmod am33xx_ecap0_hwmod = { |
| 863 | .name = "ecap0", | 695 | .name = "ecap0", |
| 864 | .class = &am33xx_ecap_hwmod_class, | 696 | .class = &am33xx_ecap_hwmod_class, |
| 865 | .clkdm_name = "l4ls_clkdm", | 697 | .clkdm_name = "l4ls_clkdm", |
| 866 | .mpu_irqs = am33xx_ecap0_irqs, | ||
| 867 | .main_clk = "l4ls_gclk", | 698 | .main_clk = "l4ls_gclk", |
| 868 | }; | 699 | }; |
| 869 | 700 | ||
| 870 | /* eqep0 */ | 701 | /* eqep0 */ |
| 871 | static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = { | ||
| 872 | { .irq = 79 + OMAP_INTC_START, }, | ||
| 873 | { .irq = -1 }, | ||
| 874 | }; | ||
| 875 | |||
| 876 | static struct omap_hwmod am33xx_eqep0_hwmod = { | 702 | static struct omap_hwmod am33xx_eqep0_hwmod = { |
| 877 | .name = "eqep0", | 703 | .name = "eqep0", |
| 878 | .class = &am33xx_eqep_hwmod_class, | 704 | .class = &am33xx_eqep_hwmod_class, |
| 879 | .clkdm_name = "l4ls_clkdm", | 705 | .clkdm_name = "l4ls_clkdm", |
| 880 | .mpu_irqs = am33xx_eqep0_irqs, | ||
| 881 | .main_clk = "l4ls_gclk", | 706 | .main_clk = "l4ls_gclk", |
| 882 | }; | 707 | }; |
| 883 | 708 | ||
| 884 | /* ehrpwm0 */ | 709 | /* ehrpwm0 */ |
| 885 | static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { | ||
| 886 | { .name = "int", .irq = 86 + OMAP_INTC_START, }, | ||
| 887 | { .name = "tzint", .irq = 58 + OMAP_INTC_START, }, | ||
| 888 | { .irq = -1 }, | ||
| 889 | }; | ||
| 890 | |||
| 891 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { | 710 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { |
| 892 | .name = "ehrpwm0", | 711 | .name = "ehrpwm0", |
| 893 | .class = &am33xx_ehrpwm_hwmod_class, | 712 | .class = &am33xx_ehrpwm_hwmod_class, |
| 894 | .clkdm_name = "l4ls_clkdm", | 713 | .clkdm_name = "l4ls_clkdm", |
| 895 | .mpu_irqs = am33xx_ehrpwm0_irqs, | ||
| 896 | .main_clk = "l4ls_gclk", | 714 | .main_clk = "l4ls_gclk", |
| 897 | }; | 715 | }; |
| 898 | 716 | ||
| @@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = { | |||
| 911 | }; | 729 | }; |
| 912 | 730 | ||
| 913 | /* ecap1 */ | 731 | /* ecap1 */ |
| 914 | static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = { | ||
| 915 | { .irq = 47 + OMAP_INTC_START, }, | ||
| 916 | { .irq = -1 }, | ||
| 917 | }; | ||
| 918 | |||
| 919 | static struct omap_hwmod am33xx_ecap1_hwmod = { | 732 | static struct omap_hwmod am33xx_ecap1_hwmod = { |
| 920 | .name = "ecap1", | 733 | .name = "ecap1", |
| 921 | .class = &am33xx_ecap_hwmod_class, | 734 | .class = &am33xx_ecap_hwmod_class, |
| 922 | .clkdm_name = "l4ls_clkdm", | 735 | .clkdm_name = "l4ls_clkdm", |
| 923 | .mpu_irqs = am33xx_ecap1_irqs, | ||
| 924 | .main_clk = "l4ls_gclk", | 736 | .main_clk = "l4ls_gclk", |
| 925 | }; | 737 | }; |
| 926 | 738 | ||
| 927 | /* eqep1 */ | 739 | /* eqep1 */ |
| 928 | static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = { | ||
| 929 | { .irq = 88 + OMAP_INTC_START, }, | ||
| 930 | { .irq = -1 }, | ||
| 931 | }; | ||
| 932 | |||
| 933 | static struct omap_hwmod am33xx_eqep1_hwmod = { | 740 | static struct omap_hwmod am33xx_eqep1_hwmod = { |
| 934 | .name = "eqep1", | 741 | .name = "eqep1", |
| 935 | .class = &am33xx_eqep_hwmod_class, | 742 | .class = &am33xx_eqep_hwmod_class, |
| 936 | .clkdm_name = "l4ls_clkdm", | 743 | .clkdm_name = "l4ls_clkdm", |
| 937 | .mpu_irqs = am33xx_eqep1_irqs, | ||
| 938 | .main_clk = "l4ls_gclk", | 744 | .main_clk = "l4ls_gclk", |
| 939 | }; | 745 | }; |
| 940 | 746 | ||
| 941 | /* ehrpwm1 */ | 747 | /* ehrpwm1 */ |
| 942 | static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { | ||
| 943 | { .name = "int", .irq = 87 + OMAP_INTC_START, }, | ||
| 944 | { .name = "tzint", .irq = 59 + OMAP_INTC_START, }, | ||
| 945 | { .irq = -1 }, | ||
| 946 | }; | ||
| 947 | |||
| 948 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { | 748 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { |
| 949 | .name = "ehrpwm1", | 749 | .name = "ehrpwm1", |
| 950 | .class = &am33xx_ehrpwm_hwmod_class, | 750 | .class = &am33xx_ehrpwm_hwmod_class, |
| 951 | .clkdm_name = "l4ls_clkdm", | 751 | .clkdm_name = "l4ls_clkdm", |
| 952 | .mpu_irqs = am33xx_ehrpwm1_irqs, | ||
| 953 | .main_clk = "l4ls_gclk", | 752 | .main_clk = "l4ls_gclk", |
| 954 | }; | 753 | }; |
| 955 | 754 | ||
| @@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = { | |||
| 968 | }; | 767 | }; |
| 969 | 768 | ||
| 970 | /* ecap2 */ | 769 | /* ecap2 */ |
| 971 | static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = { | ||
| 972 | { .irq = 61 + OMAP_INTC_START, }, | ||
| 973 | { .irq = -1 }, | ||
| 974 | }; | ||
| 975 | |||
| 976 | static struct omap_hwmod am33xx_ecap2_hwmod = { | 770 | static struct omap_hwmod am33xx_ecap2_hwmod = { |
| 977 | .name = "ecap2", | 771 | .name = "ecap2", |
| 978 | .class = &am33xx_ecap_hwmod_class, | 772 | .class = &am33xx_ecap_hwmod_class, |
| 979 | .clkdm_name = "l4ls_clkdm", | 773 | .clkdm_name = "l4ls_clkdm", |
| 980 | .mpu_irqs = am33xx_ecap2_irqs, | ||
| 981 | .main_clk = "l4ls_gclk", | 774 | .main_clk = "l4ls_gclk", |
| 982 | }; | 775 | }; |
| 983 | 776 | ||
| 984 | /* eqep2 */ | 777 | /* eqep2 */ |
| 985 | static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = { | ||
| 986 | { .irq = 89 + OMAP_INTC_START, }, | ||
| 987 | { .irq = -1 }, | ||
| 988 | }; | ||
| 989 | |||
| 990 | static struct omap_hwmod am33xx_eqep2_hwmod = { | 778 | static struct omap_hwmod am33xx_eqep2_hwmod = { |
| 991 | .name = "eqep2", | 779 | .name = "eqep2", |
| 992 | .class = &am33xx_eqep_hwmod_class, | 780 | .class = &am33xx_eqep_hwmod_class, |
| 993 | .clkdm_name = "l4ls_clkdm", | 781 | .clkdm_name = "l4ls_clkdm", |
| 994 | .mpu_irqs = am33xx_eqep2_irqs, | ||
| 995 | .main_clk = "l4ls_gclk", | 782 | .main_clk = "l4ls_gclk", |
| 996 | }; | 783 | }; |
| 997 | 784 | ||
| 998 | /* ehrpwm2 */ | 785 | /* ehrpwm2 */ |
| 999 | static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { | ||
| 1000 | { .name = "int", .irq = 39 + OMAP_INTC_START, }, | ||
| 1001 | { .name = "tzint", .irq = 60 + OMAP_INTC_START, }, | ||
| 1002 | { .irq = -1 }, | ||
| 1003 | }; | ||
| 1004 | |||
| 1005 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { | 786 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { |
| 1006 | .name = "ehrpwm2", | 787 | .name = "ehrpwm2", |
| 1007 | .class = &am33xx_ehrpwm_hwmod_class, | 788 | .class = &am33xx_ehrpwm_hwmod_class, |
| 1008 | .clkdm_name = "l4ls_clkdm", | 789 | .clkdm_name = "l4ls_clkdm", |
| 1009 | .mpu_irqs = am33xx_ehrpwm2_irqs, | ||
| 1010 | .main_clk = "l4ls_gclk", | 790 | .main_clk = "l4ls_gclk", |
| 1011 | }; | 791 | }; |
| 1012 | 792 | ||
| @@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | |||
| 1041 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | 821 | { .role = "dbclk", .clk = "gpio0_dbclk" }, |
| 1042 | }; | 822 | }; |
| 1043 | 823 | ||
| 1044 | static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = { | ||
| 1045 | { .irq = 96 + OMAP_INTC_START, }, | ||
| 1046 | { .irq = -1 }, | ||
| 1047 | }; | ||
| 1048 | |||
| 1049 | static struct omap_hwmod am33xx_gpio0_hwmod = { | 824 | static struct omap_hwmod am33xx_gpio0_hwmod = { |
| 1050 | .name = "gpio1", | 825 | .name = "gpio1", |
| 1051 | .class = &am33xx_gpio_hwmod_class, | 826 | .class = &am33xx_gpio_hwmod_class, |
| 1052 | .clkdm_name = "l4_wkup_clkdm", | 827 | .clkdm_name = "l4_wkup_clkdm", |
| 1053 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 828 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1054 | .mpu_irqs = am33xx_gpio0_irqs, | ||
| 1055 | .main_clk = "dpll_core_m4_div2_ck", | 829 | .main_clk = "dpll_core_m4_div2_ck", |
| 1056 | .prcm = { | 830 | .prcm = { |
| 1057 | .omap4 = { | 831 | .omap4 = { |
| @@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = { | |||
| 1065 | }; | 839 | }; |
| 1066 | 840 | ||
| 1067 | /* gpio1 */ | 841 | /* gpio1 */ |
| 1068 | static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = { | ||
| 1069 | { .irq = 98 + OMAP_INTC_START, }, | ||
| 1070 | { .irq = -1 }, | ||
| 1071 | }; | ||
| 1072 | |||
| 1073 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | 842 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
| 1074 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | 843 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
| 1075 | }; | 844 | }; |
| @@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { | |||
| 1079 | .class = &am33xx_gpio_hwmod_class, | 848 | .class = &am33xx_gpio_hwmod_class, |
| 1080 | .clkdm_name = "l4ls_clkdm", | 849 | .clkdm_name = "l4ls_clkdm", |
| 1081 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 850 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1082 | .mpu_irqs = am33xx_gpio1_irqs, | ||
| 1083 | .main_clk = "l4ls_gclk", | 851 | .main_clk = "l4ls_gclk", |
| 1084 | .prcm = { | 852 | .prcm = { |
| 1085 | .omap4 = { | 853 | .omap4 = { |
| @@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { | |||
| 1093 | }; | 861 | }; |
| 1094 | 862 | ||
| 1095 | /* gpio2 */ | 863 | /* gpio2 */ |
| 1096 | static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = { | ||
| 1097 | { .irq = 32 + OMAP_INTC_START, }, | ||
| 1098 | { .irq = -1 }, | ||
| 1099 | }; | ||
| 1100 | |||
| 1101 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | 864 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
| 1102 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | 865 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
| 1103 | }; | 866 | }; |
| @@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = { | |||
| 1107 | .class = &am33xx_gpio_hwmod_class, | 870 | .class = &am33xx_gpio_hwmod_class, |
| 1108 | .clkdm_name = "l4ls_clkdm", | 871 | .clkdm_name = "l4ls_clkdm", |
| 1109 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 872 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1110 | .mpu_irqs = am33xx_gpio2_irqs, | ||
| 1111 | .main_clk = "l4ls_gclk", | 873 | .main_clk = "l4ls_gclk", |
| 1112 | .prcm = { | 874 | .prcm = { |
| 1113 | .omap4 = { | 875 | .omap4 = { |
| @@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = { | |||
| 1121 | }; | 883 | }; |
| 1122 | 884 | ||
| 1123 | /* gpio3 */ | 885 | /* gpio3 */ |
| 1124 | static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = { | ||
| 1125 | { .irq = 62 + OMAP_INTC_START, }, | ||
| 1126 | { .irq = -1 }, | ||
| 1127 | }; | ||
| 1128 | |||
| 1129 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | 886 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
| 1130 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | 887 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
| 1131 | }; | 888 | }; |
| @@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = { | |||
| 1135 | .class = &am33xx_gpio_hwmod_class, | 892 | .class = &am33xx_gpio_hwmod_class, |
| 1136 | .clkdm_name = "l4ls_clkdm", | 893 | .clkdm_name = "l4ls_clkdm", |
| 1137 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 894 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1138 | .mpu_irqs = am33xx_gpio3_irqs, | ||
| 1139 | .main_clk = "l4ls_gclk", | 895 | .main_clk = "l4ls_gclk", |
| 1140 | .prcm = { | 896 | .prcm = { |
| 1141 | .omap4 = { | 897 | .omap4 = { |
| @@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | |||
| 1164 | .sysc = &gpmc_sysc, | 920 | .sysc = &gpmc_sysc, |
| 1165 | }; | 921 | }; |
| 1166 | 922 | ||
| 1167 | static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = { | ||
| 1168 | { .irq = 100 + OMAP_INTC_START, }, | ||
| 1169 | { .irq = -1 }, | ||
| 1170 | }; | ||
| 1171 | |||
| 1172 | static struct omap_hwmod am33xx_gpmc_hwmod = { | 923 | static struct omap_hwmod am33xx_gpmc_hwmod = { |
| 1173 | .name = "gpmc", | 924 | .name = "gpmc", |
| 1174 | .class = &am33xx_gpmc_hwmod_class, | 925 | .class = &am33xx_gpmc_hwmod_class, |
| 1175 | .clkdm_name = "l3s_clkdm", | 926 | .clkdm_name = "l3s_clkdm", |
| 1176 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 927 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 1177 | .mpu_irqs = am33xx_gpmc_irqs, | ||
| 1178 | .main_clk = "l3s_gclk", | 928 | .main_clk = "l3s_gclk", |
| 1179 | .prcm = { | 929 | .prcm = { |
| 1180 | .omap4 = { | 930 | .omap4 = { |
| @@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { | |||
| 1208 | }; | 958 | }; |
| 1209 | 959 | ||
| 1210 | /* i2c1 */ | 960 | /* i2c1 */ |
| 1211 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | ||
| 1212 | { .irq = 70 + OMAP_INTC_START, }, | ||
| 1213 | { .irq = -1 }, | ||
| 1214 | }; | ||
| 1215 | |||
| 1216 | static struct omap_hwmod_dma_info i2c1_edma_reqs[] = { | ||
| 1217 | { .name = "tx", .dma_req = 0, }, | ||
| 1218 | { .name = "rx", .dma_req = 0, }, | ||
| 1219 | { .dma_req = -1 } | ||
| 1220 | }; | ||
| 1221 | |||
| 1222 | static struct omap_hwmod am33xx_i2c1_hwmod = { | 961 | static struct omap_hwmod am33xx_i2c1_hwmod = { |
| 1223 | .name = "i2c1", | 962 | .name = "i2c1", |
| 1224 | .class = &i2c_class, | 963 | .class = &i2c_class, |
| 1225 | .clkdm_name = "l4_wkup_clkdm", | 964 | .clkdm_name = "l4_wkup_clkdm", |
| 1226 | .mpu_irqs = i2c1_mpu_irqs, | ||
| 1227 | .sdma_reqs = i2c1_edma_reqs, | ||
| 1228 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 965 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1229 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | 966 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", |
| 1230 | .prcm = { | 967 | .prcm = { |
| @@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = { | |||
| 1237 | }; | 974 | }; |
| 1238 | 975 | ||
| 1239 | /* i2c1 */ | 976 | /* i2c1 */ |
| 1240 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | ||
| 1241 | { .irq = 71 + OMAP_INTC_START, }, | ||
| 1242 | { .irq = -1 }, | ||
| 1243 | }; | ||
| 1244 | |||
| 1245 | static struct omap_hwmod_dma_info i2c2_edma_reqs[] = { | ||
| 1246 | { .name = "tx", .dma_req = 0, }, | ||
| 1247 | { .name = "rx", .dma_req = 0, }, | ||
| 1248 | { .dma_req = -1 } | ||
| 1249 | }; | ||
| 1250 | |||
| 1251 | static struct omap_hwmod am33xx_i2c2_hwmod = { | 977 | static struct omap_hwmod am33xx_i2c2_hwmod = { |
| 1252 | .name = "i2c2", | 978 | .name = "i2c2", |
| 1253 | .class = &i2c_class, | 979 | .class = &i2c_class, |
| 1254 | .clkdm_name = "l4ls_clkdm", | 980 | .clkdm_name = "l4ls_clkdm", |
| 1255 | .mpu_irqs = i2c2_mpu_irqs, | ||
| 1256 | .sdma_reqs = i2c2_edma_reqs, | ||
| 1257 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 981 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1258 | .main_clk = "dpll_per_m2_div4_ck", | 982 | .main_clk = "dpll_per_m2_div4_ck", |
| 1259 | .prcm = { | 983 | .prcm = { |
| @@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = { | |||
| 1266 | }; | 990 | }; |
| 1267 | 991 | ||
| 1268 | /* i2c3 */ | 992 | /* i2c3 */ |
| 1269 | static struct omap_hwmod_dma_info i2c3_edma_reqs[] = { | ||
| 1270 | { .name = "tx", .dma_req = 0, }, | ||
| 1271 | { .name = "rx", .dma_req = 0, }, | ||
| 1272 | { .dma_req = -1 } | ||
| 1273 | }; | ||
| 1274 | |||
| 1275 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | ||
| 1276 | { .irq = 30 + OMAP_INTC_START, }, | ||
| 1277 | { .irq = -1 }, | ||
| 1278 | }; | ||
| 1279 | |||
| 1280 | static struct omap_hwmod am33xx_i2c3_hwmod = { | 993 | static struct omap_hwmod am33xx_i2c3_hwmod = { |
| 1281 | .name = "i2c3", | 994 | .name = "i2c3", |
| 1282 | .class = &i2c_class, | 995 | .class = &i2c_class, |
| 1283 | .clkdm_name = "l4ls_clkdm", | 996 | .clkdm_name = "l4ls_clkdm", |
| 1284 | .mpu_irqs = i2c3_mpu_irqs, | ||
| 1285 | .sdma_reqs = i2c3_edma_reqs, | ||
| 1286 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 997 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1287 | .main_clk = "dpll_per_m2_div4_ck", | 998 | .main_clk = "dpll_per_m2_div4_ck", |
| 1288 | .prcm = { | 999 | .prcm = { |
| @@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { | |||
| 1309 | .sysc = &lcdc_sysc, | 1020 | .sysc = &lcdc_sysc, |
| 1310 | }; | 1021 | }; |
| 1311 | 1022 | ||
| 1312 | static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = { | ||
| 1313 | { .irq = 36 + OMAP_INTC_START, }, | ||
| 1314 | { .irq = -1 }, | ||
| 1315 | }; | ||
| 1316 | |||
| 1317 | static struct omap_hwmod am33xx_lcdc_hwmod = { | 1023 | static struct omap_hwmod am33xx_lcdc_hwmod = { |
| 1318 | .name = "lcdc", | 1024 | .name = "lcdc", |
| 1319 | .class = &am33xx_lcdc_hwmod_class, | 1025 | .class = &am33xx_lcdc_hwmod_class, |
| 1320 | .clkdm_name = "lcdc_clkdm", | 1026 | .clkdm_name = "lcdc_clkdm", |
| 1321 | .mpu_irqs = am33xx_lcdc_irqs, | ||
| 1322 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | 1027 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 1323 | .main_clk = "lcd_gclk", | 1028 | .main_clk = "lcd_gclk", |
| 1324 | .prcm = { | 1029 | .prcm = { |
| @@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | |||
| 1348 | .sysc = &am33xx_mailbox_sysc, | 1053 | .sysc = &am33xx_mailbox_sysc, |
| 1349 | }; | 1054 | }; |
| 1350 | 1055 | ||
| 1351 | static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = { | ||
| 1352 | { .irq = 77 + OMAP_INTC_START, }, | ||
| 1353 | { .irq = -1 }, | ||
| 1354 | }; | ||
| 1355 | |||
| 1356 | static struct omap_hwmod am33xx_mailbox_hwmod = { | 1056 | static struct omap_hwmod am33xx_mailbox_hwmod = { |
| 1357 | .name = "mailbox", | 1057 | .name = "mailbox", |
| 1358 | .class = &am33xx_mailbox_hwmod_class, | 1058 | .class = &am33xx_mailbox_hwmod_class, |
| 1359 | .clkdm_name = "l4ls_clkdm", | 1059 | .clkdm_name = "l4ls_clkdm", |
| 1360 | .mpu_irqs = am33xx_mailbox_irqs, | ||
| 1361 | .main_clk = "l4ls_gclk", | 1060 | .main_clk = "l4ls_gclk", |
| 1362 | .prcm = { | 1061 | .prcm = { |
| 1363 | .omap4 = { | 1062 | .omap4 = { |
| @@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | |||
| 1384 | }; | 1083 | }; |
| 1385 | 1084 | ||
| 1386 | /* mcasp0 */ | 1085 | /* mcasp0 */ |
| 1387 | static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = { | ||
| 1388 | { .name = "ax", .irq = 80 + OMAP_INTC_START, }, | ||
| 1389 | { .name = "ar", .irq = 81 + OMAP_INTC_START, }, | ||
| 1390 | { .irq = -1 }, | ||
| 1391 | }; | ||
| 1392 | |||
| 1393 | static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = { | ||
| 1394 | { .name = "tx", .dma_req = 8, }, | ||
| 1395 | { .name = "rx", .dma_req = 9, }, | ||
| 1396 | { .dma_req = -1 } | ||
| 1397 | }; | ||
| 1398 | |||
| 1399 | static struct omap_hwmod am33xx_mcasp0_hwmod = { | 1086 | static struct omap_hwmod am33xx_mcasp0_hwmod = { |
| 1400 | .name = "mcasp0", | 1087 | .name = "mcasp0", |
| 1401 | .class = &am33xx_mcasp_hwmod_class, | 1088 | .class = &am33xx_mcasp_hwmod_class, |
| 1402 | .clkdm_name = "l3s_clkdm", | 1089 | .clkdm_name = "l3s_clkdm", |
| 1403 | .mpu_irqs = am33xx_mcasp0_irqs, | ||
| 1404 | .sdma_reqs = am33xx_mcasp0_edma_reqs, | ||
| 1405 | .main_clk = "mcasp0_fck", | 1090 | .main_clk = "mcasp0_fck", |
| 1406 | .prcm = { | 1091 | .prcm = { |
| 1407 | .omap4 = { | 1092 | .omap4 = { |
| @@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = { | |||
| 1412 | }; | 1097 | }; |
| 1413 | 1098 | ||
| 1414 | /* mcasp1 */ | 1099 | /* mcasp1 */ |
| 1415 | static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = { | ||
| 1416 | { .name = "ax", .irq = 82 + OMAP_INTC_START, }, | ||
| 1417 | { .name = "ar", .irq = 83 + OMAP_INTC_START, }, | ||
| 1418 | { .irq = -1 }, | ||
| 1419 | }; | ||
| 1420 | |||
| 1421 | static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = { | ||
| 1422 | { .name = "tx", .dma_req = 10, }, | ||
| 1423 | { .name = "rx", .dma_req = 11, }, | ||
| 1424 | { .dma_req = -1 } | ||
| 1425 | }; | ||
| 1426 | |||
| 1427 | static struct omap_hwmod am33xx_mcasp1_hwmod = { | 1100 | static struct omap_hwmod am33xx_mcasp1_hwmod = { |
| 1428 | .name = "mcasp1", | 1101 | .name = "mcasp1", |
| 1429 | .class = &am33xx_mcasp_hwmod_class, | 1102 | .class = &am33xx_mcasp_hwmod_class, |
| 1430 | .clkdm_name = "l3s_clkdm", | 1103 | .clkdm_name = "l3s_clkdm", |
| 1431 | .mpu_irqs = am33xx_mcasp1_irqs, | ||
| 1432 | .sdma_reqs = am33xx_mcasp1_edma_reqs, | ||
| 1433 | .main_clk = "mcasp1_fck", | 1104 | .main_clk = "mcasp1_fck", |
| 1434 | .prcm = { | 1105 | .prcm = { |
| 1435 | .omap4 = { | 1106 | .omap4 = { |
| @@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | |||
| 1457 | }; | 1128 | }; |
| 1458 | 1129 | ||
| 1459 | /* mmc0 */ | 1130 | /* mmc0 */ |
| 1460 | static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = { | ||
| 1461 | { .irq = 64 + OMAP_INTC_START, }, | ||
| 1462 | { .irq = -1 }, | ||
| 1463 | }; | ||
| 1464 | |||
| 1465 | static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = { | ||
| 1466 | { .name = "tx", .dma_req = 24, }, | ||
| 1467 | { .name = "rx", .dma_req = 25, }, | ||
| 1468 | { .dma_req = -1 } | ||
| 1469 | }; | ||
| 1470 | |||
| 1471 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { | 1131 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { |
| 1472 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | 1132 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 1473 | }; | 1133 | }; |
| @@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = { | |||
| 1476 | .name = "mmc1", | 1136 | .name = "mmc1", |
| 1477 | .class = &am33xx_mmc_hwmod_class, | 1137 | .class = &am33xx_mmc_hwmod_class, |
| 1478 | .clkdm_name = "l4ls_clkdm", | 1138 | .clkdm_name = "l4ls_clkdm", |
| 1479 | .mpu_irqs = am33xx_mmc0_irqs, | ||
| 1480 | .sdma_reqs = am33xx_mmc0_edma_reqs, | ||
| 1481 | .main_clk = "mmc_clk", | 1139 | .main_clk = "mmc_clk", |
| 1482 | .prcm = { | 1140 | .prcm = { |
| 1483 | .omap4 = { | 1141 | .omap4 = { |
| @@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = { | |||
| 1489 | }; | 1147 | }; |
| 1490 | 1148 | ||
| 1491 | /* mmc1 */ | 1149 | /* mmc1 */ |
| 1492 | static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = { | ||
| 1493 | { .irq = 28 + OMAP_INTC_START, }, | ||
| 1494 | { .irq = -1 }, | ||
| 1495 | }; | ||
| 1496 | |||
| 1497 | static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = { | ||
| 1498 | { .name = "tx", .dma_req = 2, }, | ||
| 1499 | { .name = "rx", .dma_req = 3, }, | ||
| 1500 | { .dma_req = -1 } | ||
| 1501 | }; | ||
| 1502 | |||
| 1503 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { | 1150 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { |
| 1504 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | 1151 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 1505 | }; | 1152 | }; |
| @@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = { | |||
| 1508 | .name = "mmc2", | 1155 | .name = "mmc2", |
| 1509 | .class = &am33xx_mmc_hwmod_class, | 1156 | .class = &am33xx_mmc_hwmod_class, |
| 1510 | .clkdm_name = "l4ls_clkdm", | 1157 | .clkdm_name = "l4ls_clkdm", |
| 1511 | .mpu_irqs = am33xx_mmc1_irqs, | ||
| 1512 | .sdma_reqs = am33xx_mmc1_edma_reqs, | ||
| 1513 | .main_clk = "mmc_clk", | 1158 | .main_clk = "mmc_clk", |
| 1514 | .prcm = { | 1159 | .prcm = { |
| 1515 | .omap4 = { | 1160 | .omap4 = { |
| @@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = { | |||
| 1521 | }; | 1166 | }; |
| 1522 | 1167 | ||
| 1523 | /* mmc2 */ | 1168 | /* mmc2 */ |
| 1524 | static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = { | ||
| 1525 | { .irq = 29 + OMAP_INTC_START, }, | ||
| 1526 | { .irq = -1 }, | ||
| 1527 | }; | ||
| 1528 | |||
| 1529 | static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = { | ||
| 1530 | { .name = "tx", .dma_req = 64, }, | ||
| 1531 | { .name = "rx", .dma_req = 65, }, | ||
| 1532 | { .dma_req = -1 } | ||
| 1533 | }; | ||
| 1534 | |||
| 1535 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { | 1169 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { |
| 1536 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | 1170 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 1537 | }; | 1171 | }; |
| @@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = { | |||
| 1539 | .name = "mmc3", | 1173 | .name = "mmc3", |
| 1540 | .class = &am33xx_mmc_hwmod_class, | 1174 | .class = &am33xx_mmc_hwmod_class, |
| 1541 | .clkdm_name = "l3s_clkdm", | 1175 | .clkdm_name = "l3s_clkdm", |
| 1542 | .mpu_irqs = am33xx_mmc2_irqs, | ||
| 1543 | .sdma_reqs = am33xx_mmc2_edma_reqs, | ||
| 1544 | .main_clk = "mmc_clk", | 1176 | .main_clk = "mmc_clk", |
| 1545 | .prcm = { | 1177 | .prcm = { |
| 1546 | .omap4 = { | 1178 | .omap4 = { |
| @@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | |||
| 1569 | .sysc = &am33xx_rtc_sysc, | 1201 | .sysc = &am33xx_rtc_sysc, |
| 1570 | }; | 1202 | }; |
| 1571 | 1203 | ||
| 1572 | static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = { | ||
| 1573 | { .name = "rtcint", .irq = 75 + OMAP_INTC_START, }, | ||
| 1574 | { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, }, | ||
| 1575 | { .irq = -1 }, | ||
| 1576 | }; | ||
| 1577 | |||
| 1578 | static struct omap_hwmod am33xx_rtc_hwmod = { | 1204 | static struct omap_hwmod am33xx_rtc_hwmod = { |
| 1579 | .name = "rtc", | 1205 | .name = "rtc", |
| 1580 | .class = &am33xx_rtc_hwmod_class, | 1206 | .class = &am33xx_rtc_hwmod_class, |
| 1581 | .clkdm_name = "l4_rtc_clkdm", | 1207 | .clkdm_name = "l4_rtc_clkdm", |
| 1582 | .mpu_irqs = am33xx_rtc_irqs, | ||
| 1583 | .main_clk = "clk_32768_ck", | 1208 | .main_clk = "clk_32768_ck", |
| 1584 | .prcm = { | 1209 | .prcm = { |
| 1585 | .omap4 = { | 1210 | .omap4 = { |
| @@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = { | |||
| 1608 | }; | 1233 | }; |
| 1609 | 1234 | ||
| 1610 | /* spi0 */ | 1235 | /* spi0 */ |
| 1611 | static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = { | ||
| 1612 | { .irq = 65 + OMAP_INTC_START, }, | ||
| 1613 | { .irq = -1 }, | ||
| 1614 | }; | ||
| 1615 | |||
| 1616 | static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = { | ||
| 1617 | { .name = "rx0", .dma_req = 17 }, | ||
| 1618 | { .name = "tx0", .dma_req = 16 }, | ||
| 1619 | { .name = "rx1", .dma_req = 19 }, | ||
| 1620 | { .name = "tx1", .dma_req = 18 }, | ||
| 1621 | { .dma_req = -1 } | ||
| 1622 | }; | ||
| 1623 | |||
| 1624 | static struct omap2_mcspi_dev_attr mcspi_attrib = { | 1236 | static struct omap2_mcspi_dev_attr mcspi_attrib = { |
| 1625 | .num_chipselect = 2, | 1237 | .num_chipselect = 2, |
| 1626 | }; | 1238 | }; |
| @@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = { | |||
| 1628 | .name = "spi0", | 1240 | .name = "spi0", |
| 1629 | .class = &am33xx_spi_hwmod_class, | 1241 | .class = &am33xx_spi_hwmod_class, |
| 1630 | .clkdm_name = "l4ls_clkdm", | 1242 | .clkdm_name = "l4ls_clkdm", |
| 1631 | .mpu_irqs = am33xx_spi0_irqs, | ||
| 1632 | .sdma_reqs = am33xx_mcspi0_edma_reqs, | ||
| 1633 | .main_clk = "dpll_per_m2_div4_ck", | 1243 | .main_clk = "dpll_per_m2_div4_ck", |
| 1634 | .prcm = { | 1244 | .prcm = { |
| 1635 | .omap4 = { | 1245 | .omap4 = { |
| @@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = { | |||
| 1641 | }; | 1251 | }; |
| 1642 | 1252 | ||
| 1643 | /* spi1 */ | 1253 | /* spi1 */ |
| 1644 | static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = { | ||
| 1645 | { .irq = 125 + OMAP_INTC_START, }, | ||
| 1646 | { .irq = -1 }, | ||
| 1647 | }; | ||
| 1648 | |||
| 1649 | static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = { | ||
| 1650 | { .name = "rx0", .dma_req = 43 }, | ||
| 1651 | { .name = "tx0", .dma_req = 42 }, | ||
| 1652 | { .name = "rx1", .dma_req = 45 }, | ||
| 1653 | { .name = "tx1", .dma_req = 44 }, | ||
| 1654 | { .dma_req = -1 } | ||
| 1655 | }; | ||
| 1656 | |||
| 1657 | static struct omap_hwmod am33xx_spi1_hwmod = { | 1254 | static struct omap_hwmod am33xx_spi1_hwmod = { |
| 1658 | .name = "spi1", | 1255 | .name = "spi1", |
| 1659 | .class = &am33xx_spi_hwmod_class, | 1256 | .class = &am33xx_spi_hwmod_class, |
| 1660 | .clkdm_name = "l4ls_clkdm", | 1257 | .clkdm_name = "l4ls_clkdm", |
| 1661 | .mpu_irqs = am33xx_spi1_irqs, | ||
| 1662 | .sdma_reqs = am33xx_mcspi1_edma_reqs, | ||
| 1663 | .main_clk = "dpll_per_m2_div4_ck", | 1258 | .main_clk = "dpll_per_m2_div4_ck", |
| 1664 | .prcm = { | 1259 | .prcm = { |
| 1665 | .omap4 = { | 1260 | .omap4 = { |
| @@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | |||
| 1725 | .sysc = &am33xx_timer1ms_sysc, | 1320 | .sysc = &am33xx_timer1ms_sysc, |
| 1726 | }; | 1321 | }; |
| 1727 | 1322 | ||
| 1728 | static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = { | ||
| 1729 | { .irq = 67 + OMAP_INTC_START, }, | ||
| 1730 | { .irq = -1 }, | ||
| 1731 | }; | ||
| 1732 | |||
| 1733 | static struct omap_hwmod am33xx_timer1_hwmod = { | 1323 | static struct omap_hwmod am33xx_timer1_hwmod = { |
| 1734 | .name = "timer1", | 1324 | .name = "timer1", |
| 1735 | .class = &am33xx_timer1ms_hwmod_class, | 1325 | .class = &am33xx_timer1ms_hwmod_class, |
| 1736 | .clkdm_name = "l4_wkup_clkdm", | 1326 | .clkdm_name = "l4_wkup_clkdm", |
| 1737 | .mpu_irqs = am33xx_timer1_irqs, | ||
| 1738 | .main_clk = "timer1_fck", | 1327 | .main_clk = "timer1_fck", |
| 1739 | .prcm = { | 1328 | .prcm = { |
| 1740 | .omap4 = { | 1329 | .omap4 = { |
| @@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = { | |||
| 1744 | }, | 1333 | }, |
| 1745 | }; | 1334 | }; |
| 1746 | 1335 | ||
| 1747 | static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = { | ||
| 1748 | { .irq = 68 + OMAP_INTC_START, }, | ||
| 1749 | { .irq = -1 }, | ||
| 1750 | }; | ||
| 1751 | |||
| 1752 | static struct omap_hwmod am33xx_timer2_hwmod = { | 1336 | static struct omap_hwmod am33xx_timer2_hwmod = { |
| 1753 | .name = "timer2", | 1337 | .name = "timer2", |
| 1754 | .class = &am33xx_timer_hwmod_class, | 1338 | .class = &am33xx_timer_hwmod_class, |
| 1755 | .clkdm_name = "l4ls_clkdm", | 1339 | .clkdm_name = "l4ls_clkdm", |
| 1756 | .mpu_irqs = am33xx_timer2_irqs, | ||
| 1757 | .main_clk = "timer2_fck", | 1340 | .main_clk = "timer2_fck", |
| 1758 | .prcm = { | 1341 | .prcm = { |
| 1759 | .omap4 = { | 1342 | .omap4 = { |
| @@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = { | |||
| 1763 | }, | 1346 | }, |
| 1764 | }; | 1347 | }; |
| 1765 | 1348 | ||
| 1766 | static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = { | ||
| 1767 | { .irq = 69 + OMAP_INTC_START, }, | ||
| 1768 | { .irq = -1 }, | ||
| 1769 | }; | ||
| 1770 | |||
| 1771 | static struct omap_hwmod am33xx_timer3_hwmod = { | 1349 | static struct omap_hwmod am33xx_timer3_hwmod = { |
| 1772 | .name = "timer3", | 1350 | .name = "timer3", |
| 1773 | .class = &am33xx_timer_hwmod_class, | 1351 | .class = &am33xx_timer_hwmod_class, |
| 1774 | .clkdm_name = "l4ls_clkdm", | 1352 | .clkdm_name = "l4ls_clkdm", |
| 1775 | .mpu_irqs = am33xx_timer3_irqs, | ||
| 1776 | .main_clk = "timer3_fck", | 1353 | .main_clk = "timer3_fck", |
| 1777 | .prcm = { | 1354 | .prcm = { |
| 1778 | .omap4 = { | 1355 | .omap4 = { |
| @@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = { | |||
| 1782 | }, | 1359 | }, |
| 1783 | }; | 1360 | }; |
| 1784 | 1361 | ||
| 1785 | static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = { | ||
| 1786 | { .irq = 92 + OMAP_INTC_START, }, | ||
| 1787 | { .irq = -1 }, | ||
| 1788 | }; | ||
| 1789 | |||
| 1790 | static struct omap_hwmod am33xx_timer4_hwmod = { | 1362 | static struct omap_hwmod am33xx_timer4_hwmod = { |
| 1791 | .name = "timer4", | 1363 | .name = "timer4", |
| 1792 | .class = &am33xx_timer_hwmod_class, | 1364 | .class = &am33xx_timer_hwmod_class, |
| 1793 | .clkdm_name = "l4ls_clkdm", | 1365 | .clkdm_name = "l4ls_clkdm", |
| 1794 | .mpu_irqs = am33xx_timer4_irqs, | ||
| 1795 | .main_clk = "timer4_fck", | 1366 | .main_clk = "timer4_fck", |
| 1796 | .prcm = { | 1367 | .prcm = { |
| 1797 | .omap4 = { | 1368 | .omap4 = { |
| @@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = { | |||
| 1801 | }, | 1372 | }, |
| 1802 | }; | 1373 | }; |
| 1803 | 1374 | ||
| 1804 | static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = { | ||
| 1805 | { .irq = 93 + OMAP_INTC_START, }, | ||
| 1806 | { .irq = -1 }, | ||
| 1807 | }; | ||
| 1808 | |||
| 1809 | static struct omap_hwmod am33xx_timer5_hwmod = { | 1375 | static struct omap_hwmod am33xx_timer5_hwmod = { |
| 1810 | .name = "timer5", | 1376 | .name = "timer5", |
| 1811 | .class = &am33xx_timer_hwmod_class, | 1377 | .class = &am33xx_timer_hwmod_class, |
| 1812 | .clkdm_name = "l4ls_clkdm", | 1378 | .clkdm_name = "l4ls_clkdm", |
| 1813 | .mpu_irqs = am33xx_timer5_irqs, | ||
| 1814 | .main_clk = "timer5_fck", | 1379 | .main_clk = "timer5_fck", |
| 1815 | .prcm = { | 1380 | .prcm = { |
| 1816 | .omap4 = { | 1381 | .omap4 = { |
| @@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = { | |||
| 1820 | }, | 1385 | }, |
| 1821 | }; | 1386 | }; |
| 1822 | 1387 | ||
| 1823 | static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = { | ||
| 1824 | { .irq = 94 + OMAP_INTC_START, }, | ||
| 1825 | { .irq = -1 }, | ||
| 1826 | }; | ||
| 1827 | |||
| 1828 | static struct omap_hwmod am33xx_timer6_hwmod = { | 1388 | static struct omap_hwmod am33xx_timer6_hwmod = { |
| 1829 | .name = "timer6", | 1389 | .name = "timer6", |
| 1830 | .class = &am33xx_timer_hwmod_class, | 1390 | .class = &am33xx_timer_hwmod_class, |
| 1831 | .clkdm_name = "l4ls_clkdm", | 1391 | .clkdm_name = "l4ls_clkdm", |
| 1832 | .mpu_irqs = am33xx_timer6_irqs, | ||
| 1833 | .main_clk = "timer6_fck", | 1392 | .main_clk = "timer6_fck", |
| 1834 | .prcm = { | 1393 | .prcm = { |
| 1835 | .omap4 = { | 1394 | .omap4 = { |
| @@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = { | |||
| 1839 | }, | 1398 | }, |
| 1840 | }; | 1399 | }; |
| 1841 | 1400 | ||
| 1842 | static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = { | ||
| 1843 | { .irq = 95 + OMAP_INTC_START, }, | ||
| 1844 | { .irq = -1 }, | ||
| 1845 | }; | ||
| 1846 | |||
| 1847 | static struct omap_hwmod am33xx_timer7_hwmod = { | 1401 | static struct omap_hwmod am33xx_timer7_hwmod = { |
| 1848 | .name = "timer7", | 1402 | .name = "timer7", |
| 1849 | .class = &am33xx_timer_hwmod_class, | 1403 | .class = &am33xx_timer_hwmod_class, |
| 1850 | .clkdm_name = "l4ls_clkdm", | 1404 | .clkdm_name = "l4ls_clkdm", |
| 1851 | .mpu_irqs = am33xx_timer7_irqs, | ||
| 1852 | .main_clk = "timer7_fck", | 1405 | .main_clk = "timer7_fck", |
| 1853 | .prcm = { | 1406 | .prcm = { |
| 1854 | .omap4 = { | 1407 | .omap4 = { |
| @@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | |||
| 1863 | .name = "tpcc", | 1416 | .name = "tpcc", |
| 1864 | }; | 1417 | }; |
| 1865 | 1418 | ||
| 1866 | static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = { | ||
| 1867 | { .name = "edma0", .irq = 12 + OMAP_INTC_START, }, | ||
| 1868 | { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, }, | ||
| 1869 | { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, }, | ||
| 1870 | { .irq = -1 }, | ||
| 1871 | }; | ||
| 1872 | |||
| 1873 | static struct omap_hwmod am33xx_tpcc_hwmod = { | 1419 | static struct omap_hwmod am33xx_tpcc_hwmod = { |
| 1874 | .name = "tpcc", | 1420 | .name = "tpcc", |
| 1875 | .class = &am33xx_tpcc_hwmod_class, | 1421 | .class = &am33xx_tpcc_hwmod_class, |
| 1876 | .clkdm_name = "l3_clkdm", | 1422 | .clkdm_name = "l3_clkdm", |
| 1877 | .mpu_irqs = am33xx_tpcc_irqs, | ||
| 1878 | .main_clk = "l3_gclk", | 1423 | .main_clk = "l3_gclk", |
| 1879 | .prcm = { | 1424 | .prcm = { |
| 1880 | .omap4 = { | 1425 | .omap4 = { |
| @@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | |||
| 1900 | }; | 1445 | }; |
| 1901 | 1446 | ||
| 1902 | /* tptc0 */ | 1447 | /* tptc0 */ |
| 1903 | static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = { | ||
| 1904 | { .irq = 112 + OMAP_INTC_START, }, | ||
| 1905 | { .irq = -1 }, | ||
| 1906 | }; | ||
| 1907 | |||
| 1908 | static struct omap_hwmod am33xx_tptc0_hwmod = { | 1448 | static struct omap_hwmod am33xx_tptc0_hwmod = { |
| 1909 | .name = "tptc0", | 1449 | .name = "tptc0", |
| 1910 | .class = &am33xx_tptc_hwmod_class, | 1450 | .class = &am33xx_tptc_hwmod_class, |
| 1911 | .clkdm_name = "l3_clkdm", | 1451 | .clkdm_name = "l3_clkdm", |
| 1912 | .mpu_irqs = am33xx_tptc0_irqs, | ||
| 1913 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | 1452 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 1914 | .main_clk = "l3_gclk", | 1453 | .main_clk = "l3_gclk", |
| 1915 | .prcm = { | 1454 | .prcm = { |
| @@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = { | |||
| 1921 | }; | 1460 | }; |
| 1922 | 1461 | ||
| 1923 | /* tptc1 */ | 1462 | /* tptc1 */ |
| 1924 | static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = { | ||
| 1925 | { .irq = 113 + OMAP_INTC_START, }, | ||
| 1926 | { .irq = -1 }, | ||
| 1927 | }; | ||
| 1928 | |||
| 1929 | static struct omap_hwmod am33xx_tptc1_hwmod = { | 1463 | static struct omap_hwmod am33xx_tptc1_hwmod = { |
| 1930 | .name = "tptc1", | 1464 | .name = "tptc1", |
| 1931 | .class = &am33xx_tptc_hwmod_class, | 1465 | .class = &am33xx_tptc_hwmod_class, |
| 1932 | .clkdm_name = "l3_clkdm", | 1466 | .clkdm_name = "l3_clkdm", |
| 1933 | .mpu_irqs = am33xx_tptc1_irqs, | ||
| 1934 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | 1467 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
| 1935 | .main_clk = "l3_gclk", | 1468 | .main_clk = "l3_gclk", |
| 1936 | .prcm = { | 1469 | .prcm = { |
| @@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = { | |||
| 1942 | }; | 1475 | }; |
| 1943 | 1476 | ||
| 1944 | /* tptc2 */ | 1477 | /* tptc2 */ |
| 1945 | static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = { | ||
| 1946 | { .irq = 114 + OMAP_INTC_START, }, | ||
| 1947 | { .irq = -1 }, | ||
| 1948 | }; | ||
| 1949 | |||
| 1950 | static struct omap_hwmod am33xx_tptc2_hwmod = { | 1478 | static struct omap_hwmod am33xx_tptc2_hwmod = { |
| 1951 | .name = "tptc2", | 1479 | .name = "tptc2", |
| 1952 | .class = &am33xx_tptc_hwmod_class, | 1480 | .class = &am33xx_tptc_hwmod_class, |
| 1953 | .clkdm_name = "l3_clkdm", | 1481 | .clkdm_name = "l3_clkdm", |
| 1954 | .mpu_irqs = am33xx_tptc2_irqs, | ||
| 1955 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | 1482 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
| 1956 | .main_clk = "l3_gclk", | 1483 | .main_clk = "l3_gclk", |
| 1957 | .prcm = { | 1484 | .prcm = { |
| @@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = { | |||
| 1980 | }; | 1507 | }; |
| 1981 | 1508 | ||
| 1982 | /* uart1 */ | 1509 | /* uart1 */ |
| 1983 | static struct omap_hwmod_dma_info uart1_edma_reqs[] = { | ||
| 1984 | { .name = "tx", .dma_req = 26, }, | ||
| 1985 | { .name = "rx", .dma_req = 27, }, | ||
| 1986 | { .dma_req = -1 } | ||
| 1987 | }; | ||
| 1988 | |||
| 1989 | static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = { | ||
| 1990 | { .irq = 72 + OMAP_INTC_START, }, | ||
| 1991 | { .irq = -1 }, | ||
| 1992 | }; | ||
| 1993 | |||
| 1994 | static struct omap_hwmod am33xx_uart1_hwmod = { | 1510 | static struct omap_hwmod am33xx_uart1_hwmod = { |
| 1995 | .name = "uart1", | 1511 | .name = "uart1", |
| 1996 | .class = &uart_class, | 1512 | .class = &uart_class, |
| 1997 | .clkdm_name = "l4_wkup_clkdm", | 1513 | .clkdm_name = "l4_wkup_clkdm", |
| 1998 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 1514 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 1999 | .mpu_irqs = am33xx_uart1_irqs, | ||
| 2000 | .sdma_reqs = uart1_edma_reqs, | ||
| 2001 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | 1515 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", |
| 2002 | .prcm = { | 1516 | .prcm = { |
| 2003 | .omap4 = { | 1517 | .omap4 = { |
| @@ -2007,25 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = { | |||
| 2007 | }, | 1521 | }, |
| 2008 | }; | 1522 | }; |
| 2009 | 1523 | ||
| 2010 | /* uart2 */ | ||
| 2011 | static struct omap_hwmod_dma_info uart2_edma_reqs[] = { | ||
| 2012 | { .name = "tx", .dma_req = 28, }, | ||
| 2013 | { .name = "rx", .dma_req = 29, }, | ||
| 2014 | { .dma_req = -1 } | ||
| 2015 | }; | ||
| 2016 | |||
| 2017 | static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { | ||
| 2018 | { .irq = 73 + OMAP_INTC_START, }, | ||
| 2019 | { .irq = -1 }, | ||
| 2020 | }; | ||
| 2021 | |||
| 2022 | static struct omap_hwmod am33xx_uart2_hwmod = { | 1524 | static struct omap_hwmod am33xx_uart2_hwmod = { |
| 2023 | .name = "uart2", | 1525 | .name = "uart2", |
| 2024 | .class = &uart_class, | 1526 | .class = &uart_class, |
| 2025 | .clkdm_name = "l4ls_clkdm", | 1527 | .clkdm_name = "l4ls_clkdm", |
| 2026 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 1528 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 2027 | .mpu_irqs = am33xx_uart2_irqs, | ||
| 2028 | .sdma_reqs = uart2_edma_reqs, | ||
| 2029 | .main_clk = "dpll_per_m2_div4_ck", | 1529 | .main_clk = "dpll_per_m2_div4_ck", |
| 2030 | .prcm = { | 1530 | .prcm = { |
| 2031 | .omap4 = { | 1531 | .omap4 = { |
| @@ -2036,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = { | |||
| 2036 | }; | 1536 | }; |
| 2037 | 1537 | ||
| 2038 | /* uart3 */ | 1538 | /* uart3 */ |
| 2039 | static struct omap_hwmod_dma_info uart3_edma_reqs[] = { | ||
| 2040 | { .name = "tx", .dma_req = 30, }, | ||
| 2041 | { .name = "rx", .dma_req = 31, }, | ||
| 2042 | { .dma_req = -1 } | ||
| 2043 | }; | ||
| 2044 | |||
| 2045 | static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = { | ||
| 2046 | { .irq = 74 + OMAP_INTC_START, }, | ||
| 2047 | { .irq = -1 }, | ||
| 2048 | }; | ||
| 2049 | |||
| 2050 | static struct omap_hwmod am33xx_uart3_hwmod = { | 1539 | static struct omap_hwmod am33xx_uart3_hwmod = { |
| 2051 | .name = "uart3", | 1540 | .name = "uart3", |
| 2052 | .class = &uart_class, | 1541 | .class = &uart_class, |
| 2053 | .clkdm_name = "l4ls_clkdm", | 1542 | .clkdm_name = "l4ls_clkdm", |
| 2054 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 1543 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 2055 | .mpu_irqs = am33xx_uart3_irqs, | ||
| 2056 | .sdma_reqs = uart3_edma_reqs, | ||
| 2057 | .main_clk = "dpll_per_m2_div4_ck", | 1544 | .main_clk = "dpll_per_m2_div4_ck", |
| 2058 | .prcm = { | 1545 | .prcm = { |
| 2059 | .omap4 = { | 1546 | .omap4 = { |
| @@ -2063,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = { | |||
| 2063 | }, | 1550 | }, |
| 2064 | }; | 1551 | }; |
| 2065 | 1552 | ||
| 2066 | static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = { | ||
| 2067 | { .irq = 44 + OMAP_INTC_START, }, | ||
| 2068 | { .irq = -1 }, | ||
| 2069 | }; | ||
| 2070 | |||
| 2071 | static struct omap_hwmod am33xx_uart4_hwmod = { | 1553 | static struct omap_hwmod am33xx_uart4_hwmod = { |
| 2072 | .name = "uart4", | 1554 | .name = "uart4", |
| 2073 | .class = &uart_class, | 1555 | .class = &uart_class, |
| 2074 | .clkdm_name = "l4ls_clkdm", | 1556 | .clkdm_name = "l4ls_clkdm", |
| 2075 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 1557 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 2076 | .mpu_irqs = am33xx_uart4_irqs, | ||
| 2077 | .sdma_reqs = uart1_edma_reqs, | ||
| 2078 | .main_clk = "dpll_per_m2_div4_ck", | 1558 | .main_clk = "dpll_per_m2_div4_ck", |
| 2079 | .prcm = { | 1559 | .prcm = { |
| 2080 | .omap4 = { | 1560 | .omap4 = { |
| @@ -2084,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = { | |||
| 2084 | }, | 1564 | }, |
| 2085 | }; | 1565 | }; |
| 2086 | 1566 | ||
| 2087 | static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = { | ||
| 2088 | { .irq = 45 + OMAP_INTC_START, }, | ||
| 2089 | { .irq = -1 }, | ||
| 2090 | }; | ||
| 2091 | |||
| 2092 | static struct omap_hwmod am33xx_uart5_hwmod = { | 1567 | static struct omap_hwmod am33xx_uart5_hwmod = { |
| 2093 | .name = "uart5", | 1568 | .name = "uart5", |
| 2094 | .class = &uart_class, | 1569 | .class = &uart_class, |
| 2095 | .clkdm_name = "l4ls_clkdm", | 1570 | .clkdm_name = "l4ls_clkdm", |
| 2096 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 1571 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 2097 | .mpu_irqs = am33xx_uart5_irqs, | ||
| 2098 | .sdma_reqs = uart1_edma_reqs, | ||
| 2099 | .main_clk = "dpll_per_m2_div4_ck", | 1572 | .main_clk = "dpll_per_m2_div4_ck", |
| 2100 | .prcm = { | 1573 | .prcm = { |
| 2101 | .omap4 = { | 1574 | .omap4 = { |
| @@ -2105,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = { | |||
| 2105 | }, | 1578 | }, |
| 2106 | }; | 1579 | }; |
| 2107 | 1580 | ||
| 2108 | static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = { | ||
| 2109 | { .irq = 46 + OMAP_INTC_START, }, | ||
| 2110 | { .irq = -1 }, | ||
| 2111 | }; | ||
| 2112 | |||
| 2113 | static struct omap_hwmod am33xx_uart6_hwmod = { | 1581 | static struct omap_hwmod am33xx_uart6_hwmod = { |
| 2114 | .name = "uart6", | 1582 | .name = "uart6", |
| 2115 | .class = &uart_class, | 1583 | .class = &uart_class, |
| 2116 | .clkdm_name = "l4ls_clkdm", | 1584 | .clkdm_name = "l4ls_clkdm", |
| 2117 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 1585 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 2118 | .mpu_irqs = am33xx_uart6_irqs, | ||
| 2119 | .sdma_reqs = uart1_edma_reqs, | ||
| 2120 | .main_clk = "dpll_per_m2_div4_ck", | 1586 | .main_clk = "dpll_per_m2_div4_ck", |
| 2121 | .prcm = { | 1587 | .prcm = { |
| 2122 | .omap4 = { | 1588 | .omap4 = { |
| @@ -2180,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = { | |||
| 2180 | .sysc = &am33xx_usbhsotg_sysc, | 1646 | .sysc = &am33xx_usbhsotg_sysc, |
| 2181 | }; | 1647 | }; |
| 2182 | 1648 | ||
| 2183 | static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = { | ||
| 2184 | { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, }, | ||
| 2185 | { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, }, | ||
| 2186 | { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, }, | ||
| 2187 | { .irq = -1, }, | ||
| 2188 | }; | ||
| 2189 | |||
| 2190 | static struct omap_hwmod am33xx_usbss_hwmod = { | 1649 | static struct omap_hwmod am33xx_usbss_hwmod = { |
| 2191 | .name = "usb_otg_hs", | 1650 | .name = "usb_otg_hs", |
| 2192 | .class = &am33xx_usbotg_class, | 1651 | .class = &am33xx_usbotg_class, |
| 2193 | .clkdm_name = "l3s_clkdm", | 1652 | .clkdm_name = "l3s_clkdm", |
| 2194 | .mpu_irqs = am33xx_usbss_mpu_irqs, | ||
| 2195 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | 1653 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 2196 | .main_clk = "usbotg_fck", | 1654 | .main_clk = "usbotg_fck", |
| 2197 | .prcm = { | 1655 | .prcm = { |
| @@ -2207,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = { | |||
| 2207 | * Interfaces | 1665 | * Interfaces |
| 2208 | */ | 1666 | */ |
| 2209 | 1667 | ||
| 2210 | /* l4 fw -> emif fw */ | ||
| 2211 | static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = { | ||
| 2212 | .master = &am33xx_l4_fw_hwmod, | ||
| 2213 | .slave = &am33xx_emif_fw_hwmod, | ||
| 2214 | .clk = "l4fw_gclk", | ||
| 2215 | .user = OCP_USER_MPU, | ||
| 2216 | }; | ||
| 2217 | |||
| 2218 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { | 1668 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { |
| 2219 | { | 1669 | { |
| 2220 | .pa_start = 0x4c000000, | 1670 | .pa_start = 0x4c000000, |
| @@ -2272,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | |||
| 2272 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1722 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2273 | }; | 1723 | }; |
| 2274 | 1724 | ||
| 2275 | /* l3 s -> l4 fw */ | ||
| 2276 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = { | ||
| 2277 | .master = &am33xx_l3_s_hwmod, | ||
| 2278 | .slave = &am33xx_l4_fw_hwmod, | ||
| 2279 | .clk = "l3s_gclk", | ||
| 2280 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 2281 | }; | ||
| 2282 | |||
| 2283 | /* l3 main -> l3 instr */ | 1725 | /* l3 main -> l3 instr */ |
| 2284 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | 1726 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { |
| 2285 | .master = &am33xx_l3_main_hwmod, | 1727 | .master = &am33xx_l3_main_hwmod, |
| @@ -2329,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | |||
| 2329 | }; | 1771 | }; |
| 2330 | 1772 | ||
| 2331 | /* l4 wkup -> wkup m3 */ | 1773 | /* l4 wkup -> wkup m3 */ |
| 2332 | static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = { | ||
| 2333 | { | ||
| 2334 | .name = "umem", | ||
| 2335 | .pa_start = 0x44d00000, | ||
| 2336 | .pa_end = 0x44d00000 + SZ_16K - 1, | ||
| 2337 | .flags = ADDR_TYPE_RT | ||
| 2338 | }, | ||
| 2339 | { | ||
| 2340 | .name = "dmem", | ||
| 2341 | .pa_start = 0x44d80000, | ||
| 2342 | .pa_end = 0x44d80000 + SZ_8K - 1, | ||
| 2343 | .flags = ADDR_TYPE_RT | ||
| 2344 | }, | ||
| 2345 | { } | ||
| 2346 | }; | ||
| 2347 | |||
| 2348 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { | 1774 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { |
| 2349 | .master = &am33xx_l4_wkup_hwmod, | 1775 | .master = &am33xx_l4_wkup_hwmod, |
| 2350 | .slave = &am33xx_wkup_m3_hwmod, | 1776 | .slave = &am33xx_wkup_m3_hwmod, |
| 2351 | .clk = "dpll_core_m4_div2_ck", | 1777 | .clk = "dpll_core_m4_div2_ck", |
| 2352 | .addr = am33xx_wkup_m3_addrs, | ||
| 2353 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1778 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2354 | }; | 1779 | }; |
| 2355 | 1780 | ||
| 2356 | /* l4 hs -> pru-icss */ | 1781 | /* l4 hs -> pru-icss */ |
| 2357 | static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = { | ||
| 2358 | { | ||
| 2359 | .pa_start = 0x4a300000, | ||
| 2360 | .pa_end = 0x4a300000 + SZ_512K - 1, | ||
| 2361 | .flags = ADDR_TYPE_RT | ||
| 2362 | }, | ||
| 2363 | { } | ||
| 2364 | }; | ||
| 2365 | |||
| 2366 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { | 1782 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { |
| 2367 | .master = &am33xx_l4_hs_hwmod, | 1783 | .master = &am33xx_l4_hs_hwmod, |
| 2368 | .slave = &am33xx_pruss_hwmod, | 1784 | .slave = &am33xx_pruss_hwmod, |
| 2369 | .clk = "dpll_core_m4_ck", | 1785 | .clk = "dpll_core_m4_ck", |
| 2370 | .addr = am33xx_pruss_addrs, | ||
| 2371 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1786 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2372 | }; | 1787 | }; |
| 2373 | 1788 | ||
| 2374 | /* l3 main -> gfx */ | 1789 | /* l3 main -> gfx */ |
| 2375 | static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = { | ||
| 2376 | { | ||
| 2377 | .pa_start = 0x56000000, | ||
| 2378 | .pa_end = 0x56000000 + SZ_16M - 1, | ||
| 2379 | .flags = ADDR_TYPE_RT | ||
| 2380 | }, | ||
| 2381 | { } | ||
| 2382 | }; | ||
| 2383 | |||
| 2384 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { | 1790 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { |
| 2385 | .master = &am33xx_l3_main_hwmod, | 1791 | .master = &am33xx_l3_main_hwmod, |
| 2386 | .slave = &am33xx_gfx_hwmod, | 1792 | .slave = &am33xx_gfx_hwmod, |
| 2387 | .clk = "dpll_core_m4_ck", | 1793 | .clk = "dpll_core_m4_ck", |
| 2388 | .addr = am33xx_gfx_addrs, | ||
| 2389 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1794 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2390 | }; | 1795 | }; |
| 2391 | 1796 | ||
| 2392 | /* l4 wkup -> smartreflex0 */ | 1797 | /* l4 wkup -> smartreflex0 */ |
| 2393 | static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = { | ||
| 2394 | { | ||
| 2395 | .pa_start = 0x44e37000, | ||
| 2396 | .pa_end = 0x44e37000 + SZ_4K - 1, | ||
| 2397 | .flags = ADDR_TYPE_RT | ||
| 2398 | }, | ||
| 2399 | { } | ||
| 2400 | }; | ||
| 2401 | |||
| 2402 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { | 1798 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { |
| 2403 | .master = &am33xx_l4_wkup_hwmod, | 1799 | .master = &am33xx_l4_wkup_hwmod, |
| 2404 | .slave = &am33xx_smartreflex0_hwmod, | 1800 | .slave = &am33xx_smartreflex0_hwmod, |
| 2405 | .clk = "dpll_core_m4_div2_ck", | 1801 | .clk = "dpll_core_m4_div2_ck", |
| 2406 | .addr = am33xx_smartreflex0_addrs, | ||
| 2407 | .user = OCP_USER_MPU, | 1802 | .user = OCP_USER_MPU, |
| 2408 | }; | 1803 | }; |
| 2409 | 1804 | ||
| 2410 | /* l4 wkup -> smartreflex1 */ | 1805 | /* l4 wkup -> smartreflex1 */ |
| 2411 | static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = { | ||
| 2412 | { | ||
| 2413 | .pa_start = 0x44e39000, | ||
| 2414 | .pa_end = 0x44e39000 + SZ_4K - 1, | ||
| 2415 | .flags = ADDR_TYPE_RT | ||
| 2416 | }, | ||
| 2417 | { } | ||
| 2418 | }; | ||
| 2419 | |||
| 2420 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { | 1806 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { |
| 2421 | .master = &am33xx_l4_wkup_hwmod, | 1807 | .master = &am33xx_l4_wkup_hwmod, |
| 2422 | .slave = &am33xx_smartreflex1_hwmod, | 1808 | .slave = &am33xx_smartreflex1_hwmod, |
| 2423 | .clk = "dpll_core_m4_div2_ck", | 1809 | .clk = "dpll_core_m4_div2_ck", |
| 2424 | .addr = am33xx_smartreflex1_addrs, | ||
| 2425 | .user = OCP_USER_MPU, | 1810 | .user = OCP_USER_MPU, |
| 2426 | }; | 1811 | }; |
| 2427 | 1812 | ||
| 2428 | /* l4 wkup -> control */ | 1813 | /* l4 wkup -> control */ |
| 2429 | static struct omap_hwmod_addr_space am33xx_control_addrs[] = { | ||
| 2430 | { | ||
| 2431 | .pa_start = 0x44e10000, | ||
| 2432 | .pa_end = 0x44e10000 + SZ_8K - 1, | ||
| 2433 | .flags = ADDR_TYPE_RT | ||
| 2434 | }, | ||
| 2435 | { } | ||
| 2436 | }; | ||
| 2437 | |||
| 2438 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { | 1814 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { |
| 2439 | .master = &am33xx_l4_wkup_hwmod, | 1815 | .master = &am33xx_l4_wkup_hwmod, |
| 2440 | .slave = &am33xx_control_hwmod, | 1816 | .slave = &am33xx_control_hwmod, |
| 2441 | .clk = "dpll_core_m4_div2_ck", | 1817 | .clk = "dpll_core_m4_div2_ck", |
| 2442 | .addr = am33xx_control_addrs, | ||
| 2443 | .user = OCP_USER_MPU, | 1818 | .user = OCP_USER_MPU, |
| 2444 | }; | 1819 | }; |
| 2445 | 1820 | ||
| 2446 | /* l4 wkup -> rtc */ | 1821 | /* l4 wkup -> rtc */ |
| 2447 | static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = { | ||
| 2448 | { | ||
| 2449 | .pa_start = 0x44e3e000, | ||
| 2450 | .pa_end = 0x44e3e000 + SZ_4K - 1, | ||
| 2451 | .flags = ADDR_TYPE_RT | ||
| 2452 | }, | ||
| 2453 | { } | ||
| 2454 | }; | ||
| 2455 | |||
| 2456 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { | 1822 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { |
| 2457 | .master = &am33xx_l4_wkup_hwmod, | 1823 | .master = &am33xx_l4_wkup_hwmod, |
| 2458 | .slave = &am33xx_rtc_hwmod, | 1824 | .slave = &am33xx_rtc_hwmod, |
| 2459 | .clk = "clkdiv32k_ick", | 1825 | .clk = "clkdiv32k_ick", |
| 2460 | .addr = am33xx_rtc_addrs, | ||
| 2461 | .user = OCP_USER_MPU, | 1826 | .user = OCP_USER_MPU, |
| 2462 | }; | 1827 | }; |
| 2463 | 1828 | ||
| 2464 | /* l4 per/ls -> DCAN0 */ | 1829 | /* l4 per/ls -> DCAN0 */ |
| 2465 | static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = { | ||
| 2466 | { | ||
| 2467 | .pa_start = 0x481CC000, | ||
| 2468 | .pa_end = 0x481CC000 + SZ_4K - 1, | ||
| 2469 | .flags = ADDR_TYPE_RT | ||
| 2470 | }, | ||
| 2471 | { } | ||
| 2472 | }; | ||
| 2473 | |||
| 2474 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { | 1830 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { |
| 2475 | .master = &am33xx_l4_ls_hwmod, | 1831 | .master = &am33xx_l4_ls_hwmod, |
| 2476 | .slave = &am33xx_dcan0_hwmod, | 1832 | .slave = &am33xx_dcan0_hwmod, |
| 2477 | .clk = "l4ls_gclk", | 1833 | .clk = "l4ls_gclk", |
| 2478 | .addr = am33xx_dcan0_addrs, | ||
| 2479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1834 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2480 | }; | 1835 | }; |
| 2481 | 1836 | ||
| 2482 | /* l4 per/ls -> DCAN1 */ | 1837 | /* l4 per/ls -> DCAN1 */ |
| 2483 | static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = { | ||
| 2484 | { | ||
| 2485 | .pa_start = 0x481D0000, | ||
| 2486 | .pa_end = 0x481D0000 + SZ_4K - 1, | ||
| 2487 | .flags = ADDR_TYPE_RT | ||
| 2488 | }, | ||
| 2489 | { } | ||
| 2490 | }; | ||
| 2491 | |||
| 2492 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { | 1838 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { |
| 2493 | .master = &am33xx_l4_ls_hwmod, | 1839 | .master = &am33xx_l4_ls_hwmod, |
| 2494 | .slave = &am33xx_dcan1_hwmod, | 1840 | .slave = &am33xx_dcan1_hwmod, |
| 2495 | .clk = "l4ls_gclk", | 1841 | .clk = "l4ls_gclk", |
| 2496 | .addr = am33xx_dcan1_addrs, | ||
| 2497 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1842 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2498 | }; | 1843 | }; |
| 2499 | 1844 | ||
| 2500 | /* l4 per/ls -> GPIO2 */ | 1845 | /* l4 per/ls -> GPIO2 */ |
| 2501 | static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = { | ||
| 2502 | { | ||
| 2503 | .pa_start = 0x4804C000, | ||
| 2504 | .pa_end = 0x4804C000 + SZ_4K - 1, | ||
| 2505 | .flags = ADDR_TYPE_RT, | ||
| 2506 | }, | ||
| 2507 | { } | ||
| 2508 | }; | ||
| 2509 | |||
| 2510 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { | 1846 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { |
| 2511 | .master = &am33xx_l4_ls_hwmod, | 1847 | .master = &am33xx_l4_ls_hwmod, |
| 2512 | .slave = &am33xx_gpio1_hwmod, | 1848 | .slave = &am33xx_gpio1_hwmod, |
| 2513 | .clk = "l4ls_gclk", | 1849 | .clk = "l4ls_gclk", |
| 2514 | .addr = am33xx_gpio1_addrs, | ||
| 2515 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1850 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2516 | }; | 1851 | }; |
| 2517 | 1852 | ||
| 2518 | /* l4 per/ls -> gpio3 */ | 1853 | /* l4 per/ls -> gpio3 */ |
| 2519 | static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = { | ||
| 2520 | { | ||
| 2521 | .pa_start = 0x481AC000, | ||
| 2522 | .pa_end = 0x481AC000 + SZ_4K - 1, | ||
| 2523 | .flags = ADDR_TYPE_RT, | ||
| 2524 | }, | ||
| 2525 | { } | ||
| 2526 | }; | ||
| 2527 | |||
| 2528 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { | 1854 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { |
| 2529 | .master = &am33xx_l4_ls_hwmod, | 1855 | .master = &am33xx_l4_ls_hwmod, |
| 2530 | .slave = &am33xx_gpio2_hwmod, | 1856 | .slave = &am33xx_gpio2_hwmod, |
| 2531 | .clk = "l4ls_gclk", | 1857 | .clk = "l4ls_gclk", |
| 2532 | .addr = am33xx_gpio2_addrs, | ||
| 2533 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1858 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2534 | }; | 1859 | }; |
| 2535 | 1860 | ||
| 2536 | /* l4 per/ls -> gpio4 */ | 1861 | /* l4 per/ls -> gpio4 */ |
| 2537 | static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = { | ||
| 2538 | { | ||
| 2539 | .pa_start = 0x481AE000, | ||
| 2540 | .pa_end = 0x481AE000 + SZ_4K - 1, | ||
| 2541 | .flags = ADDR_TYPE_RT, | ||
| 2542 | }, | ||
| 2543 | { } | ||
| 2544 | }; | ||
| 2545 | |||
| 2546 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { | 1862 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { |
| 2547 | .master = &am33xx_l4_ls_hwmod, | 1863 | .master = &am33xx_l4_ls_hwmod, |
| 2548 | .slave = &am33xx_gpio3_hwmod, | 1864 | .slave = &am33xx_gpio3_hwmod, |
| 2549 | .clk = "l4ls_gclk", | 1865 | .clk = "l4ls_gclk", |
| 2550 | .addr = am33xx_gpio3_addrs, | ||
| 2551 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1866 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2552 | }; | 1867 | }; |
| 2553 | 1868 | ||
| 2554 | /* L4 WKUP -> I2C1 */ | 1869 | /* L4 WKUP -> I2C1 */ |
| 2555 | static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = { | ||
| 2556 | { | ||
| 2557 | .pa_start = 0x44E0B000, | ||
| 2558 | .pa_end = 0x44E0B000 + SZ_4K - 1, | ||
| 2559 | .flags = ADDR_TYPE_RT, | ||
| 2560 | }, | ||
| 2561 | { } | ||
| 2562 | }; | ||
| 2563 | |||
| 2564 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { | 1870 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { |
| 2565 | .master = &am33xx_l4_wkup_hwmod, | 1871 | .master = &am33xx_l4_wkup_hwmod, |
| 2566 | .slave = &am33xx_i2c1_hwmod, | 1872 | .slave = &am33xx_i2c1_hwmod, |
| 2567 | .clk = "dpll_core_m4_div2_ck", | 1873 | .clk = "dpll_core_m4_div2_ck", |
| 2568 | .addr = am33xx_i2c1_addr_space, | ||
| 2569 | .user = OCP_USER_MPU, | 1874 | .user = OCP_USER_MPU, |
| 2570 | }; | 1875 | }; |
| 2571 | 1876 | ||
| 2572 | /* L4 WKUP -> GPIO1 */ | 1877 | /* L4 WKUP -> GPIO1 */ |
| 2573 | static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = { | ||
| 2574 | { | ||
| 2575 | .pa_start = 0x44E07000, | ||
| 2576 | .pa_end = 0x44E07000 + SZ_4K - 1, | ||
| 2577 | .flags = ADDR_TYPE_RT, | ||
| 2578 | }, | ||
| 2579 | { } | ||
| 2580 | }; | ||
| 2581 | |||
| 2582 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { | 1878 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { |
| 2583 | .master = &am33xx_l4_wkup_hwmod, | 1879 | .master = &am33xx_l4_wkup_hwmod, |
| 2584 | .slave = &am33xx_gpio0_hwmod, | 1880 | .slave = &am33xx_gpio0_hwmod, |
| 2585 | .clk = "dpll_core_m4_div2_ck", | 1881 | .clk = "dpll_core_m4_div2_ck", |
| 2586 | .addr = am33xx_gpio0_addrs, | ||
| 2587 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 1882 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2588 | }; | 1883 | }; |
| 2589 | 1884 | ||
| @@ -2605,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { | |||
| 2605 | .user = OCP_USER_MPU, | 1900 | .user = OCP_USER_MPU, |
| 2606 | }; | 1901 | }; |
| 2607 | 1902 | ||
| 2608 | static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = { | ||
| 2609 | /* cpsw ss */ | ||
| 2610 | { | ||
| 2611 | .pa_start = 0x4a100000, | ||
| 2612 | .pa_end = 0x4a100000 + SZ_2K - 1, | ||
| 2613 | }, | ||
| 2614 | /* cpsw wr */ | ||
| 2615 | { | ||
| 2616 | .pa_start = 0x4a101200, | ||
| 2617 | .pa_end = 0x4a101200 + SZ_256 - 1, | ||
| 2618 | .flags = ADDR_TYPE_RT, | ||
| 2619 | }, | ||
| 2620 | { } | ||
| 2621 | }; | ||
| 2622 | |||
| 2623 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { | 1903 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { |
| 2624 | .master = &am33xx_l4_hs_hwmod, | 1904 | .master = &am33xx_l4_hs_hwmod, |
| 2625 | .slave = &am33xx_cpgmac0_hwmod, | 1905 | .slave = &am33xx_cpgmac0_hwmod, |
| 2626 | .clk = "cpsw_125mhz_gclk", | 1906 | .clk = "cpsw_125mhz_gclk", |
| 2627 | .addr = am33xx_cpgmac0_addr_space, | ||
| 2628 | .user = OCP_USER_MPU, | 1907 | .user = OCP_USER_MPU, |
| 2629 | }; | 1908 | }; |
| 2630 | 1909 | ||
| 2631 | static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = { | ||
| 2632 | { | ||
| 2633 | .pa_start = 0x4A101000, | ||
| 2634 | .pa_end = 0x4A101000 + SZ_256 - 1, | ||
| 2635 | }, | ||
| 2636 | { } | ||
| 2637 | }; | ||
| 2638 | |||
| 2639 | static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { | 1910 | static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { |
| 2640 | .master = &am33xx_cpgmac0_hwmod, | 1911 | .master = &am33xx_cpgmac0_hwmod, |
| 2641 | .slave = &am33xx_mdio_hwmod, | 1912 | .slave = &am33xx_mdio_hwmod, |
| 2642 | .addr = am33xx_mdio_addr_space, | ||
| 2643 | .user = OCP_USER_MPU, | 1913 | .user = OCP_USER_MPU, |
| 2644 | }; | 1914 | }; |
| 2645 | 1915 | ||
| @@ -2677,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { | |||
| 2677 | .user = OCP_USER_MPU, | 1947 | .user = OCP_USER_MPU, |
| 2678 | }; | 1948 | }; |
| 2679 | 1949 | ||
| 2680 | static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { | ||
| 2681 | { | ||
| 2682 | .pa_start = 0x48300100, | ||
| 2683 | .pa_end = 0x48300100 + SZ_128 - 1, | ||
| 2684 | }, | ||
| 2685 | { } | ||
| 2686 | }; | ||
| 2687 | |||
| 2688 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { | 1950 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { |
| 2689 | .master = &am33xx_epwmss0_hwmod, | 1951 | .master = &am33xx_epwmss0_hwmod, |
| 2690 | .slave = &am33xx_ecap0_hwmod, | 1952 | .slave = &am33xx_ecap0_hwmod, |
| 2691 | .clk = "l4ls_gclk", | 1953 | .clk = "l4ls_gclk", |
| 2692 | .addr = am33xx_ecap0_addr_space, | ||
| 2693 | .user = OCP_USER_MPU, | 1954 | .user = OCP_USER_MPU, |
| 2694 | }; | 1955 | }; |
| 2695 | 1956 | ||
| 2696 | static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = { | ||
| 2697 | { | ||
| 2698 | .pa_start = 0x48300180, | ||
| 2699 | .pa_end = 0x48300180 + SZ_128 - 1, | ||
| 2700 | }, | ||
| 2701 | { } | ||
| 2702 | }; | ||
| 2703 | |||
| 2704 | static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { | 1957 | static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { |
| 2705 | .master = &am33xx_epwmss0_hwmod, | 1958 | .master = &am33xx_epwmss0_hwmod, |
| 2706 | .slave = &am33xx_eqep0_hwmod, | 1959 | .slave = &am33xx_eqep0_hwmod, |
| 2707 | .clk = "l4ls_gclk", | 1960 | .clk = "l4ls_gclk", |
| 2708 | .addr = am33xx_eqep0_addr_space, | ||
| 2709 | .user = OCP_USER_MPU, | 1961 | .user = OCP_USER_MPU, |
| 2710 | }; | 1962 | }; |
| 2711 | 1963 | ||
| 2712 | static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = { | ||
| 2713 | { | ||
| 2714 | .pa_start = 0x48300200, | ||
| 2715 | .pa_end = 0x48300200 + SZ_128 - 1, | ||
| 2716 | }, | ||
| 2717 | { } | ||
| 2718 | }; | ||
| 2719 | |||
| 2720 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { | 1964 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { |
| 2721 | .master = &am33xx_epwmss0_hwmod, | 1965 | .master = &am33xx_epwmss0_hwmod, |
| 2722 | .slave = &am33xx_ehrpwm0_hwmod, | 1966 | .slave = &am33xx_ehrpwm0_hwmod, |
| 2723 | .clk = "l4ls_gclk", | 1967 | .clk = "l4ls_gclk", |
| 2724 | .addr = am33xx_ehrpwm0_addr_space, | ||
| 2725 | .user = OCP_USER_MPU, | 1968 | .user = OCP_USER_MPU, |
| 2726 | }; | 1969 | }; |
| 2727 | 1970 | ||
| @@ -2743,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { | |||
| 2743 | .user = OCP_USER_MPU, | 1986 | .user = OCP_USER_MPU, |
| 2744 | }; | 1987 | }; |
| 2745 | 1988 | ||
| 2746 | static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { | ||
| 2747 | { | ||
| 2748 | .pa_start = 0x48302100, | ||
| 2749 | .pa_end = 0x48302100 + SZ_128 - 1, | ||
| 2750 | }, | ||
| 2751 | { } | ||
| 2752 | }; | ||
| 2753 | |||
| 2754 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { | 1989 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { |
| 2755 | .master = &am33xx_epwmss1_hwmod, | 1990 | .master = &am33xx_epwmss1_hwmod, |
| 2756 | .slave = &am33xx_ecap1_hwmod, | 1991 | .slave = &am33xx_ecap1_hwmod, |
| 2757 | .clk = "l4ls_gclk", | 1992 | .clk = "l4ls_gclk", |
| 2758 | .addr = am33xx_ecap1_addr_space, | ||
| 2759 | .user = OCP_USER_MPU, | 1993 | .user = OCP_USER_MPU, |
| 2760 | }; | 1994 | }; |
| 2761 | 1995 | ||
| 2762 | static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = { | ||
| 2763 | { | ||
| 2764 | .pa_start = 0x48302180, | ||
| 2765 | .pa_end = 0x48302180 + SZ_128 - 1, | ||
| 2766 | }, | ||
| 2767 | { } | ||
| 2768 | }; | ||
| 2769 | |||
| 2770 | static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { | 1996 | static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { |
| 2771 | .master = &am33xx_epwmss1_hwmod, | 1997 | .master = &am33xx_epwmss1_hwmod, |
| 2772 | .slave = &am33xx_eqep1_hwmod, | 1998 | .slave = &am33xx_eqep1_hwmod, |
| 2773 | .clk = "l4ls_gclk", | 1999 | .clk = "l4ls_gclk", |
| 2774 | .addr = am33xx_eqep1_addr_space, | ||
| 2775 | .user = OCP_USER_MPU, | 2000 | .user = OCP_USER_MPU, |
| 2776 | }; | 2001 | }; |
| 2777 | 2002 | ||
| 2778 | static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = { | ||
| 2779 | { | ||
| 2780 | .pa_start = 0x48302200, | ||
| 2781 | .pa_end = 0x48302200 + SZ_128 - 1, | ||
| 2782 | }, | ||
| 2783 | { } | ||
| 2784 | }; | ||
| 2785 | |||
| 2786 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { | 2003 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { |
| 2787 | .master = &am33xx_epwmss1_hwmod, | 2004 | .master = &am33xx_epwmss1_hwmod, |
| 2788 | .slave = &am33xx_ehrpwm1_hwmod, | 2005 | .slave = &am33xx_ehrpwm1_hwmod, |
| 2789 | .clk = "l4ls_gclk", | 2006 | .clk = "l4ls_gclk", |
| 2790 | .addr = am33xx_ehrpwm1_addr_space, | ||
| 2791 | .user = OCP_USER_MPU, | 2007 | .user = OCP_USER_MPU, |
| 2792 | }; | 2008 | }; |
| 2793 | 2009 | ||
| @@ -2808,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { | |||
| 2808 | .user = OCP_USER_MPU, | 2024 | .user = OCP_USER_MPU, |
| 2809 | }; | 2025 | }; |
| 2810 | 2026 | ||
| 2811 | static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { | ||
| 2812 | { | ||
| 2813 | .pa_start = 0x48304100, | ||
| 2814 | .pa_end = 0x48304100 + SZ_128 - 1, | ||
| 2815 | }, | ||
| 2816 | { } | ||
| 2817 | }; | ||
| 2818 | |||
| 2819 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { | 2027 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { |
| 2820 | .master = &am33xx_epwmss2_hwmod, | 2028 | .master = &am33xx_epwmss2_hwmod, |
| 2821 | .slave = &am33xx_ecap2_hwmod, | 2029 | .slave = &am33xx_ecap2_hwmod, |
| 2822 | .clk = "l4ls_gclk", | 2030 | .clk = "l4ls_gclk", |
| 2823 | .addr = am33xx_ecap2_addr_space, | ||
| 2824 | .user = OCP_USER_MPU, | 2031 | .user = OCP_USER_MPU, |
| 2825 | }; | 2032 | }; |
| 2826 | 2033 | ||
| 2827 | static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = { | ||
| 2828 | { | ||
| 2829 | .pa_start = 0x48304180, | ||
| 2830 | .pa_end = 0x48304180 + SZ_128 - 1, | ||
| 2831 | }, | ||
| 2832 | { } | ||
| 2833 | }; | ||
| 2834 | |||
| 2835 | static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { | 2034 | static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { |
| 2836 | .master = &am33xx_epwmss2_hwmod, | 2035 | .master = &am33xx_epwmss2_hwmod, |
| 2837 | .slave = &am33xx_eqep2_hwmod, | 2036 | .slave = &am33xx_eqep2_hwmod, |
| 2838 | .clk = "l4ls_gclk", | 2037 | .clk = "l4ls_gclk", |
| 2839 | .addr = am33xx_eqep2_addr_space, | ||
| 2840 | .user = OCP_USER_MPU, | 2038 | .user = OCP_USER_MPU, |
| 2841 | }; | 2039 | }; |
| 2842 | 2040 | ||
| 2843 | static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = { | ||
| 2844 | { | ||
| 2845 | .pa_start = 0x48304200, | ||
| 2846 | .pa_end = 0x48304200 + SZ_128 - 1, | ||
| 2847 | }, | ||
| 2848 | { } | ||
| 2849 | }; | ||
| 2850 | |||
| 2851 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { | 2041 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { |
| 2852 | .master = &am33xx_epwmss2_hwmod, | 2042 | .master = &am33xx_epwmss2_hwmod, |
| 2853 | .slave = &am33xx_ehrpwm2_hwmod, | 2043 | .slave = &am33xx_ehrpwm2_hwmod, |
| 2854 | .clk = "l4ls_gclk", | 2044 | .clk = "l4ls_gclk", |
| 2855 | .addr = am33xx_ehrpwm2_addr_space, | ||
| 2856 | .user = OCP_USER_MPU, | 2045 | .user = OCP_USER_MPU, |
| 2857 | }; | 2046 | }; |
| 2858 | 2047 | ||
| @@ -2875,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | |||
| 2875 | }; | 2064 | }; |
| 2876 | 2065 | ||
| 2877 | /* i2c2 */ | 2066 | /* i2c2 */ |
| 2878 | static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = { | ||
| 2879 | { | ||
| 2880 | .pa_start = 0x4802A000, | ||
| 2881 | .pa_end = 0x4802A000 + SZ_4K - 1, | ||
| 2882 | .flags = ADDR_TYPE_RT, | ||
| 2883 | }, | ||
| 2884 | { } | ||
| 2885 | }; | ||
| 2886 | |||
| 2887 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { | 2067 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { |
| 2888 | .master = &am33xx_l4_ls_hwmod, | 2068 | .master = &am33xx_l4_ls_hwmod, |
| 2889 | .slave = &am33xx_i2c2_hwmod, | 2069 | .slave = &am33xx_i2c2_hwmod, |
| 2890 | .clk = "l4ls_gclk", | 2070 | .clk = "l4ls_gclk", |
| 2891 | .addr = am33xx_i2c2_addr_space, | ||
| 2892 | .user = OCP_USER_MPU, | 2071 | .user = OCP_USER_MPU, |
| 2893 | }; | 2072 | }; |
| 2894 | 2073 | ||
| 2895 | static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = { | ||
| 2896 | { | ||
| 2897 | .pa_start = 0x4819C000, | ||
| 2898 | .pa_end = 0x4819C000 + SZ_4K - 1, | ||
| 2899 | .flags = ADDR_TYPE_RT | ||
| 2900 | }, | ||
| 2901 | { } | ||
| 2902 | }; | ||
| 2903 | |||
| 2904 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { | 2074 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { |
| 2905 | .master = &am33xx_l4_ls_hwmod, | 2075 | .master = &am33xx_l4_ls_hwmod, |
| 2906 | .slave = &am33xx_i2c3_hwmod, | 2076 | .slave = &am33xx_i2c3_hwmod, |
| 2907 | .clk = "l4ls_gclk", | 2077 | .clk = "l4ls_gclk", |
| 2908 | .addr = am33xx_i2c3_addr_space, | ||
| 2909 | .user = OCP_USER_MPU, | 2078 | .user = OCP_USER_MPU, |
| 2910 | }; | 2079 | }; |
| 2911 | 2080 | ||
| @@ -2945,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | |||
| 2945 | }; | 2114 | }; |
| 2946 | 2115 | ||
| 2947 | /* l4 ls -> spinlock */ | 2116 | /* l4 ls -> spinlock */ |
| 2948 | static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = { | ||
| 2949 | { | ||
| 2950 | .pa_start = 0x480Ca000, | ||
| 2951 | .pa_end = 0x480Ca000 + SZ_4K - 1, | ||
| 2952 | .flags = ADDR_TYPE_RT | ||
| 2953 | }, | ||
| 2954 | { } | ||
| 2955 | }; | ||
| 2956 | |||
| 2957 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { | 2117 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { |
| 2958 | .master = &am33xx_l4_ls_hwmod, | 2118 | .master = &am33xx_l4_ls_hwmod, |
| 2959 | .slave = &am33xx_spinlock_hwmod, | 2119 | .slave = &am33xx_spinlock_hwmod, |
| 2960 | .clk = "l4ls_gclk", | 2120 | .clk = "l4ls_gclk", |
| 2961 | .addr = am33xx_spinlock_addrs, | ||
| 2962 | .user = OCP_USER_MPU, | 2121 | .user = OCP_USER_MPU, |
| 2963 | }; | 2122 | }; |
| 2964 | 2123 | ||
| @@ -2980,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | |||
| 2980 | .user = OCP_USER_MPU, | 2139 | .user = OCP_USER_MPU, |
| 2981 | }; | 2140 | }; |
| 2982 | 2141 | ||
| 2983 | /* l3 s -> mcasp0 data */ | ||
| 2984 | static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = { | ||
| 2985 | { | ||
| 2986 | .pa_start = 0x46000000, | ||
| 2987 | .pa_end = 0x46000000 + SZ_4M - 1, | ||
| 2988 | .flags = ADDR_TYPE_RT | ||
| 2989 | }, | ||
| 2990 | { } | ||
| 2991 | }; | ||
| 2992 | |||
| 2993 | static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = { | ||
| 2994 | .master = &am33xx_l3_s_hwmod, | ||
| 2995 | .slave = &am33xx_mcasp0_hwmod, | ||
| 2996 | .clk = "l3s_gclk", | ||
| 2997 | .addr = am33xx_mcasp0_data_addr_space, | ||
| 2998 | .user = OCP_USER_SDMA, | ||
| 2999 | }; | ||
| 3000 | |||
| 3001 | /* l4 ls -> mcasp1 */ | 2142 | /* l4 ls -> mcasp1 */ |
| 3002 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | 2143 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { |
| 3003 | { | 2144 | { |
| @@ -3016,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | |||
| 3016 | .user = OCP_USER_MPU, | 2157 | .user = OCP_USER_MPU, |
| 3017 | }; | 2158 | }; |
| 3018 | 2159 | ||
| 3019 | /* l3 s -> mcasp1 data */ | ||
| 3020 | static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = { | ||
| 3021 | { | ||
| 3022 | .pa_start = 0x46400000, | ||
| 3023 | .pa_end = 0x46400000 + SZ_4M - 1, | ||
| 3024 | .flags = ADDR_TYPE_RT | ||
| 3025 | }, | ||
| 3026 | { } | ||
| 3027 | }; | ||
| 3028 | |||
| 3029 | static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = { | ||
| 3030 | .master = &am33xx_l3_s_hwmod, | ||
| 3031 | .slave = &am33xx_mcasp1_hwmod, | ||
| 3032 | .clk = "l3s_gclk", | ||
| 3033 | .addr = am33xx_mcasp1_data_addr_space, | ||
| 3034 | .user = OCP_USER_SDMA, | ||
| 3035 | }; | ||
| 3036 | |||
| 3037 | /* l4 ls -> mmc0 */ | 2160 | /* l4 ls -> mmc0 */ |
| 3038 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | 2161 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { |
| 3039 | { | 2162 | { |
| @@ -3089,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | |||
| 3089 | }; | 2212 | }; |
| 3090 | 2213 | ||
| 3091 | /* l4 ls -> mcspi0 */ | 2214 | /* l4 ls -> mcspi0 */ |
| 3092 | static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = { | ||
| 3093 | { | ||
| 3094 | .pa_start = 0x48030000, | ||
| 3095 | .pa_end = 0x48030000 + SZ_1K - 1, | ||
| 3096 | .flags = ADDR_TYPE_RT, | ||
| 3097 | }, | ||
| 3098 | { } | ||
| 3099 | }; | ||
| 3100 | |||
| 3101 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { | 2215 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { |
| 3102 | .master = &am33xx_l4_ls_hwmod, | 2216 | .master = &am33xx_l4_ls_hwmod, |
| 3103 | .slave = &am33xx_spi0_hwmod, | 2217 | .slave = &am33xx_spi0_hwmod, |
| 3104 | .clk = "l4ls_gclk", | 2218 | .clk = "l4ls_gclk", |
| 3105 | .addr = am33xx_mcspi0_addr_space, | ||
| 3106 | .user = OCP_USER_MPU, | 2219 | .user = OCP_USER_MPU, |
| 3107 | }; | 2220 | }; |
| 3108 | 2221 | ||
| 3109 | /* l4 ls -> mcspi1 */ | 2222 | /* l4 ls -> mcspi1 */ |
| 3110 | static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = { | ||
| 3111 | { | ||
| 3112 | .pa_start = 0x481A0000, | ||
| 3113 | .pa_end = 0x481A0000 + SZ_1K - 1, | ||
| 3114 | .flags = ADDR_TYPE_RT, | ||
| 3115 | }, | ||
| 3116 | { } | ||
| 3117 | }; | ||
| 3118 | |||
| 3119 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { | 2223 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { |
| 3120 | .master = &am33xx_l4_ls_hwmod, | 2224 | .master = &am33xx_l4_ls_hwmod, |
| 3121 | .slave = &am33xx_spi1_hwmod, | 2225 | .slave = &am33xx_spi1_hwmod, |
| 3122 | .clk = "l4ls_gclk", | 2226 | .clk = "l4ls_gclk", |
| 3123 | .addr = am33xx_mcspi1_addr_space, | ||
| 3124 | .user = OCP_USER_MPU, | 2227 | .user = OCP_USER_MPU, |
| 3125 | }; | 2228 | }; |
| 3126 | 2229 | ||
| 3127 | /* l4 wkup -> timer1 */ | 2230 | /* l4 wkup -> timer1 */ |
| 3128 | static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = { | ||
| 3129 | { | ||
| 3130 | .pa_start = 0x44E31000, | ||
| 3131 | .pa_end = 0x44E31000 + SZ_1K - 1, | ||
| 3132 | .flags = ADDR_TYPE_RT | ||
| 3133 | }, | ||
| 3134 | { } | ||
| 3135 | }; | ||
| 3136 | |||
| 3137 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { | 2231 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { |
| 3138 | .master = &am33xx_l4_wkup_hwmod, | 2232 | .master = &am33xx_l4_wkup_hwmod, |
| 3139 | .slave = &am33xx_timer1_hwmod, | 2233 | .slave = &am33xx_timer1_hwmod, |
| 3140 | .clk = "dpll_core_m4_div2_ck", | 2234 | .clk = "dpll_core_m4_div2_ck", |
| 3141 | .addr = am33xx_timer1_addr_space, | ||
| 3142 | .user = OCP_USER_MPU, | 2235 | .user = OCP_USER_MPU, |
| 3143 | }; | 2236 | }; |
| 3144 | 2237 | ||
| 3145 | /* l4 per -> timer2 */ | 2238 | /* l4 per -> timer2 */ |
| 3146 | static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = { | ||
| 3147 | { | ||
| 3148 | .pa_start = 0x48040000, | ||
| 3149 | .pa_end = 0x48040000 + SZ_1K - 1, | ||
| 3150 | .flags = ADDR_TYPE_RT | ||
| 3151 | }, | ||
| 3152 | { } | ||
| 3153 | }; | ||
| 3154 | |||
| 3155 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { | 2239 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { |
| 3156 | .master = &am33xx_l4_ls_hwmod, | 2240 | .master = &am33xx_l4_ls_hwmod, |
| 3157 | .slave = &am33xx_timer2_hwmod, | 2241 | .slave = &am33xx_timer2_hwmod, |
| 3158 | .clk = "l4ls_gclk", | 2242 | .clk = "l4ls_gclk", |
| 3159 | .addr = am33xx_timer2_addr_space, | ||
| 3160 | .user = OCP_USER_MPU, | 2243 | .user = OCP_USER_MPU, |
| 3161 | }; | 2244 | }; |
| 3162 | 2245 | ||
| 3163 | /* l4 per -> timer3 */ | 2246 | /* l4 per -> timer3 */ |
| 3164 | static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = { | ||
| 3165 | { | ||
| 3166 | .pa_start = 0x48042000, | ||
| 3167 | .pa_end = 0x48042000 + SZ_1K - 1, | ||
| 3168 | .flags = ADDR_TYPE_RT | ||
| 3169 | }, | ||
| 3170 | { } | ||
| 3171 | }; | ||
| 3172 | |||
| 3173 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { | 2247 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { |
| 3174 | .master = &am33xx_l4_ls_hwmod, | 2248 | .master = &am33xx_l4_ls_hwmod, |
| 3175 | .slave = &am33xx_timer3_hwmod, | 2249 | .slave = &am33xx_timer3_hwmod, |
| 3176 | .clk = "l4ls_gclk", | 2250 | .clk = "l4ls_gclk", |
| 3177 | .addr = am33xx_timer3_addr_space, | ||
| 3178 | .user = OCP_USER_MPU, | 2251 | .user = OCP_USER_MPU, |
| 3179 | }; | 2252 | }; |
| 3180 | 2253 | ||
| 3181 | /* l4 per -> timer4 */ | 2254 | /* l4 per -> timer4 */ |
| 3182 | static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = { | ||
| 3183 | { | ||
| 3184 | .pa_start = 0x48044000, | ||
| 3185 | .pa_end = 0x48044000 + SZ_1K - 1, | ||
| 3186 | .flags = ADDR_TYPE_RT | ||
| 3187 | }, | ||
| 3188 | { } | ||
| 3189 | }; | ||
| 3190 | |||
| 3191 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { | 2255 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { |
| 3192 | .master = &am33xx_l4_ls_hwmod, | 2256 | .master = &am33xx_l4_ls_hwmod, |
| 3193 | .slave = &am33xx_timer4_hwmod, | 2257 | .slave = &am33xx_timer4_hwmod, |
| 3194 | .clk = "l4ls_gclk", | 2258 | .clk = "l4ls_gclk", |
| 3195 | .addr = am33xx_timer4_addr_space, | ||
| 3196 | .user = OCP_USER_MPU, | 2259 | .user = OCP_USER_MPU, |
| 3197 | }; | 2260 | }; |
| 3198 | 2261 | ||
| 3199 | /* l4 per -> timer5 */ | 2262 | /* l4 per -> timer5 */ |
| 3200 | static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = { | ||
| 3201 | { | ||
| 3202 | .pa_start = 0x48046000, | ||
| 3203 | .pa_end = 0x48046000 + SZ_1K - 1, | ||
| 3204 | .flags = ADDR_TYPE_RT | ||
| 3205 | }, | ||
| 3206 | { } | ||
| 3207 | }; | ||
| 3208 | |||
| 3209 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { | 2263 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { |
| 3210 | .master = &am33xx_l4_ls_hwmod, | 2264 | .master = &am33xx_l4_ls_hwmod, |
| 3211 | .slave = &am33xx_timer5_hwmod, | 2265 | .slave = &am33xx_timer5_hwmod, |
| 3212 | .clk = "l4ls_gclk", | 2266 | .clk = "l4ls_gclk", |
| 3213 | .addr = am33xx_timer5_addr_space, | ||
| 3214 | .user = OCP_USER_MPU, | 2267 | .user = OCP_USER_MPU, |
| 3215 | }; | 2268 | }; |
| 3216 | 2269 | ||
| 3217 | /* l4 per -> timer6 */ | 2270 | /* l4 per -> timer6 */ |
| 3218 | static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = { | ||
| 3219 | { | ||
| 3220 | .pa_start = 0x48048000, | ||
| 3221 | .pa_end = 0x48048000 + SZ_1K - 1, | ||
| 3222 | .flags = ADDR_TYPE_RT | ||
| 3223 | }, | ||
| 3224 | { } | ||
| 3225 | }; | ||
| 3226 | |||
| 3227 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { | 2271 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { |
| 3228 | .master = &am33xx_l4_ls_hwmod, | 2272 | .master = &am33xx_l4_ls_hwmod, |
| 3229 | .slave = &am33xx_timer6_hwmod, | 2273 | .slave = &am33xx_timer6_hwmod, |
| 3230 | .clk = "l4ls_gclk", | 2274 | .clk = "l4ls_gclk", |
| 3231 | .addr = am33xx_timer6_addr_space, | ||
| 3232 | .user = OCP_USER_MPU, | 2275 | .user = OCP_USER_MPU, |
| 3233 | }; | 2276 | }; |
| 3234 | 2277 | ||
| 3235 | /* l4 per -> timer7 */ | 2278 | /* l4 per -> timer7 */ |
| 3236 | static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = { | ||
| 3237 | { | ||
| 3238 | .pa_start = 0x4804A000, | ||
| 3239 | .pa_end = 0x4804A000 + SZ_1K - 1, | ||
| 3240 | .flags = ADDR_TYPE_RT | ||
| 3241 | }, | ||
| 3242 | { } | ||
| 3243 | }; | ||
| 3244 | |||
| 3245 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { | 2279 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { |
| 3246 | .master = &am33xx_l4_ls_hwmod, | 2280 | .master = &am33xx_l4_ls_hwmod, |
| 3247 | .slave = &am33xx_timer7_hwmod, | 2281 | .slave = &am33xx_timer7_hwmod, |
| 3248 | .clk = "l4ls_gclk", | 2282 | .clk = "l4ls_gclk", |
| 3249 | .addr = am33xx_timer7_addr_space, | ||
| 3250 | .user = OCP_USER_MPU, | 2283 | .user = OCP_USER_MPU, |
| 3251 | }; | 2284 | }; |
| 3252 | 2285 | ||
| 3253 | /* l3 main -> tpcc */ | 2286 | /* l3 main -> tpcc */ |
| 3254 | static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = { | ||
| 3255 | { | ||
| 3256 | .pa_start = 0x49000000, | ||
| 3257 | .pa_end = 0x49000000 + SZ_32K - 1, | ||
| 3258 | .flags = ADDR_TYPE_RT | ||
| 3259 | }, | ||
| 3260 | { } | ||
| 3261 | }; | ||
| 3262 | |||
| 3263 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { | 2287 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { |
| 3264 | .master = &am33xx_l3_main_hwmod, | 2288 | .master = &am33xx_l3_main_hwmod, |
| 3265 | .slave = &am33xx_tpcc_hwmod, | 2289 | .slave = &am33xx_tpcc_hwmod, |
| 3266 | .clk = "l3_gclk", | 2290 | .clk = "l3_gclk", |
| 3267 | .addr = am33xx_tpcc_addr_space, | ||
| 3268 | .user = OCP_USER_MPU, | 2291 | .user = OCP_USER_MPU, |
| 3269 | }; | 2292 | }; |
| 3270 | 2293 | ||
| @@ -3323,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | |||
| 3323 | }; | 2346 | }; |
| 3324 | 2347 | ||
| 3325 | /* l4 wkup -> uart1 */ | 2348 | /* l4 wkup -> uart1 */ |
| 3326 | static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = { | ||
| 3327 | { | ||
| 3328 | .pa_start = 0x44E09000, | ||
| 3329 | .pa_end = 0x44E09000 + SZ_8K - 1, | ||
| 3330 | .flags = ADDR_TYPE_RT, | ||
| 3331 | }, | ||
| 3332 | { } | ||
| 3333 | }; | ||
| 3334 | |||
| 3335 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { | 2349 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { |
| 3336 | .master = &am33xx_l4_wkup_hwmod, | 2350 | .master = &am33xx_l4_wkup_hwmod, |
| 3337 | .slave = &am33xx_uart1_hwmod, | 2351 | .slave = &am33xx_uart1_hwmod, |
| 3338 | .clk = "dpll_core_m4_div2_ck", | 2352 | .clk = "dpll_core_m4_div2_ck", |
| 3339 | .addr = am33xx_uart1_addr_space, | ||
| 3340 | .user = OCP_USER_MPU, | 2353 | .user = OCP_USER_MPU, |
| 3341 | }; | 2354 | }; |
| 3342 | 2355 | ||
| 3343 | /* l4 ls -> uart2 */ | 2356 | /* l4 ls -> uart2 */ |
| 3344 | static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = { | ||
| 3345 | { | ||
| 3346 | .pa_start = 0x48022000, | ||
| 3347 | .pa_end = 0x48022000 + SZ_8K - 1, | ||
| 3348 | .flags = ADDR_TYPE_RT, | ||
| 3349 | }, | ||
| 3350 | { } | ||
| 3351 | }; | ||
| 3352 | |||
| 3353 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { | 2357 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { |
| 3354 | .master = &am33xx_l4_ls_hwmod, | 2358 | .master = &am33xx_l4_ls_hwmod, |
| 3355 | .slave = &am33xx_uart2_hwmod, | 2359 | .slave = &am33xx_uart2_hwmod, |
| 3356 | .clk = "l4ls_gclk", | 2360 | .clk = "l4ls_gclk", |
| 3357 | .addr = am33xx_uart2_addr_space, | ||
| 3358 | .user = OCP_USER_MPU, | 2361 | .user = OCP_USER_MPU, |
| 3359 | }; | 2362 | }; |
| 3360 | 2363 | ||
| 3361 | /* l4 ls -> uart3 */ | 2364 | /* l4 ls -> uart3 */ |
| 3362 | static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = { | ||
| 3363 | { | ||
| 3364 | .pa_start = 0x48024000, | ||
| 3365 | .pa_end = 0x48024000 + SZ_8K - 1, | ||
| 3366 | .flags = ADDR_TYPE_RT, | ||
| 3367 | }, | ||
| 3368 | { } | ||
| 3369 | }; | ||
| 3370 | |||
| 3371 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { | 2365 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { |
| 3372 | .master = &am33xx_l4_ls_hwmod, | 2366 | .master = &am33xx_l4_ls_hwmod, |
| 3373 | .slave = &am33xx_uart3_hwmod, | 2367 | .slave = &am33xx_uart3_hwmod, |
| 3374 | .clk = "l4ls_gclk", | 2368 | .clk = "l4ls_gclk", |
| 3375 | .addr = am33xx_uart3_addr_space, | ||
| 3376 | .user = OCP_USER_MPU, | 2369 | .user = OCP_USER_MPU, |
| 3377 | }; | 2370 | }; |
| 3378 | 2371 | ||
| 3379 | /* l4 ls -> uart4 */ | 2372 | /* l4 ls -> uart4 */ |
| 3380 | static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = { | ||
| 3381 | { | ||
| 3382 | .pa_start = 0x481A6000, | ||
| 3383 | .pa_end = 0x481A6000 + SZ_8K - 1, | ||
| 3384 | .flags = ADDR_TYPE_RT, | ||
| 3385 | }, | ||
| 3386 | { } | ||
| 3387 | }; | ||
| 3388 | |||
| 3389 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { | 2373 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { |
| 3390 | .master = &am33xx_l4_ls_hwmod, | 2374 | .master = &am33xx_l4_ls_hwmod, |
| 3391 | .slave = &am33xx_uart4_hwmod, | 2375 | .slave = &am33xx_uart4_hwmod, |
| 3392 | .clk = "l4ls_gclk", | 2376 | .clk = "l4ls_gclk", |
| 3393 | .addr = am33xx_uart4_addr_space, | ||
| 3394 | .user = OCP_USER_MPU, | 2377 | .user = OCP_USER_MPU, |
| 3395 | }; | 2378 | }; |
| 3396 | 2379 | ||
| 3397 | /* l4 ls -> uart5 */ | 2380 | /* l4 ls -> uart5 */ |
| 3398 | static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = { | ||
| 3399 | { | ||
| 3400 | .pa_start = 0x481A8000, | ||
| 3401 | .pa_end = 0x481A8000 + SZ_8K - 1, | ||
| 3402 | .flags = ADDR_TYPE_RT, | ||
| 3403 | }, | ||
| 3404 | { } | ||
| 3405 | }; | ||
| 3406 | |||
| 3407 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { | 2381 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { |
| 3408 | .master = &am33xx_l4_ls_hwmod, | 2382 | .master = &am33xx_l4_ls_hwmod, |
| 3409 | .slave = &am33xx_uart5_hwmod, | 2383 | .slave = &am33xx_uart5_hwmod, |
| 3410 | .clk = "l4ls_gclk", | 2384 | .clk = "l4ls_gclk", |
| 3411 | .addr = am33xx_uart5_addr_space, | ||
| 3412 | .user = OCP_USER_MPU, | 2385 | .user = OCP_USER_MPU, |
| 3413 | }; | 2386 | }; |
| 3414 | 2387 | ||
| 3415 | /* l4 ls -> uart6 */ | 2388 | /* l4 ls -> uart6 */ |
| 3416 | static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = { | ||
| 3417 | { | ||
| 3418 | .pa_start = 0x481aa000, | ||
| 3419 | .pa_end = 0x481aa000 + SZ_8K - 1, | ||
| 3420 | .flags = ADDR_TYPE_RT, | ||
| 3421 | }, | ||
| 3422 | { } | ||
| 3423 | }; | ||
| 3424 | |||
| 3425 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { | 2389 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { |
| 3426 | .master = &am33xx_l4_ls_hwmod, | 2390 | .master = &am33xx_l4_ls_hwmod, |
| 3427 | .slave = &am33xx_uart6_hwmod, | 2391 | .slave = &am33xx_uart6_hwmod, |
| 3428 | .clk = "l4ls_gclk", | 2392 | .clk = "l4ls_gclk", |
| 3429 | .addr = am33xx_uart6_addr_space, | ||
| 3430 | .user = OCP_USER_MPU, | 2393 | .user = OCP_USER_MPU, |
| 3431 | }; | 2394 | }; |
| 3432 | 2395 | ||
| 3433 | /* l4 wkup -> wd_timer1 */ | 2396 | /* l4 wkup -> wd_timer1 */ |
| 3434 | static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = { | ||
| 3435 | { | ||
| 3436 | .pa_start = 0x44e35000, | ||
| 3437 | .pa_end = 0x44e35000 + SZ_4K - 1, | ||
| 3438 | .flags = ADDR_TYPE_RT | ||
| 3439 | }, | ||
| 3440 | { } | ||
| 3441 | }; | ||
| 3442 | |||
| 3443 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { | 2397 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { |
| 3444 | .master = &am33xx_l4_wkup_hwmod, | 2398 | .master = &am33xx_l4_wkup_hwmod, |
| 3445 | .slave = &am33xx_wd_timer1_hwmod, | 2399 | .slave = &am33xx_wd_timer1_hwmod, |
| 3446 | .clk = "dpll_core_m4_div2_ck", | 2400 | .clk = "dpll_core_m4_div2_ck", |
| 3447 | .addr = am33xx_wd_timer1_addrs, | ||
| 3448 | .user = OCP_USER_MPU, | 2401 | .user = OCP_USER_MPU, |
| 3449 | }; | 2402 | }; |
| 3450 | 2403 | ||
| 3451 | /* usbss */ | 2404 | /* usbss */ |
| 3452 | /* l3 s -> USBSS interface */ | 2405 | /* l3 s -> USBSS interface */ |
| 3453 | static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = { | ||
| 3454 | { | ||
| 3455 | .name = "usbss", | ||
| 3456 | .pa_start = 0x47400000, | ||
| 3457 | .pa_end = 0x47400000 + SZ_4K - 1, | ||
| 3458 | .flags = ADDR_TYPE_RT | ||
| 3459 | }, | ||
| 3460 | { | ||
| 3461 | .name = "musb0", | ||
| 3462 | .pa_start = 0x47401000, | ||
| 3463 | .pa_end = 0x47401000 + SZ_2K - 1, | ||
| 3464 | .flags = ADDR_TYPE_RT | ||
| 3465 | }, | ||
| 3466 | { | ||
| 3467 | .name = "musb1", | ||
| 3468 | .pa_start = 0x47401800, | ||
| 3469 | .pa_end = 0x47401800 + SZ_2K - 1, | ||
| 3470 | .flags = ADDR_TYPE_RT | ||
| 3471 | }, | ||
| 3472 | { } | ||
| 3473 | }; | ||
| 3474 | |||
| 3475 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { | 2406 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { |
| 3476 | .master = &am33xx_l3_s_hwmod, | 2407 | .master = &am33xx_l3_s_hwmod, |
| 3477 | .slave = &am33xx_usbss_hwmod, | 2408 | .slave = &am33xx_usbss_hwmod, |
| 3478 | .clk = "l3s_gclk", | 2409 | .clk = "l3s_gclk", |
| 3479 | .addr = am33xx_usbss_addr_space, | ||
| 3480 | .user = OCP_USER_MPU, | 2410 | .user = OCP_USER_MPU, |
| 3481 | .flags = OCPIF_SWSUP_IDLE, | 2411 | .flags = OCPIF_SWSUP_IDLE, |
| 3482 | }; | 2412 | }; |
| @@ -3525,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | |||
| 3525 | }; | 2455 | }; |
| 3526 | 2456 | ||
| 3527 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | 2457 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
| 3528 | &am33xx_l4_fw__emif_fw, | ||
| 3529 | &am33xx_l3_main__emif, | 2458 | &am33xx_l3_main__emif, |
| 3530 | &am33xx_mpu__l3_main, | 2459 | &am33xx_mpu__l3_main, |
| 3531 | &am33xx_mpu__prcm, | 2460 | &am33xx_mpu__prcm, |
| 3532 | &am33xx_l3_s__l4_ls, | 2461 | &am33xx_l3_s__l4_ls, |
| 3533 | &am33xx_l3_s__l4_wkup, | 2462 | &am33xx_l3_s__l4_wkup, |
| 3534 | &am33xx_l3_s__l4_fw, | ||
| 3535 | &am33xx_l3_main__l4_hs, | 2463 | &am33xx_l3_main__l4_hs, |
| 3536 | &am33xx_l3_main__l3_s, | 2464 | &am33xx_l3_main__l3_s, |
| 3537 | &am33xx_l3_main__l3_instr, | 2465 | &am33xx_l3_main__l3_instr, |
| @@ -3561,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | |||
| 3561 | &am33xx_l4_per__i2c3, | 2489 | &am33xx_l4_per__i2c3, |
| 3562 | &am33xx_l4_per__mailbox, | 2490 | &am33xx_l4_per__mailbox, |
| 3563 | &am33xx_l4_ls__mcasp0, | 2491 | &am33xx_l4_ls__mcasp0, |
| 3564 | &am33xx_l3_s__mcasp0_data, | ||
| 3565 | &am33xx_l4_ls__mcasp1, | 2492 | &am33xx_l4_ls__mcasp1, |
| 3566 | &am33xx_l3_s__mcasp1_data, | ||
| 3567 | &am33xx_l4_ls__mmc0, | 2493 | &am33xx_l4_ls__mmc0, |
| 3568 | &am33xx_l4_ls__mmc1, | 2494 | &am33xx_l4_ls__mmc1, |
| 3569 | &am33xx_l3_s__mmc2, | 2495 | &am33xx_l3_s__mmc2, |
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 848b6dc67590..d04b5e60fdbe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
| @@ -12,6 +12,8 @@ | |||
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the | 12 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 13 | * authors above to ensure that the autogeneration scripts are kept | 13 | * authors above to ensure that the autogeneration scripts are kept |
| 14 | * up-to-date with the file contents. | 14 | * up-to-date with the file contents. |
| 15 | * Note that this file is currently not in sync with autogeneration scripts. | ||
| 16 | * The above note to be removed, once it is synced up. | ||
| 15 | * | 17 | * |
| 16 | * This program is free software; you can redistribute it and/or modify | 18 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as | 19 | * it under the terms of the GNU General Public License version 2 as |
| @@ -21,7 +23,6 @@ | |||
| 21 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 22 | #include <linux/platform_data/gpio-omap.h> | 24 | #include <linux/platform_data/gpio-omap.h> |
| 23 | #include <linux/power/smartreflex.h> | 25 | #include <linux/power/smartreflex.h> |
| 24 | #include <linux/platform_data/omap_ocp2scp.h> | ||
| 25 | #include <linux/i2c-omap.h> | 26 | #include <linux/i2c-omap.h> |
| 26 | 27 | ||
| 27 | #include <linux/omap-dma.h> | 28 | #include <linux/omap-dma.h> |
| @@ -52,27 +53,6 @@ | |||
| 52 | */ | 53 | */ |
| 53 | 54 | ||
| 54 | /* | 55 | /* |
| 55 | * 'c2c_target_fw' class | ||
| 56 | * instance(s): c2c_target_fw | ||
| 57 | */ | ||
| 58 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | ||
| 59 | .name = "c2c_target_fw", | ||
| 60 | }; | ||
| 61 | |||
| 62 | /* c2c_target_fw */ | ||
| 63 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | ||
| 64 | .name = "c2c_target_fw", | ||
| 65 | .class = &omap44xx_c2c_target_fw_hwmod_class, | ||
| 66 | .clkdm_name = "d2d_clkdm", | ||
| 67 | .prcm = { | ||
| 68 | .omap4 = { | ||
| 69 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | ||
| 70 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | ||
| 71 | }, | ||
| 72 | }, | ||
| 73 | }; | ||
| 74 | |||
| 75 | /* | ||
| 76 | * 'dmm' class | 56 | * 'dmm' class |
| 77 | * instance(s): dmm | 57 | * instance(s): dmm |
| 78 | */ | 58 | */ |
| @@ -81,16 +61,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |||
| 81 | }; | 61 | }; |
| 82 | 62 | ||
| 83 | /* dmm */ | 63 | /* dmm */ |
| 84 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | ||
| 85 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | ||
| 86 | { .irq = -1 } | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct omap_hwmod omap44xx_dmm_hwmod = { | 64 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
| 90 | .name = "dmm", | 65 | .name = "dmm", |
| 91 | .class = &omap44xx_dmm_hwmod_class, | 66 | .class = &omap44xx_dmm_hwmod_class, |
| 92 | .clkdm_name = "l3_emif_clkdm", | 67 | .clkdm_name = "l3_emif_clkdm", |
| 93 | .mpu_irqs = omap44xx_dmm_irqs, | ||
| 94 | .prcm = { | 68 | .prcm = { |
| 95 | .omap4 = { | 69 | .omap4 = { |
| 96 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | 70 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, |
| @@ -100,27 +74,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { | |||
| 100 | }; | 74 | }; |
| 101 | 75 | ||
| 102 | /* | 76 | /* |
| 103 | * 'emif_fw' class | ||
| 104 | * instance(s): emif_fw | ||
| 105 | */ | ||
| 106 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | ||
| 107 | .name = "emif_fw", | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* emif_fw */ | ||
| 111 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | ||
| 112 | .name = "emif_fw", | ||
| 113 | .class = &omap44xx_emif_fw_hwmod_class, | ||
| 114 | .clkdm_name = "l3_emif_clkdm", | ||
| 115 | .prcm = { | ||
| 116 | .omap4 = { | ||
| 117 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | ||
| 118 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, | ||
| 119 | }, | ||
| 120 | }, | ||
| 121 | }; | ||
| 122 | |||
| 123 | /* | ||
| 124 | * 'l3' class | 77 | * 'l3' class |
| 125 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | 78 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 |
| 126 | */ | 79 | */ |
| @@ -143,17 +96,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |||
| 143 | }; | 96 | }; |
| 144 | 97 | ||
| 145 | /* l3_main_1 */ | 98 | /* l3_main_1 */ |
| 146 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { | ||
| 147 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | ||
| 148 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | ||
| 149 | { .irq = -1 } | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | 99 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
| 153 | .name = "l3_main_1", | 100 | .name = "l3_main_1", |
| 154 | .class = &omap44xx_l3_hwmod_class, | 101 | .class = &omap44xx_l3_hwmod_class, |
| 155 | .clkdm_name = "l3_1_clkdm", | 102 | .clkdm_name = "l3_1_clkdm", |
| 156 | .mpu_irqs = omap44xx_l3_main_1_irqs, | ||
| 157 | .prcm = { | 103 | .prcm = { |
| 158 | .omap4 = { | 104 | .omap4 = { |
| 159 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | 105 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, |
| @@ -326,29 +272,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |||
| 326 | }; | 272 | }; |
| 327 | 273 | ||
| 328 | /* aess */ | 274 | /* aess */ |
| 329 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | ||
| 330 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | ||
| 331 | { .irq = -1 } | ||
| 332 | }; | ||
| 333 | |||
| 334 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | ||
| 335 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | ||
| 336 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | ||
| 337 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | ||
| 338 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | ||
| 339 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | ||
| 340 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | ||
| 341 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | ||
| 342 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | ||
| 343 | { .dma_req = -1 } | ||
| 344 | }; | ||
| 345 | |||
| 346 | static struct omap_hwmod omap44xx_aess_hwmod = { | 275 | static struct omap_hwmod omap44xx_aess_hwmod = { |
| 347 | .name = "aess", | 276 | .name = "aess", |
| 348 | .class = &omap44xx_aess_hwmod_class, | 277 | .class = &omap44xx_aess_hwmod_class, |
| 349 | .clkdm_name = "abe_clkdm", | 278 | .clkdm_name = "abe_clkdm", |
| 350 | .mpu_irqs = omap44xx_aess_irqs, | ||
| 351 | .sdma_reqs = omap44xx_aess_sdma_reqs, | ||
| 352 | .main_clk = "aess_fclk", | 279 | .main_clk = "aess_fclk", |
| 353 | .prcm = { | 280 | .prcm = { |
| 354 | .omap4 = { | 281 | .omap4 = { |
| @@ -371,22 +298,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |||
| 371 | }; | 298 | }; |
| 372 | 299 | ||
| 373 | /* c2c */ | 300 | /* c2c */ |
| 374 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | ||
| 375 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | ||
| 376 | { .irq = -1 } | ||
| 377 | }; | ||
| 378 | |||
| 379 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | ||
| 380 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | ||
| 381 | { .dma_req = -1 } | ||
| 382 | }; | ||
| 383 | |||
| 384 | static struct omap_hwmod omap44xx_c2c_hwmod = { | 301 | static struct omap_hwmod omap44xx_c2c_hwmod = { |
| 385 | .name = "c2c", | 302 | .name = "c2c", |
| 386 | .class = &omap44xx_c2c_hwmod_class, | 303 | .class = &omap44xx_c2c_hwmod_class, |
| 387 | .clkdm_name = "d2d_clkdm", | 304 | .clkdm_name = "d2d_clkdm", |
| 388 | .mpu_irqs = omap44xx_c2c_irqs, | ||
| 389 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | ||
| 390 | .prcm = { | 305 | .prcm = { |
| 391 | .omap4 = { | 306 | .omap4 = { |
| 392 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | 307 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, |
| @@ -449,16 +364,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |||
| 449 | }; | 364 | }; |
| 450 | 365 | ||
| 451 | /* ctrl_module_core */ | 366 | /* ctrl_module_core */ |
| 452 | static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { | ||
| 453 | { .irq = 8 + OMAP44XX_IRQ_GIC_START }, | ||
| 454 | { .irq = -1 } | ||
| 455 | }; | ||
| 456 | |||
| 457 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { | 367 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { |
| 458 | .name = "ctrl_module_core", | 368 | .name = "ctrl_module_core", |
| 459 | .class = &omap44xx_ctrl_module_hwmod_class, | 369 | .class = &omap44xx_ctrl_module_hwmod_class, |
| 460 | .clkdm_name = "l4_cfg_clkdm", | 370 | .clkdm_name = "l4_cfg_clkdm", |
| 461 | .mpu_irqs = omap44xx_ctrl_module_core_irqs, | ||
| 462 | .prcm = { | 371 | .prcm = { |
| 463 | .omap4 = { | 372 | .omap4 = { |
| 464 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | 373 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
| @@ -601,22 +510,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |||
| 601 | }; | 510 | }; |
| 602 | 511 | ||
| 603 | /* dmic */ | 512 | /* dmic */ |
| 604 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { | ||
| 605 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | ||
| 606 | { .irq = -1 } | ||
| 607 | }; | ||
| 608 | |||
| 609 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | ||
| 610 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | ||
| 611 | { .dma_req = -1 } | ||
| 612 | }; | ||
| 613 | |||
| 614 | static struct omap_hwmod omap44xx_dmic_hwmod = { | 513 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
| 615 | .name = "dmic", | 514 | .name = "dmic", |
| 616 | .class = &omap44xx_dmic_hwmod_class, | 515 | .class = &omap44xx_dmic_hwmod_class, |
| 617 | .clkdm_name = "abe_clkdm", | 516 | .clkdm_name = "abe_clkdm", |
| 618 | .mpu_irqs = omap44xx_dmic_irqs, | ||
| 619 | .sdma_reqs = omap44xx_dmic_sdma_reqs, | ||
| 620 | .main_clk = "func_dmic_abe_gfclk", | 517 | .main_clk = "func_dmic_abe_gfclk", |
| 621 | .prcm = { | 518 | .prcm = { |
| 622 | .omap4 = { | 519 | .omap4 = { |
| @@ -637,11 +534,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |||
| 637 | }; | 534 | }; |
| 638 | 535 | ||
| 639 | /* dsp */ | 536 | /* dsp */ |
| 640 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | ||
| 641 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | ||
| 642 | { .irq = -1 } | ||
| 643 | }; | ||
| 644 | |||
| 645 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | 537 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
| 646 | { .name = "dsp", .rst_shift = 0 }, | 538 | { .name = "dsp", .rst_shift = 0 }, |
| 647 | }; | 539 | }; |
| @@ -650,7 +542,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { | |||
| 650 | .name = "dsp", | 542 | .name = "dsp", |
| 651 | .class = &omap44xx_dsp_hwmod_class, | 543 | .class = &omap44xx_dsp_hwmod_class, |
| 652 | .clkdm_name = "tesla_clkdm", | 544 | .clkdm_name = "tesla_clkdm", |
| 653 | .mpu_irqs = omap44xx_dsp_irqs, | ||
| 654 | .rst_lines = omap44xx_dsp_resets, | 545 | .rst_lines = omap44xx_dsp_resets, |
| 655 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | 546 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), |
| 656 | .main_clk = "dpll_iva_m4x2_ck", | 547 | .main_clk = "dpll_iva_m4x2_ck", |
| @@ -992,16 +883,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |||
| 992 | }; | 883 | }; |
| 993 | 884 | ||
| 994 | /* elm */ | 885 | /* elm */ |
| 995 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | ||
| 996 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | ||
| 997 | { .irq = -1 } | ||
| 998 | }; | ||
| 999 | |||
| 1000 | static struct omap_hwmod omap44xx_elm_hwmod = { | 886 | static struct omap_hwmod omap44xx_elm_hwmod = { |
| 1001 | .name = "elm", | 887 | .name = "elm", |
| 1002 | .class = &omap44xx_elm_hwmod_class, | 888 | .class = &omap44xx_elm_hwmod_class, |
| 1003 | .clkdm_name = "l4_per_clkdm", | 889 | .clkdm_name = "l4_per_clkdm", |
| 1004 | .mpu_irqs = omap44xx_elm_irqs, | ||
| 1005 | .prcm = { | 890 | .prcm = { |
| 1006 | .omap4 = { | 891 | .omap4 = { |
| 1007 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | 892 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, |
| @@ -1025,17 +910,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |||
| 1025 | }; | 910 | }; |
| 1026 | 911 | ||
| 1027 | /* emif1 */ | 912 | /* emif1 */ |
| 1028 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | ||
| 1029 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | ||
| 1030 | { .irq = -1 } | ||
| 1031 | }; | ||
| 1032 | |||
| 1033 | static struct omap_hwmod omap44xx_emif1_hwmod = { | 913 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
| 1034 | .name = "emif1", | 914 | .name = "emif1", |
| 1035 | .class = &omap44xx_emif_hwmod_class, | 915 | .class = &omap44xx_emif_hwmod_class, |
| 1036 | .clkdm_name = "l3_emif_clkdm", | 916 | .clkdm_name = "l3_emif_clkdm", |
| 1037 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 917 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 1038 | .mpu_irqs = omap44xx_emif1_irqs, | ||
| 1039 | .main_clk = "ddrphy_ck", | 918 | .main_clk = "ddrphy_ck", |
| 1040 | .prcm = { | 919 | .prcm = { |
| 1041 | .omap4 = { | 920 | .omap4 = { |
| @@ -1047,17 +926,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = { | |||
| 1047 | }; | 926 | }; |
| 1048 | 927 | ||
| 1049 | /* emif2 */ | 928 | /* emif2 */ |
| 1050 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | ||
| 1051 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | ||
| 1052 | { .irq = -1 } | ||
| 1053 | }; | ||
| 1054 | |||
| 1055 | static struct omap_hwmod omap44xx_emif2_hwmod = { | 929 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
| 1056 | .name = "emif2", | 930 | .name = "emif2", |
| 1057 | .class = &omap44xx_emif_hwmod_class, | 931 | .class = &omap44xx_emif_hwmod_class, |
| 1058 | .clkdm_name = "l3_emif_clkdm", | 932 | .clkdm_name = "l3_emif_clkdm", |
| 1059 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 933 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 1060 | .mpu_irqs = omap44xx_emif2_irqs, | ||
| 1061 | .main_clk = "ddrphy_ck", | 934 | .main_clk = "ddrphy_ck", |
| 1062 | .prcm = { | 935 | .prcm = { |
| 1063 | .omap4 = { | 936 | .omap4 = { |
| @@ -1098,16 +971,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |||
| 1098 | }; | 971 | }; |
| 1099 | 972 | ||
| 1100 | /* fdif */ | 973 | /* fdif */ |
| 1101 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | ||
| 1102 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | ||
| 1103 | { .irq = -1 } | ||
| 1104 | }; | ||
| 1105 | |||
| 1106 | static struct omap_hwmod omap44xx_fdif_hwmod = { | 974 | static struct omap_hwmod omap44xx_fdif_hwmod = { |
| 1107 | .name = "fdif", | 975 | .name = "fdif", |
| 1108 | .class = &omap44xx_fdif_hwmod_class, | 976 | .class = &omap44xx_fdif_hwmod_class, |
| 1109 | .clkdm_name = "iss_clkdm", | 977 | .clkdm_name = "iss_clkdm", |
| 1110 | .mpu_irqs = omap44xx_fdif_irqs, | ||
| 1111 | .main_clk = "fdif_fck", | 978 | .main_clk = "fdif_fck", |
| 1112 | .prcm = { | 979 | .prcm = { |
| 1113 | .omap4 = { | 980 | .omap4 = { |
| @@ -1148,11 +1015,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { | |||
| 1148 | }; | 1015 | }; |
| 1149 | 1016 | ||
| 1150 | /* gpio1 */ | 1017 | /* gpio1 */ |
| 1151 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | ||
| 1152 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | ||
| 1153 | { .irq = -1 } | ||
| 1154 | }; | ||
| 1155 | |||
| 1156 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | 1018 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
| 1157 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | 1019 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
| 1158 | }; | 1020 | }; |
| @@ -1161,7 +1023,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { | |||
| 1161 | .name = "gpio1", | 1023 | .name = "gpio1", |
| 1162 | .class = &omap44xx_gpio_hwmod_class, | 1024 | .class = &omap44xx_gpio_hwmod_class, |
| 1163 | .clkdm_name = "l4_wkup_clkdm", | 1025 | .clkdm_name = "l4_wkup_clkdm", |
| 1164 | .mpu_irqs = omap44xx_gpio1_irqs, | ||
| 1165 | .main_clk = "l4_wkup_clk_mux_ck", | 1026 | .main_clk = "l4_wkup_clk_mux_ck", |
| 1166 | .prcm = { | 1027 | .prcm = { |
| 1167 | .omap4 = { | 1028 | .omap4 = { |
| @@ -1176,11 +1037,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { | |||
| 1176 | }; | 1037 | }; |
| 1177 | 1038 | ||
| 1178 | /* gpio2 */ | 1039 | /* gpio2 */ |
| 1179 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | ||
| 1180 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | ||
| 1181 | { .irq = -1 } | ||
| 1182 | }; | ||
| 1183 | |||
| 1184 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | 1040 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
| 1185 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | 1041 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
| 1186 | }; | 1042 | }; |
| @@ -1190,7 +1046,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { | |||
| 1190 | .class = &omap44xx_gpio_hwmod_class, | 1046 | .class = &omap44xx_gpio_hwmod_class, |
| 1191 | .clkdm_name = "l4_per_clkdm", | 1047 | .clkdm_name = "l4_per_clkdm", |
| 1192 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1048 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1193 | .mpu_irqs = omap44xx_gpio2_irqs, | ||
| 1194 | .main_clk = "l4_div_ck", | 1049 | .main_clk = "l4_div_ck", |
| 1195 | .prcm = { | 1050 | .prcm = { |
| 1196 | .omap4 = { | 1051 | .omap4 = { |
| @@ -1205,11 +1060,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { | |||
| 1205 | }; | 1060 | }; |
| 1206 | 1061 | ||
| 1207 | /* gpio3 */ | 1062 | /* gpio3 */ |
| 1208 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | ||
| 1209 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | ||
| 1210 | { .irq = -1 } | ||
| 1211 | }; | ||
| 1212 | |||
| 1213 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | 1063 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
| 1214 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | 1064 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
| 1215 | }; | 1065 | }; |
| @@ -1219,7 +1069,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { | |||
| 1219 | .class = &omap44xx_gpio_hwmod_class, | 1069 | .class = &omap44xx_gpio_hwmod_class, |
| 1220 | .clkdm_name = "l4_per_clkdm", | 1070 | .clkdm_name = "l4_per_clkdm", |
| 1221 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1071 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1222 | .mpu_irqs = omap44xx_gpio3_irqs, | ||
| 1223 | .main_clk = "l4_div_ck", | 1072 | .main_clk = "l4_div_ck", |
| 1224 | .prcm = { | 1073 | .prcm = { |
| 1225 | .omap4 = { | 1074 | .omap4 = { |
| @@ -1234,11 +1083,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { | |||
| 1234 | }; | 1083 | }; |
| 1235 | 1084 | ||
| 1236 | /* gpio4 */ | 1085 | /* gpio4 */ |
| 1237 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | ||
| 1238 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | ||
| 1239 | { .irq = -1 } | ||
| 1240 | }; | ||
| 1241 | |||
| 1242 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | 1086 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
| 1243 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | 1087 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
| 1244 | }; | 1088 | }; |
| @@ -1248,7 +1092,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { | |||
| 1248 | .class = &omap44xx_gpio_hwmod_class, | 1092 | .class = &omap44xx_gpio_hwmod_class, |
| 1249 | .clkdm_name = "l4_per_clkdm", | 1093 | .clkdm_name = "l4_per_clkdm", |
| 1250 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1094 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1251 | .mpu_irqs = omap44xx_gpio4_irqs, | ||
| 1252 | .main_clk = "l4_div_ck", | 1095 | .main_clk = "l4_div_ck", |
| 1253 | .prcm = { | 1096 | .prcm = { |
| 1254 | .omap4 = { | 1097 | .omap4 = { |
| @@ -1263,11 +1106,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { | |||
| 1263 | }; | 1106 | }; |
| 1264 | 1107 | ||
| 1265 | /* gpio5 */ | 1108 | /* gpio5 */ |
| 1266 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | ||
| 1267 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | ||
| 1268 | { .irq = -1 } | ||
| 1269 | }; | ||
| 1270 | |||
| 1271 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | 1109 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
| 1272 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | 1110 | { .role = "dbclk", .clk = "gpio5_dbclk" }, |
| 1273 | }; | 1111 | }; |
| @@ -1277,7 +1115,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { | |||
| 1277 | .class = &omap44xx_gpio_hwmod_class, | 1115 | .class = &omap44xx_gpio_hwmod_class, |
| 1278 | .clkdm_name = "l4_per_clkdm", | 1116 | .clkdm_name = "l4_per_clkdm", |
| 1279 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1117 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1280 | .mpu_irqs = omap44xx_gpio5_irqs, | ||
| 1281 | .main_clk = "l4_div_ck", | 1118 | .main_clk = "l4_div_ck", |
| 1282 | .prcm = { | 1119 | .prcm = { |
| 1283 | .omap4 = { | 1120 | .omap4 = { |
| @@ -1292,11 +1129,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { | |||
| 1292 | }; | 1129 | }; |
| 1293 | 1130 | ||
| 1294 | /* gpio6 */ | 1131 | /* gpio6 */ |
| 1295 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | ||
| 1296 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | ||
| 1297 | { .irq = -1 } | ||
| 1298 | }; | ||
| 1299 | |||
| 1300 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | 1132 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
| 1301 | { .role = "dbclk", .clk = "gpio6_dbclk" }, | 1133 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
| 1302 | }; | 1134 | }; |
| @@ -1306,7 +1138,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { | |||
| 1306 | .class = &omap44xx_gpio_hwmod_class, | 1138 | .class = &omap44xx_gpio_hwmod_class, |
| 1307 | .clkdm_name = "l4_per_clkdm", | 1139 | .clkdm_name = "l4_per_clkdm", |
| 1308 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1140 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 1309 | .mpu_irqs = omap44xx_gpio6_irqs, | ||
| 1310 | .main_clk = "l4_div_ck", | 1141 | .main_clk = "l4_div_ck", |
| 1311 | .prcm = { | 1142 | .prcm = { |
| 1312 | .omap4 = { | 1143 | .omap4 = { |
| @@ -1341,16 +1172,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |||
| 1341 | }; | 1172 | }; |
| 1342 | 1173 | ||
| 1343 | /* gpmc */ | 1174 | /* gpmc */ |
| 1344 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | ||
| 1345 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | ||
| 1346 | { .irq = -1 } | ||
| 1347 | }; | ||
| 1348 | |||
| 1349 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | ||
| 1350 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | ||
| 1351 | { .dma_req = -1 } | ||
| 1352 | }; | ||
| 1353 | |||
| 1354 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | 1175 | static struct omap_hwmod omap44xx_gpmc_hwmod = { |
| 1355 | .name = "gpmc", | 1176 | .name = "gpmc", |
| 1356 | .class = &omap44xx_gpmc_hwmod_class, | 1177 | .class = &omap44xx_gpmc_hwmod_class, |
| @@ -1364,8 +1185,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { | |||
| 1364 | * HWMOD_INIT_NO_RESET should be removed ASAP. | 1185 | * HWMOD_INIT_NO_RESET should be removed ASAP. |
| 1365 | */ | 1186 | */ |
| 1366 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 1187 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 1367 | .mpu_irqs = omap44xx_gpmc_irqs, | ||
| 1368 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | ||
| 1369 | .prcm = { | 1188 | .prcm = { |
| 1370 | .omap4 = { | 1189 | .omap4 = { |
| 1371 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | 1190 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, |
| @@ -1396,16 +1215,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |||
| 1396 | }; | 1215 | }; |
| 1397 | 1216 | ||
| 1398 | /* gpu */ | 1217 | /* gpu */ |
| 1399 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | ||
| 1400 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | ||
| 1401 | { .irq = -1 } | ||
| 1402 | }; | ||
| 1403 | |||
| 1404 | static struct omap_hwmod omap44xx_gpu_hwmod = { | 1218 | static struct omap_hwmod omap44xx_gpu_hwmod = { |
| 1405 | .name = "gpu", | 1219 | .name = "gpu", |
| 1406 | .class = &omap44xx_gpu_hwmod_class, | 1220 | .class = &omap44xx_gpu_hwmod_class, |
| 1407 | .clkdm_name = "l3_gfx_clkdm", | 1221 | .clkdm_name = "l3_gfx_clkdm", |
| 1408 | .mpu_irqs = omap44xx_gpu_irqs, | ||
| 1409 | .main_clk = "sgx_clk_mux", | 1222 | .main_clk = "sgx_clk_mux", |
| 1410 | .prcm = { | 1223 | .prcm = { |
| 1411 | .omap4 = { | 1224 | .omap4 = { |
| @@ -1436,17 +1249,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |||
| 1436 | }; | 1249 | }; |
| 1437 | 1250 | ||
| 1438 | /* hdq1w */ | 1251 | /* hdq1w */ |
| 1439 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | ||
| 1440 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | ||
| 1441 | { .irq = -1 } | ||
| 1442 | }; | ||
| 1443 | |||
| 1444 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | 1252 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { |
| 1445 | .name = "hdq1w", | 1253 | .name = "hdq1w", |
| 1446 | .class = &omap44xx_hdq1w_hwmod_class, | 1254 | .class = &omap44xx_hdq1w_hwmod_class, |
| 1447 | .clkdm_name = "l4_per_clkdm", | 1255 | .clkdm_name = "l4_per_clkdm", |
| 1448 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | 1256 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ |
| 1449 | .mpu_irqs = omap44xx_hdq1w_irqs, | ||
| 1450 | .main_clk = "func_12m_fclk", | 1257 | .main_clk = "func_12m_fclk", |
| 1451 | .prcm = { | 1258 | .prcm = { |
| 1452 | .omap4 = { | 1259 | .omap4 = { |
| @@ -1482,18 +1289,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |||
| 1482 | }; | 1289 | }; |
| 1483 | 1290 | ||
| 1484 | /* hsi */ | 1291 | /* hsi */ |
| 1485 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | ||
| 1486 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | ||
| 1487 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | ||
| 1488 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | ||
| 1489 | { .irq = -1 } | ||
| 1490 | }; | ||
| 1491 | |||
| 1492 | static struct omap_hwmod omap44xx_hsi_hwmod = { | 1292 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
| 1493 | .name = "hsi", | 1293 | .name = "hsi", |
| 1494 | .class = &omap44xx_hsi_hwmod_class, | 1294 | .class = &omap44xx_hsi_hwmod_class, |
| 1495 | .clkdm_name = "l3_init_clkdm", | 1295 | .clkdm_name = "l3_init_clkdm", |
| 1496 | .mpu_irqs = omap44xx_hsi_irqs, | ||
| 1497 | .main_clk = "hsi_fck", | 1296 | .main_clk = "hsi_fck", |
| 1498 | .prcm = { | 1297 | .prcm = { |
| 1499 | .omap4 = { | 1298 | .omap4 = { |
| @@ -1533,24 +1332,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { | |||
| 1533 | }; | 1332 | }; |
| 1534 | 1333 | ||
| 1535 | /* i2c1 */ | 1334 | /* i2c1 */ |
| 1536 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | ||
| 1537 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | ||
| 1538 | { .irq = -1 } | ||
| 1539 | }; | ||
| 1540 | |||
| 1541 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { | ||
| 1542 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | ||
| 1543 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | ||
| 1544 | { .dma_req = -1 } | ||
| 1545 | }; | ||
| 1546 | |||
| 1547 | static struct omap_hwmod omap44xx_i2c1_hwmod = { | 1335 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
| 1548 | .name = "i2c1", | 1336 | .name = "i2c1", |
| 1549 | .class = &omap44xx_i2c_hwmod_class, | 1337 | .class = &omap44xx_i2c_hwmod_class, |
| 1550 | .clkdm_name = "l4_per_clkdm", | 1338 | .clkdm_name = "l4_per_clkdm", |
| 1551 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1339 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1552 | .mpu_irqs = omap44xx_i2c1_irqs, | ||
| 1553 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | ||
| 1554 | .main_clk = "func_96m_fclk", | 1340 | .main_clk = "func_96m_fclk", |
| 1555 | .prcm = { | 1341 | .prcm = { |
| 1556 | .omap4 = { | 1342 | .omap4 = { |
| @@ -1563,24 +1349,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { | |||
| 1563 | }; | 1349 | }; |
| 1564 | 1350 | ||
| 1565 | /* i2c2 */ | 1351 | /* i2c2 */ |
| 1566 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | ||
| 1567 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | ||
| 1568 | { .irq = -1 } | ||
| 1569 | }; | ||
| 1570 | |||
| 1571 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { | ||
| 1572 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | ||
| 1573 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | ||
| 1574 | { .dma_req = -1 } | ||
| 1575 | }; | ||
| 1576 | |||
| 1577 | static struct omap_hwmod omap44xx_i2c2_hwmod = { | 1352 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
| 1578 | .name = "i2c2", | 1353 | .name = "i2c2", |
| 1579 | .class = &omap44xx_i2c_hwmod_class, | 1354 | .class = &omap44xx_i2c_hwmod_class, |
| 1580 | .clkdm_name = "l4_per_clkdm", | 1355 | .clkdm_name = "l4_per_clkdm", |
| 1581 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1356 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1582 | .mpu_irqs = omap44xx_i2c2_irqs, | ||
| 1583 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | ||
| 1584 | .main_clk = "func_96m_fclk", | 1357 | .main_clk = "func_96m_fclk", |
| 1585 | .prcm = { | 1358 | .prcm = { |
| 1586 | .omap4 = { | 1359 | .omap4 = { |
| @@ -1593,24 +1366,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { | |||
| 1593 | }; | 1366 | }; |
| 1594 | 1367 | ||
| 1595 | /* i2c3 */ | 1368 | /* i2c3 */ |
| 1596 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | ||
| 1597 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | ||
| 1598 | { .irq = -1 } | ||
| 1599 | }; | ||
| 1600 | |||
| 1601 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { | ||
| 1602 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | ||
| 1603 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | ||
| 1604 | { .dma_req = -1 } | ||
| 1605 | }; | ||
| 1606 | |||
| 1607 | static struct omap_hwmod omap44xx_i2c3_hwmod = { | 1369 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
| 1608 | .name = "i2c3", | 1370 | .name = "i2c3", |
| 1609 | .class = &omap44xx_i2c_hwmod_class, | 1371 | .class = &omap44xx_i2c_hwmod_class, |
| 1610 | .clkdm_name = "l4_per_clkdm", | 1372 | .clkdm_name = "l4_per_clkdm", |
| 1611 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1373 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1612 | .mpu_irqs = omap44xx_i2c3_irqs, | ||
| 1613 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | ||
| 1614 | .main_clk = "func_96m_fclk", | 1374 | .main_clk = "func_96m_fclk", |
| 1615 | .prcm = { | 1375 | .prcm = { |
| 1616 | .omap4 = { | 1376 | .omap4 = { |
| @@ -1623,24 +1383,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { | |||
| 1623 | }; | 1383 | }; |
| 1624 | 1384 | ||
| 1625 | /* i2c4 */ | 1385 | /* i2c4 */ |
| 1626 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | ||
| 1627 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | ||
| 1628 | { .irq = -1 } | ||
| 1629 | }; | ||
| 1630 | |||
| 1631 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { | ||
| 1632 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | ||
| 1633 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | ||
| 1634 | { .dma_req = -1 } | ||
| 1635 | }; | ||
| 1636 | |||
| 1637 | static struct omap_hwmod omap44xx_i2c4_hwmod = { | 1386 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
| 1638 | .name = "i2c4", | 1387 | .name = "i2c4", |
| 1639 | .class = &omap44xx_i2c_hwmod_class, | 1388 | .class = &omap44xx_i2c_hwmod_class, |
| 1640 | .clkdm_name = "l4_per_clkdm", | 1389 | .clkdm_name = "l4_per_clkdm", |
| 1641 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1390 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1642 | .mpu_irqs = omap44xx_i2c4_irqs, | ||
| 1643 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | ||
| 1644 | .main_clk = "func_96m_fclk", | 1391 | .main_clk = "func_96m_fclk", |
| 1645 | .prcm = { | 1392 | .prcm = { |
| 1646 | .omap4 = { | 1393 | .omap4 = { |
| @@ -1662,11 +1409,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |||
| 1662 | }; | 1409 | }; |
| 1663 | 1410 | ||
| 1664 | /* ipu */ | 1411 | /* ipu */ |
| 1665 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | ||
| 1666 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | ||
| 1667 | { .irq = -1 } | ||
| 1668 | }; | ||
| 1669 | |||
| 1670 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { | 1412 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
| 1671 | { .name = "cpu0", .rst_shift = 0 }, | 1413 | { .name = "cpu0", .rst_shift = 0 }, |
| 1672 | { .name = "cpu1", .rst_shift = 1 }, | 1414 | { .name = "cpu1", .rst_shift = 1 }, |
| @@ -1676,7 +1418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { | |||
| 1676 | .name = "ipu", | 1418 | .name = "ipu", |
| 1677 | .class = &omap44xx_ipu_hwmod_class, | 1419 | .class = &omap44xx_ipu_hwmod_class, |
| 1678 | .clkdm_name = "ducati_clkdm", | 1420 | .clkdm_name = "ducati_clkdm", |
| 1679 | .mpu_irqs = omap44xx_ipu_irqs, | ||
| 1680 | .rst_lines = omap44xx_ipu_resets, | 1421 | .rst_lines = omap44xx_ipu_resets, |
| 1681 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | 1422 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), |
| 1682 | .main_clk = "ducati_clk_mux_ck", | 1423 | .main_clk = "ducati_clk_mux_ck", |
| @@ -1721,19 +1462,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |||
| 1721 | }; | 1462 | }; |
| 1722 | 1463 | ||
| 1723 | /* iss */ | 1464 | /* iss */ |
| 1724 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | ||
| 1725 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | ||
| 1726 | { .irq = -1 } | ||
| 1727 | }; | ||
| 1728 | |||
| 1729 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | ||
| 1730 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | ||
| 1731 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | ||
| 1732 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | ||
| 1733 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | ||
| 1734 | { .dma_req = -1 } | ||
| 1735 | }; | ||
| 1736 | |||
| 1737 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { | 1465 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
| 1738 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | 1466 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, |
| 1739 | }; | 1467 | }; |
| @@ -1742,8 +1470,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { | |||
| 1742 | .name = "iss", | 1470 | .name = "iss", |
| 1743 | .class = &omap44xx_iss_hwmod_class, | 1471 | .class = &omap44xx_iss_hwmod_class, |
| 1744 | .clkdm_name = "iss_clkdm", | 1472 | .clkdm_name = "iss_clkdm", |
| 1745 | .mpu_irqs = omap44xx_iss_irqs, | ||
| 1746 | .sdma_reqs = omap44xx_iss_sdma_reqs, | ||
| 1747 | .main_clk = "ducati_clk_mux_ck", | 1473 | .main_clk = "ducati_clk_mux_ck", |
| 1748 | .prcm = { | 1474 | .prcm = { |
| 1749 | .omap4 = { | 1475 | .omap4 = { |
| @@ -1766,13 +1492,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |||
| 1766 | }; | 1492 | }; |
| 1767 | 1493 | ||
| 1768 | /* iva */ | 1494 | /* iva */ |
| 1769 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | ||
| 1770 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | ||
| 1771 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | ||
| 1772 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | ||
| 1773 | { .irq = -1 } | ||
| 1774 | }; | ||
| 1775 | |||
| 1776 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | 1495 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
| 1777 | { .name = "seq0", .rst_shift = 0 }, | 1496 | { .name = "seq0", .rst_shift = 0 }, |
| 1778 | { .name = "seq1", .rst_shift = 1 }, | 1497 | { .name = "seq1", .rst_shift = 1 }, |
| @@ -1783,7 +1502,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { | |||
| 1783 | .name = "iva", | 1502 | .name = "iva", |
| 1784 | .class = &omap44xx_iva_hwmod_class, | 1503 | .class = &omap44xx_iva_hwmod_class, |
| 1785 | .clkdm_name = "ivahd_clkdm", | 1504 | .clkdm_name = "ivahd_clkdm", |
| 1786 | .mpu_irqs = omap44xx_iva_irqs, | ||
| 1787 | .rst_lines = omap44xx_iva_resets, | 1505 | .rst_lines = omap44xx_iva_resets, |
| 1788 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | 1506 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), |
| 1789 | .main_clk = "dpll_iva_m5x2_ck", | 1507 | .main_clk = "dpll_iva_m5x2_ck", |
| @@ -1820,16 +1538,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |||
| 1820 | }; | 1538 | }; |
| 1821 | 1539 | ||
| 1822 | /* kbd */ | 1540 | /* kbd */ |
| 1823 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { | ||
| 1824 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | ||
| 1825 | { .irq = -1 } | ||
| 1826 | }; | ||
| 1827 | |||
| 1828 | static struct omap_hwmod omap44xx_kbd_hwmod = { | 1541 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
| 1829 | .name = "kbd", | 1542 | .name = "kbd", |
| 1830 | .class = &omap44xx_kbd_hwmod_class, | 1543 | .class = &omap44xx_kbd_hwmod_class, |
| 1831 | .clkdm_name = "l4_wkup_clkdm", | 1544 | .clkdm_name = "l4_wkup_clkdm", |
| 1832 | .mpu_irqs = omap44xx_kbd_irqs, | ||
| 1833 | .main_clk = "sys_32k_ck", | 1545 | .main_clk = "sys_32k_ck", |
| 1834 | .prcm = { | 1546 | .prcm = { |
| 1835 | .omap4 = { | 1547 | .omap4 = { |
| @@ -1861,16 +1573,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |||
| 1861 | }; | 1573 | }; |
| 1862 | 1574 | ||
| 1863 | /* mailbox */ | 1575 | /* mailbox */ |
| 1864 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { | ||
| 1865 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | ||
| 1866 | { .irq = -1 } | ||
| 1867 | }; | ||
| 1868 | |||
| 1869 | static struct omap_hwmod omap44xx_mailbox_hwmod = { | 1576 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
| 1870 | .name = "mailbox", | 1577 | .name = "mailbox", |
| 1871 | .class = &omap44xx_mailbox_hwmod_class, | 1578 | .class = &omap44xx_mailbox_hwmod_class, |
| 1872 | .clkdm_name = "l4_cfg_clkdm", | 1579 | .clkdm_name = "l4_cfg_clkdm", |
| 1873 | .mpu_irqs = omap44xx_mailbox_irqs, | ||
| 1874 | .prcm = { | 1580 | .prcm = { |
| 1875 | .omap4 = { | 1581 | .omap4 = { |
| 1876 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, | 1582 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
| @@ -1903,24 +1609,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |||
| 1903 | }; | 1609 | }; |
| 1904 | 1610 | ||
| 1905 | /* mcasp */ | 1611 | /* mcasp */ |
| 1906 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | ||
| 1907 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | ||
| 1908 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | ||
| 1909 | { .irq = -1 } | ||
| 1910 | }; | ||
| 1911 | |||
| 1912 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | ||
| 1913 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | ||
| 1914 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | ||
| 1915 | { .dma_req = -1 } | ||
| 1916 | }; | ||
| 1917 | |||
| 1918 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | 1612 | static struct omap_hwmod omap44xx_mcasp_hwmod = { |
| 1919 | .name = "mcasp", | 1613 | .name = "mcasp", |
| 1920 | .class = &omap44xx_mcasp_hwmod_class, | 1614 | .class = &omap44xx_mcasp_hwmod_class, |
| 1921 | .clkdm_name = "abe_clkdm", | 1615 | .clkdm_name = "abe_clkdm", |
| 1922 | .mpu_irqs = omap44xx_mcasp_irqs, | ||
| 1923 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | ||
| 1924 | .main_clk = "func_mcasp_abe_gfclk", | 1616 | .main_clk = "func_mcasp_abe_gfclk", |
| 1925 | .prcm = { | 1617 | .prcm = { |
| 1926 | .omap4 = { | 1618 | .omap4 = { |
| @@ -1951,17 +1643,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |||
| 1951 | }; | 1643 | }; |
| 1952 | 1644 | ||
| 1953 | /* mcbsp1 */ | 1645 | /* mcbsp1 */ |
| 1954 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { | ||
| 1955 | { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, | ||
| 1956 | { .irq = -1 } | ||
| 1957 | }; | ||
| 1958 | |||
| 1959 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | ||
| 1960 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | ||
| 1961 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | ||
| 1962 | { .dma_req = -1 } | ||
| 1963 | }; | ||
| 1964 | |||
| 1965 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { | 1646 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
| 1966 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | 1647 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 1967 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, | 1648 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
| @@ -1971,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |||
| 1971 | .name = "mcbsp1", | 1652 | .name = "mcbsp1", |
| 1972 | .class = &omap44xx_mcbsp_hwmod_class, | 1653 | .class = &omap44xx_mcbsp_hwmod_class, |
| 1973 | .clkdm_name = "abe_clkdm", | 1654 | .clkdm_name = "abe_clkdm", |
| 1974 | .mpu_irqs = omap44xx_mcbsp1_irqs, | ||
| 1975 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, | ||
| 1976 | .main_clk = "func_mcbsp1_gfclk", | 1655 | .main_clk = "func_mcbsp1_gfclk", |
| 1977 | .prcm = { | 1656 | .prcm = { |
| 1978 | .omap4 = { | 1657 | .omap4 = { |
| @@ -1986,17 +1665,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |||
| 1986 | }; | 1665 | }; |
| 1987 | 1666 | ||
| 1988 | /* mcbsp2 */ | 1667 | /* mcbsp2 */ |
| 1989 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { | ||
| 1990 | { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, | ||
| 1991 | { .irq = -1 } | ||
| 1992 | }; | ||
| 1993 | |||
| 1994 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | ||
| 1995 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | ||
| 1996 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | ||
| 1997 | { .dma_req = -1 } | ||
| 1998 | }; | ||
| 1999 | |||
| 2000 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { | 1668 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
| 2001 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | 1669 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 2002 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, | 1670 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
| @@ -2006,8 +1674,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |||
| 2006 | .name = "mcbsp2", | 1674 | .name = "mcbsp2", |
| 2007 | .class = &omap44xx_mcbsp_hwmod_class, | 1675 | .class = &omap44xx_mcbsp_hwmod_class, |
| 2008 | .clkdm_name = "abe_clkdm", | 1676 | .clkdm_name = "abe_clkdm", |
| 2009 | .mpu_irqs = omap44xx_mcbsp2_irqs, | ||
| 2010 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, | ||
| 2011 | .main_clk = "func_mcbsp2_gfclk", | 1677 | .main_clk = "func_mcbsp2_gfclk", |
| 2012 | .prcm = { | 1678 | .prcm = { |
| 2013 | .omap4 = { | 1679 | .omap4 = { |
| @@ -2021,17 +1687,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |||
| 2021 | }; | 1687 | }; |
| 2022 | 1688 | ||
| 2023 | /* mcbsp3 */ | 1689 | /* mcbsp3 */ |
| 2024 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { | ||
| 2025 | { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, | ||
| 2026 | { .irq = -1 } | ||
| 2027 | }; | ||
| 2028 | |||
| 2029 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | ||
| 2030 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | ||
| 2031 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | ||
| 2032 | { .dma_req = -1 } | ||
| 2033 | }; | ||
| 2034 | |||
| 2035 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { | 1690 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
| 2036 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | 1691 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 2037 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, | 1692 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
| @@ -2041,8 +1696,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |||
| 2041 | .name = "mcbsp3", | 1696 | .name = "mcbsp3", |
| 2042 | .class = &omap44xx_mcbsp_hwmod_class, | 1697 | .class = &omap44xx_mcbsp_hwmod_class, |
| 2043 | .clkdm_name = "abe_clkdm", | 1698 | .clkdm_name = "abe_clkdm", |
| 2044 | .mpu_irqs = omap44xx_mcbsp3_irqs, | ||
| 2045 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, | ||
| 2046 | .main_clk = "func_mcbsp3_gfclk", | 1699 | .main_clk = "func_mcbsp3_gfclk", |
| 2047 | .prcm = { | 1700 | .prcm = { |
| 2048 | .omap4 = { | 1701 | .omap4 = { |
| @@ -2056,17 +1709,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |||
| 2056 | }; | 1709 | }; |
| 2057 | 1710 | ||
| 2058 | /* mcbsp4 */ | 1711 | /* mcbsp4 */ |
| 2059 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { | ||
| 2060 | { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, | ||
| 2061 | { .irq = -1 } | ||
| 2062 | }; | ||
| 2063 | |||
| 2064 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | ||
| 2065 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | ||
| 2066 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | ||
| 2067 | { .dma_req = -1 } | ||
| 2068 | }; | ||
| 2069 | |||
| 2070 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { | 1712 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
| 2071 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | 1713 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 2072 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, | 1714 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
| @@ -2076,8 +1718,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |||
| 2076 | .name = "mcbsp4", | 1718 | .name = "mcbsp4", |
| 2077 | .class = &omap44xx_mcbsp_hwmod_class, | 1719 | .class = &omap44xx_mcbsp_hwmod_class, |
| 2078 | .clkdm_name = "l4_per_clkdm", | 1720 | .clkdm_name = "l4_per_clkdm", |
| 2079 | .mpu_irqs = omap44xx_mcbsp4_irqs, | ||
| 2080 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, | ||
| 2081 | .main_clk = "per_mcbsp4_gfclk", | 1721 | .main_clk = "per_mcbsp4_gfclk", |
| 2082 | .prcm = { | 1722 | .prcm = { |
| 2083 | .omap4 = { | 1723 | .omap4 = { |
| @@ -2112,17 +1752,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |||
| 2112 | }; | 1752 | }; |
| 2113 | 1753 | ||
| 2114 | /* mcpdm */ | 1754 | /* mcpdm */ |
| 2115 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { | ||
| 2116 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | ||
| 2117 | { .irq = -1 } | ||
| 2118 | }; | ||
| 2119 | |||
| 2120 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | ||
| 2121 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | ||
| 2122 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | ||
| 2123 | { .dma_req = -1 } | ||
| 2124 | }; | ||
| 2125 | |||
| 2126 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { | 1755 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
| 2127 | .name = "mcpdm", | 1756 | .name = "mcpdm", |
| 2128 | .class = &omap44xx_mcpdm_hwmod_class, | 1757 | .class = &omap44xx_mcpdm_hwmod_class, |
| @@ -2139,8 +1768,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |||
| 2139 | * results 'slow motion' audio playback. | 1768 | * results 'slow motion' audio playback. |
| 2140 | */ | 1769 | */ |
| 2141 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, | 1770 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
| 2142 | .mpu_irqs = omap44xx_mcpdm_irqs, | ||
| 2143 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, | ||
| 2144 | .main_clk = "pad_clks_ck", | 1771 | .main_clk = "pad_clks_ck", |
| 2145 | .prcm = { | 1772 | .prcm = { |
| 2146 | .omap4 = { | 1773 | .omap4 = { |
| @@ -2174,11 +1801,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |||
| 2174 | }; | 1801 | }; |
| 2175 | 1802 | ||
| 2176 | /* mcspi1 */ | 1803 | /* mcspi1 */ |
| 2177 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { | ||
| 2178 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | ||
| 2179 | { .irq = -1 } | ||
| 2180 | }; | ||
| 2181 | |||
| 2182 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | 1804 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { |
| 2183 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | 1805 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, |
| 2184 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | 1806 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, |
| @@ -2200,7 +1822,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |||
| 2200 | .name = "mcspi1", | 1822 | .name = "mcspi1", |
| 2201 | .class = &omap44xx_mcspi_hwmod_class, | 1823 | .class = &omap44xx_mcspi_hwmod_class, |
| 2202 | .clkdm_name = "l4_per_clkdm", | 1824 | .clkdm_name = "l4_per_clkdm", |
| 2203 | .mpu_irqs = omap44xx_mcspi1_irqs, | ||
| 2204 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, | 1825 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
| 2205 | .main_clk = "func_48m_fclk", | 1826 | .main_clk = "func_48m_fclk", |
| 2206 | .prcm = { | 1827 | .prcm = { |
| @@ -2214,11 +1835,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |||
| 2214 | }; | 1835 | }; |
| 2215 | 1836 | ||
| 2216 | /* mcspi2 */ | 1837 | /* mcspi2 */ |
| 2217 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { | ||
| 2218 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | ||
| 2219 | { .irq = -1 } | ||
| 2220 | }; | ||
| 2221 | |||
| 2222 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | 1838 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { |
| 2223 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | 1839 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, |
| 2224 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | 1840 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, |
| @@ -2236,7 +1852,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |||
| 2236 | .name = "mcspi2", | 1852 | .name = "mcspi2", |
| 2237 | .class = &omap44xx_mcspi_hwmod_class, | 1853 | .class = &omap44xx_mcspi_hwmod_class, |
| 2238 | .clkdm_name = "l4_per_clkdm", | 1854 | .clkdm_name = "l4_per_clkdm", |
| 2239 | .mpu_irqs = omap44xx_mcspi2_irqs, | ||
| 2240 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, | 1855 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
| 2241 | .main_clk = "func_48m_fclk", | 1856 | .main_clk = "func_48m_fclk", |
| 2242 | .prcm = { | 1857 | .prcm = { |
| @@ -2250,11 +1865,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |||
| 2250 | }; | 1865 | }; |
| 2251 | 1866 | ||
| 2252 | /* mcspi3 */ | 1867 | /* mcspi3 */ |
| 2253 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { | ||
| 2254 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | ||
| 2255 | { .irq = -1 } | ||
| 2256 | }; | ||
| 2257 | |||
| 2258 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | 1868 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { |
| 2259 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | 1869 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, |
| 2260 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | 1870 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, |
| @@ -2272,7 +1882,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |||
| 2272 | .name = "mcspi3", | 1882 | .name = "mcspi3", |
| 2273 | .class = &omap44xx_mcspi_hwmod_class, | 1883 | .class = &omap44xx_mcspi_hwmod_class, |
| 2274 | .clkdm_name = "l4_per_clkdm", | 1884 | .clkdm_name = "l4_per_clkdm", |
| 2275 | .mpu_irqs = omap44xx_mcspi3_irqs, | ||
| 2276 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, | 1885 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
| 2277 | .main_clk = "func_48m_fclk", | 1886 | .main_clk = "func_48m_fclk", |
| 2278 | .prcm = { | 1887 | .prcm = { |
| @@ -2286,11 +1895,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |||
| 2286 | }; | 1895 | }; |
| 2287 | 1896 | ||
| 2288 | /* mcspi4 */ | 1897 | /* mcspi4 */ |
| 2289 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { | ||
| 2290 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | ||
| 2291 | { .irq = -1 } | ||
| 2292 | }; | ||
| 2293 | |||
| 2294 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | 1898 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { |
| 2295 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | 1899 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, |
| 2296 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | 1900 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, |
| @@ -2306,7 +1910,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { | |||
| 2306 | .name = "mcspi4", | 1910 | .name = "mcspi4", |
| 2307 | .class = &omap44xx_mcspi_hwmod_class, | 1911 | .class = &omap44xx_mcspi_hwmod_class, |
| 2308 | .clkdm_name = "l4_per_clkdm", | 1912 | .clkdm_name = "l4_per_clkdm", |
| 2309 | .mpu_irqs = omap44xx_mcspi4_irqs, | ||
| 2310 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, | 1913 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
| 2311 | .main_clk = "func_48m_fclk", | 1914 | .main_clk = "func_48m_fclk", |
| 2312 | .prcm = { | 1915 | .prcm = { |
| @@ -2342,11 +1945,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |||
| 2342 | }; | 1945 | }; |
| 2343 | 1946 | ||
| 2344 | /* mmc1 */ | 1947 | /* mmc1 */ |
| 2345 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | ||
| 2346 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | ||
| 2347 | { .irq = -1 } | ||
| 2348 | }; | ||
| 2349 | |||
| 2350 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | 1948 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { |
| 2351 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | 1949 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, |
| 2352 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | 1950 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, |
| @@ -2362,7 +1960,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
| 2362 | .name = "mmc1", | 1960 | .name = "mmc1", |
| 2363 | .class = &omap44xx_mmc_hwmod_class, | 1961 | .class = &omap44xx_mmc_hwmod_class, |
| 2364 | .clkdm_name = "l3_init_clkdm", | 1962 | .clkdm_name = "l3_init_clkdm", |
| 2365 | .mpu_irqs = omap44xx_mmc1_irqs, | ||
| 2366 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, | 1963 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
| 2367 | .main_clk = "hsmmc1_fclk", | 1964 | .main_clk = "hsmmc1_fclk", |
| 2368 | .prcm = { | 1965 | .prcm = { |
| @@ -2376,11 +1973,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
| 2376 | }; | 1973 | }; |
| 2377 | 1974 | ||
| 2378 | /* mmc2 */ | 1975 | /* mmc2 */ |
| 2379 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | ||
| 2380 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | ||
| 2381 | { .irq = -1 } | ||
| 2382 | }; | ||
| 2383 | |||
| 2384 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | 1976 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { |
| 2385 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | 1977 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, |
| 2386 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | 1978 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, |
| @@ -2391,7 +1983,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
| 2391 | .name = "mmc2", | 1983 | .name = "mmc2", |
| 2392 | .class = &omap44xx_mmc_hwmod_class, | 1984 | .class = &omap44xx_mmc_hwmod_class, |
| 2393 | .clkdm_name = "l3_init_clkdm", | 1985 | .clkdm_name = "l3_init_clkdm", |
| 2394 | .mpu_irqs = omap44xx_mmc2_irqs, | ||
| 2395 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, | 1986 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
| 2396 | .main_clk = "hsmmc2_fclk", | 1987 | .main_clk = "hsmmc2_fclk", |
| 2397 | .prcm = { | 1988 | .prcm = { |
| @@ -2404,11 +1995,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
| 2404 | }; | 1995 | }; |
| 2405 | 1996 | ||
| 2406 | /* mmc3 */ | 1997 | /* mmc3 */ |
| 2407 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { | ||
| 2408 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | ||
| 2409 | { .irq = -1 } | ||
| 2410 | }; | ||
| 2411 | |||
| 2412 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | 1998 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { |
| 2413 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | 1999 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, |
| 2414 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | 2000 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, |
| @@ -2419,7 +2005,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
| 2419 | .name = "mmc3", | 2005 | .name = "mmc3", |
| 2420 | .class = &omap44xx_mmc_hwmod_class, | 2006 | .class = &omap44xx_mmc_hwmod_class, |
| 2421 | .clkdm_name = "l4_per_clkdm", | 2007 | .clkdm_name = "l4_per_clkdm", |
| 2422 | .mpu_irqs = omap44xx_mmc3_irqs, | ||
| 2423 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, | 2008 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
| 2424 | .main_clk = "func_48m_fclk", | 2009 | .main_clk = "func_48m_fclk", |
| 2425 | .prcm = { | 2010 | .prcm = { |
| @@ -2432,11 +2017,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
| 2432 | }; | 2017 | }; |
| 2433 | 2018 | ||
| 2434 | /* mmc4 */ | 2019 | /* mmc4 */ |
| 2435 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { | ||
| 2436 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | ||
| 2437 | { .irq = -1 } | ||
| 2438 | }; | ||
| 2439 | |||
| 2440 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | 2020 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { |
| 2441 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | 2021 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, |
| 2442 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | 2022 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, |
| @@ -2447,7 +2027,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
| 2447 | .name = "mmc4", | 2027 | .name = "mmc4", |
| 2448 | .class = &omap44xx_mmc_hwmod_class, | 2028 | .class = &omap44xx_mmc_hwmod_class, |
| 2449 | .clkdm_name = "l4_per_clkdm", | 2029 | .clkdm_name = "l4_per_clkdm", |
| 2450 | .mpu_irqs = omap44xx_mmc4_irqs, | ||
| 2451 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, | 2030 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
| 2452 | .main_clk = "func_48m_fclk", | 2031 | .main_clk = "func_48m_fclk", |
| 2453 | .prcm = { | 2032 | .prcm = { |
| @@ -2460,11 +2039,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
| 2460 | }; | 2039 | }; |
| 2461 | 2040 | ||
| 2462 | /* mmc5 */ | 2041 | /* mmc5 */ |
| 2463 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { | ||
| 2464 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | ||
| 2465 | { .irq = -1 } | ||
| 2466 | }; | ||
| 2467 | |||
| 2468 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | 2042 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { |
| 2469 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | 2043 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, |
| 2470 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | 2044 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, |
| @@ -2475,7 +2049,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { | |||
| 2475 | .name = "mmc5", | 2049 | .name = "mmc5", |
| 2476 | .class = &omap44xx_mmc_hwmod_class, | 2050 | .class = &omap44xx_mmc_hwmod_class, |
| 2477 | .clkdm_name = "l4_per_clkdm", | 2051 | .clkdm_name = "l4_per_clkdm", |
| 2478 | .mpu_irqs = omap44xx_mmc5_irqs, | ||
| 2479 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, | 2052 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
| 2480 | .main_clk = "func_48m_fclk", | 2053 | .main_clk = "func_48m_fclk", |
| 2481 | .prcm = { | 2054 | .prcm = { |
| @@ -2517,11 +2090,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { | |||
| 2517 | }; | 2090 | }; |
| 2518 | 2091 | ||
| 2519 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; | 2092 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; |
| 2520 | static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { | ||
| 2521 | { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, | ||
| 2522 | { .irq = -1 } | ||
| 2523 | }; | ||
| 2524 | |||
| 2525 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { | 2093 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { |
| 2526 | { .name = "mmu_cache", .rst_shift = 2 }, | 2094 | { .name = "mmu_cache", .rst_shift = 2 }, |
| 2527 | }; | 2095 | }; |
| @@ -2548,7 +2116,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |||
| 2548 | .name = "mmu_ipu", | 2116 | .name = "mmu_ipu", |
| 2549 | .class = &omap44xx_mmu_hwmod_class, | 2117 | .class = &omap44xx_mmu_hwmod_class, |
| 2550 | .clkdm_name = "ducati_clkdm", | 2118 | .clkdm_name = "ducati_clkdm", |
| 2551 | .mpu_irqs = omap44xx_mmu_ipu_irqs, | ||
| 2552 | .rst_lines = omap44xx_mmu_ipu_resets, | 2119 | .rst_lines = omap44xx_mmu_ipu_resets, |
| 2553 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | 2120 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), |
| 2554 | .main_clk = "ducati_clk_mux_ck", | 2121 | .main_clk = "ducati_clk_mux_ck", |
| @@ -2572,11 +2139,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { | |||
| 2572 | }; | 2139 | }; |
| 2573 | 2140 | ||
| 2574 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; | 2141 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; |
| 2575 | static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { | ||
| 2576 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | ||
| 2577 | { .irq = -1 } | ||
| 2578 | }; | ||
| 2579 | |||
| 2580 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { | 2142 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { |
| 2581 | { .name = "mmu_cache", .rst_shift = 1 }, | 2143 | { .name = "mmu_cache", .rst_shift = 1 }, |
| 2582 | }; | 2144 | }; |
| @@ -2603,7 +2165,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |||
| 2603 | .name = "mmu_dsp", | 2165 | .name = "mmu_dsp", |
| 2604 | .class = &omap44xx_mmu_hwmod_class, | 2166 | .class = &omap44xx_mmu_hwmod_class, |
| 2605 | .clkdm_name = "tesla_clkdm", | 2167 | .clkdm_name = "tesla_clkdm", |
| 2606 | .mpu_irqs = omap44xx_mmu_dsp_irqs, | ||
| 2607 | .rst_lines = omap44xx_mmu_dsp_resets, | 2168 | .rst_lines = omap44xx_mmu_dsp_resets, |
| 2608 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | 2169 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), |
| 2609 | .main_clk = "dpll_iva_m4x2_ck", | 2170 | .main_clk = "dpll_iva_m4x2_ck", |
| @@ -2628,21 +2189,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |||
| 2628 | }; | 2189 | }; |
| 2629 | 2190 | ||
| 2630 | /* mpu */ | 2191 | /* mpu */ |
| 2631 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | ||
| 2632 | { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START }, | ||
| 2633 | { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START }, | ||
| 2634 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | ||
| 2635 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | ||
| 2636 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | ||
| 2637 | { .irq = -1 } | ||
| 2638 | }; | ||
| 2639 | |||
| 2640 | static struct omap_hwmod omap44xx_mpu_hwmod = { | 2192 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
| 2641 | .name = "mpu", | 2193 | .name = "mpu", |
| 2642 | .class = &omap44xx_mpu_hwmod_class, | 2194 | .class = &omap44xx_mpu_hwmod_class, |
| 2643 | .clkdm_name = "mpuss_clkdm", | 2195 | .clkdm_name = "mpuss_clkdm", |
| 2644 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 2196 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 2645 | .mpu_irqs = omap44xx_mpu_irqs, | ||
| 2646 | .main_clk = "dpll_mpu_m2_ck", | 2197 | .main_clk = "dpll_mpu_m2_ck", |
| 2647 | .prcm = { | 2198 | .prcm = { |
| 2648 | .omap4 = { | 2199 | .omap4 = { |
| @@ -2695,25 +2246,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { | |||
| 2695 | .sysc = &omap44xx_ocp2scp_sysc, | 2246 | .sysc = &omap44xx_ocp2scp_sysc, |
| 2696 | }; | 2247 | }; |
| 2697 | 2248 | ||
| 2698 | /* ocp2scp dev_attr */ | ||
| 2699 | static struct resource omap44xx_usb_phy_and_pll_addrs[] = { | ||
| 2700 | { | ||
| 2701 | .name = "usb_phy", | ||
| 2702 | .start = 0x4a0ad080, | ||
| 2703 | .end = 0x4a0ae000, | ||
| 2704 | .flags = IORESOURCE_MEM, | ||
| 2705 | }, | ||
| 2706 | { } | ||
| 2707 | }; | ||
| 2708 | |||
| 2709 | static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = { | ||
| 2710 | { | ||
| 2711 | .drv_name = "omap-usb2", | ||
| 2712 | .res = omap44xx_usb_phy_and_pll_addrs, | ||
| 2713 | }, | ||
| 2714 | { } | ||
| 2715 | }; | ||
| 2716 | |||
| 2717 | /* ocp2scp_usb_phy */ | 2249 | /* ocp2scp_usb_phy */ |
| 2718 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | 2250 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
| 2719 | .name = "ocp2scp_usb_phy", | 2251 | .name = "ocp2scp_usb_phy", |
| @@ -2737,7 +2269,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |||
| 2737 | .modulemode = MODULEMODE_HWCTRL, | 2269 | .modulemode = MODULEMODE_HWCTRL, |
| 2738 | }, | 2270 | }, |
| 2739 | }, | 2271 | }, |
| 2740 | .dev_attr = ocp2scp_dev_attr, | ||
| 2741 | }; | 2272 | }; |
| 2742 | 2273 | ||
| 2743 | /* | 2274 | /* |
| @@ -2788,11 +2319,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = { | |||
| 2788 | }; | 2319 | }; |
| 2789 | 2320 | ||
| 2790 | /* prm */ | 2321 | /* prm */ |
| 2791 | static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { | ||
| 2792 | { .irq = 11 + OMAP44XX_IRQ_GIC_START }, | ||
| 2793 | { .irq = -1 } | ||
| 2794 | }; | ||
| 2795 | |||
| 2796 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | 2322 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { |
| 2797 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | 2323 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, |
| 2798 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | 2324 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, |
| @@ -2801,7 +2327,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |||
| 2801 | static struct omap_hwmod omap44xx_prm_hwmod = { | 2327 | static struct omap_hwmod omap44xx_prm_hwmod = { |
| 2802 | .name = "prm", | 2328 | .name = "prm", |
| 2803 | .class = &omap44xx_prcm_hwmod_class, | 2329 | .class = &omap44xx_prcm_hwmod_class, |
| 2804 | .mpu_irqs = omap44xx_prm_irqs, | ||
| 2805 | .rst_lines = omap44xx_prm_resets, | 2330 | .rst_lines = omap44xx_prm_resets, |
| 2806 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | 2331 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), |
| 2807 | }; | 2332 | }; |
| @@ -2872,23 +2397,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |||
| 2872 | }; | 2397 | }; |
| 2873 | 2398 | ||
| 2874 | /* slimbus1 */ | 2399 | /* slimbus1 */ |
| 2875 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | ||
| 2876 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | ||
| 2877 | { .irq = -1 } | ||
| 2878 | }; | ||
| 2879 | |||
| 2880 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | ||
| 2881 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | ||
| 2882 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | ||
| 2883 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | ||
| 2884 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | ||
| 2885 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | ||
| 2886 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | ||
| 2887 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | ||
| 2888 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | ||
| 2889 | { .dma_req = -1 } | ||
| 2890 | }; | ||
| 2891 | |||
| 2892 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | 2400 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { |
| 2893 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | 2401 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, |
| 2894 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | 2402 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, |
| @@ -2900,8 +2408,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |||
| 2900 | .name = "slimbus1", | 2408 | .name = "slimbus1", |
| 2901 | .class = &omap44xx_slimbus_hwmod_class, | 2409 | .class = &omap44xx_slimbus_hwmod_class, |
| 2902 | .clkdm_name = "abe_clkdm", | 2410 | .clkdm_name = "abe_clkdm", |
| 2903 | .mpu_irqs = omap44xx_slimbus1_irqs, | ||
| 2904 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | ||
| 2905 | .prcm = { | 2411 | .prcm = { |
| 2906 | .omap4 = { | 2412 | .omap4 = { |
| 2907 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | 2413 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, |
| @@ -2914,23 +2420,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |||
| 2914 | }; | 2420 | }; |
| 2915 | 2421 | ||
| 2916 | /* slimbus2 */ | 2422 | /* slimbus2 */ |
| 2917 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | ||
| 2918 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | ||
| 2919 | { .irq = -1 } | ||
| 2920 | }; | ||
| 2921 | |||
| 2922 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | ||
| 2923 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | ||
| 2924 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | ||
| 2925 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | ||
| 2926 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | ||
| 2927 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | ||
| 2928 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | ||
| 2929 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | ||
| 2930 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | ||
| 2931 | { .dma_req = -1 } | ||
| 2932 | }; | ||
| 2933 | |||
| 2934 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | 2423 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { |
| 2935 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | 2424 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, |
| 2936 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | 2425 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, |
| @@ -2941,8 +2430,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |||
| 2941 | .name = "slimbus2", | 2430 | .name = "slimbus2", |
| 2942 | .class = &omap44xx_slimbus_hwmod_class, | 2431 | .class = &omap44xx_slimbus_hwmod_class, |
| 2943 | .clkdm_name = "l4_per_clkdm", | 2432 | .clkdm_name = "l4_per_clkdm", |
| 2944 | .mpu_irqs = omap44xx_slimbus2_irqs, | ||
| 2945 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | ||
| 2946 | .prcm = { | 2433 | .prcm = { |
| 2947 | .omap4 = { | 2434 | .omap4 = { |
| 2948 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | 2435 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, |
| @@ -2985,16 +2472,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { | |||
| 2985 | .sensor_voltdm_name = "core", | 2472 | .sensor_voltdm_name = "core", |
| 2986 | }; | 2473 | }; |
| 2987 | 2474 | ||
| 2988 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { | ||
| 2989 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | ||
| 2990 | { .irq = -1 } | ||
| 2991 | }; | ||
| 2992 | |||
| 2993 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | 2475 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
| 2994 | .name = "smartreflex_core", | 2476 | .name = "smartreflex_core", |
| 2995 | .class = &omap44xx_smartreflex_hwmod_class, | 2477 | .class = &omap44xx_smartreflex_hwmod_class, |
| 2996 | .clkdm_name = "l4_ao_clkdm", | 2478 | .clkdm_name = "l4_ao_clkdm", |
| 2997 | .mpu_irqs = omap44xx_smartreflex_core_irqs, | ||
| 2998 | 2479 | ||
| 2999 | .main_clk = "smartreflex_core_fck", | 2480 | .main_clk = "smartreflex_core_fck", |
| 3000 | .prcm = { | 2481 | .prcm = { |
| @@ -3012,16 +2493,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { | |||
| 3012 | .sensor_voltdm_name = "iva", | 2493 | .sensor_voltdm_name = "iva", |
| 3013 | }; | 2494 | }; |
| 3014 | 2495 | ||
| 3015 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | ||
| 3016 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | ||
| 3017 | { .irq = -1 } | ||
| 3018 | }; | ||
| 3019 | |||
| 3020 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | 2496 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
| 3021 | .name = "smartreflex_iva", | 2497 | .name = "smartreflex_iva", |
| 3022 | .class = &omap44xx_smartreflex_hwmod_class, | 2498 | .class = &omap44xx_smartreflex_hwmod_class, |
| 3023 | .clkdm_name = "l4_ao_clkdm", | 2499 | .clkdm_name = "l4_ao_clkdm", |
| 3024 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, | ||
| 3025 | .main_clk = "smartreflex_iva_fck", | 2500 | .main_clk = "smartreflex_iva_fck", |
| 3026 | .prcm = { | 2501 | .prcm = { |
| 3027 | .omap4 = { | 2502 | .omap4 = { |
| @@ -3038,16 +2513,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { | |||
| 3038 | .sensor_voltdm_name = "mpu", | 2513 | .sensor_voltdm_name = "mpu", |
| 3039 | }; | 2514 | }; |
| 3040 | 2515 | ||
| 3041 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | ||
| 3042 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | ||
| 3043 | { .irq = -1 } | ||
| 3044 | }; | ||
| 3045 | |||
| 3046 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | 2516 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
| 3047 | .name = "smartreflex_mpu", | 2517 | .name = "smartreflex_mpu", |
| 3048 | .class = &omap44xx_smartreflex_hwmod_class, | 2518 | .class = &omap44xx_smartreflex_hwmod_class, |
| 3049 | .clkdm_name = "l4_ao_clkdm", | 2519 | .clkdm_name = "l4_ao_clkdm", |
| 3050 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, | ||
| 3051 | .main_clk = "smartreflex_mpu_fck", | 2520 | .main_clk = "smartreflex_mpu_fck", |
| 3052 | .prcm = { | 2521 | .prcm = { |
| 3053 | .omap4 = { | 2522 | .omap4 = { |
| @@ -3155,17 +2624,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |||
| 3155 | }; | 2624 | }; |
| 3156 | 2625 | ||
| 3157 | /* timer1 */ | 2626 | /* timer1 */ |
| 3158 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { | ||
| 3159 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | ||
| 3160 | { .irq = -1 } | ||
| 3161 | }; | ||
| 3162 | |||
| 3163 | static struct omap_hwmod omap44xx_timer1_hwmod = { | 2627 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
| 3164 | .name = "timer1", | 2628 | .name = "timer1", |
| 3165 | .class = &omap44xx_timer_1ms_hwmod_class, | 2629 | .class = &omap44xx_timer_1ms_hwmod_class, |
| 3166 | .clkdm_name = "l4_wkup_clkdm", | 2630 | .clkdm_name = "l4_wkup_clkdm", |
| 3167 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | 2631 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
| 3168 | .mpu_irqs = omap44xx_timer1_irqs, | ||
| 3169 | .main_clk = "dmt1_clk_mux", | 2632 | .main_clk = "dmt1_clk_mux", |
| 3170 | .prcm = { | 2633 | .prcm = { |
| 3171 | .omap4 = { | 2634 | .omap4 = { |
| @@ -3178,17 +2641,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { | |||
| 3178 | }; | 2641 | }; |
| 3179 | 2642 | ||
| 3180 | /* timer2 */ | 2643 | /* timer2 */ |
| 3181 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { | ||
| 3182 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | ||
| 3183 | { .irq = -1 } | ||
| 3184 | }; | ||
| 3185 | |||
| 3186 | static struct omap_hwmod omap44xx_timer2_hwmod = { | 2644 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
| 3187 | .name = "timer2", | 2645 | .name = "timer2", |
| 3188 | .class = &omap44xx_timer_1ms_hwmod_class, | 2646 | .class = &omap44xx_timer_1ms_hwmod_class, |
| 3189 | .clkdm_name = "l4_per_clkdm", | 2647 | .clkdm_name = "l4_per_clkdm", |
| 3190 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | 2648 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
| 3191 | .mpu_irqs = omap44xx_timer2_irqs, | ||
| 3192 | .main_clk = "cm2_dm2_mux", | 2649 | .main_clk = "cm2_dm2_mux", |
| 3193 | .prcm = { | 2650 | .prcm = { |
| 3194 | .omap4 = { | 2651 | .omap4 = { |
| @@ -3200,16 +2657,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { | |||
| 3200 | }; | 2657 | }; |
| 3201 | 2658 | ||
| 3202 | /* timer3 */ | 2659 | /* timer3 */ |
| 3203 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { | ||
| 3204 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | ||
| 3205 | { .irq = -1 } | ||
| 3206 | }; | ||
| 3207 | |||
| 3208 | static struct omap_hwmod omap44xx_timer3_hwmod = { | 2660 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
| 3209 | .name = "timer3", | 2661 | .name = "timer3", |
| 3210 | .class = &omap44xx_timer_hwmod_class, | 2662 | .class = &omap44xx_timer_hwmod_class, |
| 3211 | .clkdm_name = "l4_per_clkdm", | 2663 | .clkdm_name = "l4_per_clkdm", |
| 3212 | .mpu_irqs = omap44xx_timer3_irqs, | ||
| 3213 | .main_clk = "cm2_dm3_mux", | 2664 | .main_clk = "cm2_dm3_mux", |
| 3214 | .prcm = { | 2665 | .prcm = { |
| 3215 | .omap4 = { | 2666 | .omap4 = { |
| @@ -3221,16 +2672,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { | |||
| 3221 | }; | 2672 | }; |
| 3222 | 2673 | ||
| 3223 | /* timer4 */ | 2674 | /* timer4 */ |
| 3224 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { | ||
| 3225 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | ||
| 3226 | { .irq = -1 } | ||
| 3227 | }; | ||
| 3228 | |||
| 3229 | static struct omap_hwmod omap44xx_timer4_hwmod = { | 2675 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
| 3230 | .name = "timer4", | 2676 | .name = "timer4", |
| 3231 | .class = &omap44xx_timer_hwmod_class, | 2677 | .class = &omap44xx_timer_hwmod_class, |
| 3232 | .clkdm_name = "l4_per_clkdm", | 2678 | .clkdm_name = "l4_per_clkdm", |
| 3233 | .mpu_irqs = omap44xx_timer4_irqs, | ||
| 3234 | .main_clk = "cm2_dm4_mux", | 2679 | .main_clk = "cm2_dm4_mux", |
| 3235 | .prcm = { | 2680 | .prcm = { |
| 3236 | .omap4 = { | 2681 | .omap4 = { |
| @@ -3242,16 +2687,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { | |||
| 3242 | }; | 2687 | }; |
| 3243 | 2688 | ||
| 3244 | /* timer5 */ | 2689 | /* timer5 */ |
| 3245 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { | ||
| 3246 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | ||
| 3247 | { .irq = -1 } | ||
| 3248 | }; | ||
| 3249 | |||
| 3250 | static struct omap_hwmod omap44xx_timer5_hwmod = { | 2690 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
| 3251 | .name = "timer5", | 2691 | .name = "timer5", |
| 3252 | .class = &omap44xx_timer_hwmod_class, | 2692 | .class = &omap44xx_timer_hwmod_class, |
| 3253 | .clkdm_name = "abe_clkdm", | 2693 | .clkdm_name = "abe_clkdm", |
| 3254 | .mpu_irqs = omap44xx_timer5_irqs, | ||
| 3255 | .main_clk = "timer5_sync_mux", | 2694 | .main_clk = "timer5_sync_mux", |
| 3256 | .prcm = { | 2695 | .prcm = { |
| 3257 | .omap4 = { | 2696 | .omap4 = { |
| @@ -3264,16 +2703,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { | |||
| 3264 | }; | 2703 | }; |
| 3265 | 2704 | ||
| 3266 | /* timer6 */ | 2705 | /* timer6 */ |
| 3267 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { | ||
| 3268 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | ||
| 3269 | { .irq = -1 } | ||
| 3270 | }; | ||
| 3271 | |||
| 3272 | static struct omap_hwmod omap44xx_timer6_hwmod = { | 2706 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
| 3273 | .name = "timer6", | 2707 | .name = "timer6", |
| 3274 | .class = &omap44xx_timer_hwmod_class, | 2708 | .class = &omap44xx_timer_hwmod_class, |
| 3275 | .clkdm_name = "abe_clkdm", | 2709 | .clkdm_name = "abe_clkdm", |
| 3276 | .mpu_irqs = omap44xx_timer6_irqs, | ||
| 3277 | .main_clk = "timer6_sync_mux", | 2710 | .main_clk = "timer6_sync_mux", |
| 3278 | .prcm = { | 2711 | .prcm = { |
| 3279 | .omap4 = { | 2712 | .omap4 = { |
| @@ -3286,16 +2719,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { | |||
| 3286 | }; | 2719 | }; |
| 3287 | 2720 | ||
| 3288 | /* timer7 */ | 2721 | /* timer7 */ |
| 3289 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { | ||
| 3290 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | ||
| 3291 | { .irq = -1 } | ||
| 3292 | }; | ||
| 3293 | |||
| 3294 | static struct omap_hwmod omap44xx_timer7_hwmod = { | 2722 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
| 3295 | .name = "timer7", | 2723 | .name = "timer7", |
| 3296 | .class = &omap44xx_timer_hwmod_class, | 2724 | .class = &omap44xx_timer_hwmod_class, |
| 3297 | .clkdm_name = "abe_clkdm", | 2725 | .clkdm_name = "abe_clkdm", |
| 3298 | .mpu_irqs = omap44xx_timer7_irqs, | ||
| 3299 | .main_clk = "timer7_sync_mux", | 2726 | .main_clk = "timer7_sync_mux", |
| 3300 | .prcm = { | 2727 | .prcm = { |
| 3301 | .omap4 = { | 2728 | .omap4 = { |
| @@ -3308,16 +2735,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { | |||
| 3308 | }; | 2735 | }; |
| 3309 | 2736 | ||
| 3310 | /* timer8 */ | 2737 | /* timer8 */ |
| 3311 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { | ||
| 3312 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | ||
| 3313 | { .irq = -1 } | ||
| 3314 | }; | ||
| 3315 | |||
| 3316 | static struct omap_hwmod omap44xx_timer8_hwmod = { | 2738 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
| 3317 | .name = "timer8", | 2739 | .name = "timer8", |
| 3318 | .class = &omap44xx_timer_hwmod_class, | 2740 | .class = &omap44xx_timer_hwmod_class, |
| 3319 | .clkdm_name = "abe_clkdm", | 2741 | .clkdm_name = "abe_clkdm", |
| 3320 | .mpu_irqs = omap44xx_timer8_irqs, | ||
| 3321 | .main_clk = "timer8_sync_mux", | 2742 | .main_clk = "timer8_sync_mux", |
| 3322 | .prcm = { | 2743 | .prcm = { |
| 3323 | .omap4 = { | 2744 | .omap4 = { |
| @@ -3330,16 +2751,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { | |||
| 3330 | }; | 2751 | }; |
| 3331 | 2752 | ||
| 3332 | /* timer9 */ | 2753 | /* timer9 */ |
| 3333 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { | ||
| 3334 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | ||
| 3335 | { .irq = -1 } | ||
| 3336 | }; | ||
| 3337 | |||
| 3338 | static struct omap_hwmod omap44xx_timer9_hwmod = { | 2754 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
| 3339 | .name = "timer9", | 2755 | .name = "timer9", |
| 3340 | .class = &omap44xx_timer_hwmod_class, | 2756 | .class = &omap44xx_timer_hwmod_class, |
| 3341 | .clkdm_name = "l4_per_clkdm", | 2757 | .clkdm_name = "l4_per_clkdm", |
| 3342 | .mpu_irqs = omap44xx_timer9_irqs, | ||
| 3343 | .main_clk = "cm2_dm9_mux", | 2758 | .main_clk = "cm2_dm9_mux", |
| 3344 | .prcm = { | 2759 | .prcm = { |
| 3345 | .omap4 = { | 2760 | .omap4 = { |
| @@ -3352,17 +2767,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { | |||
| 3352 | }; | 2767 | }; |
| 3353 | 2768 | ||
| 3354 | /* timer10 */ | 2769 | /* timer10 */ |
| 3355 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { | ||
| 3356 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | ||
| 3357 | { .irq = -1 } | ||
| 3358 | }; | ||
| 3359 | |||
| 3360 | static struct omap_hwmod omap44xx_timer10_hwmod = { | 2770 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
| 3361 | .name = "timer10", | 2771 | .name = "timer10", |
| 3362 | .class = &omap44xx_timer_1ms_hwmod_class, | 2772 | .class = &omap44xx_timer_1ms_hwmod_class, |
| 3363 | .clkdm_name = "l4_per_clkdm", | 2773 | .clkdm_name = "l4_per_clkdm", |
| 3364 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | 2774 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
| 3365 | .mpu_irqs = omap44xx_timer10_irqs, | ||
| 3366 | .main_clk = "cm2_dm10_mux", | 2775 | .main_clk = "cm2_dm10_mux", |
| 3367 | .prcm = { | 2776 | .prcm = { |
| 3368 | .omap4 = { | 2777 | .omap4 = { |
| @@ -3375,16 +2784,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { | |||
| 3375 | }; | 2784 | }; |
| 3376 | 2785 | ||
| 3377 | /* timer11 */ | 2786 | /* timer11 */ |
| 3378 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { | ||
| 3379 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | ||
| 3380 | { .irq = -1 } | ||
| 3381 | }; | ||
| 3382 | |||
| 3383 | static struct omap_hwmod omap44xx_timer11_hwmod = { | 2787 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
| 3384 | .name = "timer11", | 2788 | .name = "timer11", |
| 3385 | .class = &omap44xx_timer_hwmod_class, | 2789 | .class = &omap44xx_timer_hwmod_class, |
| 3386 | .clkdm_name = "l4_per_clkdm", | 2790 | .clkdm_name = "l4_per_clkdm", |
| 3387 | .mpu_irqs = omap44xx_timer11_irqs, | ||
| 3388 | .main_clk = "cm2_dm11_mux", | 2791 | .main_clk = "cm2_dm11_mux", |
| 3389 | .prcm = { | 2792 | .prcm = { |
| 3390 | .omap4 = { | 2793 | .omap4 = { |
| @@ -3419,24 +2822,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { | |||
| 3419 | }; | 2822 | }; |
| 3420 | 2823 | ||
| 3421 | /* uart1 */ | 2824 | /* uart1 */ |
| 3422 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | ||
| 3423 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | ||
| 3424 | { .irq = -1 } | ||
| 3425 | }; | ||
| 3426 | |||
| 3427 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { | ||
| 3428 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | ||
| 3429 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | ||
| 3430 | { .dma_req = -1 } | ||
| 3431 | }; | ||
| 3432 | |||
| 3433 | static struct omap_hwmod omap44xx_uart1_hwmod = { | 2825 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
| 3434 | .name = "uart1", | 2826 | .name = "uart1", |
| 3435 | .class = &omap44xx_uart_hwmod_class, | 2827 | .class = &omap44xx_uart_hwmod_class, |
| 3436 | .clkdm_name = "l4_per_clkdm", | 2828 | .clkdm_name = "l4_per_clkdm", |
| 3437 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 2829 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 3438 | .mpu_irqs = omap44xx_uart1_irqs, | ||
| 3439 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | ||
| 3440 | .main_clk = "func_48m_fclk", | 2830 | .main_clk = "func_48m_fclk", |
| 3441 | .prcm = { | 2831 | .prcm = { |
| 3442 | .omap4 = { | 2832 | .omap4 = { |
| @@ -3448,24 +2838,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { | |||
| 3448 | }; | 2838 | }; |
| 3449 | 2839 | ||
| 3450 | /* uart2 */ | 2840 | /* uart2 */ |
| 3451 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | ||
| 3452 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | ||
| 3453 | { .irq = -1 } | ||
| 3454 | }; | ||
| 3455 | |||
| 3456 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { | ||
| 3457 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | ||
| 3458 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | ||
| 3459 | { .dma_req = -1 } | ||
| 3460 | }; | ||
| 3461 | |||
| 3462 | static struct omap_hwmod omap44xx_uart2_hwmod = { | 2841 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
| 3463 | .name = "uart2", | 2842 | .name = "uart2", |
| 3464 | .class = &omap44xx_uart_hwmod_class, | 2843 | .class = &omap44xx_uart_hwmod_class, |
| 3465 | .clkdm_name = "l4_per_clkdm", | 2844 | .clkdm_name = "l4_per_clkdm", |
| 3466 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 2845 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 3467 | .mpu_irqs = omap44xx_uart2_irqs, | ||
| 3468 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | ||
| 3469 | .main_clk = "func_48m_fclk", | 2846 | .main_clk = "func_48m_fclk", |
| 3470 | .prcm = { | 2847 | .prcm = { |
| 3471 | .omap4 = { | 2848 | .omap4 = { |
| @@ -3477,25 +2854,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { | |||
| 3477 | }; | 2854 | }; |
| 3478 | 2855 | ||
| 3479 | /* uart3 */ | 2856 | /* uart3 */ |
| 3480 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | ||
| 3481 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | ||
| 3482 | { .irq = -1 } | ||
| 3483 | }; | ||
| 3484 | |||
| 3485 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { | ||
| 3486 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | ||
| 3487 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | ||
| 3488 | { .dma_req = -1 } | ||
| 3489 | }; | ||
| 3490 | |||
| 3491 | static struct omap_hwmod omap44xx_uart3_hwmod = { | 2857 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
| 3492 | .name = "uart3", | 2858 | .name = "uart3", |
| 3493 | .class = &omap44xx_uart_hwmod_class, | 2859 | .class = &omap44xx_uart_hwmod_class, |
| 3494 | .clkdm_name = "l4_per_clkdm", | 2860 | .clkdm_name = "l4_per_clkdm", |
| 3495 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | | 2861 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | |
| 3496 | HWMOD_SWSUP_SIDLE_ACT, | 2862 | HWMOD_SWSUP_SIDLE_ACT, |
| 3497 | .mpu_irqs = omap44xx_uart3_irqs, | ||
| 3498 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | ||
| 3499 | .main_clk = "func_48m_fclk", | 2863 | .main_clk = "func_48m_fclk", |
| 3500 | .prcm = { | 2864 | .prcm = { |
| 3501 | .omap4 = { | 2865 | .omap4 = { |
| @@ -3507,24 +2871,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { | |||
| 3507 | }; | 2871 | }; |
| 3508 | 2872 | ||
| 3509 | /* uart4 */ | 2873 | /* uart4 */ |
| 3510 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | ||
| 3511 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | ||
| 3512 | { .irq = -1 } | ||
| 3513 | }; | ||
| 3514 | |||
| 3515 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { | ||
| 3516 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | ||
| 3517 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | ||
| 3518 | { .dma_req = -1 } | ||
| 3519 | }; | ||
| 3520 | |||
| 3521 | static struct omap_hwmod omap44xx_uart4_hwmod = { | 2874 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
| 3522 | .name = "uart4", | 2875 | .name = "uart4", |
| 3523 | .class = &omap44xx_uart_hwmod_class, | 2876 | .class = &omap44xx_uart_hwmod_class, |
| 3524 | .clkdm_name = "l4_per_clkdm", | 2877 | .clkdm_name = "l4_per_clkdm", |
| 3525 | .flags = HWMOD_SWSUP_SIDLE_ACT, | 2878 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
| 3526 | .mpu_irqs = omap44xx_uart4_irqs, | ||
| 3527 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | ||
| 3528 | .main_clk = "func_48m_fclk", | 2879 | .main_clk = "func_48m_fclk", |
| 3529 | .prcm = { | 2880 | .prcm = { |
| 3530 | .omap4 = { | 2881 | .omap4 = { |
| @@ -3563,17 +2914,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |||
| 3563 | }; | 2914 | }; |
| 3564 | 2915 | ||
| 3565 | /* usb_host_fs */ | 2916 | /* usb_host_fs */ |
| 3566 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | ||
| 3567 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | ||
| 3568 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | ||
| 3569 | { .irq = -1 } | ||
| 3570 | }; | ||
| 3571 | |||
| 3572 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | 2917 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { |
| 3573 | .name = "usb_host_fs", | 2918 | .name = "usb_host_fs", |
| 3574 | .class = &omap44xx_usb_host_fs_hwmod_class, | 2919 | .class = &omap44xx_usb_host_fs_hwmod_class, |
| 3575 | .clkdm_name = "l3_init_clkdm", | 2920 | .clkdm_name = "l3_init_clkdm", |
| 3576 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | ||
| 3577 | .main_clk = "usb_host_fs_fck", | 2921 | .main_clk = "usb_host_fs_fck", |
| 3578 | .prcm = { | 2922 | .prcm = { |
| 3579 | .omap4 = { | 2923 | .omap4 = { |
| @@ -3607,12 +2951,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { | |||
| 3607 | }; | 2951 | }; |
| 3608 | 2952 | ||
| 3609 | /* usb_host_hs */ | 2953 | /* usb_host_hs */ |
| 3610 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | ||
| 3611 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | ||
| 3612 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | ||
| 3613 | { .irq = -1 } | ||
| 3614 | }; | ||
| 3615 | |||
| 3616 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { | 2954 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
| 3617 | .name = "usb_host_hs", | 2955 | .name = "usb_host_hs", |
| 3618 | .class = &omap44xx_usb_host_hs_hwmod_class, | 2956 | .class = &omap44xx_usb_host_hs_hwmod_class, |
| @@ -3625,7 +2963,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { | |||
| 3625 | .modulemode = MODULEMODE_SWCTRL, | 2963 | .modulemode = MODULEMODE_SWCTRL, |
| 3626 | }, | 2964 | }, |
| 3627 | }, | 2965 | }, |
| 3628 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | ||
| 3629 | 2966 | ||
| 3630 | /* | 2967 | /* |
| 3631 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | 2968 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock |
| @@ -3700,12 +3037,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |||
| 3700 | }; | 3037 | }; |
| 3701 | 3038 | ||
| 3702 | /* usb_otg_hs */ | 3039 | /* usb_otg_hs */ |
| 3703 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | ||
| 3704 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | ||
| 3705 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | ||
| 3706 | { .irq = -1 } | ||
| 3707 | }; | ||
| 3708 | |||
| 3709 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | 3040 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { |
| 3710 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | 3041 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, |
| 3711 | }; | 3042 | }; |
| @@ -3715,7 +3046,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |||
| 3715 | .class = &omap44xx_usb_otg_hs_hwmod_class, | 3046 | .class = &omap44xx_usb_otg_hs_hwmod_class, |
| 3716 | .clkdm_name = "l3_init_clkdm", | 3047 | .clkdm_name = "l3_init_clkdm", |
| 3717 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | 3048 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 3718 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | ||
| 3719 | .main_clk = "usb_otg_hs_ick", | 3049 | .main_clk = "usb_otg_hs_ick", |
| 3720 | .prcm = { | 3050 | .prcm = { |
| 3721 | .omap4 = { | 3051 | .omap4 = { |
| @@ -3749,16 +3079,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |||
| 3749 | .sysc = &omap44xx_usb_tll_hs_sysc, | 3079 | .sysc = &omap44xx_usb_tll_hs_sysc, |
| 3750 | }; | 3080 | }; |
| 3751 | 3081 | ||
| 3752 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | ||
| 3753 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | ||
| 3754 | { .irq = -1 } | ||
| 3755 | }; | ||
| 3756 | |||
| 3757 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | 3082 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { |
| 3758 | .name = "usb_tll_hs", | 3083 | .name = "usb_tll_hs", |
| 3759 | .class = &omap44xx_usb_tll_hs_hwmod_class, | 3084 | .class = &omap44xx_usb_tll_hs_hwmod_class, |
| 3760 | .clkdm_name = "l3_init_clkdm", | 3085 | .clkdm_name = "l3_init_clkdm", |
| 3761 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | ||
| 3762 | .main_clk = "usb_tll_hs_ick", | 3086 | .main_clk = "usb_tll_hs_ick", |
| 3763 | .prcm = { | 3087 | .prcm = { |
| 3764 | .omap4 = { | 3088 | .omap4 = { |
| @@ -3794,16 +3118,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { | |||
| 3794 | }; | 3118 | }; |
| 3795 | 3119 | ||
| 3796 | /* wd_timer2 */ | 3120 | /* wd_timer2 */ |
| 3797 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | ||
| 3798 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | ||
| 3799 | { .irq = -1 } | ||
| 3800 | }; | ||
| 3801 | |||
| 3802 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | 3121 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
| 3803 | .name = "wd_timer2", | 3122 | .name = "wd_timer2", |
| 3804 | .class = &omap44xx_wd_timer_hwmod_class, | 3123 | .class = &omap44xx_wd_timer_hwmod_class, |
| 3805 | .clkdm_name = "l4_wkup_clkdm", | 3124 | .clkdm_name = "l4_wkup_clkdm", |
| 3806 | .mpu_irqs = omap44xx_wd_timer2_irqs, | ||
| 3807 | .main_clk = "sys_32k_ck", | 3125 | .main_clk = "sys_32k_ck", |
| 3808 | .prcm = { | 3126 | .prcm = { |
| 3809 | .omap4 = { | 3127 | .omap4 = { |
| @@ -3815,16 +3133,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | |||
| 3815 | }; | 3133 | }; |
| 3816 | 3134 | ||
| 3817 | /* wd_timer3 */ | 3135 | /* wd_timer3 */ |
| 3818 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | ||
| 3819 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | ||
| 3820 | { .irq = -1 } | ||
| 3821 | }; | ||
| 3822 | |||
| 3823 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | 3136 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
| 3824 | .name = "wd_timer3", | 3137 | .name = "wd_timer3", |
| 3825 | .class = &omap44xx_wd_timer_hwmod_class, | 3138 | .class = &omap44xx_wd_timer_hwmod_class, |
| 3826 | .clkdm_name = "abe_clkdm", | 3139 | .clkdm_name = "abe_clkdm", |
| 3827 | .mpu_irqs = omap44xx_wd_timer3_irqs, | ||
| 3828 | .main_clk = "sys_32k_ck", | 3140 | .main_clk = "sys_32k_ck", |
| 3829 | .prcm = { | 3141 | .prcm = { |
| 3830 | .omap4 = { | 3142 | .omap4 = { |
| @@ -3840,32 +3152,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |||
| 3840 | * interfaces | 3152 | * interfaces |
| 3841 | */ | 3153 | */ |
| 3842 | 3154 | ||
| 3843 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { | ||
| 3844 | { | ||
| 3845 | .pa_start = 0x4a204000, | ||
| 3846 | .pa_end = 0x4a2040ff, | ||
| 3847 | .flags = ADDR_TYPE_RT | ||
| 3848 | }, | ||
| 3849 | { } | ||
| 3850 | }; | ||
| 3851 | |||
| 3852 | /* c2c -> c2c_target_fw */ | ||
| 3853 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | ||
| 3854 | .master = &omap44xx_c2c_hwmod, | ||
| 3855 | .slave = &omap44xx_c2c_target_fw_hwmod, | ||
| 3856 | .clk = "div_core_ck", | ||
| 3857 | .addr = omap44xx_c2c_target_fw_addrs, | ||
| 3858 | .user = OCP_USER_MPU, | ||
| 3859 | }; | ||
| 3860 | |||
| 3861 | /* l4_cfg -> c2c_target_fw */ | ||
| 3862 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | ||
| 3863 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 3864 | .slave = &omap44xx_c2c_target_fw_hwmod, | ||
| 3865 | .clk = "l4_div_ck", | ||
| 3866 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3867 | }; | ||
| 3868 | |||
| 3869 | /* l3_main_1 -> dmm */ | 3155 | /* l3_main_1 -> dmm */ |
| 3870 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | 3156 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { |
| 3871 | .master = &omap44xx_l3_main_1_hwmod, | 3157 | .master = &omap44xx_l3_main_1_hwmod, |
| @@ -3874,55 +3160,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |||
| 3874 | .user = OCP_USER_SDMA, | 3160 | .user = OCP_USER_SDMA, |
| 3875 | }; | 3161 | }; |
| 3876 | 3162 | ||
| 3877 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | ||
| 3878 | { | ||
| 3879 | .pa_start = 0x4e000000, | ||
| 3880 | .pa_end = 0x4e0007ff, | ||
| 3881 | .flags = ADDR_TYPE_RT | ||
| 3882 | }, | ||
| 3883 | { } | ||
| 3884 | }; | ||
| 3885 | |||
| 3886 | /* mpu -> dmm */ | 3163 | /* mpu -> dmm */ |
| 3887 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | 3164 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { |
| 3888 | .master = &omap44xx_mpu_hwmod, | 3165 | .master = &omap44xx_mpu_hwmod, |
| 3889 | .slave = &omap44xx_dmm_hwmod, | 3166 | .slave = &omap44xx_dmm_hwmod, |
| 3890 | .clk = "l3_div_ck", | 3167 | .clk = "l3_div_ck", |
| 3891 | .addr = omap44xx_dmm_addrs, | ||
| 3892 | .user = OCP_USER_MPU, | ||
| 3893 | }; | ||
| 3894 | |||
| 3895 | /* c2c -> emif_fw */ | ||
| 3896 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | ||
| 3897 | .master = &omap44xx_c2c_hwmod, | ||
| 3898 | .slave = &omap44xx_emif_fw_hwmod, | ||
| 3899 | .clk = "div_core_ck", | ||
| 3900 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3901 | }; | ||
| 3902 | |||
| 3903 | /* dmm -> emif_fw */ | ||
| 3904 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | ||
| 3905 | .master = &omap44xx_dmm_hwmod, | ||
| 3906 | .slave = &omap44xx_emif_fw_hwmod, | ||
| 3907 | .clk = "l3_div_ck", | ||
| 3908 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3909 | }; | ||
| 3910 | |||
| 3911 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | ||
| 3912 | { | ||
| 3913 | .pa_start = 0x4a20c000, | ||
| 3914 | .pa_end = 0x4a20c0ff, | ||
| 3915 | .flags = ADDR_TYPE_RT | ||
| 3916 | }, | ||
| 3917 | { } | ||
| 3918 | }; | ||
| 3919 | |||
| 3920 | /* l4_cfg -> emif_fw */ | ||
| 3921 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | ||
| 3922 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 3923 | .slave = &omap44xx_emif_fw_hwmod, | ||
| 3924 | .clk = "l4_div_ck", | ||
| 3925 | .addr = omap44xx_emif_fw_addrs, | ||
| 3926 | .user = OCP_USER_MPU, | 3168 | .user = OCP_USER_MPU, |
| 3927 | }; | 3169 | }; |
| 3928 | 3170 | ||
| @@ -3998,32 +3240,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |||
| 3998 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3240 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3999 | }; | 3241 | }; |
| 4000 | 3242 | ||
| 4001 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | ||
| 4002 | { | ||
| 4003 | .pa_start = 0x44000000, | ||
| 4004 | .pa_end = 0x44000fff, | ||
| 4005 | .flags = ADDR_TYPE_RT | ||
| 4006 | }, | ||
| 4007 | { } | ||
| 4008 | }; | ||
| 4009 | |||
| 4010 | /* mpu -> l3_main_1 */ | 3243 | /* mpu -> l3_main_1 */ |
| 4011 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | 3244 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { |
| 4012 | .master = &omap44xx_mpu_hwmod, | 3245 | .master = &omap44xx_mpu_hwmod, |
| 4013 | .slave = &omap44xx_l3_main_1_hwmod, | 3246 | .slave = &omap44xx_l3_main_1_hwmod, |
| 4014 | .clk = "l3_div_ck", | 3247 | .clk = "l3_div_ck", |
| 4015 | .addr = omap44xx_l3_main_1_addrs, | ||
| 4016 | .user = OCP_USER_MPU, | 3248 | .user = OCP_USER_MPU, |
| 4017 | }; | 3249 | }; |
| 4018 | 3250 | ||
| 4019 | /* c2c_target_fw -> l3_main_2 */ | ||
| 4020 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | ||
| 4021 | .master = &omap44xx_c2c_target_fw_hwmod, | ||
| 4022 | .slave = &omap44xx_l3_main_2_hwmod, | ||
| 4023 | .clk = "l3_div_ck", | ||
| 4024 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 4025 | }; | ||
| 4026 | |||
| 4027 | /* debugss -> l3_main_2 */ | 3251 | /* debugss -> l3_main_2 */ |
| 4028 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | 3252 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { |
| 4029 | .master = &omap44xx_debugss_hwmod, | 3253 | .master = &omap44xx_debugss_hwmod, |
| @@ -4088,21 +3312,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |||
| 4088 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3312 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4089 | }; | 3313 | }; |
| 4090 | 3314 | ||
| 4091 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | ||
| 4092 | { | ||
| 4093 | .pa_start = 0x44800000, | ||
| 4094 | .pa_end = 0x44801fff, | ||
| 4095 | .flags = ADDR_TYPE_RT | ||
| 4096 | }, | ||
| 4097 | { } | ||
| 4098 | }; | ||
| 4099 | |||
| 4100 | /* l3_main_1 -> l3_main_2 */ | 3315 | /* l3_main_1 -> l3_main_2 */ |
| 4101 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | 3316 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { |
| 4102 | .master = &omap44xx_l3_main_1_hwmod, | 3317 | .master = &omap44xx_l3_main_1_hwmod, |
| 4103 | .slave = &omap44xx_l3_main_2_hwmod, | 3318 | .slave = &omap44xx_l3_main_2_hwmod, |
| 4104 | .clk = "l3_div_ck", | 3319 | .clk = "l3_div_ck", |
| 4105 | .addr = omap44xx_l3_main_2_addrs, | ||
| 4106 | .user = OCP_USER_MPU, | 3320 | .user = OCP_USER_MPU, |
| 4107 | }; | 3321 | }; |
| 4108 | 3322 | ||
| @@ -4138,21 +3352,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |||
| 4138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3352 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4139 | }; | 3353 | }; |
| 4140 | 3354 | ||
| 4141 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | ||
| 4142 | { | ||
| 4143 | .pa_start = 0x45000000, | ||
| 4144 | .pa_end = 0x45000fff, | ||
| 4145 | .flags = ADDR_TYPE_RT | ||
| 4146 | }, | ||
| 4147 | { } | ||
| 4148 | }; | ||
| 4149 | |||
| 4150 | /* l3_main_1 -> l3_main_3 */ | 3355 | /* l3_main_1 -> l3_main_3 */ |
| 4151 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | 3356 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { |
| 4152 | .master = &omap44xx_l3_main_1_hwmod, | 3357 | .master = &omap44xx_l3_main_1_hwmod, |
| 4153 | .slave = &omap44xx_l3_main_3_hwmod, | 3358 | .slave = &omap44xx_l3_main_3_hwmod, |
| 4154 | .clk = "l3_div_ck", | 3359 | .clk = "l3_div_ck", |
| 4155 | .addr = omap44xx_l3_main_3_addrs, | ||
| 4156 | .user = OCP_USER_MPU, | 3360 | .user = OCP_USER_MPU, |
| 4157 | }; | 3361 | }; |
| 4158 | 3362 | ||
| @@ -4236,21 +3440,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |||
| 4236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3440 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4237 | }; | 3441 | }; |
| 4238 | 3442 | ||
| 4239 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { | ||
| 4240 | { | ||
| 4241 | .pa_start = 0x4a102000, | ||
| 4242 | .pa_end = 0x4a10207f, | ||
| 4243 | .flags = ADDR_TYPE_RT | ||
| 4244 | }, | ||
| 4245 | { } | ||
| 4246 | }; | ||
| 4247 | |||
| 4248 | /* l4_cfg -> ocp_wp_noc */ | 3443 | /* l4_cfg -> ocp_wp_noc */ |
| 4249 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | 3444 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { |
| 4250 | .master = &omap44xx_l4_cfg_hwmod, | 3445 | .master = &omap44xx_l4_cfg_hwmod, |
| 4251 | .slave = &omap44xx_ocp_wp_noc_hwmod, | 3446 | .slave = &omap44xx_ocp_wp_noc_hwmod, |
| 4252 | .clk = "l4_div_ck", | 3447 | .clk = "l4_div_ck", |
| 4253 | .addr = omap44xx_ocp_wp_noc_addrs, | ||
| 4254 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3448 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4255 | }; | 3449 | }; |
| 4256 | 3450 | ||
| @@ -4340,21 +3534,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |||
| 4340 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3534 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4341 | }; | 3535 | }; |
| 4342 | 3536 | ||
| 4343 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { | ||
| 4344 | { | ||
| 4345 | .pa_start = 0x4a304000, | ||
| 4346 | .pa_end = 0x4a30401f, | ||
| 4347 | .flags = ADDR_TYPE_RT | ||
| 4348 | }, | ||
| 4349 | { } | ||
| 4350 | }; | ||
| 4351 | |||
| 4352 | /* l4_wkup -> counter_32k */ | 3537 | /* l4_wkup -> counter_32k */ |
| 4353 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | 3538 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { |
| 4354 | .master = &omap44xx_l4_wkup_hwmod, | 3539 | .master = &omap44xx_l4_wkup_hwmod, |
| 4355 | .slave = &omap44xx_counter_32k_hwmod, | 3540 | .slave = &omap44xx_counter_32k_hwmod, |
| 4356 | .clk = "l4_wkup_clk_mux_ck", | 3541 | .clk = "l4_wkup_clk_mux_ck", |
| 4357 | .addr = omap44xx_counter_32k_addrs, | ||
| 4358 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3542 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4359 | }; | 3543 | }; |
| 4360 | 3544 | ||
| @@ -4430,21 +3614,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |||
| 4430 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3614 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4431 | }; | 3615 | }; |
| 4432 | 3616 | ||
| 4433 | static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { | ||
| 4434 | { | ||
| 4435 | .pa_start = 0x54160000, | ||
| 4436 | .pa_end = 0x54167fff, | ||
| 4437 | .flags = ADDR_TYPE_RT | ||
| 4438 | }, | ||
| 4439 | { } | ||
| 4440 | }; | ||
| 4441 | |||
| 4442 | /* l3_instr -> debugss */ | 3617 | /* l3_instr -> debugss */ |
| 4443 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | 3618 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { |
| 4444 | .master = &omap44xx_l3_instr_hwmod, | 3619 | .master = &omap44xx_l3_instr_hwmod, |
| 4445 | .slave = &omap44xx_debugss_hwmod, | 3620 | .slave = &omap44xx_debugss_hwmod, |
| 4446 | .clk = "l3_div_ck", | 3621 | .clk = "l3_div_ck", |
| 4447 | .addr = omap44xx_debugss_addrs, | ||
| 4448 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3622 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4449 | }; | 3623 | }; |
| 4450 | 3624 | ||
| @@ -4466,41 +3640,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |||
| 4466 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3640 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4467 | }; | 3641 | }; |
| 4468 | 3642 | ||
| 4469 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | ||
| 4470 | { | ||
| 4471 | .name = "mpu", | ||
| 4472 | .pa_start = 0x4012e000, | ||
| 4473 | .pa_end = 0x4012e07f, | ||
| 4474 | .flags = ADDR_TYPE_RT | ||
| 4475 | }, | ||
| 4476 | { } | ||
| 4477 | }; | ||
| 4478 | |||
| 4479 | /* l4_abe -> dmic */ | 3643 | /* l4_abe -> dmic */ |
| 4480 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | 3644 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { |
| 4481 | .master = &omap44xx_l4_abe_hwmod, | 3645 | .master = &omap44xx_l4_abe_hwmod, |
| 4482 | .slave = &omap44xx_dmic_hwmod, | 3646 | .slave = &omap44xx_dmic_hwmod, |
| 4483 | .clk = "ocp_abe_iclk", | 3647 | .clk = "ocp_abe_iclk", |
| 4484 | .addr = omap44xx_dmic_addrs, | ||
| 4485 | .user = OCP_USER_MPU, | 3648 | .user = OCP_USER_MPU, |
| 4486 | }; | 3649 | }; |
| 4487 | 3650 | ||
| 4488 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | ||
| 4489 | { | ||
| 4490 | .name = "dma", | ||
| 4491 | .pa_start = 0x4902e000, | ||
| 4492 | .pa_end = 0x4902e07f, | ||
| 4493 | .flags = ADDR_TYPE_RT | ||
| 4494 | }, | ||
| 4495 | { } | ||
| 4496 | }; | ||
| 4497 | |||
| 4498 | /* l4_abe -> dmic (dma) */ | 3651 | /* l4_abe -> dmic (dma) */ |
| 4499 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | 3652 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { |
| 4500 | .master = &omap44xx_l4_abe_hwmod, | 3653 | .master = &omap44xx_l4_abe_hwmod, |
| 4501 | .slave = &omap44xx_dmic_hwmod, | 3654 | .slave = &omap44xx_dmic_hwmod, |
| 4502 | .clk = "ocp_abe_iclk", | 3655 | .clk = "ocp_abe_iclk", |
| 4503 | .addr = omap44xx_dmic_dma_addrs, | ||
| 4504 | .user = OCP_USER_SDMA, | 3656 | .user = OCP_USER_SDMA, |
| 4505 | }; | 3657 | }; |
| 4506 | 3658 | ||
| @@ -4798,42 +3950,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |||
| 4798 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3950 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4799 | }; | 3951 | }; |
| 4800 | 3952 | ||
| 4801 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { | ||
| 4802 | { | ||
| 4803 | .pa_start = 0x4c000000, | ||
| 4804 | .pa_end = 0x4c0000ff, | ||
| 4805 | .flags = ADDR_TYPE_RT | ||
| 4806 | }, | ||
| 4807 | { } | ||
| 4808 | }; | ||
| 4809 | |||
| 4810 | /* emif_fw -> emif1 */ | ||
| 4811 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | ||
| 4812 | .master = &omap44xx_emif_fw_hwmod, | ||
| 4813 | .slave = &omap44xx_emif1_hwmod, | ||
| 4814 | .clk = "l3_div_ck", | ||
| 4815 | .addr = omap44xx_emif1_addrs, | ||
| 4816 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 4817 | }; | ||
| 4818 | |||
| 4819 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | ||
| 4820 | { | ||
| 4821 | .pa_start = 0x4d000000, | ||
| 4822 | .pa_end = 0x4d0000ff, | ||
| 4823 | .flags = ADDR_TYPE_RT | ||
| 4824 | }, | ||
| 4825 | { } | ||
| 4826 | }; | ||
| 4827 | |||
| 4828 | /* emif_fw -> emif2 */ | ||
| 4829 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | ||
| 4830 | .master = &omap44xx_emif_fw_hwmod, | ||
| 4831 | .slave = &omap44xx_emif2_hwmod, | ||
| 4832 | .clk = "l3_div_ck", | ||
| 4833 | .addr = omap44xx_emif2_addrs, | ||
| 4834 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 4835 | }; | ||
| 4836 | |||
| 4837 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { | 3953 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
| 4838 | { | 3954 | { |
| 4839 | .pa_start = 0x4a10a000, | 3955 | .pa_start = 0x4a10a000, |
| @@ -4852,129 +3968,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |||
| 4852 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3968 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4853 | }; | 3969 | }; |
| 4854 | 3970 | ||
| 4855 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { | ||
| 4856 | { | ||
| 4857 | .pa_start = 0x4a310000, | ||
| 4858 | .pa_end = 0x4a3101ff, | ||
| 4859 | .flags = ADDR_TYPE_RT | ||
| 4860 | }, | ||
| 4861 | { } | ||
| 4862 | }; | ||
| 4863 | |||
| 4864 | /* l4_wkup -> gpio1 */ | 3971 | /* l4_wkup -> gpio1 */ |
| 4865 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | 3972 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { |
| 4866 | .master = &omap44xx_l4_wkup_hwmod, | 3973 | .master = &omap44xx_l4_wkup_hwmod, |
| 4867 | .slave = &omap44xx_gpio1_hwmod, | 3974 | .slave = &omap44xx_gpio1_hwmod, |
| 4868 | .clk = "l4_wkup_clk_mux_ck", | 3975 | .clk = "l4_wkup_clk_mux_ck", |
| 4869 | .addr = omap44xx_gpio1_addrs, | ||
| 4870 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3976 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4871 | }; | 3977 | }; |
| 4872 | 3978 | ||
| 4873 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | ||
| 4874 | { | ||
| 4875 | .pa_start = 0x48055000, | ||
| 4876 | .pa_end = 0x480551ff, | ||
| 4877 | .flags = ADDR_TYPE_RT | ||
| 4878 | }, | ||
| 4879 | { } | ||
| 4880 | }; | ||
| 4881 | |||
| 4882 | /* l4_per -> gpio2 */ | 3979 | /* l4_per -> gpio2 */ |
| 4883 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | 3980 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { |
| 4884 | .master = &omap44xx_l4_per_hwmod, | 3981 | .master = &omap44xx_l4_per_hwmod, |
| 4885 | .slave = &omap44xx_gpio2_hwmod, | 3982 | .slave = &omap44xx_gpio2_hwmod, |
| 4886 | .clk = "l4_div_ck", | 3983 | .clk = "l4_div_ck", |
| 4887 | .addr = omap44xx_gpio2_addrs, | ||
| 4888 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3984 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4889 | }; | 3985 | }; |
| 4890 | 3986 | ||
| 4891 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | ||
| 4892 | { | ||
| 4893 | .pa_start = 0x48057000, | ||
| 4894 | .pa_end = 0x480571ff, | ||
| 4895 | .flags = ADDR_TYPE_RT | ||
| 4896 | }, | ||
| 4897 | { } | ||
| 4898 | }; | ||
| 4899 | |||
| 4900 | /* l4_per -> gpio3 */ | 3987 | /* l4_per -> gpio3 */ |
| 4901 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | 3988 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { |
| 4902 | .master = &omap44xx_l4_per_hwmod, | 3989 | .master = &omap44xx_l4_per_hwmod, |
| 4903 | .slave = &omap44xx_gpio3_hwmod, | 3990 | .slave = &omap44xx_gpio3_hwmod, |
| 4904 | .clk = "l4_div_ck", | 3991 | .clk = "l4_div_ck", |
| 4905 | .addr = omap44xx_gpio3_addrs, | ||
| 4906 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3992 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4907 | }; | 3993 | }; |
| 4908 | 3994 | ||
| 4909 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | ||
| 4910 | { | ||
| 4911 | .pa_start = 0x48059000, | ||
| 4912 | .pa_end = 0x480591ff, | ||
| 4913 | .flags = ADDR_TYPE_RT | ||
| 4914 | }, | ||
| 4915 | { } | ||
| 4916 | }; | ||
| 4917 | |||
| 4918 | /* l4_per -> gpio4 */ | 3995 | /* l4_per -> gpio4 */ |
| 4919 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | 3996 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { |
| 4920 | .master = &omap44xx_l4_per_hwmod, | 3997 | .master = &omap44xx_l4_per_hwmod, |
| 4921 | .slave = &omap44xx_gpio4_hwmod, | 3998 | .slave = &omap44xx_gpio4_hwmod, |
| 4922 | .clk = "l4_div_ck", | 3999 | .clk = "l4_div_ck", |
| 4923 | .addr = omap44xx_gpio4_addrs, | ||
| 4924 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4000 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4925 | }; | 4001 | }; |
| 4926 | 4002 | ||
| 4927 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | ||
| 4928 | { | ||
| 4929 | .pa_start = 0x4805b000, | ||
| 4930 | .pa_end = 0x4805b1ff, | ||
| 4931 | .flags = ADDR_TYPE_RT | ||
| 4932 | }, | ||
| 4933 | { } | ||
| 4934 | }; | ||
| 4935 | |||
| 4936 | /* l4_per -> gpio5 */ | 4003 | /* l4_per -> gpio5 */ |
| 4937 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | 4004 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { |
| 4938 | .master = &omap44xx_l4_per_hwmod, | 4005 | .master = &omap44xx_l4_per_hwmod, |
| 4939 | .slave = &omap44xx_gpio5_hwmod, | 4006 | .slave = &omap44xx_gpio5_hwmod, |
| 4940 | .clk = "l4_div_ck", | 4007 | .clk = "l4_div_ck", |
| 4941 | .addr = omap44xx_gpio5_addrs, | ||
| 4942 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4008 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4943 | }; | 4009 | }; |
| 4944 | 4010 | ||
| 4945 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | ||
| 4946 | { | ||
| 4947 | .pa_start = 0x4805d000, | ||
| 4948 | .pa_end = 0x4805d1ff, | ||
| 4949 | .flags = ADDR_TYPE_RT | ||
| 4950 | }, | ||
| 4951 | { } | ||
| 4952 | }; | ||
| 4953 | |||
| 4954 | /* l4_per -> gpio6 */ | 4011 | /* l4_per -> gpio6 */ |
| 4955 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | 4012 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { |
| 4956 | .master = &omap44xx_l4_per_hwmod, | 4013 | .master = &omap44xx_l4_per_hwmod, |
| 4957 | .slave = &omap44xx_gpio6_hwmod, | 4014 | .slave = &omap44xx_gpio6_hwmod, |
| 4958 | .clk = "l4_div_ck", | 4015 | .clk = "l4_div_ck", |
| 4959 | .addr = omap44xx_gpio6_addrs, | ||
| 4960 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4016 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4961 | }; | 4017 | }; |
| 4962 | 4018 | ||
| 4963 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { | ||
| 4964 | { | ||
| 4965 | .pa_start = 0x50000000, | ||
| 4966 | .pa_end = 0x500003ff, | ||
| 4967 | .flags = ADDR_TYPE_RT | ||
| 4968 | }, | ||
| 4969 | { } | ||
| 4970 | }; | ||
| 4971 | |||
| 4972 | /* l3_main_2 -> gpmc */ | 4019 | /* l3_main_2 -> gpmc */ |
| 4973 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | 4020 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { |
| 4974 | .master = &omap44xx_l3_main_2_hwmod, | 4021 | .master = &omap44xx_l3_main_2_hwmod, |
| 4975 | .slave = &omap44xx_gpmc_hwmod, | 4022 | .slave = &omap44xx_gpmc_hwmod, |
| 4976 | .clk = "l3_div_ck", | 4023 | .clk = "l3_div_ck", |
| 4977 | .addr = omap44xx_gpmc_addrs, | ||
| 4978 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4024 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4979 | }; | 4025 | }; |
| 4980 | 4026 | ||
| @@ -5032,75 +4078,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |||
| 5032 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4078 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5033 | }; | 4079 | }; |
| 5034 | 4080 | ||
| 5035 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | ||
| 5036 | { | ||
| 5037 | .pa_start = 0x48070000, | ||
| 5038 | .pa_end = 0x480700ff, | ||
| 5039 | .flags = ADDR_TYPE_RT | ||
| 5040 | }, | ||
| 5041 | { } | ||
| 5042 | }; | ||
| 5043 | |||
| 5044 | /* l4_per -> i2c1 */ | 4081 | /* l4_per -> i2c1 */ |
| 5045 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | 4082 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { |
| 5046 | .master = &omap44xx_l4_per_hwmod, | 4083 | .master = &omap44xx_l4_per_hwmod, |
| 5047 | .slave = &omap44xx_i2c1_hwmod, | 4084 | .slave = &omap44xx_i2c1_hwmod, |
| 5048 | .clk = "l4_div_ck", | 4085 | .clk = "l4_div_ck", |
| 5049 | .addr = omap44xx_i2c1_addrs, | ||
| 5050 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4086 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5051 | }; | 4087 | }; |
| 5052 | 4088 | ||
| 5053 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | ||
| 5054 | { | ||
| 5055 | .pa_start = 0x48072000, | ||
| 5056 | .pa_end = 0x480720ff, | ||
| 5057 | .flags = ADDR_TYPE_RT | ||
| 5058 | }, | ||
| 5059 | { } | ||
| 5060 | }; | ||
| 5061 | |||
| 5062 | /* l4_per -> i2c2 */ | 4089 | /* l4_per -> i2c2 */ |
| 5063 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | 4090 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { |
| 5064 | .master = &omap44xx_l4_per_hwmod, | 4091 | .master = &omap44xx_l4_per_hwmod, |
| 5065 | .slave = &omap44xx_i2c2_hwmod, | 4092 | .slave = &omap44xx_i2c2_hwmod, |
| 5066 | .clk = "l4_div_ck", | 4093 | .clk = "l4_div_ck", |
| 5067 | .addr = omap44xx_i2c2_addrs, | ||
| 5068 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4094 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5069 | }; | 4095 | }; |
| 5070 | 4096 | ||
| 5071 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | ||
| 5072 | { | ||
| 5073 | .pa_start = 0x48060000, | ||
| 5074 | .pa_end = 0x480600ff, | ||
| 5075 | .flags = ADDR_TYPE_RT | ||
| 5076 | }, | ||
| 5077 | { } | ||
| 5078 | }; | ||
| 5079 | |||
| 5080 | /* l4_per -> i2c3 */ | 4097 | /* l4_per -> i2c3 */ |
| 5081 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | 4098 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { |
| 5082 | .master = &omap44xx_l4_per_hwmod, | 4099 | .master = &omap44xx_l4_per_hwmod, |
| 5083 | .slave = &omap44xx_i2c3_hwmod, | 4100 | .slave = &omap44xx_i2c3_hwmod, |
| 5084 | .clk = "l4_div_ck", | 4101 | .clk = "l4_div_ck", |
| 5085 | .addr = omap44xx_i2c3_addrs, | ||
| 5086 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4102 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5087 | }; | 4103 | }; |
| 5088 | 4104 | ||
| 5089 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | ||
| 5090 | { | ||
| 5091 | .pa_start = 0x48350000, | ||
| 5092 | .pa_end = 0x483500ff, | ||
| 5093 | .flags = ADDR_TYPE_RT | ||
| 5094 | }, | ||
| 5095 | { } | ||
| 5096 | }; | ||
| 5097 | |||
| 5098 | /* l4_per -> i2c4 */ | 4105 | /* l4_per -> i2c4 */ |
| 5099 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | 4106 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { |
| 5100 | .master = &omap44xx_l4_per_hwmod, | 4107 | .master = &omap44xx_l4_per_hwmod, |
| 5101 | .slave = &omap44xx_i2c4_hwmod, | 4108 | .slave = &omap44xx_i2c4_hwmod, |
| 5102 | .clk = "l4_div_ck", | 4109 | .clk = "l4_div_ck", |
| 5103 | .addr = omap44xx_i2c4_addrs, | ||
| 5104 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4110 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5105 | }; | 4111 | }; |
| 5106 | 4112 | ||
| @@ -5138,39 +4144,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { | |||
| 5138 | .user = OCP_USER_IVA, | 4144 | .user = OCP_USER_IVA, |
| 5139 | }; | 4145 | }; |
| 5140 | 4146 | ||
| 5141 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | ||
| 5142 | { | ||
| 5143 | .pa_start = 0x5a000000, | ||
| 5144 | .pa_end = 0x5a07ffff, | ||
| 5145 | .flags = ADDR_TYPE_RT | ||
| 5146 | }, | ||
| 5147 | { } | ||
| 5148 | }; | ||
| 5149 | |||
| 5150 | /* l3_main_2 -> iva */ | 4147 | /* l3_main_2 -> iva */ |
| 5151 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | 4148 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { |
| 5152 | .master = &omap44xx_l3_main_2_hwmod, | 4149 | .master = &omap44xx_l3_main_2_hwmod, |
| 5153 | .slave = &omap44xx_iva_hwmod, | 4150 | .slave = &omap44xx_iva_hwmod, |
| 5154 | .clk = "l3_div_ck", | 4151 | .clk = "l3_div_ck", |
| 5155 | .addr = omap44xx_iva_addrs, | ||
| 5156 | .user = OCP_USER_MPU, | 4152 | .user = OCP_USER_MPU, |
| 5157 | }; | 4153 | }; |
| 5158 | 4154 | ||
| 5159 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | ||
| 5160 | { | ||
| 5161 | .pa_start = 0x4a31c000, | ||
| 5162 | .pa_end = 0x4a31c07f, | ||
| 5163 | .flags = ADDR_TYPE_RT | ||
| 5164 | }, | ||
| 5165 | { } | ||
| 5166 | }; | ||
| 5167 | |||
| 5168 | /* l4_wkup -> kbd */ | 4155 | /* l4_wkup -> kbd */ |
| 5169 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | 4156 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { |
| 5170 | .master = &omap44xx_l4_wkup_hwmod, | 4157 | .master = &omap44xx_l4_wkup_hwmod, |
| 5171 | .slave = &omap44xx_kbd_hwmod, | 4158 | .slave = &omap44xx_kbd_hwmod, |
| 5172 | .clk = "l4_wkup_clk_mux_ck", | 4159 | .clk = "l4_wkup_clk_mux_ck", |
| 5173 | .addr = omap44xx_kbd_addrs, | ||
| 5174 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4160 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5175 | }; | 4161 | }; |
| 5176 | 4162 | ||
| @@ -5228,335 +4214,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |||
| 5228 | .user = OCP_USER_SDMA, | 4214 | .user = OCP_USER_SDMA, |
| 5229 | }; | 4215 | }; |
| 5230 | 4216 | ||
| 5231 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { | ||
| 5232 | { | ||
| 5233 | .name = "mpu", | ||
| 5234 | .pa_start = 0x40122000, | ||
| 5235 | .pa_end = 0x401220ff, | ||
| 5236 | .flags = ADDR_TYPE_RT | ||
| 5237 | }, | ||
| 5238 | { } | ||
| 5239 | }; | ||
| 5240 | |||
| 5241 | /* l4_abe -> mcbsp1 */ | 4217 | /* l4_abe -> mcbsp1 */ |
| 5242 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | 4218 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { |
| 5243 | .master = &omap44xx_l4_abe_hwmod, | 4219 | .master = &omap44xx_l4_abe_hwmod, |
| 5244 | .slave = &omap44xx_mcbsp1_hwmod, | 4220 | .slave = &omap44xx_mcbsp1_hwmod, |
| 5245 | .clk = "ocp_abe_iclk", | 4221 | .clk = "ocp_abe_iclk", |
| 5246 | .addr = omap44xx_mcbsp1_addrs, | ||
| 5247 | .user = OCP_USER_MPU, | 4222 | .user = OCP_USER_MPU, |
| 5248 | }; | 4223 | }; |
| 5249 | 4224 | ||
| 5250 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | ||
| 5251 | { | ||
| 5252 | .name = "dma", | ||
| 5253 | .pa_start = 0x49022000, | ||
| 5254 | .pa_end = 0x490220ff, | ||
| 5255 | .flags = ADDR_TYPE_RT | ||
| 5256 | }, | ||
| 5257 | { } | ||
| 5258 | }; | ||
| 5259 | |||
| 5260 | /* l4_abe -> mcbsp1 (dma) */ | 4225 | /* l4_abe -> mcbsp1 (dma) */ |
| 5261 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | 4226 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { |
| 5262 | .master = &omap44xx_l4_abe_hwmod, | 4227 | .master = &omap44xx_l4_abe_hwmod, |
| 5263 | .slave = &omap44xx_mcbsp1_hwmod, | 4228 | .slave = &omap44xx_mcbsp1_hwmod, |
| 5264 | .clk = "ocp_abe_iclk", | 4229 | .clk = "ocp_abe_iclk", |
| 5265 | .addr = omap44xx_mcbsp1_dma_addrs, | ||
| 5266 | .user = OCP_USER_SDMA, | 4230 | .user = OCP_USER_SDMA, |
| 5267 | }; | 4231 | }; |
| 5268 | 4232 | ||
| 5269 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | ||
| 5270 | { | ||
| 5271 | .name = "mpu", | ||
| 5272 | .pa_start = 0x40124000, | ||
| 5273 | .pa_end = 0x401240ff, | ||
| 5274 | .flags = ADDR_TYPE_RT | ||
| 5275 | }, | ||
| 5276 | { } | ||
| 5277 | }; | ||
| 5278 | |||
| 5279 | /* l4_abe -> mcbsp2 */ | 4233 | /* l4_abe -> mcbsp2 */ |
| 5280 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | 4234 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { |
| 5281 | .master = &omap44xx_l4_abe_hwmod, | 4235 | .master = &omap44xx_l4_abe_hwmod, |
| 5282 | .slave = &omap44xx_mcbsp2_hwmod, | 4236 | .slave = &omap44xx_mcbsp2_hwmod, |
| 5283 | .clk = "ocp_abe_iclk", | 4237 | .clk = "ocp_abe_iclk", |
| 5284 | .addr = omap44xx_mcbsp2_addrs, | ||
| 5285 | .user = OCP_USER_MPU, | 4238 | .user = OCP_USER_MPU, |
| 5286 | }; | 4239 | }; |
| 5287 | 4240 | ||
| 5288 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | ||
| 5289 | { | ||
| 5290 | .name = "dma", | ||
| 5291 | .pa_start = 0x49024000, | ||
| 5292 | .pa_end = 0x490240ff, | ||
| 5293 | .flags = ADDR_TYPE_RT | ||
| 5294 | }, | ||
| 5295 | { } | ||
| 5296 | }; | ||
| 5297 | |||
| 5298 | /* l4_abe -> mcbsp2 (dma) */ | 4241 | /* l4_abe -> mcbsp2 (dma) */ |
| 5299 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | 4242 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { |
| 5300 | .master = &omap44xx_l4_abe_hwmod, | 4243 | .master = &omap44xx_l4_abe_hwmod, |
| 5301 | .slave = &omap44xx_mcbsp2_hwmod, | 4244 | .slave = &omap44xx_mcbsp2_hwmod, |
| 5302 | .clk = "ocp_abe_iclk", | 4245 | .clk = "ocp_abe_iclk", |
| 5303 | .addr = omap44xx_mcbsp2_dma_addrs, | ||
| 5304 | .user = OCP_USER_SDMA, | 4246 | .user = OCP_USER_SDMA, |
| 5305 | }; | 4247 | }; |
| 5306 | 4248 | ||
| 5307 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | ||
| 5308 | { | ||
| 5309 | .name = "mpu", | ||
| 5310 | .pa_start = 0x40126000, | ||
| 5311 | .pa_end = 0x401260ff, | ||
| 5312 | .flags = ADDR_TYPE_RT | ||
| 5313 | }, | ||
| 5314 | { } | ||
| 5315 | }; | ||
| 5316 | |||
| 5317 | /* l4_abe -> mcbsp3 */ | 4249 | /* l4_abe -> mcbsp3 */ |
| 5318 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | 4250 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { |
| 5319 | .master = &omap44xx_l4_abe_hwmod, | 4251 | .master = &omap44xx_l4_abe_hwmod, |
| 5320 | .slave = &omap44xx_mcbsp3_hwmod, | 4252 | .slave = &omap44xx_mcbsp3_hwmod, |
| 5321 | .clk = "ocp_abe_iclk", | 4253 | .clk = "ocp_abe_iclk", |
| 5322 | .addr = omap44xx_mcbsp3_addrs, | ||
| 5323 | .user = OCP_USER_MPU, | 4254 | .user = OCP_USER_MPU, |
| 5324 | }; | 4255 | }; |
| 5325 | 4256 | ||
| 5326 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | ||
| 5327 | { | ||
| 5328 | .name = "dma", | ||
| 5329 | .pa_start = 0x49026000, | ||
| 5330 | .pa_end = 0x490260ff, | ||
| 5331 | .flags = ADDR_TYPE_RT | ||
| 5332 | }, | ||
| 5333 | { } | ||
| 5334 | }; | ||
| 5335 | |||
| 5336 | /* l4_abe -> mcbsp3 (dma) */ | 4257 | /* l4_abe -> mcbsp3 (dma) */ |
| 5337 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | 4258 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { |
| 5338 | .master = &omap44xx_l4_abe_hwmod, | 4259 | .master = &omap44xx_l4_abe_hwmod, |
| 5339 | .slave = &omap44xx_mcbsp3_hwmod, | 4260 | .slave = &omap44xx_mcbsp3_hwmod, |
| 5340 | .clk = "ocp_abe_iclk", | 4261 | .clk = "ocp_abe_iclk", |
| 5341 | .addr = omap44xx_mcbsp3_dma_addrs, | ||
| 5342 | .user = OCP_USER_SDMA, | 4262 | .user = OCP_USER_SDMA, |
| 5343 | }; | 4263 | }; |
| 5344 | 4264 | ||
| 5345 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | ||
| 5346 | { | ||
| 5347 | .pa_start = 0x48096000, | ||
| 5348 | .pa_end = 0x480960ff, | ||
| 5349 | .flags = ADDR_TYPE_RT | ||
| 5350 | }, | ||
| 5351 | { } | ||
| 5352 | }; | ||
| 5353 | |||
| 5354 | /* l4_per -> mcbsp4 */ | 4265 | /* l4_per -> mcbsp4 */ |
| 5355 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | 4266 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { |
| 5356 | .master = &omap44xx_l4_per_hwmod, | 4267 | .master = &omap44xx_l4_per_hwmod, |
| 5357 | .slave = &omap44xx_mcbsp4_hwmod, | 4268 | .slave = &omap44xx_mcbsp4_hwmod, |
| 5358 | .clk = "l4_div_ck", | 4269 | .clk = "l4_div_ck", |
| 5359 | .addr = omap44xx_mcbsp4_addrs, | ||
| 5360 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4270 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5361 | }; | 4271 | }; |
| 5362 | 4272 | ||
| 5363 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | ||
| 5364 | { | ||
| 5365 | .name = "mpu", | ||
| 5366 | .pa_start = 0x40132000, | ||
| 5367 | .pa_end = 0x4013207f, | ||
| 5368 | .flags = ADDR_TYPE_RT | ||
| 5369 | }, | ||
| 5370 | { } | ||
| 5371 | }; | ||
| 5372 | |||
| 5373 | /* l4_abe -> mcpdm */ | 4273 | /* l4_abe -> mcpdm */ |
| 5374 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | 4274 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { |
| 5375 | .master = &omap44xx_l4_abe_hwmod, | 4275 | .master = &omap44xx_l4_abe_hwmod, |
| 5376 | .slave = &omap44xx_mcpdm_hwmod, | 4276 | .slave = &omap44xx_mcpdm_hwmod, |
| 5377 | .clk = "ocp_abe_iclk", | 4277 | .clk = "ocp_abe_iclk", |
| 5378 | .addr = omap44xx_mcpdm_addrs, | ||
| 5379 | .user = OCP_USER_MPU, | 4278 | .user = OCP_USER_MPU, |
| 5380 | }; | 4279 | }; |
| 5381 | 4280 | ||
| 5382 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | ||
| 5383 | { | ||
| 5384 | .name = "dma", | ||
| 5385 | .pa_start = 0x49032000, | ||
| 5386 | .pa_end = 0x4903207f, | ||
| 5387 | .flags = ADDR_TYPE_RT | ||
| 5388 | }, | ||
| 5389 | { } | ||
| 5390 | }; | ||
| 5391 | |||
| 5392 | /* l4_abe -> mcpdm (dma) */ | 4281 | /* l4_abe -> mcpdm (dma) */ |
| 5393 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | 4282 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { |
| 5394 | .master = &omap44xx_l4_abe_hwmod, | 4283 | .master = &omap44xx_l4_abe_hwmod, |
| 5395 | .slave = &omap44xx_mcpdm_hwmod, | 4284 | .slave = &omap44xx_mcpdm_hwmod, |
| 5396 | .clk = "ocp_abe_iclk", | 4285 | .clk = "ocp_abe_iclk", |
| 5397 | .addr = omap44xx_mcpdm_dma_addrs, | ||
| 5398 | .user = OCP_USER_SDMA, | 4286 | .user = OCP_USER_SDMA, |
| 5399 | }; | 4287 | }; |
| 5400 | 4288 | ||
| 5401 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | ||
| 5402 | { | ||
| 5403 | .pa_start = 0x48098000, | ||
| 5404 | .pa_end = 0x480981ff, | ||
| 5405 | .flags = ADDR_TYPE_RT | ||
| 5406 | }, | ||
| 5407 | { } | ||
| 5408 | }; | ||
| 5409 | |||
| 5410 | /* l4_per -> mcspi1 */ | 4289 | /* l4_per -> mcspi1 */ |
| 5411 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | 4290 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { |
| 5412 | .master = &omap44xx_l4_per_hwmod, | 4291 | .master = &omap44xx_l4_per_hwmod, |
| 5413 | .slave = &omap44xx_mcspi1_hwmod, | 4292 | .slave = &omap44xx_mcspi1_hwmod, |
| 5414 | .clk = "l4_div_ck", | 4293 | .clk = "l4_div_ck", |
| 5415 | .addr = omap44xx_mcspi1_addrs, | ||
| 5416 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4294 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5417 | }; | 4295 | }; |
| 5418 | 4296 | ||
| 5419 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | ||
| 5420 | { | ||
| 5421 | .pa_start = 0x4809a000, | ||
| 5422 | .pa_end = 0x4809a1ff, | ||
| 5423 | .flags = ADDR_TYPE_RT | ||
| 5424 | }, | ||
| 5425 | { } | ||
| 5426 | }; | ||
| 5427 | |||
| 5428 | /* l4_per -> mcspi2 */ | 4297 | /* l4_per -> mcspi2 */ |
| 5429 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | 4298 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { |
| 5430 | .master = &omap44xx_l4_per_hwmod, | 4299 | .master = &omap44xx_l4_per_hwmod, |
| 5431 | .slave = &omap44xx_mcspi2_hwmod, | 4300 | .slave = &omap44xx_mcspi2_hwmod, |
| 5432 | .clk = "l4_div_ck", | 4301 | .clk = "l4_div_ck", |
| 5433 | .addr = omap44xx_mcspi2_addrs, | ||
| 5434 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5435 | }; | 4303 | }; |
| 5436 | 4304 | ||
| 5437 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | ||
| 5438 | { | ||
| 5439 | .pa_start = 0x480b8000, | ||
| 5440 | .pa_end = 0x480b81ff, | ||
| 5441 | .flags = ADDR_TYPE_RT | ||
| 5442 | }, | ||
| 5443 | { } | ||
| 5444 | }; | ||
| 5445 | |||
| 5446 | /* l4_per -> mcspi3 */ | 4305 | /* l4_per -> mcspi3 */ |
| 5447 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | 4306 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { |
| 5448 | .master = &omap44xx_l4_per_hwmod, | 4307 | .master = &omap44xx_l4_per_hwmod, |
| 5449 | .slave = &omap44xx_mcspi3_hwmod, | 4308 | .slave = &omap44xx_mcspi3_hwmod, |
| 5450 | .clk = "l4_div_ck", | 4309 | .clk = "l4_div_ck", |
| 5451 | .addr = omap44xx_mcspi3_addrs, | ||
| 5452 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4310 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5453 | }; | 4311 | }; |
| 5454 | 4312 | ||
| 5455 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | ||
| 5456 | { | ||
| 5457 | .pa_start = 0x480ba000, | ||
| 5458 | .pa_end = 0x480ba1ff, | ||
| 5459 | .flags = ADDR_TYPE_RT | ||
| 5460 | }, | ||
| 5461 | { } | ||
| 5462 | }; | ||
| 5463 | |||
| 5464 | /* l4_per -> mcspi4 */ | 4313 | /* l4_per -> mcspi4 */ |
| 5465 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | 4314 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { |
| 5466 | .master = &omap44xx_l4_per_hwmod, | 4315 | .master = &omap44xx_l4_per_hwmod, |
| 5467 | .slave = &omap44xx_mcspi4_hwmod, | 4316 | .slave = &omap44xx_mcspi4_hwmod, |
| 5468 | .clk = "l4_div_ck", | 4317 | .clk = "l4_div_ck", |
| 5469 | .addr = omap44xx_mcspi4_addrs, | ||
| 5470 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4318 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5471 | }; | 4319 | }; |
| 5472 | 4320 | ||
| 5473 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | ||
| 5474 | { | ||
| 5475 | .pa_start = 0x4809c000, | ||
| 5476 | .pa_end = 0x4809c3ff, | ||
| 5477 | .flags = ADDR_TYPE_RT | ||
| 5478 | }, | ||
| 5479 | { } | ||
| 5480 | }; | ||
| 5481 | |||
| 5482 | /* l4_per -> mmc1 */ | 4321 | /* l4_per -> mmc1 */ |
| 5483 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | 4322 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { |
| 5484 | .master = &omap44xx_l4_per_hwmod, | 4323 | .master = &omap44xx_l4_per_hwmod, |
| 5485 | .slave = &omap44xx_mmc1_hwmod, | 4324 | .slave = &omap44xx_mmc1_hwmod, |
| 5486 | .clk = "l4_div_ck", | 4325 | .clk = "l4_div_ck", |
| 5487 | .addr = omap44xx_mmc1_addrs, | ||
| 5488 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4326 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5489 | }; | 4327 | }; |
| 5490 | 4328 | ||
| 5491 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | ||
| 5492 | { | ||
| 5493 | .pa_start = 0x480b4000, | ||
| 5494 | .pa_end = 0x480b43ff, | ||
| 5495 | .flags = ADDR_TYPE_RT | ||
| 5496 | }, | ||
| 5497 | { } | ||
| 5498 | }; | ||
| 5499 | |||
| 5500 | /* l4_per -> mmc2 */ | 4329 | /* l4_per -> mmc2 */ |
| 5501 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | 4330 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { |
| 5502 | .master = &omap44xx_l4_per_hwmod, | 4331 | .master = &omap44xx_l4_per_hwmod, |
| 5503 | .slave = &omap44xx_mmc2_hwmod, | 4332 | .slave = &omap44xx_mmc2_hwmod, |
| 5504 | .clk = "l4_div_ck", | 4333 | .clk = "l4_div_ck", |
| 5505 | .addr = omap44xx_mmc2_addrs, | ||
| 5506 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4334 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5507 | }; | 4335 | }; |
| 5508 | 4336 | ||
| 5509 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | ||
| 5510 | { | ||
| 5511 | .pa_start = 0x480ad000, | ||
| 5512 | .pa_end = 0x480ad3ff, | ||
| 5513 | .flags = ADDR_TYPE_RT | ||
| 5514 | }, | ||
| 5515 | { } | ||
| 5516 | }; | ||
| 5517 | |||
| 5518 | /* l4_per -> mmc3 */ | 4337 | /* l4_per -> mmc3 */ |
| 5519 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | 4338 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { |
| 5520 | .master = &omap44xx_l4_per_hwmod, | 4339 | .master = &omap44xx_l4_per_hwmod, |
| 5521 | .slave = &omap44xx_mmc3_hwmod, | 4340 | .slave = &omap44xx_mmc3_hwmod, |
| 5522 | .clk = "l4_div_ck", | 4341 | .clk = "l4_div_ck", |
| 5523 | .addr = omap44xx_mmc3_addrs, | ||
| 5524 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4342 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5525 | }; | 4343 | }; |
| 5526 | 4344 | ||
| 5527 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | ||
| 5528 | { | ||
| 5529 | .pa_start = 0x480d1000, | ||
| 5530 | .pa_end = 0x480d13ff, | ||
| 5531 | .flags = ADDR_TYPE_RT | ||
| 5532 | }, | ||
| 5533 | { } | ||
| 5534 | }; | ||
| 5535 | |||
| 5536 | /* l4_per -> mmc4 */ | 4345 | /* l4_per -> mmc4 */ |
| 5537 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | 4346 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { |
| 5538 | .master = &omap44xx_l4_per_hwmod, | 4347 | .master = &omap44xx_l4_per_hwmod, |
| 5539 | .slave = &omap44xx_mmc4_hwmod, | 4348 | .slave = &omap44xx_mmc4_hwmod, |
| 5540 | .clk = "l4_div_ck", | 4349 | .clk = "l4_div_ck", |
| 5541 | .addr = omap44xx_mmc4_addrs, | ||
| 5542 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4350 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5543 | }; | 4351 | }; |
| 5544 | 4352 | ||
| 5545 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | ||
| 5546 | { | ||
| 5547 | .pa_start = 0x480d5000, | ||
| 5548 | .pa_end = 0x480d53ff, | ||
| 5549 | .flags = ADDR_TYPE_RT | ||
| 5550 | }, | ||
| 5551 | { } | ||
| 5552 | }; | ||
| 5553 | |||
| 5554 | /* l4_per -> mmc5 */ | 4353 | /* l4_per -> mmc5 */ |
| 5555 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | 4354 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { |
| 5556 | .master = &omap44xx_l4_per_hwmod, | 4355 | .master = &omap44xx_l4_per_hwmod, |
| 5557 | .slave = &omap44xx_mmc5_hwmod, | 4356 | .slave = &omap44xx_mmc5_hwmod, |
| 5558 | .clk = "l4_div_ck", | 4357 | .clk = "l4_div_ck", |
| 5559 | .addr = omap44xx_mmc5_addrs, | ||
| 5560 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4358 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5561 | }; | 4359 | }; |
| 5562 | 4360 | ||
| @@ -5568,111 +4366,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |||
| 5568 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4366 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5569 | }; | 4367 | }; |
| 5570 | 4368 | ||
| 5571 | static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { | ||
| 5572 | { | ||
| 5573 | .pa_start = 0x4a0ad000, | ||
| 5574 | .pa_end = 0x4a0ad01f, | ||
| 5575 | .flags = ADDR_TYPE_RT | ||
| 5576 | }, | ||
| 5577 | { } | ||
| 5578 | }; | ||
| 5579 | |||
| 5580 | /* l4_cfg -> ocp2scp_usb_phy */ | 4369 | /* l4_cfg -> ocp2scp_usb_phy */ |
| 5581 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | 4370 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { |
| 5582 | .master = &omap44xx_l4_cfg_hwmod, | 4371 | .master = &omap44xx_l4_cfg_hwmod, |
| 5583 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | 4372 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, |
| 5584 | .clk = "l4_div_ck", | 4373 | .clk = "l4_div_ck", |
| 5585 | .addr = omap44xx_ocp2scp_usb_phy_addrs, | ||
| 5586 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4374 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5587 | }; | 4375 | }; |
| 5588 | 4376 | ||
| 5589 | static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { | ||
| 5590 | { | ||
| 5591 | .pa_start = 0x48243000, | ||
| 5592 | .pa_end = 0x48243fff, | ||
| 5593 | .flags = ADDR_TYPE_RT | ||
| 5594 | }, | ||
| 5595 | { } | ||
| 5596 | }; | ||
| 5597 | |||
| 5598 | /* mpu_private -> prcm_mpu */ | 4377 | /* mpu_private -> prcm_mpu */ |
| 5599 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | 4378 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { |
| 5600 | .master = &omap44xx_mpu_private_hwmod, | 4379 | .master = &omap44xx_mpu_private_hwmod, |
| 5601 | .slave = &omap44xx_prcm_mpu_hwmod, | 4380 | .slave = &omap44xx_prcm_mpu_hwmod, |
| 5602 | .clk = "l3_div_ck", | 4381 | .clk = "l3_div_ck", |
| 5603 | .addr = omap44xx_prcm_mpu_addrs, | ||
| 5604 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4382 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5605 | }; | 4383 | }; |
| 5606 | 4384 | ||
| 5607 | static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { | ||
| 5608 | { | ||
| 5609 | .pa_start = 0x4a004000, | ||
| 5610 | .pa_end = 0x4a004fff, | ||
| 5611 | .flags = ADDR_TYPE_RT | ||
| 5612 | }, | ||
| 5613 | { } | ||
| 5614 | }; | ||
| 5615 | |||
| 5616 | /* l4_wkup -> cm_core_aon */ | 4385 | /* l4_wkup -> cm_core_aon */ |
| 5617 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | 4386 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { |
| 5618 | .master = &omap44xx_l4_wkup_hwmod, | 4387 | .master = &omap44xx_l4_wkup_hwmod, |
| 5619 | .slave = &omap44xx_cm_core_aon_hwmod, | 4388 | .slave = &omap44xx_cm_core_aon_hwmod, |
| 5620 | .clk = "l4_wkup_clk_mux_ck", | 4389 | .clk = "l4_wkup_clk_mux_ck", |
| 5621 | .addr = omap44xx_cm_core_aon_addrs, | ||
| 5622 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4390 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5623 | }; | 4391 | }; |
| 5624 | 4392 | ||
| 5625 | static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { | ||
| 5626 | { | ||
| 5627 | .pa_start = 0x4a008000, | ||
| 5628 | .pa_end = 0x4a009fff, | ||
| 5629 | .flags = ADDR_TYPE_RT | ||
| 5630 | }, | ||
| 5631 | { } | ||
| 5632 | }; | ||
| 5633 | |||
| 5634 | /* l4_cfg -> cm_core */ | 4393 | /* l4_cfg -> cm_core */ |
| 5635 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | 4394 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { |
| 5636 | .master = &omap44xx_l4_cfg_hwmod, | 4395 | .master = &omap44xx_l4_cfg_hwmod, |
| 5637 | .slave = &omap44xx_cm_core_hwmod, | 4396 | .slave = &omap44xx_cm_core_hwmod, |
| 5638 | .clk = "l4_div_ck", | 4397 | .clk = "l4_div_ck", |
| 5639 | .addr = omap44xx_cm_core_addrs, | ||
| 5640 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4398 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5641 | }; | 4399 | }; |
| 5642 | 4400 | ||
| 5643 | static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { | ||
| 5644 | { | ||
| 5645 | .pa_start = 0x4a306000, | ||
| 5646 | .pa_end = 0x4a307fff, | ||
| 5647 | .flags = ADDR_TYPE_RT | ||
| 5648 | }, | ||
| 5649 | { } | ||
| 5650 | }; | ||
| 5651 | |||
| 5652 | /* l4_wkup -> prm */ | 4401 | /* l4_wkup -> prm */ |
| 5653 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | 4402 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { |
| 5654 | .master = &omap44xx_l4_wkup_hwmod, | 4403 | .master = &omap44xx_l4_wkup_hwmod, |
| 5655 | .slave = &omap44xx_prm_hwmod, | 4404 | .slave = &omap44xx_prm_hwmod, |
| 5656 | .clk = "l4_wkup_clk_mux_ck", | 4405 | .clk = "l4_wkup_clk_mux_ck", |
| 5657 | .addr = omap44xx_prm_addrs, | ||
| 5658 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4406 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5659 | }; | 4407 | }; |
| 5660 | 4408 | ||
| 5661 | static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { | ||
| 5662 | { | ||
| 5663 | .pa_start = 0x4a30a000, | ||
| 5664 | .pa_end = 0x4a30a7ff, | ||
| 5665 | .flags = ADDR_TYPE_RT | ||
| 5666 | }, | ||
| 5667 | { } | ||
| 5668 | }; | ||
| 5669 | |||
| 5670 | /* l4_wkup -> scrm */ | 4409 | /* l4_wkup -> scrm */ |
| 5671 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | 4410 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { |
| 5672 | .master = &omap44xx_l4_wkup_hwmod, | 4411 | .master = &omap44xx_l4_wkup_hwmod, |
| 5673 | .slave = &omap44xx_scrm_hwmod, | 4412 | .slave = &omap44xx_scrm_hwmod, |
| 5674 | .clk = "l4_wkup_clk_mux_ck", | 4413 | .clk = "l4_wkup_clk_mux_ck", |
| 5675 | .addr = omap44xx_scrm_addrs, | ||
| 5676 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4414 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5677 | }; | 4415 | }; |
| 5678 | 4416 | ||
| @@ -5810,447 +4548,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |||
| 5810 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4548 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5811 | }; | 4549 | }; |
| 5812 | 4550 | ||
| 5813 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | ||
| 5814 | { | ||
| 5815 | .pa_start = 0x4a318000, | ||
| 5816 | .pa_end = 0x4a31807f, | ||
| 5817 | .flags = ADDR_TYPE_RT | ||
| 5818 | }, | ||
| 5819 | { } | ||
| 5820 | }; | ||
| 5821 | |||
| 5822 | /* l4_wkup -> timer1 */ | 4551 | /* l4_wkup -> timer1 */ |
| 5823 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | 4552 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { |
| 5824 | .master = &omap44xx_l4_wkup_hwmod, | 4553 | .master = &omap44xx_l4_wkup_hwmod, |
| 5825 | .slave = &omap44xx_timer1_hwmod, | 4554 | .slave = &omap44xx_timer1_hwmod, |
| 5826 | .clk = "l4_wkup_clk_mux_ck", | 4555 | .clk = "l4_wkup_clk_mux_ck", |
| 5827 | .addr = omap44xx_timer1_addrs, | ||
| 5828 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4556 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5829 | }; | 4557 | }; |
| 5830 | 4558 | ||
| 5831 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | ||
| 5832 | { | ||
| 5833 | .pa_start = 0x48032000, | ||
| 5834 | .pa_end = 0x4803207f, | ||
| 5835 | .flags = ADDR_TYPE_RT | ||
| 5836 | }, | ||
| 5837 | { } | ||
| 5838 | }; | ||
| 5839 | |||
| 5840 | /* l4_per -> timer2 */ | 4559 | /* l4_per -> timer2 */ |
| 5841 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | 4560 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { |
| 5842 | .master = &omap44xx_l4_per_hwmod, | 4561 | .master = &omap44xx_l4_per_hwmod, |
| 5843 | .slave = &omap44xx_timer2_hwmod, | 4562 | .slave = &omap44xx_timer2_hwmod, |
| 5844 | .clk = "l4_div_ck", | 4563 | .clk = "l4_div_ck", |
| 5845 | .addr = omap44xx_timer2_addrs, | ||
| 5846 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4564 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5847 | }; | 4565 | }; |
| 5848 | 4566 | ||
| 5849 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | ||
| 5850 | { | ||
| 5851 | .pa_start = 0x48034000, | ||
| 5852 | .pa_end = 0x4803407f, | ||
| 5853 | .flags = ADDR_TYPE_RT | ||
| 5854 | }, | ||
| 5855 | { } | ||
| 5856 | }; | ||
| 5857 | |||
| 5858 | /* l4_per -> timer3 */ | 4567 | /* l4_per -> timer3 */ |
| 5859 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | 4568 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { |
| 5860 | .master = &omap44xx_l4_per_hwmod, | 4569 | .master = &omap44xx_l4_per_hwmod, |
| 5861 | .slave = &omap44xx_timer3_hwmod, | 4570 | .slave = &omap44xx_timer3_hwmod, |
| 5862 | .clk = "l4_div_ck", | 4571 | .clk = "l4_div_ck", |
| 5863 | .addr = omap44xx_timer3_addrs, | ||
| 5864 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4572 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5865 | }; | 4573 | }; |
| 5866 | 4574 | ||
| 5867 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | ||
| 5868 | { | ||
| 5869 | .pa_start = 0x48036000, | ||
| 5870 | .pa_end = 0x4803607f, | ||
| 5871 | .flags = ADDR_TYPE_RT | ||
| 5872 | }, | ||
| 5873 | { } | ||
| 5874 | }; | ||
| 5875 | |||
| 5876 | /* l4_per -> timer4 */ | 4575 | /* l4_per -> timer4 */ |
| 5877 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | 4576 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { |
| 5878 | .master = &omap44xx_l4_per_hwmod, | 4577 | .master = &omap44xx_l4_per_hwmod, |
| 5879 | .slave = &omap44xx_timer4_hwmod, | 4578 | .slave = &omap44xx_timer4_hwmod, |
| 5880 | .clk = "l4_div_ck", | 4579 | .clk = "l4_div_ck", |
| 5881 | .addr = omap44xx_timer4_addrs, | ||
| 5882 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4580 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 5883 | }; | 4581 | }; |
| 5884 | 4582 | ||
| 5885 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | ||
| 5886 | { | ||
| 5887 | .pa_start = 0x40138000, | ||
| 5888 | .pa_end = 0x4013807f, | ||
| 5889 | .flags = ADDR_TYPE_RT | ||
| 5890 | }, | ||
| 5891 | { } | ||
| 5892 | }; | ||
| 5893 | |||
| 5894 | /* l4_abe -> timer5 */ | 4583 | /* l4_abe -> timer5 */ |
| 5895 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | 4584 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { |
| 5896 | .master = &omap44xx_l4_abe_hwmod, | 4585 | .master = &omap44xx_l4_abe_hwmod, |
| 5897 | .slave = &omap44xx_timer5_hwmod, | 4586 | .slave = &omap44xx_timer5_hwmod, |
| 5898 | .clk = "ocp_abe_iclk", | 4587 | .clk = "ocp_abe_iclk", |
| 5899 | .addr = omap44xx_timer5_addrs, | ||
| 5900 | .user = OCP_USER_MPU, | 4588 | .user = OCP_USER_MPU, |
| 5901 | }; | 4589 | }; |
| 5902 | 4590 | ||
| 5903 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | ||
| 5904 | { | ||
| 5905 | .pa_start = 0x49038000, | ||
| 5906 | .pa_end = 0x4903807f, | ||
| 5907 | .flags = ADDR_TYPE_RT | ||
| 5908 | }, | ||
| 5909 | { } | ||
| 5910 | }; | ||
| 5911 | |||
| 5912 | /* l4_abe -> timer5 (dma) */ | 4591 | /* l4_abe -> timer5 (dma) */ |
| 5913 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | 4592 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { |
| 5914 | .master = &omap44xx_l4_abe_hwmod, | 4593 | .master = &omap44xx_l4_abe_hwmod, |
| 5915 | .slave = &omap44xx_timer5_hwmod, | 4594 | .slave = &omap44xx_timer5_hwmod, |
| 5916 | .clk = "ocp_abe_iclk", | 4595 | .clk = "ocp_abe_iclk", |
| 5917 | .addr = omap44xx_timer5_dma_addrs, | ||
| 5918 | .user = OCP_USER_SDMA, | 4596 | .user = OCP_USER_SDMA, |
| 5919 | }; | 4597 | }; |
| 5920 | 4598 | ||
| 5921 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | ||
| 5922 | { | ||
| 5923 | .pa_start = 0x4013a000, | ||
| 5924 | .pa_end = 0x4013a07f, | ||
| 5925 | .flags = ADDR_TYPE_RT | ||
| 5926 | }, | ||
| 5927 | { } | ||
| 5928 | }; | ||
| 5929 | |||
| 5930 | /* l4_abe -> timer6 */ | 4599 | /* l4_abe -> timer6 */ |
| 5931 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | 4600 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { |
| 5932 | .master = &omap44xx_l4_abe_hwmod, | 4601 | .master = &omap44xx_l4_abe_hwmod, |
| 5933 | .slave = &omap44xx_timer6_hwmod, | 4602 | .slave = &omap44xx_timer6_hwmod, |
| 5934 | .clk = "ocp_abe_iclk", | 4603 | .clk = "ocp_abe_iclk", |
| 5935 | .addr = omap44xx_timer6_addrs, | ||
| 5936 | .user = OCP_USER_MPU, | 4604 | .user = OCP_USER_MPU, |
| 5937 | }; | 4605 | }; |
| 5938 | 4606 | ||
| 5939 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | ||
| 5940 | { | ||
| 5941 | .pa_start = 0x4903a000, | ||
| 5942 | .pa_end = 0x4903a07f, | ||
| 5943 | .flags = ADDR_TYPE_RT | ||
| 5944 | }, | ||
| 5945 | { } | ||
| 5946 | }; | ||
| 5947 | |||
| 5948 | /* l4_abe -> timer6 (dma) */ | 4607 | /* l4_abe -> timer6 (dma) */ |
| 5949 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | 4608 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { |
| 5950 | .master = &omap44xx_l4_abe_hwmod, | 4609 | .master = &omap44xx_l4_abe_hwmod, |
| 5951 | .slave = &omap44xx_timer6_hwmod, | 4610 | .slave = &omap44xx_timer6_hwmod, |
| 5952 | .clk = "ocp_abe_iclk", | 4611 | .clk = "ocp_abe_iclk", |
| 5953 | .addr = omap44xx_timer6_dma_addrs, | ||
| 5954 | .user = OCP_USER_SDMA, | 4612 | .user = OCP_USER_SDMA, |
| 5955 | }; | 4613 | }; |
| 5956 | 4614 | ||
| 5957 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | ||
| 5958 | { | ||
| 5959 | .pa_start = 0x4013c000, | ||
| 5960 | .pa_end = 0x4013c07f, | ||
| 5961 | .flags = ADDR_TYPE_RT | ||
| 5962 | }, | ||
| 5963 | { } | ||
| 5964 | }; | ||
| 5965 | |||
| 5966 | /* l4_abe -> timer7 */ | 4615 | /* l4_abe -> timer7 */ |
| 5967 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | 4616 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { |
| 5968 | .master = &omap44xx_l4_abe_hwmod, | 4617 | .master = &omap44xx_l4_abe_hwmod, |
| 5969 | .slave = &omap44xx_timer7_hwmod, | 4618 | .slave = &omap44xx_timer7_hwmod, |
| 5970 | .clk = "ocp_abe_iclk", | 4619 | .clk = "ocp_abe_iclk", |
| 5971 | .addr = omap44xx_timer7_addrs, | ||
| 5972 | .user = OCP_USER_MPU, | 4620 | .user = OCP_USER_MPU, |
| 5973 | }; | 4621 | }; |
| 5974 | 4622 | ||
| 5975 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | ||
| 5976 | { | ||
| 5977 | .pa_start = 0x4903c000, | ||
| 5978 | .pa_end = 0x4903c07f, | ||
| 5979 | .flags = ADDR_TYPE_RT | ||
| 5980 | }, | ||
| 5981 | { } | ||
| 5982 | }; | ||
| 5983 | |||
| 5984 | /* l4_abe -> timer7 (dma) */ | 4623 | /* l4_abe -> timer7 (dma) */ |
| 5985 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | 4624 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { |
| 5986 | .master = &omap44xx_l4_abe_hwmod, | 4625 | .master = &omap44xx_l4_abe_hwmod, |
| 5987 | .slave = &omap44xx_timer7_hwmod, | 4626 | .slave = &omap44xx_timer7_hwmod, |
| 5988 | .clk = "ocp_abe_iclk", | 4627 | .clk = "ocp_abe_iclk", |
| 5989 | .addr = omap44xx_timer7_dma_addrs, | ||
| 5990 | .user = OCP_USER_SDMA, | 4628 | .user = OCP_USER_SDMA, |
| 5991 | }; | 4629 | }; |
| 5992 | 4630 | ||
| 5993 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | ||
| 5994 | { | ||
| 5995 | .pa_start = 0x4013e000, | ||
| 5996 | .pa_end = 0x4013e07f, | ||
| 5997 | .flags = ADDR_TYPE_RT | ||
| 5998 | }, | ||
| 5999 | { } | ||
| 6000 | }; | ||
| 6001 | |||
| 6002 | /* l4_abe -> timer8 */ | 4631 | /* l4_abe -> timer8 */ |
| 6003 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | 4632 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { |
| 6004 | .master = &omap44xx_l4_abe_hwmod, | 4633 | .master = &omap44xx_l4_abe_hwmod, |
| 6005 | .slave = &omap44xx_timer8_hwmod, | 4634 | .slave = &omap44xx_timer8_hwmod, |
| 6006 | .clk = "ocp_abe_iclk", | 4635 | .clk = "ocp_abe_iclk", |
| 6007 | .addr = omap44xx_timer8_addrs, | ||
| 6008 | .user = OCP_USER_MPU, | 4636 | .user = OCP_USER_MPU, |
| 6009 | }; | 4637 | }; |
| 6010 | 4638 | ||
| 6011 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | ||
| 6012 | { | ||
| 6013 | .pa_start = 0x4903e000, | ||
| 6014 | .pa_end = 0x4903e07f, | ||
| 6015 | .flags = ADDR_TYPE_RT | ||
| 6016 | }, | ||
| 6017 | { } | ||
| 6018 | }; | ||
| 6019 | |||
| 6020 | /* l4_abe -> timer8 (dma) */ | 4639 | /* l4_abe -> timer8 (dma) */ |
| 6021 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | 4640 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { |
| 6022 | .master = &omap44xx_l4_abe_hwmod, | 4641 | .master = &omap44xx_l4_abe_hwmod, |
| 6023 | .slave = &omap44xx_timer8_hwmod, | 4642 | .slave = &omap44xx_timer8_hwmod, |
| 6024 | .clk = "ocp_abe_iclk", | 4643 | .clk = "ocp_abe_iclk", |
| 6025 | .addr = omap44xx_timer8_dma_addrs, | ||
| 6026 | .user = OCP_USER_SDMA, | 4644 | .user = OCP_USER_SDMA, |
| 6027 | }; | 4645 | }; |
| 6028 | 4646 | ||
| 6029 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | ||
| 6030 | { | ||
| 6031 | .pa_start = 0x4803e000, | ||
| 6032 | .pa_end = 0x4803e07f, | ||
| 6033 | .flags = ADDR_TYPE_RT | ||
| 6034 | }, | ||
| 6035 | { } | ||
| 6036 | }; | ||
| 6037 | |||
| 6038 | /* l4_per -> timer9 */ | 4647 | /* l4_per -> timer9 */ |
| 6039 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | 4648 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { |
| 6040 | .master = &omap44xx_l4_per_hwmod, | 4649 | .master = &omap44xx_l4_per_hwmod, |
| 6041 | .slave = &omap44xx_timer9_hwmod, | 4650 | .slave = &omap44xx_timer9_hwmod, |
| 6042 | .clk = "l4_div_ck", | 4651 | .clk = "l4_div_ck", |
| 6043 | .addr = omap44xx_timer9_addrs, | ||
| 6044 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4652 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6045 | }; | 4653 | }; |
| 6046 | 4654 | ||
| 6047 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | ||
| 6048 | { | ||
| 6049 | .pa_start = 0x48086000, | ||
| 6050 | .pa_end = 0x4808607f, | ||
| 6051 | .flags = ADDR_TYPE_RT | ||
| 6052 | }, | ||
| 6053 | { } | ||
| 6054 | }; | ||
| 6055 | |||
| 6056 | /* l4_per -> timer10 */ | 4655 | /* l4_per -> timer10 */ |
| 6057 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | 4656 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { |
| 6058 | .master = &omap44xx_l4_per_hwmod, | 4657 | .master = &omap44xx_l4_per_hwmod, |
| 6059 | .slave = &omap44xx_timer10_hwmod, | 4658 | .slave = &omap44xx_timer10_hwmod, |
| 6060 | .clk = "l4_div_ck", | 4659 | .clk = "l4_div_ck", |
| 6061 | .addr = omap44xx_timer10_addrs, | ||
| 6062 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4660 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6063 | }; | 4661 | }; |
| 6064 | 4662 | ||
| 6065 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | ||
| 6066 | { | ||
| 6067 | .pa_start = 0x48088000, | ||
| 6068 | .pa_end = 0x4808807f, | ||
| 6069 | .flags = ADDR_TYPE_RT | ||
| 6070 | }, | ||
| 6071 | { } | ||
| 6072 | }; | ||
| 6073 | |||
| 6074 | /* l4_per -> timer11 */ | 4663 | /* l4_per -> timer11 */ |
| 6075 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | 4664 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { |
| 6076 | .master = &omap44xx_l4_per_hwmod, | 4665 | .master = &omap44xx_l4_per_hwmod, |
| 6077 | .slave = &omap44xx_timer11_hwmod, | 4666 | .slave = &omap44xx_timer11_hwmod, |
| 6078 | .clk = "l4_div_ck", | 4667 | .clk = "l4_div_ck", |
| 6079 | .addr = omap44xx_timer11_addrs, | ||
| 6080 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4668 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6081 | }; | 4669 | }; |
| 6082 | 4670 | ||
| 6083 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { | ||
| 6084 | { | ||
| 6085 | .pa_start = 0x4806a000, | ||
| 6086 | .pa_end = 0x4806a0ff, | ||
| 6087 | .flags = ADDR_TYPE_RT | ||
| 6088 | }, | ||
| 6089 | { } | ||
| 6090 | }; | ||
| 6091 | |||
| 6092 | /* l4_per -> uart1 */ | 4671 | /* l4_per -> uart1 */ |
| 6093 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | 4672 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { |
| 6094 | .master = &omap44xx_l4_per_hwmod, | 4673 | .master = &omap44xx_l4_per_hwmod, |
| 6095 | .slave = &omap44xx_uart1_hwmod, | 4674 | .slave = &omap44xx_uart1_hwmod, |
| 6096 | .clk = "l4_div_ck", | 4675 | .clk = "l4_div_ck", |
| 6097 | .addr = omap44xx_uart1_addrs, | ||
| 6098 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4676 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6099 | }; | 4677 | }; |
| 6100 | 4678 | ||
| 6101 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | ||
| 6102 | { | ||
| 6103 | .pa_start = 0x4806c000, | ||
| 6104 | .pa_end = 0x4806c0ff, | ||
| 6105 | .flags = ADDR_TYPE_RT | ||
| 6106 | }, | ||
| 6107 | { } | ||
| 6108 | }; | ||
| 6109 | |||
| 6110 | /* l4_per -> uart2 */ | 4679 | /* l4_per -> uart2 */ |
| 6111 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | 4680 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { |
| 6112 | .master = &omap44xx_l4_per_hwmod, | 4681 | .master = &omap44xx_l4_per_hwmod, |
| 6113 | .slave = &omap44xx_uart2_hwmod, | 4682 | .slave = &omap44xx_uart2_hwmod, |
| 6114 | .clk = "l4_div_ck", | 4683 | .clk = "l4_div_ck", |
| 6115 | .addr = omap44xx_uart2_addrs, | ||
| 6116 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4684 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6117 | }; | 4685 | }; |
| 6118 | 4686 | ||
| 6119 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | ||
| 6120 | { | ||
| 6121 | .pa_start = 0x48020000, | ||
| 6122 | .pa_end = 0x480200ff, | ||
| 6123 | .flags = ADDR_TYPE_RT | ||
| 6124 | }, | ||
| 6125 | { } | ||
| 6126 | }; | ||
| 6127 | |||
| 6128 | /* l4_per -> uart3 */ | 4687 | /* l4_per -> uart3 */ |
| 6129 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | 4688 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { |
| 6130 | .master = &omap44xx_l4_per_hwmod, | 4689 | .master = &omap44xx_l4_per_hwmod, |
| 6131 | .slave = &omap44xx_uart3_hwmod, | 4690 | .slave = &omap44xx_uart3_hwmod, |
| 6132 | .clk = "l4_div_ck", | 4691 | .clk = "l4_div_ck", |
| 6133 | .addr = omap44xx_uart3_addrs, | ||
| 6134 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4692 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6135 | }; | 4693 | }; |
| 6136 | 4694 | ||
| 6137 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | ||
| 6138 | { | ||
| 6139 | .pa_start = 0x4806e000, | ||
| 6140 | .pa_end = 0x4806e0ff, | ||
| 6141 | .flags = ADDR_TYPE_RT | ||
| 6142 | }, | ||
| 6143 | { } | ||
| 6144 | }; | ||
| 6145 | |||
| 6146 | /* l4_per -> uart4 */ | 4695 | /* l4_per -> uart4 */ |
| 6147 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | 4696 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { |
| 6148 | .master = &omap44xx_l4_per_hwmod, | 4697 | .master = &omap44xx_l4_per_hwmod, |
| 6149 | .slave = &omap44xx_uart4_hwmod, | 4698 | .slave = &omap44xx_uart4_hwmod, |
| 6150 | .clk = "l4_div_ck", | 4699 | .clk = "l4_div_ck", |
| 6151 | .addr = omap44xx_uart4_addrs, | ||
| 6152 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4700 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6153 | }; | 4701 | }; |
| 6154 | 4702 | ||
| 6155 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { | ||
| 6156 | { | ||
| 6157 | .pa_start = 0x4a0a9000, | ||
| 6158 | .pa_end = 0x4a0a93ff, | ||
| 6159 | .flags = ADDR_TYPE_RT | ||
| 6160 | }, | ||
| 6161 | { } | ||
| 6162 | }; | ||
| 6163 | |||
| 6164 | /* l4_cfg -> usb_host_fs */ | 4703 | /* l4_cfg -> usb_host_fs */ |
| 6165 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { | 4704 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
| 6166 | .master = &omap44xx_l4_cfg_hwmod, | 4705 | .master = &omap44xx_l4_cfg_hwmod, |
| 6167 | .slave = &omap44xx_usb_host_fs_hwmod, | 4706 | .slave = &omap44xx_usb_host_fs_hwmod, |
| 6168 | .clk = "l4_div_ck", | 4707 | .clk = "l4_div_ck", |
| 6169 | .addr = omap44xx_usb_host_fs_addrs, | ||
| 6170 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4708 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6171 | }; | 4709 | }; |
| 6172 | 4710 | ||
| 6173 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { | ||
| 6174 | { | ||
| 6175 | .name = "uhh", | ||
| 6176 | .pa_start = 0x4a064000, | ||
| 6177 | .pa_end = 0x4a0647ff, | ||
| 6178 | .flags = ADDR_TYPE_RT | ||
| 6179 | }, | ||
| 6180 | { | ||
| 6181 | .name = "ohci", | ||
| 6182 | .pa_start = 0x4a064800, | ||
| 6183 | .pa_end = 0x4a064bff, | ||
| 6184 | }, | ||
| 6185 | { | ||
| 6186 | .name = "ehci", | ||
| 6187 | .pa_start = 0x4a064c00, | ||
| 6188 | .pa_end = 0x4a064fff, | ||
| 6189 | }, | ||
| 6190 | {} | ||
| 6191 | }; | ||
| 6192 | |||
| 6193 | /* l4_cfg -> usb_host_hs */ | 4711 | /* l4_cfg -> usb_host_hs */ |
| 6194 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | 4712 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { |
| 6195 | .master = &omap44xx_l4_cfg_hwmod, | 4713 | .master = &omap44xx_l4_cfg_hwmod, |
| 6196 | .slave = &omap44xx_usb_host_hs_hwmod, | 4714 | .slave = &omap44xx_usb_host_hs_hwmod, |
| 6197 | .clk = "l4_div_ck", | 4715 | .clk = "l4_div_ck", |
| 6198 | .addr = omap44xx_usb_host_hs_addrs, | ||
| 6199 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4716 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6200 | }; | 4717 | }; |
| 6201 | 4718 | ||
| 6202 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | ||
| 6203 | { | ||
| 6204 | .pa_start = 0x4a0ab000, | ||
| 6205 | .pa_end = 0x4a0ab7ff, | ||
| 6206 | .flags = ADDR_TYPE_RT | ||
| 6207 | }, | ||
| 6208 | { } | ||
| 6209 | }; | ||
| 6210 | |||
| 6211 | /* l4_cfg -> usb_otg_hs */ | 4719 | /* l4_cfg -> usb_otg_hs */ |
| 6212 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | 4720 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { |
| 6213 | .master = &omap44xx_l4_cfg_hwmod, | 4721 | .master = &omap44xx_l4_cfg_hwmod, |
| 6214 | .slave = &omap44xx_usb_otg_hs_hwmod, | 4722 | .slave = &omap44xx_usb_otg_hs_hwmod, |
| 6215 | .clk = "l4_div_ck", | 4723 | .clk = "l4_div_ck", |
| 6216 | .addr = omap44xx_usb_otg_hs_addrs, | ||
| 6217 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4724 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6218 | }; | 4725 | }; |
| 6219 | 4726 | ||
| 6220 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | ||
| 6221 | { | ||
| 6222 | .name = "tll", | ||
| 6223 | .pa_start = 0x4a062000, | ||
| 6224 | .pa_end = 0x4a063fff, | ||
| 6225 | .flags = ADDR_TYPE_RT | ||
| 6226 | }, | ||
| 6227 | {} | ||
| 6228 | }; | ||
| 6229 | |||
| 6230 | /* l4_cfg -> usb_tll_hs */ | 4727 | /* l4_cfg -> usb_tll_hs */ |
| 6231 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { | 4728 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
| 6232 | .master = &omap44xx_l4_cfg_hwmod, | 4729 | .master = &omap44xx_l4_cfg_hwmod, |
| 6233 | .slave = &omap44xx_usb_tll_hs_hwmod, | 4730 | .slave = &omap44xx_usb_tll_hs_hwmod, |
| 6234 | .clk = "l4_div_ck", | 4731 | .clk = "l4_div_ck", |
| 6235 | .addr = omap44xx_usb_tll_hs_addrs, | ||
| 6236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4732 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6237 | }; | 4733 | }; |
| 6238 | 4734 | ||
| 6239 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | ||
| 6240 | { | ||
| 6241 | .pa_start = 0x4a314000, | ||
| 6242 | .pa_end = 0x4a31407f, | ||
| 6243 | .flags = ADDR_TYPE_RT | ||
| 6244 | }, | ||
| 6245 | { } | ||
| 6246 | }; | ||
| 6247 | |||
| 6248 | /* l4_wkup -> wd_timer2 */ | 4735 | /* l4_wkup -> wd_timer2 */ |
| 6249 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | 4736 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { |
| 6250 | .master = &omap44xx_l4_wkup_hwmod, | 4737 | .master = &omap44xx_l4_wkup_hwmod, |
| 6251 | .slave = &omap44xx_wd_timer2_hwmod, | 4738 | .slave = &omap44xx_wd_timer2_hwmod, |
| 6252 | .clk = "l4_wkup_clk_mux_ck", | 4739 | .clk = "l4_wkup_clk_mux_ck", |
| 6253 | .addr = omap44xx_wd_timer2_addrs, | ||
| 6254 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 4740 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 6255 | }; | 4741 | }; |
| 6256 | 4742 | ||
| @@ -6290,14 +4776,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |||
| 6290 | .user = OCP_USER_SDMA, | 4776 | .user = OCP_USER_SDMA, |
| 6291 | }; | 4777 | }; |
| 6292 | 4778 | ||
| 4779 | /* mpu -> emif1 */ | ||
| 4780 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { | ||
| 4781 | .master = &omap44xx_mpu_hwmod, | ||
| 4782 | .slave = &omap44xx_emif1_hwmod, | ||
| 4783 | .clk = "l3_div_ck", | ||
| 4784 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 4785 | }; | ||
| 4786 | |||
| 4787 | /* mpu -> emif2 */ | ||
| 4788 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { | ||
| 4789 | .master = &omap44xx_mpu_hwmod, | ||
| 4790 | .slave = &omap44xx_emif2_hwmod, | ||
| 4791 | .clk = "l3_div_ck", | ||
| 4792 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 4793 | }; | ||
| 4794 | |||
| 6293 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | 4795 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
| 6294 | &omap44xx_c2c__c2c_target_fw, | ||
| 6295 | &omap44xx_l4_cfg__c2c_target_fw, | ||
| 6296 | &omap44xx_l3_main_1__dmm, | 4796 | &omap44xx_l3_main_1__dmm, |
| 6297 | &omap44xx_mpu__dmm, | 4797 | &omap44xx_mpu__dmm, |
| 6298 | &omap44xx_c2c__emif_fw, | ||
| 6299 | &omap44xx_dmm__emif_fw, | ||
| 6300 | &omap44xx_l4_cfg__emif_fw, | ||
| 6301 | &omap44xx_iva__l3_instr, | 4798 | &omap44xx_iva__l3_instr, |
| 6302 | &omap44xx_l3_main_3__l3_instr, | 4799 | &omap44xx_l3_main_3__l3_instr, |
| 6303 | &omap44xx_ocp_wp_noc__l3_instr, | 4800 | &omap44xx_ocp_wp_noc__l3_instr, |
| @@ -6308,7 +4805,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6308 | &omap44xx_mmc1__l3_main_1, | 4805 | &omap44xx_mmc1__l3_main_1, |
| 6309 | &omap44xx_mmc2__l3_main_1, | 4806 | &omap44xx_mmc2__l3_main_1, |
| 6310 | &omap44xx_mpu__l3_main_1, | 4807 | &omap44xx_mpu__l3_main_1, |
| 6311 | &omap44xx_c2c_target_fw__l3_main_2, | ||
| 6312 | &omap44xx_debugss__l3_main_2, | 4808 | &omap44xx_debugss__l3_main_2, |
| 6313 | &omap44xx_dma_system__l3_main_2, | 4809 | &omap44xx_dma_system__l3_main_2, |
| 6314 | &omap44xx_fdif__l3_main_2, | 4810 | &omap44xx_fdif__l3_main_2, |
| @@ -6364,8 +4860,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6364 | &omap44xx_l3_main_2__dss_venc, | 4860 | &omap44xx_l3_main_2__dss_venc, |
| 6365 | &omap44xx_l4_per__dss_venc, | 4861 | &omap44xx_l4_per__dss_venc, |
| 6366 | &omap44xx_l4_per__elm, | 4862 | &omap44xx_l4_per__elm, |
| 6367 | &omap44xx_emif_fw__emif1, | ||
| 6368 | &omap44xx_emif_fw__emif2, | ||
| 6369 | &omap44xx_l4_cfg__fdif, | 4863 | &omap44xx_l4_cfg__fdif, |
| 6370 | &omap44xx_l4_wkup__gpio1, | 4864 | &omap44xx_l4_wkup__gpio1, |
| 6371 | &omap44xx_l4_per__gpio2, | 4865 | &omap44xx_l4_per__gpio2, |
| @@ -6450,6 +4944,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6450 | &omap44xx_l4_wkup__wd_timer2, | 4944 | &omap44xx_l4_wkup__wd_timer2, |
| 6451 | &omap44xx_l4_abe__wd_timer3, | 4945 | &omap44xx_l4_abe__wd_timer3, |
| 6452 | &omap44xx_l4_abe__wd_timer3_dma, | 4946 | &omap44xx_l4_abe__wd_timer3_dma, |
| 4947 | &omap44xx_mpu__emif1, | ||
| 4948 | &omap44xx_mpu__emif2, | ||
| 6453 | NULL, | 4949 | NULL, |
| 6454 | }; | 4950 | }; |
| 6455 | 4951 | ||
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index f6601563aa69..58d5b5667315 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
| @@ -63,7 +63,6 @@ struct omap_uart_state { | |||
| 63 | static LIST_HEAD(uart_list); | 63 | static LIST_HEAD(uart_list); |
| 64 | static u8 num_uarts; | 64 | static u8 num_uarts; |
| 65 | static u8 console_uart_id = -1; | 65 | static u8 console_uart_id = -1; |
| 66 | static u8 no_console_suspend; | ||
| 67 | static u8 uart_debug; | 66 | static u8 uart_debug; |
| 68 | 67 | ||
| 69 | #define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */ | 68 | #define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */ |
| @@ -207,9 +206,6 @@ static int __init omap_serial_early_init(void) | |||
| 207 | uart_name, uart->num); | 206 | uart_name, uart->num); |
| 208 | } | 207 | } |
| 209 | 208 | ||
| 210 | if (cmdline_find_option("no_console_suspend")) | ||
| 211 | no_console_suspend = true; | ||
| 212 | |||
| 213 | /* | 209 | /* |
| 214 | * omap-uart can be used for earlyprintk logs | 210 | * omap-uart can be used for earlyprintk logs |
| 215 | * So if omap-uart is used as console then prevent | 211 | * So if omap-uart is used as console then prevent |
| @@ -292,9 +288,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, | |||
| 292 | return; | 288 | return; |
| 293 | } | 289 | } |
| 294 | 290 | ||
| 295 | if ((console_uart_id == bdata->id) && no_console_suspend) | ||
| 296 | omap_device_disable_idle_on_suspend(pdev); | ||
| 297 | |||
| 298 | oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); | 291 | oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); |
| 299 | 292 | ||
| 300 | if (console_uart_id == bdata->id) { | 293 | if (console_uart_id == bdata->id) { |
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index aa27d7f5cbb7..544c92bf60cc 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c | |||
| @@ -188,125 +188,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) | |||
| 188 | return; | 188 | return; |
| 189 | } | 189 | } |
| 190 | 190 | ||
| 191 | static | ||
| 192 | void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) | ||
| 193 | { | ||
| 194 | switch (port_mode[0]) { | ||
| 195 | case OMAP_EHCI_PORT_MODE_PHY: | ||
| 196 | omap_mux_init_signal("usbb1_ulpiphy_stp", | ||
| 197 | OMAP_PIN_OUTPUT); | ||
| 198 | omap_mux_init_signal("usbb1_ulpiphy_clk", | ||
| 199 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 200 | omap_mux_init_signal("usbb1_ulpiphy_dir", | ||
| 201 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 202 | omap_mux_init_signal("usbb1_ulpiphy_nxt", | ||
| 203 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 204 | omap_mux_init_signal("usbb1_ulpiphy_dat0", | ||
| 205 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 206 | omap_mux_init_signal("usbb1_ulpiphy_dat1", | ||
| 207 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 208 | omap_mux_init_signal("usbb1_ulpiphy_dat2", | ||
| 209 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 210 | omap_mux_init_signal("usbb1_ulpiphy_dat3", | ||
| 211 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 212 | omap_mux_init_signal("usbb1_ulpiphy_dat4", | ||
| 213 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 214 | omap_mux_init_signal("usbb1_ulpiphy_dat5", | ||
| 215 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 216 | omap_mux_init_signal("usbb1_ulpiphy_dat6", | ||
| 217 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 218 | omap_mux_init_signal("usbb1_ulpiphy_dat7", | ||
| 219 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 220 | break; | ||
| 221 | case OMAP_EHCI_PORT_MODE_TLL: | ||
| 222 | omap_mux_init_signal("usbb1_ulpitll_stp", | ||
| 223 | OMAP_PIN_INPUT_PULLUP); | ||
| 224 | omap_mux_init_signal("usbb1_ulpitll_clk", | ||
| 225 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 226 | omap_mux_init_signal("usbb1_ulpitll_dir", | ||
| 227 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 228 | omap_mux_init_signal("usbb1_ulpitll_nxt", | ||
| 229 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 230 | omap_mux_init_signal("usbb1_ulpitll_dat0", | ||
| 231 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 232 | omap_mux_init_signal("usbb1_ulpitll_dat1", | ||
| 233 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 234 | omap_mux_init_signal("usbb1_ulpitll_dat2", | ||
| 235 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 236 | omap_mux_init_signal("usbb1_ulpitll_dat3", | ||
| 237 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 238 | omap_mux_init_signal("usbb1_ulpitll_dat4", | ||
| 239 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 240 | omap_mux_init_signal("usbb1_ulpitll_dat5", | ||
| 241 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 242 | omap_mux_init_signal("usbb1_ulpitll_dat6", | ||
| 243 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 244 | omap_mux_init_signal("usbb1_ulpitll_dat7", | ||
| 245 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 246 | break; | ||
| 247 | case OMAP_USBHS_PORT_MODE_UNUSED: | ||
| 248 | default: | ||
| 249 | break; | ||
| 250 | } | ||
| 251 | switch (port_mode[1]) { | ||
| 252 | case OMAP_EHCI_PORT_MODE_PHY: | ||
| 253 | omap_mux_init_signal("usbb2_ulpiphy_stp", | ||
| 254 | OMAP_PIN_OUTPUT); | ||
| 255 | omap_mux_init_signal("usbb2_ulpiphy_clk", | ||
| 256 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 257 | omap_mux_init_signal("usbb2_ulpiphy_dir", | ||
| 258 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 259 | omap_mux_init_signal("usbb2_ulpiphy_nxt", | ||
| 260 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 261 | omap_mux_init_signal("usbb2_ulpiphy_dat0", | ||
| 262 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 263 | omap_mux_init_signal("usbb2_ulpiphy_dat1", | ||
| 264 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 265 | omap_mux_init_signal("usbb2_ulpiphy_dat2", | ||
| 266 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 267 | omap_mux_init_signal("usbb2_ulpiphy_dat3", | ||
| 268 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 269 | omap_mux_init_signal("usbb2_ulpiphy_dat4", | ||
| 270 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 271 | omap_mux_init_signal("usbb2_ulpiphy_dat5", | ||
| 272 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 273 | omap_mux_init_signal("usbb2_ulpiphy_dat6", | ||
| 274 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 275 | omap_mux_init_signal("usbb2_ulpiphy_dat7", | ||
| 276 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 277 | break; | ||
| 278 | case OMAP_EHCI_PORT_MODE_TLL: | ||
| 279 | omap_mux_init_signal("usbb2_ulpitll_stp", | ||
| 280 | OMAP_PIN_INPUT_PULLUP); | ||
| 281 | omap_mux_init_signal("usbb2_ulpitll_clk", | ||
| 282 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 283 | omap_mux_init_signal("usbb2_ulpitll_dir", | ||
| 284 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 285 | omap_mux_init_signal("usbb2_ulpitll_nxt", | ||
| 286 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 287 | omap_mux_init_signal("usbb2_ulpitll_dat0", | ||
| 288 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 289 | omap_mux_init_signal("usbb2_ulpitll_dat1", | ||
| 290 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 291 | omap_mux_init_signal("usbb2_ulpitll_dat2", | ||
| 292 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 293 | omap_mux_init_signal("usbb2_ulpitll_dat3", | ||
| 294 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 295 | omap_mux_init_signal("usbb2_ulpitll_dat4", | ||
| 296 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 297 | omap_mux_init_signal("usbb2_ulpitll_dat5", | ||
| 298 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 299 | omap_mux_init_signal("usbb2_ulpitll_dat6", | ||
| 300 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 301 | omap_mux_init_signal("usbb2_ulpitll_dat7", | ||
| 302 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 303 | break; | ||
| 304 | case OMAP_USBHS_PORT_MODE_UNUSED: | ||
| 305 | default: | ||
| 306 | break; | ||
| 307 | } | ||
| 308 | } | ||
| 309 | |||
| 310 | static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) | 191 | static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) |
| 311 | { | 192 | { |
| 312 | switch (port_mode[0]) { | 193 | switch (port_mode[0]) { |
| @@ -404,78 +285,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) | |||
| 404 | } | 285 | } |
| 405 | } | 286 | } |
| 406 | 287 | ||
| 407 | static | ||
| 408 | void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) | ||
| 409 | { | ||
| 410 | switch (port_mode[0]) { | ||
| 411 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | ||
| 412 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | ||
| 413 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | ||
| 414 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | ||
| 415 | omap_mux_init_signal("usbb1_mm_rxdp", | ||
| 416 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 417 | omap_mux_init_signal("usbb1_mm_rxdm", | ||
| 418 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 419 | |||
| 420 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | ||
| 421 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | ||
| 422 | omap_mux_init_signal("usbb1_mm_rxrcv", | ||
| 423 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 424 | |||
| 425 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | ||
| 426 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | ||
| 427 | omap_mux_init_signal("usbb1_mm_txen", | ||
| 428 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 429 | |||
| 430 | |||
| 431 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | ||
| 432 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | ||
| 433 | omap_mux_init_signal("usbb1_mm_txdat", | ||
| 434 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 435 | omap_mux_init_signal("usbb1_mm_txse0", | ||
| 436 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 437 | break; | ||
| 438 | |||
| 439 | case OMAP_USBHS_PORT_MODE_UNUSED: | ||
| 440 | default: | ||
| 441 | break; | ||
| 442 | } | ||
| 443 | |||
| 444 | switch (port_mode[1]) { | ||
| 445 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | ||
| 446 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | ||
| 447 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | ||
| 448 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | ||
| 449 | omap_mux_init_signal("usbb2_mm_rxdp", | ||
| 450 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 451 | omap_mux_init_signal("usbb2_mm_rxdm", | ||
| 452 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 453 | |||
| 454 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | ||
| 455 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | ||
| 456 | omap_mux_init_signal("usbb2_mm_rxrcv", | ||
| 457 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 458 | |||
| 459 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | ||
| 460 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | ||
| 461 | omap_mux_init_signal("usbb2_mm_txen", | ||
| 462 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 463 | |||
| 464 | |||
| 465 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | ||
| 466 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | ||
| 467 | omap_mux_init_signal("usbb2_mm_txdat", | ||
| 468 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 469 | omap_mux_init_signal("usbb2_mm_txse0", | ||
| 470 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 471 | break; | ||
| 472 | |||
| 473 | case OMAP_USBHS_PORT_MODE_UNUSED: | ||
| 474 | default: | ||
| 475 | break; | ||
| 476 | } | ||
| 477 | } | ||
| 478 | |||
| 479 | void __init usbhs_init(struct usbhs_omap_platform_data *pdata) | 288 | void __init usbhs_init(struct usbhs_omap_platform_data *pdata) |
| 480 | { | 289 | { |
| 481 | struct omap_hwmod *uhh_hwm, *tll_hwm; | 290 | struct omap_hwmod *uhh_hwm, *tll_hwm; |
| @@ -489,9 +298,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata) | |||
| 489 | if (omap_rev() <= OMAP3430_REV_ES2_1) | 298 | if (omap_rev() <= OMAP3430_REV_ES2_1) |
| 490 | pdata->single_ulpi_bypass = true; | 299 | pdata->single_ulpi_bypass = true; |
| 491 | 300 | ||
| 492 | } else if (cpu_is_omap44xx()) { | ||
| 493 | setup_4430ehci_io_mux(pdata->port_mode); | ||
| 494 | setup_4430ohci_io_mux(pdata->port_mode); | ||
| 495 | } | 301 | } |
| 496 | 302 | ||
| 497 | uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); | 303 | uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); |
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 3242a554ad6b..8c4de2708cf2 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) | |||
| 85 | musb_plat.mode = board_data->mode; | 85 | musb_plat.mode = board_data->mode; |
| 86 | musb_plat.extvbus = board_data->extvbus; | 86 | musb_plat.extvbus = board_data->extvbus; |
| 87 | 87 | ||
| 88 | if (cpu_is_omap44xx()) | ||
| 89 | musb_plat.has_mailbox = true; | ||
| 90 | |||
| 91 | if (soc_is_am35xx()) { | 88 | if (soc_is_am35xx()) { |
| 92 | oh_name = "am35x_otg_hs"; | 89 | oh_name = "am35x_otg_hs"; |
| 93 | name = "musb-am35x"; | 90 | name = "musb-am35x"; |
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index 70b441ad1d18..b069fa6bb0e2 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c | |||
| @@ -8,20 +8,14 @@ | |||
| 8 | * All enquiries to support@picochip.com | 8 | * All enquiries to support@picochip.com |
| 9 | */ | 9 | */ |
| 10 | #include <linux/delay.h> | 10 | #include <linux/delay.h> |
| 11 | #include <linux/irq.h> | ||
| 12 | #include <linux/irqchip.h> | ||
| 13 | #include <linux/irqdomain.h> | ||
| 14 | #include <linux/of.h> | 11 | #include <linux/of.h> |
| 15 | #include <linux/of_address.h> | 12 | #include <linux/of_address.h> |
| 16 | #include <linux/of_irq.h> | ||
| 17 | #include <linux/of_platform.h> | 13 | #include <linux/of_platform.h> |
| 18 | #include <linux/dw_apb_timer.h> | 14 | #include <linux/dw_apb_timer.h> |
| 19 | 15 | ||
| 20 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 22 | 18 | ||
| 23 | #include "common.h" | ||
| 24 | |||
| 25 | #define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000) | 19 | #define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000) |
| 26 | #define PICOXCELL_PERIPH_BASE 0x80000000 | 20 | #define PICOXCELL_PERIPH_BASE 0x80000000 |
| 27 | #define PICOXCELL_PERIPH_LENGTH SZ_4M | 21 | #define PICOXCELL_PERIPH_LENGTH SZ_4M |
| @@ -87,7 +81,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd) | |||
| 87 | DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") | 81 | DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") |
| 88 | .map_io = picoxcell_map_io, | 82 | .map_io = picoxcell_map_io, |
| 89 | .nr_irqs = NR_IRQS_LEGACY, | 83 | .nr_irqs = NR_IRQS_LEGACY, |
| 90 | .init_irq = irqchip_init, | ||
| 91 | .init_time = dw_apb_timer_init, | 84 | .init_time = dw_apb_timer_init, |
| 92 | .init_machine = picoxcell_init_machine, | 85 | .init_machine = picoxcell_init_machine, |
| 93 | .dt_compat = picoxcell_dt_match, | 86 | .dt_compat = picoxcell_dt_match, |
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h deleted file mode 100644 index 481b42a4ef15..000000000000 --- a/arch/arm/mach-picoxcell/common.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2011 Picochip Ltd., Jamie Iles | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * All enquiries to support@picochip.com | ||
| 9 | */ | ||
| 10 | #ifndef __PICOXCELL_COMMON_H__ | ||
| 11 | #define __PICOXCELL_COMMON_H__ | ||
| 12 | |||
| 13 | #include <asm/mach/time.h> | ||
| 14 | |||
| 15 | extern void dw_apb_timer_init(void); | ||
| 16 | |||
| 17 | #endif /* __PICOXCELL_COMMON_H__ */ | ||
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 4f94cd87972a..a9f475cdf603 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c | |||
| @@ -9,7 +9,6 @@ | |||
| 9 | #include <linux/clocksource.h> | 9 | #include <linux/clocksource.h> |
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/irqchip.h> | ||
| 13 | #include <asm/sizes.h> | 12 | #include <asm/sizes.h> |
| 14 | #include <asm/mach-types.h> | 13 | #include <asm/mach-types.h> |
| 15 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
| @@ -55,7 +54,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") | |||
| 55 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | 54 | /* Maintainer: Barry Song <baohua.song@csr.com> */ |
| 56 | .nr_irqs = 128, | 55 | .nr_irqs = 128, |
| 57 | .map_io = sirfsoc_map_io, | 56 | .map_io = sirfsoc_map_io, |
| 58 | .init_irq = irqchip_init, | ||
| 59 | .init_time = sirfsoc_init_time, | 57 | .init_time = sirfsoc_init_time, |
| 60 | .init_machine = sirfsoc_mach_init, | 58 | .init_machine = sirfsoc_mach_init, |
| 61 | .init_late = sirfsoc_init_late, | 59 | .init_late = sirfsoc_init_late, |
| @@ -74,7 +72,6 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") | |||
| 74 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | 72 | /* Maintainer: Barry Song <baohua.song@csr.com> */ |
| 75 | .nr_irqs = 128, | 73 | .nr_irqs = 128, |
| 76 | .map_io = sirfsoc_map_io, | 74 | .map_io = sirfsoc_map_io, |
| 77 | .init_irq = irqchip_init, | ||
| 78 | .init_time = sirfsoc_init_time, | 75 | .init_time = sirfsoc_init_time, |
| 79 | .dma_zone_size = SZ_256M, | 76 | .dma_zone_size = SZ_256M, |
| 80 | .init_machine = sirfsoc_mach_init, | 77 | .init_machine = sirfsoc_mach_init, |
| @@ -94,7 +91,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") | |||
| 94 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | 91 | /* Maintainer: Barry Song <baohua.song@csr.com> */ |
| 95 | .smp = smp_ops(sirfsoc_smp_ops), | 92 | .smp = smp_ops(sirfsoc_smp_ops), |
| 96 | .map_io = sirfsoc_map_io, | 93 | .map_io = sirfsoc_map_io, |
| 97 | .init_irq = irqchip_init, | ||
| 98 | .init_time = sirfsoc_init_time, | 94 | .init_time = sirfsoc_init_time, |
| 99 | .init_machine = sirfsoc_mach_init, | 95 | .init_machine = sirfsoc_mach_init, |
| 100 | .init_late = sirfsoc_init_late, | 96 | .init_late = sirfsoc_init_late, |
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c index 9eaac2c881ea..7ad003001ab7 100644 --- a/arch/arm/mach-spear/spear1310.c +++ b/arch/arm/mach-spear/spear1310.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #define pr_fmt(fmt) "SPEAr1310: " fmt | 14 | #define pr_fmt(fmt) "SPEAr1310: " fmt |
| 15 | 15 | ||
| 16 | #include <linux/amba/pl022.h> | 16 | #include <linux/amba/pl022.h> |
| 17 | #include <linux/irqchip.h> | ||
| 18 | #include <linux/of_platform.h> | 17 | #include <linux/of_platform.h> |
| 19 | #include <linux/pata_arasan_cf_data.h> | 18 | #include <linux/pata_arasan_cf_data.h> |
| 20 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| @@ -60,7 +59,6 @@ static void __init spear1310_map_io(void) | |||
| 60 | DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") | 59 | DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") |
| 61 | .smp = smp_ops(spear13xx_smp_ops), | 60 | .smp = smp_ops(spear13xx_smp_ops), |
| 62 | .map_io = spear1310_map_io, | 61 | .map_io = spear1310_map_io, |
| 63 | .init_irq = irqchip_init, | ||
| 64 | .init_time = spear13xx_timer_init, | 62 | .init_time = spear13xx_timer_init, |
| 65 | .init_machine = spear1310_dt_init, | 63 | .init_machine = spear1310_dt_init, |
| 66 | .restart = spear_restart, | 64 | .restart = spear_restart, |
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c index a04a7fe76f71..3fb683424729 100644 --- a/arch/arm/mach-spear/spear1340.c +++ b/arch/arm/mach-spear/spear1340.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/amba/serial.h> | 17 | #include <linux/amba/serial.h> |
| 18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
| 19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/irqchip.h> | ||
| 21 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 22 | #include "generic.h" | 21 | #include "generic.h" |
| 23 | #include <mach/spear.h> | 22 | #include <mach/spear.h> |
| @@ -155,7 +154,6 @@ static const char * const spear1340_dt_board_compat[] = { | |||
| 155 | DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") | 154 | DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") |
| 156 | .smp = smp_ops(spear13xx_smp_ops), | 155 | .smp = smp_ops(spear13xx_smp_ops), |
| 157 | .map_io = spear13xx_map_io, | 156 | .map_io = spear13xx_map_io, |
| 158 | .init_irq = irqchip_init, | ||
| 159 | .init_time = spear13xx_timer_init, | 157 | .init_time = spear13xx_timer_init, |
| 160 | .init_machine = spear1340_dt_init, | 158 | .init_machine = spear1340_dt_init, |
| 161 | .restart = spear_restart, | 159 | .restart = spear_restart, |
diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c index bac56e845f7a..b52e48f342f4 100644 --- a/arch/arm/mach-spear/spear300.c +++ b/arch/arm/mach-spear/spear300.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #define pr_fmt(fmt) "SPEAr300: " fmt | 14 | #define pr_fmt(fmt) "SPEAr300: " fmt |
| 15 | 15 | ||
| 16 | #include <linux/amba/pl08x.h> | 16 | #include <linux/amba/pl08x.h> |
| 17 | #include <linux/irqchip.h> | ||
| 18 | #include <linux/of_platform.h> | 17 | #include <linux/of_platform.h> |
| 19 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
| 20 | #include "generic.h" | 19 | #include "generic.h" |
| @@ -212,7 +211,6 @@ static void __init spear300_map_io(void) | |||
| 212 | 211 | ||
| 213 | DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") | 212 | DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") |
| 214 | .map_io = spear300_map_io, | 213 | .map_io = spear300_map_io, |
| 215 | .init_irq = irqchip_init, | ||
| 216 | .init_time = spear3xx_timer_init, | 214 | .init_time = spear3xx_timer_init, |
| 217 | .init_machine = spear300_dt_init, | 215 | .init_machine = spear300_dt_init, |
| 218 | .restart = spear_restart, | 216 | .restart = spear_restart, |
diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c index 6ffbc63d516d..ed2029db391f 100644 --- a/arch/arm/mach-spear/spear310.c +++ b/arch/arm/mach-spear/spear310.c | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | 15 | ||
| 16 | #include <linux/amba/pl08x.h> | 16 | #include <linux/amba/pl08x.h> |
| 17 | #include <linux/amba/serial.h> | 17 | #include <linux/amba/serial.h> |
| 18 | #include <linux/irqchip.h> | ||
| 19 | #include <linux/of_platform.h> | 18 | #include <linux/of_platform.h> |
| 20 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 21 | #include "generic.h" | 20 | #include "generic.h" |
| @@ -254,7 +253,6 @@ static void __init spear310_map_io(void) | |||
| 254 | 253 | ||
| 255 | DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") | 254 | DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") |
| 256 | .map_io = spear310_map_io, | 255 | .map_io = spear310_map_io, |
| 257 | .init_irq = irqchip_init, | ||
| 258 | .init_time = spear3xx_timer_init, | 256 | .init_time = spear3xx_timer_init, |
| 259 | .init_machine = spear310_dt_init, | 257 | .init_machine = spear310_dt_init, |
| 260 | .restart = spear_restart, | 258 | .restart = spear_restart, |
diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c index 6eb3eec65f96..bf634b32a930 100644 --- a/arch/arm/mach-spear/spear320.c +++ b/arch/arm/mach-spear/spear320.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/amba/pl022.h> | 16 | #include <linux/amba/pl022.h> |
| 17 | #include <linux/amba/pl08x.h> | 17 | #include <linux/amba/pl08x.h> |
| 18 | #include <linux/amba/serial.h> | 18 | #include <linux/amba/serial.h> |
| 19 | #include <linux/irqchip.h> | ||
| 20 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 21 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach/map.h> | 21 | #include <asm/mach/map.h> |
| @@ -269,7 +268,6 @@ static void __init spear320_map_io(void) | |||
| 269 | 268 | ||
| 270 | DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") | 269 | DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") |
| 271 | .map_io = spear320_map_io, | 270 | .map_io = spear320_map_io, |
| 272 | .init_irq = irqchip_init, | ||
| 273 | .init_time = spear3xx_timer_init, | 271 | .init_time = spear3xx_timer_init, |
| 274 | .init_machine = spear320_dt_init, | 272 | .init_machine = spear320_dt_init, |
| 275 | .restart = spear_restart, | 273 | .restart = spear_restart, |
diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index ec8eefbbdfad..8b0295a41226 100644 --- a/arch/arm/mach-spear/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/amba/pl08x.h> | 16 | #include <linux/amba/pl08x.h> |
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/err.h> | 18 | #include <linux/err.h> |
| 19 | #include <linux/irqchip.h> | ||
| 20 | #include <linux/of.h> | 19 | #include <linux/of.h> |
| 21 | #include <linux/of_address.h> | 20 | #include <linux/of_address.h> |
| 22 | #include <linux/of_platform.h> | 21 | #include <linux/of_platform.h> |
| @@ -423,7 +422,6 @@ static const char *spear600_dt_board_compat[] = { | |||
| 423 | 422 | ||
| 424 | DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") | 423 | DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") |
| 425 | .map_io = spear6xx_map_io, | 424 | .map_io = spear6xx_map_io, |
| 426 | .init_irq = irqchip_init, | ||
| 427 | .init_time = spear6xx_timer_init, | 425 | .init_time = spear6xx_timer_init, |
| 428 | .init_machine = spear600_dt_init, | 426 | .init_machine = spear600_dt_init, |
| 429 | .restart = spear_restart, | 427 | .restart = spear_restart, |
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 706ce35396b8..a3a755fa2850 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | #include <linux/irqchip.h> | ||
| 18 | #include <linux/of_address.h> | 17 | #include <linux/of_address.h> |
| 19 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
| 20 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| @@ -26,8 +25,6 @@ | |||
| 26 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| 27 | #include <asm/system_misc.h> | 26 | #include <asm/system_misc.h> |
| 28 | 27 | ||
| 29 | #include "sunxi.h" | ||
| 30 | |||
| 31 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 | 28 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 |
| 32 | #define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) | 29 | #define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) |
| 33 | #define SUN4I_WATCHDOG_MODE_REG 0x04 | 30 | #define SUN4I_WATCHDOG_MODE_REG 0x04 |
| @@ -81,20 +78,6 @@ static void sunxi_setup_restart(void) | |||
| 81 | arm_pm_restart = of_id->data; | 78 | arm_pm_restart = of_id->data; |
| 82 | } | 79 | } |
| 83 | 80 | ||
| 84 | static struct map_desc sunxi_io_desc[] __initdata = { | ||
| 85 | { | ||
| 86 | .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE, | ||
| 87 | .pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE), | ||
| 88 | .length = SUNXI_REGS_SIZE, | ||
| 89 | .type = MT_DEVICE, | ||
| 90 | }, | ||
| 91 | }; | ||
| 92 | |||
| 93 | void __init sunxi_map_io(void) | ||
| 94 | { | ||
| 95 | iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc)); | ||
| 96 | } | ||
| 97 | |||
| 98 | static void __init sunxi_timer_init(void) | 81 | static void __init sunxi_timer_init(void) |
| 99 | { | 82 | { |
| 100 | sunxi_init_clocks(); | 83 | sunxi_init_clocks(); |
| @@ -116,8 +99,6 @@ static const char * const sunxi_board_dt_compat[] = { | |||
| 116 | 99 | ||
| 117 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") | 100 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") |
| 118 | .init_machine = sunxi_dt_init, | 101 | .init_machine = sunxi_dt_init, |
| 119 | .map_io = sunxi_map_io, | ||
| 120 | .init_irq = irqchip_init, | ||
| 121 | .init_time = sunxi_timer_init, | 102 | .init_time = sunxi_timer_init, |
| 122 | .dt_compat = sunxi_board_dt_compat, | 103 | .dt_compat = sunxi_board_dt_compat, |
| 123 | MACHINE_END | 104 | MACHINE_END |
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h deleted file mode 100644 index 33b58712adea..000000000000 --- a/arch/arm/mach-sunxi/sunxi.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Generic definitions for Allwinner SunXi SoCs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Maxime Ripard | ||
| 5 | * | ||
| 6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_SUNXI_H | ||
| 14 | #define __MACH_SUNXI_H | ||
| 15 | |||
| 16 | #define SUNXI_REGS_PHYS_BASE 0x01c00000 | ||
| 17 | #define SUNXI_REGS_VIRT_BASE IOMEM(0xf1c00000) | ||
| 18 | #define SUNXI_REGS_SIZE (SZ_2M + SZ_1M) | ||
| 19 | |||
| 20 | #endif /* __MACH_SUNXI_H */ | ||
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 8802030df98d..d6016970e2fe 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
| @@ -9,7 +9,6 @@ | |||
| 9 | #include <linux/clocksource.h> | 9 | #include <linux/clocksource.h> |
| 10 | #include <linux/smp.h> | 10 | #include <linux/smp.h> |
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/irqchip.h> | ||
| 13 | #include <linux/of_address.h> | 12 | #include <linux/of_address.h> |
| 14 | #include <linux/of_fdt.h> | 13 | #include <linux/of_fdt.h> |
| 15 | #include <linux/of_irq.h> | 14 | #include <linux/of_irq.h> |
| @@ -458,7 +457,6 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") | |||
| 458 | .smp = smp_ops(vexpress_smp_ops), | 457 | .smp = smp_ops(vexpress_smp_ops), |
| 459 | .map_io = v2m_dt_map_io, | 458 | .map_io = v2m_dt_map_io, |
| 460 | .init_early = v2m_dt_init_early, | 459 | .init_early = v2m_dt_init_early, |
| 461 | .init_irq = irqchip_init, | ||
| 462 | .init_time = v2m_dt_timer_init, | 460 | .init_time = v2m_dt_timer_init, |
| 463 | .init_machine = v2m_dt_init, | 461 | .init_machine = v2m_dt_init, |
| 464 | MACHINE_END | 462 | MACHINE_END |
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c index 061f283f579e..bdf05f41ca90 100644 --- a/arch/arm/mach-virt/virt.c +++ b/arch/arm/mach-virt/virt.c | |||
| @@ -18,7 +18,6 @@ | |||
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ | 19 | */ |
| 20 | 20 | ||
| 21 | #include <linux/irqchip.h> | ||
| 22 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
| 23 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
| 24 | #include <linux/smp.h> | 23 | #include <linux/smp.h> |
| @@ -39,7 +38,6 @@ static const char *virt_dt_match[] = { | |||
| 39 | extern struct smp_operations virt_smp_ops; | 38 | extern struct smp_operations virt_smp_ops; |
| 40 | 39 | ||
| 41 | DT_MACHINE_START(VIRT, "Dummy Virtual Machine") | 40 | DT_MACHINE_START(VIRT, "Dummy Virtual Machine") |
| 42 | .init_irq = irqchip_init, | ||
| 43 | .init_machine = virt_init, | 41 | .init_machine = virt_init, |
| 44 | .smp = smp_ops(virt_smp_ops), | 42 | .smp = smp_ops(virt_smp_ops), |
| 45 | .dt_compat = virt_dt_match, | 43 | .dt_compat = virt_dt_match, |
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index f5c33df7a597..f8f2f00856e0 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | 20 | ||
| 21 | #include <linux/clocksource.h> | 21 | #include <linux/clocksource.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/irqchip.h> | ||
| 24 | #include <linux/pm.h> | 23 | #include <linux/pm.h> |
| 25 | 24 | ||
| 26 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| @@ -179,7 +178,6 @@ static const char * const vt8500_dt_compat[] = { | |||
| 179 | DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") | 178 | DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") |
| 180 | .dt_compat = vt8500_dt_compat, | 179 | .dt_compat = vt8500_dt_compat, |
| 181 | .map_io = vt8500_map_io, | 180 | .map_io = vt8500_map_io, |
| 182 | .init_irq = irqchip_init, | ||
| 183 | .init_machine = vt8500_init, | 181 | .init_machine = vt8500_init, |
| 184 | .init_time = clocksource_of_init, | 182 | .init_time = clocksource_of_init, |
| 185 | .restart = vt8500_restart, | 183 | .restart = vt8500_restart, |
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5bfe7035b73d..4c0199b88a04 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <linux/of_irq.h> | 25 | #include <linux/of_irq.h> |
| 26 | #include <linux/of_platform.h> | 26 | #include <linux/of_platform.h> |
| 27 | #include <linux/of.h> | 27 | #include <linux/of.h> |
| 28 | #include <linux/irqchip.h> | ||
| 29 | 28 | ||
| 30 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| @@ -106,7 +105,6 @@ static const char * const zynq_dt_match[] = { | |||
| 106 | MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") | 105 | MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") |
| 107 | .smp = smp_ops(zynq_smp_ops), | 106 | .smp = smp_ops(zynq_smp_ops), |
| 108 | .map_io = zynq_map_io, | 107 | .map_io = zynq_map_io, |
| 109 | .init_irq = irqchip_init, | ||
| 110 | .init_machine = zynq_init_machine, | 108 | .init_machine = zynq_init_machine, |
| 111 | .init_time = zynq_timer_init, | 109 | .init_time = zynq_timer_init, |
| 112 | .dt_compat = zynq_dt_match, | 110 | .dt_compat = zynq_dt_match, |
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index 5fc167e07619..023f225493f2 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c | |||
| @@ -53,34 +53,34 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu) | |||
| 53 | &zynq_secondary_trampoline; | 53 | &zynq_secondary_trampoline; |
| 54 | 54 | ||
| 55 | zynq_slcr_cpu_stop(cpu); | 55 | zynq_slcr_cpu_stop(cpu); |
| 56 | 56 | if (address) { | |
| 57 | if (__pa(PAGE_OFFSET)) { | 57 | if (__pa(PAGE_OFFSET)) { |
| 58 | zero = ioremap(0, trampoline_code_size); | 58 | zero = ioremap(0, trampoline_code_size); |
| 59 | if (!zero) { | 59 | if (!zero) { |
| 60 | pr_warn("BOOTUP jump vectors not accessible\n"); | 60 | pr_warn("BOOTUP jump vectors not accessible\n"); |
| 61 | return -1; | 61 | return -1; |
| 62 | } | ||
| 63 | } else { | ||
| 64 | zero = (__force u8 __iomem *)PAGE_OFFSET; | ||
| 62 | } | 65 | } |
| 63 | } else { | ||
| 64 | zero = (__force u8 __iomem *)PAGE_OFFSET; | ||
| 65 | } | ||
| 66 | |||
| 67 | /* | ||
| 68 | * This is elegant way how to jump to any address | ||
| 69 | * 0x0: Load address at 0x8 to r0 | ||
| 70 | * 0x4: Jump by mov instruction | ||
| 71 | * 0x8: Jumping address | ||
| 72 | */ | ||
| 73 | memcpy((__force void *)zero, &zynq_secondary_trampoline, | ||
| 74 | trampoline_size); | ||
| 75 | writel(address, zero + trampoline_size); | ||
| 76 | |||
| 77 | flush_cache_all(); | ||
| 78 | outer_flush_range(0, trampoline_code_size); | ||
| 79 | smp_wmb(); | ||
| 80 | |||
| 81 | if (__pa(PAGE_OFFSET)) | ||
| 82 | iounmap(zero); | ||
| 83 | 66 | ||
| 67 | /* | ||
| 68 | * This is elegant way how to jump to any address | ||
| 69 | * 0x0: Load address at 0x8 to r0 | ||
| 70 | * 0x4: Jump by mov instruction | ||
| 71 | * 0x8: Jumping address | ||
| 72 | */ | ||
| 73 | memcpy((__force void *)zero, &zynq_secondary_trampoline, | ||
| 74 | trampoline_size); | ||
| 75 | writel(address, zero + trampoline_size); | ||
| 76 | |||
| 77 | flush_cache_all(); | ||
| 78 | outer_flush_range(0, trampoline_code_size); | ||
| 79 | smp_wmb(); | ||
| 80 | |||
| 81 | if (__pa(PAGE_OFFSET)) | ||
| 82 | iounmap(zero); | ||
| 83 | } | ||
| 84 | zynq_slcr_cpu_start(cpu); | 84 | zynq_slcr_cpu_start(cpu); |
| 85 | 85 | ||
| 86 | return 0; | 86 | return 0; |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e0d8565671a6..faa36d7b8786 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -1232,6 +1232,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc) | |||
| 1232 | */ | 1232 | */ |
| 1233 | if (mdesc->map_io) | 1233 | if (mdesc->map_io) |
| 1234 | mdesc->map_io(); | 1234 | mdesc->map_io(); |
| 1235 | else | ||
| 1236 | debug_ll_io_init(); | ||
| 1235 | fill_pmd_gaps(); | 1237 | fill_pmd_gaps(); |
| 1236 | 1238 | ||
| 1237 | /* Reserve fixed i/o space in VMALLOC region */ | 1239 | /* Reserve fixed i/o space in VMALLOC region */ |
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index 8740f46b4d0d..33c6947eebec 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c | |||
| @@ -49,6 +49,8 @@ | |||
| 49 | * configuration (file 'devices'). | 49 | * configuration (file 'devices'). |
| 50 | */ | 50 | */ |
| 51 | 51 | ||
| 52 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
| 53 | |||
| 52 | #include <linux/kernel.h> | 54 | #include <linux/kernel.h> |
| 53 | #include <linux/module.h> | 55 | #include <linux/module.h> |
| 54 | #include <linux/init.h> | 56 | #include <linux/init.h> |
| @@ -762,7 +764,7 @@ int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base, | |||
| 762 | break; | 764 | break; |
| 763 | 765 | ||
| 764 | if (!s->soc->map[i].name) { | 766 | if (!s->soc->map[i].name) { |
| 765 | pr_err("mvebu-mbus: unknown device '%s'\n", devname); | 767 | pr_err("unknown device '%s'\n", devname); |
| 766 | return -ENODEV; | 768 | return -ENODEV; |
| 767 | } | 769 | } |
| 768 | 770 | ||
| @@ -775,7 +777,7 @@ int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base, | |||
| 775 | attr |= 0x28; | 777 | attr |= 0x28; |
| 776 | 778 | ||
| 777 | if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) { | 779 | if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) { |
| 778 | pr_err("mvebu-mbus: cannot add window '%s', conflicts with another window\n", | 780 | pr_err("cannot add window '%s', conflicts with another window\n", |
| 779 | devname); | 781 | devname); |
| 780 | return -EINVAL; | 782 | return -EINVAL; |
| 781 | } | 783 | } |
| @@ -842,7 +844,7 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base, | |||
| 842 | break; | 844 | break; |
| 843 | 845 | ||
| 844 | if (!of_id->compatible) { | 846 | if (!of_id->compatible) { |
| 845 | pr_err("mvebu-mbus: could not find a matching SoC family\n"); | 847 | pr_err("could not find a matching SoC family\n"); |
| 846 | return -ENODEV; | 848 | return -ENODEV; |
| 847 | } | 849 | } |
| 848 | 850 | ||
diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c index fe7191663bbd..5511f9814ddd 100644 --- a/drivers/bus/omap-ocp2scp.c +++ b/drivers/bus/omap-ocp2scp.c | |||
| @@ -22,26 +22,6 @@ | |||
| 22 | #include <linux/pm_runtime.h> | 22 | #include <linux/pm_runtime.h> |
| 23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
| 24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
| 25 | #include <linux/platform_data/omap_ocp2scp.h> | ||
| 26 | |||
| 27 | /** | ||
| 28 | * _count_resources - count for the number of resources | ||
| 29 | * @res: struct resource * | ||
| 30 | * | ||
| 31 | * Count and return the number of resources populated for the device that is | ||
| 32 | * connected to ocp2scp. | ||
| 33 | */ | ||
| 34 | static unsigned _count_resources(struct resource *res) | ||
| 35 | { | ||
| 36 | int cnt = 0; | ||
| 37 | |||
| 38 | while (res->start != res->end) { | ||
| 39 | cnt++; | ||
| 40 | res++; | ||
| 41 | } | ||
| 42 | |||
| 43 | return cnt; | ||
| 44 | } | ||
| 45 | 25 | ||
| 46 | static int ocp2scp_remove_devices(struct device *dev, void *c) | 26 | static int ocp2scp_remove_devices(struct device *dev, void *c) |
| 47 | { | 27 | { |
| @@ -55,11 +35,7 @@ static int ocp2scp_remove_devices(struct device *dev, void *c) | |||
| 55 | static int omap_ocp2scp_probe(struct platform_device *pdev) | 35 | static int omap_ocp2scp_probe(struct platform_device *pdev) |
| 56 | { | 36 | { |
| 57 | int ret; | 37 | int ret; |
| 58 | unsigned res_cnt, i; | ||
| 59 | struct device_node *np = pdev->dev.of_node; | 38 | struct device_node *np = pdev->dev.of_node; |
| 60 | struct platform_device *pdev_child; | ||
| 61 | struct omap_ocp2scp_platform_data *pdata = pdev->dev.platform_data; | ||
| 62 | struct omap_ocp2scp_dev *dev; | ||
| 63 | 39 | ||
| 64 | if (np) { | 40 | if (np) { |
| 65 | ret = of_platform_populate(np, NULL, NULL, &pdev->dev); | 41 | ret = of_platform_populate(np, NULL, NULL, &pdev->dev); |
| @@ -68,48 +44,12 @@ static int omap_ocp2scp_probe(struct platform_device *pdev) | |||
| 68 | "failed to add resources for ocp2scp child\n"); | 44 | "failed to add resources for ocp2scp child\n"); |
| 69 | goto err0; | 45 | goto err0; |
| 70 | } | 46 | } |
| 71 | } else if (pdata) { | ||
| 72 | for (i = 0, dev = *pdata->devices; i < pdata->dev_cnt; i++, | ||
| 73 | dev++) { | ||
| 74 | res_cnt = _count_resources(dev->res); | ||
| 75 | |||
| 76 | pdev_child = platform_device_alloc(dev->drv_name, | ||
| 77 | PLATFORM_DEVID_AUTO); | ||
| 78 | if (!pdev_child) { | ||
| 79 | dev_err(&pdev->dev, | ||
| 80 | "failed to allocate mem for ocp2scp child\n"); | ||
| 81 | goto err0; | ||
| 82 | } | ||
| 83 | |||
| 84 | ret = platform_device_add_resources(pdev_child, | ||
| 85 | dev->res, res_cnt); | ||
| 86 | if (ret) { | ||
| 87 | dev_err(&pdev->dev, | ||
| 88 | "failed to add resources for ocp2scp child\n"); | ||
| 89 | goto err1; | ||
| 90 | } | ||
| 91 | |||
| 92 | pdev_child->dev.parent = &pdev->dev; | ||
| 93 | |||
| 94 | ret = platform_device_add(pdev_child); | ||
| 95 | if (ret) { | ||
| 96 | dev_err(&pdev->dev, | ||
| 97 | "failed to register ocp2scp child device\n"); | ||
| 98 | goto err1; | ||
| 99 | } | ||
| 100 | } | ||
| 101 | } else { | ||
| 102 | dev_err(&pdev->dev, "OCP2SCP initialized without plat data\n"); | ||
| 103 | return -EINVAL; | ||
| 104 | } | 47 | } |
| 105 | 48 | ||
| 106 | pm_runtime_enable(&pdev->dev); | 49 | pm_runtime_enable(&pdev->dev); |
| 107 | 50 | ||
| 108 | return 0; | 51 | return 0; |
| 109 | 52 | ||
| 110 | err1: | ||
| 111 | platform_device_put(pdev_child); | ||
| 112 | |||
| 113 | err0: | 53 | err0: |
| 114 | device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices); | 54 | device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices); |
| 115 | 55 | ||
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 573c449c49b9..847a6dc15a54 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig | |||
| @@ -165,7 +165,7 @@ config GPIO_MSM_V1 | |||
| 165 | 165 | ||
| 166 | config GPIO_MSM_V2 | 166 | config GPIO_MSM_V2 |
| 167 | tristate "Qualcomm MSM GPIO v2" | 167 | tristate "Qualcomm MSM GPIO v2" |
| 168 | depends on GPIOLIB && ARCH_MSM | 168 | depends on GPIOLIB && OF && ARCH_MSM |
| 169 | help | 169 | help |
| 170 | Say yes here to support the GPIO interface on ARM v7 based | 170 | Say yes here to support the GPIO interface on ARM v7 based |
| 171 | Qualcomm MSM chips. Most of the pins on the MSM can be | 171 | Qualcomm MSM chips. Most of the pins on the MSM can be |
diff --git a/drivers/gpio/gpio-msm-v1.c b/drivers/gpio/gpio-msm-v1.c index c798585a3fe5..fb2cc90d0134 100644 --- a/drivers/gpio/gpio-msm-v1.c +++ b/drivers/gpio/gpio-msm-v1.c | |||
| @@ -630,7 +630,7 @@ static struct irq_chip msm_gpio_irq_chip = { | |||
| 630 | .irq_set_type = msm_gpio_irq_set_type, | 630 | .irq_set_type = msm_gpio_irq_set_type, |
| 631 | }; | 631 | }; |
| 632 | 632 | ||
| 633 | static int __devinit gpio_msm_v1_probe(struct platform_device *pdev) | 633 | static int gpio_msm_v1_probe(struct platform_device *pdev) |
| 634 | { | 634 | { |
| 635 | int i, j = 0; | 635 | int i, j = 0; |
| 636 | const struct platform_device_id *dev_id = platform_get_device_id(pdev); | 636 | const struct platform_device_id *dev_id = platform_get_device_id(pdev); |
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c index dd2eddeb1e0c..f4491a497cc8 100644 --- a/drivers/gpio/gpio-msm-v2.c +++ b/drivers/gpio/gpio-msm-v2.c | |||
| @@ -19,18 +19,21 @@ | |||
| 19 | 19 | ||
| 20 | #include <linux/bitmap.h> | 20 | #include <linux/bitmap.h> |
| 21 | #include <linux/bitops.h> | 21 | #include <linux/bitops.h> |
| 22 | #include <linux/err.h> | ||
| 22 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
| 23 | #include <linux/init.h> | 24 | #include <linux/init.h> |
| 24 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 25 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 26 | #include <linux/irqchip/chained_irq.h> | 27 | #include <linux/irqchip/chained_irq.h> |
| 27 | #include <linux/irq.h> | 28 | #include <linux/irq.h> |
| 29 | #include <linux/irqdomain.h> | ||
| 28 | #include <linux/module.h> | 30 | #include <linux/module.h> |
| 31 | #include <linux/of_address.h> | ||
| 29 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
| 30 | #include <linux/spinlock.h> | 33 | #include <linux/spinlock.h> |
| 34 | #include <linux/slab.h> | ||
| 31 | 35 | ||
| 32 | #include <mach/msm_gpiomux.h> | 36 | #define MAX_NR_GPIO 300 |
| 33 | #include <mach/msm_iomap.h> | ||
| 34 | 37 | ||
| 35 | /* Bits of interest in the GPIO_IN_OUT register. | 38 | /* Bits of interest in the GPIO_IN_OUT register. |
| 36 | */ | 39 | */ |
| @@ -77,13 +80,6 @@ enum { | |||
| 77 | TARGET_PROC_NONE = 7, | 80 | TARGET_PROC_NONE = 7, |
| 78 | }; | 81 | }; |
| 79 | 82 | ||
| 80 | |||
| 81 | #define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) | ||
| 82 | #define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) | ||
| 83 | #define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) | ||
| 84 | #define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) | ||
| 85 | #define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) | ||
| 86 | |||
| 87 | /** | 83 | /** |
| 88 | * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure | 84 | * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure |
| 89 | * | 85 | * |
| @@ -102,11 +98,27 @@ enum { | |||
| 102 | */ | 98 | */ |
| 103 | struct msm_gpio_dev { | 99 | struct msm_gpio_dev { |
| 104 | struct gpio_chip gpio_chip; | 100 | struct gpio_chip gpio_chip; |
| 105 | DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); | 101 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); |
| 106 | DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); | 102 | DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO); |
| 107 | DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); | 103 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
| 104 | struct irq_domain *domain; | ||
| 105 | unsigned int summary_irq; | ||
| 106 | void __iomem *msm_tlmm_base; | ||
| 108 | }; | 107 | }; |
| 109 | 108 | ||
| 109 | struct msm_gpio_dev msm_gpio; | ||
| 110 | |||
| 111 | #define GPIO_INTR_CFG_SU(gpio) (msm_gpio.msm_tlmm_base + 0x0400 + \ | ||
| 112 | (0x04 * (gpio))) | ||
| 113 | #define GPIO_CONFIG(gpio) (msm_gpio.msm_tlmm_base + 0x1000 + \ | ||
| 114 | (0x10 * (gpio))) | ||
| 115 | #define GPIO_IN_OUT(gpio) (msm_gpio.msm_tlmm_base + 0x1004 + \ | ||
| 116 | (0x10 * (gpio))) | ||
| 117 | #define GPIO_INTR_CFG(gpio) (msm_gpio.msm_tlmm_base + 0x1008 + \ | ||
| 118 | (0x10 * (gpio))) | ||
| 119 | #define GPIO_INTR_STATUS(gpio) (msm_gpio.msm_tlmm_base + 0x100c + \ | ||
| 120 | (0x10 * (gpio))) | ||
| 121 | |||
| 110 | static DEFINE_SPINLOCK(tlmm_lock); | 122 | static DEFINE_SPINLOCK(tlmm_lock); |
| 111 | 123 | ||
| 112 | static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) | 124 | static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) |
| @@ -159,37 +171,29 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, | |||
| 159 | 171 | ||
| 160 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) | 172 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 161 | { | 173 | { |
| 162 | return msm_gpiomux_get(chip->base + offset); | 174 | return 0; |
| 163 | } | 175 | } |
| 164 | 176 | ||
| 165 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | 177 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 166 | { | 178 | { |
| 167 | msm_gpiomux_put(chip->base + offset); | 179 | return; |
| 168 | } | 180 | } |
| 169 | 181 | ||
| 170 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | 182 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 171 | { | 183 | { |
| 172 | return MSM_GPIO_TO_INT(chip->base + offset); | 184 | struct msm_gpio_dev *g_dev = to_msm_gpio_dev(chip); |
| 185 | struct irq_domain *domain = g_dev->domain; | ||
| 186 | |||
| 187 | return irq_create_mapping(domain, offset); | ||
| 173 | } | 188 | } |
| 174 | 189 | ||
| 175 | static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) | 190 | static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) |
| 176 | { | 191 | { |
| 177 | return irq - MSM_GPIO_TO_INT(chip->base); | 192 | struct irq_data *irq_data = irq_get_irq_data(irq); |
| 193 | |||
| 194 | return irq_data->hwirq; | ||
| 178 | } | 195 | } |
| 179 | 196 | ||
| 180 | static struct msm_gpio_dev msm_gpio = { | ||
| 181 | .gpio_chip = { | ||
| 182 | .base = 0, | ||
| 183 | .ngpio = NR_GPIO_IRQS, | ||
| 184 | .direction_input = msm_gpio_direction_input, | ||
| 185 | .direction_output = msm_gpio_direction_output, | ||
| 186 | .get = msm_gpio_get, | ||
| 187 | .set = msm_gpio_set, | ||
| 188 | .to_irq = msm_gpio_to_irq, | ||
| 189 | .request = msm_gpio_request, | ||
| 190 | .free = msm_gpio_free, | ||
| 191 | }, | ||
| 192 | }; | ||
| 193 | 197 | ||
| 194 | /* For dual-edge interrupts in software, since the hardware has no | 198 | /* For dual-edge interrupts in software, since the hardware has no |
| 195 | * such support: | 199 | * such support: |
| @@ -227,9 +231,9 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio) | |||
| 227 | if (intstat || val == val2) | 231 | if (intstat || val == val2) |
| 228 | return; | 232 | return; |
| 229 | } while (loop_limit-- > 0); | 233 | } while (loop_limit-- > 0); |
| 230 | pr_err("dual-edge irq failed to stabilize, " | 234 | pr_err("%s: dual-edge irq failed to stabilize, " |
| 231 | "interrupts dropped. %#08x != %#08x\n", | 235 | "interrupts dropped. %#08x != %#08x\n", |
| 232 | val, val2); | 236 | __func__, val, val2); |
| 233 | } | 237 | } |
| 234 | 238 | ||
| 235 | static void msm_gpio_irq_ack(struct irq_data *d) | 239 | static void msm_gpio_irq_ack(struct irq_data *d) |
| @@ -316,10 +320,10 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 316 | 320 | ||
| 317 | chained_irq_enter(chip, desc); | 321 | chained_irq_enter(chip, desc); |
| 318 | 322 | ||
| 319 | for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) { | 323 | for_each_set_bit(i, msm_gpio.enabled_irqs, MAX_NR_GPIO) { |
| 320 | if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) | 324 | if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) |
| 321 | generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, | 325 | generic_handle_irq(irq_find_mapping(msm_gpio.domain, |
| 322 | i)); | 326 | i)); |
| 323 | } | 327 | } |
| 324 | 328 | ||
| 325 | chained_irq_exit(chip, desc); | 329 | chained_irq_exit(chip, desc); |
| @@ -330,13 +334,13 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |||
| 330 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); | 334 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); |
| 331 | 335 | ||
| 332 | if (on) { | 336 | if (on) { |
| 333 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | 337 | if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO)) |
| 334 | irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); | 338 | irq_set_irq_wake(msm_gpio.summary_irq, 1); |
| 335 | set_bit(gpio, msm_gpio.wake_irqs); | 339 | set_bit(gpio, msm_gpio.wake_irqs); |
| 336 | } else { | 340 | } else { |
| 337 | clear_bit(gpio, msm_gpio.wake_irqs); | 341 | clear_bit(gpio, msm_gpio.wake_irqs); |
| 338 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | 342 | if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO)) |
| 339 | irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); | 343 | irq_set_irq_wake(msm_gpio.summary_irq, 0); |
| 340 | } | 344 | } |
| 341 | 345 | ||
| 342 | return 0; | 346 | return 0; |
| @@ -351,30 +355,86 @@ static struct irq_chip msm_gpio_irq_chip = { | |||
| 351 | .irq_set_wake = msm_gpio_irq_set_wake, | 355 | .irq_set_wake = msm_gpio_irq_set_wake, |
| 352 | }; | 356 | }; |
| 353 | 357 | ||
| 354 | static int msm_gpio_probe(struct platform_device *dev) | 358 | static struct lock_class_key msm_gpio_lock_class; |
| 359 | |||
| 360 | static int msm_gpio_irq_domain_map(struct irq_domain *d, unsigned int irq, | ||
| 361 | irq_hw_number_t hwirq) | ||
| 355 | { | 362 | { |
| 356 | int i, irq, ret; | 363 | irq_set_lockdep_class(irq, &msm_gpio_lock_class); |
| 364 | irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, | ||
| 365 | handle_level_irq); | ||
| 366 | set_irq_flags(irq, IRQF_VALID); | ||
| 367 | |||
| 368 | return 0; | ||
| 369 | } | ||
| 370 | |||
| 371 | static const struct irq_domain_ops msm_gpio_irq_domain_ops = { | ||
| 372 | .xlate = irq_domain_xlate_twocell, | ||
| 373 | .map = msm_gpio_irq_domain_map, | ||
| 374 | }; | ||
| 375 | |||
| 376 | static int msm_gpio_probe(struct platform_device *pdev) | ||
| 377 | { | ||
| 378 | int ret, ngpio; | ||
| 379 | struct resource *res; | ||
| 380 | |||
| 381 | if (!of_property_read_u32(pdev->dev.of_node, "ngpio", &ngpio)) { | ||
| 382 | dev_err(&pdev->dev, "%s: ngpio property missing\n", __func__); | ||
| 383 | return -EINVAL; | ||
| 384 | } | ||
| 385 | |||
| 386 | if (ngpio > MAX_NR_GPIO) | ||
| 387 | WARN(1, "ngpio exceeds the MAX_NR_GPIO. Increase MAX_NR_GPIO\n"); | ||
| 388 | |||
| 389 | bitmap_zero(msm_gpio.enabled_irqs, MAX_NR_GPIO); | ||
| 390 | bitmap_zero(msm_gpio.wake_irqs, MAX_NR_GPIO); | ||
| 391 | bitmap_zero(msm_gpio.dual_edge_irqs, MAX_NR_GPIO); | ||
| 392 | |||
| 393 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 394 | msm_gpio.msm_tlmm_base = devm_ioremap_resource(&pdev->dev, res); | ||
| 395 | if (IS_ERR(msm_gpio.msm_tlmm_base)) | ||
| 396 | return PTR_ERR(msm_gpio.msm_tlmm_base); | ||
| 397 | |||
| 398 | msm_gpio.gpio_chip.ngpio = ngpio; | ||
| 399 | msm_gpio.gpio_chip.label = pdev->name; | ||
| 400 | msm_gpio.gpio_chip.dev = &pdev->dev; | ||
| 401 | msm_gpio.gpio_chip.base = 0; | ||
| 402 | msm_gpio.gpio_chip.direction_input = msm_gpio_direction_input; | ||
| 403 | msm_gpio.gpio_chip.direction_output = msm_gpio_direction_output; | ||
| 404 | msm_gpio.gpio_chip.get = msm_gpio_get; | ||
| 405 | msm_gpio.gpio_chip.set = msm_gpio_set; | ||
| 406 | msm_gpio.gpio_chip.to_irq = msm_gpio_to_irq; | ||
| 407 | msm_gpio.gpio_chip.request = msm_gpio_request; | ||
| 408 | msm_gpio.gpio_chip.free = msm_gpio_free; | ||
| 357 | 409 | ||
| 358 | bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); | ||
| 359 | bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); | ||
| 360 | bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); | ||
| 361 | msm_gpio.gpio_chip.label = dev->name; | ||
| 362 | ret = gpiochip_add(&msm_gpio.gpio_chip); | 410 | ret = gpiochip_add(&msm_gpio.gpio_chip); |
| 363 | if (ret < 0) | 411 | if (ret < 0) { |
| 412 | dev_err(&pdev->dev, "gpiochip_add failed with error %d\n", ret); | ||
| 364 | return ret; | 413 | return ret; |
| 414 | } | ||
| 365 | 415 | ||
| 366 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { | 416 | msm_gpio.summary_irq = platform_get_irq(pdev, 0); |
| 367 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); | 417 | if (msm_gpio.summary_irq < 0) { |
| 368 | irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, | 418 | dev_err(&pdev->dev, "No Summary irq defined for msmgpio\n"); |
| 369 | handle_level_irq); | 419 | return msm_gpio.summary_irq; |
| 370 | set_irq_flags(irq, IRQF_VALID); | ||
| 371 | } | 420 | } |
| 372 | 421 | ||
| 373 | irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ, | 422 | msm_gpio.domain = irq_domain_add_linear(pdev->dev.of_node, ngpio, |
| 374 | msm_summary_irq_handler); | 423 | &msm_gpio_irq_domain_ops, |
| 424 | &msm_gpio); | ||
| 425 | if (!msm_gpio.domain) | ||
| 426 | return -ENODEV; | ||
| 427 | |||
| 428 | irq_set_chained_handler(msm_gpio.summary_irq, msm_summary_irq_handler); | ||
| 429 | |||
| 375 | return 0; | 430 | return 0; |
| 376 | } | 431 | } |
| 377 | 432 | ||
| 433 | static struct of_device_id msm_gpio_of_match[] = { | ||
| 434 | { .compatible = "qcom,msm-gpio", }, | ||
| 435 | { }, | ||
| 436 | }; | ||
| 437 | |||
| 378 | static int msm_gpio_remove(struct platform_device *dev) | 438 | static int msm_gpio_remove(struct platform_device *dev) |
| 379 | { | 439 | { |
| 380 | int ret = gpiochip_remove(&msm_gpio.gpio_chip); | 440 | int ret = gpiochip_remove(&msm_gpio.gpio_chip); |
| @@ -382,7 +442,7 @@ static int msm_gpio_remove(struct platform_device *dev) | |||
| 382 | if (ret < 0) | 442 | if (ret < 0) |
| 383 | return ret; | 443 | return ret; |
| 384 | 444 | ||
| 385 | irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); | 445 | irq_set_handler(msm_gpio.summary_irq, NULL); |
| 386 | 446 | ||
| 387 | return 0; | 447 | return 0; |
| 388 | } | 448 | } |
| @@ -393,36 +453,11 @@ static struct platform_driver msm_gpio_driver = { | |||
| 393 | .driver = { | 453 | .driver = { |
| 394 | .name = "msmgpio", | 454 | .name = "msmgpio", |
| 395 | .owner = THIS_MODULE, | 455 | .owner = THIS_MODULE, |
| 456 | .of_match_table = msm_gpio_of_match, | ||
| 396 | }, | 457 | }, |
| 397 | }; | 458 | }; |
| 398 | 459 | ||
| 399 | static struct platform_device msm_device_gpio = { | 460 | module_platform_driver(msm_gpio_driver) |
| 400 | .name = "msmgpio", | ||
| 401 | .id = -1, | ||
| 402 | }; | ||
| 403 | |||
| 404 | static int __init msm_gpio_init(void) | ||
| 405 | { | ||
| 406 | int rc; | ||
| 407 | |||
| 408 | rc = platform_driver_register(&msm_gpio_driver); | ||
| 409 | if (!rc) { | ||
| 410 | rc = platform_device_register(&msm_device_gpio); | ||
| 411 | if (rc) | ||
| 412 | platform_driver_unregister(&msm_gpio_driver); | ||
| 413 | } | ||
| 414 | |||
| 415 | return rc; | ||
| 416 | } | ||
| 417 | |||
| 418 | static void __exit msm_gpio_exit(void) | ||
| 419 | { | ||
| 420 | platform_device_unregister(&msm_device_gpio); | ||
| 421 | platform_driver_unregister(&msm_gpio_driver); | ||
| 422 | } | ||
| 423 | |||
| 424 | postcore_initcall(msm_gpio_init); | ||
| 425 | module_exit(msm_gpio_exit); | ||
| 426 | 461 | ||
| 427 | MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>"); | 462 | MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>"); |
| 428 | MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); | 463 | MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); |
diff --git a/drivers/of/address.c b/drivers/of/address.c index 04da786c84d2..fdd0636a987d 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c | |||
| @@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar, | |||
| 227 | return __of_address_to_resource(dev, addrp, size, flags, NULL, r); | 227 | return __of_address_to_resource(dev, addrp, size, flags, NULL, r); |
| 228 | } | 228 | } |
| 229 | EXPORT_SYMBOL_GPL(of_pci_address_to_resource); | 229 | EXPORT_SYMBOL_GPL(of_pci_address_to_resource); |
| 230 | |||
| 231 | int of_pci_range_parser_init(struct of_pci_range_parser *parser, | ||
| 232 | struct device_node *node) | ||
| 233 | { | ||
| 234 | const int na = 3, ns = 2; | ||
| 235 | int rlen; | ||
| 236 | |||
| 237 | parser->node = node; | ||
| 238 | parser->pna = of_n_addr_cells(node); | ||
| 239 | parser->np = parser->pna + na + ns; | ||
| 240 | |||
| 241 | parser->range = of_get_property(node, "ranges", &rlen); | ||
| 242 | if (parser->range == NULL) | ||
| 243 | return -ENOENT; | ||
| 244 | |||
| 245 | parser->end = parser->range + rlen / sizeof(__be32); | ||
| 246 | |||
| 247 | return 0; | ||
| 248 | } | ||
| 249 | EXPORT_SYMBOL_GPL(of_pci_range_parser_init); | ||
| 250 | |||
| 251 | struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, | ||
| 252 | struct of_pci_range *range) | ||
| 253 | { | ||
| 254 | const int na = 3, ns = 2; | ||
| 255 | |||
| 256 | if (!range) | ||
| 257 | return NULL; | ||
| 258 | |||
| 259 | if (!parser->range || parser->range + parser->np > parser->end) | ||
| 260 | return NULL; | ||
| 261 | |||
| 262 | range->pci_space = parser->range[0]; | ||
| 263 | range->flags = of_bus_pci_get_flags(parser->range); | ||
| 264 | range->pci_addr = of_read_number(parser->range + 1, ns); | ||
| 265 | range->cpu_addr = of_translate_address(parser->node, | ||
| 266 | parser->range + na); | ||
| 267 | range->size = of_read_number(parser->range + parser->pna + na, ns); | ||
| 268 | |||
| 269 | parser->range += parser->np; | ||
| 270 | |||
| 271 | /* Now consume following elements while they are contiguous */ | ||
| 272 | while (parser->range + parser->np <= parser->end) { | ||
| 273 | u32 flags, pci_space; | ||
| 274 | u64 pci_addr, cpu_addr, size; | ||
| 275 | |||
| 276 | pci_space = be32_to_cpup(parser->range); | ||
| 277 | flags = of_bus_pci_get_flags(parser->range); | ||
| 278 | pci_addr = of_read_number(parser->range + 1, ns); | ||
| 279 | cpu_addr = of_translate_address(parser->node, | ||
| 280 | parser->range + na); | ||
| 281 | size = of_read_number(parser->range + parser->pna + na, ns); | ||
| 282 | |||
| 283 | if (flags != range->flags) | ||
| 284 | break; | ||
| 285 | if (pci_addr != range->pci_addr + range->size || | ||
| 286 | cpu_addr != range->cpu_addr + range->size) | ||
| 287 | break; | ||
| 288 | |||
| 289 | range->size += size; | ||
| 290 | parser->range += parser->np; | ||
| 291 | } | ||
| 292 | |||
| 293 | return range; | ||
| 294 | } | ||
| 295 | EXPORT_SYMBOL_GPL(of_pci_range_parser_one); | ||
| 296 | |||
| 230 | #endif /* CONFIG_PCI */ | 297 | #endif /* CONFIG_PCI */ |
| 231 | 298 | ||
| 232 | /* | 299 | /* |
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c index 13e37e2d8ec1..42c687a820ac 100644 --- a/drivers/of/of_pci.c +++ b/drivers/of/of_pci.c | |||
| @@ -5,14 +5,15 @@ | |||
| 5 | #include <asm/prom.h> | 5 | #include <asm/prom.h> |
| 6 | 6 | ||
| 7 | static inline int __of_pci_pci_compare(struct device_node *node, | 7 | static inline int __of_pci_pci_compare(struct device_node *node, |
| 8 | unsigned int devfn) | 8 | unsigned int data) |
| 9 | { | 9 | { |
| 10 | unsigned int size; | 10 | int devfn; |
| 11 | const __be32 *reg = of_get_property(node, "reg", &size); | ||
| 12 | 11 | ||
| 13 | if (!reg || size < 5 * sizeof(__be32)) | 12 | devfn = of_pci_get_devfn(node); |
| 13 | if (devfn < 0) | ||
| 14 | return 0; | 14 | return 0; |
| 15 | return ((be32_to_cpup(®[0]) >> 8) & 0xff) == devfn; | 15 | |
| 16 | return devfn == data; | ||
| 16 | } | 17 | } |
| 17 | 18 | ||
| 18 | struct device_node *of_pci_find_child_device(struct device_node *parent, | 19 | struct device_node *of_pci_find_child_device(struct device_node *parent, |
| @@ -40,3 +41,51 @@ struct device_node *of_pci_find_child_device(struct device_node *parent, | |||
| 40 | return NULL; | 41 | return NULL; |
| 41 | } | 42 | } |
| 42 | EXPORT_SYMBOL_GPL(of_pci_find_child_device); | 43 | EXPORT_SYMBOL_GPL(of_pci_find_child_device); |
| 44 | |||
| 45 | /** | ||
| 46 | * of_pci_get_devfn() - Get device and function numbers for a device node | ||
| 47 | * @np: device node | ||
| 48 | * | ||
| 49 | * Parses a standard 5-cell PCI resource and returns an 8-bit value that can | ||
| 50 | * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device | ||
| 51 | * and function numbers respectively. On error a negative error code is | ||
| 52 | * returned. | ||
| 53 | */ | ||
| 54 | int of_pci_get_devfn(struct device_node *np) | ||
| 55 | { | ||
| 56 | unsigned int size; | ||
| 57 | const __be32 *reg; | ||
| 58 | |||
| 59 | reg = of_get_property(np, "reg", &size); | ||
| 60 | |||
| 61 | if (!reg || size < 5 * sizeof(__be32)) | ||
| 62 | return -EINVAL; | ||
| 63 | |||
| 64 | return (be32_to_cpup(reg) >> 8) & 0xff; | ||
| 65 | } | ||
| 66 | EXPORT_SYMBOL_GPL(of_pci_get_devfn); | ||
| 67 | |||
| 68 | /** | ||
| 69 | * of_pci_parse_bus_range() - parse the bus-range property of a PCI device | ||
| 70 | * @node: device node | ||
| 71 | * @res: address to a struct resource to return the bus-range | ||
| 72 | * | ||
| 73 | * Returns 0 on success or a negative error-code on failure. | ||
| 74 | */ | ||
| 75 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res) | ||
| 76 | { | ||
| 77 | const __be32 *values; | ||
| 78 | int len; | ||
| 79 | |||
| 80 | values = of_get_property(node, "bus-range", &len); | ||
| 81 | if (!values || len < sizeof(*values) * 2) | ||
| 82 | return -EINVAL; | ||
| 83 | |||
| 84 | res->name = node->name; | ||
| 85 | res->start = be32_to_cpup(values++); | ||
| 86 | res->end = be32_to_cpup(values); | ||
| 87 | res->flags = IORESOURCE_BUS; | ||
| 88 | |||
| 89 | return 0; | ||
| 90 | } | ||
| 91 | EXPORT_SYMBOL_GPL(of_pci_parse_bus_range); | ||
diff --git a/drivers/ssbi/ssbi.c b/drivers/ssbi/ssbi.c index f32da0258a8e..102a22844297 100644 --- a/drivers/ssbi/ssbi.c +++ b/drivers/ssbi/ssbi.c | |||
| @@ -268,35 +268,23 @@ static int ssbi_probe(struct platform_device *pdev) | |||
| 268 | struct device_node *np = pdev->dev.of_node; | 268 | struct device_node *np = pdev->dev.of_node; |
| 269 | struct resource *mem_res; | 269 | struct resource *mem_res; |
| 270 | struct ssbi *ssbi; | 270 | struct ssbi *ssbi; |
| 271 | int ret = 0; | ||
| 272 | const char *type; | 271 | const char *type; |
| 273 | 272 | ||
| 274 | ssbi = kzalloc(sizeof(struct ssbi), GFP_KERNEL); | 273 | ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL); |
| 275 | if (!ssbi) { | 274 | if (!ssbi) |
| 276 | pr_err("can not allocate ssbi_data\n"); | ||
| 277 | return -ENOMEM; | 275 | return -ENOMEM; |
| 278 | } | ||
| 279 | 276 | ||
| 280 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 277 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 281 | if (!mem_res) { | 278 | ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res); |
| 282 | pr_err("missing mem resource\n"); | 279 | if (IS_ERR(ssbi->base)) |
| 283 | ret = -EINVAL; | 280 | return PTR_ERR(ssbi->base); |
| 284 | goto err_get_mem_res; | ||
| 285 | } | ||
| 286 | 281 | ||
| 287 | ssbi->base = ioremap(mem_res->start, resource_size(mem_res)); | ||
| 288 | if (!ssbi->base) { | ||
| 289 | pr_err("ioremap of 0x%p failed\n", (void *)mem_res->start); | ||
| 290 | ret = -EINVAL; | ||
| 291 | goto err_ioremap; | ||
| 292 | } | ||
| 293 | platform_set_drvdata(pdev, ssbi); | 282 | platform_set_drvdata(pdev, ssbi); |
| 294 | 283 | ||
| 295 | type = of_get_property(np, "qcom,controller-type", NULL); | 284 | type = of_get_property(np, "qcom,controller-type", NULL); |
| 296 | if (type == NULL) { | 285 | if (type == NULL) { |
| 297 | pr_err("Missing qcom,controller-type property\n"); | 286 | dev_err(&pdev->dev, "Missing qcom,controller-type property\n"); |
| 298 | ret = -EINVAL; | 287 | return -EINVAL; |
| 299 | goto err_ssbi_controller; | ||
| 300 | } | 288 | } |
| 301 | dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type); | 289 | dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type); |
| 302 | if (strcmp(type, "ssbi") == 0) | 290 | if (strcmp(type, "ssbi") == 0) |
| @@ -306,9 +294,8 @@ static int ssbi_probe(struct platform_device *pdev) | |||
| 306 | else if (strcmp(type, "pmic-arbiter") == 0) | 294 | else if (strcmp(type, "pmic-arbiter") == 0) |
| 307 | ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER; | 295 | ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER; |
| 308 | else { | 296 | else { |
| 309 | pr_err("Unknown qcom,controller-type\n"); | 297 | dev_err(&pdev->dev, "Unknown qcom,controller-type\n"); |
| 310 | ret = -EINVAL; | 298 | return -EINVAL; |
| 311 | goto err_ssbi_controller; | ||
| 312 | } | 299 | } |
| 313 | 300 | ||
| 314 | if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) { | 301 | if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) { |
| @@ -321,57 +308,24 @@ static int ssbi_probe(struct platform_device *pdev) | |||
| 321 | 308 | ||
| 322 | spin_lock_init(&ssbi->lock); | 309 | spin_lock_init(&ssbi->lock); |
| 323 | 310 | ||
| 324 | ret = of_platform_populate(np, NULL, NULL, &pdev->dev); | 311 | return of_platform_populate(np, NULL, NULL, &pdev->dev); |
| 325 | if (ret) | ||
| 326 | goto err_ssbi_controller; | ||
| 327 | |||
| 328 | return 0; | ||
| 329 | |||
| 330 | err_ssbi_controller: | ||
| 331 | platform_set_drvdata(pdev, NULL); | ||
| 332 | iounmap(ssbi->base); | ||
| 333 | err_ioremap: | ||
| 334 | err_get_mem_res: | ||
| 335 | kfree(ssbi); | ||
| 336 | return ret; | ||
| 337 | } | ||
| 338 | |||
| 339 | static int ssbi_remove(struct platform_device *pdev) | ||
| 340 | { | ||
| 341 | struct ssbi *ssbi = platform_get_drvdata(pdev); | ||
| 342 | |||
| 343 | platform_set_drvdata(pdev, NULL); | ||
| 344 | iounmap(ssbi->base); | ||
| 345 | kfree(ssbi); | ||
| 346 | return 0; | ||
| 347 | } | 312 | } |
| 348 | 313 | ||
| 349 | static struct of_device_id ssbi_match_table[] = { | 314 | static struct of_device_id ssbi_match_table[] = { |
| 350 | { .compatible = "qcom,ssbi" }, | 315 | { .compatible = "qcom,ssbi" }, |
| 351 | {} | 316 | {} |
| 352 | }; | 317 | }; |
| 318 | MODULE_DEVICE_TABLE(of, ssbi_match_table); | ||
| 353 | 319 | ||
| 354 | static struct platform_driver ssbi_driver = { | 320 | static struct platform_driver ssbi_driver = { |
| 355 | .probe = ssbi_probe, | 321 | .probe = ssbi_probe, |
| 356 | .remove = ssbi_remove, | ||
| 357 | .driver = { | 322 | .driver = { |
| 358 | .name = "ssbi", | 323 | .name = "ssbi", |
| 359 | .owner = THIS_MODULE, | 324 | .owner = THIS_MODULE, |
| 360 | .of_match_table = ssbi_match_table, | 325 | .of_match_table = ssbi_match_table, |
| 361 | }, | 326 | }, |
| 362 | }; | 327 | }; |
| 363 | 328 | module_platform_driver(ssbi_driver); | |
| 364 | static int __init ssbi_init(void) | ||
| 365 | { | ||
| 366 | return platform_driver_register(&ssbi_driver); | ||
| 367 | } | ||
| 368 | module_init(ssbi_init); | ||
| 369 | |||
| 370 | static void __exit ssbi_exit(void) | ||
| 371 | { | ||
| 372 | platform_driver_unregister(&ssbi_driver); | ||
| 373 | } | ||
| 374 | module_exit(ssbi_exit) | ||
| 375 | 329 | ||
| 376 | MODULE_LICENSE("GPL v2"); | 330 | MODULE_LICENSE("GPL v2"); |
| 377 | MODULE_VERSION("1.0"); | 331 | MODULE_VERSION("1.0"); |
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h new file mode 100644 index 000000000000..d7988b4d8af9 --- /dev/null +++ b/include/dt-bindings/pinctrl/at91.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for most at91 pinctrl bindings. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | ||
| 5 | * | ||
| 6 | * GPLv2 only | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __DT_BINDINGS_AT91_PINCTRL_H__ | ||
| 10 | #define __DT_BINDINGS_AT91_PINCTRL_H__ | ||
| 11 | |||
| 12 | #define AT91_PINCTRL_NONE (0 << 0) | ||
| 13 | #define AT91_PINCTRL_PULL_UP (1 << 0) | ||
| 14 | #define AT91_PINCTRL_MULTI_DRIVE (1 << 1) | ||
| 15 | #define AT91_PINCTRL_DEGLITCH (1 << 2) | ||
| 16 | #define AT91_PINCTRL_PULL_DOWN (1 << 3) | ||
| 17 | #define AT91_PINCTRL_DIS_SCHMIT (1 << 4) | ||
| 18 | #define AT91_PINCTRL_DEBOUNCE (1 << 16) | ||
| 19 | #define AT91_PINCTRL_DEBOUNCE_VA(x) (x << 17) | ||
| 20 | |||
| 21 | #define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) | ||
| 22 | |||
| 23 | #define AT91_PIOA 0 | ||
| 24 | #define AT91_PIOB 1 | ||
| 25 | #define AT91_PIOC 2 | ||
| 26 | #define AT91_PIOD 3 | ||
| 27 | #define AT91_PIOE 4 | ||
| 28 | |||
| 29 | #define AT91_PERIPH_GPIO 0 | ||
| 30 | #define AT91_PERIPH_A 1 | ||
| 31 | #define AT91_PERIPH_B 2 | ||
| 32 | #define AT91_PERIPH_C 3 | ||
| 33 | #define AT91_PERIPH_D 4 | ||
| 34 | |||
| 35 | #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ | ||
diff --git a/include/linux/of_address.h b/include/linux/of_address.h index 0506eb53519b..4c2e6f26432c 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h | |||
| @@ -4,6 +4,36 @@ | |||
| 4 | #include <linux/errno.h> | 4 | #include <linux/errno.h> |
| 5 | #include <linux/of.h> | 5 | #include <linux/of.h> |
| 6 | 6 | ||
| 7 | struct of_pci_range_parser { | ||
| 8 | struct device_node *node; | ||
| 9 | const __be32 *range; | ||
| 10 | const __be32 *end; | ||
| 11 | int np; | ||
| 12 | int pna; | ||
| 13 | }; | ||
| 14 | |||
| 15 | struct of_pci_range { | ||
| 16 | u32 pci_space; | ||
| 17 | u64 pci_addr; | ||
| 18 | u64 cpu_addr; | ||
| 19 | u64 size; | ||
| 20 | u32 flags; | ||
| 21 | }; | ||
| 22 | |||
| 23 | #define for_each_of_pci_range(parser, range) \ | ||
| 24 | for (; of_pci_range_parser_one(parser, range);) | ||
| 25 | |||
| 26 | static inline void of_pci_range_to_resource(struct of_pci_range *range, | ||
| 27 | struct device_node *np, | ||
| 28 | struct resource *res) | ||
| 29 | { | ||
| 30 | res->flags = range->flags; | ||
| 31 | res->start = range->cpu_addr; | ||
| 32 | res->end = range->cpu_addr + range->size - 1; | ||
| 33 | res->parent = res->child = res->sibling = NULL; | ||
| 34 | res->name = np->full_name; | ||
| 35 | } | ||
| 36 | |||
| 7 | #ifdef CONFIG_OF_ADDRESS | 37 | #ifdef CONFIG_OF_ADDRESS |
| 8 | extern u64 of_translate_address(struct device_node *np, const __be32 *addr); | 38 | extern u64 of_translate_address(struct device_node *np, const __be32 *addr); |
| 9 | extern bool of_can_translate_address(struct device_node *dev); | 39 | extern bool of_can_translate_address(struct device_node *dev); |
| @@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } | |||
| 27 | #define pci_address_to_pio pci_address_to_pio | 57 | #define pci_address_to_pio pci_address_to_pio |
| 28 | #endif | 58 | #endif |
| 29 | 59 | ||
| 60 | extern int of_pci_range_parser_init(struct of_pci_range_parser *parser, | ||
| 61 | struct device_node *node); | ||
| 62 | extern struct of_pci_range *of_pci_range_parser_one( | ||
| 63 | struct of_pci_range_parser *parser, | ||
| 64 | struct of_pci_range *range); | ||
| 30 | #else /* CONFIG_OF_ADDRESS */ | 65 | #else /* CONFIG_OF_ADDRESS */ |
| 31 | #ifndef of_address_to_resource | 66 | #ifndef of_address_to_resource |
| 32 | static inline int of_address_to_resource(struct device_node *dev, int index, | 67 | static inline int of_address_to_resource(struct device_node *dev, int index, |
| @@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index, | |||
| 53 | { | 88 | { |
| 54 | return NULL; | 89 | return NULL; |
| 55 | } | 90 | } |
| 91 | |||
| 92 | static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser, | ||
| 93 | struct device_node *node) | ||
| 94 | { | ||
| 95 | return -1; | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline struct of_pci_range *of_pci_range_parser_one( | ||
| 99 | struct of_pci_range_parser *parser, | ||
| 100 | struct of_pci_range *range) | ||
| 101 | { | ||
| 102 | return NULL; | ||
| 103 | } | ||
| 56 | #endif /* CONFIG_OF_ADDRESS */ | 104 | #endif /* CONFIG_OF_ADDRESS */ |
| 57 | 105 | ||
| 58 | 106 | ||
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index bb115deb7612..7a04826018c0 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h | |||
| @@ -10,5 +10,7 @@ int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq); | |||
| 10 | struct device_node; | 10 | struct device_node; |
| 11 | struct device_node *of_pci_find_child_device(struct device_node *parent, | 11 | struct device_node *of_pci_find_child_device(struct device_node *parent, |
| 12 | unsigned int devfn); | 12 | unsigned int devfn); |
| 13 | int of_pci_get_devfn(struct device_node *np); | ||
| 14 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | ||
| 13 | 15 | ||
| 14 | #endif | 16 | #endif |
diff --git a/include/linux/platform_data/omap_ocp2scp.h b/include/linux/platform_data/omap_ocp2scp.h deleted file mode 100644 index 5c6c3939355f..000000000000 --- a/include/linux/platform_data/omap_ocp2scp.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * omap_ocp2scp.h -- ocp2scp header file | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __DRIVERS_OMAP_OCP2SCP_H | ||
| 20 | #define __DRIVERS_OMAP_OCP2SCP_H | ||
| 21 | |||
| 22 | struct omap_ocp2scp_dev { | ||
| 23 | const char *drv_name; | ||
| 24 | struct resource *res; | ||
| 25 | }; | ||
| 26 | |||
| 27 | struct omap_ocp2scp_platform_data { | ||
| 28 | int dev_cnt; | ||
| 29 | struct omap_ocp2scp_dev **devices; | ||
| 30 | }; | ||
| 31 | #endif /* __DRIVERS_OMAP_OCP2SCP_H */ | ||