diff options
65 files changed, 4107 insertions, 1492 deletions
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 9dce540771fb..3c18001dfd5d 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt | |||
@@ -38,6 +38,8 @@ Optional properties: | |||
38 | - mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported | 38 | - mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported |
39 | - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported | 39 | - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported |
40 | - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported | 40 | - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported |
41 | - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported | ||
42 | - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported | ||
41 | 43 | ||
42 | *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line | 44 | *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line |
43 | polarity properties, we have to fix the meaning of the "normal" and "inverted" | 45 | polarity properties, we have to fix the meaning of the "normal" and "inverted" |
diff --git a/Documentation/devicetree/bindings/mmc/moxa,moxart-mmc.txt b/Documentation/devicetree/bindings/mmc/moxa,moxart-mmc.txt new file mode 100644 index 000000000000..b63819149f22 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/moxa,moxart-mmc.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | MOXA ART MMC Host Controller Interface | ||
2 | |||
3 | Inherits from mmc binding[1]. | ||
4 | |||
5 | [1] Documentation/devicetree/bindings/mmc/mmc.txt | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : Must be "moxa,moxart-mmc" or "faraday,ftsdc010" | ||
10 | - reg : Should contain registers location and length | ||
11 | - interrupts : Should contain the interrupt number | ||
12 | - clocks : Should contain phandle for the clock feeding the MMC controller | ||
13 | |||
14 | Optional properties: | ||
15 | |||
16 | - dmas : Should contain two DMA channels, line request number must be 5 for | ||
17 | both channels | ||
18 | - dma-names : Must be "tx", "rx" | ||
19 | |||
20 | Example: | ||
21 | |||
22 | mmc: mmc@98e00000 { | ||
23 | compatible = "moxa,moxart-mmc"; | ||
24 | reg = <0x98e00000 0x5C>; | ||
25 | interrupts = <5 0>; | ||
26 | clocks = <&clk_apb>; | ||
27 | dmas = <&dma 5>, | ||
28 | <&dma 5>; | ||
29 | dma-names = "tx", "rx"; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index 8f3f13315358..2d4a7258a10d 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | |||
@@ -69,10 +69,6 @@ Optional properties: | |||
69 | 69 | ||
70 | * supports-highspeed: Enables support for high speed cards (up to 50MHz) | 70 | * supports-highspeed: Enables support for high speed cards (up to 50MHz) |
71 | 71 | ||
72 | * caps2-mmc-hs200-1_8v: Supports mmc HS200 SDR 1.8V mode | ||
73 | |||
74 | * caps2-mmc-hs200-1_2v: Supports mmc HS200 SDR 1.2V mode | ||
75 | |||
76 | * broken-cd: as documented in mmc core bindings. | 72 | * broken-cd: as documented in mmc core bindings. |
77 | 73 | ||
78 | * vmmc-supply: The phandle to the regulator to use for vmmc. If this is | 74 | * vmmc-supply: The phandle to the regulator to use for vmmc. If this is |
@@ -103,7 +99,6 @@ board specific portions as listed below. | |||
103 | clock-freq-min-max = <400000 200000000>; | 99 | clock-freq-min-max = <400000 200000000>; |
104 | num-slots = <1>; | 100 | num-slots = <1>; |
105 | supports-highspeed; | 101 | supports-highspeed; |
106 | caps2-mmc-hs200-1_8v; | ||
107 | broken-cd; | 102 | broken-cd; |
108 | fifo-depth = <0x80>; | 103 | fifo-depth = <0x80>; |
109 | card-detect-delay = <200>; | 104 | card-detect-delay = <200>; |
diff --git a/Documentation/devicetree/bindings/mmc/usdhi6rol0.txt b/Documentation/devicetree/bindings/mmc/usdhi6rol0.txt new file mode 100644 index 000000000000..8babdaa8623b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/usdhi6rol0.txt | |||
@@ -0,0 +1,33 @@ | |||
1 | * Renesas usdhi6rol0 SD/SDIO host controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: must be | ||
6 | "renesas,usdhi6rol0" | ||
7 | - interrupts: 3 interrupts, named "card detect", "data" and "SDIO" must be | ||
8 | specified | ||
9 | - clocks: a clock binding for the IMCLK input | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - vmmc-supply: a phandle of a regulator, supplying Vcc to the card | ||
14 | - vqmmc-supply: a phandle of a regulator, supplying VccQ to the card | ||
15 | |||
16 | Additionally any standard mmc bindings from mmc.txt can be used. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | sd0: sd@ab000000 { | ||
21 | compatible = "renesas,usdhi6rol0"; | ||
22 | reg = <0xab000000 0x200>; | ||
23 | interrupts = <0 23 0x4 | ||
24 | 0 24 0x4 | ||
25 | 0 25 0x4>; | ||
26 | interrupt-names = "card detect", "data", "SDIO"; | ||
27 | bus-width = <4>; | ||
28 | max-frequency = <50000000>; | ||
29 | cap-power-off-card; | ||
30 | clocks = <&imclk>; | ||
31 | vmmc-supply = <&vcc_sd0>; | ||
32 | vqmmc-supply = <&vccq_sd0>; | ||
33 | }; | ||
diff --git a/MAINTAINERS b/MAINTAINERS index 948379508e44..b4a66b9d6b4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
@@ -5974,6 +5974,7 @@ M: Chris Ball <chris@printf.net> | |||
5974 | M: Ulf Hansson <ulf.hansson@linaro.org> | 5974 | M: Ulf Hansson <ulf.hansson@linaro.org> |
5975 | L: linux-mmc@vger.kernel.org | 5975 | L: linux-mmc@vger.kernel.org |
5976 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git | 5976 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git |
5977 | T: git git://git.linaro.org/people/ulf.hansson/mmc.git | ||
5977 | S: Maintained | 5978 | S: Maintained |
5978 | F: drivers/mmc/ | 5979 | F: drivers/mmc/ |
5979 | F: include/linux/mmc/ | 5980 | F: include/linux/mmc/ |
@@ -9103,7 +9104,7 @@ F: include/linux/toshiba.h | |||
9103 | F: include/uapi/linux/toshiba.h | 9104 | F: include/uapi/linux/toshiba.h |
9104 | 9105 | ||
9105 | TMIO MMC DRIVER | 9106 | TMIO MMC DRIVER |
9106 | M: Ian Molton <ian@mnementh.co.uk> | 9107 | M: Ian Molton <ian.molton@codethink.co.uk> |
9107 | L: linux-mmc@vger.kernel.org | 9108 | L: linux-mmc@vger.kernel.org |
9108 | S: Maintained | 9109 | S: Maintained |
9109 | F: drivers/mmc/host/tmio_mmc* | 9110 | F: drivers/mmc/host/tmio_mmc* |
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index 824644875d41..d2dbf02022bd 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c | |||
@@ -341,16 +341,17 @@ int mmc_add_card(struct mmc_card *card) | |||
341 | if (mmc_host_is_spi(card->host)) { | 341 | if (mmc_host_is_spi(card->host)) { |
342 | pr_info("%s: new %s%s%s card on SPI\n", | 342 | pr_info("%s: new %s%s%s card on SPI\n", |
343 | mmc_hostname(card->host), | 343 | mmc_hostname(card->host), |
344 | mmc_card_highspeed(card) ? "high speed " : "", | 344 | mmc_card_hs(card) ? "high speed " : "", |
345 | mmc_card_ddr_mode(card) ? "DDR " : "", | 345 | mmc_card_ddr52(card) ? "DDR " : "", |
346 | type); | 346 | type); |
347 | } else { | 347 | } else { |
348 | pr_info("%s: new %s%s%s%s%s card at address %04x\n", | 348 | pr_info("%s: new %s%s%s%s%s card at address %04x\n", |
349 | mmc_hostname(card->host), | 349 | mmc_hostname(card->host), |
350 | mmc_card_uhs(card) ? "ultra high speed " : | 350 | mmc_card_uhs(card) ? "ultra high speed " : |
351 | (mmc_card_highspeed(card) ? "high speed " : ""), | 351 | (mmc_card_hs(card) ? "high speed " : ""), |
352 | mmc_card_hs400(card) ? "HS400 " : | ||
352 | (mmc_card_hs200(card) ? "HS200 " : ""), | 353 | (mmc_card_hs200(card) ? "HS200 " : ""), |
353 | mmc_card_ddr_mode(card) ? "DDR " : "", | 354 | mmc_card_ddr52(card) ? "DDR " : "", |
354 | uhs_bus_speed_mode, type, card->rca); | 355 | uhs_bus_speed_mode, type, card->rca); |
355 | } | 356 | } |
356 | 357 | ||
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index acbc3f2aaaf9..7dc0c85fdb60 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c | |||
@@ -800,6 +800,10 @@ void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card) | |||
800 | data->timeout_ns = limit_us * 1000; | 800 | data->timeout_ns = limit_us * 1000; |
801 | data->timeout_clks = 0; | 801 | data->timeout_clks = 0; |
802 | } | 802 | } |
803 | |||
804 | /* assign limit value if invalid */ | ||
805 | if (timeout_us == 0) | ||
806 | data->timeout_ns = limit_us * 1000; | ||
803 | } | 807 | } |
804 | 808 | ||
805 | /* | 809 | /* |
@@ -1310,31 +1314,38 @@ int mmc_regulator_set_ocr(struct mmc_host *mmc, | |||
1310 | } | 1314 | } |
1311 | EXPORT_SYMBOL_GPL(mmc_regulator_set_ocr); | 1315 | EXPORT_SYMBOL_GPL(mmc_regulator_set_ocr); |
1312 | 1316 | ||
1317 | #endif /* CONFIG_REGULATOR */ | ||
1318 | |||
1313 | int mmc_regulator_get_supply(struct mmc_host *mmc) | 1319 | int mmc_regulator_get_supply(struct mmc_host *mmc) |
1314 | { | 1320 | { |
1315 | struct device *dev = mmc_dev(mmc); | 1321 | struct device *dev = mmc_dev(mmc); |
1316 | struct regulator *supply; | ||
1317 | int ret; | 1322 | int ret; |
1318 | 1323 | ||
1319 | supply = devm_regulator_get(dev, "vmmc"); | 1324 | mmc->supply.vmmc = devm_regulator_get_optional(dev, "vmmc"); |
1320 | mmc->supply.vmmc = supply; | ||
1321 | mmc->supply.vqmmc = devm_regulator_get_optional(dev, "vqmmc"); | 1325 | mmc->supply.vqmmc = devm_regulator_get_optional(dev, "vqmmc"); |
1322 | 1326 | ||
1323 | if (IS_ERR(supply)) | 1327 | if (IS_ERR(mmc->supply.vmmc)) { |
1324 | return PTR_ERR(supply); | 1328 | if (PTR_ERR(mmc->supply.vmmc) == -EPROBE_DEFER) |
1329 | return -EPROBE_DEFER; | ||
1330 | dev_info(dev, "No vmmc regulator found\n"); | ||
1331 | } else { | ||
1332 | ret = mmc_regulator_get_ocrmask(mmc->supply.vmmc); | ||
1333 | if (ret > 0) | ||
1334 | mmc->ocr_avail = ret; | ||
1335 | else | ||
1336 | dev_warn(dev, "Failed getting OCR mask: %d\n", ret); | ||
1337 | } | ||
1325 | 1338 | ||
1326 | ret = mmc_regulator_get_ocrmask(supply); | 1339 | if (IS_ERR(mmc->supply.vqmmc)) { |
1327 | if (ret > 0) | 1340 | if (PTR_ERR(mmc->supply.vqmmc) == -EPROBE_DEFER) |
1328 | mmc->ocr_avail = ret; | 1341 | return -EPROBE_DEFER; |
1329 | else | 1342 | dev_info(dev, "No vqmmc regulator found\n"); |
1330 | dev_warn(mmc_dev(mmc), "Failed getting OCR mask: %d\n", ret); | 1343 | } |
1331 | 1344 | ||
1332 | return 0; | 1345 | return 0; |
1333 | } | 1346 | } |
1334 | EXPORT_SYMBOL_GPL(mmc_regulator_get_supply); | 1347 | EXPORT_SYMBOL_GPL(mmc_regulator_get_supply); |
1335 | 1348 | ||
1336 | #endif /* CONFIG_REGULATOR */ | ||
1337 | |||
1338 | /* | 1349 | /* |
1339 | * Mask off any voltages we don't support and select | 1350 | * Mask off any voltages we don't support and select |
1340 | * the lowest voltage | 1351 | * the lowest voltage |
@@ -1533,8 +1544,13 @@ void mmc_power_up(struct mmc_host *host, u32 ocr) | |||
1533 | host->ios.timing = MMC_TIMING_LEGACY; | 1544 | host->ios.timing = MMC_TIMING_LEGACY; |
1534 | mmc_set_ios(host); | 1545 | mmc_set_ios(host); |
1535 | 1546 | ||
1536 | /* Set signal voltage to 3.3V */ | 1547 | /* Try to set signal voltage to 3.3V but fall back to 1.8v or 1.2v */ |
1537 | __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330); | 1548 | if (__mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330) == 0) |
1549 | dev_dbg(mmc_dev(host), "Initial signal voltage of 3.3v\n"); | ||
1550 | else if (__mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180) == 0) | ||
1551 | dev_dbg(mmc_dev(host), "Initial signal voltage of 1.8v\n"); | ||
1552 | else if (__mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120) == 0) | ||
1553 | dev_dbg(mmc_dev(host), "Initial signal voltage of 1.2v\n"); | ||
1538 | 1554 | ||
1539 | /* | 1555 | /* |
1540 | * This delay should be sufficient to allow the power supply | 1556 | * This delay should be sufficient to allow the power supply |
@@ -2183,7 +2199,7 @@ int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen) | |||
2183 | { | 2199 | { |
2184 | struct mmc_command cmd = {0}; | 2200 | struct mmc_command cmd = {0}; |
2185 | 2201 | ||
2186 | if (mmc_card_blockaddr(card) || mmc_card_ddr_mode(card)) | 2202 | if (mmc_card_blockaddr(card) || mmc_card_ddr52(card)) |
2187 | return 0; | 2203 | return 0; |
2188 | 2204 | ||
2189 | cmd.opcode = MMC_SET_BLOCKLEN; | 2205 | cmd.opcode = MMC_SET_BLOCKLEN; |
@@ -2263,7 +2279,6 @@ static int mmc_do_hw_reset(struct mmc_host *host, int check) | |||
2263 | } | 2279 | } |
2264 | } | 2280 | } |
2265 | 2281 | ||
2266 | host->card->state &= ~(MMC_STATE_HIGHSPEED | MMC_STATE_HIGHSPEED_DDR); | ||
2267 | if (mmc_host_is_spi(host)) { | 2282 | if (mmc_host_is_spi(host)) { |
2268 | host->ios.chip_select = MMC_CS_HIGH; | 2283 | host->ios.chip_select = MMC_CS_HIGH; |
2269 | host->ios.bus_mode = MMC_BUSMODE_PUSHPULL; | 2284 | host->ios.bus_mode = MMC_BUSMODE_PUSHPULL; |
@@ -2403,6 +2418,11 @@ void mmc_rescan(struct work_struct *work) | |||
2403 | container_of(work, struct mmc_host, detect.work); | 2418 | container_of(work, struct mmc_host, detect.work); |
2404 | int i; | 2419 | int i; |
2405 | 2420 | ||
2421 | if (host->trigger_card_event && host->ops->card_event) { | ||
2422 | host->ops->card_event(host); | ||
2423 | host->trigger_card_event = false; | ||
2424 | } | ||
2425 | |||
2406 | if (host->rescan_disable) | 2426 | if (host->rescan_disable) |
2407 | return; | 2427 | return; |
2408 | 2428 | ||
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c index 54829c0ed000..91eb16223246 100644 --- a/drivers/mmc/core/debugfs.c +++ b/drivers/mmc/core/debugfs.c | |||
@@ -135,8 +135,14 @@ static int mmc_ios_show(struct seq_file *s, void *data) | |||
135 | case MMC_TIMING_UHS_DDR50: | 135 | case MMC_TIMING_UHS_DDR50: |
136 | str = "sd uhs DDR50"; | 136 | str = "sd uhs DDR50"; |
137 | break; | 137 | break; |
138 | case MMC_TIMING_MMC_DDR52: | ||
139 | str = "mmc DDR52"; | ||
140 | break; | ||
138 | case MMC_TIMING_MMC_HS200: | 141 | case MMC_TIMING_MMC_HS200: |
139 | str = "mmc high-speed SDR200"; | 142 | str = "mmc HS200"; |
143 | break; | ||
144 | case MMC_TIMING_MMC_HS400: | ||
145 | str = "mmc HS400"; | ||
140 | break; | 146 | break; |
141 | default: | 147 | default: |
142 | str = "invalid"; | 148 | str = "invalid"; |
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index fdea825dbb24..95cceae96944 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c | |||
@@ -447,6 +447,10 @@ int mmc_of_parse(struct mmc_host *host) | |||
447 | host->caps2 |= MMC_CAP2_HS200_1_8V_SDR; | 447 | host->caps2 |= MMC_CAP2_HS200_1_8V_SDR; |
448 | if (of_find_property(np, "mmc-hs200-1_2v", &len)) | 448 | if (of_find_property(np, "mmc-hs200-1_2v", &len)) |
449 | host->caps2 |= MMC_CAP2_HS200_1_2V_SDR; | 449 | host->caps2 |= MMC_CAP2_HS200_1_2V_SDR; |
450 | if (of_find_property(np, "mmc-hs400-1_8v", &len)) | ||
451 | host->caps2 |= MMC_CAP2_HS400_1_8V | MMC_CAP2_HS200_1_8V_SDR; | ||
452 | if (of_find_property(np, "mmc-hs400-1_2v", &len)) | ||
453 | host->caps2 |= MMC_CAP2_HS400_1_2V | MMC_CAP2_HS200_1_2V_SDR; | ||
450 | 454 | ||
451 | return 0; | 455 | return 0; |
452 | 456 | ||
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 1ab5f3a0af5b..793c6f7ddb04 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c | |||
@@ -240,31 +240,62 @@ static int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd) | |||
240 | static void mmc_select_card_type(struct mmc_card *card) | 240 | static void mmc_select_card_type(struct mmc_card *card) |
241 | { | 241 | { |
242 | struct mmc_host *host = card->host; | 242 | struct mmc_host *host = card->host; |
243 | u8 card_type = card->ext_csd.raw_card_type & EXT_CSD_CARD_TYPE_MASK; | 243 | u8 card_type = card->ext_csd.raw_card_type; |
244 | u32 caps = host->caps, caps2 = host->caps2; | 244 | u32 caps = host->caps, caps2 = host->caps2; |
245 | unsigned int hs_max_dtr = 0; | 245 | unsigned int hs_max_dtr = 0, hs200_max_dtr = 0; |
246 | unsigned int avail_type = 0; | ||
246 | 247 | ||
247 | if (card_type & EXT_CSD_CARD_TYPE_26) | 248 | if (caps & MMC_CAP_MMC_HIGHSPEED && |
249 | card_type & EXT_CSD_CARD_TYPE_HS_26) { | ||
248 | hs_max_dtr = MMC_HIGH_26_MAX_DTR; | 250 | hs_max_dtr = MMC_HIGH_26_MAX_DTR; |
251 | avail_type |= EXT_CSD_CARD_TYPE_HS_26; | ||
252 | } | ||
249 | 253 | ||
250 | if (caps & MMC_CAP_MMC_HIGHSPEED && | 254 | if (caps & MMC_CAP_MMC_HIGHSPEED && |
251 | card_type & EXT_CSD_CARD_TYPE_52) | 255 | card_type & EXT_CSD_CARD_TYPE_HS_52) { |
252 | hs_max_dtr = MMC_HIGH_52_MAX_DTR; | 256 | hs_max_dtr = MMC_HIGH_52_MAX_DTR; |
257 | avail_type |= EXT_CSD_CARD_TYPE_HS_52; | ||
258 | } | ||
259 | |||
260 | if (caps & MMC_CAP_1_8V_DDR && | ||
261 | card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) { | ||
262 | hs_max_dtr = MMC_HIGH_DDR_MAX_DTR; | ||
263 | avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V; | ||
264 | } | ||
253 | 265 | ||
254 | if ((caps & MMC_CAP_1_8V_DDR && | 266 | if (caps & MMC_CAP_1_2V_DDR && |
255 | card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) || | 267 | card_type & EXT_CSD_CARD_TYPE_DDR_1_2V) { |
256 | (caps & MMC_CAP_1_2V_DDR && | ||
257 | card_type & EXT_CSD_CARD_TYPE_DDR_1_2V)) | ||
258 | hs_max_dtr = MMC_HIGH_DDR_MAX_DTR; | 268 | hs_max_dtr = MMC_HIGH_DDR_MAX_DTR; |
269 | avail_type |= EXT_CSD_CARD_TYPE_DDR_1_2V; | ||
270 | } | ||
271 | |||
272 | if (caps2 & MMC_CAP2_HS200_1_8V_SDR && | ||
273 | card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) { | ||
274 | hs200_max_dtr = MMC_HS200_MAX_DTR; | ||
275 | avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V; | ||
276 | } | ||
277 | |||
278 | if (caps2 & MMC_CAP2_HS200_1_2V_SDR && | ||
279 | card_type & EXT_CSD_CARD_TYPE_HS200_1_2V) { | ||
280 | hs200_max_dtr = MMC_HS200_MAX_DTR; | ||
281 | avail_type |= EXT_CSD_CARD_TYPE_HS200_1_2V; | ||
282 | } | ||
283 | |||
284 | if (caps2 & MMC_CAP2_HS400_1_8V && | ||
285 | card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) { | ||
286 | hs200_max_dtr = MMC_HS200_MAX_DTR; | ||
287 | avail_type |= EXT_CSD_CARD_TYPE_HS400_1_8V; | ||
288 | } | ||
259 | 289 | ||
260 | if ((caps2 & MMC_CAP2_HS200_1_8V_SDR && | 290 | if (caps2 & MMC_CAP2_HS400_1_2V && |
261 | card_type & EXT_CSD_CARD_TYPE_SDR_1_8V) || | 291 | card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) { |
262 | (caps2 & MMC_CAP2_HS200_1_2V_SDR && | 292 | hs200_max_dtr = MMC_HS200_MAX_DTR; |
263 | card_type & EXT_CSD_CARD_TYPE_SDR_1_2V)) | 293 | avail_type |= EXT_CSD_CARD_TYPE_HS400_1_2V; |
264 | hs_max_dtr = MMC_HS200_MAX_DTR; | 294 | } |
265 | 295 | ||
266 | card->ext_csd.hs_max_dtr = hs_max_dtr; | 296 | card->ext_csd.hs_max_dtr = hs_max_dtr; |
267 | card->ext_csd.card_type = card_type; | 297 | card->ext_csd.hs200_max_dtr = hs200_max_dtr; |
298 | card->mmc_avail_type = avail_type; | ||
268 | } | 299 | } |
269 | 300 | ||
270 | /* | 301 | /* |
@@ -480,6 +511,8 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 *ext_csd) | |||
480 | ext_csd[EXT_CSD_PWR_CL_DDR_52_195]; | 511 | ext_csd[EXT_CSD_PWR_CL_DDR_52_195]; |
481 | card->ext_csd.raw_pwr_cl_ddr_52_360 = | 512 | card->ext_csd.raw_pwr_cl_ddr_52_360 = |
482 | ext_csd[EXT_CSD_PWR_CL_DDR_52_360]; | 513 | ext_csd[EXT_CSD_PWR_CL_DDR_52_360]; |
514 | card->ext_csd.raw_pwr_cl_ddr_200_360 = | ||
515 | ext_csd[EXT_CSD_PWR_CL_DDR_200_360]; | ||
483 | } | 516 | } |
484 | 517 | ||
485 | if (card->ext_csd.rev >= 5) { | 518 | if (card->ext_csd.rev >= 5) { |
@@ -646,7 +679,10 @@ static int mmc_compare_ext_csds(struct mmc_card *card, unsigned bus_width) | |||
646 | (card->ext_csd.raw_pwr_cl_ddr_52_195 == | 679 | (card->ext_csd.raw_pwr_cl_ddr_52_195 == |
647 | bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_195]) && | 680 | bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_195]) && |
648 | (card->ext_csd.raw_pwr_cl_ddr_52_360 == | 681 | (card->ext_csd.raw_pwr_cl_ddr_52_360 == |
649 | bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_360])); | 682 | bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_360]) && |
683 | (card->ext_csd.raw_pwr_cl_ddr_200_360 == | ||
684 | bw_ext_csd[EXT_CSD_PWR_CL_DDR_200_360])); | ||
685 | |||
650 | if (err) | 686 | if (err) |
651 | err = -EINVAL; | 687 | err = -EINVAL; |
652 | 688 | ||
@@ -694,18 +730,10 @@ static struct attribute *mmc_std_attrs[] = { | |||
694 | &dev_attr_rel_sectors.attr, | 730 | &dev_attr_rel_sectors.attr, |
695 | NULL, | 731 | NULL, |
696 | }; | 732 | }; |
697 | 733 | ATTRIBUTE_GROUPS(mmc_std); | |
698 | static struct attribute_group mmc_std_attr_group = { | ||
699 | .attrs = mmc_std_attrs, | ||
700 | }; | ||
701 | |||
702 | static const struct attribute_group *mmc_attr_groups[] = { | ||
703 | &mmc_std_attr_group, | ||
704 | NULL, | ||
705 | }; | ||
706 | 734 | ||
707 | static struct device_type mmc_type = { | 735 | static struct device_type mmc_type = { |
708 | .groups = mmc_attr_groups, | 736 | .groups = mmc_std_groups, |
709 | }; | 737 | }; |
710 | 738 | ||
711 | /* | 739 | /* |
@@ -714,17 +742,13 @@ static struct device_type mmc_type = { | |||
714 | * extended CSD register, select it by executing the | 742 | * extended CSD register, select it by executing the |
715 | * mmc_switch command. | 743 | * mmc_switch command. |
716 | */ | 744 | */ |
717 | static int mmc_select_powerclass(struct mmc_card *card, | 745 | static int __mmc_select_powerclass(struct mmc_card *card, |
718 | unsigned int bus_width) | 746 | unsigned int bus_width) |
719 | { | 747 | { |
720 | int err = 0; | 748 | struct mmc_host *host = card->host; |
749 | struct mmc_ext_csd *ext_csd = &card->ext_csd; | ||
721 | unsigned int pwrclass_val = 0; | 750 | unsigned int pwrclass_val = 0; |
722 | struct mmc_host *host; | 751 | int err = 0; |
723 | |||
724 | BUG_ON(!card); | ||
725 | |||
726 | host = card->host; | ||
727 | BUG_ON(!host); | ||
728 | 752 | ||
729 | /* Power class selection is supported for versions >= 4.0 */ | 753 | /* Power class selection is supported for versions >= 4.0 */ |
730 | if (card->csd.mmca_vsn < CSD_SPEC_VER_4) | 754 | if (card->csd.mmca_vsn < CSD_SPEC_VER_4) |
@@ -736,14 +760,14 @@ static int mmc_select_powerclass(struct mmc_card *card, | |||
736 | 760 | ||
737 | switch (1 << host->ios.vdd) { | 761 | switch (1 << host->ios.vdd) { |
738 | case MMC_VDD_165_195: | 762 | case MMC_VDD_165_195: |
739 | if (host->ios.clock <= 26000000) | 763 | if (host->ios.clock <= MMC_HIGH_26_MAX_DTR) |
740 | pwrclass_val = card->ext_csd.raw_pwr_cl_26_195; | 764 | pwrclass_val = ext_csd->raw_pwr_cl_26_195; |
741 | else if (host->ios.clock <= 52000000) | 765 | else if (host->ios.clock <= MMC_HIGH_52_MAX_DTR) |
742 | pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? | 766 | pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? |
743 | card->ext_csd.raw_pwr_cl_52_195 : | 767 | ext_csd->raw_pwr_cl_52_195 : |
744 | card->ext_csd.raw_pwr_cl_ddr_52_195; | 768 | ext_csd->raw_pwr_cl_ddr_52_195; |
745 | else if (host->ios.clock <= 200000000) | 769 | else if (host->ios.clock <= MMC_HS200_MAX_DTR) |
746 | pwrclass_val = card->ext_csd.raw_pwr_cl_200_195; | 770 | pwrclass_val = ext_csd->raw_pwr_cl_200_195; |
747 | break; | 771 | break; |
748 | case MMC_VDD_27_28: | 772 | case MMC_VDD_27_28: |
749 | case MMC_VDD_28_29: | 773 | case MMC_VDD_28_29: |
@@ -754,14 +778,16 @@ static int mmc_select_powerclass(struct mmc_card *card, | |||
754 | case MMC_VDD_33_34: | 778 | case MMC_VDD_33_34: |
755 | case MMC_VDD_34_35: | 779 | case MMC_VDD_34_35: |
756 | case MMC_VDD_35_36: | 780 | case MMC_VDD_35_36: |
757 | if (host->ios.clock <= 26000000) | 781 | if (host->ios.clock <= MMC_HIGH_26_MAX_DTR) |
758 | pwrclass_val = card->ext_csd.raw_pwr_cl_26_360; | 782 | pwrclass_val = ext_csd->raw_pwr_cl_26_360; |
759 | else if (host->ios.clock <= 52000000) | 783 | else if (host->ios.clock <= MMC_HIGH_52_MAX_DTR) |
760 | pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? | 784 | pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? |
761 | card->ext_csd.raw_pwr_cl_52_360 : | 785 | ext_csd->raw_pwr_cl_52_360 : |
762 | card->ext_csd.raw_pwr_cl_ddr_52_360; | 786 | ext_csd->raw_pwr_cl_ddr_52_360; |
763 | else if (host->ios.clock <= 200000000) | 787 | else if (host->ios.clock <= MMC_HS200_MAX_DTR) |
764 | pwrclass_val = card->ext_csd.raw_pwr_cl_200_360; | 788 | pwrclass_val = (bus_width == EXT_CSD_DDR_BUS_WIDTH_8) ? |
789 | ext_csd->raw_pwr_cl_ddr_200_360 : | ||
790 | ext_csd->raw_pwr_cl_200_360; | ||
765 | break; | 791 | break; |
766 | default: | 792 | default: |
767 | pr_warning("%s: Voltage range not supported " | 793 | pr_warning("%s: Voltage range not supported " |
@@ -787,40 +813,79 @@ static int mmc_select_powerclass(struct mmc_card *card, | |||
787 | return err; | 813 | return err; |
788 | } | 814 | } |
789 | 815 | ||
816 | static int mmc_select_powerclass(struct mmc_card *card) | ||
817 | { | ||
818 | struct mmc_host *host = card->host; | ||
819 | u32 bus_width, ext_csd_bits; | ||
820 | int err, ddr; | ||
821 | |||
822 | /* Power class selection is supported for versions >= 4.0 */ | ||
823 | if (card->csd.mmca_vsn < CSD_SPEC_VER_4) | ||
824 | return 0; | ||
825 | |||
826 | bus_width = host->ios.bus_width; | ||
827 | /* Power class values are defined only for 4/8 bit bus */ | ||
828 | if (bus_width == MMC_BUS_WIDTH_1) | ||
829 | return 0; | ||
830 | |||
831 | ddr = card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_52; | ||
832 | if (ddr) | ||
833 | ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ? | ||
834 | EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4; | ||
835 | else | ||
836 | ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ? | ||
837 | EXT_CSD_BUS_WIDTH_8 : EXT_CSD_BUS_WIDTH_4; | ||
838 | |||
839 | err = __mmc_select_powerclass(card, ext_csd_bits); | ||
840 | if (err) | ||
841 | pr_warn("%s: power class selection to bus width %d ddr %d failed\n", | ||
842 | mmc_hostname(host), 1 << bus_width, ddr); | ||
843 | |||
844 | return err; | ||
845 | } | ||
846 | |||
790 | /* | 847 | /* |
791 | * Selects the desired buswidth and switch to the HS200 mode | 848 | * Set the bus speed for the selected speed mode. |
792 | * if bus width set without error | ||
793 | */ | 849 | */ |
794 | static int mmc_select_hs200(struct mmc_card *card) | 850 | static void mmc_set_bus_speed(struct mmc_card *card) |
851 | { | ||
852 | unsigned int max_dtr = (unsigned int)-1; | ||
853 | |||
854 | if ((mmc_card_hs200(card) || mmc_card_hs400(card)) && | ||
855 | max_dtr > card->ext_csd.hs200_max_dtr) | ||
856 | max_dtr = card->ext_csd.hs200_max_dtr; | ||
857 | else if (mmc_card_hs(card) && max_dtr > card->ext_csd.hs_max_dtr) | ||
858 | max_dtr = card->ext_csd.hs_max_dtr; | ||
859 | else if (max_dtr > card->csd.max_dtr) | ||
860 | max_dtr = card->csd.max_dtr; | ||
861 | |||
862 | mmc_set_clock(card->host, max_dtr); | ||
863 | } | ||
864 | |||
865 | /* | ||
866 | * Select the bus width amoung 4-bit and 8-bit(SDR). | ||
867 | * If the bus width is changed successfully, return the selected width value. | ||
868 | * Zero is returned instead of error value if the wide width is not supported. | ||
869 | */ | ||
870 | static int mmc_select_bus_width(struct mmc_card *card) | ||
795 | { | 871 | { |
796 | int idx, err = -EINVAL; | ||
797 | struct mmc_host *host; | ||
798 | static unsigned ext_csd_bits[] = { | 872 | static unsigned ext_csd_bits[] = { |
799 | EXT_CSD_BUS_WIDTH_4, | ||
800 | EXT_CSD_BUS_WIDTH_8, | 873 | EXT_CSD_BUS_WIDTH_8, |
874 | EXT_CSD_BUS_WIDTH_4, | ||
801 | }; | 875 | }; |
802 | static unsigned bus_widths[] = { | 876 | static unsigned bus_widths[] = { |
803 | MMC_BUS_WIDTH_4, | ||
804 | MMC_BUS_WIDTH_8, | 877 | MMC_BUS_WIDTH_8, |
878 | MMC_BUS_WIDTH_4, | ||
805 | }; | 879 | }; |
880 | struct mmc_host *host = card->host; | ||
881 | unsigned idx, bus_width = 0; | ||
882 | int err = 0; | ||
806 | 883 | ||
807 | BUG_ON(!card); | 884 | if ((card->csd.mmca_vsn < CSD_SPEC_VER_4) && |
808 | 885 | !(host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) | |
809 | host = card->host; | 886 | return 0; |
810 | |||
811 | if (card->ext_csd.card_type & EXT_CSD_CARD_TYPE_SDR_1_2V && | ||
812 | host->caps2 & MMC_CAP2_HS200_1_2V_SDR) | ||
813 | err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120); | ||
814 | |||
815 | if (err && card->ext_csd.card_type & EXT_CSD_CARD_TYPE_SDR_1_8V && | ||
816 | host->caps2 & MMC_CAP2_HS200_1_8V_SDR) | ||
817 | err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180); | ||
818 | |||
819 | /* If fails try again during next card power cycle */ | ||
820 | if (err) | ||
821 | goto err; | ||
822 | 887 | ||
823 | idx = (host->caps & MMC_CAP_8_BIT_DATA) ? 1 : 0; | 888 | idx = (host->caps & MMC_CAP_8_BIT_DATA) ? 0 : 1; |
824 | 889 | ||
825 | /* | 890 | /* |
826 | * Unlike SD, MMC cards dont have a configuration register to notify | 891 | * Unlike SD, MMC cards dont have a configuration register to notify |
@@ -828,8 +893,7 @@ static int mmc_select_hs200(struct mmc_card *card) | |||
828 | * the supported bus width or compare the ext csd values of current | 893 | * the supported bus width or compare the ext csd values of current |
829 | * bus width and ext csd values of 1 bit mode read earlier. | 894 | * bus width and ext csd values of 1 bit mode read earlier. |
830 | */ | 895 | */ |
831 | for (; idx >= 0; idx--) { | 896 | for (; idx < ARRAY_SIZE(bus_widths); idx++) { |
832 | |||
833 | /* | 897 | /* |
834 | * Host is capable of 8bit transfer, then switch | 898 | * Host is capable of 8bit transfer, then switch |
835 | * the device to work in 8bit transfer mode. If the | 899 | * the device to work in 8bit transfer mode. If the |
@@ -844,27 +908,266 @@ static int mmc_select_hs200(struct mmc_card *card) | |||
844 | if (err) | 908 | if (err) |
845 | continue; | 909 | continue; |
846 | 910 | ||
847 | mmc_set_bus_width(card->host, bus_widths[idx]); | 911 | bus_width = bus_widths[idx]; |
912 | mmc_set_bus_width(host, bus_width); | ||
848 | 913 | ||
914 | /* | ||
915 | * If controller can't handle bus width test, | ||
916 | * compare ext_csd previously read in 1 bit mode | ||
917 | * against ext_csd at new bus width | ||
918 | */ | ||
849 | if (!(host->caps & MMC_CAP_BUS_WIDTH_TEST)) | 919 | if (!(host->caps & MMC_CAP_BUS_WIDTH_TEST)) |
850 | err = mmc_compare_ext_csds(card, bus_widths[idx]); | 920 | err = mmc_compare_ext_csds(card, bus_width); |
851 | else | 921 | else |
852 | err = mmc_bus_test(card, bus_widths[idx]); | 922 | err = mmc_bus_test(card, bus_width); |
853 | if (!err) | 923 | |
924 | if (!err) { | ||
925 | err = bus_width; | ||
854 | break; | 926 | break; |
927 | } else { | ||
928 | pr_warn("%s: switch to bus width %d failed\n", | ||
929 | mmc_hostname(host), ext_csd_bits[idx]); | ||
930 | } | ||
855 | } | 931 | } |
856 | 932 | ||
857 | /* switch to HS200 mode if bus width set successfully */ | 933 | return err; |
934 | } | ||
935 | |||
936 | /* | ||
937 | * Switch to the high-speed mode | ||
938 | */ | ||
939 | static int mmc_select_hs(struct mmc_card *card) | ||
940 | { | ||
941 | int err; | ||
942 | |||
943 | err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
944 | EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, | ||
945 | card->ext_csd.generic_cmd6_time, | ||
946 | true, true, true); | ||
858 | if (!err) | 947 | if (!err) |
948 | mmc_set_timing(card->host, MMC_TIMING_MMC_HS); | ||
949 | |||
950 | return err; | ||
951 | } | ||
952 | |||
953 | /* | ||
954 | * Activate wide bus and DDR if supported. | ||
955 | */ | ||
956 | static int mmc_select_hs_ddr(struct mmc_card *card) | ||
957 | { | ||
958 | struct mmc_host *host = card->host; | ||
959 | u32 bus_width, ext_csd_bits; | ||
960 | int err = 0; | ||
961 | |||
962 | if (!(card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_52)) | ||
963 | return 0; | ||
964 | |||
965 | bus_width = host->ios.bus_width; | ||
966 | if (bus_width == MMC_BUS_WIDTH_1) | ||
967 | return 0; | ||
968 | |||
969 | ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ? | ||
970 | EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4; | ||
971 | |||
972 | err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
973 | EXT_CSD_BUS_WIDTH, | ||
974 | ext_csd_bits, | ||
975 | card->ext_csd.generic_cmd6_time); | ||
976 | if (err) { | ||
977 | pr_warn("%s: switch to bus width %d ddr failed\n", | ||
978 | mmc_hostname(host), 1 << bus_width); | ||
979 | return err; | ||
980 | } | ||
981 | |||
982 | /* | ||
983 | * eMMC cards can support 3.3V to 1.2V i/o (vccq) | ||
984 | * signaling. | ||
985 | * | ||
986 | * EXT_CSD_CARD_TYPE_DDR_1_8V means 3.3V or 1.8V vccq. | ||
987 | * | ||
988 | * 1.8V vccq at 3.3V core voltage (vcc) is not required | ||
989 | * in the JEDEC spec for DDR. | ||
990 | * | ||
991 | * Do not force change in vccq since we are obviously | ||
992 | * working and no change to vccq is needed. | ||
993 | * | ||
994 | * WARNING: eMMC rules are NOT the same as SD DDR | ||
995 | */ | ||
996 | if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_2V) { | ||
997 | err = __mmc_set_signal_voltage(host, | ||
998 | MMC_SIGNAL_VOLTAGE_120); | ||
999 | if (err) | ||
1000 | return err; | ||
1001 | } | ||
1002 | |||
1003 | mmc_set_timing(host, MMC_TIMING_MMC_DDR52); | ||
1004 | |||
1005 | return err; | ||
1006 | } | ||
1007 | |||
1008 | static int mmc_select_hs400(struct mmc_card *card) | ||
1009 | { | ||
1010 | struct mmc_host *host = card->host; | ||
1011 | int err = 0; | ||
1012 | |||
1013 | /* | ||
1014 | * HS400 mode requires 8-bit bus width | ||
1015 | */ | ||
1016 | if (!(card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 && | ||
1017 | host->ios.bus_width == MMC_BUS_WIDTH_8)) | ||
1018 | return 0; | ||
1019 | |||
1020 | /* | ||
1021 | * Before switching to dual data rate operation for HS400, | ||
1022 | * it is required to convert from HS200 mode to HS mode. | ||
1023 | */ | ||
1024 | mmc_set_timing(card->host, MMC_TIMING_MMC_HS); | ||
1025 | mmc_set_bus_speed(card); | ||
1026 | |||
1027 | err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
1028 | EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, | ||
1029 | card->ext_csd.generic_cmd6_time, | ||
1030 | true, true, true); | ||
1031 | if (err) { | ||
1032 | pr_warn("%s: switch to high-speed from hs200 failed, err:%d\n", | ||
1033 | mmc_hostname(host), err); | ||
1034 | return err; | ||
1035 | } | ||
1036 | |||
1037 | err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
1038 | EXT_CSD_BUS_WIDTH, | ||
1039 | EXT_CSD_DDR_BUS_WIDTH_8, | ||
1040 | card->ext_csd.generic_cmd6_time); | ||
1041 | if (err) { | ||
1042 | pr_warn("%s: switch to bus width for hs400 failed, err:%d\n", | ||
1043 | mmc_hostname(host), err); | ||
1044 | return err; | ||
1045 | } | ||
1046 | |||
1047 | err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
1048 | EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400, | ||
1049 | card->ext_csd.generic_cmd6_time, | ||
1050 | true, true, true); | ||
1051 | if (err) { | ||
1052 | pr_warn("%s: switch to hs400 failed, err:%d\n", | ||
1053 | mmc_hostname(host), err); | ||
1054 | return err; | ||
1055 | } | ||
1056 | |||
1057 | mmc_set_timing(host, MMC_TIMING_MMC_HS400); | ||
1058 | mmc_set_bus_speed(card); | ||
1059 | |||
1060 | return 0; | ||
1061 | } | ||
1062 | |||
1063 | /* | ||
1064 | * For device supporting HS200 mode, the following sequence | ||
1065 | * should be done before executing the tuning process. | ||
1066 | * 1. set the desired bus width(4-bit or 8-bit, 1-bit is not supported) | ||
1067 | * 2. switch to HS200 mode | ||
1068 | * 3. set the clock to > 52Mhz and <=200MHz | ||
1069 | */ | ||
1070 | static int mmc_select_hs200(struct mmc_card *card) | ||
1071 | { | ||
1072 | struct mmc_host *host = card->host; | ||
1073 | int err = -EINVAL; | ||
1074 | |||
1075 | if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_2V) | ||
1076 | err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120); | ||
1077 | |||
1078 | if (err && card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_8V) | ||
1079 | err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180); | ||
1080 | |||
1081 | /* If fails try again during next card power cycle */ | ||
1082 | if (err) | ||
1083 | goto err; | ||
1084 | |||
1085 | /* | ||
1086 | * Set the bus width(4 or 8) with host's support and | ||
1087 | * switch to HS200 mode if bus width is set successfully. | ||
1088 | */ | ||
1089 | err = mmc_select_bus_width(card); | ||
1090 | if (!IS_ERR_VALUE(err)) { | ||
859 | err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | 1091 | err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, |
860 | EXT_CSD_HS_TIMING, 2, | 1092 | EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS200, |
861 | card->ext_csd.generic_cmd6_time, | 1093 | card->ext_csd.generic_cmd6_time, |
862 | true, true, true); | 1094 | true, true, true); |
1095 | if (!err) | ||
1096 | mmc_set_timing(host, MMC_TIMING_MMC_HS200); | ||
1097 | } | ||
863 | err: | 1098 | err: |
864 | return err; | 1099 | return err; |
865 | } | 1100 | } |
866 | 1101 | ||
867 | /* | 1102 | /* |
1103 | * Activate High Speed or HS200 mode if supported. | ||
1104 | */ | ||
1105 | static int mmc_select_timing(struct mmc_card *card) | ||
1106 | { | ||
1107 | int err = 0; | ||
1108 | |||
1109 | if ((card->csd.mmca_vsn < CSD_SPEC_VER_4 && | ||
1110 | card->ext_csd.hs_max_dtr == 0)) | ||
1111 | goto bus_speed; | ||
1112 | |||
1113 | if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) | ||
1114 | err = mmc_select_hs200(card); | ||
1115 | else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS) | ||
1116 | err = mmc_select_hs(card); | ||
1117 | |||
1118 | if (err && err != -EBADMSG) | ||
1119 | return err; | ||
1120 | |||
1121 | if (err) { | ||
1122 | pr_warn("%s: switch to %s failed\n", | ||
1123 | mmc_card_hs(card) ? "high-speed" : | ||
1124 | (mmc_card_hs200(card) ? "hs200" : ""), | ||
1125 | mmc_hostname(card->host)); | ||
1126 | err = 0; | ||
1127 | } | ||
1128 | |||
1129 | bus_speed: | ||
1130 | /* | ||
1131 | * Set the bus speed to the selected bus timing. | ||
1132 | * If timing is not selected, backward compatible is the default. | ||
1133 | */ | ||
1134 | mmc_set_bus_speed(card); | ||
1135 | return err; | ||
1136 | } | ||
1137 | |||
1138 | /* | ||
1139 | * Execute tuning sequence to seek the proper bus operating | ||
1140 | * conditions for HS200 and HS400, which sends CMD21 to the device. | ||
1141 | */ | ||
1142 | static int mmc_hs200_tuning(struct mmc_card *card) | ||
1143 | { | ||
1144 | struct mmc_host *host = card->host; | ||
1145 | int err = 0; | ||
1146 | |||
1147 | /* | ||
1148 | * Timing should be adjusted to the HS400 target | ||
1149 | * operation frequency for tuning process | ||
1150 | */ | ||
1151 | if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 && | ||
1152 | host->ios.bus_width == MMC_BUS_WIDTH_8) | ||
1153 | if (host->ops->prepare_hs400_tuning) | ||
1154 | host->ops->prepare_hs400_tuning(host, &host->ios); | ||
1155 | |||
1156 | if (host->ops->execute_tuning) { | ||
1157 | mmc_host_clk_hold(host); | ||
1158 | err = host->ops->execute_tuning(host, | ||
1159 | MMC_SEND_TUNING_BLOCK_HS200); | ||
1160 | mmc_host_clk_release(host); | ||
1161 | |||
1162 | if (err) | ||
1163 | pr_warn("%s: tuning execution failed\n", | ||
1164 | mmc_hostname(host)); | ||
1165 | } | ||
1166 | |||
1167 | return err; | ||
1168 | } | ||
1169 | |||
1170 | /* | ||
868 | * Handle the detection and initialisation of a card. | 1171 | * Handle the detection and initialisation of a card. |
869 | * | 1172 | * |
870 | * In the case of a resume, "oldcard" will contain the card | 1173 | * In the case of a resume, "oldcard" will contain the card |
@@ -874,9 +1177,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, | |||
874 | struct mmc_card *oldcard) | 1177 | struct mmc_card *oldcard) |
875 | { | 1178 | { |
876 | struct mmc_card *card; | 1179 | struct mmc_card *card; |
877 | int err, ddr = 0; | 1180 | int err; |
878 | u32 cid[4]; | 1181 | u32 cid[4]; |
879 | unsigned int max_dtr; | ||
880 | u32 rocr; | 1182 | u32 rocr; |
881 | u8 *ext_csd = NULL; | 1183 | u8 *ext_csd = NULL; |
882 | 1184 | ||
@@ -1068,206 +1370,34 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, | |||
1068 | } | 1370 | } |
1069 | 1371 | ||
1070 | /* | 1372 | /* |
1071 | * Activate high speed (if supported) | 1373 | * Select timing interface |
1072 | */ | ||
1073 | if (card->ext_csd.hs_max_dtr != 0) { | ||
1074 | err = 0; | ||
1075 | if (card->ext_csd.hs_max_dtr > 52000000 && | ||
1076 | host->caps2 & MMC_CAP2_HS200) | ||
1077 | err = mmc_select_hs200(card); | ||
1078 | else if (host->caps & MMC_CAP_MMC_HIGHSPEED) | ||
1079 | err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
1080 | EXT_CSD_HS_TIMING, 1, | ||
1081 | card->ext_csd.generic_cmd6_time, | ||
1082 | true, true, true); | ||
1083 | |||
1084 | if (err && err != -EBADMSG) | ||
1085 | goto free_card; | ||
1086 | |||
1087 | if (err) { | ||
1088 | pr_warning("%s: switch to highspeed failed\n", | ||
1089 | mmc_hostname(card->host)); | ||
1090 | err = 0; | ||
1091 | } else { | ||
1092 | if (card->ext_csd.hs_max_dtr > 52000000 && | ||
1093 | host->caps2 & MMC_CAP2_HS200) { | ||
1094 | mmc_card_set_hs200(card); | ||
1095 | mmc_set_timing(card->host, | ||
1096 | MMC_TIMING_MMC_HS200); | ||
1097 | } else { | ||
1098 | mmc_card_set_highspeed(card); | ||
1099 | mmc_set_timing(card->host, MMC_TIMING_MMC_HS); | ||
1100 | } | ||
1101 | } | ||
1102 | } | ||
1103 | |||
1104 | /* | ||
1105 | * Compute bus speed. | ||
1106 | */ | ||
1107 | max_dtr = (unsigned int)-1; | ||
1108 | |||
1109 | if (mmc_card_highspeed(card) || mmc_card_hs200(card)) { | ||
1110 | if (max_dtr > card->ext_csd.hs_max_dtr) | ||
1111 | max_dtr = card->ext_csd.hs_max_dtr; | ||
1112 | if (mmc_card_highspeed(card) && (max_dtr > 52000000)) | ||
1113 | max_dtr = 52000000; | ||
1114 | } else if (max_dtr > card->csd.max_dtr) { | ||
1115 | max_dtr = card->csd.max_dtr; | ||
1116 | } | ||
1117 | |||
1118 | mmc_set_clock(host, max_dtr); | ||
1119 | |||
1120 | /* | ||
1121 | * Indicate DDR mode (if supported). | ||
1122 | */ | 1374 | */ |
1123 | if (mmc_card_highspeed(card)) { | 1375 | err = mmc_select_timing(card); |
1124 | if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) | 1376 | if (err) |
1125 | && (host->caps & MMC_CAP_1_8V_DDR)) | 1377 | goto free_card; |
1126 | ddr = MMC_1_8V_DDR_MODE; | ||
1127 | else if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_2V) | ||
1128 | && (host->caps & MMC_CAP_1_2V_DDR)) | ||
1129 | ddr = MMC_1_2V_DDR_MODE; | ||
1130 | } | ||
1131 | 1378 | ||
1132 | /* | ||
1133 | * Indicate HS200 SDR mode (if supported). | ||
1134 | */ | ||
1135 | if (mmc_card_hs200(card)) { | 1379 | if (mmc_card_hs200(card)) { |
1136 | u32 ext_csd_bits; | 1380 | err = mmc_hs200_tuning(card); |
1137 | u32 bus_width = card->host->ios.bus_width; | 1381 | if (err) |
1138 | |||
1139 | /* | ||
1140 | * For devices supporting HS200 mode, the bus width has | ||
1141 | * to be set before executing the tuning function. If | ||
1142 | * set before tuning, then device will respond with CRC | ||
1143 | * errors for responses on CMD line. So for HS200 the | ||
1144 | * sequence will be | ||
1145 | * 1. set bus width 4bit / 8 bit (1 bit not supported) | ||
1146 | * 2. switch to HS200 mode | ||
1147 | * 3. set the clock to > 52Mhz <=200MHz and | ||
1148 | * 4. execute tuning for HS200 | ||
1149 | */ | ||
1150 | if ((host->caps2 & MMC_CAP2_HS200) && | ||
1151 | card->host->ops->execute_tuning) { | ||
1152 | mmc_host_clk_hold(card->host); | ||
1153 | err = card->host->ops->execute_tuning(card->host, | ||
1154 | MMC_SEND_TUNING_BLOCK_HS200); | ||
1155 | mmc_host_clk_release(card->host); | ||
1156 | } | ||
1157 | if (err) { | ||
1158 | pr_warning("%s: tuning execution failed\n", | ||
1159 | mmc_hostname(card->host)); | ||
1160 | goto err; | 1382 | goto err; |
1161 | } | ||
1162 | 1383 | ||
1163 | ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ? | 1384 | err = mmc_select_hs400(card); |
1164 | EXT_CSD_BUS_WIDTH_8 : EXT_CSD_BUS_WIDTH_4; | ||
1165 | err = mmc_select_powerclass(card, ext_csd_bits); | ||
1166 | if (err) | 1385 | if (err) |
1167 | pr_warning("%s: power class selection to bus width %d" | 1386 | goto err; |
1168 | " failed\n", mmc_hostname(card->host), | 1387 | } else if (mmc_card_hs(card)) { |
1169 | 1 << bus_width); | 1388 | /* Select the desired bus width optionally */ |
1389 | err = mmc_select_bus_width(card); | ||
1390 | if (!IS_ERR_VALUE(err)) { | ||
1391 | err = mmc_select_hs_ddr(card); | ||
1392 | if (err) | ||
1393 | goto err; | ||
1394 | } | ||
1170 | } | 1395 | } |
1171 | 1396 | ||
1172 | /* | 1397 | /* |
1173 | * Activate wide bus and DDR (if supported). | 1398 | * Choose the power class with selected bus interface |
1174 | */ | 1399 | */ |
1175 | if (!mmc_card_hs200(card) && | 1400 | mmc_select_powerclass(card); |
1176 | (card->csd.mmca_vsn >= CSD_SPEC_VER_4) && | ||
1177 | (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) { | ||
1178 | static unsigned ext_csd_bits[][2] = { | ||
1179 | { EXT_CSD_BUS_WIDTH_8, EXT_CSD_DDR_BUS_WIDTH_8 }, | ||
1180 | { EXT_CSD_BUS_WIDTH_4, EXT_CSD_DDR_BUS_WIDTH_4 }, | ||
1181 | { EXT_CSD_BUS_WIDTH_1, EXT_CSD_BUS_WIDTH_1 }, | ||
1182 | }; | ||
1183 | static unsigned bus_widths[] = { | ||
1184 | MMC_BUS_WIDTH_8, | ||
1185 | MMC_BUS_WIDTH_4, | ||
1186 | MMC_BUS_WIDTH_1 | ||
1187 | }; | ||
1188 | unsigned idx, bus_width = 0; | ||
1189 | |||
1190 | if (host->caps & MMC_CAP_8_BIT_DATA) | ||
1191 | idx = 0; | ||
1192 | else | ||
1193 | idx = 1; | ||
1194 | for (; idx < ARRAY_SIZE(bus_widths); idx++) { | ||
1195 | bus_width = bus_widths[idx]; | ||
1196 | if (bus_width == MMC_BUS_WIDTH_1) | ||
1197 | ddr = 0; /* no DDR for 1-bit width */ | ||
1198 | err = mmc_select_powerclass(card, ext_csd_bits[idx][0]); | ||
1199 | if (err) | ||
1200 | pr_warning("%s: power class selection to " | ||
1201 | "bus width %d failed\n", | ||
1202 | mmc_hostname(card->host), | ||
1203 | 1 << bus_width); | ||
1204 | |||
1205 | err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
1206 | EXT_CSD_BUS_WIDTH, | ||
1207 | ext_csd_bits[idx][0], | ||
1208 | card->ext_csd.generic_cmd6_time); | ||
1209 | if (!err) { | ||
1210 | mmc_set_bus_width(card->host, bus_width); | ||
1211 | |||
1212 | /* | ||
1213 | * If controller can't handle bus width test, | ||
1214 | * compare ext_csd previously read in 1 bit mode | ||
1215 | * against ext_csd at new bus width | ||
1216 | */ | ||
1217 | if (!(host->caps & MMC_CAP_BUS_WIDTH_TEST)) | ||
1218 | err = mmc_compare_ext_csds(card, | ||
1219 | bus_width); | ||
1220 | else | ||
1221 | err = mmc_bus_test(card, bus_width); | ||
1222 | if (!err) | ||
1223 | break; | ||
1224 | } | ||
1225 | } | ||
1226 | |||
1227 | if (!err && ddr) { | ||
1228 | err = mmc_select_powerclass(card, ext_csd_bits[idx][1]); | ||
1229 | if (err) | ||
1230 | pr_warning("%s: power class selection to " | ||
1231 | "bus width %d ddr %d failed\n", | ||
1232 | mmc_hostname(card->host), | ||
1233 | 1 << bus_width, ddr); | ||
1234 | |||
1235 | err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, | ||
1236 | EXT_CSD_BUS_WIDTH, | ||
1237 | ext_csd_bits[idx][1], | ||
1238 | card->ext_csd.generic_cmd6_time); | ||
1239 | } | ||
1240 | if (err) { | ||
1241 | pr_warning("%s: switch to bus width %d ddr %d " | ||
1242 | "failed\n", mmc_hostname(card->host), | ||
1243 | 1 << bus_width, ddr); | ||
1244 | goto free_card; | ||
1245 | } else if (ddr) { | ||
1246 | /* | ||
1247 | * eMMC cards can support 3.3V to 1.2V i/o (vccq) | ||
1248 | * signaling. | ||
1249 | * | ||
1250 | * EXT_CSD_CARD_TYPE_DDR_1_8V means 3.3V or 1.8V vccq. | ||
1251 | * | ||
1252 | * 1.8V vccq at 3.3V core voltage (vcc) is not required | ||
1253 | * in the JEDEC spec for DDR. | ||
1254 | * | ||
1255 | * Do not force change in vccq since we are obviously | ||
1256 | * working and no change to vccq is needed. | ||
1257 | * | ||
1258 | * WARNING: eMMC rules are NOT the same as SD DDR | ||
1259 | */ | ||
1260 | if (ddr == MMC_1_2V_DDR_MODE) { | ||
1261 | err = __mmc_set_signal_voltage(host, | ||
1262 | MMC_SIGNAL_VOLTAGE_120); | ||
1263 | if (err) | ||
1264 | goto err; | ||
1265 | } | ||
1266 | mmc_card_set_ddr_mode(card); | ||
1267 | mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50); | ||
1268 | mmc_set_bus_width(card->host, bus_width); | ||
1269 | } | ||
1270 | } | ||
1271 | 1401 | ||
1272 | /* | 1402 | /* |
1273 | * Enable HPI feature (if supported) | 1403 | * Enable HPI feature (if supported) |
@@ -1507,7 +1637,6 @@ static int _mmc_suspend(struct mmc_host *host, bool is_suspend) | |||
1507 | err = mmc_sleep(host); | 1637 | err = mmc_sleep(host); |
1508 | else if (!mmc_host_is_spi(host)) | 1638 | else if (!mmc_host_is_spi(host)) |
1509 | err = mmc_deselect_cards(host); | 1639 | err = mmc_deselect_cards(host); |
1510 | host->card->state &= ~(MMC_STATE_HIGHSPEED | MMC_STATE_HIGHSPEED_200); | ||
1511 | 1640 | ||
1512 | if (!err) { | 1641 | if (!err) { |
1513 | mmc_power_off(host); | 1642 | mmc_power_off(host); |
@@ -1637,7 +1766,6 @@ static int mmc_power_restore(struct mmc_host *host) | |||
1637 | { | 1766 | { |
1638 | int ret; | 1767 | int ret; |
1639 | 1768 | ||
1640 | host->card->state &= ~(MMC_STATE_HIGHSPEED | MMC_STATE_HIGHSPEED_200); | ||
1641 | mmc_claim_host(host); | 1769 | mmc_claim_host(host); |
1642 | ret = mmc_init_card(host, host->card->ocr, host->card); | 1770 | ret = mmc_init_card(host, host->card->ocr, host->card); |
1643 | mmc_release_host(host); | 1771 | mmc_release_host(host); |
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 2dd359d2242f..0c44510bf717 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c | |||
@@ -707,18 +707,10 @@ static struct attribute *sd_std_attrs[] = { | |||
707 | &dev_attr_serial.attr, | 707 | &dev_attr_serial.attr, |
708 | NULL, | 708 | NULL, |
709 | }; | 709 | }; |
710 | 710 | ATTRIBUTE_GROUPS(sd_std); | |
711 | static struct attribute_group sd_std_attr_group = { | ||
712 | .attrs = sd_std_attrs, | ||
713 | }; | ||
714 | |||
715 | static const struct attribute_group *sd_attr_groups[] = { | ||
716 | &sd_std_attr_group, | ||
717 | NULL, | ||
718 | }; | ||
719 | 711 | ||
720 | struct device_type sd_type = { | 712 | struct device_type sd_type = { |
721 | .groups = sd_attr_groups, | 713 | .groups = sd_std_groups, |
722 | }; | 714 | }; |
723 | 715 | ||
724 | /* | 716 | /* |
@@ -895,7 +887,7 @@ unsigned mmc_sd_get_max_clock(struct mmc_card *card) | |||
895 | { | 887 | { |
896 | unsigned max_dtr = (unsigned int)-1; | 888 | unsigned max_dtr = (unsigned int)-1; |
897 | 889 | ||
898 | if (mmc_card_highspeed(card)) { | 890 | if (mmc_card_hs(card)) { |
899 | if (max_dtr > card->sw_caps.hs_max_dtr) | 891 | if (max_dtr > card->sw_caps.hs_max_dtr) |
900 | max_dtr = card->sw_caps.hs_max_dtr; | 892 | max_dtr = card->sw_caps.hs_max_dtr; |
901 | } else if (max_dtr > card->csd.max_dtr) { | 893 | } else if (max_dtr > card->csd.max_dtr) { |
@@ -905,12 +897,6 @@ unsigned mmc_sd_get_max_clock(struct mmc_card *card) | |||
905 | return max_dtr; | 897 | return max_dtr; |
906 | } | 898 | } |
907 | 899 | ||
908 | void mmc_sd_go_highspeed(struct mmc_card *card) | ||
909 | { | ||
910 | mmc_card_set_highspeed(card); | ||
911 | mmc_set_timing(card->host, MMC_TIMING_SD_HS); | ||
912 | } | ||
913 | |||
914 | /* | 900 | /* |
915 | * Handle the detection and initialisation of a card. | 901 | * Handle the detection and initialisation of a card. |
916 | * | 902 | * |
@@ -985,16 +971,13 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, | |||
985 | err = mmc_sd_init_uhs_card(card); | 971 | err = mmc_sd_init_uhs_card(card); |
986 | if (err) | 972 | if (err) |
987 | goto free_card; | 973 | goto free_card; |
988 | |||
989 | /* Card is an ultra-high-speed card */ | ||
990 | mmc_card_set_uhs(card); | ||
991 | } else { | 974 | } else { |
992 | /* | 975 | /* |
993 | * Attempt to change to high-speed (if supported) | 976 | * Attempt to change to high-speed (if supported) |
994 | */ | 977 | */ |
995 | err = mmc_sd_switch_hs(card); | 978 | err = mmc_sd_switch_hs(card); |
996 | if (err > 0) | 979 | if (err > 0) |
997 | mmc_sd_go_highspeed(card); | 980 | mmc_set_timing(card->host, MMC_TIMING_SD_HS); |
998 | else if (err) | 981 | else if (err) |
999 | goto free_card; | 982 | goto free_card; |
1000 | 983 | ||
@@ -1089,7 +1072,7 @@ static int _mmc_sd_suspend(struct mmc_host *host) | |||
1089 | 1072 | ||
1090 | if (!mmc_host_is_spi(host)) | 1073 | if (!mmc_host_is_spi(host)) |
1091 | err = mmc_deselect_cards(host); | 1074 | err = mmc_deselect_cards(host); |
1092 | host->card->state &= ~MMC_STATE_HIGHSPEED; | 1075 | |
1093 | if (!err) { | 1076 | if (!err) { |
1094 | mmc_power_off(host); | 1077 | mmc_power_off(host); |
1095 | mmc_card_set_suspended(host->card); | 1078 | mmc_card_set_suspended(host->card); |
@@ -1198,7 +1181,6 @@ static int mmc_sd_power_restore(struct mmc_host *host) | |||
1198 | { | 1181 | { |
1199 | int ret; | 1182 | int ret; |
1200 | 1183 | ||
1201 | host->card->state &= ~MMC_STATE_HIGHSPEED; | ||
1202 | mmc_claim_host(host); | 1184 | mmc_claim_host(host); |
1203 | ret = mmc_sd_init_card(host, host->card->ocr, host->card); | 1185 | ret = mmc_sd_init_card(host, host->card->ocr, host->card); |
1204 | mmc_release_host(host); | 1186 | mmc_release_host(host); |
diff --git a/drivers/mmc/core/sd.h b/drivers/mmc/core/sd.h index 4b34b24f3f76..aab824a9a7f3 100644 --- a/drivers/mmc/core/sd.h +++ b/drivers/mmc/core/sd.h | |||
@@ -12,6 +12,5 @@ int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, | |||
12 | bool reinit); | 12 | bool reinit); |
13 | unsigned mmc_sd_get_max_clock(struct mmc_card *card); | 13 | unsigned mmc_sd_get_max_clock(struct mmc_card *card); |
14 | int mmc_sd_switch_hs(struct mmc_card *card); | 14 | int mmc_sd_switch_hs(struct mmc_card *card); |
15 | void mmc_sd_go_highspeed(struct mmc_card *card); | ||
16 | 15 | ||
17 | #endif | 16 | #endif |
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 4d721c6e2af0..e636d9e99e4a 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c | |||
@@ -363,7 +363,7 @@ static unsigned mmc_sdio_get_max_clock(struct mmc_card *card) | |||
363 | { | 363 | { |
364 | unsigned max_dtr; | 364 | unsigned max_dtr; |
365 | 365 | ||
366 | if (mmc_card_highspeed(card)) { | 366 | if (mmc_card_hs(card)) { |
367 | /* | 367 | /* |
368 | * The SDIO specification doesn't mention how | 368 | * The SDIO specification doesn't mention how |
369 | * the CIS transfer speed register relates to | 369 | * the CIS transfer speed register relates to |
@@ -733,7 +733,6 @@ try_again: | |||
733 | mmc_set_clock(host, card->cis.max_dtr); | 733 | mmc_set_clock(host, card->cis.max_dtr); |
734 | 734 | ||
735 | if (card->cccr.high_speed) { | 735 | if (card->cccr.high_speed) { |
736 | mmc_card_set_highspeed(card); | ||
737 | mmc_set_timing(card->host, MMC_TIMING_SD_HS); | 736 | mmc_set_timing(card->host, MMC_TIMING_SD_HS); |
738 | } | 737 | } |
739 | 738 | ||
@@ -792,16 +791,13 @@ try_again: | |||
792 | err = mmc_sdio_init_uhs_card(card); | 791 | err = mmc_sdio_init_uhs_card(card); |
793 | if (err) | 792 | if (err) |
794 | goto remove; | 793 | goto remove; |
795 | |||
796 | /* Card is an ultra-high-speed card */ | ||
797 | mmc_card_set_uhs(card); | ||
798 | } else { | 794 | } else { |
799 | /* | 795 | /* |
800 | * Switch to high-speed (if supported). | 796 | * Switch to high-speed (if supported). |
801 | */ | 797 | */ |
802 | err = sdio_enable_hs(card); | 798 | err = sdio_enable_hs(card); |
803 | if (err > 0) | 799 | if (err > 0) |
804 | mmc_sd_go_highspeed(card); | 800 | mmc_set_timing(card->host, MMC_TIMING_SD_HS); |
805 | else if (err) | 801 | else if (err) |
806 | goto remove; | 802 | goto remove; |
807 | 803 | ||
@@ -943,40 +939,21 @@ static int mmc_sdio_pre_suspend(struct mmc_host *host) | |||
943 | */ | 939 | */ |
944 | static int mmc_sdio_suspend(struct mmc_host *host) | 940 | static int mmc_sdio_suspend(struct mmc_host *host) |
945 | { | 941 | { |
946 | int i, err = 0; | 942 | if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) { |
947 | |||
948 | for (i = 0; i < host->card->sdio_funcs; i++) { | ||
949 | struct sdio_func *func = host->card->sdio_func[i]; | ||
950 | if (func && sdio_func_present(func) && func->dev.driver) { | ||
951 | const struct dev_pm_ops *pmops = func->dev.driver->pm; | ||
952 | err = pmops->suspend(&func->dev); | ||
953 | if (err) | ||
954 | break; | ||
955 | } | ||
956 | } | ||
957 | while (err && --i >= 0) { | ||
958 | struct sdio_func *func = host->card->sdio_func[i]; | ||
959 | if (func && sdio_func_present(func) && func->dev.driver) { | ||
960 | const struct dev_pm_ops *pmops = func->dev.driver->pm; | ||
961 | pmops->resume(&func->dev); | ||
962 | } | ||
963 | } | ||
964 | |||
965 | if (!err && mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) { | ||
966 | mmc_claim_host(host); | 943 | mmc_claim_host(host); |
967 | sdio_disable_wide(host->card); | 944 | sdio_disable_wide(host->card); |
968 | mmc_release_host(host); | 945 | mmc_release_host(host); |
969 | } | 946 | } |
970 | 947 | ||
971 | if (!err && !mmc_card_keep_power(host)) | 948 | if (!mmc_card_keep_power(host)) |
972 | mmc_power_off(host); | 949 | mmc_power_off(host); |
973 | 950 | ||
974 | return err; | 951 | return 0; |
975 | } | 952 | } |
976 | 953 | ||
977 | static int mmc_sdio_resume(struct mmc_host *host) | 954 | static int mmc_sdio_resume(struct mmc_host *host) |
978 | { | 955 | { |
979 | int i, err = 0; | 956 | int err = 0; |
980 | 957 | ||
981 | BUG_ON(!host); | 958 | BUG_ON(!host); |
982 | BUG_ON(!host->card); | 959 | BUG_ON(!host->card); |
@@ -1019,24 +996,6 @@ static int mmc_sdio_resume(struct mmc_host *host) | |||
1019 | wake_up_process(host->sdio_irq_thread); | 996 | wake_up_process(host->sdio_irq_thread); |
1020 | mmc_release_host(host); | 997 | mmc_release_host(host); |
1021 | 998 | ||
1022 | /* | ||
1023 | * If the card looked to be the same as before suspending, then | ||
1024 | * we proceed to resume all card functions. If one of them returns | ||
1025 | * an error then we simply return that error to the core and the | ||
1026 | * card will be redetected as new. It is the responsibility of | ||
1027 | * the function driver to perform further tests with the extra | ||
1028 | * knowledge it has of the card to confirm the card is indeed the | ||
1029 | * same as before suspending (same MAC address for network cards, | ||
1030 | * etc.) and return an error otherwise. | ||
1031 | */ | ||
1032 | for (i = 0; !err && i < host->card->sdio_funcs; i++) { | ||
1033 | struct sdio_func *func = host->card->sdio_func[i]; | ||
1034 | if (func && sdio_func_present(func) && func->dev.driver) { | ||
1035 | const struct dev_pm_ops *pmops = func->dev.driver->pm; | ||
1036 | err = pmops->resume(&func->dev); | ||
1037 | } | ||
1038 | } | ||
1039 | |||
1040 | host->pm_flags &= ~MMC_PM_KEEP_POWER; | 999 | host->pm_flags &= ~MMC_PM_KEEP_POWER; |
1041 | return err; | 1000 | return err; |
1042 | } | 1001 | } |
diff --git a/drivers/mmc/core/sdio_bus.c b/drivers/mmc/core/sdio_bus.c index 92d1ba8e8153..4fa8fef9147f 100644 --- a/drivers/mmc/core/sdio_bus.c +++ b/drivers/mmc/core/sdio_bus.c | |||
@@ -197,20 +197,8 @@ static int sdio_bus_remove(struct device *dev) | |||
197 | 197 | ||
198 | #ifdef CONFIG_PM | 198 | #ifdef CONFIG_PM |
199 | 199 | ||
200 | #ifdef CONFIG_PM_SLEEP | ||
201 | static int pm_no_operation(struct device *dev) | ||
202 | { | ||
203 | /* | ||
204 | * Prevent the PM core from calling SDIO device drivers' suspend | ||
205 | * callback routines, which it is not supposed to do, by using this | ||
206 | * empty function as the bus type suspend callaback for SDIO. | ||
207 | */ | ||
208 | return 0; | ||
209 | } | ||
210 | #endif | ||
211 | |||
212 | static const struct dev_pm_ops sdio_bus_pm_ops = { | 200 | static const struct dev_pm_ops sdio_bus_pm_ops = { |
213 | SET_SYSTEM_SLEEP_PM_OPS(pm_no_operation, pm_no_operation) | 201 | SET_SYSTEM_SLEEP_PM_OPS(pm_generic_suspend, pm_generic_resume) |
214 | SET_RUNTIME_PM_OPS( | 202 | SET_RUNTIME_PM_OPS( |
215 | pm_generic_runtime_suspend, | 203 | pm_generic_runtime_suspend, |
216 | pm_generic_runtime_resume, | 204 | pm_generic_runtime_resume, |
diff --git a/drivers/mmc/core/sdio_irq.c b/drivers/mmc/core/sdio_irq.c index aaa90460ed23..5cc13c8d35bb 100644 --- a/drivers/mmc/core/sdio_irq.c +++ b/drivers/mmc/core/sdio_irq.c | |||
@@ -90,6 +90,15 @@ static int process_sdio_pending_irqs(struct mmc_host *host) | |||
90 | return ret; | 90 | return ret; |
91 | } | 91 | } |
92 | 92 | ||
93 | void sdio_run_irqs(struct mmc_host *host) | ||
94 | { | ||
95 | mmc_claim_host(host); | ||
96 | host->sdio_irq_pending = true; | ||
97 | process_sdio_pending_irqs(host); | ||
98 | mmc_release_host(host); | ||
99 | } | ||
100 | EXPORT_SYMBOL_GPL(sdio_run_irqs); | ||
101 | |||
93 | static int sdio_irq_thread(void *_host) | 102 | static int sdio_irq_thread(void *_host) |
94 | { | 103 | { |
95 | struct mmc_host *host = _host; | 104 | struct mmc_host *host = _host; |
@@ -189,14 +198,20 @@ static int sdio_card_irq_get(struct mmc_card *card) | |||
189 | WARN_ON(!host->claimed); | 198 | WARN_ON(!host->claimed); |
190 | 199 | ||
191 | if (!host->sdio_irqs++) { | 200 | if (!host->sdio_irqs++) { |
192 | atomic_set(&host->sdio_irq_thread_abort, 0); | 201 | if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) { |
193 | host->sdio_irq_thread = | 202 | atomic_set(&host->sdio_irq_thread_abort, 0); |
194 | kthread_run(sdio_irq_thread, host, "ksdioirqd/%s", | 203 | host->sdio_irq_thread = |
195 | mmc_hostname(host)); | 204 | kthread_run(sdio_irq_thread, host, |
196 | if (IS_ERR(host->sdio_irq_thread)) { | 205 | "ksdioirqd/%s", mmc_hostname(host)); |
197 | int err = PTR_ERR(host->sdio_irq_thread); | 206 | if (IS_ERR(host->sdio_irq_thread)) { |
198 | host->sdio_irqs--; | 207 | int err = PTR_ERR(host->sdio_irq_thread); |
199 | return err; | 208 | host->sdio_irqs--; |
209 | return err; | ||
210 | } | ||
211 | } else { | ||
212 | mmc_host_clk_hold(host); | ||
213 | host->ops->enable_sdio_irq(host, 1); | ||
214 | mmc_host_clk_release(host); | ||
200 | } | 215 | } |
201 | } | 216 | } |
202 | 217 | ||
@@ -211,8 +226,14 @@ static int sdio_card_irq_put(struct mmc_card *card) | |||
211 | BUG_ON(host->sdio_irqs < 1); | 226 | BUG_ON(host->sdio_irqs < 1); |
212 | 227 | ||
213 | if (!--host->sdio_irqs) { | 228 | if (!--host->sdio_irqs) { |
214 | atomic_set(&host->sdio_irq_thread_abort, 1); | 229 | if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) { |
215 | kthread_stop(host->sdio_irq_thread); | 230 | atomic_set(&host->sdio_irq_thread_abort, 1); |
231 | kthread_stop(host->sdio_irq_thread); | ||
232 | } else { | ||
233 | mmc_host_clk_hold(host); | ||
234 | host->ops->enable_sdio_irq(host, 0); | ||
235 | mmc_host_clk_release(host); | ||
236 | } | ||
216 | } | 237 | } |
217 | 238 | ||
218 | return 0; | 239 | return 0; |
diff --git a/drivers/mmc/core/slot-gpio.c b/drivers/mmc/core/slot-gpio.c index f7650b899e3d..5f89cb83d5f0 100644 --- a/drivers/mmc/core/slot-gpio.c +++ b/drivers/mmc/core/slot-gpio.c | |||
@@ -32,9 +32,7 @@ static irqreturn_t mmc_gpio_cd_irqt(int irq, void *dev_id) | |||
32 | /* Schedule a card detection after a debounce timeout */ | 32 | /* Schedule a card detection after a debounce timeout */ |
33 | struct mmc_host *host = dev_id; | 33 | struct mmc_host *host = dev_id; |
34 | 34 | ||
35 | if (host->ops->card_event) | 35 | host->trigger_card_event = true; |
36 | host->ops->card_event(host); | ||
37 | |||
38 | mmc_detect_change(host, msecs_to_jiffies(200)); | 36 | mmc_detect_change(host, msecs_to_jiffies(200)); |
39 | 37 | ||
40 | return IRQ_HANDLED; | 38 | return IRQ_HANDLED; |
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 779368b683d0..7fee22432e94 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig | |||
@@ -168,7 +168,7 @@ config MMC_SDHCI_ESDHC_IMX | |||
168 | 168 | ||
169 | config MMC_SDHCI_DOVE | 169 | config MMC_SDHCI_DOVE |
170 | tristate "SDHCI support on Marvell's Dove SoC" | 170 | tristate "SDHCI support on Marvell's Dove SoC" |
171 | depends on ARCH_DOVE | 171 | depends on ARCH_DOVE || MACH_DOVE |
172 | depends on MMC_SDHCI_PLTFM | 172 | depends on MMC_SDHCI_PLTFM |
173 | select MMC_SDHCI_IO_ACCESSORS | 173 | select MMC_SDHCI_IO_ACCESSORS |
174 | help | 174 | help |
@@ -283,6 +283,15 @@ config MMC_SDHCI_BCM2835 | |||
283 | 283 | ||
284 | If unsure, say N. | 284 | If unsure, say N. |
285 | 285 | ||
286 | config MMC_MOXART | ||
287 | tristate "MOXART SD/MMC Host Controller support" | ||
288 | depends on ARCH_MOXART && MMC | ||
289 | help | ||
290 | This selects support for the MOXART SD/MMC Host Controller. | ||
291 | MOXA provides one multi-functional card reader which can | ||
292 | be found on some embedded hardware such as UC-7112-LX. | ||
293 | If you have a controller with this interface, say Y here. | ||
294 | |||
286 | config MMC_OMAP | 295 | config MMC_OMAP |
287 | tristate "TI OMAP Multimedia Card Interface support" | 296 | tristate "TI OMAP Multimedia Card Interface support" |
288 | depends on ARCH_OMAP | 297 | depends on ARCH_OMAP |
@@ -688,6 +697,12 @@ config MMC_WMT | |||
688 | To compile this driver as a module, choose M here: the | 697 | To compile this driver as a module, choose M here: the |
689 | module will be called wmt-sdmmc. | 698 | module will be called wmt-sdmmc. |
690 | 699 | ||
700 | config MMC_USDHI6ROL0 | ||
701 | tristate "Renesas USDHI6ROL0 SD/SDIO Host Controller support" | ||
702 | help | ||
703 | This selects support for the Renesas USDHI6ROL0 SD/SDIO | ||
704 | Host Controller | ||
705 | |||
691 | config MMC_REALTEK_PCI | 706 | config MMC_REALTEK_PCI |
692 | tristate "Realtek PCI-E SD/MMC Card Interface Driver" | 707 | tristate "Realtek PCI-E SD/MMC Card Interface Driver" |
693 | depends on MFD_RTSX_PCI | 708 | depends on MFD_RTSX_PCI |
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 61cbc241935b..7f81ddf1dd2c 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile | |||
@@ -50,7 +50,9 @@ obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o | |||
50 | obj-$(CONFIG_MMC_VUB300) += vub300.o | 50 | obj-$(CONFIG_MMC_VUB300) += vub300.o |
51 | obj-$(CONFIG_MMC_USHC) += ushc.o | 51 | obj-$(CONFIG_MMC_USHC) += ushc.o |
52 | obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o | 52 | obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o |
53 | obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o | ||
53 | obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o | 54 | obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o |
55 | obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o | ||
54 | 56 | ||
55 | obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o | 57 | obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o |
56 | obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o | 58 | obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o |
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index 42706ea0ba85..aece7cafbb97 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c | |||
@@ -820,16 +820,9 @@ static void atmci_pdc_complete(struct atmel_mci *host) | |||
820 | 820 | ||
821 | atmci_pdc_cleanup(host); | 821 | atmci_pdc_cleanup(host); |
822 | 822 | ||
823 | /* | 823 | dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__); |
824 | * If the card was removed, data will be NULL. No point trying | 824 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
825 | * to send the stop command or waiting for NBUSY in this case. | 825 | tasklet_schedule(&host->tasklet); |
826 | */ | ||
827 | if (host->data) { | ||
828 | dev_dbg(&host->pdev->dev, | ||
829 | "(%s) set pending xfer complete\n", __func__); | ||
830 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | ||
831 | tasklet_schedule(&host->tasklet); | ||
832 | } | ||
833 | } | 826 | } |
834 | 827 | ||
835 | static void atmci_dma_cleanup(struct atmel_mci *host) | 828 | static void atmci_dma_cleanup(struct atmel_mci *host) |
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 3423c5ed50c7..0fbc53ac7eae 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c | |||
@@ -187,7 +187,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) | |||
187 | unsigned long actual; | 187 | unsigned long actual; |
188 | u8 div = priv->ciu_div + 1; | 188 | u8 div = priv->ciu_div + 1; |
189 | 189 | ||
190 | if (ios->timing == MMC_TIMING_UHS_DDR50) { | 190 | if (ios->timing == MMC_TIMING_MMC_DDR52) { |
191 | mci_writel(host, CLKSEL, priv->ddr_timing); | 191 | mci_writel(host, CLKSEL, priv->ddr_timing); |
192 | /* Should be double rate for DDR mode */ | 192 | /* Should be double rate for DDR mode */ |
193 | if (ios->bus_width == MMC_BUS_WIDTH_8) | 193 | if (ios->bus_width == MMC_BUS_WIDTH_8) |
@@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode, | |||
386 | 386 | ||
387 | /* Common capabilities of Exynos4/Exynos5 SoC */ | 387 | /* Common capabilities of Exynos4/Exynos5 SoC */ |
388 | static unsigned long exynos_dwmmc_caps[4] = { | 388 | static unsigned long exynos_dwmmc_caps[4] = { |
389 | MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | | 389 | MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, |
390 | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, | ||
391 | MMC_CAP_CMD23, | 390 | MMC_CAP_CMD23, |
392 | MMC_CAP_CMD23, | 391 | MMC_CAP_CMD23, |
393 | MMC_CAP_CMD23, | 392 | MMC_CAP_CMD23, |
@@ -426,7 +425,7 @@ static int dw_mci_exynos_probe(struct platform_device *pdev) | |||
426 | return dw_mci_pltfm_register(pdev, drv_data); | 425 | return dw_mci_pltfm_register(pdev, drv_data); |
427 | } | 426 | } |
428 | 427 | ||
429 | const struct dev_pm_ops dw_mci_exynos_pmops = { | 428 | static const struct dev_pm_ops dw_mci_exynos_pmops = { |
430 | SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume) | 429 | SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume) |
431 | .resume_noirq = dw_mci_exynos_resume_noirq, | 430 | .resume_noirq = dw_mci_exynos_resume_noirq, |
432 | .thaw_noirq = dw_mci_exynos_resume_noirq, | 431 | .thaw_noirq = dw_mci_exynos_resume_noirq, |
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index cced599d5aeb..1ac227c603b7 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c | |||
@@ -235,12 +235,6 @@ err: | |||
235 | } | 235 | } |
236 | #endif /* defined(CONFIG_DEBUG_FS) */ | 236 | #endif /* defined(CONFIG_DEBUG_FS) */ |
237 | 237 | ||
238 | static void dw_mci_set_timeout(struct dw_mci *host) | ||
239 | { | ||
240 | /* timeout (maximum) */ | ||
241 | mci_writel(host, TMOUT, 0xffffffff); | ||
242 | } | ||
243 | |||
244 | static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) | 238 | static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) |
245 | { | 239 | { |
246 | struct mmc_data *data; | 240 | struct mmc_data *data; |
@@ -257,9 +251,8 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) | |||
257 | (cmd->opcode == SD_IO_RW_DIRECT && | 251 | (cmd->opcode == SD_IO_RW_DIRECT && |
258 | ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) | 252 | ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) |
259 | cmdr |= SDMMC_CMD_STOP; | 253 | cmdr |= SDMMC_CMD_STOP; |
260 | else | 254 | else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) |
261 | if (cmd->opcode != MMC_SEND_STATUS && cmd->data) | 255 | cmdr |= SDMMC_CMD_PRV_DAT_WAIT; |
262 | cmdr |= SDMMC_CMD_PRV_DAT_WAIT; | ||
263 | 256 | ||
264 | if (cmd->flags & MMC_RSP_PRESENT) { | 257 | if (cmd->flags & MMC_RSP_PRESENT) { |
265 | /* We expect a response, so set this bit */ | 258 | /* We expect a response, so set this bit */ |
@@ -850,8 +843,6 @@ static void __dw_mci_start_request(struct dw_mci *host, | |||
850 | u32 cmdflags; | 843 | u32 cmdflags; |
851 | 844 | ||
852 | mrq = slot->mrq; | 845 | mrq = slot->mrq; |
853 | if (host->pdata->select_slot) | ||
854 | host->pdata->select_slot(slot->id); | ||
855 | 846 | ||
856 | host->cur_slot = slot; | 847 | host->cur_slot = slot; |
857 | host->mrq = mrq; | 848 | host->mrq = mrq; |
@@ -864,7 +855,7 @@ static void __dw_mci_start_request(struct dw_mci *host, | |||
864 | 855 | ||
865 | data = cmd->data; | 856 | data = cmd->data; |
866 | if (data) { | 857 | if (data) { |
867 | dw_mci_set_timeout(host); | 858 | mci_writel(host, TMOUT, 0xFFFFFFFF); |
868 | mci_writel(host, BYTCNT, data->blksz*data->blocks); | 859 | mci_writel(host, BYTCNT, data->blksz*data->blocks); |
869 | mci_writel(host, BLKSIZ, data->blksz); | 860 | mci_writel(host, BLKSIZ, data->blksz); |
870 | } | 861 | } |
@@ -962,7 +953,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
962 | regs = mci_readl(slot->host, UHS_REG); | 953 | regs = mci_readl(slot->host, UHS_REG); |
963 | 954 | ||
964 | /* DDR mode set */ | 955 | /* DDR mode set */ |
965 | if (ios->timing == MMC_TIMING_UHS_DDR50) | 956 | if (ios->timing == MMC_TIMING_MMC_DDR52) |
966 | regs |= ((0x1 << slot->id) << 16); | 957 | regs |= ((0x1 << slot->id) << 16); |
967 | else | 958 | else |
968 | regs &= ~((0x1 << slot->id) << 16); | 959 | regs &= ~((0x1 << slot->id) << 16); |
@@ -985,17 +976,11 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
985 | switch (ios->power_mode) { | 976 | switch (ios->power_mode) { |
986 | case MMC_POWER_UP: | 977 | case MMC_POWER_UP: |
987 | set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); | 978 | set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); |
988 | /* Power up slot */ | ||
989 | if (slot->host->pdata->setpower) | ||
990 | slot->host->pdata->setpower(slot->id, mmc->ocr_avail); | ||
991 | regs = mci_readl(slot->host, PWREN); | 979 | regs = mci_readl(slot->host, PWREN); |
992 | regs |= (1 << slot->id); | 980 | regs |= (1 << slot->id); |
993 | mci_writel(slot->host, PWREN, regs); | 981 | mci_writel(slot->host, PWREN, regs); |
994 | break; | 982 | break; |
995 | case MMC_POWER_OFF: | 983 | case MMC_POWER_OFF: |
996 | /* Power down slot */ | ||
997 | if (slot->host->pdata->setpower) | ||
998 | slot->host->pdata->setpower(slot->id, 0); | ||
999 | regs = mci_readl(slot->host, PWREN); | 984 | regs = mci_readl(slot->host, PWREN); |
1000 | regs &= ~(1 << slot->id); | 985 | regs &= ~(1 << slot->id); |
1001 | mci_writel(slot->host, PWREN, regs); | 986 | mci_writel(slot->host, PWREN, regs); |
@@ -1009,15 +994,13 @@ static int dw_mci_get_ro(struct mmc_host *mmc) | |||
1009 | { | 994 | { |
1010 | int read_only; | 995 | int read_only; |
1011 | struct dw_mci_slot *slot = mmc_priv(mmc); | 996 | struct dw_mci_slot *slot = mmc_priv(mmc); |
1012 | struct dw_mci_board *brd = slot->host->pdata; | 997 | int gpio_ro = mmc_gpio_get_ro(mmc); |
1013 | 998 | ||
1014 | /* Use platform get_ro function, else try on board write protect */ | 999 | /* Use platform get_ro function, else try on board write protect */ |
1015 | if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) | 1000 | if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) |
1016 | read_only = 0; | 1001 | read_only = 0; |
1017 | else if (brd->get_ro) | 1002 | else if (!IS_ERR_VALUE(gpio_ro)) |
1018 | read_only = brd->get_ro(slot->id); | 1003 | read_only = gpio_ro; |
1019 | else if (gpio_is_valid(slot->wp_gpio)) | ||
1020 | read_only = gpio_get_value(slot->wp_gpio); | ||
1021 | else | 1004 | else |
1022 | read_only = | 1005 | read_only = |
1023 | mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; | 1006 | mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; |
@@ -1039,8 +1022,6 @@ static int dw_mci_get_cd(struct mmc_host *mmc) | |||
1039 | /* Use platform get_cd function, else try onboard card detect */ | 1022 | /* Use platform get_cd function, else try onboard card detect */ |
1040 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) | 1023 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) |
1041 | present = 1; | 1024 | present = 1; |
1042 | else if (brd->get_cd) | ||
1043 | present = !brd->get_cd(slot->id); | ||
1044 | else if (!IS_ERR_VALUE(gpio_cd)) | 1025 | else if (!IS_ERR_VALUE(gpio_cd)) |
1045 | present = gpio_cd; | 1026 | present = gpio_cd; |
1046 | else | 1027 | else |
@@ -1248,7 +1229,7 @@ static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) | |||
1248 | data->error = -EIO; | 1229 | data->error = -EIO; |
1249 | } | 1230 | } |
1250 | 1231 | ||
1251 | dev_err(host->dev, "data error, status 0x%08x\n", status); | 1232 | dev_dbg(host->dev, "data error, status 0x%08x\n", status); |
1252 | 1233 | ||
1253 | /* | 1234 | /* |
1254 | * After an error, there may be data lingering | 1235 | * After an error, there may be data lingering |
@@ -2045,86 +2026,15 @@ static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) | |||
2045 | 2026 | ||
2046 | return quirks; | 2027 | return quirks; |
2047 | } | 2028 | } |
2048 | |||
2049 | /* find out bus-width for a given slot */ | ||
2050 | static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) | ||
2051 | { | ||
2052 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | ||
2053 | u32 bus_wd = 1; | ||
2054 | |||
2055 | if (!np) | ||
2056 | return 1; | ||
2057 | |||
2058 | if (of_property_read_u32(np, "bus-width", &bus_wd)) | ||
2059 | dev_err(dev, "bus-width property not found, assuming width" | ||
2060 | " as 1\n"); | ||
2061 | return bus_wd; | ||
2062 | } | ||
2063 | |||
2064 | /* find the write protect gpio for a given slot; or -1 if none specified */ | ||
2065 | static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) | ||
2066 | { | ||
2067 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | ||
2068 | int gpio; | ||
2069 | |||
2070 | if (!np) | ||
2071 | return -EINVAL; | ||
2072 | |||
2073 | gpio = of_get_named_gpio(np, "wp-gpios", 0); | ||
2074 | |||
2075 | /* Having a missing entry is valid; return silently */ | ||
2076 | if (!gpio_is_valid(gpio)) | ||
2077 | return -EINVAL; | ||
2078 | |||
2079 | if (devm_gpio_request(dev, gpio, "dw-mci-wp")) { | ||
2080 | dev_warn(dev, "gpio [%d] request failed\n", gpio); | ||
2081 | return -EINVAL; | ||
2082 | } | ||
2083 | |||
2084 | return gpio; | ||
2085 | } | ||
2086 | |||
2087 | /* find the cd gpio for a given slot */ | ||
2088 | static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot, | ||
2089 | struct mmc_host *mmc) | ||
2090 | { | ||
2091 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | ||
2092 | int gpio; | ||
2093 | |||
2094 | if (!np) | ||
2095 | return; | ||
2096 | |||
2097 | gpio = of_get_named_gpio(np, "cd-gpios", 0); | ||
2098 | |||
2099 | /* Having a missing entry is valid; return silently */ | ||
2100 | if (!gpio_is_valid(gpio)) | ||
2101 | return; | ||
2102 | |||
2103 | if (mmc_gpio_request_cd(mmc, gpio, 0)) | ||
2104 | dev_warn(dev, "gpio [%d] request failed\n", gpio); | ||
2105 | } | ||
2106 | #else /* CONFIG_OF */ | 2029 | #else /* CONFIG_OF */ |
2107 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) | 2030 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) |
2108 | { | 2031 | { |
2109 | return 0; | 2032 | return 0; |
2110 | } | 2033 | } |
2111 | static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) | ||
2112 | { | ||
2113 | return 1; | ||
2114 | } | ||
2115 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) | 2034 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) |
2116 | { | 2035 | { |
2117 | return NULL; | 2036 | return NULL; |
2118 | } | 2037 | } |
2119 | static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) | ||
2120 | { | ||
2121 | return -EINVAL; | ||
2122 | } | ||
2123 | static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot, | ||
2124 | struct mmc_host *mmc) | ||
2125 | { | ||
2126 | return; | ||
2127 | } | ||
2128 | #endif /* CONFIG_OF */ | 2038 | #endif /* CONFIG_OF */ |
2129 | 2039 | ||
2130 | static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) | 2040 | static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) |
@@ -2134,7 +2044,6 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) | |||
2134 | const struct dw_mci_drv_data *drv_data = host->drv_data; | 2044 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
2135 | int ctrl_id, ret; | 2045 | int ctrl_id, ret; |
2136 | u32 freq[2]; | 2046 | u32 freq[2]; |
2137 | u8 bus_width; | ||
2138 | 2047 | ||
2139 | mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); | 2048 | mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); |
2140 | if (!mmc) | 2049 | if (!mmc) |
@@ -2158,17 +2067,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) | |||
2158 | mmc->f_max = freq[1]; | 2067 | mmc->f_max = freq[1]; |
2159 | } | 2068 | } |
2160 | 2069 | ||
2161 | if (host->pdata->get_ocr) | 2070 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
2162 | mmc->ocr_avail = host->pdata->get_ocr(id); | ||
2163 | else | ||
2164 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | ||
2165 | |||
2166 | /* | ||
2167 | * Start with slot power disabled, it will be enabled when a card | ||
2168 | * is detected. | ||
2169 | */ | ||
2170 | if (host->pdata->setpower) | ||
2171 | host->pdata->setpower(id, 0); | ||
2172 | 2071 | ||
2173 | if (host->pdata->caps) | 2072 | if (host->pdata->caps) |
2174 | mmc->caps = host->pdata->caps; | 2073 | mmc->caps = host->pdata->caps; |
@@ -2189,19 +2088,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) | |||
2189 | if (host->pdata->caps2) | 2088 | if (host->pdata->caps2) |
2190 | mmc->caps2 = host->pdata->caps2; | 2089 | mmc->caps2 = host->pdata->caps2; |
2191 | 2090 | ||
2192 | if (host->pdata->get_bus_wd) | 2091 | mmc_of_parse(mmc); |
2193 | bus_width = host->pdata->get_bus_wd(slot->id); | ||
2194 | else if (host->dev->of_node) | ||
2195 | bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id); | ||
2196 | else | ||
2197 | bus_width = 1; | ||
2198 | |||
2199 | switch (bus_width) { | ||
2200 | case 8: | ||
2201 | mmc->caps |= MMC_CAP_8_BIT_DATA; | ||
2202 | case 4: | ||
2203 | mmc->caps |= MMC_CAP_4_BIT_DATA; | ||
2204 | } | ||
2205 | 2092 | ||
2206 | if (host->pdata->blk_settings) { | 2093 | if (host->pdata->blk_settings) { |
2207 | mmc->max_segs = host->pdata->blk_settings->max_segs; | 2094 | mmc->max_segs = host->pdata->blk_settings->max_segs; |
@@ -2226,8 +2113,10 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) | |||
2226 | #endif /* CONFIG_MMC_DW_IDMAC */ | 2113 | #endif /* CONFIG_MMC_DW_IDMAC */ |
2227 | } | 2114 | } |
2228 | 2115 | ||
2229 | slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id); | 2116 | if (dw_mci_get_cd(mmc)) |
2230 | dw_mci_of_get_cd_gpio(host->dev, slot->id, mmc); | 2117 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
2118 | else | ||
2119 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); | ||
2231 | 2120 | ||
2232 | ret = mmc_add_host(mmc); | 2121 | ret = mmc_add_host(mmc); |
2233 | if (ret) | 2122 | if (ret) |
@@ -2249,10 +2138,6 @@ err_setup_bus: | |||
2249 | 2138 | ||
2250 | static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) | 2139 | static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) |
2251 | { | 2140 | { |
2252 | /* Shutdown detect IRQ */ | ||
2253 | if (slot->host->pdata->exit) | ||
2254 | slot->host->pdata->exit(id); | ||
2255 | |||
2256 | /* Debugfs stuff is cleaned up by mmc core */ | 2141 | /* Debugfs stuff is cleaned up by mmc core */ |
2257 | mmc_remove_host(slot->mmc); | 2142 | mmc_remove_host(slot->mmc); |
2258 | slot->host->slot[id] = NULL; | 2143 | slot->host->slot[id] = NULL; |
@@ -2399,24 +2284,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |||
2399 | return ERR_PTR(ret); | 2284 | return ERR_PTR(ret); |
2400 | } | 2285 | } |
2401 | 2286 | ||
2402 | if (of_find_property(np, "keep-power-in-suspend", NULL)) | ||
2403 | pdata->pm_caps |= MMC_PM_KEEP_POWER; | ||
2404 | |||
2405 | if (of_find_property(np, "enable-sdio-wakeup", NULL)) | ||
2406 | pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; | ||
2407 | |||
2408 | if (of_find_property(np, "supports-highspeed", NULL)) | 2287 | if (of_find_property(np, "supports-highspeed", NULL)) |
2409 | pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; | 2288 | pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
2410 | 2289 | ||
2411 | if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL)) | ||
2412 | pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR; | ||
2413 | |||
2414 | if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL)) | ||
2415 | pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR; | ||
2416 | |||
2417 | if (of_get_property(np, "cd-inverted", NULL)) | ||
2418 | pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; | ||
2419 | |||
2420 | return pdata; | 2290 | return pdata; |
2421 | } | 2291 | } |
2422 | 2292 | ||
@@ -2442,9 +2312,9 @@ int dw_mci_probe(struct dw_mci *host) | |||
2442 | } | 2312 | } |
2443 | } | 2313 | } |
2444 | 2314 | ||
2445 | if (!host->pdata->select_slot && host->pdata->num_slots > 1) { | 2315 | if (host->pdata->num_slots > 1) { |
2446 | dev_err(host->dev, | 2316 | dev_err(host->dev, |
2447 | "Platform data must supply select_slot function\n"); | 2317 | "Platform data must supply num_slots.\n"); |
2448 | return -ENODEV; | 2318 | return -ENODEV; |
2449 | } | 2319 | } |
2450 | 2320 | ||
@@ -2474,12 +2344,19 @@ int dw_mci_probe(struct dw_mci *host) | |||
2474 | ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); | 2344 | ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); |
2475 | if (ret) | 2345 | if (ret) |
2476 | dev_warn(host->dev, | 2346 | dev_warn(host->dev, |
2477 | "Unable to set bus rate to %ul\n", | 2347 | "Unable to set bus rate to %uHz\n", |
2478 | host->pdata->bus_hz); | 2348 | host->pdata->bus_hz); |
2479 | } | 2349 | } |
2480 | host->bus_hz = clk_get_rate(host->ciu_clk); | 2350 | host->bus_hz = clk_get_rate(host->ciu_clk); |
2481 | } | 2351 | } |
2482 | 2352 | ||
2353 | if (!host->bus_hz) { | ||
2354 | dev_err(host->dev, | ||
2355 | "Platform data must supply bus speed\n"); | ||
2356 | ret = -ENODEV; | ||
2357 | goto err_clk_ciu; | ||
2358 | } | ||
2359 | |||
2483 | if (drv_data && drv_data->init) { | 2360 | if (drv_data && drv_data->init) { |
2484 | ret = drv_data->init(host); | 2361 | ret = drv_data->init(host); |
2485 | if (ret) { | 2362 | if (ret) { |
@@ -2516,13 +2393,6 @@ int dw_mci_probe(struct dw_mci *host) | |||
2516 | } | 2393 | } |
2517 | } | 2394 | } |
2518 | 2395 | ||
2519 | if (!host->bus_hz) { | ||
2520 | dev_err(host->dev, | ||
2521 | "Platform data must supply bus speed\n"); | ||
2522 | ret = -ENODEV; | ||
2523 | goto err_regulator; | ||
2524 | } | ||
2525 | |||
2526 | host->quirks = host->pdata->quirks; | 2396 | host->quirks = host->pdata->quirks; |
2527 | 2397 | ||
2528 | spin_lock_init(&host->lock); | 2398 | spin_lock_init(&host->lock); |
@@ -2666,8 +2536,6 @@ err_workqueue: | |||
2666 | err_dmaunmap: | 2536 | err_dmaunmap: |
2667 | if (host->use_dma && host->dma_ops->exit) | 2537 | if (host->use_dma && host->dma_ops->exit) |
2668 | host->dma_ops->exit(host); | 2538 | host->dma_ops->exit(host); |
2669 | |||
2670 | err_regulator: | ||
2671 | if (host->vmmc) | 2539 | if (host->vmmc) |
2672 | regulator_disable(host->vmmc); | 2540 | regulator_disable(host->vmmc); |
2673 | 2541 | ||
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 68349779c396..738fa241d058 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h | |||
@@ -195,7 +195,6 @@ extern int dw_mci_resume(struct dw_mci *host); | |||
195 | * @mmc: The mmc_host representing this slot. | 195 | * @mmc: The mmc_host representing this slot. |
196 | * @host: The MMC controller this slot is using. | 196 | * @host: The MMC controller this slot is using. |
197 | * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) | 197 | * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) |
198 | * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. | ||
199 | * @ctype: Card type for this slot. | 198 | * @ctype: Card type for this slot. |
200 | * @mrq: mmc_request currently being processed or waiting to be | 199 | * @mrq: mmc_request currently being processed or waiting to be |
201 | * processed, or NULL when the slot is idle. | 200 | * processed, or NULL when the slot is idle. |
@@ -214,7 +213,6 @@ struct dw_mci_slot { | |||
214 | struct dw_mci *host; | 213 | struct dw_mci *host; |
215 | 214 | ||
216 | int quirks; | 215 | int quirks; |
217 | int wp_gpio; | ||
218 | 216 | ||
219 | u32 ctype; | 217 | u32 ctype; |
220 | 218 | ||
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index de2139cf3444..537d6c7a5ae4 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c | |||
@@ -515,10 +515,13 @@ static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) | |||
515 | 515 | ||
516 | jz4740_mmc_send_command(host, req->stop); | 516 | jz4740_mmc_send_command(host, req->stop); |
517 | 517 | ||
518 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); | 518 | if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) { |
519 | if (timeout) { | 519 | timeout = jz4740_mmc_poll_irq(host, |
520 | host->state = JZ4740_MMC_STATE_DONE; | 520 | JZ_MMC_IRQ_PRG_DONE); |
521 | break; | 521 | if (timeout) { |
522 | host->state = JZ4740_MMC_STATE_DONE; | ||
523 | break; | ||
524 | } | ||
522 | } | 525 | } |
523 | case JZ4740_MMC_STATE_DONE: | 526 | case JZ4740_MMC_STATE_DONE: |
524 | break; | 527 | break; |
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index a084edd37af5..7ad463e9741c 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
@@ -301,7 +301,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |||
301 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | 301 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
302 | clk |= MCI_ST_8BIT_BUS; | 302 | clk |= MCI_ST_8BIT_BUS; |
303 | 303 | ||
304 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) | 304 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
305 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | ||
305 | clk |= MCI_ST_UX500_NEG_EDGE; | 306 | clk |= MCI_ST_UX500_NEG_EDGE; |
306 | 307 | ||
307 | mmci_write_clkreg(host, clk); | 308 | mmci_write_clkreg(host, clk); |
@@ -764,7 +765,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) | |||
764 | mmci_write_clkreg(host, clk); | 765 | mmci_write_clkreg(host, clk); |
765 | } | 766 | } |
766 | 767 | ||
767 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) | 768 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
769 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | ||
768 | datactrl |= MCI_ST_DPSM_DDRMODE; | 770 | datactrl |= MCI_ST_DPSM_DDRMODE; |
769 | 771 | ||
770 | /* | 772 | /* |
diff --git a/drivers/mmc/host/moxart-mmc.c b/drivers/mmc/host/moxart-mmc.c new file mode 100644 index 000000000000..74924a04026e --- /dev/null +++ b/drivers/mmc/host/moxart-mmc.c | |||
@@ -0,0 +1,730 @@ | |||
1 | /* | ||
2 | * MOXA ART MMC host driver. | ||
3 | * | ||
4 | * Copyright (C) 2014 Jonas Jensen | ||
5 | * | ||
6 | * Jonas Jensen <jonas.jensen@gmail.com> | ||
7 | * | ||
8 | * Based on code from | ||
9 | * Moxa Technologies Co., Ltd. <www.moxa.com> | ||
10 | * | ||
11 | * This file is licensed under the terms of the GNU General Public | ||
12 | * License version 2. This program is licensed "as is" without any | ||
13 | * warranty of any kind, whether express or implied. | ||
14 | */ | ||
15 | |||
16 | #include <linux/version.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/delay.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/blkdev.h> | ||
23 | #include <linux/dma-mapping.h> | ||
24 | #include <linux/dmaengine.h> | ||
25 | #include <linux/mmc/host.h> | ||
26 | #include <linux/mmc/sd.h> | ||
27 | #include <linux/sched.h> | ||
28 | #include <linux/io.h> | ||
29 | #include <linux/of_address.h> | ||
30 | #include <linux/of_irq.h> | ||
31 | #include <linux/clk.h> | ||
32 | #include <linux/bitops.h> | ||
33 | #include <linux/of_dma.h> | ||
34 | #include <linux/spinlock.h> | ||
35 | |||
36 | #define REG_COMMAND 0 | ||
37 | #define REG_ARGUMENT 4 | ||
38 | #define REG_RESPONSE0 8 | ||
39 | #define REG_RESPONSE1 12 | ||
40 | #define REG_RESPONSE2 16 | ||
41 | #define REG_RESPONSE3 20 | ||
42 | #define REG_RESPONSE_COMMAND 24 | ||
43 | #define REG_DATA_CONTROL 28 | ||
44 | #define REG_DATA_TIMER 32 | ||
45 | #define REG_DATA_LENGTH 36 | ||
46 | #define REG_STATUS 40 | ||
47 | #define REG_CLEAR 44 | ||
48 | #define REG_INTERRUPT_MASK 48 | ||
49 | #define REG_POWER_CONTROL 52 | ||
50 | #define REG_CLOCK_CONTROL 56 | ||
51 | #define REG_BUS_WIDTH 60 | ||
52 | #define REG_DATA_WINDOW 64 | ||
53 | #define REG_FEATURE 68 | ||
54 | #define REG_REVISION 72 | ||
55 | |||
56 | /* REG_COMMAND */ | ||
57 | #define CMD_SDC_RESET BIT(10) | ||
58 | #define CMD_EN BIT(9) | ||
59 | #define CMD_APP_CMD BIT(8) | ||
60 | #define CMD_LONG_RSP BIT(7) | ||
61 | #define CMD_NEED_RSP BIT(6) | ||
62 | #define CMD_IDX_MASK 0x3f | ||
63 | |||
64 | /* REG_RESPONSE_COMMAND */ | ||
65 | #define RSP_CMD_APP BIT(6) | ||
66 | #define RSP_CMD_IDX_MASK 0x3f | ||
67 | |||
68 | /* REG_DATA_CONTROL */ | ||
69 | #define DCR_DATA_FIFO_RESET BIT(8) | ||
70 | #define DCR_DATA_THRES BIT(7) | ||
71 | #define DCR_DATA_EN BIT(6) | ||
72 | #define DCR_DMA_EN BIT(5) | ||
73 | #define DCR_DATA_WRITE BIT(4) | ||
74 | #define DCR_BLK_SIZE 0x0f | ||
75 | |||
76 | /* REG_DATA_LENGTH */ | ||
77 | #define DATA_LEN_MASK 0xffffff | ||
78 | |||
79 | /* REG_STATUS */ | ||
80 | #define WRITE_PROT BIT(12) | ||
81 | #define CARD_DETECT BIT(11) | ||
82 | /* 1-10 below can be sent to either registers, interrupt or clear. */ | ||
83 | #define CARD_CHANGE BIT(10) | ||
84 | #define FIFO_ORUN BIT(9) | ||
85 | #define FIFO_URUN BIT(8) | ||
86 | #define DATA_END BIT(7) | ||
87 | #define CMD_SENT BIT(6) | ||
88 | #define DATA_CRC_OK BIT(5) | ||
89 | #define RSP_CRC_OK BIT(4) | ||
90 | #define DATA_TIMEOUT BIT(3) | ||
91 | #define RSP_TIMEOUT BIT(2) | ||
92 | #define DATA_CRC_FAIL BIT(1) | ||
93 | #define RSP_CRC_FAIL BIT(0) | ||
94 | |||
95 | #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \ | ||
96 | RSP_CRC_OK | CARD_DETECT | CMD_SENT) | ||
97 | |||
98 | #define MASK_DATA (DATA_CRC_OK | DATA_END | \ | ||
99 | DATA_CRC_FAIL | DATA_TIMEOUT) | ||
100 | |||
101 | #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE) | ||
102 | |||
103 | /* REG_POWER_CONTROL */ | ||
104 | #define SD_POWER_ON BIT(4) | ||
105 | #define SD_POWER_MASK 0x0f | ||
106 | |||
107 | /* REG_CLOCK_CONTROL */ | ||
108 | #define CLK_HISPD BIT(9) | ||
109 | #define CLK_OFF BIT(8) | ||
110 | #define CLK_SD BIT(7) | ||
111 | #define CLK_DIV_MASK 0x7f | ||
112 | |||
113 | /* REG_BUS_WIDTH */ | ||
114 | #define BUS_WIDTH_8 BIT(2) | ||
115 | #define BUS_WIDTH_4 BIT(1) | ||
116 | #define BUS_WIDTH_1 BIT(0) | ||
117 | |||
118 | #define MMC_VDD_360 23 | ||
119 | #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK) | ||
120 | #define MAX_RETRIES 500000 | ||
121 | |||
122 | struct moxart_host { | ||
123 | spinlock_t lock; | ||
124 | |||
125 | void __iomem *base; | ||
126 | |||
127 | phys_addr_t reg_phys; | ||
128 | |||
129 | struct dma_chan *dma_chan_tx; | ||
130 | struct dma_chan *dma_chan_rx; | ||
131 | struct dma_async_tx_descriptor *tx_desc; | ||
132 | struct mmc_host *mmc; | ||
133 | struct mmc_request *mrq; | ||
134 | struct scatterlist *cur_sg; | ||
135 | struct completion dma_complete; | ||
136 | struct completion pio_complete; | ||
137 | |||
138 | u32 num_sg; | ||
139 | u32 data_remain; | ||
140 | u32 data_len; | ||
141 | u32 fifo_width; | ||
142 | u32 timeout; | ||
143 | u32 rate; | ||
144 | |||
145 | long sysclk; | ||
146 | |||
147 | bool have_dma; | ||
148 | bool is_removed; | ||
149 | }; | ||
150 | |||
151 | static inline void moxart_init_sg(struct moxart_host *host, | ||
152 | struct mmc_data *data) | ||
153 | { | ||
154 | host->cur_sg = data->sg; | ||
155 | host->num_sg = data->sg_len; | ||
156 | host->data_remain = host->cur_sg->length; | ||
157 | |||
158 | if (host->data_remain > host->data_len) | ||
159 | host->data_remain = host->data_len; | ||
160 | } | ||
161 | |||
162 | static inline int moxart_next_sg(struct moxart_host *host) | ||
163 | { | ||
164 | int remain; | ||
165 | struct mmc_data *data = host->mrq->cmd->data; | ||
166 | |||
167 | host->cur_sg++; | ||
168 | host->num_sg--; | ||
169 | |||
170 | if (host->num_sg > 0) { | ||
171 | host->data_remain = host->cur_sg->length; | ||
172 | remain = host->data_len - data->bytes_xfered; | ||
173 | if (remain > 0 && remain < host->data_remain) | ||
174 | host->data_remain = remain; | ||
175 | } | ||
176 | |||
177 | return host->num_sg; | ||
178 | } | ||
179 | |||
180 | static int moxart_wait_for_status(struct moxart_host *host, | ||
181 | u32 mask, u32 *status) | ||
182 | { | ||
183 | int ret = -ETIMEDOUT; | ||
184 | u32 i; | ||
185 | |||
186 | for (i = 0; i < MAX_RETRIES; i++) { | ||
187 | *status = readl(host->base + REG_STATUS); | ||
188 | if (!(*status & mask)) { | ||
189 | udelay(5); | ||
190 | continue; | ||
191 | } | ||
192 | writel(*status & mask, host->base + REG_CLEAR); | ||
193 | ret = 0; | ||
194 | break; | ||
195 | } | ||
196 | |||
197 | if (ret) | ||
198 | dev_err(mmc_dev(host->mmc), "timed out waiting for status\n"); | ||
199 | |||
200 | return ret; | ||
201 | } | ||
202 | |||
203 | |||
204 | static void moxart_send_command(struct moxart_host *host, | ||
205 | struct mmc_command *cmd) | ||
206 | { | ||
207 | u32 status, cmdctrl; | ||
208 | |||
209 | writel(RSP_TIMEOUT | RSP_CRC_OK | | ||
210 | RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR); | ||
211 | writel(cmd->arg, host->base + REG_ARGUMENT); | ||
212 | |||
213 | cmdctrl = cmd->opcode & CMD_IDX_MASK; | ||
214 | if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND || | ||
215 | cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS || | ||
216 | cmdctrl == SD_APP_SEND_NUM_WR_BLKS) | ||
217 | cmdctrl |= CMD_APP_CMD; | ||
218 | |||
219 | if (cmd->flags & MMC_RSP_PRESENT) | ||
220 | cmdctrl |= CMD_NEED_RSP; | ||
221 | |||
222 | if (cmd->flags & MMC_RSP_136) | ||
223 | cmdctrl |= CMD_LONG_RSP; | ||
224 | |||
225 | writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); | ||
226 | |||
227 | if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT) | ||
228 | cmd->error = -ETIMEDOUT; | ||
229 | |||
230 | if (status & RSP_TIMEOUT) { | ||
231 | cmd->error = -ETIMEDOUT; | ||
232 | return; | ||
233 | } | ||
234 | if (status & RSP_CRC_FAIL) { | ||
235 | cmd->error = -EIO; | ||
236 | return; | ||
237 | } | ||
238 | if (status & RSP_CRC_OK) { | ||
239 | if (cmd->flags & MMC_RSP_136) { | ||
240 | cmd->resp[3] = readl(host->base + REG_RESPONSE0); | ||
241 | cmd->resp[2] = readl(host->base + REG_RESPONSE1); | ||
242 | cmd->resp[1] = readl(host->base + REG_RESPONSE2); | ||
243 | cmd->resp[0] = readl(host->base + REG_RESPONSE3); | ||
244 | } else { | ||
245 | cmd->resp[0] = readl(host->base + REG_RESPONSE0); | ||
246 | } | ||
247 | } | ||
248 | } | ||
249 | |||
250 | static void moxart_dma_complete(void *param) | ||
251 | { | ||
252 | struct moxart_host *host = param; | ||
253 | |||
254 | complete(&host->dma_complete); | ||
255 | } | ||
256 | |||
257 | static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host) | ||
258 | { | ||
259 | u32 len, dir_data, dir_slave; | ||
260 | unsigned long dma_time; | ||
261 | struct dma_async_tx_descriptor *desc = NULL; | ||
262 | struct dma_chan *dma_chan; | ||
263 | |||
264 | if (host->data_len == data->bytes_xfered) | ||
265 | return; | ||
266 | |||
267 | if (data->flags & MMC_DATA_WRITE) { | ||
268 | dma_chan = host->dma_chan_tx; | ||
269 | dir_data = DMA_TO_DEVICE; | ||
270 | dir_slave = DMA_MEM_TO_DEV; | ||
271 | } else { | ||
272 | dma_chan = host->dma_chan_rx; | ||
273 | dir_data = DMA_FROM_DEVICE; | ||
274 | dir_slave = DMA_DEV_TO_MEM; | ||
275 | } | ||
276 | |||
277 | len = dma_map_sg(dma_chan->device->dev, data->sg, | ||
278 | data->sg_len, dir_data); | ||
279 | |||
280 | if (len > 0) { | ||
281 | desc = dmaengine_prep_slave_sg(dma_chan, data->sg, | ||
282 | len, dir_slave, | ||
283 | DMA_PREP_INTERRUPT | | ||
284 | DMA_CTRL_ACK); | ||
285 | } else { | ||
286 | dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); | ||
287 | } | ||
288 | |||
289 | if (desc) { | ||
290 | host->tx_desc = desc; | ||
291 | desc->callback = moxart_dma_complete; | ||
292 | desc->callback_param = host; | ||
293 | dmaengine_submit(desc); | ||
294 | dma_async_issue_pending(dma_chan); | ||
295 | } | ||
296 | |||
297 | data->bytes_xfered += host->data_remain; | ||
298 | |||
299 | dma_time = wait_for_completion_interruptible_timeout( | ||
300 | &host->dma_complete, host->timeout); | ||
301 | |||
302 | dma_unmap_sg(dma_chan->device->dev, | ||
303 | data->sg, data->sg_len, | ||
304 | dir_data); | ||
305 | } | ||
306 | |||
307 | |||
308 | static void moxart_transfer_pio(struct moxart_host *host) | ||
309 | { | ||
310 | struct mmc_data *data = host->mrq->cmd->data; | ||
311 | u32 *sgp, len = 0, remain, status; | ||
312 | |||
313 | if (host->data_len == data->bytes_xfered) | ||
314 | return; | ||
315 | |||
316 | sgp = sg_virt(host->cur_sg); | ||
317 | remain = host->data_remain; | ||
318 | |||
319 | if (data->flags & MMC_DATA_WRITE) { | ||
320 | while (remain > 0) { | ||
321 | if (moxart_wait_for_status(host, FIFO_URUN, &status) | ||
322 | == -ETIMEDOUT) { | ||
323 | data->error = -ETIMEDOUT; | ||
324 | complete(&host->pio_complete); | ||
325 | return; | ||
326 | } | ||
327 | for (len = 0; len < remain && len < host->fifo_width;) { | ||
328 | iowrite32(*sgp, host->base + REG_DATA_WINDOW); | ||
329 | sgp++; | ||
330 | len += 4; | ||
331 | } | ||
332 | remain -= len; | ||
333 | } | ||
334 | |||
335 | } else { | ||
336 | while (remain > 0) { | ||
337 | if (moxart_wait_for_status(host, FIFO_ORUN, &status) | ||
338 | == -ETIMEDOUT) { | ||
339 | data->error = -ETIMEDOUT; | ||
340 | complete(&host->pio_complete); | ||
341 | return; | ||
342 | } | ||
343 | for (len = 0; len < remain && len < host->fifo_width;) { | ||
344 | /* SCR data must be read in big endian. */ | ||
345 | if (data->mrq->cmd->opcode == SD_APP_SEND_SCR) | ||
346 | *sgp = ioread32be(host->base + | ||
347 | REG_DATA_WINDOW); | ||
348 | else | ||
349 | *sgp = ioread32(host->base + | ||
350 | REG_DATA_WINDOW); | ||
351 | sgp++; | ||
352 | len += 4; | ||
353 | } | ||
354 | remain -= len; | ||
355 | } | ||
356 | } | ||
357 | |||
358 | data->bytes_xfered += host->data_remain - remain; | ||
359 | host->data_remain = remain; | ||
360 | |||
361 | if (host->data_len != data->bytes_xfered) | ||
362 | moxart_next_sg(host); | ||
363 | else | ||
364 | complete(&host->pio_complete); | ||
365 | } | ||
366 | |||
367 | static void moxart_prepare_data(struct moxart_host *host) | ||
368 | { | ||
369 | struct mmc_data *data = host->mrq->cmd->data; | ||
370 | u32 datactrl; | ||
371 | int blksz_bits; | ||
372 | |||
373 | if (!data) | ||
374 | return; | ||
375 | |||
376 | host->data_len = data->blocks * data->blksz; | ||
377 | blksz_bits = ffs(data->blksz) - 1; | ||
378 | BUG_ON(1 << blksz_bits != data->blksz); | ||
379 | |||
380 | moxart_init_sg(host, data); | ||
381 | |||
382 | datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE); | ||
383 | |||
384 | if (data->flags & MMC_DATA_WRITE) | ||
385 | datactrl |= DCR_DATA_WRITE; | ||
386 | |||
387 | if ((host->data_len > host->fifo_width) && host->have_dma) | ||
388 | datactrl |= DCR_DMA_EN; | ||
389 | |||
390 | writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); | ||
391 | writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); | ||
392 | writel(host->rate, host->base + REG_DATA_TIMER); | ||
393 | writel(host->data_len, host->base + REG_DATA_LENGTH); | ||
394 | writel(datactrl, host->base + REG_DATA_CONTROL); | ||
395 | } | ||
396 | |||
397 | static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq) | ||
398 | { | ||
399 | struct moxart_host *host = mmc_priv(mmc); | ||
400 | unsigned long pio_time, flags; | ||
401 | u32 status; | ||
402 | |||
403 | spin_lock_irqsave(&host->lock, flags); | ||
404 | |||
405 | init_completion(&host->dma_complete); | ||
406 | init_completion(&host->pio_complete); | ||
407 | |||
408 | host->mrq = mrq; | ||
409 | |||
410 | if (readl(host->base + REG_STATUS) & CARD_DETECT) { | ||
411 | mrq->cmd->error = -ETIMEDOUT; | ||
412 | goto request_done; | ||
413 | } | ||
414 | |||
415 | moxart_prepare_data(host); | ||
416 | moxart_send_command(host, host->mrq->cmd); | ||
417 | |||
418 | if (mrq->cmd->data) { | ||
419 | if ((host->data_len > host->fifo_width) && host->have_dma) { | ||
420 | |||
421 | writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); | ||
422 | |||
423 | spin_unlock_irqrestore(&host->lock, flags); | ||
424 | |||
425 | moxart_transfer_dma(mrq->cmd->data, host); | ||
426 | |||
427 | spin_lock_irqsave(&host->lock, flags); | ||
428 | } else { | ||
429 | |||
430 | writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK); | ||
431 | |||
432 | spin_unlock_irqrestore(&host->lock, flags); | ||
433 | |||
434 | /* PIO transfers start from interrupt. */ | ||
435 | pio_time = wait_for_completion_interruptible_timeout( | ||
436 | &host->pio_complete, host->timeout); | ||
437 | |||
438 | spin_lock_irqsave(&host->lock, flags); | ||
439 | } | ||
440 | |||
441 | if (host->is_removed) { | ||
442 | dev_err(mmc_dev(host->mmc), "card removed\n"); | ||
443 | mrq->cmd->error = -ETIMEDOUT; | ||
444 | goto request_done; | ||
445 | } | ||
446 | |||
447 | if (moxart_wait_for_status(host, MASK_DATA, &status) | ||
448 | == -ETIMEDOUT) { | ||
449 | mrq->cmd->data->error = -ETIMEDOUT; | ||
450 | goto request_done; | ||
451 | } | ||
452 | |||
453 | if (status & DATA_CRC_FAIL) | ||
454 | mrq->cmd->data->error = -ETIMEDOUT; | ||
455 | |||
456 | if (mrq->cmd->data->stop) | ||
457 | moxart_send_command(host, mrq->cmd->data->stop); | ||
458 | } | ||
459 | |||
460 | request_done: | ||
461 | spin_unlock_irqrestore(&host->lock, flags); | ||
462 | mmc_request_done(host->mmc, mrq); | ||
463 | } | ||
464 | |||
465 | static irqreturn_t moxart_irq(int irq, void *devid) | ||
466 | { | ||
467 | struct moxart_host *host = (struct moxart_host *)devid; | ||
468 | u32 status; | ||
469 | unsigned long flags; | ||
470 | |||
471 | spin_lock_irqsave(&host->lock, flags); | ||
472 | |||
473 | status = readl(host->base + REG_STATUS); | ||
474 | if (status & CARD_CHANGE) { | ||
475 | host->is_removed = status & CARD_DETECT; | ||
476 | if (host->is_removed && host->have_dma) { | ||
477 | dmaengine_terminate_all(host->dma_chan_tx); | ||
478 | dmaengine_terminate_all(host->dma_chan_rx); | ||
479 | } | ||
480 | host->mrq = NULL; | ||
481 | writel(MASK_INTR_PIO, host->base + REG_CLEAR); | ||
482 | writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); | ||
483 | mmc_detect_change(host->mmc, 0); | ||
484 | } | ||
485 | if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq) | ||
486 | moxart_transfer_pio(host); | ||
487 | |||
488 | spin_unlock_irqrestore(&host->lock, flags); | ||
489 | |||
490 | return IRQ_HANDLED; | ||
491 | } | ||
492 | |||
493 | static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | ||
494 | { | ||
495 | struct moxart_host *host = mmc_priv(mmc); | ||
496 | unsigned long flags; | ||
497 | u8 power, div; | ||
498 | u32 ctrl; | ||
499 | |||
500 | spin_lock_irqsave(&host->lock, flags); | ||
501 | |||
502 | if (ios->clock) { | ||
503 | for (div = 0; div < CLK_DIV_MASK; ++div) { | ||
504 | if (ios->clock >= host->sysclk / (2 * (div + 1))) | ||
505 | break; | ||
506 | } | ||
507 | ctrl = CLK_SD | div; | ||
508 | host->rate = host->sysclk / (2 * (div + 1)); | ||
509 | if (host->rate > host->sysclk) | ||
510 | ctrl |= CLK_HISPD; | ||
511 | writel(ctrl, host->base + REG_CLOCK_CONTROL); | ||
512 | } | ||
513 | |||
514 | if (ios->power_mode == MMC_POWER_OFF) { | ||
515 | writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, | ||
516 | host->base + REG_POWER_CONTROL); | ||
517 | } else { | ||
518 | if (ios->vdd < MIN_POWER) | ||
519 | power = 0; | ||
520 | else | ||
521 | power = ios->vdd - MIN_POWER; | ||
522 | |||
523 | writel(SD_POWER_ON | (u32) power, | ||
524 | host->base + REG_POWER_CONTROL); | ||
525 | } | ||
526 | |||
527 | switch (ios->bus_width) { | ||
528 | case MMC_BUS_WIDTH_4: | ||
529 | writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH); | ||
530 | break; | ||
531 | case MMC_BUS_WIDTH_8: | ||
532 | writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH); | ||
533 | break; | ||
534 | default: | ||
535 | writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH); | ||
536 | break; | ||
537 | } | ||
538 | |||
539 | spin_unlock_irqrestore(&host->lock, flags); | ||
540 | } | ||
541 | |||
542 | |||
543 | static int moxart_get_ro(struct mmc_host *mmc) | ||
544 | { | ||
545 | struct moxart_host *host = mmc_priv(mmc); | ||
546 | |||
547 | return !!(readl(host->base + REG_STATUS) & WRITE_PROT); | ||
548 | } | ||
549 | |||
550 | static struct mmc_host_ops moxart_ops = { | ||
551 | .request = moxart_request, | ||
552 | .set_ios = moxart_set_ios, | ||
553 | .get_ro = moxart_get_ro, | ||
554 | }; | ||
555 | |||
556 | static int moxart_probe(struct platform_device *pdev) | ||
557 | { | ||
558 | struct device *dev = &pdev->dev; | ||
559 | struct device_node *node = dev->of_node; | ||
560 | struct resource res_mmc; | ||
561 | struct mmc_host *mmc; | ||
562 | struct moxart_host *host = NULL; | ||
563 | struct dma_slave_config cfg; | ||
564 | struct clk *clk; | ||
565 | void __iomem *reg_mmc; | ||
566 | dma_cap_mask_t mask; | ||
567 | int irq, ret; | ||
568 | u32 i; | ||
569 | |||
570 | mmc = mmc_alloc_host(sizeof(struct moxart_host), dev); | ||
571 | if (!mmc) { | ||
572 | dev_err(dev, "mmc_alloc_host failed\n"); | ||
573 | ret = -ENOMEM; | ||
574 | goto out; | ||
575 | } | ||
576 | |||
577 | ret = of_address_to_resource(node, 0, &res_mmc); | ||
578 | if (ret) { | ||
579 | dev_err(dev, "of_address_to_resource failed\n"); | ||
580 | goto out; | ||
581 | } | ||
582 | |||
583 | irq = irq_of_parse_and_map(node, 0); | ||
584 | if (irq <= 0) { | ||
585 | dev_err(dev, "irq_of_parse_and_map failed\n"); | ||
586 | ret = -EINVAL; | ||
587 | goto out; | ||
588 | } | ||
589 | |||
590 | clk = of_clk_get(node, 0); | ||
591 | if (IS_ERR(clk)) { | ||
592 | dev_err(dev, "of_clk_get failed\n"); | ||
593 | ret = PTR_ERR(clk); | ||
594 | goto out; | ||
595 | } | ||
596 | |||
597 | reg_mmc = devm_ioremap_resource(dev, &res_mmc); | ||
598 | if (IS_ERR(reg_mmc)) { | ||
599 | ret = PTR_ERR(reg_mmc); | ||
600 | goto out; | ||
601 | } | ||
602 | |||
603 | mmc_of_parse(mmc); | ||
604 | |||
605 | dma_cap_zero(mask); | ||
606 | dma_cap_set(DMA_SLAVE, mask); | ||
607 | |||
608 | host = mmc_priv(mmc); | ||
609 | host->mmc = mmc; | ||
610 | host->base = reg_mmc; | ||
611 | host->reg_phys = res_mmc.start; | ||
612 | host->timeout = msecs_to_jiffies(1000); | ||
613 | host->sysclk = clk_get_rate(clk); | ||
614 | host->fifo_width = readl(host->base + REG_FEATURE) << 2; | ||
615 | host->dma_chan_tx = of_dma_request_slave_channel(node, "tx"); | ||
616 | host->dma_chan_rx = of_dma_request_slave_channel(node, "rx"); | ||
617 | |||
618 | spin_lock_init(&host->lock); | ||
619 | |||
620 | mmc->ops = &moxart_ops; | ||
621 | mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2); | ||
622 | mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2); | ||
623 | mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */ | ||
624 | |||
625 | if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) { | ||
626 | dev_dbg(dev, "PIO mode transfer enabled\n"); | ||
627 | host->have_dma = false; | ||
628 | } else { | ||
629 | dev_dbg(dev, "DMA channels found (%p,%p)\n", | ||
630 | host->dma_chan_tx, host->dma_chan_rx); | ||
631 | host->have_dma = true; | ||
632 | |||
633 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
634 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
635 | |||
636 | cfg.direction = DMA_MEM_TO_DEV; | ||
637 | cfg.src_addr = 0; | ||
638 | cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW; | ||
639 | dmaengine_slave_config(host->dma_chan_tx, &cfg); | ||
640 | |||
641 | cfg.direction = DMA_DEV_TO_MEM; | ||
642 | cfg.src_addr = host->reg_phys + REG_DATA_WINDOW; | ||
643 | cfg.dst_addr = 0; | ||
644 | dmaengine_slave_config(host->dma_chan_rx, &cfg); | ||
645 | } | ||
646 | |||
647 | switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) { | ||
648 | case 1: | ||
649 | mmc->caps |= MMC_CAP_4_BIT_DATA; | ||
650 | break; | ||
651 | case 2: | ||
652 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; | ||
653 | break; | ||
654 | default: | ||
655 | break; | ||
656 | } | ||
657 | |||
658 | writel(0, host->base + REG_INTERRUPT_MASK); | ||
659 | |||
660 | writel(CMD_SDC_RESET, host->base + REG_COMMAND); | ||
661 | for (i = 0; i < MAX_RETRIES; i++) { | ||
662 | if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET)) | ||
663 | break; | ||
664 | udelay(5); | ||
665 | } | ||
666 | |||
667 | ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host); | ||
668 | if (ret) | ||
669 | goto out; | ||
670 | |||
671 | dev_set_drvdata(dev, mmc); | ||
672 | mmc_add_host(mmc); | ||
673 | |||
674 | dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width); | ||
675 | |||
676 | return 0; | ||
677 | |||
678 | out: | ||
679 | if (mmc) | ||
680 | mmc_free_host(mmc); | ||
681 | return ret; | ||
682 | } | ||
683 | |||
684 | static int moxart_remove(struct platform_device *pdev) | ||
685 | { | ||
686 | struct mmc_host *mmc = dev_get_drvdata(&pdev->dev); | ||
687 | struct moxart_host *host = mmc_priv(mmc); | ||
688 | |||
689 | dev_set_drvdata(&pdev->dev, NULL); | ||
690 | |||
691 | if (mmc) { | ||
692 | if (!IS_ERR(host->dma_chan_tx)) | ||
693 | dma_release_channel(host->dma_chan_tx); | ||
694 | if (!IS_ERR(host->dma_chan_rx)) | ||
695 | dma_release_channel(host->dma_chan_rx); | ||
696 | mmc_remove_host(mmc); | ||
697 | mmc_free_host(mmc); | ||
698 | |||
699 | writel(0, host->base + REG_INTERRUPT_MASK); | ||
700 | writel(0, host->base + REG_POWER_CONTROL); | ||
701 | writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, | ||
702 | host->base + REG_CLOCK_CONTROL); | ||
703 | } | ||
704 | |||
705 | kfree(host); | ||
706 | |||
707 | return 0; | ||
708 | } | ||
709 | |||
710 | static const struct of_device_id moxart_mmc_match[] = { | ||
711 | { .compatible = "moxa,moxart-mmc" }, | ||
712 | { .compatible = "faraday,ftsdc010" }, | ||
713 | { } | ||
714 | }; | ||
715 | |||
716 | static struct platform_driver moxart_mmc_driver = { | ||
717 | .probe = moxart_probe, | ||
718 | .remove = moxart_remove, | ||
719 | .driver = { | ||
720 | .name = "mmc-moxart", | ||
721 | .owner = THIS_MODULE, | ||
722 | .of_match_table = moxart_mmc_match, | ||
723 | }, | ||
724 | }; | ||
725 | module_platform_driver(moxart_mmc_driver); | ||
726 | |||
727 | MODULE_ALIAS("platform:mmc-moxart"); | ||
728 | MODULE_DESCRIPTION("MOXA ART MMC driver"); | ||
729 | MODULE_LICENSE("GPL v2"); | ||
730 | MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); | ||
diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c index 45aa2206741d..9377284f8544 100644 --- a/drivers/mmc/host/mvsdio.c +++ b/drivers/mmc/host/mvsdio.c | |||
@@ -354,6 +354,20 @@ static irqreturn_t mvsd_irq(int irq, void *dev) | |||
354 | intr_status, mvsd_read(MVSD_NOR_INTR_EN), | 354 | intr_status, mvsd_read(MVSD_NOR_INTR_EN), |
355 | mvsd_read(MVSD_HW_STATE)); | 355 | mvsd_read(MVSD_HW_STATE)); |
356 | 356 | ||
357 | /* | ||
358 | * It looks like, SDIO IP can issue one late, spurious irq | ||
359 | * although all irqs should be disabled. To work around this, | ||
360 | * bail out early, if we didn't expect any irqs to occur. | ||
361 | */ | ||
362 | if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) { | ||
363 | dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n", | ||
364 | mvsd_read(MVSD_NOR_INTR_STATUS), | ||
365 | mvsd_read(MVSD_NOR_INTR_EN), | ||
366 | mvsd_read(MVSD_ERR_INTR_STATUS), | ||
367 | mvsd_read(MVSD_ERR_INTR_EN)); | ||
368 | return IRQ_HANDLED; | ||
369 | } | ||
370 | |||
357 | spin_lock(&host->lock); | 371 | spin_lock(&host->lock); |
358 | 372 | ||
359 | /* PIO handling, if needed. Messy business... */ | 373 | /* PIO handling, if needed. Messy business... */ |
@@ -801,10 +815,10 @@ static int mvsd_probe(struct platform_device *pdev) | |||
801 | goto out; | 815 | goto out; |
802 | 816 | ||
803 | if (!(mmc->caps & MMC_CAP_NEEDS_POLL)) | 817 | if (!(mmc->caps & MMC_CAP_NEEDS_POLL)) |
804 | dev_notice(&pdev->dev, "using GPIO for card detection\n"); | 818 | dev_dbg(&pdev->dev, "using GPIO for card detection\n"); |
805 | else | 819 | else |
806 | dev_notice(&pdev->dev, | 820 | dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n"); |
807 | "lacking card detect (fall back to polling)\n"); | 821 | |
808 | return 0; | 822 | return 0; |
809 | 823 | ||
810 | out: | 824 | out: |
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index f7199c83f5cf..ed1cb93c3784 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c | |||
@@ -124,9 +124,8 @@ enum mxcmci_type { | |||
124 | 124 | ||
125 | struct mxcmci_host { | 125 | struct mxcmci_host { |
126 | struct mmc_host *mmc; | 126 | struct mmc_host *mmc; |
127 | struct resource *res; | ||
128 | void __iomem *base; | 127 | void __iomem *base; |
129 | int irq; | 128 | dma_addr_t phys_base; |
130 | int detect_irq; | 129 | int detect_irq; |
131 | struct dma_chan *dma; | 130 | struct dma_chan *dma; |
132 | struct dma_async_tx_descriptor *desc; | 131 | struct dma_async_tx_descriptor *desc; |
@@ -154,8 +153,6 @@ struct mxcmci_host { | |||
154 | struct work_struct datawork; | 153 | struct work_struct datawork; |
155 | spinlock_t lock; | 154 | spinlock_t lock; |
156 | 155 | ||
157 | struct regulator *vcc; | ||
158 | |||
159 | int burstlen; | 156 | int burstlen; |
160 | int dmareq; | 157 | int dmareq; |
161 | struct dma_slave_config dma_slave_config; | 158 | struct dma_slave_config dma_slave_config; |
@@ -241,37 +238,15 @@ static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) | |||
241 | 238 | ||
242 | static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); | 239 | static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); |
243 | 240 | ||
244 | static inline void mxcmci_init_ocr(struct mxcmci_host *host) | 241 | static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd) |
245 | { | ||
246 | host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); | ||
247 | |||
248 | if (IS_ERR(host->vcc)) { | ||
249 | host->vcc = NULL; | ||
250 | } else { | ||
251 | host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); | ||
252 | if (host->pdata && host->pdata->ocr_avail) | ||
253 | dev_warn(mmc_dev(host->mmc), | ||
254 | "pdata->ocr_avail will not be used\n"); | ||
255 | } | ||
256 | |||
257 | if (host->vcc == NULL) { | ||
258 | /* fall-back to platform data */ | ||
259 | if (host->pdata && host->pdata->ocr_avail) | ||
260 | host->mmc->ocr_avail = host->pdata->ocr_avail; | ||
261 | else | ||
262 | host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | ||
263 | } | ||
264 | } | ||
265 | |||
266 | static inline void mxcmci_set_power(struct mxcmci_host *host, | ||
267 | unsigned char power_mode, | ||
268 | unsigned int vdd) | ||
269 | { | 242 | { |
270 | if (host->vcc) { | 243 | if (!IS_ERR(host->mmc->supply.vmmc)) { |
271 | if (power_mode == MMC_POWER_UP) | 244 | if (host->power_mode == MMC_POWER_UP) |
272 | mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); | 245 | mmc_regulator_set_ocr(host->mmc, |
273 | else if (power_mode == MMC_POWER_OFF) | 246 | host->mmc->supply.vmmc, vdd); |
274 | mmc_regulator_set_ocr(host->mmc, host->vcc, 0); | 247 | else if (host->power_mode == MMC_POWER_OFF) |
248 | mmc_regulator_set_ocr(host->mmc, | ||
249 | host->mmc->supply.vmmc, 0); | ||
275 | } | 250 | } |
276 | 251 | ||
277 | if (host->pdata && host->pdata->setpower) | 252 | if (host->pdata && host->pdata->setpower) |
@@ -299,7 +274,6 @@ static void mxcmci_softreset(struct mxcmci_host *host) | |||
299 | 274 | ||
300 | mxcmci_writew(host, 0xff, MMC_REG_RES_TO); | 275 | mxcmci_writew(host, 0xff, MMC_REG_RES_TO); |
301 | } | 276 | } |
302 | static int mxcmci_setup_dma(struct mmc_host *mmc); | ||
303 | 277 | ||
304 | #if IS_ENABLED(CONFIG_PPC_MPC512x) | 278 | #if IS_ENABLED(CONFIG_PPC_MPC512x) |
305 | static inline void buffer_swap32(u32 *buf, int len) | 279 | static inline void buffer_swap32(u32 *buf, int len) |
@@ -868,8 +842,8 @@ static int mxcmci_setup_dma(struct mmc_host *mmc) | |||
868 | struct mxcmci_host *host = mmc_priv(mmc); | 842 | struct mxcmci_host *host = mmc_priv(mmc); |
869 | struct dma_slave_config *config = &host->dma_slave_config; | 843 | struct dma_slave_config *config = &host->dma_slave_config; |
870 | 844 | ||
871 | config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS; | 845 | config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; |
872 | config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS; | 846 | config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; |
873 | config->dst_addr_width = 4; | 847 | config->dst_addr_width = 4; |
874 | config->src_addr_width = 4; | 848 | config->src_addr_width = 4; |
875 | config->dst_maxburst = host->burstlen; | 849 | config->dst_maxburst = host->burstlen; |
@@ -911,8 +885,8 @@ static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
911 | host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; | 885 | host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; |
912 | 886 | ||
913 | if (host->power_mode != ios->power_mode) { | 887 | if (host->power_mode != ios->power_mode) { |
914 | mxcmci_set_power(host, ios->power_mode, ios->vdd); | ||
915 | host->power_mode = ios->power_mode; | 888 | host->power_mode = ios->power_mode; |
889 | mxcmci_set_power(host, ios->vdd); | ||
916 | 890 | ||
917 | if (ios->power_mode == MMC_POWER_ON) | 891 | if (ios->power_mode == MMC_POWER_ON) |
918 | host->cmdat |= CMD_DAT_CONT_INIT; | 892 | host->cmdat |= CMD_DAT_CONT_INIT; |
@@ -1040,8 +1014,8 @@ static const struct mmc_host_ops mxcmci_ops = { | |||
1040 | static int mxcmci_probe(struct platform_device *pdev) | 1014 | static int mxcmci_probe(struct platform_device *pdev) |
1041 | { | 1015 | { |
1042 | struct mmc_host *mmc; | 1016 | struct mmc_host *mmc; |
1043 | struct mxcmci_host *host = NULL; | 1017 | struct mxcmci_host *host; |
1044 | struct resource *iores, *r; | 1018 | struct resource *res; |
1045 | int ret = 0, irq; | 1019 | int ret = 0, irq; |
1046 | bool dat3_card_detect = false; | 1020 | bool dat3_card_detect = false; |
1047 | dma_cap_mask_t mask; | 1021 | dma_cap_mask_t mask; |
@@ -1052,21 +1026,25 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1052 | 1026 | ||
1053 | of_id = of_match_device(mxcmci_of_match, &pdev->dev); | 1027 | of_id = of_match_device(mxcmci_of_match, &pdev->dev); |
1054 | 1028 | ||
1055 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1029 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1056 | irq = platform_get_irq(pdev, 0); | 1030 | irq = platform_get_irq(pdev, 0); |
1057 | if (!iores || irq < 0) | 1031 | if (irq < 0) |
1058 | return -EINVAL; | 1032 | return -EINVAL; |
1059 | 1033 | ||
1060 | r = request_mem_region(iores->start, resource_size(iores), pdev->name); | 1034 | mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); |
1061 | if (!r) | 1035 | if (!mmc) |
1062 | return -EBUSY; | 1036 | return -ENOMEM; |
1037 | |||
1038 | host = mmc_priv(mmc); | ||
1063 | 1039 | ||
1064 | mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); | 1040 | host->base = devm_ioremap_resource(&pdev->dev, res); |
1065 | if (!mmc) { | 1041 | if (IS_ERR(host->base)) { |
1066 | ret = -ENOMEM; | 1042 | ret = PTR_ERR(host->base); |
1067 | goto out_release_mem; | 1043 | goto out_free; |
1068 | } | 1044 | } |
1069 | 1045 | ||
1046 | host->phys_base = res->start; | ||
1047 | |||
1070 | ret = mmc_of_parse(mmc); | 1048 | ret = mmc_of_parse(mmc); |
1071 | if (ret) | 1049 | if (ret) |
1072 | goto out_free; | 1050 | goto out_free; |
@@ -1084,13 +1062,6 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1084 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | 1062 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
1085 | mmc->max_seg_size = mmc->max_req_size; | 1063 | mmc->max_seg_size = mmc->max_req_size; |
1086 | 1064 | ||
1087 | host = mmc_priv(mmc); | ||
1088 | host->base = ioremap(r->start, resource_size(r)); | ||
1089 | if (!host->base) { | ||
1090 | ret = -ENOMEM; | ||
1091 | goto out_free; | ||
1092 | } | ||
1093 | |||
1094 | if (of_id) { | 1065 | if (of_id) { |
1095 | const struct platform_device_id *id_entry = of_id->data; | 1066 | const struct platform_device_id *id_entry = of_id->data; |
1096 | host->devtype = id_entry->driver_data; | 1067 | host->devtype = id_entry->driver_data; |
@@ -1112,7 +1083,14 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1112 | && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) | 1083 | && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) |
1113 | dat3_card_detect = true; | 1084 | dat3_card_detect = true; |
1114 | 1085 | ||
1115 | mxcmci_init_ocr(host); | 1086 | ret = mmc_regulator_get_supply(mmc); |
1087 | if (ret) { | ||
1088 | if (pdata && ret != -EPROBE_DEFER) | ||
1089 | mmc->ocr_avail = pdata->ocr_avail ? : | ||
1090 | MMC_VDD_32_33 | MMC_VDD_33_34; | ||
1091 | else | ||
1092 | goto out_free; | ||
1093 | } | ||
1116 | 1094 | ||
1117 | if (dat3_card_detect) | 1095 | if (dat3_card_detect) |
1118 | host->default_irq_mask = | 1096 | host->default_irq_mask = |
@@ -1120,19 +1098,16 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1120 | else | 1098 | else |
1121 | host->default_irq_mask = 0; | 1099 | host->default_irq_mask = 0; |
1122 | 1100 | ||
1123 | host->res = r; | ||
1124 | host->irq = irq; | ||
1125 | |||
1126 | host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); | 1101 | host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1127 | if (IS_ERR(host->clk_ipg)) { | 1102 | if (IS_ERR(host->clk_ipg)) { |
1128 | ret = PTR_ERR(host->clk_ipg); | 1103 | ret = PTR_ERR(host->clk_ipg); |
1129 | goto out_iounmap; | 1104 | goto out_free; |
1130 | } | 1105 | } |
1131 | 1106 | ||
1132 | host->clk_per = devm_clk_get(&pdev->dev, "per"); | 1107 | host->clk_per = devm_clk_get(&pdev->dev, "per"); |
1133 | if (IS_ERR(host->clk_per)) { | 1108 | if (IS_ERR(host->clk_per)) { |
1134 | ret = PTR_ERR(host->clk_per); | 1109 | ret = PTR_ERR(host->clk_per); |
1135 | goto out_iounmap; | 1110 | goto out_free; |
1136 | } | 1111 | } |
1137 | 1112 | ||
1138 | clk_prepare_enable(host->clk_per); | 1113 | clk_prepare_enable(host->clk_per); |
@@ -1159,9 +1134,9 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1159 | if (!host->pdata) { | 1134 | if (!host->pdata) { |
1160 | host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx"); | 1135 | host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx"); |
1161 | } else { | 1136 | } else { |
1162 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | 1137 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1163 | if (r) { | 1138 | if (res) { |
1164 | host->dmareq = r->start; | 1139 | host->dmareq = res->start; |
1165 | host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; | 1140 | host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; |
1166 | host->dma_data.priority = DMA_PRIO_LOW; | 1141 | host->dma_data.priority = DMA_PRIO_LOW; |
1167 | host->dma_data.dma_request = host->dmareq; | 1142 | host->dma_data.dma_request = host->dmareq; |
@@ -1178,7 +1153,8 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1178 | 1153 | ||
1179 | INIT_WORK(&host->datawork, mxcmci_datawork); | 1154 | INIT_WORK(&host->datawork, mxcmci_datawork); |
1180 | 1155 | ||
1181 | ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host); | 1156 | ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0, |
1157 | dev_name(&pdev->dev), host); | ||
1182 | if (ret) | 1158 | if (ret) |
1183 | goto out_free_dma; | 1159 | goto out_free_dma; |
1184 | 1160 | ||
@@ -1188,7 +1164,7 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1188 | ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, | 1164 | ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, |
1189 | host->mmc); | 1165 | host->mmc); |
1190 | if (ret) | 1166 | if (ret) |
1191 | goto out_free_irq; | 1167 | goto out_free_dma; |
1192 | } | 1168 | } |
1193 | 1169 | ||
1194 | init_timer(&host->watchdog); | 1170 | init_timer(&host->watchdog); |
@@ -1199,20 +1175,17 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
1199 | 1175 | ||
1200 | return 0; | 1176 | return 0; |
1201 | 1177 | ||
1202 | out_free_irq: | ||
1203 | free_irq(host->irq, host); | ||
1204 | out_free_dma: | 1178 | out_free_dma: |
1205 | if (host->dma) | 1179 | if (host->dma) |
1206 | dma_release_channel(host->dma); | 1180 | dma_release_channel(host->dma); |
1181 | |||
1207 | out_clk_put: | 1182 | out_clk_put: |
1208 | clk_disable_unprepare(host->clk_per); | 1183 | clk_disable_unprepare(host->clk_per); |
1209 | clk_disable_unprepare(host->clk_ipg); | 1184 | clk_disable_unprepare(host->clk_ipg); |
1210 | out_iounmap: | 1185 | |
1211 | iounmap(host->base); | ||
1212 | out_free: | 1186 | out_free: |
1213 | mmc_free_host(mmc); | 1187 | mmc_free_host(mmc); |
1214 | out_release_mem: | 1188 | |
1215 | release_mem_region(iores->start, resource_size(iores)); | ||
1216 | return ret; | 1189 | return ret; |
1217 | } | 1190 | } |
1218 | 1191 | ||
@@ -1223,30 +1196,21 @@ static int mxcmci_remove(struct platform_device *pdev) | |||
1223 | 1196 | ||
1224 | mmc_remove_host(mmc); | 1197 | mmc_remove_host(mmc); |
1225 | 1198 | ||
1226 | if (host->vcc) | ||
1227 | regulator_put(host->vcc); | ||
1228 | |||
1229 | if (host->pdata && host->pdata->exit) | 1199 | if (host->pdata && host->pdata->exit) |
1230 | host->pdata->exit(&pdev->dev, mmc); | 1200 | host->pdata->exit(&pdev->dev, mmc); |
1231 | 1201 | ||
1232 | free_irq(host->irq, host); | ||
1233 | iounmap(host->base); | ||
1234 | |||
1235 | if (host->dma) | 1202 | if (host->dma) |
1236 | dma_release_channel(host->dma); | 1203 | dma_release_channel(host->dma); |
1237 | 1204 | ||
1238 | clk_disable_unprepare(host->clk_per); | 1205 | clk_disable_unprepare(host->clk_per); |
1239 | clk_disable_unprepare(host->clk_ipg); | 1206 | clk_disable_unprepare(host->clk_ipg); |
1240 | 1207 | ||
1241 | release_mem_region(host->res->start, resource_size(host->res)); | ||
1242 | |||
1243 | mmc_free_host(mmc); | 1208 | mmc_free_host(mmc); |
1244 | 1209 | ||
1245 | return 0; | 1210 | return 0; |
1246 | } | 1211 | } |
1247 | 1212 | ||
1248 | #ifdef CONFIG_PM | 1213 | static int __maybe_unused mxcmci_suspend(struct device *dev) |
1249 | static int mxcmci_suspend(struct device *dev) | ||
1250 | { | 1214 | { |
1251 | struct mmc_host *mmc = dev_get_drvdata(dev); | 1215 | struct mmc_host *mmc = dev_get_drvdata(dev); |
1252 | struct mxcmci_host *host = mmc_priv(mmc); | 1216 | struct mxcmci_host *host = mmc_priv(mmc); |
@@ -1256,7 +1220,7 @@ static int mxcmci_suspend(struct device *dev) | |||
1256 | return 0; | 1220 | return 0; |
1257 | } | 1221 | } |
1258 | 1222 | ||
1259 | static int mxcmci_resume(struct device *dev) | 1223 | static int __maybe_unused mxcmci_resume(struct device *dev) |
1260 | { | 1224 | { |
1261 | struct mmc_host *mmc = dev_get_drvdata(dev); | 1225 | struct mmc_host *mmc = dev_get_drvdata(dev); |
1262 | struct mxcmci_host *host = mmc_priv(mmc); | 1226 | struct mxcmci_host *host = mmc_priv(mmc); |
@@ -1266,11 +1230,7 @@ static int mxcmci_resume(struct device *dev) | |||
1266 | return 0; | 1230 | return 0; |
1267 | } | 1231 | } |
1268 | 1232 | ||
1269 | static const struct dev_pm_ops mxcmci_pm_ops = { | 1233 | static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume); |
1270 | .suspend = mxcmci_suspend, | ||
1271 | .resume = mxcmci_resume, | ||
1272 | }; | ||
1273 | #endif | ||
1274 | 1234 | ||
1275 | static struct platform_driver mxcmci_driver = { | 1235 | static struct platform_driver mxcmci_driver = { |
1276 | .probe = mxcmci_probe, | 1236 | .probe = mxcmci_probe, |
@@ -1279,9 +1239,7 @@ static struct platform_driver mxcmci_driver = { | |||
1279 | .driver = { | 1239 | .driver = { |
1280 | .name = DRIVER_NAME, | 1240 | .name = DRIVER_NAME, |
1281 | .owner = THIS_MODULE, | 1241 | .owner = THIS_MODULE, |
1282 | #ifdef CONFIG_PM | ||
1283 | .pm = &mxcmci_pm_ops, | 1242 | .pm = &mxcmci_pm_ops, |
1284 | #endif | ||
1285 | .of_match_table = mxcmci_of_match, | 1243 | .of_match_table = mxcmci_of_match, |
1286 | } | 1244 | } |
1287 | }; | 1245 | }; |
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c index 073e871a0fc8..babfea03ba8a 100644 --- a/drivers/mmc/host/mxs-mmc.c +++ b/drivers/mmc/host/mxs-mmc.c | |||
@@ -70,6 +70,7 @@ struct mxs_mmc_host { | |||
70 | unsigned char bus_width; | 70 | unsigned char bus_width; |
71 | spinlock_t lock; | 71 | spinlock_t lock; |
72 | int sdio_irq_en; | 72 | int sdio_irq_en; |
73 | bool broken_cd; | ||
73 | }; | 74 | }; |
74 | 75 | ||
75 | static int mxs_mmc_get_cd(struct mmc_host *mmc) | 76 | static int mxs_mmc_get_cd(struct mmc_host *mmc) |
@@ -78,6 +79,9 @@ static int mxs_mmc_get_cd(struct mmc_host *mmc) | |||
78 | struct mxs_ssp *ssp = &host->ssp; | 79 | struct mxs_ssp *ssp = &host->ssp; |
79 | int present, ret; | 80 | int present, ret; |
80 | 81 | ||
82 | if (host->broken_cd) | ||
83 | return -ENOSYS; | ||
84 | |||
81 | ret = mmc_gpio_get_cd(mmc); | 85 | ret = mmc_gpio_get_cd(mmc); |
82 | if (ret >= 0) | 86 | if (ret >= 0) |
83 | return ret; | 87 | return ret; |
@@ -568,6 +572,7 @@ static int mxs_mmc_probe(struct platform_device *pdev) | |||
568 | { | 572 | { |
569 | const struct of_device_id *of_id = | 573 | const struct of_device_id *of_id = |
570 | of_match_device(mxs_mmc_dt_ids, &pdev->dev); | 574 | of_match_device(mxs_mmc_dt_ids, &pdev->dev); |
575 | struct device_node *np = pdev->dev.of_node; | ||
571 | struct mxs_mmc_host *host; | 576 | struct mxs_mmc_host *host; |
572 | struct mmc_host *mmc; | 577 | struct mmc_host *mmc; |
573 | struct resource *iores; | 578 | struct resource *iores; |
@@ -634,6 +639,8 @@ static int mxs_mmc_probe(struct platform_device *pdev) | |||
634 | mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | | 639 | mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | |
635 | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; | 640 | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; |
636 | 641 | ||
642 | host->broken_cd = of_property_read_bool(np, "broken-cd"); | ||
643 | |||
637 | mmc->f_min = 400000; | 644 | mmc->f_min = 400000; |
638 | mmc->f_max = 288000000; | 645 | mmc->f_max = 288000000; |
639 | 646 | ||
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 5c2e58b29305..81974ecdfcbc 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c | |||
@@ -177,7 +177,7 @@ static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) | |||
177 | unsigned long tick_ns; | 177 | unsigned long tick_ns; |
178 | 178 | ||
179 | if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { | 179 | if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { |
180 | tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq; | 180 | tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq); |
181 | ndelay(8 * tick_ns); | 181 | ndelay(8 * tick_ns); |
182 | } | 182 | } |
183 | } | 183 | } |
@@ -435,7 +435,7 @@ static void mmc_omap_send_stop_work(struct work_struct *work) | |||
435 | struct mmc_data *data = host->stop_data; | 435 | struct mmc_data *data = host->stop_data; |
436 | unsigned long tick_ns; | 436 | unsigned long tick_ns; |
437 | 437 | ||
438 | tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq; | 438 | tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq); |
439 | ndelay(8*tick_ns); | 439 | ndelay(8*tick_ns); |
440 | 440 | ||
441 | mmc_omap_start_command(host, data->stop); | 441 | mmc_omap_start_command(host, data->stop); |
@@ -477,7 +477,7 @@ mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) | |||
477 | u16 stat = 0; | 477 | u16 stat = 0; |
478 | 478 | ||
479 | /* Sending abort takes 80 clocks. Have some extra and round up */ | 479 | /* Sending abort takes 80 clocks. Have some extra and round up */ |
480 | timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq; | 480 | timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq); |
481 | restarts = 0; | 481 | restarts = 0; |
482 | while (restarts < maxloops) { | 482 | while (restarts < maxloops) { |
483 | OMAP_MMC_WRITE(host, STAT, 0xFFFF); | 483 | OMAP_MMC_WRITE(host, STAT, 0xFFFF); |
@@ -677,8 +677,8 @@ mmc_omap_xfer_data(struct mmc_omap_host *host, int write) | |||
677 | if (n > host->buffer_bytes_left) | 677 | if (n > host->buffer_bytes_left) |
678 | n = host->buffer_bytes_left; | 678 | n = host->buffer_bytes_left; |
679 | 679 | ||
680 | nwords = n / 2; | 680 | /* Round up to handle odd number of bytes to transfer */ |
681 | nwords += n & 1; /* handle odd number of bytes to transfer */ | 681 | nwords = DIV_ROUND_UP(n, 2); |
682 | 682 | ||
683 | host->buffer_bytes_left -= n; | 683 | host->buffer_bytes_left -= n; |
684 | host->total_bytes_left -= n; | 684 | host->total_bytes_left -= n; |
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index e91ee21549d0..6b7b75585926 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c | |||
@@ -31,7 +31,7 @@ | |||
31 | #include <linux/of.h> | 31 | #include <linux/of.h> |
32 | #include <linux/of_gpio.h> | 32 | #include <linux/of_gpio.h> |
33 | #include <linux/of_device.h> | 33 | #include <linux/of_device.h> |
34 | #include <linux/omap-dma.h> | 34 | #include <linux/omap-dmaengine.h> |
35 | #include <linux/mmc/host.h> | 35 | #include <linux/mmc/host.h> |
36 | #include <linux/mmc/core.h> | 36 | #include <linux/mmc/core.h> |
37 | #include <linux/mmc/mmc.h> | 37 | #include <linux/mmc/mmc.h> |
@@ -582,7 +582,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) | |||
582 | * - MMC/SD clock coming out of controller > 25MHz | 582 | * - MMC/SD clock coming out of controller > 25MHz |
583 | */ | 583 | */ |
584 | if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && | 584 | if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && |
585 | (ios->timing != MMC_TIMING_UHS_DDR50) && | 585 | (ios->timing != MMC_TIMING_MMC_DDR52) && |
586 | ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { | 586 | ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { |
587 | regval = OMAP_HSMMC_READ(host->base, HCTL); | 587 | regval = OMAP_HSMMC_READ(host->base, HCTL); |
588 | if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) | 588 | if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) |
@@ -602,7 +602,7 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) | |||
602 | u32 con; | 602 | u32 con; |
603 | 603 | ||
604 | con = OMAP_HSMMC_READ(host->base, CON); | 604 | con = OMAP_HSMMC_READ(host->base, CON); |
605 | if (ios->timing == MMC_TIMING_UHS_DDR50) | 605 | if (ios->timing == MMC_TIMING_MMC_DDR52) |
606 | con |= DDR; /* configure in DDR mode */ | 606 | con |= DDR; /* configure in DDR mode */ |
607 | else | 607 | else |
608 | con &= ~DDR; | 608 | con &= ~DDR; |
@@ -920,16 +920,17 @@ omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) | |||
920 | static void | 920 | static void |
921 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) | 921 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
922 | { | 922 | { |
923 | host->cmd = NULL; | ||
924 | |||
925 | if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && | 923 | if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && |
926 | !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { | 924 | !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { |
925 | host->cmd = NULL; | ||
927 | omap_hsmmc_start_dma_transfer(host); | 926 | omap_hsmmc_start_dma_transfer(host); |
928 | omap_hsmmc_start_command(host, host->mrq->cmd, | 927 | omap_hsmmc_start_command(host, host->mrq->cmd, |
929 | host->mrq->data); | 928 | host->mrq->data); |
930 | return; | 929 | return; |
931 | } | 930 | } |
932 | 931 | ||
932 | host->cmd = NULL; | ||
933 | |||
933 | if (cmd->flags & MMC_RSP_PRESENT) { | 934 | if (cmd->flags & MMC_RSP_PRESENT) { |
934 | if (cmd->flags & MMC_RSP_136) { | 935 | if (cmd->flags & MMC_RSP_136) { |
935 | /* response type 2 */ | 936 | /* response type 2 */ |
@@ -1851,6 +1852,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
1851 | unsigned tx_req, rx_req; | 1852 | unsigned tx_req, rx_req; |
1852 | struct pinctrl *pinctrl; | 1853 | struct pinctrl *pinctrl; |
1853 | const struct omap_mmc_of_data *data; | 1854 | const struct omap_mmc_of_data *data; |
1855 | void __iomem *base; | ||
1854 | 1856 | ||
1855 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); | 1857 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); |
1856 | if (match) { | 1858 | if (match) { |
@@ -1881,9 +1883,9 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
1881 | if (res == NULL || irq < 0) | 1883 | if (res == NULL || irq < 0) |
1882 | return -ENXIO; | 1884 | return -ENXIO; |
1883 | 1885 | ||
1884 | res = request_mem_region(res->start, resource_size(res), pdev->name); | 1886 | base = devm_ioremap_resource(&pdev->dev, res); |
1885 | if (res == NULL) | 1887 | if (IS_ERR(base)) |
1886 | return -EBUSY; | 1888 | return PTR_ERR(base); |
1887 | 1889 | ||
1888 | ret = omap_hsmmc_gpio_init(pdata); | 1890 | ret = omap_hsmmc_gpio_init(pdata); |
1889 | if (ret) | 1891 | if (ret) |
@@ -1904,7 +1906,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
1904 | host->irq = irq; | 1906 | host->irq = irq; |
1905 | host->slot_id = 0; | 1907 | host->slot_id = 0; |
1906 | host->mapbase = res->start + pdata->reg_offset; | 1908 | host->mapbase = res->start + pdata->reg_offset; |
1907 | host->base = ioremap(host->mapbase, SZ_4K); | 1909 | host->base = base + pdata->reg_offset; |
1908 | host->power_mode = MMC_POWER_OFF; | 1910 | host->power_mode = MMC_POWER_OFF; |
1909 | host->next_data.cookie = 1; | 1911 | host->next_data.cookie = 1; |
1910 | host->pbias_enabled = 0; | 1912 | host->pbias_enabled = 0; |
@@ -1922,7 +1924,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
1922 | 1924 | ||
1923 | spin_lock_init(&host->irq_lock); | 1925 | spin_lock_init(&host->irq_lock); |
1924 | 1926 | ||
1925 | host->fclk = clk_get(&pdev->dev, "fck"); | 1927 | host->fclk = devm_clk_get(&pdev->dev, "fck"); |
1926 | if (IS_ERR(host->fclk)) { | 1928 | if (IS_ERR(host->fclk)) { |
1927 | ret = PTR_ERR(host->fclk); | 1929 | ret = PTR_ERR(host->fclk); |
1928 | host->fclk = NULL; | 1930 | host->fclk = NULL; |
@@ -1941,7 +1943,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
1941 | 1943 | ||
1942 | omap_hsmmc_context_save(host); | 1944 | omap_hsmmc_context_save(host); |
1943 | 1945 | ||
1944 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); | 1946 | host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); |
1945 | /* | 1947 | /* |
1946 | * MMC can still work without debounce clock. | 1948 | * MMC can still work without debounce clock. |
1947 | */ | 1949 | */ |
@@ -1949,7 +1951,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
1949 | host->dbclk = NULL; | 1951 | host->dbclk = NULL; |
1950 | } else if (clk_prepare_enable(host->dbclk) != 0) { | 1952 | } else if (clk_prepare_enable(host->dbclk) != 0) { |
1951 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); | 1953 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); |
1952 | clk_put(host->dbclk); | ||
1953 | host->dbclk = NULL; | 1954 | host->dbclk = NULL; |
1954 | } | 1955 | } |
1955 | 1956 | ||
@@ -2018,7 +2019,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
2018 | } | 2019 | } |
2019 | 2020 | ||
2020 | /* Request IRQ for MMC operations */ | 2021 | /* Request IRQ for MMC operations */ |
2021 | ret = request_irq(host->irq, omap_hsmmc_irq, 0, | 2022 | ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, |
2022 | mmc_hostname(mmc), host); | 2023 | mmc_hostname(mmc), host); |
2023 | if (ret) { | 2024 | if (ret) { |
2024 | dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | 2025 | dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); |
@@ -2029,7 +2030,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
2029 | if (pdata->init(&pdev->dev) != 0) { | 2030 | if (pdata->init(&pdev->dev) != 0) { |
2030 | dev_err(mmc_dev(host->mmc), | 2031 | dev_err(mmc_dev(host->mmc), |
2031 | "Unable to configure MMC IRQs\n"); | 2032 | "Unable to configure MMC IRQs\n"); |
2032 | goto err_irq_cd_init; | 2033 | goto err_irq; |
2033 | } | 2034 | } |
2034 | } | 2035 | } |
2035 | 2036 | ||
@@ -2044,9 +2045,9 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
2044 | 2045 | ||
2045 | /* Request IRQ for card detect */ | 2046 | /* Request IRQ for card detect */ |
2046 | if ((mmc_slot(host).card_detect_irq)) { | 2047 | if ((mmc_slot(host).card_detect_irq)) { |
2047 | ret = request_threaded_irq(mmc_slot(host).card_detect_irq, | 2048 | ret = devm_request_threaded_irq(&pdev->dev, |
2048 | NULL, | 2049 | mmc_slot(host).card_detect_irq, |
2049 | omap_hsmmc_detect, | 2050 | NULL, omap_hsmmc_detect, |
2050 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | 2051 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
2051 | mmc_hostname(mmc), host); | 2052 | mmc_hostname(mmc), host); |
2052 | if (ret) { | 2053 | if (ret) { |
@@ -2089,15 +2090,12 @@ static int omap_hsmmc_probe(struct platform_device *pdev) | |||
2089 | 2090 | ||
2090 | err_slot_name: | 2091 | err_slot_name: |
2091 | mmc_remove_host(mmc); | 2092 | mmc_remove_host(mmc); |
2092 | free_irq(mmc_slot(host).card_detect_irq, host); | ||
2093 | err_irq_cd: | 2093 | err_irq_cd: |
2094 | if (host->use_reg) | 2094 | if (host->use_reg) |
2095 | omap_hsmmc_reg_put(host); | 2095 | omap_hsmmc_reg_put(host); |
2096 | err_reg: | 2096 | err_reg: |
2097 | if (host->pdata->cleanup) | 2097 | if (host->pdata->cleanup) |
2098 | host->pdata->cleanup(&pdev->dev); | 2098 | host->pdata->cleanup(&pdev->dev); |
2099 | err_irq_cd_init: | ||
2100 | free_irq(host->irq, host); | ||
2101 | err_irq: | 2099 | err_irq: |
2102 | if (host->tx_chan) | 2100 | if (host->tx_chan) |
2103 | dma_release_channel(host->tx_chan); | 2101 | dma_release_channel(host->tx_chan); |
@@ -2105,27 +2103,19 @@ err_irq: | |||
2105 | dma_release_channel(host->rx_chan); | 2103 | dma_release_channel(host->rx_chan); |
2106 | pm_runtime_put_sync(host->dev); | 2104 | pm_runtime_put_sync(host->dev); |
2107 | pm_runtime_disable(host->dev); | 2105 | pm_runtime_disable(host->dev); |
2108 | clk_put(host->fclk); | 2106 | if (host->dbclk) |
2109 | if (host->dbclk) { | ||
2110 | clk_disable_unprepare(host->dbclk); | 2107 | clk_disable_unprepare(host->dbclk); |
2111 | clk_put(host->dbclk); | ||
2112 | } | ||
2113 | err1: | 2108 | err1: |
2114 | iounmap(host->base); | ||
2115 | mmc_free_host(mmc); | 2109 | mmc_free_host(mmc); |
2116 | err_alloc: | 2110 | err_alloc: |
2117 | omap_hsmmc_gpio_free(pdata); | 2111 | omap_hsmmc_gpio_free(pdata); |
2118 | err: | 2112 | err: |
2119 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
2120 | if (res) | ||
2121 | release_mem_region(res->start, resource_size(res)); | ||
2122 | return ret; | 2113 | return ret; |
2123 | } | 2114 | } |
2124 | 2115 | ||
2125 | static int omap_hsmmc_remove(struct platform_device *pdev) | 2116 | static int omap_hsmmc_remove(struct platform_device *pdev) |
2126 | { | 2117 | { |
2127 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); | 2118 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
2128 | struct resource *res; | ||
2129 | 2119 | ||
2130 | pm_runtime_get_sync(host->dev); | 2120 | pm_runtime_get_sync(host->dev); |
2131 | mmc_remove_host(host->mmc); | 2121 | mmc_remove_host(host->mmc); |
@@ -2133,9 +2123,6 @@ static int omap_hsmmc_remove(struct platform_device *pdev) | |||
2133 | omap_hsmmc_reg_put(host); | 2123 | omap_hsmmc_reg_put(host); |
2134 | if (host->pdata->cleanup) | 2124 | if (host->pdata->cleanup) |
2135 | host->pdata->cleanup(&pdev->dev); | 2125 | host->pdata->cleanup(&pdev->dev); |
2136 | free_irq(host->irq, host); | ||
2137 | if (mmc_slot(host).card_detect_irq) | ||
2138 | free_irq(mmc_slot(host).card_detect_irq, host); | ||
2139 | 2126 | ||
2140 | if (host->tx_chan) | 2127 | if (host->tx_chan) |
2141 | dma_release_channel(host->tx_chan); | 2128 | dma_release_channel(host->tx_chan); |
@@ -2144,20 +2131,12 @@ static int omap_hsmmc_remove(struct platform_device *pdev) | |||
2144 | 2131 | ||
2145 | pm_runtime_put_sync(host->dev); | 2132 | pm_runtime_put_sync(host->dev); |
2146 | pm_runtime_disable(host->dev); | 2133 | pm_runtime_disable(host->dev); |
2147 | clk_put(host->fclk); | 2134 | if (host->dbclk) |
2148 | if (host->dbclk) { | ||
2149 | clk_disable_unprepare(host->dbclk); | 2135 | clk_disable_unprepare(host->dbclk); |
2150 | clk_put(host->dbclk); | ||
2151 | } | ||
2152 | 2136 | ||
2153 | omap_hsmmc_gpio_free(host->pdata); | 2137 | omap_hsmmc_gpio_free(host->pdata); |
2154 | iounmap(host->base); | ||
2155 | mmc_free_host(host->mmc); | 2138 | mmc_free_host(host->mmc); |
2156 | 2139 | ||
2157 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
2158 | if (res) | ||
2159 | release_mem_region(res->start, resource_size(res)); | ||
2160 | |||
2161 | return 0; | 2140 | return 0; |
2162 | } | 2141 | } |
2163 | 2142 | ||
diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c index 0b9ded13a3ae..0d519649b575 100644 --- a/drivers/mmc/host/rtsx_pci_sdmmc.c +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c | |||
@@ -236,6 +236,9 @@ static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, | |||
236 | case MMC_RSP_R1: | 236 | case MMC_RSP_R1: |
237 | rsp_type = SD_RSP_TYPE_R1; | 237 | rsp_type = SD_RSP_TYPE_R1; |
238 | break; | 238 | break; |
239 | case MMC_RSP_R1 & ~MMC_RSP_CRC: | ||
240 | rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; | ||
241 | break; | ||
239 | case MMC_RSP_R1B: | 242 | case MMC_RSP_R1B: |
240 | rsp_type = SD_RSP_TYPE_R1b; | 243 | rsp_type = SD_RSP_TYPE_R1b; |
241 | break; | 244 | break; |
@@ -816,6 +819,7 @@ static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) | |||
816 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | 819 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); |
817 | break; | 820 | break; |
818 | 821 | ||
822 | case MMC_TIMING_MMC_DDR52: | ||
819 | case MMC_TIMING_UHS_DDR50: | 823 | case MMC_TIMING_UHS_DDR50: |
820 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, | 824 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, |
821 | 0x0C | SD_ASYNC_FIFO_NOT_RST, | 825 | 0x0C | SD_ASYNC_FIFO_NOT_RST, |
@@ -896,6 +900,7 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
896 | host->vpclk = true; | 900 | host->vpclk = true; |
897 | host->double_clk = false; | 901 | host->double_clk = false; |
898 | break; | 902 | break; |
903 | case MMC_TIMING_MMC_DDR52: | ||
899 | case MMC_TIMING_UHS_DDR50: | 904 | case MMC_TIMING_UHS_DDR50: |
900 | case MMC_TIMING_UHS_SDR25: | 905 | case MMC_TIMING_UHS_SDR25: |
901 | host->ssc_depth = RTSX_SSC_DEPTH_1M; | 906 | host->ssc_depth = RTSX_SSC_DEPTH_1M; |
diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c b/drivers/mmc/host/rtsx_usb_sdmmc.c index e11fafa6fc6b..5d3766e792f0 100644 --- a/drivers/mmc/host/rtsx_usb_sdmmc.c +++ b/drivers/mmc/host/rtsx_usb_sdmmc.c | |||
@@ -34,7 +34,8 @@ | |||
34 | #include <linux/mfd/rtsx_usb.h> | 34 | #include <linux/mfd/rtsx_usb.h> |
35 | #include <asm/unaligned.h> | 35 | #include <asm/unaligned.h> |
36 | 36 | ||
37 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) | 37 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
38 | defined(CONFIG_MMC_REALTEK_USB_MODULE)) | ||
38 | #include <linux/leds.h> | 39 | #include <linux/leds.h> |
39 | #include <linux/workqueue.h> | 40 | #include <linux/workqueue.h> |
40 | #define RTSX_USB_USE_LEDS_CLASS | 41 | #define RTSX_USB_USE_LEDS_CLASS |
@@ -59,7 +60,7 @@ struct rtsx_usb_sdmmc { | |||
59 | 60 | ||
60 | unsigned char power_mode; | 61 | unsigned char power_mode; |
61 | 62 | ||
62 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) | 63 | #ifdef RTSX_USB_USE_LEDS_CLASS |
63 | struct led_classdev led; | 64 | struct led_classdev led; |
64 | char led_name[32]; | 65 | char led_name[32]; |
65 | struct work_struct led_work; | 66 | struct work_struct led_work; |
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index ebb3f392b589..8ce3c28cb76e 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c | |||
@@ -102,11 +102,19 @@ static void sdhci_acpi_int_hw_reset(struct sdhci_host *host) | |||
102 | } | 102 | } |
103 | 103 | ||
104 | static const struct sdhci_ops sdhci_acpi_ops_dflt = { | 104 | static const struct sdhci_ops sdhci_acpi_ops_dflt = { |
105 | .set_clock = sdhci_set_clock, | ||
105 | .enable_dma = sdhci_acpi_enable_dma, | 106 | .enable_dma = sdhci_acpi_enable_dma, |
107 | .set_bus_width = sdhci_set_bus_width, | ||
108 | .reset = sdhci_reset, | ||
109 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
106 | }; | 110 | }; |
107 | 111 | ||
108 | static const struct sdhci_ops sdhci_acpi_ops_int = { | 112 | static const struct sdhci_ops sdhci_acpi_ops_int = { |
113 | .set_clock = sdhci_set_clock, | ||
109 | .enable_dma = sdhci_acpi_enable_dma, | 114 | .enable_dma = sdhci_acpi_enable_dma, |
115 | .set_bus_width = sdhci_set_bus_width, | ||
116 | .reset = sdhci_reset, | ||
117 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
110 | .hw_reset = sdhci_acpi_int_hw_reset, | 118 | .hw_reset = sdhci_acpi_int_hw_reset, |
111 | }; | 119 | }; |
112 | 120 | ||
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c index 6f166e63b817..dd780c315a63 100644 --- a/drivers/mmc/host/sdhci-bcm-kona.c +++ b/drivers/mmc/host/sdhci-bcm-kona.c | |||
@@ -206,9 +206,13 @@ static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host, | |||
206 | } | 206 | } |
207 | 207 | ||
208 | static struct sdhci_ops sdhci_bcm_kona_ops = { | 208 | static struct sdhci_ops sdhci_bcm_kona_ops = { |
209 | .set_clock = sdhci_set_clock, | ||
209 | .get_max_clock = sdhci_bcm_kona_get_max_clk, | 210 | .get_max_clock = sdhci_bcm_kona_get_max_clk, |
210 | .get_timeout_clock = sdhci_bcm_kona_get_timeout_clock, | 211 | .get_timeout_clock = sdhci_bcm_kona_get_timeout_clock, |
211 | .platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks, | 212 | .platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks, |
213 | .set_bus_width = sdhci_set_bus_width, | ||
214 | .reset = sdhci_reset, | ||
215 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
212 | .card_event = sdhci_bcm_kona_card_event, | 216 | .card_event = sdhci_bcm_kona_card_event, |
213 | }; | 217 | }; |
214 | 218 | ||
diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c index f6d8d67c545f..46af9a439d7b 100644 --- a/drivers/mmc/host/sdhci-bcm2835.c +++ b/drivers/mmc/host/sdhci-bcm2835.c | |||
@@ -131,8 +131,12 @@ static const struct sdhci_ops bcm2835_sdhci_ops = { | |||
131 | .read_l = bcm2835_sdhci_readl, | 131 | .read_l = bcm2835_sdhci_readl, |
132 | .read_w = bcm2835_sdhci_readw, | 132 | .read_w = bcm2835_sdhci_readw, |
133 | .read_b = bcm2835_sdhci_readb, | 133 | .read_b = bcm2835_sdhci_readb, |
134 | .set_clock = sdhci_set_clock, | ||
134 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | 135 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
135 | .get_min_clock = bcm2835_sdhci_get_min_clock, | 136 | .get_min_clock = bcm2835_sdhci_get_min_clock, |
137 | .set_bus_width = sdhci_set_bus_width, | ||
138 | .reset = sdhci_reset, | ||
139 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
136 | }; | 140 | }; |
137 | 141 | ||
138 | static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = { | 142 | static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = { |
diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c index f2cc26633cb2..14b74075589a 100644 --- a/drivers/mmc/host/sdhci-cns3xxx.c +++ b/drivers/mmc/host/sdhci-cns3xxx.c | |||
@@ -30,13 +30,12 @@ static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) | |||
30 | u16 clk; | 30 | u16 clk; |
31 | unsigned long timeout; | 31 | unsigned long timeout; |
32 | 32 | ||
33 | if (clock == host->clock) | 33 | host->mmc->actual_clock = 0; |
34 | return; | ||
35 | 34 | ||
36 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | 35 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
37 | 36 | ||
38 | if (clock == 0) | 37 | if (clock == 0) |
39 | goto out; | 38 | return; |
40 | 39 | ||
41 | while (host->max_clk / div > clock) { | 40 | while (host->max_clk / div > clock) { |
42 | /* | 41 | /* |
@@ -75,13 +74,14 @@ static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) | |||
75 | 74 | ||
76 | clk |= SDHCI_CLOCK_CARD_EN; | 75 | clk |= SDHCI_CLOCK_CARD_EN; |
77 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | 76 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
78 | out: | ||
79 | host->clock = clock; | ||
80 | } | 77 | } |
81 | 78 | ||
82 | static const struct sdhci_ops sdhci_cns3xxx_ops = { | 79 | static const struct sdhci_ops sdhci_cns3xxx_ops = { |
83 | .get_max_clock = sdhci_cns3xxx_get_max_clk, | 80 | .get_max_clock = sdhci_cns3xxx_get_max_clk, |
84 | .set_clock = sdhci_cns3xxx_set_clock, | 81 | .set_clock = sdhci_cns3xxx_set_clock, |
82 | .set_bus_width = sdhci_set_bus_width, | ||
83 | .reset = sdhci_reset, | ||
84 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
85 | }; | 85 | }; |
86 | 86 | ||
87 | static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = { | 87 | static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = { |
@@ -90,8 +90,7 @@ static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = { | |||
90 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | 90 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
91 | SDHCI_QUIRK_INVERTED_WRITE_PROTECT | | 91 | SDHCI_QUIRK_INVERTED_WRITE_PROTECT | |
92 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | | 92 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | |
93 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | | 93 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
94 | SDHCI_QUIRK_NONSTANDARD_CLOCK, | ||
95 | }; | 94 | }; |
96 | 95 | ||
97 | static int sdhci_cns3xxx_probe(struct platform_device *pdev) | 96 | static int sdhci_cns3xxx_probe(struct platform_device *pdev) |
diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c index 736d7a2eb7ec..e6278ec007d7 100644 --- a/drivers/mmc/host/sdhci-dove.c +++ b/drivers/mmc/host/sdhci-dove.c | |||
@@ -21,28 +21,17 @@ | |||
21 | 21 | ||
22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
23 | #include <linux/err.h> | 23 | #include <linux/err.h> |
24 | #include <linux/gpio.h> | ||
25 | #include <linux/io.h> | 24 | #include <linux/io.h> |
26 | #include <linux/mmc/host.h> | 25 | #include <linux/mmc/host.h> |
27 | #include <linux/module.h> | 26 | #include <linux/module.h> |
28 | #include <linux/of.h> | 27 | #include <linux/of.h> |
29 | #include <linux/of_gpio.h> | ||
30 | 28 | ||
31 | #include "sdhci-pltfm.h" | 29 | #include "sdhci-pltfm.h" |
32 | 30 | ||
33 | struct sdhci_dove_priv { | 31 | struct sdhci_dove_priv { |
34 | struct clk *clk; | 32 | struct clk *clk; |
35 | int gpio_cd; | ||
36 | }; | 33 | }; |
37 | 34 | ||
38 | static irqreturn_t sdhci_dove_carddetect_irq(int irq, void *data) | ||
39 | { | ||
40 | struct sdhci_host *host = data; | ||
41 | |||
42 | tasklet_schedule(&host->card_tasklet); | ||
43 | return IRQ_HANDLED; | ||
44 | } | ||
45 | |||
46 | static u16 sdhci_dove_readw(struct sdhci_host *host, int reg) | 35 | static u16 sdhci_dove_readw(struct sdhci_host *host, int reg) |
47 | { | 36 | { |
48 | u16 ret; | 37 | u16 ret; |
@@ -60,8 +49,6 @@ static u16 sdhci_dove_readw(struct sdhci_host *host, int reg) | |||
60 | 49 | ||
61 | static u32 sdhci_dove_readl(struct sdhci_host *host, int reg) | 50 | static u32 sdhci_dove_readl(struct sdhci_host *host, int reg) |
62 | { | 51 | { |
63 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | ||
64 | struct sdhci_dove_priv *priv = pltfm_host->priv; | ||
65 | u32 ret; | 52 | u32 ret; |
66 | 53 | ||
67 | ret = readl(host->ioaddr + reg); | 54 | ret = readl(host->ioaddr + reg); |
@@ -71,14 +58,6 @@ static u32 sdhci_dove_readl(struct sdhci_host *host, int reg) | |||
71 | /* Mask the support for 3.0V */ | 58 | /* Mask the support for 3.0V */ |
72 | ret &= ~SDHCI_CAN_VDD_300; | 59 | ret &= ~SDHCI_CAN_VDD_300; |
73 | break; | 60 | break; |
74 | case SDHCI_PRESENT_STATE: | ||
75 | if (gpio_is_valid(priv->gpio_cd)) { | ||
76 | if (gpio_get_value(priv->gpio_cd) == 0) | ||
77 | ret |= SDHCI_CARD_PRESENT; | ||
78 | else | ||
79 | ret &= ~SDHCI_CARD_PRESENT; | ||
80 | } | ||
81 | break; | ||
82 | } | 61 | } |
83 | return ret; | 62 | return ret; |
84 | } | 63 | } |
@@ -86,6 +65,10 @@ static u32 sdhci_dove_readl(struct sdhci_host *host, int reg) | |||
86 | static const struct sdhci_ops sdhci_dove_ops = { | 65 | static const struct sdhci_ops sdhci_dove_ops = { |
87 | .read_w = sdhci_dove_readw, | 66 | .read_w = sdhci_dove_readw, |
88 | .read_l = sdhci_dove_readl, | 67 | .read_l = sdhci_dove_readl, |
68 | .set_clock = sdhci_set_clock, | ||
69 | .set_bus_width = sdhci_set_bus_width, | ||
70 | .reset = sdhci_reset, | ||
71 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
89 | }; | 72 | }; |
90 | 73 | ||
91 | static const struct sdhci_pltfm_data sdhci_dove_pdata = { | 74 | static const struct sdhci_pltfm_data sdhci_dove_pdata = { |
@@ -113,28 +96,9 @@ static int sdhci_dove_probe(struct platform_device *pdev) | |||
113 | 96 | ||
114 | priv->clk = devm_clk_get(&pdev->dev, NULL); | 97 | priv->clk = devm_clk_get(&pdev->dev, NULL); |
115 | 98 | ||
116 | if (pdev->dev.of_node) { | ||
117 | priv->gpio_cd = of_get_named_gpio(pdev->dev.of_node, | ||
118 | "cd-gpios", 0); | ||
119 | } else { | ||
120 | priv->gpio_cd = -EINVAL; | ||
121 | } | ||
122 | |||
123 | if (gpio_is_valid(priv->gpio_cd)) { | ||
124 | ret = gpio_request(priv->gpio_cd, "sdhci-cd"); | ||
125 | if (ret) { | ||
126 | dev_err(&pdev->dev, "card detect gpio request failed: %d\n", | ||
127 | ret); | ||
128 | return ret; | ||
129 | } | ||
130 | gpio_direction_input(priv->gpio_cd); | ||
131 | } | ||
132 | |||
133 | host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata, 0); | 99 | host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata, 0); |
134 | if (IS_ERR(host)) { | 100 | if (IS_ERR(host)) |
135 | ret = PTR_ERR(host); | 101 | return PTR_ERR(host); |
136 | goto err_sdhci_pltfm_init; | ||
137 | } | ||
138 | 102 | ||
139 | pltfm_host = sdhci_priv(host); | 103 | pltfm_host = sdhci_priv(host); |
140 | pltfm_host->priv = priv; | 104 | pltfm_host->priv = priv; |
@@ -142,39 +106,20 @@ static int sdhci_dove_probe(struct platform_device *pdev) | |||
142 | if (!IS_ERR(priv->clk)) | 106 | if (!IS_ERR(priv->clk)) |
143 | clk_prepare_enable(priv->clk); | 107 | clk_prepare_enable(priv->clk); |
144 | 108 | ||
145 | sdhci_get_of_property(pdev); | 109 | ret = mmc_of_parse(host->mmc); |
110 | if (ret) | ||
111 | goto err_sdhci_add; | ||
146 | 112 | ||
147 | ret = sdhci_add_host(host); | 113 | ret = sdhci_add_host(host); |
148 | if (ret) | 114 | if (ret) |
149 | goto err_sdhci_add; | 115 | goto err_sdhci_add; |
150 | 116 | ||
151 | /* | ||
152 | * We must request the IRQ after sdhci_add_host(), as the tasklet only | ||
153 | * gets setup in sdhci_add_host() and we oops. | ||
154 | */ | ||
155 | if (gpio_is_valid(priv->gpio_cd)) { | ||
156 | ret = request_irq(gpio_to_irq(priv->gpio_cd), | ||
157 | sdhci_dove_carddetect_irq, | ||
158 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
159 | mmc_hostname(host->mmc), host); | ||
160 | if (ret) { | ||
161 | dev_err(&pdev->dev, "card detect irq request failed: %d\n", | ||
162 | ret); | ||
163 | goto err_request_irq; | ||
164 | } | ||
165 | } | ||
166 | |||
167 | return 0; | 117 | return 0; |
168 | 118 | ||
169 | err_request_irq: | ||
170 | sdhci_remove_host(host, 0); | ||
171 | err_sdhci_add: | 119 | err_sdhci_add: |
172 | if (!IS_ERR(priv->clk)) | 120 | if (!IS_ERR(priv->clk)) |
173 | clk_disable_unprepare(priv->clk); | 121 | clk_disable_unprepare(priv->clk); |
174 | sdhci_pltfm_free(pdev); | 122 | sdhci_pltfm_free(pdev); |
175 | err_sdhci_pltfm_init: | ||
176 | if (gpio_is_valid(priv->gpio_cd)) | ||
177 | gpio_free(priv->gpio_cd); | ||
178 | return ret; | 123 | return ret; |
179 | } | 124 | } |
180 | 125 | ||
@@ -186,11 +131,6 @@ static int sdhci_dove_remove(struct platform_device *pdev) | |||
186 | 131 | ||
187 | sdhci_pltfm_unregister(pdev); | 132 | sdhci_pltfm_unregister(pdev); |
188 | 133 | ||
189 | if (gpio_is_valid(priv->gpio_cd)) { | ||
190 | free_irq(gpio_to_irq(priv->gpio_cd), host); | ||
191 | gpio_free(priv->gpio_cd); | ||
192 | } | ||
193 | |||
194 | if (!IS_ERR(priv->clk)) | 134 | if (!IS_ERR(priv->clk)) |
195 | clk_disable_unprepare(priv->clk); | 135 | clk_disable_unprepare(priv->clk); |
196 | 136 | ||
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index b841bb7cd371..ccec0e32590f 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c | |||
@@ -160,7 +160,6 @@ struct pltfm_imx_data { | |||
160 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | 160 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ |
161 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | 161 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ |
162 | } multiblock_status; | 162 | } multiblock_status; |
163 | u32 uhs_mode; | ||
164 | u32 is_ddr; | 163 | u32 is_ddr; |
165 | }; | 164 | }; |
166 | 165 | ||
@@ -382,7 +381,6 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg) | |||
382 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | 381 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) |
383 | ret |= SDHCI_CTRL_TUNED_CLK; | 382 | ret |= SDHCI_CTRL_TUNED_CLK; |
384 | 383 | ||
385 | ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); | ||
386 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | 384 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
387 | 385 | ||
388 | return ret; | 386 | return ret; |
@@ -429,7 +427,6 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |||
429 | else | 427 | else |
430 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | 428 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; |
431 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | 429 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
432 | imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; | ||
433 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { | 430 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
434 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | 431 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
435 | if (val & SDHCI_CTRL_TUNED_CLK) | 432 | if (val & SDHCI_CTRL_TUNED_CLK) |
@@ -600,12 +597,14 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, | |||
600 | u32 temp, val; | 597 | u32 temp, val; |
601 | 598 | ||
602 | if (clock == 0) { | 599 | if (clock == 0) { |
600 | host->mmc->actual_clock = 0; | ||
601 | |||
603 | if (esdhc_is_usdhc(imx_data)) { | 602 | if (esdhc_is_usdhc(imx_data)) { |
604 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | 603 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
605 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | 604 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, |
606 | host->ioaddr + ESDHC_VENDOR_SPEC); | 605 | host->ioaddr + ESDHC_VENDOR_SPEC); |
607 | } | 606 | } |
608 | goto out; | 607 | return; |
609 | } | 608 | } |
610 | 609 | ||
611 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) | 610 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
@@ -645,8 +644,6 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, | |||
645 | } | 644 | } |
646 | 645 | ||
647 | mdelay(1); | 646 | mdelay(1); |
648 | out: | ||
649 | host->clock = clock; | ||
650 | } | 647 | } |
651 | 648 | ||
652 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) | 649 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
@@ -668,7 +665,7 @@ static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) | |||
668 | return -ENOSYS; | 665 | return -ENOSYS; |
669 | } | 666 | } |
670 | 667 | ||
671 | static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) | 668 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
672 | { | 669 | { |
673 | u32 ctrl; | 670 | u32 ctrl; |
674 | 671 | ||
@@ -686,8 +683,6 @@ static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) | |||
686 | 683 | ||
687 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | 684 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, |
688 | SDHCI_HOST_CONTROL); | 685 | SDHCI_HOST_CONTROL); |
689 | |||
690 | return 0; | ||
691 | } | 686 | } |
692 | 687 | ||
693 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) | 688 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
@@ -697,6 +692,7 @@ static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) | |||
697 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | 692 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ |
698 | mdelay(1); | 693 | mdelay(1); |
699 | 694 | ||
695 | /* This is balanced by the runtime put in sdhci_tasklet_finish */ | ||
700 | pm_runtime_get_sync(host->mmc->parent); | 696 | pm_runtime_get_sync(host->mmc->parent); |
701 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | 697 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); |
702 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | 698 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | |
@@ -713,13 +709,12 @@ static void esdhc_request_done(struct mmc_request *mrq) | |||
713 | complete(&mrq->completion); | 709 | complete(&mrq->completion); |
714 | } | 710 | } |
715 | 711 | ||
716 | static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) | 712 | static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode, |
713 | struct scatterlist *sg) | ||
717 | { | 714 | { |
718 | struct mmc_command cmd = {0}; | 715 | struct mmc_command cmd = {0}; |
719 | struct mmc_request mrq = {NULL}; | 716 | struct mmc_request mrq = {NULL}; |
720 | struct mmc_data data = {0}; | 717 | struct mmc_data data = {0}; |
721 | struct scatterlist sg; | ||
722 | char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; | ||
723 | 718 | ||
724 | cmd.opcode = opcode; | 719 | cmd.opcode = opcode; |
725 | cmd.arg = 0; | 720 | cmd.arg = 0; |
@@ -728,11 +723,9 @@ static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) | |||
728 | data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; | 723 | data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; |
729 | data.blocks = 1; | 724 | data.blocks = 1; |
730 | data.flags = MMC_DATA_READ; | 725 | data.flags = MMC_DATA_READ; |
731 | data.sg = &sg; | 726 | data.sg = sg; |
732 | data.sg_len = 1; | 727 | data.sg_len = 1; |
733 | 728 | ||
734 | sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); | ||
735 | |||
736 | mrq.cmd = &cmd; | 729 | mrq.cmd = &cmd; |
737 | mrq.cmd->mrq = &mrq; | 730 | mrq.cmd->mrq = &mrq; |
738 | mrq.data = &data; | 731 | mrq.data = &data; |
@@ -742,14 +735,12 @@ static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) | |||
742 | mrq.done = esdhc_request_done; | 735 | mrq.done = esdhc_request_done; |
743 | init_completion(&(mrq.completion)); | 736 | init_completion(&(mrq.completion)); |
744 | 737 | ||
745 | disable_irq(host->irq); | 738 | spin_lock_irq(&host->lock); |
746 | spin_lock(&host->lock); | ||
747 | host->mrq = &mrq; | 739 | host->mrq = &mrq; |
748 | 740 | ||
749 | sdhci_send_command(host, mrq.cmd); | 741 | sdhci_send_command(host, mrq.cmd); |
750 | 742 | ||
751 | spin_unlock(&host->lock); | 743 | spin_unlock_irq(&host->lock); |
752 | enable_irq(host->irq); | ||
753 | 744 | ||
754 | wait_for_completion(&mrq.completion); | 745 | wait_for_completion(&mrq.completion); |
755 | 746 | ||
@@ -772,13 +763,21 @@ static void esdhc_post_tuning(struct sdhci_host *host) | |||
772 | 763 | ||
773 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | 764 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) |
774 | { | 765 | { |
766 | struct scatterlist sg; | ||
767 | char *tuning_pattern; | ||
775 | int min, max, avg, ret; | 768 | int min, max, avg, ret; |
776 | 769 | ||
770 | tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL); | ||
771 | if (!tuning_pattern) | ||
772 | return -ENOMEM; | ||
773 | |||
774 | sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN); | ||
775 | |||
777 | /* find the mininum delay first which can pass tuning */ | 776 | /* find the mininum delay first which can pass tuning */ |
778 | min = ESDHC_TUNE_CTRL_MIN; | 777 | min = ESDHC_TUNE_CTRL_MIN; |
779 | while (min < ESDHC_TUNE_CTRL_MAX) { | 778 | while (min < ESDHC_TUNE_CTRL_MAX) { |
780 | esdhc_prepare_tuning(host, min); | 779 | esdhc_prepare_tuning(host, min); |
781 | if (!esdhc_send_tuning_cmd(host, opcode)) | 780 | if (!esdhc_send_tuning_cmd(host, opcode, &sg)) |
782 | break; | 781 | break; |
783 | min += ESDHC_TUNE_CTRL_STEP; | 782 | min += ESDHC_TUNE_CTRL_STEP; |
784 | } | 783 | } |
@@ -787,7 +786,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |||
787 | max = min + ESDHC_TUNE_CTRL_STEP; | 786 | max = min + ESDHC_TUNE_CTRL_STEP; |
788 | while (max < ESDHC_TUNE_CTRL_MAX) { | 787 | while (max < ESDHC_TUNE_CTRL_MAX) { |
789 | esdhc_prepare_tuning(host, max); | 788 | esdhc_prepare_tuning(host, max); |
790 | if (esdhc_send_tuning_cmd(host, opcode)) { | 789 | if (esdhc_send_tuning_cmd(host, opcode, &sg)) { |
791 | max -= ESDHC_TUNE_CTRL_STEP; | 790 | max -= ESDHC_TUNE_CTRL_STEP; |
792 | break; | 791 | break; |
793 | } | 792 | } |
@@ -797,9 +796,11 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |||
797 | /* use average delay to get the best timing */ | 796 | /* use average delay to get the best timing */ |
798 | avg = (min + max) / 2; | 797 | avg = (min + max) / 2; |
799 | esdhc_prepare_tuning(host, avg); | 798 | esdhc_prepare_tuning(host, avg); |
800 | ret = esdhc_send_tuning_cmd(host, opcode); | 799 | ret = esdhc_send_tuning_cmd(host, opcode, &sg); |
801 | esdhc_post_tuning(host); | 800 | esdhc_post_tuning(host); |
802 | 801 | ||
802 | kfree(tuning_pattern); | ||
803 | |||
803 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | 804 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", |
804 | ret ? "failed" : "passed", avg, ret); | 805 | ret ? "failed" : "passed", avg, ret); |
805 | 806 | ||
@@ -837,28 +838,21 @@ static int esdhc_change_pinstate(struct sdhci_host *host, | |||
837 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | 838 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); |
838 | } | 839 | } |
839 | 840 | ||
840 | static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | 841 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
841 | { | 842 | { |
842 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | 843 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
843 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | 844 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
844 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | 845 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
845 | 846 | ||
846 | switch (uhs) { | 847 | switch (timing) { |
847 | case MMC_TIMING_UHS_SDR12: | 848 | case MMC_TIMING_UHS_SDR12: |
848 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; | ||
849 | break; | ||
850 | case MMC_TIMING_UHS_SDR25: | 849 | case MMC_TIMING_UHS_SDR25: |
851 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; | ||
852 | break; | ||
853 | case MMC_TIMING_UHS_SDR50: | 850 | case MMC_TIMING_UHS_SDR50: |
854 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; | ||
855 | break; | ||
856 | case MMC_TIMING_UHS_SDR104: | 851 | case MMC_TIMING_UHS_SDR104: |
857 | case MMC_TIMING_MMC_HS200: | 852 | case MMC_TIMING_MMC_HS200: |
858 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; | ||
859 | break; | 853 | break; |
860 | case MMC_TIMING_UHS_DDR50: | 854 | case MMC_TIMING_UHS_DDR50: |
861 | imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; | 855 | case MMC_TIMING_MMC_DDR52: |
862 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | | 856 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
863 | ESDHC_MIX_CTRL_DDREN, | 857 | ESDHC_MIX_CTRL_DDREN, |
864 | host->ioaddr + ESDHC_MIX_CTRL); | 858 | host->ioaddr + ESDHC_MIX_CTRL); |
@@ -875,7 +869,15 @@ static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | |||
875 | break; | 869 | break; |
876 | } | 870 | } |
877 | 871 | ||
878 | return esdhc_change_pinstate(host, uhs); | 872 | esdhc_change_pinstate(host, timing); |
873 | } | ||
874 | |||
875 | static void esdhc_reset(struct sdhci_host *host, u8 mask) | ||
876 | { | ||
877 | sdhci_reset(host, mask); | ||
878 | |||
879 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | ||
880 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
879 | } | 881 | } |
880 | 882 | ||
881 | static struct sdhci_ops sdhci_esdhc_ops = { | 883 | static struct sdhci_ops sdhci_esdhc_ops = { |
@@ -888,8 +890,9 @@ static struct sdhci_ops sdhci_esdhc_ops = { | |||
888 | .get_max_clock = esdhc_pltfm_get_max_clock, | 890 | .get_max_clock = esdhc_pltfm_get_max_clock, |
889 | .get_min_clock = esdhc_pltfm_get_min_clock, | 891 | .get_min_clock = esdhc_pltfm_get_min_clock, |
890 | .get_ro = esdhc_pltfm_get_ro, | 892 | .get_ro = esdhc_pltfm_get_ro, |
891 | .platform_bus_width = esdhc_pltfm_bus_width, | 893 | .set_bus_width = esdhc_pltfm_set_bus_width, |
892 | .set_uhs_signaling = esdhc_set_uhs_signaling, | 894 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
895 | .reset = esdhc_reset, | ||
893 | }; | 896 | }; |
894 | 897 | ||
895 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { | 898 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
@@ -1170,8 +1173,10 @@ static int sdhci_esdhc_runtime_suspend(struct device *dev) | |||
1170 | 1173 | ||
1171 | ret = sdhci_runtime_suspend_host(host); | 1174 | ret = sdhci_runtime_suspend_host(host); |
1172 | 1175 | ||
1173 | clk_disable_unprepare(imx_data->clk_per); | 1176 | if (!sdhci_sdio_irq_enabled(host)) { |
1174 | clk_disable_unprepare(imx_data->clk_ipg); | 1177 | clk_disable_unprepare(imx_data->clk_per); |
1178 | clk_disable_unprepare(imx_data->clk_ipg); | ||
1179 | } | ||
1175 | clk_disable_unprepare(imx_data->clk_ahb); | 1180 | clk_disable_unprepare(imx_data->clk_ahb); |
1176 | 1181 | ||
1177 | return ret; | 1182 | return ret; |
@@ -1183,8 +1188,10 @@ static int sdhci_esdhc_runtime_resume(struct device *dev) | |||
1183 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | 1188 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1184 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | 1189 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
1185 | 1190 | ||
1186 | clk_prepare_enable(imx_data->clk_per); | 1191 | if (!sdhci_sdio_irq_enabled(host)) { |
1187 | clk_prepare_enable(imx_data->clk_ipg); | 1192 | clk_prepare_enable(imx_data->clk_per); |
1193 | clk_prepare_enable(imx_data->clk_ipg); | ||
1194 | } | ||
1188 | clk_prepare_enable(imx_data->clk_ahb); | 1195 | clk_prepare_enable(imx_data->clk_ahb); |
1189 | 1196 | ||
1190 | return sdhci_runtime_resume_host(host); | 1197 | return sdhci_runtime_resume_host(host); |
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h index a7d9f95a7b03..3497cfaf683c 100644 --- a/drivers/mmc/host/sdhci-esdhc.h +++ b/drivers/mmc/host/sdhci-esdhc.h | |||
@@ -20,10 +20,8 @@ | |||
20 | 20 | ||
21 | #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ | 21 | #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ |
22 | SDHCI_QUIRK_NO_BUSY_IRQ | \ | 22 | SDHCI_QUIRK_NO_BUSY_IRQ | \ |
23 | SDHCI_QUIRK_NONSTANDARD_CLOCK | \ | ||
24 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ | 23 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ |
25 | SDHCI_QUIRK_PIO_NEEDS_DELAY | \ | 24 | SDHCI_QUIRK_PIO_NEEDS_DELAY) |
26 | SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | ||
27 | 25 | ||
28 | #define ESDHC_SYSTEM_CONTROL 0x2c | 26 | #define ESDHC_SYSTEM_CONTROL 0x2c |
29 | #define ESDHC_CLOCK_MASK 0x0000fff0 | 27 | #define ESDHC_CLOCK_MASK 0x0000fff0 |
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index f7c7cf62437d..5bd1092310f2 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c | |||
@@ -52,8 +52,12 @@ static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) | |||
52 | } | 52 | } |
53 | 53 | ||
54 | static struct sdhci_ops sdhci_arasan_ops = { | 54 | static struct sdhci_ops sdhci_arasan_ops = { |
55 | .set_clock = sdhci_set_clock, | ||
55 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | 56 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
56 | .get_timeout_clock = sdhci_arasan_get_timeout_clock, | 57 | .get_timeout_clock = sdhci_arasan_get_timeout_clock, |
58 | .set_bus_width = sdhci_set_bus_width, | ||
59 | .reset = sdhci_reset, | ||
60 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
57 | }; | 61 | }; |
58 | 62 | ||
59 | static struct sdhci_pltfm_data sdhci_arasan_pdata = { | 63 | static struct sdhci_pltfm_data sdhci_arasan_pdata = { |
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 0b249970b119..8be4dcfb49a0 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c | |||
@@ -199,13 +199,14 @@ static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) | |||
199 | 199 | ||
200 | static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) | 200 | static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) |
201 | { | 201 | { |
202 | |||
203 | int pre_div = 2; | 202 | int pre_div = 2; |
204 | int div = 1; | 203 | int div = 1; |
205 | u32 temp; | 204 | u32 temp; |
206 | 205 | ||
206 | host->mmc->actual_clock = 0; | ||
207 | |||
207 | if (clock == 0) | 208 | if (clock == 0) |
208 | goto out; | 209 | return; |
209 | 210 | ||
210 | /* Workaround to reduce the clock frequency for p1010 esdhc */ | 211 | /* Workaround to reduce the clock frequency for p1010 esdhc */ |
211 | if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { | 212 | if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { |
@@ -238,24 +239,8 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) | |||
238 | | (pre_div << ESDHC_PREDIV_SHIFT)); | 239 | | (pre_div << ESDHC_PREDIV_SHIFT)); |
239 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | 240 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
240 | mdelay(1); | 241 | mdelay(1); |
241 | out: | ||
242 | host->clock = clock; | ||
243 | } | ||
244 | |||
245 | #ifdef CONFIG_PM | ||
246 | static u32 esdhc_proctl; | ||
247 | static void esdhc_of_suspend(struct sdhci_host *host) | ||
248 | { | ||
249 | esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL); | ||
250 | } | 242 | } |
251 | 243 | ||
252 | static void esdhc_of_resume(struct sdhci_host *host) | ||
253 | { | ||
254 | esdhc_of_enable_dma(host); | ||
255 | sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); | ||
256 | } | ||
257 | #endif | ||
258 | |||
259 | static void esdhc_of_platform_init(struct sdhci_host *host) | 244 | static void esdhc_of_platform_init(struct sdhci_host *host) |
260 | { | 245 | { |
261 | u32 vvn; | 246 | u32 vvn; |
@@ -269,7 +254,7 @@ static void esdhc_of_platform_init(struct sdhci_host *host) | |||
269 | host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; | 254 | host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; |
270 | } | 255 | } |
271 | 256 | ||
272 | static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) | 257 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
273 | { | 258 | { |
274 | u32 ctrl; | 259 | u32 ctrl; |
275 | 260 | ||
@@ -289,8 +274,6 @@ static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) | |||
289 | 274 | ||
290 | clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL, | 275 | clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL, |
291 | ESDHC_CTRL_BUSWIDTH_MASK, ctrl); | 276 | ESDHC_CTRL_BUSWIDTH_MASK, ctrl); |
292 | |||
293 | return 0; | ||
294 | } | 277 | } |
295 | 278 | ||
296 | static const struct sdhci_ops sdhci_esdhc_ops = { | 279 | static const struct sdhci_ops sdhci_esdhc_ops = { |
@@ -305,13 +288,46 @@ static const struct sdhci_ops sdhci_esdhc_ops = { | |||
305 | .get_max_clock = esdhc_of_get_max_clock, | 288 | .get_max_clock = esdhc_of_get_max_clock, |
306 | .get_min_clock = esdhc_of_get_min_clock, | 289 | .get_min_clock = esdhc_of_get_min_clock, |
307 | .platform_init = esdhc_of_platform_init, | 290 | .platform_init = esdhc_of_platform_init, |
308 | #ifdef CONFIG_PM | ||
309 | .platform_suspend = esdhc_of_suspend, | ||
310 | .platform_resume = esdhc_of_resume, | ||
311 | #endif | ||
312 | .adma_workaround = esdhci_of_adma_workaround, | 291 | .adma_workaround = esdhci_of_adma_workaround, |
313 | .platform_bus_width = esdhc_pltfm_bus_width, | 292 | .set_bus_width = esdhc_pltfm_set_bus_width, |
293 | .reset = sdhci_reset, | ||
294 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
295 | }; | ||
296 | |||
297 | #ifdef CONFIG_PM | ||
298 | |||
299 | static u32 esdhc_proctl; | ||
300 | static int esdhc_of_suspend(struct device *dev) | ||
301 | { | ||
302 | struct sdhci_host *host = dev_get_drvdata(dev); | ||
303 | |||
304 | esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL); | ||
305 | |||
306 | return sdhci_suspend_host(host); | ||
307 | } | ||
308 | |||
309 | static int esdhc_of_resume(struct device *dev) | ||
310 | { | ||
311 | struct sdhci_host *host = dev_get_drvdata(dev); | ||
312 | int ret = sdhci_resume_host(host); | ||
313 | |||
314 | if (ret == 0) { | ||
315 | /* Isn't this already done by sdhci_resume_host() ? --rmk */ | ||
316 | esdhc_of_enable_dma(host); | ||
317 | sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); | ||
318 | } | ||
319 | |||
320 | return ret; | ||
321 | } | ||
322 | |||
323 | static const struct dev_pm_ops esdhc_pmops = { | ||
324 | .suspend = esdhc_of_suspend, | ||
325 | .resume = esdhc_of_resume, | ||
314 | }; | 326 | }; |
327 | #define ESDHC_PMOPS (&esdhc_pmops) | ||
328 | #else | ||
329 | #define ESDHC_PMOPS NULL | ||
330 | #endif | ||
315 | 331 | ||
316 | static const struct sdhci_pltfm_data sdhci_esdhc_pdata = { | 332 | static const struct sdhci_pltfm_data sdhci_esdhc_pdata = { |
317 | /* | 333 | /* |
@@ -374,7 +390,7 @@ static struct platform_driver sdhci_esdhc_driver = { | |||
374 | .name = "sdhci-esdhc", | 390 | .name = "sdhci-esdhc", |
375 | .owner = THIS_MODULE, | 391 | .owner = THIS_MODULE, |
376 | .of_match_table = sdhci_esdhc_of_match, | 392 | .of_match_table = sdhci_esdhc_of_match, |
377 | .pm = SDHCI_PLTFM_PMOPS, | 393 | .pm = ESDHC_PMOPS, |
378 | }, | 394 | }, |
379 | .probe = sdhci_esdhc_probe, | 395 | .probe = sdhci_esdhc_probe, |
380 | .remove = sdhci_esdhc_remove, | 396 | .remove = sdhci_esdhc_remove, |
diff --git a/drivers/mmc/host/sdhci-of-hlwd.c b/drivers/mmc/host/sdhci-of-hlwd.c index 57c514a81ca5..b341661369a2 100644 --- a/drivers/mmc/host/sdhci-of-hlwd.c +++ b/drivers/mmc/host/sdhci-of-hlwd.c | |||
@@ -58,6 +58,10 @@ static const struct sdhci_ops sdhci_hlwd_ops = { | |||
58 | .write_l = sdhci_hlwd_writel, | 58 | .write_l = sdhci_hlwd_writel, |
59 | .write_w = sdhci_hlwd_writew, | 59 | .write_w = sdhci_hlwd_writew, |
60 | .write_b = sdhci_hlwd_writeb, | 60 | .write_b = sdhci_hlwd_writeb, |
61 | .set_clock = sdhci_set_clock, | ||
62 | .set_bus_width = sdhci_set_bus_width, | ||
63 | .reset = sdhci_reset, | ||
64 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
61 | }; | 65 | }; |
62 | 66 | ||
63 | static const struct sdhci_pltfm_data sdhci_hlwd_pdata = { | 67 | static const struct sdhci_pltfm_data sdhci_hlwd_pdata = { |
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index f49666bcc52a..5670e381b0cf 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c | |||
@@ -21,6 +21,45 @@ | |||
21 | #include "sdhci-pci.h" | 21 | #include "sdhci-pci.h" |
22 | #include "sdhci-pci-o2micro.h" | 22 | #include "sdhci-pci-o2micro.h" |
23 | 23 | ||
24 | static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) | ||
25 | { | ||
26 | u32 scratch_32; | ||
27 | pci_read_config_dword(chip->pdev, | ||
28 | O2_SD_PLL_SETTING, &scratch_32); | ||
29 | |||
30 | scratch_32 &= 0x0000FFFF; | ||
31 | scratch_32 |= value; | ||
32 | |||
33 | pci_write_config_dword(chip->pdev, | ||
34 | O2_SD_PLL_SETTING, scratch_32); | ||
35 | } | ||
36 | |||
37 | static void o2_pci_led_enable(struct sdhci_pci_chip *chip) | ||
38 | { | ||
39 | int ret; | ||
40 | u32 scratch_32; | ||
41 | |||
42 | /* Set led of SD host function enable */ | ||
43 | ret = pci_read_config_dword(chip->pdev, | ||
44 | O2_SD_FUNC_REG0, &scratch_32); | ||
45 | if (ret) | ||
46 | return; | ||
47 | |||
48 | scratch_32 &= ~O2_SD_FREG0_LEDOFF; | ||
49 | pci_write_config_dword(chip->pdev, | ||
50 | O2_SD_FUNC_REG0, scratch_32); | ||
51 | |||
52 | ret = pci_read_config_dword(chip->pdev, | ||
53 | O2_SD_TEST_REG, &scratch_32); | ||
54 | if (ret) | ||
55 | return; | ||
56 | |||
57 | scratch_32 |= O2_SD_LED_ENABLE; | ||
58 | pci_write_config_dword(chip->pdev, | ||
59 | O2_SD_TEST_REG, scratch_32); | ||
60 | |||
61 | } | ||
62 | |||
24 | void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) | 63 | void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) |
25 | { | 64 | { |
26 | u32 scratch_32; | 65 | u32 scratch_32; |
@@ -216,6 +255,40 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) | |||
216 | scratch &= 0x7f; | 255 | scratch &= 0x7f; |
217 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | 256 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); |
218 | 257 | ||
258 | /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ | ||
259 | if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { | ||
260 | ret = pci_read_config_dword(chip->pdev, | ||
261 | O2_SD_FUNC_REG0, | ||
262 | &scratch_32); | ||
263 | scratch_32 = ((scratch_32 & 0xFF000000) >> 24); | ||
264 | |||
265 | /* Check Whether subId is 0x11 or 0x12 */ | ||
266 | if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { | ||
267 | scratch_32 = 0x2c280000; | ||
268 | |||
269 | /* Set Base Clock to 208MZ */ | ||
270 | o2_pci_set_baseclk(chip, scratch_32); | ||
271 | ret = pci_read_config_dword(chip->pdev, | ||
272 | O2_SD_FUNC_REG4, | ||
273 | &scratch_32); | ||
274 | |||
275 | /* Enable Base Clk setting change */ | ||
276 | scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; | ||
277 | pci_write_config_dword(chip->pdev, | ||
278 | O2_SD_FUNC_REG4, | ||
279 | scratch_32); | ||
280 | |||
281 | /* Set Tuning Window to 4 */ | ||
282 | pci_write_config_byte(chip->pdev, | ||
283 | O2_SD_TUNING_CTRL, 0x44); | ||
284 | |||
285 | break; | ||
286 | } | ||
287 | } | ||
288 | |||
289 | /* Enable 8520 led function */ | ||
290 | o2_pci_led_enable(chip); | ||
291 | |||
219 | /* Set timeout CLK */ | 292 | /* Set timeout CLK */ |
220 | ret = pci_read_config_dword(chip->pdev, | 293 | ret = pci_read_config_dword(chip->pdev, |
221 | O2_SD_CLK_SETTING, &scratch_32); | 294 | O2_SD_CLK_SETTING, &scratch_32); |
@@ -276,7 +349,7 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) | |||
276 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | 349 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); |
277 | 350 | ||
278 | ret = pci_read_config_dword(chip->pdev, | 351 | ret = pci_read_config_dword(chip->pdev, |
279 | O2_SD_FUNC_REG0, &scratch_32); | 352 | O2_SD_PLL_SETTING, &scratch_32); |
280 | 353 | ||
281 | if ((scratch_32 & 0xff000000) == 0x01000000) { | 354 | if ((scratch_32 & 0xff000000) == 0x01000000) { |
282 | scratch_32 &= 0x0000FFFF; | 355 | scratch_32 &= 0x0000FFFF; |
@@ -299,6 +372,9 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) | |||
299 | O2_SD_FUNC_REG4, scratch_32); | 372 | O2_SD_FUNC_REG4, scratch_32); |
300 | } | 373 | } |
301 | 374 | ||
375 | /* Set Tuning Windows to 5 */ | ||
376 | pci_write_config_byte(chip->pdev, | ||
377 | O2_SD_TUNING_CTRL, 0x55); | ||
302 | /* Lock WP */ | 378 | /* Lock WP */ |
303 | ret = pci_read_config_byte(chip->pdev, | 379 | ret = pci_read_config_byte(chip->pdev, |
304 | O2_SD_LOCK_WP, &scratch); | 380 | O2_SD_LOCK_WP, &scratch); |
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.h b/drivers/mmc/host/sdhci-pci-o2micro.h index dbec4c933488..f7ffc908d9a0 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.h +++ b/drivers/mmc/host/sdhci-pci-o2micro.h | |||
@@ -57,6 +57,9 @@ | |||
57 | #define O2_SD_UHS2_L1_CTRL 0x35C | 57 | #define O2_SD_UHS2_L1_CTRL 0x35C |
58 | #define O2_SD_FUNC_REG3 0x3E0 | 58 | #define O2_SD_FUNC_REG3 0x3E0 |
59 | #define O2_SD_FUNC_REG4 0x3E4 | 59 | #define O2_SD_FUNC_REG4 0x3E4 |
60 | #define O2_SD_LED_ENABLE BIT(6) | ||
61 | #define O2_SD_FREG0_LEDOFF BIT(13) | ||
62 | #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) | ||
60 | 63 | ||
61 | #define O2_SD_VENDOR_SETTING 0x110 | 64 | #define O2_SD_VENDOR_SETTING 0x110 |
62 | #define O2_SD_VENDOR_SETTING2 0x1C8 | 65 | #define O2_SD_VENDOR_SETTING2 0x1C8 |
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index fdc612120362..52c42fcc284c 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c | |||
@@ -1031,7 +1031,7 @@ static int sdhci_pci_enable_dma(struct sdhci_host *host) | |||
1031 | return 0; | 1031 | return 0; |
1032 | } | 1032 | } |
1033 | 1033 | ||
1034 | static int sdhci_pci_bus_width(struct sdhci_host *host, int width) | 1034 | static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) |
1035 | { | 1035 | { |
1036 | u8 ctrl; | 1036 | u8 ctrl; |
1037 | 1037 | ||
@@ -1052,8 +1052,6 @@ static int sdhci_pci_bus_width(struct sdhci_host *host, int width) | |||
1052 | } | 1052 | } |
1053 | 1053 | ||
1054 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | 1054 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
1055 | |||
1056 | return 0; | ||
1057 | } | 1055 | } |
1058 | 1056 | ||
1059 | static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) | 1057 | static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) |
@@ -1080,8 +1078,11 @@ static void sdhci_pci_hw_reset(struct sdhci_host *host) | |||
1080 | } | 1078 | } |
1081 | 1079 | ||
1082 | static const struct sdhci_ops sdhci_pci_ops = { | 1080 | static const struct sdhci_ops sdhci_pci_ops = { |
1081 | .set_clock = sdhci_set_clock, | ||
1083 | .enable_dma = sdhci_pci_enable_dma, | 1082 | .enable_dma = sdhci_pci_enable_dma, |
1084 | .platform_bus_width = sdhci_pci_bus_width, | 1083 | .set_bus_width = sdhci_pci_set_bus_width, |
1084 | .reset = sdhci_reset, | ||
1085 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
1085 | .hw_reset = sdhci_pci_hw_reset, | 1086 | .hw_reset = sdhci_pci_hw_reset, |
1086 | }; | 1087 | }; |
1087 | 1088 | ||
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index bef250e95418..7e834fb78f42 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c | |||
@@ -45,6 +45,10 @@ unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host) | |||
45 | EXPORT_SYMBOL_GPL(sdhci_pltfm_clk_get_max_clock); | 45 | EXPORT_SYMBOL_GPL(sdhci_pltfm_clk_get_max_clock); |
46 | 46 | ||
47 | static const struct sdhci_ops sdhci_pltfm_ops = { | 47 | static const struct sdhci_ops sdhci_pltfm_ops = { |
48 | .set_clock = sdhci_set_clock, | ||
49 | .set_bus_width = sdhci_set_bus_width, | ||
50 | .reset = sdhci_reset, | ||
51 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
48 | }; | 52 | }; |
49 | 53 | ||
50 | #ifdef CONFIG_OF | 54 | #ifdef CONFIG_OF |
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index d51e061ec576..3c0f3c0a1cc8 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c | |||
@@ -51,11 +51,13 @@ | |||
51 | #define MMC_CARD 0x1000 | 51 | #define MMC_CARD 0x1000 |
52 | #define MMC_WIDTH 0x0100 | 52 | #define MMC_WIDTH 0x0100 |
53 | 53 | ||
54 | static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask) | 54 | static void pxav2_reset(struct sdhci_host *host, u8 mask) |
55 | { | 55 | { |
56 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); | 56 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); |
57 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | 57 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; |
58 | 58 | ||
59 | sdhci_reset(host, mask); | ||
60 | |||
59 | if (mask == SDHCI_RESET_ALL) { | 61 | if (mask == SDHCI_RESET_ALL) { |
60 | u16 tmp = 0; | 62 | u16 tmp = 0; |
61 | 63 | ||
@@ -88,7 +90,7 @@ static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask) | |||
88 | } | 90 | } |
89 | } | 91 | } |
90 | 92 | ||
91 | static int pxav2_mmc_set_width(struct sdhci_host *host, int width) | 93 | static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) |
92 | { | 94 | { |
93 | u8 ctrl; | 95 | u8 ctrl; |
94 | u16 tmp; | 96 | u16 tmp; |
@@ -107,14 +109,14 @@ static int pxav2_mmc_set_width(struct sdhci_host *host, int width) | |||
107 | } | 109 | } |
108 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | 110 | writew(tmp, host->ioaddr + SD_CE_ATA_2); |
109 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | 111 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); |
110 | |||
111 | return 0; | ||
112 | } | 112 | } |
113 | 113 | ||
114 | static const struct sdhci_ops pxav2_sdhci_ops = { | 114 | static const struct sdhci_ops pxav2_sdhci_ops = { |
115 | .set_clock = sdhci_set_clock, | ||
115 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | 116 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
116 | .platform_reset_exit = pxav2_set_private_registers, | 117 | .set_bus_width = pxav2_mmc_set_bus_width, |
117 | .platform_bus_width = pxav2_mmc_set_width, | 118 | .reset = pxav2_reset, |
119 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
118 | }; | 120 | }; |
119 | 121 | ||
120 | #ifdef CONFIG_OF | 122 | #ifdef CONFIG_OF |
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 2fd73b38c303..f4f128947561 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c | |||
@@ -112,11 +112,13 @@ static int mv_conf_mbus_windows(struct platform_device *pdev, | |||
112 | return 0; | 112 | return 0; |
113 | } | 113 | } |
114 | 114 | ||
115 | static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask) | 115 | static void pxav3_reset(struct sdhci_host *host, u8 mask) |
116 | { | 116 | { |
117 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); | 117 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); |
118 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | 118 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; |
119 | 119 | ||
120 | sdhci_reset(host, mask); | ||
121 | |||
120 | if (mask == SDHCI_RESET_ALL) { | 122 | if (mask == SDHCI_RESET_ALL) { |
121 | /* | 123 | /* |
122 | * tune timing of read data/command when crc error happen | 124 | * tune timing of read data/command when crc error happen |
@@ -184,7 +186,7 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) | |||
184 | pxa->power_mode = power_mode; | 186 | pxa->power_mode = power_mode; |
185 | } | 187 | } |
186 | 188 | ||
187 | static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | 189 | static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) |
188 | { | 190 | { |
189 | u16 ctrl_2; | 191 | u16 ctrl_2; |
190 | 192 | ||
@@ -218,15 +220,16 @@ static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | |||
218 | dev_dbg(mmc_dev(host->mmc), | 220 | dev_dbg(mmc_dev(host->mmc), |
219 | "%s uhs = %d, ctrl_2 = %04X\n", | 221 | "%s uhs = %d, ctrl_2 = %04X\n", |
220 | __func__, uhs, ctrl_2); | 222 | __func__, uhs, ctrl_2); |
221 | |||
222 | return 0; | ||
223 | } | 223 | } |
224 | 224 | ||
225 | static const struct sdhci_ops pxav3_sdhci_ops = { | 225 | static const struct sdhci_ops pxav3_sdhci_ops = { |
226 | .platform_reset_exit = pxav3_set_private_registers, | 226 | .set_clock = sdhci_set_clock, |
227 | .set_uhs_signaling = pxav3_set_uhs_signaling, | 227 | .set_uhs_signaling = pxav3_set_uhs_signaling, |
228 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, | 228 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, |
229 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | 229 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
230 | .set_bus_width = sdhci_set_bus_width, | ||
231 | .reset = pxav3_reset, | ||
232 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
230 | }; | 233 | }; |
231 | 234 | ||
232 | static struct sdhci_pltfm_data sdhci_pxav3_pdata = { | 235 | static struct sdhci_pltfm_data sdhci_pxav3_pdata = { |
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index d61eb5a70833..fa5954a05449 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c | |||
@@ -33,9 +33,6 @@ | |||
33 | 33 | ||
34 | #define MAX_BUS_CLK (4) | 34 | #define MAX_BUS_CLK (4) |
35 | 35 | ||
36 | /* Number of gpio's used is max data bus width + command and clock lines */ | ||
37 | #define NUM_GPIOS(x) (x + 2) | ||
38 | |||
39 | /** | 36 | /** |
40 | * struct sdhci_s3c - S3C SDHCI instance | 37 | * struct sdhci_s3c - S3C SDHCI instance |
41 | * @host: The SDHCI host created | 38 | * @host: The SDHCI host created |
@@ -58,6 +55,8 @@ struct sdhci_s3c { | |||
58 | struct clk *clk_io; | 55 | struct clk *clk_io; |
59 | struct clk *clk_bus[MAX_BUS_CLK]; | 56 | struct clk *clk_bus[MAX_BUS_CLK]; |
60 | unsigned long clk_rates[MAX_BUS_CLK]; | 57 | unsigned long clk_rates[MAX_BUS_CLK]; |
58 | |||
59 | bool no_divider; | ||
61 | }; | 60 | }; |
62 | 61 | ||
63 | /** | 62 | /** |
@@ -70,6 +69,7 @@ struct sdhci_s3c { | |||
70 | */ | 69 | */ |
71 | struct sdhci_s3c_drv_data { | 70 | struct sdhci_s3c_drv_data { |
72 | unsigned int sdhci_quirks; | 71 | unsigned int sdhci_quirks; |
72 | bool no_divider; | ||
73 | }; | 73 | }; |
74 | 74 | ||
75 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) | 75 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
@@ -119,7 +119,7 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |||
119 | * If controller uses a non-standard clock division, find the best clock | 119 | * If controller uses a non-standard clock division, find the best clock |
120 | * speed possible with selected clock source and skip the division. | 120 | * speed possible with selected clock source and skip the division. |
121 | */ | 121 | */ |
122 | if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { | 122 | if (ourhost->no_divider) { |
123 | rate = clk_round_rate(clksrc, wanted); | 123 | rate = clk_round_rate(clksrc, wanted); |
124 | return wanted - rate; | 124 | return wanted - rate; |
125 | } | 125 | } |
@@ -161,9 +161,13 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |||
161 | int src; | 161 | int src; |
162 | u32 ctrl; | 162 | u32 ctrl; |
163 | 163 | ||
164 | host->mmc->actual_clock = 0; | ||
165 | |||
164 | /* don't bother if the clock is going off. */ | 166 | /* don't bother if the clock is going off. */ |
165 | if (clock == 0) | 167 | if (clock == 0) { |
168 | sdhci_set_clock(host, clock); | ||
166 | return; | 169 | return; |
170 | } | ||
167 | 171 | ||
168 | for (src = 0; src < MAX_BUS_CLK; src++) { | 172 | for (src = 0; src < MAX_BUS_CLK; src++) { |
169 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | 173 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); |
@@ -215,6 +219,8 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |||
215 | if (clock < 25 * 1000000) | 219 | if (clock < 25 * 1000000) |
216 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | 220 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); |
217 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | 221 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); |
222 | |||
223 | sdhci_set_clock(host, clock); | ||
218 | } | 224 | } |
219 | 225 | ||
220 | /** | 226 | /** |
@@ -295,10 +301,11 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |||
295 | unsigned long timeout; | 301 | unsigned long timeout; |
296 | u16 clk = 0; | 302 | u16 clk = 0; |
297 | 303 | ||
304 | host->mmc->actual_clock = 0; | ||
305 | |||
298 | /* If the clock is going off, set to 0 at clock control register */ | 306 | /* If the clock is going off, set to 0 at clock control register */ |
299 | if (clock == 0) { | 307 | if (clock == 0) { |
300 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | 308 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
301 | host->clock = clock; | ||
302 | return; | 309 | return; |
303 | } | 310 | } |
304 | 311 | ||
@@ -306,8 +313,6 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |||
306 | 313 | ||
307 | clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); | 314 | clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); |
308 | 315 | ||
309 | host->clock = clock; | ||
310 | |||
311 | clk = SDHCI_CLOCK_INT_EN; | 316 | clk = SDHCI_CLOCK_INT_EN; |
312 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | 317 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
313 | 318 | ||
@@ -329,14 +334,14 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |||
329 | } | 334 | } |
330 | 335 | ||
331 | /** | 336 | /** |
332 | * sdhci_s3c_platform_bus_width - support 8bit buswidth | 337 | * sdhci_s3c_set_bus_width - support 8bit buswidth |
333 | * @host: The SDHCI host being queried | 338 | * @host: The SDHCI host being queried |
334 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested | 339 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested |
335 | * | 340 | * |
336 | * We have 8-bit width support but is not a v3 controller. | 341 | * We have 8-bit width support but is not a v3 controller. |
337 | * So we add platform_bus_width() and support 8bit width. | 342 | * So we add platform_bus_width() and support 8bit width. |
338 | */ | 343 | */ |
339 | static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width) | 344 | static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) |
340 | { | 345 | { |
341 | u8 ctrl; | 346 | u8 ctrl; |
342 | 347 | ||
@@ -358,93 +363,23 @@ static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width) | |||
358 | } | 363 | } |
359 | 364 | ||
360 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | 365 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
361 | |||
362 | return 0; | ||
363 | } | 366 | } |
364 | 367 | ||
365 | static struct sdhci_ops sdhci_s3c_ops = { | 368 | static struct sdhci_ops sdhci_s3c_ops = { |
366 | .get_max_clock = sdhci_s3c_get_max_clk, | 369 | .get_max_clock = sdhci_s3c_get_max_clk, |
367 | .set_clock = sdhci_s3c_set_clock, | 370 | .set_clock = sdhci_s3c_set_clock, |
368 | .get_min_clock = sdhci_s3c_get_min_clock, | 371 | .get_min_clock = sdhci_s3c_get_min_clock, |
369 | .platform_bus_width = sdhci_s3c_platform_bus_width, | 372 | .set_bus_width = sdhci_s3c_set_bus_width, |
373 | .reset = sdhci_reset, | ||
374 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
370 | }; | 375 | }; |
371 | 376 | ||
372 | static void sdhci_s3c_notify_change(struct platform_device *dev, int state) | ||
373 | { | ||
374 | struct sdhci_host *host = platform_get_drvdata(dev); | ||
375 | #ifdef CONFIG_PM_RUNTIME | ||
376 | struct sdhci_s3c *sc = sdhci_priv(host); | ||
377 | #endif | ||
378 | unsigned long flags; | ||
379 | |||
380 | if (host) { | ||
381 | spin_lock_irqsave(&host->lock, flags); | ||
382 | if (state) { | ||
383 | dev_dbg(&dev->dev, "card inserted.\n"); | ||
384 | #ifdef CONFIG_PM_RUNTIME | ||
385 | clk_prepare_enable(sc->clk_io); | ||
386 | #endif | ||
387 | host->flags &= ~SDHCI_DEVICE_DEAD; | ||
388 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | ||
389 | } else { | ||
390 | dev_dbg(&dev->dev, "card removed.\n"); | ||
391 | host->flags |= SDHCI_DEVICE_DEAD; | ||
392 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | ||
393 | #ifdef CONFIG_PM_RUNTIME | ||
394 | clk_disable_unprepare(sc->clk_io); | ||
395 | #endif | ||
396 | } | ||
397 | tasklet_schedule(&host->card_tasklet); | ||
398 | spin_unlock_irqrestore(&host->lock, flags); | ||
399 | } | ||
400 | } | ||
401 | |||
402 | static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id) | ||
403 | { | ||
404 | struct sdhci_s3c *sc = dev_id; | ||
405 | int status = gpio_get_value(sc->ext_cd_gpio); | ||
406 | if (sc->pdata->ext_cd_gpio_invert) | ||
407 | status = !status; | ||
408 | sdhci_s3c_notify_change(sc->pdev, status); | ||
409 | return IRQ_HANDLED; | ||
410 | } | ||
411 | |||
412 | static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc) | ||
413 | { | ||
414 | struct s3c_sdhci_platdata *pdata = sc->pdata; | ||
415 | struct device *dev = &sc->pdev->dev; | ||
416 | |||
417 | if (devm_gpio_request(dev, pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) { | ||
418 | sc->ext_cd_gpio = pdata->ext_cd_gpio; | ||
419 | sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio); | ||
420 | if (sc->ext_cd_irq && | ||
421 | request_threaded_irq(sc->ext_cd_irq, NULL, | ||
422 | sdhci_s3c_gpio_card_detect_thread, | ||
423 | IRQF_TRIGGER_RISING | | ||
424 | IRQF_TRIGGER_FALLING | | ||
425 | IRQF_ONESHOT, | ||
426 | dev_name(dev), sc) == 0) { | ||
427 | int status = gpio_get_value(sc->ext_cd_gpio); | ||
428 | if (pdata->ext_cd_gpio_invert) | ||
429 | status = !status; | ||
430 | sdhci_s3c_notify_change(sc->pdev, status); | ||
431 | } else { | ||
432 | dev_warn(dev, "cannot request irq for card detect\n"); | ||
433 | sc->ext_cd_irq = 0; | ||
434 | } | ||
435 | } else { | ||
436 | dev_err(dev, "cannot request gpio for card detect\n"); | ||
437 | } | ||
438 | } | ||
439 | |||
440 | #ifdef CONFIG_OF | 377 | #ifdef CONFIG_OF |
441 | static int sdhci_s3c_parse_dt(struct device *dev, | 378 | static int sdhci_s3c_parse_dt(struct device *dev, |
442 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) | 379 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
443 | { | 380 | { |
444 | struct device_node *node = dev->of_node; | 381 | struct device_node *node = dev->of_node; |
445 | struct sdhci_s3c *ourhost = to_s3c(host); | ||
446 | u32 max_width; | 382 | u32 max_width; |
447 | int gpio; | ||
448 | 383 | ||
449 | /* if the bus-width property is not specified, assume width as 1 */ | 384 | /* if the bus-width property is not specified, assume width as 1 */ |
450 | if (of_property_read_u32(node, "bus-width", &max_width)) | 385 | if (of_property_read_u32(node, "bus-width", &max_width)) |
@@ -462,18 +397,8 @@ static int sdhci_s3c_parse_dt(struct device *dev, | |||
462 | return 0; | 397 | return 0; |
463 | } | 398 | } |
464 | 399 | ||
465 | gpio = of_get_named_gpio(node, "cd-gpios", 0); | 400 | if (of_get_named_gpio(node, "cd-gpios", 0)) |
466 | if (gpio_is_valid(gpio)) { | ||
467 | pdata->cd_type = S3C_SDHCI_CD_GPIO; | ||
468 | pdata->ext_cd_gpio = gpio; | ||
469 | ourhost->ext_cd_gpio = -1; | ||
470 | if (of_get_property(node, "cd-inverted", NULL)) | ||
471 | pdata->ext_cd_gpio_invert = 1; | ||
472 | return 0; | 401 | return 0; |
473 | } else if (gpio != -ENOENT) { | ||
474 | dev_err(dev, "invalid card detect gpio specified\n"); | ||
475 | return -EINVAL; | ||
476 | } | ||
477 | 402 | ||
478 | /* assuming internal card detect that will be configured by pinctrl */ | 403 | /* assuming internal card detect that will be configured by pinctrl */ |
479 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | 404 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; |
@@ -606,8 +531,10 @@ static int sdhci_s3c_probe(struct platform_device *pdev) | |||
606 | /* Setup quirks for the controller */ | 531 | /* Setup quirks for the controller */ |
607 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; | 532 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
608 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; | 533 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
609 | if (drv_data) | 534 | if (drv_data) { |
610 | host->quirks |= drv_data->sdhci_quirks; | 535 | host->quirks |= drv_data->sdhci_quirks; |
536 | sc->no_divider = drv_data->no_divider; | ||
537 | } | ||
611 | 538 | ||
612 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | 539 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA |
613 | 540 | ||
@@ -656,7 +583,7 @@ static int sdhci_s3c_probe(struct platform_device *pdev) | |||
656 | * If controller does not have internal clock divider, | 583 | * If controller does not have internal clock divider, |
657 | * we can use overriding functions instead of default. | 584 | * we can use overriding functions instead of default. |
658 | */ | 585 | */ |
659 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { | 586 | if (sc->no_divider) { |
660 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; | 587 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
661 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | 588 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; |
662 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | 589 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; |
@@ -674,6 +601,8 @@ static int sdhci_s3c_probe(struct platform_device *pdev) | |||
674 | pm_runtime_use_autosuspend(&pdev->dev); | 601 | pm_runtime_use_autosuspend(&pdev->dev); |
675 | pm_suspend_ignore_children(&pdev->dev, 1); | 602 | pm_suspend_ignore_children(&pdev->dev, 1); |
676 | 603 | ||
604 | mmc_of_parse(host->mmc); | ||
605 | |||
677 | ret = sdhci_add_host(host); | 606 | ret = sdhci_add_host(host); |
678 | if (ret) { | 607 | if (ret) { |
679 | dev_err(dev, "sdhci_add_host() failed\n"); | 608 | dev_err(dev, "sdhci_add_host() failed\n"); |
@@ -682,15 +611,6 @@ static int sdhci_s3c_probe(struct platform_device *pdev) | |||
682 | goto err_req_regs; | 611 | goto err_req_regs; |
683 | } | 612 | } |
684 | 613 | ||
685 | /* The following two methods of card detection might call | ||
686 | sdhci_s3c_notify_change() immediately, so they can be called | ||
687 | only after sdhci_add_host(). Setup errors are ignored. */ | ||
688 | if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init) | ||
689 | pdata->ext_cd_init(&sdhci_s3c_notify_change); | ||
690 | if (pdata->cd_type == S3C_SDHCI_CD_GPIO && | ||
691 | gpio_is_valid(pdata->ext_cd_gpio)) | ||
692 | sdhci_s3c_setup_card_detect_gpio(sc); | ||
693 | |||
694 | #ifdef CONFIG_PM_RUNTIME | 614 | #ifdef CONFIG_PM_RUNTIME |
695 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) | 615 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
696 | clk_disable_unprepare(sc->clk_io); | 616 | clk_disable_unprepare(sc->clk_io); |
@@ -711,16 +631,12 @@ static int sdhci_s3c_remove(struct platform_device *pdev) | |||
711 | { | 631 | { |
712 | struct sdhci_host *host = platform_get_drvdata(pdev); | 632 | struct sdhci_host *host = platform_get_drvdata(pdev); |
713 | struct sdhci_s3c *sc = sdhci_priv(host); | 633 | struct sdhci_s3c *sc = sdhci_priv(host); |
714 | struct s3c_sdhci_platdata *pdata = sc->pdata; | ||
715 | |||
716 | if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup) | ||
717 | pdata->ext_cd_cleanup(&sdhci_s3c_notify_change); | ||
718 | 634 | ||
719 | if (sc->ext_cd_irq) | 635 | if (sc->ext_cd_irq) |
720 | free_irq(sc->ext_cd_irq, sc); | 636 | free_irq(sc->ext_cd_irq, sc); |
721 | 637 | ||
722 | #ifdef CONFIG_PM_RUNTIME | 638 | #ifdef CONFIG_PM_RUNTIME |
723 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) | 639 | if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
724 | clk_prepare_enable(sc->clk_io); | 640 | clk_prepare_enable(sc->clk_io); |
725 | #endif | 641 | #endif |
726 | sdhci_remove_host(host, 1); | 642 | sdhci_remove_host(host, 1); |
@@ -797,7 +713,7 @@ static const struct dev_pm_ops sdhci_s3c_pmops = { | |||
797 | 713 | ||
798 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) | 714 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) |
799 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { | 715 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { |
800 | .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK, | 716 | .no_divider = true, |
801 | }; | 717 | }; |
802 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) | 718 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) |
803 | #else | 719 | #else |
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c index 696122c1b468..17004531d089 100644 --- a/drivers/mmc/host/sdhci-sirf.c +++ b/drivers/mmc/host/sdhci-sirf.c | |||
@@ -28,7 +28,11 @@ static unsigned int sdhci_sirf_get_max_clk(struct sdhci_host *host) | |||
28 | } | 28 | } |
29 | 29 | ||
30 | static struct sdhci_ops sdhci_sirf_ops = { | 30 | static struct sdhci_ops sdhci_sirf_ops = { |
31 | .set_clock = sdhci_set_clock, | ||
31 | .get_max_clock = sdhci_sirf_get_max_clk, | 32 | .get_max_clock = sdhci_sirf_get_max_clk, |
33 | .set_bus_width = sdhci_set_bus_width, | ||
34 | .reset = sdhci_reset, | ||
35 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
32 | }; | 36 | }; |
33 | 37 | ||
34 | static struct sdhci_pltfm_data sdhci_sirf_pdata = { | 38 | static struct sdhci_pltfm_data sdhci_sirf_pdata = { |
diff --git a/drivers/mmc/host/sdhci-spear.c b/drivers/mmc/host/sdhci-spear.c index 0316dec3f006..9d535c7336ef 100644 --- a/drivers/mmc/host/sdhci-spear.c +++ b/drivers/mmc/host/sdhci-spear.c | |||
@@ -38,7 +38,10 @@ struct spear_sdhci { | |||
38 | 38 | ||
39 | /* sdhci ops */ | 39 | /* sdhci ops */ |
40 | static const struct sdhci_ops sdhci_pltfm_ops = { | 40 | static const struct sdhci_ops sdhci_pltfm_ops = { |
41 | /* Nothing to do for now. */ | 41 | .set_clock = sdhci_set_clock, |
42 | .set_bus_width = sdhci_set_bus_width, | ||
43 | .reset = sdhci_reset, | ||
44 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
42 | }; | 45 | }; |
43 | 46 | ||
44 | #ifdef CONFIG_OF | 47 | #ifdef CONFIG_OF |
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a835898a68dd..d93a063a36f3 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c | |||
@@ -32,11 +32,17 @@ | |||
32 | 32 | ||
33 | /* Tegra SDHOST controller vendor register definitions */ | 33 | /* Tegra SDHOST controller vendor register definitions */ |
34 | #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 | 34 | #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 |
35 | #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 | ||
36 | #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 | ||
35 | #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 | 37 | #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 |
38 | #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 | ||
36 | 39 | ||
37 | #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) | 40 | #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) |
38 | #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) | 41 | #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) |
39 | #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) | 42 | #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) |
43 | #define NVQUIRK_DISABLE_SDR50 BIT(3) | ||
44 | #define NVQUIRK_DISABLE_SDR104 BIT(4) | ||
45 | #define NVQUIRK_DISABLE_DDR50 BIT(5) | ||
40 | 46 | ||
41 | struct sdhci_tegra_soc_data { | 47 | struct sdhci_tegra_soc_data { |
42 | const struct sdhci_pltfm_data *pdata; | 48 | const struct sdhci_pltfm_data *pdata; |
@@ -48,19 +54,6 @@ struct sdhci_tegra { | |||
48 | int power_gpio; | 54 | int power_gpio; |
49 | }; | 55 | }; |
50 | 56 | ||
51 | static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg) | ||
52 | { | ||
53 | u32 val; | ||
54 | |||
55 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { | ||
56 | /* Use wp_gpio here instead? */ | ||
57 | val = readl(host->ioaddr + reg); | ||
58 | return val | SDHCI_WRITE_PROTECT; | ||
59 | } | ||
60 | |||
61 | return readl(host->ioaddr + reg); | ||
62 | } | ||
63 | |||
64 | static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) | 57 | static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) |
65 | { | 58 | { |
66 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | 59 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
@@ -108,26 +101,33 @@ static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) | |||
108 | return mmc_gpio_get_ro(host->mmc); | 101 | return mmc_gpio_get_ro(host->mmc); |
109 | } | 102 | } |
110 | 103 | ||
111 | static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask) | 104 | static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) |
112 | { | 105 | { |
113 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | 106 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
114 | struct sdhci_tegra *tegra_host = pltfm_host->priv; | 107 | struct sdhci_tegra *tegra_host = pltfm_host->priv; |
115 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; | 108 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
109 | u32 misc_ctrl; | ||
110 | |||
111 | sdhci_reset(host, mask); | ||
116 | 112 | ||
117 | if (!(mask & SDHCI_RESET_ALL)) | 113 | if (!(mask & SDHCI_RESET_ALL)) |
118 | return; | 114 | return; |
119 | 115 | ||
116 | misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); | ||
120 | /* Erratum: Enable SDHCI spec v3.00 support */ | 117 | /* Erratum: Enable SDHCI spec v3.00 support */ |
121 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) { | 118 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) |
122 | u32 misc_ctrl; | ||
123 | |||
124 | misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); | ||
125 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; | 119 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; |
126 | sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); | 120 | /* Don't advertise UHS modes which aren't supported yet */ |
127 | } | 121 | if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) |
122 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; | ||
123 | if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) | ||
124 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; | ||
125 | if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) | ||
126 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; | ||
127 | sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); | ||
128 | } | 128 | } |
129 | 129 | ||
130 | static int tegra_sdhci_buswidth(struct sdhci_host *host, int bus_width) | 130 | static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) |
131 | { | 131 | { |
132 | u32 ctrl; | 132 | u32 ctrl; |
133 | 133 | ||
@@ -144,23 +144,25 @@ static int tegra_sdhci_buswidth(struct sdhci_host *host, int bus_width) | |||
144 | ctrl &= ~SDHCI_CTRL_4BITBUS; | 144 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
145 | } | 145 | } |
146 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | 146 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
147 | return 0; | ||
148 | } | 147 | } |
149 | 148 | ||
150 | static const struct sdhci_ops tegra_sdhci_ops = { | 149 | static const struct sdhci_ops tegra_sdhci_ops = { |
151 | .get_ro = tegra_sdhci_get_ro, | 150 | .get_ro = tegra_sdhci_get_ro, |
152 | .read_l = tegra_sdhci_readl, | ||
153 | .read_w = tegra_sdhci_readw, | 151 | .read_w = tegra_sdhci_readw, |
154 | .write_l = tegra_sdhci_writel, | 152 | .write_l = tegra_sdhci_writel, |
155 | .platform_bus_width = tegra_sdhci_buswidth, | 153 | .set_clock = sdhci_set_clock, |
156 | .platform_reset_exit = tegra_sdhci_reset_exit, | 154 | .set_bus_width = tegra_sdhci_set_bus_width, |
155 | .reset = tegra_sdhci_reset, | ||
156 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
157 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | ||
157 | }; | 158 | }; |
158 | 159 | ||
159 | static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { | 160 | static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { |
160 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | | 161 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
161 | SDHCI_QUIRK_SINGLE_POWER_WRITE | | 162 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
162 | SDHCI_QUIRK_NO_HISPD_BIT | | 163 | SDHCI_QUIRK_NO_HISPD_BIT | |
163 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, | 164 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
165 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | ||
164 | .ops = &tegra_sdhci_ops, | 166 | .ops = &tegra_sdhci_ops, |
165 | }; | 167 | }; |
166 | 168 | ||
@@ -175,13 +177,16 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { | |||
175 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | 177 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
176 | SDHCI_QUIRK_SINGLE_POWER_WRITE | | 178 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
177 | SDHCI_QUIRK_NO_HISPD_BIT | | 179 | SDHCI_QUIRK_NO_HISPD_BIT | |
178 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, | 180 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
181 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | ||
179 | .ops = &tegra_sdhci_ops, | 182 | .ops = &tegra_sdhci_ops, |
180 | }; | 183 | }; |
181 | 184 | ||
182 | static struct sdhci_tegra_soc_data soc_data_tegra30 = { | 185 | static struct sdhci_tegra_soc_data soc_data_tegra30 = { |
183 | .pdata = &sdhci_tegra30_pdata, | 186 | .pdata = &sdhci_tegra30_pdata, |
184 | .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300, | 187 | .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | |
188 | NVQUIRK_DISABLE_SDR50 | | ||
189 | NVQUIRK_DISABLE_SDR104, | ||
185 | }; | 190 | }; |
186 | 191 | ||
187 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { | 192 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { |
@@ -189,12 +194,16 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { | |||
189 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | 194 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
190 | SDHCI_QUIRK_SINGLE_POWER_WRITE | | 195 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
191 | SDHCI_QUIRK_NO_HISPD_BIT | | 196 | SDHCI_QUIRK_NO_HISPD_BIT | |
192 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, | 197 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
198 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | ||
193 | .ops = &tegra_sdhci_ops, | 199 | .ops = &tegra_sdhci_ops, |
194 | }; | 200 | }; |
195 | 201 | ||
196 | static struct sdhci_tegra_soc_data soc_data_tegra114 = { | 202 | static struct sdhci_tegra_soc_data soc_data_tegra114 = { |
197 | .pdata = &sdhci_tegra114_pdata, | 203 | .pdata = &sdhci_tegra114_pdata, |
204 | .nvquirks = NVQUIRK_DISABLE_SDR50 | | ||
205 | NVQUIRK_DISABLE_DDR50 | | ||
206 | NVQUIRK_DISABLE_SDR104, | ||
198 | }; | 207 | }; |
199 | 208 | ||
200 | static const struct of_device_id sdhci_tegra_dt_match[] = { | 209 | static const struct of_device_id sdhci_tegra_dt_match[] = { |
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9a79fc4b60ca..47055f3f01b8 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c | |||
@@ -44,6 +44,8 @@ | |||
44 | 44 | ||
45 | #define MAX_TUNING_LOOP 40 | 45 | #define MAX_TUNING_LOOP 40 |
46 | 46 | ||
47 | #define ADMA_SIZE ((128 * 2 + 1) * 4) | ||
48 | |||
47 | static unsigned int debug_quirks = 0; | 49 | static unsigned int debug_quirks = 0; |
48 | static unsigned int debug_quirks2; | 50 | static unsigned int debug_quirks2; |
49 | 51 | ||
@@ -131,43 +133,26 @@ static void sdhci_dumpregs(struct sdhci_host *host) | |||
131 | * * | 133 | * * |
132 | \*****************************************************************************/ | 134 | \*****************************************************************************/ |
133 | 135 | ||
134 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) | ||
135 | { | ||
136 | u32 ier; | ||
137 | |||
138 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | ||
139 | ier &= ~clear; | ||
140 | ier |= set; | ||
141 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | ||
142 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | ||
143 | } | ||
144 | |||
145 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | ||
146 | { | ||
147 | sdhci_clear_set_irqs(host, 0, irqs); | ||
148 | } | ||
149 | |||
150 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | ||
151 | { | ||
152 | sdhci_clear_set_irqs(host, irqs, 0); | ||
153 | } | ||
154 | |||
155 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | 136 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
156 | { | 137 | { |
157 | u32 present, irqs; | 138 | u32 present; |
158 | 139 | ||
159 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || | 140 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
160 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) | 141 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
161 | return; | 142 | return; |
162 | 143 | ||
163 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | 144 | if (enable) { |
164 | SDHCI_CARD_PRESENT; | 145 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
165 | irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; | 146 | SDHCI_CARD_PRESENT; |
166 | 147 | ||
167 | if (enable) | 148 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
168 | sdhci_unmask_irqs(host, irqs); | 149 | SDHCI_INT_CARD_INSERT; |
169 | else | 150 | } else { |
170 | sdhci_mask_irqs(host, irqs); | 151 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); |
152 | } | ||
153 | |||
154 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | ||
155 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
171 | } | 156 | } |
172 | 157 | ||
173 | static void sdhci_enable_card_detection(struct sdhci_host *host) | 158 | static void sdhci_enable_card_detection(struct sdhci_host *host) |
@@ -180,22 +165,9 @@ static void sdhci_disable_card_detection(struct sdhci_host *host) | |||
180 | sdhci_set_card_detection(host, false); | 165 | sdhci_set_card_detection(host, false); |
181 | } | 166 | } |
182 | 167 | ||
183 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | 168 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
184 | { | 169 | { |
185 | unsigned long timeout; | 170 | unsigned long timeout; |
186 | u32 uninitialized_var(ier); | ||
187 | |||
188 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { | ||
189 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & | ||
190 | SDHCI_CARD_PRESENT)) | ||
191 | return; | ||
192 | } | ||
193 | |||
194 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | ||
195 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | ||
196 | |||
197 | if (host->ops->platform_reset_enter) | ||
198 | host->ops->platform_reset_enter(host, mask); | ||
199 | 171 | ||
200 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); | 172 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
201 | 173 | ||
@@ -220,16 +192,27 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) | |||
220 | timeout--; | 192 | timeout--; |
221 | mdelay(1); | 193 | mdelay(1); |
222 | } | 194 | } |
195 | } | ||
196 | EXPORT_SYMBOL_GPL(sdhci_reset); | ||
197 | |||
198 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) | ||
199 | { | ||
200 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { | ||
201 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & | ||
202 | SDHCI_CARD_PRESENT)) | ||
203 | return; | ||
204 | } | ||
223 | 205 | ||
224 | if (host->ops->platform_reset_exit) | 206 | host->ops->reset(host, mask); |
225 | host->ops->platform_reset_exit(host, mask); | ||
226 | 207 | ||
227 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | 208 | if (mask & SDHCI_RESET_ALL) { |
228 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | 209 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
210 | if (host->ops->enable_dma) | ||
211 | host->ops->enable_dma(host); | ||
212 | } | ||
229 | 213 | ||
230 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | 214 | /* Resetting the controller clears many */ |
231 | if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) | 215 | host->preset_enabled = false; |
232 | host->ops->enable_dma(host); | ||
233 | } | 216 | } |
234 | } | 217 | } |
235 | 218 | ||
@@ -238,15 +221,18 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); | |||
238 | static void sdhci_init(struct sdhci_host *host, int soft) | 221 | static void sdhci_init(struct sdhci_host *host, int soft) |
239 | { | 222 | { |
240 | if (soft) | 223 | if (soft) |
241 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | 224 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
242 | else | 225 | else |
243 | sdhci_reset(host, SDHCI_RESET_ALL); | 226 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
244 | 227 | ||
245 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, | 228 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
246 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | 229 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | |
247 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | 230 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | |
248 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | 231 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | |
249 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); | 232 | SDHCI_INT_RESPONSE; |
233 | |||
234 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | ||
235 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
250 | 236 | ||
251 | if (soft) { | 237 | if (soft) { |
252 | /* force clock reconfiguration */ | 238 | /* force clock reconfiguration */ |
@@ -502,11 +488,6 @@ static int sdhci_adma_table_pre(struct sdhci_host *host, | |||
502 | else | 488 | else |
503 | direction = DMA_TO_DEVICE; | 489 | direction = DMA_TO_DEVICE; |
504 | 490 | ||
505 | /* | ||
506 | * The ADMA descriptor table is mapped further down as we | ||
507 | * need to fill it with data first. | ||
508 | */ | ||
509 | |||
510 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | 491 | host->align_addr = dma_map_single(mmc_dev(host->mmc), |
511 | host->align_buffer, 128 * 4, direction); | 492 | host->align_buffer, 128 * 4, direction); |
512 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) | 493 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
@@ -567,7 +548,7 @@ static int sdhci_adma_table_pre(struct sdhci_host *host, | |||
567 | * If this triggers then we have a calculation bug | 548 | * If this triggers then we have a calculation bug |
568 | * somewhere. :/ | 549 | * somewhere. :/ |
569 | */ | 550 | */ |
570 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | 551 | WARN_ON((desc - host->adma_desc) > ADMA_SIZE); |
571 | } | 552 | } |
572 | 553 | ||
573 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { | 554 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
@@ -595,17 +576,8 @@ static int sdhci_adma_table_pre(struct sdhci_host *host, | |||
595 | host->align_addr, 128 * 4, direction); | 576 | host->align_addr, 128 * 4, direction); |
596 | } | 577 | } |
597 | 578 | ||
598 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | ||
599 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | ||
600 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) | ||
601 | goto unmap_entries; | ||
602 | BUG_ON(host->adma_addr & 0x3); | ||
603 | |||
604 | return 0; | 579 | return 0; |
605 | 580 | ||
606 | unmap_entries: | ||
607 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | ||
608 | data->sg_len, direction); | ||
609 | unmap_align: | 581 | unmap_align: |
610 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | 582 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, |
611 | 128 * 4, direction); | 583 | 128 * 4, direction); |
@@ -623,19 +595,25 @@ static void sdhci_adma_table_post(struct sdhci_host *host, | |||
623 | u8 *align; | 595 | u8 *align; |
624 | char *buffer; | 596 | char *buffer; |
625 | unsigned long flags; | 597 | unsigned long flags; |
598 | bool has_unaligned; | ||
626 | 599 | ||
627 | if (data->flags & MMC_DATA_READ) | 600 | if (data->flags & MMC_DATA_READ) |
628 | direction = DMA_FROM_DEVICE; | 601 | direction = DMA_FROM_DEVICE; |
629 | else | 602 | else |
630 | direction = DMA_TO_DEVICE; | 603 | direction = DMA_TO_DEVICE; |
631 | 604 | ||
632 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | ||
633 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | ||
634 | |||
635 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | 605 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, |
636 | 128 * 4, direction); | 606 | 128 * 4, direction); |
637 | 607 | ||
638 | if (data->flags & MMC_DATA_READ) { | 608 | /* Do a quick scan of the SG list for any unaligned mappings */ |
609 | has_unaligned = false; | ||
610 | for_each_sg(data->sg, sg, host->sg_count, i) | ||
611 | if (sg_dma_address(sg) & 3) { | ||
612 | has_unaligned = true; | ||
613 | break; | ||
614 | } | ||
615 | |||
616 | if (has_unaligned && data->flags & MMC_DATA_READ) { | ||
639 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | 617 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
640 | data->sg_len, direction); | 618 | data->sg_len, direction); |
641 | 619 | ||
@@ -721,9 +699,12 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host) | |||
721 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | 699 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; |
722 | 700 | ||
723 | if (host->flags & SDHCI_REQ_USE_DMA) | 701 | if (host->flags & SDHCI_REQ_USE_DMA) |
724 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | 702 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
725 | else | 703 | else |
726 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | 704 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
705 | |||
706 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | ||
707 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
727 | } | 708 | } |
728 | 709 | ||
729 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) | 710 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
@@ -976,8 +957,8 @@ static void sdhci_finish_data(struct sdhci_host *host) | |||
976 | * upon error conditions. | 957 | * upon error conditions. |
977 | */ | 958 | */ |
978 | if (data->error) { | 959 | if (data->error) { |
979 | sdhci_reset(host, SDHCI_RESET_CMD); | 960 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
980 | sdhci_reset(host, SDHCI_RESET_DATA); | 961 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
981 | } | 962 | } |
982 | 963 | ||
983 | sdhci_send_command(host, data->stop); | 964 | sdhci_send_command(host, data->stop); |
@@ -1107,24 +1088,23 @@ static void sdhci_finish_command(struct sdhci_host *host) | |||
1107 | 1088 | ||
1108 | static u16 sdhci_get_preset_value(struct sdhci_host *host) | 1089 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1109 | { | 1090 | { |
1110 | u16 ctrl, preset = 0; | 1091 | u16 preset = 0; |
1111 | |||
1112 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
1113 | 1092 | ||
1114 | switch (ctrl & SDHCI_CTRL_UHS_MASK) { | 1093 | switch (host->timing) { |
1115 | case SDHCI_CTRL_UHS_SDR12: | 1094 | case MMC_TIMING_UHS_SDR12: |
1116 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | 1095 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
1117 | break; | 1096 | break; |
1118 | case SDHCI_CTRL_UHS_SDR25: | 1097 | case MMC_TIMING_UHS_SDR25: |
1119 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); | 1098 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
1120 | break; | 1099 | break; |
1121 | case SDHCI_CTRL_UHS_SDR50: | 1100 | case MMC_TIMING_UHS_SDR50: |
1122 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); | 1101 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
1123 | break; | 1102 | break; |
1124 | case SDHCI_CTRL_UHS_SDR104: | 1103 | case MMC_TIMING_UHS_SDR104: |
1104 | case MMC_TIMING_MMC_HS200: | ||
1125 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); | 1105 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
1126 | break; | 1106 | break; |
1127 | case SDHCI_CTRL_UHS_DDR50: | 1107 | case MMC_TIMING_UHS_DDR50: |
1128 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); | 1108 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
1129 | break; | 1109 | break; |
1130 | default: | 1110 | default: |
@@ -1136,32 +1116,22 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) | |||
1136 | return preset; | 1116 | return preset; |
1137 | } | 1117 | } |
1138 | 1118 | ||
1139 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | 1119 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
1140 | { | 1120 | { |
1141 | int div = 0; /* Initialized for compiler warning */ | 1121 | int div = 0; /* Initialized for compiler warning */ |
1142 | int real_div = div, clk_mul = 1; | 1122 | int real_div = div, clk_mul = 1; |
1143 | u16 clk = 0; | 1123 | u16 clk = 0; |
1144 | unsigned long timeout; | 1124 | unsigned long timeout; |
1145 | 1125 | ||
1146 | if (clock && clock == host->clock) | ||
1147 | return; | ||
1148 | |||
1149 | host->mmc->actual_clock = 0; | 1126 | host->mmc->actual_clock = 0; |
1150 | 1127 | ||
1151 | if (host->ops->set_clock) { | ||
1152 | host->ops->set_clock(host, clock); | ||
1153 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | ||
1154 | return; | ||
1155 | } | ||
1156 | |||
1157 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | 1128 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
1158 | 1129 | ||
1159 | if (clock == 0) | 1130 | if (clock == 0) |
1160 | goto out; | 1131 | return; |
1161 | 1132 | ||
1162 | if (host->version >= SDHCI_SPEC_300) { | 1133 | if (host->version >= SDHCI_SPEC_300) { |
1163 | if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & | 1134 | if (host->preset_enabled) { |
1164 | SDHCI_CTRL_PRESET_VAL_ENABLE) { | ||
1165 | u16 pre_val; | 1135 | u16 pre_val; |
1166 | 1136 | ||
1167 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | 1137 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
@@ -1247,26 +1217,16 @@ clock_set: | |||
1247 | 1217 | ||
1248 | clk |= SDHCI_CLOCK_CARD_EN; | 1218 | clk |= SDHCI_CLOCK_CARD_EN; |
1249 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | 1219 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
1250 | |||
1251 | out: | ||
1252 | host->clock = clock; | ||
1253 | } | 1220 | } |
1221 | EXPORT_SYMBOL_GPL(sdhci_set_clock); | ||
1254 | 1222 | ||
1255 | static inline void sdhci_update_clock(struct sdhci_host *host) | 1223 | static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
1256 | { | 1224 | unsigned short vdd) |
1257 | unsigned int clock; | ||
1258 | |||
1259 | clock = host->clock; | ||
1260 | host->clock = 0; | ||
1261 | sdhci_set_clock(host, clock); | ||
1262 | } | ||
1263 | |||
1264 | static int sdhci_set_power(struct sdhci_host *host, unsigned short power) | ||
1265 | { | 1225 | { |
1266 | u8 pwr = 0; | 1226 | u8 pwr = 0; |
1267 | 1227 | ||
1268 | if (power != (unsigned short)-1) { | 1228 | if (mode != MMC_POWER_OFF) { |
1269 | switch (1 << power) { | 1229 | switch (1 << vdd) { |
1270 | case MMC_VDD_165_195: | 1230 | case MMC_VDD_165_195: |
1271 | pwr = SDHCI_POWER_180; | 1231 | pwr = SDHCI_POWER_180; |
1272 | break; | 1232 | break; |
@@ -1284,7 +1244,7 @@ static int sdhci_set_power(struct sdhci_host *host, unsigned short power) | |||
1284 | } | 1244 | } |
1285 | 1245 | ||
1286 | if (host->pwr == pwr) | 1246 | if (host->pwr == pwr) |
1287 | return -1; | 1247 | return; |
1288 | 1248 | ||
1289 | host->pwr = pwr; | 1249 | host->pwr = pwr; |
1290 | 1250 | ||
@@ -1292,38 +1252,43 @@ static int sdhci_set_power(struct sdhci_host *host, unsigned short power) | |||
1292 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | 1252 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
1293 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | 1253 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1294 | sdhci_runtime_pm_bus_off(host); | 1254 | sdhci_runtime_pm_bus_off(host); |
1295 | return 0; | 1255 | vdd = 0; |
1296 | } | 1256 | } else { |
1297 | 1257 | /* | |
1298 | /* | 1258 | * Spec says that we should clear the power reg before setting |
1299 | * Spec says that we should clear the power reg before setting | 1259 | * a new value. Some controllers don't seem to like this though. |
1300 | * a new value. Some controllers don't seem to like this though. | 1260 | */ |
1301 | */ | 1261 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
1302 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | 1262 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
1303 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | ||
1304 | 1263 | ||
1305 | /* | 1264 | /* |
1306 | * At least the Marvell CaFe chip gets confused if we set the voltage | 1265 | * At least the Marvell CaFe chip gets confused if we set the |
1307 | * and set turn on power at the same time, so set the voltage first. | 1266 | * voltage and set turn on power at the same time, so set the |
1308 | */ | 1267 | * voltage first. |
1309 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) | 1268 | */ |
1310 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | 1269 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
1270 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | ||
1311 | 1271 | ||
1312 | pwr |= SDHCI_POWER_ON; | 1272 | pwr |= SDHCI_POWER_ON; |
1313 | 1273 | ||
1314 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | 1274 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
1315 | 1275 | ||
1316 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | 1276 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1317 | sdhci_runtime_pm_bus_on(host); | 1277 | sdhci_runtime_pm_bus_on(host); |
1318 | 1278 | ||
1319 | /* | 1279 | /* |
1320 | * Some controllers need an extra 10ms delay of 10ms before they | 1280 | * Some controllers need an extra 10ms delay of 10ms before |
1321 | * can apply clock after applying power | 1281 | * they can apply clock after applying power |
1322 | */ | 1282 | */ |
1323 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) | 1283 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
1324 | mdelay(10); | 1284 | mdelay(10); |
1285 | } | ||
1325 | 1286 | ||
1326 | return power; | 1287 | if (host->vmmc) { |
1288 | spin_unlock_irq(&host->lock); | ||
1289 | mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd); | ||
1290 | spin_lock_irq(&host->lock); | ||
1291 | } | ||
1327 | } | 1292 | } |
1328 | 1293 | ||
1329 | /*****************************************************************************\ | 1294 | /*****************************************************************************\ |
@@ -1427,10 +1392,53 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |||
1427 | spin_unlock_irqrestore(&host->lock, flags); | 1392 | spin_unlock_irqrestore(&host->lock, flags); |
1428 | } | 1393 | } |
1429 | 1394 | ||
1395 | void sdhci_set_bus_width(struct sdhci_host *host, int width) | ||
1396 | { | ||
1397 | u8 ctrl; | ||
1398 | |||
1399 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | ||
1400 | if (width == MMC_BUS_WIDTH_8) { | ||
1401 | ctrl &= ~SDHCI_CTRL_4BITBUS; | ||
1402 | if (host->version >= SDHCI_SPEC_300) | ||
1403 | ctrl |= SDHCI_CTRL_8BITBUS; | ||
1404 | } else { | ||
1405 | if (host->version >= SDHCI_SPEC_300) | ||
1406 | ctrl &= ~SDHCI_CTRL_8BITBUS; | ||
1407 | if (width == MMC_BUS_WIDTH_4) | ||
1408 | ctrl |= SDHCI_CTRL_4BITBUS; | ||
1409 | else | ||
1410 | ctrl &= ~SDHCI_CTRL_4BITBUS; | ||
1411 | } | ||
1412 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | ||
1413 | } | ||
1414 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); | ||
1415 | |||
1416 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) | ||
1417 | { | ||
1418 | u16 ctrl_2; | ||
1419 | |||
1420 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
1421 | /* Select Bus Speed Mode for host */ | ||
1422 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | ||
1423 | if ((timing == MMC_TIMING_MMC_HS200) || | ||
1424 | (timing == MMC_TIMING_UHS_SDR104)) | ||
1425 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | ||
1426 | else if (timing == MMC_TIMING_UHS_SDR12) | ||
1427 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | ||
1428 | else if (timing == MMC_TIMING_UHS_SDR25) | ||
1429 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | ||
1430 | else if (timing == MMC_TIMING_UHS_SDR50) | ||
1431 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | ||
1432 | else if ((timing == MMC_TIMING_UHS_DDR50) || | ||
1433 | (timing == MMC_TIMING_MMC_DDR52)) | ||
1434 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | ||
1435 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | ||
1436 | } | ||
1437 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); | ||
1438 | |||
1430 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | 1439 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
1431 | { | 1440 | { |
1432 | unsigned long flags; | 1441 | unsigned long flags; |
1433 | int vdd_bit = -1; | ||
1434 | u8 ctrl; | 1442 | u8 ctrl; |
1435 | 1443 | ||
1436 | spin_lock_irqsave(&host->lock, flags); | 1444 | spin_lock_irqsave(&host->lock, flags); |
@@ -1456,45 +1464,17 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | |||
1456 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | 1464 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) |
1457 | sdhci_enable_preset_value(host, false); | 1465 | sdhci_enable_preset_value(host, false); |
1458 | 1466 | ||
1459 | sdhci_set_clock(host, ios->clock); | 1467 | if (!ios->clock || ios->clock != host->clock) { |
1460 | 1468 | host->ops->set_clock(host, ios->clock); | |
1461 | if (ios->power_mode == MMC_POWER_OFF) | 1469 | host->clock = ios->clock; |
1462 | vdd_bit = sdhci_set_power(host, -1); | ||
1463 | else | ||
1464 | vdd_bit = sdhci_set_power(host, ios->vdd); | ||
1465 | |||
1466 | if (host->vmmc && vdd_bit != -1) { | ||
1467 | spin_unlock_irqrestore(&host->lock, flags); | ||
1468 | mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); | ||
1469 | spin_lock_irqsave(&host->lock, flags); | ||
1470 | } | 1470 | } |
1471 | 1471 | ||
1472 | sdhci_set_power(host, ios->power_mode, ios->vdd); | ||
1473 | |||
1472 | if (host->ops->platform_send_init_74_clocks) | 1474 | if (host->ops->platform_send_init_74_clocks) |
1473 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | 1475 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); |
1474 | 1476 | ||
1475 | /* | 1477 | host->ops->set_bus_width(host, ios->bus_width); |
1476 | * If your platform has 8-bit width support but is not a v3 controller, | ||
1477 | * or if it requires special setup code, you should implement that in | ||
1478 | * platform_bus_width(). | ||
1479 | */ | ||
1480 | if (host->ops->platform_bus_width) { | ||
1481 | host->ops->platform_bus_width(host, ios->bus_width); | ||
1482 | } else { | ||
1483 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | ||
1484 | if (ios->bus_width == MMC_BUS_WIDTH_8) { | ||
1485 | ctrl &= ~SDHCI_CTRL_4BITBUS; | ||
1486 | if (host->version >= SDHCI_SPEC_300) | ||
1487 | ctrl |= SDHCI_CTRL_8BITBUS; | ||
1488 | } else { | ||
1489 | if (host->version >= SDHCI_SPEC_300) | ||
1490 | ctrl &= ~SDHCI_CTRL_8BITBUS; | ||
1491 | if (ios->bus_width == MMC_BUS_WIDTH_4) | ||
1492 | ctrl |= SDHCI_CTRL_4BITBUS; | ||
1493 | else | ||
1494 | ctrl &= ~SDHCI_CTRL_4BITBUS; | ||
1495 | } | ||
1496 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | ||
1497 | } | ||
1498 | 1478 | ||
1499 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | 1479 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
1500 | 1480 | ||
@@ -1510,19 +1490,20 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | |||
1510 | 1490 | ||
1511 | /* In case of UHS-I modes, set High Speed Enable */ | 1491 | /* In case of UHS-I modes, set High Speed Enable */ |
1512 | if ((ios->timing == MMC_TIMING_MMC_HS200) || | 1492 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
1493 | (ios->timing == MMC_TIMING_MMC_DDR52) || | ||
1513 | (ios->timing == MMC_TIMING_UHS_SDR50) || | 1494 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
1514 | (ios->timing == MMC_TIMING_UHS_SDR104) || | 1495 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1515 | (ios->timing == MMC_TIMING_UHS_DDR50) || | 1496 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
1516 | (ios->timing == MMC_TIMING_UHS_SDR25)) | 1497 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
1517 | ctrl |= SDHCI_CTRL_HISPD; | 1498 | ctrl |= SDHCI_CTRL_HISPD; |
1518 | 1499 | ||
1519 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | 1500 | if (!host->preset_enabled) { |
1520 | if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | ||
1521 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | 1501 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
1522 | /* | 1502 | /* |
1523 | * We only need to set Driver Strength if the | 1503 | * We only need to set Driver Strength if the |
1524 | * preset value enable is not set. | 1504 | * preset value enable is not set. |
1525 | */ | 1505 | */ |
1506 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
1526 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; | 1507 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
1527 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | 1508 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) |
1528 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | 1509 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; |
@@ -1546,7 +1527,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | |||
1546 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | 1527 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
1547 | 1528 | ||
1548 | /* Re-enable SD Clock */ | 1529 | /* Re-enable SD Clock */ |
1549 | sdhci_update_clock(host); | 1530 | host->ops->set_clock(host, host->clock); |
1550 | } | 1531 | } |
1551 | 1532 | ||
1552 | 1533 | ||
@@ -1555,25 +1536,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | |||
1555 | clk &= ~SDHCI_CLOCK_CARD_EN; | 1536 | clk &= ~SDHCI_CLOCK_CARD_EN; |
1556 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | 1537 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
1557 | 1538 | ||
1558 | if (host->ops->set_uhs_signaling) | 1539 | host->ops->set_uhs_signaling(host, ios->timing); |
1559 | host->ops->set_uhs_signaling(host, ios->timing); | 1540 | host->timing = ios->timing; |
1560 | else { | ||
1561 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
1562 | /* Select Bus Speed Mode for host */ | ||
1563 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | ||
1564 | if ((ios->timing == MMC_TIMING_MMC_HS200) || | ||
1565 | (ios->timing == MMC_TIMING_UHS_SDR104)) | ||
1566 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | ||
1567 | else if (ios->timing == MMC_TIMING_UHS_SDR12) | ||
1568 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | ||
1569 | else if (ios->timing == MMC_TIMING_UHS_SDR25) | ||
1570 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | ||
1571 | else if (ios->timing == MMC_TIMING_UHS_SDR50) | ||
1572 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | ||
1573 | else if (ios->timing == MMC_TIMING_UHS_DDR50) | ||
1574 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | ||
1575 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | ||
1576 | } | ||
1577 | 1541 | ||
1578 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && | 1542 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1579 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | 1543 | ((ios->timing == MMC_TIMING_UHS_SDR12) || |
@@ -1590,7 +1554,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | |||
1590 | } | 1554 | } |
1591 | 1555 | ||
1592 | /* Re-enable SD Clock */ | 1556 | /* Re-enable SD Clock */ |
1593 | sdhci_update_clock(host); | 1557 | host->ops->set_clock(host, host->clock); |
1594 | } else | 1558 | } else |
1595 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | 1559 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
1596 | 1560 | ||
@@ -1600,7 +1564,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) | |||
1600 | * it on each ios seems to solve the problem. | 1564 | * it on each ios seems to solve the problem. |
1601 | */ | 1565 | */ |
1602 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) | 1566 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
1603 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); | 1567 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1604 | 1568 | ||
1605 | mmiowb(); | 1569 | mmiowb(); |
1606 | spin_unlock_irqrestore(&host->lock, flags); | 1570 | spin_unlock_irqrestore(&host->lock, flags); |
@@ -1709,24 +1673,16 @@ static int sdhci_get_ro(struct mmc_host *mmc) | |||
1709 | 1673 | ||
1710 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) | 1674 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1711 | { | 1675 | { |
1712 | if (host->flags & SDHCI_DEVICE_DEAD) | 1676 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
1713 | goto out; | 1677 | if (enable) |
1714 | 1678 | host->ier |= SDHCI_INT_CARD_INT; | |
1715 | if (enable) | 1679 | else |
1716 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | 1680 | host->ier &= ~SDHCI_INT_CARD_INT; |
1717 | else | ||
1718 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | ||
1719 | |||
1720 | /* SDIO IRQ will be enabled as appropriate in runtime resume */ | ||
1721 | if (host->runtime_suspended) | ||
1722 | goto out; | ||
1723 | 1681 | ||
1724 | if (enable) | 1682 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
1725 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); | 1683 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
1726 | else | 1684 | mmiowb(); |
1727 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | 1685 | } |
1728 | out: | ||
1729 | mmiowb(); | ||
1730 | } | 1686 | } |
1731 | 1687 | ||
1732 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | 1688 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
@@ -1734,9 +1690,18 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |||
1734 | struct sdhci_host *host = mmc_priv(mmc); | 1690 | struct sdhci_host *host = mmc_priv(mmc); |
1735 | unsigned long flags; | 1691 | unsigned long flags; |
1736 | 1692 | ||
1693 | sdhci_runtime_pm_get(host); | ||
1694 | |||
1737 | spin_lock_irqsave(&host->lock, flags); | 1695 | spin_lock_irqsave(&host->lock, flags); |
1696 | if (enable) | ||
1697 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | ||
1698 | else | ||
1699 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | ||
1700 | |||
1738 | sdhci_enable_sdio_irq_nolock(host, enable); | 1701 | sdhci_enable_sdio_irq_nolock(host, enable); |
1739 | spin_unlock_irqrestore(&host->lock, flags); | 1702 | spin_unlock_irqrestore(&host->lock, flags); |
1703 | |||
1704 | sdhci_runtime_pm_put(host); | ||
1740 | } | 1705 | } |
1741 | 1706 | ||
1742 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, | 1707 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
@@ -1855,22 +1820,15 @@ static int sdhci_card_busy(struct mmc_host *mmc) | |||
1855 | 1820 | ||
1856 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) | 1821 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
1857 | { | 1822 | { |
1858 | struct sdhci_host *host; | 1823 | struct sdhci_host *host = mmc_priv(mmc); |
1859 | u16 ctrl; | 1824 | u16 ctrl; |
1860 | u32 ier; | ||
1861 | int tuning_loop_counter = MAX_TUNING_LOOP; | 1825 | int tuning_loop_counter = MAX_TUNING_LOOP; |
1862 | unsigned long timeout; | ||
1863 | int err = 0; | 1826 | int err = 0; |
1864 | bool requires_tuning_nonuhs = false; | ||
1865 | unsigned long flags; | 1827 | unsigned long flags; |
1866 | 1828 | ||
1867 | host = mmc_priv(mmc); | ||
1868 | |||
1869 | sdhci_runtime_pm_get(host); | 1829 | sdhci_runtime_pm_get(host); |
1870 | spin_lock_irqsave(&host->lock, flags); | 1830 | spin_lock_irqsave(&host->lock, flags); |
1871 | 1831 | ||
1872 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
1873 | |||
1874 | /* | 1832 | /* |
1875 | * The Host Controller needs tuning only in case of SDR104 mode | 1833 | * The Host Controller needs tuning only in case of SDR104 mode |
1876 | * and for SDR50 mode when Use Tuning for SDR50 is set in the | 1834 | * and for SDR50 mode when Use Tuning for SDR50 is set in the |
@@ -1878,15 +1836,18 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) | |||
1878 | * If the Host Controller supports the HS200 mode then the | 1836 | * If the Host Controller supports the HS200 mode then the |
1879 | * tuning function has to be executed. | 1837 | * tuning function has to be executed. |
1880 | */ | 1838 | */ |
1881 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && | 1839 | switch (host->timing) { |
1882 | (host->flags & SDHCI_SDR50_NEEDS_TUNING || | 1840 | case MMC_TIMING_MMC_HS200: |
1883 | host->flags & SDHCI_SDR104_NEEDS_TUNING)) | 1841 | case MMC_TIMING_UHS_SDR104: |
1884 | requires_tuning_nonuhs = true; | 1842 | break; |
1885 | 1843 | ||
1886 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || | 1844 | case MMC_TIMING_UHS_SDR50: |
1887 | requires_tuning_nonuhs) | 1845 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING || |
1888 | ctrl |= SDHCI_CTRL_EXEC_TUNING; | 1846 | host->flags & SDHCI_SDR104_NEEDS_TUNING) |
1889 | else { | 1847 | break; |
1848 | /* FALLTHROUGH */ | ||
1849 | |||
1850 | default: | ||
1890 | spin_unlock_irqrestore(&host->lock, flags); | 1851 | spin_unlock_irqrestore(&host->lock, flags); |
1891 | sdhci_runtime_pm_put(host); | 1852 | sdhci_runtime_pm_put(host); |
1892 | return 0; | 1853 | return 0; |
@@ -1899,6 +1860,8 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) | |||
1899 | return err; | 1860 | return err; |
1900 | } | 1861 | } |
1901 | 1862 | ||
1863 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
1864 | ctrl |= SDHCI_CTRL_EXEC_TUNING; | ||
1902 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | 1865 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1903 | 1866 | ||
1904 | /* | 1867 | /* |
@@ -1911,21 +1874,17 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) | |||
1911 | * to make sure we don't hit a controller bug, we _only_ | 1874 | * to make sure we don't hit a controller bug, we _only_ |
1912 | * enable Buffer Read Ready interrupt here. | 1875 | * enable Buffer Read Ready interrupt here. |
1913 | */ | 1876 | */ |
1914 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | 1877 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
1915 | sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); | 1878 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); |
1916 | 1879 | ||
1917 | /* | 1880 | /* |
1918 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | 1881 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number |
1919 | * of loops reaches 40 times or a timeout of 150ms occurs. | 1882 | * of loops reaches 40 times or a timeout of 150ms occurs. |
1920 | */ | 1883 | */ |
1921 | timeout = 150; | ||
1922 | do { | 1884 | do { |
1923 | struct mmc_command cmd = {0}; | 1885 | struct mmc_command cmd = {0}; |
1924 | struct mmc_request mrq = {NULL}; | 1886 | struct mmc_request mrq = {NULL}; |
1925 | 1887 | ||
1926 | if (!tuning_loop_counter && !timeout) | ||
1927 | break; | ||
1928 | |||
1929 | cmd.opcode = opcode; | 1888 | cmd.opcode = opcode; |
1930 | cmd.arg = 0; | 1889 | cmd.arg = 0; |
1931 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | 1890 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
@@ -1933,6 +1892,9 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) | |||
1933 | cmd.data = NULL; | 1892 | cmd.data = NULL; |
1934 | cmd.error = 0; | 1893 | cmd.error = 0; |
1935 | 1894 | ||
1895 | if (tuning_loop_counter-- == 0) | ||
1896 | break; | ||
1897 | |||
1936 | mrq.cmd = &cmd; | 1898 | mrq.cmd = &cmd; |
1937 | host->mrq = &mrq; | 1899 | host->mrq = &mrq; |
1938 | 1900 | ||
@@ -1990,26 +1952,25 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) | |||
1990 | host->tuning_done = 0; | 1952 | host->tuning_done = 0; |
1991 | 1953 | ||
1992 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | 1954 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1993 | tuning_loop_counter--; | 1955 | |
1994 | timeout--; | 1956 | /* eMMC spec does not require a delay between tuning cycles */ |
1995 | mdelay(1); | 1957 | if (opcode == MMC_SEND_TUNING_BLOCK) |
1958 | mdelay(1); | ||
1996 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); | 1959 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
1997 | 1960 | ||
1998 | /* | 1961 | /* |
1999 | * The Host Driver has exhausted the maximum number of loops allowed, | 1962 | * The Host Driver has exhausted the maximum number of loops allowed, |
2000 | * so use fixed sampling frequency. | 1963 | * so use fixed sampling frequency. |
2001 | */ | 1964 | */ |
2002 | if (!tuning_loop_counter || !timeout) { | 1965 | if (tuning_loop_counter < 0) { |
2003 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | 1966 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
2004 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | 1967 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1968 | } | ||
1969 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | ||
1970 | pr_info(DRIVER_NAME ": Tuning procedure" | ||
1971 | " failed, falling back to fixed sampling" | ||
1972 | " clock\n"); | ||
2005 | err = -EIO; | 1973 | err = -EIO; |
2006 | } else { | ||
2007 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | ||
2008 | pr_info(DRIVER_NAME ": Tuning procedure" | ||
2009 | " failed, falling back to fixed sampling" | ||
2010 | " clock\n"); | ||
2011 | err = -EIO; | ||
2012 | } | ||
2013 | } | 1974 | } |
2014 | 1975 | ||
2015 | out: | 1976 | out: |
@@ -2044,7 +2005,8 @@ out: | |||
2044 | if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) | 2005 | if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) |
2045 | err = 0; | 2006 | err = 0; |
2046 | 2007 | ||
2047 | sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); | 2008 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
2009 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
2048 | spin_unlock_irqrestore(&host->lock, flags); | 2010 | spin_unlock_irqrestore(&host->lock, flags); |
2049 | sdhci_runtime_pm_put(host); | 2011 | sdhci_runtime_pm_put(host); |
2050 | 2012 | ||
@@ -2054,26 +2016,30 @@ out: | |||
2054 | 2016 | ||
2055 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | 2017 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) |
2056 | { | 2018 | { |
2057 | u16 ctrl; | ||
2058 | |||
2059 | /* Host Controller v3.00 defines preset value registers */ | 2019 | /* Host Controller v3.00 defines preset value registers */ |
2060 | if (host->version < SDHCI_SPEC_300) | 2020 | if (host->version < SDHCI_SPEC_300) |
2061 | return; | 2021 | return; |
2062 | 2022 | ||
2063 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | ||
2064 | |||
2065 | /* | 2023 | /* |
2066 | * We only enable or disable Preset Value if they are not already | 2024 | * We only enable or disable Preset Value if they are not already |
2067 | * enabled or disabled respectively. Otherwise, we bail out. | 2025 | * enabled or disabled respectively. Otherwise, we bail out. |
2068 | */ | 2026 | */ |
2069 | if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | 2027 | if (host->preset_enabled != enable) { |
2070 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | 2028 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
2071 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | 2029 | |
2072 | host->flags |= SDHCI_PV_ENABLED; | 2030 | if (enable) |
2073 | } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | 2031 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; |
2074 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | 2032 | else |
2033 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | ||
2034 | |||
2075 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | 2035 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
2076 | host->flags &= ~SDHCI_PV_ENABLED; | 2036 | |
2037 | if (enable) | ||
2038 | host->flags |= SDHCI_PV_ENABLED; | ||
2039 | else | ||
2040 | host->flags &= ~SDHCI_PV_ENABLED; | ||
2041 | |||
2042 | host->preset_enabled = enable; | ||
2077 | } | 2043 | } |
2078 | } | 2044 | } |
2079 | 2045 | ||
@@ -2095,8 +2061,8 @@ static void sdhci_card_event(struct mmc_host *mmc) | |||
2095 | pr_err("%s: Resetting controller.\n", | 2061 | pr_err("%s: Resetting controller.\n", |
2096 | mmc_hostname(host->mmc)); | 2062 | mmc_hostname(host->mmc)); |
2097 | 2063 | ||
2098 | sdhci_reset(host, SDHCI_RESET_CMD); | 2064 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2099 | sdhci_reset(host, SDHCI_RESET_DATA); | 2065 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
2100 | 2066 | ||
2101 | host->mrq->cmd->error = -ENOMEDIUM; | 2067 | host->mrq->cmd->error = -ENOMEDIUM; |
2102 | tasklet_schedule(&host->finish_tasklet); | 2068 | tasklet_schedule(&host->finish_tasklet); |
@@ -2124,15 +2090,6 @@ static const struct mmc_host_ops sdhci_ops = { | |||
2124 | * * | 2090 | * * |
2125 | \*****************************************************************************/ | 2091 | \*****************************************************************************/ |
2126 | 2092 | ||
2127 | static void sdhci_tasklet_card(unsigned long param) | ||
2128 | { | ||
2129 | struct sdhci_host *host = (struct sdhci_host*)param; | ||
2130 | |||
2131 | sdhci_card_event(host->mmc); | ||
2132 | |||
2133 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | ||
2134 | } | ||
2135 | |||
2136 | static void sdhci_tasklet_finish(unsigned long param) | 2093 | static void sdhci_tasklet_finish(unsigned long param) |
2137 | { | 2094 | { |
2138 | struct sdhci_host *host; | 2095 | struct sdhci_host *host; |
@@ -2169,12 +2126,12 @@ static void sdhci_tasklet_finish(unsigned long param) | |||
2169 | /* Some controllers need this kick or reset won't work here */ | 2126 | /* Some controllers need this kick or reset won't work here */ |
2170 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) | 2127 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
2171 | /* This is to force an update */ | 2128 | /* This is to force an update */ |
2172 | sdhci_update_clock(host); | 2129 | host->ops->set_clock(host, host->clock); |
2173 | 2130 | ||
2174 | /* Spec says we should do both at the same time, but Ricoh | 2131 | /* Spec says we should do both at the same time, but Ricoh |
2175 | controllers do not like that. */ | 2132 | controllers do not like that. */ |
2176 | sdhci_reset(host, SDHCI_RESET_CMD); | 2133 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2177 | sdhci_reset(host, SDHCI_RESET_DATA); | 2134 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
2178 | } | 2135 | } |
2179 | 2136 | ||
2180 | host->mrq = NULL; | 2137 | host->mrq = NULL; |
@@ -2424,101 +2381,94 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |||
2424 | 2381 | ||
2425 | static irqreturn_t sdhci_irq(int irq, void *dev_id) | 2382 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
2426 | { | 2383 | { |
2427 | irqreturn_t result; | 2384 | irqreturn_t result = IRQ_NONE; |
2428 | struct sdhci_host *host = dev_id; | 2385 | struct sdhci_host *host = dev_id; |
2429 | u32 intmask, unexpected = 0; | 2386 | u32 intmask, mask, unexpected = 0; |
2430 | int cardint = 0, max_loops = 16; | 2387 | int max_loops = 16; |
2431 | 2388 | ||
2432 | spin_lock(&host->lock); | 2389 | spin_lock(&host->lock); |
2433 | 2390 | ||
2434 | if (host->runtime_suspended) { | 2391 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
2435 | spin_unlock(&host->lock); | 2392 | spin_unlock(&host->lock); |
2436 | return IRQ_NONE; | 2393 | return IRQ_NONE; |
2437 | } | 2394 | } |
2438 | 2395 | ||
2439 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); | 2396 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
2440 | |||
2441 | if (!intmask || intmask == 0xffffffff) { | 2397 | if (!intmask || intmask == 0xffffffff) { |
2442 | result = IRQ_NONE; | 2398 | result = IRQ_NONE; |
2443 | goto out; | 2399 | goto out; |
2444 | } | 2400 | } |
2445 | 2401 | ||
2446 | again: | 2402 | do { |
2447 | DBG("*** %s got interrupt: 0x%08x\n", | 2403 | /* Clear selected interrupts. */ |
2448 | mmc_hostname(host->mmc), intmask); | 2404 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
2449 | 2405 | SDHCI_INT_BUS_POWER); | |
2450 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { | 2406 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
2451 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | ||
2452 | SDHCI_CARD_PRESENT; | ||
2453 | |||
2454 | /* | ||
2455 | * There is a observation on i.mx esdhc. INSERT bit will be | ||
2456 | * immediately set again when it gets cleared, if a card is | ||
2457 | * inserted. We have to mask the irq to prevent interrupt | ||
2458 | * storm which will freeze the system. And the REMOVE gets | ||
2459 | * the same situation. | ||
2460 | * | ||
2461 | * More testing are needed here to ensure it works for other | ||
2462 | * platforms though. | ||
2463 | */ | ||
2464 | sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : | ||
2465 | SDHCI_INT_CARD_REMOVE); | ||
2466 | sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : | ||
2467 | SDHCI_INT_CARD_INSERT); | ||
2468 | |||
2469 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | ||
2470 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | ||
2471 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); | ||
2472 | tasklet_schedule(&host->card_tasklet); | ||
2473 | } | ||
2474 | |||
2475 | if (intmask & SDHCI_INT_CMD_MASK) { | ||
2476 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, | ||
2477 | SDHCI_INT_STATUS); | ||
2478 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); | ||
2479 | } | ||
2480 | 2407 | ||
2481 | if (intmask & SDHCI_INT_DATA_MASK) { | 2408 | DBG("*** %s got interrupt: 0x%08x\n", |
2482 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, | 2409 | mmc_hostname(host->mmc), intmask); |
2483 | SDHCI_INT_STATUS); | ||
2484 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | ||
2485 | } | ||
2486 | 2410 | ||
2487 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | 2411 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2412 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | ||
2413 | SDHCI_CARD_PRESENT; | ||
2488 | 2414 | ||
2489 | intmask &= ~SDHCI_INT_ERROR; | 2415 | /* |
2416 | * There is a observation on i.mx esdhc. INSERT | ||
2417 | * bit will be immediately set again when it gets | ||
2418 | * cleared, if a card is inserted. We have to mask | ||
2419 | * the irq to prevent interrupt storm which will | ||
2420 | * freeze the system. And the REMOVE gets the | ||
2421 | * same situation. | ||
2422 | * | ||
2423 | * More testing are needed here to ensure it works | ||
2424 | * for other platforms though. | ||
2425 | */ | ||
2426 | host->ier &= ~(SDHCI_INT_CARD_INSERT | | ||
2427 | SDHCI_INT_CARD_REMOVE); | ||
2428 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : | ||
2429 | SDHCI_INT_CARD_INSERT; | ||
2430 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | ||
2431 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
2432 | |||
2433 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | ||
2434 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | ||
2435 | |||
2436 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | | ||
2437 | SDHCI_INT_CARD_REMOVE); | ||
2438 | result = IRQ_WAKE_THREAD; | ||
2439 | } | ||
2490 | 2440 | ||
2491 | if (intmask & SDHCI_INT_BUS_POWER) { | 2441 | if (intmask & SDHCI_INT_CMD_MASK) |
2492 | pr_err("%s: Card is consuming too much power!\n", | 2442 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
2493 | mmc_hostname(host->mmc)); | ||
2494 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); | ||
2495 | } | ||
2496 | 2443 | ||
2497 | intmask &= ~SDHCI_INT_BUS_POWER; | 2444 | if (intmask & SDHCI_INT_DATA_MASK) |
2445 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | ||
2498 | 2446 | ||
2499 | if (intmask & SDHCI_INT_CARD_INT) | 2447 | if (intmask & SDHCI_INT_BUS_POWER) |
2500 | cardint = 1; | 2448 | pr_err("%s: Card is consuming too much power!\n", |
2449 | mmc_hostname(host->mmc)); | ||
2501 | 2450 | ||
2502 | intmask &= ~SDHCI_INT_CARD_INT; | 2451 | if (intmask & SDHCI_INT_CARD_INT) { |
2452 | sdhci_enable_sdio_irq_nolock(host, false); | ||
2453 | host->thread_isr |= SDHCI_INT_CARD_INT; | ||
2454 | result = IRQ_WAKE_THREAD; | ||
2455 | } | ||
2503 | 2456 | ||
2504 | if (intmask) { | 2457 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
2505 | unexpected |= intmask; | 2458 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
2506 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | 2459 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | |
2507 | } | 2460 | SDHCI_INT_CARD_INT); |
2508 | 2461 | ||
2509 | result = IRQ_HANDLED; | 2462 | if (intmask) { |
2463 | unexpected |= intmask; | ||
2464 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | ||
2465 | } | ||
2510 | 2466 | ||
2511 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); | 2467 | if (result == IRQ_NONE) |
2468 | result = IRQ_HANDLED; | ||
2512 | 2469 | ||
2513 | /* | 2470 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
2514 | * If we know we'll call the driver to signal SDIO IRQ, disregard | 2471 | } while (intmask && --max_loops); |
2515 | * further indications of Card Interrupt in the status to avoid a | ||
2516 | * needless loop. | ||
2517 | */ | ||
2518 | if (cardint) | ||
2519 | intmask &= ~SDHCI_INT_CARD_INT; | ||
2520 | if (intmask && --max_loops) | ||
2521 | goto again; | ||
2522 | out: | 2472 | out: |
2523 | spin_unlock(&host->lock); | 2473 | spin_unlock(&host->lock); |
2524 | 2474 | ||
@@ -2527,15 +2477,38 @@ out: | |||
2527 | mmc_hostname(host->mmc), unexpected); | 2477 | mmc_hostname(host->mmc), unexpected); |
2528 | sdhci_dumpregs(host); | 2478 | sdhci_dumpregs(host); |
2529 | } | 2479 | } |
2530 | /* | ||
2531 | * We have to delay this as it calls back into the driver. | ||
2532 | */ | ||
2533 | if (cardint) | ||
2534 | mmc_signal_sdio_irq(host->mmc); | ||
2535 | 2480 | ||
2536 | return result; | 2481 | return result; |
2537 | } | 2482 | } |
2538 | 2483 | ||
2484 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) | ||
2485 | { | ||
2486 | struct sdhci_host *host = dev_id; | ||
2487 | unsigned long flags; | ||
2488 | u32 isr; | ||
2489 | |||
2490 | spin_lock_irqsave(&host->lock, flags); | ||
2491 | isr = host->thread_isr; | ||
2492 | host->thread_isr = 0; | ||
2493 | spin_unlock_irqrestore(&host->lock, flags); | ||
2494 | |||
2495 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { | ||
2496 | sdhci_card_event(host->mmc); | ||
2497 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | ||
2498 | } | ||
2499 | |||
2500 | if (isr & SDHCI_INT_CARD_INT) { | ||
2501 | sdio_run_irqs(host->mmc); | ||
2502 | |||
2503 | spin_lock_irqsave(&host->lock, flags); | ||
2504 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) | ||
2505 | sdhci_enable_sdio_irq_nolock(host, true); | ||
2506 | spin_unlock_irqrestore(&host->lock, flags); | ||
2507 | } | ||
2508 | |||
2509 | return isr ? IRQ_HANDLED : IRQ_NONE; | ||
2510 | } | ||
2511 | |||
2539 | /*****************************************************************************\ | 2512 | /*****************************************************************************\ |
2540 | * * | 2513 | * * |
2541 | * Suspend/resume * | 2514 | * Suspend/resume * |
@@ -2572,9 +2545,6 @@ EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); | |||
2572 | 2545 | ||
2573 | int sdhci_suspend_host(struct sdhci_host *host) | 2546 | int sdhci_suspend_host(struct sdhci_host *host) |
2574 | { | 2547 | { |
2575 | if (host->ops->platform_suspend) | ||
2576 | host->ops->platform_suspend(host); | ||
2577 | |||
2578 | sdhci_disable_card_detection(host); | 2548 | sdhci_disable_card_detection(host); |
2579 | 2549 | ||
2580 | /* Disable tuning since we are suspending */ | 2550 | /* Disable tuning since we are suspending */ |
@@ -2584,7 +2554,9 @@ int sdhci_suspend_host(struct sdhci_host *host) | |||
2584 | } | 2554 | } |
2585 | 2555 | ||
2586 | if (!device_may_wakeup(mmc_dev(host->mmc))) { | 2556 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
2587 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); | 2557 | host->ier = 0; |
2558 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); | ||
2559 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | ||
2588 | free_irq(host->irq, host); | 2560 | free_irq(host->irq, host); |
2589 | } else { | 2561 | } else { |
2590 | sdhci_enable_irq_wakeups(host); | 2562 | sdhci_enable_irq_wakeups(host); |
@@ -2605,8 +2577,9 @@ int sdhci_resume_host(struct sdhci_host *host) | |||
2605 | } | 2577 | } |
2606 | 2578 | ||
2607 | if (!device_may_wakeup(mmc_dev(host->mmc))) { | 2579 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
2608 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, | 2580 | ret = request_threaded_irq(host->irq, sdhci_irq, |
2609 | mmc_hostname(host->mmc), host); | 2581 | sdhci_thread_irq, IRQF_SHARED, |
2582 | mmc_hostname(host->mmc), host); | ||
2610 | if (ret) | 2583 | if (ret) |
2611 | return ret; | 2584 | return ret; |
2612 | } else { | 2585 | } else { |
@@ -2628,9 +2601,6 @@ int sdhci_resume_host(struct sdhci_host *host) | |||
2628 | 2601 | ||
2629 | sdhci_enable_card_detection(host); | 2602 | sdhci_enable_card_detection(host); |
2630 | 2603 | ||
2631 | if (host->ops->platform_resume) | ||
2632 | host->ops->platform_resume(host); | ||
2633 | |||
2634 | /* Set the re-tuning expiration flag */ | 2604 | /* Set the re-tuning expiration flag */ |
2635 | if (host->flags & SDHCI_USING_RETUNING_TIMER) | 2605 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
2636 | host->flags |= SDHCI_NEEDS_RETUNING; | 2606 | host->flags |= SDHCI_NEEDS_RETUNING; |
@@ -2682,10 +2652,12 @@ int sdhci_runtime_suspend_host(struct sdhci_host *host) | |||
2682 | } | 2652 | } |
2683 | 2653 | ||
2684 | spin_lock_irqsave(&host->lock, flags); | 2654 | spin_lock_irqsave(&host->lock, flags); |
2685 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); | 2655 | host->ier &= SDHCI_INT_CARD_INT; |
2656 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | ||
2657 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | ||
2686 | spin_unlock_irqrestore(&host->lock, flags); | 2658 | spin_unlock_irqrestore(&host->lock, flags); |
2687 | 2659 | ||
2688 | synchronize_irq(host->irq); | 2660 | synchronize_hardirq(host->irq); |
2689 | 2661 | ||
2690 | spin_lock_irqsave(&host->lock, flags); | 2662 | spin_lock_irqsave(&host->lock, flags); |
2691 | host->runtime_suspended = true; | 2663 | host->runtime_suspended = true; |
@@ -2729,7 +2701,7 @@ int sdhci_runtime_resume_host(struct sdhci_host *host) | |||
2729 | host->runtime_suspended = false; | 2701 | host->runtime_suspended = false; |
2730 | 2702 | ||
2731 | /* Enable SDIO IRQ */ | 2703 | /* Enable SDIO IRQ */ |
2732 | if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) | 2704 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
2733 | sdhci_enable_sdio_irq_nolock(host, true); | 2705 | sdhci_enable_sdio_irq_nolock(host, true); |
2734 | 2706 | ||
2735 | /* Enable Card Detection */ | 2707 | /* Enable Card Detection */ |
@@ -2788,7 +2760,7 @@ int sdhci_add_host(struct sdhci_host *host) | |||
2788 | if (debug_quirks2) | 2760 | if (debug_quirks2) |
2789 | host->quirks2 = debug_quirks2; | 2761 | host->quirks2 = debug_quirks2; |
2790 | 2762 | ||
2791 | sdhci_reset(host, SDHCI_RESET_ALL); | 2763 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
2792 | 2764 | ||
2793 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); | 2765 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2794 | host->version = (host->version & SDHCI_SPEC_VER_MASK) | 2766 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
@@ -2848,15 +2820,29 @@ int sdhci_add_host(struct sdhci_host *host) | |||
2848 | * (128) and potentially one alignment transfer for | 2820 | * (128) and potentially one alignment transfer for |
2849 | * each of those entries. | 2821 | * each of those entries. |
2850 | */ | 2822 | */ |
2851 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | 2823 | host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc), |
2824 | ADMA_SIZE, &host->adma_addr, | ||
2825 | GFP_KERNEL); | ||
2852 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | 2826 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); |
2853 | if (!host->adma_desc || !host->align_buffer) { | 2827 | if (!host->adma_desc || !host->align_buffer) { |
2854 | kfree(host->adma_desc); | 2828 | dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, |
2829 | host->adma_desc, host->adma_addr); | ||
2855 | kfree(host->align_buffer); | 2830 | kfree(host->align_buffer); |
2856 | pr_warning("%s: Unable to allocate ADMA " | 2831 | pr_warning("%s: Unable to allocate ADMA " |
2857 | "buffers. Falling back to standard DMA.\n", | 2832 | "buffers. Falling back to standard DMA.\n", |
2858 | mmc_hostname(mmc)); | 2833 | mmc_hostname(mmc)); |
2859 | host->flags &= ~SDHCI_USE_ADMA; | 2834 | host->flags &= ~SDHCI_USE_ADMA; |
2835 | host->adma_desc = NULL; | ||
2836 | host->align_buffer = NULL; | ||
2837 | } else if (host->adma_addr & 3) { | ||
2838 | pr_warning("%s: unable to allocate aligned ADMA descriptor\n", | ||
2839 | mmc_hostname(mmc)); | ||
2840 | host->flags &= ~SDHCI_USE_ADMA; | ||
2841 | dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, | ||
2842 | host->adma_desc, host->adma_addr); | ||
2843 | kfree(host->align_buffer); | ||
2844 | host->adma_desc = NULL; | ||
2845 | host->align_buffer = NULL; | ||
2860 | } | 2846 | } |
2861 | } | 2847 | } |
2862 | 2848 | ||
@@ -2941,6 +2927,7 @@ int sdhci_add_host(struct sdhci_host *host) | |||
2941 | mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; | 2927 | mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; |
2942 | 2928 | ||
2943 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; | 2929 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
2930 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; | ||
2944 | 2931 | ||
2945 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | 2932 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) |
2946 | host->flags |= SDHCI_AUTO_CMD12; | 2933 | host->flags |= SDHCI_AUTO_CMD12; |
@@ -3212,8 +3199,6 @@ int sdhci_add_host(struct sdhci_host *host) | |||
3212 | /* | 3199 | /* |
3213 | * Init tasklets. | 3200 | * Init tasklets. |
3214 | */ | 3201 | */ |
3215 | tasklet_init(&host->card_tasklet, | ||
3216 | sdhci_tasklet_card, (unsigned long)host); | ||
3217 | tasklet_init(&host->finish_tasklet, | 3202 | tasklet_init(&host->finish_tasklet, |
3218 | sdhci_tasklet_finish, (unsigned long)host); | 3203 | sdhci_tasklet_finish, (unsigned long)host); |
3219 | 3204 | ||
@@ -3230,8 +3215,8 @@ int sdhci_add_host(struct sdhci_host *host) | |||
3230 | 3215 | ||
3231 | sdhci_init(host, 0); | 3216 | sdhci_init(host, 0); |
3232 | 3217 | ||
3233 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, | 3218 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
3234 | mmc_hostname(mmc), host); | 3219 | IRQF_SHARED, mmc_hostname(mmc), host); |
3235 | if (ret) { | 3220 | if (ret) { |
3236 | pr_err("%s: Failed to request IRQ %d: %d\n", | 3221 | pr_err("%s: Failed to request IRQ %d: %d\n", |
3237 | mmc_hostname(mmc), host->irq, ret); | 3222 | mmc_hostname(mmc), host->irq, ret); |
@@ -3273,12 +3258,12 @@ int sdhci_add_host(struct sdhci_host *host) | |||
3273 | 3258 | ||
3274 | #ifdef SDHCI_USE_LEDS_CLASS | 3259 | #ifdef SDHCI_USE_LEDS_CLASS |
3275 | reset: | 3260 | reset: |
3276 | sdhci_reset(host, SDHCI_RESET_ALL); | 3261 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
3277 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); | 3262 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3263 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | ||
3278 | free_irq(host->irq, host); | 3264 | free_irq(host->irq, host); |
3279 | #endif | 3265 | #endif |
3280 | untasklet: | 3266 | untasklet: |
3281 | tasklet_kill(&host->card_tasklet); | ||
3282 | tasklet_kill(&host->finish_tasklet); | 3267 | tasklet_kill(&host->finish_tasklet); |
3283 | 3268 | ||
3284 | return ret; | 3269 | return ret; |
@@ -3315,14 +3300,14 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) | |||
3315 | #endif | 3300 | #endif |
3316 | 3301 | ||
3317 | if (!dead) | 3302 | if (!dead) |
3318 | sdhci_reset(host, SDHCI_RESET_ALL); | 3303 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
3319 | 3304 | ||
3320 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); | 3305 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3306 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | ||
3321 | free_irq(host->irq, host); | 3307 | free_irq(host->irq, host); |
3322 | 3308 | ||
3323 | del_timer_sync(&host->timer); | 3309 | del_timer_sync(&host->timer); |
3324 | 3310 | ||
3325 | tasklet_kill(&host->card_tasklet); | ||
3326 | tasklet_kill(&host->finish_tasklet); | 3311 | tasklet_kill(&host->finish_tasklet); |
3327 | 3312 | ||
3328 | if (host->vmmc) { | 3313 | if (host->vmmc) { |
@@ -3335,7 +3320,9 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) | |||
3335 | regulator_put(host->vqmmc); | 3320 | regulator_put(host->vqmmc); |
3336 | } | 3321 | } |
3337 | 3322 | ||
3338 | kfree(host->adma_desc); | 3323 | if (host->adma_desc) |
3324 | dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, | ||
3325 | host->adma_desc, host->adma_addr); | ||
3339 | kfree(host->align_buffer); | 3326 | kfree(host->align_buffer); |
3340 | 3327 | ||
3341 | host->adma_desc = NULL; | 3328 | host->adma_desc = NULL; |
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0a3ed01887db..4a5cd5e3fa3e 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h | |||
@@ -281,18 +281,14 @@ struct sdhci_ops { | |||
281 | unsigned int (*get_max_clock)(struct sdhci_host *host); | 281 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
282 | unsigned int (*get_min_clock)(struct sdhci_host *host); | 282 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
283 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); | 283 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
284 | int (*platform_bus_width)(struct sdhci_host *host, | 284 | void (*set_bus_width)(struct sdhci_host *host, int width); |
285 | int width); | ||
286 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, | 285 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
287 | u8 power_mode); | 286 | u8 power_mode); |
288 | unsigned int (*get_ro)(struct sdhci_host *host); | 287 | unsigned int (*get_ro)(struct sdhci_host *host); |
289 | void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); | 288 | void (*reset)(struct sdhci_host *host, u8 mask); |
290 | void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); | ||
291 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); | 289 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); |
292 | int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); | 290 | void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
293 | void (*hw_reset)(struct sdhci_host *host); | 291 | void (*hw_reset)(struct sdhci_host *host); |
294 | void (*platform_suspend)(struct sdhci_host *host); | ||
295 | void (*platform_resume)(struct sdhci_host *host); | ||
296 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); | 292 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); |
297 | void (*platform_init)(struct sdhci_host *host); | 293 | void (*platform_init)(struct sdhci_host *host); |
298 | void (*card_event)(struct sdhci_host *host); | 294 | void (*card_event)(struct sdhci_host *host); |
@@ -397,6 +393,16 @@ extern void sdhci_remove_host(struct sdhci_host *host, int dead); | |||
397 | extern void sdhci_send_command(struct sdhci_host *host, | 393 | extern void sdhci_send_command(struct sdhci_host *host, |
398 | struct mmc_command *cmd); | 394 | struct mmc_command *cmd); |
399 | 395 | ||
396 | static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) | ||
397 | { | ||
398 | return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); | ||
399 | } | ||
400 | |||
401 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); | ||
402 | void sdhci_set_bus_width(struct sdhci_host *host, int width); | ||
403 | void sdhci_reset(struct sdhci_host *host, u8 mask); | ||
404 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); | ||
405 | |||
400 | #ifdef CONFIG_PM | 406 | #ifdef CONFIG_PM |
401 | extern int sdhci_suspend_host(struct sdhci_host *host); | 407 | extern int sdhci_suspend_host(struct sdhci_host *host); |
402 | extern int sdhci_resume_host(struct sdhci_host *host); | 408 | extern int sdhci_resume_host(struct sdhci_host *host); |
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 54730f4aac87..656fbba4c422 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c | |||
@@ -803,12 +803,13 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |||
803 | break; | 803 | break; |
804 | } | 804 | } |
805 | switch (host->timing) { | 805 | switch (host->timing) { |
806 | case MMC_TIMING_UHS_DDR50: | 806 | case MMC_TIMING_MMC_DDR52: |
807 | /* | 807 | /* |
808 | * MMC core will only set this timing, if the host | 808 | * MMC core will only set this timing, if the host |
809 | * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF | 809 | * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR |
810 | * implementations with this capability, e.g. sh73a0, | 810 | * capability. MMCIF implementations with this |
811 | * will have to set it in their platform data. | 811 | * capability, e.g. sh73a0, will have to set it |
812 | * in their platform data. | ||
812 | */ | 813 | */ |
813 | tmp |= CMD_SET_DARS; | 814 | tmp |= CMD_SET_DARS; |
814 | break; | 815 | break; |
diff --git a/drivers/mmc/host/usdhi6rol0.c b/drivers/mmc/host/usdhi6rol0.c new file mode 100644 index 000000000000..eb2bbbef19c6 --- /dev/null +++ b/drivers/mmc/host/usdhi6rol0.c | |||
@@ -0,0 +1,1847 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd. | ||
3 | * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of version 2 of the GNU General Public License as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #include <linux/clk.h> | ||
11 | #include <linux/delay.h> | ||
12 | #include <linux/device.h> | ||
13 | #include <linux/dma-mapping.h> | ||
14 | #include <linux/dmaengine.h> | ||
15 | #include <linux/highmem.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/io.h> | ||
18 | #include <linux/log2.h> | ||
19 | #include <linux/mmc/host.h> | ||
20 | #include <linux/mmc/mmc.h> | ||
21 | #include <linux/mmc/sd.h> | ||
22 | #include <linux/mmc/sdio.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/pagemap.h> | ||
25 | #include <linux/platform_device.h> | ||
26 | #include <linux/scatterlist.h> | ||
27 | #include <linux/string.h> | ||
28 | #include <linux/time.h> | ||
29 | #include <linux/virtio.h> | ||
30 | #include <linux/workqueue.h> | ||
31 | |||
32 | #define USDHI6_SD_CMD 0x0000 | ||
33 | #define USDHI6_SD_PORT_SEL 0x0004 | ||
34 | #define USDHI6_SD_ARG 0x0008 | ||
35 | #define USDHI6_SD_STOP 0x0010 | ||
36 | #define USDHI6_SD_SECCNT 0x0014 | ||
37 | #define USDHI6_SD_RSP10 0x0018 | ||
38 | #define USDHI6_SD_RSP32 0x0020 | ||
39 | #define USDHI6_SD_RSP54 0x0028 | ||
40 | #define USDHI6_SD_RSP76 0x0030 | ||
41 | #define USDHI6_SD_INFO1 0x0038 | ||
42 | #define USDHI6_SD_INFO2 0x003c | ||
43 | #define USDHI6_SD_INFO1_MASK 0x0040 | ||
44 | #define USDHI6_SD_INFO2_MASK 0x0044 | ||
45 | #define USDHI6_SD_CLK_CTRL 0x0048 | ||
46 | #define USDHI6_SD_SIZE 0x004c | ||
47 | #define USDHI6_SD_OPTION 0x0050 | ||
48 | #define USDHI6_SD_ERR_STS1 0x0058 | ||
49 | #define USDHI6_SD_ERR_STS2 0x005c | ||
50 | #define USDHI6_SD_BUF0 0x0060 | ||
51 | #define USDHI6_SDIO_MODE 0x0068 | ||
52 | #define USDHI6_SDIO_INFO1 0x006c | ||
53 | #define USDHI6_SDIO_INFO1_MASK 0x0070 | ||
54 | #define USDHI6_CC_EXT_MODE 0x01b0 | ||
55 | #define USDHI6_SOFT_RST 0x01c0 | ||
56 | #define USDHI6_VERSION 0x01c4 | ||
57 | #define USDHI6_HOST_MODE 0x01c8 | ||
58 | #define USDHI6_SDIF_MODE 0x01cc | ||
59 | |||
60 | #define USDHI6_SD_CMD_APP 0x0040 | ||
61 | #define USDHI6_SD_CMD_MODE_RSP_AUTO 0x0000 | ||
62 | #define USDHI6_SD_CMD_MODE_RSP_NONE 0x0300 | ||
63 | #define USDHI6_SD_CMD_MODE_RSP_R1 0x0400 /* Also R5, R6, R7 */ | ||
64 | #define USDHI6_SD_CMD_MODE_RSP_R1B 0x0500 /* R1b */ | ||
65 | #define USDHI6_SD_CMD_MODE_RSP_R2 0x0600 | ||
66 | #define USDHI6_SD_CMD_MODE_RSP_R3 0x0700 /* Also R4 */ | ||
67 | #define USDHI6_SD_CMD_DATA 0x0800 | ||
68 | #define USDHI6_SD_CMD_READ 0x1000 | ||
69 | #define USDHI6_SD_CMD_MULTI 0x2000 | ||
70 | #define USDHI6_SD_CMD_CMD12_AUTO_OFF 0x4000 | ||
71 | |||
72 | #define USDHI6_CC_EXT_MODE_SDRW BIT(1) | ||
73 | |||
74 | #define USDHI6_SD_INFO1_RSP_END BIT(0) | ||
75 | #define USDHI6_SD_INFO1_ACCESS_END BIT(2) | ||
76 | #define USDHI6_SD_INFO1_CARD_OUT BIT(3) | ||
77 | #define USDHI6_SD_INFO1_CARD_IN BIT(4) | ||
78 | #define USDHI6_SD_INFO1_CD BIT(5) | ||
79 | #define USDHI6_SD_INFO1_WP BIT(7) | ||
80 | #define USDHI6_SD_INFO1_D3_CARD_OUT BIT(8) | ||
81 | #define USDHI6_SD_INFO1_D3_CARD_IN BIT(9) | ||
82 | |||
83 | #define USDHI6_SD_INFO2_CMD_ERR BIT(0) | ||
84 | #define USDHI6_SD_INFO2_CRC_ERR BIT(1) | ||
85 | #define USDHI6_SD_INFO2_END_ERR BIT(2) | ||
86 | #define USDHI6_SD_INFO2_TOUT BIT(3) | ||
87 | #define USDHI6_SD_INFO2_IWA_ERR BIT(4) | ||
88 | #define USDHI6_SD_INFO2_IRA_ERR BIT(5) | ||
89 | #define USDHI6_SD_INFO2_RSP_TOUT BIT(6) | ||
90 | #define USDHI6_SD_INFO2_SDDAT0 BIT(7) | ||
91 | #define USDHI6_SD_INFO2_BRE BIT(8) | ||
92 | #define USDHI6_SD_INFO2_BWE BIT(9) | ||
93 | #define USDHI6_SD_INFO2_SCLKDIVEN BIT(13) | ||
94 | #define USDHI6_SD_INFO2_CBSY BIT(14) | ||
95 | #define USDHI6_SD_INFO2_ILA BIT(15) | ||
96 | |||
97 | #define USDHI6_SD_INFO1_CARD_INSERT (USDHI6_SD_INFO1_CARD_IN | USDHI6_SD_INFO1_D3_CARD_IN) | ||
98 | #define USDHI6_SD_INFO1_CARD_EJECT (USDHI6_SD_INFO1_CARD_OUT | USDHI6_SD_INFO1_D3_CARD_OUT) | ||
99 | #define USDHI6_SD_INFO1_CARD (USDHI6_SD_INFO1_CARD_INSERT | USDHI6_SD_INFO1_CARD_EJECT) | ||
100 | #define USDHI6_SD_INFO1_CARD_CD (USDHI6_SD_INFO1_CARD_IN | USDHI6_SD_INFO1_CARD_OUT) | ||
101 | |||
102 | #define USDHI6_SD_INFO2_ERR (USDHI6_SD_INFO2_CMD_ERR | \ | ||
103 | USDHI6_SD_INFO2_CRC_ERR | USDHI6_SD_INFO2_END_ERR | \ | ||
104 | USDHI6_SD_INFO2_TOUT | USDHI6_SD_INFO2_IWA_ERR | \ | ||
105 | USDHI6_SD_INFO2_IRA_ERR | USDHI6_SD_INFO2_RSP_TOUT | \ | ||
106 | USDHI6_SD_INFO2_ILA) | ||
107 | |||
108 | #define USDHI6_SD_INFO1_IRQ (USDHI6_SD_INFO1_RSP_END | USDHI6_SD_INFO1_ACCESS_END | \ | ||
109 | USDHI6_SD_INFO1_CARD) | ||
110 | |||
111 | #define USDHI6_SD_INFO2_IRQ (USDHI6_SD_INFO2_ERR | USDHI6_SD_INFO2_BRE | \ | ||
112 | USDHI6_SD_INFO2_BWE | 0x0800 | USDHI6_SD_INFO2_ILA) | ||
113 | |||
114 | #define USDHI6_SD_CLK_CTRL_SCLKEN BIT(8) | ||
115 | |||
116 | #define USDHI6_SD_STOP_STP BIT(0) | ||
117 | #define USDHI6_SD_STOP_SEC BIT(8) | ||
118 | |||
119 | #define USDHI6_SDIO_INFO1_IOIRQ BIT(0) | ||
120 | #define USDHI6_SDIO_INFO1_EXPUB52 BIT(14) | ||
121 | #define USDHI6_SDIO_INFO1_EXWT BIT(15) | ||
122 | |||
123 | #define USDHI6_SD_ERR_STS1_CRC_NO_ERROR BIT(13) | ||
124 | |||
125 | #define USDHI6_SOFT_RST_RESERVED (BIT(1) | BIT(2)) | ||
126 | #define USDHI6_SOFT_RST_RESET BIT(0) | ||
127 | |||
128 | #define USDHI6_SD_OPTION_TIMEOUT_SHIFT 4 | ||
129 | #define USDHI6_SD_OPTION_TIMEOUT_MASK (0xf << USDHI6_SD_OPTION_TIMEOUT_SHIFT) | ||
130 | #define USDHI6_SD_OPTION_WIDTH_1 BIT(15) | ||
131 | |||
132 | #define USDHI6_SD_PORT_SEL_PORTS_SHIFT 8 | ||
133 | |||
134 | #define USDHI6_SD_CLK_CTRL_DIV_MASK 0xff | ||
135 | |||
136 | #define USDHI6_SDIO_INFO1_IRQ (USDHI6_SDIO_INFO1_IOIRQ | 3 | \ | ||
137 | USDHI6_SDIO_INFO1_EXPUB52 | USDHI6_SDIO_INFO1_EXWT) | ||
138 | |||
139 | #define USDHI6_MIN_DMA 64 | ||
140 | |||
141 | enum usdhi6_wait_for { | ||
142 | USDHI6_WAIT_FOR_REQUEST, | ||
143 | USDHI6_WAIT_FOR_CMD, | ||
144 | USDHI6_WAIT_FOR_MREAD, | ||
145 | USDHI6_WAIT_FOR_MWRITE, | ||
146 | USDHI6_WAIT_FOR_READ, | ||
147 | USDHI6_WAIT_FOR_WRITE, | ||
148 | USDHI6_WAIT_FOR_DATA_END, | ||
149 | USDHI6_WAIT_FOR_STOP, | ||
150 | USDHI6_WAIT_FOR_DMA, | ||
151 | }; | ||
152 | |||
153 | struct usdhi6_page { | ||
154 | struct page *page; | ||
155 | void *mapped; /* mapped page */ | ||
156 | }; | ||
157 | |||
158 | struct usdhi6_host { | ||
159 | struct mmc_host *mmc; | ||
160 | struct mmc_request *mrq; | ||
161 | void __iomem *base; | ||
162 | struct clk *clk; | ||
163 | |||
164 | /* SG memory handling */ | ||
165 | |||
166 | /* Common for multiple and single block requests */ | ||
167 | struct usdhi6_page pg; /* current page from an SG */ | ||
168 | void *blk_page; /* either a mapped page, or the bounce buffer */ | ||
169 | size_t offset; /* offset within a page, including sg->offset */ | ||
170 | |||
171 | /* Blocks, crossing a page boundary */ | ||
172 | size_t head_len; | ||
173 | struct usdhi6_page head_pg; | ||
174 | |||
175 | /* A bounce buffer for unaligned blocks or blocks, crossing a page boundary */ | ||
176 | struct scatterlist bounce_sg; | ||
177 | u8 bounce_buf[512]; | ||
178 | |||
179 | /* Multiple block requests only */ | ||
180 | struct scatterlist *sg; /* current SG segment */ | ||
181 | int page_idx; /* page index within an SG segment */ | ||
182 | |||
183 | enum usdhi6_wait_for wait; | ||
184 | u32 status_mask; | ||
185 | u32 status2_mask; | ||
186 | u32 sdio_mask; | ||
187 | u32 io_error; | ||
188 | u32 irq_status; | ||
189 | unsigned long imclk; | ||
190 | unsigned long rate; | ||
191 | bool app_cmd; | ||
192 | |||
193 | /* Timeout handling */ | ||
194 | struct delayed_work timeout_work; | ||
195 | unsigned long timeout; | ||
196 | |||
197 | /* DMA support */ | ||
198 | struct dma_chan *chan_rx; | ||
199 | struct dma_chan *chan_tx; | ||
200 | bool dma_active; | ||
201 | }; | ||
202 | |||
203 | /* I/O primitives */ | ||
204 | |||
205 | static void usdhi6_write(struct usdhi6_host *host, u32 reg, u32 data) | ||
206 | { | ||
207 | iowrite32(data, host->base + reg); | ||
208 | dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__, | ||
209 | host->base, reg, data); | ||
210 | } | ||
211 | |||
212 | static void usdhi6_write16(struct usdhi6_host *host, u32 reg, u16 data) | ||
213 | { | ||
214 | iowrite16(data, host->base + reg); | ||
215 | dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__, | ||
216 | host->base, reg, data); | ||
217 | } | ||
218 | |||
219 | static u32 usdhi6_read(struct usdhi6_host *host, u32 reg) | ||
220 | { | ||
221 | u32 data = ioread32(host->base + reg); | ||
222 | dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__, | ||
223 | host->base, reg, data); | ||
224 | return data; | ||
225 | } | ||
226 | |||
227 | static u16 usdhi6_read16(struct usdhi6_host *host, u32 reg) | ||
228 | { | ||
229 | u16 data = ioread16(host->base + reg); | ||
230 | dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__, | ||
231 | host->base, reg, data); | ||
232 | return data; | ||
233 | } | ||
234 | |||
235 | static void usdhi6_irq_enable(struct usdhi6_host *host, u32 info1, u32 info2) | ||
236 | { | ||
237 | host->status_mask = USDHI6_SD_INFO1_IRQ & ~info1; | ||
238 | host->status2_mask = USDHI6_SD_INFO2_IRQ & ~info2; | ||
239 | usdhi6_write(host, USDHI6_SD_INFO1_MASK, host->status_mask); | ||
240 | usdhi6_write(host, USDHI6_SD_INFO2_MASK, host->status2_mask); | ||
241 | } | ||
242 | |||
243 | static void usdhi6_wait_for_resp(struct usdhi6_host *host) | ||
244 | { | ||
245 | usdhi6_irq_enable(host, USDHI6_SD_INFO1_RSP_END | | ||
246 | USDHI6_SD_INFO1_ACCESS_END | USDHI6_SD_INFO1_CARD_CD, | ||
247 | USDHI6_SD_INFO2_ERR); | ||
248 | } | ||
249 | |||
250 | static void usdhi6_wait_for_brwe(struct usdhi6_host *host, bool read) | ||
251 | { | ||
252 | usdhi6_irq_enable(host, USDHI6_SD_INFO1_ACCESS_END | | ||
253 | USDHI6_SD_INFO1_CARD_CD, USDHI6_SD_INFO2_ERR | | ||
254 | (read ? USDHI6_SD_INFO2_BRE : USDHI6_SD_INFO2_BWE)); | ||
255 | } | ||
256 | |||
257 | static void usdhi6_only_cd(struct usdhi6_host *host) | ||
258 | { | ||
259 | /* Mask all except card hotplug */ | ||
260 | usdhi6_irq_enable(host, USDHI6_SD_INFO1_CARD_CD, 0); | ||
261 | } | ||
262 | |||
263 | static void usdhi6_mask_all(struct usdhi6_host *host) | ||
264 | { | ||
265 | usdhi6_irq_enable(host, 0, 0); | ||
266 | } | ||
267 | |||
268 | static int usdhi6_error_code(struct usdhi6_host *host) | ||
269 | { | ||
270 | u32 err; | ||
271 | |||
272 | usdhi6_write(host, USDHI6_SD_STOP, USDHI6_SD_STOP_STP); | ||
273 | |||
274 | if (host->io_error & | ||
275 | (USDHI6_SD_INFO2_RSP_TOUT | USDHI6_SD_INFO2_TOUT)) { | ||
276 | u32 rsp54 = usdhi6_read(host, USDHI6_SD_RSP54); | ||
277 | int opc = host->mrq ? host->mrq->cmd->opcode : -1; | ||
278 | |||
279 | err = usdhi6_read(host, USDHI6_SD_ERR_STS2); | ||
280 | /* Response timeout is often normal, don't spam the log */ | ||
281 | if (host->wait == USDHI6_WAIT_FOR_CMD) | ||
282 | dev_dbg(mmc_dev(host->mmc), | ||
283 | "T-out sts 0x%x, resp 0x%x, state %u, CMD%d\n", | ||
284 | err, rsp54, host->wait, opc); | ||
285 | else | ||
286 | dev_warn(mmc_dev(host->mmc), | ||
287 | "T-out sts 0x%x, resp 0x%x, state %u, CMD%d\n", | ||
288 | err, rsp54, host->wait, opc); | ||
289 | return -ETIMEDOUT; | ||
290 | } | ||
291 | |||
292 | err = usdhi6_read(host, USDHI6_SD_ERR_STS1); | ||
293 | if (err != USDHI6_SD_ERR_STS1_CRC_NO_ERROR) | ||
294 | dev_warn(mmc_dev(host->mmc), "Err sts 0x%x, state %u, CMD%d\n", | ||
295 | err, host->wait, host->mrq ? host->mrq->cmd->opcode : -1); | ||
296 | if (host->io_error & USDHI6_SD_INFO2_ILA) | ||
297 | return -EILSEQ; | ||
298 | |||
299 | return -EIO; | ||
300 | } | ||
301 | |||
302 | /* Scatter-Gather management */ | ||
303 | |||
304 | /* | ||
305 | * In PIO mode we have to map each page separately, using kmap(). That way | ||
306 | * adjacent pages are mapped to non-adjacent virtual addresses. That's why we | ||
307 | * have to use a bounce buffer for blocks, crossing page boundaries. Such blocks | ||
308 | * have been observed with an SDIO WiFi card (b43 driver). | ||
309 | */ | ||
310 | static void usdhi6_blk_bounce(struct usdhi6_host *host, | ||
311 | struct scatterlist *sg) | ||
312 | { | ||
313 | struct mmc_data *data = host->mrq->data; | ||
314 | size_t blk_head = host->head_len; | ||
315 | |||
316 | dev_dbg(mmc_dev(host->mmc), "%s(): CMD%u of %u SG: %ux%u @ 0x%x\n", | ||
317 | __func__, host->mrq->cmd->opcode, data->sg_len, | ||
318 | data->blksz, data->blocks, sg->offset); | ||
319 | |||
320 | host->head_pg.page = host->pg.page; | ||
321 | host->head_pg.mapped = host->pg.mapped; | ||
322 | host->pg.page = nth_page(host->pg.page, 1); | ||
323 | host->pg.mapped = kmap(host->pg.page); | ||
324 | |||
325 | host->blk_page = host->bounce_buf; | ||
326 | host->offset = 0; | ||
327 | |||
328 | if (data->flags & MMC_DATA_READ) | ||
329 | return; | ||
330 | |||
331 | memcpy(host->bounce_buf, host->head_pg.mapped + PAGE_SIZE - blk_head, | ||
332 | blk_head); | ||
333 | memcpy(host->bounce_buf + blk_head, host->pg.mapped, | ||
334 | data->blksz - blk_head); | ||
335 | } | ||
336 | |||
337 | /* Only called for multiple block IO */ | ||
338 | static void usdhi6_sg_prep(struct usdhi6_host *host) | ||
339 | { | ||
340 | struct mmc_request *mrq = host->mrq; | ||
341 | struct mmc_data *data = mrq->data; | ||
342 | |||
343 | usdhi6_write(host, USDHI6_SD_SECCNT, data->blocks); | ||
344 | |||
345 | host->sg = data->sg; | ||
346 | /* TODO: if we always map, this is redundant */ | ||
347 | host->offset = host->sg->offset; | ||
348 | } | ||
349 | |||
350 | /* Map the first page in an SG segment: common for multiple and single block IO */ | ||
351 | static void *usdhi6_sg_map(struct usdhi6_host *host) | ||
352 | { | ||
353 | struct mmc_data *data = host->mrq->data; | ||
354 | struct scatterlist *sg = data->sg_len > 1 ? host->sg : data->sg; | ||
355 | size_t head = PAGE_SIZE - sg->offset; | ||
356 | size_t blk_head = head % data->blksz; | ||
357 | |||
358 | WARN(host->pg.page, "%p not properly unmapped!\n", host->pg.page); | ||
359 | if (WARN(sg_dma_len(sg) % data->blksz, | ||
360 | "SG size %zd isn't a multiple of block size %zd\n", | ||
361 | sg_dma_len(sg), data->blksz)) | ||
362 | return NULL; | ||
363 | |||
364 | host->pg.page = sg_page(sg); | ||
365 | host->pg.mapped = kmap(host->pg.page); | ||
366 | host->offset = sg->offset; | ||
367 | |||
368 | /* | ||
369 | * Block size must be a power of 2 for multi-block transfers, | ||
370 | * therefore blk_head is equal for all pages in this SG | ||
371 | */ | ||
372 | host->head_len = blk_head; | ||
373 | |||
374 | if (head < data->blksz) | ||
375 | /* | ||
376 | * The first block in the SG crosses a page boundary. | ||
377 | * Max blksz = 512, so blocks can only span 2 pages | ||
378 | */ | ||
379 | usdhi6_blk_bounce(host, sg); | ||
380 | else | ||
381 | host->blk_page = host->pg.mapped; | ||
382 | |||
383 | dev_dbg(mmc_dev(host->mmc), "Mapped %p (%lx) at %p + %u for CMD%u @ 0x%p\n", | ||
384 | host->pg.page, page_to_pfn(host->pg.page), host->pg.mapped, | ||
385 | sg->offset, host->mrq->cmd->opcode, host->mrq); | ||
386 | |||
387 | return host->blk_page + host->offset; | ||
388 | } | ||
389 | |||
390 | /* Unmap the current page: common for multiple and single block IO */ | ||
391 | static void usdhi6_sg_unmap(struct usdhi6_host *host, bool force) | ||
392 | { | ||
393 | struct mmc_data *data = host->mrq->data; | ||
394 | struct page *page = host->head_pg.page; | ||
395 | |||
396 | if (page) { | ||
397 | /* Previous block was cross-page boundary */ | ||
398 | struct scatterlist *sg = data->sg_len > 1 ? | ||
399 | host->sg : data->sg; | ||
400 | size_t blk_head = host->head_len; | ||
401 | |||
402 | if (!data->error && data->flags & MMC_DATA_READ) { | ||
403 | memcpy(host->head_pg.mapped + PAGE_SIZE - blk_head, | ||
404 | host->bounce_buf, blk_head); | ||
405 | memcpy(host->pg.mapped, host->bounce_buf + blk_head, | ||
406 | data->blksz - blk_head); | ||
407 | } | ||
408 | |||
409 | flush_dcache_page(page); | ||
410 | kunmap(page); | ||
411 | |||
412 | host->head_pg.page = NULL; | ||
413 | |||
414 | if (!force && sg_dma_len(sg) + sg->offset > | ||
415 | (host->page_idx << PAGE_SHIFT) + data->blksz - blk_head) | ||
416 | /* More blocks in this SG, don't unmap the next page */ | ||
417 | return; | ||
418 | } | ||
419 | |||
420 | page = host->pg.page; | ||
421 | if (!page) | ||
422 | return; | ||
423 | |||
424 | flush_dcache_page(page); | ||
425 | kunmap(page); | ||
426 | |||
427 | host->pg.page = NULL; | ||
428 | } | ||
429 | |||
430 | /* Called from MMC_WRITE_MULTIPLE_BLOCK or MMC_READ_MULTIPLE_BLOCK */ | ||
431 | static void usdhi6_sg_advance(struct usdhi6_host *host) | ||
432 | { | ||
433 | struct mmc_data *data = host->mrq->data; | ||
434 | size_t done, total; | ||
435 | |||
436 | /* New offset: set at the end of the previous block */ | ||
437 | if (host->head_pg.page) { | ||
438 | /* Finished a cross-page block, jump to the new page */ | ||
439 | host->page_idx++; | ||
440 | host->offset = data->blksz - host->head_len; | ||
441 | host->blk_page = host->pg.mapped; | ||
442 | usdhi6_sg_unmap(host, false); | ||
443 | } else { | ||
444 | host->offset += data->blksz; | ||
445 | /* The completed block didn't cross a page boundary */ | ||
446 | if (host->offset == PAGE_SIZE) { | ||
447 | /* If required, we'll map the page below */ | ||
448 | host->offset = 0; | ||
449 | host->page_idx++; | ||
450 | } | ||
451 | } | ||
452 | |||
453 | /* | ||
454 | * Now host->blk_page + host->offset point at the end of our last block | ||
455 | * and host->page_idx is the index of the page, in which our new block | ||
456 | * is located, if any | ||
457 | */ | ||
458 | |||
459 | done = (host->page_idx << PAGE_SHIFT) + host->offset; | ||
460 | total = host->sg->offset + sg_dma_len(host->sg); | ||
461 | |||
462 | dev_dbg(mmc_dev(host->mmc), "%s(): %zu of %zu @ %u\n", __func__, | ||
463 | done, total, host->offset); | ||
464 | |||
465 | if (done < total && host->offset) { | ||
466 | /* More blocks in this page */ | ||
467 | if (host->offset + data->blksz > PAGE_SIZE) | ||
468 | /* We approached at a block, that spans 2 pages */ | ||
469 | usdhi6_blk_bounce(host, host->sg); | ||
470 | |||
471 | return; | ||
472 | } | ||
473 | |||
474 | /* Finished current page or an SG segment */ | ||
475 | usdhi6_sg_unmap(host, false); | ||
476 | |||
477 | if (done == total) { | ||
478 | /* | ||
479 | * End of an SG segment or the complete SG: jump to the next | ||
480 | * segment, we'll map it later in usdhi6_blk_read() or | ||
481 | * usdhi6_blk_write() | ||
482 | */ | ||
483 | struct scatterlist *next = sg_next(host->sg); | ||
484 | |||
485 | host->page_idx = 0; | ||
486 | |||
487 | if (!next) | ||
488 | host->wait = USDHI6_WAIT_FOR_DATA_END; | ||
489 | host->sg = next; | ||
490 | |||
491 | if (WARN(next && sg_dma_len(next) % data->blksz, | ||
492 | "SG size %zd isn't a multiple of block size %zd\n", | ||
493 | sg_dma_len(next), data->blksz)) | ||
494 | data->error = -EINVAL; | ||
495 | |||
496 | return; | ||
497 | } | ||
498 | |||
499 | /* We cannot get here after crossing a page border */ | ||
500 | |||
501 | /* Next page in the same SG */ | ||
502 | host->pg.page = nth_page(sg_page(host->sg), host->page_idx); | ||
503 | host->pg.mapped = kmap(host->pg.page); | ||
504 | host->blk_page = host->pg.mapped; | ||
505 | |||
506 | dev_dbg(mmc_dev(host->mmc), "Mapped %p (%lx) at %p for CMD%u @ 0x%p\n", | ||
507 | host->pg.page, page_to_pfn(host->pg.page), host->pg.mapped, | ||
508 | host->mrq->cmd->opcode, host->mrq); | ||
509 | } | ||
510 | |||
511 | /* DMA handling */ | ||
512 | |||
513 | static void usdhi6_dma_release(struct usdhi6_host *host) | ||
514 | { | ||
515 | host->dma_active = false; | ||
516 | if (host->chan_tx) { | ||
517 | struct dma_chan *chan = host->chan_tx; | ||
518 | host->chan_tx = NULL; | ||
519 | dma_release_channel(chan); | ||
520 | } | ||
521 | if (host->chan_rx) { | ||
522 | struct dma_chan *chan = host->chan_rx; | ||
523 | host->chan_rx = NULL; | ||
524 | dma_release_channel(chan); | ||
525 | } | ||
526 | } | ||
527 | |||
528 | static void usdhi6_dma_stop_unmap(struct usdhi6_host *host) | ||
529 | { | ||
530 | struct mmc_data *data = host->mrq->data; | ||
531 | |||
532 | if (!host->dma_active) | ||
533 | return; | ||
534 | |||
535 | usdhi6_write(host, USDHI6_CC_EXT_MODE, 0); | ||
536 | host->dma_active = false; | ||
537 | |||
538 | if (data->flags & MMC_DATA_READ) | ||
539 | dma_unmap_sg(host->chan_rx->device->dev, data->sg, | ||
540 | data->sg_len, DMA_FROM_DEVICE); | ||
541 | else | ||
542 | dma_unmap_sg(host->chan_tx->device->dev, data->sg, | ||
543 | data->sg_len, DMA_TO_DEVICE); | ||
544 | } | ||
545 | |||
546 | static void usdhi6_dma_complete(void *arg) | ||
547 | { | ||
548 | struct usdhi6_host *host = arg; | ||
549 | struct mmc_request *mrq = host->mrq; | ||
550 | |||
551 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion for %p!\n", | ||
552 | dev_name(mmc_dev(host->mmc)), mrq)) | ||
553 | return; | ||
554 | |||
555 | dev_dbg(mmc_dev(host->mmc), "%s(): CMD%u DMA completed\n", __func__, | ||
556 | mrq->cmd->opcode); | ||
557 | |||
558 | usdhi6_dma_stop_unmap(host); | ||
559 | usdhi6_wait_for_brwe(host, mrq->data->flags & MMC_DATA_READ); | ||
560 | } | ||
561 | |||
562 | static int usdhi6_dma_setup(struct usdhi6_host *host, struct dma_chan *chan, | ||
563 | enum dma_transfer_direction dir) | ||
564 | { | ||
565 | struct mmc_data *data = host->mrq->data; | ||
566 | struct scatterlist *sg = data->sg; | ||
567 | struct dma_async_tx_descriptor *desc = NULL; | ||
568 | dma_cookie_t cookie = -EINVAL; | ||
569 | enum dma_data_direction data_dir; | ||
570 | int ret; | ||
571 | |||
572 | switch (dir) { | ||
573 | case DMA_MEM_TO_DEV: | ||
574 | data_dir = DMA_TO_DEVICE; | ||
575 | break; | ||
576 | case DMA_DEV_TO_MEM: | ||
577 | data_dir = DMA_FROM_DEVICE; | ||
578 | break; | ||
579 | default: | ||
580 | return -EINVAL; | ||
581 | } | ||
582 | |||
583 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, data_dir); | ||
584 | if (ret > 0) { | ||
585 | host->dma_active = true; | ||
586 | desc = dmaengine_prep_slave_sg(chan, sg, ret, dir, | ||
587 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
588 | } | ||
589 | |||
590 | if (desc) { | ||
591 | desc->callback = usdhi6_dma_complete; | ||
592 | desc->callback_param = host; | ||
593 | cookie = dmaengine_submit(desc); | ||
594 | } | ||
595 | |||
596 | dev_dbg(mmc_dev(host->mmc), "%s(): mapped %d -> %d, cookie %d @ %p\n", | ||
597 | __func__, data->sg_len, ret, cookie, desc); | ||
598 | |||
599 | if (cookie < 0) { | ||
600 | /* DMA failed, fall back to PIO */ | ||
601 | if (ret >= 0) | ||
602 | ret = cookie; | ||
603 | usdhi6_dma_release(host); | ||
604 | dev_warn(mmc_dev(host->mmc), | ||
605 | "DMA failed: %d, falling back to PIO\n", ret); | ||
606 | } | ||
607 | |||
608 | return cookie; | ||
609 | } | ||
610 | |||
611 | static int usdhi6_dma_start(struct usdhi6_host *host) | ||
612 | { | ||
613 | if (!host->chan_rx || !host->chan_tx) | ||
614 | return -ENODEV; | ||
615 | |||
616 | if (host->mrq->data->flags & MMC_DATA_READ) | ||
617 | return usdhi6_dma_setup(host, host->chan_rx, DMA_DEV_TO_MEM); | ||
618 | |||
619 | return usdhi6_dma_setup(host, host->chan_tx, DMA_MEM_TO_DEV); | ||
620 | } | ||
621 | |||
622 | static void usdhi6_dma_kill(struct usdhi6_host *host) | ||
623 | { | ||
624 | struct mmc_data *data = host->mrq->data; | ||
625 | |||
626 | dev_dbg(mmc_dev(host->mmc), "%s(): SG of %u: %ux%u\n", | ||
627 | __func__, data->sg_len, data->blocks, data->blksz); | ||
628 | /* Abort DMA */ | ||
629 | if (data->flags & MMC_DATA_READ) | ||
630 | dmaengine_terminate_all(host->chan_rx); | ||
631 | else | ||
632 | dmaengine_terminate_all(host->chan_tx); | ||
633 | } | ||
634 | |||
635 | static void usdhi6_dma_check_error(struct usdhi6_host *host) | ||
636 | { | ||
637 | struct mmc_data *data = host->mrq->data; | ||
638 | |||
639 | dev_dbg(mmc_dev(host->mmc), "%s(): IO error %d, status 0x%x\n", | ||
640 | __func__, host->io_error, usdhi6_read(host, USDHI6_SD_INFO1)); | ||
641 | |||
642 | if (host->io_error) { | ||
643 | data->error = usdhi6_error_code(host); | ||
644 | data->bytes_xfered = 0; | ||
645 | usdhi6_dma_kill(host); | ||
646 | usdhi6_dma_release(host); | ||
647 | dev_warn(mmc_dev(host->mmc), | ||
648 | "DMA failed: %d, falling back to PIO\n", data->error); | ||
649 | return; | ||
650 | } | ||
651 | |||
652 | /* | ||
653 | * The datasheet tells us to check a response from the card, whereas | ||
654 | * responses only come after the command phase, not after the data | ||
655 | * phase. Let's check anyway. | ||
656 | */ | ||
657 | if (host->irq_status & USDHI6_SD_INFO1_RSP_END) | ||
658 | dev_warn(mmc_dev(host->mmc), "Unexpected response received!\n"); | ||
659 | } | ||
660 | |||
661 | static void usdhi6_dma_kick(struct usdhi6_host *host) | ||
662 | { | ||
663 | if (host->mrq->data->flags & MMC_DATA_READ) | ||
664 | dma_async_issue_pending(host->chan_rx); | ||
665 | else | ||
666 | dma_async_issue_pending(host->chan_tx); | ||
667 | } | ||
668 | |||
669 | static void usdhi6_dma_request(struct usdhi6_host *host, phys_addr_t start) | ||
670 | { | ||
671 | struct dma_slave_config cfg = { | ||
672 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | ||
673 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | ||
674 | }; | ||
675 | int ret; | ||
676 | |||
677 | host->chan_tx = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); | ||
678 | dev_dbg(mmc_dev(host->mmc), "%s: TX: got channel %p\n", __func__, | ||
679 | host->chan_tx); | ||
680 | |||
681 | if (!host->chan_tx) | ||
682 | return; | ||
683 | |||
684 | cfg.direction = DMA_MEM_TO_DEV; | ||
685 | cfg.dst_addr = start + USDHI6_SD_BUF0; | ||
686 | cfg.dst_maxburst = 128; /* 128 words * 4 bytes = 512 bytes */ | ||
687 | cfg.src_addr = 0; | ||
688 | ret = dmaengine_slave_config(host->chan_tx, &cfg); | ||
689 | if (ret < 0) | ||
690 | goto e_release_tx; | ||
691 | |||
692 | host->chan_rx = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); | ||
693 | dev_dbg(mmc_dev(host->mmc), "%s: RX: got channel %p\n", __func__, | ||
694 | host->chan_rx); | ||
695 | |||
696 | if (!host->chan_rx) | ||
697 | goto e_release_tx; | ||
698 | |||
699 | cfg.direction = DMA_DEV_TO_MEM; | ||
700 | cfg.src_addr = cfg.dst_addr; | ||
701 | cfg.src_maxburst = 128; /* 128 words * 4 bytes = 512 bytes */ | ||
702 | cfg.dst_addr = 0; | ||
703 | ret = dmaengine_slave_config(host->chan_rx, &cfg); | ||
704 | if (ret < 0) | ||
705 | goto e_release_rx; | ||
706 | |||
707 | return; | ||
708 | |||
709 | e_release_rx: | ||
710 | dma_release_channel(host->chan_rx); | ||
711 | host->chan_rx = NULL; | ||
712 | e_release_tx: | ||
713 | dma_release_channel(host->chan_tx); | ||
714 | host->chan_tx = NULL; | ||
715 | } | ||
716 | |||
717 | /* API helpers */ | ||
718 | |||
719 | static void usdhi6_clk_set(struct usdhi6_host *host, struct mmc_ios *ios) | ||
720 | { | ||
721 | unsigned long rate = ios->clock; | ||
722 | u32 val; | ||
723 | unsigned int i; | ||
724 | |||
725 | for (i = 1000; i; i--) { | ||
726 | if (usdhi6_read(host, USDHI6_SD_INFO2) & USDHI6_SD_INFO2_SCLKDIVEN) | ||
727 | break; | ||
728 | usleep_range(10, 100); | ||
729 | } | ||
730 | |||
731 | if (!i) { | ||
732 | dev_err(mmc_dev(host->mmc), "SD bus busy, clock set aborted\n"); | ||
733 | return; | ||
734 | } | ||
735 | |||
736 | val = usdhi6_read(host, USDHI6_SD_CLK_CTRL) & ~USDHI6_SD_CLK_CTRL_DIV_MASK; | ||
737 | |||
738 | if (rate) { | ||
739 | unsigned long new_rate; | ||
740 | |||
741 | if (host->imclk <= rate) { | ||
742 | if (ios->timing != MMC_TIMING_UHS_DDR50) { | ||
743 | /* Cannot have 1-to-1 clock in DDR mode */ | ||
744 | new_rate = host->imclk; | ||
745 | val |= 0xff; | ||
746 | } else { | ||
747 | new_rate = host->imclk / 2; | ||
748 | } | ||
749 | } else { | ||
750 | unsigned long div = | ||
751 | roundup_pow_of_two(DIV_ROUND_UP(host->imclk, rate)); | ||
752 | val |= div >> 2; | ||
753 | new_rate = host->imclk / div; | ||
754 | } | ||
755 | |||
756 | if (host->rate == new_rate) | ||
757 | return; | ||
758 | |||
759 | host->rate = new_rate; | ||
760 | |||
761 | dev_dbg(mmc_dev(host->mmc), "target %lu, div %u, set %lu\n", | ||
762 | rate, (val & 0xff) << 2, new_rate); | ||
763 | } | ||
764 | |||
765 | /* | ||
766 | * if old or new rate is equal to input rate, have to switch the clock | ||
767 | * off before changing and on after | ||
768 | */ | ||
769 | if (host->imclk == rate || host->imclk == host->rate || !rate) | ||
770 | usdhi6_write(host, USDHI6_SD_CLK_CTRL, | ||
771 | val & ~USDHI6_SD_CLK_CTRL_SCLKEN); | ||
772 | |||
773 | if (!rate) { | ||
774 | host->rate = 0; | ||
775 | return; | ||
776 | } | ||
777 | |||
778 | usdhi6_write(host, USDHI6_SD_CLK_CTRL, val); | ||
779 | |||
780 | if (host->imclk == rate || host->imclk == host->rate || | ||
781 | !(val & USDHI6_SD_CLK_CTRL_SCLKEN)) | ||
782 | usdhi6_write(host, USDHI6_SD_CLK_CTRL, | ||
783 | val | USDHI6_SD_CLK_CTRL_SCLKEN); | ||
784 | } | ||
785 | |||
786 | static void usdhi6_set_power(struct usdhi6_host *host, struct mmc_ios *ios) | ||
787 | { | ||
788 | struct mmc_host *mmc = host->mmc; | ||
789 | |||
790 | if (!IS_ERR(mmc->supply.vmmc)) | ||
791 | /* Errors ignored... */ | ||
792 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | ||
793 | ios->power_mode ? ios->vdd : 0); | ||
794 | } | ||
795 | |||
796 | static int usdhi6_reset(struct usdhi6_host *host) | ||
797 | { | ||
798 | int i; | ||
799 | |||
800 | usdhi6_write(host, USDHI6_SOFT_RST, USDHI6_SOFT_RST_RESERVED); | ||
801 | cpu_relax(); | ||
802 | usdhi6_write(host, USDHI6_SOFT_RST, USDHI6_SOFT_RST_RESERVED | USDHI6_SOFT_RST_RESET); | ||
803 | for (i = 1000; i; i--) | ||
804 | if (usdhi6_read(host, USDHI6_SOFT_RST) & USDHI6_SOFT_RST_RESET) | ||
805 | break; | ||
806 | |||
807 | return i ? 0 : -ETIMEDOUT; | ||
808 | } | ||
809 | |||
810 | static void usdhi6_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | ||
811 | { | ||
812 | struct usdhi6_host *host = mmc_priv(mmc); | ||
813 | u32 option, mode; | ||
814 | int ret; | ||
815 | |||
816 | dev_dbg(mmc_dev(mmc), "%uHz, OCR: %u, power %u, bus-width %u, timing %u\n", | ||
817 | ios->clock, ios->vdd, ios->power_mode, ios->bus_width, ios->timing); | ||
818 | |||
819 | switch (ios->power_mode) { | ||
820 | case MMC_POWER_OFF: | ||
821 | usdhi6_set_power(host, ios); | ||
822 | usdhi6_only_cd(host); | ||
823 | break; | ||
824 | case MMC_POWER_UP: | ||
825 | /* | ||
826 | * We only also touch USDHI6_SD_OPTION from .request(), which | ||
827 | * cannot race with MMC_POWER_UP | ||
828 | */ | ||
829 | ret = usdhi6_reset(host); | ||
830 | if (ret < 0) { | ||
831 | dev_err(mmc_dev(mmc), "Cannot reset the interface!\n"); | ||
832 | } else { | ||
833 | usdhi6_set_power(host, ios); | ||
834 | usdhi6_only_cd(host); | ||
835 | } | ||
836 | break; | ||
837 | case MMC_POWER_ON: | ||
838 | option = usdhi6_read(host, USDHI6_SD_OPTION); | ||
839 | /* | ||
840 | * The eMMC standard only allows 4 or 8 bits in the DDR mode, | ||
841 | * the same probably holds for SD cards. We check here anyway, | ||
842 | * since the datasheet explicitly requires 4 bits for DDR. | ||
843 | */ | ||
844 | if (ios->bus_width == MMC_BUS_WIDTH_1) { | ||
845 | if (ios->timing == MMC_TIMING_UHS_DDR50) | ||
846 | dev_err(mmc_dev(mmc), | ||
847 | "4 bits are required for DDR\n"); | ||
848 | option |= USDHI6_SD_OPTION_WIDTH_1; | ||
849 | mode = 0; | ||
850 | } else { | ||
851 | option &= ~USDHI6_SD_OPTION_WIDTH_1; | ||
852 | mode = ios->timing == MMC_TIMING_UHS_DDR50; | ||
853 | } | ||
854 | usdhi6_write(host, USDHI6_SD_OPTION, option); | ||
855 | usdhi6_write(host, USDHI6_SDIF_MODE, mode); | ||
856 | break; | ||
857 | } | ||
858 | |||
859 | if (host->rate != ios->clock) | ||
860 | usdhi6_clk_set(host, ios); | ||
861 | } | ||
862 | |||
863 | /* This is data timeout. Response timeout is fixed to 640 clock cycles */ | ||
864 | static void usdhi6_timeout_set(struct usdhi6_host *host) | ||
865 | { | ||
866 | struct mmc_request *mrq = host->mrq; | ||
867 | u32 val; | ||
868 | unsigned long ticks; | ||
869 | |||
870 | if (!mrq->data) | ||
871 | ticks = host->rate / 1000 * mrq->cmd->busy_timeout; | ||
872 | else | ||
873 | ticks = host->rate / 1000000 * (mrq->data->timeout_ns / 1000) + | ||
874 | mrq->data->timeout_clks; | ||
875 | |||
876 | if (!ticks || ticks > 1 << 27) | ||
877 | /* Max timeout */ | ||
878 | val = 14; | ||
879 | else if (ticks < 1 << 13) | ||
880 | /* Min timeout */ | ||
881 | val = 0; | ||
882 | else | ||
883 | val = order_base_2(ticks) - 13; | ||
884 | |||
885 | dev_dbg(mmc_dev(host->mmc), "Set %s timeout %lu ticks @ %lu Hz\n", | ||
886 | mrq->data ? "data" : "cmd", ticks, host->rate); | ||
887 | |||
888 | /* Timeout Counter mask: 0xf0 */ | ||
889 | usdhi6_write(host, USDHI6_SD_OPTION, (val << USDHI6_SD_OPTION_TIMEOUT_SHIFT) | | ||
890 | (usdhi6_read(host, USDHI6_SD_OPTION) & ~USDHI6_SD_OPTION_TIMEOUT_MASK)); | ||
891 | } | ||
892 | |||
893 | static void usdhi6_request_done(struct usdhi6_host *host) | ||
894 | { | ||
895 | struct mmc_request *mrq = host->mrq; | ||
896 | struct mmc_data *data = mrq->data; | ||
897 | |||
898 | if (WARN(host->pg.page || host->head_pg.page, | ||
899 | "Page %p or %p not unmapped: wait %u, CMD%d(%c) @ +0x%x %ux%u in SG%u!\n", | ||
900 | host->pg.page, host->head_pg.page, host->wait, mrq->cmd->opcode, | ||
901 | data ? (data->flags & MMC_DATA_READ ? 'R' : 'W') : '-', | ||
902 | data ? host->offset : 0, data ? data->blocks : 0, | ||
903 | data ? data->blksz : 0, data ? data->sg_len : 0)) | ||
904 | usdhi6_sg_unmap(host, true); | ||
905 | |||
906 | if (mrq->cmd->error || | ||
907 | (data && data->error) || | ||
908 | (mrq->stop && mrq->stop->error)) | ||
909 | dev_dbg(mmc_dev(host->mmc), "%s(CMD%d: %ux%u): err %d %d %d\n", | ||
910 | __func__, mrq->cmd->opcode, data ? data->blocks : 0, | ||
911 | data ? data->blksz : 0, | ||
912 | mrq->cmd->error, | ||
913 | data ? data->error : 1, | ||
914 | mrq->stop ? mrq->stop->error : 1); | ||
915 | |||
916 | /* Disable DMA */ | ||
917 | usdhi6_write(host, USDHI6_CC_EXT_MODE, 0); | ||
918 | host->wait = USDHI6_WAIT_FOR_REQUEST; | ||
919 | host->mrq = NULL; | ||
920 | |||
921 | mmc_request_done(host->mmc, mrq); | ||
922 | } | ||
923 | |||
924 | static int usdhi6_cmd_flags(struct usdhi6_host *host) | ||
925 | { | ||
926 | struct mmc_request *mrq = host->mrq; | ||
927 | struct mmc_command *cmd = mrq->cmd; | ||
928 | u16 opc = cmd->opcode; | ||
929 | |||
930 | if (host->app_cmd) { | ||
931 | host->app_cmd = false; | ||
932 | opc |= USDHI6_SD_CMD_APP; | ||
933 | } | ||
934 | |||
935 | if (mrq->data) { | ||
936 | opc |= USDHI6_SD_CMD_DATA; | ||
937 | |||
938 | if (mrq->data->flags & MMC_DATA_READ) | ||
939 | opc |= USDHI6_SD_CMD_READ; | ||
940 | |||
941 | if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK || | ||
942 | cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || | ||
943 | (cmd->opcode == SD_IO_RW_EXTENDED && | ||
944 | mrq->data->blocks > 1)) { | ||
945 | opc |= USDHI6_SD_CMD_MULTI; | ||
946 | if (!mrq->stop) | ||
947 | opc |= USDHI6_SD_CMD_CMD12_AUTO_OFF; | ||
948 | } | ||
949 | |||
950 | switch (mmc_resp_type(cmd)) { | ||
951 | case MMC_RSP_NONE: | ||
952 | opc |= USDHI6_SD_CMD_MODE_RSP_NONE; | ||
953 | break; | ||
954 | case MMC_RSP_R1: | ||
955 | opc |= USDHI6_SD_CMD_MODE_RSP_R1; | ||
956 | break; | ||
957 | case MMC_RSP_R1B: | ||
958 | opc |= USDHI6_SD_CMD_MODE_RSP_R1B; | ||
959 | break; | ||
960 | case MMC_RSP_R2: | ||
961 | opc |= USDHI6_SD_CMD_MODE_RSP_R2; | ||
962 | break; | ||
963 | case MMC_RSP_R3: | ||
964 | opc |= USDHI6_SD_CMD_MODE_RSP_R3; | ||
965 | break; | ||
966 | default: | ||
967 | dev_warn(mmc_dev(host->mmc), | ||
968 | "Unknown response type %d\n", | ||
969 | mmc_resp_type(cmd)); | ||
970 | return -EINVAL; | ||
971 | } | ||
972 | } | ||
973 | |||
974 | return opc; | ||
975 | } | ||
976 | |||
977 | static int usdhi6_rq_start(struct usdhi6_host *host) | ||
978 | { | ||
979 | struct mmc_request *mrq = host->mrq; | ||
980 | struct mmc_command *cmd = mrq->cmd; | ||
981 | struct mmc_data *data = mrq->data; | ||
982 | int opc = usdhi6_cmd_flags(host); | ||
983 | int i; | ||
984 | |||
985 | if (opc < 0) | ||
986 | return opc; | ||
987 | |||
988 | for (i = 1000; i; i--) { | ||
989 | if (!(usdhi6_read(host, USDHI6_SD_INFO2) & USDHI6_SD_INFO2_CBSY)) | ||
990 | break; | ||
991 | usleep_range(10, 100); | ||
992 | } | ||
993 | |||
994 | if (!i) { | ||
995 | dev_dbg(mmc_dev(host->mmc), "Command active, request aborted\n"); | ||
996 | return -EAGAIN; | ||
997 | } | ||
998 | |||
999 | if (data) { | ||
1000 | bool use_dma; | ||
1001 | int ret = 0; | ||
1002 | |||
1003 | host->page_idx = 0; | ||
1004 | |||
1005 | if (cmd->opcode == SD_IO_RW_EXTENDED && data->blocks > 1) { | ||
1006 | switch (data->blksz) { | ||
1007 | case 512: | ||
1008 | break; | ||
1009 | case 32: | ||
1010 | case 64: | ||
1011 | case 128: | ||
1012 | case 256: | ||
1013 | if (mrq->stop) | ||
1014 | ret = -EINVAL; | ||
1015 | break; | ||
1016 | default: | ||
1017 | ret = -EINVAL; | ||
1018 | } | ||
1019 | } else if ((cmd->opcode == MMC_READ_MULTIPLE_BLOCK || | ||
1020 | cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) && | ||
1021 | data->blksz != 512) { | ||
1022 | ret = -EINVAL; | ||
1023 | } | ||
1024 | |||
1025 | if (ret < 0) { | ||
1026 | dev_warn(mmc_dev(host->mmc), "%s(): %u blocks of %u bytes\n", | ||
1027 | __func__, data->blocks, data->blksz); | ||
1028 | return -EINVAL; | ||
1029 | } | ||
1030 | |||
1031 | if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK || | ||
1032 | cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || | ||
1033 | (cmd->opcode == SD_IO_RW_EXTENDED && | ||
1034 | data->blocks > 1)) | ||
1035 | usdhi6_sg_prep(host); | ||
1036 | |||
1037 | usdhi6_write(host, USDHI6_SD_SIZE, data->blksz); | ||
1038 | |||
1039 | if ((data->blksz >= USDHI6_MIN_DMA || | ||
1040 | data->blocks > 1) && | ||
1041 | (data->blksz % 4 || | ||
1042 | data->sg->offset % 4)) | ||
1043 | dev_dbg(mmc_dev(host->mmc), | ||
1044 | "Bad SG of %u: %ux%u @ %u\n", data->sg_len, | ||
1045 | data->blksz, data->blocks, data->sg->offset); | ||
1046 | |||
1047 | /* Enable DMA for USDHI6_MIN_DMA bytes or more */ | ||
1048 | use_dma = data->blksz >= USDHI6_MIN_DMA && | ||
1049 | !(data->blksz % 4) && | ||
1050 | usdhi6_dma_start(host) >= DMA_MIN_COOKIE; | ||
1051 | |||
1052 | if (use_dma) | ||
1053 | usdhi6_write(host, USDHI6_CC_EXT_MODE, USDHI6_CC_EXT_MODE_SDRW); | ||
1054 | |||
1055 | dev_dbg(mmc_dev(host->mmc), | ||
1056 | "%s(): request opcode %u, %u blocks of %u bytes in %u segments, %s %s @+0x%x%s\n", | ||
1057 | __func__, cmd->opcode, data->blocks, data->blksz, | ||
1058 | data->sg_len, use_dma ? "DMA" : "PIO", | ||
1059 | data->flags & MMC_DATA_READ ? "read" : "write", | ||
1060 | data->sg->offset, mrq->stop ? " + stop" : ""); | ||
1061 | } else { | ||
1062 | dev_dbg(mmc_dev(host->mmc), "%s(): request opcode %u\n", | ||
1063 | __func__, cmd->opcode); | ||
1064 | } | ||
1065 | |||
1066 | /* We have to get a command completion interrupt with DMA too */ | ||
1067 | usdhi6_wait_for_resp(host); | ||
1068 | |||
1069 | host->wait = USDHI6_WAIT_FOR_CMD; | ||
1070 | schedule_delayed_work(&host->timeout_work, host->timeout); | ||
1071 | |||
1072 | /* SEC bit is required to enable block counting by the core */ | ||
1073 | usdhi6_write(host, USDHI6_SD_STOP, | ||
1074 | data && data->blocks > 1 ? USDHI6_SD_STOP_SEC : 0); | ||
1075 | usdhi6_write(host, USDHI6_SD_ARG, cmd->arg); | ||
1076 | |||
1077 | /* Kick command execution */ | ||
1078 | usdhi6_write(host, USDHI6_SD_CMD, opc); | ||
1079 | |||
1080 | return 0; | ||
1081 | } | ||
1082 | |||
1083 | static void usdhi6_request(struct mmc_host *mmc, struct mmc_request *mrq) | ||
1084 | { | ||
1085 | struct usdhi6_host *host = mmc_priv(mmc); | ||
1086 | int ret; | ||
1087 | |||
1088 | cancel_delayed_work_sync(&host->timeout_work); | ||
1089 | |||
1090 | host->mrq = mrq; | ||
1091 | host->sg = NULL; | ||
1092 | |||
1093 | usdhi6_timeout_set(host); | ||
1094 | ret = usdhi6_rq_start(host); | ||
1095 | if (ret < 0) { | ||
1096 | mrq->cmd->error = ret; | ||
1097 | usdhi6_request_done(host); | ||
1098 | } | ||
1099 | } | ||
1100 | |||
1101 | static int usdhi6_get_cd(struct mmc_host *mmc) | ||
1102 | { | ||
1103 | struct usdhi6_host *host = mmc_priv(mmc); | ||
1104 | /* Read is atomic, no need to lock */ | ||
1105 | u32 status = usdhi6_read(host, USDHI6_SD_INFO1) & USDHI6_SD_INFO1_CD; | ||
1106 | |||
1107 | /* | ||
1108 | * level status.CD CD_ACTIVE_HIGH card present | ||
1109 | * 1 0 0 0 | ||
1110 | * 1 0 1 1 | ||
1111 | * 0 1 0 1 | ||
1112 | * 0 1 1 0 | ||
1113 | */ | ||
1114 | return !status ^ !(mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH); | ||
1115 | } | ||
1116 | |||
1117 | static int usdhi6_get_ro(struct mmc_host *mmc) | ||
1118 | { | ||
1119 | struct usdhi6_host *host = mmc_priv(mmc); | ||
1120 | /* No locking as above */ | ||
1121 | u32 status = usdhi6_read(host, USDHI6_SD_INFO1) & USDHI6_SD_INFO1_WP; | ||
1122 | |||
1123 | /* | ||
1124 | * level status.WP RO_ACTIVE_HIGH card read-only | ||
1125 | * 1 0 0 0 | ||
1126 | * 1 0 1 1 | ||
1127 | * 0 1 0 1 | ||
1128 | * 0 1 1 0 | ||
1129 | */ | ||
1130 | return !status ^ !(mmc->caps2 & MMC_CAP2_RO_ACTIVE_HIGH); | ||
1131 | } | ||
1132 | |||
1133 | static void usdhi6_enable_sdio_irq(struct mmc_host *mmc, int enable) | ||
1134 | { | ||
1135 | struct usdhi6_host *host = mmc_priv(mmc); | ||
1136 | |||
1137 | dev_dbg(mmc_dev(mmc), "%s(): %sable\n", __func__, enable ? "en" : "dis"); | ||
1138 | |||
1139 | if (enable) { | ||
1140 | host->sdio_mask = USDHI6_SDIO_INFO1_IRQ & ~USDHI6_SDIO_INFO1_IOIRQ; | ||
1141 | usdhi6_write(host, USDHI6_SDIO_INFO1_MASK, host->sdio_mask); | ||
1142 | usdhi6_write(host, USDHI6_SDIO_MODE, 1); | ||
1143 | } else { | ||
1144 | usdhi6_write(host, USDHI6_SDIO_MODE, 0); | ||
1145 | usdhi6_write(host, USDHI6_SDIO_INFO1_MASK, USDHI6_SDIO_INFO1_IRQ); | ||
1146 | host->sdio_mask = USDHI6_SDIO_INFO1_IRQ; | ||
1147 | } | ||
1148 | } | ||
1149 | |||
1150 | static struct mmc_host_ops usdhi6_ops = { | ||
1151 | .request = usdhi6_request, | ||
1152 | .set_ios = usdhi6_set_ios, | ||
1153 | .get_cd = usdhi6_get_cd, | ||
1154 | .get_ro = usdhi6_get_ro, | ||
1155 | .enable_sdio_irq = usdhi6_enable_sdio_irq, | ||
1156 | }; | ||
1157 | |||
1158 | /* State machine handlers */ | ||
1159 | |||
1160 | static void usdhi6_resp_cmd12(struct usdhi6_host *host) | ||
1161 | { | ||
1162 | struct mmc_command *cmd = host->mrq->stop; | ||
1163 | cmd->resp[0] = usdhi6_read(host, USDHI6_SD_RSP10); | ||
1164 | } | ||
1165 | |||
1166 | static void usdhi6_resp_read(struct usdhi6_host *host) | ||
1167 | { | ||
1168 | struct mmc_command *cmd = host->mrq->cmd; | ||
1169 | u32 *rsp = cmd->resp, tmp = 0; | ||
1170 | int i; | ||
1171 | |||
1172 | /* | ||
1173 | * RSP10 39-8 | ||
1174 | * RSP32 71-40 | ||
1175 | * RSP54 103-72 | ||
1176 | * RSP76 127-104 | ||
1177 | * R2-type response: | ||
1178 | * resp[0] = r[127..96] | ||
1179 | * resp[1] = r[95..64] | ||
1180 | * resp[2] = r[63..32] | ||
1181 | * resp[3] = r[31..0] | ||
1182 | * Other responses: | ||
1183 | * resp[0] = r[39..8] | ||
1184 | */ | ||
1185 | |||
1186 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | ||
1187 | return; | ||
1188 | |||
1189 | if (!(host->irq_status & USDHI6_SD_INFO1_RSP_END)) { | ||
1190 | dev_err(mmc_dev(host->mmc), | ||
1191 | "CMD%d: response expected but is missing!\n", cmd->opcode); | ||
1192 | return; | ||
1193 | } | ||
1194 | |||
1195 | if (mmc_resp_type(cmd) & MMC_RSP_136) | ||
1196 | for (i = 0; i < 4; i++) { | ||
1197 | if (i) | ||
1198 | rsp[3 - i] = tmp >> 24; | ||
1199 | tmp = usdhi6_read(host, USDHI6_SD_RSP10 + i * 8); | ||
1200 | rsp[3 - i] |= tmp << 8; | ||
1201 | } | ||
1202 | else if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK || | ||
1203 | cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) | ||
1204 | /* Read RSP54 to avoid conflict with auto CMD12 */ | ||
1205 | rsp[0] = usdhi6_read(host, USDHI6_SD_RSP54); | ||
1206 | else | ||
1207 | rsp[0] = usdhi6_read(host, USDHI6_SD_RSP10); | ||
1208 | |||
1209 | dev_dbg(mmc_dev(host->mmc), "Response 0x%x\n", rsp[0]); | ||
1210 | } | ||
1211 | |||
1212 | static int usdhi6_blk_read(struct usdhi6_host *host) | ||
1213 | { | ||
1214 | struct mmc_data *data = host->mrq->data; | ||
1215 | u32 *p; | ||
1216 | int i, rest; | ||
1217 | |||
1218 | if (host->io_error) { | ||
1219 | data->error = usdhi6_error_code(host); | ||
1220 | goto error; | ||
1221 | } | ||
1222 | |||
1223 | if (host->pg.page) { | ||
1224 | p = host->blk_page + host->offset; | ||
1225 | } else { | ||
1226 | p = usdhi6_sg_map(host); | ||
1227 | if (!p) { | ||
1228 | data->error = -ENOMEM; | ||
1229 | goto error; | ||
1230 | } | ||
1231 | } | ||
1232 | |||
1233 | for (i = 0; i < data->blksz / 4; i++, p++) | ||
1234 | *p = usdhi6_read(host, USDHI6_SD_BUF0); | ||
1235 | |||
1236 | rest = data->blksz % 4; | ||
1237 | for (i = 0; i < (rest + 1) / 2; i++) { | ||
1238 | u16 d = usdhi6_read16(host, USDHI6_SD_BUF0); | ||
1239 | ((u8 *)p)[2 * i] = ((u8 *)&d)[0]; | ||
1240 | if (rest > 1 && !i) | ||
1241 | ((u8 *)p)[2 * i + 1] = ((u8 *)&d)[1]; | ||
1242 | } | ||
1243 | |||
1244 | return 0; | ||
1245 | |||
1246 | error: | ||
1247 | dev_dbg(mmc_dev(host->mmc), "%s(): %d\n", __func__, data->error); | ||
1248 | host->wait = USDHI6_WAIT_FOR_REQUEST; | ||
1249 | return data->error; | ||
1250 | } | ||
1251 | |||
1252 | static int usdhi6_blk_write(struct usdhi6_host *host) | ||
1253 | { | ||
1254 | struct mmc_data *data = host->mrq->data; | ||
1255 | u32 *p; | ||
1256 | int i, rest; | ||
1257 | |||
1258 | if (host->io_error) { | ||
1259 | data->error = usdhi6_error_code(host); | ||
1260 | goto error; | ||
1261 | } | ||
1262 | |||
1263 | if (host->pg.page) { | ||
1264 | p = host->blk_page + host->offset; | ||
1265 | } else { | ||
1266 | p = usdhi6_sg_map(host); | ||
1267 | if (!p) { | ||
1268 | data->error = -ENOMEM; | ||
1269 | goto error; | ||
1270 | } | ||
1271 | } | ||
1272 | |||
1273 | for (i = 0; i < data->blksz / 4; i++, p++) | ||
1274 | usdhi6_write(host, USDHI6_SD_BUF0, *p); | ||
1275 | |||
1276 | rest = data->blksz % 4; | ||
1277 | for (i = 0; i < (rest + 1) / 2; i++) { | ||
1278 | u16 d; | ||
1279 | ((u8 *)&d)[0] = ((u8 *)p)[2 * i]; | ||
1280 | if (rest > 1 && !i) | ||
1281 | ((u8 *)&d)[1] = ((u8 *)p)[2 * i + 1]; | ||
1282 | else | ||
1283 | ((u8 *)&d)[1] = 0; | ||
1284 | usdhi6_write16(host, USDHI6_SD_BUF0, d); | ||
1285 | } | ||
1286 | |||
1287 | return 0; | ||
1288 | |||
1289 | error: | ||
1290 | dev_dbg(mmc_dev(host->mmc), "%s(): %d\n", __func__, data->error); | ||
1291 | host->wait = USDHI6_WAIT_FOR_REQUEST; | ||
1292 | return data->error; | ||
1293 | } | ||
1294 | |||
1295 | static int usdhi6_stop_cmd(struct usdhi6_host *host) | ||
1296 | { | ||
1297 | struct mmc_request *mrq = host->mrq; | ||
1298 | |||
1299 | switch (mrq->cmd->opcode) { | ||
1300 | case MMC_READ_MULTIPLE_BLOCK: | ||
1301 | case MMC_WRITE_MULTIPLE_BLOCK: | ||
1302 | if (mrq->stop->opcode == MMC_STOP_TRANSMISSION) { | ||
1303 | host->wait = USDHI6_WAIT_FOR_STOP; | ||
1304 | return 0; | ||
1305 | } | ||
1306 | /* Unsupported STOP command */ | ||
1307 | default: | ||
1308 | dev_err(mmc_dev(host->mmc), | ||
1309 | "unsupported stop CMD%d for CMD%d\n", | ||
1310 | mrq->stop->opcode, mrq->cmd->opcode); | ||
1311 | mrq->stop->error = -EOPNOTSUPP; | ||
1312 | } | ||
1313 | |||
1314 | return -EOPNOTSUPP; | ||
1315 | } | ||
1316 | |||
1317 | static bool usdhi6_end_cmd(struct usdhi6_host *host) | ||
1318 | { | ||
1319 | struct mmc_request *mrq = host->mrq; | ||
1320 | struct mmc_command *cmd = mrq->cmd; | ||
1321 | |||
1322 | if (host->io_error) { | ||
1323 | cmd->error = usdhi6_error_code(host); | ||
1324 | return false; | ||
1325 | } | ||
1326 | |||
1327 | usdhi6_resp_read(host); | ||
1328 | |||
1329 | if (!mrq->data) | ||
1330 | return false; | ||
1331 | |||
1332 | if (host->dma_active) { | ||
1333 | usdhi6_dma_kick(host); | ||
1334 | if (!mrq->stop) | ||
1335 | host->wait = USDHI6_WAIT_FOR_DMA; | ||
1336 | else if (usdhi6_stop_cmd(host) < 0) | ||
1337 | return false; | ||
1338 | } else if (mrq->data->flags & MMC_DATA_READ) { | ||
1339 | if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK || | ||
1340 | (cmd->opcode == SD_IO_RW_EXTENDED && | ||
1341 | mrq->data->blocks > 1)) | ||
1342 | host->wait = USDHI6_WAIT_FOR_MREAD; | ||
1343 | else | ||
1344 | host->wait = USDHI6_WAIT_FOR_READ; | ||
1345 | } else { | ||
1346 | if (cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || | ||
1347 | (cmd->opcode == SD_IO_RW_EXTENDED && | ||
1348 | mrq->data->blocks > 1)) | ||
1349 | host->wait = USDHI6_WAIT_FOR_MWRITE; | ||
1350 | else | ||
1351 | host->wait = USDHI6_WAIT_FOR_WRITE; | ||
1352 | } | ||
1353 | |||
1354 | return true; | ||
1355 | } | ||
1356 | |||
1357 | static bool usdhi6_read_block(struct usdhi6_host *host) | ||
1358 | { | ||
1359 | /* ACCESS_END IRQ is already unmasked */ | ||
1360 | int ret = usdhi6_blk_read(host); | ||
1361 | |||
1362 | /* | ||
1363 | * Have to force unmapping both pages: the single block could have been | ||
1364 | * cross-page, in which case for single-block IO host->page_idx == 0. | ||
1365 | * So, if we don't force, the second page won't be unmapped. | ||
1366 | */ | ||
1367 | usdhi6_sg_unmap(host, true); | ||
1368 | |||
1369 | if (ret < 0) | ||
1370 | return false; | ||
1371 | |||
1372 | host->wait = USDHI6_WAIT_FOR_DATA_END; | ||
1373 | return true; | ||
1374 | } | ||
1375 | |||
1376 | static bool usdhi6_mread_block(struct usdhi6_host *host) | ||
1377 | { | ||
1378 | int ret = usdhi6_blk_read(host); | ||
1379 | |||
1380 | if (ret < 0) | ||
1381 | return false; | ||
1382 | |||
1383 | usdhi6_sg_advance(host); | ||
1384 | |||
1385 | return !host->mrq->data->error && | ||
1386 | (host->wait != USDHI6_WAIT_FOR_DATA_END || !host->mrq->stop); | ||
1387 | } | ||
1388 | |||
1389 | static bool usdhi6_write_block(struct usdhi6_host *host) | ||
1390 | { | ||
1391 | int ret = usdhi6_blk_write(host); | ||
1392 | |||
1393 | /* See comment in usdhi6_read_block() */ | ||
1394 | usdhi6_sg_unmap(host, true); | ||
1395 | |||
1396 | if (ret < 0) | ||
1397 | return false; | ||
1398 | |||
1399 | host->wait = USDHI6_WAIT_FOR_DATA_END; | ||
1400 | return true; | ||
1401 | } | ||
1402 | |||
1403 | static bool usdhi6_mwrite_block(struct usdhi6_host *host) | ||
1404 | { | ||
1405 | int ret = usdhi6_blk_write(host); | ||
1406 | |||
1407 | if (ret < 0) | ||
1408 | return false; | ||
1409 | |||
1410 | usdhi6_sg_advance(host); | ||
1411 | |||
1412 | return !host->mrq->data->error && | ||
1413 | (host->wait != USDHI6_WAIT_FOR_DATA_END || !host->mrq->stop); | ||
1414 | } | ||
1415 | |||
1416 | /* Interrupt & timeout handlers */ | ||
1417 | |||
1418 | static irqreturn_t usdhi6_sd_bh(int irq, void *dev_id) | ||
1419 | { | ||
1420 | struct usdhi6_host *host = dev_id; | ||
1421 | struct mmc_request *mrq; | ||
1422 | struct mmc_command *cmd; | ||
1423 | struct mmc_data *data; | ||
1424 | bool io_wait = false; | ||
1425 | |||
1426 | cancel_delayed_work_sync(&host->timeout_work); | ||
1427 | |||
1428 | mrq = host->mrq; | ||
1429 | if (!mrq) | ||
1430 | return IRQ_HANDLED; | ||
1431 | |||
1432 | cmd = mrq->cmd; | ||
1433 | data = mrq->data; | ||
1434 | |||
1435 | switch (host->wait) { | ||
1436 | case USDHI6_WAIT_FOR_REQUEST: | ||
1437 | /* We're too late, the timeout has already kicked in */ | ||
1438 | return IRQ_HANDLED; | ||
1439 | case USDHI6_WAIT_FOR_CMD: | ||
1440 | /* Wait for data? */ | ||
1441 | io_wait = usdhi6_end_cmd(host); | ||
1442 | break; | ||
1443 | case USDHI6_WAIT_FOR_MREAD: | ||
1444 | /* Wait for more data? */ | ||
1445 | io_wait = usdhi6_mread_block(host); | ||
1446 | break; | ||
1447 | case USDHI6_WAIT_FOR_READ: | ||
1448 | /* Wait for data end? */ | ||
1449 | io_wait = usdhi6_read_block(host); | ||
1450 | break; | ||
1451 | case USDHI6_WAIT_FOR_MWRITE: | ||
1452 | /* Wait data to write? */ | ||
1453 | io_wait = usdhi6_mwrite_block(host); | ||
1454 | break; | ||
1455 | case USDHI6_WAIT_FOR_WRITE: | ||
1456 | /* Wait for data end? */ | ||
1457 | io_wait = usdhi6_write_block(host); | ||
1458 | break; | ||
1459 | case USDHI6_WAIT_FOR_DMA: | ||
1460 | usdhi6_dma_check_error(host); | ||
1461 | break; | ||
1462 | case USDHI6_WAIT_FOR_STOP: | ||
1463 | usdhi6_write(host, USDHI6_SD_STOP, 0); | ||
1464 | if (host->io_error) { | ||
1465 | int ret = usdhi6_error_code(host); | ||
1466 | if (mrq->stop) | ||
1467 | mrq->stop->error = ret; | ||
1468 | else | ||
1469 | mrq->data->error = ret; | ||
1470 | dev_warn(mmc_dev(host->mmc), "%s(): %d\n", __func__, ret); | ||
1471 | break; | ||
1472 | } | ||
1473 | usdhi6_resp_cmd12(host); | ||
1474 | mrq->stop->error = 0; | ||
1475 | break; | ||
1476 | case USDHI6_WAIT_FOR_DATA_END: | ||
1477 | if (host->io_error) { | ||
1478 | mrq->data->error = usdhi6_error_code(host); | ||
1479 | dev_warn(mmc_dev(host->mmc), "%s(): %d\n", __func__, | ||
1480 | mrq->data->error); | ||
1481 | } | ||
1482 | break; | ||
1483 | default: | ||
1484 | cmd->error = -EFAULT; | ||
1485 | dev_err(mmc_dev(host->mmc), "Invalid state %u\n", host->wait); | ||
1486 | usdhi6_request_done(host); | ||
1487 | return IRQ_HANDLED; | ||
1488 | } | ||
1489 | |||
1490 | if (io_wait) { | ||
1491 | schedule_delayed_work(&host->timeout_work, host->timeout); | ||
1492 | /* Wait for more data or ACCESS_END */ | ||
1493 | if (!host->dma_active) | ||
1494 | usdhi6_wait_for_brwe(host, mrq->data->flags & MMC_DATA_READ); | ||
1495 | return IRQ_HANDLED; | ||
1496 | } | ||
1497 | |||
1498 | if (!cmd->error) { | ||
1499 | if (data) { | ||
1500 | if (!data->error) { | ||
1501 | if (host->wait != USDHI6_WAIT_FOR_STOP && | ||
1502 | host->mrq->stop && | ||
1503 | !host->mrq->stop->error && | ||
1504 | !usdhi6_stop_cmd(host)) { | ||
1505 | /* Sending STOP */ | ||
1506 | usdhi6_wait_for_resp(host); | ||
1507 | |||
1508 | schedule_delayed_work(&host->timeout_work, | ||
1509 | host->timeout); | ||
1510 | |||
1511 | return IRQ_HANDLED; | ||
1512 | } | ||
1513 | |||
1514 | data->bytes_xfered = data->blocks * data->blksz; | ||
1515 | } else { | ||
1516 | /* Data error: might need to unmap the last page */ | ||
1517 | dev_warn(mmc_dev(host->mmc), "%s(): data error %d\n", | ||
1518 | __func__, data->error); | ||
1519 | usdhi6_sg_unmap(host, true); | ||
1520 | } | ||
1521 | } else if (cmd->opcode == MMC_APP_CMD) { | ||
1522 | host->app_cmd = true; | ||
1523 | } | ||
1524 | } | ||
1525 | |||
1526 | usdhi6_request_done(host); | ||
1527 | |||
1528 | return IRQ_HANDLED; | ||
1529 | } | ||
1530 | |||
1531 | static irqreturn_t usdhi6_sd(int irq, void *dev_id) | ||
1532 | { | ||
1533 | struct usdhi6_host *host = dev_id; | ||
1534 | u16 status, status2, error; | ||
1535 | |||
1536 | status = usdhi6_read(host, USDHI6_SD_INFO1) & ~host->status_mask & | ||
1537 | ~USDHI6_SD_INFO1_CARD; | ||
1538 | status2 = usdhi6_read(host, USDHI6_SD_INFO2) & ~host->status2_mask; | ||
1539 | |||
1540 | usdhi6_only_cd(host); | ||
1541 | |||
1542 | dev_dbg(mmc_dev(host->mmc), | ||
1543 | "IRQ status = 0x%08x, status2 = 0x%08x\n", status, status2); | ||
1544 | |||
1545 | if (!status && !status2) | ||
1546 | return IRQ_NONE; | ||
1547 | |||
1548 | error = status2 & USDHI6_SD_INFO2_ERR; | ||
1549 | |||
1550 | /* Ack / clear interrupts */ | ||
1551 | if (USDHI6_SD_INFO1_IRQ & status) | ||
1552 | usdhi6_write(host, USDHI6_SD_INFO1, | ||
1553 | 0xffff & ~(USDHI6_SD_INFO1_IRQ & status)); | ||
1554 | |||
1555 | if (USDHI6_SD_INFO2_IRQ & status2) { | ||
1556 | if (error) | ||
1557 | /* In error cases BWE and BRE aren't cleared automatically */ | ||
1558 | status2 |= USDHI6_SD_INFO2_BWE | USDHI6_SD_INFO2_BRE; | ||
1559 | |||
1560 | usdhi6_write(host, USDHI6_SD_INFO2, | ||
1561 | 0xffff & ~(USDHI6_SD_INFO2_IRQ & status2)); | ||
1562 | } | ||
1563 | |||
1564 | host->io_error = error; | ||
1565 | host->irq_status = status; | ||
1566 | |||
1567 | if (error) { | ||
1568 | /* Don't pollute the log with unsupported command timeouts */ | ||
1569 | if (host->wait != USDHI6_WAIT_FOR_CMD || | ||
1570 | error != USDHI6_SD_INFO2_RSP_TOUT) | ||
1571 | dev_warn(mmc_dev(host->mmc), | ||
1572 | "%s(): INFO2 error bits 0x%08x\n", | ||
1573 | __func__, error); | ||
1574 | else | ||
1575 | dev_dbg(mmc_dev(host->mmc), | ||
1576 | "%s(): INFO2 error bits 0x%08x\n", | ||
1577 | __func__, error); | ||
1578 | } | ||
1579 | |||
1580 | return IRQ_WAKE_THREAD; | ||
1581 | } | ||
1582 | |||
1583 | static irqreturn_t usdhi6_sdio(int irq, void *dev_id) | ||
1584 | { | ||
1585 | struct usdhi6_host *host = dev_id; | ||
1586 | u32 status = usdhi6_read(host, USDHI6_SDIO_INFO1) & ~host->sdio_mask; | ||
1587 | |||
1588 | dev_dbg(mmc_dev(host->mmc), "%s(): status 0x%x\n", __func__, status); | ||
1589 | |||
1590 | if (!status) | ||
1591 | return IRQ_NONE; | ||
1592 | |||
1593 | usdhi6_write(host, USDHI6_SDIO_INFO1, ~status); | ||
1594 | |||
1595 | mmc_signal_sdio_irq(host->mmc); | ||
1596 | |||
1597 | return IRQ_HANDLED; | ||
1598 | } | ||
1599 | |||
1600 | static irqreturn_t usdhi6_cd(int irq, void *dev_id) | ||
1601 | { | ||
1602 | struct usdhi6_host *host = dev_id; | ||
1603 | struct mmc_host *mmc = host->mmc; | ||
1604 | u16 status; | ||
1605 | |||
1606 | /* We're only interested in hotplug events here */ | ||
1607 | status = usdhi6_read(host, USDHI6_SD_INFO1) & ~host->status_mask & | ||
1608 | USDHI6_SD_INFO1_CARD; | ||
1609 | |||
1610 | if (!status) | ||
1611 | return IRQ_NONE; | ||
1612 | |||
1613 | /* Ack */ | ||
1614 | usdhi6_write(host, USDHI6_SD_INFO1, !status); | ||
1615 | |||
1616 | if (!work_pending(&mmc->detect.work) && | ||
1617 | (((status & USDHI6_SD_INFO1_CARD_INSERT) && | ||
1618 | !mmc->card) || | ||
1619 | ((status & USDHI6_SD_INFO1_CARD_EJECT) && | ||
1620 | mmc->card))) | ||
1621 | mmc_detect_change(mmc, msecs_to_jiffies(100)); | ||
1622 | |||
1623 | return IRQ_HANDLED; | ||
1624 | } | ||
1625 | |||
1626 | /* | ||
1627 | * Actually this should not be needed, if the built-in timeout works reliably in | ||
1628 | * the both PIO cases and DMA never fails. But if DMA does fail, a timeout | ||
1629 | * handler might be the only way to catch the error. | ||
1630 | */ | ||
1631 | static void usdhi6_timeout_work(struct work_struct *work) | ||
1632 | { | ||
1633 | struct delayed_work *d = container_of(work, struct delayed_work, work); | ||
1634 | struct usdhi6_host *host = container_of(d, struct usdhi6_host, timeout_work); | ||
1635 | struct mmc_request *mrq = host->mrq; | ||
1636 | struct mmc_data *data = mrq ? mrq->data : NULL; | ||
1637 | |||
1638 | dev_warn(mmc_dev(host->mmc), | ||
1639 | "%s timeout wait %u CMD%d: IRQ 0x%08x:0x%08x, last IRQ 0x%08x\n", | ||
1640 | host->dma_active ? "DMA" : "PIO", | ||
1641 | host->wait, mrq ? mrq->cmd->opcode : -1, | ||
1642 | usdhi6_read(host, USDHI6_SD_INFO1), | ||
1643 | usdhi6_read(host, USDHI6_SD_INFO2), host->irq_status); | ||
1644 | |||
1645 | if (host->dma_active) { | ||
1646 | usdhi6_dma_kill(host); | ||
1647 | usdhi6_dma_stop_unmap(host); | ||
1648 | } | ||
1649 | |||
1650 | switch (host->wait) { | ||
1651 | default: | ||
1652 | dev_err(mmc_dev(host->mmc), "Invalid state %u\n", host->wait); | ||
1653 | /* mrq can be NULL in this actually impossible case */ | ||
1654 | case USDHI6_WAIT_FOR_CMD: | ||
1655 | usdhi6_error_code(host); | ||
1656 | if (mrq) | ||
1657 | mrq->cmd->error = -ETIMEDOUT; | ||
1658 | break; | ||
1659 | case USDHI6_WAIT_FOR_STOP: | ||
1660 | usdhi6_error_code(host); | ||
1661 | mrq->stop->error = -ETIMEDOUT; | ||
1662 | break; | ||
1663 | case USDHI6_WAIT_FOR_DMA: | ||
1664 | case USDHI6_WAIT_FOR_MREAD: | ||
1665 | case USDHI6_WAIT_FOR_MWRITE: | ||
1666 | case USDHI6_WAIT_FOR_READ: | ||
1667 | case USDHI6_WAIT_FOR_WRITE: | ||
1668 | dev_dbg(mmc_dev(host->mmc), | ||
1669 | "%c: page #%u @ +0x%x %ux%u in SG%u. Current SG %u bytes @ %u\n", | ||
1670 | data->flags & MMC_DATA_READ ? 'R' : 'W', host->page_idx, | ||
1671 | host->offset, data->blocks, data->blksz, data->sg_len, | ||
1672 | sg_dma_len(host->sg), host->sg->offset); | ||
1673 | usdhi6_sg_unmap(host, true); | ||
1674 | /* | ||
1675 | * If USDHI6_WAIT_FOR_DATA_END times out, we have already unmapped | ||
1676 | * the page | ||
1677 | */ | ||
1678 | case USDHI6_WAIT_FOR_DATA_END: | ||
1679 | usdhi6_error_code(host); | ||
1680 | data->error = -ETIMEDOUT; | ||
1681 | } | ||
1682 | |||
1683 | if (mrq) | ||
1684 | usdhi6_request_done(host); | ||
1685 | } | ||
1686 | |||
1687 | /* Probe / release */ | ||
1688 | |||
1689 | static const struct of_device_id usdhi6_of_match[] = { | ||
1690 | {.compatible = "renesas,usdhi6rol0"}, | ||
1691 | {} | ||
1692 | }; | ||
1693 | MODULE_DEVICE_TABLE(of, usdhi6_of_match); | ||
1694 | |||
1695 | static int usdhi6_probe(struct platform_device *pdev) | ||
1696 | { | ||
1697 | struct device *dev = &pdev->dev; | ||
1698 | struct mmc_host *mmc; | ||
1699 | struct usdhi6_host *host; | ||
1700 | struct resource *res; | ||
1701 | int irq_cd, irq_sd, irq_sdio; | ||
1702 | u32 version; | ||
1703 | int ret; | ||
1704 | |||
1705 | if (!dev->of_node) | ||
1706 | return -ENODEV; | ||
1707 | |||
1708 | irq_cd = platform_get_irq_byname(pdev, "card detect"); | ||
1709 | irq_sd = platform_get_irq_byname(pdev, "data"); | ||
1710 | irq_sdio = platform_get_irq_byname(pdev, "SDIO"); | ||
1711 | if (irq_sd < 0 || irq_sdio < 0) | ||
1712 | return -ENODEV; | ||
1713 | |||
1714 | mmc = mmc_alloc_host(sizeof(struct usdhi6_host), dev); | ||
1715 | if (!mmc) | ||
1716 | return -ENOMEM; | ||
1717 | |||
1718 | ret = mmc_of_parse(mmc); | ||
1719 | if (ret < 0) | ||
1720 | goto e_free_mmc; | ||
1721 | |||
1722 | mmc_regulator_get_supply(mmc); | ||
1723 | |||
1724 | host = mmc_priv(mmc); | ||
1725 | host->mmc = mmc; | ||
1726 | host->wait = USDHI6_WAIT_FOR_REQUEST; | ||
1727 | host->timeout = msecs_to_jiffies(4000); | ||
1728 | |||
1729 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1730 | host->base = devm_ioremap_resource(dev, res); | ||
1731 | if (IS_ERR(host->base)) { | ||
1732 | ret = PTR_ERR(host->base); | ||
1733 | goto e_free_mmc; | ||
1734 | } | ||
1735 | |||
1736 | host->clk = devm_clk_get(dev, NULL); | ||
1737 | if (IS_ERR(host->clk)) | ||
1738 | goto e_free_mmc; | ||
1739 | |||
1740 | host->imclk = clk_get_rate(host->clk); | ||
1741 | |||
1742 | ret = clk_prepare_enable(host->clk); | ||
1743 | if (ret < 0) | ||
1744 | goto e_free_mmc; | ||
1745 | |||
1746 | version = usdhi6_read(host, USDHI6_VERSION); | ||
1747 | if ((version & 0xfff) != 0xa0d) { | ||
1748 | dev_err(dev, "Version not recognized %x\n", version); | ||
1749 | goto e_clk_off; | ||
1750 | } | ||
1751 | |||
1752 | dev_info(dev, "A USDHI6ROL0 SD host detected with %d ports\n", | ||
1753 | usdhi6_read(host, USDHI6_SD_PORT_SEL) >> USDHI6_SD_PORT_SEL_PORTS_SHIFT); | ||
1754 | |||
1755 | usdhi6_mask_all(host); | ||
1756 | |||
1757 | if (irq_cd >= 0) { | ||
1758 | ret = devm_request_irq(dev, irq_cd, usdhi6_cd, 0, | ||
1759 | dev_name(dev), host); | ||
1760 | if (ret < 0) | ||
1761 | goto e_clk_off; | ||
1762 | } else { | ||
1763 | mmc->caps |= MMC_CAP_NEEDS_POLL; | ||
1764 | } | ||
1765 | |||
1766 | ret = devm_request_threaded_irq(dev, irq_sd, usdhi6_sd, usdhi6_sd_bh, 0, | ||
1767 | dev_name(dev), host); | ||
1768 | if (ret < 0) | ||
1769 | goto e_clk_off; | ||
1770 | |||
1771 | ret = devm_request_irq(dev, irq_sdio, usdhi6_sdio, 0, | ||
1772 | dev_name(dev), host); | ||
1773 | if (ret < 0) | ||
1774 | goto e_clk_off; | ||
1775 | |||
1776 | INIT_DELAYED_WORK(&host->timeout_work, usdhi6_timeout_work); | ||
1777 | |||
1778 | usdhi6_dma_request(host, res->start); | ||
1779 | |||
1780 | mmc->ops = &usdhi6_ops; | ||
1781 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | | ||
1782 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ; | ||
1783 | /* Set .max_segs to some random number. Feel free to adjust. */ | ||
1784 | mmc->max_segs = 32; | ||
1785 | mmc->max_blk_size = 512; | ||
1786 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; | ||
1787 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; | ||
1788 | /* | ||
1789 | * Setting .max_seg_size to 1 page would simplify our page-mapping code, | ||
1790 | * But OTOH, having large segments makes DMA more efficient. We could | ||
1791 | * check, whether we managed to get DMA and fall back to 1 page | ||
1792 | * segments, but if we do manage to obtain DMA and then it fails at | ||
1793 | * run-time and we fall back to PIO, we will continue getting large | ||
1794 | * segments. So, we wouldn't be able to get rid of the code anyway. | ||
1795 | */ | ||
1796 | mmc->max_seg_size = mmc->max_req_size; | ||
1797 | if (!mmc->f_max) | ||
1798 | mmc->f_max = host->imclk; | ||
1799 | mmc->f_min = host->imclk / 512; | ||
1800 | |||
1801 | platform_set_drvdata(pdev, host); | ||
1802 | |||
1803 | ret = mmc_add_host(mmc); | ||
1804 | if (ret < 0) | ||
1805 | goto e_clk_off; | ||
1806 | |||
1807 | return 0; | ||
1808 | |||
1809 | e_clk_off: | ||
1810 | clk_disable_unprepare(host->clk); | ||
1811 | e_free_mmc: | ||
1812 | mmc_free_host(mmc); | ||
1813 | |||
1814 | return ret; | ||
1815 | } | ||
1816 | |||
1817 | static int usdhi6_remove(struct platform_device *pdev) | ||
1818 | { | ||
1819 | struct usdhi6_host *host = platform_get_drvdata(pdev); | ||
1820 | |||
1821 | mmc_remove_host(host->mmc); | ||
1822 | |||
1823 | usdhi6_mask_all(host); | ||
1824 | cancel_delayed_work_sync(&host->timeout_work); | ||
1825 | usdhi6_dma_release(host); | ||
1826 | clk_disable_unprepare(host->clk); | ||
1827 | mmc_free_host(host->mmc); | ||
1828 | |||
1829 | return 0; | ||
1830 | } | ||
1831 | |||
1832 | static struct platform_driver usdhi6_driver = { | ||
1833 | .probe = usdhi6_probe, | ||
1834 | .remove = usdhi6_remove, | ||
1835 | .driver = { | ||
1836 | .name = "usdhi6rol0", | ||
1837 | .owner = THIS_MODULE, | ||
1838 | .of_match_table = usdhi6_of_match, | ||
1839 | }, | ||
1840 | }; | ||
1841 | |||
1842 | module_platform_driver(usdhi6_driver); | ||
1843 | |||
1844 | MODULE_DESCRIPTION("Renesas usdhi6rol0 SD/SDIO host driver"); | ||
1845 | MODULE_LICENSE("GPL v2"); | ||
1846 | MODULE_ALIAS("platform:usdhi6rol0"); | ||
1847 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); | ||
diff --git a/drivers/mmc/host/wmt-sdmmc.c b/drivers/mmc/host/wmt-sdmmc.c index 498d1f799085..282891a8e451 100644 --- a/drivers/mmc/host/wmt-sdmmc.c +++ b/drivers/mmc/host/wmt-sdmmc.c | |||
@@ -840,7 +840,7 @@ static int wmt_mci_probe(struct platform_device *pdev) | |||
840 | priv->dma_desc_buffer = dma_alloc_coherent(&pdev->dev, | 840 | priv->dma_desc_buffer = dma_alloc_coherent(&pdev->dev, |
841 | mmc->max_blk_count * 16, | 841 | mmc->max_blk_count * 16, |
842 | &priv->dma_desc_device_addr, | 842 | &priv->dma_desc_device_addr, |
843 | 208); | 843 | GFP_KERNEL); |
844 | if (!priv->dma_desc_buffer) { | 844 | if (!priv->dma_desc_buffer) { |
845 | dev_err(&pdev->dev, "DMA alloc fail\n"); | 845 | dev_err(&pdev->dev, "DMA alloc fail\n"); |
846 | ret = -EPERM; | 846 | ret = -EPERM; |
diff --git a/drivers/net/wireless/rsi/rsi_91x_sdio.c b/drivers/net/wireless/rsi/rsi_91x_sdio.c index 2e39d38d6a9e..46e7af446f01 100644 --- a/drivers/net/wireless/rsi/rsi_91x_sdio.c +++ b/drivers/net/wireless/rsi/rsi_91x_sdio.c | |||
@@ -285,7 +285,6 @@ static void rsi_reset_card(struct sdio_func *pfunction) | |||
285 | if (err) { | 285 | if (err) { |
286 | rsi_dbg(ERR_ZONE, "%s: CCCR speed reg read failed: %d\n", | 286 | rsi_dbg(ERR_ZONE, "%s: CCCR speed reg read failed: %d\n", |
287 | __func__, err); | 287 | __func__, err); |
288 | card->state &= ~MMC_STATE_HIGHSPEED; | ||
289 | } else { | 288 | } else { |
290 | err = rsi_cmd52writebyte(card, | 289 | err = rsi_cmd52writebyte(card, |
291 | SDIO_CCCR_SPEED, | 290 | SDIO_CCCR_SPEED, |
@@ -296,14 +295,13 @@ static void rsi_reset_card(struct sdio_func *pfunction) | |||
296 | __func__, err); | 295 | __func__, err); |
297 | return; | 296 | return; |
298 | } | 297 | } |
299 | mmc_card_set_highspeed(card); | ||
300 | host->ios.timing = MMC_TIMING_SD_HS; | 298 | host->ios.timing = MMC_TIMING_SD_HS; |
301 | host->ops->set_ios(host, &host->ios); | 299 | host->ops->set_ios(host, &host->ios); |
302 | } | 300 | } |
303 | } | 301 | } |
304 | 302 | ||
305 | /* Set clock */ | 303 | /* Set clock */ |
306 | if (mmc_card_highspeed(card)) | 304 | if (mmc_card_hs(card)) |
307 | clock = 50000000; | 305 | clock = 50000000; |
308 | else | 306 | else |
309 | clock = card->cis.max_dtr; | 307 | clock = card->cis.max_dtr; |
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index b73027298b3a..d424b9de3aff 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h | |||
@@ -63,12 +63,12 @@ struct mmc_ext_csd { | |||
63 | unsigned int power_off_longtime; /* Units: ms */ | 63 | unsigned int power_off_longtime; /* Units: ms */ |
64 | u8 power_off_notification; /* state */ | 64 | u8 power_off_notification; /* state */ |
65 | unsigned int hs_max_dtr; | 65 | unsigned int hs_max_dtr; |
66 | unsigned int hs200_max_dtr; | ||
66 | #define MMC_HIGH_26_MAX_DTR 26000000 | 67 | #define MMC_HIGH_26_MAX_DTR 26000000 |
67 | #define MMC_HIGH_52_MAX_DTR 52000000 | 68 | #define MMC_HIGH_52_MAX_DTR 52000000 |
68 | #define MMC_HIGH_DDR_MAX_DTR 52000000 | 69 | #define MMC_HIGH_DDR_MAX_DTR 52000000 |
69 | #define MMC_HS200_MAX_DTR 200000000 | 70 | #define MMC_HS200_MAX_DTR 200000000 |
70 | unsigned int sectors; | 71 | unsigned int sectors; |
71 | unsigned int card_type; | ||
72 | unsigned int hc_erase_size; /* In sectors */ | 72 | unsigned int hc_erase_size; /* In sectors */ |
73 | unsigned int hc_erase_timeout; /* In milliseconds */ | 73 | unsigned int hc_erase_timeout; /* In milliseconds */ |
74 | unsigned int sec_trim_mult; /* Secure trim multiplier */ | 74 | unsigned int sec_trim_mult; /* Secure trim multiplier */ |
@@ -110,6 +110,7 @@ struct mmc_ext_csd { | |||
110 | u8 raw_pwr_cl_200_360; /* 237 */ | 110 | u8 raw_pwr_cl_200_360; /* 237 */ |
111 | u8 raw_pwr_cl_ddr_52_195; /* 238 */ | 111 | u8 raw_pwr_cl_ddr_52_195; /* 238 */ |
112 | u8 raw_pwr_cl_ddr_52_360; /* 239 */ | 112 | u8 raw_pwr_cl_ddr_52_360; /* 239 */ |
113 | u8 raw_pwr_cl_ddr_200_360; /* 253 */ | ||
113 | u8 raw_bkops_status; /* 246 */ | 114 | u8 raw_bkops_status; /* 246 */ |
114 | u8 raw_sectors[4]; /* 212 - 4 bytes */ | 115 | u8 raw_sectors[4]; /* 212 - 4 bytes */ |
115 | 116 | ||
@@ -194,6 +195,7 @@ struct sdio_cis { | |||
194 | }; | 195 | }; |
195 | 196 | ||
196 | struct mmc_host; | 197 | struct mmc_host; |
198 | struct mmc_ios; | ||
197 | struct sdio_func; | 199 | struct sdio_func; |
198 | struct sdio_func_tuple; | 200 | struct sdio_func_tuple; |
199 | 201 | ||
@@ -250,15 +252,11 @@ struct mmc_card { | |||
250 | unsigned int state; /* (our) card state */ | 252 | unsigned int state; /* (our) card state */ |
251 | #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */ | 253 | #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */ |
252 | #define MMC_STATE_READONLY (1<<1) /* card is read-only */ | 254 | #define MMC_STATE_READONLY (1<<1) /* card is read-only */ |
253 | #define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */ | 255 | #define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */ |
254 | #define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */ | 256 | #define MMC_CARD_SDXC (1<<3) /* card is SDXC */ |
255 | #define MMC_STATE_HIGHSPEED_DDR (1<<4) /* card is in high speed mode */ | 257 | #define MMC_CARD_REMOVED (1<<4) /* card has been removed */ |
256 | #define MMC_STATE_ULTRAHIGHSPEED (1<<5) /* card is in ultra high speed mode */ | 258 | #define MMC_STATE_DOING_BKOPS (1<<5) /* card is doing BKOPS */ |
257 | #define MMC_CARD_SDXC (1<<6) /* card is SDXC */ | 259 | #define MMC_STATE_SUSPENDED (1<<6) /* card is suspended */ |
258 | #define MMC_CARD_REMOVED (1<<7) /* card has been removed */ | ||
259 | #define MMC_STATE_HIGHSPEED_200 (1<<8) /* card is in HS200 mode */ | ||
260 | #define MMC_STATE_DOING_BKOPS (1<<10) /* card is doing BKOPS */ | ||
261 | #define MMC_STATE_SUSPENDED (1<<11) /* card is suspended */ | ||
262 | unsigned int quirks; /* card quirks */ | 260 | unsigned int quirks; /* card quirks */ |
263 | #define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ | 261 | #define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ |
264 | #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ | 262 | #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ |
@@ -301,6 +299,7 @@ struct mmc_card { | |||
301 | struct sdio_func_tuple *tuples; /* unknown common tuples */ | 299 | struct sdio_func_tuple *tuples; /* unknown common tuples */ |
302 | 300 | ||
303 | unsigned int sd_bus_speed; /* Bus Speed Mode set for the card */ | 301 | unsigned int sd_bus_speed; /* Bus Speed Mode set for the card */ |
302 | unsigned int mmc_avail_type; /* supported device type by both host and card */ | ||
304 | 303 | ||
305 | struct dentry *debugfs_root; | 304 | struct dentry *debugfs_root; |
306 | struct mmc_part part[MMC_NUM_PHY_PARTITION]; /* physical partitions */ | 305 | struct mmc_part part[MMC_NUM_PHY_PARTITION]; /* physical partitions */ |
@@ -353,7 +352,7 @@ struct mmc_fixup { | |||
353 | #define CID_OEMID_ANY ((unsigned short) -1) | 352 | #define CID_OEMID_ANY ((unsigned short) -1) |
354 | #define CID_NAME_ANY (NULL) | 353 | #define CID_NAME_ANY (NULL) |
355 | 354 | ||
356 | #define END_FIXUP { 0 } | 355 | #define END_FIXUP { NULL } |
357 | 356 | ||
358 | #define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ | 357 | #define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ |
359 | _cis_vendor, _cis_device, \ | 358 | _cis_vendor, _cis_device, \ |
@@ -418,11 +417,7 @@ static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data) | |||
418 | 417 | ||
419 | #define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) | 418 | #define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) |
420 | #define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) | 419 | #define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) |
421 | #define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED) | ||
422 | #define mmc_card_hs200(c) ((c)->state & MMC_STATE_HIGHSPEED_200) | ||
423 | #define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) | 420 | #define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) |
424 | #define mmc_card_ddr_mode(c) ((c)->state & MMC_STATE_HIGHSPEED_DDR) | ||
425 | #define mmc_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED) | ||
426 | #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC) | 421 | #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC) |
427 | #define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED)) | 422 | #define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED)) |
428 | #define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS) | 423 | #define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS) |
@@ -430,11 +425,7 @@ static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data) | |||
430 | 425 | ||
431 | #define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) | 426 | #define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) |
432 | #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) | 427 | #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) |
433 | #define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED) | ||
434 | #define mmc_card_set_hs200(c) ((c)->state |= MMC_STATE_HIGHSPEED_200) | ||
435 | #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) | 428 | #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) |
436 | #define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR) | ||
437 | #define mmc_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED) | ||
438 | #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC) | 429 | #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC) |
439 | #define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED) | 430 | #define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED) |
440 | #define mmc_card_set_doing_bkops(c) ((c)->state |= MMC_STATE_DOING_BKOPS) | 431 | #define mmc_card_set_doing_bkops(c) ((c)->state |= MMC_STATE_DOING_BKOPS) |
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 6ce7d2cd3c7a..babaea93bca6 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h | |||
@@ -248,20 +248,6 @@ struct dw_mci_board { | |||
248 | /* delay in mS before detecting cards after interrupt */ | 248 | /* delay in mS before detecting cards after interrupt */ |
249 | u32 detect_delay_ms; | 249 | u32 detect_delay_ms; |
250 | 250 | ||
251 | int (*init)(u32 slot_id, irq_handler_t , void *); | ||
252 | int (*get_ro)(u32 slot_id); | ||
253 | int (*get_cd)(u32 slot_id); | ||
254 | int (*get_ocr)(u32 slot_id); | ||
255 | int (*get_bus_wd)(u32 slot_id); | ||
256 | /* | ||
257 | * Enable power to selected slot and set voltage to desired level. | ||
258 | * Voltage levels are specified using MMC_VDD_xxx defines defined | ||
259 | * in linux/mmc/host.h file. | ||
260 | */ | ||
261 | void (*setpower)(u32 slot_id, u32 volt); | ||
262 | void (*exit)(u32 slot_id); | ||
263 | void (*select_slot)(u32 slot_id); | ||
264 | |||
265 | struct dw_mci_dma_ops *dma_ops; | 251 | struct dw_mci_dma_ops *dma_ops; |
266 | struct dma_pdata *data; | 252 | struct dma_pdata *data; |
267 | struct block_settings *blk_settings; | 253 | struct block_settings *blk_settings; |
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index cb61ea4d6945..7960424d0bc0 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/fault-inject.h> | 17 | #include <linux/fault-inject.h> |
18 | 18 | ||
19 | #include <linux/mmc/core.h> | 19 | #include <linux/mmc/core.h> |
20 | #include <linux/mmc/card.h> | ||
20 | #include <linux/mmc/pm.h> | 21 | #include <linux/mmc/pm.h> |
21 | 22 | ||
22 | struct mmc_ios { | 23 | struct mmc_ios { |
@@ -58,13 +59,9 @@ struct mmc_ios { | |||
58 | #define MMC_TIMING_UHS_SDR50 5 | 59 | #define MMC_TIMING_UHS_SDR50 5 |
59 | #define MMC_TIMING_UHS_SDR104 6 | 60 | #define MMC_TIMING_UHS_SDR104 6 |
60 | #define MMC_TIMING_UHS_DDR50 7 | 61 | #define MMC_TIMING_UHS_DDR50 7 |
61 | #define MMC_TIMING_MMC_HS200 8 | 62 | #define MMC_TIMING_MMC_DDR52 8 |
62 | 63 | #define MMC_TIMING_MMC_HS200 9 | |
63 | #define MMC_SDR_MODE 0 | 64 | #define MMC_TIMING_MMC_HS400 10 |
64 | #define MMC_1_2V_DDR_MODE 1 | ||
65 | #define MMC_1_8V_DDR_MODE 2 | ||
66 | #define MMC_1_2V_SDR_MODE 3 | ||
67 | #define MMC_1_8V_SDR_MODE 4 | ||
68 | 65 | ||
69 | unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ | 66 | unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ |
70 | 67 | ||
@@ -136,6 +133,9 @@ struct mmc_host_ops { | |||
136 | 133 | ||
137 | /* The tuning command opcode value is different for SD and eMMC cards */ | 134 | /* The tuning command opcode value is different for SD and eMMC cards */ |
138 | int (*execute_tuning)(struct mmc_host *host, u32 opcode); | 135 | int (*execute_tuning)(struct mmc_host *host, u32 opcode); |
136 | |||
137 | /* Prepare HS400 target operating frequency depending host driver */ | ||
138 | int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); | ||
139 | int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv); | 139 | int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv); |
140 | void (*hw_reset)(struct mmc_host *host); | 140 | void (*hw_reset)(struct mmc_host *host); |
141 | void (*card_event)(struct mmc_host *host); | 141 | void (*card_event)(struct mmc_host *host); |
@@ -278,6 +278,11 @@ struct mmc_host { | |||
278 | #define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ | 278 | #define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ |
279 | MMC_CAP2_PACKED_WR) | 279 | MMC_CAP2_PACKED_WR) |
280 | #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ | 280 | #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ |
281 | #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ | ||
282 | #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ | ||
283 | #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ | ||
284 | MMC_CAP2_HS400_1_2V) | ||
285 | #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) | ||
281 | 286 | ||
282 | mmc_pm_flag_t pm_caps; /* supported pm features */ | 287 | mmc_pm_flag_t pm_caps; /* supported pm features */ |
283 | 288 | ||
@@ -318,6 +323,8 @@ struct mmc_host { | |||
318 | int rescan_disable; /* disable card detection */ | 323 | int rescan_disable; /* disable card detection */ |
319 | int rescan_entered; /* used with nonremovable devices */ | 324 | int rescan_entered; /* used with nonremovable devices */ |
320 | 325 | ||
326 | bool trigger_card_event; /* card_event necessary */ | ||
327 | |||
321 | struct mmc_card *card; /* device attached to this host */ | 328 | struct mmc_card *card; /* device attached to this host */ |
322 | 329 | ||
323 | wait_queue_head_t wq; | 330 | wait_queue_head_t wq; |
@@ -391,12 +398,13 @@ static inline void mmc_signal_sdio_irq(struct mmc_host *host) | |||
391 | wake_up_process(host->sdio_irq_thread); | 398 | wake_up_process(host->sdio_irq_thread); |
392 | } | 399 | } |
393 | 400 | ||
401 | void sdio_run_irqs(struct mmc_host *host); | ||
402 | |||
394 | #ifdef CONFIG_REGULATOR | 403 | #ifdef CONFIG_REGULATOR |
395 | int mmc_regulator_get_ocrmask(struct regulator *supply); | 404 | int mmc_regulator_get_ocrmask(struct regulator *supply); |
396 | int mmc_regulator_set_ocr(struct mmc_host *mmc, | 405 | int mmc_regulator_set_ocr(struct mmc_host *mmc, |
397 | struct regulator *supply, | 406 | struct regulator *supply, |
398 | unsigned short vdd_bit); | 407 | unsigned short vdd_bit); |
399 | int mmc_regulator_get_supply(struct mmc_host *mmc); | ||
400 | #else | 408 | #else |
401 | static inline int mmc_regulator_get_ocrmask(struct regulator *supply) | 409 | static inline int mmc_regulator_get_ocrmask(struct regulator *supply) |
402 | { | 410 | { |
@@ -409,13 +417,10 @@ static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, | |||
409 | { | 417 | { |
410 | return 0; | 418 | return 0; |
411 | } | 419 | } |
412 | |||
413 | static inline int mmc_regulator_get_supply(struct mmc_host *mmc) | ||
414 | { | ||
415 | return 0; | ||
416 | } | ||
417 | #endif | 420 | #endif |
418 | 421 | ||
422 | int mmc_regulator_get_supply(struct mmc_host *mmc); | ||
423 | |||
419 | int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *); | 424 | int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *); |
420 | 425 | ||
421 | static inline int mmc_card_is_removable(struct mmc_host *host) | 426 | static inline int mmc_card_is_removable(struct mmc_host *host) |
@@ -475,4 +480,32 @@ static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) | |||
475 | return host->ios.clock; | 480 | return host->ios.clock; |
476 | } | 481 | } |
477 | #endif | 482 | #endif |
483 | |||
484 | static inline int mmc_card_hs(struct mmc_card *card) | ||
485 | { | ||
486 | return card->host->ios.timing == MMC_TIMING_SD_HS || | ||
487 | card->host->ios.timing == MMC_TIMING_MMC_HS; | ||
488 | } | ||
489 | |||
490 | static inline int mmc_card_uhs(struct mmc_card *card) | ||
491 | { | ||
492 | return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && | ||
493 | card->host->ios.timing <= MMC_TIMING_UHS_DDR50; | ||
494 | } | ||
495 | |||
496 | static inline bool mmc_card_hs200(struct mmc_card *card) | ||
497 | { | ||
498 | return card->host->ios.timing == MMC_TIMING_MMC_HS200; | ||
499 | } | ||
500 | |||
501 | static inline bool mmc_card_ddr52(struct mmc_card *card) | ||
502 | { | ||
503 | return card->host->ios.timing == MMC_TIMING_MMC_DDR52; | ||
504 | } | ||
505 | |||
506 | static inline bool mmc_card_hs400(struct mmc_card *card) | ||
507 | { | ||
508 | return card->host->ios.timing == MMC_TIMING_MMC_HS400; | ||
509 | } | ||
510 | |||
478 | #endif /* LINUX_MMC_HOST_H */ | 511 | #endif /* LINUX_MMC_HOST_H */ |
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 50bcde3677ca..64ec963ed347 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h | |||
@@ -325,6 +325,7 @@ struct _mmc_csd { | |||
325 | #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ | 325 | #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ |
326 | #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ | 326 | #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ |
327 | #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ | 327 | #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ |
328 | #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ | ||
328 | #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ | 329 | #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ |
329 | #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ | 330 | #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ |
330 | #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ | 331 | #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ |
@@ -354,18 +355,25 @@ struct _mmc_csd { | |||
354 | #define EXT_CSD_CMD_SET_SECURE (1<<1) | 355 | #define EXT_CSD_CMD_SET_SECURE (1<<1) |
355 | #define EXT_CSD_CMD_SET_CPSECURE (1<<2) | 356 | #define EXT_CSD_CMD_SET_CPSECURE (1<<2) |
356 | 357 | ||
357 | #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ | 358 | #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ |
358 | #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ | 359 | #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ |
359 | #define EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */ | 360 | #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ |
361 | EXT_CSD_CARD_TYPE_HS_52) | ||
360 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ | 362 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ |
361 | /* DDR mode @1.8V or 3V I/O */ | 363 | /* DDR mode @1.8V or 3V I/O */ |
362 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ | 364 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ |
363 | /* DDR mode @1.2V I/O */ | 365 | /* DDR mode @1.2V I/O */ |
364 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | 366 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ |
365 | | EXT_CSD_CARD_TYPE_DDR_1_2V) | 367 | | EXT_CSD_CARD_TYPE_DDR_1_2V) |
366 | #define EXT_CSD_CARD_TYPE_SDR_1_8V (1<<4) /* Card can run at 200MHz */ | 368 | #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ |
367 | #define EXT_CSD_CARD_TYPE_SDR_1_2V (1<<5) /* Card can run at 200MHz */ | 369 | #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ |
368 | /* SDR mode @1.2V I/O */ | 370 | /* SDR mode @1.2V I/O */ |
371 | #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ | ||
372 | EXT_CSD_CARD_TYPE_HS200_1_2V) | ||
373 | #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ | ||
374 | #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ | ||
375 | #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ | ||
376 | EXT_CSD_CARD_TYPE_HS400_1_2V) | ||
369 | 377 | ||
370 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ | 378 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
371 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | 379 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ |
@@ -373,6 +381,11 @@ struct _mmc_csd { | |||
373 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ | 381 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ |
374 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ | 382 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ |
375 | 383 | ||
384 | #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ | ||
385 | #define EXT_CSD_TIMING_HS 1 /* High speed */ | ||
386 | #define EXT_CSD_TIMING_HS200 2 /* HS200 */ | ||
387 | #define EXT_CSD_TIMING_HS400 3 /* HS400 */ | ||
388 | |||
376 | #define EXT_CSD_SEC_ER_EN BIT(0) | 389 | #define EXT_CSD_SEC_ER_EN BIT(0) |
377 | #define EXT_CSD_SEC_BD_BLK_EN BIT(2) | 390 | #define EXT_CSD_SEC_BD_BLK_EN BIT(2) |
378 | #define EXT_CSD_SEC_GB_CL_EN BIT(4) | 391 | #define EXT_CSD_SEC_GB_CL_EN BIT(4) |
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 7be12b883485..08abe9941884 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h | |||
@@ -57,12 +57,8 @@ struct sdhci_host { | |||
57 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) | 57 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) |
58 | /* Controller reports inverted write-protect state */ | 58 | /* Controller reports inverted write-protect state */ |
59 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) | 59 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) |
60 | /* Controller has nonstandard clock management */ | ||
61 | #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17) | ||
62 | /* Controller does not like fast PIO transfers */ | 60 | /* Controller does not like fast PIO transfers */ |
63 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) | 61 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) |
64 | /* Controller losing signal/interrupt enable states after reset */ | ||
65 | #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) | ||
66 | /* Controller has to be forced to use block size of 2048 bytes */ | 62 | /* Controller has to be forced to use block size of 2048 bytes */ |
67 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) | 63 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) |
68 | /* Controller cannot do multi-block transfers */ | 64 | /* Controller cannot do multi-block transfers */ |
@@ -147,6 +143,7 @@ struct sdhci_host { | |||
147 | 143 | ||
148 | bool runtime_suspended; /* Host is runtime suspended */ | 144 | bool runtime_suspended; /* Host is runtime suspended */ |
149 | bool bus_on; /* Bus power prevents runtime suspend */ | 145 | bool bus_on; /* Bus power prevents runtime suspend */ |
146 | bool preset_enabled; /* Preset is enabled */ | ||
150 | 147 | ||
151 | struct mmc_request *mrq; /* Current request */ | 148 | struct mmc_request *mrq; /* Current request */ |
152 | struct mmc_command *cmd; /* Current command */ | 149 | struct mmc_command *cmd; /* Current command */ |
@@ -164,8 +161,7 @@ struct sdhci_host { | |||
164 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ | 161 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ |
165 | dma_addr_t align_addr; /* Mapped bounce buffer */ | 162 | dma_addr_t align_addr; /* Mapped bounce buffer */ |
166 | 163 | ||
167 | struct tasklet_struct card_tasklet; /* Tasklet structures */ | 164 | struct tasklet_struct finish_tasklet; /* Tasklet structures */ |
168 | struct tasklet_struct finish_tasklet; | ||
169 | 165 | ||
170 | struct timer_list timer; /* Timer for timeouts */ | 166 | struct timer_list timer; /* Timer for timeouts */ |
171 | 167 | ||
@@ -177,6 +173,13 @@ struct sdhci_host { | |||
177 | unsigned int ocr_avail_mmc; | 173 | unsigned int ocr_avail_mmc; |
178 | u32 ocr_mask; /* available voltages */ | 174 | u32 ocr_mask; /* available voltages */ |
179 | 175 | ||
176 | unsigned timing; /* Current timing */ | ||
177 | |||
178 | u32 thread_isr; | ||
179 | |||
180 | /* cached registers */ | ||
181 | u32 ier; | ||
182 | |||
180 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ | 183 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ |
181 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ | 184 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ |
182 | 185 | ||
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index c29a6dee6bec..88e6ea4a5d36 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h | |||
@@ -1,23 +1,6 @@ | |||
1 | /* | ||
2 | * OMAP DMA Engine support | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | #ifndef __LINUX_OMAP_DMA_H | 1 | #ifndef __LINUX_OMAP_DMA_H |
9 | #define __LINUX_OMAP_DMA_H | 2 | #define __LINUX_OMAP_DMA_H |
10 | 3 | #include <linux/omap-dmaengine.h> | |
11 | struct dma_chan; | ||
12 | |||
13 | #if defined(CONFIG_DMA_OMAP) || (defined(CONFIG_DMA_OMAP_MODULE) && defined(MODULE)) | ||
14 | bool omap_dma_filter_fn(struct dma_chan *, void *); | ||
15 | #else | ||
16 | static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d) | ||
17 | { | ||
18 | return false; | ||
19 | } | ||
20 | #endif | ||
21 | 4 | ||
22 | /* | 5 | /* |
23 | * Legacy OMAP DMA handling defines and functions | 6 | * Legacy OMAP DMA handling defines and functions |
diff --git a/include/linux/omap-dmaengine.h b/include/linux/omap-dmaengine.h new file mode 100644 index 000000000000..8e6906c72e90 --- /dev/null +++ b/include/linux/omap-dmaengine.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * OMAP DMA Engine support | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | #ifndef __LINUX_OMAP_DMAENGINE_H | ||
9 | #define __LINUX_OMAP_DMAENGINE_H | ||
10 | |||
11 | struct dma_chan; | ||
12 | |||
13 | #if defined(CONFIG_DMA_OMAP) || (defined(CONFIG_DMA_OMAP_MODULE) && defined(MODULE)) | ||
14 | bool omap_dma_filter_fn(struct dma_chan *, void *); | ||
15 | #else | ||
16 | static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d) | ||
17 | { | ||
18 | return false; | ||
19 | } | ||
20 | #endif | ||
21 | #endif /* __LINUX_OMAP_DMAENGINE_H */ | ||