4 files changed, 27 insertions, 6 deletions

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426d2daa..17b22e9cc2aa 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -554,7 +554,7 @@
                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
                 clocks = <&clock CLK_PWM>;
                 clock-names = "timers";
-                #pwm-cells = <2>;
+                #pwm-cells = <3>;
                 status = "disabled";
         };
 
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f38cf7c110cc..95cad252eb1b 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -297,7 +297,7 @@ static void __init exynos_dt_machine_init(void)
          * This is called from smp_prepare_cpus if we've built for SMP, but
          * we still need to set it up for PM and firmware ops if not.
          */
-        if (!IS_ENABLED(SMP))
+        if (!IS_ENABLED(CONFIG_SMP))
                 exynos_sysram_init();
 
         exynos_cpuidle_init();
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index eb91d2350f8c..e8797bb78871 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -57,8 +57,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 
         boot_reg = sysram_ns_base_addr + 0x1c;
 
-        if (!soc_is_exynos4212() && !soc_is_exynos3250())
-                boot_reg += 4*cpu;
+        /*
+         * Almost all Exynos-series of SoCs that run in secure mode don't need
+         * additional offset for every CPU, with Exynos4412 being the only
+         * exception.
+         */
+        if (soc_is_exynos4412())
+                boot_reg += 4 * cpu;
 
         __raw_writel(boot_addr, boot_reg);
         return 0;
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index f71d55f5e6e5..ab51bf20a3ed 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void)
         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
 
-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static cycle_t notrace _exynos4_frc_read(void)
 {
         unsigned int lo, hi;
         u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
         return ((cycle_t)hi << 32) | lo;
 }
 
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+        return _exynos4_frc_read();
+}
+
 static void exynos4_frc_resume(struct clocksource *cs)
 {
         exynos4_mct_frc_start();
@@ -192,13 +197,24 @@ struct clocksource mct_frc = {
 
 static u64 notrace exynos4_read_sched_clock(void)
 {
-        return exynos4_frc_read(&mct_frc);
+        return _exynos4_frc_read();
+}
+
+static struct delay_timer exynos4_delay_timer;
+
+static cycles_t exynos4_read_current_timer(void)
+{
+        return _exynos4_frc_read();
 }
 
 static void __init exynos4_clocksource_init(void)
 {
         exynos4_mct_frc_start();
 
+        exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
+        exynos4_delay_timer.freq = clk_rate;
+        register_current_timer_delay(&exynos4_delay_timer);
+
         if (clocksource_register_hz(&mct_frc, clk_rate))
                 panic("%s: can't register clocksource\n", mct_frc.name);