diff options
-rw-r--r-- | arch/ia64/sn/pci/pcibr/pcibr_dma.c | 8 | ||||
-rw-r--r-- | include/asm-ia64/sn/pcibr_provider.h | 5 |
2 files changed, 9 insertions, 4 deletions
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c index 1ee977fb6ebb..95af40cb22f2 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c | |||
@@ -96,10 +96,14 @@ pcibr_dmamap_ate32(struct pcidev_info *info, | |||
96 | } | 96 | } |
97 | 97 | ||
98 | /* | 98 | /* |
99 | * If we're mapping for MSI, set the MSI bit in the ATE | 99 | * If we're mapping for MSI, set the MSI bit in the ATE. If it's a |
100 | * TIOCP based pci bus, we also need to set the PIO bit in the ATE. | ||
100 | */ | 101 | */ |
101 | if (dma_flags & SN_DMA_MSI) | 102 | if (dma_flags & SN_DMA_MSI) { |
102 | ate |= PCI32_ATE_MSI; | 103 | ate |= PCI32_ATE_MSI; |
104 | if (IS_TIOCP_SOFT(pcibus_info)) | ||
105 | ate |= PCI32_ATE_PIO; | ||
106 | } | ||
103 | 107 | ||
104 | ate_write(pcibus_info, ate_index, ate_count, ate); | 108 | ate_write(pcibus_info, ate_index, ate_count, ate); |
105 | 109 | ||
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h index 17cb6cc3f21a..da205b7cdaac 100644 --- a/include/asm-ia64/sn/pcibr_provider.h +++ b/include/asm-ia64/sn/pcibr_provider.h | |||
@@ -21,6 +21,7 @@ | |||
21 | #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \ | 21 | #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \ |
22 | asic == PCIIO_ASIC_TYPE_TIOCP) | 22 | asic == PCIIO_ASIC_TYPE_TIOCP) |
23 | #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) | 23 | #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) |
24 | #define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP) | ||
24 | 25 | ||
25 | 26 | ||
26 | /* | 27 | /* |
@@ -53,8 +54,8 @@ | |||
53 | * Bridge PMU Address Transaltion Entry Attibutes | 54 | * Bridge PMU Address Transaltion Entry Attibutes |
54 | */ | 55 | */ |
55 | #define PCI32_ATE_V (0x1 << 0) | 56 | #define PCI32_ATE_V (0x1 << 0) |
56 | #define PCI32_ATE_CO (0x1 << 1) | 57 | #define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */ |
57 | #define PCI32_ATE_PREC (0x1 << 2) | 58 | #define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */ |
58 | #define PCI32_ATE_MSI (0x1 << 2) | 59 | #define PCI32_ATE_MSI (0x1 << 2) |
59 | #define PCI32_ATE_PREF (0x1 << 3) | 60 | #define PCI32_ATE_PREF (0x1 << 3) |
60 | #define PCI32_ATE_BAR (0x1 << 4) | 61 | #define PCI32_ATE_BAR (0x1 << 4) |