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-rw-r--r--drivers/net/igb/e1000_82575.c285
-rw-r--r--drivers/net/igb/e1000_82575.h1
-rw-r--r--drivers/net/igb/e1000_defines.h39
-rw-r--r--drivers/net/igb/e1000_hw.h4
-rw-r--r--drivers/net/igb/e1000_nvm.c64
-rw-r--r--drivers/net/igb/e1000_nvm.h1
-rw-r--r--drivers/net/igb/e1000_regs.h13
-rw-r--r--drivers/net/igb/igb.h6
-rw-r--r--drivers/net/igb/igb_ethtool.c8
-rw-r--r--drivers/net/igb/igb_main.c74
-rw-r--r--drivers/net/ixgbe/ixgbe.h7
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c1
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.c37
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.h4
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.c44
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c71
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.h9
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_nl.c226
-rw-r--r--drivers/net/ixgbe/ixgbe_fcoe.c15
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c425
-rw-r--r--drivers/net/ixgbe/ixgbe_mbx.c6
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c335
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.h1
-rw-r--r--drivers/net/ixgbe/ixgbe_sriov.c85
-rw-r--r--drivers/net/ixgbe/ixgbe_sriov.h1
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h13
-rw-r--r--drivers/net/ixgbevf/ethtool.c4
-rw-r--r--drivers/net/ixgbevf/ixgbevf_main.c4
-rw-r--r--drivers/net/ixgbevf/regs.h2
29 files changed, 1316 insertions, 469 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index 65c1833244f7..6b256c275e10 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -64,7 +64,14 @@ static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *); 64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
66static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 66static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
67 67static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
68static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
69static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw,
70 u16 offset);
71static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
72 u16 offset);
73static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
74static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
68static const u16 e1000_82580_rxpbs_table[] = 75static const u16 e1000_82580_rxpbs_table[] =
69 { 36, 72, 144, 1, 2, 4, 8, 16, 76 { 36, 72, 144, 1, 2, 4, 8, 16,
70 35, 70, 140 }; 77 35, 70, 140 };
@@ -195,7 +202,11 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
195 mac->arc_subsystem_valid = 202 mac->arc_subsystem_valid =
196 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 203 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
197 ? true : false; 204 ? true : false;
198 205 /* enable EEE on i350 parts */
206 if (mac->type == e1000_i350)
207 dev_spec->eee_disable = false;
208 else
209 dev_spec->eee_disable = true;
199 /* physical interface link setup */ 210 /* physical interface link setup */
200 mac->ops.setup_physical_interface = 211 mac->ops.setup_physical_interface =
201 (hw->phy.media_type == e1000_media_type_copper) 212 (hw->phy.media_type == e1000_media_type_copper)
@@ -233,10 +244,32 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
233 */ 244 */
234 size += NVM_WORD_SIZE_BASE_SHIFT; 245 size += NVM_WORD_SIZE_BASE_SHIFT;
235 246
236 /* EEPROM access above 16k is unsupported */
237 if (size > 14)
238 size = 14;
239 nvm->word_size = 1 << size; 247 nvm->word_size = 1 << size;
248 if (nvm->word_size == (1 << 15))
249 nvm->page_size = 128;
250
251 /* NVM Function Pointers */
252 nvm->ops.acquire = igb_acquire_nvm_82575;
253 if (nvm->word_size < (1 << 15))
254 nvm->ops.read = igb_read_nvm_eerd;
255 else
256 nvm->ops.read = igb_read_nvm_spi;
257
258 nvm->ops.release = igb_release_nvm_82575;
259 switch (hw->mac.type) {
260 case e1000_82580:
261 nvm->ops.validate = igb_validate_nvm_checksum_82580;
262 nvm->ops.update = igb_update_nvm_checksum_82580;
263 break;
264 case e1000_i350:
265 nvm->ops.validate = igb_validate_nvm_checksum_i350;
266 nvm->ops.update = igb_update_nvm_checksum_i350;
267 break;
268 default:
269 nvm->ops.validate = igb_validate_nvm_checksum;
270 nvm->ops.update = igb_update_nvm_checksum;
271 }
272 nvm->ops.write = igb_write_nvm_spi;
240 273
241 /* if part supports SR-IOV then initialize mailbox parameters */ 274 /* if part supports SR-IOV then initialize mailbox parameters */
242 switch (mac->type) { 275 switch (mac->type) {
@@ -1754,6 +1787,248 @@ u16 igb_rxpbs_adjust_82580(u32 data)
1754 return ret_val; 1787 return ret_val;
1755} 1788}
1756 1789
1790/**
1791 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
1792 * checksum
1793 * @hw: pointer to the HW structure
1794 * @offset: offset in words of the checksum protected region
1795 *
1796 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1797 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1798 **/
1799s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1800{
1801 s32 ret_val = 0;
1802 u16 checksum = 0;
1803 u16 i, nvm_data;
1804
1805 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
1806 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1807 if (ret_val) {
1808 hw_dbg("NVM Read Error\n");
1809 goto out;
1810 }
1811 checksum += nvm_data;
1812 }
1813
1814 if (checksum != (u16) NVM_SUM) {
1815 hw_dbg("NVM Checksum Invalid\n");
1816 ret_val = -E1000_ERR_NVM;
1817 goto out;
1818 }
1819
1820out:
1821 return ret_val;
1822}
1823
1824/**
1825 * igb_update_nvm_checksum_with_offset - Update EEPROM
1826 * checksum
1827 * @hw: pointer to the HW structure
1828 * @offset: offset in words of the checksum protected region
1829 *
1830 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1831 * up to the checksum. Then calculates the EEPROM checksum and writes the
1832 * value to the EEPROM.
1833 **/
1834s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1835{
1836 s32 ret_val;
1837 u16 checksum = 0;
1838 u16 i, nvm_data;
1839
1840 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
1841 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1842 if (ret_val) {
1843 hw_dbg("NVM Read Error while updating checksum.\n");
1844 goto out;
1845 }
1846 checksum += nvm_data;
1847 }
1848 checksum = (u16) NVM_SUM - checksum;
1849 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
1850 &checksum);
1851 if (ret_val)
1852 hw_dbg("NVM Write Error while updating checksum.\n");
1853
1854out:
1855 return ret_val;
1856}
1857
1858/**
1859 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
1860 * @hw: pointer to the HW structure
1861 *
1862 * Calculates the EEPROM section checksum by reading/adding each word of
1863 * the EEPROM and then verifies that the sum of the EEPROM is
1864 * equal to 0xBABA.
1865 **/
1866static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
1867{
1868 s32 ret_val = 0;
1869 u16 eeprom_regions_count = 1;
1870 u16 j, nvm_data;
1871 u16 nvm_offset;
1872
1873 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1874 if (ret_val) {
1875 hw_dbg("NVM Read Error\n");
1876 goto out;
1877 }
1878
1879 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
1880 /* if chekcsums compatibility bit is set validate checksums
1881 * for all 4 ports. */
1882 eeprom_regions_count = 4;
1883 }
1884
1885 for (j = 0; j < eeprom_regions_count; j++) {
1886 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1887 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1888 nvm_offset);
1889 if (ret_val != 0)
1890 goto out;
1891 }
1892
1893out:
1894 return ret_val;
1895}
1896
1897/**
1898 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
1899 * @hw: pointer to the HW structure
1900 *
1901 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1902 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1903 * checksum and writes the value to the EEPROM.
1904 **/
1905static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
1906{
1907 s32 ret_val;
1908 u16 j, nvm_data;
1909 u16 nvm_offset;
1910
1911 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1912 if (ret_val) {
1913 hw_dbg("NVM Read Error while updating checksum"
1914 " compatibility bit.\n");
1915 goto out;
1916 }
1917
1918 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
1919 /* set compatibility bit to validate checksums appropriately */
1920 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
1921 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
1922 &nvm_data);
1923 if (ret_val) {
1924 hw_dbg("NVM Write Error while updating checksum"
1925 " compatibility bit.\n");
1926 goto out;
1927 }
1928 }
1929
1930 for (j = 0; j < 4; j++) {
1931 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1932 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
1933 if (ret_val)
1934 goto out;
1935 }
1936
1937out:
1938 return ret_val;
1939}
1940
1941/**
1942 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
1943 * @hw: pointer to the HW structure
1944 *
1945 * Calculates the EEPROM section checksum by reading/adding each word of
1946 * the EEPROM and then verifies that the sum of the EEPROM is
1947 * equal to 0xBABA.
1948 **/
1949static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
1950{
1951 s32 ret_val = 0;
1952 u16 j;
1953 u16 nvm_offset;
1954
1955 for (j = 0; j < 4; j++) {
1956 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1957 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1958 nvm_offset);
1959 if (ret_val != 0)
1960 goto out;
1961 }
1962
1963out:
1964 return ret_val;
1965}
1966
1967/**
1968 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
1969 * @hw: pointer to the HW structure
1970 *
1971 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1972 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1973 * checksum and writes the value to the EEPROM.
1974 **/
1975static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
1976{
1977 s32 ret_val = 0;
1978 u16 j;
1979 u16 nvm_offset;
1980
1981 for (j = 0; j < 4; j++) {
1982 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1983 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
1984 if (ret_val != 0)
1985 goto out;
1986 }
1987
1988out:
1989 return ret_val;
1990}
1991/**
1992 * igb_set_eee_i350 - Enable/disable EEE support
1993 * @hw: pointer to the HW structure
1994 *
1995 * Enable/disable EEE based on setting in dev_spec structure.
1996 *
1997 **/
1998s32 igb_set_eee_i350(struct e1000_hw *hw)
1999{
2000 s32 ret_val = 0;
2001 u32 ipcnfg, eeer, ctrl_ext;
2002
2003 ctrl_ext = rd32(E1000_CTRL_EXT);
2004 if ((hw->mac.type != e1000_i350) ||
2005 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2006 goto out;
2007 ipcnfg = rd32(E1000_IPCNFG);
2008 eeer = rd32(E1000_EEER);
2009
2010 /* enable or disable per user setting */
2011 if (!(hw->dev_spec._82575.eee_disable)) {
2012 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2013 E1000_IPCNFG_EEE_100M_AN);
2014 eeer |= (E1000_EEER_TX_LPI_EN |
2015 E1000_EEER_RX_LPI_EN |
2016 E1000_EEER_LPI_FC);
2017
2018 } else {
2019 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2020 E1000_IPCNFG_EEE_100M_AN);
2021 eeer &= ~(E1000_EEER_TX_LPI_EN |
2022 E1000_EEER_RX_LPI_EN |
2023 E1000_EEER_LPI_FC);
2024 }
2025 wr32(E1000_IPCNFG, ipcnfg);
2026 wr32(E1000_EEER, eeer);
2027out:
2028
2029 return ret_val;
2030}
2031
1757static struct e1000_mac_operations e1000_mac_ops_82575 = { 2032static struct e1000_mac_operations e1000_mac_ops_82575 = {
1758 .init_hw = igb_init_hw_82575, 2033 .init_hw = igb_init_hw_82575,
1759 .check_for_link = igb_check_for_link_82575, 2034 .check_for_link = igb_check_for_link_82575,
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index 1d01af2472e7..dd6df3498998 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -251,5 +251,6 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
251void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool); 251void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
252void igb_vmdq_set_replication_pf(struct e1000_hw *, bool); 252void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
253u16 igb_rxpbs_adjust_82580(u32 data); 253u16 igb_rxpbs_adjust_82580(u32 data);
254s32 igb_set_eee_i350(struct e1000_hw *);
254 255
255#endif 256#endif
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 92e11da25749..9bb192825893 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -287,7 +287,34 @@
287#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 287#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
288#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 288#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
289 289
290/* Transmit Arbitration Count */ 290/* DMA Coalescing register fields */
291#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing
292 * Watchdog Timer */
293#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive
294 * Threshold */
295#define E1000_DMACR_DMACTHR_SHIFT 16
296#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe
297 * transactions */
298#define E1000_DMACR_DMAC_LX_SHIFT 28
299#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
300
301#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit
302 * Threshold */
303
304#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
305
306#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate
307 * Threshold */
308#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in
309 * current window */
310
311#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic
312 * Current Cnt */
313
314#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold
315 * High val */
316#define E1000_FCRTC_RTH_COAL_SHIFT 4
317#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */
291 318
292/* SerDes Control */ 319/* SerDes Control */
293#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 320#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
@@ -566,6 +593,8 @@
566#define NVM_INIT_CONTROL3_PORT_A 0x0024 593#define NVM_INIT_CONTROL3_PORT_A 0x0024
567#define NVM_ALT_MAC_ADDR_PTR 0x0037 594#define NVM_ALT_MAC_ADDR_PTR 0x0037
568#define NVM_CHECKSUM_REG 0x003F 595#define NVM_CHECKSUM_REG 0x003F
596#define NVM_COMPATIBILITY_REG_3 0x0003
597#define NVM_COMPATIBILITY_BIT_MASK 0x8000
569 598
570#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 599#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
571#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 600#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
@@ -600,6 +629,7 @@
600/* NVM Commands - SPI */ 629/* NVM Commands - SPI */
601#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 630#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
602#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 631#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
632#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
603#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 633#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
604#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 634#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
605#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 635#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
@@ -758,6 +788,13 @@
758#define E1000_MDIC_ERROR 0x40000000 788#define E1000_MDIC_ERROR 0x40000000
759#define E1000_MDIC_DEST 0x80000000 789#define E1000_MDIC_DEST 0x80000000
760 790
791/* Energy Efficient Ethernet */
792#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */
793#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
794#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
795#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
796#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
797
761/* SerDes Control */ 798/* SerDes Control */
762#define E1000_GEN_CTL_READY 0x80000000 799#define E1000_GEN_CTL_READY 0x80000000
763#define E1000_GEN_CTL_ADDRESS_SHIFT 8 800#define E1000_GEN_CTL_ADDRESS_SHIFT 8
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h
index eec9ed735588..27153e8d7b16 100644
--- a/drivers/net/igb/e1000_hw.h
+++ b/drivers/net/igb/e1000_hw.h
@@ -336,6 +336,8 @@ struct e1000_nvm_operations {
336 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 336 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
337 void (*release)(struct e1000_hw *); 337 void (*release)(struct e1000_hw *);
338 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 338 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
339 s32 (*update)(struct e1000_hw *);
340 s32 (*validate)(struct e1000_hw *);
339}; 341};
340 342
341struct e1000_info { 343struct e1000_info {
@@ -422,7 +424,6 @@ struct e1000_phy_info {
422 424
423struct e1000_nvm_info { 425struct e1000_nvm_info {
424 struct e1000_nvm_operations ops; 426 struct e1000_nvm_operations ops;
425
426 enum e1000_nvm_type type; 427 enum e1000_nvm_type type;
427 enum e1000_nvm_override override; 428 enum e1000_nvm_override override;
428 429
@@ -488,6 +489,7 @@ struct e1000_mbx_info {
488struct e1000_dev_spec_82575 { 489struct e1000_dev_spec_82575 {
489 bool sgmii_active; 490 bool sgmii_active;
490 bool global_device_reset; 491 bool global_device_reset;
492 bool eee_disable;
491}; 493};
492 494
493struct e1000_hw { 495struct e1000_hw {
diff --git a/drivers/net/igb/e1000_nvm.c b/drivers/net/igb/e1000_nvm.c
index 6b5cc2cc453d..75bf36a4baee 100644
--- a/drivers/net/igb/e1000_nvm.c
+++ b/drivers/net/igb/e1000_nvm.c
@@ -318,6 +318,68 @@ out:
318} 318}
319 319
320/** 320/**
321 * igb_read_nvm_spi - Read EEPROM's using SPI
322 * @hw: pointer to the HW structure
323 * @offset: offset of word in the EEPROM to read
324 * @words: number of words to read
325 * @data: word read from the EEPROM
326 *
327 * Reads a 16 bit word from the EEPROM.
328 **/
329s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
330{
331 struct e1000_nvm_info *nvm = &hw->nvm;
332 u32 i = 0;
333 s32 ret_val;
334 u16 word_in;
335 u8 read_opcode = NVM_READ_OPCODE_SPI;
336
337 /*
338 * A check for invalid values: offset too large, too many words,
339 * and not enough words.
340 */
341 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
342 (words == 0)) {
343 hw_dbg("nvm parameter(s) out of bounds\n");
344 ret_val = -E1000_ERR_NVM;
345 goto out;
346 }
347
348 ret_val = nvm->ops.acquire(hw);
349 if (ret_val)
350 goto out;
351
352 ret_val = igb_ready_nvm_eeprom(hw);
353 if (ret_val)
354 goto release;
355
356 igb_standby_nvm(hw);
357
358 if ((nvm->address_bits == 8) && (offset >= 128))
359 read_opcode |= NVM_A8_OPCODE_SPI;
360
361 /* Send the READ command (opcode + addr) */
362 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
363 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
364
365 /*
366 * Read the data. SPI NVMs increment the address with each byte
367 * read and will roll over if reading beyond the end. This allows
368 * us to read the whole NVM from any offset
369 */
370 for (i = 0; i < words; i++) {
371 word_in = igb_shift_in_eec_bits(hw, 16);
372 data[i] = (word_in >> 8) | (word_in << 8);
373 }
374
375release:
376 nvm->ops.release(hw);
377
378out:
379 return ret_val;
380}
381
382/**
321 * igb_read_nvm_eerd - Reads EEPROM using EERD register 383 * igb_read_nvm_eerd - Reads EEPROM using EERD register
322 * @hw: pointer to the HW structure 384 * @hw: pointer to the HW structure
323 * @offset: offset of word in the EEPROM to read 385 * @offset: offset of word in the EEPROM to read
@@ -353,7 +415,7 @@ s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
353 break; 415 break;
354 416
355 data[i] = (rd32(E1000_EERD) >> 417 data[i] = (rd32(E1000_EERD) >>
356 E1000_NVM_RW_REG_DATA); 418 E1000_NVM_RW_REG_DATA);
357 } 419 }
358 420
359out: 421out:
diff --git a/drivers/net/igb/e1000_nvm.h b/drivers/net/igb/e1000_nvm.h
index 29c956a84bd0..7f43564c4bcc 100644
--- a/drivers/net/igb/e1000_nvm.h
+++ b/drivers/net/igb/e1000_nvm.h
@@ -35,6 +35,7 @@ s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
35s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, 35s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num,
36 u32 part_num_size); 36 u32 part_num_size);
37s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 37s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
38s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
38s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 39s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
39s32 igb_validate_nvm_checksum(struct e1000_hw *hw); 40s32 igb_validate_nvm_checksum(struct e1000_hw *hw);
40s32 igb_update_nvm_checksum(struct e1000_hw *hw); 41s32 igb_update_nvm_checksum(struct e1000_hw *hw);
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index 61713548c027..ad77ed510d7c 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -106,6 +106,15 @@
106 106
107#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40)) 107#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
108 108
109/* DMA Coalescing registers */
110#define E1000_DMACR 0x02508 /* Control Register */
111#define E1000_DMCTXTH 0x03550 /* Transmit Threshold */
112#define E1000_DMCTLX 0x02514 /* Time to Lx Request */
113#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */
114#define E1000_DMCCNT 0x05DD4 /* Current Rx Count */
115#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */
116#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */
117
109/* TX Rate Limit Registers */ 118/* TX Rate Limit Registers */
110#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select - WO */ 119#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select - WO */
111#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config - WO */ 120#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config - WO */
@@ -329,6 +338,10 @@
329/* DMA Coalescing registers */ 338/* DMA Coalescing registers */
330#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 339#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */
331 340
341/* Energy Efficient Ethernet "EEE" register */
342#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */
343#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet */
344
332/* OS2BMC Registers */ 345/* OS2BMC Registers */
333#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ 346#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */
334#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ 347#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h
index bbc5ebfe254a..1c687e298d5e 100644
--- a/drivers/net/igb/igb.h
+++ b/drivers/net/igb/igb.h
@@ -333,6 +333,12 @@ struct igb_adapter {
333#define IGB_FLAG_DCA_ENABLED (1 << 1) 333#define IGB_FLAG_DCA_ENABLED (1 << 1)
334#define IGB_FLAG_QUAD_PORT_A (1 << 2) 334#define IGB_FLAG_QUAD_PORT_A (1 << 2)
335#define IGB_FLAG_QUEUE_PAIRS (1 << 3) 335#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
336#define IGB_FLAG_DMAC (1 << 4)
337
338/* DMA Coalescing defines */
339#define IGB_MIN_TXPBSIZE 20408
340#define IGB_TX_BUF_4096 4096
341#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
336 342
337#define IGB_82576_TSYNC_SHIFT 19 343#define IGB_82576_TSYNC_SHIFT 19
338#define IGB_82580_TSYNC_SHIFT 24 344#define IGB_82580_TSYNC_SHIFT 24
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index 78d420b4b2db..d976733bbcc2 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -721,7 +721,7 @@ static int igb_set_eeprom(struct net_device *netdev,
721 /* Update the checksum over the first part of the EEPROM if needed 721 /* Update the checksum over the first part of the EEPROM if needed
722 * and flush shadow RAM for 82573 controllers */ 722 * and flush shadow RAM for 82573 controllers */
723 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) 723 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
724 igb_update_nvm_checksum(hw); 724 hw->nvm.ops.update(hw);
725 725
726 kfree(eeprom_buff); 726 kfree(eeprom_buff);
727 return ret_val; 727 return ret_val;
@@ -2009,6 +2009,12 @@ static int igb_set_coalesce(struct net_device *netdev,
2009 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2009 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2010 return -EINVAL; 2010 return -EINVAL;
2011 2011
2012 /* If ITR is disabled, disable DMAC */
2013 if (ec->rx_coalesce_usecs == 0) {
2014 if (adapter->flags & IGB_FLAG_DMAC)
2015 adapter->flags &= ~IGB_FLAG_DMAC;
2016 }
2017
2012 /* convert to rate of irq's per second */ 2018 /* convert to rate of irq's per second */
2013 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2019 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2014 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2020 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 3666b967846a..b4f92b06f2ac 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -50,7 +50,12 @@
50#endif 50#endif
51#include "igb.h" 51#include "igb.h"
52 52
53#define DRV_VERSION "2.4.13-k2" 53#define MAJ 3
54#define MIN 0
55#define BUILD 6
56#define KFIX 2
57#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
58__stringify(BUILD) "-k" __stringify(KFIX)
54char igb_driver_name[] = "igb"; 59char igb_driver_name[] = "igb";
55char igb_driver_version[] = DRV_VERSION; 60char igb_driver_version[] = DRV_VERSION;
56static const char igb_driver_string[] = 61static const char igb_driver_string[] =
@@ -1674,7 +1679,58 @@ void igb_reset(struct igb_adapter *adapter)
1674 1679
1675 if (hw->mac.ops.init_hw(hw)) 1680 if (hw->mac.ops.init_hw(hw))
1676 dev_err(&pdev->dev, "Hardware Error\n"); 1681 dev_err(&pdev->dev, "Hardware Error\n");
1682 if (hw->mac.type > e1000_82580) {
1683 if (adapter->flags & IGB_FLAG_DMAC) {
1684 u32 reg;
1677 1685
1686 /*
1687 * DMA Coalescing high water mark needs to be higher
1688 * than * the * Rx threshold. The Rx threshold is
1689 * currently * pba - 6, so we * should use a high water
1690 * mark of pba * - 4. */
1691 hwm = (pba - 4) << 10;
1692
1693 reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
1694 & E1000_DMACR_DMACTHR_MASK);
1695
1696 /* transition to L0x or L1 if available..*/
1697 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1698
1699 /* watchdog timer= +-1000 usec in 32usec intervals */
1700 reg |= (1000 >> 5);
1701 wr32(E1000_DMACR, reg);
1702
1703 /* no lower threshold to disable coalescing(smart fifb)
1704 * -UTRESH=0*/
1705 wr32(E1000_DMCRTRH, 0);
1706
1707 /* set hwm to PBA - 2 * max frame size */
1708 wr32(E1000_FCRTC, hwm);
1709
1710 /*
1711 * This sets the time to wait before requesting tran-
1712 * sition to * low power state to number of usecs needed
1713 * to receive 1 512 * byte frame at gigabit line rate
1714 */
1715 reg = rd32(E1000_DMCTLX);
1716 reg |= IGB_DMCTLX_DCFLUSH_DIS;
1717
1718 /* Delay 255 usec before entering Lx state. */
1719 reg |= 0xFF;
1720 wr32(E1000_DMCTLX, reg);
1721
1722 /* free space in Tx packet buffer to wake from DMAC */
1723 wr32(E1000_DMCTXTH,
1724 (IGB_MIN_TXPBSIZE -
1725 (IGB_TX_BUF_4096 + adapter->max_frame_size))
1726 >> 6);
1727
1728 /* make low power state decision controlled by DMAC */
1729 reg = rd32(E1000_PCIEMISC);
1730 reg |= E1000_PCIEMISC_LX_DECISION;
1731 wr32(E1000_PCIEMISC, reg);
1732 } /* end if IGB_FLAG_DMAC set */
1733 }
1678 if (hw->mac.type == e1000_82580) { 1734 if (hw->mac.type == e1000_82580) {
1679 u32 reg = rd32(E1000_PCIEMISC); 1735 u32 reg = rd32(E1000_PCIEMISC);
1680 wr32(E1000_PCIEMISC, 1736 wr32(E1000_PCIEMISC,
@@ -1884,7 +1940,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1884 hw->mac.ops.reset_hw(hw); 1940 hw->mac.ops.reset_hw(hw);
1885 1941
1886 /* make sure the NVM is good */ 1942 /* make sure the NVM is good */
1887 if (igb_validate_nvm_checksum(hw) < 0) { 1943 if (hw->nvm.ops.validate(hw) < 0) {
1888 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 1944 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1889 err = -EIO; 1945 err = -EIO;
1890 goto err_eeprom; 1946 goto err_eeprom;
@@ -2014,7 +2070,13 @@ static int __devinit igb_probe(struct pci_dev *pdev,
2014 adapter->msix_entries ? "MSI-X" : 2070 adapter->msix_entries ? "MSI-X" :
2015 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2071 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2016 adapter->num_rx_queues, adapter->num_tx_queues); 2072 adapter->num_rx_queues, adapter->num_tx_queues);
2017 2073 switch (hw->mac.type) {
2074 case e1000_i350:
2075 igb_set_eee_i350(hw);
2076 break;
2077 default:
2078 break;
2079 }
2018 return 0; 2080 return 0;
2019 2081
2020err_register: 2082err_register:
@@ -2151,6 +2213,9 @@ static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2151 random_ether_addr(mac_addr); 2213 random_ether_addr(mac_addr);
2152 igb_set_vf_mac(adapter, i, mac_addr); 2214 igb_set_vf_mac(adapter, i, mac_addr);
2153 } 2215 }
2216 /* DMA Coalescing is not supported in IOV mode. */
2217 if (adapter->flags & IGB_FLAG_DMAC)
2218 adapter->flags &= ~IGB_FLAG_DMAC;
2154 } 2219 }
2155#endif /* CONFIG_PCI_IOV */ 2220#endif /* CONFIG_PCI_IOV */
2156} 2221}
@@ -2325,6 +2390,9 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
2325 /* Explicitly disable IRQ since the NIC can be in any state. */ 2390 /* Explicitly disable IRQ since the NIC can be in any state. */
2326 igb_irq_disable(adapter); 2391 igb_irq_disable(adapter);
2327 2392
2393 if (hw->mac.type == e1000_i350)
2394 adapter->flags &= ~IGB_FLAG_DMAC;
2395
2328 set_bit(__IGB_DOWN, &adapter->state); 2396 set_bit(__IGB_DOWN, &adapter->state);
2329 return 0; 2397 return 0;
2330} 2398}
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 1e546fc127d0..8d468028bb55 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -118,6 +118,7 @@ struct vf_data_storage {
118 bool pf_set_mac; 118 bool pf_set_mac;
119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
120 u16 pf_qos; 120 u16 pf_qos;
121 u16 tx_rate;
121}; 122};
122 123
123/* wrapper around a pointer to a socket buffer, 124/* wrapper around a pointer to a socket buffer,
@@ -209,6 +210,7 @@ struct ixgbe_ring {
209 * associated with this ring, which is 210 * associated with this ring, which is
210 * different for DCB and RSS modes 211 * different for DCB and RSS modes
211 */ 212 */
213 u8 dcb_tc;
212 214
213 u16 work_limit; /* max work per interrupt */ 215 u16 work_limit; /* max work per interrupt */
214 216
@@ -243,7 +245,7 @@ enum ixgbe_ring_f_enum {
243 RING_F_ARRAY_SIZE /* must be last in enum set */ 245 RING_F_ARRAY_SIZE /* must be last in enum set */
244}; 246};
245 247
246#define IXGBE_MAX_DCB_INDICES 8 248#define IXGBE_MAX_DCB_INDICES 64
247#define IXGBE_MAX_RSS_INDICES 16 249#define IXGBE_MAX_RSS_INDICES 16
248#define IXGBE_MAX_VMDQ_INDICES 64 250#define IXGBE_MAX_VMDQ_INDICES 64
249#define IXGBE_MAX_FDIR_INDICES 64 251#define IXGBE_MAX_FDIR_INDICES 64
@@ -341,6 +343,7 @@ struct ixgbe_adapter {
341 struct ixgbe_dcb_config dcb_cfg; 343 struct ixgbe_dcb_config dcb_cfg;
342 struct ixgbe_dcb_config temp_dcb_cfg; 344 struct ixgbe_dcb_config temp_dcb_cfg;
343 u8 dcb_set_bitmap; 345 u8 dcb_set_bitmap;
346 u8 dcbx_cap;
344 enum ixgbe_fc_mode last_lfc_mode; 347 enum ixgbe_fc_mode last_lfc_mode;
345 348
346 /* Interrupt Throttle Rate */ 349 /* Interrupt Throttle Rate */
@@ -466,6 +469,7 @@ struct ixgbe_adapter {
466 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 469 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
467 unsigned int num_vfs; 470 unsigned int num_vfs;
468 struct vf_data_storage *vfinfo; 471 struct vf_data_storage *vfinfo;
472 int vf_rate_link_speed;
469}; 473};
470 474
471enum ixbge_state_t { 475enum ixbge_state_t {
@@ -541,6 +545,7 @@ extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
541extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, 545extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
542 struct ixgbe_ring *ring); 546 struct ixgbe_ring *ring);
543extern void ixgbe_set_rx_mode(struct net_device *netdev); 547extern void ixgbe_set_rx_mode(struct net_device *netdev);
548extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
544#ifdef IXGBE_FCOE 549#ifdef IXGBE_FCOE
545extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 550extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
546extern int ixgbe_fso(struct ixgbe_adapter *adapter, 551extern int ixgbe_fso(struct ixgbe_adapter *adapter,
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index ff23907bde0c..845c679c8b87 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -158,6 +158,7 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
158 158
159 switch (hw->phy.type) { 159 switch (hw->phy.type) {
160 case ixgbe_phy_tn: 160 case ixgbe_phy_tn:
161 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
161 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 162 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
162 phy->ops.get_firmware_version = 163 phy->ops.get_firmware_version =
163 &ixgbe_get_phy_firmware_version_tnx; 164 &ixgbe_get_phy_firmware_version_tnx;
diff --git a/drivers/net/ixgbe/ixgbe_dcb.c b/drivers/net/ixgbe/ixgbe_dcb.c
index c2ee6fcb4e91..41c529fac0ab 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ixgbe/ixgbe_dcb.c
@@ -64,7 +64,7 @@ s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, __u16 *max, int max_frame)
64 val = min_credit; 64 val = min_credit;
65 refill[i] = val; 65 refill[i] = val;
66 66
67 max[i] = (bw[i] * MAX_CREDIT)/100; 67 max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit;
68 } 68 }
69 return 0; 69 return 0;
70} 70}
@@ -246,6 +246,8 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
246 u8 bwgid[MAX_TRAFFIC_CLASS]; 246 u8 bwgid[MAX_TRAFFIC_CLASS];
247 u16 refill[MAX_TRAFFIC_CLASS]; 247 u16 refill[MAX_TRAFFIC_CLASS];
248 u16 max[MAX_TRAFFIC_CLASS]; 248 u16 max[MAX_TRAFFIC_CLASS];
249 /* CEE does not define a priority to tc mapping so map 1:1 */
250 u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7};
249 251
250 /* Unpack CEE standard containers */ 252 /* Unpack CEE standard containers */
251 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en); 253 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
@@ -264,7 +266,7 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
264 case ixgbe_mac_X540: 266 case ixgbe_mac_X540:
265 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg, 267 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,
266 pfc_en, refill, max, bwgid, 268 pfc_en, refill, max, bwgid,
267 ptype); 269 ptype, prio_tc);
268 break; 270 break;
269 default: 271 default:
270 break; 272 break;
@@ -292,30 +294,9 @@ s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en)
292} 294}
293 295
294s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 296s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
295 u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa) 297 u16 *refill, u16 *max, u8 *bwg_id,
298 u8 *prio_type, u8 *prio_tc)
296{ 299{
297 int i;
298 u8 prio_type[IEEE_8021QAZ_MAX_TCS];
299
300 /* Map TSA onto CEE prio type */
301 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
302 switch (tsa[i]) {
303 case IEEE_8021QAZ_TSA_STRICT:
304 prio_type[i] = 2;
305 break;
306 case IEEE_8021QAZ_TSA_ETS:
307 prio_type[i] = 0;
308 break;
309 default:
310 /* Hardware only supports priority strict or
311 * ETS transmission selection algorithms if
312 * we receive some other value from dcbnl
313 * throw an error
314 */
315 return -EINVAL;
316 }
317 }
318
319 switch (hw->mac.type) { 300 switch (hw->mac.type) {
320 case ixgbe_mac_82598EB: 301 case ixgbe_mac_82598EB:
321 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, 302 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max,
@@ -328,11 +309,11 @@ s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
328 case ixgbe_mac_82599EB: 309 case ixgbe_mac_82599EB:
329 case ixgbe_mac_X540: 310 case ixgbe_mac_X540:
330 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, 311 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
331 bwg_id, prio_type); 312 bwg_id, prio_type, prio_tc);
332 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 313 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
333 bwg_id, prio_type); 314 bwg_id, prio_type);
334 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 315 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
335 bwg_id, prio_type); 316 prio_type, prio_tc);
336 break; 317 break;
337 default: 318 default:
338 break; 319 break;
diff --git a/drivers/net/ixgbe/ixgbe_dcb.h b/drivers/net/ixgbe/ixgbe_dcb.h
index 515bc27477f6..944838fc7b59 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.h
+++ b/drivers/net/ixgbe/ixgbe_dcb.h
@@ -159,8 +159,8 @@ s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
159 struct ixgbe_dcb_config *, int, u8); 159 struct ixgbe_dcb_config *, int, u8);
160 160
161/* DCB hw initialization */ 161/* DCB hw initialization */
162s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 162s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
163 u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type); 163 u8 *bwg_id, u8 *prio_type, u8 *tc_prio);
164s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en); 164s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en);
165s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); 165s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
166 166
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index c97cf9160dc0..1bc57e52cee3 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -233,21 +233,27 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
233 u32 reg, rx_pba_size; 233 u32 reg, rx_pba_size;
234 u8 i; 234 u8 i;
235 235
236 if (!pfc_en) 236 if (pfc_en) {
237 goto out; 237 /* Enable Transmit Priority Flow Control */
238 238 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
239 /* Enable Transmit Priority Flow Control */ 239 reg &= ~IXGBE_RMCS_TFCE_802_3X;
240 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 240 /* correct the reporting of our flow control status */
241 reg &= ~IXGBE_RMCS_TFCE_802_3X; 241 reg |= IXGBE_RMCS_TFCE_PRIORITY;
242 /* correct the reporting of our flow control status */ 242 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
243 reg |= IXGBE_RMCS_TFCE_PRIORITY; 243
244 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 244 /* Enable Receive Priority Flow Control */
245 245 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
246 /* Enable Receive Priority Flow Control */ 246 reg &= ~IXGBE_FCTRL_RFCE;
247 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 247 reg |= IXGBE_FCTRL_RPFCE;
248 reg &= ~IXGBE_FCTRL_RFCE; 248 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
249 reg |= IXGBE_FCTRL_RPFCE; 249
250 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 250 /* Configure pause time */
251 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
252 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
253
254 /* Configure flow control refresh threshold value */
255 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
256 }
251 257
252 /* 258 /*
253 * Configure flow control thresholds and enable priority flow control 259 * Configure flow control thresholds and enable priority flow control
@@ -273,14 +279,6 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
273 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 279 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
274 } 280 }
275 281
276 /* Configure pause time */
277 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
278 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
279
280 /* Configure flow control refresh threshold value */
281 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
282
283out:
284 return 0; 282 return 0;
285} 283}
286 284
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index beaa1c1c1e67..025af8c53ddb 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -85,7 +85,8 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
85 u16 *refill, 85 u16 *refill,
86 u16 *max, 86 u16 *max,
87 u8 *bwg_id, 87 u8 *bwg_id,
88 u8 *prio_type) 88 u8 *prio_type,
89 u8 *prio_tc)
89{ 90{
90 u32 reg = 0; 91 u32 reg = 0;
91 u32 credit_refill = 0; 92 u32 credit_refill = 0;
@@ -102,7 +103,7 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
102 /* Map all traffic classes to their UP, 1 to 1 */ 103 /* Map all traffic classes to their UP, 1 to 1 */
103 reg = 0; 104 reg = 0;
104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 105 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
105 reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 106 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
106 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 107 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
107 108
108 /* Configure traffic class credits and priority */ 109 /* Configure traffic class credits and priority */
@@ -194,7 +195,8 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
194 u16 *refill, 195 u16 *refill,
195 u16 *max, 196 u16 *max,
196 u8 *bwg_id, 197 u8 *bwg_id,
197 u8 *prio_type) 198 u8 *prio_type,
199 u8 *prio_tc)
198{ 200{
199 u32 reg; 201 u32 reg;
200 u8 i; 202 u8 i;
@@ -211,7 +213,7 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
211 /* Map all traffic classes to their UP, 1 to 1 */ 213 /* Map all traffic classes to their UP, 1 to 1 */
212 reg = 0; 214 reg = 0;
213 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 215 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
214 reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 216 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
215 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 217 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
216 218
217 /* Configure traffic class credits and priority */ 219 /* Configure traffic class credits and priority */
@@ -251,13 +253,6 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
251{ 253{
252 u32 i, reg, rx_pba_size; 254 u32 i, reg, rx_pba_size;
253 255
254 /* If PFC is disabled globally then fall back to LFC. */
255 if (!pfc_en) {
256 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
257 hw->mac.ops.fc_enable(hw, i);
258 goto out;
259 }
260
261 /* Configure PFC Tx thresholds per TC */ 256 /* Configure PFC Tx thresholds per TC */
262 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 257 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
263 int enabled = pfc_en & (1 << i); 258 int enabled = pfc_en & (1 << i);
@@ -276,28 +271,33 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
276 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 271 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
277 } 272 }
278 273
279 /* Configure pause time (2 TCs per register) */ 274 if (pfc_en) {
280 reg = hw->fc.pause_time | (hw->fc.pause_time << 16); 275 /* Configure pause time (2 TCs per register) */
281 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 276 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
282 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 277 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
283 278 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
284 /* Configure flow control refresh threshold value */ 279
285 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 280 /* Configure flow control refresh threshold value */
286 281 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
287 /* Enable Transmit PFC */ 282
288 reg = IXGBE_FCCFG_TFCE_PRIORITY; 283
289 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg); 284 reg = IXGBE_FCCFG_TFCE_PRIORITY;
285 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
286 /*
287 * Enable Receive PFC
288 * We will always honor XOFF frames we receive when
289 * we are in PFC mode.
290 */
291 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
292 reg &= ~IXGBE_MFLCN_RFCE;
293 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
294 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
295
296 } else {
297 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
298 hw->mac.ops.fc_enable(hw, i);
299 }
290 300
291 /*
292 * Enable Receive PFC
293 * We will always honor XOFF frames we receive when
294 * we are in PFC mode.
295 */
296 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
297 reg &= ~IXGBE_MFLCN_RFCE;
298 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
299 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
300out:
301 return 0; 301 return 0;
302} 302}
303 303
@@ -424,15 +424,16 @@ static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
424 */ 424 */
425s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, 425s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
426 u8 rx_pba, u8 pfc_en, u16 *refill, 426 u8 rx_pba, u8 pfc_en, u16 *refill,
427 u16 *max, u8 *bwg_id, u8 *prio_type) 427 u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
428{ 428{
429 ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba); 429 ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
430 ixgbe_dcb_config_82599(hw); 430 ixgbe_dcb_config_82599(hw);
431 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type); 431 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
432 prio_type, prio_tc);
432 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 433 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
433 bwg_id, prio_type); 434 bwg_id, prio_type);
434 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 435 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
435 bwg_id, prio_type); 436 bwg_id, prio_type, prio_tc);
436 ixgbe_dcb_config_pfc_82599(hw, pfc_en); 437 ixgbe_dcb_config_pfc_82599(hw, pfc_en);
437 ixgbe_dcb_config_tc_stats_82599(hw); 438 ixgbe_dcb_config_tc_stats_82599(hw);
438 439
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.h b/drivers/net/ixgbe/ixgbe_dcb_82599.h
index 0b39ab4ffc70..148fd8b477a9 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.h
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.h
@@ -109,7 +109,8 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
109 u16 *refill, 109 u16 *refill,
110 u16 *max, 110 u16 *max,
111 u8 *bwg_id, 111 u8 *bwg_id,
112 u8 *prio_type); 112 u8 *prio_type,
113 u8 *prio_tc);
113 114
114s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 115s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
115 u16 *refill, 116 u16 *refill,
@@ -121,10 +122,12 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
121 u16 *refill, 122 u16 *refill,
122 u16 *max, 123 u16 *max,
123 u8 *bwg_id, 124 u8 *bwg_id,
124 u8 *prio_type); 125 u8 *prio_type,
126 u8 *prio_tc);
125 127
126s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, 128s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
127 u8 rx_pba, u8 pfc_en, u16 *refill, 129 u8 rx_pba, u8 pfc_en, u16 *refill,
128 u16 *max, u8 *bwg_id, u8 *prio_type); 130 u16 *max, u8 *bwg_id, u8 *prio_type,
131 u8 *prio_tc);
129 132
130#endif /* _DCB_82599_CONFIG_H */ 133#endif /* _DCB_82599_CONFIG_H */
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index d7f0024014b1..fec4c724c37a 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -129,7 +129,6 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
129 netdev->netdev_ops->ndo_stop(netdev); 129 netdev->netdev_ops->ndo_stop(netdev);
130 ixgbe_clear_interrupt_scheme(adapter); 130 ixgbe_clear_interrupt_scheme(adapter);
131 131
132 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
133 switch (adapter->hw.mac.type) { 132 switch (adapter->hw.mac.type) {
134 case ixgbe_mac_82598EB: 133 case ixgbe_mac_82598EB:
135 adapter->last_lfc_mode = adapter->hw.fc.current_mode; 134 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
@@ -145,6 +144,9 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
145 } 144 }
146 145
147 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 146 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
147 if (!netdev_get_num_tc(netdev))
148 ixgbe_setup_tc(netdev, MAX_TRAFFIC_CLASS);
149
148 ixgbe_init_interrupt_scheme(adapter); 150 ixgbe_init_interrupt_scheme(adapter);
149 if (netif_running(netdev)) 151 if (netif_running(netdev))
150 netdev->netdev_ops->ndo_open(netdev); 152 netdev->netdev_ops->ndo_open(netdev);
@@ -159,7 +161,6 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
159 adapter->temp_dcb_cfg.pfc_mode_enable = false; 161 adapter->temp_dcb_cfg.pfc_mode_enable = false;
160 adapter->dcb_cfg.pfc_mode_enable = false; 162 adapter->dcb_cfg.pfc_mode_enable = false;
161 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 163 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
162 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
163 switch (adapter->hw.mac.type) { 164 switch (adapter->hw.mac.type) {
164 case ixgbe_mac_82599EB: 165 case ixgbe_mac_82599EB:
165 case ixgbe_mac_X540: 166 case ixgbe_mac_X540:
@@ -169,6 +170,8 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
169 break; 170 break;
170 } 171 }
171 172
173 ixgbe_setup_tc(netdev, 0);
174
172 ixgbe_init_interrupt_scheme(adapter); 175 ixgbe_init_interrupt_scheme(adapter);
173 if (netif_running(netdev)) 176 if (netif_running(netdev))
174 netdev->netdev_ops->ndo_open(netdev); 177 netdev->netdev_ops->ndo_open(netdev);
@@ -346,11 +349,12 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
346 struct ixgbe_adapter *adapter = netdev_priv(netdev); 349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
347 int ret; 350 int ret;
348 351
349 if (!adapter->dcb_set_bitmap) 352 if (!adapter->dcb_set_bitmap ||
353 !(adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE))
350 return DCB_NO_HW_CHG; 354 return DCB_NO_HW_CHG;
351 355
352 ret = ixgbe_copy_dcb_cfg(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 356 ret = ixgbe_copy_dcb_cfg(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
353 adapter->ring_feature[RING_F_DCB].indices); 357 MAX_TRAFFIC_CLASS);
354 358
355 if (ret) 359 if (ret)
356 return DCB_NO_HW_CHG; 360 return DCB_NO_HW_CHG;
@@ -412,6 +416,8 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
412 if (adapter->dcb_set_bitmap & (BIT_PG_TX|BIT_PG_RX)) { 416 if (adapter->dcb_set_bitmap & (BIT_PG_TX|BIT_PG_RX)) {
413 u16 refill[MAX_TRAFFIC_CLASS], max[MAX_TRAFFIC_CLASS]; 417 u16 refill[MAX_TRAFFIC_CLASS], max[MAX_TRAFFIC_CLASS];
414 u8 bwg_id[MAX_TRAFFIC_CLASS], prio_type[MAX_TRAFFIC_CLASS]; 418 u8 bwg_id[MAX_TRAFFIC_CLASS], prio_type[MAX_TRAFFIC_CLASS];
419 /* Priority to TC mapping in CEE case default to 1:1 */
420 u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7};
415 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 421 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
416 422
417#ifdef CONFIG_FCOE 423#ifdef CONFIG_FCOE
@@ -433,7 +439,7 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
433 DCB_TX_CONFIG, prio_type); 439 DCB_TX_CONFIG, prio_type);
434 440
435 ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max, 441 ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max,
436 bwg_id, prio_type); 442 bwg_id, prio_type, prio_tc);
437 } 443 }
438 444
439 if (adapter->dcb_cfg.pfc_mode_enable) 445 if (adapter->dcb_cfg.pfc_mode_enable)
@@ -448,40 +454,38 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
448static u8 ixgbe_dcbnl_getcap(struct net_device *netdev, int capid, u8 *cap) 454static u8 ixgbe_dcbnl_getcap(struct net_device *netdev, int capid, u8 *cap)
449{ 455{
450 struct ixgbe_adapter *adapter = netdev_priv(netdev); 456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
451 u8 rval = 0;
452 457
453 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 458 switch (capid) {
454 switch (capid) { 459 case DCB_CAP_ATTR_PG:
455 case DCB_CAP_ATTR_PG: 460 *cap = true;
456 *cap = true; 461 break;
457 break; 462 case DCB_CAP_ATTR_PFC:
458 case DCB_CAP_ATTR_PFC: 463 *cap = true;
459 *cap = true; 464 break;
460 break; 465 case DCB_CAP_ATTR_UP2TC:
461 case DCB_CAP_ATTR_UP2TC: 466 *cap = false;
462 *cap = false; 467 break;
463 break; 468 case DCB_CAP_ATTR_PG_TCS:
464 case DCB_CAP_ATTR_PG_TCS: 469 *cap = 0x80;
465 *cap = 0x80; 470 break;
466 break; 471 case DCB_CAP_ATTR_PFC_TCS:
467 case DCB_CAP_ATTR_PFC_TCS: 472 *cap = 0x80;
468 *cap = 0x80; 473 break;
469 break; 474 case DCB_CAP_ATTR_GSP:
470 case DCB_CAP_ATTR_GSP: 475 *cap = true;
471 *cap = true; 476 break;
472 break; 477 case DCB_CAP_ATTR_BCN:
473 case DCB_CAP_ATTR_BCN: 478 *cap = false;
474 *cap = false; 479 break;
475 break; 480 case DCB_CAP_ATTR_DCBX:
476 default: 481 *cap = adapter->dcbx_cap;
477 rval = -EINVAL; 482 break;
478 break; 483 default:
479 } 484 *cap = false;
480 } else { 485 break;
481 rval = -EINVAL;
482 } 486 }
483 487
484 return rval; 488 return 0;
485} 489}
486 490
487static u8 ixgbe_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num) 491static u8 ixgbe_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num)
@@ -542,21 +546,16 @@ static void ixgbe_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
542 */ 546 */
543static u8 ixgbe_dcbnl_getapp(struct net_device *netdev, u8 idtype, u16 id) 547static u8 ixgbe_dcbnl_getapp(struct net_device *netdev, u8 idtype, u16 id)
544{ 548{
545 u8 rval = 0; 549 struct ixgbe_adapter *adapter = netdev_priv(netdev);
550 struct dcb_app app = {
551 .selector = idtype,
552 .protocol = id,
553 };
546 554
547 switch (idtype) { 555 if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE))
548 case DCB_APP_IDTYPE_ETHTYPE: 556 return 0;
549#ifdef IXGBE_FCOE 557
550 if (id == ETH_P_FCOE) 558 return dcb_getapp(netdev, &app);
551 rval = ixgbe_fcoe_getapp(netdev_priv(netdev));
552#endif
553 break;
554 case DCB_APP_IDTYPE_PORTNUM:
555 break;
556 default:
557 break;
558 }
559 return rval;
560} 559}
561 560
562/** 561/**
@@ -571,14 +570,24 @@ static u8 ixgbe_dcbnl_getapp(struct net_device *netdev, u8 idtype, u16 id)
571static u8 ixgbe_dcbnl_setapp(struct net_device *netdev, 570static u8 ixgbe_dcbnl_setapp(struct net_device *netdev,
572 u8 idtype, u16 id, u8 up) 571 u8 idtype, u16 id, u8 up)
573{ 572{
573 struct ixgbe_adapter *adapter = netdev_priv(netdev);
574 u8 rval = 1; 574 u8 rval = 1;
575 struct dcb_app app = {
576 .selector = idtype,
577 .protocol = id,
578 .priority = up
579 };
580
581 if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE))
582 return rval;
583
584 rval = dcb_setapp(netdev, &app);
575 585
576 switch (idtype) { 586 switch (idtype) {
577 case DCB_APP_IDTYPE_ETHTYPE: 587 case DCB_APP_IDTYPE_ETHTYPE:
578#ifdef IXGBE_FCOE 588#ifdef IXGBE_FCOE
579 if (id == ETH_P_FCOE) { 589 if (id == ETH_P_FCOE) {
580 u8 old_tc; 590 u8 old_tc;
581 struct ixgbe_adapter *adapter = netdev_priv(netdev);
582 591
583 /* Get current programmed tc */ 592 /* Get current programmed tc */
584 old_tc = adapter->fcoe.tc; 593 old_tc = adapter->fcoe.tc;
@@ -635,11 +644,16 @@ static int ixgbe_dcbnl_ieee_setets(struct net_device *dev,
635{ 644{
636 struct ixgbe_adapter *adapter = netdev_priv(dev); 645 struct ixgbe_adapter *adapter = netdev_priv(dev);
637 __u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS]; 646 __u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS];
647 __u8 prio_type[IEEE_8021QAZ_MAX_TCS];
638 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 648 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
639 int err; 649 int i, err;
650 __u64 *p = (__u64 *) ets->prio_tc;
640 /* naively give each TC a bwg to map onto CEE hardware */ 651 /* naively give each TC a bwg to map onto CEE hardware */
641 __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7}; 652 __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7};
642 653
654 if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))
655 return -EINVAL;
656
643 if (!adapter->ixgbe_ieee_ets) { 657 if (!adapter->ixgbe_ieee_ets) {
644 adapter->ixgbe_ieee_ets = kmalloc(sizeof(struct ieee_ets), 658 adapter->ixgbe_ieee_ets = kmalloc(sizeof(struct ieee_ets),
645 GFP_KERNEL); 659 GFP_KERNEL);
@@ -647,12 +661,35 @@ static int ixgbe_dcbnl_ieee_setets(struct net_device *dev,
647 return -ENOMEM; 661 return -ENOMEM;
648 } 662 }
649 663
650
651 memcpy(adapter->ixgbe_ieee_ets, ets, sizeof(*adapter->ixgbe_ieee_ets)); 664 memcpy(adapter->ixgbe_ieee_ets, ets, sizeof(*adapter->ixgbe_ieee_ets));
652 665
666 /* Map TSA onto CEE prio type */
667 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
668 switch (ets->tc_tsa[i]) {
669 case IEEE_8021QAZ_TSA_STRICT:
670 prio_type[i] = 2;
671 break;
672 case IEEE_8021QAZ_TSA_ETS:
673 prio_type[i] = 0;
674 break;
675 default:
676 /* Hardware only supports priority strict or
677 * ETS transmission selection algorithms if
678 * we receive some other value from dcbnl
679 * throw an error
680 */
681 return -EINVAL;
682 }
683 }
684
685 if (*p)
686 ixgbe_dcbnl_set_state(dev, 1);
687 else
688 ixgbe_dcbnl_set_state(dev, 0);
689
653 ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame); 690 ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame);
654 err = ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max, 691 err = ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max,
655 bwg_id, ets->tc_tsa); 692 bwg_id, prio_type, ets->prio_tc);
656 return err; 693 return err;
657} 694}
658 695
@@ -686,6 +723,9 @@ static int ixgbe_dcbnl_ieee_setpfc(struct net_device *dev,
686 struct ixgbe_adapter *adapter = netdev_priv(dev); 723 struct ixgbe_adapter *adapter = netdev_priv(dev);
687 int err; 724 int err;
688 725
726 if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))
727 return -EINVAL;
728
689 if (!adapter->ixgbe_ieee_pfc) { 729 if (!adapter->ixgbe_ieee_pfc) {
690 adapter->ixgbe_ieee_pfc = kmalloc(sizeof(struct ieee_pfc), 730 adapter->ixgbe_ieee_pfc = kmalloc(sizeof(struct ieee_pfc),
691 GFP_KERNEL); 731 GFP_KERNEL);
@@ -698,11 +738,86 @@ static int ixgbe_dcbnl_ieee_setpfc(struct net_device *dev,
698 return err; 738 return err;
699} 739}
700 740
741static int ixgbe_dcbnl_ieee_setapp(struct net_device *dev,
742 struct dcb_app *app)
743{
744 struct ixgbe_adapter *adapter = netdev_priv(dev);
745
746 if (!(adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))
747 return -EINVAL;
748#ifdef IXGBE_FCOE
749 if (app->selector == 1 && app->protocol == ETH_P_FCOE) {
750 if (adapter->fcoe.tc == app->priority)
751 goto setapp;
752
753 /* In IEEE mode map up to tc 1:1 */
754 adapter->fcoe.tc = app->priority;
755 adapter->fcoe.up = app->priority;
756
757 /* Force hardware reset required to push FCoE
758 * setup on {tx|rx}_rings
759 */
760 adapter->dcb_set_bitmap |= BIT_APP_UPCHG;
761 ixgbe_dcbnl_set_all(dev);
762 }
763
764setapp:
765#endif
766 dcb_setapp(dev, app);
767 return 0;
768}
769
770static u8 ixgbe_dcbnl_getdcbx(struct net_device *dev)
771{
772 struct ixgbe_adapter *adapter = netdev_priv(dev);
773 return adapter->dcbx_cap;
774}
775
776static u8 ixgbe_dcbnl_setdcbx(struct net_device *dev, u8 mode)
777{
778 struct ixgbe_adapter *adapter = netdev_priv(dev);
779 struct ieee_ets ets = {0};
780 struct ieee_pfc pfc = {0};
781
782 /* no support for LLD_MANAGED modes or CEE+IEEE */
783 if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
784 ((mode & DCB_CAP_DCBX_VER_IEEE) && (mode & DCB_CAP_DCBX_VER_CEE)) ||
785 !(mode & DCB_CAP_DCBX_HOST))
786 return 1;
787
788 if (mode == adapter->dcbx_cap)
789 return 0;
790
791 adapter->dcbx_cap = mode;
792
793 /* ETS and PFC defaults */
794 ets.ets_cap = 8;
795 pfc.pfc_cap = 8;
796
797 if (mode & DCB_CAP_DCBX_VER_IEEE) {
798 ixgbe_dcbnl_ieee_setets(dev, &ets);
799 ixgbe_dcbnl_ieee_setpfc(dev, &pfc);
800 } else if (mode & DCB_CAP_DCBX_VER_CEE) {
801 adapter->dcb_set_bitmap |= (BIT_PFC & BIT_PG_TX & BIT_PG_RX);
802 ixgbe_dcbnl_set_all(dev);
803 } else {
804 /* Drop into single TC mode strict priority as this
805 * indicates CEE and IEEE versions are disabled
806 */
807 ixgbe_dcbnl_ieee_setets(dev, &ets);
808 ixgbe_dcbnl_ieee_setpfc(dev, &pfc);
809 ixgbe_dcbnl_set_state(dev, 0);
810 }
811
812 return 0;
813}
814
701const struct dcbnl_rtnl_ops dcbnl_ops = { 815const struct dcbnl_rtnl_ops dcbnl_ops = {
702 .ieee_getets = ixgbe_dcbnl_ieee_getets, 816 .ieee_getets = ixgbe_dcbnl_ieee_getets,
703 .ieee_setets = ixgbe_dcbnl_ieee_setets, 817 .ieee_setets = ixgbe_dcbnl_ieee_setets,
704 .ieee_getpfc = ixgbe_dcbnl_ieee_getpfc, 818 .ieee_getpfc = ixgbe_dcbnl_ieee_getpfc,
705 .ieee_setpfc = ixgbe_dcbnl_ieee_setpfc, 819 .ieee_setpfc = ixgbe_dcbnl_ieee_setpfc,
820 .ieee_setapp = ixgbe_dcbnl_ieee_setapp,
706 .getstate = ixgbe_dcbnl_get_state, 821 .getstate = ixgbe_dcbnl_get_state,
707 .setstate = ixgbe_dcbnl_set_state, 822 .setstate = ixgbe_dcbnl_set_state,
708 .getpermhwaddr = ixgbe_dcbnl_get_perm_hw_addr, 823 .getpermhwaddr = ixgbe_dcbnl_get_perm_hw_addr,
@@ -724,5 +839,6 @@ const struct dcbnl_rtnl_ops dcbnl_ops = {
724 .setpfcstate = ixgbe_dcbnl_setpfcstate, 839 .setpfcstate = ixgbe_dcbnl_setpfcstate,
725 .getapp = ixgbe_dcbnl_getapp, 840 .getapp = ixgbe_dcbnl_getapp,
726 .setapp = ixgbe_dcbnl_setapp, 841 .setapp = ixgbe_dcbnl_setapp,
842 .getdcbx = ixgbe_dcbnl_getdcbx,
843 .setdcbx = ixgbe_dcbnl_setdcbx,
727}; 844};
728
diff --git a/drivers/net/ixgbe/ixgbe_fcoe.c b/drivers/net/ixgbe/ixgbe_fcoe.c
index 00af15a9cdc6..dba7d77588ef 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ixgbe/ixgbe_fcoe.c
@@ -813,21 +813,6 @@ out_disable:
813 813
814#ifdef CONFIG_IXGBE_DCB 814#ifdef CONFIG_IXGBE_DCB
815/** 815/**
816 * ixgbe_fcoe_getapp - retrieves current user priority bitmap for FCoE
817 * @adapter : ixgbe adapter
818 *
819 * Finds out the corresponding user priority bitmap from the current
820 * traffic class that FCoE belongs to. Returns 0 as the invalid user
821 * priority bitmap to indicate an error.
822 *
823 * Returns : 802.1p user priority bitmap for FCoE
824 */
825u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter)
826{
827 return 1 << adapter->fcoe.up;
828}
829
830/**
831 * ixgbe_fcoe_setapp - sets the user priority bitmap for FCoE 816 * ixgbe_fcoe_setapp - sets the user priority bitmap for FCoE
832 * @adapter : ixgbe adapter 817 * @adapter : ixgbe adapter
833 * @up : 802.1p user priority bitmap 818 * @up : 802.1p user priority bitmap
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 5998dc94dd5c..f17e4a7ee731 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -652,7 +652,7 @@ void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
652static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx) 652static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
653{ 653{
654 int tc = -1; 654 int tc = -1;
655 int dcb_i = adapter->ring_feature[RING_F_DCB].indices; 655 int dcb_i = netdev_get_num_tc(adapter->netdev);
656 656
657 /* if DCB is not enabled the queues have no TC */ 657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
@@ -2892,17 +2892,20 @@ static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2892 ); 2892 );
2893 2893
2894 switch (mask) { 2894 switch (mask) {
2895#ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2897 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2898 break;
2899 case (IXGBE_FLAG_DCB_ENABLED):
2900 mrqc = IXGBE_MRQC_RT8TCEN;
2901 break;
2902#endif /* CONFIG_IXGBE_DCB */
2895 case (IXGBE_FLAG_RSS_ENABLED): 2903 case (IXGBE_FLAG_RSS_ENABLED):
2896 mrqc = IXGBE_MRQC_RSSEN; 2904 mrqc = IXGBE_MRQC_RSSEN;
2897 break; 2905 break;
2898 case (IXGBE_FLAG_SRIOV_ENABLED): 2906 case (IXGBE_FLAG_SRIOV_ENABLED):
2899 mrqc = IXGBE_MRQC_VMDQEN; 2907 mrqc = IXGBE_MRQC_VMDQEN;
2900 break; 2908 break;
2901#ifdef CONFIG_IXGBE_DCB
2902 case (IXGBE_FLAG_DCB_ENABLED):
2903 mrqc = IXGBE_MRQC_RT8TCEN;
2904 break;
2905#endif /* CONFIG_IXGBE_DCB */
2906 default: 2909 default:
2907 break; 2910 break;
2908 } 2911 }
@@ -3655,15 +3658,6 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3655 if (hw->mac.type == ixgbe_mac_82598EB) 3658 if (hw->mac.type == ixgbe_mac_82598EB)
3656 netif_set_gso_max_size(adapter->netdev, 32768); 3659 netif_set_gso_max_size(adapter->netdev, 32768);
3657 3660
3658#ifdef CONFIG_FCOE
3659 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3660 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3661#endif
3662
3663 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3664 DCB_TX_CONFIG);
3665 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3666 DCB_RX_CONFIG);
3667 3661
3668 /* Enable VLAN tag insert/strip */ 3662 /* Enable VLAN tag insert/strip */
3669 adapter->netdev->features |= NETIF_F_HW_VLAN_RX; 3663 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
@@ -3671,7 +3665,43 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3671 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); 3665 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3672 3666
3673 /* reconfigure the hardware */ 3667 /* reconfigure the hardware */
3674 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 3668 if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3669#ifdef CONFIG_FCOE
3670 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3671 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3672#endif
3673 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3674 DCB_TX_CONFIG);
3675 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3676 DCB_RX_CONFIG);
3677 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3678 } else {
3679 struct net_device *dev = adapter->netdev;
3680
3681 if (adapter->ixgbe_ieee_ets)
3682 dev->dcbnl_ops->ieee_setets(dev,
3683 adapter->ixgbe_ieee_ets);
3684 if (adapter->ixgbe_ieee_pfc)
3685 dev->dcbnl_ops->ieee_setpfc(dev,
3686 adapter->ixgbe_ieee_pfc);
3687 }
3688
3689 /* Enable RSS Hash per TC */
3690 if (hw->mac.type != ixgbe_mac_82598EB) {
3691 int i;
3692 u32 reg = 0;
3693
3694 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3695 u8 msb = 0;
3696 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3697
3698 while (cnt >>= 1)
3699 msb++;
3700
3701 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3702 }
3703 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3704 }
3675} 3705}
3676 3706
3677#endif 3707#endif
@@ -4258,24 +4288,6 @@ static void ixgbe_reset_task(struct work_struct *work)
4258 ixgbe_reinit_locked(adapter); 4288 ixgbe_reinit_locked(adapter);
4259} 4289}
4260 4290
4261#ifdef CONFIG_IXGBE_DCB
4262static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4263{
4264 bool ret = false;
4265 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4266
4267 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4268 return ret;
4269
4270 f->mask = 0x7 << 3;
4271 adapter->num_rx_queues = f->indices;
4272 adapter->num_tx_queues = f->indices;
4273 ret = true;
4274
4275 return ret;
4276}
4277#endif
4278
4279/** 4291/**
4280 * ixgbe_set_rss_queues: Allocate queues for RSS 4292 * ixgbe_set_rss_queues: Allocate queues for RSS
4281 * @adapter: board private structure to initialize 4293 * @adapter: board private structure to initialize
@@ -4346,19 +4358,26 @@ static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4346 **/ 4358 **/
4347static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) 4359static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4348{ 4360{
4349 bool ret = false;
4350 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; 4361 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4351 4362
4352 f->indices = min((int)num_online_cpus(), f->indices); 4363 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4353 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 4364 return false;
4354 adapter->num_rx_queues = 1; 4365
4355 adapter->num_tx_queues = 1; 4366 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4356#ifdef CONFIG_IXGBE_DCB 4367#ifdef CONFIG_IXGBE_DCB
4357 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 4368 int tc;
4358 e_info(probe, "FCoE enabled with DCB\n"); 4369 struct net_device *dev = adapter->netdev;
4359 ixgbe_set_dcb_queues(adapter); 4370
4360 } 4371 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4372 f->indices = dev->tc_to_txq[tc].count;
4373 f->mask = dev->tc_to_txq[tc].offset;
4361#endif 4374#endif
4375 } else {
4376 f->indices = min((int)num_online_cpus(), f->indices);
4377
4378 adapter->num_rx_queues = 1;
4379 adapter->num_tx_queues = 1;
4380
4362 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { 4381 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4363 e_info(probe, "FCoE enabled with RSS\n"); 4382 e_info(probe, "FCoE enabled with RSS\n");
4364 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || 4383 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
@@ -4371,14 +4390,45 @@ static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4371 f->mask = adapter->num_rx_queues; 4390 f->mask = adapter->num_rx_queues;
4372 adapter->num_rx_queues += f->indices; 4391 adapter->num_rx_queues += f->indices;
4373 adapter->num_tx_queues += f->indices; 4392 adapter->num_tx_queues += f->indices;
4393 }
4374 4394
4375 ret = true; 4395 return true;
4396}
4397#endif /* IXGBE_FCOE */
4398
4399#ifdef CONFIG_IXGBE_DCB
4400static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4401{
4402 bool ret = false;
4403 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4404 int i, q;
4405
4406 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4407 return ret;
4408
4409 f->indices = 0;
4410 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4411 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4412 f->indices += q;
4376 } 4413 }
4377 4414
4415 f->mask = 0x7 << 3;
4416 adapter->num_rx_queues = f->indices;
4417 adapter->num_tx_queues = f->indices;
4418 ret = true;
4419
4420#ifdef IXGBE_FCOE
4421 /* FCoE enabled queues require special configuration done through
4422 * configure_fcoe() and others. Here we map FCoE indices onto the
4423 * DCB queue pairs allowing FCoE to own configuration later.
4424 */
4425 ixgbe_set_fcoe_queues(adapter);
4426#endif
4427
4378 return ret; 4428 return ret;
4379} 4429}
4430#endif
4380 4431
4381#endif /* IXGBE_FCOE */
4382/** 4432/**
4383 * ixgbe_set_sriov_queues: Allocate queues for IOV use 4433 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4384 * @adapter: board private structure to initialize 4434 * @adapter: board private structure to initialize
@@ -4414,16 +4464,16 @@ static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4414 if (ixgbe_set_sriov_queues(adapter)) 4464 if (ixgbe_set_sriov_queues(adapter))
4415 goto done; 4465 goto done;
4416 4466
4417#ifdef IXGBE_FCOE
4418 if (ixgbe_set_fcoe_queues(adapter))
4419 goto done;
4420
4421#endif /* IXGBE_FCOE */
4422#ifdef CONFIG_IXGBE_DCB 4467#ifdef CONFIG_IXGBE_DCB
4423 if (ixgbe_set_dcb_queues(adapter)) 4468 if (ixgbe_set_dcb_queues(adapter))
4424 goto done; 4469 goto done;
4425 4470
4426#endif 4471#endif
4472#ifdef IXGBE_FCOE
4473 if (ixgbe_set_fcoe_queues(adapter))
4474 goto done;
4475
4476#endif /* IXGBE_FCOE */
4427 if (ixgbe_set_fdir_queues(adapter)) 4477 if (ixgbe_set_fdir_queues(adapter))
4428 goto done; 4478 goto done;
4429 4479
@@ -4515,6 +4565,110 @@ static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4515} 4565}
4516 4566
4517#ifdef CONFIG_IXGBE_DCB 4567#ifdef CONFIG_IXGBE_DCB
4568
4569/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4570void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4571 unsigned int *tx, unsigned int *rx)
4572{
4573 struct net_device *dev = adapter->netdev;
4574 struct ixgbe_hw *hw = &adapter->hw;
4575 u8 num_tcs = netdev_get_num_tc(dev);
4576
4577 *tx = 0;
4578 *rx = 0;
4579
4580 switch (hw->mac.type) {
4581 case ixgbe_mac_82598EB:
4582 *tx = tc << 3;
4583 *rx = tc << 2;
4584 break;
4585 case ixgbe_mac_82599EB:
4586 case ixgbe_mac_X540:
4587 if (num_tcs == 8) {
4588 if (tc < 3) {
4589 *tx = tc << 5;
4590 *rx = tc << 4;
4591 } else if (tc < 5) {
4592 *tx = ((tc + 2) << 4);
4593 *rx = tc << 4;
4594 } else if (tc < num_tcs) {
4595 *tx = ((tc + 8) << 3);
4596 *rx = tc << 4;
4597 }
4598 } else if (num_tcs == 4) {
4599 *rx = tc << 5;
4600 switch (tc) {
4601 case 0:
4602 *tx = 0;
4603 break;
4604 case 1:
4605 *tx = 64;
4606 break;
4607 case 2:
4608 *tx = 96;
4609 break;
4610 case 3:
4611 *tx = 112;
4612 break;
4613 default:
4614 break;
4615 }
4616 }
4617 break;
4618 default:
4619 break;
4620 }
4621}
4622
4623#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4624
4625/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4626 * classes.
4627 *
4628 * @netdev: net device to configure
4629 * @tc: number of traffic classes to enable
4630 */
4631int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4632{
4633 int i;
4634 unsigned int q, offset = 0;
4635
4636 if (!tc) {
4637 netdev_reset_tc(dev);
4638 } else {
4639 struct ixgbe_adapter *adapter = netdev_priv(dev);
4640
4641 /* Hardware supports up to 8 traffic classes */
4642 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4643 return -EINVAL;
4644
4645 /* Partition Tx queues evenly amongst traffic classes */
4646 for (i = 0; i < tc; i++) {
4647 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4648 netdev_set_prio_tc_map(dev, i, i);
4649 netdev_set_tc_queue(dev, i, q, offset);
4650 offset += q;
4651 }
4652
4653 /* This enables multiple traffic class support in the hardware
4654 * which defaults to strict priority transmission by default.
4655 * If traffic classes are already enabled perhaps through DCB
4656 * code path then existing configuration will be used.
4657 */
4658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4659 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4660 struct ieee_ets ets = {
4661 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4662 };
4663 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4664
4665 dev->dcbnl_ops->setdcbx(dev, mode);
4666 dev->dcbnl_ops->ieee_setets(dev, &ets);
4667 }
4668 }
4669 return 0;
4670}
4671
4518/** 4672/**
4519 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB 4673 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4520 * @adapter: board private structure to initialize 4674 * @adapter: board private structure to initialize
@@ -4524,72 +4678,27 @@ static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4524 **/ 4678 **/
4525static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 4679static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4526{ 4680{
4527 int i; 4681 struct net_device *dev = adapter->netdev;
4528 bool ret = false; 4682 int i, j, k;
4529 int dcb_i = adapter->ring_feature[RING_F_DCB].indices; 4683 u8 num_tcs = netdev_get_num_tc(dev);
4530 4684
4531 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 4685 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4532 return false; 4686 return false;
4533 4687
4534 /* the number of queues is assumed to be symmetric */ 4688 for (i = 0, k = 0; i < num_tcs; i++) {
4535 switch (adapter->hw.mac.type) { 4689 unsigned int tx_s, rx_s;
4536 case ixgbe_mac_82598EB: 4690 u16 count = dev->tc_to_txq[i].count;
4537 for (i = 0; i < dcb_i; i++) { 4691
4538 adapter->rx_ring[i]->reg_idx = i << 3; 4692 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4539 adapter->tx_ring[i]->reg_idx = i << 2; 4693 for (j = 0; j < count; j++, k++) {
4540 } 4694 adapter->tx_ring[k]->reg_idx = tx_s + j;
4541 ret = true; 4695 adapter->rx_ring[k]->reg_idx = rx_s + j;
4542 break; 4696 adapter->tx_ring[k]->dcb_tc = i;
4543 case ixgbe_mac_82599EB: 4697 adapter->rx_ring[k]->dcb_tc = i;
4544 case ixgbe_mac_X540:
4545 if (dcb_i == 8) {
4546 /*
4547 * Tx TC0 starts at: descriptor queue 0
4548 * Tx TC1 starts at: descriptor queue 32
4549 * Tx TC2 starts at: descriptor queue 64
4550 * Tx TC3 starts at: descriptor queue 80
4551 * Tx TC4 starts at: descriptor queue 96
4552 * Tx TC5 starts at: descriptor queue 104
4553 * Tx TC6 starts at: descriptor queue 112
4554 * Tx TC7 starts at: descriptor queue 120
4555 *
4556 * Rx TC0-TC7 are offset by 16 queues each
4557 */
4558 for (i = 0; i < 3; i++) {
4559 adapter->tx_ring[i]->reg_idx = i << 5;
4560 adapter->rx_ring[i]->reg_idx = i << 4;
4561 }
4562 for ( ; i < 5; i++) {
4563 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4564 adapter->rx_ring[i]->reg_idx = i << 4;
4565 }
4566 for ( ; i < dcb_i; i++) {
4567 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4568 adapter->rx_ring[i]->reg_idx = i << 4;
4569 }
4570 ret = true;
4571 } else if (dcb_i == 4) {
4572 /*
4573 * Tx TC0 starts at: descriptor queue 0
4574 * Tx TC1 starts at: descriptor queue 64
4575 * Tx TC2 starts at: descriptor queue 96
4576 * Tx TC3 starts at: descriptor queue 112
4577 *
4578 * Rx TC0-TC3 are offset by 32 queues each
4579 */
4580 adapter->tx_ring[0]->reg_idx = 0;
4581 adapter->tx_ring[1]->reg_idx = 64;
4582 adapter->tx_ring[2]->reg_idx = 96;
4583 adapter->tx_ring[3]->reg_idx = 112;
4584 for (i = 0 ; i < dcb_i; i++)
4585 adapter->rx_ring[i]->reg_idx = i << 5;
4586 ret = true;
4587 } 4698 }
4588 break;
4589 default:
4590 break;
4591 } 4699 }
4592 return ret; 4700
4701 return true;
4593} 4702}
4594#endif 4703#endif
4595 4704
@@ -4635,33 +4744,6 @@ static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4635 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 4744 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4636 return false; 4745 return false;
4637 4746
4638#ifdef CONFIG_IXGBE_DCB
4639 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4640 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4641
4642 ixgbe_cache_ring_dcb(adapter);
4643 /* find out queues in TC for FCoE */
4644 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4645 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4646 /*
4647 * In 82599, the number of Tx queues for each traffic
4648 * class for both 8-TC and 4-TC modes are:
4649 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4650 * 8 TCs: 32 32 16 16 8 8 8 8
4651 * 4 TCs: 64 64 32 32
4652 * We have max 8 queues for FCoE, where 8 the is
4653 * FCoE redirection table size. If TC for FCoE is
4654 * less than or equal to TC3, we have enough queues
4655 * to add max of 8 queues for FCoE, so we start FCoE
4656 * Tx queue from the next one, i.e., reg_idx + 1.
4657 * If TC for FCoE is above TC3, implying 8 TC mode,
4658 * and we need 8 for FCoE, we have to take all queues
4659 * in that traffic class for FCoE.
4660 */
4661 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4662 fcoe_tx_i--;
4663 }
4664#endif /* CONFIG_IXGBE_DCB */
4665 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { 4747 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4666 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || 4748 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4667 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 4749 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
@@ -4718,16 +4800,16 @@ static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4718 if (ixgbe_cache_ring_sriov(adapter)) 4800 if (ixgbe_cache_ring_sriov(adapter))
4719 return; 4801 return;
4720 4802
4803#ifdef CONFIG_IXGBE_DCB
4804 if (ixgbe_cache_ring_dcb(adapter))
4805 return;
4806#endif
4807
4721#ifdef IXGBE_FCOE 4808#ifdef IXGBE_FCOE
4722 if (ixgbe_cache_ring_fcoe(adapter)) 4809 if (ixgbe_cache_ring_fcoe(adapter))
4723 return; 4810 return;
4724
4725#endif /* IXGBE_FCOE */ 4811#endif /* IXGBE_FCOE */
4726#ifdef CONFIG_IXGBE_DCB
4727 if (ixgbe_cache_ring_dcb(adapter))
4728 return;
4729 4812
4730#endif
4731 if (ixgbe_cache_ring_fdir(adapter)) 4813 if (ixgbe_cache_ring_fdir(adapter))
4732 return; 4814 return;
4733 4815
@@ -5190,8 +5272,9 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5190 adapter->dcb_cfg.rx_pba_cfg = pba_equal; 5272 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5191 adapter->dcb_cfg.pfc_mode_enable = false; 5273 adapter->dcb_cfg.pfc_mode_enable = false;
5192 adapter->dcb_set_bitmap = 0x00; 5274 adapter->dcb_set_bitmap = 0x00;
5275 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5193 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, 5276 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5194 adapter->ring_feature[RING_F_DCB].indices); 5277 MAX_TRAFFIC_CLASS);
5195 5278
5196#endif 5279#endif
5197 5280
@@ -6134,6 +6217,7 @@ static void ixgbe_watchdog_task(struct work_struct *work)
6134 (flow_tx ? "TX" : "None")))); 6217 (flow_tx ? "TX" : "None"))));
6135 6218
6136 netif_carrier_on(netdev); 6219 netif_carrier_on(netdev);
6220 ixgbe_check_vf_rate_limit(adapter);
6137 } else { 6221 } else {
6138 /* Force detection of hung controller */ 6222 /* Force detection of hung controller */
6139 for (i = 0; i < adapter->num_tx_queues; i++) { 6223 for (i = 0; i < adapter->num_tx_queues; i++) {
@@ -6663,18 +6747,12 @@ static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6663 6747
6664 protocol = vlan_get_protocol(skb); 6748 protocol = vlan_get_protocol(skb);
6665 6749
6666 if ((protocol == htons(ETH_P_FCOE)) || 6750 if (((protocol == htons(ETH_P_FCOE)) ||
6667 (protocol == htons(ETH_P_FIP))) { 6751 (protocol == htons(ETH_P_FIP))) &&
6668 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 6752 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6669 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); 6753 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6670 txq += adapter->ring_feature[RING_F_FCOE].mask; 6754 txq += adapter->ring_feature[RING_F_FCOE].mask;
6671 return txq; 6755 return txq;
6672#ifdef CONFIG_IXGBE_DCB
6673 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6674 txq = adapter->fcoe.up;
6675 return txq;
6676#endif
6677 }
6678 } 6756 }
6679#endif 6757#endif
6680 6758
@@ -6684,15 +6762,6 @@ static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6684 return txq; 6762 return txq;
6685 } 6763 }
6686 6764
6687 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6688 if (skb->priority == TC_PRIO_CONTROL)
6689 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6690 else
6691 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6692 >> 13;
6693 return txq;
6694 }
6695
6696 return skb_tx_hash(dev, skb); 6765 return skb_tx_hash(dev, skb);
6697} 6766}
6698 6767
@@ -6714,13 +6783,13 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6714 tx_flags |= vlan_tx_tag_get(skb); 6783 tx_flags |= vlan_tx_tag_get(skb);
6715 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 6784 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6716 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 6785 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6717 tx_flags |= ((skb->queue_mapping & 0x7) << 13); 6786 tx_flags |= tx_ring->dcb_tc << 13;
6718 } 6787 }
6719 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; 6788 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6720 tx_flags |= IXGBE_TX_FLAGS_VLAN; 6789 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6721 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED && 6790 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6722 skb->priority != TC_PRIO_CONTROL) { 6791 skb->priority != TC_PRIO_CONTROL) {
6723 tx_flags |= ((skb->queue_mapping & 0x7) << 13); 6792 tx_flags |= tx_ring->dcb_tc << 13;
6724 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; 6793 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6725 tx_flags |= IXGBE_TX_FLAGS_VLAN; 6794 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6726 } 6795 }
@@ -6729,20 +6798,8 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6729 /* for FCoE with DCB, we force the priority to what 6798 /* for FCoE with DCB, we force the priority to what
6730 * was specified by the switch */ 6799 * was specified by the switch */
6731 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED && 6800 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6732 (protocol == htons(ETH_P_FCOE) || 6801 (protocol == htons(ETH_P_FCOE)))
6733 protocol == htons(ETH_P_FIP))) { 6802 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6734#ifdef CONFIG_IXGBE_DCB
6735 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6736 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6737 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6738 tx_flags |= ((adapter->fcoe.up << 13)
6739 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6740 }
6741#endif
6742 /* flag for FCoE offloads */
6743 if (protocol == htons(ETH_P_FCOE))
6744 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6745 }
6746#endif 6803#endif
6747 6804
6748 /* four things can cause us to need a context descriptor */ 6805 /* four things can cause us to need a context descriptor */
@@ -7015,6 +7072,9 @@ static const struct net_device_ops ixgbe_netdev_ops = {
7015 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, 7072 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7016 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 7073 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7017 .ndo_get_stats64 = ixgbe_get_stats64, 7074 .ndo_get_stats64 = ixgbe_get_stats64,
7075#ifdef CONFIG_IXGBE_DCB
7076 .ndo_setup_tc = ixgbe_setup_tc,
7077#endif
7018#ifdef CONFIG_NET_POLL_CONTROLLER 7078#ifdef CONFIG_NET_POLL_CONTROLLER
7019 .ndo_poll_controller = ixgbe_netpoll, 7079 .ndo_poll_controller = ixgbe_netpoll,
7020#endif 7080#endif
@@ -7156,8 +7216,9 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
7156 else 7216 else
7157 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); 7217 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7158 7218
7219#if defined(CONFIG_DCB)
7159 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); 7220 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7160#ifdef IXGBE_FCOE 7221#elif defined(IXGBE_FCOE)
7161 indices += min_t(unsigned int, num_possible_cpus(), 7222 indices += min_t(unsigned int, num_possible_cpus(),
7162 IXGBE_MAX_FCOE_INDICES); 7223 IXGBE_MAX_FCOE_INDICES);
7163#endif 7224#endif
@@ -7313,8 +7374,6 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
7313 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7374 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7314 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | 7375 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7315 IXGBE_FLAG_DCB_ENABLED); 7376 IXGBE_FLAG_DCB_ENABLED);
7316 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7317 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7318 7377
7319#ifdef CONFIG_IXGBE_DCB 7378#ifdef CONFIG_IXGBE_DCB
7320 netdev->dcbnl_ops = &dcbnl_ops; 7379 netdev->dcbnl_ops = &dcbnl_ops;
diff --git a/drivers/net/ixgbe/ixgbe_mbx.c b/drivers/net/ixgbe/ixgbe_mbx.c
index c7ed82eb2539..1ff0eefcfd0a 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.c
+++ b/drivers/net/ixgbe/ixgbe_mbx.c
@@ -154,9 +154,6 @@ static s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id)
154 udelay(mbx->usec_delay); 154 udelay(mbx->usec_delay);
155 } 155 }
156 156
157 /* if we failed, all future posted messages fail until reset */
158 if (!countdown)
159 mbx->timeout = 0;
160out: 157out:
161 return countdown ? 0 : IXGBE_ERR_MBX; 158 return countdown ? 0 : IXGBE_ERR_MBX;
162} 159}
@@ -183,9 +180,6 @@ static s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id)
183 udelay(mbx->usec_delay); 180 udelay(mbx->usec_delay);
184 } 181 }
185 182
186 /* if we failed, all future posted messages fail until reset */
187 if (!countdown)
188 mbx->timeout = 0;
189out: 183out:
190 return countdown ? 0 : IXGBE_ERR_MBX; 184 return countdown ? 0 : IXGBE_ERR_MBX;
191} 185}
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 9190a8fca427..f72f705f6183 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -402,49 +402,89 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
402 **/ 402 **/
403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
404{ 404{
405 s32 status = IXGBE_NOT_IMPLEMENTED; 405 s32 status = 0;
406 u32 time_out; 406 u32 time_out;
407 u32 max_time_out = 10; 407 u32 max_time_out = 10;
408 u16 autoneg_reg; 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
409 bool autoneg = false;
410 ixgbe_link_speed speed;
409 411
410 /* 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
411 * Set advertisement settings in PHY based on autoneg_advertised 413
412 * settings. If autoneg_advertised = 0, then advertise default values 414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
413 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 415 /* Set or unset auto-negotiation 10G advertisement */
414 * for a 1G. 416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
415 */ 417 MDIO_MMD_AN,
416 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); 418 &autoneg_reg);
417 419
418 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
419 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
420 else 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
421 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
422 423
423 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); 424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
425 MDIO_MMD_AN,
426 autoneg_reg);
427 }
428
429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
430 /* Set or unset auto-negotiation 1G advertisement */
431 hw->phy.ops.read_reg(hw,
432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
433 MDIO_MMD_AN,
434 &autoneg_reg);
435
436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
439
440 hw->phy.ops.write_reg(hw,
441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
442 MDIO_MMD_AN,
443 autoneg_reg);
444 }
445
446 if (speed & IXGBE_LINK_SPEED_100_FULL) {
447 /* Set or unset auto-negotiation 100M advertisement */
448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
452 autoneg_reg &= ~ADVERTISE_100FULL;
453 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
454 autoneg_reg |= ADVERTISE_100FULL;
455
456 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
457 MDIO_MMD_AN,
458 autoneg_reg);
459 }
424 460
425 /* Restart PHY autonegotiation and wait for completion */ 461 /* Restart PHY autonegotiation and wait for completion */
426 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg); 462 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
463 MDIO_MMD_AN, &autoneg_reg);
427 464
428 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 465 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
429 466
430 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg); 467 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
468 MDIO_MMD_AN, autoneg_reg);
431 469
432 /* Wait for autonegotiation to finish */ 470 /* Wait for autonegotiation to finish */
433 for (time_out = 0; time_out < max_time_out; time_out++) { 471 for (time_out = 0; time_out < max_time_out; time_out++) {
434 udelay(10); 472 udelay(10);
435 /* Restart PHY autonegotiation and wait for completion */ 473 /* Restart PHY autonegotiation and wait for completion */
436 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 474 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
437 &autoneg_reg); 475 MDIO_MMD_AN,
476 &autoneg_reg);
438 477
439 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 478 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
440 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { 479 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
441 status = 0;
442 break; 480 break;
443 } 481 }
444 } 482 }
445 483
446 if (time_out == max_time_out) 484 if (time_out == max_time_out) {
447 status = IXGBE_ERR_LINK_SETUP; 485 status = IXGBE_ERR_LINK_SETUP;
486 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
487 }
448 488
449 return status; 489 return status;
450} 490}
@@ -473,6 +513,9 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
473 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 513 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
474 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 514 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
475 515
516 if (speed & IXGBE_LINK_SPEED_100_FULL)
517 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
518
476 /* Setup link based on the new speed settings */ 519 /* Setup link based on the new speed settings */
477 hw->phy.ops.setup_link(hw); 520 hw->phy.ops.setup_link(hw);
478 521
@@ -513,6 +556,180 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
513} 556}
514 557
515/** 558/**
559 * ixgbe_check_phy_link_tnx - Determine link and speed status
560 * @hw: pointer to hardware structure
561 *
562 * Reads the VS1 register to determine if link is up and the current speed for
563 * the PHY.
564 **/
565s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
566 bool *link_up)
567{
568 s32 status = 0;
569 u32 time_out;
570 u32 max_time_out = 10;
571 u16 phy_link = 0;
572 u16 phy_speed = 0;
573 u16 phy_data = 0;
574
575 /* Initialize speed and link to default case */
576 *link_up = false;
577 *speed = IXGBE_LINK_SPEED_10GB_FULL;
578
579 /*
580 * Check current speed and link status of the PHY register.
581 * This is a vendor specific register and may have to
582 * be changed for other copper PHYs.
583 */
584 for (time_out = 0; time_out < max_time_out; time_out++) {
585 udelay(10);
586 status = hw->phy.ops.read_reg(hw,
587 MDIO_STAT1,
588 MDIO_MMD_VEND1,
589 &phy_data);
590 phy_link = phy_data &
591 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
592 phy_speed = phy_data &
593 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
594 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
595 *link_up = true;
596 if (phy_speed ==
597 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
598 *speed = IXGBE_LINK_SPEED_1GB_FULL;
599 break;
600 }
601 }
602
603 return status;
604}
605
606/**
607 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
608 * @hw: pointer to hardware structure
609 *
610 * Restart autonegotiation and PHY and waits for completion.
611 **/
612s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
613{
614 s32 status = 0;
615 u32 time_out;
616 u32 max_time_out = 10;
617 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
618 bool autoneg = false;
619 ixgbe_link_speed speed;
620
621 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
622
623 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
624 /* Set or unset auto-negotiation 10G advertisement */
625 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
626 MDIO_MMD_AN,
627 &autoneg_reg);
628
629 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
630 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
631 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
632
633 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
634 MDIO_MMD_AN,
635 autoneg_reg);
636 }
637
638 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
639 /* Set or unset auto-negotiation 1G advertisement */
640 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
641 MDIO_MMD_AN,
642 &autoneg_reg);
643
644 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
645 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
646 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
647
648 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
649 MDIO_MMD_AN,
650 autoneg_reg);
651 }
652
653 if (speed & IXGBE_LINK_SPEED_100_FULL) {
654 /* Set or unset auto-negotiation 100M advertisement */
655 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
656 MDIO_MMD_AN,
657 &autoneg_reg);
658
659 autoneg_reg &= ~ADVERTISE_100FULL;
660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
661 autoneg_reg |= ADVERTISE_100FULL;
662
663 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
664 MDIO_MMD_AN,
665 autoneg_reg);
666 }
667
668 /* Restart PHY autonegotiation and wait for completion */
669 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
670 MDIO_MMD_AN, &autoneg_reg);
671
672 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
673
674 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
675 MDIO_MMD_AN, autoneg_reg);
676
677 /* Wait for autonegotiation to finish */
678 for (time_out = 0; time_out < max_time_out; time_out++) {
679 udelay(10);
680 /* Restart PHY autonegotiation and wait for completion */
681 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
682 MDIO_MMD_AN,
683 &autoneg_reg);
684
685 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
686 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
687 break;
688 }
689
690 if (time_out == max_time_out) {
691 status = IXGBE_ERR_LINK_SETUP;
692 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
693 }
694
695 return status;
696}
697
698/**
699 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
700 * @hw: pointer to hardware structure
701 * @firmware_version: pointer to the PHY Firmware Version
702 **/
703s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
704 u16 *firmware_version)
705{
706 s32 status = 0;
707
708 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
709 MDIO_MMD_VEND1,
710 firmware_version);
711
712 return status;
713}
714
715/**
716 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
717 * @hw: pointer to hardware structure
718 * @firmware_version: pointer to the PHY Firmware Version
719 **/
720s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
721 u16 *firmware_version)
722{
723 s32 status = 0;
724
725 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
726 MDIO_MMD_VEND1,
727 firmware_version);
728
729 return status;
730}
731
732/**
516 * ixgbe_reset_phy_nl - Performs a PHY reset 733 * ixgbe_reset_phy_nl - Performs a PHY reset
517 * @hw: pointer to hardware structure 734 * @hw: pointer to hardware structure
518 **/ 735 **/
@@ -1477,86 +1694,6 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1477} 1694}
1478 1695
1479/** 1696/**
1480 * ixgbe_check_phy_link_tnx - Determine link and speed status
1481 * @hw: pointer to hardware structure
1482 *
1483 * Reads the VS1 register to determine if link is up and the current speed for
1484 * the PHY.
1485 **/
1486s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1487 bool *link_up)
1488{
1489 s32 status = 0;
1490 u32 time_out;
1491 u32 max_time_out = 10;
1492 u16 phy_link = 0;
1493 u16 phy_speed = 0;
1494 u16 phy_data = 0;
1495
1496 /* Initialize speed and link to default case */
1497 *link_up = false;
1498 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1499
1500 /*
1501 * Check current speed and link status of the PHY register.
1502 * This is a vendor specific register and may have to
1503 * be changed for other copper PHYs.
1504 */
1505 for (time_out = 0; time_out < max_time_out; time_out++) {
1506 udelay(10);
1507 status = hw->phy.ops.read_reg(hw,
1508 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1509 MDIO_MMD_VEND1,
1510 &phy_data);
1511 phy_link = phy_data &
1512 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1513 phy_speed = phy_data &
1514 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1515 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1516 *link_up = true;
1517 if (phy_speed ==
1518 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1519 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1520 break;
1521 }
1522 }
1523
1524 return status;
1525}
1526
1527/**
1528 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1529 * @hw: pointer to hardware structure
1530 * @firmware_version: pointer to the PHY Firmware Version
1531 **/
1532s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1533 u16 *firmware_version)
1534{
1535 s32 status = 0;
1536
1537 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1538 firmware_version);
1539
1540 return status;
1541}
1542
1543/**
1544 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1545 * @hw: pointer to hardware structure
1546 * @firmware_version: pointer to the PHY Firmware Version
1547**/
1548s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1549 u16 *firmware_version)
1550{
1551 s32 status = 0;
1552
1553 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
1554 firmware_version);
1555
1556 return status;
1557}
1558
1559/**
1560 * ixgbe_tn_check_overtemp - Checks if an overtemp occured. 1697 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1561 * @hw: pointer to hardware structure 1698 * @hw: pointer to hardware structure
1562 * 1699 *
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h
index 9bf2783d7a74..197bdd13106a 100644
--- a/drivers/net/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ixgbe/ixgbe_phy.h
@@ -108,6 +108,7 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
108s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 108s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
109 ixgbe_link_speed *speed, 109 ixgbe_link_speed *speed,
110 bool *link_up); 110 bool *link_up);
111s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
111s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 112s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
112 u16 *firmware_version); 113 u16 *firmware_version);
113s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 114s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
diff --git a/drivers/net/ixgbe/ixgbe_sriov.c b/drivers/net/ixgbe/ixgbe_sriov.c
index 58c9b45989ff..6e50d8328942 100644
--- a/drivers/net/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ixgbe/ixgbe_sriov.c
@@ -478,9 +478,90 @@ out:
478 return err; 478 return err;
479} 479}
480 480
481static int ixgbe_link_mbps(int internal_link_speed)
482{
483 switch (internal_link_speed) {
484 case IXGBE_LINK_SPEED_100_FULL:
485 return 100;
486 case IXGBE_LINK_SPEED_1GB_FULL:
487 return 1000;
488 case IXGBE_LINK_SPEED_10GB_FULL:
489 return 10000;
490 default:
491 return 0;
492 }
493}
494
495static void ixgbe_set_vf_rate_limit(struct ixgbe_hw *hw, int vf, int tx_rate,
496 int link_speed)
497{
498 int rf_dec, rf_int;
499 u32 bcnrc_val;
500
501 if (tx_rate != 0) {
502 /* Calculate the rate factor values to set */
503 rf_int = link_speed / tx_rate;
504 rf_dec = (link_speed - (rf_int * tx_rate));
505 rf_dec = (rf_dec * (1<<IXGBE_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
506
507 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
508 bcnrc_val |= ((rf_int<<IXGBE_RTTBCNRC_RF_INT_SHIFT) &
509 IXGBE_RTTBCNRC_RF_INT_MASK);
510 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
511 } else {
512 bcnrc_val = 0;
513 }
514
515 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, 2*vf); /* vf Y uses queue 2*Y */
516 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
517}
518
519void ixgbe_check_vf_rate_limit(struct ixgbe_adapter *adapter)
520{
521 int actual_link_speed, i;
522 bool reset_rate = false;
523
524 /* VF Tx rate limit was not set */
525 if (adapter->vf_rate_link_speed == 0)
526 return;
527
528 actual_link_speed = ixgbe_link_mbps(adapter->link_speed);
529 if (actual_link_speed != adapter->vf_rate_link_speed) {
530 reset_rate = true;
531 adapter->vf_rate_link_speed = 0;
532 dev_info(&adapter->pdev->dev,
533 "Link speed has been changed. VF Transmit rate "
534 "is disabled\n");
535 }
536
537 for (i = 0; i < adapter->num_vfs; i++) {
538 if (reset_rate)
539 adapter->vfinfo[i].tx_rate = 0;
540
541 ixgbe_set_vf_rate_limit(&adapter->hw, i,
542 adapter->vfinfo[i].tx_rate,
543 actual_link_speed);
544 }
545}
546
481int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 547int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
482{ 548{
483 return -EOPNOTSUPP; 549 struct ixgbe_adapter *adapter = netdev_priv(netdev);
550 struct ixgbe_hw *hw = &adapter->hw;
551 int actual_link_speed;
552
553 actual_link_speed = ixgbe_link_mbps(adapter->link_speed);
554 if ((vf >= adapter->num_vfs) || (!adapter->link_up) ||
555 (tx_rate > actual_link_speed) || (actual_link_speed != 10000) ||
556 ((tx_rate != 0) && (tx_rate <= 10)))
557 /* rate limit cannot be set to 10Mb or less in 10Gb adapters */
558 return -EINVAL;
559
560 adapter->vf_rate_link_speed = actual_link_speed;
561 adapter->vfinfo[vf].tx_rate = (u16)tx_rate;
562 ixgbe_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
563
564 return 0;
484} 565}
485 566
486int ixgbe_ndo_get_vf_config(struct net_device *netdev, 567int ixgbe_ndo_get_vf_config(struct net_device *netdev,
@@ -491,7 +572,7 @@ int ixgbe_ndo_get_vf_config(struct net_device *netdev,
491 return -EINVAL; 572 return -EINVAL;
492 ivi->vf = vf; 573 ivi->vf = vf;
493 memcpy(&ivi->mac, adapter->vfinfo[vf].vf_mac_addresses, ETH_ALEN); 574 memcpy(&ivi->mac, adapter->vfinfo[vf].vf_mac_addresses, ETH_ALEN);
494 ivi->tx_rate = 0; 575 ivi->tx_rate = adapter->vfinfo[vf].tx_rate;
495 ivi->vlan = adapter->vfinfo[vf].pf_vlan; 576 ivi->vlan = adapter->vfinfo[vf].pf_vlan;
496 ivi->qos = adapter->vfinfo[vf].pf_qos; 577 ivi->qos = adapter->vfinfo[vf].pf_qos;
497 return 0; 578 return 0;
diff --git a/drivers/net/ixgbe/ixgbe_sriov.h b/drivers/net/ixgbe/ixgbe_sriov.h
index e7dd029d576a..34175564bb78 100644
--- a/drivers/net/ixgbe/ixgbe_sriov.h
+++ b/drivers/net/ixgbe/ixgbe_sriov.h
@@ -40,6 +40,7 @@ int ixgbe_ndo_set_vf_vlan(struct net_device *netdev, int queue, u16 vlan,
40int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 40int ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
41int ixgbe_ndo_get_vf_config(struct net_device *netdev, 41int ixgbe_ndo_get_vf_config(struct net_device *netdev,
42 int vf, struct ifla_vf_info *ivi); 42 int vf, struct ifla_vf_info *ivi);
43void ixgbe_check_vf_rate_limit(struct ixgbe_adapter *adapter);
43 44
44#endif /* _IXGBE_SRIOV_H_ */ 45#endif /* _IXGBE_SRIOV_H_ */
45 46
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index f190a4a8faf4..25c1fb7eda06 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -533,6 +533,12 @@
533#define IXGBE_RTTDTECC 0x04990 533#define IXGBE_RTTDTECC 0x04990
534#define IXGBE_RTTDTECC_NO_BCN 0x00000100 534#define IXGBE_RTTDTECC_NO_BCN 0x00000100
535#define IXGBE_RTTBCNRC 0x04984 535#define IXGBE_RTTBCNRC 0x04984
536#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
537#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
538#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
539#define IXGBE_RTTBCNRC_RF_INT_MASK \
540 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
541
536 542
537/* FCoE registers */ 543/* FCoE registers */
538#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 544#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
@@ -1009,6 +1015,13 @@
1009#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1015#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1010#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1016#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1011 1017
1018/* MII clause 22/28 definitions */
1019#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1020#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1021#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1022#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1023#define IXGBE_MII_AUTONEG_REG 0x0
1024
1012#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1025#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1013#define IXGBE_MAX_PHY_ADDR 32 1026#define IXGBE_MAX_PHY_ADDR 32
1014 1027
diff --git a/drivers/net/ixgbevf/ethtool.c b/drivers/net/ixgbevf/ethtool.c
index fa29b3c8c464..0563ab29264e 100644
--- a/drivers/net/ixgbevf/ethtool.c
+++ b/drivers/net/ixgbevf/ethtool.c
@@ -172,7 +172,7 @@ static char *ixgbevf_reg_names[] = {
172 "IXGBE_VFSTATUS", 172 "IXGBE_VFSTATUS",
173 "IXGBE_VFLINKS", 173 "IXGBE_VFLINKS",
174 "IXGBE_VFRXMEMWRAP", 174 "IXGBE_VFRXMEMWRAP",
175 "IXGBE_VFRTIMER", 175 "IXGBE_VFFRTIMER",
176 "IXGBE_VTEICR", 176 "IXGBE_VTEICR",
177 "IXGBE_VTEICS", 177 "IXGBE_VTEICS",
178 "IXGBE_VTEIMS", 178 "IXGBE_VTEIMS",
@@ -240,7 +240,7 @@ static void ixgbevf_get_regs(struct net_device *netdev,
240 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_VFSTATUS); 240 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_VFSTATUS);
241 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 241 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
242 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_VFRXMEMWRAP); 242 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_VFRXMEMWRAP);
243 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_VFRTIMER); 243 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_VFFRTIMER);
244 244
245 /* Interrupt */ 245 /* Interrupt */
246 /* don't read EICR because it can clear interrupt causes, instead 246 /* don't read EICR because it can clear interrupt causes, instead
diff --git a/drivers/net/ixgbevf/ixgbevf_main.c b/drivers/net/ixgbevf/ixgbevf_main.c
index c1fb2c1b540e..054ab05b7c6a 100644
--- a/drivers/net/ixgbevf/ixgbevf_main.c
+++ b/drivers/net/ixgbevf/ixgbevf_main.c
@@ -49,9 +49,9 @@
49 49
50char ixgbevf_driver_name[] = "ixgbevf"; 50char ixgbevf_driver_name[] = "ixgbevf";
51static const char ixgbevf_driver_string[] = 51static const char ixgbevf_driver_string[] =
52 "Intel(R) 82599 Virtual Function"; 52 "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver";
53 53
54#define DRV_VERSION "1.1.0-k0" 54#define DRV_VERSION "2.0.0-k2"
55const char ixgbevf_driver_version[] = DRV_VERSION; 55const char ixgbevf_driver_version[] = DRV_VERSION;
56static char ixgbevf_copyright[] = 56static char ixgbevf_copyright[] =
57 "Copyright (c) 2009 - 2010 Intel Corporation."; 57 "Copyright (c) 2009 - 2010 Intel Corporation.";
diff --git a/drivers/net/ixgbevf/regs.h b/drivers/net/ixgbevf/regs.h
index fb80ca1bcc93..189200eeca26 100644
--- a/drivers/net/ixgbevf/regs.h
+++ b/drivers/net/ixgbevf/regs.h
@@ -31,7 +31,7 @@
31#define IXGBE_VFCTRL 0x00000 31#define IXGBE_VFCTRL 0x00000
32#define IXGBE_VFSTATUS 0x00008 32#define IXGBE_VFSTATUS 0x00008
33#define IXGBE_VFLINKS 0x00010 33#define IXGBE_VFLINKS 0x00010
34#define IXGBE_VFRTIMER 0x00048 34#define IXGBE_VFFRTIMER 0x00048
35#define IXGBE_VFRXMEMWRAP 0x03190 35#define IXGBE_VFRXMEMWRAP 0x03190
36#define IXGBE_VTEICR 0x00100 36#define IXGBE_VTEICR 0x00100
37#define IXGBE_VTEICS 0x00104 37#define IXGBE_VTEICS 0x00104
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 23:41:09 -0500