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-rw-r--r--arch/blackfin/kernel/cplb-mpu/Makefile2
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cacheinit.c71
-rw-r--r--arch/blackfin/kernel/cplb-nompu/Makefile2
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cacheinit.c71
-rw-r--r--arch/blackfin/mach-common/cache-c.c44
5 files changed, 45 insertions, 145 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
index 7d70d3bf3212..394d0b1b28fe 100644
--- a/arch/blackfin/kernel/cplb-mpu/Makefile
+++ b/arch/blackfin/kernel/cplb-mpu/Makefile
@@ -2,7 +2,7 @@
2# arch/blackfin/kernel/cplb-nompu/Makefile 2# arch/blackfin/kernel/cplb-nompu/Makefile
3# 3#
4 4
5obj-y := cplbinit.o cacheinit.o cplbmgr.o 5obj-y := cplbinit.o cplbmgr.o
6 6
7CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ 7CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
deleted file mode 100644
index a082681faa8e..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright 2004-2007 Analog Devices Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see the file COPYING, or write
16 * to the Free Software Foundation, Inc.,
17 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/cpu.h>
21
22#include <asm/cacheflush.h>
23#include <asm/blackfin.h>
24#include <asm/cplb.h>
25#include <asm/cplbinit.h>
26
27#if defined(CONFIG_BFIN_ICACHE)
28void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
29{
30 unsigned long ctrl;
31 int i;
32
33 for (i = 0; i < MAX_CPLBS; i++) {
34 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
35 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
36 }
37 ctrl = bfin_read_IMEM_CONTROL();
38 ctrl |= IMC | ENICPLB;
39 /* CSYNC to ensure load store ordering */
40 CSYNC();
41 bfin_write_IMEM_CONTROL(ctrl);
42 SSYNC();
43}
44#endif
45
46#if defined(CONFIG_BFIN_DCACHE)
47void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
48{
49 unsigned long ctrl;
50 int i;
51
52 for (i = 0; i < MAX_CPLBS; i++) {
53 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
54 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
55 }
56
57 ctrl = bfin_read_DMEM_CONTROL();
58
59 /*
60 * Anomaly notes:
61 * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
62 * register, so that the port preferences for DAG0 and DAG1 are set
63 * to port B
64 */
65 ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
66 /* CSYNC to ensure load store ordering */
67 CSYNC();
68 bfin_write_DMEM_CONTROL(ctrl);
69 SSYNC();
70}
71#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
index 7d70d3bf3212..394d0b1b28fe 100644
--- a/arch/blackfin/kernel/cplb-nompu/Makefile
+++ b/arch/blackfin/kernel/cplb-nompu/Makefile
@@ -2,7 +2,7 @@
2# arch/blackfin/kernel/cplb-nompu/Makefile 2# arch/blackfin/kernel/cplb-nompu/Makefile
3# 3#
4 4
5obj-y := cplbinit.o cacheinit.o cplbmgr.o 5obj-y := cplbinit.o cplbmgr.o
6 6
7CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ 7CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
deleted file mode 100644
index a082681faa8e..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright 2004-2007 Analog Devices Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see the file COPYING, or write
16 * to the Free Software Foundation, Inc.,
17 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/cpu.h>
21
22#include <asm/cacheflush.h>
23#include <asm/blackfin.h>
24#include <asm/cplb.h>
25#include <asm/cplbinit.h>
26
27#if defined(CONFIG_BFIN_ICACHE)
28void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
29{
30 unsigned long ctrl;
31 int i;
32
33 for (i = 0; i < MAX_CPLBS; i++) {
34 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
35 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
36 }
37 ctrl = bfin_read_IMEM_CONTROL();
38 ctrl |= IMC | ENICPLB;
39 /* CSYNC to ensure load store ordering */
40 CSYNC();
41 bfin_write_IMEM_CONTROL(ctrl);
42 SSYNC();
43}
44#endif
45
46#if defined(CONFIG_BFIN_DCACHE)
47void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
48{
49 unsigned long ctrl;
50 int i;
51
52 for (i = 0; i < MAX_CPLBS; i++) {
53 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
54 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
55 }
56
57 ctrl = bfin_read_DMEM_CONTROL();
58
59 /*
60 * Anomaly notes:
61 * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
62 * register, so that the port preferences for DAG0 and DAG1 are set
63 * to port B
64 */
65 ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
66 /* CSYNC to ensure load store ordering */
67 CSYNC();
68 bfin_write_DMEM_CONTROL(ctrl);
69 SSYNC();
70}
71#endif
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
index b59ce3cb3807..4ebbd78db3a4 100644
--- a/arch/blackfin/mach-common/cache-c.c
+++ b/arch/blackfin/mach-common/cache-c.c
@@ -1,14 +1,16 @@
1/* 1/*
2 * Blackfin cache control code (simpler control-style functions) 2 * Blackfin cache control code (simpler control-style functions)
3 * 3 *
4 * Copyright 2004-2008 Analog Devices Inc. 4 * Copyright 2004-2009 Analog Devices Inc.
5 * 5 *
6 * Enter bugs at http://blackfin.uclinux.org/ 6 * Enter bugs at http://blackfin.uclinux.org/
7 * 7 *
8 * Licensed under the GPL-2 or later. 8 * Licensed under the GPL-2 or later.
9 */ 9 */
10 10
11#include <linux/init.h>
11#include <asm/blackfin.h> 12#include <asm/blackfin.h>
13#include <asm/cplbinit.h>
12 14
13/* Invalidate the Entire Data cache by 15/* Invalidate the Entire Data cache by
14 * clearing DMC[1:0] bits 16 * clearing DMC[1:0] bits
@@ -34,3 +36,43 @@ void blackfin_invalidate_entire_icache(void)
34 SSYNC(); 36 SSYNC();
35} 37}
36 38
39#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
40
41static void
42bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
43 unsigned long cplb_data, unsigned long mem_control,
44 unsigned long mem_mask)
45{
46 int i;
47
48 for (i = 0; i < MAX_CPLBS; i++) {
49 bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
50 bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
51 }
52
53 _enable_cplb(mem_control, mem_mask);
54}
55
56#ifdef CONFIG_BFIN_ICACHE
57void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
58{
59 bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
60 (IMC | ENICPLB));
61}
62#endif
63
64#ifdef CONFIG_BFIN_DCACHE
65void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
66{
67 /*
68 * Anomaly notes:
69 * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
70 * register, so that the port preferences for DAG0 and DAG1 are set
71 * to port B
72 */
73 bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
74 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
75}
76#endif
77
78#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-17 23:45:49 -0500