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-rw-r--r--arch/blackfin/include/asm/bfin_sdh.h119
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h135
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF542.h130
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h130
4 files changed, 117 insertions, 397 deletions
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
index d61d5497c590..6a4cfe2d3367 100644
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ b/arch/blackfin/include/asm/bfin_sdh.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * bfin_sdh.h - Blackfin SDH definitions 2 * Blackfin Secure Digital Host (SDH) definitions
3 * 3 *
4 * Copyright 2008 Analog Devices Inc. 4 * Copyright 2008-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -9,6 +9,7 @@
9#ifndef __BFIN_SDH_H__ 9#ifndef __BFIN_SDH_H__
10#define __BFIN_SDH_H__ 10#define __BFIN_SDH_H__
11 11
12/* Platform resources */
12struct bfin_sd_host { 13struct bfin_sd_host {
13 int dma_chan; 14 int dma_chan;
14 int irq_int0; 15 int irq_int0;
@@ -16,4 +17,118 @@ struct bfin_sd_host {
16 u16 pin_req[7]; 17 u16 pin_req[7];
17}; 18};
18 19
20/* SDH_COMMAND bitmasks */
21#define CMD_IDX 0x3f /* Command Index */
22#define CMD_RSP (1 << 6) /* Response */
23#define CMD_L_RSP (1 << 7) /* Long Response */
24#define CMD_INT_E (1 << 8) /* Command Interrupt */
25#define CMD_PEND_E (1 << 9) /* Command Pending */
26#define CMD_E (1 << 10) /* Command Enable */
27
28/* SDH_PWR_CTL bitmasks */
29#define PWR_ON 0x3 /* Power On */
30#define SD_CMD_OD (1 << 6) /* Open Drain Output */
31#define ROD_CTL (1 << 7) /* Rod Control */
32
33/* SDH_CLK_CTL bitmasks */
34#define CLKDIV 0xff /* MC_CLK Divisor */
35#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
36#define PWR_SV_E (1 << 9) /* Power Save Enable */
37#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
38#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
39
40/* SDH_RESP_CMD bitmasks */
41#define RESP_CMD 0x3f /* Response Command */
42
43/* SDH_DATA_CTL bitmasks */
44#define DTX_E (1 << 0) /* Data Transfer Enable */
45#define DTX_DIR (1 << 1) /* Data Transfer Direction */
46#define DTX_MODE (1 << 2) /* Data Transfer Mode */
47#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
48#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
49
50/* SDH_STATUS bitmasks */
51#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
52#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
53#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
54#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
55#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
56#define RX_OVERRUN (1 << 5) /* Receive Overrun */
57#define CMD_RESP_END (1 << 6) /* CMD Response End */
58#define CMD_SENT (1 << 7) /* CMD Sent */
59#define DAT_END (1 << 8) /* Data End */
60#define START_BIT_ERR (1 << 9) /* Start Bit Error */
61#define DAT_BLK_END (1 << 10) /* Data Block End */
62#define CMD_ACT (1 << 11) /* CMD Active */
63#define TX_ACT (1 << 12) /* Transmit Active */
64#define RX_ACT (1 << 13) /* Receive Active */
65#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
66#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
67#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
68#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
69#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
70#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
71#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
72#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
73
74/* SDH_STATUS_CLR bitmasks */
75#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
76#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
77#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
78#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
79#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
80#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
81#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
82#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
83#define DAT_END_STAT (1 << 8) /* Data End Status */
84#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
85#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
86
87/* SDH_MASK0 bitmasks */
88#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
89#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
90#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
91#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
92#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
93#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
94#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
95#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
96#define DAT_END_MASK (1 << 8) /* Data End Mask */
97#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
98#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
99#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
100#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
101#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
102#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
103#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
104#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
105#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
106#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
107#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
108#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
109#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
110
111/* SDH_FIFO_CNT bitmasks */
112#define FIFO_COUNT 0x7fff /* FIFO Count */
113
114/* SDH_E_STATUS bitmasks */
115#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
116#define SD_CARD_DET (1 << 4) /* SD Card Detect */
117
118/* SDH_E_MASK bitmasks */
119#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
120#define SCD_MSK (1 << 6) /* Mask Card Detect */
121
122/* SDH_CFG bitmasks */
123#define CLKS_EN (1 << 0) /* Clocks Enable */
124#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
125#define MWE (1 << 3) /* Moving Window Enable */
126#define SD_RST (1 << 4) /* SDMMC Reset */
127#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
128#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
129#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
130
131/* SDH_RD_WAIT_EN bitmasks */
132#define RWR (1 << 0) /* Read Wait Request */
133
19#endif 134#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index 92e950d6e996..98a51c479290 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -45,139 +45,4 @@
45#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ 45#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
46#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ 46#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
47 47
48/* ********************************************************** */
49/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
50/* and MULTI BIT READ MACROS */
51/* ********************************************************** */
52
53/* Bit masks for SDH_COMMAND */
54
55#define CMD_IDX 0x3f /* Command Index */
56#define CMD_RSP 0x40 /* Response */
57#define CMD_L_RSP 0x80 /* Long Response */
58#define CMD_INT_E 0x100 /* Command Interrupt */
59#define CMD_PEND_E 0x200 /* Command Pending */
60#define CMD_E 0x400 /* Command Enable */
61
62/* Bit masks for SDH_PWR_CTL */
63
64#define PWR_ON 0x3 /* Power On */
65#if 0
66#define TBD 0x3c /* TBD */
67#endif
68#define SD_CMD_OD 0x40 /* Open Drain Output */
69#define ROD_CTL 0x80 /* Rod Control */
70
71/* Bit masks for SDH_CLK_CTL */
72
73#define CLKDIV 0xff /* MC_CLK Divisor */
74#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
75#define PWR_SV_E 0x200 /* Power Save Enable */
76#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
77#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
78
79/* Bit masks for SDH_RESP_CMD */
80
81#define RESP_CMD 0x3f /* Response Command */
82
83/* Bit masks for SDH_DATA_CTL */
84
85#define DTX_E 0x1 /* Data Transfer Enable */
86#define DTX_DIR 0x2 /* Data Transfer Direction */
87#define DTX_MODE 0x4 /* Data Transfer Mode */
88#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
89#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
90
91/* Bit masks for SDH_STATUS */
92
93#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
94#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
95#define CMD_TIME_OUT 0x4 /* CMD Time Out */
96#define DAT_TIME_OUT 0x8 /* Data Time Out */
97#define TX_UNDERRUN 0x10 /* Transmit Underrun */
98#define RX_OVERRUN 0x20 /* Receive Overrun */
99#define CMD_RESP_END 0x40 /* CMD Response End */
100#define CMD_SENT 0x80 /* CMD Sent */
101#define DAT_END 0x100 /* Data End */
102#define START_BIT_ERR 0x200 /* Start Bit Error */
103#define DAT_BLK_END 0x400 /* Data Block End */
104#define CMD_ACT 0x800 /* CMD Active */
105#define TX_ACT 0x1000 /* Transmit Active */
106#define RX_ACT 0x2000 /* Receive Active */
107#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
108#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
109#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
110#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
111#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
112#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
113#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
114#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
115
116/* Bit masks for SDH_STATUS_CLR */
117
118#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
119#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
120#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
121#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
122#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
123#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
124#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
125#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
126#define DAT_END_STAT 0x100 /* Data End Status */
127#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
128#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
129
130/* Bit masks for SDH_MASK0 */
131
132#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
133#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
134#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
135#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
136#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
137#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
138#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
139#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
140#define DAT_END_MASK 0x100 /* Data End Mask */
141#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
142#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
143#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
144#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
145#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
146#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
147#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
148#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
149#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
150#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
151#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
152#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
153#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
154
155/* Bit masks for SDH_FIFO_CNT */
156
157#define FIFO_COUNT 0x7fff /* FIFO Count */
158
159/* Bit masks for SDH_E_STATUS */
160
161#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
162#define SD_CARD_DET 0x10 /* SD Card Detect */
163
164/* Bit masks for SDH_E_MASK */
165
166#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
167#define SCD_MSK 0x40 /* Mask Card Detect */
168
169/* Bit masks for SDH_CFG */
170
171#define CLKS_EN 0x1 /* Clocks Enable */
172#define SD4E 0x4 /* SDIO 4-Bit Enable */
173#define MWE 0x8 /* Moving Window Enable */
174#define SD_RST 0x10 /* SDMMC Reset */
175#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
176#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
177#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
178
179/* Bit masks for SDH_RD_WAIT_EN */
180
181#define RWR 0x1 /* Read Wait Request */
182
183#endif /* _DEF_BF514_H */ 48#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index d3bc6d1df547..abf5f750dd8b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -366,136 +366,6 @@
366 366
367#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 367#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
368 368
369/* Bit masks for SDH_COMMAND */
370
371#define CMD_IDX 0x3f /* Command Index */
372#define CMD_RSP 0x40 /* Response */
373#define CMD_L_RSP 0x80 /* Long Response */
374#define CMD_INT_E 0x100 /* Command Interrupt */
375#define CMD_PEND_E 0x200 /* Command Pending */
376#define CMD_E 0x400 /* Command Enable */
377
378/* Bit masks for SDH_PWR_CTL */
379
380#define PWR_ON 0x3 /* Power On */
381#if 0
382#define TBD 0x3c /* TBD */
383#endif
384#define SD_CMD_OD 0x40 /* Open Drain Output */
385#define ROD_CTL 0x80 /* Rod Control */
386
387/* Bit masks for SDH_CLK_CTL */
388
389#define CLKDIV 0xff /* MC_CLK Divisor */
390#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
391#define PWR_SV_E 0x200 /* Power Save Enable */
392#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
393#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
394
395/* Bit masks for SDH_RESP_CMD */
396
397#define RESP_CMD 0x3f /* Response Command */
398
399/* Bit masks for SDH_DATA_CTL */
400
401#define DTX_E 0x1 /* Data Transfer Enable */
402#define DTX_DIR 0x2 /* Data Transfer Direction */
403#define DTX_MODE 0x4 /* Data Transfer Mode */
404#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
405#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
406
407/* Bit masks for SDH_STATUS */
408
409#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
410#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
411#define CMD_TIME_OUT 0x4 /* CMD Time Out */
412#define DAT_TIME_OUT 0x8 /* Data Time Out */
413#define TX_UNDERRUN 0x10 /* Transmit Underrun */
414#define RX_OVERRUN 0x20 /* Receive Overrun */
415#define CMD_RESP_END 0x40 /* CMD Response End */
416#define CMD_SENT 0x80 /* CMD Sent */
417#define DAT_END 0x100 /* Data End */
418#define START_BIT_ERR 0x200 /* Start Bit Error */
419#define DAT_BLK_END 0x400 /* Data Block End */
420#define CMD_ACT 0x800 /* CMD Active */
421#define TX_ACT 0x1000 /* Transmit Active */
422#define RX_ACT 0x2000 /* Receive Active */
423#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
424#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
425#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
426#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
427#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
428#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
429#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
430#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
431
432/* Bit masks for SDH_STATUS_CLR */
433
434#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
435#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
436#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
437#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
438#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
439#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
440#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
441#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
442#define DAT_END_STAT 0x100 /* Data End Status */
443#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
444#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
445
446/* Bit masks for SDH_MASK0 */
447
448#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
449#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
450#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
451#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
452#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
453#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
454#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
455#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
456#define DAT_END_MASK 0x100 /* Data End Mask */
457#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
458#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
459#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
460#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
461#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
462#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
463#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
464#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
465#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
466#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
467#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
468#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
469#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
470
471/* Bit masks for SDH_FIFO_CNT */
472
473#define FIFO_COUNT 0x7fff /* FIFO Count */
474
475/* Bit masks for SDH_E_STATUS */
476
477#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
478#define SD_CARD_DET 0x10 /* SD Card Detect */
479
480/* Bit masks for SDH_E_MASK */
481
482#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
483#define SCD_MSK 0x40 /* Mask Card Detect */
484
485/* Bit masks for SDH_CFG */
486
487#define CLKS_EN 0x1 /* Clocks Enable */
488#define SD4E 0x4 /* SDIO 4-Bit Enable */
489#define MWE 0x8 /* Moving Window Enable */
490#define SD_RST 0x10 /* SDMMC Reset */
491#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
492#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
493#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
494
495/* Bit masks for SDH_RD_WAIT_EN */
496
497#define RWR 0x1 /* Read Wait Request */
498
499/* Bit masks for ATAPI_CONTROL */ 369/* Bit masks for ATAPI_CONTROL */
500 370
501#define PIO_START 0x1 /* Start PIO/Reg Op */ 371#define PIO_START 0x1 /* Start PIO/Reg Op */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 3d131065f8e6..be21ba5b3aa8 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -646,136 +646,6 @@
646 646
647#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 647#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
648 648
649/* Bit masks for SDH_COMMAND */
650
651#define CMD_IDX 0x3f /* Command Index */
652#define CMD_RSP 0x40 /* Response */
653#define CMD_L_RSP 0x80 /* Long Response */
654#define CMD_INT_E 0x100 /* Command Interrupt */
655#define CMD_PEND_E 0x200 /* Command Pending */
656#define CMD_E 0x400 /* Command Enable */
657
658/* Bit masks for SDH_PWR_CTL */
659
660#define PWR_ON 0x3 /* Power On */
661#if 0
662#define TBD 0x3c /* TBD */
663#endif
664#define SD_CMD_OD 0x40 /* Open Drain Output */
665#define ROD_CTL 0x80 /* Rod Control */
666
667/* Bit masks for SDH_CLK_CTL */
668
669#define CLKDIV 0xff /* MC_CLK Divisor */
670#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
671#define PWR_SV_E 0x200 /* Power Save Enable */
672#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
673#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
674
675/* Bit masks for SDH_RESP_CMD */
676
677#define RESP_CMD 0x3f /* Response Command */
678
679/* Bit masks for SDH_DATA_CTL */
680
681#define DTX_E 0x1 /* Data Transfer Enable */
682#define DTX_DIR 0x2 /* Data Transfer Direction */
683#define DTX_MODE 0x4 /* Data Transfer Mode */
684#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
685#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
686
687/* Bit masks for SDH_STATUS */
688
689#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
690#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
691#define CMD_TIME_OUT 0x4 /* CMD Time Out */
692#define DAT_TIME_OUT 0x8 /* Data Time Out */
693#define TX_UNDERRUN 0x10 /* Transmit Underrun */
694#define RX_OVERRUN 0x20 /* Receive Overrun */
695#define CMD_RESP_END 0x40 /* CMD Response End */
696#define CMD_SENT 0x80 /* CMD Sent */
697#define DAT_END 0x100 /* Data End */
698#define START_BIT_ERR 0x200 /* Start Bit Error */
699#define DAT_BLK_END 0x400 /* Data Block End */
700#define CMD_ACT 0x800 /* CMD Active */
701#define TX_ACT 0x1000 /* Transmit Active */
702#define RX_ACT 0x2000 /* Receive Active */
703#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
704#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
705#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
706#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
707#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
708#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
709#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
710#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
711
712/* Bit masks for SDH_STATUS_CLR */
713
714#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
715#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
716#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
717#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
718#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
719#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
720#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
721#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
722#define DAT_END_STAT 0x100 /* Data End Status */
723#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
724#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
725
726/* Bit masks for SDH_MASK0 */
727
728#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
729#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
730#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
731#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
732#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
733#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
734#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
735#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
736#define DAT_END_MASK 0x100 /* Data End Mask */
737#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
738#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
739#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
740#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
741#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
742#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
743#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
744#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
745#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
746#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
747#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
748#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
749#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
750
751/* Bit masks for SDH_FIFO_CNT */
752
753#define FIFO_COUNT 0x7fff /* FIFO Count */
754
755/* Bit masks for SDH_E_STATUS */
756
757#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
758#define SD_CARD_DET 0x10 /* SD Card Detect */
759
760/* Bit masks for SDH_E_MASK */
761
762#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
763#define SCD_MSK 0x40 /* Mask Card Detect */
764
765/* Bit masks for SDH_CFG */
766
767#define CLKS_EN 0x1 /* Clocks Enable */
768#define SD4E 0x4 /* SDIO 4-Bit Enable */
769#define MWE 0x8 /* Moving Window Enable */
770#define SD_RST 0x10 /* SDMMC Reset */
771#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
772#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
773#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
774
775/* Bit masks for SDH_RD_WAIT_EN */
776
777#define RWR 0x1 /* Read Wait Request */
778
779/* Bit masks for ATAPI_CONTROL */ 649/* Bit masks for ATAPI_CONTROL */
780 650
781#define PIO_START 0x1 /* Start PIO/Reg Op */ 651#define PIO_START 0x1 /* Start PIO/Reg Op */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 19:33:35 -0500