diff options
| -rw-r--r-- | arch/arm/mach-omap2/sram34xx.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 487fa8609cde..f41f8d96ddba 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S | |||
| @@ -41,8 +41,18 @@ | |||
| 41 | #define SDRC_UNLOCK_DLL 0x1 | 41 | #define SDRC_UNLOCK_DLL 0x1 |
| 42 | 42 | ||
| 43 | /* SDRC_DLLA_CTRL bit settings */ | 43 | /* SDRC_DLLA_CTRL bit settings */ |
| 44 | #define FIXEDDELAY_SHIFT 24 | ||
| 45 | #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) | ||
| 44 | #define DLLIDLE_MASK 0x4 | 46 | #define DLLIDLE_MASK 0x4 |
| 45 | 47 | ||
| 48 | /* | ||
| 49 | * SDRC_DLLA_CTRL default values: TI hardware team indicates that | ||
| 50 | * FIXEDDELAY should be initialized to 0xf. This apparently was | ||
| 51 | * empirically determined during process testing, so no derivation | ||
| 52 | * was provided. | ||
| 53 | */ | ||
| 54 | #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) | ||
| 55 | |||
| 46 | /* SDRC_DLLA_STATUS bit settings */ | 56 | /* SDRC_DLLA_STATUS bit settings */ |
| 47 | #define LOCKSTATUS_MASK 0x4 | 57 | #define LOCKSTATUS_MASK 0x4 |
| 48 | 58 | ||
| @@ -103,6 +113,8 @@ return_to_sdram: | |||
| 103 | unlock_dll: | 113 | unlock_dll: |
| 104 | ldr r11, omap3_sdrc_dlla_ctrl | 114 | ldr r11, omap3_sdrc_dlla_ctrl |
| 105 | ldr r12, [r11] | 115 | ldr r12, [r11] |
| 116 | and r12, r12, #FIXEDDELAY_MASK | ||
| 117 | orr r12, r12, #FIXEDDELAY_DEFAULT | ||
| 106 | orr r12, r12, #DLLIDLE_MASK | 118 | orr r12, r12, #DLLIDLE_MASK |
| 107 | str r12, [r11] @ (no OCP barrier needed) | 119 | str r12, [r11] @ (no OCP barrier needed) |
| 108 | bx lr | 120 | bx lr |
