diff options
| -rw-r--r-- | drivers/media/video/cx18/cx18-driver.c | 1 | ||||
| -rw-r--r-- | drivers/media/video/cx18/cx18-driver.h | 2 | ||||
| -rw-r--r-- | drivers/media/video/cx18/cx18-irq.c | 54 | ||||
| -rw-r--r-- | drivers/media/video/cx18/cx18-scb.h | 40 |
4 files changed, 49 insertions, 48 deletions
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 6a840f2d81a0..2befa3819cdb 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c | |||
| @@ -448,7 +448,6 @@ static int __devinit cx18_init_struct1(struct cx18 *cx) | |||
| 448 | mutex_init(&cx->gpio_lock); | 448 | mutex_init(&cx->gpio_lock); |
| 449 | 449 | ||
| 450 | spin_lock_init(&cx->lock); | 450 | spin_lock_init(&cx->lock); |
| 451 | spin_lock_init(&cx->dma_reg_lock); | ||
| 452 | 451 | ||
| 453 | /* start counting open_id at 1 */ | 452 | /* start counting open_id at 1 */ |
| 454 | cx->open_id = 1; | 453 | cx->open_id = 1; |
diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h index a4b1708fafe7..e721c01d2178 100644 --- a/drivers/media/video/cx18/cx18-driver.h +++ b/drivers/media/video/cx18/cx18-driver.h | |||
| @@ -402,8 +402,6 @@ struct cx18 { | |||
| 402 | spinlock_t lock; /* lock access to this struct */ | 402 | spinlock_t lock; /* lock access to this struct */ |
| 403 | int search_pack_header; | 403 | int search_pack_header; |
| 404 | 404 | ||
| 405 | spinlock_t dma_reg_lock; /* lock access to DMA engine registers */ | ||
| 406 | |||
| 407 | int open_id; /* incremented each time an open occurs, used as | 405 | int open_id; /* incremented each time an open occurs, used as |
| 408 | unique ID. Starts at 1, so 0 can be used as | 406 | unique ID. Starts at 1, so 0 can be used as |
| 409 | uninitialized value in the stream->id. */ | 407 | uninitialized value in the stream->id. */ |
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c index a366259bbb7b..c306e142c1c3 100644 --- a/drivers/media/video/cx18/cx18-irq.c +++ b/drivers/media/video/cx18/cx18-irq.c | |||
| @@ -30,8 +30,6 @@ | |||
| 30 | #include "cx18-vbi.h" | 30 | #include "cx18-vbi.h" |
| 31 | #include "cx18-scb.h" | 31 | #include "cx18-scb.h" |
| 32 | 32 | ||
| 33 | #define DMA_MAGIC_COOKIE 0x000001fe | ||
| 34 | |||
| 35 | static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) | 33 | static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) |
| 36 | { | 34 | { |
| 37 | u32 handle = mb->args[0]; | 35 | u32 handle = mb->args[0]; |
| @@ -109,7 +107,7 @@ static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb) | |||
| 109 | CX18_INFO("FW version: %s\n", p - 1); | 107 | CX18_INFO("FW version: %s\n", p - 1); |
| 110 | } | 108 | } |
| 111 | 109 | ||
| 112 | static void hpu_cmd(struct cx18 *cx, u32 sw1) | 110 | static void epu_cmd(struct cx18 *cx, u32 sw1) |
| 113 | { | 111 | { |
| 114 | struct cx18_mailbox mb; | 112 | struct cx18_mailbox mb; |
| 115 | 113 | ||
| @@ -125,12 +123,31 @@ static void hpu_cmd(struct cx18 *cx, u32 sw1) | |||
| 125 | epu_debug(cx, &mb); | 123 | epu_debug(cx, &mb); |
| 126 | break; | 124 | break; |
| 127 | default: | 125 | default: |
| 128 | CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd); | 126 | CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n", |
| 127 | mb.cmd); | ||
| 129 | break; | 128 | break; |
| 130 | } | 129 | } |
| 131 | } | 130 | } |
| 132 | if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU)) | 131 | |
| 133 | CX18_WARN("Unexpected interrupt %08x\n", sw1); | 132 | if (sw1 & IRQ_APU_TO_EPU) { |
| 133 | cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb)); | ||
| 134 | CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd); | ||
| 135 | } | ||
| 136 | |||
| 137 | if (sw1 & IRQ_HPU_TO_EPU) { | ||
| 138 | cx18_memcpy_fromio(cx, &mb, &cx->scb->hpu2epu_mb, sizeof(mb)); | ||
| 139 | CX18_WARN("Unknown HPU_TO_EPU mailbox command %#08x\n", mb.cmd); | ||
| 140 | } | ||
| 141 | } | ||
| 142 | |||
| 143 | static void xpu_ack(struct cx18 *cx, u32 sw2) | ||
| 144 | { | ||
| 145 | if (sw2 & IRQ_CPU_TO_EPU_ACK) | ||
| 146 | wake_up(&cx->mb_cpu_waitq); | ||
| 147 | if (sw2 & IRQ_APU_TO_EPU_ACK) | ||
| 148 | wake_up(&cx->mb_apu_waitq); | ||
| 149 | if (sw2 & IRQ_HPU_TO_EPU_ACK) | ||
| 150 | wake_up(&cx->mb_hpu_waitq); | ||
| 134 | } | 151 | } |
| 135 | 152 | ||
| 136 | irqreturn_t cx18_irq_handler(int irq, void *dev_id) | 153 | irqreturn_t cx18_irq_handler(int irq, void *dev_id) |
| @@ -140,11 +157,9 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id) | |||
| 140 | u32 sw2, sw2_mask; | 157 | u32 sw2, sw2_mask; |
| 141 | u32 hw2, hw2_mask; | 158 | u32 hw2, hw2_mask; |
| 142 | 159 | ||
| 143 | spin_lock(&cx->dma_reg_lock); | 160 | sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
| 144 | |||
| 145 | sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU; | ||
| 146 | sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; | 161 | sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; |
| 147 | sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK; | 162 | sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
| 148 | sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; | 163 | sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; |
| 149 | hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); | 164 | hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); |
| 150 | hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; | 165 | hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; |
| @@ -160,26 +175,15 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id) | |||
| 160 | CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); | 175 | CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); |
| 161 | 176 | ||
| 162 | /* To do: interrupt-based I2C handling | 177 | /* To do: interrupt-based I2C handling |
| 163 | if (hw2 & 0x00c00000) { | 178 | if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) { |
| 164 | } | 179 | } |
| 165 | */ | 180 | */ |
| 166 | 181 | ||
| 167 | if (sw2) { | 182 | if (sw2) |
| 168 | if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) | | 183 | xpu_ack(cx, sw2); |
| 169 | cx18_readl(cx, &cx->scb->cpu2epu_irq_ack))) | ||
| 170 | wake_up(&cx->mb_cpu_waitq); | ||
| 171 | if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) | | ||
| 172 | cx18_readl(cx, &cx->scb->apu2epu_irq_ack))) | ||
| 173 | wake_up(&cx->mb_apu_waitq); | ||
| 174 | if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack)) | ||
| 175 | wake_up(&cx->mb_epu_waitq); | ||
| 176 | if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack)) | ||
| 177 | wake_up(&cx->mb_hpu_waitq); | ||
| 178 | } | ||
| 179 | 184 | ||
| 180 | if (sw1) | 185 | if (sw1) |
| 181 | hpu_cmd(cx, sw1); | 186 | epu_cmd(cx, sw1); |
| 182 | spin_unlock(&cx->dma_reg_lock); | ||
| 183 | 187 | ||
| 184 | return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; | 188 | return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; |
| 185 | } | 189 | } |
diff --git a/drivers/media/video/cx18/cx18-scb.h b/drivers/media/video/cx18/cx18-scb.h index 86b4cb15d163..594713bbed68 100644 --- a/drivers/media/video/cx18/cx18-scb.h +++ b/drivers/media/video/cx18/cx18-scb.h | |||
| @@ -128,22 +128,22 @@ struct cx18_scb { | |||
| 128 | u32 apu2cpu_irq; | 128 | u32 apu2cpu_irq; |
| 129 | /* Value to write to register SW2 register set (0xC7003140) after the | 129 | /* Value to write to register SW2 register set (0xC7003140) after the |
| 130 | command is cleared */ | 130 | command is cleared */ |
| 131 | u32 apu2cpu_irq_ack; | 131 | u32 cpu2apu_irq_ack; |
| 132 | u32 reserved2[13]; | 132 | u32 reserved2[13]; |
| 133 | 133 | ||
| 134 | u32 hpu2cpu_mb_offset; | 134 | u32 hpu2cpu_mb_offset; |
| 135 | u32 hpu2cpu_irq; | 135 | u32 hpu2cpu_irq; |
| 136 | u32 hpu2cpu_irq_ack; | 136 | u32 cpu2hpu_irq_ack; |
| 137 | u32 reserved3[13]; | 137 | u32 reserved3[13]; |
| 138 | 138 | ||
| 139 | u32 ppu2cpu_mb_offset; | 139 | u32 ppu2cpu_mb_offset; |
| 140 | u32 ppu2cpu_irq; | 140 | u32 ppu2cpu_irq; |
| 141 | u32 ppu2cpu_irq_ack; | 141 | u32 cpu2ppu_irq_ack; |
| 142 | u32 reserved4[13]; | 142 | u32 reserved4[13]; |
| 143 | 143 | ||
| 144 | u32 epu2cpu_mb_offset; | 144 | u32 epu2cpu_mb_offset; |
| 145 | u32 epu2cpu_irq; | 145 | u32 epu2cpu_irq; |
| 146 | u32 epu2cpu_irq_ack; | 146 | u32 cpu2epu_irq_ack; |
| 147 | u32 reserved5[13]; | 147 | u32 reserved5[13]; |
| 148 | u32 reserved6[8]; | 148 | u32 reserved6[8]; |
| 149 | 149 | ||
| @@ -153,22 +153,22 @@ struct cx18_scb { | |||
| 153 | u32 reserved11[7]; | 153 | u32 reserved11[7]; |
| 154 | u32 cpu2apu_mb_offset; | 154 | u32 cpu2apu_mb_offset; |
| 155 | u32 cpu2apu_irq; | 155 | u32 cpu2apu_irq; |
| 156 | u32 cpu2apu_irq_ack; | 156 | u32 apu2cpu_irq_ack; |
| 157 | u32 reserved12[13]; | 157 | u32 reserved12[13]; |
| 158 | 158 | ||
| 159 | u32 hpu2apu_mb_offset; | 159 | u32 hpu2apu_mb_offset; |
| 160 | u32 hpu2apu_irq; | 160 | u32 hpu2apu_irq; |
| 161 | u32 hpu2apu_irq_ack; | 161 | u32 apu2hpu_irq_ack; |
| 162 | u32 reserved13[13]; | 162 | u32 reserved13[13]; |
| 163 | 163 | ||
| 164 | u32 ppu2apu_mb_offset; | 164 | u32 ppu2apu_mb_offset; |
| 165 | u32 ppu2apu_irq; | 165 | u32 ppu2apu_irq; |
| 166 | u32 ppu2apu_irq_ack; | 166 | u32 apu2ppu_irq_ack; |
| 167 | u32 reserved14[13]; | 167 | u32 reserved14[13]; |
| 168 | 168 | ||
| 169 | u32 epu2apu_mb_offset; | 169 | u32 epu2apu_mb_offset; |
| 170 | u32 epu2apu_irq; | 170 | u32 epu2apu_irq; |
| 171 | u32 epu2apu_irq_ack; | 171 | u32 apu2epu_irq_ack; |
| 172 | u32 reserved15[13]; | 172 | u32 reserved15[13]; |
| 173 | u32 reserved16[8]; | 173 | u32 reserved16[8]; |
| 174 | 174 | ||
| @@ -178,22 +178,22 @@ struct cx18_scb { | |||
| 178 | u32 reserved21[7]; | 178 | u32 reserved21[7]; |
| 179 | u32 cpu2hpu_mb_offset; | 179 | u32 cpu2hpu_mb_offset; |
| 180 | u32 cpu2hpu_irq; | 180 | u32 cpu2hpu_irq; |
| 181 | u32 cpu2hpu_irq_ack; | 181 | u32 hpu2cpu_irq_ack; |
| 182 | u32 reserved22[13]; | 182 | u32 reserved22[13]; |
| 183 | 183 | ||
| 184 | u32 apu2hpu_mb_offset; | 184 | u32 apu2hpu_mb_offset; |
| 185 | u32 apu2hpu_irq; | 185 | u32 apu2hpu_irq; |
| 186 | u32 apu2hpu_irq_ack; | 186 | u32 hpu2apu_irq_ack; |
| 187 | u32 reserved23[13]; | 187 | u32 reserved23[13]; |
| 188 | 188 | ||
| 189 | u32 ppu2hpu_mb_offset; | 189 | u32 ppu2hpu_mb_offset; |
| 190 | u32 ppu2hpu_irq; | 190 | u32 ppu2hpu_irq; |
| 191 | u32 ppu2hpu_irq_ack; | 191 | u32 hpu2ppu_irq_ack; |
| 192 | u32 reserved24[13]; | 192 | u32 reserved24[13]; |
| 193 | 193 | ||
| 194 | u32 epu2hpu_mb_offset; | 194 | u32 epu2hpu_mb_offset; |
| 195 | u32 epu2hpu_irq; | 195 | u32 epu2hpu_irq; |
| 196 | u32 epu2hpu_irq_ack; | 196 | u32 hpu2epu_irq_ack; |
| 197 | u32 reserved25[13]; | 197 | u32 reserved25[13]; |
| 198 | u32 reserved26[8]; | 198 | u32 reserved26[8]; |
| 199 | 199 | ||
| @@ -203,22 +203,22 @@ struct cx18_scb { | |||
| 203 | u32 reserved31[7]; | 203 | u32 reserved31[7]; |
| 204 | u32 cpu2ppu_mb_offset; | 204 | u32 cpu2ppu_mb_offset; |
| 205 | u32 cpu2ppu_irq; | 205 | u32 cpu2ppu_irq; |
| 206 | u32 cpu2ppu_irq_ack; | 206 | u32 ppu2cpu_irq_ack; |
| 207 | u32 reserved32[13]; | 207 | u32 reserved32[13]; |
| 208 | 208 | ||
| 209 | u32 apu2ppu_mb_offset; | 209 | u32 apu2ppu_mb_offset; |
| 210 | u32 apu2ppu_irq; | 210 | u32 apu2ppu_irq; |
| 211 | u32 apu2ppu_irq_ack; | 211 | u32 ppu2apu_irq_ack; |
| 212 | u32 reserved33[13]; | 212 | u32 reserved33[13]; |
| 213 | 213 | ||
| 214 | u32 hpu2ppu_mb_offset; | 214 | u32 hpu2ppu_mb_offset; |
| 215 | u32 hpu2ppu_irq; | 215 | u32 hpu2ppu_irq; |
| 216 | u32 hpu2ppu_irq_ack; | 216 | u32 ppu2hpu_irq_ack; |
| 217 | u32 reserved34[13]; | 217 | u32 reserved34[13]; |
| 218 | 218 | ||
| 219 | u32 epu2ppu_mb_offset; | 219 | u32 epu2ppu_mb_offset; |
| 220 | u32 epu2ppu_irq; | 220 | u32 epu2ppu_irq; |
| 221 | u32 epu2ppu_irq_ack; | 221 | u32 ppu2epu_irq_ack; |
| 222 | u32 reserved35[13]; | 222 | u32 reserved35[13]; |
| 223 | u32 reserved36[8]; | 223 | u32 reserved36[8]; |
| 224 | 224 | ||
| @@ -228,22 +228,22 @@ struct cx18_scb { | |||
| 228 | u32 reserved41[7]; | 228 | u32 reserved41[7]; |
| 229 | u32 cpu2epu_mb_offset; | 229 | u32 cpu2epu_mb_offset; |
| 230 | u32 cpu2epu_irq; | 230 | u32 cpu2epu_irq; |
| 231 | u32 cpu2epu_irq_ack; | 231 | u32 epu2cpu_irq_ack; |
| 232 | u32 reserved42[13]; | 232 | u32 reserved42[13]; |
| 233 | 233 | ||
| 234 | u32 apu2epu_mb_offset; | 234 | u32 apu2epu_mb_offset; |
| 235 | u32 apu2epu_irq; | 235 | u32 apu2epu_irq; |
| 236 | u32 apu2epu_irq_ack; | 236 | u32 epu2apu_irq_ack; |
| 237 | u32 reserved43[13]; | 237 | u32 reserved43[13]; |
| 238 | 238 | ||
| 239 | u32 hpu2epu_mb_offset; | 239 | u32 hpu2epu_mb_offset; |
| 240 | u32 hpu2epu_irq; | 240 | u32 hpu2epu_irq; |
| 241 | u32 hpu2epu_irq_ack; | 241 | u32 epu2hpu_irq_ack; |
| 242 | u32 reserved44[13]; | 242 | u32 reserved44[13]; |
| 243 | 243 | ||
| 244 | u32 ppu2epu_mb_offset; | 244 | u32 ppu2epu_mb_offset; |
| 245 | u32 ppu2epu_irq; | 245 | u32 ppu2epu_irq; |
| 246 | u32 ppu2epu_irq_ack; | 246 | u32 epu2ppu_irq_ack; |
| 247 | u32 reserved45[13]; | 247 | u32 reserved45[13]; |
| 248 | u32 reserved46[8]; | 248 | u32 reserved46[8]; |
| 249 | 249 | ||
