2 files changed, 32 insertions, 9 deletions

diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c
index d28128e0392c..93ceb19d1e90 100644
--- a/arch/x86/kernel/io_apic.c
+++ b/arch/x86/kernel/io_apic.c
@@ -1751,21 +1751,30 @@ __apicdebuginit(void) print_local_APIC(void *dummy)
         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 
         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
-                v = apic_read(APIC_ARBPRI);
-                printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
-                        v & APIC_ARBPRI_MASK);
+                if (!APIC_XAPIC(ver)) {
+                        v = apic_read(APIC_ARBPRI);
+                        printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
+                               v & APIC_ARBPRI_MASK);
+                }
                 v = apic_read(APIC_PROCPRI);
                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
         }
 
-        v = apic_read(APIC_EOI);
-        printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
-        v = apic_read(APIC_RRR);
-        printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
+        /*
+         * Remote read supported only in the 82489DX and local APIC for
+         * Pentium processors.
+         */
+        if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
+                v = apic_read(APIC_RRR);
+                printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
+        }
+
         v = apic_read(APIC_LDR);
         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
-        v = apic_read(APIC_DFR);
-        printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
+        if (!x2apic_enabled()) {
+                v = apic_read(APIC_DFR);
+                printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
+        }
         v = apic_read(APIC_SPIV);
         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
 
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
index 2d970f6bc2a1..ef1d72dbdfe0 100644
--- a/include/asm-x86/apic.h
+++ b/include/asm-x86/apic.h
@@ -98,6 +98,20 @@ extern void check_x2apic(void);
 extern void enable_x2apic(void);
 extern void enable_IR_x2apic(void);
 extern void x2apic_icr_write(u32 low, u32 id);
+static inline int x2apic_enabled(void)
+{
+        int msr, msr2;
+
+        if (!cpu_has_x2apic)
+                return 0;
+
+        rdmsr(MSR_IA32_APICBASE, msr, msr2);
+        if (msr & X2APIC_ENABLE)
+                return 1;
+        return 0;
+}
+#else
+#define x2apic_enabled()        0
 #endif
 
 struct apic_ops {