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-rw-r--r--arch/avr32/mach-at32ap/hsmc.c23
-rw-r--r--include/asm-avr32/arch-at32ap/smc.h22
2 files changed, 45 insertions, 0 deletions
diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
index 7691721928a7..5e22a750632b 100644
--- a/arch/avr32/mach-at32ap/hsmc.c
+++ b/arch/avr32/mach-at32ap/hsmc.c
@@ -75,12 +75,35 @@ int smc_set_configuration(int cs, const struct smc_config *config)
75 return -EINVAL; 75 return -EINVAL;
76 } 76 }
77 77
78 switch (config->nwait_mode) {
79 case 0:
80 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_DISABLED);
81 break;
82 case 1:
83 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_RESERVED);
84 break;
85 case 2:
86 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_FROZEN);
87 break;
88 case 3:
89 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_READY);
90 break;
91 default:
92 return -EINVAL;
93 }
94
95 if (config->tdf_cycles) {
96 mode |= HSMC_BF(TDF_CYCLES, config->tdf_cycles);
97 }
98
78 if (config->nrd_controlled) 99 if (config->nrd_controlled)
79 mode |= HSMC_BIT(READ_MODE); 100 mode |= HSMC_BIT(READ_MODE);
80 if (config->nwe_controlled) 101 if (config->nwe_controlled)
81 mode |= HSMC_BIT(WRITE_MODE); 102 mode |= HSMC_BIT(WRITE_MODE);
82 if (config->byte_write) 103 if (config->byte_write)
83 mode |= HSMC_BIT(BAT); 104 mode |= HSMC_BIT(BAT);
105 if (config->tdf_mode)
106 mode |= HSMC_BIT(TDF_MODE);
84 107
85 pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n", 108 pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n",
86 cs, setup, pulse, cycle, mode); 109 cs, setup, pulse, cycle, mode);
diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h
index 3732b328303d..07152b7fd9c9 100644
--- a/include/asm-avr32/arch-at32ap/smc.h
+++ b/include/asm-avr32/arch-at32ap/smc.h
@@ -48,10 +48,32 @@ struct smc_config {
48 unsigned int nwe_controlled:1; 48 unsigned int nwe_controlled:1;
49 49
50 /* 50 /*
51 * 0: NWAIT is disabled
52 * 1: Reserved
53 * 2: NWAIT is frozen mode
54 * 3: NWAIT in ready mode
55 */
56 unsigned int nwait_mode:2;
57
58 /*
51 * 0: Byte select access type 59 * 0: Byte select access type
52 * 1: Byte write access type 60 * 1: Byte write access type
53 */ 61 */
54 unsigned int byte_write:1; 62 unsigned int byte_write:1;
63
64 /*
65 * Number of clock cycles before data is released after
66 * the rising edge of the read controlling signal
67 *
68 * Total cycles from SMC is tdf_cycles + 1
69 */
70 unsigned int tdf_cycles:4;
71
72 /*
73 * 0: TDF optimization disabled
74 * 1: TDF optimization enabled
75 */
76 unsigned int tdf_mode:1;
55}; 77};
56 78
57extern int smc_set_configuration(int cs, const struct smc_config *config); 79extern int smc_set_configuration(int cs, const struct smc_config *config);