diff options
280 files changed, 13986 insertions, 5166 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 73883b8bbd76..d1c7be38b10a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -480,6 +480,12 @@ M: kernel@wantstofly.org | |||
| 480 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | 480 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) |
| 481 | S: Maintained | 481 | S: Maintained |
| 482 | 482 | ||
| 483 | ARM/GUMSTIX MACHINE SUPPORT | ||
| 484 | P: Steve Sakoman | ||
| 485 | M: sakoman@gmail.com | ||
| 486 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 487 | S: Maintained | ||
| 488 | |||
| 483 | ARM/HP JORNADA 7XX MACHINE SUPPORT | 489 | ARM/HP JORNADA 7XX MACHINE SUPPORT |
| 484 | P: Kristoffer Ericson | 490 | P: Kristoffer Ericson |
| 485 | M: kristoffer.ericson@gmail.com | 491 | M: kristoffer.ericson@gmail.com |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4039a133006e..ac1bef1797e6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -255,6 +255,7 @@ config ARCH_EP93XX | |||
| 255 | select ARM_AMBA | 255 | select ARM_AMBA |
| 256 | select ARM_VIC | 256 | select ARM_VIC |
| 257 | select GENERIC_GPIO | 257 | select GENERIC_GPIO |
| 258 | select HAVE_GPIO_LIB | ||
| 258 | help | 259 | help |
| 259 | This enables support for the Cirrus EP93xx series of CPUs. | 260 | This enables support for the Cirrus EP93xx series of CPUs. |
| 260 | 261 | ||
| @@ -377,15 +378,17 @@ config ARCH_MXC | |||
| 377 | help | 378 | help |
| 378 | Support for Freescale MXC/iMX-based family of processors | 379 | Support for Freescale MXC/iMX-based family of processors |
| 379 | 380 | ||
| 380 | config ARCH_ORION | 381 | config ARCH_ORION5X |
| 381 | bool "Marvell Orion" | 382 | bool "Marvell Orion" |
| 382 | depends on MMU | 383 | depends on MMU |
| 383 | select PCI | 384 | select PCI |
| 384 | select GENERIC_GPIO | 385 | select GENERIC_GPIO |
| 385 | select GENERIC_TIME | 386 | select GENERIC_TIME |
| 386 | select GENERIC_CLOCKEVENTS | 387 | select GENERIC_CLOCKEVENTS |
| 388 | select PLAT_ORION | ||
| 387 | help | 389 | help |
| 388 | Support for Marvell Orion System on Chip family. | 390 | Support for the following Marvell Orion 5x series SoCs: |
| 391 | Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) | ||
| 389 | 392 | ||
| 390 | config ARCH_PNX4008 | 393 | config ARCH_PNX4008 |
| 391 | bool "Philips Nexperia PNX4008 Mobile" | 394 | bool "Philips Nexperia PNX4008 Mobile" |
| @@ -422,10 +425,15 @@ config ARCH_SA1100 | |||
| 422 | bool "SA1100-based" | 425 | bool "SA1100-based" |
| 423 | select ISA | 426 | select ISA |
| 424 | select ARCH_DISCONTIGMEM_ENABLE | 427 | select ARCH_DISCONTIGMEM_ENABLE |
| 428 | select ARCH_SPARSEMEM_ENABLE | ||
| 429 | select ARCH_SELECT_MEMORY_MODEL | ||
| 425 | select ARCH_MTD_XIP | 430 | select ARCH_MTD_XIP |
| 426 | select GENERIC_GPIO | 431 | select GENERIC_GPIO |
| 427 | select GENERIC_TIME | 432 | select GENERIC_TIME |
| 433 | select GENERIC_CLOCKEVENTS | ||
| 434 | select TICK_ONESHOT | ||
| 428 | select HAVE_IDE | 435 | select HAVE_IDE |
| 436 | select HAVE_GPIO_LIB | ||
| 429 | help | 437 | help |
| 430 | Support for StrongARM 11x0 based boards. | 438 | Support for StrongARM 11x0 based boards. |
| 431 | 439 | ||
| @@ -516,7 +524,7 @@ source "arch/arm/mach-omap1/Kconfig" | |||
| 516 | 524 | ||
| 517 | source "arch/arm/mach-omap2/Kconfig" | 525 | source "arch/arm/mach-omap2/Kconfig" |
| 518 | 526 | ||
| 519 | source "arch/arm/mach-orion/Kconfig" | 527 | source "arch/arm/mach-orion5x/Kconfig" |
| 520 | 528 | ||
| 521 | source "arch/arm/plat-s3c24xx/Kconfig" | 529 | source "arch/arm/plat-s3c24xx/Kconfig" |
| 522 | source "arch/arm/plat-s3c/Kconfig" | 530 | source "arch/arm/plat-s3c/Kconfig" |
| @@ -563,6 +571,9 @@ config ARCH_ACORN | |||
| 563 | config PLAT_IOP | 571 | config PLAT_IOP |
| 564 | bool | 572 | bool |
| 565 | 573 | ||
| 574 | config PLAT_ORION | ||
| 575 | bool | ||
| 576 | |||
| 566 | source arch/arm/mm/Kconfig | 577 | source arch/arm/mm/Kconfig |
| 567 | 578 | ||
| 568 | config IWMMXT | 579 | config IWMMXT |
| @@ -650,7 +661,7 @@ source "kernel/time/Kconfig" | |||
| 650 | 661 | ||
| 651 | config SMP | 662 | config SMP |
| 652 | bool "Symmetric Multi-Processing (EXPERIMENTAL)" | 663 | bool "Symmetric Multi-Processing (EXPERIMENTAL)" |
| 653 | depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP | 664 | depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) |
| 654 | help | 665 | help |
| 655 | This enables support for systems with more than one CPU. If you have | 666 | This enables support for systems with more than one CPU. If you have |
| 656 | a system with only one CPU, like most personal computers, say N. If | 667 | a system with only one CPU, like most personal computers, say N. If |
| @@ -683,7 +694,7 @@ config HOTPLUG_CPU | |||
| 683 | 694 | ||
| 684 | config LOCAL_TIMERS | 695 | config LOCAL_TIMERS |
| 685 | bool "Use local timer interrupts" | 696 | bool "Use local timer interrupts" |
| 686 | depends on SMP && REALVIEW_EB_ARM11MP | 697 | depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) |
| 687 | default y | 698 | default y |
| 688 | help | 699 | help |
| 689 | Enable support for local timers on SMP platforms, rather then the | 700 | Enable support for local timers on SMP platforms, rather then the |
| @@ -774,6 +785,12 @@ config ARCH_DISCONTIGMEM_ENABLE | |||
| 774 | or have huge holes in the physical address space for other reasons. | 785 | or have huge holes in the physical address space for other reasons. |
| 775 | See <file:Documentation/vm/numa> for more. | 786 | See <file:Documentation/vm/numa> for more. |
| 776 | 787 | ||
| 788 | config ARCH_SPARSEMEM_ENABLE | ||
| 789 | bool | ||
| 790 | |||
| 791 | config ARCH_SELECT_MEMORY_MODEL | ||
| 792 | bool | ||
| 793 | |||
| 777 | config NODES_SHIFT | 794 | config NODES_SHIFT |
| 778 | int | 795 | int |
| 779 | default "4" if ARCH_LH7A40X | 796 | default "4" if ARCH_LH7A40X |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1a4649667ec8..e72db27e0ba0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -134,12 +134,11 @@ endif | |||
| 134 | machine-$(CONFIG_ARCH_PNX4008) := pnx4008 | 134 | machine-$(CONFIG_ARCH_PNX4008) := pnx4008 |
| 135 | machine-$(CONFIG_ARCH_NETX) := netx | 135 | machine-$(CONFIG_ARCH_NETX) := netx |
| 136 | machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx | 136 | machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx |
| 137 | textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 | ||
| 138 | machine-$(CONFIG_ARCH_DAVINCI) := davinci | 137 | machine-$(CONFIG_ARCH_DAVINCI) := davinci |
| 139 | machine-$(CONFIG_ARCH_KS8695) := ks8695 | 138 | machine-$(CONFIG_ARCH_KS8695) := ks8695 |
| 140 | incdir-$(CONFIG_ARCH_MXC) := mxc | 139 | incdir-$(CONFIG_ARCH_MXC) := mxc |
| 141 | machine-$(CONFIG_ARCH_MX3) := mx3 | 140 | machine-$(CONFIG_ARCH_MX3) := mx3 |
| 142 | machine-$(CONFIG_ARCH_ORION) := orion | 141 | machine-$(CONFIG_ARCH_ORION5X) := orion5x |
| 143 | machine-$(CONFIG_ARCH_MSM7X00A) := msm | 142 | machine-$(CONFIG_ARCH_MSM7X00A) := msm |
| 144 | 143 | ||
| 145 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 144 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
| @@ -185,6 +184,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ | |||
| 185 | 184 | ||
| 186 | # If we have a common platform directory, then include it in the build. | 185 | # If we have a common platform directory, then include it in the build. |
| 187 | core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ | 186 | core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ |
| 187 | core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/ | ||
| 188 | core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ | 188 | core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ |
| 189 | core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ | 189 | core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ |
| 190 | core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ | 190 | core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ |
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 25f12303b106..da226abce2d0 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile | |||
| @@ -61,9 +61,15 @@ endif | |||
| 61 | 61 | ||
| 62 | quiet_cmd_uimage = UIMAGE $@ | 62 | quiet_cmd_uimage = UIMAGE $@ |
| 63 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \ | 63 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \ |
| 64 | -C none -a $(ZRELADDR) -e $(ZRELADDR) \ | 64 | -C none -a $(LOADADDR) -e $(LOADADDR) \ |
| 65 | -n 'Linux-$(KERNELRELEASE)' -d $< $@ | 65 | -n 'Linux-$(KERNELRELEASE)' -d $< $@ |
| 66 | 66 | ||
| 67 | ifeq ($(CONFIG_ZBOOT_ROM),y) | ||
| 68 | $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT) | ||
| 69 | else | ||
| 70 | $(obj)/uImage: LOADADDR=$(ZRELADDR) | ||
| 71 | endif | ||
| 72 | |||
| 67 | $(obj)/uImage: $(obj)/zImage FORCE | 73 | $(obj)/uImage: $(obj)/zImage FORCE |
| 68 | $(call if_changed,uimage) | 74 | $(call if_changed,uimage) |
| 69 | @echo ' Image $@ is ready' | 75 | @echo ' Image $@ is ready' |
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 314ebd3a1d71..bc299b07a6fa 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/slab.h> | 16 | #include <linux/slab.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <asm/io.h> | 18 | #include <asm/io.h> |
| 19 | #include <asm/gpio.h> | ||
| 19 | #include <asm/hardware/scoop.h> | 20 | #include <asm/hardware/scoop.h> |
| 20 | 21 | ||
| 21 | /* PCMCIA to Scoop linkage | 22 | /* PCMCIA to Scoop linkage |
| @@ -30,10 +31,9 @@ | |||
| 30 | struct scoop_pcmcia_config *platform_scoop_config; | 31 | struct scoop_pcmcia_config *platform_scoop_config; |
| 31 | EXPORT_SYMBOL(platform_scoop_config); | 32 | EXPORT_SYMBOL(platform_scoop_config); |
| 32 | 33 | ||
| 33 | #define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr))) | ||
| 34 | |||
| 35 | struct scoop_dev { | 34 | struct scoop_dev { |
| 36 | void *base; | 35 | void __iomem *base; |
| 36 | struct gpio_chip gpio; | ||
| 37 | spinlock_t scoop_lock; | 37 | spinlock_t scoop_lock; |
| 38 | unsigned short suspend_clr; | 38 | unsigned short suspend_clr; |
| 39 | unsigned short suspend_set; | 39 | unsigned short suspend_set; |
| @@ -44,13 +44,84 @@ void reset_scoop(struct device *dev) | |||
| 44 | { | 44 | { |
| 45 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 45 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 46 | 46 | ||
| 47 | SCOOP_REG(sdev->base,SCOOP_MCR) = 0x0100; // 00 | 47 | iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00 |
| 48 | SCOOP_REG(sdev->base,SCOOP_CDR) = 0x0000; // 04 | 48 | iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04 |
| 49 | SCOOP_REG(sdev->base,SCOOP_CCR) = 0x0000; // 10 | 49 | iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10 |
| 50 | SCOOP_REG(sdev->base,SCOOP_IMR) = 0x0000; // 18 | 50 | iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18 |
| 51 | SCOOP_REG(sdev->base,SCOOP_IRM) = 0x00FF; // 14 | 51 | iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14 |
| 52 | SCOOP_REG(sdev->base,SCOOP_ISR) = 0x0000; // 1C | 52 | iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C |
| 53 | SCOOP_REG(sdev->base,SCOOP_IRM) = 0x0000; | 53 | iowrite16(0x0000, sdev->base + SCOOP_IRM); |
| 54 | } | ||
| 55 | |||
| 56 | static void __scoop_gpio_set(struct scoop_dev *sdev, | ||
| 57 | unsigned offset, int value) | ||
| 58 | { | ||
| 59 | unsigned short gpwr; | ||
| 60 | |||
| 61 | gpwr = ioread16(sdev->base + SCOOP_GPWR); | ||
| 62 | if (value) | ||
| 63 | gpwr |= 1 << (offset + 1); | ||
| 64 | else | ||
| 65 | gpwr &= ~(1 << (offset + 1)); | ||
| 66 | iowrite16(gpwr, sdev->base + SCOOP_GPWR); | ||
| 67 | } | ||
| 68 | |||
| 69 | static void scoop_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 70 | { | ||
| 71 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 72 | unsigned long flags; | ||
| 73 | |||
| 74 | spin_lock_irqsave(&sdev->scoop_lock, flags); | ||
| 75 | |||
| 76 | __scoop_gpio_set(sdev, offset, value); | ||
| 77 | |||
| 78 | spin_unlock_irqrestore(&sdev->scoop_lock, flags); | ||
| 79 | } | ||
| 80 | |||
| 81 | static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 82 | { | ||
| 83 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 84 | |||
| 85 | /* XXX: I'm usure, but it seems so */ | ||
| 86 | return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)); | ||
| 87 | } | ||
| 88 | |||
| 89 | static int scoop_gpio_direction_input(struct gpio_chip *chip, | ||
| 90 | unsigned offset) | ||
| 91 | { | ||
| 92 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 93 | unsigned long flags; | ||
| 94 | unsigned short gpcr; | ||
| 95 | |||
| 96 | spin_lock_irqsave(&sdev->scoop_lock, flags); | ||
| 97 | |||
| 98 | gpcr = ioread16(sdev->base + SCOOP_GPCR); | ||
| 99 | gpcr &= ~(1 << (offset + 1)); | ||
| 100 | iowrite16(gpcr, sdev->base + SCOOP_GPCR); | ||
| 101 | |||
| 102 | spin_unlock_irqrestore(&sdev->scoop_lock, flags); | ||
| 103 | |||
| 104 | return 0; | ||
| 105 | } | ||
| 106 | |||
| 107 | static int scoop_gpio_direction_output(struct gpio_chip *chip, | ||
| 108 | unsigned offset, int value) | ||
| 109 | { | ||
| 110 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 111 | unsigned long flags; | ||
| 112 | unsigned short gpcr; | ||
| 113 | |||
| 114 | spin_lock_irqsave(&sdev->scoop_lock, flags); | ||
| 115 | |||
| 116 | __scoop_gpio_set(sdev, offset, value); | ||
| 117 | |||
| 118 | gpcr = ioread16(sdev->base + SCOOP_GPCR); | ||
| 119 | gpcr |= 1 << (offset + 1); | ||
| 120 | iowrite16(gpcr, sdev->base + SCOOP_GPCR); | ||
| 121 | |||
| 122 | spin_unlock_irqrestore(&sdev->scoop_lock, flags); | ||
| 123 | |||
| 124 | return 0; | ||
| 54 | } | 125 | } |
| 55 | 126 | ||
| 56 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) | 127 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) |
| @@ -60,8 +131,8 @@ unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) | |||
| 60 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 131 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 61 | 132 | ||
| 62 | spin_lock_irqsave(&sdev->scoop_lock, flag); | 133 | spin_lock_irqsave(&sdev->scoop_lock, flag); |
| 63 | gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) | bit; | 134 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit; |
| 64 | SCOOP_REG(sdev->base, SCOOP_GPWR) = gpio_bit; | 135 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); |
| 65 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | 136 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); |
| 66 | 137 | ||
| 67 | return gpio_bit; | 138 | return gpio_bit; |
| @@ -74,8 +145,8 @@ unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit) | |||
| 74 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 145 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 75 | 146 | ||
| 76 | spin_lock_irqsave(&sdev->scoop_lock, flag); | 147 | spin_lock_irqsave(&sdev->scoop_lock, flag); |
| 77 | gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) & ~bit; | 148 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit; |
| 78 | SCOOP_REG(sdev->base,SCOOP_GPWR) = gpio_bit; | 149 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); |
| 79 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | 150 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); |
| 80 | 151 | ||
| 81 | return gpio_bit; | 152 | return gpio_bit; |
| @@ -87,13 +158,13 @@ EXPORT_SYMBOL(reset_scoop_gpio); | |||
| 87 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) | 158 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) |
| 88 | { | 159 | { |
| 89 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 160 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 90 | return SCOOP_REG(sdev->base,reg); | 161 | return ioread16(sdev->base + reg); |
| 91 | } | 162 | } |
| 92 | 163 | ||
| 93 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data) | 164 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data) |
| 94 | { | 165 | { |
| 95 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 166 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 96 | SCOOP_REG(sdev->base,reg)=data; | 167 | iowrite16(data, sdev->base + reg); |
| 97 | } | 168 | } |
| 98 | 169 | ||
| 99 | EXPORT_SYMBOL(reset_scoop); | 170 | EXPORT_SYMBOL(reset_scoop); |
| @@ -104,9 +175,9 @@ static void check_scoop_reg(struct scoop_dev *sdev) | |||
| 104 | { | 175 | { |
| 105 | unsigned short mcr; | 176 | unsigned short mcr; |
| 106 | 177 | ||
| 107 | mcr = SCOOP_REG(sdev->base, SCOOP_MCR); | 178 | mcr = ioread16(sdev->base + SCOOP_MCR); |
| 108 | if ((mcr & 0x100) == 0) | 179 | if ((mcr & 0x100) == 0) |
| 109 | SCOOP_REG(sdev->base, SCOOP_MCR) = 0x0101; | 180 | iowrite16(0x0101, sdev->base + SCOOP_MCR); |
| 110 | } | 181 | } |
| 111 | 182 | ||
| 112 | #ifdef CONFIG_PM | 183 | #ifdef CONFIG_PM |
| @@ -115,8 +186,8 @@ static int scoop_suspend(struct platform_device *dev, pm_message_t state) | |||
| 115 | struct scoop_dev *sdev = platform_get_drvdata(dev); | 186 | struct scoop_dev *sdev = platform_get_drvdata(dev); |
| 116 | 187 | ||
| 117 | check_scoop_reg(sdev); | 188 | check_scoop_reg(sdev); |
| 118 | sdev->scoop_gpwr = SCOOP_REG(sdev->base, SCOOP_GPWR); | 189 | sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR); |
| 119 | SCOOP_REG(sdev->base, SCOOP_GPWR) = (sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set; | 190 | iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR); |
| 120 | 191 | ||
| 121 | return 0; | 192 | return 0; |
| 122 | } | 193 | } |
| @@ -126,7 +197,7 @@ static int scoop_resume(struct platform_device *dev) | |||
| 126 | struct scoop_dev *sdev = platform_get_drvdata(dev); | 197 | struct scoop_dev *sdev = platform_get_drvdata(dev); |
| 127 | 198 | ||
| 128 | check_scoop_reg(sdev); | 199 | check_scoop_reg(sdev); |
| 129 | SCOOP_REG(sdev->base,SCOOP_GPWR) = sdev->scoop_gpwr; | 200 | iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR); |
| 130 | 201 | ||
| 131 | return 0; | 202 | return 0; |
| 132 | } | 203 | } |
| @@ -135,11 +206,13 @@ static int scoop_resume(struct platform_device *dev) | |||
| 135 | #define scoop_resume NULL | 206 | #define scoop_resume NULL |
| 136 | #endif | 207 | #endif |
| 137 | 208 | ||
| 138 | int __init scoop_probe(struct platform_device *pdev) | 209 | static int __devinit scoop_probe(struct platform_device *pdev) |
| 139 | { | 210 | { |
| 140 | struct scoop_dev *devptr; | 211 | struct scoop_dev *devptr; |
| 141 | struct scoop_config *inf; | 212 | struct scoop_config *inf; |
| 142 | struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 213 | struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 214 | int ret; | ||
| 215 | int temp; | ||
| 143 | 216 | ||
| 144 | if (!mem) | 217 | if (!mem) |
| 145 | return -EINVAL; | 218 | return -EINVAL; |
| @@ -154,40 +227,78 @@ int __init scoop_probe(struct platform_device *pdev) | |||
| 154 | devptr->base = ioremap(mem->start, mem->end - mem->start + 1); | 227 | devptr->base = ioremap(mem->start, mem->end - mem->start + 1); |
| 155 | 228 | ||
| 156 | if (!devptr->base) { | 229 | if (!devptr->base) { |
| 157 | kfree(devptr); | 230 | ret = -ENOMEM; |
| 158 | return -ENOMEM; | 231 | goto err_ioremap; |
| 159 | } | 232 | } |
| 160 | 233 | ||
| 161 | platform_set_drvdata(pdev, devptr); | 234 | platform_set_drvdata(pdev, devptr); |
| 162 | 235 | ||
| 163 | printk("Sharp Scoop Device found at 0x%08x -> 0x%08x\n",(unsigned int)mem->start,(unsigned int)devptr->base); | 236 | printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base); |
| 164 | 237 | ||
| 165 | SCOOP_REG(devptr->base, SCOOP_MCR) = 0x0140; | 238 | iowrite16(0x0140, devptr->base + SCOOP_MCR); |
| 166 | reset_scoop(&pdev->dev); | 239 | reset_scoop(&pdev->dev); |
| 167 | SCOOP_REG(devptr->base, SCOOP_CPR) = 0x0000; | 240 | iowrite16(0x0000, devptr->base + SCOOP_CPR); |
| 168 | SCOOP_REG(devptr->base, SCOOP_GPCR) = inf->io_dir & 0xffff; | 241 | iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR); |
| 169 | SCOOP_REG(devptr->base, SCOOP_GPWR) = inf->io_out & 0xffff; | 242 | iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR); |
| 170 | 243 | ||
| 171 | devptr->suspend_clr = inf->suspend_clr; | 244 | devptr->suspend_clr = inf->suspend_clr; |
| 172 | devptr->suspend_set = inf->suspend_set; | 245 | devptr->suspend_set = inf->suspend_set; |
| 173 | 246 | ||
| 247 | devptr->gpio.base = -1; | ||
| 248 | |||
| 249 | if (inf->gpio_base != 0) { | ||
| 250 | devptr->gpio.label = pdev->dev.bus_id; | ||
| 251 | devptr->gpio.base = inf->gpio_base; | ||
| 252 | devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */ | ||
| 253 | devptr->gpio.set = scoop_gpio_set; | ||
| 254 | devptr->gpio.get = scoop_gpio_get; | ||
| 255 | devptr->gpio.direction_input = scoop_gpio_direction_input; | ||
| 256 | devptr->gpio.direction_output = scoop_gpio_direction_output; | ||
| 257 | |||
| 258 | ret = gpiochip_add(&devptr->gpio); | ||
| 259 | if (ret) | ||
| 260 | goto err_gpio; | ||
| 261 | } | ||
| 262 | |||
| 174 | return 0; | 263 | return 0; |
| 264 | |||
| 265 | if (devptr->gpio.base != -1) | ||
| 266 | temp = gpiochip_remove(&devptr->gpio); | ||
| 267 | err_gpio: | ||
| 268 | platform_set_drvdata(pdev, NULL); | ||
| 269 | err_ioremap: | ||
| 270 | iounmap(devptr->base); | ||
| 271 | kfree(devptr); | ||
| 272 | |||
| 273 | return ret; | ||
| 175 | } | 274 | } |
| 176 | 275 | ||
| 177 | static int scoop_remove(struct platform_device *pdev) | 276 | static int __devexit scoop_remove(struct platform_device *pdev) |
| 178 | { | 277 | { |
| 179 | struct scoop_dev *sdev = platform_get_drvdata(pdev); | 278 | struct scoop_dev *sdev = platform_get_drvdata(pdev); |
| 180 | if (sdev) { | 279 | int ret; |
| 181 | iounmap(sdev->base); | 280 | |
| 182 | kfree(sdev); | 281 | if (!sdev) |
| 183 | platform_set_drvdata(pdev, NULL); | 282 | return -EINVAL; |
| 283 | |||
| 284 | if (sdev->gpio.base != -1) { | ||
| 285 | ret = gpiochip_remove(&sdev->gpio); | ||
| 286 | if (ret) { | ||
| 287 | dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret); | ||
| 288 | return ret; | ||
| 289 | } | ||
| 184 | } | 290 | } |
| 291 | |||
| 292 | platform_set_drvdata(pdev, NULL); | ||
| 293 | iounmap(sdev->base); | ||
| 294 | kfree(sdev); | ||
| 295 | |||
| 185 | return 0; | 296 | return 0; |
| 186 | } | 297 | } |
| 187 | 298 | ||
| 188 | static struct platform_driver scoop_driver = { | 299 | static struct platform_driver scoop_driver = { |
| 189 | .probe = scoop_probe, | 300 | .probe = scoop_probe, |
| 190 | .remove = scoop_remove, | 301 | .remove = __devexit_p(scoop_remove), |
| 191 | .suspend = scoop_suspend, | 302 | .suspend = scoop_suspend, |
| 192 | .resume = scoop_resume, | 303 | .resume = scoop_resume, |
| 193 | .driver = { | 304 | .driver = { |
| @@ -195,7 +306,7 @@ static struct platform_driver scoop_driver = { | |||
| 195 | }, | 306 | }, |
| 196 | }; | 307 | }; |
| 197 | 308 | ||
| 198 | int __init scoop_init(void) | 309 | static int __init scoop_init(void) |
| 199 | { | 310 | { |
| 200 | return platform_driver_register(&scoop_driver); | 311 | return platform_driver_register(&scoop_driver); |
| 201 | } | 312 | } |
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig new file mode 100644 index 000000000000..dc030cfe5009 --- /dev/null +++ b/arch/arm/configs/am200epdkit_defconfig | |||
| @@ -0,0 +1,1149 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.25-rc3 | ||
| 4 | # Sun Mar 9 06:33:33 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_ARCH_MTD_XIP=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_LOCK_KERNEL=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="gum" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | # CONFIG_POSIX_MQUEUE is not set | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | # CONFIG_IKCONFIG is not set | ||
| 47 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 48 | # CONFIG_CGROUPS is not set | ||
| 49 | CONFIG_GROUP_SCHED=y | ||
| 50 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 51 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 52 | CONFIG_USER_SCHED=y | ||
| 53 | # CONFIG_CGROUP_SCHED is not set | ||
| 54 | # CONFIG_SYSFS_DEPRECATED is not set | ||
| 55 | # CONFIG_RELAY is not set | ||
| 56 | # CONFIG_NAMESPACES is not set | ||
| 57 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 58 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 59 | CONFIG_SYSCTL=y | ||
| 60 | CONFIG_EMBEDDED=y | ||
| 61 | CONFIG_UID16=y | ||
| 62 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 63 | CONFIG_KALLSYMS=y | ||
| 64 | # CONFIG_KALLSYMS_ALL is not set | ||
| 65 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 66 | CONFIG_HOTPLUG=y | ||
| 67 | CONFIG_PRINTK=y | ||
| 68 | CONFIG_BUG=y | ||
| 69 | CONFIG_ELF_CORE=y | ||
| 70 | CONFIG_COMPAT_BRK=y | ||
| 71 | CONFIG_BASE_FULL=y | ||
| 72 | CONFIG_FUTEX=y | ||
| 73 | CONFIG_ANON_INODES=y | ||
| 74 | # CONFIG_EPOLL is not set | ||
| 75 | CONFIG_SIGNALFD=y | ||
| 76 | CONFIG_TIMERFD=y | ||
| 77 | CONFIG_EVENTFD=y | ||
| 78 | # CONFIG_SHMEM is not set | ||
| 79 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 80 | CONFIG_SLAB=y | ||
| 81 | # CONFIG_SLUB is not set | ||
| 82 | # CONFIG_SLOB is not set | ||
| 83 | # CONFIG_PROFILING is not set | ||
| 84 | # CONFIG_MARKERS is not set | ||
| 85 | CONFIG_HAVE_OPROFILE=y | ||
| 86 | # CONFIG_KPROBES is not set | ||
| 87 | CONFIG_HAVE_KPROBES=y | ||
| 88 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 89 | CONFIG_SLABINFO=y | ||
| 90 | CONFIG_RT_MUTEXES=y | ||
| 91 | CONFIG_TINY_SHMEM=y | ||
| 92 | CONFIG_BASE_SMALL=0 | ||
| 93 | CONFIG_MODULES=y | ||
| 94 | CONFIG_MODULE_UNLOAD=y | ||
| 95 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 96 | # CONFIG_MODVERSIONS is not set | ||
| 97 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 98 | CONFIG_KMOD=y | ||
| 99 | CONFIG_BLOCK=y | ||
| 100 | # CONFIG_LBD is not set | ||
| 101 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 102 | # CONFIG_LSF is not set | ||
| 103 | # CONFIG_BLK_DEV_BSG is not set | ||
| 104 | |||
| 105 | # | ||
| 106 | # IO Schedulers | ||
| 107 | # | ||
| 108 | CONFIG_IOSCHED_NOOP=y | ||
| 109 | # CONFIG_IOSCHED_AS is not set | ||
| 110 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 111 | # CONFIG_IOSCHED_CFQ is not set | ||
| 112 | # CONFIG_DEFAULT_AS is not set | ||
| 113 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 114 | # CONFIG_DEFAULT_CFQ is not set | ||
| 115 | CONFIG_DEFAULT_NOOP=y | ||
| 116 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 117 | CONFIG_CLASSIC_RCU=y | ||
| 118 | # CONFIG_PREEMPT_RCU is not set | ||
| 119 | |||
| 120 | # | ||
| 121 | # System Type | ||
| 122 | # | ||
| 123 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 124 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 125 | # CONFIG_ARCH_REALVIEW is not set | ||
| 126 | # CONFIG_ARCH_VERSATILE is not set | ||
| 127 | # CONFIG_ARCH_AT91 is not set | ||
| 128 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 129 | # CONFIG_ARCH_CLPS711X is not set | ||
| 130 | # CONFIG_ARCH_CO285 is not set | ||
| 131 | # CONFIG_ARCH_EBSA110 is not set | ||
| 132 | # CONFIG_ARCH_EP93XX is not set | ||
| 133 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 134 | # CONFIG_ARCH_NETX is not set | ||
| 135 | # CONFIG_ARCH_H720X is not set | ||
| 136 | # CONFIG_ARCH_IMX is not set | ||
| 137 | # CONFIG_ARCH_IOP13XX is not set | ||
| 138 | # CONFIG_ARCH_IOP32X is not set | ||
| 139 | # CONFIG_ARCH_IOP33X is not set | ||
| 140 | # CONFIG_ARCH_IXP23XX is not set | ||
| 141 | # CONFIG_ARCH_IXP2000 is not set | ||
| 142 | # CONFIG_ARCH_IXP4XX is not set | ||
| 143 | # CONFIG_ARCH_L7200 is not set | ||
| 144 | # CONFIG_ARCH_KS8695 is not set | ||
| 145 | # CONFIG_ARCH_NS9XXX is not set | ||
| 146 | # CONFIG_ARCH_MXC is not set | ||
| 147 | # CONFIG_ARCH_ORION is not set | ||
| 148 | # CONFIG_ARCH_PNX4008 is not set | ||
| 149 | CONFIG_ARCH_PXA=y | ||
| 150 | # CONFIG_ARCH_RPC is not set | ||
| 151 | # CONFIG_ARCH_SA1100 is not set | ||
| 152 | # CONFIG_ARCH_S3C2410 is not set | ||
| 153 | # CONFIG_ARCH_SHARK is not set | ||
| 154 | # CONFIG_ARCH_LH7A40X is not set | ||
| 155 | # CONFIG_ARCH_DAVINCI is not set | ||
| 156 | # CONFIG_ARCH_OMAP is not set | ||
| 157 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 158 | |||
| 159 | # | ||
| 160 | # Intel PXA2xx/PXA3xx Implementations | ||
| 161 | # | ||
| 162 | CONFIG_ARCH_GUMSTIX=y | ||
| 163 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 164 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 165 | # CONFIG_MACH_MAINSTONE is not set | ||
| 166 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 167 | # CONFIG_PXA_SHARPSL is not set | ||
| 168 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 169 | # CONFIG_MACH_TRIZEPS4 is not set | ||
| 170 | # CONFIG_MACH_EM_X270 is not set | ||
| 171 | # CONFIG_MACH_COLIBRI is not set | ||
| 172 | # CONFIG_MACH_ZYLONITE is not set | ||
| 173 | # CONFIG_MACH_LITTLETON is not set | ||
| 174 | # CONFIG_MACH_ARMCORE is not set | ||
| 175 | # CONFIG_MACH_MAGICIAN is not set | ||
| 176 | # CONFIG_MACH_PCM027 is not set | ||
| 177 | CONFIG_MACH_GUMSTIX_F=y | ||
| 178 | CONFIG_PXA25x=y | ||
| 179 | |||
| 180 | # | ||
| 181 | # Boot options | ||
| 182 | # | ||
| 183 | |||
| 184 | # | ||
| 185 | # Power management | ||
| 186 | # | ||
| 187 | |||
| 188 | # | ||
| 189 | # Processor Type | ||
| 190 | # | ||
| 191 | CONFIG_CPU_32=y | ||
| 192 | CONFIG_CPU_XSCALE=y | ||
| 193 | CONFIG_CPU_32v5=y | ||
| 194 | CONFIG_CPU_ABRT_EV5T=y | ||
| 195 | CONFIG_CPU_CACHE_VIVT=y | ||
| 196 | CONFIG_CPU_TLB_V4WBI=y | ||
| 197 | CONFIG_CPU_CP15=y | ||
| 198 | CONFIG_CPU_CP15_MMU=y | ||
| 199 | |||
| 200 | # | ||
| 201 | # Processor Features | ||
| 202 | # | ||
| 203 | CONFIG_ARM_THUMB=y | ||
| 204 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 205 | # CONFIG_OUTER_CACHE is not set | ||
| 206 | # CONFIG_IWMMXT is not set | ||
| 207 | CONFIG_XSCALE_PMU=y | ||
| 208 | |||
| 209 | # | ||
| 210 | # Bus support | ||
| 211 | # | ||
| 212 | # CONFIG_PCI_SYSCALL is not set | ||
| 213 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 214 | CONFIG_PCCARD=y | ||
| 215 | # CONFIG_PCMCIA_DEBUG is not set | ||
| 216 | CONFIG_PCMCIA=y | ||
| 217 | CONFIG_PCMCIA_LOAD_CIS=y | ||
| 218 | # CONFIG_PCMCIA_IOCTL is not set | ||
| 219 | |||
| 220 | # | ||
| 221 | # PC-card bridges | ||
| 222 | # | ||
| 223 | CONFIG_PCMCIA_PXA2XX=y | ||
| 224 | |||
| 225 | # | ||
| 226 | # Kernel Features | ||
| 227 | # | ||
| 228 | CONFIG_TICK_ONESHOT=y | ||
| 229 | # CONFIG_NO_HZ is not set | ||
| 230 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 231 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 232 | CONFIG_PREEMPT=y | ||
| 233 | CONFIG_HZ=100 | ||
| 234 | CONFIG_AEABI=y | ||
| 235 | # CONFIG_OABI_COMPAT is not set | ||
| 236 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 237 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 238 | CONFIG_FLATMEM_MANUAL=y | ||
| 239 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 240 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 241 | CONFIG_FLATMEM=y | ||
| 242 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 243 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 244 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 245 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 246 | # CONFIG_RESOURCES_64BIT is not set | ||
| 247 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 248 | CONFIG_BOUNCE=y | ||
| 249 | CONFIG_VIRT_TO_BUS=y | ||
| 250 | CONFIG_ALIGNMENT_TRAP=y | ||
| 251 | |||
| 252 | # | ||
| 253 | # Boot options | ||
| 254 | # | ||
| 255 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 256 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 257 | CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2" | ||
| 258 | # CONFIG_XIP_KERNEL is not set | ||
| 259 | # CONFIG_KEXEC is not set | ||
| 260 | |||
| 261 | # | ||
| 262 | # CPU Frequency scaling | ||
| 263 | # | ||
| 264 | # CONFIG_CPU_FREQ is not set | ||
| 265 | |||
| 266 | # | ||
| 267 | # Floating point emulation | ||
| 268 | # | ||
| 269 | |||
| 270 | # | ||
| 271 | # At least one emulation must be selected | ||
| 272 | # | ||
| 273 | |||
| 274 | # | ||
| 275 | # Userspace binary formats | ||
| 276 | # | ||
| 277 | CONFIG_BINFMT_ELF=y | ||
| 278 | # CONFIG_BINFMT_AOUT is not set | ||
| 279 | # CONFIG_BINFMT_MISC is not set | ||
| 280 | |||
| 281 | # | ||
| 282 | # Power management options | ||
| 283 | # | ||
| 284 | # CONFIG_PM is not set | ||
| 285 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 286 | |||
| 287 | # | ||
| 288 | # Networking | ||
| 289 | # | ||
| 290 | CONFIG_NET=y | ||
| 291 | |||
| 292 | # | ||
| 293 | # Networking options | ||
| 294 | # | ||
| 295 | CONFIG_PACKET=m | ||
| 296 | CONFIG_PACKET_MMAP=y | ||
| 297 | CONFIG_UNIX=y | ||
| 298 | # CONFIG_NET_KEY is not set | ||
| 299 | CONFIG_INET=y | ||
| 300 | # CONFIG_IP_MULTICAST is not set | ||
| 301 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 302 | CONFIG_IP_FIB_HASH=y | ||
| 303 | # CONFIG_IP_PNP is not set | ||
| 304 | # CONFIG_NET_IPIP is not set | ||
| 305 | # CONFIG_NET_IPGRE is not set | ||
| 306 | # CONFIG_ARPD is not set | ||
| 307 | # CONFIG_SYN_COOKIES is not set | ||
| 308 | # CONFIG_INET_AH is not set | ||
| 309 | # CONFIG_INET_ESP is not set | ||
| 310 | # CONFIG_INET_IPCOMP is not set | ||
| 311 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 312 | # CONFIG_INET_TUNNEL is not set | ||
| 313 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 314 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 315 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 316 | # CONFIG_INET_LRO is not set | ||
| 317 | # CONFIG_INET_DIAG is not set | ||
| 318 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 319 | CONFIG_TCP_CONG_CUBIC=y | ||
| 320 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 321 | # CONFIG_TCP_MD5SIG is not set | ||
| 322 | # CONFIG_IPV6 is not set | ||
| 323 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 324 | # CONFIG_INET6_TUNNEL is not set | ||
| 325 | # CONFIG_NETWORK_SECMARK is not set | ||
| 326 | # CONFIG_NETFILTER is not set | ||
| 327 | # CONFIG_IP_DCCP is not set | ||
| 328 | # CONFIG_IP_SCTP is not set | ||
| 329 | # CONFIG_TIPC is not set | ||
| 330 | # CONFIG_ATM is not set | ||
| 331 | # CONFIG_BRIDGE is not set | ||
| 332 | # CONFIG_VLAN_8021Q is not set | ||
| 333 | # CONFIG_DECNET is not set | ||
| 334 | # CONFIG_LLC2 is not set | ||
| 335 | # CONFIG_IPX is not set | ||
| 336 | # CONFIG_ATALK is not set | ||
| 337 | # CONFIG_X25 is not set | ||
| 338 | # CONFIG_LAPB is not set | ||
| 339 | # CONFIG_ECONET is not set | ||
| 340 | # CONFIG_WAN_ROUTER is not set | ||
| 341 | # CONFIG_NET_SCHED is not set | ||
| 342 | |||
| 343 | # | ||
| 344 | # Network testing | ||
| 345 | # | ||
| 346 | # CONFIG_NET_PKTGEN is not set | ||
| 347 | # CONFIG_HAMRADIO is not set | ||
| 348 | # CONFIG_CAN is not set | ||
| 349 | # CONFIG_IRDA is not set | ||
| 350 | CONFIG_BT=m | ||
| 351 | CONFIG_BT_L2CAP=m | ||
| 352 | CONFIG_BT_SCO=m | ||
| 353 | CONFIG_BT_RFCOMM=m | ||
| 354 | CONFIG_BT_RFCOMM_TTY=y | ||
| 355 | CONFIG_BT_BNEP=m | ||
| 356 | # CONFIG_BT_BNEP_MC_FILTER is not set | ||
| 357 | # CONFIG_BT_BNEP_PROTO_FILTER is not set | ||
| 358 | # CONFIG_BT_HIDP is not set | ||
| 359 | |||
| 360 | # | ||
| 361 | # Bluetooth device drivers | ||
| 362 | # | ||
| 363 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 364 | CONFIG_BT_HCIUART=m | ||
| 365 | CONFIG_BT_HCIUART_H4=y | ||
| 366 | # CONFIG_BT_HCIUART_BCSP is not set | ||
| 367 | # CONFIG_BT_HCIUART_LL is not set | ||
| 368 | # CONFIG_BT_HCIDTL1 is not set | ||
| 369 | # CONFIG_BT_HCIBT3C is not set | ||
| 370 | # CONFIG_BT_HCIBLUECARD is not set | ||
| 371 | # CONFIG_BT_HCIBTUART is not set | ||
| 372 | # CONFIG_BT_HCIVHCI is not set | ||
| 373 | # CONFIG_AF_RXRPC is not set | ||
| 374 | |||
| 375 | # | ||
| 376 | # Wireless | ||
| 377 | # | ||
| 378 | # CONFIG_CFG80211 is not set | ||
| 379 | CONFIG_WIRELESS_EXT=y | ||
| 380 | # CONFIG_MAC80211 is not set | ||
| 381 | CONFIG_IEEE80211=m | ||
| 382 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 383 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
| 384 | # CONFIG_IEEE80211_CRYPT_CCMP is not set | ||
| 385 | # CONFIG_IEEE80211_CRYPT_TKIP is not set | ||
| 386 | # CONFIG_IEEE80211_SOFTMAC is not set | ||
| 387 | # CONFIG_RFKILL is not set | ||
| 388 | # CONFIG_NET_9P is not set | ||
| 389 | |||
| 390 | # | ||
| 391 | # Device Drivers | ||
| 392 | # | ||
| 393 | |||
| 394 | # | ||
| 395 | # Generic Driver Options | ||
| 396 | # | ||
| 397 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 398 | CONFIG_STANDALONE=y | ||
| 399 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 400 | CONFIG_FW_LOADER=y | ||
| 401 | # CONFIG_DEBUG_DRIVER is not set | ||
| 402 | # CONFIG_DEBUG_DEVRES is not set | ||
| 403 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 404 | # CONFIG_CONNECTOR is not set | ||
| 405 | CONFIG_MTD=y | ||
| 406 | # CONFIG_MTD_DEBUG is not set | ||
| 407 | # CONFIG_MTD_CONCAT is not set | ||
| 408 | CONFIG_MTD_PARTITIONS=y | ||
| 409 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 410 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 411 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 412 | |||
| 413 | # | ||
| 414 | # User Modules And Translation Layers | ||
| 415 | # | ||
| 416 | CONFIG_MTD_CHAR=y | ||
| 417 | CONFIG_MTD_BLKDEVS=y | ||
| 418 | CONFIG_MTD_BLOCK=y | ||
| 419 | # CONFIG_FTL is not set | ||
| 420 | # CONFIG_NFTL is not set | ||
| 421 | # CONFIG_INFTL is not set | ||
| 422 | # CONFIG_RFD_FTL is not set | ||
| 423 | # CONFIG_SSFDC is not set | ||
| 424 | # CONFIG_MTD_OOPS is not set | ||
| 425 | |||
| 426 | # | ||
| 427 | # RAM/ROM/Flash chip drivers | ||
| 428 | # | ||
| 429 | CONFIG_MTD_CFI=y | ||
| 430 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 431 | CONFIG_MTD_GEN_PROBE=y | ||
| 432 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 433 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 434 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 435 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 436 | CONFIG_MTD_CFI_GEOMETRY=y | ||
| 437 | # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set | ||
| 438 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 439 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | ||
| 440 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 441 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 442 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 443 | CONFIG_MTD_CFI_I1=y | ||
| 444 | # CONFIG_MTD_CFI_I2 is not set | ||
| 445 | # CONFIG_MTD_CFI_I4 is not set | ||
| 446 | # CONFIG_MTD_CFI_I8 is not set | ||
| 447 | # CONFIG_MTD_OTP is not set | ||
| 448 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 449 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 450 | # CONFIG_MTD_CFI_STAA is not set | ||
| 451 | CONFIG_MTD_CFI_UTIL=y | ||
| 452 | # CONFIG_MTD_RAM is not set | ||
| 453 | # CONFIG_MTD_ROM is not set | ||
| 454 | # CONFIG_MTD_ABSENT is not set | ||
| 455 | # CONFIG_MTD_XIP is not set | ||
| 456 | |||
| 457 | # | ||
| 458 | # Mapping drivers for chip access | ||
| 459 | # | ||
| 460 | CONFIG_MTD_COMPLEX_MAPPINGS=y | ||
| 461 | # CONFIG_MTD_PHYSMAP is not set | ||
| 462 | CONFIG_MTD_PXA2XX=y | ||
| 463 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 464 | # CONFIG_MTD_SHARP_SL is not set | ||
| 465 | # CONFIG_MTD_PLATRAM is not set | ||
| 466 | |||
| 467 | # | ||
| 468 | # Self-contained MTD device drivers | ||
| 469 | # | ||
| 470 | # CONFIG_MTD_SLRAM is not set | ||
| 471 | # CONFIG_MTD_PHRAM is not set | ||
| 472 | # CONFIG_MTD_MTDRAM is not set | ||
| 473 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Disk-On-Chip Device Drivers | ||
| 477 | # | ||
| 478 | # CONFIG_MTD_DOC2000 is not set | ||
| 479 | # CONFIG_MTD_DOC2001 is not set | ||
| 480 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 481 | # CONFIG_MTD_NAND is not set | ||
| 482 | # CONFIG_MTD_ONENAND is not set | ||
| 483 | |||
| 484 | # | ||
| 485 | # UBI - Unsorted block images | ||
| 486 | # | ||
| 487 | # CONFIG_MTD_UBI is not set | ||
| 488 | # CONFIG_PARPORT is not set | ||
| 489 | CONFIG_BLK_DEV=y | ||
| 490 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 491 | CONFIG_BLK_DEV_LOOP=m | ||
| 492 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 493 | # CONFIG_BLK_DEV_NBD is not set | ||
| 494 | # CONFIG_BLK_DEV_RAM is not set | ||
| 495 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 496 | # CONFIG_ATA_OVER_ETH is not set | ||
| 497 | CONFIG_MISC_DEVICES=y | ||
| 498 | # CONFIG_EEPROM_93CX6 is not set | ||
| 499 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 500 | CONFIG_HAVE_IDE=y | ||
| 501 | CONFIG_IDE=m | ||
| 502 | CONFIG_IDE_MAX_HWIFS=2 | ||
| 503 | CONFIG_BLK_DEV_IDE=m | ||
| 504 | |||
| 505 | # | ||
| 506 | # Please see Documentation/ide.txt for help/info on IDE drives | ||
| 507 | # | ||
| 508 | # CONFIG_BLK_DEV_IDE_SATA is not set | ||
| 509 | CONFIG_BLK_DEV_IDEDISK=m | ||
| 510 | # CONFIG_IDEDISK_MULTI_MODE is not set | ||
| 511 | CONFIG_BLK_DEV_IDECS=m | ||
| 512 | # CONFIG_BLK_DEV_IDECD is not set | ||
| 513 | # CONFIG_BLK_DEV_IDETAPE is not set | ||
| 514 | # CONFIG_BLK_DEV_IDEFLOPPY is not set | ||
| 515 | # CONFIG_IDE_TASK_IOCTL is not set | ||
| 516 | CONFIG_IDE_PROC_FS=y | ||
| 517 | |||
| 518 | # | ||
| 519 | # IDE chipset support/bugfixes | ||
| 520 | # | ||
| 521 | CONFIG_IDE_GENERIC=m | ||
| 522 | # CONFIG_BLK_DEV_PLATFORM is not set | ||
| 523 | # CONFIG_BLK_DEV_IDEDMA is not set | ||
| 524 | CONFIG_IDE_ARCH_OBSOLETE_INIT=y | ||
| 525 | # CONFIG_BLK_DEV_HD is not set | ||
| 526 | |||
| 527 | # | ||
| 528 | # SCSI device support | ||
| 529 | # | ||
| 530 | # CONFIG_RAID_ATTRS is not set | ||
| 531 | # CONFIG_SCSI is not set | ||
| 532 | # CONFIG_SCSI_DMA is not set | ||
| 533 | # CONFIG_SCSI_NETLINK is not set | ||
| 534 | # CONFIG_ATA is not set | ||
| 535 | # CONFIG_MD is not set | ||
| 536 | CONFIG_NETDEVICES=y | ||
| 537 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 538 | # CONFIG_DUMMY is not set | ||
| 539 | # CONFIG_BONDING is not set | ||
| 540 | # CONFIG_MACVLAN is not set | ||
| 541 | # CONFIG_EQUALIZER is not set | ||
| 542 | # CONFIG_TUN is not set | ||
| 543 | # CONFIG_VETH is not set | ||
| 544 | # CONFIG_PHYLIB is not set | ||
| 545 | CONFIG_NET_ETHERNET=y | ||
| 546 | CONFIG_MII=m | ||
| 547 | # CONFIG_AX88796 is not set | ||
| 548 | CONFIG_SMC91X=m | ||
| 549 | # CONFIG_DM9000 is not set | ||
| 550 | # CONFIG_SMC911X is not set | ||
| 551 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 552 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 553 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 554 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 555 | # CONFIG_B44 is not set | ||
| 556 | CONFIG_NETDEV_1000=y | ||
| 557 | # CONFIG_E1000E_ENABLED is not set | ||
| 558 | CONFIG_NETDEV_10000=y | ||
| 559 | |||
| 560 | # | ||
| 561 | # Wireless LAN | ||
| 562 | # | ||
| 563 | # CONFIG_WLAN_PRE80211 is not set | ||
| 564 | # CONFIG_WLAN_80211 is not set | ||
| 565 | # CONFIG_NET_PCMCIA is not set | ||
| 566 | # CONFIG_WAN is not set | ||
| 567 | # CONFIG_PPP is not set | ||
| 568 | # CONFIG_SLIP is not set | ||
| 569 | # CONFIG_NETCONSOLE is not set | ||
| 570 | # CONFIG_NETPOLL is not set | ||
| 571 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 572 | # CONFIG_ISDN is not set | ||
| 573 | |||
| 574 | # | ||
| 575 | # Input device support | ||
| 576 | # | ||
| 577 | CONFIG_INPUT=y | ||
| 578 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 579 | # CONFIG_INPUT_POLLDEV is not set | ||
| 580 | |||
| 581 | # | ||
| 582 | # Userland interfaces | ||
| 583 | # | ||
| 584 | CONFIG_INPUT_MOUSEDEV=y | ||
| 585 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 586 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 587 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 588 | # CONFIG_INPUT_JOYDEV is not set | ||
| 589 | # CONFIG_INPUT_EVDEV is not set | ||
| 590 | # CONFIG_INPUT_EVBUG is not set | ||
| 591 | |||
| 592 | # | ||
| 593 | # Input Device Drivers | ||
| 594 | # | ||
| 595 | CONFIG_INPUT_KEYBOARD=y | ||
| 596 | CONFIG_KEYBOARD_ATKBD=y | ||
| 597 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 598 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 599 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 600 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 601 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 602 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 603 | CONFIG_INPUT_MOUSE=y | ||
| 604 | CONFIG_MOUSE_PS2=y | ||
| 605 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 606 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 607 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 608 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 609 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 610 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 611 | # CONFIG_MOUSE_SERIAL is not set | ||
| 612 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 613 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 614 | # CONFIG_MOUSE_GPIO is not set | ||
| 615 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 616 | # CONFIG_INPUT_TABLET is not set | ||
| 617 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 618 | # CONFIG_INPUT_MISC is not set | ||
| 619 | |||
| 620 | # | ||
| 621 | # Hardware I/O ports | ||
| 622 | # | ||
| 623 | CONFIG_SERIO=y | ||
| 624 | CONFIG_SERIO_SERPORT=y | ||
| 625 | CONFIG_SERIO_LIBPS2=y | ||
| 626 | # CONFIG_SERIO_RAW is not set | ||
| 627 | # CONFIG_GAMEPORT is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # Character devices | ||
| 631 | # | ||
| 632 | CONFIG_VT=y | ||
| 633 | CONFIG_VT_CONSOLE=y | ||
| 634 | CONFIG_HW_CONSOLE=y | ||
| 635 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 636 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Serial drivers | ||
| 640 | # | ||
| 641 | # CONFIG_SERIAL_8250 is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # Non-8250 serial port support | ||
| 645 | # | ||
| 646 | CONFIG_SERIAL_PXA=y | ||
| 647 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 648 | CONFIG_SERIAL_CORE=y | ||
| 649 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 650 | CONFIG_UNIX98_PTYS=y | ||
| 651 | # CONFIG_LEGACY_PTYS is not set | ||
| 652 | # CONFIG_IPMI_HANDLER is not set | ||
| 653 | # CONFIG_HW_RANDOM is not set | ||
| 654 | # CONFIG_NVRAM is not set | ||
| 655 | # CONFIG_R3964 is not set | ||
| 656 | |||
| 657 | # | ||
| 658 | # PCMCIA character devices | ||
| 659 | # | ||
| 660 | # CONFIG_SYNCLINK_CS is not set | ||
| 661 | # CONFIG_CARDMAN_4000 is not set | ||
| 662 | # CONFIG_CARDMAN_4040 is not set | ||
| 663 | # CONFIG_IPWIRELESS is not set | ||
| 664 | # CONFIG_RAW_DRIVER is not set | ||
| 665 | # CONFIG_TCG_TPM is not set | ||
| 666 | # CONFIG_I2C is not set | ||
| 667 | |||
| 668 | # | ||
| 669 | # SPI support | ||
| 670 | # | ||
| 671 | # CONFIG_SPI is not set | ||
| 672 | # CONFIG_SPI_MASTER is not set | ||
| 673 | CONFIG_HAVE_GPIO_LIB=y | ||
| 674 | |||
| 675 | # | ||
| 676 | # GPIO Support | ||
| 677 | # | ||
| 678 | # CONFIG_DEBUG_GPIO is not set | ||
| 679 | |||
| 680 | # | ||
| 681 | # I2C GPIO expanders: | ||
| 682 | # | ||
| 683 | |||
| 684 | # | ||
| 685 | # SPI GPIO expanders: | ||
| 686 | # | ||
| 687 | # CONFIG_W1 is not set | ||
| 688 | # CONFIG_POWER_SUPPLY is not set | ||
| 689 | # CONFIG_HWMON is not set | ||
| 690 | CONFIG_WATCHDOG=y | ||
| 691 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 692 | |||
| 693 | # | ||
| 694 | # Watchdog Device Drivers | ||
| 695 | # | ||
| 696 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 697 | CONFIG_SA1100_WATCHDOG=m | ||
| 698 | |||
| 699 | # | ||
| 700 | # Sonics Silicon Backplane | ||
| 701 | # | ||
| 702 | CONFIG_SSB_POSSIBLE=y | ||
| 703 | # CONFIG_SSB is not set | ||
| 704 | |||
| 705 | # | ||
| 706 | # Multifunction device drivers | ||
| 707 | # | ||
| 708 | # CONFIG_MFD_SM501 is not set | ||
| 709 | # CONFIG_MFD_ASIC3 is not set | ||
| 710 | |||
| 711 | # | ||
| 712 | # Multimedia devices | ||
| 713 | # | ||
| 714 | # CONFIG_VIDEO_DEV is not set | ||
| 715 | # CONFIG_DVB_CORE is not set | ||
| 716 | CONFIG_DAB=y | ||
| 717 | |||
| 718 | # | ||
| 719 | # Graphics support | ||
| 720 | # | ||
| 721 | # CONFIG_VGASTATE is not set | ||
| 722 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 723 | CONFIG_FB=y | ||
| 724 | # CONFIG_FIRMWARE_EDID is not set | ||
| 725 | # CONFIG_FB_DDC is not set | ||
| 726 | CONFIG_FB_CFB_FILLRECT=y | ||
| 727 | CONFIG_FB_CFB_COPYAREA=y | ||
| 728 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 729 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 730 | CONFIG_FB_SYS_FILLRECT=m | ||
| 731 | CONFIG_FB_SYS_COPYAREA=m | ||
| 732 | CONFIG_FB_SYS_IMAGEBLIT=m | ||
| 733 | CONFIG_FB_SYS_FOPS=m | ||
| 734 | CONFIG_FB_DEFERRED_IO=y | ||
| 735 | # CONFIG_FB_SVGALIB is not set | ||
| 736 | # CONFIG_FB_MACMODES is not set | ||
| 737 | # CONFIG_FB_BACKLIGHT is not set | ||
| 738 | CONFIG_FB_MODE_HELPERS=y | ||
| 739 | CONFIG_FB_TILEBLITTING=y | ||
| 740 | |||
| 741 | # | ||
| 742 | # Frame buffer hardware drivers | ||
| 743 | # | ||
| 744 | # CONFIG_FB_S1D13XXX is not set | ||
| 745 | CONFIG_FB_PXA=y | ||
| 746 | CONFIG_FB_PXA_PARAMETERS=y | ||
| 747 | CONFIG_FB_MBX=m | ||
| 748 | CONFIG_FB_VIRTUAL=m | ||
| 749 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 750 | |||
| 751 | # | ||
| 752 | # Display device support | ||
| 753 | # | ||
| 754 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 755 | |||
| 756 | # | ||
| 757 | # Console display driver support | ||
| 758 | # | ||
| 759 | # CONFIG_VGA_CONSOLE is not set | ||
| 760 | CONFIG_DUMMY_CONSOLE=y | ||
| 761 | # CONFIG_FRAMEBUFFER_CONSOLE is not set | ||
| 762 | # CONFIG_LOGO is not set | ||
| 763 | |||
| 764 | # | ||
| 765 | # Sound | ||
| 766 | # | ||
| 767 | CONFIG_SOUND=m | ||
| 768 | |||
| 769 | # | ||
| 770 | # Advanced Linux Sound Architecture | ||
| 771 | # | ||
| 772 | CONFIG_SND=m | ||
| 773 | CONFIG_SND_TIMER=m | ||
| 774 | CONFIG_SND_PCM=m | ||
| 775 | # CONFIG_SND_SEQUENCER is not set | ||
| 776 | CONFIG_SND_OSSEMUL=y | ||
| 777 | CONFIG_SND_MIXER_OSS=m | ||
| 778 | CONFIG_SND_PCM_OSS=m | ||
| 779 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 780 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 781 | # CONFIG_SND_SUPPORT_OLD_API is not set | ||
| 782 | # CONFIG_SND_VERBOSE_PROCFS is not set | ||
| 783 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 784 | # CONFIG_SND_DEBUG is not set | ||
| 785 | |||
| 786 | # | ||
| 787 | # Generic devices | ||
| 788 | # | ||
| 789 | CONFIG_SND_AC97_CODEC=m | ||
| 790 | # CONFIG_SND_DUMMY is not set | ||
| 791 | # CONFIG_SND_MTPAV is not set | ||
| 792 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 793 | # CONFIG_SND_MPU401 is not set | ||
| 794 | |||
| 795 | # | ||
| 796 | # ALSA ARM devices | ||
| 797 | # | ||
| 798 | CONFIG_SND_PXA2XX_PCM=m | ||
| 799 | CONFIG_SND_PXA2XX_AC97=m | ||
| 800 | |||
| 801 | # | ||
| 802 | # PCMCIA devices | ||
| 803 | # | ||
| 804 | # CONFIG_SND_VXPOCKET is not set | ||
| 805 | # CONFIG_SND_PDAUDIOCF is not set | ||
| 806 | |||
| 807 | # | ||
| 808 | # System on Chip audio support | ||
| 809 | # | ||
| 810 | # CONFIG_SND_SOC is not set | ||
| 811 | |||
| 812 | # | ||
| 813 | # SoC Audio support for SuperH | ||
| 814 | # | ||
| 815 | |||
| 816 | # | ||
| 817 | # ALSA SoC audio for Freescale SOCs | ||
| 818 | # | ||
| 819 | |||
| 820 | # | ||
| 821 | # Open Sound System | ||
| 822 | # | ||
| 823 | # CONFIG_SOUND_PRIME is not set | ||
| 824 | CONFIG_AC97_BUS=m | ||
| 825 | CONFIG_HID_SUPPORT=y | ||
| 826 | CONFIG_HID=y | ||
| 827 | # CONFIG_HID_DEBUG is not set | ||
| 828 | # CONFIG_HIDRAW is not set | ||
| 829 | CONFIG_USB_SUPPORT=y | ||
| 830 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 831 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
| 832 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 833 | # CONFIG_USB is not set | ||
| 834 | |||
| 835 | # | ||
| 836 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 837 | # | ||
| 838 | CONFIG_USB_GADGET=y | ||
| 839 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 840 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 841 | CONFIG_USB_GADGET_SELECTED=y | ||
| 842 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 843 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 844 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 845 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 846 | CONFIG_USB_GADGET_PXA2XX=y | ||
| 847 | CONFIG_USB_PXA2XX=y | ||
| 848 | # CONFIG_USB_PXA2XX_SMALL is not set | ||
| 849 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 850 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 851 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 852 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 853 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 854 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 855 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 856 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 857 | # CONFIG_USB_ZERO is not set | ||
| 858 | CONFIG_USB_ETH=y | ||
| 859 | CONFIG_USB_ETH_RNDIS=y | ||
| 860 | # CONFIG_USB_GADGETFS is not set | ||
| 861 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 862 | # CONFIG_USB_G_SERIAL is not set | ||
| 863 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 864 | # CONFIG_USB_G_PRINTER is not set | ||
| 865 | CONFIG_MMC=y | ||
| 866 | # CONFIG_MMC_DEBUG is not set | ||
| 867 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 868 | |||
| 869 | # | ||
| 870 | # MMC/SD Card Drivers | ||
| 871 | # | ||
| 872 | CONFIG_MMC_BLOCK=y | ||
| 873 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 874 | # CONFIG_SDIO_UART is not set | ||
| 875 | |||
| 876 | # | ||
| 877 | # MMC/SD Host Controller Drivers | ||
| 878 | # | ||
| 879 | CONFIG_MMC_PXA=y | ||
| 880 | # CONFIG_NEW_LEDS is not set | ||
| 881 | CONFIG_RTC_LIB=y | ||
| 882 | # CONFIG_RTC_CLASS is not set | ||
| 883 | |||
| 884 | # | ||
| 885 | # File systems | ||
| 886 | # | ||
| 887 | # CONFIG_EXT2_FS is not set | ||
| 888 | # CONFIG_EXT3_FS is not set | ||
| 889 | # CONFIG_EXT4DEV_FS is not set | ||
| 890 | # CONFIG_REISERFS_FS is not set | ||
| 891 | # CONFIG_JFS_FS is not set | ||
| 892 | # CONFIG_FS_POSIX_ACL is not set | ||
| 893 | # CONFIG_XFS_FS is not set | ||
| 894 | # CONFIG_GFS2_FS is not set | ||
| 895 | # CONFIG_OCFS2_FS is not set | ||
| 896 | # CONFIG_DNOTIFY is not set | ||
| 897 | CONFIG_INOTIFY=y | ||
| 898 | CONFIG_INOTIFY_USER=y | ||
| 899 | # CONFIG_QUOTA is not set | ||
| 900 | # CONFIG_AUTOFS_FS is not set | ||
| 901 | # CONFIG_AUTOFS4_FS is not set | ||
| 902 | # CONFIG_FUSE_FS is not set | ||
| 903 | |||
| 904 | # | ||
| 905 | # CD-ROM/DVD Filesystems | ||
| 906 | # | ||
| 907 | # CONFIG_ISO9660_FS is not set | ||
| 908 | # CONFIG_UDF_FS is not set | ||
| 909 | |||
| 910 | # | ||
| 911 | # DOS/FAT/NT Filesystems | ||
| 912 | # | ||
| 913 | CONFIG_FAT_FS=y | ||
| 914 | # CONFIG_MSDOS_FS is not set | ||
| 915 | CONFIG_VFAT_FS=y | ||
| 916 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 917 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 918 | # CONFIG_NTFS_FS is not set | ||
| 919 | |||
| 920 | # | ||
| 921 | # Pseudo filesystems | ||
| 922 | # | ||
| 923 | CONFIG_PROC_FS=y | ||
| 924 | CONFIG_PROC_SYSCTL=y | ||
| 925 | CONFIG_SYSFS=y | ||
| 926 | CONFIG_TMPFS=y | ||
| 927 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 928 | # CONFIG_HUGETLB_PAGE is not set | ||
| 929 | # CONFIG_CONFIGFS_FS is not set | ||
| 930 | |||
| 931 | # | ||
| 932 | # Miscellaneous filesystems | ||
| 933 | # | ||
| 934 | # CONFIG_ADFS_FS is not set | ||
| 935 | # CONFIG_AFFS_FS is not set | ||
| 936 | # CONFIG_HFS_FS is not set | ||
| 937 | # CONFIG_HFSPLUS_FS is not set | ||
| 938 | # CONFIG_BEFS_FS is not set | ||
| 939 | # CONFIG_BFS_FS is not set | ||
| 940 | # CONFIG_EFS_FS is not set | ||
| 941 | CONFIG_JFFS2_FS=y | ||
| 942 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 943 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 944 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 945 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 946 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 947 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 948 | CONFIG_JFFS2_ZLIB=y | ||
| 949 | # CONFIG_JFFS2_LZO is not set | ||
| 950 | CONFIG_JFFS2_RTIME=y | ||
| 951 | CONFIG_JFFS2_RUBIN=y | ||
| 952 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 953 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 954 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 955 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 956 | # CONFIG_CRAMFS is not set | ||
| 957 | # CONFIG_VXFS_FS is not set | ||
| 958 | # CONFIG_MINIX_FS is not set | ||
| 959 | # CONFIG_HPFS_FS is not set | ||
| 960 | # CONFIG_QNX4FS_FS is not set | ||
| 961 | # CONFIG_ROMFS_FS is not set | ||
| 962 | # CONFIG_SYSV_FS is not set | ||
| 963 | # CONFIG_UFS_FS is not set | ||
| 964 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 965 | # CONFIG_NFS_FS is not set | ||
| 966 | # CONFIG_NFSD is not set | ||
| 967 | # CONFIG_SMB_FS is not set | ||
| 968 | # CONFIG_CIFS is not set | ||
| 969 | # CONFIG_NCP_FS is not set | ||
| 970 | # CONFIG_CODA_FS is not set | ||
| 971 | # CONFIG_AFS_FS is not set | ||
| 972 | |||
| 973 | # | ||
| 974 | # Partition Types | ||
| 975 | # | ||
| 976 | CONFIG_PARTITION_ADVANCED=y | ||
| 977 | # CONFIG_ACORN_PARTITION is not set | ||
| 978 | # CONFIG_OSF_PARTITION is not set | ||
| 979 | # CONFIG_AMIGA_PARTITION is not set | ||
| 980 | # CONFIG_ATARI_PARTITION is not set | ||
| 981 | # CONFIG_MAC_PARTITION is not set | ||
| 982 | CONFIG_MSDOS_PARTITION=y | ||
| 983 | # CONFIG_BSD_DISKLABEL is not set | ||
| 984 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 985 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 986 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 987 | # CONFIG_LDM_PARTITION is not set | ||
| 988 | # CONFIG_SGI_PARTITION is not set | ||
| 989 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 990 | # CONFIG_SUN_PARTITION is not set | ||
| 991 | # CONFIG_KARMA_PARTITION is not set | ||
| 992 | # CONFIG_EFI_PARTITION is not set | ||
| 993 | # CONFIG_SYSV68_PARTITION is not set | ||
| 994 | CONFIG_NLS=y | ||
| 995 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 996 | CONFIG_NLS_CODEPAGE_437=y | ||
| 997 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 998 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 999 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1000 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1001 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1002 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1003 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1004 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1005 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1006 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1007 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1008 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1009 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1010 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1011 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1012 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1013 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1014 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1015 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1016 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1017 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1018 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1019 | # CONFIG_NLS_ASCII is not set | ||
| 1020 | CONFIG_NLS_ISO8859_1=y | ||
| 1021 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1022 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1023 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1024 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1025 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1026 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1027 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1028 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1029 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1030 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1031 | # CONFIG_NLS_KOI8_R is not set | ||
| 1032 | # CONFIG_NLS_KOI8_U is not set | ||
| 1033 | # CONFIG_NLS_UTF8 is not set | ||
| 1034 | # CONFIG_DLM is not set | ||
| 1035 | |||
| 1036 | # | ||
| 1037 | # Kernel hacking | ||
| 1038 | # | ||
| 1039 | # CONFIG_PRINTK_TIME is not set | ||
| 1040 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1041 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1042 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1043 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1044 | # CONFIG_DEBUG_FS is not set | ||
| 1045 | # CONFIG_HEADERS_CHECK is not set | ||
| 1046 | CONFIG_DEBUG_KERNEL=y | ||
| 1047 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1048 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 1049 | CONFIG_SCHED_DEBUG=y | ||
| 1050 | # CONFIG_SCHEDSTATS is not set | ||
| 1051 | # CONFIG_TIMER_STATS is not set | ||
| 1052 | # CONFIG_DEBUG_SLAB is not set | ||
| 1053 | # CONFIG_DEBUG_PREEMPT is not set | ||
| 1054 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1055 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1056 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1057 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1058 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1059 | # CONFIG_PROVE_LOCKING is not set | ||
| 1060 | # CONFIG_LOCK_STAT is not set | ||
| 1061 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1062 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1063 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1064 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1065 | # CONFIG_DEBUG_INFO is not set | ||
| 1066 | # CONFIG_DEBUG_VM is not set | ||
| 1067 | # CONFIG_DEBUG_LIST is not set | ||
| 1068 | # CONFIG_DEBUG_SG is not set | ||
| 1069 | CONFIG_FRAME_POINTER=y | ||
| 1070 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1071 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1072 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1073 | # CONFIG_FAULT_INJECTION is not set | ||
| 1074 | # CONFIG_SAMPLES is not set | ||
| 1075 | CONFIG_DEBUG_USER=y | ||
| 1076 | CONFIG_DEBUG_ERRORS=y | ||
| 1077 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1078 | # CONFIG_DEBUG_LL is not set | ||
| 1079 | |||
| 1080 | # | ||
| 1081 | # Security options | ||
| 1082 | # | ||
| 1083 | # CONFIG_KEYS is not set | ||
| 1084 | # CONFIG_SECURITY is not set | ||
| 1085 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1086 | CONFIG_CRYPTO=y | ||
| 1087 | CONFIG_CRYPTO_ALGAPI=m | ||
| 1088 | CONFIG_CRYPTO_BLKCIPHER=m | ||
| 1089 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1090 | CONFIG_CRYPTO_MANAGER=m | ||
| 1091 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1092 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1093 | # CONFIG_CRYPTO_NULL is not set | ||
| 1094 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1095 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1096 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1097 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1098 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1099 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1100 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1101 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1102 | CONFIG_CRYPTO_ECB=m | ||
| 1103 | CONFIG_CRYPTO_CBC=m | ||
| 1104 | CONFIG_CRYPTO_PCBC=m | ||
| 1105 | # CONFIG_CRYPTO_LRW is not set | ||
| 1106 | # CONFIG_CRYPTO_XTS is not set | ||
| 1107 | # CONFIG_CRYPTO_CTR is not set | ||
| 1108 | # CONFIG_CRYPTO_GCM is not set | ||
| 1109 | # CONFIG_CRYPTO_CCM is not set | ||
| 1110 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1111 | # CONFIG_CRYPTO_DES is not set | ||
| 1112 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1113 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1114 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1115 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1116 | # CONFIG_CRYPTO_AES is not set | ||
| 1117 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1118 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1119 | # CONFIG_CRYPTO_TEA is not set | ||
| 1120 | CONFIG_CRYPTO_ARC4=m | ||
| 1121 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1122 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1123 | # CONFIG_CRYPTO_SEED is not set | ||
| 1124 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1125 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1126 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1127 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1128 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1129 | # CONFIG_CRYPTO_TEST is not set | ||
| 1130 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1131 | # CONFIG_CRYPTO_LZO is not set | ||
| 1132 | CONFIG_CRYPTO_HW=y | ||
| 1133 | |||
| 1134 | # | ||
| 1135 | # Library routines | ||
| 1136 | # | ||
| 1137 | CONFIG_BITREVERSE=y | ||
| 1138 | # CONFIG_CRC_CCITT is not set | ||
| 1139 | # CONFIG_CRC16 is not set | ||
| 1140 | # CONFIG_CRC_ITU_T is not set | ||
| 1141 | CONFIG_CRC32=y | ||
| 1142 | # CONFIG_CRC7 is not set | ||
| 1143 | # CONFIG_LIBCRC32C is not set | ||
| 1144 | CONFIG_ZLIB_INFLATE=y | ||
| 1145 | CONFIG_ZLIB_DEFLATE=y | ||
| 1146 | CONFIG_PLIST=y | ||
| 1147 | CONFIG_HAS_IOMEM=y | ||
| 1148 | CONFIG_HAS_IOPORT=y | ||
| 1149 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig new file mode 100644 index 000000000000..4d11678584db --- /dev/null +++ b/arch/arm/configs/magician_defconfig | |||
| @@ -0,0 +1,1182 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.24-rc6 | ||
| 4 | # Sun Dec 30 13:02:54 2007 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_LOCK_KERNEL=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_USER_NS is not set | ||
| 45 | # CONFIG_PID_NS is not set | ||
| 46 | # CONFIG_AUDIT is not set | ||
| 47 | CONFIG_IKCONFIG=y | ||
| 48 | CONFIG_IKCONFIG_PROC=y | ||
| 49 | CONFIG_LOG_BUF_SHIFT=16 | ||
| 50 | # CONFIG_CGROUPS is not set | ||
| 51 | # CONFIG_FAIR_GROUP_SCHED is not set | ||
| 52 | # CONFIG_SYSFS_DEPRECATED is not set | ||
| 53 | # CONFIG_RELAY is not set | ||
| 54 | CONFIG_BLK_DEV_INITRD=y | ||
| 55 | CONFIG_INITRAMFS_SOURCE="" | ||
| 56 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 57 | CONFIG_SYSCTL=y | ||
| 58 | CONFIG_EMBEDDED=y | ||
| 59 | # CONFIG_UID16 is not set | ||
| 60 | CONFIG_SYSCTL_SYSCALL=y | ||
| 61 | CONFIG_KALLSYMS=y | ||
| 62 | # CONFIG_KALLSYMS_ALL is not set | ||
| 63 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 64 | CONFIG_HOTPLUG=y | ||
| 65 | CONFIG_PRINTK=y | ||
| 66 | CONFIG_BUG=y | ||
| 67 | CONFIG_ELF_CORE=y | ||
| 68 | CONFIG_BASE_FULL=y | ||
| 69 | CONFIG_FUTEX=y | ||
| 70 | CONFIG_ANON_INODES=y | ||
| 71 | CONFIG_EPOLL=y | ||
| 72 | CONFIG_SIGNALFD=y | ||
| 73 | CONFIG_EVENTFD=y | ||
| 74 | CONFIG_SHMEM=y | ||
| 75 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 76 | CONFIG_SLAB=y | ||
| 77 | # CONFIG_SLUB is not set | ||
| 78 | # CONFIG_SLOB is not set | ||
| 79 | CONFIG_RT_MUTEXES=y | ||
| 80 | # CONFIG_TINY_SHMEM is not set | ||
| 81 | CONFIG_BASE_SMALL=0 | ||
| 82 | CONFIG_MODULES=y | ||
| 83 | CONFIG_MODULE_UNLOAD=y | ||
| 84 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 85 | # CONFIG_MODVERSIONS is not set | ||
| 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 87 | CONFIG_KMOD=y | ||
| 88 | CONFIG_BLOCK=y | ||
| 89 | # CONFIG_LBD is not set | ||
| 90 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 91 | # CONFIG_LSF is not set | ||
| 92 | # CONFIG_BLK_DEV_BSG is not set | ||
| 93 | |||
| 94 | # | ||
| 95 | # IO Schedulers | ||
| 96 | # | ||
| 97 | CONFIG_IOSCHED_NOOP=y | ||
| 98 | # CONFIG_IOSCHED_AS is not set | ||
| 99 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 100 | # CONFIG_IOSCHED_CFQ is not set | ||
| 101 | # CONFIG_DEFAULT_AS is not set | ||
| 102 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 103 | # CONFIG_DEFAULT_CFQ is not set | ||
| 104 | CONFIG_DEFAULT_NOOP=y | ||
| 105 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 106 | CONFIG_CLASSIC_RCU=y | ||
| 107 | # CONFIG_PREEMPT_RCU is not set | ||
| 108 | |||
| 109 | # | ||
| 110 | # System Type | ||
| 111 | # | ||
| 112 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 113 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 114 | # CONFIG_ARCH_REALVIEW is not set | ||
| 115 | # CONFIG_ARCH_VERSATILE is not set | ||
| 116 | # CONFIG_ARCH_AT91 is not set | ||
| 117 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 118 | # CONFIG_ARCH_CLPS711X is not set | ||
| 119 | # CONFIG_ARCH_CO285 is not set | ||
| 120 | # CONFIG_ARCH_EBSA110 is not set | ||
| 121 | # CONFIG_ARCH_EP93XX is not set | ||
| 122 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 123 | # CONFIG_ARCH_NETX is not set | ||
| 124 | # CONFIG_ARCH_H720X is not set | ||
| 125 | # CONFIG_ARCH_IMX is not set | ||
| 126 | # CONFIG_ARCH_IOP13XX is not set | ||
| 127 | # CONFIG_ARCH_IOP32X is not set | ||
| 128 | # CONFIG_ARCH_IOP33X is not set | ||
| 129 | # CONFIG_ARCH_IXP23XX is not set | ||
| 130 | # CONFIG_ARCH_IXP2000 is not set | ||
| 131 | # CONFIG_ARCH_IXP4XX is not set | ||
| 132 | # CONFIG_ARCH_L7200 is not set | ||
| 133 | # CONFIG_ARCH_KS8695 is not set | ||
| 134 | # CONFIG_ARCH_NS9XXX is not set | ||
| 135 | # CONFIG_ARCH_MXC is not set | ||
| 136 | # CONFIG_ARCH_PNX4008 is not set | ||
| 137 | CONFIG_ARCH_PXA=y | ||
| 138 | # CONFIG_ARCH_RPC is not set | ||
| 139 | # CONFIG_ARCH_SA1100 is not set | ||
| 140 | # CONFIG_ARCH_S3C2410 is not set | ||
| 141 | # CONFIG_ARCH_SHARK is not set | ||
| 142 | # CONFIG_ARCH_LH7A40X is not set | ||
| 143 | # CONFIG_ARCH_DAVINCI is not set | ||
| 144 | # CONFIG_ARCH_OMAP is not set | ||
| 145 | |||
| 146 | # | ||
| 147 | # Intel PXA2xx/PXA3xx Implementations | ||
| 148 | # | ||
| 149 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 150 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 151 | # CONFIG_MACH_MAINSTONE is not set | ||
| 152 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 153 | # CONFIG_PXA_SHARPSL is not set | ||
| 154 | # CONFIG_MACH_TRIZEPS4 is not set | ||
| 155 | # CONFIG_MACH_EM_X270 is not set | ||
| 156 | # CONFIG_MACH_ZYLONITE is not set | ||
| 157 | # CONFIG_MACH_ARMCORE is not set | ||
| 158 | CONFIG_MACH_MAGICIAN=y | ||
| 159 | CONFIG_PXA27x=y | ||
| 160 | |||
| 161 | # | ||
| 162 | # Boot options | ||
| 163 | # | ||
| 164 | |||
| 165 | # | ||
| 166 | # Power management | ||
| 167 | # | ||
| 168 | |||
| 169 | # | ||
| 170 | # Processor Type | ||
| 171 | # | ||
| 172 | CONFIG_CPU_32=y | ||
| 173 | CONFIG_CPU_XSCALE=y | ||
| 174 | CONFIG_CPU_32v5=y | ||
| 175 | CONFIG_CPU_ABRT_EV5T=y | ||
| 176 | CONFIG_CPU_CACHE_VIVT=y | ||
| 177 | CONFIG_CPU_TLB_V4WBI=y | ||
| 178 | CONFIG_CPU_CP15=y | ||
| 179 | CONFIG_CPU_CP15_MMU=y | ||
| 180 | |||
| 181 | # | ||
| 182 | # Processor Features | ||
| 183 | # | ||
| 184 | CONFIG_ARM_THUMB=y | ||
| 185 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 186 | # CONFIG_OUTER_CACHE is not set | ||
| 187 | CONFIG_IWMMXT=y | ||
| 188 | CONFIG_XSCALE_PMU=y | ||
| 189 | |||
| 190 | # | ||
| 191 | # Bus support | ||
| 192 | # | ||
| 193 | # CONFIG_PCI_SYSCALL is not set | ||
| 194 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 195 | # CONFIG_PCCARD is not set | ||
| 196 | |||
| 197 | # | ||
| 198 | # Kernel Features | ||
| 199 | # | ||
| 200 | # CONFIG_TICK_ONESHOT is not set | ||
| 201 | # CONFIG_NO_HZ is not set | ||
| 202 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 203 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 204 | CONFIG_PREEMPT=y | ||
| 205 | CONFIG_HZ=100 | ||
| 206 | CONFIG_AEABI=y | ||
| 207 | CONFIG_OABI_COMPAT=y | ||
| 208 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 209 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 210 | CONFIG_FLATMEM_MANUAL=y | ||
| 211 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 212 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 213 | CONFIG_FLATMEM=y | ||
| 214 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 215 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 216 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 217 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 218 | # CONFIG_RESOURCES_64BIT is not set | ||
| 219 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 220 | CONFIG_BOUNCE=y | ||
| 221 | CONFIG_VIRT_TO_BUS=y | ||
| 222 | CONFIG_ALIGNMENT_TRAP=y | ||
| 223 | |||
| 224 | # | ||
| 225 | # Boot options | ||
| 226 | # | ||
| 227 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 228 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 229 | CONFIG_CMDLINE="keepinitrd" | ||
| 230 | # CONFIG_XIP_KERNEL is not set | ||
| 231 | CONFIG_KEXEC=y | ||
| 232 | |||
| 233 | # | ||
| 234 | # CPU Frequency scaling | ||
| 235 | # | ||
| 236 | CONFIG_CPU_FREQ=y | ||
| 237 | CONFIG_CPU_FREQ_TABLE=y | ||
| 238 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
| 239 | CONFIG_CPU_FREQ_STAT=y | ||
| 240 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | ||
| 241 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 242 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 243 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 244 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 245 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 246 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set | ||
| 247 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set | ||
| 248 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | ||
| 249 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | ||
| 250 | |||
| 251 | # | ||
| 252 | # Floating point emulation | ||
| 253 | # | ||
| 254 | |||
| 255 | # | ||
| 256 | # At least one emulation must be selected | ||
| 257 | # | ||
| 258 | CONFIG_FPE_NWFPE=y | ||
| 259 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 260 | # CONFIG_FPE_FASTFPE is not set | ||
| 261 | |||
| 262 | # | ||
| 263 | # Userspace binary formats | ||
| 264 | # | ||
| 265 | CONFIG_BINFMT_ELF=y | ||
| 266 | # CONFIG_BINFMT_AOUT is not set | ||
| 267 | # CONFIG_BINFMT_MISC is not set | ||
| 268 | |||
| 269 | # | ||
| 270 | # Power management options | ||
| 271 | # | ||
| 272 | CONFIG_PM=y | ||
| 273 | # CONFIG_PM_LEGACY is not set | ||
| 274 | # CONFIG_PM_DEBUG is not set | ||
| 275 | CONFIG_PM_SLEEP=y | ||
| 276 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 277 | CONFIG_SUSPEND=y | ||
| 278 | CONFIG_APM_EMULATION=y | ||
| 279 | |||
| 280 | # | ||
| 281 | # Networking | ||
| 282 | # | ||
| 283 | CONFIG_NET=y | ||
| 284 | |||
| 285 | # | ||
| 286 | # Networking options | ||
| 287 | # | ||
| 288 | CONFIG_PACKET=y | ||
| 289 | CONFIG_PACKET_MMAP=y | ||
| 290 | CONFIG_UNIX=y | ||
| 291 | # CONFIG_NET_KEY is not set | ||
| 292 | CONFIG_INET=y | ||
| 293 | CONFIG_IP_MULTICAST=y | ||
| 294 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 295 | CONFIG_IP_FIB_HASH=y | ||
| 296 | CONFIG_IP_PNP=y | ||
| 297 | # CONFIG_IP_PNP_DHCP is not set | ||
| 298 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 299 | # CONFIG_IP_PNP_RARP is not set | ||
| 300 | # CONFIG_NET_IPIP is not set | ||
| 301 | # CONFIG_NET_IPGRE is not set | ||
| 302 | # CONFIG_IP_MROUTE is not set | ||
| 303 | # CONFIG_ARPD is not set | ||
| 304 | # CONFIG_SYN_COOKIES is not set | ||
| 305 | # CONFIG_INET_AH is not set | ||
| 306 | # CONFIG_INET_ESP is not set | ||
| 307 | # CONFIG_INET_IPCOMP is not set | ||
| 308 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 309 | # CONFIG_INET_TUNNEL is not set | ||
| 310 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 311 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 312 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 313 | # CONFIG_INET_LRO is not set | ||
| 314 | # CONFIG_INET_DIAG is not set | ||
| 315 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 316 | CONFIG_TCP_CONG_CUBIC=y | ||
| 317 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 318 | # CONFIG_TCP_MD5SIG is not set | ||
| 319 | # CONFIG_IP_VS is not set | ||
| 320 | # CONFIG_IPV6 is not set | ||
| 321 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 322 | # CONFIG_INET6_TUNNEL is not set | ||
| 323 | # CONFIG_NETWORK_SECMARK is not set | ||
| 324 | CONFIG_NETFILTER=y | ||
| 325 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 326 | |||
| 327 | # | ||
| 328 | # Core Netfilter Configuration | ||
| 329 | # | ||
| 330 | # CONFIG_NETFILTER_NETLINK is not set | ||
| 331 | # CONFIG_NF_CONNTRACK_ENABLED is not set | ||
| 332 | # CONFIG_NF_CONNTRACK is not set | ||
| 333 | # CONFIG_NETFILTER_XTABLES is not set | ||
| 334 | |||
| 335 | # | ||
| 336 | # IP: Netfilter Configuration | ||
| 337 | # | ||
| 338 | # CONFIG_IP_NF_QUEUE is not set | ||
| 339 | # CONFIG_IP_NF_IPTABLES is not set | ||
| 340 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 341 | # CONFIG_IP_DCCP is not set | ||
| 342 | # CONFIG_IP_SCTP is not set | ||
| 343 | # CONFIG_TIPC is not set | ||
| 344 | # CONFIG_ATM is not set | ||
| 345 | # CONFIG_BRIDGE is not set | ||
| 346 | # CONFIG_VLAN_8021Q is not set | ||
| 347 | # CONFIG_DECNET is not set | ||
| 348 | # CONFIG_LLC2 is not set | ||
| 349 | # CONFIG_IPX is not set | ||
| 350 | # CONFIG_ATALK is not set | ||
| 351 | # CONFIG_X25 is not set | ||
| 352 | # CONFIG_LAPB is not set | ||
| 353 | # CONFIG_ECONET is not set | ||
| 354 | # CONFIG_WAN_ROUTER is not set | ||
| 355 | # CONFIG_NET_SCHED is not set | ||
| 356 | |||
| 357 | # | ||
| 358 | # Network testing | ||
| 359 | # | ||
| 360 | # CONFIG_NET_PKTGEN is not set | ||
| 361 | # CONFIG_HAMRADIO is not set | ||
| 362 | # CONFIG_CAN is not set | ||
| 363 | CONFIG_IRDA=m | ||
| 364 | |||
| 365 | # | ||
| 366 | # IrDA protocols | ||
| 367 | # | ||
| 368 | CONFIG_IRLAN=m | ||
| 369 | # CONFIG_IRNET is not set | ||
| 370 | CONFIG_IRCOMM=m | ||
| 371 | CONFIG_IRDA_ULTRA=y | ||
| 372 | |||
| 373 | # | ||
| 374 | # IrDA options | ||
| 375 | # | ||
| 376 | CONFIG_IRDA_CACHE_LAST_LSAP=y | ||
| 377 | CONFIG_IRDA_FAST_RR=y | ||
| 378 | CONFIG_IRDA_DEBUG=y | ||
| 379 | |||
| 380 | # | ||
| 381 | # Infrared-port device drivers | ||
| 382 | # | ||
| 383 | |||
| 384 | # | ||
| 385 | # SIR device drivers | ||
| 386 | # | ||
| 387 | CONFIG_IRTTY_SIR=m | ||
| 388 | |||
| 389 | # | ||
| 390 | # Dongle support | ||
| 391 | # | ||
| 392 | # CONFIG_DONGLE is not set | ||
| 393 | |||
| 394 | # | ||
| 395 | # Old SIR device drivers | ||
| 396 | # | ||
| 397 | # CONFIG_IRPORT_SIR is not set | ||
| 398 | |||
| 399 | # | ||
| 400 | # Old Serial dongle support | ||
| 401 | # | ||
| 402 | |||
| 403 | # | ||
| 404 | # FIR device drivers | ||
| 405 | # | ||
| 406 | CONFIG_PXA_FICP=m | ||
| 407 | CONFIG_BT=m | ||
| 408 | CONFIG_BT_L2CAP=m | ||
| 409 | CONFIG_BT_SCO=m | ||
| 410 | CONFIG_BT_RFCOMM=m | ||
| 411 | CONFIG_BT_RFCOMM_TTY=y | ||
| 412 | CONFIG_BT_BNEP=m | ||
| 413 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 414 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 415 | CONFIG_BT_HIDP=m | ||
| 416 | |||
| 417 | # | ||
| 418 | # Bluetooth device drivers | ||
| 419 | # | ||
| 420 | # CONFIG_BT_HCIUART is not set | ||
| 421 | # CONFIG_BT_HCIVHCI is not set | ||
| 422 | # CONFIG_AF_RXRPC is not set | ||
| 423 | |||
| 424 | # | ||
| 425 | # Wireless | ||
| 426 | # | ||
| 427 | # CONFIG_CFG80211 is not set | ||
| 428 | # CONFIG_WIRELESS_EXT is not set | ||
| 429 | # CONFIG_MAC80211 is not set | ||
| 430 | # CONFIG_IEEE80211 is not set | ||
| 431 | # CONFIG_RFKILL is not set | ||
| 432 | # CONFIG_NET_9P is not set | ||
| 433 | |||
| 434 | # | ||
| 435 | # Device Drivers | ||
| 436 | # | ||
| 437 | |||
| 438 | # | ||
| 439 | # Generic Driver Options | ||
| 440 | # | ||
| 441 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 442 | CONFIG_STANDALONE=y | ||
| 443 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 444 | CONFIG_FW_LOADER=y | ||
| 445 | # CONFIG_DEBUG_DRIVER is not set | ||
| 446 | # CONFIG_DEBUG_DEVRES is not set | ||
| 447 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 448 | # CONFIG_CONNECTOR is not set | ||
| 449 | CONFIG_MTD=y | ||
| 450 | CONFIG_MTD_DEBUG=y | ||
| 451 | CONFIG_MTD_DEBUG_VERBOSE=0 | ||
| 452 | # CONFIG_MTD_CONCAT is not set | ||
| 453 | CONFIG_MTD_PARTITIONS=y | ||
| 454 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 455 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 456 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 457 | |||
| 458 | # | ||
| 459 | # User Modules And Translation Layers | ||
| 460 | # | ||
| 461 | CONFIG_MTD_CHAR=m | ||
| 462 | CONFIG_MTD_BLKDEVS=m | ||
| 463 | CONFIG_MTD_BLOCK=m | ||
| 464 | # CONFIG_FTL is not set | ||
| 465 | # CONFIG_NFTL is not set | ||
| 466 | # CONFIG_INFTL is not set | ||
| 467 | # CONFIG_RFD_FTL is not set | ||
| 468 | # CONFIG_SSFDC is not set | ||
| 469 | # CONFIG_MTD_OOPS is not set | ||
| 470 | |||
| 471 | # | ||
| 472 | # RAM/ROM/Flash chip drivers | ||
| 473 | # | ||
| 474 | CONFIG_MTD_CFI=y | ||
| 475 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 476 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 477 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 478 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 479 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 480 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 481 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 482 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 483 | CONFIG_MTD_CFI_I1=y | ||
| 484 | CONFIG_MTD_CFI_I2=y | ||
| 485 | # CONFIG_MTD_CFI_I4 is not set | ||
| 486 | # CONFIG_MTD_CFI_I8 is not set | ||
| 487 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 488 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 489 | # CONFIG_MTD_CFI_STAA is not set | ||
| 490 | # CONFIG_MTD_RAM is not set | ||
| 491 | # CONFIG_MTD_ROM is not set | ||
| 492 | # CONFIG_MTD_ABSENT is not set | ||
| 493 | # CONFIG_MTD_XIP is not set | ||
| 494 | |||
| 495 | # | ||
| 496 | # Mapping drivers for chip access | ||
| 497 | # | ||
| 498 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 499 | CONFIG_MTD_PHYSMAP=y | ||
| 500 | CONFIG_MTD_PHYSMAP_START=0x00000000 | ||
| 501 | CONFIG_MTD_PHYSMAP_LEN=0x04000000 | ||
| 502 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 503 | # CONFIG_MTD_PXA2XX is not set | ||
| 504 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 505 | # CONFIG_MTD_SHARP_SL is not set | ||
| 506 | # CONFIG_MTD_PLATRAM is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # Self-contained MTD device drivers | ||
| 510 | # | ||
| 511 | # CONFIG_MTD_SLRAM is not set | ||
| 512 | # CONFIG_MTD_PHRAM is not set | ||
| 513 | # CONFIG_MTD_MTDRAM is not set | ||
| 514 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 515 | |||
| 516 | # | ||
| 517 | # Disk-On-Chip Device Drivers | ||
| 518 | # | ||
| 519 | # CONFIG_MTD_DOC2000 is not set | ||
| 520 | # CONFIG_MTD_DOC2001 is not set | ||
| 521 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 522 | # CONFIG_MTD_NAND is not set | ||
| 523 | # CONFIG_MTD_ONENAND is not set | ||
| 524 | |||
| 525 | # | ||
| 526 | # UBI - Unsorted block images | ||
| 527 | # | ||
| 528 | # CONFIG_MTD_UBI is not set | ||
| 529 | # CONFIG_PARPORT is not set | ||
| 530 | CONFIG_BLK_DEV=y | ||
| 531 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 532 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 533 | # CONFIG_BLK_DEV_NBD is not set | ||
| 534 | # CONFIG_BLK_DEV_RAM is not set | ||
| 535 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 536 | # CONFIG_ATA_OVER_ETH is not set | ||
| 537 | # CONFIG_MISC_DEVICES is not set | ||
| 538 | # CONFIG_IDE is not set | ||
| 539 | |||
| 540 | # | ||
| 541 | # SCSI device support | ||
| 542 | # | ||
| 543 | # CONFIG_RAID_ATTRS is not set | ||
| 544 | # CONFIG_SCSI is not set | ||
| 545 | # CONFIG_SCSI_DMA is not set | ||
| 546 | # CONFIG_SCSI_NETLINK is not set | ||
| 547 | # CONFIG_ATA is not set | ||
| 548 | # CONFIG_MD is not set | ||
| 549 | CONFIG_NETDEVICES=y | ||
| 550 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 551 | # CONFIG_DUMMY is not set | ||
| 552 | # CONFIG_BONDING is not set | ||
| 553 | # CONFIG_MACVLAN is not set | ||
| 554 | # CONFIG_EQUALIZER is not set | ||
| 555 | # CONFIG_TUN is not set | ||
| 556 | # CONFIG_VETH is not set | ||
| 557 | # CONFIG_NET_ETHERNET is not set | ||
| 558 | # CONFIG_NETDEV_1000 is not set | ||
| 559 | # CONFIG_NETDEV_10000 is not set | ||
| 560 | |||
| 561 | # | ||
| 562 | # Wireless LAN | ||
| 563 | # | ||
| 564 | # CONFIG_WLAN_PRE80211 is not set | ||
| 565 | # CONFIG_WLAN_80211 is not set | ||
| 566 | # CONFIG_WAN is not set | ||
| 567 | CONFIG_PPP=m | ||
| 568 | # CONFIG_PPP_MULTILINK is not set | ||
| 569 | # CONFIG_PPP_FILTER is not set | ||
| 570 | CONFIG_PPP_ASYNC=m | ||
| 571 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 572 | CONFIG_PPP_DEFLATE=m | ||
| 573 | CONFIG_PPP_BSDCOMP=m | ||
| 574 | CONFIG_PPP_MPPE=m | ||
| 575 | # CONFIG_PPPOE is not set | ||
| 576 | # CONFIG_PPPOL2TP is not set | ||
| 577 | # CONFIG_SLIP is not set | ||
| 578 | CONFIG_SLHC=m | ||
| 579 | # CONFIG_NETCONSOLE is not set | ||
| 580 | # CONFIG_NETPOLL is not set | ||
| 581 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 582 | # CONFIG_ISDN is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # Input device support | ||
| 586 | # | ||
| 587 | CONFIG_INPUT=y | ||
| 588 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 589 | # CONFIG_INPUT_POLLDEV is not set | ||
| 590 | |||
| 591 | # | ||
| 592 | # Userland interfaces | ||
| 593 | # | ||
| 594 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 595 | # CONFIG_INPUT_JOYDEV is not set | ||
| 596 | CONFIG_INPUT_EVDEV=y | ||
| 597 | # CONFIG_INPUT_EVBUG is not set | ||
| 598 | |||
| 599 | # | ||
| 600 | # Input Device Drivers | ||
| 601 | # | ||
| 602 | CONFIG_INPUT_KEYBOARD=y | ||
| 603 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 604 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 605 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 606 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 607 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 608 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 609 | # CONFIG_KEYBOARD_PXA27x is not set | ||
| 610 | CONFIG_KEYBOARD_GPIO=y | ||
| 611 | # CONFIG_INPUT_MOUSE is not set | ||
| 612 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 613 | # CONFIG_INPUT_TABLET is not set | ||
| 614 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 615 | CONFIG_INPUT_MISC=y | ||
| 616 | CONFIG_INPUT_UINPUT=m | ||
| 617 | |||
| 618 | # | ||
| 619 | # Hardware I/O ports | ||
| 620 | # | ||
| 621 | # CONFIG_SERIO is not set | ||
| 622 | # CONFIG_GAMEPORT is not set | ||
| 623 | |||
| 624 | # | ||
| 625 | # Character devices | ||
| 626 | # | ||
| 627 | CONFIG_VT=y | ||
| 628 | CONFIG_VT_CONSOLE=y | ||
| 629 | CONFIG_HW_CONSOLE=y | ||
| 630 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 631 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 632 | |||
| 633 | # | ||
| 634 | # Serial drivers | ||
| 635 | # | ||
| 636 | # CONFIG_SERIAL_8250 is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Non-8250 serial port support | ||
| 640 | # | ||
| 641 | CONFIG_SERIAL_PXA=y | ||
| 642 | # CONFIG_SERIAL_PXA_CONSOLE is not set | ||
| 643 | CONFIG_SERIAL_CORE=y | ||
| 644 | CONFIG_UNIX98_PTYS=y | ||
| 645 | # CONFIG_LEGACY_PTYS is not set | ||
| 646 | # CONFIG_IPMI_HANDLER is not set | ||
| 647 | # CONFIG_HW_RANDOM is not set | ||
| 648 | # CONFIG_NVRAM is not set | ||
| 649 | # CONFIG_R3964 is not set | ||
| 650 | # CONFIG_RAW_DRIVER is not set | ||
| 651 | # CONFIG_TCG_TPM is not set | ||
| 652 | CONFIG_I2C=m | ||
| 653 | CONFIG_I2C_BOARDINFO=y | ||
| 654 | CONFIG_I2C_CHARDEV=m | ||
| 655 | |||
| 656 | # | ||
| 657 | # I2C Algorithms | ||
| 658 | # | ||
| 659 | # CONFIG_I2C_ALGOBIT is not set | ||
| 660 | # CONFIG_I2C_ALGOPCF is not set | ||
| 661 | # CONFIG_I2C_ALGOPCA is not set | ||
| 662 | |||
| 663 | # | ||
| 664 | # I2C Hardware Bus support | ||
| 665 | # | ||
| 666 | # CONFIG_I2C_GPIO is not set | ||
| 667 | CONFIG_I2C_PXA=m | ||
| 668 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 669 | # CONFIG_I2C_OCORES is not set | ||
| 670 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 671 | # CONFIG_I2C_SIMTEC is not set | ||
| 672 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 673 | # CONFIG_I2C_STUB is not set | ||
| 674 | |||
| 675 | # | ||
| 676 | # Miscellaneous I2C Chip support | ||
| 677 | # | ||
| 678 | # CONFIG_SENSORS_DS1337 is not set | ||
| 679 | # CONFIG_SENSORS_DS1374 is not set | ||
| 680 | # CONFIG_DS1682 is not set | ||
| 681 | # CONFIG_SENSORS_EEPROM is not set | ||
| 682 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 683 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 684 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 685 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 686 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 687 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 688 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 689 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 690 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 691 | |||
| 692 | # | ||
| 693 | # SPI support | ||
| 694 | # | ||
| 695 | # CONFIG_SPI is not set | ||
| 696 | # CONFIG_SPI_MASTER is not set | ||
| 697 | CONFIG_W1=y | ||
| 698 | |||
| 699 | # | ||
| 700 | # 1-wire Bus Masters | ||
| 701 | # | ||
| 702 | # CONFIG_W1_MASTER_DS2482 is not set | ||
| 703 | CONFIG_W1_MASTER_DS1WM=y | ||
| 704 | |||
| 705 | # | ||
| 706 | # 1-wire Slaves | ||
| 707 | # | ||
| 708 | # CONFIG_W1_SLAVE_THERM is not set | ||
| 709 | # CONFIG_W1_SLAVE_SMEM is not set | ||
| 710 | # CONFIG_W1_SLAVE_DS2433 is not set | ||
| 711 | CONFIG_W1_SLAVE_DS2760=y | ||
| 712 | CONFIG_POWER_SUPPLY=y | ||
| 713 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 714 | CONFIG_PDA_POWER=y | ||
| 715 | # CONFIG_APM_POWER is not set | ||
| 716 | CONFIG_BATTERY_DS2760=y | ||
| 717 | # CONFIG_HWMON is not set | ||
| 718 | # CONFIG_WATCHDOG is not set | ||
| 719 | |||
| 720 | # | ||
| 721 | # Sonics Silicon Backplane | ||
| 722 | # | ||
| 723 | CONFIG_SSB_POSSIBLE=y | ||
| 724 | # CONFIG_SSB is not set | ||
| 725 | |||
| 726 | # | ||
| 727 | # Multifunction device drivers | ||
| 728 | # | ||
| 729 | # CONFIG_MFD_SM501 is not set | ||
| 730 | CONFIG_HTC_EGPIO=y | ||
| 731 | CONFIG_HTC_PASIC3=y | ||
| 732 | |||
| 733 | # | ||
| 734 | # Multimedia devices | ||
| 735 | # | ||
| 736 | # CONFIG_VIDEO_DEV is not set | ||
| 737 | # CONFIG_DVB_CORE is not set | ||
| 738 | # CONFIG_DAB is not set | ||
| 739 | |||
| 740 | # | ||
| 741 | # Graphics support | ||
| 742 | # | ||
| 743 | # CONFIG_VGASTATE is not set | ||
| 744 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 745 | CONFIG_FB=y | ||
| 746 | # CONFIG_FIRMWARE_EDID is not set | ||
| 747 | # CONFIG_FB_DDC is not set | ||
| 748 | CONFIG_FB_CFB_FILLRECT=y | ||
| 749 | CONFIG_FB_CFB_COPYAREA=y | ||
| 750 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 751 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 752 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 753 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 754 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 755 | # CONFIG_FB_SYS_FOPS is not set | ||
| 756 | CONFIG_FB_DEFERRED_IO=y | ||
| 757 | # CONFIG_FB_SVGALIB is not set | ||
| 758 | # CONFIG_FB_MACMODES is not set | ||
| 759 | # CONFIG_FB_BACKLIGHT is not set | ||
| 760 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 761 | # CONFIG_FB_TILEBLITTING is not set | ||
| 762 | |||
| 763 | # | ||
| 764 | # Frame buffer hardware drivers | ||
| 765 | # | ||
| 766 | # CONFIG_FB_S1D13XXX is not set | ||
| 767 | CONFIG_FB_PXA=y | ||
| 768 | # CONFIG_FB_PXA_PARAMETERS is not set | ||
| 769 | # CONFIG_FB_MBX is not set | ||
| 770 | # CONFIG_FB_VIRTUAL is not set | ||
| 771 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 772 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 773 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 774 | CONFIG_BACKLIGHT_CORGI=y | ||
| 775 | |||
| 776 | # | ||
| 777 | # Display device support | ||
| 778 | # | ||
| 779 | CONFIG_DISPLAY_SUPPORT=y | ||
| 780 | |||
| 781 | # | ||
| 782 | # Display hardware drivers | ||
| 783 | # | ||
| 784 | |||
| 785 | # | ||
| 786 | # Console display driver support | ||
| 787 | # | ||
| 788 | # CONFIG_VGA_CONSOLE is not set | ||
| 789 | CONFIG_DUMMY_CONSOLE=y | ||
| 790 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 791 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 792 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
| 793 | CONFIG_FONTS=y | ||
| 794 | # CONFIG_FONT_8x8 is not set | ||
| 795 | # CONFIG_FONT_8x16 is not set | ||
| 796 | # CONFIG_FONT_6x11 is not set | ||
| 797 | # CONFIG_FONT_7x14 is not set | ||
| 798 | # CONFIG_FONT_PEARL_8x8 is not set | ||
| 799 | # CONFIG_FONT_ACORN_8x8 is not set | ||
| 800 | CONFIG_FONT_MINI_4x6=y | ||
| 801 | # CONFIG_FONT_SUN8x16 is not set | ||
| 802 | # CONFIG_FONT_SUN12x22 is not set | ||
| 803 | # CONFIG_FONT_10x18 is not set | ||
| 804 | # CONFIG_LOGO is not set | ||
| 805 | |||
| 806 | # | ||
| 807 | # Sound | ||
| 808 | # | ||
| 809 | CONFIG_SOUND=y | ||
| 810 | |||
| 811 | # | ||
| 812 | # Advanced Linux Sound Architecture | ||
| 813 | # | ||
| 814 | CONFIG_SND=m | ||
| 815 | CONFIG_SND_TIMER=m | ||
| 816 | CONFIG_SND_PCM=m | ||
| 817 | # CONFIG_SND_SEQUENCER is not set | ||
| 818 | CONFIG_SND_OSSEMUL=y | ||
| 819 | CONFIG_SND_MIXER_OSS=m | ||
| 820 | CONFIG_SND_PCM_OSS=m | ||
| 821 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 822 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 823 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 824 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 825 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 826 | # CONFIG_SND_DEBUG is not set | ||
| 827 | |||
| 828 | # | ||
| 829 | # Generic devices | ||
| 830 | # | ||
| 831 | # CONFIG_SND_DUMMY is not set | ||
| 832 | # CONFIG_SND_MTPAV is not set | ||
| 833 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 834 | # CONFIG_SND_MPU401 is not set | ||
| 835 | |||
| 836 | # | ||
| 837 | # ALSA ARM devices | ||
| 838 | # | ||
| 839 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 840 | |||
| 841 | # | ||
| 842 | # System on Chip audio support | ||
| 843 | # | ||
| 844 | CONFIG_SND_SOC=m | ||
| 845 | CONFIG_SND_PXA2XX_SOC=m | ||
| 846 | |||
| 847 | # | ||
| 848 | # SoC Audio support for SuperH | ||
| 849 | # | ||
| 850 | |||
| 851 | # | ||
| 852 | # Open Sound System | ||
| 853 | # | ||
| 854 | # CONFIG_SOUND_PRIME is not set | ||
| 855 | # CONFIG_HID_SUPPORT is not set | ||
| 856 | CONFIG_HID=m | ||
| 857 | # CONFIG_USB_SUPPORT is not set | ||
| 858 | CONFIG_MMC=y | ||
| 859 | # CONFIG_MMC_DEBUG is not set | ||
| 860 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 861 | |||
| 862 | # | ||
| 863 | # MMC/SD Card Drivers | ||
| 864 | # | ||
| 865 | CONFIG_MMC_BLOCK=y | ||
| 866 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 867 | CONFIG_SDIO_UART=m | ||
| 868 | |||
| 869 | # | ||
| 870 | # MMC/SD Host Controller Drivers | ||
| 871 | # | ||
| 872 | CONFIG_MMC_PXA=y | ||
| 873 | CONFIG_NEW_LEDS=y | ||
| 874 | CONFIG_RTC_LIB=y | ||
| 875 | CONFIG_RTC_CLASS=y | ||
| 876 | CONFIG_RTC_HCTOSYS=y | ||
| 877 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 878 | CONFIG_RTC_DEBUG=y | ||
| 879 | |||
| 880 | # | ||
| 881 | # RTC interfaces | ||
| 882 | # | ||
| 883 | CONFIG_RTC_INTF_SYSFS=y | ||
| 884 | CONFIG_RTC_INTF_PROC=y | ||
| 885 | CONFIG_RTC_INTF_DEV=y | ||
| 886 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 887 | # CONFIG_RTC_DRV_TEST is not set | ||
| 888 | |||
| 889 | # | ||
| 890 | # I2C RTC drivers | ||
| 891 | # | ||
| 892 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 893 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 894 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 895 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 896 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 897 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 898 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 899 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 900 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 901 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 902 | |||
| 903 | # | ||
| 904 | # SPI RTC drivers | ||
| 905 | # | ||
| 906 | |||
| 907 | # | ||
| 908 | # Platform RTC drivers | ||
| 909 | # | ||
| 910 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 911 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 912 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 913 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 914 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 915 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 916 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 917 | |||
| 918 | # | ||
| 919 | # on-CPU RTC drivers | ||
| 920 | # | ||
| 921 | CONFIG_RTC_DRV_SA1100=y | ||
| 922 | |||
| 923 | # | ||
| 924 | # File systems | ||
| 925 | # | ||
| 926 | CONFIG_EXT2_FS=y | ||
| 927 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 928 | # CONFIG_EXT2_FS_XIP is not set | ||
| 929 | # CONFIG_EXT3_FS is not set | ||
| 930 | # CONFIG_EXT4DEV_FS is not set | ||
| 931 | # CONFIG_REISERFS_FS is not set | ||
| 932 | # CONFIG_JFS_FS is not set | ||
| 933 | # CONFIG_FS_POSIX_ACL is not set | ||
| 934 | # CONFIG_XFS_FS is not set | ||
| 935 | # CONFIG_GFS2_FS is not set | ||
| 936 | # CONFIG_OCFS2_FS is not set | ||
| 937 | # CONFIG_MINIX_FS is not set | ||
| 938 | # CONFIG_ROMFS_FS is not set | ||
| 939 | CONFIG_INOTIFY=y | ||
| 940 | CONFIG_INOTIFY_USER=y | ||
| 941 | # CONFIG_QUOTA is not set | ||
| 942 | CONFIG_DNOTIFY=y | ||
| 943 | # CONFIG_AUTOFS_FS is not set | ||
| 944 | # CONFIG_AUTOFS4_FS is not set | ||
| 945 | # CONFIG_FUSE_FS is not set | ||
| 946 | |||
| 947 | # | ||
| 948 | # CD-ROM/DVD Filesystems | ||
| 949 | # | ||
| 950 | # CONFIG_ISO9660_FS is not set | ||
| 951 | # CONFIG_UDF_FS is not set | ||
| 952 | |||
| 953 | # | ||
| 954 | # DOS/FAT/NT Filesystems | ||
| 955 | # | ||
| 956 | CONFIG_FAT_FS=m | ||
| 957 | CONFIG_MSDOS_FS=m | ||
| 958 | CONFIG_VFAT_FS=m | ||
| 959 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 960 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 961 | # CONFIG_NTFS_FS is not set | ||
| 962 | |||
| 963 | # | ||
| 964 | # Pseudo filesystems | ||
| 965 | # | ||
| 966 | CONFIG_PROC_FS=y | ||
| 967 | CONFIG_PROC_SYSCTL=y | ||
| 968 | CONFIG_SYSFS=y | ||
| 969 | CONFIG_TMPFS=y | ||
| 970 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 971 | # CONFIG_HUGETLB_PAGE is not set | ||
| 972 | # CONFIG_CONFIGFS_FS is not set | ||
| 973 | |||
| 974 | # | ||
| 975 | # Miscellaneous filesystems | ||
| 976 | # | ||
| 977 | # CONFIG_ADFS_FS is not set | ||
| 978 | # CONFIG_AFFS_FS is not set | ||
| 979 | # CONFIG_HFS_FS is not set | ||
| 980 | # CONFIG_HFSPLUS_FS is not set | ||
| 981 | # CONFIG_BEFS_FS is not set | ||
| 982 | # CONFIG_BFS_FS is not set | ||
| 983 | # CONFIG_EFS_FS is not set | ||
| 984 | CONFIG_JFFS2_FS=y | ||
| 985 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 986 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 987 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 988 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 989 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 990 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 991 | CONFIG_JFFS2_ZLIB=y | ||
| 992 | CONFIG_JFFS2_LZO=y | ||
| 993 | CONFIG_JFFS2_RTIME=y | ||
| 994 | # CONFIG_JFFS2_RUBIN is not set | ||
| 995 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 996 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 997 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 998 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 999 | # CONFIG_CRAMFS is not set | ||
| 1000 | # CONFIG_VXFS_FS is not set | ||
| 1001 | # CONFIG_HPFS_FS is not set | ||
| 1002 | # CONFIG_QNX4FS_FS is not set | ||
| 1003 | # CONFIG_SYSV_FS is not set | ||
| 1004 | # CONFIG_UFS_FS is not set | ||
| 1005 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1006 | CONFIG_NFS_FS=y | ||
| 1007 | CONFIG_NFS_V3=y | ||
| 1008 | # CONFIG_NFS_V3_ACL is not set | ||
| 1009 | # CONFIG_NFS_V4 is not set | ||
| 1010 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1011 | # CONFIG_NFSD is not set | ||
| 1012 | CONFIG_ROOT_NFS=y | ||
| 1013 | CONFIG_LOCKD=y | ||
| 1014 | CONFIG_LOCKD_V4=y | ||
| 1015 | CONFIG_NFS_COMMON=y | ||
| 1016 | CONFIG_SUNRPC=y | ||
| 1017 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1018 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1019 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1020 | # CONFIG_SMB_FS is not set | ||
| 1021 | # CONFIG_CIFS is not set | ||
| 1022 | # CONFIG_NCP_FS is not set | ||
| 1023 | # CONFIG_CODA_FS is not set | ||
| 1024 | # CONFIG_AFS_FS is not set | ||
| 1025 | |||
| 1026 | # | ||
| 1027 | # Partition Types | ||
| 1028 | # | ||
| 1029 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 1030 | CONFIG_MSDOS_PARTITION=y | ||
| 1031 | CONFIG_NLS=y | ||
| 1032 | CONFIG_NLS_DEFAULT="utf8" | ||
| 1033 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1034 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1035 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1036 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1037 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1038 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1039 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1040 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1041 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1042 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1043 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1044 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1045 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1046 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1047 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1048 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1049 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1050 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1051 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1052 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1053 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1054 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1055 | CONFIG_NLS_CODEPAGE_1251=m | ||
| 1056 | # CONFIG_NLS_ASCII is not set | ||
| 1057 | CONFIG_NLS_ISO8859_1=y | ||
| 1058 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1059 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1060 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1061 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1062 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1063 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1064 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1065 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1066 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1067 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1068 | # CONFIG_NLS_KOI8_R is not set | ||
| 1069 | # CONFIG_NLS_KOI8_U is not set | ||
| 1070 | CONFIG_NLS_UTF8=y | ||
| 1071 | # CONFIG_DLM is not set | ||
| 1072 | |||
| 1073 | # | ||
| 1074 | # Kernel hacking | ||
| 1075 | # | ||
| 1076 | CONFIG_PRINTK_TIME=y | ||
| 1077 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1078 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1079 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1080 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1081 | # CONFIG_DEBUG_FS is not set | ||
| 1082 | # CONFIG_HEADERS_CHECK is not set | ||
| 1083 | CONFIG_DEBUG_KERNEL=y | ||
| 1084 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1085 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1086 | # CONFIG_SCHED_DEBUG is not set | ||
| 1087 | # CONFIG_SCHEDSTATS is not set | ||
| 1088 | CONFIG_TIMER_STATS=y | ||
| 1089 | # CONFIG_DEBUG_SLAB is not set | ||
| 1090 | CONFIG_DEBUG_PREEMPT=y | ||
| 1091 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1092 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1093 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1094 | CONFIG_DEBUG_MUTEXES=y | ||
| 1095 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1096 | # CONFIG_PROVE_LOCKING is not set | ||
| 1097 | # CONFIG_LOCK_STAT is not set | ||
| 1098 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1099 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1100 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1101 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1102 | # CONFIG_DEBUG_INFO is not set | ||
| 1103 | CONFIG_DEBUG_VM=y | ||
| 1104 | # CONFIG_DEBUG_LIST is not set | ||
| 1105 | # CONFIG_DEBUG_SG is not set | ||
| 1106 | CONFIG_FRAME_POINTER=y | ||
| 1107 | CONFIG_FORCED_INLINING=y | ||
| 1108 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1109 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1110 | # CONFIG_FAULT_INJECTION is not set | ||
| 1111 | # CONFIG_SAMPLES is not set | ||
| 1112 | CONFIG_DEBUG_USER=y | ||
| 1113 | CONFIG_DEBUG_ERRORS=y | ||
| 1114 | CONFIG_DEBUG_LL=y | ||
| 1115 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1116 | |||
| 1117 | # | ||
| 1118 | # Security options | ||
| 1119 | # | ||
| 1120 | # CONFIG_KEYS is not set | ||
| 1121 | # CONFIG_SECURITY is not set | ||
| 1122 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1123 | CONFIG_CRYPTO=y | ||
| 1124 | CONFIG_CRYPTO_ALGAPI=m | ||
| 1125 | CONFIG_CRYPTO_BLKCIPHER=m | ||
| 1126 | CONFIG_CRYPTO_MANAGER=m | ||
| 1127 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1128 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1129 | # CONFIG_CRYPTO_NULL is not set | ||
| 1130 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1131 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1132 | CONFIG_CRYPTO_SHA1=m | ||
| 1133 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1134 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1135 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1136 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1137 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1138 | CONFIG_CRYPTO_ECB=m | ||
| 1139 | # CONFIG_CRYPTO_CBC is not set | ||
| 1140 | CONFIG_CRYPTO_PCBC=m | ||
| 1141 | # CONFIG_CRYPTO_LRW is not set | ||
| 1142 | # CONFIG_CRYPTO_XTS is not set | ||
| 1143 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1144 | # CONFIG_CRYPTO_DES is not set | ||
| 1145 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1146 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1147 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1148 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1149 | # CONFIG_CRYPTO_AES is not set | ||
| 1150 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1151 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1152 | # CONFIG_CRYPTO_TEA is not set | ||
| 1153 | CONFIG_CRYPTO_ARC4=m | ||
| 1154 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1155 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1156 | # CONFIG_CRYPTO_SEED is not set | ||
| 1157 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1158 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1159 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1160 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1161 | # CONFIG_CRYPTO_TEST is not set | ||
| 1162 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1163 | # CONFIG_CRYPTO_HW is not set | ||
| 1164 | |||
| 1165 | # | ||
| 1166 | # Library routines | ||
| 1167 | # | ||
| 1168 | CONFIG_BITREVERSE=y | ||
| 1169 | CONFIG_CRC_CCITT=y | ||
| 1170 | # CONFIG_CRC16 is not set | ||
| 1171 | # CONFIG_CRC_ITU_T is not set | ||
| 1172 | CONFIG_CRC32=y | ||
| 1173 | # CONFIG_CRC7 is not set | ||
| 1174 | # CONFIG_LIBCRC32C is not set | ||
| 1175 | CONFIG_ZLIB_INFLATE=y | ||
| 1176 | CONFIG_ZLIB_DEFLATE=y | ||
| 1177 | CONFIG_LZO_COMPRESS=y | ||
| 1178 | CONFIG_LZO_DECOMPRESS=y | ||
| 1179 | CONFIG_PLIST=y | ||
| 1180 | CONFIG_HAS_IOMEM=y | ||
| 1181 | CONFIG_HAS_IOPORT=y | ||
| 1182 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig index 0e5794c6a48e..7dc1580e4d99 100644 --- a/arch/arm/configs/ns9xxx_defconfig +++ b/arch/arm/configs/ns9xxx_defconfig | |||
| @@ -1,621 +1,79 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.20 | ||
| 4 | # Thu Feb 15 20:51:47 2007 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | # CONFIG_GENERIC_TIME is not set | ||
| 8 | CONFIG_MMU=y | ||
| 9 | CONFIG_GENERIC_HARDIRQS=y | ||
| 10 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 11 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 12 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 13 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 14 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 15 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 16 | CONFIG_GENERIC_HWEIGHT=y | ||
| 17 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 18 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 19 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 20 | |||
| 21 | # | ||
| 22 | # Code maturity level options | ||
| 23 | # | ||
| 24 | CONFIG_EXPERIMENTAL=y | ||
| 25 | CONFIG_BROKEN_ON_SMP=y | ||
| 26 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 27 | |||
| 28 | # | ||
| 29 | # General setup | ||
| 30 | # | ||
| 31 | CONFIG_LOCALVERSION="" | ||
| 32 | CONFIG_LOCALVERSION_AUTO=y | ||
| 33 | CONFIG_SWAP=y | ||
| 34 | CONFIG_SYSVIPC=y | ||
| 35 | # CONFIG_IPC_NS is not set | ||
| 36 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 37 | # CONFIG_UTS_NS is not set | ||
| 38 | CONFIG_IKCONFIG=y | 1 | CONFIG_IKCONFIG=y |
| 39 | CONFIG_IKCONFIG_PROC=y | 2 | CONFIG_IKCONFIG_PROC=y |
| 40 | CONFIG_SYSFS_DEPRECATED=y | 3 | CONFIG_BLK_DEV_INITRD=y |
| 41 | # CONFIG_RELAY is not set | ||
| 42 | CONFIG_INITRAMFS_SOURCE="" | ||
| 43 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 44 | CONFIG_SYSCTL=y | ||
| 45 | CONFIG_EMBEDDED=y | ||
| 46 | CONFIG_UID16=y | ||
| 47 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 48 | CONFIG_KALLSYMS=y | ||
| 49 | # CONFIG_KALLSYMS_ALL is not set | ||
| 50 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 51 | CONFIG_HOTPLUG=y | ||
| 52 | CONFIG_PRINTK=y | ||
| 53 | CONFIG_BUG=y | ||
| 54 | CONFIG_ELF_CORE=y | ||
| 55 | CONFIG_BASE_FULL=y | ||
| 56 | CONFIG_FUTEX=y | ||
| 57 | CONFIG_EPOLL=y | ||
| 58 | CONFIG_SHMEM=y | ||
| 59 | CONFIG_SLAB=y | ||
| 60 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 61 | CONFIG_RT_MUTEXES=y | ||
| 62 | # CONFIG_TINY_SHMEM is not set | ||
| 63 | CONFIG_BASE_SMALL=0 | ||
| 64 | # CONFIG_SLOB is not set | ||
| 65 | |||
| 66 | # | ||
| 67 | # Loadable module support | ||
| 68 | # | ||
| 69 | CONFIG_MODULES=y | 4 | CONFIG_MODULES=y |
| 70 | CONFIG_MODULE_UNLOAD=y | 5 | CONFIG_MODULE_UNLOAD=y |
| 71 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 72 | CONFIG_MODVERSIONS=y | ||
| 73 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 74 | CONFIG_KMOD=y | ||
| 75 | |||
| 76 | # | ||
| 77 | # Block layer | ||
| 78 | # | ||
| 79 | CONFIG_BLOCK=y | ||
| 80 | # CONFIG_LBD is not set | ||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 82 | # CONFIG_LSF is not set | ||
| 83 | |||
| 84 | # | ||
| 85 | # IO Schedulers | ||
| 86 | # | ||
| 87 | CONFIG_IOSCHED_NOOP=y | ||
| 88 | # CONFIG_IOSCHED_AS is not set | 6 | # CONFIG_IOSCHED_AS is not set |
| 89 | # CONFIG_IOSCHED_DEADLINE is not set | 7 | # CONFIG_IOSCHED_DEADLINE is not set |
| 90 | # CONFIG_IOSCHED_CFQ is not set | 8 | # CONFIG_IOSCHED_CFQ is not set |
| 91 | # CONFIG_DEFAULT_AS is not set | ||
| 92 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 93 | # CONFIG_DEFAULT_CFQ is not set | ||
| 94 | CONFIG_DEFAULT_NOOP=y | ||
| 95 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 96 | |||
| 97 | # | ||
| 98 | # System Type | ||
| 99 | # | ||
| 100 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 101 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 102 | # CONFIG_ARCH_REALVIEW is not set | ||
| 103 | # CONFIG_ARCH_VERSATILE is not set | ||
| 104 | # CONFIG_ARCH_AT91 is not set | ||
| 105 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 106 | # CONFIG_ARCH_CLPS711X is not set | ||
| 107 | # CONFIG_ARCH_CO285 is not set | ||
| 108 | # CONFIG_ARCH_EBSA110 is not set | ||
| 109 | # CONFIG_ARCH_EP93XX is not set | ||
| 110 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 111 | # CONFIG_ARCH_NETX is not set | ||
| 112 | # CONFIG_ARCH_H720X is not set | ||
| 113 | # CONFIG_ARCH_IMX is not set | ||
| 114 | # CONFIG_ARCH_IOP32X is not set | ||
| 115 | # CONFIG_ARCH_IOP33X is not set | ||
| 116 | # CONFIG_ARCH_IOP13XX is not set | ||
| 117 | # CONFIG_ARCH_IXP4XX is not set | ||
| 118 | # CONFIG_ARCH_IXP2000 is not set | ||
| 119 | # CONFIG_ARCH_IXP23XX is not set | ||
| 120 | # CONFIG_ARCH_L7200 is not set | ||
| 121 | CONFIG_ARCH_NS9XXX=y | 9 | CONFIG_ARCH_NS9XXX=y |
| 122 | # CONFIG_ARCH_PNX4008 is not set | 10 | CONFIG_MACH_A9M9360=y |
| 123 | # CONFIG_ARCH_PXA is not set | 11 | CONFIG_MACH_A9M9750=y |
| 124 | # CONFIG_ARCH_RPC is not set | 12 | CONFIG_MACH_CC7UCAMRY=y |
| 125 | # CONFIG_ARCH_SA1100 is not set | 13 | CONFIG_MACH_CC9C=y |
| 126 | # CONFIG_ARCH_S3C2410 is not set | 14 | CONFIG_MACH_CC9P9210=y |
| 127 | # CONFIG_ARCH_SHARK is not set | 15 | CONFIG_MACH_CC9P9210JS=y |
| 128 | # CONFIG_ARCH_LH7A40X is not set | 16 | CONFIG_MACH_CC9P9215=y |
| 129 | # CONFIG_ARCH_OMAP is not set | 17 | CONFIG_MACH_CC9P9215JS=y |
| 130 | |||
| 131 | # | ||
| 132 | # NS9xxx Implementations | ||
| 133 | # | ||
| 134 | CONFIG_MACH_CC9P9360DEV=y | 18 | CONFIG_MACH_CC9P9360DEV=y |
| 135 | CONFIG_PROCESSOR_NS9360=y | 19 | CONFIG_MACH_CC9P9360JS=y |
| 136 | CONFIG_BOARD_A9M9750DEV=y | 20 | CONFIG_MACH_CC9P9360VAL=y |
| 137 | 21 | CONFIG_MACH_CC9P9750DEV=y | |
| 138 | # | 22 | CONFIG_MACH_CC9P9750VAL=y |
| 139 | # Processor Type | 23 | CONFIG_MACH_CCW9C=y |
| 140 | # | 24 | CONFIG_MACH_INC20OTTER=y |
| 141 | CONFIG_CPU_32=y | 25 | CONFIG_MACH_OTTER=y |
| 142 | CONFIG_CPU_ARM926T=y | 26 | CONFIG_NO_HZ=y |
| 143 | CONFIG_CPU_32v5=y | 27 | CONFIG_HIGH_RES_TIMERS=y |
| 144 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 145 | CONFIG_CPU_CACHE_VIVT=y | ||
| 146 | CONFIG_CPU_COPY_V4WB=y | ||
| 147 | CONFIG_CPU_TLB_V4WBI=y | ||
| 148 | CONFIG_CPU_CP15=y | ||
| 149 | CONFIG_CPU_CP15_MMU=y | ||
| 150 | |||
| 151 | # | ||
| 152 | # Processor Features | ||
| 153 | # | ||
| 154 | # CONFIG_ARM_THUMB is not set | ||
| 155 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 156 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 157 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 158 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 159 | |||
| 160 | # | ||
| 161 | # Bus support | ||
| 162 | # | ||
| 163 | |||
| 164 | # | ||
| 165 | # PCCARD (PCMCIA/CardBus) support | ||
| 166 | # | ||
| 167 | # CONFIG_PCCARD is not set | ||
| 168 | |||
| 169 | # | ||
| 170 | # Kernel Features | ||
| 171 | # | ||
| 172 | # CONFIG_PREEMPT is not set | ||
| 173 | # CONFIG_NO_IDLE_HZ is not set | ||
| 174 | CONFIG_HZ=100 | ||
| 175 | # CONFIG_AEABI is not set | ||
| 176 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 177 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 178 | CONFIG_FLATMEM_MANUAL=y | ||
| 179 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 180 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 181 | CONFIG_FLATMEM=y | ||
| 182 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 183 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 184 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 185 | # CONFIG_RESOURCES_64BIT is not set | ||
| 186 | CONFIG_ALIGNMENT_TRAP=y | ||
| 187 | |||
| 188 | # | ||
| 189 | # Boot options | ||
| 190 | # | ||
| 191 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 192 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 193 | CONFIG_CMDLINE="" | ||
| 194 | # CONFIG_XIP_KERNEL is not set | ||
| 195 | |||
| 196 | # | ||
| 197 | # Floating point emulation | ||
| 198 | # | ||
| 199 | |||
| 200 | # | ||
| 201 | # At least one emulation must be selected | ||
| 202 | # | ||
| 203 | CONFIG_FPE_NWFPE=y | 28 | CONFIG_FPE_NWFPE=y |
| 204 | # CONFIG_FPE_NWFPE_XP is not set | 29 | CONFIG_NET=y |
| 205 | # CONFIG_FPE_FASTFPE is not set | 30 | CONFIG_PACKET=m |
| 206 | # CONFIG_VFP is not set | 31 | CONFIG_INET=y |
| 207 | 32 | CONFIG_IP_PNP=y | |
| 208 | # | 33 | CONFIG_SYN_COOKIES=y |
| 209 | # Userspace binary formats | 34 | CONFIG_MTD=m |
| 210 | # | 35 | CONFIG_MTD_CONCAT=m |
| 211 | CONFIG_BINFMT_ELF=y | 36 | CONFIG_MTD_CHAR=m |
| 212 | # CONFIG_BINFMT_AOUT is not set | 37 | CONFIG_MTD_BLOCK=m |
| 213 | # CONFIG_BINFMT_MISC is not set | 38 | CONFIG_MTD_CFI=m |
| 214 | # CONFIG_ARTHUR is not set | 39 | CONFIG_MTD_JEDECPROBE=m |
| 215 | 40 | CONFIG_MTD_CFI_AMDSTD=m | |
| 216 | # | 41 | CONFIG_MTD_PHYSMAP=m |
| 217 | # Power management options | 42 | CONFIG_MTD_PHYSMAP_START=0x0 |
| 218 | # | 43 | CONFIG_BLK_DEV_LOOP=m |
| 219 | # CONFIG_PM is not set | 44 | CONFIG_NETDEVICES=y |
| 220 | # CONFIG_APM is not set | 45 | CONFIG_NET_ETHERNET=y |
| 221 | 46 | CONFIG_NS9XXX_ETH=y | |
| 222 | # | ||
| 223 | # Networking | ||
| 224 | # | ||
| 225 | # CONFIG_NET is not set | ||
| 226 | |||
| 227 | # | ||
| 228 | # Device Drivers | ||
| 229 | # | ||
| 230 | |||
| 231 | # | ||
| 232 | # Generic Driver Options | ||
| 233 | # | ||
| 234 | CONFIG_STANDALONE=y | ||
| 235 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 236 | # CONFIG_FW_LOADER is not set | ||
| 237 | # CONFIG_DEBUG_DRIVER is not set | ||
| 238 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 239 | |||
| 240 | # | ||
| 241 | # Connector - unified userspace <-> kernelspace linker | ||
| 242 | # | ||
| 243 | |||
| 244 | # | ||
| 245 | # Memory Technology Devices (MTD) | ||
| 246 | # | ||
| 247 | # CONFIG_MTD is not set | ||
| 248 | |||
| 249 | # | ||
| 250 | # Parallel port support | ||
| 251 | # | ||
| 252 | # CONFIG_PARPORT is not set | ||
| 253 | |||
| 254 | # | ||
| 255 | # Plug and Play support | ||
| 256 | # | ||
| 257 | |||
| 258 | # | ||
| 259 | # Block devices | ||
| 260 | # | ||
| 261 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 262 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 263 | CONFIG_BLK_DEV_RAM=y | ||
| 264 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 265 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 266 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | ||
| 267 | CONFIG_BLK_DEV_INITRD=y | ||
| 268 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 269 | |||
| 270 | # | ||
| 271 | # SCSI device support | ||
| 272 | # | ||
| 273 | # CONFIG_RAID_ATTRS is not set | ||
| 274 | # CONFIG_SCSI is not set | ||
| 275 | # CONFIG_SCSI_NETLINK is not set | ||
| 276 | |||
| 277 | # | ||
| 278 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
| 279 | # | ||
| 280 | # CONFIG_ATA is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Multi-device support (RAID and LVM) | ||
| 284 | # | ||
| 285 | # CONFIG_MD is not set | ||
| 286 | |||
| 287 | # | ||
| 288 | # Fusion MPT device support | ||
| 289 | # | ||
| 290 | # CONFIG_FUSION is not set | ||
| 291 | |||
| 292 | # | ||
| 293 | # IEEE 1394 (FireWire) support | ||
| 294 | # | ||
| 295 | |||
| 296 | # | ||
| 297 | # I2O device support | ||
| 298 | # | ||
| 299 | |||
| 300 | # | ||
| 301 | # ISDN subsystem | ||
| 302 | # | ||
| 303 | |||
| 304 | # | ||
| 305 | # Input device support | ||
| 306 | # | ||
| 307 | CONFIG_INPUT=y | ||
| 308 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 309 | |||
| 310 | # | ||
| 311 | # Userland interfaces | ||
| 312 | # | ||
| 313 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 314 | # CONFIG_INPUT_JOYDEV is not set | ||
| 315 | # CONFIG_INPUT_TSDEV is not set | ||
| 316 | # CONFIG_INPUT_EVDEV is not set | ||
| 317 | # CONFIG_INPUT_EVBUG is not set | ||
| 318 | |||
| 319 | # | ||
| 320 | # Input Device Drivers | ||
| 321 | # | ||
| 322 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 323 | # CONFIG_INPUT_MOUSE is not set | ||
| 324 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 325 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 326 | # CONFIG_INPUT_MISC is not set | ||
| 327 | |||
| 328 | # | ||
| 329 | # Hardware I/O ports | ||
| 330 | # | ||
| 331 | CONFIG_SERIO=y | ||
| 332 | # CONFIG_SERIO_SERPORT is not set | 47 | # CONFIG_SERIO_SERPORT is not set |
| 333 | CONFIG_SERIO_LIBPS2=y | ||
| 334 | # CONFIG_SERIO_RAW is not set | ||
| 335 | # CONFIG_GAMEPORT is not set | ||
| 336 | |||
| 337 | # | ||
| 338 | # Character devices | ||
| 339 | # | ||
| 340 | CONFIG_VT=y | ||
| 341 | CONFIG_VT_CONSOLE=y | ||
| 342 | CONFIG_HW_CONSOLE=y | ||
| 343 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 344 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 345 | |||
| 346 | # | ||
| 347 | # Serial drivers | ||
| 348 | # | ||
| 349 | CONFIG_SERIAL_8250=y | 48 | CONFIG_SERIAL_8250=y |
| 350 | CONFIG_SERIAL_8250_CONSOLE=y | 49 | CONFIG_SERIAL_8250_CONSOLE=y |
| 351 | CONFIG_SERIAL_8250_NR_UARTS=4 | 50 | CONFIG_SERIAL_NS921X=y |
| 352 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | 51 | CONFIG_SERIAL_NS921X_CONSOLE=y |
| 353 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 354 | # CONFIG_SERIAL_8250_MANY_PORTS is not set | ||
| 355 | # CONFIG_SERIAL_8250_SHARE_IRQ is not set | ||
| 356 | # CONFIG_SERIAL_8250_DETECT_IRQ is not set | ||
| 357 | # CONFIG_SERIAL_8250_RSA is not set | ||
| 358 | |||
| 359 | # | ||
| 360 | # Non-8250 serial port support | ||
| 361 | # | ||
| 362 | CONFIG_SERIAL_CORE=y | ||
| 363 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 364 | CONFIG_UNIX98_PTYS=y | ||
| 365 | # CONFIG_LEGACY_PTYS is not set | 52 | # CONFIG_LEGACY_PTYS is not set |
| 366 | |||
| 367 | # | ||
| 368 | # IPMI | ||
| 369 | # | ||
| 370 | # CONFIG_IPMI_HANDLER is not set | ||
| 371 | |||
| 372 | # | ||
| 373 | # Watchdog Cards | ||
| 374 | # | ||
| 375 | # CONFIG_WATCHDOG is not set | ||
| 376 | # CONFIG_HW_RANDOM is not set | 53 | # CONFIG_HW_RANDOM is not set |
| 377 | # CONFIG_NVRAM is not set | 54 | CONFIG_ADC_NS9215=m |
| 378 | # CONFIG_DTLK is not set | 55 | CONFIG_I2C=m |
| 379 | # CONFIG_R3964 is not set | 56 | CONFIG_I2C_GPIO=m |
| 380 | # CONFIG_RAW_DRIVER is not set | ||
| 381 | |||
| 382 | # | ||
| 383 | # TPM devices | ||
| 384 | # | ||
| 385 | # CONFIG_TCG_TPM is not set | ||
| 386 | |||
| 387 | # | ||
| 388 | # I2C support | ||
| 389 | # | ||
| 390 | # CONFIG_I2C is not set | ||
| 391 | |||
| 392 | # | ||
| 393 | # SPI support | ||
| 394 | # | ||
| 395 | # CONFIG_SPI is not set | ||
| 396 | # CONFIG_SPI_MASTER is not set | ||
| 397 | |||
| 398 | # | ||
| 399 | # Dallas's 1-wire bus | ||
| 400 | # | ||
| 401 | # CONFIG_W1 is not set | ||
| 402 | |||
| 403 | # | ||
| 404 | # Hardware Monitoring support | ||
| 405 | # | ||
| 406 | # CONFIG_HWMON is not set | 57 | # CONFIG_HWMON is not set |
| 407 | # CONFIG_HWMON_VID is not set | ||
| 408 | |||
| 409 | # | ||
| 410 | # Misc devices | ||
| 411 | # | ||
| 412 | # CONFIG_TIFM_CORE is not set | ||
| 413 | |||
| 414 | # | ||
| 415 | # LED devices | ||
| 416 | # | ||
| 417 | # CONFIG_NEW_LEDS is not set | ||
| 418 | |||
| 419 | # | ||
| 420 | # LED drivers | ||
| 421 | # | ||
| 422 | |||
| 423 | # | ||
| 424 | # LED Triggers | ||
| 425 | # | ||
| 426 | |||
| 427 | # | ||
| 428 | # Multimedia devices | ||
| 429 | # | ||
| 430 | # CONFIG_VIDEO_DEV is not set | ||
| 431 | |||
| 432 | # | ||
| 433 | # Digital Video Broadcasting Devices | ||
| 434 | # | ||
| 435 | |||
| 436 | # | ||
| 437 | # Graphics support | ||
| 438 | # | ||
| 439 | # CONFIG_FIRMWARE_EDID is not set | ||
| 440 | # CONFIG_FB is not set | ||
| 441 | |||
| 442 | # | ||
| 443 | # Console display driver support | ||
| 444 | # | ||
| 445 | # CONFIG_VGA_CONSOLE is not set | 58 | # CONFIG_VGA_CONSOLE is not set |
| 446 | CONFIG_DUMMY_CONSOLE=y | 59 | # CONFIG_HID_DEBUG is not set |
| 447 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 60 | # CONFIG_USB_SUPPORT is not set |
| 448 | 61 | CONFIG_NEW_LEDS=y | |
| 449 | # | 62 | CONFIG_LEDS_CLASS=m |
| 450 | # Sound | 63 | CONFIG_LEDS_GPIO=m |
| 451 | # | 64 | CONFIG_LEDS_TRIGGERS=y |
| 452 | # CONFIG_SOUND is not set | 65 | CONFIG_LEDS_TRIGGER_TIMER=m |
| 453 | 66 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m | |
| 454 | # | 67 | CONFIG_RTC_CLASS=m |
| 455 | # HID Devices | 68 | CONFIG_RTC_DRV_NS9215=m |
| 456 | # | 69 | CONFIG_EXT2_FS=m |
| 457 | CONFIG_HID=y | ||
| 458 | |||
| 459 | # | ||
| 460 | # USB support | ||
| 461 | # | ||
| 462 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 463 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
| 464 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 465 | # CONFIG_USB is not set | ||
| 466 | |||
| 467 | # | ||
| 468 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 469 | # | ||
| 470 | |||
| 471 | # | ||
| 472 | # USB Gadget Support | ||
| 473 | # | ||
| 474 | # CONFIG_USB_GADGET is not set | ||
| 475 | |||
| 476 | # | ||
| 477 | # MMC/SD Card support | ||
| 478 | # | ||
| 479 | # CONFIG_MMC is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Real Time Clock | ||
| 483 | # | ||
| 484 | CONFIG_RTC_LIB=y | ||
| 485 | # CONFIG_RTC_CLASS is not set | ||
| 486 | |||
| 487 | # | ||
| 488 | # File systems | ||
| 489 | # | ||
| 490 | CONFIG_EXT2_FS=y | ||
| 491 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 492 | # CONFIG_EXT2_FS_XIP is not set | ||
| 493 | # CONFIG_EXT3_FS is not set | ||
| 494 | # CONFIG_EXT4DEV_FS is not set | ||
| 495 | # CONFIG_REISERFS_FS is not set | ||
| 496 | # CONFIG_JFS_FS is not set | ||
| 497 | # CONFIG_FS_POSIX_ACL is not set | ||
| 498 | # CONFIG_XFS_FS is not set | ||
| 499 | # CONFIG_GFS2_FS is not set | ||
| 500 | # CONFIG_MINIX_FS is not set | ||
| 501 | # CONFIG_ROMFS_FS is not set | ||
| 502 | CONFIG_INOTIFY=y | ||
| 503 | CONFIG_INOTIFY_USER=y | ||
| 504 | # CONFIG_QUOTA is not set | ||
| 505 | # CONFIG_DNOTIFY is not set | ||
| 506 | # CONFIG_AUTOFS_FS is not set | ||
| 507 | # CONFIG_AUTOFS4_FS is not set | ||
| 508 | # CONFIG_FUSE_FS is not set | ||
| 509 | |||
| 510 | # | ||
| 511 | # CD-ROM/DVD Filesystems | ||
| 512 | # | ||
| 513 | # CONFIG_ISO9660_FS is not set | ||
| 514 | # CONFIG_UDF_FS is not set | ||
| 515 | |||
| 516 | # | ||
| 517 | # DOS/FAT/NT Filesystems | ||
| 518 | # | ||
| 519 | # CONFIG_MSDOS_FS is not set | ||
| 520 | # CONFIG_VFAT_FS is not set | ||
| 521 | # CONFIG_NTFS_FS is not set | ||
| 522 | |||
| 523 | # | ||
| 524 | # Pseudo filesystems | ||
| 525 | # | ||
| 526 | CONFIG_PROC_FS=y | ||
| 527 | CONFIG_PROC_SYSCTL=y | ||
| 528 | CONFIG_SYSFS=y | ||
| 529 | CONFIG_TMPFS=y | 70 | CONFIG_TMPFS=y |
| 530 | # CONFIG_TMPFS_POSIX_ACL is not set | 71 | CONFIG_JFFS2_FS=m |
| 531 | # CONFIG_HUGETLB_PAGE is not set | 72 | CONFIG_NFS_FS=y |
| 532 | CONFIG_RAMFS=y | 73 | CONFIG_ROOT_NFS=y |
| 533 | # CONFIG_CONFIGFS_FS is not set | ||
| 534 | |||
| 535 | # | ||
| 536 | # Miscellaneous filesystems | ||
| 537 | # | ||
| 538 | # CONFIG_ADFS_FS is not set | ||
| 539 | # CONFIG_AFFS_FS is not set | ||
| 540 | # CONFIG_HFS_FS is not set | ||
| 541 | # CONFIG_HFSPLUS_FS is not set | ||
| 542 | # CONFIG_BEFS_FS is not set | ||
| 543 | # CONFIG_BFS_FS is not set | ||
| 544 | # CONFIG_EFS_FS is not set | ||
| 545 | # CONFIG_CRAMFS is not set | ||
| 546 | # CONFIG_VXFS_FS is not set | ||
| 547 | # CONFIG_HPFS_FS is not set | ||
| 548 | # CONFIG_QNX4FS_FS is not set | ||
| 549 | # CONFIG_SYSV_FS is not set | ||
| 550 | # CONFIG_UFS_FS is not set | ||
| 551 | |||
| 552 | # | ||
| 553 | # Partition Types | ||
| 554 | # | ||
| 555 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 556 | CONFIG_MSDOS_PARTITION=y | ||
| 557 | |||
| 558 | # | ||
| 559 | # Native Language Support | ||
| 560 | # | ||
| 561 | # CONFIG_NLS is not set | ||
| 562 | |||
| 563 | # | ||
| 564 | # Profiling support | ||
| 565 | # | ||
| 566 | # CONFIG_PROFILING is not set | ||
| 567 | |||
| 568 | # | ||
| 569 | # Kernel hacking | ||
| 570 | # | ||
| 571 | # CONFIG_PRINTK_TIME is not set | ||
| 572 | # CONFIG_ENABLE_MUST_CHECK is not set | 74 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 573 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 574 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 575 | # CONFIG_DEBUG_FS is not set | ||
| 576 | # CONFIG_HEADERS_CHECK is not set | ||
| 577 | CONFIG_DEBUG_KERNEL=y | 75 | CONFIG_DEBUG_KERNEL=y |
| 578 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 579 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 580 | # CONFIG_SCHEDSTATS is not set | ||
| 581 | # CONFIG_DEBUG_SLAB is not set | ||
| 582 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 583 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 584 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 585 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 586 | # CONFIG_DEBUG_RWSEMS is not set | ||
| 587 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 588 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 589 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 590 | CONFIG_DEBUG_BUGVERBOSE=y | 76 | CONFIG_DEBUG_BUGVERBOSE=y |
| 591 | CONFIG_DEBUG_INFO=y | 77 | CONFIG_DEBUG_INFO=y |
| 592 | # CONFIG_DEBUG_VM is not set | ||
| 593 | # CONFIG_DEBUG_LIST is not set | ||
| 594 | CONFIG_FRAME_POINTER=y | ||
| 595 | CONFIG_FORCED_INLINING=y | ||
| 596 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 597 | CONFIG_DEBUG_USER=y | 78 | CONFIG_DEBUG_USER=y |
| 598 | CONFIG_DEBUG_ERRORS=y | 79 | CONFIG_DEBUG_ERRORS=y |
| 599 | CONFIG_DEBUG_LL=y | ||
| 600 | CONFIG_DEBUG_ICEDCC=y | ||
| 601 | |||
| 602 | # | ||
| 603 | # Security options | ||
| 604 | # | ||
| 605 | # CONFIG_KEYS is not set | ||
| 606 | # CONFIG_SECURITY is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # Cryptographic options | ||
| 610 | # | ||
| 611 | # CONFIG_CRYPTO is not set | ||
| 612 | |||
| 613 | # | ||
| 614 | # Library routines | ||
| 615 | # | ||
| 616 | # CONFIG_CRC_CCITT is not set | ||
| 617 | # CONFIG_CRC16 is not set | ||
| 618 | # CONFIG_CRC32 is not set | ||
| 619 | # CONFIG_LIBCRC32C is not set | ||
| 620 | CONFIG_PLIST=y | ||
| 621 | CONFIG_IOMAP_COPY=y | ||
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig index 1e5aaa645fcd..52cd99bd52fb 100644 --- a/arch/arm/configs/orion_defconfig +++ b/arch/arm/configs/orion5x_defconfig | |||
| @@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y | |||
| 140 | # CONFIG_ARCH_KS8695 is not set | 140 | # CONFIG_ARCH_KS8695 is not set |
| 141 | # CONFIG_ARCH_NS9XXX is not set | 141 | # CONFIG_ARCH_NS9XXX is not set |
| 142 | # CONFIG_ARCH_MXC is not set | 142 | # CONFIG_ARCH_MXC is not set |
| 143 | CONFIG_ARCH_ORION=y | 143 | CONFIG_ARCH_ORION5X=y |
| 144 | # CONFIG_ARCH_PNX4008 is not set | 144 | # CONFIG_ARCH_PNX4008 is not set |
| 145 | # CONFIG_ARCH_PXA is not set | 145 | # CONFIG_ARCH_PXA is not set |
| 146 | # CONFIG_ARCH_RPC is not set | 146 | # CONFIG_ARCH_RPC is not set |
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig new file mode 100644 index 000000000000..576b8339f0d6 --- /dev/null +++ b/arch/arm/configs/tct_hammer_defconfig | |||
| @@ -0,0 +1,886 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.25-rc7-hammer | ||
| 4 | # Thu Mar 27 16:39:48 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | CONFIG_NO_IOPORT=y | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | CONFIG_LOCALVERSION="" | ||
| 36 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 37 | # CONFIG_SWAP is not set | ||
| 38 | CONFIG_SYSVIPC=y | ||
| 39 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 40 | # CONFIG_POSIX_MQUEUE is not set | ||
| 41 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 42 | # CONFIG_TASKSTATS is not set | ||
| 43 | # CONFIG_AUDIT is not set | ||
| 44 | # CONFIG_IKCONFIG is not set | ||
| 45 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 46 | # CONFIG_CGROUPS is not set | ||
| 47 | CONFIG_GROUP_SCHED=y | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 50 | CONFIG_USER_SCHED=y | ||
| 51 | # CONFIG_CGROUP_SCHED is not set | ||
| 52 | CONFIG_SYSFS_DEPRECATED=y | ||
| 53 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 54 | # CONFIG_RELAY is not set | ||
| 55 | # CONFIG_NAMESPACES is not set | ||
| 56 | CONFIG_BLK_DEV_INITRD=y | ||
| 57 | CONFIG_INITRAMFS_SOURCE="" | ||
| 58 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 59 | CONFIG_SYSCTL=y | ||
| 60 | CONFIG_EMBEDDED=y | ||
| 61 | CONFIG_UID16=y | ||
| 62 | CONFIG_SYSCTL_SYSCALL=y | ||
| 63 | # CONFIG_KALLSYMS is not set | ||
| 64 | CONFIG_HOTPLUG=y | ||
| 65 | CONFIG_PRINTK=y | ||
| 66 | # CONFIG_BUG is not set | ||
| 67 | # CONFIG_ELF_CORE is not set | ||
| 68 | CONFIG_COMPAT_BRK=y | ||
| 69 | CONFIG_BASE_FULL=y | ||
| 70 | CONFIG_FUTEX=y | ||
| 71 | CONFIG_ANON_INODES=y | ||
| 72 | CONFIG_EPOLL=y | ||
| 73 | CONFIG_SIGNALFD=y | ||
| 74 | CONFIG_TIMERFD=y | ||
| 75 | CONFIG_EVENTFD=y | ||
| 76 | # CONFIG_SHMEM is not set | ||
| 77 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 78 | # CONFIG_SLAB is not set | ||
| 79 | # CONFIG_SLUB is not set | ||
| 80 | CONFIG_SLOB=y | ||
| 81 | # CONFIG_PROFILING is not set | ||
| 82 | # CONFIG_MARKERS is not set | ||
| 83 | CONFIG_HAVE_OPROFILE=y | ||
| 84 | CONFIG_HAVE_KPROBES=y | ||
| 85 | CONFIG_HAVE_KRETPROBES=y | ||
| 86 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 87 | CONFIG_RT_MUTEXES=y | ||
| 88 | CONFIG_TINY_SHMEM=y | ||
| 89 | CONFIG_BASE_SMALL=0 | ||
| 90 | CONFIG_MODULES=y | ||
| 91 | CONFIG_MODULE_UNLOAD=y | ||
| 92 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 93 | # CONFIG_MODVERSIONS is not set | ||
| 94 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 95 | # CONFIG_KMOD is not set | ||
| 96 | CONFIG_BLOCK=y | ||
| 97 | # CONFIG_LBD is not set | ||
| 98 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 99 | # CONFIG_LSF is not set | ||
| 100 | # CONFIG_BLK_DEV_BSG is not set | ||
| 101 | |||
| 102 | # | ||
| 103 | # IO Schedulers | ||
| 104 | # | ||
| 105 | CONFIG_IOSCHED_NOOP=y | ||
| 106 | CONFIG_IOSCHED_AS=y | ||
| 107 | CONFIG_IOSCHED_DEADLINE=y | ||
| 108 | CONFIG_IOSCHED_CFQ=y | ||
| 109 | CONFIG_DEFAULT_AS=y | ||
| 110 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 111 | # CONFIG_DEFAULT_CFQ is not set | ||
| 112 | # CONFIG_DEFAULT_NOOP is not set | ||
| 113 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 114 | CONFIG_CLASSIC_RCU=y | ||
| 115 | |||
| 116 | # | ||
| 117 | # System Type | ||
| 118 | # | ||
| 119 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 120 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 121 | # CONFIG_ARCH_REALVIEW is not set | ||
| 122 | # CONFIG_ARCH_VERSATILE is not set | ||
| 123 | # CONFIG_ARCH_AT91 is not set | ||
| 124 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 125 | # CONFIG_ARCH_CLPS711X is not set | ||
| 126 | # CONFIG_ARCH_CO285 is not set | ||
| 127 | # CONFIG_ARCH_EBSA110 is not set | ||
| 128 | # CONFIG_ARCH_EP93XX is not set | ||
| 129 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 130 | # CONFIG_ARCH_NETX is not set | ||
| 131 | # CONFIG_ARCH_H720X is not set | ||
| 132 | # CONFIG_ARCH_IMX is not set | ||
| 133 | # CONFIG_ARCH_IOP13XX is not set | ||
| 134 | # CONFIG_ARCH_IOP32X is not set | ||
| 135 | # CONFIG_ARCH_IOP33X is not set | ||
| 136 | # CONFIG_ARCH_IXP23XX is not set | ||
| 137 | # CONFIG_ARCH_IXP2000 is not set | ||
| 138 | # CONFIG_ARCH_IXP4XX is not set | ||
| 139 | # CONFIG_ARCH_L7200 is not set | ||
| 140 | # CONFIG_ARCH_KS8695 is not set | ||
| 141 | # CONFIG_ARCH_NS9XXX is not set | ||
| 142 | # CONFIG_ARCH_MXC is not set | ||
| 143 | # CONFIG_ARCH_ORION is not set | ||
| 144 | # CONFIG_ARCH_PNX4008 is not set | ||
| 145 | # CONFIG_ARCH_PXA is not set | ||
| 146 | # CONFIG_ARCH_RPC is not set | ||
| 147 | # CONFIG_ARCH_SA1100 is not set | ||
| 148 | CONFIG_ARCH_S3C2410=y | ||
| 149 | # CONFIG_ARCH_SHARK is not set | ||
| 150 | # CONFIG_ARCH_LH7A40X is not set | ||
| 151 | # CONFIG_ARCH_DAVINCI is not set | ||
| 152 | # CONFIG_ARCH_OMAP is not set | ||
| 153 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 154 | CONFIG_PLAT_S3C24XX=y | ||
| 155 | # CONFIG_S3C2410_DMA is not set | ||
| 156 | CONFIG_PLAT_S3C=y | ||
| 157 | CONFIG_CPU_LLSERIAL_S3C2410_ONLY=y | ||
| 158 | CONFIG_CPU_LLSERIAL_S3C2410=y | ||
| 159 | |||
| 160 | # | ||
| 161 | # Boot options | ||
| 162 | # | ||
| 163 | # CONFIG_S3C_BOOT_ERROR_RESET is not set | ||
| 164 | |||
| 165 | # | ||
| 166 | # Power management | ||
| 167 | # | ||
| 168 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
| 169 | |||
| 170 | # | ||
| 171 | # S3C2400 Machines | ||
| 172 | # | ||
| 173 | CONFIG_CPU_S3C2410=y | ||
| 174 | CONFIG_S3C2410_GPIO=y | ||
| 175 | CONFIG_S3C2410_CLOCK=y | ||
| 176 | |||
| 177 | # | ||
| 178 | # S3C2410 Machines | ||
| 179 | # | ||
| 180 | # CONFIG_ARCH_SMDK2410 is not set | ||
| 181 | # CONFIG_ARCH_H1940 is not set | ||
| 182 | # CONFIG_MACH_N30 is not set | ||
| 183 | # CONFIG_ARCH_BAST is not set | ||
| 184 | # CONFIG_MACH_OTOM is not set | ||
| 185 | # CONFIG_MACH_AML_M5900 is not set | ||
| 186 | CONFIG_MACH_TCT_HAMMER=y | ||
| 187 | # CONFIG_MACH_VR1000 is not set | ||
| 188 | # CONFIG_MACH_QT2410 is not set | ||
| 189 | |||
| 190 | # | ||
| 191 | # S3C2412 Machines | ||
| 192 | # | ||
| 193 | # CONFIG_MACH_SMDK2413 is not set | ||
| 194 | # CONFIG_MACH_SMDK2412 is not set | ||
| 195 | # CONFIG_MACH_VSTMS is not set | ||
| 196 | |||
| 197 | # | ||
| 198 | # S3C2440 Machines | ||
| 199 | # | ||
| 200 | # CONFIG_MACH_ANUBIS is not set | ||
| 201 | # CONFIG_MACH_OSIRIS is not set | ||
| 202 | # CONFIG_MACH_RX3715 is not set | ||
| 203 | # CONFIG_ARCH_S3C2440 is not set | ||
| 204 | # CONFIG_MACH_NEXCODER_2440 is not set | ||
| 205 | |||
| 206 | # | ||
| 207 | # S3C2442 Machines | ||
| 208 | # | ||
| 209 | |||
| 210 | # | ||
| 211 | # S3C2443 Machines | ||
| 212 | # | ||
| 213 | # CONFIG_MACH_SMDK2443 is not set | ||
| 214 | |||
| 215 | # | ||
| 216 | # Processor Type | ||
| 217 | # | ||
| 218 | CONFIG_CPU_32=y | ||
| 219 | CONFIG_CPU_ARM920T=y | ||
| 220 | CONFIG_CPU_32v4T=y | ||
| 221 | CONFIG_CPU_ABRT_EV4T=y | ||
| 222 | CONFIG_CPU_CACHE_V4WT=y | ||
| 223 | CONFIG_CPU_CACHE_VIVT=y | ||
| 224 | CONFIG_CPU_COPY_V4WB=y | ||
| 225 | CONFIG_CPU_TLB_V4WBI=y | ||
| 226 | CONFIG_CPU_CP15=y | ||
| 227 | CONFIG_CPU_CP15_MMU=y | ||
| 228 | |||
| 229 | # | ||
| 230 | # Processor Features | ||
| 231 | # | ||
| 232 | CONFIG_ARM_THUMB=y | ||
| 233 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 234 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 235 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 236 | # CONFIG_OUTER_CACHE is not set | ||
| 237 | |||
| 238 | # | ||
| 239 | # Bus support | ||
| 240 | # | ||
| 241 | # CONFIG_PCI_SYSCALL is not set | ||
| 242 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 243 | # CONFIG_PCCARD is not set | ||
| 244 | |||
| 245 | # | ||
| 246 | # Kernel Features | ||
| 247 | # | ||
| 248 | # CONFIG_TICK_ONESHOT is not set | ||
| 249 | # CONFIG_PREEMPT is not set | ||
| 250 | # CONFIG_NO_IDLE_HZ is not set | ||
| 251 | CONFIG_HZ=200 | ||
| 252 | # CONFIG_AEABI is not set | ||
| 253 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 254 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 255 | CONFIG_FLATMEM_MANUAL=y | ||
| 256 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 257 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 258 | CONFIG_FLATMEM=y | ||
| 259 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 260 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 261 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 262 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 263 | # CONFIG_RESOURCES_64BIT is not set | ||
| 264 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 265 | CONFIG_BOUNCE=y | ||
| 266 | CONFIG_VIRT_TO_BUS=y | ||
| 267 | CONFIG_ALIGNMENT_TRAP=y | ||
| 268 | |||
| 269 | # | ||
| 270 | # Boot options | ||
| 271 | # | ||
| 272 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 273 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 274 | CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw" | ||
| 275 | # CONFIG_XIP_KERNEL is not set | ||
| 276 | # CONFIG_KEXEC is not set | ||
| 277 | |||
| 278 | # | ||
| 279 | # Floating point emulation | ||
| 280 | # | ||
| 281 | |||
| 282 | # | ||
| 283 | # At least one emulation must be selected | ||
| 284 | # | ||
| 285 | CONFIG_FPE_NWFPE=y | ||
| 286 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 287 | # CONFIG_FPE_FASTFPE is not set | ||
| 288 | |||
| 289 | # | ||
| 290 | # Userspace binary formats | ||
| 291 | # | ||
| 292 | CONFIG_BINFMT_ELF=y | ||
| 293 | # CONFIG_BINFMT_AOUT is not set | ||
| 294 | # CONFIG_BINFMT_MISC is not set | ||
| 295 | # CONFIG_ARTHUR is not set | ||
| 296 | |||
| 297 | # | ||
| 298 | # Power management options | ||
| 299 | # | ||
| 300 | # CONFIG_PM is not set | ||
| 301 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 302 | |||
| 303 | # | ||
| 304 | # Networking | ||
| 305 | # | ||
| 306 | CONFIG_NET=y | ||
| 307 | |||
| 308 | # | ||
| 309 | # Networking options | ||
| 310 | # | ||
| 311 | CONFIG_PACKET=y | ||
| 312 | # CONFIG_PACKET_MMAP is not set | ||
| 313 | CONFIG_UNIX=y | ||
| 314 | # CONFIG_NET_KEY is not set | ||
| 315 | # CONFIG_INET is not set | ||
| 316 | # CONFIG_NETWORK_SECMARK is not set | ||
| 317 | # CONFIG_NETFILTER is not set | ||
| 318 | # CONFIG_ATM is not set | ||
| 319 | # CONFIG_BRIDGE is not set | ||
| 320 | # CONFIG_VLAN_8021Q is not set | ||
| 321 | # CONFIG_DECNET is not set | ||
| 322 | # CONFIG_LLC2 is not set | ||
| 323 | # CONFIG_IPX is not set | ||
| 324 | # CONFIG_ATALK is not set | ||
| 325 | # CONFIG_X25 is not set | ||
| 326 | # CONFIG_LAPB is not set | ||
| 327 | # CONFIG_WAN_ROUTER is not set | ||
| 328 | # CONFIG_NET_SCHED is not set | ||
| 329 | |||
| 330 | # | ||
| 331 | # Network testing | ||
| 332 | # | ||
| 333 | # CONFIG_NET_PKTGEN is not set | ||
| 334 | # CONFIG_HAMRADIO is not set | ||
| 335 | # CONFIG_CAN is not set | ||
| 336 | # CONFIG_IRDA is not set | ||
| 337 | # CONFIG_BT is not set | ||
| 338 | |||
| 339 | # | ||
| 340 | # Wireless | ||
| 341 | # | ||
| 342 | # CONFIG_CFG80211 is not set | ||
| 343 | # CONFIG_WIRELESS_EXT is not set | ||
| 344 | # CONFIG_MAC80211 is not set | ||
| 345 | # CONFIG_IEEE80211 is not set | ||
| 346 | # CONFIG_RFKILL is not set | ||
| 347 | # CONFIG_NET_9P is not set | ||
| 348 | |||
| 349 | # | ||
| 350 | # Device Drivers | ||
| 351 | # | ||
| 352 | |||
| 353 | # | ||
| 354 | # Generic Driver Options | ||
| 355 | # | ||
| 356 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 357 | CONFIG_STANDALONE=y | ||
| 358 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 359 | CONFIG_FW_LOADER=y | ||
| 360 | # CONFIG_DEBUG_DRIVER is not set | ||
| 361 | # CONFIG_DEBUG_DEVRES is not set | ||
| 362 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 363 | # CONFIG_CONNECTOR is not set | ||
| 364 | CONFIG_MTD=y | ||
| 365 | # CONFIG_MTD_DEBUG is not set | ||
| 366 | # CONFIG_MTD_CONCAT is not set | ||
| 367 | CONFIG_MTD_PARTITIONS=y | ||
| 368 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 369 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 370 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 371 | |||
| 372 | # | ||
| 373 | # User Modules And Translation Layers | ||
| 374 | # | ||
| 375 | CONFIG_MTD_CHAR=y | ||
| 376 | CONFIG_MTD_BLKDEVS=y | ||
| 377 | CONFIG_MTD_BLOCK=y | ||
| 378 | # CONFIG_FTL is not set | ||
| 379 | # CONFIG_NFTL is not set | ||
| 380 | # CONFIG_INFTL is not set | ||
| 381 | # CONFIG_RFD_FTL is not set | ||
| 382 | # CONFIG_SSFDC is not set | ||
| 383 | # CONFIG_MTD_OOPS is not set | ||
| 384 | |||
| 385 | # | ||
| 386 | # RAM/ROM/Flash chip drivers | ||
| 387 | # | ||
| 388 | CONFIG_MTD_CFI=y | ||
| 389 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 390 | CONFIG_MTD_GEN_PROBE=y | ||
| 391 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 392 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 393 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 394 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 395 | CONFIG_MTD_CFI_GEOMETRY=y | ||
| 396 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 397 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 398 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 399 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 400 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 401 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 402 | CONFIG_MTD_CFI_I1=y | ||
| 403 | CONFIG_MTD_CFI_I2=y | ||
| 404 | # CONFIG_MTD_CFI_I4 is not set | ||
| 405 | # CONFIG_MTD_CFI_I8 is not set | ||
| 406 | # CONFIG_MTD_OTP is not set | ||
| 407 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 408 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 409 | # CONFIG_MTD_CFI_STAA is not set | ||
| 410 | CONFIG_MTD_CFI_UTIL=y | ||
| 411 | # CONFIG_MTD_RAM is not set | ||
| 412 | # CONFIG_MTD_ROM is not set | ||
| 413 | # CONFIG_MTD_ABSENT is not set | ||
| 414 | |||
| 415 | # | ||
| 416 | # Mapping drivers for chip access | ||
| 417 | # | ||
| 418 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 419 | CONFIG_MTD_PHYSMAP=y | ||
| 420 | CONFIG_MTD_PHYSMAP_START=0x00000000 | ||
| 421 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 422 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 423 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 424 | # CONFIG_MTD_PLATRAM is not set | ||
| 425 | |||
| 426 | # | ||
| 427 | # Self-contained MTD device drivers | ||
| 428 | # | ||
| 429 | # CONFIG_MTD_SLRAM is not set | ||
| 430 | # CONFIG_MTD_PHRAM is not set | ||
| 431 | # CONFIG_MTD_MTDRAM is not set | ||
| 432 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 433 | |||
| 434 | # | ||
| 435 | # Disk-On-Chip Device Drivers | ||
| 436 | # | ||
| 437 | # CONFIG_MTD_DOC2000 is not set | ||
| 438 | # CONFIG_MTD_DOC2001 is not set | ||
| 439 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 440 | # CONFIG_MTD_NAND is not set | ||
| 441 | # CONFIG_MTD_ONENAND is not set | ||
| 442 | |||
| 443 | # | ||
| 444 | # UBI - Unsorted block images | ||
| 445 | # | ||
| 446 | # CONFIG_MTD_UBI is not set | ||
| 447 | # CONFIG_PARPORT is not set | ||
| 448 | CONFIG_BLK_DEV=y | ||
| 449 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 450 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 451 | # CONFIG_BLK_DEV_NBD is not set | ||
| 452 | # CONFIG_BLK_DEV_UB is not set | ||
| 453 | CONFIG_BLK_DEV_RAM=y | ||
| 454 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 455 | CONFIG_BLK_DEV_RAM_SIZE=10240 | ||
| 456 | # CONFIG_BLK_DEV_XIP is not set | ||
| 457 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 458 | # CONFIG_ATA_OVER_ETH is not set | ||
| 459 | # CONFIG_MISC_DEVICES is not set | ||
| 460 | CONFIG_HAVE_IDE=y | ||
| 461 | # CONFIG_IDE is not set | ||
| 462 | |||
| 463 | # | ||
| 464 | # SCSI device support | ||
| 465 | # | ||
| 466 | # CONFIG_RAID_ATTRS is not set | ||
| 467 | # CONFIG_SCSI is not set | ||
| 468 | # CONFIG_SCSI_DMA is not set | ||
| 469 | # CONFIG_SCSI_NETLINK is not set | ||
| 470 | # CONFIG_ATA is not set | ||
| 471 | # CONFIG_MD is not set | ||
| 472 | # CONFIG_NETDEVICES is not set | ||
| 473 | # CONFIG_ISDN is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Input device support | ||
| 477 | # | ||
| 478 | CONFIG_INPUT=y | ||
| 479 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 480 | # CONFIG_INPUT_POLLDEV is not set | ||
| 481 | |||
| 482 | # | ||
| 483 | # Userland interfaces | ||
| 484 | # | ||
| 485 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 486 | # CONFIG_INPUT_JOYDEV is not set | ||
| 487 | # CONFIG_INPUT_EVDEV is not set | ||
| 488 | # CONFIG_INPUT_EVBUG is not set | ||
| 489 | |||
| 490 | # | ||
| 491 | # Input Device Drivers | ||
| 492 | # | ||
| 493 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 494 | # CONFIG_INPUT_MOUSE is not set | ||
| 495 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 496 | # CONFIG_INPUT_TABLET is not set | ||
| 497 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 498 | # CONFIG_INPUT_MISC is not set | ||
| 499 | |||
| 500 | # | ||
| 501 | # Hardware I/O ports | ||
| 502 | # | ||
| 503 | # CONFIG_SERIO is not set | ||
| 504 | # CONFIG_GAMEPORT is not set | ||
| 505 | |||
| 506 | # | ||
| 507 | # Character devices | ||
| 508 | # | ||
| 509 | CONFIG_VT=y | ||
| 510 | # CONFIG_VT_CONSOLE is not set | ||
| 511 | CONFIG_HW_CONSOLE=y | ||
| 512 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 513 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 514 | |||
| 515 | # | ||
| 516 | # Serial drivers | ||
| 517 | # | ||
| 518 | # CONFIG_SERIAL_8250 is not set | ||
| 519 | |||
| 520 | # | ||
| 521 | # Non-8250 serial port support | ||
| 522 | # | ||
| 523 | CONFIG_SERIAL_S3C2410=y | ||
| 524 | CONFIG_SERIAL_S3C2410_CONSOLE=y | ||
| 525 | CONFIG_SERIAL_CORE=y | ||
| 526 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 527 | CONFIG_UNIX98_PTYS=y | ||
| 528 | CONFIG_LEGACY_PTYS=y | ||
| 529 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 530 | # CONFIG_IPMI_HANDLER is not set | ||
| 531 | # CONFIG_HW_RANDOM is not set | ||
| 532 | # CONFIG_NVRAM is not set | ||
| 533 | # CONFIG_R3964 is not set | ||
| 534 | # CONFIG_RAW_DRIVER is not set | ||
| 535 | # CONFIG_TCG_TPM is not set | ||
| 536 | # CONFIG_I2C is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # SPI support | ||
| 540 | # | ||
| 541 | # CONFIG_SPI is not set | ||
| 542 | # CONFIG_SPI_MASTER is not set | ||
| 543 | # CONFIG_W1 is not set | ||
| 544 | # CONFIG_POWER_SUPPLY is not set | ||
| 545 | # CONFIG_HWMON is not set | ||
| 546 | # CONFIG_WATCHDOG is not set | ||
| 547 | |||
| 548 | # | ||
| 549 | # Sonics Silicon Backplane | ||
| 550 | # | ||
| 551 | CONFIG_SSB_POSSIBLE=y | ||
| 552 | # CONFIG_SSB is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # Multifunction device drivers | ||
| 556 | # | ||
| 557 | # CONFIG_MFD_SM501 is not set | ||
| 558 | # CONFIG_MFD_ASIC3 is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Multimedia devices | ||
| 562 | # | ||
| 563 | # CONFIG_VIDEO_DEV is not set | ||
| 564 | # CONFIG_DAB is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # Graphics support | ||
| 568 | # | ||
| 569 | # CONFIG_VGASTATE is not set | ||
| 570 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 571 | # CONFIG_FB is not set | ||
| 572 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 573 | |||
| 574 | # | ||
| 575 | # Display device support | ||
| 576 | # | ||
| 577 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 578 | |||
| 579 | # | ||
| 580 | # Console display driver support | ||
| 581 | # | ||
| 582 | # CONFIG_VGA_CONSOLE is not set | ||
| 583 | CONFIG_DUMMY_CONSOLE=y | ||
| 584 | |||
| 585 | # | ||
| 586 | # Sound | ||
| 587 | # | ||
| 588 | # CONFIG_SOUND is not set | ||
| 589 | # CONFIG_HID_SUPPORT is not set | ||
| 590 | CONFIG_USB_SUPPORT=y | ||
| 591 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 592 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 593 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 594 | CONFIG_USB=y | ||
| 595 | CONFIG_USB_DEBUG=y | ||
| 596 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 597 | |||
| 598 | # | ||
| 599 | # Miscellaneous USB options | ||
| 600 | # | ||
| 601 | # CONFIG_USB_DEVICEFS is not set | ||
| 602 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 603 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 604 | # CONFIG_USB_OTG is not set | ||
| 605 | |||
| 606 | # | ||
| 607 | # USB Host Controller Drivers | ||
| 608 | # | ||
| 609 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 610 | CONFIG_USB_OHCI_HCD=y | ||
| 611 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 612 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 613 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 614 | # CONFIG_USB_SL811_HCD is not set | ||
| 615 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 616 | |||
| 617 | # | ||
| 618 | # USB Device Class drivers | ||
| 619 | # | ||
| 620 | # CONFIG_USB_ACM is not set | ||
| 621 | # CONFIG_USB_PRINTER is not set | ||
| 622 | |||
| 623 | # | ||
| 624 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 625 | # | ||
| 626 | |||
| 627 | # | ||
| 628 | # may also be needed; see USB_STORAGE Help for more information | ||
| 629 | # | ||
| 630 | # CONFIG_USB_LIBUSUAL is not set | ||
| 631 | |||
| 632 | # | ||
| 633 | # USB Imaging devices | ||
| 634 | # | ||
| 635 | # CONFIG_USB_MDC800 is not set | ||
| 636 | CONFIG_USB_MON=y | ||
| 637 | |||
| 638 | # | ||
| 639 | # USB port drivers | ||
| 640 | # | ||
| 641 | # CONFIG_USB_SERIAL is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # USB Miscellaneous drivers | ||
| 645 | # | ||
| 646 | # CONFIG_USB_EMI62 is not set | ||
| 647 | # CONFIG_USB_EMI26 is not set | ||
| 648 | # CONFIG_USB_ADUTUX is not set | ||
| 649 | # CONFIG_USB_AUERSWALD is not set | ||
| 650 | # CONFIG_USB_RIO500 is not set | ||
| 651 | # CONFIG_USB_LEGOTOWER is not set | ||
| 652 | # CONFIG_USB_LCD is not set | ||
| 653 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 654 | # CONFIG_USB_LED is not set | ||
| 655 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 656 | # CONFIG_USB_CYTHERM is not set | ||
| 657 | # CONFIG_USB_PHIDGET is not set | ||
| 658 | # CONFIG_USB_IDMOUSE is not set | ||
| 659 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 660 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 661 | # CONFIG_USB_LD is not set | ||
| 662 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 663 | # CONFIG_USB_IOWARRIOR is not set | ||
| 664 | CONFIG_USB_GADGET=y | ||
| 665 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 666 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 667 | CONFIG_USB_GADGET_SELECTED=y | ||
| 668 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 669 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 670 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 671 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 672 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 673 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 674 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 675 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 676 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 677 | CONFIG_USB_GADGET_S3C2410=y | ||
| 678 | CONFIG_USB_S3C2410=y | ||
| 679 | # CONFIG_USB_S3C2410_DEBUG is not set | ||
| 680 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 681 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 682 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 683 | # CONFIG_USB_ZERO is not set | ||
| 684 | CONFIG_USB_ETH=y | ||
| 685 | CONFIG_USB_ETH_RNDIS=y | ||
| 686 | # CONFIG_USB_GADGETFS is not set | ||
| 687 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 688 | # CONFIG_USB_G_SERIAL is not set | ||
| 689 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 690 | # CONFIG_USB_G_PRINTER is not set | ||
| 691 | # CONFIG_MMC is not set | ||
| 692 | # CONFIG_NEW_LEDS is not set | ||
| 693 | CONFIG_RTC_LIB=y | ||
| 694 | # CONFIG_RTC_CLASS is not set | ||
| 695 | |||
| 696 | # | ||
| 697 | # File systems | ||
| 698 | # | ||
| 699 | CONFIG_EXT2_FS=y | ||
| 700 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 701 | # CONFIG_EXT2_FS_XIP is not set | ||
| 702 | # CONFIG_EXT3_FS is not set | ||
| 703 | # CONFIG_EXT4DEV_FS is not set | ||
| 704 | # CONFIG_REISERFS_FS is not set | ||
| 705 | # CONFIG_JFS_FS is not set | ||
| 706 | # CONFIG_FS_POSIX_ACL is not set | ||
| 707 | # CONFIG_XFS_FS is not set | ||
| 708 | # CONFIG_GFS2_FS is not set | ||
| 709 | # CONFIG_OCFS2_FS is not set | ||
| 710 | # CONFIG_DNOTIFY is not set | ||
| 711 | # CONFIG_INOTIFY is not set | ||
| 712 | # CONFIG_QUOTA is not set | ||
| 713 | # CONFIG_AUTOFS_FS is not set | ||
| 714 | # CONFIG_AUTOFS4_FS is not set | ||
| 715 | # CONFIG_FUSE_FS is not set | ||
| 716 | |||
| 717 | # | ||
| 718 | # CD-ROM/DVD Filesystems | ||
| 719 | # | ||
| 720 | # CONFIG_ISO9660_FS is not set | ||
| 721 | # CONFIG_UDF_FS is not set | ||
| 722 | |||
| 723 | # | ||
| 724 | # DOS/FAT/NT Filesystems | ||
| 725 | # | ||
| 726 | CONFIG_FAT_FS=y | ||
| 727 | CONFIG_MSDOS_FS=y | ||
| 728 | CONFIG_VFAT_FS=y | ||
| 729 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 730 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 731 | # CONFIG_NTFS_FS is not set | ||
| 732 | |||
| 733 | # | ||
| 734 | # Pseudo filesystems | ||
| 735 | # | ||
| 736 | CONFIG_PROC_FS=y | ||
| 737 | # CONFIG_PROC_SYSCTL is not set | ||
| 738 | CONFIG_SYSFS=y | ||
| 739 | # CONFIG_TMPFS is not set | ||
| 740 | # CONFIG_HUGETLB_PAGE is not set | ||
| 741 | # CONFIG_CONFIGFS_FS is not set | ||
| 742 | |||
| 743 | # | ||
| 744 | # Miscellaneous filesystems | ||
| 745 | # | ||
| 746 | # CONFIG_ADFS_FS is not set | ||
| 747 | # CONFIG_AFFS_FS is not set | ||
| 748 | # CONFIG_HFS_FS is not set | ||
| 749 | # CONFIG_HFSPLUS_FS is not set | ||
| 750 | # CONFIG_BEFS_FS is not set | ||
| 751 | # CONFIG_BFS_FS is not set | ||
| 752 | # CONFIG_EFS_FS is not set | ||
| 753 | CONFIG_JFFS2_FS=y | ||
| 754 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 755 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 756 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 757 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 758 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 759 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 760 | CONFIG_JFFS2_ZLIB=y | ||
| 761 | # CONFIG_JFFS2_LZO is not set | ||
| 762 | CONFIG_JFFS2_RTIME=y | ||
| 763 | # CONFIG_JFFS2_RUBIN is not set | ||
| 764 | # CONFIG_CRAMFS is not set | ||
| 765 | # CONFIG_VXFS_FS is not set | ||
| 766 | # CONFIG_MINIX_FS is not set | ||
| 767 | # CONFIG_HPFS_FS is not set | ||
| 768 | # CONFIG_QNX4FS_FS is not set | ||
| 769 | # CONFIG_ROMFS_FS is not set | ||
| 770 | # CONFIG_SYSV_FS is not set | ||
| 771 | # CONFIG_UFS_FS is not set | ||
| 772 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 773 | |||
| 774 | # | ||
| 775 | # Partition Types | ||
| 776 | # | ||
| 777 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 778 | CONFIG_MSDOS_PARTITION=y | ||
| 779 | CONFIG_NLS=y | ||
| 780 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 781 | CONFIG_NLS_CODEPAGE_437=y | ||
| 782 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 783 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 784 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 785 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 786 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 787 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 788 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 789 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 790 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 791 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 792 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 793 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 794 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 795 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 796 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 797 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 798 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 799 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 800 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 801 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 802 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 803 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 804 | # CONFIG_NLS_ASCII is not set | ||
| 805 | CONFIG_NLS_ISO8859_1=y | ||
| 806 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 807 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 808 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 809 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 810 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 811 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 812 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 813 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 814 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 815 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 816 | # CONFIG_NLS_KOI8_R is not set | ||
| 817 | # CONFIG_NLS_KOI8_U is not set | ||
| 818 | # CONFIG_NLS_UTF8 is not set | ||
| 819 | |||
| 820 | # | ||
| 821 | # Kernel hacking | ||
| 822 | # | ||
| 823 | # CONFIG_PRINTK_TIME is not set | ||
| 824 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 825 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 826 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 827 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 828 | # CONFIG_DEBUG_FS is not set | ||
| 829 | # CONFIG_HEADERS_CHECK is not set | ||
| 830 | CONFIG_DEBUG_KERNEL=y | ||
| 831 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 832 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 833 | CONFIG_SCHED_DEBUG=y | ||
| 834 | # CONFIG_SCHEDSTATS is not set | ||
| 835 | # CONFIG_TIMER_STATS is not set | ||
| 836 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 837 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 838 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 839 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 840 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 841 | # CONFIG_PROVE_LOCKING is not set | ||
| 842 | # CONFIG_LOCK_STAT is not set | ||
| 843 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 844 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 845 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 846 | # CONFIG_DEBUG_INFO is not set | ||
| 847 | # CONFIG_DEBUG_VM is not set | ||
| 848 | # CONFIG_DEBUG_LIST is not set | ||
| 849 | # CONFIG_DEBUG_SG is not set | ||
| 850 | CONFIG_FRAME_POINTER=y | ||
| 851 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 852 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 853 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 854 | # CONFIG_FAULT_INJECTION is not set | ||
| 855 | # CONFIG_SAMPLES is not set | ||
| 856 | # CONFIG_DEBUG_USER is not set | ||
| 857 | CONFIG_DEBUG_ERRORS=y | ||
| 858 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 859 | CONFIG_DEBUG_LL=y | ||
| 860 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 861 | # CONFIG_DEBUG_S3C_PORT is not set | ||
| 862 | CONFIG_DEBUG_S3C_UART=0 | ||
| 863 | |||
| 864 | # | ||
| 865 | # Security options | ||
| 866 | # | ||
| 867 | # CONFIG_KEYS is not set | ||
| 868 | # CONFIG_SECURITY is not set | ||
| 869 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 870 | # CONFIG_CRYPTO is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # Library routines | ||
| 874 | # | ||
| 875 | CONFIG_BITREVERSE=y | ||
| 876 | CONFIG_CRC_CCITT=y | ||
| 877 | # CONFIG_CRC16 is not set | ||
| 878 | # CONFIG_CRC_ITU_T is not set | ||
| 879 | CONFIG_CRC32=y | ||
| 880 | # CONFIG_CRC7 is not set | ||
| 881 | # CONFIG_LIBCRC32C is not set | ||
| 882 | CONFIG_ZLIB_INFLATE=y | ||
| 883 | CONFIG_ZLIB_DEFLATE=y | ||
| 884 | CONFIG_PLIST=y | ||
| 885 | CONFIG_HAS_IOMEM=y | ||
| 886 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 00d44c6fbfe9..d5be3f7ac0e3 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
| @@ -22,6 +22,7 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o | |||
| 22 | obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o | 22 | obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o |
| 23 | obj-$(CONFIG_ATAGS_PROC) += atags.o | 23 | obj-$(CONFIG_ATAGS_PROC) += atags.o |
| 24 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o | 24 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o |
| 25 | obj-$(CONFIG_ARM_THUMBEE) += thumbee.o | ||
| 25 | 26 | ||
| 26 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o | 27 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o |
| 27 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 | 28 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 |
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 3278e713c32a..0a0d2479274b 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c | |||
| @@ -58,6 +58,9 @@ int main(void) | |||
| 58 | DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); | 58 | DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); |
| 59 | DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); | 59 | DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); |
| 60 | DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); | 60 | DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); |
| 61 | #ifdef CONFIG_ARM_THUMBEE | ||
| 62 | DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state)); | ||
| 63 | #endif | ||
| 61 | #ifdef CONFIG_IWMMXT | 64 | #ifdef CONFIG_IWMMXT |
| 62 | DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); | 65 | DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); |
| 63 | #endif | 66 | #endif |
| @@ -108,5 +111,12 @@ int main(void) | |||
| 108 | DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); | 111 | DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); |
| 109 | DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags)); | 112 | DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags)); |
| 110 | DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags)); | 113 | DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags)); |
| 114 | BLANK(); | ||
| 115 | #ifdef MULTI_DABORT | ||
| 116 | DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort)); | ||
| 117 | #endif | ||
| 118 | #ifdef MULTI_PABORT | ||
| 119 | DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); | ||
| 120 | #endif | ||
| 111 | return 0; | 121 | return 0; |
| 112 | } | 122 | } |
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 283e14fff993..95f1c121cb30 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S | |||
| @@ -359,9 +359,11 @@ | |||
| 359 | CALL(sys_kexec_load) | 359 | CALL(sys_kexec_load) |
| 360 | CALL(sys_utimensat) | 360 | CALL(sys_utimensat) |
| 361 | CALL(sys_signalfd) | 361 | CALL(sys_signalfd) |
| 362 | /* 350 */ CALL(sys_ni_syscall) | 362 | /* 350 */ CALL(sys_timerfd_create) |
| 363 | CALL(sys_eventfd) | 363 | CALL(sys_eventfd) |
| 364 | CALL(sys_fallocate) | 364 | CALL(sys_fallocate) |
| 365 | CALL(sys_timerfd_settime) | ||
| 366 | CALL(sys_timerfd_gettime) | ||
| 365 | #ifndef syscalls_counted | 367 | #ifndef syscalls_counted |
| 366 | .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls | 368 | .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls |
| 367 | #define syscalls_counted | 369 | #define syscalls_counted |
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index a46d5b456765..7dca225752c1 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
| @@ -166,12 +166,12 @@ __dabt_svc: | |||
| 166 | @ The abort handler must return the aborted address in r0, and | 166 | @ The abort handler must return the aborted address in r0, and |
| 167 | @ the fault status register in r1. r9 must be preserved. | 167 | @ the fault status register in r1. r9 must be preserved. |
| 168 | @ | 168 | @ |
| 169 | #ifdef MULTI_ABORT | 169 | #ifdef MULTI_DABORT |
| 170 | ldr r4, .LCprocfns | 170 | ldr r4, .LCprocfns |
| 171 | mov lr, pc | 171 | mov lr, pc |
| 172 | ldr pc, [r4] | 172 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
| 173 | #else | 173 | #else |
| 174 | bl CPU_ABORT_HANDLER | 174 | bl CPU_DABORT_HANDLER |
| 175 | #endif | 175 | #endif |
| 176 | 176 | ||
| 177 | @ | 177 | @ |
| @@ -209,14 +209,12 @@ __irq_svc: | |||
| 209 | 209 | ||
| 210 | irq_handler | 210 | irq_handler |
| 211 | #ifdef CONFIG_PREEMPT | 211 | #ifdef CONFIG_PREEMPT |
| 212 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | ||
| 212 | ldr r0, [tsk, #TI_FLAGS] @ get flags | 213 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
| 214 | teq r8, #0 @ if preempt count != 0 | ||
| 215 | movne r0, #0 @ force flags to 0 | ||
| 213 | tst r0, #_TIF_NEED_RESCHED | 216 | tst r0, #_TIF_NEED_RESCHED |
| 214 | blne svc_preempt | 217 | blne svc_preempt |
| 215 | preempt_return: | ||
| 216 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value | ||
| 217 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | ||
| 218 | teq r0, r7 | ||
| 219 | strne r0, [r0, -r0] @ bug() | ||
| 220 | #endif | 218 | #endif |
| 221 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | 219 | ldr r0, [sp, #S_PSR] @ irqs are already disabled |
| 222 | msr spsr_cxsf, r0 | 220 | msr spsr_cxsf, r0 |
| @@ -230,19 +228,11 @@ preempt_return: | |||
| 230 | 228 | ||
| 231 | #ifdef CONFIG_PREEMPT | 229 | #ifdef CONFIG_PREEMPT |
| 232 | svc_preempt: | 230 | svc_preempt: |
| 233 | teq r8, #0 @ was preempt count = 0 | 231 | mov r8, lr |
| 234 | ldreq r6, .LCirq_stat | ||
| 235 | movne pc, lr @ no | ||
| 236 | ldr r0, [r6, #4] @ local_irq_count | ||
| 237 | ldr r1, [r6, #8] @ local_bh_count | ||
| 238 | adds r0, r0, r1 | ||
| 239 | movne pc, lr | ||
| 240 | mov r7, #0 @ preempt_schedule_irq | ||
| 241 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 | ||
| 242 | 1: bl preempt_schedule_irq @ irq en/disable is done inside | 232 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
| 243 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS | 233 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
| 244 | tst r0, #_TIF_NEED_RESCHED | 234 | tst r0, #_TIF_NEED_RESCHED |
| 245 | beq preempt_return @ go again | 235 | moveq pc, r8 @ go again |
| 246 | b 1b | 236 | b 1b |
| 247 | #endif | 237 | #endif |
| 248 | 238 | ||
| @@ -293,7 +283,6 @@ __pabt_svc: | |||
| 293 | mrs r9, cpsr | 283 | mrs r9, cpsr |
| 294 | tst r3, #PSR_I_BIT | 284 | tst r3, #PSR_I_BIT |
| 295 | biceq r9, r9, #PSR_I_BIT | 285 | biceq r9, r9, #PSR_I_BIT |
| 296 | msr cpsr_c, r9 | ||
| 297 | 286 | ||
| 298 | @ | 287 | @ |
| 299 | @ set args, then call main handler | 288 | @ set args, then call main handler |
| @@ -301,7 +290,15 @@ __pabt_svc: | |||
| 301 | @ r0 - address of faulting instruction | 290 | @ r0 - address of faulting instruction |
| 302 | @ r1 - pointer to registers on stack | 291 | @ r1 - pointer to registers on stack |
| 303 | @ | 292 | @ |
| 304 | mov r0, r2 @ address (pc) | 293 | #ifdef MULTI_PABORT |
| 294 | mov r0, r2 @ pass address of aborted instruction. | ||
| 295 | ldr r4, .LCprocfns | ||
| 296 | mov lr, pc | ||
| 297 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | ||
| 298 | #else | ||
| 299 | CPU_PABORT_HANDLER(r0, r2) | ||
| 300 | #endif | ||
| 301 | msr cpsr_c, r9 @ Maybe enable interrupts | ||
| 305 | mov r1, sp @ regs | 302 | mov r1, sp @ regs |
| 306 | bl do_PrefetchAbort @ call abort handler | 303 | bl do_PrefetchAbort @ call abort handler |
| 307 | 304 | ||
| @@ -320,16 +317,12 @@ __pabt_svc: | |||
| 320 | .align 5 | 317 | .align 5 |
| 321 | .LCcralign: | 318 | .LCcralign: |
| 322 | .word cr_alignment | 319 | .word cr_alignment |
| 323 | #ifdef MULTI_ABORT | 320 | #ifdef MULTI_DABORT |
| 324 | .LCprocfns: | 321 | .LCprocfns: |
| 325 | .word processor | 322 | .word processor |
| 326 | #endif | 323 | #endif |
| 327 | .LCfp: | 324 | .LCfp: |
| 328 | .word fp_enter | 325 | .word fp_enter |
| 329 | #ifdef CONFIG_PREEMPT | ||
| 330 | .LCirq_stat: | ||
| 331 | .word irq_stat | ||
| 332 | #endif | ||
| 333 | 326 | ||
| 334 | /* | 327 | /* |
| 335 | * User mode handlers | 328 | * User mode handlers |
| @@ -404,12 +397,12 @@ __dabt_usr: | |||
| 404 | @ The abort handler must return the aborted address in r0, and | 397 | @ The abort handler must return the aborted address in r0, and |
| 405 | @ the fault status register in r1. | 398 | @ the fault status register in r1. |
| 406 | @ | 399 | @ |
| 407 | #ifdef MULTI_ABORT | 400 | #ifdef MULTI_DABORT |
| 408 | ldr r4, .LCprocfns | 401 | ldr r4, .LCprocfns |
| 409 | mov lr, pc | 402 | mov lr, pc |
| 410 | ldr pc, [r4] | 403 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
| 411 | #else | 404 | #else |
| 412 | bl CPU_ABORT_HANDLER | 405 | bl CPU_DABORT_HANDLER |
| 413 | #endif | 406 | #endif |
| 414 | 407 | ||
| 415 | @ | 408 | @ |
| @@ -455,10 +448,6 @@ __irq_usr: | |||
| 455 | __und_usr: | 448 | __und_usr: |
| 456 | usr_entry | 449 | usr_entry |
| 457 | 450 | ||
| 458 | tst r3, #PSR_T_BIT @ Thumb mode? | ||
| 459 | bne __und_usr_unknown @ ignore FP | ||
| 460 | sub r4, r2, #4 | ||
| 461 | |||
| 462 | @ | 451 | @ |
| 463 | @ fall through to the emulation code, which returns using r9 if | 452 | @ fall through to the emulation code, which returns using r9 if |
| 464 | @ it has emulated the instruction, or the more conventional lr | 453 | @ it has emulated the instruction, or the more conventional lr |
| @@ -468,7 +457,24 @@ __und_usr: | |||
| 468 | @ | 457 | @ |
| 469 | adr r9, ret_from_exception | 458 | adr r9, ret_from_exception |
| 470 | adr lr, __und_usr_unknown | 459 | adr lr, __und_usr_unknown |
| 471 | 1: ldrt r0, [r4] | 460 | tst r3, #PSR_T_BIT @ Thumb mode? |
| 461 | subeq r4, r2, #4 @ ARM instr at LR - 4 | ||
| 462 | subne r4, r2, #2 @ Thumb instr at LR - 2 | ||
| 463 | 1: ldreqt r0, [r4] | ||
| 464 | beq call_fpe | ||
| 465 | @ Thumb instruction | ||
| 466 | #if __LINUX_ARM_ARCH__ >= 7 | ||
| 467 | 2: ldrht r5, [r4], #2 | ||
| 468 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... | ||
| 469 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | ||
| 470 | blo __und_usr_unknown | ||
| 471 | 3: ldrht r0, [r4] | ||
| 472 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | ||
| 473 | orr r0, r0, r5, lsl #16 | ||
| 474 | #else | ||
| 475 | b __und_usr_unknown | ||
| 476 | #endif | ||
| 477 | |||
| 472 | @ | 478 | @ |
| 473 | @ fallthrough to call_fpe | 479 | @ fallthrough to call_fpe |
| 474 | @ | 480 | @ |
| @@ -477,10 +483,14 @@ __und_usr: | |||
| 477 | * The out of line fixup for the ldrt above. | 483 | * The out of line fixup for the ldrt above. |
| 478 | */ | 484 | */ |
| 479 | .section .fixup, "ax" | 485 | .section .fixup, "ax" |
| 480 | 2: mov pc, r9 | 486 | 4: mov pc, r9 |
| 481 | .previous | 487 | .previous |
| 482 | .section __ex_table,"a" | 488 | .section __ex_table,"a" |
| 483 | .long 1b, 2b | 489 | .long 1b, 4b |
| 490 | #if __LINUX_ARM_ARCH__ >= 7 | ||
| 491 | .long 2b, 4b | ||
| 492 | .long 3b, 4b | ||
| 493 | #endif | ||
| 484 | .previous | 494 | .previous |
| 485 | 495 | ||
| 486 | /* | 496 | /* |
| @@ -507,9 +517,16 @@ __und_usr: | |||
| 507 | * r10 = this threads thread_info structure. | 517 | * r10 = this threads thread_info structure. |
| 508 | * lr = unrecognised instruction return address | 518 | * lr = unrecognised instruction return address |
| 509 | */ | 519 | */ |
| 520 | @ | ||
| 521 | @ Fall-through from Thumb-2 __und_usr | ||
| 522 | @ | ||
| 523 | #ifdef CONFIG_NEON | ||
| 524 | adr r6, .LCneon_thumb_opcodes | ||
| 525 | b 2f | ||
| 526 | #endif | ||
| 510 | call_fpe: | 527 | call_fpe: |
| 511 | #ifdef CONFIG_NEON | 528 | #ifdef CONFIG_NEON |
| 512 | adr r6, .LCneon_opcodes | 529 | adr r6, .LCneon_arm_opcodes |
| 513 | 2: | 530 | 2: |
| 514 | ldr r7, [r6], #4 @ mask value | 531 | ldr r7, [r6], #4 @ mask value |
| 515 | cmp r7, #0 @ end mask? | 532 | cmp r7, #0 @ end mask? |
| @@ -526,6 +543,7 @@ call_fpe: | |||
| 526 | 1: | 543 | 1: |
| 527 | #endif | 544 | #endif |
| 528 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | 545 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
| 546 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 | ||
| 529 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | 547 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
| 530 | and r8, r0, #0x0f000000 @ mask out op-code bits | 548 | and r8, r0, #0x0f000000 @ mask out op-code bits |
| 531 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | 549 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? |
| @@ -577,7 +595,7 @@ call_fpe: | |||
| 577 | #ifdef CONFIG_NEON | 595 | #ifdef CONFIG_NEON |
| 578 | .align 6 | 596 | .align 6 |
| 579 | 597 | ||
| 580 | .LCneon_opcodes: | 598 | .LCneon_arm_opcodes: |
| 581 | .word 0xfe000000 @ mask | 599 | .word 0xfe000000 @ mask |
| 582 | .word 0xf2000000 @ opcode | 600 | .word 0xf2000000 @ opcode |
| 583 | 601 | ||
| @@ -586,6 +604,16 @@ call_fpe: | |||
| 586 | 604 | ||
| 587 | .word 0x00000000 @ mask | 605 | .word 0x00000000 @ mask |
| 588 | .word 0x00000000 @ opcode | 606 | .word 0x00000000 @ opcode |
| 607 | |||
| 608 | .LCneon_thumb_opcodes: | ||
| 609 | .word 0xef000000 @ mask | ||
| 610 | .word 0xef000000 @ opcode | ||
| 611 | |||
| 612 | .word 0xff100000 @ mask | ||
| 613 | .word 0xf9000000 @ opcode | ||
| 614 | |||
| 615 | .word 0x00000000 @ mask | ||
| 616 | .word 0x00000000 @ opcode | ||
| 589 | #endif | 617 | #endif |
| 590 | 618 | ||
| 591 | do_fpe: | 619 | do_fpe: |
| @@ -619,8 +647,15 @@ __und_usr_unknown: | |||
| 619 | __pabt_usr: | 647 | __pabt_usr: |
| 620 | usr_entry | 648 | usr_entry |
| 621 | 649 | ||
| 650 | #ifdef MULTI_PABORT | ||
| 651 | mov r0, r2 @ pass address of aborted instruction. | ||
| 652 | ldr r4, .LCprocfns | ||
| 653 | mov lr, pc | ||
| 654 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | ||
| 655 | #else | ||
| 656 | CPU_PABORT_HANDLER(r0, r2) | ||
| 657 | #endif | ||
| 622 | enable_irq @ Enable interrupts | 658 | enable_irq @ Enable interrupts |
| 623 | mov r0, r2 @ address (pc) | ||
| 624 | mov r1, sp @ regs | 659 | mov r1, sp @ regs |
| 625 | bl do_PrefetchAbort @ call abort handler | 660 | bl do_PrefetchAbort @ call abort handler |
| 626 | /* fall through */ | 661 | /* fall through */ |
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 6c90c50a9ee3..597ed00a08d8 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -352,6 +352,11 @@ sys_mmap2: | |||
| 352 | b do_mmap2 | 352 | b do_mmap2 |
| 353 | #endif | 353 | #endif |
| 354 | 354 | ||
| 355 | ENTRY(pabort_ifar) | ||
| 356 | mrc p15, 0, r0, cr6, cr0, 2 | ||
| 357 | ENTRY(pabort_noifar) | ||
| 358 | mov pc, lr | ||
| 359 | |||
| 355 | #ifdef CONFIG_OABI_COMPAT | 360 | #ifdef CONFIG_OABI_COMPAT |
| 356 | 361 | ||
| 357 | /* | 362 | /* |
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 50f667febe29..7e9c00a8a412 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S | |||
| @@ -75,8 +75,13 @@ __error_p: | |||
| 75 | #ifdef CONFIG_DEBUG_LL | 75 | #ifdef CONFIG_DEBUG_LL |
| 76 | adr r0, str_p1 | 76 | adr r0, str_p1 |
| 77 | bl printascii | 77 | bl printascii |
| 78 | mov r0, r9 | ||
| 79 | bl printhex8 | ||
| 80 | adr r0, str_p2 | ||
| 81 | bl printascii | ||
| 78 | b __error | 82 | b __error |
| 79 | str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n" | 83 | str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x" |
| 84 | str_p2: .asciz ").\n" | ||
| 80 | .align | 85 | .align |
| 81 | #endif | 86 | #endif |
| 82 | 87 | ||
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c new file mode 100644 index 000000000000..df3f6b7ebcea --- /dev/null +++ b/arch/arm/kernel/thumbee.c | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/kernel/thumbee.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | |||
| 23 | #include <asm/thread_notify.h> | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Access to the ThumbEE Handler Base register | ||
| 27 | */ | ||
| 28 | static inline unsigned long teehbr_read() | ||
| 29 | { | ||
| 30 | unsigned long v; | ||
| 31 | asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); | ||
| 32 | return v; | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void teehbr_write(unsigned long v) | ||
| 36 | { | ||
| 37 | asm("mcr p14, 6, %0, c1, c0, 0\n" : : "r" (v)); | ||
| 38 | } | ||
| 39 | |||
| 40 | static int thumbee_notifier(struct notifier_block *self, unsigned long cmd, void *t) | ||
| 41 | { | ||
| 42 | struct thread_info *thread = t; | ||
| 43 | |||
| 44 | switch (cmd) { | ||
| 45 | case THREAD_NOTIFY_FLUSH: | ||
| 46 | thread->thumbee_state = 0; | ||
| 47 | break; | ||
| 48 | case THREAD_NOTIFY_SWITCH: | ||
| 49 | current_thread_info()->thumbee_state = teehbr_read(); | ||
| 50 | teehbr_write(thread->thumbee_state); | ||
| 51 | break; | ||
| 52 | } | ||
| 53 | |||
| 54 | return NOTIFY_DONE; | ||
| 55 | } | ||
| 56 | |||
| 57 | static struct notifier_block thumbee_notifier_block = { | ||
| 58 | .notifier_call = thumbee_notifier, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static int __init thumbee_init(void) | ||
| 62 | { | ||
| 63 | unsigned long pfr0; | ||
| 64 | unsigned int cpu_arch = cpu_architecture(); | ||
| 65 | |||
| 66 | if (cpu_arch < CPU_ARCH_ARMv7) | ||
| 67 | return 0; | ||
| 68 | |||
| 69 | /* processor feature register 0 */ | ||
| 70 | asm("mrc p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0)); | ||
| 71 | if ((pfr0 & 0x0000f000) != 0x00001000) | ||
| 72 | return 0; | ||
| 73 | |||
| 74 | printk(KERN_INFO "ThumbEE CPU extension supported.\n"); | ||
| 75 | elf_hwcap |= HWCAP_THUMBEE; | ||
| 76 | thread_register_notifier(&thumbee_notifier_block); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | late_initcall(thumbee_init); | ||
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 0e2b641268ad..dbaae5f746a1 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig | |||
| @@ -31,6 +31,8 @@ config ARCH_EDB7211 | |||
| 31 | bool "EDB7211" | 31 | bool "EDB7211" |
| 32 | select ISA | 32 | select ISA |
| 33 | select ARCH_DISCONTIGMEM_ENABLE | 33 | select ARCH_DISCONTIGMEM_ENABLE |
| 34 | select ARCH_SPARSEMEM_ENABLE | ||
| 35 | select ARCH_SELECT_MEMORY_MODEL | ||
| 34 | help | 36 | help |
| 35 | Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 | 37 | Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 |
| 36 | evaluation board. | 38 | evaluation board. |
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 0ecf99761feb..c1252ca9648e 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Makefile for the linux kernel. | 2 | # Makefile for the linux kernel. |
| 3 | # | 3 | # |
| 4 | obj-y := core.o clock.o | 4 | obj-y := core.o clock.o gpio.o |
| 5 | obj-m := | 5 | obj-m := |
| 6 | obj-n := | 6 | obj-n := |
| 7 | obj- := | 7 | obj- := |
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 91f6a07a51d5..8bc187240542 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
| @@ -159,7 +159,7 @@ static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; | |||
| 159 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; | 159 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; |
| 160 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; | 160 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; |
| 161 | 161 | ||
| 162 | static void update_gpio_int_params(unsigned port) | 162 | void ep93xx_gpio_update_int_params(unsigned port) |
| 163 | { | 163 | { |
| 164 | BUG_ON(port > 2); | 164 | BUG_ON(port > 2); |
| 165 | 165 | ||
| @@ -175,98 +175,10 @@ static void update_gpio_int_params(unsigned port) | |||
| 175 | EP93XX_GPIO_REG(int_en_register_offset[port])); | 175 | EP93XX_GPIO_REG(int_en_register_offset[port])); |
| 176 | } | 176 | } |
| 177 | 177 | ||
| 178 | /* Port ordering is: A B F D E C G H */ | 178 | void ep93xx_gpio_int_mask(unsigned line) |
| 179 | static const u8 data_register_offset[8] = { | ||
| 180 | 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40, | ||
| 181 | }; | ||
| 182 | |||
| 183 | static const u8 data_direction_register_offset[8] = { | ||
| 184 | 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44, | ||
| 185 | }; | ||
| 186 | |||
| 187 | #define GPIO_IN 0 | ||
| 188 | #define GPIO_OUT 1 | ||
| 189 | |||
| 190 | static void ep93xx_gpio_set_direction(unsigned line, int direction) | ||
| 191 | { | ||
| 192 | unsigned int data_direction_register; | ||
| 193 | unsigned long flags; | ||
| 194 | unsigned char v; | ||
| 195 | |||
| 196 | data_direction_register = | ||
| 197 | EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]); | ||
| 198 | |||
| 199 | local_irq_save(flags); | ||
| 200 | if (direction == GPIO_OUT) { | ||
| 201 | if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) { | ||
| 202 | /* Port A/B/F */ | ||
| 203 | gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); | ||
| 204 | update_gpio_int_params(line >> 3); | ||
| 205 | } | ||
| 206 | |||
| 207 | v = __raw_readb(data_direction_register); | ||
| 208 | v |= 1 << (line & 7); | ||
| 209 | __raw_writeb(v, data_direction_register); | ||
| 210 | } else if (direction == GPIO_IN) { | ||
| 211 | v = __raw_readb(data_direction_register); | ||
| 212 | v &= ~(1 << (line & 7)); | ||
| 213 | __raw_writeb(v, data_direction_register); | ||
| 214 | } | ||
| 215 | local_irq_restore(flags); | ||
| 216 | } | ||
| 217 | |||
| 218 | int gpio_direction_input(unsigned gpio) | ||
| 219 | { | ||
| 220 | if (gpio > EP93XX_GPIO_LINE_MAX) | ||
| 221 | return -EINVAL; | ||
| 222 | |||
| 223 | ep93xx_gpio_set_direction(gpio, GPIO_IN); | ||
| 224 | |||
| 225 | return 0; | ||
| 226 | } | ||
| 227 | EXPORT_SYMBOL(gpio_direction_input); | ||
| 228 | |||
| 229 | int gpio_direction_output(unsigned gpio, int value) | ||
| 230 | { | ||
| 231 | if (gpio > EP93XX_GPIO_LINE_MAX) | ||
| 232 | return -EINVAL; | ||
| 233 | |||
| 234 | gpio_set_value(gpio, value); | ||
| 235 | ep93xx_gpio_set_direction(gpio, GPIO_OUT); | ||
| 236 | |||
| 237 | return 0; | ||
| 238 | } | ||
| 239 | EXPORT_SYMBOL(gpio_direction_output); | ||
| 240 | |||
| 241 | int gpio_get_value(unsigned gpio) | ||
| 242 | { | ||
| 243 | unsigned int data_register; | ||
| 244 | |||
| 245 | data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]); | ||
| 246 | |||
| 247 | return !!(__raw_readb(data_register) & (1 << (gpio & 7))); | ||
| 248 | } | ||
| 249 | EXPORT_SYMBOL(gpio_get_value); | ||
| 250 | |||
| 251 | void gpio_set_value(unsigned gpio, int value) | ||
| 252 | { | 179 | { |
| 253 | unsigned int data_register; | 180 | gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); |
| 254 | unsigned long flags; | ||
| 255 | unsigned char v; | ||
| 256 | |||
| 257 | data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]); | ||
| 258 | |||
| 259 | local_irq_save(flags); | ||
| 260 | v = __raw_readb(data_register); | ||
| 261 | if (value) | ||
| 262 | v |= 1 << (gpio & 7); | ||
| 263 | else | ||
| 264 | v &= ~(1 << (gpio & 7)); | ||
| 265 | __raw_writeb(v, data_register); | ||
| 266 | local_irq_restore(flags); | ||
| 267 | } | 181 | } |
| 268 | EXPORT_SYMBOL(gpio_set_value); | ||
| 269 | |||
| 270 | 182 | ||
| 271 | /************************************************************************* | 183 | /************************************************************************* |
| 272 | * EP93xx IRQ handling | 184 | * EP93xx IRQ handling |
| @@ -316,7 +228,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq) | |||
| 316 | 228 | ||
| 317 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 229 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { |
| 318 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 230 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
| 319 | update_gpio_int_params(port); | 231 | ep93xx_gpio_update_int_params(port); |
| 320 | } | 232 | } |
| 321 | 233 | ||
| 322 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | 234 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); |
| @@ -332,7 +244,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq) | |||
| 332 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 244 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
| 333 | 245 | ||
| 334 | gpio_int_unmasked[port] &= ~port_mask; | 246 | gpio_int_unmasked[port] &= ~port_mask; |
| 335 | update_gpio_int_params(port); | 247 | ep93xx_gpio_update_int_params(port); |
| 336 | 248 | ||
| 337 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | 249 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); |
| 338 | } | 250 | } |
| @@ -343,7 +255,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq) | |||
| 343 | int port = line >> 3; | 255 | int port = line >> 3; |
| 344 | 256 | ||
| 345 | gpio_int_unmasked[port] &= ~(1 << (line & 7)); | 257 | gpio_int_unmasked[port] &= ~(1 << (line & 7)); |
| 346 | update_gpio_int_params(port); | 258 | ep93xx_gpio_update_int_params(port); |
| 347 | } | 259 | } |
| 348 | 260 | ||
| 349 | static void ep93xx_gpio_irq_unmask(unsigned int irq) | 261 | static void ep93xx_gpio_irq_unmask(unsigned int irq) |
| @@ -352,7 +264,7 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq) | |||
| 352 | int port = line >> 3; | 264 | int port = line >> 3; |
| 353 | 265 | ||
| 354 | gpio_int_unmasked[port] |= 1 << (line & 7); | 266 | gpio_int_unmasked[port] |= 1 << (line & 7); |
| 355 | update_gpio_int_params(port); | 267 | ep93xx_gpio_update_int_params(port); |
| 356 | } | 268 | } |
| 357 | 269 | ||
| 358 | 270 | ||
| @@ -368,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 368 | const int port = gpio >> 3; | 280 | const int port = gpio >> 3; |
| 369 | const int port_mask = 1 << (gpio & 7); | 281 | const int port_mask = 1 << (gpio & 7); |
| 370 | 282 | ||
| 371 | ep93xx_gpio_set_direction(gpio, GPIO_IN); | 283 | gpio_direction_output(gpio, gpio_get_value(gpio)); |
| 372 | 284 | ||
| 373 | switch (type) { | 285 | switch (type) { |
| 374 | case IRQT_RISING: | 286 | case IRQT_RISING: |
| @@ -411,7 +323,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 411 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | 323 | desc->status &= ~IRQ_TYPE_SENSE_MASK; |
| 412 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | 324 | desc->status |= type & IRQ_TYPE_SENSE_MASK; |
| 413 | 325 | ||
| 414 | update_gpio_int_params(port); | 326 | ep93xx_gpio_update_int_params(port); |
| 415 | 327 | ||
| 416 | return 0; | 328 | return 0; |
| 417 | } | 329 | } |
| @@ -549,6 +461,7 @@ static struct platform_device ep93xx_ohci_device = { | |||
| 549 | .resource = ep93xx_ohci_resources, | 461 | .resource = ep93xx_ohci_resources, |
| 550 | }; | 462 | }; |
| 551 | 463 | ||
| 464 | extern void ep93xx_gpio_init(void); | ||
| 552 | 465 | ||
| 553 | void __init ep93xx_init_devices(void) | 466 | void __init ep93xx_init_devices(void) |
| 554 | { | 467 | { |
| @@ -562,6 +475,8 @@ void __init ep93xx_init_devices(void) | |||
| 562 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 475 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); |
| 563 | __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); | 476 | __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); |
| 564 | 477 | ||
| 478 | ep93xx_gpio_init(); | ||
| 479 | |||
| 565 | amba_device_register(&uart1_device, &iomem_resource); | 480 | amba_device_register(&uart1_device, &iomem_resource); |
| 566 | amba_device_register(&uart2_device, &iomem_resource); | 481 | amba_device_register(&uart2_device, &iomem_resource); |
| 567 | amba_device_register(&uart3_device, &iomem_resource); | 482 | amba_device_register(&uart3_device, &iomem_resource); |
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c new file mode 100644 index 000000000000..dc2e4c00d989 --- /dev/null +++ b/arch/arm/mach-ep93xx/gpio.c | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-ep93xx/gpio.c | ||
| 3 | * | ||
| 4 | * Generic EP93xx GPIO handling | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com> | ||
| 7 | * | ||
| 8 | * Based on code originally from: | ||
| 9 | * linux/arch/arm/mach-ep93xx/core.c | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/module.h> | ||
| 18 | #include <linux/seq_file.h> | ||
| 19 | |||
| 20 | #include <asm/arch/ep93xx-regs.h> | ||
| 21 | #include <asm/io.h> | ||
| 22 | #include <asm/gpio.h> | ||
| 23 | |||
| 24 | struct ep93xx_gpio_chip { | ||
| 25 | struct gpio_chip chip; | ||
| 26 | |||
| 27 | unsigned int data_reg; | ||
| 28 | unsigned int data_dir_reg; | ||
| 29 | }; | ||
| 30 | |||
| 31 | #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) | ||
| 32 | |||
| 33 | /* From core.c */ | ||
| 34 | extern void ep93xx_gpio_int_mask(unsigned line); | ||
| 35 | extern void ep93xx_gpio_update_int_params(unsigned port); | ||
| 36 | |||
| 37 | static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 38 | { | ||
| 39 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 40 | unsigned long flags; | ||
| 41 | u8 v; | ||
| 42 | |||
| 43 | local_irq_save(flags); | ||
| 44 | v = __raw_readb(ep93xx_chip->data_dir_reg); | ||
| 45 | v &= ~(1 << offset); | ||
| 46 | __raw_writeb(v, ep93xx_chip->data_dir_reg); | ||
| 47 | local_irq_restore(flags); | ||
| 48 | |||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static int ep93xx_gpio_direction_output(struct gpio_chip *chip, | ||
| 53 | unsigned offset, int val) | ||
| 54 | { | ||
| 55 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 56 | unsigned long flags; | ||
| 57 | int line; | ||
| 58 | u8 v; | ||
| 59 | |||
| 60 | local_irq_save(flags); | ||
| 61 | |||
| 62 | /* Set the value */ | ||
| 63 | v = __raw_readb(ep93xx_chip->data_reg); | ||
| 64 | if (val) | ||
| 65 | v |= (1 << offset); | ||
| 66 | else | ||
| 67 | v &= ~(1 << offset); | ||
| 68 | __raw_writeb(v, ep93xx_chip->data_reg); | ||
| 69 | |||
| 70 | /* Drive as an output */ | ||
| 71 | line = chip->base + offset; | ||
| 72 | if (line <= EP93XX_GPIO_LINE_MAX_IRQ) { | ||
| 73 | /* Ports A/B/F */ | ||
| 74 | ep93xx_gpio_int_mask(line); | ||
| 75 | ep93xx_gpio_update_int_params(line >> 3); | ||
| 76 | } | ||
| 77 | |||
| 78 | v = __raw_readb(ep93xx_chip->data_dir_reg); | ||
| 79 | v |= (1 << offset); | ||
| 80 | __raw_writeb(v, ep93xx_chip->data_dir_reg); | ||
| 81 | |||
| 82 | local_irq_restore(flags); | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 88 | { | ||
| 89 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 90 | |||
| 91 | return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset)); | ||
| 92 | } | ||
| 93 | |||
| 94 | static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | ||
| 95 | { | ||
| 96 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 97 | unsigned long flags; | ||
| 98 | u8 v; | ||
| 99 | |||
| 100 | local_irq_save(flags); | ||
| 101 | v = __raw_readb(ep93xx_chip->data_reg); | ||
| 102 | if (val) | ||
| 103 | v |= (1 << offset); | ||
| 104 | else | ||
| 105 | v &= ~(1 << offset); | ||
| 106 | __raw_writeb(v, ep93xx_chip->data_reg); | ||
| 107 | local_irq_restore(flags); | ||
| 108 | } | ||
| 109 | |||
| 110 | static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | ||
| 111 | { | ||
| 112 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 113 | u8 data_reg, data_dir_reg; | ||
| 114 | int i; | ||
| 115 | |||
| 116 | data_reg = __raw_readb(ep93xx_chip->data_reg); | ||
| 117 | data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); | ||
| 118 | |||
| 119 | for (i = 0; i < chip->ngpio; i++) | ||
| 120 | seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i, | ||
| 121 | (data_reg & (1 << i)) ? "set" : "clear", | ||
| 122 | (data_dir_reg & (1 << i)) ? "out" : "in"); | ||
| 123 | } | ||
| 124 | |||
| 125 | #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ | ||
| 126 | { \ | ||
| 127 | .chip = { \ | ||
| 128 | .label = name, \ | ||
| 129 | .direction_input = ep93xx_gpio_direction_input, \ | ||
| 130 | .direction_output = ep93xx_gpio_direction_output, \ | ||
| 131 | .get = ep93xx_gpio_get, \ | ||
| 132 | .set = ep93xx_gpio_set, \ | ||
| 133 | .dbg_show = ep93xx_gpio_dbg_show, \ | ||
| 134 | .base = base_gpio, \ | ||
| 135 | .ngpio = 8, \ | ||
| 136 | }, \ | ||
| 137 | .data_reg = EP93XX_GPIO_REG(dr), \ | ||
| 138 | .data_dir_reg = EP93XX_GPIO_REG(ddr), \ | ||
| 139 | } | ||
| 140 | |||
| 141 | static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = { | ||
| 142 | EP93XX_GPIO_BANK("A", 0x00, 0x10, 0), | ||
| 143 | EP93XX_GPIO_BANK("B", 0x04, 0x14, 8), | ||
| 144 | EP93XX_GPIO_BANK("C", 0x30, 0x34, 40), | ||
| 145 | EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24), | ||
| 146 | EP93XX_GPIO_BANK("E", 0x20, 0x24, 32), | ||
| 147 | EP93XX_GPIO_BANK("F", 0x08, 0x18, 16), | ||
| 148 | EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48), | ||
| 149 | EP93XX_GPIO_BANK("H", 0x40, 0x44, 56), | ||
| 150 | }; | ||
| 151 | |||
| 152 | void __init ep93xx_gpio_init(void) | ||
| 153 | { | ||
| 154 | int i; | ||
| 155 | |||
| 156 | for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) | ||
| 157 | gpiochip_add(&ep93xx_gpio_banks[i].chip); | ||
| 158 | } | ||
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index dbe07c9472ed..5e8c6f7dfabb 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig | |||
| @@ -34,14 +34,6 @@ config MACH_N2100 | |||
| 34 | Say Y here if you want to run your kernel on the Thecus n2100 | 34 | Say Y here if you want to run your kernel on the Thecus n2100 |
| 35 | NAS appliance. | 35 | NAS appliance. |
| 36 | 36 | ||
| 37 | config IOP3XX_ATU | ||
| 38 | bool "Enable the PCI Controller" | ||
| 39 | default y | ||
| 40 | help | ||
| 41 | Say Y here if you want the IOP to initialize its PCI Controller. | ||
| 42 | Say N if the IOP is an add in card, the host system owns the PCI | ||
| 43 | bus in this case. | ||
| 44 | |||
| 45 | config MACH_EM7210 | 37 | config MACH_EM7210 |
| 46 | bool "Enable support for the Lanner EM7210" | 38 | bool "Enable support for the Lanner EM7210" |
| 47 | help | 39 | help |
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 98cfa1cd6bdb..4a89823bcebb 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c | |||
| @@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = { | |||
| 178 | 178 | ||
| 179 | static int __init iq31244_pci_init(void) | 179 | static int __init iq31244_pci_init(void) |
| 180 | { | 180 | { |
| 181 | if (is_ep80219()) { | 181 | if (is_ep80219()) |
| 182 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) | 182 | pci_common_init(&ep80219_pci); |
| 183 | pci_common_init(&ep80219_pci); | 183 | else if (machine_is_iq31244()) { |
| 184 | } else if (machine_is_iq31244()) { | ||
| 185 | if (is_80219()) { | 184 | if (is_80219()) { |
| 186 | printk("note: iq31244 board type has been selected\n"); | 185 | printk("note: iq31244 board type has been selected\n"); |
| 187 | printk("note: to select ep80219 operation:\n"); | 186 | printk("note: to select ep80219 operation:\n"); |
| @@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void) | |||
| 190 | printk("\t2/ update boot loader to pass" | 189 | printk("\t2/ update boot loader to pass" |
| 191 | " the ep80219 id: %d\n", MACH_TYPE_EP80219); | 190 | " the ep80219 id: %d\n", MACH_TYPE_EP80219); |
| 192 | } | 191 | } |
| 193 | 192 | pci_common_init(&iq31244_pci); | |
| 194 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) | ||
| 195 | pci_common_init(&iq31244_pci); | ||
| 196 | } | 193 | } |
| 197 | 194 | ||
| 198 | return 0; | 195 | return 0; |
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 18ad29f213b2..1da3c911edd3 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c | |||
| @@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = { | |||
| 106 | .swizzle = pci_std_swizzle, | 106 | .swizzle = pci_std_swizzle, |
| 107 | .nr_controllers = 1, | 107 | .nr_controllers = 1, |
| 108 | .setup = iop3xx_pci_setup, | 108 | .setup = iop3xx_pci_setup, |
| 109 | .preinit = iop3xx_pci_preinit, | 109 | .preinit = iop3xx_pci_preinit_cond, |
| 110 | .scan = iop3xx_pci_scan_bus, | 110 | .scan = iop3xx_pci_scan_bus, |
| 111 | .map_irq = iq80321_pci_map_irq, | 111 | .map_irq = iq80321_pci_map_irq, |
| 112 | }; | 112 | }; |
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig index 45598e096898..9aa016bb18f9 100644 --- a/arch/arm/mach-iop33x/Kconfig +++ b/arch/arm/mach-iop33x/Kconfig | |||
| @@ -16,14 +16,6 @@ config MACH_IQ80332 | |||
| 16 | Say Y here if you want to run your kernel on the Intel IQ80332 | 16 | Say Y here if you want to run your kernel on the Intel IQ80332 |
| 17 | evaluation kit for the IOP332 chipset. | 17 | evaluation kit for the IOP332 chipset. |
| 18 | 18 | ||
| 19 | config IOP3XX_ATU | ||
| 20 | bool "Enable the PCI Controller" | ||
| 21 | default y | ||
| 22 | help | ||
| 23 | Say Y here if you want the IOP to initialize its PCI Controller. | ||
| 24 | Say N if the IOP is an add in card, the host system owns the PCI | ||
| 25 | bus in this case. | ||
| 26 | |||
| 27 | endmenu | 19 | endmenu |
| 28 | 20 | ||
| 29 | endif | 21 | endif |
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 433188ebff2a..de39fd778579 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c | |||
| @@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = { | |||
| 89 | .swizzle = pci_std_swizzle, | 89 | .swizzle = pci_std_swizzle, |
| 90 | .nr_controllers = 1, | 90 | .nr_controllers = 1, |
| 91 | .setup = iop3xx_pci_setup, | 91 | .setup = iop3xx_pci_setup, |
| 92 | .preinit = iop3xx_pci_preinit, | 92 | .preinit = iop3xx_pci_preinit_cond, |
| 93 | .scan = iop3xx_pci_scan_bus, | 93 | .scan = iop3xx_pci_scan_bus, |
| 94 | .map_irq = iq80331_pci_map_irq, | 94 | .map_irq = iq80331_pci_map_irq, |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 416c09564cc6..4904fd78445f 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c | |||
| @@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = { | |||
| 89 | .swizzle = pci_std_swizzle, | 89 | .swizzle = pci_std_swizzle, |
| 90 | .nr_controllers = 1, | 90 | .nr_controllers = 1, |
| 91 | .setup = iop3xx_pci_setup, | 91 | .setup = iop3xx_pci_setup, |
| 92 | .preinit = iop3xx_pci_preinit, | 92 | .preinit = iop3xx_pci_preinit_cond, |
| 93 | .scan = iop3xx_pci_scan_bus, | 93 | .scan = iop3xx_pci_scan_bus, |
| 94 | .map_irq = iq80332_pci_map_irq, | 94 | .map_irq = iq80332_pci_map_irq, |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index 730a3af12c98..ade42b73afbb 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile | |||
| @@ -11,5 +11,8 @@ obj- := | |||
| 11 | # PCI support is optional | 11 | # PCI support is optional |
| 12 | obj-$(CONFIG_PCI) += pci.o | 12 | obj-$(CONFIG_PCI) += pci.o |
| 13 | 13 | ||
| 14 | # LEDs | ||
| 15 | obj-$(CONFIG_LEDS) += leds.o | ||
| 16 | |||
| 14 | # Board-specific support | 17 | # Board-specific support |
| 15 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o | 18 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o |
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c index 386593f8ac65..3db2ec61d06f 100644 --- a/arch/arm/mach-ks8695/devices.c +++ b/arch/arm/mach-ks8695/devices.c | |||
| @@ -176,6 +176,27 @@ static void __init ks8695_add_device_watchdog(void) {} | |||
| 176 | #endif | 176 | #endif |
| 177 | 177 | ||
| 178 | 178 | ||
| 179 | /* -------------------------------------------------------------------- | ||
| 180 | * LEDs | ||
| 181 | * -------------------------------------------------------------------- */ | ||
| 182 | |||
| 183 | #if defined(CONFIG_LEDS) | ||
| 184 | short ks8695_leds_cpu = -1; | ||
| 185 | short ks8695_leds_timer = -1; | ||
| 186 | |||
| 187 | void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) | ||
| 188 | { | ||
| 189 | /* Enable GPIO to access the LEDs */ | ||
| 190 | gpio_direction_output(cpu_led, 1); | ||
| 191 | gpio_direction_output(timer_led, 1); | ||
| 192 | |||
| 193 | ks8695_leds_cpu = cpu_led; | ||
| 194 | ks8695_leds_timer = timer_led; | ||
| 195 | } | ||
| 196 | #else | ||
| 197 | void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {} | ||
| 198 | #endif | ||
| 199 | |||
| 179 | /* -------------------------------------------------------------------- */ | 200 | /* -------------------------------------------------------------------- */ |
| 180 | 201 | ||
| 181 | /* | 202 | /* |
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c new file mode 100644 index 000000000000..d61762ae50d8 --- /dev/null +++ b/arch/arm/mach-ks8695/leds.c | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * LED driver for KS8695-based boards. | ||
| 3 | * | ||
| 4 | * Copyright (C) Andrew Victor | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | |||
| 15 | #include <asm/mach-types.h> | ||
| 16 | #include <asm/leds.h> | ||
| 17 | #include <asm/arch/devices.h> | ||
| 18 | #include <asm/arch/gpio.h> | ||
| 19 | |||
| 20 | |||
| 21 | static inline void ks8695_led_on(unsigned int led) | ||
| 22 | { | ||
| 23 | gpio_set_value(led, 0); | ||
| 24 | } | ||
| 25 | |||
| 26 | static inline void ks8695_led_off(unsigned int led) | ||
| 27 | { | ||
| 28 | gpio_set_value(led, 1); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void ks8695_led_toggle(unsigned int led) | ||
| 32 | { | ||
| 33 | unsigned long is_off = gpio_get_value(led); | ||
| 34 | if (is_off) | ||
| 35 | ks8695_led_on(led); | ||
| 36 | else | ||
| 37 | ks8695_led_off(led); | ||
| 38 | } | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | * Handle LED events. | ||
| 43 | */ | ||
| 44 | static void ks8695_leds_event(led_event_t evt) | ||
| 45 | { | ||
| 46 | unsigned long flags; | ||
| 47 | |||
| 48 | local_irq_save(flags); | ||
| 49 | |||
| 50 | switch(evt) { | ||
| 51 | case led_start: /* System startup */ | ||
| 52 | ks8695_led_on(ks8695_leds_cpu); | ||
| 53 | break; | ||
| 54 | |||
| 55 | case led_stop: /* System stop / suspend */ | ||
| 56 | ks8695_led_off(ks8695_leds_cpu); | ||
| 57 | break; | ||
| 58 | |||
| 59 | #ifdef CONFIG_LEDS_TIMER | ||
| 60 | case led_timer: /* Every 50 timer ticks */ | ||
| 61 | ks8695_led_toggle(ks8695_leds_timer); | ||
| 62 | break; | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifdef CONFIG_LEDS_CPU | ||
| 66 | case led_idle_start: /* Entering idle state */ | ||
| 67 | ks8695_led_off(ks8695_leds_cpu); | ||
| 68 | break; | ||
| 69 | |||
| 70 | case led_idle_end: /* Exit idle state */ | ||
| 71 | ks8695_led_on(ks8695_leds_cpu); | ||
| 72 | break; | ||
| 73 | #endif | ||
| 74 | |||
| 75 | default: | ||
| 76 | break; | ||
| 77 | } | ||
| 78 | |||
| 79 | local_irq_restore(flags); | ||
| 80 | } | ||
| 81 | |||
| 82 | |||
| 83 | static int __init leds_init(void) | ||
| 84 | { | ||
| 85 | if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1)) | ||
| 86 | return -ENODEV; | ||
| 87 | |||
| 88 | leds_event = ks8695_leds_event; | ||
| 89 | |||
| 90 | leds_event(led_start); | ||
| 91 | return 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | __initcall(leds_init); | ||
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig index 8584ed107991..dd0cd5ac4b8b 100644 --- a/arch/arm/mach-ns9xxx/Kconfig +++ b/arch/arm/mach-ns9xxx/Kconfig | |||
| @@ -2,9 +2,26 @@ if ARCH_NS9XXX | |||
| 2 | 2 | ||
| 3 | menu "NS9xxx Implementations" | 3 | menu "NS9xxx Implementations" |
| 4 | 4 | ||
| 5 | config NS9XXX_HAVE_SERIAL8250 | ||
| 6 | bool | ||
| 7 | |||
| 8 | config PROCESSOR_NS9360 | ||
| 9 | bool | ||
| 10 | |||
| 11 | config MODULE_CC9P9360 | ||
| 12 | bool | ||
| 13 | select PROCESSOR_NS9360 | ||
| 14 | |||
| 15 | config BOARD_A9M9750DEV | ||
| 16 | select NS9XXX_HAVE_SERIAL8250 | ||
| 17 | bool | ||
| 18 | |||
| 19 | config BOARD_JSCC9P9360 | ||
| 20 | bool | ||
| 21 | |||
| 5 | config MACH_CC9P9360DEV | 22 | config MACH_CC9P9360DEV |
| 6 | bool "ConnectCore 9P 9360 on an A9M9750 Devboard" | 23 | bool "ConnectCore 9P 9360 on an A9M9750 Devboard" |
| 7 | select PROCESSOR_NS9360 | 24 | select MODULE_CC9P9360 |
| 8 | select BOARD_A9M9750DEV | 25 | select BOARD_A9M9750DEV |
| 9 | help | 26 | help |
| 10 | Say Y here if you are using the Digi ConnectCore 9P 9360 | 27 | Say Y here if you are using the Digi ConnectCore 9P 9360 |
| @@ -12,21 +29,12 @@ config MACH_CC9P9360DEV | |||
| 12 | 29 | ||
| 13 | config MACH_CC9P9360JS | 30 | config MACH_CC9P9360JS |
| 14 | bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" | 31 | bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" |
| 15 | select PROCESSOR_NS9360 | 32 | select MODULE_CC9P9360 |
| 16 | select BOARD_JSCC9P9360 | 33 | select BOARD_JSCC9P9360 |
| 17 | help | 34 | help |
| 18 | Say Y here if you are using the Digi ConnectCore 9P 9360 | 35 | Say Y here if you are using the Digi ConnectCore 9P 9360 |
| 19 | on an JSCC9P9360 Development Board. | 36 | on an JSCC9P9360 Development Board. |
| 20 | 37 | ||
| 21 | config PROCESSOR_NS9360 | ||
| 22 | bool | ||
| 23 | |||
| 24 | config BOARD_A9M9750DEV | ||
| 25 | bool | ||
| 26 | |||
| 27 | config BOARD_JSCC9P9360 | ||
| 28 | bool | ||
| 29 | |||
| 30 | endmenu | 38 | endmenu |
| 31 | 39 | ||
| 32 | endif | 40 | endif |
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile index 6fb82b855a55..41efaf9ad50b 100644 --- a/arch/arm/mach-ns9xxx/Makefile +++ b/arch/arm/mach-ns9xxx/Makefile | |||
| @@ -1,7 +1,12 @@ | |||
| 1 | obj-y := irq.o time.o generic.o gpio.o | 1 | obj-y := clock.o generic.o gpio.o irq.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o | 3 | obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o |
| 4 | obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o | 4 | obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o |
| 5 | 5 | ||
| 6 | obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o | ||
| 7 | |||
| 6 | obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o | 8 | obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o |
| 7 | obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o | 9 | obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o |
| 10 | |||
| 11 | # platform devices | ||
| 12 | obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o | ||
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot index 75ed64e90fa4..54654919229b 100644 --- a/arch/arm/mach-ns9xxx/Makefile.boot +++ b/arch/arm/mach-ns9xxx/Makefile.boot | |||
| @@ -1,2 +1,2 @@ | |||
| 1 | zreladdr-y := 0x108000 | 1 | zreladdr-y := 0x8000 |
| 2 | params_phys-y := 0x100 | 2 | params_phys-y := 0x100 |
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0f65177f9e5f..a494b71c0195 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c | |||
| @@ -8,15 +8,14 @@ | |||
| 8 | * under the terms of the GNU General Public License version 2 as published by | 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. | 9 | * the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/serial_8250.h> | ||
| 13 | #include <linux/irq.h> | 11 | #include <linux/irq.h> |
| 14 | 12 | ||
| 15 | #include <asm/mach/map.h> | 13 | #include <asm/mach/map.h> |
| 16 | #include <asm/gpio.h> | 14 | #include <asm/gpio.h> |
| 17 | 15 | ||
| 18 | #include <asm/arch-ns9xxx/board.h> | 16 | #include <asm/arch-ns9xxx/board.h> |
| 19 | #include <asm/arch-ns9xxx/regs-sys.h> | 17 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 18 | #include <asm/arch-ns9xxx/regs-sys-ns9360.h> | ||
| 20 | #include <asm/arch-ns9xxx/regs-mem.h> | 19 | #include <asm/arch-ns9xxx/regs-mem.h> |
| 21 | #include <asm/arch-ns9xxx/regs-bbu.h> | 20 | #include <asm/arch-ns9xxx/regs-bbu.h> |
| 22 | #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h> | 21 | #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h> |
| @@ -105,9 +104,9 @@ void __init board_a9m9750dev_init_irq(void) | |||
| 105 | int i; | 104 | int i; |
| 106 | 105 | ||
| 107 | if (gpio_request(11, "board a9m9750dev extirq2") == 0) | 106 | if (gpio_request(11, "board a9m9750dev extirq2") == 0) |
| 108 | ns9xxx_gpio_configure(11, 0, 1); | 107 | ns9360_gpio_configure(11, 0, 1); |
| 109 | else | 108 | else |
| 110 | printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n", | 109 | printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", |
| 111 | __func__); | 110 | __func__); |
| 112 | 111 | ||
| 113 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { | 112 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { |
| @@ -116,69 +115,16 @@ void __init board_a9m9750dev_init_irq(void) | |||
| 116 | set_irq_flags(i, IRQF_VALID); | 115 | set_irq_flags(i, IRQF_VALID); |
| 117 | } | 116 | } |
| 118 | 117 | ||
| 119 | /* IRQ_EXT2: level sensitive + active low */ | 118 | /* IRQ_NS9XXX_EXT2: level sensitive + active low */ |
| 120 | eic = __raw_readl(SYS_EIC(2)); | 119 | eic = __raw_readl(SYS_EIC(2)); |
| 121 | REGSET(eic, SYS_EIC, PLTY, AL); | 120 | REGSET(eic, SYS_EIC, PLTY, AL); |
| 122 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); | 121 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); |
| 123 | __raw_writel(eic, SYS_EIC(2)); | 122 | __raw_writel(eic, SYS_EIC(2)); |
| 124 | 123 | ||
| 125 | set_irq_chained_handler(IRQ_EXT2, | 124 | set_irq_chained_handler(IRQ_NS9XXX_EXT2, |
| 126 | a9m9750dev_fpga_demux_handler); | 125 | a9m9750dev_fpga_demux_handler); |
| 127 | } | 126 | } |
| 128 | 127 | ||
| 129 | static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = { | ||
| 130 | { | ||
| 131 | .iobase = FPGA_UARTA_BASE, | ||
| 132 | .membase = (unsigned char*)FPGA_UARTA_BASE, | ||
| 133 | .mapbase = FPGA_UARTA_BASE, | ||
| 134 | .irq = IRQ_FPGA_UARTA, | ||
| 135 | .iotype = UPIO_MEM, | ||
| 136 | .uartclk = 18432000, | ||
| 137 | .regshift = 0, | ||
| 138 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 139 | }, { | ||
| 140 | .iobase = FPGA_UARTB_BASE, | ||
| 141 | .membase = (unsigned char*)FPGA_UARTB_BASE, | ||
| 142 | .mapbase = FPGA_UARTB_BASE, | ||
| 143 | .irq = IRQ_FPGA_UARTB, | ||
| 144 | .iotype = UPIO_MEM, | ||
| 145 | .uartclk = 18432000, | ||
| 146 | .regshift = 0, | ||
| 147 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 148 | }, { | ||
| 149 | .iobase = FPGA_UARTC_BASE, | ||
| 150 | .membase = (unsigned char*)FPGA_UARTC_BASE, | ||
| 151 | .mapbase = FPGA_UARTC_BASE, | ||
| 152 | .irq = IRQ_FPGA_UARTC, | ||
| 153 | .iotype = UPIO_MEM, | ||
| 154 | .uartclk = 18432000, | ||
| 155 | .regshift = 0, | ||
| 156 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 157 | }, { | ||
| 158 | .iobase = FPGA_UARTD_BASE, | ||
| 159 | .membase = (unsigned char*)FPGA_UARTD_BASE, | ||
| 160 | .mapbase = FPGA_UARTD_BASE, | ||
| 161 | .irq = IRQ_FPGA_UARTD, | ||
| 162 | .iotype = UPIO_MEM, | ||
| 163 | .uartclk = 18432000, | ||
| 164 | .regshift = 0, | ||
| 165 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 166 | }, { | ||
| 167 | /* end marker */ | ||
| 168 | }, | ||
| 169 | }; | ||
| 170 | |||
| 171 | static struct platform_device board_a9m9750dev_serial_device = { | ||
| 172 | .name = "serial8250", | ||
| 173 | .dev = { | ||
| 174 | .platform_data = board_a9m9750dev_serial8250_port, | ||
| 175 | }, | ||
| 176 | }; | ||
| 177 | |||
| 178 | static struct platform_device *board_a9m9750dev_devices[] __initdata = { | ||
| 179 | &board_a9m9750dev_serial_device, | ||
| 180 | }; | ||
| 181 | |||
| 182 | void __init board_a9m9750dev_init_machine(void) | 128 | void __init board_a9m9750dev_init_machine(void) |
| 183 | { | 129 | { |
| 184 | u32 reg; | 130 | u32 reg; |
| @@ -210,7 +156,4 @@ void __init board_a9m9750dev_init_machine(void) | |||
| 210 | __raw_writel(0x2, MEM_SMOED(0)); | 156 | __raw_writel(0x2, MEM_SMOED(0)); |
| 211 | __raw_writel(0x6, MEM_SMRD(0)); | 157 | __raw_writel(0x6, MEM_SMRD(0)); |
| 212 | __raw_writel(0x6, MEM_SMWD(0)); | 158 | __raw_writel(0x6, MEM_SMWD(0)); |
| 213 | |||
| 214 | platform_add_devices(board_a9m9750dev_devices, | ||
| 215 | ARRAY_SIZE(board_a9m9750dev_devices)); | ||
| 216 | } | 159 | } |
diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c new file mode 100644 index 000000000000..f8639161068f --- /dev/null +++ b/arch/arm/mach-ns9xxx/clock.c | |||
| @@ -0,0 +1,215 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/clock.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/err.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/list.h> | ||
| 14 | #include <linux/clk.h> | ||
| 15 | #include <linux/string.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | |||
| 18 | #include <asm/semaphore.h> | ||
| 19 | #include "clock.h" | ||
| 20 | |||
| 21 | static LIST_HEAD(clocks); | ||
| 22 | static DEFINE_SPINLOCK(clk_lock); | ||
| 23 | |||
| 24 | struct clk *clk_get(struct device *dev, const char *id) | ||
| 25 | { | ||
| 26 | struct clk *p, *ret = NULL, *retgen = NULL; | ||
| 27 | unsigned long flags; | ||
| 28 | int idno; | ||
| 29 | |||
| 30 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
| 31 | idno = -1; | ||
| 32 | else | ||
| 33 | idno = to_platform_device(dev)->id; | ||
| 34 | |||
| 35 | spin_lock_irqsave(&clk_lock, flags); | ||
| 36 | list_for_each_entry(p, &clocks, node) { | ||
| 37 | if (strcmp(id, p->name) == 0) { | ||
| 38 | if (p->id == idno) { | ||
| 39 | if (!try_module_get(p->owner)) | ||
| 40 | continue; | ||
| 41 | ret = p; | ||
| 42 | break; | ||
| 43 | } else if (p->id == -1) | ||
| 44 | /* remember match with id == -1 in case there is | ||
| 45 | * no clock for idno */ | ||
| 46 | retgen = p; | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | if (!ret && retgen && try_module_get(retgen->owner)) | ||
| 51 | ret = retgen; | ||
| 52 | |||
| 53 | if (ret) | ||
| 54 | ++ret->refcount; | ||
| 55 | |||
| 56 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 57 | |||
| 58 | return ret ? ret : ERR_PTR(-ENOENT); | ||
| 59 | } | ||
| 60 | EXPORT_SYMBOL(clk_get); | ||
| 61 | |||
| 62 | void clk_put(struct clk *clk) | ||
| 63 | { | ||
| 64 | module_put(clk->owner); | ||
| 65 | --clk->refcount; | ||
| 66 | } | ||
| 67 | EXPORT_SYMBOL(clk_put); | ||
| 68 | |||
| 69 | static int clk_enable_unlocked(struct clk *clk) | ||
| 70 | { | ||
| 71 | int ret = 0; | ||
| 72 | if (clk->parent) { | ||
| 73 | ret = clk_enable_unlocked(clk->parent); | ||
| 74 | if (ret) | ||
| 75 | return ret; | ||
| 76 | } | ||
| 77 | |||
| 78 | if (clk->usage++ == 0 && clk->endisable) | ||
| 79 | ret = clk->endisable(clk, 1); | ||
| 80 | |||
| 81 | return ret; | ||
| 82 | } | ||
| 83 | |||
| 84 | int clk_enable(struct clk *clk) | ||
| 85 | { | ||
| 86 | int ret; | ||
| 87 | unsigned long flags; | ||
| 88 | |||
| 89 | spin_lock_irqsave(&clk_lock, flags); | ||
| 90 | |||
| 91 | ret = clk_enable_unlocked(clk); | ||
| 92 | |||
| 93 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 94 | |||
| 95 | return ret; | ||
| 96 | } | ||
| 97 | EXPORT_SYMBOL(clk_enable); | ||
| 98 | |||
| 99 | static void clk_disable_unlocked(struct clk *clk) | ||
| 100 | { | ||
| 101 | if (--clk->usage == 0 && clk->endisable) | ||
| 102 | clk->endisable(clk, 0); | ||
| 103 | |||
| 104 | if (clk->parent) | ||
| 105 | clk_disable_unlocked(clk->parent); | ||
| 106 | } | ||
| 107 | |||
| 108 | void clk_disable(struct clk *clk) | ||
| 109 | { | ||
| 110 | unsigned long flags; | ||
| 111 | |||
| 112 | spin_lock_irqsave(&clk_lock, flags); | ||
| 113 | |||
| 114 | clk_disable_unlocked(clk); | ||
| 115 | |||
| 116 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 117 | } | ||
| 118 | EXPORT_SYMBOL(clk_disable); | ||
| 119 | |||
| 120 | unsigned long clk_get_rate(struct clk *clk) | ||
| 121 | { | ||
| 122 | if (clk->get_rate) | ||
| 123 | return clk->get_rate(clk); | ||
| 124 | |||
| 125 | if (clk->rate) | ||
| 126 | return clk->rate; | ||
| 127 | |||
| 128 | if (clk->parent) | ||
| 129 | return clk_get_rate(clk->parent); | ||
| 130 | |||
| 131 | return 0; | ||
| 132 | } | ||
| 133 | EXPORT_SYMBOL(clk_get_rate); | ||
| 134 | |||
| 135 | int clk_register(struct clk *clk) | ||
| 136 | { | ||
| 137 | unsigned long flags; | ||
| 138 | |||
| 139 | spin_lock_irqsave(&clk_lock, flags); | ||
| 140 | |||
| 141 | list_add(&clk->node, &clocks); | ||
| 142 | |||
| 143 | if (clk->parent) | ||
| 144 | ++clk->parent->refcount; | ||
| 145 | |||
| 146 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | int clk_unregister(struct clk *clk) | ||
| 152 | { | ||
| 153 | int ret = 0; | ||
| 154 | unsigned long flags; | ||
| 155 | |||
| 156 | spin_lock_irqsave(&clk_lock, flags); | ||
| 157 | |||
| 158 | if (clk->usage || clk->refcount) | ||
| 159 | ret = -EBUSY; | ||
| 160 | else | ||
| 161 | list_del(&clk->node); | ||
| 162 | |||
| 163 | if (clk->parent) | ||
| 164 | --clk->parent->refcount; | ||
| 165 | |||
| 166 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 167 | |||
| 168 | return ret; | ||
| 169 | } | ||
| 170 | |||
| 171 | #if defined CONFIG_DEBUG_FS | ||
| 172 | |||
| 173 | #include <linux/debugfs.h> | ||
| 174 | #include <linux/seq_file.h> | ||
| 175 | |||
| 176 | static int clk_debugfs_show(struct seq_file *s, void *null) | ||
| 177 | { | ||
| 178 | unsigned long flags; | ||
| 179 | struct clk *p; | ||
| 180 | |||
| 181 | spin_lock_irqsave(&clk_lock, flags); | ||
| 182 | |||
| 183 | list_for_each_entry(p, &clocks, node) | ||
| 184 | seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n", | ||
| 185 | p->name, p->id, p->usage, p->refcount, | ||
| 186 | p->usage ? clk_get_rate(p) : 0); | ||
| 187 | |||
| 188 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 189 | |||
| 190 | return 0; | ||
| 191 | } | ||
| 192 | |||
| 193 | static int clk_debugfs_open(struct inode *inode, struct file *file) | ||
| 194 | { | ||
| 195 | return single_open(file, clk_debugfs_show, NULL); | ||
| 196 | } | ||
| 197 | |||
| 198 | static struct file_operations clk_debugfs_operations = { | ||
| 199 | .open = clk_debugfs_open, | ||
| 200 | .read = seq_read, | ||
| 201 | .llseek = seq_lseek, | ||
| 202 | .release = single_release, | ||
| 203 | }; | ||
| 204 | |||
| 205 | static int __init clk_debugfs_init(void) | ||
| 206 | { | ||
| 207 | struct dentry *dentry; | ||
| 208 | |||
| 209 | dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL, | ||
| 210 | &clk_debugfs_operations); | ||
| 211 | return IS_ERR(dentry) ? PTR_ERR(dentry) : 0; | ||
| 212 | } | ||
| 213 | subsys_initcall(clk_debugfs_init); | ||
| 214 | |||
| 215 | #endif /* if defined CONFIG_DEBUG_FS */ | ||
diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h new file mode 100644 index 000000000000..b86c30dd79eb --- /dev/null +++ b/arch/arm/mach-ns9xxx/clock.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/clock.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __NS9XXX_CLOCK_H | ||
| 12 | #define __NS9XXX_CLOCK_H | ||
| 13 | |||
| 14 | #include <linux/list.h> | ||
| 15 | |||
| 16 | struct clk { | ||
| 17 | struct module *owner; | ||
| 18 | const char *name; | ||
| 19 | int id; | ||
| 20 | |||
| 21 | struct clk *parent; | ||
| 22 | |||
| 23 | unsigned long rate; | ||
| 24 | int (*endisable)(struct clk *, int enable); | ||
| 25 | unsigned long (*get_rate)(struct clk *); | ||
| 26 | |||
| 27 | struct list_head node; | ||
| 28 | unsigned long refcount; | ||
| 29 | unsigned long usage; | ||
| 30 | }; | ||
| 31 | |||
| 32 | int clk_register(struct clk *clk); | ||
| 33 | int clk_unregister(struct clk *clk); | ||
| 34 | |||
| 35 | #endif /* ifndef __NS9XXX_CLOCK_H */ | ||
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c index d742c921e34d..1e0f467879cc 100644 --- a/arch/arm/mach-ns9xxx/generic.c +++ b/arch/arm/mach-ns9xxx/generic.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/generic.c | 2 | * arch/arm/mach-ns9xxx/generic.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,34 +11,9 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <asm/memory.h> | 13 | #include <asm/memory.h> |
| 14 | #include <asm/page.h> | ||
| 15 | #include <asm/mach-types.h> | ||
| 16 | #include <asm/mach/map.h> | ||
| 17 | #include <asm/arch-ns9xxx/regs-sys.h> | ||
| 18 | #include <asm/arch-ns9xxx/regs-mem.h> | ||
| 19 | #include <asm/arch-ns9xxx/board.h> | ||
| 20 | 14 | ||
| 21 | #include "generic.h" | 15 | #include "generic.h" |
| 22 | 16 | ||
| 23 | static struct map_desc standard_io_desc[] __initdata = { | ||
| 24 | { /* BBus */ | ||
| 25 | .virtual = io_p2v(0x90000000), | ||
| 26 | .pfn = __phys_to_pfn(0x90000000), | ||
| 27 | .length = 0x00700000, | ||
| 28 | .type = MT_DEVICE, | ||
| 29 | }, { /* AHB */ | ||
| 30 | .virtual = io_p2v(0xa0100000), | ||
| 31 | .pfn = __phys_to_pfn(0xa0100000), | ||
| 32 | .length = 0x00900000, | ||
| 33 | .type = MT_DEVICE, | ||
| 34 | }, | ||
| 35 | }; | ||
| 36 | |||
| 37 | void __init ns9xxx_map_io(void) | ||
| 38 | { | ||
| 39 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | ||
| 40 | } | ||
| 41 | |||
| 42 | void __init ns9xxx_init_machine(void) | 17 | void __init ns9xxx_init_machine(void) |
| 43 | { | 18 | { |
| 44 | } | 19 | } |
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h index 687e291773f4..82493191aad6 100644 --- a/arch/arm/mach-ns9xxx/generic.h +++ b/arch/arm/mach-ns9xxx/generic.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/generic.h | 2 | * arch/arm/mach-ns9xxx/generic.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -13,7 +13,4 @@ | |||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | 14 | ||
| 15 | void __init ns9xxx_init_irq(void); | 15 | void __init ns9xxx_init_irq(void); |
| 16 | void __init ns9xxx_map_io(void); | ||
| 17 | void __init ns9xxx_init_machine(void); | 16 | void __init ns9xxx_init_machine(void); |
| 18 | |||
| 19 | extern struct sys_timer ns9xxx_timer; | ||
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c new file mode 100644 index 000000000000..cabfb879dda9 --- /dev/null +++ b/arch/arm/mach-ns9xxx/gpio-ns9360.c | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/gpio-ns9360.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/bug.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | |||
| 17 | #include <asm/arch-ns9xxx/regs-bbu.h> | ||
| 18 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 19 | |||
| 20 | #include "gpio-ns9360.h" | ||
| 21 | |||
| 22 | static inline int ns9360_valid_gpio(unsigned gpio) | ||
| 23 | { | ||
| 24 | return gpio <= 72; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio) | ||
| 28 | { | ||
| 29 | if (gpio < 56) | ||
| 30 | return BBU_GCONFb1(gpio / 8); | ||
| 31 | else | ||
| 32 | /* | ||
| 33 | * this could be optimised away on | ||
| 34 | * ns9750 only builds, but it isn't ... | ||
| 35 | */ | ||
| 36 | return BBU_GCONFb2((gpio - 56) / 8); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio) | ||
| 40 | { | ||
| 41 | if (gpio < 32) | ||
| 42 | return BBU_GCTRL1; | ||
| 43 | else if (gpio < 64) | ||
| 44 | return BBU_GCTRL2; | ||
| 45 | else | ||
| 46 | /* this could be optimised away on ns9750 only builds */ | ||
| 47 | return BBU_GCTRL3; | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio) | ||
| 51 | { | ||
| 52 | if (gpio < 32) | ||
| 53 | return BBU_GSTAT1; | ||
| 54 | else if (gpio < 64) | ||
| 55 | return BBU_GSTAT2; | ||
| 56 | else | ||
| 57 | /* this could be optimised away on ns9750 only builds */ | ||
| 58 | return BBU_GSTAT3; | ||
| 59 | } | ||
| 60 | |||
| 61 | /* | ||
| 62 | * each gpio can serve for 4 different purposes [0..3]. These are called | ||
| 63 | * "functions" and passed in the parameter func. Functions 0-2 are always some | ||
| 64 | * special things, function 3 is GPIO. If func == 3 dir specifies input or | ||
| 65 | * output, and with inv you can enable an inverter (independent of func). | ||
| 66 | */ | ||
| 67 | int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func) | ||
| 68 | { | ||
| 69 | void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio); | ||
| 70 | u32 confval; | ||
| 71 | |||
| 72 | confval = __raw_readl(conf); | ||
| 73 | REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); | ||
| 74 | REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); | ||
| 75 | REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); | ||
| 76 | __raw_writel(confval, conf); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | int ns9360_gpio_configure(unsigned gpio, int inv, int func) | ||
| 82 | { | ||
| 83 | if (likely(ns9360_valid_gpio(gpio))) { | ||
| 84 | if (func == 3) { | ||
| 85 | printk(KERN_WARNING "use gpio_direction_input " | ||
| 86 | "or gpio_direction_output\n"); | ||
| 87 | return -EINVAL; | ||
| 88 | } else | ||
| 89 | return __ns9360_gpio_configure(gpio, 0, inv, func); | ||
| 90 | } else | ||
| 91 | return -EINVAL; | ||
| 92 | } | ||
| 93 | EXPORT_SYMBOL(ns9360_gpio_configure); | ||
| 94 | |||
| 95 | int ns9360_gpio_get_value(unsigned gpio) | ||
| 96 | { | ||
| 97 | void __iomem *stat = ns9360_gpio_get_gstataddr(gpio); | ||
| 98 | int ret; | ||
| 99 | |||
| 100 | ret = 1 & (__raw_readl(stat) >> (gpio & 31)); | ||
| 101 | |||
| 102 | return ret; | ||
| 103 | } | ||
| 104 | |||
| 105 | void ns9360_gpio_set_value(unsigned gpio, int value) | ||
| 106 | { | ||
| 107 | void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio); | ||
| 108 | u32 ctrlval; | ||
| 109 | |||
| 110 | ctrlval = __raw_readl(ctrl); | ||
| 111 | |||
| 112 | if (value) | ||
| 113 | ctrlval |= 1 << (gpio & 31); | ||
| 114 | else | ||
| 115 | ctrlval &= ~(1 << (gpio & 31)); | ||
| 116 | |||
| 117 | __raw_writel(ctrlval, ctrl); | ||
| 118 | } | ||
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h new file mode 100644 index 000000000000..131cd1715caa --- /dev/null +++ b/arch/arm/mach-ns9xxx/gpio-ns9360.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/gpio-ns9360.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func); | ||
| 12 | int ns9360_gpio_get_value(unsigned gpio); | ||
| 13 | void ns9360_gpio_set_value(unsigned gpio, int value); | ||
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c index 5286e9fc1d30..b3c963b0c8f5 100644 --- a/arch/arm/mach-ns9xxx/gpio.c +++ b/arch/arm/mach-ns9xxx/gpio.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/gpio.c | 2 | * arch/arm/mach-ns9xxx/gpio.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -15,12 +15,13 @@ | |||
| 15 | 15 | ||
| 16 | #include <asm/arch-ns9xxx/gpio.h> | 16 | #include <asm/arch-ns9xxx/gpio.h> |
| 17 | #include <asm/arch-ns9xxx/processor.h> | 17 | #include <asm/arch-ns9xxx/processor.h> |
| 18 | #include <asm/arch-ns9xxx/regs-bbu.h> | 18 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 19 | #include <asm/io.h> | ||
| 20 | #include <asm/bug.h> | 19 | #include <asm/bug.h> |
| 21 | #include <asm/types.h> | 20 | #include <asm/types.h> |
| 22 | #include <asm/bitops.h> | 21 | #include <asm/bitops.h> |
| 23 | 22 | ||
| 23 | #include "gpio-ns9360.h" | ||
| 24 | |||
| 24 | #if defined(CONFIG_PROCESSOR_NS9360) | 25 | #if defined(CONFIG_PROCESSOR_NS9360) |
| 25 | #define GPIO_MAX 72 | 26 | #define GPIO_MAX 72 |
| 26 | #elif defined(CONFIG_PROCESSOR_NS9750) | 27 | #elif defined(CONFIG_PROCESSOR_NS9750) |
| @@ -45,41 +46,10 @@ static inline int ns9xxx_valid_gpio(unsigned gpio) | |||
| 45 | return gpio <= 49; | 46 | return gpio <= 49; |
| 46 | else | 47 | else |
| 47 | #endif | 48 | #endif |
| 49 | { | ||
| 48 | BUG(); | 50 | BUG(); |
| 49 | } | 51 | return 0; |
| 50 | 52 | } | |
| 51 | static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio) | ||
| 52 | { | ||
| 53 | if (gpio < 56) | ||
| 54 | return BBU_GCONFb1(gpio / 8); | ||
| 55 | else | ||
| 56 | /* | ||
| 57 | * this could be optimised away on | ||
| 58 | * ns9750 only builds, but it isn't ... | ||
| 59 | */ | ||
| 60 | return BBU_GCONFb2((gpio - 56) / 8); | ||
| 61 | } | ||
| 62 | |||
| 63 | static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio) | ||
| 64 | { | ||
| 65 | if (gpio < 32) | ||
| 66 | return BBU_GCTRL1; | ||
| 67 | else if (gpio < 64) | ||
| 68 | return BBU_GCTRL2; | ||
| 69 | else | ||
| 70 | /* this could be optimised away on ns9750 only builds */ | ||
| 71 | return BBU_GCTRL3; | ||
| 72 | } | ||
| 73 | |||
| 74 | static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio) | ||
| 75 | { | ||
| 76 | if (gpio < 32) | ||
| 77 | return BBU_GSTAT1; | ||
| 78 | else if (gpio < 64) | ||
| 79 | return BBU_GSTAT2; | ||
| 80 | else | ||
| 81 | /* this could be optimised away on ns9750 only builds */ | ||
| 82 | return BBU_GSTAT3; | ||
| 83 | } | 53 | } |
| 84 | 54 | ||
| 85 | int gpio_request(unsigned gpio, const char *label) | 55 | int gpio_request(unsigned gpio, const char *label) |
| @@ -98,49 +68,24 @@ void gpio_free(unsigned gpio) | |||
| 98 | } | 68 | } |
| 99 | EXPORT_SYMBOL(gpio_free); | 69 | EXPORT_SYMBOL(gpio_free); |
| 100 | 70 | ||
| 101 | /* | 71 | int gpio_direction_input(unsigned gpio) |
| 102 | * each gpio can serve for 4 different purposes [0..3]. These are called | ||
| 103 | * "functions" and passed in the parameter func. Functions 0-2 are always some | ||
| 104 | * special things, function 3 is GPIO. If func == 3 dir specifies input or | ||
| 105 | * output, and with inv you can enable an inverter (independent of func). | ||
| 106 | */ | ||
| 107 | static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func) | ||
| 108 | { | 72 | { |
| 109 | void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio); | 73 | if (likely(ns9xxx_valid_gpio(gpio))) { |
| 110 | u32 confval; | 74 | int ret = -EINVAL; |
| 111 | unsigned long flags; | 75 | unsigned long flags; |
| 112 | |||
| 113 | spin_lock_irqsave(&gpio_lock, flags); | ||
| 114 | |||
| 115 | confval = __raw_readl(conf); | ||
| 116 | REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); | ||
| 117 | REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); | ||
| 118 | REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); | ||
| 119 | __raw_writel(confval, conf); | ||
| 120 | 76 | ||
| 121 | spin_unlock_irqrestore(&gpio_lock, flags); | 77 | spin_lock_irqsave(&gpio_lock, flags); |
| 78 | #if defined(CONFIG_PROCESSOR_NS9360) | ||
| 79 | if (processor_is_ns9360()) | ||
| 80 | ret = __ns9360_gpio_configure(gpio, 0, 0, 3); | ||
| 81 | else | ||
| 82 | #endif | ||
| 83 | BUG(); | ||
| 122 | 84 | ||
| 123 | return 0; | 85 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 124 | } | ||
| 125 | 86 | ||
| 126 | int ns9xxx_gpio_configure(unsigned gpio, int inv, int func) | 87 | return ret; |
| 127 | { | ||
| 128 | if (likely(ns9xxx_valid_gpio(gpio))) { | ||
| 129 | if (func == 3) { | ||
| 130 | printk(KERN_WARNING "use gpio_direction_input " | ||
| 131 | "or gpio_direction_output\n"); | ||
| 132 | return -EINVAL; | ||
| 133 | } else | ||
| 134 | return __ns9xxx_gpio_configure(gpio, 0, inv, func); | ||
| 135 | } else | ||
| 136 | return -EINVAL; | ||
| 137 | } | ||
| 138 | EXPORT_SYMBOL(ns9xxx_gpio_configure); | ||
| 139 | 88 | ||
| 140 | int gpio_direction_input(unsigned gpio) | ||
| 141 | { | ||
| 142 | if (likely(ns9xxx_valid_gpio(gpio))) { | ||
| 143 | return __ns9xxx_gpio_configure(gpio, 0, 0, 3); | ||
| 144 | } else | 89 | } else |
| 145 | return -EINVAL; | 90 | return -EINVAL; |
| 146 | } | 91 | } |
| @@ -149,9 +94,22 @@ EXPORT_SYMBOL(gpio_direction_input); | |||
| 149 | int gpio_direction_output(unsigned gpio, int value) | 94 | int gpio_direction_output(unsigned gpio, int value) |
| 150 | { | 95 | { |
| 151 | if (likely(ns9xxx_valid_gpio(gpio))) { | 96 | if (likely(ns9xxx_valid_gpio(gpio))) { |
| 97 | int ret = -EINVAL; | ||
| 98 | unsigned long flags; | ||
| 99 | |||
| 152 | gpio_set_value(gpio, value); | 100 | gpio_set_value(gpio, value); |
| 153 | 101 | ||
| 154 | return __ns9xxx_gpio_configure(gpio, 1, 0, 3); | 102 | spin_lock_irqsave(&gpio_lock, flags); |
| 103 | #if defined(CONFIG_PROCESSOR_NS9360) | ||
| 104 | if (processor_is_ns9360()) | ||
| 105 | ret = __ns9360_gpio_configure(gpio, 1, 0, 3); | ||
| 106 | else | ||
| 107 | #endif | ||
| 108 | BUG(); | ||
| 109 | |||
| 110 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
| 111 | |||
| 112 | return ret; | ||
| 155 | } else | 113 | } else |
| 156 | return -EINVAL; | 114 | return -EINVAL; |
| 157 | } | 115 | } |
| @@ -159,31 +117,28 @@ EXPORT_SYMBOL(gpio_direction_output); | |||
| 159 | 117 | ||
| 160 | int gpio_get_value(unsigned gpio) | 118 | int gpio_get_value(unsigned gpio) |
| 161 | { | 119 | { |
| 162 | void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio); | 120 | #if defined(CONFIG_PROCESSOR_NS9360) |
| 163 | int ret; | 121 | if (processor_is_ns9360()) |
| 164 | 122 | return ns9360_gpio_get_value(gpio); | |
| 165 | ret = 1 & (__raw_readl(stat) >> (gpio & 31)); | 123 | else |
| 166 | 124 | #endif | |
| 167 | return ret; | 125 | { |
| 126 | BUG(); | ||
| 127 | return -EINVAL; | ||
| 128 | } | ||
| 168 | } | 129 | } |
| 169 | EXPORT_SYMBOL(gpio_get_value); | 130 | EXPORT_SYMBOL(gpio_get_value); |
| 170 | 131 | ||
| 171 | void gpio_set_value(unsigned gpio, int value) | 132 | void gpio_set_value(unsigned gpio, int value) |
| 172 | { | 133 | { |
| 173 | void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio); | ||
| 174 | u32 ctrlval; | ||
| 175 | unsigned long flags; | 134 | unsigned long flags; |
| 176 | |||
| 177 | spin_lock_irqsave(&gpio_lock, flags); | 135 | spin_lock_irqsave(&gpio_lock, flags); |
| 178 | 136 | #if defined(CONFIG_PROCESSOR_NS9360) | |
| 179 | ctrlval = __raw_readl(ctrl); | 137 | if (processor_is_ns9360()) |
| 180 | 138 | ns9360_gpio_set_value(gpio, value); | |
| 181 | if (value) | ||
| 182 | ctrlval |= 1 << (gpio & 31); | ||
| 183 | else | 139 | else |
| 184 | ctrlval &= ~(1 << (gpio & 31)); | 140 | #endif |
| 185 | 141 | BUG(); | |
| 186 | __raw_writel(ctrlval, ctrl); | ||
| 187 | 142 | ||
| 188 | spin_unlock_irqrestore(&gpio_lock, flags); | 143 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 189 | } | 144 | } |
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 00001b874e97..36e5835e6097 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c | |||
| @@ -9,21 +9,27 @@ | |||
| 9 | * the Free Software Foundation. | 9 | * the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/kernel_stat.h> | ||
| 12 | #include <asm/io.h> | 13 | #include <asm/io.h> |
| 13 | #include <asm/mach/irq.h> | 14 | #include <asm/mach/irq.h> |
| 14 | #include <asm/mach-types.h> | 15 | #include <asm/mach-types.h> |
| 15 | #include <asm/arch-ns9xxx/regs-sys.h> | 16 | #include <asm/arch-ns9xxx/regs-sys-common.h> |
| 16 | #include <asm/arch-ns9xxx/irqs.h> | 17 | #include <asm/arch-ns9xxx/irqs.h> |
| 17 | #include <asm/arch-ns9xxx/board.h> | 18 | #include <asm/arch-ns9xxx/board.h> |
| 18 | 19 | ||
| 19 | #include "generic.h" | 20 | #include "generic.h" |
| 20 | 21 | ||
| 22 | /* simple interrupt prio table: prio(x) < prio(y) <=> x < y */ | ||
| 23 | #define irq2prio(i) (i) | ||
| 24 | #define prio2irq(p) (p) | ||
| 25 | |||
| 21 | static void ns9xxx_mask_irq(unsigned int irq) | 26 | static void ns9xxx_mask_irq(unsigned int irq) |
| 22 | { | 27 | { |
| 23 | /* XXX: better use cpp symbols */ | 28 | /* XXX: better use cpp symbols */ |
| 24 | u32 ic = __raw_readl(SYS_IC(irq / 4)); | 29 | int prio = irq2prio(irq); |
| 25 | ic &= ~(1 << (7 + 8 * (3 - (irq & 3)))); | 30 | u32 ic = __raw_readl(SYS_IC(prio / 4)); |
| 26 | __raw_writel(ic, SYS_IC(irq / 4)); | 31 | ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); |
| 32 | __raw_writel(ic, SYS_IC(prio / 4)); | ||
| 27 | } | 33 | } |
| 28 | 34 | ||
| 29 | static void ns9xxx_ack_irq(unsigned int irq) | 35 | static void ns9xxx_ack_irq(unsigned int irq) |
| @@ -40,9 +46,10 @@ static void ns9xxx_maskack_irq(unsigned int irq) | |||
| 40 | static void ns9xxx_unmask_irq(unsigned int irq) | 46 | static void ns9xxx_unmask_irq(unsigned int irq) |
| 41 | { | 47 | { |
| 42 | /* XXX: better use cpp symbols */ | 48 | /* XXX: better use cpp symbols */ |
| 43 | u32 ic = __raw_readl(SYS_IC(irq / 4)); | 49 | int prio = irq2prio(irq); |
| 44 | ic |= 1 << (7 + 8 * (3 - (irq & 3))); | 50 | u32 ic = __raw_readl(SYS_IC(prio / 4)); |
| 45 | __raw_writel(ic, SYS_IC(irq / 4)); | 51 | ic |= 1 << (7 + 8 * (3 - (prio & 3))); |
| 52 | __raw_writel(ic, SYS_IC(prio / 4)); | ||
| 46 | } | 53 | } |
| 47 | 54 | ||
| 48 | static struct irq_chip ns9xxx_chip = { | 55 | static struct irq_chip ns9xxx_chip = { |
| @@ -52,24 +59,61 @@ static struct irq_chip ns9xxx_chip = { | |||
| 52 | .unmask = ns9xxx_unmask_irq, | 59 | .unmask = ns9xxx_unmask_irq, |
| 53 | }; | 60 | }; |
| 54 | 61 | ||
| 62 | #if 0 | ||
| 63 | #define handle_irq handle_level_irq | ||
| 64 | #else | ||
| 65 | void handle_prio_irq(unsigned int irq, struct irq_desc *desc) | ||
| 66 | { | ||
| 67 | unsigned int cpu = smp_processor_id(); | ||
| 68 | struct irqaction *action; | ||
| 69 | irqreturn_t action_ret; | ||
| 70 | |||
| 71 | spin_lock(&desc->lock); | ||
| 72 | |||
| 73 | if (unlikely(desc->status & IRQ_INPROGRESS)) | ||
| 74 | goto out_unlock; | ||
| 75 | |||
| 76 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
| 77 | kstat_cpu(cpu).irqs[irq]++; | ||
| 78 | |||
| 79 | action = desc->action; | ||
| 80 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | ||
| 81 | goto out_unlock; | ||
| 82 | |||
| 83 | desc->status |= IRQ_INPROGRESS; | ||
| 84 | spin_unlock(&desc->lock); | ||
| 85 | |||
| 86 | action_ret = handle_IRQ_event(irq, action); | ||
| 87 | |||
| 88 | spin_lock(&desc->lock); | ||
| 89 | desc->status &= ~IRQ_INPROGRESS; | ||
| 90 | if (!(desc->status & IRQ_DISABLED) && desc->chip->ack) | ||
| 91 | desc->chip->ack(irq); | ||
| 92 | |||
| 93 | out_unlock: | ||
| 94 | spin_unlock(&desc->lock); | ||
| 95 | } | ||
| 96 | #define handle_irq handle_prio_irq | ||
| 97 | #endif | ||
| 98 | |||
| 55 | void __init ns9xxx_init_irq(void) | 99 | void __init ns9xxx_init_irq(void) |
| 56 | { | 100 | { |
| 57 | int i; | 101 | int i; |
| 58 | 102 | ||
| 59 | /* disable all IRQs */ | 103 | /* disable all IRQs */ |
| 60 | for (i = 0; i < 8; ++i) | 104 | for (i = 0; i < 8; ++i) |
| 61 | __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 | | 105 | __raw_writel(prio2irq(4 * i) << 24 | |
| 62 | (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i)); | 106 | prio2irq(4 * i + 1) << 16 | |
| 107 | prio2irq(4 * i + 2) << 8 | | ||
| 108 | prio2irq(4 * i + 3), | ||
| 109 | SYS_IC(i)); | ||
| 63 | 110 | ||
| 64 | /* simple interrupt prio table: | ||
| 65 | * prio(x) < prio(y) <=> x < y | ||
| 66 | */ | ||
| 67 | for (i = 0; i < 32; ++i) | 111 | for (i = 0; i < 32; ++i) |
| 68 | __raw_writel(i, SYS_IVA(i)); | 112 | __raw_writel(prio2irq(i), SYS_IVA(i)); |
| 69 | 113 | ||
| 70 | for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) { | 114 | for (i = 0; i <= 31; ++i) { |
| 71 | set_irq_chip(i, &ns9xxx_chip); | 115 | set_irq_chip(i, &ns9xxx_chip); |
| 72 | set_irq_handler(i, handle_level_irq); | 116 | set_irq_handler(i, handle_irq); |
| 73 | set_irq_flags(i, IRQF_VALID); | 117 | set_irq_flags(i, IRQF_VALID); |
| 74 | } | 118 | } |
| 75 | } | 119 | } |
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c index 760c9d0db7c3..9623fff6b3bc 100644 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c +++ b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c | 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,12 +11,14 @@ | |||
| 11 | #include <asm/mach/arch.h> | 11 | #include <asm/mach/arch.h> |
| 12 | #include <asm/mach-types.h> | 12 | #include <asm/mach-types.h> |
| 13 | 13 | ||
| 14 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 15 | |||
| 14 | #include "board-a9m9750dev.h" | 16 | #include "board-a9m9750dev.h" |
| 15 | #include "generic.h" | 17 | #include "generic.h" |
| 16 | 18 | ||
| 17 | static void __init mach_cc9p9360dev_map_io(void) | 19 | static void __init mach_cc9p9360dev_map_io(void) |
| 18 | { | 20 | { |
| 19 | ns9xxx_map_io(); | 21 | ns9360_map_io(); |
| 20 | board_a9m9750dev_map_io(); | 22 | board_a9m9750dev_map_io(); |
| 21 | } | 23 | } |
| 22 | 24 | ||
| @@ -36,6 +38,6 @@ MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard") | |||
| 36 | .map_io = mach_cc9p9360dev_map_io, | 38 | .map_io = mach_cc9p9360dev_map_io, |
| 37 | .init_irq = mach_cc9p9360dev_init_irq, | 39 | .init_irq = mach_cc9p9360dev_init_irq, |
| 38 | .init_machine = mach_cc9p9360dev_init_machine, | 40 | .init_machine = mach_cc9p9360dev_init_machine, |
| 39 | .timer = &ns9xxx_timer, | 41 | .timer = &ns9360_timer, |
| 40 | .boot_params = 0x100, | 42 | .boot_params = 0x100, |
| 41 | MACHINE_END | 43 | MACHINE_END |
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c index 85c8b41105c9..fcc815bdd291 100644 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c +++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360js.c | 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360js.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,6 +11,8 @@ | |||
| 11 | #include <asm/mach/arch.h> | 11 | #include <asm/mach/arch.h> |
| 12 | #include <asm/mach-types.h> | 12 | #include <asm/mach-types.h> |
| 13 | 13 | ||
| 14 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 15 | |||
| 14 | #include "board-jscc9p9360.h" | 16 | #include "board-jscc9p9360.h" |
| 15 | #include "generic.h" | 17 | #include "generic.h" |
| 16 | 18 | ||
| @@ -21,9 +23,9 @@ static void __init mach_cc9p9360js_init_machine(void) | |||
| 21 | } | 23 | } |
| 22 | 24 | ||
| 23 | MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") | 25 | MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") |
| 24 | .map_io = ns9xxx_map_io, | 26 | .map_io = ns9360_map_io, |
| 25 | .init_irq = ns9xxx_init_irq, | 27 | .init_irq = ns9xxx_init_irq, |
| 26 | .init_machine = mach_cc9p9360js_init_machine, | 28 | .init_machine = mach_cc9p9360js_init_machine, |
| 27 | .timer = &ns9xxx_timer, | 29 | .timer = &ns9360_timer, |
| 28 | .boot_params = 0x100, | 30 | .boot_params = 0x100, |
| 29 | MACHINE_END | 31 | MACHINE_END |
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c new file mode 100644 index 000000000000..5aa5d9baf8c8 --- /dev/null +++ b/arch/arm/mach-ns9xxx/plat-serial8250.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/plat-serial8250.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/serial_8250.h> | ||
| 13 | |||
| 14 | #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h> | ||
| 15 | #include <asm/arch-ns9xxx/board.h> | ||
| 16 | |||
| 17 | #define DRIVER_NAME "serial8250" | ||
| 18 | |||
| 19 | static int __init ns9xxx_plat_serial8250_init(void) | ||
| 20 | { | ||
| 21 | struct plat_serial8250_port *pdata; | ||
| 22 | struct platform_device *pdev; | ||
| 23 | int ret = -ENOMEM; | ||
| 24 | int i; | ||
| 25 | |||
| 26 | if (!board_is_a9m9750dev()) | ||
| 27 | return -ENODEV; | ||
| 28 | |||
| 29 | pdev = platform_device_alloc(DRIVER_NAME, 0); | ||
| 30 | if (!pdev) | ||
| 31 | goto err; | ||
| 32 | |||
| 33 | pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL); | ||
| 34 | if (!pdata) | ||
| 35 | goto err; | ||
| 36 | |||
| 37 | pdev->dev.platform_data = pdata; | ||
| 38 | |||
| 39 | pdata[0].iobase = FPGA_UARTA_BASE; | ||
| 40 | pdata[1].iobase = FPGA_UARTB_BASE; | ||
| 41 | pdata[2].iobase = FPGA_UARTC_BASE; | ||
| 42 | pdata[3].iobase = FPGA_UARTD_BASE; | ||
| 43 | |||
| 44 | for (i = 0; i < 4; ++i) { | ||
| 45 | pdata[i].membase = (void __iomem *)pdata[i].iobase; | ||
| 46 | pdata[i].mapbase = pdata[i].iobase; | ||
| 47 | pdata[i].iotype = UPIO_MEM; | ||
| 48 | pdata[i].uartclk = 18432000; | ||
| 49 | pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | ||
| 50 | } | ||
| 51 | |||
| 52 | pdata[0].irq = IRQ_FPGA_UARTA; | ||
| 53 | pdata[1].irq = IRQ_FPGA_UARTB; | ||
| 54 | pdata[2].irq = IRQ_FPGA_UARTC; | ||
| 55 | pdata[3].irq = IRQ_FPGA_UARTD; | ||
| 56 | |||
| 57 | ret = platform_device_add(pdev); | ||
| 58 | if (ret) { | ||
| 59 | err: | ||
| 60 | platform_device_put(pdev); | ||
| 61 | |||
| 62 | printk(KERN_WARNING "Could not add %s (errno=%d)\n", | ||
| 63 | DRIVER_NAME, ret); | ||
| 64 | } | ||
| 65 | |||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | arch_initcall(ns9xxx_plat_serial8250_init); | ||
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c new file mode 100644 index 000000000000..2bee0b7fccbb --- /dev/null +++ b/arch/arm/mach-ns9xxx/processor-ns9360.c | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/processor-ns9360.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/io.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/slab.h> | ||
| 14 | |||
| 15 | #include <asm/page.h> | ||
| 16 | #include <asm/mach/map.h> | ||
| 17 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 18 | #include <asm/arch-ns9xxx/regs-sys-ns9360.h> | ||
| 19 | |||
| 20 | void ns9360_reset(char mode) | ||
| 21 | { | ||
| 22 | u32 reg; | ||
| 23 | |||
| 24 | reg = __raw_readl(SYS_PLL) >> 16; | ||
| 25 | REGSET(reg, SYS_PLL, SWC, YES); | ||
| 26 | __raw_writel(reg, SYS_PLL); | ||
| 27 | } | ||
| 28 | |||
| 29 | #define CRYSTAL 29491200 /* Hz */ | ||
| 30 | unsigned long ns9360_systemclock(void) | ||
| 31 | { | ||
| 32 | u32 pll = __raw_readl(SYS_PLL); | ||
| 33 | return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) | ||
| 34 | >> REGGETIM(pll, SYS_PLL, FS); | ||
| 35 | } | ||
| 36 | |||
| 37 | static struct map_desc ns9360_io_desc[] __initdata = { | ||
| 38 | { /* BBus */ | ||
| 39 | .virtual = io_p2v(0x90000000), | ||
| 40 | .pfn = __phys_to_pfn(0x90000000), | ||
| 41 | .length = 0x00700000, | ||
| 42 | .type = MT_DEVICE, | ||
| 43 | }, { /* AHB */ | ||
| 44 | .virtual = io_p2v(0xa0100000), | ||
| 45 | .pfn = __phys_to_pfn(0xa0100000), | ||
| 46 | .length = 0x00900000, | ||
| 47 | .type = MT_DEVICE, | ||
| 48 | }, | ||
| 49 | }; | ||
| 50 | |||
| 51 | void __init ns9360_map_io(void) | ||
| 52 | { | ||
| 53 | iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc)); | ||
| 54 | } | ||
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time-ns9360.c index c3dd1f4acb99..4d573c9793ed 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time-ns9360.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/time.c | 2 | * arch/arm/mach-ns9xxx/time-ns9360.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -15,8 +15,8 @@ | |||
| 15 | #include <linux/clocksource.h> | 15 | #include <linux/clocksource.h> |
| 16 | #include <linux/clockchips.h> | 16 | #include <linux/clockchips.h> |
| 17 | 17 | ||
| 18 | #include <asm/arch-ns9xxx/regs-sys.h> | 18 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 19 | #include <asm/arch-ns9xxx/clock.h> | 19 | #include <asm/arch-ns9xxx/regs-sys-ns9360.h> |
| 20 | #include <asm/arch-ns9xxx/irqs.h> | 20 | #include <asm/arch-ns9xxx/irqs.h> |
| 21 | #include <asm/arch/system.h> | 21 | #include <asm/arch/system.h> |
| 22 | #include "generic.h" | 22 | #include "generic.h" |
| @@ -25,26 +25,26 @@ | |||
| 25 | #define TIMER_CLOCKEVENT 1 | 25 | #define TIMER_CLOCKEVENT 1 |
| 26 | static u32 latch; | 26 | static u32 latch; |
| 27 | 27 | ||
| 28 | static cycle_t ns9xxx_clocksource_read(void) | 28 | static cycle_t ns9360_clocksource_read(void) |
| 29 | { | 29 | { |
| 30 | return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); | 30 | return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static struct clocksource ns9xxx_clocksource = { | 33 | static struct clocksource ns9360_clocksource = { |
| 34 | .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE), | 34 | .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE), |
| 35 | .rating = 300, | 35 | .rating = 300, |
| 36 | .read = ns9xxx_clocksource_read, | 36 | .read = ns9360_clocksource_read, |
| 37 | .mask = CLOCKSOURCE_MASK(32), | 37 | .mask = CLOCKSOURCE_MASK(32), |
| 38 | .shift = 20, | 38 | .shift = 20, |
| 39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, | 42 | static void ns9360_clockevent_setmode(enum clock_event_mode mode, |
| 43 | struct clock_event_device *clk) | 43 | struct clock_event_device *clk) |
| 44 | { | 44 | { |
| 45 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); | 45 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
| 46 | 46 | ||
| 47 | switch(mode) { | 47 | switch (mode) { |
| 48 | case CLOCK_EVT_MODE_PERIODIC: | 48 | case CLOCK_EVT_MODE_PERIODIC: |
| 49 | __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); | 49 | __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); |
| 50 | REGSET(tc, SYS_TCx, REN, EN); | 50 | REGSET(tc, SYS_TCx, REN, EN); |
| @@ -69,7 +69,7 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, | |||
| 69 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); | 69 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
| 70 | } | 70 | } |
| 71 | 71 | ||
| 72 | static int ns9xxx_clockevent_setnextevent(unsigned long evt, | 72 | static int ns9360_clockevent_setnextevent(unsigned long evt, |
| 73 | struct clock_event_device *clk) | 73 | struct clock_event_device *clk) |
| 74 | { | 74 | { |
| 75 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); | 75 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
| @@ -88,20 +88,20 @@ static int ns9xxx_clockevent_setnextevent(unsigned long evt, | |||
| 88 | return 0; | 88 | return 0; |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | static struct clock_event_device ns9xxx_clockevent_device = { | 91 | static struct clock_event_device ns9360_clockevent_device = { |
| 92 | .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), | 92 | .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), |
| 93 | .shift = 20, | 93 | .shift = 20, |
| 94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 95 | .set_mode = ns9xxx_clockevent_setmode, | 95 | .set_mode = ns9360_clockevent_setmode, |
| 96 | .set_next_event = ns9xxx_clockevent_setnextevent, | 96 | .set_next_event = ns9360_clockevent_setnextevent, |
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) | 99 | static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id) |
| 100 | { | 100 | { |
| 101 | int timerno = irq - IRQ_TIMER0; | 101 | int timerno = irq - IRQ_NS9360_TIMER0; |
| 102 | u32 tc; | 102 | u32 tc; |
| 103 | 103 | ||
| 104 | struct clock_event_device *evt = &ns9xxx_clockevent_device; | 104 | struct clock_event_device *evt = &ns9360_clockevent_device; |
| 105 | 105 | ||
| 106 | /* clear irq */ | 106 | /* clear irq */ |
| 107 | tc = __raw_readl(SYS_TC(timerno)); | 107 | tc = __raw_readl(SYS_TC(timerno)); |
| @@ -119,13 +119,13 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) | |||
| 119 | return IRQ_HANDLED; | 119 | return IRQ_HANDLED; |
| 120 | } | 120 | } |
| 121 | 121 | ||
| 122 | static struct irqaction ns9xxx_clockevent_action = { | 122 | static struct irqaction ns9360_clockevent_action = { |
| 123 | .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), | 123 | .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), |
| 124 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 124 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 125 | .handler = ns9xxx_clockevent_handler, | 125 | .handler = ns9360_clockevent_handler, |
| 126 | }; | 126 | }; |
| 127 | 127 | ||
| 128 | static void __init ns9xxx_timer_init(void) | 128 | static void __init ns9360_timer_init(void) |
| 129 | { | 129 | { |
| 130 | int tc; | 130 | int tc; |
| 131 | 131 | ||
| @@ -148,12 +148,12 @@ static void __init ns9xxx_timer_init(void) | |||
| 148 | 148 | ||
| 149 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); | 149 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); |
| 150 | 150 | ||
| 151 | ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(), | 151 | ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(), |
| 152 | ns9xxx_clocksource.shift); | 152 | ns9360_clocksource.shift); |
| 153 | 153 | ||
| 154 | clocksource_register(&ns9xxx_clocksource); | 154 | clocksource_register(&ns9360_clocksource); |
| 155 | 155 | ||
| 156 | latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0); | 156 | latch = SH_DIV(ns9360_cpuclock(), HZ, 0); |
| 157 | 157 | ||
| 158 | tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); | 158 | tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
| 159 | REGSET(tc, SYS_TCx, TEN, DIS); | 159 | REGSET(tc, SYS_TCx, TEN, DIS); |
| @@ -166,19 +166,20 @@ static void __init ns9xxx_timer_init(void) | |||
| 166 | REGSET(tc, SYS_TCx, REN, EN); | 166 | REGSET(tc, SYS_TCx, REN, EN); |
| 167 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); | 167 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
| 168 | 168 | ||
| 169 | ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(), | 169 | ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(), |
| 170 | NSEC_PER_SEC, ns9xxx_clockevent_device.shift); | 170 | NSEC_PER_SEC, ns9360_clockevent_device.shift); |
| 171 | ns9xxx_clockevent_device.max_delta_ns = | 171 | ns9360_clockevent_device.max_delta_ns = |
| 172 | clockevent_delta2ns(-1, &ns9xxx_clockevent_device); | 172 | clockevent_delta2ns(-1, &ns9360_clockevent_device); |
| 173 | ns9xxx_clockevent_device.min_delta_ns = | 173 | ns9360_clockevent_device.min_delta_ns = |
| 174 | clockevent_delta2ns(1, &ns9xxx_clockevent_device); | 174 | clockevent_delta2ns(1, &ns9360_clockevent_device); |
| 175 | 175 | ||
| 176 | ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0); | 176 | ns9360_clockevent_device.cpumask = cpumask_of_cpu(0); |
| 177 | clockevents_register_device(&ns9xxx_clockevent_device); | 177 | clockevents_register_device(&ns9360_clockevent_device); |
| 178 | 178 | ||
| 179 | setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action); | 179 | setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT, |
| 180 | &ns9360_clockevent_action); | ||
| 180 | } | 181 | } |
| 181 | 182 | ||
| 182 | struct sys_timer ns9xxx_timer = { | 183 | struct sys_timer ns9360_timer = { |
| 183 | .init = ns9xxx_timer_init, | 184 | .init = ns9360_timer_init, |
| 184 | }; | 185 | }; |
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c deleted file mode 100644 index 58cc3c0333b6..000000000000 --- a/arch/arm/mach-orion/addr-map.c +++ /dev/null | |||
| @@ -1,490 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <asm/hardware.h> | ||
| 16 | #include "common.h" | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The Orion has fully programable address map. There's a separate address | ||
| 20 | * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, | ||
| 21 | * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own | ||
| 22 | * address decode windows that allow it to access any of the Orion resources. | ||
| 23 | * | ||
| 24 | * CPU address decoding -- | ||
| 25 | * Linux assumes that it is the boot loader that already setup the access to | ||
| 26 | * DDR and internal registers. | ||
| 27 | * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. | ||
| 28 | * Setup access to various devices located on the device bus interface (e.g. | ||
| 29 | * flashes, RTC, etc) should be issued by machine-setup.c according to | ||
| 30 | * specific board population (by using orion_setup_cpu_win()). | ||
| 31 | * | ||
| 32 | * Non-CPU Masters address decoding -- | ||
| 33 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | ||
| 34 | * banks only (the typical use case). | ||
| 35 | * Setup access for each master to DDR is issued by common.c. | ||
| 36 | * | ||
| 37 | * Note: although orion_setbits() and orion_clrbits() are not atomic | ||
| 38 | * no locking is necessary here since code in this file is only called | ||
| 39 | * at boot time when there is no concurrency issues. | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Generic Address Decode Windows bit settings | ||
| 44 | */ | ||
| 45 | #define TARGET_DDR 0 | ||
| 46 | #define TARGET_PCI 3 | ||
| 47 | #define TARGET_PCIE 4 | ||
| 48 | #define TARGET_DEV_BUS 1 | ||
| 49 | #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ | ||
| 50 | ((n) == 1) ? 0xd : \ | ||
| 51 | ((n) == 2) ? 0xb : \ | ||
| 52 | ((n) == 3) ? 0x7 : 0xf) | ||
| 53 | #define ATTR_PCIE_MEM 0x59 | ||
| 54 | #define ATTR_PCIE_IO 0x51 | ||
| 55 | #define ATTR_PCI_MEM 0x59 | ||
| 56 | #define ATTR_PCI_IO 0x51 | ||
| 57 | #define ATTR_DEV_CS0 0x1e | ||
| 58 | #define ATTR_DEV_CS1 0x1d | ||
| 59 | #define ATTR_DEV_CS2 0x1b | ||
| 60 | #define ATTR_DEV_BOOT 0xf | ||
| 61 | #define WIN_EN 1 | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Helpers to get DDR banks info | ||
| 65 | */ | ||
| 66 | #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) | ||
| 67 | #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) | ||
| 68 | #define DDR_MAX_CS 4 | ||
| 69 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) | ||
| 70 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) | ||
| 71 | #define DDR_BANK_EN 1 | ||
| 72 | |||
| 73 | /* | ||
| 74 | * CPU Address Decode Windows registers | ||
| 75 | */ | ||
| 76 | #define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) | ||
| 77 | #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) | ||
| 78 | #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) | ||
| 79 | #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) | ||
| 80 | #define CPU_MAX_WIN 8 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Use this CPU address decode windows allocation | ||
| 84 | */ | ||
| 85 | #define CPU_WIN_PCIE_IO 0 | ||
| 86 | #define CPU_WIN_PCI_IO 1 | ||
| 87 | #define CPU_WIN_PCIE_MEM 2 | ||
| 88 | #define CPU_WIN_PCI_MEM 3 | ||
| 89 | #define CPU_WIN_DEV_BOOT 4 | ||
| 90 | #define CPU_WIN_DEV_CS0 5 | ||
| 91 | #define CPU_WIN_DEV_CS1 6 | ||
| 92 | #define CPU_WIN_DEV_CS2 7 | ||
| 93 | |||
| 94 | /* | ||
| 95 | * PCIE Address Decode Windows registers | ||
| 96 | */ | ||
| 97 | #define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) | ||
| 98 | #define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) | ||
| 99 | #define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) | ||
| 100 | #define PCIE_WIN_CTRL(n) (((n) < 5) ? \ | ||
| 101 | ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ | ||
| 102 | ORION_PCIE_REG(0x1880)) | ||
| 103 | #define PCIE_WIN_BASE(n) (((n) < 5) ? \ | ||
| 104 | ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ | ||
| 105 | ORION_PCIE_REG(0x1884)) | ||
| 106 | #define PCIE_WIN_REMAP(n) (((n) < 5) ? \ | ||
| 107 | ORION_PCIE_REG(0x182c + ((n) << 4)) : \ | ||
| 108 | ORION_PCIE_REG(0x188c)) | ||
| 109 | #define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) | ||
| 110 | #define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) | ||
| 111 | #define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) | ||
| 112 | #define PCIE_MAX_BARS 3 | ||
| 113 | #define PCIE_MAX_WINS 6 | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Use PCIE BAR '1' for all DDR banks | ||
| 117 | */ | ||
| 118 | #define PCIE_DRAM_BAR 1 | ||
| 119 | |||
| 120 | /* | ||
| 121 | * PCI Address Decode Windows registers | ||
| 122 | */ | ||
| 123 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ | ||
| 124 | ((n) == 1) ? ORION_PCI_REG(0xd08) : \ | ||
| 125 | ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ | ||
| 126 | ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) | ||
| 127 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ | ||
| 128 | ((n) == 1) ? ORION_PCI_REG(0xd48) : \ | ||
| 129 | ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ | ||
| 130 | ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) | ||
| 131 | #define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) | ||
| 132 | #define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) | ||
| 133 | #define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) | ||
| 134 | #define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) | ||
| 135 | #define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * PCI configuration heleprs for BAR settings | ||
| 139 | */ | ||
| 140 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | ||
| 141 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | ||
| 142 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Gigabit Ethernet Address Decode Windows registers | ||
| 146 | */ | ||
| 147 | #define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) | ||
| 148 | #define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) | ||
| 149 | #define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) | ||
| 150 | #define ETH_WIN_EN ORION_ETH_REG(0x290) | ||
| 151 | #define ETH_WIN_PROT ORION_ETH_REG(0x294) | ||
| 152 | #define ETH_MAX_WIN 6 | ||
| 153 | #define ETH_MAX_REMAP_WIN 4 | ||
| 154 | |||
| 155 | /* | ||
| 156 | * USB Address Decode Windows registers | ||
| 157 | */ | ||
| 158 | #define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ | ||
| 159 | : ORION_USB1_REG(0x320 + ((w) << 4))) | ||
| 160 | #define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ | ||
| 161 | : ORION_USB1_REG(0x324 + ((w) << 4))) | ||
| 162 | #define USB_MAX_WIN 4 | ||
| 163 | |||
| 164 | /* | ||
| 165 | * SATA Address Decode Windows registers | ||
| 166 | */ | ||
| 167 | #define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) | ||
| 168 | #define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) | ||
| 169 | #define SATA_MAX_WIN 4 | ||
| 170 | |||
| 171 | static int __init orion_cpu_win_can_remap(u32 win) | ||
| 172 | { | ||
| 173 | u32 dev, rev; | ||
| 174 | |||
| 175 | orion_pcie_id(&dev, &rev); | ||
| 176 | if ((dev == MV88F5281_DEV_ID && win < 4) | ||
| 177 | || (dev == MV88F5182_DEV_ID && win < 2) | ||
| 178 | || (dev == MV88F5181_DEV_ID && win < 2)) | ||
| 179 | return 1; | ||
| 180 | |||
| 181 | return 0; | ||
| 182 | } | ||
| 183 | |||
| 184 | void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) | ||
| 185 | { | ||
| 186 | u32 win, attr, ctrl; | ||
| 187 | |||
| 188 | switch (target) { | ||
| 189 | case ORION_PCIE_IO: | ||
| 190 | target = TARGET_PCIE; | ||
| 191 | attr = ATTR_PCIE_IO; | ||
| 192 | win = CPU_WIN_PCIE_IO; | ||
| 193 | break; | ||
| 194 | case ORION_PCI_IO: | ||
| 195 | target = TARGET_PCI; | ||
| 196 | attr = ATTR_PCI_IO; | ||
| 197 | win = CPU_WIN_PCI_IO; | ||
| 198 | break; | ||
| 199 | case ORION_PCIE_MEM: | ||
| 200 | target = TARGET_PCIE; | ||
| 201 | attr = ATTR_PCIE_MEM; | ||
| 202 | win = CPU_WIN_PCIE_MEM; | ||
| 203 | break; | ||
| 204 | case ORION_PCI_MEM: | ||
| 205 | target = TARGET_PCI; | ||
| 206 | attr = ATTR_PCI_MEM; | ||
| 207 | win = CPU_WIN_PCI_MEM; | ||
| 208 | break; | ||
| 209 | case ORION_DEV_BOOT: | ||
| 210 | target = TARGET_DEV_BUS; | ||
| 211 | attr = ATTR_DEV_BOOT; | ||
| 212 | win = CPU_WIN_DEV_BOOT; | ||
| 213 | break; | ||
| 214 | case ORION_DEV0: | ||
| 215 | target = TARGET_DEV_BUS; | ||
| 216 | attr = ATTR_DEV_CS0; | ||
| 217 | win = CPU_WIN_DEV_CS0; | ||
| 218 | break; | ||
| 219 | case ORION_DEV1: | ||
| 220 | target = TARGET_DEV_BUS; | ||
| 221 | attr = ATTR_DEV_CS1; | ||
| 222 | win = CPU_WIN_DEV_CS1; | ||
| 223 | break; | ||
| 224 | case ORION_DEV2: | ||
| 225 | target = TARGET_DEV_BUS; | ||
| 226 | attr = ATTR_DEV_CS2; | ||
| 227 | win = CPU_WIN_DEV_CS2; | ||
| 228 | break; | ||
| 229 | case ORION_DDR: | ||
| 230 | case ORION_REGS: | ||
| 231 | /* | ||
| 232 | * Must be mapped by bootloader. | ||
| 233 | */ | ||
| 234 | default: | ||
| 235 | target = attr = win = -1; | ||
| 236 | BUG(); | ||
| 237 | } | ||
| 238 | |||
| 239 | base &= 0xffff0000; | ||
| 240 | ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | | ||
| 241 | (target << 4) | WIN_EN); | ||
| 242 | |||
| 243 | orion_write(CPU_WIN_BASE(win), base); | ||
| 244 | orion_write(CPU_WIN_CTRL(win), ctrl); | ||
| 245 | |||
| 246 | if (orion_cpu_win_can_remap(win)) { | ||
| 247 | if (remap >= 0) { | ||
| 248 | orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | ||
| 249 | orion_write(CPU_WIN_REMAP_HI(win), 0); | ||
| 250 | } else { | ||
| 251 | orion_write(CPU_WIN_REMAP_LO(win), base); | ||
| 252 | orion_write(CPU_WIN_REMAP_HI(win), 0); | ||
| 253 | } | ||
| 254 | } | ||
| 255 | } | ||
| 256 | |||
| 257 | void __init orion_setup_cpu_wins(void) | ||
| 258 | { | ||
| 259 | int i; | ||
| 260 | |||
| 261 | /* | ||
| 262 | * First, disable and clear windows | ||
| 263 | */ | ||
| 264 | for (i = 0; i < CPU_MAX_WIN; i++) { | ||
| 265 | orion_write(CPU_WIN_BASE(i), 0); | ||
| 266 | orion_write(CPU_WIN_CTRL(i), 0); | ||
| 267 | if (orion_cpu_win_can_remap(i)) { | ||
| 268 | orion_write(CPU_WIN_REMAP_LO(i), 0); | ||
| 269 | orion_write(CPU_WIN_REMAP_HI(i), 0); | ||
| 270 | } | ||
| 271 | } | ||
| 272 | |||
| 273 | /* | ||
| 274 | * Setup windows for PCI+PCIe IO+MEM space. | ||
| 275 | */ | ||
| 276 | orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, | ||
| 277 | ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); | ||
| 278 | orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, | ||
| 279 | ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); | ||
| 280 | orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, | ||
| 281 | ORION_PCIE_MEM_SIZE, -1); | ||
| 282 | orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, | ||
| 283 | ORION_PCI_MEM_SIZE, -1); | ||
| 284 | } | ||
| 285 | |||
| 286 | /* | ||
| 287 | * Setup PCIE BARs and Address Decode Wins: | ||
| 288 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | ||
| 289 | * WIN[0-3] -> DRAM bank[0-3] | ||
| 290 | */ | ||
| 291 | void __init orion_setup_pcie_wins(void) | ||
| 292 | { | ||
| 293 | u32 base, size, i; | ||
| 294 | |||
| 295 | /* | ||
| 296 | * First, disable and clear BARs and windows | ||
| 297 | */ | ||
| 298 | for (i = 1; i < PCIE_MAX_BARS; i++) { | ||
| 299 | orion_write(PCIE_BAR_CTRL(i), 0); | ||
| 300 | orion_write(PCIE_BAR_LO(i), 0); | ||
| 301 | orion_write(PCIE_BAR_HI(i), 0); | ||
| 302 | } | ||
| 303 | |||
| 304 | for (i = 0; i < PCIE_MAX_WINS; i++) { | ||
| 305 | orion_write(PCIE_WIN_CTRL(i), 0); | ||
| 306 | orion_write(PCIE_WIN_BASE(i), 0); | ||
| 307 | orion_write(PCIE_WIN_REMAP(i), 0); | ||
| 308 | } | ||
| 309 | |||
| 310 | /* | ||
| 311 | * Setup windows for DDR banks. Count total DDR size on the fly. | ||
| 312 | */ | ||
| 313 | base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); | ||
| 314 | size = 0; | ||
| 315 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 316 | u32 bank_base, bank_size; | ||
| 317 | bank_size = orion_read(DDR_SIZE_CS(i)); | ||
| 318 | bank_base = orion_read(DDR_BASE_CS(i)); | ||
| 319 | if (bank_size & DDR_BANK_EN) { | ||
| 320 | bank_size = DDR_REG_TO_SIZE(bank_size); | ||
| 321 | bank_base = DDR_REG_TO_BASE(bank_base); | ||
| 322 | orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); | ||
| 323 | orion_write(PCIE_WIN_REMAP(i), 0); | ||
| 324 | orion_write(PCIE_WIN_CTRL(i), | ||
| 325 | ((bank_size-1) & 0xffff0000) | | ||
| 326 | (ATTR_DDR_CS(i) << 8) | | ||
| 327 | (TARGET_DDR << 4) | | ||
| 328 | (PCIE_DRAM_BAR << 1) | WIN_EN); | ||
| 329 | size += bank_size; | ||
| 330 | } | ||
| 331 | } | ||
| 332 | |||
| 333 | /* | ||
| 334 | * Setup BAR[1] to all DRAM banks | ||
| 335 | */ | ||
| 336 | orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); | ||
| 337 | orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); | ||
| 338 | orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), | ||
| 339 | ((size - 1) & 0xffff0000) | WIN_EN); | ||
| 340 | } | ||
| 341 | |||
| 342 | void __init orion_setup_pci_wins(void) | ||
| 343 | { | ||
| 344 | u32 base, size, i; | ||
| 345 | |||
| 346 | /* | ||
| 347 | * First, disable windows | ||
| 348 | */ | ||
| 349 | orion_write(PCI_BAR_ENABLE, 0xffffffff); | ||
| 350 | |||
| 351 | /* | ||
| 352 | * Setup windows for DDR banks. | ||
| 353 | */ | ||
| 354 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 355 | base = orion_read(DDR_BASE_CS(i)); | ||
| 356 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 357 | if (size & DDR_BANK_EN) { | ||
| 358 | u32 bus, dev, func, reg, val; | ||
| 359 | size = DDR_REG_TO_SIZE(size); | ||
| 360 | base = DDR_REG_TO_BASE(base); | ||
| 361 | bus = orion_pci_local_bus_nr(); | ||
| 362 | dev = orion_pci_local_dev_nr(); | ||
| 363 | func = PCI_CONF_FUNC_BAR_CS(i); | ||
| 364 | reg = PCI_CONF_REG_BAR_LO_CS(i); | ||
| 365 | orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); | ||
| 366 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, | ||
| 367 | (base & 0xfffff000) | (val & 0xfff)); | ||
| 368 | reg = PCI_CONF_REG_BAR_HI_CS(i); | ||
| 369 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); | ||
| 370 | orion_write(PCI_BAR_SIZE_DDR_CS(i), | ||
| 371 | (size - 1) & 0xfffff000); | ||
| 372 | orion_write(PCI_BAR_REMAP_DDR_CS(i), | ||
| 373 | base & 0xfffff000); | ||
| 374 | orion_clrbits(PCI_BAR_ENABLE, (1 << i)); | ||
| 375 | } | ||
| 376 | } | ||
| 377 | |||
| 378 | /* | ||
| 379 | * Disable automatic update of address remaping when writing to BARs | ||
| 380 | */ | ||
| 381 | orion_setbits(PCI_ADDR_DECODE_CTRL, 1); | ||
| 382 | } | ||
| 383 | |||
| 384 | void __init orion_setup_usb_wins(void) | ||
| 385 | { | ||
| 386 | int i; | ||
| 387 | u32 usb_if, dev, rev; | ||
| 388 | u32 max_usb_if = 1; | ||
| 389 | |||
| 390 | orion_pcie_id(&dev, &rev); | ||
| 391 | if (dev == MV88F5182_DEV_ID) | ||
| 392 | max_usb_if = 2; | ||
| 393 | |||
| 394 | for (usb_if = 0; usb_if < max_usb_if; usb_if++) { | ||
| 395 | /* | ||
| 396 | * First, disable and clear windows | ||
| 397 | */ | ||
| 398 | for (i = 0; i < USB_MAX_WIN; i++) { | ||
| 399 | orion_write(USB_WIN_BASE(usb_if, i), 0); | ||
| 400 | orion_write(USB_WIN_CTRL(usb_if, i), 0); | ||
| 401 | } | ||
| 402 | |||
| 403 | /* | ||
| 404 | * Setup windows for DDR banks. | ||
| 405 | */ | ||
| 406 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 407 | u32 base, size; | ||
| 408 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 409 | base = orion_read(DDR_BASE_CS(i)); | ||
| 410 | if (size & DDR_BANK_EN) { | ||
| 411 | base = DDR_REG_TO_BASE(base); | ||
| 412 | size = DDR_REG_TO_SIZE(size); | ||
| 413 | orion_write(USB_WIN_CTRL(usb_if, i), | ||
| 414 | ((size-1) & 0xffff0000) | | ||
| 415 | (ATTR_DDR_CS(i) << 8) | | ||
| 416 | (TARGET_DDR << 4) | WIN_EN); | ||
| 417 | orion_write(USB_WIN_BASE(usb_if, i), | ||
| 418 | base & 0xffff0000); | ||
| 419 | } | ||
| 420 | } | ||
| 421 | } | ||
| 422 | } | ||
| 423 | |||
| 424 | void __init orion_setup_eth_wins(void) | ||
| 425 | { | ||
| 426 | int i; | ||
| 427 | |||
| 428 | /* | ||
| 429 | * First, disable and clear windows | ||
| 430 | */ | ||
| 431 | for (i = 0; i < ETH_MAX_WIN; i++) { | ||
| 432 | orion_write(ETH_WIN_BASE(i), 0); | ||
| 433 | orion_write(ETH_WIN_SIZE(i), 0); | ||
| 434 | orion_setbits(ETH_WIN_EN, 1 << i); | ||
| 435 | orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 436 | if (i < ETH_MAX_REMAP_WIN) | ||
| 437 | orion_write(ETH_WIN_REMAP(i), 0); | ||
| 438 | } | ||
| 439 | |||
| 440 | /* | ||
| 441 | * Setup windows for DDR banks. | ||
| 442 | */ | ||
| 443 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 444 | u32 base, size; | ||
| 445 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 446 | base = orion_read(DDR_BASE_CS(i)); | ||
| 447 | if (size & DDR_BANK_EN) { | ||
| 448 | base = DDR_REG_TO_BASE(base); | ||
| 449 | size = DDR_REG_TO_SIZE(size); | ||
| 450 | orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); | ||
| 451 | orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | | ||
| 452 | (ATTR_DDR_CS(i) << 8) | | ||
| 453 | TARGET_DDR); | ||
| 454 | orion_clrbits(ETH_WIN_EN, 1 << i); | ||
| 455 | orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 456 | } | ||
| 457 | } | ||
| 458 | } | ||
| 459 | |||
| 460 | void __init orion_setup_sata_wins(void) | ||
| 461 | { | ||
| 462 | int i; | ||
| 463 | |||
| 464 | /* | ||
| 465 | * First, disable and clear windows | ||
| 466 | */ | ||
| 467 | for (i = 0; i < SATA_MAX_WIN; i++) { | ||
| 468 | orion_write(SATA_WIN_BASE(i), 0); | ||
| 469 | orion_write(SATA_WIN_CTRL(i), 0); | ||
| 470 | } | ||
| 471 | |||
| 472 | /* | ||
| 473 | * Setup windows for DDR banks. | ||
| 474 | */ | ||
| 475 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 476 | u32 base, size; | ||
| 477 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 478 | base = orion_read(DDR_BASE_CS(i)); | ||
| 479 | if (size & DDR_BANK_EN) { | ||
| 480 | base = DDR_REG_TO_BASE(base); | ||
| 481 | size = DDR_REG_TO_SIZE(size); | ||
| 482 | orion_write(SATA_WIN_CTRL(i), | ||
| 483 | ((size-1) & 0xffff0000) | | ||
| 484 | (ATTR_DDR_CS(i) << 8) | | ||
| 485 | (TARGET_DDR << 4) | WIN_EN); | ||
| 486 | orion_write(SATA_WIN_BASE(i), | ||
| 487 | base & 0xffff0000); | ||
| 488 | } | ||
| 489 | } | ||
| 490 | } | ||
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h deleted file mode 100644 index 501497cc2c4d..000000000000 --- a/arch/arm/mach-orion/common.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | #ifndef __ARCH_ORION_COMMON_H__ | ||
| 2 | #define __ARCH_ORION_COMMON_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Basic Orion init functions used early by machine-setup. | ||
| 6 | */ | ||
| 7 | |||
| 8 | void __init orion_map_io(void); | ||
| 9 | void __init orion_init_irq(void); | ||
| 10 | void __init orion_init(void); | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
| 14 | * functions to map its interfaces and by the machine-setup to map its on- | ||
| 15 | * board devices. Details in /mach-orion/addr-map.c | ||
| 16 | */ | ||
| 17 | |||
| 18 | enum orion_target { | ||
| 19 | ORION_DEV_BOOT = 0, | ||
| 20 | ORION_DEV0, | ||
| 21 | ORION_DEV1, | ||
| 22 | ORION_DEV2, | ||
| 23 | ORION_PCIE_MEM, | ||
| 24 | ORION_PCIE_IO, | ||
| 25 | ORION_PCI_MEM, | ||
| 26 | ORION_PCI_IO, | ||
| 27 | ORION_DDR, | ||
| 28 | ORION_REGS, | ||
| 29 | ORION_MAX_TARGETS | ||
| 30 | }; | ||
| 31 | |||
| 32 | void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); | ||
| 33 | void orion_setup_cpu_wins(void); | ||
| 34 | void orion_setup_eth_wins(void); | ||
| 35 | void orion_setup_usb_wins(void); | ||
| 36 | void orion_setup_pci_wins(void); | ||
| 37 | void orion_setup_pcie_wins(void); | ||
| 38 | void orion_setup_sata_wins(void); | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Shared code used internally by other Orion core functions. | ||
| 42 | * (/mach-orion/pci.c) | ||
| 43 | */ | ||
| 44 | |||
| 45 | struct pci_sys_data; | ||
| 46 | struct pci_bus; | ||
| 47 | |||
| 48 | void orion_pcie_id(u32 *dev, u32 *rev); | ||
| 49 | u32 orion_pcie_local_bus_nr(void); | ||
| 50 | u32 orion_pci_local_bus_nr(void); | ||
| 51 | u32 orion_pci_local_dev_nr(void); | ||
| 52 | int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); | ||
| 53 | struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | ||
| 54 | int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val); | ||
| 55 | int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val); | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
| 59 | * (/mach-orion/gpio.c). | ||
| 60 | */ | ||
| 61 | |||
| 62 | void __init orion_gpio_set_valid_pins(u32 pins); | ||
| 63 | void gpio_display(void); /* debug */ | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Orion system timer (clocksource + clockevnt, /mach-orion/time.c) | ||
| 67 | */ | ||
| 68 | extern struct sys_timer orion_timer; | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Pull in Orion Ethernet platform_data, used by machine-setup | ||
| 72 | */ | ||
| 73 | |||
| 74 | struct mv643xx_eth_platform_data; | ||
| 75 | |||
| 76 | void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Orion Sata platform_data, used by machine-setup | ||
| 80 | */ | ||
| 81 | |||
| 82 | struct mv_sata_platform_data; | ||
| 83 | |||
| 84 | void __init orion_sata_init(struct mv_sata_platform_data *sata_data); | ||
| 85 | |||
| 86 | struct machine_desc; | ||
| 87 | struct meminfo; | ||
| 88 | struct tag; | ||
| 89 | extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, | ||
| 90 | char **, struct meminfo *); | ||
| 91 | |||
| 92 | #endif /* __ARCH_ORION_COMMON_H__ */ | ||
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c deleted file mode 100644 index b109bb46681e..000000000000 --- a/arch/arm/mach-orion/pci.c +++ /dev/null | |||
| @@ -1,557 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion/pci.c | ||
| 3 | * | ||
| 4 | * PCI and PCIE functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/pci.h> | ||
| 15 | #include <asm/mach/pci.h> | ||
| 16 | #include "common.h" | ||
| 17 | |||
| 18 | /***************************************************************************** | ||
| 19 | * Orion has one PCIE controller and one PCI controller. | ||
| 20 | * | ||
| 21 | * Note1: The local PCIE bus number is '0'. The local PCI bus number | ||
| 22 | * follows the scanned PCIE bridged busses, if any. | ||
| 23 | * | ||
| 24 | * Note2: It is possible for PCI/PCIE agents to access many subsystem's | ||
| 25 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on | ||
| 26 | * device bus, Orion registers, etc. However this code only enable the | ||
| 27 | * access to DDR banks. | ||
| 28 | ****************************************************************************/ | ||
| 29 | |||
| 30 | |||
| 31 | /***************************************************************************** | ||
| 32 | * PCIE controller | ||
| 33 | ****************************************************************************/ | ||
| 34 | #define PCIE_CTRL ORION_PCIE_REG(0x1a00) | ||
| 35 | #define PCIE_STAT ORION_PCIE_REG(0x1a04) | ||
| 36 | #define PCIE_DEV_ID ORION_PCIE_REG(0x0000) | ||
| 37 | #define PCIE_CMD_STAT ORION_PCIE_REG(0x0004) | ||
| 38 | #define PCIE_DEV_REV ORION_PCIE_REG(0x0008) | ||
| 39 | #define PCIE_MASK ORION_PCIE_REG(0x1910) | ||
| 40 | #define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8) | ||
| 41 | #define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * PCIE_STAT bits | ||
| 45 | */ | ||
| 46 | #define PCIE_STAT_LINK_DOWN 1 | ||
| 47 | #define PCIE_STAT_BUS_OFFS 8 | ||
| 48 | #define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS) | ||
| 49 | #define PCIE_STAT_DEV_OFFS 20 | ||
| 50 | #define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS) | ||
| 51 | |||
| 52 | /* | ||
| 53 | * PCIE_CONF_ADDR bits | ||
| 54 | */ | ||
| 55 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc)) | ||
| 56 | #define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) | ||
| 57 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | ||
| 58 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | ||
| 59 | #define PCIE_CONF_ADDR_EN (1 << 31) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * PCIE config cycles are done by programming the PCIE_CONF_ADDR register | ||
| 63 | * and then reading the PCIE_CONF_DATA register. Need to make sure these | ||
| 64 | * transactions are atomic. | ||
| 65 | */ | ||
| 66 | static DEFINE_SPINLOCK(orion_pcie_lock); | ||
| 67 | |||
| 68 | void orion_pcie_id(u32 *dev, u32 *rev) | ||
| 69 | { | ||
| 70 | *dev = orion_read(PCIE_DEV_ID) >> 16; | ||
| 71 | *rev = orion_read(PCIE_DEV_REV) & 0xff; | ||
| 72 | } | ||
| 73 | |||
| 74 | u32 orion_pcie_local_bus_nr(void) | ||
| 75 | { | ||
| 76 | u32 stat = orion_read(PCIE_STAT); | ||
| 77 | return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS); | ||
| 78 | } | ||
| 79 | |||
| 80 | static u32 orion_pcie_local_dev_nr(void) | ||
| 81 | { | ||
| 82 | u32 stat = orion_read(PCIE_STAT); | ||
| 83 | return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS); | ||
| 84 | } | ||
| 85 | |||
| 86 | static u32 orion_pcie_no_link(void) | ||
| 87 | { | ||
| 88 | u32 stat = orion_read(PCIE_STAT); | ||
| 89 | return(stat & PCIE_STAT_LINK_DOWN); | ||
| 90 | } | ||
| 91 | |||
| 92 | static void orion_pcie_set_bus_nr(int nr) | ||
| 93 | { | ||
| 94 | orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK); | ||
| 95 | orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); | ||
| 96 | } | ||
| 97 | |||
| 98 | static void orion_pcie_master_slave_enable(void) | ||
| 99 | { | ||
| 100 | orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | | ||
| 101 | PCI_COMMAND_IO | | ||
| 102 | PCI_COMMAND_MEMORY); | ||
| 103 | } | ||
| 104 | |||
| 105 | static void orion_pcie_enable_interrupts(void) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * Enable interrupts lines | ||
| 109 | * INTA[24] INTB[25] INTC[26] INTD[27] | ||
| 110 | */ | ||
| 111 | orion_setbits(PCIE_MASK, 0xf<<24); | ||
| 112 | } | ||
| 113 | |||
| 114 | static int orion_pcie_valid_config(u32 bus, u32 dev) | ||
| 115 | { | ||
| 116 | /* | ||
| 117 | * Don't go out when trying to access -- | ||
| 118 | * 1. our own device | ||
| 119 | * 2. where there's no device connected (no link) | ||
| 120 | * 3. nonexisting devices on local bus | ||
| 121 | */ | ||
| 122 | |||
| 123 | if ((orion_pcie_local_bus_nr() == bus) && | ||
| 124 | (orion_pcie_local_dev_nr() == dev)) | ||
| 125 | return 0; | ||
| 126 | |||
| 127 | if (orion_pcie_no_link()) | ||
| 128 | return 0; | ||
| 129 | |||
| 130 | if (bus == orion_pcie_local_bus_nr()) | ||
| 131 | if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) || | ||
| 132 | ((orion_pcie_local_dev_nr() != 0) && (dev != 0))) | ||
| 133 | return 0; | ||
| 134 | |||
| 135 | return 1; | ||
| 136 | } | ||
| 137 | |||
| 138 | static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 139 | int size, u32 *val) | ||
| 140 | { | ||
| 141 | unsigned long flags; | ||
| 142 | unsigned int dev, rev, pcie_addr; | ||
| 143 | |||
| 144 | if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 145 | *val = 0xffffffff; | ||
| 146 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 147 | } | ||
| 148 | |||
| 149 | spin_lock_irqsave(&orion_pcie_lock, flags); | ||
| 150 | |||
| 151 | orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | | ||
| 152 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 153 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 154 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); | ||
| 155 | |||
| 156 | orion_pcie_id(&dev, &rev); | ||
| 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | ||
| 158 | /* extended register space */ | ||
| 159 | pcie_addr = ORION_PCIE_WA_VIRT_BASE; | ||
| 160 | pcie_addr |= PCIE_CONF_BUS(bus->number) | | ||
| 161 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 162 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 163 | PCIE_CONF_REG(where); | ||
| 164 | *val = orion_read(pcie_addr); | ||
| 165 | } else | ||
| 166 | *val = orion_read(PCIE_CONF_DATA); | ||
| 167 | |||
| 168 | if (size == 1) | ||
| 169 | *val = (*val >> (8*(where & 0x3))) & 0xff; | ||
| 170 | else if (size == 2) | ||
| 171 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | ||
| 172 | |||
| 173 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | ||
| 174 | |||
| 175 | return PCIBIOS_SUCCESSFUL; | ||
| 176 | } | ||
| 177 | |||
| 178 | |||
| 179 | static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 180 | int size, u32 val) | ||
| 181 | { | ||
| 182 | unsigned long flags; | ||
| 183 | int ret; | ||
| 184 | |||
| 185 | if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) | ||
| 186 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 187 | |||
| 188 | spin_lock_irqsave(&orion_pcie_lock, flags); | ||
| 189 | |||
| 190 | ret = PCIBIOS_SUCCESSFUL; | ||
| 191 | |||
| 192 | orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | | ||
| 193 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 194 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 195 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); | ||
| 196 | |||
| 197 | if (size == 4) { | ||
| 198 | __raw_writel(val, PCIE_CONF_DATA); | ||
| 199 | } else if (size == 2) { | ||
| 200 | __raw_writew(val, PCIE_CONF_DATA + (where & 0x3)); | ||
| 201 | } else if (size == 1) { | ||
| 202 | __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3)); | ||
| 203 | } else { | ||
| 204 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 205 | } | ||
| 206 | |||
| 207 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | ||
| 208 | |||
| 209 | return ret; | ||
| 210 | } | ||
| 211 | |||
| 212 | struct pci_ops orion_pcie_ops = { | ||
| 213 | .read = orion_pcie_rd_conf, | ||
| 214 | .write = orion_pcie_wr_conf, | ||
| 215 | }; | ||
| 216 | |||
| 217 | |||
| 218 | static int orion_pcie_setup(struct pci_sys_data *sys) | ||
| 219 | { | ||
| 220 | struct resource *res; | ||
| 221 | |||
| 222 | /* | ||
| 223 | * Master + Slave enable | ||
| 224 | */ | ||
| 225 | orion_pcie_master_slave_enable(); | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Enable interrupts lines A-D | ||
| 229 | */ | ||
| 230 | orion_pcie_enable_interrupts(); | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Request resource | ||
| 234 | */ | ||
| 235 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 236 | if (!res) | ||
| 237 | panic("orion_pci_setup unable to alloc resources"); | ||
| 238 | |||
| 239 | /* | ||
| 240 | * IORESOURCE_IO | ||
| 241 | */ | ||
| 242 | res[0].name = "PCI-EX I/O Space"; | ||
| 243 | res[0].flags = IORESOURCE_IO; | ||
| 244 | res[0].start = ORION_PCIE_IO_BUS_BASE; | ||
| 245 | res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; | ||
| 246 | if (request_resource(&ioport_resource, &res[0])) | ||
| 247 | panic("Request PCIE IO resource failed\n"); | ||
| 248 | sys->resource[0] = &res[0]; | ||
| 249 | |||
| 250 | /* | ||
| 251 | * IORESOURCE_MEM | ||
| 252 | */ | ||
| 253 | res[1].name = "PCI-EX Memory Space"; | ||
| 254 | res[1].flags = IORESOURCE_MEM; | ||
| 255 | res[1].start = ORION_PCIE_MEM_PHYS_BASE; | ||
| 256 | res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; | ||
| 257 | if (request_resource(&iomem_resource, &res[1])) | ||
| 258 | panic("Request PCIE Memory resource failed\n"); | ||
| 259 | sys->resource[1] = &res[1]; | ||
| 260 | |||
| 261 | sys->resource[2] = NULL; | ||
| 262 | sys->io_offset = 0; | ||
| 263 | |||
| 264 | return 1; | ||
| 265 | } | ||
| 266 | |||
| 267 | /***************************************************************************** | ||
| 268 | * PCI controller | ||
| 269 | ****************************************************************************/ | ||
| 270 | #define PCI_MODE ORION_PCI_REG(0xd00) | ||
| 271 | #define PCI_CMD ORION_PCI_REG(0xc00) | ||
| 272 | #define PCI_P2P_CONF ORION_PCI_REG(0x1d14) | ||
| 273 | #define PCI_CONF_ADDR ORION_PCI_REG(0xc78) | ||
| 274 | #define PCI_CONF_DATA ORION_PCI_REG(0xc7c) | ||
| 275 | |||
| 276 | /* | ||
| 277 | * PCI_MODE bits | ||
| 278 | */ | ||
| 279 | #define PCI_MODE_64BIT (1 << 2) | ||
| 280 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | ||
| 281 | |||
| 282 | /* | ||
| 283 | * PCI_CMD bits | ||
| 284 | */ | ||
| 285 | #define PCI_CMD_HOST_REORDER (1 << 29) | ||
| 286 | |||
| 287 | /* | ||
| 288 | * PCI_P2P_CONF bits | ||
| 289 | */ | ||
| 290 | #define PCI_P2P_BUS_OFFS 16 | ||
| 291 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | ||
| 292 | #define PCI_P2P_DEV_OFFS 24 | ||
| 293 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | ||
| 294 | |||
| 295 | /* | ||
| 296 | * PCI_CONF_ADDR bits | ||
| 297 | */ | ||
| 298 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | ||
| 299 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | ||
| 300 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | ||
| 301 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | ||
| 302 | #define PCI_CONF_ADDR_EN (1 << 31) | ||
| 303 | |||
| 304 | /* | ||
| 305 | * Internal configuration space | ||
| 306 | */ | ||
| 307 | #define PCI_CONF_FUNC_STAT_CMD 0 | ||
| 308 | #define PCI_CONF_REG_STAT_CMD 4 | ||
| 309 | #define PCIX_STAT 0x64 | ||
| 310 | #define PCIX_STAT_BUS_OFFS 8 | ||
| 311 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | ||
| 312 | |||
| 313 | /* | ||
| 314 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | ||
| 315 | * and then reading the PCI_CONF_DATA register. Need to make sure these | ||
| 316 | * transactions are atomic. | ||
| 317 | */ | ||
| 318 | static DEFINE_SPINLOCK(orion_pci_lock); | ||
| 319 | |||
| 320 | u32 orion_pci_local_bus_nr(void) | ||
| 321 | { | ||
| 322 | u32 conf = orion_read(PCI_P2P_CONF); | ||
| 323 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); | ||
| 324 | } | ||
| 325 | |||
| 326 | u32 orion_pci_local_dev_nr(void) | ||
| 327 | { | ||
| 328 | u32 conf = orion_read(PCI_P2P_CONF); | ||
| 329 | return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); | ||
| 330 | } | ||
| 331 | |||
| 332 | int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, | ||
| 333 | u32 where, u32 size, u32 *val) | ||
| 334 | { | ||
| 335 | unsigned long flags; | ||
| 336 | spin_lock_irqsave(&orion_pci_lock, flags); | ||
| 337 | |||
| 338 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 339 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 340 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 341 | |||
| 342 | *val = orion_read(PCI_CONF_DATA); | ||
| 343 | |||
| 344 | if (size == 1) | ||
| 345 | *val = (*val >> (8*(where & 0x3))) & 0xff; | ||
| 346 | else if (size == 2) | ||
| 347 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | ||
| 348 | |||
| 349 | spin_unlock_irqrestore(&orion_pci_lock, flags); | ||
| 350 | |||
| 351 | return PCIBIOS_SUCCESSFUL; | ||
| 352 | } | ||
| 353 | |||
| 354 | int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, | ||
| 355 | u32 where, u32 size, u32 val) | ||
| 356 | { | ||
| 357 | unsigned long flags; | ||
| 358 | int ret = PCIBIOS_SUCCESSFUL; | ||
| 359 | |||
| 360 | spin_lock_irqsave(&orion_pci_lock, flags); | ||
| 361 | |||
| 362 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 363 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 364 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 365 | |||
| 366 | if (size == 4) { | ||
| 367 | __raw_writel(val, PCI_CONF_DATA); | ||
| 368 | } else if (size == 2) { | ||
| 369 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 370 | } else if (size == 1) { | ||
| 371 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 372 | } else { | ||
| 373 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 374 | } | ||
| 375 | |||
| 376 | spin_unlock_irqrestore(&orion_pci_lock, flags); | ||
| 377 | |||
| 378 | return ret; | ||
| 379 | } | ||
| 380 | |||
| 381 | static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, | ||
| 382 | int where, int size, u32 *val) | ||
| 383 | { | ||
| 384 | /* | ||
| 385 | * Don't go out for local device | ||
| 386 | */ | ||
| 387 | if ((orion_pci_local_bus_nr() == bus->number) && | ||
| 388 | (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { | ||
| 389 | *val = 0xffffffff; | ||
| 390 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 391 | } | ||
| 392 | |||
| 393 | return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), | ||
| 394 | PCI_FUNC(devfn), where, size, val); | ||
| 395 | } | ||
| 396 | |||
| 397 | static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 398 | int where, int size, u32 val) | ||
| 399 | { | ||
| 400 | /* | ||
| 401 | * Don't go out for local device | ||
| 402 | */ | ||
| 403 | if ((orion_pci_local_bus_nr() == bus->number) && | ||
| 404 | (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) | ||
| 405 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 406 | |||
| 407 | return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), | ||
| 408 | PCI_FUNC(devfn), where, size, val); | ||
| 409 | } | ||
| 410 | |||
| 411 | struct pci_ops orion_pci_ops = { | ||
| 412 | .read = orion_pci_rd_conf, | ||
| 413 | .write = orion_pci_wr_conf, | ||
| 414 | }; | ||
| 415 | |||
| 416 | static void orion_pci_set_bus_nr(int nr) | ||
| 417 | { | ||
| 418 | u32 p2p = orion_read(PCI_P2P_CONF); | ||
| 419 | |||
| 420 | if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { | ||
| 421 | /* | ||
| 422 | * PCI-X mode | ||
| 423 | */ | ||
| 424 | u32 pcix_status, bus, dev; | ||
| 425 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | ||
| 426 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | ||
| 427 | orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); | ||
| 428 | pcix_status &= ~PCIX_STAT_BUS_MASK; | ||
| 429 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | ||
| 430 | orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); | ||
| 431 | } else { | ||
| 432 | /* | ||
| 433 | * PCI Conventional mode | ||
| 434 | */ | ||
| 435 | p2p &= ~PCI_P2P_BUS_MASK; | ||
| 436 | p2p |= (nr << PCI_P2P_BUS_OFFS); | ||
| 437 | orion_write(PCI_P2P_CONF, p2p); | ||
| 438 | } | ||
| 439 | } | ||
| 440 | |||
| 441 | static void orion_pci_master_slave_enable(void) | ||
| 442 | { | ||
| 443 | u32 bus_nr, dev_nr, func, reg, val; | ||
| 444 | |||
| 445 | bus_nr = orion_pci_local_bus_nr(); | ||
| 446 | dev_nr = orion_pci_local_dev_nr(); | ||
| 447 | func = PCI_CONF_FUNC_STAT_CMD; | ||
| 448 | reg = PCI_CONF_REG_STAT_CMD; | ||
| 449 | orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); | ||
| 450 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | ||
| 451 | orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); | ||
| 452 | } | ||
| 453 | |||
| 454 | static int orion_pci_setup(struct pci_sys_data *sys) | ||
| 455 | { | ||
| 456 | struct resource *res; | ||
| 457 | |||
| 458 | /* | ||
| 459 | * Master + Slave enable | ||
| 460 | */ | ||
| 461 | orion_pci_master_slave_enable(); | ||
| 462 | |||
| 463 | /* | ||
| 464 | * Force ordering | ||
| 465 | */ | ||
| 466 | orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); | ||
| 467 | |||
| 468 | /* | ||
| 469 | * Request resources | ||
| 470 | */ | ||
| 471 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 472 | if (!res) | ||
| 473 | panic("orion_pci_setup unable to alloc resources"); | ||
| 474 | |||
| 475 | /* | ||
| 476 | * IORESOURCE_IO | ||
| 477 | */ | ||
| 478 | res[0].name = "PCI I/O Space"; | ||
| 479 | res[0].flags = IORESOURCE_IO; | ||
| 480 | res[0].start = ORION_PCI_IO_BUS_BASE; | ||
| 481 | res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; | ||
| 482 | if (request_resource(&ioport_resource, &res[0])) | ||
| 483 | panic("Request PCI IO resource failed\n"); | ||
| 484 | sys->resource[0] = &res[0]; | ||
| 485 | |||
| 486 | /* | ||
| 487 | * IORESOURCE_MEM | ||
| 488 | */ | ||
| 489 | res[1].name = "PCI Memory Space"; | ||
| 490 | res[1].flags = IORESOURCE_MEM; | ||
| 491 | res[1].start = ORION_PCI_MEM_PHYS_BASE; | ||
| 492 | res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; | ||
| 493 | if (request_resource(&iomem_resource, &res[1])) | ||
| 494 | panic("Request PCI Memory resource failed\n"); | ||
| 495 | sys->resource[1] = &res[1]; | ||
| 496 | |||
| 497 | sys->resource[2] = NULL; | ||
| 498 | sys->io_offset = 0; | ||
| 499 | |||
| 500 | return 1; | ||
| 501 | } | ||
| 502 | |||
| 503 | |||
| 504 | /***************************************************************************** | ||
| 505 | * General PCIE + PCI | ||
| 506 | ****************************************************************************/ | ||
| 507 | int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) | ||
| 508 | { | ||
| 509 | int ret = 0; | ||
| 510 | |||
| 511 | if (nr == 0) { | ||
| 512 | /* | ||
| 513 | * PCIE setup | ||
| 514 | */ | ||
| 515 | orion_pcie_set_bus_nr(0); | ||
| 516 | ret = orion_pcie_setup(sys); | ||
| 517 | } else if (nr == 1) { | ||
| 518 | /* | ||
| 519 | * PCI setup | ||
| 520 | */ | ||
| 521 | ret = orion_pci_setup(sys); | ||
| 522 | } | ||
| 523 | |||
| 524 | return ret; | ||
| 525 | } | ||
| 526 | |||
| 527 | struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) | ||
| 528 | { | ||
| 529 | struct pci_ops *ops; | ||
| 530 | struct pci_bus *bus; | ||
| 531 | |||
| 532 | |||
| 533 | if (nr == 0) { | ||
| 534 | u32 pci_bus; | ||
| 535 | /* | ||
| 536 | * PCIE scan | ||
| 537 | */ | ||
| 538 | ops = &orion_pcie_ops; | ||
| 539 | bus = pci_scan_bus(sys->busnr, ops, sys); | ||
| 540 | /* | ||
| 541 | * Set local PCI bus number to follow PCIE bridges (if any) | ||
| 542 | */ | ||
| 543 | pci_bus = bus->number + bus->subordinate - bus->secondary + 1; | ||
| 544 | orion_pci_set_bus_nr(pci_bus); | ||
| 545 | } else if (nr == 1) { | ||
| 546 | /* | ||
| 547 | * PCI scan | ||
| 548 | */ | ||
| 549 | ops = &orion_pci_ops; | ||
| 550 | bus = pci_scan_bus(sys->busnr, ops, sys); | ||
| 551 | } else { | ||
| 552 | BUG(); | ||
| 553 | bus = NULL; | ||
| 554 | } | ||
| 555 | |||
| 556 | return bus; | ||
| 557 | } | ||
diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c deleted file mode 100644 index bd4262da4f40..000000000000 --- a/arch/arm/mach-orion/time.c +++ /dev/null | |||
| @@ -1,181 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion/time.c | ||
| 3 | * | ||
| 4 | * Core time functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/clockchips.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <asm/mach/time.h> | ||
| 18 | #include <asm/arch/orion.h> | ||
| 19 | #include "common.h" | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Timer0: clock_event_device, Tick. | ||
| 23 | * Timer1: clocksource, Free running. | ||
| 24 | * WatchDog: Not used. | ||
| 25 | * | ||
| 26 | * Timers are counting down. | ||
| 27 | */ | ||
| 28 | #define CLOCKEVENT 0 | ||
| 29 | #define CLOCKSOURCE 1 | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Timers bits | ||
| 33 | */ | ||
| 34 | #define BRIDGE_INT_TIMER(x) (1 << ((x) + 1)) | ||
| 35 | #define TIMER_EN(x) (1 << ((x) * 2)) | ||
| 36 | #define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1)) | ||
| 37 | #define BRIDGE_INT_TIMER_WD (1 << 3) | ||
| 38 | #define TIMER_WD_EN (1 << 4) | ||
| 39 | #define TIMER_WD_RELOAD_EN (1 << 5) | ||
| 40 | |||
| 41 | static cycle_t orion_clksrc_read(void) | ||
| 42 | { | ||
| 43 | return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE))); | ||
| 44 | } | ||
| 45 | |||
| 46 | static struct clocksource orion_clksrc = { | ||
| 47 | .name = "orion_clocksource", | ||
| 48 | .shift = 20, | ||
| 49 | .rating = 300, | ||
| 50 | .read = orion_clksrc_read, | ||
| 51 | .mask = CLOCKSOURCE_MASK(32), | ||
| 52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static int | ||
| 56 | orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) | ||
| 57 | { | ||
| 58 | unsigned long flags; | ||
| 59 | |||
| 60 | if (delta == 0) | ||
| 61 | return -ETIME; | ||
| 62 | |||
| 63 | local_irq_save(flags); | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Clear and enable timer interrupt bit | ||
| 67 | */ | ||
| 68 | orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 69 | orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Setup new timer value | ||
| 73 | */ | ||
| 74 | orion_write(TIMER_VAL(CLOCKEVENT), delta); | ||
| 75 | |||
| 76 | /* | ||
| 77 | * Disable auto reload and kickoff the timer | ||
| 78 | */ | ||
| 79 | orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT)); | ||
| 80 | orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT)); | ||
| 81 | |||
| 82 | local_irq_restore(flags); | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static void | ||
| 88 | orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | ||
| 89 | { | ||
| 90 | unsigned long flags; | ||
| 91 | |||
| 92 | local_irq_save(flags); | ||
| 93 | |||
| 94 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | ||
| 95 | /* | ||
| 96 | * Setup latch cycles in timer and enable reload interrupt. | ||
| 97 | */ | ||
| 98 | orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH); | ||
| 99 | orion_write(TIMER_VAL(CLOCKEVENT), LATCH); | ||
| 100 | orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 101 | orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | | ||
| 102 | TIMER_EN(CLOCKEVENT)); | ||
| 103 | } else { | ||
| 104 | /* | ||
| 105 | * Disable timer and interrupt | ||
| 106 | */ | ||
| 107 | orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 108 | orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 109 | orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | | ||
| 110 | TIMER_EN(CLOCKEVENT)); | ||
| 111 | } | ||
| 112 | |||
| 113 | local_irq_restore(flags); | ||
| 114 | } | ||
| 115 | |||
| 116 | static struct clock_event_device orion_clkevt = { | ||
| 117 | .name = "orion_tick", | ||
| 118 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 119 | .shift = 32, | ||
| 120 | .rating = 300, | ||
| 121 | .cpumask = CPU_MASK_CPU0, | ||
| 122 | .set_next_event = orion_clkevt_next_event, | ||
| 123 | .set_mode = orion_clkevt_mode, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) | ||
| 127 | { | ||
| 128 | /* | ||
| 129 | * Clear cause bit and do event | ||
| 130 | */ | ||
| 131 | orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 132 | orion_clkevt.event_handler(&orion_clkevt); | ||
| 133 | return IRQ_HANDLED; | ||
| 134 | } | ||
| 135 | |||
| 136 | static struct irqaction orion_timer_irq = { | ||
| 137 | .name = "orion_tick", | ||
| 138 | .flags = IRQF_DISABLED | IRQF_TIMER, | ||
| 139 | .handler = orion_timer_interrupt | ||
| 140 | }; | ||
| 141 | |||
| 142 | static void orion_timer_init(void) | ||
| 143 | { | ||
| 144 | /* | ||
| 145 | * Setup clocksource free running timer (no interrupt on reload) | ||
| 146 | */ | ||
| 147 | orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff); | ||
| 148 | orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff); | ||
| 149 | orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE)); | ||
| 150 | orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) | | ||
| 151 | TIMER_EN(CLOCKSOURCE)); | ||
| 152 | |||
| 153 | /* | ||
| 154 | * Register clocksource | ||
| 155 | */ | ||
| 156 | orion_clksrc.mult = | ||
| 157 | clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift); | ||
| 158 | |||
| 159 | clocksource_register(&orion_clksrc); | ||
| 160 | |||
| 161 | /* | ||
| 162 | * Connect and enable tick handler | ||
| 163 | */ | ||
| 164 | setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq); | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Register clockevent | ||
| 168 | */ | ||
| 169 | orion_clkevt.mult = | ||
| 170 | div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift); | ||
| 171 | orion_clkevt.max_delta_ns = | ||
| 172 | clockevent_delta2ns(0xfffffffe, &orion_clkevt); | ||
| 173 | orion_clkevt.min_delta_ns = | ||
| 174 | clockevent_delta2ns(1, &orion_clkevt); | ||
| 175 | |||
| 176 | clockevents_register_device(&orion_clkevt); | ||
| 177 | } | ||
| 178 | |||
| 179 | struct sys_timer orion_timer = { | ||
| 180 | .init = orion_timer_init, | ||
| 181 | }; | ||
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig index 1dcbb6ac5a30..93debf336155 100644 --- a/arch/arm/mach-orion/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | if ARCH_ORION | 1 | if ARCH_ORION5X |
| 2 | 2 | ||
| 3 | menu "Orion Implementations" | 3 | menu "Orion Implementations" |
| 4 | 4 | ||
| @@ -36,6 +36,14 @@ config MACH_TS209 | |||
| 36 | Say 'Y' here if you want your kernel to support the | 36 | Say 'Y' here if you want your kernel to support the |
| 37 | QNAP TS-109/TS-209 platform. | 37 | QNAP TS-109/TS-209 platform. |
| 38 | 38 | ||
| 39 | config MACH_LINKSTATION_PRO | ||
| 40 | bool "Buffalo Linkstation Pro/Live" | ||
| 41 | select I2C_BOARDINFO | ||
| 42 | help | ||
| 43 | Say 'Y' here if you want your kernel to support the | ||
| 44 | Buffalo Linkstation Pro/Live platform. Both v1 and | ||
| 45 | v2 devices are supported. | ||
| 46 | |||
| 39 | endmenu | 47 | endmenu |
| 40 | 48 | ||
| 41 | endif | 49 | endif |
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile index f91d937a73e8..9301bf55910b 100644 --- a/arch/arm/mach-orion/Makefile +++ b/arch/arm/mach-orion5x/Makefile | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o | 1 | obj-y += common.o addr-map.o pci.o gpio.o irq.o |
| 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o | 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o |
| 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o | 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o |
| 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o | 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o |
| 5 | obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o | ||
| 5 | obj-$(CONFIG_MACH_DNS323) += dns323-setup.o | 6 | obj-$(CONFIG_MACH_DNS323) += dns323-setup.o |
| 6 | obj-$(CONFIG_MACH_TS209) += ts209-setup.o | 7 | obj-$(CONFIG_MACH_TS209) += ts209-setup.o |
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot index 67039c3e0c48..67039c3e0c48 100644 --- a/arch/arm/mach-orion/Makefile.boot +++ b/arch/arm/mach-orion5x/Makefile.boot | |||
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c new file mode 100644 index 000000000000..6b179371e0a2 --- /dev/null +++ b/arch/arm/mach-orion5x/addr-map.c | |||
| @@ -0,0 +1,240 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Orion 5x SoCs | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/mbus.h> | ||
| 16 | #include <asm/hardware.h> | ||
| 17 | #include <asm/io.h> | ||
| 18 | #include "common.h" | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The Orion has fully programable address map. There's a separate address | ||
| 22 | * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, | ||
| 23 | * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own | ||
| 24 | * address decode windows that allow it to access any of the Orion resources. | ||
| 25 | * | ||
| 26 | * CPU address decoding -- | ||
| 27 | * Linux assumes that it is the boot loader that already setup the access to | ||
| 28 | * DDR and internal registers. | ||
| 29 | * Setup access to PCI and PCI-E IO/MEM space is issued by this file. | ||
| 30 | * Setup access to various devices located on the device bus interface (e.g. | ||
| 31 | * flashes, RTC, etc) should be issued by machine-setup.c according to | ||
| 32 | * specific board population (by using orion5x_setup_*_win()). | ||
| 33 | * | ||
| 34 | * Non-CPU Masters address decoding -- | ||
| 35 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | ||
| 36 | * banks only (the typical use case). | ||
| 37 | * Setup access for each master to DDR is issued by common.c. | ||
| 38 | * | ||
| 39 | * Note: although orion_setbits() and orion_clrbits() are not atomic | ||
| 40 | * no locking is necessary here since code in this file is only called | ||
| 41 | * at boot time when there is no concurrency issues. | ||
| 42 | */ | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Generic Address Decode Windows bit settings | ||
| 46 | */ | ||
| 47 | #define TARGET_DDR 0 | ||
| 48 | #define TARGET_DEV_BUS 1 | ||
| 49 | #define TARGET_PCI 3 | ||
| 50 | #define TARGET_PCIE 4 | ||
| 51 | #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ | ||
| 52 | ((n) == 1) ? 0xd : \ | ||
| 53 | ((n) == 2) ? 0xb : \ | ||
| 54 | ((n) == 3) ? 0x7 : 0xf) | ||
| 55 | #define ATTR_PCIE_MEM 0x59 | ||
| 56 | #define ATTR_PCIE_IO 0x51 | ||
| 57 | #define ATTR_PCIE_WA 0x79 | ||
| 58 | #define ATTR_PCI_MEM 0x59 | ||
| 59 | #define ATTR_PCI_IO 0x51 | ||
| 60 | #define ATTR_DEV_CS0 0x1e | ||
| 61 | #define ATTR_DEV_CS1 0x1d | ||
| 62 | #define ATTR_DEV_CS2 0x1b | ||
| 63 | #define ATTR_DEV_BOOT 0xf | ||
| 64 | #define WIN_EN 1 | ||
| 65 | |||
| 66 | /* | ||
| 67 | * Helpers to get DDR bank info | ||
| 68 | */ | ||
| 69 | #define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) | ||
| 70 | #define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) | ||
| 71 | #define DDR_MAX_CS 4 | ||
| 72 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) | ||
| 73 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) | ||
| 74 | #define DDR_BANK_EN 1 | ||
| 75 | |||
| 76 | /* | ||
| 77 | * CPU Address Decode Windows registers | ||
| 78 | */ | ||
| 79 | #define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) | ||
| 80 | #define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) | ||
| 81 | #define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) | ||
| 82 | #define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) | ||
| 83 | |||
| 84 | /* | ||
| 85 | * Gigabit Ethernet Address Decode Windows registers | ||
| 86 | */ | ||
| 87 | #define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) | ||
| 88 | #define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) | ||
| 89 | #define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) | ||
| 90 | #define ETH_WIN_EN ORION5X_ETH_REG(0x290) | ||
| 91 | #define ETH_WIN_PROT ORION5X_ETH_REG(0x294) | ||
| 92 | #define ETH_MAX_WIN 6 | ||
| 93 | #define ETH_MAX_REMAP_WIN 4 | ||
| 94 | |||
| 95 | |||
| 96 | struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
| 97 | |||
| 98 | static int __init orion5x_cpu_win_can_remap(int win) | ||
| 99 | { | ||
| 100 | u32 dev, rev; | ||
| 101 | |||
| 102 | orion5x_pcie_id(&dev, &rev); | ||
| 103 | if ((dev == MV88F5281_DEV_ID && win < 4) | ||
| 104 | || (dev == MV88F5182_DEV_ID && win < 2) | ||
| 105 | || (dev == MV88F5181_DEV_ID && win < 2)) | ||
| 106 | return 1; | ||
| 107 | |||
| 108 | return 0; | ||
| 109 | } | ||
| 110 | |||
| 111 | static void __init setup_cpu_win(int win, u32 base, u32 size, | ||
| 112 | u8 target, u8 attr, int remap) | ||
| 113 | { | ||
| 114 | orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); | ||
| 115 | orion5x_write(CPU_WIN_CTRL(win), | ||
| 116 | ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); | ||
| 117 | |||
| 118 | if (orion5x_cpu_win_can_remap(win)) { | ||
| 119 | if (remap < 0) | ||
| 120 | remap = base; | ||
| 121 | |||
| 122 | orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | ||
| 123 | orion5x_write(CPU_WIN_REMAP_HI(win), 0); | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | void __init orion5x_setup_cpu_mbus_bridge(void) | ||
| 128 | { | ||
| 129 | int i; | ||
| 130 | int cs; | ||
| 131 | |||
| 132 | /* | ||
| 133 | * First, disable and clear windows. | ||
| 134 | */ | ||
| 135 | for (i = 0; i < 8; i++) { | ||
| 136 | orion5x_write(CPU_WIN_BASE(i), 0); | ||
| 137 | orion5x_write(CPU_WIN_CTRL(i), 0); | ||
| 138 | if (orion5x_cpu_win_can_remap(i)) { | ||
| 139 | orion5x_write(CPU_WIN_REMAP_LO(i), 0); | ||
| 140 | orion5x_write(CPU_WIN_REMAP_HI(i), 0); | ||
| 141 | } | ||
| 142 | } | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Setup windows for PCI+PCIe IO+MEM space. | ||
| 146 | */ | ||
| 147 | setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, | ||
| 148 | TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); | ||
| 149 | setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, | ||
| 150 | TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); | ||
| 151 | setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, | ||
| 152 | TARGET_PCIE, ATTR_PCIE_MEM, -1); | ||
| 153 | setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, | ||
| 154 | TARGET_PCI, ATTR_PCI_MEM, -1); | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Setup MBUS dram target info. | ||
| 158 | */ | ||
| 159 | orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 160 | |||
| 161 | for (i = 0, cs = 0; i < 4; i++) { | ||
| 162 | u32 base = readl(DDR_BASE_CS(i)); | ||
| 163 | u32 size = readl(DDR_SIZE_CS(i)); | ||
| 164 | |||
| 165 | /* | ||
| 166 | * Chip select enabled? | ||
| 167 | */ | ||
| 168 | if (size & 1) { | ||
| 169 | struct mbus_dram_window *w; | ||
| 170 | |||
| 171 | w = &orion5x_mbus_dram_info.cs[cs++]; | ||
| 172 | w->cs_index = i; | ||
| 173 | w->mbus_attr = 0xf & ~(1 << i); | ||
| 174 | w->base = base & 0xff000000; | ||
| 175 | w->size = (size | 0x00ffffff) + 1; | ||
| 176 | } | ||
| 177 | } | ||
| 178 | orion5x_mbus_dram_info.num_cs = cs; | ||
| 179 | } | ||
| 180 | |||
| 181 | void __init orion5x_setup_dev_boot_win(u32 base, u32 size) | ||
| 182 | { | ||
| 183 | setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); | ||
| 184 | } | ||
| 185 | |||
| 186 | void __init orion5x_setup_dev0_win(u32 base, u32 size) | ||
| 187 | { | ||
| 188 | setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); | ||
| 189 | } | ||
| 190 | |||
| 191 | void __init orion5x_setup_dev1_win(u32 base, u32 size) | ||
| 192 | { | ||
| 193 | setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); | ||
| 194 | } | ||
| 195 | |||
| 196 | void __init orion5x_setup_dev2_win(u32 base, u32 size) | ||
| 197 | { | ||
| 198 | setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); | ||
| 199 | } | ||
| 200 | |||
| 201 | void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) | ||
| 202 | { | ||
| 203 | setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); | ||
| 204 | } | ||
| 205 | |||
| 206 | void __init orion5x_setup_eth_wins(void) | ||
| 207 | { | ||
| 208 | int i; | ||
| 209 | |||
| 210 | /* | ||
| 211 | * First, disable and clear windows | ||
| 212 | */ | ||
| 213 | for (i = 0; i < ETH_MAX_WIN; i++) { | ||
| 214 | orion5x_write(ETH_WIN_BASE(i), 0); | ||
| 215 | orion5x_write(ETH_WIN_SIZE(i), 0); | ||
| 216 | orion5x_setbits(ETH_WIN_EN, 1 << i); | ||
| 217 | orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 218 | if (i < ETH_MAX_REMAP_WIN) | ||
| 219 | orion5x_write(ETH_WIN_REMAP(i), 0); | ||
| 220 | } | ||
| 221 | |||
| 222 | /* | ||
| 223 | * Setup windows for DDR banks. | ||
| 224 | */ | ||
| 225 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 226 | u32 base, size; | ||
| 227 | size = orion5x_read(DDR_SIZE_CS(i)); | ||
| 228 | base = orion5x_read(DDR_BASE_CS(i)); | ||
| 229 | if (size & DDR_BANK_EN) { | ||
| 230 | base = DDR_REG_TO_BASE(base); | ||
| 231 | size = DDR_REG_TO_SIZE(size); | ||
| 232 | orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); | ||
| 233 | orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | | ||
| 234 | (ATTR_DDR_CS(i) << 8) | | ||
| 235 | TARGET_DDR); | ||
| 236 | orion5x_clrbits(ETH_WIN_EN, 1 << i); | ||
| 237 | orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 238 | } | ||
| 239 | } | ||
| 240 | } | ||
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c index bbc2b4ec932c..439c7784af02 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/common.c | 2 | * arch/arm/mach-orion5x/common.c |
| 3 | * | 3 | * |
| 4 | * Core functions for Marvell Orion System On Chip | 4 | * Core functions for Marvell Orion 5x SoCs |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -14,64 +14,71 @@ | |||
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/serial_8250.h> | 16 | #include <linux/serial_8250.h> |
| 17 | #include <linux/mbus.h> | ||
| 17 | #include <linux/mv643xx_eth.h> | 18 | #include <linux/mv643xx_eth.h> |
| 18 | #include <linux/mv643xx_i2c.h> | 19 | #include <linux/mv643xx_i2c.h> |
| 20 | #include <linux/ata_platform.h> | ||
| 19 | #include <asm/page.h> | 21 | #include <asm/page.h> |
| 20 | #include <asm/setup.h> | 22 | #include <asm/setup.h> |
| 21 | #include <asm/timex.h> | 23 | #include <asm/timex.h> |
| 22 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| 26 | #include <asm/mach/time.h> | ||
| 24 | #include <asm/arch/hardware.h> | 27 | #include <asm/arch/hardware.h> |
| 28 | #include <asm/arch/orion5x.h> | ||
| 29 | #include <asm/plat-orion/ehci-orion.h> | ||
| 30 | #include <asm/plat-orion/orion_nand.h> | ||
| 31 | #include <asm/plat-orion/time.h> | ||
| 25 | #include "common.h" | 32 | #include "common.h" |
| 26 | 33 | ||
| 27 | /***************************************************************************** | 34 | /***************************************************************************** |
| 28 | * I/O Address Mapping | 35 | * I/O Address Mapping |
| 29 | ****************************************************************************/ | 36 | ****************************************************************************/ |
| 30 | static struct map_desc orion_io_desc[] __initdata = { | 37 | static struct map_desc orion5x_io_desc[] __initdata = { |
| 31 | { | 38 | { |
| 32 | .virtual = ORION_REGS_VIRT_BASE, | 39 | .virtual = ORION5X_REGS_VIRT_BASE, |
| 33 | .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), | 40 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), |
| 34 | .length = ORION_REGS_SIZE, | 41 | .length = ORION5X_REGS_SIZE, |
| 35 | .type = MT_DEVICE | 42 | .type = MT_DEVICE |
| 36 | }, | 43 | }, |
| 37 | { | 44 | { |
| 38 | .virtual = ORION_PCIE_IO_VIRT_BASE, | 45 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
| 39 | .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), | 46 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), |
| 40 | .length = ORION_PCIE_IO_SIZE, | 47 | .length = ORION5X_PCIE_IO_SIZE, |
| 41 | .type = MT_DEVICE | 48 | .type = MT_DEVICE |
| 42 | }, | 49 | }, |
| 43 | { | 50 | { |
| 44 | .virtual = ORION_PCI_IO_VIRT_BASE, | 51 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
| 45 | .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), | 52 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), |
| 46 | .length = ORION_PCI_IO_SIZE, | 53 | .length = ORION5X_PCI_IO_SIZE, |
| 47 | .type = MT_DEVICE | 54 | .type = MT_DEVICE |
| 48 | }, | 55 | }, |
| 49 | { | 56 | { |
| 50 | .virtual = ORION_PCIE_WA_VIRT_BASE, | 57 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
| 51 | .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), | 58 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), |
| 52 | .length = ORION_PCIE_WA_SIZE, | 59 | .length = ORION5X_PCIE_WA_SIZE, |
| 53 | .type = MT_DEVICE | 60 | .type = MT_DEVICE |
| 54 | }, | 61 | }, |
| 55 | }; | 62 | }; |
| 56 | 63 | ||
| 57 | void __init orion_map_io(void) | 64 | void __init orion5x_map_io(void) |
| 58 | { | 65 | { |
| 59 | iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); | 66 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
| 60 | } | 67 | } |
| 61 | 68 | ||
| 62 | /***************************************************************************** | 69 | /***************************************************************************** |
| 63 | * UART | 70 | * UART |
| 64 | ****************************************************************************/ | 71 | ****************************************************************************/ |
| 65 | 72 | ||
| 66 | static struct resource orion_uart_resources[] = { | 73 | static struct resource orion5x_uart_resources[] = { |
| 67 | { | 74 | { |
| 68 | .start = UART0_PHYS_BASE, | 75 | .start = UART0_PHYS_BASE, |
| 69 | .end = UART0_PHYS_BASE + 0xff, | 76 | .end = UART0_PHYS_BASE + 0xff, |
| 70 | .flags = IORESOURCE_MEM, | 77 | .flags = IORESOURCE_MEM, |
| 71 | }, | 78 | }, |
| 72 | { | 79 | { |
| 73 | .start = IRQ_ORION_UART0, | 80 | .start = IRQ_ORION5X_UART0, |
| 74 | .end = IRQ_ORION_UART0, | 81 | .end = IRQ_ORION5X_UART0, |
| 75 | .flags = IORESOURCE_IRQ, | 82 | .flags = IORESOURCE_IRQ, |
| 76 | }, | 83 | }, |
| 77 | { | 84 | { |
| @@ -80,96 +87,102 @@ static struct resource orion_uart_resources[] = { | |||
| 80 | .flags = IORESOURCE_MEM, | 87 | .flags = IORESOURCE_MEM, |
| 81 | }, | 88 | }, |
| 82 | { | 89 | { |
| 83 | .start = IRQ_ORION_UART1, | 90 | .start = IRQ_ORION5X_UART1, |
| 84 | .end = IRQ_ORION_UART1, | 91 | .end = IRQ_ORION5X_UART1, |
| 85 | .flags = IORESOURCE_IRQ, | 92 | .flags = IORESOURCE_IRQ, |
| 86 | }, | 93 | }, |
| 87 | }; | 94 | }; |
| 88 | 95 | ||
| 89 | static struct plat_serial8250_port orion_uart_data[] = { | 96 | static struct plat_serial8250_port orion5x_uart_data[] = { |
| 90 | { | 97 | { |
| 91 | .mapbase = UART0_PHYS_BASE, | 98 | .mapbase = UART0_PHYS_BASE, |
| 92 | .membase = (char *)UART0_VIRT_BASE, | 99 | .membase = (char *)UART0_VIRT_BASE, |
| 93 | .irq = IRQ_ORION_UART0, | 100 | .irq = IRQ_ORION5X_UART0, |
| 94 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | 101 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
| 95 | .iotype = UPIO_MEM, | 102 | .iotype = UPIO_MEM, |
| 96 | .regshift = 2, | 103 | .regshift = 2, |
| 97 | .uartclk = ORION_TCLK, | 104 | .uartclk = ORION5X_TCLK, |
| 98 | }, | 105 | }, |
| 99 | { | 106 | { |
| 100 | .mapbase = UART1_PHYS_BASE, | 107 | .mapbase = UART1_PHYS_BASE, |
| 101 | .membase = (char *)UART1_VIRT_BASE, | 108 | .membase = (char *)UART1_VIRT_BASE, |
| 102 | .irq = IRQ_ORION_UART1, | 109 | .irq = IRQ_ORION5X_UART1, |
| 103 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | 110 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
| 104 | .iotype = UPIO_MEM, | 111 | .iotype = UPIO_MEM, |
| 105 | .regshift = 2, | 112 | .regshift = 2, |
| 106 | .uartclk = ORION_TCLK, | 113 | .uartclk = ORION5X_TCLK, |
| 107 | }, | 114 | }, |
| 108 | { }, | 115 | { }, |
| 109 | }; | 116 | }; |
| 110 | 117 | ||
| 111 | static struct platform_device orion_uart = { | 118 | static struct platform_device orion5x_uart = { |
| 112 | .name = "serial8250", | 119 | .name = "serial8250", |
| 113 | .id = PLAT8250_DEV_PLATFORM, | 120 | .id = PLAT8250_DEV_PLATFORM, |
| 114 | .dev = { | 121 | .dev = { |
| 115 | .platform_data = orion_uart_data, | 122 | .platform_data = orion5x_uart_data, |
| 116 | }, | 123 | }, |
| 117 | .resource = orion_uart_resources, | 124 | .resource = orion5x_uart_resources, |
| 118 | .num_resources = ARRAY_SIZE(orion_uart_resources), | 125 | .num_resources = ARRAY_SIZE(orion5x_uart_resources), |
| 119 | }; | 126 | }; |
| 120 | 127 | ||
| 121 | /******************************************************************************* | 128 | /******************************************************************************* |
| 122 | * USB Controller - 2 interfaces | 129 | * USB Controller - 2 interfaces |
| 123 | ******************************************************************************/ | 130 | ******************************************************************************/ |
| 124 | 131 | ||
| 125 | static struct resource orion_ehci0_resources[] = { | 132 | static struct resource orion5x_ehci0_resources[] = { |
| 126 | { | 133 | { |
| 127 | .start = ORION_USB0_PHYS_BASE, | 134 | .start = ORION5X_USB0_PHYS_BASE, |
| 128 | .end = ORION_USB0_PHYS_BASE + SZ_4K, | 135 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K, |
| 129 | .flags = IORESOURCE_MEM, | 136 | .flags = IORESOURCE_MEM, |
| 130 | }, | 137 | }, |
| 131 | { | 138 | { |
| 132 | .start = IRQ_ORION_USB0_CTRL, | 139 | .start = IRQ_ORION5X_USB0_CTRL, |
| 133 | .end = IRQ_ORION_USB0_CTRL, | 140 | .end = IRQ_ORION5X_USB0_CTRL, |
| 134 | .flags = IORESOURCE_IRQ, | 141 | .flags = IORESOURCE_IRQ, |
| 135 | }, | 142 | }, |
| 136 | }; | 143 | }; |
| 137 | 144 | ||
| 138 | static struct resource orion_ehci1_resources[] = { | 145 | static struct resource orion5x_ehci1_resources[] = { |
| 139 | { | 146 | { |
| 140 | .start = ORION_USB1_PHYS_BASE, | 147 | .start = ORION5X_USB1_PHYS_BASE, |
| 141 | .end = ORION_USB1_PHYS_BASE + SZ_4K, | 148 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K, |
| 142 | .flags = IORESOURCE_MEM, | 149 | .flags = IORESOURCE_MEM, |
| 143 | }, | 150 | }, |
| 144 | { | 151 | { |
| 145 | .start = IRQ_ORION_USB1_CTRL, | 152 | .start = IRQ_ORION5X_USB1_CTRL, |
| 146 | .end = IRQ_ORION_USB1_CTRL, | 153 | .end = IRQ_ORION5X_USB1_CTRL, |
| 147 | .flags = IORESOURCE_IRQ, | 154 | .flags = IORESOURCE_IRQ, |
| 148 | }, | 155 | }, |
| 149 | }; | 156 | }; |
| 150 | 157 | ||
| 158 | static struct orion_ehci_data orion5x_ehci_data = { | ||
| 159 | .dram = &orion5x_mbus_dram_info, | ||
| 160 | }; | ||
| 161 | |||
| 151 | static u64 ehci_dmamask = 0xffffffffUL; | 162 | static u64 ehci_dmamask = 0xffffffffUL; |
| 152 | 163 | ||
| 153 | static struct platform_device orion_ehci0 = { | 164 | static struct platform_device orion5x_ehci0 = { |
| 154 | .name = "orion-ehci", | 165 | .name = "orion-ehci", |
| 155 | .id = 0, | 166 | .id = 0, |
| 156 | .dev = { | 167 | .dev = { |
| 157 | .dma_mask = &ehci_dmamask, | 168 | .dma_mask = &ehci_dmamask, |
| 158 | .coherent_dma_mask = 0xffffffff, | 169 | .coherent_dma_mask = 0xffffffff, |
| 170 | .platform_data = &orion5x_ehci_data, | ||
| 159 | }, | 171 | }, |
| 160 | .resource = orion_ehci0_resources, | 172 | .resource = orion5x_ehci0_resources, |
| 161 | .num_resources = ARRAY_SIZE(orion_ehci0_resources), | 173 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), |
| 162 | }; | 174 | }; |
| 163 | 175 | ||
| 164 | static struct platform_device orion_ehci1 = { | 176 | static struct platform_device orion5x_ehci1 = { |
| 165 | .name = "orion-ehci", | 177 | .name = "orion-ehci", |
| 166 | .id = 1, | 178 | .id = 1, |
| 167 | .dev = { | 179 | .dev = { |
| 168 | .dma_mask = &ehci_dmamask, | 180 | .dma_mask = &ehci_dmamask, |
| 169 | .coherent_dma_mask = 0xffffffff, | 181 | .coherent_dma_mask = 0xffffffff, |
| 182 | .platform_data = &orion5x_ehci_data, | ||
| 170 | }, | 183 | }, |
| 171 | .resource = orion_ehci1_resources, | 184 | .resource = orion5x_ehci1_resources, |
| 172 | .num_resources = ARRAY_SIZE(orion_ehci1_resources), | 185 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), |
| 173 | }; | 186 | }; |
| 174 | 187 | ||
| 175 | /***************************************************************************** | 188 | /***************************************************************************** |
| @@ -177,42 +190,42 @@ static struct platform_device orion_ehci1 = { | |||
| 177 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) | 190 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) |
| 178 | ****************************************************************************/ | 191 | ****************************************************************************/ |
| 179 | 192 | ||
| 180 | static struct resource orion_eth_shared_resources[] = { | 193 | static struct resource orion5x_eth_shared_resources[] = { |
| 181 | { | 194 | { |
| 182 | .start = ORION_ETH_PHYS_BASE + 0x2000, | 195 | .start = ORION5X_ETH_PHYS_BASE + 0x2000, |
| 183 | .end = ORION_ETH_PHYS_BASE + 0x3fff, | 196 | .end = ORION5X_ETH_PHYS_BASE + 0x3fff, |
| 184 | .flags = IORESOURCE_MEM, | 197 | .flags = IORESOURCE_MEM, |
| 185 | }, | 198 | }, |
| 186 | }; | 199 | }; |
| 187 | 200 | ||
| 188 | static struct platform_device orion_eth_shared = { | 201 | static struct platform_device orion5x_eth_shared = { |
| 189 | .name = MV643XX_ETH_SHARED_NAME, | 202 | .name = MV643XX_ETH_SHARED_NAME, |
| 190 | .id = 0, | 203 | .id = 0, |
| 191 | .num_resources = 1, | 204 | .num_resources = 1, |
| 192 | .resource = orion_eth_shared_resources, | 205 | .resource = orion5x_eth_shared_resources, |
| 193 | }; | 206 | }; |
| 194 | 207 | ||
| 195 | static struct resource orion_eth_resources[] = { | 208 | static struct resource orion5x_eth_resources[] = { |
| 196 | { | 209 | { |
| 197 | .name = "eth irq", | 210 | .name = "eth irq", |
| 198 | .start = IRQ_ORION_ETH_SUM, | 211 | .start = IRQ_ORION5X_ETH_SUM, |
| 199 | .end = IRQ_ORION_ETH_SUM, | 212 | .end = IRQ_ORION5X_ETH_SUM, |
| 200 | .flags = IORESOURCE_IRQ, | 213 | .flags = IORESOURCE_IRQ, |
| 201 | } | 214 | } |
| 202 | }; | 215 | }; |
| 203 | 216 | ||
| 204 | static struct platform_device orion_eth = { | 217 | static struct platform_device orion5x_eth = { |
| 205 | .name = MV643XX_ETH_NAME, | 218 | .name = MV643XX_ETH_NAME, |
| 206 | .id = 0, | 219 | .id = 0, |
| 207 | .num_resources = 1, | 220 | .num_resources = 1, |
| 208 | .resource = orion_eth_resources, | 221 | .resource = orion5x_eth_resources, |
| 209 | }; | 222 | }; |
| 210 | 223 | ||
| 211 | void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) | 224 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
| 212 | { | 225 | { |
| 213 | orion_eth.dev.platform_data = eth_data; | 226 | orion5x_eth.dev.platform_data = eth_data; |
| 214 | platform_device_register(&orion_eth_shared); | 227 | platform_device_register(&orion5x_eth_shared); |
| 215 | platform_device_register(&orion_eth); | 228 | platform_device_register(&orion5x_eth); |
| 216 | } | 229 | } |
| 217 | 230 | ||
| 218 | /***************************************************************************** | 231 | /***************************************************************************** |
| @@ -220,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 220 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) | 233 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) |
| 221 | ****************************************************************************/ | 234 | ****************************************************************************/ |
| 222 | 235 | ||
| 223 | static struct mv64xxx_i2c_pdata orion_i2c_pdata = { | 236 | static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { |
| 224 | .freq_m = 8, /* assumes 166 MHz TCLK */ | 237 | .freq_m = 8, /* assumes 166 MHz TCLK */ |
| 225 | .freq_n = 3, | 238 | .freq_n = 3, |
| 226 | .timeout = 1000, /* Default timeout of 1 second */ | 239 | .timeout = 1000, /* Default timeout of 1 second */ |
| 227 | }; | 240 | }; |
| 228 | 241 | ||
| 229 | static struct resource orion_i2c_resources[] = { | 242 | static struct resource orion5x_i2c_resources[] = { |
| 230 | { | 243 | { |
| 231 | .name = "i2c base", | 244 | .name = "i2c base", |
| 232 | .start = I2C_PHYS_BASE, | 245 | .start = I2C_PHYS_BASE, |
| @@ -235,66 +248,80 @@ static struct resource orion_i2c_resources[] = { | |||
| 235 | }, | 248 | }, |
| 236 | { | 249 | { |
| 237 | .name = "i2c irq", | 250 | .name = "i2c irq", |
| 238 | .start = IRQ_ORION_I2C, | 251 | .start = IRQ_ORION5X_I2C, |
| 239 | .end = IRQ_ORION_I2C, | 252 | .end = IRQ_ORION5X_I2C, |
| 240 | .flags = IORESOURCE_IRQ, | 253 | .flags = IORESOURCE_IRQ, |
| 241 | }, | 254 | }, |
| 242 | }; | 255 | }; |
| 243 | 256 | ||
| 244 | static struct platform_device orion_i2c = { | 257 | static struct platform_device orion5x_i2c = { |
| 245 | .name = MV64XXX_I2C_CTLR_NAME, | 258 | .name = MV64XXX_I2C_CTLR_NAME, |
| 246 | .id = 0, | 259 | .id = 0, |
| 247 | .num_resources = ARRAY_SIZE(orion_i2c_resources), | 260 | .num_resources = ARRAY_SIZE(orion5x_i2c_resources), |
| 248 | .resource = orion_i2c_resources, | 261 | .resource = orion5x_i2c_resources, |
| 249 | .dev = { | 262 | .dev = { |
| 250 | .platform_data = &orion_i2c_pdata, | 263 | .platform_data = &orion5x_i2c_pdata, |
| 251 | }, | 264 | }, |
| 252 | }; | 265 | }; |
| 253 | 266 | ||
| 254 | /***************************************************************************** | 267 | /***************************************************************************** |
| 255 | * Sata port | 268 | * Sata port |
| 256 | ****************************************************************************/ | 269 | ****************************************************************************/ |
| 257 | static struct resource orion_sata_resources[] = { | 270 | static struct resource orion5x_sata_resources[] = { |
| 258 | { | 271 | { |
| 259 | .name = "sata base", | 272 | .name = "sata base", |
| 260 | .start = ORION_SATA_PHYS_BASE, | 273 | .start = ORION5X_SATA_PHYS_BASE, |
| 261 | .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, | 274 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, |
| 262 | .flags = IORESOURCE_MEM, | 275 | .flags = IORESOURCE_MEM, |
| 263 | }, | 276 | }, |
| 264 | { | 277 | { |
| 265 | .name = "sata irq", | 278 | .name = "sata irq", |
| 266 | .start = IRQ_ORION_SATA, | 279 | .start = IRQ_ORION5X_SATA, |
| 267 | .end = IRQ_ORION_SATA, | 280 | .end = IRQ_ORION5X_SATA, |
| 268 | .flags = IORESOURCE_IRQ, | 281 | .flags = IORESOURCE_IRQ, |
| 269 | }, | 282 | }, |
| 270 | }; | 283 | }; |
| 271 | 284 | ||
| 272 | static struct platform_device orion_sata = { | 285 | static struct platform_device orion5x_sata = { |
| 273 | .name = "sata_mv", | 286 | .name = "sata_mv", |
| 274 | .id = 0, | 287 | .id = 0, |
| 275 | .dev = { | 288 | .dev = { |
| 276 | .coherent_dma_mask = 0xffffffff, | 289 | .coherent_dma_mask = 0xffffffff, |
| 277 | }, | 290 | }, |
| 278 | .num_resources = ARRAY_SIZE(orion_sata_resources), | 291 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
| 279 | .resource = orion_sata_resources, | 292 | .resource = orion5x_sata_resources, |
| 280 | }; | 293 | }; |
| 281 | 294 | ||
| 282 | void __init orion_sata_init(struct mv_sata_platform_data *sata_data) | 295 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
| 283 | { | 296 | { |
| 284 | orion_sata.dev.platform_data = sata_data; | 297 | sata_data->dram = &orion5x_mbus_dram_info; |
| 285 | platform_device_register(&orion_sata); | 298 | orion5x_sata.dev.platform_data = sata_data; |
| 299 | platform_device_register(&orion5x_sata); | ||
| 286 | } | 300 | } |
| 287 | 301 | ||
| 288 | /***************************************************************************** | 302 | /***************************************************************************** |
| 303 | * Time handling | ||
| 304 | ****************************************************************************/ | ||
| 305 | |||
| 306 | static void orion5x_timer_init(void) | ||
| 307 | { | ||
| 308 | orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); | ||
| 309 | } | ||
| 310 | |||
| 311 | struct sys_timer orion5x_timer = { | ||
| 312 | .init = orion5x_timer_init, | ||
| 313 | }; | ||
| 314 | |||
| 315 | /***************************************************************************** | ||
| 289 | * General | 316 | * General |
| 290 | ****************************************************************************/ | 317 | ****************************************************************************/ |
| 291 | 318 | ||
| 292 | /* | 319 | /* |
| 293 | * Identify device ID and rev from PCIE configuration header space '0'. | 320 | * Identify device ID and rev from PCIE configuration header space '0'. |
| 294 | */ | 321 | */ |
| 295 | static void orion_id(u32 *dev, u32 *rev, char **dev_name) | 322 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
| 296 | { | 323 | { |
| 297 | orion_pcie_id(dev, rev); | 324 | orion5x_pcie_id(dev, rev); |
| 298 | 325 | ||
| 299 | if (*dev == MV88F5281_DEV_ID) { | 326 | if (*dev == MV88F5281_DEV_ID) { |
| 300 | if (*rev == MV88F5281_REV_D2) { | 327 | if (*rev == MV88F5281_REV_D2) { |
| @@ -321,33 +348,28 @@ static void orion_id(u32 *dev, u32 *rev, char **dev_name) | |||
| 321 | } | 348 | } |
| 322 | } | 349 | } |
| 323 | 350 | ||
| 324 | void __init orion_init(void) | 351 | void __init orion5x_init(void) |
| 325 | { | 352 | { |
| 326 | char *dev_name; | 353 | char *dev_name; |
| 327 | u32 dev, rev; | 354 | u32 dev, rev; |
| 328 | 355 | ||
| 329 | orion_id(&dev, &rev, &dev_name); | 356 | orion5x_id(&dev, &rev, &dev_name); |
| 330 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); | 357 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); |
| 331 | 358 | ||
| 332 | /* | 359 | /* |
| 333 | * Setup Orion address map | 360 | * Setup Orion address map |
| 334 | */ | 361 | */ |
| 335 | orion_setup_cpu_wins(); | 362 | orion5x_setup_cpu_mbus_bridge(); |
| 336 | orion_setup_usb_wins(); | 363 | orion5x_setup_eth_wins(); |
| 337 | orion_setup_eth_wins(); | ||
| 338 | orion_setup_pci_wins(); | ||
| 339 | orion_setup_pcie_wins(); | ||
| 340 | if (dev == MV88F5182_DEV_ID) | ||
| 341 | orion_setup_sata_wins(); | ||
| 342 | 364 | ||
| 343 | /* | 365 | /* |
| 344 | * REgister devices | 366 | * Register devices. |
| 345 | */ | 367 | */ |
| 346 | platform_device_register(&orion_uart); | 368 | platform_device_register(&orion5x_uart); |
| 347 | platform_device_register(&orion_ehci0); | 369 | platform_device_register(&orion5x_ehci0); |
| 348 | if (dev == MV88F5182_DEV_ID) | 370 | if (dev == MV88F5182_DEV_ID) |
| 349 | platform_device_register(&orion_ehci1); | 371 | platform_device_register(&orion5x_ehci1); |
| 350 | platform_device_register(&orion_i2c); | 372 | platform_device_register(&orion5x_i2c); |
| 351 | } | 373 | } |
| 352 | 374 | ||
| 353 | /* | 375 | /* |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h new file mode 100644 index 000000000000..f4c4c9a72a7c --- /dev/null +++ b/arch/arm/mach-orion5x/common.h | |||
| @@ -0,0 +1,72 @@ | |||
| 1 | #ifndef __ARCH_ORION5X_COMMON_H | ||
| 2 | #define __ARCH_ORION5X_COMMON_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Basic Orion init functions used early by machine-setup. | ||
| 6 | */ | ||
| 7 | |||
| 8 | void orion5x_map_io(void); | ||
| 9 | void orion5x_init_irq(void); | ||
| 10 | void orion5x_init(void); | ||
| 11 | extern struct sys_timer orion5x_timer; | ||
| 12 | |||
| 13 | /* | ||
| 14 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
| 15 | * functions to map its interfaces and by the machine-setup to map its on- | ||
| 16 | * board devices. Details in /mach-orion/addr-map.c | ||
| 17 | */ | ||
| 18 | extern struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
| 19 | void orion5x_setup_cpu_mbus_bridge(void); | ||
| 20 | void orion5x_setup_dev_boot_win(u32 base, u32 size); | ||
| 21 | void orion5x_setup_dev0_win(u32 base, u32 size); | ||
| 22 | void orion5x_setup_dev1_win(u32 base, u32 size); | ||
| 23 | void orion5x_setup_dev2_win(u32 base, u32 size); | ||
| 24 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); | ||
| 25 | void orion5x_setup_eth_wins(void); | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Shared code used internally by other Orion core functions. | ||
| 29 | * (/mach-orion/pci.c) | ||
| 30 | */ | ||
| 31 | |||
| 32 | struct pci_sys_data; | ||
| 33 | struct pci_bus; | ||
| 34 | |||
| 35 | void orion5x_pcie_id(u32 *dev, u32 *rev); | ||
| 36 | int orion5x_pcie_local_bus_nr(void); | ||
| 37 | int orion5x_pci_local_bus_nr(void); | ||
| 38 | int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); | ||
| 39 | struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
| 43 | * (/mach-orion/gpio.c). | ||
| 44 | */ | ||
| 45 | |||
| 46 | void orion5x_gpio_set_valid_pins(u32 pins); | ||
| 47 | void gpio_display(void); /* debug */ | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Pull in Orion Ethernet platform_data, used by machine-setup | ||
| 51 | */ | ||
| 52 | |||
| 53 | struct mv643xx_eth_platform_data; | ||
| 54 | |||
| 55 | void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Orion Sata platform_data, used by machine-setup | ||
| 59 | */ | ||
| 60 | |||
| 61 | struct mv_sata_platform_data; | ||
| 62 | |||
| 63 | void orion5x_sata_init(struct mv_sata_platform_data *sata_data); | ||
| 64 | |||
| 65 | struct machine_desc; | ||
| 66 | struct meminfo; | ||
| 67 | struct tag; | ||
| 68 | extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, | ||
| 69 | char **, struct meminfo *); | ||
| 70 | |||
| 71 | |||
| 72 | #endif | ||
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 5ef44e1a2d36..872aed372327 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/db88f5281-setup.c | 2 | * arch/arm/mach-orion5x/db88f5281-setup.c |
| 3 | * | 3 | * |
| 4 | * Marvell Orion-2 Development Board Setup | 4 | * Marvell Orion-2 Development Board Setup |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -24,8 +24,8 @@ | |||
| 24 | #include <asm/gpio.h> | 24 | #include <asm/gpio.h> |
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/pci.h> | 26 | #include <asm/mach/pci.h> |
| 27 | #include <asm/arch/orion.h> | 27 | #include <asm/arch/orion5x.h> |
| 28 | #include <asm/arch/platform.h> | 28 | #include <asm/plat-orion/orion_nand.h> |
| 29 | #include "common.h" | 29 | #include "common.h" |
| 30 | 30 | ||
| 31 | /***************************************************************************** | 31 | /***************************************************************************** |
| @@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 244 | /* | 244 | /* |
| 245 | * PCIE IRQ is connected internally (not GPIO) | 245 | * PCIE IRQ is connected internally (not GPIO) |
| 246 | */ | 246 | */ |
| 247 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 247 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
| 248 | return IRQ_ORION_PCIE0_INT; | 248 | return IRQ_ORION5X_PCIE0_INT; |
| 249 | 249 | ||
| 250 | /* | 250 | /* |
| 251 | * PCI IRQs are connected via GPIOs | 251 | * PCI IRQs are connected via GPIOs |
| @@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = { | |||
| 265 | .nr_controllers = 2, | 265 | .nr_controllers = 2, |
| 266 | .preinit = db88f5281_pci_preinit, | 266 | .preinit = db88f5281_pci_preinit, |
| 267 | .swizzle = pci_std_swizzle, | 267 | .swizzle = pci_std_swizzle, |
| 268 | .setup = orion_pci_sys_setup, | 268 | .setup = orion5x_pci_sys_setup, |
| 269 | .scan = orion_pci_sys_scan_bus, | 269 | .scan = orion5x_pci_sys_scan_bus, |
| 270 | .map_irq = db88f5281_pci_map_irq, | 270 | .map_irq = db88f5281_pci_map_irq, |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| @@ -312,19 +312,16 @@ static void __init db88f5281_init(void) | |||
| 312 | /* | 312 | /* |
| 313 | * Basic Orion setup. Need to be called early. | 313 | * Basic Orion setup. Need to be called early. |
| 314 | */ | 314 | */ |
| 315 | orion_init(); | 315 | orion5x_init(); |
| 316 | 316 | ||
| 317 | /* | 317 | /* |
| 318 | * Setup the CPU address decode windows for our on-board devices | 318 | * Setup the CPU address decode windows for our on-board devices |
| 319 | */ | 319 | */ |
| 320 | orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, | 320 | orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, |
| 321 | DB88F5281_NOR_BOOT_SIZE, -1); | 321 | DB88F5281_NOR_BOOT_SIZE); |
| 322 | orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, | 322 | orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); |
| 323 | DB88F5281_7SEG_SIZE, -1); | 323 | orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); |
| 324 | orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, | 324 | orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); |
| 325 | DB88F5281_NOR_SIZE, -1); | ||
| 326 | orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, | ||
| 327 | DB88F5281_NAND_SIZE, -1); | ||
| 328 | 325 | ||
| 329 | /* | 326 | /* |
| 330 | * Setup Multiplexing Pins: | 327 | * Setup Multiplexing Pins: |
| @@ -340,25 +337,25 @@ static void __init db88f5281_init(void) | |||
| 340 | * MPP18: UART1_CTS MPP19: UART1_RTS | 337 | * MPP18: UART1_CTS MPP19: UART1_RTS |
| 341 | * MPP-DEV: DEV_D[16:31] | 338 | * MPP-DEV: DEV_D[16:31] |
| 342 | */ | 339 | */ |
| 343 | orion_write(MPP_0_7_CTRL, 0x00222203); | 340 | orion5x_write(MPP_0_7_CTRL, 0x00222203); |
| 344 | orion_write(MPP_8_15_CTRL, 0x44000000); | 341 | orion5x_write(MPP_8_15_CTRL, 0x44000000); |
| 345 | orion_write(MPP_16_19_CTRL, 0); | 342 | orion5x_write(MPP_16_19_CTRL, 0); |
| 346 | orion_write(MPP_DEV_CTRL, 0); | 343 | orion5x_write(MPP_DEV_CTRL, 0); |
| 347 | 344 | ||
| 348 | orion_gpio_set_valid_pins(0x00003fc3); | 345 | orion5x_gpio_set_valid_pins(0x00003fc3); |
| 349 | 346 | ||
| 350 | platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); | 347 | platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); |
| 351 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); | 348 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); |
| 352 | orion_eth_init(&db88f5281_eth_data); | 349 | orion5x_eth_init(&db88f5281_eth_data); |
| 353 | } | 350 | } |
| 354 | 351 | ||
| 355 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") | 352 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") |
| 356 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ | 353 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ |
| 357 | .phys_io = ORION_REGS_PHYS_BASE, | 354 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 358 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, | 355 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, |
| 359 | .boot_params = 0x00000100, | 356 | .boot_params = 0x00000100, |
| 360 | .init_machine = db88f5281_init, | 357 | .init_machine = db88f5281_init, |
| 361 | .map_io = orion_map_io, | 358 | .map_io = orion5x_map_io, |
| 362 | .init_irq = orion_init_irq, | 359 | .init_irq = orion5x_init_irq, |
| 363 | .timer = &orion_timer, | 360 | .timer = &orion5x_timer, |
| 364 | MACHINE_END | 361 | MACHINE_END |
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 076e155ad510..d67790ef236e 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/dns323-setup.c | 2 | * arch/arm/mach-orion5x/dns323-setup.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> | 4 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> |
| 5 | * | 5 | * |
| @@ -25,8 +25,7 @@ | |||
| 25 | #include <asm/gpio.h> | 25 | #include <asm/gpio.h> |
| 26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/pci.h> | 27 | #include <asm/mach/pci.h> |
| 28 | #include <asm/arch/orion.h> | 28 | #include <asm/arch/orion5x.h> |
| 29 | #include <asm/arch/platform.h> | ||
| 30 | #include "common.h" | 29 | #include "common.h" |
| 31 | 30 | ||
| 32 | #define DNS323_GPIO_LED_RIGHT_AMBER 1 | 31 | #define DNS323_GPIO_LED_RIGHT_AMBER 1 |
| @@ -45,8 +44,8 @@ | |||
| 45 | static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 44 | static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 46 | { | 45 | { |
| 47 | /* PCI-E */ | 46 | /* PCI-E */ |
| 48 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 47 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
| 49 | return IRQ_ORION_PCIE0_INT; | 48 | return IRQ_ORION5X_PCIE0_INT; |
| 50 | 49 | ||
| 51 | pr_err("%s: requested mapping for unknown bus\n", __func__); | 50 | pr_err("%s: requested mapping for unknown bus\n", __func__); |
| 52 | 51 | ||
| @@ -56,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 56 | static struct hw_pci dns323_pci __initdata = { | 55 | static struct hw_pci dns323_pci __initdata = { |
| 57 | .nr_controllers = 1, | 56 | .nr_controllers = 1, |
| 58 | .swizzle = pci_std_swizzle, | 57 | .swizzle = pci_std_swizzle, |
| 59 | .setup = orion_pci_sys_setup, | 58 | .setup = orion5x_pci_sys_setup, |
| 60 | .scan = orion_pci_sys_scan_bus, | 59 | .scan = orion5x_pci_sys_scan_bus, |
| 61 | .map_irq = dns323_pci_map_irq, | 60 | .map_irq = dns323_pci_map_irq, |
| 62 | }; | 61 | }; |
| 63 | 62 | ||
| @@ -247,27 +246,25 @@ static void dns323_power_off(void) | |||
| 247 | static void __init dns323_init(void) | 246 | static void __init dns323_init(void) |
| 248 | { | 247 | { |
| 249 | /* Setup basic Orion functions. Need to be called early. */ | 248 | /* Setup basic Orion functions. Need to be called early. */ |
| 250 | orion_init(); | 249 | orion5x_init(); |
| 251 | 250 | ||
| 252 | /* setup flash mapping | 251 | /* setup flash mapping |
| 253 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 | 252 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 |
| 254 | */ | 253 | */ |
| 255 | orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, | 254 | orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); |
| 256 | DNS323_NOR_BOOT_SIZE, -1); | ||
| 257 | 255 | ||
| 258 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE | 256 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE |
| 259 | * | 257 | * |
| 260 | * Open a special address decode windows for the PCIE WA. | 258 | * Open a special address decode windows for the PCIE WA. |
| 261 | */ | 259 | */ |
| 262 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 260 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 263 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, | 261 | ORION5X_PCIE_WA_SIZE); |
| 264 | (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 265 | 262 | ||
| 266 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ | 263 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ |
| 267 | orion_write(MPP_0_7_CTRL, 0); | 264 | orion5x_write(MPP_0_7_CTRL, 0); |
| 268 | orion_write(MPP_8_15_CTRL, 0); | 265 | orion5x_write(MPP_8_15_CTRL, 0); |
| 269 | orion_write(MPP_16_19_CTRL, 0); | 266 | orion5x_write(MPP_16_19_CTRL, 0); |
| 270 | orion_write(MPP_DEV_CTRL, 0); | 267 | orion5x_write(MPP_DEV_CTRL, 0); |
| 271 | 268 | ||
| 272 | /* Define used GPIO pins | 269 | /* Define used GPIO pins |
| 273 | 270 | ||
| @@ -290,7 +287,7 @@ static void __init dns323_init(void) | |||
| 290 | | 14 | Out | //unknown// | 287 | | 14 | Out | //unknown// |
| 291 | | 15 | Out | //unknown// | 288 | | 15 | Out | //unknown// |
| 292 | */ | 289 | */ |
| 293 | orion_gpio_set_valid_pins(0x07f6); | 290 | orion5x_gpio_set_valid_pins(0x07f6); |
| 294 | 291 | ||
| 295 | /* register dns323 specific power-off method */ | 292 | /* register dns323 specific power-off method */ |
| 296 | if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) | 293 | if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) |
| @@ -306,18 +303,18 @@ static void __init dns323_init(void) | |||
| 306 | i2c_register_board_info(0, dns323_i2c_devices, | 303 | i2c_register_board_info(0, dns323_i2c_devices, |
| 307 | ARRAY_SIZE(dns323_i2c_devices)); | 304 | ARRAY_SIZE(dns323_i2c_devices)); |
| 308 | 305 | ||
| 309 | orion_eth_init(&dns323_eth_data); | 306 | orion5x_eth_init(&dns323_eth_data); |
| 310 | } | 307 | } |
| 311 | 308 | ||
| 312 | /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ | 309 | /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ |
| 313 | MACHINE_START(DNS323, "D-Link DNS-323") | 310 | MACHINE_START(DNS323, "D-Link DNS-323") |
| 314 | /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ | 311 | /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ |
| 315 | .phys_io = ORION_REGS_PHYS_BASE, | 312 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 316 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 313 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 317 | .boot_params = 0x00000100, | 314 | .boot_params = 0x00000100, |
| 318 | .init_machine = dns323_init, | 315 | .init_machine = dns323_init, |
| 319 | .map_io = orion_map_io, | 316 | .map_io = orion5x_map_io, |
| 320 | .init_irq = orion_init_irq, | 317 | .init_irq = orion5x_init_irq, |
| 321 | .timer = &orion_timer, | 318 | .timer = &orion5x_timer, |
| 322 | .fixup = tag_fixup_mem32, | 319 | .fixup = tag_fixup_mem32, |
| 323 | MACHINE_END | 320 | MACHINE_END |
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c index f713818c66a3..8108c316c426 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/gpio.c | 2 | * arch/arm/mach-orion5x/gpio.c |
| 3 | * | 3 | * |
| 4 | * GPIO functions for Marvell Orion System On Chip | 4 | * GPIO functions for Marvell Orion System On Chip |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -16,14 +16,15 @@ | |||
| 16 | #include <linux/spinlock.h> | 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/bitops.h> | 17 | #include <linux/bitops.h> |
| 18 | #include <asm/gpio.h> | 18 | #include <asm/gpio.h> |
| 19 | #include <asm/arch/orion.h> | 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/orion5x.h> | ||
| 20 | #include "common.h" | 21 | #include "common.h" |
| 21 | 22 | ||
| 22 | static DEFINE_SPINLOCK(gpio_lock); | 23 | static DEFINE_SPINLOCK(gpio_lock); |
| 23 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; | 24 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; |
| 24 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ | 25 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ |
| 25 | 26 | ||
| 26 | void __init orion_gpio_set_valid_pins(u32 pins) | 27 | void __init orion5x_gpio_set_valid_pins(u32 pins) |
| 27 | { | 28 | { |
| 28 | gpio_valid[0] = pins; | 29 | gpio_valid[0] = pins; |
| 29 | } | 30 | } |
| @@ -49,7 +50,7 @@ int gpio_direction_input(unsigned pin) | |||
| 49 | if (!gpio_label[pin]) | 50 | if (!gpio_label[pin]) |
| 50 | gpio_label[pin] = "?"; | 51 | gpio_label[pin] = "?"; |
| 51 | 52 | ||
| 52 | orion_setbits(GPIO_IO_CONF, 1 << pin); | 53 | orion5x_setbits(GPIO_IO_CONF, 1 << pin); |
| 53 | 54 | ||
| 54 | spin_unlock_irqrestore(&gpio_lock, flags); | 55 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 55 | return 0; | 56 | return 0; |
| @@ -76,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value) | |||
| 76 | gpio_label[pin] = "?"; | 77 | gpio_label[pin] = "?"; |
| 77 | 78 | ||
| 78 | mask = 1 << pin; | 79 | mask = 1 << pin; |
| 79 | orion_clrbits(GPIO_BLINK_EN, mask); | 80 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
| 80 | if (value) | 81 | if (value) |
| 81 | orion_setbits(GPIO_OUT, mask); | 82 | orion5x_setbits(GPIO_OUT, mask); |
| 82 | else | 83 | else |
| 83 | orion_clrbits(GPIO_OUT, mask); | 84 | orion5x_clrbits(GPIO_OUT, mask); |
| 84 | orion_clrbits(GPIO_IO_CONF, mask); | 85 | orion5x_clrbits(GPIO_IO_CONF, mask); |
| 85 | 86 | ||
| 86 | spin_unlock_irqrestore(&gpio_lock, flags); | 87 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 87 | return 0; | 88 | return 0; |
| @@ -92,10 +93,10 @@ int gpio_get_value(unsigned pin) | |||
| 92 | { | 93 | { |
| 93 | int val, mask = 1 << pin; | 94 | int val, mask = 1 << pin; |
| 94 | 95 | ||
| 95 | if (orion_read(GPIO_IO_CONF) & mask) | 96 | if (orion5x_read(GPIO_IO_CONF) & mask) |
| 96 | val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); | 97 | val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); |
| 97 | else | 98 | else |
| 98 | val = orion_read(GPIO_OUT); | 99 | val = orion5x_read(GPIO_OUT); |
| 99 | 100 | ||
| 100 | return val & mask; | 101 | return val & mask; |
| 101 | } | 102 | } |
| @@ -108,32 +109,32 @@ void gpio_set_value(unsigned pin, int value) | |||
| 108 | 109 | ||
| 109 | spin_lock_irqsave(&gpio_lock, flags); | 110 | spin_lock_irqsave(&gpio_lock, flags); |
| 110 | 111 | ||
| 111 | orion_clrbits(GPIO_BLINK_EN, mask); | 112 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
| 112 | if (value) | 113 | if (value) |
| 113 | orion_setbits(GPIO_OUT, mask); | 114 | orion5x_setbits(GPIO_OUT, mask); |
| 114 | else | 115 | else |
| 115 | orion_clrbits(GPIO_OUT, mask); | 116 | orion5x_clrbits(GPIO_OUT, mask); |
| 116 | 117 | ||
| 117 | spin_unlock_irqrestore(&gpio_lock, flags); | 118 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 118 | } | 119 | } |
| 119 | EXPORT_SYMBOL(gpio_set_value); | 120 | EXPORT_SYMBOL(gpio_set_value); |
| 120 | 121 | ||
| 121 | void orion_gpio_set_blink(unsigned pin, int blink) | 122 | void orion5x_gpio_set_blink(unsigned pin, int blink) |
| 122 | { | 123 | { |
| 123 | unsigned long flags; | 124 | unsigned long flags; |
| 124 | int mask = 1 << pin; | 125 | int mask = 1 << pin; |
| 125 | 126 | ||
| 126 | spin_lock_irqsave(&gpio_lock, flags); | 127 | spin_lock_irqsave(&gpio_lock, flags); |
| 127 | 128 | ||
| 128 | orion_clrbits(GPIO_OUT, mask); | 129 | orion5x_clrbits(GPIO_OUT, mask); |
| 129 | if (blink) | 130 | if (blink) |
| 130 | orion_setbits(GPIO_BLINK_EN, mask); | 131 | orion5x_setbits(GPIO_BLINK_EN, mask); |
| 131 | else | 132 | else |
| 132 | orion_clrbits(GPIO_BLINK_EN, mask); | 133 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
| 133 | 134 | ||
| 134 | spin_unlock_irqrestore(&gpio_lock, flags); | 135 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 135 | } | 136 | } |
| 136 | EXPORT_SYMBOL(orion_gpio_set_blink); | 137 | EXPORT_SYMBOL(orion5x_gpio_set_blink); |
| 137 | 138 | ||
| 138 | int gpio_request(unsigned pin, const char *label) | 139 | int gpio_request(unsigned pin, const char *label) |
| 139 | { | 140 | { |
| @@ -187,39 +188,39 @@ void gpio_display(void) | |||
| 187 | printk("GPIO, free\n"); | 188 | printk("GPIO, free\n"); |
| 188 | } else { | 189 | } else { |
| 189 | printk("GPIO, used by %s, ", gpio_label[i]); | 190 | printk("GPIO, used by %s, ", gpio_label[i]); |
| 190 | if (orion_read(GPIO_IO_CONF) & (1 << i)) { | 191 | if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { |
| 191 | printk("input, active %s, level %s, edge %s\n", | 192 | printk("input, active %s, level %s, edge %s\n", |
| 192 | ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", | 193 | ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", |
| 193 | ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", | 194 | ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", |
| 194 | ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); | 195 | ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); |
| 195 | } else { | 196 | } else { |
| 196 | printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); | 197 | printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); |
| 197 | } | 198 | } |
| 198 | } | 199 | } |
| 199 | } | 200 | } |
| 200 | 201 | ||
| 201 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", | 202 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", |
| 202 | MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); | 203 | MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); |
| 203 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", | 204 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", |
| 204 | MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); | 205 | MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); |
| 205 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", | 206 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", |
| 206 | MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); | 207 | MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); |
| 207 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", | 208 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", |
| 208 | MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); | 209 | MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); |
| 209 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", | 210 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", |
| 210 | GPIO_OUT, orion_read(GPIO_OUT)); | 211 | GPIO_OUT, orion5x_read(GPIO_OUT)); |
| 211 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", | 212 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", |
| 212 | GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); | 213 | GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); |
| 213 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", | 214 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", |
| 214 | GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); | 215 | GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); |
| 215 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", | 216 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", |
| 216 | GPIO_IN_POL, orion_read(GPIO_IN_POL)); | 217 | GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); |
| 217 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", | 218 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", |
| 218 | GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); | 219 | GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); |
| 219 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", | 220 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", |
| 220 | GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); | 221 | GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); |
| 221 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", | 222 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", |
| 222 | GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); | 223 | GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); |
| 223 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", | 224 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", |
| 224 | GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); | 225 | GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); |
| 225 | } | 226 | } |
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c index df7e12ad378b..dd21f38c5d37 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/irq.c | 2 | * arch/arm/mach-orion5x/irq.c |
| 3 | * | 3 | * |
| 4 | * Core IRQ functions for Marvell Orion System On Chip | 4 | * Core IRQ functions for Marvell Orion System On Chip |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -14,7 +14,9 @@ | |||
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
| 16 | #include <asm/gpio.h> | 16 | #include <asm/gpio.h> |
| 17 | #include <asm/arch/orion.h> | 17 | #include <asm/io.h> |
| 18 | #include <asm/arch/orion5x.h> | ||
| 19 | #include <asm/plat-orion/irq.h> | ||
| 18 | #include "common.h" | 20 | #include "common.h" |
| 19 | 21 | ||
| 20 | /***************************************************************************** | 22 | /***************************************************************************** |
| @@ -42,46 +44,46 @@ | |||
| 42 | * polarity LEVEL mask | 44 | * polarity LEVEL mask |
| 43 | * | 45 | * |
| 44 | ****************************************************************************/ | 46 | ****************************************************************************/ |
| 45 | static void orion_gpio_irq_ack(u32 irq) | 47 | static void orion5x_gpio_irq_ack(u32 irq) |
| 46 | { | 48 | { |
| 47 | int pin = irq_to_gpio(irq); | 49 | int pin = irq_to_gpio(irq); |
| 48 | if (irq_desc[irq].status & IRQ_LEVEL) | 50 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 49 | /* | 51 | /* |
| 50 | * Mask bit for level interrupt | 52 | * Mask bit for level interrupt |
| 51 | */ | 53 | */ |
| 52 | orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); | 54 | orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); |
| 53 | else | 55 | else |
| 54 | /* | 56 | /* |
| 55 | * Clear casue bit for egde interrupt | 57 | * Clear casue bit for egde interrupt |
| 56 | */ | 58 | */ |
| 57 | orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); | 59 | orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); |
| 58 | } | 60 | } |
| 59 | 61 | ||
| 60 | static void orion_gpio_irq_mask(u32 irq) | 62 | static void orion5x_gpio_irq_mask(u32 irq) |
| 61 | { | 63 | { |
| 62 | int pin = irq_to_gpio(irq); | 64 | int pin = irq_to_gpio(irq); |
| 63 | if (irq_desc[irq].status & IRQ_LEVEL) | 65 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 64 | orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); | 66 | orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); |
| 65 | else | 67 | else |
| 66 | orion_clrbits(GPIO_EDGE_MASK, 1 << pin); | 68 | orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); |
| 67 | } | 69 | } |
| 68 | 70 | ||
| 69 | static void orion_gpio_irq_unmask(u32 irq) | 71 | static void orion5x_gpio_irq_unmask(u32 irq) |
| 70 | { | 72 | { |
| 71 | int pin = irq_to_gpio(irq); | 73 | int pin = irq_to_gpio(irq); |
| 72 | if (irq_desc[irq].status & IRQ_LEVEL) | 74 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 73 | orion_setbits(GPIO_LEVEL_MASK, 1 << pin); | 75 | orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); |
| 74 | else | 76 | else |
| 75 | orion_setbits(GPIO_EDGE_MASK, 1 << pin); | 77 | orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); |
| 76 | } | 78 | } |
| 77 | 79 | ||
| 78 | static int orion_gpio_set_irq_type(u32 irq, u32 type) | 80 | static int orion5x_gpio_set_irq_type(u32 irq, u32 type) |
| 79 | { | 81 | { |
| 80 | int pin = irq_to_gpio(irq); | 82 | int pin = irq_to_gpio(irq); |
| 81 | struct irq_desc *desc; | 83 | struct irq_desc *desc; |
| 82 | 84 | ||
| 83 | if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { | 85 | if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { |
| 84 | printk(KERN_ERR "orion_gpio_set_irq_type failed " | 86 | printk(KERN_ERR "orion5x_gpio_set_irq_type failed " |
| 85 | "(irq %d, pin %d).\n", irq, pin); | 87 | "(irq %d, pin %d).\n", irq, pin); |
| 86 | return -EINVAL; | 88 | return -EINVAL; |
| 87 | } | 89 | } |
| @@ -92,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
| 92 | case IRQT_HIGH: | 94 | case IRQT_HIGH: |
| 93 | desc->handle_irq = handle_level_irq; | 95 | desc->handle_irq = handle_level_irq; |
| 94 | desc->status |= IRQ_LEVEL; | 96 | desc->status |= IRQ_LEVEL; |
| 95 | orion_clrbits(GPIO_IN_POL, (1 << pin)); | 97 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
| 96 | break; | 98 | break; |
| 97 | case IRQT_LOW: | 99 | case IRQT_LOW: |
| 98 | desc->handle_irq = handle_level_irq; | 100 | desc->handle_irq = handle_level_irq; |
| 99 | desc->status |= IRQ_LEVEL; | 101 | desc->status |= IRQ_LEVEL; |
| 100 | orion_setbits(GPIO_IN_POL, (1 << pin)); | 102 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
| 101 | break; | 103 | break; |
| 102 | case IRQT_RISING: | 104 | case IRQT_RISING: |
| 103 | desc->handle_irq = handle_edge_irq; | 105 | desc->handle_irq = handle_edge_irq; |
| 104 | desc->status &= ~IRQ_LEVEL; | 106 | desc->status &= ~IRQ_LEVEL; |
| 105 | orion_clrbits(GPIO_IN_POL, (1 << pin)); | 107 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
| 106 | break; | 108 | break; |
| 107 | case IRQT_FALLING: | 109 | case IRQT_FALLING: |
| 108 | desc->handle_irq = handle_edge_irq; | 110 | desc->handle_irq = handle_edge_irq; |
| 109 | desc->status &= ~IRQ_LEVEL; | 111 | desc->status &= ~IRQ_LEVEL; |
| 110 | orion_setbits(GPIO_IN_POL, (1 << pin)); | 112 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
| 111 | break; | 113 | break; |
| 112 | case IRQT_BOTHEDGE: | 114 | case IRQT_BOTHEDGE: |
| 113 | desc->handle_irq = handle_edge_irq; | 115 | desc->handle_irq = handle_edge_irq; |
| @@ -115,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
| 115 | /* | 117 | /* |
| 116 | * set initial polarity based on current input level | 118 | * set initial polarity based on current input level |
| 117 | */ | 119 | */ |
| 118 | if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) | 120 | if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) |
| 119 | & (1 << pin)) | 121 | & (1 << pin)) |
| 120 | orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ | 122 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ |
| 121 | else | 123 | else |
| 122 | orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ | 124 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ |
| 123 | 125 | ||
| 124 | break; | 126 | break; |
| 125 | default: | 127 | default: |
| @@ -133,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
| 133 | return 0; | 135 | return 0; |
| 134 | } | 136 | } |
| 135 | 137 | ||
| 136 | static struct irq_chip orion_gpio_irq_chip = { | 138 | static struct irq_chip orion5x_gpio_irq_chip = { |
| 137 | .name = "Orion-IRQ-GPIO", | 139 | .name = "Orion-IRQ-GPIO", |
| 138 | .ack = orion_gpio_irq_ack, | 140 | .ack = orion5x_gpio_irq_ack, |
| 139 | .mask = orion_gpio_irq_mask, | 141 | .mask = orion5x_gpio_irq_mask, |
| 140 | .unmask = orion_gpio_irq_unmask, | 142 | .unmask = orion5x_gpio_irq_unmask, |
| 141 | .set_type = orion_gpio_set_irq_type, | 143 | .set_type = orion5x_gpio_set_irq_type, |
| 142 | }; | 144 | }; |
| 143 | 145 | ||
| 144 | static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 146 | static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 145 | { | 147 | { |
| 146 | u32 cause, offs, pin; | 148 | u32 cause, offs, pin; |
| 147 | 149 | ||
| 148 | BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); | 150 | BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); |
| 149 | offs = (irq - IRQ_ORION_GPIO_0_7) * 8; | 151 | offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; |
| 150 | cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | | 152 | cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | |
| 151 | (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); | 153 | (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); |
| 152 | 154 | ||
| 153 | for (pin = offs; pin < offs + 8; pin++) { | 155 | for (pin = offs; pin < offs + 8; pin++) { |
| 154 | if (cause & (1 << pin)) { | 156 | if (cause & (1 << pin)) { |
| @@ -156,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 156 | desc = irq_desc + irq; | 158 | desc = irq_desc + irq; |
| 157 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { |
| 158 | /* Swap polarity (race with GPIO line) */ | 160 | /* Swap polarity (race with GPIO line) */ |
| 159 | u32 polarity = orion_read(GPIO_IN_POL); | 161 | u32 polarity = orion5x_read(GPIO_IN_POL); |
| 160 | polarity ^= 1 << pin; | 162 | polarity ^= 1 << pin; |
| 161 | orion_write(GPIO_IN_POL, polarity); | 163 | orion5x_write(GPIO_IN_POL, polarity); |
| 162 | } | 164 | } |
| 163 | desc_handle_irq(irq, desc); | 165 | desc_handle_irq(irq, desc); |
| 164 | } | 166 | } |
| 165 | } | 167 | } |
| 166 | } | 168 | } |
| 167 | 169 | ||
| 168 | static void __init orion_init_gpio_irq(void) | 170 | static void __init orion5x_init_gpio_irq(void) |
| 169 | { | 171 | { |
| 170 | int i; | 172 | int i; |
| 171 | struct irq_desc *desc; | 173 | struct irq_desc *desc; |
| @@ -173,69 +175,37 @@ static void __init orion_init_gpio_irq(void) | |||
| 173 | /* | 175 | /* |
| 174 | * Mask and clear GPIO IRQ interrupts | 176 | * Mask and clear GPIO IRQ interrupts |
| 175 | */ | 177 | */ |
| 176 | orion_write(GPIO_LEVEL_MASK, 0x0); | 178 | orion5x_write(GPIO_LEVEL_MASK, 0x0); |
| 177 | orion_write(GPIO_EDGE_MASK, 0x0); | 179 | orion5x_write(GPIO_EDGE_MASK, 0x0); |
| 178 | orion_write(GPIO_EDGE_CAUSE, 0x0); | 180 | orion5x_write(GPIO_EDGE_CAUSE, 0x0); |
| 179 | 181 | ||
| 180 | /* | 182 | /* |
| 181 | * Register chained level handlers for GPIO IRQs by default. | 183 | * Register chained level handlers for GPIO IRQs by default. |
| 182 | * User can use set_type() if he wants to use edge types handlers. | 184 | * User can use set_type() if he wants to use edge types handlers. |
| 183 | */ | 185 | */ |
| 184 | for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { | 186 | for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { |
| 185 | set_irq_chip(i, &orion_gpio_irq_chip); | 187 | set_irq_chip(i, &orion5x_gpio_irq_chip); |
| 186 | set_irq_handler(i, handle_level_irq); | 188 | set_irq_handler(i, handle_level_irq); |
| 187 | desc = irq_desc + i; | 189 | desc = irq_desc + i; |
| 188 | desc->status |= IRQ_LEVEL; | 190 | desc->status |= IRQ_LEVEL; |
| 189 | set_irq_flags(i, IRQF_VALID); | 191 | set_irq_flags(i, IRQF_VALID); |
| 190 | } | 192 | } |
| 191 | set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); | 193 | set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); |
| 192 | set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); | 194 | set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); |
| 193 | set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); | 195 | set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); |
| 194 | set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); | 196 | set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); |
| 195 | } | 197 | } |
| 196 | 198 | ||
| 197 | /***************************************************************************** | 199 | /***************************************************************************** |
| 198 | * Orion Main IRQ | 200 | * Orion Main IRQ |
| 199 | ****************************************************************************/ | 201 | ****************************************************************************/ |
| 200 | static void orion_main_irq_mask(u32 irq) | 202 | static void __init orion5x_init_main_irq(void) |
| 201 | { | 203 | { |
| 202 | orion_clrbits(MAIN_IRQ_MASK, 1 << irq); | 204 | orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); |
| 203 | } | 205 | } |
| 204 | 206 | ||
| 205 | static void orion_main_irq_unmask(u32 irq) | 207 | void __init orion5x_init_irq(void) |
| 206 | { | 208 | { |
| 207 | orion_setbits(MAIN_IRQ_MASK, 1 << irq); | 209 | orion5x_init_main_irq(); |
| 208 | } | 210 | orion5x_init_gpio_irq(); |
| 209 | |||
| 210 | static struct irq_chip orion_main_irq_chip = { | ||
| 211 | .name = "Orion-IRQ-Main", | ||
| 212 | .ack = orion_main_irq_mask, | ||
| 213 | .mask = orion_main_irq_mask, | ||
| 214 | .unmask = orion_main_irq_unmask, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static void __init orion_init_main_irq(void) | ||
| 218 | { | ||
| 219 | int i; | ||
| 220 | |||
| 221 | /* | ||
| 222 | * Mask and clear Main IRQ interrupts | ||
| 223 | */ | ||
| 224 | orion_write(MAIN_IRQ_MASK, 0x0); | ||
| 225 | orion_write(MAIN_IRQ_CAUSE, 0x0); | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Register level handler for Main IRQs | ||
| 229 | */ | ||
| 230 | for (i = 0; i < IRQ_ORION_GPIO_START; i++) { | ||
| 231 | set_irq_chip(i, &orion_main_irq_chip); | ||
| 232 | set_irq_handler(i, handle_level_irq); | ||
| 233 | set_irq_flags(i, IRQF_VALID); | ||
| 234 | } | ||
| 235 | } | ||
| 236 | |||
| 237 | void __init orion_init_irq(void) | ||
| 238 | { | ||
| 239 | orion_init_main_irq(); | ||
| 240 | orion_init_gpio_irq(); | ||
| 241 | } | 211 | } |
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 785a07bdf1e2..91413455beba 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c | |||
| @@ -1,10 +1,10 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/kurobox_pro-setup.c | 2 | * arch/arm/mach-orion5x/kurobox_pro-setup.c |
| 3 | * | 3 | * |
| 4 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> | 4 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> |
| 5 | * | 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any | 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include <asm/gpio.h> | 22 | #include <asm/gpio.h> |
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach/pci.h> | 24 | #include <asm/mach/pci.h> |
| 25 | #include <asm/arch/orion.h> | 25 | #include <asm/arch/orion5x.h> |
| 26 | #include <asm/arch/platform.h> | 26 | #include <asm/plat-orion/orion_nand.h> |
| 27 | #include "common.h" | 27 | #include "common.h" |
| 28 | 28 | ||
| 29 | /***************************************************************************** | 29 | /***************************************************************************** |
| @@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 123 | /* | 123 | /* |
| 124 | * PCI isn't used on the Kuro | 124 | * PCI isn't used on the Kuro |
| 125 | */ | 125 | */ |
| 126 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 126 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
| 127 | return IRQ_ORION_PCIE0_INT; | 127 | return IRQ_ORION5X_PCIE0_INT; |
| 128 | else | 128 | else |
| 129 | printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); | 129 | printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); |
| 130 | 130 | ||
| @@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 134 | static struct hw_pci kurobox_pro_pci __initdata = { | 134 | static struct hw_pci kurobox_pro_pci __initdata = { |
| 135 | .nr_controllers = 1, | 135 | .nr_controllers = 1, |
| 136 | .swizzle = pci_std_swizzle, | 136 | .swizzle = pci_std_swizzle, |
| 137 | .setup = orion_pci_sys_setup, | 137 | .setup = orion5x_pci_sys_setup, |
| 138 | .scan = orion_pci_sys_scan_bus, | 138 | .scan = orion5x_pci_sys_scan_bus, |
| 139 | .map_irq = kurobox_pro_pci_map_irq, | 139 | .map_irq = kurobox_pro_pci_map_irq, |
| 140 | }; | 140 | }; |
| 141 | 141 | ||
| @@ -178,31 +178,25 @@ static struct mv_sata_platform_data kurobox_pro_sata_data = { | |||
| 178 | * General Setup | 178 | * General Setup |
| 179 | ****************************************************************************/ | 179 | ****************************************************************************/ |
| 180 | 180 | ||
| 181 | static struct platform_device *kurobox_pro_devices[] __initdata = { | ||
| 182 | &kurobox_pro_nor_flash, | ||
| 183 | &kurobox_pro_nand_flash, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static void __init kurobox_pro_init(void) | 181 | static void __init kurobox_pro_init(void) |
| 187 | { | 182 | { |
| 188 | /* | 183 | /* |
| 189 | * Setup basic Orion functions. Need to be called early. | 184 | * Setup basic Orion functions. Need to be called early. |
| 190 | */ | 185 | */ |
| 191 | orion_init(); | 186 | orion5x_init(); |
| 192 | 187 | ||
| 193 | /* | 188 | /* |
| 194 | * Setup the CPU address decode windows for our devices | 189 | * Setup the CPU address decode windows for our devices |
| 195 | */ | 190 | */ |
| 196 | orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, | 191 | orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, |
| 197 | KUROBOX_PRO_NOR_BOOT_SIZE, -1); | 192 | KUROBOX_PRO_NOR_BOOT_SIZE); |
| 198 | orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, | 193 | orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); |
| 199 | KUROBOX_PRO_NAND_SIZE, -1); | 194 | |
| 200 | /* | 195 | /* |
| 201 | * Open a special address decode windows for the PCIE WA. | 196 | * Open a special address decode windows for the PCIE WA. |
| 202 | */ | 197 | */ |
| 203 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 198 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 204 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | 199 | ORION5X_PCIE_WA_SIZE); |
| 205 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 206 | 200 | ||
| 207 | /* | 201 | /* |
| 208 | * Setup Multiplexing Pins -- | 202 | * Setup Multiplexing Pins -- |
| @@ -219,26 +213,44 @@ static void __init kurobox_pro_init(void) | |||
| 219 | * MPP[15] SATA 1 active indication | 213 | * MPP[15] SATA 1 active indication |
| 220 | * MPP[16-19] Not used | 214 | * MPP[16-19] Not used |
| 221 | */ | 215 | */ |
| 222 | orion_write(MPP_0_7_CTRL, 0x44220003); | 216 | orion5x_write(MPP_0_7_CTRL, 0x44220003); |
| 223 | orion_write(MPP_8_15_CTRL, 0x55550000); | 217 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
| 224 | orion_write(MPP_16_19_CTRL, 0x0); | 218 | orion5x_write(MPP_16_19_CTRL, 0x0); |
| 225 | 219 | ||
| 226 | orion_gpio_set_valid_pins(0x0000000c); | 220 | orion5x_gpio_set_valid_pins(0x0000000c); |
| 227 | 221 | ||
| 228 | platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); | 222 | platform_device_register(&kurobox_pro_nor_flash); |
| 223 | if (machine_is_kurobox_pro()) | ||
| 224 | platform_device_register(&kurobox_pro_nand_flash); | ||
| 229 | i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); | 225 | i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); |
| 230 | orion_eth_init(&kurobox_pro_eth_data); | 226 | orion5x_eth_init(&kurobox_pro_eth_data); |
| 231 | orion_sata_init(&kurobox_pro_sata_data); | 227 | orion5x_sata_init(&kurobox_pro_sata_data); |
| 232 | } | 228 | } |
| 233 | 229 | ||
| 230 | #ifdef CONFIG_MACH_KUROBOX_PRO | ||
| 234 | MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") | 231 | MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") |
| 235 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ | 232 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ |
| 236 | .phys_io = ORION_REGS_PHYS_BASE, | 233 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 237 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 234 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 235 | .boot_params = 0x00000100, | ||
| 236 | .init_machine = kurobox_pro_init, | ||
| 237 | .map_io = orion5x_map_io, | ||
| 238 | .init_irq = orion5x_init_irq, | ||
| 239 | .timer = &orion5x_timer, | ||
| 240 | .fixup = tag_fixup_mem32, | ||
| 241 | MACHINE_END | ||
| 242 | #endif | ||
| 243 | |||
| 244 | #ifdef CONFIG_MACH_LINKSTATION_PRO | ||
| 245 | MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") | ||
| 246 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ | ||
| 247 | .phys_io = ORION5X_REGS_PHYS_BASE, | ||
| 248 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, | ||
| 238 | .boot_params = 0x00000100, | 249 | .boot_params = 0x00000100, |
| 239 | .init_machine = kurobox_pro_init, | 250 | .init_machine = kurobox_pro_init, |
| 240 | .map_io = orion_map_io, | 251 | .map_io = orion5x_map_io, |
| 241 | .init_irq = orion_init_irq, | 252 | .init_irq = orion5x_init_irq, |
| 242 | .timer = &orion_timer, | 253 | .timer = &orion5x_timer, |
| 243 | .fixup = tag_fixup_mem32, | 254 | .fixup = tag_fixup_mem32, |
| 244 | MACHINE_END | 255 | MACHINE_END |
| 256 | #endif | ||
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c new file mode 100644 index 000000000000..fdf99fca85b3 --- /dev/null +++ b/arch/arm/mach-orion5x/pci.c | |||
| @@ -0,0 +1,559 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/pci.c | ||
| 3 | * | ||
| 4 | * PCI and PCIe functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/mbus.h> | ||
| 16 | #include <asm/mach/pci.h> | ||
| 17 | #include <asm/plat-orion/pcie.h> | ||
| 18 | #include "common.h" | ||
| 19 | |||
| 20 | /***************************************************************************** | ||
| 21 | * Orion has one PCIe controller and one PCI controller. | ||
| 22 | * | ||
| 23 | * Note1: The local PCIe bus number is '0'. The local PCI bus number | ||
| 24 | * follows the scanned PCIe bridged busses, if any. | ||
| 25 | * | ||
| 26 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's | ||
| 27 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on | ||
| 28 | * device bus, Orion registers, etc. However this code only enable the | ||
| 29 | * access to DDR banks. | ||
| 30 | ****************************************************************************/ | ||
| 31 | |||
| 32 | |||
| 33 | /***************************************************************************** | ||
| 34 | * PCIe controller | ||
| 35 | ****************************************************************************/ | ||
| 36 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) | ||
| 37 | |||
| 38 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) | ||
| 39 | { | ||
| 40 | *dev = orion_pcie_dev_id(PCIE_BASE); | ||
| 41 | *rev = orion_pcie_rev(PCIE_BASE); | ||
| 42 | } | ||
| 43 | |||
| 44 | int __init orion5x_pcie_local_bus_nr(void) | ||
| 45 | { | ||
| 46 | return orion_pcie_get_local_bus_nr(PCIE_BASE); | ||
| 47 | } | ||
| 48 | |||
| 49 | static int pcie_valid_config(int bus, int dev) | ||
| 50 | { | ||
| 51 | /* | ||
| 52 | * Don't go out when trying to access -- | ||
| 53 | * 1. nonexisting device on local bus | ||
| 54 | * 2. where there's no device connected (no link) | ||
| 55 | */ | ||
| 56 | if (bus == 0 && dev == 0) | ||
| 57 | return 1; | ||
| 58 | |||
| 59 | if (!orion_pcie_link_up(PCIE_BASE)) | ||
| 60 | return 0; | ||
| 61 | |||
| 62 | if (bus == 0 && dev != 1) | ||
| 63 | return 0; | ||
| 64 | |||
| 65 | return 1; | ||
| 66 | } | ||
| 67 | |||
| 68 | |||
| 69 | /* | ||
| 70 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register | ||
| 71 | * and then reading the PCIE_CONF_DATA register. Need to make sure these | ||
| 72 | * transactions are atomic. | ||
| 73 | */ | ||
| 74 | static DEFINE_SPINLOCK(orion5x_pcie_lock); | ||
| 75 | |||
| 76 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 77 | int size, u32 *val) | ||
| 78 | { | ||
| 79 | unsigned long flags; | ||
| 80 | int ret; | ||
| 81 | |||
| 82 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 83 | *val = 0xffffffff; | ||
| 84 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 85 | } | ||
| 86 | |||
| 87 | spin_lock_irqsave(&orion5x_pcie_lock, flags); | ||
| 88 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); | ||
| 89 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); | ||
| 90 | |||
| 91 | return ret; | ||
| 92 | } | ||
| 93 | |||
| 94 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, | ||
| 95 | int where, int size, u32 *val) | ||
| 96 | { | ||
| 97 | int ret; | ||
| 98 | |||
| 99 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 100 | *val = 0xffffffff; | ||
| 101 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 102 | } | ||
| 103 | |||
| 104 | /* | ||
| 105 | * We only support access to the non-extended configuration | ||
| 106 | * space when using the WA access method (or we would have to | ||
| 107 | * sacrifice 256M of CPU virtual address space.) | ||
| 108 | */ | ||
| 109 | if (where >= 0x100) { | ||
| 110 | *val = 0xffffffff; | ||
| 111 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 112 | } | ||
| 113 | |||
| 114 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, | ||
| 115 | bus, devfn, where, size, val); | ||
| 116 | |||
| 117 | return ret; | ||
| 118 | } | ||
| 119 | |||
| 120 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 121 | int where, int size, u32 val) | ||
| 122 | { | ||
| 123 | unsigned long flags; | ||
| 124 | int ret; | ||
| 125 | |||
| 126 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) | ||
| 127 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 128 | |||
| 129 | spin_lock_irqsave(&orion5x_pcie_lock, flags); | ||
| 130 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); | ||
| 131 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); | ||
| 132 | |||
| 133 | return ret; | ||
| 134 | } | ||
| 135 | |||
| 136 | static struct pci_ops pcie_ops = { | ||
| 137 | .read = pcie_rd_conf, | ||
| 138 | .write = pcie_wr_conf, | ||
| 139 | }; | ||
| 140 | |||
| 141 | |||
| 142 | static int __init pcie_setup(struct pci_sys_data *sys) | ||
| 143 | { | ||
| 144 | struct resource *res; | ||
| 145 | int dev; | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Generic PCIe unit setup. | ||
| 149 | */ | ||
| 150 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Check whether to apply Orion-1/Orion-NAS PCIe config | ||
| 154 | * read transaction workaround. | ||
| 155 | */ | ||
| 156 | dev = orion_pcie_dev_id(PCIE_BASE); | ||
| 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | ||
| 158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | ||
| 159 | "read transaction workaround\n"); | ||
| 160 | pcie_ops.read = pcie_rd_conf_wa; | ||
| 161 | } | ||
| 162 | |||
| 163 | /* | ||
| 164 | * Request resources. | ||
| 165 | */ | ||
| 166 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 167 | if (!res) | ||
| 168 | panic("pcie_setup unable to alloc resources"); | ||
| 169 | |||
| 170 | /* | ||
| 171 | * IORESOURCE_IO | ||
| 172 | */ | ||
| 173 | res[0].name = "PCIe I/O Space"; | ||
| 174 | res[0].flags = IORESOURCE_IO; | ||
| 175 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; | ||
| 176 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; | ||
| 177 | if (request_resource(&ioport_resource, &res[0])) | ||
| 178 | panic("Request PCIe IO resource failed\n"); | ||
| 179 | sys->resource[0] = &res[0]; | ||
| 180 | |||
| 181 | /* | ||
| 182 | * IORESOURCE_MEM | ||
| 183 | */ | ||
| 184 | res[1].name = "PCIe Memory Space"; | ||
| 185 | res[1].flags = IORESOURCE_MEM; | ||
| 186 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; | ||
| 187 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; | ||
| 188 | if (request_resource(&iomem_resource, &res[1])) | ||
| 189 | panic("Request PCIe Memory resource failed\n"); | ||
| 190 | sys->resource[1] = &res[1]; | ||
| 191 | |||
| 192 | sys->resource[2] = NULL; | ||
| 193 | sys->io_offset = 0; | ||
| 194 | |||
| 195 | return 1; | ||
| 196 | } | ||
| 197 | |||
| 198 | /***************************************************************************** | ||
| 199 | * PCI controller | ||
| 200 | ****************************************************************************/ | ||
| 201 | #define PCI_MODE ORION5X_PCI_REG(0xd00) | ||
| 202 | #define PCI_CMD ORION5X_PCI_REG(0xc00) | ||
| 203 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) | ||
| 204 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) | ||
| 205 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) | ||
| 206 | |||
| 207 | /* | ||
| 208 | * PCI_MODE bits | ||
| 209 | */ | ||
| 210 | #define PCI_MODE_64BIT (1 << 2) | ||
| 211 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | ||
| 212 | |||
| 213 | /* | ||
| 214 | * PCI_CMD bits | ||
| 215 | */ | ||
| 216 | #define PCI_CMD_HOST_REORDER (1 << 29) | ||
| 217 | |||
| 218 | /* | ||
| 219 | * PCI_P2P_CONF bits | ||
| 220 | */ | ||
| 221 | #define PCI_P2P_BUS_OFFS 16 | ||
| 222 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | ||
| 223 | #define PCI_P2P_DEV_OFFS 24 | ||
| 224 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | ||
| 225 | |||
| 226 | /* | ||
| 227 | * PCI_CONF_ADDR bits | ||
| 228 | */ | ||
| 229 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | ||
| 230 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | ||
| 231 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | ||
| 232 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | ||
| 233 | #define PCI_CONF_ADDR_EN (1 << 31) | ||
| 234 | |||
| 235 | /* | ||
| 236 | * Internal configuration space | ||
| 237 | */ | ||
| 238 | #define PCI_CONF_FUNC_STAT_CMD 0 | ||
| 239 | #define PCI_CONF_REG_STAT_CMD 4 | ||
| 240 | #define PCIX_STAT 0x64 | ||
| 241 | #define PCIX_STAT_BUS_OFFS 8 | ||
| 242 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | ||
| 243 | |||
| 244 | /* | ||
| 245 | * PCI Address Decode Windows registers | ||
| 246 | */ | ||
| 247 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ | ||
| 248 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ | ||
| 249 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ | ||
| 250 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) | ||
| 251 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ | ||
| 252 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ | ||
| 253 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ | ||
| 254 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) | ||
| 255 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) | ||
| 256 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) | ||
| 257 | |||
| 258 | /* | ||
| 259 | * PCI configuration helpers for BAR settings | ||
| 260 | */ | ||
| 261 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | ||
| 262 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | ||
| 263 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | ||
| 264 | |||
| 265 | /* | ||
| 266 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | ||
| 267 | * and then reading the PCI_CONF_DATA register. Need to make sure these | ||
| 268 | * transactions are atomic. | ||
| 269 | */ | ||
| 270 | static DEFINE_SPINLOCK(orion5x_pci_lock); | ||
| 271 | |||
| 272 | int orion5x_pci_local_bus_nr(void) | ||
| 273 | { | ||
| 274 | u32 conf = orion5x_read(PCI_P2P_CONF); | ||
| 275 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); | ||
| 276 | } | ||
| 277 | |||
| 278 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, | ||
| 279 | u32 where, u32 size, u32 *val) | ||
| 280 | { | ||
| 281 | unsigned long flags; | ||
| 282 | spin_lock_irqsave(&orion5x_pci_lock, flags); | ||
| 283 | |||
| 284 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 285 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 286 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 287 | |||
| 288 | *val = orion5x_read(PCI_CONF_DATA); | ||
| 289 | |||
| 290 | if (size == 1) | ||
| 291 | *val = (*val >> (8*(where & 0x3))) & 0xff; | ||
| 292 | else if (size == 2) | ||
| 293 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | ||
| 294 | |||
| 295 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); | ||
| 296 | |||
| 297 | return PCIBIOS_SUCCESSFUL; | ||
| 298 | } | ||
| 299 | |||
| 300 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, | ||
| 301 | u32 where, u32 size, u32 val) | ||
| 302 | { | ||
| 303 | unsigned long flags; | ||
| 304 | int ret = PCIBIOS_SUCCESSFUL; | ||
| 305 | |||
| 306 | spin_lock_irqsave(&orion5x_pci_lock, flags); | ||
| 307 | |||
| 308 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 309 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 310 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 311 | |||
| 312 | if (size == 4) { | ||
| 313 | __raw_writel(val, PCI_CONF_DATA); | ||
| 314 | } else if (size == 2) { | ||
| 315 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 316 | } else if (size == 1) { | ||
| 317 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 318 | } else { | ||
| 319 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 320 | } | ||
| 321 | |||
| 322 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); | ||
| 323 | |||
| 324 | return ret; | ||
| 325 | } | ||
| 326 | |||
| 327 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, | ||
| 328 | int where, int size, u32 *val) | ||
| 329 | { | ||
| 330 | /* | ||
| 331 | * Don't go out for local device | ||
| 332 | */ | ||
| 333 | if (bus->number == orion5x_pci_local_bus_nr() && | ||
| 334 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { | ||
| 335 | *val = 0xffffffff; | ||
| 336 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 337 | } | ||
| 338 | |||
| 339 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), | ||
| 340 | PCI_FUNC(devfn), where, size, val); | ||
| 341 | } | ||
| 342 | |||
| 343 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 344 | int where, int size, u32 val) | ||
| 345 | { | ||
| 346 | if (bus->number == orion5x_pci_local_bus_nr() && | ||
| 347 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) | ||
| 348 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 349 | |||
| 350 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), | ||
| 351 | PCI_FUNC(devfn), where, size, val); | ||
| 352 | } | ||
| 353 | |||
| 354 | static struct pci_ops pci_ops = { | ||
| 355 | .read = orion5x_pci_rd_conf, | ||
| 356 | .write = orion5x_pci_wr_conf, | ||
| 357 | }; | ||
| 358 | |||
| 359 | static void __init orion5x_pci_set_bus_nr(int nr) | ||
| 360 | { | ||
| 361 | u32 p2p = orion5x_read(PCI_P2P_CONF); | ||
| 362 | |||
| 363 | if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { | ||
| 364 | /* | ||
| 365 | * PCI-X mode | ||
| 366 | */ | ||
| 367 | u32 pcix_status, bus, dev; | ||
| 368 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | ||
| 369 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | ||
| 370 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); | ||
| 371 | pcix_status &= ~PCIX_STAT_BUS_MASK; | ||
| 372 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | ||
| 373 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); | ||
| 374 | } else { | ||
| 375 | /* | ||
| 376 | * PCI Conventional mode | ||
| 377 | */ | ||
| 378 | p2p &= ~PCI_P2P_BUS_MASK; | ||
| 379 | p2p |= (nr << PCI_P2P_BUS_OFFS); | ||
| 380 | orion5x_write(PCI_P2P_CONF, p2p); | ||
| 381 | } | ||
| 382 | } | ||
| 383 | |||
| 384 | static void __init orion5x_pci_master_slave_enable(void) | ||
| 385 | { | ||
| 386 | int bus_nr, func, reg; | ||
| 387 | u32 val; | ||
| 388 | |||
| 389 | bus_nr = orion5x_pci_local_bus_nr(); | ||
| 390 | func = PCI_CONF_FUNC_STAT_CMD; | ||
| 391 | reg = PCI_CONF_REG_STAT_CMD; | ||
| 392 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); | ||
| 393 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | ||
| 394 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); | ||
| 395 | } | ||
| 396 | |||
| 397 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) | ||
| 398 | { | ||
| 399 | u32 win_enable; | ||
| 400 | int bus; | ||
| 401 | int i; | ||
| 402 | |||
| 403 | /* | ||
| 404 | * First, disable windows. | ||
| 405 | */ | ||
| 406 | win_enable = 0xffffffff; | ||
| 407 | orion5x_write(PCI_BAR_ENABLE, win_enable); | ||
| 408 | |||
| 409 | /* | ||
| 410 | * Setup windows for DDR banks. | ||
| 411 | */ | ||
| 412 | bus = orion5x_pci_local_bus_nr(); | ||
| 413 | |||
| 414 | for (i = 0; i < dram->num_cs; i++) { | ||
| 415 | struct mbus_dram_window *cs = dram->cs + i; | ||
| 416 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | ||
| 417 | u32 reg; | ||
| 418 | u32 val; | ||
| 419 | |||
| 420 | /* | ||
| 421 | * Write DRAM bank base address register. | ||
| 422 | */ | ||
| 423 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | ||
| 424 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); | ||
| 425 | val = (cs->base & 0xfffff000) | (val & 0xfff); | ||
| 426 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); | ||
| 427 | |||
| 428 | /* | ||
| 429 | * Write DRAM bank size register. | ||
| 430 | */ | ||
| 431 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | ||
| 432 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); | ||
| 433 | orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), | ||
| 434 | (cs->size - 1) & 0xfffff000); | ||
| 435 | orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), | ||
| 436 | cs->base & 0xfffff000); | ||
| 437 | |||
| 438 | /* | ||
| 439 | * Enable decode window for this chip select. | ||
| 440 | */ | ||
| 441 | win_enable &= ~(1 << cs->cs_index); | ||
| 442 | } | ||
| 443 | |||
| 444 | /* | ||
| 445 | * Re-enable decode windows. | ||
| 446 | */ | ||
| 447 | orion5x_write(PCI_BAR_ENABLE, win_enable); | ||
| 448 | |||
| 449 | /* | ||
| 450 | * Disable automatic update of address remaping when writing to BARs. | ||
| 451 | */ | ||
| 452 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); | ||
| 453 | } | ||
| 454 | |||
| 455 | static int __init pci_setup(struct pci_sys_data *sys) | ||
| 456 | { | ||
| 457 | struct resource *res; | ||
| 458 | |||
| 459 | /* | ||
| 460 | * Point PCI unit MBUS decode windows to DRAM space. | ||
| 461 | */ | ||
| 462 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); | ||
| 463 | |||
| 464 | /* | ||
| 465 | * Master + Slave enable | ||
| 466 | */ | ||
| 467 | orion5x_pci_master_slave_enable(); | ||
| 468 | |||
| 469 | /* | ||
| 470 | * Force ordering | ||
| 471 | */ | ||
| 472 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); | ||
| 473 | |||
| 474 | /* | ||
| 475 | * Request resources | ||
| 476 | */ | ||
| 477 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 478 | if (!res) | ||
| 479 | panic("pci_setup unable to alloc resources"); | ||
| 480 | |||
| 481 | /* | ||
| 482 | * IORESOURCE_IO | ||
| 483 | */ | ||
| 484 | res[0].name = "PCI I/O Space"; | ||
| 485 | res[0].flags = IORESOURCE_IO; | ||
| 486 | res[0].start = ORION5X_PCI_IO_BUS_BASE; | ||
| 487 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; | ||
| 488 | if (request_resource(&ioport_resource, &res[0])) | ||
| 489 | panic("Request PCI IO resource failed\n"); | ||
| 490 | sys->resource[0] = &res[0]; | ||
| 491 | |||
| 492 | /* | ||
| 493 | * IORESOURCE_MEM | ||
| 494 | */ | ||
| 495 | res[1].name = "PCI Memory Space"; | ||
| 496 | res[1].flags = IORESOURCE_MEM; | ||
| 497 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; | ||
| 498 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; | ||
| 499 | if (request_resource(&iomem_resource, &res[1])) | ||
| 500 | panic("Request PCI Memory resource failed\n"); | ||
| 501 | sys->resource[1] = &res[1]; | ||
| 502 | |||
| 503 | sys->resource[2] = NULL; | ||
| 504 | sys->io_offset = 0; | ||
| 505 | |||
| 506 | return 1; | ||
| 507 | } | ||
| 508 | |||
| 509 | |||
| 510 | /***************************************************************************** | ||
| 511 | * General PCIe + PCI | ||
| 512 | ****************************************************************************/ | ||
| 513 | static void __devinit rc_pci_fixup(struct pci_dev *dev) | ||
| 514 | { | ||
| 515 | /* | ||
| 516 | * Prevent enumeration of root complex. | ||
| 517 | */ | ||
| 518 | if (dev->bus->parent == NULL && dev->devfn == 0) { | ||
| 519 | int i; | ||
| 520 | |||
| 521 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
| 522 | dev->resource[i].start = 0; | ||
| 523 | dev->resource[i].end = 0; | ||
| 524 | dev->resource[i].flags = 0; | ||
| 525 | } | ||
| 526 | } | ||
| 527 | } | ||
| 528 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | ||
| 529 | |||
| 530 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) | ||
| 531 | { | ||
| 532 | int ret = 0; | ||
| 533 | |||
| 534 | if (nr == 0) { | ||
| 535 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); | ||
| 536 | ret = pcie_setup(sys); | ||
| 537 | } else if (nr == 1) { | ||
| 538 | orion5x_pci_set_bus_nr(sys->busnr); | ||
| 539 | ret = pci_setup(sys); | ||
| 540 | } | ||
| 541 | |||
| 542 | return ret; | ||
| 543 | } | ||
| 544 | |||
| 545 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) | ||
| 546 | { | ||
| 547 | struct pci_bus *bus; | ||
| 548 | |||
| 549 | if (nr == 0) { | ||
| 550 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); | ||
| 551 | } else if (nr == 1) { | ||
| 552 | bus = pci_scan_bus(sys->busnr, &pci_ops, sys); | ||
| 553 | } else { | ||
| 554 | bus = NULL; | ||
| 555 | BUG(); | ||
| 556 | } | ||
| 557 | |||
| 558 | return bus; | ||
| 559 | } | ||
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index e851b8ca5ac6..37e8b2dc3ed5 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/rd88f5182-setup.c | 2 | * arch/arm/mach-orion5x/rd88f5182-setup.c |
| 3 | * | 3 | * |
| 4 | * Marvell Orion-NAS Reference Design Setup | 4 | * Marvell Orion-NAS Reference Design Setup |
| 5 | * | 5 | * |
| 6 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> | 6 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -24,8 +24,7 @@ | |||
| 24 | #include <asm/leds.h> | 24 | #include <asm/leds.h> |
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/pci.h> | 26 | #include <asm/mach/pci.h> |
| 27 | #include <asm/arch/orion.h> | 27 | #include <asm/arch/orion5x.h> |
| 28 | #include <asm/arch/platform.h> | ||
| 29 | #include "common.h" | 28 | #include "common.h" |
| 30 | 29 | ||
| 31 | /***************************************************************************** | 30 | /***************************************************************************** |
| @@ -176,8 +175,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 176 | /* | 175 | /* |
| 177 | * PCI-E isn't used on the RD2 | 176 | * PCI-E isn't used on the RD2 |
| 178 | */ | 177 | */ |
| 179 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 178 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
| 180 | return IRQ_ORION_PCIE0_INT; | 179 | return IRQ_ORION5X_PCIE0_INT; |
| 181 | 180 | ||
| 182 | /* | 181 | /* |
| 183 | * PCI IRQs are connected via GPIOs | 182 | * PCI IRQs are connected via GPIOs |
| @@ -197,8 +196,8 @@ static struct hw_pci rd88f5182_pci __initdata = { | |||
| 197 | .nr_controllers = 2, | 196 | .nr_controllers = 2, |
| 198 | .preinit = rd88f5182_pci_preinit, | 197 | .preinit = rd88f5182_pci_preinit, |
| 199 | .swizzle = pci_std_swizzle, | 198 | .swizzle = pci_std_swizzle, |
| 200 | .setup = orion_pci_sys_setup, | 199 | .setup = orion5x_pci_sys_setup, |
| 201 | .scan = orion_pci_sys_scan_bus, | 200 | .scan = orion5x_pci_sys_scan_bus, |
| 202 | .map_irq = rd88f5182_pci_map_irq, | 201 | .map_irq = rd88f5182_pci_map_irq, |
| 203 | }; | 202 | }; |
| 204 | 203 | ||
| @@ -250,22 +249,20 @@ static void __init rd88f5182_init(void) | |||
| 250 | /* | 249 | /* |
| 251 | * Setup basic Orion functions. Need to be called early. | 250 | * Setup basic Orion functions. Need to be called early. |
| 252 | */ | 251 | */ |
| 253 | orion_init(); | 252 | orion5x_init(); |
| 254 | 253 | ||
| 255 | /* | 254 | /* |
| 256 | * Setup the CPU address decode windows for our devices | 255 | * Setup the CPU address decode windows for our devices |
| 257 | */ | 256 | */ |
| 258 | orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, | 257 | orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, |
| 259 | RD88F5182_NOR_BOOT_SIZE, -1); | 258 | RD88F5182_NOR_BOOT_SIZE); |
| 260 | orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, | 259 | orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); |
| 261 | RD88F5182_NOR_SIZE, -1); | ||
| 262 | 260 | ||
| 263 | /* | 261 | /* |
| 264 | * Open a special address decode windows for the PCIE WA. | 262 | * Open a special address decode windows for the PCIE WA. |
| 265 | */ | 263 | */ |
| 266 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 264 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 267 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | 265 | ORION5X_PCIE_WA_SIZE); |
| 268 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 269 | 266 | ||
| 270 | /* | 267 | /* |
| 271 | * Setup Multiplexing Pins -- | 268 | * Setup Multiplexing Pins -- |
| @@ -291,25 +288,25 @@ static void __init rd88f5182_init(void) | |||
| 291 | * MPP[25] USB 0 over current enable | 288 | * MPP[25] USB 0 over current enable |
| 292 | */ | 289 | */ |
| 293 | 290 | ||
| 294 | orion_write(MPP_0_7_CTRL, 0x00000003); | 291 | orion5x_write(MPP_0_7_CTRL, 0x00000003); |
| 295 | orion_write(MPP_8_15_CTRL, 0x55550000); | 292 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
| 296 | orion_write(MPP_16_19_CTRL, 0x5555); | 293 | orion5x_write(MPP_16_19_CTRL, 0x5555); |
| 297 | 294 | ||
| 298 | orion_gpio_set_valid_pins(0x000000fb); | 295 | orion5x_gpio_set_valid_pins(0x000000fb); |
| 299 | 296 | ||
| 300 | platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); | 297 | platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); |
| 301 | i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); | 298 | i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); |
| 302 | orion_eth_init(&rd88f5182_eth_data); | 299 | orion5x_eth_init(&rd88f5182_eth_data); |
| 303 | orion_sata_init(&rd88f5182_sata_data); | 300 | orion5x_sata_init(&rd88f5182_sata_data); |
| 304 | } | 301 | } |
| 305 | 302 | ||
| 306 | MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") | 303 | MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") |
| 307 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ | 304 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ |
| 308 | .phys_io = ORION_REGS_PHYS_BASE, | 305 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 309 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 306 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 310 | .boot_params = 0x00000100, | 307 | .boot_params = 0x00000100, |
| 311 | .init_machine = rd88f5182_init, | 308 | .init_machine = rd88f5182_init, |
| 312 | .map_io = orion_map_io, | 309 | .map_io = orion5x_map_io, |
| 313 | .init_irq = orion_init_irq, | 310 | .init_irq = orion5x_init_irq, |
| 314 | .timer = &orion_timer, | 311 | .timer = &orion5x_timer, |
| 315 | MACHINE_END | 312 | MACHINE_END |
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 45764dad16d0..fd43863a86f6 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
| @@ -26,8 +26,7 @@ | |||
| 26 | #include <asm/gpio.h> | 26 | #include <asm/gpio.h> |
| 27 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 28 | #include <asm/mach/pci.h> | 28 | #include <asm/mach/pci.h> |
| 29 | #include <asm/arch/orion.h> | 29 | #include <asm/arch/orion5x.h> |
| 30 | #include <asm/arch/platform.h> | ||
| 31 | #include "common.h" | 30 | #include "common.h" |
| 32 | 31 | ||
| 33 | #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 | 32 | #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 |
| @@ -145,8 +144,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 145 | /* | 144 | /* |
| 146 | * PCIE IRQ is connected internally (not GPIO) | 145 | * PCIE IRQ is connected internally (not GPIO) |
| 147 | */ | 146 | */ |
| 148 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 147 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
| 149 | return IRQ_ORION_PCIE0_INT; | 148 | return IRQ_ORION5X_PCIE0_INT; |
| 150 | 149 | ||
| 151 | /* | 150 | /* |
| 152 | * PCI IRQs are connected via GPIOs | 151 | * PCI IRQs are connected via GPIOs |
| @@ -165,8 +164,8 @@ static struct hw_pci qnap_ts209_pci __initdata = { | |||
| 165 | .nr_controllers = 2, | 164 | .nr_controllers = 2, |
| 166 | .preinit = qnap_ts209_pci_preinit, | 165 | .preinit = qnap_ts209_pci_preinit, |
| 167 | .swizzle = pci_std_swizzle, | 166 | .swizzle = pci_std_swizzle, |
| 168 | .setup = orion_pci_sys_setup, | 167 | .setup = orion5x_pci_sys_setup, |
| 169 | .scan = orion_pci_sys_scan_bus, | 168 | .scan = orion5x_pci_sys_scan_bus, |
| 170 | .map_irq = qnap_ts209_pci_map_irq, | 169 | .map_irq = qnap_ts209_pci_map_irq, |
| 171 | }; | 170 | }; |
| 172 | 171 | ||
| @@ -189,6 +188,87 @@ static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { | |||
| 189 | .force_phy_addr = 1, | 188 | .force_phy_addr = 1, |
| 190 | }; | 189 | }; |
| 191 | 190 | ||
| 191 | static int __init parse_hex_nibble(char n) | ||
| 192 | { | ||
| 193 | if (n >= '0' && n <= '9') | ||
| 194 | return n - '0'; | ||
| 195 | |||
| 196 | if (n >= 'A' && n <= 'F') | ||
| 197 | return n - 'A' + 10; | ||
| 198 | |||
| 199 | if (n >= 'a' && n <= 'f') | ||
| 200 | return n - 'a' + 10; | ||
| 201 | |||
| 202 | return -1; | ||
| 203 | } | ||
| 204 | |||
| 205 | static int __init parse_hex_byte(const char *b) | ||
| 206 | { | ||
| 207 | int hi; | ||
| 208 | int lo; | ||
| 209 | |||
| 210 | hi = parse_hex_nibble(b[0]); | ||
| 211 | lo = parse_hex_nibble(b[1]); | ||
| 212 | |||
| 213 | if (hi < 0 || lo < 0) | ||
| 214 | return -1; | ||
| 215 | |||
| 216 | return (hi << 4) | lo; | ||
| 217 | } | ||
| 218 | |||
| 219 | static int __init check_mac_addr(const char *addr_str) | ||
| 220 | { | ||
| 221 | u_int8_t addr[6]; | ||
| 222 | int i; | ||
| 223 | |||
| 224 | for (i = 0; i < 6; i++) { | ||
| 225 | int byte; | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Enforce "xx:xx:xx:xx:xx:xx\n" format. | ||
| 229 | */ | ||
| 230 | if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) | ||
| 231 | return -1; | ||
| 232 | |||
| 233 | byte = parse_hex_byte(addr_str + (i * 3)); | ||
| 234 | if (byte < 0) | ||
| 235 | return -1; | ||
| 236 | addr[i] = byte; | ||
| 237 | } | ||
| 238 | |||
| 239 | printk(KERN_INFO "ts209: found ethernet mac address "); | ||
| 240 | for (i = 0; i < 6; i++) | ||
| 241 | printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); | ||
| 242 | |||
| 243 | memcpy(qnap_ts209_eth_data.mac_addr, addr, 6); | ||
| 244 | |||
| 245 | return 0; | ||
| 246 | } | ||
| 247 | |||
| 248 | /* | ||
| 249 | * The 'NAS Config' flash partition has an ext2 filesystem which | ||
| 250 | * contains a file that has the ethernet MAC address in plain text | ||
| 251 | * (format "xx:xx:xx:xx:xx:xx\n".) | ||
| 252 | */ | ||
| 253 | static void __init ts209_find_mac_addr(void) | ||
| 254 | { | ||
| 255 | unsigned long addr; | ||
| 256 | |||
| 257 | for (addr = 0x00700000; addr < 0x00760000; addr += 1024) { | ||
| 258 | char *nor_page; | ||
| 259 | int ret = 0; | ||
| 260 | |||
| 261 | nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024); | ||
| 262 | if (nor_page != NULL) { | ||
| 263 | ret = check_mac_addr(nor_page); | ||
| 264 | iounmap(nor_page); | ||
| 265 | } | ||
| 266 | |||
| 267 | if (ret == 0) | ||
| 268 | break; | ||
| 269 | } | ||
| 270 | } | ||
| 271 | |||
| 192 | /***************************************************************************** | 272 | /***************************************************************************** |
| 193 | * RTC S35390A on I2C bus | 273 | * RTC S35390A on I2C bus |
| 194 | ****************************************************************************/ | 274 | ****************************************************************************/ |
| @@ -262,21 +342,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = { | |||
| 262 | static void qnap_ts209_power_off(void) | 342 | static void qnap_ts209_power_off(void) |
| 263 | { | 343 | { |
| 264 | /* 19200 baud divisor */ | 344 | /* 19200 baud divisor */ |
| 265 | const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); | 345 | const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); |
| 266 | 346 | ||
| 267 | pr_info("%s: triggering power-off...\n", __func__); | 347 | pr_info("%s: triggering power-off...\n", __func__); |
| 268 | 348 | ||
| 269 | /* hijack uart1 and reset into sane state (19200,8n1) */ | 349 | /* hijack uart1 and reset into sane state (19200,8n1) */ |
| 270 | orion_write(UART1_REG(LCR), 0x83); | 350 | orion5x_write(UART1_REG(LCR), 0x83); |
| 271 | orion_write(UART1_REG(DLL), divisor & 0xff); | 351 | orion5x_write(UART1_REG(DLL), divisor & 0xff); |
| 272 | orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); | 352 | orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); |
| 273 | orion_write(UART1_REG(LCR), 0x03); | 353 | orion5x_write(UART1_REG(LCR), 0x03); |
| 274 | orion_write(UART1_REG(IER), 0x00); | 354 | orion5x_write(UART1_REG(IER), 0x00); |
| 275 | orion_write(UART1_REG(FCR), 0x00); | 355 | orion5x_write(UART1_REG(FCR), 0x00); |
| 276 | orion_write(UART1_REG(MCR), 0x00); | 356 | orion5x_write(UART1_REG(MCR), 0x00); |
| 277 | 357 | ||
| 278 | /* send the power-off command 'A' to PIC */ | 358 | /* send the power-off command 'A' to PIC */ |
| 279 | orion_write(UART1_REG(TX), 'A'); | 359 | orion5x_write(UART1_REG(TX), 'A'); |
| 280 | } | 360 | } |
| 281 | 361 | ||
| 282 | static void __init qnap_ts209_init(void) | 362 | static void __init qnap_ts209_init(void) |
| @@ -284,20 +364,19 @@ static void __init qnap_ts209_init(void) | |||
| 284 | /* | 364 | /* |
| 285 | * Setup basic Orion functions. Need to be called early. | 365 | * Setup basic Orion functions. Need to be called early. |
| 286 | */ | 366 | */ |
| 287 | orion_init(); | 367 | orion5x_init(); |
| 288 | 368 | ||
| 289 | /* | 369 | /* |
| 290 | * Setup flash mapping | 370 | * Setup flash mapping |
| 291 | */ | 371 | */ |
| 292 | orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, | 372 | orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, |
| 293 | QNAP_TS209_NOR_BOOT_SIZE, -1); | 373 | QNAP_TS209_NOR_BOOT_SIZE); |
| 294 | 374 | ||
| 295 | /* | 375 | /* |
| 296 | * Open a special address decode windows for the PCIE WA. | 376 | * Open a special address decode windows for the PCIE WA. |
| 297 | */ | 377 | */ |
| 298 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 378 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 299 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | 379 | ORION5X_PCIE_WA_SIZE); |
| 300 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 301 | 380 | ||
| 302 | /* | 381 | /* |
| 303 | * Setup Multiplexing Pins -- | 382 | * Setup Multiplexing Pins -- |
| @@ -322,10 +401,10 @@ static void __init qnap_ts209_init(void) | |||
| 322 | * MPP[22] USB 0 over current | 401 | * MPP[22] USB 0 over current |
| 323 | * MPP[23-25] Reserved | 402 | * MPP[23-25] Reserved |
| 324 | */ | 403 | */ |
| 325 | orion_write(MPP_0_7_CTRL, 0x3); | 404 | orion5x_write(MPP_0_7_CTRL, 0x3); |
| 326 | orion_write(MPP_8_15_CTRL, 0x55550000); | 405 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
| 327 | orion_write(MPP_16_19_CTRL, 0x5500); | 406 | orion5x_write(MPP_16_19_CTRL, 0x5500); |
| 328 | orion_gpio_set_valid_pins(0x3cc0fff); | 407 | orion5x_gpio_set_valid_pins(0x3cc0fff); |
| 329 | 408 | ||
| 330 | /* register ts209 specific power-off method */ | 409 | /* register ts209 specific power-off method */ |
| 331 | pm_power_off = qnap_ts209_power_off; | 410 | pm_power_off = qnap_ts209_power_off; |
| @@ -344,18 +423,20 @@ static void __init qnap_ts209_init(void) | |||
| 344 | pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); | 423 | pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); |
| 345 | i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); | 424 | i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); |
| 346 | 425 | ||
| 347 | orion_eth_init(&qnap_ts209_eth_data); | 426 | ts209_find_mac_addr(); |
| 348 | orion_sata_init(&qnap_ts209_sata_data); | 427 | orion5x_eth_init(&qnap_ts209_eth_data); |
| 428 | |||
| 429 | orion5x_sata_init(&qnap_ts209_sata_data); | ||
| 349 | } | 430 | } |
| 350 | 431 | ||
| 351 | MACHINE_START(TS209, "QNAP TS-109/TS-209") | 432 | MACHINE_START(TS209, "QNAP TS-109/TS-209") |
| 352 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ | 433 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ |
| 353 | .phys_io = ORION_REGS_PHYS_BASE, | 434 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 354 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 435 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 355 | .boot_params = 0x00000100, | 436 | .boot_params = 0x00000100, |
| 356 | .init_machine = qnap_ts209_init, | 437 | .init_machine = qnap_ts209_init, |
| 357 | .map_io = orion_map_io, | 438 | .map_io = orion5x_map_io, |
| 358 | .init_irq = orion_init_irq, | 439 | .init_irq = orion5x_init_irq, |
| 359 | .timer = &orion_timer, | 440 | .timer = &orion5x_timer, |
| 360 | .fixup = tag_fixup_mem32, | 441 | .fixup = tag_fixup_mem32, |
| 361 | MACHINE_END | 442 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 0908bea0f609..5da7a6820492 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -23,6 +23,12 @@ endif | |||
| 23 | choice | 23 | choice |
| 24 | prompt "Select target board" | 24 | prompt "Select target board" |
| 25 | 25 | ||
| 26 | config ARCH_GUMSTIX | ||
| 27 | bool "Gumstix XScale boards" | ||
| 28 | help | ||
| 29 | Say Y here if you intend to run this kernel on a | ||
| 30 | Gumstix Full Function Minature Computer. | ||
| 31 | |||
| 26 | config ARCH_LUBBOCK | 32 | config ARCH_LUBBOCK |
| 27 | bool "Intel DBPXA250 Development Platform" | 33 | bool "Intel DBPXA250 Development Platform" |
| 28 | select PXA25x | 34 | select PXA25x |
| @@ -160,6 +166,20 @@ endchoice | |||
| 160 | 166 | ||
| 161 | endif | 167 | endif |
| 162 | 168 | ||
| 169 | if ARCH_GUMSTIX | ||
| 170 | |||
| 171 | choice | ||
| 172 | prompt "Select target Gumstix board" | ||
| 173 | |||
| 174 | config MACH_GUMSTIX_F | ||
| 175 | bool "Basix, Connex, ws-200ax, ws-400ax systems" | ||
| 176 | select PXA25x | ||
| 177 | |||
| 178 | endchoice | ||
| 179 | |||
| 180 | endif | ||
| 181 | |||
| 182 | |||
| 163 | if MACH_TRIZEPS4 | 183 | if MACH_TRIZEPS4 |
| 164 | 184 | ||
| 165 | choice | 185 | choice |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 6e0c4f5b5ae6..7cdcb459ea9d 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -5,13 +5,14 @@ | |||
| 5 | # Common support (must be linked before board specific support) | 5 | # Common support (must be linked before board specific support) |
| 6 | obj-y += clock.o devices.o generic.o irq.o dma.o \ | 6 | obj-y += clock.o devices.o generic.o irq.o dma.o \ |
| 7 | time.o gpio.o | 7 | time.o gpio.o |
| 8 | obj-$(CONFIG_PXA25x) += pxa25x.o | 8 | obj-$(CONFIG_PXA25x) += pxa25x.o mfp-pxa2xx.o |
| 9 | obj-$(CONFIG_PXA27x) += pxa27x.o | 9 | obj-$(CONFIG_PXA27x) += pxa27x.o mfp-pxa2xx.o |
| 10 | obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o smemc.o | 10 | obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp-pxa3xx.o smemc.o |
| 11 | obj-$(CONFIG_CPU_PXA300) += pxa300.o | 11 | obj-$(CONFIG_CPU_PXA300) += pxa300.o |
| 12 | obj-$(CONFIG_CPU_PXA320) += pxa320.o | 12 | obj-$(CONFIG_CPU_PXA320) += pxa320.o |
| 13 | 13 | ||
| 14 | # Specific board support | 14 | # Specific board support |
| 15 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o | ||
| 15 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 16 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
| 16 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | 17 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o |
| 17 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 18 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index df5ae2710ab1..e97dc59813c8 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <linux/delay.h> | 13 | #include <linux/delay.h> |
| 14 | 14 | ||
| 15 | #include <asm/arch/pxa-regs.h> | 15 | #include <asm/arch/pxa-regs.h> |
| 16 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 16 | #include <asm/hardware.h> | 17 | #include <asm/hardware.h> |
| 17 | 18 | ||
| 18 | #include "devices.h" | 19 | #include "devices.h" |
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c index fcda7d5cb693..ac7f05f9f3eb 100644 --- a/arch/arm/mach-pxa/cm-x270-pci.c +++ b/arch/arm/mach-pxa/cm-x270-pci.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <asm/mach/pci.h> | 23 | #include <asm/mach/pci.h> |
| 24 | #include <asm/arch/cm-x270.h> | 24 | #include <asm/arch/cm-x270.h> |
| 25 | #include <asm/arch/pxa-regs.h> | 25 | #include <asm/arch/pxa-regs.h> |
| 26 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 26 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 27 | 28 | ||
| 28 | #include <asm/hardware/it8152.h> | 29 | #include <asm/hardware/it8152.h> |
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index ecdbc96a4de1..6d4416a4f378 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | 30 | ||
| 31 | #include <asm/arch/pxa-regs.h> | 31 | #include <asm/arch/pxa-regs.h> |
| 32 | #include <asm/arch/pxa2xx-regs.h> | 32 | #include <asm/arch/pxa2xx-regs.h> |
| 33 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 33 | #include <asm/arch/pxafb.h> | 34 | #include <asm/arch/pxafb.h> |
| 34 | #include <asm/arch/ohci.h> | 35 | #include <asm/arch/ohci.h> |
| 35 | #include <asm/arch/mmc.h> | 36 | #include <asm/arch/mmc.h> |
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c index 6db54e31c397..43bf5a183e90 100644 --- a/arch/arm/mach-pxa/colibri.c +++ b/arch/arm/mach-pxa/colibri.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <asm/mach/irq.h> | 29 | #include <asm/mach/irq.h> |
| 30 | #include <asm/mach/flash.h> | 30 | #include <asm/mach/flash.h> |
| 31 | #include <asm/arch/pxa-regs.h> | 31 | #include <asm/arch/pxa-regs.h> |
| 32 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 32 | #include <asm/arch/colibri.h> | 33 | #include <asm/arch/colibri.h> |
| 33 | 34 | ||
| 34 | #include "generic.h" | 35 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 9292576b83b3..259ca821e464 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <asm/mach/irq.h> | 36 | #include <asm/mach/irq.h> |
| 37 | 37 | ||
| 38 | #include <asm/arch/pxa-regs.h> | 38 | #include <asm/arch/pxa-regs.h> |
| 39 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 39 | #include <asm/arch/irda.h> | 40 | #include <asm/arch/irda.h> |
| 40 | #include <asm/arch/mmc.h> | 41 | #include <asm/arch/mmc.h> |
| 41 | #include <asm/arch/udc.h> | 42 | #include <asm/arch/udc.h> |
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index 392c38717362..0a85f706e887 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/arch/sharpsl.h> | 26 | #include <asm/arch/sharpsl.h> |
| 27 | #include <asm/arch/corgi.h> | 27 | #include <asm/arch/corgi.h> |
| 28 | #include <asm/arch/pxa-regs.h> | 28 | #include <asm/arch/pxa-regs.h> |
| 29 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 29 | #include "sharpsl.h" | 30 | #include "sharpsl.h" |
| 30 | 31 | ||
| 31 | #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ | 32 | #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ |
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 31706224a04c..eccc45d21f75 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | 21 | ||
| 22 | #include <asm/arch/ssp.h> | 22 | #include <asm/arch/ssp.h> |
| 23 | #include <asm/arch/pxa-regs.h> | 23 | #include <asm/arch/pxa-regs.h> |
| 24 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 24 | #include <asm/arch/regs-ssp.h> | 25 | #include <asm/arch/regs-ssp.h> |
| 25 | #include "sharpsl.h" | 26 | #include "sharpsl.h" |
| 26 | 27 | ||
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index bfccb80ac8ef..d6c05b6eab35 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
| @@ -11,6 +11,8 @@ | |||
| 11 | #include <asm/arch/irda.h> | 11 | #include <asm/arch/irda.h> |
| 12 | #include <asm/arch/i2c.h> | 12 | #include <asm/arch/i2c.h> |
| 13 | #include <asm/arch/ohci.h> | 13 | #include <asm/arch/ohci.h> |
| 14 | #include <asm/arch/pxa27x_keypad.h> | ||
| 15 | #include <asm/arch/camera.h> | ||
| 14 | 16 | ||
| 15 | #include "devices.h" | 17 | #include "devices.h" |
| 16 | 18 | ||
| @@ -396,6 +398,31 @@ struct platform_device pxa25x_device_assp = { | |||
| 396 | 398 | ||
| 397 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | 399 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
| 398 | 400 | ||
| 401 | static struct resource pxa27x_resource_keypad[] = { | ||
| 402 | [0] = { | ||
| 403 | .start = 0x41500000, | ||
| 404 | .end = 0x4150004c, | ||
| 405 | .flags = IORESOURCE_MEM, | ||
| 406 | }, | ||
| 407 | [1] = { | ||
| 408 | .start = IRQ_KEYPAD, | ||
| 409 | .end = IRQ_KEYPAD, | ||
| 410 | .flags = IORESOURCE_IRQ, | ||
| 411 | }, | ||
| 412 | }; | ||
| 413 | |||
| 414 | struct platform_device pxa27x_device_keypad = { | ||
| 415 | .name = "pxa27x-keypad", | ||
| 416 | .id = -1, | ||
| 417 | .resource = pxa27x_resource_keypad, | ||
| 418 | .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), | ||
| 419 | }; | ||
| 420 | |||
| 421 | void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) | ||
| 422 | { | ||
| 423 | pxa_register_device(&pxa27x_device_keypad, info); | ||
| 424 | } | ||
| 425 | |||
| 399 | static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); | 426 | static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); |
| 400 | 427 | ||
| 401 | static struct resource pxa27x_resource_ohci[] = { | 428 | static struct resource pxa27x_resource_ohci[] = { |
| @@ -540,6 +567,37 @@ struct platform_device pxa27x_device_ssp3 = { | |||
| 540 | .resource = pxa27x_resource_ssp3, | 567 | .resource = pxa27x_resource_ssp3, |
| 541 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), | 568 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), |
| 542 | }; | 569 | }; |
| 570 | |||
| 571 | static struct resource pxa27x_resource_camera[] = { | ||
| 572 | [0] = { | ||
| 573 | .start = 0x50000000, | ||
| 574 | .end = 0x50000fff, | ||
| 575 | .flags = IORESOURCE_MEM, | ||
| 576 | }, | ||
| 577 | [1] = { | ||
| 578 | .start = IRQ_CAMERA, | ||
| 579 | .end = IRQ_CAMERA, | ||
| 580 | .flags = IORESOURCE_IRQ, | ||
| 581 | }, | ||
| 582 | }; | ||
| 583 | |||
| 584 | static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); | ||
| 585 | |||
| 586 | static struct platform_device pxa27x_device_camera = { | ||
| 587 | .name = "pxa27x-camera", | ||
| 588 | .id = 0, /* This is used to put cameras on this interface */ | ||
| 589 | .dev = { | ||
| 590 | .dma_mask = &pxa27x_dma_mask_camera, | ||
| 591 | .coherent_dma_mask = 0xffffffff, | ||
| 592 | }, | ||
| 593 | .num_resources = ARRAY_SIZE(pxa27x_resource_camera), | ||
| 594 | .resource = pxa27x_resource_camera, | ||
| 595 | }; | ||
| 596 | |||
| 597 | void __init pxa_set_camera_info(struct pxacamera_platform_data *info) | ||
| 598 | { | ||
| 599 | pxa_register_device(&pxa27x_device_camera, info); | ||
| 600 | } | ||
| 543 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ | 601 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ |
| 544 | 602 | ||
| 545 | #ifdef CONFIG_PXA3xx | 603 | #ifdef CONFIG_PXA3xx |
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 96c7c8909068..fcab017f27ee 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h | |||
| @@ -14,6 +14,7 @@ extern struct platform_device pxa_device_rtc; | |||
| 14 | 14 | ||
| 15 | extern struct platform_device pxa27x_device_i2c_power; | 15 | extern struct platform_device pxa27x_device_i2c_power; |
| 16 | extern struct platform_device pxa27x_device_ohci; | 16 | extern struct platform_device pxa27x_device_ohci; |
| 17 | extern struct platform_device pxa27x_device_keypad; | ||
| 17 | 18 | ||
| 18 | extern struct platform_device pxa25x_device_ssp; | 19 | extern struct platform_device pxa25x_device_ssp; |
| 19 | extern struct platform_device pxa25x_device_nssp; | 20 | extern struct platform_device pxa25x_device_nssp; |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 3bb31314429a..edc4f07a230d 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | 24 | ||
| 25 | #include <asm/arch/pxa-regs.h> | 25 | #include <asm/arch/pxa-regs.h> |
| 26 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 26 | #include <asm/arch/pxafb.h> | 27 | #include <asm/arch/pxafb.h> |
| 27 | #include <asm/arch/ohci.h> | 28 | #include <asm/arch/ohci.h> |
| 28 | #include <asm/arch/mmc.h> | 29 | #include <asm/arch/mmc.h> |
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 80721c610d41..331f29b2d0cd 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
| @@ -19,14 +19,8 @@ | |||
| 19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 22 | #include <linux/delay.h> | ||
| 23 | #include <linux/ioport.h> | ||
| 24 | #include <linux/pm.h> | ||
| 25 | #include <linux/string.h> | ||
| 26 | #include <linux/sysdev.h> | ||
| 27 | 22 | ||
| 28 | #include <asm/hardware.h> | 23 | #include <asm/hardware.h> |
| 29 | #include <asm/irq.h> | ||
| 30 | #include <asm/system.h> | 24 | #include <asm/system.h> |
| 31 | #include <asm/pgtable.h> | 25 | #include <asm/pgtable.h> |
| 32 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| @@ -134,59 +128,3 @@ void __init pxa_map_io(void) | |||
| 134 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | 128 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); |
| 135 | get_clk_frequency_khz(1); | 129 | get_clk_frequency_khz(1); |
| 136 | } | 130 | } |
| 137 | |||
| 138 | #ifdef CONFIG_PM | ||
| 139 | |||
| 140 | static unsigned long saved_gplr[4]; | ||
| 141 | static unsigned long saved_gpdr[4]; | ||
| 142 | static unsigned long saved_grer[4]; | ||
| 143 | static unsigned long saved_gfer[4]; | ||
| 144 | |||
| 145 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) | ||
| 146 | { | ||
| 147 | int i, gpio; | ||
| 148 | |||
| 149 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 150 | saved_gplr[i] = GPLR(gpio); | ||
| 151 | saved_gpdr[i] = GPDR(gpio); | ||
| 152 | saved_grer[i] = GRER(gpio); | ||
| 153 | saved_gfer[i] = GFER(gpio); | ||
| 154 | |||
| 155 | /* Clear GPIO transition detect bits */ | ||
| 156 | GEDR(gpio) = GEDR(gpio); | ||
| 157 | } | ||
| 158 | return 0; | ||
| 159 | } | ||
| 160 | |||
| 161 | static int pxa_gpio_resume(struct sys_device *dev) | ||
| 162 | { | ||
| 163 | int i, gpio; | ||
| 164 | |||
| 165 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 166 | /* restore level with set/clear */ | ||
| 167 | GPSR(gpio) = saved_gplr[i]; | ||
| 168 | GPCR(gpio) = ~saved_gplr[i]; | ||
| 169 | |||
| 170 | GRER(gpio) = saved_grer[i]; | ||
| 171 | GFER(gpio) = saved_gfer[i]; | ||
| 172 | GPDR(gpio) = saved_gpdr[i]; | ||
| 173 | } | ||
| 174 | return 0; | ||
| 175 | } | ||
| 176 | #else | ||
| 177 | #define pxa_gpio_suspend NULL | ||
| 178 | #define pxa_gpio_resume NULL | ||
| 179 | #endif | ||
| 180 | |||
| 181 | struct sysdev_class pxa_gpio_sysclass = { | ||
| 182 | .name = "gpio", | ||
| 183 | .suspend = pxa_gpio_suspend, | ||
| 184 | .resume = pxa_gpio_resume, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static int __init pxa_gpio_init(void) | ||
| 188 | { | ||
| 189 | return sysdev_class_register(&pxa_gpio_sysclass); | ||
| 190 | } | ||
| 191 | |||
| 192 | core_initcall(pxa_gpio_init); | ||
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index b3d10b0e52a0..5bb7ae757831 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
| @@ -9,14 +9,13 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | typedef int (*set_wake_t)(unsigned int, unsigned int); | ||
| 13 | |||
| 12 | struct sys_timer; | 14 | struct sys_timer; |
| 13 | 15 | ||
| 14 | extern struct sys_timer pxa_timer; | 16 | extern struct sys_timer pxa_timer; |
| 15 | extern void __init pxa_init_irq_low(void); | 17 | extern void __init pxa_init_irq(int irq_nr, set_wake_t fn); |
| 16 | extern void __init pxa_init_irq_high(void); | 18 | extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn); |
| 17 | extern void __init pxa_init_irq_gpio(int gpio_nr); | ||
| 18 | extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)); | ||
| 19 | extern void __init pxa_init_gpio(int gpio_nr); | ||
| 20 | extern void __init pxa25x_init_irq(void); | 19 | extern void __init pxa25x_init_irq(void); |
| 21 | extern void __init pxa27x_init_irq(void); | 20 | extern void __init pxa27x_init_irq(void); |
| 22 | extern void __init pxa3xx_init_irq(void); | 21 | extern void __init pxa3xx_init_irq(void); |
| @@ -30,6 +29,8 @@ extern int pxa_last_gpio; | |||
| 30 | mi->bank[__nr].size = (__size), \ | 29 | mi->bank[__nr].size = (__size), \ |
| 31 | mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) | 30 | mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) |
| 32 | 31 | ||
| 32 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
| 33 | |||
| 33 | #ifdef CONFIG_PXA25x | 34 | #ifdef CONFIG_PXA25x |
| 34 | extern unsigned pxa25x_get_clk_frequency_khz(int); | 35 | extern unsigned pxa25x_get_clk_frequency_khz(int); |
| 35 | extern unsigned pxa25x_get_memclk_frequency_10khz(void); | 36 | extern unsigned pxa25x_get_memclk_frequency_10khz(void); |
| @@ -56,3 +57,4 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void); | |||
| 56 | 57 | ||
| 57 | extern struct sysdev_class pxa_irq_sysclass; | 58 | extern struct sysdev_class pxa_irq_sysclass; |
| 58 | extern struct sysdev_class pxa_gpio_sysclass; | 59 | extern struct sysdev_class pxa_gpio_sysclass; |
| 60 | extern struct sysdev_class pxa3xx_mfp_sysclass; | ||
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 8638dd7dd076..7d3e16970be0 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c | |||
| @@ -14,11 +14,14 @@ | |||
| 14 | 14 | ||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> | 16 | #include <linux/module.h> |
| 17 | #include <linux/irq.h> | ||
| 18 | #include <linux/sysdev.h> | ||
| 17 | 19 | ||
| 18 | #include <asm/gpio.h> | 20 | #include <asm/gpio.h> |
| 19 | #include <asm/hardware.h> | 21 | #include <asm/hardware.h> |
| 20 | #include <asm/io.h> | 22 | #include <asm/io.h> |
| 21 | #include <asm/arch/pxa-regs.h> | 23 | #include <asm/arch/pxa-regs.h> |
| 24 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 22 | 25 | ||
| 23 | #include "generic.h" | 26 | #include "generic.h" |
| 24 | 27 | ||
| @@ -129,69 +132,283 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |||
| 129 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); | 132 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); |
| 130 | } | 133 | } |
| 131 | 134 | ||
| 135 | #define GPIO_CHIP(_n) \ | ||
| 136 | [_n] = { \ | ||
| 137 | .regbase = GPIO##_n##_BASE, \ | ||
| 138 | .chip = { \ | ||
| 139 | .label = "gpio-" #_n, \ | ||
| 140 | .direction_input = pxa_gpio_direction_input, \ | ||
| 141 | .direction_output = pxa_gpio_direction_output, \ | ||
| 142 | .get = pxa_gpio_get, \ | ||
| 143 | .set = pxa_gpio_set, \ | ||
| 144 | .base = (_n) * 32, \ | ||
| 145 | .ngpio = 32, \ | ||
| 146 | }, \ | ||
| 147 | } | ||
| 148 | |||
| 132 | static struct pxa_gpio_chip pxa_gpio_chip[] = { | 149 | static struct pxa_gpio_chip pxa_gpio_chip[] = { |
| 133 | [0] = { | 150 | GPIO_CHIP(0), |
| 134 | .regbase = GPIO0_BASE, | 151 | GPIO_CHIP(1), |
| 135 | .chip = { | 152 | GPIO_CHIP(2), |
| 136 | .label = "gpio-0", | ||
| 137 | .direction_input = pxa_gpio_direction_input, | ||
| 138 | .direction_output = pxa_gpio_direction_output, | ||
| 139 | .get = pxa_gpio_get, | ||
| 140 | .set = pxa_gpio_set, | ||
| 141 | .base = 0, | ||
| 142 | .ngpio = 32, | ||
| 143 | }, | ||
| 144 | }, | ||
| 145 | [1] = { | ||
| 146 | .regbase = GPIO1_BASE, | ||
| 147 | .chip = { | ||
| 148 | .label = "gpio-1", | ||
| 149 | .direction_input = pxa_gpio_direction_input, | ||
| 150 | .direction_output = pxa_gpio_direction_output, | ||
| 151 | .get = pxa_gpio_get, | ||
| 152 | .set = pxa_gpio_set, | ||
| 153 | .base = 32, | ||
| 154 | .ngpio = 32, | ||
| 155 | }, | ||
| 156 | }, | ||
| 157 | [2] = { | ||
| 158 | .regbase = GPIO2_BASE, | ||
| 159 | .chip = { | ||
| 160 | .label = "gpio-2", | ||
| 161 | .direction_input = pxa_gpio_direction_input, | ||
| 162 | .direction_output = pxa_gpio_direction_output, | ||
| 163 | .get = pxa_gpio_get, | ||
| 164 | .set = pxa_gpio_set, | ||
| 165 | .base = 64, | ||
| 166 | .ngpio = 32, /* 21 for PXA25x */ | ||
| 167 | }, | ||
| 168 | }, | ||
| 169 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | 153 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
| 170 | [3] = { | 154 | GPIO_CHIP(3), |
| 171 | .regbase = GPIO3_BASE, | ||
| 172 | .chip = { | ||
| 173 | .label = "gpio-3", | ||
| 174 | .direction_input = pxa_gpio_direction_input, | ||
| 175 | .direction_output = pxa_gpio_direction_output, | ||
| 176 | .get = pxa_gpio_get, | ||
| 177 | .set = pxa_gpio_set, | ||
| 178 | .base = 96, | ||
| 179 | .ngpio = 32, | ||
| 180 | }, | ||
| 181 | }, | ||
| 182 | #endif | 155 | #endif |
| 183 | }; | 156 | }; |
| 184 | 157 | ||
| 185 | void __init pxa_init_gpio(int gpio_nr) | 158 | /* |
| 159 | * PXA GPIO edge detection for IRQs: | ||
| 160 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | ||
| 161 | * Use this instead of directly setting GRER/GFER. | ||
| 162 | */ | ||
| 163 | |||
| 164 | static unsigned long GPIO_IRQ_rising_edge[4]; | ||
| 165 | static unsigned long GPIO_IRQ_falling_edge[4]; | ||
| 166 | static unsigned long GPIO_IRQ_mask[4]; | ||
| 167 | |||
| 168 | /* | ||
| 169 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | ||
| 170 | * function of a GPIO, and GPDRx cannot be altered once configured. It | ||
| 171 | * is attributed as "occupied" here (I know this terminology isn't | ||
| 172 | * accurate, you are welcome to propose a better one :-) | ||
| 173 | */ | ||
| 174 | static int __gpio_is_occupied(unsigned gpio) | ||
| 175 | { | ||
| 176 | if (cpu_is_pxa25x() || cpu_is_pxa27x()) | ||
| 177 | return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2)); | ||
| 178 | else | ||
| 179 | return 0; | ||
| 180 | } | ||
| 181 | |||
| 182 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
| 183 | { | ||
| 184 | int gpio, idx; | ||
| 185 | |||
| 186 | gpio = IRQ_TO_GPIO(irq); | ||
| 187 | idx = gpio >> 5; | ||
| 188 | |||
| 189 | if (type == IRQ_TYPE_PROBE) { | ||
| 190 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
| 191 | * GPIOs set to alternate function or to output during probe | ||
| 192 | */ | ||
| 193 | if ((GPIO_IRQ_rising_edge[idx] | | ||
| 194 | GPIO_IRQ_falling_edge[idx] | | ||
| 195 | GPDR(gpio)) & GPIO_bit(gpio)) | ||
| 196 | return 0; | ||
| 197 | |||
| 198 | if (__gpio_is_occupied(gpio)) | ||
| 199 | return 0; | ||
| 200 | |||
| 201 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
| 202 | } | ||
| 203 | |||
| 204 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 205 | |||
| 206 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 207 | __set_bit(gpio, GPIO_IRQ_rising_edge); | ||
| 208 | else | ||
| 209 | __clear_bit(gpio, GPIO_IRQ_rising_edge); | ||
| 210 | |||
| 211 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 212 | __set_bit(gpio, GPIO_IRQ_falling_edge); | ||
| 213 | else | ||
| 214 | __clear_bit(gpio, GPIO_IRQ_falling_edge); | ||
| 215 | |||
| 216 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 217 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 218 | |||
| 219 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | ||
| 220 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | ||
| 221 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | ||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | |||
| 225 | /* | ||
| 226 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | ||
| 227 | */ | ||
| 228 | |||
| 229 | static void pxa_ack_low_gpio(unsigned int irq) | ||
| 230 | { | ||
| 231 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
| 232 | } | ||
| 233 | |||
| 234 | static void pxa_mask_low_gpio(unsigned int irq) | ||
| 235 | { | ||
| 236 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | ||
| 237 | } | ||
| 238 | |||
| 239 | static void pxa_unmask_low_gpio(unsigned int irq) | ||
| 240 | { | ||
| 241 | ICMR |= 1 << (irq - PXA_IRQ(0)); | ||
| 242 | } | ||
| 243 | |||
| 244 | static struct irq_chip pxa_low_gpio_chip = { | ||
| 245 | .name = "GPIO-l", | ||
| 246 | .ack = pxa_ack_low_gpio, | ||
| 247 | .mask = pxa_mask_low_gpio, | ||
| 248 | .unmask = pxa_unmask_low_gpio, | ||
| 249 | .set_type = pxa_gpio_irq_type, | ||
| 250 | }; | ||
| 251 | |||
| 252 | /* | ||
| 253 | * Demux handler for GPIO>=2 edge detect interrupts | ||
| 254 | */ | ||
| 255 | |||
| 256 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) | ||
| 257 | |||
| 258 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
| 259 | { | ||
| 260 | int loop, bit, n; | ||
| 261 | unsigned long gedr[4]; | ||
| 262 | |||
| 263 | do { | ||
| 264 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; | ||
| 265 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; | ||
| 266 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; | ||
| 267 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; | ||
| 268 | |||
| 269 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; | ||
| 270 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; | ||
| 271 | |||
| 272 | loop = 0; | ||
| 273 | bit = find_first_bit(gedr, GEDR_BITS); | ||
| 274 | while (bit < GEDR_BITS) { | ||
| 275 | loop = 1; | ||
| 276 | |||
| 277 | n = PXA_GPIO_IRQ_BASE + bit; | ||
| 278 | desc_handle_irq(n, irq_desc + n); | ||
| 279 | |||
| 280 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); | ||
| 281 | } | ||
| 282 | } while (loop); | ||
| 283 | } | ||
| 284 | |||
| 285 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
| 286 | { | ||
| 287 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 288 | GEDR(gpio) = GPIO_bit(gpio); | ||
| 289 | } | ||
| 290 | |||
| 291 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
| 292 | { | ||
| 293 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 294 | __clear_bit(gpio, GPIO_IRQ_mask); | ||
| 295 | GRER(gpio) &= ~GPIO_bit(gpio); | ||
| 296 | GFER(gpio) &= ~GPIO_bit(gpio); | ||
| 297 | } | ||
| 298 | |||
| 299 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
| 300 | { | ||
| 301 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 302 | int idx = gpio >> 5; | ||
| 303 | __set_bit(gpio, GPIO_IRQ_mask); | ||
| 304 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 305 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 306 | } | ||
| 307 | |||
| 308 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
| 309 | .name = "GPIO", | ||
| 310 | .ack = pxa_ack_muxed_gpio, | ||
| 311 | .mask = pxa_mask_muxed_gpio, | ||
| 312 | .unmask = pxa_unmask_muxed_gpio, | ||
| 313 | .set_type = pxa_gpio_irq_type, | ||
| 314 | }; | ||
| 315 | |||
| 316 | void __init pxa_init_gpio(int gpio_nr, set_wake_t fn) | ||
| 186 | { | 317 | { |
| 187 | int i; | 318 | int irq, i, gpio; |
| 319 | |||
| 320 | pxa_last_gpio = gpio_nr - 1; | ||
| 321 | |||
| 322 | /* clear all GPIO edge detects */ | ||
| 323 | for (i = 0; i < gpio_nr; i += 32) { | ||
| 324 | GFER(i) = 0; | ||
| 325 | GRER(i) = 0; | ||
| 326 | GEDR(i) = GEDR(i); | ||
| 327 | } | ||
| 328 | |||
| 329 | /* GPIO 0 and 1 must have their mask bit always set */ | ||
| 330 | GPIO_IRQ_mask[0] = 3; | ||
| 331 | |||
| 332 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
| 333 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
| 334 | set_irq_handler(irq, handle_edge_irq); | ||
| 335 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 336 | } | ||
| 337 | |||
| 338 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { | ||
| 339 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
| 340 | set_irq_handler(irq, handle_edge_irq); | ||
| 341 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 342 | } | ||
| 343 | |||
| 344 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
| 345 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | ||
| 346 | |||
| 347 | pxa_low_gpio_chip.set_wake = fn; | ||
| 348 | pxa_muxed_gpio_chip.set_wake = fn; | ||
| 188 | 349 | ||
| 189 | /* add a GPIO chip for each register bank. | 350 | /* add a GPIO chip for each register bank. |
| 190 | * the last PXA25x register only contains 21 GPIOs | 351 | * the last PXA25x register only contains 21 GPIOs |
| 191 | */ | 352 | */ |
| 192 | for (i = 0; i < gpio_nr; i += 32) { | 353 | for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { |
| 193 | if (i+32 > gpio_nr) | 354 | if (gpio + 32 > gpio_nr) |
| 194 | pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i; | 355 | pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; |
| 195 | gpiochip_add(&pxa_gpio_chip[i/32].chip); | 356 | gpiochip_add(&pxa_gpio_chip[i].chip); |
| 196 | } | 357 | } |
| 197 | } | 358 | } |
| 359 | |||
| 360 | #ifdef CONFIG_PM | ||
| 361 | |||
| 362 | static unsigned long saved_gplr[4]; | ||
| 363 | static unsigned long saved_gpdr[4]; | ||
| 364 | static unsigned long saved_grer[4]; | ||
| 365 | static unsigned long saved_gfer[4]; | ||
| 366 | |||
| 367 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) | ||
| 368 | { | ||
| 369 | int i, gpio; | ||
| 370 | |||
| 371 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 372 | saved_gplr[i] = GPLR(gpio); | ||
| 373 | saved_gpdr[i] = GPDR(gpio); | ||
| 374 | saved_grer[i] = GRER(gpio); | ||
| 375 | saved_gfer[i] = GFER(gpio); | ||
| 376 | |||
| 377 | /* Clear GPIO transition detect bits */ | ||
| 378 | GEDR(gpio) = GEDR(gpio); | ||
| 379 | } | ||
| 380 | return 0; | ||
| 381 | } | ||
| 382 | |||
| 383 | static int pxa_gpio_resume(struct sys_device *dev) | ||
| 384 | { | ||
| 385 | int i, gpio; | ||
| 386 | |||
| 387 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 388 | /* restore level with set/clear */ | ||
| 389 | GPSR(gpio) = saved_gplr[i]; | ||
| 390 | GPCR(gpio) = ~saved_gplr[i]; | ||
| 391 | |||
| 392 | GRER(gpio) = saved_grer[i]; | ||
| 393 | GFER(gpio) = saved_gfer[i]; | ||
| 394 | GPDR(gpio) = saved_gpdr[i]; | ||
| 395 | } | ||
| 396 | return 0; | ||
| 397 | } | ||
| 398 | #else | ||
| 399 | #define pxa_gpio_suspend NULL | ||
| 400 | #define pxa_gpio_resume NULL | ||
| 401 | #endif | ||
| 402 | |||
| 403 | struct sysdev_class pxa_gpio_sysclass = { | ||
| 404 | .name = "gpio", | ||
| 405 | .suspend = pxa_gpio_suspend, | ||
| 406 | .resume = pxa_gpio_resume, | ||
| 407 | }; | ||
| 408 | |||
| 409 | static int __init pxa_gpio_init(void) | ||
| 410 | { | ||
| 411 | return sysdev_class_register(&pxa_gpio_sysclass); | ||
| 412 | } | ||
| 413 | |||
| 414 | core_initcall(pxa_gpio_init); | ||
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c new file mode 100644 index 000000000000..f01d18544133 --- /dev/null +++ b/arch/arm/mach-pxa/gumstix.c | |||
| @@ -0,0 +1,147 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/gumstix.c | ||
| 3 | * | ||
| 4 | * Support for the Gumstix motherboards. | ||
| 5 | * | ||
| 6 | * Original Author: Craig Hughes | ||
| 7 | * Created: Feb 14, 2008 | ||
| 8 | * Copyright: Craig Hughes | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * Implemented based on lubbock.c by Nicolas Pitre and code from Craig | ||
| 15 | * Hughes | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/interrupt.h> | ||
| 23 | #include <linux/mtd/mtd.h> | ||
| 24 | #include <linux/mtd/partitions.h> | ||
| 25 | |||
| 26 | #include <asm/setup.h> | ||
| 27 | #include <asm/memory.h> | ||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/hardware.h> | ||
| 30 | #include <asm/irq.h> | ||
| 31 | #include <asm/sizes.h> | ||
| 32 | |||
| 33 | #include <asm/mach/arch.h> | ||
| 34 | #include <asm/mach/map.h> | ||
| 35 | #include <asm/mach/irq.h> | ||
| 36 | #include <asm/mach/flash.h> | ||
| 37 | #include <asm/arch/mmc.h> | ||
| 38 | #include <asm/arch/udc.h> | ||
| 39 | #include <asm/arch/gumstix.h> | ||
| 40 | |||
| 41 | #include <asm/arch/pxa-regs.h> | ||
| 42 | #include <asm/arch/pxa2xx-regs.h> | ||
| 43 | |||
| 44 | #include "generic.h" | ||
| 45 | |||
| 46 | static struct resource flash_resource = { | ||
| 47 | .start = 0x00000000, | ||
| 48 | .end = SZ_64M - 1, | ||
| 49 | .flags = IORESOURCE_MEM, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static struct mtd_partition gumstix_partitions[] = { | ||
| 53 | { | ||
| 54 | .name = "Bootloader", | ||
| 55 | .size = 0x00040000, | ||
| 56 | .offset = 0, | ||
| 57 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 58 | } , { | ||
| 59 | .name = "rootfs", | ||
| 60 | .size = MTDPART_SIZ_FULL, | ||
| 61 | .offset = MTDPART_OFS_APPEND | ||
| 62 | } | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct flash_platform_data gumstix_flash_data = { | ||
| 66 | .map_name = "cfi_probe", | ||
| 67 | .parts = gumstix_partitions, | ||
| 68 | .nr_parts = ARRAY_SIZE(gumstix_partitions), | ||
| 69 | .width = 2, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct platform_device gumstix_flash_device = { | ||
| 73 | .name = "pxa2xx-flash", | ||
| 74 | .id = 0, | ||
| 75 | .dev = { | ||
| 76 | .platform_data = &gumstix_flash_data, | ||
| 77 | }, | ||
| 78 | .resource = &flash_resource, | ||
| 79 | .num_resources = 1, | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct platform_device *devices[] __initdata = { | ||
| 83 | &gumstix_flash_device, | ||
| 84 | }; | ||
| 85 | |||
| 86 | #ifdef CONFIG_MMC_PXA | ||
| 87 | static struct pxamci_platform_data gumstix_mci_platform_data; | ||
| 88 | |||
| 89 | static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int, | ||
| 90 | void *data) | ||
| 91 | { | ||
| 92 | pxa_gpio_mode(GPIO6_MMCCLK_MD); | ||
| 93 | pxa_gpio_mode(GPIO53_MMCCLK_MD); | ||
| 94 | pxa_gpio_mode(GPIO8_MMCCS0_MD); | ||
| 95 | |||
| 96 | return 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | static struct pxamci_platform_data gumstix_mci_platform_data = { | ||
| 100 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
| 101 | .init = gumstix_mci_init, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static void __init gumstix_mmc_init(void) | ||
| 105 | { | ||
| 106 | pxa_set_mci_info(&gumstix_mci_platform_data); | ||
| 107 | } | ||
| 108 | #else | ||
| 109 | static void __init gumstix_mmc_init(void) | ||
| 110 | { | ||
| 111 | printk(KERN_INFO "Gumstix mmc disabled\n"); | ||
| 112 | } | ||
| 113 | #endif | ||
| 114 | |||
| 115 | #ifdef CONFIG_USB_GADGET_PXA2XX | ||
| 116 | static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { | ||
| 117 | .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, | ||
| 118 | .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static void __init gumstix_udc_init(void) | ||
| 122 | { | ||
| 123 | pxa_set_udc_info(&gumstix_udc_info); | ||
| 124 | } | ||
| 125 | #else | ||
| 126 | static void gumstix_udc_init(void) | ||
| 127 | { | ||
| 128 | printk(KERN_INFO "Gumstix udc is disabled\n"); | ||
| 129 | } | ||
| 130 | #endif | ||
| 131 | |||
| 132 | static void __init gumstix_init(void) | ||
| 133 | { | ||
| 134 | gumstix_udc_init(); | ||
| 135 | gumstix_mmc_init(); | ||
| 136 | (void) platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 137 | } | ||
| 138 | |||
| 139 | MACHINE_START(GUMSTIX, "Gumstix") | ||
| 140 | .phys_io = 0x40000000, | ||
| 141 | .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ | ||
| 142 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 143 | .map_io = pxa_map_io, | ||
| 144 | .init_irq = pxa25x_init_irq, | ||
| 145 | .timer = &pxa_timer, | ||
| 146 | .init_machine = gumstix_init, | ||
| 147 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 0a9434432c55..2637633f9166 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
| 33 | 33 | ||
| 34 | #include <asm/arch/pxa-regs.h> | 34 | #include <asm/arch/pxa-regs.h> |
| 35 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 35 | #include <asm/arch/idp.h> | 36 | #include <asm/arch/idp.h> |
| 36 | #include <asm/arch/pxafb.h> | 37 | #include <asm/arch/pxafb.h> |
| 37 | #include <asm/arch/bitfield.h> | 38 | #include <asm/arch/bitfield.h> |
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 36c6a68beca2..a9a0c3fab159 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/irq.c | 2 | * linux/arch/arm/mach-pxa/irq.c |
| 3 | * | 3 | * |
| 4 | * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. | 4 | * Generic PXA IRQ handling |
| 5 | * | 5 | * |
| 6 | * Author: Nicolas Pitre | 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 | 7 | * Created: Jun 15, 2001 |
| @@ -21,308 +21,58 @@ | |||
| 21 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
| 22 | #include <asm/mach/irq.h> | 22 | #include <asm/mach/irq.h> |
| 23 | #include <asm/arch/pxa-regs.h> | 23 | #include <asm/arch/pxa-regs.h> |
| 24 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 24 | 25 | ||
| 25 | #include "generic.h" | 26 | #include "generic.h" |
| 26 | 27 | ||
| 28 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) | ||
| 29 | #define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR)) | ||
| 30 | #define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR)) | ||
| 27 | 31 | ||
| 28 | /* | 32 | /* |
| 29 | * This is for peripheral IRQs internal to the PXA chip. | 33 | * This is for peripheral IRQs internal to the PXA chip. |
| 30 | */ | 34 | */ |
| 31 | 35 | ||
| 32 | static void pxa_mask_low_irq(unsigned int irq) | 36 | static int pxa_internal_irq_nr; |
| 37 | |||
| 38 | static void pxa_mask_irq(unsigned int irq) | ||
| 33 | { | 39 | { |
| 34 | ICMR &= ~(1 << irq); | 40 | _ICMR(irq) &= ~(1 << IRQ_BIT(irq)); |
| 35 | } | 41 | } |
| 36 | 42 | ||
| 37 | static void pxa_unmask_low_irq(unsigned int irq) | 43 | static void pxa_unmask_irq(unsigned int irq) |
| 38 | { | 44 | { |
| 39 | ICMR |= (1 << irq); | 45 | _ICMR(irq) |= 1 << IRQ_BIT(irq); |
| 40 | } | 46 | } |
| 41 | 47 | ||
| 42 | static struct irq_chip pxa_internal_chip_low = { | 48 | static struct irq_chip pxa_internal_irq_chip = { |
| 43 | .name = "SC", | 49 | .name = "SC", |
| 44 | .ack = pxa_mask_low_irq, | 50 | .ack = pxa_mask_irq, |
| 45 | .mask = pxa_mask_low_irq, | 51 | .mask = pxa_mask_irq, |
| 46 | .unmask = pxa_unmask_low_irq, | 52 | .unmask = pxa_unmask_irq, |
| 47 | }; | 53 | }; |
| 48 | 54 | ||
| 49 | void __init pxa_init_irq_low(void) | 55 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
| 50 | { | 56 | { |
| 51 | int irq; | 57 | int irq; |
| 52 | 58 | ||
| 53 | /* disable all IRQs */ | 59 | pxa_internal_irq_nr = irq_nr; |
| 54 | ICMR = 0; | ||
| 55 | 60 | ||
| 56 | /* all IRQs are IRQ, not FIQ */ | 61 | for (irq = 0; irq < irq_nr; irq += 32) { |
| 57 | ICLR = 0; | 62 | _ICMR(irq) = 0; /* disable all IRQs */ |
| 63 | _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ | ||
| 64 | } | ||
| 58 | 65 | ||
| 59 | /* only unmasked interrupts kick us out of idle */ | 66 | /* only unmasked interrupts kick us out of idle */ |
| 60 | ICCR = 1; | 67 | ICCR = 1; |
| 61 | 68 | ||
| 62 | for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { | 69 | for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { |
| 63 | set_irq_chip(irq, &pxa_internal_chip_low); | 70 | set_irq_chip(irq, &pxa_internal_irq_chip); |
| 64 | set_irq_handler(irq, handle_level_irq); | ||
| 65 | set_irq_flags(irq, IRQF_VALID); | ||
| 66 | } | ||
| 67 | } | ||
| 68 | |||
| 69 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * This is for the second set of internal IRQs as found on the PXA27x. | ||
| 73 | */ | ||
| 74 | |||
| 75 | static void pxa_mask_high_irq(unsigned int irq) | ||
| 76 | { | ||
| 77 | ICMR2 &= ~(1 << (irq - 32)); | ||
| 78 | } | ||
| 79 | |||
| 80 | static void pxa_unmask_high_irq(unsigned int irq) | ||
| 81 | { | ||
| 82 | ICMR2 |= (1 << (irq - 32)); | ||
| 83 | } | ||
| 84 | |||
| 85 | static struct irq_chip pxa_internal_chip_high = { | ||
| 86 | .name = "SC-hi", | ||
| 87 | .ack = pxa_mask_high_irq, | ||
| 88 | .mask = pxa_mask_high_irq, | ||
| 89 | .unmask = pxa_unmask_high_irq, | ||
| 90 | }; | ||
| 91 | |||
| 92 | void __init pxa_init_irq_high(void) | ||
| 93 | { | ||
| 94 | int irq; | ||
| 95 | |||
| 96 | ICMR2 = 0; | ||
| 97 | ICLR2 = 0; | ||
| 98 | |||
| 99 | for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { | ||
| 100 | set_irq_chip(irq, &pxa_internal_chip_high); | ||
| 101 | set_irq_handler(irq, handle_level_irq); | 71 | set_irq_handler(irq, handle_level_irq); |
| 102 | set_irq_flags(irq, IRQF_VALID); | 72 | set_irq_flags(irq, IRQF_VALID); |
| 103 | } | 73 | } |
| 104 | } | ||
| 105 | #endif | ||
| 106 | |||
| 107 | /* | ||
| 108 | * PXA GPIO edge detection for IRQs: | ||
| 109 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | ||
| 110 | * Use this instead of directly setting GRER/GFER. | ||
| 111 | */ | ||
| 112 | |||
| 113 | static long GPIO_IRQ_rising_edge[4]; | ||
| 114 | static long GPIO_IRQ_falling_edge[4]; | ||
| 115 | static long GPIO_IRQ_mask[4]; | ||
| 116 | |||
| 117 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
| 118 | { | ||
| 119 | int gpio, idx; | ||
| 120 | |||
| 121 | gpio = IRQ_TO_GPIO(irq); | ||
| 122 | idx = gpio >> 5; | ||
| 123 | |||
| 124 | if (type == IRQT_PROBE) { | ||
| 125 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
| 126 | GPIOs set to alternate function or to output during probe */ | ||
| 127 | if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & | ||
| 128 | GPIO_bit(gpio)) | ||
| 129 | return 0; | ||
| 130 | if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) | ||
| 131 | return 0; | ||
| 132 | type = __IRQT_RISEDGE | __IRQT_FALEDGE; | ||
| 133 | } | ||
| 134 | |||
| 135 | /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ | ||
| 136 | |||
| 137 | pxa_gpio_mode(gpio | GPIO_IN); | ||
| 138 | |||
| 139 | if (type & __IRQT_RISEDGE) { | ||
| 140 | /* printk("rising "); */ | ||
| 141 | __set_bit (gpio, GPIO_IRQ_rising_edge); | ||
| 142 | } else { | ||
| 143 | __clear_bit (gpio, GPIO_IRQ_rising_edge); | ||
| 144 | } | ||
| 145 | |||
| 146 | if (type & __IRQT_FALEDGE) { | ||
| 147 | /* printk("falling "); */ | ||
| 148 | __set_bit (gpio, GPIO_IRQ_falling_edge); | ||
| 149 | } else { | ||
| 150 | __clear_bit (gpio, GPIO_IRQ_falling_edge); | ||
| 151 | } | ||
| 152 | |||
| 153 | /* printk("edges\n"); */ | ||
| 154 | |||
| 155 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 156 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 157 | return 0; | ||
| 158 | } | ||
| 159 | |||
| 160 | /* | ||
| 161 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | ||
| 162 | */ | ||
| 163 | |||
| 164 | static void pxa_ack_low_gpio(unsigned int irq) | ||
| 165 | { | ||
| 166 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
| 167 | } | ||
| 168 | |||
| 169 | static struct irq_chip pxa_low_gpio_chip = { | ||
| 170 | .name = "GPIO-l", | ||
| 171 | .ack = pxa_ack_low_gpio, | ||
| 172 | .mask = pxa_mask_low_irq, | ||
| 173 | .unmask = pxa_unmask_low_irq, | ||
| 174 | .set_type = pxa_gpio_irq_type, | ||
| 175 | }; | ||
| 176 | |||
| 177 | /* | ||
| 178 | * Demux handler for GPIO>=2 edge detect interrupts | ||
| 179 | */ | ||
| 180 | |||
| 181 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
| 182 | { | ||
| 183 | unsigned int mask; | ||
| 184 | int loop; | ||
| 185 | |||
| 186 | do { | ||
| 187 | loop = 0; | ||
| 188 | |||
| 189 | mask = GEDR0 & GPIO_IRQ_mask[0] & ~3; | ||
| 190 | if (mask) { | ||
| 191 | GEDR0 = mask; | ||
| 192 | irq = IRQ_GPIO(2); | ||
| 193 | desc = irq_desc + irq; | ||
| 194 | mask >>= 2; | ||
| 195 | do { | ||
| 196 | if (mask & 1) | ||
| 197 | desc_handle_irq(irq, desc); | ||
| 198 | irq++; | ||
| 199 | desc++; | ||
| 200 | mask >>= 1; | ||
| 201 | } while (mask); | ||
| 202 | loop = 1; | ||
| 203 | } | ||
| 204 | |||
| 205 | mask = GEDR1 & GPIO_IRQ_mask[1]; | ||
| 206 | if (mask) { | ||
| 207 | GEDR1 = mask; | ||
| 208 | irq = IRQ_GPIO(32); | ||
| 209 | desc = irq_desc + irq; | ||
| 210 | do { | ||
| 211 | if (mask & 1) | ||
| 212 | desc_handle_irq(irq, desc); | ||
| 213 | irq++; | ||
| 214 | desc++; | ||
| 215 | mask >>= 1; | ||
| 216 | } while (mask); | ||
| 217 | loop = 1; | ||
| 218 | } | ||
| 219 | |||
| 220 | mask = GEDR2 & GPIO_IRQ_mask[2]; | ||
| 221 | if (mask) { | ||
| 222 | GEDR2 = mask; | ||
| 223 | irq = IRQ_GPIO(64); | ||
| 224 | desc = irq_desc + irq; | ||
| 225 | do { | ||
| 226 | if (mask & 1) | ||
| 227 | desc_handle_irq(irq, desc); | ||
| 228 | irq++; | ||
| 229 | desc++; | ||
| 230 | mask >>= 1; | ||
| 231 | } while (mask); | ||
| 232 | loop = 1; | ||
| 233 | } | ||
| 234 | |||
| 235 | mask = GEDR3 & GPIO_IRQ_mask[3]; | ||
| 236 | if (mask) { | ||
| 237 | GEDR3 = mask; | ||
| 238 | irq = IRQ_GPIO(96); | ||
| 239 | desc = irq_desc + irq; | ||
| 240 | do { | ||
| 241 | if (mask & 1) | ||
| 242 | desc_handle_irq(irq, desc); | ||
| 243 | irq++; | ||
| 244 | desc++; | ||
| 245 | mask >>= 1; | ||
| 246 | } while (mask); | ||
| 247 | loop = 1; | ||
| 248 | } | ||
| 249 | } while (loop); | ||
| 250 | } | ||
| 251 | |||
| 252 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
| 253 | { | ||
| 254 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 255 | GEDR(gpio) = GPIO_bit(gpio); | ||
| 256 | } | ||
| 257 | |||
| 258 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
| 259 | { | ||
| 260 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 261 | __clear_bit(gpio, GPIO_IRQ_mask); | ||
| 262 | GRER(gpio) &= ~GPIO_bit(gpio); | ||
| 263 | GFER(gpio) &= ~GPIO_bit(gpio); | ||
| 264 | } | ||
| 265 | |||
| 266 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
| 267 | { | ||
| 268 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 269 | int idx = gpio >> 5; | ||
| 270 | __set_bit(gpio, GPIO_IRQ_mask); | ||
| 271 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 272 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 273 | } | ||
| 274 | |||
| 275 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
| 276 | .name = "GPIO", | ||
| 277 | .ack = pxa_ack_muxed_gpio, | ||
| 278 | .mask = pxa_mask_muxed_gpio, | ||
| 279 | .unmask = pxa_unmask_muxed_gpio, | ||
| 280 | .set_type = pxa_gpio_irq_type, | ||
| 281 | }; | ||
| 282 | |||
| 283 | void __init pxa_init_irq_gpio(int gpio_nr) | ||
| 284 | { | ||
| 285 | int irq, i; | ||
| 286 | |||
| 287 | pxa_last_gpio = gpio_nr - 1; | ||
| 288 | |||
| 289 | /* clear all GPIO edge detects */ | ||
| 290 | for (i = 0; i < gpio_nr; i += 32) { | ||
| 291 | GFER(i) = 0; | ||
| 292 | GRER(i) = 0; | ||
| 293 | GEDR(i) = GEDR(i); | ||
| 294 | } | ||
| 295 | |||
| 296 | /* GPIO 0 and 1 must have their mask bit always set */ | ||
| 297 | GPIO_IRQ_mask[0] = 3; | ||
| 298 | |||
| 299 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
| 300 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
| 301 | set_irq_handler(irq, handle_edge_irq); | ||
| 302 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 303 | } | ||
| 304 | 74 | ||
| 305 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { | 75 | pxa_internal_irq_chip.set_wake = fn; |
| 306 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
| 307 | set_irq_handler(irq, handle_edge_irq); | ||
| 308 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 309 | } | ||
| 310 | |||
| 311 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
| 312 | set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); | ||
| 313 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | ||
| 314 | |||
| 315 | pxa_init_gpio(gpio_nr); | ||
| 316 | } | ||
| 317 | |||
| 318 | void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) | ||
| 319 | { | ||
| 320 | pxa_internal_chip_low.set_wake = set_wake; | ||
| 321 | #ifdef CONFIG_PXA27x | ||
| 322 | pxa_internal_chip_high.set_wake = set_wake; | ||
| 323 | #endif | ||
| 324 | pxa_low_gpio_chip.set_wake = set_wake; | ||
| 325 | pxa_muxed_gpio_chip.set_wake = set_wake; | ||
| 326 | } | 76 | } |
| 327 | 77 | ||
| 328 | #ifdef CONFIG_PM | 78 | #ifdef CONFIG_PM |
| @@ -330,19 +80,11 @@ static unsigned long saved_icmr[2]; | |||
| 330 | 80 | ||
| 331 | static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | 81 | static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) |
| 332 | { | 82 | { |
| 333 | switch (dev->id) { | 83 | int i, irq = PXA_IRQ(0); |
| 334 | case 0: | 84 | |
| 335 | saved_icmr[0] = ICMR; | 85 | for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { |
| 336 | ICMR = 0; | 86 | saved_icmr[i] = _ICMR(irq); |
| 337 | break; | 87 | _ICMR(irq) = 0; |
| 338 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 339 | case 1: | ||
| 340 | saved_icmr[1] = ICMR2; | ||
| 341 | ICMR2 = 0; | ||
| 342 | break; | ||
| 343 | #endif | ||
| 344 | default: | ||
| 345 | return -EINVAL; | ||
| 346 | } | 88 | } |
| 347 | 89 | ||
| 348 | return 0; | 90 | return 0; |
| @@ -350,22 +92,14 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | |||
| 350 | 92 | ||
| 351 | static int pxa_irq_resume(struct sys_device *dev) | 93 | static int pxa_irq_resume(struct sys_device *dev) |
| 352 | { | 94 | { |
| 353 | switch (dev->id) { | 95 | int i, irq = PXA_IRQ(0); |
| 354 | case 0: | 96 | |
| 355 | ICMR = saved_icmr[0]; | 97 | for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { |
| 356 | ICLR = 0; | 98 | _ICMR(irq) = saved_icmr[i]; |
| 357 | ICCR = 1; | 99 | _ICLR(irq) = 0; |
| 358 | break; | ||
| 359 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 360 | case 1: | ||
| 361 | ICMR2 = saved_icmr[1]; | ||
| 362 | ICLR2 = 0; | ||
| 363 | break; | ||
| 364 | #endif | ||
| 365 | default: | ||
| 366 | return -EINVAL; | ||
| 367 | } | 100 | } |
| 368 | 101 | ||
| 102 | ICCR = 1; | ||
| 369 | return 0; | 103 | return 0; |
| 370 | } | 104 | } |
| 371 | #else | 105 | #else |
diff --git a/arch/arm/mach-pxa/leds-trizeps4.c b/arch/arm/mach-pxa/leds-trizeps4.c index 2271d20ffeda..21880daabafe 100644 --- a/arch/arm/mach-pxa/leds-trizeps4.c +++ b/arch/arm/mach-pxa/leds-trizeps4.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <asm/leds.h> | 18 | #include <asm/leds.h> |
| 19 | 19 | ||
| 20 | #include <asm/arch/pxa-regs.h> | 20 | #include <asm/arch/pxa-regs.h> |
| 21 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 21 | #include <asm/arch/trizeps4.h> | 22 | #include <asm/arch/trizeps4.h> |
| 22 | 23 | ||
| 23 | #include "leds.h" | 24 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 0a4b54c21314..03396063b561 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
| @@ -37,12 +37,11 @@ | |||
| 37 | #include <asm/arch/gpio.h> | 37 | #include <asm/arch/gpio.h> |
| 38 | #include <asm/arch/pxafb.h> | 38 | #include <asm/arch/pxafb.h> |
| 39 | #include <asm/arch/ssp.h> | 39 | #include <asm/arch/ssp.h> |
| 40 | #include <asm/arch/pxa27x_keypad.h> | ||
| 40 | #include <asm/arch/littleton.h> | 41 | #include <asm/arch/littleton.h> |
| 41 | 42 | ||
| 42 | #include "generic.h" | 43 | #include "generic.h" |
| 43 | 44 | ||
| 44 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
| 45 | |||
| 46 | /* Littleton MFP configurations */ | 45 | /* Littleton MFP configurations */ |
| 47 | static mfp_cfg_t littleton_mfp_cfg[] __initdata = { | 46 | static mfp_cfg_t littleton_mfp_cfg[] __initdata = { |
| 48 | /* LCD */ | 47 | /* LCD */ |
| @@ -76,6 +75,21 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = { | |||
| 76 | 75 | ||
| 77 | /* Debug Ethernet */ | 76 | /* Debug Ethernet */ |
| 78 | GPIO90_GPIO, | 77 | GPIO90_GPIO, |
| 78 | |||
| 79 | /* Keypad */ | ||
| 80 | GPIO107_KP_DKIN_0, | ||
| 81 | GPIO108_KP_DKIN_1, | ||
| 82 | GPIO115_KP_MKIN_0, | ||
| 83 | GPIO116_KP_MKIN_1, | ||
| 84 | GPIO117_KP_MKIN_2, | ||
| 85 | GPIO118_KP_MKIN_3, | ||
| 86 | GPIO119_KP_MKIN_4, | ||
| 87 | GPIO120_KP_MKIN_5, | ||
| 88 | GPIO121_KP_MKOUT_0, | ||
| 89 | GPIO122_KP_MKOUT_1, | ||
| 90 | GPIO123_KP_MKOUT_2, | ||
| 91 | GPIO124_KP_MKOUT_3, | ||
| 92 | GPIO125_KP_MKOUT_4, | ||
| 79 | }; | 93 | }; |
| 80 | 94 | ||
| 81 | static struct resource smc91x_resources[] = { | 95 | static struct resource smc91x_resources[] = { |
| @@ -300,6 +314,54 @@ static void littleton_init_lcd(void) | |||
| 300 | static inline void littleton_init_lcd(void) {}; | 314 | static inline void littleton_init_lcd(void) {}; |
| 301 | #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */ | 315 | #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */ |
| 302 | 316 | ||
| 317 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES) | ||
| 318 | static unsigned int littleton_matrix_key_map[] = { | ||
| 319 | /* KEY(row, col, key_code) */ | ||
| 320 | KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), | ||
| 321 | KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7), | ||
| 322 | KEY(1, 2, KEY_8), KEY(2, 2, KEY_9), | ||
| 323 | |||
| 324 | KEY(0, 3, KEY_KPASTERISK), /* * */ | ||
| 325 | KEY(2, 3, KEY_KPDOT), /* # */ | ||
| 326 | |||
| 327 | KEY(5, 4, KEY_ENTER), | ||
| 328 | |||
| 329 | KEY(5, 0, KEY_UP), | ||
| 330 | KEY(5, 1, KEY_DOWN), | ||
| 331 | KEY(5, 2, KEY_LEFT), | ||
| 332 | KEY(5, 3, KEY_RIGHT), | ||
| 333 | KEY(3, 2, KEY_HOME), | ||
| 334 | KEY(4, 1, KEY_END), | ||
| 335 | KEY(3, 3, KEY_BACK), | ||
| 336 | |||
| 337 | KEY(4, 0, KEY_SEND), | ||
| 338 | KEY(4, 2, KEY_VOLUMEUP), | ||
| 339 | KEY(4, 3, KEY_VOLUMEDOWN), | ||
| 340 | |||
| 341 | KEY(3, 0, KEY_F22), /* soft1 */ | ||
| 342 | KEY(3, 1, KEY_F23), /* soft2 */ | ||
| 343 | }; | ||
| 344 | |||
| 345 | static struct pxa27x_keypad_platform_data littleton_keypad_info = { | ||
| 346 | .matrix_key_rows = 6, | ||
| 347 | .matrix_key_cols = 5, | ||
| 348 | .matrix_key_map = littleton_matrix_key_map, | ||
| 349 | .matrix_key_map_size = ARRAY_SIZE(littleton_matrix_key_map), | ||
| 350 | |||
| 351 | .enable_rotary0 = 1, | ||
| 352 | .rotary0_up_key = KEY_UP, | ||
| 353 | .rotary0_down_key = KEY_DOWN, | ||
| 354 | |||
| 355 | .debounce_interval = 30, | ||
| 356 | }; | ||
| 357 | static void __init littleton_init_keypad(void) | ||
| 358 | { | ||
| 359 | pxa_set_keypad_info(&littleton_keypad_info); | ||
| 360 | } | ||
| 361 | #else | ||
| 362 | static inline void littleton_init_keypad(void) {} | ||
| 363 | #endif | ||
| 364 | |||
| 303 | static void __init littleton_init(void) | 365 | static void __init littleton_init(void) |
| 304 | { | 366 | { |
| 305 | /* initialize MFP configurations */ | 367 | /* initialize MFP configurations */ |
| @@ -312,6 +374,7 @@ static void __init littleton_init(void) | |||
| 312 | platform_device_register(&smc91x_device); | 374 | platform_device_register(&smc91x_device); |
| 313 | 375 | ||
| 314 | littleton_init_lcd(); | 376 | littleton_init_lcd(); |
| 377 | littleton_init_keypad(); | ||
| 315 | } | 378 | } |
| 316 | 379 | ||
| 317 | MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") | 380 | MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index afa62ffe3ad5..a20e4b1649d6 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #include <asm/arch/pxa-regs.h> | 40 | #include <asm/arch/pxa-regs.h> |
| 41 | #include <asm/arch/pxa2xx-regs.h> | 41 | #include <asm/arch/pxa2xx-regs.h> |
| 42 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 42 | #include <asm/arch/lpd270.h> | 43 | #include <asm/arch/lpd270.h> |
| 43 | #include <asm/arch/audio.h> | 44 | #include <asm/arch/audio.h> |
| 44 | #include <asm/arch/pxafb.h> | 45 | #include <asm/arch/pxafb.h> |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index e7ae4bb3e361..ca209c443f34 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | 42 | ||
| 43 | #include <asm/arch/pxa-regs.h> | 43 | #include <asm/arch/pxa-regs.h> |
| 44 | #include <asm/arch/pxa2xx-regs.h> | 44 | #include <asm/arch/pxa2xx-regs.h> |
| 45 | #include <asm/arch/mfp-pxa25x.h> | ||
| 45 | #include <asm/arch/lubbock.h> | 46 | #include <asm/arch/lubbock.h> |
| 46 | #include <asm/arch/udc.h> | 47 | #include <asm/arch/udc.h> |
| 47 | #include <asm/arch/irda.h> | 48 | #include <asm/arch/irda.h> |
| @@ -51,6 +52,40 @@ | |||
| 51 | #include "generic.h" | 52 | #include "generic.h" |
| 52 | #include "devices.h" | 53 | #include "devices.h" |
| 53 | 54 | ||
| 55 | static unsigned long lubbock_pin_config[] __initdata = { | ||
| 56 | GPIO15_nCS_1, /* CS1 - Flash */ | ||
| 57 | GPIO79_nCS_3, /* CS3 - SMC ethernet */ | ||
| 58 | |||
| 59 | /* SSP data pins */ | ||
| 60 | GPIO23_SSP1_SCLK, | ||
| 61 | GPIO25_SSP1_TXD, | ||
| 62 | GPIO26_SSP1_RXD, | ||
| 63 | |||
| 64 | /* BTUART */ | ||
| 65 | GPIO42_BTUART_RXD, | ||
| 66 | GPIO43_BTUART_TXD, | ||
| 67 | GPIO44_BTUART_CTS, | ||
| 68 | GPIO45_BTUART_RTS, | ||
| 69 | |||
| 70 | /* PC Card */ | ||
| 71 | GPIO48_nPOE, | ||
| 72 | GPIO49_nPWE, | ||
| 73 | GPIO50_nPIOR, | ||
| 74 | GPIO51_nPIOW, | ||
| 75 | GPIO52_nPCE_1, | ||
| 76 | GPIO53_nPCE_2, | ||
| 77 | GPIO54_nPSKTSEL, | ||
| 78 | GPIO55_nPREG, | ||
| 79 | GPIO56_nPWAIT, | ||
| 80 | GPIO57_nIOIS16, | ||
| 81 | |||
| 82 | /* MMC */ | ||
| 83 | GPIO6_MMC_CLK, | ||
| 84 | GPIO8_MMC_CS0, | ||
| 85 | |||
| 86 | /* wakeup */ | ||
| 87 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, | ||
| 88 | }; | ||
| 54 | 89 | ||
| 55 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) | 90 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) |
| 56 | 91 | ||
| @@ -186,26 +221,6 @@ static struct platform_device sa1111_device = { | |||
| 186 | .resource = sa1111_resources, | 221 | .resource = sa1111_resources, |
| 187 | }; | 222 | }; |
| 188 | 223 | ||
| 189 | static struct resource smc91x_resources[] = { | ||
| 190 | [0] = { | ||
| 191 | .name = "smc91x-regs", | ||
| 192 | .start = 0x0c000c00, | ||
| 193 | .end = 0x0c0fffff, | ||
| 194 | .flags = IORESOURCE_MEM, | ||
| 195 | }, | ||
| 196 | [1] = { | ||
| 197 | .start = LUBBOCK_ETH_IRQ, | ||
| 198 | .end = LUBBOCK_ETH_IRQ, | ||
| 199 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 200 | }, | ||
| 201 | [2] = { | ||
| 202 | .name = "smc91x-attrib", | ||
| 203 | .start = 0x0e000000, | ||
| 204 | .end = 0x0e0fffff, | ||
| 205 | .flags = IORESOURCE_MEM, | ||
| 206 | }, | ||
| 207 | }; | ||
| 208 | |||
| 209 | /* ADS7846 is connected through SSP ... and if your board has J5 populated, | 224 | /* ADS7846 is connected through SSP ... and if your board has J5 populated, |
| 210 | * you can select it to replace the ucb1400 by switching the touchscreen cable | 225 | * you can select it to replace the ucb1400 by switching the touchscreen cable |
| 211 | * (to J5) and poking board registers (as done below). Else it's only useful | 226 | * (to J5) and poking board registers (as done below). Else it's only useful |
| @@ -261,6 +276,26 @@ static struct spi_board_info spi_board_info[] __initdata = { { | |||
| 261 | }, | 276 | }, |
| 262 | }; | 277 | }; |
| 263 | 278 | ||
| 279 | static struct resource smc91x_resources[] = { | ||
| 280 | [0] = { | ||
| 281 | .name = "smc91x-regs", | ||
| 282 | .start = 0x0c000c00, | ||
| 283 | .end = 0x0c0fffff, | ||
| 284 | .flags = IORESOURCE_MEM, | ||
| 285 | }, | ||
| 286 | [1] = { | ||
| 287 | .start = LUBBOCK_ETH_IRQ, | ||
| 288 | .end = LUBBOCK_ETH_IRQ, | ||
| 289 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 290 | }, | ||
| 291 | [2] = { | ||
| 292 | .name = "smc91x-attrib", | ||
| 293 | .start = 0x0e000000, | ||
| 294 | .end = 0x0e0fffff, | ||
| 295 | .flags = IORESOURCE_MEM, | ||
| 296 | }, | ||
| 297 | }; | ||
| 298 | |||
| 264 | static struct platform_device smc91x_device = { | 299 | static struct platform_device smc91x_device = { |
| 265 | .name = "smc91x", | 300 | .name = "smc91x", |
| 266 | .id = -1, | 301 | .id = -1, |
| @@ -404,10 +439,6 @@ static int lubbock_mci_init(struct device *dev, | |||
| 404 | irq_handler_t detect_int, | 439 | irq_handler_t detect_int, |
| 405 | void *data) | 440 | void *data) |
| 406 | { | 441 | { |
| 407 | /* setup GPIO for PXA25x MMC controller */ | ||
| 408 | pxa_gpio_mode(GPIO6_MMCCLK_MD); | ||
| 409 | pxa_gpio_mode(GPIO8_MMCCS0_MD); | ||
| 410 | |||
| 411 | /* detect card insert/eject */ | 442 | /* detect card insert/eject */ |
| 412 | mmc_detect_int = detect_int; | 443 | mmc_detect_int = detect_int; |
| 413 | init_timer(&mmc_timer); | 444 | init_timer(&mmc_timer); |
| @@ -457,6 +488,8 @@ static void __init lubbock_init(void) | |||
| 457 | { | 488 | { |
| 458 | int flashboot = (LUB_CONF_SWITCHES & 1); | 489 | int flashboot = (LUB_CONF_SWITCHES & 1); |
| 459 | 490 | ||
| 491 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); | ||
| 492 | |||
| 460 | pxa_set_udc_info(&udc_info); | 493 | pxa_set_udc_info(&udc_info); |
| 461 | set_pxa_fb_info(&sharp_lm8v31); | 494 | set_pxa_fb_info(&sharp_lm8v31); |
| 462 | pxa_set_mci_info(&lubbock_mci_platform_data); | 495 | pxa_set_mci_info(&lubbock_mci_platform_data); |
| @@ -489,46 +522,6 @@ static void __init lubbock_map_io(void) | |||
| 489 | pxa_map_io(); | 522 | pxa_map_io(); |
| 490 | iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); | 523 | iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); |
| 491 | 524 | ||
| 492 | /* SSP data pins */ | ||
| 493 | pxa_gpio_mode(GPIO23_SCLK_MD); | ||
| 494 | pxa_gpio_mode(GPIO25_STXD_MD); | ||
| 495 | pxa_gpio_mode(GPIO26_SRXD_MD); | ||
| 496 | |||
| 497 | /* This enables the BTUART */ | ||
| 498 | pxa_gpio_mode(GPIO42_BTRXD_MD); | ||
| 499 | pxa_gpio_mode(GPIO43_BTTXD_MD); | ||
| 500 | pxa_gpio_mode(GPIO44_BTCTS_MD); | ||
| 501 | pxa_gpio_mode(GPIO45_BTRTS_MD); | ||
| 502 | |||
| 503 | GPSR(GPIO48_nPOE) = | ||
| 504 | GPIO_bit(GPIO48_nPOE) | | ||
| 505 | GPIO_bit(GPIO49_nPWE) | | ||
| 506 | GPIO_bit(GPIO50_nPIOR) | | ||
| 507 | GPIO_bit(GPIO51_nPIOW) | | ||
| 508 | GPIO_bit(GPIO52_nPCE_1) | | ||
| 509 | GPIO_bit(GPIO53_nPCE_2); | ||
| 510 | |||
| 511 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
| 512 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
| 513 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
| 514 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
| 515 | pxa_gpio_mode(GPIO52_nPCE_1_MD); | ||
| 516 | pxa_gpio_mode(GPIO53_nPCE_2_MD); | ||
| 517 | pxa_gpio_mode(GPIO54_pSKTSEL_MD); | ||
| 518 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
| 519 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
| 520 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
| 521 | |||
| 522 | /* This is for the SMC chip select */ | ||
| 523 | pxa_gpio_mode(GPIO79_nCS_3_MD); | ||
| 524 | |||
| 525 | /* setup sleep mode values */ | ||
| 526 | PWER = 0x00000002; | ||
| 527 | PFER = 0x00000000; | ||
| 528 | PRER = 0x00000002; | ||
| 529 | PGSR0 = 0x00008000; | ||
| 530 | PGSR1 = 0x003F0202; | ||
| 531 | PGSR2 = 0x0001C000; | ||
| 532 | PCFR |= PCFR_OPDE; | 525 | PCFR |= PCFR_OPDE; |
| 533 | } | 526 | } |
| 534 | 527 | ||
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index d98ef7ada2f8..d70be75bd199 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
| @@ -16,24 +16,106 @@ | |||
| 16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/delay.h> | ||
| 19 | #include <linux/gpio_keys.h> | 20 | #include <linux/gpio_keys.h> |
| 20 | #include <linux/input.h> | 21 | #include <linux/input.h> |
| 22 | #include <linux/mfd/htc-egpio.h> | ||
| 23 | #include <linux/mfd/htc-pasic3.h> | ||
| 21 | #include <linux/mtd/mtd.h> | 24 | #include <linux/mtd/mtd.h> |
| 22 | #include <linux/mtd/map.h> | 25 | #include <linux/mtd/map.h> |
| 23 | #include <linux/mtd/physmap.h> | 26 | #include <linux/mtd/physmap.h> |
| 27 | #include <linux/pda_power.h> | ||
| 24 | 28 | ||
| 25 | #include <asm/gpio.h> | 29 | #include <asm/gpio.h> |
| 26 | #include <asm/hardware.h> | 30 | #include <asm/hardware.h> |
| 27 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 29 | #include <asm/arch/magician.h> | 33 | #include <asm/arch/magician.h> |
| 34 | #include <asm/arch/mfp-pxa27x.h> | ||
| 30 | #include <asm/arch/pxa-regs.h> | 35 | #include <asm/arch/pxa-regs.h> |
| 31 | #include <asm/arch/pxafb.h> | 36 | #include <asm/arch/pxafb.h> |
| 37 | #include <asm/arch/i2c.h> | ||
| 38 | #include <asm/arch/mmc.h> | ||
| 32 | #include <asm/arch/irda.h> | 39 | #include <asm/arch/irda.h> |
| 33 | #include <asm/arch/ohci.h> | 40 | #include <asm/arch/ohci.h> |
| 34 | 41 | ||
| 35 | #include "generic.h" | 42 | #include "generic.h" |
| 36 | 43 | ||
| 44 | static unsigned long magician_pin_config[] = { | ||
| 45 | |||
| 46 | /* SDRAM and Static Memory I/O Signals */ | ||
| 47 | GPIO20_nSDCS_2, | ||
| 48 | GPIO21_nSDCS_3, | ||
| 49 | GPIO15_nCS_1, | ||
| 50 | GPIO78_nCS_2, /* PASIC3 */ | ||
| 51 | GPIO79_nCS_3, /* EGPIO CPLD */ | ||
| 52 | GPIO80_nCS_4, | ||
| 53 | GPIO33_nCS_5, | ||
| 54 | |||
| 55 | /* I2C */ | ||
| 56 | GPIO117_I2C_SCL, | ||
| 57 | GPIO118_I2C_SDA, | ||
| 58 | |||
| 59 | /* PWM 0 */ | ||
| 60 | GPIO16_PWM0_OUT, | ||
| 61 | |||
| 62 | /* I2S */ | ||
| 63 | GPIO28_I2S_BITCLK_OUT, | ||
| 64 | GPIO29_I2S_SDATA_IN, | ||
| 65 | GPIO31_I2S_SYNC, | ||
| 66 | GPIO113_I2S_SYSCLK, | ||
| 67 | |||
| 68 | /* SSP 2 */ | ||
| 69 | GPIO19_SSP2_SCLK, | ||
| 70 | GPIO14_SSP2_SFRM, | ||
| 71 | GPIO89_SSP2_TXD, | ||
| 72 | GPIO88_SSP2_RXD, | ||
| 73 | |||
| 74 | /* MMC */ | ||
| 75 | GPIO32_MMC_CLK, | ||
| 76 | GPIO92_MMC_DAT_0, | ||
| 77 | GPIO109_MMC_DAT_1, | ||
| 78 | GPIO110_MMC_DAT_2, | ||
| 79 | GPIO111_MMC_DAT_3, | ||
| 80 | GPIO112_MMC_CMD, | ||
| 81 | |||
| 82 | /* LCD */ | ||
| 83 | GPIO58_LCD_LDD_0, | ||
| 84 | GPIO59_LCD_LDD_1, | ||
| 85 | GPIO60_LCD_LDD_2, | ||
| 86 | GPIO61_LCD_LDD_3, | ||
| 87 | GPIO62_LCD_LDD_4, | ||
| 88 | GPIO63_LCD_LDD_5, | ||
| 89 | GPIO64_LCD_LDD_6, | ||
| 90 | GPIO65_LCD_LDD_7, | ||
| 91 | GPIO66_LCD_LDD_8, | ||
| 92 | GPIO67_LCD_LDD_9, | ||
| 93 | GPIO68_LCD_LDD_10, | ||
| 94 | GPIO69_LCD_LDD_11, | ||
| 95 | GPIO70_LCD_LDD_12, | ||
| 96 | GPIO71_LCD_LDD_13, | ||
| 97 | GPIO72_LCD_LDD_14, | ||
| 98 | GPIO73_LCD_LDD_15, | ||
| 99 | GPIO74_LCD_FCLK, | ||
| 100 | GPIO75_LCD_LCLK, | ||
| 101 | GPIO76_LCD_PCLK, | ||
| 102 | GPIO77_LCD_BIAS, | ||
| 103 | |||
| 104 | /* QCI */ | ||
| 105 | GPIO12_CIF_DD_7, | ||
| 106 | GPIO17_CIF_DD_6, | ||
| 107 | GPIO50_CIF_DD_3, | ||
| 108 | GPIO51_CIF_DD_2, | ||
| 109 | GPIO52_CIF_DD_4, | ||
| 110 | GPIO53_CIF_MCLK, | ||
| 111 | GPIO54_CIF_PCLK, | ||
| 112 | GPIO55_CIF_DD_1, | ||
| 113 | GPIO81_CIF_DD_0, | ||
| 114 | GPIO82_CIF_DD_5, | ||
| 115 | GPIO84_CIF_FV, | ||
| 116 | GPIO85_CIF_LV, | ||
| 117 | }; | ||
| 118 | |||
| 37 | /* | 119 | /* |
| 38 | * IRDA | 120 | * IRDA |
| 39 | */ | 121 | */ |
| @@ -83,8 +165,64 @@ static struct platform_device gpio_keys = { | |||
| 83 | .id = -1, | 165 | .id = -1, |
| 84 | }; | 166 | }; |
| 85 | 167 | ||
| 168 | |||
| 169 | /* | ||
| 170 | * EGPIO (Xilinx CPLD) | ||
| 171 | * | ||
| 172 | * 7 32-bit aligned 8-bit registers: 3x output, 1x irq, 3x input | ||
| 173 | */ | ||
| 174 | |||
| 175 | static struct resource egpio_resources[] = { | ||
| 176 | [0] = { | ||
| 177 | .start = PXA_CS3_PHYS, | ||
| 178 | .end = PXA_CS3_PHYS + 0x20, | ||
| 179 | .flags = IORESOURCE_MEM, | ||
| 180 | }, | ||
| 181 | [1] = { | ||
| 182 | .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), | ||
| 183 | .end = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), | ||
| 184 | .flags = IORESOURCE_IRQ, | ||
| 185 | }, | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct htc_egpio_chip egpio_chips[] = { | ||
| 189 | [0] = { | ||
| 190 | .reg_start = 0, | ||
| 191 | .gpio_base = MAGICIAN_EGPIO(0, 0), | ||
| 192 | .num_gpios = 24, | ||
| 193 | .direction = HTC_EGPIO_OUTPUT, | ||
| 194 | .initial_values = 0x40, /* EGPIO_MAGICIAN_GSM_RESET */ | ||
| 195 | }, | ||
| 196 | [1] = { | ||
| 197 | .reg_start = 4, | ||
| 198 | .gpio_base = MAGICIAN_EGPIO(4, 0), | ||
| 199 | .num_gpios = 24, | ||
| 200 | .direction = HTC_EGPIO_INPUT, | ||
| 201 | }, | ||
| 202 | }; | ||
| 203 | |||
| 204 | static struct htc_egpio_platform_data egpio_info = { | ||
| 205 | .reg_width = 8, | ||
| 206 | .bus_width = 32, | ||
| 207 | .irq_base = IRQ_BOARD_START, | ||
| 208 | .num_irqs = 4, | ||
| 209 | .ack_register = 3, | ||
| 210 | .chip = egpio_chips, | ||
| 211 | .num_chips = ARRAY_SIZE(egpio_chips), | ||
| 212 | }; | ||
| 213 | |||
| 214 | static struct platform_device egpio = { | ||
| 215 | .name = "htc-egpio", | ||
| 216 | .id = -1, | ||
| 217 | .resource = egpio_resources, | ||
| 218 | .num_resources = ARRAY_SIZE(egpio_resources), | ||
| 219 | .dev = { | ||
| 220 | .platform_data = &egpio_info, | ||
| 221 | }, | ||
| 222 | }; | ||
| 223 | |||
| 86 | /* | 224 | /* |
| 87 | * LCD - Toppoly TD028STEB1 | 225 | * LCD - Toppoly TD028STEB1 or Samsung LTP280QV |
| 88 | */ | 226 | */ |
| 89 | 227 | ||
| 90 | static struct pxafb_mode_info toppoly_modes[] = { | 228 | static struct pxafb_mode_info toppoly_modes[] = { |
| @@ -103,12 +241,99 @@ static struct pxafb_mode_info toppoly_modes[] = { | |||
| 103 | }, | 241 | }, |
| 104 | }; | 242 | }; |
| 105 | 243 | ||
| 244 | static struct pxafb_mode_info samsung_modes[] = { | ||
| 245 | { | ||
| 246 | .pixclock = 96153, | ||
| 247 | .bpp = 16, | ||
| 248 | .xres = 240, | ||
| 249 | .yres = 320, | ||
| 250 | .hsync_len = 8, | ||
| 251 | .vsync_len = 4, | ||
| 252 | .left_margin = 9, | ||
| 253 | .upper_margin = 4, | ||
| 254 | .right_margin = 9, | ||
| 255 | .lower_margin = 4, | ||
| 256 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static void toppoly_lcd_power(int on, struct fb_var_screeninfo *si) | ||
| 261 | { | ||
| 262 | pr_debug("Toppoly LCD power\n"); | ||
| 263 | |||
| 264 | if (on) { | ||
| 265 | pr_debug("on\n"); | ||
| 266 | gpio_set_value(EGPIO_MAGICIAN_TOPPOLY_POWER, 1); | ||
| 267 | gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1); | ||
| 268 | udelay(2000); | ||
| 269 | gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1); | ||
| 270 | udelay(2000); | ||
| 271 | /* FIXME: enable LCDC here */ | ||
| 272 | udelay(2000); | ||
| 273 | gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1); | ||
| 274 | udelay(2000); | ||
| 275 | gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1); | ||
| 276 | } else { | ||
| 277 | pr_debug("off\n"); | ||
| 278 | msleep(15); | ||
| 279 | gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0); | ||
| 280 | udelay(500); | ||
| 281 | gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0); | ||
| 282 | udelay(1000); | ||
| 283 | gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0); | ||
| 284 | gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0); | ||
| 285 | } | ||
| 286 | } | ||
| 287 | |||
| 288 | static void samsung_lcd_power(int on, struct fb_var_screeninfo *si) | ||
| 289 | { | ||
| 290 | pr_debug("Samsung LCD power\n"); | ||
| 291 | |||
| 292 | if (on) { | ||
| 293 | pr_debug("on\n"); | ||
| 294 | if (system_rev < 3) | ||
| 295 | gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 1); | ||
| 296 | else | ||
| 297 | gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1); | ||
| 298 | mdelay(10); | ||
| 299 | gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1); | ||
| 300 | mdelay(10); | ||
| 301 | gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1); | ||
| 302 | mdelay(30); | ||
| 303 | gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1); | ||
| 304 | mdelay(10); | ||
| 305 | } else { | ||
| 306 | pr_debug("off\n"); | ||
| 307 | mdelay(10); | ||
| 308 | gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0); | ||
| 309 | mdelay(30); | ||
| 310 | gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0); | ||
| 311 | mdelay(10); | ||
| 312 | gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0); | ||
| 313 | mdelay(10); | ||
| 314 | if (system_rev < 3) | ||
| 315 | gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 0); | ||
| 316 | else | ||
| 317 | gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0); | ||
| 318 | } | ||
| 319 | } | ||
| 320 | |||
| 106 | static struct pxafb_mach_info toppoly_info = { | 321 | static struct pxafb_mach_info toppoly_info = { |
| 107 | .modes = toppoly_modes, | 322 | .modes = toppoly_modes, |
| 108 | .num_modes = 1, | 323 | .num_modes = 1, |
| 109 | .fixed_modes = 1, | 324 | .fixed_modes = 1, |
| 110 | .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | 325 | .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, |
| 111 | .lccr3 = LCCR3_PixRsEdg, | 326 | .lccr3 = LCCR3_PixRsEdg, |
| 327 | .pxafb_lcd_power = toppoly_lcd_power, | ||
| 328 | }; | ||
| 329 | |||
| 330 | static struct pxafb_mach_info samsung_info = { | ||
| 331 | .modes = samsung_modes, | ||
| 332 | .num_modes = 1, | ||
| 333 | .fixed_modes = 1, | ||
| 334 | .lccr0 = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | ||
| 335 | .lccr3 = LCCR3_PixFlEdg, | ||
| 336 | .pxafb_lcd_power = samsung_lcd_power, | ||
| 112 | }; | 337 | }; |
| 113 | 338 | ||
| 114 | /* | 339 | /* |
| @@ -120,9 +345,18 @@ static void magician_set_bl_intensity(int intensity) | |||
| 120 | if (intensity) { | 345 | if (intensity) { |
| 121 | PWM_CTRL0 = 1; | 346 | PWM_CTRL0 = 1; |
| 122 | PWM_PERVAL0 = 0xc8; | 347 | PWM_PERVAL0 = 0xc8; |
| 123 | PWM_PWDUTY0 = intensity; | 348 | if (intensity > 0xc7) { |
| 349 | PWM_PWDUTY0 = intensity - 0x48; | ||
| 350 | gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1); | ||
| 351 | } else { | ||
| 352 | PWM_PWDUTY0 = intensity; | ||
| 353 | gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0); | ||
| 354 | } | ||
| 355 | gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1); | ||
| 124 | pxa_set_cken(CKEN_PWM0, 1); | 356 | pxa_set_cken(CKEN_PWM0, 1); |
| 125 | } else { | 357 | } else { |
| 358 | /* PWM_PWDUTY0 = intensity; */ | ||
| 359 | gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0); | ||
| 126 | pxa_set_cken(CKEN_PWM0, 0); | 360 | pxa_set_cken(CKEN_PWM0, 0); |
| 127 | } | 361 | } |
| 128 | } | 362 | } |
| @@ -130,18 +364,215 @@ static void magician_set_bl_intensity(int intensity) | |||
| 130 | static struct generic_bl_info backlight_info = { | 364 | static struct generic_bl_info backlight_info = { |
| 131 | .default_intensity = 0x64, | 365 | .default_intensity = 0x64, |
| 132 | .limit_mask = 0x0b, | 366 | .limit_mask = 0x0b, |
| 133 | .max_intensity = 0xc7, | 367 | .max_intensity = 0xc7+0x48, |
| 134 | .set_bl_intensity = magician_set_bl_intensity, | 368 | .set_bl_intensity = magician_set_bl_intensity, |
| 135 | }; | 369 | }; |
| 136 | 370 | ||
| 137 | static struct platform_device backlight = { | 371 | static struct platform_device backlight = { |
| 138 | .name = "corgi-bl", | 372 | .name = "generic-bl", |
| 139 | .dev = { | 373 | .dev = { |
| 140 | .platform_data = &backlight_info, | 374 | .platform_data = &backlight_info, |
| 141 | }, | 375 | }, |
| 142 | .id = -1, | 376 | .id = -1, |
| 143 | }; | 377 | }; |
| 144 | 378 | ||
| 379 | /* | ||
| 380 | * LEDs | ||
| 381 | */ | ||
| 382 | |||
| 383 | struct gpio_led gpio_leds[] = { | ||
| 384 | { | ||
| 385 | .name = "magician::vibra", | ||
| 386 | .default_trigger = "none", | ||
| 387 | .gpio = GPIO22_MAGICIAN_VIBRA_EN, | ||
| 388 | }, | ||
| 389 | { | ||
| 390 | .name = "magician::phone_bl", | ||
| 391 | .default_trigger = "none", | ||
| 392 | .gpio = GPIO103_MAGICIAN_LED_KP, | ||
| 393 | }, | ||
| 394 | }; | ||
| 395 | |||
| 396 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 397 | .leds = gpio_leds, | ||
| 398 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 399 | }; | ||
| 400 | |||
| 401 | static struct platform_device leds_gpio = { | ||
| 402 | .name = "leds-gpio", | ||
| 403 | .id = -1, | ||
| 404 | .dev = { | ||
| 405 | .platform_data = &gpio_led_info, | ||
| 406 | }, | ||
| 407 | }; | ||
| 408 | |||
| 409 | static struct pasic3_led pasic3_leds[] = { | ||
| 410 | { | ||
| 411 | .led = { | ||
| 412 | .name = "magician:red", | ||
| 413 | .default_trigger = "ds2760-battery.0-charging", | ||
| 414 | }, | ||
| 415 | .hw_num = 0, | ||
| 416 | .bit2 = PASIC3_BIT2_LED0, | ||
| 417 | .mask = PASIC3_MASK_LED0, | ||
| 418 | }, | ||
| 419 | { | ||
| 420 | .led = { | ||
| 421 | .name = "magician:green", | ||
| 422 | .default_trigger = "ds2760-battery.0-charging-or-full", | ||
| 423 | }, | ||
| 424 | .hw_num = 1, | ||
| 425 | .bit2 = PASIC3_BIT2_LED1, | ||
| 426 | .mask = PASIC3_MASK_LED1, | ||
| 427 | }, | ||
| 428 | { | ||
| 429 | .led = { | ||
| 430 | .name = "magician:blue", | ||
| 431 | .default_trigger = "bluetooth", | ||
| 432 | }, | ||
| 433 | .hw_num = 2, | ||
| 434 | .bit2 = PASIC3_BIT2_LED2, | ||
| 435 | .mask = PASIC3_MASK_LED2, | ||
| 436 | }, | ||
| 437 | }; | ||
| 438 | |||
| 439 | static struct platform_device pasic3; | ||
| 440 | |||
| 441 | static struct pasic3_leds_machinfo __devinit pasic3_leds_info = { | ||
| 442 | .num_leds = ARRAY_SIZE(pasic3_leds), | ||
| 443 | .power_gpio = EGPIO_MAGICIAN_LED_POWER, | ||
| 444 | .leds = pasic3_leds, | ||
| 445 | }; | ||
| 446 | |||
| 447 | /* | ||
| 448 | * PASIC3 with DS1WM | ||
| 449 | */ | ||
| 450 | |||
| 451 | static struct resource pasic3_resources[] = { | ||
| 452 | [0] = { | ||
| 453 | .start = PXA_CS2_PHYS, | ||
| 454 | .end = PXA_CS2_PHYS + 0x1b, | ||
| 455 | .flags = IORESOURCE_MEM, | ||
| 456 | }, | ||
| 457 | /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */ | ||
| 458 | [1] = { | ||
| 459 | .start = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ), | ||
| 460 | .end = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ), | ||
| 461 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 462 | } | ||
| 463 | }; | ||
| 464 | |||
| 465 | static struct pasic3_platform_data pasic3_platform_data = { | ||
| 466 | .bus_shift = 2, | ||
| 467 | .led_pdata = &pasic3_leds_info, | ||
| 468 | .clock_rate = 4000000, | ||
| 469 | }; | ||
| 470 | |||
| 471 | static struct platform_device pasic3 = { | ||
| 472 | .name = "pasic3", | ||
| 473 | .id = -1, | ||
| 474 | .num_resources = ARRAY_SIZE(pasic3_resources), | ||
| 475 | .resource = pasic3_resources, | ||
| 476 | .dev = { | ||
| 477 | .platform_data = &pasic3_platform_data, | ||
| 478 | }, | ||
| 479 | }; | ||
| 480 | |||
| 481 | /* | ||
| 482 | * External power | ||
| 483 | */ | ||
| 484 | |||
| 485 | static int magician_is_ac_online(void) | ||
| 486 | { | ||
| 487 | return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_AC); | ||
| 488 | } | ||
| 489 | |||
| 490 | static int magician_is_usb_online(void) | ||
| 491 | { | ||
| 492 | return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_USB); | ||
| 493 | } | ||
| 494 | |||
| 495 | static void magician_set_charge(int flags) | ||
| 496 | { | ||
| 497 | gpio_set_value(GPIO30_MAGICIAN_nCHARGE_EN, !flags); | ||
| 498 | gpio_set_value(EGPIO_MAGICIAN_CHARGE_EN, flags); | ||
| 499 | } | ||
| 500 | |||
| 501 | static char *magician_supplicants[] = { | ||
| 502 | "ds2760-battery.0", "backup-battery" | ||
| 503 | }; | ||
| 504 | |||
| 505 | static struct pda_power_pdata power_supply_info = { | ||
| 506 | .is_ac_online = magician_is_ac_online, | ||
| 507 | .is_usb_online = magician_is_usb_online, | ||
| 508 | .set_charge = magician_set_charge, | ||
| 509 | .supplied_to = magician_supplicants, | ||
| 510 | .num_supplicants = ARRAY_SIZE(magician_supplicants), | ||
| 511 | }; | ||
| 512 | |||
| 513 | static struct resource power_supply_resources[] = { | ||
| 514 | [0] = { | ||
| 515 | .name = "ac", | ||
| 516 | .flags = IORESOURCE_IRQ, | ||
| 517 | .start = IRQ_MAGICIAN_AC, | ||
| 518 | .end = IRQ_MAGICIAN_AC, | ||
| 519 | }, | ||
| 520 | [1] = { | ||
| 521 | .name = "usb", | ||
| 522 | .flags = IORESOURCE_IRQ, | ||
| 523 | .start = IRQ_MAGICIAN_AC, | ||
| 524 | .end = IRQ_MAGICIAN_AC, | ||
| 525 | }, | ||
| 526 | }; | ||
| 527 | |||
| 528 | static struct platform_device power_supply = { | ||
| 529 | .name = "pda-power", | ||
| 530 | .id = -1, | ||
| 531 | .dev = { | ||
| 532 | .platform_data = &power_supply_info, | ||
| 533 | }, | ||
| 534 | .resource = power_supply_resources, | ||
| 535 | .num_resources = ARRAY_SIZE(power_supply_resources), | ||
| 536 | }; | ||
| 537 | |||
| 538 | |||
| 539 | /* | ||
| 540 | * MMC/SD | ||
| 541 | */ | ||
| 542 | |||
| 543 | static int magician_mci_init(struct device *dev, | ||
| 544 | irq_handler_t detect_irq, void *data) | ||
| 545 | { | ||
| 546 | return request_irq(IRQ_MAGICIAN_SD, detect_irq, | ||
| 547 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, | ||
| 548 | "MMC card detect", data); | ||
| 549 | } | ||
| 550 | |||
| 551 | static void magician_mci_setpower(struct device *dev, unsigned int vdd) | ||
| 552 | { | ||
| 553 | struct pxamci_platform_data *pdata = dev->platform_data; | ||
| 554 | |||
| 555 | gpio_set_value(EGPIO_MAGICIAN_SD_POWER, (1 << vdd) & pdata->ocr_mask); | ||
| 556 | } | ||
| 557 | |||
| 558 | static int magician_mci_get_ro(struct device *dev) | ||
| 559 | { | ||
| 560 | return (!gpio_get_value(EGPIO_MAGICIAN_nSD_READONLY)); | ||
| 561 | } | ||
| 562 | |||
| 563 | static void magician_mci_exit(struct device *dev, void *data) | ||
| 564 | { | ||
| 565 | free_irq(IRQ_MAGICIAN_SD, data); | ||
| 566 | } | ||
| 567 | |||
| 568 | static struct pxamci_platform_data magician_mci_info = { | ||
| 569 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
| 570 | .init = magician_mci_init, | ||
| 571 | .get_ro = magician_mci_get_ro, | ||
| 572 | .setpower = magician_mci_setpower, | ||
| 573 | .exit = magician_mci_exit, | ||
| 574 | }; | ||
| 575 | |||
| 145 | 576 | ||
| 146 | /* | 577 | /* |
| 147 | * USB OHCI | 578 | * USB OHCI |
| @@ -166,6 +597,11 @@ static struct pxaohci_platform_data magician_ohci_info = { | |||
| 166 | * StrataFlash | 597 | * StrataFlash |
| 167 | */ | 598 | */ |
| 168 | 599 | ||
| 600 | static void magician_set_vpp(struct map_info *map, int vpp) | ||
| 601 | { | ||
| 602 | gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); | ||
| 603 | } | ||
| 604 | |||
| 169 | #define PXA_CS_SIZE 0x04000000 | 605 | #define PXA_CS_SIZE 0x04000000 |
| 170 | 606 | ||
| 171 | static struct resource strataflash_resource = { | 607 | static struct resource strataflash_resource = { |
| @@ -176,13 +612,14 @@ static struct resource strataflash_resource = { | |||
| 176 | 612 | ||
| 177 | static struct physmap_flash_data strataflash_data = { | 613 | static struct physmap_flash_data strataflash_data = { |
| 178 | .width = 4, | 614 | .width = 4, |
| 615 | .set_vpp = magician_set_vpp, | ||
| 179 | }; | 616 | }; |
| 180 | 617 | ||
| 181 | static struct platform_device strataflash = { | 618 | static struct platform_device strataflash = { |
| 182 | .name = "physmap-flash", | 619 | .name = "physmap-flash", |
| 183 | .id = -1, | 620 | .id = -1, |
| 184 | .num_resources = 1, | ||
| 185 | .resource = &strataflash_resource, | 621 | .resource = &strataflash_resource, |
| 622 | .num_resources = 1, | ||
| 186 | .dev = { | 623 | .dev = { |
| 187 | .platform_data = &strataflash_data, | 624 | .platform_data = &strataflash_data, |
| 188 | }, | 625 | }, |
| @@ -194,16 +631,43 @@ static struct platform_device strataflash = { | |||
| 194 | 631 | ||
| 195 | static struct platform_device *devices[] __initdata = { | 632 | static struct platform_device *devices[] __initdata = { |
| 196 | &gpio_keys, | 633 | &gpio_keys, |
| 634 | &egpio, | ||
| 197 | &backlight, | 635 | &backlight, |
| 636 | &pasic3, | ||
| 637 | &power_supply, | ||
| 198 | &strataflash, | 638 | &strataflash, |
| 639 | &leds_gpio, | ||
| 199 | }; | 640 | }; |
| 200 | 641 | ||
| 201 | static void __init magician_init(void) | 642 | static void __init magician_init(void) |
| 202 | { | 643 | { |
| 644 | void __iomem *cpld; | ||
| 645 | int lcd_select; | ||
| 646 | |||
| 647 | pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config)); | ||
| 648 | |||
| 203 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 649 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 650 | pxa_set_i2c_info(NULL); | ||
| 651 | pxa_set_mci_info(&magician_mci_info); | ||
| 204 | pxa_set_ohci_info(&magician_ohci_info); | 652 | pxa_set_ohci_info(&magician_ohci_info); |
| 205 | pxa_set_ficp_info(&magician_ficp_info); | 653 | pxa_set_ficp_info(&magician_ficp_info); |
| 206 | set_pxa_fb_info(&toppoly_info); | 654 | |
| 655 | /* Check LCD type we have */ | ||
| 656 | cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000); | ||
| 657 | if (cpld) { | ||
| 658 | u8 board_id = __raw_readb(cpld+0x14); | ||
| 659 | system_rev = board_id & 0x7; | ||
| 660 | lcd_select = board_id & 0x8; | ||
| 661 | iounmap(cpld); | ||
| 662 | pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly"); | ||
| 663 | if (lcd_select && (system_rev < 3)) | ||
| 664 | pxa_gpio_mode(GPIO75_MAGICIAN_SAMSUNG_POWER_MD); | ||
| 665 | pxa_gpio_mode(GPIO104_MAGICIAN_LCD_POWER_1_MD); | ||
| 666 | pxa_gpio_mode(GPIO105_MAGICIAN_LCD_POWER_2_MD); | ||
| 667 | pxa_gpio_mode(GPIO106_MAGICIAN_LCD_POWER_3_MD); | ||
| 668 | set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info); | ||
| 669 | } else | ||
| 670 | pr_err("LCD detection: CPLD mapping failed\n"); | ||
| 207 | } | 671 | } |
| 208 | 672 | ||
| 209 | 673 | ||
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 72a436fb9a29..18d47cfa2a18 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
| @@ -24,6 +24,8 @@ | |||
| 24 | #include <linux/mtd/mtd.h> | 24 | #include <linux/mtd/mtd.h> |
| 25 | #include <linux/mtd/partitions.h> | 25 | #include <linux/mtd/partitions.h> |
| 26 | #include <linux/backlight.h> | 26 | #include <linux/backlight.h> |
| 27 | #include <linux/input.h> | ||
| 28 | #include <linux/gpio_keys.h> | ||
| 27 | 29 | ||
| 28 | #include <asm/types.h> | 30 | #include <asm/types.h> |
| 29 | #include <asm/setup.h> | 31 | #include <asm/setup.h> |
| @@ -40,16 +42,94 @@ | |||
| 40 | 42 | ||
| 41 | #include <asm/arch/pxa-regs.h> | 43 | #include <asm/arch/pxa-regs.h> |
| 42 | #include <asm/arch/pxa2xx-regs.h> | 44 | #include <asm/arch/pxa2xx-regs.h> |
| 45 | #include <asm/arch/mfp-pxa27x.h> | ||
| 43 | #include <asm/arch/mainstone.h> | 46 | #include <asm/arch/mainstone.h> |
| 44 | #include <asm/arch/audio.h> | 47 | #include <asm/arch/audio.h> |
| 45 | #include <asm/arch/pxafb.h> | 48 | #include <asm/arch/pxafb.h> |
| 49 | #include <asm/arch/i2c.h> | ||
| 46 | #include <asm/arch/mmc.h> | 50 | #include <asm/arch/mmc.h> |
| 47 | #include <asm/arch/irda.h> | 51 | #include <asm/arch/irda.h> |
| 48 | #include <asm/arch/ohci.h> | 52 | #include <asm/arch/ohci.h> |
| 53 | #include <asm/arch/pxa27x_keypad.h> | ||
| 49 | 54 | ||
| 50 | #include "generic.h" | 55 | #include "generic.h" |
| 51 | #include "devices.h" | 56 | #include "devices.h" |
| 52 | 57 | ||
| 58 | static unsigned long mainstone_pin_config[] = { | ||
| 59 | /* Chip Select */ | ||
| 60 | GPIO15_nCS_1, | ||
| 61 | |||
| 62 | /* LCD - 16bpp Active TFT */ | ||
| 63 | GPIO58_LCD_LDD_0, | ||
| 64 | GPIO59_LCD_LDD_1, | ||
| 65 | GPIO60_LCD_LDD_2, | ||
| 66 | GPIO61_LCD_LDD_3, | ||
| 67 | GPIO62_LCD_LDD_4, | ||
| 68 | GPIO63_LCD_LDD_5, | ||
| 69 | GPIO64_LCD_LDD_6, | ||
| 70 | GPIO65_LCD_LDD_7, | ||
| 71 | GPIO66_LCD_LDD_8, | ||
| 72 | GPIO67_LCD_LDD_9, | ||
| 73 | GPIO68_LCD_LDD_10, | ||
| 74 | GPIO69_LCD_LDD_11, | ||
| 75 | GPIO70_LCD_LDD_12, | ||
| 76 | GPIO71_LCD_LDD_13, | ||
| 77 | GPIO72_LCD_LDD_14, | ||
| 78 | GPIO73_LCD_LDD_15, | ||
| 79 | GPIO74_LCD_FCLK, | ||
| 80 | GPIO75_LCD_LCLK, | ||
| 81 | GPIO76_LCD_PCLK, | ||
| 82 | GPIO77_LCD_BIAS, | ||
| 83 | GPIO16_PWM0_OUT, /* Backlight */ | ||
| 84 | |||
| 85 | /* MMC */ | ||
| 86 | GPIO32_MMC_CLK, | ||
| 87 | GPIO112_MMC_CMD, | ||
| 88 | GPIO92_MMC_DAT_0, | ||
| 89 | GPIO109_MMC_DAT_1, | ||
| 90 | GPIO110_MMC_DAT_2, | ||
| 91 | GPIO111_MMC_DAT_3, | ||
| 92 | |||
| 93 | /* USB Host Port 1 */ | ||
| 94 | GPIO88_USBH1_PWR, | ||
| 95 | GPIO89_USBH1_PEN, | ||
| 96 | |||
| 97 | /* PC Card */ | ||
| 98 | GPIO48_nPOE, | ||
| 99 | GPIO49_nPWE, | ||
| 100 | GPIO50_nPIOR, | ||
| 101 | GPIO51_nPIOW, | ||
| 102 | GPIO85_nPCE_1, | ||
| 103 | GPIO54_nPCE_2, | ||
| 104 | GPIO79_PSKTSEL, | ||
| 105 | GPIO55_nPREG, | ||
| 106 | GPIO56_nPWAIT, | ||
| 107 | GPIO57_nIOIS16, | ||
| 108 | |||
| 109 | /* AC97 */ | ||
| 110 | GPIO45_AC97_SYSCLK, | ||
| 111 | |||
| 112 | /* Keypad */ | ||
| 113 | GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
| 114 | GPIO94_KP_DKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
| 115 | GPIO95_KP_DKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
| 116 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
| 117 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | ||
| 118 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | ||
| 119 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | ||
| 120 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | ||
| 121 | GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, | ||
| 122 | GPIO103_KP_MKOUT_0, | ||
| 123 | GPIO104_KP_MKOUT_1, | ||
| 124 | GPIO105_KP_MKOUT_2, | ||
| 125 | GPIO106_KP_MKOUT_3, | ||
| 126 | GPIO107_KP_MKOUT_4, | ||
| 127 | GPIO108_KP_MKOUT_5, | ||
| 128 | GPIO96_KP_MKOUT_6, | ||
| 129 | |||
| 130 | /* GPIO */ | ||
| 131 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | ||
| 132 | }; | ||
| 53 | 133 | ||
| 54 | static unsigned long mainstone_irq_enabled; | 134 | static unsigned long mainstone_irq_enabled; |
| 55 | 135 | ||
| @@ -278,13 +358,13 @@ static int mainstone_backlight_update_status(struct backlight_device *bl) | |||
| 278 | bl->props.fb_blank != FB_BLANK_UNBLANK) | 358 | bl->props.fb_blank != FB_BLANK_UNBLANK) |
| 279 | brightness = 0; | 359 | brightness = 0; |
| 280 | 360 | ||
| 281 | if (brightness != 0) { | 361 | if (brightness != 0) |
| 282 | pxa_gpio_mode(GPIO16_PWM0_MD); | ||
| 283 | pxa_set_cken(CKEN_PWM0, 1); | 362 | pxa_set_cken(CKEN_PWM0, 1); |
| 284 | } | 363 | |
| 285 | PWM_CTRL0 = 0; | 364 | PWM_CTRL0 = 0; |
| 286 | PWM_PWDUTY0 = brightness; | 365 | PWM_PWDUTY0 = brightness; |
| 287 | PWM_PERVAL0 = bl->props.max_brightness; | 366 | PWM_PERVAL0 = bl->props.max_brightness; |
| 367 | |||
| 288 | if (brightness == 0) | 368 | if (brightness == 0) |
| 289 | pxa_set_cken(CKEN_PWM0, 0); | 369 | pxa_set_cken(CKEN_PWM0, 0); |
| 290 | return 0; /* pointless return value */ | 370 | return 0; /* pointless return value */ |
| @@ -362,16 +442,6 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in | |||
| 362 | { | 442 | { |
| 363 | int err; | 443 | int err; |
| 364 | 444 | ||
| 365 | /* | ||
| 366 | * setup GPIO for PXA27x MMC controller | ||
| 367 | */ | ||
| 368 | pxa_gpio_mode(GPIO32_MMCCLK_MD); | ||
| 369 | pxa_gpio_mode(GPIO112_MMCCMD_MD); | ||
| 370 | pxa_gpio_mode(GPIO92_MMCDAT0_MD); | ||
| 371 | pxa_gpio_mode(GPIO109_MMCDAT1_MD); | ||
| 372 | pxa_gpio_mode(GPIO110_MMCDAT2_MD); | ||
| 373 | pxa_gpio_mode(GPIO111_MMCDAT3_MD); | ||
| 374 | |||
| 375 | /* make sure SD/Memory Stick multiplexer's signals | 445 | /* make sure SD/Memory Stick multiplexer's signals |
| 376 | * are routed to MMC controller | 446 | * are routed to MMC controller |
| 377 | */ | 447 | */ |
| @@ -434,19 +504,39 @@ static struct pxaficp_platform_data mainstone_ficp_platform_data = { | |||
| 434 | .transceiver_mode = mainstone_irda_transceiver_mode, | 504 | .transceiver_mode = mainstone_irda_transceiver_mode, |
| 435 | }; | 505 | }; |
| 436 | 506 | ||
| 507 | static struct gpio_keys_button gpio_keys_button[] = { | ||
| 508 | [0] = { | ||
| 509 | .desc = "wakeup", | ||
| 510 | .code = KEY_SUSPEND, | ||
| 511 | .type = EV_KEY, | ||
| 512 | .gpio = 1, | ||
| 513 | .wakeup = 1, | ||
| 514 | }, | ||
| 515 | }; | ||
| 516 | |||
| 517 | static struct gpio_keys_platform_data mainstone_gpio_keys = { | ||
| 518 | .buttons = gpio_keys_button, | ||
| 519 | .nbuttons = 1, | ||
| 520 | }; | ||
| 521 | |||
| 522 | static struct platform_device mst_gpio_keys_device = { | ||
| 523 | .name = "gpio-keys", | ||
| 524 | .id = -1, | ||
| 525 | .dev = { | ||
| 526 | .platform_data = &mainstone_gpio_keys, | ||
| 527 | }, | ||
| 528 | }; | ||
| 529 | |||
| 437 | static struct platform_device *platform_devices[] __initdata = { | 530 | static struct platform_device *platform_devices[] __initdata = { |
| 438 | &smc91x_device, | 531 | &smc91x_device, |
| 439 | &mst_audio_device, | 532 | &mst_audio_device, |
| 440 | &mst_flash_device[0], | 533 | &mst_flash_device[0], |
| 441 | &mst_flash_device[1], | 534 | &mst_flash_device[1], |
| 535 | &mst_gpio_keys_device, | ||
| 442 | }; | 536 | }; |
| 443 | 537 | ||
| 444 | static int mainstone_ohci_init(struct device *dev) | 538 | static int mainstone_ohci_init(struct device *dev) |
| 445 | { | 539 | { |
| 446 | /* setup Port1 GPIO pin. */ | ||
| 447 | pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */ | ||
| 448 | pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */ | ||
| 449 | |||
| 450 | /* Set the Power Control Polarity Low and Power Sense | 540 | /* Set the Power Control Polarity Low and Power Sense |
| 451 | Polarity Low to active low. */ | 541 | Polarity Low to active low. */ |
| 452 | UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & | 542 | UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
| @@ -460,10 +550,63 @@ static struct pxaohci_platform_data mainstone_ohci_platform_data = { | |||
| 460 | .init = mainstone_ohci_init, | 550 | .init = mainstone_ohci_init, |
| 461 | }; | 551 | }; |
| 462 | 552 | ||
| 553 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES) | ||
| 554 | static unsigned int mainstone_matrix_keys[] = { | ||
| 555 | KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C), | ||
| 556 | KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F), | ||
| 557 | KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I), | ||
| 558 | KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L), | ||
| 559 | KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O), | ||
| 560 | KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R), | ||
| 561 | KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U), | ||
| 562 | KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X), | ||
| 563 | KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z), | ||
| 564 | |||
| 565 | KEY(0, 4, KEY_DOT), /* . */ | ||
| 566 | KEY(1, 4, KEY_CLOSE), /* @ */ | ||
| 567 | KEY(4, 4, KEY_SLASH), | ||
| 568 | KEY(5, 4, KEY_BACKSLASH), | ||
| 569 | KEY(0, 5, KEY_HOME), | ||
| 570 | KEY(1, 5, KEY_LEFTSHIFT), | ||
| 571 | KEY(2, 5, KEY_SPACE), | ||
| 572 | KEY(3, 5, KEY_SPACE), | ||
| 573 | KEY(4, 5, KEY_ENTER), | ||
| 574 | KEY(5, 5, KEY_BACKSPACE), | ||
| 575 | |||
| 576 | KEY(0, 6, KEY_UP), | ||
| 577 | KEY(1, 6, KEY_DOWN), | ||
| 578 | KEY(2, 6, KEY_LEFT), | ||
| 579 | KEY(3, 6, KEY_RIGHT), | ||
| 580 | KEY(4, 6, KEY_SELECT), | ||
| 581 | }; | ||
| 582 | |||
| 583 | struct pxa27x_keypad_platform_data mainstone_keypad_info = { | ||
| 584 | .matrix_key_rows = 6, | ||
| 585 | .matrix_key_cols = 7, | ||
| 586 | .matrix_key_map = mainstone_matrix_keys, | ||
| 587 | .matrix_key_map_size = ARRAY_SIZE(mainstone_matrix_keys), | ||
| 588 | |||
| 589 | .enable_rotary0 = 1, | ||
| 590 | .rotary0_up_key = KEY_UP, | ||
| 591 | .rotary0_down_key = KEY_DOWN, | ||
| 592 | |||
| 593 | .debounce_interval = 30, | ||
| 594 | }; | ||
| 595 | |||
| 596 | static void __init mainstone_init_keypad(void) | ||
| 597 | { | ||
| 598 | pxa_set_keypad_info(&mainstone_keypad_info); | ||
| 599 | } | ||
| 600 | #else | ||
| 601 | static inline void mainstone_init_keypad(void) {} | ||
| 602 | #endif | ||
| 603 | |||
| 463 | static void __init mainstone_init(void) | 604 | static void __init mainstone_init(void) |
| 464 | { | 605 | { |
| 465 | int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ | 606 | int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ |
| 466 | 607 | ||
| 608 | pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config)); | ||
| 609 | |||
| 467 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | 610 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; |
| 468 | mst_flash_data[1].width = 4; | 611 | mst_flash_data[1].width = 4; |
| 469 | 612 | ||
| @@ -480,31 +623,6 @@ static void __init mainstone_init(void) | |||
| 480 | */ | 623 | */ |
| 481 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | 624 | ARB_CNTRL = ARB_CORE_PARK | 0x234; |
| 482 | 625 | ||
| 483 | /* | ||
| 484 | * On Mainstone, we route AC97_SYSCLK via GPIO45 to | ||
| 485 | * the audio daughter card | ||
| 486 | */ | ||
| 487 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); | ||
| 488 | |||
| 489 | GPSR(GPIO48_nPOE) = | ||
| 490 | GPIO_bit(GPIO48_nPOE) | | ||
| 491 | GPIO_bit(GPIO49_nPWE) | | ||
| 492 | GPIO_bit(GPIO50_nPIOR) | | ||
| 493 | GPIO_bit(GPIO51_nPIOW) | | ||
| 494 | GPIO_bit(GPIO85_nPCE_1) | | ||
| 495 | GPIO_bit(GPIO54_nPCE_2); | ||
| 496 | |||
| 497 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
| 498 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
| 499 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
| 500 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
| 501 | pxa_gpio_mode(GPIO85_nPCE_1_MD); | ||
| 502 | pxa_gpio_mode(GPIO54_nPCE_2_MD); | ||
| 503 | pxa_gpio_mode(GPIO79_pSKTSEL_MD); | ||
| 504 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
| 505 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
| 506 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
| 507 | |||
| 508 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 626 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 509 | 627 | ||
| 510 | /* reading Mainstone's "Virtual Configuration Register" | 628 | /* reading Mainstone's "Virtual Configuration Register" |
| @@ -520,6 +638,9 @@ static void __init mainstone_init(void) | |||
| 520 | pxa_set_mci_info(&mainstone_mci_platform_data); | 638 | pxa_set_mci_info(&mainstone_mci_platform_data); |
| 521 | pxa_set_ficp_info(&mainstone_ficp_platform_data); | 639 | pxa_set_ficp_info(&mainstone_ficp_platform_data); |
| 522 | pxa_set_ohci_info(&mainstone_ohci_platform_data); | 640 | pxa_set_ohci_info(&mainstone_ohci_platform_data); |
| 641 | pxa_set_i2c_info(NULL); | ||
| 642 | |||
| 643 | mainstone_init_keypad(); | ||
| 523 | } | 644 | } |
| 524 | 645 | ||
| 525 | 646 | ||
| @@ -537,23 +658,9 @@ static void __init mainstone_map_io(void) | |||
| 537 | pxa_map_io(); | 658 | pxa_map_io(); |
| 538 | iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); | 659 | iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); |
| 539 | 660 | ||
| 540 | /* initialize sleep mode regs (wake-up sources, etc) */ | ||
| 541 | PGSR0 = 0x00008800; | ||
| 542 | PGSR1 = 0x00000002; | ||
| 543 | PGSR2 = 0x0001FC00; | ||
| 544 | PGSR3 = 0x00001F81; | ||
| 545 | PWER = 0xC0000002; | ||
| 546 | PRER = 0x00000002; | ||
| 547 | PFER = 0x00000002; | ||
| 548 | /* for use I SRAM as framebuffer. */ | 661 | /* for use I SRAM as framebuffer. */ |
| 549 | PSLR |= 0xF04; | 662 | PSLR |= 0xF04; |
| 550 | PCFR = 0x66; | 663 | PCFR = 0x66; |
| 551 | /* For Keypad wakeup. */ | ||
| 552 | KPC &=~KPC_ASACT; | ||
| 553 | KPC |=KPC_AS; | ||
| 554 | PKWR = 0x000FD000; | ||
| 555 | /* Need read PKWR back after set it. */ | ||
| 556 | PKWR; | ||
| 557 | } | 664 | } |
| 558 | 665 | ||
| 559 | MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") | 666 | MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") |
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c new file mode 100644 index 000000000000..22097a1707cc --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c | |||
| @@ -0,0 +1,245 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/mfp-pxa2xx.c | ||
| 3 | * | ||
| 4 | * PXA2xx pin mux configuration support | ||
| 5 | * | ||
| 6 | * The GPIOs on PXA2xx can be configured as one of many alternate | ||
| 7 | * functions, this is by concept samilar to the MFP configuration | ||
| 8 | * on PXA3xx, what's more important, the low power pin state and | ||
| 9 | * wakeup detection are also supported by the same framework. | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/sysdev.h> | ||
| 20 | |||
| 21 | #include <asm/arch/hardware.h> | ||
| 22 | #include <asm/arch/pxa-regs.h> | ||
| 23 | #include <asm/arch/mfp-pxa2xx.h> | ||
| 24 | |||
| 25 | #include "generic.h" | ||
| 26 | |||
| 27 | #define PGSR(x) __REG2(0x40F00020, ((x) & 0x60) >> 3) | ||
| 28 | |||
| 29 | #define PWER_WE35 (1 << 24) | ||
| 30 | |||
| 31 | struct gpio_desc { | ||
| 32 | unsigned valid : 1; | ||
| 33 | unsigned can_wakeup : 1; | ||
| 34 | unsigned keypad_gpio : 1; | ||
| 35 | unsigned int mask; /* bit mask in PWER or PKWR */ | ||
| 36 | unsigned long config; | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; | ||
| 40 | |||
| 41 | static int __mfp_config_gpio(unsigned gpio, unsigned long c) | ||
| 42 | { | ||
| 43 | unsigned long gafr, mask = GPIO_bit(gpio); | ||
| 44 | int fn; | ||
| 45 | |||
| 46 | fn = MFP_AF(c); | ||
| 47 | if (fn > 3) | ||
| 48 | return -EINVAL; | ||
| 49 | |||
| 50 | /* alternate function and direction */ | ||
| 51 | gafr = GAFR(gpio) & ~(0x3 << ((gpio & 0xf) * 2)); | ||
| 52 | GAFR(gpio) = gafr | (fn << ((gpio & 0xf) * 2)); | ||
| 53 | |||
| 54 | if (c & MFP_DIR_OUT) | ||
| 55 | GPDR(gpio) |= mask; | ||
| 56 | else | ||
| 57 | GPDR(gpio) &= ~mask; | ||
| 58 | |||
| 59 | /* low power state */ | ||
| 60 | switch (c & MFP_LPM_STATE_MASK) { | ||
| 61 | case MFP_LPM_DRIVE_HIGH: | ||
| 62 | PGSR(gpio) |= mask; | ||
| 63 | break; | ||
| 64 | case MFP_LPM_DRIVE_LOW: | ||
| 65 | PGSR(gpio) &= ~mask; | ||
| 66 | break; | ||
| 67 | case MFP_LPM_INPUT: | ||
| 68 | break; | ||
| 69 | default: | ||
| 70 | pr_warning("%s: invalid low power state for GPIO%d\n", | ||
| 71 | __func__, gpio); | ||
| 72 | return -EINVAL; | ||
| 73 | } | ||
| 74 | |||
| 75 | /* give early warning if MFP_LPM_CAN_WAKEUP is set on the | ||
| 76 | * configurations of those pins not able to wakeup | ||
| 77 | */ | ||
| 78 | if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) { | ||
| 79 | pr_warning("%s: GPIO%d unable to wakeup\n", | ||
| 80 | __func__, gpio); | ||
| 81 | return -EINVAL; | ||
| 82 | } | ||
| 83 | |||
| 84 | if ((c & MFP_LPM_CAN_WAKEUP) && (c & MFP_DIR_OUT)) { | ||
| 85 | pr_warning("%s: output GPIO%d unable to wakeup\n", | ||
| 86 | __func__, gpio); | ||
| 87 | return -EINVAL; | ||
| 88 | } | ||
| 89 | |||
| 90 | return 0; | ||
| 91 | } | ||
| 92 | |||
| 93 | void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num) | ||
| 94 | { | ||
| 95 | unsigned long flags; | ||
| 96 | unsigned long *c; | ||
| 97 | int i, gpio; | ||
| 98 | |||
| 99 | for (i = 0, c = mfp_cfgs; i < num; i++, c++) { | ||
| 100 | |||
| 101 | gpio = mfp_to_gpio(MFP_PIN(*c)); | ||
| 102 | |||
| 103 | if (!gpio_desc[gpio].valid) { | ||
| 104 | pr_warning("%s: GPIO%d is invalid pin\n", | ||
| 105 | __func__, gpio); | ||
| 106 | continue; | ||
| 107 | } | ||
| 108 | |||
| 109 | local_irq_save(flags); | ||
| 110 | |||
| 111 | gpio_desc[gpio].config = *c; | ||
| 112 | __mfp_config_gpio(gpio, *c); | ||
| 113 | |||
| 114 | local_irq_restore(flags); | ||
| 115 | } | ||
| 116 | } | ||
| 117 | |||
| 118 | int gpio_set_wake(unsigned int gpio, unsigned int on) | ||
| 119 | { | ||
| 120 | struct gpio_desc *d; | ||
| 121 | unsigned long c; | ||
| 122 | |||
| 123 | if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) | ||
| 124 | return -EINVAL; | ||
| 125 | |||
| 126 | d = &gpio_desc[gpio]; | ||
| 127 | c = d->config; | ||
| 128 | |||
| 129 | if (!d->valid) | ||
| 130 | return -EINVAL; | ||
| 131 | |||
| 132 | if (d->keypad_gpio) | ||
| 133 | return -EINVAL; | ||
| 134 | |||
| 135 | if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { | ||
| 136 | if (on) { | ||
| 137 | PWER |= d->mask; | ||
| 138 | |||
| 139 | if (c & MFP_LPM_EDGE_RISE) | ||
| 140 | PRER |= d->mask; | ||
| 141 | else | ||
| 142 | PRER &= ~d->mask; | ||
| 143 | |||
| 144 | if (c & MFP_LPM_EDGE_FALL) | ||
| 145 | PFER |= d->mask; | ||
| 146 | else | ||
| 147 | PFER &= ~d->mask; | ||
| 148 | } else { | ||
| 149 | PWER &= ~d->mask; | ||
| 150 | PRER &= ~d->mask; | ||
| 151 | PFER &= ~d->mask; | ||
| 152 | } | ||
| 153 | } | ||
| 154 | return 0; | ||
| 155 | } | ||
| 156 | |||
| 157 | #ifdef CONFIG_PXA25x | ||
| 158 | static int __init pxa25x_mfp_init(void) | ||
| 159 | { | ||
| 160 | int i; | ||
| 161 | |||
| 162 | if (cpu_is_pxa25x()) { | ||
| 163 | for (i = 0; i <= 84; i++) | ||
| 164 | gpio_desc[i].valid = 1; | ||
| 165 | |||
| 166 | for (i = 0; i <= 15; i++) { | ||
| 167 | gpio_desc[i].can_wakeup = 1; | ||
| 168 | gpio_desc[i].mask = GPIO_bit(i); | ||
| 169 | } | ||
| 170 | } | ||
| 171 | |||
| 172 | return 0; | ||
| 173 | } | ||
| 174 | postcore_initcall(pxa25x_mfp_init); | ||
| 175 | #endif /* CONFIG_PXA25x */ | ||
| 176 | |||
| 177 | #ifdef CONFIG_PXA27x | ||
| 178 | static int pxa27x_pkwr_gpio[] = { | ||
| 179 | 13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94, | ||
| 180 | 95, 96, 97, 98, 99, 100, 101, 102 | ||
| 181 | }; | ||
| 182 | |||
| 183 | int keypad_set_wake(unsigned int on) | ||
| 184 | { | ||
| 185 | unsigned int i, gpio, mask = 0; | ||
| 186 | |||
| 187 | if (!on) { | ||
| 188 | PKWR = 0; | ||
| 189 | return 0; | ||
| 190 | } | ||
| 191 | |||
| 192 | for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { | ||
| 193 | |||
| 194 | gpio = pxa27x_pkwr_gpio[i]; | ||
| 195 | |||
| 196 | if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP) | ||
| 197 | mask |= gpio_desc[gpio].mask; | ||
| 198 | } | ||
| 199 | |||
| 200 | PKWR = mask; | ||
| 201 | return 0; | ||
| 202 | } | ||
| 203 | |||
| 204 | static int __init pxa27x_mfp_init(void) | ||
| 205 | { | ||
| 206 | int i, gpio; | ||
| 207 | |||
| 208 | if (cpu_is_pxa27x()) { | ||
| 209 | for (i = 0; i <= 120; i++) { | ||
| 210 | /* skip GPIO2, 5, 6, 7, 8, they are not | ||
| 211 | * valid pins allow configuration | ||
| 212 | */ | ||
| 213 | if (i == 2 || i == 5 || i == 6 || | ||
| 214 | i == 7 || i == 8) | ||
| 215 | continue; | ||
| 216 | |||
| 217 | gpio_desc[i].valid = 1; | ||
| 218 | } | ||
| 219 | |||
| 220 | /* Keypad GPIOs */ | ||
| 221 | for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { | ||
| 222 | gpio = pxa27x_pkwr_gpio[i]; | ||
| 223 | gpio_desc[gpio].can_wakeup = 1; | ||
| 224 | gpio_desc[gpio].keypad_gpio = 1; | ||
| 225 | gpio_desc[gpio].mask = 1 << i; | ||
| 226 | } | ||
| 227 | |||
| 228 | /* Overwrite GPIO13 as a PWER wakeup source */ | ||
| 229 | for (i = 0; i <= 15; i++) { | ||
| 230 | /* skip GPIO2, 5, 6, 7, 8 */ | ||
| 231 | if (GPIO_bit(i) & 0x1e4) | ||
| 232 | continue; | ||
| 233 | |||
| 234 | gpio_desc[i].can_wakeup = 1; | ||
| 235 | gpio_desc[i].mask = GPIO_bit(i); | ||
| 236 | } | ||
| 237 | |||
| 238 | gpio_desc[35].can_wakeup = 1; | ||
| 239 | gpio_desc[35].mask = PWER_WE35; | ||
| 240 | } | ||
| 241 | |||
| 242 | return 0; | ||
| 243 | } | ||
| 244 | postcore_initcall(pxa27x_mfp_init); | ||
| 245 | #endif /* CONFIG_PXA27x */ | ||
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index f5809adce298..b84c3ba7a8d6 100644 --- a/arch/arm/mach-pxa/mfp.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c | |||
| @@ -234,22 +234,22 @@ static int pxa3xx_mfp_resume(struct sys_device *d) | |||
| 234 | 234 | ||
| 235 | return 0; | 235 | return 0; |
| 236 | } | 236 | } |
| 237 | #else | ||
| 238 | #define pxa3xx_mfp_suspend NULL | ||
| 239 | #define pxa3xx_mfp_resume NULL | ||
| 240 | #endif | ||
| 237 | 241 | ||
| 238 | static struct sysdev_class mfp_sysclass = { | 242 | struct sysdev_class pxa3xx_mfp_sysclass = { |
| 239 | .name = "mfp", | 243 | .name = "mfp", |
| 240 | .suspend = pxa3xx_mfp_suspend, | 244 | .suspend = pxa3xx_mfp_suspend, |
| 241 | .resume = pxa3xx_mfp_resume, | 245 | .resume = pxa3xx_mfp_resume, |
| 242 | }; | 246 | }; |
| 243 | 247 | ||
| 244 | static struct sys_device mfp_device = { | ||
| 245 | .id = 0, | ||
| 246 | .cls = &mfp_sysclass, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static int __init mfp_init_devicefs(void) | 248 | static int __init mfp_init_devicefs(void) |
| 250 | { | 249 | { |
| 251 | sysdev_class_register(&mfp_sysclass); | 250 | if (cpu_is_pxa3xx()) |
| 252 | return sysdev_register(&mfp_device); | 251 | return sysdev_class_register(&pxa3xx_mfp_sysclass); |
| 252 | |||
| 253 | return 0; | ||
| 253 | } | 254 | } |
| 254 | device_initcall(mfp_init_devicefs); | 255 | postcore_initcall(mfp_init_devicefs); |
| 255 | #endif | ||
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index c14696b9979d..3b945eb0aee3 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 30 | #include <asm/arch/hardware.h> | 30 | #include <asm/arch/hardware.h> |
| 31 | #include <asm/arch/pxa-regs.h> | 31 | #include <asm/arch/pxa-regs.h> |
| 32 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 32 | #include <asm/arch/pxa2xx-regs.h> | 33 | #include <asm/arch/pxa2xx-regs.h> |
| 33 | #include <asm/arch/pxa2xx_spi.h> | 34 | #include <asm/arch/pxa2xx_spi.h> |
| 34 | #include <asm/arch/pcm027.h> | 35 | #include <asm/arch/pcm027.h> |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 3dda16a20049..e6be9d0aeccf 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
| @@ -23,8 +23,16 @@ | |||
| 23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/ide.h> | 25 | #include <linux/ide.h> |
| 26 | #include <linux/i2c.h> | ||
| 27 | |||
| 28 | #include <media/soc_camera.h> | ||
| 29 | |||
| 30 | #include <asm/gpio.h> | ||
| 31 | #include <asm/arch/i2c.h> | ||
| 32 | #include <asm/arch/camera.h> | ||
| 26 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 27 | #include <asm/arch/pxa-regs.h> | 34 | #include <asm/arch/pxa-regs.h> |
| 35 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 28 | #include <asm/arch/mmc.h> | 36 | #include <asm/arch/mmc.h> |
| 29 | #include <asm/arch/ohci.h> | 37 | #include <asm/arch/ohci.h> |
| 30 | #include <asm/arch/pcm990_baseboard.h> | 38 | #include <asm/arch/pcm990_baseboard.h> |
| @@ -258,6 +266,76 @@ static struct pxaohci_platform_data pcm990_ohci_platform_data = { | |||
| 258 | }; | 266 | }; |
| 259 | 267 | ||
| 260 | /* | 268 | /* |
| 269 | * PXA27x Camera specific stuff | ||
| 270 | */ | ||
| 271 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) | ||
| 272 | static int pcm990_pxacamera_init(struct device *dev) | ||
| 273 | { | ||
| 274 | pxa_gpio_mode(GPIO98_CIF_DD_0_MD); | ||
| 275 | pxa_gpio_mode(GPIO105_CIF_DD_1_MD); | ||
| 276 | pxa_gpio_mode(GPIO104_CIF_DD_2_MD); | ||
| 277 | pxa_gpio_mode(GPIO103_CIF_DD_3_MD); | ||
| 278 | pxa_gpio_mode(GPIO95_CIF_DD_4_MD); | ||
| 279 | pxa_gpio_mode(GPIO94_CIF_DD_5_MD); | ||
| 280 | pxa_gpio_mode(GPIO93_CIF_DD_6_MD); | ||
| 281 | pxa_gpio_mode(GPIO108_CIF_DD_7_MD); | ||
| 282 | pxa_gpio_mode(GPIO107_CIF_DD_8_MD); | ||
| 283 | pxa_gpio_mode(GPIO106_CIF_DD_9_MD); | ||
| 284 | pxa_gpio_mode(GPIO42_CIF_MCLK_MD); | ||
| 285 | pxa_gpio_mode(GPIO45_CIF_PCLK_MD); | ||
| 286 | pxa_gpio_mode(GPIO43_CIF_FV_MD); | ||
| 287 | pxa_gpio_mode(GPIO44_CIF_LV_MD); | ||
| 288 | |||
| 289 | return 0; | ||
| 290 | } | ||
| 291 | |||
| 292 | /* | ||
| 293 | * CICR4: PCLK_EN: Pixel clock is supplied by the sensor | ||
| 294 | * MCLK_EN: Master clock is generated by PXA | ||
| 295 | * PCP: Data sampled on the falling edge of pixel clock | ||
| 296 | */ | ||
| 297 | struct pxacamera_platform_data pcm990_pxacamera_platform_data = { | ||
| 298 | .init = pcm990_pxacamera_init, | ||
| 299 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 | | ||
| 300 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/, | ||
| 301 | .mclk_10khz = 1000, | ||
| 302 | }; | ||
| 303 | |||
| 304 | #include <linux/i2c/pca953x.h> | ||
| 305 | |||
| 306 | static struct pca953x_platform_data pca9536_data = { | ||
| 307 | .gpio_base = NR_BUILTIN_GPIO + 1, | ||
| 308 | }; | ||
| 309 | |||
| 310 | static struct soc_camera_link iclink[] = { | ||
| 311 | { | ||
| 312 | .bus_id = 0, /* Must match with the camera ID above */ | ||
| 313 | .gpio = NR_BUILTIN_GPIO + 1, | ||
| 314 | }, { | ||
| 315 | .bus_id = 0, /* Must match with the camera ID above */ | ||
| 316 | } | ||
| 317 | }; | ||
| 318 | |||
| 319 | /* Board I2C devices. */ | ||
| 320 | static struct i2c_board_info __initdata pcm990_i2c_devices[] = { | ||
| 321 | { | ||
| 322 | /* Must initialize before the camera(s) */ | ||
| 323 | I2C_BOARD_INFO("pca953x", 0x41), | ||
| 324 | .type = "pca9536", | ||
| 325 | .platform_data = &pca9536_data, | ||
| 326 | }, { | ||
| 327 | I2C_BOARD_INFO("mt9v022", 0x48), | ||
| 328 | .type = "mt9v022", | ||
| 329 | .platform_data = &iclink[0], /* With extender */ | ||
| 330 | }, { | ||
| 331 | I2C_BOARD_INFO("mt9m001", 0x5d), | ||
| 332 | .type = "mt9m001", | ||
| 333 | .platform_data = &iclink[0], /* With extender */ | ||
| 334 | }, | ||
| 335 | }; | ||
| 336 | #endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */ | ||
| 337 | |||
| 338 | /* | ||
| 261 | * AC97 support | 339 | * AC97 support |
| 262 | * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ | 340 | * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ |
| 263 | */ | 341 | */ |
| @@ -326,5 +404,14 @@ void __init pcm990_baseboard_init(void) | |||
| 326 | /* USB host */ | 404 | /* USB host */ |
| 327 | pxa_set_ohci_info(&pcm990_ohci_platform_data); | 405 | pxa_set_ohci_info(&pcm990_ohci_platform_data); |
| 328 | 406 | ||
| 407 | pxa_set_i2c_info(NULL); | ||
| 408 | |||
| 409 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) | ||
| 410 | pxa_set_camera_info(&pcm990_pxacamera_platform_data); | ||
| 411 | |||
| 412 | i2c_register_board_info(0, pcm990_i2c_devices, | ||
| 413 | ARRAY_SIZE(pcm990_i2c_devices)); | ||
| 414 | #endif | ||
| 415 | |||
| 329 | printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n"); | 416 | printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n"); |
| 330 | } | 417 | } |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 209eabf0ed3e..ca5ac196b47b 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <asm/mach/irq.h> | 32 | #include <asm/mach/irq.h> |
| 33 | 33 | ||
| 34 | #include <asm/arch/pxa-regs.h> | 34 | #include <asm/arch/pxa-regs.h> |
| 35 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 35 | #include <asm/arch/mmc.h> | 36 | #include <asm/arch/mmc.h> |
| 36 | #include <asm/arch/udc.h> | 37 | #include <asm/arch/udc.h> |
| 37 | #include <asm/arch/irda.h> | 38 | #include <asm/arch/irda.h> |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 599e53fcc2c5..d9b5450aee5b 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/hardware.h> | 26 | #include <asm/hardware.h> |
| 27 | #include <asm/arch/irqs.h> | 27 | #include <asm/arch/irqs.h> |
| 28 | #include <asm/arch/pxa-regs.h> | 28 | #include <asm/arch/pxa-regs.h> |
| 29 | #include <asm/arch/mfp-pxa25x.h> | ||
| 29 | #include <asm/arch/pm.h> | 30 | #include <asm/arch/pm.h> |
| 30 | #include <asm/arch/dma.h> | 31 | #include <asm/arch/dma.h> |
| 31 | 32 | ||
| @@ -129,6 +130,8 @@ static struct clk pxa25x_clks[] = { | |||
| 129 | INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), | 130 | INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), |
| 130 | INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), | 131 | INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), |
| 131 | 132 | ||
| 133 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), | ||
| 134 | |||
| 132 | /* | 135 | /* |
| 133 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), | 136 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), |
| 134 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), | 137 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), |
| @@ -228,24 +231,10 @@ static inline void pxa25x_init_pm(void) {} | |||
| 228 | static int pxa25x_set_wake(unsigned int irq, unsigned int on) | 231 | static int pxa25x_set_wake(unsigned int irq, unsigned int on) |
| 229 | { | 232 | { |
| 230 | int gpio = IRQ_TO_GPIO(irq); | 233 | int gpio = IRQ_TO_GPIO(irq); |
| 231 | uint32_t gpio_bit, mask = 0; | 234 | uint32_t mask = 0; |
| 232 | 235 | ||
| 233 | if (gpio >= 0 && gpio <= 15) { | 236 | if (gpio >= 0 && gpio < 85) |
| 234 | gpio_bit = GPIO_bit(gpio); | 237 | return gpio_set_wake(gpio, on); |
| 235 | mask = gpio_bit; | ||
| 236 | if (on) { | ||
| 237 | if (GRER(gpio) | gpio_bit) | ||
| 238 | PRER |= gpio_bit; | ||
| 239 | else | ||
| 240 | PRER &= ~gpio_bit; | ||
| 241 | |||
| 242 | if (GFER(gpio) | gpio_bit) | ||
| 243 | PFER |= gpio_bit; | ||
| 244 | else | ||
| 245 | PFER &= ~gpio_bit; | ||
| 246 | } | ||
| 247 | goto set_pwer; | ||
| 248 | } | ||
| 249 | 238 | ||
| 250 | if (irq == IRQ_RTCAlrm) { | 239 | if (irq == IRQ_RTCAlrm) { |
| 251 | mask = PWER_RTC; | 240 | mask = PWER_RTC; |
| @@ -265,9 +254,8 @@ set_pwer: | |||
| 265 | 254 | ||
| 266 | void __init pxa25x_init_irq(void) | 255 | void __init pxa25x_init_irq(void) |
| 267 | { | 256 | { |
| 268 | pxa_init_irq_low(); | 257 | pxa_init_irq(32, pxa25x_set_wake); |
| 269 | pxa_init_irq_gpio(85); | 258 | pxa_init_gpio(85, pxa25x_set_wake); |
| 270 | pxa_init_irq_set_wake(pxa25x_set_wake); | ||
| 271 | } | 259 | } |
| 272 | 260 | ||
| 273 | static struct platform_device *pxa25x_devices[] __initdata = { | 261 | static struct platform_device *pxa25x_devices[] __initdata = { |
| @@ -325,4 +313,4 @@ static int __init pxa25x_init(void) | |||
| 325 | return ret; | 313 | return ret; |
| 326 | } | 314 | } |
| 327 | 315 | ||
| 328 | subsys_initcall(pxa25x_init); | 316 | postcore_initcall(pxa25x_init); |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 46a951c3e5a0..7a2449dd0fd4 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <asm/arch/irqs.h> | 23 | #include <asm/arch/irqs.h> |
| 24 | #include <asm/arch/pxa-regs.h> | 24 | #include <asm/arch/pxa-regs.h> |
| 25 | #include <asm/arch/pxa2xx-regs.h> | 25 | #include <asm/arch/pxa2xx-regs.h> |
| 26 | #include <asm/arch/mfp-pxa27x.h> | ||
| 26 | #include <asm/arch/ohci.h> | 27 | #include <asm/arch/ohci.h> |
| 27 | #include <asm/arch/pm.h> | 28 | #include <asm/arch/pm.h> |
| 28 | #include <asm/arch/dma.h> | 29 | #include <asm/arch/dma.h> |
| @@ -151,12 +152,15 @@ static struct clk pxa27x_clks[] = { | |||
| 151 | 152 | ||
| 152 | INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), | 153 | INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), |
| 153 | INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), | 154 | INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), |
| 154 | INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), | 155 | INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), |
| 155 | 156 | ||
| 156 | INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), | 157 | INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), |
| 157 | INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), | 158 | INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), |
| 158 | INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), | 159 | INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), |
| 159 | 160 | ||
| 161 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), | ||
| 162 | INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), | ||
| 163 | |||
| 160 | /* | 164 | /* |
| 161 | INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), | 165 | INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), |
| 162 | INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), | 166 | INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), |
| @@ -283,37 +287,16 @@ static inline void pxa27x_init_pm(void) {} | |||
| 283 | /* PXA27x: Various gpios can issue wakeup events. This logic only | 287 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
| 284 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | 288 | * handles the simple cases, not the WEMUX2 and WEMUX3 options |
| 285 | */ | 289 | */ |
| 286 | #define PXA27x_GPIO_NOWAKE_MASK \ | ||
| 287 | ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) | ||
| 288 | #define WAKEMASK(gpio) \ | ||
| 289 | (((gpio) <= 15) \ | ||
| 290 | ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ | ||
| 291 | : ((gpio == 35) ? (1 << 24) : 0)) | ||
| 292 | |||
| 293 | static int pxa27x_set_wake(unsigned int irq, unsigned int on) | 290 | static int pxa27x_set_wake(unsigned int irq, unsigned int on) |
| 294 | { | 291 | { |
| 295 | int gpio = IRQ_TO_GPIO(irq); | 292 | int gpio = IRQ_TO_GPIO(irq); |
| 296 | uint32_t mask; | 293 | uint32_t mask; |
| 297 | 294 | ||
| 298 | if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) { | 295 | if (gpio >= 0 && gpio < 128) |
| 299 | if (WAKEMASK(gpio) == 0) | 296 | return gpio_set_wake(gpio, on); |
| 300 | return -EINVAL; | ||
| 301 | |||
| 302 | mask = WAKEMASK(gpio); | ||
| 303 | |||
| 304 | if (on) { | ||
| 305 | if (GRER(gpio) | GPIO_bit(gpio)) | ||
| 306 | PRER |= mask; | ||
| 307 | else | ||
| 308 | PRER &= ~mask; | ||
| 309 | 297 | ||
| 310 | if (GFER(gpio) | GPIO_bit(gpio)) | 298 | if (irq == IRQ_KEYPAD) |
| 311 | PFER |= mask; | 299 | return keypad_set_wake(on); |
| 312 | else | ||
| 313 | PFER &= ~mask; | ||
| 314 | } | ||
| 315 | goto set_pwer; | ||
| 316 | } | ||
| 317 | 300 | ||
| 318 | switch (irq) { | 301 | switch (irq) { |
| 319 | case IRQ_RTCAlrm: | 302 | case IRQ_RTCAlrm: |
| @@ -326,7 +309,6 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on) | |||
| 326 | return -EINVAL; | 309 | return -EINVAL; |
| 327 | } | 310 | } |
| 328 | 311 | ||
| 329 | set_pwer: | ||
| 330 | if (on) | 312 | if (on) |
| 331 | PWER |= mask; | 313 | PWER |= mask; |
| 332 | else | 314 | else |
| @@ -337,10 +319,8 @@ set_pwer: | |||
| 337 | 319 | ||
| 338 | void __init pxa27x_init_irq(void) | 320 | void __init pxa27x_init_irq(void) |
| 339 | { | 321 | { |
| 340 | pxa_init_irq_low(); | 322 | pxa_init_irq(34, pxa27x_set_wake); |
| 341 | pxa_init_irq_high(); | 323 | pxa_init_gpio(128, pxa27x_set_wake); |
| 342 | pxa_init_irq_gpio(128); | ||
| 343 | pxa_init_irq_set_wake(pxa27x_set_wake); | ||
| 344 | } | 324 | } |
| 345 | 325 | ||
| 346 | /* | 326 | /* |
| @@ -386,10 +366,6 @@ static struct platform_device *devices[] __initdata = { | |||
| 386 | 366 | ||
| 387 | static struct sys_device pxa27x_sysdev[] = { | 367 | static struct sys_device pxa27x_sysdev[] = { |
| 388 | { | 368 | { |
| 389 | .id = 0, | ||
| 390 | .cls = &pxa_irq_sysclass, | ||
| 391 | }, { | ||
| 392 | .id = 1, | ||
| 393 | .cls = &pxa_irq_sysclass, | 369 | .cls = &pxa_irq_sysclass, |
| 394 | }, { | 370 | }, { |
| 395 | .cls = &pxa_gpio_sysclass, | 371 | .cls = &pxa_gpio_sysclass, |
| @@ -420,4 +396,4 @@ static int __init pxa27x_init(void) | |||
| 420 | return ret; | 396 | return ret; |
| 421 | } | 397 | } |
| 422 | 398 | ||
| 423 | subsys_initcall(pxa27x_init); | 399 | postcore_initcall(pxa27x_init); |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 35f25fdaeba3..dde355e88fa1 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -110,6 +110,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void) | |||
| 110 | } | 110 | } |
| 111 | 111 | ||
| 112 | /* | 112 | /* |
| 113 | * Return the current AC97 clock frequency. | ||
| 114 | */ | ||
| 115 | static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | ||
| 116 | { | ||
| 117 | unsigned long rate = 312000000; | ||
| 118 | unsigned long ac97_div; | ||
| 119 | |||
| 120 | ac97_div = AC97_DIV; | ||
| 121 | |||
| 122 | /* This may loose precision for some rates but won't for the | ||
| 123 | * standard 24.576MHz. | ||
| 124 | */ | ||
| 125 | rate /= (ac97_div >> 12) & 0x7fff; | ||
| 126 | rate *= (ac97_div & 0xfff); | ||
| 127 | |||
| 128 | return rate; | ||
| 129 | } | ||
| 130 | |||
| 131 | /* | ||
| 113 | * Return the current HSIO bus clock frequency | 132 | * Return the current HSIO bus clock frequency |
| 114 | */ | 133 | */ |
| 115 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | 134 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) |
| @@ -156,6 +175,27 @@ static const struct clkops clk_pxa3xx_hsio_ops = { | |||
| 156 | .getrate = clk_pxa3xx_hsio_getrate, | 175 | .getrate = clk_pxa3xx_hsio_getrate, |
| 157 | }; | 176 | }; |
| 158 | 177 | ||
| 178 | static const struct clkops clk_pxa3xx_ac97_ops = { | ||
| 179 | .enable = clk_pxa3xx_cken_enable, | ||
| 180 | .disable = clk_pxa3xx_cken_disable, | ||
| 181 | .getrate = clk_pxa3xx_ac97_getrate, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static void clk_pout_enable(struct clk *clk) | ||
| 185 | { | ||
| 186 | OSCC |= OSCC_PEN; | ||
| 187 | } | ||
| 188 | |||
| 189 | static void clk_pout_disable(struct clk *clk) | ||
| 190 | { | ||
| 191 | OSCC &= ~OSCC_PEN; | ||
| 192 | } | ||
| 193 | |||
| 194 | static const struct clkops clk_pout_ops = { | ||
| 195 | .enable = clk_pout_enable, | ||
| 196 | .disable = clk_pout_disable, | ||
| 197 | }; | ||
| 198 | |||
| 159 | #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ | 199 | #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ |
| 160 | { \ | 200 | { \ |
| 161 | .name = _name, \ | 201 | .name = _name, \ |
| @@ -175,8 +215,16 @@ static const struct clkops clk_pxa3xx_hsio_ops = { | |||
| 175 | } | 215 | } |
| 176 | 216 | ||
| 177 | static struct clk pxa3xx_clks[] = { | 217 | static struct clk pxa3xx_clks[] = { |
| 178 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), | 218 | { |
| 179 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), | 219 | .name = "CLK_POUT", |
| 220 | .ops = &clk_pout_ops, | ||
| 221 | .rate = 13000000, | ||
| 222 | .delay = 70, | ||
| 223 | }, | ||
| 224 | |||
| 225 | PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), | ||
| 226 | PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), | ||
| 227 | PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), | ||
| 180 | 228 | ||
| 181 | PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), | 229 | PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), |
| 182 | PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | 230 | PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), |
| @@ -185,6 +233,7 @@ static struct clk pxa3xx_clks[] = { | |||
| 185 | PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | 233 | PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), |
| 186 | PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), | 234 | PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), |
| 187 | PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), | 235 | PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), |
| 236 | PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), | ||
| 188 | 237 | ||
| 189 | PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), | 238 | PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), |
| 190 | PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), | 239 | PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), |
| @@ -305,8 +354,10 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state) | |||
| 305 | /* | 354 | /* |
| 306 | * Don't sleep if no wakeup sources are defined | 355 | * Don't sleep if no wakeup sources are defined |
| 307 | */ | 356 | */ |
| 308 | if (wakeup_src == 0) | 357 | if (wakeup_src == 0) { |
| 358 | printk(KERN_ERR "Not suspending: no wakeup sources\n"); | ||
| 309 | return; | 359 | return; |
| 360 | } | ||
| 310 | 361 | ||
| 311 | switch (state) { | 362 | switch (state) { |
| 312 | case PM_SUSPEND_STANDBY: | 363 | case PM_SUSPEND_STANDBY: |
| @@ -446,15 +497,9 @@ static int pxa3xx_set_wake(unsigned int irq, unsigned int on) | |||
| 446 | 497 | ||
| 447 | return 0; | 498 | return 0; |
| 448 | } | 499 | } |
| 449 | |||
| 450 | static void pxa3xx_init_irq_pm(void) | ||
| 451 | { | ||
| 452 | pxa_init_irq_set_wake(pxa3xx_set_wake); | ||
| 453 | } | ||
| 454 | |||
| 455 | #else | 500 | #else |
| 456 | static inline void pxa3xx_init_pm(void) {} | 501 | static inline void pxa3xx_init_pm(void) {} |
| 457 | static inline void pxa3xx_init_irq_pm(void) {} | 502 | #define pxa3xx_set_wake NULL |
| 458 | #endif | 503 | #endif |
| 459 | 504 | ||
| 460 | void __init pxa3xx_init_irq(void) | 505 | void __init pxa3xx_init_irq(void) |
| @@ -465,10 +510,8 @@ void __init pxa3xx_init_irq(void) | |||
| 465 | value |= (1 << 6); | 510 | value |= (1 << 6); |
| 466 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | 511 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
| 467 | 512 | ||
| 468 | pxa_init_irq_low(); | 513 | pxa_init_irq(56, pxa3xx_set_wake); |
| 469 | pxa_init_irq_high(); | 514 | pxa_init_gpio(128, NULL); |
| 470 | pxa_init_irq_gpio(128); | ||
| 471 | pxa3xx_init_irq_pm(); | ||
| 472 | } | 515 | } |
| 473 | 516 | ||
| 474 | /* | 517 | /* |
| @@ -490,11 +533,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 490 | 533 | ||
| 491 | static struct sys_device pxa3xx_sysdev[] = { | 534 | static struct sys_device pxa3xx_sysdev[] = { |
| 492 | { | 535 | { |
| 493 | .id = 0, | ||
| 494 | .cls = &pxa_irq_sysclass, | 536 | .cls = &pxa_irq_sysclass, |
| 495 | }, { | 537 | }, { |
| 496 | .id = 1, | 538 | .cls = &pxa3xx_mfp_sysclass, |
| 497 | .cls = &pxa_irq_sysclass, | ||
| 498 | }, { | 539 | }, { |
| 499 | .cls = &pxa_gpio_sysclass, | 540 | .cls = &pxa_gpio_sysclass, |
| 500 | }, | 541 | }, |
| @@ -532,4 +573,4 @@ static int __init pxa3xx_init(void) | |||
| 532 | return ret; | 573 | return ret; |
| 533 | } | 574 | } |
| 534 | 575 | ||
| 535 | subsys_initcall(pxa3xx_init); | 576 | postcore_initcall(pxa3xx_init); |
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index f9d1b61e1185..34cd585075b0 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <asm/arch/pm.h> | 27 | #include <asm/arch/pm.h> |
| 28 | #include <asm/arch/pxa-regs.h> | 28 | #include <asm/arch/pxa-regs.h> |
| 29 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 29 | #include <asm/arch/sharpsl.h> | 30 | #include <asm/arch/sharpsl.h> |
| 30 | #include "sharpsl.h" | 31 | #include "sharpsl.h" |
| 31 | 32 | ||
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 9e7773fca01c..62a02c3927c5 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | 37 | ||
| 38 | #include <asm/arch/pxa-regs.h> | 38 | #include <asm/arch/pxa-regs.h> |
| 39 | #include <asm/arch/pxa2xx-regs.h> | 39 | #include <asm/arch/pxa2xx-regs.h> |
| 40 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 40 | #include <asm/arch/irda.h> | 41 | #include <asm/arch/irda.h> |
| 41 | #include <asm/arch/mmc.h> | 42 | #include <asm/arch/mmc.h> |
| 42 | #include <asm/arch/ohci.h> | 43 | #include <asm/arch/ohci.h> |
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 745a4dc7acdd..7a7f5f947cc5 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/arch/sharpsl.h> | 26 | #include <asm/arch/sharpsl.h> |
| 27 | #include <asm/arch/spitz.h> | 27 | #include <asm/arch/spitz.h> |
| 28 | #include <asm/arch/pxa-regs.h> | 28 | #include <asm/arch/pxa-regs.h> |
| 29 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 29 | #include "sharpsl.h" | 30 | #include "sharpsl.h" |
| 30 | 31 | ||
| 31 | #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ | 32 | #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index f99112d50b41..6458f6d371d9 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 24 | #include <linux/gpio_keys.h> | 24 | #include <linux/gpio_keys.h> |
| 25 | #include <linux/input.h> | 25 | #include <linux/input.h> |
| 26 | #include <linux/gpio.h> | ||
| 26 | 27 | ||
| 27 | #include <asm/setup.h> | 28 | #include <asm/setup.h> |
| 28 | #include <asm/memory.h> | 29 | #include <asm/memory.h> |
| @@ -32,7 +33,9 @@ | |||
| 32 | #include <asm/system.h> | 33 | #include <asm/system.h> |
| 33 | #include <asm/arch/pxa-regs.h> | 34 | #include <asm/arch/pxa-regs.h> |
| 34 | #include <asm/arch/pxa2xx-regs.h> | 35 | #include <asm/arch/pxa2xx-regs.h> |
| 36 | #include <asm/arch/mfp-pxa25x.h> | ||
| 35 | #include <asm/arch/irda.h> | 37 | #include <asm/arch/irda.h> |
| 38 | #include <asm/arch/i2c.h> | ||
| 36 | #include <asm/arch/mmc.h> | 39 | #include <asm/arch/mmc.h> |
| 37 | #include <asm/arch/udc.h> | 40 | #include <asm/arch/udc.h> |
| 38 | 41 | ||
| @@ -47,6 +50,110 @@ | |||
| 47 | #include "generic.h" | 50 | #include "generic.h" |
| 48 | #include "devices.h" | 51 | #include "devices.h" |
| 49 | 52 | ||
| 53 | static unsigned long tosa_pin_config[] = { | ||
| 54 | GPIO78_nCS_2, /* Scoop */ | ||
| 55 | GPIO80_nCS_4, /* tg6393xb */ | ||
| 56 | GPIO33_nCS_5, /* Scoop */ | ||
| 57 | |||
| 58 | // GPIO76 CARD_VCC_ON1 | ||
| 59 | |||
| 60 | GPIO19_GPIO, /* Reset out */ | ||
| 61 | GPIO1_RST | WAKEUP_ON_EDGE_FALL, | ||
| 62 | |||
| 63 | GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* WAKE_UP */ | ||
| 64 | GPIO2_GPIO | WAKEUP_ON_EDGE_BOTH, /* AC_IN */ | ||
| 65 | GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* RECORD */ | ||
| 66 | GPIO4_GPIO | WAKEUP_ON_EDGE_FALL, /* SYNC */ | ||
| 67 | GPIO20_GPIO, /* EAR_IN */ | ||
| 68 | GPIO22_GPIO, /* On */ | ||
| 69 | |||
| 70 | GPIO5_GPIO, /* USB_IN */ | ||
| 71 | GPIO32_GPIO, /* Pen IRQ */ | ||
| 72 | |||
| 73 | GPIO7_GPIO, /* Jacket Detect */ | ||
| 74 | GPIO14_GPIO, /* BAT0_CRG */ | ||
| 75 | GPIO12_GPIO, /* BAT1_CRG */ | ||
| 76 | GPIO17_GPIO, /* BAT0_LOW */ | ||
| 77 | GPIO84_GPIO, /* BAT1_LOW */ | ||
| 78 | GPIO38_GPIO, /* BAT_LOCK */ | ||
| 79 | |||
| 80 | GPIO11_3_6MHz, | ||
| 81 | GPIO15_GPIO, /* TC6393XB IRQ */ | ||
| 82 | GPIO18_RDY, | ||
| 83 | GPIO27_GPIO, /* LCD Sync */ | ||
| 84 | |||
| 85 | /* MMC */ | ||
| 86 | GPIO6_MMC_CLK, | ||
| 87 | GPIO8_MMC_CS0, | ||
| 88 | GPIO9_GPIO, /* Detect */ | ||
| 89 | // GPIO10 nSD_INT | ||
| 90 | |||
| 91 | /* CF */ | ||
| 92 | GPIO13_GPIO, /* CD_IRQ */ | ||
| 93 | GPIO21_GPIO, /* Main Slot IRQ */ | ||
| 94 | GPIO36_GPIO, /* Jacket Slot IRQ */ | ||
| 95 | GPIO48_nPOE, | ||
| 96 | GPIO49_nPWE, | ||
| 97 | GPIO50_nPIOR, | ||
| 98 | GPIO51_nPIOW, | ||
| 99 | GPIO52_nPCE_1, | ||
| 100 | GPIO53_nPCE_2, | ||
| 101 | GPIO54_nPSKTSEL, | ||
| 102 | GPIO55_nPREG, | ||
| 103 | GPIO56_nPWAIT, | ||
| 104 | GPIO57_nIOIS16, | ||
| 105 | |||
| 106 | /* AC97 */ | ||
| 107 | GPIO31_AC97_SYNC, | ||
| 108 | GPIO30_AC97_SDATA_OUT, | ||
| 109 | GPIO28_AC97_BITCLK, | ||
| 110 | GPIO29_AC97_SDATA_IN_0, | ||
| 111 | // GPIO79 nAUD_IRQ | ||
| 112 | |||
| 113 | /* FFUART */ | ||
| 114 | GPIO34_FFUART_RXD, | ||
| 115 | GPIO35_FFUART_CTS, | ||
| 116 | GPIO37_FFUART_DSR, | ||
| 117 | GPIO39_FFUART_TXD, | ||
| 118 | GPIO40_FFUART_DTR, | ||
| 119 | GPIO41_FFUART_RTS, | ||
| 120 | |||
| 121 | /* BTUART */ | ||
| 122 | GPIO42_BTUART_RXD, | ||
| 123 | GPIO43_BTUART_TXD, | ||
| 124 | GPIO44_BTUART_CTS, | ||
| 125 | GPIO45_BTUART_RTS, | ||
| 126 | |||
| 127 | /* IrDA */ | ||
| 128 | GPIO46_STUART_RXD, | ||
| 129 | GPIO47_STUART_TXD, | ||
| 130 | |||
| 131 | /* Keybd */ | ||
| 132 | GPIO58_GPIO, | ||
| 133 | GPIO59_GPIO, | ||
| 134 | GPIO60_GPIO, | ||
| 135 | GPIO61_GPIO, | ||
| 136 | GPIO62_GPIO, | ||
| 137 | GPIO63_GPIO, | ||
| 138 | GPIO64_GPIO, | ||
| 139 | GPIO65_GPIO, | ||
| 140 | GPIO66_GPIO, | ||
| 141 | GPIO67_GPIO, | ||
| 142 | GPIO68_GPIO, | ||
| 143 | GPIO69_GPIO, | ||
| 144 | GPIO70_GPIO, | ||
| 145 | GPIO71_GPIO, | ||
| 146 | GPIO72_GPIO, | ||
| 147 | GPIO73_GPIO, | ||
| 148 | GPIO74_GPIO, | ||
| 149 | GPIO75_GPIO, | ||
| 150 | |||
| 151 | /* SPI */ | ||
| 152 | GPIO81_SSP2_CLK_OUT, | ||
| 153 | GPIO82_SSP2_FRM_OUT, | ||
| 154 | GPIO83_SSP2_TXD, | ||
| 155 | }; | ||
| 156 | |||
| 50 | /* | 157 | /* |
| 51 | * SCOOP Device | 158 | * SCOOP Device |
| 52 | */ | 159 | */ |
| @@ -60,11 +167,10 @@ static struct resource tosa_scoop_resources[] = { | |||
| 60 | 167 | ||
| 61 | static struct scoop_config tosa_scoop_setup = { | 168 | static struct scoop_config tosa_scoop_setup = { |
| 62 | .io_dir = TOSA_SCOOP_IO_DIR, | 169 | .io_dir = TOSA_SCOOP_IO_DIR, |
| 63 | .io_out = TOSA_SCOOP_IO_OUT, | 170 | .gpio_base = TOSA_SCOOP_GPIO_BASE, |
| 64 | |||
| 65 | }; | 171 | }; |
| 66 | 172 | ||
| 67 | struct platform_device tosascoop_device = { | 173 | static struct platform_device tosascoop_device = { |
| 68 | .name = "sharp-scoop", | 174 | .name = "sharp-scoop", |
| 69 | .id = 0, | 175 | .id = 0, |
| 70 | .dev = { | 176 | .dev = { |
| @@ -88,10 +194,10 @@ static struct resource tosa_scoop_jc_resources[] = { | |||
| 88 | 194 | ||
| 89 | static struct scoop_config tosa_scoop_jc_setup = { | 195 | static struct scoop_config tosa_scoop_jc_setup = { |
| 90 | .io_dir = TOSA_SCOOP_JC_IO_DIR, | 196 | .io_dir = TOSA_SCOOP_JC_IO_DIR, |
| 91 | .io_out = TOSA_SCOOP_JC_IO_OUT, | 197 | .gpio_base = TOSA_SCOOP_JC_GPIO_BASE, |
| 92 | }; | 198 | }; |
| 93 | 199 | ||
| 94 | struct platform_device tosascoop_jc_device = { | 200 | static struct platform_device tosascoop_jc_device = { |
| 95 | .name = "sharp-scoop", | 201 | .name = "sharp-scoop", |
| 96 | .id = 1, | 202 | .id = 1, |
| 97 | .dev = { | 203 | .dev = { |
| @@ -118,50 +224,16 @@ static struct scoop_pcmcia_dev tosa_pcmcia_scoop[] = { | |||
| 118 | }, | 224 | }, |
| 119 | }; | 225 | }; |
| 120 | 226 | ||
| 121 | static void tosa_pcmcia_init(void) | ||
| 122 | { | ||
| 123 | /* Setup default state of GPIO outputs | ||
| 124 | before we enable them as outputs. */ | ||
| 125 | GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) | | ||
| 126 | GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) | | ||
| 127 | GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) | | ||
| 128 | GPIO_bit(GPIO53_nPCE_2); | ||
| 129 | |||
| 130 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
| 131 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
| 132 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
| 133 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
| 134 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
| 135 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
| 136 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
| 137 | pxa_gpio_mode(GPIO52_nPCE_1_MD); | ||
| 138 | pxa_gpio_mode(GPIO53_nPCE_2_MD); | ||
| 139 | pxa_gpio_mode(GPIO54_pSKTSEL_MD); | ||
| 140 | } | ||
| 141 | |||
| 142 | static struct scoop_pcmcia_config tosa_pcmcia_config = { | 227 | static struct scoop_pcmcia_config tosa_pcmcia_config = { |
| 143 | .devs = &tosa_pcmcia_scoop[0], | 228 | .devs = &tosa_pcmcia_scoop[0], |
| 144 | .num_devs = 2, | 229 | .num_devs = 2, |
| 145 | .pcmcia_init = tosa_pcmcia_init, | ||
| 146 | }; | 230 | }; |
| 147 | 231 | ||
| 148 | /* | 232 | /* |
| 149 | * USB Device Controller | 233 | * USB Device Controller |
| 150 | */ | 234 | */ |
| 151 | static void tosa_udc_command(int cmd) | ||
| 152 | { | ||
| 153 | switch(cmd) { | ||
| 154 | case PXA2XX_UDC_CMD_CONNECT: | ||
| 155 | set_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP); | ||
| 156 | break; | ||
| 157 | case PXA2XX_UDC_CMD_DISCONNECT: | ||
| 158 | reset_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP); | ||
| 159 | break; | ||
| 160 | } | ||
| 161 | } | ||
| 162 | |||
| 163 | static struct pxa2xx_udc_mach_info udc_info __initdata = { | 235 | static struct pxa2xx_udc_mach_info udc_info __initdata = { |
| 164 | .udc_command = tosa_udc_command, | 236 | .gpio_pullup = TOSA_GPIO_USB_PULLUP, |
| 165 | .gpio_vbus = TOSA_GPIO_USB_IN, | 237 | .gpio_vbus = TOSA_GPIO_USB_IN, |
| 166 | .gpio_vbus_inverted = 1, | 238 | .gpio_vbus_inverted = 1, |
| 167 | }; | 239 | }; |
| @@ -175,19 +247,44 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void | |||
| 175 | { | 247 | { |
| 176 | int err; | 248 | int err; |
| 177 | 249 | ||
| 178 | /* setup GPIO for PXA25x MMC controller */ | ||
| 179 | pxa_gpio_mode(GPIO6_MMCCLK_MD); | ||
| 180 | pxa_gpio_mode(GPIO8_MMCCS0_MD); | ||
| 181 | pxa_gpio_mode(TOSA_GPIO_nSD_DETECT | GPIO_IN); | ||
| 182 | |||
| 183 | tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250); | 250 | tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250); |
| 184 | 251 | ||
| 185 | err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int, | 252 | err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int, |
| 186 | IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | 253 | IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 187 | "MMC/SD card detect", data); | 254 | "MMC/SD card detect", data); |
| 188 | if (err) | 255 | if (err) { |
| 189 | printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); | 256 | printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); |
| 257 | goto err_irq; | ||
| 258 | } | ||
| 190 | 259 | ||
| 260 | err = gpio_request(TOSA_GPIO_SD_WP, "sd_wp"); | ||
| 261 | if (err) { | ||
| 262 | printk(KERN_ERR "tosa_mci_init: can't request SD_WP gpio\n"); | ||
| 263 | goto err_gpio_wp; | ||
| 264 | } | ||
| 265 | err = gpio_direction_input(TOSA_GPIO_SD_WP); | ||
| 266 | if (err) | ||
| 267 | goto err_gpio_wp_dir; | ||
| 268 | |||
| 269 | err = gpio_request(TOSA_GPIO_PWR_ON, "sd_pwr"); | ||
| 270 | if (err) { | ||
| 271 | printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n"); | ||
| 272 | goto err_gpio_pwr; | ||
| 273 | } | ||
| 274 | err = gpio_direction_output(TOSA_GPIO_PWR_ON, 0); | ||
| 275 | if (err) | ||
| 276 | goto err_gpio_pwr_dir; | ||
| 277 | |||
| 278 | return 0; | ||
| 279 | |||
| 280 | err_gpio_pwr_dir: | ||
| 281 | gpio_free(TOSA_GPIO_PWR_ON); | ||
| 282 | err_gpio_pwr: | ||
| 283 | err_gpio_wp_dir: | ||
| 284 | gpio_free(TOSA_GPIO_SD_WP); | ||
| 285 | err_gpio_wp: | ||
| 286 | free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data); | ||
| 287 | err_irq: | ||
| 191 | return err; | 288 | return err; |
| 192 | } | 289 | } |
| 193 | 290 | ||
| @@ -196,19 +293,21 @@ static void tosa_mci_setpower(struct device *dev, unsigned int vdd) | |||
| 196 | struct pxamci_platform_data* p_d = dev->platform_data; | 293 | struct pxamci_platform_data* p_d = dev->platform_data; |
| 197 | 294 | ||
| 198 | if (( 1 << vdd) & p_d->ocr_mask) { | 295 | if (( 1 << vdd) & p_d->ocr_mask) { |
| 199 | set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON); | 296 | gpio_set_value(TOSA_GPIO_PWR_ON, 1); |
| 200 | } else { | 297 | } else { |
| 201 | reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON); | 298 | gpio_set_value(TOSA_GPIO_PWR_ON, 0); |
| 202 | } | 299 | } |
| 203 | } | 300 | } |
| 204 | 301 | ||
| 205 | static int tosa_mci_get_ro(struct device *dev) | 302 | static int tosa_mci_get_ro(struct device *dev) |
| 206 | { | 303 | { |
| 207 | return (read_scoop_reg(&tosascoop_device.dev, SCOOP_GPWR)&TOSA_SCOOP_SD_WP); | 304 | return gpio_get_value(TOSA_GPIO_SD_WP); |
| 208 | } | 305 | } |
| 209 | 306 | ||
| 210 | static void tosa_mci_exit(struct device *dev, void *data) | 307 | static void tosa_mci_exit(struct device *dev, void *data) |
| 211 | { | 308 | { |
| 309 | gpio_free(TOSA_GPIO_PWR_ON); | ||
| 310 | gpio_free(TOSA_GPIO_SD_WP); | ||
| 212 | free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data); | 311 | free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data); |
| 213 | } | 312 | } |
| 214 | 313 | ||
| @@ -223,21 +322,36 @@ static struct pxamci_platform_data tosa_mci_platform_data = { | |||
| 223 | /* | 322 | /* |
| 224 | * Irda | 323 | * Irda |
| 225 | */ | 324 | */ |
| 226 | static void tosa_irda_transceiver_mode(struct device *dev, int mode) | 325 | static int tosa_irda_startup(struct device *dev) |
| 227 | { | 326 | { |
| 228 | if (mode & IR_OFF) { | 327 | int ret; |
| 229 | reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN); | 328 | |
| 230 | pxa_gpio_mode(GPIO47_STTXD|GPIO_DFLT_LOW); | 329 | ret = gpio_request(TOSA_GPIO_IR_POWERDWN, "IrDA powerdown"); |
| 231 | pxa_gpio_mode(GPIO47_STTXD|GPIO_OUT); | 330 | if (ret) |
| 232 | } else { | 331 | return ret; |
| 233 | pxa_gpio_mode(GPIO47_STTXD_MD); | 332 | |
| 234 | set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN); | 333 | ret = gpio_direction_output(TOSA_GPIO_IR_POWERDWN, 0); |
| 334 | if (ret) | ||
| 335 | gpio_free(TOSA_GPIO_IR_POWERDWN); | ||
| 336 | |||
| 337 | return ret; | ||
| 235 | } | 338 | } |
| 339 | |||
| 340 | static void tosa_irda_shutdown(struct device *dev) | ||
| 341 | { | ||
| 342 | gpio_free(TOSA_GPIO_IR_POWERDWN); | ||
| 343 | } | ||
| 344 | |||
| 345 | static void tosa_irda_transceiver_mode(struct device *dev, int mode) | ||
| 346 | { | ||
| 347 | gpio_set_value(TOSA_GPIO_IR_POWERDWN, !(mode & IR_OFF)); | ||
| 236 | } | 348 | } |
| 237 | 349 | ||
| 238 | static struct pxaficp_platform_data tosa_ficp_platform_data = { | 350 | static struct pxaficp_platform_data tosa_ficp_platform_data = { |
| 239 | .transceiver_cap = IR_SIRMODE | IR_OFF, | 351 | .transceiver_cap = IR_SIRMODE | IR_OFF, |
| 240 | .transceiver_mode = tosa_irda_transceiver_mode, | 352 | .transceiver_mode = tosa_irda_transceiver_mode, |
| 353 | .startup = tosa_irda_startup, | ||
| 354 | .shutdown = tosa_irda_shutdown, | ||
| 241 | }; | 355 | }; |
| 242 | 356 | ||
| 243 | /* | 357 | /* |
| @@ -249,12 +363,28 @@ static struct platform_device tosakbd_device = { | |||
| 249 | }; | 363 | }; |
| 250 | 364 | ||
| 251 | static struct gpio_keys_button tosa_gpio_keys[] = { | 365 | static struct gpio_keys_button tosa_gpio_keys[] = { |
| 366 | /* | ||
| 367 | * Two following keys are directly tied to "ON" button of tosa. Why? | ||
| 368 | * The first one can be used as a wakeup source, the second can't; | ||
| 369 | * also the first one is OR of ac_powered and on_button. | ||
| 370 | */ | ||
| 371 | { | ||
| 372 | .type = EV_PWR, | ||
| 373 | .code = KEY_RESERVED, | ||
| 374 | .gpio = TOSA_GPIO_POWERON, | ||
| 375 | .desc = "Poweron", | ||
| 376 | .wakeup = 1, | ||
| 377 | .active_low = 1, | ||
| 378 | }, | ||
| 252 | { | 379 | { |
| 253 | .type = EV_PWR, | 380 | .type = EV_PWR, |
| 254 | .code = KEY_SUSPEND, | 381 | .code = KEY_SUSPEND, |
| 255 | .gpio = TOSA_GPIO_ON_KEY, | 382 | .gpio = TOSA_GPIO_ON_KEY, |
| 256 | .desc = "On key", | 383 | .desc = "On key", |
| 257 | .wakeup = 1, | 384 | /* |
| 385 | * can't be used as wakeup | ||
| 386 | * .wakeup = 1, | ||
| 387 | */ | ||
| 258 | .active_low = 1, | 388 | .active_low = 1, |
| 259 | }, | 389 | }, |
| 260 | { | 390 | { |
| @@ -291,9 +421,40 @@ static struct platform_device tosa_gpio_keys_device = { | |||
| 291 | /* | 421 | /* |
| 292 | * Tosa LEDs | 422 | * Tosa LEDs |
| 293 | */ | 423 | */ |
| 424 | static struct gpio_led tosa_gpio_leds[] = { | ||
| 425 | { | ||
| 426 | .name = "tosa:amber:charge", | ||
| 427 | .default_trigger = "main-battery-charging", | ||
| 428 | .gpio = TOSA_GPIO_CHRG_ERR_LED, | ||
| 429 | }, | ||
| 430 | { | ||
| 431 | .name = "tosa:green:mail", | ||
| 432 | .default_trigger = "nand-disk", | ||
| 433 | .gpio = TOSA_GPIO_NOTE_LED, | ||
| 434 | }, | ||
| 435 | { | ||
| 436 | .name = "tosa:dual:wlan", | ||
| 437 | .default_trigger = "none", | ||
| 438 | .gpio = TOSA_GPIO_WLAN_LED, | ||
| 439 | }, | ||
| 440 | { | ||
| 441 | .name = "tosa:blue:bluetooth", | ||
| 442 | .default_trigger = "none", | ||
| 443 | .gpio = TOSA_GPIO_BT_LED, | ||
| 444 | }, | ||
| 445 | }; | ||
| 446 | |||
| 447 | static struct gpio_led_platform_data tosa_gpio_leds_platform_data = { | ||
| 448 | .leds = tosa_gpio_leds, | ||
| 449 | .num_leds = ARRAY_SIZE(tosa_gpio_leds), | ||
| 450 | }; | ||
| 451 | |||
| 294 | static struct platform_device tosaled_device = { | 452 | static struct platform_device tosaled_device = { |
| 295 | .name = "tosa-led", | 453 | .name = "leds-gpio", |
| 296 | .id = -1, | 454 | .id = -1, |
| 455 | .dev = { | ||
| 456 | .platform_data = &tosa_gpio_leds_platform_data, | ||
| 457 | }, | ||
| 297 | }; | 458 | }; |
| 298 | 459 | ||
| 299 | static struct platform_device *devices[] __initdata = { | 460 | static struct platform_device *devices[] __initdata = { |
| @@ -326,20 +487,13 @@ static void tosa_restart(char mode) | |||
| 326 | 487 | ||
| 327 | static void __init tosa_init(void) | 488 | static void __init tosa_init(void) |
| 328 | { | 489 | { |
| 490 | pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config)); | ||
| 491 | gpio_set_wake(MFP_PIN_GPIO1, 1); | ||
| 492 | /* We can't pass to gpio-keys since it will drop the Reset altfunc */ | ||
| 493 | |||
| 329 | pm_power_off = tosa_poweroff; | 494 | pm_power_off = tosa_poweroff; |
| 330 | arm_pm_restart = tosa_restart; | 495 | arm_pm_restart = tosa_restart; |
| 331 | 496 | ||
| 332 | pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN); | ||
| 333 | pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN); | ||
| 334 | pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN); | ||
| 335 | |||
| 336 | /* setup sleep mode values */ | ||
| 337 | PWER = 0x00000002; | ||
| 338 | PFER = 0x00000000; | ||
| 339 | PRER = 0x00000002; | ||
| 340 | PGSR0 = 0x00000000; | ||
| 341 | PGSR1 = 0x00FF0002; | ||
| 342 | PGSR2 = 0x00014000; | ||
| 343 | PCFR |= PCFR_OPDE; | 497 | PCFR |= PCFR_OPDE; |
| 344 | 498 | ||
| 345 | /* enable batt_fault */ | 499 | /* enable batt_fault */ |
| @@ -348,6 +502,7 @@ static void __init tosa_init(void) | |||
| 348 | pxa_set_mci_info(&tosa_mci_platform_data); | 502 | pxa_set_mci_info(&tosa_mci_platform_data); |
| 349 | pxa_set_udc_info(&udc_info); | 503 | pxa_set_udc_info(&udc_info); |
| 350 | pxa_set_ficp_info(&tosa_ficp_platform_data); | 504 | pxa_set_ficp_info(&tosa_ficp_platform_data); |
| 505 | pxa_set_i2c_info(NULL); | ||
| 351 | platform_scoop_config = &tosa_pcmcia_config; | 506 | platform_scoop_config = &tosa_pcmcia_config; |
| 352 | 507 | ||
| 353 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 508 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index f207fcd30cd7..931885d86b91 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #include <asm/mach/flash.h> | 41 | #include <asm/mach/flash.h> |
| 42 | 42 | ||
| 43 | #include <asm/arch/pxa-regs.h> | 43 | #include <asm/arch/pxa-regs.h> |
| 44 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 44 | #include <asm/arch/trizeps4.h> | 45 | #include <asm/arch/trizeps4.h> |
| 45 | #include <asm/arch/audio.h> | 46 | #include <asm/arch/audio.h> |
| 46 | #include <asm/arch/pxafb.h> | 47 | #include <asm/arch/pxafb.h> |
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index afd2cbfca0d9..dbb546216be1 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/arch/pxafb.h> | 26 | #include <asm/arch/pxafb.h> |
| 27 | #include <asm/arch/zylonite.h> | 27 | #include <asm/arch/zylonite.h> |
| 28 | #include <asm/arch/mmc.h> | 28 | #include <asm/arch/mmc.h> |
| 29 | #include <asm/arch/pxa27x_keypad.h> | ||
| 29 | 30 | ||
| 30 | #include "generic.h" | 31 | #include "generic.h" |
| 31 | 32 | ||
| @@ -35,6 +36,8 @@ struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS]; | |||
| 35 | int gpio_backlight; | 36 | int gpio_backlight; |
| 36 | int gpio_eth_irq; | 37 | int gpio_eth_irq; |
| 37 | 38 | ||
| 39 | int wm9713_irq; | ||
| 40 | |||
| 38 | int lcd_id; | 41 | int lcd_id; |
| 39 | int lcd_orientation; | 42 | int lcd_orientation; |
| 40 | 43 | ||
| @@ -249,6 +252,71 @@ static void __init zylonite_init_mmc(void) | |||
| 249 | static inline void zylonite_init_mmc(void) {} | 252 | static inline void zylonite_init_mmc(void) {} |
| 250 | #endif | 253 | #endif |
| 251 | 254 | ||
| 255 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES) | ||
| 256 | static unsigned int zylonite_matrix_key_map[] = { | ||
| 257 | /* KEY(row, col, key_code) */ | ||
| 258 | KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D), | ||
| 259 | KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H), | ||
| 260 | KEY(2, 0, KEY_I), KEY(2, 1, KEY_J), KEY(2, 2, KEY_K), KEY(2, 5, KEY_L), | ||
| 261 | KEY(3, 0, KEY_M), KEY(3, 1, KEY_N), KEY(3, 2, KEY_O), KEY(3, 5, KEY_P), | ||
| 262 | KEY(5, 0, KEY_Q), KEY(5, 1, KEY_R), KEY(5, 2, KEY_S), KEY(5, 5, KEY_T), | ||
| 263 | KEY(6, 0, KEY_U), KEY(6, 1, KEY_V), KEY(6, 2, KEY_W), KEY(6, 5, KEY_X), | ||
| 264 | KEY(7, 1, KEY_Y), KEY(7, 2, KEY_Z), | ||
| 265 | |||
| 266 | KEY(4, 4, KEY_0), KEY(1, 3, KEY_1), KEY(4, 1, KEY_2), KEY(1, 4, KEY_3), | ||
| 267 | KEY(2, 3, KEY_4), KEY(4, 2, KEY_5), KEY(2, 4, KEY_6), KEY(3, 3, KEY_7), | ||
| 268 | KEY(4, 3, KEY_8), KEY(3, 4, KEY_9), | ||
| 269 | |||
| 270 | KEY(4, 5, KEY_SPACE), | ||
| 271 | KEY(5, 3, KEY_KPASTERISK), /* * */ | ||
| 272 | KEY(5, 4, KEY_KPDOT), /* #" */ | ||
| 273 | |||
| 274 | KEY(0, 7, KEY_UP), | ||
| 275 | KEY(1, 7, KEY_DOWN), | ||
| 276 | KEY(2, 7, KEY_LEFT), | ||
| 277 | KEY(3, 7, KEY_RIGHT), | ||
| 278 | KEY(2, 6, KEY_HOME), | ||
| 279 | KEY(3, 6, KEY_END), | ||
| 280 | KEY(6, 4, KEY_DELETE), | ||
| 281 | KEY(6, 6, KEY_BACK), | ||
| 282 | KEY(6, 3, KEY_CAPSLOCK), /* KEY_LEFTSHIFT), */ | ||
| 283 | |||
| 284 | KEY(4, 6, KEY_ENTER), /* scroll push */ | ||
| 285 | KEY(5, 7, KEY_ENTER), /* keypad action */ | ||
| 286 | |||
| 287 | KEY(0, 4, KEY_EMAIL), | ||
| 288 | KEY(5, 6, KEY_SEND), | ||
| 289 | KEY(4, 0, KEY_CALENDAR), | ||
| 290 | KEY(7, 6, KEY_RECORD), | ||
| 291 | KEY(6, 7, KEY_VOLUMEUP), | ||
| 292 | KEY(7, 7, KEY_VOLUMEDOWN), | ||
| 293 | |||
| 294 | KEY(0, 6, KEY_F22), /* soft1 */ | ||
| 295 | KEY(1, 6, KEY_F23), /* soft2 */ | ||
| 296 | KEY(0, 3, KEY_AUX), /* contact */ | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct pxa27x_keypad_platform_data zylonite_keypad_info = { | ||
| 300 | .matrix_key_rows = 8, | ||
| 301 | .matrix_key_cols = 8, | ||
| 302 | .matrix_key_map = zylonite_matrix_key_map, | ||
| 303 | .matrix_key_map_size = ARRAY_SIZE(zylonite_matrix_key_map), | ||
| 304 | |||
| 305 | .enable_rotary0 = 1, | ||
| 306 | .rotary0_up_key = KEY_UP, | ||
| 307 | .rotary0_down_key = KEY_DOWN, | ||
| 308 | |||
| 309 | .debounce_interval = 30, | ||
| 310 | }; | ||
| 311 | |||
| 312 | static void __init zylonite_init_keypad(void) | ||
| 313 | { | ||
| 314 | pxa_set_keypad_info(&zylonite_keypad_info); | ||
| 315 | } | ||
| 316 | #else | ||
| 317 | static inline void zylonite_init_keypad(void) {} | ||
| 318 | #endif | ||
| 319 | |||
| 252 | static void __init zylonite_init(void) | 320 | static void __init zylonite_init(void) |
| 253 | { | 321 | { |
| 254 | /* board-processor specific initialization */ | 322 | /* board-processor specific initialization */ |
| @@ -265,6 +333,7 @@ static void __init zylonite_init(void) | |||
| 265 | 333 | ||
| 266 | zylonite_init_lcd(); | 334 | zylonite_init_lcd(); |
| 267 | zylonite_init_mmc(); | 335 | zylonite_init_mmc(); |
| 336 | zylonite_init_keypad(); | ||
| 268 | } | 337 | } |
| 269 | 338 | ||
| 270 | MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") | 339 | MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") |
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 6ac04c09b0e9..324fb9daae28 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | #include <asm/arch/mfp-pxa300.h> | 21 | #include <asm/arch/mfp-pxa300.h> |
| 22 | #include <asm/arch/zylonite.h> | 22 | #include <asm/arch/zylonite.h> |
| 23 | 23 | ||
| 24 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | 24 | #include "generic.h" |
| 25 | 25 | ||
| 26 | /* PXA300/PXA310 common configurations */ | 26 | /* PXA300/PXA310 common configurations */ |
| 27 | static mfp_cfg_t common_mfp_cfg[] __initdata = { | 27 | static mfp_cfg_t common_mfp_cfg[] __initdata = { |
| @@ -69,6 +69,9 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { | |||
| 69 | GPIO27_AC97_SDATA_OUT, | 69 | GPIO27_AC97_SDATA_OUT, |
| 70 | GPIO28_AC97_SYNC, | 70 | GPIO28_AC97_SYNC, |
| 71 | 71 | ||
| 72 | /* WM9713 IRQ */ | ||
| 73 | GPIO26_GPIO, | ||
| 74 | |||
| 72 | /* Keypad */ | 75 | /* Keypad */ |
| 73 | GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH, | 76 | GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH, |
| 74 | GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH, | 77 | GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH, |
| @@ -203,6 +206,9 @@ void __init zylonite_pxa300_init(void) | |||
| 203 | /* MMC card detect & write protect for controller 0 */ | 206 | /* MMC card detect & write protect for controller 0 */ |
| 204 | zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0); | 207 | zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0); |
| 205 | zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2); | 208 | zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2); |
| 209 | |||
| 210 | /* WM9713 IRQ */ | ||
| 211 | wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26); | ||
| 206 | } | 212 | } |
| 207 | 213 | ||
| 208 | if (cpu_is_pxa300()) { | 214 | if (cpu_is_pxa300()) { |
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index dfa79992b8ab..193d07903b06 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | #include <asm/arch/mfp-pxa320.h> | 21 | #include <asm/arch/mfp-pxa320.h> |
| 22 | #include <asm/arch/zylonite.h> | 22 | #include <asm/arch/zylonite.h> |
| 23 | 23 | ||
| 24 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | 24 | #include "generic.h" |
| 25 | 25 | ||
| 26 | static mfp_cfg_t mfp_cfg[] __initdata = { | 26 | static mfp_cfg_t mfp_cfg[] __initdata = { |
| 27 | /* LCD */ | 27 | /* LCD */ |
| @@ -68,6 +68,9 @@ static mfp_cfg_t mfp_cfg[] __initdata = { | |||
| 68 | GPIO39_AC97_BITCLK, | 68 | GPIO39_AC97_BITCLK, |
| 69 | GPIO40_AC97_nACRESET, | 69 | GPIO40_AC97_nACRESET, |
| 70 | 70 | ||
| 71 | /* WM9713 IRQ */ | ||
| 72 | GPIO15_GPIO, | ||
| 73 | |||
| 71 | /* I2C */ | 74 | /* I2C */ |
| 72 | GPIO32_I2C_SCL, | 75 | GPIO32_I2C_SCL, |
| 73 | GPIO33_I2C_SDA, | 76 | GPIO33_I2C_SDA, |
| @@ -190,5 +193,8 @@ void __init zylonite_pxa320_init(void) | |||
| 190 | /* MMC card detect & write protect for controller 0 */ | 193 | /* MMC card detect & write protect for controller 0 */ |
| 191 | zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1); | 194 | zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1); |
| 192 | zylonite_mmc_slot[0].gpio_wp = mfp_to_gpio(MFP_PIN_GPIO5); | 195 | zylonite_mmc_slot[0].gpio_wp = mfp_to_gpio(MFP_PIN_GPIO5); |
| 196 | |||
| 197 | /* WM9713 IRQ */ | ||
| 198 | wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO15); | ||
| 193 | } | 199 | } |
| 194 | } | 200 | } |
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 39b3bb7f1020..5ccde7cf39e8 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig | |||
| @@ -10,7 +10,6 @@ config MACH_REALVIEW_EB | |||
| 10 | config REALVIEW_EB_ARM11MP | 10 | config REALVIEW_EB_ARM11MP |
| 11 | bool "Support ARM11MPCore tile" | 11 | bool "Support ARM11MPCore tile" |
| 12 | depends on MACH_REALVIEW_EB | 12 | depends on MACH_REALVIEW_EB |
| 13 | select CACHE_L2X0 | ||
| 14 | help | 13 | help |
| 15 | Enable support for the ARM11MPCore tile on the Realview platform. | 14 | Enable support for the ARM11MPCore tile on the Realview platform. |
| 16 | 15 | ||
| @@ -24,4 +23,18 @@ config REALVIEW_EB_ARM11MP_REVB | |||
| 24 | kernel built with this option enabled is not compatible with | 23 | kernel built with this option enabled is not compatible with |
| 25 | other revisions of the ARM11MPCore tile. | 24 | other revisions of the ARM11MPCore tile. |
| 26 | 25 | ||
| 26 | config MACH_REALVIEW_PB11MP | ||
| 27 | bool "Support RealView/PB11MPCore platform" | ||
| 28 | select ARM_GIC | ||
| 29 | help | ||
| 30 | Include support for the ARM(R) RealView MPCore Platform Baseboard. | ||
| 31 | PB11MPCore is a platform with an on-board ARM11MPCore and has | ||
| 32 | support for PCI-E and Compact Flash. | ||
| 33 | |||
| 34 | config MACH_REALVIEW_PB1176 | ||
| 35 | bool "Support RealView/PB1176 platform" | ||
| 36 | select ARM_GIC | ||
| 37 | help | ||
| 38 | Include support for the ARM(R) RealView ARM1176 Platform Baseboard. | ||
| 39 | |||
| 27 | endmenu | 40 | endmenu |
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index ca1e390c3c28..d2ae077431dd 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile | |||
| @@ -4,5 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | obj-y := core.o clock.o | 5 | obj-y := core.o clock.o |
| 6 | obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o | 6 | obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o |
| 7 | obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o | ||
| 8 | obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o | ||
| 7 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o | 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o |
| 8 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 98aefc9f4df3..131990d196f5 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -109,22 +109,21 @@ static struct flash_platform_data realview_flash_data = { | |||
| 109 | .set_vpp = realview_flash_set_vpp, | 109 | .set_vpp = realview_flash_set_vpp, |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | static struct resource realview_flash_resource = { | ||
| 113 | .start = REALVIEW_FLASH_BASE, | ||
| 114 | .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE, | ||
| 115 | .flags = IORESOURCE_MEM, | ||
| 116 | }; | ||
| 117 | |||
| 118 | struct platform_device realview_flash_device = { | 112 | struct platform_device realview_flash_device = { |
| 119 | .name = "armflash", | 113 | .name = "armflash", |
| 120 | .id = 0, | 114 | .id = 0, |
| 121 | .dev = { | 115 | .dev = { |
| 122 | .platform_data = &realview_flash_data, | 116 | .platform_data = &realview_flash_data, |
| 123 | }, | 117 | }, |
| 124 | .num_resources = 1, | ||
| 125 | .resource = &realview_flash_resource, | ||
| 126 | }; | 118 | }; |
| 127 | 119 | ||
| 120 | int realview_flash_register(struct resource *res, u32 num) | ||
| 121 | { | ||
| 122 | realview_flash_device.resource = res; | ||
| 123 | realview_flash_device.num_resources = num; | ||
| 124 | return platform_device_register(&realview_flash_device); | ||
| 125 | } | ||
| 126 | |||
| 128 | static struct resource realview_i2c_resource = { | 127 | static struct resource realview_i2c_resource = { |
| 129 | .start = REALVIEW_I2C_BASE, | 128 | .start = REALVIEW_I2C_BASE, |
| 130 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | 129 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, |
| @@ -445,10 +444,10 @@ void realview_leds_event(led_event_t ledevt) | |||
| 445 | /* | 444 | /* |
| 446 | * Where is the timer (VA)? | 445 | * Where is the timer (VA)? |
| 447 | */ | 446 | */ |
| 448 | #define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE) | 447 | void __iomem *timer0_va_base; |
| 449 | #define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20) | 448 | void __iomem *timer1_va_base; |
| 450 | #define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE) | 449 | void __iomem *timer2_va_base; |
| 451 | #define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20) | 450 | void __iomem *timer3_va_base; |
| 452 | 451 | ||
| 453 | /* | 452 | /* |
| 454 | * How long is the timer interval? | 453 | * How long is the timer interval? |
| @@ -475,7 +474,7 @@ static void timer_set_mode(enum clock_event_mode mode, | |||
| 475 | 474 | ||
| 476 | switch(mode) { | 475 | switch(mode) { |
| 477 | case CLOCK_EVT_MODE_PERIODIC: | 476 | case CLOCK_EVT_MODE_PERIODIC: |
| 478 | writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); | 477 | writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD); |
| 479 | 478 | ||
| 480 | ctrl = TIMER_CTRL_PERIODIC; | 479 | ctrl = TIMER_CTRL_PERIODIC; |
| 481 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; | 480 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; |
| @@ -491,16 +490,16 @@ static void timer_set_mode(enum clock_event_mode mode, | |||
| 491 | ctrl = 0; | 490 | ctrl = 0; |
| 492 | } | 491 | } |
| 493 | 492 | ||
| 494 | writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); | 493 | writel(ctrl, timer0_va_base + TIMER_CTRL); |
| 495 | } | 494 | } |
| 496 | 495 | ||
| 497 | static int timer_set_next_event(unsigned long evt, | 496 | static int timer_set_next_event(unsigned long evt, |
| 498 | struct clock_event_device *unused) | 497 | struct clock_event_device *unused) |
| 499 | { | 498 | { |
| 500 | unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); | 499 | unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL); |
| 501 | 500 | ||
| 502 | writel(evt, TIMER0_VA_BASE + TIMER_LOAD); | 501 | writel(evt, timer0_va_base + TIMER_LOAD); |
| 503 | writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); | 502 | writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL); |
| 504 | 503 | ||
| 505 | return 0; | 504 | return 0; |
| 506 | } | 505 | } |
| @@ -536,7 +535,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) | |||
| 536 | struct clock_event_device *evt = &timer0_clockevent; | 535 | struct clock_event_device *evt = &timer0_clockevent; |
| 537 | 536 | ||
| 538 | /* clear the interrupt */ | 537 | /* clear the interrupt */ |
| 539 | writel(1, TIMER0_VA_BASE + TIMER_INTCLR); | 538 | writel(1, timer0_va_base + TIMER_INTCLR); |
| 540 | 539 | ||
| 541 | evt->event_handler(evt); | 540 | evt->event_handler(evt); |
| 542 | 541 | ||
| @@ -551,7 +550,7 @@ static struct irqaction realview_timer_irq = { | |||
| 551 | 550 | ||
| 552 | static cycle_t realview_get_cycles(void) | 551 | static cycle_t realview_get_cycles(void) |
| 553 | { | 552 | { |
| 554 | return ~readl(TIMER3_VA_BASE + TIMER_VALUE); | 553 | return ~readl(timer3_va_base + TIMER_VALUE); |
| 555 | } | 554 | } |
| 556 | 555 | ||
| 557 | static struct clocksource clocksource_realview = { | 556 | static struct clocksource clocksource_realview = { |
| @@ -566,11 +565,11 @@ static struct clocksource clocksource_realview = { | |||
| 566 | static void __init realview_clocksource_init(void) | 565 | static void __init realview_clocksource_init(void) |
| 567 | { | 566 | { |
| 568 | /* setup timer 0 as free-running clocksource */ | 567 | /* setup timer 0 as free-running clocksource */ |
| 569 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | 568 | writel(0, timer3_va_base + TIMER_CTRL); |
| 570 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); | 569 | writel(0xffffffff, timer3_va_base + TIMER_LOAD); |
| 571 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); | 570 | writel(0xffffffff, timer3_va_base + TIMER_VALUE); |
| 572 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | 571 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
| 573 | TIMER3_VA_BASE + TIMER_CTRL); | 572 | timer3_va_base + TIMER_CTRL); |
| 574 | 573 | ||
| 575 | clocksource_realview.mult = | 574 | clocksource_realview.mult = |
| 576 | clocksource_khz2mult(1000, clocksource_realview.shift); | 575 | clocksource_khz2mult(1000, clocksource_realview.shift); |
| @@ -607,10 +606,10 @@ void __init realview_timer_init(unsigned int timer_irq) | |||
| 607 | /* | 606 | /* |
| 608 | * Initialise to a known state (all timers off) | 607 | * Initialise to a known state (all timers off) |
| 609 | */ | 608 | */ |
| 610 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | 609 | writel(0, timer0_va_base + TIMER_CTRL); |
| 611 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | 610 | writel(0, timer1_va_base + TIMER_CTRL); |
| 612 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | 611 | writel(0, timer2_va_base + TIMER_CTRL); |
| 613 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | 612 | writel(0, timer3_va_base + TIMER_CTRL); |
| 614 | 613 | ||
| 615 | /* | 614 | /* |
| 616 | * Make irqs happen for the system timer | 615 | * Make irqs happen for the system timer |
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 492a14c0d604..33dbbb41a663 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h | |||
| @@ -55,8 +55,13 @@ extern void __iomem *gic_cpu_base_addr; | |||
| 55 | extern void __iomem *twd_base_addr; | 55 | extern void __iomem *twd_base_addr; |
| 56 | extern unsigned int twd_size; | 56 | extern unsigned int twd_size; |
| 57 | #endif | 57 | #endif |
| 58 | extern void __iomem *timer0_va_base; | ||
| 59 | extern void __iomem *timer1_va_base; | ||
| 60 | extern void __iomem *timer2_va_base; | ||
| 61 | extern void __iomem *timer3_va_base; | ||
| 58 | 62 | ||
| 59 | extern void realview_leds_event(led_event_t ledevt); | 63 | extern void realview_leds_event(led_event_t ledevt); |
| 60 | extern void realview_timer_init(unsigned int timer_irq); | 64 | extern void realview_timer_init(unsigned int timer_irq); |
| 65 | extern int realview_flash_register(struct resource *res, u32 num); | ||
| 61 | 66 | ||
| 62 | #endif | 67 | #endif |
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index de2b7159557d..3e57428affee 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c | |||
| @@ -15,11 +15,14 @@ | |||
| 15 | #include <linux/smp.h> | 15 | #include <linux/smp.h> |
| 16 | 16 | ||
| 17 | #include <asm/cacheflush.h> | 17 | #include <asm/cacheflush.h> |
| 18 | #include <asm/hardware/arm_scu.h> | ||
| 19 | #include <asm/hardware.h> | 18 | #include <asm/hardware.h> |
| 20 | #include <asm/io.h> | 19 | #include <asm/io.h> |
| 21 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 22 | 21 | ||
| 22 | #include <asm/arch/board-eb.h> | ||
| 23 | #include <asm/arch/board-pb11mp.h> | ||
| 24 | #include <asm/arch/scu.h> | ||
| 25 | |||
| 23 | extern void realview_secondary_startup(void); | 26 | extern void realview_secondary_startup(void); |
| 24 | 27 | ||
| 25 | /* | 28 | /* |
| @@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1; | |||
| 31 | static unsigned int __init get_core_count(void) | 34 | static unsigned int __init get_core_count(void) |
| 32 | { | 35 | { |
| 33 | unsigned int ncores; | 36 | unsigned int ncores; |
| 37 | void __iomem *scu_base = 0; | ||
| 38 | |||
| 39 | if (machine_is_realview_eb() && core_tile_eb11mp()) | ||
| 40 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); | ||
| 41 | else if (machine_is_realview_pb11mp()) | ||
| 42 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); | ||
| 34 | 43 | ||
| 35 | if (machine_is_realview_eb() && core_tile_eb11mp()) { | 44 | if (scu_base) { |
| 36 | ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); | 45 | ncores = __raw_readl(scu_base + SCU_CONFIG); |
| 37 | ncores = (ncores & 0x03) + 1; | 46 | ncores = (ncores & 0x03) + 1; |
| 38 | } else | 47 | } else |
| 39 | ncores = 1; | 48 | ncores = 1; |
| @@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void) | |||
| 41 | return ncores; | 50 | return ncores; |
| 42 | } | 51 | } |
| 43 | 52 | ||
| 53 | /* | ||
| 54 | * Setup the SCU | ||
| 55 | */ | ||
| 56 | static void scu_enable(void) | ||
| 57 | { | ||
| 58 | u32 scu_ctrl; | ||
| 59 | void __iomem *scu_base; | ||
| 60 | |||
| 61 | if (machine_is_realview_eb() && core_tile_eb11mp()) | ||
| 62 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); | ||
| 63 | else if (machine_is_realview_pb11mp()) | ||
| 64 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); | ||
| 65 | else | ||
| 66 | BUG(); | ||
| 67 | |||
| 68 | scu_ctrl = __raw_readl(scu_base + SCU_CTRL); | ||
| 69 | scu_ctrl |= 1; | ||
| 70 | __raw_writel(scu_ctrl, scu_base + SCU_CTRL); | ||
| 71 | } | ||
| 72 | |||
| 44 | static DEFINE_SPINLOCK(boot_lock); | 73 | static DEFINE_SPINLOCK(boot_lock); |
| 45 | 74 | ||
| 46 | void __cpuinit platform_secondary_init(unsigned int cpu) | 75 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| @@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
| 57 | * core (e.g. timer irq), then they will not have been enabled | 86 | * core (e.g. timer irq), then they will not have been enabled |
| 58 | * for us: do so | 87 | * for us: do so |
| 59 | */ | 88 | */ |
| 60 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); | 89 | if (machine_is_realview_eb() && core_tile_eb11mp()) |
| 90 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); | ||
| 91 | else if (machine_is_realview_pb11mp()) | ||
| 92 | gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); | ||
| 61 | 93 | ||
| 62 | /* | 94 | /* |
| 63 | * let the primary processor know we're out of the | 95 | * let the primary processor know we're out of the |
| @@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 198 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in | 230 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in |
| 199 | * realview_timer_init | 231 | * realview_timer_init |
| 200 | */ | 232 | */ |
| 201 | if (machine_is_realview_eb() && core_tile_eb11mp()) | 233 | if ((machine_is_realview_eb() && core_tile_eb11mp()) || |
| 234 | machine_is_realview_pb11mp()) | ||
| 202 | local_timer_setup(cpu); | 235 | local_timer_setup(cpu); |
| 203 | #endif | 236 | #endif |
| 204 | 237 | ||
| @@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 210 | cpu_set(i, cpu_present_map); | 243 | cpu_set(i, cpu_present_map); |
| 211 | 244 | ||
| 212 | /* | 245 | /* |
| 213 | * Do we need any more CPUs? If so, then let them know where | 246 | * Initialise the SCU if there are more than one CPU and let |
| 214 | * to start. Note that, on modern versions of MILO, the "poke" | 247 | * them know where to start. Note that, on modern versions of |
| 215 | * doesn't actually do anything until each individual core is | 248 | * MILO, the "poke" doesn't actually do anything until each |
| 216 | * sent a soft interrupt to get it out of WFI | 249 | * individual core is sent a soft interrupt to get it out of |
| 250 | * WFI | ||
| 217 | */ | 251 | */ |
| 218 | if (max_cpus > 1) | 252 | if (max_cpus > 1) { |
| 253 | scu_enable(); | ||
| 219 | poke_milo(); | 254 | poke_milo(); |
| 255 | } | ||
| 220 | } | 256 | } |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 60d9eb810246..5782d83fd886 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -51,13 +51,13 @@ static struct map_desc realview_eb_io_desc[] __initdata = { | |||
| 51 | .length = SZ_4K, | 51 | .length = SZ_4K, |
| 52 | .type = MT_DEVICE, | 52 | .type = MT_DEVICE, |
| 53 | }, { | 53 | }, { |
| 54 | .virtual = IO_ADDRESS(REALVIEW_GIC_CPU_BASE), | 54 | .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE), |
| 55 | .pfn = __phys_to_pfn(REALVIEW_GIC_CPU_BASE), | 55 | .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE), |
| 56 | .length = SZ_4K, | 56 | .length = SZ_4K, |
| 57 | .type = MT_DEVICE, | 57 | .type = MT_DEVICE, |
| 58 | }, { | 58 | }, { |
| 59 | .virtual = IO_ADDRESS(REALVIEW_GIC_DIST_BASE), | 59 | .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE), |
| 60 | .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), | 60 | .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE), |
| 61 | .length = SZ_4K, | 61 | .length = SZ_4K, |
| 62 | .type = MT_DEVICE, | 62 | .type = MT_DEVICE, |
| 63 | }, { | 63 | }, { |
| @@ -66,20 +66,20 @@ static struct map_desc realview_eb_io_desc[] __initdata = { | |||
| 66 | .length = SZ_4K, | 66 | .length = SZ_4K, |
| 67 | .type = MT_DEVICE, | 67 | .type = MT_DEVICE, |
| 68 | }, { | 68 | }, { |
| 69 | .virtual = IO_ADDRESS(REALVIEW_TIMER0_1_BASE), | 69 | .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE), |
| 70 | .pfn = __phys_to_pfn(REALVIEW_TIMER0_1_BASE), | 70 | .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE), |
| 71 | .length = SZ_4K, | 71 | .length = SZ_4K, |
| 72 | .type = MT_DEVICE, | 72 | .type = MT_DEVICE, |
| 73 | }, { | 73 | }, { |
| 74 | .virtual = IO_ADDRESS(REALVIEW_TIMER2_3_BASE), | 74 | .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE), |
| 75 | .pfn = __phys_to_pfn(REALVIEW_TIMER2_3_BASE), | 75 | .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE), |
| 76 | .length = SZ_4K, | 76 | .length = SZ_4K, |
| 77 | .type = MT_DEVICE, | 77 | .type = MT_DEVICE, |
| 78 | }, | 78 | }, |
| 79 | #ifdef CONFIG_DEBUG_LL | 79 | #ifdef CONFIG_DEBUG_LL |
| 80 | { | 80 | { |
| 81 | .virtual = IO_ADDRESS(REALVIEW_UART0_BASE), | 81 | .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE), |
| 82 | .pfn = __phys_to_pfn(REALVIEW_UART0_BASE), | 82 | .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE), |
| 83 | .length = SZ_4K, | 83 | .length = SZ_4K, |
| 84 | .type = MT_DEVICE, | 84 | .type = MT_DEVICE, |
| 85 | } | 85 | } |
| @@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void) | |||
| 136 | /* | 136 | /* |
| 137 | * These devices are connected directly to the multi-layer AHB switch | 137 | * These devices are connected directly to the multi-layer AHB switch |
| 138 | */ | 138 | */ |
| 139 | #define SMC_IRQ { NO_IRQ, NO_IRQ } | 139 | #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } |
| 140 | #define SMC_DMA { 0, 0 } | 140 | #define EB_SMC_DMA { 0, 0 } |
| 141 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 141 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
| 142 | #define MPMC_DMA { 0, 0 } | 142 | #define MPMC_DMA { 0, 0 } |
| 143 | #define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } | 143 | #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } |
| 144 | #define CLCD_DMA { 0, 0 } | 144 | #define EB_CLCD_DMA { 0, 0 } |
| 145 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } | 145 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } |
| 146 | #define DMAC_DMA { 0, 0 } | 146 | #define DMAC_DMA { 0, 0 } |
| 147 | 147 | ||
| @@ -150,53 +150,53 @@ static void __init realview_eb_map_io(void) | |||
| 150 | */ | 150 | */ |
| 151 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 151 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
| 152 | #define SCTL_DMA { 0, 0 } | 152 | #define SCTL_DMA { 0, 0 } |
| 153 | #define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } | 153 | #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } |
| 154 | #define WATCHDOG_DMA { 0, 0 } | 154 | #define EB_WATCHDOG_DMA { 0, 0 } |
| 155 | #define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } | 155 | #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } |
| 156 | #define GPIO0_DMA { 0, 0 } | 156 | #define EB_GPIO0_DMA { 0, 0 } |
| 157 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } | 157 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } |
| 158 | #define GPIO1_DMA { 0, 0 } | 158 | #define GPIO1_DMA { 0, 0 } |
| 159 | #define RTC_IRQ { IRQ_EB_RTC, NO_IRQ } | 159 | #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } |
| 160 | #define RTC_DMA { 0, 0 } | 160 | #define EB_RTC_DMA { 0, 0 } |
| 161 | 161 | ||
| 162 | /* | 162 | /* |
| 163 | * These devices are connected via the DMA APB bridge | 163 | * These devices are connected via the DMA APB bridge |
| 164 | */ | 164 | */ |
| 165 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } | 165 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } |
| 166 | #define SCI_DMA { 7, 6 } | 166 | #define SCI_DMA { 7, 6 } |
| 167 | #define UART0_IRQ { IRQ_EB_UART0, NO_IRQ } | 167 | #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } |
| 168 | #define UART0_DMA { 15, 14 } | 168 | #define EB_UART0_DMA { 15, 14 } |
| 169 | #define UART1_IRQ { IRQ_EB_UART1, NO_IRQ } | 169 | #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } |
| 170 | #define UART1_DMA { 13, 12 } | 170 | #define EB_UART1_DMA { 13, 12 } |
| 171 | #define UART2_IRQ { IRQ_EB_UART2, NO_IRQ } | 171 | #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } |
| 172 | #define UART2_DMA { 11, 10 } | 172 | #define EB_UART2_DMA { 11, 10 } |
| 173 | #define UART3_IRQ { IRQ_EB_UART3, NO_IRQ } | 173 | #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } |
| 174 | #define UART3_DMA { 0x86, 0x87 } | 174 | #define EB_UART3_DMA { 0x86, 0x87 } |
| 175 | #define SSP_IRQ { IRQ_EB_SSP, NO_IRQ } | 175 | #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } |
| 176 | #define SSP_DMA { 9, 8 } | 176 | #define EB_SSP_DMA { 9, 8 } |
| 177 | 177 | ||
| 178 | /* FPGA Primecells */ | 178 | /* FPGA Primecells */ |
| 179 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | 179 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); |
| 180 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); | 180 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); |
| 181 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | 181 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); |
| 182 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | 182 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); |
| 183 | AMBA_DEVICE(uart3, "fpga:09", UART3, NULL); | 183 | AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL); |
| 184 | 184 | ||
| 185 | /* DevChip Primecells */ | 185 | /* DevChip Primecells */ |
| 186 | AMBA_DEVICE(smc, "dev:00", SMC, NULL); | 186 | AMBA_DEVICE(smc, "dev:00", EB_SMC, NULL); |
| 187 | AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); | 187 | AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data); |
| 188 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); | 188 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); |
| 189 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 189 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 190 | AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); | 190 | AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL); |
| 191 | AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL); | 191 | AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL); |
| 192 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 192 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); |
| 193 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 193 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); |
| 194 | AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); | 194 | AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL); |
| 195 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 195 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 196 | AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); | 196 | AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL); |
| 197 | AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); | 197 | AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL); |
| 198 | AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); | 198 | AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL); |
| 199 | AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); | 199 | AMBA_DEVICE(ssp0, "dev:f4", EB_SSP, NULL); |
| 200 | 200 | ||
| 201 | static struct amba_device *amba_devs[] __initdata = { | 201 | static struct amba_device *amba_devs[] __initdata = { |
| 202 | &dmac_device, | 202 | &dmac_device, |
| @@ -223,11 +223,16 @@ static struct amba_device *amba_devs[] __initdata = { | |||
| 223 | /* | 223 | /* |
| 224 | * RealView EB platform devices | 224 | * RealView EB platform devices |
| 225 | */ | 225 | */ |
| 226 | static struct resource realview_eb_flash_resource = { | ||
| 227 | .start = REALVIEW_EB_FLASH_BASE, | ||
| 228 | .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1, | ||
| 229 | .flags = IORESOURCE_MEM, | ||
| 230 | }; | ||
| 226 | 231 | ||
| 227 | static struct resource realview_eb_smc91x_resources[] = { | 232 | static struct resource realview_eb_eth_resources[] = { |
| 228 | [0] = { | 233 | [0] = { |
| 229 | .start = REALVIEW_ETH_BASE, | 234 | .start = REALVIEW_EB_ETH_BASE, |
| 230 | .end = REALVIEW_ETH_BASE + SZ_64K - 1, | 235 | .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1, |
| 231 | .flags = IORESOURCE_MEM, | 236 | .flags = IORESOURCE_MEM, |
| 232 | }, | 237 | }, |
| 233 | [1] = { | 238 | [1] = { |
| @@ -237,13 +242,36 @@ static struct resource realview_eb_smc91x_resources[] = { | |||
| 237 | }, | 242 | }, |
| 238 | }; | 243 | }; |
| 239 | 244 | ||
| 240 | static struct platform_device realview_eb_smc91x_device = { | 245 | static struct platform_device realview_eb_eth_device = { |
| 241 | .name = "smc91x", | ||
| 242 | .id = 0, | 246 | .id = 0, |
| 243 | .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources), | 247 | .num_resources = ARRAY_SIZE(realview_eb_eth_resources), |
| 244 | .resource = realview_eb_smc91x_resources, | 248 | .resource = realview_eb_eth_resources, |
| 245 | }; | 249 | }; |
| 246 | 250 | ||
| 251 | /* | ||
| 252 | * Detect and register the correct Ethernet device. RealView/EB rev D | ||
| 253 | * platforms use the newer SMSC LAN9118 Ethernet chip | ||
| 254 | */ | ||
| 255 | static int eth_device_register(void) | ||
| 256 | { | ||
| 257 | void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K); | ||
| 258 | u32 idrev; | ||
| 259 | |||
| 260 | if (!eth_addr) | ||
| 261 | return -ENOMEM; | ||
| 262 | |||
| 263 | idrev = readl(eth_addr + 0x50); | ||
| 264 | if ((idrev & 0xFFFF0000) == 0x01180000) | ||
| 265 | /* SMSC LAN9118 chip present */ | ||
| 266 | realview_eb_eth_device.name = "smc911x"; | ||
| 267 | else | ||
| 268 | /* SMSC 91C111 chip present */ | ||
| 269 | realview_eb_eth_device.name = "smc91x"; | ||
| 270 | |||
| 271 | iounmap(eth_addr); | ||
| 272 | return platform_device_register(&realview_eb_eth_device); | ||
| 273 | } | ||
| 274 | |||
| 247 | static void __init gic_init_irq(void) | 275 | static void __init gic_init_irq(void) |
| 248 | { | 276 | { |
| 249 | if (core_tile_eb11mp()) { | 277 | if (core_tile_eb11mp()) { |
| @@ -263,14 +291,14 @@ static void __init gic_init_irq(void) | |||
| 263 | 291 | ||
| 264 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB | 292 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB |
| 265 | /* board GIC, secondary */ | 293 | /* board GIC, secondary */ |
| 266 | gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); | 294 | gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); |
| 267 | gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); | 295 | gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); |
| 268 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); | 296 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); |
| 269 | #endif | 297 | #endif |
| 270 | } else { | 298 | } else { |
| 271 | /* board GIC, primary */ | 299 | /* board GIC, primary */ |
| 272 | gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE); | 300 | gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); |
| 273 | gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); | 301 | gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); |
| 274 | gic_cpu_init(0, gic_cpu_base_addr); | 302 | gic_cpu_init(0, gic_cpu_base_addr); |
| 275 | } | 303 | } |
| 276 | } | 304 | } |
| @@ -301,14 +329,19 @@ static void realview_eb11mp_fixup(void) | |||
| 301 | kmi1_device.irq[0] = IRQ_EB11MP_KMI1; | 329 | kmi1_device.irq[0] = IRQ_EB11MP_KMI1; |
| 302 | 330 | ||
| 303 | /* platform devices */ | 331 | /* platform devices */ |
| 304 | realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; | 332 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; |
| 305 | realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; | 333 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; |
| 306 | } | 334 | } |
| 307 | 335 | ||
| 308 | static void __init realview_eb_timer_init(void) | 336 | static void __init realview_eb_timer_init(void) |
| 309 | { | 337 | { |
| 310 | unsigned int timer_irq; | 338 | unsigned int timer_irq; |
| 311 | 339 | ||
| 340 | timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); | ||
| 341 | timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; | ||
| 342 | timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); | ||
| 343 | timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; | ||
| 344 | |||
| 312 | if (core_tile_eb11mp()) { | 345 | if (core_tile_eb11mp()) { |
| 313 | #ifdef CONFIG_LOCAL_TIMERS | 346 | #ifdef CONFIG_LOCAL_TIMERS |
| 314 | twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); | 347 | twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); |
| @@ -332,16 +365,18 @@ static void __init realview_eb_init(void) | |||
| 332 | if (core_tile_eb11mp()) { | 365 | if (core_tile_eb11mp()) { |
| 333 | realview_eb11mp_fixup(); | 366 | realview_eb11mp_fixup(); |
| 334 | 367 | ||
| 368 | #ifdef CONFIG_CACHE_L2X0 | ||
| 335 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled | 369 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled |
| 336 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ | 370 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ |
| 337 | l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); | 371 | l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); |
| 372 | #endif | ||
| 338 | } | 373 | } |
| 339 | 374 | ||
| 340 | clk_register(&realview_clcd_clk); | 375 | clk_register(&realview_clcd_clk); |
| 341 | 376 | ||
| 342 | platform_device_register(&realview_flash_device); | 377 | realview_flash_register(&realview_eb_flash_resource, 1); |
| 343 | platform_device_register(&realview_eb_smc91x_device); | ||
| 344 | platform_device_register(&realview_i2c_device); | 378 | platform_device_register(&realview_i2c_device); |
| 379 | eth_device_register(); | ||
| 345 | 380 | ||
| 346 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 381 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 347 | struct amba_device *d = amba_devs[i]; | 382 | struct amba_device *d = amba_devs[i]; |
| @@ -355,8 +390,8 @@ static void __init realview_eb_init(void) | |||
| 355 | 390 | ||
| 356 | MACHINE_START(REALVIEW_EB, "ARM-RealView EB") | 391 | MACHINE_START(REALVIEW_EB, "ARM-RealView EB") |
| 357 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | 392 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
| 358 | .phys_io = REALVIEW_UART0_BASE, | 393 | .phys_io = REALVIEW_EB_UART0_BASE, |
| 359 | .io_pg_offst = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc, | 394 | .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, |
| 360 | .boot_params = 0x00000100, | 395 | .boot_params = 0x00000100, |
| 361 | .map_io = realview_eb_map_io, | 396 | .map_io = realview_eb_map_io, |
| 362 | .init_irq = gic_init_irq, | 397 | .init_irq = gic_init_irq, |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c new file mode 100644 index 000000000000..cf7f576a5860 --- /dev/null +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -0,0 +1,292 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/realview_pb1176.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/sysdev.h> | ||
| 25 | #include <linux/amba/bus.h> | ||
| 26 | |||
| 27 | #include <asm/hardware.h> | ||
| 28 | #include <asm/io.h> | ||
| 29 | #include <asm/irq.h> | ||
| 30 | #include <asm/leds.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/hardware/gic.h> | ||
| 33 | #include <asm/hardware/icst307.h> | ||
| 34 | #include <asm/hardware/cache-l2x0.h> | ||
| 35 | |||
| 36 | #include <asm/mach/arch.h> | ||
| 37 | #include <asm/mach/flash.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/mmc.h> | ||
| 40 | #include <asm/mach/time.h> | ||
| 41 | |||
| 42 | #include <asm/arch/board-pb1176.h> | ||
| 43 | #include <asm/arch/irqs.h> | ||
| 44 | |||
| 45 | #include "core.h" | ||
| 46 | #include "clock.h" | ||
| 47 | |||
| 48 | static struct map_desc realview_pb1176_io_desc[] __initdata = { | ||
| 49 | { | ||
| 50 | .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), | ||
| 51 | .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), | ||
| 52 | .length = SZ_4K, | ||
| 53 | .type = MT_DEVICE, | ||
| 54 | }, { | ||
| 55 | .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE), | ||
| 56 | .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE), | ||
| 57 | .length = SZ_4K, | ||
| 58 | .type = MT_DEVICE, | ||
| 59 | }, { | ||
| 60 | .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE), | ||
| 61 | .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE), | ||
| 62 | .length = SZ_4K, | ||
| 63 | .type = MT_DEVICE, | ||
| 64 | }, { | ||
| 65 | .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE), | ||
| 66 | .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE), | ||
| 67 | .length = SZ_4K, | ||
| 68 | .type = MT_DEVICE, | ||
| 69 | }, { | ||
| 70 | .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE), | ||
| 71 | .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE), | ||
| 72 | .length = SZ_4K, | ||
| 73 | .type = MT_DEVICE, | ||
| 74 | }, { | ||
| 75 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | ||
| 76 | .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), | ||
| 77 | .length = SZ_4K, | ||
| 78 | .type = MT_DEVICE, | ||
| 79 | }, { | ||
| 80 | .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE), | ||
| 81 | .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE), | ||
| 82 | .length = SZ_4K, | ||
| 83 | .type = MT_DEVICE, | ||
| 84 | }, { | ||
| 85 | .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE), | ||
| 86 | .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE), | ||
| 87 | .length = SZ_4K, | ||
| 88 | .type = MT_DEVICE, | ||
| 89 | }, { | ||
| 90 | .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE), | ||
| 91 | .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE), | ||
| 92 | .length = SZ_8K, | ||
| 93 | .type = MT_DEVICE, | ||
| 94 | }, | ||
| 95 | #ifdef CONFIG_DEBUG_LL | ||
| 96 | { | ||
| 97 | .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE), | ||
| 98 | .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE), | ||
| 99 | .length = SZ_4K, | ||
| 100 | .type = MT_DEVICE, | ||
| 101 | }, | ||
| 102 | #endif | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init realview_pb1176_map_io(void) | ||
| 106 | { | ||
| 107 | iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc)); | ||
| 108 | } | ||
| 109 | |||
| 110 | /* | ||
| 111 | * RealView PB1176 AMBA devices | ||
| 112 | */ | ||
| 113 | #define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } | ||
| 114 | #define GPIO2_DMA { 0, 0 } | ||
| 115 | #define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } | ||
| 116 | #define GPIO3_DMA { 0, 0 } | ||
| 117 | #define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } | ||
| 118 | #define AACI_DMA { 0x80, 0x81 } | ||
| 119 | #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } | ||
| 120 | #define MMCI0_DMA { 0x84, 0 } | ||
| 121 | #define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } | ||
| 122 | #define KMI0_DMA { 0, 0 } | ||
| 123 | #define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } | ||
| 124 | #define KMI1_DMA { 0, 0 } | ||
| 125 | #define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 126 | #define PB1176_SMC_DMA { 0, 0 } | ||
| 127 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 128 | #define MPMC_DMA { 0, 0 } | ||
| 129 | #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } | ||
| 130 | #define PB1176_CLCD_DMA { 0, 0 } | ||
| 131 | #define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ } | ||
| 132 | #define DMAC_DMA { 0, 0 } | ||
| 133 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | ||
| 134 | #define SCTL_DMA { 0, 0 } | ||
| 135 | #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } | ||
| 136 | #define PB1176_WATCHDOG_DMA { 0, 0 } | ||
| 137 | #define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } | ||
| 138 | #define PB1176_GPIO0_DMA { 0, 0 } | ||
| 139 | #define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } | ||
| 140 | #define GPIO1_DMA { 0, 0 } | ||
| 141 | #define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } | ||
| 142 | #define PB1176_RTC_DMA { 0, 0 } | ||
| 143 | #define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } | ||
| 144 | #define SCI_DMA { 7, 6 } | ||
| 145 | #define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } | ||
| 146 | #define PB1176_UART0_DMA { 15, 14 } | ||
| 147 | #define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } | ||
| 148 | #define PB1176_UART1_DMA { 13, 12 } | ||
| 149 | #define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } | ||
| 150 | #define PB1176_UART2_DMA { 11, 10 } | ||
| 151 | #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } | ||
| 152 | #define PB1176_UART3_DMA { 0x86, 0x87 } | ||
| 153 | #define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ } | ||
| 154 | #define PB1176_SSP_DMA { 9, 8 } | ||
| 155 | |||
| 156 | /* FPGA Primecells */ | ||
| 157 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | ||
| 158 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); | ||
| 159 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | ||
| 160 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | ||
| 161 | AMBA_DEVICE(uart3, "fpga:09", PB1176_UART3, NULL); | ||
| 162 | |||
| 163 | /* DevChip Primecells */ | ||
| 164 | AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL); | ||
| 165 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | ||
| 166 | AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL); | ||
| 167 | AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, NULL); | ||
| 168 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | ||
| 169 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | ||
| 170 | AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL); | ||
| 171 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | ||
| 172 | AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL); | ||
| 173 | AMBA_DEVICE(uart1, "dev:f2", PB1176_UART1, NULL); | ||
| 174 | AMBA_DEVICE(uart2, "dev:f3", PB1176_UART2, NULL); | ||
| 175 | AMBA_DEVICE(ssp0, "dev:f4", PB1176_SSP, NULL); | ||
| 176 | |||
| 177 | /* Primecells on the NEC ISSP chip */ | ||
| 178 | AMBA_DEVICE(clcd, "issp:20", PB1176_CLCD, &clcd_plat_data); | ||
| 179 | //AMBA_DEVICE(dmac, "issp:30", PB1176_DMAC, NULL); | ||
| 180 | |||
| 181 | static struct amba_device *amba_devs[] __initdata = { | ||
| 182 | // &dmac_device, | ||
| 183 | &uart0_device, | ||
| 184 | &uart1_device, | ||
| 185 | &uart2_device, | ||
| 186 | &uart3_device, | ||
| 187 | &smc_device, | ||
| 188 | &clcd_device, | ||
| 189 | &sctl_device, | ||
| 190 | &wdog_device, | ||
| 191 | &gpio0_device, | ||
| 192 | &gpio1_device, | ||
| 193 | &gpio2_device, | ||
| 194 | &rtc_device, | ||
| 195 | &sci0_device, | ||
| 196 | &ssp0_device, | ||
| 197 | &aaci_device, | ||
| 198 | &mmc0_device, | ||
| 199 | &kmi0_device, | ||
| 200 | &kmi1_device, | ||
| 201 | }; | ||
| 202 | |||
| 203 | /* | ||
| 204 | * RealView PB1176 platform devices | ||
| 205 | */ | ||
| 206 | static struct resource realview_pb1176_flash_resource = { | ||
| 207 | .start = REALVIEW_PB1176_FLASH_BASE, | ||
| 208 | .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, | ||
| 209 | .flags = IORESOURCE_MEM, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct resource realview_pb1176_smsc911x_resources[] = { | ||
| 213 | [0] = { | ||
| 214 | .start = REALVIEW_PB1176_ETH_BASE, | ||
| 215 | .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1, | ||
| 216 | .flags = IORESOURCE_MEM, | ||
| 217 | }, | ||
| 218 | [1] = { | ||
| 219 | .start = IRQ_PB1176_ETH, | ||
| 220 | .end = IRQ_PB1176_ETH, | ||
| 221 | .flags = IORESOURCE_IRQ, | ||
| 222 | }, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct platform_device realview_pb1176_smsc911x_device = { | ||
| 226 | .name = "smc911x", | ||
| 227 | .id = 0, | ||
| 228 | .num_resources = ARRAY_SIZE(realview_pb1176_smsc911x_resources), | ||
| 229 | .resource = realview_pb1176_smsc911x_resources, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static void __init gic_init_irq(void) | ||
| 233 | { | ||
| 234 | /* ARM1176 DevChip GIC, primary */ | ||
| 235 | gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE); | ||
| 236 | gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START); | ||
| 237 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 238 | |||
| 239 | /* board GIC, secondary */ | ||
| 240 | gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START); | ||
| 241 | gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); | ||
| 242 | gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1); | ||
| 243 | } | ||
| 244 | |||
| 245 | static void __init realview_pb1176_timer_init(void) | ||
| 246 | { | ||
| 247 | timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE); | ||
| 248 | timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20; | ||
| 249 | timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); | ||
| 250 | timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; | ||
| 251 | |||
| 252 | realview_timer_init(IRQ_DC1176_TIMER0); | ||
| 253 | } | ||
| 254 | |||
| 255 | static struct sys_timer realview_pb1176_timer = { | ||
| 256 | .init = realview_pb1176_timer_init, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static void __init realview_pb1176_init(void) | ||
| 260 | { | ||
| 261 | int i; | ||
| 262 | |||
| 263 | #ifdef CONFIG_CACHE_L2X0 | ||
| 264 | /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */ | ||
| 265 | l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); | ||
| 266 | #endif | ||
| 267 | |||
| 268 | clk_register(&realview_clcd_clk); | ||
| 269 | |||
| 270 | realview_flash_register(&realview_pb1176_flash_resource, 1); | ||
| 271 | platform_device_register(&realview_pb1176_smsc911x_device); | ||
| 272 | |||
| 273 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
| 274 | struct amba_device *d = amba_devs[i]; | ||
| 275 | amba_device_register(d, &iomem_resource); | ||
| 276 | } | ||
| 277 | |||
| 278 | #ifdef CONFIG_LEDS | ||
| 279 | leds_event = realview_leds_event; | ||
| 280 | #endif | ||
| 281 | } | ||
| 282 | |||
| 283 | MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") | ||
| 284 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
| 285 | .phys_io = REALVIEW_PB1176_UART0_BASE, | ||
| 286 | .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc, | ||
| 287 | .boot_params = 0x00000100, | ||
| 288 | .map_io = realview_pb1176_map_io, | ||
| 289 | .init_irq = gic_init_irq, | ||
| 290 | .timer = &realview_pb1176_timer, | ||
| 291 | .init_machine = realview_pb1176_init, | ||
| 292 | MACHINE_END | ||
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c new file mode 100644 index 000000000000..f7ce1c5a178a --- /dev/null +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -0,0 +1,342 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/realview_pb11mp.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/sysdev.h> | ||
| 25 | #include <linux/amba/bus.h> | ||
| 26 | |||
| 27 | #include <asm/hardware.h> | ||
| 28 | #include <asm/io.h> | ||
| 29 | #include <asm/irq.h> | ||
| 30 | #include <asm/leds.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/hardware/gic.h> | ||
| 33 | #include <asm/hardware/icst307.h> | ||
| 34 | #include <asm/hardware/cache-l2x0.h> | ||
| 35 | |||
| 36 | #include <asm/mach/arch.h> | ||
| 37 | #include <asm/mach/flash.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/mmc.h> | ||
| 40 | #include <asm/mach/time.h> | ||
| 41 | |||
| 42 | #include <asm/arch/board-pb11mp.h> | ||
| 43 | #include <asm/arch/irqs.h> | ||
| 44 | |||
| 45 | #include "core.h" | ||
| 46 | #include "clock.h" | ||
| 47 | |||
| 48 | static struct map_desc realview_pb11mp_io_desc[] __initdata = { | ||
| 49 | { | ||
| 50 | .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), | ||
| 51 | .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), | ||
| 52 | .length = SZ_4K, | ||
| 53 | .type = MT_DEVICE, | ||
| 54 | }, { | ||
| 55 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE), | ||
| 56 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE), | ||
| 57 | .length = SZ_4K, | ||
| 58 | .type = MT_DEVICE, | ||
| 59 | }, { | ||
| 60 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE), | ||
| 61 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), | ||
| 62 | .length = SZ_4K, | ||
| 63 | .type = MT_DEVICE, | ||
| 64 | }, { | ||
| 65 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), | ||
| 66 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), | ||
| 67 | .length = SZ_4K, | ||
| 68 | .type = MT_DEVICE, | ||
| 69 | }, { | ||
| 70 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE), | ||
| 71 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE), | ||
| 72 | .length = SZ_4K, | ||
| 73 | .type = MT_DEVICE, | ||
| 74 | }, { | ||
| 75 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | ||
| 76 | .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), | ||
| 77 | .length = SZ_4K, | ||
| 78 | .type = MT_DEVICE, | ||
| 79 | }, { | ||
| 80 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE), | ||
| 81 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE), | ||
| 82 | .length = SZ_4K, | ||
| 83 | .type = MT_DEVICE, | ||
| 84 | }, { | ||
| 85 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE), | ||
| 86 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE), | ||
| 87 | .length = SZ_4K, | ||
| 88 | .type = MT_DEVICE, | ||
| 89 | }, { | ||
| 90 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE), | ||
| 91 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE), | ||
| 92 | .length = SZ_8K, | ||
| 93 | .type = MT_DEVICE, | ||
| 94 | }, | ||
| 95 | #ifdef CONFIG_DEBUG_LL | ||
| 96 | { | ||
| 97 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE), | ||
| 98 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE), | ||
| 99 | .length = SZ_4K, | ||
| 100 | .type = MT_DEVICE, | ||
| 101 | }, | ||
| 102 | #endif | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init realview_pb11mp_map_io(void) | ||
| 106 | { | ||
| 107 | iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc)); | ||
| 108 | } | ||
| 109 | |||
| 110 | /* | ||
| 111 | * RealView PB11MPCore AMBA devices | ||
| 112 | */ | ||
| 113 | |||
| 114 | #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } | ||
| 115 | #define GPIO2_DMA { 0, 0 } | ||
| 116 | #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } | ||
| 117 | #define GPIO3_DMA { 0, 0 } | ||
| 118 | #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } | ||
| 119 | #define AACI_DMA { 0x80, 0x81 } | ||
| 120 | #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } | ||
| 121 | #define MMCI0_DMA { 0x84, 0 } | ||
| 122 | #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } | ||
| 123 | #define KMI0_DMA { 0, 0 } | ||
| 124 | #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } | ||
| 125 | #define KMI1_DMA { 0, 0 } | ||
| 126 | #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 127 | #define PB11MP_SMC_DMA { 0, 0 } | ||
| 128 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 129 | #define MPMC_DMA { 0, 0 } | ||
| 130 | #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } | ||
| 131 | #define PB11MP_CLCD_DMA { 0, 0 } | ||
| 132 | #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } | ||
| 133 | #define DMAC_DMA { 0, 0 } | ||
| 134 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | ||
| 135 | #define SCTL_DMA { 0, 0 } | ||
| 136 | #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } | ||
| 137 | #define PB11MP_WATCHDOG_DMA { 0, 0 } | ||
| 138 | #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } | ||
| 139 | #define PB11MP_GPIO0_DMA { 0, 0 } | ||
| 140 | #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } | ||
| 141 | #define GPIO1_DMA { 0, 0 } | ||
| 142 | #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } | ||
| 143 | #define PB11MP_RTC_DMA { 0, 0 } | ||
| 144 | #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } | ||
| 145 | #define SCI_DMA { 7, 6 } | ||
| 146 | #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } | ||
| 147 | #define PB11MP_UART0_DMA { 15, 14 } | ||
| 148 | #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } | ||
| 149 | #define PB11MP_UART1_DMA { 13, 12 } | ||
| 150 | #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } | ||
| 151 | #define PB11MP_UART2_DMA { 11, 10 } | ||
| 152 | #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } | ||
| 153 | #define PB11MP_UART3_DMA { 0x86, 0x87 } | ||
| 154 | #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } | ||
| 155 | #define PB11MP_SSP_DMA { 9, 8 } | ||
| 156 | |||
| 157 | /* FPGA Primecells */ | ||
| 158 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | ||
| 159 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); | ||
| 160 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | ||
| 161 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | ||
| 162 | AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL); | ||
| 163 | |||
| 164 | /* DevChip Primecells */ | ||
| 165 | AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL); | ||
| 166 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | ||
| 167 | AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL); | ||
| 168 | AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL); | ||
| 169 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | ||
| 170 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | ||
| 171 | AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL); | ||
| 172 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | ||
| 173 | AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL); | ||
| 174 | AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL); | ||
| 175 | AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL); | ||
| 176 | AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL); | ||
| 177 | |||
| 178 | /* Primecells on the NEC ISSP chip */ | ||
| 179 | AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data); | ||
| 180 | AMBA_DEVICE(dmac, "issp:30", DMAC, NULL); | ||
| 181 | |||
| 182 | static struct amba_device *amba_devs[] __initdata = { | ||
| 183 | &dmac_device, | ||
| 184 | &uart0_device, | ||
| 185 | &uart1_device, | ||
| 186 | &uart2_device, | ||
| 187 | &uart3_device, | ||
| 188 | &smc_device, | ||
| 189 | &clcd_device, | ||
| 190 | &sctl_device, | ||
| 191 | &wdog_device, | ||
| 192 | &gpio0_device, | ||
| 193 | &gpio1_device, | ||
| 194 | &gpio2_device, | ||
| 195 | &rtc_device, | ||
| 196 | &sci0_device, | ||
| 197 | &ssp0_device, | ||
| 198 | &aaci_device, | ||
| 199 | &mmc0_device, | ||
| 200 | &kmi0_device, | ||
| 201 | &kmi1_device, | ||
| 202 | }; | ||
| 203 | |||
| 204 | /* | ||
| 205 | * RealView PB11MPCore platform devices | ||
| 206 | */ | ||
| 207 | static struct resource realview_pb11mp_flash_resource[] = { | ||
| 208 | [0] = { | ||
| 209 | .start = REALVIEW_PB11MP_FLASH0_BASE, | ||
| 210 | .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1, | ||
| 211 | .flags = IORESOURCE_MEM, | ||
| 212 | }, | ||
| 213 | [1] = { | ||
| 214 | .start = REALVIEW_PB11MP_FLASH1_BASE, | ||
| 215 | .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1, | ||
| 216 | .flags = IORESOURCE_MEM, | ||
| 217 | }, | ||
| 218 | }; | ||
| 219 | |||
| 220 | static struct resource realview_pb11mp_smsc911x_resources[] = { | ||
| 221 | [0] = { | ||
| 222 | .start = REALVIEW_PB11MP_ETH_BASE, | ||
| 223 | .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1, | ||
| 224 | .flags = IORESOURCE_MEM, | ||
| 225 | }, | ||
| 226 | [1] = { | ||
| 227 | .start = IRQ_TC11MP_ETH, | ||
| 228 | .end = IRQ_TC11MP_ETH, | ||
| 229 | .flags = IORESOURCE_IRQ, | ||
| 230 | }, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct platform_device realview_pb11mp_smsc911x_device = { | ||
| 234 | .name = "smc911x", | ||
| 235 | .id = 0, | ||
| 236 | .num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources), | ||
| 237 | .resource = realview_pb11mp_smsc911x_resources, | ||
| 238 | }; | ||
| 239 | |||
| 240 | struct resource realview_pb11mp_cf_resources[] = { | ||
| 241 | [0] = { | ||
| 242 | .start = REALVIEW_PB11MP_CF_BASE, | ||
| 243 | .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1, | ||
| 244 | .flags = IORESOURCE_MEM, | ||
| 245 | }, | ||
| 246 | [1] = { | ||
| 247 | .start = REALVIEW_PB11MP_CF_MEM_BASE, | ||
| 248 | .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1, | ||
| 249 | .flags = IORESOURCE_MEM, | ||
| 250 | }, | ||
| 251 | [2] = { | ||
| 252 | .start = -1, /* FIXME: Find correct irq */ | ||
| 253 | .end = -1, | ||
| 254 | .flags = IORESOURCE_IRQ, | ||
| 255 | }, | ||
| 256 | }; | ||
| 257 | |||
| 258 | struct platform_device realview_pb11mp_cf_device = { | ||
| 259 | .name = "compactflash", | ||
| 260 | .id = 0, | ||
| 261 | .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources), | ||
| 262 | .resource = realview_pb11mp_cf_resources, | ||
| 263 | }; | ||
| 264 | |||
| 265 | static void __init gic_init_irq(void) | ||
| 266 | { | ||
| 267 | unsigned int pldctrl; | ||
| 268 | |||
| 269 | /* new irq mode with no DCC */ | ||
| 270 | writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); | ||
| 271 | pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); | ||
| 272 | pldctrl |= 2 << 22; | ||
| 273 | writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); | ||
| 274 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); | ||
| 275 | |||
| 276 | /* ARM11MPCore test chip GIC, primary */ | ||
| 277 | gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); | ||
| 278 | gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29); | ||
| 279 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 280 | |||
| 281 | /* board GIC, secondary */ | ||
| 282 | gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START); | ||
| 283 | gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); | ||
| 284 | gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); | ||
| 285 | } | ||
| 286 | |||
| 287 | static void __init realview_pb11mp_timer_init(void) | ||
| 288 | { | ||
| 289 | timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE); | ||
| 290 | timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20; | ||
| 291 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); | ||
| 292 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; | ||
| 293 | |||
| 294 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 295 | twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE); | ||
| 296 | twd_size = REALVIEW_TC11MP_TWD_SIZE; | ||
| 297 | #endif | ||
| 298 | realview_timer_init(IRQ_TC11MP_TIMER0_1); | ||
| 299 | } | ||
| 300 | |||
| 301 | static struct sys_timer realview_pb11mp_timer = { | ||
| 302 | .init = realview_pb11mp_timer_init, | ||
| 303 | }; | ||
| 304 | |||
| 305 | static void __init realview_pb11mp_init(void) | ||
| 306 | { | ||
| 307 | int i; | ||
| 308 | |||
| 309 | #ifdef CONFIG_CACHE_L2X0 | ||
| 310 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled | ||
| 311 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ | ||
| 312 | l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff); | ||
| 313 | #endif | ||
| 314 | |||
| 315 | clk_register(&realview_clcd_clk); | ||
| 316 | |||
| 317 | realview_flash_register(realview_pb11mp_flash_resource, | ||
| 318 | ARRAY_SIZE(realview_pb11mp_flash_resource)); | ||
| 319 | platform_device_register(&realview_pb11mp_smsc911x_device); | ||
| 320 | platform_device_register(&realview_i2c_device); | ||
| 321 | platform_device_register(&realview_pb11mp_cf_device); | ||
| 322 | |||
| 323 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
| 324 | struct amba_device *d = amba_devs[i]; | ||
| 325 | amba_device_register(d, &iomem_resource); | ||
| 326 | } | ||
| 327 | |||
| 328 | #ifdef CONFIG_LEDS | ||
| 329 | leds_event = realview_leds_event; | ||
| 330 | #endif | ||
| 331 | } | ||
| 332 | |||
| 333 | MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") | ||
| 334 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
| 335 | .phys_io = REALVIEW_PB11MP_UART0_BASE, | ||
| 336 | .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc, | ||
| 337 | .boot_params = 0x00000100, | ||
| 338 | .map_io = realview_pb11mp_map_io, | ||
| 339 | .init_irq = gic_init_irq, | ||
| 340 | .timer = &realview_pb11mp_timer, | ||
| 341 | .init_machine = realview_pb11mp_init, | ||
| 342 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index e2079cf9266f..cd3dc0834b3b 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
| @@ -97,6 +97,13 @@ config BAST_PC104_IRQ | |||
| 97 | Say Y here to enable the PC104 IRQ routing on the | 97 | Say Y here to enable the PC104 IRQ routing on the |
| 98 | Simtec BAST (EB2410ITX) | 98 | Simtec BAST (EB2410ITX) |
| 99 | 99 | ||
| 100 | config MACH_TCT_HAMMER | ||
| 101 | bool "TCT Hammer Board" | ||
| 102 | select CPU_S3C2410 | ||
| 103 | help | ||
| 104 | Say Y here if you are using the TinCanTools Hammer Board | ||
| 105 | <http://www.tincantools.com> | ||
| 106 | |||
| 100 | config MACH_VR1000 | 107 | config MACH_VR1000 |
| 101 | bool "Thorcom VR1000" | 108 | bool "Thorcom VR1000" |
| 102 | select PM_SIMTEC if PM | 109 | select PM_SIMTEC if PM |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 3e7a85594d9c..cabc13ce09e4 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
| @@ -27,5 +27,6 @@ obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o | |||
| 27 | obj-$(CONFIG_MACH_OTOM) += mach-otom.o | 27 | obj-$(CONFIG_MACH_OTOM) += mach-otom.o |
| 28 | obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o | 28 | obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o |
| 29 | obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o | 29 | obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o |
| 30 | obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o | ||
| 30 | obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o | 31 | obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o |
| 31 | obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o | 32 | obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o |
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 66175471fff3..661a2358ac22 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/list.h> | 16 | #include <linux/list.h> |
| 17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/sysdev.h> | ||
| 19 | #include <linux/serial_core.h> | 20 | #include <linux/serial_core.h> |
| 20 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 21 | #include <linux/dm9000.h> | 22 | #include <linux/dm9000.h> |
| @@ -236,6 +237,36 @@ static struct platform_device bast_device_nor = { | |||
| 236 | 237 | ||
| 237 | /* NAND Flash on BAST board */ | 238 | /* NAND Flash on BAST board */ |
| 238 | 239 | ||
| 240 | #ifdef CONFIG_PM | ||
| 241 | static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) | ||
| 242 | { | ||
| 243 | /* ensure that an nRESET is not generated on resume. */ | ||
| 244 | s3c2410_gpio_setpin(S3C2410_GPA21, 1); | ||
| 245 | s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); | ||
| 246 | |||
| 247 | return 0; | ||
| 248 | } | ||
| 249 | |||
| 250 | static int bast_pm_resume(struct sys_device *sd) | ||
| 251 | { | ||
| 252 | s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); | ||
| 253 | return 0; | ||
| 254 | } | ||
| 255 | |||
| 256 | #else | ||
| 257 | #define bast_pm_suspend NULL | ||
| 258 | #define bast_pm_resume NULL | ||
| 259 | #endif | ||
| 260 | |||
| 261 | static struct sysdev_class bast_pm_sysclass = { | ||
| 262 | .name = "mach-bast", | ||
| 263 | .suspend = bast_pm_suspend, | ||
| 264 | .resume = bast_pm_resume, | ||
| 265 | }; | ||
| 266 | |||
| 267 | static struct sys_device bast_pm_sysdev = { | ||
| 268 | .cls = &bast_pm_sysclass, | ||
| 269 | }; | ||
| 239 | 270 | ||
| 240 | static int smartmedia_map[] = { 0 }; | 271 | static int smartmedia_map[] = { 0 }; |
| 241 | static int chip0_map[] = { 1 }; | 272 | static int chip0_map[] = { 1 }; |
| @@ -561,10 +592,10 @@ static void __init bast_map_io(void) | |||
| 561 | { | 592 | { |
| 562 | /* initialise the clocks */ | 593 | /* initialise the clocks */ |
| 563 | 594 | ||
| 564 | s3c24xx_dclk0.parent = NULL; | 595 | s3c24xx_dclk0.parent = &clk_upll; |
| 565 | s3c24xx_dclk0.rate = 12*1000*1000; | 596 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 566 | 597 | ||
| 567 | s3c24xx_dclk1.parent = NULL; | 598 | s3c24xx_dclk1.parent = &clk_upll; |
| 568 | s3c24xx_dclk1.rate = 24*1000*1000; | 599 | s3c24xx_dclk1.rate = 24*1000*1000; |
| 569 | 600 | ||
| 570 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | 601 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; |
| @@ -586,6 +617,9 @@ static void __init bast_map_io(void) | |||
| 586 | 617 | ||
| 587 | static void __init bast_init(void) | 618 | static void __init bast_init(void) |
| 588 | { | 619 | { |
| 620 | sysdev_class_register(&bast_pm_sysclass); | ||
| 621 | sysdev_register(&bast_pm_sysdev); | ||
| 622 | |||
| 589 | s3c24xx_fb_set_platdata(&bast_fb_info); | 623 | s3c24xx_fb_set_platdata(&bast_fb_info); |
| 590 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); | 624 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); |
| 591 | } | 625 | } |
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c new file mode 100644 index 000000000000..d90d445ccfb4 --- /dev/null +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/mach-tct_hammer.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2007 TinCanTools | ||
| 4 | * David Anders <danders@amltd.com> | ||
| 5 | |||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation; either version 2 of | ||
| 9 | * the License, or (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 19 | * MA 02111-1307 USA | ||
| 20 | * | ||
| 21 | * @History: | ||
| 22 | * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by | ||
| 23 | * Ben Dooks <ben@simtec.co.uk> | ||
| 24 | * | ||
| 25 | ***********************************************************************/ | ||
| 26 | |||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/types.h> | ||
| 29 | #include <linux/interrupt.h> | ||
| 30 | #include <linux/list.h> | ||
| 31 | #include <linux/timer.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/device.h> | ||
| 34 | #include <linux/platform_device.h> | ||
| 35 | #include <linux/serial_core.h> | ||
| 36 | |||
| 37 | #include <asm/mach/arch.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/irq.h> | ||
| 40 | #include <asm/mach/flash.h> | ||
| 41 | |||
| 42 | #include <asm/hardware.h> | ||
| 43 | #include <asm/io.h> | ||
| 44 | #include <asm/irq.h> | ||
| 45 | #include <asm/mach-types.h> | ||
| 46 | |||
| 47 | #include <asm/plat-s3c/regs-serial.h> | ||
| 48 | #include <asm/plat-s3c24xx/devs.h> | ||
| 49 | #include <asm/plat-s3c24xx/cpu.h> | ||
| 50 | |||
| 51 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 52 | |||
| 53 | #include <linux/mtd/mtd.h> | ||
| 54 | #include <linux/mtd/partitions.h> | ||
| 55 | #include <linux/mtd/map.h> | ||
| 56 | #include <linux/mtd/physmap.h> | ||
| 57 | |||
| 58 | static struct resource tct_hammer_nor_resource = { | ||
| 59 | .start = 0x00000000, | ||
| 60 | .end = 0x01000000 - 1, | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }; | ||
| 63 | |||
| 64 | static struct mtd_partition tct_hammer_mtd_partitions[] = { | ||
| 65 | { | ||
| 66 | .name = "System", | ||
| 67 | .size = 0x240000, | ||
| 68 | .offset = 0, | ||
| 69 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 70 | }, { | ||
| 71 | .name = "JFFS2", | ||
| 72 | .size = MTDPART_SIZ_FULL, | ||
| 73 | .offset = MTDPART_OFS_APPEND, | ||
| 74 | } | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct physmap_flash_data tct_hammer_flash_data = { | ||
| 78 | .width = 2, | ||
| 79 | .parts = tct_hammer_mtd_partitions, | ||
| 80 | .nr_parts = ARRAY_SIZE(tct_hammer_mtd_partitions), | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct platform_device tct_hammer_device_nor = { | ||
| 84 | .name = "physmap-flash", | ||
| 85 | .id = 0, | ||
| 86 | .dev = { | ||
| 87 | .platform_data = &tct_hammer_flash_data, | ||
| 88 | }, | ||
| 89 | .num_resources = 1, | ||
| 90 | .resource = &tct_hammer_nor_resource, | ||
| 91 | }; | ||
| 92 | |||
| 93 | #endif | ||
| 94 | |||
| 95 | static struct map_desc tct_hammer_iodesc[] __initdata = { | ||
| 96 | }; | ||
| 97 | |||
| 98 | #define UCON S3C2410_UCON_DEFAULT | ||
| 99 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | ||
| 100 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | ||
| 101 | |||
| 102 | static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = { | ||
| 103 | [0] = { | ||
| 104 | .hwport = 0, | ||
| 105 | .flags = 0, | ||
| 106 | .ucon = UCON, | ||
| 107 | .ulcon = ULCON, | ||
| 108 | .ufcon = UFCON, | ||
| 109 | }, | ||
| 110 | [1] = { | ||
| 111 | .hwport = 1, | ||
| 112 | .flags = 0, | ||
| 113 | .ucon = UCON, | ||
| 114 | .ulcon = ULCON, | ||
| 115 | .ufcon = UFCON, | ||
| 116 | }, | ||
| 117 | [2] = { | ||
| 118 | .hwport = 2, | ||
| 119 | .flags = 0, | ||
| 120 | .ucon = UCON, | ||
| 121 | .ulcon = ULCON, | ||
| 122 | .ufcon = UFCON, | ||
| 123 | } | ||
| 124 | }; | ||
| 125 | |||
| 126 | |||
| 127 | static struct platform_device *tct_hammer_devices[] __initdata = { | ||
| 128 | &s3c_device_adc, | ||
| 129 | &s3c_device_wdt, | ||
| 130 | &s3c_device_i2c, | ||
| 131 | &s3c_device_usb, | ||
| 132 | &s3c_device_rtc, | ||
| 133 | &s3c_device_usbgadget, | ||
| 134 | &s3c_device_sdi, | ||
| 135 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 136 | &tct_hammer_device_nor, | ||
| 137 | #endif | ||
| 138 | }; | ||
| 139 | |||
| 140 | static void __init tct_hammer_map_io(void) | ||
| 141 | { | ||
| 142 | s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); | ||
| 143 | s3c24xx_init_clocks(0); | ||
| 144 | s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); | ||
| 145 | } | ||
| 146 | |||
| 147 | static void __init tct_hammer_init(void) | ||
| 148 | { | ||
| 149 | platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); | ||
| 150 | } | ||
| 151 | |||
| 152 | MACHINE_START(TCT_HAMMER, "TCT_HAMMER") | ||
| 153 | .phys_io = S3C2410_PA_UART, | ||
| 154 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | ||
| 155 | .boot_params = S3C2410_SDRAM_PA + 0x100, | ||
| 156 | .map_io = tct_hammer_map_io, | ||
| 157 | .init_irq = s3c24xx_init_irq, | ||
| 158 | .init_machine = tct_hammer_init, | ||
| 159 | .timer = &s3c24xx_timer, | ||
| 160 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 3aade7b78fe5..c56423373ff3 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c | |||
| @@ -393,7 +393,7 @@ static void __init vr1000_map_io(void) | |||
| 393 | { | 393 | { |
| 394 | /* initialise clock sources */ | 394 | /* initialise clock sources */ |
| 395 | 395 | ||
| 396 | s3c24xx_dclk0.parent = NULL; | 396 | s3c24xx_dclk0.parent = &clk_upll; |
| 397 | s3c24xx_dclk0.rate = 12*1000*1000; | 397 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 398 | 398 | ||
| 399 | s3c24xx_dclk1.parent = NULL; | 399 | s3c24xx_dclk1.parent = NULL; |
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index abf1599c9f97..98a0de924c22 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c | |||
| @@ -175,7 +175,7 @@ void __init s3c2412_init_clocks(int xtal) | |||
| 175 | /* work out clock scalings */ | 175 | /* work out clock scalings */ |
| 176 | 176 | ||
| 177 | hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); | 177 | hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); |
| 178 | hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1); | 178 | hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); |
| 179 | pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); | 179 | pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); |
| 180 | 180 | ||
| 181 | /* print brieft summary of clocks, etc */ | 181 | /* print brieft summary of clocks, etc */ |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 3d3dfa95db8e..47258915a2f9 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c | |||
| @@ -413,10 +413,10 @@ static void __init anubis_map_io(void) | |||
| 413 | { | 413 | { |
| 414 | /* initialise the clocks */ | 414 | /* initialise the clocks */ |
| 415 | 415 | ||
| 416 | s3c24xx_dclk0.parent = NULL; | 416 | s3c24xx_dclk0.parent = &clk_upll; |
| 417 | s3c24xx_dclk0.rate = 12*1000*1000; | 417 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 418 | 418 | ||
| 419 | s3c24xx_dclk1.parent = NULL; | 419 | s3c24xx_dclk1.parent = &clk_upll; |
| 420 | s3c24xx_dclk1.rate = 24*1000*1000; | 420 | s3c24xx_dclk1.rate = 24*1000*1000; |
| 421 | 421 | ||
| 422 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | 422 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; |
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 78af7664988b..8a8acdbd072d 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <linux/device.h> | 18 | #include <linux/device.h> |
| 19 | #include <linux/sysdev.h> | 19 | #include <linux/sysdev.h> |
| 20 | #include <linux/serial_core.h> | 20 | #include <linux/serial_core.h> |
| 21 | #include <linux/clk.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
| @@ -344,10 +345,10 @@ static void __init osiris_map_io(void) | |||
| 344 | 345 | ||
| 345 | /* initialise the clocks */ | 346 | /* initialise the clocks */ |
| 346 | 347 | ||
| 347 | s3c24xx_dclk0.parent = NULL; | 348 | s3c24xx_dclk0.parent = &clk_upll; |
| 348 | s3c24xx_dclk0.rate = 12*1000*1000; | 349 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 349 | 350 | ||
| 350 | s3c24xx_dclk1.parent = NULL; | 351 | s3c24xx_dclk1.parent = &clk_upll; |
| 351 | s3c24xx_dclk1.rate = 24*1000*1000; | 352 | s3c24xx_dclk1.rate = 24*1000*1000; |
| 352 | 353 | ||
| 353 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | 354 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; |
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 7a61e8d33ab7..8e0244631d65 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o | 6 | obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o |
| 7 | obj-m := | 7 | obj-m := |
| 8 | obj-n := | 8 | obj-n := |
| 9 | obj- := | 9 | obj- := |
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 5c84c604ed86..0c2fa1c4fb4c 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
| @@ -139,37 +139,6 @@ unsigned long long sched_clock(void) | |||
| 139 | return v; | 139 | return v; |
| 140 | } | 140 | } |
| 141 | 141 | ||
| 142 | int gpio_direction_input(unsigned gpio) | ||
| 143 | { | ||
| 144 | unsigned long flags; | ||
| 145 | |||
| 146 | if (gpio > GPIO_MAX) | ||
| 147 | return -EINVAL; | ||
| 148 | |||
| 149 | local_irq_save(flags); | ||
| 150 | GPDR &= ~GPIO_GPIO(gpio); | ||
| 151 | local_irq_restore(flags); | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | EXPORT_SYMBOL(gpio_direction_input); | ||
| 156 | |||
| 157 | int gpio_direction_output(unsigned gpio, int value) | ||
| 158 | { | ||
| 159 | unsigned long flags; | ||
| 160 | |||
| 161 | if (gpio > GPIO_MAX) | ||
| 162 | return -EINVAL; | ||
| 163 | |||
| 164 | local_irq_save(flags); | ||
| 165 | gpio_set_value(gpio, value); | ||
| 166 | GPDR |= GPIO_GPIO(gpio); | ||
| 167 | local_irq_restore(flags); | ||
| 168 | return 0; | ||
| 169 | } | ||
| 170 | |||
| 171 | EXPORT_SYMBOL(gpio_direction_output); | ||
| 172 | |||
| 173 | /* | 142 | /* |
| 174 | * Default power-off for SA1100 | 143 | * Default power-off for SA1100 |
| 175 | */ | 144 | */ |
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index f085d68e568e..793c2e6c991f 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h | |||
| @@ -9,6 +9,7 @@ struct sys_timer; | |||
| 9 | extern struct sys_timer sa1100_timer; | 9 | extern struct sys_timer sa1100_timer; |
| 10 | extern void __init sa1100_map_io(void); | 10 | extern void __init sa1100_map_io(void); |
| 11 | extern void __init sa1100_init_irq(void); | 11 | extern void __init sa1100_init_irq(void); |
| 12 | extern void __init sa1100_init_gpio(void); | ||
| 12 | 13 | ||
| 13 | #define SET_BANK(__nr,__start,__size) \ | 14 | #define SET_BANK(__nr,__start,__size) \ |
| 14 | mi->bank[__nr].start = (__start), \ | 15 | mi->bank[__nr].start = (__start), \ |
diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c new file mode 100644 index 000000000000..372f1f4f54a1 --- /dev/null +++ b/arch/arm/mach-sa1100/gpio.c | |||
| @@ -0,0 +1,65 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-sa1100/gpio.c | ||
| 3 | * | ||
| 4 | * Generic SA-1100 GPIO handling | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | |||
| 14 | #include <asm/gpio.h> | ||
| 15 | #include <asm/hardware.h> | ||
| 16 | #include "generic.h" | ||
| 17 | |||
| 18 | static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 19 | { | ||
| 20 | return GPLR & GPIO_GPIO(offset); | ||
| 21 | } | ||
| 22 | |||
| 23 | static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 24 | { | ||
| 25 | if (value) | ||
| 26 | GPSR = GPIO_GPIO(offset); | ||
| 27 | else | ||
| 28 | GPCR = GPIO_GPIO(offset); | ||
| 29 | } | ||
| 30 | |||
| 31 | static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 32 | { | ||
| 33 | unsigned long flags; | ||
| 34 | |||
| 35 | local_irq_save(flags); | ||
| 36 | GPDR &= ~GPIO_GPIO(offset); | ||
| 37 | local_irq_restore(flags); | ||
| 38 | return 0; | ||
| 39 | } | ||
| 40 | |||
| 41 | static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) | ||
| 42 | { | ||
| 43 | unsigned long flags; | ||
| 44 | |||
| 45 | local_irq_save(flags); | ||
| 46 | sa1100_gpio_set(chip, offset, value); | ||
| 47 | GPDR |= GPIO_GPIO(offset); | ||
| 48 | local_irq_restore(flags); | ||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static struct gpio_chip sa1100_gpio_chip = { | ||
| 53 | .label = "gpio", | ||
| 54 | .direction_input = sa1100_direction_input, | ||
| 55 | .direction_output = sa1100_direction_output, | ||
| 56 | .set = sa1100_gpio_set, | ||
| 57 | .get = sa1100_gpio_get, | ||
| 58 | .base = 0, | ||
| 59 | .ngpio = GPIO_MAX + 1, | ||
| 60 | }; | ||
| 61 | |||
| 62 | void __init sa1100_init_gpio(void) | ||
| 63 | { | ||
| 64 | gpiochip_add(&sa1100_gpio_chip); | ||
| 65 | } | ||
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3dc17d7bf38e..fa0403af7eec 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c | |||
| @@ -347,4 +347,6 @@ void __init sa1100_init_irq(void) | |||
| 347 | */ | 347 | */ |
| 348 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); | 348 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); |
| 349 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | 349 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); |
| 350 | |||
| 351 | sa1100_init_gpio(); | ||
| 350 | } | 352 | } |
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index c2677368d6af..a9799cb35b74 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c | |||
| @@ -13,67 +13,69 @@ | |||
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 15 | #include <linux/timex.h> | 15 | #include <linux/timex.h> |
| 16 | #include <linux/signal.h> | 16 | #include <linux/clockchips.h> |
| 17 | #include <linux/clocksource.h> | ||
| 18 | 17 | ||
| 19 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
| 20 | #include <asm/hardware.h> | 19 | #include <asm/hardware.h> |
| 21 | 20 | ||
| 22 | #define RTC_DEF_DIVIDER (32768 - 1) | 21 | #define MIN_OSCR_DELTA 2 |
| 23 | #define RTC_DEF_TRIM 0 | ||
| 24 | 22 | ||
| 25 | static int sa1100_set_rtc(void) | 23 | static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) |
| 26 | { | 24 | { |
| 27 | unsigned long current_time = xtime.tv_sec; | 25 | struct clock_event_device *c = dev_id; |
| 28 | 26 | ||
| 29 | if (RTSR & RTSR_ALE) { | 27 | /* Disarm the compare/match, signal the event. */ |
| 30 | /* make sure not to forward the clock over an alarm */ | 28 | OIER &= ~OIER_E0; |
| 31 | unsigned long alarm = RTAR; | 29 | OSSR = OSSR_M0; |
| 32 | if (current_time >= alarm && alarm >= RCNR) | 30 | c->event_handler(c); |
| 33 | return -ERESTARTSYS; | ||
| 34 | } | ||
| 35 | RCNR = current_time; | ||
| 36 | return 0; | ||
| 37 | } | ||
| 38 | 31 | ||
| 39 | #ifdef CONFIG_NO_IDLE_HZ | 32 | return IRQ_HANDLED; |
| 40 | static unsigned long initial_match; | 33 | } |
| 41 | static int match_posponed; | ||
| 42 | #endif | ||
| 43 | 34 | ||
| 44 | static irqreturn_t | 35 | static int |
| 45 | sa1100_timer_interrupt(int irq, void *dev_id) | 36 | sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) |
| 46 | { | 37 | { |
| 47 | unsigned int next_match; | 38 | unsigned long flags, next, oscr; |
| 48 | 39 | ||
| 49 | #ifdef CONFIG_NO_IDLE_HZ | 40 | raw_local_irq_save(flags); |
| 50 | if (match_posponed) { | 41 | OIER |= OIER_E0; |
| 51 | match_posponed = 0; | 42 | next = OSCR + delta; |
| 52 | OSMR0 = initial_match; | 43 | OSMR0 = next; |
| 53 | } | 44 | oscr = OSCR; |
| 54 | #endif | 45 | raw_local_irq_restore(flags); |
| 55 | 46 | ||
| 56 | /* | 47 | return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; |
| 57 | * Loop until we get ahead of the free running timer. | 48 | } |
| 58 | * This ensures an exact clock tick count and time accuracy. | ||
| 59 | * Since IRQs are disabled at this point, coherence between | ||
| 60 | * lost_ticks(updated in do_timer()) and the match reg value is | ||
| 61 | * ensured, hence we can use do_gettimeofday() from interrupt | ||
| 62 | * handlers. | ||
| 63 | */ | ||
| 64 | do { | ||
| 65 | timer_tick(); | ||
| 66 | OSSR = OSSR_M0; /* Clear match on timer 0 */ | ||
| 67 | next_match = (OSMR0 += LATCH); | ||
| 68 | } while ((signed long)(next_match - OSCR) <= 0); | ||
| 69 | 49 | ||
| 70 | return IRQ_HANDLED; | 50 | static void |
| 51 | sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) | ||
| 52 | { | ||
| 53 | unsigned long flags; | ||
| 54 | |||
| 55 | switch (mode) { | ||
| 56 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 57 | case CLOCK_EVT_MODE_UNUSED: | ||
| 58 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 59 | raw_local_irq_save(flags); | ||
| 60 | OIER &= ~OIER_E0; | ||
| 61 | OSSR = OSSR_M0; | ||
| 62 | raw_local_irq_restore(flags); | ||
| 63 | break; | ||
| 64 | |||
| 65 | case CLOCK_EVT_MODE_RESUME: | ||
| 66 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 67 | break; | ||
| 68 | } | ||
| 71 | } | 69 | } |
| 72 | 70 | ||
| 73 | static struct irqaction sa1100_timer_irq = { | 71 | static struct clock_event_device ckevt_sa1100_osmr0 = { |
| 74 | .name = "SA11xx Timer Tick", | 72 | .name = "osmr0", |
| 75 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 73 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| 76 | .handler = sa1100_timer_interrupt, | 74 | .shift = 32, |
| 75 | .rating = 200, | ||
| 76 | .cpumask = CPU_MASK_CPU0, | ||
| 77 | .set_next_event = sa1100_osmr0_set_next_event, | ||
| 78 | .set_mode = sa1100_osmr0_set_mode, | ||
| 77 | }; | 79 | }; |
| 78 | 80 | ||
| 79 | static cycle_t sa1100_read_oscr(void) | 81 | static cycle_t sa1100_read_oscr(void) |
| @@ -90,62 +92,34 @@ static struct clocksource cksrc_sa1100_oscr = { | |||
| 90 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 92 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 91 | }; | 93 | }; |
| 92 | 94 | ||
| 95 | static struct irqaction sa1100_timer_irq = { | ||
| 96 | .name = "ost0", | ||
| 97 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 98 | .handler = sa1100_ost0_interrupt, | ||
| 99 | .dev_id = &ckevt_sa1100_osmr0, | ||
| 100 | }; | ||
| 101 | |||
| 93 | static void __init sa1100_timer_init(void) | 102 | static void __init sa1100_timer_init(void) |
| 94 | { | 103 | { |
| 95 | unsigned long flags; | ||
| 96 | |||
| 97 | set_rtc = sa1100_set_rtc; | ||
| 98 | |||
| 99 | OIER = 0; /* disable any timer interrupts */ | 104 | OIER = 0; /* disable any timer interrupts */ |
| 100 | OSSR = 0xf; /* clear status on all timers */ | 105 | OSSR = 0xf; /* clear status on all timers */ |
| 101 | setup_irq(IRQ_OST0, &sa1100_timer_irq); | 106 | |
| 102 | local_irq_save(flags); | 107 | ckevt_sa1100_osmr0.mult = |
| 103 | OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ | 108 | div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); |
| 104 | OSMR0 = OSCR + LATCH; /* set initial match */ | 109 | ckevt_sa1100_osmr0.max_delta_ns = |
| 105 | local_irq_restore(flags); | 110 | clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); |
| 111 | ckevt_sa1100_osmr0.min_delta_ns = | ||
| 112 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; | ||
| 106 | 113 | ||
| 107 | cksrc_sa1100_oscr.mult = | 114 | cksrc_sa1100_oscr.mult = |
| 108 | clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); | 115 | clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); |
| 109 | 116 | ||
| 110 | clocksource_register(&cksrc_sa1100_oscr); | 117 | setup_irq(IRQ_OST0, &sa1100_timer_irq); |
| 111 | } | ||
| 112 | |||
| 113 | #ifdef CONFIG_NO_IDLE_HZ | ||
| 114 | static int sa1100_dyn_tick_enable_disable(void) | ||
| 115 | { | ||
| 116 | /* nothing to do */ | ||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | static void sa1100_dyn_tick_reprogram(unsigned long ticks) | ||
| 121 | { | ||
| 122 | if (ticks > 1) { | ||
| 123 | initial_match = OSMR0; | ||
| 124 | OSMR0 = initial_match + ticks * LATCH; | ||
| 125 | match_posponed = 1; | ||
| 126 | } | ||
| 127 | } | ||
| 128 | 118 | ||
| 129 | static irqreturn_t | 119 | clocksource_register(&cksrc_sa1100_oscr); |
| 130 | sa1100_dyn_tick_handler(int irq, void *dev_id) | 120 | clockevents_register_device(&ckevt_sa1100_osmr0); |
| 131 | { | ||
| 132 | if (match_posponed) { | ||
| 133 | match_posponed = 0; | ||
| 134 | OSMR0 = initial_match; | ||
| 135 | if ((signed long)(initial_match - OSCR) <= 0) | ||
| 136 | return sa1100_timer_interrupt(irq, dev_id); | ||
| 137 | } | ||
| 138 | return IRQ_NONE; | ||
| 139 | } | 121 | } |
| 140 | 122 | ||
| 141 | static struct dyn_tick_timer sa1100_dyn_tick = { | ||
| 142 | .enable = sa1100_dyn_tick_enable_disable, | ||
| 143 | .disable = sa1100_dyn_tick_enable_disable, | ||
| 144 | .reprogram = sa1100_dyn_tick_reprogram, | ||
| 145 | .handler = sa1100_dyn_tick_handler, | ||
| 146 | }; | ||
| 147 | #endif | ||
| 148 | |||
| 149 | #ifdef CONFIG_PM | 123 | #ifdef CONFIG_PM |
| 150 | unsigned long osmr[4], oier; | 124 | unsigned long osmr[4], oier; |
| 151 | 125 | ||
| @@ -181,7 +155,4 @@ struct sys_timer sa1100_timer = { | |||
| 181 | .init = sa1100_timer_init, | 155 | .init = sa1100_timer_init, |
| 182 | .suspend = sa1100_timer_suspend, | 156 | .suspend = sa1100_timer_suspend, |
| 183 | .resume = sa1100_timer_resume, | 157 | .resume = sa1100_timer_resume, |
| 184 | #ifdef CONFIG_NO_IDLE_HZ | ||
| 185 | .dyn_tick = &sa1100_dyn_tick, | ||
| 186 | #endif | ||
| 187 | }; | 158 | }; |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76348f060f27..746cbb7c8e95 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -18,6 +18,7 @@ config CPU_ARM610 | |||
| 18 | select CPU_CP15_MMU | 18 | select CPU_CP15_MMU |
| 19 | select CPU_COPY_V3 if MMU | 19 | select CPU_COPY_V3 if MMU |
| 20 | select CPU_TLB_V3 if MMU | 20 | select CPU_TLB_V3 if MMU |
| 21 | select CPU_PABRT_NOIFAR | ||
| 21 | help | 22 | help |
| 22 | The ARM610 is the successor to the ARM3 processor | 23 | The ARM610 is the successor to the ARM3 processor |
| 23 | and was produced by VLSI Technology Inc. | 24 | and was produced by VLSI Technology Inc. |
| @@ -49,6 +50,7 @@ config CPU_ARM710 | |||
| 49 | select CPU_CP15_MMU | 50 | select CPU_CP15_MMU |
| 50 | select CPU_COPY_V3 if MMU | 51 | select CPU_COPY_V3 if MMU |
| 51 | select CPU_TLB_V3 if MMU | 52 | select CPU_TLB_V3 if MMU |
| 53 | select CPU_PABRT_NOIFAR | ||
| 52 | help | 54 | help |
| 53 | A 32-bit RISC microprocessor based on the ARM7 processor core | 55 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 54 | designed by Advanced RISC Machines Ltd. The ARM710 is the | 56 | designed by Advanced RISC Machines Ltd. The ARM710 is the |
| @@ -64,6 +66,7 @@ config CPU_ARM720T | |||
| 64 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X | 66 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X |
| 65 | select CPU_32v4T | 67 | select CPU_32v4T |
| 66 | select CPU_ABRT_LV4T | 68 | select CPU_ABRT_LV4T |
| 69 | select CPU_PABRT_NOIFAR | ||
| 67 | select CPU_CACHE_V4 | 70 | select CPU_CACHE_V4 |
| 68 | select CPU_CACHE_VIVT | 71 | select CPU_CACHE_VIVT |
| 69 | select CPU_CP15_MMU | 72 | select CPU_CP15_MMU |
| @@ -113,6 +116,7 @@ config CPU_ARM920T | |||
| 113 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 | 116 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 |
| 114 | select CPU_32v4T | 117 | select CPU_32v4T |
| 115 | select CPU_ABRT_EV4T | 118 | select CPU_ABRT_EV4T |
| 119 | select CPU_PABRT_NOIFAR | ||
| 116 | select CPU_CACHE_V4WT | 120 | select CPU_CACHE_V4WT |
| 117 | select CPU_CACHE_VIVT | 121 | select CPU_CACHE_VIVT |
| 118 | select CPU_CP15_MMU | 122 | select CPU_CP15_MMU |
| @@ -135,6 +139,7 @@ config CPU_ARM922T | |||
| 135 | default y if ARCH_LH7A40X || ARCH_KS8695 | 139 | default y if ARCH_LH7A40X || ARCH_KS8695 |
| 136 | select CPU_32v4T | 140 | select CPU_32v4T |
| 137 | select CPU_ABRT_EV4T | 141 | select CPU_ABRT_EV4T |
| 142 | select CPU_PABRT_NOIFAR | ||
| 138 | select CPU_CACHE_V4WT | 143 | select CPU_CACHE_V4WT |
| 139 | select CPU_CACHE_VIVT | 144 | select CPU_CACHE_VIVT |
| 140 | select CPU_CP15_MMU | 145 | select CPU_CP15_MMU |
| @@ -155,6 +160,7 @@ config CPU_ARM925T | |||
| 155 | default y if ARCH_OMAP15XX | 160 | default y if ARCH_OMAP15XX |
| 156 | select CPU_32v4T | 161 | select CPU_32v4T |
| 157 | select CPU_ABRT_EV4T | 162 | select CPU_ABRT_EV4T |
| 163 | select CPU_PABRT_NOIFAR | ||
| 158 | select CPU_CACHE_V4WT | 164 | select CPU_CACHE_V4WT |
| 159 | select CPU_CACHE_VIVT | 165 | select CPU_CACHE_VIVT |
| 160 | select CPU_CP15_MMU | 166 | select CPU_CP15_MMU |
| @@ -175,6 +181,7 @@ config CPU_ARM926T | |||
| 175 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI | 181 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI |
| 176 | select CPU_32v5 | 182 | select CPU_32v5 |
| 177 | select CPU_ABRT_EV5TJ | 183 | select CPU_ABRT_EV5TJ |
| 184 | select CPU_PABRT_NOIFAR | ||
| 178 | select CPU_CACHE_VIVT | 185 | select CPU_CACHE_VIVT |
| 179 | select CPU_CP15_MMU | 186 | select CPU_CP15_MMU |
| 180 | select CPU_COPY_V4WB if MMU | 187 | select CPU_COPY_V4WB if MMU |
| @@ -226,6 +233,7 @@ config CPU_ARM1020 | |||
| 226 | depends on ARCH_INTEGRATOR | 233 | depends on ARCH_INTEGRATOR |
| 227 | select CPU_32v5 | 234 | select CPU_32v5 |
| 228 | select CPU_ABRT_EV4T | 235 | select CPU_ABRT_EV4T |
| 236 | select CPU_PABRT_NOIFAR | ||
| 229 | select CPU_CACHE_V4WT | 237 | select CPU_CACHE_V4WT |
| 230 | select CPU_CACHE_VIVT | 238 | select CPU_CACHE_VIVT |
| 231 | select CPU_CP15_MMU | 239 | select CPU_CP15_MMU |
| @@ -244,6 +252,7 @@ config CPU_ARM1020E | |||
| 244 | depends on ARCH_INTEGRATOR | 252 | depends on ARCH_INTEGRATOR |
| 245 | select CPU_32v5 | 253 | select CPU_32v5 |
| 246 | select CPU_ABRT_EV4T | 254 | select CPU_ABRT_EV4T |
| 255 | select CPU_PABRT_NOIFAR | ||
| 247 | select CPU_CACHE_V4WT | 256 | select CPU_CACHE_V4WT |
| 248 | select CPU_CACHE_VIVT | 257 | select CPU_CACHE_VIVT |
| 249 | select CPU_CP15_MMU | 258 | select CPU_CP15_MMU |
| @@ -257,6 +266,7 @@ config CPU_ARM1022 | |||
| 257 | depends on ARCH_INTEGRATOR | 266 | depends on ARCH_INTEGRATOR |
| 258 | select CPU_32v5 | 267 | select CPU_32v5 |
| 259 | select CPU_ABRT_EV4T | 268 | select CPU_ABRT_EV4T |
| 269 | select CPU_PABRT_NOIFAR | ||
| 260 | select CPU_CACHE_VIVT | 270 | select CPU_CACHE_VIVT |
| 261 | select CPU_CP15_MMU | 271 | select CPU_CP15_MMU |
| 262 | select CPU_COPY_V4WB if MMU # can probably do better | 272 | select CPU_COPY_V4WB if MMU # can probably do better |
| @@ -275,6 +285,7 @@ config CPU_ARM1026 | |||
| 275 | depends on ARCH_INTEGRATOR | 285 | depends on ARCH_INTEGRATOR |
| 276 | select CPU_32v5 | 286 | select CPU_32v5 |
| 277 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | 287 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 |
| 288 | select CPU_PABRT_NOIFAR | ||
| 278 | select CPU_CACHE_VIVT | 289 | select CPU_CACHE_VIVT |
| 279 | select CPU_CP15_MMU | 290 | select CPU_CP15_MMU |
| 280 | select CPU_COPY_V4WB if MMU # can probably do better | 291 | select CPU_COPY_V4WB if MMU # can probably do better |
| @@ -293,6 +304,7 @@ config CPU_SA110 | |||
| 293 | select CPU_32v3 if ARCH_RPC | 304 | select CPU_32v3 if ARCH_RPC |
| 294 | select CPU_32v4 if !ARCH_RPC | 305 | select CPU_32v4 if !ARCH_RPC |
| 295 | select CPU_ABRT_EV4 | 306 | select CPU_ABRT_EV4 |
| 307 | select CPU_PABRT_NOIFAR | ||
| 296 | select CPU_CACHE_V4WB | 308 | select CPU_CACHE_V4WB |
| 297 | select CPU_CACHE_VIVT | 309 | select CPU_CACHE_VIVT |
| 298 | select CPU_CP15_MMU | 310 | select CPU_CP15_MMU |
| @@ -314,6 +326,7 @@ config CPU_SA1100 | |||
| 314 | default y | 326 | default y |
| 315 | select CPU_32v4 | 327 | select CPU_32v4 |
| 316 | select CPU_ABRT_EV4 | 328 | select CPU_ABRT_EV4 |
| 329 | select CPU_PABRT_NOIFAR | ||
| 317 | select CPU_CACHE_V4WB | 330 | select CPU_CACHE_V4WB |
| 318 | select CPU_CACHE_VIVT | 331 | select CPU_CACHE_VIVT |
| 319 | select CPU_CP15_MMU | 332 | select CPU_CP15_MMU |
| @@ -326,6 +339,7 @@ config CPU_XSCALE | |||
| 326 | default y | 339 | default y |
| 327 | select CPU_32v5 | 340 | select CPU_32v5 |
| 328 | select CPU_ABRT_EV5T | 341 | select CPU_ABRT_EV5T |
| 342 | select CPU_PABRT_NOIFAR | ||
| 329 | select CPU_CACHE_VIVT | 343 | select CPU_CACHE_VIVT |
| 330 | select CPU_CP15_MMU | 344 | select CPU_CP15_MMU |
| 331 | select CPU_TLB_V4WBI if MMU | 345 | select CPU_TLB_V4WBI if MMU |
| @@ -345,10 +359,11 @@ config CPU_XSC3 | |||
| 345 | # Feroceon | 359 | # Feroceon |
| 346 | config CPU_FEROCEON | 360 | config CPU_FEROCEON |
| 347 | bool | 361 | bool |
| 348 | depends on ARCH_ORION | 362 | depends on ARCH_ORION5X |
| 349 | default y | 363 | default y |
| 350 | select CPU_32v5 | 364 | select CPU_32v5 |
| 351 | select CPU_ABRT_EV5T | 365 | select CPU_ABRT_EV5T |
| 366 | select CPU_PABRT_NOIFAR | ||
| 352 | select CPU_CACHE_VIVT | 367 | select CPU_CACHE_VIVT |
| 353 | select CPU_CP15_MMU | 368 | select CPU_CP15_MMU |
| 354 | select CPU_COPY_V4WB if MMU | 369 | select CPU_COPY_V4WB if MMU |
| @@ -366,11 +381,12 @@ config CPU_FEROCEON_OLD_ID | |||
| 366 | # ARMv6 | 381 | # ARMv6 |
| 367 | config CPU_V6 | 382 | config CPU_V6 |
| 368 | bool "Support ARM V6 processor" | 383 | bool "Support ARM V6 processor" |
| 369 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A | 384 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 |
| 370 | default y if ARCH_MX3 | 385 | default y if ARCH_MX3 |
| 371 | default y if ARCH_MSM7X00A | 386 | default y if ARCH_MSM7X00A |
| 372 | select CPU_32v6 | 387 | select CPU_32v6 |
| 373 | select CPU_ABRT_EV6 | 388 | select CPU_ABRT_EV6 |
| 389 | select CPU_PABRT_NOIFAR | ||
| 374 | select CPU_CACHE_V6 | 390 | select CPU_CACHE_V6 |
| 375 | select CPU_CACHE_VIPT | 391 | select CPU_CACHE_VIPT |
| 376 | select CPU_CP15_MMU | 392 | select CPU_CP15_MMU |
| @@ -393,10 +409,11 @@ config CPU_32v6K | |||
| 393 | # ARMv7 | 409 | # ARMv7 |
| 394 | config CPU_V7 | 410 | config CPU_V7 |
| 395 | bool "Support ARM V7 processor" | 411 | bool "Support ARM V7 processor" |
| 396 | depends on ARCH_INTEGRATOR | 412 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB |
| 397 | select CPU_32v6K | 413 | select CPU_32v6K |
| 398 | select CPU_32v7 | 414 | select CPU_32v7 |
| 399 | select CPU_ABRT_EV7 | 415 | select CPU_ABRT_EV7 |
| 416 | select CPU_PABRT_IFAR | ||
| 400 | select CPU_CACHE_V7 | 417 | select CPU_CACHE_V7 |
| 401 | select CPU_CACHE_VIPT | 418 | select CPU_CACHE_VIPT |
| 402 | select CPU_CP15_MMU | 419 | select CPU_CP15_MMU |
| @@ -458,6 +475,12 @@ config CPU_ABRT_EV6 | |||
| 458 | config CPU_ABRT_EV7 | 475 | config CPU_ABRT_EV7 |
| 459 | bool | 476 | bool |
| 460 | 477 | ||
| 478 | config CPU_PABRT_IFAR | ||
| 479 | bool | ||
| 480 | |||
| 481 | config CPU_PABRT_NOIFAR | ||
| 482 | bool | ||
| 483 | |||
| 461 | # The cache model | 484 | # The cache model |
| 462 | config CPU_CACHE_V3 | 485 | config CPU_CACHE_V3 |
| 463 | bool | 486 | bool |
| @@ -572,6 +595,13 @@ config ARM_THUMB | |||
| 572 | 595 | ||
| 573 | If you don't know what this all is, saying Y is a safe choice. | 596 | If you don't know what this all is, saying Y is a safe choice. |
| 574 | 597 | ||
| 598 | config ARM_THUMBEE | ||
| 599 | bool "Enable ThumbEE CPU extension" | ||
| 600 | depends on CPU_V7 | ||
| 601 | help | ||
| 602 | Say Y here if you have a CPU with the ThumbEE extension and code to | ||
| 603 | make use of it. Say N for code that can run on CPUs without ThumbEE. | ||
| 604 | |||
| 575 | config CPU_BIG_ENDIAN | 605 | config CPU_BIG_ENDIAN |
| 576 | bool "Build big-endian kernel" | 606 | bool "Build big-endian kernel" |
| 577 | depends on ARCH_SUPPORTS_BIG_ENDIAN | 607 | depends on ARCH_SUPPORTS_BIG_ENDIAN |
| @@ -671,5 +701,9 @@ config OUTER_CACHE | |||
| 671 | default n | 701 | default n |
| 672 | 702 | ||
| 673 | config CACHE_L2X0 | 703 | config CACHE_L2X0 |
| 674 | bool | 704 | bool "Enable the L2x0 outer cache controller" |
| 705 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 | ||
| 706 | default y | ||
| 675 | select OUTER_CACHE | 707 | select OUTER_CACHE |
| 708 | help | ||
| 709 | This option enables the L2x0 PrimeCell. | ||
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index ec00f26bffa4..b657f1719af0 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
| @@ -48,8 +48,6 @@ void show_mem(void) | |||
| 48 | 48 | ||
| 49 | printk("Mem-info:\n"); | 49 | printk("Mem-info:\n"); |
| 50 | show_free_areas(); | 50 | show_free_areas(); |
| 51 | printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10)); | ||
| 52 | |||
| 53 | for_each_online_node(node) { | 51 | for_each_online_node(node) { |
| 54 | pg_data_t *n = NODE_DATA(node); | 52 | pg_data_t *n = NODE_DATA(node); |
| 55 | struct page *map = n->node_mem_map - n->node_start_pfn; | 53 | struct page *map = n->node_mem_map - n->node_start_pfn; |
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 700c04d6996e..32fd7ea533f2 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S | |||
| @@ -478,6 +478,7 @@ arm1020_processor_functions: | |||
| 478 | .word cpu_arm1020_dcache_clean_area | 478 | .word cpu_arm1020_dcache_clean_area |
| 479 | .word cpu_arm1020_switch_mm | 479 | .word cpu_arm1020_switch_mm |
| 480 | .word cpu_arm1020_set_pte_ext | 480 | .word cpu_arm1020_set_pte_ext |
| 481 | .word pabort_noifar | ||
| 481 | .size arm1020_processor_functions, . - arm1020_processor_functions | 482 | .size arm1020_processor_functions, . - arm1020_processor_functions |
| 482 | 483 | ||
| 483 | .section ".rodata" | 484 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 1cc206ab5eae..fe2b0ae70274 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S | |||
| @@ -459,6 +459,7 @@ arm1020e_processor_functions: | |||
| 459 | .word cpu_arm1020e_dcache_clean_area | 459 | .word cpu_arm1020e_dcache_clean_area |
| 460 | .word cpu_arm1020e_switch_mm | 460 | .word cpu_arm1020e_switch_mm |
| 461 | .word cpu_arm1020e_set_pte_ext | 461 | .word cpu_arm1020e_set_pte_ext |
| 462 | .word pabort_noifar | ||
| 462 | .size arm1020e_processor_functions, . - arm1020e_processor_functions | 463 | .size arm1020e_processor_functions, . - arm1020e_processor_functions |
| 463 | 464 | ||
| 464 | .section ".rodata" | 465 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index aff0ea08e2f8..06dde678e19d 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S | |||
| @@ -442,6 +442,7 @@ arm1022_processor_functions: | |||
| 442 | .word cpu_arm1022_dcache_clean_area | 442 | .word cpu_arm1022_dcache_clean_area |
| 443 | .word cpu_arm1022_switch_mm | 443 | .word cpu_arm1022_switch_mm |
| 444 | .word cpu_arm1022_set_pte_ext | 444 | .word cpu_arm1022_set_pte_ext |
| 445 | .word pabort_noifar | ||
| 445 | .size arm1022_processor_functions, . - arm1022_processor_functions | 446 | .size arm1022_processor_functions, . - arm1022_processor_functions |
| 446 | 447 | ||
| 447 | .section ".rodata" | 448 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 65e43a109085..f5506e6e681e 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S | |||
| @@ -437,6 +437,7 @@ arm1026_processor_functions: | |||
| 437 | .word cpu_arm1026_dcache_clean_area | 437 | .word cpu_arm1026_dcache_clean_area |
| 438 | .word cpu_arm1026_switch_mm | 438 | .word cpu_arm1026_switch_mm |
| 439 | .word cpu_arm1026_set_pte_ext | 439 | .word cpu_arm1026_set_pte_ext |
| 440 | .word pabort_noifar | ||
| 440 | .size arm1026_processor_functions, . - arm1026_processor_functions | 441 | .size arm1026_processor_functions, . - arm1026_processor_functions |
| 441 | 442 | ||
| 442 | .section .rodata | 443 | .section .rodata |
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 123a7dc7a433..14b6a95c8d45 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S | |||
| @@ -300,6 +300,7 @@ ENTRY(arm6_processor_functions) | |||
| 300 | .word cpu_arm6_dcache_clean_area | 300 | .word cpu_arm6_dcache_clean_area |
| 301 | .word cpu_arm6_switch_mm | 301 | .word cpu_arm6_switch_mm |
| 302 | .word cpu_arm6_set_pte_ext | 302 | .word cpu_arm6_set_pte_ext |
| 303 | .word pabort_noifar | ||
| 303 | .size arm6_processor_functions, . - arm6_processor_functions | 304 | .size arm6_processor_functions, . - arm6_processor_functions |
| 304 | 305 | ||
| 305 | /* | 306 | /* |
| @@ -316,6 +317,7 @@ ENTRY(arm7_processor_functions) | |||
| 316 | .word cpu_arm7_dcache_clean_area | 317 | .word cpu_arm7_dcache_clean_area |
| 317 | .word cpu_arm7_switch_mm | 318 | .word cpu_arm7_switch_mm |
| 318 | .word cpu_arm7_set_pte_ext | 319 | .word cpu_arm7_set_pte_ext |
| 320 | .word pabort_noifar | ||
| 319 | .size arm7_processor_functions, . - arm7_processor_functions | 321 | .size arm7_processor_functions, . - arm7_processor_functions |
| 320 | 322 | ||
| 321 | .section ".rodata" | 323 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index dc763be43362..ca5e7aac2da7 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S | |||
| @@ -205,6 +205,7 @@ ENTRY(arm720_processor_functions) | |||
| 205 | .word cpu_arm720_dcache_clean_area | 205 | .word cpu_arm720_dcache_clean_area |
| 206 | .word cpu_arm720_switch_mm | 206 | .word cpu_arm720_switch_mm |
| 207 | .word cpu_arm720_set_pte_ext | 207 | .word cpu_arm720_set_pte_ext |
| 208 | .word pabort_noifar | ||
| 208 | .size arm720_processor_functions, . - arm720_processor_functions | 209 | .size arm720_processor_functions, . - arm720_processor_functions |
| 209 | 210 | ||
| 210 | .section ".rodata" | 211 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 75c945ed6c4d..0170d4f466ea 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S | |||
| @@ -424,6 +424,7 @@ arm920_processor_functions: | |||
| 424 | .word cpu_arm920_dcache_clean_area | 424 | .word cpu_arm920_dcache_clean_area |
| 425 | .word cpu_arm920_switch_mm | 425 | .word cpu_arm920_switch_mm |
| 426 | .word cpu_arm920_set_pte_ext | 426 | .word cpu_arm920_set_pte_ext |
| 427 | .word pabort_noifar | ||
| 427 | .size arm920_processor_functions, . - arm920_processor_functions | 428 | .size arm920_processor_functions, . - arm920_processor_functions |
| 428 | 429 | ||
| 429 | .section ".rodata" | 430 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index ffb751b877ff..b7952493d404 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S | |||
| @@ -428,6 +428,7 @@ arm922_processor_functions: | |||
| 428 | .word cpu_arm922_dcache_clean_area | 428 | .word cpu_arm922_dcache_clean_area |
| 429 | .word cpu_arm922_switch_mm | 429 | .word cpu_arm922_switch_mm |
| 430 | .word cpu_arm922_set_pte_ext | 430 | .word cpu_arm922_set_pte_ext |
| 431 | .word pabort_noifar | ||
| 431 | .size arm922_processor_functions, . - arm922_processor_functions | 432 | .size arm922_processor_functions, . - arm922_processor_functions |
| 432 | 433 | ||
| 433 | .section ".rodata" | 434 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 44c2c997819f..e2988eba4cf6 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S | |||
| @@ -491,6 +491,7 @@ arm925_processor_functions: | |||
| 491 | .word cpu_arm925_dcache_clean_area | 491 | .word cpu_arm925_dcache_clean_area |
| 492 | .word cpu_arm925_switch_mm | 492 | .word cpu_arm925_switch_mm |
| 493 | .word cpu_arm925_set_pte_ext | 493 | .word cpu_arm925_set_pte_ext |
| 494 | .word pabort_noifar | ||
| 494 | .size arm925_processor_functions, . - arm925_processor_functions | 495 | .size arm925_processor_functions, . - arm925_processor_functions |
| 495 | 496 | ||
| 496 | .section ".rodata" | 497 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 194ef48968e6..62f7d1dfe016 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
| @@ -444,6 +444,7 @@ arm926_processor_functions: | |||
| 444 | .word cpu_arm926_dcache_clean_area | 444 | .word cpu_arm926_dcache_clean_area |
| 445 | .word cpu_arm926_switch_mm | 445 | .word cpu_arm926_switch_mm |
| 446 | .word cpu_arm926_set_pte_ext | 446 | .word cpu_arm926_set_pte_ext |
| 447 | .word pabort_noifar | ||
| 447 | .size arm926_processor_functions, . - arm926_processor_functions | 448 | .size arm926_processor_functions, . - arm926_processor_functions |
| 448 | 449 | ||
| 449 | .section ".rodata" | 450 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index fa0dc7e6f0ea..2f169b28e938 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
| @@ -430,6 +430,7 @@ feroceon_processor_functions: | |||
| 430 | .word cpu_feroceon_dcache_clean_area | 430 | .word cpu_feroceon_dcache_clean_area |
| 431 | .word cpu_feroceon_switch_mm | 431 | .word cpu_feroceon_switch_mm |
| 432 | .word cpu_feroceon_set_pte_ext | 432 | .word cpu_feroceon_set_pte_ext |
| 433 | .word pabort_noifar | ||
| 433 | .size feroceon_processor_functions, . - feroceon_processor_functions | 434 | .size feroceon_processor_functions, . - feroceon_processor_functions |
| 434 | 435 | ||
| 435 | .section ".rodata" | 436 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 6e226e12989f..4db3d6299a2b 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S | |||
| @@ -223,6 +223,7 @@ ENTRY(sa110_processor_functions) | |||
| 223 | .word cpu_sa110_dcache_clean_area | 223 | .word cpu_sa110_dcache_clean_area |
| 224 | .word cpu_sa110_switch_mm | 224 | .word cpu_sa110_switch_mm |
| 225 | .word cpu_sa110_set_pte_ext | 225 | .word cpu_sa110_set_pte_ext |
| 226 | .word pabort_noifar | ||
| 226 | .size sa110_processor_functions, . - sa110_processor_functions | 227 | .size sa110_processor_functions, . - sa110_processor_functions |
| 227 | 228 | ||
| 228 | .section ".rodata" | 229 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 9afb11d089fe..3cdef043760f 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S | |||
| @@ -238,6 +238,7 @@ ENTRY(sa1100_processor_functions) | |||
| 238 | .word cpu_sa1100_dcache_clean_area | 238 | .word cpu_sa1100_dcache_clean_area |
| 239 | .word cpu_sa1100_switch_mm | 239 | .word cpu_sa1100_switch_mm |
| 240 | .word cpu_sa1100_set_pte_ext | 240 | .word cpu_sa1100_set_pte_ext |
| 241 | .word pabort_noifar | ||
| 241 | .size sa1100_processor_functions, . - sa1100_processor_functions | 242 | .size sa1100_processor_functions, . - sa1100_processor_functions |
| 242 | 243 | ||
| 243 | .section ".rodata" | 244 | .section ".rodata" |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index eb42e5b94863..bf760ea2f789 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
| @@ -17,10 +17,6 @@ | |||
| 17 | #include <asm/pgtable-hwdef.h> | 17 | #include <asm/pgtable-hwdef.h> |
| 18 | #include <asm/pgtable.h> | 18 | #include <asm/pgtable.h> |
| 19 | 19 | ||
| 20 | #ifdef CONFIG_SMP | ||
| 21 | #include <asm/hardware/arm_scu.h> | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #include "proc-macros.S" | 20 | #include "proc-macros.S" |
| 25 | 21 | ||
| 26 | #define D_CACHE_LINE_SIZE 32 | 22 | #define D_CACHE_LINE_SIZE 32 |
| @@ -187,20 +183,10 @@ cpu_v6_name: | |||
| 187 | */ | 183 | */ |
| 188 | __v6_setup: | 184 | __v6_setup: |
| 189 | #ifdef CONFIG_SMP | 185 | #ifdef CONFIG_SMP |
| 190 | /* Set up the SCU on core 0 only */ | ||
| 191 | mrc p15, 0, r0, c0, c0, 5 @ CPU core number | ||
| 192 | ands r0, r0, #15 | ||
| 193 | ldreq r0, =SCU_BASE | ||
| 194 | ldreq r5, [r0, #SCU_CTRL] | ||
| 195 | orreq r5, r5, #1 | ||
| 196 | streq r5, [r0, #SCU_CTRL] | ||
| 197 | |||
| 198 | #ifndef CONFIG_CPU_DCACHE_DISABLE | ||
| 199 | mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode | 186 | mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode |
| 200 | orr r0, r0, #0x20 | 187 | orr r0, r0, #0x20 |
| 201 | mcr p15, 0, r0, c1, c0, 1 | 188 | mcr p15, 0, r0, c1, c0, 1 |
| 202 | #endif | 189 | #endif |
| 203 | #endif | ||
| 204 | 190 | ||
| 205 | mov r0, #0 | 191 | mov r0, #0 |
| 206 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | 192 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache |
| @@ -240,6 +226,7 @@ ENTRY(v6_processor_functions) | |||
| 240 | .word cpu_v6_dcache_clean_area | 226 | .word cpu_v6_dcache_clean_area |
| 241 | .word cpu_v6_switch_mm | 227 | .word cpu_v6_switch_mm |
| 242 | .word cpu_v6_set_pte_ext | 228 | .word cpu_v6_set_pte_ext |
| 229 | .word pabort_noifar | ||
| 243 | .size v6_processor_functions, . - v6_processor_functions | 230 | .size v6_processor_functions, . - v6_processor_functions |
| 244 | 231 | ||
| 245 | .type cpu_arch_name, #object | 232 | .type cpu_arch_name, #object |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index e0acc5ae6f6f..a1d7331cd64c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -212,6 +212,7 @@ ENTRY(v7_processor_functions) | |||
| 212 | .word cpu_v7_dcache_clean_area | 212 | .word cpu_v7_dcache_clean_area |
| 213 | .word cpu_v7_switch_mm | 213 | .word cpu_v7_switch_mm |
| 214 | .word cpu_v7_set_pte_ext | 214 | .word cpu_v7_set_pte_ext |
| 215 | .word pabort_ifar | ||
| 215 | .size v7_processor_functions, . - v7_processor_functions | 216 | .size v7_processor_functions, . - v7_processor_functions |
| 216 | 217 | ||
| 217 | .type cpu_arch_name, #object | 218 | .type cpu_arch_name, #object |
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 016690b9d564..1a6d89823dff 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
| @@ -534,6 +534,7 @@ ENTRY(xscale_processor_functions) | |||
| 534 | .word cpu_xscale_dcache_clean_area | 534 | .word cpu_xscale_dcache_clean_area |
| 535 | .word cpu_xscale_switch_mm | 535 | .word cpu_xscale_switch_mm |
| 536 | .word cpu_xscale_set_pte_ext | 536 | .word cpu_xscale_set_pte_ext |
| 537 | .word pabort_noifar | ||
| 537 | .size xscale_processor_functions, . - xscale_processor_functions | 538 | .size xscale_processor_functions, . - xscale_processor_functions |
| 538 | 539 | ||
| 539 | .section ".rodata" | 540 | .section ".rodata" |
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 98d01517b563..d9bc15a69e5d 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | #include <asm/mach/pci.h> | 25 | #include <asm/mach/pci.h> |
| 26 | #include <asm/hardware/iop3xx.h> | 26 | #include <asm/hardware/iop3xx.h> |
| 27 | #include <asm/mach-types.h> | ||
| 27 | 28 | ||
| 28 | // #define DEBUG | 29 | // #define DEBUG |
| 29 | 30 | ||
| @@ -209,8 +210,11 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
| 209 | res[1].flags = IORESOURCE_MEM; | 210 | res[1].flags = IORESOURCE_MEM; |
| 210 | request_resource(&iomem_resource, &res[1]); | 211 | request_resource(&iomem_resource, &res[1]); |
| 211 | 212 | ||
| 212 | sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA; | 213 | /* |
| 213 | sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA; | 214 | * Use whatever translation is already setup. |
| 215 | */ | ||
| 216 | sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; | ||
| 217 | sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; | ||
| 214 | 218 | ||
| 215 | sys->resource[0] = &res[0]; | 219 | sys->resource[0] = &res[0]; |
| 216 | sys->resource[1] = &res[1]; | 220 | sys->resource[1] = &res[1]; |
| @@ -250,11 +254,11 @@ void __init iop3xx_atu_setup(void) | |||
| 250 | *IOP3XX_IATVR2 = PHYS_OFFSET; | 254 | *IOP3XX_IATVR2 = PHYS_OFFSET; |
| 251 | 255 | ||
| 252 | /* Outbound window 0 */ | 256 | /* Outbound window 0 */ |
| 253 | *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA; | 257 | *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; |
| 254 | *IOP3XX_OUMWTVR0 = 0; | 258 | *IOP3XX_OUMWTVR0 = 0; |
| 255 | 259 | ||
| 256 | /* Outbound window 1 */ | 260 | /* Outbound window 1 */ |
| 257 | *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE; | 261 | *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE; |
| 258 | *IOP3XX_OUMWTVR1 = 0; | 262 | *IOP3XX_OUMWTVR1 = 0; |
| 259 | 263 | ||
| 260 | /* BAR 3 ( Disabled ) */ | 264 | /* BAR 3 ( Disabled ) */ |
| @@ -265,7 +269,7 @@ void __init iop3xx_atu_setup(void) | |||
| 265 | 269 | ||
| 266 | /* Setup the I/O Bar | 270 | /* Setup the I/O Bar |
| 267 | */ | 271 | */ |
| 268 | *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;; | 272 | *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; |
| 269 | 273 | ||
| 270 | /* Enable inbound and outbound cycles | 274 | /* Enable inbound and outbound cycles |
| 271 | */ | 275 | */ |
| @@ -322,34 +326,59 @@ void __init iop3xx_atu_disable(void) | |||
| 322 | /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ | 326 | /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ |
| 323 | int init_atu; | 327 | int init_atu; |
| 324 | 328 | ||
| 325 | void __init iop3xx_pci_preinit(void) | 329 | int iop3xx_get_init_atu(void) { |
| 330 | /* check if default has been overridden */ | ||
| 331 | if (init_atu != IOP3XX_INIT_ATU_DEFAULT) | ||
| 332 | return init_atu; | ||
| 333 | else | ||
| 334 | return IOP3XX_INIT_ATU_DISABLE; | ||
| 335 | } | ||
| 336 | |||
| 337 | static void __init iop3xx_atu_debug(void) | ||
| 326 | { | 338 | { |
| 327 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { | 339 | DBG("PCI: Intel IOP3xx PCI init.\n"); |
| 328 | iop3xx_atu_disable(); | 340 | DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", |
| 329 | iop3xx_atu_setup(); | 341 | *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); |
| 330 | } | 342 | DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", |
| 343 | *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); | ||
| 344 | DBG("PCI: Outbound IO window: PCI 0x%08x\n", | ||
| 345 | *IOP3XX_OIOWTVR); | ||
| 346 | |||
| 347 | DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 348 | *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); | ||
| 349 | DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", | ||
| 350 | *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); | ||
| 351 | DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 352 | *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); | ||
| 353 | DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 354 | *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); | ||
| 355 | |||
| 356 | DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 357 | 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); | ||
| 331 | 358 | ||
| 332 | DBG("PCI: Intel 803xx PCI init code.\n"); | ||
| 333 | DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); | 359 | DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); |
| 334 | DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", | ||
| 335 | *IOP3XX_OMWTVR0, | ||
| 336 | *IOP3XX_OIOWTVR); | ||
| 337 | DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); | 360 | DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); |
| 338 | DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n", | ||
| 339 | *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); | ||
| 340 | DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0); | ||
| 341 | DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n", | ||
| 342 | *IOP3XX_IABAR1, *IOP3XX_IALR1); | ||
| 343 | DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n", | ||
| 344 | *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); | ||
| 345 | DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n", | ||
| 346 | *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); | ||
| 347 | DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n", | ||
| 348 | *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); | ||
| 349 | 361 | ||
| 350 | hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); | 362 | hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); |
| 351 | } | 363 | } |
| 352 | 364 | ||
| 365 | /* for platforms that might be host-bus-adapters */ | ||
| 366 | void __init iop3xx_pci_preinit_cond(void) | ||
| 367 | { | ||
| 368 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { | ||
| 369 | iop3xx_atu_disable(); | ||
| 370 | iop3xx_atu_setup(); | ||
| 371 | iop3xx_atu_debug(); | ||
| 372 | } | ||
| 373 | } | ||
| 374 | |||
| 375 | void __init iop3xx_pci_preinit(void) | ||
| 376 | { | ||
| 377 | iop3xx_atu_disable(); | ||
| 378 | iop3xx_atu_setup(); | ||
| 379 | iop3xx_atu_debug(); | ||
| 380 | } | ||
| 381 | |||
| 353 | /* allow init_atu to be user overridden */ | 382 | /* allow init_atu to be user overridden */ |
| 354 | static int __init iop3xx_init_atu_setup(char *str) | 383 | static int __init iop3xx_init_atu_setup(char *str) |
| 355 | { | 384 | { |
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 03a65c0dfb60..bb6e12738fb3 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -4,7 +4,7 @@ menu "Freescale MXC Implementations" | |||
| 4 | 4 | ||
| 5 | choice | 5 | choice |
| 6 | prompt "MXC/iMX System Type" | 6 | prompt "MXC/iMX System Type" |
| 7 | default 0 | 7 | default ARCH_MX3 |
| 8 | 8 | ||
| 9 | config ARCH_MX3 | 9 | config ARCH_MX3 |
| 10 | bool "MX3-based" | 10 | bool "MX3-based" |
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 66ad9c2b6d64..f96dc0362068 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile | |||
| @@ -4,7 +4,3 @@ | |||
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o | 6 | obj-y := irq.o |
| 7 | |||
| 8 | obj-m := | ||
| 9 | obj-n := | ||
| 10 | obj- := | ||
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 87d253bc3d3c..2ad5a6917b3f 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c | |||
| @@ -19,21 +19,13 @@ | |||
| 19 | #include <asm/mach/irq.h> | 19 | #include <asm/mach/irq.h> |
| 20 | #include <asm/arch/common.h> | 20 | #include <asm/arch/common.h> |
| 21 | 21 | ||
| 22 | /*! | 22 | /* Disable interrupt number "irq" in the AVIC */ |
| 23 | * Disable interrupt number "irq" in the AVIC | ||
| 24 | * | ||
| 25 | * @param irq interrupt source number | ||
| 26 | */ | ||
| 27 | static void mxc_mask_irq(unsigned int irq) | 23 | static void mxc_mask_irq(unsigned int irq) |
| 28 | { | 24 | { |
| 29 | __raw_writel(irq, AVIC_INTDISNUM); | 25 | __raw_writel(irq, AVIC_INTDISNUM); |
| 30 | } | 26 | } |
| 31 | 27 | ||
| 32 | /*! | 28 | /* Enable interrupt number "irq" in the AVIC */ |
| 33 | * Enable interrupt number "irq" in the AVIC | ||
| 34 | * | ||
| 35 | * @param irq interrupt source number | ||
| 36 | */ | ||
| 37 | static void mxc_unmask_irq(unsigned int irq) | 29 | static void mxc_unmask_irq(unsigned int irq) |
| 38 | { | 30 | { |
| 39 | __raw_writel(irq, AVIC_INTENNUM); | 31 | __raw_writel(irq, AVIC_INTENNUM); |
| @@ -45,7 +37,7 @@ static struct irq_chip mxc_avic_chip = { | |||
| 45 | .unmask = mxc_unmask_irq, | 37 | .unmask = mxc_unmask_irq, |
| 46 | }; | 38 | }; |
| 47 | 39 | ||
| 48 | /*! | 40 | /* |
| 49 | * This function initializes the AVIC hardware and disables all the | 41 | * This function initializes the AVIC hardware and disables all the |
| 50 | * interrupts. It registers the interrupt enable and disable functions | 42 | * interrupts. It registers the interrupt enable and disable functions |
| 51 | * to the kernel for each interrupt source. | 43 | * to the kernel for each interrupt source. |
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile new file mode 100644 index 000000000000..198f3dde2be3 --- /dev/null +++ b/arch/arm/plat-orion/Makefile | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the linux kernel. | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y := irq.o pcie.o time.o | ||
| 6 | obj-m := | ||
| 7 | obj-n := | ||
| 8 | obj- := | ||
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c new file mode 100644 index 000000000000..c5b669d234bc --- /dev/null +++ b/arch/arm/plat-orion/irq.c | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/irq.c | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC IRQ handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/irq.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <asm/plat-orion/irq.h> | ||
| 16 | |||
| 17 | static void orion_irq_mask(u32 irq) | ||
| 18 | { | ||
| 19 | void __iomem *maskaddr = get_irq_chip_data(irq); | ||
| 20 | u32 mask; | ||
| 21 | |||
| 22 | mask = readl(maskaddr); | ||
| 23 | mask &= ~(1 << (irq & 31)); | ||
| 24 | writel(mask, maskaddr); | ||
| 25 | } | ||
| 26 | |||
| 27 | static void orion_irq_unmask(u32 irq) | ||
| 28 | { | ||
| 29 | void __iomem *maskaddr = get_irq_chip_data(irq); | ||
| 30 | u32 mask; | ||
| 31 | |||
| 32 | mask = readl(maskaddr); | ||
| 33 | mask |= 1 << (irq & 31); | ||
| 34 | writel(mask, maskaddr); | ||
| 35 | } | ||
| 36 | |||
| 37 | static struct irq_chip orion_irq_chip = { | ||
| 38 | .name = "orion_irq", | ||
| 39 | .ack = orion_irq_mask, | ||
| 40 | .mask = orion_irq_mask, | ||
| 41 | .unmask = orion_irq_unmask, | ||
| 42 | }; | ||
| 43 | |||
| 44 | void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) | ||
| 45 | { | ||
| 46 | unsigned int i; | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Mask all interrupts initially. | ||
| 50 | */ | ||
| 51 | writel(0, maskaddr); | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Register IRQ sources. | ||
| 55 | */ | ||
| 56 | for (i = 0; i < 32; i++) { | ||
| 57 | unsigned int irq = irq_start + i; | ||
| 58 | |||
| 59 | set_irq_chip(irq, &orion_irq_chip); | ||
| 60 | set_irq_chip_data(irq, maskaddr); | ||
| 61 | set_irq_handler(irq, handle_level_irq); | ||
| 62 | set_irq_flags(irq, IRQF_VALID); | ||
| 63 | } | ||
| 64 | } | ||
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c new file mode 100644 index 000000000000..abfda53f1800 --- /dev/null +++ b/arch/arm/plat-orion/pcie.c | |||
| @@ -0,0 +1,245 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/pcie.c | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC PCIe handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/pci.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <asm/mach/pci.h> | ||
| 15 | #include <asm/plat-orion/pcie.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * PCIe unit register offsets. | ||
| 19 | */ | ||
| 20 | #define PCIE_DEV_ID_OFF 0x0000 | ||
| 21 | #define PCIE_CMD_OFF 0x0004 | ||
| 22 | #define PCIE_DEV_REV_OFF 0x0008 | ||
| 23 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | ||
| 24 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | ||
| 25 | #define PCIE_HEADER_LOG_4_OFF 0x0128 | ||
| 26 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4)) | ||
| 27 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | ||
| 28 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | ||
| 29 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | ||
| 30 | #define PCIE_WIN5_CTRL_OFF 0x1880 | ||
| 31 | #define PCIE_WIN5_BASE_OFF 0x1884 | ||
| 32 | #define PCIE_WIN5_REMAP_OFF 0x188c | ||
| 33 | #define PCIE_CONF_ADDR_OFF 0x18f8 | ||
| 34 | #define PCIE_CONF_ADDR_EN 0x80000000 | ||
| 35 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | ||
| 36 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | ||
| 37 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | ||
| 38 | #define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) | ||
| 39 | #define PCIE_CONF_DATA_OFF 0x18fc | ||
| 40 | #define PCIE_MASK_OFF 0x1910 | ||
| 41 | #define PCIE_CTRL_OFF 0x1a00 | ||
| 42 | #define PCIE_STAT_OFF 0x1a04 | ||
| 43 | #define PCIE_STAT_DEV_OFFS 20 | ||
| 44 | #define PCIE_STAT_DEV_MASK 0x1f | ||
| 45 | #define PCIE_STAT_BUS_OFFS 8 | ||
| 46 | #define PCIE_STAT_BUS_MASK 0xff | ||
| 47 | #define PCIE_STAT_LINK_DOWN 1 | ||
| 48 | |||
| 49 | |||
| 50 | u32 __init orion_pcie_dev_id(void __iomem *base) | ||
| 51 | { | ||
| 52 | return readl(base + PCIE_DEV_ID_OFF) >> 16; | ||
| 53 | } | ||
| 54 | |||
| 55 | u32 __init orion_pcie_rev(void __iomem *base) | ||
| 56 | { | ||
| 57 | return readl(base + PCIE_DEV_REV_OFF) & 0xff; | ||
| 58 | } | ||
| 59 | |||
| 60 | int orion_pcie_link_up(void __iomem *base) | ||
| 61 | { | ||
| 62 | return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); | ||
| 63 | } | ||
| 64 | |||
| 65 | int orion_pcie_get_local_bus_nr(void __iomem *base) | ||
| 66 | { | ||
| 67 | u32 stat = readl(base + PCIE_STAT_OFF); | ||
| 68 | |||
| 69 | return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK; | ||
| 70 | } | ||
| 71 | |||
| 72 | void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) | ||
| 73 | { | ||
| 74 | u32 stat; | ||
| 75 | |||
| 76 | stat = readl(base + PCIE_STAT_OFF); | ||
| 77 | stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS); | ||
| 78 | stat |= nr << PCIE_STAT_BUS_OFFS; | ||
| 79 | writel(stat, base + PCIE_STAT_OFF); | ||
| 80 | } | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Setup PCIE BARs and Address Decode Wins: | ||
| 84 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | ||
| 85 | * WIN[0-3] -> DRAM bank[0-3] | ||
| 86 | */ | ||
| 87 | static void __init orion_pcie_setup_wins(void __iomem *base, | ||
| 88 | struct mbus_dram_target_info *dram) | ||
| 89 | { | ||
| 90 | u32 size; | ||
| 91 | int i; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * First, disable and clear BARs and windows. | ||
| 95 | */ | ||
| 96 | for (i = 1; i <= 2; i++) { | ||
| 97 | writel(0, base + PCIE_BAR_CTRL_OFF(i)); | ||
| 98 | writel(0, base + PCIE_BAR_LO_OFF(i)); | ||
| 99 | writel(0, base + PCIE_BAR_HI_OFF(i)); | ||
| 100 | } | ||
| 101 | |||
| 102 | for (i = 0; i < 5; i++) { | ||
| 103 | writel(0, base + PCIE_WIN04_CTRL_OFF(i)); | ||
| 104 | writel(0, base + PCIE_WIN04_BASE_OFF(i)); | ||
| 105 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | ||
| 106 | } | ||
| 107 | |||
| 108 | writel(0, base + PCIE_WIN5_CTRL_OFF); | ||
| 109 | writel(0, base + PCIE_WIN5_BASE_OFF); | ||
| 110 | writel(0, base + PCIE_WIN5_REMAP_OFF); | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Setup windows for DDR banks. Count total DDR size on the fly. | ||
| 114 | */ | ||
| 115 | size = 0; | ||
| 116 | for (i = 0; i < dram->num_cs; i++) { | ||
| 117 | struct mbus_dram_window *cs = dram->cs + i; | ||
| 118 | |||
| 119 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); | ||
| 120 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | ||
| 121 | writel(((cs->size - 1) & 0xffff0000) | | ||
| 122 | (cs->mbus_attr << 8) | | ||
| 123 | (dram->mbus_dram_target_id << 4) | 1, | ||
| 124 | base + PCIE_WIN04_CTRL_OFF(i)); | ||
| 125 | |||
| 126 | size += cs->size; | ||
| 127 | } | ||
| 128 | |||
| 129 | /* | ||
| 130 | * Setup BAR[1] to all DRAM banks. | ||
| 131 | */ | ||
| 132 | writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); | ||
| 133 | writel(0, base + PCIE_BAR_HI_OFF(1)); | ||
| 134 | writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); | ||
| 135 | } | ||
| 136 | |||
| 137 | void __init orion_pcie_setup(void __iomem *base, | ||
| 138 | struct mbus_dram_target_info *dram) | ||
| 139 | { | ||
| 140 | u16 cmd; | ||
| 141 | u32 mask; | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Point PCIe unit MBUS decode windows to DRAM space. | ||
| 145 | */ | ||
| 146 | orion_pcie_setup_wins(base, dram); | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Master + slave enable. | ||
| 150 | */ | ||
| 151 | cmd = readw(base + PCIE_CMD_OFF); | ||
| 152 | cmd |= PCI_COMMAND_IO; | ||
| 153 | cmd |= PCI_COMMAND_MEMORY; | ||
| 154 | cmd |= PCI_COMMAND_MASTER; | ||
| 155 | writew(cmd, base + PCIE_CMD_OFF); | ||
| 156 | |||
| 157 | /* | ||
| 158 | * Enable interrupt lines A-D. | ||
| 159 | */ | ||
| 160 | mask = readl(base + PCIE_MASK_OFF); | ||
| 161 | mask |= 0x0f000000; | ||
| 162 | writel(mask, base + PCIE_MASK_OFF); | ||
| 163 | } | ||
| 164 | |||
| 165 | int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, | ||
| 166 | u32 devfn, int where, int size, u32 *val) | ||
| 167 | { | ||
| 168 | writel(PCIE_CONF_BUS(bus->number) | | ||
| 169 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 170 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 171 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | ||
| 172 | base + PCIE_CONF_ADDR_OFF); | ||
| 173 | |||
| 174 | *val = readl(base + PCIE_CONF_DATA_OFF); | ||
| 175 | |||
| 176 | if (size == 1) | ||
| 177 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 178 | else if (size == 2) | ||
| 179 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 180 | |||
| 181 | return PCIBIOS_SUCCESSFUL; | ||
| 182 | } | ||
| 183 | |||
| 184 | int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, | ||
| 185 | u32 devfn, int where, int size, u32 *val) | ||
| 186 | { | ||
| 187 | writel(PCIE_CONF_BUS(bus->number) | | ||
| 188 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 189 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 190 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | ||
| 191 | base + PCIE_CONF_ADDR_OFF); | ||
| 192 | |||
| 193 | *val = readl(base + PCIE_CONF_DATA_OFF); | ||
| 194 | |||
| 195 | if (bus->number != orion_pcie_get_local_bus_nr(base) || | ||
| 196 | PCI_FUNC(devfn) != 0) | ||
| 197 | *val = readl(base + PCIE_HEADER_LOG_4_OFF); | ||
| 198 | |||
| 199 | if (size == 1) | ||
| 200 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 201 | else if (size == 2) | ||
| 202 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 203 | |||
| 204 | return PCIBIOS_SUCCESSFUL; | ||
| 205 | } | ||
| 206 | |||
| 207 | int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, | ||
| 208 | u32 devfn, int where, int size, u32 *val) | ||
| 209 | { | ||
| 210 | *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | | ||
| 211 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 212 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 213 | PCIE_CONF_REG(where))); | ||
| 214 | |||
| 215 | if (size == 1) | ||
| 216 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 217 | else if (size == 2) | ||
| 218 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 219 | |||
| 220 | return PCIBIOS_SUCCESSFUL; | ||
| 221 | } | ||
| 222 | |||
| 223 | int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, | ||
| 224 | u32 devfn, int where, int size, u32 val) | ||
| 225 | { | ||
| 226 | int ret = PCIBIOS_SUCCESSFUL; | ||
| 227 | |||
| 228 | writel(PCIE_CONF_BUS(bus->number) | | ||
| 229 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 230 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 231 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | ||
| 232 | base + PCIE_CONF_ADDR_OFF); | ||
| 233 | |||
| 234 | if (size == 4) { | ||
| 235 | writel(val, base + PCIE_CONF_DATA_OFF); | ||
| 236 | } else if (size == 2) { | ||
| 237 | writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); | ||
| 238 | } else if (size == 1) { | ||
| 239 | writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); | ||
| 240 | } else { | ||
| 241 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 242 | } | ||
| 243 | |||
| 244 | return ret; | ||
| 245 | } | ||
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c new file mode 100644 index 000000000000..28b5285446e8 --- /dev/null +++ b/arch/arm/plat-orion/time.c | |||
| @@ -0,0 +1,203 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/time.c | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC timer handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * Timer 0 is used as free-running clocksource, while timer 1 is | ||
| 11 | * used as clock_event_device. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/clockchips.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/irq.h> | ||
| 18 | #include <asm/mach/time.h> | ||
| 19 | #include <asm/arch/hardware.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Number of timer ticks per jiffy. | ||
| 23 | */ | ||
| 24 | static u32 ticks_per_jiffy; | ||
| 25 | |||
| 26 | |||
| 27 | /* | ||
| 28 | * Timer block registers. | ||
| 29 | */ | ||
| 30 | #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) | ||
| 31 | #define TIMER0_EN 0x0001 | ||
| 32 | #define TIMER0_RELOAD_EN 0x0002 | ||
| 33 | #define TIMER1_EN 0x0004 | ||
| 34 | #define TIMER1_RELOAD_EN 0x0008 | ||
| 35 | #define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) | ||
| 36 | #define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) | ||
| 37 | #define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) | ||
| 38 | #define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | * Clocksource handling. | ||
| 43 | */ | ||
| 44 | static cycle_t orion_clksrc_read(void) | ||
| 45 | { | ||
| 46 | return 0xffffffff - readl(TIMER0_VAL); | ||
| 47 | } | ||
| 48 | |||
| 49 | static struct clocksource orion_clksrc = { | ||
| 50 | .name = "orion_clocksource", | ||
| 51 | .shift = 20, | ||
| 52 | .rating = 300, | ||
| 53 | .read = orion_clksrc_read, | ||
| 54 | .mask = CLOCKSOURCE_MASK(32), | ||
| 55 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 56 | }; | ||
| 57 | |||
| 58 | |||
| 59 | |||
| 60 | /* | ||
| 61 | * Clockevent handling. | ||
| 62 | */ | ||
| 63 | static int | ||
| 64 | orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) | ||
| 65 | { | ||
| 66 | unsigned long flags; | ||
| 67 | u32 u; | ||
| 68 | |||
| 69 | if (delta == 0) | ||
| 70 | return -ETIME; | ||
| 71 | |||
| 72 | local_irq_save(flags); | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Clear and enable clockevent timer interrupt. | ||
| 76 | */ | ||
| 77 | writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); | ||
| 78 | |||
| 79 | u = readl(BRIDGE_MASK); | ||
| 80 | u |= BRIDGE_INT_TIMER1; | ||
| 81 | writel(u, BRIDGE_MASK); | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Setup new clockevent timer value. | ||
| 85 | */ | ||
| 86 | writel(delta, TIMER1_VAL); | ||
| 87 | |||
| 88 | /* | ||
| 89 | * Enable the timer. | ||
| 90 | */ | ||
| 91 | u = readl(TIMER_CTRL); | ||
| 92 | u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; | ||
| 93 | writel(u, TIMER_CTRL); | ||
| 94 | |||
| 95 | local_irq_restore(flags); | ||
| 96 | |||
| 97 | return 0; | ||
| 98 | } | ||
| 99 | |||
| 100 | static void | ||
| 101 | orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | ||
| 102 | { | ||
| 103 | unsigned long flags; | ||
| 104 | u32 u; | ||
| 105 | |||
| 106 | local_irq_save(flags); | ||
| 107 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | ||
| 108 | /* | ||
| 109 | * Setup timer to fire at 1/HZ intervals. | ||
| 110 | */ | ||
| 111 | writel(ticks_per_jiffy - 1, TIMER1_RELOAD); | ||
| 112 | writel(ticks_per_jiffy - 1, TIMER1_VAL); | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Enable timer interrupt. | ||
| 116 | */ | ||
| 117 | u = readl(BRIDGE_MASK); | ||
| 118 | writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); | ||
| 119 | |||
| 120 | /* | ||
| 121 | * Enable timer. | ||
| 122 | */ | ||
| 123 | u = readl(TIMER_CTRL); | ||
| 124 | writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); | ||
| 125 | } else { | ||
| 126 | /* | ||
| 127 | * Disable timer. | ||
| 128 | */ | ||
| 129 | u = readl(TIMER_CTRL); | ||
| 130 | writel(u & ~TIMER1_EN, TIMER_CTRL); | ||
| 131 | |||
| 132 | /* | ||
| 133 | * Disable timer interrupt. | ||
| 134 | */ | ||
| 135 | u = readl(BRIDGE_MASK); | ||
| 136 | writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); | ||
| 137 | |||
| 138 | /* | ||
| 139 | * ACK pending timer interrupt. | ||
| 140 | */ | ||
| 141 | writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); | ||
| 142 | |||
| 143 | } | ||
| 144 | local_irq_restore(flags); | ||
| 145 | } | ||
| 146 | |||
| 147 | static struct clock_event_device orion_clkevt = { | ||
| 148 | .name = "orion_tick", | ||
| 149 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | ||
| 150 | .shift = 32, | ||
| 151 | .rating = 300, | ||
| 152 | .cpumask = CPU_MASK_CPU0, | ||
| 153 | .set_next_event = orion_clkevt_next_event, | ||
| 154 | .set_mode = orion_clkevt_mode, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) | ||
| 158 | { | ||
| 159 | /* | ||
| 160 | * ACK timer interrupt and call event handler. | ||
| 161 | */ | ||
| 162 | writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); | ||
| 163 | orion_clkevt.event_handler(&orion_clkevt); | ||
| 164 | |||
| 165 | return IRQ_HANDLED; | ||
| 166 | } | ||
| 167 | |||
| 168 | static struct irqaction orion_timer_irq = { | ||
| 169 | .name = "orion_tick", | ||
| 170 | .flags = IRQF_DISABLED | IRQF_TIMER, | ||
| 171 | .handler = orion_timer_interrupt | ||
| 172 | }; | ||
| 173 | |||
| 174 | void __init orion_time_init(unsigned int irq, unsigned int tclk) | ||
| 175 | { | ||
| 176 | u32 u; | ||
| 177 | |||
| 178 | ticks_per_jiffy = (tclk + HZ/2) / HZ; | ||
| 179 | |||
| 180 | |||
| 181 | /* | ||
| 182 | * Setup free-running clocksource timer (interrupts | ||
| 183 | * disabled.) | ||
| 184 | */ | ||
| 185 | writel(0xffffffff, TIMER0_VAL); | ||
| 186 | writel(0xffffffff, TIMER0_RELOAD); | ||
| 187 | u = readl(BRIDGE_MASK); | ||
| 188 | writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); | ||
| 189 | u = readl(TIMER_CTRL); | ||
| 190 | writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); | ||
| 191 | orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); | ||
| 192 | clocksource_register(&orion_clksrc); | ||
| 193 | |||
| 194 | |||
| 195 | /* | ||
| 196 | * Setup clockevent timer (interrupt-driven.) | ||
| 197 | */ | ||
| 198 | setup_irq(irq, &orion_timer_irq); | ||
| 199 | orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); | ||
| 200 | orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); | ||
| 201 | orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); | ||
| 202 | clockevents_register_device(&orion_clkevt); | ||
| 203 | } | ||
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index 99a44746f8f2..d84167fb33b1 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
| @@ -332,6 +332,58 @@ static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) | |||
| 332 | return 0; | 332 | return 0; |
| 333 | } | 333 | } |
| 334 | 334 | ||
| 335 | static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) | ||
| 336 | { | ||
| 337 | unsigned long div; | ||
| 338 | |||
| 339 | if ((rate == 0) || !clk->parent) | ||
| 340 | return 0; | ||
| 341 | |||
| 342 | div = clk_get_rate(clk->parent) / rate; | ||
| 343 | if (div < 2) | ||
| 344 | div = 2; | ||
| 345 | else if (div > 16) | ||
| 346 | div = 16; | ||
| 347 | |||
| 348 | return div; | ||
| 349 | } | ||
| 350 | |||
| 351 | static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, | ||
| 352 | unsigned long rate) | ||
| 353 | { | ||
| 354 | unsigned long div = s3c24xx_calc_div(clk, rate); | ||
| 355 | |||
| 356 | if (div == 0) | ||
| 357 | return 0; | ||
| 358 | |||
| 359 | return clk_get_rate(clk->parent) / div; | ||
| 360 | } | ||
| 361 | |||
| 362 | static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) | ||
| 363 | { | ||
| 364 | unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); | ||
| 365 | |||
| 366 | if (div == 0) | ||
| 367 | return -EINVAL; | ||
| 368 | |||
| 369 | if (clk == &s3c24xx_dclk0) { | ||
| 370 | mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | | ||
| 371 | S3C2410_DCLKCON_DCLK0_CMP_MASK; | ||
| 372 | data = S3C2410_DCLKCON_DCLK0_DIV(div) | | ||
| 373 | S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); | ||
| 374 | } else if (clk == &s3c24xx_dclk1) { | ||
| 375 | mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | | ||
| 376 | S3C2410_DCLKCON_DCLK1_CMP_MASK; | ||
| 377 | data = S3C2410_DCLKCON_DCLK1_DIV(div) | | ||
| 378 | S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); | ||
| 379 | } else | ||
| 380 | return -EINVAL; | ||
| 381 | |||
| 382 | clk->rate = clk_get_rate(clk->parent) / div; | ||
| 383 | __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), | ||
| 384 | S3C24XX_DCLKCON); | ||
| 385 | return clk->rate; | ||
| 386 | } | ||
| 335 | 387 | ||
| 336 | static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) | 388 | static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) |
| 337 | { | 389 | { |
| @@ -378,6 +430,8 @@ struct clk s3c24xx_dclk0 = { | |||
| 378 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | 430 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, |
| 379 | .enable = s3c24xx_dclk_enable, | 431 | .enable = s3c24xx_dclk_enable, |
| 380 | .set_parent = s3c24xx_dclk_setparent, | 432 | .set_parent = s3c24xx_dclk_setparent, |
| 433 | .set_rate = s3c24xx_set_dclk_rate, | ||
| 434 | .round_rate = s3c24xx_round_dclk_rate, | ||
| 381 | }; | 435 | }; |
| 382 | 436 | ||
| 383 | struct clk s3c24xx_dclk1 = { | 437 | struct clk s3c24xx_dclk1 = { |
| @@ -386,6 +440,8 @@ struct clk s3c24xx_dclk1 = { | |||
| 386 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | 440 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, |
| 387 | .enable = s3c24xx_dclk_enable, | 441 | .enable = s3c24xx_dclk_enable, |
| 388 | .set_parent = s3c24xx_dclk_setparent, | 442 | .set_parent = s3c24xx_dclk_setparent, |
| 443 | .set_rate = s3c24xx_set_dclk_rate, | ||
| 444 | .round_rate = s3c24xx_round_dclk_rate, | ||
| 389 | }; | 445 | }; |
| 390 | 446 | ||
| 391 | struct clk s3c24xx_clkout0 = { | 447 | struct clk s3c24xx_clkout0 = { |
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index f513ab083b8f..f5699cadb0c3 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
| @@ -28,15 +28,19 @@ | |||
| 28 | #include <linux/ioport.h> | 28 | #include <linux/ioport.h> |
| 29 | #include <linux/serial_core.h> | 29 | #include <linux/serial_core.h> |
| 30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
| 31 | #include <linux/delay.h> | ||
| 31 | 32 | ||
| 32 | #include <asm/hardware.h> | 33 | #include <asm/hardware.h> |
| 33 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
| 34 | #include <asm/io.h> | 35 | #include <asm/io.h> |
| 35 | #include <asm/delay.h> | 36 | #include <asm/delay.h> |
| 37 | #include <asm/cacheflush.h> | ||
| 36 | 38 | ||
| 37 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| 38 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
| 39 | 41 | ||
| 42 | #include <asm/arch/system-reset.h> | ||
| 43 | |||
| 40 | #include <asm/arch/regs-gpio.h> | 44 | #include <asm/arch/regs-gpio.h> |
| 41 | #include <asm/plat-s3c/regs-serial.h> | 45 | #include <asm/plat-s3c/regs-serial.h> |
| 42 | 46 | ||
| @@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void) | |||
| 203 | #endif | 207 | #endif |
| 204 | } | 208 | } |
| 205 | 209 | ||
| 210 | /* Hook for arm_pm_restart to ensure we execute the reset code | ||
| 211 | * with the caches enabled. It seems at least the S3C2440 has a problem | ||
| 212 | * resetting if there is bus activity interrupted by the reset. | ||
| 213 | */ | ||
| 214 | static void s3c24xx_pm_restart(char mode) | ||
| 215 | { | ||
| 216 | if (mode != 's') { | ||
| 217 | unsigned long flags; | ||
| 218 | |||
| 219 | local_irq_save(flags); | ||
| 220 | __cpuc_flush_kern_all(); | ||
| 221 | __cpuc_flush_user_all(); | ||
| 222 | |||
| 223 | arch_reset(mode); | ||
| 224 | local_irq_restore(flags); | ||
| 225 | } | ||
| 226 | |||
| 227 | /* fallback, or unhandled */ | ||
| 228 | arm_machine_restart(mode); | ||
| 229 | } | ||
| 230 | |||
| 206 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | 231 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
| 207 | { | 232 | { |
| 208 | unsigned long idcode = 0x0; | 233 | unsigned long idcode = 0x0; |
| @@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | |||
| 230 | panic("Unsupported S3C24XX CPU"); | 255 | panic("Unsupported S3C24XX CPU"); |
| 231 | } | 256 | } |
| 232 | 257 | ||
| 258 | arm_pm_restart = s3c24xx_pm_restart; | ||
| 259 | |||
| 233 | (cpu->map_io)(mach_desc, size); | 260 | (cpu->map_io)(mach_desc, size); |
| 234 | } | 261 | } |
| 235 | 262 | ||
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 7ed58c0c24c2..207a8b5a0c4a 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | # | 12 | # |
| 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new | 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new |
| 14 | # | 14 | # |
| 15 | # Last update: Sat Jan 26 14:45:34 2008 | 15 | # Last update: Sat Apr 19 11:23:38 2008 |
| 16 | # | 16 | # |
| 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number | 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number |
| 18 | # | 18 | # |
| @@ -381,13 +381,13 @@ ks8695p ARCH_KS8695P KS8695P 363 | |||
| 381 | se4000 ARCH_SE4000 SE4000 364 | 381 | se4000 ARCH_SE4000 SE4000 364 |
| 382 | quadriceps ARCH_QUADRICEPS QUADRICEPS 365 | 382 | quadriceps ARCH_QUADRICEPS QUADRICEPS 365 |
| 383 | bronco ARCH_BRONCO BRONCO 366 | 383 | bronco ARCH_BRONCO BRONCO 366 |
| 384 | esl_wireless_tab ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET 367 | 384 | esl_wireless_tab ARCH_ESL_WIRELESS_TAB ESL_WIRELESS_TAB 367 |
| 385 | esl_sofcomp ARCH_ESL_SOFCOMP ESL_SOFCOMP 368 | 385 | esl_sofcomp ARCH_ESL_SOFCOMP ESL_SOFCOMP 368 |
| 386 | s5c7375 ARCH_S5C7375 S5C7375 369 | 386 | s5c7375 ARCH_S5C7375 S5C7375 369 |
| 387 | spearhead ARCH_SPEARHEAD SPEARHEAD 370 | 387 | spearhead ARCH_SPEARHEAD SPEARHEAD 370 |
| 388 | pantera ARCH_PANTERA PANTERA 371 | 388 | pantera ARCH_PANTERA PANTERA 371 |
| 389 | prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372 | 389 | prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372 |
| 390 | gumstix ARCH_GUMSTIK GUMSTIK 373 | 390 | gumstix ARCH_GUMSTIX GUMSTIX 373 |
| 391 | rcube ARCH_RCUBE RCUBE 374 | 391 | rcube ARCH_RCUBE RCUBE 374 |
| 392 | rea_olv ARCH_REA_OLV REA_OLV 375 | 392 | rea_olv ARCH_REA_OLV REA_OLV 375 |
| 393 | pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376 | 393 | pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376 |
| @@ -1463,7 +1463,7 @@ artemis MACH_ARTEMIS ARTEMIS 1462 | |||
| 1463 | htctitan MACH_HTCTITAN HTCTITAN 1463 | 1463 | htctitan MACH_HTCTITAN HTCTITAN 1463 |
| 1464 | qranium MACH_QRANIUM QRANIUM 1464 | 1464 | qranium MACH_QRANIUM QRANIUM 1464 |
| 1465 | adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465 | 1465 | adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465 |
| 1466 | adx_medinet MACH_ADX_MEDINET ADX_MEDINET 1466 | 1466 | adx_medcom MACH_ADX_MEDINET ADX_MEDINET 1466 |
| 1467 | bboard MACH_BBOARD BBOARD 1467 | 1467 | bboard MACH_BBOARD BBOARD 1467 |
| 1468 | cambria MACH_CAMBRIA CAMBRIA 1468 | 1468 | cambria MACH_CAMBRIA CAMBRIA 1468 |
| 1469 | mt7xxx MACH_MT7XXX MT7XXX 1469 | 1469 | mt7xxx MACH_MT7XXX MT7XXX 1469 |
| @@ -1611,3 +1611,112 @@ kb9263 MACH_KB9263 KB9263 1612 | |||
| 1611 | mt7108 MACH_MT7108 MT7108 1613 | 1611 | mt7108 MACH_MT7108 MT7108 1613 |
| 1612 | smtr2440 MACH_SMTR2440 SMTR2440 1614 | 1612 | smtr2440 MACH_SMTR2440 SMTR2440 1614 |
| 1613 | manao MACH_MANAO MANAO 1615 | 1613 | manao MACH_MANAO MANAO 1615 |
| 1614 | cm_x300 MACH_CM_X300 CM_X300 1616 | ||
| 1615 | gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617 | ||
| 1616 | lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618 | ||
| 1617 | arma37 MACH_ARMA37 ARMA37 1619 | ||
| 1618 | mendel MACH_MENDEL MENDEL 1620 | ||
| 1619 | pelco_iliad MACH_PELCO_ILIAD PELCO_ILIAD 1621 | ||
| 1620 | unit2p MACH_UNIT2P UNIT2P 1622 | ||
| 1621 | inc20otter MACH_INC20OTTER INC20OTTER 1623 | ||
| 1622 | at91sam9g20ek MACH_AT91SAM9G20EK AT91SAM9G20EK 1624 | ||
| 1623 | sc_ge2 MACH_STORCENTER STORCENTER 1625 | ||
| 1624 | smdk6410 MACH_SMDK6410 SMDK6410 1626 | ||
| 1625 | u300 MACH_U300 U300 1627 | ||
| 1626 | u500 MACH_U500 U500 1628 | ||
| 1627 | ds9260 MACH_DS9260 DS9260 1629 | ||
| 1628 | riverrock MACH_RIVERROCK RIVERROCK 1630 | ||
| 1629 | scibath MACH_SCIBATH SCIBATH 1631 | ||
| 1630 | at91sam7se MACH_AT91SAM7SE512EK AT91SAM7SE512EK 1632 | ||
| 1631 | wrt350n_v2 MACH_WRT350N_V2 WRT350N_V2 1633 | ||
| 1632 | multimedia MACH_MULTIMEDIA MULTIMEDIA 1634 | ||
| 1633 | marvin MACH_MARVIN MARVIN 1635 | ||
| 1634 | x500 MACH_X500 X500 1636 | ||
| 1635 | awlug4lcu MACH_AWLUG4LCU AWLUG4LCU 1637 | ||
| 1636 | palermoc MACH_PALERMOC PALERMOC 1638 | ||
| 1637 | omap_ldp MACH_OMAP_LDP OMAP_LDP 1639 | ||
| 1638 | ip500 MACH_IP500 IP500 1640 | ||
| 1639 | mx35ads MACH_MACH_MX35ADS MACH_MX35ADS 1641 | ||
| 1640 | ase2 MACH_ASE2 ASE2 1642 | ||
| 1641 | mx35evb MACH_MX35EVB MX35EVB 1643 | ||
| 1642 | aml_m8050 MACH_AML_M8050 AML_M8050 1644 | ||
| 1643 | mx35_3ds MACH_MX35_3DS MX35_3DS 1645 | ||
| 1644 | mars MACH_MARS MARS 1646 | ||
| 1645 | ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647 | ||
| 1646 | badger MACH_BADGER BADGER 1648 | ||
| 1647 | trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649 | ||
| 1648 | trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650 | ||
| 1649 | marlin MACH_MARLIN MARLIN 1651 | ||
| 1650 | ts7800 MACH_TS7800 TS7800 1652 | ||
| 1651 | hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653 | ||
| 1652 | at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654 | ||
| 1653 | ne1board MACH_NE1BOARD NE1BOARD 1655 | ||
| 1654 | zante MACH_ZANTE ZANTE 1656 | ||
| 1655 | sffsdr MACH_SFFSDR SFFSDR 1657 | ||
| 1656 | tw2662 MACH_TW2662 TW2662 1658 | ||
| 1657 | vf10xx MACH_VF10XX VF10XX 1659 | ||
| 1658 | zoran43xx MACH_ZORAN43XX ZORAN43XX 1660 | ||
| 1659 | sonix926 MACH_SONIX926 SONIX926 1661 | ||
| 1660 | celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662 | ||
| 1661 | cc9m2443 MACH_CC9M2443 CC9M2443 1663 | ||
| 1662 | tw5334 MACH_TW5334 TW5334 1664 | ||
| 1663 | omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665 | ||
| 1664 | nal_hlite MACH_NAL_HLITE NAL_HLITE 1666 | ||
| 1665 | htcvogue MACH_HTCVOGUE HTCVOGUE 1667 | ||
| 1666 | smartweb MACH_SMARTWEB SMARTWEB 1668 | ||
| 1667 | mv86xx MACH_MV86XX MV86XX 1669 | ||
| 1668 | mv87xx MACH_MV87XX MV87XX 1670 | ||
| 1669 | songyoungho MACH_SONGYOUNGHO SONGYOUNGHO 1671 | ||
| 1670 | younghotema MACH_YOUNGHOTEMA YOUNGHOTEMA 1672 | ||
| 1671 | pcm037 MACH_PCM037 PCM037 1673 | ||
| 1672 | mmvp MACH_MMVP MMVP 1674 | ||
| 1673 | mmap MACH_MMAP MMAP 1675 | ||
| 1674 | ptid2410 MACH_PTID2410 PTID2410 1676 | ||
| 1675 | james_926 MACH_JAMES_926 JAMES_926 1677 | ||
| 1676 | fm6000 MACH_FM6000 FM6000 1678 | ||
| 1677 | db88f6281_bp MACH_DB88F6281_BP DB88F6281_BP 1680 | ||
| 1678 | rd88f6192_nas MACH_RD88F6192_NAS RD88F6192_NAS 1681 | ||
| 1679 | rd88f6281 MACH_RD88F6281 RD88F6281 1682 | ||
| 1680 | db78x00_bp MACH_DB78X00_BP DB78X00_BP 1683 | ||
| 1681 | smdk2416 MACH_SMDK2416 SMDK2416 1685 | ||
| 1682 | oce_spider_si MACH_OCE_SPIDER_SI OCE_SPIDER_SI 1686 | ||
| 1683 | oce_spider_sk MACH_OCE_SPIDER_SK OCE_SPIDER_SK 1687 | ||
| 1684 | rovern6 MACH_ROVERN6 ROVERN6 1688 | ||
| 1685 | pelco_evolution MACH_PELCO_EVOLUTION PELCO_EVOLUTION 1689 | ||
| 1686 | wbd111 MACH_WBD111 WBD111 1690 | ||
| 1687 | elaracpe MACH_ELARACPE ELARACPE 1691 | ||
| 1688 | mabv3 MACH_MABV3 MABV3 1692 | ||
| 1689 | mv2120 MACH_MV2120 MV2120 1693 | ||
| 1690 | csb737 MACH_CSB737 CSB737 1695 | ||
| 1691 | mx51_3ds MACH_MX51_3DS MX51_3DS 1696 | ||
| 1692 | g900 MACH_G900 G900 1697 | ||
| 1693 | apf27 MACH_APF27 APF27 1698 | ||
| 1694 | ggus2000 MACH_GGUS2000 GGUS2000 1699 | ||
| 1695 | omap_2430_mimic MACH_OMAP_2430_MIMIC OMAP_2430_MIMIC 1700 | ||
| 1696 | imx27lite MACH_IMX27LITE IMX27LITE 1701 | ||
| 1697 | almex MACH_ALMEX ALMEX 1702 | ||
| 1698 | control MACH_CONTROL CONTROL 1703 | ||
| 1699 | mba2410 MACH_MBA2410 MBA2410 1704 | ||
| 1700 | volcano MACH_VOLCANO VOLCANO 1705 | ||
| 1701 | zenith MACH_ZENITH ZENITH 1706 | ||
| 1702 | muchip MACH_MUCHIP MUCHIP 1707 | ||
| 1703 | magellan MACH_MAGELLAN MAGELLAN 1708 | ||
| 1704 | usb_a9260 MACH_USB_A9260 USB_A9260 1709 | ||
| 1705 | usb_a9263 MACH_USB_A9263 USB_A9263 1710 | ||
| 1706 | qil_a9260 MACH_QIL_A9260 QIL_A9260 1711 | ||
| 1707 | cme9210 MACH_CME9210 CME9210 1712 | ||
| 1708 | hczh4 MACH_HCZH4 HCZH4 1713 | ||
| 1709 | spearbasic MACH_SPEARBASIC SPEARBASIC 1714 | ||
| 1710 | dep2440 MACH_DEP2440 DEP2440 1715 | ||
| 1711 | hdl_gxr MACH_HDL_GXR HDL_GXR 1716 | ||
| 1712 | hdl_gt MACH_HDL_GT HDL_GT 1717 | ||
| 1713 | hdl_4g MACH_HDL_4G HDL_4G 1718 | ||
| 1714 | s3c6000 MACH_S3C6000 S3C6000 1719 | ||
| 1715 | mmsp2_mdk MACH_MMSP2_MDK MMSP2_MDK 1720 | ||
| 1716 | mpx220 MACH_MPX220 MPX220 1721 | ||
| 1717 | kzm_arm11_01 MACH_KZM_ARM11_01 KZM_ARM11_01 1722 | ||
| 1718 | htc_polaris MACH_HTC_POLARIS HTC_POLARIS 1723 | ||
| 1719 | htc_kaiser MACH_HTC_KAISER HTC_KAISER 1724 | ||
| 1720 | lg_ks20 MACH_LG_KS20 LG_KS20 1725 | ||
| 1721 | hhgps MACH_HHGPS HHGPS 1726 | ||
| 1722 | nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727 | ||
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 6ebebde8454a..83584b6e1ba5 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
| @@ -74,6 +74,7 @@ | |||
| 74 | #include <linux/device.h> | 74 | #include <linux/device.h> |
| 75 | #include <linux/platform_device.h> | 75 | #include <linux/platform_device.h> |
| 76 | #include <linux/ata_platform.h> | 76 | #include <linux/ata_platform.h> |
| 77 | #include <linux/mbus.h> | ||
| 77 | #include <scsi/scsi_host.h> | 78 | #include <scsi/scsi_host.h> |
| 78 | #include <scsi/scsi_cmnd.h> | 79 | #include <scsi/scsi_cmnd.h> |
| 79 | #include <scsi/scsi_device.h> | 80 | #include <scsi/scsi_device.h> |
| @@ -352,6 +353,9 @@ enum { | |||
| 352 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) | 353 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
| 353 | #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) | 354 | #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) |
| 354 | 355 | ||
| 356 | #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) | ||
| 357 | #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) | ||
| 358 | |||
| 355 | enum { | 359 | enum { |
| 356 | /* DMA boundary 0xffff is required by the s/g splitting | 360 | /* DMA boundary 0xffff is required by the s/g splitting |
| 357 | * we need on /length/ in mv_fill-sg(). | 361 | * we need on /length/ in mv_fill-sg(). |
| @@ -2897,6 +2901,27 @@ static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) | |||
| 2897 | return 0; | 2901 | return 0; |
| 2898 | } | 2902 | } |
| 2899 | 2903 | ||
| 2904 | static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, | ||
| 2905 | struct mbus_dram_target_info *dram) | ||
| 2906 | { | ||
| 2907 | int i; | ||
| 2908 | |||
| 2909 | for (i = 0; i < 4; i++) { | ||
| 2910 | writel(0, hpriv->base + WINDOW_CTRL(i)); | ||
| 2911 | writel(0, hpriv->base + WINDOW_BASE(i)); | ||
| 2912 | } | ||
| 2913 | |||
| 2914 | for (i = 0; i < dram->num_cs; i++) { | ||
| 2915 | struct mbus_dram_window *cs = dram->cs + i; | ||
| 2916 | |||
| 2917 | writel(((cs->size - 1) & 0xffff0000) | | ||
| 2918 | (cs->mbus_attr << 8) | | ||
| 2919 | (dram->mbus_dram_target_id << 4) | 1, | ||
| 2920 | hpriv->base + WINDOW_CTRL(i)); | ||
| 2921 | writel(cs->base, hpriv->base + WINDOW_BASE(i)); | ||
| 2922 | } | ||
| 2923 | } | ||
| 2924 | |||
| 2900 | /** | 2925 | /** |
| 2901 | * mv_platform_probe - handle a positive probe of an soc Marvell | 2926 | * mv_platform_probe - handle a positive probe of an soc Marvell |
| 2902 | * host | 2927 | * host |
| @@ -2951,6 +2976,12 @@ static int mv_platform_probe(struct platform_device *pdev) | |||
| 2951 | res->end - res->start + 1); | 2976 | res->end - res->start + 1); |
| 2952 | hpriv->base -= MV_SATAHC0_REG_BASE; | 2977 | hpriv->base -= MV_SATAHC0_REG_BASE; |
| 2953 | 2978 | ||
| 2979 | /* | ||
| 2980 | * (Re-)program MBUS remapping windows if we are asked to. | ||
| 2981 | */ | ||
| 2982 | if (mv_platform_data->dram != NULL) | ||
| 2983 | mv_conf_mbus_windows(hpriv, mv_platform_data->dram); | ||
| 2984 | |||
| 2954 | rc = mv_create_dma_pools(hpriv, &pdev->dev); | 2985 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
| 2955 | if (rc) | 2986 | if (rc) |
| 2956 | return rc; | 2987 | return rc; |
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 5fa9c3c67e0c..b04c99580d0d 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig | |||
| @@ -645,7 +645,7 @@ config I2C_PCA_ISA | |||
| 645 | 645 | ||
| 646 | config I2C_MV64XXX | 646 | config I2C_MV64XXX |
| 647 | tristate "Marvell mv64xxx I2C Controller" | 647 | tristate "Marvell mv64xxx I2C Controller" |
| 648 | depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL | 648 | depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL |
| 649 | help | 649 | help |
| 650 | If you say yes to this option, support will be included for the | 650 | If you say yes to this option, support will be included for the |
| 651 | built-in I2C interface on the Marvell 64xxx line of host bridges. | 651 | built-in I2C interface on the Marvell 64xxx line of host bridges. |
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index 2d2087ad708f..6fd2d6a84eff 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | #include <asm/io.h> | 39 | #include <asm/io.h> |
| 40 | #include <asm/arch/i2c.h> | 40 | #include <asm/arch/i2c.h> |
| 41 | #include <asm/arch/pxa-regs.h> | 41 | #include <asm/arch/pxa-regs.h> |
| 42 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 42 | 43 | ||
| 43 | struct pxa_i2c { | 44 | struct pxa_i2c { |
| 44 | spinlock_t lock; | 45 | spinlock_t lock; |
diff --git a/drivers/input/keyboard/corgikbd.c b/drivers/input/keyboard/corgikbd.c index 790fed368aae..5d6cc7f1dc94 100644 --- a/drivers/input/keyboard/corgikbd.c +++ b/drivers/input/keyboard/corgikbd.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <asm/arch/corgi.h> | 23 | #include <asm/arch/corgi.h> |
| 24 | #include <asm/arch/hardware.h> | 24 | #include <asm/arch/hardware.h> |
| 25 | #include <asm/arch/pxa-regs.h> | 25 | #include <asm/arch/pxa-regs.h> |
| 26 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 26 | #include <asm/hardware/scoop.h> | 27 | #include <asm/hardware/scoop.h> |
| 27 | 28 | ||
| 28 | #define KB_ROWS 8 | 29 | #define KB_ROWS 8 |
diff --git a/drivers/input/keyboard/spitzkbd.c b/drivers/input/keyboard/spitzkbd.c index 1d59a2dc3c17..0be74bfc58fe 100644 --- a/drivers/input/keyboard/spitzkbd.c +++ b/drivers/input/keyboard/spitzkbd.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <asm/arch/spitz.h> | 23 | #include <asm/arch/spitz.h> |
| 24 | #include <asm/arch/hardware.h> | 24 | #include <asm/arch/hardware.h> |
| 25 | #include <asm/arch/pxa-regs.h> | 25 | #include <asm/arch/pxa-regs.h> |
| 26 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 26 | 27 | ||
| 27 | #define KB_ROWS 7 | 28 | #define KB_ROWS 7 |
| 28 | #define KB_COLS 11 | 29 | #define KB_COLS 11 |
diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c index 99d92f5c93d6..a22576779acd 100644 --- a/drivers/input/touchscreen/corgi_ts.c +++ b/drivers/input/touchscreen/corgi_ts.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <asm/arch/sharpsl.h> | 22 | #include <asm/arch/sharpsl.h> |
| 23 | #include <asm/arch/hardware.h> | 23 | #include <asm/arch/hardware.h> |
| 24 | #include <asm/arch/pxa-regs.h> | 24 | #include <asm/arch/pxa-regs.h> |
| 25 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 25 | 26 | ||
| 26 | 27 | ||
| 27 | #define PWR_MODE_ACTIVE 0 | 28 | #define PWR_MODE_ACTIVE 0 |
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 859814f62cb0..a3a6199639f9 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig | |||
| @@ -46,13 +46,6 @@ config LEDS_SPITZ | |||
| 46 | This option enables support for the LEDs on Sharp Zaurus | 46 | This option enables support for the LEDs on Sharp Zaurus |
| 47 | SL-Cxx00 series (C1000, C3000, C3100). | 47 | SL-Cxx00 series (C1000, C3000, C3100). |
| 48 | 48 | ||
| 49 | config LEDS_TOSA | ||
| 50 | tristate "LED Support for the Sharp SL-6000 series" | ||
| 51 | depends on LEDS_CLASS && PXA_SHARPSL | ||
| 52 | help | ||
| 53 | This option enables support for the LEDs on Sharp Zaurus | ||
| 54 | SL-6000 series. | ||
| 55 | |||
| 56 | config LEDS_S3C24XX | 49 | config LEDS_S3C24XX |
| 57 | tristate "LED Support for Samsung S3C24XX GPIO LEDs" | 50 | tristate "LED Support for Samsung S3C24XX GPIO LEDs" |
| 58 | depends on LEDS_CLASS && ARCH_S3C2410 | 51 | depends on LEDS_CLASS && ARCH_S3C2410 |
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 84ced3b1a13d..e54f42da21a2 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile | |||
| @@ -9,7 +9,6 @@ obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o | |||
| 9 | obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o | 9 | obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o |
| 10 | obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o | 10 | obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o |
| 11 | obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o | 11 | obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o |
| 12 | obj-$(CONFIG_LEDS_TOSA) += leds-tosa.o | ||
| 13 | obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o | 12 | obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o |
| 14 | obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o | 13 | obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o |
| 15 | obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o | 14 | obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o |
diff --git a/drivers/leds/leds-tosa.c b/drivers/leds/leds-tosa.c deleted file mode 100644 index 9e0a188fbb0a..000000000000 --- a/drivers/leds/leds-tosa.c +++ /dev/null | |||
| @@ -1,130 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * LED Triggers Core | ||
| 3 | * | ||
| 4 | * Copyright 2005 Dirk Opfer | ||
| 5 | * | ||
| 6 | * Author: Dirk Opfer <Dirk@Opfer-Online.de> | ||
| 7 | * based on spitz.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <asm/hardware/scoop.h> | ||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/arch/hardware.h> | ||
| 22 | #include <asm/arch/pxa-regs.h> | ||
| 23 | #include <asm/arch/tosa.h> | ||
| 24 | |||
| 25 | static void tosaled_amber_set(struct led_classdev *led_cdev, | ||
| 26 | enum led_brightness value) | ||
| 27 | { | ||
| 28 | if (value) | ||
| 29 | set_scoop_gpio(&tosascoop_jc_device.dev, | ||
| 30 | TOSA_SCOOP_JC_CHRG_ERR_LED); | ||
| 31 | else | ||
| 32 | reset_scoop_gpio(&tosascoop_jc_device.dev, | ||
| 33 | TOSA_SCOOP_JC_CHRG_ERR_LED); | ||
| 34 | } | ||
| 35 | |||
| 36 | static void tosaled_green_set(struct led_classdev *led_cdev, | ||
| 37 | enum led_brightness value) | ||
| 38 | { | ||
| 39 | if (value) | ||
| 40 | set_scoop_gpio(&tosascoop_jc_device.dev, | ||
| 41 | TOSA_SCOOP_JC_NOTE_LED); | ||
| 42 | else | ||
| 43 | reset_scoop_gpio(&tosascoop_jc_device.dev, | ||
| 44 | TOSA_SCOOP_JC_NOTE_LED); | ||
| 45 | } | ||
| 46 | |||
| 47 | static struct led_classdev tosa_amber_led = { | ||
| 48 | .name = "tosa:amber:charge", | ||
| 49 | .default_trigger = "sharpsl-charge", | ||
| 50 | .brightness_set = tosaled_amber_set, | ||
| 51 | }; | ||
| 52 | |||
| 53 | static struct led_classdev tosa_green_led = { | ||
| 54 | .name = "tosa:green:mail", | ||
| 55 | .default_trigger = "nand-disk", | ||
| 56 | .brightness_set = tosaled_green_set, | ||
| 57 | }; | ||
| 58 | |||
| 59 | #ifdef CONFIG_PM | ||
| 60 | static int tosaled_suspend(struct platform_device *dev, pm_message_t state) | ||
| 61 | { | ||
| 62 | #ifdef CONFIG_LEDS_TRIGGERS | ||
| 63 | if (tosa_amber_led.trigger && strcmp(tosa_amber_led.trigger->name, | ||
| 64 | "sharpsl-charge")) | ||
| 65 | #endif | ||
| 66 | led_classdev_suspend(&tosa_amber_led); | ||
| 67 | led_classdev_suspend(&tosa_green_led); | ||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | static int tosaled_resume(struct platform_device *dev) | ||
| 72 | { | ||
| 73 | led_classdev_resume(&tosa_amber_led); | ||
| 74 | led_classdev_resume(&tosa_green_led); | ||
| 75 | return 0; | ||
| 76 | } | ||
| 77 | #else | ||
| 78 | #define tosaled_suspend NULL | ||
| 79 | #define tosaled_resume NULL | ||
| 80 | #endif | ||
| 81 | |||
| 82 | static int tosaled_probe(struct platform_device *pdev) | ||
| 83 | { | ||
| 84 | int ret; | ||
| 85 | |||
| 86 | ret = led_classdev_register(&pdev->dev, &tosa_amber_led); | ||
| 87 | if (ret < 0) | ||
| 88 | return ret; | ||
| 89 | |||
| 90 | ret = led_classdev_register(&pdev->dev, &tosa_green_led); | ||
| 91 | if (ret < 0) | ||
| 92 | led_classdev_unregister(&tosa_amber_led); | ||
| 93 | |||
| 94 | return ret; | ||
| 95 | } | ||
| 96 | |||
| 97 | static int tosaled_remove(struct platform_device *pdev) | ||
| 98 | { | ||
| 99 | led_classdev_unregister(&tosa_amber_led); | ||
| 100 | led_classdev_unregister(&tosa_green_led); | ||
| 101 | |||
| 102 | return 0; | ||
| 103 | } | ||
| 104 | |||
| 105 | static struct platform_driver tosaled_driver = { | ||
| 106 | .probe = tosaled_probe, | ||
| 107 | .remove = tosaled_remove, | ||
| 108 | .suspend = tosaled_suspend, | ||
| 109 | .resume = tosaled_resume, | ||
| 110 | .driver = { | ||
| 111 | .name = "tosa-led", | ||
| 112 | }, | ||
| 113 | }; | ||
| 114 | |||
| 115 | static int __init tosaled_init(void) | ||
| 116 | { | ||
| 117 | return platform_driver_register(&tosaled_driver); | ||
| 118 | } | ||
| 119 | |||
| 120 | static void __exit tosaled_exit(void) | ||
| 121 | { | ||
| 122 | platform_driver_unregister(&tosaled_driver); | ||
| 123 | } | ||
| 124 | |||
| 125 | module_init(tosaled_init); | ||
| 126 | module_exit(tosaled_exit); | ||
| 127 | |||
| 128 | MODULE_AUTHOR("Dirk Opfer <Dirk@Opfer-Online.de>"); | ||
| 129 | MODULE_DESCRIPTION("Tosa LED driver"); | ||
| 130 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 0c886c882385..2566479937c9 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig | |||
| @@ -22,6 +22,22 @@ config MFD_ASIC3 | |||
| 22 | This driver supports the ASIC3 multifunction chip found on many | 22 | This driver supports the ASIC3 multifunction chip found on many |
| 23 | PDAs (mainly iPAQ and HTC based ones) | 23 | PDAs (mainly iPAQ and HTC based ones) |
| 24 | 24 | ||
| 25 | config HTC_EGPIO | ||
| 26 | bool "HTC EGPIO support" | ||
| 27 | depends on GENERIC_HARDIRQS && HAVE_GPIO_LIB | ||
| 28 | help | ||
| 29 | This driver supports the CPLD egpio chip present on | ||
| 30 | several HTC phones. It provides basic support for input | ||
| 31 | pins, output pins, and irqs. | ||
| 32 | |||
| 33 | config HTC_PASIC3 | ||
| 34 | tristate "HTC PASIC3 LED/DS1WM chip support" | ||
| 35 | help | ||
| 36 | This core driver provides register access for the LED/DS1WM | ||
| 37 | chips labeled "AIC2" and "AIC3", found on HTC Blueangel and | ||
| 38 | HTC Magician devices, respectively. Actual functionality is | ||
| 39 | handled by the leds-pasic3 and ds1wm drivers. | ||
| 40 | |||
| 25 | endmenu | 41 | endmenu |
| 26 | 42 | ||
| 27 | menu "Multimedia Capabilities Port drivers" | 43 | menu "Multimedia Capabilities Port drivers" |
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 521cd5cb68af..eef4e26807df 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile | |||
| @@ -5,6 +5,9 @@ | |||
| 5 | obj-$(CONFIG_MFD_SM501) += sm501.o | 5 | obj-$(CONFIG_MFD_SM501) += sm501.o |
| 6 | obj-$(CONFIG_MFD_ASIC3) += asic3.o | 6 | obj-$(CONFIG_MFD_ASIC3) += asic3.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o | ||
| 9 | obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o | ||
| 10 | |||
| 8 | obj-$(CONFIG_MCP) += mcp-core.o | 11 | obj-$(CONFIG_MCP) += mcp-core.o |
| 9 | obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o | 12 | obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o |
| 10 | obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o | 13 | obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o |
diff --git a/drivers/mfd/htc-egpio.c b/drivers/mfd/htc-egpio.c new file mode 100644 index 000000000000..8872cc077519 --- /dev/null +++ b/drivers/mfd/htc-egpio.c | |||
| @@ -0,0 +1,440 @@ | |||
| 1 | /* | ||
| 2 | * Support for the GPIO/IRQ expander chips present on several HTC phones. | ||
| 3 | * These are implemented in CPLD chips present on the board. | ||
| 4 | * | ||
| 5 | * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net> | ||
| 6 | * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com> | ||
| 7 | * | ||
| 8 | * This file may be distributed under the terms of the GNU GPL license. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/interrupt.h> | ||
| 14 | #include <linux/irq.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/spinlock.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/mfd/htc-egpio.h> | ||
| 20 | |||
| 21 | struct egpio_chip { | ||
| 22 | int reg_start; | ||
| 23 | int cached_values; | ||
| 24 | unsigned long is_out; | ||
| 25 | struct device *dev; | ||
| 26 | struct gpio_chip chip; | ||
| 27 | }; | ||
| 28 | |||
| 29 | struct egpio_info { | ||
| 30 | spinlock_t lock; | ||
| 31 | |||
| 32 | /* iomem info */ | ||
| 33 | void __iomem *base_addr; | ||
| 34 | int bus_shift; /* byte shift */ | ||
| 35 | int reg_shift; /* bit shift */ | ||
| 36 | int reg_mask; | ||
| 37 | |||
| 38 | /* irq info */ | ||
| 39 | int ack_register; | ||
| 40 | int ack_write; | ||
| 41 | u16 irqs_enabled; | ||
| 42 | uint irq_start; | ||
| 43 | int nirqs; | ||
| 44 | uint chained_irq; | ||
| 45 | |||
| 46 | /* egpio info */ | ||
| 47 | struct egpio_chip *chip; | ||
| 48 | int nchips; | ||
| 49 | }; | ||
| 50 | |||
| 51 | static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg) | ||
| 52 | { | ||
| 53 | writew(value, ei->base_addr + (reg << ei->bus_shift)); | ||
| 54 | } | ||
| 55 | |||
| 56 | static inline u16 egpio_readw(struct egpio_info *ei, int reg) | ||
| 57 | { | ||
| 58 | return readw(ei->base_addr + (reg << ei->bus_shift)); | ||
| 59 | } | ||
| 60 | |||
| 61 | /* | ||
| 62 | * IRQs | ||
| 63 | */ | ||
| 64 | |||
| 65 | static inline void ack_irqs(struct egpio_info *ei) | ||
| 66 | { | ||
| 67 | egpio_writew(ei->ack_write, ei, ei->ack_register); | ||
| 68 | pr_debug("EGPIO ack - write %x to base+%x\n", | ||
| 69 | ei->ack_write, ei->ack_register << ei->bus_shift); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void egpio_ack(unsigned int irq) | ||
| 73 | { | ||
| 74 | } | ||
| 75 | |||
| 76 | /* There does not appear to be a way to proactively mask interrupts | ||
| 77 | * on the egpio chip itself. So, we simply ignore interrupts that | ||
| 78 | * aren't desired. */ | ||
| 79 | static void egpio_mask(unsigned int irq) | ||
| 80 | { | ||
| 81 | struct egpio_info *ei = get_irq_chip_data(irq); | ||
| 82 | ei->irqs_enabled &= ~(1 << (irq - ei->irq_start)); | ||
| 83 | pr_debug("EGPIO mask %d %04x\n", irq, ei->irqs_enabled); | ||
| 84 | } | ||
| 85 | static void egpio_unmask(unsigned int irq) | ||
| 86 | { | ||
| 87 | struct egpio_info *ei = get_irq_chip_data(irq); | ||
| 88 | ei->irqs_enabled |= 1 << (irq - ei->irq_start); | ||
| 89 | pr_debug("EGPIO unmask %d %04x\n", irq, ei->irqs_enabled); | ||
| 90 | } | ||
| 91 | |||
| 92 | static struct irq_chip egpio_muxed_chip = { | ||
| 93 | .name = "htc-egpio", | ||
| 94 | .ack = egpio_ack, | ||
| 95 | .mask = egpio_mask, | ||
| 96 | .unmask = egpio_unmask, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static void egpio_handler(unsigned int irq, struct irq_desc *desc) | ||
| 100 | { | ||
| 101 | struct egpio_info *ei = get_irq_data(irq); | ||
| 102 | int irqpin; | ||
| 103 | |||
| 104 | /* Read current pins. */ | ||
| 105 | unsigned long readval = egpio_readw(ei, ei->ack_register); | ||
| 106 | pr_debug("IRQ reg: %x\n", (unsigned int)readval); | ||
| 107 | /* Ack/unmask interrupts. */ | ||
| 108 | ack_irqs(ei); | ||
| 109 | /* Process all set pins. */ | ||
| 110 | readval &= ei->irqs_enabled; | ||
| 111 | for_each_bit(irqpin, &readval, ei->nirqs) { | ||
| 112 | /* Run irq handler */ | ||
| 113 | pr_debug("got IRQ %d\n", irqpin); | ||
| 114 | irq = ei->irq_start + irqpin; | ||
| 115 | desc = &irq_desc[irq]; | ||
| 116 | desc->handle_irq(irq, desc); | ||
| 117 | } | ||
| 118 | } | ||
| 119 | |||
| 120 | int htc_egpio_get_wakeup_irq(struct device *dev) | ||
| 121 | { | ||
| 122 | struct egpio_info *ei = dev_get_drvdata(dev); | ||
| 123 | |||
| 124 | /* Read current pins. */ | ||
| 125 | u16 readval = egpio_readw(ei, ei->ack_register); | ||
| 126 | /* Ack/unmask interrupts. */ | ||
| 127 | ack_irqs(ei); | ||
| 128 | /* Return first set pin. */ | ||
| 129 | readval &= ei->irqs_enabled; | ||
| 130 | return ei->irq_start + ffs(readval) - 1; | ||
| 131 | } | ||
| 132 | EXPORT_SYMBOL(htc_egpio_get_wakeup_irq); | ||
| 133 | |||
| 134 | static inline int egpio_pos(struct egpio_info *ei, int bit) | ||
| 135 | { | ||
| 136 | return bit >> ei->reg_shift; | ||
| 137 | } | ||
| 138 | |||
| 139 | static inline int egpio_bit(struct egpio_info *ei, int bit) | ||
| 140 | { | ||
| 141 | return 1 << (bit & ((1 << ei->reg_shift)-1)); | ||
| 142 | } | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Input pins | ||
| 146 | */ | ||
| 147 | |||
| 148 | static int egpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 149 | { | ||
| 150 | struct egpio_chip *egpio; | ||
| 151 | struct egpio_info *ei; | ||
| 152 | unsigned bit; | ||
| 153 | int reg; | ||
| 154 | int value; | ||
| 155 | |||
| 156 | pr_debug("egpio_get_value(%d)\n", chip->base + offset); | ||
| 157 | |||
| 158 | egpio = container_of(chip, struct egpio_chip, chip); | ||
| 159 | ei = dev_get_drvdata(egpio->dev); | ||
| 160 | bit = egpio_bit(ei, offset); | ||
| 161 | reg = egpio->reg_start + egpio_pos(ei, offset); | ||
| 162 | |||
| 163 | value = egpio_readw(ei, reg); | ||
| 164 | pr_debug("readw(%p + %x) = %x\n", | ||
| 165 | ei->base_addr, reg << ei->bus_shift, value); | ||
| 166 | return value & bit; | ||
| 167 | } | ||
| 168 | |||
| 169 | static int egpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 170 | { | ||
| 171 | struct egpio_chip *egpio; | ||
| 172 | |||
| 173 | egpio = container_of(chip, struct egpio_chip, chip); | ||
| 174 | return test_bit(offset, &egpio->is_out) ? -EINVAL : 0; | ||
| 175 | } | ||
| 176 | |||
| 177 | |||
| 178 | /* | ||
| 179 | * Output pins | ||
| 180 | */ | ||
| 181 | |||
| 182 | static void egpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 183 | { | ||
| 184 | unsigned long flag; | ||
| 185 | struct egpio_chip *egpio; | ||
| 186 | struct egpio_info *ei; | ||
| 187 | unsigned bit; | ||
| 188 | int pos; | ||
| 189 | int reg; | ||
| 190 | int shift; | ||
| 191 | |||
| 192 | pr_debug("egpio_set(%s, %d(%d), %d)\n", | ||
| 193 | chip->label, offset, offset+chip->base, value); | ||
| 194 | |||
| 195 | egpio = container_of(chip, struct egpio_chip, chip); | ||
| 196 | ei = dev_get_drvdata(egpio->dev); | ||
| 197 | bit = egpio_bit(ei, offset); | ||
| 198 | pos = egpio_pos(ei, offset); | ||
| 199 | reg = egpio->reg_start + pos; | ||
| 200 | shift = pos << ei->reg_shift; | ||
| 201 | |||
| 202 | pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear", | ||
| 203 | reg, (egpio->cached_values >> shift) & ei->reg_mask); | ||
| 204 | |||
| 205 | spin_lock_irqsave(&ei->lock, flag); | ||
| 206 | if (value) | ||
| 207 | egpio->cached_values |= (1 << offset); | ||
| 208 | else | ||
| 209 | egpio->cached_values &= ~(1 << offset); | ||
| 210 | egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg); | ||
| 211 | spin_unlock_irqrestore(&ei->lock, flag); | ||
| 212 | } | ||
| 213 | |||
| 214 | static int egpio_direction_output(struct gpio_chip *chip, | ||
| 215 | unsigned offset, int value) | ||
| 216 | { | ||
| 217 | struct egpio_chip *egpio; | ||
| 218 | |||
| 219 | egpio = container_of(chip, struct egpio_chip, chip); | ||
| 220 | if (test_bit(offset, &egpio->is_out)) { | ||
| 221 | egpio_set(chip, offset, value); | ||
| 222 | return 0; | ||
| 223 | } else { | ||
| 224 | return -EINVAL; | ||
| 225 | } | ||
| 226 | } | ||
| 227 | |||
| 228 | static void egpio_write_cache(struct egpio_info *ei) | ||
| 229 | { | ||
| 230 | int i; | ||
| 231 | struct egpio_chip *egpio; | ||
| 232 | int shift; | ||
| 233 | |||
| 234 | for (i = 0; i < ei->nchips; i++) { | ||
| 235 | egpio = &(ei->chip[i]); | ||
| 236 | if (!egpio->is_out) | ||
| 237 | continue; | ||
| 238 | |||
| 239 | for (shift = 0; shift < egpio->chip.ngpio; | ||
| 240 | shift += (1<<ei->reg_shift)) { | ||
| 241 | |||
| 242 | int reg = egpio->reg_start + egpio_pos(ei, shift); | ||
| 243 | |||
| 244 | if (!((egpio->is_out >> shift) & ei->reg_mask)) | ||
| 245 | continue; | ||
| 246 | |||
| 247 | pr_debug("EGPIO: setting %x to %x, was %x\n", reg, | ||
| 248 | (egpio->cached_values >> shift) & ei->reg_mask, | ||
| 249 | egpio_readw(ei, reg)); | ||
| 250 | |||
| 251 | egpio_writew((egpio->cached_values >> shift) | ||
| 252 | & ei->reg_mask, ei, reg); | ||
| 253 | } | ||
| 254 | } | ||
| 255 | } | ||
| 256 | |||
| 257 | |||
| 258 | /* | ||
| 259 | * Setup | ||
| 260 | */ | ||
| 261 | |||
| 262 | static int __init egpio_probe(struct platform_device *pdev) | ||
| 263 | { | ||
| 264 | struct htc_egpio_platform_data *pdata = pdev->dev.platform_data; | ||
| 265 | struct resource *res; | ||
| 266 | struct egpio_info *ei; | ||
| 267 | struct gpio_chip *chip; | ||
| 268 | unsigned int irq, irq_end; | ||
| 269 | int i; | ||
| 270 | int ret; | ||
| 271 | |||
| 272 | /* Initialize ei data structure. */ | ||
| 273 | ei = kzalloc(sizeof(*ei), GFP_KERNEL); | ||
| 274 | if (!ei) | ||
| 275 | return -ENOMEM; | ||
| 276 | |||
| 277 | spin_lock_init(&ei->lock); | ||
| 278 | |||
| 279 | /* Find chained irq */ | ||
| 280 | ret = -EINVAL; | ||
| 281 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
| 282 | if (res) | ||
| 283 | ei->chained_irq = res->start; | ||
| 284 | |||
| 285 | /* Map egpio chip into virtual address space. */ | ||
| 286 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 287 | if (!res) | ||
| 288 | goto fail; | ||
| 289 | ei->base_addr = ioremap_nocache(res->start, res->end - res->start); | ||
| 290 | if (!ei->base_addr) | ||
| 291 | goto fail; | ||
| 292 | pr_debug("EGPIO phys=%08x virt=%p\n", res->start, ei->base_addr); | ||
| 293 | |||
| 294 | if ((pdata->bus_width != 16) && (pdata->bus_width != 32)) | ||
| 295 | goto fail; | ||
| 296 | ei->bus_shift = fls(pdata->bus_width - 1) - 3; | ||
| 297 | pr_debug("bus_shift = %d\n", ei->bus_shift); | ||
| 298 | |||
| 299 | if ((pdata->reg_width != 8) && (pdata->reg_width != 16)) | ||
| 300 | goto fail; | ||
| 301 | ei->reg_shift = fls(pdata->reg_width - 1); | ||
| 302 | pr_debug("reg_shift = %d\n", ei->reg_shift); | ||
| 303 | |||
| 304 | ei->reg_mask = (1 << pdata->reg_width) - 1; | ||
| 305 | |||
| 306 | platform_set_drvdata(pdev, ei); | ||
| 307 | |||
| 308 | ei->nchips = pdata->num_chips; | ||
| 309 | ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL); | ||
| 310 | if (!ei) { | ||
| 311 | ret = -ENOMEM; | ||
| 312 | goto fail; | ||
| 313 | } | ||
| 314 | for (i = 0; i < ei->nchips; i++) { | ||
| 315 | ei->chip[i].reg_start = pdata->chip[i].reg_start; | ||
| 316 | ei->chip[i].cached_values = pdata->chip[i].initial_values; | ||
| 317 | ei->chip[i].is_out = pdata->chip[i].direction; | ||
| 318 | ei->chip[i].dev = &(pdev->dev); | ||
| 319 | chip = &(ei->chip[i].chip); | ||
| 320 | chip->label = "htc-egpio"; | ||
| 321 | chip->get = egpio_get; | ||
| 322 | chip->set = egpio_set; | ||
| 323 | chip->direction_input = egpio_direction_input; | ||
| 324 | chip->direction_output = egpio_direction_output; | ||
| 325 | chip->base = pdata->chip[i].gpio_base; | ||
| 326 | chip->ngpio = pdata->chip[i].num_gpios; | ||
| 327 | |||
| 328 | gpiochip_add(chip); | ||
| 329 | } | ||
| 330 | |||
| 331 | /* Set initial pin values */ | ||
| 332 | egpio_write_cache(ei); | ||
| 333 | |||
| 334 | ei->irq_start = pdata->irq_base; | ||
| 335 | ei->nirqs = pdata->num_irqs; | ||
| 336 | ei->ack_register = pdata->ack_register; | ||
| 337 | |||
| 338 | if (ei->chained_irq) { | ||
| 339 | /* Setup irq handlers */ | ||
| 340 | ei->ack_write = 0xFFFF; | ||
| 341 | if (pdata->invert_acks) | ||
| 342 | ei->ack_write = 0; | ||
| 343 | irq_end = ei->irq_start + ei->nirqs; | ||
| 344 | for (irq = ei->irq_start; irq < irq_end; irq++) { | ||
| 345 | set_irq_chip(irq, &egpio_muxed_chip); | ||
| 346 | set_irq_chip_data(irq, ei); | ||
| 347 | set_irq_handler(irq, handle_simple_irq); | ||
| 348 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 349 | } | ||
| 350 | set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING); | ||
| 351 | set_irq_data(ei->chained_irq, ei); | ||
| 352 | set_irq_chained_handler(ei->chained_irq, egpio_handler); | ||
| 353 | ack_irqs(ei); | ||
| 354 | |||
| 355 | device_init_wakeup(&pdev->dev, 1); | ||
| 356 | } | ||
| 357 | |||
| 358 | return 0; | ||
| 359 | |||
| 360 | fail: | ||
| 361 | printk(KERN_ERR "EGPIO failed to setup\n"); | ||
| 362 | kfree(ei); | ||
| 363 | return ret; | ||
| 364 | } | ||
| 365 | |||
| 366 | static int __exit egpio_remove(struct platform_device *pdev) | ||
| 367 | { | ||
| 368 | struct egpio_info *ei = platform_get_drvdata(pdev); | ||
| 369 | unsigned int irq, irq_end; | ||
| 370 | |||
| 371 | if (ei->chained_irq) { | ||
| 372 | irq_end = ei->irq_start + ei->nirqs; | ||
| 373 | for (irq = ei->irq_start; irq < irq_end; irq++) { | ||
| 374 | set_irq_chip(irq, NULL); | ||
| 375 | set_irq_handler(irq, NULL); | ||
| 376 | set_irq_flags(irq, 0); | ||
| 377 | } | ||
| 378 | set_irq_chained_handler(ei->chained_irq, NULL); | ||
| 379 | device_init_wakeup(&pdev->dev, 0); | ||
| 380 | } | ||
| 381 | iounmap(ei->base_addr); | ||
| 382 | kfree(ei->chip); | ||
| 383 | kfree(ei); | ||
| 384 | |||
| 385 | return 0; | ||
| 386 | } | ||
| 387 | |||
| 388 | #ifdef CONFIG_PM | ||
| 389 | static int egpio_suspend(struct platform_device *pdev, pm_message_t state) | ||
| 390 | { | ||
| 391 | struct egpio_info *ei = platform_get_drvdata(pdev); | ||
| 392 | |||
| 393 | if (ei->chained_irq && device_may_wakeup(&pdev->dev)) | ||
| 394 | enable_irq_wake(ei->chained_irq); | ||
| 395 | return 0; | ||
| 396 | } | ||
| 397 | |||
| 398 | static int egpio_resume(struct platform_device *pdev) | ||
| 399 | { | ||
| 400 | struct egpio_info *ei = platform_get_drvdata(pdev); | ||
| 401 | |||
| 402 | if (ei->chained_irq && device_may_wakeup(&pdev->dev)) | ||
| 403 | disable_irq_wake(ei->chained_irq); | ||
| 404 | |||
| 405 | /* Update registers from the cache, in case | ||
| 406 | the CPLD was powered off during suspend */ | ||
| 407 | egpio_write_cache(ei); | ||
| 408 | return 0; | ||
| 409 | } | ||
| 410 | #else | ||
| 411 | #define egpio_suspend NULL | ||
| 412 | #define egpio_resume NULL | ||
| 413 | #endif | ||
| 414 | |||
| 415 | |||
| 416 | static struct platform_driver egpio_driver = { | ||
| 417 | .driver = { | ||
| 418 | .name = "htc-egpio", | ||
| 419 | }, | ||
| 420 | .remove = __exit_p(egpio_remove), | ||
| 421 | .suspend = egpio_suspend, | ||
| 422 | .resume = egpio_resume, | ||
| 423 | }; | ||
| 424 | |||
| 425 | static int __init egpio_init(void) | ||
| 426 | { | ||
| 427 | return platform_driver_probe(&egpio_driver, egpio_probe); | ||
| 428 | } | ||
| 429 | |||
| 430 | static void __exit egpio_exit(void) | ||
| 431 | { | ||
| 432 | platform_driver_unregister(&egpio_driver); | ||
| 433 | } | ||
| 434 | |||
| 435 | /* start early for dependencies */ | ||
| 436 | subsys_initcall(egpio_init); | ||
| 437 | module_exit(egpio_exit) | ||
| 438 | |||
| 439 | MODULE_LICENSE("GPL"); | ||
| 440 | MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>"); | ||
diff --git a/drivers/mfd/htc-pasic3.c b/drivers/mfd/htc-pasic3.c new file mode 100644 index 000000000000..af66f4f28300 --- /dev/null +++ b/drivers/mfd/htc-pasic3.c | |||
| @@ -0,0 +1,265 @@ | |||
| 1 | /* | ||
| 2 | * Core driver for HTC PASIC3 LED/DS1WM chip. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Philipp Zabel <philipp.zabel@gmail.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; version 2 of the License. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | |||
| 15 | #include <linux/ds1wm.h> | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/irq.h> | ||
| 19 | #include <linux/interrupt.h> | ||
| 20 | #include <linux/mfd/htc-pasic3.h> | ||
| 21 | |||
| 22 | #include <asm/arch/pxa-regs.h> | ||
| 23 | |||
| 24 | struct pasic3_data { | ||
| 25 | void __iomem *mapping; | ||
| 26 | unsigned int bus_shift; | ||
| 27 | struct platform_device *ds1wm_pdev; | ||
| 28 | struct platform_device *led_pdev; | ||
| 29 | }; | ||
| 30 | |||
| 31 | #define REG_ADDR 5 | ||
| 32 | #define REG_DATA 6 | ||
| 33 | #define NUM_REGS 7 | ||
| 34 | |||
| 35 | #define READ_MODE 0x80 | ||
| 36 | |||
| 37 | /* | ||
| 38 | * write to a secondary register on the PASIC3 | ||
| 39 | */ | ||
| 40 | void pasic3_write_register(struct device *dev, u32 reg, u8 val) | ||
| 41 | { | ||
| 42 | struct pasic3_data *asic = dev->driver_data; | ||
| 43 | int bus_shift = asic->bus_shift; | ||
| 44 | void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift); | ||
| 45 | void __iomem *data = asic->mapping + (REG_DATA << bus_shift); | ||
| 46 | |||
| 47 | __raw_writeb(~READ_MODE & reg, addr); | ||
| 48 | __raw_writeb(val, data); | ||
| 49 | } | ||
| 50 | EXPORT_SYMBOL(pasic3_write_register); /* for leds-pasic3 */ | ||
| 51 | |||
| 52 | /* | ||
| 53 | * read from a secondary register on the PASIC3 | ||
| 54 | */ | ||
| 55 | u8 pasic3_read_register(struct device *dev, u32 reg) | ||
| 56 | { | ||
| 57 | struct pasic3_data *asic = dev->driver_data; | ||
| 58 | int bus_shift = asic->bus_shift; | ||
| 59 | void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift); | ||
| 60 | void __iomem *data = asic->mapping + (REG_DATA << bus_shift); | ||
| 61 | |||
| 62 | __raw_writeb(READ_MODE | reg, addr); | ||
| 63 | return __raw_readb(data); | ||
| 64 | } | ||
| 65 | EXPORT_SYMBOL(pasic3_read_register); /* for leds-pasic3 */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * LEDs | ||
| 69 | */ | ||
| 70 | |||
| 71 | static int led_device_add(struct device *pasic3_dev, | ||
| 72 | const struct pasic3_leds_machinfo *pdata) | ||
| 73 | { | ||
| 74 | struct pasic3_data *asic = pasic3_dev->driver_data; | ||
| 75 | struct platform_device *pdev; | ||
| 76 | int ret; | ||
| 77 | |||
| 78 | pdev = platform_device_alloc("pasic3-led", -1); | ||
| 79 | if (!pdev) { | ||
| 80 | dev_dbg(pasic3_dev, "failed to allocate LED platform device\n"); | ||
| 81 | return -ENOMEM; | ||
| 82 | } | ||
| 83 | |||
| 84 | ret = platform_device_add_data(pdev, pdata, | ||
| 85 | sizeof(struct pasic3_leds_machinfo)); | ||
| 86 | if (ret < 0) { | ||
| 87 | dev_dbg(pasic3_dev, "failed to add LED platform data\n"); | ||
| 88 | goto exit_pdev_put; | ||
| 89 | } | ||
| 90 | |||
| 91 | pdev->dev.parent = pasic3_dev; | ||
| 92 | ret = platform_device_add(pdev); | ||
| 93 | if (ret < 0) { | ||
| 94 | dev_dbg(pasic3_dev, "failed to add LED platform device\n"); | ||
| 95 | goto exit_pdev_put; | ||
| 96 | } | ||
| 97 | |||
| 98 | asic->led_pdev = pdev; | ||
| 99 | return 0; | ||
| 100 | |||
| 101 | exit_pdev_put: | ||
| 102 | platform_device_put(pdev); | ||
| 103 | return ret; | ||
| 104 | } | ||
| 105 | |||
| 106 | /* | ||
| 107 | * DS1WM | ||
| 108 | */ | ||
| 109 | |||
| 110 | static void ds1wm_enable(struct platform_device *pdev) | ||
| 111 | { | ||
| 112 | struct device *dev = pdev->dev.parent; | ||
| 113 | int c; | ||
| 114 | |||
| 115 | c = pasic3_read_register(dev, 0x28); | ||
| 116 | pasic3_write_register(dev, 0x28, c & 0x7f); | ||
| 117 | |||
| 118 | dev_dbg(dev, "DS1WM OWM_EN low (active) %02x\n", c & 0x7f); | ||
| 119 | } | ||
| 120 | |||
| 121 | static void ds1wm_disable(struct platform_device *pdev) | ||
| 122 | { | ||
| 123 | struct device *dev = pdev->dev.parent; | ||
| 124 | int c; | ||
| 125 | |||
| 126 | c = pasic3_read_register(dev, 0x28); | ||
| 127 | pasic3_write_register(dev, 0x28, c | 0x80); | ||
| 128 | |||
| 129 | dev_dbg(dev, "DS1WM OWM_EN high (inactive) %02x\n", c | 0x80); | ||
| 130 | } | ||
| 131 | |||
| 132 | static struct ds1wm_platform_data ds1wm_pdata = { | ||
| 133 | .bus_shift = 2, | ||
| 134 | .enable = ds1wm_enable, | ||
| 135 | .disable = ds1wm_disable, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static int ds1wm_device_add(struct device *pasic3_dev, int bus_shift) | ||
| 139 | { | ||
| 140 | struct pasic3_data *asic = pasic3_dev->driver_data; | ||
| 141 | struct platform_device *pdev; | ||
| 142 | int ret; | ||
| 143 | |||
| 144 | pdev = platform_device_alloc("ds1wm", -1); | ||
| 145 | if (!pdev) { | ||
| 146 | dev_dbg(pasic3_dev, "failed to allocate DS1WM platform device\n"); | ||
| 147 | return -ENOMEM; | ||
| 148 | } | ||
| 149 | |||
| 150 | ret = platform_device_add_resources(pdev, pdev->resource, | ||
| 151 | pdev->num_resources); | ||
| 152 | if (ret < 0) { | ||
| 153 | dev_dbg(pasic3_dev, "failed to add DS1WM resources\n"); | ||
| 154 | goto exit_pdev_put; | ||
| 155 | } | ||
| 156 | |||
| 157 | ds1wm_pdata.bus_shift = asic->bus_shift; | ||
| 158 | ret = platform_device_add_data(pdev, &ds1wm_pdata, | ||
| 159 | sizeof(struct ds1wm_platform_data)); | ||
| 160 | if (ret < 0) { | ||
| 161 | dev_dbg(pasic3_dev, "failed to add DS1WM platform data\n"); | ||
| 162 | goto exit_pdev_put; | ||
| 163 | } | ||
| 164 | |||
| 165 | pdev->dev.parent = pasic3_dev; | ||
| 166 | ret = platform_device_add(pdev); | ||
| 167 | if (ret < 0) { | ||
| 168 | dev_dbg(pasic3_dev, "failed to add DS1WM platform device\n"); | ||
| 169 | goto exit_pdev_put; | ||
| 170 | } | ||
| 171 | |||
| 172 | asic->ds1wm_pdev = pdev; | ||
| 173 | return 0; | ||
| 174 | |||
| 175 | exit_pdev_put: | ||
| 176 | platform_device_put(pdev); | ||
| 177 | return ret; | ||
| 178 | } | ||
| 179 | |||
| 180 | static int __init pasic3_probe(struct platform_device *pdev) | ||
| 181 | { | ||
| 182 | struct pasic3_platform_data *pdata = pdev->dev.platform_data; | ||
| 183 | struct device *dev = &pdev->dev; | ||
| 184 | struct pasic3_data *asic; | ||
| 185 | struct resource *r; | ||
| 186 | int ret; | ||
| 187 | |||
| 188 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 189 | if (!r) | ||
| 190 | return -ENXIO; | ||
| 191 | |||
| 192 | if (!request_mem_region(r->start, r->end - r->start + 1, "pasic3")) | ||
| 193 | return -EBUSY; | ||
| 194 | |||
| 195 | asic = kzalloc(sizeof(struct pasic3_data), GFP_KERNEL); | ||
| 196 | if (!asic) | ||
| 197 | return -ENOMEM; | ||
| 198 | |||
| 199 | platform_set_drvdata(pdev, asic); | ||
| 200 | |||
| 201 | if (pdata && pdata->bus_shift) | ||
| 202 | asic->bus_shift = pdata->bus_shift; | ||
| 203 | else | ||
| 204 | asic->bus_shift = 2; | ||
| 205 | |||
| 206 | asic->mapping = ioremap(r->start, r->end - r->start + 1); | ||
| 207 | if (!asic->mapping) { | ||
| 208 | dev_err(dev, "couldn't ioremap PASIC3\n"); | ||
| 209 | kfree(asic); | ||
| 210 | return -ENOMEM; | ||
| 211 | } | ||
| 212 | |||
| 213 | ret = ds1wm_device_add(dev, asic->bus_shift); | ||
| 214 | if (ret < 0) | ||
| 215 | dev_warn(dev, "failed to register DS1WM\n"); | ||
| 216 | |||
| 217 | if (pdata->led_pdata) { | ||
| 218 | ret = led_device_add(dev, pdata->led_pdata); | ||
| 219 | if (ret < 0) | ||
| 220 | dev_warn(dev, "failed to register LED device\n"); | ||
| 221 | } | ||
| 222 | |||
| 223 | return 0; | ||
| 224 | } | ||
| 225 | |||
| 226 | static int pasic3_remove(struct platform_device *pdev) | ||
| 227 | { | ||
| 228 | struct pasic3_data *asic = platform_get_drvdata(pdev); | ||
| 229 | struct resource *r; | ||
| 230 | |||
| 231 | if (asic->led_pdev) | ||
| 232 | platform_device_unregister(asic->led_pdev); | ||
| 233 | if (asic->ds1wm_pdev) | ||
| 234 | platform_device_unregister(asic->ds1wm_pdev); | ||
| 235 | |||
| 236 | iounmap(asic->mapping); | ||
| 237 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 238 | release_mem_region(r->start, r->end - r->start + 1); | ||
| 239 | kfree(asic); | ||
| 240 | return 0; | ||
| 241 | } | ||
| 242 | |||
| 243 | static struct platform_driver pasic3_driver = { | ||
| 244 | .driver = { | ||
| 245 | .name = "pasic3", | ||
| 246 | }, | ||
| 247 | .remove = pasic3_remove, | ||
| 248 | }; | ||
| 249 | |||
| 250 | static int __init pasic3_base_init(void) | ||
| 251 | { | ||
| 252 | return platform_driver_probe(&pasic3_driver, pasic3_probe); | ||
| 253 | } | ||
| 254 | |||
| 255 | static void __exit pasic3_base_exit(void) | ||
| 256 | { | ||
| 257 | platform_driver_unregister(&pasic3_driver); | ||
| 258 | } | ||
| 259 | |||
| 260 | module_init(pasic3_base_init); | ||
| 261 | module_exit(pasic3_base_exit); | ||
| 262 | |||
| 263 | MODULE_AUTHOR("Philipp Zabel <philipp.zabel@gmail.com>"); | ||
| 264 | MODULE_DESCRIPTION("Core driver for HTC PASIC3"); | ||
| 265 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 4a3c6759492b..959fb86cda01 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig | |||
| @@ -314,7 +314,7 @@ config MTD_ALAUDA | |||
| 314 | 314 | ||
| 315 | config MTD_NAND_ORION | 315 | config MTD_NAND_ORION |
| 316 | tristate "NAND Flash support for Marvell Orion SoC" | 316 | tristate "NAND Flash support for Marvell Orion SoC" |
| 317 | depends on ARCH_ORION && MTD_NAND | 317 | depends on PLAT_ORION && MTD_NAND |
| 318 | help | 318 | help |
| 319 | This enables the NAND flash controller on Orion machines. | 319 | This enables the NAND flash controller on Orion machines. |
| 320 | 320 | ||
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index 9162cca0182b..ec5ad28b237e 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c | |||
| @@ -18,8 +18,8 @@ | |||
| 18 | #include <linux/mtd/partitions.h> | 18 | #include <linux/mtd/partitions.h> |
| 19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
| 20 | #include <asm/sizes.h> | 20 | #include <asm/sizes.h> |
| 21 | #include <asm/arch/platform.h> | ||
| 22 | #include <asm/arch/hardware.h> | 21 | #include <asm/arch/hardware.h> |
| 22 | #include <asm/plat-orion/orion_nand.h> | ||
| 23 | 23 | ||
| 24 | #ifdef CONFIG_MTD_CMDLINE_PARTS | 24 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
| 25 | static const char *part_probes[] = { "cmdlinepart", NULL }; | 25 | static const char *part_probes[] = { "cmdlinepart", NULL }; |
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index fe7b5ec09708..124d29f5fa0c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
| @@ -2415,7 +2415,7 @@ config UGETH_TX_ON_DEMAND | |||
| 2415 | 2415 | ||
| 2416 | config MV643XX_ETH | 2416 | config MV643XX_ETH |
| 2417 | tristate "Marvell Discovery (643XX) and Orion ethernet support" | 2417 | tristate "Marvell Discovery (643XX) and Orion ethernet support" |
| 2418 | depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || ARCH_ORION | 2418 | depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || PLAT_ORION |
| 2419 | select MII | 2419 | select MII |
| 2420 | help | 2420 | help |
| 2421 | This driver supports the gigabit ethernet MACs in the | 2421 | This driver supports the gigabit ethernet MACs in the |
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index 8c09344f58dc..8db71ab20456 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <asm/hardware.h> | 36 | #include <asm/hardware.h> |
| 37 | #include <asm/arch/irda.h> | 37 | #include <asm/arch/irda.h> |
| 38 | #include <asm/arch/pxa-regs.h> | 38 | #include <asm/arch/pxa-regs.h> |
| 39 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 39 | 40 | ||
| 40 | #ifdef CONFIG_MACH_MAINSTONE | 41 | #ifdef CONFIG_MACH_MAINSTONE |
| 41 | #include <asm/arch/mainstone.h> | 42 | #include <asm/arch/mainstone.h> |
| @@ -831,6 +832,11 @@ static int pxa_irda_probe(struct platform_device *pdev) | |||
| 831 | if (err) | 832 | if (err) |
| 832 | goto err_mem_5; | 833 | goto err_mem_5; |
| 833 | 834 | ||
| 835 | if (si->pdata->startup) | ||
| 836 | err = si->pdata->startup(si->dev); | ||
| 837 | if (err) | ||
| 838 | goto err_startup; | ||
| 839 | |||
| 834 | dev->hard_start_xmit = pxa_irda_hard_xmit; | 840 | dev->hard_start_xmit = pxa_irda_hard_xmit; |
| 835 | dev->open = pxa_irda_start; | 841 | dev->open = pxa_irda_start; |
| 836 | dev->stop = pxa_irda_stop; | 842 | dev->stop = pxa_irda_stop; |
| @@ -856,6 +862,9 @@ static int pxa_irda_probe(struct platform_device *pdev) | |||
| 856 | dev_set_drvdata(&pdev->dev, dev); | 862 | dev_set_drvdata(&pdev->dev, dev); |
| 857 | 863 | ||
| 858 | if (err) { | 864 | if (err) { |
| 865 | if (si->pdata->shutdown) | ||
| 866 | si->pdata->shutdown(si->dev); | ||
| 867 | err_startup: | ||
| 859 | kfree(si->tx_buff.head); | 868 | kfree(si->tx_buff.head); |
| 860 | err_mem_5: | 869 | err_mem_5: |
| 861 | kfree(si->rx_buff.head); | 870 | kfree(si->rx_buff.head); |
| @@ -881,6 +890,8 @@ static int pxa_irda_remove(struct platform_device *_dev) | |||
| 881 | if (dev) { | 890 | if (dev) { |
| 882 | struct pxa_irda *si = netdev_priv(dev); | 891 | struct pxa_irda *si = netdev_priv(dev); |
| 883 | unregister_netdev(dev); | 892 | unregister_netdev(dev); |
| 893 | if (si->pdata->shutdown) | ||
| 894 | si->pdata->shutdown(si->dev); | ||
| 884 | kfree(si->tx_buff.head); | 895 | kfree(si->tx_buff.head); |
| 885 | kfree(si->rx_buff.head); | 896 | kfree(si->rx_buff.head); |
| 886 | clk_put(si->fir_clk); | 897 | clk_put(si->fir_clk); |
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 125e7b7f34ff..f7cb8e0758b4 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c | |||
| @@ -486,12 +486,7 @@ void __ref pci_bus_size_bridges(struct pci_bus *bus) | |||
| 486 | break; | 486 | break; |
| 487 | 487 | ||
| 488 | case PCI_CLASS_BRIDGE_PCI: | 488 | case PCI_CLASS_BRIDGE_PCI: |
| 489 | /* don't size subtractive decoding (transparent) | ||
| 490 | * PCI-to-PCI bridges */ | ||
| 491 | if (bus->self->transparent) | ||
| 492 | break; | ||
| 493 | pci_bridge_check_ranges(bus); | 489 | pci_bridge_check_ranges(bus); |
| 494 | /* fall through */ | ||
| 495 | default: | 490 | default: |
| 496 | pbus_size_io(bus); | 491 | pbus_size_io(bus); |
| 497 | /* If the bridge supports prefetchable range, size it | 492 | /* If the bridge supports prefetchable range, size it |
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 8b22281b087f..ed8c06904807 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig | |||
| @@ -200,6 +200,7 @@ config PCMCIA_AU1X00 | |||
| 200 | config PCMCIA_SA1100 | 200 | config PCMCIA_SA1100 |
| 201 | tristate "SA1100 support" | 201 | tristate "SA1100 support" |
| 202 | depends on ARM && ARCH_SA1100 && PCMCIA | 202 | depends on ARM && ARCH_SA1100 && PCMCIA |
| 203 | depends on ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL || MACH_ARMCORE | ||
| 203 | help | 204 | help |
| 204 | Say Y here to include support for SA11x0-based PCMCIA or CF | 205 | Say Y here to include support for SA11x0-based PCMCIA or CF |
| 205 | sockets, found on HP iPAQs, Yopy, and other StrongARM(R)/ | 206 | sockets, found on HP iPAQs, Yopy, and other StrongARM(R)/ |
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c index fbf2f3a6984c..e7ab060ff118 100644 --- a/drivers/pcmcia/pxa2xx_cm_x270.c +++ b/drivers/pcmcia/pxa2xx_cm_x270.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <asm/hardware.h> | 20 | #include <asm/hardware.h> |
| 21 | 21 | ||
| 22 | #include <asm/arch/pxa-regs.h> | 22 | #include <asm/arch/pxa-regs.h> |
| 23 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 23 | #include <asm/arch/cm-x270.h> | 24 | #include <asm/arch/cm-x270.h> |
| 24 | 25 | ||
| 25 | #include "soc_common.h" | 26 | #include "soc_common.h" |
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 56af1f566a4c..cf29a2d0ba4c 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
| @@ -166,15 +166,6 @@ | |||
| 166 | #define SERIAL_IMX_MAJOR 204 | 166 | #define SERIAL_IMX_MAJOR 204 |
| 167 | #define MINOR_START 41 | 167 | #define MINOR_START 41 |
| 168 | 168 | ||
| 169 | #define NR_PORTS 2 | ||
| 170 | |||
| 171 | #define IMX_ISR_PASS_LIMIT 256 | ||
| 172 | |||
| 173 | /* | ||
| 174 | * This is the size of our serial port register set. | ||
| 175 | */ | ||
| 176 | #define UART_PORT_SIZE 0x100 | ||
| 177 | |||
| 178 | /* | 169 | /* |
| 179 | * This determines how often we check the modem status signals | 170 | * This determines how often we check the modem status signals |
| 180 | * for any change. They generally aren't connected to an IRQ | 171 | * for any change. They generally aren't connected to an IRQ |
| @@ -358,66 +349,60 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) | |||
| 358 | struct tty_struct *tty = sport->port.info->tty; | 349 | struct tty_struct *tty = sport->port.info->tty; |
| 359 | unsigned long flags, temp; | 350 | unsigned long flags, temp; |
| 360 | 351 | ||
| 361 | rx = readl(sport->port.membase + URXD0); | ||
| 362 | spin_lock_irqsave(&sport->port.lock,flags); | 352 | spin_lock_irqsave(&sport->port.lock,flags); |
| 363 | 353 | ||
| 364 | do { | 354 | while (readl(sport->port.membase + USR2) & USR2_RDR) { |
| 365 | flg = TTY_NORMAL; | 355 | flg = TTY_NORMAL; |
| 366 | sport->port.icount.rx++; | 356 | sport->port.icount.rx++; |
| 367 | 357 | ||
| 358 | rx = readl(sport->port.membase + URXD0); | ||
| 359 | |||
| 368 | temp = readl(sport->port.membase + USR2); | 360 | temp = readl(sport->port.membase + USR2); |
| 369 | if( temp & USR2_BRCD ) { | 361 | if (temp & USR2_BRCD) { |
| 370 | writel(temp | USR2_BRCD, sport->port.membase + USR2); | 362 | writel(temp | USR2_BRCD, sport->port.membase + USR2); |
| 371 | if(uart_handle_break(&sport->port)) | 363 | if (uart_handle_break(&sport->port)) |
| 372 | goto ignore_char; | 364 | continue; |
| 373 | } | 365 | } |
| 374 | 366 | ||
| 375 | if (uart_handle_sysrq_char | 367 | if (uart_handle_sysrq_char |
| 376 | (&sport->port, (unsigned char)rx)) | 368 | (&sport->port, (unsigned char)rx)) |
| 377 | goto ignore_char; | 369 | continue; |
| 370 | |||
| 371 | if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) { | ||
| 372 | if (rx & URXD_PRERR) | ||
| 373 | sport->port.icount.parity++; | ||
| 374 | else if (rx & URXD_FRMERR) | ||
| 375 | sport->port.icount.frame++; | ||
| 376 | if (rx & URXD_OVRRUN) | ||
| 377 | sport->port.icount.overrun++; | ||
| 378 | |||
| 379 | if (rx & sport->port.ignore_status_mask) { | ||
| 380 | if (++ignored > 100) | ||
| 381 | goto out; | ||
| 382 | continue; | ||
| 383 | } | ||
| 384 | |||
| 385 | rx &= sport->port.read_status_mask; | ||
| 386 | |||
| 387 | if (rx & URXD_PRERR) | ||
| 388 | flg = TTY_PARITY; | ||
| 389 | else if (rx & URXD_FRMERR) | ||
| 390 | flg = TTY_FRAME; | ||
| 391 | if (rx & URXD_OVRRUN) | ||
| 392 | flg = TTY_OVERRUN; | ||
| 378 | 393 | ||
| 379 | if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) | 394 | #ifdef SUPPORT_SYSRQ |
| 380 | goto handle_error; | 395 | sport->port.sysrq = 0; |
| 396 | #endif | ||
| 397 | } | ||
| 381 | 398 | ||
| 382 | error_return: | ||
| 383 | tty_insert_flip_char(tty, rx, flg); | 399 | tty_insert_flip_char(tty, rx, flg); |
| 384 | 400 | } | |
| 385 | ignore_char: | ||
| 386 | rx = readl(sport->port.membase + URXD0); | ||
| 387 | } while(rx & URXD_CHARRDY); | ||
| 388 | 401 | ||
| 389 | out: | 402 | out: |
| 390 | spin_unlock_irqrestore(&sport->port.lock,flags); | 403 | spin_unlock_irqrestore(&sport->port.lock,flags); |
| 391 | tty_flip_buffer_push(tty); | 404 | tty_flip_buffer_push(tty); |
| 392 | return IRQ_HANDLED; | 405 | return IRQ_HANDLED; |
| 393 | |||
| 394 | handle_error: | ||
| 395 | if (rx & URXD_PRERR) | ||
| 396 | sport->port.icount.parity++; | ||
| 397 | else if (rx & URXD_FRMERR) | ||
| 398 | sport->port.icount.frame++; | ||
| 399 | if (rx & URXD_OVRRUN) | ||
| 400 | sport->port.icount.overrun++; | ||
| 401 | |||
| 402 | if (rx & sport->port.ignore_status_mask) { | ||
| 403 | if (++ignored > 100) | ||
| 404 | goto out; | ||
| 405 | goto ignore_char; | ||
| 406 | } | ||
| 407 | |||
| 408 | rx &= sport->port.read_status_mask; | ||
| 409 | |||
| 410 | if (rx & URXD_PRERR) | ||
| 411 | flg = TTY_PARITY; | ||
| 412 | else if (rx & URXD_FRMERR) | ||
| 413 | flg = TTY_FRAME; | ||
| 414 | if (rx & URXD_OVRRUN) | ||
| 415 | flg = TTY_OVERRUN; | ||
| 416 | |||
| 417 | #ifdef SUPPORT_SYSRQ | ||
| 418 | sport->port.sysrq = 0; | ||
| 419 | #endif | ||
| 420 | goto error_return; | ||
| 421 | } | 406 | } |
| 422 | 407 | ||
| 423 | /* | 408 | /* |
| @@ -546,7 +531,7 @@ static int imx_startup(struct uart_port *port) | |||
| 546 | writel(USR1_RTSD, sport->port.membase + USR1); | 531 | writel(USR1_RTSD, sport->port.membase + USR1); |
| 547 | 532 | ||
| 548 | temp = readl(sport->port.membase + UCR1); | 533 | temp = readl(sport->port.membase + UCR1); |
| 549 | temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); | 534 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; |
| 550 | writel(temp, sport->port.membase + UCR1); | 535 | writel(temp, sport->port.membase + UCR1); |
| 551 | 536 | ||
| 552 | temp = readl(sport->port.membase + UCR2); | 537 | temp = readl(sport->port.membase + UCR2); |
| @@ -731,9 +716,11 @@ static const char *imx_type(struct uart_port *port) | |||
| 731 | */ | 716 | */ |
| 732 | static void imx_release_port(struct uart_port *port) | 717 | static void imx_release_port(struct uart_port *port) |
| 733 | { | 718 | { |
| 734 | struct imx_port *sport = (struct imx_port *)port; | 719 | struct platform_device *pdev = to_platform_device(port->dev); |
| 720 | struct resource *mmres; | ||
| 735 | 721 | ||
| 736 | release_mem_region(sport->port.mapbase, UART_PORT_SIZE); | 722 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 723 | release_mem_region(mmres->start, mmres->end - mmres->start + 1); | ||
| 737 | } | 724 | } |
| 738 | 725 | ||
| 739 | /* | 726 | /* |
| @@ -741,10 +728,18 @@ static void imx_release_port(struct uart_port *port) | |||
| 741 | */ | 728 | */ |
| 742 | static int imx_request_port(struct uart_port *port) | 729 | static int imx_request_port(struct uart_port *port) |
| 743 | { | 730 | { |
| 744 | struct imx_port *sport = (struct imx_port *)port; | 731 | struct platform_device *pdev = to_platform_device(port->dev); |
| 732 | struct resource *mmres; | ||
| 733 | void *ret; | ||
| 734 | |||
| 735 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 736 | if (!mmres) | ||
| 737 | return -ENODEV; | ||
| 738 | |||
| 739 | ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1, | ||
| 740 | "imx-uart"); | ||
| 745 | 741 | ||
| 746 | return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, | 742 | return ret ? 0 : -EBUSY; |
| 747 | "imx-uart") != NULL ? 0 : -EBUSY; | ||
| 748 | } | 743 | } |
| 749 | 744 | ||
| 750 | /* | 745 | /* |
| @@ -815,7 +810,7 @@ static struct imx_port imx_ports[] = { | |||
| 815 | .type = PORT_IMX, | 810 | .type = PORT_IMX, |
| 816 | .iotype = UPIO_MEM, | 811 | .iotype = UPIO_MEM, |
| 817 | .membase = (void *)IMX_UART1_BASE, | 812 | .membase = (void *)IMX_UART1_BASE, |
| 818 | .mapbase = IMX_UART1_BASE, /* FIXME */ | 813 | .mapbase = 0x00206000, |
| 819 | .irq = UART1_MINT_RX, | 814 | .irq = UART1_MINT_RX, |
| 820 | .uartclk = 16000000, | 815 | .uartclk = 16000000, |
| 821 | .fifosize = 32, | 816 | .fifosize = 32, |
| @@ -831,7 +826,7 @@ static struct imx_port imx_ports[] = { | |||
| 831 | .type = PORT_IMX, | 826 | .type = PORT_IMX, |
| 832 | .iotype = UPIO_MEM, | 827 | .iotype = UPIO_MEM, |
| 833 | .membase = (void *)IMX_UART2_BASE, | 828 | .membase = (void *)IMX_UART2_BASE, |
| 834 | .mapbase = IMX_UART2_BASE, /* FIXME */ | 829 | .mapbase = 0x00207000, |
| 835 | .irq = UART2_MINT_RX, | 830 | .irq = UART2_MINT_RX, |
| 836 | .uartclk = 16000000, | 831 | .uartclk = 16000000, |
| 837 | .fifosize = 32, | 832 | .fifosize = 32, |
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 46ee7f4c0912..85074cb36f38 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c | |||
| @@ -1033,7 +1033,7 @@ MODULE_LICENSE ("GPL"); | |||
| 1033 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | 1033 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver |
| 1034 | #endif | 1034 | #endif |
| 1035 | 1035 | ||
| 1036 | #ifdef CONFIG_ARCH_ORION | 1036 | #ifdef CONFIG_PLAT_ORION |
| 1037 | #include "ehci-orion.c" | 1037 | #include "ehci-orion.c" |
| 1038 | #define PLATFORM_DRIVER ehci_orion_driver | 1038 | #define PLATFORM_DRIVER ehci_orion_driver |
| 1039 | #endif | 1039 | #endif |
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index e129981f139f..d187d0313742 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c | |||
| @@ -11,15 +11,18 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <asm/arch/orion.h> | 14 | #include <linux/mbus.h> |
| 15 | #include <asm/plat-orion/ehci-orion.h> | ||
| 15 | 16 | ||
| 16 | #define rdl(off) __raw_readl(hcd->regs + (off)) | 17 | #define rdl(off) __raw_readl(hcd->regs + (off)) |
| 17 | #define wrl(off, val) __raw_writel((val), hcd->regs + (off)) | 18 | #define wrl(off, val) __raw_writel((val), hcd->regs + (off)) |
| 18 | 19 | ||
| 19 | #define USB_CAUSE 0x310 | ||
| 20 | #define USB_MASK 0x314 | ||
| 21 | #define USB_CMD 0x140 | 20 | #define USB_CMD 0x140 |
| 22 | #define USB_MODE 0x1a8 | 21 | #define USB_MODE 0x1a8 |
| 22 | #define USB_CAUSE 0x310 | ||
| 23 | #define USB_MASK 0x314 | ||
| 24 | #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) | ||
| 25 | #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) | ||
| 23 | #define USB_IPG 0x360 | 26 | #define USB_IPG 0x360 |
| 24 | #define USB_PHY_PWR_CTRL 0x400 | 27 | #define USB_PHY_PWR_CTRL 0x400 |
| 25 | #define USB_PHY_TX_CTRL 0x420 | 28 | #define USB_PHY_TX_CTRL 0x420 |
| @@ -162,8 +165,30 @@ static const struct hc_driver ehci_orion_hc_driver = { | |||
| 162 | .bus_resume = ehci_bus_resume, | 165 | .bus_resume = ehci_bus_resume, |
| 163 | }; | 166 | }; |
| 164 | 167 | ||
| 168 | static void __init | ||
| 169 | ehci_orion_conf_mbus_windows(struct usb_hcd *hcd, | ||
| 170 | struct mbus_dram_target_info *dram) | ||
| 171 | { | ||
| 172 | int i; | ||
| 173 | |||
| 174 | for (i = 0; i < 4; i++) { | ||
| 175 | wrl(USB_WINDOW_CTRL(i), 0); | ||
| 176 | wrl(USB_WINDOW_BASE(i), 0); | ||
| 177 | } | ||
| 178 | |||
| 179 | for (i = 0; i < dram->num_cs; i++) { | ||
| 180 | struct mbus_dram_window *cs = dram->cs + i; | ||
| 181 | |||
| 182 | wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | | ||
| 183 | (cs->mbus_attr << 8) | | ||
| 184 | (dram->mbus_dram_target_id << 4) | 1); | ||
| 185 | wrl(USB_WINDOW_BASE(i), cs->base); | ||
| 186 | } | ||
| 187 | } | ||
| 188 | |||
| 165 | static int __init ehci_orion_drv_probe(struct platform_device *pdev) | 189 | static int __init ehci_orion_drv_probe(struct platform_device *pdev) |
| 166 | { | 190 | { |
| 191 | struct orion_ehci_data *pd = pdev->dev.platform_data; | ||
| 167 | struct resource *res; | 192 | struct resource *res; |
| 168 | struct usb_hcd *hcd; | 193 | struct usb_hcd *hcd; |
| 169 | struct ehci_hcd *ehci; | 194 | struct ehci_hcd *ehci; |
| @@ -227,6 +252,12 @@ static int __init ehci_orion_drv_probe(struct platform_device *pdev) | |||
| 227 | ehci->sbrn = 0x20; | 252 | ehci->sbrn = 0x20; |
| 228 | 253 | ||
| 229 | /* | 254 | /* |
| 255 | * (Re-)program MBUS remapping windows if we are asked to. | ||
| 256 | */ | ||
| 257 | if (pd != NULL && pd->dram != NULL) | ||
| 258 | ehci_orion_conf_mbus_windows(hcd, pd->dram); | ||
| 259 | |||
| 260 | /* | ||
| 230 | * setup Orion USB controller | 261 | * setup Orion USB controller |
| 231 | */ | 262 | */ |
| 232 | orion_usb_setup(hcd); | 263 | orion_usb_setup(hcd); |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 97facb121c73..757651954e6c 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | #include <asm/irq.h> | 45 | #include <asm/irq.h> |
| 46 | #include <asm/div64.h> | 46 | #include <asm/div64.h> |
| 47 | #include <asm/arch/pxa-regs.h> | 47 | #include <asm/arch/pxa-regs.h> |
| 48 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 48 | #include <asm/arch/bitfield.h> | 49 | #include <asm/arch/bitfield.h> |
| 49 | #include <asm/arch/pxafb.h> | 50 | #include <asm/arch/pxafb.h> |
| 50 | 51 | ||
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h index 9b1864bbd9a8..186e7c715f8a 100644 --- a/include/asm-arm/arch-ep93xx/gpio.h +++ b/include/asm-arm/arch-ep93xx/gpio.h | |||
| @@ -101,30 +101,17 @@ | |||
| 101 | 101 | ||
| 102 | /* new generic GPIO API - see Documentation/gpio.txt */ | 102 | /* new generic GPIO API - see Documentation/gpio.txt */ |
| 103 | 103 | ||
| 104 | static inline int gpio_request(unsigned gpio, const char *label) | 104 | #include <asm-generic/gpio.h> |
| 105 | { | ||
| 106 | if (gpio > EP93XX_GPIO_LINE_MAX) | ||
| 107 | return -EINVAL; | ||
| 108 | return 0; | ||
| 109 | } | ||
| 110 | 105 | ||
| 111 | static inline void gpio_free(unsigned gpio) | 106 | #define gpio_get_value __gpio_get_value |
| 112 | { | 107 | #define gpio_set_value __gpio_set_value |
| 113 | } | 108 | #define gpio_cansleep __gpio_cansleep |
| 114 | |||
| 115 | int gpio_direction_input(unsigned gpio); | ||
| 116 | int gpio_direction_output(unsigned gpio, int value); | ||
| 117 | int gpio_get_value(unsigned gpio); | ||
| 118 | void gpio_set_value(unsigned gpio, int value); | ||
| 119 | |||
| 120 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 121 | 109 | ||
| 122 | /* | 110 | /* |
| 123 | * Map GPIO A0..A7 (0..7) to irq 64..71, | 111 | * Map GPIO A0..A7 (0..7) to irq 64..71, |
| 124 | * B0..B7 (7..15) to irq 72..79, and | 112 | * B0..B7 (7..15) to irq 72..79, and |
| 125 | * F0..F7 (16..24) to irq 80..87. | 113 | * F0..F7 (16..24) to irq 80..87. |
| 126 | */ | 114 | */ |
| 127 | |||
| 128 | static inline int gpio_to_irq(unsigned gpio) | 115 | static inline int gpio_to_irq(unsigned gpio) |
| 129 | { | 116 | { |
| 130 | if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ) | 117 | if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ) |
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h index b0364dce463f..7ad2c656e162 100644 --- a/include/asm-arm/arch-ks8695/devices.h +++ b/include/asm-arm/arch-ks8695/devices.h | |||
| @@ -18,6 +18,11 @@ extern void __init ks8695_add_device_wan(void); | |||
| 18 | extern void __init ks8695_add_device_lan(void); | 18 | extern void __init ks8695_add_device_lan(void); |
| 19 | extern void __init ks8695_add_device_hpna(void); | 19 | extern void __init ks8695_add_device_hpna(void); |
| 20 | 20 | ||
| 21 | /* LEDs */ | ||
| 22 | extern short ks8695_leds_cpu; | ||
| 23 | extern short ks8695_leds_timer; | ||
| 24 | extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led); | ||
| 25 | |||
| 21 | /* PCI */ | 26 | /* PCI */ |
| 22 | #define KS8695_MODE_PCI 0 | 27 | #define KS8695_MODE_PCI 0 |
| 23 | #define KS8695_MODE_MINIPCI 1 | 28 | #define KS8695_MODE_MINIPCI 1 |
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h index be29b83ad4ae..8590127760a8 100644 --- a/include/asm-arm/arch-mxc/board-mx31ads.h +++ b/include/asm-arm/arch-mxc/board-mx31ads.h | |||
| @@ -11,107 +11,77 @@ | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 13 | 13 | ||
| 14 | /*! | 14 | /* Base address of PBC controller */ |
| 15 | * @name PBC Controller parameters | ||
| 16 | */ | ||
| 17 | /*! @{ */ | ||
| 18 | /*! | ||
| 19 | * Base address of PBC controller | ||
| 20 | */ | ||
| 21 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) | 15 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) |
| 22 | /* Offsets for the PBC Controller register */ | 16 | /* Offsets for the PBC Controller register */ |
| 23 | /*! | 17 | |
| 24 | * PBC Board status register offset | 18 | /* PBC Board status register offset */ |
| 25 | */ | ||
| 26 | #define PBC_BSTAT 0x000002 | 19 | #define PBC_BSTAT 0x000002 |
| 27 | /*! | 20 | |
| 28 | * PBC Board control register 1 set address. | 21 | /* PBC Board control register 1 set address */ |
| 29 | */ | ||
| 30 | #define PBC_BCTRL1_SET 0x000004 | 22 | #define PBC_BCTRL1_SET 0x000004 |
| 31 | /*! | 23 | |
| 32 | * PBC Board control register 1 clear address. | 24 | /* PBC Board control register 1 clear address */ |
| 33 | */ | ||
| 34 | #define PBC_BCTRL1_CLEAR 0x000006 | 25 | #define PBC_BCTRL1_CLEAR 0x000006 |
| 35 | /*! | 26 | |
| 36 | * PBC Board control register 2 set address. | 27 | /* PBC Board control register 2 set address */ |
| 37 | */ | ||
| 38 | #define PBC_BCTRL2_SET 0x000008 | 28 | #define PBC_BCTRL2_SET 0x000008 |
| 39 | /*! | 29 | |
| 40 | * PBC Board control register 2 clear address. | 30 | /* PBC Board control register 2 clear address */ |
| 41 | */ | ||
| 42 | #define PBC_BCTRL2_CLEAR 0x00000A | 31 | #define PBC_BCTRL2_CLEAR 0x00000A |
| 43 | /*! | 32 | |
| 44 | * PBC Board control register 3 set address. | 33 | /* PBC Board control register 3 set address */ |
| 45 | */ | ||
| 46 | #define PBC_BCTRL3_SET 0x00000C | 34 | #define PBC_BCTRL3_SET 0x00000C |
| 47 | /*! | 35 | |
| 48 | * PBC Board control register 3 clear address. | 36 | /* PBC Board control register 3 clear address */ |
| 49 | */ | ||
| 50 | #define PBC_BCTRL3_CLEAR 0x00000E | 37 | #define PBC_BCTRL3_CLEAR 0x00000E |
| 51 | /*! | 38 | |
| 52 | * PBC Board control register 4 set address. | 39 | /* PBC Board control register 4 set address */ |
| 53 | */ | ||
| 54 | #define PBC_BCTRL4_SET 0x000010 | 40 | #define PBC_BCTRL4_SET 0x000010 |
| 55 | /*! | 41 | |
| 56 | * PBC Board control register 4 clear address. | 42 | /* PBC Board control register 4 clear address */ |
| 57 | */ | ||
| 58 | #define PBC_BCTRL4_CLEAR 0x000012 | 43 | #define PBC_BCTRL4_CLEAR 0x000012 |
| 59 | /*! | 44 | |
| 60 | * PBC Board status register 1. | 45 | /* PBC Board status register 1 */ |
| 61 | */ | ||
| 62 | #define PBC_BSTAT1 0x000014 | 46 | #define PBC_BSTAT1 0x000014 |
| 63 | /*! | 47 | |
| 64 | * PBC Board interrupt status register. | 48 | /* PBC Board interrupt status register */ |
| 65 | */ | ||
| 66 | #define PBC_INTSTATUS 0x000016 | 49 | #define PBC_INTSTATUS 0x000016 |
| 67 | /*! | 50 | |
| 68 | * PBC Board interrupt current status register. | 51 | /* PBC Board interrupt current status register */ |
| 69 | */ | ||
| 70 | #define PBC_INTCURR_STATUS 0x000018 | 52 | #define PBC_INTCURR_STATUS 0x000018 |
| 71 | /*! | 53 | |
| 72 | * PBC Interrupt mask register set address. | 54 | /* PBC Interrupt mask register set address */ |
| 73 | */ | ||
| 74 | #define PBC_INTMASK_SET 0x00001A | 55 | #define PBC_INTMASK_SET 0x00001A |
| 75 | /*! | 56 | |
| 76 | * PBC Interrupt mask register clear address. | 57 | /* PBC Interrupt mask register clear address */ |
| 77 | */ | ||
| 78 | #define PBC_INTMASK_CLEAR 0x00001C | 58 | #define PBC_INTMASK_CLEAR 0x00001C |
| 79 | 59 | ||
| 80 | /*! | 60 | /* External UART A */ |
| 81 | * External UART A. | ||
| 82 | */ | ||
| 83 | #define PBC_SC16C652_UARTA 0x010000 | 61 | #define PBC_SC16C652_UARTA 0x010000 |
| 84 | /*! | 62 | |
| 85 | * External UART B. | 63 | /* External UART B */ |
| 86 | */ | ||
| 87 | #define PBC_SC16C652_UARTB 0x010010 | 64 | #define PBC_SC16C652_UARTB 0x010010 |
| 88 | /*! | 65 | |
| 89 | * Ethernet Controller IO base address. | 66 | /* Ethernet Controller IO base address */ |
| 90 | */ | ||
| 91 | #define PBC_CS8900A_IOBASE 0x020000 | 67 | #define PBC_CS8900A_IOBASE 0x020000 |
| 92 | /*! | 68 | |
| 93 | * Ethernet Controller Memory base address. | 69 | /* Ethernet Controller Memory base address */ |
| 94 | */ | ||
| 95 | #define PBC_CS8900A_MEMBASE 0x021000 | 70 | #define PBC_CS8900A_MEMBASE 0x021000 |
| 96 | /*! | 71 | |
| 97 | * Ethernet Controller DMA base address. | 72 | /* Ethernet Controller DMA base address */ |
| 98 | */ | ||
| 99 | #define PBC_CS8900A_DMABASE 0x022000 | 73 | #define PBC_CS8900A_DMABASE 0x022000 |
| 100 | /*! | 74 | |
| 101 | * External chip select 0. | 75 | /* External chip select 0 */ |
| 102 | */ | ||
| 103 | #define PBC_XCS0 0x040000 | 76 | #define PBC_XCS0 0x040000 |
| 104 | /*! | 77 | |
| 105 | * LCD Display enable. | 78 | /* LCD Display enable */ |
| 106 | */ | ||
| 107 | #define PBC_LCD_EN_B 0x060000 | 79 | #define PBC_LCD_EN_B 0x060000 |
| 108 | /*! | 80 | |
| 109 | * Code test debug enable. | 81 | /* Code test debug enable */ |
| 110 | */ | ||
| 111 | #define PBC_CODE_B 0x070000 | 82 | #define PBC_CODE_B 0x070000 |
| 112 | /*! | 83 | |
| 113 | * PSRAM memory select. | 84 | /* PSRAM memory select */ |
| 114 | */ | ||
| 115 | #define PBC_PSRAM_B 0x5000000 | 85 | #define PBC_PSRAM_B 0x5000000 |
| 116 | 86 | ||
| 117 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) | 87 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) |
| @@ -139,4 +109,4 @@ | |||
| 139 | 109 | ||
| 140 | #define MXC_MAX_EXP_IO_LINES 16 | 110 | #define MXC_MAX_EXP_IO_LINES 16 |
| 141 | 111 | ||
| 142 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ | 112 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ |
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h index 65e639d51d2b..c822d569a05e 100644 --- a/include/asm-arm/arch-mxc/dma.h +++ b/include/asm-arm/arch-mxc/dma.h | |||
| @@ -11,11 +11,4 @@ | |||
| 11 | #ifndef __ASM_ARCH_MXC_DMA_H__ | 11 | #ifndef __ASM_ARCH_MXC_DMA_H__ |
| 12 | #define __ASM_ARCH_MXC_DMA_H__ | 12 | #define __ASM_ARCH_MXC_DMA_H__ |
| 13 | 13 | ||
| 14 | /*! | ||
| 15 | * @file dma.h | ||
| 16 | * @brief This file contains Unified DMA API for all MXC platforms. | ||
| 17 | * The API is platform independent. | ||
| 18 | * | ||
| 19 | * @ingroup SDMA | ||
| 20 | */ | ||
| 21 | #endif | 14 | #endif |
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h index 3c09b92fef0d..e87ff0679d5e 100644 --- a/include/asm-arm/arch-mxc/hardware.h +++ b/include/asm-arm/arch-mxc/hardware.h | |||
| @@ -8,45 +8,24 @@ | |||
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /*! | ||
| 12 | * @file hardware.h | ||
| 13 | * @brief This file contains the hardware definitions of the board. | ||
| 14 | * | ||
| 15 | * @ingroup System | ||
| 16 | */ | ||
| 17 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | 11 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ |
| 18 | #define __ASM_ARCH_MXC_HARDWARE_H__ | 12 | #define __ASM_ARCH_MXC_HARDWARE_H__ |
| 19 | 13 | ||
| 20 | #include <asm/sizes.h> | 14 | #include <asm/sizes.h> |
| 21 | 15 | ||
| 22 | #include <asm/arch/mx31.h> | 16 | #ifdef CONFIG_ARCH_MX3 |
| 17 | # include <asm/arch/mx31.h> | ||
| 18 | #endif | ||
| 23 | 19 | ||
| 24 | #include <asm/arch/mxc.h> | 20 | #include <asm/arch/mxc.h> |
| 25 | 21 | ||
| 26 | #define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) | ||
| 27 | |||
| 28 | /* | 22 | /* |
| 29 | * --------------------------------------------------------------------------- | 23 | * --------------------------------------------------------------------------- |
| 30 | * Board specific defines | 24 | * Board specific defines |
| 31 | * --------------------------------------------------------------------------- | 25 | * --------------------------------------------------------------------------- |
| 32 | */ | 26 | */ |
| 33 | #define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES) | 27 | #ifdef CONFIG_MACH_MX31ADS |
| 34 | 28 | # include <asm/arch/board-mx31ads.h> | |
| 35 | #include <asm/arch/board-mx31ads.h> | ||
| 36 | |||
| 37 | #ifndef MXC_MAX_EXP_IO_LINES | ||
| 38 | #define MXC_MAX_EXP_IO_LINES 0 | ||
| 39 | #endif | 29 | #endif |
| 40 | 30 | ||
| 41 | #define MXC_MAX_VIRTUAL_INTS 16 | 31 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ |
| 42 | #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) | ||
| 43 | #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE | ||
| 44 | #define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) | ||
| 45 | #define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) | ||
| 46 | |||
| 47 | #define MXC_MAX_INTS (MXC_MAX_INT_LINES + \ | ||
| 48 | MXC_MAX_GPIO_LINES + \ | ||
| 49 | MXC_MAX_EXP_IO_LINES + \ | ||
| 50 | MXC_MAX_VIRTUAL_INTS) | ||
| 51 | |||
| 52 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h index cf6c83a4b9f7..65b6810124c1 100644 --- a/include/asm-arm/arch-mxc/io.h +++ b/include/asm-arm/arch-mxc/io.h | |||
| @@ -8,24 +8,13 @@ | |||
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /*! | ||
| 12 | * @file io.h | ||
| 13 | * @brief This file contains some memory mapping macros. | ||
| 14 | * @note There is no real ISA or PCI buses. But have to define these macros | ||
| 15 | * for some drivers to compile. | ||
| 16 | * | ||
| 17 | * @ingroup System | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_IO_H__ | 11 | #ifndef __ASM_ARCH_MXC_IO_H__ |
| 21 | #define __ASM_ARCH_MXC_IO_H__ | 12 | #define __ASM_ARCH_MXC_IO_H__ |
| 22 | 13 | ||
| 23 | /*! Allow IO space to be anywhere in the memory */ | 14 | /* Allow IO space to be anywhere in the memory */ |
| 24 | #define IO_SPACE_LIMIT 0xffffffff | 15 | #define IO_SPACE_LIMIT 0xffffffff |
| 25 | 16 | ||
| 26 | /*! | 17 | /* io address mapping macro */ |
| 27 | * io address mapping macro | ||
| 28 | */ | ||
| 29 | #define __io(a) ((void __iomem *)(a)) | 18 | #define __io(a) ((void __iomem *)(a)) |
| 30 | 19 | ||
| 31 | #define __mem_pci(a) (a) | 20 | #define __mem_pci(a) (a) |
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h index e4686c6bc4bf..b2c5205e1962 100644 --- a/include/asm-arm/arch-mxc/irqs.h +++ b/include/asm-arm/arch-mxc/irqs.h | |||
| @@ -13,26 +13,17 @@ | |||
| 13 | 13 | ||
| 14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
| 15 | 15 | ||
| 16 | /*! | ||
| 17 | * @file irqs.h | ||
| 18 | * @brief This file defines the number of normal interrupts and fast interrupts | ||
| 19 | * | ||
| 20 | * @ingroup Interrupt | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) | 16 | #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) |
| 24 | 17 | ||
| 25 | #define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE) | 18 | #define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE) |
| 26 | #define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x) | 19 | #define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x) |
| 27 | 20 | ||
| 28 | /*! | 21 | /* Number of normal interrupts */ |
| 29 | * Number of normal interrupts | 22 | #define NR_IRQS (MXC_MAX_INT_LINES + \ |
| 30 | */ | 23 | MXC_MAX_GPIO_LINES + \ |
| 31 | #define NR_IRQS MXC_MAX_INTS | 24 | MXC_MAX_VIRTUAL_INTS) |
| 32 | 25 | ||
| 33 | /*! | 26 | /* Number of fast interrupts */ |
| 34 | * Number of fast interrupts | ||
| 35 | */ | ||
| 36 | #define NR_FIQS MXC_MAX_INTS | 27 | #define NR_FIQS MXC_MAX_INTS |
| 37 | 28 | ||
| 38 | #endif /* __ASM_ARCH_MXC_IRQS_H__ */ | 29 | #endif /* __ASM_ARCH_MXC_IRQS_H__ */ |
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h index c89aac83a407..059f83023a10 100644 --- a/include/asm-arm/arch-mxc/memory.h +++ b/include/asm-arm/arch-mxc/memory.h | |||
| @@ -13,24 +13,17 @@ | |||
| 13 | 13 | ||
| 14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
| 15 | 15 | ||
| 16 | /*! | 16 | /* |
| 17 | * @file memory.h | ||
| 18 | * @brief This file contains macros needed by the Linux kernel and drivers. | ||
| 19 | * | ||
| 20 | * @ingroup Memory | ||
| 21 | */ | ||
| 22 | |||
| 23 | /*! | ||
| 24 | * Virtual view <-> DMA view memory address translations | 17 | * Virtual view <-> DMA view memory address translations |
| 25 | * This macro is used to translate the virtual address to an address | 18 | * This macro is used to translate the virtual address to an address |
| 26 | * suitable to be passed to set_dma_addr() | 19 | * suitable to be passed to set_dma_addr() |
| 27 | */ | 20 | */ |
| 28 | #define __virt_to_bus(a) __virt_to_phys(a) | 21 | #define __virt_to_bus(a) __virt_to_phys(a) |
| 29 | 22 | ||
| 30 | /*! | 23 | /* |
| 31 | * Used to convert an address for DMA operations to an address that the | 24 | * Used to convert an address for DMA operations to an address that the |
| 32 | * kernel can use. | 25 | * kernel can use. |
| 33 | */ | 26 | */ |
| 34 | #define __bus_to_virt(a) __phys_to_virt(a) | 27 | #define __bus_to_virt(a) __phys_to_virt(a) |
| 35 | 28 | ||
| 36 | #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ | 29 | #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ |
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h index 85c49c9e5d15..36a1af495bb3 100644 --- a/include/asm-arm/arch-mxc/mx31.h +++ b/include/asm-arm/arch-mxc/mx31.h | |||
| @@ -317,6 +317,8 @@ | |||
| 317 | #define MXC_MAX_INT_LINES 64 | 317 | #define MXC_MAX_INT_LINES 64 |
| 318 | 318 | ||
| 319 | #define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES | 319 | #define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES |
| 320 | #define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) | ||
| 321 | #define MXC_MAX_VIRTUAL_INTS 16 | ||
| 320 | 322 | ||
| 321 | /*! | 323 | /*! |
| 322 | * Number of GPIO port as defined in the IC Spec | 324 | * Number of GPIO port as defined in the IC Spec |
| @@ -329,7 +331,33 @@ | |||
| 329 | 331 | ||
| 330 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | 332 | #define PROD_SIGNATURE 0x1 /* For MX31 */ |
| 331 | 333 | ||
| 334 | /* silicon revisions specific to i.MX31 */ | ||
| 335 | #define CHIP_REV_1_0 0x10 | ||
| 336 | #define CHIP_REV_1_1 0x11 | ||
| 337 | #define CHIP_REV_1_2 0x12 | ||
| 338 | #define CHIP_REV_1_3 0x13 | ||
| 339 | #define CHIP_REV_2_0 0x20 | ||
| 340 | #define CHIP_REV_2_1 0x21 | ||
| 341 | #define CHIP_REV_2_2 0x22 | ||
| 342 | #define CHIP_REV_2_3 0x23 | ||
| 343 | #define CHIP_REV_3_0 0x30 | ||
| 344 | #define CHIP_REV_3_1 0x31 | ||
| 345 | #define CHIP_REV_3_2 0x32 | ||
| 346 | |||
| 332 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | 347 | #define SYSTEM_REV_MIN CHIP_REV_1_0 |
| 333 | #define SYSTEM_REV_NUM 3 | 348 | #define SYSTEM_REV_NUM 3 |
| 334 | 349 | ||
| 335 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | 350 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 351 | |||
| 352 | /* this is a i.MX31 CPU */ | ||
| 353 | #define cpu_is_mx31() (1) | ||
| 354 | |||
| 355 | extern unsigned int system_rev; | ||
| 356 | |||
| 357 | static inline int mx31_revision(void) | ||
| 358 | { | ||
| 359 | return system_rev; | ||
| 360 | } | ||
| 361 | #endif | ||
| 362 | |||
| 363 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h index 0837f1f9ca31..146d3f60951a 100644 --- a/include/asm-arm/arch-mxc/mxc.h +++ b/include/asm-arm/arch-mxc/mxc.h | |||
| @@ -15,6 +15,11 @@ | |||
| 15 | #error "Do not include directly." | 15 | #error "Do not include directly." |
| 16 | #endif | 16 | #endif |
| 17 | 17 | ||
| 18 | /* clean up all things that are not used */ | ||
| 19 | #ifndef CONFIG_ARCH_MX3 | ||
| 20 | # define cpu_is_mx31() (0) | ||
| 21 | #endif | ||
| 22 | |||
| 18 | /* | 23 | /* |
| 19 | ***************************************** | 24 | ***************************************** |
| 20 | * GPT Register definitions * | 25 | * GPT Register definitions * |
| @@ -31,9 +36,7 @@ | |||
| 31 | #define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20) | 36 | #define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20) |
| 32 | #define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24) | 37 | #define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24) |
| 33 | 38 | ||
| 34 | /*! | 39 | /* GPT Control register bit definitions */ |
| 35 | * GPT Control register bit definitions | ||
| 36 | */ | ||
| 37 | #define GPTCR_FO3 (1 << 31) | 40 | #define GPTCR_FO3 (1 << 31) |
| 38 | #define GPTCR_FO2 (1 << 30) | 41 | #define GPTCR_FO2 (1 << 30) |
| 39 | #define GPTCR_FO1 (1 << 29) | 42 | #define GPTCR_FO1 (1 << 29) |
| @@ -146,4 +149,4 @@ | |||
| 146 | #define IIM_PROD_REV_SH 3 | 149 | #define IIM_PROD_REV_SH 3 |
| 147 | #define IIM_PROD_REV_LEN 5 | 150 | #define IIM_PROD_REV_LEN 5 |
| 148 | 151 | ||
| 149 | #endif /* __ASM_ARCH_MXC_H__ */ | 152 | #endif /* __ASM_ARCH_MXC_H__ */ |
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h index 109956b41aca..bbfc37465fc5 100644 --- a/include/asm-arm/arch-mxc/system.h +++ b/include/asm-arm/arch-mxc/system.h | |||
| @@ -21,30 +21,14 @@ | |||
| 21 | #ifndef __ASM_ARCH_MXC_SYSTEM_H__ | 21 | #ifndef __ASM_ARCH_MXC_SYSTEM_H__ |
| 22 | #define __ASM_ARCH_MXC_SYSTEM_H__ | 22 | #define __ASM_ARCH_MXC_SYSTEM_H__ |
| 23 | 23 | ||
| 24 | /*! | ||
| 25 | * @file system.h | ||
| 26 | * @brief This file contains idle and reset functions. | ||
| 27 | * | ||
| 28 | * @ingroup System | ||
| 29 | */ | ||
| 30 | |||
| 31 | /*! | ||
| 32 | * This function puts the CPU into idle mode. It is called by default_idle() | ||
| 33 | * in process.c file. | ||
| 34 | */ | ||
| 35 | static inline void arch_idle(void) | 24 | static inline void arch_idle(void) |
| 36 | { | 25 | { |
| 37 | cpu_do_idle(); | 26 | cpu_do_idle(); |
| 38 | } | 27 | } |
| 39 | 28 | ||
| 40 | /* | ||
| 41 | * This function resets the system. It is called by machine_restart(). | ||
| 42 | * | ||
| 43 | * @param mode indicates different kinds of resets | ||
| 44 | */ | ||
| 45 | static inline void arch_reset(char mode) | 29 | static inline void arch_reset(char mode) |
| 46 | { | 30 | { |
| 47 | cpu_reset(0); | 31 | cpu_reset(0); |
| 48 | } | 32 | } |
| 49 | 33 | ||
| 50 | #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ | 34 | #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ |
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h index 83a73da895eb..62d97623412f 100644 --- a/include/asm-arm/arch-mxc/vmalloc.h +++ b/include/asm-arm/arch-mxc/vmalloc.h | |||
| @@ -20,17 +20,7 @@ | |||
| 20 | #ifndef __ASM_ARCH_MXC_VMALLOC_H__ | 20 | #ifndef __ASM_ARCH_MXC_VMALLOC_H__ |
| 21 | #define __ASM_ARCH_MXC_VMALLOC_H__ | 21 | #define __ASM_ARCH_MXC_VMALLOC_H__ |
| 22 | 22 | ||
| 23 | /*! | 23 | /* vmalloc ending address */ |
| 24 | * @file vmalloc.h | ||
| 25 | * | ||
| 26 | * @brief This file contains platform specific macros for vmalloc. | ||
| 27 | * | ||
| 28 | * @ingroup System | ||
| 29 | */ | ||
| 30 | |||
| 31 | /*! | ||
| 32 | * vmalloc ending address | ||
| 33 | */ | ||
| 34 | #define VMALLOC_END 0xF4000000 | 24 | #define VMALLOC_END 0xF4000000 |
| 35 | 25 | ||
| 36 | #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ | 26 | #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ |
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h index 716f34fdb716..e57443bdbbd9 100644 --- a/include/asm-arm/arch-ns9xxx/board.h +++ b/include/asm-arm/arch-ns9xxx/board.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-ns9xxx/board.h | 2 | * include/asm-arm/arch-ns9xxx/board.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -13,8 +13,30 @@ | |||
| 13 | 13 | ||
| 14 | #include <asm/mach-types.h> | 14 | #include <asm/mach-types.h> |
| 15 | 15 | ||
| 16 | #define board_is_a9m9750dev() (machine_is_cc9p9360dev()) | 16 | #define board_is_a9m9750dev() (0 \ |
| 17 | || machine_is_cc9p9360dev() \ | ||
| 18 | || machine_is_cc9p9750dev() \ | ||
| 19 | ) | ||
| 17 | 20 | ||
| 18 | #define board_is_jscc9p9360() (machine_is_cc9p9360js()) | 21 | #define board_is_a9mvali() (0 \ |
| 22 | || machine_is_cc9p9360val() \ | ||
| 23 | || machine_is_cc9p9750val() \ | ||
| 24 | ) | ||
| 25 | |||
| 26 | #define board_is_jscc9p9210() (0 \ | ||
| 27 | || machine_is_cc9p9210js() \ | ||
| 28 | ) | ||
| 29 | |||
| 30 | #define board_is_jscc9p9215() (0 \ | ||
| 31 | || machine_is_cc9p9215js() \ | ||
| 32 | ) | ||
| 33 | |||
| 34 | #define board_is_jscc9p9360() (0 \ | ||
| 35 | || machine_is_cc9p9360js() \ | ||
| 36 | ) | ||
| 37 | |||
| 38 | #define board_is_uncbas() (0 \ | ||
| 39 | || machine_is_cc7ucamry() \ | ||
| 40 | ) | ||
| 19 | 41 | ||
| 20 | #endif /* ifndef __ASM_ARCH_BOARD_H */ | 42 | #endif /* ifndef __ASM_ARCH_BOARD_H */ |
diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h deleted file mode 100644 index b943d3a92a1d..000000000000 --- a/include/asm-arm/arch-ns9xxx/clock.h +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/clock.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_CLOCK_H | ||
| 12 | #define __ASM_ARCH_CLOCK_H | ||
| 13 | |||
| 14 | #include <asm/arch-ns9xxx/regs-sys.h> | ||
| 15 | |||
| 16 | #define CRYSTAL 29491200 /* Hz */ | ||
| 17 | |||
| 18 | /* The HRM calls this value f_vco */ | ||
| 19 | static inline u32 ns9xxx_systemclock(void) __attribute__((const)); | ||
| 20 | static inline u32 ns9xxx_systemclock(void) | ||
| 21 | { | ||
| 22 | u32 pll = __raw_readl(SYS_PLL); | ||
| 23 | |||
| 24 | /* | ||
| 25 | * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in | ||
| 26 | * time.c). | ||
| 27 | * | ||
| 28 | * The following values are given: | ||
| 29 | * - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6} | ||
| 30 | * - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2 | ||
| 31 | * - ND in {0 .. 31} | ||
| 32 | * - FS in {0 .. 3} | ||
| 33 | * | ||
| 34 | * Assuming the worst, we consider: | ||
| 35 | * - TIMERCLOCKSELECT == 64 | ||
| 36 | * - ND == 0 | ||
| 37 | * - FS == 3 | ||
| 38 | * | ||
| 39 | * So HZ should be a divisor of: | ||
| 40 | * (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT | ||
| 41 | * == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64 | ||
| 42 | * == 2^8 * 3^2 * 5^2 | ||
| 43 | * == 57600 | ||
| 44 | * | ||
| 45 | * Currently HZ is defined to be 100 for this platform. | ||
| 46 | * | ||
| 47 | * Fine. | ||
| 48 | */ | ||
| 49 | return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) | ||
| 50 | >> REGGETIM(pll, SYS_PLL, FS); | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline u32 ns9xxx_cpuclock(void) __attribute__((const)); | ||
| 54 | static inline u32 ns9xxx_cpuclock(void) | ||
| 55 | { | ||
| 56 | return ns9xxx_systemclock() / 2; | ||
| 57 | } | ||
| 58 | |||
| 59 | static inline u32 ns9xxx_ahbclock(void) __attribute__((const)); | ||
| 60 | static inline u32 ns9xxx_ahbclock(void) | ||
| 61 | { | ||
| 62 | return ns9xxx_systemclock() / 4; | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline u32 ns9xxx_bbusclock(void) __attribute__((const)); | ||
| 66 | static inline u32 ns9xxx_bbusclock(void) | ||
| 67 | { | ||
| 68 | return ns9xxx_systemclock() / 8; | ||
| 69 | } | ||
| 70 | |||
| 71 | #endif /* ifndef __ASM_ARCH_CLOCK_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S b/include/asm-arm/arch-ns9xxx/entry-macro.S index 86aec87303e4..89a21c530468 100644 --- a/include/asm-arm/arch-ns9xxx/entry-macro.S +++ b/include/asm-arm/arch-ns9xxx/entry-macro.S | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-ns9xxx/entry-macro.S | 2 | * include/asm-arm/arch-ns9xxx/entry-macro.S |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -9,16 +9,16 @@ | |||
| 9 | * the Free Software Foundation. | 9 | * the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | #include <asm/hardware.h> | 11 | #include <asm/hardware.h> |
| 12 | #include <asm/arch-ns9xxx/regs-sys.h> | 12 | #include <asm/arch-ns9xxx/regs-sys-common.h> |
| 13 | 13 | ||
| 14 | .macro get_irqnr_preamble, base, tmp | 14 | .macro get_irqnr_preamble, base, tmp |
| 15 | ldr \base, =SYS_ISRADDR | ||
| 15 | .endm | 16 | .endm |
| 16 | 17 | ||
| 17 | .macro arch_ret_to_user, tmp1, tmp2 | 18 | .macro arch_ret_to_user, tmp1, tmp2 |
| 18 | .endm | 19 | .endm |
| 19 | 20 | ||
| 20 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 21 | ldr \base, =SYS_ISRADDR | ||
| 22 | ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] | 22 | ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] |
| 23 | cmp \irqstat, #0 | 23 | cmp \irqstat, #0 |
| 24 | ldrne \irqnr, [\base] | 24 | ldrne \irqnr, [\base] |
diff --git a/include/asm-arm/arch-ns9xxx/irqs.h b/include/asm-arm/arch-ns9xxx/irqs.h index 25d8d28b27f3..e83d48ec42c9 100644 --- a/include/asm-arm/arch-ns9xxx/irqs.h +++ b/include/asm-arm/arch-ns9xxx/irqs.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-ns9xxx/irqs.h | 2 | * include/asm-arm/arch-ns9xxx/irqs.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,38 +11,39 @@ | |||
| 11 | #ifndef __ASM_ARCH_IRQS_H | 11 | #ifndef __ASM_ARCH_IRQS_H |
| 12 | #define __ASM_ARCH_IRQS_H | 12 | #define __ASM_ARCH_IRQS_H |
| 13 | 13 | ||
| 14 | #define IRQ_WATCHDOG 0 | 14 | /* NetSilicon 9360 */ |
| 15 | #define IRQ_AHBBUSERR 1 | 15 | #define IRQ_NS9XXX_WATCHDOG 0 |
| 16 | #define IRQ_BBUSAGG 2 | 16 | #define IRQ_NS9XXX_AHBBUSERR 1 |
| 17 | #define IRQ_NS9360_BBUSAGG 2 | ||
| 17 | /* irq 3 is reserved for NS9360 */ | 18 | /* irq 3 is reserved for NS9360 */ |
| 18 | #define IRQ_ETHRX 4 | 19 | #define IRQ_NS9XXX_ETHRX 4 |
| 19 | #define IRQ_ETHTX 5 | 20 | #define IRQ_NS9XXX_ETHTX 5 |
| 20 | #define IRQ_ETHPHY 6 | 21 | #define IRQ_NS9XXX_ETHPHY 6 |
| 21 | #define IRQ_LCD 7 | 22 | #define IRQ_NS9360_LCD 7 |
| 22 | #define IRQ_SERBRX 8 | 23 | #define IRQ_NS9360_SERBRX 8 |
| 23 | #define IRQ_SERBTX 9 | 24 | #define IRQ_NS9360_SERBTX 9 |
| 24 | #define IRQ_SERARX 10 | 25 | #define IRQ_NS9360_SERARX 10 |
| 25 | #define IRQ_SERATX 11 | 26 | #define IRQ_NS9360_SERATX 11 |
| 26 | #define IRQ_SERCRX 12 | 27 | #define IRQ_NS9360_SERCRX 12 |
| 27 | #define IRQ_SERCTX 13 | 28 | #define IRQ_NS9360_SERCTX 13 |
| 28 | #define IRQ_I2C 14 | 29 | #define IRQ_NS9360_I2C 14 |
| 29 | #define IRQ_BBUSDMA 15 | 30 | #define IRQ_NS9360_BBUSDMA 15 |
| 30 | #define IRQ_TIMER0 16 | 31 | #define IRQ_NS9360_TIMER0 16 |
| 31 | #define IRQ_TIMER1 17 | 32 | #define IRQ_NS9360_TIMER1 17 |
| 32 | #define IRQ_TIMER2 18 | 33 | #define IRQ_NS9360_TIMER2 18 |
| 33 | #define IRQ_TIMER3 19 | 34 | #define IRQ_NS9360_TIMER3 19 |
| 34 | #define IRQ_TIMER4 20 | 35 | #define IRQ_NS9360_TIMER4 20 |
| 35 | #define IRQ_TIMER5 21 | 36 | #define IRQ_NS9360_TIMER5 21 |
| 36 | #define IRQ_TIMER6 22 | 37 | #define IRQ_NS9360_TIMER6 22 |
| 37 | #define IRQ_TIMER7 23 | 38 | #define IRQ_NS9360_TIMER7 23 |
| 38 | #define IRQ_RTC 24 | 39 | #define IRQ_NS9360_RTC 24 |
| 39 | #define IRQ_USBHOST 25 | 40 | #define IRQ_NS9360_USBHOST 25 |
| 40 | #define IRQ_USBDEVICE 26 | 41 | #define IRQ_NS9360_USBDEVICE 26 |
| 41 | #define IRQ_IEEE1284 27 | 42 | #define IRQ_NS9360_IEEE1284 27 |
| 42 | #define IRQ_EXT0 28 | 43 | #define IRQ_NS9XXX_EXT0 28 |
| 43 | #define IRQ_EXT1 29 | 44 | #define IRQ_NS9XXX_EXT1 29 |
| 44 | #define IRQ_EXT2 30 | 45 | #define IRQ_NS9XXX_EXT2 30 |
| 45 | #define IRQ_EXT3 31 | 46 | #define IRQ_NS9XXX_EXT3 31 |
| 46 | 47 | ||
| 47 | #define BBUS_IRQ(irq) (32 + irq) | 48 | #define BBUS_IRQ(irq) (32 + irq) |
| 48 | 49 | ||
| @@ -67,7 +68,7 @@ | |||
| 67 | /* | 68 | /* |
| 68 | * these Interrupts are specific for the a9m9750dev board. | 69 | * these Interrupts are specific for the a9m9750dev board. |
| 69 | * They are generated by an FPGA that interrupts the CPU on | 70 | * They are generated by an FPGA that interrupts the CPU on |
| 70 | * IRQ_EXT2 | 71 | * IRQ_NS9360_EXT2 |
| 71 | */ | 72 | */ |
| 72 | #define FPGA_IRQ(irq) (64 + irq) | 73 | #define FPGA_IRQ(irq) (64 + irq) |
| 73 | 74 | ||
diff --git a/include/asm-arm/arch-ns9xxx/module.h b/include/asm-arm/arch-ns9xxx/module.h new file mode 100644 index 000000000000..ac08a31111e4 --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/module.h | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/module.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_MODULE_H | ||
| 12 | #define __ASM_ARCH_MODULE_H | ||
| 13 | |||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #define module_is_cc7ucamry() (0 \ | ||
| 17 | || machine_is_cc7ucamry() \ | ||
| 18 | ) | ||
| 19 | |||
| 20 | #define module_is_cc9c() (0 \ | ||
| 21 | || machine_is_cc9c() \ | ||
| 22 | ) | ||
| 23 | |||
| 24 | #define module_is_cc9p9210() (0 \ | ||
| 25 | || machine_is_cc9p9210() \ | ||
| 26 | || machine_is_cc9p9210js() \ | ||
| 27 | ) | ||
| 28 | |||
| 29 | #define module_is_cc9p9215() (0 \ | ||
| 30 | || machine_is_cc9p9215() \ | ||
| 31 | || machine_is_cc9p9215js() \ | ||
| 32 | ) | ||
| 33 | |||
| 34 | #define module_is_cc9p9360() (0 \ | ||
| 35 | || machine_is_a9m9360() \ | ||
| 36 | || machine_is_cc9p9360dev() \ | ||
| 37 | || machine_is_cc9p9360js() \ | ||
| 38 | || machine_is_cc9p9360val() \ | ||
| 39 | ) | ||
| 40 | |||
| 41 | #define module_is_cc9p9750() (0 \ | ||
| 42 | || machine_is_a9m9750() \ | ||
| 43 | || machine_is_cc9p9750dev() \ | ||
| 44 | || machine_is_cc9p9750js() \ | ||
| 45 | || machine_is_cc9p9750val() \ | ||
| 46 | ) | ||
| 47 | |||
| 48 | #define module_is_ccw9c() (0 \ | ||
| 49 | || machine_is_ccw9c() \ | ||
| 50 | ) | ||
| 51 | |||
| 52 | #define module_is_inc20otter() (0 \ | ||
| 53 | || machine_is_inc20otter() \ | ||
| 54 | ) | ||
| 55 | |||
| 56 | #define module_is_otter() (0 \ | ||
| 57 | || machine_is_otter() \ | ||
| 58 | ) | ||
| 59 | |||
| 60 | #endif /* ifndef __ASM_ARCH_MODULE_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/processor-ns9360.h b/include/asm-arm/arch-ns9xxx/processor-ns9360.h new file mode 100644 index 000000000000..f3aa6c50dbe5 --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/processor-ns9360.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/processor-ns9360.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_PROCESSORNS9360_H | ||
| 12 | #define __ASM_ARCH_PROCESSORNS9360_H | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | |||
| 16 | void ns9360_reset(char mode); | ||
| 17 | |||
| 18 | unsigned long ns9360_systemclock(void) __attribute__((const)); | ||
| 19 | |||
| 20 | static inline unsigned long ns9360_cpuclock(void) __attribute__((const)); | ||
| 21 | static inline unsigned long ns9360_cpuclock(void) | ||
| 22 | { | ||
| 23 | return ns9360_systemclock() / 2; | ||
| 24 | } | ||
| 25 | |||
| 26 | void __init ns9360_map_io(void); | ||
| 27 | |||
| 28 | extern struct sys_timer ns9360_timer; | ||
| 29 | |||
| 30 | int ns9360_gpio_configure(unsigned gpio, int inv, int func); | ||
| 31 | |||
| 32 | #endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h index 223e51b8e104..f7b53b65de81 100644 --- a/include/asm-arm/arch-ns9xxx/processor.h +++ b/include/asm-arm/arch-ns9xxx/processor.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-ns9xxx/processor.h | 2 | * include/asm-arm/arch-ns9xxx/processor.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,9 +11,32 @@ | |||
| 11 | #ifndef __ASM_ARCH_PROCESSOR_H | 11 | #ifndef __ASM_ARCH_PROCESSOR_H |
| 12 | #define __ASM_ARCH_PROCESSOR_H | 12 | #define __ASM_ARCH_PROCESSOR_H |
| 13 | 13 | ||
| 14 | #include <asm/mach-types.h> | 14 | #include <asm/arch-ns9xxx/module.h> |
| 15 | 15 | ||
| 16 | #define processor_is_ns9360() (machine_is_cc9p9360dev() \ | 16 | #define processor_is_ns9210() (0 \ |
| 17 | || machine_is_cc9p9360js()) | 17 | || module_is_cc7ucamry() \ |
| 18 | || module_is_cc9p9210() \ | ||
| 19 | || module_is_inc20otter() \ | ||
| 20 | || module_is_otter() \ | ||
| 21 | ) | ||
| 22 | |||
| 23 | #define processor_is_ns9215() (0 \ | ||
| 24 | || module_is_cc9p9215() \ | ||
| 25 | ) | ||
| 26 | |||
| 27 | #define processor_is_ns9360() (0 \ | ||
| 28 | || module_is_cc9p9360() \ | ||
| 29 | || module_is_cc9c() \ | ||
| 30 | || module_is_ccw9c() \ | ||
| 31 | ) | ||
| 32 | |||
| 33 | #define processor_is_ns9750() (0 \ | ||
| 34 | || module_is_cc9p9750() \ | ||
| 35 | ) | ||
| 36 | |||
| 37 | #define processor_is_ns921x() (0 \ | ||
| 38 | || processor_is_ns9210() \ | ||
| 39 | || processor_is_ns9215() \ | ||
| 40 | ) | ||
| 18 | 41 | ||
| 19 | #endif /* ifndef __ASM_ARCH_PROCESSOR_H */ | 42 | #endif /* ifndef __ASM_ARCH_PROCESSOR_H */ |
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-common.h b/include/asm-arm/arch-ns9xxx/regs-sys-common.h new file mode 100644 index 000000000000..956c57cb781f --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/regs-sys-common.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/regs-sys-common.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_REGSSYSCOMMON_H | ||
| 13 | #define __ASM_ARCH_REGSSYSCOMMON_H | ||
| 14 | #include <asm/hardware.h> | ||
| 15 | |||
| 16 | /* Interrupt Vector Address Register Level x */ | ||
| 17 | #define SYS_IVA(x) __REG2(0xa09000c4, (x)) | ||
| 18 | |||
| 19 | /* Interrupt Configuration registers */ | ||
| 20 | #define SYS_IC(x) __REG2(0xa0900144, (x)) | ||
| 21 | |||
| 22 | /* ISRADDR */ | ||
| 23 | #define SYS_ISRADDR __REG(0xa0900164) | ||
| 24 | |||
| 25 | /* Interrupt Status Active */ | ||
| 26 | #define SYS_ISA __REG(0xa0900168) | ||
| 27 | |||
| 28 | /* Interrupt Status Raw */ | ||
| 29 | #define SYS_ISR __REG(0xa090016c) | ||
| 30 | |||
| 31 | #endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h index 749262f86204..318b6945afb6 100644 --- a/include/asm-arm/arch-ns9xxx/regs-sys.h +++ b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h | |||
| @@ -1,15 +1,15 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-ns9xxx/regs-sys.h | 2 | * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by | 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. | 9 | * the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | #ifndef __ASM_ARCH_REGSSYS_H | 11 | #ifndef __ASM_ARCH_REGSSYSNS9360_H |
| 12 | #define __ASM_ARCH_REGSSYS_H | 12 | #define __ASM_ARCH_REGSSYSNS9360_H |
| 13 | 13 | ||
| 14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
| 15 | 15 | ||
| @@ -27,21 +27,6 @@ | |||
| 27 | /* Timer x Read register */ | 27 | /* Timer x Read register */ |
| 28 | #define SYS_TR(x) __REG2(0xa0900084, (x)) | 28 | #define SYS_TR(x) __REG2(0xa0900084, (x)) |
| 29 | 29 | ||
| 30 | /* Interrupt Vector Address Register Level x */ | ||
| 31 | #define SYS_IVA(x) __REG2(0xa09000c4, (x)) | ||
| 32 | |||
| 33 | /* Interrupt Configuration registers */ | ||
| 34 | #define SYS_IC(x) __REG2(0xa0900144, (x)) | ||
| 35 | |||
| 36 | /* ISRADDR */ | ||
| 37 | #define SYS_ISRADDR __REG(0xa0900164) | ||
| 38 | |||
| 39 | /* Interrupt Status Active */ | ||
| 40 | #define SYS_ISA __REG(0xa0900168) | ||
| 41 | |||
| 42 | /* Interrupt Status Raw */ | ||
| 43 | #define SYS_ISR __REG(0xa090016c) | ||
| 44 | |||
| 45 | /* Timer Interrupt Status register */ | 30 | /* Timer Interrupt Status register */ |
| 46 | #define SYS_TIS __REG(0xa0900170) | 31 | #define SYS_TIS __REG(0xa0900170) |
| 47 | 32 | ||
| @@ -160,4 +145,4 @@ | |||
| 160 | #define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) | 145 | #define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) |
| 161 | #define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) | 146 | #define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) |
| 162 | 147 | ||
| 163 | #endif /* ifndef __ASM_ARCH_REGSSYS_H */ | 148 | #endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ |
diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h index c1082bd8977c..1348073afe48 100644 --- a/include/asm-arm/arch-ns9xxx/system.h +++ b/include/asm-arm/arch-ns9xxx/system.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-ns9xxx/system.h | 2 | * include/asm-arm/arch-ns9xxx/system.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -12,8 +12,8 @@ | |||
| 12 | #define __ASM_ARCH_SYSTEM_H | 12 | #define __ASM_ARCH_SYSTEM_H |
| 13 | 13 | ||
| 14 | #include <asm/proc-fns.h> | 14 | #include <asm/proc-fns.h> |
| 15 | #include <asm/arch-ns9xxx/regs-sys.h> | 15 | #include <asm/arch-ns9xxx/processor.h> |
| 16 | #include <asm/mach-types.h> | 16 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 17 | 17 | ||
| 18 | static inline void arch_idle(void) | 18 | static inline void arch_idle(void) |
| 19 | { | 19 | { |
| @@ -22,11 +22,12 @@ static inline void arch_idle(void) | |||
| 22 | 22 | ||
| 23 | static inline void arch_reset(char mode) | 23 | static inline void arch_reset(char mode) |
| 24 | { | 24 | { |
| 25 | u32 reg; | 25 | #ifdef CONFIG_PROCESSOR_NS9360 |
| 26 | 26 | if (processor_is_ns9360()) | |
| 27 | reg = __raw_readl(SYS_PLL) >> 16; | 27 | ns9360_reset(mode); |
| 28 | REGSET(reg, SYS_PLL, SWC, YES); | 28 | else |
| 29 | __raw_writel(reg, SYS_PLL); | 29 | #endif |
| 30 | BUG(); | ||
| 30 | 31 | ||
| 31 | BUG(); | 32 | BUG(); |
| 32 | } | 33 | } |
diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h b/include/asm-arm/arch-ns9xxx/uncompress.h index 961ca7dc9954..71066baceab7 100644 --- a/include/asm-arm/arch-ns9xxx/uncompress.h +++ b/include/asm-arm/arch-ns9xxx/uncompress.h | |||
| @@ -11,20 +11,149 @@ | |||
| 11 | #ifndef __ASM_ARCH_UNCOMPRESS_H | 11 | #ifndef __ASM_ARCH_UNCOMPRESS_H |
| 12 | #define __ASM_ARCH_UNCOMPRESS_H | 12 | #define __ASM_ARCH_UNCOMPRESS_H |
| 13 | 13 | ||
| 14 | static void putc(char c) | 14 | #include <asm/io.h> |
| 15 | |||
| 16 | #define __REG(x) ((void __iomem __force *)(x)) | ||
| 17 | |||
| 18 | static void putc_dummy(char c, void __iomem *base) | ||
| 15 | { | 19 | { |
| 16 | volatile u8 *base = (volatile u8 *)0x40000000; | 20 | /* nothing */ |
| 17 | int t = 0x10000; | 21 | } |
| 18 | 22 | ||
| 23 | static void putc_ns9360(char c, void __iomem *base) | ||
| 24 | { | ||
| 25 | static int t = 0x10000; | ||
| 26 | do { | ||
| 27 | if (t) | ||
| 28 | --t; | ||
| 29 | |||
| 30 | if (__raw_readl(base + 8) & (1 << 3)) { | ||
| 31 | __raw_writeb(c, base + 16); | ||
| 32 | t = 0x10000; | ||
| 33 | break; | ||
| 34 | } | ||
| 35 | } while (t); | ||
| 36 | } | ||
| 37 | |||
| 38 | static void putc_a9m9750dev(char c, void __iomem *base) | ||
| 39 | { | ||
| 40 | static int t = 0x10000; | ||
| 41 | do { | ||
| 42 | if (t) | ||
| 43 | --t; | ||
| 44 | |||
| 45 | if (__raw_readb(base + 5) & (1 << 5)) { | ||
| 46 | __raw_writeb(c, base); | ||
| 47 | t = 0x10000; | ||
| 48 | break; | ||
| 49 | } | ||
| 50 | } while (t); | ||
| 51 | |||
| 52 | } | ||
| 53 | |||
| 54 | static void putc_ns921x(char c, void __iomem *base) | ||
| 55 | { | ||
| 56 | static int t = 0x10000; | ||
| 19 | do { | 57 | do { |
| 20 | if (base[5] & 0x20) { | 58 | if (t) |
| 21 | base[0] = c; | 59 | --t; |
| 60 | |||
| 61 | if (!(__raw_readl(base) & (1 << 11))) { | ||
| 62 | __raw_writeb(c, base + 0x0028); | ||
| 63 | t = 0x10000; | ||
| 22 | break; | 64 | break; |
| 23 | } | 65 | } |
| 24 | } while (--t); | 66 | } while (t); |
| 25 | } | 67 | } |
| 26 | 68 | ||
| 27 | #define arch_decomp_setup() | 69 | #define MSCS __REG(0xA0900184) |
| 70 | |||
| 71 | #define NS9360_UARTA __REG(0x90200040) | ||
| 72 | #define NS9360_UARTB __REG(0x90200000) | ||
| 73 | #define NS9360_UARTC __REG(0x90300000) | ||
| 74 | #define NS9360_UARTD __REG(0x90300040) | ||
| 75 | |||
| 76 | #define NS9360_UART_ENABLED(base) \ | ||
| 77 | (__raw_readl(NS9360_UARTA) & (1 << 31)) | ||
| 78 | |||
| 79 | #define A9M9750DEV_UARTA __REG(0x40000000) | ||
| 80 | |||
| 81 | #define NS921XSYS_CLOCK __REG(0xa090017c) | ||
| 82 | #define NS921X_UARTA __REG(0x90010000) | ||
| 83 | #define NS921X_UARTB __REG(0x90018000) | ||
| 84 | #define NS921X_UARTC __REG(0x90020000) | ||
| 85 | #define NS921X_UARTD __REG(0x90028000) | ||
| 86 | |||
| 87 | #define NS921X_UART_ENABLED(base) \ | ||
| 88 | (__raw_readl((base) + 0x1000) & (1 << 29)) | ||
| 89 | |||
| 90 | static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) | ||
| 91 | { | ||
| 92 | if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { | ||
| 93 | /* ns9360 or ns9750 */ | ||
| 94 | if (NS9360_UART_ENABLED(NS9360_UARTA)) { | ||
| 95 | *putc = putc_ns9360; | ||
| 96 | *base = NS9360_UARTA; | ||
| 97 | return; | ||
| 98 | } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { | ||
| 99 | *putc = putc_ns9360; | ||
| 100 | *base = NS9360_UARTB; | ||
| 101 | return; | ||
| 102 | } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { | ||
| 103 | *putc = putc_ns9360; | ||
| 104 | *base = NS9360_UARTC; | ||
| 105 | return; | ||
| 106 | } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { | ||
| 107 | *putc = putc_ns9360; | ||
| 108 | *base = NS9360_UARTD; | ||
| 109 | return; | ||
| 110 | } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { | ||
| 111 | *putc = putc_a9m9750dev; | ||
| 112 | *base = A9M9750DEV_UARTA; | ||
| 113 | return; | ||
| 114 | } | ||
| 115 | } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { | ||
| 116 | /* ns921x */ | ||
| 117 | u32 clock = __raw_readl(NS921XSYS_CLOCK); | ||
| 118 | |||
| 119 | if ((clock & (1 << 1)) && | ||
| 120 | NS921X_UART_ENABLED(NS921X_UARTA)) { | ||
| 121 | *putc = putc_ns921x; | ||
| 122 | *base = NS921X_UARTA; | ||
| 123 | return; | ||
| 124 | } else if ((clock & (1 << 2)) && | ||
| 125 | NS921X_UART_ENABLED(NS921X_UARTB)) { | ||
| 126 | *putc = putc_ns921x; | ||
| 127 | *base = NS921X_UARTB; | ||
| 128 | return; | ||
| 129 | } else if ((clock & (1 << 3)) && | ||
| 130 | NS921X_UART_ENABLED(NS921X_UARTC)) { | ||
| 131 | *putc = putc_ns921x; | ||
| 132 | *base = NS921X_UARTC; | ||
| 133 | return; | ||
| 134 | } else if ((clock & (1 << 4)) && | ||
| 135 | NS921X_UART_ENABLED(NS921X_UARTD)) { | ||
| 136 | *putc = putc_ns921x; | ||
| 137 | *base = NS921X_UARTD; | ||
| 138 | return; | ||
| 139 | } | ||
| 140 | } | ||
| 141 | |||
| 142 | *putc = putc_dummy; | ||
| 143 | } | ||
| 144 | |||
| 145 | void (*myputc)(char, void __iomem *); | ||
| 146 | void __iomem *base; | ||
| 147 | |||
| 148 | static void putc(char c) | ||
| 149 | { | ||
| 150 | myputc(c, base); | ||
| 151 | } | ||
| 152 | |||
| 153 | static void arch_decomp_setup(void) | ||
| 154 | { | ||
| 155 | autodetect(&myputc, &base); | ||
| 156 | } | ||
| 28 | #define arch_decomp_wdog() | 157 | #define arch_decomp_wdog() |
| 29 | 158 | ||
| 30 | static void flush(void) | 159 | static void flush(void) |
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h deleted file mode 100644 index e0b8c39b9167..000000000000 --- a/include/asm-arm/arch-orion/io.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion/io.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 12 | #define __ASM_ARM_ARCH_IO_H | ||
| 13 | |||
| 14 | #include "orion.h" | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 17 | #define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE | ||
| 18 | |||
| 19 | static inline void __iomem *__io(unsigned long addr) | ||
| 20 | { | ||
| 21 | return (void __iomem *)addr; | ||
| 22 | } | ||
| 23 | |||
| 24 | #define __io(a) __io(a) | ||
| 25 | #define __mem_pci(a) (a) | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h deleted file mode 100644 index eea65ca6076a..000000000000 --- a/include/asm-arm/arch-orion/irqs.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Orion SoC | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_IRQS_H__ | ||
| 14 | #define __ASM_ARCH_IRQS_H__ | ||
| 15 | |||
| 16 | #include "orion.h" /* need GPIO_MAX */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Orion Main Interrupt Controller | ||
| 20 | */ | ||
| 21 | #define IRQ_ORION_BRIDGE 0 | ||
| 22 | #define IRQ_ORION_DOORBELL_H2C 1 | ||
| 23 | #define IRQ_ORION_DOORBELL_C2H 2 | ||
| 24 | #define IRQ_ORION_UART0 3 | ||
| 25 | #define IRQ_ORION_UART1 4 | ||
| 26 | #define IRQ_ORION_I2C 5 | ||
| 27 | #define IRQ_ORION_GPIO_0_7 6 | ||
| 28 | #define IRQ_ORION_GPIO_8_15 7 | ||
| 29 | #define IRQ_ORION_GPIO_16_23 8 | ||
| 30 | #define IRQ_ORION_GPIO_24_31 9 | ||
| 31 | #define IRQ_ORION_PCIE0_ERR 10 | ||
| 32 | #define IRQ_ORION_PCIE0_INT 11 | ||
| 33 | #define IRQ_ORION_USB1_CTRL 12 | ||
| 34 | #define IRQ_ORION_DEV_BUS_ERR 14 | ||
| 35 | #define IRQ_ORION_PCI_ERR 15 | ||
| 36 | #define IRQ_ORION_USB_BR_ERR 16 | ||
| 37 | #define IRQ_ORION_USB0_CTRL 17 | ||
| 38 | #define IRQ_ORION_ETH_RX 18 | ||
| 39 | #define IRQ_ORION_ETH_TX 19 | ||
| 40 | #define IRQ_ORION_ETH_MISC 20 | ||
| 41 | #define IRQ_ORION_ETH_SUM 21 | ||
| 42 | #define IRQ_ORION_ETH_ERR 22 | ||
| 43 | #define IRQ_ORION_IDMA_ERR 23 | ||
| 44 | #define IRQ_ORION_IDMA_0 24 | ||
| 45 | #define IRQ_ORION_IDMA_1 25 | ||
| 46 | #define IRQ_ORION_IDMA_2 26 | ||
| 47 | #define IRQ_ORION_IDMA_3 27 | ||
| 48 | #define IRQ_ORION_CESA 28 | ||
| 49 | #define IRQ_ORION_SATA 29 | ||
| 50 | #define IRQ_ORION_XOR0 30 | ||
| 51 | #define IRQ_ORION_XOR1 31 | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Orion General Purpose Pins | ||
| 55 | */ | ||
| 56 | #define IRQ_ORION_GPIO_START 32 | ||
| 57 | #define NR_GPIO_IRQS GPIO_MAX | ||
| 58 | |||
| 59 | #define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) | ||
| 60 | |||
| 61 | #endif /* __ASM_ARCH_IRQS_H__ */ | ||
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h deleted file mode 100644 index 673a418a7419..000000000000 --- a/include/asm-arm/arch-orion/orion.h +++ /dev/null | |||
| @@ -1,165 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion/orion.h | ||
| 3 | * | ||
| 4 | * Generic definitions of Orion SoC flavors: | ||
| 5 | * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. | ||
| 6 | * | ||
| 7 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_ORION_H__ | ||
| 15 | #define __ASM_ARCH_ORION_H__ | ||
| 16 | |||
| 17 | /***************************************************************************** | ||
| 18 | * Orion Address Map | ||
| 19 | * | ||
| 20 | * virt phys size | ||
| 21 | * fdd00000 f1000000 1M on-chip peripheral registers | ||
| 22 | * fde00000 f2000000 1M PCIe I/O space | ||
| 23 | * fdf00000 f2100000 1M PCI I/O space | ||
| 24 | * fe000000 f0000000 16M PCIe WA space (Orion-NAS only) | ||
| 25 | ****************************************************************************/ | ||
| 26 | #define ORION_REGS_PHYS_BASE 0xf1000000 | ||
| 27 | #define ORION_REGS_VIRT_BASE 0xfdd00000 | ||
| 28 | #define ORION_REGS_SIZE SZ_1M | ||
| 29 | |||
| 30 | #define ORION_PCIE_IO_PHYS_BASE 0xf2000000 | ||
| 31 | #define ORION_PCIE_IO_VIRT_BASE 0xfde00000 | ||
| 32 | #define ORION_PCIE_IO_BUS_BASE 0x00000000 | ||
| 33 | #define ORION_PCIE_IO_SIZE SZ_1M | ||
| 34 | |||
| 35 | #define ORION_PCI_IO_PHYS_BASE 0xf2100000 | ||
| 36 | #define ORION_PCI_IO_VIRT_BASE 0xfdf00000 | ||
| 37 | #define ORION_PCI_IO_BUS_BASE 0x00100000 | ||
| 38 | #define ORION_PCI_IO_SIZE SZ_1M | ||
| 39 | |||
| 40 | /* Relevant only for Orion-NAS */ | ||
| 41 | #define ORION_PCIE_WA_PHYS_BASE 0xf0000000 | ||
| 42 | #define ORION_PCIE_WA_VIRT_BASE 0xfe000000 | ||
| 43 | #define ORION_PCIE_WA_SIZE SZ_16M | ||
| 44 | |||
| 45 | #define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 | ||
| 46 | #define ORION_PCIE_MEM_SIZE SZ_128M | ||
| 47 | |||
| 48 | #define ORION_PCI_MEM_PHYS_BASE 0xe8000000 | ||
| 49 | #define ORION_PCI_MEM_SIZE SZ_128M | ||
| 50 | |||
| 51 | /******************************************************************************* | ||
| 52 | * Supported Devices & Revisions | ||
| 53 | ******************************************************************************/ | ||
| 54 | /* Orion-1 (88F5181) */ | ||
| 55 | #define MV88F5181_DEV_ID 0x5181 | ||
| 56 | #define MV88F5181_REV_B1 3 | ||
| 57 | /* Orion-NAS (88F5182) */ | ||
| 58 | #define MV88F5182_DEV_ID 0x5182 | ||
| 59 | #define MV88F5182_REV_A2 2 | ||
| 60 | /* Orion-2 (88F5281) */ | ||
| 61 | #define MV88F5281_DEV_ID 0x5281 | ||
| 62 | #define MV88F5281_REV_D1 5 | ||
| 63 | #define MV88F5281_REV_D2 6 | ||
| 64 | |||
| 65 | /******************************************************************************* | ||
| 66 | * Orion Registers Map | ||
| 67 | ******************************************************************************/ | ||
| 68 | #define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) | ||
| 69 | #define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) | ||
| 70 | |||
| 71 | #define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) | ||
| 72 | #define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) | ||
| 73 | #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) | ||
| 74 | #define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) | ||
| 75 | #define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) | ||
| 76 | #define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) | ||
| 77 | #define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) | ||
| 78 | #define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) | ||
| 79 | |||
| 80 | #define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) | ||
| 81 | #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) | ||
| 82 | |||
| 83 | #define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) | ||
| 84 | #define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) | ||
| 85 | |||
| 86 | #define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) | ||
| 87 | #define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) | ||
| 88 | |||
| 89 | #define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) | ||
| 90 | #define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) | ||
| 91 | #define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) | ||
| 92 | |||
| 93 | #define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) | ||
| 94 | #define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) | ||
| 95 | #define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) | ||
| 96 | |||
| 97 | #define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) | ||
| 98 | #define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) | ||
| 99 | #define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) | ||
| 100 | |||
| 101 | #define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) | ||
| 102 | #define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) | ||
| 103 | #define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) | ||
| 104 | |||
| 105 | /******************************************************************************* | ||
| 106 | * Device Bus Registers | ||
| 107 | ******************************************************************************/ | ||
| 108 | #define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) | ||
| 109 | #define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) | ||
| 110 | #define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) | ||
| 111 | #define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) | ||
| 112 | #define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) | ||
| 113 | #define GPIO_OUT ORION_DEV_BUS_REG(0x100) | ||
| 114 | #define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) | ||
| 115 | #define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) | ||
| 116 | #define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) | ||
| 117 | #define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) | ||
| 118 | #define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) | ||
| 119 | #define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) | ||
| 120 | #define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) | ||
| 121 | #define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) | ||
| 122 | #define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) | ||
| 123 | #define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) | ||
| 124 | #define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) | ||
| 125 | #define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) | ||
| 126 | #define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) | ||
| 127 | #define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) | ||
| 128 | #define GPIO_MAX 32 | ||
| 129 | |||
| 130 | /*************************************************************************** | ||
| 131 | * Orion CPU Bridge Registers | ||
| 132 | **************************************************************************/ | ||
| 133 | #define CPU_CONF ORION_BRIDGE_REG(0x100) | ||
| 134 | #define CPU_CTRL ORION_BRIDGE_REG(0x104) | ||
| 135 | #define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) | ||
| 136 | #define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) | ||
| 137 | #define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) | ||
| 138 | #define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) | ||
| 139 | #define BRIDGE_MASK ORION_BRIDGE_REG(0x114) | ||
| 140 | #define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) | ||
| 141 | #define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) | ||
| 142 | #define TIMER_CTRL ORION_BRIDGE_REG(0x300) | ||
| 143 | #define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8)) | ||
| 144 | #define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8)) | ||
| 145 | |||
| 146 | #ifndef __ASSEMBLY__ | ||
| 147 | |||
| 148 | /******************************************************************************* | ||
| 149 | * Helpers to access Orion registers | ||
| 150 | ******************************************************************************/ | ||
| 151 | #include <asm/types.h> | ||
| 152 | #include <asm/io.h> | ||
| 153 | |||
| 154 | #define orion_read(r) __raw_readl(r) | ||
| 155 | #define orion_write(r, val) __raw_writel(val, r) | ||
| 156 | |||
| 157 | /* | ||
| 158 | * These are not preempt safe. Locks, if needed, must be taken care by caller. | ||
| 159 | */ | ||
| 160 | #define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) | ||
| 161 | #define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) | ||
| 162 | |||
| 163 | #endif /* __ASSEMBLY__ */ | ||
| 164 | |||
| 165 | #endif /* __ASM_ARCH_ORION_H__ */ | ||
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h deleted file mode 100644 index 26c2c91eecf0..000000000000 --- a/include/asm-arm/arch-orion/timex.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion/timex.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define ORION_TCLK 166666667 | ||
| 12 | #define CLOCK_TICK_RATE ORION_TCLK | ||
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S index 2746220f5d85..4f98f3ba2929 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion5x/debug-macro.S | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/include/asm-arm/arch-orion/debug-macro.S | 2 | * include/asm-arm/arch-orion5x/debug-macro.S |
| 3 | * | 3 | * |
| 4 | * Debugging macro include header | 4 | * Debugging macro include header |
| 5 | * | 5 | * |
| @@ -8,13 +8,13 @@ | |||
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <asm/arch/orion.h> | 11 | #include <asm/arch/orion5x.h> |
| 12 | 12 | ||
| 13 | .macro addruart,rx | 13 | .macro addruart,rx |
| 14 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
| 15 | tst \rx, #1 @ MMU enabled? | 15 | tst \rx, #1 @ MMU enabled? |
| 16 | ldreq \rx, =ORION_REGS_PHYS_BASE | 16 | ldreq \rx, =ORION5X_REGS_PHYS_BASE |
| 17 | ldrne \rx, =ORION_REGS_VIRT_BASE | 17 | ldrne \rx, =ORION5X_REGS_VIRT_BASE |
| 18 | orr \rx, \rx, #0x00012000 | 18 | orr \rx, \rx, #0x00012000 |
| 19 | .endm | 19 | .endm |
| 20 | 20 | ||
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h index 40a8c178f10d..40a8c178f10d 100644 --- a/include/asm-arm/arch-orion/dma.h +++ b/include/asm-arm/arch-orion5x/dma.h | |||
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S index cda096b2acfd..d8ef54c0ee9a 100644 --- a/include/asm-arm/arch-orion/entry-macro.S +++ b/include/asm-arm/arch-orion5x/entry-macro.S | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/entry-macro.S | 2 | * include/asm-arm/arch-orion5x/entry-macro.S |
| 3 | * | 3 | * |
| 4 | * Low-level IRQ helper macros for Orion platforms | 4 | * Low-level IRQ helper macros for Orion platforms |
| 5 | * | 5 | * |
| @@ -8,7 +8,7 @@ | |||
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <asm/arch/orion.h> | 11 | #include <asm/arch/orion5x.h> |
| 12 | 12 | ||
| 13 | .macro disable_fiq | 13 | .macro disable_fiq |
| 14 | .endm | 14 | .endm |
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h index d66284f9a14c..c85e498388b6 100644 --- a/include/asm-arm/arch-orion/gpio.h +++ b/include/asm-arm/arch-orion5x/gpio.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/gpio.h | 2 | * include/asm-arm/arch-orion5x/gpio.h |
| 3 | * | 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public | 4 | * This file is licensed under the terms of the GNU General Public |
| 5 | * License version 2. This program is licensed "as is" without any | 5 | * License version 2. This program is licensed "as is" without any |
| @@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin); | |||
| 12 | extern int gpio_direction_output(unsigned pin, int value); | 12 | extern int gpio_direction_output(unsigned pin, int value); |
| 13 | extern int gpio_get_value(unsigned pin); | 13 | extern int gpio_get_value(unsigned pin); |
| 14 | extern void gpio_set_value(unsigned pin, int value); | 14 | extern void gpio_set_value(unsigned pin, int value); |
| 15 | extern void orion_gpio_set_blink(unsigned pin, int blink); | 15 | extern void orion5x_gpio_set_blink(unsigned pin, int blink); |
| 16 | extern void gpio_display(void); /* debug */ | 16 | extern void gpio_display(void); /* debug */ |
| 17 | 17 | ||
| 18 | static inline int gpio_to_irq(int pin) | 18 | static inline int gpio_to_irq(int pin) |
| 19 | { | 19 | { |
| 20 | return pin + IRQ_ORION_GPIO_START; | 20 | return pin + IRQ_ORION5X_GPIO_START; |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | static inline int irq_to_gpio(int irq) | 23 | static inline int irq_to_gpio(int irq) |
| 24 | { | 24 | { |
| 25 | return irq - IRQ_ORION_GPIO_START; | 25 | return irq - IRQ_ORION5X_GPIO_START; |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 28 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h index 65da374de735..5d2d8e0b5630 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion5x/hardware.h | |||
| @@ -1,21 +1,21 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/hardware.h | 2 | * include/asm-arm/arch-orion5x/hardware.h |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #ifndef __ASM_ARCH_HARDWARE_H__ | 9 | #ifndef __ASM_ARCH_HARDWARE_H |
| 10 | #define __ASM_ARCH_HARDWARE_H__ | 10 | #define __ASM_ARCH_HARDWARE_H |
| 11 | 11 | ||
| 12 | #include "orion.h" | 12 | #include "orion5x.h" |
| 13 | 13 | ||
| 14 | #define pcibios_assign_all_busses() 1 | 14 | #define pcibios_assign_all_busses() 1 |
| 15 | 15 | ||
| 16 | #define PCIBIOS_MIN_IO 0x00001000 | 16 | #define PCIBIOS_MIN_IO 0x00001000 |
| 17 | #define PCIBIOS_MIN_MEM 0x01000000 | 17 | #define PCIBIOS_MIN_MEM 0x01000000 |
| 18 | #define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE | 18 | #define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE |
| 19 | 19 | ||
| 20 | 20 | ||
| 21 | #endif | 21 | #endif |
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h new file mode 100644 index 000000000000..5148ab7ad1f8 --- /dev/null +++ b/include/asm-arm/arch-orion5x/io.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/io.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IO_H | ||
| 12 | #define __ASM_ARCH_IO_H | ||
| 13 | |||
| 14 | #include "orion5x.h" | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 17 | #define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE | ||
| 18 | |||
| 19 | static inline void __iomem * | ||
| 20 | __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) | ||
| 21 | { | ||
| 22 | void __iomem *retval; | ||
| 23 | |||
| 24 | if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE && | ||
| 25 | paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) { | ||
| 26 | retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + | ||
| 27 | (paddr - ORION5X_REGS_PHYS_BASE); | ||
| 28 | } else { | ||
| 29 | retval = __arm_ioremap(paddr, size, mtype); | ||
| 30 | } | ||
| 31 | |||
| 32 | return retval; | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void | ||
| 36 | __arch_iounmap(void __iomem *addr) | ||
| 37 | { | ||
| 38 | if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || | ||
| 39 | addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) | ||
| 40 | __iounmap(addr); | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline void __iomem *__io(unsigned long addr) | ||
| 44 | { | ||
| 45 | return (void __iomem *)addr; | ||
| 46 | } | ||
| 47 | |||
| 48 | #define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) | ||
| 49 | #define __arch_iounmap(a) __arch_iounmap(a) | ||
| 50 | #define __io(a) __io(a) | ||
| 51 | #define __mem_pci(a) (a) | ||
| 52 | |||
| 53 | |||
| 54 | /***************************************************************************** | ||
| 55 | * Helpers to access Orion registers | ||
| 56 | ****************************************************************************/ | ||
| 57 | #define orion5x_read(r) __raw_readl(r) | ||
| 58 | #define orion5x_write(r, val) __raw_writel(val, r) | ||
| 59 | |||
| 60 | /* | ||
| 61 | * These are not preempt-safe. Locks, if needed, must be taken | ||
| 62 | * care of by the caller. | ||
| 63 | */ | ||
| 64 | #define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) | ||
| 65 | #define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) | ||
| 66 | |||
| 67 | |||
| 68 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h new file mode 100644 index 000000000000..abdd61a4833a --- /dev/null +++ b/include/asm-arm/arch-orion5x/irqs.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Orion SoC | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_IRQS_H | ||
| 14 | #define __ASM_ARCH_IRQS_H | ||
| 15 | |||
| 16 | #include "orion5x.h" /* need GPIO_MAX */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Orion Main Interrupt Controller | ||
| 20 | */ | ||
| 21 | #define IRQ_ORION5X_BRIDGE 0 | ||
| 22 | #define IRQ_ORION5X_DOORBELL_H2C 1 | ||
| 23 | #define IRQ_ORION5X_DOORBELL_C2H 2 | ||
| 24 | #define IRQ_ORION5X_UART0 3 | ||
| 25 | #define IRQ_ORION5X_UART1 4 | ||
| 26 | #define IRQ_ORION5X_I2C 5 | ||
| 27 | #define IRQ_ORION5X_GPIO_0_7 6 | ||
| 28 | #define IRQ_ORION5X_GPIO_8_15 7 | ||
| 29 | #define IRQ_ORION5X_GPIO_16_23 8 | ||
| 30 | #define IRQ_ORION5X_GPIO_24_31 9 | ||
| 31 | #define IRQ_ORION5X_PCIE0_ERR 10 | ||
| 32 | #define IRQ_ORION5X_PCIE0_INT 11 | ||
| 33 | #define IRQ_ORION5X_USB1_CTRL 12 | ||
| 34 | #define IRQ_ORION5X_DEV_BUS_ERR 14 | ||
| 35 | #define IRQ_ORION5X_PCI_ERR 15 | ||
| 36 | #define IRQ_ORION5X_USB_BR_ERR 16 | ||
| 37 | #define IRQ_ORION5X_USB0_CTRL 17 | ||
| 38 | #define IRQ_ORION5X_ETH_RX 18 | ||
| 39 | #define IRQ_ORION5X_ETH_TX 19 | ||
| 40 | #define IRQ_ORION5X_ETH_MISC 20 | ||
| 41 | #define IRQ_ORION5X_ETH_SUM 21 | ||
| 42 | #define IRQ_ORION5X_ETH_ERR 22 | ||
| 43 | #define IRQ_ORION5X_IDMA_ERR 23 | ||
| 44 | #define IRQ_ORION5X_IDMA_0 24 | ||
| 45 | #define IRQ_ORION5X_IDMA_1 25 | ||
| 46 | #define IRQ_ORION5X_IDMA_2 26 | ||
| 47 | #define IRQ_ORION5X_IDMA_3 27 | ||
| 48 | #define IRQ_ORION5X_CESA 28 | ||
| 49 | #define IRQ_ORION5X_SATA 29 | ||
| 50 | #define IRQ_ORION5X_XOR0 30 | ||
| 51 | #define IRQ_ORION5X_XOR1 31 | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Orion General Purpose Pins | ||
| 55 | */ | ||
| 56 | #define IRQ_ORION5X_GPIO_START 32 | ||
| 57 | #define NR_GPIO_IRQS GPIO_MAX | ||
| 58 | |||
| 59 | #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) | ||
| 60 | |||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h index d954dba87ced..80053a7afc7a 100644 --- a/include/asm-arm/arch-orion/memory.h +++ b/include/asm-arm/arch-orion5x/memory.h | |||
| @@ -1,15 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/memory.h | 2 | * include/asm-arm/arch-orion5x/memory.h |
| 3 | * | 3 | * |
| 4 | * Marvell Orion memory definitions | 4 | * Marvell Orion memory definitions |
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| 7 | #ifndef __ASM_ARCH_MMU_H | 7 | #ifndef __ASM_ARCH_MEMORY_H |
| 8 | #define __ASM_ARCH_MMU_H | 8 | #define __ASM_ARCH_MEMORY_H |
| 9 | 9 | ||
| 10 | #define PHYS_OFFSET UL(0x00000000) | 10 | #define PHYS_OFFSET UL(0x00000000) |
| 11 | 11 | ||
| 12 | #define __virt_to_bus(x) __virt_to_phys(x) | 12 | #define __virt_to_bus(x) __virt_to_phys(x) |
| 13 | #define __bus_to_virt(x) __phys_to_virt(x) | 13 | #define __bus_to_virt(x) __phys_to_virt(x) |
| 14 | 14 | ||
| 15 | |||
| 15 | #endif | 16 | #endif |
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 000000000000..206ddd71e193 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/orion5x.h | ||
| 3 | * | ||
| 4 | * Generic definitions of Orion SoC flavors: | ||
| 5 | * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. | ||
| 6 | * | ||
| 7 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_ORION5X_H | ||
| 15 | #define __ASM_ARCH_ORION5X_H | ||
| 16 | |||
| 17 | /***************************************************************************** | ||
| 18 | * Orion Address Maps | ||
| 19 | * | ||
| 20 | * phys | ||
| 21 | * e0000000 PCIe MEM space | ||
| 22 | * e8000000 PCI MEM space | ||
| 23 | * f0000000 PCIe WA space (Orion-1/Orion-NAS only) | ||
| 24 | * f1000000 on-chip peripheral registers | ||
| 25 | * f2000000 PCIe I/O space | ||
| 26 | * f2100000 PCI I/O space | ||
| 27 | * f4000000 device bus mappings (boot) | ||
| 28 | * fa000000 device bus mappings (cs0) | ||
| 29 | * fa800000 device bus mappings (cs2) | ||
| 30 | * fc000000 device bus mappings (cs0/cs1) | ||
| 31 | * | ||
| 32 | * virt phys size | ||
| 33 | * fdd00000 f1000000 1M on-chip peripheral registers | ||
| 34 | * fde00000 f2000000 1M PCIe I/O space | ||
| 35 | * fdf00000 f2100000 1M PCI I/O space | ||
| 36 | * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) | ||
| 37 | ****************************************************************************/ | ||
| 38 | #define ORION5X_REGS_PHYS_BASE 0xf1000000 | ||
| 39 | #define ORION5X_REGS_VIRT_BASE 0xfdd00000 | ||
| 40 | #define ORION5X_REGS_SIZE SZ_1M | ||
| 41 | |||
| 42 | #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 | ||
| 43 | #define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 | ||
| 44 | #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 | ||
| 45 | #define ORION5X_PCIE_IO_SIZE SZ_1M | ||
| 46 | |||
| 47 | #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 | ||
| 48 | #define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 | ||
| 49 | #define ORION5X_PCI_IO_BUS_BASE 0x00100000 | ||
| 50 | #define ORION5X_PCI_IO_SIZE SZ_1M | ||
| 51 | |||
| 52 | /* Relevant only for Orion-1/Orion-NAS */ | ||
| 53 | #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 | ||
| 54 | #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 | ||
| 55 | #define ORION5X_PCIE_WA_SIZE SZ_16M | ||
| 56 | |||
| 57 | #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 | ||
| 58 | #define ORION5X_PCIE_MEM_SIZE SZ_128M | ||
| 59 | |||
| 60 | #define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 | ||
| 61 | #define ORION5X_PCI_MEM_SIZE SZ_128M | ||
| 62 | |||
| 63 | /******************************************************************************* | ||
| 64 | * Supported Devices & Revisions | ||
| 65 | ******************************************************************************/ | ||
| 66 | /* Orion-1 (88F5181) */ | ||
| 67 | #define MV88F5181_DEV_ID 0x5181 | ||
| 68 | #define MV88F5181_REV_B1 3 | ||
| 69 | /* Orion-NAS (88F5182) */ | ||
| 70 | #define MV88F5182_DEV_ID 0x5182 | ||
| 71 | #define MV88F5182_REV_A2 2 | ||
| 72 | /* Orion-2 (88F5281) */ | ||
| 73 | #define MV88F5281_DEV_ID 0x5281 | ||
| 74 | #define MV88F5281_REV_D1 5 | ||
| 75 | #define MV88F5281_REV_D2 6 | ||
| 76 | |||
| 77 | /******************************************************************************* | ||
| 78 | * Orion Registers Map | ||
| 79 | ******************************************************************************/ | ||
| 80 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) | ||
| 81 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) | ||
| 82 | |||
| 83 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) | ||
| 84 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) | ||
| 85 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) | ||
| 86 | #define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) | ||
| 87 | #define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) | ||
| 88 | #define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) | ||
| 89 | #define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) | ||
| 90 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) | ||
| 91 | |||
| 92 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) | ||
| 93 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) | ||
| 94 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) | ||
| 95 | |||
| 96 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) | ||
| 97 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) | ||
| 98 | |||
| 99 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) | ||
| 100 | #define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) | ||
| 101 | |||
| 102 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) | ||
| 103 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) | ||
| 104 | #define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) | ||
| 105 | |||
| 106 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) | ||
| 107 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) | ||
| 108 | #define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) | ||
| 109 | |||
| 110 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) | ||
| 111 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) | ||
| 112 | #define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) | ||
| 113 | |||
| 114 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) | ||
| 115 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) | ||
| 116 | #define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) | ||
| 117 | |||
| 118 | /******************************************************************************* | ||
| 119 | * Device Bus Registers | ||
| 120 | ******************************************************************************/ | ||
| 121 | #define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) | ||
| 122 | #define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) | ||
| 123 | #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) | ||
| 124 | #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) | ||
| 125 | #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) | ||
| 126 | #define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) | ||
| 127 | #define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) | ||
| 128 | #define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) | ||
| 129 | #define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) | ||
| 130 | #define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) | ||
| 131 | #define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) | ||
| 132 | #define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) | ||
| 133 | #define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) | ||
| 134 | #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) | ||
| 135 | #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) | ||
| 136 | #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) | ||
| 137 | #define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) | ||
| 138 | #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) | ||
| 139 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) | ||
| 140 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) | ||
| 141 | #define GPIO_MAX 32 | ||
| 142 | |||
| 143 | /*************************************************************************** | ||
| 144 | * Orion CPU Bridge Registers | ||
| 145 | **************************************************************************/ | ||
| 146 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) | ||
| 147 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) | ||
| 148 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) | ||
| 149 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) | ||
| 150 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) | ||
| 151 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) | ||
| 152 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) | ||
| 153 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 154 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 155 | #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) | ||
| 156 | #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) | ||
| 157 | |||
| 158 | |||
| 159 | #endif | ||
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h index 17704c68f90e..3f1d1e2d38f8 100644 --- a/include/asm-arm/arch-orion/system.h +++ b/include/asm-arm/arch-orion5x/system.h | |||
| @@ -1,10 +1,10 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/system.h | 2 | * include/asm-arm/arch-orion5x/system.h |
| 3 | * | 3 | * |
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | 4 | * Tzachi Perelstein <tzachi@marvell.com> |
| 5 | * | 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any | 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| @@ -12,7 +12,7 @@ | |||
| 12 | #define __ASM_ARCH_SYSTEM_H | 12 | #define __ASM_ARCH_SYSTEM_H |
| 13 | 13 | ||
| 14 | #include <asm/arch/hardware.h> | 14 | #include <asm/arch/hardware.h> |
| 15 | #include <asm/arch/orion.h> | 15 | #include <asm/arch/orion5x.h> |
| 16 | 16 | ||
| 17 | static inline void arch_idle(void) | 17 | static inline void arch_idle(void) |
| 18 | { | 18 | { |
| @@ -24,8 +24,9 @@ static inline void arch_reset(char mode) | |||
| 24 | /* | 24 | /* |
| 25 | * Enable and issue soft reset | 25 | * Enable and issue soft reset |
| 26 | */ | 26 | */ |
| 27 | orion_setbits(CPU_RESET_MASK, (1 << 2)); | 27 | orion5x_setbits(CPU_RESET_MASK, (1 << 2)); |
| 28 | orion_setbits(CPU_SOFT_RESET, 1); | 28 | orion5x_setbits(CPU_SOFT_RESET, 1); |
| 29 | } | 29 | } |
| 30 | 30 | ||
| 31 | |||
| 31 | #endif | 32 | #endif |
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h new file mode 100644 index 000000000000..31c568e28cc3 --- /dev/null +++ b/include/asm-arm/arch-orion5x/timex.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/timex.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define CLOCK_TICK_RATE (100 * HZ) | ||
| 12 | |||
| 13 | #define ORION5X_TCLK 166666667 | ||
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h index 59f44039909a..5c13d4fafb4e 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion5x/uncompress.h | |||
| @@ -1,14 +1,14 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/uncompress.h | 2 | * include/asm-arm/arch-orion5x/uncompress.h |
| 3 | * | 3 | * |
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | 4 | * Tzachi Perelstein <tzachi@marvell.com> |
| 5 | * | 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any | 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <asm/arch/orion.h> | 11 | #include <asm/arch/orion5x.h> |
| 12 | 12 | ||
| 13 | #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) | 13 | #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) |
| 14 | #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) | 14 | #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) |
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h index 9d580278d2bc..2b3061e90dc1 100644 --- a/include/asm-arm/arch-orion/vmalloc.h +++ b/include/asm-arm/arch-orion5x/vmalloc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-orion/vmalloc.h | 2 | * include/asm-arm/arch-orion5x/vmalloc.h |
| 3 | */ | 3 | */ |
| 4 | 4 | ||
| 5 | #define VMALLOC_END 0xfd800000 | 5 | #define VMALLOC_END 0xfd800000 |
diff --git a/include/asm-arm/arch-pxa/camera.h b/include/asm-arm/arch-pxa/camera.h new file mode 100644 index 000000000000..39516ced8b1f --- /dev/null +++ b/include/asm-arm/arch-pxa/camera.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | camera.h - PXA camera driver header file | ||
| 3 | |||
| 4 | Copyright (C) 2003, Intel Corporation | ||
| 5 | Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | ||
| 6 | |||
| 7 | This program is free software; you can redistribute it and/or modify | ||
| 8 | it under the terms of the GNU General Public License as published by | ||
| 9 | the Free Software Foundation; either version 2 of the License, or | ||
| 10 | (at your option) any later version. | ||
| 11 | |||
| 12 | This program is distributed in the hope that it will be useful, | ||
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | GNU General Public License for more details. | ||
| 16 | |||
| 17 | You should have received a copy of the GNU General Public License | ||
| 18 | along with this program; if not, write to the Free Software | ||
| 19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_ARCH_CAMERA_H_ | ||
| 23 | #define __ASM_ARCH_CAMERA_H_ | ||
| 24 | |||
| 25 | #define PXA_CAMERA_MASTER 1 | ||
| 26 | #define PXA_CAMERA_DATAWIDTH_4 2 | ||
| 27 | #define PXA_CAMERA_DATAWIDTH_5 4 | ||
| 28 | #define PXA_CAMERA_DATAWIDTH_8 8 | ||
| 29 | #define PXA_CAMERA_DATAWIDTH_9 0x10 | ||
| 30 | #define PXA_CAMERA_DATAWIDTH_10 0x20 | ||
| 31 | #define PXA_CAMERA_PCLK_EN 0x40 | ||
| 32 | #define PXA_CAMERA_MCLK_EN 0x80 | ||
| 33 | #define PXA_CAMERA_PCP 0x100 | ||
| 34 | #define PXA_CAMERA_HSP 0x200 | ||
| 35 | #define PXA_CAMERA_VSP 0x400 | ||
| 36 | |||
| 37 | struct pxacamera_platform_data { | ||
| 38 | int (*init)(struct device *); | ||
| 39 | int (*power)(struct device *, int); | ||
| 40 | int (*reset)(struct device *, int); | ||
| 41 | |||
| 42 | unsigned long flags; | ||
| 43 | unsigned long mclk_10khz; | ||
| 44 | }; | ||
| 45 | |||
| 46 | extern void pxa_set_camera_info(struct pxacamera_platform_data *); | ||
| 47 | |||
| 48 | #endif /* __ASM_ARCH_CAMERA_H_ */ | ||
diff --git a/include/asm-arm/arch-pxa/gumstix.h b/include/asm-arm/arch-pxa/gumstix.h new file mode 100644 index 000000000000..6fa85c4f94f8 --- /dev/null +++ b/include/asm-arm/arch-pxa/gumstix.h | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/gumstix.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | /* BTRESET - Reset line to Bluetooth module, active low signal. */ | ||
| 11 | #define GPIO_GUMSTIX_BTRESET 7 | ||
| 12 | #define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT) | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean | ||
| 17 | interrupt signal for determining cable presence. On the original gumstix, | ||
| 18 | this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F, | ||
| 19 | this moves to GPIO17 and GPIO37. */ | ||
| 20 | |||
| 21 | /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn | ||
| 22 | has detected a cable insertion; driven low otherwise. */ | ||
| 23 | |||
| 24 | #ifdef CONFIG_ARCH_GUMSTIX_ORIG | ||
| 25 | |||
| 26 | #define GPIO_GUMSTIX_USB_GPIOn 81 | ||
| 27 | #define GPIO_GUMSTIX_USB_GPIOx 83 | ||
| 28 | |||
| 29 | #else | ||
| 30 | |||
| 31 | #define GPIO_GUMSTIX_USB_GPIOn 35 | ||
| 32 | #define GPIO_GUMSTIX_USB_GPIOx 41 | ||
| 33 | |||
| 34 | #endif | ||
| 35 | |||
| 36 | /* usb state change */ | ||
| 37 | #define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) | ||
| 38 | |||
| 39 | #define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) | ||
| 40 | #define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) | ||
| 41 | #define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * SD/MMC definitions | ||
| 45 | */ | ||
| 46 | #define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ | ||
| 47 | #define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ | ||
| 48 | #define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * SMC Ethernet definitions | ||
| 52 | * ETH_RST provides a hardware reset line to the ethernet chip | ||
| 53 | * ETH is the IRQ line in from the ethernet chip to the PXA | ||
| 54 | */ | ||
| 55 | #define GPIO_GUMSTIX_ETH0_RST 80 | ||
| 56 | #define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT) | ||
| 57 | #define GPIO_GUMSTIX_ETH1_RST 52 | ||
| 58 | #define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT) | ||
| 59 | |||
| 60 | #define GPIO_GUMSTIX_ETH0 36 | ||
| 61 | #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) | ||
| 62 | #define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) | ||
| 63 | #define GPIO_GUMSTIX_ETH1 27 | ||
| 64 | #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) | ||
| 65 | #define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) | ||
| 66 | |||
| 67 | |||
| 68 | /* CF reset line */ | ||
| 69 | #define GPIO8_RESET 8 | ||
| 70 | |||
| 71 | /* CF slot 0 */ | ||
| 72 | #define GPIO4_nBVD1 4 | ||
| 73 | #define GPIO4_nSTSCHG GPIO4_nBVD1 | ||
| 74 | #define GPIO11_nCD 11 | ||
| 75 | #define GPIO26_PRDY_nBSY 26 | ||
| 76 | #define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG) | ||
| 77 | #define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD) | ||
| 78 | #define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY) | ||
| 79 | |||
| 80 | /* CF slot 1 */ | ||
| 81 | #define GPIO18_nBVD1 18 | ||
| 82 | #define GPIO18_nSTSCHG GPIO18_nBVD1 | ||
| 83 | #define GPIO36_nCD 36 | ||
| 84 | #define GPIO27_PRDY_nBSY 27 | ||
| 85 | #define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG) | ||
| 86 | #define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD) | ||
| 87 | #define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY) | ||
| 88 | |||
| 89 | /* CF GPIO line modes */ | ||
| 90 | #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) | ||
| 91 | #define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT) | ||
| 92 | #define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN) | ||
| 93 | #define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN) | ||
| 94 | #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) | ||
| 95 | #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) | ||
| 96 | #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) | ||
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h index 748406f384c2..99f4f423a8e1 100644 --- a/include/asm-arm/arch-pxa/irda.h +++ b/include/asm-arm/arch-pxa/irda.h | |||
| @@ -10,6 +10,8 @@ | |||
| 10 | struct pxaficp_platform_data { | 10 | struct pxaficp_platform_data { |
| 11 | int transceiver_cap; | 11 | int transceiver_cap; |
| 12 | void (*transceiver_mode)(struct device *dev, int mode); | 12 | void (*transceiver_mode)(struct device *dev, int mode); |
| 13 | int (*startup)(struct device *dev); | ||
| 14 | void (*shutdown)(struct device *dev); | ||
| 13 | }; | 15 | }; |
| 14 | 16 | ||
| 15 | extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); | 17 | extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); |
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index c562b972a4a6..50c77eacbd5e 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h | |||
| @@ -181,7 +181,8 @@ | |||
| 181 | #elif defined(CONFIG_ARCH_LUBBOCK) || \ | 181 | #elif defined(CONFIG_ARCH_LUBBOCK) || \ |
| 182 | defined(CONFIG_MACH_LOGICPD_PXA270) || \ | 182 | defined(CONFIG_MACH_LOGICPD_PXA270) || \ |
| 183 | defined(CONFIG_MACH_MAINSTONE) || \ | 183 | defined(CONFIG_MACH_MAINSTONE) || \ |
| 184 | defined(CONFIG_MACH_PCM027) | 184 | defined(CONFIG_MACH_PCM027) || \ |
| 185 | defined(CONFIG_MACH_MAGICIAN) | ||
| 185 | #define NR_IRQS (IRQ_BOARD_END) | 186 | #define NR_IRQS (IRQ_BOARD_END) |
| 186 | #else | 187 | #else |
| 187 | #define NR_IRQS (IRQ_BOARD_START) | 188 | #define NR_IRQS (IRQ_BOARD_START) |
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h index 337f51f06b3a..b34fd5683e2d 100644 --- a/include/asm-arm/arch-pxa/magician.h +++ b/include/asm-arm/arch-pxa/magician.h | |||
| @@ -12,7 +12,8 @@ | |||
| 12 | #ifndef _MAGICIAN_H_ | 12 | #ifndef _MAGICIAN_H_ |
| 13 | #define _MAGICIAN_H_ | 13 | #define _MAGICIAN_H_ |
| 14 | 14 | ||
| 15 | #include <asm/arch/pxa-regs.h> | 15 | #include <asm/arch/irqs.h> |
| 16 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 16 | 17 | ||
| 17 | /* | 18 | /* |
| 18 | * PXA GPIOs | 19 | * PXA GPIOs |
| @@ -34,6 +35,7 @@ | |||
| 34 | #define GPIO48_MAGICIAN_UNKNOWN 48 | 35 | #define GPIO48_MAGICIAN_UNKNOWN 48 |
| 35 | #define GPIO56_MAGICIAN_UNKNOWN 56 | 36 | #define GPIO56_MAGICIAN_UNKNOWN 56 |
| 36 | #define GPIO57_MAGICIAN_CAM_RESET 57 | 37 | #define GPIO57_MAGICIAN_CAM_RESET 57 |
| 38 | #define GPIO75_MAGICIAN_SAMSUNG_POWER 75 | ||
| 37 | #define GPIO83_MAGICIAN_nIR_EN 83 | 39 | #define GPIO83_MAGICIAN_nIR_EN 83 |
| 38 | #define GPIO86_MAGICIAN_GSM_RESET 86 | 40 | #define GPIO86_MAGICIAN_GSM_RESET 86 |
| 39 | #define GPIO87_MAGICIAN_GSM_SELECT 87 | 41 | #define GPIO87_MAGICIAN_GSM_SELECT 87 |
| @@ -81,6 +83,7 @@ | |||
| 81 | #define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT) | 83 | #define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT) |
| 82 | #define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT) | 84 | #define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT) |
| 83 | #define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT) | 85 | #define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT) |
| 86 | #define GPIO75_MAGICIAN_SAMSUNG_POWER_MD (75 | GPIO_OUT) | ||
| 84 | #define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT) | 87 | #define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT) |
| 85 | #define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT) | 88 | #define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT) |
| 86 | #define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT) | 89 | #define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT) |
| @@ -108,4 +111,56 @@ | |||
| 108 | #define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT) | 111 | #define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT) |
| 109 | #define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT) | 112 | #define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT) |
| 110 | 113 | ||
| 114 | /* | ||
| 115 | * CPLD IRQs | ||
| 116 | */ | ||
| 117 | |||
| 118 | #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) | ||
| 119 | #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) | ||
| 120 | #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) | ||
| 121 | #define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3) | ||
| 122 | |||
| 123 | /* | ||
| 124 | * CPLD EGPIOs | ||
| 125 | */ | ||
| 126 | |||
| 127 | #define MAGICIAN_EGPIO_BASE 0x80 /* GPIO_BOARD_START */ | ||
| 128 | #define MAGICIAN_EGPIO(reg,bit) \ | ||
| 129 | (MAGICIAN_EGPIO_BASE + 8*reg + bit) | ||
| 130 | |||
| 131 | /* output */ | ||
| 132 | |||
| 133 | #define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2) | ||
| 134 | #define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5) | ||
| 135 | #define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6) | ||
| 136 | #define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7) | ||
| 137 | #define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0) | ||
| 138 | #define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1) | ||
| 139 | #define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2) | ||
| 140 | #define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3) | ||
| 141 | #define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4) | ||
| 142 | #define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5) | ||
| 143 | #define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6) | ||
| 144 | #define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7) | ||
| 145 | #define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0) | ||
| 146 | #define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1) | ||
| 147 | #define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2) | ||
| 148 | #define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3) | ||
| 149 | #define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4) | ||
| 150 | #define EGPIO_MAGICIAN_CHARGE_EN MAGICIAN_EGPIO(2, 5) | ||
| 151 | #define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7) | ||
| 152 | |||
| 153 | /* input */ | ||
| 154 | |||
| 155 | #define EGPIO_MAGICIAN_CABLE_STATE_AC MAGICIAN_EGPIO(4, 0) | ||
| 156 | #define EGPIO_MAGICIAN_CABLE_STATE_USB MAGICIAN_EGPIO(4, 1) | ||
| 157 | |||
| 158 | #define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0) | ||
| 159 | #define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1) | ||
| 160 | #define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2) | ||
| 161 | #define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3) | ||
| 162 | #define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4) | ||
| 163 | |||
| 164 | #define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1) | ||
| 165 | |||
| 111 | #endif /* _MAGICIAN_H_ */ | 166 | #endif /* _MAGICIAN_H_ */ |
diff --git a/include/asm-arm/arch-pxa/mfp-pxa25x.h b/include/asm-arm/arch-pxa/mfp-pxa25x.h new file mode 100644 index 000000000000..0499323010ba --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa25x.h | |||
| @@ -0,0 +1,161 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA25X_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA25X_H | ||
| 3 | |||
| 4 | #include <asm/arch/mfp.h> | ||
| 5 | #include <asm/arch/mfp-pxa2xx.h> | ||
| 6 | |||
| 7 | /* GPIO */ | ||
| 8 | #define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0) | ||
| 9 | #define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) | ||
| 10 | #define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) | ||
| 11 | #define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0) | ||
| 12 | #define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0) | ||
| 13 | #define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0) | ||
| 14 | #define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0) | ||
| 15 | |||
| 16 | #define GPIO1_RST MFP_CFG_IN(GPIO1, AF1) | ||
| 17 | |||
| 18 | /* Crystal and Clock Signals */ | ||
| 19 | #define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) | ||
| 20 | #define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) | ||
| 21 | #define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) | ||
| 22 | #define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) | ||
| 23 | #define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) | ||
| 24 | #define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) | ||
| 25 | #define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW) | ||
| 26 | |||
| 27 | /* SDRAM and Static Memory I/O Signals */ | ||
| 28 | #define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) | ||
| 29 | #define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) | ||
| 30 | #define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) | ||
| 31 | #define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) | ||
| 32 | #define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) | ||
| 33 | |||
| 34 | /* Miscellaneous I/O and DMA Signals */ | ||
| 35 | #define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) | ||
| 36 | #define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) | ||
| 37 | #define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1) | ||
| 38 | |||
| 39 | /* Alternate Bus Master Mode I/O Signals */ | ||
| 40 | #define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW) | ||
| 41 | #define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW) | ||
| 42 | #define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1) | ||
| 43 | #define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1) | ||
| 44 | |||
| 45 | /* PC CARD */ | ||
| 46 | #define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH) | ||
| 47 | #define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH) | ||
| 48 | #define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) | ||
| 49 | #define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) | ||
| 50 | #define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) | ||
| 51 | #define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) | ||
| 52 | #define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) | ||
| 53 | #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) | ||
| 54 | #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) | ||
| 55 | #define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) | ||
| 56 | |||
| 57 | /* FFUART */ | ||
| 58 | #define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) | ||
| 59 | #define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) | ||
| 60 | #define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) | ||
| 61 | #define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) | ||
| 62 | #define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) | ||
| 63 | #define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) | ||
| 64 | #define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) | ||
| 65 | #define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) | ||
| 66 | |||
| 67 | /* BTUART */ | ||
| 68 | #define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) | ||
| 69 | #define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) | ||
| 70 | #define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) | ||
| 71 | #define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) | ||
| 72 | |||
| 73 | /* STUART */ | ||
| 74 | #define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) | ||
| 75 | #define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) | ||
| 76 | |||
| 77 | /* HWUART */ | ||
| 78 | #define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3) | ||
| 79 | #define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH) | ||
| 80 | #define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3) | ||
| 81 | #define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH) | ||
| 82 | #define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH) | ||
| 83 | #define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1) | ||
| 84 | #define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1) | ||
| 85 | #define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH) | ||
| 86 | |||
| 87 | /* FICP */ | ||
| 88 | #define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) | ||
| 89 | #define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) | ||
| 90 | |||
| 91 | /* PWM 0/1 */ | ||
| 92 | #define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) | ||
| 93 | #define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) | ||
| 94 | |||
| 95 | /* AC97 */ | ||
| 96 | #define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) | ||
| 97 | #define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) | ||
| 98 | #define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) | ||
| 99 | #define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) | ||
| 100 | #define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1) | ||
| 101 | |||
| 102 | /* I2S */ | ||
| 103 | #define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) | ||
| 104 | #define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) | ||
| 105 | #define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) | ||
| 106 | #define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) | ||
| 107 | #define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) | ||
| 108 | #define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) | ||
| 109 | |||
| 110 | /* SSP 1 */ | ||
| 111 | #define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) | ||
| 112 | #define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW) | ||
| 113 | #define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) | ||
| 114 | #define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) | ||
| 115 | #define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1) | ||
| 116 | |||
| 117 | /* SSP 2 - NSSP */ | ||
| 118 | #define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) | ||
| 119 | #define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1) | ||
| 120 | #define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW) | ||
| 121 | #define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1) | ||
| 122 | #define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW) | ||
| 123 | #define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2) | ||
| 124 | #define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW) | ||
| 125 | #define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2) | ||
| 126 | |||
| 127 | /* MMC */ | ||
| 128 | #define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW) | ||
| 129 | #define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW) | ||
| 130 | #define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) | ||
| 131 | #define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW) | ||
| 132 | #define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) | ||
| 133 | #define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) | ||
| 134 | #define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW) | ||
| 135 | #define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW) | ||
| 136 | #define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW) | ||
| 137 | #define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW) | ||
| 138 | |||
| 139 | /* LCD */ | ||
| 140 | #define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) | ||
| 141 | #define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) | ||
| 142 | #define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) | ||
| 143 | #define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) | ||
| 144 | #define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) | ||
| 145 | #define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) | ||
| 146 | #define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) | ||
| 147 | #define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) | ||
| 148 | #define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) | ||
| 149 | #define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) | ||
| 150 | #define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) | ||
| 151 | #define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) | ||
| 152 | #define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) | ||
| 153 | #define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) | ||
| 154 | #define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) | ||
| 155 | #define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) | ||
| 156 | #define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) | ||
| 157 | #define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) | ||
| 158 | #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) | ||
| 159 | #define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) | ||
| 160 | |||
| 161 | #endif /* __ASM_ARCH_MFP_PXA25X_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h new file mode 100644 index 000000000000..eb6eaa174f8d --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa27x.h | |||
| @@ -0,0 +1,432 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA27X_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA27X_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * NOTE: for those special-function bidirectional GPIOs, as described | ||
| 6 | * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input | ||
| 7 | * alternative is preserved, the direction is actually selected by the | ||
| 8 | * specific controller, and this should work in most cases. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/mfp.h> | ||
| 12 | #include <asm/arch/mfp-pxa2xx.h> | ||
| 13 | |||
| 14 | /* GPIO */ | ||
| 15 | #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) | ||
| 16 | #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) | ||
| 17 | #define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) | ||
| 18 | #define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) | ||
| 19 | #define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) | ||
| 20 | #define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) | ||
| 21 | #define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) | ||
| 22 | #define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) | ||
| 23 | #define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) | ||
| 24 | #define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) | ||
| 25 | #define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) | ||
| 26 | #define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) | ||
| 27 | #define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) | ||
| 28 | #define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) | ||
| 29 | #define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) | ||
| 30 | #define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) | ||
| 31 | #define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) | ||
| 32 | #define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) | ||
| 33 | #define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) | ||
| 34 | #define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) | ||
| 35 | #define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) | ||
| 36 | #define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) | ||
| 37 | #define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) | ||
| 38 | #define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) | ||
| 39 | #define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) | ||
| 40 | #define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) | ||
| 41 | #define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) | ||
| 42 | #define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) | ||
| 43 | #define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) | ||
| 44 | #define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) | ||
| 45 | #define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) | ||
| 46 | #define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) | ||
| 47 | #define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) | ||
| 48 | #define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) | ||
| 49 | #define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) | ||
| 50 | #define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) | ||
| 51 | |||
| 52 | /* Crystal and Clock Signals */ | ||
| 53 | #define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) | ||
| 54 | #define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) | ||
| 55 | #define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) | ||
| 56 | #define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) | ||
| 57 | #define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) | ||
| 58 | |||
| 59 | /* OS Timer Signals */ | ||
| 60 | #define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) | ||
| 61 | #define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) | ||
| 62 | #define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) | ||
| 63 | #define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) | ||
| 64 | #define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) | ||
| 65 | #define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) | ||
| 66 | |||
| 67 | /* SDRAM and Static Memory I/O Signals */ | ||
| 68 | #define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) | ||
| 69 | #define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) | ||
| 70 | #define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) | ||
| 71 | #define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) | ||
| 72 | #define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) | ||
| 73 | #define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) | ||
| 74 | #define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) | ||
| 75 | |||
| 76 | /* Miscellaneous I/O and DMA Signals */ | ||
| 77 | #define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) | ||
| 78 | #define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) | ||
| 79 | #define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) | ||
| 80 | #define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) | ||
| 81 | #define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) | ||
| 82 | #define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) | ||
| 83 | #define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) | ||
| 84 | #define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) | ||
| 85 | #define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) | ||
| 86 | #define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) | ||
| 87 | #define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) | ||
| 88 | |||
| 89 | /* Alternate Bus Master Mode I/O Signals */ | ||
| 90 | #define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) | ||
| 91 | #define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) | ||
| 92 | #define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) | ||
| 93 | #define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) | ||
| 94 | #define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) | ||
| 95 | #define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) | ||
| 96 | #define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) | ||
| 97 | #define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) | ||
| 98 | |||
| 99 | /* PC CARD */ | ||
| 100 | #define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) | ||
| 101 | #define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) | ||
| 102 | #define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) | ||
| 103 | #define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) | ||
| 104 | #define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) | ||
| 105 | #define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) | ||
| 106 | #define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) | ||
| 107 | #define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) | ||
| 108 | #define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) | ||
| 109 | #define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) | ||
| 110 | #define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) | ||
| 111 | #define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) | ||
| 112 | #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) | ||
| 113 | #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) | ||
| 114 | #define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) | ||
| 115 | |||
| 116 | /* I2C */ | ||
| 117 | #define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) | ||
| 118 | #define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) | ||
| 119 | |||
| 120 | /* FFUART */ | ||
| 121 | #define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) | ||
| 122 | #define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) | ||
| 123 | #define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) | ||
| 124 | #define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) | ||
| 125 | #define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) | ||
| 126 | #define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) | ||
| 127 | #define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) | ||
| 128 | #define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) | ||
| 129 | #define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) | ||
| 130 | #define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) | ||
| 131 | #define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) | ||
| 132 | #define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) | ||
| 133 | #define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) | ||
| 134 | #define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) | ||
| 135 | #define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) | ||
| 136 | #define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) | ||
| 137 | #define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) | ||
| 138 | #define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) | ||
| 139 | #define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) | ||
| 140 | #define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) | ||
| 141 | #define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) | ||
| 142 | #define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) | ||
| 143 | #define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) | ||
| 144 | #define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) | ||
| 145 | #define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) | ||
| 146 | #define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) | ||
| 147 | #define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) | ||
| 148 | #define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) | ||
| 149 | #define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) | ||
| 150 | |||
| 151 | /* BTUART */ | ||
| 152 | #define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) | ||
| 153 | #define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) | ||
| 154 | #define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) | ||
| 155 | #define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) | ||
| 156 | |||
| 157 | /* STUART */ | ||
| 158 | #define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) | ||
| 159 | #define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) | ||
| 160 | |||
| 161 | /* FICP */ | ||
| 162 | #define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) | ||
| 163 | #define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) | ||
| 164 | #define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) | ||
| 165 | #define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) | ||
| 166 | |||
| 167 | /* PWM 0/1/2/3 */ | ||
| 168 | #define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) | ||
| 169 | #define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) | ||
| 170 | #define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) | ||
| 171 | #define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) | ||
| 172 | #define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) | ||
| 173 | #define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) | ||
| 174 | #define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) | ||
| 175 | #define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) | ||
| 176 | #define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) | ||
| 177 | #define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) | ||
| 178 | |||
| 179 | /* AC97 */ | ||
| 180 | #define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) | ||
| 181 | #define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) | ||
| 182 | #define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) | ||
| 183 | #define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) | ||
| 184 | #define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) | ||
| 185 | #define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) | ||
| 186 | #define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) | ||
| 187 | #define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) | ||
| 188 | #define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) | ||
| 189 | #define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) | ||
| 190 | #define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) | ||
| 191 | #define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) | ||
| 192 | #define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) | ||
| 193 | |||
| 194 | /* I2S */ | ||
| 195 | #define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) | ||
| 196 | #define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) | ||
| 197 | #define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) | ||
| 198 | #define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) | ||
| 199 | #define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) | ||
| 200 | #define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) | ||
| 201 | |||
| 202 | /* SSP 1 */ | ||
| 203 | #define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) | ||
| 204 | #define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) | ||
| 205 | #define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) | ||
| 206 | #define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) | ||
| 207 | #define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) | ||
| 208 | #define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) | ||
| 209 | #define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) | ||
| 210 | #define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) | ||
| 211 | #define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) | ||
| 212 | #define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) | ||
| 213 | |||
| 214 | /* SSP 2 */ | ||
| 215 | #define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) | ||
| 216 | #define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) | ||
| 217 | #define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) | ||
| 218 | #define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) | ||
| 219 | #define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) | ||
| 220 | #define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) | ||
| 221 | #define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) | ||
| 222 | #define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) | ||
| 223 | #define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) | ||
| 224 | #define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) | ||
| 225 | #define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) | ||
| 226 | #define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) | ||
| 227 | #define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) | ||
| 228 | #define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) | ||
| 229 | #define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) | ||
| 230 | #define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) | ||
| 231 | #define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) | ||
| 232 | #define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) | ||
| 233 | #define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) | ||
| 234 | #define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) | ||
| 235 | #define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) | ||
| 236 | #define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) | ||
| 237 | #define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) | ||
| 238 | |||
| 239 | /* SSP 3 */ | ||
| 240 | #define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) | ||
| 241 | #define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) | ||
| 242 | #define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) | ||
| 243 | #define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) | ||
| 244 | #define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) | ||
| 245 | #define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) | ||
| 246 | #define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) | ||
| 247 | #define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) | ||
| 248 | #define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) | ||
| 249 | #define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) | ||
| 250 | #define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) | ||
| 251 | #define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) | ||
| 252 | #define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) | ||
| 253 | #define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) | ||
| 254 | |||
| 255 | /* MMC */ | ||
| 256 | #define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) | ||
| 257 | #define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) | ||
| 258 | #define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) | ||
| 259 | #define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) | ||
| 260 | #define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) | ||
| 261 | #define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) | ||
| 262 | |||
| 263 | /* LCD */ | ||
| 264 | #define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) | ||
| 265 | #define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) | ||
| 266 | #define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) | ||
| 267 | #define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) | ||
| 268 | #define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) | ||
| 269 | #define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) | ||
| 270 | #define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) | ||
| 271 | #define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) | ||
| 272 | #define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) | ||
| 273 | #define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) | ||
| 274 | #define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) | ||
| 275 | #define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) | ||
| 276 | #define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) | ||
| 277 | #define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) | ||
| 278 | #define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) | ||
| 279 | #define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) | ||
| 280 | #define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) | ||
| 281 | #define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) | ||
| 282 | #define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) | ||
| 283 | #define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) | ||
| 284 | #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) | ||
| 285 | #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) | ||
| 286 | #define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) | ||
| 287 | #define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) | ||
| 288 | |||
| 289 | /* Keypad */ | ||
| 290 | #define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) | ||
| 291 | #define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) | ||
| 292 | #define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) | ||
| 293 | #define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) | ||
| 294 | #define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) | ||
| 295 | #define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) | ||
| 296 | #define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) | ||
| 297 | #define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) | ||
| 298 | #define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) | ||
| 299 | #define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) | ||
| 300 | #define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) | ||
| 301 | #define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) | ||
| 302 | #define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) | ||
| 303 | #define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) | ||
| 304 | #define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) | ||
| 305 | #define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) | ||
| 306 | #define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) | ||
| 307 | #define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) | ||
| 308 | #define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) | ||
| 309 | #define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) | ||
| 310 | #define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) | ||
| 311 | #define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) | ||
| 312 | #define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) | ||
| 313 | #define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) | ||
| 314 | #define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) | ||
| 315 | #define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) | ||
| 316 | #define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) | ||
| 317 | #define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) | ||
| 318 | #define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) | ||
| 319 | #define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) | ||
| 320 | #define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) | ||
| 321 | #define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) | ||
| 322 | #define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) | ||
| 323 | #define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) | ||
| 324 | #define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) | ||
| 325 | #define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) | ||
| 326 | |||
| 327 | /* USB P3 */ | ||
| 328 | #define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) | ||
| 329 | #define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) | ||
| 330 | #define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) | ||
| 331 | #define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) | ||
| 332 | #define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) | ||
| 333 | #define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) | ||
| 334 | #define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) | ||
| 335 | #define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) | ||
| 336 | #define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) | ||
| 337 | #define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) | ||
| 338 | |||
| 339 | /* USB P2 */ | ||
| 340 | #define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) | ||
| 341 | #define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) | ||
| 342 | #define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) | ||
| 343 | #define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) | ||
| 344 | #define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) | ||
| 345 | #define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) | ||
| 346 | #define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) | ||
| 347 | #define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) | ||
| 348 | #define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) | ||
| 349 | |||
| 350 | /* USB Host Port 1/2 */ | ||
| 351 | #define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) | ||
| 352 | #define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) | ||
| 353 | #define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) | ||
| 354 | #define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) | ||
| 355 | |||
| 356 | /* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ | ||
| 357 | #define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) | ||
| 358 | #define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) | ||
| 359 | #define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) | ||
| 360 | #define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) | ||
| 361 | #define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) | ||
| 362 | #define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) | ||
| 363 | #define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) | ||
| 364 | #define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) | ||
| 365 | #define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) | ||
| 366 | #define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) | ||
| 367 | #define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) | ||
| 368 | #define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) | ||
| 369 | #define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) | ||
| 370 | #define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) | ||
| 371 | #define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) | ||
| 372 | #define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) | ||
| 373 | #define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) | ||
| 374 | #define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) | ||
| 375 | #define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) | ||
| 376 | #define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) | ||
| 377 | #define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) | ||
| 378 | #define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) | ||
| 379 | #define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) | ||
| 380 | #define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) | ||
| 381 | #define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) | ||
| 382 | #define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) | ||
| 383 | #define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) | ||
| 384 | #define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) | ||
| 385 | #define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) | ||
| 386 | #define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) | ||
| 387 | #define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) | ||
| 388 | #define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) | ||
| 389 | #define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) | ||
| 390 | #define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) | ||
| 391 | #define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) | ||
| 392 | #define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) | ||
| 393 | #define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) | ||
| 394 | #define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) | ||
| 395 | #define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) | ||
| 396 | |||
| 397 | /* Universal Subscriber ID Interface */ | ||
| 398 | #define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) | ||
| 399 | #define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) | ||
| 400 | #define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) | ||
| 401 | #define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) | ||
| 402 | #define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) | ||
| 403 | #define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) | ||
| 404 | #define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) | ||
| 405 | #define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) | ||
| 406 | #define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) | ||
| 407 | #define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) | ||
| 408 | |||
| 409 | /* Mobile Scalable Link (MSL) Interface */ | ||
| 410 | #define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) | ||
| 411 | #define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) | ||
| 412 | #define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) | ||
| 413 | #define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) | ||
| 414 | #define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) | ||
| 415 | #define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) | ||
| 416 | #define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) | ||
| 417 | #define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) | ||
| 418 | #define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) | ||
| 419 | #define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) | ||
| 420 | #define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) | ||
| 421 | #define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) | ||
| 422 | #define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) | ||
| 423 | #define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) | ||
| 424 | |||
| 425 | /* Memory Stick Host Controller */ | ||
| 426 | #define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) | ||
| 427 | #define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) | ||
| 428 | #define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) | ||
| 429 | #define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) | ||
| 430 | |||
| 431 | extern int keypad_set_wake(unsigned int on); | ||
| 432 | #endif /* __ASM_ARCH_MFP_PXA27X_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h new file mode 100644 index 000000000000..db8d890d237c --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA2XX_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA2XX_H | ||
| 3 | |||
| 4 | #include <asm/arch/mfp.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: | ||
| 8 | * | ||
| 9 | * MFP_PIN(x) | ||
| 10 | * MFP_AFx | ||
| 11 | * MFP_LPM_DRIVE_{LOW, HIGH} | ||
| 12 | * MFP_LPM_EDGE_x | ||
| 13 | * | ||
| 14 | * other MFP_x bit definitions will be ignored | ||
| 15 | * | ||
| 16 | * and adds the below two bits specifically for pxa2xx: | ||
| 17 | * | ||
| 18 | * bit 23 - Input/Output (PXA2xx specific) | ||
| 19 | * bit 24 - Wakeup Enable(PXA2xx specific) | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define MFP_DIR_IN (0x0 << 23) | ||
| 23 | #define MFP_DIR_OUT (0x1 << 23) | ||
| 24 | #define MFP_DIR_MASK (0x1 << 23) | ||
| 25 | #define MFP_DIR(x) (((x) >> 23) & 0x1) | ||
| 26 | |||
| 27 | #define MFP_LPM_CAN_WAKEUP (0x1 << 24) | ||
| 28 | #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) | ||
| 29 | #define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) | ||
| 30 | #define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) | ||
| 31 | |||
| 32 | /* specifically for enabling wakeup on keypad GPIOs */ | ||
| 33 | #define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) | ||
| 34 | |||
| 35 | #define MFP_CFG_IN(pin, af) \ | ||
| 36 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ | ||
| 37 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) | ||
| 38 | |||
| 39 | /* NOTE: pins configured as output _must_ provide a low power state, | ||
| 40 | * and this state should help to minimize the power dissipation. | ||
| 41 | */ | ||
| 42 | #define MFP_CFG_OUT(pin, af, state) \ | ||
| 43 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 44 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) | ||
| 45 | |||
| 46 | /* Common configurations for pxa25x and pxa27x | ||
| 47 | * | ||
| 48 | * Note: pins configured as GPIO are always initialized to input | ||
| 49 | * so not to cause any side effect | ||
| 50 | */ | ||
| 51 | #define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) | ||
| 52 | #define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) | ||
| 53 | #define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) | ||
| 54 | #define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) | ||
| 55 | #define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) | ||
| 56 | #define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) | ||
| 57 | #define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) | ||
| 58 | #define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) | ||
| 59 | #define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) | ||
| 60 | #define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) | ||
| 61 | #define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) | ||
| 62 | #define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) | ||
| 63 | #define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) | ||
| 64 | #define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) | ||
| 65 | #define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) | ||
| 66 | #define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) | ||
| 67 | #define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) | ||
| 68 | #define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) | ||
| 69 | #define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) | ||
| 70 | #define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) | ||
| 71 | #define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) | ||
| 72 | #define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) | ||
| 73 | #define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) | ||
| 74 | #define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) | ||
| 75 | #define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) | ||
| 76 | #define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) | ||
| 77 | #define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) | ||
| 78 | #define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) | ||
| 79 | #define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) | ||
| 80 | #define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) | ||
| 81 | #define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) | ||
| 82 | #define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) | ||
| 83 | #define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) | ||
| 84 | #define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) | ||
| 85 | #define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) | ||
| 86 | #define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) | ||
| 87 | #define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) | ||
| 88 | #define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) | ||
| 89 | #define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) | ||
| 90 | #define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) | ||
| 91 | #define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) | ||
| 92 | #define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) | ||
| 93 | #define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) | ||
| 94 | #define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) | ||
| 95 | #define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) | ||
| 96 | #define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) | ||
| 97 | #define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) | ||
| 98 | #define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) | ||
| 99 | #define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) | ||
| 100 | #define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) | ||
| 101 | #define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) | ||
| 102 | #define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) | ||
| 103 | #define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) | ||
| 104 | #define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) | ||
| 105 | #define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) | ||
| 106 | #define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) | ||
| 107 | #define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) | ||
| 108 | #define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) | ||
| 109 | #define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) | ||
| 110 | #define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) | ||
| 111 | #define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) | ||
| 112 | #define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) | ||
| 113 | #define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) | ||
| 114 | #define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) | ||
| 115 | #define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) | ||
| 116 | #define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) | ||
| 117 | #define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) | ||
| 118 | #define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) | ||
| 119 | #define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) | ||
| 120 | #define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) | ||
| 121 | #define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) | ||
| 122 | #define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) | ||
| 123 | #define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) | ||
| 124 | #define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) | ||
| 125 | #define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) | ||
| 126 | #define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) | ||
| 127 | #define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) | ||
| 128 | #define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) | ||
| 129 | |||
| 130 | extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 131 | extern int gpio_set_wake(unsigned int gpio, unsigned int on); | ||
| 132 | #endif /* __ASM_ARCH_MFP_PXA2XX_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 2357a73340d4..a322012f16ac 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
| @@ -1129,6 +1129,11 @@ | |||
| 1129 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | 1129 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ |
| 1130 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | 1130 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ |
| 1131 | 1131 | ||
| 1132 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 1133 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 1134 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 1135 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 1136 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 1132 | 1137 | ||
| 1133 | /* | 1138 | /* |
| 1134 | * General Purpose I/O | 1139 | * General Purpose I/O |
| @@ -1200,12 +1205,6 @@ | |||
| 1200 | 1205 | ||
| 1201 | /* Interrupt Controller */ | 1206 | /* Interrupt Controller */ |
| 1202 | 1207 | ||
| 1203 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 1204 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 1205 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 1206 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 1207 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 1208 | |||
| 1209 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | 1208 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
| 1210 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | 1209 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) |
| 1211 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | 1210 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) |
| @@ -1237,267 +1236,6 @@ | |||
| 1237 | 1236 | ||
| 1238 | #endif | 1237 | #endif |
| 1239 | 1238 | ||
| 1240 | |||
| 1241 | /* GPIO alternate function assignments */ | ||
| 1242 | |||
| 1243 | #define GPIO1_RST 1 /* reset */ | ||
| 1244 | #define GPIO6_MMCCLK 6 /* MMC Clock */ | ||
| 1245 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ | ||
| 1246 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ | ||
| 1247 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ | ||
| 1248 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ | ||
| 1249 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ | ||
| 1250 | #define GPIO12_32KHz 12 /* 32 kHz out */ | ||
| 1251 | #define GPIO13_MBGNT 13 /* memory controller grant */ | ||
| 1252 | #define GPIO14_MBREQ 14 /* alternate bus master request */ | ||
| 1253 | #define GPIO15_nCS_1 15 /* chip select 1 */ | ||
| 1254 | #define GPIO16_PWM0 16 /* PWM0 output */ | ||
| 1255 | #define GPIO17_PWM1 17 /* PWM1 output */ | ||
| 1256 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ | ||
| 1257 | #define GPIO19_DREQ1 19 /* External DMA Request */ | ||
| 1258 | #define GPIO20_DREQ0 20 /* External DMA Request */ | ||
| 1259 | #define GPIO23_SCLK 23 /* SSP clock */ | ||
| 1260 | #define GPIO24_SFRM 24 /* SSP Frame */ | ||
| 1261 | #define GPIO25_STXD 25 /* SSP transmit */ | ||
| 1262 | #define GPIO26_SRXD 26 /* SSP receive */ | ||
| 1263 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | ||
| 1264 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | ||
| 1265 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | ||
| 1266 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | ||
| 1267 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ | ||
| 1268 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ | ||
| 1269 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ | ||
| 1270 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ | ||
| 1271 | #define GPIO33_nCS_5 33 /* chip select 5 */ | ||
| 1272 | #define GPIO34_FFRXD 34 /* FFUART receive */ | ||
| 1273 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ | ||
| 1274 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ | ||
| 1275 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ | ||
| 1276 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ | ||
| 1277 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ | ||
| 1278 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ | ||
| 1279 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ | ||
| 1280 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | ||
| 1281 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | ||
| 1282 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | ||
| 1283 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | ||
| 1284 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | ||
| 1285 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | ||
| 1286 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | ||
| 1287 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | ||
| 1288 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | ||
| 1289 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | ||
| 1290 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | ||
| 1291 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | ||
| 1292 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | ||
| 1293 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | ||
| 1294 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | ||
| 1295 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | ||
| 1296 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | ||
| 1297 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | ||
| 1298 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ | ||
| 1299 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ | ||
| 1300 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ | ||
| 1301 | #define GPIO53_MMCCLK 53 /* MMC Clock */ | ||
| 1302 | #define GPIO54_MMCCLK 54 /* MMC Clock */ | ||
| 1303 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ | ||
| 1304 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ | ||
| 1305 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ | ||
| 1306 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ | ||
| 1307 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ | ||
| 1308 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ | ||
| 1309 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ | ||
| 1310 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ | ||
| 1311 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ | ||
| 1312 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ | ||
| 1313 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ | ||
| 1314 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ | ||
| 1315 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ | ||
| 1316 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ | ||
| 1317 | #define GPIO66_MBREQ 66 /* alternate bus master req */ | ||
| 1318 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ | ||
| 1319 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ | ||
| 1320 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ | ||
| 1321 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ | ||
| 1322 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ | ||
| 1323 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ | ||
| 1324 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ | ||
| 1325 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ | ||
| 1326 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ | ||
| 1327 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ | ||
| 1328 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ | ||
| 1329 | #define GPIO72_32kHz 72 /* 32 kHz clock */ | ||
| 1330 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ | ||
| 1331 | #define GPIO73_MBGNT 73 /* Memory controller grant */ | ||
| 1332 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ | ||
| 1333 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ | ||
| 1334 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ | ||
| 1335 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ | ||
| 1336 | #define GPIO78_nCS_2 78 /* chip select 2 */ | ||
| 1337 | #define GPIO79_nCS_3 79 /* chip select 3 */ | ||
| 1338 | #define GPIO80_nCS_4 80 /* chip select 4 */ | ||
| 1339 | #define GPIO81_NSCLK 81 /* NSSP clock */ | ||
| 1340 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | ||
| 1341 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | ||
| 1342 | #define GPIO84_NSRXD 84 /* NSSP receive */ | ||
| 1343 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | ||
| 1344 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ | ||
| 1345 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | ||
| 1346 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ | ||
| 1347 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ | ||
| 1348 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ | ||
| 1349 | #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ | ||
| 1350 | #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ | ||
| 1351 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ | ||
| 1352 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ | ||
| 1353 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ | ||
| 1354 | |||
| 1355 | /* GPIO alternate function mode & direction */ | ||
| 1356 | |||
| 1357 | #define GPIO_IN 0x000 | ||
| 1358 | #define GPIO_OUT 0x080 | ||
| 1359 | #define GPIO_ALT_FN_1_IN 0x100 | ||
| 1360 | #define GPIO_ALT_FN_1_OUT 0x180 | ||
| 1361 | #define GPIO_ALT_FN_2_IN 0x200 | ||
| 1362 | #define GPIO_ALT_FN_2_OUT 0x280 | ||
| 1363 | #define GPIO_ALT_FN_3_IN 0x300 | ||
| 1364 | #define GPIO_ALT_FN_3_OUT 0x380 | ||
| 1365 | #define GPIO_MD_MASK_NR 0x07f | ||
| 1366 | #define GPIO_MD_MASK_DIR 0x080 | ||
| 1367 | #define GPIO_MD_MASK_FN 0x300 | ||
| 1368 | #define GPIO_DFLT_LOW 0x400 | ||
| 1369 | #define GPIO_DFLT_HIGH 0x800 | ||
| 1370 | |||
| 1371 | #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) | ||
| 1372 | #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) | ||
| 1373 | #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) | ||
| 1374 | #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) | ||
| 1375 | #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) | ||
| 1376 | #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) | ||
| 1377 | #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) | ||
| 1378 | #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) | ||
| 1379 | #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) | ||
| 1380 | #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) | ||
| 1381 | #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) | ||
| 1382 | #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) | ||
| 1383 | #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) | ||
| 1384 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) | ||
| 1385 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) | ||
| 1386 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) | ||
| 1387 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) | ||
| 1388 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) | ||
| 1389 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) | ||
| 1390 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) | ||
| 1391 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) | ||
| 1392 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) | ||
| 1393 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) | ||
| 1394 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) | ||
| 1395 | #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) | ||
| 1396 | #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) | ||
| 1397 | #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) | ||
| 1398 | #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) | ||
| 1399 | #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) | ||
| 1400 | #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) | ||
| 1401 | #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) | ||
| 1402 | #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) | ||
| 1403 | #define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT) | ||
| 1404 | #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) | ||
| 1405 | #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) | ||
| 1406 | #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) | ||
| 1407 | #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) | ||
| 1408 | #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) | ||
| 1409 | #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) | ||
| 1410 | #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) | ||
| 1411 | #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) | ||
| 1412 | #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) | ||
| 1413 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) | ||
| 1414 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) | ||
| 1415 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | ||
| 1416 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | ||
| 1417 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | ||
| 1418 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 1419 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | ||
| 1420 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | ||
| 1421 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | ||
| 1422 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | ||
| 1423 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | ||
| 1424 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | ||
| 1425 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | ||
| 1426 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | ||
| 1427 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | ||
| 1428 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 1429 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | ||
| 1430 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 1431 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | ||
| 1432 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | ||
| 1433 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | ||
| 1434 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 1435 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | ||
| 1436 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | ||
| 1437 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) | ||
| 1438 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 1439 | #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) | ||
| 1440 | #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) | ||
| 1441 | #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 1442 | #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 1443 | #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) | ||
| 1444 | #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) | ||
| 1445 | #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) | ||
| 1446 | #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) | ||
| 1447 | #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) | ||
| 1448 | #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) | ||
| 1449 | #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) | ||
| 1450 | #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) | ||
| 1451 | #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) | ||
| 1452 | #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) | ||
| 1453 | #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) | ||
| 1454 | #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) | ||
| 1455 | #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) | ||
| 1456 | #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) | ||
| 1457 | #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) | ||
| 1458 | #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) | ||
| 1459 | #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) | ||
| 1460 | #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) | ||
| 1461 | #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) | ||
| 1462 | #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) | ||
| 1463 | #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) | ||
| 1464 | #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) | ||
| 1465 | #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) | ||
| 1466 | #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) | ||
| 1467 | #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) | ||
| 1468 | #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) | ||
| 1469 | #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) | ||
| 1470 | #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) | ||
| 1471 | #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) | ||
| 1472 | #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) | ||
| 1473 | #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) | ||
| 1474 | #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) | ||
| 1475 | #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) | ||
| 1476 | #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) | ||
| 1477 | #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) | ||
| 1478 | #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) | ||
| 1479 | #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) | ||
| 1480 | #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) | ||
| 1481 | #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) | ||
| 1482 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) | ||
| 1483 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) | ||
| 1484 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) | ||
| 1485 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) | ||
| 1486 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | ||
| 1487 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | ||
| 1488 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | ||
| 1489 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) | ||
| 1490 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) | ||
| 1491 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 1492 | #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 1493 | #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 1494 | #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 1495 | #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) | ||
| 1496 | #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) | ||
| 1497 | #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) | ||
| 1498 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) | ||
| 1499 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) | ||
| 1500 | |||
| 1501 | /* | 1239 | /* |
| 1502 | * Power Manager | 1240 | * Power Manager |
| 1503 | */ | 1241 | */ |
| @@ -1866,62 +1604,6 @@ | |||
| 1866 | 1604 | ||
| 1867 | #ifdef CONFIG_PXA27x | 1605 | #ifdef CONFIG_PXA27x |
| 1868 | 1606 | ||
| 1869 | /* | ||
| 1870 | * Keypad | ||
| 1871 | */ | ||
| 1872 | #define KPC __REG(0x41500000) /* Keypad Interface Control register */ | ||
| 1873 | #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ | ||
| 1874 | #define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */ | ||
| 1875 | #define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */ | ||
| 1876 | #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ | ||
| 1877 | #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ | ||
| 1878 | #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ | ||
| 1879 | #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ | ||
| 1880 | #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ | ||
| 1881 | #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ | ||
| 1882 | |||
| 1883 | #define KPC_AS (0x1 << 30) /* Automatic Scan bit */ | ||
| 1884 | #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ | ||
| 1885 | #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ | ||
| 1886 | #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ | ||
| 1887 | #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ | ||
| 1888 | #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ | ||
| 1889 | #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ | ||
| 1890 | #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ | ||
| 1891 | #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ | ||
| 1892 | #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ | ||
| 1893 | #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ | ||
| 1894 | #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ | ||
| 1895 | #define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7) | ||
| 1896 | #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ | ||
| 1897 | #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ | ||
| 1898 | #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */ | ||
| 1899 | #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ | ||
| 1900 | #define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */ | ||
| 1901 | #define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */ | ||
| 1902 | #define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */ | ||
| 1903 | #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ | ||
| 1904 | #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ | ||
| 1905 | |||
| 1906 | #define KPDK_DKP (0x1 << 31) | ||
| 1907 | #define KPDK_DK7 (0x1 << 7) | ||
| 1908 | #define KPDK_DK6 (0x1 << 6) | ||
| 1909 | #define KPDK_DK5 (0x1 << 5) | ||
| 1910 | #define KPDK_DK4 (0x1 << 4) | ||
| 1911 | #define KPDK_DK3 (0x1 << 3) | ||
| 1912 | #define KPDK_DK2 (0x1 << 2) | ||
| 1913 | #define KPDK_DK1 (0x1 << 1) | ||
| 1914 | #define KPDK_DK0 (0x1 << 0) | ||
| 1915 | |||
| 1916 | #define KPREC_OF1 (0x1 << 31) | ||
| 1917 | #define kPREC_UF1 (0x1 << 30) | ||
| 1918 | #define KPREC_OF0 (0x1 << 15) | ||
| 1919 | #define KPREC_UF0 (0x1 << 14) | ||
| 1920 | |||
| 1921 | #define KPMK_MKP (0x1 << 31) | ||
| 1922 | #define KPAS_SO (0x1 << 31) | ||
| 1923 | #define KPASMKPx_SO (0x1 << 31) | ||
| 1924 | |||
| 1925 | /* Camera Interface */ | 1607 | /* Camera Interface */ |
| 1926 | #define CICR0 __REG(0x50000000) | 1608 | #define CICR0 __REG(0x50000000) |
| 1927 | #define CICR1 __REG(0x50000004) | 1609 | #define CICR1 __REG(0x50000004) |
| @@ -1953,7 +1635,7 @@ | |||
| 1953 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | 1635 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ |
| 1954 | 1636 | ||
| 1955 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | 1637 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ |
| 1956 | #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ | 1638 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ |
| 1957 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | 1639 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ |
| 1958 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | 1640 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ |
| 1959 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | 1641 | #define CICR1_RGB_F (1 << 11) /* RGB format */ |
diff --git a/include/asm-arm/arch-pxa/pxa27x_keypad.h b/include/asm-arm/arch-pxa/pxa27x_keypad.h index 644f7609b523..d5a48a96dea7 100644 --- a/include/asm-arm/arch-pxa/pxa27x_keypad.h +++ b/include/asm-arm/arch-pxa/pxa27x_keypad.h | |||
| @@ -53,4 +53,6 @@ struct pxa27x_keypad_platform_data { | |||
| 53 | 53 | ||
| 54 | #define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) | 54 | #define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) |
| 55 | 55 | ||
| 56 | extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info); | ||
| 57 | |||
| 56 | #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */ | 58 | #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */ |
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h new file mode 100644 index 000000000000..763313c5e6be --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h | |||
| @@ -0,0 +1,357 @@ | |||
| 1 | #ifndef __ASM_ARCH_PXA2XX_GPIO_H | ||
| 2 | #define __ASM_ARCH_PXA2XX_GPIO_H | ||
| 3 | |||
| 4 | /* GPIO alternate function assignments */ | ||
| 5 | |||
| 6 | #define GPIO1_RST 1 /* reset */ | ||
| 7 | #define GPIO6_MMCCLK 6 /* MMC Clock */ | ||
| 8 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ | ||
| 9 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ | ||
| 10 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ | ||
| 11 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ | ||
| 12 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ | ||
| 13 | #define GPIO12_32KHz 12 /* 32 kHz out */ | ||
| 14 | #define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */ | ||
| 15 | #define GPIO13_MBGNT 13 /* memory controller grant */ | ||
| 16 | #define GPIO14_MBREQ 14 /* alternate bus master request */ | ||
| 17 | #define GPIO15_nCS_1 15 /* chip select 1 */ | ||
| 18 | #define GPIO16_PWM0 16 /* PWM0 output */ | ||
| 19 | #define GPIO17_PWM1 17 /* PWM1 output */ | ||
| 20 | #define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */ | ||
| 21 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ | ||
| 22 | #define GPIO19_DREQ1 19 /* External DMA Request */ | ||
| 23 | #define GPIO20_DREQ0 20 /* External DMA Request */ | ||
| 24 | #define GPIO23_SCLK 23 /* SSP clock */ | ||
| 25 | #define GPIO23_CIF_MCLK 23 /* Camera Master Clock */ | ||
| 26 | #define GPIO24_SFRM 24 /* SSP Frame */ | ||
| 27 | #define GPIO24_CIF_FV 24 /* Camera frame start signal */ | ||
| 28 | #define GPIO25_STXD 25 /* SSP transmit */ | ||
| 29 | #define GPIO25_CIF_LV 25 /* Camera line start signal */ | ||
| 30 | #define GPIO26_SRXD 26 /* SSP receive */ | ||
| 31 | #define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */ | ||
| 32 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | ||
| 33 | #define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */ | ||
| 34 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | ||
| 35 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | ||
| 36 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | ||
| 37 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ | ||
| 38 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ | ||
| 39 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ | ||
| 40 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ | ||
| 41 | #define GPIO33_nCS_5 33 /* chip select 5 */ | ||
| 42 | #define GPIO34_FFRXD 34 /* FFUART receive */ | ||
| 43 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ | ||
| 44 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ | ||
| 45 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ | ||
| 46 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ | ||
| 47 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ | ||
| 48 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ | ||
| 49 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ | ||
| 50 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | ||
| 51 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | ||
| 52 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | ||
| 53 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | ||
| 54 | #define GPIO42_CIF_MCLK 42 /* Camera Master Clock */ | ||
| 55 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | ||
| 56 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | ||
| 57 | #define GPIO43_CIF_FV 43 /* Camera frame start signal */ | ||
| 58 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | ||
| 59 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | ||
| 60 | #define GPIO44_CIF_LV 44 /* Camera line start signal */ | ||
| 61 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | ||
| 62 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | ||
| 63 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | ||
| 64 | #define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */ | ||
| 65 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | ||
| 66 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | ||
| 67 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | ||
| 68 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | ||
| 69 | #define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */ | ||
| 70 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | ||
| 71 | #define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */ | ||
| 72 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | ||
| 73 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | ||
| 74 | #define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ | ||
| 75 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ | ||
| 76 | #define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */ | ||
| 77 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ | ||
| 78 | #define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */ | ||
| 79 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ | ||
| 80 | #define GPIO53_MMCCLK 53 /* MMC Clock */ | ||
| 81 | #define GPIO53_CIF_MCLK 53 /* Camera Master Clock */ | ||
| 82 | #define GPIO54_MMCCLK 54 /* MMC Clock */ | ||
| 83 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ | ||
| 84 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ | ||
| 85 | #define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */ | ||
| 86 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ | ||
| 87 | #define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */ | ||
| 88 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ | ||
| 89 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ | ||
| 90 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ | ||
| 91 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ | ||
| 92 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ | ||
| 93 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ | ||
| 94 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ | ||
| 95 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ | ||
| 96 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ | ||
| 97 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ | ||
| 98 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ | ||
| 99 | #define GPIO66_MBREQ 66 /* alternate bus master req */ | ||
| 100 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ | ||
| 101 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ | ||
| 102 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ | ||
| 103 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ | ||
| 104 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ | ||
| 105 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ | ||
| 106 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ | ||
| 107 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ | ||
| 108 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ | ||
| 109 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ | ||
| 110 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ | ||
| 111 | #define GPIO72_32kHz 72 /* 32 kHz clock */ | ||
| 112 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ | ||
| 113 | #define GPIO73_MBGNT 73 /* Memory controller grant */ | ||
| 114 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ | ||
| 115 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ | ||
| 116 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ | ||
| 117 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ | ||
| 118 | #define GPIO78_nCS_2 78 /* chip select 2 */ | ||
| 119 | #define GPIO79_nCS_3 79 /* chip select 3 */ | ||
| 120 | #define GPIO80_nCS_4 80 /* chip select 4 */ | ||
| 121 | #define GPIO81_NSCLK 81 /* NSSP clock */ | ||
| 122 | #define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */ | ||
| 123 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | ||
| 124 | #define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ | ||
| 125 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | ||
| 126 | #define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */ | ||
| 127 | #define GPIO84_NSRXD 84 /* NSSP receive */ | ||
| 128 | #define GPIO84_CIF_FV 84 /* Camera frame start signal */ | ||
| 129 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | ||
| 130 | #define GPIO85_CIF_LV 85 /* Camera line start signal */ | ||
| 131 | #define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */ | ||
| 132 | #define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */ | ||
| 133 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ | ||
| 134 | #define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ | ||
| 135 | #define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ | ||
| 136 | #define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ | ||
| 137 | #define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ | ||
| 138 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | ||
| 139 | #define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ | ||
| 140 | #define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ | ||
| 141 | #define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */ | ||
| 142 | #define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */ | ||
| 143 | #define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */ | ||
| 144 | #define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */ | ||
| 145 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ | ||
| 146 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ | ||
| 147 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ | ||
| 148 | #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ | ||
| 149 | #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ | ||
| 150 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ | ||
| 151 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ | ||
| 152 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ | ||
| 153 | #define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */ | ||
| 154 | #define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */ | ||
| 155 | #define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */ | ||
| 156 | |||
| 157 | /* GPIO alternate function mode & direction */ | ||
| 158 | |||
| 159 | #define GPIO_IN 0x000 | ||
| 160 | #define GPIO_OUT 0x080 | ||
| 161 | #define GPIO_ALT_FN_1_IN 0x100 | ||
| 162 | #define GPIO_ALT_FN_1_OUT 0x180 | ||
| 163 | #define GPIO_ALT_FN_2_IN 0x200 | ||
| 164 | #define GPIO_ALT_FN_2_OUT 0x280 | ||
| 165 | #define GPIO_ALT_FN_3_IN 0x300 | ||
| 166 | #define GPIO_ALT_FN_3_OUT 0x380 | ||
| 167 | #define GPIO_MD_MASK_NR 0x07f | ||
| 168 | #define GPIO_MD_MASK_DIR 0x080 | ||
| 169 | #define GPIO_MD_MASK_FN 0x300 | ||
| 170 | #define GPIO_DFLT_LOW 0x400 | ||
| 171 | #define GPIO_DFLT_HIGH 0x800 | ||
| 172 | |||
| 173 | #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) | ||
| 174 | #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) | ||
| 175 | #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) | ||
| 176 | #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) | ||
| 177 | #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) | ||
| 178 | #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) | ||
| 179 | #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) | ||
| 180 | #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) | ||
| 181 | #define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN) | ||
| 182 | #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) | ||
| 183 | #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) | ||
| 184 | #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) | ||
| 185 | #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) | ||
| 186 | #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) | ||
| 187 | #define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN) | ||
| 188 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) | ||
| 189 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) | ||
| 190 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) | ||
| 191 | #define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT) | ||
| 192 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) | ||
| 193 | #define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT) | ||
| 194 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) | ||
| 195 | #define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT) | ||
| 196 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) | ||
| 197 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) | ||
| 198 | #define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN) | ||
| 199 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) | ||
| 200 | #define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN) | ||
| 201 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) | ||
| 202 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) | ||
| 203 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) | ||
| 204 | #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) | ||
| 205 | #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) | ||
| 206 | #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) | ||
| 207 | #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) | ||
| 208 | #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) | ||
| 209 | #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) | ||
| 210 | #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) | ||
| 211 | #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) | ||
| 212 | #define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT) | ||
| 213 | #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) | ||
| 214 | #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) | ||
| 215 | #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) | ||
| 216 | #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) | ||
| 217 | #define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT) | ||
| 218 | #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) | ||
| 219 | #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) | ||
| 220 | #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) | ||
| 221 | #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) | ||
| 222 | #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) | ||
| 223 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) | ||
| 224 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) | ||
| 225 | #define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) | ||
| 226 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | ||
| 227 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | ||
| 228 | #define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT) | ||
| 229 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | ||
| 230 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 231 | #define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 232 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | ||
| 233 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | ||
| 234 | #define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT) | ||
| 235 | #define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN) | ||
| 236 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | ||
| 237 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | ||
| 238 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | ||
| 239 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | ||
| 240 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | ||
| 241 | #define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN) | ||
| 242 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | ||
| 243 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | ||
| 244 | #define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN) | ||
| 245 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 246 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | ||
| 247 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 248 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | ||
| 249 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | ||
| 250 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 251 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | ||
| 252 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 253 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 254 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | ||
| 255 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | ||
| 256 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | ||
| 257 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | ||
| 258 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) | ||
| 259 | #define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN) | ||
| 260 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 261 | #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) | ||
| 262 | #define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 263 | #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) | ||
| 264 | #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 265 | #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 266 | #define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN) | ||
| 267 | #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) | ||
| 268 | #define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN) | ||
| 269 | #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) | ||
| 270 | #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) | ||
| 271 | #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) | ||
| 272 | #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) | ||
| 273 | #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) | ||
| 274 | #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) | ||
| 275 | #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) | ||
| 276 | #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) | ||
| 277 | #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) | ||
| 278 | #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) | ||
| 279 | #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) | ||
| 280 | #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) | ||
| 281 | #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) | ||
| 282 | #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) | ||
| 283 | #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) | ||
| 284 | #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) | ||
| 285 | #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) | ||
| 286 | #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) | ||
| 287 | #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) | ||
| 288 | #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) | ||
| 289 | #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) | ||
| 290 | #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) | ||
| 291 | #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) | ||
| 292 | #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) | ||
| 293 | #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) | ||
| 294 | #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) | ||
| 295 | #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) | ||
| 296 | #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) | ||
| 297 | #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) | ||
| 298 | #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) | ||
| 299 | #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) | ||
| 300 | #define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT) | ||
| 301 | #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) | ||
| 302 | #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) | ||
| 303 | #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) | ||
| 304 | #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) | ||
| 305 | #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) | ||
| 306 | #define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN) | ||
| 307 | #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) | ||
| 308 | #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) | ||
| 309 | #define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) | ||
| 310 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) | ||
| 311 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) | ||
| 312 | #define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN) | ||
| 313 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) | ||
| 314 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) | ||
| 315 | #define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) | ||
| 316 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | ||
| 317 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) | ||
| 318 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) | ||
| 319 | #define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) | ||
| 320 | #define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) | ||
| 321 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | ||
| 322 | #define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN) | ||
| 323 | #define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN) | ||
| 324 | #define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) | ||
| 325 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) | ||
| 326 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) | ||
| 327 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) | ||
| 328 | #define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) | ||
| 329 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) | ||
| 330 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) | ||
| 331 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | ||
| 332 | #define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) | ||
| 333 | #define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN) | ||
| 334 | #define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) | ||
| 335 | #define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN) | ||
| 336 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) | ||
| 337 | #define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) | ||
| 338 | #define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN) | ||
| 339 | #define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) | ||
| 340 | #define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN) | ||
| 341 | #define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) | ||
| 342 | #define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN) | ||
| 343 | #define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) | ||
| 344 | #define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN) | ||
| 345 | #define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) | ||
| 346 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) | ||
| 347 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 348 | #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 349 | #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 350 | #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 351 | #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) | ||
| 352 | #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) | ||
| 353 | #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) | ||
| 354 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) | ||
| 355 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) | ||
| 356 | |||
| 357 | #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h index 8e1b3ead827f..fe9364c83a28 100644 --- a/include/asm-arm/arch-pxa/pxa3xx-regs.h +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h | |||
| @@ -12,6 +12,15 @@ | |||
| 12 | 12 | ||
| 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H | 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H |
| 14 | #define __ASM_ARCH_PXA3XX_REGS_H | 14 | #define __ASM_ARCH_PXA3XX_REGS_H |
| 15 | |||
| 16 | /* | ||
| 17 | * Oscillator Configuration Register (OSCC) | ||
| 18 | */ | ||
| 19 | #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ | ||
| 20 | |||
| 21 | #define OSCC_PEN (1 << 11) /* 13MHz POUT */ | ||
| 22 | |||
| 23 | |||
| 15 | /* | 24 | /* |
| 16 | * Service Power Management Unit (MPMU) | 25 | * Service Power Management Unit (MPMU) |
| 17 | */ | 26 | */ |
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h index c05e4faf85a6..c5b6fde6907c 100644 --- a/include/asm-arm/arch-pxa/tosa.h +++ b/include/asm-arm/arch-pxa/tosa.h | |||
| @@ -23,11 +23,12 @@ | |||
| 23 | /* | 23 | /* |
| 24 | * SCOOP2 internal GPIOs | 24 | * SCOOP2 internal GPIOs |
| 25 | */ | 25 | */ |
| 26 | #define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO | ||
| 26 | #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 | 27 | #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 |
| 27 | #define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 | 28 | #define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 |
| 28 | #define TOSA_SCOOP_IR_POWERDWN SCOOP_GPCR_PA13 | 29 | #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) |
| 29 | #define TOSA_SCOOP_SD_WP SCOOP_GPCR_PA14 | 30 | #define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) |
| 30 | #define TOSA_SCOOP_PWR_ON SCOOP_GPCR_PA15 | 31 | #define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) |
| 31 | #define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 | 32 | #define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 |
| 32 | #define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 | 33 | #define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 |
| 33 | #define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 | 34 | #define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 |
| @@ -35,7 +36,7 @@ | |||
| 35 | 36 | ||
| 36 | /* GPIO Direction 1 : output mode / 0:input mode */ | 37 | /* GPIO Direction 1 : output mode / 0:input mode */ |
| 37 | #define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ | 38 | #define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ |
| 38 | TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\ | 39 | TOSA_SCOOP_AUD_PWR_ON |\ |
| 39 | TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) | 40 | TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) |
| 40 | /* GPIO out put level when init 1: Hi */ | 41 | /* GPIO out put level when init 1: Hi */ |
| 41 | #define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) | 42 | #define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) |
| @@ -43,23 +44,21 @@ | |||
| 43 | /* | 44 | /* |
| 44 | * SCOOP2 jacket GPIOs | 45 | * SCOOP2 jacket GPIOs |
| 45 | */ | 46 | */ |
| 46 | #define TOSA_SCOOP_JC_BT_LED SCOOP_GPCR_PA11 | 47 | #define TOSA_SCOOP_JC_GPIO_BASE (NR_BUILTIN_GPIO + 12) |
| 47 | #define TOSA_SCOOP_JC_NOTE_LED SCOOP_GPCR_PA12 | 48 | #define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0) |
| 48 | #define TOSA_SCOOP_JC_CHRG_ERR_LED SCOOP_GPCR_PA13 | 49 | #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) |
| 49 | #define TOSA_SCOOP_JC_USB_PULLUP SCOOP_GPCR_PA14 | 50 | #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) |
| 51 | #define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) | ||
| 50 | #define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 | 52 | #define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 |
| 51 | #define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 | 53 | #define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 |
| 52 | #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 | 54 | #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 |
| 53 | #define TOSA_SCOOP_JC_WLAN_LED SCOOP_GPCR_PA18 | 55 | #define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) |
| 54 | #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 | 56 | #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 |
| 55 | 57 | ||
| 56 | /* GPIO Direction 1 : output mode / 0:input mode */ | 58 | /* GPIO Direction 1 : output mode / 0:input mode */ |
| 57 | #define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \ | 59 | #define TOSA_SCOOP_JC_IO_DIR ( \ |
| 58 | TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \ | ||
| 59 | TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ | 60 | TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ |
| 60 | TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL ) | 61 | TOSA_SCOOP_JC_CARD_LIMIT_SEL ) |
| 61 | /* GPIO out put level when init 1: Hi */ | ||
| 62 | #define TOSA_SCOOP_JC_IO_OUT ( 0 ) | ||
| 63 | 62 | ||
| 64 | /* | 63 | /* |
| 65 | * Timing Generator | 64 | * Timing Generator |
| @@ -74,15 +73,6 @@ | |||
| 74 | #define TG_HPOSCTL 0x07 | 73 | #define TG_HPOSCTL 0x07 |
| 75 | 74 | ||
| 76 | /* | 75 | /* |
| 77 | * LED | ||
| 78 | */ | ||
| 79 | #define TOSA_SCOOP_LED_BLUE TOSA_SCOOP_GPCR_PA11 | ||
| 80 | #define TOSA_SCOOP_LED_GREEN TOSA_SCOOP_GPCR_PA12 | ||
| 81 | #define TOSA_SCOOP_LED_ORANGE TOSA_SCOOP_GPCR_PA13 | ||
| 82 | #define TOSA_SCOOP_LED_WLAN TOSA_SCOOP_GPCR_PA18 | ||
| 83 | |||
| 84 | |||
| 85 | /* | ||
| 86 | * PXA GPIOs | 76 | * PXA GPIOs |
| 87 | */ | 77 | */ |
| 88 | #define TOSA_GPIO_POWERON (0) | 78 | #define TOSA_GPIO_POWERON (0) |
| @@ -161,12 +151,8 @@ | |||
| 161 | 151 | ||
| 162 | #define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) | 152 | #define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) |
| 163 | 153 | ||
| 164 | extern struct platform_device tosascoop_jc_device; | ||
| 165 | extern struct platform_device tosascoop_device; | ||
| 166 | |||
| 167 | #define TOSA_KEY_SYNC KEY_102ND /* ??? */ | 154 | #define TOSA_KEY_SYNC KEY_102ND /* ??? */ |
| 168 | 155 | ||
| 169 | |||
| 170 | #ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES | 156 | #ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES |
| 171 | #define TOSA_KEY_RECORD KEY_YEN | 157 | #define TOSA_KEY_RECORD KEY_YEN |
| 172 | #define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA | 158 | #define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA |
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h index 5f717d64ea7d..4881b80f0f90 100644 --- a/include/asm-arm/arch-pxa/zylonite.h +++ b/include/asm-arm/arch-pxa/zylonite.h | |||
| @@ -18,6 +18,8 @@ extern struct platform_mmc_slot zylonite_mmc_slot[]; | |||
| 18 | extern int gpio_backlight; | 18 | extern int gpio_backlight; |
| 19 | extern int gpio_eth_irq; | 19 | extern int gpio_eth_irq; |
| 20 | 20 | ||
| 21 | extern int wm9713_irq; | ||
| 22 | |||
| 21 | extern int lcd_id; | 23 | extern int lcd_id; |
| 22 | extern int lcd_orientation; | 24 | extern int lcd_orientation; |
| 23 | 25 | ||
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h index 3e437b7f425a..206f7a752882 100644 --- a/include/asm-arm/arch-realview/board-eb.h +++ b/include/asm-arm/arch-realview/board-eb.h | |||
| @@ -26,6 +26,26 @@ | |||
| 26 | /* | 26 | /* |
| 27 | * RealView EB + ARM11MPCore peripheral addresses | 27 | * RealView EB + ARM11MPCore peripheral addresses |
| 28 | */ | 28 | */ |
| 29 | #define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */ | ||
| 30 | #define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */ | ||
| 31 | #define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */ | ||
| 32 | #define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */ | ||
| 33 | #define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ | ||
| 34 | #define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */ | ||
| 35 | #define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ | ||
| 36 | #define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ | ||
| 37 | #define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */ | ||
| 38 | #define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */ | ||
| 39 | #define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */ | ||
| 40 | #define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ | ||
| 41 | #define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ | ||
| 42 | #define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */ | ||
| 43 | |||
| 44 | #define REALVIEW_EB_FLASH_BASE 0x40000000 | ||
| 45 | #define REALVIEW_EB_FLASH_SIZE SZ_64M | ||
| 46 | #define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */ | ||
| 47 | #define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ | ||
| 48 | |||
| 29 | #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB | 49 | #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB |
| 30 | #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ | 50 | #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ |
| 31 | #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ | 51 | #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ |
diff --git a/include/asm-arm/arch-realview/board-pb1176.h b/include/asm-arm/arch-realview/board-pb1176.h new file mode 100644 index 000000000000..48ce9c833705 --- /dev/null +++ b/include/asm-arm/arch-realview/board-pb1176.h | |||
| @@ -0,0 +1,152 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-realview/board-pb1176.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_BOARD_PB1176_H | ||
| 22 | #define __ASM_ARCH_BOARD_PB1176_H | ||
| 23 | |||
| 24 | #include <asm/arch/platform.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Peripheral addresses | ||
| 28 | */ | ||
| 29 | #define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */ | ||
| 30 | #define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */ | ||
| 31 | #define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */ | ||
| 32 | #define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ | ||
| 33 | #define REALVIEW_PB1176_FLASH_BASE 0x30000000 | ||
| 34 | #define REALVIEW_PB1176_FLASH_SIZE SZ_64M | ||
| 35 | |||
| 36 | #define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */ | ||
| 37 | #define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */ | ||
| 38 | #define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */ | ||
| 39 | #define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */ | ||
| 40 | #define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */ | ||
| 41 | #define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */ | ||
| 42 | #define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */ | ||
| 43 | #define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */ | ||
| 44 | #define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */ | ||
| 45 | #define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */ | ||
| 46 | #define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */ | ||
| 47 | #define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */ | ||
| 48 | #define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */ | ||
| 49 | #define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */ | ||
| 50 | |||
| 51 | /* | ||
| 52 | * PCI regions | ||
| 53 | */ | ||
| 54 | #define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */ | ||
| 55 | #define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */ | ||
| 56 | #define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */ | ||
| 57 | #define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */ | ||
| 58 | #define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */ | ||
| 59 | #define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */ | ||
| 60 | |||
| 61 | #define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */ | ||
| 62 | #define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */ | ||
| 63 | #define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */ | ||
| 64 | #define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */ | ||
| 65 | #define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */ | ||
| 66 | #define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */ | ||
| 67 | |||
| 68 | #define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */ | ||
| 69 | #define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */ | ||
| 70 | #define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */ | ||
| 71 | #define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ | ||
| 72 | #define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Irqs | ||
| 76 | */ | ||
| 77 | #define IRQ_DC1176_GIC_START 32 | ||
| 78 | #define IRQ_PB1176_GIC_START 64 | ||
| 79 | |||
| 80 | /* | ||
| 81 | * ARM1176 DevChip interrupt sources (primary GIC) | ||
| 82 | */ | ||
| 83 | #define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */ | ||
| 84 | #define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */ | ||
| 85 | #define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */ | ||
| 86 | #define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */ | ||
| 87 | #define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */ | ||
| 88 | #define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */ | ||
| 89 | #define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */ | ||
| 90 | #define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11) | ||
| 91 | #define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12) | ||
| 92 | #define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) | ||
| 93 | #define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) | ||
| 94 | #define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ | ||
| 95 | #define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ | ||
| 96 | #define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ | ||
| 97 | #define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ | ||
| 98 | #define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */ | ||
| 99 | |||
| 100 | #define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */ | ||
| 101 | #define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */ | ||
| 102 | |||
| 103 | /* | ||
| 104 | * RealView PB1176 interrupt sources (secondary GIC) | ||
| 105 | */ | ||
| 106 | #define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */ | ||
| 107 | #define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */ | ||
| 108 | #define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */ | ||
| 109 | #define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */ | ||
| 110 | #define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5) | ||
| 111 | #define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */ | ||
| 112 | #define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */ | ||
| 113 | #define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8) | ||
| 114 | #define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9) | ||
| 115 | #define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */ | ||
| 116 | #define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */ | ||
| 117 | |||
| 118 | #define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16) | ||
| 119 | |||
| 120 | #define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */ | ||
| 121 | |||
| 122 | #define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22) | ||
| 123 | #define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23) | ||
| 124 | #define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */ | ||
| 125 | #define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ | ||
| 126 | |||
| 127 | #define IRQ_PB1176_GPIO0 -1 | ||
| 128 | #define IRQ_PB1176_SSP -1 | ||
| 129 | #define IRQ_PB1176_SCTL -1 | ||
| 130 | |||
| 131 | #define NR_GIC_PB1176 2 | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Only define NR_IRQS if less than NR_IRQS_PB1176 | ||
| 135 | */ | ||
| 136 | #define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96) | ||
| 137 | |||
| 138 | #if defined(CONFIG_MACH_REALVIEW_PB1176) | ||
| 139 | |||
| 140 | #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176) | ||
| 141 | #undef NR_IRQS | ||
| 142 | #define NR_IRQS NR_IRQS_PB1176 | ||
| 143 | #endif | ||
| 144 | |||
| 145 | #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176) | ||
| 146 | #undef MAX_GIC_NR | ||
| 147 | #define MAX_GIC_NR NR_GIC_PB1176 | ||
| 148 | #endif | ||
| 149 | |||
| 150 | #endif /* CONFIG_MACH_REALVIEW_PB1176 */ | ||
| 151 | |||
| 152 | #endif /* __ASM_ARCH_BOARD_PB1176_H */ | ||
diff --git a/include/asm-arm/arch-realview/board-pb11mp.h b/include/asm-arm/arch-realview/board-pb11mp.h new file mode 100644 index 000000000000..a1294d915fa8 --- /dev/null +++ b/include/asm-arm/arch-realview/board-pb11mp.h | |||
| @@ -0,0 +1,186 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-realview/board-pb11mp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_BOARD_PB11MP_H | ||
| 22 | #define __ASM_ARCH_BOARD_PB11MP_H | ||
| 23 | |||
| 24 | #include <asm/arch/platform.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Peripheral addresses | ||
| 28 | */ | ||
| 29 | #define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */ | ||
| 30 | #define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */ | ||
| 31 | #define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */ | ||
| 32 | #define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */ | ||
| 33 | #define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ | ||
| 34 | #define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ | ||
| 35 | #define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */ | ||
| 36 | #define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ | ||
| 37 | #define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ | ||
| 38 | #define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */ | ||
| 39 | #define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */ | ||
| 40 | #define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ | ||
| 41 | #define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ | ||
| 42 | #define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */ | ||
| 43 | #define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */ | ||
| 44 | #define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ | ||
| 45 | #define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */ | ||
| 46 | #define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */ | ||
| 47 | #define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */ | ||
| 48 | #define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */ | ||
| 49 | #define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ | ||
| 50 | #define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ | ||
| 51 | #define REALVIEW_PB11MP_FLASH0_BASE 0x40000000 | ||
| 52 | #define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M | ||
| 53 | #define REALVIEW_PB11MP_FLASH1_BASE 0x44000000 | ||
| 54 | #define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M | ||
| 55 | #define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */ | ||
| 56 | #define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */ | ||
| 57 | #define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ | ||
| 58 | #define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */ | ||
| 59 | #define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ | ||
| 60 | #define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ | ||
| 61 | |||
| 62 | #define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 | ||
| 63 | |||
| 64 | /* | ||
| 65 | * PB11MPCore PCI regions | ||
| 66 | */ | ||
| 67 | #define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */ | ||
| 68 | #define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ | ||
| 69 | #define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ | ||
| 70 | |||
| 71 | #define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */ | ||
| 72 | #define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */ | ||
| 73 | #define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */ | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Testchip peripheral and fpga gic regions | ||
| 77 | */ | ||
| 78 | #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ | ||
| 79 | #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ | ||
| 80 | #define REALVIEW_TC11MP_TWD_BASE 0x1F000700 | ||
| 81 | #define REALVIEW_TC11MP_TWD_SIZE 0x00000100 | ||
| 82 | #define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ | ||
| 83 | #define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ | ||
| 84 | |||
| 85 | /* | ||
| 86 | * Irqs | ||
| 87 | */ | ||
| 88 | #define IRQ_TC11MP_GIC_START 32 | ||
| 89 | #define IRQ_PB11MP_GIC_START 64 | ||
| 90 | |||
| 91 | /* | ||
| 92 | * ARM11MPCore test chip interrupt sources (primary GIC on the test chip) | ||
| 93 | */ | ||
| 94 | #define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0) | ||
| 95 | #define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1) | ||
| 96 | #define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2) | ||
| 97 | #define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3) | ||
| 98 | #define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4) | ||
| 99 | #define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5) | ||
| 100 | #define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6) | ||
| 101 | #define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7) | ||
| 102 | #define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8) | ||
| 103 | #define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9) | ||
| 104 | #define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */ | ||
| 105 | #define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */ | ||
| 106 | #define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */ | ||
| 107 | #define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */ | ||
| 108 | #define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14) | ||
| 109 | #define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15) | ||
| 110 | |||
| 111 | #define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17) | ||
| 112 | #define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18) | ||
| 113 | #define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19) | ||
| 114 | #define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20) | ||
| 115 | #define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21) | ||
| 116 | #define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22) | ||
| 117 | #define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23) | ||
| 118 | #define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24) | ||
| 119 | #define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25) | ||
| 120 | #define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26) | ||
| 121 | #define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27) | ||
| 122 | #define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28) | ||
| 123 | |||
| 124 | #define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29) | ||
| 125 | #define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30) | ||
| 126 | #define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31) | ||
| 127 | |||
| 128 | /* | ||
| 129 | * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board) | ||
| 130 | */ | ||
| 131 | #define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */ | ||
| 132 | #define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */ | ||
| 133 | #define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */ | ||
| 134 | #define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */ | ||
| 135 | #define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */ | ||
| 136 | #define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */ | ||
| 137 | #define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */ | ||
| 138 | /* 9 reserved */ | ||
| 139 | #define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */ | ||
| 140 | #define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */ | ||
| 141 | #define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */ | ||
| 142 | #define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */ | ||
| 143 | #define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */ | ||
| 144 | #define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */ | ||
| 145 | #define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */ | ||
| 146 | #define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */ | ||
| 147 | #define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */ | ||
| 148 | #define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */ | ||
| 149 | #define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */ | ||
| 150 | #define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */ | ||
| 151 | #define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */ | ||
| 152 | #define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */ | ||
| 153 | #define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */ | ||
| 154 | #define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */ | ||
| 155 | #define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */ | ||
| 156 | #define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */ | ||
| 157 | #define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */ | ||
| 158 | #define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */ | ||
| 159 | #define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */ | ||
| 160 | #define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */ | ||
| 161 | |||
| 162 | #define IRQ_PB11MP_SMC -1 | ||
| 163 | #define IRQ_PB11MP_SCTL -1 | ||
| 164 | |||
| 165 | #define NR_GIC_PB11MP 2 | ||
| 166 | |||
| 167 | /* | ||
| 168 | * Only define NR_IRQS if less than NR_IRQS_PB11MP | ||
| 169 | */ | ||
| 170 | #define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96) | ||
| 171 | |||
| 172 | #if defined(CONFIG_MACH_REALVIEW_PB11MP) | ||
| 173 | |||
| 174 | #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP) | ||
| 175 | #undef NR_IRQS | ||
| 176 | #define NR_IRQS NR_IRQS_PB11MP | ||
| 177 | #endif | ||
| 178 | |||
| 179 | #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP) | ||
| 180 | #undef MAX_GIC_NR | ||
| 181 | #define MAX_GIC_NR NR_GIC_PB11MP | ||
| 182 | #endif | ||
| 183 | |||
| 184 | #endif /* CONFIG_MACH_REALVIEW_PB11MP */ | ||
| 185 | |||
| 186 | #endif /* __ASM_ARCH_BOARD_PB11MP_H */ | ||
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S index f17efc65518a..c8c860c3c26e 100644 --- a/include/asm-arm/arch-realview/debug-macro.S +++ b/include/asm-arm/arch-realview/debug-macro.S | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
| 16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
| 17 | moveq \rx, #0x10000000 | 17 | moveq \rx, #0x10000000 |
| 18 | movne \rx, #0xf1000000 @ virtual base | 18 | movne \rx, #0xf0000000 @ virtual base |
| 19 | orr \rx, \rx, #0x00009000 | 19 | orr \rx, \rx, #0x00009000 |
| 20 | .endm | 20 | .endm |
| 21 | 21 | ||
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h index bad8d7ce9bfe..1ee8313ceb6a 100644 --- a/include/asm-arm/arch-realview/hardware.h +++ b/include/asm-arm/arch-realview/hardware.h | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | #include <asm/sizes.h> | 25 | #include <asm/sizes.h> |
| 26 | 26 | ||
| 27 | /* macro to get at IO space when running virtually */ | 27 | /* macro to get at IO space when running virtually */ |
| 28 | #define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) | 28 | #define IO_ADDRESS(x) (((x) & 0x0fffffff) + 0xf0000000) |
| 29 | #define __io_address(n) __io(IO_ADDRESS(n)) | 29 | #define __io_address(n) __io(IO_ADDRESS(n)) |
| 30 | 30 | ||
| 31 | #endif | 31 | #endif |
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index ad0c911002fc..ccbac59235c6 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h | |||
| @@ -23,6 +23,8 @@ | |||
| 23 | #define __ASM_ARCH_IRQS_H | 23 | #define __ASM_ARCH_IRQS_H |
| 24 | 24 | ||
| 25 | #include <asm/arch/board-eb.h> | 25 | #include <asm/arch/board-eb.h> |
| 26 | #include <asm/arch/board-pb11mp.h> | ||
| 27 | #include <asm/arch/board-pb1176.h> | ||
| 26 | 28 | ||
| 27 | #define IRQ_LOCALTIMER 29 | 29 | #define IRQ_LOCALTIMER 29 |
| 28 | #define IRQ_LOCALWDOG 30 | 30 | #define IRQ_LOCALWDOG 30 |
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h index 4fd351b5e4a2..424c0aaf46a0 100644 --- a/include/asm-arm/arch-realview/platform.h +++ b/include/asm-arm/arch-realview/platform.h | |||
| @@ -32,9 +32,6 @@ | |||
| 32 | #define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ | 32 | #define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ |
| 33 | #define REALVIEW_SSRAM_SIZE SZ_2M | 33 | #define REALVIEW_SSRAM_SIZE SZ_2M |
| 34 | 34 | ||
| 35 | #define REALVIEW_FLASH_BASE 0x40000000 | ||
| 36 | #define REALVIEW_FLASH_SIZE SZ_64M | ||
| 37 | |||
| 38 | /* | 35 | /* |
| 39 | * SDRAM | 36 | * SDRAM |
| 40 | */ | 37 | */ |
| @@ -175,42 +172,20 @@ | |||
| 175 | #define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ | 172 | #define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ |
| 176 | 173 | ||
| 177 | /* | 174 | /* |
| 178 | * REALVIEW peripheral addresses | 175 | * RealView common peripheral addresses |
| 179 | */ | 176 | */ |
| 180 | #define REALVIEW_SCTL_BASE 0x10001000 /* System controller */ | 177 | #define REALVIEW_SCTL_BASE 0x10001000 /* System controller */ |
| 181 | #define REALVIEW_I2C_BASE 0x10002000 /* I2C control */ | 178 | #define REALVIEW_I2C_BASE 0x10002000 /* I2C control */ |
| 182 | /* Reserved 0x10003000 */ | ||
| 183 | #define REALVIEW_AACI_BASE 0x10004000 /* Audio */ | 179 | #define REALVIEW_AACI_BASE 0x10004000 /* Audio */ |
| 184 | #define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */ | 180 | #define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */ |
| 185 | #define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */ | 181 | #define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */ |
| 186 | #define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */ | 182 | #define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */ |
| 187 | #define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */ | 183 | #define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */ |
| 188 | #define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ | ||
| 189 | #define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ | ||
| 190 | #define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ | ||
| 191 | #define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ | ||
| 192 | #define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ | ||
| 193 | #define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */ | 184 | #define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */ |
| 194 | /* Reserved 0x1000F000 */ | ||
| 195 | #define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ | ||
| 196 | #define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ | ||
| 197 | #define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ | ||
| 198 | #define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ | ||
| 199 | #define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */ | 185 | #define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */ |
| 200 | #define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */ | 186 | #define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */ |
| 201 | /* Reserved 0x10016000 */ | ||
| 202 | #define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ | ||
| 203 | #define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */ | 187 | #define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */ |
| 204 | #define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */ | ||
| 205 | /* Reserved 0x1001A000 - 0x1001FFFF */ | ||
| 206 | #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ | ||
| 207 | #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ | 188 | #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ |
| 208 | #define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ | ||
| 209 | #define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ | ||
| 210 | #define REALVIEW_SMC_BASE 0x10080000 /* SMC */ | ||
| 211 | /* Reserved 0x10090000 - 0x100EFFFF */ | ||
| 212 | |||
| 213 | #define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ | ||
| 214 | 189 | ||
| 215 | /* PCI space */ | 190 | /* PCI space */ |
| 216 | #define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */ | 191 | #define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */ |
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h index 08b3db883c36..d55802d645af 100644 --- a/include/asm-arm/arch-realview/scu.h +++ b/include/asm-arm/arch-realview/scu.h | |||
| @@ -1,8 +1,13 @@ | |||
| 1 | #ifndef __ASMARM_ARCH_SCU_H | 1 | #ifndef __ASMARM_ARCH_SCU_H |
| 2 | #define __ASMARM_ARCH_SCU_H | 2 | #define __ASMARM_ARCH_SCU_H |
| 3 | 3 | ||
| 4 | #include <asm/arch/board-eb.h> | 4 | /* |
| 5 | 5 | * SCU registers | |
| 6 | #define SCU_BASE REALVIEW_EB11MP_SCU_BASE | 6 | */ |
| 7 | #define SCU_CTRL 0x00 | ||
| 8 | #define SCU_CONFIG 0x04 | ||
| 9 | #define SCU_CPU_STATUS 0x08 | ||
| 10 | #define SCU_INVALIDATE 0x0c | ||
| 11 | #define SCU_FPGA_REVISION 0x10 | ||
| 7 | 12 | ||
| 8 | #endif | 13 | #endif |
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h index 3d5c2db07a26..4c905d7a13a1 100644 --- a/include/asm-arm/arch-realview/uncompress.h +++ b/include/asm-arm/arch-realview/uncompress.h | |||
| @@ -18,28 +18,50 @@ | |||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ | 19 | */ |
| 20 | #include <asm/hardware.h> | 20 | #include <asm/hardware.h> |
| 21 | #include <asm/mach-types.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/arch/platform.h> | 23 | #include <asm/arch/board-eb.h> |
| 24 | #include <asm/arch/board-pb11mp.h> | ||
| 25 | #include <asm/arch/board-pb1176.h> | ||
| 23 | 26 | ||
| 24 | #define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) | 27 | #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) |
| 25 | #define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) | 28 | #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) |
| 26 | #define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) | 29 | #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) |
| 27 | #define AMBA_UART_FR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18)) | 30 | #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) |
| 31 | |||
| 32 | /* | ||
| 33 | * Return the UART base address | ||
| 34 | */ | ||
| 35 | static inline unsigned long get_uart_base(void) | ||
| 36 | { | ||
| 37 | if (machine_is_realview_eb()) | ||
| 38 | return REALVIEW_EB_UART0_BASE; | ||
| 39 | else if (machine_is_realview_pb11mp()) | ||
| 40 | return REALVIEW_PB11MP_UART0_BASE; | ||
| 41 | else if (machine_is_realview_pb1176()) | ||
| 42 | return REALVIEW_PB1176_UART0_BASE; | ||
| 43 | else | ||
| 44 | return 0; | ||
| 45 | } | ||
| 28 | 46 | ||
| 29 | /* | 47 | /* |
| 30 | * This does not append a newline | 48 | * This does not append a newline |
| 31 | */ | 49 | */ |
| 32 | static inline void putc(int c) | 50 | static inline void putc(int c) |
| 33 | { | 51 | { |
| 34 | while (AMBA_UART_FR & (1 << 5)) | 52 | unsigned long base = get_uart_base(); |
| 53 | |||
| 54 | while (AMBA_UART_FR(base) & (1 << 5)) | ||
| 35 | barrier(); | 55 | barrier(); |
| 36 | 56 | ||
| 37 | AMBA_UART_DR = c; | 57 | AMBA_UART_DR(base) = c; |
| 38 | } | 58 | } |
| 39 | 59 | ||
| 40 | static inline void flush(void) | 60 | static inline void flush(void) |
| 41 | { | 61 | { |
| 42 | while (AMBA_UART_FR & (1 << 3)) | 62 | unsigned long base = get_uart_base(); |
| 63 | |||
| 64 | while (AMBA_UART_FR(base) & (1 << 3)) | ||
| 43 | barrier(); | 65 | barrier(); |
| 44 | } | 66 | } |
| 45 | 67 | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index dba9df9d8713..ecae9e7f5e45 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h | |||
| @@ -137,7 +137,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | |||
| 137 | 137 | ||
| 138 | #define S3C2412_CLKDIVN_PDIVN (1<<2) | 138 | #define S3C2412_CLKDIVN_PDIVN (1<<2) |
| 139 | #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) | 139 | #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) |
| 140 | #define S3C2421_CLKDIVN_ARMDIVN (1<<3) | 140 | #define S3C2412_CLKDIVN_ARMDIVN (1<<3) |
| 141 | #define S3C2412_CLKDIVN_DVSEN (1<<4) | 141 | #define S3C2412_CLKDIVN_DVSEN (1<<4) |
| 142 | #define S3C2412_CLKDIVN_HALFHCLK (1<<5) | 142 | #define S3C2412_CLKDIVN_HALFHCLK (1<<5) |
| 143 | #define S3C2412_CLKDIVN_USB48DIV (1<<6) | 143 | #define S3C2412_CLKDIVN_USB48DIV (1<<6) |
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index 0ad75d716ded..497dd06e2c99 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h | |||
| @@ -529,11 +529,13 @@ | |||
| 529 | #define S3C2410_GPD14_INP (0x00 << 28) | 529 | #define S3C2410_GPD14_INP (0x00 << 28) |
| 530 | #define S3C2410_GPD14_OUTP (0x01 << 28) | 530 | #define S3C2410_GPD14_OUTP (0x01 << 28) |
| 531 | #define S3C2410_GPD14_VD22 (0x02 << 28) | 531 | #define S3C2410_GPD14_VD22 (0x02 << 28) |
| 532 | #define S3C2410_GPD14_nSS1 (0x03 << 28) | ||
| 532 | 533 | ||
| 533 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) | 534 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) |
| 534 | #define S3C2410_GPD15_INP (0x00 << 30) | 535 | #define S3C2410_GPD15_INP (0x00 << 30) |
| 535 | #define S3C2410_GPD15_OUTP (0x01 << 30) | 536 | #define S3C2410_GPD15_OUTP (0x01 << 30) |
| 536 | #define S3C2410_GPD15_VD23 (0x02 << 30) | 537 | #define S3C2410_GPD15_VD23 (0x02 << 30) |
| 538 | #define S3C2410_GPD15_nSS0 (0x03 << 30) | ||
| 537 | 539 | ||
| 538 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) | 540 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) |
| 539 | 541 | ||
| @@ -801,12 +803,14 @@ | |||
| 801 | #define S3C2410_GPG2_INP (0x00 << 4) | 803 | #define S3C2410_GPG2_INP (0x00 << 4) |
| 802 | #define S3C2410_GPG2_OUTP (0x01 << 4) | 804 | #define S3C2410_GPG2_OUTP (0x01 << 4) |
| 803 | #define S3C2410_GPG2_EINT10 (0x02 << 4) | 805 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
| 806 | #define S3C2410_GPG2_nSS0 (0x03 << 4) | ||
| 804 | #define S3C2400_GPG2_CDCLK (0x02 << 4) | 807 | #define S3C2400_GPG2_CDCLK (0x02 << 4) |
| 805 | 808 | ||
| 806 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) | 809 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) |
| 807 | #define S3C2410_GPG3_INP (0x00 << 6) | 810 | #define S3C2410_GPG3_INP (0x00 << 6) |
| 808 | #define S3C2410_GPG3_OUTP (0x01 << 6) | 811 | #define S3C2410_GPG3_OUTP (0x01 << 6) |
| 809 | #define S3C2410_GPG3_EINT11 (0x02 << 6) | 812 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
| 813 | #define S3C2410_GPG3_nSS1 (0x03 << 6) | ||
| 810 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) | 814 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) |
| 811 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | 815 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) |
| 812 | 816 | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h new file mode 100644 index 000000000000..c8c793e78936 --- /dev/null +++ b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * S3C2412 memory register definitions | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM | ||
| 15 | #define __ASM_ARM_REGS_S3C2412_MEM | ||
| 16 | |||
| 17 | #ifndef S3C2412_MEMREG | ||
| 18 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) | ||
| 22 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) | ||
| 23 | #define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) | ||
| 24 | #define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) | ||
| 25 | |||
| 26 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) | ||
| 27 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) | ||
| 28 | |||
| 29 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ | ||
diff --git a/include/asm-arm/arch-s3c2410/system-reset.h b/include/asm-arm/arch-s3c2410/system-reset.h new file mode 100644 index 000000000000..1615bce0c026 --- /dev/null +++ b/include/asm-arm/arch-s3c2410/system-reset.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/system-reset.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - System define for arch_reset() function | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/hardware.h> | ||
| 14 | #include <asm/io.h> | ||
| 15 | |||
| 16 | #include <asm/plat-s3c/regs-watchdog.h> | ||
| 17 | #include <asm/arch/regs-clock.h> | ||
| 18 | |||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | |||
| 22 | extern void (*s3c24xx_reset_hook)(void); | ||
| 23 | |||
| 24 | static void | ||
| 25 | arch_reset(char mode) | ||
| 26 | { | ||
| 27 | struct clk *wdtclk; | ||
| 28 | |||
| 29 | if (mode == 's') { | ||
| 30 | cpu_reset(0); | ||
| 31 | } | ||
| 32 | |||
| 33 | if (s3c24xx_reset_hook) | ||
| 34 | s3c24xx_reset_hook(); | ||
| 35 | |||
| 36 | printk("arch_reset: attempting watchdog reset\n"); | ||
| 37 | |||
| 38 | __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ | ||
| 39 | |||
| 40 | wdtclk = clk_get(NULL, "watchdog"); | ||
| 41 | if (!IS_ERR(wdtclk)) { | ||
| 42 | clk_enable(wdtclk); | ||
| 43 | } else | ||
| 44 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | ||
| 45 | |||
| 46 | /* put initial values into count and data */ | ||
| 47 | __raw_writel(0x80, S3C2410_WTCNT); | ||
| 48 | __raw_writel(0x80, S3C2410_WTDAT); | ||
| 49 | |||
| 50 | /* set the watchdog to go and reset... */ | ||
| 51 | __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | | ||
| 52 | S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); | ||
| 53 | |||
| 54 | /* wait for reset to assert... */ | ||
| 55 | mdelay(500); | ||
| 56 | |||
| 57 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | ||
| 58 | |||
| 59 | /* delay to allow the serial port to show the message */ | ||
| 60 | mdelay(50); | ||
| 61 | |||
| 62 | /* we'll take a jump through zero as a poor second */ | ||
| 63 | cpu_reset(0); | ||
| 64 | } | ||
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h index 14de4e596f87..ad258085e53b 100644 --- a/include/asm-arm/arch-s3c2410/system.h +++ b/include/asm-arm/arch-s3c2410/system.h | |||
| @@ -17,12 +17,8 @@ | |||
| 17 | #include <asm/arch/idle.h> | 17 | #include <asm/arch/idle.h> |
| 18 | #include <asm/arch/reset.h> | 18 | #include <asm/arch/reset.h> |
| 19 | 19 | ||
| 20 | #include <asm/plat-s3c/regs-watchdog.h> | ||
| 21 | #include <asm/arch/regs-clock.h> | 20 | #include <asm/arch/regs-clock.h> |
| 22 | 21 | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/err.h> | ||
| 25 | |||
| 26 | void (*s3c24xx_idle)(void); | 22 | void (*s3c24xx_idle)(void); |
| 27 | void (*s3c24xx_reset_hook)(void); | 23 | void (*s3c24xx_reset_hook)(void); |
| 28 | 24 | ||
| @@ -59,44 +55,4 @@ static void arch_idle(void) | |||
| 59 | s3c24xx_default_idle(); | 55 | s3c24xx_default_idle(); |
| 60 | } | 56 | } |
| 61 | 57 | ||
| 62 | static void | 58 | #include <asm/arch/system-reset.h> |
| 63 | arch_reset(char mode) | ||
| 64 | { | ||
| 65 | struct clk *wdtclk; | ||
| 66 | |||
| 67 | if (mode == 's') { | ||
| 68 | cpu_reset(0); | ||
| 69 | } | ||
| 70 | |||
| 71 | if (s3c24xx_reset_hook) | ||
| 72 | s3c24xx_reset_hook(); | ||
| 73 | |||
| 74 | printk("arch_reset: attempting watchdog reset\n"); | ||
| 75 | |||
| 76 | __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ | ||
| 77 | |||
| 78 | wdtclk = clk_get(NULL, "watchdog"); | ||
| 79 | if (!IS_ERR(wdtclk)) { | ||
| 80 | clk_enable(wdtclk); | ||
| 81 | } else | ||
| 82 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | ||
| 83 | |||
| 84 | /* put initial values into count and data */ | ||
| 85 | __raw_writel(0x80, S3C2410_WTCNT); | ||
| 86 | __raw_writel(0x80, S3C2410_WTDAT); | ||
| 87 | |||
| 88 | /* set the watchdog to go and reset... */ | ||
| 89 | __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | | ||
| 90 | S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); | ||
| 91 | |||
| 92 | /* wait for reset to assert... */ | ||
| 93 | mdelay(500); | ||
| 94 | |||
| 95 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | ||
| 96 | |||
| 97 | /* delay to allow the serial port to show the message */ | ||
| 98 | mdelay(50); | ||
| 99 | |||
| 100 | /* we'll take a jump through zero as a poor second */ | ||
| 101 | cpu_reset(0); | ||
| 102 | } | ||
diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h index e7a9d26e22a8..93d3395b102d 100644 --- a/include/asm-arm/arch-sa1100/gpio.h +++ b/include/asm-arm/arch-sa1100/gpio.h | |||
| @@ -26,35 +26,28 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/hardware.h> | 27 | #include <asm/hardware.h> |
| 28 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| 29 | 29 | #include <asm-generic/gpio.h> | |
| 30 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 31 | { | ||
| 32 | return 0; | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void gpio_free(unsigned gpio) | ||
| 36 | { | ||
| 37 | return; | ||
| 38 | } | ||
| 39 | |||
| 40 | extern int gpio_direction_input(unsigned gpio); | ||
| 41 | extern int gpio_direction_output(unsigned gpio, int value); | ||
| 42 | |||
| 43 | 30 | ||
| 44 | static inline int gpio_get_value(unsigned gpio) | 31 | static inline int gpio_get_value(unsigned gpio) |
| 45 | { | 32 | { |
| 46 | return GPLR & GPIO_GPIO(gpio); | 33 | if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) |
| 34 | return GPLR & GPIO_GPIO(gpio); | ||
| 35 | else | ||
| 36 | return __gpio_get_value(gpio); | ||
| 47 | } | 37 | } |
| 48 | 38 | ||
| 49 | static inline void gpio_set_value(unsigned gpio, int value) | 39 | static inline void gpio_set_value(unsigned gpio, int value) |
| 50 | { | 40 | { |
| 51 | if (value) | 41 | if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) |
| 52 | GPSR = GPIO_GPIO(gpio); | 42 | if (value) |
| 43 | GPSR = GPIO_GPIO(gpio); | ||
| 44 | else | ||
| 45 | GPCR = GPIO_GPIO(gpio); | ||
| 53 | else | 46 | else |
| 54 | GPCR = GPIO_GPIO(gpio); | 47 | __gpio_set_value(gpio, value); |
| 55 | } | 48 | } |
| 56 | 49 | ||
| 57 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 50 | #define gpio_cansleep __gpio_cansleep |
| 58 | 51 | ||
| 59 | static inline unsigned gpio_to_irq(unsigned gpio) | 52 | static inline unsigned gpio_to_irq(unsigned gpio) |
| 60 | { | 53 | { |
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h index 715e18a4add1..3479de9266e5 100644 --- a/include/asm-arm/cpu-multi32.h +++ b/include/asm-arm/cpu-multi32.h | |||
| @@ -21,6 +21,10 @@ extern struct processor { | |||
| 21 | */ | 21 | */ |
| 22 | void (*_data_abort)(unsigned long pc); | 22 | void (*_data_abort)(unsigned long pc); |
| 23 | /* | 23 | /* |
| 24 | * Retrieve prefetch fault address | ||
| 25 | */ | ||
| 26 | unsigned long (*_prefetch_abort)(unsigned long lr); | ||
| 27 | /* | ||
| 24 | * Set up any processor specifics | 28 | * Set up any processor specifics |
| 25 | */ | 29 | */ |
| 26 | void (*_proc_init)(void); | 30 | void (*_proc_init)(void); |
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h index 22274ce81375..a97a182ba287 100644 --- a/include/asm-arm/glue.h +++ b/include/asm-arm/glue.h | |||
| @@ -40,83 +40,110 @@ | |||
| 40 | * v6_early - ARMv6 generic early abort handler | 40 | * v6_early - ARMv6 generic early abort handler |
| 41 | * v7_early - ARMv7 generic early abort handler | 41 | * v7_early - ARMv7 generic early abort handler |
| 42 | */ | 42 | */ |
| 43 | #undef CPU_ABORT_HANDLER | 43 | #undef CPU_DABORT_HANDLER |
| 44 | #undef MULTI_ABORT | 44 | #undef MULTI_DABORT |
| 45 | 45 | ||
| 46 | #if defined(CONFIG_CPU_ARM610) | 46 | #if defined(CONFIG_CPU_ARM610) |
| 47 | # ifdef CPU_ABORT_HANDLER | 47 | # ifdef CPU_DABORT_HANDLER |
| 48 | # define MULTI_ABORT 1 | 48 | # define MULTI_DABORT 1 |
| 49 | # else | 49 | # else |
| 50 | # define CPU_ABORT_HANDLER cpu_arm6_data_abort | 50 | # define CPU_DABORT_HANDLER cpu_arm6_data_abort |
| 51 | # endif | 51 | # endif |
| 52 | #endif | 52 | #endif |
| 53 | 53 | ||
| 54 | #if defined(CONFIG_CPU_ARM710) | 54 | #if defined(CONFIG_CPU_ARM710) |
| 55 | # ifdef CPU_ABORT_HANDLER | 55 | # ifdef CPU_DABORT_HANDLER |
| 56 | # define MULTI_ABORT 1 | 56 | # define MULTI_DABORT 1 |
| 57 | # else | 57 | # else |
| 58 | # define CPU_ABORT_HANDLER cpu_arm7_data_abort | 58 | # define CPU_DABORT_HANDLER cpu_arm7_data_abort |
| 59 | # endif | 59 | # endif |
| 60 | #endif | 60 | #endif |
| 61 | 61 | ||
| 62 | #ifdef CONFIG_CPU_ABRT_LV4T | 62 | #ifdef CONFIG_CPU_ABRT_LV4T |
| 63 | # ifdef CPU_ABORT_HANDLER | 63 | # ifdef CPU_DABORT_HANDLER |
| 64 | # define MULTI_ABORT 1 | 64 | # define MULTI_DABORT 1 |
| 65 | # else | 65 | # else |
| 66 | # define CPU_ABORT_HANDLER v4t_late_abort | 66 | # define CPU_DABORT_HANDLER v4t_late_abort |
| 67 | # endif | 67 | # endif |
| 68 | #endif | 68 | #endif |
| 69 | 69 | ||
| 70 | #ifdef CONFIG_CPU_ABRT_EV4 | 70 | #ifdef CONFIG_CPU_ABRT_EV4 |
| 71 | # ifdef CPU_ABORT_HANDLER | 71 | # ifdef CPU_DABORT_HANDLER |
| 72 | # define MULTI_ABORT 1 | 72 | # define MULTI_DABORT 1 |
| 73 | # else | 73 | # else |
| 74 | # define CPU_ABORT_HANDLER v4_early_abort | 74 | # define CPU_DABORT_HANDLER v4_early_abort |
| 75 | # endif | 75 | # endif |
| 76 | #endif | 76 | #endif |
| 77 | 77 | ||
| 78 | #ifdef CONFIG_CPU_ABRT_EV4T | 78 | #ifdef CONFIG_CPU_ABRT_EV4T |
| 79 | # ifdef CPU_ABORT_HANDLER | 79 | # ifdef CPU_DABORT_HANDLER |
| 80 | # define MULTI_ABORT 1 | 80 | # define MULTI_DABORT 1 |
| 81 | # else | 81 | # else |
| 82 | # define CPU_ABORT_HANDLER v4t_early_abort | 82 | # define CPU_DABORT_HANDLER v4t_early_abort |
| 83 | # endif | 83 | # endif |
| 84 | #endif | 84 | #endif |
| 85 | 85 | ||
| 86 | #ifdef CONFIG_CPU_ABRT_EV5TJ | 86 | #ifdef CONFIG_CPU_ABRT_EV5TJ |
| 87 | # ifdef CPU_ABORT_HANDLER | 87 | # ifdef CPU_DABORT_HANDLER |
| 88 | # define MULTI_ABORT 1 | 88 | # define MULTI_DABORT 1 |
| 89 | # else | 89 | # else |
| 90 | # define CPU_ABORT_HANDLER v5tj_early_abort | 90 | # define CPU_DABORT_HANDLER v5tj_early_abort |
| 91 | # endif | 91 | # endif |
| 92 | #endif | 92 | #endif |
| 93 | 93 | ||
| 94 | #ifdef CONFIG_CPU_ABRT_EV5T | 94 | #ifdef CONFIG_CPU_ABRT_EV5T |
| 95 | # ifdef CPU_ABORT_HANDLER | 95 | # ifdef CPU_DABORT_HANDLER |
| 96 | # define MULTI_ABORT 1 | 96 | # define MULTI_DABORT 1 |
| 97 | # else | 97 | # else |
| 98 | # define CPU_ABORT_HANDLER v5t_early_abort | 98 | # define CPU_DABORT_HANDLER v5t_early_abort |
| 99 | # endif | 99 | # endif |
| 100 | #endif | 100 | #endif |
| 101 | 101 | ||
| 102 | #ifdef CONFIG_CPU_ABRT_EV6 | 102 | #ifdef CONFIG_CPU_ABRT_EV6 |
| 103 | # ifdef CPU_ABORT_HANDLER | 103 | # ifdef CPU_DABORT_HANDLER |
| 104 | # define MULTI_ABORT 1 | 104 | # define MULTI_DABORT 1 |
| 105 | # else | 105 | # else |
| 106 | # define CPU_ABORT_HANDLER v6_early_abort | 106 | # define CPU_DABORT_HANDLER v6_early_abort |
| 107 | # endif | 107 | # endif |
| 108 | #endif | 108 | #endif |
| 109 | 109 | ||
| 110 | #ifdef CONFIG_CPU_ABRT_EV7 | 110 | #ifdef CONFIG_CPU_ABRT_EV7 |
| 111 | # ifdef CPU_ABORT_HANDLER | 111 | # ifdef CPU_DABORT_HANDLER |
| 112 | # define MULTI_ABORT 1 | 112 | # define MULTI_DABORT 1 |
| 113 | # else | 113 | # else |
| 114 | # define CPU_ABORT_HANDLER v7_early_abort | 114 | # define CPU_DABORT_HANDLER v7_early_abort |
| 115 | # endif | 115 | # endif |
| 116 | #endif | 116 | #endif |
| 117 | 117 | ||
| 118 | #ifndef CPU_ABORT_HANDLER | 118 | #ifndef CPU_DABORT_HANDLER |
| 119 | #error Unknown data abort handler type | 119 | #error Unknown data abort handler type |
| 120 | #endif | 120 | #endif |
| 121 | 121 | ||
| 122 | /* | ||
| 123 | * Prefetch abort handler. If the CPU has an IFAR use that, otherwise | ||
| 124 | * use the address of the aborted instruction | ||
| 125 | */ | ||
| 126 | #undef CPU_PABORT_HANDLER | ||
| 127 | #undef MULTI_PABORT | ||
| 128 | |||
| 129 | #ifdef CONFIG_CPU_PABRT_IFAR | ||
| 130 | # ifdef CPU_PABORT_HANDLER | ||
| 131 | # define MULTI_PABORT 1 | ||
| 132 | # else | ||
| 133 | # define CPU_PABORT_HANDLER(reg, insn) mrc p15, 0, reg, cr6, cr0, 2 | ||
| 134 | # endif | ||
| 135 | #endif | ||
| 136 | |||
| 137 | #ifdef CONFIG_CPU_PABRT_NOIFAR | ||
| 138 | # ifdef CPU_PABORT_HANDLER | ||
| 139 | # define MULTI_PABORT 1 | ||
| 140 | # else | ||
| 141 | # define CPU_PABORT_HANDLER(reg, insn) mov reg, insn | ||
| 142 | # endif | ||
| 143 | #endif | ||
| 144 | |||
| 145 | #ifndef CPU_PABORT_HANDLER | ||
| 146 | #error Unknown prefetch abort handler type | ||
| 147 | #endif | ||
| 148 | |||
| 122 | #endif | 149 | #endif |
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h deleted file mode 100644 index 7d28eb5a1758..000000000000 --- a/include/asm-arm/hardware/arm_scu.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | #ifndef ASMARM_HARDWARE_ARM_SCU_H | ||
| 2 | #define ASMARM_HARDWARE_ARM_SCU_H | ||
| 3 | |||
| 4 | #include <asm/arch/scu.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * SCU registers | ||
| 8 | */ | ||
| 9 | #define SCU_CTRL 0x00 | ||
| 10 | #define SCU_CONFIG 0x04 | ||
| 11 | #define SCU_CPU_STATUS 0x08 | ||
| 12 | #define SCU_INVALIDATE 0x0c | ||
| 13 | #define SCU_FPGA_REVISION 0x10 | ||
| 14 | |||
| 15 | #endif | ||
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index ede377ec9147..18f6937f5010 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h | |||
| @@ -29,6 +29,7 @@ extern void gpio_line_config(int line, int direction); | |||
| 29 | extern int gpio_line_get(int line); | 29 | extern int gpio_line_get(int line); |
| 30 | extern void gpio_line_set(int line, int value); | 30 | extern void gpio_line_set(int line, int value); |
| 31 | extern int init_atu; | 31 | extern int init_atu; |
| 32 | extern int iop3xx_get_init_atu(void); | ||
| 32 | #endif | 33 | #endif |
| 33 | 34 | ||
| 34 | 35 | ||
| @@ -112,14 +113,6 @@ extern int init_atu; | |||
| 112 | #define IOP3XX_INIT_ATU_DISABLE -1 | 113 | #define IOP3XX_INIT_ATU_DISABLE -1 |
| 113 | #define IOP3XX_INIT_ATU_ENABLE 1 | 114 | #define IOP3XX_INIT_ATU_ENABLE 1 |
| 114 | 115 | ||
| 115 | #ifdef CONFIG_IOP3XX_ATU | ||
| 116 | #define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ | ||
| 117 | IOP3XX_INIT_ATU_ENABLE : init_atu) | ||
| 118 | #else | ||
| 119 | #define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ | ||
| 120 | IOP3XX_INIT_ATU_DISABLE : init_atu) | ||
| 121 | #endif | ||
| 122 | |||
| 123 | /* Messaging Unit */ | 116 | /* Messaging Unit */ |
| 124 | #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) | 117 | #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) |
| 125 | #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) | 118 | #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) |
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h index d37bf7443264..dfb8330599f9 100644 --- a/include/asm-arm/hardware/scoop.h +++ b/include/asm-arm/hardware/scoop.h | |||
| @@ -40,6 +40,7 @@ struct scoop_config { | |||
| 40 | unsigned short io_dir; | 40 | unsigned short io_dir; |
| 41 | unsigned short suspend_clr; | 41 | unsigned short suspend_clr; |
| 42 | unsigned short suspend_set; | 42 | unsigned short suspend_set; |
| 43 | int gpio_base; | ||
| 43 | }; | 44 | }; |
| 44 | 45 | ||
| 45 | /* Structure for linking scoop devices to PCMCIA sockets */ | 46 | /* Structure for linking scoop devices to PCMCIA sockets */ |
| @@ -62,7 +63,7 @@ struct scoop_pcmcia_config { | |||
| 62 | extern struct scoop_pcmcia_config *platform_scoop_config; | 63 | extern struct scoop_pcmcia_config *platform_scoop_config; |
| 63 | 64 | ||
| 64 | void reset_scoop(struct device *dev); | 65 | void reset_scoop(struct device *dev); |
| 65 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit); | 66 | unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit); |
| 66 | unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit); | 67 | unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit); |
| 67 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); | 68 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); |
| 68 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); | 69 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); |
diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h index 01a1391d3014..81f4c899a555 100644 --- a/include/asm-arm/hwcap.h +++ b/include/asm-arm/hwcap.h | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #define HWCAP_JAVA 256 | 15 | #define HWCAP_JAVA 256 |
| 16 | #define HWCAP_IWMMXT 512 | 16 | #define HWCAP_IWMMXT 512 |
| 17 | #define HWCAP_CRUNCH 1024 | 17 | #define HWCAP_CRUNCH 1024 |
| 18 | #define HWCAP_THUMBEE 2048 | ||
| 18 | 19 | ||
| 19 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | 20 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 20 | /* | 21 | /* |
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index 24621c49a0c7..9d4f6b5ea419 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h | |||
| @@ -55,6 +55,7 @@ void pci_common_init(struct hw_pci *); | |||
| 55 | extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); | 55 | extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); |
| 56 | extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); | 56 | extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); |
| 57 | extern void iop3xx_pci_preinit(void); | 57 | extern void iop3xx_pci_preinit(void); |
| 58 | extern void iop3xx_pci_preinit_cond(void); | ||
| 58 | 59 | ||
| 59 | extern int dc21285_setup(int nr, struct pci_sys_data *); | 60 | extern int dc21285_setup(int nr, struct pci_sys_data *); |
| 60 | extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); | 61 | extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); |
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index d9bfb39adabf..9ba4d7136e6b 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h | |||
| @@ -217,7 +217,10 @@ static inline __deprecated void *bus_to_virt(unsigned long x) | |||
| 217 | #ifndef CONFIG_DISCONTIGMEM | 217 | #ifndef CONFIG_DISCONTIGMEM |
| 218 | 218 | ||
| 219 | #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET | 219 | #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET |
| 220 | |||
| 221 | #ifndef CONFIG_SPARSEMEM | ||
| 220 | #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) | 222 | #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) |
| 223 | #endif | ||
| 221 | 224 | ||
| 222 | #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) | 225 | #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) |
| 223 | #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) | 226 | #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) |
diff --git a/include/asm-arm/plat-orion/ehci-orion.h b/include/asm-arm/plat-orion/ehci-orion.h new file mode 100644 index 000000000000..785705651e24 --- /dev/null +++ b/include/asm-arm/plat-orion/ehci-orion.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/plat-orion/ehci-orion.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_PLAT_ORION_EHCI_ORION_H | ||
| 10 | #define __ASM_PLAT_ORION_EHCI_ORION_H | ||
| 11 | |||
| 12 | #include <linux/mbus.h> | ||
| 13 | |||
| 14 | struct orion_ehci_data { | ||
| 15 | struct mbus_dram_target_info *dram; | ||
| 16 | }; | ||
| 17 | |||
| 18 | |||
| 19 | #endif | ||
diff --git a/include/asm-arm/plat-orion/irq.h b/include/asm-arm/plat-orion/irq.h new file mode 100644 index 000000000000..94aeed919d5b --- /dev/null +++ b/include/asm-arm/plat-orion/irq.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/plat-orion/irq.h | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC IRQ handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_PLAT_ORION_IRQ_H | ||
| 12 | #define __ASM_PLAT_ORION_IRQ_H | ||
| 13 | |||
| 14 | void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr); | ||
| 15 | |||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/plat-orion/orion_nand.h index 143c38e2fa0b..ffd3852a0dd7 100644 --- a/include/asm-arm/arch-orion/platform.h +++ b/include/asm-arm/plat-orion/orion_nand.h | |||
| @@ -1,15 +1,13 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * asm-arm/arch-orion/platform.h | 2 | * include/asm-arm/plat-orion/orion_nand.h |
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | 3 | * |
| 6 | * This file is licensed under the terms of the GNU General Public | 4 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any | 5 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. | 6 | * warranty of any kind, whether express or implied. |
| 9 | */ | 7 | */ |
| 10 | 8 | ||
| 11 | #ifndef __ASM_ARCH_PLATFORM_H__ | 9 | #ifndef __ASM_PLAT_ORION_ORION_NAND_H |
| 12 | #define __ASM_ARCH_PLATFORM_H__ | 10 | #define __ASM_PLAT_ORION_ORION_NAND_H |
| 13 | 11 | ||
| 14 | /* | 12 | /* |
| 15 | * Device bus NAND private data | 13 | * Device bus NAND private data |
| @@ -22,4 +20,5 @@ struct orion_nand_data { | |||
| 22 | u8 width; /* buswidth */ | 20 | u8 width; /* buswidth */ |
| 23 | }; | 21 | }; |
| 24 | 22 | ||
| 23 | |||
| 25 | #endif | 24 | #endif |
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h new file mode 100644 index 000000000000..6434ac685d21 --- /dev/null +++ b/include/asm-arm/plat-orion/pcie.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/plat-orion/pcie.h | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC PCIe handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_PLAT_ORION_PCIE_H | ||
| 12 | #define __ASM_PLAT_ORION_PCIE_H | ||
| 13 | |||
| 14 | u32 orion_pcie_dev_id(void __iomem *base); | ||
| 15 | u32 orion_pcie_rev(void __iomem *base); | ||
| 16 | int orion_pcie_link_up(void __iomem *base); | ||
| 17 | int orion_pcie_get_local_bus_nr(void __iomem *base); | ||
| 18 | void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); | ||
| 19 | void orion_pcie_setup(void __iomem *base, | ||
| 20 | struct mbus_dram_target_info *dram); | ||
| 21 | int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, | ||
| 22 | u32 devfn, int where, int size, u32 *val); | ||
| 23 | int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, | ||
| 24 | u32 devfn, int where, int size, u32 *val); | ||
| 25 | int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, | ||
| 26 | u32 devfn, int where, int size, u32 *val); | ||
| 27 | int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, | ||
| 28 | u32 devfn, int where, int size, u32 val); | ||
| 29 | |||
| 30 | |||
| 31 | #endif | ||
diff --git a/include/asm-arm/plat-orion/time.h b/include/asm-arm/plat-orion/time.h new file mode 100644 index 000000000000..0e85cc8f44d9 --- /dev/null +++ b/include/asm-arm/plat-orion/time.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/plat-orion/time.h | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC time handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_PLAT_ORION_TIME_H | ||
| 12 | #define __ASM_PLAT_ORION_TIME_H | ||
| 13 | |||
| 14 | void orion_time_init(unsigned int irq, unsigned int tclk); | ||
| 15 | |||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-arm/sparsemem.h b/include/asm-arm/sparsemem.h new file mode 100644 index 000000000000..277158191a0d --- /dev/null +++ b/include/asm-arm/sparsemem.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | #ifndef ASMARM_SPARSEMEM_H | ||
| 2 | #define ASMARM_SPARSEMEM_H | ||
| 3 | |||
| 4 | #include <asm/memory.h> | ||
| 5 | |||
| 6 | #define MAX_PHYSADDR_BITS 32 | ||
| 7 | #define MAX_PHYSMEM_BITS 32 | ||
| 8 | #define SECTION_SIZE_BITS NODE_MEM_SIZE_BITS | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index 41784357a204..f5a664786311 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h | |||
| @@ -62,6 +62,9 @@ struct thread_info { | |||
| 62 | struct crunch_state crunchstate; | 62 | struct crunch_state crunchstate; |
| 63 | union fp_state fpstate __attribute__((aligned(8))); | 63 | union fp_state fpstate __attribute__((aligned(8))); |
| 64 | union vfp_state vfpstate; | 64 | union vfp_state vfpstate; |
| 65 | #ifdef CONFIG_ARM_THUMBEE | ||
| 66 | unsigned long thumbee_state; /* ThumbEE Handler Base register */ | ||
| 67 | #endif | ||
| 65 | struct restart_block restart_block; | 68 | struct restart_block restart_block; |
| 66 | }; | 69 | }; |
| 67 | 70 | ||
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index 88e868b7aae0..7c570082b1e0 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h | |||
| @@ -376,9 +376,11 @@ | |||
| 376 | #define __NR_kexec_load (__NR_SYSCALL_BASE+347) | 376 | #define __NR_kexec_load (__NR_SYSCALL_BASE+347) |
| 377 | #define __NR_utimensat (__NR_SYSCALL_BASE+348) | 377 | #define __NR_utimensat (__NR_SYSCALL_BASE+348) |
| 378 | #define __NR_signalfd (__NR_SYSCALL_BASE+349) | 378 | #define __NR_signalfd (__NR_SYSCALL_BASE+349) |
| 379 | #define __NR_timerfd (__NR_SYSCALL_BASE+350) | 379 | #define __NR_timerfd_create (__NR_SYSCALL_BASE+350) |
| 380 | #define __NR_eventfd (__NR_SYSCALL_BASE+351) | 380 | #define __NR_eventfd (__NR_SYSCALL_BASE+351) |
| 381 | #define __NR_fallocate (__NR_SYSCALL_BASE+352) | 381 | #define __NR_fallocate (__NR_SYSCALL_BASE+352) |
| 382 | #define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) | ||
| 383 | #define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) | ||
| 382 | 384 | ||
| 383 | /* | 385 | /* |
| 384 | * The following SWIs are ARM private. | 386 | * The following SWIs are ARM private. |
diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h index b856a2a590d9..9a26c83a2c9e 100644 --- a/include/linux/ata_platform.h +++ b/include/linux/ata_platform.h | |||
| @@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev); | |||
| 27 | /* | 27 | /* |
| 28 | * Marvell SATA private data | 28 | * Marvell SATA private data |
| 29 | */ | 29 | */ |
| 30 | struct mbus_dram_target_info; | ||
| 31 | |||
| 30 | struct mv_sata_platform_data { | 32 | struct mv_sata_platform_data { |
| 33 | struct mbus_dram_target_info *dram; | ||
| 31 | int n_ports; /* number of sata ports */ | 34 | int n_ports; /* number of sata ports */ |
| 32 | }; | 35 | }; |
| 33 | 36 | ||
diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 000000000000..c11ff2932549 --- /dev/null +++ b/include/linux/mbus.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* | ||
| 2 | * Marvell MBUS common definitions. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Marvell Semiconductor | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __LINUX_MBUS_H | ||
| 12 | #define __LINUX_MBUS_H | ||
| 13 | |||
| 14 | struct mbus_dram_target_info | ||
| 15 | { | ||
| 16 | /* | ||
| 17 | * The 4-bit MBUS target ID of the DRAM controller. | ||
| 18 | */ | ||
| 19 | u8 mbus_dram_target_id; | ||
| 20 | |||
| 21 | /* | ||
| 22 | * The base address, size, and MBUS attribute ID for each | ||
| 23 | * of the possible DRAM chip selects. Peripherals are | ||
| 24 | * required to support at least 4 decode windows. | ||
| 25 | */ | ||
| 26 | int num_cs; | ||
| 27 | struct mbus_dram_window { | ||
| 28 | u8 cs_index; | ||
| 29 | u8 mbus_attr; | ||
| 30 | u32 base; | ||
| 31 | u32 size; | ||
| 32 | } cs[4]; | ||
| 33 | }; | ||
| 34 | |||
| 35 | |||
| 36 | #endif | ||
diff --git a/include/linux/mfd/htc-egpio.h b/include/linux/mfd/htc-egpio.h new file mode 100644 index 000000000000..b4201c971367 --- /dev/null +++ b/include/linux/mfd/htc-egpio.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * HTC simple EGPIO irq and gpio extender | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __HTC_EGPIO_H__ | ||
| 6 | #define __HTC_EGPIO_H__ | ||
| 7 | |||
| 8 | #include <linux/gpio.h> | ||
| 9 | |||
| 10 | /* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */ | ||
| 11 | #define HTC_EGPIO_OUTPUT (~0) | ||
| 12 | #define HTC_EGPIO_INPUT 0 | ||
| 13 | |||
| 14 | /** | ||
| 15 | * struct htc_egpio_chip - descriptor to create gpio_chip for register range | ||
| 16 | * @reg_start: index of first register | ||
| 17 | * @gpio_base: gpio number of first pin in this register range | ||
| 18 | * @num_gpios: number of gpios in this register range, max BITS_PER_LONG | ||
| 19 | * (number of registers = DIV_ROUND_UP(num_gpios, reg_width)) | ||
| 20 | * @direction: bitfield, '0' = input, '1' = output, | ||
| 21 | */ | ||
| 22 | struct htc_egpio_chip { | ||
| 23 | int reg_start; | ||
| 24 | int gpio_base; | ||
| 25 | int num_gpios; | ||
| 26 | unsigned long direction; | ||
| 27 | unsigned long initial_values; | ||
| 28 | }; | ||
| 29 | |||
| 30 | /** | ||
| 31 | * struct htc_egpio_platform_data - description provided by the arch | ||
| 32 | * @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START) | ||
| 33 | * @num_irqs: number of irqs | ||
| 34 | * @reg_width: number of bits per register, either 8 or 16 bit | ||
| 35 | * @bus_width: alignment of the registers, either 16 or 32 bit | ||
| 36 | * @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1' | ||
| 37 | * @ack_register: location of the irq/ack register | ||
| 38 | * @chip: pointer to array of htc_egpio_chip descriptors | ||
| 39 | * @num_chips: number of egpio chip descriptors | ||
| 40 | */ | ||
| 41 | struct htc_egpio_platform_data { | ||
| 42 | int bus_width; | ||
| 43 | int reg_width; | ||
| 44 | |||
| 45 | int irq_base; | ||
| 46 | int num_irqs; | ||
| 47 | int invert_acks; | ||
| 48 | int ack_register; | ||
| 49 | |||
| 50 | struct htc_egpio_chip *chip; | ||
| 51 | int num_chips; | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* Determine the wakeup irq, to be called during early resume */ | ||
| 55 | extern int htc_egpio_get_wakeup_irq(struct device *dev); | ||
| 56 | |||
| 57 | #endif | ||
diff --git a/include/linux/mfd/htc-pasic3.h b/include/linux/mfd/htc-pasic3.h new file mode 100644 index 000000000000..b4294f12c4f8 --- /dev/null +++ b/include/linux/mfd/htc-pasic3.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * HTC PASIC3 driver - LEDs and DS1WM | ||
| 3 | * | ||
| 4 | * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com> | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __PASIC3_H | ||
| 13 | #define __PASIC3_H | ||
| 14 | |||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/leds.h> | ||
| 17 | |||
| 18 | extern void pasic3_write_register(struct device *dev, u32 reg, u8 val); | ||
| 19 | extern u8 pasic3_read_register(struct device *dev, u32 reg); | ||
| 20 | |||
| 21 | /* | ||
| 22 | * mask for registers 0x20,0x21,0x22 | ||
| 23 | */ | ||
| 24 | #define PASIC3_MASK_LED0 0x04 | ||
| 25 | #define PASIC3_MASK_LED1 0x08 | ||
| 26 | #define PASIC3_MASK_LED2 0x40 | ||
| 27 | |||
| 28 | /* | ||
| 29 | * bits in register 0x06 | ||
| 30 | */ | ||
| 31 | #define PASIC3_BIT2_LED0 0x08 | ||
| 32 | #define PASIC3_BIT2_LED1 0x10 | ||
| 33 | #define PASIC3_BIT2_LED2 0x20 | ||
| 34 | |||
| 35 | struct pasic3_led { | ||
| 36 | struct led_classdev led; | ||
| 37 | unsigned int hw_num; | ||
| 38 | unsigned int bit2; | ||
| 39 | unsigned int mask; | ||
| 40 | struct pasic3_leds_machinfo *pdata; | ||
| 41 | }; | ||
| 42 | |||
| 43 | struct pasic3_leds_machinfo { | ||
| 44 | unsigned int num_leds; | ||
| 45 | unsigned int power_gpio; | ||
| 46 | struct pasic3_led *leds; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct pasic3_platform_data { | ||
| 50 | struct pasic3_leds_machinfo *led_pdata; | ||
| 51 | unsigned int bus_shift; | ||
| 52 | unsigned int clock_rate; | ||
| 53 | }; | ||
| 54 | |||
| 55 | #endif | ||
diff --git a/include/linux/sched.h b/include/linux/sched.h index fed07d03364e..6a1e7afb099b 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h | |||
| @@ -1541,6 +1541,12 @@ static inline void idle_task_exit(void) {} | |||
| 1541 | 1541 | ||
| 1542 | extern void sched_idle_next(void); | 1542 | extern void sched_idle_next(void); |
| 1543 | 1543 | ||
| 1544 | #if defined(CONFIG_NO_HZ) && defined(CONFIG_SMP) | ||
| 1545 | extern void wake_up_idle_cpu(int cpu); | ||
| 1546 | #else | ||
| 1547 | static inline void wake_up_idle_cpu(int cpu) { } | ||
| 1548 | #endif | ||
| 1549 | |||
| 1544 | #ifdef CONFIG_SCHED_DEBUG | 1550 | #ifdef CONFIG_SCHED_DEBUG |
| 1545 | extern unsigned int sysctl_sched_latency; | 1551 | extern unsigned int sysctl_sched_latency; |
| 1546 | extern unsigned int sysctl_sched_min_granularity; | 1552 | extern unsigned int sysctl_sched_min_granularity; |
diff --git a/kernel/relay.c b/kernel/relay.c index 4c035a8a248c..d6204a485818 100644 --- a/kernel/relay.c +++ b/kernel/relay.c | |||
| @@ -736,7 +736,7 @@ static int relay_file_open(struct inode *inode, struct file *filp) | |||
| 736 | kref_get(&buf->kref); | 736 | kref_get(&buf->kref); |
| 737 | filp->private_data = buf; | 737 | filp->private_data = buf; |
| 738 | 738 | ||
| 739 | return 0; | 739 | return nonseekable_open(inode, filp); |
| 740 | } | 740 | } |
| 741 | 741 | ||
| 742 | /** | 742 | /** |
| @@ -1056,6 +1056,10 @@ static struct pipe_buf_operations relay_pipe_buf_ops = { | |||
| 1056 | .get = generic_pipe_buf_get, | 1056 | .get = generic_pipe_buf_get, |
| 1057 | }; | 1057 | }; |
| 1058 | 1058 | ||
| 1059 | static void relay_page_release(struct splice_pipe_desc *spd, unsigned int i) | ||
| 1060 | { | ||
| 1061 | } | ||
| 1062 | |||
| 1059 | /* | 1063 | /* |
| 1060 | * subbuf_splice_actor - splice up to one subbuf's worth of data | 1064 | * subbuf_splice_actor - splice up to one subbuf's worth of data |
| 1061 | */ | 1065 | */ |
| @@ -1083,6 +1087,7 @@ static int subbuf_splice_actor(struct file *in, | |||
| 1083 | .partial = partial, | 1087 | .partial = partial, |
| 1084 | .flags = flags, | 1088 | .flags = flags, |
| 1085 | .ops = &relay_pipe_buf_ops, | 1089 | .ops = &relay_pipe_buf_ops, |
| 1090 | .spd_release = relay_page_release, | ||
| 1086 | }; | 1091 | }; |
| 1087 | 1092 | ||
| 1088 | if (rbuf->subbufs_produced == rbuf->subbufs_consumed) | 1093 | if (rbuf->subbufs_produced == rbuf->subbufs_consumed) |
diff --git a/kernel/sched.c b/kernel/sched.c index 28c73f07efb2..8dcdec6fe0fe 100644 --- a/kernel/sched.c +++ b/kernel/sched.c | |||
| @@ -1052,6 +1052,49 @@ static void resched_cpu(int cpu) | |||
| 1052 | resched_task(cpu_curr(cpu)); | 1052 | resched_task(cpu_curr(cpu)); |
| 1053 | spin_unlock_irqrestore(&rq->lock, flags); | 1053 | spin_unlock_irqrestore(&rq->lock, flags); |
| 1054 | } | 1054 | } |
| 1055 | |||
| 1056 | #ifdef CONFIG_NO_HZ | ||
| 1057 | /* | ||
| 1058 | * When add_timer_on() enqueues a timer into the timer wheel of an | ||
| 1059 | * idle CPU then this timer might expire before the next timer event | ||
| 1060 | * which is scheduled to wake up that CPU. In case of a completely | ||
| 1061 | * idle system the next event might even be infinite time into the | ||
| 1062 | * future. wake_up_idle_cpu() ensures that the CPU is woken up and | ||
| 1063 | * leaves the inner idle loop so the newly added timer is taken into | ||
| 1064 | * account when the CPU goes back to idle and evaluates the timer | ||
| 1065 | * wheel for the next timer event. | ||
| 1066 | */ | ||
| 1067 | void wake_up_idle_cpu(int cpu) | ||
| 1068 | { | ||
| 1069 | struct rq *rq = cpu_rq(cpu); | ||
| 1070 | |||
| 1071 | if (cpu == smp_processor_id()) | ||
| 1072 | return; | ||
| 1073 | |||
| 1074 | /* | ||
| 1075 | * This is safe, as this function is called with the timer | ||
| 1076 | * wheel base lock of (cpu) held. When the CPU is on the way | ||
| 1077 | * to idle and has not yet set rq->curr to idle then it will | ||
| 1078 | * be serialized on the timer wheel base lock and take the new | ||
| 1079 | * timer into account automatically. | ||
| 1080 | */ | ||
| 1081 | if (rq->curr != rq->idle) | ||
| 1082 | return; | ||
| 1083 | |||
| 1084 | /* | ||
| 1085 | * We can set TIF_RESCHED on the idle task of the other CPU | ||
| 1086 | * lockless. The worst case is that the other CPU runs the | ||
| 1087 | * idle task through an additional NOOP schedule() | ||
| 1088 | */ | ||
| 1089 | set_tsk_thread_flag(rq->idle, TIF_NEED_RESCHED); | ||
| 1090 | |||
| 1091 | /* NEED_RESCHED must be visible before we test polling */ | ||
| 1092 | smp_mb(); | ||
| 1093 | if (!tsk_is_polling(rq->idle)) | ||
| 1094 | smp_send_reschedule(cpu); | ||
| 1095 | } | ||
| 1096 | #endif | ||
| 1097 | |||
| 1055 | #else | 1098 | #else |
| 1056 | static void __resched_task(struct task_struct *p, int tif_bit) | 1099 | static void __resched_task(struct task_struct *p, int tif_bit) |
| 1057 | { | 1100 | { |
diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c index 278534bbca95..7f60097d443a 100644 --- a/kernel/time/clocksource.c +++ b/kernel/time/clocksource.c | |||
| @@ -174,7 +174,7 @@ static void clocksource_check_watchdog(struct clocksource *cs) | |||
| 174 | if (watchdog) | 174 | if (watchdog) |
| 175 | del_timer(&watchdog_timer); | 175 | del_timer(&watchdog_timer); |
| 176 | watchdog = cs; | 176 | watchdog = cs; |
| 177 | init_timer_deferrable(&watchdog_timer); | 177 | init_timer(&watchdog_timer); |
| 178 | watchdog_timer.function = clocksource_watchdog; | 178 | watchdog_timer.function = clocksource_watchdog; |
| 179 | 179 | ||
| 180 | /* Reset watchdog cycles */ | 180 | /* Reset watchdog cycles */ |
diff --git a/kernel/timer.c b/kernel/timer.c index 99b00a25f88b..b024106daa70 100644 --- a/kernel/timer.c +++ b/kernel/timer.c | |||
| @@ -451,10 +451,18 @@ void add_timer_on(struct timer_list *timer, int cpu) | |||
| 451 | spin_lock_irqsave(&base->lock, flags); | 451 | spin_lock_irqsave(&base->lock, flags); |
| 452 | timer_set_base(timer, base); | 452 | timer_set_base(timer, base); |
| 453 | internal_add_timer(base, timer); | 453 | internal_add_timer(base, timer); |
| 454 | /* | ||
| 455 | * Check whether the other CPU is idle and needs to be | ||
| 456 | * triggered to reevaluate the timer wheel when nohz is | ||
| 457 | * active. We are protected against the other CPU fiddling | ||
| 458 | * with the timer by holding the timer base lock. This also | ||
| 459 | * makes sure that a CPU on the way to idle can not evaluate | ||
| 460 | * the timer wheel. | ||
| 461 | */ | ||
| 462 | wake_up_idle_cpu(cpu); | ||
| 454 | spin_unlock_irqrestore(&base->lock, flags); | 463 | spin_unlock_irqrestore(&base->lock, flags); |
| 455 | } | 464 | } |
| 456 | 465 | ||
| 457 | |||
| 458 | /** | 466 | /** |
| 459 | * mod_timer - modify a timer's timeout | 467 | * mod_timer - modify a timer's timeout |
| 460 | * @timer: the timer to be modified | 468 | * @timer: the timer to be modified |
| @@ -1481,7 +1481,7 @@ void __init kmem_cache_init(void) | |||
| 1481 | list_add(&cache_cache.next, &cache_chain); | 1481 | list_add(&cache_cache.next, &cache_chain); |
| 1482 | cache_cache.colour_off = cache_line_size(); | 1482 | cache_cache.colour_off = cache_line_size(); |
| 1483 | cache_cache.array[smp_processor_id()] = &initarray_cache.cache; | 1483 | cache_cache.array[smp_processor_id()] = &initarray_cache.cache; |
| 1484 | cache_cache.nodelists[node] = &initkmem_list3[CACHE_CACHE]; | 1484 | cache_cache.nodelists[node] = &initkmem_list3[CACHE_CACHE + node]; |
| 1485 | 1485 | ||
| 1486 | /* | 1486 | /* |
| 1487 | * struct kmem_cache size depends on nr_node_ids, which | 1487 | * struct kmem_cache size depends on nr_node_ids, which |
| @@ -1602,7 +1602,7 @@ void __init kmem_cache_init(void) | |||
| 1602 | int nid; | 1602 | int nid; |
| 1603 | 1603 | ||
| 1604 | for_each_online_node(nid) { | 1604 | for_each_online_node(nid) { |
| 1605 | init_list(&cache_cache, &initkmem_list3[CACHE_CACHE], nid); | 1605 | init_list(&cache_cache, &initkmem_list3[CACHE_CACHE + nid], nid); |
| 1606 | 1606 | ||
| 1607 | init_list(malloc_sizes[INDEX_AC].cs_cachep, | 1607 | init_list(malloc_sizes[INDEX_AC].cs_cachep, |
| 1608 | &initkmem_list3[SIZE_AC + nid], nid); | 1608 | &initkmem_list3[SIZE_AC + nid], nid); |
| @@ -2685,6 +2685,7 @@ void kfree(const void *x) | |||
| 2685 | } | 2685 | } |
| 2686 | EXPORT_SYMBOL(kfree); | 2686 | EXPORT_SYMBOL(kfree); |
| 2687 | 2687 | ||
| 2688 | #if defined(SLUB_DEBUG) || defined(CONFIG_SLABINFO) | ||
| 2688 | static unsigned long count_partial(struct kmem_cache_node *n) | 2689 | static unsigned long count_partial(struct kmem_cache_node *n) |
| 2689 | { | 2690 | { |
| 2690 | unsigned long flags; | 2691 | unsigned long flags; |
| @@ -2697,6 +2698,7 @@ static unsigned long count_partial(struct kmem_cache_node *n) | |||
| 2697 | spin_unlock_irqrestore(&n->list_lock, flags); | 2698 | spin_unlock_irqrestore(&n->list_lock, flags); |
| 2698 | return x; | 2699 | return x; |
| 2699 | } | 2700 | } |
| 2701 | #endif | ||
| 2700 | 2702 | ||
| 2701 | /* | 2703 | /* |
| 2702 | * kmem_cache_shrink removes empty slabs from the partial lists and sorts | 2704 | * kmem_cache_shrink removes empty slabs from the partial lists and sorts |
diff --git a/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c b/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c index 971271602dd0..c22d6b6f2db4 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c +++ b/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c | |||
| @@ -322,15 +322,6 @@ next_sge: | |||
| 322 | ctxt->direction = DMA_FROM_DEVICE; | 322 | ctxt->direction = DMA_FROM_DEVICE; |
| 323 | clear_bit(RDMACTXT_F_READ_DONE, &ctxt->flags); | 323 | clear_bit(RDMACTXT_F_READ_DONE, &ctxt->flags); |
| 324 | clear_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags); | 324 | clear_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags); |
| 325 | if ((ch+1)->rc_discrim == 0) { | ||
| 326 | /* | ||
| 327 | * Checked in sq_cq_reap to see if we need to | ||
| 328 | * be enqueued | ||
| 329 | */ | ||
| 330 | set_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags); | ||
| 331 | ctxt->next = hdr_ctxt; | ||
| 332 | hdr_ctxt->next = head; | ||
| 333 | } | ||
| 334 | 325 | ||
| 335 | /* Prepare READ WR */ | 326 | /* Prepare READ WR */ |
| 336 | memset(&read_wr, 0, sizeof read_wr); | 327 | memset(&read_wr, 0, sizeof read_wr); |
| @@ -348,7 +339,17 @@ next_sge: | |||
| 348 | rdma_set_ctxt_sge(ctxt, &sge[ch_sge_ary[ch_no].start], | 339 | rdma_set_ctxt_sge(ctxt, &sge[ch_sge_ary[ch_no].start], |
| 349 | &sgl_offset, | 340 | &sgl_offset, |
| 350 | read_wr.num_sge); | 341 | read_wr.num_sge); |
| 351 | 342 | if (((ch+1)->rc_discrim == 0) && | |
| 343 | (read_wr.num_sge == ch_sge_ary[ch_no].count)) { | ||
| 344 | /* | ||
| 345 | * Mark the last RDMA_READ with a bit to | ||
| 346 | * indicate all RPC data has been fetched from | ||
| 347 | * the client and the RPC needs to be enqueued. | ||
| 348 | */ | ||
| 349 | set_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags); | ||
| 350 | ctxt->next = hdr_ctxt; | ||
| 351 | hdr_ctxt->next = head; | ||
| 352 | } | ||
| 352 | /* Post the read */ | 353 | /* Post the read */ |
| 353 | err = svc_rdma_send(xprt, &read_wr); | 354 | err = svc_rdma_send(xprt, &read_wr); |
| 354 | if (err) { | 355 | if (err) { |
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c index 5d86e6809752..8704e2825b10 100644 --- a/sound/arm/pxa2xx-ac97.c +++ b/sound/arm/pxa2xx-ac97.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/wait.h> | 18 | #include <linux/wait.h> |
| 19 | #include <linux/clk.h> | ||
| 19 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
| 20 | 21 | ||
| 21 | #include <sound/core.h> | 22 | #include <sound/core.h> |
| @@ -27,6 +28,7 @@ | |||
| 27 | #include <linux/mutex.h> | 28 | #include <linux/mutex.h> |
| 28 | #include <asm/hardware.h> | 29 | #include <asm/hardware.h> |
| 29 | #include <asm/arch/pxa-regs.h> | 30 | #include <asm/arch/pxa-regs.h> |
| 31 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 30 | #include <asm/arch/audio.h> | 32 | #include <asm/arch/audio.h> |
| 31 | 33 | ||
| 32 | #include "pxa2xx-pcm.h" | 34 | #include "pxa2xx-pcm.h" |
| @@ -35,6 +37,10 @@ | |||
| 35 | static DEFINE_MUTEX(car_mutex); | 37 | static DEFINE_MUTEX(car_mutex); |
| 36 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); | 38 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); |
| 37 | static volatile long gsr_bits; | 39 | static volatile long gsr_bits; |
| 40 | static struct clk *ac97_clk; | ||
| 41 | #ifdef CONFIG_PXA27x | ||
| 42 | static struct clk *ac97conf_clk; | ||
| 43 | #endif | ||
| 38 | 44 | ||
| 39 | /* | 45 | /* |
| 40 | * Beware PXA27x bugs: | 46 | * Beware PXA27x bugs: |
| @@ -112,9 +118,9 @@ static void pxa2xx_ac97_reset(struct snd_ac97 *ac97) | |||
| 112 | gsr_bits = 0; | 118 | gsr_bits = 0; |
| 113 | #ifdef CONFIG_PXA27x | 119 | #ifdef CONFIG_PXA27x |
| 114 | /* PXA27x Developers Manual section 13.5.2.2.1 */ | 120 | /* PXA27x Developers Manual section 13.5.2.2.1 */ |
| 115 | pxa_set_cken(CKEN_AC97CONF, 1); | 121 | clk_enable(ac97conf_clk); |
| 116 | udelay(5); | 122 | udelay(5); |
| 117 | pxa_set_cken(CKEN_AC97CONF, 0); | 123 | clk_disable(ac97conf_clk); |
| 118 | GCR = GCR_COLD_RST; | 124 | GCR = GCR_COLD_RST; |
| 119 | udelay(50); | 125 | udelay(50); |
| 120 | #else | 126 | #else |
| @@ -259,7 +265,7 @@ static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state) | |||
| 259 | if (platform_ops && platform_ops->suspend) | 265 | if (platform_ops && platform_ops->suspend) |
| 260 | platform_ops->suspend(platform_ops->priv); | 266 | platform_ops->suspend(platform_ops->priv); |
| 261 | GCR |= GCR_ACLINK_OFF; | 267 | GCR |= GCR_ACLINK_OFF; |
| 262 | pxa_set_cken(CKEN_AC97, 0); | 268 | clk_disable(ac97_clk); |
| 263 | 269 | ||
| 264 | return 0; | 270 | return 0; |
| 265 | } | 271 | } |
| @@ -268,7 +274,7 @@ static int pxa2xx_ac97_do_resume(struct snd_card *card) | |||
| 268 | { | 274 | { |
| 269 | pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data; | 275 | pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data; |
| 270 | 276 | ||
| 271 | pxa_set_cken(CKEN_AC97, 1); | 277 | clk_enable(ac97_clk); |
| 272 | if (platform_ops && platform_ops->resume) | 278 | if (platform_ops && platform_ops->resume) |
| 273 | platform_ops->resume(platform_ops->priv); | 279 | platform_ops->resume(platform_ops->priv); |
| 274 | snd_ac97_resume(pxa2xx_ac97_ac97); | 280 | snd_ac97_resume(pxa2xx_ac97_ac97); |
| @@ -335,8 +341,21 @@ static int __devinit pxa2xx_ac97_probe(struct platform_device *dev) | |||
| 335 | #ifdef CONFIG_PXA27x | 341 | #ifdef CONFIG_PXA27x |
| 336 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | 342 | /* Use GPIO 113 as AC97 Reset on Bulverde */ |
| 337 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | 343 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); |
| 344 | ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); | ||
| 345 | if (IS_ERR(ac97conf_clk)) { | ||
| 346 | ret = PTR_ERR(ac97conf_clk); | ||
| 347 | ac97conf_clk = NULL; | ||
| 348 | goto err; | ||
| 349 | } | ||
| 338 | #endif | 350 | #endif |
| 339 | pxa_set_cken(CKEN_AC97, 1); | 351 | |
| 352 | ac97_clk = clk_get(&dev->dev, "AC97CLK"); | ||
| 353 | if (IS_ERR(ac97_clk)) { | ||
| 354 | ret = PTR_ERR(ac97_clk); | ||
| 355 | ac97_clk = NULL; | ||
| 356 | goto err; | ||
| 357 | } | ||
| 358 | clk_enable(ac97_clk); | ||
| 340 | 359 | ||
| 341 | ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus); | 360 | ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus); |
| 342 | if (ret) | 361 | if (ret) |
| @@ -361,11 +380,19 @@ static int __devinit pxa2xx_ac97_probe(struct platform_device *dev) | |||
| 361 | err: | 380 | err: |
| 362 | if (card) | 381 | if (card) |
| 363 | snd_card_free(card); | 382 | snd_card_free(card); |
| 364 | if (CKEN & (1 << CKEN_AC97)) { | 383 | if (ac97_clk) { |
| 365 | GCR |= GCR_ACLINK_OFF; | 384 | GCR |= GCR_ACLINK_OFF; |
| 366 | free_irq(IRQ_AC97, NULL); | 385 | free_irq(IRQ_AC97, NULL); |
| 367 | pxa_set_cken(CKEN_AC97, 0); | 386 | clk_disable(ac97_clk); |
| 387 | clk_put(ac97_clk); | ||
| 388 | ac97_clk = NULL; | ||
| 389 | } | ||
| 390 | #ifdef CONFIG_PXA27x | ||
| 391 | if (ac97conf_clk) { | ||
| 392 | clk_put(ac97conf_clk); | ||
| 393 | ac97conf_clk = NULL; | ||
| 368 | } | 394 | } |
| 395 | #endif | ||
| 369 | return ret; | 396 | return ret; |
| 370 | } | 397 | } |
| 371 | 398 | ||
| @@ -378,7 +405,13 @@ static int __devexit pxa2xx_ac97_remove(struct platform_device *dev) | |||
| 378 | platform_set_drvdata(dev, NULL); | 405 | platform_set_drvdata(dev, NULL); |
| 379 | GCR |= GCR_ACLINK_OFF; | 406 | GCR |= GCR_ACLINK_OFF; |
| 380 | free_irq(IRQ_AC97, NULL); | 407 | free_irq(IRQ_AC97, NULL); |
| 381 | pxa_set_cken(CKEN_AC97, 0); | 408 | clk_disable(ac97_clk); |
| 409 | clk_put(ac97_clk); | ||
| 410 | ac97_clk = NULL; | ||
| 411 | #ifdef CONFIG_PXA27x | ||
| 412 | clk_put(ac97conf_clk); | ||
| 413 | ac97conf_clk = NULL; | ||
| 414 | #endif | ||
| 382 | } | 415 | } |
| 383 | 416 | ||
| 384 | return 0; | 417 | return 0; |
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c index 815c15336255..e17379998802 100644 --- a/sound/soc/pxa/pxa2xx-ac97.c +++ b/sound/soc/pxa/pxa2xx-ac97.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/wait.h> | 17 | #include <linux/wait.h> |
| 18 | #include <linux/clk.h> | ||
| 18 | #include <linux/delay.h> | 19 | #include <linux/delay.h> |
| 19 | 20 | ||
| 20 | #include <sound/core.h> | 21 | #include <sound/core.h> |
| @@ -27,6 +28,7 @@ | |||
| 27 | #include <linux/mutex.h> | 28 | #include <linux/mutex.h> |
| 28 | #include <asm/hardware.h> | 29 | #include <asm/hardware.h> |
| 29 | #include <asm/arch/pxa-regs.h> | 30 | #include <asm/arch/pxa-regs.h> |
| 31 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 30 | #include <asm/arch/audio.h> | 32 | #include <asm/arch/audio.h> |
| 31 | 33 | ||
| 32 | #include "pxa2xx-pcm.h" | 34 | #include "pxa2xx-pcm.h" |
| @@ -35,6 +37,10 @@ | |||
| 35 | static DEFINE_MUTEX(car_mutex); | 37 | static DEFINE_MUTEX(car_mutex); |
| 36 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); | 38 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); |
| 37 | static volatile long gsr_bits; | 39 | static volatile long gsr_bits; |
| 40 | static struct clk *ac97_clk; | ||
| 41 | #ifdef CONFIG_PXA27x | ||
| 42 | static struct clk *ac97conf_clk; | ||
| 43 | #endif | ||
| 38 | 44 | ||
| 39 | /* | 45 | /* |
| 40 | * Beware PXA27x bugs: | 46 | * Beware PXA27x bugs: |
| @@ -159,9 +165,9 @@ static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) | |||
| 159 | gsr_bits = 0; | 165 | gsr_bits = 0; |
| 160 | #ifdef CONFIG_PXA27x | 166 | #ifdef CONFIG_PXA27x |
| 161 | /* PXA27x Developers Manual section 13.5.2.2.1 */ | 167 | /* PXA27x Developers Manual section 13.5.2.2.1 */ |
| 162 | pxa_set_cken(CKEN_AC97CONF, 1); | 168 | clk_enable(ac97conf_clk); |
| 163 | udelay(5); | 169 | udelay(5); |
| 164 | pxa_set_cken(CKEN_AC97CONF, 0); | 170 | clk_disable(ac97conf_clk); |
| 165 | GCR = GCR_COLD_RST; | 171 | GCR = GCR_COLD_RST; |
| 166 | udelay(50); | 172 | udelay(50); |
| 167 | #else | 173 | #else |
| @@ -255,7 +261,7 @@ static int pxa2xx_ac97_suspend(struct platform_device *pdev, | |||
| 255 | struct snd_soc_cpu_dai *dai) | 261 | struct snd_soc_cpu_dai *dai) |
| 256 | { | 262 | { |
| 257 | GCR |= GCR_ACLINK_OFF; | 263 | GCR |= GCR_ACLINK_OFF; |
| 258 | pxa_set_cken(CKEN_AC97, 0); | 264 | clk_disable(ac97_clk); |
| 259 | return 0; | 265 | return 0; |
| 260 | } | 266 | } |
| 261 | 267 | ||
| @@ -270,7 +276,7 @@ static int pxa2xx_ac97_resume(struct platform_device *pdev, | |||
| 270 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | 276 | /* Use GPIO 113 as AC97 Reset on Bulverde */ |
| 271 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | 277 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); |
| 272 | #endif | 278 | #endif |
| 273 | pxa_set_cken(CKEN_AC97, 1); | 279 | clk_enable(ac97_clk); |
| 274 | return 0; | 280 | return 0; |
| 275 | } | 281 | } |
| 276 | 282 | ||
| @@ -294,16 +300,33 @@ static int pxa2xx_ac97_probe(struct platform_device *pdev) | |||
| 294 | #ifdef CONFIG_PXA27x | 300 | #ifdef CONFIG_PXA27x |
| 295 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | 301 | /* Use GPIO 113 as AC97 Reset on Bulverde */ |
| 296 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | 302 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); |
| 303 | |||
| 304 | ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK"); | ||
| 305 | if (IS_ERR(ac97conf_clk)) { | ||
| 306 | ret = PTR_ERR(ac97conf_clk); | ||
| 307 | ac97conf_clk = NULL; | ||
| 308 | goto err_irq; | ||
| 309 | } | ||
| 297 | #endif | 310 | #endif |
| 298 | pxa_set_cken(CKEN_AC97, 1); | 311 | ac97_clk = clk_get(&pdev->dev, "AC97CLK"); |
| 312 | if (IS_ERR(ac97_clk)) { | ||
| 313 | ret = PTR_ERR(ac97_clk); | ||
| 314 | ac97_clk = NULL; | ||
| 315 | goto err_irq; | ||
| 316 | } | ||
| 317 | clk_enable(ac97_clk); | ||
| 299 | return 0; | 318 | return 0; |
| 300 | 319 | ||
| 301 | err: | 320 | err_irq: |
| 302 | if (CKEN & (1 << CKEN_AC97)) { | 321 | GCR |= GCR_ACLINK_OFF; |
| 303 | GCR |= GCR_ACLINK_OFF; | 322 | #ifdef CONFIG_PXA27x |
| 304 | free_irq(IRQ_AC97, NULL); | 323 | if (ac97conf_clk) { |
| 305 | pxa_set_cken(CKEN_AC97, 0); | 324 | clk_put(ac97conf_clk); |
| 325 | ac97conf_clk = NULL; | ||
| 306 | } | 326 | } |
| 327 | #endif | ||
| 328 | free_irq(IRQ_AC97, NULL); | ||
| 329 | err: | ||
| 307 | return ret; | 330 | return ret; |
| 308 | } | 331 | } |
| 309 | 332 | ||
| @@ -311,7 +334,13 @@ static void pxa2xx_ac97_remove(struct platform_device *pdev) | |||
| 311 | { | 334 | { |
| 312 | GCR |= GCR_ACLINK_OFF; | 335 | GCR |= GCR_ACLINK_OFF; |
| 313 | free_irq(IRQ_AC97, NULL); | 336 | free_irq(IRQ_AC97, NULL); |
| 314 | pxa_set_cken(CKEN_AC97, 0); | 337 | #ifdef CONFIG_PXA27x |
| 338 | clk_put(ac97conf_clk); | ||
| 339 | ac97conf_clk = NULL; | ||
| 340 | #endif | ||
| 341 | clk_disable(ac97_clk); | ||
| 342 | clk_put(ac97_clk); | ||
| 343 | ac97_clk = NULL; | ||
| 315 | } | 344 | } |
| 316 | 345 | ||
| 317 | static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, | 346 | static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, |
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c index 692b90002489..425071030970 100644 --- a/sound/soc/pxa/pxa2xx-i2s.c +++ b/sound/soc/pxa/pxa2xx-i2s.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include <asm/hardware.h> | 26 | #include <asm/hardware.h> |
| 27 | #include <asm/arch/pxa-regs.h> | 27 | #include <asm/arch/pxa-regs.h> |
| 28 | #include <asm/arch/pxa2xx-gpio.h> | ||
| 28 | #include <asm/arch/audio.h> | 29 | #include <asm/arch/audio.h> |
| 29 | 30 | ||
| 30 | #include "pxa2xx-pcm.h" | 31 | #include "pxa2xx-pcm.h" |