diff options
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0e8af6309160..a706d429a741 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h | |||
| @@ -277,39 +277,6 @@ | |||
| 277 | #define ST0_MX 0x01000000 | 277 | #define ST0_MX 0x01000000 |
| 278 | 278 | ||
| 279 | /* | 279 | /* |
| 280 | * Bitfields in the TX39 family CP0 Configuration Register 3 | ||
| 281 | */ | ||
| 282 | #define TX39_CONF_ICS_SHIFT 19 | ||
| 283 | #define TX39_CONF_ICS_MASK 0x00380000 | ||
| 284 | #define TX39_CONF_ICS_1KB 0x00000000 | ||
| 285 | #define TX39_CONF_ICS_2KB 0x00080000 | ||
| 286 | #define TX39_CONF_ICS_4KB 0x00100000 | ||
| 287 | #define TX39_CONF_ICS_8KB 0x00180000 | ||
| 288 | #define TX39_CONF_ICS_16KB 0x00200000 | ||
| 289 | |||
| 290 | #define TX39_CONF_DCS_SHIFT 16 | ||
| 291 | #define TX39_CONF_DCS_MASK 0x00070000 | ||
| 292 | #define TX39_CONF_DCS_1KB 0x00000000 | ||
| 293 | #define TX39_CONF_DCS_2KB 0x00010000 | ||
| 294 | #define TX39_CONF_DCS_4KB 0x00020000 | ||
| 295 | #define TX39_CONF_DCS_8KB 0x00030000 | ||
| 296 | #define TX39_CONF_DCS_16KB 0x00040000 | ||
| 297 | |||
| 298 | #define TX39_CONF_CWFON 0x00004000 | ||
| 299 | #define TX39_CONF_WBON 0x00002000 | ||
| 300 | #define TX39_CONF_RF_SHIFT 10 | ||
| 301 | #define TX39_CONF_RF_MASK 0x00000c00 | ||
| 302 | #define TX39_CONF_DOZE 0x00000200 | ||
| 303 | #define TX39_CONF_HALT 0x00000100 | ||
| 304 | #define TX39_CONF_LOCK 0x00000080 | ||
| 305 | #define TX39_CONF_ICE 0x00000020 | ||
| 306 | #define TX39_CONF_DCE 0x00000010 | ||
| 307 | #define TX39_CONF_IRSIZE_SHIFT 2 | ||
| 308 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | ||
| 309 | #define TX39_CONF_DRSIZE_SHIFT 0 | ||
| 310 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | ||
| 311 | |||
| 312 | /* | ||
| 313 | * Status register bits available in all MIPS CPUs. | 280 | * Status register bits available in all MIPS CPUs. |
| 314 | */ | 281 | */ |
| 315 | #define ST0_IM 0x0000ff00 | 282 | #define ST0_IM 0x0000ff00 |
| @@ -685,6 +652,39 @@ | |||
| 685 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 | 652 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 |
| 686 | #define MIPS_CDMMBASE_ADDR_START 15 | 653 | #define MIPS_CDMMBASE_ADDR_START 15 |
| 687 | 654 | ||
| 655 | /* | ||
| 656 | * Bitfields in the TX39 family CP0 Configuration Register 3 | ||
| 657 | */ | ||
| 658 | #define TX39_CONF_ICS_SHIFT 19 | ||
| 659 | #define TX39_CONF_ICS_MASK 0x00380000 | ||
| 660 | #define TX39_CONF_ICS_1KB 0x00000000 | ||
| 661 | #define TX39_CONF_ICS_2KB 0x00080000 | ||
| 662 | #define TX39_CONF_ICS_4KB 0x00100000 | ||
| 663 | #define TX39_CONF_ICS_8KB 0x00180000 | ||
| 664 | #define TX39_CONF_ICS_16KB 0x00200000 | ||
| 665 | |||
| 666 | #define TX39_CONF_DCS_SHIFT 16 | ||
| 667 | #define TX39_CONF_DCS_MASK 0x00070000 | ||
| 668 | #define TX39_CONF_DCS_1KB 0x00000000 | ||
| 669 | #define TX39_CONF_DCS_2KB 0x00010000 | ||
| 670 | #define TX39_CONF_DCS_4KB 0x00020000 | ||
| 671 | #define TX39_CONF_DCS_8KB 0x00030000 | ||
| 672 | #define TX39_CONF_DCS_16KB 0x00040000 | ||
| 673 | |||
| 674 | #define TX39_CONF_CWFON 0x00004000 | ||
| 675 | #define TX39_CONF_WBON 0x00002000 | ||
| 676 | #define TX39_CONF_RF_SHIFT 10 | ||
| 677 | #define TX39_CONF_RF_MASK 0x00000c00 | ||
| 678 | #define TX39_CONF_DOZE 0x00000200 | ||
| 679 | #define TX39_CONF_HALT 0x00000100 | ||
| 680 | #define TX39_CONF_LOCK 0x00000080 | ||
| 681 | #define TX39_CONF_ICE 0x00000020 | ||
| 682 | #define TX39_CONF_DCE 0x00000010 | ||
| 683 | #define TX39_CONF_IRSIZE_SHIFT 2 | ||
| 684 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | ||
| 685 | #define TX39_CONF_DRSIZE_SHIFT 0 | ||
| 686 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | ||
| 687 | |||
| 688 | 688 | ||
| 689 | /* | 689 | /* |
| 690 | * Coprocessor 1 (FPU) register names | 690 | * Coprocessor 1 (FPU) register names |