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-rw-r--r--drivers/spi/spi-rockchip.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index f96ea8a38d64..3044c6c27332 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -145,6 +145,9 @@
145#define RXBUSY (1 << 0) 145#define RXBUSY (1 << 0)
146#define TXBUSY (1 << 1) 146#define TXBUSY (1 << 1)
147 147
148/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
149#define MAX_SCLK_OUT 50000000
150
148enum rockchip_ssi_type { 151enum rockchip_ssi_type {
149 SSI_MOTO_SPI = 0, 152 SSI_MOTO_SPI = 0,
150 SSI_TI_SSP, 153 SSI_TI_SSP,
@@ -496,6 +499,15 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
496 dmacr |= RF_DMA_EN; 499 dmacr |= RF_DMA_EN;
497 } 500 }
498 501
502 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
503 rs->speed = MAX_SCLK_OUT;
504
505 /* the minimum divsor is 2 */
506 if (rs->max_freq < 2 * rs->speed) {
507 clk_set_rate(rs->spiclk, 2 * rs->speed);
508 rs->max_freq = clk_get_rate(rs->spiclk);
509 }
510
499 /* div doesn't support odd number */ 511 /* div doesn't support odd number */
500 div = max_t(u32, rs->max_freq / rs->speed, 1); 512 div = max_t(u32, rs->max_freq / rs->speed, 1);
501 div = (div + 1) & 0xfffe; 513 div = (div + 1) & 0xfffe;