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-rw-r--r--drivers/tty/serial/Kconfig13
-rw-r--r--drivers/tty/serial/Makefile2
-rw-r--r--drivers/tty/serial/max3107.c1215
-rw-r--r--drivers/tty/serial/max3107.h441
-rw-r--r--drivers/tty/serial/max310x.c1259
-rw-r--r--include/linux/platform_data/max310x.h67
-rw-r--r--include/linux/serial_core.h4
7 files changed, 1339 insertions, 1662 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 00207865ec55..7b3d9de938e0 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -257,12 +257,19 @@ config SERIAL_MAX3100
257 help 257 help
258 MAX3100 chip support 258 MAX3100 chip support
259 259
260config SERIAL_MAX3107 260config SERIAL_MAX310X
261 tristate "MAX3107 support" 261 bool "MAX310X support"
262 depends on SPI 262 depends on SPI
263 select SERIAL_CORE 263 select SERIAL_CORE
264 select REGMAP_SPI if SPI
265 default n
264 help 266 help
265 MAX3107 chip support 267 This selects support for an advanced UART from Maxim (Dallas).
268 Supported ICs are MAX3107, MAX3108.
269 Each IC contains 128 words each of receive and transmit FIFO
270 that can be controlled through I2C or high-speed SPI.
271
272 Say Y here if you want to support this ICs.
266 273
267config SERIAL_DZ 274config SERIAL_DZ
268 bool "DECstation DZ serial driver" 275 bool "DECstation DZ serial driver"
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 8a5df3804e5f..2af9e5279dab 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o
28obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o 28obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
29obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o 29obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
30obj-$(CONFIG_SERIAL_MAX3100) += max3100.o 30obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
31obj-$(CONFIG_SERIAL_MAX3107) += max3107.o 31obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
32obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 32obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
33obj-$(CONFIG_SERIAL_MUX) += mux.o 33obj-$(CONFIG_SERIAL_MUX) += mux.o
34obj-$(CONFIG_SERIAL_68328) += 68328serial.o 34obj-$(CONFIG_SERIAL_68328) += 68328serial.o
diff --git a/drivers/tty/serial/max3107.c b/drivers/tty/serial/max3107.c
deleted file mode 100644
index 17c7ba805d98..000000000000
--- a/drivers/tty/serial/max3107.c
+++ /dev/null
@@ -1,1215 +0,0 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/gpio.h>
37#include <linux/spi/spi.h>
38#include <linux/freezer.h>
39#include <linux/module.h>
40#include "max3107.h"
41
42static const struct baud_table brg26_ext[] = {
43 { 300, MAX3107_BRG26_B300 },
44 { 600, MAX3107_BRG26_B600 },
45 { 1200, MAX3107_BRG26_B1200 },
46 { 2400, MAX3107_BRG26_B2400 },
47 { 4800, MAX3107_BRG26_B4800 },
48 { 9600, MAX3107_BRG26_B9600 },
49 { 19200, MAX3107_BRG26_B19200 },
50 { 57600, MAX3107_BRG26_B57600 },
51 { 115200, MAX3107_BRG26_B115200 },
52 { 230400, MAX3107_BRG26_B230400 },
53 { 460800, MAX3107_BRG26_B460800 },
54 { 921600, MAX3107_BRG26_B921600 },
55 { 0, 0 }
56};
57
58static const struct baud_table brg13_int[] = {
59 { 300, MAX3107_BRG13_IB300 },
60 { 600, MAX3107_BRG13_IB600 },
61 { 1200, MAX3107_BRG13_IB1200 },
62 { 2400, MAX3107_BRG13_IB2400 },
63 { 4800, MAX3107_BRG13_IB4800 },
64 { 9600, MAX3107_BRG13_IB9600 },
65 { 19200, MAX3107_BRG13_IB19200 },
66 { 57600, MAX3107_BRG13_IB57600 },
67 { 115200, MAX3107_BRG13_IB115200 },
68 { 230400, MAX3107_BRG13_IB230400 },
69 { 460800, MAX3107_BRG13_IB460800 },
70 { 921600, MAX3107_BRG13_IB921600 },
71 { 0, 0 }
72};
73
74static u32 get_new_brg(int baud, struct max3107_port *s)
75{
76 int i;
77 const struct baud_table *baud_tbl = s->baud_tbl;
78
79 for (i = 0; i < 13; i++) {
80 if (baud == baud_tbl[i].baud)
81 return baud_tbl[i].new_brg;
82 }
83
84 return 0;
85}
86
87/* Perform SPI transfer for write/read of device register(s) */
88int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
89{
90 struct spi_message spi_msg;
91 struct spi_transfer spi_xfer;
92
93 /* Initialize SPI ,message */
94 spi_message_init(&spi_msg);
95
96 /* Initialize SPI transfer */
97 memset(&spi_xfer, 0, sizeof spi_xfer);
98 spi_xfer.len = len;
99 spi_xfer.tx_buf = tx;
100 spi_xfer.rx_buf = rx;
101 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
102
103 /* Add SPI transfer to SPI message */
104 spi_message_add_tail(&spi_xfer, &spi_msg);
105
106#ifdef DBG_TRACE_SPI_DATA
107 {
108 int i;
109 pr_info("tx len %d:\n", spi_xfer.len);
110 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
111 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
112 pr_info("\n");
113 }
114#endif
115
116 /* Perform synchronous SPI transfer */
117 if (spi_sync(s->spi, &spi_msg)) {
118 dev_err(&s->spi->dev, "spi_sync failure\n");
119 return -EIO;
120 }
121
122#ifdef DBG_TRACE_SPI_DATA
123 if (spi_xfer.rx_buf) {
124 int i;
125 pr_info("rx len %d:\n", spi_xfer.len);
126 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
127 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
128 pr_info("\n");
129 }
130#endif
131 return 0;
132}
133EXPORT_SYMBOL_GPL(max3107_rw);
134
135/* Puts received data to circular buffer */
136static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
137 int len)
138{
139 struct uart_port *port = &s->port;
140 struct tty_struct *tty;
141
142 if (!port->state)
143 return;
144
145 tty = port->state->port.tty;
146 if (!tty)
147 return;
148
149 /* Insert received data */
150 tty_insert_flip_string(tty, data, len);
151 /* Update RX counter */
152 port->icount.rx += len;
153}
154
155/* Handle data receiving */
156static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
157{
158 int i;
159 int j;
160 int len; /* SPI transfer buffer length */
161 u16 *buf;
162 u8 *valid_str;
163
164 if (!s->rx_enabled)
165 /* RX is disabled */
166 return;
167
168 if (rxlvl == 0) {
169 /* RX fifo is empty */
170 return;
171 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
172 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
173 /* Ensure sanity of RX level */
174 rxlvl = MAX3107_RX_FIFO_SIZE;
175 }
176 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
177 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
178 return;
179 }
180 buf = s->rxbuf;
181 valid_str = s->rxstr;
182 while (rxlvl) {
183 pr_debug("rxlvl %d\n", rxlvl);
184 /* Clear buffer */
185 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
186 len = 0;
187 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
188 /* First disable RX FIFO interrupt */
189 pr_debug("Disabling RX INT\n");
190 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
191 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
192 buf[0] |= s->irqen_reg;
193 len++;
194 }
195 /* Just increase the length by amount of words in FIFO since
196 * buffer was zeroed and SPI transfer of 0x0000 means reading
197 * from RX FIFO
198 */
199 len += rxlvl;
200 /* Append RX level query */
201 buf[len] = MAX3107_RXFIFOLVL_REG;
202 len++;
203
204 /* Perform the SPI transfer */
205 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
206 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
207 return;
208 }
209
210 /* Skip RX FIFO interrupt disabling word if it was added */
211 j = ((len - 1) - rxlvl);
212 /* Read received words */
213 for (i = 0; i < rxlvl; i++, j++)
214 valid_str[i] = (u8)buf[j];
215 put_data_to_circ_buf(s, valid_str, rxlvl);
216 /* Get new RX level */
217 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
218 }
219
220 if (s->rx_enabled) {
221 /* RX still enabled, re-enable RX FIFO interrupt */
222 pr_debug("Enabling RX INT\n");
223 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
224 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
225 buf[0] |= s->irqen_reg;
226 if (max3107_rw(s, (u8 *)buf, NULL, 2))
227 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
228 }
229
230 /* Push the received data to receivers */
231 if (s->port.state->port.tty)
232 tty_flip_buffer_push(s->port.state->port.tty);
233}
234
235
236/* Handle data sending */
237static void max3107_handletx(struct max3107_port *s)
238{
239 struct circ_buf *xmit = &s->port.state->xmit;
240 int i;
241 unsigned long flags;
242 int len; /* SPI transfer buffer length */
243 u16 *buf;
244
245 if (!s->tx_fifo_empty)
246 /* Don't send more data before previous data is sent */
247 return;
248
249 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
250 /* No data to send or TX is stopped */
251 return;
252
253 if (!s->txbuf) {
254 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
255 return;
256 }
257 buf = s->txbuf;
258 /* Get length of data pending in circular buffer */
259 len = uart_circ_chars_pending(xmit);
260 if (len) {
261 /* Limit to size of TX FIFO */
262 if (len > MAX3107_TX_FIFO_SIZE)
263 len = MAX3107_TX_FIFO_SIZE;
264
265 pr_debug("txlen %d\n", len);
266
267 /* Update TX counter */
268 s->port.icount.tx += len;
269
270 /* TX FIFO will no longer be empty */
271 s->tx_fifo_empty = 0;
272
273 i = 0;
274 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
275 /* First disable TX empty interrupt */
276 pr_debug("Disabling TE INT\n");
277 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
278 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
279 buf[i] |= s->irqen_reg;
280 i++;
281 len++;
282 }
283 /* Add data to send */
284 spin_lock_irqsave(&s->port.lock, flags);
285 for ( ; i < len ; i++) {
286 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
287 buf[i] |= ((u16)xmit->buf[xmit->tail] &
288 MAX3107_SPI_TX_DATA_MASK);
289 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
290 }
291 spin_unlock_irqrestore(&s->port.lock, flags);
292 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
293 /* Enable TX empty interrupt */
294 pr_debug("Enabling TE INT\n");
295 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
296 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
297 buf[i] |= s->irqen_reg;
298 i++;
299 len++;
300 }
301 if (!s->tx_enabled) {
302 /* Enable TX */
303 pr_debug("Enable TX\n");
304 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
305 spin_lock_irqsave(&s->data_lock, flags);
306 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
307 buf[i] |= s->mode1_reg;
308 spin_unlock_irqrestore(&s->data_lock, flags);
309 s->tx_enabled = 1;
310 i++;
311 len++;
312 }
313
314 /* Perform the SPI transfer */
315 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
316 dev_err(&s->spi->dev,
317 "SPI transfer TX handling failed\n");
318 return;
319 }
320 }
321
322 /* Indicate wake up if circular buffer is getting low on data */
323 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
324 uart_write_wakeup(&s->port);
325
326}
327
328/* Handle interrupts
329 * Also reads and returns current RX FIFO level
330 */
331static u16 handle_interrupt(struct max3107_port *s)
332{
333 u16 buf[4]; /* Buffer for SPI transfers */
334 u8 irq_status;
335 u16 rx_level;
336 unsigned long flags;
337
338 /* Read IRQ status register */
339 buf[0] = MAX3107_IRQSTS_REG;
340 /* Read status IRQ status register */
341 buf[1] = MAX3107_STS_IRQSTS_REG;
342 /* Read LSR IRQ status register */
343 buf[2] = MAX3107_LSR_IRQSTS_REG;
344 /* Query RX level */
345 buf[3] = MAX3107_RXFIFOLVL_REG;
346
347 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
348 dev_err(&s->spi->dev,
349 "SPI transfer for INTR handling failed\n");
350 return 0;
351 }
352
353 irq_status = (u8)buf[0];
354 pr_debug("IRQSTS %x\n", irq_status);
355 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
356
357 if (irq_status & MAX3107_IRQ_LSR_BIT) {
358 /* LSR interrupt */
359 if (buf[2] & MAX3107_LSR_RXTO_BIT)
360 /* RX timeout interrupt,
361 * handled by normal RX handling
362 */
363 pr_debug("RX TO INT\n");
364 }
365
366 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
367 /* Tx empty interrupt,
368 * disable TX and set tx_fifo_empty flag
369 */
370 pr_debug("TE INT, disabling TX\n");
371 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
372 spin_lock_irqsave(&s->data_lock, flags);
373 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
374 buf[0] |= s->mode1_reg;
375 spin_unlock_irqrestore(&s->data_lock, flags);
376 if (max3107_rw(s, (u8 *)buf, NULL, 2))
377 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
378 s->tx_enabled = 0;
379 s->tx_fifo_empty = 1;
380 }
381
382 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
383 /* RX FIFO interrupt,
384 * handled by normal RX handling
385 */
386 pr_debug("RFIFO INT\n");
387
388 /* Return RX level */
389 return rx_level;
390}
391
392/* Trigger work thread*/
393static void max3107_dowork(struct max3107_port *s)
394{
395 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
396 queue_work(s->workqueue, &s->work);
397 else
398 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
399}
400
401/* Work thread */
402static void max3107_work(struct work_struct *w)
403{
404 struct max3107_port *s = container_of(w, struct max3107_port, work);
405 u16 rxlvl = 0;
406 int len; /* SPI transfer buffer length */
407 u16 buf[5]; /* Buffer for SPI transfers */
408 unsigned long flags;
409
410 /* Start by reading current RX FIFO level */
411 buf[0] = MAX3107_RXFIFOLVL_REG;
412 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
413 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
414 rxlvl = 0;
415 } else {
416 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
417 }
418
419 do {
420 pr_debug("rxlvl %d\n", rxlvl);
421
422 /* Handle RX */
423 max3107_handlerx(s, rxlvl);
424 rxlvl = 0;
425
426 if (s->handle_irq) {
427 /* Handle pending interrupts
428 * We also get new RX FIFO level since new data may
429 * have been received while pushing received data to
430 * receivers
431 */
432 s->handle_irq = 0;
433 rxlvl = handle_interrupt(s);
434 }
435
436 /* Handle TX */
437 max3107_handletx(s);
438
439 /* Handle configuration changes */
440 len = 0;
441 spin_lock_irqsave(&s->data_lock, flags);
442 if (s->mode1_commit) {
443 pr_debug("mode1_commit\n");
444 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
445 buf[len++] |= s->mode1_reg;
446 s->mode1_commit = 0;
447 }
448 if (s->lcr_commit) {
449 pr_debug("lcr_commit\n");
450 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
451 buf[len++] |= s->lcr_reg;
452 s->lcr_commit = 0;
453 }
454 if (s->brg_commit) {
455 pr_debug("brg_commit\n");
456 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
457 buf[len++] |= ((s->brg_cfg >> 16) &
458 MAX3107_SPI_TX_DATA_MASK);
459 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
460 buf[len++] |= ((s->brg_cfg >> 8) &
461 MAX3107_SPI_TX_DATA_MASK);
462 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
463 buf[len++] |= ((s->brg_cfg) & 0xff);
464 s->brg_commit = 0;
465 }
466 spin_unlock_irqrestore(&s->data_lock, flags);
467
468 if (len > 0) {
469 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
470 dev_err(&s->spi->dev,
471 "SPI transfer config failed\n");
472 }
473
474 /* Reloop if interrupt handling indicated data in RX FIFO */
475 } while (rxlvl);
476
477}
478
479/* Set sleep mode */
480static void max3107_set_sleep(struct max3107_port *s, int mode)
481{
482 u16 buf[1]; /* Buffer for SPI transfer */
483 unsigned long flags;
484 pr_debug("enter, mode %d\n", mode);
485
486 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
487 spin_lock_irqsave(&s->data_lock, flags);
488 switch (mode) {
489 case MAX3107_DISABLE_FORCED_SLEEP:
490 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
491 break;
492 case MAX3107_ENABLE_FORCED_SLEEP:
493 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
494 break;
495 case MAX3107_DISABLE_AUTOSLEEP:
496 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
497 break;
498 case MAX3107_ENABLE_AUTOSLEEP:
499 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
500 break;
501 default:
502 spin_unlock_irqrestore(&s->data_lock, flags);
503 dev_warn(&s->spi->dev, "invalid sleep mode\n");
504 return;
505 }
506 buf[0] |= s->mode1_reg;
507 spin_unlock_irqrestore(&s->data_lock, flags);
508
509 if (max3107_rw(s, (u8 *)buf, NULL, 2))
510 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
511
512 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
513 mode == MAX3107_DISABLE_FORCED_SLEEP)
514 msleep(MAX3107_WAKEUP_DELAY);
515}
516
517/* Perform full register initialization */
518static void max3107_register_init(struct max3107_port *s)
519{
520 u16 buf[11]; /* Buffer for SPI transfers */
521
522 /* 1. Configure baud rate, 9600 as default */
523 s->baud = 9600;
524 /* the below is default*/
525 if (s->ext_clk) {
526 s->brg_cfg = MAX3107_BRG26_B9600;
527 s->baud_tbl = (struct baud_table *)brg26_ext;
528 } else {
529 s->brg_cfg = MAX3107_BRG13_IB9600;
530 s->baud_tbl = (struct baud_table *)brg13_int;
531 }
532
533 if (s->pdata->init)
534 s->pdata->init(s);
535
536 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
537 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
538 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
539 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
540 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
541 | ((s->brg_cfg) & 0xff);
542
543 /* 2. Configure LCR register, 8N1 mode by default */
544 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
545 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
546 | s->lcr_reg;
547
548 /* 3. Configure MODE 1 register */
549 s->mode1_reg = 0;
550 /* Enable IRQ pin */
551 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
552 /* Disable TX */
553 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
554 s->tx_enabled = 0;
555 /* RX is enabled */
556 s->rx_enabled = 1;
557 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
558 | s->mode1_reg;
559
560 /* 4. Configure MODE 2 register */
561 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
562 if (s->loopback) {
563 /* Enable loopback */
564 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
565 }
566 /* Reset FIFOs */
567 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
568 s->tx_fifo_empty = 1;
569
570 /* 5. Configure FIFO trigger level register */
571 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
572 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
573 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
574
575 /* 6. Configure flow control levels */
576 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
577 /* Flow control halt level 96, resume level 48 */
578 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
579
580 /* 7. Configure flow control */
581 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
582 /* Enable auto CTS and auto RTS flow control */
583 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
584
585 /* 8. Configure RX timeout register */
586 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
587 /* Timeout after 48 character intervals */
588 buf[9] |= 0x0030;
589
590 /* 9. Configure LSR interrupt enable register */
591 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
592 /* Enable RX timeout interrupt */
593 buf[10] |= MAX3107_LSR_RXTO_BIT;
594
595 /* Perform SPI transfer */
596 if (max3107_rw(s, (u8 *)buf, NULL, 22))
597 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
598
599 /* 10. Clear IRQ status register by reading it */
600 buf[0] = MAX3107_IRQSTS_REG;
601
602 /* 11. Configure interrupt enable register */
603 /* Enable LSR interrupt */
604 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
605 /* Enable RX FIFO interrupt */
606 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
607 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
608 | s->irqen_reg;
609
610 /* 12. Clear FIFO reset that was set in step 6 */
611 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
612 if (s->loopback) {
613 /* Keep loopback enabled */
614 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
615 }
616
617 /* Perform SPI transfer */
618 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
619 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
620
621}
622
623/* IRQ handler */
624static irqreturn_t max3107_irq(int irqno, void *dev_id)
625{
626 struct max3107_port *s = dev_id;
627
628 if (irqno != s->spi->irq) {
629 /* Unexpected IRQ */
630 return IRQ_NONE;
631 }
632
633 /* Indicate irq */
634 s->handle_irq = 1;
635
636 /* Trigger work thread */
637 max3107_dowork(s);
638
639 return IRQ_HANDLED;
640}
641
642/* HW suspension function
643 *
644 * Currently autosleep is used to decrease current consumption, alternative
645 * approach would be to set the chip to reset mode if UART is not being
646 * used but that would mess the GPIOs
647 *
648 */
649void max3107_hw_susp(struct max3107_port *s, int suspend)
650{
651 pr_debug("enter, suspend %d\n", suspend);
652
653 if (suspend) {
654 /* Suspend requested,
655 * enable autosleep to decrease current consumption
656 */
657 s->suspended = 1;
658 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
659 } else {
660 /* Resume requested,
661 * disable autosleep
662 */
663 s->suspended = 0;
664 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
665 }
666}
667EXPORT_SYMBOL_GPL(max3107_hw_susp);
668
669/* Modem status IRQ enabling */
670static void max3107_enable_ms(struct uart_port *port)
671{
672 /* Modem status not supported */
673}
674
675/* Data send function */
676static void max3107_start_tx(struct uart_port *port)
677{
678 struct max3107_port *s = container_of(port, struct max3107_port, port);
679
680 /* Trigger work thread for sending data */
681 max3107_dowork(s);
682}
683
684/* Function for checking that there is no pending transfers */
685static unsigned int max3107_tx_empty(struct uart_port *port)
686{
687 struct max3107_port *s = container_of(port, struct max3107_port, port);
688
689 pr_debug("returning %d\n",
690 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
691 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
692}
693
694/* Function for stopping RX */
695static void max3107_stop_rx(struct uart_port *port)
696{
697 struct max3107_port *s = container_of(port, struct max3107_port, port);
698 unsigned long flags;
699
700 /* Set RX disabled in MODE 1 register */
701 spin_lock_irqsave(&s->data_lock, flags);
702 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
703 s->mode1_commit = 1;
704 spin_unlock_irqrestore(&s->data_lock, flags);
705 /* Set RX disabled */
706 s->rx_enabled = 0;
707 /* Trigger work thread for doing the actual configuration change */
708 max3107_dowork(s);
709}
710
711/* Function for returning control pin states */
712static unsigned int max3107_get_mctrl(struct uart_port *port)
713{
714 /* DCD and DSR are not wired and CTS/RTS is handled automatically
715 * so just indicate DSR and CAR asserted
716 */
717 return TIOCM_DSR | TIOCM_CAR;
718}
719
720/* Function for setting control pin states */
721static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
722{
723 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
724 * so do nothing
725 */
726}
727
728/* Function for configuring UART parameters */
729static void max3107_set_termios(struct uart_port *port,
730 struct ktermios *termios,
731 struct ktermios *old)
732{
733 struct max3107_port *s = container_of(port, struct max3107_port, port);
734 struct tty_struct *tty;
735 int baud;
736 u16 new_lcr = 0;
737 u32 new_brg = 0;
738 unsigned long flags;
739
740 if (!port->state)
741 return;
742
743 tty = port->state->port.tty;
744 if (!tty)
745 return;
746
747 /* Get new LCR register values */
748 /* Word size */
749 if ((termios->c_cflag & CSIZE) == CS7)
750 new_lcr |= MAX3107_LCR_WORD_LEN_7;
751 else
752 new_lcr |= MAX3107_LCR_WORD_LEN_8;
753
754 /* Parity */
755 if (termios->c_cflag & PARENB) {
756 new_lcr |= MAX3107_LCR_PARITY_BIT;
757 if (!(termios->c_cflag & PARODD))
758 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
759 }
760
761 /* Stop bits */
762 if (termios->c_cflag & CSTOPB) {
763 /* 2 stop bits */
764 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
765 }
766
767 /* Mask termios capabilities we don't support */
768 termios->c_cflag &= ~CMSPAR;
769
770 /* Set status ignore mask */
771 s->port.ignore_status_mask = 0;
772 if (termios->c_iflag & IGNPAR)
773 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
774
775 /* Set low latency to immediately handle pushed data */
776 s->port.state->port.tty->low_latency = 1;
777
778 /* Get new baud rate generator configuration */
779 baud = tty_get_baud_rate(tty);
780
781 spin_lock_irqsave(&s->data_lock, flags);
782 new_brg = get_new_brg(baud, s);
783 /* if can't find the corrent config, use previous */
784 if (!new_brg) {
785 baud = s->baud;
786 new_brg = s->brg_cfg;
787 }
788 spin_unlock_irqrestore(&s->data_lock, flags);
789 tty_termios_encode_baud_rate(termios, baud, baud);
790 s->baud = baud;
791
792 /* Update timeout according to new baud rate */
793 uart_update_timeout(port, termios->c_cflag, baud);
794
795 spin_lock_irqsave(&s->data_lock, flags);
796 if (s->lcr_reg != new_lcr) {
797 s->lcr_reg = new_lcr;
798 s->lcr_commit = 1;
799 }
800 if (s->brg_cfg != new_brg) {
801 s->brg_cfg = new_brg;
802 s->brg_commit = 1;
803 }
804 spin_unlock_irqrestore(&s->data_lock, flags);
805
806 /* Trigger work thread for doing the actual configuration change */
807 max3107_dowork(s);
808}
809
810/* Port shutdown function */
811static void max3107_shutdown(struct uart_port *port)
812{
813 struct max3107_port *s = container_of(port, struct max3107_port, port);
814
815 if (s->suspended && s->pdata->hw_suspend)
816 s->pdata->hw_suspend(s, 0);
817
818 /* Free the interrupt */
819 free_irq(s->spi->irq, s);
820
821 if (s->workqueue) {
822 /* Flush and destroy work queue */
823 flush_workqueue(s->workqueue);
824 destroy_workqueue(s->workqueue);
825 s->workqueue = NULL;
826 }
827
828 /* Suspend HW */
829 if (s->pdata->hw_suspend)
830 s->pdata->hw_suspend(s, 1);
831}
832
833/* Port startup function */
834static int max3107_startup(struct uart_port *port)
835{
836 struct max3107_port *s = container_of(port, struct max3107_port, port);
837
838 /* Initialize work queue */
839 s->workqueue = create_freezable_workqueue("max3107");
840 if (!s->workqueue) {
841 dev_err(&s->spi->dev, "Workqueue creation failed\n");
842 return -EBUSY;
843 }
844 INIT_WORK(&s->work, max3107_work);
845
846 /* Setup IRQ */
847 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
848 "max3107", s)) {
849 dev_err(&s->spi->dev, "IRQ reguest failed\n");
850 destroy_workqueue(s->workqueue);
851 s->workqueue = NULL;
852 return -EBUSY;
853 }
854
855 /* Resume HW */
856 if (s->pdata->hw_suspend)
857 s->pdata->hw_suspend(s, 0);
858
859 /* Init registers */
860 max3107_register_init(s);
861
862 return 0;
863}
864
865/* Port type function */
866static const char *max3107_type(struct uart_port *port)
867{
868 struct max3107_port *s = container_of(port, struct max3107_port, port);
869 return s->spi->modalias;
870}
871
872/* Port release function */
873static void max3107_release_port(struct uart_port *port)
874{
875 /* Do nothing */
876}
877
878/* Port request function */
879static int max3107_request_port(struct uart_port *port)
880{
881 /* Do nothing */
882 return 0;
883}
884
885/* Port config function */
886static void max3107_config_port(struct uart_port *port, int flags)
887{
888 struct max3107_port *s = container_of(port, struct max3107_port, port);
889 s->port.type = PORT_MAX3107;
890}
891
892/* Port verify function */
893static int max3107_verify_port(struct uart_port *port,
894 struct serial_struct *ser)
895{
896 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
897 return 0;
898
899 return -EINVAL;
900}
901
902/* Port stop TX function */
903static void max3107_stop_tx(struct uart_port *port)
904{
905 /* Do nothing */
906}
907
908/* Port break control function */
909static void max3107_break_ctl(struct uart_port *port, int break_state)
910{
911 /* We don't support break control, do nothing */
912}
913
914
915/* Port functions */
916static struct uart_ops max3107_ops = {
917 .tx_empty = max3107_tx_empty,
918 .set_mctrl = max3107_set_mctrl,
919 .get_mctrl = max3107_get_mctrl,
920 .stop_tx = max3107_stop_tx,
921 .start_tx = max3107_start_tx,
922 .stop_rx = max3107_stop_rx,
923 .enable_ms = max3107_enable_ms,
924 .break_ctl = max3107_break_ctl,
925 .startup = max3107_startup,
926 .shutdown = max3107_shutdown,
927 .set_termios = max3107_set_termios,
928 .type = max3107_type,
929 .release_port = max3107_release_port,
930 .request_port = max3107_request_port,
931 .config_port = max3107_config_port,
932 .verify_port = max3107_verify_port,
933};
934
935/* UART driver data */
936static struct uart_driver max3107_uart_driver = {
937 .owner = THIS_MODULE,
938 .driver_name = "ttyMAX",
939 .dev_name = "ttyMAX",
940 .nr = 1,
941};
942
943static int driver_registered = 0;
944
945
946
947/* 'Generic' platform data */
948static struct max3107_plat generic_plat_data = {
949 .loopback = 0,
950 .ext_clk = 1,
951 .hw_suspend = max3107_hw_susp,
952 .polled_mode = 0,
953 .poll_time = 0,
954};
955
956
957/*******************************************************************/
958
959/**
960 * max3107_probe - SPI bus probe entry point
961 * @spi: the spi device
962 *
963 * SPI wants us to probe this device and if appropriate claim it.
964 * Perform any platform specific requirements and then initialise
965 * the device.
966 */
967
968int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
969{
970 struct max3107_port *s;
971 u16 buf[2]; /* Buffer for SPI transfers */
972 int retval;
973
974 pr_info("enter max3107 probe\n");
975
976 /* Allocate port structure */
977 s = kzalloc(sizeof(*s), GFP_KERNEL);
978 if (!s) {
979 pr_err("Allocating port structure failed\n");
980 return -ENOMEM;
981 }
982
983 s->pdata = pdata;
984
985 /* SPI Rx buffer
986 * +2 for RX FIFO interrupt
987 * disabling and RX level query
988 */
989 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
990 if (!s->rxbuf) {
991 pr_err("Allocating RX buffer failed\n");
992 retval = -ENOMEM;
993 goto err_free4;
994 }
995 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
996 if (!s->rxstr) {
997 pr_err("Allocating RX buffer failed\n");
998 retval = -ENOMEM;
999 goto err_free3;
1000 }
1001 /* SPI Tx buffer
1002 * SPI transfer buffer
1003 * +3 for TX FIFO empty
1004 * interrupt disabling and
1005 * enabling and TX enabling
1006 */
1007 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1008 if (!s->txbuf) {
1009 pr_err("Allocating TX buffer failed\n");
1010 retval = -ENOMEM;
1011 goto err_free2;
1012 }
1013 /* Initialize shared data lock */
1014 spin_lock_init(&s->data_lock);
1015
1016 /* SPI intializations */
1017 dev_set_drvdata(&spi->dev, s);
1018 spi->mode = SPI_MODE_0;
1019 spi->dev.platform_data = pdata;
1020 spi->bits_per_word = 16;
1021 s->ext_clk = pdata->ext_clk;
1022 s->loopback = pdata->loopback;
1023 spi_setup(spi);
1024 s->spi = spi;
1025
1026 /* Check REV ID to ensure we are talking to what we expect */
1027 buf[0] = MAX3107_REVID_REG;
1028 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1029 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1030 retval = -EIO;
1031 goto err_free1;
1032 }
1033 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1034 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1035 dev_err(&s->spi->dev, "REVID %x does not match\n",
1036 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1037 retval = -ENODEV;
1038 goto err_free1;
1039 }
1040
1041 /* Disable all interrupts */
1042 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1043 buf[0] |= 0x0000;
1044
1045 /* Configure clock source */
1046 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1047 if (s->ext_clk) {
1048 /* External clock */
1049 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1050 }
1051
1052 /* PLL bypass ON */
1053 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1054
1055 /* Perform SPI transfer */
1056 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1057 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1058 retval = -EIO;
1059 goto err_free1;
1060 }
1061
1062 /* Register UART driver */
1063 if (!driver_registered) {
1064 retval = uart_register_driver(&max3107_uart_driver);
1065 if (retval) {
1066 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1067 goto err_free1;
1068 }
1069 driver_registered = 1;
1070 }
1071
1072 /* Initialize UART port data */
1073 s->port.fifosize = 128;
1074 s->port.ops = &max3107_ops;
1075 s->port.line = 0;
1076 s->port.dev = &spi->dev;
1077 s->port.uartclk = 9600;
1078 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1079 s->port.irq = s->spi->irq;
1080 s->port.type = PORT_MAX3107;
1081
1082 /* Add UART port */
1083 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1084 if (retval < 0) {
1085 dev_err(&s->spi->dev, "Adding UART port failed\n");
1086 goto err_free1;
1087 }
1088
1089 if (pdata->configure) {
1090 retval = pdata->configure(s);
1091 if (retval < 0)
1092 goto err_free1;
1093 }
1094
1095 /* Go to suspend mode */
1096 if (pdata->hw_suspend)
1097 pdata->hw_suspend(s, 1);
1098
1099 return 0;
1100
1101err_free1:
1102 kfree(s->txbuf);
1103err_free2:
1104 kfree(s->rxstr);
1105err_free3:
1106 kfree(s->rxbuf);
1107err_free4:
1108 kfree(s);
1109 return retval;
1110}
1111EXPORT_SYMBOL_GPL(max3107_probe);
1112
1113/* Driver remove function */
1114int max3107_remove(struct spi_device *spi)
1115{
1116 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1117
1118 pr_info("enter max3107 remove\n");
1119
1120 /* Remove port */
1121 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1122 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1123
1124
1125 /* Free TxRx buffer */
1126 kfree(s->rxbuf);
1127 kfree(s->rxstr);
1128 kfree(s->txbuf);
1129
1130 /* Free port structure */
1131 kfree(s);
1132
1133 return 0;
1134}
1135EXPORT_SYMBOL_GPL(max3107_remove);
1136
1137/* Driver suspend function */
1138int max3107_suspend(struct spi_device *spi, pm_message_t state)
1139{
1140#ifdef CONFIG_PM
1141 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1142
1143 pr_debug("enter suspend\n");
1144
1145 /* Suspend UART port */
1146 uart_suspend_port(&max3107_uart_driver, &s->port);
1147
1148 /* Go to suspend mode */
1149 if (s->pdata->hw_suspend)
1150 s->pdata->hw_suspend(s, 1);
1151#endif /* CONFIG_PM */
1152 return 0;
1153}
1154EXPORT_SYMBOL_GPL(max3107_suspend);
1155
1156/* Driver resume function */
1157int max3107_resume(struct spi_device *spi)
1158{
1159#ifdef CONFIG_PM
1160 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1161
1162 pr_debug("enter resume\n");
1163
1164 /* Resume from suspend */
1165 if (s->pdata->hw_suspend)
1166 s->pdata->hw_suspend(s, 0);
1167
1168 /* Resume UART port */
1169 uart_resume_port(&max3107_uart_driver, &s->port);
1170#endif /* CONFIG_PM */
1171 return 0;
1172}
1173EXPORT_SYMBOL_GPL(max3107_resume);
1174
1175static int max3107_probe_generic(struct spi_device *spi)
1176{
1177 return max3107_probe(spi, &generic_plat_data);
1178}
1179
1180/* Spi driver data */
1181static struct spi_driver max3107_driver = {
1182 .driver = {
1183 .name = "max3107",
1184 .owner = THIS_MODULE,
1185 },
1186 .probe = max3107_probe_generic,
1187 .remove = __devexit_p(max3107_remove),
1188 .suspend = max3107_suspend,
1189 .resume = max3107_resume,
1190};
1191
1192/* Driver init function */
1193static int __init max3107_init(void)
1194{
1195 pr_info("enter max3107 init\n");
1196 return spi_register_driver(&max3107_driver);
1197}
1198
1199/* Driver exit function */
1200static void __exit max3107_exit(void)
1201{
1202 pr_info("enter max3107 exit\n");
1203 /* Unregister UART driver */
1204 if (driver_registered)
1205 uart_unregister_driver(&max3107_uart_driver);
1206 spi_unregister_driver(&max3107_driver);
1207}
1208
1209module_init(max3107_init);
1210module_exit(max3107_exit);
1211
1212MODULE_DESCRIPTION("MAX3107 driver");
1213MODULE_AUTHOR("Aavamobile");
1214MODULE_ALIAS("spi:max3107");
1215MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/max3107.h b/drivers/tty/serial/max3107.h
deleted file mode 100644
index 8415fc723b96..000000000000
--- a/drivers/tty/serial/max3107.h
+++ /dev/null
@@ -1,441 +0,0 @@
1/*
2 * max3107.h - spi uart protocol driver header for Maxim 3107
3 *
4 * Copyright (C) Aavamobile 2009
5 * Based on serial_max3100.h by Christian Pellegrin
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _MAX3107_H
14#define _MAX3107_H
15
16/* Serial error status definitions */
17#define MAX3107_PARITY_ERROR 1
18#define MAX3107_FRAME_ERROR 2
19#define MAX3107_OVERRUN_ERROR 4
20#define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \
21 MAX3107_FRAME_ERROR | \
22 MAX3107_OVERRUN_ERROR)
23
24/* GPIO definitions */
25#define MAX3107_GPIO_BASE 88
26#define MAX3107_GPIO_COUNT 4
27
28
29/* GPIO connected to chip's reset pin */
30#define MAX3107_RESET_GPIO 87
31
32
33/* Chip reset delay */
34#define MAX3107_RESET_DELAY 10
35
36/* Chip wakeup delay */
37#define MAX3107_WAKEUP_DELAY 50
38
39
40/* Sleep mode definitions */
41#define MAX3107_DISABLE_FORCED_SLEEP 0
42#define MAX3107_ENABLE_FORCED_SLEEP 1
43#define MAX3107_DISABLE_AUTOSLEEP 2
44#define MAX3107_ENABLE_AUTOSLEEP 3
45
46
47/* Definitions for register access with SPI transfers
48 *
49 * SPI transfer format:
50 *
51 * Master to slave bits xzzzzzzzyyyyyyyy
52 * Slave to master bits aaaaaaaabbbbbbbb
53 *
54 * where:
55 * x = 0 for reads, 1 for writes
56 * z = register address
57 * y = new register value if write, 0 if read
58 * a = unspecified
59 * b = register value if read, unspecified if write
60 */
61
62/* SPI speed */
63#define MAX3107_SPI_SPEED (3125000 * 2)
64
65/* Write bit */
66#define MAX3107_WRITE_BIT (1 << 15)
67
68/* SPI TX data mask */
69#define MAX3107_SPI_RX_DATA_MASK (0x00ff)
70
71/* SPI RX data mask */
72#define MAX3107_SPI_TX_DATA_MASK (0x00ff)
73
74/* Register access masks */
75#define MAX3107_RHR_REG (0x0000) /* RX FIFO */
76#define MAX3107_THR_REG (0x0000) /* TX FIFO */
77#define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */
78#define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */
79#define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */
80#define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */
81#define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */
82#define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */
83#define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */
84#define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */
85#define MAX3107_MODE1_REG (0x0900) /* MODE1 */
86#define MAX3107_MODE2_REG (0x0a00) /* MODE2 */
87#define MAX3107_LCR_REG (0x0b00) /* LCR */
88#define MAX3107_RXTO_REG (0x0c00) /* RX timeout */
89#define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */
90#define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */
91#define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */
92#define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */
93#define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */
94#define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */
95#define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */
96#define MAX3107_XON1_REG (0x1400) /* XON1 character */
97#define MAX3107_XON2_REG (0x1500) /* XON2 character */
98#define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */
99#define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */
100#define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */
101#define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */
102#define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */
103#define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */
104#define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */
105#define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */
106#define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */
107#define MAX3107_REVID_REG (0x1f00) /* Revision identification */
108
109/* IRQ register bits */
110#define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
111#define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
112#define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */
113#define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
114#define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
115#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
116#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
117#define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
118
119/* LSR register bits */
120#define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */
121#define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
122#define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
123#define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */
124#define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */
125#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
126#define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
127#define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */
128
129/* Special character register bits */
130#define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
131#define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
132#define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
133#define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
134#define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */
135#define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
136#define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
137#define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */
138
139/* Status register bits */
140#define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
141#define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
142#define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
143#define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
144#define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */
145#define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
146#define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
147#define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */
148
149/* MODE1 register bits */
150#define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
151#define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
152#define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
153#define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
154#define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
155#define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
156#define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
157#define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
158
159/* MODE2 register bits */
160#define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */
161#define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
162#define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
163#define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
164#define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
165#define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
166#define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
167#define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
168
169/* LCR register bits */
170#define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
171#define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
172 *
173 * Word length bits table:
174 * 00 -> 5 bit words
175 * 01 -> 6 bit words
176 * 10 -> 7 bit words
177 * 11 -> 8 bit words
178 */
179#define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
180 *
181 * STOP length bit table:
182 * 0 -> 1 stop bit
183 * 1 -> 1-1.5 stop bits if
184 * word length is 5,
185 * 2 stop bits otherwise
186 */
187#define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
188#define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
189#define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
190#define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
191#define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */
192#define MAX3107_LCR_WORD_LEN_5 (0x0000)
193#define MAX3107_LCR_WORD_LEN_6 (0x0001)
194#define MAX3107_LCR_WORD_LEN_7 (0x0002)
195#define MAX3107_LCR_WORD_LEN_8 (0x0003)
196
197
198/* IRDA register bits */
199#define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
200#define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
201#define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
202#define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
203#define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
204#define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
205#define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */
206#define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */
207
208/* Flow control trigger level register masks */
209#define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
210#define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
211#define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f)
212#define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4)
213
214/* FIFO interrupt trigger level register masks */
215#define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */
216#define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */
217#define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f)
218#define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4)
219
220/* Flow control register bits */
221#define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
222#define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
223#define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
224 * are used in conjunction with
225 * XOFF2 for definition of
226 * special character */
227#define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
228#define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
229#define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
230 *
231 * SWFLOW bits 1 & 0 table:
232 * 00 -> no transmitter flow
233 * control
234 * 01 -> receiver compares
235 * XON2 and XOFF2
236 * and controls
237 * transmitter
238 * 10 -> receiver compares
239 * XON1 and XOFF1
240 * and controls
241 * transmitter
242 * 11 -> receiver compares
243 * XON1, XON2, XOFF1 and
244 * XOFF2 and controls
245 * transmitter
246 */
247#define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
248#define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
249 *
250 * SWFLOW bits 3 & 2 table:
251 * 00 -> no received flow
252 * control
253 * 01 -> transmitter generates
254 * XON2 and XOFF2
255 * 10 -> transmitter generates
256 * XON1 and XOFF1
257 * 11 -> transmitter generates
258 * XON1, XON2, XOFF1 and
259 * XOFF2
260 */
261
262/* GPIO configuration register bits */
263#define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
264#define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
265#define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
266#define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
267#define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
268#define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
269#define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
270#define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
271
272/* GPIO DATA register bits */
273#define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
274#define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
275#define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
276#define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
277#define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
278#define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
279#define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
280#define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
281
282/* PLL configuration register masks */
283#define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */
284#define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */
285
286/* Baud rate generator configuration register masks and bits */
287#define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of
288 * Baud rate generator divisor
289 */
290#define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
291#define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
292#define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */
293#define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */
294
295/* Clock source register bits */
296#define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */
297#define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
298#define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
299#define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
300#define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
301#define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */
302#define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */
303#define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
304
305
306/* HW definitions */
307#define MAX3107_RX_FIFO_SIZE 128
308#define MAX3107_TX_FIFO_SIZE 128
309#define MAX3107_REVID1 0x00a0
310#define MAX3107_REVID2 0x00a1
311
312
313/* Baud rate generator configuration values for external clock 13MHz */
314#define MAX3107_BRG13_B300 (0x0A9400 | 0x05)
315#define MAX3107_BRG13_B600 (0x054A00 | 0x03)
316#define MAX3107_BRG13_B1200 (0x02A500 | 0x01)
317#define MAX3107_BRG13_B2400 (0x015200 | 0x09)
318#define MAX3107_BRG13_B4800 (0x00A900 | 0x04)
319#define MAX3107_BRG13_B9600 (0x005400 | 0x0A)
320#define MAX3107_BRG13_B19200 (0x002A00 | 0x05)
321#define MAX3107_BRG13_B38400 (0x001500 | 0x03)
322#define MAX3107_BRG13_B57600 (0x000E00 | 0x02)
323#define MAX3107_BRG13_B115200 (0x000700 | 0x01)
324#define MAX3107_BRG13_B230400 (0x000300 | 0x08)
325#define MAX3107_BRG13_B460800 (0x000100 | 0x0c)
326#define MAX3107_BRG13_B921600 (0x000100 | 0x1c)
327
328/* Baud rate generator configuration values for external clock 26MHz */
329#define MAX3107_BRG26_B300 (0x152800 | 0x0A)
330#define MAX3107_BRG26_B600 (0x0A9400 | 0x05)
331#define MAX3107_BRG26_B1200 (0x054A00 | 0x03)
332#define MAX3107_BRG26_B2400 (0x02A500 | 0x01)
333#define MAX3107_BRG26_B4800 (0x015200 | 0x09)
334#define MAX3107_BRG26_B9600 (0x00A900 | 0x04)
335#define MAX3107_BRG26_B19200 (0x005400 | 0x0A)
336#define MAX3107_BRG26_B38400 (0x002A00 | 0x05)
337#define MAX3107_BRG26_B57600 (0x001C00 | 0x03)
338#define MAX3107_BRG26_B115200 (0x000E00 | 0x02)
339#define MAX3107_BRG26_B230400 (0x000700 | 0x01)
340#define MAX3107_BRG26_B460800 (0x000300 | 0x08)
341#define MAX3107_BRG26_B921600 (0x000100 | 0x0C)
342
343/* Baud rate generator configuration values for internal clock */
344#define MAX3107_BRG13_IB300 (0x008000 | 0x00)
345#define MAX3107_BRG13_IB600 (0x004000 | 0x00)
346#define MAX3107_BRG13_IB1200 (0x002000 | 0x00)
347#define MAX3107_BRG13_IB2400 (0x001000 | 0x00)
348#define MAX3107_BRG13_IB4800 (0x000800 | 0x00)
349#define MAX3107_BRG13_IB9600 (0x000400 | 0x00)
350#define MAX3107_BRG13_IB19200 (0x000200 | 0x00)
351#define MAX3107_BRG13_IB38400 (0x000100 | 0x00)
352#define MAX3107_BRG13_IB57600 (0x000000 | 0x0B)
353#define MAX3107_BRG13_IB115200 (0x000000 | 0x05)
354#define MAX3107_BRG13_IB230400 (0x000000 | 0x03)
355#define MAX3107_BRG13_IB460800 (0x000000 | 0x00)
356#define MAX3107_BRG13_IB921600 (0x000000 | 0x00)
357
358
359struct baud_table {
360 int baud;
361 u32 new_brg;
362};
363
364struct max3107_port {
365 /* UART port structure */
366 struct uart_port port;
367
368 /* SPI device structure */
369 struct spi_device *spi;
370
371#if defined(CONFIG_GPIOLIB)
372 /* GPIO chip structure */
373 struct gpio_chip chip;
374#endif
375
376 /* Workqueue that does all the magic */
377 struct workqueue_struct *workqueue;
378 struct work_struct work;
379
380 /* Lock for shared data */
381 spinlock_t data_lock;
382
383 /* Device configuration */
384 int ext_clk; /* 1 if external clock used */
385 int loopback; /* Current loopback mode state */
386 int baud; /* Current baud rate */
387
388 /* State flags */
389 int suspended; /* Indicates suspend mode */
390 int tx_fifo_empty; /* Flag for TX FIFO state */
391 int rx_enabled; /* Flag for receiver state */
392 int tx_enabled; /* Flag for transmitter state */
393
394 u16 irqen_reg; /* Current IRQ enable register value */
395 /* Shared data */
396 u16 mode1_reg; /* Current mode1 register value*/
397 int mode1_commit; /* Flag for setting new mode1 register value */
398 u16 lcr_reg; /* Current LCR register value */
399 int lcr_commit; /* Flag for setting new LCR register value */
400 u32 brg_cfg; /* Current Baud rate generator config */
401 int brg_commit; /* Flag for setting new baud rate generator
402 * config
403 */
404 struct baud_table *baud_tbl;
405 int handle_irq; /* Indicates that IRQ should be handled */
406
407 /* Rx buffer and str*/
408 u16 *rxbuf;
409 u8 *rxstr;
410 /* Tx buffer*/
411 u16 *txbuf;
412
413 struct max3107_plat *pdata; /* Platform data */
414};
415
416/* Platform data structure */
417struct max3107_plat {
418 /* Loopback mode enable */
419 int loopback;
420 /* External clock enable */
421 int ext_clk;
422 /* Called during the register initialisation */
423 void (*init)(struct max3107_port *s);
424 /* Called when the port is found and configured */
425 int (*configure)(struct max3107_port *s);
426 /* HW suspend function */
427 void (*hw_suspend) (struct max3107_port *s, int suspend);
428 /* Polling mode enable */
429 int polled_mode;
430 /* Polling period if polling mode enabled */
431 int poll_time;
432};
433
434extern int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len);
435extern void max3107_hw_susp(struct max3107_port *s, int suspend);
436extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata);
437extern int max3107_remove(struct spi_device *spi);
438extern int max3107_suspend(struct spi_device *spi, pm_message_t state);
439extern int max3107_resume(struct spi_device *spi);
440
441#endif /* _LINUX_SERIAL_MAX3107_H */
diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
new file mode 100644
index 000000000000..534e44851b7f
--- /dev/null
+++ b/drivers/tty/serial/max310x.c
@@ -0,0 +1,1259 @@
1/*
2 * Maxim (Dallas) MAX3107/8 serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16/* TODO: MAX3109 support (Dual) */
17/* TODO: MAX14830 support (Quad) */
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/regmap.h>
26#include <linux/gpio.h>
27#include <linux/spi/spi.h>
28#include <linux/platform_data/max310x.h>
29
30#define MAX310X_MAJOR 204
31#define MAX310X_MINOR 209
32
33/* MAX310X register definitions */
34#define MAX310X_RHR_REG (0x00) /* RX FIFO */
35#define MAX310X_THR_REG (0x00) /* TX FIFO */
36#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
37#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
38#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
39#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
40#define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */
41#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
42#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
43#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
44#define MAX310X_MODE1_REG (0x09) /* MODE1 */
45#define MAX310X_MODE2_REG (0x0a) /* MODE2 */
46#define MAX310X_LCR_REG (0x0b) /* LCR */
47#define MAX310X_RXTO_REG (0x0c) /* RX timeout */
48#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
49#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
50#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
51#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
52#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
53#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
54#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
55#define MAX310X_XON1_REG (0x14) /* XON1 character */
56#define MAX310X_XON2_REG (0x15) /* XON2 character */
57#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
58#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
59#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
60#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
61#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
62#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
63#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
64#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
65#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
66/* Only present in MAX3107 */
67#define MAX3107_REVID_REG (0x1f) /* Revision identification */
68
69/* IRQ register bits */
70#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
71#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
72#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
73#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
74#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
75#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
76#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
77#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
78
79/* LSR register bits */
80#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
81#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
82#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
83#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
84#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
85#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
86#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
87
88/* Special character register bits */
89#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
90#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
91#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
92#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
93#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
94#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
95
96/* Status register bits */
97#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
98#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
99#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
100#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
101#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
102#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
103
104/* MODE1 register bits */
105#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
106#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
107#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
108#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
109#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
110#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
111#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
112#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
113
114/* MODE2 register bits */
115#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
116#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
117#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
118#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
119#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
120#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
121#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
122#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
123
124/* LCR register bits */
125#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
126#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
127 *
128 * Word length bits table:
129 * 00 -> 5 bit words
130 * 01 -> 6 bit words
131 * 10 -> 7 bit words
132 * 11 -> 8 bit words
133 */
134#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
135 *
136 * STOP length bit table:
137 * 0 -> 1 stop bit
138 * 1 -> 1-1.5 stop bits if
139 * word length is 5,
140 * 2 stop bits otherwise
141 */
142#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
143#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
144#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
145#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
146#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
147#define MAX310X_LCR_WORD_LEN_5 (0x00)
148#define MAX310X_LCR_WORD_LEN_6 (0x01)
149#define MAX310X_LCR_WORD_LEN_7 (0x02)
150#define MAX310X_LCR_WORD_LEN_8 (0x03)
151
152/* IRDA register bits */
153#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
154#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
155#define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
156#define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
157#define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
158#define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
159
160/* Flow control trigger level register masks */
161#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
162#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
163#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
164#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
165
166/* FIFO interrupt trigger level register masks */
167#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
168#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
169#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
170#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
171
172/* Flow control register bits */
173#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
174#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
175#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
176 * are used in conjunction with
177 * XOFF2 for definition of
178 * special character */
179#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
180#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
181#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
182 *
183 * SWFLOW bits 1 & 0 table:
184 * 00 -> no transmitter flow
185 * control
186 * 01 -> receiver compares
187 * XON2 and XOFF2
188 * and controls
189 * transmitter
190 * 10 -> receiver compares
191 * XON1 and XOFF1
192 * and controls
193 * transmitter
194 * 11 -> receiver compares
195 * XON1, XON2, XOFF1 and
196 * XOFF2 and controls
197 * transmitter
198 */
199#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
200#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
201 *
202 * SWFLOW bits 3 & 2 table:
203 * 00 -> no received flow
204 * control
205 * 01 -> transmitter generates
206 * XON2 and XOFF2
207 * 10 -> transmitter generates
208 * XON1 and XOFF1
209 * 11 -> transmitter generates
210 * XON1, XON2, XOFF1 and
211 * XOFF2
212 */
213
214/* GPIO configuration register bits */
215#define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
216#define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
217#define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
218#define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
219#define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
220#define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
221#define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
222#define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
223
224/* GPIO DATA register bits */
225#define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
226#define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
227#define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
228#define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
229#define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
230#define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
231#define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
232#define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
233
234/* PLL configuration register masks */
235#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
236#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
237
238/* Baud rate generator configuration register bits */
239#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
240#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
241
242/* Clock source register bits */
243#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
244#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
245#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
246#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
247#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
248
249/* Misc definitions */
250#define MAX310X_FIFO_SIZE (128)
251
252/* MAX3107 specific */
253#define MAX3107_REV_ID (0xa0)
254#define MAX3107_REV_MASK (0xfe)
255
256/* IRQ status bits definitions */
257#define MAX310X_IRQ_TX (MAX310X_IRQ_TXFIFO_BIT | \
258 MAX310X_IRQ_TXEMPTY_BIT)
259#define MAX310X_IRQ_RX (MAX310X_IRQ_RXFIFO_BIT | \
260 MAX310X_IRQ_RXEMPTY_BIT)
261
262/* Supported chip types */
263enum {
264 MAX310X_TYPE_MAX3107 = 3107,
265 MAX310X_TYPE_MAX3108 = 3108,
266};
267
268struct max310x_port {
269 struct uart_driver uart;
270 struct uart_port port;
271
272 const char *name;
273 int uartclk;
274
275 unsigned int nr_gpio;
276#ifdef CONFIG_GPIOLIB
277 struct gpio_chip gpio;
278#endif
279
280 struct regmap *regmap;
281 struct regmap_config regcfg;
282
283 struct workqueue_struct *wq;
284 struct work_struct tx_work;
285
286 struct mutex max310x_mutex;
287
288 struct max310x_pdata *pdata;
289};
290
291static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg)
292{
293 switch (reg) {
294 case MAX310X_IRQSTS_REG:
295 case MAX310X_LSR_IRQSTS_REG:
296 case MAX310X_SPCHR_IRQSTS_REG:
297 case MAX310X_STS_IRQSTS_REG:
298 case MAX310X_TXFIFOLVL_REG:
299 case MAX310X_RXFIFOLVL_REG:
300 case MAX3107_REVID_REG: /* Only available on MAX3107 */
301 return false;
302 default:
303 break;
304 }
305
306 return true;
307}
308
309static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
310{
311 switch (reg) {
312 case MAX310X_RHR_REG:
313 case MAX310X_IRQSTS_REG:
314 case MAX310X_LSR_IRQSTS_REG:
315 case MAX310X_SPCHR_IRQSTS_REG:
316 case MAX310X_STS_IRQSTS_REG:
317 case MAX310X_TXFIFOLVL_REG:
318 case MAX310X_RXFIFOLVL_REG:
319 case MAX310X_GPIODATA_REG:
320 return true;
321 default:
322 break;
323 }
324
325 return false;
326}
327
328static bool max310x_reg_precious(struct device *dev, unsigned int reg)
329{
330 switch (reg) {
331 case MAX310X_RHR_REG:
332 case MAX310X_IRQSTS_REG:
333 case MAX310X_SPCHR_IRQSTS_REG:
334 case MAX310X_STS_IRQSTS_REG:
335 return true;
336 default:
337 break;
338 }
339
340 return false;
341}
342
343static void max310x_set_baud(struct max310x_port *s, int baud)
344{
345 unsigned int mode = 0, div = s->uartclk / baud;
346
347 if (!(div / 16)) {
348 /* Mode x2 */
349 mode = MAX310X_BRGCFG_2XMODE_BIT;
350 div = (s->uartclk * 2) / baud;
351 }
352
353 if (!(div / 16)) {
354 /* Mode x4 */
355 mode = MAX310X_BRGCFG_4XMODE_BIT;
356 div = (s->uartclk * 4) / baud;
357 }
358
359 regmap_write(s->regmap, MAX310X_BRGDIVMSB_REG,
360 ((div / 16) >> 8) & 0xff);
361 regmap_write(s->regmap, MAX310X_BRGDIVLSB_REG, (div / 16) & 0xff);
362 regmap_write(s->regmap, MAX310X_BRGCFG_REG, (div % 16) | mode);
363}
364
365static void max310x_wait_pll(struct max310x_port *s)
366{
367 int tryes = 1000;
368
369 /* Wait for PLL only if crystal is used */
370 if (!(s->pdata->driver_flags & MAX310X_EXT_CLK)) {
371 unsigned int sts = 0;
372
373 while (tryes--) {
374 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &sts);
375 if (sts & MAX310X_STS_CLKREADY_BIT)
376 break;
377 }
378 }
379}
380
381static int __devinit max310x_update_best_err(unsigned long f, long *besterr)
382{
383 /* Use baudrate 115200 for calculate error */
384 long err = f % (115200 * 16);
385
386 if ((*besterr < 0) || (*besterr > err)) {
387 *besterr = err;
388 return 0;
389 }
390
391 return 1;
392}
393
394static int __devinit max310x_set_ref_clk(struct max310x_port *s)
395{
396 unsigned int div, clksrc, pllcfg = 0;
397 long besterr = -1;
398 unsigned long fdiv, fmul, bestfreq = s->pdata->frequency;
399
400 /* First, update error without PLL */
401 max310x_update_best_err(s->pdata->frequency, &besterr);
402
403 /* Try all possible PLL dividers */
404 for (div = 1; (div <= 63) && besterr; div++) {
405 fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div);
406
407 /* Try multiplier 6 */
408 fmul = fdiv * 6;
409 if ((fdiv >= 500000) && (fdiv <= 800000))
410 if (!max310x_update_best_err(fmul, &besterr)) {
411 pllcfg = (0 << 6) | div;
412 bestfreq = fmul;
413 }
414 /* Try multiplier 48 */
415 fmul = fdiv * 48;
416 if ((fdiv >= 850000) && (fdiv <= 1200000))
417 if (!max310x_update_best_err(fmul, &besterr)) {
418 pllcfg = (1 << 6) | div;
419 bestfreq = fmul;
420 }
421 /* Try multiplier 96 */
422 fmul = fdiv * 96;
423 if ((fdiv >= 425000) && (fdiv <= 1000000))
424 if (!max310x_update_best_err(fmul, &besterr)) {
425 pllcfg = (2 << 6) | div;
426 bestfreq = fmul;
427 }
428 /* Try multiplier 144 */
429 fmul = fdiv * 144;
430 if ((fdiv >= 390000) && (fdiv <= 667000))
431 if (!max310x_update_best_err(fmul, &besterr)) {
432 pllcfg = (3 << 6) | div;
433 bestfreq = fmul;
434 }
435 }
436
437 /* Configure clock source */
438 if (s->pdata->driver_flags & MAX310X_EXT_CLK)
439 clksrc = MAX310X_CLKSRC_EXTCLK_BIT;
440 else
441 clksrc = MAX310X_CLKSRC_CRYST_BIT;
442
443 /* Configure PLL */
444 if (pllcfg) {
445 clksrc |= MAX310X_CLKSRC_PLL_BIT;
446 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
447 } else
448 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
449
450 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
451
452 if (pllcfg)
453 max310x_wait_pll(s);
454
455 dev_dbg(s->port.dev, "Reference clock set to %lu Hz\n", bestfreq);
456
457 return (int)bestfreq;
458}
459
460static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen)
461{
462 unsigned int sts = 0, ch = 0, flag;
463 struct tty_struct *tty = tty_port_tty_get(&s->port.state->port);
464
465 if (!tty)
466 return;
467
468 if (unlikely(rxlen >= MAX310X_FIFO_SIZE)) {
469 dev_warn(s->port.dev, "Possible RX FIFO overrun %d\n", rxlen);
470 /* Ensure sanity of RX level */
471 rxlen = MAX310X_FIFO_SIZE;
472 }
473
474 dev_dbg(s->port.dev, "RX Len = %u\n", rxlen);
475
476 while (rxlen--) {
477 regmap_read(s->regmap, MAX310X_RHR_REG, &ch);
478 regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &sts);
479
480 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
481 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
482
483 s->port.icount.rx++;
484 flag = TTY_NORMAL;
485
486 if (unlikely(sts)) {
487 if (sts & MAX310X_LSR_RXBRK_BIT) {
488 s->port.icount.brk++;
489 if (uart_handle_break(&s->port))
490 continue;
491 } else if (sts & MAX310X_LSR_RXPAR_BIT)
492 s->port.icount.parity++;
493 else if (sts & MAX310X_LSR_FRERR_BIT)
494 s->port.icount.frame++;
495 else if (sts & MAX310X_LSR_RXOVR_BIT)
496 s->port.icount.overrun++;
497
498 sts &= s->port.read_status_mask;
499 if (sts & MAX310X_LSR_RXBRK_BIT)
500 flag = TTY_BREAK;
501 else if (sts & MAX310X_LSR_RXPAR_BIT)
502 flag = TTY_PARITY;
503 else if (sts & MAX310X_LSR_FRERR_BIT)
504 flag = TTY_FRAME;
505 else if (sts & MAX310X_LSR_RXOVR_BIT)
506 flag = TTY_OVERRUN;
507 }
508
509 if (uart_handle_sysrq_char(s->port, ch))
510 continue;
511
512 if (sts & s->port.ignore_status_mask)
513 continue;
514
515 uart_insert_char(&s->port, sts, MAX310X_LSR_RXOVR_BIT,
516 ch, flag);
517 }
518
519 tty_flip_buffer_push(tty);
520
521 tty_kref_put(tty);
522}
523
524static void max310x_handle_tx(struct max310x_port *s)
525{
526 struct circ_buf *xmit = &s->port.state->xmit;
527 unsigned int txlen = 0, to_send;
528
529 if (unlikely(s->port.x_char)) {
530 regmap_write(s->regmap, MAX310X_THR_REG, s->port.x_char);
531 s->port.icount.tx++;
532 s->port.x_char = 0;
533 return;
534 }
535
536 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
537 return;
538
539 /* Get length of data pending in circular buffer */
540 to_send = uart_circ_chars_pending(xmit);
541 if (likely(to_send)) {
542 /* Limit to size of TX FIFO */
543 regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &txlen);
544 txlen = MAX310X_FIFO_SIZE - txlen;
545 to_send = (to_send > txlen) ? txlen : to_send;
546
547 dev_dbg(s->port.dev, "TX Len = %u\n", to_send);
548
549 /* Add data to send */
550 s->port.icount.tx += to_send;
551 while (to_send--) {
552 regmap_write(s->regmap, MAX310X_THR_REG,
553 xmit->buf[xmit->tail]);
554 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
555 };
556 }
557
558 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(&s->port);
560}
561
562static irqreturn_t max310x_ist(int irq, void *dev_id)
563{
564 struct max310x_port *s = (struct max310x_port *)dev_id;
565 unsigned int ists = 0, lsr = 0, rxlen = 0;
566
567 mutex_lock(&s->max310x_mutex);
568
569 for (;;) {
570 /* Read IRQ status & RX FIFO level */
571 regmap_read(s->regmap, MAX310X_IRQSTS_REG, &ists);
572 regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &lsr);
573 regmap_read(s->regmap, MAX310X_RXFIFOLVL_REG, &rxlen);
574 if (!ists && !(lsr & MAX310X_LSR_RXTO_BIT) && !rxlen)
575 break;
576
577 dev_dbg(s->port.dev, "IRQ status: 0x%02x\n", ists);
578
579 if (rxlen)
580 max310x_handle_rx(s, rxlen);
581 if (ists & MAX310X_IRQ_TX)
582 max310x_handle_tx(s);
583 if (ists & MAX310X_IRQ_CTS_BIT)
584 uart_handle_cts_change(&s->port,
585 !!(lsr & MAX310X_LSR_CTS_BIT));
586 }
587
588 mutex_unlock(&s->max310x_mutex);
589
590 return IRQ_HANDLED;
591}
592
593static void max310x_wq_proc(struct work_struct *ws)
594{
595 struct max310x_port *s = container_of(ws, struct max310x_port, tx_work);
596
597 mutex_lock(&s->max310x_mutex);
598 max310x_handle_tx(s);
599 mutex_unlock(&s->max310x_mutex);
600}
601
602static void max310x_start_tx(struct uart_port *port)
603{
604 struct max310x_port *s = container_of(port, struct max310x_port, port);
605
606 queue_work(s->wq, &s->tx_work);
607}
608
609static void max310x_stop_tx(struct uart_port *port)
610{
611 /* Do nothing */
612}
613
614static void max310x_stop_rx(struct uart_port *port)
615{
616 /* Do nothing */
617}
618
619static unsigned int max310x_tx_empty(struct uart_port *port)
620{
621 unsigned int val = 0;
622 struct max310x_port *s = container_of(port, struct max310x_port, port);
623
624 mutex_lock(&s->max310x_mutex);
625 regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &val);
626 mutex_unlock(&s->max310x_mutex);
627
628 return val ? 0 : TIOCSER_TEMT;
629}
630
631static void max310x_enable_ms(struct uart_port *port)
632{
633 /* Modem status not supported */
634}
635
636static unsigned int max310x_get_mctrl(struct uart_port *port)
637{
638 /* DCD and DSR are not wired and CTS/RTS is handled automatically
639 * so just indicate DSR and CAR asserted
640 */
641 return TIOCM_DSR | TIOCM_CAR;
642}
643
644static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
645{
646 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
647 * so do nothing
648 */
649}
650
651static void max310x_break_ctl(struct uart_port *port, int break_state)
652{
653 struct max310x_port *s = container_of(port, struct max310x_port, port);
654
655 mutex_lock(&s->max310x_mutex);
656 regmap_update_bits(s->regmap, MAX310X_LCR_REG,
657 MAX310X_LCR_TXBREAK_BIT,
658 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
659 mutex_unlock(&s->max310x_mutex);
660}
661
662static void max310x_set_termios(struct uart_port *port,
663 struct ktermios *termios,
664 struct ktermios *old)
665{
666 struct max310x_port *s = container_of(port, struct max310x_port, port);
667 unsigned int lcr, flow = 0;
668 int baud;
669
670 mutex_lock(&s->max310x_mutex);
671
672 /* Mask termios capabilities we don't support */
673 termios->c_cflag &= ~CMSPAR;
674 termios->c_iflag &= ~IXANY;
675
676 /* Word size */
677 switch (termios->c_cflag & CSIZE) {
678 case CS5:
679 lcr = MAX310X_LCR_WORD_LEN_5;
680 break;
681 case CS6:
682 lcr = MAX310X_LCR_WORD_LEN_6;
683 break;
684 case CS7:
685 lcr = MAX310X_LCR_WORD_LEN_7;
686 break;
687 case CS8:
688 default:
689 lcr = MAX310X_LCR_WORD_LEN_8;
690 break;
691 }
692
693 /* Parity */
694 if (termios->c_cflag & PARENB) {
695 lcr |= MAX310X_LCR_PARITY_BIT;
696 if (!(termios->c_cflag & PARODD))
697 lcr |= MAX310X_LCR_EVENPARITY_BIT;
698 }
699
700 /* Stop bits */
701 if (termios->c_cflag & CSTOPB)
702 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
703
704 /* Update LCR register */
705 regmap_write(s->regmap, MAX310X_LCR_REG, lcr);
706
707 /* Set read status mask */
708 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
709 if (termios->c_iflag & INPCK)
710 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
711 MAX310X_LSR_FRERR_BIT;
712 if (termios->c_iflag & (BRKINT | PARMRK))
713 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
714
715 /* Set status ignore mask */
716 port->ignore_status_mask = 0;
717 if (termios->c_iflag & IGNBRK)
718 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
719 if (!(termios->c_cflag & CREAD))
720 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
721 MAX310X_LSR_RXOVR_BIT |
722 MAX310X_LSR_FRERR_BIT |
723 MAX310X_LSR_RXBRK_BIT;
724
725 /* Configure flow control */
726 regmap_write(s->regmap, MAX310X_XON1_REG, termios->c_cc[VSTART]);
727 regmap_write(s->regmap, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
728 if (termios->c_cflag & CRTSCTS)
729 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
730 MAX310X_FLOWCTRL_AUTORTS_BIT;
731 if (termios->c_iflag & IXON)
732 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
733 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
734 if (termios->c_iflag & IXOFF)
735 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
736 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
737 regmap_write(s->regmap, MAX310X_FLOWCTRL_REG, flow);
738
739 /* Get baud rate generator configuration */
740 baud = uart_get_baud_rate(port, termios, old,
741 port->uartclk / 16 / 0xffff,
742 port->uartclk / 4);
743
744 /* Setup baudrate generator */
745 max310x_set_baud(s, baud);
746
747 /* Update timeout according to new baud rate */
748 uart_update_timeout(port, termios->c_cflag, baud);
749
750 mutex_unlock(&s->max310x_mutex);
751}
752
753static int max310x_startup(struct uart_port *port)
754{
755 unsigned int val, line = port->line;
756 struct max310x_port *s = container_of(port, struct max310x_port, port);
757
758 if (s->pdata->suspend)
759 s->pdata->suspend(0);
760
761 mutex_lock(&s->max310x_mutex);
762
763 /* Configure baud rate, 9600 as default */
764 max310x_set_baud(s, 9600);
765
766 /* Configure LCR register, 8N1 mode by default */
767 val = MAX310X_LCR_WORD_LEN_8;
768 regmap_write(s->regmap, MAX310X_LCR_REG, val);
769
770 /* Configure MODE1 register */
771 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
772 MAX310X_MODE1_TRNSCVCTRL_BIT,
773 (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL)
774 ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0);
775
776 /* Configure MODE2 register */
777 val = MAX310X_MODE2_RXEMPTINV_BIT;
778 if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK)
779 val |= MAX310X_MODE2_LOOPBACK_BIT;
780 if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS)
781 val |= MAX310X_MODE2_ECHOSUPR_BIT;
782
783 /* Reset FIFOs */
784 val |= MAX310X_MODE2_FIFORST_BIT;
785 regmap_write(s->regmap, MAX310X_MODE2_REG, val);
786
787 /* Configure FIFO trigger level register */
788 /* RX FIFO trigger for 16 words, TX FIFO trigger for 64 words */
789 val = MAX310X_FIFOTRIGLVL_RX(16) | MAX310X_FIFOTRIGLVL_TX(64);
790 regmap_write(s->regmap, MAX310X_FIFOTRIGLVL_REG, val);
791
792 /* Configure flow control levels */
793 /* Flow control halt level 96, resume level 48 */
794 val = MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96);
795 regmap_write(s->regmap, MAX310X_FLOWLVL_REG, val);
796
797 /* Clear timeout register */
798 regmap_write(s->regmap, MAX310X_RXTO_REG, 0);
799
800 /* Configure LSR interrupt enable register */
801 /* Enable RX timeout interrupt */
802 val = MAX310X_LSR_RXTO_BIT;
803 regmap_write(s->regmap, MAX310X_LSR_IRQEN_REG, val);
804
805 /* Clear FIFO reset */
806 regmap_update_bits(s->regmap, MAX310X_MODE2_REG,
807 MAX310X_MODE2_FIFORST_BIT, 0);
808
809 /* Clear IRQ status register by reading it */
810 regmap_read(s->regmap, MAX310X_IRQSTS_REG, &val);
811
812 /* Configure interrupt enable register */
813 /* Enable CTS change interrupt */
814 val = MAX310X_IRQ_CTS_BIT;
815 /* Enable RX, TX interrupts */
816 val |= MAX310X_IRQ_RX | MAX310X_IRQ_TX;
817 regmap_write(s->regmap, MAX310X_IRQEN_REG, val);
818
819 mutex_unlock(&s->max310x_mutex);
820
821 return 0;
822}
823
824static void max310x_shutdown(struct uart_port *port)
825{
826 struct max310x_port *s = container_of(port, struct max310x_port, port);
827
828 /* Disable all interrupts */
829 mutex_lock(&s->max310x_mutex);
830 regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
831 mutex_unlock(&s->max310x_mutex);
832
833 if (s->pdata->suspend)
834 s->pdata->suspend(1);
835}
836
837static const char *max310x_type(struct uart_port *port)
838{
839 struct max310x_port *s = container_of(port, struct max310x_port, port);
840
841 return (port->type == PORT_MAX310X) ? s->name : NULL;
842}
843
844static int max310x_request_port(struct uart_port *port)
845{
846 /* Do nothing */
847 return 0;
848}
849
850static void max310x_release_port(struct uart_port *port)
851{
852 /* Do nothing */
853}
854
855static void max310x_config_port(struct uart_port *port, int flags)
856{
857 if (flags & UART_CONFIG_TYPE)
858 port->type = PORT_MAX310X;
859}
860
861static int max310x_verify_port(struct uart_port *port, struct serial_struct *ser)
862{
863 if ((ser->type == PORT_UNKNOWN) || (ser->type == PORT_MAX310X))
864 return 0;
865 if (ser->irq == port->irq)
866 return 0;
867
868 return -EINVAL;
869}
870
871static struct uart_ops max310x_ops = {
872 .tx_empty = max310x_tx_empty,
873 .set_mctrl = max310x_set_mctrl,
874 .get_mctrl = max310x_get_mctrl,
875 .stop_tx = max310x_stop_tx,
876 .start_tx = max310x_start_tx,
877 .stop_rx = max310x_stop_rx,
878 .enable_ms = max310x_enable_ms,
879 .break_ctl = max310x_break_ctl,
880 .startup = max310x_startup,
881 .shutdown = max310x_shutdown,
882 .set_termios = max310x_set_termios,
883 .type = max310x_type,
884 .request_port = max310x_request_port,
885 .release_port = max310x_release_port,
886 .config_port = max310x_config_port,
887 .verify_port = max310x_verify_port,
888};
889
890static int max310x_suspend(struct spi_device *spi, pm_message_t state)
891{
892 int ret;
893 struct max310x_port *s = dev_get_drvdata(&spi->dev);
894
895 dev_dbg(&spi->dev, "Suspend\n");
896
897 ret = uart_suspend_port(&s->uart, &s->port);
898
899 mutex_lock(&s->max310x_mutex);
900
901 /* Enable sleep mode */
902 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
903 MAX310X_MODE1_FORCESLEEP_BIT,
904 MAX310X_MODE1_FORCESLEEP_BIT);
905
906 mutex_unlock(&s->max310x_mutex);
907
908 if (s->pdata->suspend)
909 s->pdata->suspend(1);
910
911 return ret;
912}
913
914static int max310x_resume(struct spi_device *spi)
915{
916 struct max310x_port *s = dev_get_drvdata(&spi->dev);
917
918 dev_dbg(&spi->dev, "Resume\n");
919
920 if (s->pdata->suspend)
921 s->pdata->suspend(0);
922
923 mutex_lock(&s->max310x_mutex);
924
925 /* Disable sleep mode */
926 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
927 MAX310X_MODE1_FORCESLEEP_BIT,
928 0);
929
930 max310x_wait_pll(s);
931
932 mutex_unlock(&s->max310x_mutex);
933
934 return uart_resume_port(&s->uart, &s->port);
935}
936
937#ifdef CONFIG_GPIOLIB
938static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
939{
940 unsigned int val = 0;
941 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
942
943 mutex_lock(&s->max310x_mutex);
944 regmap_read(s->regmap, MAX310X_GPIODATA_REG, &val);
945 mutex_unlock(&s->max310x_mutex);
946
947 return !!((val >> 4) & (1 << offset));
948}
949
950static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
951{
952 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
953
954 mutex_lock(&s->max310x_mutex);
955 regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
956 1 << offset : 0);
957 mutex_unlock(&s->max310x_mutex);
958}
959
960static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
961{
962 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
963
964 mutex_lock(&s->max310x_mutex);
965
966 regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, 0);
967
968 mutex_unlock(&s->max310x_mutex);
969
970 return 0;
971}
972
973static int max310x_gpio_direction_output(struct gpio_chip *chip,
974 unsigned offset, int value)
975{
976 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
977
978 mutex_lock(&s->max310x_mutex);
979
980 regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset,
981 1 << offset);
982 regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
983 1 << offset : 0);
984
985 mutex_unlock(&s->max310x_mutex);
986
987 return 0;
988}
989#endif
990
991/* Generic platform data */
992static struct max310x_pdata generic_plat_data = {
993 .driver_flags = MAX310X_EXT_CLK,
994 .uart_flags[0] = MAX310X_ECHO_SUPRESS,
995 .frequency = 26000000,
996};
997
998static int __devinit max310x_probe(struct spi_device *spi)
999{
1000 struct max310x_port *s;
1001 struct device *dev = &spi->dev;
1002 int chiptype = spi_get_device_id(spi)->driver_data;
1003 struct max310x_pdata *pdata = dev->platform_data;
1004 unsigned int val = 0;
1005 int ret;
1006
1007 /* Check for IRQ */
1008 if (spi->irq <= 0) {
1009 dev_err(dev, "No IRQ specified\n");
1010 return -ENOTSUPP;
1011 }
1012
1013 /* Alloc port structure */
1014 s = devm_kzalloc(dev, sizeof(struct max310x_port), GFP_KERNEL);
1015 if (!s) {
1016 dev_err(dev, "Error allocating port structure\n");
1017 return -ENOMEM;
1018 }
1019 dev_set_drvdata(dev, s);
1020
1021 if (!pdata) {
1022 dev_warn(dev, "No platform data supplied, using defaults\n");
1023 pdata = &generic_plat_data;
1024 }
1025 s->pdata = pdata;
1026
1027 /* Individual chip settings */
1028 switch (chiptype) {
1029 case MAX310X_TYPE_MAX3107:
1030 s->name = "MAX3107";
1031 s->nr_gpio = 4;
1032 s->uart.nr = 1;
1033 s->regcfg.max_register = 0x1f;
1034 break;
1035 case MAX310X_TYPE_MAX3108:
1036 s->name = "MAX3108";
1037 s->nr_gpio = 4;
1038 s->uart.nr = 1;
1039 s->regcfg.max_register = 0x1e;
1040 break;
1041 default:
1042 dev_err(dev, "Unsupported chip type %i\n", chiptype);
1043 return -ENOTSUPP;
1044 }
1045
1046 /* Check input frequency */
1047 if ((pdata->driver_flags & MAX310X_EXT_CLK) &&
1048 ((pdata->frequency < 500000) || (pdata->frequency > 35000000)))
1049 goto err_freq;
1050 /* Check frequency for quartz */
1051 if (!(pdata->driver_flags & MAX310X_EXT_CLK) &&
1052 ((pdata->frequency < 1000000) || (pdata->frequency > 4000000)))
1053 goto err_freq;
1054
1055 mutex_init(&s->max310x_mutex);
1056
1057 /* Setup SPI bus */
1058 spi->mode = SPI_MODE_0;
1059 spi->bits_per_word = 8;
1060 spi->max_speed_hz = 26000000;
1061 spi_setup(spi);
1062
1063 /* Setup regmap */
1064 s->regcfg.reg_bits = 8;
1065 s->regcfg.val_bits = 8;
1066 s->regcfg.read_flag_mask = 0x00;
1067 s->regcfg.write_flag_mask = 0x80;
1068 s->regcfg.cache_type = REGCACHE_RBTREE;
1069 s->regcfg.writeable_reg = max3107_8_reg_writeable;
1070 s->regcfg.volatile_reg = max310x_reg_volatile;
1071 s->regcfg.precious_reg = max310x_reg_precious;
1072 s->regmap = devm_regmap_init_spi(spi, &s->regcfg);
1073 if (IS_ERR(s->regmap)) {
1074 ret = PTR_ERR(s->regmap);
1075 dev_err(dev, "Failed to initialize register map\n");
1076 goto err_out;
1077 }
1078
1079 /* Reset chip & check SPI function */
1080 ret = regmap_write(s->regmap, MAX310X_MODE2_REG, MAX310X_MODE2_RST_BIT);
1081 if (ret) {
1082 dev_err(dev, "SPI transfer failed\n");
1083 goto err_out;
1084 }
1085 /* Clear chip reset */
1086 regmap_write(s->regmap, MAX310X_MODE2_REG, 0);
1087
1088 switch (chiptype) {
1089 case MAX310X_TYPE_MAX3107:
1090 /* Check REV ID to ensure we are talking to what we expect */
1091 regmap_read(s->regmap, MAX3107_REVID_REG, &val);
1092 if (((val & MAX3107_REV_MASK) != MAX3107_REV_ID)) {
1093 dev_err(dev, "%s ID 0x%02x does not match\n",
1094 s->name, val);
1095 ret = -ENODEV;
1096 goto err_out;
1097 }
1098 break;
1099 case MAX310X_TYPE_MAX3108:
1100 /* MAX3108 have not REV ID register, we just check default value
1101 * from clocksource register to make sure everything works.
1102 */
1103 regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
1104 if (val != (MAX310X_CLKSRC_EXTCLK_BIT |
1105 MAX310X_CLKSRC_PLLBYP_BIT)) {
1106 dev_err(dev, "%s not present\n", s->name);
1107 ret = -ENODEV;
1108 goto err_out;
1109 }
1110 break;
1111 }
1112
1113 /* Board specific configure */
1114 if (pdata->init)
1115 pdata->init();
1116 if (pdata->suspend)
1117 pdata->suspend(0);
1118
1119 /* Calculate referecne clock */
1120 s->uartclk = max310x_set_ref_clk(s);
1121
1122 /* Disable all interrupts */
1123 regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
1124
1125 /* Setup MODE1 register */
1126 val = MAX310X_MODE1_IRQSEL_BIT; /* Enable IRQ pin */
1127 if (pdata->driver_flags & MAX310X_AUTOSLEEP)
1128 val = MAX310X_MODE1_AUTOSLEEP_BIT;
1129 regmap_write(s->regmap, MAX310X_MODE1_REG, val);
1130
1131 /* Setup interrupt */
1132 ret = devm_request_threaded_irq(dev, spi->irq, NULL, max310x_ist,
1133 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1134 dev_name(dev), s);
1135 if (ret) {
1136 dev_err(dev, "Unable to reguest IRQ %i\n", spi->irq);
1137 goto err_out;
1138 }
1139
1140 /* Register UART driver */
1141 s->uart.owner = THIS_MODULE;
1142 s->uart.driver_name = dev_name(dev);
1143 s->uart.dev_name = "ttyMAX";
1144 s->uart.major = MAX310X_MAJOR;
1145 s->uart.minor = MAX310X_MINOR;
1146 ret = uart_register_driver(&s->uart);
1147 if (ret) {
1148 dev_err(dev, "Registering UART driver failed\n");
1149 goto err_out;
1150 }
1151
1152 /* Initialize workqueue for start TX */
1153 s->wq = create_freezable_workqueue(dev_name(dev));
1154 INIT_WORK(&s->tx_work, max310x_wq_proc);
1155
1156 /* Initialize UART port data */
1157 s->port.line = 0;
1158 s->port.dev = dev;
1159 s->port.irq = spi->irq;
1160 s->port.type = PORT_MAX310X;
1161 s->port.fifosize = MAX310X_FIFO_SIZE;
1162 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
1163 s->port.iotype = UPIO_PORT;
1164 s->port.membase = (void __iomem *)0xffffffff; /* Bogus value */
1165 s->port.uartclk = s->uartclk;
1166 s->port.ops = &max310x_ops;
1167 uart_add_one_port(&s->uart, &s->port);
1168
1169#ifdef CONFIG_GPIOLIB
1170 /* Setup GPIO cotroller */
1171 if (pdata->gpio_base) {
1172 s->gpio.owner = THIS_MODULE;
1173 s->gpio.dev = dev;
1174 s->gpio.label = dev_name(dev);
1175 s->gpio.direction_input = max310x_gpio_direction_input;
1176 s->gpio.get = max310x_gpio_get;
1177 s->gpio.direction_output= max310x_gpio_direction_output;
1178 s->gpio.set = max310x_gpio_set;
1179 s->gpio.base = pdata->gpio_base;
1180 s->gpio.ngpio = s->nr_gpio;
1181 if (gpiochip_add(&s->gpio)) {
1182 /* Indicate that we should not call gpiochip_remove */
1183 s->gpio.base = 0;
1184 }
1185 } else
1186 dev_info(dev, "GPIO support not enabled\n");
1187#endif
1188
1189 /* Go to suspend mode */
1190 if (pdata->suspend)
1191 pdata->suspend(1);
1192
1193 return 0;
1194
1195err_freq:
1196 dev_err(dev, "Frequency parameter incorrect\n");
1197 ret = -EINVAL;
1198
1199err_out:
1200 dev_set_drvdata(dev, NULL);
1201 devm_kfree(dev, s);
1202
1203 return ret;
1204}
1205
1206static int __devexit max310x_remove(struct spi_device *spi)
1207{
1208 struct device *dev = &spi->dev;
1209 struct max310x_port *s = dev_get_drvdata(dev);
1210
1211 dev_dbg(dev, "Removing port\n");
1212
1213 devm_free_irq(dev, s->port.irq, s);
1214
1215 destroy_workqueue(s->wq);
1216
1217 uart_remove_one_port(&s->uart, &s->port);
1218
1219 uart_unregister_driver(&s->uart);
1220
1221#ifdef CONFIG_GPIOLIB
1222 if (s->pdata->gpio_base)
1223 gpiochip_remove(&s->gpio);
1224#endif
1225
1226 dev_set_drvdata(dev, NULL);
1227
1228 if (s->pdata->suspend)
1229 s->pdata->suspend(1);
1230 if (s->pdata->exit)
1231 s->pdata->exit();
1232
1233 devm_kfree(dev, s);
1234
1235 return 0;
1236}
1237
1238static const struct spi_device_id max310x_id_table[] = {
1239 { "max3107", MAX310X_TYPE_MAX3107 },
1240 { "max3108", MAX310X_TYPE_MAX3108 },
1241};
1242MODULE_DEVICE_TABLE(spi, max310x_id_table);
1243
1244static struct spi_driver max310x_driver = {
1245 .driver = {
1246 .name = "max310x",
1247 .owner = THIS_MODULE,
1248 },
1249 .probe = max310x_probe,
1250 .remove = __devexit_p(max310x_remove),
1251 .suspend = max310x_suspend,
1252 .resume = max310x_resume,
1253 .id_table = max310x_id_table,
1254};
1255module_spi_driver(max310x_driver);
1256
1257MODULE_LICENSE("GPL v2");
1258MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1259MODULE_DESCRIPTION("MAX310X serial driver");
diff --git a/include/linux/platform_data/max310x.h b/include/linux/platform_data/max310x.h
new file mode 100644
index 000000000000..91648bf5fc5c
--- /dev/null
+++ b/include/linux/platform_data/max310x.h
@@ -0,0 +1,67 @@
1/*
2 * Maxim (Dallas) MAX3107/8 serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _MAX310X_H_
17#define _MAX310X_H_
18
19/*
20 * Example board initialization data:
21 *
22 * static struct max310x_pdata max3107_pdata = {
23 * .driver_flags = MAX310X_EXT_CLK,
24 * .uart_flags[0] = MAX310X_ECHO_SUPRESS | MAX310X_AUTO_DIR_CTRL,
25 * .frequency = 3686400,
26 * .gpio_base = -1,
27 * };
28 *
29 * static struct spi_board_info spi_device_max3107[] = {
30 * {
31 * .modalias = "max3107",
32 * .irq = IRQ_EINT3,
33 * .bus_num = 1,
34 * .chip_select = 1,
35 * .platform_data = &max3107_pdata,
36 * },
37 * };
38 */
39
40#define MAX310X_MAX_UARTS 1
41
42/* MAX310X platform data structure */
43struct max310x_pdata {
44 /* Flags global to driver */
45 const u8 driver_flags:2;
46#define MAX310X_EXT_CLK (0x00000001) /* External clock enable */
47#define MAX310X_AUTOSLEEP (0x00000002) /* Enable AutoSleep mode */
48 /* Flags global to UART port */
49 const u8 uart_flags[MAX310X_MAX_UARTS];
50#define MAX310X_LOOPBACK (0x00000001) /* Loopback mode enable */
51#define MAX310X_ECHO_SUPRESS (0x00000002) /* Enable echo supress */
52#define MAX310X_AUTO_DIR_CTRL (0x00000004) /* Enable Auto direction
53 * control (RS-485)
54 */
55 /* Frequency (extrenal clock or crystal) */
56 const int frequency;
57 /* GPIO base number (can be negative) */
58 const int gpio_base;
59 /* Called during startup */
60 void (*init)(void);
61 /* Called before finish */
62 void (*exit)(void);
63 /* Suspend callback */
64 void (*suspend)(int do_suspend);
65};
66
67#endif
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 0253c2022e53..7cf0b68bbe9e 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -193,8 +193,8 @@
193/* SH-SCI */ 193/* SH-SCI */
194#define PORT_SCIFB 93 194#define PORT_SCIFB 93
195 195
196/* MAX3107 */ 196/* MAX310X */
197#define PORT_MAX3107 94 197#define PORT_MAX310X 94
198 198
199/* High Speed UART for Medfield */ 199/* High Speed UART for Medfield */
200#define PORT_MFD 95 200#define PORT_MFD 95
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 08:50:36 -0500