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-rw-r--r--Documentation/filesystems/proc.txt1
-rw-r--r--Documentation/networking/00-INDEX8
-rw-r--r--Documentation/networking/3c359.txt58
-rw-r--r--Documentation/networking/olympic.txt79
-rw-r--r--Documentation/networking/smctr.txt66
-rw-r--r--Documentation/networking/tms380tr.txt147
-rw-r--r--arch/mips/configs/mtx1_defconfig4
-rw-r--r--arch/xtensa/configs/common_defconfig5
-rw-r--r--drivers/message/fusion/mptlan.h1
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/Space.c46
-rw-r--r--drivers/net/tokenring/3c359.c1831
-rw-r--r--drivers/net/tokenring/3c359.h291
-rw-r--r--drivers/net/tokenring/Kconfig199
-rw-r--r--drivers/net/tokenring/Makefile16
-rw-r--r--drivers/net/tokenring/abyss.c468
-rw-r--r--drivers/net/tokenring/abyss.h58
-rw-r--r--drivers/net/tokenring/ibmtr.c1964
-rw-r--r--drivers/net/tokenring/ibmtr_cs.c370
-rw-r--r--drivers/net/tokenring/lanstreamer.c1909
-rw-r--r--drivers/net/tokenring/lanstreamer.h343
-rw-r--r--drivers/net/tokenring/madgemc.c761
-rw-r--r--drivers/net/tokenring/madgemc.h70
-rw-r--r--drivers/net/tokenring/olympic.c1737
-rw-r--r--drivers/net/tokenring/olympic.h321
-rw-r--r--drivers/net/tokenring/proteon.c422
-rw-r--r--drivers/net/tokenring/skisa.c432
-rw-r--r--drivers/net/tokenring/smctr.c5717
-rw-r--r--drivers/net/tokenring/smctr.h1585
-rw-r--r--drivers/net/tokenring/tms380tr.c2306
-rw-r--r--drivers/net/tokenring/tms380tr.h1141
-rw-r--r--drivers/net/tokenring/tmspci.c236
-rw-r--r--firmware/3com/3C359.bin.ihex1573
-rw-r--r--firmware/Makefile2
-rw-r--r--firmware/WHENCE38
-rw-r--r--firmware/tr_smctr.bin.ihex477
-rw-r--r--include/linux/Kbuild1
-rw-r--r--include/linux/ibmtr.h373
-rw-r--r--include/linux/if_tr.h103
-rw-r--r--include/linux/trdevice.h37
-rw-r--r--net/802/Makefile1
-rw-r--r--net/802/tr.c669
43 files changed, 0 insertions, 25869 deletions
diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
index b7413cb46dcb..ef088e55ab2e 100644
--- a/Documentation/filesystems/proc.txt
+++ b/Documentation/filesystems/proc.txt
@@ -996,7 +996,6 @@ Table 1-9: Network info in /proc/net
996 snmp SNMP data 996 snmp SNMP data
997 sockstat Socket statistics 997 sockstat Socket statistics
998 tcp TCP sockets 998 tcp TCP sockets
999 tr_rif Token ring RIF routing table
1000 udp UDP sockets 999 udp UDP sockets
1001 unix UNIX domain sockets 1000 unix UNIX domain sockets
1002 wireless Wireless interface data (Wavelan etc) 1001 wireless Wireless interface data (Wavelan etc)
diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX
index 9ad9ddeb384c..2cc3c7733a2f 100644
--- a/Documentation/networking/00-INDEX
+++ b/Documentation/networking/00-INDEX
@@ -1,7 +1,5 @@
100-INDEX 100-INDEX
2 - this file 2 - this file
33c359.txt
4 - information on the 3Com TokenLink Velocity XL (3c5359) driver.
53c505.txt 33c505.txt
6 - information on the 3Com EtherLink Plus (3c505) driver. 4 - information on the 3Com EtherLink Plus (3c505) driver.
73c509.txt 53c509.txt
@@ -142,8 +140,6 @@ netif-msg.txt
142 - Design of the network interface message level setting (NETIF_MSG_*). 140 - Design of the network interface message level setting (NETIF_MSG_*).
143nfc.txt 141nfc.txt
144 - The Linux Near Field Communication (NFS) subsystem. 142 - The Linux Near Field Communication (NFS) subsystem.
145olympic.txt
146 - IBM PCI Pit/Pit-Phy/Olympic Token Ring driver info.
147openvswitch.txt 143openvswitch.txt
148 - Open vSwitch developer documentation. 144 - Open vSwitch developer documentation.
149operstates.txt 145operstates.txt
@@ -184,8 +180,6 @@ skfp.txt
184 - SysKonnect FDDI (SK-5xxx, Compaq Netelligent) driver info. 180 - SysKonnect FDDI (SK-5xxx, Compaq Netelligent) driver info.
185smc9.txt 181smc9.txt
186 - the driver for SMC's 9000 series of Ethernet cards 182 - the driver for SMC's 9000 series of Ethernet cards
187smctr.txt
188 - SMC TokenCard TokenRing Linux driver info.
189spider-net.txt 183spider-net.txt
190 - README for the Spidernet Driver (as found in PS3 / Cell BE). 184 - README for the Spidernet Driver (as found in PS3 / Cell BE).
191stmmac.txt 185stmmac.txt
@@ -200,8 +194,6 @@ tcp-thin.txt
200 - kernel tuning options for low rate 'thin' TCP streams. 194 - kernel tuning options for low rate 'thin' TCP streams.
201tlan.txt 195tlan.txt
202 - ThunderLAN (Compaq Netelligent 10/100, Olicom OC-2xxx) driver info. 196 - ThunderLAN (Compaq Netelligent 10/100, Olicom OC-2xxx) driver info.
203tms380tr.txt
204 - SysKonnect Token Ring ISA/PCI adapter driver info.
205tproxy.txt 197tproxy.txt
206 - Transparent proxy support user guide. 198 - Transparent proxy support user guide.
207tuntap.txt 199tuntap.txt
diff --git a/Documentation/networking/3c359.txt b/Documentation/networking/3c359.txt
deleted file mode 100644
index dadfe8147ab8..000000000000
--- a/Documentation/networking/3c359.txt
+++ /dev/null
@@ -1,58 +0,0 @@
1
23COM PCI TOKEN LINK VELOCITY XL TOKEN RING CARDS README
3
4Release 0.9.0 - Release
5 Jul 17th 2000 Mike Phillips
6
7 1.2.0 - Final
8 Feb 17th 2002 Mike Phillips
9 Updated for submission to the 2.4.x kernel.
10
11Thanks:
12 Terry Murphy from 3Com for tech docs and support,
13 Adam D. Ligas for testing the driver.
14
15Note:
16 This driver will NOT work with the 3C339 Token Ring cards, you need
17to use the tms380 driver instead.
18
19Options:
20
21The driver accepts three options: ringspeed, pkt_buf_sz and message_level.
22
23These options can be specified differently for each card found.
24
25ringspeed: Has one of three settings 0 (default), 4 or 16. 0 will
26make the card autosense the ringspeed and join at the appropriate speed,
27this will be the default option for most people. 4 or 16 allow you to
28explicitly force the card to operate at a certain speed. The card will fail
29if you try to insert it at the wrong speed. (Although some hubs will allow
30this so be *very* careful). The main purpose for explicitly setting the ring
31speed is for when the card is first on the ring. In autosense mode, if the card
32cannot detect any active monitors on the ring it will open at the same speed as
33its last opening. This can be hazardous if this speed does not match the speed
34you want the ring to operate at.
35
36pkt_buf_sz: This is this initial receive buffer allocation size. This will
37default to 4096 if no value is entered. You may increase performance of the
38driver by setting this to a value larger than the network packet size, although
39the driver now re-sizes buffers based on MTU settings as well.
40
41message_level: Controls level of messages created by the driver. Defaults to 0:
42which only displays start-up and critical messages. Presently any non-zero
43value will display all soft messages as well. NB This does not turn
44debugging messages on, that must be done by modified the source code.
45
46Variable MTU size:
47
48The driver can handle a MTU size up to either 4500 or 18000 depending upon
49ring speed. The driver also changes the size of the receive buffers as part
50of the mtu re-sizing, so if you set mtu = 18000, you will need to be able
51to allocate 16 * (sk_buff with 18000 buffer size) call it 18500 bytes per ring
52position = 296,000 bytes of memory space, plus of course anything
53necessary for the tx sk_buff's. Remember this is per card, so if you are
54building routers, gateway's etc, you could start to use a lot of memory
55real fast.
56
572/17/02 Mike Phillips
58
diff --git a/Documentation/networking/olympic.txt b/Documentation/networking/olympic.txt
deleted file mode 100644
index b95b5bf96751..000000000000
--- a/Documentation/networking/olympic.txt
+++ /dev/null
@@ -1,79 +0,0 @@
1
2IBM PCI Pit/Pit-Phy/Olympic CHIPSET BASED TOKEN RING CARDS README
3
4Release 0.2.0 - Release
5 June 8th 1999 Peter De Schrijver & Mike Phillips
6Release 0.9.C - Release
7 April 18th 2001 Mike Phillips
8
9Thanks:
10Erik De Cock, Adrian Bridgett and Frank Fiene for their
11patience and testing.
12Donald Champion for the cardbus support
13Kyle Lucke for the dma api changes.
14Jonathon Bitner for hardware support.
15Everybody on linux-tr for their continued support.
16
17Options:
18
19The driver accepts four options: ringspeed, pkt_buf_sz,
20message_level and network_monitor.
21
22These options can be specified differently for each card found.
23
24ringspeed: Has one of three settings 0 (default), 4 or 16. 0 will
25make the card autosense the ringspeed and join at the appropriate speed,
26this will be the default option for most people. 4 or 16 allow you to
27explicitly force the card to operate at a certain speed. The card will fail
28if you try to insert it at the wrong speed. (Although some hubs will allow
29this so be *very* careful). The main purpose for explicitly setting the ring
30speed is for when the card is first on the ring. In autosense mode, if the card
31cannot detect any active monitors on the ring it will not open, so you must
32re-init the card at the appropriate speed. Unfortunately at present the only
33way of doing this is rmmod and insmod which is a bit tough if it is compiled
34in the kernel.
35
36pkt_buf_sz: This is this initial receive buffer allocation size. This will
37default to 4096 if no value is entered. You may increase performance of the
38driver by setting this to a value larger than the network packet size, although
39the driver now re-sizes buffers based on MTU settings as well.
40
41message_level: Controls level of messages created by the driver. Defaults to 0:
42which only displays start-up and critical messages. Presently any non-zero
43value will display all soft messages as well. NB This does not turn
44debugging messages on, that must be done by modified the source code.
45
46network_monitor: Any non-zero value will provide a quasi network monitoring
47mode. All unexpected MAC frames (beaconing etc.) will be received
48by the driver and the source and destination addresses printed.
49Also an entry will be added in /proc/net called olympic_tr%d, where tr%d
50is the registered device name, i.e tr0, tr1, etc. This displays low
51level information about the configuration of the ring and the adapter.
52This feature has been designed for network administrators to assist in
53the diagnosis of network / ring problems. (This used to OLYMPIC_NETWORK_MONITOR,
54but has now changed to allow each adapter to be configured differently and
55to alleviate the necessity to re-compile olympic to turn the option on).
56
57Multi-card:
58
59The driver will detect multiple cards and will work with shared interrupts,
60each card is assigned the next token ring device, i.e. tr0 , tr1, tr2. The
61driver should also happily reside in the system with other drivers. It has
62been tested with ibmtr.c running, and I personally have had one Olicom PCI
63card and two IBM olympic cards (all on the same interrupt), all running
64together.
65
66Variable MTU size:
67
68The driver can handle a MTU size up to either 4500 or 18000 depending upon
69ring speed. The driver also changes the size of the receive buffers as part
70of the mtu re-sizing, so if you set mtu = 18000, you will need to be able
71to allocate 16 * (sk_buff with 18000 buffer size) call it 18500 bytes per ring
72position = 296,000 bytes of memory space, plus of course anything
73necessary for the tx sk_buff's. Remember this is per card, so if you are
74building routers, gateway's etc, you could start to use a lot of memory
75real fast.
76
77
786/8/99 Peter De Schrijver and Mike Phillips
79
diff --git a/Documentation/networking/smctr.txt b/Documentation/networking/smctr.txt
deleted file mode 100644
index 9af25b810c1f..000000000000
--- a/Documentation/networking/smctr.txt
+++ /dev/null
@@ -1,66 +0,0 @@
1Text File for the SMC TokenCard TokenRing Linux driver (smctr.c).
2 By Jay Schulist <jschlst@samba.org>
3
4The Linux SMC Token Ring driver works with the SMC TokenCard Elite (8115T)
5ISA and SMC TokenCard Elite/A (8115T/A) MCA adapters.
6
7Latest information on this driver can be obtained on the Linux-SNA WWW site.
8Please point your browser to: http://www.linux-sna.org
9
10This driver is rather simple to use. Select Y to Token Ring adapter support
11in the kernel configuration. A choice for SMC Token Ring adapters will
12appear. This drives supports all SMC ISA/MCA adapters. Choose this
13option. I personally recommend compiling the driver as a module (M), but if you
14you would like to compile it statically answer Y instead.
15
16This driver supports multiple adapters without the need to load multiple copies
17of the driver. You should be able to load up to 7 adapters without any kernel
18modifications, if you are in need of more please contact the maintainer of this
19driver.
20
21Load the driver either by lilo/loadlin or as a module. When a module using the
22following command will suffice for most:
23
24# modprobe smctr
25smctr.c: v1.00 12/6/99 by jschlst@samba.org
26tr0: SMC TokenCard 8115T at Io 0x300, Irq 10, Rom 0xd8000, Ram 0xcc000.
27
28Now just setup the device via ifconfig and set and routes you may have. After
29this you are ready to start sending some tokens.
30
31Errata:
321). For anyone wondering where to pick up the SMC adapters please browse
33 to http://www.smc.com
34
352). If you are the first/only Token Ring Client on a Token Ring LAN, please
36 specify the ringspeed with the ringspeed=[4/16] module option. If no
37 ringspeed is specified the driver will attempt to autodetect the ring
38 speed and/or if the adapter is the first/only station on the ring take
39 the appropriate actions.
40
41 NOTE: Default ring speed is 16MB UTP.
42
433). PnP support for this adapter sucks. I recommend hard setting the
44 IO/MEM/IRQ by the jumpers on the adapter. If this is not possible
45 load the module with the following io=[ioaddr] mem=[mem_addr]
46 irq=[irq_num].
47
48 The following IRQ, IO, and MEM settings are supported.
49
50 IO ports:
51 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, 0x300,
52 0x320, 0x340, 0x360, 0x380.
53
54 IRQs:
55 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15
56
57 Memory addresses:
58 0xA0000, 0xA4000, 0xA8000, 0xAC000, 0xB0000, 0xB4000,
59 0xB8000, 0xBC000, 0xC0000, 0xC4000, 0xC8000, 0xCC000,
60 0xD0000, 0xD4000, 0xD8000, 0xDC000, 0xE0000, 0xE4000,
61 0xE8000, 0xEC000, 0xF0000, 0xF4000, 0xF8000, 0xFC000
62
63This driver is under the GNU General Public License. Its Firmware image is
64included as an initialized C-array and is licensed by SMC to the Linux
65users of this driver. However no warranty about its fitness is expressed or
66implied by SMC.
diff --git a/Documentation/networking/tms380tr.txt b/Documentation/networking/tms380tr.txt
deleted file mode 100644
index 1f73e13058df..000000000000
--- a/Documentation/networking/tms380tr.txt
+++ /dev/null
@@ -1,147 +0,0 @@
1Text file for the Linux SysKonnect Token Ring ISA/PCI Adapter Driver.
2 Text file by: Jay Schulist <jschlst@samba.org>
3
4The Linux SysKonnect Token Ring driver works with the SysKonnect TR4/16(+) ISA,
5SysKonnect TR4/16(+) PCI, SysKonnect TR4/16 PCI, and older revisions of the
6SK NET TR4/16 ISA card.
7
8Latest information on this driver can be obtained on the Linux-SNA WWW site.
9Please point your browser to:
10http://www.linux-sna.org
11
12Many thanks to Christoph Goos for his excellent work on this driver and
13SysKonnect for donating the adapters to Linux-SNA for the testing and
14maintenance of this device driver.
15
16Important information to be noted:
171. Adapters can be slow to open (~20 secs) and close (~5 secs), please be
18 patient.
192. This driver works very well when autoprobing for adapters. Why even
20 think about those nasty io/int/dma settings of modprobe when the driver
21 will do it all for you!
22
23This driver is rather simple to use. Select Y to Token Ring adapter support
24in the kernel configuration. A choice for SysKonnect Token Ring adapters will
25appear. This drives supports all SysKonnect ISA and PCI adapters. Choose this
26option. I personally recommend compiling the driver as a module (M), but if you
27you would like to compile it statically answer Y instead.
28
29This driver supports multiple adapters without the need to load multiple copies
30of the driver. You should be able to load up to 7 adapters without any kernel
31modifications, if you are in need of more please contact the maintainer of this
32driver.
33
34Load the driver either by lilo/loadlin or as a module. When a module using the
35following command will suffice for most:
36
37# modprobe sktr
38
39This will produce output similar to the following: (Output is user specific)
40
41sktr.c: v1.01 08/29/97 by Christoph Goos
42tr0: SK NET TR 4/16 PCI found at 0x6100, using IRQ 17.
43tr1: SK NET TR 4/16 PCI found at 0x6200, using IRQ 16.
44tr2: SK NET TR 4/16 ISA found at 0xa20, using IRQ 10 and DMA 5.
45
46Now just setup the device via ifconfig and set and routes you may have. After
47this you are ready to start sending some tokens.
48
49Errata:
50For anyone wondering where to pick up the SysKonnect adapters please browse
51to http://www.syskonnect.com
52
53This driver is under the GNU General Public License. Its Firmware image is
54included as an initialized C-array and is licensed by SysKonnect to the Linux
55users of this driver. However no warranty about its fitness is expressed or
56implied by SysKonnect.
57
58Below find attached the setting for the SK NET TR 4/16 ISA adapters
59-------------------------------------------------------------------
60
61 ***************************
62 *** C O N T E N T S ***
63 ***************************
64
65 1) Location of DIP-Switch W1
66 2) Default settings
67 3) DIP-Switch W1 description
68
69
70 ==============================================================
71 CHAPTER 1 LOCATION OF DIP-SWITCH
72 ==============================================================
73
74UÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿
75þUÄÄÄÄÄÄ¿ UÄÄÄÄÄ¿ UÄÄÄ¿ þ
76þAÄÄÄÄÄÄU W1 AÄÄÄÄÄU UÄÄÄÄ¿ þ þ þ
77þUÄÄÄÄÄÄ¿ þ þ þ þ UÄÄÅ¿
78þAÄÄÄÄÄÄU UÄÄÄÄÄÄÄÄÄÄÄ¿ AÄÄÄÄU þ þ þ þþ
79þUÄÄÄÄÄÄ¿ þ þ UÄÄÄ¿ AÄÄÄU AÄÄÅU
80þAÄÄÄÄÄÄU þ TMS380C26 þ þ þ þ
81þUÄÄÄÄÄÄ¿ þ þ AÄÄÄU AÄ¿
82þAÄÄÄÄÄÄU þ þ þ þ
83þ AÄÄÄÄÄÄÄÄÄÄÄU þ þ
84þ þ þ
85þ AÄU
86þ þ
87þ þ
88þ þ
89þ þ
90AÄÄÄÄÄÄÄÄÄÄÄÄAÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄAÄÄAÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄAÄÄÄÄÄÄÄÄÄU
91 AÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄU AÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄU
92
93 ==============================================================
94 CHAPTER 2 DEFAULT SETTINGS
95 ==============================================================
96
97 W1 1 2 3 4 5 6 7 8
98 +------------------------------+
99 | ON X |
100 | OFF X X X X X X X |
101 +------------------------------+
102
103 W1.1 = ON Adapter drives address lines SA17..19
104 W1.2 - 1.5 = OFF BootROM disabled
105 W1.6 - 1.8 = OFF I/O address 0A20h
106
107 ==============================================================
108 CHAPTER 3 DIP SWITCH W1 DESCRIPTION
109 ==============================================================
110
111 UÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄ¿ ON
112 þ 1 þ 2 þ 3 þ 4 þ 5 þ 6 þ 7 þ 8 þ
113 AÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄAÄÄÄU OFF
114 |AD | BootROM Addr. | I/O |
115 +-+-+-------+-------+-----+-----+
116 | | |
117 | | +------ 6 7 8
118 | | ON ON ON 1900h
119 | | ON ON OFF 0900h
120 | | ON OFF ON 1980h
121 | | ON OFF OFF 0980h
122 | | OFF ON ON 1b20h
123 | | OFF ON OFF 0b20h
124 | | OFF OFF ON 1a20h
125 | | OFF OFF OFF 0a20h (+)
126 | |
127 | |
128 | +-------- 2 3 4 5
129 | OFF x x x disabled (+)
130 | ON ON ON ON C0000
131 | ON ON ON OFF C4000
132 | ON ON OFF ON C8000
133 | ON ON OFF OFF CC000
134 | ON OFF ON ON D0000
135 | ON OFF ON OFF D4000
136 | ON OFF OFF ON D8000
137 | ON OFF OFF OFF DC000
138 |
139 |
140 +----- 1
141 OFF adapter does NOT drive SA<17..19>
142 ON adapter drives SA<17..19> (+)
143
144
145 (+) means default setting
146
147 ********************************
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 807c97eed8a8..46c61edcdf7b 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -346,11 +346,8 @@ CONFIG_CHELSIO_T1=m
346CONFIG_IXGB=m 346CONFIG_IXGB=m
347CONFIG_S2IO=m 347CONFIG_S2IO=m
348CONFIG_MYRI10GE=m 348CONFIG_MYRI10GE=m
349CONFIG_TR=y
350CONFIG_IBMOL=m 349CONFIG_IBMOL=m
351CONFIG_IBMLS=m 350CONFIG_IBMLS=m
352CONFIG_3C359=m
353CONFIG_TMS380TR=m
354CONFIG_TMSPCI=m 351CONFIG_TMSPCI=m
355CONFIG_ABYSS=m 352CONFIG_ABYSS=m
356CONFIG_USB_CATC=m 353CONFIG_USB_CATC=m
@@ -376,7 +373,6 @@ CONFIG_PCMCIA_SMC91C92=m
376CONFIG_PCMCIA_XIRC2PS=m 373CONFIG_PCMCIA_XIRC2PS=m
377CONFIG_PCMCIA_AXNET=m 374CONFIG_PCMCIA_AXNET=m
378CONFIG_ARCNET_COM20020_CS=m 375CONFIG_ARCNET_COM20020_CS=m
379CONFIG_PCMCIA_IBMTR=m
380CONFIG_WAN=y 376CONFIG_WAN=y
381CONFIG_LANMEDIA=m 377CONFIG_LANMEDIA=m
382CONFIG_HDLC=m 378CONFIG_HDLC=m
diff --git a/arch/xtensa/configs/common_defconfig b/arch/xtensa/configs/common_defconfig
index b90038e40dd3..a182a4e6d688 100644
--- a/arch/xtensa/configs/common_defconfig
+++ b/arch/xtensa/configs/common_defconfig
@@ -333,11 +333,6 @@ CONFIG_XT2000_SONIC=y
333# CONFIG_S2IO is not set 333# CONFIG_S2IO is not set
334 334
335# 335#
336# Token Ring devices
337#
338# CONFIG_TR is not set
339
340#
341# Wireless LAN (non-hamradio) 336# Wireless LAN (non-hamradio)
342# 337#
343CONFIG_NET_RADIO=y 338CONFIG_NET_RADIO=y
diff --git a/drivers/message/fusion/mptlan.h b/drivers/message/fusion/mptlan.h
index c171afa93239..69e9d5463564 100644
--- a/drivers/message/fusion/mptlan.h
+++ b/drivers/message/fusion/mptlan.h
@@ -69,7 +69,6 @@
69#include <linux/spinlock.h> 69#include <linux/spinlock.h>
70#include <linux/workqueue.h> 70#include <linux/workqueue.h>
71#include <linux/delay.h> 71#include <linux/delay.h>
72// #include <linux/trdevice.h>
73 72
74#include <asm/uaccess.h> 73#include <asm/uaccess.h>
75#include <asm/io.h> 74#include <asm/io.h>
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 78a6259f5c1c..0c2bd806950e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -282,8 +282,6 @@ source "drivers/net/slip/Kconfig"
282 282
283source "drivers/s390/net/Kconfig" 283source "drivers/s390/net/Kconfig"
284 284
285source "drivers/net/tokenring/Kconfig"
286
287source "drivers/net/usb/Kconfig" 285source "drivers/net/usb/Kconfig"
288 286
289source "drivers/net/wireless/Kconfig" 287source "drivers/net/wireless/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a6b8ce11a22f..3d375ca128a6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -50,7 +50,6 @@ obj-$(CONFIG_SLIP) += slip/
50obj-$(CONFIG_SLHC) += slip/ 50obj-$(CONFIG_SLHC) += slip/
51obj-$(CONFIG_NET_SB1000) += sb1000.o 51obj-$(CONFIG_NET_SB1000) += sb1000.o
52obj-$(CONFIG_SUNGEM_PHY) += sungem_phy.o 52obj-$(CONFIG_SUNGEM_PHY) += sungem_phy.o
53obj-$(CONFIG_TR) += tokenring/
54obj-$(CONFIG_WAN) += wan/ 53obj-$(CONFIG_WAN) += wan/
55obj-$(CONFIG_WLAN) += wireless/ 54obj-$(CONFIG_WLAN) += wireless/
56obj-$(CONFIG_WIMAX) += wimax/ 55obj-$(CONFIG_WIMAX) += wimax/
diff --git a/drivers/net/Space.c b/drivers/net/Space.c
index 88bbd8ffa7fe..486e2dc366e0 100644
--- a/drivers/net/Space.c
+++ b/drivers/net/Space.c
@@ -29,7 +29,6 @@
29 */ 29 */
30#include <linux/netdevice.h> 30#include <linux/netdevice.h>
31#include <linux/etherdevice.h> 31#include <linux/etherdevice.h>
32#include <linux/trdevice.h>
33#include <linux/errno.h> 32#include <linux/errno.h>
34#include <linux/init.h> 33#include <linux/init.h>
35#include <linux/netlink.h> 34#include <linux/netlink.h>
@@ -284,46 +283,6 @@ static void __init ethif_probe2(int unit)
284 probe_list2(unit, parport_probes, base_addr == 0)); 283 probe_list2(unit, parport_probes, base_addr == 0));
285} 284}
286 285
287#ifdef CONFIG_TR
288/* Token-ring device probe */
289extern int ibmtr_probe_card(struct net_device *);
290extern struct net_device *smctr_probe(int unit);
291
292static struct devprobe2 tr_probes2[] __initdata = {
293#ifdef CONFIG_SMCTR
294 {smctr_probe, 0},
295#endif
296 {NULL, 0},
297};
298
299static __init int trif_probe(int unit)
300{
301 int err = -ENODEV;
302#ifdef CONFIG_IBMTR
303 struct net_device *dev = alloc_trdev(0);
304 if (!dev)
305 return -ENOMEM;
306
307 sprintf(dev->name, "tr%d", unit);
308 netdev_boot_setup_check(dev);
309 err = ibmtr_probe_card(dev);
310 if (err)
311 free_netdev(dev);
312#endif
313 return err;
314}
315
316static void __init trif_probe2(int unit)
317{
318 unsigned long base_addr = netdev_boot_base("tr", unit);
319
320 if (base_addr == 1)
321 return;
322 probe_list2(unit, tr_probes2, base_addr == 0);
323}
324#endif
325
326
327/* Statically configured drivers -- order matters here. */ 286/* Statically configured drivers -- order matters here. */
328static int __init net_olddevs_init(void) 287static int __init net_olddevs_init(void)
329{ 288{
@@ -333,11 +292,6 @@ static int __init net_olddevs_init(void)
333 for (num = 0; num < 8; ++num) 292 for (num = 0; num < 8; ++num)
334 sbni_probe(num); 293 sbni_probe(num);
335#endif 294#endif
336#ifdef CONFIG_TR
337 for (num = 0; num < 8; ++num)
338 if (!trif_probe(num))
339 trif_probe2(num);
340#endif
341 for (num = 0; num < 8; ++num) 295 for (num = 0; num < 8; ++num)
342 ethif_probe2(num); 296 ethif_probe2(num);
343 297
diff --git a/drivers/net/tokenring/3c359.c b/drivers/net/tokenring/3c359.c
deleted file mode 100644
index 0924f572f59b..000000000000
--- a/drivers/net/tokenring/3c359.c
+++ /dev/null
@@ -1,1831 +0,0 @@
1/*
2 * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 *
4 * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
5 *
6 * Base Driver Olympic:
7 * Written 1999 Peter De Schrijver & Mike Phillips
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
13 *
14 * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
15 * 3/05/01 - Last clean up stuff before submission.
16 * 2/15/01 - Finally, update to new pci api.
17 *
18 * To Do:
19 */
20
21/*
22 * Technical Card Details
23 *
24 * All access to data is done with 16/8 bit transfers. The transfer
25 * method really sucks. You can only read or write one location at a time.
26 *
27 * Also, the microcode for the card must be uploaded if the card does not have
28 * the flashrom on board. This is a 28K bloat in the driver when compiled
29 * as a module.
30 *
31 * Rx is very simple, status into a ring of descriptors, dma data transfer,
32 * interrupts to tell us when a packet is received.
33 *
34 * Tx is a little more interesting. Similar scenario, descriptor and dma data
35 * transfers, but we don't have to interrupt the card to tell it another packet
36 * is ready for transmission, we are just doing simple memory writes, not io or mmio
37 * writes. The card can be set up to simply poll on the next
38 * descriptor pointer and when this value is non-zero will automatically download
39 * the next packet. The card then interrupts us when the packet is done.
40 *
41 */
42
43#define XL_DEBUG 0
44
45#include <linux/jiffies.h>
46#include <linux/module.h>
47#include <linux/kernel.h>
48#include <linux/errno.h>
49#include <linux/timer.h>
50#include <linux/in.h>
51#include <linux/ioport.h>
52#include <linux/string.h>
53#include <linux/proc_fs.h>
54#include <linux/ptrace.h>
55#include <linux/skbuff.h>
56#include <linux/interrupt.h>
57#include <linux/delay.h>
58#include <linux/netdevice.h>
59#include <linux/trdevice.h>
60#include <linux/stddef.h>
61#include <linux/init.h>
62#include <linux/pci.h>
63#include <linux/spinlock.h>
64#include <linux/bitops.h>
65#include <linux/firmware.h>
66#include <linux/slab.h>
67
68#include <net/checksum.h>
69
70#include <asm/io.h>
71
72#include "3c359.h"
73
74static char version[] __devinitdata =
75"3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
76
77#define FW_NAME "3com/3C359.bin"
78MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
79MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver\n") ;
80MODULE_FIRMWARE(FW_NAME);
81
82/* Module parameters */
83
84/* Ring Speed 0,4,16
85 * 0 = Autosense
86 * 4,16 = Selected speed only, no autosense
87 * This allows the card to be the first on the ring
88 * and become the active monitor.
89 *
90 * WARNING: Some hubs will allow you to insert
91 * at the wrong speed.
92 *
93 * The adapter will _not_ fail to open if there are no
94 * active monitors on the ring, it will simply open up in
95 * its last known ringspeed if no ringspeed is specified.
96 */
97
98static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
99
100module_param_array(ringspeed, int, NULL, 0);
101MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
102
103/* Packet buffer size */
104
105static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
106
107module_param_array(pkt_buf_sz, int, NULL, 0) ;
108MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
109/* Message Level */
110
111static int message_level[XL_MAX_ADAPTERS] = {0,} ;
112
113module_param_array(message_level, int, NULL, 0) ;
114MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ;
115/*
116 * This is a real nasty way of doing this, but otherwise you
117 * will be stuck with 1555 lines of hex #'s in the code.
118 */
119
120static DEFINE_PCI_DEVICE_TABLE(xl_pci_tbl) =
121{
122 {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
123 { } /* terminate list */
124};
125MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
126
127static int xl_init(struct net_device *dev);
128static int xl_open(struct net_device *dev);
129static int xl_open_hw(struct net_device *dev) ;
130static int xl_hw_reset(struct net_device *dev);
131static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev);
132static void xl_dn_comp(struct net_device *dev);
133static int xl_close(struct net_device *dev);
134static void xl_set_rx_mode(struct net_device *dev);
135static irqreturn_t xl_interrupt(int irq, void *dev_id);
136static int xl_set_mac_address(struct net_device *dev, void *addr) ;
137static void xl_arb_cmd(struct net_device *dev);
138static void xl_asb_cmd(struct net_device *dev) ;
139static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
140static void xl_wait_misr_flags(struct net_device *dev) ;
141static int xl_change_mtu(struct net_device *dev, int mtu);
142static void xl_srb_bh(struct net_device *dev) ;
143static void xl_asb_bh(struct net_device *dev) ;
144static void xl_reset(struct net_device *dev) ;
145static void xl_freemem(struct net_device *dev) ;
146
147
148/* EEProm Access Functions */
149static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
150static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
151
152/* Debugging functions */
153#if XL_DEBUG
154static void print_tx_state(struct net_device *dev) ;
155static void print_rx_state(struct net_device *dev) ;
156
157static void print_tx_state(struct net_device *dev)
158{
159
160 struct xl_private *xl_priv = netdev_priv(dev);
161 struct xl_tx_desc *txd ;
162 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
163 int i ;
164
165 printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d\n",xl_priv->tx_ring_head,
166 xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
167 printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len\n");
168 for (i = 0; i < 16; i++) {
169 txd = &(xl_priv->xl_tx_ring[i]) ;
170 printk("%d, %08lx, %08x, %08x, %08x, %08x\n", i, virt_to_bus(txd),
171 txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
172 }
173
174 printk("DNLISTPTR = %04x\n", readl(xl_mmio + MMIO_DNLISTPTR) );
175
176 printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL) );
177 printk("Queue status = %0x\n",netif_running(dev) ) ;
178}
179
180static void print_rx_state(struct net_device *dev)
181{
182
183 struct xl_private *xl_priv = netdev_priv(dev);
184 struct xl_rx_desc *rxd ;
185 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
186 int i ;
187
188 printk("rx_ring_tail: %d\n", xl_priv->rx_ring_tail);
189 printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len\n");
190 for (i = 0; i < 16; i++) {
191 /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
192 rxd = &(xl_priv->xl_rx_ring[i]) ;
193 printk("%d, %08lx, %08x, %08x, %08x, %08x\n", i, virt_to_bus(rxd),
194 rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
195 }
196
197 printk("UPLISTPTR = %04x\n", readl(xl_mmio + MMIO_UPLISTPTR));
198
199 printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL));
200 printk("Queue status = %0x\n",netif_running(dev));
201}
202#endif
203
204/*
205 * Read values from the on-board EEProm. This looks very strange
206 * but you have to wait for the EEProm to get/set the value before
207 * passing/getting the next value from the nic. As with all requests
208 * on this nic it has to be done in two stages, a) tell the nic which
209 * memory address you want to access and b) pass/get the value from the nic.
210 * With the EEProm, you have to wait before and between access a) and b).
211 * As this is only read at initialization time and the wait period is very
212 * small we shouldn't have to worry about scheduling issues.
213 */
214
215static u16 xl_ee_read(struct net_device *dev, int ee_addr)
216{
217 struct xl_private *xl_priv = netdev_priv(dev);
218 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
219
220 /* Wait for EEProm to not be busy */
221 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
222 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
223
224 /* Tell EEProm what we want to do and where */
225 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
226 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
227
228 /* Wait for EEProm to not be busy */
229 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
230 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
231
232 /* Tell EEProm what we want to do and where */
233 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
234 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
235
236 /* Finally read the value from the EEProm */
237 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
238 return readw(xl_mmio + MMIO_MACDATA) ;
239}
240
241/*
242 * Write values to the onboard eeprom. As with eeprom read you need to
243 * set which location to write, wait, value to write, wait, with the
244 * added twist of having to enable eeprom writes as well.
245 */
246
247static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
248{
249 struct xl_private *xl_priv = netdev_priv(dev);
250 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
251
252 /* Wait for EEProm to not be busy */
253 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
254 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
255
256 /* Enable write/erase */
257 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
258 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
259
260 /* Wait for EEProm to not be busy */
261 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
262 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
263
264 /* Put the value we want to write into EEDATA */
265 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
266 writew(ee_value, xl_mmio + MMIO_MACDATA) ;
267
268 /* Tell EEProm to write eevalue into ee_addr */
269 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
270 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
271
272 /* Wait for EEProm to not be busy, to ensure write gets done */
273 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
274 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
275
276 return ;
277}
278
279static const struct net_device_ops xl_netdev_ops = {
280 .ndo_open = xl_open,
281 .ndo_stop = xl_close,
282 .ndo_start_xmit = xl_xmit,
283 .ndo_change_mtu = xl_change_mtu,
284 .ndo_set_rx_mode = xl_set_rx_mode,
285 .ndo_set_mac_address = xl_set_mac_address,
286};
287
288static int __devinit xl_probe(struct pci_dev *pdev,
289 const struct pci_device_id *ent)
290{
291 struct net_device *dev ;
292 struct xl_private *xl_priv ;
293 static int card_no = -1 ;
294 int i ;
295
296 card_no++ ;
297
298 if (pci_enable_device(pdev)) {
299 return -ENODEV ;
300 }
301
302 pci_set_master(pdev);
303
304 if ((i = pci_request_regions(pdev,"3c359"))) {
305 return i ;
306 }
307
308 /*
309 * Allowing init_trdev to allocate the private data will align
310 * xl_private on a 32 bytes boundary which we need for the rx/tx
311 * descriptors
312 */
313
314 dev = alloc_trdev(sizeof(struct xl_private)) ;
315 if (!dev) {
316 pci_release_regions(pdev) ;
317 return -ENOMEM ;
318 }
319 xl_priv = netdev_priv(dev);
320
321#if XL_DEBUG
322 printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
323 pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
324#endif
325
326 dev->irq=pdev->irq;
327 dev->base_addr=pci_resource_start(pdev,0) ;
328 xl_priv->xl_card_name = pci_name(pdev);
329 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
330 xl_priv->pdev = pdev ;
331
332 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
333 xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
334 else
335 xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
336
337 dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
338 xl_priv->xl_ring_speed = ringspeed[card_no] ;
339 xl_priv->xl_message_level = message_level[card_no] ;
340 xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
341 xl_priv->xl_copy_all_options = 0 ;
342
343 if((i = xl_init(dev))) {
344 iounmap(xl_priv->xl_mmio) ;
345 free_netdev(dev) ;
346 pci_release_regions(pdev) ;
347 return i ;
348 }
349
350 dev->netdev_ops = &xl_netdev_ops;
351 SET_NETDEV_DEV(dev, &pdev->dev);
352
353 pci_set_drvdata(pdev,dev) ;
354 if ((i = register_netdev(dev))) {
355 printk(KERN_ERR "3C359, register netdev failed\n") ;
356 pci_set_drvdata(pdev,NULL) ;
357 iounmap(xl_priv->xl_mmio) ;
358 free_netdev(dev) ;
359 pci_release_regions(pdev) ;
360 return i ;
361 }
362
363 printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
364
365 return 0;
366}
367
368static int xl_init_firmware(struct xl_private *xl_priv)
369{
370 int err;
371
372 err = request_firmware(&xl_priv->fw, FW_NAME, &xl_priv->pdev->dev);
373 if (err) {
374 printk(KERN_ERR "Failed to load firmware \"%s\"\n", FW_NAME);
375 return err;
376 }
377
378 if (xl_priv->fw->size < 16) {
379 printk(KERN_ERR "Bogus length %zu in \"%s\"\n",
380 xl_priv->fw->size, FW_NAME);
381 release_firmware(xl_priv->fw);
382 err = -EINVAL;
383 }
384
385 return err;
386}
387
388static int __devinit xl_init(struct net_device *dev)
389{
390 struct xl_private *xl_priv = netdev_priv(dev);
391 int err;
392
393 printk(KERN_INFO "%s\n", version);
394 printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
395 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
396
397 spin_lock_init(&xl_priv->xl_lock) ;
398
399 err = xl_init_firmware(xl_priv);
400 if (err == 0)
401 err = xl_hw_reset(dev);
402
403 return err;
404}
405
406
407/*
408 * Hardware reset. This needs to be a separate entity as we need to reset the card
409 * when we change the EEProm settings.
410 */
411
412static int xl_hw_reset(struct net_device *dev)
413{
414 struct xl_private *xl_priv = netdev_priv(dev);
415 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
416 unsigned long t ;
417 u16 i ;
418 u16 result_16 ;
419 u8 result_8 ;
420 u16 start ;
421 int j ;
422
423 if (xl_priv->fw == NULL)
424 return -EINVAL;
425
426 /*
427 * Reset the card. If the card has got the microcode on board, we have
428 * missed the initialization interrupt, so we must always do this.
429 */
430
431 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
432
433 /*
434 * Must wait for cmdInProgress bit (12) to clear before continuing with
435 * card configuration.
436 */
437
438 t=jiffies;
439 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
440 schedule();
441 if (time_after(jiffies, t + 40 * HZ)) {
442 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
443 return -ENODEV;
444 }
445 }
446
447 /*
448 * Enable pmbar by setting bit in CPAttention
449 */
450
451 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
452 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
453 result_8 = result_8 | CPA_PMBARVIS ;
454 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
455 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
456
457 /*
458 * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
459 * If not, we need to upload the microcode to the card
460 */
461
462 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
463
464#if XL_DEBUG
465 printk(KERN_INFO "Read from PMBAR = %04x\n", readw(xl_mmio + MMIO_MACDATA));
466#endif
467
468 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
469
470 /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
471
472 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
473 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
474 result_16 = result_16 & ~((0x7F) << 2) ;
475 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
476 writew(result_16,xl_mmio + MMIO_MACDATA) ;
477
478 /* Set CPAttention, memWrEn bit */
479
480 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
481 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
482 result_8 = result_8 | CPA_MEMWREN ;
483 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
484 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
485
486 /*
487 * Now to write the microcode into the shared ram
488 * The microcode must finish at position 0xFFFF,
489 * so we must subtract to get the start position for the code
490 *
491 * Looks strange but ensures compiler only uses
492 * 16 bit unsigned int
493 */
494 start = (0xFFFF - (xl_priv->fw->size) + 1) ;
495
496 printk(KERN_INFO "3C359: Uploading Microcode: ");
497
498 for (i = start, j = 0; j < xl_priv->fw->size; i++, j++) {
499 writel(MEM_BYTE_WRITE | 0XD0000 | i,
500 xl_mmio + MMIO_MAC_ACCESS_CMD);
501 writeb(xl_priv->fw->data[j], xl_mmio + MMIO_MACDATA);
502 if (j % 1024 == 0)
503 printk(".");
504 }
505 printk("\n") ;
506
507 for (i = 0; i < 16; i++) {
508 writel((MEM_BYTE_WRITE | 0xDFFF0) + i,
509 xl_mmio + MMIO_MAC_ACCESS_CMD);
510 writeb(xl_priv->fw->data[xl_priv->fw->size - 16 + i],
511 xl_mmio + MMIO_MACDATA);
512 }
513
514 /*
515 * Have to write the start address of the upload to FFF4, but
516 * the address must be >> 4. You do not want to know how long
517 * it took me to discover this.
518 */
519
520 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
521 writew(start >> 4, xl_mmio + MMIO_MACDATA);
522
523 /* Clear the CPAttention, memWrEn Bit */
524
525 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
526 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
527 result_8 = result_8 & ~CPA_MEMWREN ;
528 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
529 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
530
531 /* Clear the cpHold bit in pmbar */
532
533 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
534 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
535 result_16 = result_16 & ~PMB_CPHOLD ;
536 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
537 writew(result_16,xl_mmio + MMIO_MACDATA) ;
538
539
540 } /* If microcode upload required */
541
542 /*
543 * The card should now go though a self test procedure and get itself ready
544 * to be opened, we must wait for an srb response with the initialization
545 * information.
546 */
547
548#if XL_DEBUG
549 printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
550#endif
551
552 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
553
554 t=jiffies;
555 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
556 schedule();
557 if (time_after(jiffies, t + 15 * HZ)) {
558 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
559 return -ENODEV;
560 }
561 }
562
563 /*
564 * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
565 * DnPriReqThresh, read the tech docs if you want to know what
566 * values they need to be.
567 */
568
569 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
570 writew(0xD000, xl_mmio + MMIO_MACDATA) ;
571
572 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
573 writew(0X0020, xl_mmio + MMIO_MACDATA) ;
574
575 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
576
577 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
578 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
579
580 /*
581 * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
582 * Tech docs have this wrong !!!!
583 */
584
585 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
586 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
587 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
588 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
589
590#if XL_DEBUG
591 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
592 if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
593 printk(KERN_INFO "Default ring speed 4 mbps\n");
594 } else {
595 printk(KERN_INFO "Default ring speed 16 mbps\n");
596 }
597 printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
598#endif
599
600 return 0;
601}
602
603static int xl_open(struct net_device *dev)
604{
605 struct xl_private *xl_priv=netdev_priv(dev);
606 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
607 u8 i ;
608 __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
609 int open_err ;
610
611 u16 switchsettings, switchsettings_eeprom ;
612
613 if (request_irq(dev->irq, xl_interrupt, IRQF_SHARED , "3c359", dev))
614 return -EAGAIN;
615
616 /*
617 * Read the information from the EEPROM that we need.
618 */
619
620 hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10));
621 hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11));
622 hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12));
623
624 /* Ring speed */
625
626 switchsettings_eeprom = xl_ee_read(dev,0x08) ;
627 switchsettings = switchsettings_eeprom ;
628
629 if (xl_priv->xl_ring_speed != 0) {
630 if (xl_priv->xl_ring_speed == 4)
631 switchsettings = switchsettings | 0x02 ;
632 else
633 switchsettings = switchsettings & ~0x02 ;
634 }
635
636 /* Only write EEProm if there has been a change */
637 if (switchsettings != switchsettings_eeprom) {
638 xl_ee_write(dev,0x08,switchsettings) ;
639 /* Hardware reset after changing EEProm */
640 xl_hw_reset(dev) ;
641 }
642
643 memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
644
645 open_err = xl_open_hw(dev) ;
646
647 /*
648 * This really needs to be cleaned up with better error reporting.
649 */
650
651 if (open_err != 0) { /* Something went wrong with the open command */
652 if (open_err & 0x07) { /* Wrong speed, retry at different speed */
653 printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed\n", dev->name);
654 switchsettings = switchsettings ^ 2 ;
655 xl_ee_write(dev,0x08,switchsettings) ;
656 xl_hw_reset(dev) ;
657 open_err = xl_open_hw(dev) ;
658 if (open_err != 0) {
659 printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
660 free_irq(dev->irq,dev) ;
661 return -ENODEV ;
662 }
663 } else {
664 printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
665 free_irq(dev->irq,dev) ;
666 return -ENODEV ;
667 }
668 }
669
670 /*
671 * Now to set up the Rx and Tx buffer structures
672 */
673 /* These MUST be on 8 byte boundaries */
674 xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
675 if (xl_priv->xl_tx_ring == NULL) {
676 free_irq(dev->irq,dev);
677 return -ENOMEM;
678 }
679 xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
680 if (xl_priv->xl_rx_ring == NULL) {
681 free_irq(dev->irq,dev);
682 kfree(xl_priv->xl_tx_ring);
683 return -ENOMEM;
684 }
685
686 /* Setup Rx Ring */
687 for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
688 struct sk_buff *skb ;
689
690 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
691 if (skb==NULL)
692 break ;
693
694 skb->dev = dev ;
695 xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
696 xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
697 xl_priv->rx_ring_skb[i] = skb ;
698 }
699
700 if (i==0) {
701 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n",dev->name);
702 free_irq(dev->irq,dev) ;
703 kfree(xl_priv->xl_tx_ring);
704 kfree(xl_priv->xl_rx_ring);
705 return -EIO ;
706 }
707
708 xl_priv->rx_ring_no = i ;
709 xl_priv->rx_ring_tail = 0 ;
710 xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
711 for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
712 xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)));
713 }
714 xl_priv->xl_rx_ring[i].upnextptr = 0 ;
715
716 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
717
718 /* Setup Tx Ring */
719
720 xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
721
722 xl_priv->tx_ring_head = 1 ;
723 xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
724 xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
725
726 /*
727 * Setup the first dummy DPD entry for polling to start working.
728 */
729
730 xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY;
731 xl_priv->xl_tx_ring[0].buffer = 0 ;
732 xl_priv->xl_tx_ring[0].buffer_length = 0 ;
733 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
734
735 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
736 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
737 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
738 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
739 writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
740
741 /*
742 * Enable interrupts on the card
743 */
744
745 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
746 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
747
748 netif_start_queue(dev) ;
749 return 0;
750
751}
752
753static int xl_open_hw(struct net_device *dev)
754{
755 struct xl_private *xl_priv=netdev_priv(dev);
756 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
757 u16 vsoff ;
758 char ver_str[33];
759 int open_err ;
760 int i ;
761 unsigned long t ;
762
763 /*
764 * Okay, let's build up the Open.NIC srb command
765 *
766 */
767
768 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
769 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
770
771 /*
772 * Use this as a test byte, if it comes back with the same value, the command didn't work
773 */
774
775 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
776 writeb(0xff,xl_mmio + MMIO_MACDATA) ;
777
778 /* Open options */
779 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
780 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
781 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
782 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
783
784 /*
785 * Node address, be careful here, the docs say you can just put zeros here and it will use
786 * the hardware address, it doesn't, you must include the node address in the open command.
787 */
788
789 if (xl_priv->xl_laa[0]) { /* If using a LAA address */
790 for (i=10;i<16;i++) {
791 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
792 writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
793 }
794 memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
795 } else { /* Regular hardware address */
796 for (i=10;i<16;i++) {
797 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
798 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
799 }
800 }
801
802 /* Default everything else to 0 */
803 for (i = 16; i < 34; i++) {
804 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
805 writeb(0x00,xl_mmio + MMIO_MACDATA) ;
806 }
807
808 /*
809 * Set the csrb bit in the MISR register
810 */
811
812 xl_wait_misr_flags(dev) ;
813 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
814 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
815 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
816 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
817
818 /*
819 * Now wait for the command to run
820 */
821
822 t=jiffies;
823 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
824 schedule();
825 if (time_after(jiffies, t + 40 * HZ)) {
826 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
827 break ;
828 }
829 }
830
831 /*
832 * Let's interpret the open response
833 */
834
835 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
836 if (readb(xl_mmio + MMIO_MACDATA)!=0) {
837 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
838 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
839 open_err |= readb(xl_mmio + MMIO_MACDATA) ;
840 return open_err ;
841 } else {
842 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
843 xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
844 printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
845 printk("ASB: %04x",xl_priv->asb ) ;
846 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
847 printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
848
849 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
850 xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
851 printk(", ARB: %04x\n",xl_priv->arb );
852 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
853 vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
854
855 /*
856 * Interesting, sending the individual characters directly to printk was causing klogd to use
857 * use 100% of processor time, so we build up the string and print that instead.
858 */
859
860 for (i=0;i<0x20;i++) {
861 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
862 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
863 }
864 ver_str[i] = '\0' ;
865 printk(KERN_INFO "%s: Microcode version String: %s\n",dev->name,ver_str);
866 }
867
868 /*
869 * Issue the AckInterrupt
870 */
871 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
872
873 return 0 ;
874}
875
876/*
877 * There are two ways of implementing rx on the 359 NIC, either
878 * interrupt driven or polling. We are going to uses interrupts,
879 * it is the easier way of doing things.
880 *
881 * The Rx works with a ring of Rx descriptors. At initialise time the ring
882 * entries point to the next entry except for the last entry in the ring
883 * which points to 0. The card is programmed with the location of the first
884 * available descriptor and keeps reading the next_ptr until next_ptr is set
885 * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
886 * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
887 * and then point the end of the ring to our current position and point our current
888 * position to 0, therefore making the current position the last position on the ring.
889 * The last position on the ring therefore loops continually loops around the rx ring.
890 *
891 * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
892 * expands as the card adds new packets and we go around eating the tail processing the
893 * packets.)
894 *
895 * Undoubtably it could be streamlined and improved upon, but at the moment it works
896 * and the fast path through the routine is fine.
897 *
898 * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
899 * in xl_rx so would increase the size of the function significantly.
900 */
901
902static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
903{
904 struct xl_private *xl_priv=netdev_priv(dev);
905 int n = xl_priv->rx_ring_tail;
906 int prev_ring_loc;
907
908 prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
909 xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n));
910 xl_priv->xl_rx_ring[n].framestatus = 0;
911 xl_priv->xl_rx_ring[n].upnextptr = 0;
912 xl_priv->rx_ring_tail++;
913 xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1);
914}
915
916static void xl_rx(struct net_device *dev)
917{
918 struct xl_private *xl_priv=netdev_priv(dev);
919 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
920 struct sk_buff *skb, *skb2 ;
921 int frame_length = 0, copy_len = 0 ;
922 int temp_ring_loc ;
923
924 /*
925 * Receive the next frame, loop around the ring until all frames
926 * have been received.
927 */
928
929 while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
930
931 if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
932
933 /*
934 * This is a pain, you need to go through all the descriptors until the last one
935 * for this frame to find the framelength
936 */
937
938 temp_ring_loc = xl_priv->rx_ring_tail ;
939
940 while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
941 temp_ring_loc++ ;
942 temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
943 }
944
945 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF;
946
947 skb = dev_alloc_skb(frame_length) ;
948
949 if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
950 printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
951 while (xl_priv->rx_ring_tail != temp_ring_loc)
952 adv_rx_ring(dev) ;
953
954 adv_rx_ring(dev) ; /* One more time just for luck :) */
955 dev->stats.rx_dropped++ ;
956
957 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
958 return ;
959 }
960
961 while (xl_priv->rx_ring_tail != temp_ring_loc) {
962 copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF;
963 frame_length -= copy_len ;
964 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
965 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
966 skb_put(skb, copy_len),
967 copy_len);
968 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
969 adv_rx_ring(dev) ;
970 }
971
972 /* Now we have found the last fragment */
973 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
974 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
975 skb_put(skb,copy_len), frame_length);
976/* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
977 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
978 adv_rx_ring(dev) ;
979 skb->protocol = tr_type_trans(skb,dev) ;
980 netif_rx(skb) ;
981
982 } else { /* Single Descriptor Used, simply swap buffers over, fast path */
983
984 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF;
985
986 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
987
988 if (skb==NULL) { /* Still need to fix the rx ring */
989 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer\n",dev->name);
990 adv_rx_ring(dev) ;
991 dev->stats.rx_dropped++ ;
992 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
993 return ;
994 }
995
996 skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
997 pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
998 skb_put(skb2, frame_length) ;
999 skb2->protocol = tr_type_trans(skb2,dev) ;
1000
1001 xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
1002 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
1003 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
1004 adv_rx_ring(dev) ;
1005 dev->stats.rx_packets++ ;
1006 dev->stats.rx_bytes += frame_length ;
1007
1008 netif_rx(skb2) ;
1009 } /* if multiple buffers */
1010 } /* while packet to do */
1011
1012 /* Clear the updComplete interrupt */
1013 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1014 return ;
1015}
1016
1017/*
1018 * This is ruthless, it doesn't care what state the card is in it will
1019 * completely reset the adapter.
1020 */
1021
1022static void xl_reset(struct net_device *dev)
1023{
1024 struct xl_private *xl_priv=netdev_priv(dev);
1025 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1026 unsigned long t;
1027
1028 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1029
1030 /*
1031 * Must wait for cmdInProgress bit (12) to clear before continuing with
1032 * card configuration.
1033 */
1034
1035 t=jiffies;
1036 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1037 if (time_after(jiffies, t + 40 * HZ)) {
1038 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
1039 break ;
1040 }
1041 }
1042
1043}
1044
1045static void xl_freemem(struct net_device *dev)
1046{
1047 struct xl_private *xl_priv=netdev_priv(dev);
1048 int i ;
1049
1050 for (i=0;i<XL_RX_RING_SIZE;i++) {
1051 dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
1052 pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
1053 xl_priv->rx_ring_tail++ ;
1054 xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
1055 }
1056
1057 /* unmap ring */
1058 pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
1059
1060 pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
1061
1062 kfree(xl_priv->xl_rx_ring) ;
1063 kfree(xl_priv->xl_tx_ring) ;
1064
1065 return ;
1066}
1067
1068static irqreturn_t xl_interrupt(int irq, void *dev_id)
1069{
1070 struct net_device *dev = (struct net_device *)dev_id;
1071 struct xl_private *xl_priv =netdev_priv(dev);
1072 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1073 u16 intstatus, macstatus ;
1074
1075 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
1076
1077 if (!(intstatus & 1)) /* We didn't generate the interrupt */
1078 return IRQ_NONE;
1079
1080 spin_lock(&xl_priv->xl_lock) ;
1081
1082 /*
1083 * Process the interrupt
1084 */
1085 /*
1086 * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
1087 */
1088 if (intstatus == 0x0001) {
1089 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1090 printk(KERN_INFO "%s: 00001 int received\n",dev->name);
1091 } else {
1092 if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
1093
1094 /*
1095 * Host Error.
1096 * It may be possible to recover from this, but usually it means something
1097 * is seriously fubar, so we just close the adapter.
1098 */
1099
1100 if (intstatus & HOSTERRINT) {
1101 printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x\n",dev->name,intstatus);
1102 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1103 printk(KERN_WARNING "%s: Resetting hardware:\n", dev->name);
1104 netif_stop_queue(dev) ;
1105 xl_freemem(dev) ;
1106 free_irq(dev->irq,dev);
1107 xl_reset(dev) ;
1108 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1109 spin_unlock(&xl_priv->xl_lock) ;
1110 return IRQ_HANDLED;
1111 } /* Host Error */
1112
1113 if (intstatus & SRBRINT ) { /* Srbc interrupt */
1114 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1115 if (xl_priv->srb_queued)
1116 xl_srb_bh(dev) ;
1117 } /* SRBR Interrupt */
1118
1119 if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
1120 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1121 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
1122 /* !!! FIX-ME !!!!
1123 Must put a timeout check here ! */
1124 /* Empty Loop */
1125 }
1126 printk(KERN_WARNING "%s: TX Underrun received\n",dev->name);
1127 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1128 } /* TxUnderRun */
1129
1130 if (intstatus & ARBCINT ) { /* Arbc interrupt */
1131 xl_arb_cmd(dev) ;
1132 } /* Arbc */
1133
1134 if (intstatus & ASBFINT) {
1135 if (xl_priv->asb_queued == 1) {
1136 xl_asb_cmd(dev) ;
1137 } else if (xl_priv->asb_queued == 2) {
1138 xl_asb_bh(dev) ;
1139 } else {
1140 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1141 }
1142 } /* Asbf */
1143
1144 if (intstatus & UPCOMPINT ) /* UpComplete */
1145 xl_rx(dev) ;
1146
1147 if (intstatus & DNCOMPINT ) /* DnComplete */
1148 xl_dn_comp(dev) ;
1149
1150 if (intstatus & HARDERRINT ) { /* Hardware error */
1151 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1152 macstatus = readw(xl_mmio + MMIO_MACDATA) ;
1153 printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
1154 if (macstatus & (1<<14))
1155 printk(KERN_WARNING "tchk error: Unrecoverable error\n");
1156 if (macstatus & (1<<3))
1157 printk(KERN_WARNING "eint error: Internal watchdog timer expired\n");
1158 if (macstatus & (1<<2))
1159 printk(KERN_WARNING "aint error: Host tried to perform invalid operation\n");
1160 printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
1161 printk(KERN_WARNING "%s: Resetting hardware:\n", dev->name);
1162 netif_stop_queue(dev) ;
1163 xl_freemem(dev) ;
1164 free_irq(dev->irq,dev);
1165 unregister_netdev(dev) ;
1166 free_netdev(dev) ;
1167 xl_reset(dev) ;
1168 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1169 spin_unlock(&xl_priv->xl_lock) ;
1170 return IRQ_HANDLED;
1171 }
1172 } else {
1173 printk(KERN_WARNING "%s: Received Unknown interrupt : %04x\n", dev->name, intstatus);
1174 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1175 }
1176 }
1177
1178 /* Turn interrupts back on */
1179
1180 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1181 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1182
1183 spin_unlock(&xl_priv->xl_lock) ;
1184 return IRQ_HANDLED;
1185}
1186
1187/*
1188 * Tx - Polling configuration
1189 */
1190
1191static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev)
1192{
1193 struct xl_private *xl_priv=netdev_priv(dev);
1194 struct xl_tx_desc *txd ;
1195 int tx_head, tx_tail, tx_prev ;
1196 unsigned long flags ;
1197
1198 spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
1199
1200 netif_stop_queue(dev) ;
1201
1202 if (xl_priv->free_ring_entries > 1 ) {
1203 /*
1204 * Set up the descriptor for the packet
1205 */
1206 tx_head = xl_priv->tx_ring_head ;
1207 tx_tail = xl_priv->tx_ring_tail ;
1208
1209 txd = &(xl_priv->xl_tx_ring[tx_head]) ;
1210 txd->dnnextptr = 0 ;
1211 txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE;
1212 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
1213 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
1214 xl_priv->tx_ring_skb[tx_head] = skb ;
1215 dev->stats.tx_packets++ ;
1216 dev->stats.tx_bytes += skb->len ;
1217
1218 /*
1219 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
1220 * to ensure no negative numbers in unsigned locations.
1221 */
1222
1223 tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
1224
1225 xl_priv->tx_ring_head++ ;
1226 xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
1227 xl_priv->free_ring_entries-- ;
1228
1229 xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head));
1230
1231 /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
1232 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
1233
1234 netif_wake_queue(dev) ;
1235
1236 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1237
1238 return NETDEV_TX_OK;
1239 } else {
1240 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1241 return NETDEV_TX_BUSY;
1242 }
1243
1244}
1245
1246/*
1247 * The NIC has told us that a packet has been downloaded onto the card, we must
1248 * find out which packet it has done, clear the skb and information for the packet
1249 * then advance around the ring for all transmitted packets
1250 */
1251
1252static void xl_dn_comp(struct net_device *dev)
1253{
1254 struct xl_private *xl_priv=netdev_priv(dev);
1255 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1256 struct xl_tx_desc *txd ;
1257
1258
1259 if (xl_priv->tx_ring_tail == 255) {/* First time */
1260 xl_priv->xl_tx_ring[0].framestartheader = 0 ;
1261 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
1262 xl_priv->tx_ring_tail = 1 ;
1263 }
1264
1265 while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
1266 txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
1267 pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE);
1268 txd->framestartheader = 0 ;
1269 txd->buffer = cpu_to_le32(0xdeadbeef);
1270 txd->buffer_length = 0 ;
1271 dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
1272 xl_priv->tx_ring_tail++ ;
1273 xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
1274 xl_priv->free_ring_entries++ ;
1275 }
1276
1277 netif_wake_queue(dev) ;
1278
1279 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1280}
1281
1282/*
1283 * Close the adapter properly.
1284 * This srb reply cannot be handled from interrupt context as we have
1285 * to free the interrupt from the driver.
1286 */
1287
1288static int xl_close(struct net_device *dev)
1289{
1290 struct xl_private *xl_priv = netdev_priv(dev);
1291 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1292 unsigned long t ;
1293
1294 netif_stop_queue(dev) ;
1295
1296 /*
1297 * Close the adapter, need to stall the rx and tx queues.
1298 */
1299
1300 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
1301 t=jiffies;
1302 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1303 schedule();
1304 if (time_after(jiffies, t + 10 * HZ)) {
1305 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
1306 break ;
1307 }
1308 }
1309 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
1310 t=jiffies;
1311 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1312 schedule();
1313 if (time_after(jiffies, t + 10 * HZ)) {
1314 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
1315 break ;
1316 }
1317 }
1318 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
1319 t=jiffies;
1320 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1321 schedule();
1322 if (time_after(jiffies, t + 10 * HZ)) {
1323 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
1324 break ;
1325 }
1326 }
1327
1328 /* Turn off interrupts, we will still get the indication though
1329 * so we can trap it
1330 */
1331
1332 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
1333
1334 xl_srb_cmd(dev,CLOSE_NIC) ;
1335
1336 t=jiffies;
1337 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
1338 schedule();
1339 if (time_after(jiffies, t + 10 * HZ)) {
1340 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
1341 break ;
1342 }
1343 }
1344 /* Read the srb response from the adapter */
1345
1346 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
1347 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
1348 printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response\n",dev->name);
1349 } else {
1350 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1351 if (readb(xl_mmio + MMIO_MACDATA)==0) {
1352 printk(KERN_INFO "%s: Adapter has been closed\n",dev->name);
1353 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1354
1355 xl_freemem(dev) ;
1356 free_irq(dev->irq,dev) ;
1357 } else {
1358 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
1359 }
1360 }
1361
1362 /* Reset the upload and download logic */
1363
1364 writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
1365 t=jiffies;
1366 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1367 schedule();
1368 if (time_after(jiffies, t + 10 * HZ)) {
1369 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
1370 break ;
1371 }
1372 }
1373 writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
1374 t=jiffies;
1375 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1376 schedule();
1377 if (time_after(jiffies, t + 10 * HZ)) {
1378 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
1379 break ;
1380 }
1381 }
1382 xl_hw_reset(dev) ;
1383 return 0 ;
1384}
1385
1386static void xl_set_rx_mode(struct net_device *dev)
1387{
1388 struct xl_private *xl_priv = netdev_priv(dev);
1389 struct netdev_hw_addr *ha;
1390 unsigned char dev_mc_address[4] ;
1391 u16 options ;
1392
1393 if (dev->flags & IFF_PROMISC)
1394 options = 0x0004 ;
1395 else
1396 options = 0x0000 ;
1397
1398 if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
1399 xl_priv->xl_copy_all_options = options ;
1400 xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
1401 return ;
1402 }
1403
1404 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1405
1406 netdev_for_each_mc_addr(ha, dev) {
1407 dev_mc_address[0] |= ha->addr[2];
1408 dev_mc_address[1] |= ha->addr[3];
1409 dev_mc_address[2] |= ha->addr[4];
1410 dev_mc_address[3] |= ha->addr[5];
1411 }
1412
1413 if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
1414 memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
1415 xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
1416 }
1417 return ;
1418}
1419
1420
1421/*
1422 * We issued an srb command and now we must read
1423 * the response from the completed command.
1424 */
1425
1426static void xl_srb_bh(struct net_device *dev)
1427{
1428 struct xl_private *xl_priv = netdev_priv(dev);
1429 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1430 u8 srb_cmd, ret_code ;
1431 int i ;
1432
1433 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1434 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1435 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1436 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1437
1438 /* Ret_code is standard across all commands */
1439
1440 switch (ret_code) {
1441 case 1:
1442 printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
1443 break ;
1444 case 4:
1445 printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command\n",dev->name,srb_cmd);
1446 break ;
1447
1448 case 6:
1449 printk(KERN_INFO "%s: Command: %d - Options Invalid for command\n",dev->name,srb_cmd);
1450 break ;
1451
1452 case 0: /* Successful command execution */
1453 switch (srb_cmd) {
1454 case READ_LOG: /* Returns 14 bytes of data from the NIC */
1455 if(xl_priv->xl_message_level)
1456 printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
1457 /*
1458 * We still have to read the log even if message_level = 0 and we don't want
1459 * to see it
1460 */
1461 for (i=0;i<14;i++) {
1462 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1463 if(xl_priv->xl_message_level)
1464 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
1465 }
1466 printk("\n") ;
1467 break ;
1468 case SET_FUNC_ADDRESS:
1469 if(xl_priv->xl_message_level)
1470 printk(KERN_INFO "%s: Functional Address Set\n",dev->name);
1471 break ;
1472 case CLOSE_NIC:
1473 if(xl_priv->xl_message_level)
1474 printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler\n",dev->name);
1475 break ;
1476 case SET_MULTICAST_MODE:
1477 if(xl_priv->xl_message_level)
1478 printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
1479 break ;
1480 case SET_RECEIVE_MODE:
1481 if(xl_priv->xl_message_level) {
1482 if (xl_priv->xl_copy_all_options == 0x0004)
1483 printk(KERN_INFO "%s: Entering promiscuous mode\n", dev->name);
1484 else
1485 printk(KERN_INFO "%s: Entering normal receive mode\n",dev->name);
1486 }
1487 break ;
1488
1489 } /* switch */
1490 break ;
1491 } /* switch */
1492 return ;
1493}
1494
1495static int xl_set_mac_address (struct net_device *dev, void *addr)
1496{
1497 struct sockaddr *saddr = addr ;
1498 struct xl_private *xl_priv = netdev_priv(dev);
1499
1500 if (netif_running(dev)) {
1501 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
1502 return -EIO ;
1503 }
1504
1505 memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
1506
1507 if (xl_priv->xl_message_level) {
1508 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
1509 xl_priv->xl_laa[1], xl_priv->xl_laa[2],
1510 xl_priv->xl_laa[3], xl_priv->xl_laa[4],
1511 xl_priv->xl_laa[5]);
1512 }
1513
1514 return 0 ;
1515}
1516
1517static void xl_arb_cmd(struct net_device *dev)
1518{
1519 struct xl_private *xl_priv = netdev_priv(dev);
1520 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1521 u8 arb_cmd ;
1522 u16 lan_status, lan_status_diff ;
1523
1524 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1525 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1526
1527 if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
1528 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1529
1530 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
1531
1532 lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
1533
1534 /* Acknowledge interrupt, this tells nic we are done with the arb */
1535 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1536
1537 lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
1538
1539 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
1540 if (lan_status_diff & LSC_LWF)
1541 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
1542 if (lan_status_diff & LSC_ARW)
1543 printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
1544 if (lan_status_diff & LSC_FPE)
1545 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
1546 if (lan_status_diff & LSC_RR)
1547 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
1548
1549 /* Adapter has been closed by the hardware */
1550
1551 netif_stop_queue(dev);
1552 xl_freemem(dev) ;
1553 free_irq(dev->irq,dev);
1554
1555 printk(KERN_WARNING "%s: Adapter has been closed\n", dev->name);
1556 } /* If serious error */
1557
1558 if (xl_priv->xl_message_level) {
1559 if (lan_status_diff & LSC_SIG_LOSS)
1560 printk(KERN_WARNING "%s: No receive signal detected\n", dev->name);
1561 if (lan_status_diff & LSC_HARD_ERR)
1562 printk(KERN_INFO "%s: Beaconing\n",dev->name);
1563 if (lan_status_diff & LSC_SOFT_ERR)
1564 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame\n",dev->name);
1565 if (lan_status_diff & LSC_TRAN_BCN)
1566 printk(KERN_INFO "%s: We are transmitting the beacon, aaah\n",dev->name);
1567 if (lan_status_diff & LSC_SS)
1568 printk(KERN_INFO "%s: Single Station on the ring\n", dev->name);
1569 if (lan_status_diff & LSC_RING_REC)
1570 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
1571 if (lan_status_diff & LSC_FDX_MODE)
1572 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
1573 }
1574
1575 if (lan_status_diff & LSC_CO) {
1576 if (xl_priv->xl_message_level)
1577 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
1578 /* Issue READ.LOG command */
1579 xl_srb_cmd(dev, READ_LOG) ;
1580 }
1581
1582 /* There is no command in the tech docs to issue the read_sr_counters */
1583 if (lan_status_diff & LSC_SR_CO) {
1584 if (xl_priv->xl_message_level)
1585 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1586 }
1587
1588 xl_priv->xl_lan_status = lan_status ;
1589
1590 } /* Lan.change.status */
1591 else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
1592#if XL_DEBUG
1593 printk(KERN_INFO "Received.Data\n");
1594#endif
1595 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1596 xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
1597
1598 /* Now we are going to be really basic here and not do anything
1599 * with the data at all. The tech docs do not give me enough
1600 * information to calculate the buffers properly so we're
1601 * just going to tell the nic that we've dealt with the frame
1602 * anyway.
1603 */
1604
1605 /* Acknowledge interrupt, this tells nic we are done with the arb */
1606 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1607
1608 /* Is the ASB free ? */
1609
1610 xl_priv->asb_queued = 0 ;
1611 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1612 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
1613 xl_priv->asb_queued = 1 ;
1614
1615 xl_wait_misr_flags(dev) ;
1616
1617 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
1618 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1619 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1620 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
1621 return ;
1622 /* Drop out and wait for the bottom half to be run */
1623 }
1624
1625 xl_asb_cmd(dev) ;
1626
1627 } else {
1628 printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x\n",dev->name,arb_cmd);
1629 }
1630
1631 /* Acknowledge the arb interrupt */
1632
1633 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1634
1635 return ;
1636}
1637
1638
1639/*
1640 * There is only one asb command, but we can get called from different
1641 * places.
1642 */
1643
1644static void xl_asb_cmd(struct net_device *dev)
1645{
1646 struct xl_private *xl_priv = netdev_priv(dev);
1647 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1648
1649 if (xl_priv->asb_queued == 1)
1650 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1651
1652 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1653 writeb(0x81, xl_mmio + MMIO_MACDATA) ;
1654
1655 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1656 writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
1657
1658 xl_wait_misr_flags(dev) ;
1659
1660 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
1661 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1662
1663 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1664 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
1665
1666 xl_priv->asb_queued = 2 ;
1667
1668 return ;
1669}
1670
1671/*
1672 * This will only get called if there was an error
1673 * from the asb cmd.
1674 */
1675static void xl_asb_bh(struct net_device *dev)
1676{
1677 struct xl_private *xl_priv = netdev_priv(dev);
1678 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1679 u8 ret_code ;
1680
1681 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1682 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1683 switch (ret_code) {
1684 case 0x01:
1685 printk(KERN_INFO "%s: ASB Command, unrecognized command code\n",dev->name);
1686 break ;
1687 case 0x26:
1688 printk(KERN_INFO "%s: ASB Command, unexpected receive buffer\n", dev->name);
1689 break ;
1690 case 0x40:
1691 printk(KERN_INFO "%s: ASB Command, Invalid Station ID\n", dev->name);
1692 break ;
1693 }
1694 xl_priv->asb_queued = 0 ;
1695 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1696 return ;
1697}
1698
1699/*
1700 * Issue srb commands to the nic
1701 */
1702
1703static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
1704{
1705 struct xl_private *xl_priv = netdev_priv(dev);
1706 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1707
1708 switch (srb_cmd) {
1709 case READ_LOG:
1710 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1711 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
1712 break;
1713
1714 case CLOSE_NIC:
1715 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1716 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
1717 break ;
1718
1719 case SET_RECEIVE_MODE:
1720 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1721 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
1722 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1723 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
1724 break ;
1725
1726 case SET_FUNC_ADDRESS:
1727 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1728 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
1729 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1730 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
1731 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1732 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
1733 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1734 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
1735 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1736 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
1737 break ;
1738 } /* switch */
1739
1740
1741 xl_wait_misr_flags(dev) ;
1742
1743 /* Write 0xff to the CSRB flag */
1744 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1745 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
1746 /* Set csrb bit in MISR register to process command */
1747 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1748 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
1749 xl_priv->srb_queued = 1 ;
1750
1751 return ;
1752}
1753
1754/*
1755 * This is nasty, to use the MISR command you have to wait for 6 memory locations
1756 * to be zero. This is the way the driver does on other OS'es so we should be ok with
1757 * the empty loop.
1758 */
1759
1760static void xl_wait_misr_flags(struct net_device *dev)
1761{
1762 struct xl_private *xl_priv = netdev_priv(dev);
1763 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1764
1765 int i ;
1766
1767 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1768 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
1769 for (i=0; i<6; i++) {
1770 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1771 while (readb(xl_mmio + MMIO_MACDATA) != 0) {
1772 ; /* Empty Loop */
1773 }
1774 }
1775 }
1776
1777 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1778 writeb(0x80, xl_mmio + MMIO_MACDATA) ;
1779
1780 return ;
1781}
1782
1783/*
1784 * Change mtu size, this should work the same as olympic
1785 */
1786
1787static int xl_change_mtu(struct net_device *dev, int mtu)
1788{
1789 struct xl_private *xl_priv = netdev_priv(dev);
1790 u16 max_mtu ;
1791
1792 if (xl_priv->xl_ring_speed == 4)
1793 max_mtu = 4500 ;
1794 else
1795 max_mtu = 18000 ;
1796
1797 if (mtu > max_mtu)
1798 return -EINVAL ;
1799 if (mtu < 100)
1800 return -EINVAL ;
1801
1802 dev->mtu = mtu ;
1803 xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
1804
1805 return 0 ;
1806}
1807
1808static void __devexit xl_remove_one (struct pci_dev *pdev)
1809{
1810 struct net_device *dev = pci_get_drvdata(pdev);
1811 struct xl_private *xl_priv=netdev_priv(dev);
1812
1813 release_firmware(xl_priv->fw);
1814 unregister_netdev(dev);
1815 iounmap(xl_priv->xl_mmio) ;
1816 pci_release_regions(pdev) ;
1817 pci_set_drvdata(pdev,NULL) ;
1818 free_netdev(dev);
1819 return ;
1820}
1821
1822static struct pci_driver xl_3c359_driver = {
1823 .name = "3c359",
1824 .id_table = xl_pci_tbl,
1825 .probe = xl_probe,
1826 .remove = __devexit_p(xl_remove_one),
1827};
1828
1829module_pci_driver(xl_3c359_driver);
1830
1831MODULE_LICENSE("GPL") ;
diff --git a/drivers/net/tokenring/3c359.h b/drivers/net/tokenring/3c359.h
deleted file mode 100644
index bcb1a6b4a4c7..000000000000
--- a/drivers/net/tokenring/3c359.h
+++ /dev/null
@@ -1,291 +0,0 @@
1/*
2 * 3c359.h (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 *
4 * Linux driver for 3Com 3C359 Token Link PCI XL cards.
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License Version 2 or (at your option)
8 * any later verion, incorporated herein by reference.
9 */
10
11/* Memory Access Commands */
12#define IO_BYTE_READ 0x28 << 24
13#define IO_BYTE_WRITE 0x18 << 24
14#define IO_WORD_READ 0x20 << 24
15#define IO_WORD_WRITE 0x10 << 24
16#define MMIO_BYTE_READ 0x88 << 24
17#define MMIO_BYTE_WRITE 0x48 << 24
18#define MMIO_WORD_READ 0x80 << 24
19#define MMIO_WORD_WRITE 0x40 << 24
20#define MEM_BYTE_READ 0x8C << 24
21#define MEM_BYTE_WRITE 0x4C << 24
22#define MEM_WORD_READ 0x84 << 24
23#define MEM_WORD_WRITE 0x44 << 24
24
25#define PMBAR 0x1C80
26#define PMB_CPHOLD (1<<10)
27
28#define CPATTENTION 0x180D
29#define CPA_PMBARVIS (1<<7)
30#define CPA_MEMWREN (1<<6)
31
32#define SWITCHSETTINGS 0x1C88
33#define EECONTROL 0x1C8A
34#define EEDATA 0x1C8C
35#define EEREAD 0x0080
36#define EEWRITE 0x0040
37#define EEERASE 0x0060
38#define EE_ENABLE_WRITE 0x0030
39#define EEBUSY (1<<15)
40
41#define WRBR 0xCDE02
42#define WWOR 0xCDE04
43#define WWCR 0xCDE06
44#define MACSTATUS 0xCDE08
45#define MISR_RW 0xCDE0B
46#define MISR_AND 0xCDE2B
47#define MISR_SET 0xCDE4B
48#define RXBUFAREA 0xCDE10
49#define RXEARLYTHRESH 0xCDE12
50#define TXSTARTTHRESH 0x58
51#define DNPRIREQTHRESH 0x2C
52
53#define MISR_CSRB (1<<5)
54#define MISR_RASB (1<<4)
55#define MISR_SRBFR (1<<3)
56#define MISR_ASBFR (1<<2)
57#define MISR_ARBF (1<<1)
58
59/* MISR Flags memory locations */
60#define MF_SSBF 0xDFFE0
61#define MF_ARBF 0xDFFE1
62#define MF_ASBFR 0xDFFE2
63#define MF_SRBFR 0xDFFE3
64#define MF_RASB 0xDFFE4
65#define MF_CSRB 0xDFFE5
66
67#define MMIO_MACDATA 0x10
68#define MMIO_MAC_ACCESS_CMD 0x14
69#define MMIO_TIMER 0x1A
70#define MMIO_DMA_CTRL 0x20
71#define MMIO_DNLISTPTR 0x24
72#define MMIO_HASHFILTER 0x28
73#define MMIO_CONFIG 0x29
74#define MMIO_DNPRIREQTHRESH 0x2C
75#define MMIO_DNPOLL 0x2D
76#define MMIO_UPPKTSTATUS 0x30
77#define MMIO_FREETIMER 0x34
78#define MMIO_COUNTDOWN 0x36
79#define MMIO_UPLISTPTR 0x38
80#define MMIO_UPPOLL 0x3C
81#define MMIO_UPBURSTTHRESH 0x40
82#define MMIO_DNBURSTTHRESH 0x41
83#define MMIO_INTSTATUS_AUTO 0x56
84#define MMIO_TXSTARTTHRESH 0x58
85#define MMIO_INTERRUPTENABLE 0x5A
86#define MMIO_INDICATIONENABLE 0x5C
87#define MMIO_COMMAND 0x5E /* These two are meant to be the same */
88#define MMIO_INTSTATUS 0x5E /* Makes the code more readable this way */
89#define INTSTAT_CMD_IN_PROGRESS (1<<12)
90#define INTSTAT_SRB (1<<14)
91#define INTSTAT_INTLATCH (1<<0)
92
93/* Indication / Interrupt Mask
94 * Annoyingly the bits to be set in the indication and interrupt enable
95 * do not match with the actual bits received in the interrupt, although
96 * they are in the same order.
97 * The mapping for the indication / interrupt are:
98 * Bit Indication / Interrupt
99 * 0 HostError
100 * 1 txcomplete
101 * 2 updneeded
102 * 3 rxcomplete
103 * 4 intrequested
104 * 5 macerror
105 * 6 dncomplete
106 * 7 upcomplete
107 * 8 txunderrun
108 * 9 asbf
109 * 10 srbr
110 * 11 arbc
111 *
112 * The only ones we don't want to receive are txcomplete and rxcomplete
113 * we use dncomplete and upcomplete instead.
114 */
115
116#define INT_MASK 0xFF5
117
118/* Note the subtle difference here, IND and INT */
119
120#define SETINDENABLE (8<<12)
121#define SETINTENABLE (7<<12)
122#define SRBBIT (1<<10)
123#define ASBBIT (1<<9)
124#define ARBBIT (1<<11)
125
126#define SRB 0xDFE90
127#define ASB 0xDFED0
128#define ARB 0xD0000
129#define SCRATCH 0xDFEF0
130
131#define INT_REQUEST 0x6000 /* (6 << 12) */
132#define ACK_INTERRUPT 0x6800 /* (13 <<11) */
133#define GLOBAL_RESET 0x00
134#define DNDISABLE 0x5000
135#define DNENABLE 0x4800
136#define DNSTALL 0x3002
137#define DNRESET 0x5800
138#define DNUNSTALL 0x3003
139#define UPRESET 0x2800
140#define UPSTALL 0x3000
141#define UPUNSTALL 0x3001
142#define SETCONFIG 0x4000
143#define SETTXSTARTTHRESH 0x9800
144
145/* Received Interrupts */
146#define ASBFINT (1<<13)
147#define SRBRINT (1<<14)
148#define ARBCINT (1<<15)
149#define TXUNDERRUN (1<<11)
150
151#define UPCOMPINT (1<<10)
152#define DNCOMPINT (1<<9)
153#define HARDERRINT (1<<7)
154#define RXCOMPLETE (1<<4)
155#define TXCOMPINT (1<<2)
156#define HOSTERRINT (1<<1)
157
158/* Receive descriptor bits */
159#define RXOVERRUN cpu_to_le32(1<<19)
160#define RXFC cpu_to_le32(1<<21)
161#define RXAR cpu_to_le32(1<<22)
162#define RXUPDCOMPLETE cpu_to_le32(1<<23)
163#define RXUPDFULL cpu_to_le32(1<<24)
164#define RXUPLASTFRAG cpu_to_le32(1<<31)
165
166/* Transmit descriptor bits */
167#define TXDNCOMPLETE cpu_to_le32(1<<16)
168#define TXTXINDICATE cpu_to_le32(1<<27)
169#define TXDPDEMPTY cpu_to_le32(1<<29)
170#define TXDNINDICATE cpu_to_le32(1<<31)
171#define TXDNFRAGLAST cpu_to_le32(1<<31)
172
173/* Interrupts to Acknowledge */
174#define LATCH_ACK 1
175#define TXCOMPACK (1<<1)
176#define INTREQACK (1<<2)
177#define DNCOMPACK (1<<3)
178#define UPCOMPACK (1<<4)
179#define ASBFACK (1<<5)
180#define SRBRACK (1<<6)
181#define ARBCACK (1<<7)
182
183#define XL_IO_SPACE 128
184#define SRB_COMMAND_SIZE 50
185
186/* Adapter Commands */
187#define REQUEST_INT 0x00
188#define MODIFY_OPEN_PARMS 0x01
189#define RESTORE_OPEN_PARMS 0x02
190#define OPEN_NIC 0x03
191#define CLOSE_NIC 0x04
192#define SET_SLEEP_MODE 0x05
193#define SET_GROUP_ADDRESS 0x06
194#define SET_FUNC_ADDRESS 0x07
195#define READ_LOG 0x08
196#define SET_MULTICAST_MODE 0x0C
197#define CHANGE_WAKEUP_PATTERN 0x0D
198#define GET_STATISTICS 0x13
199#define SET_RECEIVE_MODE 0x1F
200
201/* ARB Commands */
202#define RECEIVE_DATA 0x81
203#define RING_STATUS_CHANGE 0x84
204
205/* ASB Commands */
206#define ASB_RECEIVE_DATE 0x81
207
208/* Defines for LAN STATUS CHANGE reports */
209#define LSC_SIG_LOSS 0x8000
210#define LSC_HARD_ERR 0x4000
211#define LSC_SOFT_ERR 0x2000
212#define LSC_TRAN_BCN 0x1000
213#define LSC_LWF 0x0800
214#define LSC_ARW 0x0400
215#define LSC_FPE 0x0200
216#define LSC_RR 0x0100
217#define LSC_CO 0x0080
218#define LSC_SS 0x0040
219#define LSC_RING_REC 0x0020
220#define LSC_SR_CO 0x0010
221#define LSC_FDX_MODE 0x0004
222
223#define XL_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
224
225/* 3c359 defaults for buffers */
226
227#define XL_RX_RING_SIZE 16 /* must be a power of 2 */
228#define XL_TX_RING_SIZE 16 /* must be a power of 2 */
229
230#define PKT_BUF_SZ 4096 /* Default packet size */
231
232/* 3c359 data structures */
233
234struct xl_tx_desc {
235 __le32 dnnextptr;
236 __le32 framestartheader;
237 __le32 buffer;
238 __le32 buffer_length;
239};
240
241struct xl_rx_desc {
242 __le32 upnextptr;
243 __le32 framestatus;
244 __le32 upfragaddr;
245 __le32 upfraglen;
246};
247
248struct xl_private {
249
250
251 /* These two structures must be aligned on 8 byte boundaries */
252
253 /* struct xl_rx_desc xl_rx_ring[XL_RX_RING_SIZE]; */
254 /* struct xl_tx_desc xl_tx_ring[XL_TX_RING_SIZE]; */
255 struct xl_rx_desc *xl_rx_ring ;
256 struct xl_tx_desc *xl_tx_ring ;
257 struct sk_buff *tx_ring_skb[XL_TX_RING_SIZE], *rx_ring_skb[XL_RX_RING_SIZE];
258 int tx_ring_head, tx_ring_tail ;
259 int rx_ring_tail, rx_ring_no ;
260 int free_ring_entries ;
261
262 u16 srb;
263 u16 arb;
264 u16 asb;
265
266 u8 __iomem *xl_mmio;
267 const char *xl_card_name;
268 struct pci_dev *pdev ;
269
270 spinlock_t xl_lock ;
271
272 volatile int srb_queued;
273 struct wait_queue *srb_wait;
274 volatile int asb_queued;
275
276 u16 mac_buffer ;
277 u16 xl_lan_status ;
278 u8 xl_ring_speed ;
279 u16 pkt_buf_sz ;
280 u8 xl_message_level;
281 u16 xl_copy_all_options ;
282 unsigned char xl_functional_addr[4] ;
283 u16 xl_addr_table_addr, xl_parms_addr ;
284 u8 xl_laa[6] ;
285 u32 rx_ring_dma_addr ;
286 u32 tx_ring_dma_addr ;
287
288 /* firmware section */
289 const struct firmware *fw;
290};
291
diff --git a/drivers/net/tokenring/Kconfig b/drivers/net/tokenring/Kconfig
deleted file mode 100644
index ef3bb1326e4f..000000000000
--- a/drivers/net/tokenring/Kconfig
+++ /dev/null
@@ -1,199 +0,0 @@
1#
2# Token Ring driver configuration
3#
4
5# So far, we only have PCI, ISA, and MCA token ring devices
6menuconfig TR
7 bool "Token Ring driver support"
8 depends on NETDEVICES && !UML
9 depends on (PCI || ISA || MCA || CCW || PCMCIA)
10 help
11 Token Ring is IBM's way of communication on a local network; the
12 rest of the world uses Ethernet. To participate on a Token Ring
13 network, you need a special Token ring network card. If you are
14 connected to such a Token Ring network and want to use your Token
15 Ring card under Linux, say Y here and to the driver for your
16 particular card below and read the Token-Ring mini-HOWTO, available
17 from <http://www.tldp.org/docs.html#howto>. Most people can
18 say N here.
19
20if TR
21
22config WANT_LLC
23 def_bool y
24 select LLC
25
26config PCMCIA_IBMTR
27 tristate "IBM PCMCIA tokenring adapter support"
28 depends on IBMTR!=y && PCMCIA
29 ---help---
30 Say Y here if you intend to attach this type of Token Ring PCMCIA
31 card to your computer. You then also need to say Y to "Token Ring
32 driver support".
33
34 To compile this driver as a module, choose M here: the module will be
35 called ibmtr_cs.
36
37config IBMTR
38 tristate "IBM Tropic chipset based adapter support"
39 depends on ISA || MCA
40 ---help---
41 This is support for all IBM Token Ring cards that don't use DMA. If
42 you have such a beast, say Y and read the Token-Ring mini-HOWTO,
43 available from <http://www.tldp.org/docs.html#howto>.
44
45 Warning: this driver will almost definitely fail if more than one
46 active Token Ring card is present.
47
48 To compile this driver as a module, choose M here: the module will be
49 called ibmtr.
50
51config IBMOL
52 tristate "IBM Olympic chipset PCI adapter support"
53 depends on PCI
54 ---help---
55 This is support for all non-Lanstreamer IBM PCI Token Ring Cards.
56 Specifically this is all IBM PCI, PCI Wake On Lan, PCI II, PCI II
57 Wake On Lan, and PCI 100/16/4 adapters.
58
59 If you have such an adapter, say Y and read the Token-Ring
60 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
61
62 To compile this driver as a module, choose M here: the module will be
63 called olympic.
64
65 Also read <file:Documentation/networking/olympic.txt> or check the
66 Linux Token Ring Project site for the latest information at
67 <http://www.linuxtr.net/>.
68
69config IBMLS
70 tristate "IBM Lanstreamer chipset PCI adapter support"
71 depends on PCI && !64BIT
72 help
73 This is support for IBM Lanstreamer PCI Token Ring Cards.
74
75 If you have such an adapter, say Y and read the Token-Ring
76 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
77
78 To compile this driver as a module, choose M here: the module will be
79 called lanstreamer.
80
81config 3C359
82 tristate "3Com 3C359 Token Link Velocity XL adapter support"
83 depends on PCI
84 ---help---
85 This is support for the 3Com PCI Velocity XL cards, specifically
86 the 3Com 3C359, please note this is not for the 3C339 cards, you
87 should use the tms380 driver instead.
88
89 If you have such an adapter, say Y and read the Token-Ring
90 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
91
92 To compile this driver as a module, choose M here: the module will be
93 called 3c359.
94
95 Also read the file <file:Documentation/networking/3c359.txt> or check the
96 Linux Token Ring Project site for the latest information at
97 <http://www.linuxtr.net>
98
99config TMS380TR
100 tristate "Generic TMS380 Token Ring ISA/PCI adapter support"
101 depends on PCI || ISA || MCA
102 select FW_LOADER
103 ---help---
104 This driver provides generic support for token ring adapters
105 based on the Texas Instruments TMS380 series chipsets. This
106 includes the SysKonnect TR4/16(+) ISA (SK-4190), SysKonnect
107 TR4/16(+) PCI (SK-4590), SysKonnect TR4/16 PCI (SK-4591),
108 Compaq 4/16 PCI, Thomas-Conrad TC4048 4/16 PCI, and several
109 Madge adapters. If you say Y here, you will be asked to select
110 which cards to support below. If you're using modules, each
111 class of card will be supported by a separate module.
112
113 If you have such an adapter and would like to use it, say Y and
114 read the Token-Ring mini-HOWTO, available from
115 <http://www.tldp.org/docs.html#howto>.
116
117 Also read the file <file:Documentation/networking/tms380tr.txt> or
118 check <http://www.auk.cx/tms380tr/>.
119
120 To compile this driver as a module, choose M here: the module will be
121 called tms380tr.
122
123config TMSPCI
124 tristate "Generic TMS380 PCI support"
125 depends on TMS380TR && PCI
126 ---help---
127 This tms380 module supports generic TMS380-based PCI cards.
128
129 These cards are known to work:
130 - Compaq 4/16 TR PCI
131 - SysKonnect TR4/16 PCI (SK-4590/SK-4591)
132 - Thomas-Conrad TC4048 PCI 4/16
133 - 3Com Token Link Velocity
134
135 To compile this driver as a module, choose M here: the module will be
136 called tmspci.
137
138config SKISA
139 tristate "SysKonnect TR4/16 ISA support"
140 depends on TMS380TR && ISA && ISA_DMA_API
141 help
142 This tms380 module supports SysKonnect TR4/16 ISA cards.
143
144 These cards are known to work:
145 - SysKonnect TR4/16 ISA (SK-4190)
146
147 To compile this driver as a module, choose M here: the module will be
148 called skisa.
149
150config PROTEON
151 tristate "Proteon ISA support"
152 depends on TMS380TR && ISA && ISA_DMA_API
153 help
154 This tms380 module supports Proteon ISA cards.
155
156 These cards are known to work:
157 - Proteon 1392
158 - Proteon 1392 plus
159
160 To compile this driver as a module, choose M here: the module will be
161 called proteon.
162
163config ABYSS
164 tristate "Madge Smart 16/4 PCI Mk2 support"
165 depends on TMS380TR && PCI
166 help
167 This tms380 module supports the Madge Smart 16/4 PCI Mk2
168 cards (51-02).
169
170 To compile this driver as a module, choose M here: the module will be
171 called abyss.
172
173config MADGEMC
174 tristate "Madge Smart 16/4 Ringnode MicroChannel"
175 depends on TMS380TR && MCA
176 help
177 This tms380 module supports the Madge Smart 16/4 MC16 and MC32
178 MicroChannel adapters.
179
180 To compile this driver as a module, choose M here: the module will be
181 called madgemc.
182
183config SMCTR
184 tristate "SMC ISA/MCA adapter support"
185 depends on (ISA || MCA_LEGACY) && (BROKEN || !64BIT)
186 ---help---
187 This is support for the ISA and MCA SMC Token Ring cards,
188 specifically SMC TokenCard Elite (8115T) and SMC TokenCard Elite/A
189 (8115T/A) adapters.
190
191 If you have such an adapter and would like to use it, say Y or M and
192 read the Token-Ring mini-HOWTO, available from
193 <http://www.tldp.org/docs.html#howto> and the file
194 <file:Documentation/networking/smctr.txt>.
195
196 To compile this driver as a module, choose M here: the module will be
197 called smctr.
198
199endif # TR
diff --git a/drivers/net/tokenring/Makefile b/drivers/net/tokenring/Makefile
deleted file mode 100644
index f1be8d97b7a8..000000000000
--- a/drivers/net/tokenring/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
1#
2# Makefile for drivers/net/tokenring
3#
4
5obj-$(CONFIG_PCMCIA_IBMTR) += ibmtr_cs.o
6obj-$(CONFIG_IBMTR) += ibmtr.o
7obj-$(CONFIG_IBMOL) += olympic.o
8obj-$(CONFIG_IBMLS) += lanstreamer.o
9obj-$(CONFIG_TMS380TR) += tms380tr.o
10obj-$(CONFIG_ABYSS) += abyss.o
11obj-$(CONFIG_MADGEMC) += madgemc.o
12obj-$(CONFIG_PROTEON) += proteon.o
13obj-$(CONFIG_TMSPCI) += tmspci.o
14obj-$(CONFIG_SKISA) += skisa.o
15obj-$(CONFIG_SMCTR) += smctr.o
16obj-$(CONFIG_3C359) += 3c359.o
diff --git a/drivers/net/tokenring/abyss.c b/drivers/net/tokenring/abyss.c
deleted file mode 100644
index b715e6b444da..000000000000
--- a/drivers/net/tokenring/abyss.c
+++ /dev/null
@@ -1,468 +0,0 @@
1/*
2 * abyss.c: Network driver for the Madge Smart 16/4 PCI Mk2 token ring card.
3 *
4 * Written 1999-2000 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - Madge Smart 16/4 PCI Mk2
11 *
12 * Maintainer(s):
13 * AF Adam Fritzler
14 *
15 * Modification History:
16 * 30-Dec-99 AF Split off from the tms380tr driver.
17 * 22-Jan-00 AF Updated to use indirect read/writes
18 * 23-Nov-00 JG New PCI API, cleanups
19 *
20 *
21 * TODO:
22 * 1. See if we can use MMIO instead of inb/outb/inw/outw
23 * 2. Add support for Mk1 (has AT24 attached to the PCI
24 * config registers)
25 *
26 */
27
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/errno.h>
31#include <linux/pci.h>
32#include <linux/init.h>
33#include <linux/netdevice.h>
34#include <linux/trdevice.h>
35
36#include <asm/io.h>
37#include <asm/irq.h>
38
39#include "tms380tr.h"
40#include "abyss.h" /* Madge-specific constants */
41
42static char version[] __devinitdata =
43"abyss.c: v1.02 23/11/2000 by Adam Fritzler\n";
44
45#define ABYSS_IO_EXTENT 64
46
47static DEFINE_PCI_DEVICE_TABLE(abyss_pci_tbl) = {
48 { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_MK2,
49 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_TOKEN_RING << 8, 0x00ffffff, },
50 { } /* Terminating entry */
51};
52MODULE_DEVICE_TABLE(pci, abyss_pci_tbl);
53
54MODULE_LICENSE("GPL");
55
56static int abyss_open(struct net_device *dev);
57static int abyss_close(struct net_device *dev);
58static void abyss_enable(struct net_device *dev);
59static int abyss_chipset_init(struct net_device *dev);
60static void abyss_read_eeprom(struct net_device *dev);
61static unsigned short abyss_setnselout_pins(struct net_device *dev);
62
63static void at24_writedatabyte(unsigned long regaddr, unsigned char byte);
64static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr);
65static int at24_sendcmd(unsigned long regaddr, unsigned char cmd);
66static unsigned char at24_readdatabit(unsigned long regaddr);
67static unsigned char at24_readdatabyte(unsigned long regaddr);
68static int at24_waitforack(unsigned long regaddr);
69static int at24_waitfornack(unsigned long regaddr);
70static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data);
71static void at24_start(unsigned long regaddr);
72static unsigned char at24_readb(unsigned long regaddr, unsigned char addr);
73
74static unsigned short abyss_sifreadb(struct net_device *dev, unsigned short reg)
75{
76 return inb(dev->base_addr + reg);
77}
78
79static unsigned short abyss_sifreadw(struct net_device *dev, unsigned short reg)
80{
81 return inw(dev->base_addr + reg);
82}
83
84static void abyss_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
85{
86 outb(val, dev->base_addr + reg);
87}
88
89static void abyss_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
90{
91 outw(val, dev->base_addr + reg);
92}
93
94static struct net_device_ops abyss_netdev_ops;
95
96static int __devinit abyss_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
97{
98 static int versionprinted;
99 struct net_device *dev;
100 struct net_local *tp;
101 int ret, pci_irq_line;
102 unsigned long pci_ioaddr;
103
104 if (versionprinted++ == 0)
105 printk("%s", version);
106
107 if (pci_enable_device(pdev))
108 return -EIO;
109
110 /* Remove I/O space marker in bit 0. */
111 pci_irq_line = pdev->irq;
112 pci_ioaddr = pci_resource_start (pdev, 0);
113
114 /* At this point we have found a valid card. */
115
116 dev = alloc_trdev(sizeof(struct net_local));
117 if (!dev)
118 return -ENOMEM;
119
120 if (!request_region(pci_ioaddr, ABYSS_IO_EXTENT, dev->name)) {
121 ret = -EBUSY;
122 goto err_out_trdev;
123 }
124
125 ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED,
126 dev->name, dev);
127 if (ret)
128 goto err_out_region;
129
130 dev->base_addr = pci_ioaddr;
131 dev->irq = pci_irq_line;
132
133 printk("%s: Madge Smart 16/4 PCI Mk2 (Abyss)\n", dev->name);
134 printk("%s: IO: %#4lx IRQ: %d\n",
135 dev->name, pci_ioaddr, dev->irq);
136 /*
137 * The TMS SIF registers lay 0x10 above the card base address.
138 */
139 dev->base_addr += 0x10;
140
141 ret = tmsdev_init(dev, &pdev->dev);
142 if (ret) {
143 printk("%s: unable to get memory for dev->priv.\n",
144 dev->name);
145 goto err_out_irq;
146 }
147
148 abyss_read_eeprom(dev);
149
150 printk("%s: Ring Station Address: %pM\n", dev->name, dev->dev_addr);
151
152 tp = netdev_priv(dev);
153 tp->setnselout = abyss_setnselout_pins;
154 tp->sifreadb = abyss_sifreadb;
155 tp->sifreadw = abyss_sifreadw;
156 tp->sifwriteb = abyss_sifwriteb;
157 tp->sifwritew = abyss_sifwritew;
158
159 memcpy(tp->ProductID, "Madge PCI 16/4 Mk2", PROD_ID_SIZE + 1);
160
161 dev->netdev_ops = &abyss_netdev_ops;
162
163 pci_set_drvdata(pdev, dev);
164 SET_NETDEV_DEV(dev, &pdev->dev);
165
166 ret = register_netdev(dev);
167 if (ret)
168 goto err_out_tmsdev;
169 return 0;
170
171err_out_tmsdev:
172 pci_set_drvdata(pdev, NULL);
173 tmsdev_term(dev);
174err_out_irq:
175 free_irq(pdev->irq, dev);
176err_out_region:
177 release_region(pci_ioaddr, ABYSS_IO_EXTENT);
178err_out_trdev:
179 free_netdev(dev);
180 return ret;
181}
182
183static unsigned short abyss_setnselout_pins(struct net_device *dev)
184{
185 unsigned short val = 0;
186 struct net_local *tp = netdev_priv(dev);
187
188 if(tp->DataRate == SPEED_4)
189 val |= 0x01; /* Set 4Mbps */
190 else
191 val |= 0x00; /* Set 16Mbps */
192
193 return val;
194}
195
196/*
197 * The following Madge boards should use this code:
198 * - Smart 16/4 PCI Mk2 (Abyss)
199 * - Smart 16/4 PCI Mk1 (PCI T)
200 * - Smart 16/4 Client Plus PnP (Big Apple)
201 * - Smart 16/4 Cardbus Mk2
202 *
203 * These access an Atmel AT24 SEEPROM using their glue chip registers.
204 *
205 */
206static void at24_writedatabyte(unsigned long regaddr, unsigned char byte)
207{
208 int i;
209
210 for (i = 0; i < 8; i++) {
211 at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
212 at24_setlines(regaddr, 1, (byte >> (7-i))&0x01);
213 at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
214 }
215}
216
217static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr)
218{
219 if (at24_sendcmd(regaddr, cmd)) {
220 at24_writedatabyte(regaddr, addr);
221 return at24_waitforack(regaddr);
222 }
223 return 0;
224}
225
226static int at24_sendcmd(unsigned long regaddr, unsigned char cmd)
227{
228 int i;
229
230 for (i = 0; i < 10; i++) {
231 at24_start(regaddr);
232 at24_writedatabyte(regaddr, cmd);
233 if (at24_waitforack(regaddr))
234 return 1;
235 }
236 return 0;
237}
238
239static unsigned char at24_readdatabit(unsigned long regaddr)
240{
241 unsigned char val;
242
243 at24_setlines(regaddr, 0, 1);
244 at24_setlines(regaddr, 1, 1);
245 val = (inb(regaddr) & AT24_DATA)?1:0;
246 at24_setlines(regaddr, 1, 1);
247 at24_setlines(regaddr, 0, 1);
248 return val;
249}
250
251static unsigned char at24_readdatabyte(unsigned long regaddr)
252{
253 unsigned char data = 0;
254 int i;
255
256 for (i = 0; i < 8; i++) {
257 data <<= 1;
258 data |= at24_readdatabit(regaddr);
259 }
260
261 return data;
262}
263
264static int at24_waitforack(unsigned long regaddr)
265{
266 int i;
267
268 for (i = 0; i < 10; i++) {
269 if ((at24_readdatabit(regaddr) & 0x01) == 0x00)
270 return 1;
271 }
272 return 0;
273}
274
275static int at24_waitfornack(unsigned long regaddr)
276{
277 int i;
278 for (i = 0; i < 10; i++) {
279 if ((at24_readdatabit(regaddr) & 0x01) == 0x01)
280 return 1;
281 }
282 return 0;
283}
284
285static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data)
286{
287 unsigned char val = AT24_ENABLE;
288 if (clock)
289 val |= AT24_CLOCK;
290 if (data)
291 val |= AT24_DATA;
292
293 outb(val, regaddr);
294 tms380tr_wait(20); /* Very necessary. */
295}
296
297static void at24_start(unsigned long regaddr)
298{
299 at24_setlines(regaddr, 0, 1);
300 at24_setlines(regaddr, 1, 1);
301 at24_setlines(regaddr, 1, 0);
302 at24_setlines(regaddr, 0, 1);
303}
304
305static unsigned char at24_readb(unsigned long regaddr, unsigned char addr)
306{
307 unsigned char data = 0xff;
308
309 if (at24_sendfullcmd(regaddr, AT24_WRITE, addr)) {
310 if (at24_sendcmd(regaddr, AT24_READ)) {
311 data = at24_readdatabyte(regaddr);
312 if (!at24_waitfornack(regaddr))
313 data = 0xff;
314 }
315 }
316 return data;
317}
318
319
320/*
321 * Enable basic functions of the Madge chipset needed
322 * for initialization.
323 */
324static void abyss_enable(struct net_device *dev)
325{
326 unsigned char reset_reg;
327 unsigned long ioaddr;
328
329 ioaddr = dev->base_addr;
330 reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
331 reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
332 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
333 tms380tr_wait(100);
334}
335
336/*
337 * Enable the functions of the Madge chipset needed for
338 * full working order.
339 */
340static int abyss_chipset_init(struct net_device *dev)
341{
342 unsigned char reset_reg;
343 unsigned long ioaddr;
344
345 ioaddr = dev->base_addr;
346
347 reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
348
349 reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
350 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
351
352 reset_reg &= ~(PCIBM2_RESET_REG_CHIP_NRES |
353 PCIBM2_RESET_REG_FIFO_NRES |
354 PCIBM2_RESET_REG_SIF_NRES);
355 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
356
357 tms380tr_wait(100);
358
359 reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
360 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
361
362 reset_reg |= PCIBM2_RESET_REG_SIF_NRES;
363 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
364
365 reset_reg |= PCIBM2_RESET_REG_FIFO_NRES;
366 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
367
368 outb(PCIBM2_INT_CONTROL_REG_SINTEN |
369 PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE,
370 ioaddr + PCIBM2_INT_CONTROL_REG);
371
372 outb(30, ioaddr + PCIBM2_FIFO_THRESHOLD);
373
374 return 0;
375}
376
377static inline void abyss_chipset_close(struct net_device *dev)
378{
379 unsigned long ioaddr;
380
381 ioaddr = dev->base_addr;
382 outb(0, ioaddr + PCIBM2_RESET_REG);
383}
384
385/*
386 * Read configuration data from the AT24 SEEPROM on Madge cards.
387 *
388 */
389static void abyss_read_eeprom(struct net_device *dev)
390{
391 struct net_local *tp;
392 unsigned long ioaddr;
393 unsigned short val;
394 int i;
395
396 tp = netdev_priv(dev);
397 ioaddr = dev->base_addr;
398
399 /* Must enable glue chip first */
400 abyss_enable(dev);
401
402 val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
403 PCIBM2_SEEPROM_RING_SPEED);
404 tp->DataRate = val?SPEED_4:SPEED_16; /* set open speed */
405 printk("%s: SEEPROM: ring speed: %dMb/sec\n", dev->name, tp->DataRate);
406
407 val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
408 PCIBM2_SEEPROM_RAM_SIZE) * 128;
409 printk("%s: SEEPROM: adapter RAM: %dkb\n", dev->name, val);
410
411 dev->addr_len = 6;
412 for (i = 0; i < 6; i++)
413 dev->dev_addr[i] = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
414 PCIBM2_SEEPROM_BIA+i);
415}
416
417static int abyss_open(struct net_device *dev)
418{
419 abyss_chipset_init(dev);
420 tms380tr_open(dev);
421 return 0;
422}
423
424static int abyss_close(struct net_device *dev)
425{
426 tms380tr_close(dev);
427 abyss_chipset_close(dev);
428 return 0;
429}
430
431static void __devexit abyss_detach (struct pci_dev *pdev)
432{
433 struct net_device *dev = pci_get_drvdata(pdev);
434
435 BUG_ON(!dev);
436 unregister_netdev(dev);
437 release_region(dev->base_addr-0x10, ABYSS_IO_EXTENT);
438 free_irq(dev->irq, dev);
439 tmsdev_term(dev);
440 free_netdev(dev);
441 pci_set_drvdata(pdev, NULL);
442}
443
444static struct pci_driver abyss_driver = {
445 .name = "abyss",
446 .id_table = abyss_pci_tbl,
447 .probe = abyss_attach,
448 .remove = __devexit_p(abyss_detach),
449};
450
451static int __init abyss_init (void)
452{
453 abyss_netdev_ops = tms380tr_netdev_ops;
454
455 abyss_netdev_ops.ndo_open = abyss_open;
456 abyss_netdev_ops.ndo_stop = abyss_close;
457
458 return pci_register_driver(&abyss_driver);
459}
460
461static void __exit abyss_rmmod (void)
462{
463 pci_unregister_driver (&abyss_driver);
464}
465
466module_init(abyss_init);
467module_exit(abyss_rmmod);
468
diff --git a/drivers/net/tokenring/abyss.h b/drivers/net/tokenring/abyss.h
deleted file mode 100644
index b0a473b89133..000000000000
--- a/drivers/net/tokenring/abyss.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * abyss.h: Header for the abyss tms380tr module
3 *
4 * Authors:
5 * - Adam Fritzler
6 */
7
8#ifndef __LINUX_MADGETR_H
9#define __LINUX_MADGETR_H
10
11#ifdef __KERNEL__
12
13/*
14 * For Madge Smart 16/4 PCI Mk2. Since we increment the base address
15 * to get everything correct for the TMS SIF, we do these as negatives
16 * as they fall below the SIF in addressing.
17 */
18#define PCIBM2_INT_STATUS_REG ((short)-15)/* 0x01 */
19#define PCIBM2_INT_CONTROL_REG ((short)-14)/* 0x02 */
20#define PCIBM2_RESET_REG ((short)-12)/* 0x04 */
21#define PCIBM2_SEEPROM_REG ((short)-9) /* 0x07 */
22
23#define PCIBM2_INT_CONTROL_REG_SINTEN 0x02
24#define PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE 0x80
25#define PCIBM2_INT_STATUS_REG_PCI_ERR 0x80
26
27#define PCIBM2_RESET_REG_CHIP_NRES 0x01
28#define PCIBM2_RESET_REG_FIFO_NRES 0x02
29#define PCIBM2_RESET_REG_SIF_NRES 0x04
30
31#define PCIBM2_FIFO_THRESHOLD 0x21
32#define PCIBM2_BURST_LENGTH 0x22
33
34/*
35 * Bits in PCIBM2_SEEPROM_REG.
36 */
37#define AT24_ENABLE 0x04
38#define AT24_DATA 0x02
39#define AT24_CLOCK 0x01
40
41/*
42 * AT24 Commands.
43 */
44#define AT24_WRITE 0xA0
45#define AT24_READ 0xA1
46
47/*
48 * Addresses in AT24 SEEPROM.
49 */
50#define PCIBM2_SEEPROM_BIA 0x12
51#define PCIBM2_SEEPROM_RING_SPEED 0x18
52#define PCIBM2_SEEPROM_RAM_SIZE 0x1A
53#define PCIBM2_SEEPROM_HWF1 0x1C
54#define PCIBM2_SEEPROM_HWF2 0x1E
55
56
57#endif /* __KERNEL__ */
58#endif /* __LINUX_MADGETR_H */
diff --git a/drivers/net/tokenring/ibmtr.c b/drivers/net/tokenring/ibmtr.c
deleted file mode 100644
index b5c8c18f5046..000000000000
--- a/drivers/net/tokenring/ibmtr.c
+++ /dev/null
@@ -1,1964 +0,0 @@
1/* ibmtr.c: A shared-memory IBM Token Ring 16/4 driver for linux
2 *
3 * Written 1993 by Mark Swanson and Peter De Schrijver.
4 * This software may be used and distributed according to the terms
5 * of the GNU General Public License, incorporated herein by reference.
6 *
7 * This device driver should work with Any IBM Token Ring Card that does
8 * not use DMA.
9 *
10 * I used Donald Becker's (becker@scyld.com) device driver work
11 * as a base for most of my initial work.
12 *
13 * Changes by Peter De Schrijver
14 * (Peter.Deschrijver@linux.cc.kuleuven.ac.be) :
15 *
16 * + changed name to ibmtr.c in anticipation of other tr boards.
17 * + changed reset code and adapter open code.
18 * + added SAP open code.
19 * + a first attempt to write interrupt, transmit and receive routines.
20 *
21 * Changes by David W. Morris (dwm@shell.portal.com) :
22 * 941003 dwm: - Restructure tok_probe for multiple adapters, devices.
23 * + Add comments, misc reorg for clarity.
24 * + Flatten interrupt handler levels.
25 *
26 * Changes by Farzad Farid (farzy@zen.via.ecp.fr)
27 * and Pascal Andre (andre@chimay.via.ecp.fr) (March 9 1995) :
28 * + multi ring support clean up.
29 * + RFC1042 compliance enhanced.
30 *
31 * Changes by Pascal Andre (andre@chimay.via.ecp.fr) (September 7 1995) :
32 * + bug correction in tr_tx
33 * + removed redundant information display
34 * + some code reworking
35 *
36 * Changes by Michel Lespinasse (walken@via.ecp.fr),
37 * Yann Doussot (doussot@via.ecp.fr) and Pascal Andre (andre@via.ecp.fr)
38 * (February 18, 1996) :
39 * + modified shared memory and mmio access port the driver to
40 * alpha platform (structure access -> readb/writeb)
41 *
42 * Changes by Steve Kipisz (bungy@ibm.net or kipisz@vnet.ibm.com)
43 * (January 18 1996):
44 * + swapped WWOR and WWCR in ibmtr.h
45 * + moved some init code from tok_probe into trdev_init. The
46 * PCMCIA code can call trdev_init to complete initializing
47 * the driver.
48 * + added -DPCMCIA to support PCMCIA
49 * + detecting PCMCIA Card Removal in interrupt handler. If
50 * ISRP is FF, then a PCMCIA card has been removed
51 * 10/2000 Burt needed a new method to avoid crashing the OS
52 *
53 * Changes by Paul Norton (pnorton@cts.com) :
54 * + restructured the READ.LOG logic to prevent the transmit SRB
55 * from being rudely overwritten before the transmit cycle is
56 * complete. (August 15 1996)
57 * + completed multiple adapter support. (November 20 1996)
58 * + implemented csum_partial_copy in tr_rx and increased receive
59 * buffer size and count. Minor fixes. (March 15, 1997)
60 *
61 * Changes by Christopher Turcksin <wabbit@rtfc.demon.co.uk>
62 * + Now compiles ok as a module again.
63 *
64 * Changes by Paul Norton (pnorton@ieee.org) :
65 * + moved the header manipulation code in tr_tx and tr_rx to
66 * net/802/tr.c. (July 12 1997)
67 * + add retry and timeout on open if cable disconnected. (May 5 1998)
68 * + lifted 2000 byte mtu limit. now depends on shared-RAM size.
69 * May 25 1998)
70 * + can't allocate 2k recv buff at 8k shared-RAM. (20 October 1998)
71 *
72 * Changes by Joel Sloan (jjs@c-me.com) :
73 * + disable verbose debug messages by default - to enable verbose
74 * debugging, edit the IBMTR_DEBUG_MESSAGES define below
75 *
76 * Changes by Mike Phillips <phillim@amtrak.com> :
77 * + Added extra #ifdef's to work with new PCMCIA Token Ring Code.
78 * The PCMCIA code now just sets up the card so it can be recognized
79 * by ibmtr_probe. Also checks allocated memory vs. on-board memory
80 * for correct figure to use.
81 *
82 * Changes by Tim Hockin (thockin@isunix.it.ilstu.edu) :
83 * + added spinlocks for SMP sanity (10 March 1999)
84 *
85 * Changes by Jochen Friedrich to enable RFC1469 Option 2 multicasting
86 * i.e. using functional address C0 00 00 04 00 00 to transmit and
87 * receive multicast packets.
88 *
89 * Changes by Mike Sullivan (based on original sram patch by Dave Grothe
90 * to support windowing into on adapter shared ram.
91 * i.e. Use LANAID to setup a PnP configuration with 16K RAM. Paging
92 * will shift this 16K window over the entire available shared RAM.
93 *
94 * Changes by Peter De Schrijver (p2@mind.be) :
95 * + fixed a problem with PCMCIA card removal
96 *
97 * Change by Mike Sullivan et al.:
98 * + added turbo card support. No need to use lanaid to configure
99 * the adapter into isa compatibility mode.
100 *
101 * Changes by Burt Silverman to allow the computer to behave nicely when
102 * a cable is pulled or not in place, or a PCMCIA card is removed hot.
103 */
104
105/* change the define of IBMTR_DEBUG_MESSAGES to a nonzero value
106in the event that chatty debug messages are desired - jjs 12/30/98 */
107
108#define IBMTR_DEBUG_MESSAGES 0
109
110#include <linux/module.h>
111#include <linux/sched.h>
112
113#ifdef PCMCIA /* required for ibmtr_cs.c to build */
114#undef MODULE /* yes, really */
115#undef ENABLE_PAGING
116#else
117#define ENABLE_PAGING 1
118#endif
119
120/* changes the output format of driver initialization */
121#define TR_VERBOSE 0
122
123/* some 95 OS send many non UI frame; this allow removing the warning */
124#define TR_FILTERNONUI 1
125
126#include <linux/interrupt.h>
127#include <linux/ioport.h>
128#include <linux/netdevice.h>
129#include <linux/ip.h>
130#include <linux/trdevice.h>
131#include <linux/ibmtr.h>
132
133#include <net/checksum.h>
134
135#include <asm/io.h>
136
137#define DPRINTK(format, args...) printk("%s: " format, dev->name , ## args)
138#define DPRINTD(format, args...) DummyCall("%s: " format, dev->name , ## args)
139
140/* version and credits */
141#ifndef PCMCIA
142static char version[] __devinitdata =
143 "\nibmtr.c: v1.3.57 8/ 7/94 Peter De Schrijver and Mark Swanson\n"
144 " v2.1.125 10/20/98 Paul Norton <pnorton@ieee.org>\n"
145 " v2.2.0 12/30/98 Joel Sloan <jjs@c-me.com>\n"
146 " v2.2.1 02/08/00 Mike Sullivan <sullivam@us.ibm.com>\n"
147 " v2.2.2 07/27/00 Burt Silverman <burts@us.ibm.com>\n"
148 " v2.4.0 03/01/01 Mike Sullivan <sullivan@us.ibm.com>\n";
149#endif
150
151/* this allows displaying full adapter information */
152
153static char *channel_def[] __devinitdata = { "ISA", "MCA", "ISA P&P" };
154
155static char pcchannelid[] __devinitdata = {
156 0x05, 0x00, 0x04, 0x09,
157 0x04, 0x03, 0x04, 0x0f,
158 0x03, 0x06, 0x03, 0x01,
159 0x03, 0x01, 0x03, 0x00,
160 0x03, 0x09, 0x03, 0x09,
161 0x03, 0x00, 0x02, 0x00
162};
163
164static char mcchannelid[] __devinitdata = {
165 0x04, 0x0d, 0x04, 0x01,
166 0x05, 0x02, 0x05, 0x03,
167 0x03, 0x06, 0x03, 0x03,
168 0x05, 0x08, 0x03, 0x04,
169 0x03, 0x05, 0x03, 0x01,
170 0x03, 0x08, 0x02, 0x00
171};
172
173static char __devinit *adapter_def(char type)
174{
175 switch (type) {
176 case 0xF: return "PC Adapter | PC Adapter II | Adapter/A";
177 case 0xE: return "16/4 Adapter | 16/4 Adapter/A (long)";
178 case 0xD: return "16/4 Adapter/A (short) | 16/4 ISA-16 Adapter";
179 case 0xC: return "Auto 16/4 Adapter";
180 default: return "adapter (unknown type)";
181 }
182};
183
184#define TRC_INIT 0x01 /* Trace initialization & PROBEs */
185#define TRC_INITV 0x02 /* verbose init trace points */
186static unsigned char ibmtr_debug_trace = 0;
187
188static int ibmtr_probe1(struct net_device *dev, int ioaddr);
189static unsigned char get_sram_size(struct tok_info *adapt_info);
190static int trdev_init(struct net_device *dev);
191static int tok_open(struct net_device *dev);
192static int tok_init_card(struct net_device *dev);
193static void tok_open_adapter(unsigned long dev_addr);
194static void open_sap(unsigned char type, struct net_device *dev);
195static void tok_set_multicast_list(struct net_device *dev);
196static netdev_tx_t tok_send_packet(struct sk_buff *skb,
197 struct net_device *dev);
198static int tok_close(struct net_device *dev);
199static irqreturn_t tok_interrupt(int irq, void *dev_id);
200static void initial_tok_int(struct net_device *dev);
201static void tr_tx(struct net_device *dev);
202static void tr_rx(struct net_device *dev);
203static void ibmtr_reset_timer(struct timer_list*tmr,struct net_device *dev);
204static void tok_rerun(unsigned long dev_addr);
205static void ibmtr_readlog(struct net_device *dev);
206static int ibmtr_change_mtu(struct net_device *dev, int mtu);
207static void find_turbo_adapters(int *iolist);
208
209static int ibmtr_portlist[IBMTR_MAX_ADAPTERS+1] __devinitdata = {
210 0xa20, 0xa24, 0, 0, 0
211};
212static int __devinitdata turbo_io[IBMTR_MAX_ADAPTERS] = {0};
213static int __devinitdata turbo_irq[IBMTR_MAX_ADAPTERS] = {0};
214static int __devinitdata turbo_searched = 0;
215
216#ifndef PCMCIA
217static __u32 ibmtr_mem_base __devinitdata = 0xd0000;
218#endif
219
220static void __devinit PrtChanID(char *pcid, short stride)
221{
222 short i, j;
223 for (i = 0, j = 0; i < 24; i++, j += stride)
224 printk("%1x", ((int) pcid[j]) & 0x0f);
225 printk("\n");
226}
227
228static void __devinit HWPrtChanID(void __iomem *pcid, short stride)
229{
230 short i, j;
231 for (i = 0, j = 0; i < 24; i++, j += stride)
232 printk("%1x", ((int) readb(pcid + j)) & 0x0f);
233 printk("\n");
234}
235
236/* We have to ioremap every checked address, because isa_readb is
237 * going away.
238 */
239
240static void __devinit find_turbo_adapters(int *iolist)
241{
242 int ram_addr;
243 int index=0;
244 void __iomem *chanid;
245 int found_turbo=0;
246 unsigned char *tchanid, ctemp;
247 int i, j;
248 unsigned long jif;
249 void __iomem *ram_mapped ;
250
251 if (turbo_searched == 1) return;
252 turbo_searched=1;
253 for (ram_addr=0xC0000; ram_addr < 0xE0000; ram_addr+=0x2000) {
254
255 __u32 intf_tbl=0;
256
257 found_turbo=1;
258 ram_mapped = ioremap((u32)ram_addr,0x1fff) ;
259 if (ram_mapped==NULL)
260 continue ;
261 chanid=(CHANNEL_ID + ram_mapped);
262 tchanid=pcchannelid;
263 ctemp=readb(chanid) & 0x0f;
264 if (ctemp != *tchanid) continue;
265 for (i=2,j=1; i<=46; i=i+2,j++) {
266 if ((readb(chanid+i) & 0x0f) != tchanid[j]){
267 found_turbo=0;
268 break;
269 }
270 }
271 if (!found_turbo) continue;
272
273 writeb(0x90, ram_mapped+0x1E01);
274 for(i=2; i<0x0f; i++) {
275 writeb(0x00, ram_mapped+0x1E01+i);
276 }
277 writeb(0x00, ram_mapped+0x1E01);
278 for(jif=jiffies+TR_BUSY_INTERVAL; time_before_eq(jiffies,jif););
279 intf_tbl=ntohs(readw(ram_mapped+ACA_OFFSET+ACA_RW+WRBR_EVEN));
280 if (intf_tbl) {
281#if IBMTR_DEBUG_MESSAGES
282 printk("ibmtr::find_turbo_adapters, Turbo found at "
283 "ram_addr %x\n",ram_addr);
284 printk("ibmtr::find_turbo_adapters, interface_table ");
285 for(i=0; i<6; i++) {
286 printk("%x:",readb(ram_addr+intf_tbl+i));
287 }
288 printk("\n");
289#endif
290 turbo_io[index]=ntohs(readw(ram_mapped+intf_tbl+4));
291 turbo_irq[index]=readb(ram_mapped+intf_tbl+3);
292 outb(0, turbo_io[index] + ADAPTRESET);
293 for(jif=jiffies+TR_RST_TIME;time_before_eq(jiffies,jif););
294 outb(0, turbo_io[index] + ADAPTRESETREL);
295 index++;
296 continue;
297 }
298#if IBMTR_DEBUG_MESSAGES
299 printk("ibmtr::find_turbo_adapters, ibmtr card found at"
300 " %x but not a Turbo model\n",ram_addr);
301#endif
302 iounmap(ram_mapped) ;
303 } /* for */
304 for(i=0; i<IBMTR_MAX_ADAPTERS; i++) {
305 if(!turbo_io[i]) break;
306 for (j=0; j<IBMTR_MAX_ADAPTERS; j++) {
307 if ( iolist[j] && iolist[j] != turbo_io[i]) continue;
308 iolist[j]=turbo_io[i];
309 break;
310 }
311 }
312}
313
314static void ibmtr_cleanup_card(struct net_device *dev)
315{
316 if (dev->base_addr) {
317 outb(0,dev->base_addr+ADAPTRESET);
318
319 schedule_timeout_uninterruptible(TR_RST_TIME); /* wait 50ms */
320
321 outb(0,dev->base_addr+ADAPTRESETREL);
322 }
323
324#ifndef PCMCIA
325 free_irq(dev->irq, dev);
326 release_region(dev->base_addr, IBMTR_IO_EXTENT);
327
328 {
329 struct tok_info *ti = netdev_priv(dev);
330 iounmap(ti->mmio);
331 iounmap(ti->sram_virt);
332 }
333#endif
334}
335
336/****************************************************************************
337 * ibmtr_probe(): Routine specified in the network device structure
338 * to probe for an IBM Token Ring Adapter. Routine outline:
339 * I. Interrogate hardware to determine if an adapter exists
340 * and what the speeds and feeds are
341 * II. Setup data structures to control execution based upon
342 * adapter characteristics.
343 *
344 * We expect ibmtr_probe to be called once for each device entry
345 * which references it.
346 ****************************************************************************/
347
348static int __devinit ibmtr_probe(struct net_device *dev)
349{
350 int i;
351 int base_addr = dev->base_addr;
352
353 if (base_addr && base_addr <= 0x1ff) /* Don't probe at all. */
354 return -ENXIO;
355 if (base_addr > 0x1ff) { /* Check a single specified location. */
356 if (!ibmtr_probe1(dev, base_addr)) return 0;
357 return -ENODEV;
358 }
359 find_turbo_adapters(ibmtr_portlist);
360 for (i = 0; ibmtr_portlist[i]; i++) {
361 int ioaddr = ibmtr_portlist[i];
362
363 if (!ibmtr_probe1(dev, ioaddr)) return 0;
364 }
365 return -ENODEV;
366}
367
368int __devinit ibmtr_probe_card(struct net_device *dev)
369{
370 int err = ibmtr_probe(dev);
371 if (!err) {
372 err = register_netdev(dev);
373 if (err)
374 ibmtr_cleanup_card(dev);
375 }
376 return err;
377}
378
379/*****************************************************************************/
380
381static int __devinit ibmtr_probe1(struct net_device *dev, int PIOaddr)
382{
383
384 unsigned char segment, intr=0, irq=0, i, j, cardpresent=NOTOK, temp=0;
385 void __iomem * t_mmio = NULL;
386 struct tok_info *ti = netdev_priv(dev);
387 void __iomem *cd_chanid;
388 unsigned char *tchanid, ctemp;
389#ifndef PCMCIA
390 unsigned char t_irq=0;
391 unsigned long timeout;
392 static int version_printed;
393#endif
394
395 /* Query the adapter PIO base port which will return
396 * indication of where MMIO was placed. We also have a
397 * coded interrupt number.
398 */
399 segment = inb(PIOaddr);
400 if (segment < 0x40 || segment > 0xe0) {
401 /* Out of range values so we'll assume non-existent IO device
402 * but this is not necessarily a problem, esp if a turbo
403 * adapter is being used. */
404#if IBMTR_DEBUG_MESSAGES
405 DPRINTK("ibmtr_probe1(): unhappy that inb(0x%X) == 0x%X, "
406 "Hardware Problem?\n",PIOaddr,segment);
407#endif
408 return -ENODEV;
409 }
410 /*
411 * Compute the linear base address of the MMIO area
412 * as LINUX doesn't care about segments
413 */
414 t_mmio = ioremap(((__u32) (segment & 0xfc) << 11) + 0x80000,2048);
415 if (!t_mmio) {
416 DPRINTK("Cannot remap mmiobase memory area") ;
417 return -ENODEV ;
418 }
419 intr = segment & 0x03; /* low bits is coded interrupt # */
420 if (ibmtr_debug_trace & TRC_INIT)
421 DPRINTK("PIOaddr: %4hx seg/intr: %2x mmio base: %p intr: %d\n"
422 , PIOaddr, (int) segment, t_mmio, (int) intr);
423
424 /*
425 * Now we will compare expected 'channelid' strings with
426 * what we is there to learn of ISA/MCA or not TR card
427 */
428#ifdef PCMCIA
429 iounmap(t_mmio);
430 t_mmio = ti->mmio; /*BMS to get virtual address */
431 irq = ti->irq; /*BMS to display the irq! */
432#endif
433 cd_chanid = (CHANNEL_ID + t_mmio); /* for efficiency */
434 tchanid = pcchannelid;
435 cardpresent = TR_ISA; /* try ISA */
436
437 /* Suboptimize knowing first byte different */
438 ctemp = readb(cd_chanid) & 0x0f;
439 if (ctemp != *tchanid) { /* NOT ISA card, try MCA */
440 tchanid = mcchannelid;
441 cardpresent = TR_MCA;
442 if (ctemp != *tchanid) /* Neither ISA nor MCA */
443 cardpresent = NOTOK;
444 }
445 if (cardpresent != NOTOK) {
446 /* Know presumed type, try rest of ID */
447 for (i = 2, j = 1; i <= 46; i = i + 2, j++) {
448 if( (readb(cd_chanid+i)&0x0f) == tchanid[j]) continue;
449 /* match failed, not TR card */
450 cardpresent = NOTOK;
451 break;
452 }
453 }
454 /*
455 * If we have an ISA board check for the ISA P&P version,
456 * as it has different IRQ settings
457 */
458 if (cardpresent == TR_ISA && (readb(AIPFID + t_mmio) == 0x0e))
459 cardpresent = TR_ISAPNP;
460 if (cardpresent == NOTOK) { /* "channel_id" did not match, report */
461 if (!(ibmtr_debug_trace & TRC_INIT)) {
462#ifndef PCMCIA
463 iounmap(t_mmio);
464#endif
465 return -ENODEV;
466 }
467 DPRINTK( "Channel ID string not found for PIOaddr: %4hx\n",
468 PIOaddr);
469 DPRINTK("Expected for ISA: ");
470 PrtChanID(pcchannelid, 1);
471 DPRINTK(" found: ");
472/* BMS Note that this can be misleading, when hardware is flaky, because you
473 are reading it a second time here. So with my flaky hardware, I'll see my-
474 self in this block, with the HW ID matching the ISA ID exactly! */
475 HWPrtChanID(cd_chanid, 2);
476 DPRINTK("Expected for MCA: ");
477 PrtChanID(mcchannelid, 1);
478 }
479 /* Now, setup some of the pl0 buffers for this driver.. */
480 /* If called from PCMCIA, it is already set up, so no need to
481 waste the memory, just use the existing structure */
482#ifndef PCMCIA
483 ti->mmio = t_mmio;
484 for (i = 0; i < IBMTR_MAX_ADAPTERS; i++) {
485 if (turbo_io[i] != PIOaddr)
486 continue;
487#if IBMTR_DEBUG_MESSAGES
488 printk("ibmtr::tr_probe1, setting PIOaddr %x to Turbo\n",
489 PIOaddr);
490#endif
491 ti->turbo = 1;
492 t_irq = turbo_irq[i];
493 }
494#endif /* !PCMCIA */
495 ti->readlog_pending = 0;
496 init_waitqueue_head(&ti->wait_for_reset);
497
498 /* if PCMCIA, the card can be recognized as either TR_ISA or TR_ISAPNP
499 * depending which card is inserted. */
500
501#ifndef PCMCIA
502 switch (cardpresent) {
503 case TR_ISA:
504 if (intr == 0) irq = 9; /* irq2 really is irq9 */
505 if (intr == 1) irq = 3;
506 if (intr == 2) irq = 6;
507 if (intr == 3) irq = 7;
508 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
509 break;
510 case TR_MCA:
511 if (intr == 0) irq = 9;
512 if (intr == 1) irq = 3;
513 if (intr == 2) irq = 10;
514 if (intr == 3) irq = 11;
515 ti->global_int_enable = 0;
516 ti->adapter_int_enable = 0;
517 ti->sram_phys=(__u32)(inb(PIOaddr+ADAPTRESETREL) & 0xfe) << 12;
518 break;
519 case TR_ISAPNP:
520 if (!t_irq) {
521 if (intr == 0) irq = 9;
522 if (intr == 1) irq = 3;
523 if (intr == 2) irq = 10;
524 if (intr == 3) irq = 11;
525 } else
526 irq=t_irq;
527 timeout = jiffies + TR_SPIN_INTERVAL;
528 while (!readb(ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN)){
529 if (!time_after(jiffies, timeout)) continue;
530 DPRINTK( "Hardware timeout during initialization.\n");
531 iounmap(t_mmio);
532 return -ENODEV;
533 }
534 ti->sram_phys =
535 ((__u32)readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_EVEN)<<12);
536 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
537 break;
538 } /*end switch (cardpresent) */
539#endif /*not PCMCIA */
540
541 if (ibmtr_debug_trace & TRC_INIT) { /* just report int */
542 DPRINTK("irq=%d", irq);
543 printk(", sram_phys=0x%x", ti->sram_phys);
544 if(ibmtr_debug_trace&TRC_INITV){ /* full chat in verbose only */
545 DPRINTK(", ti->mmio=%p", ti->mmio);
546 printk(", segment=%02X", segment);
547 }
548 printk(".\n");
549 }
550
551 /* Get hw address of token ring card */
552 j = 0;
553 for (i = 0; i < 0x18; i = i + 2) {
554 /* technical reference states to do this */
555 temp = readb(ti->mmio + AIP + i) & 0x0f;
556 ti->hw_address[j] = temp;
557 if (j & 1)
558 dev->dev_addr[(j / 2)] =
559 ti->hw_address[j]+ (ti->hw_address[j - 1] << 4);
560 ++j;
561 }
562 /* get Adapter type: 'F' = Adapter/A, 'E' = 16/4 Adapter II,... */
563 ti->adapter_type = readb(ti->mmio + AIPADAPTYPE);
564
565 /* get Data Rate: F=4Mb, E=16Mb, D=4Mb & 16Mb ?? */
566 ti->data_rate = readb(ti->mmio + AIPDATARATE);
567
568 /* Get Early Token Release support?: F=no, E=4Mb, D=16Mb, C=4&16Mb */
569 ti->token_release = readb(ti->mmio + AIPEARLYTOKEN);
570
571 /* How much shared RAM is on adapter ? */
572 if (ti->turbo) {
573 ti->avail_shared_ram=127;
574 } else {
575 ti->avail_shared_ram = get_sram_size(ti);/*in 512 byte units */
576 }
577 /* We need to set or do a bunch of work here based on previous results*/
578 /* Support paging? What sizes?: F=no, E=16k, D=32k, C=16 & 32k */
579 ti->shared_ram_paging = readb(ti->mmio + AIPSHRAMPAGE);
580
581 /* Available DHB 4Mb size: F=2048, E=4096, D=4464 */
582 switch (readb(ti->mmio + AIP4MBDHB)) {
583 case 0xe: ti->dhb_size4mb = 4096; break;
584 case 0xd: ti->dhb_size4mb = 4464; break;
585 default: ti->dhb_size4mb = 2048; break;
586 }
587
588 /* Available DHB 16Mb size: F=2048, E=4096, D=8192, C=16384, B=17960 */
589 switch (readb(ti->mmio + AIP16MBDHB)) {
590 case 0xe: ti->dhb_size16mb = 4096; break;
591 case 0xd: ti->dhb_size16mb = 8192; break;
592 case 0xc: ti->dhb_size16mb = 16384; break;
593 case 0xb: ti->dhb_size16mb = 17960; break;
594 default: ti->dhb_size16mb = 2048; break;
595 }
596
597 /* We must figure out how much shared memory space this adapter
598 * will occupy so that if there are two adapters we can fit both
599 * in. Given a choice, we will limit this adapter to 32K. The
600 * maximum space will will use for two adapters is 64K so if the
601 * adapter we are working on demands 64K (it also doesn't support
602 * paging), then only one adapter can be supported.
603 */
604
605 /*
606 * determine how much of total RAM is mapped into PC space
607 */
608 ti->mapped_ram_size= /*sixteen to onehundredtwentyeight 512byte blocks*/
609 1<< ((readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03) + 4);
610 ti->page_mask = 0;
611 if (ti->turbo) ti->page_mask=0xf0;
612 else if (ti->shared_ram_paging == 0xf); /* No paging in adapter */
613 else {
614#ifdef ENABLE_PAGING
615 unsigned char pg_size = 0;
616 /* BMS: page size: PCMCIA, use configuration register;
617 ISAPNP, use LANAIDC config tool from www.ibm.com */
618 switch (ti->shared_ram_paging) {
619 case 0xf:
620 break;
621 case 0xe:
622 ti->page_mask = (ti->mapped_ram_size == 32) ? 0xc0 : 0;
623 pg_size = 32; /* 16KB page size */
624 break;
625 case 0xd:
626 ti->page_mask = (ti->mapped_ram_size == 64) ? 0x80 : 0;
627 pg_size = 64; /* 32KB page size */
628 break;
629 case 0xc:
630 switch (ti->mapped_ram_size) {
631 case 32:
632 ti->page_mask = 0xc0;
633 pg_size = 32;
634 break;
635 case 64:
636 ti->page_mask = 0x80;
637 pg_size = 64;
638 break;
639 }
640 break;
641 default:
642 DPRINTK("Unknown shared ram paging info %01X\n",
643 ti->shared_ram_paging);
644 iounmap(t_mmio);
645 return -ENODEV;
646 break;
647 } /*end switch shared_ram_paging */
648
649 if (ibmtr_debug_trace & TRC_INIT)
650 DPRINTK("Shared RAM paging code: %02X, "
651 "mapped RAM size: %dK, shared RAM size: %dK, "
652 "page mask: %02X\n:",
653 ti->shared_ram_paging, ti->mapped_ram_size / 2,
654 ti->avail_shared_ram / 2, ti->page_mask);
655#endif /*ENABLE_PAGING */
656 }
657
658#ifndef PCMCIA
659 /* finish figuring the shared RAM address */
660 if (cardpresent == TR_ISA) {
661 static const __u32 ram_bndry_mask[] = {
662 0xffffe000, 0xffffc000, 0xffff8000, 0xffff0000
663 };
664 __u32 new_base, rrr_32, chk_base, rbm;
665
666 rrr_32=readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03;
667 rbm = ram_bndry_mask[rrr_32];
668 new_base = (ibmtr_mem_base + (~rbm)) & rbm;/* up to boundary */
669 chk_base = new_base + (ti->mapped_ram_size << 9);
670 if (chk_base > (ibmtr_mem_base + IBMTR_SHARED_RAM_SIZE)) {
671 DPRINTK("Shared RAM for this adapter (%05x) exceeds "
672 "driver limit (%05x), adapter not started.\n",
673 chk_base, ibmtr_mem_base + IBMTR_SHARED_RAM_SIZE);
674 iounmap(t_mmio);
675 return -ENODEV;
676 } else { /* seems cool, record what we have figured out */
677 ti->sram_base = new_base >> 12;
678 ibmtr_mem_base = chk_base;
679 }
680 }
681 else ti->sram_base = ti->sram_phys >> 12;
682
683 /* The PCMCIA has already got the interrupt line and the io port,
684 so no chance of anybody else getting it - MLP */
685 if (request_irq(dev->irq = irq, tok_interrupt, 0, "ibmtr", dev) != 0) {
686 DPRINTK("Could not grab irq %d. Halting Token Ring driver.\n",
687 irq);
688 iounmap(t_mmio);
689 return -ENODEV;
690 }
691 /*?? Now, allocate some of the PIO PORTs for this driver.. */
692 /* record PIOaddr range as busy */
693 if (!request_region(PIOaddr, IBMTR_IO_EXTENT, "ibmtr")) {
694 DPRINTK("Could not grab PIO range. Halting driver.\n");
695 free_irq(dev->irq, dev);
696 iounmap(t_mmio);
697 return -EBUSY;
698 }
699
700 if (!version_printed++) {
701 printk(version);
702 }
703#endif /* !PCMCIA */
704 DPRINTK("%s %s found\n",
705 channel_def[cardpresent - 1], adapter_def(ti->adapter_type));
706 DPRINTK("using irq %d, PIOaddr %hx, %dK shared RAM.\n",
707 irq, PIOaddr, ti->mapped_ram_size / 2);
708 DPRINTK("Hardware address : %pM\n", dev->dev_addr);
709 if (ti->page_mask)
710 DPRINTK("Shared RAM paging enabled. "
711 "Page size: %uK Shared Ram size %dK\n",
712 ((ti->page_mask^0xff)+1) >>2, ti->avail_shared_ram / 2);
713 else
714 DPRINTK("Shared RAM paging disabled. ti->page_mask %x\n",
715 ti->page_mask);
716
717 /* Calculate the maximum DHB we can use */
718 /* two cases where avail_shared_ram doesn't equal mapped_ram_size:
719 1. avail_shared_ram is 127 but mapped_ram_size is 128 (typical)
720 2. user has configured adapter for less than avail_shared_ram
721 but is not using paging (she should use paging, I believe)
722 */
723 if (!ti->page_mask) {
724 ti->avail_shared_ram=
725 min(ti->mapped_ram_size,ti->avail_shared_ram);
726 }
727
728 switch (ti->avail_shared_ram) {
729 case 16: /* 8KB shared RAM */
730 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)2048);
731 ti->rbuf_len4 = 1032;
732 ti->rbuf_cnt4=2;
733 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)2048);
734 ti->rbuf_len16 = 1032;
735 ti->rbuf_cnt16=2;
736 break;
737 case 32: /* 16KB shared RAM */
738 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
739 ti->rbuf_len4 = 1032;
740 ti->rbuf_cnt4=4;
741 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)4096);
742 ti->rbuf_len16 = 1032; /*1024 usable */
743 ti->rbuf_cnt16=4;
744 break;
745 case 64: /* 32KB shared RAM */
746 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
747 ti->rbuf_len4 = 1032;
748 ti->rbuf_cnt4=6;
749 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)10240);
750 ti->rbuf_len16 = 1032;
751 ti->rbuf_cnt16=6;
752 break;
753 case 127: /* 63.5KB shared RAM */
754 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
755 ti->rbuf_len4 = 1032;
756 ti->rbuf_cnt4=6;
757 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)16384);
758 ti->rbuf_len16 = 1032;
759 ti->rbuf_cnt16=16;
760 break;
761 case 128: /* 64KB shared RAM */
762 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
763 ti->rbuf_len4 = 1032;
764 ti->rbuf_cnt4=6;
765 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)17960);
766 ti->rbuf_len16 = 1032;
767 ti->rbuf_cnt16=16;
768 break;
769 default:
770 ti->dhb_size4mb = 2048;
771 ti->rbuf_len4 = 1032;
772 ti->rbuf_cnt4=2;
773 ti->dhb_size16mb = 2048;
774 ti->rbuf_len16 = 1032;
775 ti->rbuf_cnt16=2;
776 break;
777 }
778 /* this formula is not smart enough for the paging case
779 ti->rbuf_cnt<x> = (ti->avail_shared_ram * BLOCKSZ - ADAPT_PRIVATE -
780 ARBLENGTH - SSBLENGTH - DLC_MAX_SAP * SAPLENGTH -
781 DLC_MAX_STA * STALENGTH - ti->dhb_size<x>mb * NUM_DHB -
782 SRBLENGTH - ASBLENGTH) / ti->rbuf_len<x>;
783 */
784 ti->maxmtu16 = (ti->rbuf_len16 - 8) * ti->rbuf_cnt16 - TR_HLEN;
785 ti->maxmtu4 = (ti->rbuf_len4 - 8) * ti->rbuf_cnt4 - TR_HLEN;
786 /*BMS assuming 18 bytes of Routing Information (usually works) */
787 DPRINTK("Maximum Receive Internet Protocol MTU 16Mbps: %d, 4Mbps: %d\n",
788 ti->maxmtu16, ti->maxmtu4);
789
790 dev->base_addr = PIOaddr; /* set the value for device */
791 dev->mem_start = ti->sram_base << 12;
792 dev->mem_end = dev->mem_start + (ti->mapped_ram_size << 9) - 1;
793 trdev_init(dev);
794 return 0; /* Return 0 to indicate we have found a Token Ring card. */
795} /*ibmtr_probe1() */
796
797/*****************************************************************************/
798
799/* query the adapter for the size of shared RAM */
800/* the function returns the RAM size in units of 512 bytes */
801
802static unsigned char __devinit get_sram_size(struct tok_info *adapt_info)
803{
804 unsigned char avail_sram_code;
805 static unsigned char size_code[] = { 0, 16, 32, 64, 127, 128 };
806 /* Adapter gives
807 'F' -- use RRR bits 3,2
808 'E' -- 8kb 'D' -- 16kb
809 'C' -- 32kb 'A' -- 64KB
810 'B' - 64KB less 512 bytes at top
811 (WARNING ... must zero top bytes in INIT */
812
813 avail_sram_code = 0xf - readb(adapt_info->mmio + AIPAVAILSHRAM);
814 if (avail_sram_code) return size_code[avail_sram_code];
815 else /* for code 'F', must compute size from RRR(3,2) bits */
816 return 1 <<
817 ((readb(adapt_info->mmio+ACA_OFFSET+ACA_RW+RRR_ODD)>>2&3)+4);
818}
819
820/*****************************************************************************/
821
822static const struct net_device_ops trdev_netdev_ops = {
823 .ndo_open = tok_open,
824 .ndo_stop = tok_close,
825 .ndo_start_xmit = tok_send_packet,
826 .ndo_set_rx_mode = tok_set_multicast_list,
827 .ndo_change_mtu = ibmtr_change_mtu,
828};
829
830static int __devinit trdev_init(struct net_device *dev)
831{
832 struct tok_info *ti = netdev_priv(dev);
833
834 SET_PAGE(ti->srb_page);
835 ti->open_failure = NO ;
836 dev->netdev_ops = &trdev_netdev_ops;
837
838 return 0;
839}
840
841/*****************************************************************************/
842
843static int tok_init_card(struct net_device *dev)
844{
845 struct tok_info *ti;
846 short PIOaddr;
847 unsigned long i;
848
849 PIOaddr = dev->base_addr;
850 ti = netdev_priv(dev);
851 /* Special processing for first interrupt after reset */
852 ti->do_tok_int = FIRST_INT;
853 /* Reset adapter */
854 writeb(~INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
855 outb(0, PIOaddr + ADAPTRESET);
856
857 schedule_timeout_uninterruptible(TR_RST_TIME); /* wait 50ms */
858
859 outb(0, PIOaddr + ADAPTRESETREL);
860#ifdef ENABLE_PAGING
861 if (ti->page_mask)
862 writeb(SRPR_ENABLE_PAGING,ti->mmio+ACA_OFFSET+ACA_RW+SRPR_EVEN);
863#endif
864 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
865 i = sleep_on_timeout(&ti->wait_for_reset, 4 * HZ);
866 return i? 0 : -EAGAIN;
867}
868
869/*****************************************************************************/
870static int tok_open(struct net_device *dev)
871{
872 struct tok_info *ti = netdev_priv(dev);
873 int i;
874
875 /*the case we were left in a failure state during a previous open */
876 if (ti->open_failure == YES) {
877 DPRINTK("Last time you were disconnected, how about now?\n");
878 printk("You can't insert with an ICS connector half-cocked.\n");
879 }
880
881 ti->open_status = CLOSED; /* CLOSED or OPEN */
882 ti->sap_status = CLOSED; /* CLOSED or OPEN */
883 ti->open_failure = NO; /* NO or YES */
884 ti->open_mode = MANUAL; /* MANUAL or AUTOMATIC */
885
886 ti->sram_phys &= ~1; /* to reverse what we do in tok_close */
887 /* init the spinlock */
888 spin_lock_init(&ti->lock);
889 init_timer(&ti->tr_timer);
890
891 i = tok_init_card(dev);
892 if (i) return i;
893
894 while (1){
895 tok_open_adapter((unsigned long) dev);
896 i= interruptible_sleep_on_timeout(&ti->wait_for_reset, 25 * HZ);
897 /* sig catch: estimate opening adapter takes more than .5 sec*/
898 if (i>(245*HZ)/10) break; /* fancier than if (i==25*HZ) */
899 if (i==0) break;
900 if (ti->open_status == OPEN && ti->sap_status==OPEN) {
901 netif_start_queue(dev);
902 DPRINTK("Adapter is up and running\n");
903 return 0;
904 }
905 i=schedule_timeout_interruptible(TR_RETRY_INTERVAL);
906 /* wait 30 seconds */
907 if(i!=0) break; /*prob. a signal, like the i>24*HZ case above */
908 }
909 outb(0, dev->base_addr + ADAPTRESET);/* kill pending interrupts*/
910 DPRINTK("TERMINATED via signal\n"); /*BMS useful */
911 return -EAGAIN;
912}
913
914/*****************************************************************************/
915
916#define COMMAND_OFST 0
917#define OPEN_OPTIONS_OFST 8
918#define NUM_RCV_BUF_OFST 24
919#define RCV_BUF_LEN_OFST 26
920#define DHB_LENGTH_OFST 28
921#define NUM_DHB_OFST 30
922#define DLC_MAX_SAP_OFST 32
923#define DLC_MAX_STA_OFST 33
924
925static void tok_open_adapter(unsigned long dev_addr)
926{
927 struct net_device *dev = (struct net_device *) dev_addr;
928 struct tok_info *ti;
929 int i;
930
931 ti = netdev_priv(dev);
932 SET_PAGE(ti->init_srb_page);
933 writeb(~SRB_RESP_INT, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_ODD);
934 for (i = 0; i < sizeof(struct dir_open_adapter); i++)
935 writeb(0, ti->init_srb + i);
936 writeb(DIR_OPEN_ADAPTER, ti->init_srb + COMMAND_OFST);
937 writew(htons(OPEN_PASS_BCON_MAC), ti->init_srb + OPEN_OPTIONS_OFST);
938 if (ti->ring_speed == 16) {
939 writew(htons(ti->dhb_size16mb), ti->init_srb + DHB_LENGTH_OFST);
940 writew(htons(ti->rbuf_cnt16), ti->init_srb + NUM_RCV_BUF_OFST);
941 writew(htons(ti->rbuf_len16), ti->init_srb + RCV_BUF_LEN_OFST);
942 } else {
943 writew(htons(ti->dhb_size4mb), ti->init_srb + DHB_LENGTH_OFST);
944 writew(htons(ti->rbuf_cnt4), ti->init_srb + NUM_RCV_BUF_OFST);
945 writew(htons(ti->rbuf_len4), ti->init_srb + RCV_BUF_LEN_OFST);
946 }
947 writeb(NUM_DHB, /* always 2 */ ti->init_srb + NUM_DHB_OFST);
948 writeb(DLC_MAX_SAP, ti->init_srb + DLC_MAX_SAP_OFST);
949 writeb(DLC_MAX_STA, ti->init_srb + DLC_MAX_STA_OFST);
950 ti->srb = ti->init_srb; /* We use this one in the interrupt handler */
951 ti->srb_page = ti->init_srb_page;
952 DPRINTK("Opening adapter: Xmit bfrs: %d X %d, Rcv bfrs: %d X %d\n",
953 readb(ti->init_srb + NUM_DHB_OFST),
954 ntohs(readw(ti->init_srb + DHB_LENGTH_OFST)),
955 ntohs(readw(ti->init_srb + NUM_RCV_BUF_OFST)),
956 ntohs(readw(ti->init_srb + RCV_BUF_LEN_OFST)));
957 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
958 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
959}
960
961/*****************************************************************************/
962
963static void open_sap(unsigned char type, struct net_device *dev)
964{
965 int i;
966 struct tok_info *ti = netdev_priv(dev);
967
968 SET_PAGE(ti->srb_page);
969 for (i = 0; i < sizeof(struct dlc_open_sap); i++)
970 writeb(0, ti->srb + i);
971
972#define MAX_I_FIELD_OFST 14
973#define SAP_VALUE_OFST 16
974#define SAP_OPTIONS_OFST 17
975#define STATION_COUNT_OFST 18
976
977 writeb(DLC_OPEN_SAP, ti->srb + COMMAND_OFST);
978 writew(htons(MAX_I_FIELD), ti->srb + MAX_I_FIELD_OFST);
979 writeb(SAP_OPEN_IND_SAP | SAP_OPEN_PRIORITY, ti->srb+ SAP_OPTIONS_OFST);
980 writeb(SAP_OPEN_STATION_CNT, ti->srb + STATION_COUNT_OFST);
981 writeb(type, ti->srb + SAP_VALUE_OFST);
982 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
983}
984
985
986/*****************************************************************************/
987
988static void tok_set_multicast_list(struct net_device *dev)
989{
990 struct tok_info *ti = netdev_priv(dev);
991 struct netdev_hw_addr *ha;
992 unsigned char address[4];
993
994 int i;
995
996 /*BMS the next line is CRUCIAL or you may be sad when you */
997 /*BMS ifconfig tr down or hot unplug a PCMCIA card ??hownowbrowncow*/
998 if (/*BMSHELPdev->start == 0 ||*/ ti->open_status != OPEN) return;
999 address[0] = address[1] = address[2] = address[3] = 0;
1000 netdev_for_each_mc_addr(ha, dev) {
1001 address[0] |= ha->addr[2];
1002 address[1] |= ha->addr[3];
1003 address[2] |= ha->addr[4];
1004 address[3] |= ha->addr[5];
1005 }
1006 SET_PAGE(ti->srb_page);
1007 for (i = 0; i < sizeof(struct srb_set_funct_addr); i++)
1008 writeb(0, ti->srb + i);
1009
1010#define FUNCT_ADDRESS_OFST 6
1011
1012 writeb(DIR_SET_FUNC_ADDR, ti->srb + COMMAND_OFST);
1013 for (i = 0; i < 4; i++)
1014 writeb(address[i], ti->srb + FUNCT_ADDRESS_OFST + i);
1015 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1016#if TR_VERBOSE
1017 DPRINTK("Setting functional address: ");
1018 for (i=0;i<4;i++) printk("%02X ", address[i]);
1019 printk("\n");
1020#endif
1021}
1022
1023/*****************************************************************************/
1024
1025#define STATION_ID_OFST 4
1026
1027static netdev_tx_t tok_send_packet(struct sk_buff *skb,
1028 struct net_device *dev)
1029{
1030 struct tok_info *ti;
1031 unsigned long flags;
1032 ti = netdev_priv(dev);
1033
1034 netif_stop_queue(dev);
1035
1036 /* lock against other CPUs */
1037 spin_lock_irqsave(&(ti->lock), flags);
1038
1039 /* Save skb; we'll need it when the adapter asks for the data */
1040 ti->current_skb = skb;
1041 SET_PAGE(ti->srb_page);
1042 writeb(XMIT_UI_FRAME, ti->srb + COMMAND_OFST);
1043 writew(ti->exsap_station_id, ti->srb + STATION_ID_OFST);
1044 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1045 spin_unlock_irqrestore(&(ti->lock), flags);
1046 return NETDEV_TX_OK;
1047}
1048
1049/*****************************************************************************/
1050
1051static int tok_close(struct net_device *dev)
1052{
1053 struct tok_info *ti = netdev_priv(dev);
1054
1055 /* Important for PCMCIA hot unplug, otherwise, we'll pull the card, */
1056 /* unloading the module from memory, and then if a timer pops, ouch */
1057 del_timer_sync(&ti->tr_timer);
1058 outb(0, dev->base_addr + ADAPTRESET);
1059 ti->sram_phys |= 1;
1060 ti->open_status = CLOSED;
1061
1062 netif_stop_queue(dev);
1063 DPRINTK("Adapter is closed.\n");
1064 return 0;
1065}
1066
1067/*****************************************************************************/
1068
1069#define RETCODE_OFST 2
1070#define OPEN_ERROR_CODE_OFST 6
1071#define ASB_ADDRESS_OFST 8
1072#define SRB_ADDRESS_OFST 10
1073#define ARB_ADDRESS_OFST 12
1074#define SSB_ADDRESS_OFST 14
1075
1076static char *printphase[]= {"Lobe media test","Physical insertion",
1077 "Address verification","Roll call poll","Request Parameters"};
1078static char *printerror[]={"Function failure","Signal loss","Reserved",
1079 "Frequency error","Timeout","Ring failure","Ring beaconing",
1080 "Duplicate node address",
1081 "Parameter request-retry count exceeded","Remove received",
1082 "IMPL force received","Duplicate modifier",
1083 "No monitor detected","Monitor contention failed for RPL"};
1084
1085static void __iomem *map_address(struct tok_info *ti, unsigned index, __u8 *page)
1086{
1087 if (ti->page_mask) {
1088 *page = (index >> 8) & ti->page_mask;
1089 index &= ~(ti->page_mask << 8);
1090 }
1091 return ti->sram_virt + index;
1092}
1093
1094static void dir_open_adapter (struct net_device *dev)
1095{
1096 struct tok_info *ti = netdev_priv(dev);
1097 unsigned char ret_code;
1098 __u16 err;
1099
1100 ti->srb = map_address(ti,
1101 ntohs(readw(ti->init_srb + SRB_ADDRESS_OFST)),
1102 &ti->srb_page);
1103 ti->ssb = map_address(ti,
1104 ntohs(readw(ti->init_srb + SSB_ADDRESS_OFST)),
1105 &ti->ssb_page);
1106 ti->arb = map_address(ti,
1107 ntohs(readw(ti->init_srb + ARB_ADDRESS_OFST)),
1108 &ti->arb_page);
1109 ti->asb = map_address(ti,
1110 ntohs(readw(ti->init_srb + ASB_ADDRESS_OFST)),
1111 &ti->asb_page);
1112 ti->current_skb = NULL;
1113 ret_code = readb(ti->init_srb + RETCODE_OFST);
1114 err = ntohs(readw(ti->init_srb + OPEN_ERROR_CODE_OFST));
1115 if (!ret_code) {
1116 ti->open_status = OPEN; /* TR adapter is now available */
1117 if (ti->open_mode == AUTOMATIC) {
1118 DPRINTK("Adapter reopened.\n");
1119 }
1120 writeb(~SRB_RESP_INT, ti->mmio+ACA_OFFSET+ACA_RESET+ISRP_ODD);
1121 open_sap(EXTENDED_SAP, dev);
1122 return;
1123 }
1124 ti->open_failure = YES;
1125 if (ret_code == 7){
1126 if (err == 0x24) {
1127 if (!ti->auto_speedsave) {
1128 DPRINTK("Open failed: Adapter speed must match "
1129 "ring speed if Automatic Ring Speed Save is "
1130 "disabled.\n");
1131 ti->open_action = FAIL;
1132 }else
1133 DPRINTK("Retrying open to adjust to "
1134 "ring speed, ");
1135 } else if (err == 0x2d) {
1136 DPRINTK("Physical Insertion: No Monitor Detected, ");
1137 printk("retrying after %ds delay...\n",
1138 TR_RETRY_INTERVAL/HZ);
1139 } else if (err == 0x11) {
1140 DPRINTK("Lobe Media Function Failure (0x11), ");
1141 printk(" retrying after %ds delay...\n",
1142 TR_RETRY_INTERVAL/HZ);
1143 } else {
1144 char **prphase = printphase;
1145 char **prerror = printerror;
1146 int pnr = err / 16 - 1;
1147 int enr = err % 16 - 1;
1148 DPRINTK("TR Adapter misc open failure, error code = ");
1149 if (pnr < 0 || pnr >= ARRAY_SIZE(printphase) ||
1150 enr < 0 ||
1151 enr >= ARRAY_SIZE(printerror))
1152 printk("0x%x, invalid Phase/Error.", err);
1153 else
1154 printk("0x%x, Phase: %s, Error: %s\n", err,
1155 prphase[pnr], prerror[enr]);
1156 printk(" retrying after %ds delay...\n",
1157 TR_RETRY_INTERVAL/HZ);
1158 }
1159 } else DPRINTK("open failed: ret_code = %02X..., ", ret_code);
1160 if (ti->open_action != FAIL) {
1161 if (ti->open_mode==AUTOMATIC){
1162 ti->open_action = REOPEN;
1163 ibmtr_reset_timer(&(ti->tr_timer), dev);
1164 return;
1165 }
1166 wake_up(&ti->wait_for_reset);
1167 return;
1168 }
1169 DPRINTK("FAILURE, CAPUT\n");
1170}
1171
1172/******************************************************************************/
1173
1174static irqreturn_t tok_interrupt(int irq, void *dev_id)
1175{
1176 unsigned char status;
1177 /* unsigned char status_even ; */
1178 struct tok_info *ti;
1179 struct net_device *dev;
1180#ifdef ENABLE_PAGING
1181 unsigned char save_srpr;
1182#endif
1183
1184 dev = dev_id;
1185#if TR_VERBOSE
1186 DPRINTK("Int from tok_driver, dev : %p irq%d\n", dev,irq);
1187#endif
1188 ti = netdev_priv(dev);
1189 if (ti->sram_phys & 1)
1190 return IRQ_NONE; /* PCMCIA card extraction flag */
1191 spin_lock(&(ti->lock));
1192#ifdef ENABLE_PAGING
1193 save_srpr = readb(ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1194#endif
1195
1196 /* Disable interrupts till processing is finished */
1197 writeb((~INT_ENABLE), ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1198
1199 /* Reset interrupt for ISA boards */
1200 if (ti->adapter_int_enable)
1201 outb(0, ti->adapter_int_enable);
1202 else /* used for PCMCIA cards */
1203 outb(0, ti->global_int_enable);
1204 if (ti->do_tok_int == FIRST_INT){
1205 initial_tok_int(dev);
1206#ifdef ENABLE_PAGING
1207 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1208#endif
1209 spin_unlock(&(ti->lock));
1210 return IRQ_HANDLED;
1211 }
1212 /* Begin interrupt handler HERE inline to avoid the extra
1213 levels of logic and call depth for the original solution. */
1214 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_ODD);
1215 /*BMSstatus_even = readb (ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN) */
1216 /*BMSdebugprintk("tok_interrupt: ISRP_ODD = 0x%x ISRP_EVEN = 0x%x\n", */
1217 /*BMS status,status_even); */
1218
1219 if (status & ADAP_CHK_INT) {
1220 int i;
1221 void __iomem *check_reason;
1222 __u8 check_reason_page = 0;
1223 check_reason = map_address(ti,
1224 ntohs(readw(ti->mmio+ ACA_OFFSET+ACA_RW + WWCR_EVEN)),
1225 &check_reason_page);
1226 SET_PAGE(check_reason_page);
1227
1228 DPRINTK("Adapter check interrupt\n");
1229 DPRINTK("8 reason bytes follow: ");
1230 for (i = 0; i < 8; i++, check_reason++)
1231 printk("%02X ", (int) readb(check_reason));
1232 printk("\n");
1233 writeb(~ADAP_CHK_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1234 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRA_EVEN);
1235 DPRINTK("ISRA_EVEN == 0x02%x\n",status);
1236 ti->open_status = CLOSED;
1237 ti->sap_status = CLOSED;
1238 ti->open_mode = AUTOMATIC;
1239 netif_carrier_off(dev);
1240 netif_stop_queue(dev);
1241 ti->open_action = RESTART;
1242 outb(0, dev->base_addr + ADAPTRESET);
1243 ibmtr_reset_timer(&(ti->tr_timer), dev);/*BMS try to reopen*/
1244 spin_unlock(&(ti->lock));
1245 return IRQ_HANDLED;
1246 }
1247 if (readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN)
1248 & (TCR_INT | ERR_INT | ACCESS_INT)) {
1249 DPRINTK("adapter error: ISRP_EVEN : %02x\n",
1250 (int)readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRP_EVEN));
1251 writeb(~(TCR_INT | ERR_INT | ACCESS_INT),
1252 ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1253 status= readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRA_EVEN);/*BMS*/
1254 DPRINTK("ISRA_EVEN == 0x02%x\n",status);/*BMS*/
1255 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1256#ifdef ENABLE_PAGING
1257 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1258#endif
1259 spin_unlock(&(ti->lock));
1260 return IRQ_HANDLED;
1261 }
1262 if (status & SRB_RESP_INT) { /* SRB response */
1263 SET_PAGE(ti->srb_page);
1264#if TR_VERBOSE
1265 DPRINTK("SRB resp: cmd=%02X rsp=%02X\n",
1266 readb(ti->srb), readb(ti->srb + RETCODE_OFST));
1267#endif
1268 switch (readb(ti->srb)) { /* SRB command check */
1269 case XMIT_DIR_FRAME:{
1270 unsigned char xmit_ret_code;
1271 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1272 if (xmit_ret_code == 0xff) break;
1273 DPRINTK("error on xmit_dir_frame request: %02X\n",
1274 xmit_ret_code);
1275 if (ti->current_skb) {
1276 dev_kfree_skb_irq(ti->current_skb);
1277 ti->current_skb = NULL;
1278 }
1279 /*dev->tbusy = 0;*/
1280 netif_wake_queue(dev);
1281 if (ti->readlog_pending)
1282 ibmtr_readlog(dev);
1283 break;
1284 }
1285 case XMIT_UI_FRAME:{
1286 unsigned char xmit_ret_code;
1287
1288 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1289 if (xmit_ret_code == 0xff) break;
1290 DPRINTK("error on xmit_ui_frame request: %02X\n",
1291 xmit_ret_code);
1292 if (ti->current_skb) {
1293 dev_kfree_skb_irq(ti->current_skb);
1294 ti->current_skb = NULL;
1295 }
1296 netif_wake_queue(dev);
1297 if (ti->readlog_pending)
1298 ibmtr_readlog(dev);
1299 break;
1300 }
1301 case DIR_OPEN_ADAPTER:
1302 dir_open_adapter(dev);
1303 break;
1304 case DLC_OPEN_SAP:
1305 if (readb(ti->srb + RETCODE_OFST)) {
1306 DPRINTK("open_sap failed: ret_code = %02X, "
1307 "retrying\n",
1308 (int) readb(ti->srb + RETCODE_OFST));
1309 ti->open_action = REOPEN;
1310 ibmtr_reset_timer(&(ti->tr_timer), dev);
1311 break;
1312 }
1313 ti->exsap_station_id = readw(ti->srb + STATION_ID_OFST);
1314 ti->sap_status = OPEN;/* TR adapter is now available */
1315 if (ti->open_mode==MANUAL){
1316 wake_up(&ti->wait_for_reset);
1317 break;
1318 }
1319 netif_wake_queue(dev);
1320 netif_carrier_on(dev);
1321 break;
1322 case DIR_INTERRUPT:
1323 case DIR_MOD_OPEN_PARAMS:
1324 case DIR_SET_GRP_ADDR:
1325 case DIR_SET_FUNC_ADDR:
1326 case DLC_CLOSE_SAP:
1327 if (readb(ti->srb + RETCODE_OFST))
1328 DPRINTK("error on %02X: %02X\n",
1329 (int) readb(ti->srb + COMMAND_OFST),
1330 (int) readb(ti->srb + RETCODE_OFST));
1331 break;
1332 case DIR_READ_LOG:
1333 if (readb(ti->srb + RETCODE_OFST)){
1334 DPRINTK("error on dir_read_log: %02X\n",
1335 (int) readb(ti->srb + RETCODE_OFST));
1336 netif_wake_queue(dev);
1337 break;
1338 }
1339#if IBMTR_DEBUG_MESSAGES
1340
1341#define LINE_ERRORS_OFST 0
1342#define INTERNAL_ERRORS_OFST 1
1343#define BURST_ERRORS_OFST 2
1344#define AC_ERRORS_OFST 3
1345#define ABORT_DELIMITERS_OFST 4
1346#define LOST_FRAMES_OFST 6
1347#define RECV_CONGEST_COUNT_OFST 7
1348#define FRAME_COPIED_ERRORS_OFST 8
1349#define FREQUENCY_ERRORS_OFST 9
1350#define TOKEN_ERRORS_OFST 10
1351
1352 DPRINTK("Line errors %02X, Internal errors %02X, "
1353 "Burst errors %02X\n" "A/C errors %02X, "
1354 "Abort delimiters %02X, Lost frames %02X\n"
1355 "Receive congestion count %02X, "
1356 "Frame copied errors %02X\nFrequency errors %02X, "
1357 "Token errors %02X\n",
1358 (int) readb(ti->srb + LINE_ERRORS_OFST),
1359 (int) readb(ti->srb + INTERNAL_ERRORS_OFST),
1360 (int) readb(ti->srb + BURST_ERRORS_OFST),
1361 (int) readb(ti->srb + AC_ERRORS_OFST),
1362 (int) readb(ti->srb + ABORT_DELIMITERS_OFST),
1363 (int) readb(ti->srb + LOST_FRAMES_OFST),
1364 (int) readb(ti->srb + RECV_CONGEST_COUNT_OFST),
1365 (int) readb(ti->srb + FRAME_COPIED_ERRORS_OFST),
1366 (int) readb(ti->srb + FREQUENCY_ERRORS_OFST),
1367 (int) readb(ti->srb + TOKEN_ERRORS_OFST));
1368#endif
1369 netif_wake_queue(dev);
1370 break;
1371 default:
1372 DPRINTK("Unknown command %02X encountered\n",
1373 (int) readb(ti->srb));
1374 } /* end switch SRB command check */
1375 writeb(~SRB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1376 } /* if SRB response */
1377 if (status & ASB_FREE_INT) { /* ASB response */
1378 SET_PAGE(ti->asb_page);
1379#if TR_VERBOSE
1380 DPRINTK("ASB resp: cmd=%02X\n", readb(ti->asb));
1381#endif
1382
1383 switch (readb(ti->asb)) { /* ASB command check */
1384 case REC_DATA:
1385 case XMIT_UI_FRAME:
1386 case XMIT_DIR_FRAME:
1387 break;
1388 default:
1389 DPRINTK("unknown command in asb %02X\n",
1390 (int) readb(ti->asb));
1391 } /* switch ASB command check */
1392 if (readb(ti->asb + 2) != 0xff) /* checks ret_code */
1393 DPRINTK("ASB error %02X in cmd %02X\n",
1394 (int) readb(ti->asb + 2), (int) readb(ti->asb));
1395 writeb(~ASB_FREE_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1396 } /* if ASB response */
1397
1398#define STATUS_OFST 6
1399#define NETW_STATUS_OFST 6
1400
1401 if (status & ARB_CMD_INT) { /* ARB response */
1402 SET_PAGE(ti->arb_page);
1403#if TR_VERBOSE
1404 DPRINTK("ARB resp: cmd=%02X\n", readb(ti->arb));
1405#endif
1406
1407 switch (readb(ti->arb)) { /* ARB command check */
1408 case DLC_STATUS:
1409 DPRINTK("DLC_STATUS new status: %02X on station %02X\n",
1410 ntohs(readw(ti->arb + STATUS_OFST)),
1411 ntohs(readw(ti->arb+ STATION_ID_OFST)));
1412 break;
1413 case REC_DATA:
1414 tr_rx(dev);
1415 break;
1416 case RING_STAT_CHANGE:{
1417 unsigned short ring_status;
1418 ring_status= ntohs(readw(ti->arb + NETW_STATUS_OFST));
1419 if (ibmtr_debug_trace & TRC_INIT)
1420 DPRINTK("Ring Status Change...(0x%x)\n",
1421 ring_status);
1422 if(ring_status& (REMOVE_RECV|AUTO_REMOVAL|LOBE_FAULT)){
1423 netif_stop_queue(dev);
1424 netif_carrier_off(dev);
1425 DPRINTK("Remove received, or Auto-removal error"
1426 ", or Lobe fault\n");
1427 DPRINTK("We'll try to reopen the closed adapter"
1428 " after a %d second delay.\n",
1429 TR_RETRY_INTERVAL/HZ);
1430 /*I was confused: I saw the TR reopening but */
1431 /*forgot:with an RJ45 in an RJ45/ICS adapter */
1432 /*but adapter not in the ring, the TR will */
1433 /* open, and then soon close and come here. */
1434 ti->open_mode = AUTOMATIC;
1435 ti->open_status = CLOSED; /*12/2000 BMS*/
1436 ti->open_action = REOPEN;
1437 ibmtr_reset_timer(&(ti->tr_timer), dev);
1438 } else if (ring_status & LOG_OVERFLOW) {
1439 if(netif_queue_stopped(dev))
1440 ti->readlog_pending = 1;
1441 else
1442 ibmtr_readlog(dev);
1443 }
1444 break;
1445 }
1446 case XMIT_DATA_REQ:
1447 tr_tx(dev);
1448 break;
1449 default:
1450 DPRINTK("Unknown command %02X in arb\n",
1451 (int) readb(ti->arb));
1452 break;
1453 } /* switch ARB command check */
1454 writeb(~ARB_CMD_INT, ti->mmio+ ACA_OFFSET+ACA_RESET + ISRP_ODD);
1455 writeb(ARB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1456 } /* if ARB response */
1457 if (status & SSB_RESP_INT) { /* SSB response */
1458 unsigned char retcode;
1459 SET_PAGE(ti->ssb_page);
1460#if TR_VERBOSE
1461 DPRINTK("SSB resp: cmd=%02X rsp=%02X\n",
1462 readb(ti->ssb), readb(ti->ssb + 2));
1463#endif
1464
1465 switch (readb(ti->ssb)) { /* SSB command check */
1466 case XMIT_DIR_FRAME:
1467 case XMIT_UI_FRAME:
1468 retcode = readb(ti->ssb + 2);
1469 if (retcode && (retcode != 0x22))/* checks ret_code */
1470 DPRINTK("xmit ret_code: %02X xmit error code: "
1471 "%02X\n",
1472 (int)retcode, (int)readb(ti->ssb + 6));
1473 else
1474 dev->stats.tx_packets++;
1475 break;
1476 case XMIT_XID_CMD:
1477 DPRINTK("xmit xid ret_code: %02X\n",
1478 (int) readb(ti->ssb + 2));
1479 default:
1480 DPRINTK("Unknown command %02X in ssb\n",
1481 (int) readb(ti->ssb));
1482 } /* SSB command check */
1483 writeb(~SSB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1484 writeb(SSB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1485 } /* if SSB response */
1486#ifdef ENABLE_PAGING
1487 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1488#endif
1489 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1490 spin_unlock(&(ti->lock));
1491 return IRQ_HANDLED;
1492} /*tok_interrupt */
1493
1494/*****************************************************************************/
1495
1496#define INIT_STATUS_OFST 1
1497#define INIT_STATUS_2_OFST 2
1498#define ENCODED_ADDRESS_OFST 8
1499
1500static void initial_tok_int(struct net_device *dev)
1501{
1502
1503 __u32 encoded_addr, hw_encoded_addr;
1504 struct tok_info *ti;
1505 unsigned char init_status; /*BMS 12/2000*/
1506
1507 ti = netdev_priv(dev);
1508
1509 ti->do_tok_int = NOT_FIRST;
1510
1511 /* we assign the shared-ram address for ISA devices */
1512 writeb(ti->sram_base, ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN);
1513#ifndef PCMCIA
1514 ti->sram_virt = ioremap(((__u32)ti->sram_base << 12), ti->avail_shared_ram);
1515#endif
1516 ti->init_srb = map_address(ti,
1517 ntohs(readw(ti->mmio + ACA_OFFSET + WRBR_EVEN)),
1518 &ti->init_srb_page);
1519 if (ti->page_mask && ti->avail_shared_ram == 127) {
1520 void __iomem *last_512;
1521 __u8 last_512_page=0;
1522 int i;
1523 last_512 = map_address(ti, 0xfe00, &last_512_page);
1524 /* initialize high section of ram (if necessary) */
1525 SET_PAGE(last_512_page);
1526 for (i = 0; i < 512; i++)
1527 writeb(0, last_512 + i);
1528 }
1529 SET_PAGE(ti->init_srb_page);
1530
1531#if TR_VERBOSE
1532 {
1533 int i;
1534
1535 DPRINTK("ti->init_srb_page=0x%x\n", ti->init_srb_page);
1536 DPRINTK("init_srb(%p):", ti->init_srb );
1537 for (i = 0; i < 20; i++)
1538 printk("%02X ", (int) readb(ti->init_srb + i));
1539 printk("\n");
1540 }
1541#endif
1542
1543 hw_encoded_addr = readw(ti->init_srb + ENCODED_ADDRESS_OFST);
1544 encoded_addr = ntohs(hw_encoded_addr);
1545 init_status= /*BMS 12/2000 check for shallow mode possibility (Turbo)*/
1546 readb(ti->init_srb+offsetof(struct srb_init_response,init_status));
1547 /*printk("Initial interrupt: init_status= 0x%02x\n",init_status);*/
1548 ti->ring_speed = init_status & 0x01 ? 16 : 4;
1549 DPRINTK("Initial interrupt : %d Mbps, shared RAM base %08x.\n",
1550 ti->ring_speed, (unsigned int)dev->mem_start);
1551 ti->auto_speedsave = (readb(ti->init_srb+INIT_STATUS_2_OFST) & 4) != 0;
1552
1553 if (ti->open_mode == MANUAL) wake_up(&ti->wait_for_reset);
1554 else tok_open_adapter((unsigned long)dev);
1555
1556} /*initial_tok_int() */
1557
1558/*****************************************************************************/
1559
1560#define CMD_CORRELATE_OFST 1
1561#define DHB_ADDRESS_OFST 6
1562
1563#define FRAME_LENGTH_OFST 6
1564#define HEADER_LENGTH_OFST 8
1565#define RSAP_VALUE_OFST 9
1566
1567static void tr_tx(struct net_device *dev)
1568{
1569 struct tok_info *ti = netdev_priv(dev);
1570 struct trh_hdr *trhdr = (struct trh_hdr *) ti->current_skb->data;
1571 unsigned int hdr_len;
1572 __u32 dhb=0,dhb_base;
1573 void __iomem *dhbuf = NULL;
1574 unsigned char xmit_command;
1575 int i,dhb_len=0x4000,src_len,src_offset;
1576 struct trllc *llc;
1577 struct srb_xmit xsrb;
1578 __u8 dhb_page = 0;
1579 __u8 llc_ssap;
1580
1581 SET_PAGE(ti->asb_page);
1582
1583 if (readb(ti->asb+RETCODE_OFST) != 0xFF) DPRINTK("ASB not free !!!\n");
1584
1585 /* in providing the transmit interrupts, is telling us it is ready for
1586 data and providing a shared memory address for us to stuff with data.
1587 Here we compute the effective address where we will place data.
1588 */
1589 SET_PAGE(ti->arb_page);
1590 dhb=dhb_base=ntohs(readw(ti->arb + DHB_ADDRESS_OFST));
1591 if (ti->page_mask) {
1592 dhb_page = (dhb_base >> 8) & ti->page_mask;
1593 dhb=dhb_base & ~(ti->page_mask << 8);
1594 }
1595 dhbuf = ti->sram_virt + dhb;
1596
1597 /* Figure out the size of the 802.5 header */
1598 if (!(trhdr->saddr[0] & 0x80)) /* RIF present? */
1599 hdr_len = sizeof(struct trh_hdr) - TR_MAXRIFLEN;
1600 else
1601 hdr_len = ((ntohs(trhdr->rcf) & TR_RCF_LEN_MASK) >> 8)
1602 + sizeof(struct trh_hdr) - TR_MAXRIFLEN;
1603
1604 llc = (struct trllc *) (ti->current_skb->data + hdr_len);
1605
1606 llc_ssap = llc->ssap;
1607 SET_PAGE(ti->srb_page);
1608 memcpy_fromio(&xsrb, ti->srb, sizeof(xsrb));
1609 SET_PAGE(ti->asb_page);
1610 xmit_command = xsrb.command;
1611
1612 writeb(xmit_command, ti->asb + COMMAND_OFST);
1613 writew(xsrb.station_id, ti->asb + STATION_ID_OFST);
1614 writeb(llc_ssap, ti->asb + RSAP_VALUE_OFST);
1615 writeb(xsrb.cmd_corr, ti->asb + CMD_CORRELATE_OFST);
1616 writeb(0, ti->asb + RETCODE_OFST);
1617 if ((xmit_command == XMIT_XID_CMD) || (xmit_command == XMIT_TEST_CMD)) {
1618 writew(htons(0x11), ti->asb + FRAME_LENGTH_OFST);
1619 writeb(0x0e, ti->asb + HEADER_LENGTH_OFST);
1620 SET_PAGE(dhb_page);
1621 writeb(AC, dhbuf);
1622 writeb(LLC_FRAME, dhbuf + 1);
1623 for (i = 0; i < TR_ALEN; i++)
1624 writeb((int) 0x0FF, dhbuf + i + 2);
1625 for (i = 0; i < TR_ALEN; i++)
1626 writeb(0, dhbuf + i + TR_ALEN + 2);
1627 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1628 return;
1629 }
1630 /*
1631 * the token ring packet is copied from sk_buff to the adapter
1632 * buffer identified in the command data received with the interrupt.
1633 */
1634 writeb(hdr_len, ti->asb + HEADER_LENGTH_OFST);
1635 writew(htons(ti->current_skb->len), ti->asb + FRAME_LENGTH_OFST);
1636 src_len=ti->current_skb->len;
1637 src_offset=0;
1638 dhb=dhb_base;
1639 while(1) {
1640 if (ti->page_mask) {
1641 dhb_page=(dhb >> 8) & ti->page_mask;
1642 dhb=dhb & ~(ti->page_mask << 8);
1643 dhb_len=0x4000-dhb; /* remaining size of this page */
1644 }
1645 dhbuf = ti->sram_virt + dhb;
1646 SET_PAGE(dhb_page);
1647 if (src_len > dhb_len) {
1648 memcpy_toio(dhbuf,&ti->current_skb->data[src_offset],
1649 dhb_len);
1650 src_len -= dhb_len;
1651 src_offset += dhb_len;
1652 dhb_base+=dhb_len;
1653 dhb=dhb_base;
1654 continue;
1655 }
1656 memcpy_toio(dhbuf, &ti->current_skb->data[src_offset], src_len);
1657 break;
1658 }
1659 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1660 dev->stats.tx_bytes += ti->current_skb->len;
1661 dev_kfree_skb_irq(ti->current_skb);
1662 ti->current_skb = NULL;
1663 netif_wake_queue(dev);
1664 if (ti->readlog_pending)
1665 ibmtr_readlog(dev);
1666} /*tr_tx */
1667
1668/*****************************************************************************/
1669
1670
1671#define RECEIVE_BUFFER_OFST 6
1672#define LAN_HDR_LENGTH_OFST 8
1673#define DLC_HDR_LENGTH_OFST 9
1674
1675#define DSAP_OFST 0
1676#define SSAP_OFST 1
1677#define LLC_OFST 2
1678#define PROTID_OFST 3
1679#define ETHERTYPE_OFST 6
1680
1681static void tr_rx(struct net_device *dev)
1682{
1683 struct tok_info *ti = netdev_priv(dev);
1684 __u32 rbuffer;
1685 void __iomem *rbuf, *rbufdata, *llc;
1686 __u8 rbuffer_page = 0;
1687 unsigned char *data;
1688 unsigned int rbuffer_len, lan_hdr_len, hdr_len, ip_len, length;
1689 unsigned char dlc_hdr_len;
1690 struct sk_buff *skb;
1691 unsigned int skb_size = 0;
1692 int IPv4_p = 0;
1693 unsigned int chksum = 0;
1694 struct iphdr *iph;
1695 struct arb_rec_req rarb;
1696
1697 SET_PAGE(ti->arb_page);
1698 memcpy_fromio(&rarb, ti->arb, sizeof(rarb));
1699 rbuffer = ntohs(rarb.rec_buf_addr) ;
1700 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1701
1702 SET_PAGE(ti->asb_page);
1703
1704 if (readb(ti->asb + RETCODE_OFST) !=0xFF) DPRINTK("ASB not free !!!\n");
1705
1706 writeb(REC_DATA, ti->asb + COMMAND_OFST);
1707 writew(rarb.station_id, ti->asb + STATION_ID_OFST);
1708 writew(rarb.rec_buf_addr, ti->asb + RECEIVE_BUFFER_OFST);
1709
1710 lan_hdr_len = rarb.lan_hdr_len;
1711 if (lan_hdr_len > sizeof(struct trh_hdr)) {
1712 DPRINTK("Linux cannot handle greater than 18 bytes RIF\n");
1713 return;
1714 } /*BMS I added this above just to be very safe */
1715 dlc_hdr_len = readb(ti->arb + DLC_HDR_LENGTH_OFST);
1716 hdr_len = lan_hdr_len + sizeof(struct trllc) + sizeof(struct iphdr);
1717
1718 SET_PAGE(rbuffer_page);
1719 llc = rbuf + offsetof(struct rec_buf, data) + lan_hdr_len;
1720
1721#if TR_VERBOSE
1722 DPRINTK("offsetof data: %02X lan_hdr_len: %02X\n",
1723 (__u32) offsetof(struct rec_buf, data), (unsigned int) lan_hdr_len);
1724 DPRINTK("llc: %08X rec_buf_addr: %04X dev->mem_start: %lX\n",
1725 llc, ntohs(rarb.rec_buf_addr), dev->mem_start);
1726 DPRINTK("dsap: %02X, ssap: %02X, llc: %02X, protid: %02X%02X%02X, "
1727 "ethertype: %04X\n",
1728 (int) readb(llc + DSAP_OFST), (int) readb(llc + SSAP_OFST),
1729 (int) readb(llc + LLC_OFST), (int) readb(llc + PROTID_OFST),
1730 (int) readb(llc+PROTID_OFST+1),(int)readb(llc+PROTID_OFST + 2),
1731 (int) ntohs(readw(llc + ETHERTYPE_OFST)));
1732#endif
1733 if (readb(llc + offsetof(struct trllc, llc)) != UI_CMD) {
1734 SET_PAGE(ti->asb_page);
1735 writeb(DATA_LOST, ti->asb + RETCODE_OFST);
1736 dev->stats.rx_dropped++;
1737 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1738 return;
1739 }
1740 length = ntohs(rarb.frame_len);
1741 if (readb(llc + DSAP_OFST) == EXTENDED_SAP &&
1742 readb(llc + SSAP_OFST) == EXTENDED_SAP &&
1743 length >= hdr_len) IPv4_p = 1;
1744#if TR_VERBOSE
1745#define SADDR_OFST 8
1746#define DADDR_OFST 2
1747
1748 if (!IPv4_p) {
1749
1750 void __iomem *trhhdr = rbuf + offsetof(struct rec_buf, data);
1751 u8 saddr[6];
1752 u8 daddr[6];
1753 int i;
1754 for (i = 0 ; i < 6 ; i++)
1755 saddr[i] = readb(trhhdr + SADDR_OFST + i);
1756 for (i = 0 ; i < 6 ; i++)
1757 daddr[i] = readb(trhhdr + DADDR_OFST + i);
1758 DPRINTK("Probably non-IP frame received.\n");
1759 DPRINTK("ssap: %02X dsap: %02X "
1760 "saddr: %pM daddr: %pM\n",
1761 readb(llc + SSAP_OFST), readb(llc + DSAP_OFST),
1762 saddr, daddr);
1763 }
1764#endif
1765
1766 /*BMS handle the case she comes in with few hops but leaves with many */
1767 skb_size=length-lan_hdr_len+sizeof(struct trh_hdr)+sizeof(struct trllc);
1768
1769 if (!(skb = dev_alloc_skb(skb_size))) {
1770 DPRINTK("out of memory. frame dropped.\n");
1771 dev->stats.rx_dropped++;
1772 SET_PAGE(ti->asb_page);
1773 writeb(DATA_LOST, ti->asb + offsetof(struct asb_rec, ret_code));
1774 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1775 return;
1776 }
1777 /*BMS again, if she comes in with few but leaves with many */
1778 skb_reserve(skb, sizeof(struct trh_hdr) - lan_hdr_len);
1779 skb_put(skb, length);
1780 data = skb->data;
1781 rbuffer_len = ntohs(readw(rbuf + offsetof(struct rec_buf, buf_len)));
1782 rbufdata = rbuf + offsetof(struct rec_buf, data);
1783
1784 if (IPv4_p) {
1785 /* Copy the headers without checksumming */
1786 memcpy_fromio(data, rbufdata, hdr_len);
1787
1788 /* Watch for padded packets and bogons */
1789 iph= (struct iphdr *)(data+ lan_hdr_len + sizeof(struct trllc));
1790 ip_len = ntohs(iph->tot_len) - sizeof(struct iphdr);
1791 length -= hdr_len;
1792 if ((ip_len <= length) && (ip_len > 7))
1793 length = ip_len;
1794 data += hdr_len;
1795 rbuffer_len -= hdr_len;
1796 rbufdata += hdr_len;
1797 }
1798 /* Copy the payload... */
1799#define BUFFER_POINTER_OFST 2
1800#define BUFFER_LENGTH_OFST 6
1801 for (;;) {
1802 if (ibmtr_debug_trace&TRC_INITV && length < rbuffer_len)
1803 DPRINTK("CURIOUS, length=%d < rbuffer_len=%d\n",
1804 length,rbuffer_len);
1805 if (IPv4_p)
1806 chksum=csum_partial_copy_nocheck((void*)rbufdata,
1807 data,length<rbuffer_len?length:rbuffer_len,chksum);
1808 else
1809 memcpy_fromio(data, rbufdata, rbuffer_len);
1810 rbuffer = ntohs(readw(rbuf+BUFFER_POINTER_OFST)) ;
1811 if (!rbuffer)
1812 break;
1813 rbuffer -= 2;
1814 length -= rbuffer_len;
1815 data += rbuffer_len;
1816 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1817 SET_PAGE(rbuffer_page);
1818 rbuffer_len = ntohs(readw(rbuf + BUFFER_LENGTH_OFST));
1819 rbufdata = rbuf + offsetof(struct rec_buf, data);
1820 }
1821
1822 SET_PAGE(ti->asb_page);
1823 writeb(0, ti->asb + offsetof(struct asb_rec, ret_code));
1824
1825 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1826
1827 dev->stats.rx_bytes += skb->len;
1828 dev->stats.rx_packets++;
1829
1830 skb->protocol = tr_type_trans(skb, dev);
1831 if (IPv4_p) {
1832 skb->csum = chksum;
1833 skb->ip_summed = CHECKSUM_COMPLETE;
1834 }
1835 netif_rx(skb);
1836} /*tr_rx */
1837
1838/*****************************************************************************/
1839
1840static void ibmtr_reset_timer(struct timer_list *tmr, struct net_device *dev)
1841{
1842 tmr->expires = jiffies + TR_RETRY_INTERVAL;
1843 tmr->data = (unsigned long) dev;
1844 tmr->function = tok_rerun;
1845 init_timer(tmr);
1846 add_timer(tmr);
1847}
1848
1849/*****************************************************************************/
1850
1851static void tok_rerun(unsigned long dev_addr)
1852{
1853 struct net_device *dev = (struct net_device *)dev_addr;
1854 struct tok_info *ti = netdev_priv(dev);
1855
1856 if ( ti->open_action == RESTART){
1857 ti->do_tok_int = FIRST_INT;
1858 outb(0, dev->base_addr + ADAPTRESETREL);
1859#ifdef ENABLE_PAGING
1860 if (ti->page_mask)
1861 writeb(SRPR_ENABLE_PAGING,
1862 ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1863#endif
1864
1865 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1866 } else
1867 tok_open_adapter(dev_addr);
1868}
1869
1870/*****************************************************************************/
1871
1872static void ibmtr_readlog(struct net_device *dev)
1873{
1874 struct tok_info *ti;
1875
1876 ti = netdev_priv(dev);
1877
1878 ti->readlog_pending = 0;
1879 SET_PAGE(ti->srb_page);
1880 writeb(DIR_READ_LOG, ti->srb);
1881 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1882 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1883
1884 netif_stop_queue(dev);
1885
1886}
1887
1888/*****************************************************************************/
1889
1890static int ibmtr_change_mtu(struct net_device *dev, int mtu)
1891{
1892 struct tok_info *ti = netdev_priv(dev);
1893
1894 if (ti->ring_speed == 16 && mtu > ti->maxmtu16)
1895 return -EINVAL;
1896 if (ti->ring_speed == 4 && mtu > ti->maxmtu4)
1897 return -EINVAL;
1898 dev->mtu = mtu;
1899 return 0;
1900}
1901
1902/*****************************************************************************/
1903#ifdef MODULE
1904
1905/* 3COM 3C619C supports 8 interrupts, 32 I/O ports */
1906static struct net_device *dev_ibmtr[IBMTR_MAX_ADAPTERS];
1907static int io[IBMTR_MAX_ADAPTERS] = { 0xa20, 0xa24 };
1908static int irq[IBMTR_MAX_ADAPTERS];
1909static int mem[IBMTR_MAX_ADAPTERS];
1910
1911MODULE_LICENSE("GPL");
1912
1913module_param_array(io, int, NULL, 0);
1914module_param_array(irq, int, NULL, 0);
1915module_param_array(mem, int, NULL, 0);
1916
1917static int __init ibmtr_init(void)
1918{
1919 int i;
1920 int count=0;
1921
1922 find_turbo_adapters(io);
1923
1924 for (i = 0; i < IBMTR_MAX_ADAPTERS && io[i]; i++) {
1925 struct net_device *dev;
1926 irq[i] = 0;
1927 mem[i] = 0;
1928 dev = alloc_trdev(sizeof(struct tok_info));
1929 if (dev == NULL) {
1930 if (i == 0)
1931 return -ENOMEM;
1932 break;
1933 }
1934 dev->base_addr = io[i];
1935 dev->irq = irq[i];
1936 dev->mem_start = mem[i];
1937
1938 if (ibmtr_probe_card(dev)) {
1939 free_netdev(dev);
1940 continue;
1941 }
1942 dev_ibmtr[i] = dev;
1943 count++;
1944 }
1945 if (count) return 0;
1946 printk("ibmtr: register_netdev() returned non-zero.\n");
1947 return -EIO;
1948}
1949module_init(ibmtr_init);
1950
1951static void __exit ibmtr_cleanup(void)
1952{
1953 int i;
1954
1955 for (i = 0; i < IBMTR_MAX_ADAPTERS; i++){
1956 if (!dev_ibmtr[i])
1957 continue;
1958 unregister_netdev(dev_ibmtr[i]);
1959 ibmtr_cleanup_card(dev_ibmtr[i]);
1960 free_netdev(dev_ibmtr[i]);
1961 }
1962}
1963module_exit(ibmtr_cleanup);
1964#endif
diff --git a/drivers/net/tokenring/ibmtr_cs.c b/drivers/net/tokenring/ibmtr_cs.c
deleted file mode 100644
index 356e28e4881b..000000000000
--- a/drivers/net/tokenring/ibmtr_cs.c
+++ /dev/null
@@ -1,370 +0,0 @@
1/*======================================================================
2
3 A PCMCIA token-ring driver for IBM-based cards
4
5 This driver supports the IBM PCMCIA Token-Ring Card.
6 Written by Steve Kipisz, kipisz@vnet.ibm.com or
7 bungy@ibm.net
8
9 Written 1995,1996.
10
11 This code is based on pcnet_cs.c from David Hinds.
12
13 V2.2.0 February 1999 - Mike Phillips phillim@amtrak.com
14
15 Linux V2.2.x presented significant changes to the underlying
16 ibmtr.c code. Mainly the code became a lot more organized and
17 modular.
18
19 This caused the old PCMCIA Token Ring driver to give up and go
20 home early. Instead of just patching the old code to make it
21 work, the PCMCIA code has been streamlined, updated and possibly
22 improved.
23
24 This code now only contains code required for the Card Services.
25 All we do here is set the card up enough so that the real ibmtr.c
26 driver can find it and work with it properly.
27
28 i.e. We set up the io port, irq, mmio memory and shared ram
29 memory. This enables ibmtr_probe in ibmtr.c to find the card and
30 configure it as though it was a normal ISA and/or PnP card.
31
32 CHANGES
33
34 v2.2.5 April 1999 Mike Phillips (phillim@amtrak.com)
35 Obscure bug fix, required changed to ibmtr.c not ibmtr_cs.c
36
37 v2.2.7 May 1999 Mike Phillips (phillim@amtrak.com)
38 Updated to version 2.2.7 to match the first version of the kernel
39 that the modification to ibmtr.c were incorporated into.
40
41 v2.2.17 July 2000 Burt Silverman (burts@us.ibm.com)
42 Address translation feature of PCMCIA controller is usable so
43 memory windows can be placed in High memory (meaning above
44 0xFFFFF.)
45
46======================================================================*/
47
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50#include <linux/kernel.h>
51#include <linux/init.h>
52#include <linux/ptrace.h>
53#include <linux/slab.h>
54#include <linux/string.h>
55#include <linux/timer.h>
56#include <linux/module.h>
57#include <linux/netdevice.h>
58#include <linux/trdevice.h>
59#include <linux/ibmtr.h>
60
61#include <pcmcia/cistpl.h>
62#include <pcmcia/ds.h>
63
64#include <asm/uaccess.h>
65#include <asm/io.h>
66
67#define PCMCIA
68#include "ibmtr.c"
69
70
71/*====================================================================*/
72
73/* Parameters that can be set with 'insmod' */
74
75/* MMIO base address */
76static u_long mmiobase = 0xce000;
77
78/* SRAM base address */
79static u_long srambase = 0xd0000;
80
81/* SRAM size 8,16,32,64 */
82static u_long sramsize = 64;
83
84/* Ringspeed 4,16 */
85static int ringspeed = 16;
86
87module_param(mmiobase, ulong, 0);
88module_param(srambase, ulong, 0);
89module_param(sramsize, ulong, 0);
90module_param(ringspeed, int, 0);
91MODULE_LICENSE("GPL");
92
93/*====================================================================*/
94
95static int ibmtr_config(struct pcmcia_device *link);
96static void ibmtr_hw_setup(struct net_device *dev, u_int mmiobase);
97static void ibmtr_release(struct pcmcia_device *link);
98static void ibmtr_detach(struct pcmcia_device *p_dev);
99
100/*====================================================================*/
101
102typedef struct ibmtr_dev_t {
103 struct pcmcia_device *p_dev;
104 struct net_device *dev;
105 struct tok_info *ti;
106} ibmtr_dev_t;
107
108static irqreturn_t ibmtr_interrupt(int irq, void *dev_id) {
109 ibmtr_dev_t *info = dev_id;
110 struct net_device *dev = info->dev;
111 return tok_interrupt(irq, dev);
112};
113
114static int __devinit ibmtr_attach(struct pcmcia_device *link)
115{
116 ibmtr_dev_t *info;
117 struct net_device *dev;
118
119 dev_dbg(&link->dev, "ibmtr_attach()\n");
120
121 /* Create new token-ring device */
122 info = kzalloc(sizeof(*info), GFP_KERNEL);
123 if (!info) return -ENOMEM;
124 dev = alloc_trdev(sizeof(struct tok_info));
125 if (!dev) {
126 kfree(info);
127 return -ENOMEM;
128 }
129
130 info->p_dev = link;
131 link->priv = info;
132 info->ti = netdev_priv(dev);
133
134 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
135 link->resource[0]->end = 4;
136 link->config_flags |= CONF_ENABLE_IRQ;
137 link->config_regs = PRESENT_OPTION;
138
139 info->dev = dev;
140
141 return ibmtr_config(link);
142} /* ibmtr_attach */
143
144static void ibmtr_detach(struct pcmcia_device *link)
145{
146 struct ibmtr_dev_t *info = link->priv;
147 struct net_device *dev = info->dev;
148 struct tok_info *ti = netdev_priv(dev);
149
150 dev_dbg(&link->dev, "ibmtr_detach\n");
151
152 /*
153 * When the card removal interrupt hits tok_interrupt(),
154 * bail out early, so we don't crash the machine
155 */
156 ti->sram_phys |= 1;
157
158 unregister_netdev(dev);
159
160 del_timer_sync(&(ti->tr_timer));
161
162 ibmtr_release(link);
163
164 free_netdev(dev);
165 kfree(info);
166} /* ibmtr_detach */
167
168static int __devinit ibmtr_config(struct pcmcia_device *link)
169{
170 ibmtr_dev_t *info = link->priv;
171 struct net_device *dev = info->dev;
172 struct tok_info *ti = netdev_priv(dev);
173 int i, ret;
174
175 dev_dbg(&link->dev, "ibmtr_config\n");
176
177 link->io_lines = 16;
178 link->config_index = 0x61;
179
180 /* Determine if this is PRIMARY or ALTERNATE. */
181
182 /* Try PRIMARY card at 0xA20-0xA23 */
183 link->resource[0]->start = 0xA20;
184 i = pcmcia_request_io(link);
185 if (i != 0) {
186 /* Couldn't get 0xA20-0xA23. Try ALTERNATE at 0xA24-0xA27. */
187 link->resource[0]->start = 0xA24;
188 ret = pcmcia_request_io(link);
189 if (ret)
190 goto failed;
191 }
192 dev->base_addr = link->resource[0]->start;
193
194 ret = pcmcia_request_exclusive_irq(link, ibmtr_interrupt);
195 if (ret)
196 goto failed;
197 dev->irq = link->irq;
198 ti->irq = link->irq;
199 ti->global_int_enable=GLOBAL_INT_ENABLE+((dev->irq==9) ? 2 : dev->irq);
200
201 /* Allocate the MMIO memory window */
202 link->resource[2]->flags |= WIN_DATA_WIDTH_16|WIN_MEMORY_TYPE_CM|WIN_ENABLE;
203 link->resource[2]->flags |= WIN_USE_WAIT;
204 link->resource[2]->start = 0;
205 link->resource[2]->end = 0x2000;
206 ret = pcmcia_request_window(link, link->resource[2], 250);
207 if (ret)
208 goto failed;
209
210 ret = pcmcia_map_mem_page(link, link->resource[2], mmiobase);
211 if (ret)
212 goto failed;
213 ti->mmio = ioremap(link->resource[2]->start,
214 resource_size(link->resource[2]));
215
216 /* Allocate the SRAM memory window */
217 link->resource[3]->flags = WIN_DATA_WIDTH_16|WIN_MEMORY_TYPE_CM|WIN_ENABLE;
218 link->resource[3]->flags |= WIN_USE_WAIT;
219 link->resource[3]->start = 0;
220 link->resource[3]->end = sramsize * 1024;
221 ret = pcmcia_request_window(link, link->resource[3], 250);
222 if (ret)
223 goto failed;
224
225 ret = pcmcia_map_mem_page(link, link->resource[3], srambase);
226 if (ret)
227 goto failed;
228
229 ti->sram_base = srambase >> 12;
230 ti->sram_virt = ioremap(link->resource[3]->start,
231 resource_size(link->resource[3]));
232 ti->sram_phys = link->resource[3]->start;
233
234 ret = pcmcia_enable_device(link);
235 if (ret)
236 goto failed;
237
238 /* Set up the Token-Ring Controller Configuration Register and
239 turn on the card. Check the "Local Area Network Credit Card
240 Adapters Technical Reference" SC30-3585 for this info. */
241 ibmtr_hw_setup(dev, mmiobase);
242
243 SET_NETDEV_DEV(dev, &link->dev);
244
245 i = ibmtr_probe_card(dev);
246 if (i != 0) {
247 pr_notice("register_netdev() failed\n");
248 goto failed;
249 }
250
251 netdev_info(dev, "port %#3lx, irq %d, mmio %#5lx, sram %#5lx, hwaddr=%pM\n",
252 dev->base_addr, dev->irq,
253 (u_long)ti->mmio, (u_long)(ti->sram_base << 12),
254 dev->dev_addr);
255 return 0;
256
257failed:
258 ibmtr_release(link);
259 return -ENODEV;
260} /* ibmtr_config */
261
262static void ibmtr_release(struct pcmcia_device *link)
263{
264 ibmtr_dev_t *info = link->priv;
265 struct net_device *dev = info->dev;
266
267 dev_dbg(&link->dev, "ibmtr_release\n");
268
269 if (link->resource[2]->end) {
270 struct tok_info *ti = netdev_priv(dev);
271 iounmap(ti->mmio);
272 }
273 pcmcia_disable_device(link);
274}
275
276static int ibmtr_suspend(struct pcmcia_device *link)
277{
278 ibmtr_dev_t *info = link->priv;
279 struct net_device *dev = info->dev;
280
281 if (link->open)
282 netif_device_detach(dev);
283
284 return 0;
285}
286
287static int __devinit ibmtr_resume(struct pcmcia_device *link)
288{
289 ibmtr_dev_t *info = link->priv;
290 struct net_device *dev = info->dev;
291
292 if (link->open) {
293 ibmtr_probe(dev); /* really? */
294 netif_device_attach(dev);
295 }
296
297 return 0;
298}
299
300
301/*====================================================================*/
302
303static void ibmtr_hw_setup(struct net_device *dev, u_int mmiobase)
304{
305 int i;
306
307 /* Bizarre IBM behavior, there are 16 bits of information we
308 need to set, but the card only allows us to send 4 bits at a
309 time. For each byte sent to base_addr, bits 7-4 tell the
310 card which part of the 16 bits we are setting, bits 3-0 contain
311 the actual information */
312
313 /* First nibble provides 4 bits of mmio */
314 i = (mmiobase >> 16) & 0x0F;
315 outb(i, dev->base_addr);
316
317 /* Second nibble provides 3 bits of mmio */
318 i = 0x10 | ((mmiobase >> 12) & 0x0E);
319 outb(i, dev->base_addr);
320
321 /* Third nibble, hard-coded values */
322 i = 0x26;
323 outb(i, dev->base_addr);
324
325 /* Fourth nibble sets shared ram page size */
326
327 /* 8 = 00, 16 = 01, 32 = 10, 64 = 11 */
328 i = (sramsize >> 4) & 0x07;
329 i = ((i == 4) ? 3 : i) << 2;
330 i |= 0x30;
331
332 if (ringspeed == 16)
333 i |= 2;
334 if (dev->base_addr == 0xA24)
335 i |= 1;
336 outb(i, dev->base_addr);
337
338 /* 0x40 will release the card for use */
339 outb(0x40, dev->base_addr);
340}
341
342static const struct pcmcia_device_id ibmtr_ids[] = {
343 PCMCIA_DEVICE_PROD_ID12("3Com", "TokenLink Velocity PC Card", 0x41240e5b, 0x82c3734e),
344 PCMCIA_DEVICE_PROD_ID12("IBM", "TOKEN RING", 0xb569a6e5, 0xbf8eed47),
345 PCMCIA_DEVICE_NULL,
346};
347MODULE_DEVICE_TABLE(pcmcia, ibmtr_ids);
348
349static struct pcmcia_driver ibmtr_cs_driver = {
350 .owner = THIS_MODULE,
351 .name = "ibmtr_cs",
352 .probe = ibmtr_attach,
353 .remove = ibmtr_detach,
354 .id_table = ibmtr_ids,
355 .suspend = ibmtr_suspend,
356 .resume = ibmtr_resume,
357};
358
359static int __init init_ibmtr_cs(void)
360{
361 return pcmcia_register_driver(&ibmtr_cs_driver);
362}
363
364static void __exit exit_ibmtr_cs(void)
365{
366 pcmcia_unregister_driver(&ibmtr_cs_driver);
367}
368
369module_init(init_ibmtr_cs);
370module_exit(exit_ibmtr_cs);
diff --git a/drivers/net/tokenring/lanstreamer.c b/drivers/net/tokenring/lanstreamer.c
deleted file mode 100644
index 97e4c65c1e29..000000000000
--- a/drivers/net/tokenring/lanstreamer.c
+++ /dev/null
@@ -1,1909 +0,0 @@
1/*
2 * lanstreamer.c -- driver for the IBM Auto LANStreamer PCI Adapter
3 *
4 * Written By: Mike Sullivan, IBM Corporation
5 *
6 * Copyright (C) 1999 IBM Corporation
7 *
8 * Linux driver for IBM PCI tokenring cards based on the LanStreamer MPC
9 * chipset.
10 *
11 * This driver is based on the olympic driver for IBM PCI TokenRing cards (Pit/Pit-Phy/Olympic
12 * chipsets) written by:
13 * 1999 Peter De Schrijver All Rights Reserved
14 * 1999 Mike Phillips (phillim@amtrak.com)
15 *
16 * Base Driver Skeleton:
17 * Written 1993-94 by Donald Becker.
18 *
19 * Copyright 1993 United States Government as represented by the
20 * Director, National Security Agency.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * NO WARRANTY
33 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
34 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
35 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
36 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
37 * solely responsible for determining the appropriateness of using and
38 * distributing the Program and assumes all risks associated with its
39 * exercise of rights under this Agreement, including but not limited to
40 * the risks and costs of program errors, damage to or loss of data,
41 * programs or equipment, and unavailability or interruption of operations.
42 *
43 * DISCLAIMER OF LIABILITY
44 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
47 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
48 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
49 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
50 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
51 *
52 * You should have received a copy of the GNU General Public License
53 * along with this program; if not, write to the Free Software
54 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
55 *
56 *
57 * 12/10/99 - Alpha Release 0.1.0
58 * First release to the public
59 * 03/03/00 - Merged to kernel, indented -kr -i8 -bri0, fixed some missing
60 * malloc free checks, reviewed code. <alan@redhat.com>
61 * 03/13/00 - Added spinlocks for smp
62 * 03/08/01 - Added support for module_init() and module_exit()
63 * 08/15/01 - Added ioctl() functionality for debugging, changed netif_*_queue
64 * calls and other incorrectness - Kent Yoder <yoder1@us.ibm.com>
65 * 11/05/01 - Restructured the interrupt function, added delays, reduced the
66 * the number of TX descriptors to 1, which together can prevent
67 * the card from locking up the box - <yoder1@us.ibm.com>
68 * 09/27/02 - New PCI interface + bug fix. - <yoder1@us.ibm.com>
69 * 11/13/02 - Removed free_irq calls which could cause a hang, added
70 * netif_carrier_{on|off} - <yoder1@us.ibm.com>
71 *
72 * To Do:
73 *
74 *
75 * If Problems do Occur
76 * Most problems can be rectified by either closing and opening the interface
77 * (ifconfig down and up) or rmmod and insmod'ing the driver (a bit difficult
78 * if compiled into the kernel).
79 */
80
81/* Change STREAMER_DEBUG to 1 to get verbose, and I mean really verbose, messages */
82
83#define STREAMER_DEBUG 0
84#define STREAMER_DEBUG_PACKETS 0
85
86/* Change STREAMER_NETWORK_MONITOR to receive mac frames through the arb channel.
87 * Will also create a /proc/net/streamer_tr entry if proc_fs is compiled into the
88 * kernel.
89 * Intended to be used to create a ring-error reporting network module
90 * i.e. it will give you the source address of beaconers on the ring
91 */
92
93#define STREAMER_NETWORK_MONITOR 0
94
95/* #define CONFIG_PROC_FS */
96
97/*
98 * Allow or disallow ioctl's for debugging
99 */
100
101#define STREAMER_IOCTL 0
102
103#include <linux/module.h>
104#include <linux/kernel.h>
105#include <linux/errno.h>
106#include <linux/timer.h>
107#include <linux/in.h>
108#include <linux/ioport.h>
109#include <linux/string.h>
110#include <linux/proc_fs.h>
111#include <linux/ptrace.h>
112#include <linux/skbuff.h>
113#include <linux/interrupt.h>
114#include <linux/delay.h>
115#include <linux/netdevice.h>
116#include <linux/trdevice.h>
117#include <linux/stddef.h>
118#include <linux/init.h>
119#include <linux/pci.h>
120#include <linux/dma-mapping.h>
121#include <linux/spinlock.h>
122#include <linux/bitops.h>
123#include <linux/jiffies.h>
124#include <linux/slab.h>
125
126#include <net/net_namespace.h>
127#include <net/checksum.h>
128
129#include <asm/io.h>
130
131#include "lanstreamer.h"
132
133#if (BITS_PER_LONG == 64)
134#error broken on 64-bit: stores pointer to rx_ring->buffer in 32-bit int
135#endif
136
137
138/* I've got to put some intelligence into the version number so that Peter and I know
139 * which version of the code somebody has got.
140 * Version Number = a.b.c.d where a.b.c is the level of code and d is the latest author.
141 * So 0.0.1.pds = Peter, 0.0.1.mlp = Mike
142 *
143 * Official releases will only have an a.b.c version number format.
144 */
145
146static char version[] = "LanStreamer.c v0.4.0 03/08/01 - Mike Sullivan\n"
147 " v0.5.3 11/13/02 - Kent Yoder";
148
149static DEFINE_PCI_DEVICE_TABLE(streamer_pci_tbl) = {
150 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_TR, PCI_ANY_ID, PCI_ANY_ID,},
151 {} /* terminating entry */
152};
153MODULE_DEVICE_TABLE(pci,streamer_pci_tbl);
154
155
156static char *open_maj_error[] = {
157 "No error", "Lobe Media Test", "Physical Insertion",
158 "Address Verification", "Neighbor Notification (Ring Poll)",
159 "Request Parameters", "FDX Registration Request",
160 "FDX Lobe Media Test", "FDX Duplicate Address Check",
161 "Unknown stage"
162};
163
164static char *open_min_error[] = {
165 "No error", "Function Failure", "Signal Lost", "Wire Fault",
166 "Ring Speed Mismatch", "Timeout", "Ring Failure", "Ring Beaconing",
167 "Duplicate Node Address", "Request Parameters", "Remove Received",
168 "Reserved", "Reserved", "No Monitor Detected for RPL",
169 "Monitor Contention failer for RPL", "FDX Protocol Error"
170};
171
172/* Module parameters */
173
174/* Ring Speed 0,4,16
175 * 0 = Autosense
176 * 4,16 = Selected speed only, no autosense
177 * This allows the card to be the first on the ring
178 * and become the active monitor.
179 *
180 * WARNING: Some hubs will allow you to insert
181 * at the wrong speed
182 */
183
184static int ringspeed[STREAMER_MAX_ADAPTERS] = { 0, };
185
186module_param_array(ringspeed, int, NULL, 0);
187
188/* Packet buffer size */
189
190static int pkt_buf_sz[STREAMER_MAX_ADAPTERS] = { 0, };
191
192module_param_array(pkt_buf_sz, int, NULL, 0);
193
194/* Message Level */
195
196static int message_level[STREAMER_MAX_ADAPTERS] = { 1, };
197
198module_param_array(message_level, int, NULL, 0);
199
200#if STREAMER_IOCTL
201static int streamer_ioctl(struct net_device *, struct ifreq *, int);
202#endif
203
204static int streamer_reset(struct net_device *dev);
205static int streamer_open(struct net_device *dev);
206static netdev_tx_t streamer_xmit(struct sk_buff *skb,
207 struct net_device *dev);
208static int streamer_close(struct net_device *dev);
209static void streamer_set_rx_mode(struct net_device *dev);
210static irqreturn_t streamer_interrupt(int irq, void *dev_id);
211static int streamer_set_mac_address(struct net_device *dev, void *addr);
212static void streamer_arb_cmd(struct net_device *dev);
213static int streamer_change_mtu(struct net_device *dev, int mtu);
214static void streamer_srb_bh(struct net_device *dev);
215static void streamer_asb_bh(struct net_device *dev);
216#if STREAMER_NETWORK_MONITOR
217#ifdef CONFIG_PROC_FS
218static int streamer_proc_info(char *buffer, char **start, off_t offset,
219 int length, int *eof, void *data);
220static int sprintf_info(char *buffer, struct net_device *dev);
221struct streamer_private *dev_streamer=NULL;
222#endif
223#endif
224
225static const struct net_device_ops streamer_netdev_ops = {
226 .ndo_open = streamer_open,
227 .ndo_stop = streamer_close,
228 .ndo_start_xmit = streamer_xmit,
229 .ndo_change_mtu = streamer_change_mtu,
230#if STREAMER_IOCTL
231 .ndo_do_ioctl = streamer_ioctl,
232#endif
233 .ndo_set_rx_mode = streamer_set_rx_mode,
234 .ndo_set_mac_address = streamer_set_mac_address,
235};
236
237static int __devinit streamer_init_one(struct pci_dev *pdev,
238 const struct pci_device_id *ent)
239{
240 struct net_device *dev;
241 struct streamer_private *streamer_priv;
242 unsigned long pio_start, pio_end, pio_flags, pio_len;
243 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
244 int rc = 0;
245 static int card_no=-1;
246 u16 pcr;
247
248#if STREAMER_DEBUG
249 printk("lanstreamer::streamer_init_one, entry pdev %p\n",pdev);
250#endif
251
252 card_no++;
253 dev = alloc_trdev(sizeof(*streamer_priv));
254 if (dev==NULL) {
255 printk(KERN_ERR "lanstreamer: out of memory.\n");
256 return -ENOMEM;
257 }
258
259 streamer_priv = netdev_priv(dev);
260
261#if STREAMER_NETWORK_MONITOR
262#ifdef CONFIG_PROC_FS
263 if (!dev_streamer)
264 create_proc_read_entry("streamer_tr", 0, init_net.proc_net,
265 streamer_proc_info, NULL);
266 streamer_priv->next = dev_streamer;
267 dev_streamer = streamer_priv;
268#endif
269#endif
270
271 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
272 if (rc) {
273 printk(KERN_ERR "%s: No suitable PCI mapping available.\n",
274 dev->name);
275 rc = -ENODEV;
276 goto err_out;
277 }
278
279 rc = pci_enable_device(pdev);
280 if (rc) {
281 printk(KERN_ERR "lanstreamer: unable to enable pci device\n");
282 rc=-EIO;
283 goto err_out;
284 }
285
286 pci_set_master(pdev);
287
288 rc = pci_set_mwi(pdev);
289 if (rc) {
290 printk(KERN_ERR "lanstreamer: unable to enable MWI on pci device\n");
291 goto err_out_disable;
292 }
293
294 pio_start = pci_resource_start(pdev, 0);
295 pio_end = pci_resource_end(pdev, 0);
296 pio_flags = pci_resource_flags(pdev, 0);
297 pio_len = pci_resource_len(pdev, 0);
298
299 mmio_start = pci_resource_start(pdev, 1);
300 mmio_end = pci_resource_end(pdev, 1);
301 mmio_flags = pci_resource_flags(pdev, 1);
302 mmio_len = pci_resource_len(pdev, 1);
303
304#if STREAMER_DEBUG
305 printk("lanstreamer: pio_start %x pio_end %x pio_len %x pio_flags %x\n",
306 pio_start, pio_end, pio_len, pio_flags);
307 printk("lanstreamer: mmio_start %x mmio_end %x mmio_len %x mmio_flags %x\n",
308 mmio_start, mmio_end, mmio_flags, mmio_len);
309#endif
310
311 if (!request_region(pio_start, pio_len, "lanstreamer")) {
312 printk(KERN_ERR "lanstreamer: unable to get pci io addr %lx\n",
313 pio_start);
314 rc= -EBUSY;
315 goto err_out_mwi;
316 }
317
318 if (!request_mem_region(mmio_start, mmio_len, "lanstreamer")) {
319 printk(KERN_ERR "lanstreamer: unable to get pci mmio addr %lx\n",
320 mmio_start);
321 rc= -EBUSY;
322 goto err_out_free_pio;
323 }
324
325 streamer_priv->streamer_mmio=ioremap(mmio_start, mmio_len);
326 if (streamer_priv->streamer_mmio == NULL) {
327 printk(KERN_ERR "lanstreamer: unable to remap MMIO %lx\n",
328 mmio_start);
329 rc= -EIO;
330 goto err_out_free_mmio;
331 }
332
333 init_waitqueue_head(&streamer_priv->srb_wait);
334 init_waitqueue_head(&streamer_priv->trb_wait);
335
336 dev->netdev_ops = &streamer_netdev_ops;
337 dev->irq = pdev->irq;
338 dev->base_addr=pio_start;
339 SET_NETDEV_DEV(dev, &pdev->dev);
340
341 streamer_priv->streamer_card_name = (char *)pdev->resource[0].name;
342 streamer_priv->pci_dev = pdev;
343
344 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000))
345 streamer_priv->pkt_buf_sz = PKT_BUF_SZ;
346 else
347 streamer_priv->pkt_buf_sz = pkt_buf_sz[card_no];
348
349 streamer_priv->streamer_ring_speed = ringspeed[card_no];
350 streamer_priv->streamer_message_level = message_level[card_no];
351
352 pci_set_drvdata(pdev, dev);
353
354 spin_lock_init(&streamer_priv->streamer_lock);
355
356 pci_read_config_word (pdev, PCI_COMMAND, &pcr);
357 pcr |= PCI_COMMAND_SERR;
358 pci_write_config_word (pdev, PCI_COMMAND, pcr);
359
360 printk("%s\n", version);
361 printk("%s: %s. I/O at %hx, MMIO at %p, using irq %d\n",dev->name,
362 streamer_priv->streamer_card_name,
363 (unsigned int) dev->base_addr,
364 streamer_priv->streamer_mmio,
365 dev->irq);
366
367 if (streamer_reset(dev))
368 goto err_out_unmap;
369
370 rc = register_netdev(dev);
371 if (rc)
372 goto err_out_unmap;
373 return 0;
374
375err_out_unmap:
376 iounmap(streamer_priv->streamer_mmio);
377err_out_free_mmio:
378 release_mem_region(mmio_start, mmio_len);
379err_out_free_pio:
380 release_region(pio_start, pio_len);
381err_out_mwi:
382 pci_clear_mwi(pdev);
383err_out_disable:
384 pci_disable_device(pdev);
385err_out:
386 free_netdev(dev);
387#if STREAMER_DEBUG
388 printk("lanstreamer: Exit error %x\n",rc);
389#endif
390 return rc;
391}
392
393static void __devexit streamer_remove_one(struct pci_dev *pdev)
394{
395 struct net_device *dev=pci_get_drvdata(pdev);
396 struct streamer_private *streamer_priv;
397
398#if STREAMER_DEBUG
399 printk("lanstreamer::streamer_remove_one entry pdev %p\n",pdev);
400#endif
401
402 if (dev == NULL) {
403 printk(KERN_ERR "lanstreamer::streamer_remove_one, ERROR dev is NULL\n");
404 return;
405 }
406
407 streamer_priv=netdev_priv(dev);
408 if (streamer_priv == NULL) {
409 printk(KERN_ERR "lanstreamer::streamer_remove_one, ERROR dev->priv is NULL\n");
410 return;
411 }
412
413#if STREAMER_NETWORK_MONITOR
414#ifdef CONFIG_PROC_FS
415 {
416 struct streamer_private **p, **next;
417
418 for (p = &dev_streamer; *p; p = next) {
419 next = &(*p)->next;
420 if (*p == streamer_priv) {
421 *p = *next;
422 break;
423 }
424 }
425 if (!dev_streamer)
426 remove_proc_entry("streamer_tr", init_net.proc_net);
427 }
428#endif
429#endif
430
431 unregister_netdev(dev);
432 iounmap(streamer_priv->streamer_mmio);
433 release_mem_region(pci_resource_start(pdev, 1), pci_resource_len(pdev,1));
434 release_region(pci_resource_start(pdev, 0), pci_resource_len(pdev,0));
435 pci_clear_mwi(pdev);
436 pci_disable_device(pdev);
437 free_netdev(dev);
438 pci_set_drvdata(pdev, NULL);
439}
440
441
442static int streamer_reset(struct net_device *dev)
443{
444 struct streamer_private *streamer_priv;
445 __u8 __iomem *streamer_mmio;
446 unsigned long t;
447 unsigned int uaa_addr;
448 struct sk_buff *skb = NULL;
449 __u16 misr;
450
451 streamer_priv = netdev_priv(dev);
452 streamer_mmio = streamer_priv->streamer_mmio;
453
454 writew(readw(streamer_mmio + BCTL) | BCTL_SOFTRESET, streamer_mmio + BCTL);
455 t = jiffies;
456 /* Hold soft reset bit for a while */
457 ssleep(1);
458
459 writew(readw(streamer_mmio + BCTL) & ~BCTL_SOFTRESET,
460 streamer_mmio + BCTL);
461
462#if STREAMER_DEBUG
463 printk("BCTL: %x\n", readw(streamer_mmio + BCTL));
464 printk("GPR: %x\n", readw(streamer_mmio + GPR));
465 printk("SISRMASK: %x\n", readw(streamer_mmio + SISR_MASK));
466#endif
467 writew(readw(streamer_mmio + BCTL) | (BCTL_RX_FIFO_8 | BCTL_TX_FIFO_8), streamer_mmio + BCTL );
468
469 if (streamer_priv->streamer_ring_speed == 0) { /* Autosense */
470 writew(readw(streamer_mmio + GPR) | GPR_AUTOSENSE,
471 streamer_mmio + GPR);
472 if (streamer_priv->streamer_message_level)
473 printk(KERN_INFO "%s: Ringspeed autosense mode on\n",
474 dev->name);
475 } else if (streamer_priv->streamer_ring_speed == 16) {
476 if (streamer_priv->streamer_message_level)
477 printk(KERN_INFO "%s: Trying to open at 16 Mbps as requested\n",
478 dev->name);
479 writew(GPR_16MBPS, streamer_mmio + GPR);
480 } else if (streamer_priv->streamer_ring_speed == 4) {
481 if (streamer_priv->streamer_message_level)
482 printk(KERN_INFO "%s: Trying to open at 4 Mbps as requested\n",
483 dev->name);
484 writew(0, streamer_mmio + GPR);
485 }
486
487 skb = dev_alloc_skb(streamer_priv->pkt_buf_sz);
488 if (!skb) {
489 printk(KERN_INFO "%s: skb allocation for diagnostics failed...proceeding\n",
490 dev->name);
491 } else {
492 struct streamer_rx_desc *rx_ring;
493 u8 *data;
494
495 rx_ring=(struct streamer_rx_desc *)skb->data;
496 data=((u8 *)skb->data)+sizeof(struct streamer_rx_desc);
497 rx_ring->forward=0;
498 rx_ring->status=0;
499 rx_ring->buffer=cpu_to_le32(pci_map_single(streamer_priv->pci_dev, data,
500 512, PCI_DMA_FROMDEVICE));
501 rx_ring->framelen_buflen=512;
502 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev, rx_ring, 512, PCI_DMA_FROMDEVICE)),
503 streamer_mmio+RXBDA);
504 }
505
506#if STREAMER_DEBUG
507 printk("GPR = %x\n", readw(streamer_mmio + GPR));
508#endif
509 /* start solo init */
510 writew(SISR_MI, streamer_mmio + SISR_MASK_SUM);
511
512 while (!((readw(streamer_mmio + SISR)) & SISR_SRB_REPLY)) {
513 msleep_interruptible(100);
514 if (time_after(jiffies, t + 40 * HZ)) {
515 printk(KERN_ERR
516 "IBM PCI tokenring card not responding\n");
517 release_region(dev->base_addr, STREAMER_IO_SPACE);
518 if (skb)
519 dev_kfree_skb(skb);
520 return -1;
521 }
522 }
523 writew(~SISR_SRB_REPLY, streamer_mmio + SISR_RUM);
524 misr = readw(streamer_mmio + MISR_RUM);
525 writew(~misr, streamer_mmio + MISR_RUM);
526
527 if (skb)
528 dev_kfree_skb(skb); /* release skb used for diagnostics */
529
530#if STREAMER_DEBUG
531 printk("LAPWWO: %x, LAPA: %x LAPE: %x\n",
532 readw(streamer_mmio + LAPWWO), readw(streamer_mmio + LAPA),
533 readw(streamer_mmio + LAPE));
534#endif
535
536#if STREAMER_DEBUG
537 {
538 int i;
539 writew(readw(streamer_mmio + LAPWWO),
540 streamer_mmio + LAPA);
541 printk("initialization response srb dump: ");
542 for (i = 0; i < 10; i++)
543 printk("%x:",
544 ntohs(readw(streamer_mmio + LAPDINC)));
545 printk("\n");
546 }
547#endif
548
549 writew(readw(streamer_mmio + LAPWWO) + 6, streamer_mmio + LAPA);
550 if (readw(streamer_mmio + LAPD)) {
551 printk(KERN_INFO "tokenring card initialization failed. errorcode : %x\n",
552 ntohs(readw(streamer_mmio + LAPD)));
553 release_region(dev->base_addr, STREAMER_IO_SPACE);
554 return -1;
555 }
556
557 writew(readw(streamer_mmio + LAPWWO) + 8, streamer_mmio + LAPA);
558 uaa_addr = ntohs(readw(streamer_mmio + LAPDINC));
559 readw(streamer_mmio + LAPDINC); /* skip over Level.Addr field */
560 streamer_priv->streamer_addr_table_addr = ntohs(readw(streamer_mmio + LAPDINC));
561 streamer_priv->streamer_parms_addr = ntohs(readw(streamer_mmio + LAPDINC));
562
563#if STREAMER_DEBUG
564 printk("UAA resides at %x\n", uaa_addr);
565#endif
566
567 /* setup uaa area for access with LAPD */
568 {
569 int i;
570 __u16 addr;
571 writew(uaa_addr, streamer_mmio + LAPA);
572 for (i = 0; i < 6; i += 2) {
573 addr=ntohs(readw(streamer_mmio+LAPDINC));
574 dev->dev_addr[i]= (addr >> 8) & 0xff;
575 dev->dev_addr[i+1]= addr & 0xff;
576 }
577#if STREAMER_DEBUG
578 printk("Adapter address: %pM\n", dev->dev_addr);
579#endif
580 }
581 return 0;
582}
583
584static int streamer_open(struct net_device *dev)
585{
586 struct streamer_private *streamer_priv = netdev_priv(dev);
587 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
588 unsigned long flags;
589 char open_error[255];
590 int i, open_finished = 1;
591 __u16 srb_word;
592 __u16 srb_open;
593 int rc;
594
595 if (readw(streamer_mmio+BMCTL_SUM) & BMCTL_RX_ENABLED) {
596 rc=streamer_reset(dev);
597 }
598
599 if (request_irq(dev->irq, streamer_interrupt, IRQF_SHARED, "lanstreamer", dev)) {
600 return -EAGAIN;
601 }
602#if STREAMER_DEBUG
603 printk("BMCTL: %x\n", readw(streamer_mmio + BMCTL_SUM));
604 printk("pending ints: %x\n", readw(streamer_mmio + SISR));
605#endif
606
607 writew(SISR_MI | SISR_SRB_REPLY, streamer_mmio + SISR_MASK); /* more ints later, doesn't stop arb cmd interrupt */
608 writew(LISR_LIE, streamer_mmio + LISR); /* more ints later */
609
610 /* adapter is closed, so SRB is pointed to by LAPWWO */
611 writew(readw(streamer_mmio + LAPWWO), streamer_mmio + LAPA);
612
613#if STREAMER_DEBUG
614 printk("LAPWWO: %x, LAPA: %x\n", readw(streamer_mmio + LAPWWO),
615 readw(streamer_mmio + LAPA));
616 printk("LAPE: %x\n", readw(streamer_mmio + LAPE));
617 printk("SISR Mask = %04x\n", readw(streamer_mmio + SISR_MASK));
618#endif
619 do {
620 for (i = 0; i < SRB_COMMAND_SIZE; i += 2) {
621 writew(0, streamer_mmio + LAPDINC);
622 }
623
624 writew(readw(streamer_mmio+LAPWWO),streamer_mmio+LAPA);
625 writew(htons(SRB_OPEN_ADAPTER<<8),streamer_mmio+LAPDINC) ; /* open */
626 writew(htons(STREAMER_CLEAR_RET_CODE<<8),streamer_mmio+LAPDINC);
627 writew(STREAMER_CLEAR_RET_CODE, streamer_mmio + LAPDINC);
628
629 writew(readw(streamer_mmio + LAPWWO) + 8, streamer_mmio + LAPA);
630#if STREAMER_NETWORK_MONITOR
631 /* If Network Monitor, instruct card to copy MAC frames through the ARB */
632 writew(htons(OPEN_ADAPTER_ENABLE_FDX | OPEN_ADAPTER_PASS_ADC_MAC | OPEN_ADAPTER_PASS_ATT_MAC | OPEN_ADAPTER_PASS_BEACON), streamer_mmio + LAPDINC); /* offset 8 word contains open options */
633#else
634 writew(htons(OPEN_ADAPTER_ENABLE_FDX), streamer_mmio + LAPDINC); /* Offset 8 word contains Open.Options */
635#endif
636
637 if (streamer_priv->streamer_laa[0]) {
638 writew(readw(streamer_mmio + LAPWWO) + 12, streamer_mmio + LAPA);
639 writew(htons((streamer_priv->streamer_laa[0] << 8) |
640 streamer_priv->streamer_laa[1]),streamer_mmio+LAPDINC);
641 writew(htons((streamer_priv->streamer_laa[2] << 8) |
642 streamer_priv->streamer_laa[3]),streamer_mmio+LAPDINC);
643 writew(htons((streamer_priv->streamer_laa[4] << 8) |
644 streamer_priv->streamer_laa[5]),streamer_mmio+LAPDINC);
645 memcpy(dev->dev_addr, streamer_priv->streamer_laa, dev->addr_len);
646 }
647
648 /* save off srb open offset */
649 srb_open = readw(streamer_mmio + LAPWWO);
650#if STREAMER_DEBUG
651 writew(readw(streamer_mmio + LAPWWO),
652 streamer_mmio + LAPA);
653 printk("srb open request:\n");
654 for (i = 0; i < 16; i++) {
655 printk("%x:", ntohs(readw(streamer_mmio + LAPDINC)));
656 }
657 printk("\n");
658#endif
659 spin_lock_irqsave(&streamer_priv->streamer_lock, flags);
660 streamer_priv->srb_queued = 1;
661
662 /* signal solo that SRB command has been issued */
663 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
664 spin_unlock_irqrestore(&streamer_priv->streamer_lock, flags);
665
666 while (streamer_priv->srb_queued) {
667 interruptible_sleep_on_timeout(&streamer_priv->srb_wait, 5 * HZ);
668 if (signal_pending(current)) {
669 printk(KERN_WARNING "%s: SRB timed out.\n", dev->name);
670 printk(KERN_WARNING "SISR=%x MISR=%x, LISR=%x\n",
671 readw(streamer_mmio + SISR),
672 readw(streamer_mmio + MISR_RUM),
673 readw(streamer_mmio + LISR));
674 streamer_priv->srb_queued = 0;
675 break;
676 }
677 }
678
679#if STREAMER_DEBUG
680 printk("SISR_MASK: %x\n", readw(streamer_mmio + SISR_MASK));
681 printk("srb open response:\n");
682 writew(srb_open, streamer_mmio + LAPA);
683 for (i = 0; i < 10; i++) {
684 printk("%x:",
685 ntohs(readw(streamer_mmio + LAPDINC)));
686 }
687#endif
688
689 /* If we get the same return response as we set, the interrupt wasn't raised and the open
690 * timed out.
691 */
692 writew(srb_open + 2, streamer_mmio + LAPA);
693 srb_word = ntohs(readw(streamer_mmio + LAPD)) >> 8;
694 if (srb_word == STREAMER_CLEAR_RET_CODE) {
695 printk(KERN_WARNING "%s: Adapter Open time out or error.\n",
696 dev->name);
697 return -EIO;
698 }
699
700 if (srb_word != 0) {
701 if (srb_word == 0x07) {
702 if (!streamer_priv->streamer_ring_speed && open_finished) { /* Autosense , first time around */
703 printk(KERN_WARNING "%s: Retrying at different ring speed\n",
704 dev->name);
705 open_finished = 0;
706 } else {
707 __u16 error_code;
708
709 writew(srb_open + 6, streamer_mmio + LAPA);
710 error_code = ntohs(readw(streamer_mmio + LAPD));
711 strcpy(open_error, open_maj_error[(error_code & 0xf0) >> 4]);
712 strcat(open_error, " - ");
713 strcat(open_error, open_min_error[(error_code & 0x0f)]);
714
715 if (!streamer_priv->streamer_ring_speed &&
716 ((error_code & 0x0f) == 0x0d))
717 {
718 printk(KERN_WARNING "%s: Tried to autosense ring speed with no monitors present\n", dev->name);
719 printk(KERN_WARNING "%s: Please try again with a specified ring speed\n", dev->name);
720 free_irq(dev->irq, dev);
721 return -EIO;
722 }
723
724 printk(KERN_WARNING "%s: %s\n",
725 dev->name, open_error);
726 free_irq(dev->irq, dev);
727 return -EIO;
728
729 } /* if autosense && open_finished */
730 } else {
731 printk(KERN_WARNING "%s: Bad OPEN response: %x\n",
732 dev->name, srb_word);
733 free_irq(dev->irq, dev);
734 return -EIO;
735 }
736 } else
737 open_finished = 1;
738 } while (!(open_finished)); /* Will only loop if ring speed mismatch re-open attempted && autosense is on */
739
740 writew(srb_open + 18, streamer_mmio + LAPA);
741 srb_word=ntohs(readw(streamer_mmio+LAPD)) >> 8;
742 if (srb_word & (1 << 3))
743 if (streamer_priv->streamer_message_level)
744 printk(KERN_INFO "%s: Opened in FDX Mode\n", dev->name);
745
746 if (srb_word & 1)
747 streamer_priv->streamer_ring_speed = 16;
748 else
749 streamer_priv->streamer_ring_speed = 4;
750
751 if (streamer_priv->streamer_message_level)
752 printk(KERN_INFO "%s: Opened in %d Mbps mode\n",
753 dev->name,
754 streamer_priv->streamer_ring_speed);
755
756 writew(srb_open + 8, streamer_mmio + LAPA);
757 streamer_priv->asb = ntohs(readw(streamer_mmio + LAPDINC));
758 streamer_priv->srb = ntohs(readw(streamer_mmio + LAPDINC));
759 streamer_priv->arb = ntohs(readw(streamer_mmio + LAPDINC));
760 readw(streamer_mmio + LAPDINC); /* offset 14 word is rsvd */
761 streamer_priv->trb = ntohs(readw(streamer_mmio + LAPDINC));
762
763 streamer_priv->streamer_receive_options = 0x00;
764 streamer_priv->streamer_copy_all_options = 0;
765
766 /* setup rx ring */
767 /* enable rx channel */
768 writew(~BMCTL_RX_DIS, streamer_mmio + BMCTL_RUM);
769
770 /* setup rx descriptors */
771 streamer_priv->streamer_rx_ring=
772 kmalloc( sizeof(struct streamer_rx_desc)*
773 STREAMER_RX_RING_SIZE,GFP_KERNEL);
774 if (!streamer_priv->streamer_rx_ring) {
775 printk(KERN_WARNING "%s ALLOC of streamer rx ring FAILED!!\n",dev->name);
776 return -EIO;
777 }
778
779 for (i = 0; i < STREAMER_RX_RING_SIZE; i++) {
780 struct sk_buff *skb;
781
782 skb = dev_alloc_skb(streamer_priv->pkt_buf_sz);
783 if (skb == NULL)
784 break;
785
786 skb->dev = dev;
787
788 streamer_priv->streamer_rx_ring[i].forward =
789 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[i + 1],
790 sizeof(struct streamer_rx_desc), PCI_DMA_FROMDEVICE));
791 streamer_priv->streamer_rx_ring[i].status = 0;
792 streamer_priv->streamer_rx_ring[i].buffer =
793 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, skb->data,
794 streamer_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
795 streamer_priv->streamer_rx_ring[i].framelen_buflen = streamer_priv->pkt_buf_sz;
796 streamer_priv->rx_ring_skb[i] = skb;
797 }
798 streamer_priv->streamer_rx_ring[STREAMER_RX_RING_SIZE - 1].forward =
799 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[0],
800 sizeof(struct streamer_rx_desc), PCI_DMA_FROMDEVICE));
801
802 if (i == 0) {
803 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n", dev->name);
804 free_irq(dev->irq, dev);
805 return -EIO;
806 }
807
808 streamer_priv->rx_ring_last_received = STREAMER_RX_RING_SIZE - 1; /* last processed rx status */
809
810 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[0],
811 sizeof(struct streamer_rx_desc), PCI_DMA_TODEVICE)),
812 streamer_mmio + RXBDA);
813 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[STREAMER_RX_RING_SIZE - 1],
814 sizeof(struct streamer_rx_desc), PCI_DMA_TODEVICE)),
815 streamer_mmio + RXLBDA);
816
817 /* set bus master interrupt event mask */
818 writew(MISR_RX_NOBUF | MISR_RX_EOF, streamer_mmio + MISR_MASK);
819
820
821 /* setup tx ring */
822 streamer_priv->streamer_tx_ring=kmalloc(sizeof(struct streamer_tx_desc)*
823 STREAMER_TX_RING_SIZE,GFP_KERNEL);
824 if (!streamer_priv->streamer_tx_ring) {
825 printk(KERN_WARNING "%s ALLOC of streamer_tx_ring FAILED\n",dev->name);
826 return -EIO;
827 }
828
829 writew(~BMCTL_TX2_DIS, streamer_mmio + BMCTL_RUM); /* Enables TX channel 2 */
830 for (i = 0; i < STREAMER_TX_RING_SIZE; i++) {
831 streamer_priv->streamer_tx_ring[i].forward = cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
832 &streamer_priv->streamer_tx_ring[i + 1],
833 sizeof(struct streamer_tx_desc),
834 PCI_DMA_TODEVICE));
835 streamer_priv->streamer_tx_ring[i].status = 0;
836 streamer_priv->streamer_tx_ring[i].bufcnt_framelen = 0;
837 streamer_priv->streamer_tx_ring[i].buffer = 0;
838 streamer_priv->streamer_tx_ring[i].buflen = 0;
839 streamer_priv->streamer_tx_ring[i].rsvd1 = 0;
840 streamer_priv->streamer_tx_ring[i].rsvd2 = 0;
841 streamer_priv->streamer_tx_ring[i].rsvd3 = 0;
842 }
843 streamer_priv->streamer_tx_ring[STREAMER_TX_RING_SIZE - 1].forward =
844 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_tx_ring[0],
845 sizeof(struct streamer_tx_desc), PCI_DMA_TODEVICE));
846
847 streamer_priv->free_tx_ring_entries = STREAMER_TX_RING_SIZE;
848 streamer_priv->tx_ring_free = 0; /* next entry in tx ring to use */
849 streamer_priv->tx_ring_last_status = STREAMER_TX_RING_SIZE - 1;
850
851 /* set Busmaster interrupt event mask (handle receives on interrupt only */
852 writew(MISR_TX2_EOF | MISR_RX_NOBUF | MISR_RX_EOF, streamer_mmio + MISR_MASK);
853 /* set system event interrupt mask */
854 writew(SISR_ADAPTER_CHECK | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_ASB_FREE, streamer_mmio + SISR_MASK_SUM);
855
856#if STREAMER_DEBUG
857 printk("BMCTL: %x\n", readw(streamer_mmio + BMCTL_SUM));
858 printk("SISR MASK: %x\n", readw(streamer_mmio + SISR_MASK));
859#endif
860
861#if STREAMER_NETWORK_MONITOR
862
863 writew(streamer_priv->streamer_addr_table_addr, streamer_mmio + LAPA);
864 printk("%s: Node Address: %04x:%04x:%04x\n", dev->name,
865 ntohs(readw(streamer_mmio + LAPDINC)),
866 ntohs(readw(streamer_mmio + LAPDINC)),
867 ntohs(readw(streamer_mmio + LAPDINC)));
868 readw(streamer_mmio + LAPDINC);
869 readw(streamer_mmio + LAPDINC);
870 printk("%s: Functional Address: %04x:%04x\n", dev->name,
871 ntohs(readw(streamer_mmio + LAPDINC)),
872 ntohs(readw(streamer_mmio + LAPDINC)));
873
874 writew(streamer_priv->streamer_parms_addr + 4,
875 streamer_mmio + LAPA);
876 printk("%s: NAUN Address: %04x:%04x:%04x\n", dev->name,
877 ntohs(readw(streamer_mmio + LAPDINC)),
878 ntohs(readw(streamer_mmio + LAPDINC)),
879 ntohs(readw(streamer_mmio + LAPDINC)));
880#endif
881
882 netif_start_queue(dev);
883 netif_carrier_on(dev);
884 return 0;
885}
886
887/*
888 * When we enter the rx routine we do not know how many frames have been
889 * queued on the rx channel. Therefore we start at the next rx status
890 * position and travel around the receive ring until we have completed
891 * all the frames.
892 *
893 * This means that we may process the frame before we receive the end
894 * of frame interrupt. This is why we always test the status instead
895 * of blindly processing the next frame.
896 *
897 */
898static void streamer_rx(struct net_device *dev)
899{
900 struct streamer_private *streamer_priv =
901 netdev_priv(dev);
902 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
903 struct streamer_rx_desc *rx_desc;
904 int rx_ring_last_received, length, frame_length, buffer_cnt = 0;
905 struct sk_buff *skb, *skb2;
906
907 /* setup the next rx descriptor to be received */
908 rx_desc = &streamer_priv->streamer_rx_ring[(streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1)];
909 rx_ring_last_received = streamer_priv->rx_ring_last_received;
910
911 while (rx_desc->status & 0x01000000) { /* While processed descriptors are available */
912 if (rx_ring_last_received != streamer_priv->rx_ring_last_received)
913 {
914 printk(KERN_WARNING "RX Error 1 rx_ring_last_received not the same %x %x\n",
915 rx_ring_last_received, streamer_priv->rx_ring_last_received);
916 }
917 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1);
918 rx_ring_last_received = streamer_priv->rx_ring_last_received;
919
920 length = rx_desc->framelen_buflen & 0xffff; /* buffer length */
921 frame_length = (rx_desc->framelen_buflen >> 16) & 0xffff;
922
923 if (rx_desc->status & 0x7E830000) { /* errors */
924 if (streamer_priv->streamer_message_level) {
925 printk(KERN_WARNING "%s: Rx Error %x\n",
926 dev->name, rx_desc->status);
927 }
928 } else { /* received without errors */
929 if (rx_desc->status & 0x80000000) { /* frame complete */
930 buffer_cnt = 1;
931 skb = dev_alloc_skb(streamer_priv->pkt_buf_sz);
932 } else {
933 skb = dev_alloc_skb(frame_length);
934 }
935
936 if (skb == NULL)
937 {
938 printk(KERN_WARNING "%s: Not enough memory to copy packet to upper layers.\n", dev->name);
939 dev->stats.rx_dropped++;
940 } else { /* we allocated an skb OK */
941 if (buffer_cnt == 1) {
942 /* release the DMA mapping */
943 pci_unmap_single(streamer_priv->pci_dev,
944 le32_to_cpu(streamer_priv->streamer_rx_ring[rx_ring_last_received].buffer),
945 streamer_priv->pkt_buf_sz,
946 PCI_DMA_FROMDEVICE);
947 skb2 = streamer_priv->rx_ring_skb[rx_ring_last_received];
948#if STREAMER_DEBUG_PACKETS
949 {
950 int i;
951 printk("streamer_rx packet print: skb->data2 %p skb->head %p\n", skb2->data, skb2->head);
952 for (i = 0; i < frame_length; i++)
953 {
954 printk("%x:", skb2->data[i]);
955 if (((i + 1) % 16) == 0)
956 printk("\n");
957 }
958 printk("\n");
959 }
960#endif
961 skb_put(skb2, length);
962 skb2->protocol = tr_type_trans(skb2, dev);
963 /* recycle this descriptor */
964 streamer_priv->streamer_rx_ring[rx_ring_last_received].status = 0;
965 streamer_priv->streamer_rx_ring[rx_ring_last_received].framelen_buflen = streamer_priv->pkt_buf_sz;
966 streamer_priv->streamer_rx_ring[rx_ring_last_received].buffer =
967 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, skb->data, streamer_priv->pkt_buf_sz,
968 PCI_DMA_FROMDEVICE));
969 streamer_priv->rx_ring_skb[rx_ring_last_received] = skb;
970 /* place recycled descriptor back on the adapter */
971 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
972 &streamer_priv->streamer_rx_ring[rx_ring_last_received],
973 sizeof(struct streamer_rx_desc), PCI_DMA_FROMDEVICE)),
974 streamer_mmio + RXLBDA);
975 /* pass the received skb up to the protocol */
976 netif_rx(skb2);
977 } else {
978 do { /* Walk the buffers */
979 pci_unmap_single(streamer_priv->pci_dev, le32_to_cpu(rx_desc->buffer), length, PCI_DMA_FROMDEVICE),
980 memcpy(skb_put(skb, length), (void *)rx_desc->buffer, length); /* copy this fragment */
981 streamer_priv->streamer_rx_ring[rx_ring_last_received].status = 0;
982 streamer_priv->streamer_rx_ring[rx_ring_last_received].framelen_buflen = streamer_priv->pkt_buf_sz;
983
984 /* give descriptor back to the adapter */
985 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
986 &streamer_priv->streamer_rx_ring[rx_ring_last_received],
987 length, PCI_DMA_FROMDEVICE)),
988 streamer_mmio + RXLBDA);
989
990 if (rx_desc->status & 0x80000000)
991 break; /* this descriptor completes the frame */
992
993 /* else get the next pending descriptor */
994 if (rx_ring_last_received!= streamer_priv->rx_ring_last_received)
995 {
996 printk("RX Error rx_ring_last_received not the same %x %x\n",
997 rx_ring_last_received,
998 streamer_priv->rx_ring_last_received);
999 }
1000 rx_desc = &streamer_priv->streamer_rx_ring[(streamer_priv->rx_ring_last_received+1) & (STREAMER_RX_RING_SIZE-1)];
1001
1002 length = rx_desc->framelen_buflen & 0xffff; /* buffer length */
1003 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received+1) & (STREAMER_RX_RING_SIZE - 1);
1004 rx_ring_last_received = streamer_priv->rx_ring_last_received;
1005 } while (1);
1006
1007 skb->protocol = tr_type_trans(skb, dev);
1008 /* send up to the protocol */
1009 netif_rx(skb);
1010 }
1011 dev->stats.rx_packets++;
1012 dev->stats.rx_bytes += length;
1013 } /* if skb == null */
1014 } /* end received without errors */
1015
1016 /* try the next one */
1017 rx_desc = &streamer_priv->streamer_rx_ring[(rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1)];
1018 } /* end for all completed rx descriptors */
1019}
1020
1021static irqreturn_t streamer_interrupt(int irq, void *dev_id)
1022{
1023 struct net_device *dev = (struct net_device *) dev_id;
1024 struct streamer_private *streamer_priv =
1025 netdev_priv(dev);
1026 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1027 __u16 sisr;
1028 __u16 misr;
1029 u8 max_intr = MAX_INTR;
1030
1031 spin_lock(&streamer_priv->streamer_lock);
1032 sisr = readw(streamer_mmio + SISR);
1033
1034 while((sisr & (SISR_MI | SISR_SRB_REPLY | SISR_ADAPTER_CHECK | SISR_ASB_FREE |
1035 SISR_ARB_CMD | SISR_TRB_REPLY | SISR_PAR_ERR | SISR_SERR_ERR)) &&
1036 (max_intr > 0)) {
1037
1038 if(sisr & SISR_PAR_ERR) {
1039 writew(~SISR_PAR_ERR, streamer_mmio + SISR_RUM);
1040 (void)readw(streamer_mmio + SISR_RUM);
1041 }
1042
1043 else if(sisr & SISR_SERR_ERR) {
1044 writew(~SISR_SERR_ERR, streamer_mmio + SISR_RUM);
1045 (void)readw(streamer_mmio + SISR_RUM);
1046 }
1047
1048 else if(sisr & SISR_MI) {
1049 misr = readw(streamer_mmio + MISR_RUM);
1050
1051 if (misr & MISR_TX2_EOF) {
1052 while(streamer_priv->streamer_tx_ring[(streamer_priv->tx_ring_last_status + 1) & (STREAMER_TX_RING_SIZE - 1)].status) {
1053 streamer_priv->tx_ring_last_status = (streamer_priv->tx_ring_last_status + 1) & (STREAMER_TX_RING_SIZE - 1);
1054 streamer_priv->free_tx_ring_entries++;
1055 dev->stats.tx_bytes += streamer_priv->tx_ring_skb[streamer_priv->tx_ring_last_status]->len;
1056 dev->stats.tx_packets++;
1057 dev_kfree_skb_irq(streamer_priv->tx_ring_skb[streamer_priv->tx_ring_last_status]);
1058 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].buffer = 0xdeadbeef;
1059 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].status = 0;
1060 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].bufcnt_framelen = 0;
1061 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].buflen = 0;
1062 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].rsvd1 = 0;
1063 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].rsvd2 = 0;
1064 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].rsvd3 = 0;
1065 }
1066 netif_wake_queue(dev);
1067 }
1068
1069 if (misr & MISR_RX_EOF) {
1070 streamer_rx(dev);
1071 }
1072 /* MISR_RX_EOF */
1073
1074 if (misr & MISR_RX_NOBUF) {
1075 /* According to the documentation, we don't have to do anything,
1076 * but trapping it keeps it out of /var/log/messages.
1077 */
1078 } /* SISR_RX_NOBUF */
1079
1080 writew(~misr, streamer_mmio + MISR_RUM);
1081 (void)readw(streamer_mmio + MISR_RUM);
1082 }
1083
1084 else if (sisr & SISR_SRB_REPLY) {
1085 if (streamer_priv->srb_queued == 1) {
1086 wake_up_interruptible(&streamer_priv->srb_wait);
1087 } else if (streamer_priv->srb_queued == 2) {
1088 streamer_srb_bh(dev);
1089 }
1090 streamer_priv->srb_queued = 0;
1091
1092 writew(~SISR_SRB_REPLY, streamer_mmio + SISR_RUM);
1093 (void)readw(streamer_mmio + SISR_RUM);
1094 }
1095
1096 else if (sisr & SISR_ADAPTER_CHECK) {
1097 printk(KERN_WARNING "%s: Adapter Check Interrupt Raised, 8 bytes of information follow:\n", dev->name);
1098 writel(readl(streamer_mmio + LAPWWO), streamer_mmio + LAPA);
1099 printk(KERN_WARNING "%s: Words %x:%x:%x:%x:\n",
1100 dev->name, readw(streamer_mmio + LAPDINC),
1101 ntohs(readw(streamer_mmio + LAPDINC)),
1102 ntohs(readw(streamer_mmio + LAPDINC)),
1103 ntohs(readw(streamer_mmio + LAPDINC)));
1104 netif_stop_queue(dev);
1105 netif_carrier_off(dev);
1106 printk(KERN_WARNING "%s: Adapter must be manually reset.\n", dev->name);
1107 }
1108
1109 /* SISR_ADAPTER_CHECK */
1110 else if (sisr & SISR_ASB_FREE) {
1111 /* Wake up anything that is waiting for the asb response */
1112 if (streamer_priv->asb_queued) {
1113 streamer_asb_bh(dev);
1114 }
1115 writew(~SISR_ASB_FREE, streamer_mmio + SISR_RUM);
1116 (void)readw(streamer_mmio + SISR_RUM);
1117 }
1118 /* SISR_ASB_FREE */
1119 else if (sisr & SISR_ARB_CMD) {
1120 streamer_arb_cmd(dev);
1121 writew(~SISR_ARB_CMD, streamer_mmio + SISR_RUM);
1122 (void)readw(streamer_mmio + SISR_RUM);
1123 }
1124 /* SISR_ARB_CMD */
1125 else if (sisr & SISR_TRB_REPLY) {
1126 /* Wake up anything that is waiting for the trb response */
1127 if (streamer_priv->trb_queued) {
1128 wake_up_interruptible(&streamer_priv->
1129 trb_wait);
1130 }
1131 streamer_priv->trb_queued = 0;
1132 writew(~SISR_TRB_REPLY, streamer_mmio + SISR_RUM);
1133 (void)readw(streamer_mmio + SISR_RUM);
1134 }
1135 /* SISR_TRB_REPLY */
1136
1137 sisr = readw(streamer_mmio + SISR);
1138 max_intr--;
1139 } /* while() */
1140
1141 spin_unlock(&streamer_priv->streamer_lock) ;
1142 return IRQ_HANDLED;
1143}
1144
1145static netdev_tx_t streamer_xmit(struct sk_buff *skb,
1146 struct net_device *dev)
1147{
1148 struct streamer_private *streamer_priv =
1149 netdev_priv(dev);
1150 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1151 unsigned long flags ;
1152
1153 spin_lock_irqsave(&streamer_priv->streamer_lock, flags);
1154
1155 if (streamer_priv->free_tx_ring_entries) {
1156 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].status = 0;
1157 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].bufcnt_framelen = 0x00020000 | skb->len;
1158 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].buffer =
1159 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE));
1160 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].rsvd1 = skb->len;
1161 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].rsvd2 = 0;
1162 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].rsvd3 = 0;
1163 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].buflen = skb->len;
1164
1165 streamer_priv->tx_ring_skb[streamer_priv->tx_ring_free] = skb;
1166 streamer_priv->free_tx_ring_entries--;
1167#if STREAMER_DEBUG_PACKETS
1168 {
1169 int i;
1170 printk("streamer_xmit packet print:\n");
1171 for (i = 0; i < skb->len; i++) {
1172 printk("%x:", skb->data[i]);
1173 if (((i + 1) % 16) == 0)
1174 printk("\n");
1175 }
1176 printk("\n");
1177 }
1178#endif
1179
1180 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
1181 &streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free],
1182 sizeof(struct streamer_tx_desc), PCI_DMA_TODEVICE)),
1183 streamer_mmio + TX2LFDA);
1184 (void)readl(streamer_mmio + TX2LFDA);
1185
1186 streamer_priv->tx_ring_free = (streamer_priv->tx_ring_free + 1) & (STREAMER_TX_RING_SIZE - 1);
1187 spin_unlock_irqrestore(&streamer_priv->streamer_lock,flags);
1188 return NETDEV_TX_OK;
1189 } else {
1190 netif_stop_queue(dev);
1191 spin_unlock_irqrestore(&streamer_priv->streamer_lock,flags);
1192 return NETDEV_TX_BUSY;
1193 }
1194}
1195
1196
1197static int streamer_close(struct net_device *dev)
1198{
1199 struct streamer_private *streamer_priv =
1200 netdev_priv(dev);
1201 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1202 unsigned long flags;
1203 int i;
1204
1205 netif_stop_queue(dev);
1206 netif_carrier_off(dev);
1207 writew(streamer_priv->srb, streamer_mmio + LAPA);
1208 writew(htons(SRB_CLOSE_ADAPTER << 8),streamer_mmio+LAPDINC);
1209 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1210
1211 spin_lock_irqsave(&streamer_priv->streamer_lock, flags);
1212
1213 streamer_priv->srb_queued = 1;
1214 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1215
1216 spin_unlock_irqrestore(&streamer_priv->streamer_lock, flags);
1217
1218 while (streamer_priv->srb_queued)
1219 {
1220 interruptible_sleep_on_timeout(&streamer_priv->srb_wait,
1221 jiffies + 60 * HZ);
1222 if (signal_pending(current))
1223 {
1224 printk(KERN_WARNING "%s: SRB timed out.\n", dev->name);
1225 printk(KERN_WARNING "SISR=%x MISR=%x LISR=%x\n",
1226 readw(streamer_mmio + SISR),
1227 readw(streamer_mmio + MISR_RUM),
1228 readw(streamer_mmio + LISR));
1229 streamer_priv->srb_queued = 0;
1230 break;
1231 }
1232 }
1233
1234 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1);
1235
1236 for (i = 0; i < STREAMER_RX_RING_SIZE; i++) {
1237 if (streamer_priv->rx_ring_skb[streamer_priv->rx_ring_last_received]) {
1238 dev_kfree_skb(streamer_priv->rx_ring_skb[streamer_priv->rx_ring_last_received]);
1239 }
1240 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1);
1241 }
1242
1243 /* reset tx/rx fifo's and busmaster logic */
1244
1245 /* TBD. Add graceful way to reset the LLC channel without doing a soft reset.
1246 writel(readl(streamer_mmio+BCTL)|(3<<13),streamer_mmio+BCTL);
1247 udelay(1);
1248 writel(readl(streamer_mmio+BCTL)&~(3<<13),streamer_mmio+BCTL);
1249 */
1250
1251#if STREAMER_DEBUG
1252 writew(streamer_priv->srb, streamer_mmio + LAPA);
1253 printk("srb): ");
1254 for (i = 0; i < 2; i++) {
1255 printk("%x ", ntohs(readw(streamer_mmio + LAPDINC)));
1256 }
1257 printk("\n");
1258#endif
1259 free_irq(dev->irq, dev);
1260 return 0;
1261}
1262
1263static void streamer_set_rx_mode(struct net_device *dev)
1264{
1265 struct streamer_private *streamer_priv =
1266 netdev_priv(dev);
1267 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1268 __u8 options = 0;
1269 struct netdev_hw_addr *ha;
1270 unsigned char dev_mc_address[5];
1271
1272 writel(streamer_priv->srb, streamer_mmio + LAPA);
1273 options = streamer_priv->streamer_copy_all_options;
1274
1275 if (dev->flags & IFF_PROMISC)
1276 options |= (3 << 5); /* All LLC and MAC frames, all through the main rx channel */
1277 else
1278 options &= ~(3 << 5);
1279
1280 /* Only issue the srb if there is a change in options */
1281
1282 if ((options ^ streamer_priv->streamer_copy_all_options))
1283 {
1284 /* Now to issue the srb command to alter the copy.all.options */
1285 writew(htons(SRB_MODIFY_RECEIVE_OPTIONS << 8), streamer_mmio+LAPDINC);
1286 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1287 writew(htons((streamer_priv->streamer_receive_options << 8) | options),streamer_mmio+LAPDINC);
1288 writew(htons(0x4a41),streamer_mmio+LAPDINC);
1289 writew(htons(0x4d45),streamer_mmio+LAPDINC);
1290 writew(htons(0x5320),streamer_mmio+LAPDINC);
1291 writew(0x2020, streamer_mmio + LAPDINC);
1292
1293 streamer_priv->srb_queued = 2; /* Can't sleep, use srb_bh */
1294
1295 writel(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1296
1297 streamer_priv->streamer_copy_all_options = options;
1298 return;
1299 }
1300
1301 /* Set the functional addresses we need for multicast */
1302 writel(streamer_priv->srb,streamer_mmio+LAPA);
1303 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1304
1305 netdev_for_each_mc_addr(ha, dev) {
1306 dev_mc_address[0] |= ha->addr[2];
1307 dev_mc_address[1] |= ha->addr[3];
1308 dev_mc_address[2] |= ha->addr[4];
1309 dev_mc_address[3] |= ha->addr[5];
1310 }
1311
1312 writew(htons(SRB_SET_FUNC_ADDRESS << 8),streamer_mmio+LAPDINC);
1313 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1314 writew(0,streamer_mmio+LAPDINC);
1315 writew(htons( (dev_mc_address[0] << 8) | dev_mc_address[1]),streamer_mmio+LAPDINC);
1316 writew(htons( (dev_mc_address[2] << 8) | dev_mc_address[3]),streamer_mmio+LAPDINC);
1317 streamer_priv->srb_queued = 2 ;
1318 writel(LISR_SRB_CMD,streamer_mmio+LISR_SUM);
1319}
1320
1321static void streamer_srb_bh(struct net_device *dev)
1322{
1323 struct streamer_private *streamer_priv = netdev_priv(dev);
1324 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1325 __u16 srb_word;
1326
1327 writew(streamer_priv->srb, streamer_mmio + LAPA);
1328 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1329
1330 switch (srb_word) {
1331
1332 /* SRB_MODIFY_RECEIVE_OPTIONS i.e. set_multicast_list options (promiscuous)
1333 * At some point we should do something if we get an error, such as
1334 * resetting the IFF_PROMISC flag in dev
1335 */
1336
1337 case SRB_MODIFY_RECEIVE_OPTIONS:
1338 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1339
1340 switch (srb_word) {
1341 case 0x01:
1342 printk(KERN_WARNING "%s: Unrecognized srb command\n", dev->name);
1343 break;
1344 case 0x04:
1345 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1346 break;
1347 default:
1348 if (streamer_priv->streamer_message_level)
1349 printk(KERN_WARNING "%s: Receive Options Modified to %x,%x\n",
1350 dev->name,
1351 streamer_priv->streamer_copy_all_options,
1352 streamer_priv->streamer_receive_options);
1353 break;
1354 } /* switch srb[2] */
1355 break;
1356
1357
1358 /* SRB_SET_GROUP_ADDRESS - Multicast group setting
1359 */
1360 case SRB_SET_GROUP_ADDRESS:
1361 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1362 switch (srb_word) {
1363 case 0x00:
1364 break;
1365 case 0x01:
1366 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name);
1367 break;
1368 case 0x04:
1369 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1370 break;
1371 case 0x3c:
1372 printk(KERN_WARNING "%s: Group/Functional address indicator bits not set correctly\n", dev->name);
1373 break;
1374 case 0x3e: /* If we ever implement individual multicast addresses, will need to deal with this */
1375 printk(KERN_WARNING "%s: Group address registers full\n", dev->name);
1376 break;
1377 case 0x55:
1378 printk(KERN_INFO "%s: Group Address already set.\n", dev->name);
1379 break;
1380 default:
1381 break;
1382 } /* switch srb[2] */
1383 break;
1384
1385
1386 /* SRB_RESET_GROUP_ADDRESS - Remove a multicast address from group list
1387 */
1388 case SRB_RESET_GROUP_ADDRESS:
1389 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1390 switch (srb_word) {
1391 case 0x00:
1392 break;
1393 case 0x01:
1394 printk(KERN_WARNING "%s: Unrecognized srb command\n", dev->name);
1395 break;
1396 case 0x04:
1397 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1398 break;
1399 case 0x39: /* Must deal with this if individual multicast addresses used */
1400 printk(KERN_INFO "%s: Group address not found\n", dev->name);
1401 break;
1402 default:
1403 break;
1404 } /* switch srb[2] */
1405 break;
1406
1407
1408 /* SRB_SET_FUNC_ADDRESS - Called by the set_rx_mode
1409 */
1410
1411 case SRB_SET_FUNC_ADDRESS:
1412 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1413 switch (srb_word) {
1414 case 0x00:
1415 if (streamer_priv->streamer_message_level)
1416 printk(KERN_INFO "%s: Functional Address Mask Set\n", dev->name);
1417 break;
1418 case 0x01:
1419 printk(KERN_WARNING "%s: Unrecognized srb command\n", dev->name);
1420 break;
1421 case 0x04:
1422 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1423 break;
1424 default:
1425 break;
1426 } /* switch srb[2] */
1427 break;
1428
1429 /* SRB_READ_LOG - Read and reset the adapter error counters
1430 */
1431
1432 case SRB_READ_LOG:
1433 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1434 switch (srb_word) {
1435 case 0x00:
1436 {
1437 int i;
1438 if (streamer_priv->streamer_message_level)
1439 printk(KERN_INFO "%s: Read Log command complete\n", dev->name);
1440 printk("Read Log statistics: ");
1441 writew(streamer_priv->srb + 6,
1442 streamer_mmio + LAPA);
1443 for (i = 0; i < 5; i++) {
1444 printk("%x:", ntohs(readw(streamer_mmio + LAPDINC)));
1445 }
1446 printk("\n");
1447 }
1448 break;
1449 case 0x01:
1450 printk(KERN_WARNING "%s: Unrecognized srb command\n", dev->name);
1451 break;
1452 case 0x04:
1453 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1454 break;
1455
1456 } /* switch srb[2] */
1457 break;
1458
1459 /* SRB_READ_SR_COUNTERS - Read and reset the source routing bridge related counters */
1460
1461 case SRB_READ_SR_COUNTERS:
1462 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1463 switch (srb_word) {
1464 case 0x00:
1465 if (streamer_priv->streamer_message_level)
1466 printk(KERN_INFO "%s: Read Source Routing Counters issued\n", dev->name);
1467 break;
1468 case 0x01:
1469 printk(KERN_WARNING "%s: Unrecognized srb command\n", dev->name);
1470 break;
1471 case 0x04:
1472 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1473 break;
1474 default:
1475 break;
1476 } /* switch srb[2] */
1477 break;
1478
1479 default:
1480 printk(KERN_WARNING "%s: Unrecognized srb bh return value.\n", dev->name);
1481 break;
1482 } /* switch srb[0] */
1483}
1484
1485static int streamer_set_mac_address(struct net_device *dev, void *addr)
1486{
1487 struct sockaddr *saddr = addr;
1488 struct streamer_private *streamer_priv = netdev_priv(dev);
1489
1490 if (netif_running(dev))
1491 {
1492 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name);
1493 return -EIO;
1494 }
1495
1496 memcpy(streamer_priv->streamer_laa, saddr->sa_data, dev->addr_len);
1497
1498 if (streamer_priv->streamer_message_level) {
1499 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",
1500 dev->name, streamer_priv->streamer_laa[0],
1501 streamer_priv->streamer_laa[1],
1502 streamer_priv->streamer_laa[2],
1503 streamer_priv->streamer_laa[3],
1504 streamer_priv->streamer_laa[4],
1505 streamer_priv->streamer_laa[5]);
1506 }
1507 return 0;
1508}
1509
1510static void streamer_arb_cmd(struct net_device *dev)
1511{
1512 struct streamer_private *streamer_priv =
1513 netdev_priv(dev);
1514 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1515 __u8 header_len;
1516 __u16 frame_len, buffer_len;
1517 struct sk_buff *mac_frame;
1518 __u8 frame_data[256];
1519 __u16 buff_off;
1520 __u16 lan_status = 0, lan_status_diff; /* Initialize to stop compiler warning */
1521 __u8 fdx_prot_error;
1522 __u16 next_ptr;
1523 __u16 arb_word;
1524
1525#if STREAMER_NETWORK_MONITOR
1526 struct trh_hdr *mac_hdr;
1527#endif
1528
1529 writew(streamer_priv->arb, streamer_mmio + LAPA);
1530 arb_word=ntohs(readw(streamer_mmio+LAPD)) >> 8;
1531
1532 if (arb_word == ARB_RECEIVE_DATA) { /* Receive.data, MAC frames */
1533 writew(streamer_priv->arb + 6, streamer_mmio + LAPA);
1534 streamer_priv->mac_rx_buffer = buff_off = ntohs(readw(streamer_mmio + LAPDINC));
1535 header_len=ntohs(readw(streamer_mmio+LAPDINC)) >> 8; /* 802.5 Token-Ring Header Length */
1536 frame_len = ntohs(readw(streamer_mmio + LAPDINC));
1537
1538#if STREAMER_DEBUG
1539 {
1540 int i;
1541 __u16 next;
1542 __u8 status;
1543 __u16 len;
1544
1545 writew(ntohs(buff_off), streamer_mmio + LAPA); /*setup window to frame data */
1546 next = htons(readw(streamer_mmio + LAPDINC));
1547 status =
1548 ntohs(readw(streamer_mmio + LAPDINC)) & 0xff;
1549 len = ntohs(readw(streamer_mmio + LAPDINC));
1550
1551 /* print out 1st 14 bytes of frame data */
1552 for (i = 0; i < 7; i++) {
1553 printk("Loc %d = %04x\n", i,
1554 ntohs(readw
1555 (streamer_mmio + LAPDINC)));
1556 }
1557
1558 printk("next %04x, fs %02x, len %04x\n", next,
1559 status, len);
1560 }
1561#endif
1562 if (!(mac_frame = dev_alloc_skb(frame_len))) {
1563 printk(KERN_WARNING "%s: Memory squeeze, dropping frame.\n",
1564 dev->name);
1565 goto drop_frame;
1566 }
1567 /* Walk the buffer chain, creating the frame */
1568
1569 do {
1570 int i;
1571 __u16 rx_word;
1572
1573 writew(htons(buff_off), streamer_mmio + LAPA); /* setup window to frame data */
1574 next_ptr = ntohs(readw(streamer_mmio + LAPDINC));
1575 readw(streamer_mmio + LAPDINC); /* read thru status word */
1576 buffer_len = ntohs(readw(streamer_mmio + LAPDINC));
1577
1578 if (buffer_len > 256)
1579 break;
1580
1581 i = 0;
1582 while (i < buffer_len) {
1583 rx_word=ntohs(readw(streamer_mmio+LAPDINC));
1584 frame_data[i]=rx_word >> 8;
1585 frame_data[i+1]=rx_word & 0xff;
1586 i += 2;
1587 }
1588
1589 memcpy(skb_put(mac_frame, buffer_len),
1590 frame_data, buffer_len);
1591 } while (next_ptr && (buff_off = next_ptr));
1592
1593 mac_frame->protocol = tr_type_trans(mac_frame, dev);
1594#if STREAMER_NETWORK_MONITOR
1595 printk(KERN_WARNING "%s: Received MAC Frame, details:\n",
1596 dev->name);
1597 mac_hdr = tr_hdr(mac_frame);
1598 printk(KERN_WARNING
1599 "%s: MAC Frame Dest. Addr: %pM\n",
1600 dev->name, mac_hdr->daddr);
1601 printk(KERN_WARNING
1602 "%s: MAC Frame Srce. Addr: %pM\n",
1603 dev->name, mac_hdr->saddr);
1604#endif
1605 netif_rx(mac_frame);
1606
1607 /* Now tell the card we have dealt with the received frame */
1608drop_frame:
1609 /* Set LISR Bit 1 */
1610 writel(LISR_ARB_FREE, streamer_priv->streamer_mmio + LISR_SUM);
1611
1612 /* Is the ASB free ? */
1613
1614 if (!(readl(streamer_priv->streamer_mmio + SISR) & SISR_ASB_FREE))
1615 {
1616 streamer_priv->asb_queued = 1;
1617 writel(LISR_ASB_FREE_REQ, streamer_priv->streamer_mmio + LISR_SUM);
1618 return;
1619 /* Drop out and wait for the bottom half to be run */
1620 }
1621
1622
1623 writew(streamer_priv->asb, streamer_mmio + LAPA);
1624 writew(htons(ASB_RECEIVE_DATA << 8), streamer_mmio+LAPDINC);
1625 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1626 writew(0, streamer_mmio + LAPDINC);
1627 writew(htons(streamer_priv->mac_rx_buffer), streamer_mmio + LAPD);
1628
1629 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ, streamer_priv->streamer_mmio + LISR_SUM);
1630
1631 streamer_priv->asb_queued = 2;
1632 return;
1633
1634 } else if (arb_word == ARB_LAN_CHANGE_STATUS) { /* Lan.change.status */
1635 writew(streamer_priv->arb + 6, streamer_mmio + LAPA);
1636 lan_status = ntohs(readw(streamer_mmio + LAPDINC));
1637 fdx_prot_error = ntohs(readw(streamer_mmio+LAPD)) >> 8;
1638
1639 /* Issue ARB Free */
1640 writew(LISR_ARB_FREE, streamer_priv->streamer_mmio + LISR_SUM);
1641
1642 lan_status_diff = (streamer_priv->streamer_lan_status ^ lan_status) &
1643 lan_status;
1644
1645 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR))
1646 {
1647 if (lan_status_diff & LSC_LWF)
1648 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n", dev->name);
1649 if (lan_status_diff & LSC_ARW)
1650 printk(KERN_WARNING "%s: Auto removal error\n", dev->name);
1651 if (lan_status_diff & LSC_FPE)
1652 printk(KERN_WARNING "%s: FDX Protocol Error\n", dev->name);
1653 if (lan_status_diff & LSC_RR)
1654 printk(KERN_WARNING "%s: Force remove MAC frame received\n", dev->name);
1655
1656 /* Adapter has been closed by the hardware */
1657
1658 /* reset tx/rx fifo's and busmaster logic */
1659
1660 /* @TBD. no llc reset on autostreamer writel(readl(streamer_mmio+BCTL)|(3<<13),streamer_mmio+BCTL);
1661 udelay(1);
1662 writel(readl(streamer_mmio+BCTL)&~(3<<13),streamer_mmio+BCTL); */
1663
1664 netif_stop_queue(dev);
1665 netif_carrier_off(dev);
1666 printk(KERN_WARNING "%s: Adapter must be manually reset.\n", dev->name);
1667 }
1668 /* If serious error */
1669 if (streamer_priv->streamer_message_level) {
1670 if (lan_status_diff & LSC_SIG_LOSS)
1671 printk(KERN_WARNING "%s: No receive signal detected\n", dev->name);
1672 if (lan_status_diff & LSC_HARD_ERR)
1673 printk(KERN_INFO "%s: Beaconing\n", dev->name);
1674 if (lan_status_diff & LSC_SOFT_ERR)
1675 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame\n", dev->name);
1676 if (lan_status_diff & LSC_TRAN_BCN)
1677 printk(KERN_INFO "%s: We are transmitting the beacon, aaah\n", dev->name);
1678 if (lan_status_diff & LSC_SS)
1679 printk(KERN_INFO "%s: Single Station on the ring\n", dev->name);
1680 if (lan_status_diff & LSC_RING_REC)
1681 printk(KERN_INFO "%s: Ring recovery ongoing\n", dev->name);
1682 if (lan_status_diff & LSC_FDX_MODE)
1683 printk(KERN_INFO "%s: Operating in FDX mode\n", dev->name);
1684 }
1685
1686 if (lan_status_diff & LSC_CO) {
1687 if (streamer_priv->streamer_message_level)
1688 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
1689
1690 /* Issue READ.LOG command */
1691
1692 writew(streamer_priv->srb, streamer_mmio + LAPA);
1693 writew(htons(SRB_READ_LOG << 8),streamer_mmio+LAPDINC);
1694 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1695 writew(0, streamer_mmio + LAPDINC);
1696 streamer_priv->srb_queued = 2; /* Can't sleep, use srb_bh */
1697
1698 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1699 }
1700
1701 if (lan_status_diff & LSC_SR_CO) {
1702 if (streamer_priv->streamer_message_level)
1703 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1704
1705 /* Issue a READ.SR.COUNTERS */
1706 writew(streamer_priv->srb, streamer_mmio + LAPA);
1707 writew(htons(SRB_READ_SR_COUNTERS << 8),
1708 streamer_mmio+LAPDINC);
1709 writew(htons(STREAMER_CLEAR_RET_CODE << 8),
1710 streamer_mmio+LAPDINC);
1711 streamer_priv->srb_queued = 2; /* Can't sleep, use srb_bh */
1712 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1713
1714 }
1715 streamer_priv->streamer_lan_status = lan_status;
1716 } /* Lan.change.status */
1717 else
1718 printk(KERN_WARNING "%s: Unknown arb command\n", dev->name);
1719}
1720
1721static void streamer_asb_bh(struct net_device *dev)
1722{
1723 struct streamer_private *streamer_priv =
1724 netdev_priv(dev);
1725 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1726
1727 if (streamer_priv->asb_queued == 1)
1728 {
1729 /* Dropped through the first time */
1730
1731 writew(streamer_priv->asb, streamer_mmio + LAPA);
1732 writew(htons(ASB_RECEIVE_DATA << 8),streamer_mmio+LAPDINC);
1733 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1734 writew(0, streamer_mmio + LAPDINC);
1735 writew(htons(streamer_priv->mac_rx_buffer), streamer_mmio + LAPD);
1736
1737 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ, streamer_priv->streamer_mmio + LISR_SUM);
1738 streamer_priv->asb_queued = 2;
1739
1740 return;
1741 }
1742
1743 if (streamer_priv->asb_queued == 2) {
1744 __u8 rc;
1745 writew(streamer_priv->asb + 2, streamer_mmio + LAPA);
1746 rc=ntohs(readw(streamer_mmio+LAPD)) >> 8;
1747 switch (rc) {
1748 case 0x01:
1749 printk(KERN_WARNING "%s: Unrecognized command code\n", dev->name);
1750 break;
1751 case 0x26:
1752 printk(KERN_WARNING "%s: Unrecognized buffer address\n", dev->name);
1753 break;
1754 case 0xFF:
1755 /* Valid response, everything should be ok again */
1756 break;
1757 default:
1758 printk(KERN_WARNING "%s: Invalid return code in asb\n", dev->name);
1759 break;
1760 }
1761 }
1762 streamer_priv->asb_queued = 0;
1763}
1764
1765static int streamer_change_mtu(struct net_device *dev, int mtu)
1766{
1767 struct streamer_private *streamer_priv =
1768 netdev_priv(dev);
1769 __u16 max_mtu;
1770
1771 if (streamer_priv->streamer_ring_speed == 4)
1772 max_mtu = 4500;
1773 else
1774 max_mtu = 18000;
1775
1776 if (mtu > max_mtu)
1777 return -EINVAL;
1778 if (mtu < 100)
1779 return -EINVAL;
1780
1781 dev->mtu = mtu;
1782 streamer_priv->pkt_buf_sz = mtu + TR_HLEN;
1783
1784 return 0;
1785}
1786
1787#if STREAMER_NETWORK_MONITOR
1788#ifdef CONFIG_PROC_FS
1789static int streamer_proc_info(char *buffer, char **start, off_t offset,
1790 int length, int *eof, void *data)
1791{
1792 struct streamer_private *sdev=NULL;
1793 struct pci_dev *pci_device = NULL;
1794 int len = 0;
1795 off_t begin = 0;
1796 off_t pos = 0;
1797 int size;
1798
1799 struct net_device *dev;
1800
1801 size = sprintf(buffer, "IBM LanStreamer/MPC Chipset Token Ring Adapters\n");
1802
1803 pos += size;
1804 len += size;
1805
1806 for(sdev=dev_streamer; sdev; sdev=sdev->next) {
1807 pci_device=sdev->pci_dev;
1808 dev=pci_get_drvdata(pci_device);
1809
1810 size = sprintf_info(buffer + len, dev);
1811 len += size;
1812 pos = begin + len;
1813
1814 if (pos < offset) {
1815 len = 0;
1816 begin = pos;
1817 }
1818 if (pos > offset + length)
1819 break;
1820 } /* for */
1821
1822 *start = buffer + (offset - begin); /* Start of wanted data */
1823 len -= (offset - begin); /* Start slop */
1824 if (len > length)
1825 len = length; /* Ending slop */
1826 return len;
1827}
1828
1829static int sprintf_info(char *buffer, struct net_device *dev)
1830{
1831 struct streamer_private *streamer_priv =
1832 netdev_priv(dev);
1833 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1834 struct streamer_adapter_addr_table sat;
1835 struct streamer_parameters_table spt;
1836 int size = 0;
1837 int i;
1838
1839 writew(streamer_priv->streamer_addr_table_addr, streamer_mmio + LAPA);
1840 for (i = 0; i < 14; i += 2) {
1841 __u16 io_word;
1842 __u8 *datap = (__u8 *) & sat;
1843 io_word=ntohs(readw(streamer_mmio+LAPDINC));
1844 datap[size]=io_word >> 8;
1845 datap[size+1]=io_word & 0xff;
1846 }
1847 writew(streamer_priv->streamer_parms_addr, streamer_mmio + LAPA);
1848 for (i = 0; i < 68; i += 2) {
1849 __u16 io_word;
1850 __u8 *datap = (__u8 *) & spt;
1851 io_word=ntohs(readw(streamer_mmio+LAPDINC));
1852 datap[size]=io_word >> 8;
1853 datap[size+1]=io_word & 0xff;
1854 }
1855
1856 size = sprintf(buffer, "\n%6s: Adapter Address : Node Address : Functional Addr\n", dev->name);
1857
1858 size += sprintf(buffer + size,
1859 "%6s: %pM : %pM : %02x:%02x:%02x:%02x\n",
1860 dev->name, dev->dev_addr, sat.node_addr,
1861 sat.func_addr[0], sat.func_addr[1],
1862 sat.func_addr[2], sat.func_addr[3]);
1863
1864 size += sprintf(buffer + size, "\n%6s: Token Ring Parameters Table:\n", dev->name);
1865
1866 size += sprintf(buffer + size, "%6s: Physical Addr : Up Node Address : Poll Address : AccPri : Auth Src : Att Code :\n", dev->name);
1867
1868 size += sprintf(buffer + size,
1869 "%6s: %02x:%02x:%02x:%02x : %pM : %pM : %04x : %04x : %04x :\n",
1870 dev->name, spt.phys_addr[0], spt.phys_addr[1],
1871 spt.phys_addr[2], spt.phys_addr[3],
1872 spt.up_node_addr, spt.poll_addr,
1873 ntohs(spt.acc_priority), ntohs(spt.auth_source_class),
1874 ntohs(spt.att_code));
1875
1876 size += sprintf(buffer + size, "%6s: Source Address : Bcn T : Maj. V : Lan St : Lcl Rg : Mon Err : Frame Correl : \n", dev->name);
1877
1878 size += sprintf(buffer + size,
1879 "%6s: %pM : %04x : %04x : %04x : %04x : %04x : %04x : \n",
1880 dev->name, spt.source_addr,
1881 ntohs(spt.beacon_type), ntohs(spt.major_vector),
1882 ntohs(spt.lan_status), ntohs(spt.local_ring),
1883 ntohs(spt.mon_error), ntohs(spt.frame_correl));
1884
1885 size += sprintf(buffer + size, "%6s: Beacon Details : Tx : Rx : NAUN Node Address : NAUN Node Phys : \n",
1886 dev->name);
1887
1888 size += sprintf(buffer + size,
1889 "%6s: : %02x : %02x : %pM : %02x:%02x:%02x:%02x : \n",
1890 dev->name, ntohs(spt.beacon_transmit),
1891 ntohs(spt.beacon_receive),
1892 spt.beacon_naun,
1893 spt.beacon_phys[0], spt.beacon_phys[1],
1894 spt.beacon_phys[2], spt.beacon_phys[3]);
1895 return size;
1896}
1897#endif
1898#endif
1899
1900static struct pci_driver streamer_pci_driver = {
1901 .name = "lanstreamer",
1902 .id_table = streamer_pci_tbl,
1903 .probe = streamer_init_one,
1904 .remove = __devexit_p(streamer_remove_one),
1905};
1906
1907module_pci_driver(streamer_pci_driver);
1908
1909MODULE_LICENSE("GPL");
diff --git a/drivers/net/tokenring/lanstreamer.h b/drivers/net/tokenring/lanstreamer.h
deleted file mode 100644
index 3c58d6a3fbc9..000000000000
--- a/drivers/net/tokenring/lanstreamer.h
+++ /dev/null
@@ -1,343 +0,0 @@
1/*
2 * lanstreamer.h -- driver for the IBM Auto LANStreamer PCI Adapter
3 *
4 * Written By: Mike Sullivan, IBM Corporation
5 *
6 * Copyright (C) 1999 IBM Corporation
7 *
8 * Linux driver for IBM PCI tokenring cards based on the LanStreamer MPC
9 * chipset.
10 *
11 * This driver is based on the olympic driver for IBM PCI TokenRing cards (Pit/Pit-Phy/Olympic
12 * chipsets) written by:
13 * 1999 Peter De Schrijver All Rights Reserved
14 * 1999 Mike Phillips (phillim@amtrak.com)
15 *
16 * Base Driver Skeleton:
17 * Written 1993-94 by Donald Becker.
18 *
19 * Copyright 1993 United States Government as represented by the
20 * Director, National Security Agency.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * NO WARRANTY
33 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
34 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
35 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
36 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
37 * solely responsible for determining the appropriateness of using and
38 * distributing the Program and assumes all risks associated with its
39 * exercise of rights under this Agreement, including but not limited to
40 * the risks and costs of program errors, damage to or loss of data,
41 * programs or equipment, and unavailability or interruption of operations.
42 *
43 * DISCLAIMER OF LIABILITY
44 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
47 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
48 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
49 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
50 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
51 *
52 * You should have received a copy of the GNU General Public License
53 * along with this program; if not, write to the Free Software
54 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
55 *
56 *
57 * 12/10/99 - Alpha Release 0.1.0
58 * First release to the public
59 * 08/15/01 - Added ioctl() definitions and others - Kent Yoder <yoder1@us.ibm.com>
60 *
61 */
62
63/* MAX_INTR - the maximum number of times we can loop
64 * inside the interrupt function before returning
65 * control to the OS (maximum value is 256)
66 */
67#define MAX_INTR 5
68
69#define CLS 0x0C
70#define MLR 0x86
71#define LTR 0x0D
72
73#define BCTL 0x60
74#define BCTL_SOFTRESET (1<<15)
75#define BCTL_RX_FIFO_8 (1<<1)
76#define BCTL_TX_FIFO_8 (1<<3)
77
78#define GPR 0x4a
79#define GPR_AUTOSENSE (1<<2)
80#define GPR_16MBPS (1<<3)
81
82#define LISR 0x10
83#define LISR_SUM 0x12
84#define LISR_RUM 0x14
85
86#define LISR_LIE (1<<15)
87#define LISR_SLIM (1<<13)
88#define LISR_SLI (1<<12)
89#define LISR_BPEI (1<<9)
90#define LISR_BPE (1<<8)
91#define LISR_SRB_CMD (1<<5)
92#define LISR_ASB_REPLY (1<<4)
93#define LISR_ASB_FREE_REQ (1<<2)
94#define LISR_ARB_FREE (1<<1)
95#define LISR_TRB_FRAME (1<<0)
96
97#define SISR 0x16
98#define SISR_SUM 0x18
99#define SISR_RUM 0x1A
100#define SISR_MASK 0x54
101#define SISR_MASK_SUM 0x56
102#define SISR_MASK_RUM 0x58
103
104#define SISR_MI (1<<15)
105#define SISR_SERR_ERR (1<<14)
106#define SISR_TIMER (1<<11)
107#define SISR_LAP_PAR_ERR (1<<10)
108#define SISR_LAP_ACC_ERR (1<<9)
109#define SISR_PAR_ERR (1<<8)
110#define SISR_ADAPTER_CHECK (1<<6)
111#define SISR_SRB_REPLY (1<<5)
112#define SISR_ASB_FREE (1<<4)
113#define SISR_ARB_CMD (1<<3)
114#define SISR_TRB_REPLY (1<<2)
115
116#define MISR_RUM 0x5A
117#define MISR_MASK 0x5C
118#define MISR_MASK_RUM 0x5E
119
120#define MISR_TX2_IDLE (1<<15)
121#define MISR_TX2_NO_STATUS (1<<14)
122#define MISR_TX2_HALT (1<<13)
123#define MISR_TX2_EOF (1<<12)
124#define MISR_TX1_IDLE (1<<11)
125#define MISR_TX1_NO_STATUS (1<<10)
126#define MISR_TX1_HALT (1<<9)
127#define MISR_TX1_EOF (1<<8)
128#define MISR_RX_NOBUF (1<<5)
129#define MISR_RX_EOB (1<<4)
130#define MISR_RX_NO_STATUS (1<<2)
131#define MISR_RX_HALT (1<<1)
132#define MISR_RX_EOF (1<<0)
133
134#define LAPA 0x62
135#define LAPE 0x64
136#define LAPD 0x66
137#define LAPDINC 0x68
138#define LAPWWO 0x6A
139#define LAPWWC 0x6C
140#define LAPCTL 0x6E
141
142#define TIMER 0x4E4
143
144#define BMCTL_SUM 0x50
145#define BMCTL_RUM 0x52
146#define BMCTL_TX1_DIS (1<<14)
147#define BMCTL_TX2_DIS (1<<10)
148#define BMCTL_RX_DIS (1<<6)
149#define BMCTL_RX_ENABLED (1<<5)
150
151#define RXLBDA 0x90
152#define RXBDA 0x94
153#define RXSTAT 0x98
154#define RXDBA 0x9C
155
156#define TX1LFDA 0xA0
157#define TX1FDA 0xA4
158#define TX1STAT 0xA8
159#define TX1DBA 0xAC
160#define TX2LFDA 0xB0
161#define TX2FDA 0xB4
162#define TX2STAT 0xB8
163#define TX2DBA 0xBC
164
165#define STREAMER_IO_SPACE 256
166
167#define SRB_COMMAND_SIZE 50
168
169#define STREAMER_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
170
171/* Defines for LAN STATUS CHANGE reports */
172#define LSC_SIG_LOSS 0x8000
173#define LSC_HARD_ERR 0x4000
174#define LSC_SOFT_ERR 0x2000
175#define LSC_TRAN_BCN 0x1000
176#define LSC_LWF 0x0800
177#define LSC_ARW 0x0400
178#define LSC_FPE 0x0200
179#define LSC_RR 0x0100
180#define LSC_CO 0x0080
181#define LSC_SS 0x0040
182#define LSC_RING_REC 0x0020
183#define LSC_SR_CO 0x0010
184#define LSC_FDX_MODE 0x0004
185
186/* Defines for OPEN ADAPTER command */
187
188#define OPEN_ADAPTER_EXT_WRAP (1<<15)
189#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
190#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
191#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
192#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
193#define OPEN_ADAPTER_ENABLE_EC (1<<10)
194#define OPEN_ADAPTER_CONTENDER (1<<8)
195#define OPEN_ADAPTER_PASS_BEACON (1<<7)
196#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
197#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
198#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
199#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
200
201
202/* Defines for SRB Commands */
203#define SRB_CLOSE_ADAPTER 0x04
204#define SRB_CONFIGURE_BRIDGE 0x0c
205#define SRB_CONFIGURE_HP_CHANNEL 0x13
206#define SRB_MODIFY_BRIDGE_PARMS 0x15
207#define SRB_MODIFY_OPEN_OPTIONS 0x01
208#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
209#define SRB_NO_OPERATION 0x00
210#define SRB_OPEN_ADAPTER 0x03
211#define SRB_READ_LOG 0x08
212#define SRB_READ_SR_COUNTERS 0x16
213#define SRB_RESET_GROUP_ADDRESS 0x02
214#define SRB_RESET_TARGET_SEGMETN 0x14
215#define SRB_SAVE_CONFIGURATION 0x1b
216#define SRB_SET_BRIDGE_PARMS 0x09
217#define SRB_SET_FUNC_ADDRESS 0x07
218#define SRB_SET_GROUP_ADDRESS 0x06
219#define SRB_SET_TARGET_SEGMENT 0x05
220
221/* Clear return code */
222#define STREAMER_CLEAR_RET_CODE 0xfe
223
224/* ARB Commands */
225#define ARB_RECEIVE_DATA 0x81
226#define ARB_LAN_CHANGE_STATUS 0x84
227
228/* ASB Response commands */
229#define ASB_RECEIVE_DATA 0x81
230
231
232/* Streamer defaults for buffers */
233
234#define STREAMER_RX_RING_SIZE 16 /* should be a power of 2 */
235/* Setting the number of TX descriptors to 1 is a workaround for an
236 * undocumented hardware problem with the lanstreamer board. Setting
237 * this to something higher may slightly increase the throughput you
238 * can get from the card, but at the risk of locking up the box. -
239 * <yoder1@us.ibm.com>
240 */
241#define STREAMER_TX_RING_SIZE 1 /* should be a power of 2 */
242
243#define PKT_BUF_SZ 4096 /* Default packet size */
244
245/* Streamer data structures */
246
247struct streamer_tx_desc {
248 __u32 forward;
249 __u32 status;
250 __u32 bufcnt_framelen;
251 __u32 buffer;
252 __u32 buflen;
253 __u32 rsvd1;
254 __u32 rsvd2;
255 __u32 rsvd3;
256};
257
258struct streamer_rx_desc {
259 __u32 forward;
260 __u32 status;
261 __u32 buffer;
262 __u32 framelen_buflen;
263};
264
265struct mac_receive_buffer {
266 __u16 next;
267 __u8 padding;
268 __u8 frame_status;
269 __u16 buffer_length;
270 __u8 frame_data;
271};
272
273struct streamer_private {
274
275 __u16 srb;
276 __u16 trb;
277 __u16 arb;
278 __u16 asb;
279
280 struct streamer_private *next;
281 struct pci_dev *pci_dev;
282 __u8 __iomem *streamer_mmio;
283 char *streamer_card_name;
284
285 spinlock_t streamer_lock;
286
287 volatile int srb_queued; /* True if an SRB is still posted */
288 wait_queue_head_t srb_wait;
289
290 volatile int asb_queued; /* True if an ASB is posted */
291
292 volatile int trb_queued; /* True if a TRB is posted */
293 wait_queue_head_t trb_wait;
294
295 struct streamer_rx_desc *streamer_rx_ring;
296 struct streamer_tx_desc *streamer_tx_ring;
297 struct sk_buff *tx_ring_skb[STREAMER_TX_RING_SIZE],
298 *rx_ring_skb[STREAMER_RX_RING_SIZE];
299 int tx_ring_free, tx_ring_last_status, rx_ring_last_received,
300 free_tx_ring_entries;
301
302 __u16 streamer_lan_status;
303 __u8 streamer_ring_speed;
304 __u16 pkt_buf_sz;
305 __u8 streamer_receive_options, streamer_copy_all_options,
306 streamer_message_level;
307 __u16 streamer_addr_table_addr, streamer_parms_addr;
308 __u16 mac_rx_buffer;
309 __u8 streamer_laa[6];
310};
311
312struct streamer_adapter_addr_table {
313
314 __u8 node_addr[6];
315 __u8 reserved[4];
316 __u8 func_addr[4];
317};
318
319struct streamer_parameters_table {
320
321 __u8 phys_addr[4];
322 __u8 up_node_addr[6];
323 __u8 up_phys_addr[4];
324 __u8 poll_addr[6];
325 __u16 reserved;
326 __u16 acc_priority;
327 __u16 auth_source_class;
328 __u16 att_code;
329 __u8 source_addr[6];
330 __u16 beacon_type;
331 __u16 major_vector;
332 __u16 lan_status;
333 __u16 soft_error_time;
334 __u16 reserved1;
335 __u16 local_ring;
336 __u16 mon_error;
337 __u16 beacon_transmit;
338 __u16 beacon_receive;
339 __u16 frame_correl;
340 __u8 beacon_naun[6];
341 __u32 reserved2;
342 __u8 beacon_phys[4];
343};
diff --git a/drivers/net/tokenring/madgemc.c b/drivers/net/tokenring/madgemc.c
deleted file mode 100644
index 28adcdf3b14c..000000000000
--- a/drivers/net/tokenring/madgemc.c
+++ /dev/null
@@ -1,761 +0,0 @@
1/*
2 * madgemc.c: Driver for the Madge Smart 16/4 MC16 MCA token ring card.
3 *
4 * Written 2000 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - Madge Smart 16/4 Ringnode MC16
11 * - Madge Smart 16/4 Ringnode MC32 (??)
12 *
13 * Maintainer(s):
14 * AF Adam Fritzler
15 *
16 * Modification History:
17 * 16-Jan-00 AF Created
18 *
19 */
20static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n";
21
22#include <linux/module.h>
23#include <linux/mca.h>
24#include <linux/slab.h>
25#include <linux/kernel.h>
26#include <linux/errno.h>
27#include <linux/init.h>
28#include <linux/netdevice.h>
29#include <linux/trdevice.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33
34#include "tms380tr.h"
35#include "madgemc.h" /* Madge-specific constants */
36
37#define MADGEMC_IO_EXTENT 32
38#define MADGEMC_SIF_OFFSET 0x08
39
40struct card_info {
41 /*
42 * These are read from the BIA ROM.
43 */
44 unsigned int manid;
45 unsigned int cardtype;
46 unsigned int cardrev;
47 unsigned int ramsize;
48
49 /*
50 * These are read from the MCA POS registers.
51 */
52 unsigned int burstmode:2;
53 unsigned int fairness:1; /* 0 = Fair, 1 = Unfair */
54 unsigned int arblevel:4;
55 unsigned int ringspeed:2; /* 0 = 4mb, 1 = 16, 2 = Auto/none */
56 unsigned int cabletype:1; /* 0 = RJ45, 1 = DB9 */
57};
58
59static int madgemc_open(struct net_device *dev);
60static int madgemc_close(struct net_device *dev);
61static int madgemc_chipset_init(struct net_device *dev);
62static void madgemc_read_rom(struct net_device *dev, struct card_info *card);
63static unsigned short madgemc_setnselout_pins(struct net_device *dev);
64static void madgemc_setcabletype(struct net_device *dev, int type);
65
66static int madgemc_mcaproc(char *buf, int slot, void *d);
67
68static void madgemc_setregpage(struct net_device *dev, int page);
69static void madgemc_setsifsel(struct net_device *dev, int val);
70static void madgemc_setint(struct net_device *dev, int val);
71
72static irqreturn_t madgemc_interrupt(int irq, void *dev_id);
73
74/*
75 * These work around paging, however they don't guarantee you're on the
76 * right page.
77 */
78#define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
79#define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
80#define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
81#define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
82
83/*
84 * Read a byte-length value from the register.
85 */
86static unsigned short madgemc_sifreadb(struct net_device *dev, unsigned short reg)
87{
88 unsigned short ret;
89 if (reg<0x8)
90 ret = SIFREADB(reg);
91 else {
92 madgemc_setregpage(dev, 1);
93 ret = SIFREADB(reg);
94 madgemc_setregpage(dev, 0);
95 }
96 return ret;
97}
98
99/*
100 * Write a byte-length value to a register.
101 */
102static void madgemc_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
103{
104 if (reg<0x8)
105 SIFWRITEB(val, reg);
106 else {
107 madgemc_setregpage(dev, 1);
108 SIFWRITEB(val, reg);
109 madgemc_setregpage(dev, 0);
110 }
111}
112
113/*
114 * Read a word-length value from a register
115 */
116static unsigned short madgemc_sifreadw(struct net_device *dev, unsigned short reg)
117{
118 unsigned short ret;
119 if (reg<0x8)
120 ret = SIFREADW(reg);
121 else {
122 madgemc_setregpage(dev, 1);
123 ret = SIFREADW(reg);
124 madgemc_setregpage(dev, 0);
125 }
126 return ret;
127}
128
129/*
130 * Write a word-length value to a register.
131 */
132static void madgemc_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
133{
134 if (reg<0x8)
135 SIFWRITEW(val, reg);
136 else {
137 madgemc_setregpage(dev, 1);
138 SIFWRITEW(val, reg);
139 madgemc_setregpage(dev, 0);
140 }
141}
142
143static struct net_device_ops madgemc_netdev_ops __read_mostly;
144
145static int __devinit madgemc_probe(struct device *device)
146{
147 static int versionprinted;
148 struct net_device *dev;
149 struct net_local *tp;
150 struct card_info *card;
151 struct mca_device *mdev = to_mca_device(device);
152 int ret = 0;
153
154 if (versionprinted++ == 0)
155 printk("%s", version);
156
157 if(mca_device_claimed(mdev))
158 return -EBUSY;
159 mca_device_set_claim(mdev, 1);
160
161 dev = alloc_trdev(sizeof(struct net_local));
162 if (!dev) {
163 printk("madgemc: unable to allocate dev space\n");
164 mca_device_set_claim(mdev, 0);
165 ret = -ENOMEM;
166 goto getout;
167 }
168
169 dev->netdev_ops = &madgemc_netdev_ops;
170
171 card = kmalloc(sizeof(struct card_info), GFP_KERNEL);
172 if (card==NULL) {
173 ret = -ENOMEM;
174 goto getout1;
175 }
176
177 /*
178 * Parse configuration information. This all comes
179 * directly from the publicly available @002d.ADF.
180 * Get it from Madge or your local ADF library.
181 */
182
183 /*
184 * Base address
185 */
186 dev->base_addr = 0x0a20 +
187 ((mdev->pos[2] & MC16_POS2_ADDR2)?0x0400:0) +
188 ((mdev->pos[0] & MC16_POS0_ADDR1)?0x1000:0) +
189 ((mdev->pos[3] & MC16_POS3_ADDR3)?0x2000:0);
190
191 /*
192 * Interrupt line
193 */
194 switch(mdev->pos[0] >> 6) { /* upper two bits */
195 case 0x1: dev->irq = 3; break;
196 case 0x2: dev->irq = 9; break; /* IRQ 2 = IRQ 9 */
197 case 0x3: dev->irq = 10; break;
198 default: dev->irq = 0; break;
199 }
200
201 if (dev->irq == 0) {
202 printk("%s: invalid IRQ\n", dev->name);
203 ret = -EBUSY;
204 goto getout2;
205 }
206
207 if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT,
208 "madgemc")) {
209 printk(KERN_INFO "madgemc: unable to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", mdev->slot, dev->base_addr);
210 dev->base_addr += MADGEMC_SIF_OFFSET;
211 ret = -EBUSY;
212 goto getout2;
213 }
214 dev->base_addr += MADGEMC_SIF_OFFSET;
215
216 /*
217 * Arbitration Level
218 */
219 card->arblevel = ((mdev->pos[0] >> 1) & 0x7) + 8;
220
221 /*
222 * Burst mode and Fairness
223 */
224 card->burstmode = ((mdev->pos[2] >> 6) & 0x3);
225 card->fairness = ((mdev->pos[2] >> 4) & 0x1);
226
227 /*
228 * Ring Speed
229 */
230 if ((mdev->pos[1] >> 2)&0x1)
231 card->ringspeed = 2; /* not selected */
232 else if ((mdev->pos[2] >> 5) & 0x1)
233 card->ringspeed = 1; /* 16Mb */
234 else
235 card->ringspeed = 0; /* 4Mb */
236
237 /*
238 * Cable type
239 */
240 if ((mdev->pos[1] >> 6)&0x1)
241 card->cabletype = 1; /* STP/DB9 */
242 else
243 card->cabletype = 0; /* UTP/RJ-45 */
244
245
246 /*
247 * ROM Info. This requires us to actually twiddle
248 * bits on the card, so we must ensure above that
249 * the base address is free of conflict (request_region above).
250 */
251 madgemc_read_rom(dev, card);
252
253 if (card->manid != 0x4d) { /* something went wrong */
254 printk(KERN_INFO "%s: Madge MC ROM read failed (unknown manufacturer ID %02x)\n", dev->name, card->manid);
255 goto getout3;
256 }
257
258 if ((card->cardtype != 0x08) && (card->cardtype != 0x0d)) {
259 printk(KERN_INFO "%s: Madge MC ROM read failed (unknown card ID %02x)\n", dev->name, card->cardtype);
260 ret = -EIO;
261 goto getout3;
262 }
263
264 /* All cards except Rev 0 and 1 MC16's have 256kb of RAM */
265 if ((card->cardtype == 0x08) && (card->cardrev <= 0x01))
266 card->ramsize = 128;
267 else
268 card->ramsize = 256;
269
270 printk("%s: %s Rev %d at 0x%04lx IRQ %d\n",
271 dev->name,
272 (card->cardtype == 0x08)?MADGEMC16_CARDNAME:
273 MADGEMC32_CARDNAME, card->cardrev,
274 dev->base_addr, dev->irq);
275
276 if (card->cardtype == 0x0d)
277 printk("%s: Warning: MC32 support is experimental and highly untested\n", dev->name);
278
279 if (card->ringspeed==2) { /* Unknown */
280 printk("%s: Warning: Ring speed not set in POS -- Please run the reference disk and set it!\n", dev->name);
281 card->ringspeed = 1; /* default to 16mb */
282 }
283
284 printk("%s: RAM Size: %dKB\n", dev->name, card->ramsize);
285
286 printk("%s: Ring Speed: %dMb/sec on %s\n", dev->name,
287 (card->ringspeed)?16:4,
288 card->cabletype?"STP/DB9":"UTP/RJ-45");
289 printk("%s: Arbitration Level: %d\n", dev->name,
290 card->arblevel);
291
292 printk("%s: Burst Mode: ", dev->name);
293 switch(card->burstmode) {
294 case 0: printk("Cycle steal"); break;
295 case 1: printk("Limited burst"); break;
296 case 2: printk("Delayed release"); break;
297 case 3: printk("Immediate release"); break;
298 }
299 printk(" (%s)\n", (card->fairness)?"Unfair":"Fair");
300
301
302 /*
303 * Enable SIF before we assign the interrupt handler,
304 * just in case we get spurious interrupts that need
305 * handling.
306 */
307 outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */
308 madgemc_setsifsel(dev, 1);
309 if (request_irq(dev->irq, madgemc_interrupt, IRQF_SHARED,
310 "madgemc", dev)) {
311 ret = -EBUSY;
312 goto getout3;
313 }
314
315 madgemc_chipset_init(dev); /* enables interrupts! */
316 madgemc_setcabletype(dev, card->cabletype);
317
318 /* Setup MCA structures */
319 mca_device_set_name(mdev, (card->cardtype == 0x08)?MADGEMC16_CARDNAME:MADGEMC32_CARDNAME);
320 mca_set_adapter_procfn(mdev->slot, madgemc_mcaproc, dev);
321
322 printk("%s: Ring Station Address: %pM\n",
323 dev->name, dev->dev_addr);
324
325 if (tmsdev_init(dev, device)) {
326 printk("%s: unable to get memory for dev->priv.\n",
327 dev->name);
328 ret = -ENOMEM;
329 goto getout4;
330 }
331 tp = netdev_priv(dev);
332
333 /*
334 * The MC16 is physically a 32bit card. However, Madge
335 * insists on calling it 16bit, so I'll assume here that
336 * they know what they're talking about. Cut off DMA
337 * at 16mb.
338 */
339 tp->setnselout = madgemc_setnselout_pins;
340 tp->sifwriteb = madgemc_sifwriteb;
341 tp->sifreadb = madgemc_sifreadb;
342 tp->sifwritew = madgemc_sifwritew;
343 tp->sifreadw = madgemc_sifreadw;
344 tp->DataRate = (card->ringspeed)?SPEED_16:SPEED_4;
345
346 memcpy(tp->ProductID, "Madge MCA 16/4 ", PROD_ID_SIZE + 1);
347
348 tp->tmspriv = card;
349 dev_set_drvdata(device, dev);
350
351 if (register_netdev(dev) == 0)
352 return 0;
353
354 dev_set_drvdata(device, NULL);
355 ret = -ENOMEM;
356getout4:
357 free_irq(dev->irq, dev);
358getout3:
359 release_region(dev->base_addr-MADGEMC_SIF_OFFSET,
360 MADGEMC_IO_EXTENT);
361getout2:
362 kfree(card);
363getout1:
364 free_netdev(dev);
365getout:
366 mca_device_set_claim(mdev, 0);
367 return ret;
368}
369
370/*
371 * Handle interrupts generated by the card
372 *
373 * The MicroChannel Madge cards need slightly more handling
374 * after an interrupt than other TMS380 cards do.
375 *
376 * First we must make sure it was this card that generated the
377 * interrupt (since interrupt sharing is allowed). Then,
378 * because we're using level-triggered interrupts (as is
379 * standard on MCA), we must toggle the interrupt line
380 * on the card in order to claim and acknowledge the interrupt.
381 * Once that is done, the interrupt should be handlable in
382 * the normal tms380tr_interrupt() routine.
383 *
384 * There's two ways we can check to see if the interrupt is ours,
385 * both with their own disadvantages...
386 *
387 * 1) Read in the SIFSTS register from the TMS controller. This
388 * is guaranteed to be accurate, however, there's a fairly
389 * large performance penalty for doing so: the Madge chips
390 * must request the register from the Eagle, the Eagle must
391 * read them from its internal bus, and then take the route
392 * back out again, for a 16bit read.
393 *
394 * 2) Use the MC_CONTROL_REG0_SINTR bit from the Madge ASICs.
395 * The major disadvantage here is that the accuracy of the
396 * bit is in question. However, it cuts out the extra read
397 * cycles it takes to read the Eagle's SIF, as its only an
398 * 8bit read, and theoretically the Madge bit is directly
399 * connected to the interrupt latch coming out of the Eagle
400 * hardware (that statement is not verified).
401 *
402 * I can't determine which of these methods has the best win. For now,
403 * we make a compromise. Use the Madge way for the first interrupt,
404 * which should be the fast-path, and then once we hit the first
405 * interrupt, keep on trying using the SIF method until we've
406 * exhausted all contiguous interrupts.
407 *
408 */
409static irqreturn_t madgemc_interrupt(int irq, void *dev_id)
410{
411 int pending,reg1;
412 struct net_device *dev;
413
414 if (!dev_id) {
415 printk("madgemc_interrupt: was not passed a dev_id!\n");
416 return IRQ_NONE;
417 }
418
419 dev = dev_id;
420
421 /* Make sure its really us. -- the Madge way */
422 pending = inb(dev->base_addr + MC_CONTROL_REG0);
423 if (!(pending & MC_CONTROL_REG0_SINTR))
424 return IRQ_NONE; /* not our interrupt */
425
426 /*
427 * Since we're level-triggered, we may miss the rising edge
428 * of the next interrupt while we're off handling this one,
429 * so keep checking until the SIF verifies that it has nothing
430 * left for us to do.
431 */
432 pending = STS_SYSTEM_IRQ;
433 do {
434 if (pending & STS_SYSTEM_IRQ) {
435
436 /* Toggle the interrupt to reset the latch on card */
437 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
438 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
439 dev->base_addr + MC_CONTROL_REG1);
440 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
441
442 /* Continue handling as normal */
443 tms380tr_interrupt(irq, dev_id);
444
445 pending = SIFREADW(SIFSTS); /* restart - the SIF way */
446
447 } else
448 return IRQ_HANDLED;
449 } while (1);
450
451 return IRQ_HANDLED; /* not reachable */
452}
453
454/*
455 * Set the card to the preferred ring speed.
456 *
457 * Unlike newer cards, the MC16/32 have their speed selection
458 * circuit connected to the Madge ASICs and not to the TMS380
459 * NSELOUT pins. Set the ASIC bits correctly here, and return
460 * zero to leave the TMS NSELOUT bits unaffected.
461 *
462 */
463static unsigned short madgemc_setnselout_pins(struct net_device *dev)
464{
465 unsigned char reg1;
466 struct net_local *tp = netdev_priv(dev);
467
468 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
469
470 if(tp->DataRate == SPEED_16)
471 reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */
472 else if (reg1 & MC_CONTROL_REG1_SPEED_SEL)
473 reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */
474 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
475
476 return 0; /* no change */
477}
478
479/*
480 * Set the register page. This equates to the SRSX line
481 * on the TMS380Cx6.
482 *
483 * Register selection is normally done via three contiguous
484 * bits. However, some boards (such as the MC16/32) use only
485 * two bits, plus a separate bit in the glue chip. This
486 * sets the SRSX bit (the top bit). See page 4-17 in the
487 * Yellow Book for which registers are affected.
488 *
489 */
490static void madgemc_setregpage(struct net_device *dev, int page)
491{
492 static int reg1;
493
494 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
495 if ((page == 0) && (reg1 & MC_CONTROL_REG1_SRSX)) {
496 outb(reg1 ^ MC_CONTROL_REG1_SRSX,
497 dev->base_addr + MC_CONTROL_REG1);
498 }
499 else if (page == 1) {
500 outb(reg1 | MC_CONTROL_REG1_SRSX,
501 dev->base_addr + MC_CONTROL_REG1);
502 }
503 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
504}
505
506/*
507 * The SIF registers are not mapped into register space by default
508 * Set this to 1 to map them, 0 to map the BIA ROM.
509 *
510 */
511static void madgemc_setsifsel(struct net_device *dev, int val)
512{
513 unsigned int reg0;
514
515 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
516 if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) {
517 outb(reg0 ^ MC_CONTROL_REG0_SIFSEL,
518 dev->base_addr + MC_CONTROL_REG0);
519 } else if (val == 1) {
520 outb(reg0 | MC_CONTROL_REG0_SIFSEL,
521 dev->base_addr + MC_CONTROL_REG0);
522 }
523 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
524}
525
526/*
527 * Enable SIF interrupts
528 *
529 * This does not enable interrupts in the SIF, but rather
530 * enables SIF interrupts to be passed onto the host.
531 *
532 */
533static void madgemc_setint(struct net_device *dev, int val)
534{
535 unsigned int reg1;
536
537 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
538 if ((val == 0) && (reg1 & MC_CONTROL_REG1_SINTEN)) {
539 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
540 dev->base_addr + MC_CONTROL_REG1);
541 } else if (val == 1) {
542 outb(reg1 | MC_CONTROL_REG1_SINTEN,
543 dev->base_addr + MC_CONTROL_REG1);
544 }
545}
546
547/*
548 * Cable type is set via control register 7. Bit zero high
549 * for UTP, low for STP.
550 */
551static void madgemc_setcabletype(struct net_device *dev, int type)
552{
553 outb((type==0)?MC_CONTROL_REG7_CABLEUTP:MC_CONTROL_REG7_CABLESTP,
554 dev->base_addr + MC_CONTROL_REG7);
555}
556
557/*
558 * Enable the functions of the Madge chipset needed for
559 * full working order.
560 */
561static int madgemc_chipset_init(struct net_device *dev)
562{
563 outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */
564 tms380tr_wait(100); /* wait for card to reset */
565
566 /* bring back into normal operating mode */
567 outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1);
568
569 /* map SIF registers */
570 madgemc_setsifsel(dev, 1);
571
572 /* enable SIF interrupts */
573 madgemc_setint(dev, 1);
574
575 return 0;
576}
577
578/*
579 * Disable the board, and put back into power-up state.
580 */
581static void madgemc_chipset_close(struct net_device *dev)
582{
583 /* disable interrupts */
584 madgemc_setint(dev, 0);
585 /* unmap SIF registers */
586 madgemc_setsifsel(dev, 0);
587}
588
589/*
590 * Read the card type (MC16 or MC32) from the card.
591 *
592 * The configuration registers are stored in two separate
593 * pages. Pages are flipped by clearing bit 3 of CONTROL_REG0 (PAGE)
594 * for page zero, or setting bit 3 for page one.
595 *
596 * Page zero contains the following data:
597 * Byte 0: Manufacturer ID (0x4D -- ASCII "M")
598 * Byte 1: Card type:
599 * 0x08 for MC16
600 * 0x0D for MC32
601 * Byte 2: Card revision
602 * Byte 3: Mirror of POS config register 0
603 * Byte 4: Mirror of POS 1
604 * Byte 5: Mirror of POS 2
605 *
606 * Page one contains the following data:
607 * Byte 0: Unused
608 * Byte 1-6: BIA, MSB to LSB.
609 *
610 * Note that to read the BIA, we must unmap the SIF registers
611 * by clearing bit 2 of CONTROL_REG0 (SIFSEL), as the data
612 * will reside in the same logical location. For this reason,
613 * _never_ read the BIA while the Eagle processor is running!
614 * The SIF will be completely inaccessible until the BIA operation
615 * is complete.
616 *
617 */
618static void madgemc_read_rom(struct net_device *dev, struct card_info *card)
619{
620 unsigned long ioaddr;
621 unsigned char reg0, reg1, tmpreg0, i;
622
623 ioaddr = dev->base_addr;
624
625 reg0 = inb(ioaddr + MC_CONTROL_REG0);
626 reg1 = inb(ioaddr + MC_CONTROL_REG1);
627
628 /* Switch to page zero and unmap SIF */
629 tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL);
630 outb(tmpreg0, ioaddr + MC_CONTROL_REG0);
631
632 card->manid = inb(ioaddr + MC_ROM_MANUFACTURERID);
633 card->cardtype = inb(ioaddr + MC_ROM_ADAPTERID);
634 card->cardrev = inb(ioaddr + MC_ROM_REVISION);
635
636 /* Switch to rom page one */
637 outb(tmpreg0 | MC_CONTROL_REG0_PAGE, ioaddr + MC_CONTROL_REG0);
638
639 /* Read BIA */
640 dev->addr_len = 6;
641 for (i = 0; i < 6; i++)
642 dev->dev_addr[i] = inb(ioaddr + MC_ROM_BIA_START + i);
643
644 /* Restore original register values */
645 outb(reg0, ioaddr + MC_CONTROL_REG0);
646 outb(reg1, ioaddr + MC_CONTROL_REG1);
647}
648
649static int madgemc_open(struct net_device *dev)
650{
651 /*
652 * Go ahead and reinitialize the chipset again, just to
653 * make sure we didn't get left in a bad state.
654 */
655 madgemc_chipset_init(dev);
656 tms380tr_open(dev);
657 return 0;
658}
659
660static int madgemc_close(struct net_device *dev)
661{
662 tms380tr_close(dev);
663 madgemc_chipset_close(dev);
664 return 0;
665}
666
667/*
668 * Give some details available from /proc/mca/slotX
669 */
670static int madgemc_mcaproc(char *buf, int slot, void *d)
671{
672 struct net_device *dev = (struct net_device *)d;
673 struct net_local *tp = netdev_priv(dev);
674 struct card_info *curcard = tp->tmspriv;
675 int len = 0;
676
677 len += sprintf(buf+len, "-------\n");
678 if (curcard) {
679 len += sprintf(buf+len, "Card Revision: %d\n", curcard->cardrev);
680 len += sprintf(buf+len, "RAM Size: %dkb\n", curcard->ramsize);
681 len += sprintf(buf+len, "Cable type: %s\n", (curcard->cabletype)?"STP/DB9":"UTP/RJ-45");
682 len += sprintf(buf+len, "Configured ring speed: %dMb/sec\n", (curcard->ringspeed)?16:4);
683 len += sprintf(buf+len, "Running ring speed: %dMb/sec\n", (tp->DataRate==SPEED_16)?16:4);
684 len += sprintf(buf+len, "Device: %s\n", dev->name);
685 len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr);
686 len += sprintf(buf+len, "IRQ: %d\n", dev->irq);
687 len += sprintf(buf+len, "Arbitration Level: %d\n", curcard->arblevel);
688 len += sprintf(buf+len, "Burst Mode: ");
689 switch(curcard->burstmode) {
690 case 0: len += sprintf(buf+len, "Cycle steal"); break;
691 case 1: len += sprintf(buf+len, "Limited burst"); break;
692 case 2: len += sprintf(buf+len, "Delayed release"); break;
693 case 3: len += sprintf(buf+len, "Immediate release"); break;
694 }
695 len += sprintf(buf+len, " (%s)\n", (curcard->fairness)?"Unfair":"Fair");
696
697 len += sprintf(buf+len, "Ring Station Address: %pM\n",
698 dev->dev_addr);
699 } else
700 len += sprintf(buf+len, "Card not configured\n");
701
702 return len;
703}
704
705static int __devexit madgemc_remove(struct device *device)
706{
707 struct net_device *dev = dev_get_drvdata(device);
708 struct net_local *tp;
709 struct card_info *card;
710
711 BUG_ON(!dev);
712
713 tp = netdev_priv(dev);
714 card = tp->tmspriv;
715 kfree(card);
716 tp->tmspriv = NULL;
717
718 unregister_netdev(dev);
719 release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT);
720 free_irq(dev->irq, dev);
721 tmsdev_term(dev);
722 free_netdev(dev);
723 dev_set_drvdata(device, NULL);
724
725 return 0;
726}
727
728static short madgemc_adapter_ids[] __initdata = {
729 0x002d,
730 0x0000
731};
732
733static struct mca_driver madgemc_driver = {
734 .id_table = madgemc_adapter_ids,
735 .driver = {
736 .name = "madgemc",
737 .bus = &mca_bus_type,
738 .probe = madgemc_probe,
739 .remove = __devexit_p(madgemc_remove),
740 },
741};
742
743static int __init madgemc_init (void)
744{
745 madgemc_netdev_ops = tms380tr_netdev_ops;
746 madgemc_netdev_ops.ndo_open = madgemc_open;
747 madgemc_netdev_ops.ndo_stop = madgemc_close;
748
749 return mca_register_driver (&madgemc_driver);
750}
751
752static void __exit madgemc_exit (void)
753{
754 mca_unregister_driver (&madgemc_driver);
755}
756
757module_init(madgemc_init);
758module_exit(madgemc_exit);
759
760MODULE_LICENSE("GPL");
761
diff --git a/drivers/net/tokenring/madgemc.h b/drivers/net/tokenring/madgemc.h
deleted file mode 100644
index fe88e272c531..000000000000
--- a/drivers/net/tokenring/madgemc.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * madgemc.h: Header for the madgemc tms380tr module
3 *
4 * Authors:
5 * - Adam Fritzler
6 */
7
8#ifndef __LINUX_MADGEMC_H
9#define __LINUX_MADGEMC_H
10
11#ifdef __KERNEL__
12
13#define MADGEMC16_CARDNAME "Madge Smart 16/4 MC16 Ringnode"
14#define MADGEMC32_CARDNAME "Madge Smart 16/4 MC32 Ringnode"
15
16/*
17 * Bit definitions for the POS config registers
18 */
19#define MC16_POS0_ADDR1 0x20
20#define MC16_POS2_ADDR2 0x04
21#define MC16_POS3_ADDR3 0x20
22
23#define MC_CONTROL_REG0 ((long)-8) /* 0x00 */
24#define MC_CONTROL_REG1 ((long)-7) /* 0x01 */
25#define MC_ADAPTER_POS_REG0 ((long)-6) /* 0x02 */
26#define MC_ADAPTER_POS_REG1 ((long)-5) /* 0x03 */
27#define MC_ADAPTER_POS_REG2 ((long)-4) /* 0x04 */
28#define MC_ADAPTER_REG5_UNUSED ((long)-3) /* 0x05 */
29#define MC_ADAPTER_REG6_UNUSED ((long)-2) /* 0x06 */
30#define MC_CONTROL_REG7 ((long)-1) /* 0x07 */
31
32#define MC_CONTROL_REG0_UNKNOWN1 0x01
33#define MC_CONTROL_REG0_UNKNOWN2 0x02
34#define MC_CONTROL_REG0_SIFSEL 0x04
35#define MC_CONTROL_REG0_PAGE 0x08
36#define MC_CONTROL_REG0_TESTINTERRUPT 0x10
37#define MC_CONTROL_REG0_UNKNOWN20 0x20
38#define MC_CONTROL_REG0_SINTR 0x40
39#define MC_CONTROL_REG0_UNKNOWN80 0x80
40
41#define MC_CONTROL_REG1_SINTEN 0x01
42#define MC_CONTROL_REG1_BITOFDEATH 0x02
43#define MC_CONTROL_REG1_NSRESET 0x04
44#define MC_CONTROL_REG1_UNKNOWN8 0x08
45#define MC_CONTROL_REG1_UNKNOWN10 0x10
46#define MC_CONTROL_REG1_UNKNOWN20 0x20
47#define MC_CONTROL_REG1_SRSX 0x40
48#define MC_CONTROL_REG1_SPEED_SEL 0x80
49
50#define MC_CONTROL_REG7_CABLESTP 0x00
51#define MC_CONTROL_REG7_CABLEUTP 0x01
52
53/*
54 * ROM Page Zero
55 */
56#define MC_ROM_MANUFACTURERID 0x00
57#define MC_ROM_ADAPTERID 0x01
58#define MC_ROM_REVISION 0x02
59#define MC_ROM_CONFIG0 0x03
60#define MC_ROM_CONFIG1 0x04
61#define MC_ROM_CONFIG2 0x05
62
63/*
64 * ROM Page One
65 */
66#define MC_ROM_UNUSED_BYTE 0x00
67#define MC_ROM_BIA_START 0x01
68
69#endif /* __KERNEL__ */
70#endif /* __LINUX_MADGEMC_H */
diff --git a/drivers/net/tokenring/olympic.c b/drivers/net/tokenring/olympic.c
deleted file mode 100644
index 4d45fe8bd206..000000000000
--- a/drivers/net/tokenring/olympic.c
+++ /dev/null
@@ -1,1737 +0,0 @@
1/*
2 * olympic.c (c) 1999 Peter De Schrijver All Rights Reserved
3 * 1999/2000 Mike Phillips (mikep@linuxtr.net)
4 *
5 * Linux driver for IBM PCI tokenring cards based on the Pit/Pit-Phy/Olympic
6 * chipset.
7 *
8 * Base Driver Skeleton:
9 * Written 1993-94 by Donald Becker.
10 *
11 * Copyright 1993 United States Government as represented by the
12 * Director, National Security Agency.
13 *
14 * Thanks to Erik De Cock, Adrian Bridgett and Frank Fiene for their
15 * assistance and perserverance with the testing of this driver.
16 *
17 * This software may be used and distributed according to the terms
18 * of the GNU General Public License, incorporated herein by reference.
19 *
20 * 4/27/99 - Alpha Release 0.1.0
21 * First release to the public
22 *
23 * 6/8/99 - Official Release 0.2.0
24 * Merged into the kernel code
25 * 8/18/99 - Updated driver for 2.3.13 kernel to use new pci
26 * resource. Driver also reports the card name returned by
27 * the pci resource.
28 * 1/11/00 - Added spinlocks for smp
29 * 2/23/00 - Updated to dev_kfree_irq
30 * 3/10/00 - Fixed FDX enable which triggered other bugs also
31 * squashed.
32 * 5/20/00 - Changes to handle Olympic on LinuxPPC. Endian changes.
33 * The odd thing about the changes is that the fix for
34 * endian issues with the big-endian data in the arb, asb...
35 * was to always swab() the bytes, no matter what CPU.
36 * That's because the read[wl]() functions always swap the
37 * bytes on the way in on PPC.
38 * Fixing the hardware descriptors was another matter,
39 * because they weren't going through read[wl](), there all
40 * the results had to be in memory in le32 values. kdaaker
41 *
42 * 12/23/00 - Added minimal Cardbus support (Thanks Donald).
43 *
44 * 03/09/01 - Add new pci api, dev_base_lock, general clean up.
45 *
46 * 03/27/01 - Add new dma pci (Thanks to Kyle Lucke) and alloc_trdev
47 * Change proc_fs behaviour, now one entry per adapter.
48 *
49 * 04/09/01 - Couple of bug fixes to the dma unmaps and ejecting the
50 * adapter when live does not take the system down with it.
51 *
52 * 06/02/01 - Clean up, copy skb for small packets
53 *
54 * 06/22/01 - Add EISR error handling routines
55 *
56 * 07/19/01 - Improve bad LAA reporting, strip out freemem
57 * into a separate function, its called from 3
58 * different places now.
59 * 02/09/02 - Replaced sleep_on.
60 * 03/01/02 - Replace access to several registers from 32 bit to
61 * 16 bit. Fixes alignment errors on PPC 64 bit machines.
62 * Thanks to Al Trautman for this one.
63 * 03/10/02 - Fix BUG in arb_cmd. Bug was there all along but was
64 * silently ignored until the error checking code
65 * went into version 1.0.0
66 * 06/04/02 - Add correct start up sequence for the cardbus adapters.
67 * Required for strict compliance with pci power mgmt specs.
68 * To Do:
69 *
70 * Wake on lan
71 *
72 * If Problems do Occur
73 * Most problems can be rectified by either closing and opening the interface
74 * (ifconfig down and up) or rmmod and insmod'ing the driver (a bit difficult
75 * if compiled into the kernel).
76 */
77
78/* Change OLYMPIC_DEBUG to 1 to get verbose, and I mean really verbose, messages */
79
80#define OLYMPIC_DEBUG 0
81
82
83#include <linux/module.h>
84#include <linux/kernel.h>
85#include <linux/errno.h>
86#include <linux/timer.h>
87#include <linux/in.h>
88#include <linux/ioport.h>
89#include <linux/seq_file.h>
90#include <linux/string.h>
91#include <linux/proc_fs.h>
92#include <linux/ptrace.h>
93#include <linux/skbuff.h>
94#include <linux/interrupt.h>
95#include <linux/delay.h>
96#include <linux/netdevice.h>
97#include <linux/trdevice.h>
98#include <linux/stddef.h>
99#include <linux/init.h>
100#include <linux/pci.h>
101#include <linux/spinlock.h>
102#include <linux/bitops.h>
103#include <linux/jiffies.h>
104
105#include <net/checksum.h>
106#include <net/net_namespace.h>
107
108#include <asm/io.h>
109
110#include "olympic.h"
111
112/* I've got to put some intelligence into the version number so that Peter and I know
113 * which version of the code somebody has got.
114 * Version Number = a.b.c.d where a.b.c is the level of code and d is the latest author.
115 * So 0.0.1.pds = Peter, 0.0.1.mlp = Mike
116 *
117 * Official releases will only have an a.b.c version number format.
118 */
119
120static char version[] =
121"Olympic.c v1.0.5 6/04/02 - Peter De Schrijver & Mike Phillips" ;
122
123static char *open_maj_error[] = {"No error", "Lobe Media Test", "Physical Insertion",
124 "Address Verification", "Neighbor Notification (Ring Poll)",
125 "Request Parameters","FDX Registration Request",
126 "FDX Duplicate Address Check", "Station registration Query Wait",
127 "Unknown stage"};
128
129static char *open_min_error[] = {"No error", "Function Failure", "Signal Lost", "Wire Fault",
130 "Ring Speed Mismatch", "Timeout","Ring Failure","Ring Beaconing",
131 "Duplicate Node Address","Request Parameters","Remove Received",
132 "Reserved", "Reserved", "No Monitor Detected for RPL",
133 "Monitor Contention failer for RPL", "FDX Protocol Error"};
134
135/* Module parameters */
136
137MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
138MODULE_DESCRIPTION("Olympic PCI/Cardbus Chipset Driver") ;
139
140/* Ring Speed 0,4,16,100
141 * 0 = Autosense
142 * 4,16 = Selected speed only, no autosense
143 * This allows the card to be the first on the ring
144 * and become the active monitor.
145 * 100 = Nothing at present, 100mbps is autodetected
146 * if FDX is turned on. May be implemented in the future to
147 * fail if 100mpbs is not detected.
148 *
149 * WARNING: Some hubs will allow you to insert
150 * at the wrong speed
151 */
152
153static int ringspeed[OLYMPIC_MAX_ADAPTERS] = {0,} ;
154module_param_array(ringspeed, int, NULL, 0);
155
156/* Packet buffer size */
157
158static int pkt_buf_sz[OLYMPIC_MAX_ADAPTERS] = {0,} ;
159module_param_array(pkt_buf_sz, int, NULL, 0) ;
160
161/* Message Level */
162
163static int message_level[OLYMPIC_MAX_ADAPTERS] = {0,} ;
164module_param_array(message_level, int, NULL, 0) ;
165
166/* Change network_monitor to receive mac frames through the arb channel.
167 * Will also create a /proc/net/olympic_tr%d entry, where %d is the tr
168 * device, i.e. tr0, tr1 etc.
169 * Intended to be used to create a ring-error reporting network module
170 * i.e. it will give you the source address of beaconers on the ring
171 */
172static int network_monitor[OLYMPIC_MAX_ADAPTERS] = {0,};
173module_param_array(network_monitor, int, NULL, 0);
174
175static DEFINE_PCI_DEVICE_TABLE(olympic_pci_tbl) = {
176 {PCI_VENDOR_ID_IBM,PCI_DEVICE_ID_IBM_TR_WAKE,PCI_ANY_ID,PCI_ANY_ID,},
177 { } /* Terminating Entry */
178};
179MODULE_DEVICE_TABLE(pci,olympic_pci_tbl) ;
180
181
182static int olympic_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
183static int olympic_init(struct net_device *dev);
184static int olympic_open(struct net_device *dev);
185static netdev_tx_t olympic_xmit(struct sk_buff *skb,
186 struct net_device *dev);
187static int olympic_close(struct net_device *dev);
188static void olympic_set_rx_mode(struct net_device *dev);
189static void olympic_freemem(struct net_device *dev) ;
190static irqreturn_t olympic_interrupt(int irq, void *dev_id);
191static int olympic_set_mac_address(struct net_device *dev, void *addr) ;
192static void olympic_arb_cmd(struct net_device *dev);
193static int olympic_change_mtu(struct net_device *dev, int mtu);
194static void olympic_srb_bh(struct net_device *dev) ;
195static void olympic_asb_bh(struct net_device *dev) ;
196static const struct file_operations olympic_proc_ops;
197
198static const struct net_device_ops olympic_netdev_ops = {
199 .ndo_open = olympic_open,
200 .ndo_stop = olympic_close,
201 .ndo_start_xmit = olympic_xmit,
202 .ndo_change_mtu = olympic_change_mtu,
203 .ndo_set_rx_mode = olympic_set_rx_mode,
204 .ndo_set_mac_address = olympic_set_mac_address,
205};
206
207static int __devinit olympic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
208{
209 struct net_device *dev ;
210 struct olympic_private *olympic_priv;
211 static int card_no = -1 ;
212 int i ;
213
214 card_no++ ;
215
216 if ((i = pci_enable_device(pdev))) {
217 return i ;
218 }
219
220 pci_set_master(pdev);
221
222 if ((i = pci_request_regions(pdev,"olympic"))) {
223 goto op_disable_dev;
224 }
225
226 dev = alloc_trdev(sizeof(struct olympic_private)) ;
227 if (!dev) {
228 i = -ENOMEM;
229 goto op_release_dev;
230 }
231
232 olympic_priv = netdev_priv(dev) ;
233
234 spin_lock_init(&olympic_priv->olympic_lock) ;
235
236 init_waitqueue_head(&olympic_priv->srb_wait);
237 init_waitqueue_head(&olympic_priv->trb_wait);
238#if OLYMPIC_DEBUG
239 printk(KERN_INFO "pci_device: %p, dev:%p, dev->priv: %p\n", pdev, dev, netdev_priv(dev));
240#endif
241 dev->irq=pdev->irq;
242 dev->base_addr=pci_resource_start(pdev, 0);
243 olympic_priv->olympic_card_name = pci_name(pdev);
244 olympic_priv->pdev = pdev;
245 olympic_priv->olympic_mmio = ioremap(pci_resource_start(pdev,1),256);
246 olympic_priv->olympic_lap = ioremap(pci_resource_start(pdev,2),2048);
247 if (!olympic_priv->olympic_mmio || !olympic_priv->olympic_lap) {
248 goto op_free_iomap;
249 }
250
251 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
252 olympic_priv->pkt_buf_sz = PKT_BUF_SZ ;
253 else
254 olympic_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
255
256 dev->mtu = olympic_priv->pkt_buf_sz - TR_HLEN ;
257 olympic_priv->olympic_ring_speed = ringspeed[card_no] ;
258 olympic_priv->olympic_message_level = message_level[card_no] ;
259 olympic_priv->olympic_network_monitor = network_monitor[card_no];
260
261 if ((i = olympic_init(dev))) {
262 goto op_free_iomap;
263 }
264
265 dev->netdev_ops = &olympic_netdev_ops;
266 SET_NETDEV_DEV(dev, &pdev->dev);
267
268 pci_set_drvdata(pdev,dev) ;
269 register_netdev(dev) ;
270 printk("Olympic: %s registered as: %s\n",olympic_priv->olympic_card_name,dev->name);
271 if (olympic_priv->olympic_network_monitor) { /* Must go after register_netdev as we need the device name */
272 char proc_name[20] ;
273 strcpy(proc_name,"olympic_") ;
274 strcat(proc_name,dev->name) ;
275 proc_create_data(proc_name, 0, init_net.proc_net, &olympic_proc_ops, dev);
276 printk("Olympic: Network Monitor information: /proc/%s\n",proc_name);
277 }
278 return 0 ;
279
280op_free_iomap:
281 if (olympic_priv->olympic_mmio)
282 iounmap(olympic_priv->olympic_mmio);
283 if (olympic_priv->olympic_lap)
284 iounmap(olympic_priv->olympic_lap);
285
286 free_netdev(dev);
287op_release_dev:
288 pci_release_regions(pdev);
289
290op_disable_dev:
291 pci_disable_device(pdev);
292 return i;
293}
294
295static int olympic_init(struct net_device *dev)
296{
297 struct olympic_private *olympic_priv;
298 u8 __iomem *olympic_mmio, *init_srb,*adapter_addr;
299 unsigned long t;
300 unsigned int uaa_addr;
301
302 olympic_priv=netdev_priv(dev);
303 olympic_mmio=olympic_priv->olympic_mmio;
304
305 printk("%s\n", version);
306 printk("%s. I/O at %hx, MMIO at %p, LAP at %p, using irq %d\n", olympic_priv->olympic_card_name, (unsigned int) dev->base_addr,olympic_priv->olympic_mmio, olympic_priv->olympic_lap, dev->irq);
307
308 writel(readl(olympic_mmio+BCTL) | BCTL_SOFTRESET,olympic_mmio+BCTL);
309 t=jiffies;
310 while((readl(olympic_mmio+BCTL)) & BCTL_SOFTRESET) {
311 schedule();
312 if(time_after(jiffies, t + 40*HZ)) {
313 printk(KERN_ERR "IBM PCI tokenring card not responding.\n");
314 return -ENODEV;
315 }
316 }
317
318
319 /* Needed for cardbus */
320 if(!(readl(olympic_mmio+BCTL) & BCTL_MODE_INDICATOR)) {
321 writel(readl(olympic_priv->olympic_mmio+FERMASK)|FERMASK_INT_BIT, olympic_mmio+FERMASK);
322 }
323
324#if OLYMPIC_DEBUG
325 printk("BCTL: %x\n",readl(olympic_mmio+BCTL));
326 printk("GPR: %x\n",readw(olympic_mmio+GPR));
327 printk("SISRMASK: %x\n",readl(olympic_mmio+SISR_MASK));
328#endif
329 /* Aaaahhh, You have got to be real careful setting GPR, the card
330 holds the previous values from flash memory, including autosense
331 and ring speed */
332
333 writel(readl(olympic_mmio+BCTL)|BCTL_MIMREB,olympic_mmio+BCTL);
334
335 if (olympic_priv->olympic_ring_speed == 0) { /* Autosense */
336 writew(readw(olympic_mmio+GPR)|GPR_AUTOSENSE,olympic_mmio+GPR);
337 if (olympic_priv->olympic_message_level)
338 printk(KERN_INFO "%s: Ringspeed autosense mode on\n",olympic_priv->olympic_card_name);
339 } else if (olympic_priv->olympic_ring_speed == 16) {
340 if (olympic_priv->olympic_message_level)
341 printk(KERN_INFO "%s: Trying to open at 16 Mbps as requested\n", olympic_priv->olympic_card_name);
342 writew(GPR_16MBPS, olympic_mmio+GPR);
343 } else if (olympic_priv->olympic_ring_speed == 4) {
344 if (olympic_priv->olympic_message_level)
345 printk(KERN_INFO "%s: Trying to open at 4 Mbps as requested\n", olympic_priv->olympic_card_name) ;
346 writew(0, olympic_mmio+GPR);
347 }
348
349 writew(readw(olympic_mmio+GPR)|GPR_NEPTUNE_BF,olympic_mmio+GPR);
350
351#if OLYMPIC_DEBUG
352 printk("GPR = %x\n",readw(olympic_mmio + GPR) ) ;
353#endif
354 /* Solo has been paused to meet the Cardbus power
355 * specs if the adapter is cardbus. Check to
356 * see its been paused and then restart solo. The
357 * adapter should set the pause bit within 1 second.
358 */
359
360 if(!(readl(olympic_mmio+BCTL) & BCTL_MODE_INDICATOR)) {
361 t=jiffies;
362 while (!(readl(olympic_mmio+CLKCTL) & CLKCTL_PAUSE)) {
363 schedule() ;
364 if(time_after(jiffies, t + 2*HZ)) {
365 printk(KERN_ERR "IBM Cardbus tokenring adapter not responsing.\n") ;
366 return -ENODEV;
367 }
368 }
369 writel(readl(olympic_mmio+CLKCTL) & ~CLKCTL_PAUSE, olympic_mmio+CLKCTL) ;
370 }
371
372 /* start solo init */
373 writel((1<<15),olympic_mmio+SISR_MASK_SUM);
374
375 t=jiffies;
376 while(!((readl(olympic_mmio+SISR_RR)) & SISR_SRB_REPLY)) {
377 schedule();
378 if(time_after(jiffies, t + 15*HZ)) {
379 printk(KERN_ERR "IBM PCI tokenring card not responding.\n");
380 return -ENODEV;
381 }
382 }
383
384 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
385
386#if OLYMPIC_DEBUG
387 printk("LAPWWO: %x, LAPA: %x\n",readl(olympic_mmio+LAPWWO), readl(olympic_mmio+LAPA));
388#endif
389
390 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
391
392#if OLYMPIC_DEBUG
393{
394 int i;
395 printk("init_srb(%p): ",init_srb);
396 for(i=0;i<20;i++)
397 printk("%x ",readb(init_srb+i));
398 printk("\n");
399}
400#endif
401 if(readw(init_srb+6)) {
402 printk(KERN_INFO "tokenring card initialization failed. errorcode : %x\n",readw(init_srb+6));
403 return -ENODEV;
404 }
405
406 if (olympic_priv->olympic_message_level) {
407 if ( readb(init_srb +2) & 0x40) {
408 printk(KERN_INFO "Olympic: Adapter is FDX capable.\n") ;
409 } else {
410 printk(KERN_INFO "Olympic: Adapter cannot do FDX.\n");
411 }
412 }
413
414 uaa_addr=swab16(readw(init_srb+8));
415
416#if OLYMPIC_DEBUG
417 printk("UAA resides at %x\n",uaa_addr);
418#endif
419
420 writel(uaa_addr,olympic_mmio+LAPA);
421 adapter_addr=olympic_priv->olympic_lap + (uaa_addr & (~0xf800));
422
423 memcpy_fromio(&dev->dev_addr[0], adapter_addr,6);
424
425#if OLYMPIC_DEBUG
426 printk("adapter address: %pM\n", dev->dev_addr);
427#endif
428
429 olympic_priv->olympic_addr_table_addr = swab16(readw(init_srb + 12));
430 olympic_priv->olympic_parms_addr = swab16(readw(init_srb + 14));
431
432 return 0;
433
434}
435
436static int olympic_open(struct net_device *dev)
437{
438 struct olympic_private *olympic_priv=netdev_priv(dev);
439 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio,*init_srb;
440 unsigned long flags, t;
441 int i, open_finished = 1 ;
442 u8 resp, err;
443
444 DECLARE_WAITQUEUE(wait,current) ;
445
446 olympic_init(dev);
447
448 if (request_irq(dev->irq, olympic_interrupt, IRQF_SHARED , "olympic",
449 dev))
450 return -EAGAIN;
451
452#if OLYMPIC_DEBUG
453 printk("BMCTL: %x\n",readl(olympic_mmio+BMCTL_SUM));
454 printk("pending ints: %x\n",readl(olympic_mmio+SISR_RR));
455#endif
456
457 writel(SISR_MI,olympic_mmio+SISR_MASK_SUM);
458
459 writel(SISR_MI | SISR_SRB_REPLY, olympic_mmio+SISR_MASK); /* more ints later, doesn't stop arb cmd interrupt */
460
461 writel(LISR_LIE,olympic_mmio+LISR); /* more ints later */
462
463 /* adapter is closed, so SRB is pointed to by LAPWWO */
464
465 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
466 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
467
468#if OLYMPIC_DEBUG
469 printk("LAPWWO: %x, LAPA: %x\n",readw(olympic_mmio+LAPWWO), readl(olympic_mmio+LAPA));
470 printk("SISR Mask = %04x\n", readl(olympic_mmio+SISR_MASK));
471 printk("Before the open command\n");
472#endif
473 do {
474 memset_io(init_srb,0,SRB_COMMAND_SIZE);
475
476 writeb(SRB_OPEN_ADAPTER,init_srb) ; /* open */
477 writeb(OLYMPIC_CLEAR_RET_CODE,init_srb+2);
478
479 /* If Network Monitor, instruct card to copy MAC frames through the ARB */
480 if (olympic_priv->olympic_network_monitor)
481 writew(swab16(OPEN_ADAPTER_ENABLE_FDX | OPEN_ADAPTER_PASS_ADC_MAC | OPEN_ADAPTER_PASS_ATT_MAC | OPEN_ADAPTER_PASS_BEACON), init_srb+8);
482 else
483 writew(swab16(OPEN_ADAPTER_ENABLE_FDX), init_srb+8);
484
485 /* Test OR of first 3 bytes as its totally possible for
486 * someone to set the first 2 bytes to be zero, although this
487 * is an error, the first byte must have bit 6 set to 1 */
488
489 if (olympic_priv->olympic_laa[0] | olympic_priv->olympic_laa[1] | olympic_priv->olympic_laa[2]) {
490 writeb(olympic_priv->olympic_laa[0],init_srb+12);
491 writeb(olympic_priv->olympic_laa[1],init_srb+13);
492 writeb(olympic_priv->olympic_laa[2],init_srb+14);
493 writeb(olympic_priv->olympic_laa[3],init_srb+15);
494 writeb(olympic_priv->olympic_laa[4],init_srb+16);
495 writeb(olympic_priv->olympic_laa[5],init_srb+17);
496 memcpy(dev->dev_addr,olympic_priv->olympic_laa,dev->addr_len) ;
497 }
498 writeb(1,init_srb+30);
499
500 spin_lock_irqsave(&olympic_priv->olympic_lock,flags);
501 olympic_priv->srb_queued=1;
502
503 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
504 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
505
506 t = jiffies ;
507
508 add_wait_queue(&olympic_priv->srb_wait,&wait) ;
509 set_current_state(TASK_INTERRUPTIBLE) ;
510
511 while(olympic_priv->srb_queued) {
512 schedule() ;
513 if(signal_pending(current)) {
514 printk(KERN_WARNING "%s: Signal received in open.\n",
515 dev->name);
516 printk(KERN_WARNING "SISR=%x LISR=%x\n",
517 readl(olympic_mmio+SISR),
518 readl(olympic_mmio+LISR));
519 olympic_priv->srb_queued=0;
520 break;
521 }
522 if (time_after(jiffies, t + 10*HZ)) {
523 printk(KERN_WARNING "%s: SRB timed out.\n",dev->name);
524 olympic_priv->srb_queued=0;
525 break ;
526 }
527 set_current_state(TASK_INTERRUPTIBLE) ;
528 }
529 remove_wait_queue(&olympic_priv->srb_wait,&wait) ;
530 set_current_state(TASK_RUNNING) ;
531 olympic_priv->srb_queued = 0 ;
532#if OLYMPIC_DEBUG
533 printk("init_srb(%p): ",init_srb);
534 for(i=0;i<20;i++)
535 printk("%02x ",readb(init_srb+i));
536 printk("\n");
537#endif
538
539 /* If we get the same return response as we set, the interrupt wasn't raised and the open
540 * timed out.
541 */
542
543 switch (resp = readb(init_srb+2)) {
544 case OLYMPIC_CLEAR_RET_CODE:
545 printk(KERN_WARNING "%s: Adapter Open time out or error.\n", dev->name) ;
546 goto out;
547 case 0:
548 open_finished = 1;
549 break;
550 case 0x07:
551 if (!olympic_priv->olympic_ring_speed && open_finished) { /* Autosense , first time around */
552 printk(KERN_WARNING "%s: Retrying at different ring speed\n", dev->name);
553 open_finished = 0 ;
554 continue;
555 }
556
557 err = readb(init_srb+7);
558
559 if (!olympic_priv->olympic_ring_speed && ((err & 0x0f) == 0x0d)) {
560 printk(KERN_WARNING "%s: Tried to autosense ring speed with no monitors present\n",dev->name);
561 printk(KERN_WARNING "%s: Please try again with a specified ring speed\n",dev->name);
562 } else {
563 printk(KERN_WARNING "%s: %s - %s\n", dev->name,
564 open_maj_error[(err & 0xf0) >> 4],
565 open_min_error[(err & 0x0f)]);
566 }
567 goto out;
568
569 case 0x32:
570 printk(KERN_WARNING "%s: Invalid LAA: %pM\n",
571 dev->name, olympic_priv->olympic_laa);
572 goto out;
573
574 default:
575 printk(KERN_WARNING "%s: Bad OPEN response: %x\n", dev->name, resp);
576 goto out;
577
578 }
579 } while (!(open_finished)) ; /* Will only loop if ring speed mismatch re-open attempted && autosense is on */
580
581 if (readb(init_srb+18) & (1<<3))
582 if (olympic_priv->olympic_message_level)
583 printk(KERN_INFO "%s: Opened in FDX Mode\n",dev->name);
584
585 if (readb(init_srb+18) & (1<<1))
586 olympic_priv->olympic_ring_speed = 100 ;
587 else if (readb(init_srb+18) & 1)
588 olympic_priv->olympic_ring_speed = 16 ;
589 else
590 olympic_priv->olympic_ring_speed = 4 ;
591
592 if (olympic_priv->olympic_message_level)
593 printk(KERN_INFO "%s: Opened in %d Mbps mode\n",dev->name, olympic_priv->olympic_ring_speed);
594
595 olympic_priv->asb = swab16(readw(init_srb+8));
596 olympic_priv->srb = swab16(readw(init_srb+10));
597 olympic_priv->arb = swab16(readw(init_srb+12));
598 olympic_priv->trb = swab16(readw(init_srb+16));
599
600 olympic_priv->olympic_receive_options = 0x01 ;
601 olympic_priv->olympic_copy_all_options = 0 ;
602
603 /* setup rx ring */
604
605 writel((3<<16),olympic_mmio+BMCTL_RWM); /* Ensure end of frame generated interrupts */
606
607 writel(BMCTL_RX_DIS|3,olympic_mmio+BMCTL_RWM); /* Yes, this the enables RX channel */
608
609 for(i=0;i<OLYMPIC_RX_RING_SIZE;i++) {
610
611 struct sk_buff *skb;
612
613 skb=dev_alloc_skb(olympic_priv->pkt_buf_sz);
614 if(skb == NULL)
615 break;
616
617 skb->dev = dev;
618
619 olympic_priv->olympic_rx_ring[i].buffer = cpu_to_le32(pci_map_single(olympic_priv->pdev,
620 skb->data,olympic_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)) ;
621 olympic_priv->olympic_rx_ring[i].res_length = cpu_to_le32(olympic_priv->pkt_buf_sz);
622 olympic_priv->rx_ring_skb[i]=skb;
623 }
624
625 if (i==0) {
626 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n",dev->name);
627 goto out;
628 }
629
630 olympic_priv->rx_ring_dma_addr = pci_map_single(olympic_priv->pdev,olympic_priv->olympic_rx_ring,
631 sizeof(struct olympic_rx_desc) * OLYMPIC_RX_RING_SIZE, PCI_DMA_TODEVICE);
632 writel(olympic_priv->rx_ring_dma_addr, olympic_mmio+RXDESCQ);
633 writel(olympic_priv->rx_ring_dma_addr, olympic_mmio+RXCDA);
634 writew(i, olympic_mmio+RXDESCQCNT);
635
636 olympic_priv->rx_status_ring_dma_addr = pci_map_single(olympic_priv->pdev, olympic_priv->olympic_rx_status_ring,
637 sizeof(struct olympic_rx_status) * OLYMPIC_RX_RING_SIZE, PCI_DMA_FROMDEVICE);
638 writel(olympic_priv->rx_status_ring_dma_addr, olympic_mmio+RXSTATQ);
639 writel(olympic_priv->rx_status_ring_dma_addr, olympic_mmio+RXCSA);
640
641 olympic_priv->rx_ring_last_received = OLYMPIC_RX_RING_SIZE - 1; /* last processed rx status */
642 olympic_priv->rx_status_last_received = OLYMPIC_RX_RING_SIZE - 1;
643
644 writew(i, olympic_mmio+RXSTATQCNT);
645
646#if OLYMPIC_DEBUG
647 printk("# of rx buffers: %d, RXENQ: %x\n",i, readw(olympic_mmio+RXENQ));
648 printk("RXCSA: %x, rx_status_ring[0]: %p\n",readl(olympic_mmio+RXCSA),&olympic_priv->olympic_rx_status_ring[0]);
649 printk(" stat_ring[1]: %p, stat_ring[2]: %p, stat_ring[3]: %p\n", &(olympic_priv->olympic_rx_status_ring[1]), &(olympic_priv->olympic_rx_status_ring[2]), &(olympic_priv->olympic_rx_status_ring[3]) );
650 printk(" stat_ring[4]: %p, stat_ring[5]: %p, stat_ring[6]: %p\n", &(olympic_priv->olympic_rx_status_ring[4]), &(olympic_priv->olympic_rx_status_ring[5]), &(olympic_priv->olympic_rx_status_ring[6]) );
651 printk(" stat_ring[7]: %p\n", &(olympic_priv->olympic_rx_status_ring[7]) );
652
653 printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
654 printk("Rx_ring_dma_addr = %08x, rx_status_dma_addr = %08x\n",
655 olympic_priv->rx_ring_dma_addr,olympic_priv->rx_status_ring_dma_addr) ;
656#endif
657
658 writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | i,olympic_mmio+RXENQ);
659
660#if OLYMPIC_DEBUG
661 printk("# of rx buffers: %d, RXENQ: %x\n",i, readw(olympic_mmio+RXENQ));
662 printk("RXCSA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCSA),&olympic_priv->olympic_rx_status_ring[0]);
663 printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
664#endif
665
666 writel(SISR_RX_STATUS | SISR_RX_NOBUF,olympic_mmio+SISR_MASK_SUM);
667
668 /* setup tx ring */
669
670 writel(BMCTL_TX1_DIS,olympic_mmio+BMCTL_RWM); /* Yes, this enables TX channel 1 */
671 for(i=0;i<OLYMPIC_TX_RING_SIZE;i++)
672 olympic_priv->olympic_tx_ring[i].buffer=cpu_to_le32(0xdeadbeef);
673
674 olympic_priv->free_tx_ring_entries=OLYMPIC_TX_RING_SIZE;
675 olympic_priv->tx_ring_dma_addr = pci_map_single(olympic_priv->pdev,olympic_priv->olympic_tx_ring,
676 sizeof(struct olympic_tx_desc) * OLYMPIC_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
677 writel(olympic_priv->tx_ring_dma_addr, olympic_mmio+TXDESCQ_1);
678 writel(olympic_priv->tx_ring_dma_addr, olympic_mmio+TXCDA_1);
679 writew(OLYMPIC_TX_RING_SIZE, olympic_mmio+TXDESCQCNT_1);
680
681 olympic_priv->tx_status_ring_dma_addr = pci_map_single(olympic_priv->pdev, olympic_priv->olympic_tx_status_ring,
682 sizeof(struct olympic_tx_status) * OLYMPIC_TX_RING_SIZE, PCI_DMA_FROMDEVICE);
683 writel(olympic_priv->tx_status_ring_dma_addr,olympic_mmio+TXSTATQ_1);
684 writel(olympic_priv->tx_status_ring_dma_addr,olympic_mmio+TXCSA_1);
685 writew(OLYMPIC_TX_RING_SIZE,olympic_mmio+TXSTATQCNT_1);
686
687 olympic_priv->tx_ring_free=0; /* next entry in tx ring to use */
688 olympic_priv->tx_ring_last_status=OLYMPIC_TX_RING_SIZE-1; /* last processed tx status */
689
690 writel(0xffffffff, olympic_mmio+EISR_RWM) ; /* clean the eisr */
691 writel(0,olympic_mmio+EISR) ;
692 writel(EISR_MASK_OPTIONS,olympic_mmio+EISR_MASK) ; /* enables most of the TX error interrupts */
693 writel(SISR_TX1_EOF | SISR_ADAPTER_CHECK | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_ASB_FREE | SISR_ERR,olympic_mmio+SISR_MASK_SUM);
694
695#if OLYMPIC_DEBUG
696 printk("BMCTL: %x\n",readl(olympic_mmio+BMCTL_SUM));
697 printk("SISR MASK: %x\n",readl(olympic_mmio+SISR_MASK));
698#endif
699
700 if (olympic_priv->olympic_network_monitor) {
701 u8 __iomem *oat;
702 u8 __iomem *opt;
703 u8 addr[6];
704 oat = (olympic_priv->olympic_lap + olympic_priv->olympic_addr_table_addr);
705 opt = (olympic_priv->olympic_lap + olympic_priv->olympic_parms_addr);
706
707 for (i = 0; i < 6; i++)
708 addr[i] = readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+i);
709 printk("%s: Node Address: %pM\n", dev->name, addr);
710 printk("%s: Functional Address: %02x:%02x:%02x:%02x\n",dev->name,
711 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)),
712 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+1),
713 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+2),
714 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+3));
715
716 for (i = 0; i < 6; i++)
717 addr[i] = readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+i);
718 printk("%s: NAUN Address: %pM\n", dev->name, addr);
719 }
720
721 netif_start_queue(dev);
722 return 0;
723
724out:
725 free_irq(dev->irq, dev);
726 return -EIO;
727}
728
729/*
730 * When we enter the rx routine we do not know how many frames have been
731 * queued on the rx channel. Therefore we start at the next rx status
732 * position and travel around the receive ring until we have completed
733 * all the frames.
734 *
735 * This means that we may process the frame before we receive the end
736 * of frame interrupt. This is why we always test the status instead
737 * of blindly processing the next frame.
738 *
739 * We also remove the last 4 bytes from the packet as well, these are
740 * just token ring trailer info and upset protocols that don't check
741 * their own length, i.e. SNA.
742 *
743 */
744static void olympic_rx(struct net_device *dev)
745{
746 struct olympic_private *olympic_priv=netdev_priv(dev);
747 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
748 struct olympic_rx_status *rx_status;
749 struct olympic_rx_desc *rx_desc ;
750 int rx_ring_last_received,length, buffer_cnt, cpy_length, frag_len;
751 struct sk_buff *skb, *skb2;
752 int i;
753
754 rx_status=&(olympic_priv->olympic_rx_status_ring[(olympic_priv->rx_status_last_received + 1) & (OLYMPIC_RX_RING_SIZE - 1)]) ;
755
756 while (rx_status->status_buffercnt) {
757 u32 l_status_buffercnt;
758
759 olympic_priv->rx_status_last_received++ ;
760 olympic_priv->rx_status_last_received &= (OLYMPIC_RX_RING_SIZE -1);
761#if OLYMPIC_DEBUG
762 printk("rx status: %x rx len: %x\n", le32_to_cpu(rx_status->status_buffercnt), le32_to_cpu(rx_status->fragmentcnt_framelen));
763#endif
764 length = le32_to_cpu(rx_status->fragmentcnt_framelen) & 0xffff;
765 buffer_cnt = le32_to_cpu(rx_status->status_buffercnt) & 0xffff;
766 i = buffer_cnt ; /* Need buffer_cnt later for rxenq update */
767 frag_len = le32_to_cpu(rx_status->fragmentcnt_framelen) >> 16;
768
769#if OLYMPIC_DEBUG
770 printk("length: %x, frag_len: %x, buffer_cnt: %x\n", length, frag_len, buffer_cnt);
771#endif
772 l_status_buffercnt = le32_to_cpu(rx_status->status_buffercnt);
773 if(l_status_buffercnt & 0xC0000000) {
774 if (l_status_buffercnt & 0x3B000000) {
775 if (olympic_priv->olympic_message_level) {
776 if (l_status_buffercnt & (1<<29)) /* Rx Frame Truncated */
777 printk(KERN_WARNING "%s: Rx Frame Truncated\n",dev->name);
778 if (l_status_buffercnt & (1<<28)) /*Rx receive overrun */
779 printk(KERN_WARNING "%s: Rx Frame Receive overrun\n",dev->name);
780 if (l_status_buffercnt & (1<<27)) /* No receive buffers */
781 printk(KERN_WARNING "%s: No receive buffers\n",dev->name);
782 if (l_status_buffercnt & (1<<25)) /* Receive frame error detect */
783 printk(KERN_WARNING "%s: Receive frame error detect\n",dev->name);
784 if (l_status_buffercnt & (1<<24)) /* Received Error Detect */
785 printk(KERN_WARNING "%s: Received Error Detect\n",dev->name);
786 }
787 olympic_priv->rx_ring_last_received += i ;
788 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1) ;
789 dev->stats.rx_errors++;
790 } else {
791
792 if (buffer_cnt == 1) {
793 skb = dev_alloc_skb(max_t(int, olympic_priv->pkt_buf_sz,length)) ;
794 } else {
795 skb = dev_alloc_skb(length) ;
796 }
797
798 if (skb == NULL) {
799 printk(KERN_WARNING "%s: Not enough memory to copy packet to upper layers.\n",dev->name) ;
800 dev->stats.rx_dropped++;
801 /* Update counters even though we don't transfer the frame */
802 olympic_priv->rx_ring_last_received += i ;
803 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1) ;
804 } else {
805 /* Optimise based upon number of buffers used.
806 If only one buffer is used we can simply swap the buffers around.
807 If more than one then we must use the new buffer and copy the information
808 first. Ideally all frames would be in a single buffer, this can be tuned by
809 altering the buffer size. If the length of the packet is less than
810 1500 bytes we're going to copy it over anyway to stop packets getting
811 dropped from sockets with buffers smaller than our pkt_buf_sz. */
812
813 if (buffer_cnt==1) {
814 olympic_priv->rx_ring_last_received++ ;
815 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1);
816 rx_ring_last_received = olympic_priv->rx_ring_last_received ;
817 if (length > 1500) {
818 skb2=olympic_priv->rx_ring_skb[rx_ring_last_received] ;
819 /* unmap buffer */
820 pci_unmap_single(olympic_priv->pdev,
821 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
822 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
823 skb_put(skb2,length-4);
824 skb2->protocol = tr_type_trans(skb2,dev);
825 olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer =
826 cpu_to_le32(pci_map_single(olympic_priv->pdev, skb->data,
827 olympic_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
828 olympic_priv->olympic_rx_ring[rx_ring_last_received].res_length =
829 cpu_to_le32(olympic_priv->pkt_buf_sz);
830 olympic_priv->rx_ring_skb[rx_ring_last_received] = skb ;
831 netif_rx(skb2) ;
832 } else {
833 pci_dma_sync_single_for_cpu(olympic_priv->pdev,
834 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
835 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
836 skb_copy_from_linear_data(olympic_priv->rx_ring_skb[rx_ring_last_received],
837 skb_put(skb,length - 4),
838 length - 4);
839 pci_dma_sync_single_for_device(olympic_priv->pdev,
840 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
841 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
842 skb->protocol = tr_type_trans(skb,dev) ;
843 netif_rx(skb) ;
844 }
845 } else {
846 do { /* Walk the buffers */
847 olympic_priv->rx_ring_last_received++ ;
848 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1);
849 rx_ring_last_received = olympic_priv->rx_ring_last_received ;
850 pci_dma_sync_single_for_cpu(olympic_priv->pdev,
851 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
852 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
853 rx_desc = &(olympic_priv->olympic_rx_ring[rx_ring_last_received]);
854 cpy_length = (i == 1 ? frag_len : le32_to_cpu(rx_desc->res_length));
855 skb_copy_from_linear_data(olympic_priv->rx_ring_skb[rx_ring_last_received],
856 skb_put(skb, cpy_length),
857 cpy_length);
858 pci_dma_sync_single_for_device(olympic_priv->pdev,
859 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
860 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
861 } while (--i) ;
862 skb_trim(skb,skb->len-4) ;
863 skb->protocol = tr_type_trans(skb,dev);
864 netif_rx(skb) ;
865 }
866 dev->stats.rx_packets++ ;
867 dev->stats.rx_bytes += length ;
868 } /* if skb == null */
869 } /* If status & 0x3b */
870
871 } else { /*if buffercnt & 0xC */
872 olympic_priv->rx_ring_last_received += i ;
873 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE - 1) ;
874 }
875
876 rx_status->fragmentcnt_framelen = 0 ;
877 rx_status->status_buffercnt = 0 ;
878 rx_status = &(olympic_priv->olympic_rx_status_ring[(olympic_priv->rx_status_last_received+1) & (OLYMPIC_RX_RING_SIZE -1) ]);
879
880 writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | buffer_cnt , olympic_mmio+RXENQ);
881 } /* while */
882
883}
884
885static void olympic_freemem(struct net_device *dev)
886{
887 struct olympic_private *olympic_priv=netdev_priv(dev);
888 int i;
889
890 for(i=0;i<OLYMPIC_RX_RING_SIZE;i++) {
891 if (olympic_priv->rx_ring_skb[olympic_priv->rx_status_last_received] != NULL) {
892 dev_kfree_skb_irq(olympic_priv->rx_ring_skb[olympic_priv->rx_status_last_received]);
893 olympic_priv->rx_ring_skb[olympic_priv->rx_status_last_received] = NULL;
894 }
895 if (olympic_priv->olympic_rx_ring[olympic_priv->rx_status_last_received].buffer != cpu_to_le32(0xdeadbeef)) {
896 pci_unmap_single(olympic_priv->pdev,
897 le32_to_cpu(olympic_priv->olympic_rx_ring[olympic_priv->rx_status_last_received].buffer),
898 olympic_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
899 }
900 olympic_priv->rx_status_last_received++;
901 olympic_priv->rx_status_last_received&=OLYMPIC_RX_RING_SIZE-1;
902 }
903 /* unmap rings */
904 pci_unmap_single(olympic_priv->pdev, olympic_priv->rx_status_ring_dma_addr,
905 sizeof(struct olympic_rx_status) * OLYMPIC_RX_RING_SIZE, PCI_DMA_FROMDEVICE);
906 pci_unmap_single(olympic_priv->pdev, olympic_priv->rx_ring_dma_addr,
907 sizeof(struct olympic_rx_desc) * OLYMPIC_RX_RING_SIZE, PCI_DMA_TODEVICE);
908
909 pci_unmap_single(olympic_priv->pdev, olympic_priv->tx_status_ring_dma_addr,
910 sizeof(struct olympic_tx_status) * OLYMPIC_TX_RING_SIZE, PCI_DMA_FROMDEVICE);
911 pci_unmap_single(olympic_priv->pdev, olympic_priv->tx_ring_dma_addr,
912 sizeof(struct olympic_tx_desc) * OLYMPIC_TX_RING_SIZE, PCI_DMA_TODEVICE);
913
914 return ;
915}
916
917static irqreturn_t olympic_interrupt(int irq, void *dev_id)
918{
919 struct net_device *dev= (struct net_device *)dev_id;
920 struct olympic_private *olympic_priv=netdev_priv(dev);
921 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
922 u32 sisr;
923 u8 __iomem *adapter_check_area ;
924
925 /*
926 * Read sisr but don't reset it yet.
927 * The indication bit may have been set but the interrupt latch
928 * bit may not be set, so we'd lose the interrupt later.
929 */
930 sisr=readl(olympic_mmio+SISR) ;
931 if (!(sisr & SISR_MI)) /* Interrupt isn't for us */
932 return IRQ_NONE;
933 sisr=readl(olympic_mmio+SISR_RR) ; /* Read & Reset sisr */
934
935 spin_lock(&olympic_priv->olympic_lock);
936
937 /* Hotswap gives us this on removal */
938 if (sisr == 0xffffffff) {
939 printk(KERN_WARNING "%s: Hotswap adapter removal.\n",dev->name) ;
940 spin_unlock(&olympic_priv->olympic_lock) ;
941 return IRQ_NONE;
942 }
943
944 if (sisr & (SISR_SRB_REPLY | SISR_TX1_EOF | SISR_RX_STATUS | SISR_ADAPTER_CHECK |
945 SISR_ASB_FREE | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_RX_NOBUF | SISR_ERR)) {
946
947 /* If we ever get this the adapter is seriously dead. Only a reset is going to
948 * bring it back to life. We're talking pci bus errors and such like :( */
949 if((sisr & SISR_ERR) && (readl(olympic_mmio+EISR) & EISR_MASK_OPTIONS)) {
950 printk(KERN_ERR "Olympic: EISR Error, EISR=%08x\n",readl(olympic_mmio+EISR)) ;
951 printk(KERN_ERR "The adapter must be reset to clear this condition.\n") ;
952 printk(KERN_ERR "Please report this error to the driver maintainer and/\n") ;
953 printk(KERN_ERR "or the linux-tr mailing list.\n") ;
954 wake_up_interruptible(&olympic_priv->srb_wait);
955 spin_unlock(&olympic_priv->olympic_lock) ;
956 return IRQ_HANDLED;
957 } /* SISR_ERR */
958
959 if(sisr & SISR_SRB_REPLY) {
960 if(olympic_priv->srb_queued==1) {
961 wake_up_interruptible(&olympic_priv->srb_wait);
962 } else if (olympic_priv->srb_queued==2) {
963 olympic_srb_bh(dev) ;
964 }
965 olympic_priv->srb_queued=0;
966 } /* SISR_SRB_REPLY */
967
968 /* We shouldn't ever miss the Tx interrupt, but the you never know, hence the loop to ensure
969 we get all tx completions. */
970 if (sisr & SISR_TX1_EOF) {
971 while(olympic_priv->olympic_tx_status_ring[(olympic_priv->tx_ring_last_status + 1) & (OLYMPIC_TX_RING_SIZE-1)].status) {
972 olympic_priv->tx_ring_last_status++;
973 olympic_priv->tx_ring_last_status &= (OLYMPIC_TX_RING_SIZE-1);
974 olympic_priv->free_tx_ring_entries++;
975 dev->stats.tx_bytes += olympic_priv->tx_ring_skb[olympic_priv->tx_ring_last_status]->len;
976 dev->stats.tx_packets++ ;
977 pci_unmap_single(olympic_priv->pdev,
978 le32_to_cpu(olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_last_status].buffer),
979 olympic_priv->tx_ring_skb[olympic_priv->tx_ring_last_status]->len,PCI_DMA_TODEVICE);
980 dev_kfree_skb_irq(olympic_priv->tx_ring_skb[olympic_priv->tx_ring_last_status]);
981 olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_last_status].buffer=cpu_to_le32(0xdeadbeef);
982 olympic_priv->olympic_tx_status_ring[olympic_priv->tx_ring_last_status].status=0;
983 }
984 netif_wake_queue(dev);
985 } /* SISR_TX1_EOF */
986
987 if (sisr & SISR_RX_STATUS) {
988 olympic_rx(dev);
989 } /* SISR_RX_STATUS */
990
991 if (sisr & SISR_ADAPTER_CHECK) {
992 netif_stop_queue(dev);
993 printk(KERN_WARNING "%s: Adapter Check Interrupt Raised, 8 bytes of information follow:\n", dev->name);
994 writel(readl(olympic_mmio+LAPWWC),olympic_mmio+LAPA);
995 adapter_check_area = olympic_priv->olympic_lap + ((readl(olympic_mmio+LAPWWC)) & (~0xf800)) ;
996 printk(KERN_WARNING "%s: Bytes %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",dev->name, readb(adapter_check_area+0), readb(adapter_check_area+1), readb(adapter_check_area+2), readb(adapter_check_area+3), readb(adapter_check_area+4), readb(adapter_check_area+5), readb(adapter_check_area+6), readb(adapter_check_area+7)) ;
997 spin_unlock(&olympic_priv->olympic_lock) ;
998 return IRQ_HANDLED;
999 } /* SISR_ADAPTER_CHECK */
1000
1001 if (sisr & SISR_ASB_FREE) {
1002 /* Wake up anything that is waiting for the asb response */
1003 if (olympic_priv->asb_queued) {
1004 olympic_asb_bh(dev) ;
1005 }
1006 } /* SISR_ASB_FREE */
1007
1008 if (sisr & SISR_ARB_CMD) {
1009 olympic_arb_cmd(dev) ;
1010 } /* SISR_ARB_CMD */
1011
1012 if (sisr & SISR_TRB_REPLY) {
1013 /* Wake up anything that is waiting for the trb response */
1014 if (olympic_priv->trb_queued) {
1015 wake_up_interruptible(&olympic_priv->trb_wait);
1016 }
1017 olympic_priv->trb_queued = 0 ;
1018 } /* SISR_TRB_REPLY */
1019
1020 if (sisr & SISR_RX_NOBUF) {
1021 /* According to the documentation, we don't have to do anything, but trapping it keeps it out of
1022 /var/log/messages. */
1023 } /* SISR_RX_NOBUF */
1024 } else {
1025 printk(KERN_WARNING "%s: Unexpected interrupt: %x\n",dev->name, sisr);
1026 printk(KERN_WARNING "%s: SISR_MASK: %x\n",dev->name, readl(olympic_mmio+SISR_MASK)) ;
1027 } /* One if the interrupts we want */
1028 writel(SISR_MI,olympic_mmio+SISR_MASK_SUM);
1029
1030 spin_unlock(&olympic_priv->olympic_lock) ;
1031 return IRQ_HANDLED;
1032}
1033
1034static netdev_tx_t olympic_xmit(struct sk_buff *skb,
1035 struct net_device *dev)
1036{
1037 struct olympic_private *olympic_priv=netdev_priv(dev);
1038 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
1039 unsigned long flags ;
1040
1041 spin_lock_irqsave(&olympic_priv->olympic_lock, flags);
1042
1043 netif_stop_queue(dev);
1044
1045 if(olympic_priv->free_tx_ring_entries) {
1046 olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_free].buffer =
1047 cpu_to_le32(pci_map_single(olympic_priv->pdev, skb->data, skb->len,PCI_DMA_TODEVICE));
1048 olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_free].status_length = cpu_to_le32(skb->len | (0x80000000));
1049 olympic_priv->tx_ring_skb[olympic_priv->tx_ring_free]=skb;
1050 olympic_priv->free_tx_ring_entries--;
1051
1052 olympic_priv->tx_ring_free++;
1053 olympic_priv->tx_ring_free &= (OLYMPIC_TX_RING_SIZE-1);
1054 writew((((readw(olympic_mmio+TXENQ_1)) & 0x8000) ^ 0x8000) | 1,olympic_mmio+TXENQ_1);
1055 netif_wake_queue(dev);
1056 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
1057 return NETDEV_TX_OK;
1058 } else {
1059 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
1060 return NETDEV_TX_BUSY;
1061 }
1062
1063}
1064
1065
1066static int olympic_close(struct net_device *dev)
1067{
1068 struct olympic_private *olympic_priv=netdev_priv(dev);
1069 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio,*srb;
1070 unsigned long t,flags;
1071
1072 DECLARE_WAITQUEUE(wait,current) ;
1073
1074 netif_stop_queue(dev);
1075
1076 writel(olympic_priv->srb,olympic_mmio+LAPA);
1077 srb=olympic_priv->olympic_lap + (olympic_priv->srb & (~0xf800));
1078
1079 writeb(SRB_CLOSE_ADAPTER,srb+0);
1080 writeb(0,srb+1);
1081 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1082
1083 add_wait_queue(&olympic_priv->srb_wait,&wait) ;
1084 set_current_state(TASK_INTERRUPTIBLE) ;
1085
1086 spin_lock_irqsave(&olympic_priv->olympic_lock,flags);
1087 olympic_priv->srb_queued=1;
1088
1089 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1090 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
1091
1092 while(olympic_priv->srb_queued) {
1093
1094 t = schedule_timeout_interruptible(60*HZ);
1095
1096 if(signal_pending(current)) {
1097 printk(KERN_WARNING "%s: SRB timed out.\n",dev->name);
1098 printk(KERN_WARNING "SISR=%x MISR=%x\n",readl(olympic_mmio+SISR),readl(olympic_mmio+LISR));
1099 olympic_priv->srb_queued=0;
1100 break;
1101 }
1102
1103 if (t == 0) {
1104 printk(KERN_WARNING "%s: SRB timed out. May not be fatal.\n",dev->name);
1105 }
1106 olympic_priv->srb_queued=0;
1107 }
1108 remove_wait_queue(&olympic_priv->srb_wait,&wait) ;
1109
1110 olympic_priv->rx_status_last_received++;
1111 olympic_priv->rx_status_last_received&=OLYMPIC_RX_RING_SIZE-1;
1112
1113 olympic_freemem(dev) ;
1114
1115 /* reset tx/rx fifo's and busmaster logic */
1116
1117 writel(readl(olympic_mmio+BCTL)|(3<<13),olympic_mmio+BCTL);
1118 udelay(1);
1119 writel(readl(olympic_mmio+BCTL)&~(3<<13),olympic_mmio+BCTL);
1120
1121#if OLYMPIC_DEBUG
1122 {
1123 int i ;
1124 printk("srb(%p): ",srb);
1125 for(i=0;i<4;i++)
1126 printk("%x ",readb(srb+i));
1127 printk("\n");
1128 }
1129#endif
1130 free_irq(dev->irq,dev);
1131
1132 return 0;
1133
1134}
1135
1136static void olympic_set_rx_mode(struct net_device *dev)
1137{
1138 struct olympic_private *olympic_priv = netdev_priv(dev);
1139 u8 __iomem *olympic_mmio = olympic_priv->olympic_mmio ;
1140 u8 options = 0;
1141 u8 __iomem *srb;
1142 struct netdev_hw_addr *ha;
1143 unsigned char dev_mc_address[4] ;
1144
1145 writel(olympic_priv->srb,olympic_mmio+LAPA);
1146 srb=olympic_priv->olympic_lap + (olympic_priv->srb & (~0xf800));
1147 options = olympic_priv->olympic_copy_all_options;
1148
1149 if (dev->flags&IFF_PROMISC)
1150 options |= 0x61 ;
1151 else
1152 options &= ~0x61 ;
1153
1154 /* Only issue the srb if there is a change in options */
1155
1156 if ((options ^ olympic_priv->olympic_copy_all_options)) {
1157
1158 /* Now to issue the srb command to alter the copy.all.options */
1159
1160 writeb(SRB_MODIFY_RECEIVE_OPTIONS,srb);
1161 writeb(0,srb+1);
1162 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1163 writeb(0,srb+3);
1164 writeb(olympic_priv->olympic_receive_options,srb+4);
1165 writeb(options,srb+5);
1166
1167 olympic_priv->srb_queued=2; /* Can't sleep, use srb_bh */
1168
1169 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1170
1171 olympic_priv->olympic_copy_all_options = options ;
1172
1173 return ;
1174 }
1175
1176 /* Set the functional addresses we need for multicast */
1177
1178 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1179
1180 netdev_for_each_mc_addr(ha, dev) {
1181 dev_mc_address[0] |= ha->addr[2];
1182 dev_mc_address[1] |= ha->addr[3];
1183 dev_mc_address[2] |= ha->addr[4];
1184 dev_mc_address[3] |= ha->addr[5];
1185 }
1186
1187 writeb(SRB_SET_FUNC_ADDRESS,srb+0);
1188 writeb(0,srb+1);
1189 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1190 writeb(0,srb+3);
1191 writeb(0,srb+4);
1192 writeb(0,srb+5);
1193 writeb(dev_mc_address[0],srb+6);
1194 writeb(dev_mc_address[1],srb+7);
1195 writeb(dev_mc_address[2],srb+8);
1196 writeb(dev_mc_address[3],srb+9);
1197
1198 olympic_priv->srb_queued = 2 ;
1199 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1200
1201}
1202
1203static void olympic_srb_bh(struct net_device *dev)
1204{
1205 struct olympic_private *olympic_priv = netdev_priv(dev);
1206 u8 __iomem *olympic_mmio = olympic_priv->olympic_mmio ;
1207 u8 __iomem *srb;
1208
1209 writel(olympic_priv->srb,olympic_mmio+LAPA);
1210 srb=olympic_priv->olympic_lap + (olympic_priv->srb & (~0xf800));
1211
1212 switch (readb(srb)) {
1213
1214 /* SRB_MODIFY_RECEIVE_OPTIONS i.e. set_multicast_list options (promiscuous)
1215 * At some point we should do something if we get an error, such as
1216 * resetting the IFF_PROMISC flag in dev
1217 */
1218
1219 case SRB_MODIFY_RECEIVE_OPTIONS:
1220 switch (readb(srb+2)) {
1221 case 0x01:
1222 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name) ;
1223 break ;
1224 case 0x04:
1225 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name);
1226 break ;
1227 default:
1228 if (olympic_priv->olympic_message_level)
1229 printk(KERN_WARNING "%s: Receive Options Modified to %x,%x\n",dev->name,olympic_priv->olympic_copy_all_options, olympic_priv->olympic_receive_options) ;
1230 break ;
1231 } /* switch srb[2] */
1232 break ;
1233
1234 /* SRB_SET_GROUP_ADDRESS - Multicast group setting
1235 */
1236
1237 case SRB_SET_GROUP_ADDRESS:
1238 switch (readb(srb+2)) {
1239 case 0x00:
1240 break ;
1241 case 0x01:
1242 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name);
1243 break ;
1244 case 0x04:
1245 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name);
1246 break ;
1247 case 0x3c:
1248 printk(KERN_WARNING "%s: Group/Functional address indicator bits not set correctly\n",dev->name) ;
1249 break ;
1250 case 0x3e: /* If we ever implement individual multicast addresses, will need to deal with this */
1251 printk(KERN_WARNING "%s: Group address registers full\n",dev->name) ;
1252 break ;
1253 case 0x55:
1254 printk(KERN_INFO "%s: Group Address already set.\n",dev->name) ;
1255 break ;
1256 default:
1257 break ;
1258 } /* switch srb[2] */
1259 break ;
1260
1261 /* SRB_RESET_GROUP_ADDRESS - Remove a multicast address from group list
1262 */
1263
1264 case SRB_RESET_GROUP_ADDRESS:
1265 switch (readb(srb+2)) {
1266 case 0x00:
1267 break ;
1268 case 0x01:
1269 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name);
1270 break ;
1271 case 0x04:
1272 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1273 break ;
1274 case 0x39: /* Must deal with this if individual multicast addresses used */
1275 printk(KERN_INFO "%s: Group address not found\n",dev->name);
1276 break ;
1277 default:
1278 break ;
1279 } /* switch srb[2] */
1280 break ;
1281
1282
1283 /* SRB_SET_FUNC_ADDRESS - Called by the set_rx_mode
1284 */
1285
1286 case SRB_SET_FUNC_ADDRESS:
1287 switch (readb(srb+2)) {
1288 case 0x00:
1289 if (olympic_priv->olympic_message_level)
1290 printk(KERN_INFO "%s: Functional Address Mask Set\n",dev->name);
1291 break ;
1292 case 0x01:
1293 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name);
1294 break ;
1295 case 0x04:
1296 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1297 break ;
1298 default:
1299 break ;
1300 } /* switch srb[2] */
1301 break ;
1302
1303 /* SRB_READ_LOG - Read and reset the adapter error counters
1304 */
1305
1306 case SRB_READ_LOG:
1307 switch (readb(srb+2)) {
1308 case 0x00:
1309 if (olympic_priv->olympic_message_level)
1310 printk(KERN_INFO "%s: Read Log issued\n",dev->name) ;
1311 break ;
1312 case 0x01:
1313 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name);
1314 break ;
1315 case 0x04:
1316 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1317 break ;
1318
1319 } /* switch srb[2] */
1320 break ;
1321
1322 /* SRB_READ_SR_COUNTERS - Read and reset the source routing bridge related counters */
1323
1324 case SRB_READ_SR_COUNTERS:
1325 switch (readb(srb+2)) {
1326 case 0x00:
1327 if (olympic_priv->olympic_message_level)
1328 printk(KERN_INFO "%s: Read Source Routing Counters issued\n",dev->name) ;
1329 break ;
1330 case 0x01:
1331 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name);
1332 break ;
1333 case 0x04:
1334 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1335 break ;
1336 default:
1337 break ;
1338 } /* switch srb[2] */
1339 break ;
1340
1341 default:
1342 printk(KERN_WARNING "%s: Unrecognized srb bh return value.\n",dev->name);
1343 break ;
1344 } /* switch srb[0] */
1345
1346}
1347
1348static int olympic_set_mac_address (struct net_device *dev, void *addr)
1349{
1350 struct sockaddr *saddr = addr ;
1351 struct olympic_private *olympic_priv = netdev_priv(dev);
1352
1353 if (netif_running(dev)) {
1354 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
1355 return -EIO ;
1356 }
1357
1358 memcpy(olympic_priv->olympic_laa, saddr->sa_data,dev->addr_len) ;
1359
1360 if (olympic_priv->olympic_message_level) {
1361 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, olympic_priv->olympic_laa[0],
1362 olympic_priv->olympic_laa[1], olympic_priv->olympic_laa[2],
1363 olympic_priv->olympic_laa[3], olympic_priv->olympic_laa[4],
1364 olympic_priv->olympic_laa[5]);
1365 }
1366
1367 return 0 ;
1368}
1369
1370static void olympic_arb_cmd(struct net_device *dev)
1371{
1372 struct olympic_private *olympic_priv = netdev_priv(dev);
1373 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
1374 u8 __iomem *arb_block, *asb_block, *srb ;
1375 u8 header_len ;
1376 u16 frame_len, buffer_len ;
1377 struct sk_buff *mac_frame ;
1378 u8 __iomem *buf_ptr ;
1379 u8 __iomem *frame_data ;
1380 u16 buff_off ;
1381 u16 lan_status = 0, lan_status_diff ; /* Initialize to stop compiler warning */
1382 u8 fdx_prot_error ;
1383 u16 next_ptr;
1384
1385 arb_block = (olympic_priv->olympic_lap + olympic_priv->arb) ;
1386 asb_block = (olympic_priv->olympic_lap + olympic_priv->asb) ;
1387 srb = (olympic_priv->olympic_lap + olympic_priv->srb) ;
1388
1389 if (readb(arb_block+0) == ARB_RECEIVE_DATA) { /* Receive.data, MAC frames */
1390
1391 header_len = readb(arb_block+8) ; /* 802.5 Token-Ring Header Length */
1392 frame_len = swab16(readw(arb_block + 10)) ;
1393
1394 buff_off = swab16(readw(arb_block + 6)) ;
1395
1396 buf_ptr = olympic_priv->olympic_lap + buff_off ;
1397
1398#if OLYMPIC_DEBUG
1399{
1400 int i;
1401 frame_data = buf_ptr+offsetof(struct mac_receive_buffer,frame_data) ;
1402
1403 for (i=0 ; i < 14 ; i++) {
1404 printk("Loc %d = %02x\n",i,readb(frame_data + i));
1405 }
1406
1407 printk("next %04x, fs %02x, len %04x\n",readw(buf_ptr+offsetof(struct mac_receive_buffer,next)), readb(buf_ptr+offsetof(struct mac_receive_buffer,frame_status)), readw(buf_ptr+offsetof(struct mac_receive_buffer,buffer_length)));
1408}
1409#endif
1410 mac_frame = dev_alloc_skb(frame_len) ;
1411 if (!mac_frame) {
1412 printk(KERN_WARNING "%s: Memory squeeze, dropping frame.\n", dev->name);
1413 goto drop_frame;
1414 }
1415
1416 /* Walk the buffer chain, creating the frame */
1417
1418 do {
1419 frame_data = buf_ptr+offsetof(struct mac_receive_buffer,frame_data) ;
1420 buffer_len = swab16(readw(buf_ptr+offsetof(struct mac_receive_buffer,buffer_length)));
1421 memcpy_fromio(skb_put(mac_frame, buffer_len), frame_data , buffer_len ) ;
1422 next_ptr=readw(buf_ptr+offsetof(struct mac_receive_buffer,next));
1423 } while (next_ptr && (buf_ptr=olympic_priv->olympic_lap + swab16(next_ptr)));
1424
1425 mac_frame->protocol = tr_type_trans(mac_frame, dev);
1426
1427 if (olympic_priv->olympic_network_monitor) {
1428 struct trh_hdr *mac_hdr;
1429 printk(KERN_WARNING "%s: Received MAC Frame, details:\n",dev->name);
1430 mac_hdr = tr_hdr(mac_frame);
1431 printk(KERN_WARNING "%s: MAC Frame Dest. Addr: %pM\n",
1432 dev->name, mac_hdr->daddr);
1433 printk(KERN_WARNING "%s: MAC Frame Srce. Addr: %pM\n",
1434 dev->name, mac_hdr->saddr);
1435 }
1436 netif_rx(mac_frame);
1437
1438drop_frame:
1439 /* Now tell the card we have dealt with the received frame */
1440
1441 /* Set LISR Bit 1 */
1442 writel(LISR_ARB_FREE,olympic_priv->olympic_mmio + LISR_SUM);
1443
1444 /* Is the ASB free ? */
1445
1446 if (readb(asb_block + 2) != 0xff) {
1447 olympic_priv->asb_queued = 1 ;
1448 writel(LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1449 return ;
1450 /* Drop out and wait for the bottom half to be run */
1451 }
1452
1453 writeb(ASB_RECEIVE_DATA,asb_block); /* Receive data */
1454 writeb(OLYMPIC_CLEAR_RET_CODE,asb_block+2); /* Necessary ?? */
1455 writeb(readb(arb_block+6),asb_block+6); /* Must send the address back to the adapter */
1456 writeb(readb(arb_block+7),asb_block+7); /* To let it know we have dealt with the data */
1457
1458 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1459
1460 olympic_priv->asb_queued = 2 ;
1461
1462 return ;
1463
1464 } else if (readb(arb_block) == ARB_LAN_CHANGE_STATUS) { /* Lan.change.status */
1465 lan_status = swab16(readw(arb_block+6));
1466 fdx_prot_error = readb(arb_block+8) ;
1467
1468 /* Issue ARB Free */
1469 writel(LISR_ARB_FREE,olympic_priv->olympic_mmio+LISR_SUM);
1470
1471 lan_status_diff = olympic_priv->olympic_lan_status ^ lan_status ;
1472
1473 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
1474 if (lan_status_diff & LSC_LWF)
1475 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
1476 if (lan_status_diff & LSC_ARW)
1477 printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
1478 if (lan_status_diff & LSC_FPE)
1479 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
1480 if (lan_status_diff & LSC_RR)
1481 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
1482
1483 /* Adapter has been closed by the hardware */
1484
1485 /* reset tx/rx fifo's and busmaster logic */
1486
1487 writel(readl(olympic_mmio+BCTL)|(3<<13),olympic_mmio+BCTL);
1488 udelay(1);
1489 writel(readl(olympic_mmio+BCTL)&~(3<<13),olympic_mmio+BCTL);
1490 netif_stop_queue(dev);
1491 olympic_priv->srb = readw(olympic_priv->olympic_lap + LAPWWO) ;
1492 printk(KERN_WARNING "%s: Adapter has been closed\n", dev->name);
1493 } /* If serious error */
1494
1495 if (olympic_priv->olympic_message_level) {
1496 if (lan_status_diff & LSC_SIG_LOSS)
1497 printk(KERN_WARNING "%s: No receive signal detected\n", dev->name);
1498 if (lan_status_diff & LSC_HARD_ERR)
1499 printk(KERN_INFO "%s: Beaconing\n",dev->name);
1500 if (lan_status_diff & LSC_SOFT_ERR)
1501 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame\n",dev->name);
1502 if (lan_status_diff & LSC_TRAN_BCN)
1503 printk(KERN_INFO "%s: We are transmitting the beacon, aaah\n",dev->name);
1504 if (lan_status_diff & LSC_SS)
1505 printk(KERN_INFO "%s: Single Station on the ring\n", dev->name);
1506 if (lan_status_diff & LSC_RING_REC)
1507 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
1508 if (lan_status_diff & LSC_FDX_MODE)
1509 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
1510 }
1511
1512 if (lan_status_diff & LSC_CO) {
1513
1514 if (olympic_priv->olympic_message_level)
1515 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
1516
1517 /* Issue READ.LOG command */
1518
1519 writeb(SRB_READ_LOG, srb);
1520 writeb(0,srb+1);
1521 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1522 writeb(0,srb+3);
1523 writeb(0,srb+4);
1524 writeb(0,srb+5);
1525
1526 olympic_priv->srb_queued=2; /* Can't sleep, use srb_bh */
1527
1528 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1529
1530 }
1531
1532 if (lan_status_diff & LSC_SR_CO) {
1533
1534 if (olympic_priv->olympic_message_level)
1535 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1536
1537 /* Issue a READ.SR.COUNTERS */
1538
1539 writeb(SRB_READ_SR_COUNTERS,srb);
1540 writeb(0,srb+1);
1541 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1542 writeb(0,srb+3);
1543
1544 olympic_priv->srb_queued=2; /* Can't sleep, use srb_bh */
1545
1546 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1547
1548 }
1549
1550 olympic_priv->olympic_lan_status = lan_status ;
1551
1552 } /* Lan.change.status */
1553 else
1554 printk(KERN_WARNING "%s: Unknown arb command\n", dev->name);
1555}
1556
1557static void olympic_asb_bh(struct net_device *dev)
1558{
1559 struct olympic_private *olympic_priv = netdev_priv(dev);
1560 u8 __iomem *arb_block, *asb_block ;
1561
1562 arb_block = (olympic_priv->olympic_lap + olympic_priv->arb) ;
1563 asb_block = (olympic_priv->olympic_lap + olympic_priv->asb) ;
1564
1565 if (olympic_priv->asb_queued == 1) { /* Dropped through the first time */
1566
1567 writeb(ASB_RECEIVE_DATA,asb_block); /* Receive data */
1568 writeb(OLYMPIC_CLEAR_RET_CODE,asb_block+2); /* Necessary ?? */
1569 writeb(readb(arb_block+6),asb_block+6); /* Must send the address back to the adapter */
1570 writeb(readb(arb_block+7),asb_block+7); /* To let it know we have dealt with the data */
1571
1572 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1573 olympic_priv->asb_queued = 2 ;
1574
1575 return ;
1576 }
1577
1578 if (olympic_priv->asb_queued == 2) {
1579 switch (readb(asb_block+2)) {
1580 case 0x01:
1581 printk(KERN_WARNING "%s: Unrecognized command code\n", dev->name);
1582 break ;
1583 case 0x26:
1584 printk(KERN_WARNING "%s: Unrecognized buffer address\n", dev->name);
1585 break ;
1586 case 0xFF:
1587 /* Valid response, everything should be ok again */
1588 break ;
1589 default:
1590 printk(KERN_WARNING "%s: Invalid return code in asb\n",dev->name);
1591 break ;
1592 }
1593 }
1594 olympic_priv->asb_queued = 0 ;
1595}
1596
1597static int olympic_change_mtu(struct net_device *dev, int mtu)
1598{
1599 struct olympic_private *olympic_priv = netdev_priv(dev);
1600 u16 max_mtu ;
1601
1602 if (olympic_priv->olympic_ring_speed == 4)
1603 max_mtu = 4500 ;
1604 else
1605 max_mtu = 18000 ;
1606
1607 if (mtu > max_mtu)
1608 return -EINVAL ;
1609 if (mtu < 100)
1610 return -EINVAL ;
1611
1612 dev->mtu = mtu ;
1613 olympic_priv->pkt_buf_sz = mtu + TR_HLEN ;
1614
1615 return 0 ;
1616}
1617
1618static int olympic_proc_show(struct seq_file *m, void *v)
1619{
1620 struct net_device *dev = m->private;
1621 struct olympic_private *olympic_priv=netdev_priv(dev);
1622 u8 __iomem *oat = (olympic_priv->olympic_lap + olympic_priv->olympic_addr_table_addr) ;
1623 u8 __iomem *opt = (olympic_priv->olympic_lap + olympic_priv->olympic_parms_addr) ;
1624 u8 addr[6];
1625 u8 addr2[6];
1626 int i;
1627
1628 seq_printf(m,
1629 "IBM Pit/Pit-Phy/Olympic Chipset Token Ring Adapter %s\n",dev->name);
1630 seq_printf(m, "\n%6s: Adapter Address : Node Address : Functional Addr\n",
1631 dev->name);
1632
1633 for (i = 0 ; i < 6 ; i++)
1634 addr[i] = readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr) + i);
1635
1636 seq_printf(m, "%6s: %pM : %pM : %02x:%02x:%02x:%02x\n",
1637 dev->name,
1638 dev->dev_addr, addr,
1639 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)),
1640 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+1),
1641 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+2),
1642 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+3));
1643
1644 seq_printf(m, "\n%6s: Token Ring Parameters Table:\n", dev->name);
1645
1646 seq_printf(m, "%6s: Physical Addr : Up Node Address : Poll Address : AccPri : Auth Src : Att Code :\n",
1647 dev->name) ;
1648
1649 for (i = 0 ; i < 6 ; i++)
1650 addr[i] = readb(opt+offsetof(struct olympic_parameters_table, up_node_addr) + i);
1651 for (i = 0 ; i < 6 ; i++)
1652 addr2[i] = readb(opt+offsetof(struct olympic_parameters_table, poll_addr) + i);
1653
1654 seq_printf(m, "%6s: %02x:%02x:%02x:%02x : %pM : %pM : %04x : %04x : %04x :\n",
1655 dev->name,
1656 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)),
1657 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)+1),
1658 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)+2),
1659 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)+3),
1660 addr, addr2,
1661 swab16(readw(opt+offsetof(struct olympic_parameters_table, acc_priority))),
1662 swab16(readw(opt+offsetof(struct olympic_parameters_table, auth_source_class))),
1663 swab16(readw(opt+offsetof(struct olympic_parameters_table, att_code))));
1664
1665 seq_printf(m, "%6s: Source Address : Bcn T : Maj. V : Lan St : Lcl Rg : Mon Err : Frame Correl : \n",
1666 dev->name) ;
1667
1668 for (i = 0 ; i < 6 ; i++)
1669 addr[i] = readb(opt+offsetof(struct olympic_parameters_table, source_addr) + i);
1670 seq_printf(m, "%6s: %pM : %04x : %04x : %04x : %04x : %04x : %04x : \n",
1671 dev->name, addr,
1672 swab16(readw(opt+offsetof(struct olympic_parameters_table, beacon_type))),
1673 swab16(readw(opt+offsetof(struct olympic_parameters_table, major_vector))),
1674 swab16(readw(opt+offsetof(struct olympic_parameters_table, lan_status))),
1675 swab16(readw(opt+offsetof(struct olympic_parameters_table, local_ring))),
1676 swab16(readw(opt+offsetof(struct olympic_parameters_table, mon_error))),
1677 swab16(readw(opt+offsetof(struct olympic_parameters_table, frame_correl))));
1678
1679 seq_printf(m, "%6s: Beacon Details : Tx : Rx : NAUN Node Address : NAUN Node Phys : \n",
1680 dev->name) ;
1681
1682 for (i = 0 ; i < 6 ; i++)
1683 addr[i] = readb(opt+offsetof(struct olympic_parameters_table, beacon_naun) + i);
1684 seq_printf(m, "%6s: : %02x : %02x : %pM : %02x:%02x:%02x:%02x : \n",
1685 dev->name,
1686 swab16(readw(opt+offsetof(struct olympic_parameters_table, beacon_transmit))),
1687 swab16(readw(opt+offsetof(struct olympic_parameters_table, beacon_receive))),
1688 addr,
1689 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)),
1690 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)+1),
1691 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)+2),
1692 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)+3));
1693
1694 return 0;
1695}
1696
1697static int olympic_proc_open(struct inode *inode, struct file *file)
1698{
1699 return single_open(file, olympic_proc_show, PDE(inode)->data);
1700}
1701
1702static const struct file_operations olympic_proc_ops = {
1703 .open = olympic_proc_open,
1704 .read = seq_read,
1705 .llseek = seq_lseek,
1706 .release = single_release,
1707};
1708
1709static void __devexit olympic_remove_one(struct pci_dev *pdev)
1710{
1711 struct net_device *dev = pci_get_drvdata(pdev) ;
1712 struct olympic_private *olympic_priv=netdev_priv(dev);
1713
1714 if (olympic_priv->olympic_network_monitor) {
1715 char proc_name[20] ;
1716 strcpy(proc_name,"olympic_") ;
1717 strcat(proc_name,dev->name) ;
1718 remove_proc_entry(proc_name,init_net.proc_net);
1719 }
1720 unregister_netdev(dev) ;
1721 iounmap(olympic_priv->olympic_mmio) ;
1722 iounmap(olympic_priv->olympic_lap) ;
1723 pci_release_regions(pdev) ;
1724 pci_set_drvdata(pdev,NULL) ;
1725 free_netdev(dev) ;
1726}
1727
1728static struct pci_driver olympic_driver = {
1729 .name = "olympic",
1730 .id_table = olympic_pci_tbl,
1731 .probe = olympic_probe,
1732 .remove = __devexit_p(olympic_remove_one),
1733};
1734
1735module_pci_driver(olympic_driver);
1736
1737MODULE_LICENSE("GPL");
diff --git a/drivers/net/tokenring/olympic.h b/drivers/net/tokenring/olympic.h
deleted file mode 100644
index 30631bae4c94..000000000000
--- a/drivers/net/tokenring/olympic.h
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * olympic.h (c) 1999 Peter De Schrijver All Rights Reserved
3 * 1999,2000 Mike Phillips (mikep@linuxtr.net)
4 *
5 * Linux driver for IBM PCI tokenring cards based on the olympic and the PIT/PHY chipset.
6 *
7 * Base Driver Skeleton:
8 * Written 1993-94 by Donald Becker.
9 *
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.
12 *
13 * This software may be used and distributed according to the terms
14 * of the GNU General Public License, incorporated herein by reference.
15 */
16
17#define CID 0x4e
18
19#define BCTL 0x70
20#define BCTL_SOFTRESET (1<<15)
21#define BCTL_MIMREB (1<<6)
22#define BCTL_MODE_INDICATOR (1<<5)
23
24#define GPR 0x4a
25#define GPR_OPTI_BF (1<<6)
26#define GPR_NEPTUNE_BF (1<<4)
27#define GPR_AUTOSENSE (1<<2)
28#define GPR_16MBPS (1<<3)
29
30#define PAG 0x85
31#define LBC 0x8e
32
33#define LISR 0x10
34#define LISR_SUM 0x14
35#define LISR_RWM 0x18
36
37#define LISR_LIE (1<<15)
38#define LISR_SLIM (1<<13)
39#define LISR_SLI (1<<12)
40#define LISR_PCMSRMASK (1<<11)
41#define LISR_PCMSRINT (1<<10)
42#define LISR_WOLMASK (1<<9)
43#define LISR_WOL (1<<8)
44#define LISR_SRB_CMD (1<<5)
45#define LISR_ASB_REPLY (1<<4)
46#define LISR_ASB_FREE_REQ (1<<2)
47#define LISR_ARB_FREE (1<<1)
48#define LISR_TRB_FRAME (1<<0)
49
50#define SISR 0x20
51#define SISR_SUM 0x24
52#define SISR_RWM 0x28
53#define SISR_RR 0x2C
54#define SISR_RESMASK 0x30
55#define SISR_MASK 0x54
56#define SISR_MASK_SUM 0x58
57#define SISR_MASK_RWM 0x5C
58
59#define SISR_TX2_IDLE (1<<31)
60#define SISR_TX2_HALT (1<<29)
61#define SISR_TX2_EOF (1<<28)
62#define SISR_TX1_IDLE (1<<27)
63#define SISR_TX1_HALT (1<<25)
64#define SISR_TX1_EOF (1<<24)
65#define SISR_TIMEOUT (1<<23)
66#define SISR_RX_NOBUF (1<<22)
67#define SISR_RX_STATUS (1<<21)
68#define SISR_RX_HALT (1<<18)
69#define SISR_RX_EOF_EARLY (1<<16)
70#define SISR_MI (1<<15)
71#define SISR_PI (1<<13)
72#define SISR_ERR (1<<9)
73#define SISR_ADAPTER_CHECK (1<<6)
74#define SISR_SRB_REPLY (1<<5)
75#define SISR_ASB_FREE (1<<4)
76#define SISR_ARB_CMD (1<<3)
77#define SISR_TRB_REPLY (1<<2)
78
79#define EISR 0x34
80#define EISR_RWM 0x38
81#define EISR_MASK 0x3c
82#define EISR_MASK_OPTIONS 0x001FFF7F
83
84#define LAPA 0x60
85#define LAPWWO 0x64
86#define LAPWWC 0x68
87#define LAPCTL 0x6C
88#define LAIPD 0x78
89#define LAIPDDINC 0x7C
90
91#define TIMER 0x50
92
93#define CLKCTL 0x74
94#define CLKCTL_PAUSE (1<<15)
95
96#define PM_CON 0x4
97
98#define BMCTL_SUM 0x40
99#define BMCTL_RWM 0x44
100#define BMCTL_TX2_DIS (1<<30)
101#define BMCTL_TX1_DIS (1<<26)
102#define BMCTL_RX_DIS (1<<22)
103
104#define BMASR 0xcc
105
106#define RXDESCQ 0x90
107#define RXDESCQCNT 0x94
108#define RXCDA 0x98
109#define RXENQ 0x9C
110#define RXSTATQ 0xA0
111#define RXSTATQCNT 0xA4
112#define RXCSA 0xA8
113#define RXCLEN 0xAC
114#define RXHLEN 0xAE
115
116#define TXDESCQ_1 0xb0
117#define TXDESCQ_2 0xd0
118#define TXDESCQCNT_1 0xb4
119#define TXDESCQCNT_2 0xd4
120#define TXCDA_1 0xb8
121#define TXCDA_2 0xd8
122#define TXENQ_1 0xbc
123#define TXENQ_2 0xdc
124#define TXSTATQ_1 0xc0
125#define TXSTATQ_2 0xe0
126#define TXSTATQCNT_1 0xc4
127#define TXSTATQCNT_2 0xe4
128#define TXCSA_1 0xc8
129#define TXCSA_2 0xe8
130/* Cardbus */
131#define FERMASK 0xf4
132#define FERMASK_INT_BIT (1<<15)
133
134#define OLYMPIC_IO_SPACE 256
135
136#define SRB_COMMAND_SIZE 50
137
138#define OLYMPIC_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
139
140/* Defines for LAN STATUS CHANGE reports */
141#define LSC_SIG_LOSS 0x8000
142#define LSC_HARD_ERR 0x4000
143#define LSC_SOFT_ERR 0x2000
144#define LSC_TRAN_BCN 0x1000
145#define LSC_LWF 0x0800
146#define LSC_ARW 0x0400
147#define LSC_FPE 0x0200
148#define LSC_RR 0x0100
149#define LSC_CO 0x0080
150#define LSC_SS 0x0040
151#define LSC_RING_REC 0x0020
152#define LSC_SR_CO 0x0010
153#define LSC_FDX_MODE 0x0004
154
155/* Defines for OPEN ADAPTER command */
156
157#define OPEN_ADAPTER_EXT_WRAP (1<<15)
158#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
159#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
160#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
161#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
162#define OPEN_ADAPTER_ENABLE_EC (1<<10)
163#define OPEN_ADAPTER_CONTENDER (1<<8)
164#define OPEN_ADAPTER_PASS_BEACON (1<<7)
165#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
166#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
167#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
168#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
169#define OPEN_ADAPTER_USE_OPTS2 (1<<0)
170
171#define OPEN_ADAPTER_2_ENABLE_ONNOW (1<<15)
172
173/* Defines for SRB Commands */
174
175#define SRB_ACCESS_REGISTER 0x1f
176#define SRB_CLOSE_ADAPTER 0x04
177#define SRB_CONFIGURE_BRIDGE 0x0c
178#define SRB_CONFIGURE_WAKEUP_EVENT 0x1a
179#define SRB_MODIFY_BRIDGE_PARMS 0x15
180#define SRB_MODIFY_OPEN_OPTIONS 0x01
181#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
182#define SRB_NO_OPERATION 0x00
183#define SRB_OPEN_ADAPTER 0x03
184#define SRB_READ_LOG 0x08
185#define SRB_READ_SR_COUNTERS 0x16
186#define SRB_RESET_GROUP_ADDRESS 0x02
187#define SRB_SAVE_CONFIGURATION 0x1b
188#define SRB_SET_BRIDGE_PARMS 0x09
189#define SRB_SET_BRIDGE_TARGETS 0x10
190#define SRB_SET_FUNC_ADDRESS 0x07
191#define SRB_SET_GROUP_ADDRESS 0x06
192#define SRB_SET_GROUP_ADDR_OPTIONS 0x11
193#define SRB_UPDATE_WAKEUP_PATTERN 0x19
194
195/* Clear return code */
196
197#define OLYMPIC_CLEAR_RET_CODE 0xfe
198
199/* ARB Commands */
200#define ARB_RECEIVE_DATA 0x81
201#define ARB_LAN_CHANGE_STATUS 0x84
202/* ASB Response commands */
203
204#define ASB_RECEIVE_DATA 0x81
205
206
207/* Olympic defaults for buffers */
208
209#define OLYMPIC_RX_RING_SIZE 16 /* should be a power of 2 */
210#define OLYMPIC_TX_RING_SIZE 8 /* should be a power of 2 */
211
212#define PKT_BUF_SZ 4096 /* Default packet size */
213
214/* Olympic data structures */
215
216/* xxxx These structures are all little endian in hardware. */
217
218struct olympic_tx_desc {
219 __le32 buffer;
220 __le32 status_length;
221};
222
223struct olympic_tx_status {
224 __le32 status;
225};
226
227struct olympic_rx_desc {
228 __le32 buffer;
229 __le32 res_length;
230};
231
232struct olympic_rx_status {
233 __le32 fragmentcnt_framelen;
234 __le32 status_buffercnt;
235};
236/* xxxx END These structures are all little endian in hardware. */
237/* xxxx There may be more, but I'm pretty sure about these */
238
239struct mac_receive_buffer {
240 __le16 next ;
241 u8 padding ;
242 u8 frame_status ;
243 __le16 buffer_length ;
244 u8 frame_data ;
245};
246
247struct olympic_private {
248
249 u16 srb; /* be16 */
250 u16 trb; /* be16 */
251 u16 arb; /* be16 */
252 u16 asb; /* be16 */
253
254 u8 __iomem *olympic_mmio;
255 u8 __iomem *olympic_lap;
256 struct pci_dev *pdev ;
257 const char *olympic_card_name;
258
259 spinlock_t olympic_lock ;
260
261 volatile int srb_queued; /* True if an SRB is still posted */
262 wait_queue_head_t srb_wait;
263
264 volatile int asb_queued; /* True if an ASB is posted */
265
266 volatile int trb_queued; /* True if a TRB is posted */
267 wait_queue_head_t trb_wait ;
268
269 /* These must be on a 4 byte boundary. */
270 struct olympic_rx_desc olympic_rx_ring[OLYMPIC_RX_RING_SIZE];
271 struct olympic_tx_desc olympic_tx_ring[OLYMPIC_TX_RING_SIZE];
272 struct olympic_rx_status olympic_rx_status_ring[OLYMPIC_RX_RING_SIZE];
273 struct olympic_tx_status olympic_tx_status_ring[OLYMPIC_TX_RING_SIZE];
274
275 struct sk_buff *tx_ring_skb[OLYMPIC_TX_RING_SIZE], *rx_ring_skb[OLYMPIC_RX_RING_SIZE];
276 int tx_ring_free, tx_ring_last_status, rx_ring_last_received,rx_status_last_received, free_tx_ring_entries;
277
278 u16 olympic_lan_status ;
279 u8 olympic_ring_speed ;
280 u16 pkt_buf_sz ;
281 u8 olympic_receive_options, olympic_copy_all_options,olympic_message_level, olympic_network_monitor;
282 u16 olympic_addr_table_addr, olympic_parms_addr ;
283 u8 olympic_laa[6] ;
284 u32 rx_ring_dma_addr;
285 u32 rx_status_ring_dma_addr;
286 u32 tx_ring_dma_addr;
287 u32 tx_status_ring_dma_addr;
288};
289
290struct olympic_adapter_addr_table {
291
292 u8 node_addr[6] ;
293 u8 reserved[4] ;
294 u8 func_addr[4] ;
295} ;
296
297struct olympic_parameters_table {
298
299 u8 phys_addr[4] ;
300 u8 up_node_addr[6] ;
301 u8 up_phys_addr[4] ;
302 u8 poll_addr[6] ;
303 u16 reserved ;
304 u16 acc_priority ;
305 u16 auth_source_class ;
306 u16 att_code ;
307 u8 source_addr[6] ;
308 u16 beacon_type ;
309 u16 major_vector ;
310 u16 lan_status ;
311 u16 soft_error_time ;
312 u16 reserved1 ;
313 u16 local_ring ;
314 u16 mon_error ;
315 u16 beacon_transmit ;
316 u16 beacon_receive ;
317 u16 frame_correl ;
318 u8 beacon_naun[6] ;
319 u32 reserved2 ;
320 u8 beacon_phys[4] ;
321};
diff --git a/drivers/net/tokenring/proteon.c b/drivers/net/tokenring/proteon.c
deleted file mode 100644
index 62d90e40f9ec..000000000000
--- a/drivers/net/tokenring/proteon.c
+++ /dev/null
@@ -1,422 +0,0 @@
1/*
2 * proteon.c: A network driver for Proteon ISA token ring cards.
3 *
4 * Based on tmspci written 1999 by Adam Fritzler
5 *
6 * Written 2003 by Jochen Friedrich
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 * This driver module supports the following cards:
12 * - Proteon 1392, 1392+
13 *
14 * Maintainer(s):
15 * AF Adam Fritzler
16 * JF Jochen Friedrich jochen@scram.de
17 *
18 * Modification History:
19 * 02-Jan-03 JF Created
20 *
21 */
22static const char version[] = "proteon.c: v1.00 02/01/2003 by Jochen Friedrich\n";
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/trdevice.h>
32#include <linux/platform_device.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/pci.h>
37#include <asm/dma.h>
38
39#include "tms380tr.h"
40
41#define PROTEON_IO_EXTENT 32
42
43/* A zero-terminated list of I/O addresses to be probed. */
44static unsigned int portlist[] __initdata = {
45 0x0A20, 0x0E20, 0x1A20, 0x1E20, 0x2A20, 0x2E20, 0x3A20, 0x3E20,// Prot.
46 0x4A20, 0x4E20, 0x5A20, 0x5E20, 0x6A20, 0x6E20, 0x7A20, 0x7E20,// Prot.
47 0x8A20, 0x8E20, 0x9A20, 0x9E20, 0xAA20, 0xAE20, 0xBA20, 0xBE20,// Prot.
48 0xCA20, 0xCE20, 0xDA20, 0xDE20, 0xEA20, 0xEE20, 0xFA20, 0xFE20,// Prot.
49 0
50};
51
52/* A zero-terminated list of IRQs to be probed. */
53static unsigned short irqlist[] = {
54 7, 6, 5, 4, 3, 12, 11, 10, 9,
55 0
56};
57
58/* A zero-terminated list of DMAs to be probed. */
59static int dmalist[] __initdata = {
60 5, 6, 7,
61 0
62};
63
64static char cardname[] = "Proteon 1392\0";
65static u64 dma_mask = ISA_MAX_ADDRESS;
66static int proteon_open(struct net_device *dev);
67static void proteon_read_eeprom(struct net_device *dev);
68static unsigned short proteon_setnselout_pins(struct net_device *dev);
69
70static unsigned short proteon_sifreadb(struct net_device *dev, unsigned short reg)
71{
72 return inb(dev->base_addr + reg);
73}
74
75static unsigned short proteon_sifreadw(struct net_device *dev, unsigned short reg)
76{
77 return inw(dev->base_addr + reg);
78}
79
80static void proteon_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
81{
82 outb(val, dev->base_addr + reg);
83}
84
85static void proteon_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
86{
87 outw(val, dev->base_addr + reg);
88}
89
90static int __init proteon_probe1(struct net_device *dev, int ioaddr)
91{
92 unsigned char chk1, chk2;
93 int i;
94
95 if (!request_region(ioaddr, PROTEON_IO_EXTENT, cardname))
96 return -ENODEV;
97
98
99 chk1 = inb(ioaddr + 0x1f); /* Get Proteon ID reg 1 */
100 if (chk1 != 0x1f)
101 goto nodev;
102
103 chk1 = inb(ioaddr + 0x1e) & 0x07; /* Get Proteon ID reg 0 */
104 for (i=0; i<16; i++) {
105 chk2 = inb(ioaddr + 0x1e) & 0x07;
106 if (((chk1 + 1) & 0x07) != chk2)
107 goto nodev;
108 chk1 = chk2;
109 }
110
111 dev->base_addr = ioaddr;
112 return 0;
113nodev:
114 release_region(ioaddr, PROTEON_IO_EXTENT);
115 return -ENODEV;
116}
117
118static struct net_device_ops proteon_netdev_ops __read_mostly;
119
120static int __init setup_card(struct net_device *dev, struct device *pdev)
121{
122 struct net_local *tp;
123 static int versionprinted;
124 const unsigned *port;
125 int j,err = 0;
126
127 if (!dev)
128 return -ENOMEM;
129
130 if (dev->base_addr) /* probe specific location */
131 err = proteon_probe1(dev, dev->base_addr);
132 else {
133 for (port = portlist; *port; port++) {
134 err = proteon_probe1(dev, *port);
135 if (!err)
136 break;
137 }
138 }
139 if (err)
140 goto out5;
141
142 /* At this point we have found a valid card. */
143
144 if (versionprinted++ == 0)
145 printk(KERN_DEBUG "%s", version);
146
147 err = -EIO;
148 pdev->dma_mask = &dma_mask;
149 if (tmsdev_init(dev, pdev))
150 goto out4;
151
152 dev->base_addr &= ~3;
153
154 proteon_read_eeprom(dev);
155
156 printk(KERN_DEBUG "proteon.c: Ring Station Address: %pM\n",
157 dev->dev_addr);
158
159 tp = netdev_priv(dev);
160 tp->setnselout = proteon_setnselout_pins;
161
162 tp->sifreadb = proteon_sifreadb;
163 tp->sifreadw = proteon_sifreadw;
164 tp->sifwriteb = proteon_sifwriteb;
165 tp->sifwritew = proteon_sifwritew;
166
167 memcpy(tp->ProductID, cardname, PROD_ID_SIZE + 1);
168
169 tp->tmspriv = NULL;
170
171 dev->netdev_ops = &proteon_netdev_ops;
172
173 if (dev->irq == 0)
174 {
175 for(j = 0; irqlist[j] != 0; j++)
176 {
177 dev->irq = irqlist[j];
178 if (!request_irq(dev->irq, tms380tr_interrupt, 0,
179 cardname, dev))
180 break;
181 }
182
183 if(irqlist[j] == 0)
184 {
185 printk(KERN_INFO "proteon.c: AutoSelect no IRQ available\n");
186 goto out3;
187 }
188 }
189 else
190 {
191 for(j = 0; irqlist[j] != 0; j++)
192 if (irqlist[j] == dev->irq)
193 break;
194 if (irqlist[j] == 0)
195 {
196 printk(KERN_INFO "proteon.c: Illegal IRQ %d specified\n",
197 dev->irq);
198 goto out3;
199 }
200 if (request_irq(dev->irq, tms380tr_interrupt, 0,
201 cardname, dev))
202 {
203 printk(KERN_INFO "proteon.c: Selected IRQ %d not available\n",
204 dev->irq);
205 goto out3;
206 }
207 }
208
209 if (dev->dma == 0)
210 {
211 for(j = 0; dmalist[j] != 0; j++)
212 {
213 dev->dma = dmalist[j];
214 if (!request_dma(dev->dma, cardname))
215 break;
216 }
217
218 if(dmalist[j] == 0)
219 {
220 printk(KERN_INFO "proteon.c: AutoSelect no DMA available\n");
221 goto out2;
222 }
223 }
224 else
225 {
226 for(j = 0; dmalist[j] != 0; j++)
227 if (dmalist[j] == dev->dma)
228 break;
229 if (dmalist[j] == 0)
230 {
231 printk(KERN_INFO "proteon.c: Illegal DMA %d specified\n",
232 dev->dma);
233 goto out2;
234 }
235 if (request_dma(dev->dma, cardname))
236 {
237 printk(KERN_INFO "proteon.c: Selected DMA %d not available\n",
238 dev->dma);
239 goto out2;
240 }
241 }
242
243 err = register_netdev(dev);
244 if (err)
245 goto out;
246
247 printk(KERN_DEBUG "%s: IO: %#4lx IRQ: %d DMA: %d\n",
248 dev->name, dev->base_addr, dev->irq, dev->dma);
249
250 return 0;
251out:
252 free_dma(dev->dma);
253out2:
254 free_irq(dev->irq, dev);
255out3:
256 tmsdev_term(dev);
257out4:
258 release_region(dev->base_addr, PROTEON_IO_EXTENT);
259out5:
260 return err;
261}
262
263/*
264 * Reads MAC address from adapter RAM, which should've read it from
265 * the onboard ROM.
266 *
267 * Calling this on a board that does not support it can be a very
268 * dangerous thing. The Madge board, for instance, will lock your
269 * machine hard when this is called. Luckily, its supported in a
270 * separate driver. --ASF
271 */
272static void proteon_read_eeprom(struct net_device *dev)
273{
274 int i;
275
276 /* Address: 0000:0000 */
277 proteon_sifwritew(dev, 0, SIFADX);
278 proteon_sifwritew(dev, 0, SIFADR);
279
280 /* Read six byte MAC address data */
281 dev->addr_len = 6;
282 for(i = 0; i < 6; i++)
283 dev->dev_addr[i] = proteon_sifreadw(dev, SIFINC) >> 8;
284}
285
286static unsigned short proteon_setnselout_pins(struct net_device *dev)
287{
288 return 0;
289}
290
291static int proteon_open(struct net_device *dev)
292{
293 struct net_local *tp = netdev_priv(dev);
294 unsigned short val = 0;
295 int i;
296
297 /* Proteon reset sequence */
298 outb(0, dev->base_addr + 0x11);
299 mdelay(20);
300 outb(0x04, dev->base_addr + 0x11);
301 mdelay(20);
302 outb(0, dev->base_addr + 0x11);
303 mdelay(100);
304
305 /* set control/status reg */
306 val = inb(dev->base_addr + 0x11);
307 val |= 0x78;
308 val &= 0xf9;
309 if(tp->DataRate == SPEED_4)
310 val |= 0x20;
311 else
312 val &= ~0x20;
313
314 outb(val, dev->base_addr + 0x11);
315 outb(0xff, dev->base_addr + 0x12);
316 for(i = 0; irqlist[i] != 0; i++)
317 {
318 if(irqlist[i] == dev->irq)
319 break;
320 }
321 val = i;
322 i = (7 - dev->dma) << 4;
323 val |= i;
324 outb(val, dev->base_addr + 0x13);
325
326 return tms380tr_open(dev);
327}
328
329#define ISATR_MAX_ADAPTERS 3
330
331static int io[ISATR_MAX_ADAPTERS];
332static int irq[ISATR_MAX_ADAPTERS];
333static int dma[ISATR_MAX_ADAPTERS];
334
335MODULE_LICENSE("GPL");
336
337module_param_array(io, int, NULL, 0);
338module_param_array(irq, int, NULL, 0);
339module_param_array(dma, int, NULL, 0);
340
341static struct platform_device *proteon_dev[ISATR_MAX_ADAPTERS];
342
343static struct platform_driver proteon_driver = {
344 .driver = {
345 .name = "proteon",
346 },
347};
348
349static int __init proteon_init(void)
350{
351 struct net_device *dev;
352 struct platform_device *pdev;
353 int i, num = 0, err = 0;
354
355 proteon_netdev_ops = tms380tr_netdev_ops;
356 proteon_netdev_ops.ndo_open = proteon_open;
357 proteon_netdev_ops.ndo_stop = tms380tr_close;
358
359 err = platform_driver_register(&proteon_driver);
360 if (err)
361 return err;
362
363 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
364 dev = alloc_trdev(sizeof(struct net_local));
365 if (!dev)
366 continue;
367
368 dev->base_addr = io[i];
369 dev->irq = irq[i];
370 dev->dma = dma[i];
371 pdev = platform_device_register_simple("proteon",
372 i, NULL, 0);
373 if (IS_ERR(pdev)) {
374 free_netdev(dev);
375 continue;
376 }
377 err = setup_card(dev, &pdev->dev);
378 if (!err) {
379 proteon_dev[i] = pdev;
380 platform_set_drvdata(pdev, dev);
381 ++num;
382 } else {
383 platform_device_unregister(pdev);
384 free_netdev(dev);
385 }
386 }
387
388 printk(KERN_NOTICE "proteon.c: %d cards found.\n", num);
389 /* Probe for cards. */
390 if (num == 0) {
391 printk(KERN_NOTICE "proteon.c: No cards found.\n");
392 platform_driver_unregister(&proteon_driver);
393 return -ENODEV;
394 }
395 return 0;
396}
397
398static void __exit proteon_cleanup(void)
399{
400 struct net_device *dev;
401 int i;
402
403 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
404 struct platform_device *pdev = proteon_dev[i];
405
406 if (!pdev)
407 continue;
408 dev = platform_get_drvdata(pdev);
409 unregister_netdev(dev);
410 release_region(dev->base_addr, PROTEON_IO_EXTENT);
411 free_irq(dev->irq, dev);
412 free_dma(dev->dma);
413 tmsdev_term(dev);
414 free_netdev(dev);
415 platform_set_drvdata(pdev, NULL);
416 platform_device_unregister(pdev);
417 }
418 platform_driver_unregister(&proteon_driver);
419}
420
421module_init(proteon_init);
422module_exit(proteon_cleanup);
diff --git a/drivers/net/tokenring/skisa.c b/drivers/net/tokenring/skisa.c
deleted file mode 100644
index ee11e93dc30e..000000000000
--- a/drivers/net/tokenring/skisa.c
+++ /dev/null
@@ -1,432 +0,0 @@
1/*
2 * skisa.c: A network driver for SK-NET TMS380-based ISA token ring cards.
3 *
4 * Based on tmspci written 1999 by Adam Fritzler
5 *
6 * Written 2000 by Jochen Friedrich
7 * Dedicated to my girlfriend Steffi Bopp
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 * This driver module supports the following cards:
13 * - SysKonnect TR4/16(+) ISA (SK-4190)
14 *
15 * Maintainer(s):
16 * AF Adam Fritzler
17 * JF Jochen Friedrich jochen@scram.de
18 *
19 * Modification History:
20 * 14-Jan-01 JF Created
21 * 28-Oct-02 JF Fixed probe of card for static compilation.
22 * Fixed module init to not make hotplug go wild.
23 * 09-Nov-02 JF Fixed early bail out on out of memory
24 * situations if multiple cards are found.
25 * Cleaned up some unnecessary console SPAM.
26 * 09-Dec-02 JF Fixed module reference counting.
27 * 02-Jan-03 JF Renamed to skisa.c
28 *
29 */
30static const char version[] = "skisa.c: v1.03 09/12/2002 by Jochen Friedrich\n";
31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/netdevice.h>
38#include <linux/trdevice.h>
39#include <linux/platform_device.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/pci.h>
44#include <asm/dma.h>
45
46#include "tms380tr.h"
47
48#define SK_ISA_IO_EXTENT 32
49
50/* A zero-terminated list of I/O addresses to be probed. */
51static unsigned int portlist[] __initdata = {
52 0x0A20, 0x1A20, 0x0B20, 0x1B20, 0x0980, 0x1980, 0x0900, 0x1900,// SK
53 0
54};
55
56/* A zero-terminated list of IRQs to be probed.
57 * Used again after initial probe for sktr_chipset_init, called from sktr_open.
58 */
59static const unsigned short irqlist[] = {
60 3, 5, 9, 10, 11, 12, 15,
61 0
62};
63
64/* A zero-terminated list of DMAs to be probed. */
65static int dmalist[] __initdata = {
66 5, 6, 7,
67 0
68};
69
70static char isa_cardname[] = "SK NET TR 4/16 ISA\0";
71static u64 dma_mask = ISA_MAX_ADDRESS;
72static int sk_isa_open(struct net_device *dev);
73static void sk_isa_read_eeprom(struct net_device *dev);
74static unsigned short sk_isa_setnselout_pins(struct net_device *dev);
75
76static unsigned short sk_isa_sifreadb(struct net_device *dev, unsigned short reg)
77{
78 return inb(dev->base_addr + reg);
79}
80
81static unsigned short sk_isa_sifreadw(struct net_device *dev, unsigned short reg)
82{
83 return inw(dev->base_addr + reg);
84}
85
86static void sk_isa_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
87{
88 outb(val, dev->base_addr + reg);
89}
90
91static void sk_isa_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
92{
93 outw(val, dev->base_addr + reg);
94}
95
96
97static int __init sk_isa_probe1(struct net_device *dev, int ioaddr)
98{
99 unsigned char old, chk1, chk2;
100
101 if (!request_region(ioaddr, SK_ISA_IO_EXTENT, isa_cardname))
102 return -ENODEV;
103
104 old = inb(ioaddr + SIFADR); /* Get the old SIFADR value */
105
106 chk1 = 0; /* Begin with check value 0 */
107 do {
108 /* Write new SIFADR value */
109 outb(chk1, ioaddr + SIFADR);
110
111 /* Read, invert and write */
112 chk2 = inb(ioaddr + SIFADD);
113 chk2 ^= 0x0FE;
114 outb(chk2, ioaddr + SIFADR);
115
116 /* Read, invert and compare */
117 chk2 = inb(ioaddr + SIFADD);
118 chk2 ^= 0x0FE;
119
120 if(chk1 != chk2) {
121 release_region(ioaddr, SK_ISA_IO_EXTENT);
122 return -ENODEV;
123 }
124
125 chk1 -= 2;
126 } while(chk1 != 0); /* Repeat 128 times (all byte values) */
127
128 /* Restore the SIFADR value */
129 outb(old, ioaddr + SIFADR);
130
131 dev->base_addr = ioaddr;
132 return 0;
133}
134
135static struct net_device_ops sk_isa_netdev_ops __read_mostly;
136
137static int __init setup_card(struct net_device *dev, struct device *pdev)
138{
139 struct net_local *tp;
140 static int versionprinted;
141 const unsigned *port;
142 int j, err = 0;
143
144 if (!dev)
145 return -ENOMEM;
146
147 if (dev->base_addr) /* probe specific location */
148 err = sk_isa_probe1(dev, dev->base_addr);
149 else {
150 for (port = portlist; *port; port++) {
151 err = sk_isa_probe1(dev, *port);
152 if (!err)
153 break;
154 }
155 }
156 if (err)
157 goto out5;
158
159 /* At this point we have found a valid card. */
160
161 if (versionprinted++ == 0)
162 printk(KERN_DEBUG "%s", version);
163
164 err = -EIO;
165 pdev->dma_mask = &dma_mask;
166 if (tmsdev_init(dev, pdev))
167 goto out4;
168
169 dev->base_addr &= ~3;
170
171 sk_isa_read_eeprom(dev);
172
173 printk(KERN_DEBUG "skisa.c: Ring Station Address: %pM\n",
174 dev->dev_addr);
175
176 tp = netdev_priv(dev);
177 tp->setnselout = sk_isa_setnselout_pins;
178
179 tp->sifreadb = sk_isa_sifreadb;
180 tp->sifreadw = sk_isa_sifreadw;
181 tp->sifwriteb = sk_isa_sifwriteb;
182 tp->sifwritew = sk_isa_sifwritew;
183
184 memcpy(tp->ProductID, isa_cardname, PROD_ID_SIZE + 1);
185
186 tp->tmspriv = NULL;
187
188 dev->netdev_ops = &sk_isa_netdev_ops;
189
190 if (dev->irq == 0)
191 {
192 for(j = 0; irqlist[j] != 0; j++)
193 {
194 dev->irq = irqlist[j];
195 if (!request_irq(dev->irq, tms380tr_interrupt, 0,
196 isa_cardname, dev))
197 break;
198 }
199
200 if(irqlist[j] == 0)
201 {
202 printk(KERN_INFO "skisa.c: AutoSelect no IRQ available\n");
203 goto out3;
204 }
205 }
206 else
207 {
208 for(j = 0; irqlist[j] != 0; j++)
209 if (irqlist[j] == dev->irq)
210 break;
211 if (irqlist[j] == 0)
212 {
213 printk(KERN_INFO "skisa.c: Illegal IRQ %d specified\n",
214 dev->irq);
215 goto out3;
216 }
217 if (request_irq(dev->irq, tms380tr_interrupt, 0,
218 isa_cardname, dev))
219 {
220 printk(KERN_INFO "skisa.c: Selected IRQ %d not available\n",
221 dev->irq);
222 goto out3;
223 }
224 }
225
226 if (dev->dma == 0)
227 {
228 for(j = 0; dmalist[j] != 0; j++)
229 {
230 dev->dma = dmalist[j];
231 if (!request_dma(dev->dma, isa_cardname))
232 break;
233 }
234
235 if(dmalist[j] == 0)
236 {
237 printk(KERN_INFO "skisa.c: AutoSelect no DMA available\n");
238 goto out2;
239 }
240 }
241 else
242 {
243 for(j = 0; dmalist[j] != 0; j++)
244 if (dmalist[j] == dev->dma)
245 break;
246 if (dmalist[j] == 0)
247 {
248 printk(KERN_INFO "skisa.c: Illegal DMA %d specified\n",
249 dev->dma);
250 goto out2;
251 }
252 if (request_dma(dev->dma, isa_cardname))
253 {
254 printk(KERN_INFO "skisa.c: Selected DMA %d not available\n",
255 dev->dma);
256 goto out2;
257 }
258 }
259
260 err = register_netdev(dev);
261 if (err)
262 goto out;
263
264 printk(KERN_DEBUG "%s: IO: %#4lx IRQ: %d DMA: %d\n",
265 dev->name, dev->base_addr, dev->irq, dev->dma);
266
267 return 0;
268out:
269 free_dma(dev->dma);
270out2:
271 free_irq(dev->irq, dev);
272out3:
273 tmsdev_term(dev);
274out4:
275 release_region(dev->base_addr, SK_ISA_IO_EXTENT);
276out5:
277 return err;
278}
279
280/*
281 * Reads MAC address from adapter RAM, which should've read it from
282 * the onboard ROM.
283 *
284 * Calling this on a board that does not support it can be a very
285 * dangerous thing. The Madge board, for instance, will lock your
286 * machine hard when this is called. Luckily, its supported in a
287 * separate driver. --ASF
288 */
289static void sk_isa_read_eeprom(struct net_device *dev)
290{
291 int i;
292
293 /* Address: 0000:0000 */
294 sk_isa_sifwritew(dev, 0, SIFADX);
295 sk_isa_sifwritew(dev, 0, SIFADR);
296
297 /* Read six byte MAC address data */
298 dev->addr_len = 6;
299 for(i = 0; i < 6; i++)
300 dev->dev_addr[i] = sk_isa_sifreadw(dev, SIFINC) >> 8;
301}
302
303static unsigned short sk_isa_setnselout_pins(struct net_device *dev)
304{
305 return 0;
306}
307
308static int sk_isa_open(struct net_device *dev)
309{
310 struct net_local *tp = netdev_priv(dev);
311 unsigned short val = 0;
312 unsigned short oldval;
313 int i;
314
315 val = 0;
316 for(i = 0; irqlist[i] != 0; i++)
317 {
318 if(irqlist[i] == dev->irq)
319 break;
320 }
321
322 val |= CYCLE_TIME << 2;
323 val |= i << 4;
324 i = dev->dma - 5;
325 val |= i;
326 if(tp->DataRate == SPEED_4)
327 val |= LINE_SPEED_BIT;
328 else
329 val &= ~LINE_SPEED_BIT;
330 oldval = sk_isa_sifreadb(dev, POSREG);
331 /* Leave cycle bits alone */
332 oldval |= 0xf3;
333 val &= oldval;
334 sk_isa_sifwriteb(dev, val, POSREG);
335
336 return tms380tr_open(dev);
337}
338
339#define ISATR_MAX_ADAPTERS 3
340
341static int io[ISATR_MAX_ADAPTERS];
342static int irq[ISATR_MAX_ADAPTERS];
343static int dma[ISATR_MAX_ADAPTERS];
344
345MODULE_LICENSE("GPL");
346
347module_param_array(io, int, NULL, 0);
348module_param_array(irq, int, NULL, 0);
349module_param_array(dma, int, NULL, 0);
350
351static struct platform_device *sk_isa_dev[ISATR_MAX_ADAPTERS];
352
353static struct platform_driver sk_isa_driver = {
354 .driver = {
355 .name = "skisa",
356 },
357};
358
359static int __init sk_isa_init(void)
360{
361 struct net_device *dev;
362 struct platform_device *pdev;
363 int i, num = 0, err = 0;
364
365 sk_isa_netdev_ops = tms380tr_netdev_ops;
366 sk_isa_netdev_ops.ndo_open = sk_isa_open;
367 sk_isa_netdev_ops.ndo_stop = tms380tr_close;
368
369 err = platform_driver_register(&sk_isa_driver);
370 if (err)
371 return err;
372
373 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
374 dev = alloc_trdev(sizeof(struct net_local));
375 if (!dev)
376 continue;
377
378 dev->base_addr = io[i];
379 dev->irq = irq[i];
380 dev->dma = dma[i];
381 pdev = platform_device_register_simple("skisa",
382 i, NULL, 0);
383 if (IS_ERR(pdev)) {
384 free_netdev(dev);
385 continue;
386 }
387 err = setup_card(dev, &pdev->dev);
388 if (!err) {
389 sk_isa_dev[i] = pdev;
390 platform_set_drvdata(sk_isa_dev[i], dev);
391 ++num;
392 } else {
393 platform_device_unregister(pdev);
394 free_netdev(dev);
395 }
396 }
397
398 printk(KERN_NOTICE "skisa.c: %d cards found.\n", num);
399 /* Probe for cards. */
400 if (num == 0) {
401 printk(KERN_NOTICE "skisa.c: No cards found.\n");
402 platform_driver_unregister(&sk_isa_driver);
403 return -ENODEV;
404 }
405 return 0;
406}
407
408static void __exit sk_isa_cleanup(void)
409{
410 struct net_device *dev;
411 int i;
412
413 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
414 struct platform_device *pdev = sk_isa_dev[i];
415
416 if (!pdev)
417 continue;
418 dev = platform_get_drvdata(pdev);
419 unregister_netdev(dev);
420 release_region(dev->base_addr, SK_ISA_IO_EXTENT);
421 free_irq(dev->irq, dev);
422 free_dma(dev->dma);
423 tmsdev_term(dev);
424 free_netdev(dev);
425 platform_set_drvdata(pdev, NULL);
426 platform_device_unregister(pdev);
427 }
428 platform_driver_unregister(&sk_isa_driver);
429}
430
431module_init(sk_isa_init);
432module_exit(sk_isa_cleanup);
diff --git a/drivers/net/tokenring/smctr.c b/drivers/net/tokenring/smctr.c
deleted file mode 100644
index cb35fb79e016..000000000000
--- a/drivers/net/tokenring/smctr.c
+++ /dev/null
@@ -1,5717 +0,0 @@
1/*
2 * smctr.c: A network driver for the SMC Token Ring Adapters.
3 *
4 * Written by Jay Schulist <jschlst@samba.org>
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This device driver works with the following SMC adapters:
10 * - SMC TokenCard Elite (8115T, chips 825/584)
11 * - SMC TokenCard Elite/A MCA (8115T/A, chips 825/594)
12 *
13 * Source(s):
14 * - SMC TokenCard SDK.
15 *
16 * Maintainer(s):
17 * JS Jay Schulist <jschlst@samba.org>
18 *
19 * Changes:
20 * 07102000 JS Fixed a timing problem in smctr_wait_cmd();
21 * Also added a bit more discriptive error msgs.
22 * 07122000 JS Fixed problem with detecting a card with
23 * module io/irq/mem specified.
24 *
25 * To do:
26 * 1. Multicast support.
27 *
28 * Initial 2.5 cleanup Alan Cox <alan@lxorguk.ukuu.org.uk> 2002/10/28
29 */
30
31#include <linux/module.h>
32#include <linux/kernel.h>
33#include <linux/types.h>
34#include <linux/fcntl.h>
35#include <linux/interrupt.h>
36#include <linux/ptrace.h>
37#include <linux/ioport.h>
38#include <linux/in.h>
39#include <linux/string.h>
40#include <linux/time.h>
41#include <linux/errno.h>
42#include <linux/init.h>
43#include <linux/mca-legacy.h>
44#include <linux/delay.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/trdevice.h>
49#include <linux/bitops.h>
50#include <linux/firmware.h>
51
52#include <asm/io.h>
53#include <asm/dma.h>
54#include <asm/irq.h>
55
56#if BITS_PER_LONG == 64
57#error FIXME: driver does not support 64-bit platforms
58#endif
59
60#include "smctr.h" /* Our Stuff */
61
62static const char version[] __initdata =
63 KERN_INFO "smctr.c: v1.4 7/12/00 by jschlst@samba.org\n";
64static const char cardname[] = "smctr";
65
66
67#define SMCTR_IO_EXTENT 20
68
69#ifdef CONFIG_MCA_LEGACY
70static unsigned int smctr_posid = 0x6ec6;
71#endif
72
73static int ringspeed;
74
75/* SMC Name of the Adapter. */
76static char smctr_name[] = "SMC TokenCard";
77static char *smctr_model = "Unknown";
78
79/* Use 0 for production, 1 for verification, 2 for debug, and
80 * 3 for very verbose debug.
81 */
82#ifndef SMCTR_DEBUG
83#define SMCTR_DEBUG 1
84#endif
85static unsigned int smctr_debug = SMCTR_DEBUG;
86
87/* smctr.c prototypes and functions are arranged alphabeticly
88 * for clearity, maintainability and pure old fashion fun.
89 */
90/* A */
91static int smctr_alloc_shared_memory(struct net_device *dev);
92
93/* B */
94static int smctr_bypass_state(struct net_device *dev);
95
96/* C */
97static int smctr_checksum_firmware(struct net_device *dev);
98static int __init smctr_chk_isa(struct net_device *dev);
99static int smctr_chg_rx_mask(struct net_device *dev);
100static int smctr_clear_int(struct net_device *dev);
101static int smctr_clear_trc_reset(int ioaddr);
102static int smctr_close(struct net_device *dev);
103
104/* D */
105static int smctr_decode_firmware(struct net_device *dev,
106 const struct firmware *fw);
107static int smctr_disable_16bit(struct net_device *dev);
108static int smctr_disable_adapter_ctrl_store(struct net_device *dev);
109static int smctr_disable_bic_int(struct net_device *dev);
110
111/* E */
112static int smctr_enable_16bit(struct net_device *dev);
113static int smctr_enable_adapter_ctrl_store(struct net_device *dev);
114static int smctr_enable_adapter_ram(struct net_device *dev);
115static int smctr_enable_bic_int(struct net_device *dev);
116
117/* G */
118static int __init smctr_get_boardid(struct net_device *dev, int mca);
119static int smctr_get_group_address(struct net_device *dev);
120static int smctr_get_functional_address(struct net_device *dev);
121static unsigned int smctr_get_num_rx_bdbs(struct net_device *dev);
122static int smctr_get_physical_drop_number(struct net_device *dev);
123static __u8 *smctr_get_rx_pointer(struct net_device *dev, short queue);
124static int smctr_get_station_id(struct net_device *dev);
125static FCBlock *smctr_get_tx_fcb(struct net_device *dev, __u16 queue,
126 __u16 bytes_count);
127static int smctr_get_upstream_neighbor_addr(struct net_device *dev);
128
129/* H */
130static int smctr_hardware_send_packet(struct net_device *dev,
131 struct net_local *tp);
132/* I */
133static int smctr_init_acbs(struct net_device *dev);
134static int smctr_init_adapter(struct net_device *dev);
135static int smctr_init_card_real(struct net_device *dev);
136static int smctr_init_rx_bdbs(struct net_device *dev);
137static int smctr_init_rx_fcbs(struct net_device *dev);
138static int smctr_init_shared_memory(struct net_device *dev);
139static int smctr_init_tx_bdbs(struct net_device *dev);
140static int smctr_init_tx_fcbs(struct net_device *dev);
141static int smctr_internal_self_test(struct net_device *dev);
142static irqreturn_t smctr_interrupt(int irq, void *dev_id);
143static int smctr_issue_enable_int_cmd(struct net_device *dev,
144 __u16 interrupt_enable_mask);
145static int smctr_issue_int_ack(struct net_device *dev, __u16 iack_code,
146 __u16 ibits);
147static int smctr_issue_init_timers_cmd(struct net_device *dev);
148static int smctr_issue_init_txrx_cmd(struct net_device *dev);
149static int smctr_issue_insert_cmd(struct net_device *dev);
150static int smctr_issue_read_ring_status_cmd(struct net_device *dev);
151static int smctr_issue_read_word_cmd(struct net_device *dev, __u16 aword_cnt);
152static int smctr_issue_remove_cmd(struct net_device *dev);
153static int smctr_issue_resume_acb_cmd(struct net_device *dev);
154static int smctr_issue_resume_rx_bdb_cmd(struct net_device *dev, __u16 queue);
155static int smctr_issue_resume_rx_fcb_cmd(struct net_device *dev, __u16 queue);
156static int smctr_issue_resume_tx_fcb_cmd(struct net_device *dev, __u16 queue);
157static int smctr_issue_test_internal_rom_cmd(struct net_device *dev);
158static int smctr_issue_test_hic_cmd(struct net_device *dev);
159static int smctr_issue_test_mac_reg_cmd(struct net_device *dev);
160static int smctr_issue_trc_loopback_cmd(struct net_device *dev);
161static int smctr_issue_tri_loopback_cmd(struct net_device *dev);
162static int smctr_issue_write_byte_cmd(struct net_device *dev,
163 short aword_cnt, void *byte);
164static int smctr_issue_write_word_cmd(struct net_device *dev,
165 short aword_cnt, void *word);
166
167/* J */
168static int smctr_join_complete_state(struct net_device *dev);
169
170/* L */
171static int smctr_link_tx_fcbs_to_bdbs(struct net_device *dev);
172static int smctr_load_firmware(struct net_device *dev);
173static int smctr_load_node_addr(struct net_device *dev);
174static int smctr_lobe_media_test(struct net_device *dev);
175static int smctr_lobe_media_test_cmd(struct net_device *dev);
176static int smctr_lobe_media_test_state(struct net_device *dev);
177
178/* M */
179static int smctr_make_8025_hdr(struct net_device *dev,
180 MAC_HEADER *rmf, MAC_HEADER *tmf, __u16 ac_fc);
181static int smctr_make_access_pri(struct net_device *dev,
182 MAC_SUB_VECTOR *tsv);
183static int smctr_make_addr_mod(struct net_device *dev, MAC_SUB_VECTOR *tsv);
184static int smctr_make_auth_funct_class(struct net_device *dev,
185 MAC_SUB_VECTOR *tsv);
186static int smctr_make_corr(struct net_device *dev,
187 MAC_SUB_VECTOR *tsv, __u16 correlator);
188static int smctr_make_funct_addr(struct net_device *dev,
189 MAC_SUB_VECTOR *tsv);
190static int smctr_make_group_addr(struct net_device *dev,
191 MAC_SUB_VECTOR *tsv);
192static int smctr_make_phy_drop_num(struct net_device *dev,
193 MAC_SUB_VECTOR *tsv);
194static int smctr_make_product_id(struct net_device *dev, MAC_SUB_VECTOR *tsv);
195static int smctr_make_station_id(struct net_device *dev, MAC_SUB_VECTOR *tsv);
196static int smctr_make_ring_station_status(struct net_device *dev,
197 MAC_SUB_VECTOR *tsv);
198static int smctr_make_ring_station_version(struct net_device *dev,
199 MAC_SUB_VECTOR *tsv);
200static int smctr_make_tx_status_code(struct net_device *dev,
201 MAC_SUB_VECTOR *tsv, __u16 tx_fstatus);
202static int smctr_make_upstream_neighbor_addr(struct net_device *dev,
203 MAC_SUB_VECTOR *tsv);
204static int smctr_make_wrap_data(struct net_device *dev,
205 MAC_SUB_VECTOR *tsv);
206
207/* O */
208static int smctr_open(struct net_device *dev);
209static int smctr_open_tr(struct net_device *dev);
210
211/* P */
212struct net_device *smctr_probe(int unit);
213static int __init smctr_probe1(struct net_device *dev, int ioaddr);
214static int smctr_process_rx_packet(MAC_HEADER *rmf, __u16 size,
215 struct net_device *dev, __u16 rx_status);
216
217/* R */
218static int smctr_ram_memory_test(struct net_device *dev);
219static int smctr_rcv_chg_param(struct net_device *dev, MAC_HEADER *rmf,
220 __u16 *correlator);
221static int smctr_rcv_init(struct net_device *dev, MAC_HEADER *rmf,
222 __u16 *correlator);
223static int smctr_rcv_tx_forward(struct net_device *dev, MAC_HEADER *rmf);
224static int smctr_rcv_rq_addr_state_attch(struct net_device *dev,
225 MAC_HEADER *rmf, __u16 *correlator);
226static int smctr_rcv_unknown(struct net_device *dev, MAC_HEADER *rmf,
227 __u16 *correlator);
228static int smctr_reset_adapter(struct net_device *dev);
229static int smctr_restart_tx_chain(struct net_device *dev, short queue);
230static int smctr_ring_status_chg(struct net_device *dev);
231static int smctr_rx_frame(struct net_device *dev);
232
233/* S */
234static int smctr_send_dat(struct net_device *dev);
235static netdev_tx_t smctr_send_packet(struct sk_buff *skb,
236 struct net_device *dev);
237static int smctr_send_lobe_media_test(struct net_device *dev);
238static int smctr_send_rpt_addr(struct net_device *dev, MAC_HEADER *rmf,
239 __u16 correlator);
240static int smctr_send_rpt_attch(struct net_device *dev, MAC_HEADER *rmf,
241 __u16 correlator);
242static int smctr_send_rpt_state(struct net_device *dev, MAC_HEADER *rmf,
243 __u16 correlator);
244static int smctr_send_rpt_tx_forward(struct net_device *dev,
245 MAC_HEADER *rmf, __u16 tx_fstatus);
246static int smctr_send_rsp(struct net_device *dev, MAC_HEADER *rmf,
247 __u16 rcode, __u16 correlator);
248static int smctr_send_rq_init(struct net_device *dev);
249static int smctr_send_tx_forward(struct net_device *dev, MAC_HEADER *rmf,
250 __u16 *tx_fstatus);
251static int smctr_set_auth_access_pri(struct net_device *dev,
252 MAC_SUB_VECTOR *rsv);
253static int smctr_set_auth_funct_class(struct net_device *dev,
254 MAC_SUB_VECTOR *rsv);
255static int smctr_set_corr(struct net_device *dev, MAC_SUB_VECTOR *rsv,
256 __u16 *correlator);
257static int smctr_set_error_timer_value(struct net_device *dev,
258 MAC_SUB_VECTOR *rsv);
259static int smctr_set_frame_forward(struct net_device *dev,
260 MAC_SUB_VECTOR *rsv, __u8 dc_sc);
261static int smctr_set_local_ring_num(struct net_device *dev,
262 MAC_SUB_VECTOR *rsv);
263static unsigned short smctr_set_ctrl_attention(struct net_device *dev);
264static void smctr_set_multicast_list(struct net_device *dev);
265static int smctr_set_page(struct net_device *dev, __u8 *buf);
266static int smctr_set_phy_drop(struct net_device *dev,
267 MAC_SUB_VECTOR *rsv);
268static int smctr_set_ring_speed(struct net_device *dev);
269static int smctr_set_rx_look_ahead(struct net_device *dev);
270static int smctr_set_trc_reset(int ioaddr);
271static int smctr_setup_single_cmd(struct net_device *dev,
272 __u16 command, __u16 subcommand);
273static int smctr_setup_single_cmd_w_data(struct net_device *dev,
274 __u16 command, __u16 subcommand);
275static char *smctr_malloc(struct net_device *dev, __u16 size);
276static int smctr_status_chg(struct net_device *dev);
277
278/* T */
279static void smctr_timeout(struct net_device *dev);
280static int smctr_trc_send_packet(struct net_device *dev, FCBlock *fcb,
281 __u16 queue);
282static __u16 smctr_tx_complete(struct net_device *dev, __u16 queue);
283static unsigned short smctr_tx_move_frame(struct net_device *dev,
284 struct sk_buff *skb, __u8 *pbuff, unsigned int bytes);
285
286/* U */
287static int smctr_update_err_stats(struct net_device *dev);
288static int smctr_update_rx_chain(struct net_device *dev, __u16 queue);
289static int smctr_update_tx_chain(struct net_device *dev, FCBlock *fcb,
290 __u16 queue);
291
292/* W */
293static int smctr_wait_cmd(struct net_device *dev);
294static int smctr_wait_while_cbusy(struct net_device *dev);
295
296#define TO_256_BYTE_BOUNDRY(X) (((X + 0xff) & 0xff00) - X)
297#define TO_PARAGRAPH_BOUNDRY(X) (((X + 0x0f) & 0xfff0) - X)
298#define PARAGRAPH_BOUNDRY(X) smctr_malloc(dev, TO_PARAGRAPH_BOUNDRY(X))
299
300/* Allocate Adapter Shared Memory.
301 * IMPORTANT NOTE: Any changes to this function MUST be mirrored in the
302 * function "get_num_rx_bdbs" below!!!
303 *
304 * Order of memory allocation:
305 *
306 * 0. Initial System Configuration Block Pointer
307 * 1. System Configuration Block
308 * 2. System Control Block
309 * 3. Action Command Block
310 * 4. Interrupt Status Block
311 *
312 * 5. MAC TX FCB'S
313 * 6. NON-MAC TX FCB'S
314 * 7. MAC TX BDB'S
315 * 8. NON-MAC TX BDB'S
316 * 9. MAC RX FCB'S
317 * 10. NON-MAC RX FCB'S
318 * 11. MAC RX BDB'S
319 * 12. NON-MAC RX BDB'S
320 * 13. MAC TX Data Buffer( 1, 256 byte buffer)
321 * 14. MAC RX Data Buffer( 1, 256 byte buffer)
322 *
323 * 15. NON-MAC TX Data Buffer
324 * 16. NON-MAC RX Data Buffer
325 */
326static int smctr_alloc_shared_memory(struct net_device *dev)
327{
328 struct net_local *tp = netdev_priv(dev);
329
330 if(smctr_debug > 10)
331 printk(KERN_DEBUG "%s: smctr_alloc_shared_memory\n", dev->name);
332
333 /* Allocate initial System Control Block pointer.
334 * This pointer is located in the last page, last offset - 4.
335 */
336 tp->iscpb_ptr = (ISCPBlock *)(tp->ram_access + ((__u32)64 * 0x400)
337 - (long)ISCP_BLOCK_SIZE);
338
339 /* Allocate System Control Blocks. */
340 tp->scgb_ptr = (SCGBlock *)smctr_malloc(dev, sizeof(SCGBlock));
341 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
342
343 tp->sclb_ptr = (SCLBlock *)smctr_malloc(dev, sizeof(SCLBlock));
344 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
345
346 tp->acb_head = (ACBlock *)smctr_malloc(dev,
347 sizeof(ACBlock)*tp->num_acbs);
348 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
349
350 tp->isb_ptr = (ISBlock *)smctr_malloc(dev, sizeof(ISBlock));
351 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
352
353 tp->misc_command_data = (__u16 *)smctr_malloc(dev, MISC_DATA_SIZE);
354 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
355
356 /* Allocate transmit FCBs. */
357 tp->tx_fcb_head[MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
358 sizeof(FCBlock) * tp->num_tx_fcbs[MAC_QUEUE]);
359
360 tp->tx_fcb_head[NON_MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
361 sizeof(FCBlock) * tp->num_tx_fcbs[NON_MAC_QUEUE]);
362
363 tp->tx_fcb_head[BUG_QUEUE] = (FCBlock *)smctr_malloc(dev,
364 sizeof(FCBlock) * tp->num_tx_fcbs[BUG_QUEUE]);
365
366 /* Allocate transmit BDBs. */
367 tp->tx_bdb_head[MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
368 sizeof(BDBlock) * tp->num_tx_bdbs[MAC_QUEUE]);
369
370 tp->tx_bdb_head[NON_MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
371 sizeof(BDBlock) * tp->num_tx_bdbs[NON_MAC_QUEUE]);
372
373 tp->tx_bdb_head[BUG_QUEUE] = (BDBlock *)smctr_malloc(dev,
374 sizeof(BDBlock) * tp->num_tx_bdbs[BUG_QUEUE]);
375
376 /* Allocate receive FCBs. */
377 tp->rx_fcb_head[MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
378 sizeof(FCBlock) * tp->num_rx_fcbs[MAC_QUEUE]);
379
380 tp->rx_fcb_head[NON_MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
381 sizeof(FCBlock) * tp->num_rx_fcbs[NON_MAC_QUEUE]);
382
383 /* Allocate receive BDBs. */
384 tp->rx_bdb_head[MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
385 sizeof(BDBlock) * tp->num_rx_bdbs[MAC_QUEUE]);
386
387 tp->rx_bdb_end[MAC_QUEUE] = (BDBlock *)smctr_malloc(dev, 0);
388
389 tp->rx_bdb_head[NON_MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
390 sizeof(BDBlock) * tp->num_rx_bdbs[NON_MAC_QUEUE]);
391
392 tp->rx_bdb_end[NON_MAC_QUEUE] = (BDBlock *)smctr_malloc(dev, 0);
393
394 /* Allocate MAC transmit buffers.
395 * MAC Tx Buffers doen't have to be on an ODD Boundary.
396 */
397 tp->tx_buff_head[MAC_QUEUE]
398 = (__u16 *)smctr_malloc(dev, tp->tx_buff_size[MAC_QUEUE]);
399 tp->tx_buff_curr[MAC_QUEUE] = tp->tx_buff_head[MAC_QUEUE];
400 tp->tx_buff_end [MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
401
402 /* Allocate BUG transmit buffers. */
403 tp->tx_buff_head[BUG_QUEUE]
404 = (__u16 *)smctr_malloc(dev, tp->tx_buff_size[BUG_QUEUE]);
405 tp->tx_buff_curr[BUG_QUEUE] = tp->tx_buff_head[BUG_QUEUE];
406 tp->tx_buff_end[BUG_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
407
408 /* Allocate MAC receive data buffers.
409 * MAC Rx buffer doesn't have to be on a 256 byte boundary.
410 */
411 tp->rx_buff_head[MAC_QUEUE] = (__u16 *)smctr_malloc(dev,
412 RX_DATA_BUFFER_SIZE * tp->num_rx_bdbs[MAC_QUEUE]);
413 tp->rx_buff_end[MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
414
415 /* Allocate Non-MAC transmit buffers.
416 * ?? For maximum Netware performance, put Tx Buffers on
417 * ODD Boundary and then restore malloc to Even Boundrys.
418 */
419 smctr_malloc(dev, 1L);
420 tp->tx_buff_head[NON_MAC_QUEUE]
421 = (__u16 *)smctr_malloc(dev, tp->tx_buff_size[NON_MAC_QUEUE]);
422 tp->tx_buff_curr[NON_MAC_QUEUE] = tp->tx_buff_head[NON_MAC_QUEUE];
423 tp->tx_buff_end [NON_MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
424 smctr_malloc(dev, 1L);
425
426 /* Allocate Non-MAC receive data buffers.
427 * To guarantee a minimum of 256 contiguous memory to
428 * UM_Receive_Packet's lookahead pointer, before a page
429 * change or ring end is encountered, place each rx buffer on
430 * a 256 byte boundary.
431 */
432 smctr_malloc(dev, TO_256_BYTE_BOUNDRY(tp->sh_mem_used));
433 tp->rx_buff_head[NON_MAC_QUEUE] = (__u16 *)smctr_malloc(dev,
434 RX_DATA_BUFFER_SIZE * tp->num_rx_bdbs[NON_MAC_QUEUE]);
435 tp->rx_buff_end[NON_MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
436
437 return 0;
438}
439
440/* Enter Bypass state. */
441static int smctr_bypass_state(struct net_device *dev)
442{
443 int err;
444
445 if(smctr_debug > 10)
446 printk(KERN_DEBUG "%s: smctr_bypass_state\n", dev->name);
447
448 err = smctr_setup_single_cmd(dev, ACB_CMD_CHANGE_JOIN_STATE, JS_BYPASS_STATE);
449
450 return err;
451}
452
453static int smctr_checksum_firmware(struct net_device *dev)
454{
455 struct net_local *tp = netdev_priv(dev);
456 __u16 i, checksum = 0;
457
458 if(smctr_debug > 10)
459 printk(KERN_DEBUG "%s: smctr_checksum_firmware\n", dev->name);
460
461 smctr_enable_adapter_ctrl_store(dev);
462
463 for(i = 0; i < CS_RAM_SIZE; i += 2)
464 checksum += *((__u16 *)(tp->ram_access + i));
465
466 tp->microcode_version = *(__u16 *)(tp->ram_access
467 + CS_RAM_VERSION_OFFSET);
468 tp->microcode_version >>= 8;
469
470 smctr_disable_adapter_ctrl_store(dev);
471
472 if(checksum)
473 return checksum;
474
475 return 0;
476}
477
478static int __init smctr_chk_mca(struct net_device *dev)
479{
480#ifdef CONFIG_MCA_LEGACY
481 struct net_local *tp = netdev_priv(dev);
482 int current_slot;
483 __u8 r1, r2, r3, r4, r5;
484
485 current_slot = mca_find_unused_adapter(smctr_posid, 0);
486 if(current_slot == MCA_NOTFOUND)
487 return -ENODEV;
488
489 mca_set_adapter_name(current_slot, smctr_name);
490 mca_mark_as_used(current_slot);
491 tp->slot_num = current_slot;
492
493 r1 = mca_read_stored_pos(tp->slot_num, 2);
494 r2 = mca_read_stored_pos(tp->slot_num, 3);
495
496 if(tp->slot_num)
497 outb(CNFG_POS_CONTROL_REG, (__u8)((tp->slot_num - 1) | CNFG_SLOT_ENABLE_BIT));
498 else
499 outb(CNFG_POS_CONTROL_REG, (__u8)((tp->slot_num) | CNFG_SLOT_ENABLE_BIT));
500
501 r1 = inb(CNFG_POS_REG1);
502 r2 = inb(CNFG_POS_REG0);
503
504 tp->bic_type = BIC_594_CHIP;
505
506 /* IO */
507 r2 = mca_read_stored_pos(tp->slot_num, 2);
508 r2 &= 0xF0;
509 dev->base_addr = ((__u16)r2 << 8) + (__u16)0x800;
510 request_region(dev->base_addr, SMCTR_IO_EXTENT, smctr_name);
511
512 /* IRQ */
513 r5 = mca_read_stored_pos(tp->slot_num, 5);
514 r5 &= 0xC;
515 switch(r5)
516 {
517 case 0:
518 dev->irq = 3;
519 break;
520
521 case 0x4:
522 dev->irq = 4;
523 break;
524
525 case 0x8:
526 dev->irq = 10;
527 break;
528
529 default:
530 dev->irq = 15;
531 break;
532 }
533 if (request_irq(dev->irq, smctr_interrupt, IRQF_SHARED, smctr_name, dev)) {
534 release_region(dev->base_addr, SMCTR_IO_EXTENT);
535 return -ENODEV;
536 }
537
538 /* Get RAM base */
539 r3 = mca_read_stored_pos(tp->slot_num, 3);
540 tp->ram_base = ((__u32)(r3 & 0x7) << 13) + 0x0C0000;
541 if (r3 & 0x8)
542 tp->ram_base += 0x010000;
543 if (r3 & 0x80)
544 tp->ram_base += 0xF00000;
545
546 /* Get Ram Size */
547 r3 &= 0x30;
548 r3 >>= 4;
549
550 tp->ram_usable = (__u16)CNFG_SIZE_8KB << r3;
551 tp->ram_size = (__u16)CNFG_SIZE_64KB;
552 tp->board_id |= TOKEN_MEDIA;
553
554 r4 = mca_read_stored_pos(tp->slot_num, 4);
555 tp->rom_base = ((__u32)(r4 & 0x7) << 13) + 0x0C0000;
556 if (r4 & 0x8)
557 tp->rom_base += 0x010000;
558
559 /* Get ROM size. */
560 r4 >>= 4;
561 switch (r4) {
562 case 0:
563 tp->rom_size = CNFG_SIZE_8KB;
564 break;
565 case 1:
566 tp->rom_size = CNFG_SIZE_16KB;
567 break;
568 case 2:
569 tp->rom_size = CNFG_SIZE_32KB;
570 break;
571 default:
572 tp->rom_size = ROM_DISABLE;
573 }
574
575 /* Get Media Type. */
576 r5 = mca_read_stored_pos(tp->slot_num, 5);
577 r5 &= CNFG_MEDIA_TYPE_MASK;
578 switch(r5)
579 {
580 case (0):
581 tp->media_type = MEDIA_STP_4;
582 break;
583
584 case (1):
585 tp->media_type = MEDIA_STP_16;
586 break;
587
588 case (3):
589 tp->media_type = MEDIA_UTP_16;
590 break;
591
592 default:
593 tp->media_type = MEDIA_UTP_4;
594 break;
595 }
596 tp->media_menu = 14;
597
598 r2 = mca_read_stored_pos(tp->slot_num, 2);
599 if(!(r2 & 0x02))
600 tp->mode_bits |= EARLY_TOKEN_REL;
601
602 /* Disable slot */
603 outb(CNFG_POS_CONTROL_REG, 0);
604
605 tp->board_id = smctr_get_boardid(dev, 1);
606 switch(tp->board_id & 0xffff)
607 {
608 case WD8115TA:
609 smctr_model = "8115T/A";
610 break;
611
612 case WD8115T:
613 if(tp->extra_info & CHIP_REV_MASK)
614 smctr_model = "8115T rev XE";
615 else
616 smctr_model = "8115T rev XD";
617 break;
618
619 default:
620 smctr_model = "Unknown";
621 break;
622 }
623
624 return 0;
625#else
626 return -1;
627#endif /* CONFIG_MCA_LEGACY */
628}
629
630static int smctr_chg_rx_mask(struct net_device *dev)
631{
632 struct net_local *tp = netdev_priv(dev);
633 int err = 0;
634
635 if(smctr_debug > 10)
636 printk(KERN_DEBUG "%s: smctr_chg_rx_mask\n", dev->name);
637
638 smctr_enable_16bit(dev);
639 smctr_set_page(dev, (__u8 *)tp->ram_access);
640
641 if(tp->mode_bits & LOOPING_MODE_MASK)
642 tp->config_word0 |= RX_OWN_BIT;
643 else
644 tp->config_word0 &= ~RX_OWN_BIT;
645
646 if(tp->receive_mask & PROMISCUOUS_MODE)
647 tp->config_word0 |= PROMISCUOUS_BIT;
648 else
649 tp->config_word0 &= ~PROMISCUOUS_BIT;
650
651 if(tp->receive_mask & ACCEPT_ERR_PACKETS)
652 tp->config_word0 |= SAVBAD_BIT;
653 else
654 tp->config_word0 &= ~SAVBAD_BIT;
655
656 if(tp->receive_mask & ACCEPT_ATT_MAC_FRAMES)
657 tp->config_word0 |= RXATMAC;
658 else
659 tp->config_word0 &= ~RXATMAC;
660
661 if(tp->receive_mask & ACCEPT_MULTI_PROM)
662 tp->config_word1 |= MULTICAST_ADDRESS_BIT;
663 else
664 tp->config_word1 &= ~MULTICAST_ADDRESS_BIT;
665
666 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING_SPANNING)
667 tp->config_word1 |= SOURCE_ROUTING_SPANNING_BITS;
668 else
669 {
670 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING)
671 tp->config_word1 |= SOURCE_ROUTING_EXPLORER_BIT;
672 else
673 tp->config_word1 &= ~SOURCE_ROUTING_SPANNING_BITS;
674 }
675
676 if((err = smctr_issue_write_word_cmd(dev, RW_CONFIG_REGISTER_0,
677 &tp->config_word0)))
678 {
679 return err;
680 }
681
682 if((err = smctr_issue_write_word_cmd(dev, RW_CONFIG_REGISTER_1,
683 &tp->config_word1)))
684 {
685 return err;
686 }
687
688 smctr_disable_16bit(dev);
689
690 return 0;
691}
692
693static int smctr_clear_int(struct net_device *dev)
694{
695 struct net_local *tp = netdev_priv(dev);
696
697 outb((tp->trc_mask | CSR_CLRTINT), dev->base_addr + CSR);
698
699 return 0;
700}
701
702static int smctr_clear_trc_reset(int ioaddr)
703{
704 __u8 r;
705
706 r = inb(ioaddr + MSR);
707 outb(~MSR_RST & r, ioaddr + MSR);
708
709 return 0;
710}
711
712/*
713 * The inverse routine to smctr_open().
714 */
715static int smctr_close(struct net_device *dev)
716{
717 struct net_local *tp = netdev_priv(dev);
718 struct sk_buff *skb;
719 int err;
720
721 netif_stop_queue(dev);
722
723 tp->cleanup = 1;
724
725 /* Check to see if adapter is already in a closed state. */
726 if(tp->status != OPEN)
727 return 0;
728
729 smctr_enable_16bit(dev);
730 smctr_set_page(dev, (__u8 *)tp->ram_access);
731
732 if((err = smctr_issue_remove_cmd(dev)))
733 {
734 smctr_disable_16bit(dev);
735 return err;
736 }
737
738 for(;;)
739 {
740 skb = skb_dequeue(&tp->SendSkbQueue);
741 if(skb == NULL)
742 break;
743 tp->QueueSkb++;
744 dev_kfree_skb(skb);
745 }
746
747
748 return 0;
749}
750
751static int smctr_decode_firmware(struct net_device *dev,
752 const struct firmware *fw)
753{
754 struct net_local *tp = netdev_priv(dev);
755 short bit = 0x80, shift = 12;
756 DECODE_TREE_NODE *tree;
757 short branch, tsize;
758 __u16 buff = 0;
759 long weight;
760 __u8 *ucode;
761 __u16 *mem;
762
763 if(smctr_debug > 10)
764 printk(KERN_DEBUG "%s: smctr_decode_firmware\n", dev->name);
765
766 weight = *(long *)(fw->data + WEIGHT_OFFSET);
767 tsize = *(__u8 *)(fw->data + TREE_SIZE_OFFSET);
768 tree = (DECODE_TREE_NODE *)(fw->data + TREE_OFFSET);
769 ucode = (__u8 *)(fw->data + TREE_OFFSET
770 + (tsize * sizeof(DECODE_TREE_NODE)));
771 mem = (__u16 *)(tp->ram_access);
772
773 while(weight)
774 {
775 branch = ROOT;
776 while((tree + branch)->tag != LEAF && weight)
777 {
778 branch = *ucode & bit ? (tree + branch)->llink
779 : (tree + branch)->rlink;
780
781 bit >>= 1;
782 weight--;
783
784 if(bit == 0)
785 {
786 bit = 0x80;
787 ucode++;
788 }
789 }
790
791 buff |= (tree + branch)->info << shift;
792 shift -= 4;
793
794 if(shift < 0)
795 {
796 *(mem++) = SWAP_BYTES(buff);
797 buff = 0;
798 shift = 12;
799 }
800 }
801
802 /* The following assumes the Control Store Memory has
803 * been initialized to zero. If the last partial word
804 * is zero, it will not be written.
805 */
806 if(buff)
807 *(mem++) = SWAP_BYTES(buff);
808
809 return 0;
810}
811
812static int smctr_disable_16bit(struct net_device *dev)
813{
814 return 0;
815}
816
817/*
818 * On Exit, Adapter is:
819 * 1. TRC is in a reset state and un-initialized.
820 * 2. Adapter memory is enabled.
821 * 3. Control Store memory is out of context (-WCSS is 1).
822 */
823static int smctr_disable_adapter_ctrl_store(struct net_device *dev)
824{
825 struct net_local *tp = netdev_priv(dev);
826 int ioaddr = dev->base_addr;
827
828 if(smctr_debug > 10)
829 printk(KERN_DEBUG "%s: smctr_disable_adapter_ctrl_store\n", dev->name);
830
831 tp->trc_mask |= CSR_WCSS;
832 outb(tp->trc_mask, ioaddr + CSR);
833
834 return 0;
835}
836
837static int smctr_disable_bic_int(struct net_device *dev)
838{
839 struct net_local *tp = netdev_priv(dev);
840 int ioaddr = dev->base_addr;
841
842 tp->trc_mask = CSR_MSK_ALL | CSR_MSKCBUSY
843 | CSR_MSKTINT | CSR_WCSS;
844 outb(tp->trc_mask, ioaddr + CSR);
845
846 return 0;
847}
848
849static int smctr_enable_16bit(struct net_device *dev)
850{
851 struct net_local *tp = netdev_priv(dev);
852 __u8 r;
853
854 if(tp->adapter_bus == BUS_ISA16_TYPE)
855 {
856 r = inb(dev->base_addr + LAAR);
857 outb((r | LAAR_MEM16ENB), dev->base_addr + LAAR);
858 }
859
860 return 0;
861}
862
863/*
864 * To enable the adapter control store memory:
865 * 1. Adapter must be in a RESET state.
866 * 2. Adapter memory must be enabled.
867 * 3. Control Store Memory is in context (-WCSS is 0).
868 */
869static int smctr_enable_adapter_ctrl_store(struct net_device *dev)
870{
871 struct net_local *tp = netdev_priv(dev);
872 int ioaddr = dev->base_addr;
873
874 if(smctr_debug > 10)
875 printk(KERN_DEBUG "%s: smctr_enable_adapter_ctrl_store\n", dev->name);
876
877 smctr_set_trc_reset(ioaddr);
878 smctr_enable_adapter_ram(dev);
879
880 tp->trc_mask &= ~CSR_WCSS;
881 outb(tp->trc_mask, ioaddr + CSR);
882
883 return 0;
884}
885
886static int smctr_enable_adapter_ram(struct net_device *dev)
887{
888 int ioaddr = dev->base_addr;
889 __u8 r;
890
891 if(smctr_debug > 10)
892 printk(KERN_DEBUG "%s: smctr_enable_adapter_ram\n", dev->name);
893
894 r = inb(ioaddr + MSR);
895 outb(MSR_MEMB | r, ioaddr + MSR);
896
897 return 0;
898}
899
900static int smctr_enable_bic_int(struct net_device *dev)
901{
902 struct net_local *tp = netdev_priv(dev);
903 int ioaddr = dev->base_addr;
904 __u8 r;
905
906 switch(tp->bic_type)
907 {
908 case (BIC_584_CHIP):
909 tp->trc_mask = CSR_MSKCBUSY | CSR_WCSS;
910 outb(tp->trc_mask, ioaddr + CSR);
911 r = inb(ioaddr + IRR);
912 outb(r | IRR_IEN, ioaddr + IRR);
913 break;
914
915 case (BIC_594_CHIP):
916 tp->trc_mask = CSR_MSKCBUSY | CSR_WCSS;
917 outb(tp->trc_mask, ioaddr + CSR);
918 r = inb(ioaddr + IMCCR);
919 outb(r | IMCCR_EIL, ioaddr + IMCCR);
920 break;
921 }
922
923 return 0;
924}
925
926static int __init smctr_chk_isa(struct net_device *dev)
927{
928 struct net_local *tp = netdev_priv(dev);
929 int ioaddr = dev->base_addr;
930 __u8 r1, r2, b, chksum = 0;
931 __u16 r;
932 int i;
933 int err = -ENODEV;
934
935 if(smctr_debug > 10)
936 printk(KERN_DEBUG "%s: smctr_chk_isa %#4x\n", dev->name, ioaddr);
937
938 if((ioaddr & 0x1F) != 0)
939 goto out;
940
941 /* Grab the region so that no one else tries to probe our ioports. */
942 if (!request_region(ioaddr, SMCTR_IO_EXTENT, smctr_name)) {
943 err = -EBUSY;
944 goto out;
945 }
946
947 /* Checksum SMC node address */
948 for(i = 0; i < 8; i++)
949 {
950 b = inb(ioaddr + LAR0 + i);
951 chksum += b;
952 }
953
954 if (chksum != NODE_ADDR_CKSUM)
955 goto out2;
956
957 b = inb(ioaddr + BDID);
958 if(b != BRD_ID_8115T)
959 {
960 printk(KERN_ERR "%s: The adapter found is not supported\n", dev->name);
961 goto out2;
962 }
963
964 /* Check for 8115T Board ID */
965 r2 = 0;
966 for(r = 0; r < 8; r++)
967 {
968 r1 = inb(ioaddr + 0x8 + r);
969 r2 += r1;
970 }
971
972 /* value of RegF adds up the sum to 0xFF */
973 if((r2 != 0xFF) && (r2 != 0xEE))
974 goto out2;
975
976 /* Get adapter ID */
977 tp->board_id = smctr_get_boardid(dev, 0);
978 switch(tp->board_id & 0xffff)
979 {
980 case WD8115TA:
981 smctr_model = "8115T/A";
982 break;
983
984 case WD8115T:
985 if(tp->extra_info & CHIP_REV_MASK)
986 smctr_model = "8115T rev XE";
987 else
988 smctr_model = "8115T rev XD";
989 break;
990
991 default:
992 smctr_model = "Unknown";
993 break;
994 }
995
996 /* Store BIC type. */
997 tp->bic_type = BIC_584_CHIP;
998 tp->nic_type = NIC_825_CHIP;
999
1000 /* Copy Ram Size */
1001 tp->ram_usable = CNFG_SIZE_16KB;
1002 tp->ram_size = CNFG_SIZE_64KB;
1003
1004 /* Get 58x Ram Base */
1005 r1 = inb(ioaddr);
1006 r1 &= 0x3F;
1007
1008 r2 = inb(ioaddr + CNFG_LAAR_584);
1009 r2 &= CNFG_LAAR_MASK;
1010 r2 <<= 3;
1011 r2 |= ((r1 & 0x38) >> 3);
1012
1013 tp->ram_base = ((__u32)r2 << 16) + (((__u32)(r1 & 0x7)) << 13);
1014
1015 /* Get 584 Irq */
1016 r1 = 0;
1017 r1 = inb(ioaddr + CNFG_ICR_583);
1018 r1 &= CNFG_ICR_IR2_584;
1019
1020 r2 = inb(ioaddr + CNFG_IRR_583);
1021 r2 &= CNFG_IRR_IRQS; /* 0x60 */
1022 r2 >>= 5;
1023
1024 switch(r2)
1025 {
1026 case 0:
1027 if(r1 == 0)
1028 dev->irq = 2;
1029 else
1030 dev->irq = 10;
1031 break;
1032
1033 case 1:
1034 if(r1 == 0)
1035 dev->irq = 3;
1036 else
1037 dev->irq = 11;
1038 break;
1039
1040 case 2:
1041 if(r1 == 0)
1042 {
1043 if(tp->extra_info & ALTERNATE_IRQ_BIT)
1044 dev->irq = 5;
1045 else
1046 dev->irq = 4;
1047 }
1048 else
1049 dev->irq = 15;
1050 break;
1051
1052 case 3:
1053 if(r1 == 0)
1054 dev->irq = 7;
1055 else
1056 dev->irq = 4;
1057 break;
1058
1059 default:
1060 printk(KERN_ERR "%s: No IRQ found aborting\n", dev->name);
1061 goto out2;
1062 }
1063
1064 if (request_irq(dev->irq, smctr_interrupt, IRQF_SHARED, smctr_name, dev))
1065 goto out2;
1066
1067 /* Get 58x Rom Base */
1068 r1 = inb(ioaddr + CNFG_BIO_583);
1069 r1 &= 0x3E;
1070 r1 |= 0x40;
1071
1072 tp->rom_base = (__u32)r1 << 13;
1073
1074 /* Get 58x Rom Size */
1075 r1 = inb(ioaddr + CNFG_BIO_583);
1076 r1 &= 0xC0;
1077 if(r1 == 0)
1078 tp->rom_size = ROM_DISABLE;
1079 else
1080 {
1081 r1 >>= 6;
1082 tp->rom_size = (__u16)CNFG_SIZE_8KB << r1;
1083 }
1084
1085 /* Get 58x Boot Status */
1086 r1 = inb(ioaddr + CNFG_GP2);
1087
1088 tp->mode_bits &= (~BOOT_STATUS_MASK);
1089
1090 if(r1 & CNFG_GP2_BOOT_NIBBLE)
1091 tp->mode_bits |= BOOT_TYPE_1;
1092
1093 /* Get 58x Zero Wait State */
1094 tp->mode_bits &= (~ZERO_WAIT_STATE_MASK);
1095
1096 r1 = inb(ioaddr + CNFG_IRR_583);
1097
1098 if(r1 & CNFG_IRR_ZWS)
1099 tp->mode_bits |= ZERO_WAIT_STATE_8_BIT;
1100
1101 if(tp->board_id & BOARD_16BIT)
1102 {
1103 r1 = inb(ioaddr + CNFG_LAAR_584);
1104
1105 if(r1 & CNFG_LAAR_ZWS)
1106 tp->mode_bits |= ZERO_WAIT_STATE_16_BIT;
1107 }
1108
1109 /* Get 584 Media Menu */
1110 tp->media_menu = 14;
1111 r1 = inb(ioaddr + CNFG_IRR_583);
1112
1113 tp->mode_bits &= 0xf8ff; /* (~CNFG_INTERFACE_TYPE_MASK) */
1114 if((tp->board_id & TOKEN_MEDIA) == TOKEN_MEDIA)
1115 {
1116 /* Get Advanced Features */
1117 if(((r1 & 0x6) >> 1) == 0x3)
1118 tp->media_type |= MEDIA_UTP_16;
1119 else
1120 {
1121 if(((r1 & 0x6) >> 1) == 0x2)
1122 tp->media_type |= MEDIA_STP_16;
1123 else
1124 {
1125 if(((r1 & 0x6) >> 1) == 0x1)
1126 tp->media_type |= MEDIA_UTP_4;
1127
1128 else
1129 tp->media_type |= MEDIA_STP_4;
1130 }
1131 }
1132
1133 r1 = inb(ioaddr + CNFG_GP2);
1134 if(!(r1 & 0x2) ) /* GP2_ETRD */
1135 tp->mode_bits |= EARLY_TOKEN_REL;
1136
1137 /* see if the chip is corrupted
1138 if(smctr_read_584_chksum(ioaddr))
1139 {
1140 printk(KERN_ERR "%s: EEPROM Checksum Failure\n", dev->name);
1141 free_irq(dev->irq, dev);
1142 goto out2;
1143 }
1144 */
1145 }
1146
1147 return 0;
1148
1149out2:
1150 release_region(ioaddr, SMCTR_IO_EXTENT);
1151out:
1152 return err;
1153}
1154
1155static int __init smctr_get_boardid(struct net_device *dev, int mca)
1156{
1157 struct net_local *tp = netdev_priv(dev);
1158 int ioaddr = dev->base_addr;
1159 __u8 r, r1, IdByte;
1160 __u16 BoardIdMask;
1161
1162 tp->board_id = BoardIdMask = 0;
1163
1164 if(mca)
1165 {
1166 BoardIdMask |= (MICROCHANNEL+INTERFACE_CHIP+TOKEN_MEDIA+PAGED_RAM+BOARD_16BIT);
1167 tp->extra_info |= (INTERFACE_594_CHIP+RAM_SIZE_64K+NIC_825_BIT+ALTERNATE_IRQ_BIT+SLOT_16BIT);
1168 }
1169 else
1170 {
1171 BoardIdMask|=(INTERFACE_CHIP+TOKEN_MEDIA+PAGED_RAM+BOARD_16BIT);
1172 tp->extra_info |= (INTERFACE_584_CHIP + RAM_SIZE_64K
1173 + NIC_825_BIT + ALTERNATE_IRQ_BIT);
1174 }
1175
1176 if(!mca)
1177 {
1178 r = inb(ioaddr + BID_REG_1);
1179 r &= 0x0c;
1180 outb(r, ioaddr + BID_REG_1);
1181 r = inb(ioaddr + BID_REG_1);
1182
1183 if(r & BID_SIXTEEN_BIT_BIT)
1184 {
1185 tp->extra_info |= SLOT_16BIT;
1186 tp->adapter_bus = BUS_ISA16_TYPE;
1187 }
1188 else
1189 tp->adapter_bus = BUS_ISA8_TYPE;
1190 }
1191 else
1192 tp->adapter_bus = BUS_MCA_TYPE;
1193
1194 /* Get Board Id Byte */
1195 IdByte = inb(ioaddr + BID_BOARD_ID_BYTE);
1196
1197 /* if Major version > 1.0 then
1198 * return;
1199 */
1200 if(IdByte & 0xF8)
1201 return -1;
1202
1203 r1 = inb(ioaddr + BID_REG_1);
1204 r1 &= BID_ICR_MASK;
1205 r1 |= BID_OTHER_BIT;
1206
1207 outb(r1, ioaddr + BID_REG_1);
1208 r1 = inb(ioaddr + BID_REG_3);
1209
1210 r1 &= BID_EAR_MASK;
1211 r1 |= BID_ENGR_PAGE;
1212
1213 outb(r1, ioaddr + BID_REG_3);
1214 r1 = inb(ioaddr + BID_REG_1);
1215 r1 &= BID_ICR_MASK;
1216 r1 |= (BID_RLA | BID_OTHER_BIT);
1217
1218 outb(r1, ioaddr + BID_REG_1);
1219
1220 r1 = inb(ioaddr + BID_REG_1);
1221 while(r1 & BID_RECALL_DONE_MASK)
1222 r1 = inb(ioaddr + BID_REG_1);
1223
1224 r = inb(ioaddr + BID_LAR_0 + BID_REG_6);
1225
1226 /* clear chip rev bits */
1227 tp->extra_info &= ~CHIP_REV_MASK;
1228 tp->extra_info |= ((r & BID_EEPROM_CHIP_REV_MASK) << 6);
1229
1230 r1 = inb(ioaddr + BID_REG_1);
1231 r1 &= BID_ICR_MASK;
1232 r1 |= BID_OTHER_BIT;
1233
1234 outb(r1, ioaddr + BID_REG_1);
1235 r1 = inb(ioaddr + BID_REG_3);
1236
1237 r1 &= BID_EAR_MASK;
1238 r1 |= BID_EA6;
1239
1240 outb(r1, ioaddr + BID_REG_3);
1241 r1 = inb(ioaddr + BID_REG_1);
1242
1243 r1 &= BID_ICR_MASK;
1244 r1 |= BID_RLA;
1245
1246 outb(r1, ioaddr + BID_REG_1);
1247 r1 = inb(ioaddr + BID_REG_1);
1248
1249 while(r1 & BID_RECALL_DONE_MASK)
1250 r1 = inb(ioaddr + BID_REG_1);
1251
1252 return BoardIdMask;
1253}
1254
1255static int smctr_get_group_address(struct net_device *dev)
1256{
1257 smctr_issue_read_word_cmd(dev, RW_INDIVIDUAL_GROUP_ADDR);
1258
1259 return smctr_wait_cmd(dev);
1260}
1261
1262static int smctr_get_functional_address(struct net_device *dev)
1263{
1264 smctr_issue_read_word_cmd(dev, RW_FUNCTIONAL_ADDR);
1265
1266 return smctr_wait_cmd(dev);
1267}
1268
1269/* Calculate number of Non-MAC receive BDB's and data buffers.
1270 * This function must simulate allocateing shared memory exactly
1271 * as the allocate_shared_memory function above.
1272 */
1273static unsigned int smctr_get_num_rx_bdbs(struct net_device *dev)
1274{
1275 struct net_local *tp = netdev_priv(dev);
1276 unsigned int mem_used = 0;
1277
1278 /* Allocate System Control Blocks. */
1279 mem_used += sizeof(SCGBlock);
1280
1281 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1282 mem_used += sizeof(SCLBlock);
1283
1284 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1285 mem_used += sizeof(ACBlock) * tp->num_acbs;
1286
1287 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1288 mem_used += sizeof(ISBlock);
1289
1290 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1291 mem_used += MISC_DATA_SIZE;
1292
1293 /* Allocate transmit FCB's. */
1294 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1295
1296 mem_used += sizeof(FCBlock) * tp->num_tx_fcbs[MAC_QUEUE];
1297 mem_used += sizeof(FCBlock) * tp->num_tx_fcbs[NON_MAC_QUEUE];
1298 mem_used += sizeof(FCBlock) * tp->num_tx_fcbs[BUG_QUEUE];
1299
1300 /* Allocate transmit BDBs. */
1301 mem_used += sizeof(BDBlock) * tp->num_tx_bdbs[MAC_QUEUE];
1302 mem_used += sizeof(BDBlock) * tp->num_tx_bdbs[NON_MAC_QUEUE];
1303 mem_used += sizeof(BDBlock) * tp->num_tx_bdbs[BUG_QUEUE];
1304
1305 /* Allocate receive FCBs. */
1306 mem_used += sizeof(FCBlock) * tp->num_rx_fcbs[MAC_QUEUE];
1307 mem_used += sizeof(FCBlock) * tp->num_rx_fcbs[NON_MAC_QUEUE];
1308
1309 /* Allocate receive BDBs. */
1310 mem_used += sizeof(BDBlock) * tp->num_rx_bdbs[MAC_QUEUE];
1311
1312 /* Allocate MAC transmit buffers.
1313 * MAC transmit buffers don't have to be on an ODD Boundary.
1314 */
1315 mem_used += tp->tx_buff_size[MAC_QUEUE];
1316
1317 /* Allocate BUG transmit buffers. */
1318 mem_used += tp->tx_buff_size[BUG_QUEUE];
1319
1320 /* Allocate MAC receive data buffers.
1321 * MAC receive buffers don't have to be on a 256 byte boundary.
1322 */
1323 mem_used += RX_DATA_BUFFER_SIZE * tp->num_rx_bdbs[MAC_QUEUE];
1324
1325 /* Allocate Non-MAC transmit buffers.
1326 * For maximum Netware performance, put Tx Buffers on
1327 * ODD Boundary,and then restore malloc to Even Boundrys.
1328 */
1329 mem_used += 1L;
1330 mem_used += tp->tx_buff_size[NON_MAC_QUEUE];
1331 mem_used += 1L;
1332
1333 /* CALCULATE NUMBER OF NON-MAC RX BDB'S
1334 * AND NON-MAC RX DATA BUFFERS
1335 *
1336 * Make sure the mem_used offset at this point is the
1337 * same as in allocate_shared memory or the following
1338 * boundary adjustment will be incorrect (i.e. not allocating
1339 * the non-mac receive buffers above cannot change the 256
1340 * byte offset).
1341 *
1342 * Since this cannot be guaranteed, adding the full 256 bytes
1343 * to the amount of shared memory used at this point will guaranteed
1344 * that the rx data buffers do not overflow shared memory.
1345 */
1346 mem_used += 0x100;
1347
1348 return (0xffff - mem_used) / (RX_DATA_BUFFER_SIZE + sizeof(BDBlock));
1349}
1350
1351static int smctr_get_physical_drop_number(struct net_device *dev)
1352{
1353 smctr_issue_read_word_cmd(dev, RW_PHYSICAL_DROP_NUMBER);
1354
1355 return smctr_wait_cmd(dev);
1356}
1357
1358static __u8 * smctr_get_rx_pointer(struct net_device *dev, short queue)
1359{
1360 struct net_local *tp = netdev_priv(dev);
1361 BDBlock *bdb;
1362
1363 bdb = (BDBlock *)((__u32)tp->ram_access
1364 + (__u32)(tp->rx_fcb_curr[queue]->trc_bdb_ptr));
1365
1366 tp->rx_fcb_curr[queue]->bdb_ptr = bdb;
1367
1368 return (__u8 *)bdb->data_block_ptr;
1369}
1370
1371static int smctr_get_station_id(struct net_device *dev)
1372{
1373 smctr_issue_read_word_cmd(dev, RW_INDIVIDUAL_MAC_ADDRESS);
1374
1375 return smctr_wait_cmd(dev);
1376}
1377
1378/*
1379 * Get the current statistics. This may be called with the card open
1380 * or closed.
1381 */
1382static struct net_device_stats *smctr_get_stats(struct net_device *dev)
1383{
1384 struct net_local *tp = netdev_priv(dev);
1385
1386 return (struct net_device_stats *)&tp->MacStat;
1387}
1388
1389static FCBlock *smctr_get_tx_fcb(struct net_device *dev, __u16 queue,
1390 __u16 bytes_count)
1391{
1392 struct net_local *tp = netdev_priv(dev);
1393 FCBlock *pFCB;
1394 BDBlock *pbdb;
1395 unsigned short alloc_size;
1396 unsigned short *temp;
1397
1398 if(smctr_debug > 20)
1399 printk(KERN_DEBUG "smctr_get_tx_fcb\n");
1400
1401 /* check if there is enough FCB blocks */
1402 if(tp->num_tx_fcbs_used[queue] >= tp->num_tx_fcbs[queue])
1403 return (FCBlock *)(-1L);
1404
1405 /* round off the input pkt size to the nearest even number */
1406 alloc_size = (bytes_count + 1) & 0xfffe;
1407
1408 /* check if enough mem */
1409 if((tp->tx_buff_used[queue] + alloc_size) > tp->tx_buff_size[queue])
1410 return (FCBlock *)(-1L);
1411
1412 /* check if past the end ;
1413 * if exactly enough mem to end of ring, alloc from front.
1414 * this avoids update of curr when curr = end
1415 */
1416 if(((unsigned long)(tp->tx_buff_curr[queue]) + alloc_size)
1417 >= (unsigned long)(tp->tx_buff_end[queue]))
1418 {
1419 /* check if enough memory from ring head */
1420 alloc_size = alloc_size +
1421 (__u16)((__u32)tp->tx_buff_end[queue]
1422 - (__u32)tp->tx_buff_curr[queue]);
1423
1424 if((tp->tx_buff_used[queue] + alloc_size)
1425 > tp->tx_buff_size[queue])
1426 {
1427 return (FCBlock *)(-1L);
1428 }
1429
1430 /* ring wrap */
1431 tp->tx_buff_curr[queue] = tp->tx_buff_head[queue];
1432 }
1433
1434 tp->tx_buff_used[queue] += alloc_size;
1435 tp->num_tx_fcbs_used[queue]++;
1436 tp->tx_fcb_curr[queue]->frame_length = bytes_count;
1437 tp->tx_fcb_curr[queue]->memory_alloc = alloc_size;
1438 temp = tp->tx_buff_curr[queue];
1439 tp->tx_buff_curr[queue]
1440 = (__u16 *)((__u32)temp + (__u32)((bytes_count + 1) & 0xfffe));
1441
1442 pbdb = tp->tx_fcb_curr[queue]->bdb_ptr;
1443 pbdb->buffer_length = bytes_count;
1444 pbdb->data_block_ptr = temp;
1445 pbdb->trc_data_block_ptr = TRC_POINTER(temp);
1446
1447 pFCB = tp->tx_fcb_curr[queue];
1448 tp->tx_fcb_curr[queue] = tp->tx_fcb_curr[queue]->next_ptr;
1449
1450 return pFCB;
1451}
1452
1453static int smctr_get_upstream_neighbor_addr(struct net_device *dev)
1454{
1455 smctr_issue_read_word_cmd(dev, RW_UPSTREAM_NEIGHBOR_ADDRESS);
1456
1457 return smctr_wait_cmd(dev);
1458}
1459
1460static int smctr_hardware_send_packet(struct net_device *dev,
1461 struct net_local *tp)
1462{
1463 struct tr_statistics *tstat = &tp->MacStat;
1464 struct sk_buff *skb;
1465 FCBlock *fcb;
1466
1467 if(smctr_debug > 10)
1468 printk(KERN_DEBUG"%s: smctr_hardware_send_packet\n", dev->name);
1469
1470 if(tp->status != OPEN)
1471 return -1;
1472
1473 if(tp->monitor_state_ready != 1)
1474 return -1;
1475
1476 for(;;)
1477 {
1478 /* Send first buffer from queue */
1479 skb = skb_dequeue(&tp->SendSkbQueue);
1480 if(skb == NULL)
1481 return -1;
1482
1483 tp->QueueSkb++;
1484
1485 if(skb->len < SMC_HEADER_SIZE || skb->len > tp->max_packet_size)
1486 return -1;
1487
1488 smctr_enable_16bit(dev);
1489 smctr_set_page(dev, (__u8 *)tp->ram_access);
1490
1491 if((fcb = smctr_get_tx_fcb(dev, NON_MAC_QUEUE, skb->len))
1492 == (FCBlock *)(-1L))
1493 {
1494 smctr_disable_16bit(dev);
1495 return -1;
1496 }
1497
1498 smctr_tx_move_frame(dev, skb,
1499 (__u8 *)fcb->bdb_ptr->data_block_ptr, skb->len);
1500
1501 smctr_set_page(dev, (__u8 *)fcb);
1502
1503 smctr_trc_send_packet(dev, fcb, NON_MAC_QUEUE);
1504 dev_kfree_skb(skb);
1505
1506 tstat->tx_packets++;
1507
1508 smctr_disable_16bit(dev);
1509 }
1510
1511 return 0;
1512}
1513
1514static int smctr_init_acbs(struct net_device *dev)
1515{
1516 struct net_local *tp = netdev_priv(dev);
1517 unsigned int i;
1518 ACBlock *acb;
1519
1520 if(smctr_debug > 10)
1521 printk(KERN_DEBUG "%s: smctr_init_acbs\n", dev->name);
1522
1523 acb = tp->acb_head;
1524 acb->cmd_done_status = (ACB_COMMAND_DONE | ACB_COMMAND_SUCCESSFUL);
1525 acb->cmd_info = ACB_CHAIN_END;
1526 acb->cmd = 0;
1527 acb->subcmd = 0;
1528 acb->data_offset_lo = 0;
1529 acb->data_offset_hi = 0;
1530 acb->next_ptr
1531 = (ACBlock *)(((char *)acb) + sizeof(ACBlock));
1532 acb->trc_next_ptr = TRC_POINTER(acb->next_ptr);
1533
1534 for(i = 1; i < tp->num_acbs; i++)
1535 {
1536 acb = acb->next_ptr;
1537 acb->cmd_done_status
1538 = (ACB_COMMAND_DONE | ACB_COMMAND_SUCCESSFUL);
1539 acb->cmd_info = ACB_CHAIN_END;
1540 acb->cmd = 0;
1541 acb->subcmd = 0;
1542 acb->data_offset_lo = 0;
1543 acb->data_offset_hi = 0;
1544 acb->next_ptr
1545 = (ACBlock *)(((char *)acb) + sizeof(ACBlock));
1546 acb->trc_next_ptr = TRC_POINTER(acb->next_ptr);
1547 }
1548
1549 acb->next_ptr = tp->acb_head;
1550 acb->trc_next_ptr = TRC_POINTER(tp->acb_head);
1551 tp->acb_next = tp->acb_head->next_ptr;
1552 tp->acb_curr = tp->acb_head->next_ptr;
1553 tp->num_acbs_used = 0;
1554
1555 return 0;
1556}
1557
1558static int smctr_init_adapter(struct net_device *dev)
1559{
1560 struct net_local *tp = netdev_priv(dev);
1561 int err;
1562
1563 if(smctr_debug > 10)
1564 printk(KERN_DEBUG "%s: smctr_init_adapter\n", dev->name);
1565
1566 tp->status = CLOSED;
1567 tp->page_offset_mask = (tp->ram_usable * 1024) - 1;
1568 skb_queue_head_init(&tp->SendSkbQueue);
1569 tp->QueueSkb = MAX_TX_QUEUE;
1570
1571 if(!(tp->group_address_0 & 0x0080))
1572 tp->group_address_0 |= 0x00C0;
1573
1574 if(!(tp->functional_address_0 & 0x00C0))
1575 tp->functional_address_0 |= 0x00C0;
1576
1577 tp->functional_address[0] &= 0xFF7F;
1578
1579 if(tp->authorized_function_classes == 0)
1580 tp->authorized_function_classes = 0x7FFF;
1581
1582 if(tp->authorized_access_priority == 0)
1583 tp->authorized_access_priority = 0x06;
1584
1585 smctr_disable_bic_int(dev);
1586 smctr_set_trc_reset(dev->base_addr);
1587
1588 smctr_enable_16bit(dev);
1589 smctr_set_page(dev, (__u8 *)tp->ram_access);
1590
1591 if(smctr_checksum_firmware(dev))
1592 {
1593 printk(KERN_ERR "%s: Previously loaded firmware is missing\n",dev->name);
1594 return -ENOENT;
1595 }
1596
1597 if((err = smctr_ram_memory_test(dev)))
1598 {
1599 printk(KERN_ERR "%s: RAM memory test failed.\n", dev->name);
1600 return -EIO;
1601 }
1602
1603 smctr_set_rx_look_ahead(dev);
1604 smctr_load_node_addr(dev);
1605
1606 /* Initialize adapter for Internal Self Test. */
1607 smctr_reset_adapter(dev);
1608 if((err = smctr_init_card_real(dev)))
1609 {
1610 printk(KERN_ERR "%s: Initialization of card failed (%d)\n",
1611 dev->name, err);
1612 return -EINVAL;
1613 }
1614
1615 /* This routine clobbers the TRC's internal registers. */
1616 if((err = smctr_internal_self_test(dev)))
1617 {
1618 printk(KERN_ERR "%s: Card failed internal self test (%d)\n",
1619 dev->name, err);
1620 return -EINVAL;
1621 }
1622
1623 /* Re-Initialize adapter's internal registers */
1624 smctr_reset_adapter(dev);
1625 if((err = smctr_init_card_real(dev)))
1626 {
1627 printk(KERN_ERR "%s: Initialization of card failed (%d)\n",
1628 dev->name, err);
1629 return -EINVAL;
1630 }
1631
1632 smctr_enable_bic_int(dev);
1633
1634 if((err = smctr_issue_enable_int_cmd(dev, TRC_INTERRUPT_ENABLE_MASK)))
1635 return err;
1636
1637 smctr_disable_16bit(dev);
1638
1639 return 0;
1640}
1641
1642static int smctr_init_card_real(struct net_device *dev)
1643{
1644 struct net_local *tp = netdev_priv(dev);
1645 int err = 0;
1646
1647 if(smctr_debug > 10)
1648 printk(KERN_DEBUG "%s: smctr_init_card_real\n", dev->name);
1649
1650 tp->sh_mem_used = 0;
1651 tp->num_acbs = NUM_OF_ACBS;
1652
1653 /* Range Check Max Packet Size */
1654 if(tp->max_packet_size < 256)
1655 tp->max_packet_size = 256;
1656 else
1657 {
1658 if(tp->max_packet_size > NON_MAC_TX_BUFFER_MEMORY)
1659 tp->max_packet_size = NON_MAC_TX_BUFFER_MEMORY;
1660 }
1661
1662 tp->num_of_tx_buffs = (NON_MAC_TX_BUFFER_MEMORY
1663 / tp->max_packet_size) - 1;
1664
1665 if(tp->num_of_tx_buffs > NUM_NON_MAC_TX_FCBS)
1666 tp->num_of_tx_buffs = NUM_NON_MAC_TX_FCBS;
1667 else
1668 {
1669 if(tp->num_of_tx_buffs == 0)
1670 tp->num_of_tx_buffs = 1;
1671 }
1672
1673 /* Tx queue constants */
1674 tp->num_tx_fcbs [BUG_QUEUE] = NUM_BUG_TX_FCBS;
1675 tp->num_tx_bdbs [BUG_QUEUE] = NUM_BUG_TX_BDBS;
1676 tp->tx_buff_size [BUG_QUEUE] = BUG_TX_BUFFER_MEMORY;
1677 tp->tx_buff_used [BUG_QUEUE] = 0;
1678 tp->tx_queue_status [BUG_QUEUE] = NOT_TRANSMITING;
1679
1680 tp->num_tx_fcbs [MAC_QUEUE] = NUM_MAC_TX_FCBS;
1681 tp->num_tx_bdbs [MAC_QUEUE] = NUM_MAC_TX_BDBS;
1682 tp->tx_buff_size [MAC_QUEUE] = MAC_TX_BUFFER_MEMORY;
1683 tp->tx_buff_used [MAC_QUEUE] = 0;
1684 tp->tx_queue_status [MAC_QUEUE] = NOT_TRANSMITING;
1685
1686 tp->num_tx_fcbs [NON_MAC_QUEUE] = NUM_NON_MAC_TX_FCBS;
1687 tp->num_tx_bdbs [NON_MAC_QUEUE] = NUM_NON_MAC_TX_BDBS;
1688 tp->tx_buff_size [NON_MAC_QUEUE] = NON_MAC_TX_BUFFER_MEMORY;
1689 tp->tx_buff_used [NON_MAC_QUEUE] = 0;
1690 tp->tx_queue_status [NON_MAC_QUEUE] = NOT_TRANSMITING;
1691
1692 /* Receive Queue Constants */
1693 tp->num_rx_fcbs[MAC_QUEUE] = NUM_MAC_RX_FCBS;
1694 tp->num_rx_bdbs[MAC_QUEUE] = NUM_MAC_RX_BDBS;
1695
1696 if(tp->extra_info & CHIP_REV_MASK)
1697 tp->num_rx_fcbs[NON_MAC_QUEUE] = 78; /* 825 Rev. XE */
1698 else
1699 tp->num_rx_fcbs[NON_MAC_QUEUE] = 7; /* 825 Rev. XD */
1700
1701 tp->num_rx_bdbs[NON_MAC_QUEUE] = smctr_get_num_rx_bdbs(dev);
1702
1703 smctr_alloc_shared_memory(dev);
1704 smctr_init_shared_memory(dev);
1705
1706 if((err = smctr_issue_init_timers_cmd(dev)))
1707 return err;
1708
1709 if((err = smctr_issue_init_txrx_cmd(dev)))
1710 {
1711 printk(KERN_ERR "%s: Hardware failure\n", dev->name);
1712 return err;
1713 }
1714
1715 return 0;
1716}
1717
1718static int smctr_init_rx_bdbs(struct net_device *dev)
1719{
1720 struct net_local *tp = netdev_priv(dev);
1721 unsigned int i, j;
1722 BDBlock *bdb;
1723 __u16 *buf;
1724
1725 if(smctr_debug > 10)
1726 printk(KERN_DEBUG "%s: smctr_init_rx_bdbs\n", dev->name);
1727
1728 for(i = 0; i < NUM_RX_QS_USED; i++)
1729 {
1730 bdb = tp->rx_bdb_head[i];
1731 buf = tp->rx_buff_head[i];
1732 bdb->info = (BDB_CHAIN_END | BDB_NO_WARNING);
1733 bdb->buffer_length = RX_DATA_BUFFER_SIZE;
1734 bdb->next_ptr = (BDBlock *)(((char *)bdb) + sizeof(BDBlock));
1735 bdb->data_block_ptr = buf;
1736 bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1737
1738 if(i == NON_MAC_QUEUE)
1739 bdb->trc_data_block_ptr = RX_BUFF_TRC_POINTER(buf);
1740 else
1741 bdb->trc_data_block_ptr = TRC_POINTER(buf);
1742
1743 for(j = 1; j < tp->num_rx_bdbs[i]; j++)
1744 {
1745 bdb->next_ptr->back_ptr = bdb;
1746 bdb = bdb->next_ptr;
1747 buf = (__u16 *)((char *)buf + RX_DATA_BUFFER_SIZE);
1748 bdb->info = (BDB_NOT_CHAIN_END | BDB_NO_WARNING);
1749 bdb->buffer_length = RX_DATA_BUFFER_SIZE;
1750 bdb->next_ptr = (BDBlock *)(((char *)bdb) + sizeof(BDBlock));
1751 bdb->data_block_ptr = buf;
1752 bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1753
1754 if(i == NON_MAC_QUEUE)
1755 bdb->trc_data_block_ptr = RX_BUFF_TRC_POINTER(buf);
1756 else
1757 bdb->trc_data_block_ptr = TRC_POINTER(buf);
1758 }
1759
1760 bdb->next_ptr = tp->rx_bdb_head[i];
1761 bdb->trc_next_ptr = TRC_POINTER(tp->rx_bdb_head[i]);
1762
1763 tp->rx_bdb_head[i]->back_ptr = bdb;
1764 tp->rx_bdb_curr[i] = tp->rx_bdb_head[i]->next_ptr;
1765 }
1766
1767 return 0;
1768}
1769
1770static int smctr_init_rx_fcbs(struct net_device *dev)
1771{
1772 struct net_local *tp = netdev_priv(dev);
1773 unsigned int i, j;
1774 FCBlock *fcb;
1775
1776 for(i = 0; i < NUM_RX_QS_USED; i++)
1777 {
1778 fcb = tp->rx_fcb_head[i];
1779 fcb->frame_status = 0;
1780 fcb->frame_length = 0;
1781 fcb->info = FCB_CHAIN_END;
1782 fcb->next_ptr = (FCBlock *)(((char*)fcb) + sizeof(FCBlock));
1783 if(i == NON_MAC_QUEUE)
1784 fcb->trc_next_ptr = RX_FCB_TRC_POINTER(fcb->next_ptr);
1785 else
1786 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1787
1788 for(j = 1; j < tp->num_rx_fcbs[i]; j++)
1789 {
1790 fcb->next_ptr->back_ptr = fcb;
1791 fcb = fcb->next_ptr;
1792 fcb->frame_status = 0;
1793 fcb->frame_length = 0;
1794 fcb->info = FCB_WARNING;
1795 fcb->next_ptr
1796 = (FCBlock *)(((char *)fcb) + sizeof(FCBlock));
1797
1798 if(i == NON_MAC_QUEUE)
1799 fcb->trc_next_ptr
1800 = RX_FCB_TRC_POINTER(fcb->next_ptr);
1801 else
1802 fcb->trc_next_ptr
1803 = TRC_POINTER(fcb->next_ptr);
1804 }
1805
1806 fcb->next_ptr = tp->rx_fcb_head[i];
1807
1808 if(i == NON_MAC_QUEUE)
1809 fcb->trc_next_ptr = RX_FCB_TRC_POINTER(fcb->next_ptr);
1810 else
1811 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1812
1813 tp->rx_fcb_head[i]->back_ptr = fcb;
1814 tp->rx_fcb_curr[i] = tp->rx_fcb_head[i]->next_ptr;
1815 }
1816
1817 return 0;
1818}
1819
1820static int smctr_init_shared_memory(struct net_device *dev)
1821{
1822 struct net_local *tp = netdev_priv(dev);
1823 unsigned int i;
1824 __u32 *iscpb;
1825
1826 if(smctr_debug > 10)
1827 printk(KERN_DEBUG "%s: smctr_init_shared_memory\n", dev->name);
1828
1829 smctr_set_page(dev, (__u8 *)(unsigned int)tp->iscpb_ptr);
1830
1831 /* Initialize Initial System Configuration Point. (ISCP) */
1832 iscpb = (__u32 *)PAGE_POINTER(&tp->iscpb_ptr->trc_scgb_ptr);
1833 *iscpb = (__u32)(SWAP_WORDS(TRC_POINTER(tp->scgb_ptr)));
1834
1835 smctr_set_page(dev, (__u8 *)tp->ram_access);
1836
1837 /* Initialize System Configuration Pointers. (SCP) */
1838 tp->scgb_ptr->config = (SCGB_ADDRESS_POINTER_FORMAT
1839 | SCGB_MULTI_WORD_CONTROL | SCGB_DATA_FORMAT
1840 | SCGB_BURST_LENGTH);
1841
1842 tp->scgb_ptr->trc_sclb_ptr = TRC_POINTER(tp->sclb_ptr);
1843 tp->scgb_ptr->trc_acb_ptr = TRC_POINTER(tp->acb_head);
1844 tp->scgb_ptr->trc_isb_ptr = TRC_POINTER(tp->isb_ptr);
1845 tp->scgb_ptr->isbsiz = (sizeof(ISBlock)) - 2;
1846
1847 /* Initialize System Control Block. (SCB) */
1848 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_CMD_NOP;
1849 tp->sclb_ptr->iack_code = 0;
1850 tp->sclb_ptr->resume_control = 0;
1851 tp->sclb_ptr->int_mask_control = 0;
1852 tp->sclb_ptr->int_mask_state = 0;
1853
1854 /* Initialize Interrupt Status Block. (ISB) */
1855 for(i = 0; i < NUM_OF_INTERRUPTS; i++)
1856 {
1857 tp->isb_ptr->IStatus[i].IType = 0xf0;
1858 tp->isb_ptr->IStatus[i].ISubtype = 0;
1859 }
1860
1861 tp->current_isb_index = 0;
1862
1863 /* Initialize Action Command Block. (ACB) */
1864 smctr_init_acbs(dev);
1865
1866 /* Initialize transmit FCB's and BDB's. */
1867 smctr_link_tx_fcbs_to_bdbs(dev);
1868 smctr_init_tx_bdbs(dev);
1869 smctr_init_tx_fcbs(dev);
1870
1871 /* Initialize receive FCB's and BDB's. */
1872 smctr_init_rx_bdbs(dev);
1873 smctr_init_rx_fcbs(dev);
1874
1875 return 0;
1876}
1877
1878static int smctr_init_tx_bdbs(struct net_device *dev)
1879{
1880 struct net_local *tp = netdev_priv(dev);
1881 unsigned int i, j;
1882 BDBlock *bdb;
1883
1884 for(i = 0; i < NUM_TX_QS_USED; i++)
1885 {
1886 bdb = tp->tx_bdb_head[i];
1887 bdb->info = (BDB_NOT_CHAIN_END | BDB_NO_WARNING);
1888 bdb->next_ptr = (BDBlock *)(((char *)bdb) + sizeof(BDBlock));
1889 bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1890
1891 for(j = 1; j < tp->num_tx_bdbs[i]; j++)
1892 {
1893 bdb->next_ptr->back_ptr = bdb;
1894 bdb = bdb->next_ptr;
1895 bdb->info = (BDB_NOT_CHAIN_END | BDB_NO_WARNING);
1896 bdb->next_ptr
1897 = (BDBlock *)(((char *)bdb) + sizeof( BDBlock)); bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1898 }
1899
1900 bdb->next_ptr = tp->tx_bdb_head[i];
1901 bdb->trc_next_ptr = TRC_POINTER(tp->tx_bdb_head[i]);
1902 tp->tx_bdb_head[i]->back_ptr = bdb;
1903 }
1904
1905 return 0;
1906}
1907
1908static int smctr_init_tx_fcbs(struct net_device *dev)
1909{
1910 struct net_local *tp = netdev_priv(dev);
1911 unsigned int i, j;
1912 FCBlock *fcb;
1913
1914 for(i = 0; i < NUM_TX_QS_USED; i++)
1915 {
1916 fcb = tp->tx_fcb_head[i];
1917 fcb->frame_status = 0;
1918 fcb->frame_length = 0;
1919 fcb->info = FCB_CHAIN_END;
1920 fcb->next_ptr = (FCBlock *)(((char *)fcb) + sizeof(FCBlock));
1921 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1922
1923 for(j = 1; j < tp->num_tx_fcbs[i]; j++)
1924 {
1925 fcb->next_ptr->back_ptr = fcb;
1926 fcb = fcb->next_ptr;
1927 fcb->frame_status = 0;
1928 fcb->frame_length = 0;
1929 fcb->info = FCB_CHAIN_END;
1930 fcb->next_ptr
1931 = (FCBlock *)(((char *)fcb) + sizeof(FCBlock));
1932 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1933 }
1934
1935 fcb->next_ptr = tp->tx_fcb_head[i];
1936 fcb->trc_next_ptr = TRC_POINTER(tp->tx_fcb_head[i]);
1937
1938 tp->tx_fcb_head[i]->back_ptr = fcb;
1939 tp->tx_fcb_end[i] = tp->tx_fcb_head[i]->next_ptr;
1940 tp->tx_fcb_curr[i] = tp->tx_fcb_head[i]->next_ptr;
1941 tp->num_tx_fcbs_used[i] = 0;
1942 }
1943
1944 return 0;
1945}
1946
1947static int smctr_internal_self_test(struct net_device *dev)
1948{
1949 struct net_local *tp = netdev_priv(dev);
1950 int err;
1951
1952 if((err = smctr_issue_test_internal_rom_cmd(dev)))
1953 return err;
1954
1955 if((err = smctr_wait_cmd(dev)))
1956 return err;
1957
1958 if(tp->acb_head->cmd_done_status & 0xff)
1959 return -1;
1960
1961 if((err = smctr_issue_test_hic_cmd(dev)))
1962 return err;
1963
1964 if((err = smctr_wait_cmd(dev)))
1965 return err;
1966
1967 if(tp->acb_head->cmd_done_status & 0xff)
1968 return -1;
1969
1970 if((err = smctr_issue_test_mac_reg_cmd(dev)))
1971 return err;
1972
1973 if((err = smctr_wait_cmd(dev)))
1974 return err;
1975
1976 if(tp->acb_head->cmd_done_status & 0xff)
1977 return -1;
1978
1979 return 0;
1980}
1981
1982/*
1983 * The typical workload of the driver: Handle the network interface interrupts.
1984 */
1985static irqreturn_t smctr_interrupt(int irq, void *dev_id)
1986{
1987 struct net_device *dev = dev_id;
1988 struct net_local *tp;
1989 int ioaddr;
1990 __u16 interrupt_unmask_bits = 0, interrupt_ack_code = 0xff00;
1991 __u16 err1, err = NOT_MY_INTERRUPT;
1992 __u8 isb_type, isb_subtype;
1993 __u16 isb_index;
1994
1995 ioaddr = dev->base_addr;
1996 tp = netdev_priv(dev);
1997
1998 if(tp->status == NOT_INITIALIZED)
1999 return IRQ_NONE;
2000
2001 spin_lock(&tp->lock);
2002
2003 smctr_disable_bic_int(dev);
2004 smctr_enable_16bit(dev);
2005
2006 smctr_clear_int(dev);
2007
2008 /* First read the LSB */
2009 while((tp->isb_ptr->IStatus[tp->current_isb_index].IType & 0xf0) == 0)
2010 {
2011 isb_index = tp->current_isb_index;
2012 isb_type = tp->isb_ptr->IStatus[isb_index].IType;
2013 isb_subtype = tp->isb_ptr->IStatus[isb_index].ISubtype;
2014
2015 (tp->current_isb_index)++;
2016 if(tp->current_isb_index == NUM_OF_INTERRUPTS)
2017 tp->current_isb_index = 0;
2018
2019 if(isb_type >= 0x10)
2020 {
2021 smctr_disable_16bit(dev);
2022 spin_unlock(&tp->lock);
2023 return IRQ_HANDLED;
2024 }
2025
2026 err = HARDWARE_FAILED;
2027 interrupt_ack_code = isb_index;
2028 tp->isb_ptr->IStatus[isb_index].IType |= 0xf0;
2029
2030 interrupt_unmask_bits |= (1 << (__u16)isb_type);
2031
2032 switch(isb_type)
2033 {
2034 case ISB_IMC_MAC_TYPE_3:
2035 smctr_disable_16bit(dev);
2036
2037 switch(isb_subtype)
2038 {
2039 case 0:
2040 tp->monitor_state = MS_MONITOR_FSM_INACTIVE;
2041 break;
2042
2043 case 1:
2044 tp->monitor_state = MS_REPEAT_BEACON_STATE;
2045 break;
2046
2047 case 2:
2048 tp->monitor_state = MS_REPEAT_CLAIM_TOKEN_STATE;
2049 break;
2050
2051 case 3:
2052 tp->monitor_state = MS_TRANSMIT_CLAIM_TOKEN_STATE; break;
2053
2054 case 4:
2055 tp->monitor_state = MS_STANDBY_MONITOR_STATE;
2056 break;
2057
2058 case 5:
2059 tp->monitor_state = MS_TRANSMIT_BEACON_STATE;
2060 break;
2061
2062 case 6:
2063 tp->monitor_state = MS_ACTIVE_MONITOR_STATE;
2064 break;
2065
2066 case 7:
2067 tp->monitor_state = MS_TRANSMIT_RING_PURGE_STATE;
2068 break;
2069
2070 case 8: /* diagnostic state */
2071 break;
2072
2073 case 9:
2074 tp->monitor_state = MS_BEACON_TEST_STATE;
2075 if(smctr_lobe_media_test(dev))
2076 {
2077 tp->ring_status_flags = RING_STATUS_CHANGED;
2078 tp->ring_status = AUTO_REMOVAL_ERROR;
2079 smctr_ring_status_chg(dev);
2080 smctr_bypass_state(dev);
2081 }
2082 else
2083 smctr_issue_insert_cmd(dev);
2084 break;
2085
2086 /* case 0x0a-0xff, illegal states */
2087 default:
2088 break;
2089 }
2090
2091 tp->ring_status_flags = MONITOR_STATE_CHANGED;
2092 err = smctr_ring_status_chg(dev);
2093
2094 smctr_enable_16bit(dev);
2095 break;
2096
2097 /* Type 0x02 - MAC Error Counters Interrupt
2098 * One or more MAC Error Counter is half full
2099 * MAC Error Counters
2100 * Lost_FR_Error_Counter
2101 * RCV_Congestion_Counter
2102 * FR_copied_Error_Counter
2103 * FREQ_Error_Counter
2104 * Token_Error_Counter
2105 * Line_Error_Counter
2106 * Internal_Error_Count
2107 */
2108 case ISB_IMC_MAC_ERROR_COUNTERS:
2109 /* Read 802.5 Error Counters */
2110 err = smctr_issue_read_ring_status_cmd(dev);
2111 break;
2112
2113 /* Type 0x04 - MAC Type 2 Interrupt
2114 * HOST needs to enqueue MAC Frame for transmission
2115 * SubType Bit 15 - RQ_INIT_PDU( Request Initialization) * Changed from RQ_INIT_PDU to
2116 * TRC_Status_Changed_Indicate
2117 */
2118 case ISB_IMC_MAC_TYPE_2:
2119 err = smctr_issue_read_ring_status_cmd(dev);
2120 break;
2121
2122
2123 /* Type 0x05 - TX Frame Interrupt (FI). */
2124 case ISB_IMC_TX_FRAME:
2125 /* BUG QUEUE for TRC stuck receive BUG */
2126 if(isb_subtype & TX_PENDING_PRIORITY_2)
2127 {
2128 if((err = smctr_tx_complete(dev, BUG_QUEUE)) != SUCCESS)
2129 break;
2130 }
2131
2132 /* NON-MAC frames only */
2133 if(isb_subtype & TX_PENDING_PRIORITY_1)
2134 {
2135 if((err = smctr_tx_complete(dev, NON_MAC_QUEUE)) != SUCCESS)
2136 break;
2137 }
2138
2139 /* MAC frames only */
2140 if(isb_subtype & TX_PENDING_PRIORITY_0)
2141 err = smctr_tx_complete(dev, MAC_QUEUE); break;
2142
2143 /* Type 0x06 - TX END OF QUEUE (FE) */
2144 case ISB_IMC_END_OF_TX_QUEUE:
2145 /* BUG queue */
2146 if(isb_subtype & TX_PENDING_PRIORITY_2)
2147 {
2148 /* ok to clear Receive FIFO overrun
2149 * imask send_BUG now completes.
2150 */
2151 interrupt_unmask_bits |= 0x800;
2152
2153 tp->tx_queue_status[BUG_QUEUE] = NOT_TRANSMITING;
2154 if((err = smctr_tx_complete(dev, BUG_QUEUE)) != SUCCESS)
2155 break;
2156 if((err = smctr_restart_tx_chain(dev, BUG_QUEUE)) != SUCCESS)
2157 break;
2158 }
2159
2160 /* NON-MAC queue only */
2161 if(isb_subtype & TX_PENDING_PRIORITY_1)
2162 {
2163 tp->tx_queue_status[NON_MAC_QUEUE] = NOT_TRANSMITING;
2164 if((err = smctr_tx_complete(dev, NON_MAC_QUEUE)) != SUCCESS)
2165 break;
2166 if((err = smctr_restart_tx_chain(dev, NON_MAC_QUEUE)) != SUCCESS)
2167 break;
2168 }
2169
2170 /* MAC queue only */
2171 if(isb_subtype & TX_PENDING_PRIORITY_0)
2172 {
2173 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
2174 if((err = smctr_tx_complete(dev, MAC_QUEUE)) != SUCCESS)
2175 break;
2176
2177 err = smctr_restart_tx_chain(dev, MAC_QUEUE);
2178 }
2179 break;
2180
2181 /* Type 0x07 - NON-MAC RX Resource Interrupt
2182 * Subtype bit 12 - (BW) BDB warning
2183 * Subtype bit 13 - (FW) FCB warning
2184 * Subtype bit 14 - (BE) BDB End of chain
2185 * Subtype bit 15 - (FE) FCB End of chain
2186 */
2187 case ISB_IMC_NON_MAC_RX_RESOURCE:
2188 tp->rx_fifo_overrun_count = 0;
2189 tp->receive_queue_number = NON_MAC_QUEUE;
2190 err1 = smctr_rx_frame(dev);
2191
2192 if(isb_subtype & NON_MAC_RX_RESOURCE_FE)
2193 {
2194 if((err = smctr_issue_resume_rx_fcb_cmd( dev, NON_MAC_QUEUE)) != SUCCESS) break;
2195
2196 if(tp->ptr_rx_fcb_overruns)
2197 (*tp->ptr_rx_fcb_overruns)++;
2198 }
2199
2200 if(isb_subtype & NON_MAC_RX_RESOURCE_BE)
2201 {
2202 if((err = smctr_issue_resume_rx_bdb_cmd( dev, NON_MAC_QUEUE)) != SUCCESS) break;
2203
2204 if(tp->ptr_rx_bdb_overruns)
2205 (*tp->ptr_rx_bdb_overruns)++;
2206 }
2207 err = err1;
2208 break;
2209
2210 /* Type 0x08 - MAC RX Resource Interrupt
2211 * Subtype bit 12 - (BW) BDB warning
2212 * Subtype bit 13 - (FW) FCB warning
2213 * Subtype bit 14 - (BE) BDB End of chain
2214 * Subtype bit 15 - (FE) FCB End of chain
2215 */
2216 case ISB_IMC_MAC_RX_RESOURCE:
2217 tp->receive_queue_number = MAC_QUEUE;
2218 err1 = smctr_rx_frame(dev);
2219
2220 if(isb_subtype & MAC_RX_RESOURCE_FE)
2221 {
2222 if((err = smctr_issue_resume_rx_fcb_cmd( dev, MAC_QUEUE)) != SUCCESS)
2223 break;
2224
2225 if(tp->ptr_rx_fcb_overruns)
2226 (*tp->ptr_rx_fcb_overruns)++;
2227 }
2228
2229 if(isb_subtype & MAC_RX_RESOURCE_BE)
2230 {
2231 if((err = smctr_issue_resume_rx_bdb_cmd( dev, MAC_QUEUE)) != SUCCESS)
2232 break;
2233
2234 if(tp->ptr_rx_bdb_overruns)
2235 (*tp->ptr_rx_bdb_overruns)++;
2236 }
2237 err = err1;
2238 break;
2239
2240 /* Type 0x09 - NON_MAC RX Frame Interrupt */
2241 case ISB_IMC_NON_MAC_RX_FRAME:
2242 tp->rx_fifo_overrun_count = 0;
2243 tp->receive_queue_number = NON_MAC_QUEUE;
2244 err = smctr_rx_frame(dev);
2245 break;
2246
2247 /* Type 0x0A - MAC RX Frame Interrupt */
2248 case ISB_IMC_MAC_RX_FRAME:
2249 tp->receive_queue_number = MAC_QUEUE;
2250 err = smctr_rx_frame(dev);
2251 break;
2252
2253 /* Type 0x0B - TRC status
2254 * TRC has encountered an error condition
2255 * subtype bit 14 - transmit FIFO underrun
2256 * subtype bit 15 - receive FIFO overrun
2257 */
2258 case ISB_IMC_TRC_FIFO_STATUS:
2259 if(isb_subtype & TRC_FIFO_STATUS_TX_UNDERRUN)
2260 {
2261 if(tp->ptr_tx_fifo_underruns)
2262 (*tp->ptr_tx_fifo_underruns)++;
2263 }
2264
2265 if(isb_subtype & TRC_FIFO_STATUS_RX_OVERRUN)
2266 {
2267 /* update overrun stuck receive counter
2268 * if >= 3, has to clear it by sending
2269 * back to back frames. We pick
2270 * DAT(duplicate address MAC frame)
2271 */
2272 tp->rx_fifo_overrun_count++;
2273
2274 if(tp->rx_fifo_overrun_count >= 3)
2275 {
2276 tp->rx_fifo_overrun_count = 0;
2277
2278 /* delay clearing fifo overrun
2279 * imask till send_BUG tx
2280 * complete posted
2281 */
2282 interrupt_unmask_bits &= (~0x800);
2283 printk(KERN_CRIT "Jay please send bug\n");// smctr_send_bug(dev);
2284 }
2285
2286 if(tp->ptr_rx_fifo_overruns)
2287 (*tp->ptr_rx_fifo_overruns)++;
2288 }
2289
2290 err = SUCCESS;
2291 break;
2292
2293 /* Type 0x0C - Action Command Status Interrupt
2294 * Subtype bit 14 - CB end of command chain (CE)
2295 * Subtype bit 15 - CB command interrupt (CI)
2296 */
2297 case ISB_IMC_COMMAND_STATUS:
2298 err = SUCCESS;
2299 if(tp->acb_head->cmd == ACB_CMD_HIC_NOP)
2300 {
2301 printk(KERN_ERR "i1\n");
2302 smctr_disable_16bit(dev);
2303
2304 /* XXXXXXXXXXXXXXXXX */
2305 /* err = UM_Interrupt(dev); */
2306
2307 smctr_enable_16bit(dev);
2308 }
2309 else
2310 {
2311 if((tp->acb_head->cmd
2312 == ACB_CMD_READ_TRC_STATUS) &&
2313 (tp->acb_head->subcmd
2314 == RW_TRC_STATUS_BLOCK))
2315 {
2316 if(tp->ptr_bcn_type)
2317 {
2318 *(tp->ptr_bcn_type)
2319 = (__u32)((SBlock *)tp->misc_command_data)->BCN_Type;
2320 }
2321
2322 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & ERROR_COUNTERS_CHANGED)
2323 {
2324 smctr_update_err_stats(dev);
2325 }
2326
2327 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & TI_NDIS_RING_STATUS_CHANGED)
2328 {
2329 tp->ring_status
2330 = ((SBlock*)tp->misc_command_data)->TI_NDIS_Ring_Status;
2331 smctr_disable_16bit(dev);
2332 err = smctr_ring_status_chg(dev);
2333 smctr_enable_16bit(dev);
2334 if((tp->ring_status & REMOVE_RECEIVED) &&
2335 (tp->config_word0 & NO_AUTOREMOVE))
2336 {
2337 smctr_issue_remove_cmd(dev);
2338 }
2339
2340 if(err != SUCCESS)
2341 {
2342 tp->acb_pending = 0;
2343 break;
2344 }
2345 }
2346
2347 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & UNA_CHANGED)
2348 {
2349 if(tp->ptr_una)
2350 {
2351 tp->ptr_una[0] = SWAP_BYTES(((SBlock *)tp->misc_command_data)->UNA[0]);
2352 tp->ptr_una[1] = SWAP_BYTES(((SBlock *)tp->misc_command_data)->UNA[1]);
2353 tp->ptr_una[2] = SWAP_BYTES(((SBlock *)tp->misc_command_data)->UNA[2]);
2354 }
2355
2356 }
2357
2358 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & READY_TO_SEND_RQ_INIT) {
2359 err = smctr_send_rq_init(dev);
2360 }
2361 }
2362 }
2363
2364 tp->acb_pending = 0;
2365 break;
2366
2367 /* Type 0x0D - MAC Type 1 interrupt
2368 * Subtype -- 00 FR_BCN received at S12
2369 * 01 FR_BCN received at S21
2370 * 02 FR_DAT(DA=MA, A<>0) received at S21
2371 * 03 TSM_EXP at S21
2372 * 04 FR_REMOVE received at S42
2373 * 05 TBR_EXP, BR_FLAG_SET at S42
2374 * 06 TBT_EXP at S53
2375 */
2376 case ISB_IMC_MAC_TYPE_1:
2377 if(isb_subtype > 8)
2378 {
2379 err = HARDWARE_FAILED;
2380 break;
2381 }
2382
2383 err = SUCCESS;
2384 switch(isb_subtype)
2385 {
2386 case 0:
2387 tp->join_state = JS_BYPASS_STATE;
2388 if(tp->status != CLOSED)
2389 {
2390 tp->status = CLOSED;
2391 err = smctr_status_chg(dev);
2392 }
2393 break;
2394
2395 case 1:
2396 tp->join_state = JS_LOBE_TEST_STATE;
2397 break;
2398
2399 case 2:
2400 tp->join_state = JS_DETECT_MONITOR_PRESENT_STATE;
2401 break;
2402
2403 case 3:
2404 tp->join_state = JS_AWAIT_NEW_MONITOR_STATE;
2405 break;
2406
2407 case 4:
2408 tp->join_state = JS_DUPLICATE_ADDRESS_TEST_STATE;
2409 break;
2410
2411 case 5:
2412 tp->join_state = JS_NEIGHBOR_NOTIFICATION_STATE;
2413 break;
2414
2415 case 6:
2416 tp->join_state = JS_REQUEST_INITIALIZATION_STATE;
2417 break;
2418
2419 case 7:
2420 tp->join_state = JS_JOIN_COMPLETE_STATE;
2421 tp->status = OPEN;
2422 err = smctr_status_chg(dev);
2423 break;
2424
2425 case 8:
2426 tp->join_state = JS_BYPASS_WAIT_STATE;
2427 break;
2428 }
2429 break ;
2430
2431 /* Type 0x0E - TRC Initialization Sequence Interrupt
2432 * Subtype -- 00-FF Initializatin sequence complete
2433 */
2434 case ISB_IMC_TRC_INTRNL_TST_STATUS:
2435 tp->status = INITIALIZED;
2436 smctr_disable_16bit(dev);
2437 err = smctr_status_chg(dev);
2438 smctr_enable_16bit(dev);
2439 break;
2440
2441 /* other interrupt types, illegal */
2442 default:
2443 break;
2444 }
2445
2446 if(err != SUCCESS)
2447 break;
2448 }
2449
2450 /* Checking the ack code instead of the unmask bits here is because :
2451 * while fixing the stuck receive, DAT frame are sent and mask off
2452 * FIFO overrun interrupt temporarily (interrupt_unmask_bits = 0)
2453 * but we still want to issue ack to ISB
2454 */
2455 if(!(interrupt_ack_code & 0xff00))
2456 smctr_issue_int_ack(dev, interrupt_ack_code, interrupt_unmask_bits);
2457
2458 smctr_disable_16bit(dev);
2459 smctr_enable_bic_int(dev);
2460 spin_unlock(&tp->lock);
2461
2462 return IRQ_HANDLED;
2463}
2464
2465static int smctr_issue_enable_int_cmd(struct net_device *dev,
2466 __u16 interrupt_enable_mask)
2467{
2468 struct net_local *tp = netdev_priv(dev);
2469 int err;
2470
2471 if((err = smctr_wait_while_cbusy(dev)))
2472 return err;
2473
2474 tp->sclb_ptr->int_mask_control = interrupt_enable_mask;
2475 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_CMD_CLEAR_INTERRUPT_MASK;
2476
2477 smctr_set_ctrl_attention(dev);
2478
2479 return 0;
2480}
2481
2482static int smctr_issue_int_ack(struct net_device *dev, __u16 iack_code, __u16 ibits)
2483{
2484 struct net_local *tp = netdev_priv(dev);
2485
2486 if(smctr_wait_while_cbusy(dev))
2487 return -1;
2488
2489 tp->sclb_ptr->int_mask_control = ibits;
2490 tp->sclb_ptr->iack_code = iack_code << 1; /* use the offset from base */ tp->sclb_ptr->resume_control = 0;
2491 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_IACK_CODE_VALID | SCLB_CMD_CLEAR_INTERRUPT_MASK;
2492
2493 smctr_set_ctrl_attention(dev);
2494
2495 return 0;
2496}
2497
2498static int smctr_issue_init_timers_cmd(struct net_device *dev)
2499{
2500 struct net_local *tp = netdev_priv(dev);
2501 unsigned int i;
2502 int err;
2503 __u16 *pTimer_Struc = (__u16 *)tp->misc_command_data;
2504
2505 if((err = smctr_wait_while_cbusy(dev)))
2506 return err;
2507
2508 if((err = smctr_wait_cmd(dev)))
2509 return err;
2510
2511 tp->config_word0 = THDREN | DMA_TRIGGER | USETPT | NO_AUTOREMOVE;
2512 tp->config_word1 = 0;
2513
2514 if((tp->media_type == MEDIA_STP_16) ||
2515 (tp->media_type == MEDIA_UTP_16) ||
2516 (tp->media_type == MEDIA_STP_16_UTP_16))
2517 {
2518 tp->config_word0 |= FREQ_16MB_BIT;
2519 }
2520
2521 if(tp->mode_bits & EARLY_TOKEN_REL)
2522 tp->config_word0 |= ETREN;
2523
2524 if(tp->mode_bits & LOOPING_MODE_MASK)
2525 tp->config_word0 |= RX_OWN_BIT;
2526 else
2527 tp->config_word0 &= ~RX_OWN_BIT;
2528
2529 if(tp->receive_mask & PROMISCUOUS_MODE)
2530 tp->config_word0 |= PROMISCUOUS_BIT;
2531 else
2532 tp->config_word0 &= ~PROMISCUOUS_BIT;
2533
2534 if(tp->receive_mask & ACCEPT_ERR_PACKETS)
2535 tp->config_word0 |= SAVBAD_BIT;
2536 else
2537 tp->config_word0 &= ~SAVBAD_BIT;
2538
2539 if(tp->receive_mask & ACCEPT_ATT_MAC_FRAMES)
2540 tp->config_word0 |= RXATMAC;
2541 else
2542 tp->config_word0 &= ~RXATMAC;
2543
2544 if(tp->receive_mask & ACCEPT_MULTI_PROM)
2545 tp->config_word1 |= MULTICAST_ADDRESS_BIT;
2546 else
2547 tp->config_word1 &= ~MULTICAST_ADDRESS_BIT;
2548
2549 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING_SPANNING)
2550 tp->config_word1 |= SOURCE_ROUTING_SPANNING_BITS;
2551 else
2552 {
2553 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING)
2554 tp->config_word1 |= SOURCE_ROUTING_EXPLORER_BIT;
2555 else
2556 tp->config_word1 &= ~SOURCE_ROUTING_SPANNING_BITS;
2557 }
2558
2559 if((tp->media_type == MEDIA_STP_16) ||
2560 (tp->media_type == MEDIA_UTP_16) ||
2561 (tp->media_type == MEDIA_STP_16_UTP_16))
2562 {
2563 tp->config_word1 |= INTERFRAME_SPACING_16;
2564 }
2565 else
2566 tp->config_word1 |= INTERFRAME_SPACING_4;
2567
2568 *pTimer_Struc++ = tp->config_word0;
2569 *pTimer_Struc++ = tp->config_word1;
2570
2571 if((tp->media_type == MEDIA_STP_4) ||
2572 (tp->media_type == MEDIA_UTP_4) ||
2573 (tp->media_type == MEDIA_STP_4_UTP_4))
2574 {
2575 *pTimer_Struc++ = 0x00FA; /* prescale */
2576 *pTimer_Struc++ = 0x2710; /* TPT_limit */
2577 *pTimer_Struc++ = 0x2710; /* TQP_limit */
2578 *pTimer_Struc++ = 0x0A28; /* TNT_limit */
2579 *pTimer_Struc++ = 0x3E80; /* TBT_limit */
2580 *pTimer_Struc++ = 0x3A98; /* TSM_limit */
2581 *pTimer_Struc++ = 0x1B58; /* TAM_limit */
2582 *pTimer_Struc++ = 0x00C8; /* TBR_limit */
2583 *pTimer_Struc++ = 0x07D0; /* TER_limit */
2584 *pTimer_Struc++ = 0x000A; /* TGT_limit */
2585 *pTimer_Struc++ = 0x1162; /* THT_limit */
2586 *pTimer_Struc++ = 0x07D0; /* TRR_limit */
2587 *pTimer_Struc++ = 0x1388; /* TVX_limit */
2588 *pTimer_Struc++ = 0x0000; /* reserved */
2589 }
2590 else
2591 {
2592 *pTimer_Struc++ = 0x03E8; /* prescale */
2593 *pTimer_Struc++ = 0x9C40; /* TPT_limit */
2594 *pTimer_Struc++ = 0x9C40; /* TQP_limit */
2595 *pTimer_Struc++ = 0x0A28; /* TNT_limit */
2596 *pTimer_Struc++ = 0x3E80; /* TBT_limit */
2597 *pTimer_Struc++ = 0x3A98; /* TSM_limit */
2598 *pTimer_Struc++ = 0x1B58; /* TAM_limit */
2599 *pTimer_Struc++ = 0x00C8; /* TBR_limit */
2600 *pTimer_Struc++ = 0x07D0; /* TER_limit */
2601 *pTimer_Struc++ = 0x000A; /* TGT_limit */
2602 *pTimer_Struc++ = 0x4588; /* THT_limit */
2603 *pTimer_Struc++ = 0x1F40; /* TRR_limit */
2604 *pTimer_Struc++ = 0x4E20; /* TVX_limit */
2605 *pTimer_Struc++ = 0x0000; /* reserved */
2606 }
2607
2608 /* Set node address. */
2609 *pTimer_Struc++ = dev->dev_addr[0] << 8
2610 | (dev->dev_addr[1] & 0xFF);
2611 *pTimer_Struc++ = dev->dev_addr[2] << 8
2612 | (dev->dev_addr[3] & 0xFF);
2613 *pTimer_Struc++ = dev->dev_addr[4] << 8
2614 | (dev->dev_addr[5] & 0xFF);
2615
2616 /* Set group address. */
2617 *pTimer_Struc++ = tp->group_address_0 << 8
2618 | tp->group_address_0 >> 8;
2619 *pTimer_Struc++ = tp->group_address[0] << 8
2620 | tp->group_address[0] >> 8;
2621 *pTimer_Struc++ = tp->group_address[1] << 8
2622 | tp->group_address[1] >> 8;
2623
2624 /* Set functional address. */
2625 *pTimer_Struc++ = tp->functional_address_0 << 8
2626 | tp->functional_address_0 >> 8;
2627 *pTimer_Struc++ = tp->functional_address[0] << 8
2628 | tp->functional_address[0] >> 8;
2629 *pTimer_Struc++ = tp->functional_address[1] << 8
2630 | tp->functional_address[1] >> 8;
2631
2632 /* Set Bit-Wise group address. */
2633 *pTimer_Struc++ = tp->bitwise_group_address[0] << 8
2634 | tp->bitwise_group_address[0] >> 8;
2635 *pTimer_Struc++ = tp->bitwise_group_address[1] << 8
2636 | tp->bitwise_group_address[1] >> 8;
2637
2638 /* Set ring number address. */
2639 *pTimer_Struc++ = tp->source_ring_number;
2640 *pTimer_Struc++ = tp->target_ring_number;
2641
2642 /* Physical drop number. */
2643 *pTimer_Struc++ = (unsigned short)0;
2644 *pTimer_Struc++ = (unsigned short)0;
2645
2646 /* Product instance ID. */
2647 for(i = 0; i < 9; i++)
2648 *pTimer_Struc++ = (unsigned short)0;
2649
2650 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_INIT_TRC_TIMERS, 0);
2651
2652 return err;
2653}
2654
2655static int smctr_issue_init_txrx_cmd(struct net_device *dev)
2656{
2657 struct net_local *tp = netdev_priv(dev);
2658 unsigned int i;
2659 int err;
2660 void **txrx_ptrs = (void *)tp->misc_command_data;
2661
2662 if((err = smctr_wait_while_cbusy(dev)))
2663 return err;
2664
2665 if((err = smctr_wait_cmd(dev)))
2666 {
2667 printk(KERN_ERR "%s: Hardware failure\n", dev->name);
2668 return err;
2669 }
2670
2671 /* Initialize Transmit Queue Pointers that are used, to point to
2672 * a single FCB.
2673 */
2674 for(i = 0; i < NUM_TX_QS_USED; i++)
2675 *txrx_ptrs++ = (void *)TRC_POINTER(tp->tx_fcb_head[i]);
2676
2677 /* Initialize Transmit Queue Pointers that are NOT used to ZERO. */
2678 for(; i < MAX_TX_QS; i++)
2679 *txrx_ptrs++ = (void *)0;
2680
2681 /* Initialize Receive Queue Pointers (MAC and Non-MAC) that are
2682 * used, to point to a single FCB and a BDB chain of buffers.
2683 */
2684 for(i = 0; i < NUM_RX_QS_USED; i++)
2685 {
2686 *txrx_ptrs++ = (void *)TRC_POINTER(tp->rx_fcb_head[i]);
2687 *txrx_ptrs++ = (void *)TRC_POINTER(tp->rx_bdb_head[i]);
2688 }
2689
2690 /* Initialize Receive Queue Pointers that are NOT used to ZERO. */
2691 for(; i < MAX_RX_QS; i++)
2692 {
2693 *txrx_ptrs++ = (void *)0;
2694 *txrx_ptrs++ = (void *)0;
2695 }
2696
2697 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_INIT_TX_RX, 0);
2698
2699 return err;
2700}
2701
2702static int smctr_issue_insert_cmd(struct net_device *dev)
2703{
2704 int err;
2705
2706 err = smctr_setup_single_cmd(dev, ACB_CMD_INSERT, ACB_SUB_CMD_NOP);
2707
2708 return err;
2709}
2710
2711static int smctr_issue_read_ring_status_cmd(struct net_device *dev)
2712{
2713 int err;
2714
2715 if((err = smctr_wait_while_cbusy(dev)))
2716 return err;
2717
2718 if((err = smctr_wait_cmd(dev)))
2719 return err;
2720
2721 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_READ_TRC_STATUS,
2722 RW_TRC_STATUS_BLOCK);
2723
2724 return err;
2725}
2726
2727static int smctr_issue_read_word_cmd(struct net_device *dev, __u16 aword_cnt)
2728{
2729 int err;
2730
2731 if((err = smctr_wait_while_cbusy(dev)))
2732 return err;
2733
2734 if((err = smctr_wait_cmd(dev)))
2735 return err;
2736
2737 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_MCT_READ_VALUE,
2738 aword_cnt);
2739
2740 return err;
2741}
2742
2743static int smctr_issue_remove_cmd(struct net_device *dev)
2744{
2745 struct net_local *tp = netdev_priv(dev);
2746 int err;
2747
2748 if((err = smctr_wait_while_cbusy(dev)))
2749 return err;
2750
2751 tp->sclb_ptr->resume_control = 0;
2752 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_CMD_REMOVE;
2753
2754 smctr_set_ctrl_attention(dev);
2755
2756 return 0;
2757}
2758
2759static int smctr_issue_resume_acb_cmd(struct net_device *dev)
2760{
2761 struct net_local *tp = netdev_priv(dev);
2762 int err;
2763
2764 if((err = smctr_wait_while_cbusy(dev)))
2765 return err;
2766
2767 tp->sclb_ptr->resume_control = SCLB_RC_ACB;
2768 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_RESUME_CONTROL_VALID;
2769
2770 tp->acb_pending = 1;
2771
2772 smctr_set_ctrl_attention(dev);
2773
2774 return 0;
2775}
2776
2777static int smctr_issue_resume_rx_bdb_cmd(struct net_device *dev, __u16 queue)
2778{
2779 struct net_local *tp = netdev_priv(dev);
2780 int err;
2781
2782 if((err = smctr_wait_while_cbusy(dev)))
2783 return err;
2784
2785 if(queue == MAC_QUEUE)
2786 tp->sclb_ptr->resume_control = SCLB_RC_RX_MAC_BDB;
2787 else
2788 tp->sclb_ptr->resume_control = SCLB_RC_RX_NON_MAC_BDB;
2789
2790 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_RESUME_CONTROL_VALID;
2791
2792 smctr_set_ctrl_attention(dev);
2793
2794 return 0;
2795}
2796
2797static int smctr_issue_resume_rx_fcb_cmd(struct net_device *dev, __u16 queue)
2798{
2799 struct net_local *tp = netdev_priv(dev);
2800
2801 if(smctr_debug > 10)
2802 printk(KERN_DEBUG "%s: smctr_issue_resume_rx_fcb_cmd\n", dev->name);
2803
2804 if(smctr_wait_while_cbusy(dev))
2805 return -1;
2806
2807 if(queue == MAC_QUEUE)
2808 tp->sclb_ptr->resume_control = SCLB_RC_RX_MAC_FCB;
2809 else
2810 tp->sclb_ptr->resume_control = SCLB_RC_RX_NON_MAC_FCB;
2811
2812 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_RESUME_CONTROL_VALID;
2813
2814 smctr_set_ctrl_attention(dev);
2815
2816 return 0;
2817}
2818
2819static int smctr_issue_resume_tx_fcb_cmd(struct net_device *dev, __u16 queue)
2820{
2821 struct net_local *tp = netdev_priv(dev);
2822
2823 if(smctr_debug > 10)
2824 printk(KERN_DEBUG "%s: smctr_issue_resume_tx_fcb_cmd\n", dev->name);
2825
2826 if(smctr_wait_while_cbusy(dev))
2827 return -1;
2828
2829 tp->sclb_ptr->resume_control = (SCLB_RC_TFCB0 << queue);
2830 tp->sclb_ptr->valid_command = SCLB_RESUME_CONTROL_VALID | SCLB_VALID;
2831
2832 smctr_set_ctrl_attention(dev);
2833
2834 return 0;
2835}
2836
2837static int smctr_issue_test_internal_rom_cmd(struct net_device *dev)
2838{
2839 int err;
2840
2841 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2842 TRC_INTERNAL_ROM_TEST);
2843
2844 return err;
2845}
2846
2847static int smctr_issue_test_hic_cmd(struct net_device *dev)
2848{
2849 int err;
2850
2851 err = smctr_setup_single_cmd(dev, ACB_CMD_HIC_TEST,
2852 TRC_HOST_INTERFACE_REG_TEST);
2853
2854 return err;
2855}
2856
2857static int smctr_issue_test_mac_reg_cmd(struct net_device *dev)
2858{
2859 int err;
2860
2861 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2862 TRC_MAC_REGISTERS_TEST);
2863
2864 return err;
2865}
2866
2867static int smctr_issue_trc_loopback_cmd(struct net_device *dev)
2868{
2869 int err;
2870
2871 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2872 TRC_INTERNAL_LOOPBACK);
2873
2874 return err;
2875}
2876
2877static int smctr_issue_tri_loopback_cmd(struct net_device *dev)
2878{
2879 int err;
2880
2881 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2882 TRC_TRI_LOOPBACK);
2883
2884 return err;
2885}
2886
2887static int smctr_issue_write_byte_cmd(struct net_device *dev,
2888 short aword_cnt, void *byte)
2889{
2890 struct net_local *tp = netdev_priv(dev);
2891 unsigned int iword, ibyte;
2892 int err;
2893
2894 if((err = smctr_wait_while_cbusy(dev)))
2895 return err;
2896
2897 if((err = smctr_wait_cmd(dev)))
2898 return err;
2899
2900 for(iword = 0, ibyte = 0; iword < (unsigned int)(aword_cnt & 0xff);
2901 iword++, ibyte += 2)
2902 {
2903 tp->misc_command_data[iword] = (*((__u8 *)byte + ibyte) << 8)
2904 | (*((__u8 *)byte + ibyte + 1));
2905 }
2906
2907 return smctr_setup_single_cmd_w_data(dev, ACB_CMD_MCT_WRITE_VALUE,
2908 aword_cnt);
2909}
2910
2911static int smctr_issue_write_word_cmd(struct net_device *dev,
2912 short aword_cnt, void *word)
2913{
2914 struct net_local *tp = netdev_priv(dev);
2915 unsigned int i, err;
2916
2917 if((err = smctr_wait_while_cbusy(dev)))
2918 return err;
2919
2920 if((err = smctr_wait_cmd(dev)))
2921 return err;
2922
2923 for(i = 0; i < (unsigned int)(aword_cnt & 0xff); i++)
2924 tp->misc_command_data[i] = *((__u16 *)word + i);
2925
2926 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_MCT_WRITE_VALUE,
2927 aword_cnt);
2928
2929 return err;
2930}
2931
2932static int smctr_join_complete_state(struct net_device *dev)
2933{
2934 int err;
2935
2936 err = smctr_setup_single_cmd(dev, ACB_CMD_CHANGE_JOIN_STATE,
2937 JS_JOIN_COMPLETE_STATE);
2938
2939 return err;
2940}
2941
2942static int smctr_link_tx_fcbs_to_bdbs(struct net_device *dev)
2943{
2944 struct net_local *tp = netdev_priv(dev);
2945 unsigned int i, j;
2946 FCBlock *fcb;
2947 BDBlock *bdb;
2948
2949 for(i = 0; i < NUM_TX_QS_USED; i++)
2950 {
2951 fcb = tp->tx_fcb_head[i];
2952 bdb = tp->tx_bdb_head[i];
2953
2954 for(j = 0; j < tp->num_tx_fcbs[i]; j++)
2955 {
2956 fcb->bdb_ptr = bdb;
2957 fcb->trc_bdb_ptr = TRC_POINTER(bdb);
2958 fcb = (FCBlock *)((char *)fcb + sizeof(FCBlock));
2959 bdb = (BDBlock *)((char *)bdb + sizeof(BDBlock));
2960 }
2961 }
2962
2963 return 0;
2964}
2965
2966static int smctr_load_firmware(struct net_device *dev)
2967{
2968 struct net_local *tp = netdev_priv(dev);
2969 const struct firmware *fw;
2970 __u16 i, checksum = 0;
2971 int err = 0;
2972
2973 if(smctr_debug > 10)
2974 printk(KERN_DEBUG "%s: smctr_load_firmware\n", dev->name);
2975
2976 if (request_firmware(&fw, "tr_smctr.bin", &dev->dev)) {
2977 printk(KERN_ERR "%s: firmware not found\n", dev->name);
2978 return UCODE_NOT_PRESENT;
2979 }
2980
2981 tp->num_of_tx_buffs = 4;
2982 tp->mode_bits |= UMAC;
2983 tp->receive_mask = 0;
2984 tp->max_packet_size = 4177;
2985
2986 /* Can only upload the firmware once per adapter reset. */
2987 if (tp->microcode_version != 0) {
2988 err = (UCODE_PRESENT);
2989 goto out;
2990 }
2991
2992 /* Verify the firmware exists and is there in the right amount. */
2993 if (!fw->data ||
2994 (*(fw->data + UCODE_VERSION_OFFSET) < UCODE_VERSION))
2995 {
2996 err = (UCODE_NOT_PRESENT);
2997 goto out;
2998 }
2999
3000 /* UCODE_SIZE is not included in Checksum. */
3001 for(i = 0; i < *((__u16 *)(fw->data + UCODE_SIZE_OFFSET)); i += 2)
3002 checksum += *((__u16 *)(fw->data + 2 + i));
3003 if (checksum) {
3004 err = (UCODE_NOT_PRESENT);
3005 goto out;
3006 }
3007
3008 /* At this point we have a valid firmware image, lets kick it on up. */
3009 smctr_enable_adapter_ram(dev);
3010 smctr_enable_16bit(dev);
3011 smctr_set_page(dev, (__u8 *)tp->ram_access);
3012
3013 if((smctr_checksum_firmware(dev)) ||
3014 (*(fw->data + UCODE_VERSION_OFFSET) > tp->microcode_version))
3015 {
3016 smctr_enable_adapter_ctrl_store(dev);
3017
3018 /* Zero out ram space for firmware. */
3019 for(i = 0; i < CS_RAM_SIZE; i += 2)
3020 *((__u16 *)(tp->ram_access + i)) = 0;
3021
3022 smctr_decode_firmware(dev, fw);
3023
3024 tp->microcode_version = *(fw->data + UCODE_VERSION_OFFSET); *((__u16 *)(tp->ram_access + CS_RAM_VERSION_OFFSET))
3025 = (tp->microcode_version << 8);
3026 *((__u16 *)(tp->ram_access + CS_RAM_CHECKSUM_OFFSET))
3027 = ~(tp->microcode_version << 8) + 1;
3028
3029 smctr_disable_adapter_ctrl_store(dev);
3030
3031 if(smctr_checksum_firmware(dev))
3032 err = HARDWARE_FAILED;
3033 }
3034 else
3035 err = UCODE_PRESENT;
3036
3037 smctr_disable_16bit(dev);
3038 out:
3039 release_firmware(fw);
3040 return err;
3041}
3042
3043static int smctr_load_node_addr(struct net_device *dev)
3044{
3045 int ioaddr = dev->base_addr;
3046 unsigned int i;
3047 __u8 r;
3048
3049 for(i = 0; i < 6; i++)
3050 {
3051 r = inb(ioaddr + LAR0 + i);
3052 dev->dev_addr[i] = (char)r;
3053 }
3054 dev->addr_len = 6;
3055
3056 return 0;
3057}
3058
3059/* Lobe Media Test.
3060 * During the transmission of the initial 1500 lobe media MAC frames,
3061 * the phase lock loop in the 805 chip may lock, and then un-lock, causing
3062 * the 825 to go into a PURGE state. When performing a PURGE, the MCT
3063 * microcode will not transmit any frames given to it by the host, and
3064 * will consequently cause a timeout.
3065 *
3066 * NOTE 1: If the monitor_state is MS_BEACON_TEST_STATE, all transmit
3067 * queues other than the one used for the lobe_media_test should be
3068 * disabled.!?
3069 *
3070 * NOTE 2: If the monitor_state is MS_BEACON_TEST_STATE and the receive_mask
3071 * has any multi-cast or promiscuous bits set, the receive_mask needs to
3072 * be changed to clear the multi-cast or promiscuous mode bits, the lobe_test
3073 * run, and then the receive mask set back to its original value if the test
3074 * is successful.
3075 */
3076static int smctr_lobe_media_test(struct net_device *dev)
3077{
3078 struct net_local *tp = netdev_priv(dev);
3079 unsigned int i, perror = 0;
3080 unsigned short saved_rcv_mask;
3081
3082 if(smctr_debug > 10)
3083 printk(KERN_DEBUG "%s: smctr_lobe_media_test\n", dev->name);
3084
3085 /* Clear receive mask for lobe test. */
3086 saved_rcv_mask = tp->receive_mask;
3087 tp->receive_mask = 0;
3088
3089 smctr_chg_rx_mask(dev);
3090
3091 /* Setup the lobe media test. */
3092 smctr_lobe_media_test_cmd(dev);
3093 if(smctr_wait_cmd(dev))
3094 goto err;
3095
3096 /* Tx lobe media test frames. */
3097 for(i = 0; i < 1500; ++i)
3098 {
3099 if(smctr_send_lobe_media_test(dev))
3100 {
3101 if(perror)
3102 goto err;
3103 else
3104 {
3105 perror = 1;
3106 if(smctr_lobe_media_test_cmd(dev))
3107 goto err;
3108 }
3109 }
3110 }
3111
3112 if(smctr_send_dat(dev))
3113 {
3114 if(smctr_send_dat(dev))
3115 goto err;
3116 }
3117
3118 /* Check if any frames received during test. */
3119 if((tp->rx_fcb_curr[MAC_QUEUE]->frame_status) ||
3120 (tp->rx_fcb_curr[NON_MAC_QUEUE]->frame_status))
3121 goto err;
3122
3123 /* Set receive mask to "Promisc" mode. */
3124 tp->receive_mask = saved_rcv_mask;
3125
3126 smctr_chg_rx_mask(dev);
3127
3128 return 0;
3129err:
3130 smctr_reset_adapter(dev);
3131 tp->status = CLOSED;
3132 return LOBE_MEDIA_TEST_FAILED;
3133}
3134
3135static int smctr_lobe_media_test_cmd(struct net_device *dev)
3136{
3137 struct net_local *tp = netdev_priv(dev);
3138 int err;
3139
3140 if(smctr_debug > 10)
3141 printk(KERN_DEBUG "%s: smctr_lobe_media_test_cmd\n", dev->name);
3142
3143 /* Change to lobe media test state. */
3144 if(tp->monitor_state != MS_BEACON_TEST_STATE)
3145 {
3146 smctr_lobe_media_test_state(dev);
3147 if(smctr_wait_cmd(dev))
3148 {
3149 printk(KERN_ERR "Lobe Failed test state\n");
3150 return LOBE_MEDIA_TEST_FAILED;
3151 }
3152 }
3153
3154 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
3155 TRC_LOBE_MEDIA_TEST);
3156
3157 return err;
3158}
3159
3160static int smctr_lobe_media_test_state(struct net_device *dev)
3161{
3162 int err;
3163
3164 err = smctr_setup_single_cmd(dev, ACB_CMD_CHANGE_JOIN_STATE,
3165 JS_LOBE_TEST_STATE);
3166
3167 return err;
3168}
3169
3170static int smctr_make_8025_hdr(struct net_device *dev,
3171 MAC_HEADER *rmf, MAC_HEADER *tmf, __u16 ac_fc)
3172{
3173 tmf->ac = MSB(ac_fc); /* msb is access control */
3174 tmf->fc = LSB(ac_fc); /* lsb is frame control */
3175
3176 tmf->sa[0] = dev->dev_addr[0];
3177 tmf->sa[1] = dev->dev_addr[1];
3178 tmf->sa[2] = dev->dev_addr[2];
3179 tmf->sa[3] = dev->dev_addr[3];
3180 tmf->sa[4] = dev->dev_addr[4];
3181 tmf->sa[5] = dev->dev_addr[5];
3182
3183 switch(tmf->vc)
3184 {
3185 /* Send RQ_INIT to RPS */
3186 case RQ_INIT:
3187 tmf->da[0] = 0xc0;
3188 tmf->da[1] = 0x00;
3189 tmf->da[2] = 0x00;
3190 tmf->da[3] = 0x00;
3191 tmf->da[4] = 0x00;
3192 tmf->da[5] = 0x02;
3193 break;
3194
3195 /* Send RPT_TX_FORWARD to CRS */
3196 case RPT_TX_FORWARD:
3197 tmf->da[0] = 0xc0;
3198 tmf->da[1] = 0x00;
3199 tmf->da[2] = 0x00;
3200 tmf->da[3] = 0x00;
3201 tmf->da[4] = 0x00;
3202 tmf->da[5] = 0x10;
3203 break;
3204
3205 /* Everything else goes to sender */
3206 default:
3207 tmf->da[0] = rmf->sa[0];
3208 tmf->da[1] = rmf->sa[1];
3209 tmf->da[2] = rmf->sa[2];
3210 tmf->da[3] = rmf->sa[3];
3211 tmf->da[4] = rmf->sa[4];
3212 tmf->da[5] = rmf->sa[5];
3213 break;
3214 }
3215
3216 return 0;
3217}
3218
3219static int smctr_make_access_pri(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3220{
3221 struct net_local *tp = netdev_priv(dev);
3222
3223 tsv->svi = AUTHORIZED_ACCESS_PRIORITY;
3224 tsv->svl = S_AUTHORIZED_ACCESS_PRIORITY;
3225
3226 tsv->svv[0] = MSB(tp->authorized_access_priority);
3227 tsv->svv[1] = LSB(tp->authorized_access_priority);
3228
3229 return 0;
3230}
3231
3232static int smctr_make_addr_mod(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3233{
3234 tsv->svi = ADDRESS_MODIFER;
3235 tsv->svl = S_ADDRESS_MODIFER;
3236
3237 tsv->svv[0] = 0;
3238 tsv->svv[1] = 0;
3239
3240 return 0;
3241}
3242
3243static int smctr_make_auth_funct_class(struct net_device *dev,
3244 MAC_SUB_VECTOR *tsv)
3245{
3246 struct net_local *tp = netdev_priv(dev);
3247
3248 tsv->svi = AUTHORIZED_FUNCTION_CLASS;
3249 tsv->svl = S_AUTHORIZED_FUNCTION_CLASS;
3250
3251 tsv->svv[0] = MSB(tp->authorized_function_classes);
3252 tsv->svv[1] = LSB(tp->authorized_function_classes);
3253
3254 return 0;
3255}
3256
3257static int smctr_make_corr(struct net_device *dev,
3258 MAC_SUB_VECTOR *tsv, __u16 correlator)
3259{
3260 tsv->svi = CORRELATOR;
3261 tsv->svl = S_CORRELATOR;
3262
3263 tsv->svv[0] = MSB(correlator);
3264 tsv->svv[1] = LSB(correlator);
3265
3266 return 0;
3267}
3268
3269static int smctr_make_funct_addr(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3270{
3271 struct net_local *tp = netdev_priv(dev);
3272
3273 smctr_get_functional_address(dev);
3274
3275 tsv->svi = FUNCTIONAL_ADDRESS;
3276 tsv->svl = S_FUNCTIONAL_ADDRESS;
3277
3278 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3279 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3280
3281 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3282 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3283
3284 return 0;
3285}
3286
3287static int smctr_make_group_addr(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3288{
3289 struct net_local *tp = netdev_priv(dev);
3290
3291 smctr_get_group_address(dev);
3292
3293 tsv->svi = GROUP_ADDRESS;
3294 tsv->svl = S_GROUP_ADDRESS;
3295
3296 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3297 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3298
3299 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3300 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3301
3302 /* Set Group Address Sub-vector to all zeros if only the
3303 * Group Address/Functional Address Indicator is set.
3304 */
3305 if(tsv->svv[0] == 0x80 && tsv->svv[1] == 0x00 &&
3306 tsv->svv[2] == 0x00 && tsv->svv[3] == 0x00)
3307 tsv->svv[0] = 0x00;
3308
3309 return 0;
3310}
3311
3312static int smctr_make_phy_drop_num(struct net_device *dev,
3313 MAC_SUB_VECTOR *tsv)
3314{
3315 struct net_local *tp = netdev_priv(dev);
3316
3317 smctr_get_physical_drop_number(dev);
3318
3319 tsv->svi = PHYSICAL_DROP;
3320 tsv->svl = S_PHYSICAL_DROP;
3321
3322 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3323 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3324
3325 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3326 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3327
3328 return 0;
3329}
3330
3331static int smctr_make_product_id(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3332{
3333 int i;
3334
3335 tsv->svi = PRODUCT_INSTANCE_ID;
3336 tsv->svl = S_PRODUCT_INSTANCE_ID;
3337
3338 for(i = 0; i < 18; i++)
3339 tsv->svv[i] = 0xF0;
3340
3341 return 0;
3342}
3343
3344static int smctr_make_station_id(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3345{
3346 struct net_local *tp = netdev_priv(dev);
3347
3348 smctr_get_station_id(dev);
3349
3350 tsv->svi = STATION_IDENTIFER;
3351 tsv->svl = S_STATION_IDENTIFER;
3352
3353 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3354 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3355
3356 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3357 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3358
3359 tsv->svv[4] = MSB(tp->misc_command_data[2]);
3360 tsv->svv[5] = LSB(tp->misc_command_data[2]);
3361
3362 return 0;
3363}
3364
3365static int smctr_make_ring_station_status(struct net_device *dev,
3366 MAC_SUB_VECTOR * tsv)
3367{
3368 tsv->svi = RING_STATION_STATUS;
3369 tsv->svl = S_RING_STATION_STATUS;
3370
3371 tsv->svv[0] = 0;
3372 tsv->svv[1] = 0;
3373 tsv->svv[2] = 0;
3374 tsv->svv[3] = 0;
3375 tsv->svv[4] = 0;
3376 tsv->svv[5] = 0;
3377
3378 return 0;
3379}
3380
3381static int smctr_make_ring_station_version(struct net_device *dev,
3382 MAC_SUB_VECTOR *tsv)
3383{
3384 struct net_local *tp = netdev_priv(dev);
3385
3386 tsv->svi = RING_STATION_VERSION_NUMBER;
3387 tsv->svl = S_RING_STATION_VERSION_NUMBER;
3388
3389 tsv->svv[0] = 0xe2; /* EBCDIC - S */
3390 tsv->svv[1] = 0xd4; /* EBCDIC - M */
3391 tsv->svv[2] = 0xc3; /* EBCDIC - C */
3392 tsv->svv[3] = 0x40; /* EBCDIC - */
3393 tsv->svv[4] = 0xe5; /* EBCDIC - V */
3394 tsv->svv[5] = 0xF0 + (tp->microcode_version >> 4);
3395 tsv->svv[6] = 0xF0 + (tp->microcode_version & 0x0f);
3396 tsv->svv[7] = 0x40; /* EBCDIC - */
3397 tsv->svv[8] = 0xe7; /* EBCDIC - X */
3398
3399 if(tp->extra_info & CHIP_REV_MASK)
3400 tsv->svv[9] = 0xc5; /* EBCDIC - E */
3401 else
3402 tsv->svv[9] = 0xc4; /* EBCDIC - D */
3403
3404 return 0;
3405}
3406
3407static int smctr_make_tx_status_code(struct net_device *dev,
3408 MAC_SUB_VECTOR *tsv, __u16 tx_fstatus)
3409{
3410 tsv->svi = TRANSMIT_STATUS_CODE;
3411 tsv->svl = S_TRANSMIT_STATUS_CODE;
3412
3413 tsv->svv[0] = ((tx_fstatus & 0x0100 >> 6) | IBM_PASS_SOURCE_ADDR);
3414
3415 /* Stripped frame status of Transmitted Frame */
3416 tsv->svv[1] = tx_fstatus & 0xff;
3417
3418 return 0;
3419}
3420
3421static int smctr_make_upstream_neighbor_addr(struct net_device *dev,
3422 MAC_SUB_VECTOR *tsv)
3423{
3424 struct net_local *tp = netdev_priv(dev);
3425
3426 smctr_get_upstream_neighbor_addr(dev);
3427
3428 tsv->svi = UPSTREAM_NEIGHBOR_ADDRESS;
3429 tsv->svl = S_UPSTREAM_NEIGHBOR_ADDRESS;
3430
3431 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3432 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3433
3434 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3435 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3436
3437 tsv->svv[4] = MSB(tp->misc_command_data[2]);
3438 tsv->svv[5] = LSB(tp->misc_command_data[2]);
3439
3440 return 0;
3441}
3442
3443static int smctr_make_wrap_data(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3444{
3445 tsv->svi = WRAP_DATA;
3446 tsv->svl = S_WRAP_DATA;
3447
3448 return 0;
3449}
3450
3451/*
3452 * Open/initialize the board. This is called sometime after
3453 * booting when the 'ifconfig' program is run.
3454 *
3455 * This routine should set everything up anew at each open, even
3456 * registers that "should" only need to be set once at boot, so that
3457 * there is non-reboot way to recover if something goes wrong.
3458 */
3459static int smctr_open(struct net_device *dev)
3460{
3461 int err;
3462
3463 if(smctr_debug > 10)
3464 printk(KERN_DEBUG "%s: smctr_open\n", dev->name);
3465
3466 err = smctr_init_adapter(dev);
3467 if(err < 0)
3468 return err;
3469
3470 return err;
3471}
3472
3473/* Interrupt driven open of Token card. */
3474static int smctr_open_tr(struct net_device *dev)
3475{
3476 struct net_local *tp = netdev_priv(dev);
3477 unsigned long flags;
3478 int err;
3479
3480 if(smctr_debug > 10)
3481 printk(KERN_DEBUG "%s: smctr_open_tr\n", dev->name);
3482
3483 /* Now we can actually open the adapter. */
3484 if(tp->status == OPEN)
3485 return 0;
3486 if(tp->status != INITIALIZED)
3487 return -1;
3488
3489 /* FIXME: it would work a lot better if we masked the irq sources
3490 on the card here, then we could skip the locking and poll nicely */
3491 spin_lock_irqsave(&tp->lock, flags);
3492
3493 smctr_set_page(dev, (__u8 *)tp->ram_access);
3494
3495 if((err = smctr_issue_resume_rx_fcb_cmd(dev, (short)MAC_QUEUE)))
3496 goto out;
3497
3498 if((err = smctr_issue_resume_rx_bdb_cmd(dev, (short)MAC_QUEUE)))
3499 goto out;
3500
3501 if((err = smctr_issue_resume_rx_fcb_cmd(dev, (short)NON_MAC_QUEUE)))
3502 goto out;
3503
3504 if((err = smctr_issue_resume_rx_bdb_cmd(dev, (short)NON_MAC_QUEUE)))
3505 goto out;
3506
3507 tp->status = CLOSED;
3508
3509 /* Insert into the Ring or Enter Loopback Mode. */
3510 if((tp->mode_bits & LOOPING_MODE_MASK) == LOOPBACK_MODE_1)
3511 {
3512 tp->status = CLOSED;
3513
3514 if(!(err = smctr_issue_trc_loopback_cmd(dev)))
3515 {
3516 if(!(err = smctr_wait_cmd(dev)))
3517 tp->status = OPEN;
3518 }
3519
3520 smctr_status_chg(dev);
3521 }
3522 else
3523 {
3524 if((tp->mode_bits & LOOPING_MODE_MASK) == LOOPBACK_MODE_2)
3525 {
3526 tp->status = CLOSED;
3527 if(!(err = smctr_issue_tri_loopback_cmd(dev)))
3528 {
3529 if(!(err = smctr_wait_cmd(dev)))
3530 tp->status = OPEN;
3531 }
3532
3533 smctr_status_chg(dev);
3534 }
3535 else
3536 {
3537 if((tp->mode_bits & LOOPING_MODE_MASK)
3538 == LOOPBACK_MODE_3)
3539 {
3540 tp->status = CLOSED;
3541 if(!(err = smctr_lobe_media_test_cmd(dev)))
3542 {
3543 if(!(err = smctr_wait_cmd(dev)))
3544 tp->status = OPEN;
3545 }
3546 smctr_status_chg(dev);
3547 }
3548 else
3549 {
3550 if(!(err = smctr_lobe_media_test(dev)))
3551 err = smctr_issue_insert_cmd(dev);
3552 else
3553 {
3554 if(err == LOBE_MEDIA_TEST_FAILED)
3555 printk(KERN_WARNING "%s: Lobe Media Test Failure - Check cable?\n", dev->name);
3556 }
3557 }
3558 }
3559 }
3560
3561out:
3562 spin_unlock_irqrestore(&tp->lock, flags);
3563
3564 return err;
3565}
3566
3567/* Check for a network adapter of this type,
3568 * and return device structure if one exists.
3569 */
3570struct net_device __init *smctr_probe(int unit)
3571{
3572 struct net_device *dev = alloc_trdev(sizeof(struct net_local));
3573 static const unsigned ports[] = {
3574 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, 0x300,
3575 0x320, 0x340, 0x360, 0x380, 0
3576 };
3577 const unsigned *port;
3578 int err = 0;
3579
3580 if (!dev)
3581 return ERR_PTR(-ENOMEM);
3582
3583 if (unit >= 0) {
3584 sprintf(dev->name, "tr%d", unit);
3585 netdev_boot_setup_check(dev);
3586 }
3587
3588 if (dev->base_addr > 0x1ff) /* Check a single specified location. */
3589 err = smctr_probe1(dev, dev->base_addr);
3590 else if(dev->base_addr != 0) /* Don't probe at all. */
3591 err =-ENXIO;
3592 else {
3593 for (port = ports; *port; port++) {
3594 err = smctr_probe1(dev, *port);
3595 if (!err)
3596 break;
3597 }
3598 }
3599 if (err)
3600 goto out;
3601 err = register_netdev(dev);
3602 if (err)
3603 goto out1;
3604 return dev;
3605out1:
3606#ifdef CONFIG_MCA_LEGACY
3607 { struct net_local *tp = netdev_priv(dev);
3608 if (tp->slot_num)
3609 mca_mark_as_unused(tp->slot_num);
3610 }
3611#endif
3612 release_region(dev->base_addr, SMCTR_IO_EXTENT);
3613 free_irq(dev->irq, dev);
3614out:
3615 free_netdev(dev);
3616 return ERR_PTR(err);
3617}
3618
3619static const struct net_device_ops smctr_netdev_ops = {
3620 .ndo_open = smctr_open,
3621 .ndo_stop = smctr_close,
3622 .ndo_start_xmit = smctr_send_packet,
3623 .ndo_tx_timeout = smctr_timeout,
3624 .ndo_get_stats = smctr_get_stats,
3625 .ndo_set_rx_mode = smctr_set_multicast_list,
3626};
3627
3628static int __init smctr_probe1(struct net_device *dev, int ioaddr)
3629{
3630 static unsigned version_printed;
3631 struct net_local *tp = netdev_priv(dev);
3632 int err;
3633 __u32 *ram;
3634
3635 if(smctr_debug && version_printed++ == 0)
3636 printk(version);
3637
3638 spin_lock_init(&tp->lock);
3639 dev->base_addr = ioaddr;
3640
3641 /* Actually detect an adapter now. */
3642 err = smctr_chk_isa(dev);
3643 if(err < 0)
3644 {
3645 if ((err = smctr_chk_mca(dev)) < 0) {
3646 err = -ENODEV;
3647 goto out;
3648 }
3649 }
3650
3651 tp = netdev_priv(dev);
3652 dev->mem_start = tp->ram_base;
3653 dev->mem_end = dev->mem_start + 0x10000;
3654 ram = (__u32 *)phys_to_virt(dev->mem_start);
3655 tp->ram_access = *(__u32 *)&ram;
3656 tp->status = NOT_INITIALIZED;
3657
3658 err = smctr_load_firmware(dev);
3659 if(err != UCODE_PRESENT && err != SUCCESS)
3660 {
3661 printk(KERN_ERR "%s: Firmware load failed (%d)\n", dev->name, err);
3662 err = -EIO;
3663 goto out;
3664 }
3665
3666 /* Allow user to specify ring speed on module insert. */
3667 if(ringspeed == 4)
3668 tp->media_type = MEDIA_UTP_4;
3669 else
3670 tp->media_type = MEDIA_UTP_16;
3671
3672 printk(KERN_INFO "%s: %s %s at Io %#4x, Irq %d, Rom %#4x, Ram %#4x.\n",
3673 dev->name, smctr_name, smctr_model,
3674 (unsigned int)dev->base_addr,
3675 dev->irq, tp->rom_base, tp->ram_base);
3676
3677 dev->netdev_ops = &smctr_netdev_ops;
3678 dev->watchdog_timeo = HZ;
3679 return 0;
3680
3681out:
3682 return err;
3683}
3684
3685static int smctr_process_rx_packet(MAC_HEADER *rmf, __u16 size,
3686 struct net_device *dev, __u16 rx_status)
3687{
3688 struct net_local *tp = netdev_priv(dev);
3689 struct sk_buff *skb;
3690 __u16 rcode, correlator;
3691 int err = 0;
3692 __u8 xframe = 1;
3693
3694 rmf->vl = SWAP_BYTES(rmf->vl);
3695 if(rx_status & FCB_RX_STATUS_DA_MATCHED)
3696 {
3697 switch(rmf->vc)
3698 {
3699 /* Received MAC Frames Processed by RS. */
3700 case INIT:
3701 if((rcode = smctr_rcv_init(dev, rmf, &correlator)) == HARDWARE_FAILED)
3702 {
3703 return rcode;
3704 }
3705
3706 if((err = smctr_send_rsp(dev, rmf, rcode,
3707 correlator)))
3708 {
3709 return err;
3710 }
3711 break;
3712
3713 case CHG_PARM:
3714 if((rcode = smctr_rcv_chg_param(dev, rmf,
3715 &correlator)) ==HARDWARE_FAILED)
3716 {
3717 return rcode;
3718 }
3719
3720 if((err = smctr_send_rsp(dev, rmf, rcode,
3721 correlator)))
3722 {
3723 return err;
3724 }
3725 break;
3726
3727 case RQ_ADDR:
3728 if((rcode = smctr_rcv_rq_addr_state_attch(dev,
3729 rmf, &correlator)) != POSITIVE_ACK)
3730 {
3731 if(rcode == HARDWARE_FAILED)
3732 return rcode;
3733 else
3734 return smctr_send_rsp(dev, rmf,
3735 rcode, correlator);
3736 }
3737
3738 if((err = smctr_send_rpt_addr(dev, rmf,
3739 correlator)))
3740 {
3741 return err;
3742 }
3743 break;
3744
3745 case RQ_ATTCH:
3746 if((rcode = smctr_rcv_rq_addr_state_attch(dev,
3747 rmf, &correlator)) != POSITIVE_ACK)
3748 {
3749 if(rcode == HARDWARE_FAILED)
3750 return rcode;
3751 else
3752 return smctr_send_rsp(dev, rmf,
3753 rcode,
3754 correlator);
3755 }
3756
3757 if((err = smctr_send_rpt_attch(dev, rmf,
3758 correlator)))
3759 {
3760 return err;
3761 }
3762 break;
3763
3764 case RQ_STATE:
3765 if((rcode = smctr_rcv_rq_addr_state_attch(dev,
3766 rmf, &correlator)) != POSITIVE_ACK)
3767 {
3768 if(rcode == HARDWARE_FAILED)
3769 return rcode;
3770 else
3771 return smctr_send_rsp(dev, rmf,
3772 rcode,
3773 correlator);
3774 }
3775
3776 if((err = smctr_send_rpt_state(dev, rmf,
3777 correlator)))
3778 {
3779 return err;
3780 }
3781 break;
3782
3783 case TX_FORWARD: {
3784 __u16 uninitialized_var(tx_fstatus);
3785
3786 if((rcode = smctr_rcv_tx_forward(dev, rmf))
3787 != POSITIVE_ACK)
3788 {
3789 if(rcode == HARDWARE_FAILED)
3790 return rcode;
3791 else
3792 return smctr_send_rsp(dev, rmf,
3793 rcode,
3794 correlator);
3795 }
3796
3797 if((err = smctr_send_tx_forward(dev, rmf,
3798 &tx_fstatus)) == HARDWARE_FAILED)
3799 {
3800 return err;
3801 }
3802
3803 if(err == A_FRAME_WAS_FORWARDED)
3804 {
3805 if((err = smctr_send_rpt_tx_forward(dev,
3806 rmf, tx_fstatus))
3807 == HARDWARE_FAILED)
3808 {
3809 return err;
3810 }
3811 }
3812 break;
3813 }
3814
3815 /* Received MAC Frames Processed by CRS/REM/RPS. */
3816 case RSP:
3817 case RQ_INIT:
3818 case RPT_NEW_MON:
3819 case RPT_SUA_CHG:
3820 case RPT_ACTIVE_ERR:
3821 case RPT_NN_INCMP:
3822 case RPT_ERROR:
3823 case RPT_ATTCH:
3824 case RPT_STATE:
3825 case RPT_ADDR:
3826 break;
3827
3828 /* Rcvd Att. MAC Frame (if RXATMAC set) or UNKNOWN */
3829 default:
3830 xframe = 0;
3831 if(!(tp->receive_mask & ACCEPT_ATT_MAC_FRAMES))
3832 {
3833 rcode = smctr_rcv_unknown(dev, rmf,
3834 &correlator);
3835 if((err = smctr_send_rsp(dev, rmf,rcode,
3836 correlator)))
3837 {
3838 return err;
3839 }
3840 }
3841
3842 break;
3843 }
3844 }
3845 else
3846 {
3847 /* 1. DA doesn't match (Promiscuous Mode).
3848 * 2. Parse for Extended MAC Frame Type.
3849 */
3850 switch(rmf->vc)
3851 {
3852 case RSP:
3853 case INIT:
3854 case RQ_INIT:
3855 case RQ_ADDR:
3856 case RQ_ATTCH:
3857 case RQ_STATE:
3858 case CHG_PARM:
3859 case RPT_ADDR:
3860 case RPT_ERROR:
3861 case RPT_ATTCH:
3862 case RPT_STATE:
3863 case RPT_NEW_MON:
3864 case RPT_SUA_CHG:
3865 case RPT_NN_INCMP:
3866 case RPT_ACTIVE_ERR:
3867 break;
3868
3869 default:
3870 xframe = 0;
3871 break;
3872 }
3873 }
3874
3875 /* NOTE: UNKNOWN MAC frames will NOT be passed up unless
3876 * ACCEPT_ATT_MAC_FRAMES is set.
3877 */
3878 if(((tp->receive_mask & ACCEPT_ATT_MAC_FRAMES) &&
3879 (xframe == (__u8)0)) ||
3880 ((tp->receive_mask & ACCEPT_EXT_MAC_FRAMES) &&
3881 (xframe == (__u8)1)))
3882 {
3883 rmf->vl = SWAP_BYTES(rmf->vl);
3884
3885 if (!(skb = dev_alloc_skb(size)))
3886 return -ENOMEM;
3887 skb->len = size;
3888
3889 /* Slide data into a sleek skb. */
3890 skb_put(skb, skb->len);
3891 skb_copy_to_linear_data(skb, rmf, skb->len);
3892
3893 /* Update Counters */
3894 tp->MacStat.rx_packets++;
3895 tp->MacStat.rx_bytes += skb->len;
3896
3897 /* Kick the packet on up. */
3898 skb->protocol = tr_type_trans(skb, dev);
3899 netif_rx(skb);
3900 err = 0;
3901 }
3902
3903 return err;
3904}
3905
3906/* Adapter RAM test. Incremental word ODD boundary data test. */
3907static int smctr_ram_memory_test(struct net_device *dev)
3908{
3909 struct net_local *tp = netdev_priv(dev);
3910 __u16 page, pages_of_ram, start_pattern = 0, word_pattern = 0,
3911 word_read = 0, err_word = 0, err_pattern = 0;
3912 unsigned int err_offset;
3913 __u32 j, pword;
3914 __u8 err = 0;
3915
3916 if(smctr_debug > 10)
3917 printk(KERN_DEBUG "%s: smctr_ram_memory_test\n", dev->name);
3918
3919 start_pattern = 0x0001;
3920 pages_of_ram = tp->ram_size / tp->ram_usable;
3921 pword = tp->ram_access;
3922
3923 /* Incremental word ODD boundary test. */
3924 for(page = 0; (page < pages_of_ram) && (~err);
3925 page++, start_pattern += 0x8000)
3926 {
3927 smctr_set_page(dev, (__u8 *)(tp->ram_access
3928 + (page * tp->ram_usable * 1024) + 1));
3929 word_pattern = start_pattern;
3930
3931 for(j = 1; j < (__u32)(tp->ram_usable * 1024) - 1; j += 2)
3932 *(__u16 *)(pword + j) = word_pattern++;
3933
3934 word_pattern = start_pattern;
3935
3936 for(j = 1; j < (__u32)(tp->ram_usable * 1024) - 1 && (~err);
3937 j += 2, word_pattern++)
3938 {
3939 word_read = *(__u16 *)(pword + j);
3940 if(word_read != word_pattern)
3941 {
3942 err = (__u8)1;
3943 err_offset = j;
3944 err_word = word_read;
3945 err_pattern = word_pattern;
3946 return RAM_TEST_FAILED;
3947 }
3948 }
3949 }
3950
3951 /* Zero out memory. */
3952 for(page = 0; page < pages_of_ram && (~err); page++)
3953 {
3954 smctr_set_page(dev, (__u8 *)(tp->ram_access
3955 + (page * tp->ram_usable * 1024)));
3956 word_pattern = 0;
3957
3958 for(j = 0; j < (__u32)tp->ram_usable * 1024; j +=2)
3959 *(__u16 *)(pword + j) = word_pattern;
3960
3961 for(j =0; j < (__u32)tp->ram_usable * 1024 && (~err); j += 2)
3962 {
3963 word_read = *(__u16 *)(pword + j);
3964 if(word_read != word_pattern)
3965 {
3966 err = (__u8)1;
3967 err_offset = j;
3968 err_word = word_read;
3969 err_pattern = word_pattern;
3970 return RAM_TEST_FAILED;
3971 }
3972 }
3973 }
3974
3975 smctr_set_page(dev, (__u8 *)tp->ram_access);
3976
3977 return 0;
3978}
3979
3980static int smctr_rcv_chg_param(struct net_device *dev, MAC_HEADER *rmf,
3981 __u16 *correlator)
3982{
3983 MAC_SUB_VECTOR *rsv;
3984 signed short vlen;
3985 __u16 rcode = POSITIVE_ACK;
3986 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
3987
3988 /* This Frame can only come from a CRS */
3989 if((rmf->dc_sc & SC_MASK) != SC_CRS)
3990 return E_INAPPROPRIATE_SOURCE_CLASS;
3991
3992 /* Remove MVID Length from total length. */
3993 vlen = (signed short)rmf->vl - 4;
3994
3995 /* Point to First SVID */
3996 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
3997
3998 /* Search for Appropriate SVID's. */
3999 while((vlen > 0) && (rcode == POSITIVE_ACK))
4000 {
4001 switch(rsv->svi)
4002 {
4003 case CORRELATOR:
4004 svectors |= F_CORRELATOR;
4005 rcode = smctr_set_corr(dev, rsv, correlator);
4006 break;
4007
4008 case LOCAL_RING_NUMBER:
4009 svectors |= F_LOCAL_RING_NUMBER;
4010 rcode = smctr_set_local_ring_num(dev, rsv);
4011 break;
4012
4013 case ASSIGN_PHYSICAL_DROP:
4014 svectors |= F_ASSIGN_PHYSICAL_DROP;
4015 rcode = smctr_set_phy_drop(dev, rsv);
4016 break;
4017
4018 case ERROR_TIMER_VALUE:
4019 svectors |= F_ERROR_TIMER_VALUE;
4020 rcode = smctr_set_error_timer_value(dev, rsv);
4021 break;
4022
4023 case AUTHORIZED_FUNCTION_CLASS:
4024 svectors |= F_AUTHORIZED_FUNCTION_CLASS;
4025 rcode = smctr_set_auth_funct_class(dev, rsv);
4026 break;
4027
4028 case AUTHORIZED_ACCESS_PRIORITY:
4029 svectors |= F_AUTHORIZED_ACCESS_PRIORITY;
4030 rcode = smctr_set_auth_access_pri(dev, rsv);
4031 break;
4032
4033 default:
4034 rcode = E_SUB_VECTOR_UNKNOWN;
4035 break;
4036 }
4037
4038 /* Let Sender Know if SUM of SV length's is
4039 * larger then length in MVID length field
4040 */
4041 if((vlen -= rsv->svl) < 0)
4042 rcode = E_VECTOR_LENGTH_ERROR;
4043
4044 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4045 }
4046
4047 if(rcode == POSITIVE_ACK)
4048 {
4049 /* Let Sender Know if MVID length field
4050 * is larger then SUM of SV length's
4051 */
4052 if(vlen != 0)
4053 rcode = E_VECTOR_LENGTH_ERROR;
4054 else
4055 {
4056 /* Let Sender Know if Expected SVID Missing */
4057 if((svectors & R_CHG_PARM) ^ R_CHG_PARM)
4058 rcode = E_MISSING_SUB_VECTOR;
4059 }
4060 }
4061
4062 return rcode;
4063}
4064
4065static int smctr_rcv_init(struct net_device *dev, MAC_HEADER *rmf,
4066 __u16 *correlator)
4067{
4068 MAC_SUB_VECTOR *rsv;
4069 signed short vlen;
4070 __u16 rcode = POSITIVE_ACK;
4071 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
4072
4073 /* This Frame can only come from a RPS */
4074 if((rmf->dc_sc & SC_MASK) != SC_RPS)
4075 return E_INAPPROPRIATE_SOURCE_CLASS;
4076
4077 /* Remove MVID Length from total length. */
4078 vlen = (signed short)rmf->vl - 4;
4079
4080 /* Point to First SVID */
4081 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4082
4083 /* Search for Appropriate SVID's */
4084 while((vlen > 0) && (rcode == POSITIVE_ACK))
4085 {
4086 switch(rsv->svi)
4087 {
4088 case CORRELATOR:
4089 svectors |= F_CORRELATOR;
4090 rcode = smctr_set_corr(dev, rsv, correlator);
4091 break;
4092
4093 case LOCAL_RING_NUMBER:
4094 svectors |= F_LOCAL_RING_NUMBER;
4095 rcode = smctr_set_local_ring_num(dev, rsv);
4096 break;
4097
4098 case ASSIGN_PHYSICAL_DROP:
4099 svectors |= F_ASSIGN_PHYSICAL_DROP;
4100 rcode = smctr_set_phy_drop(dev, rsv);
4101 break;
4102
4103 case ERROR_TIMER_VALUE:
4104 svectors |= F_ERROR_TIMER_VALUE;
4105 rcode = smctr_set_error_timer_value(dev, rsv);
4106 break;
4107
4108 default:
4109 rcode = E_SUB_VECTOR_UNKNOWN;
4110 break;
4111 }
4112
4113 /* Let Sender Know if SUM of SV length's is
4114 * larger then length in MVID length field
4115 */
4116 if((vlen -= rsv->svl) < 0)
4117 rcode = E_VECTOR_LENGTH_ERROR;
4118
4119 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4120 }
4121
4122 if(rcode == POSITIVE_ACK)
4123 {
4124 /* Let Sender Know if MVID length field
4125 * is larger then SUM of SV length's
4126 */
4127 if(vlen != 0)
4128 rcode = E_VECTOR_LENGTH_ERROR;
4129 else
4130 {
4131 /* Let Sender Know if Expected SV Missing */
4132 if((svectors & R_INIT) ^ R_INIT)
4133 rcode = E_MISSING_SUB_VECTOR;
4134 }
4135 }
4136
4137 return rcode;
4138}
4139
4140static int smctr_rcv_tx_forward(struct net_device *dev, MAC_HEADER *rmf)
4141{
4142 MAC_SUB_VECTOR *rsv;
4143 signed short vlen;
4144 __u16 rcode = POSITIVE_ACK;
4145 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
4146
4147 /* This Frame can only come from a CRS */
4148 if((rmf->dc_sc & SC_MASK) != SC_CRS)
4149 return E_INAPPROPRIATE_SOURCE_CLASS;
4150
4151 /* Remove MVID Length from total length */
4152 vlen = (signed short)rmf->vl - 4;
4153
4154 /* Point to First SVID */
4155 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4156
4157 /* Search for Appropriate SVID's */
4158 while((vlen > 0) && (rcode == POSITIVE_ACK))
4159 {
4160 switch(rsv->svi)
4161 {
4162 case FRAME_FORWARD:
4163 svectors |= F_FRAME_FORWARD;
4164 rcode = smctr_set_frame_forward(dev, rsv,
4165 rmf->dc_sc);
4166 break;
4167
4168 default:
4169 rcode = E_SUB_VECTOR_UNKNOWN;
4170 break;
4171 }
4172
4173 /* Let Sender Know if SUM of SV length's is
4174 * larger then length in MVID length field
4175 */
4176 if((vlen -= rsv->svl) < 0)
4177 rcode = E_VECTOR_LENGTH_ERROR;
4178
4179 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4180 }
4181
4182 if(rcode == POSITIVE_ACK)
4183 {
4184 /* Let Sender Know if MVID length field
4185 * is larger then SUM of SV length's
4186 */
4187 if(vlen != 0)
4188 rcode = E_VECTOR_LENGTH_ERROR;
4189 else
4190 {
4191 /* Let Sender Know if Expected SV Missing */
4192 if((svectors & R_TX_FORWARD) ^ R_TX_FORWARD)
4193 rcode = E_MISSING_SUB_VECTOR;
4194 }
4195 }
4196
4197 return rcode;
4198}
4199
4200static int smctr_rcv_rq_addr_state_attch(struct net_device *dev,
4201 MAC_HEADER *rmf, __u16 *correlator)
4202{
4203 MAC_SUB_VECTOR *rsv;
4204 signed short vlen;
4205 __u16 rcode = POSITIVE_ACK;
4206 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
4207
4208 /* Remove MVID Length from total length */
4209 vlen = (signed short)rmf->vl - 4;
4210
4211 /* Point to First SVID */
4212 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4213
4214 /* Search for Appropriate SVID's */
4215 while((vlen > 0) && (rcode == POSITIVE_ACK))
4216 {
4217 switch(rsv->svi)
4218 {
4219 case CORRELATOR:
4220 svectors |= F_CORRELATOR;
4221 rcode = smctr_set_corr(dev, rsv, correlator);
4222 break;
4223
4224 default:
4225 rcode = E_SUB_VECTOR_UNKNOWN;
4226 break;
4227 }
4228
4229 /* Let Sender Know if SUM of SV length's is
4230 * larger then length in MVID length field
4231 */
4232 if((vlen -= rsv->svl) < 0)
4233 rcode = E_VECTOR_LENGTH_ERROR;
4234
4235 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4236 }
4237
4238 if(rcode == POSITIVE_ACK)
4239 {
4240 /* Let Sender Know if MVID length field
4241 * is larger then SUM of SV length's
4242 */
4243 if(vlen != 0)
4244 rcode = E_VECTOR_LENGTH_ERROR;
4245 else
4246 {
4247 /* Let Sender Know if Expected SVID Missing */
4248 if((svectors & R_RQ_ATTCH_STATE_ADDR)
4249 ^ R_RQ_ATTCH_STATE_ADDR)
4250 rcode = E_MISSING_SUB_VECTOR;
4251 }
4252 }
4253
4254 return rcode;
4255}
4256
4257static int smctr_rcv_unknown(struct net_device *dev, MAC_HEADER *rmf,
4258 __u16 *correlator)
4259{
4260 MAC_SUB_VECTOR *rsv;
4261 signed short vlen;
4262
4263 *correlator = 0;
4264
4265 /* Remove MVID Length from total length */
4266 vlen = (signed short)rmf->vl - 4;
4267
4268 /* Point to First SVID */
4269 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4270
4271 /* Search for CORRELATOR for RSP to UNKNOWN */
4272 while((vlen > 0) && (*correlator == 0))
4273 {
4274 switch(rsv->svi)
4275 {
4276 case CORRELATOR:
4277 smctr_set_corr(dev, rsv, correlator);
4278 break;
4279
4280 default:
4281 break;
4282 }
4283
4284 vlen -= rsv->svl;
4285 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4286 }
4287
4288 return E_UNRECOGNIZED_VECTOR_ID;
4289}
4290
4291/*
4292 * Reset the 825 NIC and exit w:
4293 * 1. The NIC reset cleared (non-reset state), halted and un-initialized.
4294 * 2. TINT masked.
4295 * 3. CBUSY masked.
4296 * 4. TINT clear.
4297 * 5. CBUSY clear.
4298 */
4299static int smctr_reset_adapter(struct net_device *dev)
4300{
4301 struct net_local *tp = netdev_priv(dev);
4302 int ioaddr = dev->base_addr;
4303
4304 /* Reseting the NIC will put it in a halted and un-initialized state. */ smctr_set_trc_reset(ioaddr);
4305 mdelay(200); /* ~2 ms */
4306
4307 smctr_clear_trc_reset(ioaddr);
4308 mdelay(200); /* ~2 ms */
4309
4310 /* Remove any latched interrupts that occurred prior to reseting the
4311 * adapter or possibily caused by line glitches due to the reset.
4312 */
4313 outb(tp->trc_mask | CSR_CLRTINT | CSR_CLRCBUSY, ioaddr + CSR);
4314
4315 return 0;
4316}
4317
4318static int smctr_restart_tx_chain(struct net_device *dev, short queue)
4319{
4320 struct net_local *tp = netdev_priv(dev);
4321 int err = 0;
4322
4323 if(smctr_debug > 10)
4324 printk(KERN_DEBUG "%s: smctr_restart_tx_chain\n", dev->name);
4325
4326 if(tp->num_tx_fcbs_used[queue] != 0 &&
4327 tp->tx_queue_status[queue] == NOT_TRANSMITING)
4328 {
4329 tp->tx_queue_status[queue] = TRANSMITING;
4330 err = smctr_issue_resume_tx_fcb_cmd(dev, queue);
4331 }
4332
4333 return err;
4334}
4335
4336static int smctr_ring_status_chg(struct net_device *dev)
4337{
4338 struct net_local *tp = netdev_priv(dev);
4339
4340 if(smctr_debug > 10)
4341 printk(KERN_DEBUG "%s: smctr_ring_status_chg\n", dev->name);
4342
4343 /* Check for ring_status_flag: whenever MONITOR_STATE_BIT
4344 * Bit is set, check value of monitor_state, only then we
4345 * enable and start transmit/receive timeout (if and only
4346 * if it is MS_ACTIVE_MONITOR_STATE or MS_STANDBY_MONITOR_STATE)
4347 */
4348 if(tp->ring_status_flags == MONITOR_STATE_CHANGED)
4349 {
4350 if((tp->monitor_state == MS_ACTIVE_MONITOR_STATE) ||
4351 (tp->monitor_state == MS_STANDBY_MONITOR_STATE))
4352 {
4353 tp->monitor_state_ready = 1;
4354 }
4355 else
4356 {
4357 /* if adapter is NOT in either active monitor
4358 * or standby monitor state => Disable
4359 * transmit/receive timeout.
4360 */
4361 tp->monitor_state_ready = 0;
4362
4363 /* Ring speed problem, switching to auto mode. */
4364 if(tp->monitor_state == MS_MONITOR_FSM_INACTIVE &&
4365 !tp->cleanup)
4366 {
4367 printk(KERN_INFO "%s: Incorrect ring speed switching.\n",
4368 dev->name);
4369 smctr_set_ring_speed(dev);
4370 }
4371 }
4372 }
4373
4374 if(!(tp->ring_status_flags & RING_STATUS_CHANGED))
4375 return 0;
4376
4377 switch(tp->ring_status)
4378 {
4379 case RING_RECOVERY:
4380 printk(KERN_INFO "%s: Ring Recovery\n", dev->name);
4381 break;
4382
4383 case SINGLE_STATION:
4384 printk(KERN_INFO "%s: Single Statinon\n", dev->name);
4385 break;
4386
4387 case COUNTER_OVERFLOW:
4388 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
4389 break;
4390
4391 case REMOVE_RECEIVED:
4392 printk(KERN_INFO "%s: Remove Received\n", dev->name);
4393 break;
4394
4395 case AUTO_REMOVAL_ERROR:
4396 printk(KERN_INFO "%s: Auto Remove Error\n", dev->name);
4397 break;
4398
4399 case LOBE_WIRE_FAULT:
4400 printk(KERN_INFO "%s: Lobe Wire Fault\n", dev->name);
4401 break;
4402
4403 case TRANSMIT_BEACON:
4404 printk(KERN_INFO "%s: Transmit Beacon\n", dev->name);
4405 break;
4406
4407 case SOFT_ERROR:
4408 printk(KERN_INFO "%s: Soft Error\n", dev->name);
4409 break;
4410
4411 case HARD_ERROR:
4412 printk(KERN_INFO "%s: Hard Error\n", dev->name);
4413 break;
4414
4415 case SIGNAL_LOSS:
4416 printk(KERN_INFO "%s: Signal Loss\n", dev->name);
4417 break;
4418
4419 default:
4420 printk(KERN_INFO "%s: Unknown ring status change\n",
4421 dev->name);
4422 break;
4423 }
4424
4425 return 0;
4426}
4427
4428static int smctr_rx_frame(struct net_device *dev)
4429{
4430 struct net_local *tp = netdev_priv(dev);
4431 __u16 queue, status, rx_size, err = 0;
4432 __u8 *pbuff;
4433
4434 if(smctr_debug > 10)
4435 printk(KERN_DEBUG "%s: smctr_rx_frame\n", dev->name);
4436
4437 queue = tp->receive_queue_number;
4438
4439 while((status = tp->rx_fcb_curr[queue]->frame_status) != SUCCESS)
4440 {
4441 err = HARDWARE_FAILED;
4442
4443 if(((status & 0x007f) == 0) ||
4444 ((tp->receive_mask & ACCEPT_ERR_PACKETS) != 0))
4445 {
4446 /* frame length less the CRC (4 bytes) + FS (1 byte) */
4447 rx_size = tp->rx_fcb_curr[queue]->frame_length - 5;
4448
4449 pbuff = smctr_get_rx_pointer(dev, queue);
4450
4451 smctr_set_page(dev, pbuff);
4452 smctr_disable_16bit(dev);
4453
4454 /* pbuff points to addr within one page */
4455 pbuff = (__u8 *)PAGE_POINTER(pbuff);
4456
4457 if(queue == NON_MAC_QUEUE)
4458 {
4459 struct sk_buff *skb;
4460
4461 skb = dev_alloc_skb(rx_size);
4462 if (skb) {
4463 skb_put(skb, rx_size);
4464
4465 skb_copy_to_linear_data(skb, pbuff, rx_size);
4466
4467 /* Update Counters */
4468 tp->MacStat.rx_packets++;
4469 tp->MacStat.rx_bytes += skb->len;
4470
4471 /* Kick the packet on up. */
4472 skb->protocol = tr_type_trans(skb, dev);
4473 netif_rx(skb);
4474 } else {
4475 }
4476 }
4477 else
4478 smctr_process_rx_packet((MAC_HEADER *)pbuff,
4479 rx_size, dev, status);
4480 }
4481
4482 smctr_enable_16bit(dev);
4483 smctr_set_page(dev, (__u8 *)tp->ram_access);
4484 smctr_update_rx_chain(dev, queue);
4485
4486 if(err != SUCCESS)
4487 break;
4488 }
4489
4490 return err;
4491}
4492
4493static int smctr_send_dat(struct net_device *dev)
4494{
4495 struct net_local *tp = netdev_priv(dev);
4496 unsigned int i, err;
4497 MAC_HEADER *tmf;
4498 FCBlock *fcb;
4499
4500 if(smctr_debug > 10)
4501 printk(KERN_DEBUG "%s: smctr_send_dat\n", dev->name);
4502
4503 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE,
4504 sizeof(MAC_HEADER))) == (FCBlock *)(-1L))
4505 {
4506 return OUT_OF_RESOURCES;
4507 }
4508
4509 /* Initialize DAT Data Fields. */
4510 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4511 tmf->ac = MSB(AC_FC_DAT);
4512 tmf->fc = LSB(AC_FC_DAT);
4513
4514 for(i = 0; i < 6; i++)
4515 {
4516 tmf->sa[i] = dev->dev_addr[i];
4517 tmf->da[i] = dev->dev_addr[i];
4518
4519 }
4520
4521 tmf->vc = DAT;
4522 tmf->dc_sc = DC_RS | SC_RS;
4523 tmf->vl = 4;
4524 tmf->vl = SWAP_BYTES(tmf->vl);
4525
4526 /* Start Transmit. */
4527 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
4528 return err;
4529
4530 /* Wait for Transmit to Complete */
4531 for(i = 0; i < 10000; i++)
4532 {
4533 if(fcb->frame_status & FCB_COMMAND_DONE)
4534 break;
4535 mdelay(1);
4536 }
4537
4538 /* Check if GOOD frame Tx'ed. */
4539 if(!(fcb->frame_status & FCB_COMMAND_DONE) ||
4540 fcb->frame_status & (FCB_TX_STATUS_E | FCB_TX_AC_BITS))
4541 {
4542 return INITIALIZE_FAILED;
4543 }
4544
4545 /* De-allocated Tx FCB and Frame Buffer
4546 * The FCB must be de-allocated manually if executing with
4547 * interrupts disabled, other wise the ISR (LM_Service_Events)
4548 * will de-allocate it when the interrupt occurs.
4549 */
4550 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
4551 smctr_update_tx_chain(dev, fcb, MAC_QUEUE);
4552
4553 return 0;
4554}
4555
4556static void smctr_timeout(struct net_device *dev)
4557{
4558 /*
4559 * If we get here, some higher level has decided we are broken.
4560 * There should really be a "kick me" function call instead.
4561 *
4562 * Resetting the token ring adapter takes a long time so just
4563 * fake transmission time and go on trying. Our own timeout
4564 * routine is in sktr_timer_chk()
4565 */
4566 dev->trans_start = jiffies; /* prevent tx timeout */
4567 netif_wake_queue(dev);
4568}
4569
4570/*
4571 * Gets skb from system, queues it and checks if it can be sent
4572 */
4573static netdev_tx_t smctr_send_packet(struct sk_buff *skb,
4574 struct net_device *dev)
4575{
4576 struct net_local *tp = netdev_priv(dev);
4577
4578 if(smctr_debug > 10)
4579 printk(KERN_DEBUG "%s: smctr_send_packet\n", dev->name);
4580
4581 /*
4582 * Block a transmit overlap
4583 */
4584
4585 netif_stop_queue(dev);
4586
4587 if(tp->QueueSkb == 0)
4588 return NETDEV_TX_BUSY; /* Return with tbusy set: queue full */
4589
4590 tp->QueueSkb--;
4591 skb_queue_tail(&tp->SendSkbQueue, skb);
4592 smctr_hardware_send_packet(dev, tp);
4593 if(tp->QueueSkb > 0)
4594 netif_wake_queue(dev);
4595
4596 return NETDEV_TX_OK;
4597}
4598
4599static int smctr_send_lobe_media_test(struct net_device *dev)
4600{
4601 struct net_local *tp = netdev_priv(dev);
4602 MAC_SUB_VECTOR *tsv;
4603 MAC_HEADER *tmf;
4604 FCBlock *fcb;
4605 __u32 i;
4606 int err;
4607
4608 if(smctr_debug > 15)
4609 printk(KERN_DEBUG "%s: smctr_send_lobe_media_test\n", dev->name);
4610
4611 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(struct trh_hdr)
4612 + S_WRAP_DATA + S_WRAP_DATA)) == (FCBlock *)(-1L))
4613 {
4614 return OUT_OF_RESOURCES;
4615 }
4616
4617 /* Initialize DAT Data Fields. */
4618 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4619 tmf->ac = MSB(AC_FC_LOBE_MEDIA_TEST);
4620 tmf->fc = LSB(AC_FC_LOBE_MEDIA_TEST);
4621
4622 for(i = 0; i < 6; i++)
4623 {
4624 tmf->da[i] = 0;
4625 tmf->sa[i] = dev->dev_addr[i];
4626 }
4627
4628 tmf->vc = LOBE_MEDIA_TEST;
4629 tmf->dc_sc = DC_RS | SC_RS;
4630 tmf->vl = 4;
4631
4632 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4633 smctr_make_wrap_data(dev, tsv);
4634 tmf->vl += tsv->svl;
4635
4636 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4637 smctr_make_wrap_data(dev, tsv);
4638 tmf->vl += tsv->svl;
4639
4640 /* Start Transmit. */
4641 tmf->vl = SWAP_BYTES(tmf->vl);
4642 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
4643 return err;
4644
4645 /* Wait for Transmit to Complete. (10 ms). */
4646 for(i=0; i < 10000; i++)
4647 {
4648 if(fcb->frame_status & FCB_COMMAND_DONE)
4649 break;
4650 mdelay(1);
4651 }
4652
4653 /* Check if GOOD frame Tx'ed */
4654 if(!(fcb->frame_status & FCB_COMMAND_DONE) ||
4655 fcb->frame_status & (FCB_TX_STATUS_E | FCB_TX_AC_BITS))
4656 {
4657 return LOBE_MEDIA_TEST_FAILED;
4658 }
4659
4660 /* De-allocated Tx FCB and Frame Buffer
4661 * The FCB must be de-allocated manually if executing with
4662 * interrupts disabled, other wise the ISR (LM_Service_Events)
4663 * will de-allocate it when the interrupt occurs.
4664 */
4665 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
4666 smctr_update_tx_chain(dev, fcb, MAC_QUEUE);
4667
4668 return 0;
4669}
4670
4671static int smctr_send_rpt_addr(struct net_device *dev, MAC_HEADER *rmf,
4672 __u16 correlator)
4673{
4674 MAC_HEADER *tmf;
4675 MAC_SUB_VECTOR *tsv;
4676 FCBlock *fcb;
4677
4678 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4679 + S_CORRELATOR + S_PHYSICAL_DROP + S_UPSTREAM_NEIGHBOR_ADDRESS
4680 + S_ADDRESS_MODIFER + S_GROUP_ADDRESS + S_FUNCTIONAL_ADDRESS))
4681 == (FCBlock *)(-1L))
4682 {
4683 return 0;
4684 }
4685
4686 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4687 tmf->vc = RPT_ADDR;
4688 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4689 tmf->vl = 4;
4690
4691 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_ADDR);
4692
4693 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4694 smctr_make_corr(dev, tsv, correlator);
4695
4696 tmf->vl += tsv->svl;
4697 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4698 smctr_make_phy_drop_num(dev, tsv);
4699
4700 tmf->vl += tsv->svl;
4701 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4702 smctr_make_upstream_neighbor_addr(dev, tsv);
4703
4704 tmf->vl += tsv->svl;
4705 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4706 smctr_make_addr_mod(dev, tsv);
4707
4708 tmf->vl += tsv->svl;
4709 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4710 smctr_make_group_addr(dev, tsv);
4711
4712 tmf->vl += tsv->svl;
4713 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4714 smctr_make_funct_addr(dev, tsv);
4715
4716 tmf->vl += tsv->svl;
4717
4718 /* Subtract out MVID and MVL which is
4719 * include in both vl and MAC_HEADER
4720 */
4721/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4722 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4723*/
4724 tmf->vl = SWAP_BYTES(tmf->vl);
4725
4726 return smctr_trc_send_packet(dev, fcb, MAC_QUEUE);
4727}
4728
4729static int smctr_send_rpt_attch(struct net_device *dev, MAC_HEADER *rmf,
4730 __u16 correlator)
4731{
4732 MAC_HEADER *tmf;
4733 MAC_SUB_VECTOR *tsv;
4734 FCBlock *fcb;
4735
4736 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4737 + S_CORRELATOR + S_PRODUCT_INSTANCE_ID + S_FUNCTIONAL_ADDRESS
4738 + S_AUTHORIZED_FUNCTION_CLASS + S_AUTHORIZED_ACCESS_PRIORITY))
4739 == (FCBlock *)(-1L))
4740 {
4741 return 0;
4742 }
4743
4744 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4745 tmf->vc = RPT_ATTCH;
4746 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4747 tmf->vl = 4;
4748
4749 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_ATTCH);
4750
4751 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4752 smctr_make_corr(dev, tsv, correlator);
4753
4754 tmf->vl += tsv->svl;
4755 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4756 smctr_make_product_id(dev, tsv);
4757
4758 tmf->vl += tsv->svl;
4759 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4760 smctr_make_funct_addr(dev, tsv);
4761
4762 tmf->vl += tsv->svl;
4763 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4764 smctr_make_auth_funct_class(dev, tsv);
4765
4766 tmf->vl += tsv->svl;
4767 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4768 smctr_make_access_pri(dev, tsv);
4769
4770 tmf->vl += tsv->svl;
4771
4772 /* Subtract out MVID and MVL which is
4773 * include in both vl and MAC_HEADER
4774 */
4775/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4776 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4777*/
4778 tmf->vl = SWAP_BYTES(tmf->vl);
4779
4780 return smctr_trc_send_packet(dev, fcb, MAC_QUEUE);
4781}
4782
4783static int smctr_send_rpt_state(struct net_device *dev, MAC_HEADER *rmf,
4784 __u16 correlator)
4785{
4786 MAC_HEADER *tmf;
4787 MAC_SUB_VECTOR *tsv;
4788 FCBlock *fcb;
4789
4790 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4791 + S_CORRELATOR + S_RING_STATION_VERSION_NUMBER
4792 + S_RING_STATION_STATUS + S_STATION_IDENTIFER))
4793 == (FCBlock *)(-1L))
4794 {
4795 return 0;
4796 }
4797
4798 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4799 tmf->vc = RPT_STATE;
4800 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4801 tmf->vl = 4;
4802
4803 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_STATE);
4804
4805 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4806 smctr_make_corr(dev, tsv, correlator);
4807
4808 tmf->vl += tsv->svl;
4809 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4810 smctr_make_ring_station_version(dev, tsv);
4811
4812 tmf->vl += tsv->svl;
4813 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4814 smctr_make_ring_station_status(dev, tsv);
4815
4816 tmf->vl += tsv->svl;
4817 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4818 smctr_make_station_id(dev, tsv);
4819
4820 tmf->vl += tsv->svl;
4821
4822 /* Subtract out MVID and MVL which is
4823 * include in both vl and MAC_HEADER
4824 */
4825/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4826 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4827*/
4828 tmf->vl = SWAP_BYTES(tmf->vl);
4829
4830 return smctr_trc_send_packet(dev, fcb, MAC_QUEUE);
4831}
4832
4833static int smctr_send_rpt_tx_forward(struct net_device *dev,
4834 MAC_HEADER *rmf, __u16 tx_fstatus)
4835{
4836 MAC_HEADER *tmf;
4837 MAC_SUB_VECTOR *tsv;
4838 FCBlock *fcb;
4839
4840 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4841 + S_TRANSMIT_STATUS_CODE)) == (FCBlock *)(-1L))
4842 {
4843 return 0;
4844 }
4845
4846 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4847 tmf->vc = RPT_TX_FORWARD;
4848 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4849 tmf->vl = 4;
4850
4851 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_TX_FORWARD);
4852
4853 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4854 smctr_make_tx_status_code(dev, tsv, tx_fstatus);
4855
4856 tmf->vl += tsv->svl;
4857
4858 /* Subtract out MVID and MVL which is
4859 * include in both vl and MAC_HEADER
4860 */
4861/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4862 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4863*/
4864 tmf->vl = SWAP_BYTES(tmf->vl);
4865
4866 return smctr_trc_send_packet(dev, fcb, MAC_QUEUE);
4867}
4868
4869static int smctr_send_rsp(struct net_device *dev, MAC_HEADER *rmf,
4870 __u16 rcode, __u16 correlator)
4871{
4872 MAC_HEADER *tmf;
4873 MAC_SUB_VECTOR *tsv;
4874 FCBlock *fcb;
4875
4876 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4877 + S_CORRELATOR + S_RESPONSE_CODE)) == (FCBlock *)(-1L))
4878 {
4879 return 0;
4880 }
4881
4882 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4883 tmf->vc = RSP;
4884 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4885 tmf->vl = 4;
4886
4887 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RSP);
4888
4889 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4890 smctr_make_corr(dev, tsv, correlator);
4891
4892 return 0;
4893}
4894
4895static int smctr_send_rq_init(struct net_device *dev)
4896{
4897 struct net_local *tp = netdev_priv(dev);
4898 MAC_HEADER *tmf;
4899 MAC_SUB_VECTOR *tsv;
4900 FCBlock *fcb;
4901 unsigned int i, count = 0;
4902 __u16 fstatus;
4903 int err;
4904
4905 do {
4906 if(((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4907 + S_PRODUCT_INSTANCE_ID + S_UPSTREAM_NEIGHBOR_ADDRESS
4908 + S_RING_STATION_VERSION_NUMBER + S_ADDRESS_MODIFER))
4909 == (FCBlock *)(-1L)))
4910 {
4911 return 0;
4912 }
4913
4914 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4915 tmf->vc = RQ_INIT;
4916 tmf->dc_sc = DC_RPS | SC_RS;
4917 tmf->vl = 4;
4918
4919 smctr_make_8025_hdr(dev, NULL, tmf, AC_FC_RQ_INIT);
4920
4921 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4922 smctr_make_product_id(dev, tsv);
4923
4924 tmf->vl += tsv->svl;
4925 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4926 smctr_make_upstream_neighbor_addr(dev, tsv);
4927
4928 tmf->vl += tsv->svl;
4929 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4930 smctr_make_ring_station_version(dev, tsv);
4931
4932 tmf->vl += tsv->svl;
4933 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4934 smctr_make_addr_mod(dev, tsv);
4935
4936 tmf->vl += tsv->svl;
4937
4938 /* Subtract out MVID and MVL which is
4939 * include in both vl and MAC_HEADER
4940 */
4941/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4942 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4943*/
4944 tmf->vl = SWAP_BYTES(tmf->vl);
4945
4946 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
4947 return err;
4948
4949 /* Wait for Transmit to Complete */
4950 for(i = 0; i < 10000; i++)
4951 {
4952 if(fcb->frame_status & FCB_COMMAND_DONE)
4953 break;
4954 mdelay(1);
4955 }
4956
4957 /* Check if GOOD frame Tx'ed */
4958 fstatus = fcb->frame_status;
4959
4960 if(!(fstatus & FCB_COMMAND_DONE))
4961 return HARDWARE_FAILED;
4962
4963 if(!(fstatus & FCB_TX_STATUS_E))
4964 count++;
4965
4966 /* De-allocated Tx FCB and Frame Buffer
4967 * The FCB must be de-allocated manually if executing with
4968 * interrupts disabled, other wise the ISR (LM_Service_Events)
4969 * will de-allocate it when the interrupt occurs.
4970 */
4971 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
4972 smctr_update_tx_chain(dev, fcb, MAC_QUEUE);
4973 } while(count < 4 && ((fstatus & FCB_TX_AC_BITS) ^ FCB_TX_AC_BITS));
4974
4975 return smctr_join_complete_state(dev);
4976}
4977
4978static int smctr_send_tx_forward(struct net_device *dev, MAC_HEADER *rmf,
4979 __u16 *tx_fstatus)
4980{
4981 struct net_local *tp = netdev_priv(dev);
4982 FCBlock *fcb;
4983 unsigned int i;
4984 int err;
4985
4986 /* Check if this is the END POINT of the Transmit Forward Chain. */
4987 if(rmf->vl <= 18)
4988 return 0;
4989
4990 /* Allocate Transmit FCB only by requesting 0 bytes
4991 * of data buffer.
4992 */
4993 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, 0)) == (FCBlock *)(-1L))
4994 return 0;
4995
4996 /* Set pointer to Transmit Frame Buffer to the data
4997 * portion of the received TX Forward frame, making
4998 * sure to skip over the Vector Code (vc) and Vector
4999 * length (vl).
5000 */
5001 fcb->bdb_ptr->trc_data_block_ptr = TRC_POINTER((__u32)rmf
5002 + sizeof(MAC_HEADER) + 2);
5003 fcb->bdb_ptr->data_block_ptr = (__u16 *)((__u32)rmf
5004 + sizeof(MAC_HEADER) + 2);
5005
5006 fcb->frame_length = rmf->vl - 4 - 2;
5007 fcb->bdb_ptr->buffer_length = rmf->vl - 4 - 2;
5008
5009 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
5010 return err;
5011
5012 /* Wait for Transmit to Complete */
5013 for(i = 0; i < 10000; i++)
5014 {
5015 if(fcb->frame_status & FCB_COMMAND_DONE)
5016 break;
5017 mdelay(1);
5018 }
5019
5020 /* Check if GOOD frame Tx'ed */
5021 if(!(fcb->frame_status & FCB_COMMAND_DONE))
5022 {
5023 if((err = smctr_issue_resume_tx_fcb_cmd(dev, MAC_QUEUE)))
5024 return err;
5025
5026 for(i = 0; i < 10000; i++)
5027 {
5028 if(fcb->frame_status & FCB_COMMAND_DONE)
5029 break;
5030 mdelay(1);
5031 }
5032
5033 if(!(fcb->frame_status & FCB_COMMAND_DONE))
5034 return HARDWARE_FAILED;
5035 }
5036
5037 *tx_fstatus = fcb->frame_status;
5038
5039 return A_FRAME_WAS_FORWARDED;
5040}
5041
5042static int smctr_set_auth_access_pri(struct net_device *dev,
5043 MAC_SUB_VECTOR *rsv)
5044{
5045 struct net_local *tp = netdev_priv(dev);
5046
5047 if(rsv->svl != S_AUTHORIZED_ACCESS_PRIORITY)
5048 return E_SUB_VECTOR_LENGTH_ERROR;
5049
5050 tp->authorized_access_priority = (rsv->svv[0] << 8 | rsv->svv[1]);
5051
5052 return POSITIVE_ACK;
5053}
5054
5055static int smctr_set_auth_funct_class(struct net_device *dev,
5056 MAC_SUB_VECTOR *rsv)
5057{
5058 struct net_local *tp = netdev_priv(dev);
5059
5060 if(rsv->svl != S_AUTHORIZED_FUNCTION_CLASS)
5061 return E_SUB_VECTOR_LENGTH_ERROR;
5062
5063 tp->authorized_function_classes = (rsv->svv[0] << 8 | rsv->svv[1]);
5064
5065 return POSITIVE_ACK;
5066}
5067
5068static int smctr_set_corr(struct net_device *dev, MAC_SUB_VECTOR *rsv,
5069 __u16 *correlator)
5070{
5071 if(rsv->svl != S_CORRELATOR)
5072 return E_SUB_VECTOR_LENGTH_ERROR;
5073
5074 *correlator = (rsv->svv[0] << 8 | rsv->svv[1]);
5075
5076 return POSITIVE_ACK;
5077}
5078
5079static int smctr_set_error_timer_value(struct net_device *dev,
5080 MAC_SUB_VECTOR *rsv)
5081{
5082 __u16 err_tval;
5083 int err;
5084
5085 if(rsv->svl != S_ERROR_TIMER_VALUE)
5086 return E_SUB_VECTOR_LENGTH_ERROR;
5087
5088 err_tval = (rsv->svv[0] << 8 | rsv->svv[1])*10;
5089
5090 smctr_issue_write_word_cmd(dev, RW_TER_THRESHOLD, &err_tval);
5091
5092 if((err = smctr_wait_cmd(dev)))
5093 return err;
5094
5095 return POSITIVE_ACK;
5096}
5097
5098static int smctr_set_frame_forward(struct net_device *dev,
5099 MAC_SUB_VECTOR *rsv, __u8 dc_sc)
5100{
5101 if((rsv->svl < 2) || (rsv->svl > S_FRAME_FORWARD))
5102 return E_SUB_VECTOR_LENGTH_ERROR;
5103
5104 if((dc_sc & DC_MASK) != DC_CRS)
5105 {
5106 if(rsv->svl >= 2 && rsv->svl < 20)
5107 return E_TRANSMIT_FORWARD_INVALID;
5108
5109 if((rsv->svv[0] != 0) || (rsv->svv[1] != 0))
5110 return E_TRANSMIT_FORWARD_INVALID;
5111 }
5112
5113 return POSITIVE_ACK;
5114}
5115
5116static int smctr_set_local_ring_num(struct net_device *dev,
5117 MAC_SUB_VECTOR *rsv)
5118{
5119 struct net_local *tp = netdev_priv(dev);
5120
5121 if(rsv->svl != S_LOCAL_RING_NUMBER)
5122 return E_SUB_VECTOR_LENGTH_ERROR;
5123
5124 if(tp->ptr_local_ring_num)
5125 *(__u16 *)(tp->ptr_local_ring_num)
5126 = (rsv->svv[0] << 8 | rsv->svv[1]);
5127
5128 return POSITIVE_ACK;
5129}
5130
5131static unsigned short smctr_set_ctrl_attention(struct net_device *dev)
5132{
5133 struct net_local *tp = netdev_priv(dev);
5134 int ioaddr = dev->base_addr;
5135
5136 if(tp->bic_type == BIC_585_CHIP)
5137 outb((tp->trc_mask | HWR_CA), ioaddr + HWR);
5138 else
5139 {
5140 outb((tp->trc_mask | CSR_CA), ioaddr + CSR);
5141 outb(tp->trc_mask, ioaddr + CSR);
5142 }
5143
5144 return 0;
5145}
5146
5147static void smctr_set_multicast_list(struct net_device *dev)
5148{
5149 if(smctr_debug > 10)
5150 printk(KERN_DEBUG "%s: smctr_set_multicast_list\n", dev->name);
5151}
5152
5153static int smctr_set_page(struct net_device *dev, __u8 *buf)
5154{
5155 struct net_local *tp = netdev_priv(dev);
5156 __u8 amask;
5157 __u32 tptr;
5158
5159 tptr = (__u32)buf - (__u32)tp->ram_access;
5160 amask = (__u8)((tptr & PR_PAGE_MASK) >> 8);
5161 outb(amask, dev->base_addr + PR);
5162
5163 return 0;
5164}
5165
5166static int smctr_set_phy_drop(struct net_device *dev, MAC_SUB_VECTOR *rsv)
5167{
5168 int err;
5169
5170 if(rsv->svl != S_PHYSICAL_DROP)
5171 return E_SUB_VECTOR_LENGTH_ERROR;
5172
5173 smctr_issue_write_byte_cmd(dev, RW_PHYSICAL_DROP_NUMBER, &rsv->svv[0]);
5174 if((err = smctr_wait_cmd(dev)))
5175 return err;
5176
5177 return POSITIVE_ACK;
5178}
5179
5180/* Reset the ring speed to the opposite of what it was. This auto-pilot
5181 * mode requires a complete reset and re-init of the adapter.
5182 */
5183static int smctr_set_ring_speed(struct net_device *dev)
5184{
5185 struct net_local *tp = netdev_priv(dev);
5186 int err;
5187
5188 if(tp->media_type == MEDIA_UTP_16)
5189 tp->media_type = MEDIA_UTP_4;
5190 else
5191 tp->media_type = MEDIA_UTP_16;
5192
5193 smctr_enable_16bit(dev);
5194
5195 /* Re-Initialize adapter's internal registers */
5196 smctr_reset_adapter(dev);
5197
5198 if((err = smctr_init_card_real(dev)))
5199 return err;
5200
5201 smctr_enable_bic_int(dev);
5202
5203 if((err = smctr_issue_enable_int_cmd(dev, TRC_INTERRUPT_ENABLE_MASK)))
5204 return err;
5205
5206 smctr_disable_16bit(dev);
5207
5208 return 0;
5209}
5210
5211static int smctr_set_rx_look_ahead(struct net_device *dev)
5212{
5213 struct net_local *tp = netdev_priv(dev);
5214 __u16 sword, rword;
5215
5216 if(smctr_debug > 10)
5217 printk(KERN_DEBUG "%s: smctr_set_rx_look_ahead_flag\n", dev->name);
5218
5219 tp->adapter_flags &= ~(FORCED_16BIT_MODE);
5220 tp->adapter_flags |= RX_VALID_LOOKAHEAD;
5221
5222 if(tp->adapter_bus == BUS_ISA16_TYPE)
5223 {
5224 sword = *((__u16 *)(tp->ram_access));
5225 *((__u16 *)(tp->ram_access)) = 0x1234;
5226
5227 smctr_disable_16bit(dev);
5228 rword = *((__u16 *)(tp->ram_access));
5229 smctr_enable_16bit(dev);
5230
5231 if(rword != 0x1234)
5232 tp->adapter_flags |= FORCED_16BIT_MODE;
5233
5234 *((__u16 *)(tp->ram_access)) = sword;
5235 }
5236
5237 return 0;
5238}
5239
5240static int smctr_set_trc_reset(int ioaddr)
5241{
5242 __u8 r;
5243
5244 r = inb(ioaddr + MSR);
5245 outb(MSR_RST | r, ioaddr + MSR);
5246
5247 return 0;
5248}
5249
5250/*
5251 * This function can be called if the adapter is busy or not.
5252 */
5253static int smctr_setup_single_cmd(struct net_device *dev,
5254 __u16 command, __u16 subcommand)
5255{
5256 struct net_local *tp = netdev_priv(dev);
5257 unsigned int err;
5258
5259 if(smctr_debug > 10)
5260 printk(KERN_DEBUG "%s: smctr_setup_single_cmd\n", dev->name);
5261
5262 if((err = smctr_wait_while_cbusy(dev)))
5263 return err;
5264
5265 if((err = (unsigned int)smctr_wait_cmd(dev)))
5266 return err;
5267
5268 tp->acb_head->cmd_done_status = 0;
5269 tp->acb_head->cmd = command;
5270 tp->acb_head->subcmd = subcommand;
5271
5272 err = smctr_issue_resume_acb_cmd(dev);
5273
5274 return err;
5275}
5276
5277/*
5278 * This function can not be called with the adapter busy.
5279 */
5280static int smctr_setup_single_cmd_w_data(struct net_device *dev,
5281 __u16 command, __u16 subcommand)
5282{
5283 struct net_local *tp = netdev_priv(dev);
5284
5285 tp->acb_head->cmd_done_status = ACB_COMMAND_NOT_DONE;
5286 tp->acb_head->cmd = command;
5287 tp->acb_head->subcmd = subcommand;
5288 tp->acb_head->data_offset_lo
5289 = (__u16)TRC_POINTER(tp->misc_command_data);
5290
5291 return smctr_issue_resume_acb_cmd(dev);
5292}
5293
5294static char *smctr_malloc(struct net_device *dev, __u16 size)
5295{
5296 struct net_local *tp = netdev_priv(dev);
5297 char *m;
5298
5299 m = (char *)(tp->ram_access + tp->sh_mem_used);
5300 tp->sh_mem_used += (__u32)size;
5301
5302 return m;
5303}
5304
5305static int smctr_status_chg(struct net_device *dev)
5306{
5307 struct net_local *tp = netdev_priv(dev);
5308
5309 if(smctr_debug > 10)
5310 printk(KERN_DEBUG "%s: smctr_status_chg\n", dev->name);
5311
5312 switch(tp->status)
5313 {
5314 case OPEN:
5315 break;
5316
5317 case CLOSED:
5318 break;
5319
5320 /* Interrupt driven open() completion. XXX */
5321 case INITIALIZED:
5322 tp->group_address_0 = 0;
5323 tp->group_address[0] = 0;
5324 tp->group_address[1] = 0;
5325 tp->functional_address_0 = 0;
5326 tp->functional_address[0] = 0;
5327 tp->functional_address[1] = 0;
5328 smctr_open_tr(dev);
5329 break;
5330
5331 default:
5332 printk(KERN_INFO "%s: status change unknown %x\n",
5333 dev->name, tp->status);
5334 break;
5335 }
5336
5337 return 0;
5338}
5339
5340static int smctr_trc_send_packet(struct net_device *dev, FCBlock *fcb,
5341 __u16 queue)
5342{
5343 struct net_local *tp = netdev_priv(dev);
5344 int err = 0;
5345
5346 if(smctr_debug > 10)
5347 printk(KERN_DEBUG "%s: smctr_trc_send_packet\n", dev->name);
5348
5349 fcb->info = FCB_CHAIN_END | FCB_ENABLE_TFS;
5350 if(tp->num_tx_fcbs[queue] != 1)
5351 fcb->back_ptr->info = FCB_INTERRUPT_ENABLE | FCB_ENABLE_TFS;
5352
5353 if(tp->tx_queue_status[queue] == NOT_TRANSMITING)
5354 {
5355 tp->tx_queue_status[queue] = TRANSMITING;
5356 err = smctr_issue_resume_tx_fcb_cmd(dev, queue);
5357 }
5358
5359 return err;
5360}
5361
5362static __u16 smctr_tx_complete(struct net_device *dev, __u16 queue)
5363{
5364 struct net_local *tp = netdev_priv(dev);
5365 __u16 status, err = 0;
5366 int cstatus;
5367
5368 if(smctr_debug > 10)
5369 printk(KERN_DEBUG "%s: smctr_tx_complete\n", dev->name);
5370
5371 while((status = tp->tx_fcb_end[queue]->frame_status) != SUCCESS)
5372 {
5373 if(status & 0x7e00 )
5374 {
5375 err = HARDWARE_FAILED;
5376 break;
5377 }
5378
5379 if((err = smctr_update_tx_chain(dev, tp->tx_fcb_end[queue],
5380 queue)) != SUCCESS)
5381 break;
5382
5383 smctr_disable_16bit(dev);
5384
5385 if(tp->mode_bits & UMAC)
5386 {
5387 if(!(status & (FCB_TX_STATUS_AR1 | FCB_TX_STATUS_AR2)))
5388 cstatus = NO_SUCH_DESTINATION;
5389 else
5390 {
5391 if(!(status & (FCB_TX_STATUS_CR1 | FCB_TX_STATUS_CR2)))
5392 cstatus = DEST_OUT_OF_RESOURCES;
5393 else
5394 {
5395 if(status & FCB_TX_STATUS_E)
5396 cstatus = MAX_COLLISIONS;
5397 else
5398 cstatus = SUCCESS;
5399 }
5400 }
5401 }
5402 else
5403 cstatus = SUCCESS;
5404
5405 if(queue == BUG_QUEUE)
5406 err = SUCCESS;
5407
5408 smctr_enable_16bit(dev);
5409 if(err != SUCCESS)
5410 break;
5411 }
5412
5413 return err;
5414}
5415
5416static unsigned short smctr_tx_move_frame(struct net_device *dev,
5417 struct sk_buff *skb, __u8 *pbuff, unsigned int bytes)
5418{
5419 struct net_local *tp = netdev_priv(dev);
5420 unsigned int ram_usable;
5421 __u32 flen, len, offset = 0;
5422 __u8 *frag, *page;
5423
5424 if(smctr_debug > 10)
5425 printk(KERN_DEBUG "%s: smctr_tx_move_frame\n", dev->name);
5426
5427 ram_usable = ((unsigned int)tp->ram_usable) << 10;
5428 frag = skb->data;
5429 flen = skb->len;
5430
5431 while(flen > 0 && bytes > 0)
5432 {
5433 smctr_set_page(dev, pbuff);
5434
5435 offset = SMC_PAGE_OFFSET(pbuff);
5436
5437 if(offset + flen > ram_usable)
5438 len = ram_usable - offset;
5439 else
5440 len = flen;
5441
5442 if(len > bytes)
5443 len = bytes;
5444
5445 page = (char *) (offset + tp->ram_access);
5446 memcpy(page, frag, len);
5447
5448 flen -=len;
5449 bytes -= len;
5450 frag += len;
5451 pbuff += len;
5452 }
5453
5454 return 0;
5455}
5456
5457/* Update the error statistic counters for this adapter. */
5458static int smctr_update_err_stats(struct net_device *dev)
5459{
5460 struct net_local *tp = netdev_priv(dev);
5461 struct tr_statistics *tstat = &tp->MacStat;
5462
5463 if(tstat->internal_errors)
5464 tstat->internal_errors
5465 += *(tp->misc_command_data + 0) & 0x00ff;
5466
5467 if(tstat->line_errors)
5468 tstat->line_errors += *(tp->misc_command_data + 0) >> 8;
5469
5470 if(tstat->A_C_errors)
5471 tstat->A_C_errors += *(tp->misc_command_data + 1) & 0x00ff;
5472
5473 if(tstat->burst_errors)
5474 tstat->burst_errors += *(tp->misc_command_data + 1) >> 8;
5475
5476 if(tstat->abort_delimiters)
5477 tstat->abort_delimiters += *(tp->misc_command_data + 2) >> 8;
5478
5479 if(tstat->recv_congest_count)
5480 tstat->recv_congest_count
5481 += *(tp->misc_command_data + 3) & 0x00ff;
5482
5483 if(tstat->lost_frames)
5484 tstat->lost_frames
5485 += *(tp->misc_command_data + 3) >> 8;
5486
5487 if(tstat->frequency_errors)
5488 tstat->frequency_errors += *(tp->misc_command_data + 4) & 0x00ff;
5489
5490 if(tstat->frame_copied_errors)
5491 tstat->frame_copied_errors
5492 += *(tp->misc_command_data + 4) >> 8;
5493
5494 if(tstat->token_errors)
5495 tstat->token_errors += *(tp->misc_command_data + 5) >> 8;
5496
5497 return 0;
5498}
5499
5500static int smctr_update_rx_chain(struct net_device *dev, __u16 queue)
5501{
5502 struct net_local *tp = netdev_priv(dev);
5503 FCBlock *fcb;
5504 BDBlock *bdb;
5505 __u16 size, len;
5506
5507 fcb = tp->rx_fcb_curr[queue];
5508 len = fcb->frame_length;
5509
5510 fcb->frame_status = 0;
5511 fcb->info = FCB_CHAIN_END;
5512 fcb->back_ptr->info = FCB_WARNING;
5513
5514 tp->rx_fcb_curr[queue] = tp->rx_fcb_curr[queue]->next_ptr;
5515
5516 /* update RX BDBs */
5517 size = (len >> RX_BDB_SIZE_SHIFT);
5518 if(len & RX_DATA_BUFFER_SIZE_MASK)
5519 size += sizeof(BDBlock);
5520 size &= (~RX_BDB_SIZE_MASK);
5521
5522 /* check if wrap around */
5523 bdb = (BDBlock *)((__u32)(tp->rx_bdb_curr[queue]) + (__u32)(size));
5524 if((__u32)bdb >= (__u32)tp->rx_bdb_end[queue])
5525 {
5526 bdb = (BDBlock *)((__u32)(tp->rx_bdb_head[queue])
5527 + (__u32)(bdb) - (__u32)(tp->rx_bdb_end[queue]));
5528 }
5529
5530 bdb->back_ptr->info = BDB_CHAIN_END;
5531 tp->rx_bdb_curr[queue]->back_ptr->info = BDB_NOT_CHAIN_END;
5532 tp->rx_bdb_curr[queue] = bdb;
5533
5534 return 0;
5535}
5536
5537static int smctr_update_tx_chain(struct net_device *dev, FCBlock *fcb,
5538 __u16 queue)
5539{
5540 struct net_local *tp = netdev_priv(dev);
5541
5542 if(smctr_debug > 20)
5543 printk(KERN_DEBUG "smctr_update_tx_chain\n");
5544
5545 if(tp->num_tx_fcbs_used[queue] <= 0)
5546 return HARDWARE_FAILED;
5547 else
5548 {
5549 if(tp->tx_buff_used[queue] < fcb->memory_alloc)
5550 {
5551 tp->tx_buff_used[queue] = 0;
5552 return HARDWARE_FAILED;
5553 }
5554
5555 tp->tx_buff_used[queue] -= fcb->memory_alloc;
5556
5557 /* if all transmit buffer are cleared
5558 * need to set the tx_buff_curr[] to tx_buff_head[]
5559 * otherwise, tx buffer will be segregate and cannot
5560 * accommodate and buffer greater than (curr - head) and
5561 * (end - curr) since we do not allow wrap around allocation.
5562 */
5563 if(tp->tx_buff_used[queue] == 0)
5564 tp->tx_buff_curr[queue] = tp->tx_buff_head[queue];
5565
5566 tp->num_tx_fcbs_used[queue]--;
5567 fcb->frame_status = 0;
5568 tp->tx_fcb_end[queue] = fcb->next_ptr;
5569 netif_wake_queue(dev);
5570 return 0;
5571 }
5572}
5573
5574static int smctr_wait_cmd(struct net_device *dev)
5575{
5576 struct net_local *tp = netdev_priv(dev);
5577 unsigned int loop_count = 0x20000;
5578
5579 if(smctr_debug > 10)
5580 printk(KERN_DEBUG "%s: smctr_wait_cmd\n", dev->name);
5581
5582 while(loop_count)
5583 {
5584 if(tp->acb_head->cmd_done_status & ACB_COMMAND_DONE)
5585 break;
5586 udelay(1);
5587 loop_count--;
5588 }
5589
5590 if(loop_count == 0)
5591 return HARDWARE_FAILED;
5592
5593 if(tp->acb_head->cmd_done_status & 0xff)
5594 return HARDWARE_FAILED;
5595
5596 return 0;
5597}
5598
5599static int smctr_wait_while_cbusy(struct net_device *dev)
5600{
5601 struct net_local *tp = netdev_priv(dev);
5602 unsigned int timeout = 0x20000;
5603 int ioaddr = dev->base_addr;
5604 __u8 r;
5605
5606 if(tp->bic_type == BIC_585_CHIP)
5607 {
5608 while(timeout)
5609 {
5610 r = inb(ioaddr + HWR);
5611 if((r & HWR_CBUSY) == 0)
5612 break;
5613 timeout--;
5614 }
5615 }
5616 else
5617 {
5618 while(timeout)
5619 {
5620 r = inb(ioaddr + CSR);
5621 if((r & CSR_CBUSY) == 0)
5622 break;
5623 timeout--;
5624 }
5625 }
5626
5627 if(timeout)
5628 return 0;
5629 else
5630 return HARDWARE_FAILED;
5631}
5632
5633#ifdef MODULE
5634
5635static struct net_device* dev_smctr[SMCTR_MAX_ADAPTERS];
5636static int io[SMCTR_MAX_ADAPTERS];
5637static int irq[SMCTR_MAX_ADAPTERS];
5638
5639MODULE_LICENSE("GPL");
5640MODULE_FIRMWARE("tr_smctr.bin");
5641
5642module_param_array(io, int, NULL, 0);
5643module_param_array(irq, int, NULL, 0);
5644module_param(ringspeed, int, 0);
5645
5646static struct net_device * __init setup_card(int n)
5647{
5648 struct net_device *dev = alloc_trdev(sizeof(struct net_local));
5649 int err;
5650
5651 if (!dev)
5652 return ERR_PTR(-ENOMEM);
5653
5654 dev->irq = irq[n];
5655 err = smctr_probe1(dev, io[n]);
5656 if (err)
5657 goto out;
5658
5659 err = register_netdev(dev);
5660 if (err)
5661 goto out1;
5662 return dev;
5663 out1:
5664#ifdef CONFIG_MCA_LEGACY
5665 { struct net_local *tp = netdev_priv(dev);
5666 if (tp->slot_num)
5667 mca_mark_as_unused(tp->slot_num);
5668 }
5669#endif
5670 release_region(dev->base_addr, SMCTR_IO_EXTENT);
5671 free_irq(dev->irq, dev);
5672out:
5673 free_netdev(dev);
5674 return ERR_PTR(err);
5675}
5676
5677int __init init_module(void)
5678{
5679 int i, found = 0;
5680 struct net_device *dev;
5681
5682 for(i = 0; i < SMCTR_MAX_ADAPTERS; i++) {
5683 dev = io[0]? setup_card(i) : smctr_probe(-1);
5684 if (!IS_ERR(dev)) {
5685 ++found;
5686 dev_smctr[i] = dev;
5687 }
5688 }
5689
5690 return found ? 0 : -ENODEV;
5691}
5692
5693void __exit cleanup_module(void)
5694{
5695 int i;
5696
5697 for(i = 0; i < SMCTR_MAX_ADAPTERS; i++) {
5698 struct net_device *dev = dev_smctr[i];
5699
5700 if (dev) {
5701
5702 unregister_netdev(dev);
5703#ifdef CONFIG_MCA_LEGACY
5704 { struct net_local *tp = netdev_priv(dev);
5705 if (tp->slot_num)
5706 mca_mark_as_unused(tp->slot_num);
5707 }
5708#endif
5709 release_region(dev->base_addr, SMCTR_IO_EXTENT);
5710 if (dev->irq)
5711 free_irq(dev->irq, dev);
5712
5713 free_netdev(dev);
5714 }
5715 }
5716}
5717#endif /* MODULE */
diff --git a/drivers/net/tokenring/smctr.h b/drivers/net/tokenring/smctr.h
deleted file mode 100644
index 6e5700ab4fc3..000000000000
--- a/drivers/net/tokenring/smctr.h
+++ /dev/null
@@ -1,1585 +0,0 @@
1/* smctr.h: SMC Token Ring driver header for Linux
2 *
3 * Authors:
4 * - Jay Schulist <jschlst@samba.org>
5 */
6
7#ifndef __LINUX_SMCTR_H
8#define __LINUX_SMCTR_H
9
10#ifdef __KERNEL__
11
12#define MAX_TX_QUEUE 10
13
14#define SMC_HEADER_SIZE 14
15
16#define SMC_PAGE_OFFSET(X) (((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask)
17
18#define INIT 0x0D
19#define RQ_ATTCH 0x10
20#define RQ_STATE 0x0F
21#define RQ_ADDR 0x0E
22#define CHG_PARM 0x0C
23#define RSP 0x00
24#define TX_FORWARD 0x09
25
26#define AC_FC_DAT ((3<<13) | 1)
27#define DAT 0x07
28
29#define RPT_NEW_MON 0x25
30#define RPT_SUA_CHG 0x26
31#define RPT_ACTIVE_ERR 0x28
32#define RPT_NN_INCMP 0x27
33#define RPT_ERROR 0x29
34
35#define RQ_INIT 0x20
36#define RPT_ATTCH 0x24
37#define RPT_STATE 0x23
38#define RPT_ADDR 0x22
39
40#define POSITIVE_ACK 0x0001
41#define A_FRAME_WAS_FORWARDED 0x8888
42
43#define GROUP_ADDRESS 0x2B
44#define PHYSICAL_DROP 0x0B
45#define AUTHORIZED_ACCESS_PRIORITY 0x07
46#define AUTHORIZED_FUNCTION_CLASS 0x06
47#define FUNCTIONAL_ADDRESS 0x2C
48#define RING_STATION_STATUS 0x29
49#define TRANSMIT_STATUS_CODE 0x2A
50#define IBM_PASS_SOURCE_ADDR 0x01
51#define AC_FC_RPT_TX_FORWARD ((0<<13) | 0)
52#define AC_FC_RPT_STATE ((0<<13) | 0)
53#define AC_FC_RPT_ADDR ((0<<13) | 0)
54#define CORRELATOR 0x09
55
56#define POSITIVE_ACK 0x0001 /* */
57#define E_MAC_DATA_INCOMPLETE 0x8001 /* not used */
58#define E_VECTOR_LENGTH_ERROR 0x8002 /* */
59#define E_UNRECOGNIZED_VECTOR_ID 0x8003 /* */
60#define E_INAPPROPRIATE_SOURCE_CLASS 0x8004 /* */
61#define E_SUB_VECTOR_LENGTH_ERROR 0x8005 /* */
62#define E_TRANSMIT_FORWARD_INVALID 0x8006 /* def. by IBM */
63#define E_MISSING_SUB_VECTOR 0x8007 /* */
64#define E_SUB_VECTOR_UNKNOWN 0x8008 /* */
65#define E_MAC_HEADER_TOO_LONG 0x8009 /* */
66#define E_FUNCTION_DISABLED 0x800A /* not used */
67
68#define A_FRAME_WAS_FORWARDED 0x8888 /* used by send_TX_FORWARD */
69
70#define UPSTREAM_NEIGHBOR_ADDRESS 0x02
71#define LOCAL_RING_NUMBER 0x03
72#define ASSIGN_PHYSICAL_DROP 0x04
73#define ERROR_TIMER_VALUE 0x05
74#define AUTHORIZED_FUNCTION_CLASS 0x06
75#define AUTHORIZED_ACCESS_PRIORITY 0x07
76#define CORRELATOR 0x09
77#define PHYSICAL_DROP 0x0B
78#define RESPONSE_CODE 0x20
79#define ADDRESS_MODIFER 0x21
80#define PRODUCT_INSTANCE_ID 0x22
81#define RING_STATION_VERSION_NUMBER 0x23
82#define WRAP_DATA 0x26
83#define FRAME_FORWARD 0x27
84#define STATION_IDENTIFER 0x28
85#define RING_STATION_STATUS 0x29
86#define TRANSMIT_STATUS_CODE 0x2A
87#define GROUP_ADDRESS 0x2B
88#define FUNCTIONAL_ADDRESS 0x2C
89
90#define F_NO_SUB_VECTORS_FOUND 0x0000
91#define F_UPSTREAM_NEIGHBOR_ADDRESS 0x0001
92#define F_LOCAL_RING_NUMBER 0x0002
93#define F_ASSIGN_PHYSICAL_DROP 0x0004
94#define F_ERROR_TIMER_VALUE 0x0008
95#define F_AUTHORIZED_FUNCTION_CLASS 0x0010
96#define F_AUTHORIZED_ACCESS_PRIORITY 0x0020
97#define F_CORRELATOR 0x0040
98#define F_PHYSICAL_DROP 0x0080
99#define F_RESPONSE_CODE 0x0100
100#define F_PRODUCT_INSTANCE_ID 0x0200
101#define F_RING_STATION_VERSION_NUMBER 0x0400
102#define F_STATION_IDENTIFER 0x0800
103#define F_RING_STATION_STATUS 0x1000
104#define F_GROUP_ADDRESS 0x2000
105#define F_FUNCTIONAL_ADDRESS 0x4000
106#define F_FRAME_FORWARD 0x8000
107
108#define R_INIT 0x00
109#define R_RQ_ATTCH_STATE_ADDR 0x00
110#define R_CHG_PARM 0x00
111#define R_TX_FORWARD F_FRAME_FORWARD
112
113
114#define UPSTREAM_NEIGHBOR_ADDRESS 0x02
115#define ADDRESS_MODIFER 0x21
116#define RING_STATION_VERSION_NUMBER 0x23
117#define PRODUCT_INSTANCE_ID 0x22
118
119#define RPT_TX_FORWARD 0x2A
120
121#define AC_FC_INIT (3<<13) | 0 /* */
122#define AC_FC_RQ_INIT ((3<<13) | 0) /* */
123#define AC_FC_RQ_ATTCH (3<<13) | 0 /* DC = SC of rx frame */
124#define AC_FC_RQ_STATE (3<<13) | 0 /* DC = SC of rx frame */
125#define AC_FC_RQ_ADDR (3<<13) | 0 /* DC = SC of rx frame */
126#define AC_FC_CHG_PARM (3<<13) | 0 /* */
127#define AC_FC_RSP (0<<13) | 0 /* DC = SC of rx frame */
128#define AC_FC_RPT_ATTCH (0<<13) | 0
129
130#define S_UPSTREAM_NEIGHBOR_ADDRESS 6 + 2
131#define S_LOCAL_RING_NUMBER 2 + 2
132#define S_ASSIGN_PHYSICAL_DROP 4 + 2
133#define S_ERROR_TIMER_VALUE 2 + 2
134#define S_AUTHORIZED_FUNCTION_CLASS 2 + 2
135#define S_AUTHORIZED_ACCESS_PRIORITY 2 + 2
136#define S_CORRELATOR 2 + 2
137#define S_PHYSICAL_DROP 4 + 2
138#define S_RESPONSE_CODE 4 + 2
139#define S_ADDRESS_MODIFER 2 + 2
140#define S_PRODUCT_INSTANCE_ID 18 + 2
141#define S_RING_STATION_VERSION_NUMBER 10 + 2
142#define S_STATION_IDENTIFER 6 + 2
143#define S_RING_STATION_STATUS 6 + 2
144#define S_GROUP_ADDRESS 4 + 2
145#define S_FUNCTIONAL_ADDRESS 4 + 2
146#define S_FRAME_FORWARD 252 + 2
147#define S_TRANSMIT_STATUS_CODE 2 + 2
148
149#define ISB_IMC_RES0 0x0000 /* */
150#define ISB_IMC_MAC_TYPE_3 0x0001 /* MAC_ARC_INDICATE */
151#define ISB_IMC_MAC_ERROR_COUNTERS 0x0002 /* */
152#define ISB_IMC_RES1 0x0003 /* */
153#define ISB_IMC_MAC_TYPE_2 0x0004 /* QUE_MAC_INDICATE */
154#define ISB_IMC_TX_FRAME 0x0005 /* */
155#define ISB_IMC_END_OF_TX_QUEUE 0x0006 /* */
156#define ISB_IMC_NON_MAC_RX_RESOURCE 0x0007 /* */
157#define ISB_IMC_MAC_RX_RESOURCE 0x0008 /* */
158#define ISB_IMC_NON_MAC_RX_FRAME 0x0009 /* */
159#define ISB_IMC_MAC_RX_FRAME 0x000A /* */
160#define ISB_IMC_TRC_FIFO_STATUS 0x000B /* */
161#define ISB_IMC_COMMAND_STATUS 0x000C /* */
162#define ISB_IMC_MAC_TYPE_1 0x000D /* Self Removed */
163#define ISB_IMC_TRC_INTRNL_TST_STATUS 0x000E /* */
164#define ISB_IMC_RES2 0x000F /* */
165
166#define NON_MAC_RX_RESOURCE_BW 0x10 /* shifted right 8 bits */
167#define NON_MAC_RX_RESOURCE_FW 0x20 /* shifted right 8 bits */
168#define NON_MAC_RX_RESOURCE_BE 0x40 /* shifted right 8 bits */
169#define NON_MAC_RX_RESOURCE_FE 0x80 /* shifted right 8 bits */
170#define RAW_NON_MAC_RX_RESOURCE_BW 0x1000 /* */
171#define RAW_NON_MAC_RX_RESOURCE_FW 0x2000 /* */
172#define RAW_NON_MAC_RX_RESOURCE_BE 0x4000 /* */
173#define RAW_NON_MAC_RX_RESOURCE_FE 0x8000 /* */
174
175#define MAC_RX_RESOURCE_BW 0x10 /* shifted right 8 bits */
176#define MAC_RX_RESOURCE_FW 0x20 /* shifted right 8 bits */
177#define MAC_RX_RESOURCE_BE 0x40 /* shifted right 8 bits */
178#define MAC_RX_RESOURCE_FE 0x80 /* shifted right 8 bits */
179#define RAW_MAC_RX_RESOURCE_BW 0x1000 /* */
180#define RAW_MAC_RX_RESOURCE_FW 0x2000 /* */
181#define RAW_MAC_RX_RESOURCE_BE 0x4000 /* */
182#define RAW_MAC_RX_RESOURCE_FE 0x8000 /* */
183
184#define TRC_FIFO_STATUS_TX_UNDERRUN 0x40 /* shifted right 8 bits */
185#define TRC_FIFO_STATUS_RX_OVERRUN 0x80 /* shifted right 8 bits */
186#define RAW_TRC_FIFO_STATUS_TX_UNDERRUN 0x4000 /* */
187#define RAW_TRC_FIFO_STATUS_RX_OVERRUN 0x8000 /* */
188
189#define CSR_CLRTINT 0x08
190
191#define MSB(X) ((__u8)((__u16) X >> 8))
192#define LSB(X) ((__u8)((__u16) X & 0xff))
193
194#define AC_FC_LOBE_MEDIA_TEST ((3<<13) | 0)
195#define S_WRAP_DATA 248 + 2 /* 500 + 2 */
196#define WRAP_DATA 0x26
197#define LOBE_MEDIA_TEST 0x08
198
199/* Destination Class (dc) */
200
201#define DC_MASK 0xF0
202#define DC_RS 0x00
203#define DC_CRS 0x40
204#define DC_RPS 0x50
205#define DC_REM 0x60
206
207/* Source Classes (sc) */
208
209#define SC_MASK 0x0F
210#define SC_RS 0x00
211#define SC_CRS 0x04
212#define SC_RPS 0x05
213#define SC_REM 0x06
214
215#define PR 0x11
216#define PR_PAGE_MASK 0x0C000
217
218#define MICROCHANNEL 0x0008
219#define INTERFACE_CHIP 0x0010
220#define BOARD_16BIT 0x0040
221#define PAGED_RAM 0x0080
222#define WD8115TA (TOKEN_MEDIA | MICROCHANNEL | INTERFACE_CHIP | PAGED_RAM)
223#define WD8115T (TOKEN_MEDIA | INTERFACE_CHIP | BOARD_16BIT | PAGED_RAM)
224
225#define BRD_ID_8316 0x50
226
227#define r587_SER 0x001
228#define SER_DIN 0x80
229#define SER_DOUT 0x40
230#define SER_CLK 0x20
231#define SER_ECS 0x10
232#define SER_E806 0x08
233#define SER_PNP 0x04
234#define SER_BIO 0x02
235#define SER_16B 0x01
236
237#define r587_IDR 0x004
238#define IDR_IRQ_MASK 0x0F0
239#define IDR_DCS_MASK 0x007
240#define IDR_RWS 0x008
241
242
243#define r587_BIO 0x003
244#define BIO_ENB 0x080
245#define BIO_MASK 0x03F
246
247#define r587_PCR 0x005
248#define PCR_RAMS 0x040
249
250
251
252#define NUM_ADDR_BITS 8
253
254#define ISA_MAX_ADDRESS 0x00ffffff
255
256#define SMCTR_MAX_ADAPTERS 7
257
258#define MC_TABLE_ENTRIES 16
259
260#define MAXFRAGMENTS 32
261
262#define CHIP_REV_MASK 0x3000
263
264#define MAX_TX_QS 8
265#define NUM_TX_QS_USED 3
266
267#define MAX_RX_QS 2
268#define NUM_RX_QS_USED 2
269
270#define INTEL_DATA_FORMAT 0x4000
271#define INTEL_ADDRESS_POINTER_FORMAT 0x8000
272#define PAGE_POINTER(X) ((((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask) + tp->ram_access)
273#define SWAP_WORDS(X) (((X & 0xFFFF) << 16) | (X >> 16))
274
275#define INTERFACE_CHIP 0x0010 /* Soft Config Adapter */
276#define ADVANCED_FEATURES 0x0020 /* Adv. netw. interface features */
277#define BOARD_16BIT 0x0040 /* 16 bit capability */
278#define PAGED_RAM 0x0080 /* Adapter has paged RAM */
279
280#define PAGED_ROM 0x0100 /* Adapter has paged ROM */
281
282#define RAM_SIZE_UNKNOWN 0x0000 /* Unknown RAM size */
283#define RAM_SIZE_0K 0x0001 /* 0K RAM */
284#define RAM_SIZE_8K 0x0002 /* 8k RAM */
285#define RAM_SIZE_16K 0x0003 /* 16k RAM */
286#define RAM_SIZE_32K 0x0004 /* 32k RAM */
287#define RAM_SIZE_64K 0x0005 /* 64k RAM */
288#define RAM_SIZE_RESERVED_6 0x0006 /* Reserved RAM size */
289#define RAM_SIZE_RESERVED_7 0x0007 /* Reserved RAM size */
290#define RAM_SIZE_MASK 0x0007 /* Isolates RAM Size */
291
292#define TOKEN_MEDIA 0x0005
293
294#define BID_REG_0 0x00
295#define BID_REG_1 0x01
296#define BID_REG_2 0x02
297#define BID_REG_3 0x03
298#define BID_REG_4 0x04
299#define BID_REG_5 0x05
300#define BID_REG_6 0x06
301#define BID_REG_7 0x07
302#define BID_LAR_0 0x08
303#define BID_LAR_1 0x09
304#define BID_LAR_2 0x0A
305#define BID_LAR_3 0x0B
306#define BID_LAR_4 0x0C
307#define BID_LAR_5 0x0D
308
309#define BID_BOARD_ID_BYTE 0x0E
310#define BID_CHCKSM_BYTE 0x0F
311#define BID_LAR_OFFSET 0x08
312
313#define BID_MSZ_583_BIT 0x08
314#define BID_SIXTEEN_BIT_BIT 0x01
315
316#define BID_BOARD_REV_MASK 0x1E
317
318#define BID_MEDIA_TYPE_BIT 0x01
319#define BID_SOFT_CONFIG_BIT 0x20
320#define BID_RAM_SIZE_BIT 0x40
321#define BID_BUS_TYPE_BIT 0x80
322
323#define BID_CR 0x10
324
325#define BID_TXP 0x04 /* Transmit Packet Command */
326
327#define BID_TCR_DIFF 0x0D /* Transmit Configuration Register */
328
329#define BID_TCR_VAL 0x18 /* Value to Test 8390 or 690 */
330#define BID_PS0 0x00 /* Register Page Select 0 */
331#define BID_PS1 0x40 /* Register Page Select 1 */
332#define BID_PS2 0x80 /* Register Page Select 2 */
333#define BID_PS_MASK 0x3F /* For Masking Off Page Select Bits */
334
335#define BID_EEPROM_0 0x08
336#define BID_EEPROM_1 0x09
337#define BID_EEPROM_2 0x0A
338#define BID_EEPROM_3 0x0B
339#define BID_EEPROM_4 0x0C
340#define BID_EEPROM_5 0x0D
341#define BID_EEPROM_6 0x0E
342#define BID_EEPROM_7 0x0F
343
344#define BID_OTHER_BIT 0x02
345#define BID_ICR_MASK 0x0C
346#define BID_EAR_MASK 0x0F
347#define BID_ENGR_PAGE 0x0A0
348#define BID_RLA 0x10
349#define BID_EA6 0x80
350#define BID_RECALL_DONE_MASK 0x10
351#define BID_BID_EEPROM_OVERRIDE 0xFFB0
352#define BID_EXTRA_EEPROM_OVERRIDE 0xFFD0
353#define BID_EEPROM_MEDIA_MASK 0x07
354#define BID_STARLAN_TYPE 0x00
355#define BID_ETHERNET_TYPE 0x01
356#define BID_TP_TYPE 0x02
357#define BID_EW_TYPE 0x03
358#define BID_TOKEN_RING_TYPE 0x04
359#define BID_UTP2_TYPE 0x05
360#define BID_EEPROM_IRQ_MASK 0x18
361#define BID_PRIMARY_IRQ 0x00
362#define BID_ALTERNATE_IRQ_1 0x08
363#define BID_ALTERNATE_IRQ_2 0x10
364#define BID_ALTERNATE_IRQ_3 0x18
365#define BID_EEPROM_RAM_SIZE_MASK 0xE0
366#define BID_EEPROM_RAM_SIZE_RES1 0x00
367#define BID_EEPROM_RAM_SIZE_RES2 0x20
368#define BID_EEPROM_RAM_SIZE_8K 0x40
369#define BID_EEPROM_RAM_SIZE_16K 0x60
370#define BID_EEPROM_RAM_SIZE_32K 0x80
371#define BID_EEPROM_RAM_SIZE_64K 0xA0
372#define BID_EEPROM_RAM_SIZE_RES3 0xC0
373#define BID_EEPROM_RAM_SIZE_RES4 0xE0
374#define BID_EEPROM_BUS_TYPE_MASK 0x07
375#define BID_EEPROM_BUS_TYPE_AT 0x00
376#define BID_EEPROM_BUS_TYPE_MCA 0x01
377#define BID_EEPROM_BUS_TYPE_EISA 0x02
378#define BID_EEPROM_BUS_TYPE_NEC 0x03
379#define BID_EEPROM_BUS_SIZE_MASK 0x18
380#define BID_EEPROM_BUS_SIZE_8BIT 0x00
381#define BID_EEPROM_BUS_SIZE_16BIT 0x08
382#define BID_EEPROM_BUS_SIZE_32BIT 0x10
383#define BID_EEPROM_BUS_SIZE_64BIT 0x18
384#define BID_EEPROM_BUS_MASTER 0x20
385#define BID_EEPROM_RAM_PAGING 0x40
386#define BID_EEPROM_ROM_PAGING 0x80
387#define BID_EEPROM_PAGING_MASK 0xC0
388#define BID_EEPROM_LOW_COST 0x08
389#define BID_EEPROM_IO_MAPPED 0x10
390#define BID_EEPROM_HMI 0x01
391#define BID_EEPROM_AUTO_MEDIA_DETECT 0x01
392#define BID_EEPROM_CHIP_REV_MASK 0x0C
393
394#define BID_EEPROM_LAN_ADDR 0x30
395
396#define BID_EEPROM_MEDIA_OPTION 0x54
397#define BID_EEPROM_MEDIA_UTP 0x01
398#define BID_EEPROM_4MB_RING 0x08
399#define BID_EEPROM_16MB_RING 0x10
400#define BID_EEPROM_MEDIA_STP 0x40
401
402#define BID_EEPROM_MISC_DATA 0x56
403#define BID_EEPROM_EARLY_TOKEN_RELEASE 0x02
404
405#define CNFG_ID_8003E 0x6fc0
406#define CNFG_ID_8003S 0x6fc1
407#define CNFG_ID_8003W 0x6fc2
408#define CNFG_ID_8115TRA 0x6ec6
409#define CNFG_ID_8013E 0x61C8
410#define CNFG_ID_8013W 0x61C9
411#define CNFG_ID_BISTRO03E 0xEFE5
412#define CNFG_ID_BISTRO13E 0xEFD5
413#define CNFG_ID_BISTRO13W 0xEFD4
414#define CNFG_MSR_583 0x0
415#define CNFG_ICR_583 0x1
416#define CNFG_IAR_583 0x2
417#define CNFG_BIO_583 0x3
418#define CNFG_EAR_583 0x3
419#define CNFG_IRR_583 0x4
420#define CNFG_LAAR_584 0x5
421#define CNFG_GP2 0x7
422#define CNFG_LAAR_MASK 0x1F
423#define CNFG_LAAR_ZWS 0x20
424#define CNFG_LAAR_L16E 0x40
425#define CNFG_ICR_IR2_584 0x04
426#define CNFG_ICR_MASK 0x08
427#define CNFG_ICR_MSZ 0x08
428#define CNFG_ICR_RLA 0x10
429#define CNFG_ICR_STO 0x80
430#define CNFG_IRR_IRQS 0x60
431#define CNFG_IRR_IEN 0x80
432#define CNFG_IRR_ZWS 0x01
433#define CNFG_GP2_BOOT_NIBBLE 0x0F
434#define CNFG_IRR_OUT2 0x04
435#define CNFG_IRR_OUT1 0x02
436
437#define CNFG_SIZE_8KB 8
438#define CNFG_SIZE_16KB 16
439#define CNFG_SIZE_32KB 32
440#define CNFG_SIZE_64KB 64
441#define CNFG_SIZE_128KB 128
442#define CNFG_SIZE_256KB 256
443#define ROM_DISABLE 0x0
444
445#define CNFG_SLOT_ENABLE_BIT 0x08
446
447#define CNFG_POS_CONTROL_REG 0x096
448#define CNFG_POS_REG0 0x100
449#define CNFG_POS_REG1 0x101
450#define CNFG_POS_REG2 0x102
451#define CNFG_POS_REG3 0x103
452#define CNFG_POS_REG4 0x104
453#define CNFG_POS_REG5 0x105
454
455#define CNFG_ADAPTER_TYPE_MASK 0x0e
456
457#define SLOT_16BIT 0x0008
458#define INTERFACE_5X3_CHIP 0x0000 /* 0000 = 583 or 593 chips */
459#define NIC_690_BIT 0x0010 /* NIC is 690 */
460#define ALTERNATE_IRQ_BIT 0x0020 /* Alternate IRQ is used */
461#define INTERFACE_584_CHIP 0x0040 /* 0001 = 584 chip */
462#define INTERFACE_594_CHIP 0x0080 /* 0010 = 594 chip */
463#define INTERFACE_585_CHIP 0x0100 /* 0100 = 585/790 chip */
464#define INTERFACE_CHIP_MASK 0x03C0 /* Isolates Intfc Chip Type */
465
466#define BOARD_16BIT 0x0040
467#define NODE_ADDR_CKSUM 0xEE
468#define BRD_ID_8115T 0x04
469
470#define NIC_825_BIT 0x0400 /* TRC 83C825 NIC */
471#define NIC_790_BIT 0x0800 /* NIC is 83C790 Ethernet */
472
473#define CHIP_REV_MASK 0x3000
474
475#define HWR_CBUSY 0x02
476#define HWR_CA 0x01
477
478#define MAC_QUEUE 0
479#define NON_MAC_QUEUE 1
480#define BUG_QUEUE 2 /* NO RECEIVE QUEUE, ONLY TX */
481
482#define NUM_MAC_TX_FCBS 8
483#define NUM_MAC_TX_BDBS NUM_MAC_TX_FCBS
484#define NUM_MAC_RX_FCBS 7
485#define NUM_MAC_RX_BDBS 8
486
487#define NUM_NON_MAC_TX_FCBS 6
488#define NUM_NON_MAC_TX_BDBS NUM_NON_MAC_TX_FCBS
489
490#define NUM_NON_MAC_RX_BDBS 0 /* CALCULATED DYNAMICALLY */
491
492#define NUM_BUG_TX_FCBS 8
493#define NUM_BUG_TX_BDBS NUM_BUG_TX_FCBS
494
495#define MAC_TX_BUFFER_MEMORY 1024
496#define NON_MAC_TX_BUFFER_MEMORY (20 * 1024)
497#define BUG_TX_BUFFER_MEMORY (NUM_BUG_TX_FCBS * 32)
498
499#define RX_BUFFER_MEMORY 0 /* CALCULATED DYNAMICALLY */
500#define RX_DATA_BUFFER_SIZE 256
501#define RX_BDB_SIZE_SHIFT 3 /* log2(RX_DATA_BUFFER_SIZE)-log2(sizeof(BDBlock)) */
502#define RX_BDB_SIZE_MASK (sizeof(BDBlock) - 1)
503#define RX_DATA_BUFFER_SIZE_MASK (RX_DATA_BUFFER_SIZE-1)
504
505#define NUM_OF_INTERRUPTS 0x20
506
507#define NOT_TRANSMITING 0
508#define TRANSMITING 1
509
510#define TRC_INTERRUPT_ENABLE_MASK 0x7FF6
511
512#define UCODE_VERSION 0x58
513
514#define UCODE_SIZE_OFFSET 0x0000 /* WORD */
515#define UCODE_CHECKSUM_OFFSET 0x0002 /* WORD */
516#define UCODE_VERSION_OFFSET 0x0004 /* BYTE */
517
518#define CS_RAM_SIZE 0X2000
519#define CS_RAM_CHECKSUM_OFFSET 0x1FFE /* WORD 1FFE(MSB)-1FFF(LSB)*/
520#define CS_RAM_VERSION_OFFSET 0x1FFC /* WORD 1FFC(MSB)-1FFD(LSB)*/
521
522#define MISC_DATA_SIZE 128
523#define NUM_OF_ACBS 1
524
525#define ACB_COMMAND_NOT_DONE 0x0000 /* Init, command not done */
526#define ACB_COMMAND_DONE 0x8000 /* TRC says command done */
527#define ACB_COMMAND_STATUS_MASK 0x00FF /* low byte is status */
528#define ACB_COMMAND_SUCCESSFUL 0x0000 /* means cmd was successful */
529#define ACB_NOT_CHAIN_END 0x0000 /* tell TRC more CBs in chain */
530#define ACB_CHAIN_END 0x8000 /* tell TRC last CB in chain */
531#define ACB_COMMAND_NO_INTERRUPT 0x0000 /* tell TRC no INT after CB */
532#define ACB_COMMAND_INTERRUPT 0x2000 /* tell TRC to INT after CB */
533#define ACB_SUB_CMD_NOP 0x0000
534#define ACB_CMD_HIC_NOP 0x0080
535#define ACB_CMD_MCT_NOP 0x0000
536#define ACB_CMD_MCT_TEST 0x0001
537#define ACB_CMD_HIC_TEST 0x0081
538#define ACB_CMD_INSERT 0x0002
539#define ACB_CMD_REMOVE 0x0003
540#define ACB_CMD_MCT_WRITE_VALUE 0x0004
541#define ACB_CMD_HIC_WRITE_VALUE 0x0084
542#define ACB_CMD_MCT_READ_VALUE 0x0005
543#define ACB_CMD_HIC_READ_VALUE 0x0085
544#define ACB_CMD_INIT_TX_RX 0x0086
545#define ACB_CMD_INIT_TRC_TIMERS 0x0006
546#define ACB_CMD_READ_TRC_STATUS 0x0007
547#define ACB_CMD_CHANGE_JOIN_STATE 0x0008
548#define ACB_CMD_RESERVED_9 0x0009
549#define ACB_CMD_RESERVED_A 0x000A
550#define ACB_CMD_RESERVED_B 0x000B
551#define ACB_CMD_RESERVED_C 0x000C
552#define ACB_CMD_RESERVED_D 0x000D
553#define ACB_CMD_RESERVED_E 0x000E
554#define ACB_CMD_RESERVED_F 0x000F
555
556#define TRC_MAC_REGISTERS_TEST 0x0000
557#define TRC_INTERNAL_LOOPBACK 0x0001
558#define TRC_TRI_LOOPBACK 0x0002
559#define TRC_INTERNAL_ROM_TEST 0x0003
560#define TRC_LOBE_MEDIA_TEST 0x0004
561#define TRC_ANALOG_TEST 0x0005
562#define TRC_HOST_INTERFACE_REG_TEST 0x0003
563
564#define TEST_DMA_1 0x0000
565#define TEST_DMA_2 0x0001
566#define TEST_MCT_ROM 0x0002
567#define HIC_INTERNAL_DIAG 0x0003
568
569#define ABORT_TRANSMIT_PRIORITY_0 0x0001
570#define ABORT_TRANSMIT_PRIORITY_1 0x0002
571#define ABORT_TRANSMIT_PRIORITY_2 0x0004
572#define ABORT_TRANSMIT_PRIORITY_3 0x0008
573#define ABORT_TRANSMIT_PRIORITY_4 0x0010
574#define ABORT_TRANSMIT_PRIORITY_5 0x0020
575#define ABORT_TRANSMIT_PRIORITY_6 0x0040
576#define ABORT_TRANSMIT_PRIORITY_7 0x0080
577
578#define TX_PENDING_PRIORITY_0 0x0001
579#define TX_PENDING_PRIORITY_1 0x0002
580#define TX_PENDING_PRIORITY_2 0x0004
581#define TX_PENDING_PRIORITY_3 0x0008
582#define TX_PENDING_PRIORITY_4 0x0010
583#define TX_PENDING_PRIORITY_5 0x0020
584#define TX_PENDING_PRIORITY_6 0x0040
585#define TX_PENDING_PRIORITY_7 0x0080
586
587#define FCB_FRAME_LENGTH 0x100
588#define FCB_COMMAND_DONE 0x8000 /* FCB Word 0 */
589#define FCB_NOT_CHAIN_END 0x0000 /* FCB Word 1 */
590#define FCB_CHAIN_END 0x8000
591#define FCB_NO_WARNING 0x0000
592#define FCB_WARNING 0x4000
593#define FCB_INTERRUPT_DISABLE 0x0000
594#define FCB_INTERRUPT_ENABLE 0x2000
595
596#define FCB_ENABLE_IMA 0x0008
597#define FCB_ENABLE_TES 0x0004 /* Guarantee Tx before Int */
598#define FCB_ENABLE_TFS 0x0002 /* Post Tx Frame Status */
599#define FCB_ENABLE_NTC 0x0001 /* No Tx CRC */
600
601#define FCB_TX_STATUS_CR2 0x0004
602#define FCB_TX_STATUS_AR2 0x0008
603#define FCB_TX_STATUS_CR1 0x0040
604#define FCB_TX_STATUS_AR1 0x0080
605#define FCB_TX_AC_BITS (FCB_TX_STATUS_AR1+FCB_TX_STATUS_AR2+FCB_TX_STATUS_CR1+FCB_TX_STATUS_CR2)
606#define FCB_TX_STATUS_E 0x0100
607
608#define FCB_RX_STATUS_ANY_ERROR 0x0001
609#define FCB_RX_STATUS_FCS_ERROR 0x0002
610
611#define FCB_RX_STATUS_IA_MATCHED 0x0400
612#define FCB_RX_STATUS_IGA_BSGA_MATCHED 0x0500
613#define FCB_RX_STATUS_FA_MATCHED 0x0600
614#define FCB_RX_STATUS_BA_MATCHED 0x0700
615#define FCB_RX_STATUS_DA_MATCHED 0x0400
616#define FCB_RX_STATUS_SOURCE_ROUTING 0x0800
617
618#define BDB_BUFFER_SIZE 0x100
619#define BDB_NOT_CHAIN_END 0x0000
620#define BDB_CHAIN_END 0x8000
621#define BDB_NO_WARNING 0x0000
622#define BDB_WARNING 0x4000
623
624#define ERROR_COUNTERS_CHANGED 0x0001
625#define TI_NDIS_RING_STATUS_CHANGED 0x0002
626#define UNA_CHANGED 0x0004
627#define READY_TO_SEND_RQ_INIT 0x0008
628
629#define SCGB_ADDRESS_POINTER_FORMAT INTEL_ADDRESS_POINTER_FORMAT
630#define SCGB_DATA_FORMAT INTEL_DATA_FORMAT
631#define SCGB_MULTI_WORD_CONTROL 0
632#define SCGB_BURST_LENGTH 0x000E /* DMA Burst Length */
633
634#define SCGB_CONFIG (INTEL_ADDRESS_POINTER_FORMAT+INTEL_DATA_FORMAT+SCGB_BURST_LENGTH)
635
636#define ISCP_BLOCK_SIZE 0x0A
637#define RAM_SIZE 0x10000
638#define INIT_SYS_CONFIG_PTR_OFFSET (RAM_SIZE-ISCP_BLOCK_SIZE)
639#define SCGP_BLOCK_OFFSET 0
640
641#define SCLB_NOT_VALID 0x0000 /* Initially, SCLB not valid */
642#define SCLB_VALID 0x8000 /* Host tells TRC SCLB valid */
643#define SCLB_PROCESSED 0x0000 /* TRC says SCLB processed */
644#define SCLB_RESUME_CONTROL_NOT_VALID 0x0000 /* Initially, RC not valid */
645#define SCLB_RESUME_CONTROL_VALID 0x4000 /* Host tells TRC RC valid */
646#define SCLB_IACK_CODE_NOT_VALID 0x0000 /* Initially, IACK not valid */
647#define SCLB_IACK_CODE_VALID 0x2000 /* Host tells TRC IACK valid */
648#define SCLB_CMD_NOP 0x0000
649#define SCLB_CMD_REMOVE 0x0001
650#define SCLB_CMD_SUSPEND_ACB_CHAIN 0x0002
651#define SCLB_CMD_SET_INTERRUPT_MASK 0x0003
652#define SCLB_CMD_CLEAR_INTERRUPT_MASK 0x0004
653#define SCLB_CMD_RESERVED_5 0x0005
654#define SCLB_CMD_RESERVED_6 0x0006
655#define SCLB_CMD_RESERVED_7 0x0007
656#define SCLB_CMD_RESERVED_8 0x0008
657#define SCLB_CMD_RESERVED_9 0x0009
658#define SCLB_CMD_RESERVED_A 0x000A
659#define SCLB_CMD_RESERVED_B 0x000B
660#define SCLB_CMD_RESERVED_C 0x000C
661#define SCLB_CMD_RESERVED_D 0x000D
662#define SCLB_CMD_RESERVED_E 0x000E
663#define SCLB_CMD_RESERVED_F 0x000F
664
665#define SCLB_RC_ACB 0x0001 /* Action Command Block Chain */
666#define SCLB_RC_RES0 0x0002 /* Always Zero */
667#define SCLB_RC_RES1 0x0004 /* Always Zero */
668#define SCLB_RC_RES2 0x0008 /* Always Zero */
669#define SCLB_RC_RX_MAC_FCB 0x0010 /* RX_MAC_FCB Chain */
670#define SCLB_RC_RX_MAC_BDB 0x0020 /* RX_MAC_BDB Chain */
671#define SCLB_RC_RX_NON_MAC_FCB 0x0040 /* RX_NON_MAC_FCB Chain */
672#define SCLB_RC_RX_NON_MAC_BDB 0x0080 /* RX_NON_MAC_BDB Chain */
673#define SCLB_RC_TFCB0 0x0100 /* TX Priority 0 FCB Chain */
674#define SCLB_RC_TFCB1 0x0200 /* TX Priority 1 FCB Chain */
675#define SCLB_RC_TFCB2 0x0400 /* TX Priority 2 FCB Chain */
676#define SCLB_RC_TFCB3 0x0800 /* TX Priority 3 FCB Chain */
677#define SCLB_RC_TFCB4 0x1000 /* TX Priority 4 FCB Chain */
678#define SCLB_RC_TFCB5 0x2000 /* TX Priority 5 FCB Chain */
679#define SCLB_RC_TFCB6 0x4000 /* TX Priority 6 FCB Chain */
680#define SCLB_RC_TFCB7 0x8000 /* TX Priority 7 FCB Chain */
681
682#define SCLB_IMC_RES0 0x0001 /* */
683#define SCLB_IMC_MAC_TYPE_3 0x0002 /* MAC_ARC_INDICATE */
684#define SCLB_IMC_MAC_ERROR_COUNTERS 0x0004 /* */
685#define SCLB_IMC_RES1 0x0008 /* */
686#define SCLB_IMC_MAC_TYPE_2 0x0010 /* QUE_MAC_INDICATE */
687#define SCLB_IMC_TX_FRAME 0x0020 /* */
688#define SCLB_IMC_END_OF_TX_QUEUE 0x0040 /* */
689#define SCLB_IMC_NON_MAC_RX_RESOURCE 0x0080 /* */
690#define SCLB_IMC_MAC_RX_RESOURCE 0x0100 /* */
691#define SCLB_IMC_NON_MAC_RX_FRAME 0x0200 /* */
692#define SCLB_IMC_MAC_RX_FRAME 0x0400 /* */
693#define SCLB_IMC_TRC_FIFO_STATUS 0x0800 /* */
694#define SCLB_IMC_COMMAND_STATUS 0x1000 /* */
695#define SCLB_IMC_MAC_TYPE_1 0x2000 /* Self Removed */
696#define SCLB_IMC_TRC_INTRNL_TST_STATUS 0x4000 /* */
697#define SCLB_IMC_RES2 0x8000 /* */
698
699#define DMA_TRIGGER 0x0004
700#define FREQ_16MB_BIT 0x0010
701#define THDREN 0x0020
702#define CFG0_RSV1 0x0040
703#define CFG0_RSV2 0x0080
704#define ETREN 0x0100
705#define RX_OWN_BIT 0x0200
706#define RXATMAC 0x0400
707#define PROMISCUOUS_BIT 0x0800
708#define USETPT 0x1000
709#define SAVBAD_BIT 0x2000
710#define ONEQUE 0x4000
711#define NO_AUTOREMOVE 0x8000
712
713#define RX_FCB_AREA_8316 0x00000000
714#define RX_BUFF_AREA_8316 0x00000000
715
716#define TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access)
717#define RX_FCB_TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access + RX_FCB_AREA_8316)
718#define RX_BUFF_TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access + RX_BUFF_AREA_8316)
719
720// Offset 0: MSR - Memory Select Register
721//
722#define r587_MSR 0x000 // Register Offset
723//#define MSR_RST 0x080 // LAN Controller Reset
724#define MSR_MENB 0x040 // Shared Memory Enable
725#define MSR_RA18 0x020 // Ram Address bit 18 (583, 584, 587)
726#define MSR_RA17 0x010 // Ram Address bit 17 (583, 584, 585/790)
727#define MSR_RA16 0x008 // Ram Address bit 16 (583, 584, 585/790)
728#define MSR_RA15 0x004 // Ram Address bit 15 (583, 584, 585/790)
729#define MSR_RA14 0x002 // Ram Address bit 14 (583, 584, 585/790)
730#define MSR_RA13 0x001 // Ram Address bit 13 (583, 584, 585/790)
731
732#define MSR_MASK 0x03F // Mask for Address bits RA18-RA13 (583, 584, 587)
733
734#define MSR 0x00
735#define IRR 0x04
736#define HWR 0x04
737#define LAAR 0x05
738#define IMCCR 0x05
739#define LAR0 0x08
740#define BDID 0x0E // Adapter ID byte register offset
741#define CSR 0x10
742#define PR 0x11
743
744#define MSR_RST 0x80
745#define MSR_MEMB 0x40
746#define MSR_0WS 0x20
747
748#define FORCED_16BIT_MODE 0x0002
749
750#define INTERFRAME_SPACING_16 0x0003 /* 6 bytes */
751#define INTERFRAME_SPACING_4 0x0001 /* 2 bytes */
752#define MULTICAST_ADDRESS_BIT 0x0010
753#define NON_SRC_ROUTING_BIT 0x0020
754
755#define LOOPING_MODE_MASK 0x0007
756
757/*
758 * Decode firmware defines.
759 */
760#define SWAP_BYTES(X) ((X & 0xff) << 8) | (X >> 8)
761#define WEIGHT_OFFSET 5
762#define TREE_SIZE_OFFSET 9
763#define TREE_OFFSET 11
764
765/* The Huffman Encoding Tree is constructed of these nodes. */
766typedef struct {
767 __u8 llink; /* Short version of above node. */
768 __u8 tag;
769 __u8 info; /* This node is used on decodes. */
770 __u8 rlink;
771} DECODE_TREE_NODE;
772
773#define ROOT 0 /* Branch value. */
774#define LEAF 0 /* Tag field value. */
775#define BRANCH 1 /* Tag field value. */
776
777/*
778 * Multicast Table Structure
779 */
780typedef struct {
781 __u8 address[6];
782 __u8 instance_count;
783} McTable;
784
785/*
786 * Fragment Descriptor Definition
787 */
788typedef struct {
789 __u8 *fragment_ptr;
790 __u32 fragment_length;
791} FragmentStructure;
792
793/*
794 * Data Buffer Structure Definition
795 */
796typedef struct {
797 __u32 fragment_count;
798 FragmentStructure fragment_list[MAXFRAGMENTS];
799} DataBufferStructure;
800
801#pragma pack(1)
802typedef struct {
803 __u8 IType;
804 __u8 ISubtype;
805} Interrupt_Status_Word;
806
807#pragma pack(1)
808typedef struct BDBlockType {
809 __u16 info; /* 02 */
810 __u32 trc_next_ptr; /* 06 */
811 __u32 trc_data_block_ptr; /* 10 */
812 __u16 buffer_length; /* 12 */
813
814 __u16 *data_block_ptr; /* 16 */
815 struct BDBlockType *next_ptr; /* 20 */
816 struct BDBlockType *back_ptr; /* 24 */
817 __u8 filler[8]; /* 32 */
818} BDBlock;
819
820#pragma pack(1)
821typedef struct FCBlockType {
822 __u16 frame_status; /* 02 */
823 __u16 info; /* 04 */
824 __u32 trc_next_ptr; /* 08 */
825 __u32 trc_bdb_ptr; /* 12 */
826 __u16 frame_length; /* 14 */
827
828 BDBlock *bdb_ptr; /* 18 */
829 struct FCBlockType *next_ptr; /* 22 */
830 struct FCBlockType *back_ptr; /* 26 */
831 __u16 memory_alloc; /* 28 */
832 __u8 filler[4]; /* 32 */
833
834} FCBlock;
835
836#pragma pack(1)
837typedef struct SBlockType{
838 __u8 Internal_Error_Count;
839 __u8 Line_Error_Count;
840 __u8 AC_Error_Count;
841 __u8 Burst_Error_Count;
842 __u8 RESERVED_COUNTER_0;
843 __u8 AD_TRANS_Count;
844 __u8 RCV_Congestion_Count;
845 __u8 Lost_FR_Error_Count;
846 __u8 FREQ_Error_Count;
847 __u8 FR_Copied_Error_Count;
848 __u8 RESERVED_COUNTER_1;
849 __u8 Token_Error_Count;
850
851 __u16 TI_NDIS_Ring_Status;
852 __u16 BCN_Type;
853 __u16 Error_Code;
854 __u16 SA_of_Last_AMP_SMP[3];
855 __u16 UNA[3];
856 __u16 Ucode_Version_Number;
857 __u16 Status_CHG_Indicate;
858 __u16 RESERVED_STATUS_0;
859} SBlock;
860
861#pragma pack(1)
862typedef struct ACBlockType {
863 __u16 cmd_done_status; /* 02 */
864 __u16 cmd_info; /* 04 */
865 __u32 trc_next_ptr; /* 08 */
866 __u16 cmd; /* 10 */
867 __u16 subcmd; /* 12 */
868 __u16 data_offset_lo; /* 14 */
869 __u16 data_offset_hi; /* 16 */
870
871 struct ACBlockType *next_ptr; /* 20 */
872
873 __u8 filler[12]; /* 32 */
874} ACBlock;
875
876#define NUM_OF_INTERRUPTS 0x20
877
878#pragma pack(1)
879typedef struct {
880 Interrupt_Status_Word IStatus[NUM_OF_INTERRUPTS];
881} ISBlock;
882
883#pragma pack(1)
884typedef struct {
885 __u16 valid_command; /* 02 */
886 __u16 iack_code; /* 04 */
887 __u16 resume_control; /* 06 */
888 __u16 int_mask_control; /* 08 */
889 __u16 int_mask_state; /* 10 */
890
891 __u8 filler[6]; /* 16 */
892} SCLBlock;
893
894#pragma pack(1)
895typedef struct
896{
897 __u16 config; /* 02 */
898 __u32 trc_sclb_ptr; /* 06 */
899 __u32 trc_acb_ptr; /* 10 */
900 __u32 trc_isb_ptr; /* 14 */
901 __u16 isbsiz; /* 16 */
902
903 SCLBlock *sclb_ptr; /* 20 */
904 ACBlock *acb_ptr; /* 24 */
905 ISBlock *isb_ptr; /* 28 */
906
907 __u16 Non_Mac_Rx_Bdbs; /* 30 DEBUG */
908 __u8 filler[2]; /* 32 */
909
910} SCGBlock;
911
912#pragma pack(1)
913typedef struct
914{
915 __u32 trc_scgb_ptr;
916 SCGBlock *scgb_ptr;
917} ISCPBlock;
918#pragma pack()
919
920typedef struct net_local {
921 ISCPBlock *iscpb_ptr;
922 SCGBlock *scgb_ptr;
923 SCLBlock *sclb_ptr;
924 ISBlock *isb_ptr;
925
926 ACBlock *acb_head;
927 ACBlock *acb_curr;
928 ACBlock *acb_next;
929
930 __u8 adapter_name[12];
931
932 __u16 num_rx_bdbs [NUM_RX_QS_USED];
933 __u16 num_rx_fcbs [NUM_RX_QS_USED];
934
935 __u16 num_tx_bdbs [NUM_TX_QS_USED];
936 __u16 num_tx_fcbs [NUM_TX_QS_USED];
937
938 __u16 num_of_tx_buffs;
939
940 __u16 tx_buff_size [NUM_TX_QS_USED];
941 __u16 tx_buff_used [NUM_TX_QS_USED];
942 __u16 tx_queue_status [NUM_TX_QS_USED];
943
944 FCBlock *tx_fcb_head[NUM_TX_QS_USED];
945 FCBlock *tx_fcb_curr[NUM_TX_QS_USED];
946 FCBlock *tx_fcb_end[NUM_TX_QS_USED];
947 BDBlock *tx_bdb_head[NUM_TX_QS_USED];
948 __u16 *tx_buff_head[NUM_TX_QS_USED];
949 __u16 *tx_buff_end[NUM_TX_QS_USED];
950 __u16 *tx_buff_curr[NUM_TX_QS_USED];
951 __u16 num_tx_fcbs_used[NUM_TX_QS_USED];
952
953 FCBlock *rx_fcb_head[NUM_RX_QS_USED];
954 FCBlock *rx_fcb_curr[NUM_RX_QS_USED];
955 BDBlock *rx_bdb_head[NUM_RX_QS_USED];
956 BDBlock *rx_bdb_curr[NUM_RX_QS_USED];
957 BDBlock *rx_bdb_end[NUM_RX_QS_USED];
958 __u16 *rx_buff_head[NUM_RX_QS_USED];
959 __u16 *rx_buff_end[NUM_RX_QS_USED];
960
961 __u32 *ptr_local_ring_num;
962
963 __u32 sh_mem_used;
964
965 __u16 page_offset_mask;
966
967 __u16 authorized_function_classes;
968 __u16 authorized_access_priority;
969
970 __u16 num_acbs;
971 __u16 num_acbs_used;
972 __u16 acb_pending;
973
974 __u16 current_isb_index;
975
976 __u8 monitor_state;
977 __u8 monitor_state_ready;
978 __u16 ring_status;
979 __u8 ring_status_flags;
980 __u8 state;
981
982 __u8 join_state;
983
984 __u8 slot_num;
985 __u16 pos_id;
986
987 __u32 *ptr_una;
988 __u32 *ptr_bcn_type;
989 __u32 *ptr_tx_fifo_underruns;
990 __u32 *ptr_rx_fifo_underruns;
991 __u32 *ptr_rx_fifo_overruns;
992 __u32 *ptr_tx_fifo_overruns;
993 __u32 *ptr_tx_fcb_overruns;
994 __u32 *ptr_rx_fcb_overruns;
995 __u32 *ptr_tx_bdb_overruns;
996 __u32 *ptr_rx_bdb_overruns;
997
998 __u16 receive_queue_number;
999
1000 __u8 rx_fifo_overrun_count;
1001 __u8 tx_fifo_overrun_count;
1002
1003 __u16 adapter_flags;
1004 __u16 adapter_flags1;
1005 __u16 *misc_command_data;
1006 __u16 max_packet_size;
1007
1008 __u16 config_word0;
1009 __u16 config_word1;
1010
1011 __u8 trc_mask;
1012
1013 __u16 source_ring_number;
1014 __u16 target_ring_number;
1015
1016 __u16 microcode_version;
1017
1018 __u16 bic_type;
1019 __u16 nic_type;
1020 __u16 board_id;
1021
1022 __u16 rom_size;
1023 __u32 rom_base;
1024 __u16 ram_size;
1025 __u16 ram_usable;
1026 __u32 ram_base;
1027 __u32 ram_access;
1028
1029 __u16 extra_info;
1030 __u16 mode_bits;
1031 __u16 media_menu;
1032 __u16 media_type;
1033 __u16 adapter_bus;
1034
1035 __u16 status;
1036 __u16 receive_mask;
1037
1038 __u16 group_address_0;
1039 __u16 group_address[2];
1040 __u16 functional_address_0;
1041 __u16 functional_address[2];
1042 __u16 bitwise_group_address[2];
1043
1044 __u8 cleanup;
1045
1046 struct sk_buff_head SendSkbQueue;
1047 __u16 QueueSkb;
1048
1049 struct tr_statistics MacStat; /* MAC statistics structure */
1050
1051 spinlock_t lock;
1052} NET_LOCAL;
1053
1054/************************************
1055 * SNMP-ON-BOARD Agent Link Structure
1056 ************************************/
1057
1058typedef struct {
1059 __u8 LnkSigStr[12]; /* signature string "SmcLinkTable" */
1060 __u8 LnkDrvTyp; /* 1=Redbox ODI, 2=ODI DOS, 3=ODI OS/2, 4=NDIS DOS */
1061 __u8 LnkFlg; /* 0 if no agent linked, 1 if agent linked */
1062 void *LnkNfo; /* routine which returns pointer to NIC info */
1063 void *LnkAgtRcv; /* pointer to agent receive trap entry */
1064 void *LnkAgtXmt; /* pointer to agent transmit trap
1065entry */
1066void *LnkGet; /* pointer to NIC receive data
1067copy routine */
1068 void *LnkSnd; /* pointer to NIC send routine
1069*/
1070 void *LnkRst; /* pointer to NIC driver reset
1071routine */
1072 void *LnkMib; /* pointer to MIB data base */
1073 void *LnkMibAct; /* pointer to MIB action routine list */
1074 __u16 LnkCntOffset; /* offset to error counters */
1075 __u16 LnkCntNum; /* number of error counters */
1076 __u16 LnkCntSize; /* size of error counters i.e. 32 = 32 bits */
1077 void *LnkISR; /* pointer to interrupt vector */
1078 __u8 LnkFrmTyp; /* 1=Ethernet, 2=Token Ring */
1079 __u8 LnkDrvVer1 ; /* driver major version */
1080 __u8 LnkDrvVer2 ; /* driver minor version */
1081} AgentLink;
1082
1083/*
1084 * Definitions for pcm_card_flags(bit_mapped)
1085 */
1086#define REG_COMPLETE 0x0001
1087#define INSERTED 0x0002
1088#define PCC_INSERTED 0x0004 /* 1=currently inserted, 0=cur removed */
1089
1090/*
1091 * Adapter RAM test patterns
1092 */
1093#define RAM_PATTERN_1 0x55AA
1094#define RAM_PATTERN_2 0x9249
1095#define RAM_PATTERN_3 0xDB6D
1096
1097/*
1098 * definitions for RAM test
1099 */
1100#define ROM_SIGNATURE 0xAA55
1101#define MIN_ROM_SIZE 0x2000
1102
1103/*
1104 * Return Codes
1105 */
1106#define SUCCESS 0x0000
1107#define ADAPTER_AND_CONFIG 0x0001
1108#define ADAPTER_NO_CONFIG 0x0002
1109#define NOT_MY_INTERRUPT 0x0003
1110#define FRAME_REJECTED 0x0004
1111#define EVENTS_DISABLED 0x0005
1112#define OUT_OF_RESOURCES 0x0006
1113#define INVALID_PARAMETER 0x0007
1114#define INVALID_FUNCTION 0x0008
1115#define INITIALIZE_FAILED 0x0009
1116#define CLOSE_FAILED 0x000A
1117#define MAX_COLLISIONS 0x000B
1118#define NO_SUCH_DESTINATION 0x000C
1119#define BUFFER_TOO_SMALL_ERROR 0x000D
1120#define ADAPTER_CLOSED 0x000E
1121#define UCODE_NOT_PRESENT 0x000F
1122#define FIFO_UNDERRUN 0x0010
1123#define DEST_OUT_OF_RESOURCES 0x0011
1124#define ADAPTER_NOT_INITIALIZED 0x0012
1125#define PENDING 0x0013
1126#define UCODE_PRESENT 0x0014
1127#define NOT_INIT_BY_BRIDGE 0x0015
1128
1129#define OPEN_FAILED 0x0080
1130#define HARDWARE_FAILED 0x0081
1131#define SELF_TEST_FAILED 0x0082
1132#define RAM_TEST_FAILED 0x0083
1133#define RAM_CONFLICT 0x0084
1134#define ROM_CONFLICT 0x0085
1135#define UNKNOWN_ADAPTER 0x0086
1136#define CONFIG_ERROR 0x0087
1137#define CONFIG_WARNING 0x0088
1138#define NO_FIXED_CNFG 0x0089
1139#define EEROM_CKSUM_ERROR 0x008A
1140#define ROM_SIGNATURE_ERROR 0x008B
1141#define ROM_CHECKSUM_ERROR 0x008C
1142#define ROM_SIZE_ERROR 0x008D
1143#define UNSUPPORTED_NIC_CHIP 0x008E
1144#define NIC_REG_ERROR 0x008F
1145#define BIC_REG_ERROR 0x0090
1146#define MICROCODE_TEST_ERROR 0x0091
1147#define LOBE_MEDIA_TEST_FAILED 0x0092
1148
1149#define ADAPTER_FOUND_LAN_CORRUPT 0x009B
1150
1151#define ADAPTER_NOT_FOUND 0xFFFF
1152
1153#define ILLEGAL_FUNCTION INVALID_FUNCTION
1154
1155/* Errors */
1156#define IO_BASE_INVALID 0x0001
1157#define IO_BASE_RANGE 0x0002
1158#define IRQ_INVALID 0x0004
1159#define IRQ_RANGE 0x0008
1160#define RAM_BASE_INVALID 0x0010
1161#define RAM_BASE_RANGE 0x0020
1162#define RAM_SIZE_RANGE 0x0040
1163#define MEDIA_INVALID 0x0800
1164
1165/* Warnings */
1166#define IRQ_MISMATCH 0x0080
1167#define RAM_BASE_MISMATCH 0x0100
1168#define RAM_SIZE_MISMATCH 0x0200
1169#define BUS_MODE_MISMATCH 0x0400
1170
1171#define RX_CRC_ERROR 0x01
1172#define RX_ALIGNMENT_ERROR 0x02
1173#define RX_HW_FAILED 0x80
1174
1175/*
1176 * Definitions for the field RING_STATUS_FLAGS
1177 */
1178#define RING_STATUS_CHANGED 0X01
1179#define MONITOR_STATE_CHANGED 0X02
1180#define JOIN_STATE_CHANGED 0X04
1181
1182/*
1183 * Definitions for the field JOIN_STATE
1184 */
1185#define JS_BYPASS_STATE 0x00
1186#define JS_LOBE_TEST_STATE 0x01
1187#define JS_DETECT_MONITOR_PRESENT_STATE 0x02
1188#define JS_AWAIT_NEW_MONITOR_STATE 0x03
1189#define JS_DUPLICATE_ADDRESS_TEST_STATE 0x04
1190#define JS_NEIGHBOR_NOTIFICATION_STATE 0x05
1191#define JS_REQUEST_INITIALIZATION_STATE 0x06
1192#define JS_JOIN_COMPLETE_STATE 0x07
1193#define JS_BYPASS_WAIT_STATE 0x08
1194
1195/*
1196 * Definitions for the field MONITOR_STATE
1197 */
1198#define MS_MONITOR_FSM_INACTIVE 0x00
1199#define MS_REPEAT_BEACON_STATE 0x01
1200#define MS_REPEAT_CLAIM_TOKEN_STATE 0x02
1201#define MS_TRANSMIT_CLAIM_TOKEN_STATE 0x03
1202#define MS_STANDBY_MONITOR_STATE 0x04
1203#define MS_TRANSMIT_BEACON_STATE 0x05
1204#define MS_ACTIVE_MONITOR_STATE 0x06
1205#define MS_TRANSMIT_RING_PURGE_STATE 0x07
1206#define MS_BEACON_TEST_STATE 0x09
1207
1208/*
1209 * Definitions for the bit-field RING_STATUS
1210 */
1211#define SIGNAL_LOSS 0x8000
1212#define HARD_ERROR 0x4000
1213#define SOFT_ERROR 0x2000
1214#define TRANSMIT_BEACON 0x1000
1215#define LOBE_WIRE_FAULT 0x0800
1216#define AUTO_REMOVAL_ERROR 0x0400
1217#define REMOVE_RECEIVED 0x0100
1218#define COUNTER_OVERFLOW 0x0080
1219#define SINGLE_STATION 0x0040
1220#define RING_RECOVERY 0x0020
1221
1222/*
1223 * Definitions for the field BUS_TYPE
1224 */
1225#define AT_BUS 0x00
1226#define MCA_BUS 0x01
1227#define EISA_BUS 0x02
1228#define PCI_BUS 0x03
1229#define PCMCIA_BUS 0x04
1230
1231/*
1232 * Definitions for adapter_flags
1233 */
1234#define RX_VALID_LOOKAHEAD 0x0001
1235#define FORCED_16BIT_MODE 0x0002
1236#define ADAPTER_DISABLED 0x0004
1237#define TRANSMIT_CHAIN_INT 0x0008
1238#define EARLY_RX_FRAME 0x0010
1239#define EARLY_TX 0x0020
1240#define EARLY_RX_COPY 0x0040
1241#define USES_PHYSICAL_ADDR 0x0080 /* Rsvd for DEC PCI and 9232 */
1242#define NEEDS_PHYSICAL_ADDR 0x0100 /* Reserved*/
1243#define RX_STATUS_PENDING 0x0200
1244#define ERX_DISABLED 0x0400 /* EARLY_RX_ENABLE rcv_mask */
1245#define ENABLE_TX_PENDING 0x0800
1246#define ENABLE_RX_PENDING 0x1000
1247#define PERM_CLOSE 0x2000
1248#define IO_MAPPED 0x4000 /* IOmapped bus interface 795 */
1249#define ETX_DISABLED 0x8000
1250
1251
1252/*
1253 * Definitions for adapter_flags1
1254 */
1255#define TX_PHY_RX_VIRT 0x0001
1256#define NEEDS_HOST_RAM 0x0002
1257#define NEEDS_MEDIA_TYPE 0x0004
1258#define EARLY_RX_DONE 0x0008
1259#define PNP_BOOT_BIT 0x0010 /* activates PnP & config on power-up */
1260 /* clear => regular PnP operation */
1261#define PNP_ENABLE 0x0020 /* regular PnP operation clear => */
1262 /* no PnP, overrides PNP_BOOT_BIT */
1263#define SATURN_ENABLE 0x0040
1264
1265#define ADAPTER_REMOVABLE 0x0080 /* adapter is hot swappable */
1266#define TX_PHY 0x0100 /* Uses physical address for tx bufs */
1267#define RX_PHY 0x0200 /* Uses physical address for rx bufs */
1268#define TX_VIRT 0x0400 /* Uses virtual addr for tx bufs */
1269#define RX_VIRT 0x0800
1270#define NEEDS_SERVICE 0x1000
1271
1272/*
1273 * Adapter Status Codes
1274 */
1275#define OPEN 0x0001
1276#define INITIALIZED 0x0002
1277#define CLOSED 0x0003
1278#define FAILED 0x0005
1279#define NOT_INITIALIZED 0x0006
1280#define IO_CONFLICT 0x0007
1281#define CARD_REMOVED 0x0008
1282#define CARD_INSERTED 0x0009
1283
1284/*
1285 * Mode Bit Definitions
1286 */
1287#define INTERRUPT_STATUS_BIT 0x8000 /* PC Interrupt Line: 0 = Not Enabled */
1288#define BOOT_STATUS_MASK 0x6000 /* Mask to isolate BOOT_STATUS */
1289#define BOOT_INHIBIT 0x0000 /* BOOT_STATUS is 'inhibited' */
1290#define BOOT_TYPE_1 0x2000 /* Unused BOOT_STATUS value */
1291#define BOOT_TYPE_2 0x4000 /* Unused BOOT_STATUS value */
1292#define BOOT_TYPE_3 0x6000 /* Unused BOOT_STATUS value */
1293#define ZERO_WAIT_STATE_MASK 0x1800 /* Mask to isolate Wait State flags */
1294#define ZERO_WAIT_STATE_8_BIT 0x1000 /* 0 = Disabled (Inserts Wait States) */
1295#define ZERO_WAIT_STATE_16_BIT 0x0800 /* 0 = Disabled (Inserts Wait States) */
1296#define LOOPING_MODE_MASK 0x0007
1297#define LOOPBACK_MODE_0 0x0000
1298#define LOOPBACK_MODE_1 0x0001
1299#define LOOPBACK_MODE_2 0x0002
1300#define LOOPBACK_MODE_3 0x0003
1301#define LOOPBACK_MODE_4 0x0004
1302#define LOOPBACK_MODE_5 0x0005
1303#define LOOPBACK_MODE_6 0x0006
1304#define LOOPBACK_MODE_7 0x0007
1305#define AUTO_MEDIA_DETECT 0x0008
1306#define MANUAL_CRC 0x0010
1307#define EARLY_TOKEN_REL 0x0020 /* Early Token Release for Token Ring */
1308#define UMAC 0x0040
1309#define UTP2_PORT 0x0080 /* For 8216T2, 0=port A, 1=Port B. */
1310#define BNC_10BT_INTERFACE 0x0600 /* BNC and UTP current media set */
1311#define UTP_INTERFACE 0x0500 /* Ethernet UTP Only. */
1312#define BNC_INTERFACE 0x0400
1313#define AUI_INTERFACE 0x0300
1314#define AUI_10BT_INTERFACE 0x0200
1315#define STARLAN_10_INTERFACE 0x0100
1316#define INTERFACE_TYPE_MASK 0x0700
1317
1318/*
1319 * Media Type Bit Definitions
1320 *
1321 * legend: TP = Twisted Pair
1322 * STP = Shielded twisted pair
1323 * UTP = Unshielded twisted pair
1324 */
1325
1326#define CNFG_MEDIA_TYPE_MASK 0x001e /* POS Register 3 Mask */
1327
1328#define MEDIA_S10 0x0000 /* Ethernet adapter, TP. */
1329#define MEDIA_AUI_UTP 0x0001 /* Ethernet adapter, AUI/UTP media */
1330#define MEDIA_BNC 0x0002 /* Ethernet adapter, BNC media. */
1331#define MEDIA_AUI 0x0003 /* Ethernet Adapter, AUI media. */
1332#define MEDIA_STP_16 0x0004 /* TokenRing adap, 16Mbit STP. */
1333#define MEDIA_STP_4 0x0005 /* TokenRing adap, 4Mbit STP. */
1334#define MEDIA_UTP_16 0x0006 /* TokenRing adap, 16Mbit UTP. */
1335#define MEDIA_UTP_4 0x0007 /* TokenRing adap, 4Mbit UTP. */
1336#define MEDIA_UTP 0x0008 /* Ethernet adapter, UTP media (no AUI)
1337*/
1338#define MEDIA_BNC_UTP 0x0010 /* Ethernet adapter, BNC/UTP media */
1339#define MEDIA_UTPFD 0x0011 /* Ethernet adapter, TP full duplex */
1340#define MEDIA_UTPNL 0x0012 /* Ethernet adapter, TP with link integrity test disabled */
1341#define MEDIA_AUI_BNC 0x0013 /* Ethernet adapter, AUI/BNC media */
1342#define MEDIA_AUI_BNC_UTP 0x0014 /* Ethernet adapter, AUI_BNC/UTP */
1343#define MEDIA_UTPA 0x0015 /* Ethernet UTP-10Mbps Ports A */
1344#define MEDIA_UTPB 0x0016 /* Ethernet UTP-10Mbps Ports B */
1345#define MEDIA_STP_16_UTP_16 0x0017 /* Token Ring STP-16Mbps/UTP-16Mbps */
1346#define MEDIA_STP_4_UTP_4 0x0018 /* Token Ring STP-4Mbps/UTP-4Mbps */
1347
1348#define MEDIA_STP100_UTP100 0x0020 /* Ethernet STP-100Mbps/UTP-100Mbps */
1349#define MEDIA_UTP100FD 0x0021 /* Ethernet UTP-100Mbps, full duplex */
1350#define MEDIA_UTP100 0x0022 /* Ethernet UTP-100Mbps */
1351
1352
1353#define MEDIA_UNKNOWN 0xFFFF /* Unknown adapter/media type */
1354
1355/*
1356 * Definitions for the field:
1357 * media_type2
1358 */
1359#define MEDIA_TYPE_MII 0x0001
1360#define MEDIA_TYPE_UTP 0x0002
1361#define MEDIA_TYPE_BNC 0x0004
1362#define MEDIA_TYPE_AUI 0x0008
1363#define MEDIA_TYPE_S10 0x0010
1364#define MEDIA_TYPE_AUTO_SENSE 0x1000
1365#define MEDIA_TYPE_AUTO_DETECT 0x4000
1366#define MEDIA_TYPE_AUTO_NEGOTIATE 0x8000
1367
1368/*
1369 * Definitions for the field:
1370 * line_speed
1371 */
1372#define LINE_SPEED_UNKNOWN 0x0000
1373#define LINE_SPEED_4 0x0001
1374#define LINE_SPEED_10 0x0002
1375#define LINE_SPEED_16 0x0004
1376#define LINE_SPEED_100 0x0008
1377#define LINE_SPEED_T4 0x0008 /* 100BaseT4 aliased for 9332BVT */
1378#define LINE_SPEED_FULL_DUPLEX 0x8000
1379
1380/*
1381 * Definitions for the field:
1382 * bic_type (Bus interface chip type)
1383 */
1384#define BIC_NO_CHIP 0x0000 /* Bus interface chip not implemented */
1385#define BIC_583_CHIP 0x0001 /* 83C583 bus interface chip */
1386#define BIC_584_CHIP 0x0002 /* 83C584 bus interface chip */
1387#define BIC_585_CHIP 0x0003 /* 83C585 bus interface chip */
1388#define BIC_593_CHIP 0x0004 /* 83C593 bus interface chip */
1389#define BIC_594_CHIP 0x0005 /* 83C594 bus interface chip */
1390#define BIC_564_CHIP 0x0006 /* PCMCIA Bus interface chip */
1391#define BIC_790_CHIP 0x0007 /* 83C790 bus i-face/Ethernet NIC chip */
1392#define BIC_571_CHIP 0x0008 /* 83C571 EISA bus master i-face */
1393#define BIC_587_CHIP 0x0009 /* Token Ring AT bus master i-face */
1394#define BIC_574_CHIP 0x0010 /* FEAST bus interface chip */
1395#define BIC_8432_CHIP 0x0011 /* 8432 bus i-face/Ethernet NIC(DEC PCI) */
1396#define BIC_9332_CHIP 0x0012 /* 9332 bus i-face/100Mbps Ether NIC(DEC PCI) */
1397#define BIC_8432E_CHIP 0x0013 /* 8432 Enhanced bus iface/Ethernet NIC(DEC) */
1398#define BIC_EPIC100_CHIP 0x0014 /* EPIC/100 10/100 Mbps Ethernet BIC/NIC */
1399#define BIC_C94_CHIP 0x0015 /* 91C94 bus i-face in PCMCIA mode */
1400#define BIC_X8020_CHIP 0x0016 /* Xilinx PCMCIA multi-func i-face */
1401
1402/*
1403 * Definitions for the field:
1404 * nic_type (Bus interface chip type)
1405 */
1406#define NIC_UNK_CHIP 0x0000 /* Unknown NIC chip */
1407#define NIC_8390_CHIP 0x0001 /* DP8390 Ethernet NIC */
1408#define NIC_690_CHIP 0x0002 /* 83C690 Ethernet NIC */
1409#define NIC_825_CHIP 0x0003 /* 83C825 Token Ring NIC */
1410/* #define NIC_???_CHIP 0x0004 */ /* Not used */
1411/* #define NIC_???_CHIP 0x0005 */ /* Not used */
1412/* #define NIC_???_CHIP 0x0006 */ /* Not used */
1413#define NIC_790_CHIP 0x0007 /* 83C790 bus i-face/Ethernet NIC chip */
1414#define NIC_C100_CHIP 0x0010 /* FEAST 100Mbps Ethernet NIC */
1415#define NIC_8432_CHIP 0x0011 /* 8432 bus i-face/Ethernet NIC(DEC PCI) */
1416#define NIC_9332_CHIP 0x0012 /* 9332 bus i-face/100Mbps Ether NIC(DEC PCI) */
1417#define NIC_8432E_CHIP 0x0013 /* 8432 enhanced bus iface/Ethernet NIC(DEC) */
1418#define NIC_EPIC100_CHIP 0x0014 /* EPIC/100 10/100 Mbps Ethernet BIC/NIC */
1419#define NIC_C94_CHIP 0x0015 /* 91C94 PC Card with multi func */
1420
1421/*
1422 * Definitions for the field:
1423 * adapter_type The adapter_type field describes the adapter/bus
1424 * configuration.
1425 */
1426#define BUS_ISA16_TYPE 0x0001 /* 16 bit adap in 16 bit (E)ISA slot */
1427#define BUS_ISA8_TYPE 0x0002 /* 8/16b adap in 8 bit XT/(E)ISA slot */
1428#define BUS_MCA_TYPE 0x0003 /* Micro Channel adapter */
1429
1430/*
1431 * Receive Mask definitions
1432 */
1433#define ACCEPT_MULTICAST 0x0001
1434#define ACCEPT_BROADCAST 0x0002
1435#define PROMISCUOUS_MODE 0x0004
1436#define ACCEPT_SOURCE_ROUTING 0x0008
1437#define ACCEPT_ERR_PACKETS 0x0010
1438#define ACCEPT_ATT_MAC_FRAMES 0x0020
1439#define ACCEPT_MULTI_PROM 0x0040
1440#define TRANSMIT_ONLY 0x0080
1441#define ACCEPT_EXT_MAC_FRAMES 0x0100
1442#define EARLY_RX_ENABLE 0x0200
1443#define PKT_SIZE_NOT_NEEDED 0x0400
1444#define ACCEPT_SOURCE_ROUTING_SPANNING 0x0808
1445
1446#define ACCEPT_ALL_MAC_FRAMES 0x0120
1447
1448/*
1449 * config_mode defs
1450 */
1451#define STORE_EEROM 0x0001 /* Store config in EEROM. */
1452#define STORE_REGS 0x0002 /* Store config in register set. */
1453
1454/*
1455 * equates for lmac_flags in adapter structure (Ethernet)
1456 */
1457#define MEM_DISABLE 0x0001
1458#define RX_STATUS_POLL 0x0002
1459#define USE_RE_BIT 0x0004
1460/*#define RESERVED 0x0008 */
1461/*#define RESERVED 0x0010 */
1462/*#define RESERVED 0x0020 */
1463/*#define RESERVED 0x0040 */
1464/*#define RESERVED 0x0080 */
1465/*#define RESERVED 0x0100 */
1466/*#define RESERVED 0x0200 */
1467/*#define RESERVED 0x0400 */
1468/*#define RESERVED 0x0800 */
1469/*#define RESERVED 0x1000 */
1470/*#define RESERVED 0x2000 */
1471/*#define RESERVED 0x4000 */
1472/*#define RESERVED 0x8000 */
1473
1474/* media_opts & media_set Fields bit defs for Ethernet ... */
1475#define MED_OPT_BNC 0x01
1476#define MED_OPT_UTP 0x02
1477#define MED_OPT_AUI 0x04
1478#define MED_OPT_10MB 0x08
1479#define MED_OPT_100MB 0x10
1480#define MED_OPT_S10 0x20
1481
1482/* media_opts & media_set Fields bit defs for Token Ring ... */
1483#define MED_OPT_4MB 0x08
1484#define MED_OPT_16MB 0x10
1485#define MED_OPT_STP 0x40
1486
1487#define MAX_8023_SIZE 1500 /* Max 802.3 size of frame. */
1488#define DEFAULT_ERX_VALUE 4 /* Number of 16-byte blocks for 790B early Rx. */
1489#define DEFAULT_ETX_VALUE 32 /* Number of bytes for 790B early Tx. */
1490#define DEFAULT_TX_RETRIES 3 /* Number of transmit retries */
1491#define LPBK_FRAME_SIZE 1024 /* Default loopback frame for Rx calibration test. */
1492#define MAX_LOOKAHEAD_SIZE 252 /* Max lookahead size for ethernet. */
1493
1494#define RW_MAC_STATE 0x1101
1495#define RW_SA_OF_LAST_AMP_OR_SMP 0x2803
1496#define RW_PHYSICAL_DROP_NUMBER 0x3B02
1497#define RW_UPSTREAM_NEIGHBOR_ADDRESS 0x3E03
1498#define RW_PRODUCT_INSTANCE_ID 0x4B09
1499
1500#define RW_TRC_STATUS_BLOCK 0x5412
1501
1502#define RW_MAC_ERROR_COUNTERS_NO_CLEAR 0x8006
1503#define RW_MAC_ERROR_COUNTER_CLEAR 0x7A06
1504#define RW_CONFIG_REGISTER_0 0xA001
1505#define RW_CONFIG_REGISTER_1 0xA101
1506#define RW_PRESCALE_TIMER_THRESHOLD 0xA201
1507#define RW_TPT_THRESHOLD 0xA301
1508#define RW_TQP_THRESHOLD 0xA401
1509#define RW_TNT_THRESHOLD 0xA501
1510#define RW_TBT_THRESHOLD 0xA601
1511#define RW_TSM_THRESHOLD 0xA701
1512#define RW_TAM_THRESHOLD 0xA801
1513#define RW_TBR_THRESHOLD 0xA901
1514#define RW_TER_THRESHOLD 0xAA01
1515#define RW_TGT_THRESHOLD 0xAB01
1516#define RW_THT_THRESHOLD 0xAC01
1517#define RW_TRR_THRESHOLD 0xAD01
1518#define RW_TVX_THRESHOLD 0xAE01
1519#define RW_INDIVIDUAL_MAC_ADDRESS 0xB003
1520
1521#define RW_INDIVIDUAL_GROUP_ADDRESS 0xB303 /* all of group addr */
1522#define RW_INDIVIDUAL_GROUP_ADDR_WORD_0 0xB301 /* 1st word of group addr */
1523#define RW_INDIVIDUAL_GROUP_ADDR 0xB402 /* 2nd-3rd word of group addr */
1524#define RW_FUNCTIONAL_ADDRESS 0xB603 /* all of functional addr */
1525#define RW_FUNCTIONAL_ADDR_WORD_0 0xB601 /* 1st word of func addr */
1526#define RW_FUNCTIONAL_ADDR 0xB702 /* 2nd-3rd word func addr */
1527
1528#define RW_BIT_SIGNIFICANT_GROUP_ADDR 0xB902
1529#define RW_SOURCE_RING_BRIDGE_NUMBER 0xBB01
1530#define RW_TARGET_RING_NUMBER 0xBC01
1531
1532#define RW_HIC_INTERRUPT_MASK 0xC601
1533
1534#define SOURCE_ROUTING_SPANNING_BITS 0x00C0 /* Spanning Tree Frames */
1535#define SOURCE_ROUTING_EXPLORER_BIT 0x0040 /* Explorer and Single Route */
1536
1537 /* write */
1538
1539#define CSR_MSK_ALL 0x80 // Bic 587 Only
1540#define CSR_MSKTINT 0x20
1541#define CSR_MSKCBUSY 0x10
1542#define CSR_CLRTINT 0x08
1543#define CSR_CLRCBUSY 0x04
1544#define CSR_WCSS 0x02
1545#define CSR_CA 0x01
1546
1547 /* read */
1548
1549#define CSR_TINT 0x20
1550#define CSR_CINT 0x10
1551#define CSR_TSTAT 0x08
1552#define CSR_CSTAT 0x04
1553#define CSR_FAULT 0x02
1554#define CSR_CBUSY 0x01
1555
1556#define LAAR_MEM16ENB 0x80
1557#define Zws16 0x20
1558
1559#define IRR_IEN 0x80
1560#define Zws8 0x01
1561
1562#define IMCCR_EIL 0x04
1563
1564typedef struct {
1565 __u8 ac; /* Access Control */
1566 __u8 fc; /* Frame Control */
1567 __u8 da[6]; /* Dest Addr */
1568 __u8 sa[6]; /* Source Addr */
1569
1570 __u16 vl; /* Vector Length */
1571 __u8 dc_sc; /* Dest/Source Class */
1572 __u8 vc; /* Vector Code */
1573 } MAC_HEADER;
1574
1575#define MAX_SUB_VECTOR_INFO (RX_DATA_BUFFER_SIZE - sizeof(MAC_HEADER) - 2)
1576
1577typedef struct
1578 {
1579 __u8 svl; /* Sub-vector Length */
1580 __u8 svi; /* Sub-vector Code */
1581 __u8 svv[MAX_SUB_VECTOR_INFO]; /* Sub-vector Info */
1582 } MAC_SUB_VECTOR;
1583
1584#endif /* __KERNEL__ */
1585#endif /* __LINUX_SMCTR_H */
diff --git a/drivers/net/tokenring/tms380tr.c b/drivers/net/tokenring/tms380tr.c
deleted file mode 100644
index b5e0855e4b39..000000000000
--- a/drivers/net/tokenring/tms380tr.c
+++ /dev/null
@@ -1,2306 +0,0 @@
1/*
2 * tms380tr.c: A network driver library for Texas Instruments TMS380-based
3 * Token Ring Adapters.
4 *
5 * Originally sktr.c: Written 1997 by Christoph Goos
6 *
7 * A fine result of the Linux Systems Network Architecture Project.
8 * http://www.vanheusden.com/sna/
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * The following modules are currently available for card support:
14 * - tmspci (Generic PCI card support)
15 * - abyss (Madge PCI support)
16 * - tmsisa (SysKonnect TR4/16 ISA)
17 *
18 * Sources:
19 * - The hardware related parts of this driver are take from
20 * the SysKonnect Token Ring driver for Windows NT.
21 * - I used the IBM Token Ring driver 'ibmtr.c' as a base for this
22 * driver, as well as the 'skeleton.c' driver by Donald Becker.
23 * - Also various other drivers in the linux source tree were taken
24 * as samples for some tasks.
25 * - TI TMS380 Second-Generation Token Ring User's Guide
26 * - TI datasheets for respective chips
27 * - David Hein at Texas Instruments
28 * - Various Madge employees
29 *
30 * Maintainer(s):
31 * JS Jay Schulist jschlst@samba.org
32 * CG Christoph Goos cgoos@syskonnect.de
33 * AF Adam Fritzler
34 * MLP Mike Phillips phillim@amtrak.com
35 * JF Jochen Friedrich jochen@scram.de
36 *
37 * Modification History:
38 * 29-Aug-97 CG Created
39 * 04-Apr-98 CG Fixed problems caused by tok_timer_check
40 * 10-Apr-98 CG Fixed lockups at cable disconnection
41 * 27-May-98 JS Formated to Linux Kernel Format
42 * 31-May-98 JS Hacked in PCI support
43 * 16-Jun-98 JS Modulized for multiple cards with one driver
44 * Sep-99 AF Renamed to tms380tr (supports more than SK's)
45 * 23-Sep-99 AF Added Compaq and Thomas-Conrad PCI support
46 * Fixed a bug causing double copies on PCI
47 * Fixed for new multicast stuff (2.2/2.3)
48 * 25-Sep-99 AF Uped TPL_NUM from 3 to 9
49 * Removed extraneous 'No free TPL'
50 * 22-Dec-99 AF Added Madge PCI Mk2 support and generalized
51 * parts of the initilization procedure.
52 * 30-Dec-99 AF Turned tms380tr into a library ala 8390.
53 * Madge support is provided in the abyss module
54 * Generic PCI support is in the tmspci module.
55 * 30-Nov-00 JF Updated PCI code to support IO MMU via
56 * pci_map_static(). Alpha uses this MMU for ISA
57 * as well.
58 * 14-Jan-01 JF Fix DMA on ifdown/ifup sequences. Some
59 * cleanup.
60 * 13-Jan-02 JF Add spinlock to fix race condition.
61 * 09-Nov-02 JF Fixed printks to not SPAM the console during
62 * normal operation.
63 * 30-Dec-02 JF Removed incorrect __init from
64 * tms380tr_init_card.
65 * 22-Jul-05 JF Converted to dma-mapping.
66 *
67 * To do:
68 * 1. Multi/Broadcast packet handling (this may have fixed itself)
69 * 2. Write a sktrisa module that includes the old ISA support (done)
70 * 3. Allow modules to load their own microcode
71 * 4. Speed up the BUD process -- freezing the kernel for 3+sec is
72 * quite unacceptable.
73 * 5. Still a few remaining stalls when the cable is unplugged.
74 */
75
76#ifdef MODULE
77static const char version[] = "tms380tr.c: v1.10 30/12/2002 by Christoph Goos, Adam Fritzler\n";
78#endif
79
80#include <linux/module.h>
81#include <linux/kernel.h>
82#include <linux/types.h>
83#include <linux/fcntl.h>
84#include <linux/interrupt.h>
85#include <linux/ptrace.h>
86#include <linux/ioport.h>
87#include <linux/in.h>
88#include <linux/string.h>
89#include <linux/time.h>
90#include <linux/errno.h>
91#include <linux/init.h>
92#include <linux/dma-mapping.h>
93#include <linux/delay.h>
94#include <linux/netdevice.h>
95#include <linux/etherdevice.h>
96#include <linux/skbuff.h>
97#include <linux/trdevice.h>
98#include <linux/firmware.h>
99#include <linux/bitops.h>
100
101#include <asm/io.h>
102#include <asm/dma.h>
103#include <asm/irq.h>
104#include <asm/uaccess.h>
105
106#include "tms380tr.h" /* Our Stuff */
107
108/* Use 0 for production, 1 for verification, 2 for debug, and
109 * 3 for very verbose debug.
110 */
111#ifndef TMS380TR_DEBUG
112#define TMS380TR_DEBUG 0
113#endif
114static unsigned int tms380tr_debug = TMS380TR_DEBUG;
115
116/* Index to functions, as function prototypes.
117 * Alphabetical by function name.
118 */
119
120/* "A" */
121/* "B" */
122static int tms380tr_bringup_diags(struct net_device *dev);
123/* "C" */
124static void tms380tr_cancel_tx_queue(struct net_local* tp);
125static int tms380tr_chipset_init(struct net_device *dev);
126static void tms380tr_chk_irq(struct net_device *dev);
127static void tms380tr_chk_outstanding_cmds(struct net_device *dev);
128static void tms380tr_chk_src_addr(unsigned char *frame, unsigned char *hw_addr);
129static unsigned char tms380tr_chk_ssb(struct net_local *tp, unsigned short IrqType);
130int tms380tr_close(struct net_device *dev);
131static void tms380tr_cmd_status_irq(struct net_device *dev);
132/* "D" */
133static void tms380tr_disable_interrupts(struct net_device *dev);
134#if TMS380TR_DEBUG > 0
135static void tms380tr_dump(unsigned char *Data, int length);
136#endif
137/* "E" */
138static void tms380tr_enable_interrupts(struct net_device *dev);
139static void tms380tr_exec_cmd(struct net_device *dev, unsigned short Command);
140static void tms380tr_exec_sifcmd(struct net_device *dev, unsigned int WriteValue);
141/* "F" */
142/* "G" */
143static struct net_device_stats *tms380tr_get_stats(struct net_device *dev);
144/* "H" */
145static netdev_tx_t tms380tr_hardware_send_packet(struct sk_buff *skb,
146 struct net_device *dev);
147/* "I" */
148static int tms380tr_init_adapter(struct net_device *dev);
149static void tms380tr_init_ipb(struct net_local *tp);
150static void tms380tr_init_net_local(struct net_device *dev);
151static void tms380tr_init_opb(struct net_device *dev);
152/* "M" */
153/* "O" */
154int tms380tr_open(struct net_device *dev);
155static void tms380tr_open_adapter(struct net_device *dev);
156/* "P" */
157/* "R" */
158static void tms380tr_rcv_status_irq(struct net_device *dev);
159static int tms380tr_read_ptr(struct net_device *dev);
160static void tms380tr_read_ram(struct net_device *dev, unsigned char *Data,
161 unsigned short Address, int Length);
162static int tms380tr_reset_adapter(struct net_device *dev);
163static void tms380tr_reset_interrupt(struct net_device *dev);
164static void tms380tr_ring_status_irq(struct net_device *dev);
165/* "S" */
166static netdev_tx_t tms380tr_send_packet(struct sk_buff *skb,
167 struct net_device *dev);
168static void tms380tr_set_multicast_list(struct net_device *dev);
169static int tms380tr_set_mac_address(struct net_device *dev, void *addr);
170/* "T" */
171static void tms380tr_timer_chk(unsigned long data);
172static void tms380tr_timer_end_wait(unsigned long data);
173static void tms380tr_tx_status_irq(struct net_device *dev);
174/* "U" */
175static void tms380tr_update_rcv_stats(struct net_local *tp,
176 unsigned char DataPtr[], unsigned int Length);
177/* "W" */
178void tms380tr_wait(unsigned long time);
179static void tms380tr_write_rpl_status(RPL *rpl, unsigned int Status);
180static void tms380tr_write_tpl_status(TPL *tpl, unsigned int Status);
181
182#define SIFREADB(reg) \
183 (((struct net_local *)netdev_priv(dev))->sifreadb(dev, reg))
184#define SIFWRITEB(val, reg) \
185 (((struct net_local *)netdev_priv(dev))->sifwriteb(dev, val, reg))
186#define SIFREADW(reg) \
187 (((struct net_local *)netdev_priv(dev))->sifreadw(dev, reg))
188#define SIFWRITEW(val, reg) \
189 (((struct net_local *)netdev_priv(dev))->sifwritew(dev, val, reg))
190
191
192
193#if 0 /* TMS380TR_DEBUG > 0 */
194static int madgemc_sifprobe(struct net_device *dev)
195{
196 unsigned char old, chk1, chk2;
197
198 old = SIFREADB(SIFADR); /* Get the old SIFADR value */
199
200 chk1 = 0; /* Begin with check value 0 */
201 do {
202 madgemc_setregpage(dev, 0);
203 /* Write new SIFADR value */
204 SIFWRITEB(chk1, SIFADR);
205 chk2 = SIFREADB(SIFADR);
206 if (chk2 != chk1)
207 return -1;
208
209 madgemc_setregpage(dev, 1);
210 /* Read, invert and write */
211 chk2 = SIFREADB(SIFADD);
212 if (chk2 != chk1)
213 return -1;
214
215 madgemc_setregpage(dev, 0);
216 chk2 ^= 0x0FE;
217 SIFWRITEB(chk2, SIFADR);
218
219 /* Read, invert and compare */
220 madgemc_setregpage(dev, 1);
221 chk2 = SIFREADB(SIFADD);
222 madgemc_setregpage(dev, 0);
223 chk2 ^= 0x0FE;
224
225 if(chk1 != chk2)
226 return -1; /* No adapter */
227 chk1 -= 2;
228 } while(chk1 != 0); /* Repeat 128 times (all byte values) */
229
230 madgemc_setregpage(dev, 0); /* sanity */
231 /* Restore the SIFADR value */
232 SIFWRITEB(old, SIFADR);
233
234 return 0;
235}
236#endif
237
238/*
239 * Open/initialize the board. This is called sometime after
240 * booting when the 'ifconfig' program is run.
241 *
242 * This routine should set everything up anew at each open, even
243 * registers that "should" only need to be set once at boot, so that
244 * there is non-reboot way to recover if something goes wrong.
245 */
246int tms380tr_open(struct net_device *dev)
247{
248 struct net_local *tp = netdev_priv(dev);
249 int err;
250
251 /* init the spinlock */
252 spin_lock_init(&tp->lock);
253 init_timer(&tp->timer);
254
255 /* Reset the hardware here. Don't forget to set the station address. */
256
257#if defined(CONFIG_ISA) && defined(CONFIG_ISA_DMA_API)
258 if(dev->dma > 0)
259 {
260 unsigned long flags=claim_dma_lock();
261 disable_dma(dev->dma);
262 set_dma_mode(dev->dma, DMA_MODE_CASCADE);
263 enable_dma(dev->dma);
264 release_dma_lock(flags);
265 }
266#endif
267
268 err = tms380tr_chipset_init(dev);
269 if(err)
270 {
271 printk(KERN_INFO "%s: Chipset initialization error\n",
272 dev->name);
273 return -1;
274 }
275
276 tp->timer.expires = jiffies + 30*HZ;
277 tp->timer.function = tms380tr_timer_end_wait;
278 tp->timer.data = (unsigned long)dev;
279 add_timer(&tp->timer);
280
281 printk(KERN_DEBUG "%s: Adapter RAM size: %dK\n",
282 dev->name, tms380tr_read_ptr(dev));
283
284 tms380tr_enable_interrupts(dev);
285 tms380tr_open_adapter(dev);
286
287 netif_start_queue(dev);
288
289 /* Wait for interrupt from hardware. If interrupt does not come,
290 * there will be a timeout from the timer.
291 */
292 tp->Sleeping = 1;
293 interruptible_sleep_on(&tp->wait_for_tok_int);
294 del_timer(&tp->timer);
295
296 /* If AdapterVirtOpenFlag is 1, the adapter is now open for use */
297 if(tp->AdapterVirtOpenFlag == 0)
298 {
299 tms380tr_disable_interrupts(dev);
300 return -1;
301 }
302
303 tp->StartTime = jiffies;
304
305 /* Start function control timer */
306 tp->timer.expires = jiffies + 2*HZ;
307 tp->timer.function = tms380tr_timer_chk;
308 tp->timer.data = (unsigned long)dev;
309 add_timer(&tp->timer);
310
311 return 0;
312}
313
314/*
315 * Timeout function while waiting for event
316 */
317static void tms380tr_timer_end_wait(unsigned long data)
318{
319 struct net_device *dev = (struct net_device*)data;
320 struct net_local *tp = netdev_priv(dev);
321
322 if(tp->Sleeping)
323 {
324 tp->Sleeping = 0;
325 wake_up_interruptible(&tp->wait_for_tok_int);
326 }
327}
328
329/*
330 * Initialize the chipset
331 */
332static int tms380tr_chipset_init(struct net_device *dev)
333{
334 struct net_local *tp = netdev_priv(dev);
335 int err;
336
337 tms380tr_init_ipb(tp);
338 tms380tr_init_opb(dev);
339 tms380tr_init_net_local(dev);
340
341 if(tms380tr_debug > 3)
342 printk(KERN_DEBUG "%s: Resetting adapter...\n", dev->name);
343 err = tms380tr_reset_adapter(dev);
344 if(err < 0)
345 return -1;
346
347 if(tms380tr_debug > 3)
348 printk(KERN_DEBUG "%s: Bringup diags...\n", dev->name);
349 err = tms380tr_bringup_diags(dev);
350 if(err < 0)
351 return -1;
352
353 if(tms380tr_debug > 3)
354 printk(KERN_DEBUG "%s: Init adapter...\n", dev->name);
355 err = tms380tr_init_adapter(dev);
356 if(err < 0)
357 return -1;
358
359 if(tms380tr_debug > 3)
360 printk(KERN_DEBUG "%s: Done!\n", dev->name);
361 return 0;
362}
363
364/*
365 * Initializes the net_local structure.
366 */
367static void tms380tr_init_net_local(struct net_device *dev)
368{
369 struct net_local *tp = netdev_priv(dev);
370 int i;
371 dma_addr_t dmabuf;
372
373 tp->scb.CMD = 0;
374 tp->scb.Parm[0] = 0;
375 tp->scb.Parm[1] = 0;
376
377 tp->ssb.STS = 0;
378 tp->ssb.Parm[0] = 0;
379 tp->ssb.Parm[1] = 0;
380 tp->ssb.Parm[2] = 0;
381
382 tp->CMDqueue = 0;
383
384 tp->AdapterOpenFlag = 0;
385 tp->AdapterVirtOpenFlag = 0;
386 tp->ScbInUse = 0;
387 tp->OpenCommandIssued = 0;
388 tp->ReOpenInProgress = 0;
389 tp->HaltInProgress = 0;
390 tp->TransmitHaltScheduled = 0;
391 tp->LobeWireFaultLogged = 0;
392 tp->LastOpenStatus = 0;
393 tp->MaxPacketSize = DEFAULT_PACKET_SIZE;
394
395 /* Create circular chain of transmit lists */
396 for (i = 0; i < TPL_NUM; i++)
397 {
398 tp->Tpl[i].NextTPLAddr = htonl(((char *)(&tp->Tpl[(i+1) % TPL_NUM]) - (char *)tp) + tp->dmabuffer); /* DMA buffer may be MMU driven */
399 tp->Tpl[i].Status = 0;
400 tp->Tpl[i].FrameSize = 0;
401 tp->Tpl[i].FragList[0].DataCount = 0;
402 tp->Tpl[i].FragList[0].DataAddr = 0;
403 tp->Tpl[i].NextTPLPtr = &tp->Tpl[(i+1) % TPL_NUM];
404 tp->Tpl[i].MData = NULL;
405 tp->Tpl[i].TPLIndex = i;
406 tp->Tpl[i].DMABuff = 0;
407 tp->Tpl[i].BusyFlag = 0;
408 }
409
410 tp->TplFree = tp->TplBusy = &tp->Tpl[0];
411
412 /* Create circular chain of receive lists */
413 for (i = 0; i < RPL_NUM; i++)
414 {
415 tp->Rpl[i].NextRPLAddr = htonl(((char *)(&tp->Rpl[(i+1) % RPL_NUM]) - (char *)tp) + tp->dmabuffer); /* DMA buffer may be MMU driven */
416 tp->Rpl[i].Status = (RX_VALID | RX_START_FRAME | RX_END_FRAME | RX_FRAME_IRQ);
417 tp->Rpl[i].FrameSize = 0;
418 tp->Rpl[i].FragList[0].DataCount = cpu_to_be16((unsigned short)tp->MaxPacketSize);
419
420 /* Alloc skb and point adapter to data area */
421 tp->Rpl[i].Skb = dev_alloc_skb(tp->MaxPacketSize);
422 tp->Rpl[i].DMABuff = 0;
423
424 /* skb == NULL ? then use local buffer */
425 if(tp->Rpl[i].Skb == NULL)
426 {
427 tp->Rpl[i].SkbStat = SKB_UNAVAILABLE;
428 tp->Rpl[i].FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[i] - (char *)tp) + tp->dmabuffer);
429 tp->Rpl[i].MData = tp->LocalRxBuffers[i];
430 }
431 else /* SKB != NULL */
432 {
433 tp->Rpl[i].Skb->dev = dev;
434 skb_put(tp->Rpl[i].Skb, tp->MaxPacketSize);
435
436 /* data unreachable for DMA ? then use local buffer */
437 dmabuf = dma_map_single(tp->pdev, tp->Rpl[i].Skb->data, tp->MaxPacketSize, DMA_FROM_DEVICE);
438 if(tp->dmalimit && (dmabuf + tp->MaxPacketSize > tp->dmalimit))
439 {
440 tp->Rpl[i].SkbStat = SKB_DATA_COPY;
441 tp->Rpl[i].FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[i] - (char *)tp) + tp->dmabuffer);
442 tp->Rpl[i].MData = tp->LocalRxBuffers[i];
443 }
444 else /* DMA directly in skb->data */
445 {
446 tp->Rpl[i].SkbStat = SKB_DMA_DIRECT;
447 tp->Rpl[i].FragList[0].DataAddr = htonl(dmabuf);
448 tp->Rpl[i].MData = tp->Rpl[i].Skb->data;
449 tp->Rpl[i].DMABuff = dmabuf;
450 }
451 }
452
453 tp->Rpl[i].NextRPLPtr = &tp->Rpl[(i+1) % RPL_NUM];
454 tp->Rpl[i].RPLIndex = i;
455 }
456
457 tp->RplHead = &tp->Rpl[0];
458 tp->RplTail = &tp->Rpl[RPL_NUM-1];
459 tp->RplTail->Status = (RX_START_FRAME | RX_END_FRAME | RX_FRAME_IRQ);
460}
461
462/*
463 * Initializes the initialisation parameter block.
464 */
465static void tms380tr_init_ipb(struct net_local *tp)
466{
467 tp->ipb.Init_Options = BURST_MODE;
468 tp->ipb.CMD_Status_IV = 0;
469 tp->ipb.TX_IV = 0;
470 tp->ipb.RX_IV = 0;
471 tp->ipb.Ring_Status_IV = 0;
472 tp->ipb.SCB_Clear_IV = 0;
473 tp->ipb.Adapter_CHK_IV = 0;
474 tp->ipb.RX_Burst_Size = BURST_SIZE;
475 tp->ipb.TX_Burst_Size = BURST_SIZE;
476 tp->ipb.DMA_Abort_Thrhld = DMA_RETRIES;
477 tp->ipb.SCB_Addr = 0;
478 tp->ipb.SSB_Addr = 0;
479}
480
481/*
482 * Initializes the open parameter block.
483 */
484static void tms380tr_init_opb(struct net_device *dev)
485{
486 struct net_local *tp;
487 unsigned long Addr;
488 unsigned short RplSize = RPL_SIZE;
489 unsigned short TplSize = TPL_SIZE;
490 unsigned short BufferSize = BUFFER_SIZE;
491 int i;
492
493 tp = netdev_priv(dev);
494
495 tp->ocpl.OPENOptions = 0;
496 tp->ocpl.OPENOptions |= ENABLE_FULL_DUPLEX_SELECTION;
497 tp->ocpl.FullDuplex = 0;
498 tp->ocpl.FullDuplex |= OPEN_FULL_DUPLEX_OFF;
499
500 /*
501 * Set node address
502 *
503 * We go ahead and put it in the OPB even though on
504 * most of the generic adapters this isn't required.
505 * Its simpler this way. -- ASF
506 */
507 for (i=0;i<6;i++)
508 tp->ocpl.NodeAddr[i] = ((unsigned char *)dev->dev_addr)[i];
509
510 tp->ocpl.GroupAddr = 0;
511 tp->ocpl.FunctAddr = 0;
512 tp->ocpl.RxListSize = cpu_to_be16((unsigned short)RplSize);
513 tp->ocpl.TxListSize = cpu_to_be16((unsigned short)TplSize);
514 tp->ocpl.BufSize = cpu_to_be16((unsigned short)BufferSize);
515 tp->ocpl.Reserved = 0;
516 tp->ocpl.TXBufMin = TX_BUF_MIN;
517 tp->ocpl.TXBufMax = TX_BUF_MAX;
518
519 Addr = htonl(((char *)tp->ProductID - (char *)tp) + tp->dmabuffer);
520
521 tp->ocpl.ProdIDAddr[0] = LOWORD(Addr);
522 tp->ocpl.ProdIDAddr[1] = HIWORD(Addr);
523}
524
525/*
526 * Send OPEN command to adapter
527 */
528static void tms380tr_open_adapter(struct net_device *dev)
529{
530 struct net_local *tp = netdev_priv(dev);
531
532 if(tp->OpenCommandIssued)
533 return;
534
535 tp->OpenCommandIssued = 1;
536 tms380tr_exec_cmd(dev, OC_OPEN);
537}
538
539/*
540 * Clear the adapter's interrupt flag. Clear system interrupt enable
541 * (SINTEN): disable adapter to system interrupts.
542 */
543static void tms380tr_disable_interrupts(struct net_device *dev)
544{
545 SIFWRITEB(0, SIFACL);
546}
547
548/*
549 * Set the adapter's interrupt flag. Set system interrupt enable
550 * (SINTEN): enable adapter to system interrupts.
551 */
552static void tms380tr_enable_interrupts(struct net_device *dev)
553{
554 SIFWRITEB(ACL_SINTEN, SIFACL);
555}
556
557/*
558 * Put command in command queue, try to execute it.
559 */
560static void tms380tr_exec_cmd(struct net_device *dev, unsigned short Command)
561{
562 struct net_local *tp = netdev_priv(dev);
563
564 tp->CMDqueue |= Command;
565 tms380tr_chk_outstanding_cmds(dev);
566}
567
568static void tms380tr_timeout(struct net_device *dev)
569{
570 /*
571 * If we get here, some higher level has decided we are broken.
572 * There should really be a "kick me" function call instead.
573 *
574 * Resetting the token ring adapter takes a long time so just
575 * fake transmission time and go on trying. Our own timeout
576 * routine is in tms380tr_timer_chk()
577 */
578 dev->trans_start = jiffies; /* prevent tx timeout */
579 netif_wake_queue(dev);
580}
581
582/*
583 * Gets skb from system, queues it and checks if it can be sent
584 */
585static netdev_tx_t tms380tr_send_packet(struct sk_buff *skb,
586 struct net_device *dev)
587{
588 struct net_local *tp = netdev_priv(dev);
589 netdev_tx_t rc;
590
591 rc = tms380tr_hardware_send_packet(skb, dev);
592 if(tp->TplFree->NextTPLPtr->BusyFlag)
593 netif_stop_queue(dev);
594 return rc;
595}
596
597/*
598 * Move frames into adapter tx queue
599 */
600static netdev_tx_t tms380tr_hardware_send_packet(struct sk_buff *skb,
601 struct net_device *dev)
602{
603 TPL *tpl;
604 short length;
605 unsigned char *buf;
606 unsigned long flags;
607 int i;
608 dma_addr_t dmabuf, newbuf;
609 struct net_local *tp = netdev_priv(dev);
610
611 /* Try to get a free TPL from the chain.
612 *
613 * NOTE: We *must* always leave one unused TPL in the chain,
614 * because otherwise the adapter might send frames twice.
615 */
616 spin_lock_irqsave(&tp->lock, flags);
617 if(tp->TplFree->NextTPLPtr->BusyFlag) { /* No free TPL */
618 if (tms380tr_debug > 0)
619 printk(KERN_DEBUG "%s: No free TPL\n", dev->name);
620 spin_unlock_irqrestore(&tp->lock, flags);
621 return NETDEV_TX_BUSY;
622 }
623
624 dmabuf = 0;
625
626 /* Is buffer reachable for Busmaster-DMA? */
627
628 length = skb->len;
629 dmabuf = dma_map_single(tp->pdev, skb->data, length, DMA_TO_DEVICE);
630 if(tp->dmalimit && (dmabuf + length > tp->dmalimit)) {
631 /* Copy frame to local buffer */
632 dma_unmap_single(tp->pdev, dmabuf, length, DMA_TO_DEVICE);
633 dmabuf = 0;
634 i = tp->TplFree->TPLIndex;
635 buf = tp->LocalTxBuffers[i];
636 skb_copy_from_linear_data(skb, buf, length);
637 newbuf = ((char *)buf - (char *)tp) + tp->dmabuffer;
638 }
639 else {
640 /* Send direct from skb->data */
641 newbuf = dmabuf;
642 buf = skb->data;
643 }
644 /* Source address in packet? */
645 tms380tr_chk_src_addr(buf, dev->dev_addr);
646 tp->LastSendTime = jiffies;
647 tpl = tp->TplFree; /* Get the "free" TPL */
648 tpl->BusyFlag = 1; /* Mark TPL as busy */
649 tp->TplFree = tpl->NextTPLPtr;
650
651 /* Save the skb for delayed return of skb to system */
652 tpl->Skb = skb;
653 tpl->DMABuff = dmabuf;
654 tpl->FragList[0].DataCount = cpu_to_be16((unsigned short)length);
655 tpl->FragList[0].DataAddr = htonl(newbuf);
656
657 /* Write the data length in the transmit list. */
658 tpl->FrameSize = cpu_to_be16((unsigned short)length);
659 tpl->MData = buf;
660
661 /* Transmit the frame and set the status values. */
662 tms380tr_write_tpl_status(tpl, TX_VALID | TX_START_FRAME
663 | TX_END_FRAME | TX_PASS_SRC_ADDR
664 | TX_FRAME_IRQ);
665
666 /* Let adapter send the frame. */
667 tms380tr_exec_sifcmd(dev, CMD_TX_VALID);
668 spin_unlock_irqrestore(&tp->lock, flags);
669
670 return NETDEV_TX_OK;
671}
672
673/*
674 * Write the given value to the 'Status' field of the specified TPL.
675 * NOTE: This function should be used whenever the status of any TPL must be
676 * modified by the driver, because the compiler may otherwise change the
677 * order of instructions such that writing the TPL status may be executed at
678 * an undesirable time. When this function is used, the status is always
679 * written when the function is called.
680 */
681static void tms380tr_write_tpl_status(TPL *tpl, unsigned int Status)
682{
683 tpl->Status = Status;
684}
685
686static void tms380tr_chk_src_addr(unsigned char *frame, unsigned char *hw_addr)
687{
688 unsigned char SRBit;
689
690 if((((unsigned long)frame[8]) & ~0x80) != 0) /* Compare 4 bytes */
691 return;
692 if((unsigned short)frame[12] != 0) /* Compare 2 bytes */
693 return;
694
695 SRBit = frame[8] & 0x80;
696 memcpy(&frame[8], hw_addr, 6);
697 frame[8] |= SRBit;
698}
699
700/*
701 * The timer routine: Check if adapter still open and working, reopen if not.
702 */
703static void tms380tr_timer_chk(unsigned long data)
704{
705 struct net_device *dev = (struct net_device*)data;
706 struct net_local *tp = netdev_priv(dev);
707
708 if(tp->HaltInProgress)
709 return;
710
711 tms380tr_chk_outstanding_cmds(dev);
712 if(time_before(tp->LastSendTime + SEND_TIMEOUT, jiffies) &&
713 (tp->TplFree != tp->TplBusy))
714 {
715 /* Anything to send, but stalled too long */
716 tp->LastSendTime = jiffies;
717 tms380tr_exec_cmd(dev, OC_CLOSE); /* Does reopen automatically */
718 }
719
720 tp->timer.expires = jiffies + 2*HZ;
721 add_timer(&tp->timer);
722
723 if(tp->AdapterOpenFlag || tp->ReOpenInProgress)
724 return;
725 tp->ReOpenInProgress = 1;
726 tms380tr_open_adapter(dev);
727}
728
729/*
730 * The typical workload of the driver: Handle the network interface interrupts.
731 */
732irqreturn_t tms380tr_interrupt(int irq, void *dev_id)
733{
734 struct net_device *dev = dev_id;
735 struct net_local *tp;
736 unsigned short irq_type;
737 int handled = 0;
738
739 tp = netdev_priv(dev);
740
741 irq_type = SIFREADW(SIFSTS);
742
743 while(irq_type & STS_SYSTEM_IRQ) {
744 handled = 1;
745 irq_type &= STS_IRQ_MASK;
746
747 if(!tms380tr_chk_ssb(tp, irq_type)) {
748 printk(KERN_DEBUG "%s: DATA LATE occurred\n", dev->name);
749 break;
750 }
751
752 switch(irq_type) {
753 case STS_IRQ_RECEIVE_STATUS:
754 tms380tr_reset_interrupt(dev);
755 tms380tr_rcv_status_irq(dev);
756 break;
757
758 case STS_IRQ_TRANSMIT_STATUS:
759 /* Check if TRANSMIT.HALT command is complete */
760 if(tp->ssb.Parm[0] & COMMAND_COMPLETE) {
761 tp->TransmitCommandActive = 0;
762 tp->TransmitHaltScheduled = 0;
763
764 /* Issue a new transmit command. */
765 tms380tr_exec_cmd(dev, OC_TRANSMIT);
766 }
767
768 tms380tr_reset_interrupt(dev);
769 tms380tr_tx_status_irq(dev);
770 break;
771
772 case STS_IRQ_COMMAND_STATUS:
773 /* The SSB contains status of last command
774 * other than receive/transmit.
775 */
776 tms380tr_cmd_status_irq(dev);
777 break;
778
779 case STS_IRQ_SCB_CLEAR:
780 /* The SCB is free for another command. */
781 tp->ScbInUse = 0;
782 tms380tr_chk_outstanding_cmds(dev);
783 break;
784
785 case STS_IRQ_RING_STATUS:
786 tms380tr_ring_status_irq(dev);
787 break;
788
789 case STS_IRQ_ADAPTER_CHECK:
790 tms380tr_chk_irq(dev);
791 break;
792
793 case STS_IRQ_LLC_STATUS:
794 printk(KERN_DEBUG "tms380tr: unexpected LLC status IRQ\n");
795 break;
796
797 case STS_IRQ_TIMER:
798 printk(KERN_DEBUG "tms380tr: unexpected Timer IRQ\n");
799 break;
800
801 case STS_IRQ_RECEIVE_PENDING:
802 printk(KERN_DEBUG "tms380tr: unexpected Receive Pending IRQ\n");
803 break;
804
805 default:
806 printk(KERN_DEBUG "Unknown Token Ring IRQ (0x%04x)\n", irq_type);
807 break;
808 }
809
810 /* Reset system interrupt if not already done. */
811 if(irq_type != STS_IRQ_TRANSMIT_STATUS &&
812 irq_type != STS_IRQ_RECEIVE_STATUS) {
813 tms380tr_reset_interrupt(dev);
814 }
815
816 irq_type = SIFREADW(SIFSTS);
817 }
818
819 return IRQ_RETVAL(handled);
820}
821
822/*
823 * Reset the INTERRUPT SYSTEM bit and issue SSB CLEAR command.
824 */
825static void tms380tr_reset_interrupt(struct net_device *dev)
826{
827 struct net_local *tp = netdev_priv(dev);
828 SSB *ssb = &tp->ssb;
829
830 /*
831 * [Workaround for "Data Late"]
832 * Set all fields of the SSB to well-defined values so we can
833 * check if the adapter has written the SSB.
834 */
835
836 ssb->STS = (unsigned short) -1;
837 ssb->Parm[0] = (unsigned short) -1;
838 ssb->Parm[1] = (unsigned short) -1;
839 ssb->Parm[2] = (unsigned short) -1;
840
841 /* Free SSB by issuing SSB_CLEAR command after reading IRQ code
842 * and clear STS_SYSTEM_IRQ bit: enable adapter for further interrupts.
843 */
844 tms380tr_exec_sifcmd(dev, CMD_SSB_CLEAR | CMD_CLEAR_SYSTEM_IRQ);
845}
846
847/*
848 * Check if the SSB has actually been written by the adapter.
849 */
850static unsigned char tms380tr_chk_ssb(struct net_local *tp, unsigned short IrqType)
851{
852 SSB *ssb = &tp->ssb; /* The address of the SSB. */
853
854 /* C 0 1 2 INTERRUPT CODE
855 * - - - - --------------
856 * 1 1 1 1 TRANSMIT STATUS
857 * 1 1 1 1 RECEIVE STATUS
858 * 1 ? ? 0 COMMAND STATUS
859 * 0 0 0 0 SCB CLEAR
860 * 1 1 0 0 RING STATUS
861 * 0 0 0 0 ADAPTER CHECK
862 *
863 * 0 = SSB field not affected by interrupt
864 * 1 = SSB field is affected by interrupt
865 *
866 * C = SSB ADDRESS +0: COMMAND
867 * 0 = SSB ADDRESS +2: STATUS 0
868 * 1 = SSB ADDRESS +4: STATUS 1
869 * 2 = SSB ADDRESS +6: STATUS 2
870 */
871
872 /* Check if this interrupt does use the SSB. */
873
874 if(IrqType != STS_IRQ_TRANSMIT_STATUS &&
875 IrqType != STS_IRQ_RECEIVE_STATUS &&
876 IrqType != STS_IRQ_COMMAND_STATUS &&
877 IrqType != STS_IRQ_RING_STATUS)
878 {
879 return 1; /* SSB not involved. */
880 }
881
882 /* Note: All fields of the SSB have been set to all ones (-1) after it
883 * has last been used by the software (see DriverIsr()).
884 *
885 * Check if the affected SSB fields are still unchanged.
886 */
887
888 if(ssb->STS == (unsigned short) -1)
889 return 0; /* Command field not yet available. */
890 if(IrqType == STS_IRQ_COMMAND_STATUS)
891 return 1; /* Status fields not always affected. */
892 if(ssb->Parm[0] == (unsigned short) -1)
893 return 0; /* Status 1 field not yet available. */
894 if(IrqType == STS_IRQ_RING_STATUS)
895 return 1; /* Status 2 & 3 fields not affected. */
896
897 /* Note: At this point, the interrupt is either TRANSMIT or RECEIVE. */
898 if(ssb->Parm[1] == (unsigned short) -1)
899 return 0; /* Status 2 field not yet available. */
900 if(ssb->Parm[2] == (unsigned short) -1)
901 return 0; /* Status 3 field not yet available. */
902
903 return 1; /* All SSB fields have been written by the adapter. */
904}
905
906/*
907 * Evaluates the command results status in the SSB status field.
908 */
909static void tms380tr_cmd_status_irq(struct net_device *dev)
910{
911 struct net_local *tp = netdev_priv(dev);
912 unsigned short ssb_cmd, ssb_parm_0;
913 unsigned short ssb_parm_1;
914 char *open_err = "Open error -";
915 char *code_err = "Open code -";
916
917 /* Copy the ssb values to local variables */
918 ssb_cmd = tp->ssb.STS;
919 ssb_parm_0 = tp->ssb.Parm[0];
920 ssb_parm_1 = tp->ssb.Parm[1];
921
922 if(ssb_cmd == OPEN)
923 {
924 tp->Sleeping = 0;
925 if(!tp->ReOpenInProgress)
926 wake_up_interruptible(&tp->wait_for_tok_int);
927
928 tp->OpenCommandIssued = 0;
929 tp->ScbInUse = 0;
930
931 if((ssb_parm_0 & 0x00FF) == GOOD_COMPLETION)
932 {
933 /* Success, the adapter is open. */
934 tp->LobeWireFaultLogged = 0;
935 tp->AdapterOpenFlag = 1;
936 tp->AdapterVirtOpenFlag = 1;
937 tp->TransmitCommandActive = 0;
938 tms380tr_exec_cmd(dev, OC_TRANSMIT);
939 tms380tr_exec_cmd(dev, OC_RECEIVE);
940
941 if(tp->ReOpenInProgress)
942 tp->ReOpenInProgress = 0;
943
944 return;
945 }
946 else /* The adapter did not open. */
947 {
948 if(ssb_parm_0 & NODE_ADDR_ERROR)
949 printk(KERN_INFO "%s: Node address error\n",
950 dev->name);
951 if(ssb_parm_0 & LIST_SIZE_ERROR)
952 printk(KERN_INFO "%s: List size error\n",
953 dev->name);
954 if(ssb_parm_0 & BUF_SIZE_ERROR)
955 printk(KERN_INFO "%s: Buffer size error\n",
956 dev->name);
957 if(ssb_parm_0 & TX_BUF_COUNT_ERROR)
958 printk(KERN_INFO "%s: Tx buffer count error\n",
959 dev->name);
960 if(ssb_parm_0 & INVALID_OPEN_OPTION)
961 printk(KERN_INFO "%s: Invalid open option\n",
962 dev->name);
963 if(ssb_parm_0 & OPEN_ERROR)
964 {
965 /* Show the open phase. */
966 switch(ssb_parm_0 & OPEN_PHASES_MASK)
967 {
968 case LOBE_MEDIA_TEST:
969 if(!tp->LobeWireFaultLogged)
970 {
971 tp->LobeWireFaultLogged = 1;
972 printk(KERN_INFO "%s: %s Lobe wire fault (check cable !).\n", dev->name, open_err);
973 }
974 tp->ReOpenInProgress = 1;
975 tp->AdapterOpenFlag = 0;
976 tp->AdapterVirtOpenFlag = 1;
977 tms380tr_open_adapter(dev);
978 return;
979
980 case PHYSICAL_INSERTION:
981 printk(KERN_INFO "%s: %s Physical insertion.\n", dev->name, open_err);
982 break;
983
984 case ADDRESS_VERIFICATION:
985 printk(KERN_INFO "%s: %s Address verification.\n", dev->name, open_err);
986 break;
987
988 case PARTICIPATION_IN_RING_POLL:
989 printk(KERN_INFO "%s: %s Participation in ring poll.\n", dev->name, open_err);
990 break;
991
992 case REQUEST_INITIALISATION:
993 printk(KERN_INFO "%s: %s Request initialisation.\n", dev->name, open_err);
994 break;
995
996 case FULLDUPLEX_CHECK:
997 printk(KERN_INFO "%s: %s Full duplex check.\n", dev->name, open_err);
998 break;
999
1000 default:
1001 printk(KERN_INFO "%s: %s Unknown open phase\n", dev->name, open_err);
1002 break;
1003 }
1004
1005 /* Show the open errors. */
1006 switch(ssb_parm_0 & OPEN_ERROR_CODES_MASK)
1007 {
1008 case OPEN_FUNCTION_FAILURE:
1009 printk(KERN_INFO "%s: %s OPEN_FUNCTION_FAILURE", dev->name, code_err);
1010 tp->LastOpenStatus =
1011 OPEN_FUNCTION_FAILURE;
1012 break;
1013
1014 case OPEN_SIGNAL_LOSS:
1015 printk(KERN_INFO "%s: %s OPEN_SIGNAL_LOSS\n", dev->name, code_err);
1016 tp->LastOpenStatus =
1017 OPEN_SIGNAL_LOSS;
1018 break;
1019
1020 case OPEN_TIMEOUT:
1021 printk(KERN_INFO "%s: %s OPEN_TIMEOUT\n", dev->name, code_err);
1022 tp->LastOpenStatus =
1023 OPEN_TIMEOUT;
1024 break;
1025
1026 case OPEN_RING_FAILURE:
1027 printk(KERN_INFO "%s: %s OPEN_RING_FAILURE\n", dev->name, code_err);
1028 tp->LastOpenStatus =
1029 OPEN_RING_FAILURE;
1030 break;
1031
1032 case OPEN_RING_BEACONING:
1033 printk(KERN_INFO "%s: %s OPEN_RING_BEACONING\n", dev->name, code_err);
1034 tp->LastOpenStatus =
1035 OPEN_RING_BEACONING;
1036 break;
1037
1038 case OPEN_DUPLICATE_NODEADDR:
1039 printk(KERN_INFO "%s: %s OPEN_DUPLICATE_NODEADDR\n", dev->name, code_err);
1040 tp->LastOpenStatus =
1041 OPEN_DUPLICATE_NODEADDR;
1042 break;
1043
1044 case OPEN_REQUEST_INIT:
1045 printk(KERN_INFO "%s: %s OPEN_REQUEST_INIT\n", dev->name, code_err);
1046 tp->LastOpenStatus =
1047 OPEN_REQUEST_INIT;
1048 break;
1049
1050 case OPEN_REMOVE_RECEIVED:
1051 printk(KERN_INFO "%s: %s OPEN_REMOVE_RECEIVED", dev->name, code_err);
1052 tp->LastOpenStatus =
1053 OPEN_REMOVE_RECEIVED;
1054 break;
1055
1056 case OPEN_FULLDUPLEX_SET:
1057 printk(KERN_INFO "%s: %s OPEN_FULLDUPLEX_SET\n", dev->name, code_err);
1058 tp->LastOpenStatus =
1059 OPEN_FULLDUPLEX_SET;
1060 break;
1061
1062 default:
1063 printk(KERN_INFO "%s: %s Unknown open err code", dev->name, code_err);
1064 tp->LastOpenStatus =
1065 OPEN_FUNCTION_FAILURE;
1066 break;
1067 }
1068 }
1069
1070 tp->AdapterOpenFlag = 0;
1071 tp->AdapterVirtOpenFlag = 0;
1072
1073 return;
1074 }
1075 }
1076 else
1077 {
1078 if(ssb_cmd != READ_ERROR_LOG)
1079 return;
1080
1081 /* Add values from the error log table to the MAC
1082 * statistics counters and update the errorlogtable
1083 * memory.
1084 */
1085 tp->MacStat.line_errors += tp->errorlogtable.Line_Error;
1086 tp->MacStat.burst_errors += tp->errorlogtable.Burst_Error;
1087 tp->MacStat.A_C_errors += tp->errorlogtable.ARI_FCI_Error;
1088 tp->MacStat.lost_frames += tp->errorlogtable.Lost_Frame_Error;
1089 tp->MacStat.recv_congest_count += tp->errorlogtable.Rx_Congest_Error;
1090 tp->MacStat.rx_errors += tp->errorlogtable.Rx_Congest_Error;
1091 tp->MacStat.frame_copied_errors += tp->errorlogtable.Frame_Copied_Error;
1092 tp->MacStat.token_errors += tp->errorlogtable.Token_Error;
1093 tp->MacStat.dummy1 += tp->errorlogtable.DMA_Bus_Error;
1094 tp->MacStat.dummy1 += tp->errorlogtable.DMA_Parity_Error;
1095 tp->MacStat.abort_delimiters += tp->errorlogtable.AbortDelimeters;
1096 tp->MacStat.frequency_errors += tp->errorlogtable.Frequency_Error;
1097 tp->MacStat.internal_errors += tp->errorlogtable.Internal_Error;
1098 }
1099}
1100
1101/*
1102 * The inverse routine to tms380tr_open().
1103 */
1104int tms380tr_close(struct net_device *dev)
1105{
1106 struct net_local *tp = netdev_priv(dev);
1107 netif_stop_queue(dev);
1108
1109 del_timer(&tp->timer);
1110
1111 /* Flush the Tx and disable Rx here. */
1112
1113 tp->HaltInProgress = 1;
1114 tms380tr_exec_cmd(dev, OC_CLOSE);
1115 tp->timer.expires = jiffies + 1*HZ;
1116 tp->timer.function = tms380tr_timer_end_wait;
1117 tp->timer.data = (unsigned long)dev;
1118 add_timer(&tp->timer);
1119
1120 tms380tr_enable_interrupts(dev);
1121
1122 tp->Sleeping = 1;
1123 interruptible_sleep_on(&tp->wait_for_tok_int);
1124 tp->TransmitCommandActive = 0;
1125
1126 del_timer(&tp->timer);
1127 tms380tr_disable_interrupts(dev);
1128
1129#if defined(CONFIG_ISA) && defined(CONFIG_ISA_DMA_API)
1130 if(dev->dma > 0)
1131 {
1132 unsigned long flags=claim_dma_lock();
1133 disable_dma(dev->dma);
1134 release_dma_lock(flags);
1135 }
1136#endif
1137
1138 SIFWRITEW(0xFF00, SIFCMD);
1139#if 0
1140 if(dev->dma > 0) /* what the? */
1141 SIFWRITEB(0xff, POSREG);
1142#endif
1143 tms380tr_cancel_tx_queue(tp);
1144
1145 return 0;
1146}
1147
1148/*
1149 * Get the current statistics. This may be called with the card open
1150 * or closed.
1151 */
1152static struct net_device_stats *tms380tr_get_stats(struct net_device *dev)
1153{
1154 struct net_local *tp = netdev_priv(dev);
1155
1156 return (struct net_device_stats *)&tp->MacStat;
1157}
1158
1159/*
1160 * Set or clear the multicast filter for this adapter.
1161 */
1162static void tms380tr_set_multicast_list(struct net_device *dev)
1163{
1164 struct net_local *tp = netdev_priv(dev);
1165 unsigned int OpenOptions;
1166
1167 OpenOptions = tp->ocpl.OPENOptions &
1168 ~(PASS_ADAPTER_MAC_FRAMES
1169 | PASS_ATTENTION_FRAMES
1170 | PASS_BEACON_MAC_FRAMES
1171 | COPY_ALL_MAC_FRAMES
1172 | COPY_ALL_NON_MAC_FRAMES);
1173
1174 tp->ocpl.FunctAddr = 0;
1175
1176 if(dev->flags & IFF_PROMISC)
1177 /* Enable promiscuous mode */
1178 OpenOptions |= COPY_ALL_NON_MAC_FRAMES |
1179 COPY_ALL_MAC_FRAMES;
1180 else
1181 {
1182 if(dev->flags & IFF_ALLMULTI)
1183 {
1184 /* Disable promiscuous mode, use normal mode. */
1185 tp->ocpl.FunctAddr = 0xFFFFFFFF;
1186 }
1187 else
1188 {
1189 struct netdev_hw_addr *ha;
1190
1191 netdev_for_each_mc_addr(ha, dev) {
1192 ((char *)(&tp->ocpl.FunctAddr))[0] |=
1193 ha->addr[2];
1194 ((char *)(&tp->ocpl.FunctAddr))[1] |=
1195 ha->addr[3];
1196 ((char *)(&tp->ocpl.FunctAddr))[2] |=
1197 ha->addr[4];
1198 ((char *)(&tp->ocpl.FunctAddr))[3] |=
1199 ha->addr[5];
1200 }
1201 }
1202 tms380tr_exec_cmd(dev, OC_SET_FUNCT_ADDR);
1203 }
1204
1205 tp->ocpl.OPENOptions = OpenOptions;
1206 tms380tr_exec_cmd(dev, OC_MODIFY_OPEN_PARMS);
1207}
1208
1209/*
1210 * Wait for some time (microseconds)
1211 */
1212void tms380tr_wait(unsigned long time)
1213{
1214#if 0
1215 long tmp;
1216
1217 tmp = jiffies + time/(1000000/HZ);
1218 do {
1219 tmp = schedule_timeout_interruptible(tmp);
1220 } while(time_after(tmp, jiffies));
1221#else
1222 mdelay(time / 1000);
1223#endif
1224}
1225
1226/*
1227 * Write a command value to the SIFCMD register
1228 */
1229static void tms380tr_exec_sifcmd(struct net_device *dev, unsigned int WriteValue)
1230{
1231 unsigned short cmd;
1232 unsigned short SifStsValue;
1233 unsigned long loop_counter;
1234
1235 WriteValue = ((WriteValue ^ CMD_SYSTEM_IRQ) | CMD_INTERRUPT_ADAPTER);
1236 cmd = (unsigned short)WriteValue;
1237 loop_counter = 0,5 * 800000;
1238 do {
1239 SifStsValue = SIFREADW(SIFSTS);
1240 } while((SifStsValue & CMD_INTERRUPT_ADAPTER) && loop_counter--);
1241 SIFWRITEW(cmd, SIFCMD);
1242}
1243
1244/*
1245 * Processes adapter hardware reset, halts adapter and downloads firmware,
1246 * clears the halt bit.
1247 */
1248static int tms380tr_reset_adapter(struct net_device *dev)
1249{
1250 struct net_local *tp = netdev_priv(dev);
1251 unsigned short *fw_ptr;
1252 unsigned short count, c, count2;
1253 const struct firmware *fw_entry = NULL;
1254
1255 if (request_firmware(&fw_entry, "tms380tr.bin", tp->pdev) != 0) {
1256 printk(KERN_ALERT "%s: firmware %s is missing, cannot start.\n",
1257 dev->name, "tms380tr.bin");
1258 return -1;
1259 }
1260
1261 fw_ptr = (unsigned short *)fw_entry->data;
1262 count2 = fw_entry->size / 2;
1263
1264 /* Hardware adapter reset */
1265 SIFWRITEW(ACL_ARESET, SIFACL);
1266 tms380tr_wait(40);
1267
1268 c = SIFREADW(SIFACL);
1269 tms380tr_wait(20);
1270
1271 if(dev->dma == 0) /* For PCI adapters */
1272 {
1273 c &= ~(ACL_NSELOUT0 | ACL_NSELOUT1); /* Clear bits */
1274 if(tp->setnselout)
1275 c |= (*tp->setnselout)(dev);
1276 }
1277
1278 /* In case a command is pending - forget it */
1279 tp->ScbInUse = 0;
1280
1281 c &= ~ACL_ARESET; /* Clear adapter reset bit */
1282 c |= ACL_CPHALT; /* Halt adapter CPU, allow download */
1283 c |= ACL_BOOT;
1284 c |= ACL_SINTEN;
1285 c &= ~ACL_PSDMAEN; /* Clear pseudo dma bit */
1286 SIFWRITEW(c, SIFACL);
1287 tms380tr_wait(40);
1288
1289 count = 0;
1290 /* Download firmware via DIO interface: */
1291 do {
1292 if (count2 < 3) continue;
1293
1294 /* Download first address part */
1295 SIFWRITEW(*fw_ptr, SIFADX);
1296 fw_ptr++;
1297 count2--;
1298 /* Download second address part */
1299 SIFWRITEW(*fw_ptr, SIFADD);
1300 fw_ptr++;
1301 count2--;
1302
1303 if((count = *fw_ptr) != 0) /* Load loop counter */
1304 {
1305 fw_ptr++; /* Download block data */
1306 count2--;
1307 if (count > count2) continue;
1308
1309 for(; count > 0; count--)
1310 {
1311 SIFWRITEW(*fw_ptr, SIFINC);
1312 fw_ptr++;
1313 count2--;
1314 }
1315 }
1316 else /* Stop, if last block downloaded */
1317 {
1318 c = SIFREADW(SIFACL);
1319 c &= (~ACL_CPHALT | ACL_SINTEN);
1320
1321 /* Clear CPHALT and start BUD */
1322 SIFWRITEW(c, SIFACL);
1323 release_firmware(fw_entry);
1324 return 1;
1325 }
1326 } while(count == 0);
1327
1328 release_firmware(fw_entry);
1329 printk(KERN_INFO "%s: Adapter Download Failed\n", dev->name);
1330 return -1;
1331}
1332
1333MODULE_FIRMWARE("tms380tr.bin");
1334
1335/*
1336 * Starts bring up diagnostics of token ring adapter and evaluates
1337 * diagnostic results.
1338 */
1339static int tms380tr_bringup_diags(struct net_device *dev)
1340{
1341 int loop_cnt, retry_cnt;
1342 unsigned short Status;
1343
1344 tms380tr_wait(HALF_SECOND);
1345 tms380tr_exec_sifcmd(dev, EXEC_SOFT_RESET);
1346 tms380tr_wait(HALF_SECOND);
1347
1348 retry_cnt = BUD_MAX_RETRIES; /* maximal number of retrys */
1349
1350 do {
1351 retry_cnt--;
1352 if(tms380tr_debug > 3)
1353 printk(KERN_DEBUG "BUD-Status: ");
1354 loop_cnt = BUD_MAX_LOOPCNT; /* maximum: three seconds*/
1355 do { /* Inspect BUD results */
1356 loop_cnt--;
1357 tms380tr_wait(HALF_SECOND);
1358 Status = SIFREADW(SIFSTS);
1359 Status &= STS_MASK;
1360
1361 if(tms380tr_debug > 3)
1362 printk(KERN_DEBUG " %04X\n", Status);
1363 /* BUD successfully completed */
1364 if(Status == STS_INITIALIZE)
1365 return 1;
1366 /* Unrecoverable hardware error, BUD not completed? */
1367 } while((loop_cnt > 0) && ((Status & (STS_ERROR | STS_TEST))
1368 != (STS_ERROR | STS_TEST)));
1369
1370 /* Error preventing completion of BUD */
1371 if(retry_cnt > 0)
1372 {
1373 printk(KERN_INFO "%s: Adapter Software Reset.\n",
1374 dev->name);
1375 tms380tr_exec_sifcmd(dev, EXEC_SOFT_RESET);
1376 tms380tr_wait(HALF_SECOND);
1377 }
1378 } while(retry_cnt > 0);
1379
1380 Status = SIFREADW(SIFSTS);
1381
1382 printk(KERN_INFO "%s: Hardware error\n", dev->name);
1383 /* Hardware error occurred! */
1384 Status &= 0x001f;
1385 if (Status & 0x0010)
1386 printk(KERN_INFO "%s: BUD Error: Timeout\n", dev->name);
1387 else if ((Status & 0x000f) > 6)
1388 printk(KERN_INFO "%s: BUD Error: Illegal Failure\n", dev->name);
1389 else
1390 printk(KERN_INFO "%s: Bring Up Diagnostics Error (%04X) occurred\n", dev->name, Status & 0x000f);
1391
1392 return -1;
1393}
1394
1395/*
1396 * Copy initialisation data to adapter memory, beginning at address
1397 * 1:0A00; Starting DMA test and evaluating result bits.
1398 */
1399static int tms380tr_init_adapter(struct net_device *dev)
1400{
1401 struct net_local *tp = netdev_priv(dev);
1402
1403 const unsigned char SCB_Test[6] = {0x00, 0x00, 0xC1, 0xE2, 0xD4, 0x8B};
1404 const unsigned char SSB_Test[8] = {0xFF, 0xFF, 0xD1, 0xD7,
1405 0xC5, 0xD9, 0xC3, 0xD4};
1406 void *ptr = (void *)&tp->ipb;
1407 unsigned short *ipb_ptr = (unsigned short *)ptr;
1408 unsigned char *cb_ptr = (unsigned char *) &tp->scb;
1409 unsigned char *sb_ptr = (unsigned char *) &tp->ssb;
1410 unsigned short Status;
1411 int i, loop_cnt, retry_cnt;
1412
1413 /* Normalize: byte order low/high, word order high/low! (only IPB!) */
1414 tp->ipb.SCB_Addr = SWAPW(((char *)&tp->scb - (char *)tp) + tp->dmabuffer);
1415 tp->ipb.SSB_Addr = SWAPW(((char *)&tp->ssb - (char *)tp) + tp->dmabuffer);
1416
1417 if(tms380tr_debug > 3)
1418 {
1419 printk(KERN_DEBUG "%s: buffer (real): %lx\n", dev->name, (long) &tp->scb);
1420 printk(KERN_DEBUG "%s: buffer (virt): %lx\n", dev->name, (long) ((char *)&tp->scb - (char *)tp) + (long) tp->dmabuffer);
1421 printk(KERN_DEBUG "%s: buffer (DMA) : %lx\n", dev->name, (long) tp->dmabuffer);
1422 printk(KERN_DEBUG "%s: buffer (tp) : %lx\n", dev->name, (long) tp);
1423 }
1424 /* Maximum: three initialization retries */
1425 retry_cnt = INIT_MAX_RETRIES;
1426
1427 do {
1428 retry_cnt--;
1429
1430 /* Transfer initialization block */
1431 SIFWRITEW(0x0001, SIFADX);
1432
1433 /* To address 0001:0A00 of adapter RAM */
1434 SIFWRITEW(0x0A00, SIFADD);
1435
1436 /* Write 11 words to adapter RAM */
1437 for(i = 0; i < 11; i++)
1438 SIFWRITEW(ipb_ptr[i], SIFINC);
1439
1440 /* Execute SCB adapter command */
1441 tms380tr_exec_sifcmd(dev, CMD_EXECUTE);
1442
1443 loop_cnt = INIT_MAX_LOOPCNT; /* Maximum: 11 seconds */
1444
1445 /* While remaining retries, no error and not completed */
1446 do {
1447 Status = 0;
1448 loop_cnt--;
1449 tms380tr_wait(HALF_SECOND);
1450
1451 /* Mask interesting status bits */
1452 Status = SIFREADW(SIFSTS);
1453 Status &= STS_MASK;
1454 } while(((Status &(STS_INITIALIZE | STS_ERROR | STS_TEST)) != 0) &&
1455 ((Status & STS_ERROR) == 0) && (loop_cnt != 0));
1456
1457 if((Status & (STS_INITIALIZE | STS_ERROR | STS_TEST)) == 0)
1458 {
1459 /* Initialization completed without error */
1460 i = 0;
1461 do { /* Test if contents of SCB is valid */
1462 if(SCB_Test[i] != *(cb_ptr + i))
1463 {
1464 printk(KERN_INFO "%s: DMA failed\n", dev->name);
1465 /* DMA data error: wrong data in SCB */
1466 return -1;
1467 }
1468 i++;
1469 } while(i < 6);
1470
1471 i = 0;
1472 do { /* Test if contents of SSB is valid */
1473 if(SSB_Test[i] != *(sb_ptr + i))
1474 /* DMA data error: wrong data in SSB */
1475 return -1;
1476 i++;
1477 } while (i < 8);
1478
1479 return 1; /* Adapter successfully initialized */
1480 }
1481 else
1482 {
1483 if((Status & STS_ERROR) != 0)
1484 {
1485 /* Initialization error occurred */
1486 Status = SIFREADW(SIFSTS);
1487 Status &= STS_ERROR_MASK;
1488 /* ShowInitialisationErrorCode(Status); */
1489 printk(KERN_INFO "%s: Status error: %d\n", dev->name, Status);
1490 return -1; /* Unrecoverable error */
1491 }
1492 else
1493 {
1494 if(retry_cnt > 0)
1495 {
1496 /* Reset adapter and try init again */
1497 tms380tr_exec_sifcmd(dev, EXEC_SOFT_RESET);
1498 tms380tr_wait(HALF_SECOND);
1499 }
1500 }
1501 }
1502 } while(retry_cnt > 0);
1503
1504 printk(KERN_INFO "%s: Retry exceeded\n", dev->name);
1505 return -1;
1506}
1507
1508/*
1509 * Check for outstanding commands in command queue and tries to execute
1510 * command immediately. Corresponding command flag in command queue is cleared.
1511 */
1512static void tms380tr_chk_outstanding_cmds(struct net_device *dev)
1513{
1514 struct net_local *tp = netdev_priv(dev);
1515 unsigned long Addr = 0;
1516
1517 if(tp->CMDqueue == 0)
1518 return; /* No command execution */
1519
1520 /* If SCB in use: no command */
1521 if(tp->ScbInUse == 1)
1522 return;
1523
1524 /* Check if adapter is opened, avoiding COMMAND_REJECT
1525 * interrupt by the adapter!
1526 */
1527 if (tp->AdapterOpenFlag == 0) {
1528 if (tp->CMDqueue & OC_OPEN) {
1529 /* Execute OPEN command */
1530 tp->CMDqueue ^= OC_OPEN;
1531
1532 Addr = htonl(((char *)&tp->ocpl - (char *)tp) + tp->dmabuffer);
1533 tp->scb.Parm[0] = LOWORD(Addr);
1534 tp->scb.Parm[1] = HIWORD(Addr);
1535 tp->scb.CMD = OPEN;
1536 } else
1537 /* No OPEN command queued, but adapter closed. Note:
1538 * We'll try to re-open the adapter in DriverPoll()
1539 */
1540 return; /* No adapter command issued */
1541 } else {
1542 /* Adapter is open; evaluate command queue: try to execute
1543 * outstanding commands (depending on priority!) CLOSE
1544 * command queued
1545 */
1546 if (tp->CMDqueue & OC_CLOSE) {
1547 tp->CMDqueue ^= OC_CLOSE;
1548 tp->AdapterOpenFlag = 0;
1549 tp->scb.Parm[0] = 0; /* Parm[0], Parm[1] are ignored */
1550 tp->scb.Parm[1] = 0; /* but should be set to zero! */
1551 tp->scb.CMD = CLOSE;
1552 if(!tp->HaltInProgress)
1553 tp->CMDqueue |= OC_OPEN; /* re-open adapter */
1554 else
1555 tp->CMDqueue = 0; /* no more commands */
1556 } else if (tp->CMDqueue & OC_RECEIVE) {
1557 tp->CMDqueue ^= OC_RECEIVE;
1558 Addr = htonl(((char *)tp->RplHead - (char *)tp) + tp->dmabuffer);
1559 tp->scb.Parm[0] = LOWORD(Addr);
1560 tp->scb.Parm[1] = HIWORD(Addr);
1561 tp->scb.CMD = RECEIVE;
1562 } else if (tp->CMDqueue & OC_TRANSMIT_HALT) {
1563 /* NOTE: TRANSMIT.HALT must be checked
1564 * before TRANSMIT.
1565 */
1566 tp->CMDqueue ^= OC_TRANSMIT_HALT;
1567 tp->scb.CMD = TRANSMIT_HALT;
1568
1569 /* Parm[0] and Parm[1] are ignored
1570 * but should be set to zero!
1571 */
1572 tp->scb.Parm[0] = 0;
1573 tp->scb.Parm[1] = 0;
1574 } else if (tp->CMDqueue & OC_TRANSMIT) {
1575 /* NOTE: TRANSMIT must be
1576 * checked after TRANSMIT.HALT
1577 */
1578 if (tp->TransmitCommandActive) {
1579 if (!tp->TransmitHaltScheduled) {
1580 tp->TransmitHaltScheduled = 1;
1581 tms380tr_exec_cmd(dev, OC_TRANSMIT_HALT);
1582 }
1583 tp->TransmitCommandActive = 0;
1584 return;
1585 }
1586
1587 tp->CMDqueue ^= OC_TRANSMIT;
1588 tms380tr_cancel_tx_queue(tp);
1589 Addr = htonl(((char *)tp->TplBusy - (char *)tp) + tp->dmabuffer);
1590 tp->scb.Parm[0] = LOWORD(Addr);
1591 tp->scb.Parm[1] = HIWORD(Addr);
1592 tp->scb.CMD = TRANSMIT;
1593 tp->TransmitCommandActive = 1;
1594 } else if (tp->CMDqueue & OC_MODIFY_OPEN_PARMS) {
1595 tp->CMDqueue ^= OC_MODIFY_OPEN_PARMS;
1596 tp->scb.Parm[0] = tp->ocpl.OPENOptions; /* new OPEN options*/
1597 tp->scb.Parm[0] |= ENABLE_FULL_DUPLEX_SELECTION;
1598 tp->scb.Parm[1] = 0; /* is ignored but should be zero */
1599 tp->scb.CMD = MODIFY_OPEN_PARMS;
1600 } else if (tp->CMDqueue & OC_SET_FUNCT_ADDR) {
1601 tp->CMDqueue ^= OC_SET_FUNCT_ADDR;
1602 tp->scb.Parm[0] = LOWORD(tp->ocpl.FunctAddr);
1603 tp->scb.Parm[1] = HIWORD(tp->ocpl.FunctAddr);
1604 tp->scb.CMD = SET_FUNCT_ADDR;
1605 } else if (tp->CMDqueue & OC_SET_GROUP_ADDR) {
1606 tp->CMDqueue ^= OC_SET_GROUP_ADDR;
1607 tp->scb.Parm[0] = LOWORD(tp->ocpl.GroupAddr);
1608 tp->scb.Parm[1] = HIWORD(tp->ocpl.GroupAddr);
1609 tp->scb.CMD = SET_GROUP_ADDR;
1610 } else if (tp->CMDqueue & OC_READ_ERROR_LOG) {
1611 tp->CMDqueue ^= OC_READ_ERROR_LOG;
1612 Addr = htonl(((char *)&tp->errorlogtable - (char *)tp) + tp->dmabuffer);
1613 tp->scb.Parm[0] = LOWORD(Addr);
1614 tp->scb.Parm[1] = HIWORD(Addr);
1615 tp->scb.CMD = READ_ERROR_LOG;
1616 } else {
1617 printk(KERN_WARNING "CheckForOutstandingCommand: unknown Command\n");
1618 tp->CMDqueue = 0;
1619 return;
1620 }
1621 }
1622
1623 tp->ScbInUse = 1; /* Set semaphore: SCB in use. */
1624
1625 /* Execute SCB and generate IRQ when done. */
1626 tms380tr_exec_sifcmd(dev, CMD_EXECUTE | CMD_SCB_REQUEST);
1627}
1628
1629/*
1630 * IRQ conditions: signal loss on the ring, transmit or receive of beacon
1631 * frames (disabled if bit 1 of OPEN option is set); report error MAC
1632 * frame transmit (disabled if bit 2 of OPEN option is set); open or short
1633 * circuit fault on the lobe is detected; remove MAC frame received;
1634 * error counter overflow (255); opened adapter is the only station in ring.
1635 * After some of the IRQs the adapter is closed!
1636 */
1637static void tms380tr_ring_status_irq(struct net_device *dev)
1638{
1639 struct net_local *tp = netdev_priv(dev);
1640
1641 tp->CurrentRingStatus = be16_to_cpu((unsigned short)tp->ssb.Parm[0]);
1642
1643 /* First: fill up statistics */
1644 if(tp->ssb.Parm[0] & SIGNAL_LOSS)
1645 {
1646 printk(KERN_INFO "%s: Signal Loss\n", dev->name);
1647 tp->MacStat.line_errors++;
1648 }
1649
1650 /* Adapter is closed, but initialized */
1651 if(tp->ssb.Parm[0] & LOBE_WIRE_FAULT)
1652 {
1653 printk(KERN_INFO "%s: Lobe Wire Fault, Reopen Adapter\n",
1654 dev->name);
1655 tp->MacStat.line_errors++;
1656 }
1657
1658 if(tp->ssb.Parm[0] & RING_RECOVERY)
1659 printk(KERN_INFO "%s: Ring Recovery\n", dev->name);
1660
1661 /* Counter overflow: read error log */
1662 if(tp->ssb.Parm[0] & COUNTER_OVERFLOW)
1663 {
1664 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
1665 tms380tr_exec_cmd(dev, OC_READ_ERROR_LOG);
1666 }
1667
1668 /* Adapter is closed, but initialized */
1669 if(tp->ssb.Parm[0] & REMOVE_RECEIVED)
1670 printk(KERN_INFO "%s: Remove Received, Reopen Adapter\n",
1671 dev->name);
1672
1673 /* Adapter is closed, but initialized */
1674 if(tp->ssb.Parm[0] & AUTO_REMOVAL_ERROR)
1675 printk(KERN_INFO "%s: Auto Removal Error, Reopen Adapter\n",
1676 dev->name);
1677
1678 if(tp->ssb.Parm[0] & HARD_ERROR)
1679 printk(KERN_INFO "%s: Hard Error\n", dev->name);
1680
1681 if(tp->ssb.Parm[0] & SOFT_ERROR)
1682 printk(KERN_INFO "%s: Soft Error\n", dev->name);
1683
1684 if(tp->ssb.Parm[0] & TRANSMIT_BEACON)
1685 printk(KERN_INFO "%s: Transmit Beacon\n", dev->name);
1686
1687 if(tp->ssb.Parm[0] & SINGLE_STATION)
1688 printk(KERN_INFO "%s: Single Station\n", dev->name);
1689
1690 /* Check if adapter has been closed */
1691 if(tp->ssb.Parm[0] & ADAPTER_CLOSED)
1692 {
1693 printk(KERN_INFO "%s: Adapter closed (Reopening),"
1694 "CurrentRingStat %x\n",
1695 dev->name, tp->CurrentRingStatus);
1696 tp->AdapterOpenFlag = 0;
1697 tms380tr_open_adapter(dev);
1698 }
1699}
1700
1701/*
1702 * Issued if adapter has encountered an unrecoverable hardware
1703 * or software error.
1704 */
1705static void tms380tr_chk_irq(struct net_device *dev)
1706{
1707 int i;
1708 unsigned short AdapterCheckBlock[4];
1709 struct net_local *tp = netdev_priv(dev);
1710
1711 tp->AdapterOpenFlag = 0; /* Adapter closed now */
1712
1713 /* Page number of adapter memory */
1714 SIFWRITEW(0x0001, SIFADX);
1715 /* Address offset */
1716 SIFWRITEW(CHECKADDR, SIFADR);
1717
1718 /* Reading 8 byte adapter check block. */
1719 for(i = 0; i < 4; i++)
1720 AdapterCheckBlock[i] = SIFREADW(SIFINC);
1721
1722 if(tms380tr_debug > 3)
1723 {
1724 printk(KERN_DEBUG "%s: AdapterCheckBlock: ", dev->name);
1725 for (i = 0; i < 4; i++)
1726 printk("%04X", AdapterCheckBlock[i]);
1727 printk("\n");
1728 }
1729
1730 switch(AdapterCheckBlock[0])
1731 {
1732 case DIO_PARITY:
1733 printk(KERN_INFO "%s: DIO parity error\n", dev->name);
1734 break;
1735
1736 case DMA_READ_ABORT:
1737 printk(KERN_INFO "%s DMA read operation aborted:\n",
1738 dev->name);
1739 switch (AdapterCheckBlock[1])
1740 {
1741 case 0:
1742 printk(KERN_INFO "Timeout\n");
1743 printk(KERN_INFO "Address: %04X %04X\n",
1744 AdapterCheckBlock[2],
1745 AdapterCheckBlock[3]);
1746 break;
1747
1748 case 1:
1749 printk(KERN_INFO "Parity error\n");
1750 printk(KERN_INFO "Address: %04X %04X\n",
1751 AdapterCheckBlock[2],
1752 AdapterCheckBlock[3]);
1753 break;
1754
1755 case 2:
1756 printk(KERN_INFO "Bus error\n");
1757 printk(KERN_INFO "Address: %04X %04X\n",
1758 AdapterCheckBlock[2],
1759 AdapterCheckBlock[3]);
1760 break;
1761
1762 default:
1763 printk(KERN_INFO "Unknown error.\n");
1764 break;
1765 }
1766 break;
1767
1768 case DMA_WRITE_ABORT:
1769 printk(KERN_INFO "%s: DMA write operation aborted:\n",
1770 dev->name);
1771 switch (AdapterCheckBlock[1])
1772 {
1773 case 0:
1774 printk(KERN_INFO "Timeout\n");
1775 printk(KERN_INFO "Address: %04X %04X\n",
1776 AdapterCheckBlock[2],
1777 AdapterCheckBlock[3]);
1778 break;
1779
1780 case 1:
1781 printk(KERN_INFO "Parity error\n");
1782 printk(KERN_INFO "Address: %04X %04X\n",
1783 AdapterCheckBlock[2],
1784 AdapterCheckBlock[3]);
1785 break;
1786
1787 case 2:
1788 printk(KERN_INFO "Bus error\n");
1789 printk(KERN_INFO "Address: %04X %04X\n",
1790 AdapterCheckBlock[2],
1791 AdapterCheckBlock[3]);
1792 break;
1793
1794 default:
1795 printk(KERN_INFO "Unknown error.\n");
1796 break;
1797 }
1798 break;
1799
1800 case ILLEGAL_OP_CODE:
1801 printk(KERN_INFO "%s: Illegal operation code in firmware\n",
1802 dev->name);
1803 /* Parm[0-3]: adapter internal register R13-R15 */
1804 break;
1805
1806 case PARITY_ERRORS:
1807 printk(KERN_INFO "%s: Adapter internal bus parity error\n",
1808 dev->name);
1809 /* Parm[0-3]: adapter internal register R13-R15 */
1810 break;
1811
1812 case RAM_DATA_ERROR:
1813 printk(KERN_INFO "%s: RAM data error\n", dev->name);
1814 /* Parm[0-1]: MSW/LSW address of RAM location. */
1815 break;
1816
1817 case RAM_PARITY_ERROR:
1818 printk(KERN_INFO "%s: RAM parity error\n", dev->name);
1819 /* Parm[0-1]: MSW/LSW address of RAM location. */
1820 break;
1821
1822 case RING_UNDERRUN:
1823 printk(KERN_INFO "%s: Internal DMA underrun detected\n",
1824 dev->name);
1825 break;
1826
1827 case INVALID_IRQ:
1828 printk(KERN_INFO "%s: Unrecognized interrupt detected\n",
1829 dev->name);
1830 /* Parm[0-3]: adapter internal register R13-R15 */
1831 break;
1832
1833 case INVALID_ERROR_IRQ:
1834 printk(KERN_INFO "%s: Unrecognized error interrupt detected\n",
1835 dev->name);
1836 /* Parm[0-3]: adapter internal register R13-R15 */
1837 break;
1838
1839 case INVALID_XOP:
1840 printk(KERN_INFO "%s: Unrecognized XOP request detected\n",
1841 dev->name);
1842 /* Parm[0-3]: adapter internal register R13-R15 */
1843 break;
1844
1845 default:
1846 printk(KERN_INFO "%s: Unknown status", dev->name);
1847 break;
1848 }
1849
1850 if(tms380tr_chipset_init(dev) == 1)
1851 {
1852 /* Restart of firmware successful */
1853 tp->AdapterOpenFlag = 1;
1854 }
1855}
1856
1857/*
1858 * Internal adapter pointer to RAM data are copied from adapter into
1859 * host system.
1860 */
1861static int tms380tr_read_ptr(struct net_device *dev)
1862{
1863 struct net_local *tp = netdev_priv(dev);
1864 unsigned short adapterram;
1865
1866 tms380tr_read_ram(dev, (unsigned char *)&tp->intptrs.BurnedInAddrPtr,
1867 ADAPTER_INT_PTRS, 16);
1868 tms380tr_read_ram(dev, (unsigned char *)&adapterram,
1869 cpu_to_be16((unsigned short)tp->intptrs.AdapterRAMPtr), 2);
1870 return be16_to_cpu(adapterram);
1871}
1872
1873/*
1874 * Reads a number of bytes from adapter to system memory.
1875 */
1876static void tms380tr_read_ram(struct net_device *dev, unsigned char *Data,
1877 unsigned short Address, int Length)
1878{
1879 int i;
1880 unsigned short old_sifadx, old_sifadr, InWord;
1881
1882 /* Save the current values */
1883 old_sifadx = SIFREADW(SIFADX);
1884 old_sifadr = SIFREADW(SIFADR);
1885
1886 /* Page number of adapter memory */
1887 SIFWRITEW(0x0001, SIFADX);
1888 /* Address offset in adapter RAM */
1889 SIFWRITEW(Address, SIFADR);
1890
1891 /* Copy len byte from adapter memory to system data area. */
1892 i = 0;
1893 for(;;)
1894 {
1895 InWord = SIFREADW(SIFINC);
1896
1897 *(Data + i) = HIBYTE(InWord); /* Write first byte */
1898 if(++i == Length) /* All is done break */
1899 break;
1900
1901 *(Data + i) = LOBYTE(InWord); /* Write second byte */
1902 if (++i == Length) /* All is done break */
1903 break;
1904 }
1905
1906 /* Restore original values */
1907 SIFWRITEW(old_sifadx, SIFADX);
1908 SIFWRITEW(old_sifadr, SIFADR);
1909}
1910
1911/*
1912 * Cancel all queued packets in the transmission queue.
1913 */
1914static void tms380tr_cancel_tx_queue(struct net_local* tp)
1915{
1916 TPL *tpl;
1917
1918 /*
1919 * NOTE: There must not be an active TRANSMIT command pending, when
1920 * this function is called.
1921 */
1922 if(tp->TransmitCommandActive)
1923 return;
1924
1925 for(;;)
1926 {
1927 tpl = tp->TplBusy;
1928 if(!tpl->BusyFlag)
1929 break;
1930 /* "Remove" TPL from busy list. */
1931 tp->TplBusy = tpl->NextTPLPtr;
1932 tms380tr_write_tpl_status(tpl, 0); /* Clear VALID bit */
1933 tpl->BusyFlag = 0; /* "free" TPL */
1934
1935 printk(KERN_INFO "Cancel tx (%08lXh).\n", (unsigned long)tpl);
1936 if (tpl->DMABuff)
1937 dma_unmap_single(tp->pdev, tpl->DMABuff, tpl->Skb->len, DMA_TO_DEVICE);
1938 dev_kfree_skb_any(tpl->Skb);
1939 }
1940}
1941
1942/*
1943 * This function is called whenever a transmit interrupt is generated by the
1944 * adapter. For a command complete interrupt, it is checked if we have to
1945 * issue a new transmit command or not.
1946 */
1947static void tms380tr_tx_status_irq(struct net_device *dev)
1948{
1949 struct net_local *tp = netdev_priv(dev);
1950 unsigned char HighByte, HighAc, LowAc;
1951 TPL *tpl;
1952
1953 /* NOTE: At this point the SSB from TRANSMIT STATUS is no longer
1954 * available, because the CLEAR SSB command has already been issued.
1955 *
1956 * Process all complete transmissions.
1957 */
1958
1959 for(;;)
1960 {
1961 tpl = tp->TplBusy;
1962 if(!tpl->BusyFlag || (tpl->Status
1963 & (TX_VALID | TX_FRAME_COMPLETE))
1964 != TX_FRAME_COMPLETE)
1965 {
1966 break;
1967 }
1968
1969 /* "Remove" TPL from busy list. */
1970 tp->TplBusy = tpl->NextTPLPtr ;
1971
1972 /* Check the transmit status field only for directed frames*/
1973 if(DIRECTED_FRAME(tpl) && (tpl->Status & TX_ERROR) == 0)
1974 {
1975 HighByte = GET_TRANSMIT_STATUS_HIGH_BYTE(tpl->Status);
1976 HighAc = GET_FRAME_STATUS_HIGH_AC(HighByte);
1977 LowAc = GET_FRAME_STATUS_LOW_AC(HighByte);
1978
1979 if((HighAc != LowAc) || (HighAc == AC_NOT_RECOGNIZED))
1980 {
1981 printk(KERN_DEBUG "%s: (DA=%08lX not recognized)\n",
1982 dev->name,
1983 *(unsigned long *)&tpl->MData[2+2]);
1984 }
1985 else
1986 {
1987 if(tms380tr_debug > 3)
1988 printk(KERN_DEBUG "%s: Directed frame tx'd\n",
1989 dev->name);
1990 }
1991 }
1992 else
1993 {
1994 if(!DIRECTED_FRAME(tpl))
1995 {
1996 if(tms380tr_debug > 3)
1997 printk(KERN_DEBUG "%s: Broadcast frame tx'd\n",
1998 dev->name);
1999 }
2000 }
2001
2002 tp->MacStat.tx_packets++;
2003 if (tpl->DMABuff)
2004 dma_unmap_single(tp->pdev, tpl->DMABuff, tpl->Skb->len, DMA_TO_DEVICE);
2005 dev_kfree_skb_irq(tpl->Skb);
2006 tpl->BusyFlag = 0; /* "free" TPL */
2007 }
2008
2009 if(!tp->TplFree->NextTPLPtr->BusyFlag)
2010 netif_wake_queue(dev);
2011}
2012
2013/*
2014 * Called if a frame receive interrupt is generated by the adapter.
2015 * Check if the frame is valid and indicate it to system.
2016 */
2017static void tms380tr_rcv_status_irq(struct net_device *dev)
2018{
2019 struct net_local *tp = netdev_priv(dev);
2020 unsigned char *ReceiveDataPtr;
2021 struct sk_buff *skb;
2022 unsigned int Length, Length2;
2023 RPL *rpl;
2024 RPL *SaveHead;
2025 dma_addr_t dmabuf;
2026
2027 /* NOTE: At this point the SSB from RECEIVE STATUS is no longer
2028 * available, because the CLEAR SSB command has already been issued.
2029 *
2030 * Process all complete receives.
2031 */
2032
2033 for(;;)
2034 {
2035 rpl = tp->RplHead;
2036 if(rpl->Status & RX_VALID)
2037 break; /* RPL still in use by adapter */
2038
2039 /* Forward RPLHead pointer to next list. */
2040 SaveHead = tp->RplHead;
2041 tp->RplHead = rpl->NextRPLPtr;
2042
2043 /* Get the frame size (Byte swap for Intel).
2044 * Do this early (see workaround comment below)
2045 */
2046 Length = be16_to_cpu(rpl->FrameSize);
2047
2048 /* Check if the Frame_Start, Frame_End and
2049 * Frame_Complete bits are set.
2050 */
2051 if((rpl->Status & VALID_SINGLE_BUFFER_FRAME)
2052 == VALID_SINGLE_BUFFER_FRAME)
2053 {
2054 ReceiveDataPtr = rpl->MData;
2055
2056 /* Workaround for delayed write of FrameSize on ISA
2057 * (FrameSize is false but valid-bit is reset)
2058 * Frame size is set to zero when the RPL is freed.
2059 * Length2 is there because there have also been
2060 * cases where the FrameSize was partially written
2061 */
2062 Length2 = be16_to_cpu(rpl->FrameSize);
2063
2064 if(Length == 0 || Length != Length2)
2065 {
2066 tp->RplHead = SaveHead;
2067 break; /* Return to tms380tr_interrupt */
2068 }
2069 tms380tr_update_rcv_stats(tp,ReceiveDataPtr,Length);
2070
2071 if(tms380tr_debug > 3)
2072 printk(KERN_DEBUG "%s: Packet Length %04X (%d)\n",
2073 dev->name, Length, Length);
2074
2075 /* Indicate the received frame to system the
2076 * adapter does the Source-Routing padding for
2077 * us. See: OpenOptions in tms380tr_init_opb()
2078 */
2079 skb = rpl->Skb;
2080 if(rpl->SkbStat == SKB_UNAVAILABLE)
2081 {
2082 /* Try again to allocate skb */
2083 skb = dev_alloc_skb(tp->MaxPacketSize);
2084 if(skb == NULL)
2085 {
2086 /* Update Stats ?? */
2087 }
2088 else
2089 {
2090 skb_put(skb, tp->MaxPacketSize);
2091 rpl->SkbStat = SKB_DATA_COPY;
2092 ReceiveDataPtr = rpl->MData;
2093 }
2094 }
2095
2096 if(skb && (rpl->SkbStat == SKB_DATA_COPY ||
2097 rpl->SkbStat == SKB_DMA_DIRECT))
2098 {
2099 if(rpl->SkbStat == SKB_DATA_COPY)
2100 skb_copy_to_linear_data(skb, ReceiveDataPtr,
2101 Length);
2102
2103 /* Deliver frame to system */
2104 rpl->Skb = NULL;
2105 skb_trim(skb,Length);
2106 skb->protocol = tr_type_trans(skb,dev);
2107 netif_rx(skb);
2108 }
2109 }
2110 else /* Invalid frame */
2111 {
2112 if(rpl->Skb != NULL)
2113 dev_kfree_skb_irq(rpl->Skb);
2114
2115 /* Skip list. */
2116 if(rpl->Status & RX_START_FRAME)
2117 /* Frame start bit is set -> overflow. */
2118 tp->MacStat.rx_errors++;
2119 }
2120 if (rpl->DMABuff)
2121 dma_unmap_single(tp->pdev, rpl->DMABuff, tp->MaxPacketSize, DMA_TO_DEVICE);
2122 rpl->DMABuff = 0;
2123
2124 /* Allocate new skb for rpl */
2125 rpl->Skb = dev_alloc_skb(tp->MaxPacketSize);
2126 /* skb == NULL ? then use local buffer */
2127 if(rpl->Skb == NULL)
2128 {
2129 rpl->SkbStat = SKB_UNAVAILABLE;
2130 rpl->FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[rpl->RPLIndex] - (char *)tp) + tp->dmabuffer);
2131 rpl->MData = tp->LocalRxBuffers[rpl->RPLIndex];
2132 }
2133 else /* skb != NULL */
2134 {
2135 rpl->Skb->dev = dev;
2136 skb_put(rpl->Skb, tp->MaxPacketSize);
2137
2138 /* Data unreachable for DMA ? then use local buffer */
2139 dmabuf = dma_map_single(tp->pdev, rpl->Skb->data, tp->MaxPacketSize, DMA_FROM_DEVICE);
2140 if(tp->dmalimit && (dmabuf + tp->MaxPacketSize > tp->dmalimit))
2141 {
2142 rpl->SkbStat = SKB_DATA_COPY;
2143 rpl->FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[rpl->RPLIndex] - (char *)tp) + tp->dmabuffer);
2144 rpl->MData = tp->LocalRxBuffers[rpl->RPLIndex];
2145 }
2146 else
2147 {
2148 /* DMA directly in skb->data */
2149 rpl->SkbStat = SKB_DMA_DIRECT;
2150 rpl->FragList[0].DataAddr = htonl(dmabuf);
2151 rpl->MData = rpl->Skb->data;
2152 rpl->DMABuff = dmabuf;
2153 }
2154 }
2155
2156 rpl->FragList[0].DataCount = cpu_to_be16((unsigned short)tp->MaxPacketSize);
2157 rpl->FrameSize = 0;
2158
2159 /* Pass the last RPL back to the adapter */
2160 tp->RplTail->FrameSize = 0;
2161
2162 /* Reset the CSTAT field in the list. */
2163 tms380tr_write_rpl_status(tp->RplTail, RX_VALID | RX_FRAME_IRQ);
2164
2165 /* Current RPL becomes last one in list. */
2166 tp->RplTail = tp->RplTail->NextRPLPtr;
2167
2168 /* Inform adapter about RPL valid. */
2169 tms380tr_exec_sifcmd(dev, CMD_RX_VALID);
2170 }
2171}
2172
2173/*
2174 * This function should be used whenever the status of any RPL must be
2175 * modified by the driver, because the compiler may otherwise change the
2176 * order of instructions such that writing the RPL status may be executed
2177 * at an undesirable time. When this function is used, the status is
2178 * always written when the function is called.
2179 */
2180static void tms380tr_write_rpl_status(RPL *rpl, unsigned int Status)
2181{
2182 rpl->Status = Status;
2183}
2184
2185/*
2186 * The function updates the statistic counters in mac->MacStat.
2187 * It differtiates between directed and broadcast/multicast ( ==functional)
2188 * frames.
2189 */
2190static void tms380tr_update_rcv_stats(struct net_local *tp, unsigned char DataPtr[],
2191 unsigned int Length)
2192{
2193 tp->MacStat.rx_packets++;
2194 tp->MacStat.rx_bytes += Length;
2195
2196 /* Test functional bit */
2197 if(DataPtr[2] & GROUP_BIT)
2198 tp->MacStat.multicast++;
2199}
2200
2201static int tms380tr_set_mac_address(struct net_device *dev, void *addr)
2202{
2203 struct net_local *tp = netdev_priv(dev);
2204 struct sockaddr *saddr = addr;
2205
2206 if (tp->AdapterOpenFlag || tp->AdapterVirtOpenFlag) {
2207 printk(KERN_WARNING "%s: Cannot set MAC/LAA address while card is open\n", dev->name);
2208 return -EIO;
2209 }
2210 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
2211 return 0;
2212}
2213
2214#if TMS380TR_DEBUG > 0
2215/*
2216 * Dump Packet (data)
2217 */
2218static void tms380tr_dump(unsigned char *Data, int length)
2219{
2220 int i, j;
2221
2222 for (i = 0, j = 0; i < length / 8; i++, j += 8)
2223 {
2224 printk(KERN_DEBUG "%02x %02x %02x %02x %02x %02x %02x %02x\n",
2225 Data[j+0],Data[j+1],Data[j+2],Data[j+3],
2226 Data[j+4],Data[j+5],Data[j+6],Data[j+7]);
2227 }
2228}
2229#endif
2230
2231void tmsdev_term(struct net_device *dev)
2232{
2233 struct net_local *tp;
2234
2235 tp = netdev_priv(dev);
2236 dma_unmap_single(tp->pdev, tp->dmabuffer, sizeof(struct net_local),
2237 DMA_BIDIRECTIONAL);
2238}
2239
2240const struct net_device_ops tms380tr_netdev_ops = {
2241 .ndo_open = tms380tr_open,
2242 .ndo_stop = tms380tr_close,
2243 .ndo_start_xmit = tms380tr_send_packet,
2244 .ndo_tx_timeout = tms380tr_timeout,
2245 .ndo_get_stats = tms380tr_get_stats,
2246 .ndo_set_rx_mode = tms380tr_set_multicast_list,
2247 .ndo_set_mac_address = tms380tr_set_mac_address,
2248};
2249EXPORT_SYMBOL(tms380tr_netdev_ops);
2250
2251int tmsdev_init(struct net_device *dev, struct device *pdev)
2252{
2253 struct net_local *tms_local;
2254
2255 memset(netdev_priv(dev), 0, sizeof(struct net_local));
2256 tms_local = netdev_priv(dev);
2257 init_waitqueue_head(&tms_local->wait_for_tok_int);
2258 if (pdev->dma_mask)
2259 tms_local->dmalimit = *pdev->dma_mask;
2260 else
2261 return -ENOMEM;
2262 tms_local->pdev = pdev;
2263 tms_local->dmabuffer = dma_map_single(pdev, (void *)tms_local,
2264 sizeof(struct net_local), DMA_BIDIRECTIONAL);
2265 if (tms_local->dmabuffer + sizeof(struct net_local) >
2266 tms_local->dmalimit)
2267 {
2268 printk(KERN_INFO "%s: Memory not accessible for DMA\n",
2269 dev->name);
2270 tmsdev_term(dev);
2271 return -ENOMEM;
2272 }
2273
2274 dev->netdev_ops = &tms380tr_netdev_ops;
2275 dev->watchdog_timeo = HZ;
2276
2277 return 0;
2278}
2279
2280EXPORT_SYMBOL(tms380tr_open);
2281EXPORT_SYMBOL(tms380tr_close);
2282EXPORT_SYMBOL(tms380tr_interrupt);
2283EXPORT_SYMBOL(tmsdev_init);
2284EXPORT_SYMBOL(tmsdev_term);
2285EXPORT_SYMBOL(tms380tr_wait);
2286
2287#ifdef MODULE
2288
2289static struct module *TMS380_module = NULL;
2290
2291int init_module(void)
2292{
2293 printk(KERN_DEBUG "%s", version);
2294
2295 TMS380_module = &__this_module;
2296 return 0;
2297}
2298
2299void cleanup_module(void)
2300{
2301 TMS380_module = NULL;
2302}
2303#endif
2304
2305MODULE_LICENSE("GPL");
2306
diff --git a/drivers/net/tokenring/tms380tr.h b/drivers/net/tokenring/tms380tr.h
deleted file mode 100644
index e5a617c586c2..000000000000
--- a/drivers/net/tokenring/tms380tr.h
+++ /dev/null
@@ -1,1141 +0,0 @@
1/*
2 * tms380tr.h: TI TMS380 Token Ring driver for Linux
3 *
4 * Authors:
5 * - Christoph Goos <cgoos@syskonnect.de>
6 * - Adam Fritzler
7 */
8
9#ifndef __LINUX_TMS380TR_H
10#define __LINUX_TMS380TR_H
11
12#ifdef __KERNEL__
13
14#include <linux/interrupt.h>
15
16/* module prototypes */
17extern const struct net_device_ops tms380tr_netdev_ops;
18int tms380tr_open(struct net_device *dev);
19int tms380tr_close(struct net_device *dev);
20irqreturn_t tms380tr_interrupt(int irq, void *dev_id);
21int tmsdev_init(struct net_device *dev, struct device *pdev);
22void tmsdev_term(struct net_device *dev);
23void tms380tr_wait(unsigned long time);
24
25#define TMS380TR_MAX_ADAPTERS 7
26
27#define SEND_TIMEOUT 10*HZ
28
29#define TR_RCF_LONGEST_FRAME_MASK 0x0070
30#define TR_RCF_FRAME4K 0x0030
31
32/*------------------------------------------------------------------*/
33/* Bit order for adapter communication with DMA */
34/* -------------------------------------------------------------- */
35/* Bit 8 | 9| 10| 11|| 12| 13| 14| 15|| 0| 1| 2| 3|| 4| 5| 6| 7| */
36/* -------------------------------------------------------------- */
37/* The bytes in a word must be byte swapped. Also, if a double */
38/* word is used for storage, then the words, as well as the bytes, */
39/* must be swapped. */
40/* Bit order for adapter communication with DIO */
41/* -------------------------------------------------------------- */
42/* Bit 0 | 1| 2| 3|| 4| 5| 6| 7|| 8| 9| 10| 11|| 12| 13| 14| 15| */
43/* -------------------------------------------------------------- */
44/*------------------------------------------------------------------*/
45
46/* Swap words of a long. */
47#define SWAPW(x) (((x) << 16) | ((x) >> 16))
48
49/* Get the low byte of a word. */
50#define LOBYTE(w) ((unsigned char)(w))
51
52/* Get the high byte of a word. */
53#define HIBYTE(w) ((unsigned char)((unsigned short)(w) >> 8))
54
55/* Get the low word of a long. */
56#define LOWORD(l) ((unsigned short)(l))
57
58/* Get the high word of a long. */
59#define HIWORD(l) ((unsigned short)((unsigned long)(l) >> 16))
60
61
62
63/* Token ring adapter I/O addresses for normal mode. */
64
65/*
66 * The SIF registers. Common to all adapters.
67 */
68/* Basic SIF (SRSX = 0) */
69#define SIFDAT 0x00 /* SIF/DMA data. */
70#define SIFINC 0x02 /* IO Word data with auto increment. */
71#define SIFINH 0x03 /* IO Byte data with auto increment. */
72#define SIFADR 0x04 /* SIF/DMA Address. */
73#define SIFCMD 0x06 /* SIF Command. */
74#define SIFSTS 0x06 /* SIF Status. */
75
76/* "Extended" SIF (SRSX = 1) */
77#define SIFACL 0x08 /* SIF Adapter Control Register. */
78#define SIFADD 0x0a /* SIF/DMA Address. -- 0x0a */
79#define SIFADX 0x0c /* 0x0c */
80#define DMALEN 0x0e /* SIF DMA length. -- 0x0e */
81
82/*
83 * POS Registers. Only for ISA Adapters.
84 */
85#define POSREG 0x10 /* Adapter Program Option Select (POS)
86 * Register: base IO address + 16 byte.
87 */
88#define POSREG_2 24L /* only for TR4/16+ adapter
89 * base IO address + 24 byte. -- 0x18
90 */
91
92/* SIFCMD command codes (high-low) */
93#define CMD_INTERRUPT_ADAPTER 0x8000 /* Cause internal adapter interrupt */
94#define CMD_ADAPTER_RESET 0x4000 /* Hardware reset of adapter */
95#define CMD_SSB_CLEAR 0x2000 /* Acknowledge to adapter to
96 * system interrupts.
97 */
98#define CMD_EXECUTE 0x1000 /* Execute SCB command */
99#define CMD_SCB_REQUEST 0x0800 /* Request adapter to interrupt
100 * system when SCB is available for
101 * another command.
102 */
103#define CMD_RX_CONTINUE 0x0400 /* Continue receive after odd pointer
104 * stop. (odd pointer receive method)
105 */
106#define CMD_RX_VALID 0x0200 /* Now actual RPL is valid. */
107#define CMD_TX_VALID 0x0100 /* Now actual TPL is valid. (valid
108 * bit receive/transmit method)
109 */
110#define CMD_SYSTEM_IRQ 0x0080 /* Adapter-to-attached-system
111 * interrupt is reset.
112 */
113#define CMD_CLEAR_SYSTEM_IRQ 0x0080 /* Clear SYSTEM_INTERRUPT bit.
114 * (write: 1=ignore, 0=reset)
115 */
116#define EXEC_SOFT_RESET 0xFF00 /* adapter soft reset. (restart
117 * adapter after hardware reset)
118 */
119
120
121/* ACL commands (high-low) */
122#define ACL_SWHLDA 0x0800 /* Software hold acknowledge. */
123#define ACL_SWDDIR 0x0400 /* Data transfer direction. */
124#define ACL_SWHRQ 0x0200 /* Pseudo DMA operation. */
125#define ACL_PSDMAEN 0x0100 /* Enable pseudo system DMA. */
126#define ACL_ARESET 0x0080 /* Adapter hardware reset command.
127 * (held in reset condition as
128 * long as bit is set)
129 */
130#define ACL_CPHALT 0x0040 /* Communication processor halt.
131 * (can only be set while ACL_ARESET
132 * bit is set; prevents adapter
133 * processor from executing code while
134 * downloading firmware)
135 */
136#define ACL_BOOT 0x0020
137#define ACL_SINTEN 0x0008 /* System interrupt enable/disable
138 * (1/0): can be written if ACL_ARESET
139 * is zero.
140 */
141#define ACL_PEN 0x0004
142
143#define ACL_NSELOUT0 0x0002
144#define ACL_NSELOUT1 0x0001 /* NSELOUTx have a card-specific
145 * meaning for setting ring speed.
146 */
147
148#define PS_DMA_MASK (ACL_SWHRQ | ACL_PSDMAEN)
149
150
151/* SIFSTS register return codes (high-low) */
152#define STS_SYSTEM_IRQ 0x0080 /* Adapter-to-attached-system
153 * interrupt is valid.
154 */
155#define STS_INITIALIZE 0x0040 /* INITIALIZE status. (ready to
156 * initialize)
157 */
158#define STS_TEST 0x0020 /* TEST status. (BUD not completed) */
159#define STS_ERROR 0x0010 /* ERROR status. (unrecoverable
160 * HW error occurred)
161 */
162#define STS_MASK 0x00F0 /* Mask interesting status bits. */
163#define STS_ERROR_MASK 0x000F /* Get Error Code by masking the
164 * interrupt code bits.
165 */
166#define ADAPTER_INT_PTRS 0x0A00 /* Address offset of adapter internal
167 * pointers 01:0a00 (high-low) have to
168 * be read after init and before open.
169 */
170
171
172/* Interrupt Codes (only MAC IRQs) */
173#define STS_IRQ_ADAPTER_CHECK 0x0000 /* unrecoverable hardware or
174 * software error.
175 */
176#define STS_IRQ_RING_STATUS 0x0004 /* SSB is updated with ring status. */
177#define STS_IRQ_LLC_STATUS 0x0005 /* Not used in MAC-only microcode */
178#define STS_IRQ_SCB_CLEAR 0x0006 /* SCB clear, following an
179 * SCB_REQUEST IRQ.
180 */
181#define STS_IRQ_TIMER 0x0007 /* Not normally used in MAC ucode */
182#define STS_IRQ_COMMAND_STATUS 0x0008 /* SSB is updated with command
183 * status.
184 */
185#define STS_IRQ_RECEIVE_STATUS 0x000A /* SSB is updated with receive
186 * status.
187 */
188#define STS_IRQ_TRANSMIT_STATUS 0x000C /* SSB is updated with transmit
189 * status
190 */
191#define STS_IRQ_RECEIVE_PENDING 0x000E /* Not used in MAC-only microcode */
192#define STS_IRQ_MASK 0x000F /* = STS_ERROR_MASK. */
193
194
195/* TRANSMIT_STATUS completion code: (SSB.Parm[0]) */
196#define COMMAND_COMPLETE 0x0080 /* TRANSMIT command completed
197 * (avoid this!) issue another transmit
198 * to send additional frames.
199 */
200#define FRAME_COMPLETE 0x0040 /* Frame has been transmitted;
201 * INTERRUPT_FRAME bit was set in the
202 * CSTAT request; indication of possibly
203 * more than one frame transmissions!
204 * SSB.Parm[0-1]: 32 bit pointer to
205 * TPL of last frame.
206 */
207#define LIST_ERROR 0x0020 /* Error in one of the TPLs that
208 * compose the frame; TRANSMIT
209 * terminated; Parm[1-2]: 32bit pointer
210 * to TPL which starts the error
211 * frame; error details in bits 8-13.
212 * (14?)
213 */
214#define FRAME_SIZE_ERROR 0x8000 /* FRAME_SIZE does not equal the sum of
215 * the valid DATA_COUNT fields;
216 * FRAME_SIZE less than header plus
217 * information field. (15 bytes +
218 * routing field) Or if FRAME_SIZE
219 * was specified as zero in one list.
220 */
221#define TX_THRESHOLD 0x4000 /* FRAME_SIZE greater than (BUFFER_SIZE
222 * - 9) * TX_BUF_MAX.
223 */
224#define ODD_ADDRESS 0x2000 /* Odd forward pointer value is
225 * read on a list without END_FRAME
226 * indication.
227 */
228#define FRAME_ERROR 0x1000 /* START_FRAME bit (not) anticipated,
229 * but (not) set.
230 */
231#define ACCESS_PRIORITY_ERROR 0x0800 /* Access priority requested has not
232 * been allowed.
233 */
234#define UNENABLED_MAC_FRAME 0x0400 /* MAC frame has source class of zero
235 * or MAC frame PCF ATTN field is
236 * greater than one.
237 */
238#define ILLEGAL_FRAME_FORMAT 0x0200 /* Bit 0 or FC field was set to one. */
239
240
241/*
242 * Since we need to support some functions even if the adapter is in a
243 * CLOSED state, we have a (pseudo-) command queue which holds commands
244 * that are outstandig to be executed.
245 *
246 * Each time a command completes, an interrupt occurs and the next
247 * command is executed. The command queue is actually a simple word with
248 * a bit for each outstandig command. Therefore the commands will not be
249 * executed in the order they have been queued.
250 *
251 * The following defines the command code bits and the command queue:
252 */
253#define OC_OPEN 0x0001 /* OPEN command */
254#define OC_TRANSMIT 0x0002 /* TRANSMIT command */
255#define OC_TRANSMIT_HALT 0x0004 /* TRANSMIT_HALT command */
256#define OC_RECEIVE 0x0008 /* RECEIVE command */
257#define OC_CLOSE 0x0010 /* CLOSE command */
258#define OC_SET_GROUP_ADDR 0x0020 /* SET_GROUP_ADDR command */
259#define OC_SET_FUNCT_ADDR 0x0040 /* SET_FUNCT_ADDR command */
260#define OC_READ_ERROR_LOG 0x0080 /* READ_ERROR_LOG command */
261#define OC_READ_ADAPTER 0x0100 /* READ_ADAPTER command */
262#define OC_MODIFY_OPEN_PARMS 0x0400 /* MODIFY_OPEN_PARMS command */
263#define OC_RESTORE_OPEN_PARMS 0x0800 /* RESTORE_OPEN_PARMS command */
264#define OC_SET_FIRST_16_GROUP 0x1000 /* SET_FIRST_16_GROUP command */
265#define OC_SET_BRIDGE_PARMS 0x2000 /* SET_BRIDGE_PARMS command */
266#define OC_CONFIG_BRIDGE_PARMS 0x4000 /* CONFIG_BRIDGE_PARMS command */
267
268#define OPEN 0x0300 /* C: open command. S: completion. */
269#define TRANSMIT 0x0400 /* C: transmit command. S: completion
270 * status. (reject: COMMAND_REJECT if
271 * adapter not opened, TRANSMIT already
272 * issued or address passed in the SCB
273 * not word aligned)
274 */
275#define TRANSMIT_HALT 0x0500 /* C: interrupt TX TPL chain; if no
276 * TRANSMIT command issued, the command
277 * is ignored (completion with TRANSMIT
278 * status (0x0400)!)
279 */
280#define RECEIVE 0x0600 /* C: receive command. S: completion
281 * status. (reject: COMMAND_REJECT if
282 * adapter not opened, RECEIVE already
283 * issued or address passed in the SCB
284 * not word aligned)
285 */
286#define CLOSE 0x0700 /* C: close adapter. S: completion.
287 * (COMMAND_REJECT if adapter not open)
288 */
289#define SET_GROUP_ADDR 0x0800 /* C: alter adapter group address after
290 * OPEN. S: completion. (COMMAND_REJECT
291 * if adapter not open)
292 */
293#define SET_FUNCT_ADDR 0x0900 /* C: alter adapter functional address
294 * after OPEN. S: completion.
295 * (COMMAND_REJECT if adapter not open)
296 */
297#define READ_ERROR_LOG 0x0A00 /* C: read adapter error counters.
298 * S: completion. (command ignored
299 * if adapter not open!)
300 */
301#define READ_ADAPTER 0x0B00 /* C: read data from adapter memory.
302 * (important: after init and before
303 * open!) S: completion. (ADAPTER_CHECK
304 * interrupt if undefined storage area
305 * read)
306 */
307#define MODIFY_OPEN_PARMS 0x0D00 /* C: modify some adapter operational
308 * parameters. (bit correspondend to
309 * WRAP_INTERFACE is ignored)
310 * S: completion. (reject:
311 * COMMAND_REJECT)
312 */
313#define RESTORE_OPEN_PARMS 0x0E00 /* C: modify some adapter operational
314 * parameters. (bit correspondend
315 * to WRAP_INTERFACE is ignored)
316 * S: completion. (reject:
317 * COMMAND_REJECT)
318 */
319#define SET_FIRST_16_GROUP 0x0F00 /* C: alter the first two bytes in
320 * adapter group address.
321 * S: completion. (reject:
322 * COMMAND_REJECT)
323 */
324#define SET_BRIDGE_PARMS 0x1000 /* C: values and conditions for the
325 * adapter hardware to use when frames
326 * are copied for forwarding.
327 * S: completion. (reject:
328 * COMMAND_REJECT)
329 */
330#define CONFIG_BRIDGE_PARMS 0x1100 /* C: ..
331 * S: completion. (reject:
332 * COMMAND_REJECT)
333 */
334
335#define SPEED_4 4
336#define SPEED_16 16 /* Default transmission speed */
337
338
339/* Initialization Parameter Block (IPB); word alignment necessary! */
340#define BURST_SIZE 0x0018 /* Default burst size */
341#define BURST_MODE 0x9F00 /* Burst mode enable */
342#define DMA_RETRIES 0x0505 /* Magic DMA retry number... */
343
344#define CYCLE_TIME 3 /* Default AT-bus cycle time: 500 ns
345 * (later adapter version: fix cycle time!)
346 */
347#define LINE_SPEED_BIT 0x80
348
349/* Macro definition for the wait function. */
350#define ONE_SECOND_TICKS 1000000
351#define HALF_SECOND (ONE_SECOND_TICKS / 2)
352#define ONE_SECOND (ONE_SECOND_TICKS)
353#define TWO_SECONDS (ONE_SECOND_TICKS * 2)
354#define THREE_SECONDS (ONE_SECOND_TICKS * 3)
355#define FOUR_SECONDS (ONE_SECOND_TICKS * 4)
356#define FIVE_SECONDS (ONE_SECOND_TICKS * 5)
357
358#define BUFFER_SIZE 2048 /* Buffers on Adapter */
359
360#pragma pack(1)
361typedef struct {
362 unsigned short Init_Options; /* Initialize with burst mode;
363 * LLC disabled. (MAC only)
364 */
365
366 /* Interrupt vectors the adapter places on attached system bus. */
367 u_int8_t CMD_Status_IV; /* Interrupt vector: command status. */
368 u_int8_t TX_IV; /* Interrupt vector: transmit. */
369 u_int8_t RX_IV; /* Interrupt vector: receive. */
370 u_int8_t Ring_Status_IV; /* Interrupt vector: ring status. */
371 u_int8_t SCB_Clear_IV; /* Interrupt vector: SCB clear. */
372 u_int8_t Adapter_CHK_IV; /* Interrupt vector: adapter check. */
373
374 u_int16_t RX_Burst_Size; /* Max. number of transfer cycles. */
375 u_int16_t TX_Burst_Size; /* During DMA burst; even value! */
376 u_int16_t DMA_Abort_Thrhld; /* Number of DMA retries. */
377
378 u_int32_t SCB_Addr; /* SCB address: even, word aligned, high-low */
379 u_int32_t SSB_Addr; /* SSB address: even, word aligned, high-low */
380} IPB, *IPB_Ptr;
381#pragma pack()
382
383/*
384 * OPEN Command Parameter List (OCPL) (can be reused, if the adapter has to
385 * be reopened)
386 */
387#define BUFFER_SIZE 2048 /* Buffers on Adapter. */
388#define TPL_SIZE 8+6*TX_FRAG_NUM /* Depending on fragments per TPL. */
389#define RPL_SIZE 14 /* (with TI firmware v2.26 handling
390 * up to nine fragments possible)
391 */
392#define TX_BUF_MIN 20 /* ??? (Stephan: calculation with */
393#define TX_BUF_MAX 40 /* BUFFER_SIZE and MAX_FRAME_SIZE) ???
394 */
395#define DISABLE_EARLY_TOKEN_RELEASE 0x1000
396
397/* OPEN Options (high-low) */
398#define WRAP_INTERFACE 0x0080 /* Inserting omitted for test
399 * purposes; transmit data appears
400 * as receive data. (useful for
401 * testing; change: CLOSE necessary)
402 */
403#define DISABLE_HARD_ERROR 0x0040 /* On HARD_ERROR & TRANSMIT_BEACON
404 * no RING.STATUS interrupt.
405 */
406#define DISABLE_SOFT_ERROR 0x0020 /* On SOFT_ERROR, no RING.STATUS
407 * interrupt.
408 */
409#define PASS_ADAPTER_MAC_FRAMES 0x0010 /* Passing unsupported MAC frames
410 * to system.
411 */
412#define PASS_ATTENTION_FRAMES 0x0008 /* All changed attention MAC frames are
413 * passed to the system.
414 */
415#define PAD_ROUTING_FIELD 0x0004 /* Routing field is padded to 18
416 * bytes.
417 */
418#define FRAME_HOLD 0x0002 /*Adapter waits for entire frame before
419 * initiating DMA transfer; otherwise:
420 * DMA transfer initiation if internal
421 * buffer filled.
422 */
423#define CONTENDER 0x0001 /* Adapter participates in the monitor
424 * contention process.
425 */
426#define PASS_BEACON_MAC_FRAMES 0x8000 /* Adapter passes beacon MAC frames
427 * to the system.
428 */
429#define EARLY_TOKEN_RELEASE 0x1000 /* Only valid in 16 Mbps operation;
430 * 0 = ETR. (no effect in 4 Mbps
431 * operation)
432 */
433#define COPY_ALL_MAC_FRAMES 0x0400 /* All MAC frames are copied to
434 * the system. (after OPEN: duplicate
435 * address test (DAT) MAC frame is
436 * first received frame copied to the
437 * system)
438 */
439#define COPY_ALL_NON_MAC_FRAMES 0x0200 /* All non MAC frames are copied to
440 * the system.
441 */
442#define PASS_FIRST_BUF_ONLY 0x0100 /* Passes only first internal buffer
443 * of each received frame; FrameSize
444 * of RPLs must contain internal
445 * BUFFER_SIZE bits for promiscuous mode.
446 */
447#define ENABLE_FULL_DUPLEX_SELECTION 0x2000
448 /* Enable the use of full-duplex
449 * settings with bits in byte 22 in
450 * ocpl. (new feature in firmware
451 * version 3.09)
452 */
453
454/* Full-duplex settings */
455#define OPEN_FULL_DUPLEX_OFF 0x0000
456#define OPEN_FULL_DUPLEX_ON 0x00c0
457#define OPEN_FULL_DUPLEX_AUTO 0x0080
458
459#define PROD_ID_SIZE 18 /* Length of product ID. */
460
461#define TX_FRAG_NUM 3 /* Number of fragments used in one TPL. */
462#define TX_MORE_FRAGMENTS 0x8000 /* Bit set in DataCount to indicate more
463 * fragments following.
464 */
465
466/* XXX is there some better way to do this? */
467#define ISA_MAX_ADDRESS 0x00ffffff
468#define PCI_MAX_ADDRESS 0xffffffff
469
470#pragma pack(1)
471typedef struct {
472 u_int16_t OPENOptions;
473 u_int8_t NodeAddr[6]; /* Adapter node address; use ROM
474 * address
475 */
476 u_int32_t GroupAddr; /* Multicast: high order
477 * bytes = 0xC000
478 */
479 u_int32_t FunctAddr; /* High order bytes = 0xC000 */
480 __be16 RxListSize; /* RPL size: 0 (=26), 14, 20 or
481 * 26 bytes read by the adapter.
482 * (Depending on the number of
483 * fragments/list)
484 */
485 __be16 TxListSize; /* TPL size */
486 __be16 BufSize; /* Is automatically rounded up to the
487 * nearest nK boundary.
488 */
489 u_int16_t FullDuplex;
490 u_int16_t Reserved;
491 u_int8_t TXBufMin; /* Number of adapter buffers reserved
492 * for transmission a minimum of 2
493 * buffers must be allocated.
494 */
495 u_int8_t TXBufMax; /* Maximum number of adapter buffers
496 * for transmit; a minimum of 2 buffers
497 * must be available for receive.
498 * Default: 6
499 */
500 u_int16_t ProdIDAddr[2];/* Pointer to product ID. */
501} OPB, *OPB_Ptr;
502#pragma pack()
503
504/*
505 * SCB: adapter commands enabled by the host system started by writing
506 * CMD_INTERRUPT_ADAPTER | CMD_EXECUTE (|SCB_REQUEST) to the SIFCMD IO
507 * register. (special case: | CMD_SYSTEM_IRQ for initialization)
508 */
509#pragma pack(1)
510typedef struct {
511 u_int16_t CMD; /* Command code */
512 u_int16_t Parm[2]; /* Pointer to Command Parameter Block */
513} SCB; /* System Command Block (32 bit physical address; big endian)*/
514#pragma pack()
515
516/*
517 * SSB: adapter command return status can be evaluated after COMMAND_STATUS
518 * adapter to system interrupt after reading SSB, the availability of the SSB
519 * has to be told the adapter by writing CMD_INTERRUPT_ADAPTER | CMD_SSB_CLEAR
520 * in the SIFCMD IO register.
521 */
522#pragma pack(1)
523typedef struct {
524 u_int16_t STS; /* Status code */
525 u_int16_t Parm[3]; /* Parameter or pointer to Status Parameter
526 * Block.
527 */
528} SSB; /* System Status Block (big endian - physical address) */
529#pragma pack()
530
531typedef struct {
532 unsigned short BurnedInAddrPtr; /* Pointer to adapter burned in
533 * address. (BIA)
534 */
535 unsigned short SoftwareLevelPtr;/* Pointer to software level data. */
536 unsigned short AdapterAddrPtr; /* Pointer to adapter addresses. */
537 unsigned short AdapterParmsPtr; /* Pointer to adapter parameters. */
538 unsigned short MACBufferPtr; /* Pointer to MAC buffer. (internal) */
539 unsigned short LLCCountersPtr; /* Pointer to LLC counters. */
540 unsigned short SpeedFlagPtr; /* Pointer to data rate flag.
541 * (4/16 Mbps)
542 */
543 unsigned short AdapterRAMPtr; /* Pointer to adapter RAM found. (KB) */
544} INTPTRS; /* Adapter internal pointers */
545
546#pragma pack(1)
547typedef struct {
548 u_int8_t Line_Error; /* Line error: code violation in
549 * frame or in a token, or FCS error.
550 */
551 u_int8_t Internal_Error; /* IBM specific. (Reserved_1) */
552 u_int8_t Burst_Error;
553 u_int8_t ARI_FCI_Error; /* ARI/FCI bit zero in AMP or
554 * SMP MAC frame.
555 */
556 u_int8_t AbortDelimeters; /* IBM specific. (Reserved_2) */
557 u_int8_t Reserved_3;
558 u_int8_t Lost_Frame_Error; /* Receive of end of transmitted
559 * frame failed.
560 */
561 u_int8_t Rx_Congest_Error; /* Adapter in repeat mode has not
562 * enough buffer space to copy incoming
563 * frame.
564 */
565 u_int8_t Frame_Copied_Error; /* ARI bit not zero in frame
566 * addressed to adapter.
567 */
568 u_int8_t Frequency_Error; /* IBM specific. (Reserved_4) */
569 u_int8_t Token_Error; /* (active only in monitor station) */
570 u_int8_t Reserved_5;
571 u_int8_t DMA_Bus_Error; /* DMA bus errors not exceeding the
572 * abort thresholds.
573 */
574 u_int8_t DMA_Parity_Error; /* DMA parity errors not exceeding
575 * the abort thresholds.
576 */
577} ERRORTAB; /* Adapter error counters */
578#pragma pack()
579
580
581/*--------------------- Send and Receive definitions -------------------*/
582#pragma pack(1)
583typedef struct {
584 __be16 DataCount; /* Value 0, even and odd values are
585 * permitted; value is unaltered most
586 * significant bit set: following
587 * fragments last fragment: most
588 * significant bit is not evaluated.
589 * (???)
590 */
591 __be32 DataAddr; /* Pointer to frame data fragment;
592 * even or odd.
593 */
594} Fragment;
595#pragma pack()
596
597#define MAX_FRAG_NUMBERS 9 /* Maximal number of fragments possible to use
598 * in one RPL/TPL. (depending on TI firmware
599 * version)
600 */
601
602/*
603 * AC (1), FC (1), Dst (6), Src (6), RIF (18), Data (4472) = 4504
604 * The packet size can be one of the follows: 548, 1502, 2084, 4504, 8176,
605 * 11439, 17832. Refer to TMS380 Second Generation Token Ring User's Guide
606 * Page 2-27.
607 */
608#define HEADER_SIZE (1 + 1 + 6 + 6)
609#define SRC_SIZE 18
610#define MIN_DATA_SIZE 516
611#define DEFAULT_DATA_SIZE 4472
612#define MAX_DATA_SIZE 17800
613
614#define DEFAULT_PACKET_SIZE (HEADER_SIZE + SRC_SIZE + DEFAULT_DATA_SIZE)
615#define MIN_PACKET_SIZE (HEADER_SIZE + SRC_SIZE + MIN_DATA_SIZE)
616#define MAX_PACKET_SIZE (HEADER_SIZE + SRC_SIZE + MAX_DATA_SIZE)
617
618/*
619 * Macros to deal with the frame status field.
620 */
621#define AC_NOT_RECOGNIZED 0x00
622#define GROUP_BIT 0x80
623#define GET_TRANSMIT_STATUS_HIGH_BYTE(Ts) ((unsigned char)((Ts) >> 8))
624#define GET_FRAME_STATUS_HIGH_AC(Fs) ((unsigned char)(((Fs) & 0xC0) >> 6))
625#define GET_FRAME_STATUS_LOW_AC(Fs) ((unsigned char)(((Fs) & 0x0C) >> 2))
626#define DIRECTED_FRAME(Context) (!((Context)->MData[2] & GROUP_BIT))
627
628
629/*--------------------- Send Functions ---------------------------------*/
630/* define TX_CSTAT _REQUEST (R) and _COMPLETE (C) values (high-low) */
631
632#define TX_VALID 0x0080 /* R: set via TRANSMIT.VALID interrupt.
633 * C: always reset to zero!
634 */
635#define TX_FRAME_COMPLETE 0x0040 /* R: must be reset to zero.
636 * C: set to one.
637 */
638#define TX_START_FRAME 0x0020 /* R: start of a frame: 1
639 * C: unchanged.
640 */
641#define TX_END_FRAME 0x0010 /* R: end of a frame: 1
642 * C: unchanged.
643 */
644#define TX_FRAME_IRQ 0x0008 /* R: request interrupt generation
645 * after transmission.
646 * C: unchanged.
647 */
648#define TX_ERROR 0x0004 /* R: reserved.
649 * C: set to one if Error occurred.
650 */
651#define TX_INTERFRAME_WAIT 0x0004
652#define TX_PASS_CRC 0x0002 /* R: set if CRC value is already
653 * calculated. (valid only in
654 * FRAME_START TPL)
655 * C: unchanged.
656 */
657#define TX_PASS_SRC_ADDR 0x0001 /* R: adapter uses explicit frame
658 * source address and does not overwrite
659 * with the adapter node address.
660 * (valid only in FRAME_START TPL)
661 *
662 * C: unchanged.
663 */
664#define TX_STRIP_FS 0xFF00 /* R: reserved.
665 * C: if no Transmission Error,
666 * field contains copy of FS byte after
667 * stripping of frame.
668 */
669
670/*
671 * Structure of Transmit Parameter Lists (TPLs) (only one frame every TPL,
672 * but possibly multiple TPLs for one frame) the length of the TPLs has to be
673 * initialized in the OPL. (OPEN parameter list)
674 */
675#define TPL_NUM 3 /* Number of Transmit Parameter Lists.
676 * !! MUST BE >= 3 !!
677 */
678
679#pragma pack(1)
680typedef struct s_TPL TPL;
681
682struct s_TPL { /* Transmit Parameter List (align on even word boundaries) */
683 __be32 NextTPLAddr; /* Pointer to next TPL in chain; if
684 * pointer is odd: this is the last
685 * TPL. Pointing to itself can cause
686 * problems!
687 */
688 volatile u_int16_t Status; /* Initialized by the adapter:
689 * CSTAT_REQUEST important: update least
690 * significant bit first! Set by the
691 * adapter: CSTAT_COMPLETE status.
692 */
693 __be16 FrameSize; /* Number of bytes to be transmitted
694 * as a frame including AC/FC,
695 * Destination, Source, Routing field
696 * not including CRC, FS, End Delimiter
697 * (valid only if START_FRAME bit in
698 * CSTAT nonzero) must not be zero in
699 * any list; maximum value: (BUFFER_SIZE
700 * - 8) * TX_BUF_MAX sum of DataCount
701 * values in FragmentList must equal
702 * Frame_Size value in START_FRAME TPL!
703 * frame data fragment list.
704 */
705
706 /* TPL/RPL size in OPEN parameter list depending on maximal
707 * numbers of fragments used in one parameter list.
708 */
709 Fragment FragList[TX_FRAG_NUM]; /* Maximum: nine frame fragments in one
710 * TPL actual version of firmware: 9
711 * fragments possible.
712 */
713#pragma pack()
714
715 /* Special proprietary data and precalculations */
716
717 TPL *NextTPLPtr; /* Pointer to next TPL in chain. */
718 unsigned char *MData;
719 struct sk_buff *Skb;
720 unsigned char TPLIndex;
721 volatile unsigned char BusyFlag;/* Flag: TPL busy? */
722 dma_addr_t DMABuff; /* DMA IO bus address from dma_map */
723};
724
725/* ---------------------Receive Functions-------------------------------*
726 * define RECEIVE_CSTAT_REQUEST (R) and RECEIVE_CSTAT_COMPLETE (C) values.
727 * (high-low)
728 */
729#define RX_VALID 0x0080 /* R: set; tell adapter with
730 * RECEIVE.VALID interrupt.
731 * C: reset to zero.
732 */
733#define RX_FRAME_COMPLETE 0x0040 /* R: must be reset to zero,
734 * C: set to one.
735 */
736#define RX_START_FRAME 0x0020 /* R: must be reset to zero.
737 * C: set to one on the list.
738 */
739#define RX_END_FRAME 0x0010 /* R: must be reset to zero.
740 * C: set to one on the list
741 * that ends the frame.
742 */
743#define RX_FRAME_IRQ 0x0008 /* R: request interrupt generation
744 * after receive.
745 * C: unchanged.
746 */
747#define RX_INTERFRAME_WAIT 0x0004 /* R: after receiving a frame:
748 * interrupt and wait for a
749 * RECEIVE.CONTINUE.
750 * C: unchanged.
751 */
752#define RX_PASS_CRC 0x0002 /* R: if set, the adapter includes
753 * the CRC in data passed. (last four
754 * bytes; valid only if FRAME_START is
755 * set)
756 * C: set, if CRC is included in
757 * received data.
758 */
759#define RX_PASS_SRC_ADDR 0x0001 /* R: adapter uses explicit frame
760 * source address and does not
761 * overwrite with the adapter node
762 * address. (valid only if FRAME_START
763 * is set)
764 * C: unchanged.
765 */
766#define RX_RECEIVE_FS 0xFC00 /* R: reserved; must be reset to zero.
767 * C: on lists with START_FRAME, field
768 * contains frame status field from
769 * received frame; otherwise cleared.
770 */
771#define RX_ADDR_MATCH 0x0300 /* R: reserved; must be reset to zero.
772 * C: address match code mask.
773 */
774#define RX_STATUS_MASK 0x00FF /* Mask for receive status bits. */
775
776#define RX_INTERN_ADDR_MATCH 0x0100 /* C: internally address match. */
777#define RX_EXTERN_ADDR_MATCH 0x0200 /* C: externally matched via
778 * XMATCH/XFAIL interface.
779 */
780#define RX_INTEXT_ADDR_MATCH 0x0300 /* C: internally and externally
781 * matched.
782 */
783#define RX_READY (RX_VALID | RX_FRAME_IRQ) /* Ready for receive. */
784
785/* Constants for Command Status Interrupt.
786 * COMMAND_REJECT status field bit functions (SSB.Parm[0])
787 */
788#define ILLEGAL_COMMAND 0x0080 /* Set if an unknown command
789 * is issued to the adapter
790 */
791#define ADDRESS_ERROR 0x0040 /* Set if any address field in
792 * the SCB is odd. (not word aligned)
793 */
794#define ADAPTER_OPEN 0x0020 /* Command issued illegal with
795 * open adapter.
796 */
797#define ADAPTER_CLOSE 0x0010 /* Command issued illegal with
798 * closed adapter.
799 */
800#define SAME_COMMAND 0x0008 /* Command issued with same command
801 * already executing.
802 */
803
804/* OPEN_COMPLETION values (SSB.Parm[0], MSB) */
805#define NODE_ADDR_ERROR 0x0040 /* Wrong address or BIA read
806 * zero address.
807 */
808#define LIST_SIZE_ERROR 0x0020 /* If List_Size value not in 0,
809 * 14, 20, 26.
810 */
811#define BUF_SIZE_ERROR 0x0010 /* Not enough available memory for
812 * two buffers.
813 */
814#define TX_BUF_COUNT_ERROR 0x0004 /* Remaining receive buffers less than
815 * two.
816 */
817#define OPEN_ERROR 0x0002 /* Error during ring insertion; more
818 * information in bits 8-15.
819 */
820
821/* Standard return codes */
822#define GOOD_COMPLETION 0x0080 /* =OPEN_SUCCESSFULL */
823#define INVALID_OPEN_OPTION 0x0001 /* OPEN options are not supported by
824 * the adapter.
825 */
826
827/* OPEN phases; details of OPEN_ERROR (SSB.Parm[0], LSB) */
828#define OPEN_PHASES_MASK 0xF000 /* Check only the bits 8-11. */
829#define LOBE_MEDIA_TEST 0x1000
830#define PHYSICAL_INSERTION 0x2000
831#define ADDRESS_VERIFICATION 0x3000
832#define PARTICIPATION_IN_RING_POLL 0x4000
833#define REQUEST_INITIALISATION 0x5000
834#define FULLDUPLEX_CHECK 0x6000
835
836/* OPEN error codes; details of OPEN_ERROR (SSB.Parm[0], LSB) */
837#define OPEN_ERROR_CODES_MASK 0x0F00 /* Check only the bits 12-15. */
838#define OPEN_FUNCTION_FAILURE 0x0100 /* Unable to transmit to itself or
839 * frames received before insertion.
840 */
841#define OPEN_SIGNAL_LOSS 0x0200 /* Signal loss condition detected at
842 * receiver.
843 */
844#define OPEN_TIMEOUT 0x0500 /* Insertion timer expired before
845 * logical insertion.
846 */
847#define OPEN_RING_FAILURE 0x0600 /* Unable to receive own ring purge
848 * MAC frames.
849 */
850#define OPEN_RING_BEACONING 0x0700 /* Beacon MAC frame received after
851 * ring insertion.
852 */
853#define OPEN_DUPLICATE_NODEADDR 0x0800 /* Other station in ring found
854 * with the same address.
855 */
856#define OPEN_REQUEST_INIT 0x0900 /* RPS present but does not respond. */
857#define OPEN_REMOVE_RECEIVED 0x0A00 /* Adapter received a remove adapter
858 * MAC frame.
859 */
860#define OPEN_FULLDUPLEX_SET 0x0D00 /* Got this with full duplex on when
861 * trying to connect to a normal ring.
862 */
863
864/* SET_BRIDGE_PARMS return codes: */
865#define BRIDGE_INVALID_MAX_LEN 0x4000 /* MAX_ROUTING_FIELD_LENGTH odd,
866 * less than 6 or > 30.
867 */
868#define BRIDGE_INVALID_SRC_RING 0x2000 /* SOURCE_RING number zero, too large
869 * or = TARGET_RING.
870 */
871#define BRIDGE_INVALID_TRG_RING 0x1000 /* TARGET_RING number zero, too large
872 * or = SOURCE_RING.
873 */
874#define BRIDGE_INVALID_BRDGE_NO 0x0800 /* BRIDGE_NUMBER too large. */
875#define BRIDGE_INVALID_OPTIONS 0x0400 /* Invalid bridge options. */
876#define BRIDGE_DIAGS_FAILED 0x0200 /* Diagnostics of TMS380SRA failed. */
877#define BRIDGE_NO_SRA 0x0100 /* The TMS380SRA does not exist in HW
878 * configuration.
879 */
880
881/*
882 * Bring Up Diagnostics error codes.
883 */
884#define BUD_INITIAL_ERROR 0x0
885#define BUD_CHECKSUM_ERROR 0x1
886#define BUD_ADAPTER_RAM_ERROR 0x2
887#define BUD_INSTRUCTION_ERROR 0x3
888#define BUD_CONTEXT_ERROR 0x4
889#define BUD_PROTOCOL_ERROR 0x5
890#define BUD_INTERFACE_ERROR 0x6
891
892/* BUD constants */
893#define BUD_MAX_RETRIES 3
894#define BUD_MAX_LOOPCNT 6
895#define BUD_TIMEOUT 3000
896
897/* Initialization constants */
898#define INIT_MAX_RETRIES 3 /* Maximum three retries. */
899#define INIT_MAX_LOOPCNT 22 /* Maximum loop counts. */
900
901/* RING STATUS field values (high/low) */
902#define SIGNAL_LOSS 0x0080 /* Loss of signal on the ring
903 * detected.
904 */
905#define HARD_ERROR 0x0040 /* Transmitting or receiving beacon
906 * frames.
907 */
908#define SOFT_ERROR 0x0020 /* Report error MAC frame
909 * transmitted.
910 */
911#define TRANSMIT_BEACON 0x0010 /* Transmitting beacon frames on the
912 * ring.
913 */
914#define LOBE_WIRE_FAULT 0x0008 /* Open or short circuit in the
915 * cable to concentrator; adapter
916 * closed.
917 */
918#define AUTO_REMOVAL_ERROR 0x0004 /* Lobe wrap test failed, deinserted;
919 * adapter closed.
920 */
921#define REMOVE_RECEIVED 0x0001 /* Received a remove ring station MAC
922 * MAC frame request; adapter closed.
923 */
924#define COUNTER_OVERFLOW 0x8000 /* Overflow of one of the adapters
925 * error counters; READ.ERROR.LOG.
926 */
927#define SINGLE_STATION 0x4000 /* Adapter is the only station on the
928 * ring.
929 */
930#define RING_RECOVERY 0x2000 /* Claim token MAC frames on the ring;
931 * reset after ring purge frame.
932 */
933
934#define ADAPTER_CLOSED (LOBE_WIRE_FAULT | AUTO_REMOVAL_ERROR |\
935 REMOVE_RECEIVED)
936
937/* Adapter_check_block.Status field bit assignments: */
938#define DIO_PARITY 0x8000 /* Adapter detects bad parity
939 * through direct I/O access.
940 */
941#define DMA_READ_ABORT 0x4000 /* Aborting DMA read operation
942 * from system Parm[0]: 0=timeout,
943 * 1=parity error, 2=bus error;
944 * Parm[1]: 32 bit pointer to host
945 * system address at failure.
946 */
947#define DMA_WRITE_ABORT 0x2000 /* Aborting DMA write operation
948 * to system. (parameters analogous to
949 * DMA_READ_ABORT)
950 */
951#define ILLEGAL_OP_CODE 0x1000 /* Illegal operation code in the
952 * the adapters firmware Parm[0]-2:
953 * communications processor registers
954 * R13-R15.
955 */
956#define PARITY_ERRORS 0x0800 /* Adapter detects internal bus
957 * parity error.
958 */
959#define RAM_DATA_ERROR 0x0080 /* Valid only during RAM testing;
960 * RAM data error Parm[0-1]: 32 bit
961 * pointer to RAM location.
962 */
963#define RAM_PARITY_ERROR 0x0040 /* Valid only during RAM testing;
964 * RAM parity error Parm[0-1]: 32 bit
965 * pointer to RAM location.
966 */
967#define RING_UNDERRUN 0x0020 /* Internal DMA underrun when
968 * transmitting onto ring.
969 */
970#define INVALID_IRQ 0x0008 /* Unrecognized interrupt generated
971 * internal to adapter Parm[0-2]:
972 * adapter register R13-R15.
973 */
974#define INVALID_ERROR_IRQ 0x0004 /* Unrecognized error interrupt
975 * generated Parm[0-2]: adapter register
976 * R13-R15.
977 */
978#define INVALID_XOP 0x0002 /* Unrecognized XOP request in
979 * communication processor Parm[0-2]:
980 * adapter register R13-R15.
981 */
982#define CHECKADDR 0x05E0 /* Adapter check status information
983 * address offset.
984 */
985#define ROM_PAGE_0 0x0000 /* Adapter ROM page 0. */
986
987/*
988 * RECEIVE.STATUS interrupt result SSB values: (high-low)
989 * (RECEIVE_COMPLETE field bit definitions in SSB.Parm[0])
990 */
991#define RX_COMPLETE 0x0080 /* SSB.Parm[0]; SSB.Parm[1]: 32
992 * bit pointer to last RPL.
993 */
994#define RX_SUSPENDED 0x0040 /* SSB.Parm[0]; SSB.Parm[1]: 32
995 * bit pointer to RPL with odd
996 * forward pointer.
997 */
998
999/* Valid receive CSTAT: */
1000#define RX_FRAME_CONTROL_BITS (RX_VALID | RX_START_FRAME | RX_END_FRAME | \
1001 RX_FRAME_COMPLETE)
1002#define VALID_SINGLE_BUFFER_FRAME (RX_START_FRAME | RX_END_FRAME | \
1003 RX_FRAME_COMPLETE)
1004
1005typedef enum SKB_STAT SKB_STAT;
1006enum SKB_STAT {
1007 SKB_UNAVAILABLE,
1008 SKB_DMA_DIRECT,
1009 SKB_DATA_COPY
1010};
1011
1012/* Receive Parameter List (RPL) The length of the RPLs has to be initialized
1013 * in the OPL. (OPEN parameter list)
1014 */
1015#define RPL_NUM 3
1016
1017#define RX_FRAG_NUM 1 /* Maximal number of used fragments in one RPL.
1018 * (up to firmware v2.24: 3, now: up to 9)
1019 */
1020
1021#pragma pack(1)
1022typedef struct s_RPL RPL;
1023struct s_RPL { /* Receive Parameter List */
1024 __be32 NextRPLAddr; /* Pointer to next RPL in chain
1025 * (normalized = physical 32 bit
1026 * address) if pointer is odd: this
1027 * is last RPL. Pointing to itself can
1028 * cause problems!
1029 */
1030 volatile u_int16_t Status; /* Set by creation of Receive Parameter
1031 * List RECEIVE_CSTAT_COMPLETE set by
1032 * adapter in lists that start or end
1033 * a frame.
1034 */
1035 volatile __be16 FrameSize; /* Number of bytes received as a
1036 * frame including AC/FC, Destination,
1037 * Source, Routing field not including
1038 * CRC, FS (Frame Status), End Delimiter
1039 * (valid only if START_FRAME bit in
1040 * CSTAT nonzero) must not be zero in
1041 * any list; maximum value: (BUFFER_SIZE
1042 * - 8) * TX_BUF_MAX sum of DataCount
1043 * values in FragmentList must equal
1044 * Frame_Size value in START_FRAME TPL!
1045 * frame data fragment list
1046 */
1047
1048 /* TPL/RPL size in OPEN parameter list depending on maximal numbers
1049 * of fragments used in one parameter list.
1050 */
1051 Fragment FragList[RX_FRAG_NUM]; /* Maximum: nine frame fragments in
1052 * one TPL. Actual version of firmware:
1053 * 9 fragments possible.
1054 */
1055#pragma pack()
1056
1057 /* Special proprietary data and precalculations. */
1058 RPL *NextRPLPtr; /* Logical pointer to next RPL in chain. */
1059 unsigned char *MData;
1060 struct sk_buff *Skb;
1061 SKB_STAT SkbStat;
1062 int RPLIndex;
1063 dma_addr_t DMABuff; /* DMA IO bus address from dma_map */
1064};
1065
1066/* Information that need to be kept for each board. */
1067typedef struct net_local {
1068#pragma pack(1)
1069 IPB ipb; /* Initialization Parameter Block. */
1070 SCB scb; /* System Command Block: system to adapter
1071 * communication.
1072 */
1073 SSB ssb; /* System Status Block: adapter to system
1074 * communication.
1075 */
1076 OPB ocpl; /* Open Options Parameter Block. */
1077
1078 ERRORTAB errorlogtable; /* Adapter statistic error counters.
1079 * (read from adapter memory)
1080 */
1081 unsigned char ProductID[PROD_ID_SIZE + 1]; /* Product ID */
1082#pragma pack()
1083
1084 TPL Tpl[TPL_NUM];
1085 TPL *TplFree;
1086 TPL *TplBusy;
1087 unsigned char LocalTxBuffers[TPL_NUM][DEFAULT_PACKET_SIZE];
1088
1089 RPL Rpl[RPL_NUM];
1090 RPL *RplHead;
1091 RPL *RplTail;
1092 unsigned char LocalRxBuffers[RPL_NUM][DEFAULT_PACKET_SIZE];
1093
1094 struct device *pdev;
1095 int DataRate;
1096 unsigned char ScbInUse;
1097 unsigned short CMDqueue;
1098
1099 unsigned long AdapterOpenFlag:1;
1100 unsigned long AdapterVirtOpenFlag:1;
1101 unsigned long OpenCommandIssued:1;
1102 unsigned long TransmitCommandActive:1;
1103 unsigned long TransmitHaltScheduled:1;
1104 unsigned long HaltInProgress:1;
1105 unsigned long LobeWireFaultLogged:1;
1106 unsigned long ReOpenInProgress:1;
1107 unsigned long Sleeping:1;
1108
1109 unsigned long LastOpenStatus;
1110 unsigned short CurrentRingStatus;
1111 unsigned long MaxPacketSize;
1112
1113 unsigned long StartTime;
1114 unsigned long LastSendTime;
1115
1116 struct tr_statistics MacStat; /* MAC statistics structure */
1117
1118 unsigned long dmalimit; /* the max DMA address (ie, ISA) */
1119 dma_addr_t dmabuffer; /* the DMA bus address corresponding to
1120 priv. Might be different from virt_to_bus()
1121 for architectures with IO MMU (Alpha) */
1122
1123 struct timer_list timer;
1124
1125 wait_queue_head_t wait_for_tok_int;
1126
1127 INTPTRS intptrs; /* Internal adapter pointer. Must be read
1128 * before OPEN command.
1129 */
1130 unsigned short (*setnselout)(struct net_device *);
1131 unsigned short (*sifreadb)(struct net_device *, unsigned short);
1132 void (*sifwriteb)(struct net_device *, unsigned short, unsigned short);
1133 unsigned short (*sifreadw)(struct net_device *, unsigned short);
1134 void (*sifwritew)(struct net_device *, unsigned short, unsigned short);
1135
1136 spinlock_t lock; /* SMP protection */
1137 void *tmspriv;
1138} NET_LOCAL;
1139
1140#endif /* __KERNEL__ */
1141#endif /* __LINUX_TMS380TR_H */
diff --git a/drivers/net/tokenring/tmspci.c b/drivers/net/tokenring/tmspci.c
deleted file mode 100644
index 90f3fa44a151..000000000000
--- a/drivers/net/tokenring/tmspci.c
+++ /dev/null
@@ -1,236 +0,0 @@
1/*
2 * tmspci.c: A generic network driver for TMS380-based PCI token ring cards.
3 *
4 * Written 1999 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - SysKonnect TR4/16(+) PCI (SK-4590)
11 * - SysKonnect TR4/16 PCI (SK-4591)
12 * - Compaq TR 4/16 PCI
13 * - Thomas-Conrad TC4048 4/16 PCI
14 * - 3Com 3C339 Token Link Velocity
15 *
16 * Maintainer(s):
17 * AF Adam Fritzler
18 *
19 * Modification History:
20 * 30-Dec-99 AF Split off from the tms380tr driver.
21 * 22-Jan-00 AF Updated to use indirect read/writes
22 * 23-Nov-00 JG New PCI API, cleanups
23 *
24 * TODO:
25 * 1. See if we can use MMIO instead of port accesses
26 *
27 */
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/errno.h>
32#include <linux/pci.h>
33#include <linux/init.h>
34#include <linux/netdevice.h>
35#include <linux/trdevice.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39
40#include "tms380tr.h"
41
42static char version[] __devinitdata =
43"tmspci.c: v1.02 23/11/2000 by Adam Fritzler\n";
44
45#define TMS_PCI_IO_EXTENT 32
46
47struct card_info {
48 unsigned char nselout[2]; /* NSELOUT vals for 4mb([0]) and 16mb([1]) */
49 char *name;
50};
51
52static struct card_info card_info_table[] = {
53 { {0x03, 0x01}, "Compaq 4/16 TR PCI"},
54 { {0x03, 0x01}, "SK NET TR 4/16 PCI"},
55 { {0x03, 0x01}, "Thomas-Conrad TC4048 PCI 4/16"},
56 { {0x03, 0x01}, "3Com Token Link Velocity"},
57};
58
59static DEFINE_PCI_DEVICE_TABLE(tmspci_pci_tbl) = {
60 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_TOKENRING, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
61 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_TR, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
62 { PCI_VENDOR_ID_TCONRAD, PCI_DEVICE_ID_TCONRAD_TOKENRING, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
63 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C339, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
64 { } /* Terminating entry */
65};
66MODULE_DEVICE_TABLE(pci, tmspci_pci_tbl);
67
68MODULE_LICENSE("GPL");
69
70static void tms_pci_read_eeprom(struct net_device *dev);
71static unsigned short tms_pci_setnselout_pins(struct net_device *dev);
72
73static unsigned short tms_pci_sifreadb(struct net_device *dev, unsigned short reg)
74{
75 return inb(dev->base_addr + reg);
76}
77
78static unsigned short tms_pci_sifreadw(struct net_device *dev, unsigned short reg)
79{
80 return inw(dev->base_addr + reg);
81}
82
83static void tms_pci_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
84{
85 outb(val, dev->base_addr + reg);
86}
87
88static void tms_pci_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
89{
90 outw(val, dev->base_addr + reg);
91}
92
93static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
94{
95 static int versionprinted;
96 struct net_device *dev;
97 struct net_local *tp;
98 int ret;
99 unsigned int pci_irq_line;
100 unsigned long pci_ioaddr;
101 struct card_info *cardinfo = &card_info_table[ent->driver_data];
102
103 if (versionprinted++ == 0)
104 printk("%s", version);
105
106 if (pci_enable_device(pdev))
107 return -EIO;
108
109 /* Remove I/O space marker in bit 0. */
110 pci_irq_line = pdev->irq;
111 pci_ioaddr = pci_resource_start (pdev, 0);
112
113 /* At this point we have found a valid card. */
114 dev = alloc_trdev(sizeof(struct net_local));
115 if (!dev)
116 return -ENOMEM;
117
118 if (!request_region(pci_ioaddr, TMS_PCI_IO_EXTENT, dev->name)) {
119 ret = -EBUSY;
120 goto err_out_trdev;
121 }
122
123 dev->base_addr = pci_ioaddr;
124 dev->irq = pci_irq_line;
125 dev->dma = 0;
126
127 dev_info(&pdev->dev, "%s\n", cardinfo->name);
128 dev_info(&pdev->dev, " IO: %#4lx IRQ: %d\n", dev->base_addr, dev->irq);
129
130 tms_pci_read_eeprom(dev);
131
132 dev_info(&pdev->dev, " Ring Station Address: %pM\n", dev->dev_addr);
133
134 ret = tmsdev_init(dev, &pdev->dev);
135 if (ret) {
136 dev_info(&pdev->dev, "unable to get memory for dev->priv.\n");
137 goto err_out_region;
138 }
139
140 tp = netdev_priv(dev);
141 tp->setnselout = tms_pci_setnselout_pins;
142
143 tp->sifreadb = tms_pci_sifreadb;
144 tp->sifreadw = tms_pci_sifreadw;
145 tp->sifwriteb = tms_pci_sifwriteb;
146 tp->sifwritew = tms_pci_sifwritew;
147
148 memcpy(tp->ProductID, cardinfo->name, PROD_ID_SIZE + 1);
149
150 tp->tmspriv = cardinfo;
151
152 dev->netdev_ops = &tms380tr_netdev_ops;
153
154 ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED,
155 dev->name, dev);
156 if (ret)
157 goto err_out_tmsdev;
158
159 pci_set_drvdata(pdev, dev);
160 SET_NETDEV_DEV(dev, &pdev->dev);
161
162 ret = register_netdev(dev);
163 if (ret)
164 goto err_out_irq;
165
166 return 0;
167
168err_out_irq:
169 free_irq(pdev->irq, dev);
170err_out_tmsdev:
171 pci_set_drvdata(pdev, NULL);
172 tmsdev_term(dev);
173err_out_region:
174 release_region(pci_ioaddr, TMS_PCI_IO_EXTENT);
175err_out_trdev:
176 free_netdev(dev);
177 return ret;
178}
179
180/*
181 * Reads MAC address from adapter RAM, which should've read it from
182 * the onboard ROM.
183 *
184 * Calling this on a board that does not support it can be a very
185 * dangerous thing. The Madge board, for instance, will lock your
186 * machine hard when this is called. Luckily, its supported in a
187 * separate driver. --ASF
188 */
189static void tms_pci_read_eeprom(struct net_device *dev)
190{
191 int i;
192
193 /* Address: 0000:0000 */
194 tms_pci_sifwritew(dev, 0, SIFADX);
195 tms_pci_sifwritew(dev, 0, SIFADR);
196
197 /* Read six byte MAC address data */
198 dev->addr_len = 6;
199 for(i = 0; i < 6; i++)
200 dev->dev_addr[i] = tms_pci_sifreadw(dev, SIFINC) >> 8;
201}
202
203static unsigned short tms_pci_setnselout_pins(struct net_device *dev)
204{
205 unsigned short val = 0;
206 struct net_local *tp = netdev_priv(dev);
207 struct card_info *cardinfo = tp->tmspriv;
208
209 if(tp->DataRate == SPEED_4)
210 val |= cardinfo->nselout[0]; /* Set 4Mbps */
211 else
212 val |= cardinfo->nselout[1]; /* Set 16Mbps */
213 return val;
214}
215
216static void __devexit tms_pci_detach (struct pci_dev *pdev)
217{
218 struct net_device *dev = pci_get_drvdata(pdev);
219
220 BUG_ON(!dev);
221 unregister_netdev(dev);
222 release_region(dev->base_addr, TMS_PCI_IO_EXTENT);
223 free_irq(dev->irq, dev);
224 tmsdev_term(dev);
225 free_netdev(dev);
226 pci_set_drvdata(pdev, NULL);
227}
228
229static struct pci_driver tms_pci_driver = {
230 .name = "tmspci",
231 .id_table = tmspci_pci_tbl,
232 .probe = tms_pci_attach,
233 .remove = __devexit_p(tms_pci_detach),
234};
235
236module_pci_driver(tms_pci_driver);
diff --git a/firmware/3com/3C359.bin.ihex b/firmware/3com/3C359.bin.ihex
deleted file mode 100644
index 781bac3b2a02..000000000000
--- a/firmware/3com/3C359.bin.ihex
+++ /dev/null
@@ -1,1573 +0,0 @@
1:10000000FE3A0000000000000000000000000000B8
2:1000100000000000000000000000000000000000E0
3:1000200000000000000000000000000000000000D0
4:1000300000000000000000000000000000000000C0
5:1000400000000000000030332F30322F39392031CA
6:10005000373A3133000000000000000000000000CB
7:1000600030313233343536373839414243444546EE
8:10007000000007FF0200FE9F0600007C48000070A1
9:100080008200FFFF8600FFFF8800FFFF9A00FFFF4E
10:10009000FFFF1100C000FFFFFFFF11223344556630
11:1000A00033434F4D20424142451140C000FFFFFF06
12:1000B000FF1122334455665374617274206F6620B9
13:1000C0004C4C43206672616D652E2020546F746124
14:1000D0006C20646174612073697A6520697320788B
15:1000E000787820202042414245E8D201833EF7340F
16:1000F000007521E84100833EF734007517E882005F
17:10010000833EF73400750DE8BF00833EF734007579
18:1001100003E84102C31EB800F08ED833F6B9008060
19:1001200033DBAD03D8E2FB1FB8000083FB00740390
20:10013000B82200A3F734C3FABA5600B0FFEE33C0BA
21:100140008EC033F6B9FF7F833EFF340074088D3EC6
22:100150003061D1EF2BCF268B1C26C704FFFF2683EF
23:100160003CFF751726C704000026833C00750C264B
24:10017000891C4646E2E0B80000EB03B82400A3F770
25:1001800034C3FAB4D79E733A753879367B349FB14D
26:1001900005D2EC732DB040D0E071277925D0E07303
27:1001A000217B1F32C0751B32E49E721674147812C4
28:1001B0007A109FD2EC720BD0E470077505B800007E
29:1001C000EB03B82600A3F734C3FABA5A0033C0EFE2
30:1001D000EFEFEFB000E656B000E654BA5200B801B7
31:1001E00001EFE8CA003C01757FE88300BA5200B80D
32:1001F0000202EFE8B9003C02756EE87A00BA5200DC
33:10020000B80404EFE8A8003C04755DE87100BA5238
34:1002100000B80808EFE897003C08754CE86800BA99
35:100220005200B81010EFE886003C10753BE85F0004
36:10023000BA5200B82020EFE875003C20752AE85635
37:1002400000BA5200B84040EFE864003C407519E83D
38:100250004D00BA5200B88080EFE853003C8075082A
39:10026000E84400B80000EB03B82800A3F734C3BA91
40:100270005A00B80080EFC3BA5A00B80180EFC3BA81
41:100280005A00B80280EFC3BA5A00B80380EFC3BA6D
42:100290005A00B80480EFC3BA5A00B80580EFC3BA59
43:1002A0005A00B80680EFC3BA5A00B80780EFC3B946
44:1002B000FFFFE458E4543C0075034975F7C3FA3274
45:1002C000C0E656E4563C007403E98200B0FFE656EF
46:1002D000E4563CFF7578BA5200B8FFFFEFED3CFFE3
47:1002E000756CB800FFEFED3C007563B0FFE654E4B9
48:1002F000543CFF755932C0E654E4543C00754FB08D
49:100300000FE650E450240F3C0F7543B000E650E474
50:1003100050240F3C0075378CC88EC0BE7000268BF1
51:1003200014268B5C02B80000EFED23C33D0000757E
52:100330001DB8FFFF23C3EF8BC8ED23C33BC1750E70
53:1003400083C60426833CFF75D5B80000EB03B82AAA
54:1003500000A3F734C3FA33C0BF0020B91700F3ABD2
55:10036000BF0030B91700F3ABBF0022B94000F3ABB8
56:10037000BF0032B94000F3ABFC1E8CC88ED833C02E
57:100380008EC0BE9200BF0020B91700F3A4BEA90022
58:10039000BF0022B94000F3A41FC706FB346400BAB3
59:1003A0000800B80F00EFE88201E89B01720DC70654
60:1003B000F7342C00C706F9340400C3BA0A0033C06E
61:1003C000EFE89801E8B501B81700BA9C00EFB80053
62:1003D00010BA9A00EFB81700A90100740140BA8C56
63:1003E00000EFB80018BA8600EFB80C00BA8200EF30
64:1003F000BA0200ED25F9FF0D0200EFBA060033C086
65:10040000EFBA0400B86000EFBA0000B81800EFBA05
66:100410008000B9FFFFEDA901007504E2F8EB3EBAD8
67:100420000A00EDA900407435A90020743033C0EFF4
68:1004300051B9C800E2FE591E061F268B0E023083FA
69:10044000F91775184949BE0220BF0630F3A61F23CD
70:10045000C9750AFF0EFB347412E94DFF1FB82C005A
71:10046000BB0000A3F734891EF934C3C706FB34640C
72:1004700000E8D300720DC706F7342C00C706F93424
73:100480000400C3E8D600E8F300B80300BA8200EF26
74:10049000B84080BA9800EFB80011BA9600EFB840A3
75:1004A00000A90100740140BA9200EFB80019BA8E99
76:1004B00000EFBA0200ED25F9FF0D0600EFBA0600C5
77:1004C00033C0EFBA0000B81800EFBA8000B9FFFFE0
78:1004D000EDA920007504E2F8EB43BA0A00EDA9008B
79:1004E00040743AA90020743533C0EF51B9C800E216
80:1004F000FE591E061F268B0E023283F940751D49D8
81:1005000049BE0222BF0632F3A61F23C9750FFF0E94
82:10051000FB347403E95AFFB80000EB0B1FB82C0042
83:10052000BB0200891EF934A3F734C3BA0200B80035
84:100530009CEFBA0000B80084EF33C0EFBA0A00EFB6
85:10054000BA0E0033C0EFC3BA0A00B9FFFFED2500B1
86:10055000603D00607404E2F5F8C3F9C3B000E656EC
87:10056000B800FFBA5200EFB9FFFFBA5800ED25EF0F
88:10057000007408BA5A0033C0EFE2EFC3BA8000ED4E
89:10058000BA8400EFBA8000EDC30000000000000054
90:10059000C606EC341533C08ED88EC01E8CC8BE4043
91:1005A00054BF60FE8ED8B91000F3A41FC706803672
92:1005B0001035C7068C3630358D063835A33035A357
93:1005C0003235053301A33435C70636355001C70629
94:1005D000843680FEC7068836C0FEC606C2FEFFC649
95:1005E00006933680C606923600C60680FE80C70691
96:1005F00082FE5450C70684FE2B4DE5CEA90200753D
97:1006000008C60681FE23E90500C60681FE22A1F781
98:1006100034A386FEB8483486E0A388FE8D064E34A7
99:1006200086E0A38AFEB8583486E0A38CFEB89C34DA
100:1006300086E0A38EFE8D06200386E0A390FE33C0E5
101:10064000BA7200EF33C0BA7400EFBA7600EFB88028
102:10065000FE86E0BA7200EFE8BF07BA0C01B840406E
103:10066000EFEDBA6A00B80300C1E0080D0300EFB96E
104:100670000A00E89400BA6A00B80300C1E008EFA1DC
105:100680003234A3A233C706A63304008D06A033C1BB
106:10069000E804CD39C7069036FFFFE9E300630D6635
107:1006A0000D660D8A0DE60E75122E0F030F500F60AA
108:1006B0000D600D600DED0FE912600D600D600D60B5
109:1006C0000D600D2210600D600D600D600DFE10605C
110:1006D0000D600D600D600D600D600DAF0F321037B5
111:1006E0000D600D600D600D600D600D600D600D60A2
112:1006F0000D600D600D600D600D600D600D600D6092
113:100700000D640E000F9509600A49BBFFFFBA6A002D
114:10071000EDA900207438803E80FE127531E84A0051
115:10072000A13234A3A233C706A63304008D06A0333A
116:10073000C1E804CD39E82200C706F3344600C706F5
117:10074000F534FFFFC7069036FFFF58E932004B83B0
118:10075000FB0075B983F90075B0C352BA6A00B803DB
119:1007600000C1E0080D0300EF5AC352BA6A00B80393
120:1007700000C1E008EF5AC3000000000000000000C4
121:10078000688007A19036CD358B3624022EFFA43524
122:100790000AFA8A2694368826E834C606943600FB80
123:1007A00022E47501C3F6C420747DF6C40874058084
124:1007B0000E9236048026E834D7C41E8436268B3742
125:1007C00081E6FF0083FE207605B001E9280053068C
126:1007D000D1E62EFF949D06075B268847023CFF74F6
127:1007E000073CFE7511E93B00F6069236087534F6B3
128:1007F00006923604742D80269236F3803E9536009C
129:10080000752126803F057513C60695360026807F24
130:1008100006007407268B4704A29536BA0C01B8402F
131:1008200040EFED8A26E834F6C4107503E95B00F664
132:10083000C4047405800E9236018026E834EBC43E71
133:100840008836268B3583E67F83FE12720826C645DE
134:100850000201E9240083C620D1E62EFF949D06C440
135:100860003E8836268845023CFF750EF60692360114
136:100870007414F606923602750D80269236FCBA0C78
137:1008800001B82020EFED8A26E834F6C408742280EF
138:1008900026E834F7800E923604F606923608741174
139:1008A00080269236F3BA0C01B84040EFED8A26E874
140:1008B00034F6C40474228026E834FB800E9236019C
141:1008C000F606923602751180269236FEBA0C01B8F1
142:1008D0002020EFED8A26E834F6C40174678026E80C
143:1008E00034FE803EE8FF007439803EE8FF04743235
144:1008F000803EE8FF017521E580A90007740ABA9ED1
145:1009000000B80002EFE9EFFFC606E8FF03BA0C01EA
146:10091000B80808EFEDE92800803EE8FF037406E917
147:100920001E00E90000BA1001B80202EFEDE5000D6B
148:100930001800E700E5820D0200E782C606E8FF0422
149:100940008A26E834F6C402740D8026E834FD802639
150:100950009236BFE84F0BFAA0E83408069436C60674
151:10096000E83400FBC3E8E70FC41E84362EFF1601EF
152:100970000726884702E97EFEE82D10C41E84362E25
153:10098000FF16030726884702E96BFE8E0626022E15
154:10099000FF160707C3C3833EF53400740FFF0EF341
155:1009A000347509E8C4FDC706F5340000F606933631
156:1009B000207430A1C2343B06E934A3E934742480A6
157:1009C0003E953600751DF706E63420007412A92006
158:1009D00000740D8326C234DF8326E934DFE9030087
159:1009E000E8DD09BA0601ED8BD081E200C0C1EA0E54
160:1009F00003167434C1E002110672347304FF0674E6
161:100A000034BA0201ED8BD081E200C0C1EA0E0316B8
162:100A10007034C1E00211066E347304FF067034C7EF
163:100A200006A6330400C706AA3300008D06A033C112
164:100A3000E804CD39C39509950965097809950995A3
165:100A4000099107950996098B0995099509950995C5
166:100A500009950995098BC08BC08BC08BC08BC0904A
167:100A6000F6069336207503E9CC008CC0408EC02674
168:100A70008B0E060086E926890E06008CC2C1E204B0
169:100A8000BE0E0026A10400D0E024C08AE0C0EC0421
170:100A90000AC426A2050026A10800A900C07403E923
171:100AA0009E0026F6061000807503E90A0026A016AF
172:100AB00000241F32E403F0803EEC3406725C803E7A
173:100AC00095360075668BFA33DB8EC326891D268822
174:100AD0005D045150C41E8C36B90F0033C0E82109A3
175:100AE00058590BDB7434FE0EE63A26C6078126C63B
176:100AF00047010026C64702FF26C747040000268993
177:100B00004F0A86F2268957062689770826C647099E
178:100B10000026C6470C02E88C09C3FF06EC338CC0E4
179:100B2000488EC0FAE89710FBE9EBFF8CC0488EC0F6
180:100B3000FAE88A10FBC38CC08EC0FAE88010FBC3B1
181:100B4000803E9536007503E9C200BF080026F60610
182:100B5000100080750503FEE90C0026A01600241F76
183:100B600032E403F003FEA095363C007503E99C00D7
184:100B70003C01740B3C0274143C03741DE98D00C6E7
185:100B800006963601E83C017227E98000C6069636D3
186:100B900002E88300721AE97300C606963601E8225D
187:100BA00001720DC606963602E86C007203E95C001D
188:100BB000530650C41E8C36B90B0033C0E8420858A7
189:100BC00026C6078226C64702FF8D06E0FE86C4269B
190:100BD000894706A0963626884708E8C808075B8339
191:100BE00026AD36FEA1AD36E704BA1001B88080EF1D
192:100BF000EDBA1001B80202EFED52BAE000B84110B0
193:100C0000EF5AB89C03CD39C6069536008CC0488E85
194:100C1000C0FAE8A90FFBC31E061F0633C08EC08BA7
195:100C2000F08D3E20F351B10A26837D0C01752A57C1
196:100C300026837D0E007406E82F00E90300E86607AE
197:100C40005F731633C08ED8268B4D128D75208D3E66
198:100C5000E0FEF3A459071FF9C3FEC9740781C7203A
199:100C600001E9C4FF59071FF8C35150535652573377
200:100C7000DB268A5D0E268B4D128D7D205A87D72666
201:100C80008A451487D74232FF80FF087508FECB22C1
202:100C9000DB75EA33DB23DB7406FEC7D0C8730C5068
203:100CA000268A053804587403E90A0049464723C9CF
204:100CB000740AE9D3FF5A5E5B5859F8C35A5E5B5811
205:100CC00059F9C31E061F0633C08EC086CD2BCE8BAE
206:100CD000F78BC133C9803CFF741680F90673093263
207:100CE000C94648742EE9EDFF3D6000730CE923000E
208:100CF000FEC14648741DE9DCFFB810008D3E183473
209:100D000032EDB106F3A67403E908004823C0740766
210:100D1000E9E9FF071FF8C38D36183433C08ED88D2C
211:100D20003EE0FEB81000B9060056F3A45E483D0050
212:100D30000075F3071FF9C3FF06E433C606EB340062
213:100D4000268B450686E0C1E80448068EC0FE06E60E
214:100D50003AFAE8690EFB07B0FFC30000000000008C
215:100D6000B001C3B000C3F6069336207503B004C3C8
216:100D70008B0E973681E18030268B4704257FCF0B81
217:100D8000C1A39736A3E634B000C3F60693362074A9
218:100D900003B003C3268B4708A39736A3E634268AFD
219:100DA0004720A2FD343C017506C706A13600002687
220:100DB0008A4721A2FE34268B470AA31834A358344D
221:100DC000268B470CA31A34A35A34268B470EA31C38
222:100DD00034A35C34C6062A34C0268B4714257FFF13
223:100DE00009062C34268B471625FFFE25FFFC090635
224:100DF0002E34C6060034C0268B4710A30234268B3F
225:100E00004712A304340653E8840A5B073D000075CB
226:100E100007800E923608B0FEC3B90001A1AC33338F
227:100E2000D2F7F9A3AE33914933D2F7E905003BA3DA
228:100E30004634BF003B893E4434BA6800B8E0E0EF76
229:100E4000A1AE33E762A1AE33BA0801EFA14434E7A3
230:100E500064A14434BA0A01EFB800012D04000D006A
231:100E600010E792C33D0000740A26894707E8833AD9
232:100E7000B007C3A1AE332689472BA1443426894746
233:100E80002DA146342689472F800E933620A188361F
234:100E900086E026894708A1843686E02689470AA18C
235:100EA000803686E02689470CB860FE86E0268947B2
236:100EB0000EA0A136268847108B36883626C64402F7
237:100EC000FFE59EA90008740CBA8400ED0D0800EF40
238:100ED000BA8E00EFE50225F9FFE702BA1001B80269
239:100EE00002EFEDB000C3F6069336207503B001C3E0
240:100EF000802693369FE88D0A800E923608B0FEC396
241:100F0000B000C3F6069336207503B004C3C6062AA4
242:100F100034C0268B4706257FFFA32C34268B470839
243:100F200025FFFE25FFFCA32E34CD52B000C3F606EC
244:100F30009336207503B004C3C6060034C0268B4721
245:100F400006A30234268B4708A30434CD52B000C355
246:100F5000F6069336207503B004C3578D7F0651B94A
247:100F6000070033C0F3AB598D7F06A17A34030639ED
248:100F700037268805A1953726884502A180340306C7
249:100F8000763426884507A1C63426884509A1D8337A
250:100F90002688450A33C0A37A34A33937A39537A3EB
251:100FA0008034A37634A3C634A3D8335FB000C3F62D
252:100FB000069336207503B004C3268B4F0483F906CD
253:100FC000741283F904740D83F900740883F90274B0
254:100FD00003B001C3890EE83A8326AB36F9090EAB9C
255:100FE00036E50225F9FF0BC1E702B000C3F6069310
256:100FF00036207503B004C3268B4F0480F9FF7408B4
257:1010000080F9007410B001C3830EAD3602A1AD3675
258:10101000E704E90A008326AD36FDA1AD36E704B04A
259:1010200000C3F6069336207503B004C3E8D504B0B8
260:1010300000C3F6069336807503B001C326837F068E
261:10104000057503E99D00268B5704268B47082681EA
262:101050007F0600807508ED2689470AE99D002683F2
263:101060007F06017504EFE9920026817F06018075F5
264:1010700009EFED2689470AE9810026837F0602757C
265:101080000726214704E9730026817F060280750C3C
266:1010900026214704ED2689470AE95F0026837F065B
267:1010A00003750726094704E9510026817F0603805E
268:1010B000750C26094704ED2689470AE93D00268379
269:1010C0007F0604750726314704E92F0026817F0635
270:1010D0000480750C26314704ED2689470AE91B0078
271:1010E000B001C3FA53268B4F080BC9740C8D1EE058
272:1010F000FEE852FF83C308E2F85BFBB000C3F606CC
273:10110000933680750AF6069336207503B001C38DB9
274:101110003EE0FEE500268905E50226894502A1ADEF
275:101120003626894504E50626894506E508268945CB
276:1011300008E50A2689450AE50E2689450CE5482674
277:1011400089450EE54A26894510E54C26894512A1B8
278:10115000B73626894514E55026894516E552268975
279:101160004518E5542689451AE5562689451CE55853
280:101170002689451EE56226894520E56426894522A3
281:10118000E56626894524E56826894526E56A268997
282:101190004528E56C2689452AE5702689452CE572A7
283:1011A0002689452EE57426894530E576268945321F
284:1011B000E57C26894534E57E26894536E580268905
285:1011C0004538E5822689453AE5862689453CE58805
286:1011D0002689453EE59A26894540E59E2689454271
287:1011E000E5CC26894544E5CE26894546E5D02689C5
288:1011F0004548E5D22689454ABA0001ED1106663414
289:101200007304FF0668342689454CBA0201EDC1E03B
290:101210000211066E347304FF0670342689454EBAF7
291:101220000401ED11066A347304FF066C3426894507
292:1012300050BA0601EDC1E002110672347304FF06D4
293:10124000743426894552BA0801ED26894554BA0AF4
294:1012500001ED26894556BA0C01ED26894558BA0E8E
295:1012600001ED01067A342689455EBA1001ED268922
296:10127000455CB000C3F6069336807407F6069336D5
297:10128000207503B001C326807F06007530803E952F
298:1012900036007452C6069536008326AD36FEA1ADE3
299:1012A00036E704BA1001B88080EFEDBA1001B80239
300:1012B00002EFEDBAE000B80010EFB000C3268B4794
301:1012C000043D000074203D0300771BBA1001B802F2
302:1012D00000EFBAE000B80110EF830EAD3601A1AD0A
303:1012E00036E704B000C3B006C3F606933680750334
304:1012F000B001C326837F0401740A26837F0402742D
305:1013000019B006C326837F060C77F626837F0A6012
306:1013100077EFE81000720BB046C3E84E007203B0DE
307:1013200046C3B000C351B10A8B3E20F326837D0C27
308:10133000027503E90E00FEC9740781C72001E9EBBD
309:10134000FF59F8C3578D7D0E8D7706B91200F3A4AF
310:101350008D7D208D36E0FE268B4D12F3A4FF060115
311:10136000355F26C7450C010059F9C351B10A8D3EBE
312:1013700020F38D36E0FE26837D0C01751B57E82592
313:10138000005F731433C0B92001F3AA26C7450C02CD
314:1013900000FF0E013559F9C3FEC9740781C720014A
315:1013A000E9D3FF59F8C351268B4D128D7D20F3A64A
316:1013B000740359F8C359F9C300000000000000008D
317:1013C000803EEC34067233FF06F03350C41E8C3678
318:1013D000B90F0033C0E82900588126C234DF7F816D
319:1013E00026E934DF7F0BDB741126C6078426C64747
320:1013F00002FF26894706E8AC00C3FF06EA33E9F599
321:10140000FF57268B3F03F9263B7F027416263B7F4E
322:10141000047C2A3D000075138D7F0803F9263B7F6D
323:10142000027C14FF06DE3333DB5FC3268B7F02268C
324:10143000893F03F9E9060026893F26290F26C705BB
325:10144000FFFF26873F26890D8D5D02508BFB83E9C8
326:101450000233C0F3AA58FE0EEC345FC38B7C023B10
327:101460003C742F833DFF750B8D7C08897C02833D86
328:10147000FF741E8A45023C81750C803EEB3400747B
329:101480000533C0E90B008B0D014C028D750283E919
330:1014900002C3803EEC3406720533C0E9F3FFFF0659
331:1014A000EE33E9BEFFF6069236407401C35756513B
332:1014B000528B368C36E8A4FF7503E91A00E91C004C
333:1014C000FE06EC34C43E8036F3A4800E923640BA59
334:1014D0000C01B88080EFED5A595E5FC3FF06E03320
335:1014E000803C81750CFF06E233C606EB3401E9CF80
336:1014F000FF803C847507FF06E633E9C3FFFF06E87B
337:1015000033E9BCFF8D3EE0FEA17234C706723400A1
338:10151000008905A17434C70674340000894502BAF5
339:101520000401ED894504C745060000A16E34C706D5
340:101530006E340000894508A17034C706703400007D
341:1015400089450ABA0001ED89450CC7450E000032F5
342:10155000E4BA0E01EC894510A17E34C7067E340042
343:1015600000894512A18C34C7068C340000894514CB
344:10157000A18A34C7068A340000894516A17C34C785
345:10158000067C340000894518A18834C706883400D9
346:101590000089451AA1CA33C706CA33000089451C11
347:1015A000A17834C7067834000089451EA1C634C727
348:1015B00006C6340000894520C3000000000000007A
349:1015C000FA33C08ED88EC0B8A001C1E8048ED08D89
350:1015D000268000E80001E810EB8B1EF7348B16F92B
351:1015E000348B36FF3433C0B9EFFF8D3E14002BCF60
352:1015F0002BCED1E9F3AB891EF7348916F93483FE7B
353:1016000000740CB9EFFFBF80FE2BCFD1E9F3ABB96B
354:10161000FFFF81E9003B83FE007403E91B00511EBC
355:10162000B800E08ED833F68D3E00D8B9000CF3A593
356:101630001F59BEFFFF81EE00D82BCE81E100FF894C
357:101640000EAC338D062002C1E804A332348ED036AE
358:10165000C7061E00801836C7062200FF7F36C70661
359:101660000A00FFFF36C7061C0080008D06A002C1DD
360:10167000E804A330348ED036C7061E00502836C783
361:10168000060A00FFFF36C7061C008000B8A001C193
362:10169000E804A33434A3F2338ED08D268000B80042
363:1016A00090E7028D3E70018BC7C1E804B903008941
364:1016B000450E894502C705FFFF83C710050100E2FB
365:1016C000EEE85B01E5CEA3B536E82100E84501A1CF
366:1016D00032348CCBCD370E58A900F0740733F6891D
367:1016E00036FF34C38D3630618936FF34C333C08B47
368:1016F000D08BF2B968002E80BCAC17807501EF83E7
369:10170000C20246E2F1B80200E750B95A0033FFC7FF
370:101710000565188C4D0283C704E2F433C08EC08C7B
371:10172000C88ED88D3E80008D369C17B90800E837EA
372:10173000008D3620218D3EC000B90D00E829008DB6
373:101740003E4001B90A00E81F00E84B0E33C08ED8B6
374:10175000C7064E376F17E748E74CB8409CE74AE5A5
375:101760004890B80070E748C3A583C702E2FAC3E512
376:101770004CC35051565752061E33C08ED8E558D12F
377:10178000E073118BF0D1E633C08ED88BB480008328
378:10179000C60BFFE61F075A5F5E5958CF581CE41C62
379:1017A0006C1C8E1AC01F401A441C6518808080FF74
380:1017B00080030280FFFFFFFFFFFFFFFFFFFFFFFF30
381:1017C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF29
382:1017D0008003034380800280420302FF0301030170
383:1017E00001030203FFFFFFFFFFFFFFFF02030103EF
384:1017F00003FF0101FF01FF0101030303FFFFFFFFDF
385:10180000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE8
386:10181000FFFFFF02B80F00E784B80FF8E782C3B9F3
387:101820000800890EE63A8D0620038BD0C1E804A398
388:1018300090018BC28BD8C1E8048EC005610026A33D
389:101840000000A1303426A3020083C314D1EB268903
390:101850001E080081C21006E2D926C7060000FFFF5D
391:101860008C069201C35051565752061E33C08ED873
392:10187000E75AFF06BE33BAD200EDCF0000000000E9
393:101880008CCBA13034CD37E906EDB83200C3E88CFB
394:1018900001FE06E234E8210175F0E8530E810EAF37
395:1018A0003600C0C706AD366000F706E63480007526
396:1018B0001AF706E63400087409C706AB360B00E9D0
397:1018C0000F00C706AB360300E90600C706AB3611AA
398:1018D0009CC706A9361800F706E6348000750DF798
399:1018E00006B53602007405830EA93620A1A936E795
400:1018F00000A1AB36E702F706E6348000742EE8F26A
401:101900002F33C00D4100E756A1B1360D0010E70896
402:10191000A1B336E70AA1AF36E706B84000E74E3379
403:10192000C0E70EC70626020000E92300C7064E37AF
404:101930003F208E06303426F7060A00008074072602
405:10194000810E08000080C606E03401B80000C3FE26
406:1019500006E134C606E03400A126020BC07401C3C0
407:10196000E80400B80000C3A1A936E7008B1EAB361F
408:1019700083E306E50225F9FF0BC30D1000E702A182
409:10198000AD36E704C3B80A00E784FE06E534C606B0
410:10199000E334018E06303426F7060A00004074074F
411:1019A00026810E08000040C3C7064E376F17FE069B
412:1019B000E434C606E33400C3C3F606183480750D5C
413:1019C000A118340B061A340B061C347501C3A12E62
414:1019D0003425FFFE8B16E73681E200010BC2A32EF1
415:1019E000348D161000BF0000B908008B850034EF5D
416:1019F00083C2108B850234EF83C2108B850434EFD1
417:101A000083C2E283C7064975E2B800008EC0BE00FB
418:101A100034BFB936B91800F3A5B80000C333C08E7F
419:101A2000C08D3EB033B90800F3AB8D3E3E34B903F0
420:101A300000F3ABC300000000000000000000000045
421:101A40005051565752061E33C08ED8E75AFF06BA79
422:101A500033E5560D2000E756BA7A00ED0826943695
423:101A600033C0B10832ED068EC08D3EE0FFF3AA8E82
424:101A700006323426810E0800000207E55625DFFFF6
425:101A8000E756E9F8FC00BD1B101BD91AF31A505198
426:101A9000565752061E33C08ED8E75AFF06B6335348
427:101AA0000651E580A3B4338BD88BC8251000A3ED75
428:101AB000340BC07414FF068034803EFE340074037F
429:101AC000E90600B88000E89D0483E303D1E32EFF1C
430:101AD00097861A59075BE9A4FCBA20008E063C34AD
431:101AE000833E3C34007503E9F000C7063C34000037
432:101AF000E92A00BA10008E063A34833E3A34007563
433:101B000003E9D5FFC7063A340000E81000E9C9FF31
434:101B1000BA10008E063A34C7063A34000026A114E3
435:101B20000026A30C0026A1160026A30E0026C6063A
436:101B30000A0000C1EA0223D1741CBA200026C7069D
437:101B40000E00EA05260B160C002689160C00FF066F
438:101B50008634FF06DC3326A10C00A9003774162654
439:101B6000C6060A0002A900307404FF067A34FF0694
440:101B7000DA33E94900C0EC0783168A340024073CB5
441:101B8000077504FF068C34FF067E34A130348CC305
442:101B90008EC08EDB26830E0800408CD82687061662
443:101BA0000026833E1400FF740A8EC0268C1E00009F
444:101BB000E90500268C1E140033C08ED8C3C38CC028
445:101BC000870692013DFFFF740D8ED88C060000330E
446:101BD000C08ED8E904008C069001E80100C306839A
447:101BE0003E9001FF7429833E3A34007511BA860095
448:101BF000E81E008C063A34833E9001FF7411833E48
449:101C00003C3400750ABA8800E806008C063C3407AC
450:101C1000C3A190018EC026A10800EF26A1000026D6
451:101C2000C7060000FFFFA390013DFFFF7503A392CD
452:101C300001833EED3400740BB81000E784C706ED55
453:101C4000340000C35051565752061E33C08ED8E799
454:101C50005AFF06BC33E925FB5051565752061E3336
455:101C6000C08ED8E75AFF06B033E911FB50515657E2
456:101C700052061E33C08ED8E75AFF06B43306FF065D
457:101C80007634803EFE3400740407E9F0FAB8800030
458:101C9000E8D30207E9E6FA000000000000000000B7
459:101CA000C61D081D911E5D1E731E891E911EA81D56
460:101CB000911E911EAF1EAF1E151D151D911E991F61
461:101CC000000000000000000000040000000200000E
462:101CD00000010010000100400000000000010000B1
463:101CE00007E999FA5051565752061E33C08ED8E76D
464:101CF0005AFF06B2330668F61CE506A3B2338BF032
465:101D000083E61E2EFFA4A01CE50CA980007406E843
466:101D1000A401E506C353E50C8BD8A9010074148314
467:101D20003EE03A00740D8E063834E8BF06C706E080
468:101D30003A0000E5000D1800E700E5020D1100E78C
469:101D4000028BC35BA901007401C38BD0B80008E704
470:101D5000848BC28E06383426A30C008BD0C1E003DE
471:101D60008316883400FF067C3426833E06000A75FD
472:101D7000218BC22540183D4000740C3D00107512A7
473:101D800026FE0E0A00740BF706EF3420007503E9F7
474:101D90005A068CC0268E06020026830E08002026D6
475:101DA000A3120026A31000C3FF06C433E50CA9014B
476:101DB000007501C3A9F0077401C3FF06D433E50021
477:101DC0000D1800E700C3FF06CA33803EA036087531
478:101DD000148E06303426F7060A00000874072681A0
479:101DE0000E08000008E58225FDFFE782E50C50E5BE
480:101DF00080250007A3E43AE58C250080A3E23A5849
481:101E0000A902007525833EE23A00751E833EE43A3E
482:101E1000007517E5080D000425FF04E708E86A01CE
483:101E2000E5820D0200E782E92100E81A06803EE81B
484:101E3000FF00740A803EE8FF047403E90D00C60643
485:101E4000E8FF01BA0C01B80808EFED803E9F3606A6
486:101E50007505830E993640B80001E90901FF06CCEB
487:101E6000338126AF36FFF7A1AF36E706FF06C6344B
488:101E7000E91E00FF06CE33FF0695378126AF36FFF9
489:101E8000EFA1AF36E706E90800FF06D033FF067A78
490:101E900034FF06D233D1E68E0630342E8B84C01C3C
491:101EA00026090608002E8B84C21C09066637C3E586
492:101EB0000CA98000745650E8F00058A9000175077D
493:101EC000FF06C633E90800FF067834FF06C833E58D
494:101ED0008225FDFFE782E86E05BA1001ED803EE83D
495:101EE000FF00740A803EE8FF047403E91D00C60683
496:101EF000E8FF01BA0C01B80808EFEDE90D00C606CD
497:101F0000E8FF03BA0C01B80808EFEDC3A90100749B
498:101F10001CE82C00833EE03A00740F068E0638342D
499:101F2000E8C904C706E03A000007E95D008BD08EDF
500:101F300006383426A30C00E8060068691DE94A004B
501:101F4000A90004740AB80004FF06D833E91700A9F1
502:101F50000001740AFF063937B80001E90800A9102A
503:101F600000B81000741D090666378CC08E06303428
504:101F700026F7060A000001740726810E08000001FA
505:101F80008EC0C3FF06C233E9F8FFE5000D1800E775
506:101F900000E5020D1100E702C358E943FDE5080D15
507:101FA000000425FF04E708E9E0FFE50EA900087535
508:101FB00001C3E9F5FF000000000000000000000080
509:101FC0005051565752061E33C08ED8E75AFF06B8F6
510:101FD00033E548065357FF164E375F5B833E80015B
511:101FE000FF74588E06800126FF0E0800754D26A14D
512:101FF0000000A3800126C7060000FFFF8CC0268ECC
513:1020000006020026810E080080008BD02687061A63
514:102010000026833E1800FF740A8EC0268916000031
515:10202000E905002689161800833E8001FF740C8E96
516:1020300006800126833E08000074B307E93EF7E5F9
517:102040004C90E502A90020740D25FFDF0D0100E78B
518:10205000020D0020E702E50A8BD8A3F43325C3570D
519:102060000D0010E70AF7069B3600807437F7C300AF
520:10207000807406F7C30008745D8126C2347FFFC7F1
521:102080000635370500B88003CD3981269B36FF7FA2
522:10209000C7060F370400F7069B3640007506C706D3
523:1020A0000F370300F7069B360020742AF7C3000899
524:1020B0007424803E9D36067C1DFF069434830E6694
525:1020C00037208E06303426F7060A000001740726F2
526:1020D000810E08000001F7C30020753BF7069A3710
527:1020E0008000740BFF06893733C0E70EE90400FF58
528:1020F000063B37F7069B360020741C80269E36FF71
529:1021000075158E06303426F7060A00000874072677
530:10211000810E08000008C3C300000000000000009A
531:1021200002230223022302230323DD220223FD21B3
532:102130000223A424F32402238D227A23022397244A
533:102140001B247524022302238E25FB8E067E01FBB1
534:1021500026833E0000FF74F2268E060000FA268BCE
535:102160001E080026231E0A0074E58CC08ED0268B24
536:102170002602008C16F23322FF756A26A11C008A03
537:10218000E38ADC22D8750DD0E824F80AC075F2B0D5
538:1021900080E9EDFFD0E824F80AC07502B08032E48F
539:1021A00026A31C00F7C3080075472E8A9FC5252E5D
540:1021B0008BBFC52680C310268E1D268C1E06008B65
541:1021C000160000C7060000FFFF26891583FAFF7579
542:1021D0000A2E8B97CD26262116080033C08ED826CE
543:1021E000891E0400C38ADFB7002E8A9FC525E9E057
544:1021F000FF2683260800F783C310E9DEFF60061E72
545:102200006887256A001F8E06F2338B0E3434390E30
546:10221000F233740E26810E0A00000226810E080099
547:1022200000022689260200A3F2338ED08D2680007C
548:10223000368926020036891E200036C706080000AF
549:1022400000B90400BE00002E8BBCC52636C705FFB2
550:10225000FF36C74502FFFF83C602E2EB8E067E0112
551:10226000368B0E22008CC026833E0000FF268E0691
552:1022700000007407263B0E22007DEA368C06000023
553:102280008EC0268C160000FB36FF2E1E00061E6830
554:102290008B256A001F2609360800F7C600FF740167
555:1022A000C356522E8BB4C52581E6FF002E8BB4C5D4
556:1022B000268CC28EC026C7060000FFFF8EC2268372
557:1022C0003CFF740F8BD0268754028EC226A30000D9
558:1022D000E90700268944022689045A5EC3061E685F
559:1022E0008B256A001F8E06F23326A30A0026892654
560:1022F0000200A134348ED08D2680008C16F233E992
561:102300004DFECF501E525333C08ED826833E04005C
562:10231000FF26C706040000007403E91A00833EE6A6
563:102320003A027613FF06D6338CC08E063234BE4096
564:1023300000683A23E95EFFE884F85B5A1F58CFE84B
565:10234000E10026C606180010268A1E2900881E1BDA
566:102350003726C7060C00FF7F26A10E00E79C26A1AA
567:102360000800E79AE50080FB0874090D18ACE70047
568:10237000071F58CF0D1800E9F4FF501E0633C08E1A
569:10238000D8833EA1360075B7268B3606002EFF9403
570:10239000DC23071F58CFE88A00E5000D1800E7008E
571:1023A000E84900C353F706EF342000752DE58C256E
572:1023B00000708BD8E58C2500703BC374058BD8E981
573:1023C000F2FF3D00307510E50225EFFFE702C7067A
574:1023D000E03AFFFFE90300E812005BC3A323962362
575:1023E000A423A4239623A4239623962326A029007E
576:1023F000A21B3726C7060C00FF7F26A10E00E79C14
577:1024000026A10800E79AE50025FF53268B36060033
578:1024100083E60E2E0B84AD25E700C3061E688B25D0
579:102420006A001F830EEF3420830E9B3608E50025DB
580:10243000EFFF0D0800E700E500A910007501C3E5F6
581:1024400000A9100075F9C350535156061E33C08EB3
582:10245000D8B80500E784E5080D000425FF04E70867
583:10246000E5000D1800E700E5020D1100E7021F0767
584:102470005E595B58C3501E33C08ED8C706EF340078
585:102480000083269B36F7E5000D1800E700E5020DF6
586:102490001100E7021F58CF60061E6887256A001FDB
587:1024A000E816F5C3061E688B256A001F8EC02683BA
588:1024B0003E0A00007403E8430026C7060A00FFFF37
589:1024C000268B1606008E1E8E018CD88BCA833E008A
590:1024D00000FF8E1E0000740A2B16080073EB290EF5
591:1024E000080026890E0800268C1E00008ED88C0657
592:1024F0000000C360061E6887256A001F8EC08BC857
593:102500008E1E8E0126C7060A0000008CD8833E006E
594:1025100000FF74253B0E00008E1E000075ED8ED866
595:1025200026A10000A300003DFFFF74568ED826A10F
596:10253000080001060800E94900268E1E0200BE18A8
597:1025400000833CFF743C390C74198E1CBE00008360
598:102550003E0000FF742C390E000074078E1E000030
599:10256000E9ECFF26A10000890433C98ED93DFFFFA5
600:10257000751083FE18750B268E1E0200812608003A
601:102580007FFF33C08ED8C31F0761CF1F07CF600600
602:102590001E6887256A001FE506251E003D1E007582
603:1025A000F6B90800E558E75A23C0E0F8C300000078
604:1025B000000000000000AC000000A8008C02040035
605:1025C0000008102000FF0E0C0C0A0A0A0A0808086E
606:1025D0000808080808060606060606060606060691
607:1025E00006060606060404040404040404040404A1
608:1025F000040404040404040404040404040404049B
609:1026000004040404040202020202020202020202A0
610:10261000020202020202020202020202020202029A
611:10262000020202020202020202020202020202028A
612:10263000020202020202020202020202020202027A
613:102640000202020202000000000000000000000080
614:10265000000000000000000000000000000000007A
615:10266000000000000000000000000000000000006A
616:10267000000000000000000000000000000000005A
617:10268000000000000000000000000000000000004A
618:10269000000000000000000000000000000000003A
619:1026A000000000000000000000000000000000002A
620:1026B000000000000000000000000000000000001A
621:1026C00000000000001800140010000C00FF7FFF45
622:1026D000BFFFDFFFEFFFF7FFFBFFFDFFFE7FFFBF49
623:1026E000FFDFFFEFFFF7FFFBFFFDFFFEFF00000036
624:1026F000803EE234017603E9A500B80000E74EB958
625:102700002800E2FEC606453702BF3F282E8B45084B
626:10271000E74EB92800E2FE2E8B1DC706B3364011E6
627:10272000C706B1362700C70646370200C706483736
628:102730006400F706B5360200751C2E0B5D0281267B
629:10274000B336FFFEC706B1369C00C7064637080001
630:10275000C70648379001891EB736891EFE33BE2052
631:10276000008BC3E74EB92800E2FE2E8B4504E74EEE
632:10277000B92800E2FEE54E8BCB2E2345062E234DD5
633:10278000063AC174364E75D9803E453700740BC683
634:1027900006453700BF2F28E972FFC606453701F707
635:1027A00006B53602007414E5CE25FDFFE7CEE843FA
636:1027B00000E5CE0D0200E7CEE83900803EE23401AC
637:1027C0007601C3B8EA05E78CFAE812F4FB8D06D06F
638:1027D000398BD8C1E804A338348EC0A1303426A385
639:1027E000020026C7060000FFFF83C318D1EB26892D
640:1027F0001E0800C3E5020D0040E702E5000D0400DD
641:10280000E700B80000E70AE50AA900807514E508AA
642:102810000D0010E708E50A0D0008B90500E70AE217
643:10282000FCC3E5080D0010B90500E708E2FCC3048D
644:102830000C2000010C7EFF000C0200100040000C78
645:10284000C6010000C0F7FF00C002001000400000F9
646:1028500033C08ED88D3E72498D36B037B914008B97
647:102860001E3034895C022E8B45028944062E8B056E
648:1028700089440483C70483C610E2E8C6069E360E68
649:10288000E8FD26688328A1AA02CD35833EA1360043
650:102890007403E93B2733FF8E06A6028B36A4022E73
651:1028A000FFA42E30830E993604C70637370100C6C1
652:1028B00006CA3401E97D19803EA0360874E68026F8
653:1028C0009E36FF751AF7069B3600207412F7069B9A
654:1028D000360300750A830E663710C606A03608E96F
655:1028E000FB01803E9E360275CEC606A03606E9EC98
656:1028F00001C3E9E80126C7060A00000026FF2604F6
657:1029000000A1D1362639061A007522A1D336263900
658:10291000061C007518A1D5362639061E00750E2630
659:10292000F7060C0040007405830E663740810EAF39
660:10293000360010A1AF36E706803E9D36027506CD03
661:1029400034E9A21AC3F7069B361000755426F60622
662:102950000A00FF754C26A0190024C03C4075118068
663:102960003E953600743B26C7060400FFFFE93100A0
664:10297000E8F104F7069B360300742F8BD8B87D036B
665:10298000CD3A8BC3C606A03606F7069B3602007505
666:1029900005C606A03604810E9B36800083269B3632
667:1029A000FCE92301E8871DE933015026A10C00252D
668:1029B00007003D07007503E984003D05007503E944
669:1029C0007C00833EE83A047475833EE83A02746EF4
670:1029D000F706E63418807503E96A00F706E6340066
671:1029E00080743526803E290002752D5156578D364C
672:1029F0003E348D3E2000B90600F3A65F5E59744553
673:102A000026A12000A33E3426A12200A3403426A103
674:102A10002400A34234E92600F706E6340800740BCC
675:102A200026803E1900007403E91300F706E634100F
676:102A300000741226A02800C0E80422C0740726C72C
677:102A4000060400FFFF5823C07403E957FF81269B4B
678:102A500036FFFE83FE067F2426A120003B06D136EA
679:102A6000751A26A122003B06D336751026A1240034
680:102A70003B06D5367506810E9B36000126A1200047
681:102A8000257FFFA3B83426A12200A3BA3426A124AF
682:102A900000A3BC348BC686C4A3C034D1E680FC0935
683:102AA0007403E8AA1C8BC62EFFA4304926A10C0093
684:102AB0003DFF7F740F26FF2604008E063834E8366B
685:102AC00006CD50C3E91600CD34E91100CD34893666
686:102AD0003D37A19D36A33F37C606A0360CE88E00D1
687:102AE000A19F3622E47532F7064C370100752AF6AD
688:102AF000069D3680740788269E36E931003A069D89
689:102B000036A39D3674288BF02EFFA40D2B4429EE9E
690:102B1000421944CD442F455A453A269E367501C385
691:102B200032C086C48BF0A29E362EFFA420498B2E85
692:102B3000993623ED7501C3BF0100BE000085FD7508
693:102B40001A46D1E7E9F6FF2A0029002800270025C8
694:102B50000005000700260006002000F7D7213E9957
695:102B600036D1E62E8BB4472BE94FFFE956FF80267E
696:102B70009E36FF7517F7064C370100750FF6069D58
697:102B800036807408F7066637FFFF7507C706663795
698:102B90000000C3F70641370100750BB87F03CD393C
699:102BA000C7064137010033F6B80040850666377422
700:102BB0002180BC5437FF7404FE84543780BC9634A3
701:102BC000FF7404FE84963431066637833E66370010
702:102BD000740546D1E873D4C3A1F433A90088740BFB
703:102BE000A9001075098B1E4337FFE3E9D700C7061C
704:102BF00035370500C70643371E2CF706F4330008A7
705:102C00007406C7064337102CB88003CD39E9CDFED2
706:102C1000A9000874D9FF0E353775EDE96600A900E3
707:102C20000875CBFF0E353775DF810EC234C000F654
708:102C3000069D36807448810E9B360080F7069B36D1
709:102C40000100741EB87D03CD3A810E9B368000834F
710:102C5000269B36FEC7060F370200C606A03604E9DB
711:102C60007BFE803EA036047507833E0F3701750555
712:102C7000C606A03606C7060F370200E95FFEBE0291
713:102C800000E94AFE80269E36FF753AF6069D36809C
714:102C9000742DF7069B360020752BC606A03606FF5E
715:102CA000069434830E6637208E06303426F7060AE3
716:102CB000000001740726810E08000001E90600BE2D
717:102CC0000400E909FE810EAF360008A1AF36E70621
718:102CD000E50AA90080740E8126AF36FFF7A1AF3652
719:102CE000E706E909FFE9F5FDC70641370000830E55
720:102CF000993602E9E7FD80269E36FF751DF7069B93
721:102D00003600407505830E993608830E993620816A
722:102D1000269B36FFBFB88503CD39E9C0FD803E9EB6
723:102D200036067407803E9E360A7534F6069D368058
724:102D30007506BE0700E996FDC606A03604833E0F61
725:102D40003702741BC7060F370400803E9E36067597
726:102D50000EF7069B3640007506C7060F370300E9DD
727:102D60007BFD803E9D36047512810EC2340040FF0B
728:102D7000069234C606A03606E962FDBE0500E94D9E
729:102D8000FDF6069D36807519830EC23404BE06001A
730:102D9000E93BFD80269E36FF75C5FF063137E90009
731:102DA000008326C234BFC606A03606E92FFDE50A19
732:102DB0005025C3BFE70A5880269E36FF750DA9002F
733:102DC000407508C606A03606E912FDB88303CD3962
734:102DD000C3B87C03CD39F706F43300107509C70674
735:102DE00033370200E9F6FCFF0E33377403E9EDFCDC
736:102DF000FF068E34E8F719830EC23408BE0300E9DB
737:102E0000CCFC0000000000000000000400040405E9
738:102E1000040404000300030300000000000000009D
739:102E20000004000808050808080003000303000068
740:102E3000020404040400000800000A1400001A0040
741:102E40001C001E2000000441060B08C2FFE704031B
742:102E500006040405040604870403060404854EA240
743:102E600004CF04CDC706A2370000C706A63700006E
744:102E700026A12000257FFFA3F53626A12200A3F777
745:102E80003626A12400A3F936E83B198BF0268B0ED9
746:102E90000E002BC883E90EB8018083F9047C51260B
747:102EA0008A542888161C3740268B6C2686CD3BCD4D
748:102EB00086CD890EA43775384032FF268A5C29807A
749:102EC000FB15772580FB0A742080FB01741BB80476
750:102ED000802E3A97022E74072E3A97182E751133CA
751:102EE000C080FB09754F8BF3C326C7060400FFFFA4
752:102EF0005052A1A43786C4263B0626007C32268188
753:102F00003E260000047E298D742A268B1422D2745A
754:102F10001F80E6BF80FE097517C706A23701008033
755:102F2000FA04750C268B4402A3033786C4A3D0345D
756:102F30005A58E9B1FFBD72372E8A872E2E22C074EF
757:102F40001605442E8BF82E8B053E89460083C5025C
758:102F500083C70222E47DEF8D742A83E9047503E9B7
759:102F6000A100268B1422D27503E97C00C706A63780
760:102F70000100BF72378B0583C70280E6BF80E43F44
761:102F800080FE09752280FA04755EC706A23701002B
762:102F9000268B4402A3033786C4A3D03486C4C70655
763:102FA000A6370000E947003BFD7E15268B04A840AC
764:102FB0007406B80780E938FF32C0268B04E92E007A
765:102FC0003AF475B1C745FE000080FE22750D3AD077
766:102FD0007716C706A6370000E913003AD07509C76F
767:102FE00006A6370000E90600B80580E902FF32F6C0
768:102FF00003F22BCAB8058023C97603E964FF740382
769:10300000E9EDFE33C0BF72378B1547473BFD7F1B91
770:10301000F6C6807416F706A63701007406B8088055
771:10302000E9C3FEF6C64074E0B80780E9B8FE7D4209
772:10303000A34544294429B728E228EE2BF228F52895
773:103040000129AC2A4429442944294429442900005F
774:10305000733600000336C535833545350735D23420
775:1030600045340000000000000000000000000000E7
776:103070000000A6380000E03800000000000000005A
777:103080000000000000000000000000000000000040
778:10309000F2330000A6336033FD32BC3277323C326B
779:1030A000FB316A310A31E0E0101010E0E0E0E000AE
780:1030B0000000000000000000000000000000000010
781:1030C000000000000000E000E0E0E0E0E0E0E0E020
782:1030D000E033FF26F6061A0080741B2680261A00AD
783:1030E0007F268B3E260083E71F740B26800E200070
784:1030F0008026013E0E00C3602E8B84A63026A318C6
785:1031000000D1E62EFF94503061C326C7060400C4E8
786:103110002A26C7060E00160026C706060006002649
787:10312000C606190000E8BF05E8980526C706260070
788:10313000000826C60628004026C60629002ABF2AFF
789:103140000026C6050426C645012AA1933733DBA90C
790:1031500040007502B301A900107402B788A90008E5
791:10316000740380CF4426895D02C3830EC2342026B7
792:10317000C70604006B2B26C7060E00300026C706C4
793:1031800006000A0026C7060A00040026C606190023
794:1031900000E86905E82C0526C7062600002226C699
795:1031A0000628006026C606290029BF2A0026C60573
796:1031B0000826C645012D8D7D02BE5437B90300F3A4
797:1031C000A526C6050826C645012E8D7D02BE5A37A6
798:1031D000B90300F3A5E8D405E86405B90600BE54B8
799:1031E000378D2E2C00268B4600290483C60283C50A
800:1031F0000283F90475024545E2EBC326C7060400C5
801:10320000C42A26C7060E00240026C70606000600AC
802:1032100026C606190000E8E404E8A70426C7062627
803:1032200000001626C60628006026C606290028BF0C
804:103230002A00E85B06E87405E80405C326C706040F
805:1032400000C42A26C7060E001A0026C70606000676
806:103250000026C606190000E8A304E8660426C7068F
807:103260002600000C26C60628006026C60629002770
808:10327000BF2A00E82105C326C7060400C42A26C7C2
809:10328000060E00200026C70606000A0026C7060A0A
810:1032900000040026C606190000E84B04E8240426B2
811:1032A000C7062600001226C60628004026C60629A4
812:1032B0000026BF2A00E8F404E88404C326C70604F5
813:1032C00000C42A26C7060E00340026C706060006DC
814:1032D0000026C606190000E80D04E8E60326C70626
815:1032E0002600002626C60628004026C606290025F8
816:1032F000BF2A00E8B604E84604E8FA04C326C70675
817:103300000400C42A26C7060E003800A1A237500BBD
818:10331000C0750726C7060E00340026C7060600063D
819:103320000026C606190000E89903E8A4FD26C74553
820:1033300026002A580BC0750626C745260026A11C64
821:1033400037C1E0042688452826C645292483C72A94
822:10335000E82904E8A004E82205E8F803E80904C322
823:1033600026C7060400C42A26C7060E00320026C758
824:10337000060600060026C606190000E84503E850C8
825:10338000FD26C745260024A11C37C1E00426884538
826:103390002826C645292383C72AE8E003E86C04E809
827:1033A0008A04E89C04C326C7060400C42A26C7066C
828:1033B0000E00340026C7060600060026C6061900C1
829:1033C00000E8FF02E80AFD26C745260026A11C37B3
830:1033D000C1E0042688452826C645292283C72AE855
831:1033E0009A03E8C703E85703E8F803E87804E88A93
832:1033F00004C326C7060400744526C7060E003E0017
833:1034000026C7060600060026C7060A00040026C6D0
834:1034100006190000E8FC02E8A902833E8D37037517
835:10342000019026C7062600003026C6062800502632
836:10343000C606290020BF2A00E8D003E80103E8B54A
837:1034400003E89F03C326C70604006143B9F0008365
838:10345000E90226890E0E0026C7060600020026C6CF
839:103460000619000026C7061A00000026C7061C0021
840:10347000000026C7061E000000E8470283E90E860A
841:10348000CD26890E260086CD26C60628000026C633
842:1034900006290008BF2A0083E90426890D26C645AF
843:1034A00001268D7D0283E902BB0100B830304B75E7
844:1034B00017BB0A008AC4268805B03180C40180FC8D
845:1034C0003A750AB461E90500268805040147497583
846:1034D000DDC326C7060400044526C7060E001200F9
847:1034E00026C7060600060026C606190001E8E50103
848:1034F000E8D00126C7062600000426C606280000DC
849:1035000026C606290007C326C7060400C42A26C704
850:10351000060E00200026C7060600060026C606196D
851:103520000006E80402E89B0126C7062600001226D2
852:10353000C60628000026C606290006BF2A00E86B3A
853:1035400002E8FB01C326C7060400C42A26C7060EEC
854:1035500000200026C7060600060026C6061900053C
855:10356000E8C601E85D0126C7062600001226C60649
856:1035700028000026C606290005BF2A00E82D02E81B
857:10358000BD01C3FF06823426C70604003D4126C79D
858:10359000060E00200026C70606000E0026C60619E5
859:1035A0000004E88401E81B0126C706260000122655
860:1035B000C60628000026C606290004BF2A00E8EB3C
861:1035C00001E87B01C326C7060400674226C7060E32
862:1035D00000200026C7060600080026C606190003BC
863:1035E000E84601E8DD0026C7062600001226C606CA
864:1035F00028000026C606290003BF2A00E8AD01E81E
865:103600003D01C3FF06843426C7060400674226C76F
866:10361000060E00240026C7060600080026C6061966
867:103620000002E80401E89B0026C7062600001626D3
868:10363000C60628000026C606290002BF2A0026C6A4
869:10364000050426C6450101A10F3786E0F6066F374F
870:1036500001750F3906CC3474098BD8B88903CD397C
871:103660008BC3A3CC34268945028D7D04E83D01E857
872:10367000CD00C326C7060400C42A26C7060E001CB8
873:1036800000A1A237500BC0750726C7060E00180010
874:1036900026C7060600060026C606190000E8230015
875:1036A000E82EFA26C74526000E580BC0750626C719
876:1036B0004526000A26C645290083C72AE8BD00E83A
877:1036C000FF00C3565751B90300BED136BF2000F3E7
878:1036D000A5595F5EC3565751B90300BED136BF1A14
879:1036E00000F3A5595F5EC326C7061A00C00026C7AF
880:1036F000061C00000026C7061E000010C326C706D1
881:103700001A00C00026C7061C00000026C7061E00BF
882:103710000008C326C7061A00C00026C7061C000002
883:103720000026C7061E000002C326C7061A00C000F6
884:1037300026C7061C00FFFF26C7061E00FFFFC32684
885:10374000C6050826C64501028D7D02BE0537B903B0
886:1037500000F3A5C326C6050426C6450106A10D37FC
887:10376000268945028D7D04C326C6050426C645016B
888:1037700007A10B372689450283C704C3A1A2370BD3
889:10378000C0741326C6050426C6450109A1033726C1
890:1037900089450283C704C326C6050826C64501021B
891:1037A0008D7D02BE0537B90300F3A5C326C6050605
892:1037B00026C645010B8D7D02BEEF36B90200F3A58A
893:1037C000C326C6050626C6450120A16837268945B9
894:1037D00002A16A3726886505C1E00426884504836E
895:1037E000C706C326C6050426C645012126C74502CD
896:1037F000000083C704C326C6051426C64501228DD2
897:103800007D02BE1F37B90900F3A5C326C6050C26E5
898:10381000C64501238D7D021E0E1F8D364054B9030F
899:1038200000F3A533C0B90200F3AB1FC326C60508D9
900:1038300026C64501288D7D02BED136B90300F3A509
901:10384000C326C6050826C6450129A1C23486E0263E
902:10385000894502A19B362689450426884506268887
903:1038600045078D7D08C326C6050626C645012B8D56
904:103870007D02BEBB36B90200F3A5C326C6050626E7
905:10388000C645012C8D7D02BEE536B90200F3A5C305
906:1038900026C6050426C6450130A1373786E02689AD
907:1038A00045028D7D04C326C7060E001E0026C706EE
908:1038B0000600020026C606190000E86CFEE803FEBA
909:1038C00026C7062600001026C60628003026C60693
910:1038D000290011BF2A00E83500E84500E85500C37B
911:1038E00026C7060E00120026C7060600020026C6DE
912:1038F00006190000E832FEE8C9FD26C706260000CA
913:103900000426C60628003026C606290013C326C68C
914:10391000050426C645010C26C74502000183C704DD
915:10392000C326C6050426C645010E26C74502000269
916:1039300083C704C326C6050426C645012126C745FC
917:1039400002000083C704C300000000000000000064
918:10395000B339C939833AB339B339B3391C3A1C3A4C
919:10396000A3B634A1E936A31137A3D234A1EB36A311
920:103970001337A3D434A1ED36A31537A3D634A10150
921:1039800037A3CE34A1F736A31737A3DC34A1F93619
922:10399000A31937A3DE34F7069B360200750C33C03B
923:1039A000A09E368BF02EFFA45039E90F01BE070010
924:1039B000E919F1F6069D368074F3C606A03602C6F4
925:1039C000066E3708C606703702B88803CD39F6068A
926:1039D0006F3701754AA1D1363A06E93675413A2664
927:1039E000EA36753BA1D3363A06EB3675323A26EC09
928:1039F00036752CA1D5363A06ED3675233A26EE36C5
929:103A0000751DC606703702FE0E6E37750FB8880337
930:103A1000CD3A830E9B3612C606A0360CE9A8F0A15B
931:103A20000537263B0620007540A10737263B0622B6
932:103A3000007536A10937263B062400752CA09E365A
933:103A40003C02750826F6061800087547C6066E374C
934:103A500008FE0E7037751CC606703702E5020D01B0
935:103A60000425EFFFE702E95EF0C606703702C606DE
936:103A70006E3708E50225FFFB0D010025EFFFE70289
937:103A8000E944F0F7069B360001742526F606180077
938:103A90000875ED81269B367FFFB88903CD3AB8843F
939:103AA00003CD3AC606A036068326C234AFE917F026
940:103AB000A101373A260F377FC7E9F7FE83269B36E9
941:103AC000ECE82A0D810E9B368000BBFF7FCD53C6EC
942:103AD00006A03602E9F0EF830E9B3611C606A0362B
943:103AE0000CE9F9EF443B2C3BC72A6B3B443BC72A0C
944:103AF000C72AC72AA3B634810EC2340020F7064174
945:103B0000370100741B8CC3C70641370000B87F0320
946:103B1000CD3A33C08EC0BF5437B90600F3AB8EC365
947:103B200033C0A09E368BF02EFFA4E43AF7069B36F6
948:103B3000000175218326C234BFA1A936E700A19BED
949:103B400036E90900A19B3681269B36FFDFA90020BC
950:103B50007506E96E00E96FEF830E993604C70637E4
951:103B6000370100C606CA3401E95800830E9B36406F
952:103B7000E85800A105373B06E9367537A107373B02
953:103B800006EB36752EA109373B06ED367525FE0E80
954:103B90007137751CB88703CD3A830E993610A15042
955:103BA00037C7065037000009069936C606A0360802
956:103BB000E914EF830E993604C70637370300C606AB
957:103BC000CA3403C606A0360AE9FCEEA1D136263B6C
958:103BD0000620007515A1D336263B0622007512A1DA
959:103BE000D536263B062400750FC38D362000E90B21
960:103BF000008D362200E904008D36240083C402F7CC
961:103C000006E63401007415263A047708720E263A47
962:103C100064017208C606A03606E9ABEEE87C0A8CA1
963:103C2000C03DFFFF741B26C60618001026C70604F9
964:103C300000493C26C70606000C00CD50B94E00E2F4
965:103C4000FEC606A0360AE994EEE97BEE8F3C063DFF
966:103C5000063D063DD23CEA3C063D063DA3B6348116
967:103C600026C234AFDFC7064C370000B88A03CD3A0E
968:103C7000803E9D3604750C803E9E36067405C60651
969:103C80009F360633C0A09E368BF02EFFA44C3CF727
970:103C9000069B360020750E81269B36FFBFB88B032E
971:103CA000CD3AE95400F7069B3600017403E917EE9C
972:103CB000C70637370200C606CA3402830E99360497
973:103CC000830E503704F6069D3680752AE81F0BE9EF
974:103CD0002700F7069B36000175D3C7063737020069
975:103CE000C606CA3402830E993604C606A03600F60C
976:103CF000069D36807403E8DE0A81269B367CFFBB76
977:103D0000FFFFCD53CD54E9BEEDA3B634E8AD01B805
978:103D10008603CD39C7064C3700008126C234AFDF99
979:103D2000F6069D36807434F7069B3600207456F7ED
980:103D3000069B3600017427E83501721CBE004085E1
981:103D400036C23475080936C234FF069234E88B0156
982:103D50007306810E99368000E96CEDE9B500C7065F
983:103D600037370200C606CA3402830E993604830E22
984:103D7000503704803E9E36087403E85A0AE8EF0084
985:103D800072D6E9C8FF803E9E360A7512C606A03676
986:103D900000F7069B3608007402CD54E8390A8126E4
987:103DA0009B36FFBFE8C80072AFB88B03CD39E99CE2
988:103DB000FFF6069E36FF7558A3B634E8FE0081264E
989:103DC000C234FFBFF6069D36807448F7069B360066
990:103DD000207422F7069B3600407508E89100723087
991:103DE000E9220026A10C00A960007524810E663727
992:103DF0000008E9D2ECC7064C370000E871007210E9
993:103E0000B88B03CD39E8D3007306810E9936800054
994:103E1000E9B4EC803E9D3604750C803E9E360674F7
995:103E200046C6069F3606F7069B360001740C803E98
996:103E30009D36087505C6069F360AE8320072D1E83D
997:103E40009900803E9D36087513810E99368000F7E3
998:103E5000069B3600207508B88B03CD39E968ECC69F
999:103E6000069F360AE960ECB88603CD3AE958EC269D
1000:103E7000A10C00A9600074088126C234FFBFF9C3F9
1001:103E8000F7069B3600407413810E66370008E84A37
1002:103E9000007306810E99368000F9C3810E9B3600AF
1003:103EA0004080266F37FE81269B367FFFC606A036F0
1004:103EB00000F8C3810E99360001E921EC26A120000B
1005:103EC000A3FB36A3AA3426A12200A3FD36A3AC345B
1006:103ED00026A12400A3FF36A3AE34C3A10537263B99
1007:103EE0000620007519A10737263B062200750FA191
1008:103EF0000937263B0624007505E80200F8C3511E69
1009:103F0000068BC78D362000BF0537B903001E061F7C
1010:103F100007F3A58BF88D362000BFA034B90300F35A
1011:103F2000A5071F598BF8A10737A3A634A10937A30A
1012:103F3000A834F9C3C606B63401E98BEBE887088BD1
1013:103F4000F00512002629060E00268B442A263A0682
1014:103F50000E00755B26832E0E000280FC277550260E
1015:103F60008B442CA9FFFF75478BFE33C026F6453CDA
1016:103F7000807406268A453A241F03F826807D450969
1017:103F8000752D8CC28E0638348EDA8B0E0E00268983
1018:103F90000E0E008D742CBF1800F3A433C08ED826EB
1019:103FA000C7060400B53F26C70606000600CD50B878
1020:103FB0000680E9EFE926A10C00A39337830E99361A
1021:103FC00001E900EB26803E1C00FF752F26803E1E77
1022:103FD00000FF752726F7060C004000751BA1D1369F
1023:103FE00026A31A00A1D33626A31C00A1D53626A3EA
1024:103FF0001E00B80A80E83607E9E2EAFF069034BE00
1025:104000000A00C606B63401F6069D36807505830E95
1026:10401000C23401E9B6EA803E9D360A750F26A10C2E
1027:10402000002507003D04007503E87900A1F33686FA
1028:10403000E0E71EA3E33681260B37000381260D3708
1029:104040007B7F830E0D3748E81E0026A10C00250754
1030:10405000003D0400740926F7060C0020007506B820
1031:104060000100E93FE9E95FEAC70641370000B87F90
1032:1040700003CD3AA11D37A3C43486E0687F031FA394
1033:10408000060033C08ED8A10B37A3B234A10D37A3DD
1034:10409000B434A1F336A3C834A1EF36A39C34A1F104
1035:1040A00036A39E34C3800E9D3680BE0000E8B40760
1036:1040B000B87B03CD3AB87C03CD39C706333702004D
1037:1040C000A1E536E72EA1E736E73EB88203CD3AF701
1038:1040D000069B3600207503E8FD06A1D336A3EF3614
1039:1040E000A39C34A1D536A3F136A39E34C3F6069D16
1040:1040F00036807431BE2200E91700F6069D368074C2
1041:1041000024BE2300E90A00F6069D36807417BE24FB
1042:104110000056E8A8058CC03DFFFF5E7405E8D7EFA8
1043:10412000CD50E91FE8E99FE9000000000000000011
1044:10413000B88403CD3AB88A03CD39E9F700803EA0B0
1045:104140003608752EA9D007752CA1B1360D0004E7ED
1046:1041500008E50025FF73E700B88A03CD3AE8C306F7
1047:1041600033C0E70EE50A25C317E70ACD54C606A0FB
1048:104170003600E968E9BE0400E93FE983269B36BFC3
1049:10418000C606713703B88603CD3AB88803CD3AB86E
1050:104190008303CD3AB88703CD39810EC2340020E9BC
1051:1041A0009200E84906B88703CD39BBFF7FCD53B8ED
1052:1041B0008403CD3AB88803CD3AB88B03CD3AB8839F
1053:1041C00003CD3AB88603CD3AB88503CD3AC3E500AE
1054:1041D00025FF53E700830EC234408326C234EFE844
1055:1041E0000C06BBFF7FCD53B88A03CD3AB88503CD0B
1056:1041F0003AB88603CD3AB88303CD3AB88703CD3AAF
1057:10420000B88B03CD3AB88403CD3AB88903CD3AC30D
1058:10421000830EC23450E81804E8D305F6066F370160
1059:104220007512B88903CD39833E0F37007506C7066E
1060:104230000F370400A19D3680FC087405B88403CDB7
1061:1042400039E5020D010825EFFFE702A19D3686E062
1062:1042500032E48BF0D1EE33C00D20000906AD36A15B
1063:10426000AD36E704E953E8E95AE833C0A01B37D17B
1064:10427000E03A06A0367503E9BAFFE960E8C70641EF
1065:10428000370000E8C1E1E86A0633C00D4100E75697
1066:10429000A1B1360D0010E708E50225F9FF0D030076
1067:1042A000E702A1B336E70AA1AF36E706A1AD36E7CC
1068:1042B00004E87C03E89F03C7061D3700C8C7060B48
1069:1042C000370003C7060D377B7F33C0A39936A39B06
1070:1042D00036A39D36A39F36A34C37A3F336A3EF3600
1071:1042E000A3F136E882FDC6069F3602E9EFE7E50254
1072:1042F0000D018825EFFF0D00400D0004E702E8F2F4
1073:1043000005E50A0D4000E70A33C0A38137A38537CE
1074:10431000A38337A38737A38937E5000D0084E7001F
1075:10432000B88C03CD39B88000CD35C706AA02FFFF8F
1076:10433000E50025FF7BE700810E9A378000B87E03F9
1077:10434000CD3933C0E70EBE08008E063834E8A7ED3D
1078:104350008326EF34DFFF068137CD50830EEF342004
1079:10436000C3F7069A378000743DA9D0077410A900DE
1080:1043700004741233C0E70EFF068737E9D2FFFF0649
1081:104380008537E9CBFFFF068337E9C4FF83269A37D9
1082:104390007FA18937030687373D05007F01C3BBFF37
1083:1043A0007FCD53E90000E50225FFFB25EFFF0D015E
1084:1043B00000E702A183373B0646377F2AA185373BBA
1085:1043C0000648377C21A18937030687373D05007FE2
1086:1043D00015C6069F3604E50225FFF70D010025EFFF
1087:1043E000FFE702E9F7E6BE0100F7069B360300741B
1088:1043F0000A83269B36FC830EC23404E9D0E6B87BE0
1089:1044000003CD39E5020D016025EFFFE702C706F194
1090:10441000342003B88E03CD39C38126C2347FFF8098
1091:104420000E6F3701F7069B36030074D2B87B03CDBD
1092:104430003AB87D03CD3983269B36EF33C0B08AA2CC
1093:104440009F36A29D36C7064C370100C7060F3704BA
1094:1044500000F7069B3640007506C7060F370300B805
1095:104460008D03CD39E800D5E5020D014025EFFF8B26
1096:10447000D8B87C03CD39C706333702008BC30D0093
1097:104480002025F9FF0B06E83AE702C3FF0EF1347569
1098:1044900001C3E54EA901007512E500A900047505E8
1099:1044A0000D0004E700B88E03CD39C3E500A9000470
1100:1044B00074F325FFFBE700E9EBFFC606A036048393
1101:1044C000269B36FC810E9B368000E910E6B88E03F1
1102:1044D000CD3ACD54810EAF360018A1AF36E706B8FD
1103:1044E0007B03CD39A1D336A38F37A1D536A391371E
1104:1044F000C7068B370200C7068D370200830E993638
1105:1045000040E9D9E5803E9F36067515A9D00775ECC0
1106:10451000250018750EFF0E8B3775E1C6069F36080D
1107:10452000E9BAE5FF0E8D3775D3BE0800E99FE5B8FF
1108:104530007B03CD39F7069B3600207408C6069F36EC
1109:104540000AE90D00F7069B360040740BB88B03CDCB
1110:1045500039810E99368000E983E5B87B03CD39C7F0
1111:10456000068B370400C7068D370400810E9936008C
1112:1045700002E969E5F6069D3680751BA9D00775EB43
1113:10458000A90018750CFF0E8D3775E0E817FBE94C94
1114:10459000E5B88203CD39C3FF0E8B3775CEBE090057
1115:1045A000E92BE5C7063D370000C7069B360000E84B
1116:1045B0003C028126AF36FFE7A1AF36E70681269B96
1117:1045C00036FF7FE5020D010025EFFF25FFDFE70243
1118:1045D000BBFF7FCD5333C0A39D36A39F36E8500069
1119:1045E000E87300B88103CD39C3F7069B3603007426
1120:1045F0000DC6069F3602C606A03600E9DFE4830E2C
1121:104600009B3610C70699360000E8E702E5560D0212
1122:1046100000E756C706A80200008B363D37E8440283
1123:10462000C606A0360EE9B5E4000000000000000058
1124:1046300006B88A03CD3AB88503CD3AB88603CD3A99
1125:10464000B88303CD3AB88703CD3AB88B03CD3AB8D7
1126:104650008803CD3A07C306B88803CD3AB87B03CDAB
1127:104660003AB88203CD3AB87F03CD3AB87C03CD3A4D
1128:10467000B87E03CD3AB88003CD3AB88103CD3AB8BD
1129:104680008403CD3AB88903CD3AB87D03CD3AB88DCD
1130:1046900003CD3AC7064137000007C3068E063834FB
1131:1046A0001F8B0E0E0026890E0E00BE1800BF1800CC
1132:1046B000F3A4061E07CD340733C08ED8C326F606F2
1133:1046C000200080744433C026A02600241F8BF026CF
1134:1046D0008B5C28891E6A37068E0638341FC0E304B7
1135:1046E00026885C288BC6B90600BE2000BF1A00F3DE
1136:1046F000A48BC883C706F3A426812626001F802624
1137:10470000813626000080E9A9FF268B1E2800891E1D
1138:104710006A37068E0638341FC0E30426881E280038
1139:10472000B90600BE2000BF1A00F3A4E984FF86C4C6
1140:10473000A36837E887FFF7066A370F007410803EDA
1141:104740009E36007509BE0000E8ACE9CD50C3C350E9
1142:10475000560633C026F606200080740626A02600E2
1143:10476000241F8BF0268B5C2686FB83EB04744F831F
1144:10477000C62A8CC08ED8B9070033C08EC0BF72372E
1145:10478000F3AB33C98A0C80F9007503E930003BD9DB
1146:104790007303E929002BD98A4401253F0074193D90
1147:1047A0000B007D14D1E08BF82E8BBD5C498D74021B
1148:1047B00083E902F3A4E9020003F123DB75C433C0EB
1149:1047C0008ED8075E58C333C026F6062000807406D4
1150:1047D00026A02600241FC3E50A25C3BFE70AB88622
1151:1047E00003CD39B88303CD3981269B367CDFB8856C
1152:1047F00003CD3AE50225FFF30D010025EFFFE702A7
1153:10480000E50025FF53E700A1E73625FFFEA3E736C5
1154:10481000E73E83269936CF810EAF360010A1AF3622
1155:10482000E706C3E5020D010C25EFFFE702A1E7361D
1156:104830000D0001E73EA3E736810E9B360020830E74
1157:1048400099362081269B367CBF810EAF360010A1A1
1158:10485000AF36E706B88603CD39B88503CD39B883BE
1159:1048600003CD3AC30BF67549068E063234803EE01E
1160:104870003401751B26893606008E06323426F7066B
1161:104880000A000020740726810E0800002007C3805C
1162:104890003EE33401751926893606008E0632342629
1163:1048A000F7060A000010740726810E0800001007A2
1164:1048B000C3E9B4FF50515733C0B906008EC0BFD111
1165:1048C00036F3AE5F740C26F6060000C07504F85986
1166:1048D00058C3F9E9F9FF8B050B45020B4504C35298
1167:1048E00050E506251E003D1E0075F6B80180E75A0A
1168:1048F000585AC3E8E9FF50E50225FF7F0D01002566
1169:10490000EFFFE7020D0080E702A1AD36E704A1AF9B
1170:1049100036E70658C3000000000000000000000059
1171:104920002E2BCE4110427B413041A241AF4544295C
1172:10493000C72AC72A6039F43A5C3C093DB13D343F8F
1173:10494000C72A3C3FC72AC43F16401640ED40FA40F4
1174:104950000741C72AC72AC72AC72AD65200000137EB
1175:10496000E936F336EF361D370D370B379C370337F3
1176:10497000FB36622D4006D12DF401BA4440068C432B
1177:104980006400E82CC800D82B0500E9455000974585
1178:10499000FA00AE2D04016A420200F62CBC02932DEF
1179:1049A000DC051D2D6400A12D1400D73A0807812DC8
1180:1049B0006400B33E020030436400C52CF4018B4414
1181:1049C00002000000000000000000000000000000E5
1182:1049D000803EFD3402740CE82005C706A1360000B5
1183:1049E000E99AF8FF06C033E810058B363D37E873C7
1184:1049F000FEC3CD34E9E805C706A3360000C706416B
1185:104A0000370000E8EDFE33C00D4100E756A1B13696
1186:104A10000D0010E708A1B336E70AA1AF36E706A1FB
1187:104A2000AD36E704E82B09C7061D3700C8C7060BDB
1188:104A3000370003C7060D377B7F33C0A39B36A39D8A
1189:104A400036C7064C370100C6069E36FFC706053737
1190:104A50000000C70607370000C70609370000A3F3A8
1191:104A600036A3EF36A3F136E8FEF5E50225F9FF0D92
1192:104A700003000D008825EFFF0D00400D0004E70244
1193:104A8000B88F03CD39B88000CD35C706AA02FFFF25
1194:104A9000A1A936A3A7360D00A40D0008E700A3A91D
1195:104AA00036C706A3360100C706A5360C00833EA50F
1196:104AB00036007509C7063D370500E913FFFF0EA54F
1197:104AC00036BE1100E82205B89003CD39C3833EA35A
1198:104AD000360174D9C3B89003CD3A26A02B00268B9B
1199:104AE0001E2C00CD34833EA336017403E9F0043C50
1200:104AF0000F751E81FB0002751826A12000A3053743
1201:104B000026A12200A3073726A12400A30937E9091B
1202:104B100000C7063D370100E9B6FEC706A33602000E
1203:104B2000C6069E36FFE8CBFDE81CD933C0A3853707
1204:104B3000A38337A38737A38937B89103CD39B880CA
1205:104B400000CD35C706AA02FFFFE50025FF53E700A9
1206:104B5000810E9A378000B89203CD3933C0E70EBE7C
1207:104B600008008E063834E88EE526C70604007D4B23
1208:104B70008326EF34DFCD50830EEF3420C3F7069A3F
1209:104B80003780007432A9D007740CA90004740E3366
1210:104B9000C0E70EE9DAFFFF068537E9D3FFFF06839A
1211:104BA00037E9CCFFC7063D370100E936FE83269A78
1212:104BB000377FBBFF7FCD53E5000D00ACE700E5027A
1213:104BC00025FFFB25EFFF25FFF70D0100E702A1837D
1214:104BD000373B0646377FCDA185373B0648377CC437
1215:104BE000C706A3360300BE1300E8FD03B89303CD48
1216:104BF00039B89403CD39B89603CD39B89503CD397A
1217:104C0000BE0600E8E303E9D603833EA3360374013E
1218:104C1000C3BE1300E8D203B89403CD39C3B89403DC
1219:104C2000CD3A26A02B00268B1E2C00CD34833EA32C
1220:104C300036037403E9A8033C0D753E83FB00753908
1221:104C4000E5020D0020E702B89303CD3AC706A3366C
1222:104C50000400BE0000E80CFCC6069D3680C6069E19
1223:104C60003600C70633370200B89A03CD39E8FC0096
1224:104C7000C7064C370000E96603C7063D370800E960
1225:104C800061FD833EA336037509C7063D370500E97C
1226:104C900051FDE94A03833EA336047412833EA336D2
1227:104CA00005740BCD34C7063D370700E935FDC7064F
1228:104CB000A3360600C6069E36FFB89A03CD3AB899C9
1229:104CC00003CD3AB89603CD3AB89703CD39B89803D7
1230:104CD000CD39B89B03CD39E918FDCD34833EA336D9
1231:104CE000047718833EA336037508F7069B36000148
1232:104CF0007509C7063D370100E9E8FCE9E102CD345A
1233:104D0000833EA336027709C7063D370100E9D3FC8D
1234:104D1000833EA336047705B89603CD39E9C00283F4
1235:104D20003EA33603751026A10C00250700503D0454
1236:104D3000007503E83600A1F33686E0E71EA3E336EC
1237:104D400081260B37000381260D377B7F830E0D37BD
1238:104D500048E814F3583D0400740926F7060C0020B7
1239:104D6000007506B80100E97A02E986FCA1E536E79C
1240:104D70002EA1E736E73EA1D336A39C34A1D536A3B6
1241:104D80009E34C326803E1C00FF752F26803E1E00E9
1242:104D9000FF752726F7060C004000751BA1D13626AB
1243:104DA000A31A00A1D33626A31C00A1D53626A31E24
1244:104DB00000B80A80E92C02E938FCFF069034BE0AEC
1245:104DC00000C606B63401F6069D36807505830EC210
1246:104DD0003401CD34E90CFC833EA336037509C706C4
1247:104DE0003D370500E9FCFBE5020D03000D00880DD1
1248:104DF00000400D0004E702C706A3360500C6069E64
1249:104E000036FFBE0200E8E101B88903CD3AB89A0343
1250:104E1000CD3AB89903CD39B89703CD39B89803CDB9
1251:104E200039E9BB01833EA33603740A833EA33604EB
1252:104E30007403E9AA01BE0600E8AE01B89503CD39B6
1253:104E4000E99C01833EA336057403E99201BE02008A
1254:104E5000E89601B89903CD39E98401C7060F3705F3
1255:104E600000E97B01E50225FFDFE702C706A336075D
1256:104E700000C7060F370500E96501E8D504C6069DA1
1257:104E80003600C7069B360000C7060F370500C70669
1258:104E9000A8020000C7064C370100E50225F9FF0D06
1259:104EA00003000D008825EFFF0D00400D0004E70210
1260:104EB000E967FCB89A03CD39F706F4330010750999
1261:104EC000C70633370200E91601FF0E33377403E9D2
1262:104ED0000D01FF068E34830EC23408C7063D37032A
1263:104EE00000E9FFFAC35250BAE000B80010EF585A78
1264:104EF000C3C7063D370000E9E9FAFAE85404B88070
1265:104F0000038EC026C7060400D82BB87F038EC026A8
1266:104F1000C7060400E82C33C08EC0A1A736A3A9366B
1267:104F2000A1A936E700A1AB36E702C70605370000A6
1268:104F3000C70607370000C70609370000C6069D36BA
1269:104F400000C6069E36FFC7069B360000C706A3367E
1270:104F50000000C7060F370000C706A8020000C706FA
1271:104F60004C3701008126AF36FFE7A1AF36E706BB1D
1272:104F7000FF7FCD53E87CF9E5560D0200E756FBC3F1
1273:104F80008D3EC0538D36F038B90E008B1E303489FB
1274:104F90005C022E8B45028944062E8B0589440483CE
1275:104FA000C70483C610E2E8B880038EC026C7060493
1276:104FB00000E251B87F038EC026C7060400B2523308
1277:104FC000C08EC0C706A1360100C7060F370500C353
1278:104FD00033FF8E06A6028B36A4022EFFA4A053E850
1279:104FE0008CDBC3E848F7E9F6FF8E063834E807E1C2
1280:104FF00026C7060400DF4FCD50C326C7060A0000AF
1281:105000000026FF260400CD34E9D4FFA1D13626398D
1282:10501000061A007522A1D3362639061C007518A180
1283:10502000D5362639061E00750E26F7060C00400000
1284:105030007405830E663740810EAF360010A1AF367F
1285:10504000E706833EA336027505CD34E956FB833E61
1286:10505000A3360074B1833EA3360577AA26F6060A66
1287:1050600000FF75A2E8FDDD50F6069336207503E9D2
1288:105070008C0026A10C002507003D07007503E9768A
1289:10508000003D05007503E96E00F706E634188075EB
1290:1050900003E96A00F706E6340080743526803E296D
1291:1050A0000002752D5156578D363E348D3E2000B985
1292:1050B0000600F3A65F5E59754526A12000A33E3485
1293:1050C00026A12200A3403426A12400A34234E926CD
1294:1050D00000F706E6340800740B26803E19000074C1
1295:1050E00003E91300F706E6341000741226A0280026
1296:1050F000C0E80422C0740726C7060400FFFF582337
1297:10510000C07403E9DDFE81269B36FFFE26A1200048
1298:105110003B06D136751A26A122003B06D336751000
1299:1051200026A124003B06D5367506810E9B3600016C
1300:1051300026A12000257FFFA3B83426A12200A3BA10
1301:105140003426A12400A3BC348BC686C4A3C034D1AA
1302:10515000E680FC097403E8F6F5A105370B0607376E
1303:105160000B060937743E26A120003B06053775174C
1304:1051700026A122003B060737750D26A124003B0619
1305:1051800009377503E91D0026A02800240F3C03748D
1306:105190001B3C00750F833EA336047410F7069B3644
1307:1051A000000174082EFF94F853E933FECD34C7068E
1308:1051B0003D370100E92CF8833EA336057410833E89
1309:1051C000A336017E0983EE162EFF942454C3CD34FA
1310:1051D000C326A10C003DFF7F740526FF260400E9CD
1311:1051E000FDFDA1F433A90088740BA9001075098B8B
1312:1051F0001E4337FFE3E99700C70635370500C706AA
1313:1052000043372852F706F43300087406C7064337BD
1314:105210001A52B88003CD39E9C5FDA9000874D9FF39
1315:105220000E353775EDE93000A9000875CBFF0E3556
1316:105230003775DF810EC234C000F6069D3680740FCC
1317:10524000810E9B360080C7060F370200E990FDC72C
1318:10525000063D370200E98BF780269E36FF7530F653
1319:10526000069D36807420FF069434830E6637208EA8
1320:1052700006303426F7060A000001740726810E085E
1321:10528000000001E90900C7063D370400E954F78131
1322:105290000EAF360008A1AF36E706E50AA900807414
1323:1052A0000E8126AF36FFF7A1AF36E706E949FFE9E1
1324:1052B0002DFDC70641370000BE2900E82BFDE91E81
1325:1052C000FDCD34833EA336047709C7063D37010080
1326:1052D000E910F7E909FDCD34C3C7069B360000E8A5
1327:1052E0000CF58126AF36FFE7A1AF36E70681269B96
1328:1052F00036FF7FE5020D010025EFFF25FFDFE70206
1329:10530000BBFF7FCD5333C0A39D36A39F36E820F368
1330:10531000E843F3830E9B3610C70699360000E8D2A7
1331:10532000F5E5560D0200E756C706A8020000BE00CC
1332:1053300000E830F5C606A0360EB89C03CD39B8801B
1333:1053400000CD35C706AA02FFFFC706A1360100E956
1334:10535000A5F606B88F03CD3AB89003CD3AB89103BD
1335:10536000CD3AB89203CD3AB89303CD3AB89403CD71
1336:105370003AB89503CD3AB89603CD3AB89703CD3AEB
1337:10538000B89803CD3AB89903CD3AB89A03CD3AB854
1338:105390009B03CD3AB87F03CD3AB88003CD3A07C31B
1339:1053A000F749F14EDF4FDF4FDF4FDF4FF851DF4F4F
1340:1053B000FA4F0B50D151DF4FDF4FDF4FDF4FDF4F41
1341:1053C000E44E0600CD4A0400E44E1900AD4BFA004D
1342:1053D000824C0807094C1400244E6400D74DF40198
1343:1053E000644EBC027A4EE803434E0200B34EF40111
1344:1053F0005B4EF401E54E140006500650954CC15228
1345:10540000C152FE4CDA4C0650065006500650B751B9
1346:10541000B751B751B751B751B7510650D54A065099
1347:105420001D4C0650834D1F4D1F4DED40FA40074166
1348:1054300037372E3737202079792F79792F797920CE
1349:1054400030312E3930202030322F31372F3939206A
1350:10545000000000000000000000000000000000004C
1351:10546000000000000000000000000000000000003C
1352:10547000000000000000000000000000000000002C
1353:10548000000000000000000000000000000000001C
1354:10549000000000000000000000000000000000000C
1355:1054A00000000000000000000000000000000000FC
1356:1054B00000000000000000000000000000000000EC
1357:1054C00000000000000000000000000000000000DC
1358:1054D00000000000000000000000000000000000CC
1359:1054E00000000000000000000000000000000000BC
1360:1054F00000000000000000000000000000000000AC
1361:10550000000000000000000000000000000000009B
1362:10551000000000000000000000000000000000008B
1363:10552000000000000000000000000000000000007B
1364:10553000000000000000000000000000000000006B
1365:10554000000000000000000000000000000000005B
1366:10555000000000000000000000000000000000004B
1367:10556000000000000000000000000000000000003B
1368:10557000000000000000000000000000000000002B
1369:10558000000000000000000000000000000000001B
1370:10559000000000000000000000000000000000000B
1371:1055A00000000000000000000000000000000000FB
1372:1055B00000000000000000000000000000000000EB
1373:1055C00000000000000000000000000000000000DB
1374:1055D00000000000000000000000000000000000CB
1375:1055E00000000000000000000000000000000000BB
1376:1055F00000000000000000000000000000000000AB
1377:10560000000000000000000000000000000000009A
1378:10561000000000000000000000000000000000008A
1379:10562000000000000000000000000000000000007A
1380:10563000000000000000000000000000000000006A
1381:10564000000000000000000000000000000000005A
1382:10565000000000000000000000000000000000004A
1383:10566000000000000000000000000000000000003A
1384:10567000000000000000000000000000000000002A
1385:10568000000000000000000000000000000000001A
1386:10569000000000000000000000000000000000000A
1387:1056A00000000000000000000000000000000000FA
1388:1056B00000000000000000000000000000000000EA
1389:1056C00000000000000000000000000000000000DA
1390:1056D00000000000000000000000000000000000CA
1391:1056E00000000000000000000000000000000000BA
1392:1056F00000000000000000000000000000000000AA
1393:105700000000000000000000000000000000000099
1394:105710000000000000000000000000000000000089
1395:105720000000000000000000000000000000000079
1396:105730000000000000000000000000000000000069
1397:105740000000000000000000000000000000000059
1398:105750000000000000000000000000000000000049
1399:105760000000000000000000000000000000000039
1400:105770000000000000000000000000000000000029
1401:105780000000000000000000000000000000000019
1402:105790000000000000000000000000000000000009
1403:1057A00000000000000000000000000000000000F9
1404:1057B00000000000000000000000000000000000E9
1405:1057C00000000000000000000000000000000000D9
1406:1057D00000000000000000000000000000000000C9
1407:1057E00000000000000000000000000000000000B9
1408:1057F00000000000000000000000000000000000A9
1409:105800000000000000000000000000000000000098
1410:105810000000000000000000000000000000000088
1411:105820000000000000000000000000000000000078
1412:105830000000000000000000000000000000000068
1413:105840000000000000000000000000000000000058
1414:105850000000000000000000000000000000000048
1415:105860000000000000000000000000000000000038
1416:105870000000000000000000000000000000000028
1417:105880000000000000000000000000000000000018
1418:105890000000000000000000000000000000000008
1419:1058A00000000000000000000000000000000000F8
1420:1058B00000000000000000000000000000000000E8
1421:1058C00000000000000000000000000000000000D8
1422:1058D00000000000000000000000000000000000C8
1423:1058E00000000000000000000000000000000000B8
1424:1058F00000000000000000000000000000000000A8
1425:105900000000000000000000000000000000000097
1426:105910000000000000000000000000000000000087
1427:105920000000000000000000000000000000000077
1428:105930000000000000000000000000000000000067
1429:105940000000000000000000000000000000000057
1430:105950000000000000000000000000000000000047
1431:105960000000000000000000000000000000000037
1432:105970000000000000000000000000000000000027
1433:105980000000000000000000000000000000000017
1434:105990000000000000000000000000000000000007
1435:1059A00000000000000000000000000000000000F7
1436:1059B00000000000000000000000000000000000E7
1437:1059C00000000000000000000000000000000000D7
1438:1059D00000000000000000000000000000000000C7
1439:1059E00000000000000000000000000000000000B7
1440:1059F00000000000000000000000000000000000A7
1441:105A00000000000000000000000000000000000096
1442:105A10000000000000000000000000000000000086
1443:105A20000000000000000000000000000000000076
1444:105A30000000000000000000000000000000000066
1445:105A40000000000000000000000000000000000056
1446:105A50000000000000000000000000000000000046
1447:105A60000000000000000000000000000000000036
1448:105A70000000000000000000000000000000000026
1449:105A80000000000000000000000000000000000016
1450:105A90000000000000000000000000000000000006
1451:105AA00000000000000000000000000000000000F6
1452:105AB00000000000000000000000000000000000E6
1453:105AC00000000000000000000000000000000000D6
1454:105AD00000000000000000000000000000000000C6
1455:105AE00000000000000000000000000000000000B6
1456:105AF00000000000000000000000000000000000A6
1457:105B00000000000000000000000000000000000095
1458:105B10000000000000000000000000000000000085
1459:105B20000000000000000000000000000000000075
1460:105B30000000000000000000000000000000000065
1461:105B40000000000000000000000000000000000055
1462:105B50000000000000000000000000000000000045
1463:105B60000000000000000000000000000000000035
1464:105B70000000000000000000000000000000000025
1465:105B80000000000000000000000000000000000015
1466:105B90000000000000000000000000000000000005
1467:105BA00000000000000000000000000000000000F5
1468:105BB00000000000000000000000000000000000E5
1469:105BC00000000000000000000000000000000000D5
1470:105BD00000000000000000000000000000000000C5
1471:105BE00000000000000000000000000000000000B5
1472:105BF00000000000000000000000000000000000A5
1473:105C00000000000000000000000000000000000094
1474:105C10000000000000000000000000000000000084
1475:105C20000000000000000000000000000000000074
1476:105C30000000000000000000000000000000000064
1477:105C40000000000000000000000000000000000054
1478:105C50000000000000000000000000000000000044
1479:105C60000000000000000000000000000000000034
1480:105C70000000000000000000000000000000000024
1481:105C80000000000000000000000000000000000014
1482:105C90000000000000000000000000000000000004
1483:105CA00000000000000000000000000000000000F4
1484:105CB00000000000000000000000000000000000E4
1485:105CC00000000000000000000000000000000000D4
1486:105CD00000000000000000000000000000000000C4
1487:105CE00000000000000000000000000000000000B4
1488:105CF00000000000000000000000000000000000A4
1489:105D00000000000000000000000000000000000093
1490:105D10000000000000000000000000000000000083
1491:105D20000000000000000000000000000000000073
1492:105D30000000000000000000000000000000000063
1493:105D40000000000000000000000000000000000053
1494:105D50000000000000000000000000000000000043
1495:105D60000000000000000000000000000000000033
1496:105D70000000000000000000000000000000000023
1497:105D80000000000000000000000000000000000013
1498:105D90000000000000000000000000000000000003
1499:105DA00000000000000000000000000000000000F3
1500:105DB00000000000000000000000000000000000E3
1501:105DC00000000000000000000000000000000000D3
1502:105DD00000000000000000000000000000000000C3
1503:105DE00000000000000000000000000000000000B3
1504:105DF00000000000000000000000000000000000A3
1505:105E00000000000000000000000000000000000092
1506:105E10000000000000000000000000000000000082
1507:105E20000000000000000000000000000000000072
1508:105E30000000000000000000000000000000000062
1509:105E40000000000000000000000000000000000052
1510:105E50000000000000000000000000000000000042
1511:105E60000000000000000000000000000000000032
1512:105E70000000000000000000000000000000000022
1513:105E80000000000000000000000000000000000012
1514:105E90000000000000000000000000000000000002
1515:105EA00000000000000000000000000000000000F2
1516:105EB00000000000000000000000000000000000E2
1517:105EC00000000000000000000000000000000000D2
1518:105ED00000000000000000000000000000000000C2
1519:105EE00000000000000000000000000000000000B2
1520:105EF00000000000000000000000000000000000A2
1521:105F00000000000000000000000000000000000091
1522:105F10000000000000000000000000000000000081
1523:105F20000000000000000000000000000000000071
1524:105F30000000000000000000000000000000000061
1525:105F40000000000000000000000000000000000051
1526:105F50000000000000000000000000000000000041
1527:105F60000000000000000000000000000000000031
1528:105F70000000000000000000000000000000000021
1529:105F80000000000000000000000000000000000011
1530:105F90000000000000000000000000000000000001
1531:105FA00000000000000000000000000000000000F1
1532:105FB00000000000000000000000000000000000E1
1533:105FC00000000000000000000000000000000000D1
1534:105FD00000000000000000000000000000000000C1
1535:105FE00000000000000000000000000000000000B1
1536:105FF00000000000000000000000000000000000A1
1537:106000000000000000000000000000000000000090
1538:106010000000000000000000000000000000000080
1539:106020000000000000000000000000000000000070
1540:106030000000000000000000000000000000000060
1541:106040000000000000000000000000000000000050
1542:106050000000000000000000000000000000000040
1543:106060000000000000000000000000000000000030
1544:106070000000000000000000000000000000000020
1545:106080000000000000000000000000000000000010
1546:106090000000000000000000000000000000000000
1547:1060A00000000000000000000000000000000000F0
1548:1060B00000000000000000000000000000000000E0
1549:1060C00000000000000000000000000000000000D0
1550:1060D00000000000000000000000000000000000C0
1551:1060E00000000000000000000000000000000000B0
1552:1060F00000000000000000000000000000000000A0
1553:10610000000000000000000000000000000000008F
1554:10611000000000000000000000000000000000007F
1555:1061200090EAC01500000000000000000000130607
1556:00000001FF
1557/*
1558 * The firmware this driver downloads into the tokenring card is a
1559 * separate program and is not GPL'd source code, even though the Linux
1560 * side driver and the routine that loads this data into the card are.
1561 *
1562 * This firmware is licensed to you strictly for use in conjunction
1563 * with the use of 3Com 3C359 TokenRing adapters. There is no
1564 * waranty expressed or implied about its fitness for any purpose.
1565 */
1566
1567/* 3c359_microcode.mac: 3Com 3C359 Tokenring microcode.
1568 *
1569 * Notes:
1570 * - Loaded from xl_init upon adapter initialization.
1571 *
1572 * Available from 3Com as part of their standard 3C359 driver.
1573 */
diff --git a/firmware/Makefile b/firmware/Makefile
index 0d15a3d113a2..344713b11669 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -26,7 +26,6 @@ fw-shipped- += acenic/tg1.bin
26else 26else
27acenic-objs := acenic/tg1.bin acenic/tg2.bin 27acenic-objs := acenic/tg1.bin acenic/tg2.bin
28endif 28endif
29fw-shipped-$(CONFIG_3C359) += 3com/3C359.bin
30fw-shipped-$(CONFIG_ACENIC) += $(acenic-objs) 29fw-shipped-$(CONFIG_ACENIC) += $(acenic-objs)
31fw-shipped-$(CONFIG_ADAPTEC_STARFIRE) += adaptec/starfire_rx.bin \ 30fw-shipped-$(CONFIG_ADAPTEC_STARFIRE) += adaptec/starfire_rx.bin \
32 adaptec/starfire_tx.bin 31 adaptec/starfire_tx.bin
@@ -86,7 +85,6 @@ fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \
86 qlogic/12160.bin 85 qlogic/12160.bin
87fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin 86fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin
88fw-shipped-$(CONFIG_INFINIBAND_QIB) += qlogic/sd7220.fw 87fw-shipped-$(CONFIG_INFINIBAND_QIB) += qlogic/sd7220.fw
89fw-shipped-$(CONFIG_SMCTR) += tr_smctr.bin
90fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp 88fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp
91fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \ 89fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \
92 ess/maestro3_assp_minisrc.fw 90 ess/maestro3_assp_minisrc.fw
diff --git a/firmware/WHENCE b/firmware/WHENCE
index 182ecb6c275e..8388f02de2bd 100644
--- a/firmware/WHENCE
+++ b/firmware/WHENCE
@@ -89,18 +89,6 @@ Licence: Allegedly GPLv2+, but no source visible. Marked:
89 Copyright (C) 2001 Qlogic Corporation (www.qlogic.com) 89 Copyright (C) 2001 Qlogic Corporation (www.qlogic.com)
90 90
91-------------------------------------------------------------------------- 91--------------------------------------------------------------------------
92Driver: smctr -- SMC ISA/MCA Token Ring adapter
93
94File: tr_smctr.bin
95Info: MCT.BIN v6.3C1 03/01/95
96
97Original licence info:
98
99 * This firmware is licensed to you strictly for use in conjunction
100 * with the use of SMC TokenRing adapters. There is no waranty
101 * expressed or implied about its fitness for any purpose.
102
103--------------------------------------------------------------------------
104 92
105Driver: kaweth -- USB KLSI KL5USB101-based Ethernet device 93Driver: kaweth -- USB KLSI KL5USB101-based Ethernet device
106 94
@@ -567,32 +555,6 @@ Found in hex form in kernel source.
567 555
568-------------------------------------------------------------------------- 556--------------------------------------------------------------------------
569 557
570Driver: 3C359 - 3Com 3C359 Token Link Velocity XL adapter
571
572File: 3com/3C359.bin
573
574Licence:
575/*
576 * The firmware this driver downloads into the tokenring card is a
577 * separate program and is not GPL'd source code, even though the Linux
578 * side driver and the routine that loads this data into the card are.
579 *
580 * This firmware is licensed to you strictly for use in conjunction
581 * with the use of 3Com 3C359 TokenRing adapters. There is no
582 * waranty expressed or implied about its fitness for any purpose.
583 */
584/* 3c359_microcode.mac: 3Com 3C359 Tokenring microcode.
585 *
586 * Notes:
587 * - Loaded from xl_init upon adapter initialization.
588 *
589 * Available from 3Com as part of their standard 3C359 driver.
590 */
591
592Found in hex form in kernel source.
593
594--------------------------------------------------------------------------
595
596Driver: PCMCIA_PCNET - NE2000 compatible PCMCIA adapter 558Driver: PCMCIA_PCNET - NE2000 compatible PCMCIA adapter
597 559
598File: cis/LA-PCM.cis 560File: cis/LA-PCM.cis
diff --git a/firmware/tr_smctr.bin.ihex b/firmware/tr_smctr.bin.ihex
deleted file mode 100644
index 6797451ffa9c..000000000000
--- a/firmware/tr_smctr.bin.ihex
+++ /dev/null
@@ -1,477 +0,0 @@
1:10000000BC1D123B63B4E900001F000101000205A2
2:10001000010006030100040901000A070100080BA2
3:1000200001000C000000000F0100100D01000E1374
4:10003000010014110100120000050015010016193D
5:1000400001001A1701001800000E00000001000056
6:100050000004001B01001C0000070000000F00004E
7:10006000000B001D01001E0000080000000200003F
8:10007000000C000000060000000D0000000300005E
9:10008000000A00000009000478C6BC0194049380B3
10:10009000C84062E9DA1C2C1555555555555555582B
11:1000A0000BE9E5D595C19D77CEBBA06E1C05F67713
12:1000B000C602FA9670E81DC0170E02FA587DC05F9E
13:1000C00072CEECA4C384907A30CD8D7919E76C247C
14:1000D000279C08390738A84A4CEA4D989B244CC005
15:1000E00026D3E7545A4DF24C0C13234990326EA498
16:1000F000DF9371137726E126F8260C4C12260809A7
17:10010000828260A9307936B0B2A8A772648F9B331F
18:1001100033F9B839D51173AA75265D2651932A494A
19:1001200094C99589BC4DC89B809BA099064C862696
20:10013000589BA49B9937626C679B3330BF366661CE
21:10014000BF36ECC5BD66825A5031D59D9818293C02
22:1001500098864C17263E2CB8693B492EB408431AA2
23:10016000A4F9B351F110F343CD086F6379B3330EA3
24:100170001398499804DA7CE05279310C982E4DACF2
25:100180002C8414EE4CFE675EE49A7529D7A9353AA3
26:10019000945BD59B58B4AF7566AF14A9EF40952515
27:1001A00008B9AD42FCD8D98C330E1398661E45AC05
28:1001B000B00C42D3CCA61262DEB4B180497DA2DE7F
29:1001C000B418C02484E654F5834601681A630CC64B
30:1001D0001264FA4C351C2C0EAAAAAAAAAAAAAAAA88
31:1001E000AAAAAAAAAAADD70270E04CF3A1C1D5C0B1
32:1001F0003CB96939604E58770267933C99E4CF382F
33:100200001C972E401B903146A35E0E88346A35E061
34:10021000E8AA351AA9F51546A3EA7D4AA351AA9F73
35:100220007054A6572EB4CDC8A30CC1DAC6E1CB7A60
36:10023000D41C68FFCF55A8C02D851117442A300B58
37:100240004A88C24DB520D5260169516952195260BC
38:100250001695168296549805A545F3DD6AF9281877
39:10026000EF003030514E445D12D143E6126F9EBA1A
40:10027000CCDF25031DE006060A30CCA9EB2D008655
41:10028000A612654F56D665495F3DE837C940C77825
42:100290000181828C33184980AE40C518059C6D18C9
43:1002A000660EF3A0C61262DEF504B4AC6BC61991FB
44:1002B0007305482E72948073A1C8473666642F3642
45:1002C0006664079902918E72D10F9D063173A0C3A7
46:1002D000516A1A20BF3A0C2C7387435E600223FCDC
47:1002E000E0D635EF9EF5EF92818EF0030305186698
48:1002F00045CC0B482E700A4039D0E4239B3332178B
49:100300009B333203CC8548C73814A5CE297ED280D2
50:10031000A1A8B448882FCE830B1CE1D0D7980488BD
51:1003200087CE963173A58FF38358D7BE7B82AF9269
52:10033000818EF0030305186645CC1520B9C8290045
53:10034000E743908E6CCCC85E6CCCC80F3205231C82
54:10035000E450D45A17882FCE8310F9D023173A04CB
55:1003600035E600221639C3A3FCE0D635E0BFF41809
56:10037000F22D4D43516E5A221F30D417E74191732D
57:1003800005482E776900E743908E6CCCC85E6CCC34
58:10039000C80F3205231CEF4C4E0604C99E0BFF41CB
59:1003A0008F22D4D43516E5A221F35A82FCE8322EEE
60:1003B00060A905CE1348073A1C8473666642F3664B
61:1003C000664079902918E70A989C0A9EB5125C7CD1
62:1003D000C3318B982A7CD3ED38E9D34E74ED499E16
63:1003E0000BFF418F22D4D43516E5A22DEB45338F78
64:1003F000FCF7A05F25031DE40E060A30CC0CF3EBDE
65:1004000040DE61A870920A00E1241E00E1241E0073
66:10041000E1241E00E1241E00E1241E010F982A0B96
67:10042000F3A0C8B9A2A4173A6900E743908E7548B3
68:100430005E706901E6005231CC1814A5CC09829493
69:10044000730CA091F525CC070684849F30A2A47D6F
70:100450005075A665014A8EB4CCC435547566A49710
71:100460007A895053138019E3495C6DCEA940350653
72:1004700078D25706F1B32A8D972362925D69991C51
73:100480006A36E6CD46126F9EE1ABE4A30CC0DEAC4B
74:10049000D40D281BD012A500F84BAD332806A0DEE2
75:1004A00014973A895DC00DE30690925D699866B92C
76:1004B0001995E4A8CF9D331849BE7B86AF928C3343
77:1004C00024140CF4832421C270BFF418F22D4D4380
78:1004D000516E5A221F32A82FCE8322E605A4173A66
79:1004E0006900E743908E75485E706901E642A46337
80:1004F0009802294B9A2978E9405313818132678207
81:10050000FFD063C8B5350D45AE50087CE0D05F9D87
82:100510000645CC01A4173A6900E743908E75485E02
83:10052000706901E659A463981C52973B30528E7D46
84:100530002A091F51EBA4A40AB99487AEC531380229
85:10054000FFD063C8B5350D45AE50087CEA20BF3AF0
86:100550000C8B9A16905CE9A4039D0E4239D5217943
87:1005600095480F300A918E60EB297300095404CA34
88:1005700082655265E4CA226572650932E099724C5F
89:10058000C4E00BFF418F22D4D43516B94021F38A41
90:1005900082FCE8322E60A905CE9A4039D0E4239D32
91:1005A00052179954619901E640A4639804B1849864
92:1005B00018EF2D0305313802FFD063C8B5350D455E
93:1005C000B968887CE0505F9D0645CC81482E713427
94:1005D0008F48014815210521E90A5203CE5A4639B0
95:1005E000CF478E60AB1AF35343EB3524B81B30076B
96:1005F000098A742F7E41741E1D0D874649D595D1F9
97:10060000D5D5BBA94E829D053A0A7414E829D0427B
98:10061000745BCE50C40745BCE20C40745BCE8304CF
99:10062000F9954D13635E6F313BA08BA2C5398D7870
100:100630003A22A0006BC1D1546016D991A2E7438C35
101:1006400024DC1CE05117396B3BCC4B422E6B50BF66
102:100650003636654F7A185525789823E7503EF38152
103:100660004C026D3E7153AF78A9D4A629B1BCD9997B
104:10067000B28E628F222E7516B0B2AB23281654525A
105:1006800031BCD999B28E6619022E7516502CA9C8A4
106:10069000C6F520D3E47F4F9C0AD6167F90EE4CEB34
107:1006A000CFE288BA2F4286AEBDE5A7529F93637909
108:1006B000EB3308F9945247CD99256F3A0C13E65560
109:1006C000344C5A4DB52395A548115A0A4395AC2C84
110:1006D000BA240549B1BCCAA7726C6BC5BDE83169C3
111:1006E000525D0612653EB1504C7D4FAC0A300B3660
112:1006F0006411738A838E75129F7BD29958EE822E75
113:1007000077A0E39D5D4FBC2A532953DE9324BAB3EF
114:1007100036AA4AC679D4B9DE625A11735050BF372F
115:10072000366F1323BA0C24CEBDE2A752B28E6B6093
116:10073000622E751330ACA059CA646379B333651C5B
117:10074000CC32045CEA2CA059DF231BD4835247DD52
118:100750007996D49EB3524BA25A1A8D5D7B82A752D2
119:10076000B28E6619022E7516502C8C321D7B8EA708
120:1007700052B1BCD9999804DA7CE2ACFE6619022E1B
121:100780006550BF336664FE7418864C1726D6165221
122:100790003918DE7ACCC23E651491F36649086E833F
123:1007A0000933AF31ED0D9D0612622A318D6DE7419F
124:1007B000827CCAA68987092E29B1AF1039D66497E1
125:1007C000301D42759344028C24D27AB350F68905C9
126:1007D000435E6198C02C92253C8B2489490549E7EA
127:1007E0000CB98498B7AD3344AE5A5186609F38A98E
128:1007F000A26C6BC48EF45E49461262DEB4CD215CFD
129:10080000B4A30CC13E7229A26C6BC6126247F0E819
130:10081000C33204354092A4828810927CCBD42FA49A
131:1008200002118498B7AD3344AE5A5186609F38A9FF
132:10083000A26C6BC48EF45E494408493E65EA17D247
133:100840000108C24C5BD699A42B9694619827CE459B
134:10085000344D8D78810927CCBD12286C58AFB6F382
135:10086000A0C13E655344D8D7928E7D4BC2FA612613
136:10087000063AB36B030549E70CB96F5A66955CB449
137:10088000A30CC13E7029A26EA4DF9371137726E1F9
138:1008900026F826C6BC9473F92F0BE9849818EACC85
139:1008A000EC0C15279C32FF3D56AF928B7AD335D591
140:1008B000CB4A30CC13E7029A26C6BC947341979179
141:1008C000F483CE0420628B0516498C24C0C7569051
142:1008D000C0C15279C32E5BD5A672D294FAAD58C866
143:1008E000FA9F54B3324BB954A651866B79D0609FAE
144:1008F0003205344D8D7A4D1E7AB35100A93D59A869
145:100900007B4482A1AF4A8D52A95241494F3A2E40B1
146:10091000A49950BE90085279C32E61262DEB4CD07D
147:1009200015CB4A30CC13E7029A26C6BC48FE1D25DB
148:1009300046A954A920A4A79D1720524CA85F48049B
149:100940002309316F5A6680AE5A5186609F3814D1A0
150:100950003635E4A79D1720524CA2450D8B15F49116
151:10096000DE8BC928C24C5BD699A95CB4A30CD6F324
152:10097000A0C13E640A689B1AF16D4CAA92E03694BD
153:10098000709B297813AEB3AA85D44375093AC9EB95
154:100990003524B81B328E13487E4EFD40FD40FD408D
155:1009A000FD40FD40FC13F421F917458A300B335FFD
156:1009B00083A22A300B335F83A2A8C02DB32070928C
157:1009C000139ADE741827CCAA689B1AF70745518042
158:1009D0005B66470738A823E751113FE0E8854601E9
159:1009E0006D990612654F7A2024BAB33215257BAD76
160:1009F0003378AE0E73D047CEA730CC44FF83A2A885
161:100A0000C02CD991C1D11518059B3208BA2C518040
162:100A100059B3207092E29889FDBCEE1890FC8BA22D
163:100A2000C52B0D783A22A561AF074551805B66441E
164:100A30009EB3524B83ADC709BE1F9F74655D0A17F5
165:100A40007CABA0C24C3849122E384907A30CC13EDA
166:100A5000655344D8D7ADE700324B9B33344A03008B
167:100A60009D25CE8324B819998C02124BA199D8C028
168:100A7000274973CFF93CF47CE79804E92E7F39E3EA
169:100A80004F4653C06013A4B9E53C03DE8F9CF300CE
170:100A90009C6FCF3E85F9A336021E6038923E631AE2
171:100AA000109FCF181092BCD0A40CDCC00F9C9734C0
172:100AB00062B6E7F3F3A5CF1842341CC2CAFA8E68B7
173:100AC0005206AF3CA30DBF9E50E1D173CAE03AFC81
174:100AD000C1091A1E6A5C5B8E634E7773CC6167DD59
175:100AE000E66C48D1F31B24695108D4421BF467D14A
176:100AF000804E2FD08CD83009C21E801C46013A4748
177:100B0000D031A106013A7F4630211804E95E8429DC
178:100B100000C027CDD0007C9804F92E84628C027D21
179:100B2000BA3E7E4C027D2E8C61083009F41D0165B1
180:100B300073009F51D085201804FABD194618C027AC
181:100B4000DFD194384C027D174657013009F5FA0180
182:100B50000906013E87A14B88C027DC740D39D300FC
183:100B60009F73D030B39804FBBD06C483009F47D069
184:100B70003648CC0271BF3F9A17E63F0821E692A49F
185:100B80008F9A1031A7F310B184AF3AACDCF773F24F
186:100B90005CC62ADB9E7E7E97310863D0737B43A8B8
187:100BA000E63D34EAF3E315BF9F185F45CFE89F5F4A
188:100BB0009A5B03D0F3D3CE371CD00FBB9E68783B33
189:100BC000BCCA31E8F9A20212A27351086FD1F346F0
190:100BD0000138BF40FC23009C21E84951804E91F42C
191:100BE000210319804E9FD0216306013A568C02746E
192:100BF000FE75495E63D34A54423513A7D1804E95A2
193:100C0000E81E9A4C027CDD1BB9E6013E4BA062A3B4
194:100C1000009F6E8CFCF3009F4BA04218CC027D0716
195:100C200043DA13009F51D03D349804FABD1C628C06
196:100C3000027DFD1C6173009F45D1F44E6013EBF4FF
197:100C400025B033009F43D1A79C1804FB8E8403E991
198:100C5000804FB9E843C13009F77A0A319804FA3E67
199:100C6000844041804E82E7418709230423009D058B
200:100C7000CE961C248C108C0274173A043849182123
201:100C80001804E82E7450E12460846013A0B9D411D4
202:100C9000C248C108C0274173A82384918211804EA5
203:100CA00082E7528E12460846013A0B9D401C248C66
204:100CB000108C0274173A090E12460846013A0B9836
205:100CC0006A1C24B0E11804E82E6B50E1258708C0A7
206:100CD000274173054384961C23009D05CCAA1C2440
207:100CE000B0E11804E82E70687092C3846013E54484
208:100CF000F9409D05CE5A1C24B0E11804F9D13E708C
209:100D000027CF13E5442CA042CB89F2213A0B9C0A51
210:100D10001C24B0E11804F9D10B3810B3C4213936C2
211:100D20005C42C8842B79D061C2741524BAD331E5F2
212:100D300059082908E066634295128100290BC151C8
213:100D400024B81999902290B418A0914101414141D1
214:100D50005283CA4028682908BA16109C990B5694E9
215:100D600090521574C0271A2AD29025D3009D28AB23
216:100D70004A42174C0270D4842E9804E12A42174C40
217:100D8000027082904BA60138514842E9804E15A46A
218:100D90002174C0270FA412E9804E82AC80ACA0ACB5
219:100DA000A959E5644565CAC84ACE0ACE4ACE95918E
220:100DB000959495932925C0CCCC88A4975636647217
221:100DC00090548A9C4508B9B766129309C9B2748ECB
222:100DD000BA6013E5348EBA6013E4748EBA6013E51A
223:100DE000691D74C027CA291D74C027CED225D3001F
224:100DF0009F38A44BA6013E5E912E9804F915225D02
225:100E00003009F3E912E9804F905225D3009DC5487F
226:100E100025D3009C45CECD09C9B21A44BA6013E768
227:100E2000348974C0271C27B79C80C2D776599B93FE
228:100E30000C64C31D1BF4454BC7C63A37E8814BC74A
229:100E4000C63A37E8914BC7C632618EB3BCC34A225B
230:100E5000E6B5249771C987B431AE73A2CF39D25D9C
231:100E6000044442C0D6DE710616BBDBCE830C64C3DD
232:100E70001D311304F9954D133293635E6614CC292A
233:100E80002A5330A6614CC299853A72CCC299850624
234:100E90001BB30A661414249985330A08B186614C81
235:100EA000C2842168733B30A661414EA5985330AC93
236:100EB0005976614CC2B08DD6614CC2B02CF6614CF3
237:100EC000C2B18CA5985330AC0F24CC2998560F286A
238:100ED0006615921A1985330ACA850CC2998565C3AD
239:100EE000D985330ACE7086614CC2B397710C993B99
240:100EF000CC83580BEA779D064ABE047460E0D14E5D
241:100F0000384C3EEE3EEE3EEE3EEE30BBCAE11F7781
242:100F10001F771F771F7727708FBB800E11F771F730
243:100F20007C6F3CB33602FB8DE655707F2D246955EE
244:100F30004F58A9231F54F78A95252B750CCCAC5616
245:100F400051CC51E445CEA21239C0A0AF566A497FB8
246:100F5000028C09F80BEBAF56766752B28E69A71177
247:100F600073A8B1BCCAA0A936502C98E70AF566A4AC
248:100F700097E25A3027BAF7834EA5330A66158DE6F5
249:100F80005539D2A7AC546016701B728E628F222E18
250:100F9000751602FB8DE60A953D62A300B701B553B5
251:100FA000DE2A5494ADD43332B15947314791173AC0
252:100FB0008848E702B017DC679D4B8DE752AA7BD4C7
253:100FC000AA92BDD699BC5602FB8CF36666C6F36640
254:100FD0006662992AF8186870B08A0D5555555552B1
255:100FE00032E1405C380BEA9B87017DC05F7017DC03
256:100FF00005F5DC9B017D614D80BEA77982A21F5063
257:10100000152A8F8B1CE5A5138458E702915405021D
258:101010004BBD221A947F9C1AC05F421A21D180597D
259:10102000C06D1C2C0A83555555555555555555556C
260:1010300055541CB85C6E179C2F385E70E7B85E7014
261:10104000BCE179C2F385E70BCE179C299C299C292A
262:101050009C230F5814EE357726219305C9B017D27B
263:101060001D188A219305C9B017D187AC0A740FAE39
264:10107000F55A82A3E43A3114BBD7599974A21930B6
265:101080005C9B017D187AC0A740F843D4638925D0C2
266:1010900010D61C6A10F5558925D151661F51F5915E
267:1010A000492E8915986AA3E08A9465640E1317384F
268:1010B000A8864C1726C05F461EB028631F087A8C8E
269:1010C0007124BA021AD00D421EAAB124BA2A2D31B7
270:1010D000F51F587492E8875A6352DEF451694A3E0C
271:1010E00009694650F0E131730545BD598D8B4A7C45
272:1010F000D3ED38E9D34E74ED443260B93602FA5B71
273:10110000DE8A2D29D0E121F5A39221F219305C9BD2
274:10111000017D21F5A0C6016701B445CEA51239D4E1
275:101120001C05F440A1C2C3506AAAAAAAAAAAAAAAE4
276:10113000AAAAAAAAAAAA81AF869F191BE781F3656A
277:10114000F280BE7017DFDF380BEB0DC380BEA70F38
278:10115000954F5A94C02CD8B1A7CE5A1173A83AC251
279:10116000CCB63017DC6F35A9804DA7CE2A1879C5CB
280:1011700049DE61A822E75033F9986408B99542FC2A
281:10118000CCD9953D62A248D448E70288B9C1A0E312
282:101190009D4E62E6CCC66BCE8310C982E4DAC2C82B
283:1011A0001EC3B93602FAA9EB4E3030FA0DF0A9EBA6
284:1011B00040B90FAA7AD2C2C8FAA7AD410A47D53DB5
285:1011C00068ACF1F54F5A97547D4FA8AA551F11737B
286:1011D0005AB017DE5D59A925D0552A46BCB822AEB3
287:1011E00045293E14FAE19994CA4ABE3DD699925DCA
288:1011F0001517C8D7DC15178A401F0A9EACC9654968
289:101200005C1D10684A3E5BDE83169580BE91745863
290:10121000A4007C38E7563017DF75A6649745209DFB
291:10122000035F70545E291DF0A9EACC865495C1D1A4
292:1012300006830FAA7BD0654945BDE962D291DF04E0
293:101240005D16291C7D4FAC1A471AA9F5676653280D
294:10125000B7BD2C5A523BE3DD59A925D1A8AC086B88
295:10126000EE08ABC5202F854F566675495C1C181DCE
296:1012700081C26405F080BE355CD017C255F0957C04
297:10128000255F080BE1017C7BAB3524BA1055931A1E
298:10129000FB822AF148D7C2A7AB31B2A4AC639D4A06
299:1012A0008D7C7BAB3524BA1054308D7DC11578AC64
300:1012B0006F5A94601AE379D4AA4F854F5666D54980
301:1012C00058C73A9549F045D1629486BC1D13D29017
302:1012D000FFCF7A83F25031DE006060A11735A85F3E
303:1012E0009B1B3707441A300B380DBC1CE0D047CE8F
304:1012F000A0AA7AA1986A92953D6831805B80DAA9AC
305:10130000EF41952516F7A58B4AC679B333602FAA0E
306:101310009EB15180599ECAA7AC0A300B67B2ADD5B9
307:10132000DA925D17A300B32D956E08A958A1173A5C
308:101330008B017D54F78E9525081CE05602FBC1D128
309:10134000151805926B3C1D1228C02CA56C11701746
310:10135000B2384D80BEE02FB4EC4AEDB39E02FB8064
311:10136000BEE02FB139933E6DE710609F32A9A26CA9
312:1013700005F440E60A953D6A2300B380DAA7D62A31
313:10138000030D7017D22E76294FBC54A6516F7A5890
314:10139000B4AC05F48BA2F40E350D492EB4CC18A5CF
315:1013A000C8F84A9723E1052E47C28A5C8F85697287
316:1013B0003E1F4AC3551F5643328CA35E60A845CEDC
317:1013C0000D602FA3849DD8F017D22E0E1B2384D836
318:1013D0000BEB89F380BEE02FBB3985DF2203E701E9
319:1013E0007DC05F7017D11738145BD6A2740D4B7A8D
320:1013F000B33196946BCC3523D749481573290F5DCB
321:101400008AC05F4D79843580BE881CC3529F59685D
322:10141000C02CE036AA7BCD4A92BEF3814A7D5B594F
323:1014200094CA1C24EEC780BE881CC3529F5968C052
324:101430002CE036AA7BCD4A92BEF38143849C7B3854
325:101440000BEBAF70D4EA53009B4F9C5430F38A945B
326:10145000FAB6B3299422E61A85F9B05993F9D2C4A1
327:101460003260B936B0B390D977261C2722E896B4FB
328:1014700023EA9EB511805965862073968D79AD5803
329:101480000BE917448A4A07D77A82A190FAEF0154F0
330:10149000BA50D4591E2CE9F38A99856B0B23159702
331:1014A00072611730D42C738748AA028125DE910D12
332:1014B0004AC05F7ED280A53EB2D0C86B80BE881C79
333:1014C000EA0917441A371A917458A371AF074454A4
334:1014D0006E35E0E8AA640F90FAD06300B380DA2C8E
335:1014E000738748AA028125DE910D4AC05F48BA275A
336:1014F000A300B701B74F9CB46BCC3516F566632DCE
337:10150000291EBA4A40AB99487AEC508B9C0822FCC1
338:10151000F9B2553D62A92351239C0A3C730D445CEA
339:10152000E15071CEA11FE7156B0B25ED0B93602FDA
340:10153000AA9EAC3665495F7A2050087FEF3914497E
341:10154000011181046040CC59C0AD23EB41B081F260
342:101550003A41AA5043E4D48654A087C152CA9301A9
343:1015600032549D2402000052AF1646A7916708B47A
344:101570000451F16519B46E2DC0AD490092571B742A
345:10158000455F2351B7440A1006A36E8B6B081F19E1
346:10159000D1E680828054042A4591A9E459C22D01E4
347:1015A000140450D3FC558461D980512FE21F465F4B
348:1015B00040E020154ABC591A9E459C22D01148CBC8
349:1015C000E81408015415E2C8D4F22CE116808A46CA
350:1015D0005F527CD9A8F888D05A3CD25C5B80DAA7ED
351:1015E000D65A0886A45D17A0C3522E88A8221F537E
352:1015F000EADACCA650E127763C05F54FAB6B329981
353:1016000043849C7B380BE927ACD492E00EDA384D4A
354:1016100080BEE67D50BA51AE66EFBCDC7B871E0211
355:10162000FA93E6CD47C443CD0F349DA300B05501D6
356:10163000AE038404CE01D0E17002800E89E9221F3E
357:10164000E0E896B011F4C2CE036A442DC06D48059F
358:10165000B80DA300B776D5DEB150DC7D77BC54BAA7
359:10166000527F5814340F9AF381580BEAEF581460E4
360:1016700016A56C2EF7814BA56F7D5DEEB52E95807E
361:10168000BEF073BD047CEAFEEB4CDE2953DD6A54E8
362:1016900094A9EA0A8C02D64C3C05F400EACD56AF78
363:1016A000C047D29C8D29CAE02FAEBD75999D4AF9DD
364:1016B000EF517C940C77801818292AF8E0E8AA30BA
365:1016C0000B2A987C1D1151805954C351F51B3324AA
366:1016D000BB82A5195C1D1028C02C9AC7C1D1228CD1
367:1016E00002C994645C0CD68E13602FB80BEA30E309
368:1016F000C05F48DC780BE800E3C05F6C38D52E355E
369:101700004F5A8A61AA9F561B32994642C8010C451E
370:10171000CEA517E6C6CEA9EB151646A24738144348
371:101720002622E73D602FAA9EB512E07F017DE3E708
372:101730000293F995445CE5A0E39D4A7F9C54A9EB94
373:10174000510546B9FCC01B222E64542FCD46CCA7B0
374:10175000D586CCA65055C645CE5A0E39D4A7F9C564
375:101760004A9EB5118059C06DCFE600D9117322A1F0
376:101770007E6A36653EAC366532B017DD3E72D27990
377:10178000310C982E4C20732A8FF38AADE741827C6E
378:10179000CAA689B5859FB0F017D51F5454251AA83D
379:1017A000FF2A946511D74944D5CCA055D8AE0E88F0
380:1017B0001460164D6322E07286384D80BEE02FB86B
381:1017C0000BEE02FB8138F017D7D71E02FAFAE3C0FE
382:1017D0005F4C85900218C85B80DA300B701B4C227E
383:1017E000D34C33038C2E4C4326D0F56366D095A79B
384:1017F000CE45330AD61642386EE4CEBD592CD2AB54
385:10180000BA949DE61AB017D54F5A8B091A88B9C5F4
386:10181000424730D43216728865BD599925A5602F8C
387:10182000B860F308B74A1A8FAB0D994651AF38A884
388:101830008E9065135218A054B1422E61A848E72D2E
389:1018400016F7A805A5602FA475D251357328157613
390:101850002B83A20518059358C8B806286384D80BB3
391:10186000EE02FB80BEE02FA043A7017D4CE3C05FEA
392:101870007017DC05F4642DC06D1805B80DA5BD6AA0
393:101880002386AA9EB511A46AA3EA8A8D23E117389C
394:101890003469719845A6986A3EAC36651946BCE233
395:1018A000A23A41944D48628152C516F7A88B4A541A
396:1018B000F5A88C02DC06D1039CB4A9EE0A95252A72
397:1018C0007AAD46016701B5D7AC0A300B6C4935E6F5
398:1018D000B567F3006C88B99150BF311B32A7B86867
399:1018E00095257BAD3378A7CD3ED38E9D34E74ED47E
400:1018F00022E706848E60A8FF38AB839C2A08F9D4BF
401:101900002063BC1A060AC05F4642DC06D1805B80B9
402:10191000DA22E61A848E72D16F5A80871AAA7AD494
403:1019200048C8D547D5152323E11738348CBA4B7BEB
404:10193000D402D28C22DC06D51F561B328CA35E71DA
405:10194000511D20CA26A43140A962B017DF9EF4B70A
406:10195000C940C778018182B83839491C26C05F70F8
407:1019600017D4ABE12AF84ABE12AF8F974FCBA7012D
408:101970007DDA80AA91647F4A81D522C8FE828025C3
409:1019800048B23EBBDC352E9407E88A9C03E24BA5A7
410:1019900077ABB332E94BBD598684977A04BA53E1E9
411:1019A00032EF50D4E63553EB029CC7D77AB330D22E
412:1019B0005DEA02E9445D1628C02CE0369174455971
413:1019C00018D54FAC0AC435308B38692BBD5998698E
414:1019D0002EF512E958674AEF50D58E3E1CA4B0CEC2
415:1019E00093216E1A481FA22AC30D577AB30D092EF0
416:1019F000F4435D288B832092384D80BEE02FAC17D6
417:101A000049B3A582E93EE93674E02FA6CE9C05F4E1
418:101A1000C22C8C52577AD48D48FAEF50D5AE35533C
419:101A2000EB028621AAEF56661A4BBD44BA50C4E9B0
420:101A300053EB028681F5DEA1A8621F5DFEA25D293F
421:101A400077A86A618D40FD11530C6AA7D60530C78F
422:101A5000D77FA9574A5DEB481B0C7C8B9D8A53EFBF
423:101A60006694CA54F5A0C6016E036A9F5676653225
424:101A70008B7BD2C5A5602FAA7D65A300B701B4C832
425:101A80005A078FED01D527916701B48B9C541C73C5
426:101A9000A8845CC150BF365660AB8C8B9C541C73C1
427:101AA000A8845CC150BF36566C05F553D6A2300BE6
428:101AB000295B19FCF69445CF150BF33CB32A7AC584
429:101AC0004601648A31239C0A5DEA34332E95C7CEE1
430:101AD0002A4FE65020B9310C9BEF391445CE45070B
431:101AE0001CEA4687AB1B3684A75EAC966752B017DC
432:101AF000DCFE7B4A22E78A85F99E59977A8D0CCBCA
433:101B0000A527F3A0443260B937DE72288B9C8A0E79
434:101B100039D48C05F7E7B82AF92818EF0030305788
435:101B200007440A508FF07391411F3A9045C0BB188B
436:101B3000E13602FBFB9E02FAEEE7F5CF017D105C79
437:101B4000F017D105CF017D53EB2D1805B80DA64236
438:101B5000DC06D31735A88B9C0A0E39D40CFE7B4AC1
439:101B600022E6550BF331B3602FBC7CE2A4FE655135
440:101B70001738141C73A819FCF69445CCAA17E66311
441:101B8000660AB8CC85A158F6A23548487F4A89959F
442:101B90002121FD0502549E45910E3C05F507405557
443:101BA00048523E86A07548523EB5004A9C006BC71D
444:101BB000CE4527F32A843735DEA0AB231AAEF58352
445:101BC0005918D743DE2AD094EBDE053A959FCCC353
446:101BD0002045CCAA17E666CC43264FE741222E705B
447:101BE0006838E753E02FABBC12D2E9580BEAA7AD37
448:101BF00045A11FC05F7839C8A08F9D481C24EEC73F
449:101C000080BEBAF56D6649770D4EA53009B4F9C5A9
450:101C1000430F38A93F9D02FBCE4511739141C73A4E
451:101C2000919FCF69445CF150BF33CB32A7AC549045
452:101C30008D448E702977A8D0CCBA56B0B29D8C86D0
453:101C40004C172677261C271C249E2361BE8E124F1C
454:101C500011871CEA5C05F5D7B86A752977AB0D9931
455:101C600074A54F72A0AA4AC6F36666C63982AF75DC
456:101C7000A66F146BCE05707396823E7528E13AA765
457:101C8000AD44601652B61D7AB6B324BB86A75298EF
458:101C900004DA7CE2A1879C55F79CB5AC2C9533B94E
459:101CA0003105D953D6A2300B295B022E615A17E6B3
460:101CB0009CB32A7AC54021A891CE0527F3A5886454
461:101CC000C172654F58140C8D7EF381445CEF41C79F
462:101CD0003ABE02FAA9EACECCA92953D6A24647DDDC
463:101CE0007AC0A30086E29B29788B810998709B2992
464:101CF000795DD972ED94BCB976133B2A5DB29795A4
465:101D00002ED94BCA7D5B5994CA1C24EEC794BCC023
466:101D100026D3E7150C3CE2ACFE7B4A22E78A85F924
467:101D20009E59977A8D0CCBA527F3A0417262193783
468:101D3000DE70288B9C8A0E39D48D0F56366D094E75
469:101D4000BD592CCEA56B0B22D99DC9B297BEF3818C
470:101D50004A7D65A300938F672978C24DC1D1068261
471:101D600031AF07383411F3A82A9EA8661AA4A54FEC
472:101D70005A0C118FAA7BD0654945BDE962D2B19E4C
473:101D80006CCCC6198709C38E75411F3AA513D5556A
474:101D900055555555555555555555555555555555F3
475:101DA00055555555555555555555555555555555E3
476:0E1DB00055555555555555555555555ACC90C8
477:00000001FF
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 3c9b616c834a..b738f2dc38d9 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -186,7 +186,6 @@ header-y += if_pppox.h
186header-y += if_slip.h 186header-y += if_slip.h
187header-y += if_strip.h 187header-y += if_strip.h
188header-y += if_team.h 188header-y += if_team.h
189header-y += if_tr.h
190header-y += if_tun.h 189header-y += if_tun.h
191header-y += if_tunnel.h 190header-y += if_tunnel.h
192header-y += if_vlan.h 191header-y += if_vlan.h
diff --git a/include/linux/ibmtr.h b/include/linux/ibmtr.h
deleted file mode 100644
index 06695b74d405..000000000000
--- a/include/linux/ibmtr.h
+++ /dev/null
@@ -1,373 +0,0 @@
1#ifndef __LINUX_IBMTR_H__
2#define __LINUX_IBMTR_H__
3
4/* Definitions for an IBM Token Ring card. */
5/* This file is distributed under the GNU GPL */
6
7/* ported to the Alpha architecture 02/20/96 (just used the HZ macro) */
8
9#define TR_RETRY_INTERVAL (30*HZ) /* 500 on PC = 5 s */
10#define TR_RST_TIME (msecs_to_jiffies(50)) /* 5 on PC = 50 ms */
11#define TR_BUSY_INTERVAL (msecs_to_jiffies(200)) /* 5 on PC = 200 ms */
12#define TR_SPIN_INTERVAL (3*HZ) /* 3 seconds before init timeout */
13
14#define TR_ISA 1
15#define TR_MCA 2
16#define TR_ISAPNP 3
17#define NOTOK 0
18
19#define IBMTR_SHARED_RAM_SIZE 0x10000
20#define IBMTR_IO_EXTENT 4
21#define IBMTR_MAX_ADAPTERS 4
22
23#define CHANNEL_ID 0X1F30
24#define AIP 0X1F00
25#define AIPADAPTYPE 0X1FA0
26#define AIPDATARATE 0X1FA2
27#define AIPEARLYTOKEN 0X1FA4
28#define AIPAVAILSHRAM 0X1FA6
29#define AIPSHRAMPAGE 0X1FA8
30#define AIP4MBDHB 0X1FAA
31#define AIP16MBDHB 0X1FAC
32#define AIPFID 0X1FBA
33
34#define ADAPTRESET 0x1 /* Control Adapter reset (add to base) */
35#define ADAPTRESETREL 0x2 /* Release Adapter from reset ( """) */
36#define ADAPTINTREL 0x3 /* Adapter interrupt release */
37
38#define GLOBAL_INT_ENABLE 0x02f0
39
40/* MMIO bits 0-4 select register */
41#define RRR_EVEN 0x00 /* Shared RAM relocation registers - even and odd */
42/* Used to set the starting address of shared RAM */
43/* Bits 1 through 7 of this register map to bits 13 through 19 of the shared
44 RAM address.*/
45/* ie: 0x02 sets RAM address to ...ato! issy su wazzoo !! GODZILLA!!! */
46#define RRR_ODD 0x01
47/* Bits 2 and 3 of this register can be read to determine shared RAM size */
48/* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k */
49#define WRBR_EVEN 0x02 /* Write region base registers - even and odd */
50#define WRBR_ODD 0x03
51#define WWOR_EVEN 0x04 /* Write window open registers - even and odd */
52#define WWOR_ODD 0x05
53#define WWCR_EVEN 0x06 /* Write window close registers - even and odd */
54#define WWCR_ODD 0x07
55
56/* Interrupt status registers - PC system - even and odd */
57#define ISRP_EVEN 0x08
58
59#define TCR_INT 0x10 /* Bit 4 - Timer interrupt. The TVR_EVEN timer has
60 expired. */
61#define ERR_INT 0x08 /* Bit 3 - Error interrupt. The adapter has had an
62 internal error. */
63#define ACCESS_INT 0x04 /* Bit 2 - Access interrupt. You have attempted to
64 write to an invalid area of shared RAM
65 or an invalid register within the MMIO. */
66/* In addition, the following bits within ISRP_EVEN can be turned on or off */
67/* by you to control the interrupt processing: */
68#define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable. If 0, no interrupts will
69 occur. If 1, interrupts will occur normally.
70 Normally set to 1. */
71/* Bit 0 - Primary or alternate adapter. Set to zero if this adapter is the
72 primary adapter, 1 if this adapter is the alternate adapter. */
73
74
75#define ISRP_ODD 0x09
76
77#define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check. the adapter has
78 encountered a serious problem and has closed
79 itself. Whoa. */
80#define SRB_RESP_INT 0x20 /* Bit 5 - SRB response. The adapter has accepted
81 an SRB request and set the return code within
82 the SRB. */
83#define ASB_FREE_INT 0x10 /* Bit 4 - ASB free. The adapter has read the ASB
84 and this area can be safely reused. This interrupt
85 is only used if your application has set the ASB
86 free request bit in ISRA_ODD or if an error was
87 detected in your response. */
88#define ARB_CMD_INT 0x08 /* Bit 3 - ARB command. The adapter has given you a
89 command for action. The command is located in the
90 ARB area of shared memory. */
91#define SSB_RESP_INT 0x04 /* Bit 2 - SSB response. The adapter has posted a
92 response to your SRB (the response is located in
93 the SSB area of shared memory). */
94/* Bit 1 - Bridge frame forward complete. */
95
96
97
98#define ISRA_EVEN 0x0A /*Interrupt status registers - adapter - even and odd */
99/* Bit 7 - Internal parity error (on adapter's internal bus) */
100/* Bit 6 - Timer interrupt pending */
101/* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */
102/* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */
103/* Bit 3 - Adapter processor check status */
104/* Bit 2 - Reserved */
105/* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */
106/* Bit 0 - Adapter software interrupt mask (prevents internal software ints) */
107
108#define ISRA_ODD 0x0B
109#define CMD_IN_SRB 0x20 /* Bit 5 - Indicates that you have placed a new
110 command in the SRB and are ready for the adapter to
111 process the command. */
112#define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response
113 (an ASB) in the shared RAM which is available for
114 the adapter's use. */
115/* Bit 3 - Indicates that you are ready to put an SRB in the shared RAM, but
116 that a previous command is still pending. The adapter will then
117 interrupt you when the previous command is completed */
118/* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but
119 that a previous ASB is still pending. The adapter will then interrupt
120 you when the previous ASB is copied. */
121#define ARB_FREE 0x2
122#define SSB_FREE 0x1
123
124#define TCR_EVEN 0x0C /* Timer control registers - even and odd */
125#define TCR_ODD 0x0D
126#define TVR_EVEN 0x0E /* Timer value registers - even and odd */
127#define TVR_ODD 0x0F
128#define SRPR_EVEN 0x18 /* Shared RAM paging registers - even and odd */
129#define SRPR_ENABLE_PAGING 0xc0
130#define SRPR_ODD 0x19 /* Not used. */
131#define TOKREAD 0x60
132#define TOKOR 0x40
133#define TOKAND 0x20
134#define TOKWRITE 0x00
135
136/* MMIO bits 5-6 select operation */
137/* 00 is used to write to a register */
138/* 01 is used to bitwise AND a byte with a register */
139/* 10 is used to bitwise OR a byte with a register */
140/* 11 is used to read from a register */
141
142/* MMIO bits 7-8 select area of interest.. see below */
143/* 00 selects attachment control area. */
144/* 01 is reserved. */
145/* 10 selects adapter identification area A containing the adapter encoded
146 address. */
147/* 11 selects the adapter identification area B containing test patterns. */
148
149#define PCCHANNELID 5049434F3631313039393020
150#define MCCHANNELID 4D4152533633583435313820
151
152#define ACA_OFFSET 0x1e00
153#define ACA_SET 0x40
154#define ACA_RESET 0x20
155#define ACA_RW 0x00
156
157#ifdef ENABLE_PAGING
158#define SET_PAGE(x) (writeb((x), ti->mmio + ACA_OFFSET+ ACA_RW + SRPR_EVEN))
159#else
160#define SET_PAGE(x)
161#endif
162
163/* do_tok_int possible values */
164#define FIRST_INT 1
165#define NOT_FIRST 2
166
167typedef enum { CLOSED, OPEN } open_state;
168//staic const char *printstate[] = { "CLOSED","OPEN"};
169
170struct tok_info {
171 unsigned char irq;
172 void __iomem *mmio;
173 unsigned char hw_address[32];
174 unsigned char adapter_type;
175 unsigned char data_rate;
176 unsigned char token_release;
177 unsigned char avail_shared_ram;
178 unsigned char shared_ram_paging;
179 unsigned char turbo;
180 unsigned short dhb_size4mb;
181 unsigned short rbuf_len4;
182 unsigned short rbuf_cnt4;
183 unsigned short maxmtu4;
184 unsigned short dhb_size16mb;
185 unsigned short rbuf_len16;
186 unsigned short rbuf_cnt16;
187 unsigned short maxmtu16;
188 /* Additions by David Morris */
189 unsigned char do_tok_int;
190 wait_queue_head_t wait_for_reset;
191 unsigned char sram_base;
192 /* Additions by Peter De Schrijver */
193 unsigned char page_mask; /* mask to select RAM page to Map*/
194 unsigned char mapped_ram_size; /* size of RAM page */
195 __u32 sram_phys; /* Shared memory base address */
196 void __iomem *sram_virt; /* Shared memory base address */
197 void __iomem *init_srb; /* Initial System Request Block address */
198 void __iomem *srb; /* System Request Block address */
199 void __iomem *ssb; /* System Status Block address */
200 void __iomem *arb; /* Adapter Request Block address */
201 void __iomem *asb; /* Adapter Status Block address */
202 __u8 init_srb_page;
203 __u8 srb_page;
204 __u8 ssb_page;
205 __u8 arb_page;
206 __u8 asb_page;
207 unsigned short exsap_station_id;
208 unsigned short global_int_enable;
209 struct sk_buff *current_skb;
210
211 unsigned char auto_speedsave;
212 open_state open_status, sap_status;
213 enum {MANUAL, AUTOMATIC} open_mode;
214 enum {FAIL, RESTART, REOPEN} open_action;
215 enum {NO, YES} open_failure;
216 unsigned char readlog_pending;
217 unsigned short adapter_int_enable; /* Adapter-specific int enable */
218 struct timer_list tr_timer;
219 unsigned char ring_speed;
220 spinlock_t lock; /* SMP protection */
221};
222
223/* token ring adapter commands */
224#define DIR_INTERRUPT 0x00 /* struct srb_interrupt */
225#define DIR_MOD_OPEN_PARAMS 0x01
226#define DIR_OPEN_ADAPTER 0x03 /* struct dir_open_adapter */
227#define DIR_CLOSE_ADAPTER 0x04
228#define DIR_SET_GRP_ADDR 0x06
229#define DIR_SET_FUNC_ADDR 0x07 /* struct srb_set_funct_addr */
230#define DIR_READ_LOG 0x08 /* struct srb_read_log */
231#define DLC_OPEN_SAP 0x15 /* struct dlc_open_sap */
232#define DLC_CLOSE_SAP 0x16
233#define DATA_LOST 0x20 /* struct asb_rec */
234#define REC_DATA 0x81 /* struct arb_rec_req */
235#define XMIT_DATA_REQ 0x82 /* struct arb_xmit_req */
236#define DLC_STATUS 0x83 /* struct arb_dlc_status */
237#define RING_STAT_CHANGE 0x84 /* struct dlc_open_sap ??? */
238
239/* DIR_OPEN_ADAPTER options */
240#define OPEN_PASS_BCON_MAC 0x0100
241#define NUM_RCV_BUF 2
242#define RCV_BUF_LEN 1024
243#define DHB_LENGTH 2048
244#define NUM_DHB 2
245#define DLC_MAX_SAP 2
246#define DLC_MAX_STA 1
247
248/* DLC_OPEN_SAP options */
249#define MAX_I_FIELD 0x0088
250#define SAP_OPEN_IND_SAP 0x04
251#define SAP_OPEN_PRIORITY 0x20
252#define SAP_OPEN_STATION_CNT 0x1
253#define XMIT_DIR_FRAME 0x0A
254#define XMIT_UI_FRAME 0x0d
255#define XMIT_XID_CMD 0x0e
256#define XMIT_TEST_CMD 0x11
257
258/* srb close return code */
259#define SIGNAL_LOSS 0x8000
260#define HARD_ERROR 0x4000
261#define XMIT_BEACON 0x1000
262#define LOBE_FAULT 0x0800
263#define AUTO_REMOVAL 0x0400
264#define REMOVE_RECV 0x0100
265#define LOG_OVERFLOW 0x0080
266#define RING_RECOVER 0x0020
267
268struct srb_init_response {
269 unsigned char command;
270 unsigned char init_status;
271 unsigned char init_status_2;
272 unsigned char reserved[3];
273 __u16 bring_up_code;
274 __u16 encoded_address;
275 __u16 level_address;
276 __u16 adapter_address;
277 __u16 parms_address;
278 __u16 mac_address;
279};
280
281struct dir_open_adapter {
282 unsigned char command;
283 char reserved[7];
284 __u16 open_options;
285 unsigned char node_address[6];
286 unsigned char group_address[4];
287 unsigned char funct_address[4];
288 __u16 num_rcv_buf;
289 __u16 rcv_buf_len;
290 __u16 dhb_length;
291 unsigned char num_dhb;
292 char reserved2;
293 unsigned char dlc_max_sap;
294 unsigned char dlc_max_sta;
295 unsigned char dlc_max_gsap;
296 unsigned char dlc_max_gmem;
297 unsigned char dlc_t1_tick_1;
298 unsigned char dlc_t2_tick_1;
299 unsigned char dlc_ti_tick_1;
300 unsigned char dlc_t1_tick_2;
301 unsigned char dlc_t2_tick_2;
302 unsigned char dlc_ti_tick_2;
303 unsigned char product_id[18];
304};
305
306struct dlc_open_sap {
307 unsigned char command;
308 unsigned char reserved1;
309 unsigned char ret_code;
310 unsigned char reserved2;
311 __u16 station_id;
312 unsigned char timer_t1;
313 unsigned char timer_t2;
314 unsigned char timer_ti;
315 unsigned char maxout;
316 unsigned char maxin;
317 unsigned char maxout_incr;
318 unsigned char max_retry_count;
319 unsigned char gsap_max_mem;
320 __u16 max_i_field;
321 unsigned char sap_value;
322 unsigned char sap_options;
323 unsigned char station_count;
324 unsigned char sap_gsap_mem;
325 unsigned char gsap[0];
326};
327
328struct srb_xmit {
329 unsigned char command;
330 unsigned char cmd_corr;
331 unsigned char ret_code;
332 unsigned char reserved1;
333 __u16 station_id;
334};
335
336struct arb_rec_req {
337 unsigned char command;
338 unsigned char reserved1[3];
339 __u16 station_id;
340 __u16 rec_buf_addr;
341 unsigned char lan_hdr_len;
342 unsigned char dlc_hdr_len;
343 __u16 frame_len;
344 unsigned char msg_type;
345};
346
347struct asb_rec {
348 unsigned char command;
349 unsigned char reserved1;
350 unsigned char ret_code;
351 unsigned char reserved2;
352 __u16 station_id;
353 __u16 rec_buf_addr;
354};
355
356struct rec_buf {
357 unsigned char reserved1[2];
358 __u16 buf_ptr;
359 unsigned char reserved2;
360 unsigned char receive_fs;
361 __u16 buf_len;
362 unsigned char data[0];
363};
364
365struct srb_set_funct_addr {
366 unsigned char command;
367 unsigned char reserved1;
368 unsigned char ret_code;
369 unsigned char reserved2[3];
370 unsigned char funct_address[4];
371};
372
373#endif
diff --git a/include/linux/if_tr.h b/include/linux/if_tr.h
deleted file mode 100644
index fc23aeb0f201..000000000000
--- a/include/linux/if_tr.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * INET An implementation of the TCP/IP protocol suite for the LINUX
3 * operating system. INET is implemented using the BSD Socket
4 * interface as the means of communication with the user level.
5 *
6 * Global definitions for the Token-Ring IEEE 802.5 interface.
7 *
8 * Version: @(#)if_tr.h 0.0 07/11/94
9 *
10 * Author: Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
11 * Donald Becker, <becker@super.org>
12 * Peter De Schrijver, <stud11@cc4.kuleuven.ac.be>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19#ifndef _LINUX_IF_TR_H
20#define _LINUX_IF_TR_H
21
22#include <linux/types.h>
23#include <asm/byteorder.h> /* For __be16 */
24
25/* IEEE 802.5 Token-Ring magic constants. The frame sizes omit the preamble
26 and FCS/CRC (frame check sequence). */
27#define TR_ALEN 6 /* Octets in one token-ring addr */
28#define TR_HLEN (sizeof(struct trh_hdr)+sizeof(struct trllc))
29#define AC 0x10
30#define LLC_FRAME 0x40
31
32/* LLC and SNAP constants */
33#define EXTENDED_SAP 0xAA
34#define UI_CMD 0x03
35
36/* This is an Token-Ring frame header. */
37struct trh_hdr {
38 __u8 ac; /* access control field */
39 __u8 fc; /* frame control field */
40 __u8 daddr[TR_ALEN]; /* destination address */
41 __u8 saddr[TR_ALEN]; /* source address */
42 __be16 rcf; /* route control field */
43 __be16 rseg[8]; /* routing registers */
44};
45
46#ifdef __KERNEL__
47#include <linux/skbuff.h>
48
49static inline struct trh_hdr *tr_hdr(const struct sk_buff *skb)
50{
51 return (struct trh_hdr *)skb_mac_header(skb);
52}
53#endif
54
55/* This is an Token-Ring LLC structure */
56struct trllc {
57 __u8 dsap; /* destination SAP */
58 __u8 ssap; /* source SAP */
59 __u8 llc; /* LLC control field */
60 __u8 protid[3]; /* protocol id */
61 __be16 ethertype; /* ether type field */
62};
63
64/* Token-Ring statistics collection data. */
65struct tr_statistics {
66 unsigned long rx_packets; /* total packets received */
67 unsigned long tx_packets; /* total packets transmitted */
68 unsigned long rx_bytes; /* total bytes received */
69 unsigned long tx_bytes; /* total bytes transmitted */
70 unsigned long rx_errors; /* bad packets received */
71 unsigned long tx_errors; /* packet transmit problems */
72 unsigned long rx_dropped; /* no space in linux buffers */
73 unsigned long tx_dropped; /* no space available in linux */
74 unsigned long multicast; /* multicast packets received */
75 unsigned long transmit_collision;
76
77 /* detailed Token-Ring errors. See IBM Token-Ring Network
78 Architecture for more info */
79
80 unsigned long line_errors;
81 unsigned long internal_errors;
82 unsigned long burst_errors;
83 unsigned long A_C_errors;
84 unsigned long abort_delimiters;
85 unsigned long lost_frames;
86 unsigned long recv_congest_count;
87 unsigned long frame_copied_errors;
88 unsigned long frequency_errors;
89 unsigned long token_errors;
90 unsigned long dummy1;
91};
92
93/* source routing stuff */
94#define TR_RII 0x80
95#define TR_RCF_DIR_BIT 0x80
96#define TR_RCF_LEN_MASK 0x1f00
97#define TR_RCF_BROADCAST 0x8000 /* all-routes broadcast */
98#define TR_RCF_LIMITED_BROADCAST 0xC000 /* single-route broadcast */
99#define TR_RCF_FRAME2K 0x20
100#define TR_RCF_BROADCAST_MASK 0xC000
101#define TR_MAXRIFLEN 18
102
103#endif /* _LINUX_IF_TR_H */
diff --git a/include/linux/trdevice.h b/include/linux/trdevice.h
deleted file mode 100644
index bfc84a7aecc5..000000000000
--- a/include/linux/trdevice.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * INET An implementation of the TCP/IP protocol suite for the LINUX
3 * operating system. NET is implemented using the BSD Socket
4 * interface as the means of communication with the user level.
5 *
6 * Definitions for the Token-ring handlers.
7 *
8 * Version: @(#)eth.h 1.0.4 05/13/93
9 *
10 * Authors: Ross Biro
11 * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
12 *
13 * Relocated to include/linux where it belongs by Alan Cox
14 * <gw4pts@gw4pts.ampr.org>
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
20 *
21 * WARNING: This move may well be temporary. This file will get merged with others RSN.
22 *
23 */
24#ifndef _LINUX_TRDEVICE_H
25#define _LINUX_TRDEVICE_H
26
27
28#include <linux/if_tr.h>
29
30#ifdef __KERNEL__
31extern __be16 tr_type_trans(struct sk_buff *skb, struct net_device *dev);
32extern void tr_source_route(struct sk_buff *skb, struct trh_hdr *trh, struct net_device *dev);
33extern struct net_device *alloc_trdev(int sizeof_priv);
34
35#endif
36
37#endif /* _LINUX_TRDEVICE_H */
diff --git a/net/802/Makefile b/net/802/Makefile
index 7893d679910c..a30d6e385aed 100644
--- a/net/802/Makefile
+++ b/net/802/Makefile
@@ -4,7 +4,6 @@
4 4
5# Check the p8022 selections against net/core/Makefile. 5# Check the p8022 selections against net/core/Makefile.
6obj-$(CONFIG_LLC) += p8022.o psnap.o 6obj-$(CONFIG_LLC) += p8022.o psnap.o
7obj-$(CONFIG_TR) += p8022.o psnap.o tr.o
8obj-$(CONFIG_NET_FC) += fc.o 7obj-$(CONFIG_NET_FC) += fc.o
9obj-$(CONFIG_FDDI) += fddi.o 8obj-$(CONFIG_FDDI) += fddi.o
10obj-$(CONFIG_HIPPI) += hippi.o 9obj-$(CONFIG_HIPPI) += hippi.o
diff --git a/net/802/tr.c b/net/802/tr.c
deleted file mode 100644
index 175243b0d6d8..000000000000
--- a/net/802/tr.c
+++ /dev/null
@@ -1,669 +0,0 @@
1/*
2 * NET3: Token ring device handling subroutines
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Fixes: 3 Feb 97 Paul Norton <pnorton@cts.com> Minor routing fixes.
10 * Added rif table to /proc/net/tr_rif and rif timeout to
11 * /proc/sys/net/token-ring/rif_timeout.
12 * 22 Jun 98 Paul Norton <p.norton@computer.org> Rearranged
13 * tr_header and tr_type_trans to handle passing IPX SNAP and
14 * 802.2 through the correct layers. Eliminated tr_reformat.
15 *
16 */
17
18#include <asm/uaccess.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/kernel.h>
22#include <linux/jiffies.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/socket.h>
26#include <linux/in.h>
27#include <linux/inet.h>
28#include <linux/netdevice.h>
29#include <linux/trdevice.h>
30#include <linux/skbuff.h>
31#include <linux/errno.h>
32#include <linux/timer.h>
33#include <linux/net.h>
34#include <linux/proc_fs.h>
35#include <linux/seq_file.h>
36#include <linux/init.h>
37#include <linux/sysctl.h>
38#include <linux/slab.h>
39#include <net/arp.h>
40#include <net/net_namespace.h>
41
42static void tr_add_rif_info(struct trh_hdr *trh, struct net_device *dev);
43static void rif_check_expire(unsigned long dummy);
44
45#define TR_SR_DEBUG 0
46
47/*
48 * Each RIF entry we learn is kept this way
49 */
50
51struct rif_cache {
52 unsigned char addr[TR_ALEN];
53 int iface;
54 __be16 rcf;
55 __be16 rseg[8];
56 struct rif_cache *next;
57 unsigned long last_used;
58 unsigned char local_ring;
59};
60
61#define RIF_TABLE_SIZE 32
62
63/*
64 * We hash the RIF cache 32 ways. We do after all have to look it
65 * up a lot.
66 */
67
68static struct rif_cache *rif_table[RIF_TABLE_SIZE];
69
70static DEFINE_SPINLOCK(rif_lock);
71
72
73/*
74 * Garbage disposal timer.
75 */
76
77static struct timer_list rif_timer;
78
79static int sysctl_tr_rif_timeout = 60*10*HZ;
80
81static inline unsigned long rif_hash(const unsigned char *addr)
82{
83 unsigned long x;
84
85 x = addr[0];
86 x = (x << 2) ^ addr[1];
87 x = (x << 2) ^ addr[2];
88 x = (x << 2) ^ addr[3];
89 x = (x << 2) ^ addr[4];
90 x = (x << 2) ^ addr[5];
91
92 x ^= x >> 8;
93
94 return x & (RIF_TABLE_SIZE - 1);
95}
96
97/*
98 * Put the headers on a token ring packet. Token ring source routing
99 * makes this a little more exciting than on ethernet.
100 */
101
102static int tr_header(struct sk_buff *skb, struct net_device *dev,
103 unsigned short type,
104 const void *daddr, const void *saddr, unsigned int len)
105{
106 struct trh_hdr *trh;
107 int hdr_len;
108
109 /*
110 * Add the 802.2 SNAP header if IP as the IPv4/IPv6 code calls
111 * dev->hard_header directly.
112 */
113 if (type == ETH_P_IP || type == ETH_P_IPV6 || type == ETH_P_ARP)
114 {
115 struct trllc *trllc;
116
117 hdr_len = sizeof(struct trh_hdr) + sizeof(struct trllc);
118 trh = (struct trh_hdr *)skb_push(skb, hdr_len);
119 trllc = (struct trllc *)(trh+1);
120 trllc->dsap = trllc->ssap = EXTENDED_SAP;
121 trllc->llc = UI_CMD;
122 trllc->protid[0] = trllc->protid[1] = trllc->protid[2] = 0x00;
123 trllc->ethertype = htons(type);
124 }
125 else
126 {
127 hdr_len = sizeof(struct trh_hdr);
128 trh = (struct trh_hdr *)skb_push(skb, hdr_len);
129 }
130
131 trh->ac=AC;
132 trh->fc=LLC_FRAME;
133
134 if(saddr)
135 memcpy(trh->saddr,saddr,dev->addr_len);
136 else
137 memcpy(trh->saddr,dev->dev_addr,dev->addr_len);
138
139 /*
140 * Build the destination and then source route the frame
141 */
142
143 if(daddr)
144 {
145 memcpy(trh->daddr,daddr,dev->addr_len);
146 tr_source_route(skb, trh, dev);
147 return hdr_len;
148 }
149
150 return -hdr_len;
151}
152
153/*
154 * A neighbour discovery of some species (eg arp) has completed. We
155 * can now send the packet.
156 */
157
158static int tr_rebuild_header(struct sk_buff *skb)
159{
160 struct trh_hdr *trh=(struct trh_hdr *)skb->data;
161 struct trllc *trllc=(struct trllc *)(skb->data+sizeof(struct trh_hdr));
162 struct net_device *dev = skb->dev;
163
164 /*
165 * FIXME: We don't yet support IPv6 over token rings
166 */
167
168 if(trllc->ethertype != htons(ETH_P_IP)) {
169 printk("tr_rebuild_header: Don't know how to resolve type %04X addresses ?\n", ntohs(trllc->ethertype));
170 return 0;
171 }
172
173#ifdef CONFIG_INET
174 if(arp_find(trh->daddr, skb)) {
175 return 1;
176 }
177 else
178#endif
179 {
180 tr_source_route(skb,trh,dev);
181 return 0;
182 }
183}
184
185/*
186 * Some of this is a bit hackish. We intercept RIF information
187 * used for source routing. We also grab IP directly and don't feed
188 * it via SNAP.
189 */
190
191__be16 tr_type_trans(struct sk_buff *skb, struct net_device *dev)
192{
193
194 struct trh_hdr *trh;
195 struct trllc *trllc;
196 unsigned int riflen=0;
197
198 skb->dev = dev;
199 skb_reset_mac_header(skb);
200 trh = tr_hdr(skb);
201
202 if(trh->saddr[0] & TR_RII)
203 riflen = (ntohs(trh->rcf) & TR_RCF_LEN_MASK) >> 8;
204
205 trllc = (struct trllc *)(skb->data+sizeof(struct trh_hdr)-TR_MAXRIFLEN+riflen);
206
207 skb_pull(skb,sizeof(struct trh_hdr)-TR_MAXRIFLEN+riflen);
208
209 if(*trh->daddr & 0x80)
210 {
211 if(!memcmp(trh->daddr,dev->broadcast,TR_ALEN))
212 skb->pkt_type=PACKET_BROADCAST;
213 else
214 skb->pkt_type=PACKET_MULTICAST;
215 }
216 else if ( (trh->daddr[0] & 0x01) && (trh->daddr[1] & 0x00) && (trh->daddr[2] & 0x5E))
217 {
218 skb->pkt_type=PACKET_MULTICAST;
219 }
220 else if(dev->flags & IFF_PROMISC)
221 {
222 if(memcmp(trh->daddr, dev->dev_addr, TR_ALEN))
223 skb->pkt_type=PACKET_OTHERHOST;
224 }
225
226 if ((skb->pkt_type != PACKET_BROADCAST) &&
227 (skb->pkt_type != PACKET_MULTICAST))
228 tr_add_rif_info(trh,dev) ;
229
230 /*
231 * Strip the SNAP header from ARP packets since we don't
232 * pass them through to the 802.2/SNAP layers.
233 */
234
235 if (trllc->dsap == EXTENDED_SAP &&
236 (trllc->ethertype == htons(ETH_P_IP) ||
237 trllc->ethertype == htons(ETH_P_IPV6) ||
238 trllc->ethertype == htons(ETH_P_ARP)))
239 {
240 skb_pull(skb, sizeof(struct trllc));
241 return trllc->ethertype;
242 }
243
244 return htons(ETH_P_TR_802_2);
245}
246
247/*
248 * We try to do source routing...
249 */
250
251void tr_source_route(struct sk_buff *skb,struct trh_hdr *trh,
252 struct net_device *dev)
253{
254 int slack;
255 unsigned int hash;
256 struct rif_cache *entry;
257 unsigned char *olddata;
258 unsigned long flags;
259 static const unsigned char mcast_func_addr[]
260 = {0xC0,0x00,0x00,0x04,0x00,0x00};
261
262 spin_lock_irqsave(&rif_lock, flags);
263
264 /*
265 * Broadcasts are single route as stated in RFC 1042
266 */
267 if( (!memcmp(&(trh->daddr[0]),&(dev->broadcast[0]),TR_ALEN)) ||
268 (!memcmp(&(trh->daddr[0]),&(mcast_func_addr[0]), TR_ALEN)) )
269 {
270 trh->rcf=htons((((sizeof(trh->rcf)) << 8) & TR_RCF_LEN_MASK)
271 | TR_RCF_FRAME2K | TR_RCF_LIMITED_BROADCAST);
272 trh->saddr[0]|=TR_RII;
273 }
274 else
275 {
276 hash = rif_hash(trh->daddr);
277 /*
278 * Walk the hash table and look for an entry
279 */
280 for(entry=rif_table[hash];entry && memcmp(&(entry->addr[0]),&(trh->daddr[0]),TR_ALEN);entry=entry->next);
281
282 /*
283 * If we found an entry we can route the frame.
284 */
285 if(entry)
286 {
287#if TR_SR_DEBUG
288printk("source routing for %pM\n", trh->daddr);
289#endif
290 if(!entry->local_ring && (ntohs(entry->rcf) & TR_RCF_LEN_MASK) >> 8)
291 {
292 trh->rcf=entry->rcf;
293 memcpy(&trh->rseg[0],&entry->rseg[0],8*sizeof(unsigned short));
294 trh->rcf^=htons(TR_RCF_DIR_BIT);
295 trh->rcf&=htons(0x1fff); /* Issam Chehab <ichehab@madge1.demon.co.uk> */
296
297 trh->saddr[0]|=TR_RII;
298#if TR_SR_DEBUG
299 printk("entry found with rcf %04x\n", entry->rcf);
300 }
301 else
302 {
303 printk("entry found but without rcf length, local=%02x\n", entry->local_ring);
304#endif
305 }
306 entry->last_used=jiffies;
307 }
308 else
309 {
310 /*
311 * Without the information we simply have to shout
312 * on the wire. The replies should rapidly clean this
313 * situation up.
314 */
315 trh->rcf=htons((((sizeof(trh->rcf)) << 8) & TR_RCF_LEN_MASK)
316 | TR_RCF_FRAME2K | TR_RCF_LIMITED_BROADCAST);
317 trh->saddr[0]|=TR_RII;
318#if TR_SR_DEBUG
319 printk("no entry in rif table found - broadcasting frame\n");
320#endif
321 }
322 }
323
324 /* Compress the RIF here so we don't have to do it in the driver(s) */
325 if (!(trh->saddr[0] & 0x80))
326 slack = 18;
327 else
328 slack = 18 - ((ntohs(trh->rcf) & TR_RCF_LEN_MASK)>>8);
329 olddata = skb->data;
330 spin_unlock_irqrestore(&rif_lock, flags);
331
332 skb_pull(skb, slack);
333 memmove(skb->data, olddata, sizeof(struct trh_hdr) - slack);
334}
335
336/*
337 * We have learned some new RIF information for our source
338 * routing.
339 */
340
341static void tr_add_rif_info(struct trh_hdr *trh, struct net_device *dev)
342{
343 unsigned int hash, rii_p = 0;
344 unsigned long flags;
345 struct rif_cache *entry;
346 unsigned char saddr0;
347
348 spin_lock_irqsave(&rif_lock, flags);
349 saddr0 = trh->saddr[0];
350
351 /*
352 * Firstly see if the entry exists
353 */
354
355 if(trh->saddr[0] & TR_RII)
356 {
357 trh->saddr[0]&=0x7f;
358 if (((ntohs(trh->rcf) & TR_RCF_LEN_MASK) >> 8) > 2)
359 {
360 rii_p = 1;
361 }
362 }
363
364 hash = rif_hash(trh->saddr);
365 for(entry=rif_table[hash];entry && memcmp(&(entry->addr[0]),&(trh->saddr[0]),TR_ALEN);entry=entry->next);
366
367 if(entry==NULL)
368 {
369#if TR_SR_DEBUG
370 printk("adding rif_entry: addr:%pM rcf:%04X\n",
371 trh->saddr, ntohs(trh->rcf));
372#endif
373 /*
374 * Allocate our new entry. A failure to allocate loses
375 * use the information. This is harmless.
376 *
377 * FIXME: We ought to keep some kind of cache size
378 * limiting and adjust the timers to suit.
379 */
380 entry=kmalloc(sizeof(struct rif_cache),GFP_ATOMIC);
381
382 if(!entry)
383 {
384 printk(KERN_DEBUG "tr.c: Couldn't malloc rif cache entry !\n");
385 spin_unlock_irqrestore(&rif_lock, flags);
386 return;
387 }
388
389 memcpy(&(entry->addr[0]),&(trh->saddr[0]),TR_ALEN);
390 entry->iface = dev->ifindex;
391 entry->next=rif_table[hash];
392 entry->last_used=jiffies;
393 rif_table[hash]=entry;
394
395 if (rii_p)
396 {
397 entry->rcf = trh->rcf & htons((unsigned short)~TR_RCF_BROADCAST_MASK);
398 memcpy(&(entry->rseg[0]),&(trh->rseg[0]),8*sizeof(unsigned short));
399 entry->local_ring = 0;
400 }
401 else
402 {
403 entry->local_ring = 1;
404 }
405 }
406 else /* Y. Tahara added */
407 {
408 /*
409 * Update existing entries
410 */
411 if (!entry->local_ring)
412 if (entry->rcf != (trh->rcf & htons((unsigned short)~TR_RCF_BROADCAST_MASK)) &&
413 !(trh->rcf & htons(TR_RCF_BROADCAST_MASK)))
414 {
415#if TR_SR_DEBUG
416printk("updating rif_entry: addr:%pM rcf:%04X\n",
417 trh->saddr, ntohs(trh->rcf));
418#endif
419 entry->rcf = trh->rcf & htons((unsigned short)~TR_RCF_BROADCAST_MASK);
420 memcpy(&(entry->rseg[0]),&(trh->rseg[0]),8*sizeof(unsigned short));
421 }
422 entry->last_used=jiffies;
423 }
424 trh->saddr[0]=saddr0; /* put the routing indicator back for tcpdump */
425 spin_unlock_irqrestore(&rif_lock, flags);
426}
427
428/*
429 * Scan the cache with a timer and see what we need to throw out.
430 */
431
432static void rif_check_expire(unsigned long dummy)
433{
434 int i;
435 unsigned long flags, next_interval = jiffies + sysctl_tr_rif_timeout/2;
436
437 spin_lock_irqsave(&rif_lock, flags);
438
439 for(i =0; i < RIF_TABLE_SIZE; i++) {
440 struct rif_cache *entry, **pentry;
441
442 pentry = rif_table+i;
443 while((entry=*pentry) != NULL) {
444 unsigned long expires
445 = entry->last_used + sysctl_tr_rif_timeout;
446
447 if (time_before_eq(expires, jiffies)) {
448 *pentry = entry->next;
449 kfree(entry);
450 } else {
451 pentry = &entry->next;
452
453 if (time_before(expires, next_interval))
454 next_interval = expires;
455 }
456 }
457 }
458
459 spin_unlock_irqrestore(&rif_lock, flags);
460
461 mod_timer(&rif_timer, next_interval);
462
463}
464
465/*
466 * Generate the /proc/net information for the token ring RIF
467 * routing.
468 */
469
470#ifdef CONFIG_PROC_FS
471
472static struct rif_cache *rif_get_idx(loff_t pos)
473{
474 int i;
475 struct rif_cache *entry;
476 loff_t off = 0;
477
478 for(i = 0; i < RIF_TABLE_SIZE; i++)
479 for(entry = rif_table[i]; entry; entry = entry->next) {
480 if (off == pos)
481 return entry;
482 ++off;
483 }
484
485 return NULL;
486}
487
488static void *rif_seq_start(struct seq_file *seq, loff_t *pos)
489 __acquires(&rif_lock)
490{
491 spin_lock_irq(&rif_lock);
492
493 return *pos ? rif_get_idx(*pos - 1) : SEQ_START_TOKEN;
494}
495
496static void *rif_seq_next(struct seq_file *seq, void *v, loff_t *pos)
497{
498 int i;
499 struct rif_cache *ent = v;
500
501 ++*pos;
502
503 if (v == SEQ_START_TOKEN) {
504 i = -1;
505 goto scan;
506 }
507
508 if (ent->next)
509 return ent->next;
510
511 i = rif_hash(ent->addr);
512 scan:
513 while (++i < RIF_TABLE_SIZE) {
514 if ((ent = rif_table[i]) != NULL)
515 return ent;
516 }
517 return NULL;
518}
519
520static void rif_seq_stop(struct seq_file *seq, void *v)
521 __releases(&rif_lock)
522{
523 spin_unlock_irq(&rif_lock);
524}
525
526static int rif_seq_show(struct seq_file *seq, void *v)
527{
528 int j, rcf_len, segment, brdgnmb;
529 struct rif_cache *entry = v;
530
531 if (v == SEQ_START_TOKEN)
532 seq_puts(seq,
533 "if TR address TTL rcf routing segments\n");
534 else {
535 struct net_device *dev = dev_get_by_index(&init_net, entry->iface);
536 long ttl = (long) (entry->last_used + sysctl_tr_rif_timeout)
537 - (long) jiffies;
538
539 seq_printf(seq, "%s %pM %7li ",
540 dev?dev->name:"?",
541 entry->addr,
542 ttl/HZ);
543
544 if (entry->local_ring)
545 seq_puts(seq, "local\n");
546 else {
547
548 seq_printf(seq, "%04X", ntohs(entry->rcf));
549 rcf_len = ((ntohs(entry->rcf) & TR_RCF_LEN_MASK)>>8)-2;
550 if (rcf_len)
551 rcf_len >>= 1;
552 for(j = 1; j < rcf_len; j++) {
553 if(j==1) {
554 segment=ntohs(entry->rseg[j-1])>>4;
555 seq_printf(seq," %03X",segment);
556 }
557
558 segment=ntohs(entry->rseg[j])>>4;
559 brdgnmb=ntohs(entry->rseg[j-1])&0x00f;
560 seq_printf(seq,"-%01X-%03X",brdgnmb,segment);
561 }
562 seq_putc(seq, '\n');
563 }
564
565 if (dev)
566 dev_put(dev);
567 }
568 return 0;
569}
570
571
572static const struct seq_operations rif_seq_ops = {
573 .start = rif_seq_start,
574 .next = rif_seq_next,
575 .stop = rif_seq_stop,
576 .show = rif_seq_show,
577};
578
579static int rif_seq_open(struct inode *inode, struct file *file)
580{
581 return seq_open(file, &rif_seq_ops);
582}
583
584static const struct file_operations rif_seq_fops = {
585 .owner = THIS_MODULE,
586 .open = rif_seq_open,
587 .read = seq_read,
588 .llseek = seq_lseek,
589 .release = seq_release,
590};
591
592#endif
593
594static const struct header_ops tr_header_ops = {
595 .create = tr_header,
596 .rebuild= tr_rebuild_header,
597};
598
599static void tr_setup(struct net_device *dev)
600{
601 /*
602 * Configure and register
603 */
604
605 dev->header_ops = &tr_header_ops;
606
607 dev->hard_header_len = TR_HLEN;
608 dev->mtu = 2000;
609 dev->addr_len = TR_ALEN;
610 dev->tx_queue_len = 100; /* Long queues on tr */
611
612 memset(dev->broadcast,0xFF, TR_ALEN);
613
614 /* New-style flags. */
615 dev->flags = IFF_BROADCAST | IFF_MULTICAST ;
616}
617
618/**
619 * alloc_trdev - Register token ring device
620 * @sizeof_priv: Size of additional driver-private structure to be allocated
621 * for this token ring device
622 *
623 * Fill in the fields of the device structure with token ring-generic values.
624 *
625 * Constructs a new net device, complete with a private data area of
626 * size @sizeof_priv. A 32-byte (not bit) alignment is enforced for
627 * this private data area.
628 */
629struct net_device *alloc_trdev(int sizeof_priv)
630{
631 return alloc_netdev(sizeof_priv, "tr%d", tr_setup);
632}
633
634#ifdef CONFIG_SYSCTL
635static struct ctl_table tr_table[] = {
636 {
637 .procname = "rif_timeout",
638 .data = &sysctl_tr_rif_timeout,
639 .maxlen = sizeof(int),
640 .mode = 0644,
641 .proc_handler = proc_dointvec
642 },
643 { },
644};
645#endif
646
647/*
648 * Called during bootup. We don't actually have to initialise
649 * too much for this.
650 */
651
652static int __init rif_init(void)
653{
654 rif_timer.expires = jiffies + sysctl_tr_rif_timeout;
655 setup_timer(&rif_timer, rif_check_expire, 0);
656 add_timer(&rif_timer);
657#ifdef CONFIG_SYSCTL
658 register_net_sysctl(&init_net, "net/token-ring", tr_table);
659#endif
660 proc_net_fops_create(&init_net, "tr_rif", S_IRUGO, &rif_seq_fops);
661 return 0;
662}
663
664module_init(rif_init);
665
666EXPORT_SYMBOL(tr_type_trans);
667EXPORT_SYMBOL(alloc_trdev);
668
669MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 00:39:52 -0500