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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-iop13xx/include/mach/io.h28
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iop13xx.h22
-rw-r--r--arch/arm/mach-iop13xx/pci.c37
-rw-r--r--arch/arm/mach-iop13xx/setup.c10
5 files changed, 16 insertions, 82 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e542f99091ac..c61e0a41d799 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -486,7 +486,6 @@ config ARCH_IOP13XX
486 select PCI 486 select PCI
487 select ARCH_SUPPORTS_MSI 487 select ARCH_SUPPORTS_MSI
488 select VMSPLIT_1G 488 select VMSPLIT_1G
489 select NEED_MACH_IO_H
490 select NEED_MACH_MEMORY_H 489 select NEED_MACH_MEMORY_H
491 select NEED_RET_TO_USER 490 select NEED_RET_TO_USER
492 help 491 help
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index e197cb8994ac..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#include <mach/iop13xx.h>
23
24#define IO_SPACE_LIMIT (IOP13XX_PCIE_IO_WINDOW_SIZE + IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
25
26#define __io(a) (IOP13XX_PCIX_LOWER_IO_VA + ((a) & IO_SPACE_LIMIT))
27
28#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index d3777dbc2e8b..e10e101645dd 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,19 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window 69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
70 * 70 *
71 * IO MAP 71 * IO MAP
72 * 0x1000 + 64K 0x0.fffb.1000 0xfed6.1000 PCIX outbound i/o window 72 * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
73 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window 73 * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
74 */ 74 */
75#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
76#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL 75#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
77#define IOP13XX_PCIX_LOWER_IO_VA 0xfed60000UL
78#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ 76#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
79#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
80#define IOP13XX_PCIX_UPPER_IO_BA (IOP13XX_PCIX_LOWER_IO_BA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
83 (IOP13XX_PCIX_LOWER_IO_PA\
84 - IOP13XX_PCIX_LOWER_IO_VA))
85 77
86#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL 78#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
87#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL 79#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
@@ -101,16 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
101 IOP13XX_PCIX_LOWER_MEM_BA) 93 IOP13XX_PCIX_LOWER_MEM_BA)
102 94
103/* PCI-E ranges */ 95/* PCI-E ranges */
104#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
105#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL 96#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
106#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL 97#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
107#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
108#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
109#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
110 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
111#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
112 (IOP13XX_PCIE_LOWER_IO_PA\
113 - IOP13XX_PCIE_LOWER_IO_VA))
114 98
115#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL 99#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
116#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL 100#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 1bb905adb3dd..91f731a2957b 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -970,7 +970,6 @@ void __init iop13xx_pci_init(void)
970 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); 970 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
971 971
972 /* Setup the Min Address for PCI memory... */ 972 /* Setup the Min Address for PCI memory... */
973 pcibios_min_io = 0;
974 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 973 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
975 974
976 /* if Linux is given control of an ATU 975 /* if Linux is given control of an ATU
@@ -1003,7 +1002,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1003 if (nr > 1) 1002 if (nr > 1)
1004 return 0; 1003 return 0;
1005 1004
1006 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); 1005 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1007 if (!res) 1006 if (!res)
1008 panic("PCI: unable to alloc resources"); 1007 panic("PCI: unable to alloc resources");
1009 1008
@@ -1042,17 +1041,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1042 << IOP13XX_ATUX_PCIXSR_FUNC_NUM; 1041 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1043 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); 1042 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1044 1043
1045 res[0].start = IOP13XX_PCIX_LOWER_IO_BA + IOP13XX_PCIX_IO_BUS_OFFSET; 1044 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1046 res[0].end = IOP13XX_PCIX_UPPER_IO_BA;
1047 res[0].name = "IQ81340 ATUX PCI I/O Space";
1048 res[0].flags = IORESOURCE_IO;
1049 1045
1050 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; 1046 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1051 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; 1047 res->end = IOP13XX_PCIX_UPPER_MEM_RA;
1052 res[1].name = "IQ81340 ATUX PCI Memory Space"; 1048 res->name = "IQ81340 ATUX PCI Memory Space";
1053 res[1].flags = IORESOURCE_MEM; 1049 res->flags = IORESOURCE_MEM;
1054 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; 1050 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1055 sys->io_offset = IOP13XX_PCIX_LOWER_IO_BA;
1056 break; 1051 break;
1057 case IOP13XX_INIT_ATU_ATUE: 1052 case IOP13XX_INIT_ATU_ATUE:
1058 /* Note: the function number field in the PCSR is ro */ 1053 /* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1058,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1063 1058
1064 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); 1059 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1065 1060
1066 res[0].start = IOP13XX_PCIE_LOWER_IO_BA + IOP13XX_PCIE_IO_BUS_OFFSET; 1061 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1067 res[0].end = IOP13XX_PCIE_UPPER_IO_BA;
1068 res[0].name = "IQ81340 ATUE PCI I/O Space";
1069 res[0].flags = IORESOURCE_IO;
1070 1062
1071 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; 1063 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1072 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; 1064 res->end = IOP13XX_PCIE_UPPER_MEM_RA;
1073 res[1].name = "IQ81340 ATUE PCI Memory Space"; 1065 res->name = "IQ81340 ATUE PCI Memory Space";
1074 res[1].flags = IORESOURCE_MEM; 1066 res->flags = IORESOURCE_MEM;
1075 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; 1067 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1076 sys->io_offset = IOP13XX_PCIE_LOWER_IO_BA;
1077 sys->map_irq = iop13xx_pcie_map_irq; 1068 sys->map_irq = iop13xx_pcie_map_irq;
1078 break; 1069 break;
1079 default: 1070 default:
@@ -1081,11 +1072,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1081 return 0; 1072 return 0;
1082 } 1073 }
1083 1074
1084 request_resource(&ioport_resource, &res[0]); 1075 request_resource(&iomem_resource, res);
1085 request_resource(&iomem_resource, &res[1]);
1086 1076
1087 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 1077 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1088 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
1089 1078
1090 return 1; 1079 return 1;
1091} 1080}
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1fa6c2c..4a7f20d7fb6e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -40,16 +40,6 @@ static struct map_desc iop13xx_std_desc[] __initdata = {
40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), 40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
41 .length = IOP13XX_PMMR_SIZE, 41 .length = IOP13XX_PMMR_SIZE,
42 .type = MT_DEVICE, 42 .type = MT_DEVICE,
43 }, { /* PCIE IO space */
44 .virtual = IOP13XX_PCIE_LOWER_IO_VA,
45 .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
46 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
47 .type = MT_DEVICE,
48 }, { /* PCIX IO space */
49 .virtual = IOP13XX_PCIX_LOWER_IO_VA,
50 .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
51 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
52 .type = MT_DEVICE,
53 }, 43 },
54}; 44};
55 45
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 11:01:54 -0500