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-rw-r--r--arch/powerpc/boot/dts/a3m071.dts6
-rw-r--r--arch/powerpc/boot/dts/a4m072.dts27
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts6
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts14
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts23
-rw-r--r--arch/powerpc/boot/dts/media5200.dts6
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts26
-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi410
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts319
-rw-r--r--arch/powerpc/boot/dts/mpc5200b.dtsi25
-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts48
-rw-r--r--arch/powerpc/boot/dts/o2d.dtsi27
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts48
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts45
-rw-r--r--arch/powerpc/boot/dts/pdm360ng.dts273
-rw-r--r--arch/powerpc/boot/dts/uc101.dts52
-rw-r--r--arch/powerpc/include/asm/mpc5121.h17
-rw-r--r--arch/powerpc/platforms/512x/clock.c34
-rw-r--r--arch/powerpc/platforms/512x/mpc512x_shared.c32
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c6
-rw-r--r--arch/powerpc/platforms/Kconfig2
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/mpc5xxx_clocks.c4
-rw-r--r--drivers/Makefile2
-rw-r--r--drivers/ata/pata_mpc52xx.c6
-rw-r--r--drivers/dma/Kconfig2
-rw-r--r--drivers/dma/Makefile1
-rw-r--r--drivers/dma/bestcomm/Kconfig (renamed from arch/powerpc/sysdev/bestcomm/Kconfig)0
-rw-r--r--drivers/dma/bestcomm/Makefile (renamed from arch/powerpc/sysdev/bestcomm/Makefile)0
-rw-r--r--drivers/dma/bestcomm/ata.c (renamed from arch/powerpc/sysdev/bestcomm/ata.c)6
-rw-r--r--drivers/dma/bestcomm/bcom_ata_task.c (renamed from arch/powerpc/sysdev/bestcomm/bcom_ata_task.c)0
-rw-r--r--drivers/dma/bestcomm/bcom_fec_rx_task.c (renamed from arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c)0
-rw-r--r--drivers/dma/bestcomm/bcom_fec_tx_task.c (renamed from arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c)0
-rw-r--r--drivers/dma/bestcomm/bcom_gen_bd_rx_task.c (renamed from arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c)0
-rw-r--r--drivers/dma/bestcomm/bcom_gen_bd_tx_task.c (renamed from arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c)0
-rw-r--r--drivers/dma/bestcomm/bestcomm.c (renamed from arch/powerpc/sysdev/bestcomm/bestcomm.c)6
-rw-r--r--drivers/dma/bestcomm/fec.c (renamed from arch/powerpc/sysdev/bestcomm/fec.c)6
-rw-r--r--drivers/dma/bestcomm/gen_bd.c (renamed from arch/powerpc/sysdev/bestcomm/gen_bd.c)6
-rw-r--r--drivers/dma/bestcomm/sram.c (renamed from arch/powerpc/sysdev/bestcomm/sram.c)2
-rw-r--r--drivers/net/ethernet/freescale/fec_mpc52xx.c4
-rw-r--r--drivers/video/fsl-diu-fb.c64
-rw-r--r--include/linux/fsl/bestcomm/ata.h (renamed from arch/powerpc/sysdev/bestcomm/ata.h)0
-rw-r--r--include/linux/fsl/bestcomm/bestcomm.h (renamed from arch/powerpc/sysdev/bestcomm/bestcomm.h)0
-rw-r--r--include/linux/fsl/bestcomm/bestcomm_priv.h (renamed from arch/powerpc/sysdev/bestcomm/bestcomm_priv.h)0
-rw-r--r--include/linux/fsl/bestcomm/fec.h (renamed from arch/powerpc/sysdev/bestcomm/fec.h)0
-rw-r--r--include/linux/fsl/bestcomm/gen_bd.h (renamed from arch/powerpc/sysdev/bestcomm/gen_bd.h)0
-rw-r--r--include/linux/fsl/bestcomm/sram.h (renamed from arch/powerpc/sysdev/bestcomm/sram.h)0
-rw-r--r--sound/soc/fsl/mpc5200_dma.c4
48 files changed, 716 insertions, 844 deletions
diff --git a/arch/powerpc/boot/dts/a3m071.dts b/arch/powerpc/boot/dts/a3m071.dts
index 877a28cb77e4..bf81b8f9704c 100644
--- a/arch/powerpc/boot/dts/a3m071.dts
+++ b/arch/powerpc/boot/dts/a3m071.dts
@@ -17,6 +17,8 @@
17 17
18/include/ "mpc5200b.dtsi" 18/include/ "mpc5200b.dtsi"
19 19
20&gpt0 { fsl,has-wdt; };
21
20/ { 22/ {
21 model = "anonymous,a3m071"; 23 model = "anonymous,a3m071";
22 compatible = "anonymous,a3m071"; 24 compatible = "anonymous,a3m071";
@@ -30,10 +32,6 @@
30 bus-frequency = <0>; /* From boot loader */ 32 bus-frequency = <0>; /* From boot loader */
31 system-frequency = <0>; /* From boot loader */ 33 system-frequency = <0>; /* From boot loader */
32 34
33 timer@600 {
34 fsl,has-wdt;
35 };
36
37 spi@f00 { 35 spi@f00 {
38 status = "disabled"; 36 status = "disabled";
39 }; 37 };
diff --git a/arch/powerpc/boot/dts/a4m072.dts b/arch/powerpc/boot/dts/a4m072.dts
index fabe7b7d5f13..1f02034c7e99 100644
--- a/arch/powerpc/boot/dts/a4m072.dts
+++ b/arch/powerpc/boot/dts/a4m072.dts
@@ -15,6 +15,11 @@
15 15
16/include/ "mpc5200b.dtsi" 16/include/ "mpc5200b.dtsi"
17 17
18&gpt0 { fsl,has-wdt; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22
18/ { 23/ {
19 model = "anonymous,a4m072"; 24 model = "anonymous,a4m072";
20 compatible = "anonymous,a4m072"; 25 compatible = "anonymous,a4m072";
@@ -34,28 +39,6 @@
34 fsl,init-fd-counters = <0x3333>; 39 fsl,init-fd-counters = <0x3333>;
35 }; 40 };
36 41
37 timer@600 {
38 fsl,has-wdt;
39 };
40
41 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
42 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
43 gpio-controller;
44 #gpio-cells = <2>;
45 };
46
47 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
48 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
49 gpio-controller;
50 #gpio-cells = <2>;
51 };
52
53 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
54 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 spi@f00 { 42 spi@f00 {
60 status = "disabled"; 43 status = "disabled";
61 }; 44 };
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index ad3a4f4a2b04..fb580dd84ddf 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -12,15 +12,13 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 { fsl,has-wdt; };
16
15/ { 17/ {
16 model = "schindler,cm5200"; 18 model = "schindler,cm5200";
17 compatible = "schindler,cm5200"; 19 compatible = "schindler,cm5200";
18 20
19 soc5200@f0000000 { 21 soc5200@f0000000 {
20 timer@600 { // General Purpose Timer
21 fsl,has-wdt;
22 };
23
24 can@900 { 22 can@900 {
25 status = "disabled"; 23 status = "disabled";
26 }; 24 };
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index a7511f2d844d..955bff629df3 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -13,6 +13,9 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16&gpt0 { gpio-controller; fsl,has-wdt; };
17&gpt1 { gpio-controller; };
18
16/ { 19/ {
17 model = "intercontrol,digsy-mtc"; 20 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc"; 21 compatible = "intercontrol,digsy-mtc";
@@ -22,17 +25,6 @@
22 }; 25 };
23 26
24 soc5200@f0000000 { 27 soc5200@f0000000 {
25 timer@600 { // General Purpose Timer
26 #gpio-cells = <2>;
27 fsl,has-wdt;
28 gpio-controller;
29 };
30
31 timer@610 {
32 #gpio-cells = <2>;
33 gpio-controller;
34 };
35
36 rtc@800 { 28 rtc@800 {
37 status = "disabled"; 29 status = "disabled";
38 }; 30 };
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index fb288bb882b6..5abb46c5cc95 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -12,19 +12,34 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 { fsl,has-wdt; };
16&gpt2 { gpio-controller; };
17&gpt3 { gpio-controller; };
18
15/ { 19/ {
16 model = "fsl,lite5200b"; 20 model = "fsl,lite5200b";
17 compatible = "fsl,lite5200b"; 21 compatible = "fsl,lite5200b";
18 22
23 leds {
24 compatible = "gpio-leds";
25 tmr2 {
26 gpios = <&gpt2 0 1>;
27 };
28 tmr3 {
29 gpios = <&gpt3 0 1>;
30 linux,default-trigger = "heartbeat";
31 };
32 led1 { gpios = <&gpio_wkup 2 1>; };
33 led2 { gpios = <&gpio_simple 3 1>; };
34 led3 { gpios = <&gpio_wkup 3 1>; };
35 led4 { gpios = <&gpio_simple 2 1>; };
36 };
37
19 memory { 38 memory {
20 reg = <0x00000000 0x10000000>; // 256MB 39 reg = <0x00000000 0x10000000>; // 256MB
21 }; 40 };
22 41
23 soc5200@f0000000 { 42 soc5200@f0000000 {
24 timer@600 { // General Purpose Timer
25 fsl,has-wdt;
26 };
27
28 psc@2000 { // PSC1 43 psc@2000 { // PSC1
29 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 44 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
30 cell-index = <0>; 45 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index 48d72f38e5ed..b5413cb85f13 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -13,6 +13,8 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16&gpt0 { fsl,has-wdt; };
17
16/ { 18/ {
17 model = "fsl,media5200"; 19 model = "fsl,media5200";
18 compatible = "fsl,media5200"; 20 compatible = "fsl,media5200";
@@ -41,10 +43,6 @@
41 soc5200@f0000000 { 43 soc5200@f0000000 {
42 bus-frequency = <132000000>;// 132 MHz 44 bus-frequency = <132000000>;// 132 MHz
43 45
44 timer@600 { // General Purpose Timer
45 fsl,has-wdt;
46 };
47
48 psc@2000 { // PSC1 46 psc@2000 { // PSC1
49 status = "disabled"; 47 status = "disabled";
50 }; 48 };
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 0b78e89ac69b..bbabd97492ad 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -12,26 +12,22 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 { fsl,has-wdt; };
16&gpt6 { // Motion-PRO status LED
17 compatible = "promess,motionpro-led";
18 label = "motionpro-statusled";
19 blink-delay = <100>; // 100 msec
20};
21&gpt7 { // Motion-PRO ready LED
22 compatible = "promess,motionpro-led";
23 label = "motionpro-readyled";
24};
25
15/ { 26/ {
16 model = "promess,motionpro"; 27 model = "promess,motionpro";
17 compatible = "promess,motionpro"; 28 compatible = "promess,motionpro";
18 29
19 soc5200@f0000000 { 30 soc5200@f0000000 {
20 timer@600 { // General Purpose Timer
21 fsl,has-wdt;
22 };
23
24 timer@660 { // Motion-PRO status LED
25 compatible = "promess,motionpro-led";
26 label = "motionpro-statusled";
27 blink-delay = <100>; // 100 msec
28 };
29
30 timer@670 { // Motion-PRO ready LED
31 compatible = "promess,motionpro-led";
32 label = "motionpro-readyled";
33 };
34
35 can@900 { 31 can@900 {
36 status = "disabled"; 32 status = "disabled";
37 }; 33 };
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
new file mode 100644
index 000000000000..723e292b6b4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -0,0 +1,410 @@
1/*
2 * base MPC5121 Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "mpc5121";
16 compatible = "fsl,mpc5121";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&ipic>;
20
21 aliases {
22 ethernet0 = &eth0;
23 pci = &pci;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,5121@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <0x20>; /* 32 bytes */
34 i-cache-line-size = <0x20>; /* 32 bytes */
35 d-cache-size = <0x8000>; /* L1, 32K */
36 i-cache-size = <0x8000>; /* L1, 32K */
37 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
38 bus-frequency = <198000000>; /* 198 MHz csb bus */
39 clock-frequency = <396000000>; /* 396 MHz ppc core */
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
46 };
47
48 mbx@20000000 {
49 compatible = "fsl,mpc5121-mbx";
50 reg = <0x20000000 0x4000>;
51 interrupts = <66 0x8>;
52 };
53
54 sram@30000000 {
55 compatible = "fsl,mpc5121-sram";
56 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
57 };
58
59 nfc@40000000 {
60 compatible = "fsl,mpc5121-nfc";
61 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
62 interrupts = <6 8>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 };
66
67 localbus@80000020 {
68 compatible = "fsl,mpc5121-localbus";
69 #address-cells = <2>;
70 #size-cells = <1>;
71 reg = <0x80000020 0x40>;
72 interrupts = <7 0x8>;
73 ranges = <0x0 0x0 0xfc000000 0x04000000>;
74 };
75
76 soc@80000000 {
77 compatible = "fsl,mpc5121-immr";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 #interrupt-cells = <2>;
81 ranges = <0x0 0x80000000 0x400000>;
82 reg = <0x80000000 0x400000>;
83 bus-frequency = <66000000>; /* 66 MHz ips bus */
84
85
86 /*
87 * IPIC
88 * interrupts cell = <intr #, sense>
89 * sense values match linux IORESOURCE_IRQ_* defines:
90 * sense == 8: Level, low assertion
91 * sense == 2: Edge, high-to-low change
92 */
93 ipic: interrupt-controller@c00 {
94 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
95 interrupt-controller;
96 #address-cells = <0>;
97 #interrupt-cells = <2>;
98 reg = <0xc00 0x100>;
99 };
100
101 /* Watchdog timer */
102 wdt@900 {
103 compatible = "fsl,mpc5121-wdt";
104 reg = <0x900 0x100>;
105 };
106
107 /* Real time clock */
108 rtc@a00 {
109 compatible = "fsl,mpc5121-rtc";
110 reg = <0xa00 0x100>;
111 interrupts = <79 0x8 80 0x8>;
112 };
113
114 /* Reset module */
115 reset@e00 {
116 compatible = "fsl,mpc5121-reset";
117 reg = <0xe00 0x100>;
118 };
119
120 /* Clock control */
121 clock@f00 {
122 compatible = "fsl,mpc5121-clock";
123 reg = <0xf00 0x100>;
124 };
125
126 /* Power Management Controller */
127 pmc@1000{
128 compatible = "fsl,mpc5121-pmc";
129 reg = <0x1000 0x100>;
130 interrupts = <83 0x8>;
131 };
132
133 gpio@1100 {
134 compatible = "fsl,mpc5121-gpio";
135 reg = <0x1100 0x100>;
136 interrupts = <78 0x8>;
137 };
138
139 can@1300 {
140 compatible = "fsl,mpc5121-mscan";
141 reg = <0x1300 0x80>;
142 interrupts = <12 0x8>;
143 };
144
145 can@1380 {
146 compatible = "fsl,mpc5121-mscan";
147 reg = <0x1380 0x80>;
148 interrupts = <13 0x8>;
149 };
150
151 sdhc@1500 {
152 compatible = "fsl,mpc5121-sdhc";
153 reg = <0x1500 0x100>;
154 interrupts = <8 0x8>;
155 };
156
157 i2c@1700 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
161 reg = <0x1700 0x20>;
162 interrupts = <9 0x8>;
163 };
164
165 i2c@1720 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
169 reg = <0x1720 0x20>;
170 interrupts = <10 0x8>;
171 };
172
173 i2c@1740 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
177 reg = <0x1740 0x20>;
178 interrupts = <11 0x8>;
179 };
180
181 i2ccontrol@1760 {
182 compatible = "fsl,mpc5121-i2c-ctrl";
183 reg = <0x1760 0x8>;
184 };
185
186 axe@2000 {
187 compatible = "fsl,mpc5121-axe";
188 reg = <0x2000 0x100>;
189 interrupts = <42 0x8>;
190 };
191
192 display@2100 {
193 compatible = "fsl,mpc5121-diu";
194 reg = <0x2100 0x100>;
195 interrupts = <64 0x8>;
196 };
197
198 can@2300 {
199 compatible = "fsl,mpc5121-mscan";
200 reg = <0x2300 0x80>;
201 interrupts = <90 0x8>;
202 };
203
204 can@2380 {
205 compatible = "fsl,mpc5121-mscan";
206 reg = <0x2380 0x80>;
207 interrupts = <91 0x8>;
208 };
209
210 viu@2400 {
211 compatible = "fsl,mpc5121-viu";
212 reg = <0x2400 0x400>;
213 interrupts = <67 0x8>;
214 };
215
216 mdio@2800 {
217 compatible = "fsl,mpc5121-fec-mdio";
218 reg = <0x2800 0x800>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 eth0: ethernet@2800 {
224 device_type = "network";
225 compatible = "fsl,mpc5121-fec";
226 reg = <0x2800 0x800>;
227 local-mac-address = [ 00 00 00 00 00 00 ];
228 interrupts = <4 0x8>;
229 };
230
231 /* USB1 using external ULPI PHY */
232 usb@3000 {
233 compatible = "fsl,mpc5121-usb2-dr";
234 reg = <0x3000 0x600>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 interrupts = <43 0x8>;
238 dr_mode = "otg";
239 phy_type = "ulpi";
240 };
241
242 /* USB0 using internal UTMI PHY */
243 usb@4000 {
244 compatible = "fsl,mpc5121-usb2-dr";
245 reg = <0x4000 0x600>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 interrupts = <44 0x8>;
249 dr_mode = "otg";
250 phy_type = "utmi_wide";
251 };
252
253 /* IO control */
254 ioctl@a000 {
255 compatible = "fsl,mpc5121-ioctl";
256 reg = <0xA000 0x1000>;
257 };
258
259 /* LocalPlus controller */
260 lpc@10000 {
261 compatible = "fsl,mpc5121-lpc";
262 reg = <0x10000 0x200>;
263 };
264
265 pata@10200 {
266 compatible = "fsl,mpc5121-pata";
267 reg = <0x10200 0x100>;
268 interrupts = <5 0x8>;
269 };
270
271 /* 512x PSCs are not 52xx PSC compatible */
272
273 /* PSC0 */
274 psc@11000 {
275 compatible = "fsl,mpc5121-psc";
276 reg = <0x11000 0x100>;
277 interrupts = <40 0x8>;
278 fsl,rx-fifo-size = <16>;
279 fsl,tx-fifo-size = <16>;
280 };
281
282 /* PSC1 */
283 psc@11100 {
284 compatible = "fsl,mpc5121-psc";
285 reg = <0x11100 0x100>;
286 interrupts = <40 0x8>;
287 fsl,rx-fifo-size = <16>;
288 fsl,tx-fifo-size = <16>;
289 };
290
291 /* PSC2 */
292 psc@11200 {
293 compatible = "fsl,mpc5121-psc";
294 reg = <0x11200 0x100>;
295 interrupts = <40 0x8>;
296 fsl,rx-fifo-size = <16>;
297 fsl,tx-fifo-size = <16>;
298 };
299
300 /* PSC3 */
301 psc@11300 {
302 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
303 reg = <0x11300 0x100>;
304 interrupts = <40 0x8>;
305 fsl,rx-fifo-size = <16>;
306 fsl,tx-fifo-size = <16>;
307 };
308
309 /* PSC4 */
310 psc@11400 {
311 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
312 reg = <0x11400 0x100>;
313 interrupts = <40 0x8>;
314 fsl,rx-fifo-size = <16>;
315 fsl,tx-fifo-size = <16>;
316 };
317
318 /* PSC5 */
319 psc@11500 {
320 compatible = "fsl,mpc5121-psc";
321 reg = <0x11500 0x100>;
322 interrupts = <40 0x8>;
323 fsl,rx-fifo-size = <16>;
324 fsl,tx-fifo-size = <16>;
325 };
326
327 /* PSC6 */
328 psc@11600 {
329 compatible = "fsl,mpc5121-psc";
330 reg = <0x11600 0x100>;
331 interrupts = <40 0x8>;
332 fsl,rx-fifo-size = <16>;
333 fsl,tx-fifo-size = <16>;
334 };
335
336 /* PSC7 */
337 psc@11700 {
338 compatible = "fsl,mpc5121-psc";
339 reg = <0x11700 0x100>;
340 interrupts = <40 0x8>;
341 fsl,rx-fifo-size = <16>;
342 fsl,tx-fifo-size = <16>;
343 };
344
345 /* PSC8 */
346 psc@11800 {
347 compatible = "fsl,mpc5121-psc";
348 reg = <0x11800 0x100>;
349 interrupts = <40 0x8>;
350 fsl,rx-fifo-size = <16>;
351 fsl,tx-fifo-size = <16>;
352 };
353
354 /* PSC9 */
355 psc@11900 {
356 compatible = "fsl,mpc5121-psc";
357 reg = <0x11900 0x100>;
358 interrupts = <40 0x8>;
359 fsl,rx-fifo-size = <16>;
360 fsl,tx-fifo-size = <16>;
361 };
362
363 /* PSC10 */
364 psc@11a00 {
365 compatible = "fsl,mpc5121-psc";
366 reg = <0x11a00 0x100>;
367 interrupts = <40 0x8>;
368 fsl,rx-fifo-size = <16>;
369 fsl,tx-fifo-size = <16>;
370 };
371
372 /* PSC11 */
373 psc@11b00 {
374 compatible = "fsl,mpc5121-psc";
375 reg = <0x11b00 0x100>;
376 interrupts = <40 0x8>;
377 fsl,rx-fifo-size = <16>;
378 fsl,tx-fifo-size = <16>;
379 };
380
381 pscfifo@11f00 {
382 compatible = "fsl,mpc5121-psc-fifo";
383 reg = <0x11f00 0x100>;
384 interrupts = <40 0x8>;
385 };
386
387 dma@14000 {
388 compatible = "fsl,mpc5121-dma";
389 reg = <0x14000 0x1800>;
390 interrupts = <65 0x8>;
391 };
392 };
393
394 pci: pci@80008500 {
395 compatible = "fsl,mpc5121-pci";
396 device_type = "pci";
397 interrupts = <1 0x8>;
398 clock-frequency = <0>;
399 #address-cells = <3>;
400 #size-cells = <2>;
401 #interrupt-cells = <1>;
402
403 reg = <0x80008500 0x100 /* internal registers */
404 0x80008300 0x8>; /* config space access registers */
405 bus-range = <0x0 0x0>;
406 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
407 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
408 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
409 };
410};
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c9ef6bbe26cf..f269b1382ef7 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC5121E ADS Device Tree Source 2 * MPC5121E ADS Device Tree Source
3 * 3 *
4 * Copyright 2007,2008 Freescale Semiconductor Inc. 4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,74 +9,26 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "mpc5121.dtsi"
13 13
14/ { 14/ {
15 model = "mpc5121ads"; 15 model = "mpc5121ads";
16 compatible = "fsl,mpc5121ads"; 16 compatible = "fsl,mpc5121ads";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 pci = &pci;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5121@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <0x8000>; // L1, 32K
34 i-cache-size = <0x8000>; // L1, 32K
35 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
36 bus-frequency = <198000000>; // 198 MHz csb bus
37 clock-frequency = <396000000>; // 396 MHz ppc core
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x10000000>; // 256MB at 0
44 };
45
46 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx";
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
50 interrupt-parent = < &ipic >;
51 };
52
53 sram@30000000 {
54 compatible = "fsl,mpc5121-sram";
55 reg = <0x30000000 0x20000>; // 128K at 0x30000000
56 };
57 17
58 nfc@40000000 { 18 nfc@40000000 {
59 compatible = "fsl,mpc5121-nfc"; 19 /*
60 reg = <0x40000000 0x100000>; // 1M at 0x40000000 20 * ADS has two Hynix 512MB Nand flash chips in a single
61 interrupts = <6 8>; 21 * stacked package.
62 interrupt-parent = < &ipic >; 22 */
63 #address-cells = <1>;
64 #size-cells = <1>;
65 // ADS has two Hynix 512MB Nand flash chips in a single
66 // stacked package.
67 chips = <2>; 23 chips = <2>;
24
68 nand@0 { 25 nand@0 {
69 label = "nand"; 26 label = "nand";
70 reg = <0x00000000 0x40000000>; // 512MB + 512MB 27 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
71 }; 28 };
72 }; 29 };
73 30
74 localbus@80000020 { 31 localbus@80000020 {
75 compatible = "fsl,mpc5121-localbus";
76 #address-cells = <2>;
77 #size-cells = <1>;
78 reg = <0x80000020 0x40>;
79
80 ranges = <0x0 0x0 0xfc000000 0x04000000 32 ranges = <0x0 0x0 0xfc000000 0x04000000
81 0x2 0x0 0x82000000 0x00008000>; 33 0x2 0x0 0x82000000 0x00008000>;
82 34
@@ -87,6 +39,7 @@
87 #size-cells = <1>; 39 #size-cells = <1>;
88 bank-width = <4>; 40 bank-width = <4>;
89 device-width = <2>; 41 device-width = <2>;
42
90 protected@0 { 43 protected@0 {
91 label = "protected"; 44 label = "protected";
92 reg = <0x00000000 0x00040000>; // first sector is protected 45 reg = <0x00000000 0x00040000>; // first sector is protected
@@ -121,91 +74,18 @@
121 interrupt-controller; 74 interrupt-controller;
122 #interrupt-cells = <2>; 75 #interrupt-cells = <2>;
123 reg = <0x2 0xa 0x5>; 76 reg = <0x2 0xa 0x5>;
124 interrupt-parent = < &ipic >; 77 /* irq routing:
125 // irq routing 78 * all irqs but touch screen are routed to irq0 (ipic 48)
126 // all irqs but touch screen are routed to irq0 (ipic 48) 79 * touch screen is statically routed to irq1 (ipic 17)
127 // touch screen is statically routed to irq1 (ipic 17) 80 * so don't use it here
128 // so don't use it here 81 */
129 interrupts = <48 0x8>; 82 interrupts = <48 0x8>;
130 }; 83 };
131 }; 84 };
132 85
133 soc@80000000 { 86 soc@80000000 {
134 compatible = "fsl,mpc5121-immr";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 #interrupt-cells = <2>;
138 ranges = <0x0 0x80000000 0x400000>;
139 reg = <0x80000000 0x400000>;
140 bus-frequency = <66000000>; // 66 MHz ips bus
141
142
143 // IPIC
144 // interrupts cell = <intr #, sense>
145 // sense values match linux IORESOURCE_IRQ_* defines:
146 // sense == 8: Level, low assertion
147 // sense == 2: Edge, high-to-low change
148 //
149 ipic: interrupt-controller@c00 {
150 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
151 interrupt-controller;
152 #address-cells = <0>;
153 #interrupt-cells = <2>;
154 reg = <0xc00 0x100>;
155 };
156
157 rtc@a00 { // Real time clock
158 compatible = "fsl,mpc5121-rtc";
159 reg = <0xa00 0x100>;
160 interrupts = <79 0x8 80 0x8>;
161 interrupt-parent = < &ipic >;
162 };
163
164 reset@e00 { // Reset module
165 compatible = "fsl,mpc5121-reset";
166 reg = <0xe00 0x100>;
167 };
168
169 clock@f00 { // Clock control
170 compatible = "fsl,mpc5121-clock";
171 reg = <0xf00 0x100>;
172 };
173
174 pmc@1000{ //Power Management Controller
175 compatible = "fsl,mpc5121-pmc";
176 reg = <0x1000 0x100>;
177 interrupts = <83 0x2>;
178 interrupt-parent = < &ipic >;
179 };
180
181 gpio@1100 {
182 compatible = "fsl,mpc5121-gpio";
183 reg = <0x1100 0x100>;
184 interrupts = <78 0x8>;
185 interrupt-parent = < &ipic >;
186 };
187
188 can@1300 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <12 0x8>;
191 interrupt-parent = < &ipic >;
192 reg = <0x1300 0x80>;
193 };
194
195 can@1380 {
196 compatible = "fsl,mpc5121-mscan";
197 interrupts = <13 0x8>;
198 interrupt-parent = < &ipic >;
199 reg = <0x1380 0x80>;
200 };
201 87
202 i2c@1700 { 88 i2c@1700 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
206 reg = <0x1700 0x20>;
207 interrupts = <9 0x8>;
208 interrupt-parent = < &ipic >;
209 fsl,preserve-clocking; 89 fsl,preserve-clocking;
210 90
211 hwmon@4a { 91 hwmon@4a {
@@ -224,196 +104,75 @@
224 }; 104 };
225 }; 105 };
226 106
227 i2c@1720 { 107 eth0: ethernet@2800 {
228 #address-cells = <1>; 108 phy-handle = <&phy0>;
229 #size-cells = <0>;
230 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
231 reg = <0x1720 0x20>;
232 interrupts = <10 0x8>;
233 interrupt-parent = < &ipic >;
234 };
235
236 i2c@1740 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
240 reg = <0x1740 0x20>;
241 interrupts = <11 0x8>;
242 interrupt-parent = < &ipic >;
243 }; 109 };
244 110
245 i2ccontrol@1760 { 111 can@2300 {
246 compatible = "fsl,mpc5121-i2c-ctrl"; 112 status = "disabled";
247 reg = <0x1760 0x8>;
248 }; 113 };
249 114
250 axe@2000 { 115 can@2380 {
251 compatible = "fsl,mpc5121-axe"; 116 status = "disabled";
252 reg = <0x2000 0x100>;
253 interrupts = <42 0x8>;
254 interrupt-parent = < &ipic >;
255 }; 117 };
256 118
257 display@2100 { 119 viu@2400 {
258 compatible = "fsl,mpc5121-diu"; 120 status = "disabled";
259 reg = <0x2100 0x100>;
260 interrupts = <64 0x8>;
261 interrupt-parent = < &ipic >;
262 }; 121 };
263 122
264 mdio@2800 { 123 mdio@2800 {
265 compatible = "fsl,mpc5121-fec-mdio"; 124 phy0: ethernet-phy@0 {
266 reg = <0x2800 0x800>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 phy: ethernet-phy@0 {
270 reg = <1>; 125 reg = <1>;
271 device_type = "ethernet-phy";
272 }; 126 };
273 }; 127 };
274 128
275 ethernet@2800 { 129 /* mpc5121ads only uses USB0 */
276 device_type = "network"; 130 usb@3000 {
277 compatible = "fsl,mpc5121-fec"; 131 status = "disabled";
278 reg = <0x2800 0x800>;
279 local-mac-address = [ 00 00 00 00 00 00 ];
280 interrupts = <4 0x8>;
281 interrupt-parent = < &ipic >;
282 phy-handle = < &phy >;
283 fsl,align-tx-packets = <4>;
284 }; 132 };
285 133
286 // 5121e has two dr usb modules 134 /* USB0 using internal UTMI PHY */
287 // mpc5121_ads only uses USB0
288
289 // USB1 using external ULPI PHY
290 //usb@3000 {
291 // compatible = "fsl,mpc5121-usb2-dr";
292 // reg = <0x3000 0x1000>;
293 // #address-cells = <1>;
294 // #size-cells = <0>;
295 // interrupt-parent = < &ipic >;
296 // interrupts = <43 0x8>;
297 // dr_mode = "otg";
298 // phy_type = "ulpi";
299 //};
300
301 // USB0 using internal UTMI PHY
302 usb@4000 { 135 usb@4000 {
303 compatible = "fsl,mpc5121-usb2-dr"; 136 dr_mode = "host";
304 reg = <0x4000 0x1000>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 interrupt-parent = < &ipic >;
308 interrupts = <44 0x8>;
309 dr_mode = "otg";
310 phy_type = "utmi_wide";
311 fsl,invert-drvvbus; 137 fsl,invert-drvvbus;
312 fsl,invert-pwr-fault; 138 fsl,invert-pwr-fault;
313 }; 139 };
314 140
315 // IO control 141 /* PSC3 serial port A aka ttyPSC0 */
316 ioctl@a000 { 142 psc@11300 {
317 compatible = "fsl,mpc5121-ioctl";
318 reg = <0xA000 0x1000>;
319 };
320
321 pata@10200 {
322 compatible = "fsl,mpc5121-pata";
323 reg = <0x10200 0x100>;
324 interrupts = <5 0x8>;
325 interrupt-parent = < &ipic >;
326 };
327
328 // 512x PSCs are not 52xx PSC compatible
329 // PSC3 serial port A aka ttyPSC0
330 serial@11300 {
331 device_type = "serial";
332 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 143 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
333 // Logical port assignment needed until driver
334 // learns to use aliases
335 port-number = <0>;
336 cell-index = <3>;
337 reg = <0x11300 0x100>;
338 interrupts = <40 0x8>;
339 interrupt-parent = < &ipic >;
340 rx-fifo-size = <16>;
341 tx-fifo-size = <16>;
342 }; 144 };
343 145
344 // PSC4 serial port B aka ttyPSC1 146 /* PSC4 serial port B aka ttyPSC1 */
345 serial@11400 { 147 psc@11400 {
346 device_type = "serial";
347 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 148 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
348 // Logical port assignment needed until driver
349 // learns to use aliases
350 port-number = <1>;
351 cell-index = <4>;
352 reg = <0x11400 0x100>;
353 interrupts = <40 0x8>;
354 interrupt-parent = < &ipic >;
355 rx-fifo-size = <16>;
356 tx-fifo-size = <16>;
357 }; 149 };
358 150
359 // PSC5 in ac97 mode 151 /* PSC5 in ac97 mode */
360 ac97@11500 { 152 ac97: psc@11500 {
361 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc"; 153 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
362 cell-index = <5>;
363 reg = <0x11500 0x100>;
364 interrupts = <40 0x8>;
365 interrupt-parent = < &ipic >;
366 fsl,mode = "ac97-slave"; 154 fsl,mode = "ac97-slave";
367 rx-fifo-size = <384>; 155 fsl,rx-fifo-size = <384>;
368 tx-fifo-size = <384>; 156 fsl,tx-fifo-size = <384>;
369 };
370
371 pscfifo@11f00 {
372 compatible = "fsl,mpc5121-psc-fifo";
373 reg = <0x11f00 0x100>;
374 interrupts = <40 0x8>;
375 interrupt-parent = < &ipic >;
376 }; 157 };
377
378 dma@14000 {
379 compatible = "fsl,mpc5121-dma";
380 reg = <0x14000 0x1800>;
381 interrupts = <65 0x8>;
382 interrupt-parent = < &ipic >;
383 };
384
385 }; 158 };
386 159
387 pci: pci@80008500 { 160 pci: pci@80008500 {
388 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 161 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
389 interrupt-map = < 162 interrupt-map = <
390 // IDSEL 0x15 - Slot 1 PCI 163 /* IDSEL 0x15 - Slot 1 PCI */
391 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8 164 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
392 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8 165 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
393 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8 166 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
394 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8 167 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
395 168
396 // IDSEL 0x16 - Slot 2 MiniPCI 169 /* IDSEL 0x16 - Slot 2 MiniPCI */
397 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8 170 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
398 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8 171 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
399 172
400 // IDSEL 0x17 - Slot 3 MiniPCI 173 /* IDSEL 0x17 - Slot 3 MiniPCI */
401 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8 174 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
402 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8 175 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
403 >; 176 >;
404 interrupt-parent = < &ipic >;
405 interrupts = <1 0x8>;
406 bus-range = <0 0>;
407 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
408 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
409 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
410 clock-frequency = <0>;
411 #interrupt-cells = <1>;
412 #size-cells = <2>;
413 #address-cells = <3>;
414 reg = <0x80008500 0x100 /* internal registers */
415 0x80008300 0x8>; /* config space access registers */
416 compatible = "fsl,mpc5121-pci";
417 device_type = "pci";
418 }; 177 };
419}; 178};
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
index 39ed65a44c5f..969b2200b2f9 100644
--- a/arch/powerpc/boot/dts/mpc5200b.dtsi
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -64,50 +64,59 @@
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { // General Purpose Timer 67 gpt0: timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
69 reg = <0x600 0x10>; 70 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 71 interrupts = <1 9 0>;
72 // add 'fsl,has-wdt' to enable watchdog
71 }; 73 };
72 74
73 timer@610 { // General Purpose Timer 75 gpt1: timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
75 reg = <0x610 0x10>; 78 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 79 interrupts = <1 10 0>;
77 }; 80 };
78 81
79 timer@620 { // General Purpose Timer 82 gpt2: timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 83 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
84 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
81 reg = <0x620 0x10>; 85 reg = <0x620 0x10>;
82 interrupts = <1 11 0>; 86 interrupts = <1 11 0>;
83 }; 87 };
84 88
85 timer@630 { // General Purpose Timer 89 gpt3: timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
87 reg = <0x630 0x10>; 92 reg = <0x630 0x10>;
88 interrupts = <1 12 0>; 93 interrupts = <1 12 0>;
89 }; 94 };
90 95
91 timer@640 { // General Purpose Timer 96 gpt4: timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
98 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
93 reg = <0x640 0x10>; 99 reg = <0x640 0x10>;
94 interrupts = <1 13 0>; 100 interrupts = <1 13 0>;
95 }; 101 };
96 102
97 timer@650 { // General Purpose Timer 103 gpt5: timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
99 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
100 interrupts = <1 14 0>; 107 interrupts = <1 14 0>;
101 }; 108 };
102 109
103 timer@660 { // General Purpose Timer 110 gpt6: timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
112 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
105 reg = <0x660 0x10>; 113 reg = <0x660 0x10>;
106 interrupts = <1 15 0>; 114 interrupts = <1 15 0>;
107 }; 115 };
108 116
109 timer@670 { // General Purpose Timer 117 gpt7: timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 118 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
119 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
111 reg = <0x670 0x10>; 120 reg = <0x670 0x10>;
112 interrupts = <1 16 0>; 121 interrupts = <1 16 0>;
113 }; 122 };
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index 21d34720fcc9..d3a792bb5c1a 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -13,47 +13,23 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16/* Timer pins that need to be in GPIO mode */
17&gpt0 { gpio-controller; };
18&gpt1 { gpio-controller; };
19&gpt2 { gpio-controller; };
20&gpt3 { gpio-controller; };
21
22/* Disabled timers */
23&gpt4 { status = "disabled"; };
24&gpt5 { status = "disabled"; };
25&gpt6 { status = "disabled"; };
26&gpt7 { status = "disabled"; };
27
16/ { 28/ {
17 model = "manroland,mucmc52"; 29 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52"; 30 compatible = "manroland,mucmc52";
19 31
20 soc5200@f0000000 { 32 soc5200@f0000000 {
21 gpt0: timer@600 { // GPT 0 in GPIO mode
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
27 gpio-controller;
28 #gpio-cells = <2>;
29 };
30
31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35
36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
37 gpio-controller;
38 #gpio-cells = <2>;
39 };
40
41 timer@640 {
42 status = "disabled";
43 };
44
45 timer@650 {
46 status = "disabled";
47 };
48
49 timer@660 {
50 status = "disabled";
51 };
52
53 timer@670 {
54 status = "disabled";
55 };
56
57 rtc@800 { 33 rtc@800 {
58 status = "disabled"; 34 status = "disabled";
59 }; 35 };
diff --git a/arch/powerpc/boot/dts/o2d.dtsi b/arch/powerpc/boot/dts/o2d.dtsi
index 24f668039295..cf073e693f24 100644
--- a/arch/powerpc/boot/dts/o2d.dtsi
+++ b/arch/powerpc/boot/dts/o2d.dtsi
@@ -12,6 +12,13 @@
12 12
13/include/ "mpc5200b.dtsi" 13/include/ "mpc5200b.dtsi"
14 14
15&gpt0 {
16 gpio-controller;
17 fsl,has-wdt;
18 fsl,wdt-on-boot = <0>;
19};
20&gpt1 { gpio-controller; };
21
15/ { 22/ {
16 model = "ifm,o2d"; 23 model = "ifm,o2d";
17 compatible = "ifm,o2d"; 24 compatible = "ifm,o2d";
@@ -22,24 +29,6 @@
22 29
23 soc5200@f0000000 { 30 soc5200@f0000000 {
24 31
25 gpio_simple: gpio@b00 {
26 };
27
28 timer@600 { // General Purpose Timer
29 #gpio-cells = <2>;
30 gpio-controller;
31 fsl,has-wdt;
32 fsl,wdt-on-boot = <0>;
33 };
34
35 timer@610 {
36 #gpio-cells = <2>;
37 gpio-controller;
38 };
39
40 timer7: timer@670 {
41 };
42
43 rtc@800 { 32 rtc@800 {
44 status = "disabled"; 33 status = "disabled";
45 }; 34 };
@@ -118,7 +107,7 @@
118 csi@3,0 { 107 csi@3,0 {
119 compatible = "ifm,o2d-csi"; 108 compatible = "ifm,o2d-csi";
120 reg = <3 0 0x00100000>; 109 reg = <3 0 0x00100000>;
121 ifm,csi-clk-handle = <&timer7>; 110 ifm,csi-clk-handle = <&gpt7>;
122 gpios = <&gpio_simple 23 0 /* imag_capture */ 111 gpios = <&gpio_simple 23 0 /* imag_capture */
123 &gpio_simple 26 0 /* imag_reset */ 112 &gpio_simple 26 0 /* imag_reset */
124 &gpio_simple 29 0>; /* imag_master_en */ 113 &gpio_simple 29 0>; /* imag_master_en */
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 96512c058033..192e66af0001 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -14,51 +14,19 @@
14 14
15/include/ "mpc5200b.dtsi" 15/include/ "mpc5200b.dtsi"
16 16
17&gpt0 { fsl,has-wdt; };
18&gpt2 { gpio-controller; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22&gpt6 { gpio-controller; };
23&gpt7 { gpio-controller; };
24
17/ { 25/ {
18 model = "phytec,pcm030"; 26 model = "phytec,pcm030";
19 compatible = "phytec,pcm030"; 27 compatible = "phytec,pcm030";
20 28
21 soc5200@f0000000 { 29 soc5200@f0000000 {
22 timer@600 { // General Purpose Timer
23 fsl,has-wdt;
24 };
25
26 gpt2: timer@620 { // General Purpose Timer in GPIO mode
27 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
28 gpio-controller;
29 #gpio-cells = <2>;
30 };
31
32 gpt3: timer@630 { // General Purpose Timer in GPIO mode
33 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
34 gpio-controller;
35 #gpio-cells = <2>;
36 };
37
38 gpt4: timer@640 { // General Purpose Timer in GPIO mode
39 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
40 gpio-controller;
41 #gpio-cells = <2>;
42 };
43
44 gpt5: timer@650 { // General Purpose Timer in GPIO mode
45 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
46 gpio-controller;
47 #gpio-cells = <2>;
48 };
49
50 gpt6: timer@660 { // General Purpose Timer in GPIO mode
51 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
52 gpio-controller;
53 #gpio-cells = <2>;
54 };
55
56 gpt7: timer@670 { // General Purpose Timer in GPIO mode
57 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
58 gpio-controller;
59 #gpio-cells = <2>;
60 };
61
62 audioplatform: psc@2000 { /* PSC1 in ac97 mode */ 30 audioplatform: psc@2000 { /* PSC1 in ac97 mode */
63 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 31 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
64 cell-index = <0>; 32 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 1dd478bfff96..96b139bf50e9 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -14,6 +14,14 @@
14 14
15/include/ "mpc5200b.dtsi" 15/include/ "mpc5200b.dtsi"
16 16
17&gpt0 { fsl,has-wdt; };
18&gpt2 { gpio-controller; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22&gpt6 { gpio-controller; };
23&gpt7 { gpio-controller; };
24
17/ { 25/ {
18 model = "phytec,pcm032"; 26 model = "phytec,pcm032";
19 compatible = "phytec,pcm032"; 27 compatible = "phytec,pcm032";
@@ -23,43 +31,6 @@
23 }; 31 };
24 32
25 soc5200@f0000000 { 33 soc5200@f0000000 {
26 timer@600 { // General Purpose Timer
27 fsl,has-wdt;
28 };
29
30 gpt2: timer@620 { // General Purpose Timer in GPIO mode
31 gpio-controller;
32 #gpio-cells = <2>;
33 };
34
35 gpt3: timer@630 { // General Purpose Timer in GPIO mode
36 gpio-controller;
37 #gpio-cells = <2>;
38 };
39
40 gpt4: timer@640 { // General Purpose Timer in GPIO mode
41 gpio-controller;
42 #gpio-cells = <2>;
43 };
44
45 gpt5: timer@650 { // General Purpose Timer in GPIO mode
46 gpio-controller;
47 #gpio-cells = <2>;
48 };
49
50 gpt6: timer@660 { // General Purpose Timer in GPIO mode
51 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
52 reg = <0x660 0x10>;
53 interrupts = <1 15 0>;
54 gpio-controller;
55 #gpio-cells = <2>;
56 };
57
58 gpt7: timer@670 { // General Purpose Timer in GPIO mode
59 gpio-controller;
60 #gpio-cells = <2>;
61 };
62
63 psc@2000 { /* PSC1 is ac97 */ 34 psc@2000 { /* PSC1 is ac97 */
64 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 35 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
65 cell-index = <0>; 36 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 94dfa5c9a7f9..0b069477838a 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -13,7 +13,7 @@
13 * option) any later version. 13 * option) any later version.
14 */ 14 */
15 15
16/dts-v1/; 16/include/ "mpc5121.dtsi"
17 17
18/ { 18/ {
19 model = "pdm360ng"; 19 model = "pdm360ng";
@@ -22,38 +22,12 @@
22 #size-cells = <1>; 22 #size-cells = <1>;
23 interrupt-parent = <&ipic>; 23 interrupt-parent = <&ipic>;
24 24
25 aliases {
26 ethernet0 = &eth0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,5121@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
41 bus-frequency = <198000000>; // 198 MHz csb bus
42 clock-frequency = <396000000>; // 396 MHz ppc core
43 };
44 };
45
46 memory { 25 memory {
47 device_type = "memory"; 26 device_type = "memory";
48 reg = <0x00000000 0x20000000>; // 512MB at 0 27 reg = <0x00000000 0x20000000>; // 512MB at 0
49 }; 28 };
50 29
51 nfc@40000000 { 30 nfc@40000000 {
52 compatible = "fsl,mpc5121-nfc";
53 reg = <0x40000000 0x100000>;
54 interrupts = <0x6 0x8>;
55 #address-cells = <0x1>;
56 #size-cells = <0x1>;
57 bank-width = <0x1>; 31 bank-width = <0x1>;
58 chips = <0x1>; 32 chips = <0x1>;
59 33
@@ -63,17 +37,7 @@
63 }; 37 };
64 }; 38 };
65 39
66 sram@50000000 {
67 compatible = "fsl,mpc5121-sram";
68 reg = <0x50000000 0x20000>; // 128K at 0x50000000
69 };
70
71 localbus@80000020 { 40 localbus@80000020 {
72 compatible = "fsl,mpc5121-localbus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 reg = <0x80000020 0x40>;
76
77 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */ 41 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
78 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */ 42 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
79 43
@@ -129,74 +93,8 @@
129 }; 93 };
130 94
131 soc@80000000 { 95 soc@80000000 {
132 compatible = "fsl,mpc5121-immr";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 #interrupt-cells = <2>;
136 ranges = <0x0 0x80000000 0x400000>;
137 reg = <0x80000000 0x400000>;
138 bus-frequency = <66000000>; // 66 MHz ips bus
139
140 // IPIC
141 // interrupts cell = <intr #, sense>
142 // sense values match linux IORESOURCE_IRQ_* defines:
143 // sense == 8: Level, low assertion
144 // sense == 2: Edge, high-to-low change
145 //
146 ipic: interrupt-controller@c00 {
147 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0xc00 0x100>;
152 };
153
154 rtc@a00 { // Real time clock
155 compatible = "fsl,mpc5121-rtc";
156 reg = <0xa00 0x100>;
157 interrupts = <79 0x8 80 0x8>;
158 };
159
160 reset@e00 { // Reset module
161 compatible = "fsl,mpc5121-reset";
162 reg = <0xe00 0x100>;
163 };
164
165 clock@f00 { // Clock control
166 compatible = "fsl,mpc5121-clock";
167 reg = <0xf00 0x100>;
168 };
169
170 pmc@1000{ //Power Management Controller
171 compatible = "fsl,mpc5121-pmc";
172 reg = <0x1000 0x100>;
173 interrupts = <83 0x2>;
174 };
175
176 gpio@1100 {
177 compatible = "fsl,mpc5121-gpio";
178 reg = <0x1100 0x100>;
179 interrupts = <78 0x8>;
180 };
181
182 can@1300 {
183 compatible = "fsl,mpc5121-mscan";
184 interrupts = <12 0x8>;
185 reg = <0x1300 0x80>;
186 };
187
188 can@1380 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <13 0x8>;
191 reg = <0x1380 0x80>;
192 };
193 96
194 i2c@1700 { 97 i2c@1700 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,mpc5121-i2c";
198 reg = <0x1700 0x20>;
199 interrupts = <0x9 0x8>;
200 fsl,preserve-clocking; 98 fsl,preserve-clocking;
201 99
202 eeprom@50 { 100 eeprom@50 {
@@ -210,201 +108,92 @@
210 }; 108 };
211 }; 109 };
212 110
213 i2c@1740 { 111 i2c@1720 {
214 #address-cells = <1>; 112 status = "disabled";
215 #size-cells = <0>;
216 compatible = "fsl,mpc5121-i2c";
217 reg = <0x1740 0x20>;
218 interrupts = <0xb 0x8>;
219 fsl,preserve-clocking;
220 };
221
222 i2ccontrol@1760 {
223 compatible = "fsl,mpc5121-i2c-ctrl";
224 reg = <0x1760 0x8>;
225 };
226
227 axe@2000 {
228 compatible = "fsl,mpc5121-axe";
229 reg = <0x2000 0x100>;
230 interrupts = <42 0x8>;
231 };
232
233 display@2100 {
234 compatible = "fsl,mpc5121-diu";
235 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>;
237 }; 113 };
238 114
239 can@2300 { 115 i2c@1740 {
240 compatible = "fsl,mpc5121-mscan"; 116 fsl,preserve-clocking;
241 interrupts = <90 0x8>;
242 reg = <0x2300 0x80>;
243 };
244
245 can@2380 {
246 compatible = "fsl,mpc5121-mscan";
247 interrupts = <91 0x8>;
248 reg = <0x2380 0x80>;
249 }; 117 };
250 118
251 viu@2400 { 119 ethernet@2800 {
252 compatible = "fsl,mpc5121-viu"; 120 phy-handle = <&phy0>;
253 reg = <0x2400 0x400>;
254 interrupts = <67 0x8>;
255 }; 121 };
256 122
257 mdio@2800 { 123 mdio@2800 {
258 compatible = "fsl,mpc5121-fec-mdio"; 124 phy0: ethernet-phy@1f {
259 reg = <0x2800 0x200>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 phy: ethernet-phy@0 {
263 compatible = "smsc,lan8700"; 125 compatible = "smsc,lan8700";
264 reg = <0x1f>; 126 reg = <0x1f>;
265 }; 127 };
266 }; 128 };
267 129
268 eth0: ethernet@2800 { 130 /* USB1 using external ULPI PHY */
269 compatible = "fsl,mpc5121-fec";
270 reg = <0x2800 0x200>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <4 0x8>;
273 phy-handle = < &phy >;
274 };
275
276 // USB1 using external ULPI PHY
277 usb@3000 { 131 usb@3000 {
278 compatible = "fsl,mpc5121-usb2-dr";
279 reg = <0x3000 0x600>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <43 0x8>;
283 dr_mode = "host"; 132 dr_mode = "host";
284 phy_type = "ulpi";
285 }; 133 };
286 134
287 // USB0 using internal UTMI PHY 135 /* USB0 using internal UTMI PHY */
288 usb@4000 { 136 usb@4000 {
289 compatible = "fsl,mpc5121-usb2-dr";
290 reg = <0x4000 0x600>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 interrupts = <44 0x8>;
294 dr_mode = "otg";
295 phy_type = "utmi_wide";
296 fsl,invert-pwr-fault; 137 fsl,invert-pwr-fault;
297 }; 138 };
298 139
299 // IO control 140 psc@11000 {
300 ioctl@a000 {
301 compatible = "fsl,mpc5121-ioctl";
302 reg = <0xA000 0x1000>;
303 };
304
305 // 512x PSCs are not 52xx PSCs compatible
306 serial@11000 {
307 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 141 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
308 cell-index = <0>;
309 reg = <0x11000 0x100>;
310 interrupts = <40 0x8>;
311 fsl,rx-fifo-size = <16>;
312 fsl,tx-fifo-size = <16>;
313 }; 142 };
314 143
315 serial@11100 { 144 psc@11100 {
316 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 145 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
317 cell-index = <1>;
318 reg = <0x11100 0x100>;
319 interrupts = <40 0x8>;
320 fsl,rx-fifo-size = <16>;
321 fsl,tx-fifo-size = <16>;
322 }; 146 };
323 147
324 serial@11200 { 148 psc@11200 {
325 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 149 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
326 cell-index = <2>;
327 reg = <0x11200 0x100>;
328 interrupts = <40 0x8>;
329 fsl,rx-fifo-size = <16>;
330 fsl,tx-fifo-size = <16>;
331 }; 150 };
332 151
333 serial@11300 { 152 psc@11300 {
334 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 153 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
335 cell-index = <3>;
336 reg = <0x11300 0x100>;
337 interrupts = <40 0x8>;
338 fsl,rx-fifo-size = <16>;
339 fsl,tx-fifo-size = <16>;
340 }; 154 };
341 155
342 serial@11400 { 156 psc@11400 {
343 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 157 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
344 cell-index = <4>;
345 reg = <0x11400 0x100>;
346 interrupts = <40 0x8>;
347 fsl,rx-fifo-size = <16>;
348 fsl,tx-fifo-size = <16>;
349 }; 158 };
350 159
351 serial@11600 { 160 psc@11500 {
352 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 161 status = "disabled";
353 cell-index = <6>;
354 reg = <0x11600 0x100>;
355 interrupts = <40 0x8>;
356 fsl,rx-fifo-size = <16>;
357 fsl,tx-fifo-size = <16>;
358 }; 162 };
359 163
360 serial@11800 { 164 psc@11600 {
361 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 165 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
362 cell-index = <8>;
363 reg = <0x11800 0x100>;
364 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16>;
366 fsl,tx-fifo-size = <16>;
367 }; 166 };
368 167
369 serial@11B00 { 168 psc@11700 {
370 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 169 status = "disabled";
371 cell-index = <11>;
372 reg = <0x11B00 0x100>;
373 interrupts = <40 0x8>;
374 fsl,rx-fifo-size = <16>;
375 fsl,tx-fifo-size = <16>;
376 }; 170 };
377 171
378 pscfifo@11f00 { 172 psc@11800 {
379 compatible = "fsl,mpc5121-psc-fifo"; 173 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
380 reg = <0x11f00 0x100>;
381 interrupts = <40 0x8>;
382 }; 174 };
383 175
384 spi@11900 { 176 psc@11900 {
385 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; 177 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
386 cell-index = <9>;
387 #address-cells = <1>; 178 #address-cells = <1>;
388 #size-cells = <0>; 179 #size-cells = <0>;
389 reg = <0x11900 0x100>;
390 interrupts = <40 0x8>;
391 fsl,rx-fifo-size = <16>;
392 fsl,tx-fifo-size = <16>;
393 180
394 // 7845 touch screen controller 181 /* ADS7845 touch screen controller */
395 ts@0 { 182 ts@0 {
396 compatible = "ti,ads7846"; 183 compatible = "ti,ads7846";
397 reg = <0x0>; 184 reg = <0x0>;
398 spi-max-frequency = <3000000>; 185 spi-max-frequency = <3000000>;
399 // pen irq is GPIO25 186 /* pen irq is GPIO25 */
400 interrupts = <78 0x8>; 187 interrupts = <78 0x8>;
401 }; 188 };
402 }; 189 };
403 190
404 dma@14000 { 191 psc@11a00 {
405 compatible = "fsl,mpc5121-dma"; 192 status = "disabled";
406 reg = <0x14000 0x1800>; 193 };
407 interrupts = <65 0x8>; 194
195 psc@11b00 {
196 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
408 }; 197 };
409 }; 198 };
410}; 199};
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index ba83d5488ec6..5c462194ef06 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -13,54 +13,20 @@
13 13
14/include/ "mpc5200b.dtsi" 14/include/ "mpc5200b.dtsi"
15 15
16&gpt0 { gpio-controller; };
17&gpt1 { gpio-controller; };
18&gpt2 { gpio-controller; };
19&gpt3 { gpio-controller; };
20&gpt4 { gpio-controller; };
21&gpt5 { gpio-controller; };
22&gpt6 { gpio-controller; };
23&gpt7 { gpio-controller; };
24
16/ { 25/ {
17 model = "manroland,uc101"; 26 model = "manroland,uc101";
18 compatible = "manroland,uc101"; 27 compatible = "manroland,uc101";
19 28
20 soc5200@f0000000 { 29 soc5200@f0000000 {
21 gpt0: timer@600 { // General Purpose Timer in GPIO mode
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
27 gpio-controller;
28 #gpio-cells = <2>;
29 };
30
31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35
36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
37 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
38 reg = <0x630 0x10>;
39 interrupts = <1 12 0>;
40 gpio-controller;
41 #gpio-cells = <2>;
42 };
43
44 gpt4: timer@640 { // General Purpose Timer in GPIO mode
45 gpio-controller;
46 #gpio-cells = <2>;
47 };
48
49 gpt5: timer@650 { // General Purpose Timer in GPIO mode
50 gpio-controller;
51 #gpio-cells = <2>;
52 };
53
54 gpt6: timer@660 { // General Purpose Timer in GPIO mode
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 gpt7: timer@670 { // General Purpose Timer in GPIO mode
60 gpio-controller;
61 #gpio-cells = <2>;
62 };
63
64 rtc@800 { 30 rtc@800 {
65 status = "disabled"; 31 status = "disabled";
66 }; 32 };
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8c0ab2ca689c..885c040d6194 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -53,4 +53,21 @@ struct mpc512x_ccm {
53 u32 m4ccr; /* MSCAN4 CCR */ 53 u32 m4ccr; /* MSCAN4 CCR */
54 u8 res[0x98]; /* Reserved */ 54 u8 res[0x98]; /* Reserved */
55}; 55};
56
57/*
58 * LPC Module
59 */
60struct mpc512x_lpc {
61 u32 cs_cfg[8]; /* CS config */
62 u32 cs_ctrl; /* CS Control Register */
63 u32 cs_status; /* CS Status Register */
64 u32 burst_ctrl; /* CS Burst Control Register */
65 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
66 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
67 u32 alt; /* Address Latch Timing Register */
68};
69
70int mpc512x_cs_config(unsigned int cs, u32 val);
71int __init mpc5121_clk_init(void);
72
56#endif /* __ASM_POWERPC_MPC5121_H__ */ 73#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 9f771e05457c..52d57d281724 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -26,6 +26,7 @@
26 26
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <asm/mpc5xxx.h> 28#include <asm/mpc5xxx.h>
29#include <asm/mpc5121.h>
29#include <asm/clk_interface.h> 30#include <asm/clk_interface.h>
30 31
31#undef CLK_DEBUG 32#undef CLK_DEBUG
@@ -122,7 +123,7 @@ struct mpc512x_clockctl {
122 u32 dccr; /* DIU Clk Cnfg Reg */ 123 u32 dccr; /* DIU Clk Cnfg Reg */
123}; 124};
124 125
125struct mpc512x_clockctl __iomem *clockctl; 126static struct mpc512x_clockctl __iomem *clockctl;
126 127
127static int mpc5121_clk_enable(struct clk *clk) 128static int mpc5121_clk_enable(struct clk *clk)
128{ 129{
@@ -184,7 +185,7 @@ static unsigned long spmf_mult(void)
184 36, 40, 44, 48, 185 36, 40, 44, 48,
185 52, 56, 60, 64 186 52, 56, 60, 64
186 }; 187 };
187 int spmf = (clockctl->spmr >> 24) & 0xf; 188 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
188 return spmf_to_mult[spmf]; 189 return spmf_to_mult[spmf];
189} 190}
190 191
@@ -206,7 +207,7 @@ static unsigned long sysdiv_div_x_2(void)
206 52, 56, 58, 62, 207 52, 56, 58, 62,
207 60, 64, 66, 208 60, 64, 66,
208 }; 209 };
209 int sysdiv = (clockctl->scfr2 >> 26) & 0x3f; 210 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
210 return sysdiv_to_div_x_2[sysdiv]; 211 return sysdiv_to_div_x_2[sysdiv];
211} 212}
212 213
@@ -230,7 +231,7 @@ static unsigned long sys_to_ref(unsigned long rate)
230 231
231static long ips_to_ref(unsigned long rate) 232static long ips_to_ref(unsigned long rate)
232{ 233{
233 int ips_div = (clockctl->scfr1 >> 23) & 0x7; 234 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
234 235
235 rate *= ips_div; /* csb_clk = ips_clk * ips_div */ 236 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
236 rate *= 2; /* sys_clk = csb_clk * 2 */ 237 rate *= 2; /* sys_clk = csb_clk * 2 */
@@ -284,7 +285,7 @@ static struct clk sys_clk = {
284 285
285static void diu_clk_calc(struct clk *clk) 286static void diu_clk_calc(struct clk *clk)
286{ 287{
287 int diudiv_x_2 = clockctl->scfr1 & 0xff; 288 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
288 unsigned long rate; 289 unsigned long rate;
289 290
290 rate = sys_clk.rate; 291 rate = sys_clk.rate;
@@ -311,7 +312,7 @@ static void half_clk_calc(struct clk *clk)
311 312
312static void generic_div_clk_calc(struct clk *clk) 313static void generic_div_clk_calc(struct clk *clk)
313{ 314{
314 int div = (clockctl->scfr1 >> clk->div_shift) & 0x7; 315 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
315 316
316 clk->rate = clk->parent->rate / div; 317 clk->rate = clk->parent->rate / div;
317} 318}
@@ -329,7 +330,7 @@ static struct clk csb_clk = {
329 330
330static void e300_clk_calc(struct clk *clk) 331static void e300_clk_calc(struct clk *clk)
331{ 332{
332 int spmf = (clockctl->spmr >> 16) & 0xf; 333 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
333 int ratex2 = clk->parent->rate * spmf; 334 int ratex2 = clk->parent->rate * spmf;
334 335
335 clk->rate = ratex2 / 2; 336 clk->rate = ratex2 / 2;
@@ -551,7 +552,7 @@ static struct clk ac97_clk = {
551 .calc = ac97_clk_calc, 552 .calc = ac97_clk_calc,
552}; 553};
553 554
554struct clk *rate_clks[] = { 555static struct clk *rate_clks[] = {
555 &ref_clk, 556 &ref_clk,
556 &sys_clk, 557 &sys_clk,
557 &diu_clk, 558 &diu_clk,
@@ -607,7 +608,7 @@ static void rate_clks_init(void)
607 * There are two clk enable registers with 32 enable bits each 608 * There are two clk enable registers with 32 enable bits each
608 * psc clocks and device clocks are all stored in dev_clks 609 * psc clocks and device clocks are all stored in dev_clks
609 */ 610 */
610struct clk dev_clks[2][32]; 611static struct clk dev_clks[2][32];
611 612
612/* 613/*
613 * Given a psc number return the dev_clk 614 * Given a psc number return the dev_clk
@@ -648,12 +649,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
648 out_be32(&clockctl->pccr[pscnum], 0x00020000); 649 out_be32(&clockctl->pccr[pscnum], 0x00020000);
649 out_be32(&clockctl->pccr[pscnum], 0x00030000); 650 out_be32(&clockctl->pccr[pscnum], 0x00030000);
650 651
651 if (clockctl->pccr[pscnum] & 0x80) { 652 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
652 clk->rate = spdif_rxclk.rate; 653 clk->rate = spdif_rxclk.rate;
653 return; 654 return;
654 } 655 }
655 656
656 switch ((clockctl->pccr[pscnum] >> 14) & 0x3) { 657 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
657 case 0: 658 case 0:
658 mclk_src = sys_clk.rate; 659 mclk_src = sys_clk.rate;
659 break; 660 break;
@@ -668,7 +669,7 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
668 break; 669 break;
669 } 670 }
670 671
671 mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1; 672 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
672 clk->rate = mclk_src / mclk_div; 673 clk->rate = mclk_src / mclk_div;
673} 674}
674 675
@@ -680,13 +681,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
680static void psc_clks_init(void) 681static void psc_clks_init(void)
681{ 682{
682 struct device_node *np; 683 struct device_node *np;
683 const u32 *cell_index;
684 struct platform_device *ofdev; 684 struct platform_device *ofdev;
685 u32 reg;
685 686
686 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") { 687 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
687 cell_index = of_get_property(np, "cell-index", NULL); 688 if (!of_property_read_u32(np, "reg", &reg)) {
688 if (cell_index) { 689 int pscnum = (reg & 0xf00) >> 8;
689 int pscnum = *cell_index;
690 struct clk *clk = psc_dev_clk(pscnum); 690 struct clk *clk = psc_dev_clk(pscnum);
691 691
692 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL; 692 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
@@ -696,7 +696,7 @@ static void psc_clks_init(void)
696 * AC97 is special rate clock does 696 * AC97 is special rate clock does
697 * not go through normal path 697 * not go through normal path
698 */ 698 */
699 if (strcmp("ac97", np->name) == 0) 699 if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
700 clk->rate = ac97_clk.rate; 700 clk->rate = ac97_clk.rate;
701 else 701 else
702 psc_calc_rate(clk, pscnum, np); 702 psc_calc_rate(clk, pscnum, np);
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index c7f47cfa9c29..d30235b7e3f7 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -426,8 +426,38 @@ void __init mpc512x_psc_fifo_init(void)
426 426
427void __init mpc512x_init(void) 427void __init mpc512x_init(void)
428{ 428{
429 mpc512x_declare_of_platform_devices();
430 mpc5121_clk_init(); 429 mpc5121_clk_init();
430 mpc512x_declare_of_platform_devices();
431 mpc512x_restart_init(); 431 mpc512x_restart_init();
432 mpc512x_psc_fifo_init(); 432 mpc512x_psc_fifo_init();
433} 433}
434
435/**
436 * mpc512x_cs_config - Setup chip select configuration
437 * @cs: chip select number
438 * @val: chip select configuration value
439 *
440 * Perform chip select configuration for devices on LocalPlus Bus.
441 * Intended to dynamically reconfigure the chip select parameters
442 * for configurable devices on the bus.
443 */
444int mpc512x_cs_config(unsigned int cs, u32 val)
445{
446 static struct mpc512x_lpc __iomem *lpc;
447 struct device_node *np;
448
449 if (cs > 7)
450 return -EINVAL;
451
452 if (!lpc) {
453 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-lpc");
454 lpc = of_iomap(np, 0);
455 of_node_put(np);
456 if (!lpc)
457 return -ENOMEM;
458 }
459
460 out_be32(&lpc->cs_cfg[cs], val);
461 return 0;
462}
463EXPORT_SYMBOL(mpc512x_cs_config);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
index f9f4537f546d..be7b1aa4d54c 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -20,9 +20,9 @@
20#include <asm/mpc52xx.h> 20#include <asm/mpc52xx.h>
21#include <asm/time.h> 21#include <asm/time.h>
22 22
23#include <sysdev/bestcomm/bestcomm.h> 23#include <linux/fsl/bestcomm/bestcomm.h>
24#include <sysdev/bestcomm/bestcomm_priv.h> 24#include <linux/fsl/bestcomm/bestcomm_priv.h>
25#include <sysdev/bestcomm/gen_bd.h> 25#include <linux/fsl/bestcomm/gen_bd.h>
26 26
27MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 27MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
28MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver"); 28MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 48a920d51489..52de8bccfb30 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -352,8 +352,6 @@ config OF_RTC
352 Uses information from the OF or flattened device tree to instantiate 352 Uses information from the OF or flattened device tree to instantiate
353 platform devices for direct mapped RTC chips like the DS1742 or DS1743. 353 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
354 354
355source "arch/powerpc/sysdev/bestcomm/Kconfig"
356
357config SIMPLE_GPIO 355config SIMPLE_GPIO
358 bool "Support for simple, memory-mapped GPIO controllers" 356 bool "Support for simple, memory-mapped GPIO controllers"
359 depends on PPC 357 depends on PPC
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index eca3d19304c7..b0a518e97599 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
26obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o 26obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
27obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 27obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
28obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 28obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
29obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
30mv64x60-$(CONFIG_PCI) += mv64x60_pci.o 29mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
31obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \ 30obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
32 mv64x60_udbg.o 31 mv64x60_udbg.o
diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c b/arch/powerpc/sysdev/mpc5xxx_clocks.c
index 96f815a55dfd..5492dc5f56f4 100644
--- a/arch/powerpc/sysdev/mpc5xxx_clocks.c
+++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c
@@ -9,9 +9,9 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/of_platform.h> 10#include <linux/of_platform.h>
11#include <linux/export.h> 11#include <linux/export.h>
12#include <asm/mpc5xxx.h>
12 13
13unsigned int 14unsigned long mpc5xxx_get_bus_frequency(struct device_node *node)
14mpc5xxx_get_bus_frequency(struct device_node *node)
15{ 15{
16 struct device_node *np; 16 struct device_node *np;
17 const unsigned int *p_bus_freq = NULL; 17 const unsigned int *p_bus_freq = NULL;
diff --git a/drivers/Makefile b/drivers/Makefile
index 7863b9fee50b..d8372ab2e4cf 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_PNP) += pnp/
29obj-y += amba/ 29obj-y += amba/
30# Many drivers will want to use DMA so this has to be made available 30# Many drivers will want to use DMA so this has to be made available
31# really early. 31# really early.
32obj-$(CONFIG_DMA_ENGINE) += dma/ 32obj-$(CONFIG_DMADEVICES) += dma/
33 33
34obj-$(CONFIG_VIRTIO) += virtio/ 34obj-$(CONFIG_VIRTIO) += virtio/
35obj-$(CONFIG_XEN) += xen/ 35obj-$(CONFIG_XEN) += xen/
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
index 652f57e83484..3a8fb28b71f2 100644
--- a/drivers/ata/pata_mpc52xx.c
+++ b/drivers/ata/pata_mpc52xx.c
@@ -26,9 +26,9 @@
26#include <asm/prom.h> 26#include <asm/prom.h>
27#include <asm/mpc52xx.h> 27#include <asm/mpc52xx.h>
28 28
29#include <sysdev/bestcomm/bestcomm.h> 29#include <linux/fsl/bestcomm/bestcomm.h>
30#include <sysdev/bestcomm/bestcomm_priv.h> 30#include <linux/fsl/bestcomm/bestcomm_priv.h>
31#include <sysdev/bestcomm/ata.h> 31#include <linux/fsl/bestcomm/ata.h>
32 32
33#define DRV_NAME "mpc52xx_ata" 33#define DRV_NAME "mpc52xx_ata"
34 34
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d4c12180c654..40179e749f08 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -125,6 +125,8 @@ config MPC512X_DMA
125 ---help--- 125 ---help---
126 Enable support for the Freescale MPC512x built-in DMA engine. 126 Enable support for the Freescale MPC512x built-in DMA engine.
127 127
128source "drivers/dma/bestcomm/Kconfig"
129
128config MV_XOR 130config MV_XOR
129 bool "Marvell XOR engine support" 131 bool "Marvell XOR engine support"
130 depends on PLAT_ORION 132 depends on PLAT_ORION
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7428feaa8705..642d96736cf5 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioat/
10obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o 10obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
11obj-$(CONFIG_FSL_DMA) += fsldma.o 11obj-$(CONFIG_FSL_DMA) += fsldma.o
12obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o 12obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
13obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
13obj-$(CONFIG_MV_XOR) += mv_xor.o 14obj-$(CONFIG_MV_XOR) += mv_xor.o
14obj-$(CONFIG_DW_DMAC) += dw_dmac.o 15obj-$(CONFIG_DW_DMAC) += dw_dmac.o
15obj-$(CONFIG_AT_HDMAC) += at_hdmac.o 16obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
diff --git a/arch/powerpc/sysdev/bestcomm/Kconfig b/drivers/dma/bestcomm/Kconfig
index 29e427085efb..29e427085efb 100644
--- a/arch/powerpc/sysdev/bestcomm/Kconfig
+++ b/drivers/dma/bestcomm/Kconfig
diff --git a/arch/powerpc/sysdev/bestcomm/Makefile b/drivers/dma/bestcomm/Makefile
index aed2df2a6580..aed2df2a6580 100644
--- a/arch/powerpc/sysdev/bestcomm/Makefile
+++ b/drivers/dma/bestcomm/Makefile
diff --git a/arch/powerpc/sysdev/bestcomm/ata.c b/drivers/dma/bestcomm/ata.c
index 901c9f91e5dd..2fd87f83cf90 100644
--- a/arch/powerpc/sysdev/bestcomm/ata.c
+++ b/drivers/dma/bestcomm/ata.c
@@ -18,9 +18,9 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <asm/io.h> 19#include <asm/io.h>
20 20
21#include "bestcomm.h" 21#include <linux/fsl/bestcomm/bestcomm.h>
22#include "bestcomm_priv.h" 22#include <linux/fsl/bestcomm/bestcomm_priv.h>
23#include "ata.h" 23#include <linux/fsl/bestcomm/ata.h>
24 24
25 25
26/* ======================================================================== */ 26/* ======================================================================== */
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_ata_task.c b/drivers/dma/bestcomm/bcom_ata_task.c
index cc6049a4e469..cc6049a4e469 100644
--- a/arch/powerpc/sysdev/bestcomm/bcom_ata_task.c
+++ b/drivers/dma/bestcomm/bcom_ata_task.c
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c b/drivers/dma/bestcomm/bcom_fec_rx_task.c
index a1ad6a02fcef..a1ad6a02fcef 100644
--- a/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c
+++ b/drivers/dma/bestcomm/bcom_fec_rx_task.c
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c b/drivers/dma/bestcomm/bcom_fec_tx_task.c
index b1c495c3a65a..b1c495c3a65a 100644
--- a/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c
+++ b/drivers/dma/bestcomm/bcom_fec_tx_task.c
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c b/drivers/dma/bestcomm/bcom_gen_bd_rx_task.c
index efee022b0256..efee022b0256 100644
--- a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_rx_task.c
+++ b/drivers/dma/bestcomm/bcom_gen_bd_rx_task.c
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c b/drivers/dma/bestcomm/bcom_gen_bd_tx_task.c
index c605aa42ecbb..c605aa42ecbb 100644
--- a/arch/powerpc/sysdev/bestcomm/bcom_gen_bd_tx_task.c
+++ b/drivers/dma/bestcomm/bcom_gen_bd_tx_task.c
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.c b/drivers/dma/bestcomm/bestcomm.c
index d9130630f7ef..3a1894603282 100644
--- a/arch/powerpc/sysdev/bestcomm/bestcomm.c
+++ b/drivers/dma/bestcomm/bestcomm.c
@@ -23,9 +23,9 @@
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/mpc52xx.h> 24#include <asm/mpc52xx.h>
25 25
26#include "sram.h" 26#include <linux/fsl/bestcomm/sram.h>
27#include "bestcomm_priv.h" 27#include <linux/fsl/bestcomm/bestcomm_priv.h>
28#include "bestcomm.h" 28#include "linux/fsl/bestcomm/bestcomm.h"
29 29
30#define DRIVER_NAME "bestcomm-core" 30#define DRIVER_NAME "bestcomm-core"
31 31
diff --git a/arch/powerpc/sysdev/bestcomm/fec.c b/drivers/dma/bestcomm/fec.c
index 957a988d23ea..7f1fb1c999e4 100644
--- a/arch/powerpc/sysdev/bestcomm/fec.c
+++ b/drivers/dma/bestcomm/fec.c
@@ -16,9 +16,9 @@
16#include <linux/types.h> 16#include <linux/types.h>
17#include <asm/io.h> 17#include <asm/io.h>
18 18
19#include "bestcomm.h" 19#include <linux/fsl/bestcomm/bestcomm.h>
20#include "bestcomm_priv.h" 20#include <linux/fsl/bestcomm/bestcomm_priv.h>
21#include "fec.h" 21#include <linux/fsl/bestcomm/fec.h>
22 22
23 23
24/* ======================================================================== */ 24/* ======================================================================== */
diff --git a/arch/powerpc/sysdev/bestcomm/gen_bd.c b/drivers/dma/bestcomm/gen_bd.c
index e0a53e3147b2..1a5b22d88127 100644
--- a/arch/powerpc/sysdev/bestcomm/gen_bd.c
+++ b/drivers/dma/bestcomm/gen_bd.c
@@ -21,9 +21,9 @@
21#include <asm/mpc52xx.h> 21#include <asm/mpc52xx.h>
22#include <asm/mpc52xx_psc.h> 22#include <asm/mpc52xx_psc.h>
23 23
24#include "bestcomm.h" 24#include <linux/fsl/bestcomm/bestcomm.h>
25#include "bestcomm_priv.h" 25#include <linux/fsl/bestcomm/bestcomm_priv.h>
26#include "gen_bd.h" 26#include <linux/fsl/bestcomm/gen_bd.h>
27 27
28 28
29/* ======================================================================== */ 29/* ======================================================================== */
diff --git a/arch/powerpc/sysdev/bestcomm/sram.c b/drivers/dma/bestcomm/sram.c
index b6db23e085fb..5e2ed30ba2c4 100644
--- a/arch/powerpc/sysdev/bestcomm/sram.c
+++ b/drivers/dma/bestcomm/sram.c
@@ -23,7 +23,7 @@
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/mmu.h> 24#include <asm/mmu.h>
25 25
26#include "sram.h" 26#include <linux/fsl/bestcomm/sram.h>
27 27
28 28
29/* Struct keeping our 'state' */ 29/* Struct keeping our 'state' */
diff --git a/drivers/net/ethernet/freescale/fec_mpc52xx.c b/drivers/net/ethernet/freescale/fec_mpc52xx.c
index 817d081d2cd8..85e776d500a6 100644
--- a/drivers/net/ethernet/freescale/fec_mpc52xx.c
+++ b/drivers/net/ethernet/freescale/fec_mpc52xx.c
@@ -40,8 +40,8 @@
40#include <asm/delay.h> 40#include <asm/delay.h>
41#include <asm/mpc52xx.h> 41#include <asm/mpc52xx.h>
42 42
43#include <sysdev/bestcomm/bestcomm.h> 43#include <linux/fsl/bestcomm/bestcomm.h>
44#include <sysdev/bestcomm/fec.h> 44#include <linux/fsl/bestcomm/fec.h>
45 45
46#include "fec_mpc52xx.h" 46#include "fec_mpc52xx.h"
47 47
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index 19cfd7a92563..41fbd9453c5f 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -944,7 +944,7 @@ static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
944#define PF_COMP_0_MASK 0x0000000F 944#define PF_COMP_0_MASK 0x0000000F
945#define PF_COMP_0_SHIFT 0 945#define PF_COMP_0_SHIFT 0
946 946
947#define MAKE_PF(alpha, red, blue, green, size, c0, c1, c2, c3) \ 947#define MAKE_PF(alpha, red, green, blue, size, c0, c1, c2, c3) \
948 cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \ 948 cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
949 (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \ 949 (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
950 (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \ 950 (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
@@ -954,10 +954,10 @@ static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
954 switch (bits_per_pixel) { 954 switch (bits_per_pixel) {
955 case 32: 955 case 32:
956 /* 0x88883316 */ 956 /* 0x88883316 */
957 return MAKE_PF(3, 2, 0, 1, 3, 8, 8, 8, 8); 957 return MAKE_PF(3, 2, 1, 0, 3, 8, 8, 8, 8);
958 case 24: 958 case 24:
959 /* 0x88082219 */ 959 /* 0x88082219 */
960 return MAKE_PF(4, 0, 1, 2, 2, 0, 8, 8, 8); 960 return MAKE_PF(4, 0, 1, 2, 2, 8, 8, 8, 0);
961 case 16: 961 case 16:
962 /* 0x65053118 */ 962 /* 0x65053118 */
963 return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0); 963 return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
@@ -1232,6 +1232,16 @@ static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
1232 return 0; 1232 return 0;
1233} 1233}
1234 1234
1235static inline void fsl_diu_enable_interrupts(struct fsl_diu_data *data)
1236{
1237 u32 int_mask = INT_UNDRUN; /* enable underrun detection */
1238
1239 if (IS_ENABLED(CONFIG_NOT_COHERENT_CACHE))
1240 int_mask |= INT_VSYNC; /* enable vertical sync */
1241
1242 clrbits32(&data->diu_reg->int_mask, int_mask);
1243}
1244
1235/* turn on fb if count == 1 1245/* turn on fb if count == 1
1236 */ 1246 */
1237static int fsl_diu_open(struct fb_info *info, int user) 1247static int fsl_diu_open(struct fb_info *info, int user)
@@ -1251,19 +1261,7 @@ static int fsl_diu_open(struct fb_info *info, int user)
1251 if (res < 0) 1261 if (res < 0)
1252 mfbi->count--; 1262 mfbi->count--;
1253 else { 1263 else {
1254 struct fsl_diu_data *data = mfbi->parent; 1264 fsl_diu_enable_interrupts(mfbi->parent);
1255
1256#ifdef CONFIG_NOT_COHERENT_CACHE
1257 /*
1258 * Enable underrun detection and vertical sync
1259 * interrupts.
1260 */
1261 clrbits32(&data->diu_reg->int_mask,
1262 INT_UNDRUN | INT_VSYNC);
1263#else
1264 /* Enable underrun detection */
1265 clrbits32(&data->diu_reg->int_mask, INT_UNDRUN);
1266#endif
1267 fsl_diu_enable_panel(info); 1265 fsl_diu_enable_panel(info);
1268 } 1266 }
1269 } 1267 }
@@ -1283,9 +1281,18 @@ static int fsl_diu_release(struct fb_info *info, int user)
1283 mfbi->count--; 1281 mfbi->count--;
1284 if (mfbi->count == 0) { 1282 if (mfbi->count == 0) {
1285 struct fsl_diu_data *data = mfbi->parent; 1283 struct fsl_diu_data *data = mfbi->parent;
1284 bool disable = true;
1285 int i;
1286 1286
1287 /* Disable interrupts */ 1287 /* Disable interrupts only if all AOIs are closed */
1288 out_be32(&data->diu_reg->int_mask, 0xffffffff); 1288 for (i = 0; i < NUM_AOIS; i++) {
1289 struct mfb_info *mi = data->fsl_diu_info[i].par;
1290
1291 if (mi->count)
1292 disable = false;
1293 }
1294 if (disable)
1295 out_be32(&data->diu_reg->int_mask, 0xffffffff);
1289 fsl_diu_disable_panel(info); 1296 fsl_diu_disable_panel(info);
1290 } 1297 }
1291 1298
@@ -1614,14 +1621,6 @@ static int fsl_diu_probe(struct platform_device *pdev)
1614 out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr); 1621 out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
1615 out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr); 1622 out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
1616 1623
1617 for (i = 0; i < NUM_AOIS; i++) {
1618 ret = install_fb(&data->fsl_diu_info[i]);
1619 if (ret) {
1620 dev_err(&pdev->dev, "could not register fb %d\n", i);
1621 goto error;
1622 }
1623 }
1624
1625 /* 1624 /*
1626 * Older versions of U-Boot leave interrupts enabled, so disable 1625 * Older versions of U-Boot leave interrupts enabled, so disable
1627 * all of them and clear the status register. 1626 * all of them and clear the status register.
@@ -1630,12 +1629,21 @@ static int fsl_diu_probe(struct platform_device *pdev)
1630 in_be32(&data->diu_reg->int_status); 1629 in_be32(&data->diu_reg->int_status);
1631 1630
1632 ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb", 1631 ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb",
1633 &data->diu_reg); 1632 data->diu_reg);
1634 if (ret) { 1633 if (ret) {
1635 dev_err(&pdev->dev, "could not claim irq\n"); 1634 dev_err(&pdev->dev, "could not claim irq\n");
1636 goto error; 1635 goto error;
1637 } 1636 }
1638 1637
1638 for (i = 0; i < NUM_AOIS; i++) {
1639 ret = install_fb(&data->fsl_diu_info[i]);
1640 if (ret) {
1641 dev_err(&pdev->dev, "could not register fb %d\n", i);
1642 free_irq(data->irq, data->diu_reg);
1643 goto error;
1644 }
1645 }
1646
1639 sysfs_attr_init(&data->dev_attr.attr); 1647 sysfs_attr_init(&data->dev_attr.attr);
1640 data->dev_attr.attr.name = "monitor"; 1648 data->dev_attr.attr.name = "monitor";
1641 data->dev_attr.attr.mode = S_IRUGO|S_IWUSR; 1649 data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
@@ -1667,7 +1675,7 @@ static int fsl_diu_remove(struct platform_device *pdev)
1667 data = dev_get_drvdata(&pdev->dev); 1675 data = dev_get_drvdata(&pdev->dev);
1668 disable_lcdc(&data->fsl_diu_info[0]); 1676 disable_lcdc(&data->fsl_diu_info[0]);
1669 1677
1670 free_irq(data->irq, &data->diu_reg); 1678 free_irq(data->irq, data->diu_reg);
1671 1679
1672 for (i = 0; i < NUM_AOIS; i++) 1680 for (i = 0; i < NUM_AOIS; i++)
1673 uninstall_fb(&data->fsl_diu_info[i]); 1681 uninstall_fb(&data->fsl_diu_info[i]);
diff --git a/arch/powerpc/sysdev/bestcomm/ata.h b/include/linux/fsl/bestcomm/ata.h
index 0b2371811334..0b2371811334 100644
--- a/arch/powerpc/sysdev/bestcomm/ata.h
+++ b/include/linux/fsl/bestcomm/ata.h
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.h b/include/linux/fsl/bestcomm/bestcomm.h
index a0e2e6b19b57..a0e2e6b19b57 100644
--- a/arch/powerpc/sysdev/bestcomm/bestcomm.h
+++ b/include/linux/fsl/bestcomm/bestcomm.h
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h b/include/linux/fsl/bestcomm/bestcomm_priv.h
index 3b52f3ffbdf8..3b52f3ffbdf8 100644
--- a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h
+++ b/include/linux/fsl/bestcomm/bestcomm_priv.h
diff --git a/arch/powerpc/sysdev/bestcomm/fec.h b/include/linux/fsl/bestcomm/fec.h
index ee565d94d503..ee565d94d503 100644
--- a/arch/powerpc/sysdev/bestcomm/fec.h
+++ b/include/linux/fsl/bestcomm/fec.h
diff --git a/arch/powerpc/sysdev/bestcomm/gen_bd.h b/include/linux/fsl/bestcomm/gen_bd.h
index de47260e69da..de47260e69da 100644
--- a/arch/powerpc/sysdev/bestcomm/gen_bd.h
+++ b/include/linux/fsl/bestcomm/gen_bd.h
diff --git a/arch/powerpc/sysdev/bestcomm/sram.h b/include/linux/fsl/bestcomm/sram.h
index b6d668963cce..b6d668963cce 100644
--- a/arch/powerpc/sysdev/bestcomm/sram.h
+++ b/include/linux/fsl/bestcomm/sram.h
diff --git a/sound/soc/fsl/mpc5200_dma.c b/sound/soc/fsl/mpc5200_dma.c
index 9997c039bb24..2a847ca494b5 100644
--- a/sound/soc/fsl/mpc5200_dma.c
+++ b/sound/soc/fsl/mpc5200_dma.c
@@ -14,8 +14,8 @@
14 14
15#include <sound/soc.h> 15#include <sound/soc.h>
16 16
17#include <sysdev/bestcomm/bestcomm.h> 17#include <linux/fsl/bestcomm/bestcomm.h>
18#include <sysdev/bestcomm/gen_bd.h> 18#include <linux/fsl/bestcomm/gen_bd.h>
19#include <asm/mpc52xx_psc.h> 19#include <asm/mpc52xx_psc.h>
20 20
21#include "mpc5200_dma.h" 21#include "mpc5200_dma.h"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 23:57:21 -0500