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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-tegra/include/mach/io.h46
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h3
-rw-r--r--arch/arm/mach-tegra/pcie.c95
4 files changed, 25 insertions, 120 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8fb7e4af28ed..ac446e3d802a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -644,7 +644,6 @@ config ARCH_TEGRA
644 select HAVE_CLK 644 select HAVE_CLK
645 select HAVE_SMP 645 select HAVE_SMP
646 select MIGHT_HAVE_CACHE_L2X0 646 select MIGHT_HAVE_CACHE_L2X0
647 select NEED_MACH_IO_H if PCI
648 select ARCH_HAS_CPUFREQ 647 select ARCH_HAS_CPUFREQ
649 help 648 help
650 This enables support for NVIDIA Tegra based systems (Tegra APX, 649 This enables support for NVIDIA Tegra based systems (Tegra APX,
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644
index fe700f9ce7dc..000000000000
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/io.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IO_H
22#define __MACH_TEGRA_IO_H
23
24#define IO_SPACE_LIMIT 0xffff
25
26#ifndef __ASSEMBLER__
27
28#ifdef CONFIG_TEGRA_PCI
29extern void __iomem *tegra_pcie_io_base;
30
31static inline void __iomem *__io(unsigned long addr)
32{
33 return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
34}
35#else
36static inline void __iomem *__io(unsigned long addr)
37{
38 return (void __iomem *)addr;
39}
40#endif
41
42#define __io(a) __io(a)
43
44#endif
45
46#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 7e76da73121c..fee3a94c4549 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -303,6 +303,9 @@
303#define IO_APB_VIRT IOMEM(0xFE300000) 303#define IO_APB_VIRT IOMEM(0xFE300000)
304#define IO_APB_SIZE SZ_1M 304#define IO_APB_SIZE SZ_1M
305 305
306#define TEGRA_PCIE_BASE 0x80000000
307#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
308
306#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 309#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
307#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 310#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
308 311
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 0e09137506ec..e483be8c6f04 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
171 * 0x90000000 - 0x9fffffff - non-prefetchable memory 171 * 0x90000000 - 0x9fffffff - non-prefetchable memory
172 * 0xa0000000 - 0xbfffffff - prefetchable memory 172 * 0xa0000000 - 0xbfffffff - prefetchable memory
173 */ 173 */
174#define TEGRA_PCIE_BASE 0x80000000
175
176#define PCIE_REGS_SZ SZ_16K 174#define PCIE_REGS_SZ SZ_16K
177#define PCIE_CFG_OFF PCIE_REGS_SZ 175#define PCIE_CFG_OFF PCIE_REGS_SZ
178#define PCIE_CFG_SZ SZ_1M 176#define PCIE_CFG_SZ SZ_1M
@@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
180#define PCIE_EXT_CFG_SZ SZ_1M 178#define PCIE_EXT_CFG_SZ SZ_1M
181#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) 179#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
182 180
183#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M)
184#define MMIO_SIZE SZ_64K
185#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) 181#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
186#define MEM_SIZE_0 SZ_128M 182#define MEM_SIZE_0 SZ_128M
187#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) 183#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
@@ -204,10 +200,9 @@ struct tegra_pcie_port {
204 200
205 bool link_up; 201 bool link_up;
206 202
207 char io_space_name[16];
208 char mem_space_name[16]; 203 char mem_space_name[16];
209 char prefetch_space_name[20]; 204 char prefetch_space_name[20];
210 struct resource res[3]; 205 struct resource res[2];
211}; 206};
212 207
213struct tegra_pcie_info { 208struct tegra_pcie_info {
@@ -223,17 +218,7 @@ struct tegra_pcie_info {
223 struct clk *pll_e; 218 struct clk *pll_e;
224}; 219};
225 220
226static struct tegra_pcie_info tegra_pcie = { 221static struct tegra_pcie_info tegra_pcie;
227 .res_mmio = {
228 .name = "PCI IO",
229 .start = MMIO_BASE,
230 .end = MMIO_BASE + MMIO_SIZE - 1,
231 .flags = IORESOURCE_MEM,
232 },
233};
234
235void __iomem *tegra_pcie_io_base;
236EXPORT_SYMBOL(tegra_pcie_io_base);
237 222
238static inline void afi_writel(u32 value, unsigned long offset) 223static inline void afi_writel(u32 value, unsigned long offset)
239{ 224{
@@ -391,24 +376,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
391 pp = tegra_pcie.port + nr; 376 pp = tegra_pcie.port + nr;
392 pp->root_bus_nr = sys->busnr; 377 pp->root_bus_nr = sys->busnr;
393 378
394 /* 379 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
395 * IORESOURCE_IO
396 */
397 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
398 "PCIe %d I/O", pp->index);
399 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
400 pp->res[0].name = pp->io_space_name;
401 if (pp->index == 0) {
402 pp->res[0].start = PCIBIOS_MIN_IO;
403 pp->res[0].end = pp->res[0].start + SZ_32K - 1;
404 } else {
405 pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
406 pp->res[0].end = IO_SPACE_LIMIT;
407 }
408 pp->res[0].flags = IORESOURCE_IO;
409 if (request_resource(&ioport_resource, &pp->res[0]))
410 panic("Request PCIe IO resource failed\n");
411 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
412 380
413 /* 381 /*
414 * IORESOURCE_MEM 382 * IORESOURCE_MEM
@@ -416,18 +384,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
416 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 384 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
417 "PCIe %d MEM", pp->index); 385 "PCIe %d MEM", pp->index);
418 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 386 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
419 pp->res[1].name = pp->mem_space_name; 387 pp->res[0].name = pp->mem_space_name;
420 if (pp->index == 0) { 388 if (pp->index == 0) {
421 pp->res[1].start = MEM_BASE_0; 389 pp->res[0].start = MEM_BASE_0;
422 pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; 390 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
423 } else { 391 } else {
424 pp->res[1].start = MEM_BASE_1; 392 pp->res[0].start = MEM_BASE_1;
425 pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; 393 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
426 } 394 }
427 pp->res[1].flags = IORESOURCE_MEM; 395 pp->res[0].flags = IORESOURCE_MEM;
428 if (request_resource(&iomem_resource, &pp->res[1])) 396 if (request_resource(&iomem_resource, &pp->res[0]))
429 panic("Request PCIe Memory resource failed\n"); 397 panic("Request PCIe Memory resource failed\n");
430 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); 398 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
431 399
432 /* 400 /*
433 * IORESOURCE_MEM | IORESOURCE_PREFETCH 401 * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -435,18 +403,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
435 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), 403 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
436 "PCIe %d PREFETCH MEM", pp->index); 404 "PCIe %d PREFETCH MEM", pp->index);
437 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; 405 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
438 pp->res[2].name = pp->prefetch_space_name; 406 pp->res[1].name = pp->prefetch_space_name;
439 if (pp->index == 0) { 407 if (pp->index == 0) {
440 pp->res[2].start = PREFETCH_MEM_BASE_0; 408 pp->res[1].start = PREFETCH_MEM_BASE_0;
441 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; 409 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
442 } else { 410 } else {
443 pp->res[2].start = PREFETCH_MEM_BASE_1; 411 pp->res[1].start = PREFETCH_MEM_BASE_1;
444 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; 412 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
445 } 413 }
446 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 414 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (request_resource(&iomem_resource, &pp->res[2])) 415 if (request_resource(&iomem_resource, &pp->res[1]))
448 panic("Request PCIe Prefetch Memory resource failed\n"); 416 panic("Request PCIe Prefetch Memory resource failed\n");
449 pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset); 417 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
450 418
451 return 1; 419 return 1;
452} 420}
@@ -541,8 +509,8 @@ static void tegra_pcie_setup_translations(void)
541 509
542 /* Bar 2: downstream IO bar */ 510 /* Bar 2: downstream IO bar */
543 fpci_bar = ((__u32)0xfdfc << 16); 511 fpci_bar = ((__u32)0xfdfc << 16);
544 size = MMIO_SIZE; 512 size = SZ_128K;
545 axi_address = MMIO_BASE; 513 axi_address = TEGRA_PCIE_IO_BASE;
546 afi_writel(axi_address, AFI_AXI_BAR2_START); 514 afi_writel(axi_address, AFI_AXI_BAR2_START);
547 afi_writel(size >> 12, AFI_AXI_BAR2_SZ); 515 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
548 afi_writel(fpci_bar, AFI_FPCI_BAR2); 516 afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -776,7 +744,6 @@ static void tegra_pcie_clocks_put(void)
776 744
777static int __init tegra_pcie_get_resources(void) 745static int __init tegra_pcie_get_resources(void)
778{ 746{
779 struct resource *res_mmio = &tegra_pcie.res_mmio;
780 int err; 747 int err;
781 748
782 err = tegra_pcie_clocks_get(); 749 err = tegra_pcie_clocks_get();
@@ -798,34 +765,16 @@ static int __init tegra_pcie_get_resources(void)
798 goto err_map_reg; 765 goto err_map_reg;
799 } 766 }
800 767
801 err = request_resource(&iomem_resource, res_mmio);
802 if (err) {
803 pr_err("PCIE: Failed to request resources: %d\n", err);
804 goto err_req_io;
805 }
806
807 tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
808 resource_size(res_mmio));
809 if (tegra_pcie_io_base == NULL) {
810 pr_err("PCIE: Failed to map IO\n");
811 err = -ENOMEM;
812 goto err_map_io;
813 }
814
815 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, 768 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
816 IRQF_SHARED, "PCIE", &tegra_pcie); 769 IRQF_SHARED, "PCIE", &tegra_pcie);
817 if (err) { 770 if (err) {
818 pr_err("PCIE: Failed to register IRQ: %d\n", err); 771 pr_err("PCIE: Failed to register IRQ: %d\n", err);
819 goto err_irq; 772 goto err_req_io;
820 } 773 }
821 set_irq_flags(INT_PCIE_INTR, IRQF_VALID); 774 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
822 775
823 return 0; 776 return 0;
824 777
825err_irq:
826 iounmap(tegra_pcie_io_base);
827err_map_io:
828 release_resource(&tegra_pcie.res_mmio);
829err_req_io: 778err_req_io:
830 iounmap(tegra_pcie.regs); 779 iounmap(tegra_pcie.regs);
831err_map_reg: 780err_map_reg: