diff options
-rw-r--r-- | drivers/net/tg3.c | 20 | ||||
-rw-r--r-- | include/linux/pci_regs.h | 1 |
2 files changed, 17 insertions, 4 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 6e86866bd3fa..1dbdd6bb587b 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -68,8 +68,8 @@ | |||
68 | 68 | ||
69 | #define DRV_MODULE_NAME "tg3" | 69 | #define DRV_MODULE_NAME "tg3" |
70 | #define PFX DRV_MODULE_NAME ": " | 70 | #define PFX DRV_MODULE_NAME ": " |
71 | #define DRV_MODULE_VERSION "3.68" | 71 | #define DRV_MODULE_VERSION "3.69" |
72 | #define DRV_MODULE_RELDATE "November 02, 2006" | 72 | #define DRV_MODULE_RELDATE "November 15, 2006" |
73 | 73 | ||
74 | #define TG3_DEF_MAC_MODE 0 | 74 | #define TG3_DEF_MAC_MODE 0 |
75 | #define TG3_DEF_RX_MODE 0 | 75 | #define TG3_DEF_RX_MODE 0 |
@@ -10366,7 +10366,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
10366 | u32 pci_state_reg, grc_misc_cfg; | 10366 | u32 pci_state_reg, grc_misc_cfg; |
10367 | u32 val; | 10367 | u32 val; |
10368 | u16 pci_cmd; | 10368 | u16 pci_cmd; |
10369 | int err; | 10369 | int err, pcie_cap; |
10370 | 10370 | ||
10371 | /* Force memory write invalidate off. If we leave it on, | 10371 | /* Force memory write invalidate off. If we leave it on, |
10372 | * then on 5700_BX chips we have to enable a workaround. | 10372 | * then on 5700_BX chips we have to enable a workaround. |
@@ -10541,8 +10541,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
10541 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) | 10541 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) |
10542 | tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; | 10542 | tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; |
10543 | 10543 | ||
10544 | if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) | 10544 | pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
10545 | if (pcie_cap != 0) { | ||
10545 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; | 10546 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
10547 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | ||
10548 | u16 lnkctl; | ||
10549 | |||
10550 | pci_read_config_word(tp->pdev, | ||
10551 | pcie_cap + PCI_EXP_LNKCTL, | ||
10552 | &lnkctl); | ||
10553 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) | ||
10554 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; | ||
10555 | } | ||
10556 | } | ||
10546 | 10557 | ||
10547 | /* If we have an AMD 762 or VIA K8T800 chipset, write | 10558 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
10548 | * reordering to the mailbox registers done by the host | 10559 | * reordering to the mailbox registers done by the host |
@@ -11809,6 +11820,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, | |||
11809 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 11820 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
11810 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | 11821 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
11811 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 || | 11822 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 || |
11823 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | ||
11812 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | 11824 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { |
11813 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | 11825 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
11814 | } else { | 11826 | } else { |
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index c312a12ad2d6..c321316f1bc7 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
@@ -371,6 +371,7 @@ | |||
371 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ | 371 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
372 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ | 372 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
373 | #define PCI_EXP_LNKCTL 16 /* Link Control */ | 373 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
374 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ | ||
374 | #define PCI_EXP_LNKSTA 18 /* Link Status */ | 375 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
375 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ | 376 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
376 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ | 377 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |