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-rw-r--r--Documentation/arm/Samsung/Overview.txt9
-rwxr-xr-xDocumentation/arm/Samsung/clksrc-change-registers.awk1
-rw-r--r--arch/arm/Kconfig21
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/s5pc100_defconfig49
-rw-r--r--arch/arm/mach-s5pc100/Kconfig81
-rw-r--r--arch/arm/mach-s5pc100/Makefile32
-rw-r--r--arch/arm/mach-s5pc100/Makefile.boot2
-rw-r--r--arch/arm/mach-s5pc100/clock.c1361
-rw-r--r--arch/arm/mach-s5pc100/common.c255
-rw-r--r--arch/arm/mach-s5pc100/common.h30
-rw-r--r--arch/arm/mach-s5pc100/dev-audio.c239
-rw-r--r--arch/arm/mach-s5pc100/dma.c130
-rw-r--r--arch/arm/mach-s5pc100/include/mach/debug-macro.S39
-rw-r--r--arch/arm/mach-s5pc100/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pc100/include/mach/entry-macro.S19
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h144
-rw-r--r--arch/arm/mach-s5pc100/include/mach/hardware.h14
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h115
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h137
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-clock.h80
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h38
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-irq.h18
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c264
-rw-r--r--arch/arm/mach-s5pc100/setup-fb-24bpp.c35
-rw-r--r--arch/arm/mach-s5pc100/setup-i2c0.c28
-rw-r--r--arch/arm/mach-s5pc100/setup-i2c1.c28
-rw-r--r--arch/arm/mach-s5pc100/setup-ide.c57
-rw-r--r--arch/arm/mach-s5pc100/setup-keypad.c23
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci-gpio.c70
-rw-r--r--arch/arm/mach-s5pc100/setup-spi.c41
-rw-r--r--arch/arm/plat-samsung/Kconfig10
-rw-r--r--arch/arm/plat-samsung/adc.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h34
-rw-r--r--drivers/irqchip/Kconfig1
39 files changed, 7 insertions, 3454 deletions
diff --git a/Documentation/arm/Samsung/Overview.txt b/Documentation/arm/Samsung/Overview.txt
index 66edb1e8101a..8f7309bad460 100644
--- a/Documentation/arm/Samsung/Overview.txt
+++ b/Documentation/arm/Samsung/Overview.txt
@@ -13,7 +13,6 @@ Introduction
13 13
14 - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list 14 - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list
15 - S3C64XX: S3C6400 and S3C6410 15 - S3C64XX: S3C6400 and S3C6410
16 - S5PC100
17 - S5PC110 / S5PV210 16 - S5PC110 / S5PV210
18 17
19 18
@@ -33,7 +32,6 @@ Configuration
33 A number of configurations are supplied, as there is no current way of 32 A number of configurations are supplied, as there is no current way of
34 unifying all the SoCs into one kernel. 33 unifying all the SoCs into one kernel.
35 34
36 s5pc100_defconfig - S5PC100 specific default configuration
37 s5pc110_defconfig - S5PC110 specific default configuration 35 s5pc110_defconfig - S5PC110 specific default configuration
38 s5pv210_defconfig - S5PV210 specific default configuration 36 s5pv210_defconfig - S5PV210 specific default configuration
39 37
@@ -65,13 +63,6 @@ Layout changes
65 where to simplify the include and dependency issues involved with having 63 where to simplify the include and dependency issues involved with having
66 so many different platform directories. 64 so many different platform directories.
67 65
68 It was decided to remove plat-s5pc1xx as some of the support was already
69 in plat-s5p or plat-samsung, with the S5PC110 support added with S5PV210
70 the only user was the S5PC100. The S5PC100 specific items where moved to
71 arch/arm/mach-s5pc100.
72
73
74
75 66
76Port Contributors 67Port Contributors
77----------------- 68-----------------
diff --git a/Documentation/arm/Samsung/clksrc-change-registers.awk b/Documentation/arm/Samsung/clksrc-change-registers.awk
index 0c50220851fb..d9174fabe37e 100755
--- a/Documentation/arm/Samsung/clksrc-change-registers.awk
+++ b/Documentation/arm/Samsung/clksrc-change-registers.awk
@@ -68,7 +68,6 @@ BEGIN {
68 68
69 while (getline line < ARGV[1] > 0) { 69 while (getline line < ARGV[1] > 0) {
70 if (line ~ /\#define.*_MASK/ && 70 if (line ~ /\#define.*_MASK/ &&
71 !(line ~ /S5PC100_EPLL_MASK/) &&
72 !(line ~ /USB_SIG_MASK/)) { 71 !(line ~ /USB_SIG_MASK/)) {
73 splitdefine(line, fields) 72 splitdefine(line, fields)
74 name = fields[0] 73 name = fields[0]
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 48be04bb3baf..f4396fd8d6b9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -758,24 +758,6 @@ config ARCH_S3C64XX
758 help 758 help
759 Samsung S3C64XX series based systems 759 Samsung S3C64XX series based systems
760 760
761config ARCH_S5PC100
762 bool "Samsung S5PC100"
763 select ARCH_REQUIRE_GPIOLIB
764 select ATAGS
765 select CLKDEV_LOOKUP
766 select CLKSRC_SAMSUNG_PWM
767 select CPU_V7
768 select GENERIC_CLOCKEVENTS
769 select GPIO_SAMSUNG
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select HAVE_S3C_RTC if RTC_CLASS
773 select NEED_MACH_GPIO_H
774 select SAMSUNG_ATAGS
775 select SAMSUNG_WDT_RESET
776 help
777 Samsung S5PC100 series based systems
778
779config ARCH_S5PV210 761config ARCH_S5PV210
780 bool "Samsung S5PV210/S5PC110" 762 bool "Samsung S5PV210/S5PC110"
781 select ARCH_HAS_HOLES_MEMORYMODEL 763 select ARCH_HAS_HOLES_MEMORYMODEL
@@ -986,8 +968,6 @@ source "arch/arm/mach-s3c24xx/Kconfig"
986 968
987source "arch/arm/mach-s3c64xx/Kconfig" 969source "arch/arm/mach-s3c64xx/Kconfig"
988 970
989source "arch/arm/mach-s5pc100/Kconfig"
990
991source "arch/arm/mach-s5pv210/Kconfig" 971source "arch/arm/mach-s5pv210/Kconfig"
992 972
993source "arch/arm/mach-exynos/Kconfig" 973source "arch/arm/mach-exynos/Kconfig"
@@ -2174,7 +2154,6 @@ menu "Power management options"
2174source "kernel/power/Kconfig" 2154source "kernel/power/Kconfig"
2175 2155
2176config ARCH_SUSPEND_POSSIBLE 2156config ARCH_SUSPEND_POSSIBLE
2177 depends on !ARCH_S5PC100
2178 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2157 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2179 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2158 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2180 def_bool y 2159 def_bool y
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 826b26289be6..d3f470c2201b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -187,7 +187,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
187machine-$(CONFIG_ARCH_RPC) += rpc 187machine-$(CONFIG_ARCH_RPC) += rpc
188machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx 188machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
189machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx 189machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
190machine-$(CONFIG_ARCH_S5PC100) += s5pc100
191machine-$(CONFIG_ARCH_S5PV210) += s5pv210 190machine-$(CONFIG_ARCH_S5PV210) += s5pv210
192machine-$(CONFIG_ARCH_SA1100) += sa1100 191machine-$(CONFIG_ARCH_SA1100) += sa1100
193machine-$(CONFIG_ARCH_SHMOBILE) += shmobile 192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
deleted file mode 100644
index 41bafc94dd85..000000000000
--- a/arch/arm/configs/s5pc100_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSFS_DEPRECATED_V2=y
3CONFIG_BLK_DEV_INITRD=y
4CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5PC100=y
9CONFIG_MACH_SMDKC100=y
10CONFIG_AEABI=y
11CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
12CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
13CONFIG_BLK_DEV_LOOP=y
14CONFIG_BLK_DEV_RAM=y
15CONFIG_BLK_DEV_RAM_SIZE=8192
16CONFIG_EEPROM_AT24=y
17CONFIG_SERIAL_8250=y
18CONFIG_SERIAL_SAMSUNG=y
19CONFIG_SERIAL_SAMSUNG_CONSOLE=y
20CONFIG_HW_RANDOM=y
21CONFIG_I2C=y
22CONFIG_I2C_CHARDEV=y
23# CONFIG_VGA_CONSOLE is not set
24CONFIG_MMC=y
25CONFIG_MMC_DEBUG=y
26CONFIG_MMC_UNSAFE_RESUME=y
27CONFIG_SDIO_UART=y
28CONFIG_MMC_SDHCI=y
29CONFIG_EXT2_FS=y
30CONFIG_EXT3_FS=y
31CONFIG_EXT3_FS_POSIX_ACL=y
32CONFIG_EXT3_FS_SECURITY=y
33CONFIG_INOTIFY=y
34CONFIG_TMPFS=y
35CONFIG_TMPFS_POSIX_ACL=y
36CONFIG_CRAMFS=y
37CONFIG_ROMFS_FS=y
38CONFIG_MAGIC_SYSRQ=y
39CONFIG_DEBUG_KERNEL=y
40CONFIG_DEBUG_RT_MUTEXES=y
41CONFIG_DEBUG_SPINLOCK=y
42CONFIG_DEBUG_MUTEXES=y
43CONFIG_DEBUG_SPINLOCK_SLEEP=y
44CONFIG_DEBUG_INFO=y
45# CONFIG_RCU_CPU_STALL_DETECTOR is not set
46CONFIG_SYSCTL_SYSCALL_CHECK=y
47CONFIG_DEBUG_USER=y
48CONFIG_DEBUG_ERRORS=y
49CONFIG_DEBUG_LL=y
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
deleted file mode 100644
index c5e3a969b063..000000000000
--- a/arch/arm/mach-s5pc100/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
1# Copyright 2009 Samsung Electronics Co.
2# Byungho Min <bhmin@samsung.com>
3#
4# Licensed under GPLv2
5
6# Configuration options for the S5PC100 CPU
7
8if ARCH_S5PC100
9
10config CPU_S5PC100
11 bool
12 select ARM_AMBA
13 select PL330_DMA if DMADEVICES
14 select S5P_EXT_INT
15 help
16 Enable S5PC100 CPU support
17
18config S5PC100_SETUP_FB_24BPP
19 bool
20 help
21 Common setup code for S5PC1XX with an 24bpp RGB display helper.
22
23config S5PC100_SETUP_I2C1
24 bool
25 help
26 Common setup code for i2c bus 1.
27
28config S5PC100_SETUP_IDE
29 bool
30 help
31 Common setup code for S5PC100 IDE GPIO configurations
32
33config S5PC100_SETUP_KEYPAD
34 bool
35 help
36 Common setup code for KEYPAD GPIO configurations.
37
38config S5PC100_SETUP_SDHCI
39 bool
40 select S5PC100_SETUP_SDHCI_GPIO
41 help
42 Internal helper functions for S5PC100 based SDHCI systems
43
44config S5PC100_SETUP_SDHCI_GPIO
45 bool
46 help
47 Common setup code for SDHCI gpio.
48
49config S5PC100_SETUP_SPI
50 bool
51 help
52 Common setup code for SPI GPIO configurations.
53
54config MACH_SMDKC100
55 bool "SMDKC100"
56 select CPU_S5PC100
57 select S3C_DEV_FB
58 select S3C_DEV_HSMMC
59 select S3C_DEV_HSMMC1
60 select S3C_DEV_HSMMC2
61 select S3C_DEV_I2C1
62 select S3C_DEV_RTC
63 select S3C_DEV_WDT
64 select S5PC100_SETUP_FB_24BPP
65 select S5PC100_SETUP_I2C1
66 select S5PC100_SETUP_IDE
67 select S5PC100_SETUP_KEYPAD
68 select S5PC100_SETUP_SDHCI
69 select S5P_DEV_FIMC0
70 select S5P_DEV_FIMC1
71 select S5P_DEV_FIMC2
72 select SAMSUNG_DEV_ADC
73 select SAMSUNG_DEV_BACKLIGHT
74 select SAMSUNG_DEV_IDE
75 select SAMSUNG_DEV_KEYPAD
76 select SAMSUNG_DEV_PWM
77 select SAMSUNG_DEV_TS
78 help
79 Machine support for the Samsung SMDKC100
80
81endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
deleted file mode 100644
index 118c711f74e8..000000000000
--- a/arch/arm/mach-s5pc100/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
1# arch/arm/mach-s5pc100/Makefile
2#
3# Copyright 2009 Samsung Electronics Co.
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12# Core
13
14obj-y += common.o clock.o
15
16obj-y += dma.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
21
22# device support
23
24obj-y += dev-audio.o
25
26obj-y += setup-i2c0.o
27obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
28obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
29obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
30obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
31obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
32obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5pc100/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
deleted file mode 100644
index d0dc10ee7729..000000000000
--- a/arch/arm/mach-s5pc100/clock.c
+++ /dev/null
@@ -1,1361 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PC100 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22
23#include <plat/cpu-freq.h>
24#include <mach/regs-clock.h>
25#include <plat/clock.h>
26#include <plat/cpu.h>
27#include <plat/pll.h>
28#include <plat/s5p-clock.h>
29#include <plat/clock-clksrc.h>
30
31#include "common.h"
32
33static struct clk s5p_clk_otgphy = {
34 .name = "otg_phy",
35};
36
37static struct clk dummy_apb_pclk = {
38 .name = "apb_pclk",
39 .id = -1,
40};
41
42static struct clk *clk_src_mout_href_list[] = {
43 [0] = &s5p_clk_27m,
44 [1] = &clk_fin_hpll,
45};
46
47static struct clksrc_sources clk_src_mout_href = {
48 .sources = clk_src_mout_href_list,
49 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
50};
51
52static struct clksrc_clk clk_mout_href = {
53 .clk = {
54 .name = "mout_href",
55 },
56 .sources = &clk_src_mout_href,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
58};
59
60static struct clk *clk_src_mout_48m_list[] = {
61 [0] = &clk_xusbxti,
62 [1] = &s5p_clk_otgphy,
63};
64
65static struct clksrc_sources clk_src_mout_48m = {
66 .sources = clk_src_mout_48m_list,
67 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
68};
69
70static struct clksrc_clk clk_mout_48m = {
71 .clk = {
72 .name = "mout_48m",
73 },
74 .sources = &clk_src_mout_48m,
75 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
76};
77
78static struct clksrc_clk clk_mout_mpll = {
79 .clk = {
80 .name = "mout_mpll",
81 },
82 .sources = &clk_src_mpll,
83 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
84};
85
86
87static struct clksrc_clk clk_mout_apll = {
88 .clk = {
89 .name = "mout_apll",
90 },
91 .sources = &clk_src_apll,
92 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
93};
94
95static struct clksrc_clk clk_mout_epll = {
96 .clk = {
97 .name = "mout_epll",
98 },
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
101};
102
103static struct clk *clk_src_mout_hpll_list[] = {
104 [0] = &s5p_clk_27m,
105};
106
107static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
110};
111
112static struct clksrc_clk clk_mout_hpll = {
113 .clk = {
114 .name = "mout_hpll",
115 },
116 .sources = &clk_src_mout_hpll,
117 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
118};
119
120static struct clksrc_clk clk_div_apll = {
121 .clk = {
122 .name = "div_apll",
123 .parent = &clk_mout_apll.clk,
124 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
126};
127
128static struct clksrc_clk clk_div_arm = {
129 .clk = {
130 .name = "div_arm",
131 .parent = &clk_div_apll.clk,
132 },
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
134};
135
136static struct clksrc_clk clk_div_d0_bus = {
137 .clk = {
138 .name = "div_d0_bus",
139 .parent = &clk_div_arm.clk,
140 },
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
142};
143
144static struct clksrc_clk clk_div_pclkd0 = {
145 .clk = {
146 .name = "div_pclkd0",
147 .parent = &clk_div_d0_bus.clk,
148 },
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
150};
151
152static struct clksrc_clk clk_div_secss = {
153 .clk = {
154 .name = "div_secss",
155 .parent = &clk_div_d0_bus.clk,
156 },
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
158};
159
160static struct clksrc_clk clk_div_apll2 = {
161 .clk = {
162 .name = "div_apll2",
163 .parent = &clk_mout_apll.clk,
164 },
165 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
166};
167
168static struct clk *clk_src_mout_am_list[] = {
169 [0] = &clk_mout_mpll.clk,
170 [1] = &clk_div_apll2.clk,
171};
172
173static struct clksrc_sources clk_src_mout_am = {
174 .sources = clk_src_mout_am_list,
175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
176};
177
178static struct clksrc_clk clk_mout_am = {
179 .clk = {
180 .name = "mout_am",
181 },
182 .sources = &clk_src_mout_am,
183 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
184};
185
186static struct clksrc_clk clk_div_d1_bus = {
187 .clk = {
188 .name = "div_d1_bus",
189 .parent = &clk_mout_am.clk,
190 },
191 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
192};
193
194static struct clksrc_clk clk_div_mpll2 = {
195 .clk = {
196 .name = "div_mpll2",
197 .parent = &clk_mout_am.clk,
198 },
199 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
200};
201
202static struct clksrc_clk clk_div_mpll = {
203 .clk = {
204 .name = "div_mpll",
205 .parent = &clk_mout_am.clk,
206 },
207 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
208};
209
210static struct clk *clk_src_mout_onenand_list[] = {
211 [0] = &clk_div_d0_bus.clk,
212 [1] = &clk_div_d1_bus.clk,
213};
214
215static struct clksrc_sources clk_src_mout_onenand = {
216 .sources = clk_src_mout_onenand_list,
217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
218};
219
220static struct clksrc_clk clk_mout_onenand = {
221 .clk = {
222 .name = "mout_onenand",
223 },
224 .sources = &clk_src_mout_onenand,
225 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
226};
227
228static struct clksrc_clk clk_div_onenand = {
229 .clk = {
230 .name = "div_onenand",
231 .parent = &clk_mout_onenand.clk,
232 },
233 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
234};
235
236static struct clksrc_clk clk_div_pclkd1 = {
237 .clk = {
238 .name = "div_pclkd1",
239 .parent = &clk_div_d1_bus.clk,
240 },
241 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
242};
243
244static struct clksrc_clk clk_div_cam = {
245 .clk = {
246 .name = "div_cam",
247 .parent = &clk_div_mpll2.clk,
248 },
249 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
250};
251
252static struct clksrc_clk clk_div_hdmi = {
253 .clk = {
254 .name = "div_hdmi",
255 .parent = &clk_mout_hpll.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
258};
259
260static u32 epll_div[][4] = {
261 { 32750000, 131, 3, 4 },
262 { 32768000, 131, 3, 4 },
263 { 36000000, 72, 3, 3 },
264 { 45000000, 90, 3, 3 },
265 { 45158000, 90, 3, 3 },
266 { 45158400, 90, 3, 3 },
267 { 48000000, 96, 3, 3 },
268 { 49125000, 131, 4, 3 },
269 { 49152000, 131, 4, 3 },
270 { 60000000, 120, 3, 3 },
271 { 67737600, 226, 5, 3 },
272 { 67738000, 226, 5, 3 },
273 { 73800000, 246, 5, 3 },
274 { 73728000, 246, 5, 3 },
275 { 72000000, 144, 3, 3 },
276 { 84000000, 168, 3, 3 },
277 { 96000000, 96, 3, 2 },
278 { 144000000, 144, 3, 2 },
279 { 192000000, 96, 3, 1 }
280};
281
282static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
283{
284 unsigned int epll_con;
285 unsigned int i;
286
287 if (clk->rate == rate) /* Return if nothing changed */
288 return 0;
289
290 epll_con = __raw_readl(S5P_EPLL_CON);
291
292 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
293
294 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
295 if (epll_div[i][0] == rate) {
296 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
297 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
298 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
299 break;
300 }
301 }
302
303 if (i == ARRAY_SIZE(epll_div)) {
304 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
305 return -EINVAL;
306 }
307
308 __raw_writel(epll_con, S5P_EPLL_CON);
309
310 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
311 clk->rate, rate);
312
313 clk->rate = rate;
314
315 return 0;
316}
317
318static struct clk_ops s5pc100_epll_ops = {
319 .get_rate = s5p_epll_get_rate,
320 .set_rate = s5pc100_epll_set_rate,
321};
322
323static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
324{
325 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
326}
327
328static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
329{
330 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
331}
332
333static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
334{
335 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
336}
337
338static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
339{
340 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
341}
342
343static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
344{
345 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
346}
347
348static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
349{
350 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
351}
352
353static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
354{
355 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
356}
357
358static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
359{
360 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
361}
362
363static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
364{
365 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
366}
367
368static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
369{
370 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
371}
372
373static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
374{
375 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
376}
377
378/*
379 * The following clocks will be disabled during clock initialization. It is
380 * recommended to keep the following clocks disabled until the driver requests
381 * for enabling the clock.
382 */
383static struct clk init_clocks_off[] = {
384 {
385 .name = "cssys",
386 .parent = &clk_div_d0_bus.clk,
387 .enable = s5pc100_d0_0_ctrl,
388 .ctrlbit = (1 << 6),
389 }, {
390 .name = "secss",
391 .parent = &clk_div_d0_bus.clk,
392 .enable = s5pc100_d0_0_ctrl,
393 .ctrlbit = (1 << 5),
394 }, {
395 .name = "g2d",
396 .parent = &clk_div_d0_bus.clk,
397 .enable = s5pc100_d0_0_ctrl,
398 .ctrlbit = (1 << 4),
399 }, {
400 .name = "mdma",
401 .parent = &clk_div_d0_bus.clk,
402 .enable = s5pc100_d0_0_ctrl,
403 .ctrlbit = (1 << 3),
404 }, {
405 .name = "cfcon",
406 .parent = &clk_div_d0_bus.clk,
407 .enable = s5pc100_d0_0_ctrl,
408 .ctrlbit = (1 << 2),
409 }, {
410 .name = "nfcon",
411 .parent = &clk_div_d0_bus.clk,
412 .enable = s5pc100_d0_1_ctrl,
413 .ctrlbit = (1 << 3),
414 }, {
415 .name = "onenandc",
416 .parent = &clk_div_d0_bus.clk,
417 .enable = s5pc100_d0_1_ctrl,
418 .ctrlbit = (1 << 2),
419 }, {
420 .name = "sdm",
421 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_2_ctrl,
423 .ctrlbit = (1 << 2),
424 }, {
425 .name = "seckey",
426 .parent = &clk_div_d0_bus.clk,
427 .enable = s5pc100_d0_2_ctrl,
428 .ctrlbit = (1 << 1),
429 }, {
430 .name = "modemif",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 4),
434 }, {
435 .name = "otg",
436 .parent = &clk_div_d1_bus.clk,
437 .enable = s5pc100_d1_0_ctrl,
438 .ctrlbit = (1 << 3),
439 }, {
440 .name = "usbhost",
441 .parent = &clk_div_d1_bus.clk,
442 .enable = s5pc100_d1_0_ctrl,
443 .ctrlbit = (1 << 2),
444 }, {
445 .name = "dma",
446 .devname = "dma-pl330.1",
447 .parent = &clk_div_d1_bus.clk,
448 .enable = s5pc100_d1_0_ctrl,
449 .ctrlbit = (1 << 1),
450 }, {
451 .name = "dma",
452 .devname = "dma-pl330.0",
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
455 .ctrlbit = (1 << 0),
456 }, {
457 .name = "lcd",
458 .parent = &clk_div_d1_bus.clk,
459 .enable = s5pc100_d1_1_ctrl,
460 .ctrlbit = (1 << 0),
461 }, {
462 .name = "rotator",
463 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_1_ctrl,
465 .ctrlbit = (1 << 1),
466 }, {
467 .name = "fimc",
468 .devname = "s5p-fimc.0",
469 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_1_ctrl,
471 .ctrlbit = (1 << 2),
472 }, {
473 .name = "fimc",
474 .devname = "s5p-fimc.1",
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
477 .ctrlbit = (1 << 3),
478 }, {
479 .name = "fimc",
480 .devname = "s5p-fimc.2",
481 .enable = s5pc100_d1_1_ctrl,
482 .ctrlbit = (1 << 4),
483 }, {
484 .name = "jpeg",
485 .parent = &clk_div_d1_bus.clk,
486 .enable = s5pc100_d1_1_ctrl,
487 .ctrlbit = (1 << 5),
488 }, {
489 .name = "mipi-dsim",
490 .parent = &clk_div_d1_bus.clk,
491 .enable = s5pc100_d1_1_ctrl,
492 .ctrlbit = (1 << 6),
493 }, {
494 .name = "mipi-csis",
495 .parent = &clk_div_d1_bus.clk,
496 .enable = s5pc100_d1_1_ctrl,
497 .ctrlbit = (1 << 7),
498 }, {
499 .name = "g3d",
500 .parent = &clk_div_d1_bus.clk,
501 .enable = s5pc100_d1_0_ctrl,
502 .ctrlbit = (1 << 8),
503 }, {
504 .name = "tv",
505 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_2_ctrl,
507 .ctrlbit = (1 << 0),
508 }, {
509 .name = "vp",
510 .parent = &clk_div_d1_bus.clk,
511 .enable = s5pc100_d1_2_ctrl,
512 .ctrlbit = (1 << 1),
513 }, {
514 .name = "mixer",
515 .parent = &clk_div_d1_bus.clk,
516 .enable = s5pc100_d1_2_ctrl,
517 .ctrlbit = (1 << 2),
518 }, {
519 .name = "hdmi",
520 .parent = &clk_div_d1_bus.clk,
521 .enable = s5pc100_d1_2_ctrl,
522 .ctrlbit = (1 << 3),
523 }, {
524 .name = "mfc",
525 .parent = &clk_div_d1_bus.clk,
526 .enable = s5pc100_d1_2_ctrl,
527 .ctrlbit = (1 << 4),
528 }, {
529 .name = "apc",
530 .parent = &clk_div_d1_bus.clk,
531 .enable = s5pc100_d1_3_ctrl,
532 .ctrlbit = (1 << 2),
533 }, {
534 .name = "iec",
535 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_3_ctrl,
537 .ctrlbit = (1 << 3),
538 }, {
539 .name = "systimer",
540 .parent = &clk_div_d1_bus.clk,
541 .enable = s5pc100_d1_3_ctrl,
542 .ctrlbit = (1 << 7),
543 }, {
544 .name = "watchdog",
545 .parent = &clk_div_d1_bus.clk,
546 .enable = s5pc100_d1_3_ctrl,
547 .ctrlbit = (1 << 8),
548 }, {
549 .name = "rtc",
550 .parent = &clk_div_d1_bus.clk,
551 .enable = s5pc100_d1_3_ctrl,
552 .ctrlbit = (1 << 9),
553 }, {
554 .name = "i2c",
555 .devname = "s3c2440-i2c.0",
556 .parent = &clk_div_d1_bus.clk,
557 .enable = s5pc100_d1_4_ctrl,
558 .ctrlbit = (1 << 4),
559 }, {
560 .name = "i2c",
561 .devname = "s3c2440-i2c.1",
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_4_ctrl,
564 .ctrlbit = (1 << 5),
565 }, {
566 .name = "spi",
567 .devname = "s5pc100-spi.0",
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl,
570 .ctrlbit = (1 << 6),
571 }, {
572 .name = "spi",
573 .devname = "s5pc100-spi.1",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
576 .ctrlbit = (1 << 7),
577 }, {
578 .name = "spi",
579 .devname = "s5pc100-spi.2",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
582 .ctrlbit = (1 << 8),
583 }, {
584 .name = "irda",
585 .parent = &clk_div_d1_bus.clk,
586 .enable = s5pc100_d1_4_ctrl,
587 .ctrlbit = (1 << 9),
588 }, {
589 .name = "ccan",
590 .parent = &clk_div_d1_bus.clk,
591 .enable = s5pc100_d1_4_ctrl,
592 .ctrlbit = (1 << 10),
593 }, {
594 .name = "ccan",
595 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_4_ctrl,
597 .ctrlbit = (1 << 11),
598 }, {
599 .name = "hsitx",
600 .parent = &clk_div_d1_bus.clk,
601 .enable = s5pc100_d1_4_ctrl,
602 .ctrlbit = (1 << 12),
603 }, {
604 .name = "hsirx",
605 .parent = &clk_div_d1_bus.clk,
606 .enable = s5pc100_d1_4_ctrl,
607 .ctrlbit = (1 << 13),
608 }, {
609 .name = "ac97",
610 .parent = &clk_div_pclkd1.clk,
611 .enable = s5pc100_d1_5_ctrl,
612 .ctrlbit = (1 << 3),
613 }, {
614 .name = "pcm",
615 .devname = "samsung-pcm.0",
616 .parent = &clk_div_pclkd1.clk,
617 .enable = s5pc100_d1_5_ctrl,
618 .ctrlbit = (1 << 4),
619 }, {
620 .name = "pcm",
621 .devname = "samsung-pcm.1",
622 .parent = &clk_div_pclkd1.clk,
623 .enable = s5pc100_d1_5_ctrl,
624 .ctrlbit = (1 << 5),
625 }, {
626 .name = "spdif",
627 .parent = &clk_div_pclkd1.clk,
628 .enable = s5pc100_d1_5_ctrl,
629 .ctrlbit = (1 << 6),
630 }, {
631 .name = "adc",
632 .parent = &clk_div_pclkd1.clk,
633 .enable = s5pc100_d1_5_ctrl,
634 .ctrlbit = (1 << 7),
635 }, {
636 .name = "keypad",
637 .parent = &clk_div_pclkd1.clk,
638 .enable = s5pc100_d1_5_ctrl,
639 .ctrlbit = (1 << 8),
640 }, {
641 .name = "mmc_48m",
642 .devname = "s3c-sdhci.0",
643 .parent = &clk_mout_48m.clk,
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = (1 << 15),
646 }, {
647 .name = "mmc_48m",
648 .devname = "s3c-sdhci.1",
649 .parent = &clk_mout_48m.clk,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = (1 << 16),
652 }, {
653 .name = "mmc_48m",
654 .devname = "s3c-sdhci.2",
655 .parent = &clk_mout_48m.clk,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = (1 << 17),
658 },
659};
660
661static struct clk clk_hsmmc2 = {
662 .name = "hsmmc",
663 .devname = "s3c-sdhci.2",
664 .parent = &clk_div_d1_bus.clk,
665 .enable = s5pc100_d1_0_ctrl,
666 .ctrlbit = (1 << 7),
667};
668
669static struct clk clk_hsmmc1 = {
670 .name = "hsmmc",
671 .devname = "s3c-sdhci.1",
672 .parent = &clk_div_d1_bus.clk,
673 .enable = s5pc100_d1_0_ctrl,
674 .ctrlbit = (1 << 6),
675};
676
677static struct clk clk_hsmmc0 = {
678 .name = "hsmmc",
679 .devname = "s3c-sdhci.0",
680 .parent = &clk_div_d1_bus.clk,
681 .enable = s5pc100_d1_0_ctrl,
682 .ctrlbit = (1 << 5),
683};
684
685static struct clk clk_48m_spi0 = {
686 .name = "spi_48m",
687 .devname = "s5pc100-spi.0",
688 .parent = &clk_mout_48m.clk,
689 .enable = s5pc100_sclk0_ctrl,
690 .ctrlbit = (1 << 7),
691};
692
693static struct clk clk_48m_spi1 = {
694 .name = "spi_48m",
695 .devname = "s5pc100-spi.1",
696 .parent = &clk_mout_48m.clk,
697 .enable = s5pc100_sclk0_ctrl,
698 .ctrlbit = (1 << 8),
699};
700
701static struct clk clk_48m_spi2 = {
702 .name = "spi_48m",
703 .devname = "s5pc100-spi.2",
704 .parent = &clk_mout_48m.clk,
705 .enable = s5pc100_sclk0_ctrl,
706 .ctrlbit = (1 << 9),
707};
708
709static struct clk clk_i2s0 = {
710 .name = "iis",
711 .devname = "samsung-i2s.0",
712 .parent = &clk_div_pclkd1.clk,
713 .enable = s5pc100_d1_5_ctrl,
714 .ctrlbit = (1 << 0),
715};
716
717static struct clk clk_i2s1 = {
718 .name = "iis",
719 .devname = "samsung-i2s.1",
720 .parent = &clk_div_pclkd1.clk,
721 .enable = s5pc100_d1_5_ctrl,
722 .ctrlbit = (1 << 1),
723};
724
725static struct clk clk_i2s2 = {
726 .name = "iis",
727 .devname = "samsung-i2s.2",
728 .parent = &clk_div_pclkd1.clk,
729 .enable = s5pc100_d1_5_ctrl,
730 .ctrlbit = (1 << 2),
731};
732
733static struct clk clk_vclk54m = {
734 .name = "vclk_54m",
735 .rate = 54000000,
736};
737
738static struct clk clk_i2scdclk0 = {
739 .name = "i2s_cdclk0",
740};
741
742static struct clk clk_i2scdclk1 = {
743 .name = "i2s_cdclk1",
744};
745
746static struct clk clk_i2scdclk2 = {
747 .name = "i2s_cdclk2",
748};
749
750static struct clk clk_pcmcdclk0 = {
751 .name = "pcm_cdclk0",
752};
753
754static struct clk clk_pcmcdclk1 = {
755 .name = "pcm_cdclk1",
756};
757
758static struct clk *clk_src_group1_list[] = {
759 [0] = &clk_mout_epll.clk,
760 [1] = &clk_div_mpll2.clk,
761 [2] = &clk_fin_epll,
762 [3] = &clk_mout_hpll.clk,
763};
764
765static struct clksrc_sources clk_src_group1 = {
766 .sources = clk_src_group1_list,
767 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
768};
769
770static struct clk *clk_src_group2_list[] = {
771 [0] = &clk_mout_epll.clk,
772 [1] = &clk_div_mpll.clk,
773};
774
775static struct clksrc_sources clk_src_group2 = {
776 .sources = clk_src_group2_list,
777 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
778};
779
780static struct clk *clk_src_group3_list[] = {
781 [0] = &clk_mout_epll.clk,
782 [1] = &clk_div_mpll.clk,
783 [2] = &clk_fin_epll,
784 [3] = &clk_i2scdclk0,
785 [4] = &clk_pcmcdclk0,
786 [5] = &clk_mout_hpll.clk,
787};
788
789static struct clksrc_sources clk_src_group3 = {
790 .sources = clk_src_group3_list,
791 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
792};
793
794static struct clksrc_clk clk_sclk_audio0 = {
795 .clk = {
796 .name = "sclk_audio",
797 .devname = "samsung-pcm.0",
798 .ctrlbit = (1 << 8),
799 .enable = s5pc100_sclk1_ctrl,
800 },
801 .sources = &clk_src_group3,
802 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
803 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
804};
805
806static struct clk *clk_src_group4_list[] = {
807 [0] = &clk_mout_epll.clk,
808 [1] = &clk_div_mpll.clk,
809 [2] = &clk_fin_epll,
810 [3] = &clk_i2scdclk1,
811 [4] = &clk_pcmcdclk1,
812 [5] = &clk_mout_hpll.clk,
813};
814
815static struct clksrc_sources clk_src_group4 = {
816 .sources = clk_src_group4_list,
817 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
818};
819
820static struct clksrc_clk clk_sclk_audio1 = {
821 .clk = {
822 .name = "sclk_audio",
823 .devname = "samsung-pcm.1",
824 .ctrlbit = (1 << 9),
825 .enable = s5pc100_sclk1_ctrl,
826 },
827 .sources = &clk_src_group4,
828 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
830};
831
832static struct clk *clk_src_group5_list[] = {
833 [0] = &clk_mout_epll.clk,
834 [1] = &clk_div_mpll.clk,
835 [2] = &clk_fin_epll,
836 [3] = &clk_i2scdclk2,
837 [4] = &clk_mout_hpll.clk,
838};
839
840static struct clksrc_sources clk_src_group5 = {
841 .sources = clk_src_group5_list,
842 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
843};
844
845static struct clksrc_clk clk_sclk_audio2 = {
846 .clk = {
847 .name = "sclk_audio",
848 .devname = "samsung-pcm.2",
849 .ctrlbit = (1 << 10),
850 .enable = s5pc100_sclk1_ctrl,
851 },
852 .sources = &clk_src_group5,
853 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
854 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
855};
856
857static struct clk *clk_src_group6_list[] = {
858 [0] = &s5p_clk_27m,
859 [1] = &clk_vclk54m,
860 [2] = &clk_div_hdmi.clk,
861};
862
863static struct clksrc_sources clk_src_group6 = {
864 .sources = clk_src_group6_list,
865 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
866};
867
868static struct clk *clk_src_group7_list[] = {
869 [0] = &clk_mout_epll.clk,
870 [1] = &clk_div_mpll.clk,
871 [2] = &clk_mout_hpll.clk,
872 [3] = &clk_vclk54m,
873};
874
875static struct clksrc_sources clk_src_group7 = {
876 .sources = clk_src_group7_list,
877 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
878};
879
880static struct clk *clk_src_mmc0_list[] = {
881 [0] = &clk_mout_epll.clk,
882 [1] = &clk_div_mpll.clk,
883 [2] = &clk_fin_epll,
884};
885
886static struct clksrc_sources clk_src_mmc0 = {
887 .sources = clk_src_mmc0_list,
888 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
889};
890
891static struct clk *clk_src_mmc12_list[] = {
892 [0] = &clk_mout_epll.clk,
893 [1] = &clk_div_mpll.clk,
894 [2] = &clk_fin_epll,
895 [3] = &clk_mout_hpll.clk,
896};
897
898static struct clksrc_sources clk_src_mmc12 = {
899 .sources = clk_src_mmc12_list,
900 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
901};
902
903static struct clk *clk_src_irda_usb_list[] = {
904 [0] = &clk_mout_epll.clk,
905 [1] = &clk_div_mpll.clk,
906 [2] = &clk_fin_epll,
907 [3] = &clk_mout_hpll.clk,
908};
909
910static struct clksrc_sources clk_src_irda_usb = {
911 .sources = clk_src_irda_usb_list,
912 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
913};
914
915static struct clk *clk_src_pwi_list[] = {
916 [0] = &clk_fin_epll,
917 [1] = &clk_mout_epll.clk,
918 [2] = &clk_div_mpll.clk,
919};
920
921static struct clksrc_sources clk_src_pwi = {
922 .sources = clk_src_pwi_list,
923 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
924};
925
926static struct clk *clk_sclk_spdif_list[] = {
927 [0] = &clk_sclk_audio0.clk,
928 [1] = &clk_sclk_audio1.clk,
929 [2] = &clk_sclk_audio2.clk,
930};
931
932static struct clksrc_sources clk_src_sclk_spdif = {
933 .sources = clk_sclk_spdif_list,
934 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
935};
936
937static struct clksrc_clk clk_sclk_spdif = {
938 .clk = {
939 .name = "sclk_spdif",
940 .ctrlbit = (1 << 11),
941 .enable = s5pc100_sclk1_ctrl,
942 .ops = &s5p_sclk_spdif_ops,
943 },
944 .sources = &clk_src_sclk_spdif,
945 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
946};
947
948static struct clksrc_clk clksrcs[] = {
949 {
950 .clk = {
951 .name = "sclk_mixer",
952 .ctrlbit = (1 << 6),
953 .enable = s5pc100_sclk0_ctrl,
954
955 },
956 .sources = &clk_src_group6,
957 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
958 }, {
959 .clk = {
960 .name = "sclk_lcd",
961 .ctrlbit = (1 << 0),
962 .enable = s5pc100_sclk1_ctrl,
963
964 },
965 .sources = &clk_src_group7,
966 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
967 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
968 }, {
969 .clk = {
970 .name = "sclk_fimc",
971 .devname = "s5p-fimc.0",
972 .ctrlbit = (1 << 1),
973 .enable = s5pc100_sclk1_ctrl,
974
975 },
976 .sources = &clk_src_group7,
977 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
978 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
979 }, {
980 .clk = {
981 .name = "sclk_fimc",
982 .devname = "s5p-fimc.1",
983 .ctrlbit = (1 << 2),
984 .enable = s5pc100_sclk1_ctrl,
985
986 },
987 .sources = &clk_src_group7,
988 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
989 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
990 }, {
991 .clk = {
992 .name = "sclk_fimc",
993 .devname = "s5p-fimc.2",
994 .ctrlbit = (1 << 3),
995 .enable = s5pc100_sclk1_ctrl,
996
997 },
998 .sources = &clk_src_group7,
999 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1000 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1001 }, {
1002 .clk = {
1003 .name = "sclk_irda",
1004 .ctrlbit = (1 << 10),
1005 .enable = s5pc100_sclk0_ctrl,
1006
1007 },
1008 .sources = &clk_src_irda_usb,
1009 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1010 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1011 }, {
1012 .clk = {
1013 .name = "sclk_irda",
1014 .ctrlbit = (1 << 10),
1015 .enable = s5pc100_sclk0_ctrl,
1016
1017 },
1018 .sources = &clk_src_mmc12,
1019 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1020 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1021 }, {
1022 .clk = {
1023 .name = "sclk_pwi",
1024 .ctrlbit = (1 << 1),
1025 .enable = s5pc100_sclk0_ctrl,
1026
1027 },
1028 .sources = &clk_src_pwi,
1029 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1030 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1031 }, {
1032 .clk = {
1033 .name = "sclk_uhost",
1034 .ctrlbit = (1 << 11),
1035 .enable = s5pc100_sclk0_ctrl,
1036
1037 },
1038 .sources = &clk_src_irda_usb,
1039 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1040 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1041 },
1042};
1043
1044static struct clksrc_clk clk_sclk_uart = {
1045 .clk = {
1046 .name = "uclk1",
1047 .ctrlbit = (1 << 3),
1048 .enable = s5pc100_sclk0_ctrl,
1049 },
1050 .sources = &clk_src_group2,
1051 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1052 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1053};
1054
1055static struct clksrc_clk clk_sclk_mmc0 = {
1056 .clk = {
1057 .name = "sclk_mmc",
1058 .devname = "s3c-sdhci.0",
1059 .ctrlbit = (1 << 12),
1060 .enable = s5pc100_sclk1_ctrl,
1061 },
1062 .sources = &clk_src_mmc0,
1063 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1064 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1065};
1066
1067static struct clksrc_clk clk_sclk_mmc1 = {
1068 .clk = {
1069 .name = "sclk_mmc",
1070 .devname = "s3c-sdhci.1",
1071 .ctrlbit = (1 << 13),
1072 .enable = s5pc100_sclk1_ctrl,
1073 },
1074 .sources = &clk_src_mmc12,
1075 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1076 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1077};
1078
1079static struct clksrc_clk clk_sclk_mmc2 = {
1080 .clk = {
1081 .name = "sclk_mmc",
1082 .devname = "s3c-sdhci.2",
1083 .ctrlbit = (1 << 14),
1084 .enable = s5pc100_sclk1_ctrl,
1085 },
1086 .sources = &clk_src_mmc12,
1087 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1088 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1089};
1090
1091static struct clksrc_clk clk_sclk_spi0 = {
1092 .clk = {
1093 .name = "sclk_spi",
1094 .devname = "s5pc100-spi.0",
1095 .ctrlbit = (1 << 4),
1096 .enable = s5pc100_sclk0_ctrl,
1097 },
1098 .sources = &clk_src_group1,
1099 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1100 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1101};
1102
1103static struct clksrc_clk clk_sclk_spi1 = {
1104 .clk = {
1105 .name = "sclk_spi",
1106 .devname = "s5pc100-spi.1",
1107 .ctrlbit = (1 << 5),
1108 .enable = s5pc100_sclk0_ctrl,
1109 },
1110 .sources = &clk_src_group1,
1111 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1112 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1113};
1114
1115static struct clksrc_clk clk_sclk_spi2 = {
1116 .clk = {
1117 .name = "sclk_spi",
1118 .devname = "s5pc100-spi.2",
1119 .ctrlbit = (1 << 6),
1120 .enable = s5pc100_sclk0_ctrl,
1121 },
1122 .sources = &clk_src_group1,
1123 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1124 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1125};
1126
1127/* Clock initialisation code */
1128static struct clksrc_clk *sysclks[] = {
1129 &clk_mout_apll,
1130 &clk_mout_epll,
1131 &clk_mout_mpll,
1132 &clk_mout_hpll,
1133 &clk_mout_href,
1134 &clk_mout_48m,
1135 &clk_div_apll,
1136 &clk_div_arm,
1137 &clk_div_d0_bus,
1138 &clk_div_pclkd0,
1139 &clk_div_secss,
1140 &clk_div_apll2,
1141 &clk_mout_am,
1142 &clk_div_d1_bus,
1143 &clk_div_mpll2,
1144 &clk_div_mpll,
1145 &clk_mout_onenand,
1146 &clk_div_onenand,
1147 &clk_div_pclkd1,
1148 &clk_div_cam,
1149 &clk_div_hdmi,
1150 &clk_sclk_audio0,
1151 &clk_sclk_audio1,
1152 &clk_sclk_audio2,
1153 &clk_sclk_spdif,
1154};
1155
1156static struct clk *clk_cdev[] = {
1157 &clk_hsmmc0,
1158 &clk_hsmmc1,
1159 &clk_hsmmc2,
1160 &clk_48m_spi0,
1161 &clk_48m_spi1,
1162 &clk_48m_spi2,
1163 &clk_i2s0,
1164 &clk_i2s1,
1165 &clk_i2s2,
1166};
1167
1168static struct clksrc_clk *clksrc_cdev[] = {
1169 &clk_sclk_uart,
1170 &clk_sclk_mmc0,
1171 &clk_sclk_mmc1,
1172 &clk_sclk_mmc2,
1173 &clk_sclk_spi0,
1174 &clk_sclk_spi1,
1175 &clk_sclk_spi2,
1176};
1177
1178void __init_or_cpufreq s5pc100_setup_clocks(void)
1179{
1180 unsigned long xtal;
1181 unsigned long arm;
1182 unsigned long hclkd0;
1183 unsigned long hclkd1;
1184 unsigned long pclkd0;
1185 unsigned long pclkd1;
1186 unsigned long apll;
1187 unsigned long mpll;
1188 unsigned long epll;
1189 unsigned long hpll;
1190 unsigned int ptr;
1191
1192 /* Set S5PC100 functions for clk_fout_epll */
1193 clk_fout_epll.enable = s5p_epll_enable;
1194 clk_fout_epll.ops = &s5pc100_epll_ops;
1195
1196 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1197
1198 xtal = clk_get_rate(&clk_xtal);
1199
1200 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1201
1202 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1203 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1204 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1205 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1206
1207 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1208 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1209
1210 clk_fout_apll.rate = apll;
1211 clk_fout_mpll.rate = mpll;
1212 clk_fout_epll.rate = epll;
1213 clk_mout_hpll.clk.rate = hpll;
1214
1215 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1216 s3c_set_clksrc(&clksrcs[ptr], true);
1217
1218 arm = clk_get_rate(&clk_div_arm.clk);
1219 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1220 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1221 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1222 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1223
1224 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1225 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1226
1227 clk_f.rate = arm;
1228 clk_h.rate = hclkd1;
1229 clk_p.rate = pclkd1;
1230}
1231
1232/*
1233 * The following clocks will be enabled during clock initialization.
1234 */
1235static struct clk init_clocks[] = {
1236 {
1237 .name = "tzic",
1238 .parent = &clk_div_d0_bus.clk,
1239 .enable = s5pc100_d0_0_ctrl,
1240 .ctrlbit = (1 << 1),
1241 }, {
1242 .name = "intc",
1243 .parent = &clk_div_d0_bus.clk,
1244 .enable = s5pc100_d0_0_ctrl,
1245 .ctrlbit = (1 << 0),
1246 }, {
1247 .name = "ebi",
1248 .parent = &clk_div_d0_bus.clk,
1249 .enable = s5pc100_d0_1_ctrl,
1250 .ctrlbit = (1 << 5),
1251 }, {
1252 .name = "intmem",
1253 .parent = &clk_div_d0_bus.clk,
1254 .enable = s5pc100_d0_1_ctrl,
1255 .ctrlbit = (1 << 4),
1256 }, {
1257 .name = "sromc",
1258 .parent = &clk_div_d0_bus.clk,
1259 .enable = s5pc100_d0_1_ctrl,
1260 .ctrlbit = (1 << 1),
1261 }, {
1262 .name = "dmc",
1263 .parent = &clk_div_d0_bus.clk,
1264 .enable = s5pc100_d0_1_ctrl,
1265 .ctrlbit = (1 << 0),
1266 }, {
1267 .name = "chipid",
1268 .parent = &clk_div_d0_bus.clk,
1269 .enable = s5pc100_d0_1_ctrl,
1270 .ctrlbit = (1 << 0),
1271 }, {
1272 .name = "gpio",
1273 .parent = &clk_div_d1_bus.clk,
1274 .enable = s5pc100_d1_3_ctrl,
1275 .ctrlbit = (1 << 1),
1276 }, {
1277 .name = "uart",
1278 .devname = "s3c6400-uart.0",
1279 .parent = &clk_div_d1_bus.clk,
1280 .enable = s5pc100_d1_4_ctrl,
1281 .ctrlbit = (1 << 0),
1282 }, {
1283 .name = "uart",
1284 .devname = "s3c6400-uart.1",
1285 .parent = &clk_div_d1_bus.clk,
1286 .enable = s5pc100_d1_4_ctrl,
1287 .ctrlbit = (1 << 1),
1288 }, {
1289 .name = "uart",
1290 .devname = "s3c6400-uart.2",
1291 .parent = &clk_div_d1_bus.clk,
1292 .enable = s5pc100_d1_4_ctrl,
1293 .ctrlbit = (1 << 2),
1294 }, {
1295 .name = "uart",
1296 .devname = "s3c6400-uart.3",
1297 .parent = &clk_div_d1_bus.clk,
1298 .enable = s5pc100_d1_4_ctrl,
1299 .ctrlbit = (1 << 3),
1300 }, {
1301 .name = "timers",
1302 .parent = &clk_div_d1_bus.clk,
1303 .enable = s5pc100_d1_3_ctrl,
1304 .ctrlbit = (1 << 6),
1305 },
1306};
1307
1308static struct clk *clks[] __initdata = {
1309 &clk_ext,
1310 &clk_i2scdclk0,
1311 &clk_i2scdclk1,
1312 &clk_i2scdclk2,
1313 &clk_pcmcdclk0,
1314 &clk_pcmcdclk1,
1315};
1316
1317static struct clk_lookup s5pc100_clk_lookup[] = {
1318 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1319 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1320 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1321 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1322 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1323 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1326 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1327 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
1328 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
1330 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1331 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
1332 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1333 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
1334 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
1335 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
1336};
1337
1338void __init s5pc100_register_clocks(void)
1339{
1340 int ptr;
1341
1342 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1343
1344 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1345 s3c_register_clksrc(sysclks[ptr], 1);
1346
1347 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1348 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1349 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1350 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1351
1352 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1353 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1354 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1355
1356 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1357 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1358 s3c_disable_clocks(clk_cdev[ptr], 1);
1359
1360 s3c24xx_register_clock(&dummy_apb_pclk);
1361}
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
deleted file mode 100644
index 6a41bf7dacf6..000000000000
--- a/arch/arm/mach-s5pc100/common.c
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2009 Samsung Electronics Co.
6 * Byungho Min <bhmin@samsung.com>
7 *
8 * Common Codes for S5PC100
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/device.h>
24#include <linux/serial_core.h>
25#include <linux/serial_s3c.h>
26#include <clocksource/samsung_pwm.h>
27#include <linux/platform_device.h>
28#include <linux/sched.h>
29#include <linux/reboot.h>
30
31#include <asm/irq.h>
32#include <asm/proc-fns.h>
33#include <asm/system_misc.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/map.h>
39#include <mach/hardware.h>
40#include <mach/regs-clock.h>
41
42#include <plat/cpu.h>
43#include <plat/devs.h>
44#include <plat/clock.h>
45#include <plat/sdhci.h>
46#include <plat/adc-core.h>
47#include <plat/ata-core.h>
48#include <plat/fb-core.h>
49#include <plat/iic-core.h>
50#include <plat/onenand-core.h>
51#include <plat/pwm-core.h>
52#include <plat/spi-core.h>
53#include <plat/watchdog-reset.h>
54
55#include "common.h"
56
57static const char name_s5pc100[] = "S5PC100";
58
59static struct cpu_table cpu_ids[] __initdata = {
60 {
61 .idcode = S5PC100_CPU_ID,
62 .idmask = S5PC100_CPU_MASK,
63 .map_io = s5pc100_map_io,
64 .init_clocks = s5pc100_init_clocks,
65 .init_uarts = s5pc100_init_uarts,
66 .init = s5pc100_init,
67 .name = name_s5pc100,
68 },
69};
70
71/* Initial IO mappings */
72
73static struct map_desc s5pc100_iodesc[] __initdata = {
74 {
75 .virtual = (unsigned long)S5P_VA_CHIPID,
76 .pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
77 .length = SZ_4K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = (unsigned long)S3C_VA_SYS,
81 .pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
82 .length = SZ_64K,
83 .type = MT_DEVICE,
84 }, {
85 .virtual = (unsigned long)S3C_VA_TIMER,
86 .pfn = __phys_to_pfn(S5PC100_PA_TIMER),
87 .length = SZ_16K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_WATCHDOG,
91 .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S5P_VA_SROMC,
96 .pfn = __phys_to_pfn(S5PC100_PA_SROMC),
97 .length = SZ_4K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S5P_VA_SYSTIMER,
101 .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
102 .length = SZ_16K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_GPIO,
106 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)VA_VIC0,
111 .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
112 .length = SZ_16K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)VA_VIC1,
116 .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
117 .length = SZ_16K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)VA_VIC2,
121 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
122 .length = SZ_16K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S3C_VA_UART,
126 .pfn = __phys_to_pfn(S3C_PA_UART),
127 .length = SZ_512K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S5PC100_VA_OTHERS,
131 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 }
135};
136
137static struct samsung_pwm_variant s5pc100_pwm_variant = {
138 .bits = 32,
139 .div_base = 0,
140 .has_tint_cstat = true,
141 .tclk_mask = (1 << 5),
142};
143
144void __init samsung_set_timer_source(unsigned int event, unsigned int source)
145{
146 s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
147 s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
148}
149
150void __init samsung_timer_init(void)
151{
152 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
153 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
154 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
155 };
156
157 samsung_pwm_clocksource_init(S3C_VA_TIMER,
158 timer_irqs, &s5pc100_pwm_variant);
159}
160
161/*
162 * s5pc100_map_io
163 *
164 * register the standard CPU IO areas
165 */
166
167void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
168{
169 /* initialize the io descriptors we need for initialization */
170 iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
171 if (mach_desc)
172 iotable_init(mach_desc, size);
173
174 /* detect cpu id and rev. */
175 s5p_init_cpu(S5P_VA_CHIPID);
176
177 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
178
179 samsung_pwm_set_platdata(&s5pc100_pwm_variant);
180}
181
182void __init s5pc100_map_io(void)
183{
184 /* initialise device information early */
185 s5pc100_default_sdhci0();
186 s5pc100_default_sdhci1();
187 s5pc100_default_sdhci2();
188
189 s3c_adc_setname("s3c64xx-adc");
190
191 /* the i2c devices are directly compatible with s3c2440 */
192 s3c_i2c0_setname("s3c2440-i2c");
193 s3c_i2c1_setname("s3c2440-i2c");
194
195 s3c_onenand_setname("s5pc100-onenand");
196 s3c_fb_setname("s5pc100-fb");
197 s3c_cfcon_setname("s5pc100-pata");
198
199 s3c64xx_spi_setname("s5pc100-spi");
200}
201
202void __init s5pc100_init_clocks(int xtal)
203{
204 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
205
206 s3c24xx_register_baseclocks(xtal);
207 s5p_register_clocks(xtal);
208 s5pc100_register_clocks();
209 s5pc100_setup_clocks();
210 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
211}
212
213void __init s5pc100_init_irq(void)
214{
215 u32 vic[] = {~0, ~0, ~0};
216
217 /* VIC0, VIC1, and VIC2 are fully populated. */
218 s5p_init_irq(vic, ARRAY_SIZE(vic));
219}
220
221static struct bus_type s5pc100_subsys = {
222 .name = "s5pc100-core",
223 .dev_name = "s5pc100-core",
224};
225
226static struct device s5pc100_dev = {
227 .bus = &s5pc100_subsys,
228};
229
230static int __init s5pc100_core_init(void)
231{
232 return subsys_system_register(&s5pc100_subsys, NULL);
233}
234core_initcall(s5pc100_core_init);
235
236int __init s5pc100_init(void)
237{
238 printk(KERN_INFO "S5PC100: Initializing architecture\n");
239 return device_register(&s5pc100_dev);
240}
241
242/* uart registration process */
243
244void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
245{
246 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
247}
248
249void s5pc100_restart(enum reboot_mode mode, const char *cmd)
250{
251 if (mode != REBOOT_SOFT)
252 samsung_wdt_reset();
253
254 soft_restart(0);
255}
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
deleted file mode 100644
index 08d782d65d7b..000000000000
--- a/arch/arm/mach-s5pc100/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for S5PC100 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
13#define __ARCH_ARM_MACH_S5PC100_COMMON_H
14
15#include <linux/reboot.h>
16
17void s5pc100_init_io(struct map_desc *mach_desc, int size);
18void s5pc100_init_irq(void);
19
20void s5pc100_register_clocks(void);
21void s5pc100_setup_clocks(void);
22
23void s5pc100_restart(enum reboot_mode mode, const char *cmd);
24
25extern int s5pc100_init(void);
26extern void s5pc100_map_io(void);
27extern void s5pc100_init_clocks(int xtal);
28extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29
30#endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
deleted file mode 100644
index 46f488b09391..000000000000
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ /dev/null
@@ -1,239 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <linux/platform_data/asoc-s3c.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5pc100_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case 0: /* Dedicated pins */
27 break;
28 case 1:
29 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
30 break;
31 case 2:
32 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
33 break;
34 default:
35 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
36 return -EINVAL;
37 }
38
39 return 0;
40}
41
42static struct s3c_audio_pdata i2sv5_pdata = {
43 .cfg_gpio = s5pc100_cfg_i2s,
44 .type = {
45 .i2s = {
46 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
47 | QUIRK_NEED_RSTCLR,
48 },
49 },
50};
51
52static struct resource s5pc100_iis0_resource[] = {
53 [0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256),
54 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
55 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
56 [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
57};
58
59struct platform_device s5pc100_device_iis0 = {
60 .name = "samsung-i2s",
61 .id = 0,
62 .num_resources = ARRAY_SIZE(s5pc100_iis0_resource),
63 .resource = s5pc100_iis0_resource,
64 .dev = {
65 .platform_data = &i2sv5_pdata,
66 },
67};
68
69static struct s3c_audio_pdata i2sv3_pdata = {
70 .cfg_gpio = s5pc100_cfg_i2s,
71};
72
73static struct resource s5pc100_iis1_resource[] = {
74 [0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256),
75 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
76 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
77};
78
79struct platform_device s5pc100_device_iis1 = {
80 .name = "samsung-i2s",
81 .id = 1,
82 .num_resources = ARRAY_SIZE(s5pc100_iis1_resource),
83 .resource = s5pc100_iis1_resource,
84 .dev = {
85 .platform_data = &i2sv3_pdata,
86 },
87};
88
89static struct resource s5pc100_iis2_resource[] = {
90 [0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256),
91 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
92 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
93};
94
95struct platform_device s5pc100_device_iis2 = {
96 .name = "samsung-i2s",
97 .id = 2,
98 .num_resources = ARRAY_SIZE(s5pc100_iis2_resource),
99 .resource = s5pc100_iis2_resource,
100 .dev = {
101 .platform_data = &i2sv3_pdata,
102 },
103};
104
105/* PCM Controller platform_devices */
106
107static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
108{
109 switch (pdev->id) {
110 case 0:
111 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
112 break;
113
114 case 1:
115 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
116 break;
117
118 default:
119 printk(KERN_DEBUG "Invalid PCM Controller number!");
120 return -EINVAL;
121 }
122
123 return 0;
124}
125
126static struct s3c_audio_pdata s3c_pcm_pdata = {
127 .cfg_gpio = s5pc100_pcm_cfg_gpio,
128};
129
130static struct resource s5pc100_pcm0_resource[] = {
131 [0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256),
132 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
133 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
134};
135
136struct platform_device s5pc100_device_pcm0 = {
137 .name = "samsung-pcm",
138 .id = 0,
139 .num_resources = ARRAY_SIZE(s5pc100_pcm0_resource),
140 .resource = s5pc100_pcm0_resource,
141 .dev = {
142 .platform_data = &s3c_pcm_pdata,
143 },
144};
145
146static struct resource s5pc100_pcm1_resource[] = {
147 [0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256),
148 [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
149 [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
150};
151
152struct platform_device s5pc100_device_pcm1 = {
153 .name = "samsung-pcm",
154 .id = 1,
155 .num_resources = ARRAY_SIZE(s5pc100_pcm1_resource),
156 .resource = s5pc100_pcm1_resource,
157 .dev = {
158 .platform_data = &s3c_pcm_pdata,
159 },
160};
161
162/* AC97 Controller platform devices */
163
164static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
165{
166 return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
167}
168
169static struct resource s5pc100_ac97_resource[] = {
170 [0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256),
171 [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
172 [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
173 [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
174 [4] = DEFINE_RES_IRQ(IRQ_AC97),
175};
176
177static struct s3c_audio_pdata s3c_ac97_pdata = {
178 .cfg_gpio = s5pc100_ac97_cfg_gpio,
179};
180
181static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32);
182
183struct platform_device s5pc100_device_ac97 = {
184 .name = "samsung-ac97",
185 .id = -1,
186 .num_resources = ARRAY_SIZE(s5pc100_ac97_resource),
187 .resource = s5pc100_ac97_resource,
188 .dev = {
189 .platform_data = &s3c_ac97_pdata,
190 .dma_mask = &s5pc100_ac97_dmamask,
191 .coherent_dma_mask = DMA_BIT_MASK(32),
192 },
193};
194
195/* S/PDIF Controller platform_device */
196static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
197{
198 s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
199
200 return 0;
201}
202
203static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
204{
205 s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
206
207 return 0;
208}
209
210static struct resource s5pc100_spdif_resource[] = {
211 [0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256),
212 [1] = DEFINE_RES_DMA(DMACH_SPDIF),
213};
214
215static struct s3c_audio_pdata s5p_spdif_pdata = {
216 .cfg_gpio = s5pc100_spdif_cfg_gpd,
217};
218
219static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
220
221struct platform_device s5pc100_device_spdif = {
222 .name = "samsung-spdif",
223 .id = -1,
224 .num_resources = ARRAY_SIZE(s5pc100_spdif_resource),
225 .resource = s5pc100_spdif_resource,
226 .dev = {
227 .platform_data = &s5p_spdif_pdata,
228 .dma_mask = &s5pc100_spdif_dmamask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
230 },
231};
232
233void __init s5pc100_spdif_setup_gpio(int gpio)
234{
235 if (gpio == S5PC100_SPDIF_GPD)
236 s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
237 else
238 s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
239}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
deleted file mode 100644
index b1418409709e..000000000000
--- a/arch/arm/mach-s5pc100/dma.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
29#include <plat/devs.h>
30#include <plat/irqs.h>
31
32#include <mach/map.h>
33#include <mach/irqs.h>
34#include <mach/dma.h>
35
36static u8 pdma0_peri[] = {
37 DMACH_UART0_RX,
38 DMACH_UART0_TX,
39 DMACH_UART1_RX,
40 DMACH_UART1_TX,
41 DMACH_UART2_RX,
42 DMACH_UART2_TX,
43 DMACH_UART3_RX,
44 DMACH_UART3_TX,
45 DMACH_IRDA,
46 DMACH_I2S0_RX,
47 DMACH_I2S0_TX,
48 DMACH_I2S0S_TX,
49 DMACH_I2S1_RX,
50 DMACH_I2S1_TX,
51 DMACH_I2S2_RX,
52 DMACH_I2S2_TX,
53 DMACH_SPI0_RX,
54 DMACH_SPI0_TX,
55 DMACH_SPI1_RX,
56 DMACH_SPI1_TX,
57 DMACH_SPI2_RX,
58 DMACH_SPI2_TX,
59 DMACH_AC97_MICIN,
60 DMACH_AC97_PCMIN,
61 DMACH_AC97_PCMOUT,
62 DMACH_EXTERNAL,
63 DMACH_PWM,
64 DMACH_SPDIF,
65 DMACH_HSI_RX,
66 DMACH_HSI_TX,
67};
68
69static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
70 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
71 .peri_id = pdma0_peri,
72};
73
74static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330,
75 S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
76
77static u8 pdma1_peri[] = {
78 DMACH_UART0_RX,
79 DMACH_UART0_TX,
80 DMACH_UART1_RX,
81 DMACH_UART1_TX,
82 DMACH_UART2_RX,
83 DMACH_UART2_TX,
84 DMACH_UART3_RX,
85 DMACH_UART3_TX,
86 DMACH_IRDA,
87 DMACH_I2S0_RX,
88 DMACH_I2S0_TX,
89 DMACH_I2S0S_TX,
90 DMACH_I2S1_RX,
91 DMACH_I2S1_TX,
92 DMACH_I2S2_RX,
93 DMACH_I2S2_TX,
94 DMACH_SPI0_RX,
95 DMACH_SPI0_TX,
96 DMACH_SPI1_RX,
97 DMACH_SPI1_TX,
98 DMACH_SPI2_RX,
99 DMACH_SPI2_TX,
100 DMACH_PCM0_RX,
101 DMACH_PCM0_TX,
102 DMACH_PCM1_RX,
103 DMACH_PCM1_TX,
104 DMACH_MSM_REQ0,
105 DMACH_MSM_REQ1,
106 DMACH_MSM_REQ2,
107 DMACH_MSM_REQ3,
108};
109
110static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
111 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
112 .peri_id = pdma1_peri,
113};
114
115static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
116 S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
117
118static int __init s5pc100_dma_init(void)
119{
120 dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
121 dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
122 amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
123
124 dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
125 dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
126 amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
127
128 return 0;
129}
130arch_initcall(s5pc100_dma_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
deleted file mode 100644
index 22c23859e45e..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/debug-macro.S
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 *
7 * Based on mach-s3c6400/include/mach/debug-macro.S
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* pull in the relevant register and map files. */
15
16#include <linux/serial_s3c.h>
17#include <mach/map.h>
18
19 /* note, for the boot process to work we have to keep the UART
20 * virtual address aligned to an 1MiB boundary for the L1
21 * mapping the head code makes. We keep the UART virtual address
22 * aligned and add in the offset when we load the value here.
23 */
24
25 .macro addruart, rp, rv, tmp
26 ldr \rp, = S3C_PA_UART
27 ldr \rv, = S3C_VA_UART
28#if CONFIG_DEBUG_S3C_UART != 0
29 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
30 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
31#endif
32 .endm
33
34/* include the reset of the code which will do the work, we're only
35 * compiling for a single cpu processor type so the default of s3c2440
36 * will be fine with us.
37 */
38
39#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
deleted file mode 100644
index 201842a3769e..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
deleted file mode 100644
index bad0700457db..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/entry-macro.S
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Based on mach-s3c6400/include/mach/entry-macro.S
7 *
8 * Low-level IRQ helper macros for the Samsung S5PC1XX series
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13*/
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
deleted file mode 100644
index 5e1a924b595f..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/gpio.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - GPIO lib support
7 *
8 * Base on mach-s3c6400/include/mach/gpio.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_GPIO_H
16#define __ASM_ARCH_GPIO_H __FILE__
17
18/* GPIO bank sizes */
19#define S5PC100_GPIO_A0_NR (8)
20#define S5PC100_GPIO_A1_NR (5)
21#define S5PC100_GPIO_B_NR (8)
22#define S5PC100_GPIO_C_NR (5)
23#define S5PC100_GPIO_D_NR (7)
24#define S5PC100_GPIO_E0_NR (8)
25#define S5PC100_GPIO_E1_NR (6)
26#define S5PC100_GPIO_F0_NR (8)
27#define S5PC100_GPIO_F1_NR (8)
28#define S5PC100_GPIO_F2_NR (8)
29#define S5PC100_GPIO_F3_NR (4)
30#define S5PC100_GPIO_G0_NR (8)
31#define S5PC100_GPIO_G1_NR (3)
32#define S5PC100_GPIO_G2_NR (7)
33#define S5PC100_GPIO_G3_NR (7)
34#define S5PC100_GPIO_H0_NR (8)
35#define S5PC100_GPIO_H1_NR (8)
36#define S5PC100_GPIO_H2_NR (8)
37#define S5PC100_GPIO_H3_NR (8)
38#define S5PC100_GPIO_I_NR (8)
39#define S5PC100_GPIO_J0_NR (8)
40#define S5PC100_GPIO_J1_NR (5)
41#define S5PC100_GPIO_J2_NR (8)
42#define S5PC100_GPIO_J3_NR (8)
43#define S5PC100_GPIO_J4_NR (4)
44#define S5PC100_GPIO_K0_NR (8)
45#define S5PC100_GPIO_K1_NR (6)
46#define S5PC100_GPIO_K2_NR (8)
47#define S5PC100_GPIO_K3_NR (8)
48#define S5PC100_GPIO_L0_NR (8)
49#define S5PC100_GPIO_L1_NR (8)
50#define S5PC100_GPIO_L2_NR (8)
51#define S5PC100_GPIO_L3_NR (8)
52#define S5PC100_GPIO_L4_NR (8)
53
54/* GPIO bank numbes */
55
56/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
57 * space for debugging purposes so that any accidental
58 * change from one gpio bank to another can be caught.
59*/
60
61#define S5PC100_GPIO_NEXT(__gpio) \
62 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
63
64enum s5p_gpio_number {
65 S5PC100_GPIO_A0_START = 0,
66 S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
67 S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
68 S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
69 S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
70 S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
71 S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
72 S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
73 S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
74 S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
75 S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
76 S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
77 S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
78 S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
79 S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
80 S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
81 S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
82 S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
83 S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
84 S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
85 S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
86 S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
87 S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
88 S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
89 S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
90 S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
91 S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
92 S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
93 S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
94 S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
95 S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
96 S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
97 S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
98 S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
99 S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
100};
101
102/* S5PC100 GPIO number definitions. */
103#define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr))
104#define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr))
105#define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr))
106#define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr))
107#define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr))
108#define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr))
109#define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr))
110#define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr))
111#define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr))
112#define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr))
113#define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr))
114#define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr))
115#define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr))
116#define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr))
117#define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr))
118#define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr))
119#define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr))
120#define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr))
121#define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr))
122#define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr))
123#define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr))
124#define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr))
125#define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr))
126#define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr))
127#define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr))
128#define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr))
129#define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr))
130#define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr))
131#define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr))
132#define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr))
133#define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr))
134#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr))
135#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr))
136#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr))
137
138/* It used the end of the S5PC100 gpios */
139#define S3C_GPIO_END S5PC100_GPIO_END
140
141/* define the number of gpios we need to the one after the MP04() range */
142#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
143
144#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h
deleted file mode 100644
index 6b38618c2fd9..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/hardware.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - Hardware support
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H __FILE__
11
12/* currently nothing here, placeholder */
13
14#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
deleted file mode 100644
index d2eb4757381f..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - IRQ definitions
7 */
8
9#ifndef __ASM_ARCH_IRQS_H
10#define __ASM_ARCH_IRQS_H __FILE__
11
12#include <plat/irqs.h>
13
14/* VIC0: system, DMA, timer */
15#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
16#define IRQ_BATF S5P_IRQ_VIC0(17)
17#define IRQ_MDMA S5P_IRQ_VIC0(18)
18#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
19#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
20#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
21#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
22#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
23#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
24#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
25#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
26#define IRQ_WDT S5P_IRQ_VIC0(27)
27#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
28#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
29#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
30
31/* VIC1: ARM, power, memory, connectivity */
32#define IRQ_PMU S5P_IRQ_VIC1(0)
33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
36#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
37#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
38#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
39#define IRQ_ONENAND S5P_IRQ_VIC1(7)
40#define IRQ_NFC S5P_IRQ_VIC1(8)
41#define IRQ_CFCON S5P_IRQ_VIC1(9)
42#define IRQ_UART0 S5P_IRQ_VIC1(10)
43#define IRQ_UART1 S5P_IRQ_VIC1(11)
44#define IRQ_UART2 S5P_IRQ_VIC1(12)
45#define IRQ_UART3 S5P_IRQ_VIC1(13)
46#define IRQ_IIC S5P_IRQ_VIC1(14)
47#define IRQ_SPI0 S5P_IRQ_VIC1(15)
48#define IRQ_SPI1 S5P_IRQ_VIC1(16)
49#define IRQ_SPI2 S5P_IRQ_VIC1(17)
50#define IRQ_IRDA S5P_IRQ_VIC1(18)
51#define IRQ_IIC2 S5P_IRQ_VIC1(19)
52#define IRQ_IIC3 S5P_IRQ_VIC1(20)
53#define IRQ_HSIRX S5P_IRQ_VIC1(21)
54#define IRQ_HSITX S5P_IRQ_VIC1(22)
55#define IRQ_UHOST S5P_IRQ_VIC1(23)
56#define IRQ_OTG S5P_IRQ_VIC1(24)
57#define IRQ_MSM S5P_IRQ_VIC1(25)
58#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
59#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
60#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
61#define IRQ_MIPICSI S5P_IRQ_VIC1(29)
62#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
63
64/* VIC2: multimedia, audio, security */
65#define IRQ_LCD0 S5P_IRQ_VIC2(0)
66#define IRQ_LCD1 S5P_IRQ_VIC2(1)
67#define IRQ_LCD2 S5P_IRQ_VIC2(2)
68#define IRQ_LCD3 S5P_IRQ_VIC2(3)
69#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
70#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
71#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
72#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
73#define IRQ_JPEG S5P_IRQ_VIC2(8)
74#define IRQ_2D S5P_IRQ_VIC2(9)
75#define IRQ_3D S5P_IRQ_VIC2(10)
76#define IRQ_MIXER S5P_IRQ_VIC2(11)
77#define IRQ_HDMI S5P_IRQ_VIC2(12)
78#define IRQ_IIC1 S5P_IRQ_VIC2(13)
79#define IRQ_MFC S5P_IRQ_VIC2(14)
80#define IRQ_TVENC S5P_IRQ_VIC2(15)
81#define IRQ_I2S0 S5P_IRQ_VIC2(16)
82#define IRQ_I2S1 S5P_IRQ_VIC2(17)
83#define IRQ_I2S2 S5P_IRQ_VIC2(18)
84#define IRQ_AC97 S5P_IRQ_VIC2(19)
85#define IRQ_PCM0 S5P_IRQ_VIC2(20)
86#define IRQ_PCM1 S5P_IRQ_VIC2(21)
87#define IRQ_SPDIF S5P_IRQ_VIC2(22)
88#define IRQ_ADC S5P_IRQ_VIC2(23)
89#define IRQ_PENDN S5P_IRQ_VIC2(24)
90#define IRQ_TC IRQ_PENDN
91#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
92#define IRQ_CG S5P_IRQ_VIC2(26)
93#define IRQ_SEC S5P_IRQ_VIC2(27)
94#define IRQ_SECRX S5P_IRQ_VIC2(28)
95#define IRQ_SECTX S5P_IRQ_VIC2(29)
96#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102
103/* GPIO interrupt */
104#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
105#define S5P_GPIOINT_GROUP_MAXNR 21
106
107/* Set the default NR_IRQS */
108#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
109
110/* Compatibility */
111#define IRQ_LCD_FIFO IRQ_LCD0
112#define IRQ_LCD_VSYNC IRQ_LCD1
113#define IRQ_LCD_SYSTEM IRQ_LCD2
114
115#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
deleted file mode 100644
index 2550b6112b82..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2009 Samsung Electronics Co.
7 * Byungho Min <bhmin@samsung.com>
8 *
9 * S5PC100 - Memory map definitions
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARCH_MAP_H
17#define __ASM_ARCH_MAP_H __FILE__
18
19#include <plat/map-base.h>
20#include <plat/map-s5p.h>
21
22#define S5PC100_PA_SDRAM 0x20000000
23
24#define S5PC100_PA_ONENAND 0xE7100000
25#define S5PC100_PA_ONENAND_BUF 0xB0000000
26
27#define S5PC100_PA_CHIPID 0xE0000000
28
29#define S5PC100_PA_SYSCON 0xE0100000
30
31#define S5PC100_PA_OTHERS 0xE0200000
32
33#define S5PC100_PA_GPIO 0xE0300000
34
35#define S5PC100_PA_VIC0 0xE4000000
36#define S5PC100_PA_VIC1 0xE4100000
37#define S5PC100_PA_VIC2 0xE4200000
38
39#define S5PC100_PA_SROMC 0xE7000000
40
41#define S5PC100_PA_CFCON 0xE7800000
42
43#define S5PC100_PA_MDMA 0xE8100000
44#define S5PC100_PA_PDMA0 0xE9000000
45#define S5PC100_PA_PDMA1 0xE9200000
46
47#define S5PC100_PA_TIMER 0xEA000000
48#define S5PC100_PA_SYSTIMER 0xEA100000
49#define S5PC100_PA_WATCHDOG 0xEA200000
50#define S5PC100_PA_RTC 0xEA300000
51
52#define S5PC100_PA_UART 0xEC000000
53
54#define S5PC100_PA_IIC0 0xEC100000
55#define S5PC100_PA_IIC1 0xEC200000
56
57#define S5PC100_PA_SPI0 0xEC300000
58#define S5PC100_PA_SPI1 0xEC400000
59#define S5PC100_PA_SPI2 0xEC500000
60
61#define S5PC100_PA_USB_HSOTG 0xED200000
62#define S5PC100_PA_USB_HSPHY 0xED300000
63
64#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
65
66#define S5PC100_PA_FB 0xEE000000
67
68#define S5PC100_PA_FIMC0 0xEE200000
69#define S5PC100_PA_FIMC1 0xEE300000
70#define S5PC100_PA_FIMC2 0xEE400000
71
72#define S5PC100_PA_I2S0 0xF2000000
73#define S5PC100_PA_I2S1 0xF2100000
74#define S5PC100_PA_I2S2 0xF2200000
75
76#define S5PC100_PA_AC97 0xF2300000
77
78#define S5PC100_PA_PCM0 0xF2400000
79#define S5PC100_PA_PCM1 0xF2500000
80
81#define S5PC100_PA_SPDIF 0xF2600000
82
83#define S5PC100_PA_TSADC 0xF3000000
84
85#define S5PC100_PA_KEYPAD 0xF3100000
86
87/* Compatibiltiy Defines */
88
89#define S3C_PA_FB S5PC100_PA_FB
90#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
91#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
92#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
93#define S3C_PA_IIC S5PC100_PA_IIC0
94#define S3C_PA_IIC1 S5PC100_PA_IIC1
95#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
96#define S3C_PA_ONENAND S5PC100_PA_ONENAND
97#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
98#define S3C_PA_RTC S5PC100_PA_RTC
99#define S3C_PA_TSADC S5PC100_PA_TSADC
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
103#define S3C_PA_SPI0 S5PC100_PA_SPI0
104#define S3C_PA_SPI1 S5PC100_PA_SPI1
105#define S3C_PA_SPI2 S5PC100_PA_SPI2
106
107#define S5P_PA_CHIPID S5PC100_PA_CHIPID
108#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
109#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
110#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
111#define S5P_PA_SDRAM S5PC100_PA_SDRAM
112#define S5P_PA_SROMC S5PC100_PA_SROMC
113#define S5P_PA_SYSCON S5PC100_PA_SYSCON
114#define S5P_PA_TIMER S5PC100_PA_TIMER
115
116#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
117#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
118#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
119#define SAMSUNG_PA_TIMER S5PC100_PA_TIMER
120
121#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
122
123#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
124
125/* UART */
126
127#define S3C_PA_UART S5PC100_PA_UART
128
129#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
130#define S5P_PA_UART0 S5P_PA_UART(0)
131#define S5P_PA_UART1 S5P_PA_UART(1)
132#define S5P_PA_UART2 S5P_PA_UART(2)
133#define S5P_PA_UART3 S5P_PA_UART(3)
134
135#define S5P_SZ_UART SZ_256
136
137#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
deleted file mode 100644
index bc92da2e0ba2..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PC100 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x))
21
22#define S5P_APLL_LOCK S5P_CLKREG(0x00)
23#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
24#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
25#define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
26
27#define S5P_APLL_CON S5P_CLKREG(0x100)
28#define S5P_MPLL_CON S5P_CLKREG(0x104)
29#define S5P_EPLL_CON S5P_CLKREG(0x108)
30#define S5P_HPLL_CON S5P_CLKREG(0x10C)
31
32#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
33#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
34#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
35#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
36
37#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
38#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
39#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
40#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
41#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
42
43#define S5P_CLK_OUT S5P_CLKREG(0x400)
44
45#define S5P_CLKGATE_D00 S5P_CLKREG(0x500)
46#define S5P_CLKGATE_D01 S5P_CLKREG(0x504)
47#define S5P_CLKGATE_D02 S5P_CLKREG(0x508)
48
49#define S5P_CLKGATE_D10 S5P_CLKREG(0x520)
50#define S5P_CLKGATE_D11 S5P_CLKREG(0x524)
51#define S5P_CLKGATE_D12 S5P_CLKREG(0x528)
52#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C)
53#define S5P_CLKGATE_D14 S5P_CLKREG(0x530)
54#define S5P_CLKGATE_D15 S5P_CLKREG(0x534)
55
56#define S5P_CLKGATE_D20 S5P_CLKREG(0x540)
57
58#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560)
59#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564)
60
61/* CLKDIV0 */
62#define S5P_CLKDIV0_D0_MASK (0x7<<8)
63#define S5P_CLKDIV0_D0_SHIFT (8)
64#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12)
65#define S5P_CLKDIV0_PCLKD0_SHIFT (12)
66
67/* CLKDIV1 */
68#define S5P_CLKDIV1_D1_MASK (0x7<<12)
69#define S5P_CLKDIV1_D1_SHIFT (12)
70#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
71#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
72
73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
74#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200)
75
76#define S5PC100_SWRESET_RESETVAL 0xc100
77
78#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
79
80#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
deleted file mode 100644
index 0bf73209ec7b..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - GPIO register definitions
7 */
8
9#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
10#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
11
12#include <mach/map.h>
13
14#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
15#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
16
17#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
18#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
19
20#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
21#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
22
23#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
24#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
25
26#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
27
28#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
29
30#define EINT_MODE S3C_GPIO_SFN(0x2)
31
32#define EINT_GPIO_0(x) S5PC100_GPH0(x)
33#define EINT_GPIO_1(x) S5PC100_GPH1(x)
34#define EINT_GPIO_2(x) S5PC100_GPH2(x)
35#define EINT_GPIO_3(x) S5PC100_GPH3(x)
36
37#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
38
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
deleted file mode 100644
index 761627897f30..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
deleted file mode 100644
index 668af3ac31f3..000000000000
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ /dev/null
@@ -1,264 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Author: Byungho Min <bhmin@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/serial_s3c.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/fb.h>
25#include <linux/delay.h>
26#include <linux/input.h>
27#include <linux/pwm_backlight.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31
32#include <mach/map.h>
33#include <mach/regs-gpio.h>
34
35#include <video/platform_lcd.h>
36#include <video/samsung_fimd.h>
37
38#include <asm/irq.h>
39#include <asm/mach-types.h>
40
41#include <plat/gpio-cfg.h>
42
43#include <plat/clock.h>
44#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/fb.h>
47#include <linux/platform_data/i2c-s3c2410.h>
48#include <linux/platform_data/ata-samsung_cf.h>
49#include <plat/adc.h>
50#include <plat/keypad.h>
51#include <linux/platform_data/touchscreen-s3c2410.h>
52#include <linux/platform_data/asoc-s3c.h>
53#include <plat/backlight.h>
54#include <plat/samsung-time.h>
55
56#include "common.h"
57
58/* Following are default values for UCON, ULCON and UFCON UART registers */
59#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8
67
68#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S3C2440_UFCON_RXTRIG8 | \
70 S3C2440_UFCON_TXTRIG16)
71
72static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = SMDKC100_UCON_DEFAULT,
77 .ulcon = SMDKC100_ULCON_DEFAULT,
78 .ufcon = SMDKC100_UFCON_DEFAULT,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = SMDKC100_UCON_DEFAULT,
84 .ulcon = SMDKC100_ULCON_DEFAULT,
85 .ufcon = SMDKC100_UFCON_DEFAULT,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = SMDKC100_UCON_DEFAULT,
91 .ulcon = SMDKC100_ULCON_DEFAULT,
92 .ufcon = SMDKC100_UFCON_DEFAULT,
93 },
94 [3] = {
95 .hwport = 3,
96 .flags = 0,
97 .ucon = SMDKC100_UCON_DEFAULT,
98 .ulcon = SMDKC100_ULCON_DEFAULT,
99 .ufcon = SMDKC100_UFCON_DEFAULT,
100 },
101};
102
103/* I2C0 */
104static struct i2c_board_info i2c_devs0[] __initdata = {
105 {I2C_BOARD_INFO("wm8580", 0x1b),},
106};
107
108/* I2C1 */
109static struct i2c_board_info i2c_devs1[] __initdata = {
110};
111
112/* LCD power controller */
113static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
114 unsigned int power)
115{
116 if (power) {
117 /* module reset */
118 gpio_direction_output(S5PC100_GPH0(6), 1);
119 mdelay(100);
120 gpio_direction_output(S5PC100_GPH0(6), 0);
121 mdelay(10);
122 gpio_direction_output(S5PC100_GPH0(6), 1);
123 mdelay(10);
124 }
125}
126
127static struct plat_lcd_data smdkc100_lcd_power_data = {
128 .set_power = smdkc100_lcd_power_set,
129};
130
131static struct platform_device smdkc100_lcd_powerdev = {
132 .name = "platform-lcd",
133 .dev.parent = &s3c_device_fb.dev,
134 .dev.platform_data = &smdkc100_lcd_power_data,
135};
136
137/* Frame Buffer */
138static struct s3c_fb_pd_win smdkc100_fb_win0 = {
139 .max_bpp = 32,
140 .default_bpp = 16,
141 .xres = 800,
142 .yres = 480,
143};
144
145static struct fb_videomode smdkc100_lcd_timing = {
146 .left_margin = 8,
147 .right_margin = 13,
148 .upper_margin = 7,
149 .lower_margin = 5,
150 .hsync_len = 3,
151 .vsync_len = 1,
152 .xres = 800,
153 .yres = 480,
154 .refresh = 80,
155};
156
157static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
158 .win[0] = &smdkc100_fb_win0,
159 .vtiming = &smdkc100_lcd_timing,
160 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
161 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
162 .setup_gpio = s5pc100_fb_gpio_setup_24bpp,
163};
164
165static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = {
166 .setup_gpio = s5pc100_ide_setup_gpio,
167};
168
169static uint32_t smdkc100_keymap[] __initdata = {
170 /* KEY(row, col, keycode) */
171 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
172 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
173 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
174 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
175};
176
177static struct matrix_keymap_data smdkc100_keymap_data __initdata = {
178 .keymap = smdkc100_keymap,
179 .keymap_size = ARRAY_SIZE(smdkc100_keymap),
180};
181
182static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
183 .keymap_data = &smdkc100_keymap_data,
184 .rows = 2,
185 .cols = 8,
186};
187
188static struct platform_device *smdkc100_devices[] __initdata = {
189 &s3c_device_adc,
190 &s3c_device_cfcon,
191 &s3c_device_i2c0,
192 &s3c_device_i2c1,
193 &s3c_device_fb,
194 &s3c_device_hsmmc0,
195 &s3c_device_hsmmc1,
196 &s3c_device_hsmmc2,
197 &samsung_device_pwm,
198 &s3c_device_ts,
199 &s3c_device_wdt,
200 &smdkc100_lcd_powerdev,
201 &s5pc100_device_iis0,
202 &samsung_device_keypad,
203 &s5pc100_device_ac97,
204 &s3c_device_rtc,
205 &s5p_device_fimc0,
206 &s5p_device_fimc1,
207 &s5p_device_fimc2,
208 &s5pc100_device_spdif,
209};
210
211/* LCD Backlight data */
212static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
213 .no = S5PC100_GPD(0),
214 .func = S3C_GPIO_SFN(2),
215};
216
217static struct platform_pwm_backlight_data smdkc100_bl_data = {
218 .pwm_id = 0,
219 .enable_gpio = -1,
220};
221
222static void __init smdkc100_map_io(void)
223{
224 s5pc100_init_io(NULL, 0);
225 s3c24xx_init_clocks(12000000);
226 s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
227 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
228}
229
230static void __init smdkc100_machine_init(void)
231{
232 s3c24xx_ts_set_platdata(NULL);
233
234 /* I2C */
235 s3c_i2c0_set_platdata(NULL);
236 s3c_i2c1_set_platdata(NULL);
237 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
238 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
239
240 s3c_fb_set_platdata(&smdkc100_lcd_pdata);
241 s3c_ide_set_platdata(&smdkc100_ide_pdata);
242
243 samsung_keypad_set_platdata(&smdkc100_keypad_data);
244
245 s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
246
247 /* LCD init */
248 gpio_request(S5PC100_GPH0(6), "GPH0");
249 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
250
251 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
252
253 samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
254}
255
256MACHINE_START(SMDKC100, "SMDKC100")
257 /* Maintainer: Byungho Min <bhmin@samsung.com> */
258 .atag_offset = 0x100,
259 .init_irq = s5pc100_init_irq,
260 .map_io = smdkc100_map_io,
261 .init_machine = smdkc100_machine_init,
262 .init_time = samsung_timer_init,
263 .restart = s5pc100_restart,
264MACHINE_END
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
deleted file mode 100644
index 8978e4cf9ed5..000000000000
--- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
3 *
4 * Copyright 2009 Samsung Electronics
5 *
6 * Base S5PC100 setup information for 24bpp LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/fb.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <plat/fb.h>
20#include <plat/gpio-cfg.h>
21
22#define DISR_OFFSET 0x7008
23
24static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
25{
26 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
27}
28
29void s5pc100_fb_gpio_setup_24bpp(void)
30{
31 s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
32 s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
33 s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
34 s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
35}
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
deleted file mode 100644
index 89a6a769d622..000000000000
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Base S5PC100 I2C bus 0 gpio configuration
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <linux/gpio.h>
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
deleted file mode 100644
index faa667ef02cb..000000000000
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Base S5PC100 I2C bus 1 gpio configuration
7 *
8 * Based on plat-s3c64xx/setup-i2c1.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <linux/gpio.h>
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
deleted file mode 100644
index 223aae044466..000000000000
--- a/arch/arm/mach-s5pc100/setup-ide.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PC100 setup information for IDE
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16
17#include <mach/regs-clock.h>
18#include <plat/gpio-cfg.h>
19
20static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
21{
22 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
23
24 for (; nr > 0; nr--, base++)
25 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
26}
27
28void s5pc100_ide_setup_gpio(void)
29{
30 u32 reg;
31
32 /* Independent CF interface, CF chip select configuration */
33 reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
34 writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
35
36 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
37 s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
38
39 /*CF_Data[0 - 7] */
40 s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
41
42 /* CF_Data[8 - 15] */
43 s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
44
45 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
46 s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
47
48 /* EBI_OE, EBI_WE */
49 s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
50
51 /* CF_OE, CF_WE */
52 s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
53
54 /* CF_CD */
55 s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
56 s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE);
57}
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
deleted file mode 100644
index ada377f0c206..000000000000
--- a/arch/arm/mach-s5pc100/setup-keypad.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-keypad.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * GPIO configuration for S5PC100 KeyPad device
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/gpio.h>
14#include <plat/gpio-cfg.h>
15
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{
18 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
19 s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
20
21 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
22 s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
23}
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
deleted file mode 100644
index 6010c0310cb5..000000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
2 *
3 * Copyright 2009 Samsung Eletronics
4 *
5 * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/card.h>
20
21#include <plat/gpio-cfg.h>
22#include <plat/sdhci.h>
23
24void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27 unsigned int num;
28
29 num = width;
30 /* In case of 8 width, we should decrease the 2 */
31 if (width == 8)
32 num = width - 2;
33
34 /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
35 s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
36
37 if (width == 8)
38 s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
39
40 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
41 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
42 s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
43 }
44}
45
46void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
47{
48 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
49
50 /* Set all the necessary GPG2 pins to special-function 2 */
51 s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
52
53 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
54 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
55 s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
56 }
57}
58
59void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
60{
61 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
62
63 /* Set all the necessary GPG3 pins to special-function 2 */
64 s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
65
66 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
67 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
68 s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
69 }
70}
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
deleted file mode 100644
index 183567961de1..000000000000
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
18 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
19 return 0;
20}
21#endif
22
23#ifdef CONFIG_S3C64XX_DEV_SPI1
24int s3c64xx_spi1_cfg_gpio(void)
25{
26 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 return 0;
29}
30#endif
31
32#ifdef CONFIG_S3C64XX_DEV_SPI2
33int s3c64xx_spi2_cfg_gpio(void)
34{
35 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
36 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
37 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
38 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
39 return 0;
40}
41#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index d2d375b3db2d..1c629c2c270f 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -15,7 +15,7 @@ config PLAT_SAMSUNG
15 15
16config PLAT_S5P 16config PLAT_S5P
17 bool 17 bool
18 depends on (ARCH_S5PC100 || ARCH_S5PV210) 18 depends on ARCH_S5PV210
19 default y 19 default y
20 select ARCH_REQUIRE_GPIOLIB 20 select ARCH_REQUIRE_GPIOLIB
21 select ARM_VIC 21 select ARM_VIC
@@ -78,14 +78,14 @@ config SAMSUNG_CLKSRC
78 used by newer systems such as the S3C64XX. 78 used by newer systems such as the S3C64XX.
79 79
80config S5P_CLOCK 80config S5P_CLOCK
81 def_bool (ARCH_S5PC100 || ARCH_S5PV210) 81 def_bool ARCH_S5PV210
82 help 82 help
83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs 83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
84 84
85# options for IRQ support 85# options for IRQ support
86 86
87config S5P_IRQ 87config S5P_IRQ
88 def_bool (ARCH_S5PC100 || ARCH_S5PV210) 88 def_bool ARCH_S5PV210
89 help 89 help
90 Support common interrupt part for ARCH_S5P SoCs 90 Support common interrupt part for ARCH_S5P SoCs
91 91
@@ -142,7 +142,7 @@ config S3C_GPIO_TRACK
142 142
143config S5P_DEV_UART 143config S5P_DEV_UART
144 def_bool y 144 def_bool y
145 depends on (ARCH_S5PC100 || ARCH_S5PV210) 145 depends on ARCH_S5PV210
146 146
147# ADC driver 147# ADC driver
148 148
@@ -396,7 +396,7 @@ config SAMSUNG_PM_GPIO
396 396
397config SAMSUNG_DMADEV 397config SAMSUNG_DMADEV
398 bool "Use legacy Samsung DMA abstraction" 398 bool "Use legacy Samsung DMA abstraction"
399 depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S3C64XX 399 depends on CPU_S5PV210 || ARCH_S3C64XX
400 select DMADEVICES 400 select DMADEVICES
401 default y 401 default y
402 help 402 help
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 8033561f6200..468352633101 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -43,7 +43,7 @@ enum s3c_cpu_type {
43 TYPE_ADCV1, /* S3C24XX */ 43 TYPE_ADCV1, /* S3C24XX */
44 TYPE_ADCV11, /* S3C2443 */ 44 TYPE_ADCV11, /* S3C2443 */
45 TYPE_ADCV12, /* S3C2416, S3C2450 */ 45 TYPE_ADCV12, /* S3C2416, S3C2450 */
46 TYPE_ADCV2, /* S3C64XX, S5PC100 */ 46 TYPE_ADCV2, /* S3C64XX */
47 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ 47 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
48}; 48};
49 49
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 18e4365b0d26..d1d4659025bb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -33,9 +33,6 @@ extern unsigned long samsung_cpu_id;
33#define S3C6410_CPU_ID 0x36410000 33#define S3C6410_CPU_ID 0x36410000
34#define S3C64XX_CPU_MASK 0xFFFFF000 34#define S3C64XX_CPU_MASK 0xFFFFF000
35 35
36#define S5PC100_CPU_ID 0x43100000
37#define S5PC100_CPU_MASK 0xFFFFF000
38
39#define S5PV210_CPU_ID 0x43110000 36#define S5PV210_CPU_ID 0x43110000
40#define S5PV210_CPU_MASK 0xFFFFF000 37#define S5PV210_CPU_MASK 0xFFFFF000
41 38
@@ -50,7 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
50IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) 47IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
51IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) 48IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
52IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) 49IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
53IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
54IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) 50IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
55 51
56#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 52#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -80,12 +76,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
80# define soc_is_s3c64xx() 0 76# define soc_is_s3c64xx() 0
81#endif 77#endif
82 78
83#if defined(CONFIG_CPU_S5PC100)
84# define soc_is_s5pc100() is_samsung_s5pc100()
85#else
86# define soc_is_s5pc100() 0
87#endif
88
89#if defined(CONFIG_CPU_S5PV210) 79#if defined(CONFIG_CPU_S5PV210)
90# define soc_is_s5pv210() is_samsung_s5pv210() 80# define soc_is_s5pv210() is_samsung_s5pv210()
91#else 81#else
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ca66f5137f4b..5f5a28d08c2e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -94,14 +94,6 @@ extern struct platform_device s5p_device_mixer;
94extern struct platform_device s5p_device_onenand; 94extern struct platform_device s5p_device_onenand;
95extern struct platform_device s5p_device_sdo; 95extern struct platform_device s5p_device_sdo;
96 96
97extern struct platform_device s5pc100_device_ac97;
98extern struct platform_device s5pc100_device_iis0;
99extern struct platform_device s5pc100_device_iis1;
100extern struct platform_device s5pc100_device_iis2;
101extern struct platform_device s5pc100_device_pcm0;
102extern struct platform_device s5pc100_device_pcm1;
103extern struct platform_device s5pc100_device_spdif;
104
105extern struct platform_device s5pv210_device_ac97; 97extern struct platform_device s5pv210_device_ac97;
106extern struct platform_device s5pv210_device_iis0; 98extern struct platform_device s5pv210_device_iis0;
107extern struct platform_device s5pv210_device_iis1; 99extern struct platform_device s5pv210_device_iis1;
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index a400464c7a6d..5a0e26afb961 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -41,13 +41,6 @@ extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
41extern void s3c64xx_fb_gpio_setup_24bpp(void); 41extern void s3c64xx_fb_gpio_setup_24bpp(void);
42 42
43/** 43/**
44 * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
45 *
46 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
47 */
48extern void s5pc100_fb_gpio_setup_24bpp(void);
49
50/**
51 * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD 44 * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
52 * 45 *
53 * Initialise the GPIO for an 24bpp LCD display on the RGB interface. 46 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 8364b4bea8b8..acacc4b88a39 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -57,7 +57,7 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
57extern int s5p_epll_enable(struct clk *clk, int enable); 57extern int s5p_epll_enable(struct clk *clk, int enable);
58extern unsigned long s5p_epll_get_rate(struct clk *clk); 58extern unsigned long s5p_epll_get_rate(struct clk *clk);
59 59
60/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */ 60/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); 61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
62extern unsigned long s5p_spdif_get_rate(struct clk *clk); 62extern unsigned long s5p_spdif_get_rate(struct clk *clk);
63 63
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 7b2332fc7ac6..f84b6cbc8745 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -56,9 +56,6 @@ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
56extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 56extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
59extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
60extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
61extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
62extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 59extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
63extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 60extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
64extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 61extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
@@ -147,37 +144,6 @@ static inline void s3c6400_default_sdhci2(void) { }
147 144
148#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 145#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
149 146
150/* S5PC100 SDHCI setup */
151
152#ifdef CONFIG_S5PC100_SETUP_SDHCI
153static inline void s5pc100_default_sdhci0(void)
154{
155#ifdef CONFIG_S3C_DEV_HSMMC
156 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
157#endif
158}
159
160static inline void s5pc100_default_sdhci1(void)
161{
162#ifdef CONFIG_S3C_DEV_HSMMC1
163 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
164#endif
165}
166
167static inline void s5pc100_default_sdhci2(void)
168{
169#ifdef CONFIG_S3C_DEV_HSMMC2
170 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
171#endif
172}
173
174#else
175static inline void s5pc100_default_sdhci0(void) { }
176static inline void s5pc100_default_sdhci1(void) { }
177static inline void s5pc100_default_sdhci2(void) { }
178
179#endif /* CONFIG_S5PC100_SETUP_SDHCI */
180
181/* S5PV210 SDHCI setup */ 147/* S5PV210 SDHCI setup */
182 148
183#ifdef CONFIG_S5PV210_SETUP_SDHCI 149#ifdef CONFIG_S5PV210_SETUP_SDHCI
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bbb746e35500..e7028681aa70 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -23,7 +23,6 @@ config ARM_VIC
23config ARM_VIC_NR 23config ARM_VIC_NR
24 int 24 int
25 default 4 if ARCH_S5PV210 25 default 4 if ARCH_S5PV210
26 default 3 if ARCH_S5PC100
27 default 2 26 default 2
28 depends on ARM_VIC 27 depends on ARM_VIC
29 help 28 help
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 02:05:17 -0500