diff options
277 files changed, 12020 insertions, 1567 deletions
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index 9d58c7c5eddd..eb0fae18ffb1 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt | |||
@@ -59,7 +59,11 @@ PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region. | |||
59 | This maps the platforms RAM, and typically | 59 | This maps the platforms RAM, and typically |
60 | maps all platform RAM in a 1:1 relationship. | 60 | maps all platform RAM in a 1:1 relationship. |
61 | 61 | ||
62 | TASK_SIZE PAGE_OFFSET-1 Kernel module space | 62 | PKMAP_BASE PAGE_OFFSET-1 Permanent kernel mappings |
63 | One way of mapping HIGHMEM pages into kernel | ||
64 | space. | ||
65 | |||
66 | MODULES_VADDR MODULES_END-1 Kernel module space | ||
63 | Kernel modules inserted via insmod are | 67 | Kernel modules inserted via insmod are |
64 | placed here using dynamic mappings. | 68 | placed here using dynamic mappings. |
65 | 69 | ||
diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt index da42ab414c48..74a8b6fefa29 100644 --- a/Documentation/cachetlb.txt +++ b/Documentation/cachetlb.txt | |||
@@ -88,12 +88,12 @@ changes occur: | |||
88 | This is used primarily during fault processing. | 88 | This is used primarily during fault processing. |
89 | 89 | ||
90 | 5) void update_mmu_cache(struct vm_area_struct *vma, | 90 | 5) void update_mmu_cache(struct vm_area_struct *vma, |
91 | unsigned long address, pte_t pte) | 91 | unsigned long address, pte_t *ptep) |
92 | 92 | ||
93 | At the end of every page fault, this routine is invoked to | 93 | At the end of every page fault, this routine is invoked to |
94 | tell the architecture specific code that a translation | 94 | tell the architecture specific code that a translation |
95 | described by "pte" now exists at virtual address "address" | 95 | now exists at virtual address "address" for address space |
96 | for address space "vma->vm_mm", in the software page tables. | 96 | "vma->vm_mm", in the software page tables. |
97 | 97 | ||
98 | A port may use this information in any way it so chooses. | 98 | A port may use this information in any way it so chooses. |
99 | For example, it could use this event to pre-load TLB | 99 | For example, it could use this event to pre-load TLB |
diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h index 3f0c59f6d8aa..71a243294142 100644 --- a/arch/alpha/include/asm/pgtable.h +++ b/arch/alpha/include/asm/pgtable.h | |||
@@ -329,7 +329,7 @@ extern pgd_t swapper_pg_dir[1024]; | |||
329 | * tables contain all the necessary information. | 329 | * tables contain all the necessary information. |
330 | */ | 330 | */ |
331 | extern inline void update_mmu_cache(struct vm_area_struct * vma, | 331 | extern inline void update_mmu_cache(struct vm_area_struct * vma, |
332 | unsigned long address, pte_t pte) | 332 | unsigned long address, pte_t *ptep) |
333 | { | 333 | { |
334 | } | 334 | } |
335 | 335 | ||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fb2a51b0ec15..e4a765438ee3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -12,6 +12,7 @@ config ARM | |||
12 | select HAVE_IDE | 12 | select HAVE_IDE |
13 | select RTC_LIB | 13 | select RTC_LIB |
14 | select SYS_SUPPORTS_APM_EMULATION | 14 | select SYS_SUPPORTS_APM_EMULATION |
15 | select GENERIC_ATOMIC64 if (!CPU_32v6K) | ||
15 | select HAVE_OPROFILE | 16 | select HAVE_OPROFILE |
16 | select HAVE_ARCH_KGDB | 17 | select HAVE_ARCH_KGDB |
17 | select HAVE_KPROBES if (!XIP_KERNEL) | 18 | select HAVE_KPROBES if (!XIP_KERNEL) |
@@ -20,6 +21,8 @@ config ARM | |||
20 | select HAVE_GENERIC_DMA_COHERENT | 21 | select HAVE_GENERIC_DMA_COHERENT |
21 | select HAVE_KERNEL_GZIP | 22 | select HAVE_KERNEL_GZIP |
22 | select HAVE_KERNEL_LZO | 23 | select HAVE_KERNEL_LZO |
24 | select HAVE_PERF_EVENTS | ||
25 | select PERF_USE_VMALLOC | ||
23 | help | 26 | help |
24 | The ARM series is a line of low-power-consumption RISC chip designs | 27 | The ARM series is a line of low-power-consumption RISC chip designs |
25 | licensed by ARM Ltd and targeted at embedded applications and | 28 | licensed by ARM Ltd and targeted at embedded applications and |
@@ -52,6 +55,9 @@ config HAVE_TCM | |||
52 | bool | 55 | bool |
53 | select GENERIC_ALLOCATOR | 56 | select GENERIC_ALLOCATOR |
54 | 57 | ||
58 | config HAVE_PROC_CPU | ||
59 | bool | ||
60 | |||
55 | config NO_IOPORT | 61 | config NO_IOPORT |
56 | bool | 62 | bool |
57 | 63 | ||
@@ -161,6 +167,11 @@ config ARCH_MTD_XIP | |||
161 | config GENERIC_HARDIRQS_NO__DO_IRQ | 167 | config GENERIC_HARDIRQS_NO__DO_IRQ |
162 | def_bool y | 168 | def_bool y |
163 | 169 | ||
170 | config ARM_L1_CACHE_SHIFT_6 | ||
171 | bool | ||
172 | help | ||
173 | Setting ARM L1 cache line size to 64 Bytes. | ||
174 | |||
164 | if OPROFILE | 175 | if OPROFILE |
165 | 176 | ||
166 | config OPROFILE_ARMV6 | 177 | config OPROFILE_ARMV6 |
@@ -550,6 +561,15 @@ config ARCH_W90X900 | |||
550 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | 561 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ |
551 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | 562 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> |
552 | 563 | ||
564 | config ARCH_NUC93X | ||
565 | bool "Nuvoton NUC93X CPU" | ||
566 | select CPU_ARM926T | ||
567 | select HAVE_CLK | ||
568 | select COMMON_CLKDEV | ||
569 | help | ||
570 | Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a | ||
571 | low-power and high performance MPEG-4/JPEG multimedia controller chip. | ||
572 | |||
553 | config ARCH_PNX4008 | 573 | config ARCH_PNX4008 |
554 | bool "Philips Nexperia PNX4008 Mobile" | 574 | bool "Philips Nexperia PNX4008 Mobile" |
555 | select CPU_ARM926T | 575 | select CPU_ARM926T |
@@ -639,6 +659,7 @@ config ARCH_S5PC1XX | |||
639 | select GENERIC_GPIO | 659 | select GENERIC_GPIO |
640 | select HAVE_CLK | 660 | select HAVE_CLK |
641 | select CPU_V7 | 661 | select CPU_V7 |
662 | select ARM_L1_CACHE_SHIFT_6 | ||
642 | help | 663 | help |
643 | Samsung S5PC1XX series based systems | 664 | Samsung S5PC1XX series based systems |
644 | 665 | ||
@@ -785,6 +806,8 @@ source "arch/arm/plat-nomadik/Kconfig" | |||
785 | 806 | ||
786 | source "arch/arm/mach-ns9xxx/Kconfig" | 807 | source "arch/arm/mach-ns9xxx/Kconfig" |
787 | 808 | ||
809 | source "arch/arm/mach-nuc93x/Kconfig" | ||
810 | |||
788 | source "arch/arm/plat-omap/Kconfig" | 811 | source "arch/arm/plat-omap/Kconfig" |
789 | 812 | ||
790 | source "arch/arm/mach-omap1/Kconfig" | 813 | source "arch/arm/mach-omap1/Kconfig" |
@@ -867,6 +890,11 @@ config XSCALE_PMU | |||
867 | depends on CPU_XSCALE && !XSCALE_PMU_TIMER | 890 | depends on CPU_XSCALE && !XSCALE_PMU_TIMER |
868 | default y | 891 | default y |
869 | 892 | ||
893 | config CPU_HAS_PMU | ||
894 | depends on CPU_V6 || CPU_V7 || XSCALE_PMU | ||
895 | default y | ||
896 | bool | ||
897 | |||
870 | if !MMU | 898 | if !MMU |
871 | source "arch/arm/Kconfig-nommu" | 899 | source "arch/arm/Kconfig-nommu" |
872 | endif | 900 | endif |
@@ -921,6 +949,19 @@ config ARM_ERRATA_460075 | |||
921 | ACTLR register. Note that setting specific bits in the ACTLR register | 949 | ACTLR register. Note that setting specific bits in the ACTLR register |
922 | may not be available in non-secure mode. | 950 | may not be available in non-secure mode. |
923 | 951 | ||
952 | config PL310_ERRATA_588369 | ||
953 | bool "Clean & Invalidate maintenance operations do not invalidate clean lines" | ||
954 | depends on CACHE_L2X0 && ARCH_OMAP4 | ||
955 | help | ||
956 | The PL310 L2 cache controller implements three types of Clean & | ||
957 | Invalidate maintenance operations: by Physical Address | ||
958 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | ||
959 | They are architecturally defined to behave as the execution of a | ||
960 | clean operation followed immediately by an invalidate operation, | ||
961 | both performing to the same memory location. This functionality | ||
962 | is not correctly implemented in PL310 as clean lines are not | ||
963 | invalidated as a result of these operations. Note that this errata | ||
964 | uses Texas Instrument's secure monitor api. | ||
924 | endmenu | 965 | endmenu |
925 | 966 | ||
926 | source "arch/arm/common/Kconfig" | 967 | source "arch/arm/common/Kconfig" |
@@ -1171,6 +1212,14 @@ config HIGHPTE | |||
1171 | depends on HIGHMEM | 1212 | depends on HIGHMEM |
1172 | depends on !OUTER_CACHE | 1213 | depends on !OUTER_CACHE |
1173 | 1214 | ||
1215 | config HW_PERF_EVENTS | ||
1216 | bool "Enable hardware performance counter support for perf events" | ||
1217 | depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7) | ||
1218 | default y | ||
1219 | help | ||
1220 | Enable hardware performance counter support for perf events. If | ||
1221 | disabled, perf events will use software events only. | ||
1222 | |||
1174 | source "mm/Kconfig" | 1223 | source "mm/Kconfig" |
1175 | 1224 | ||
1176 | config LEDS | 1225 | config LEDS |
@@ -1230,6 +1279,7 @@ config ALIGNMENT_TRAP | |||
1230 | bool | 1279 | bool |
1231 | depends on CPU_CP15_MMU | 1280 | depends on CPU_CP15_MMU |
1232 | default y if !ARCH_EBSA110 | 1281 | default y if !ARCH_EBSA110 |
1282 | select HAVE_PROC_CPU if PROC_FS | ||
1233 | help | 1283 | help |
1234 | ARM processors cannot fetch/store information which is not | 1284 | ARM processors cannot fetch/store information which is not |
1235 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an | 1285 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 9e7582572741..52a820d42776 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -171,6 +171,7 @@ machine-$(CONFIG_ARCH_U300) := u300 | |||
171 | machine-$(CONFIG_ARCH_U8500) := ux500 | 171 | machine-$(CONFIG_ARCH_U8500) := ux500 |
172 | machine-$(CONFIG_ARCH_VERSATILE) := versatile | 172 | machine-$(CONFIG_ARCH_VERSATILE) := versatile |
173 | machine-$(CONFIG_ARCH_W90X900) := w90x900 | 173 | machine-$(CONFIG_ARCH_W90X900) := w90x900 |
174 | machine-$(CONFIG_ARCH_NUC93X) := nuc93x | ||
174 | machine-$(CONFIG_FOOTBRIDGE) := footbridge | 175 | machine-$(CONFIG_FOOTBRIDGE) := footbridge |
175 | 176 | ||
176 | # Platform directory name. This list is sorted alphanumerically | 177 | # Platform directory name. This list is sorted alphanumerically |
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 2d4d88ba73bf..97c89e7de7d3 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile | |||
@@ -5,7 +5,7 @@ | |||
5 | # | 5 | # |
6 | 6 | ||
7 | HEAD = head.o | 7 | HEAD = head.o |
8 | OBJS = misc.o | 8 | OBJS = misc.o decompress.o |
9 | FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c | 9 | FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c |
10 | 10 | ||
11 | # | 11 | # |
@@ -106,10 +106,6 @@ lib1funcs = $(obj)/lib1funcs.o | |||
106 | $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE | 106 | $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE |
107 | $(call cmd,shipped) | 107 | $(call cmd,shipped) |
108 | 108 | ||
109 | # Don't allow any static data in misc.o, which | ||
110 | # would otherwise mess up our GOT table | ||
111 | CFLAGS_misc.o := -Dstatic= | ||
112 | |||
113 | $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ | 109 | $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ |
114 | $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE | 110 | $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE |
115 | $(call if_changed,ld) | 111 | $(call if_changed,ld) |
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c new file mode 100644 index 000000000000..0da382f33157 --- /dev/null +++ b/arch/arm/boot/compressed/decompress.c | |||
@@ -0,0 +1,45 @@ | |||
1 | #define _LINUX_STRING_H_ | ||
2 | |||
3 | #include <linux/compiler.h> /* for inline */ | ||
4 | #include <linux/types.h> /* for size_t */ | ||
5 | #include <linux/stddef.h> /* for NULL */ | ||
6 | #include <linux/linkage.h> | ||
7 | #include <asm/string.h> | ||
8 | |||
9 | extern unsigned long free_mem_ptr; | ||
10 | extern unsigned long free_mem_end_ptr; | ||
11 | extern void error(char *); | ||
12 | |||
13 | #define STATIC static | ||
14 | |||
15 | #define ARCH_HAS_DECOMP_WDOG | ||
16 | |||
17 | /* Diagnostic functions */ | ||
18 | #ifdef DEBUG | ||
19 | # define Assert(cond,msg) {if(!(cond)) error(msg);} | ||
20 | # define Trace(x) fprintf x | ||
21 | # define Tracev(x) {if (verbose) fprintf x ;} | ||
22 | # define Tracevv(x) {if (verbose>1) fprintf x ;} | ||
23 | # define Tracec(c,x) {if (verbose && (c)) fprintf x ;} | ||
24 | # define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} | ||
25 | #else | ||
26 | # define Assert(cond,msg) | ||
27 | # define Trace(x) | ||
28 | # define Tracev(x) | ||
29 | # define Tracevv(x) | ||
30 | # define Tracec(c,x) | ||
31 | # define Tracecv(c,x) | ||
32 | #endif | ||
33 | |||
34 | #ifdef CONFIG_KERNEL_GZIP | ||
35 | #include "../../../../lib/decompress_inflate.c" | ||
36 | #endif | ||
37 | |||
38 | #ifdef CONFIG_KERNEL_LZO | ||
39 | #include "../../../../lib/decompress_unlzo.c" | ||
40 | #endif | ||
41 | |||
42 | void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) | ||
43 | { | ||
44 | decompress(input, len, NULL, NULL, output, NULL, error); | ||
45 | } | ||
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 4fddc509e78e..99b75aa1c2ec 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
@@ -22,13 +22,13 @@ | |||
22 | #if defined(CONFIG_DEBUG_ICEDCC) | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
23 | 23 | ||
24 | #ifdef CONFIG_CPU_V6 | 24 | #ifdef CONFIG_CPU_V6 |
25 | .macro loadsp, rb | 25 | .macro loadsp, rb, tmp |
26 | .endm | 26 | .endm |
27 | .macro writeb, ch, rb | 27 | .macro writeb, ch, rb |
28 | mcr p14, 0, \ch, c0, c5, 0 | 28 | mcr p14, 0, \ch, c0, c5, 0 |
29 | .endm | 29 | .endm |
30 | #elif defined(CONFIG_CPU_V7) | 30 | #elif defined(CONFIG_CPU_V7) |
31 | .macro loadsp, rb | 31 | .macro loadsp, rb, tmp |
32 | .endm | 32 | .endm |
33 | .macro writeb, ch, rb | 33 | .macro writeb, ch, rb |
34 | wait: mrc p14, 0, pc, c0, c1, 0 | 34 | wait: mrc p14, 0, pc, c0, c1, 0 |
@@ -36,13 +36,13 @@ wait: mrc p14, 0, pc, c0, c1, 0 | |||
36 | mcr p14, 0, \ch, c0, c5, 0 | 36 | mcr p14, 0, \ch, c0, c5, 0 |
37 | .endm | 37 | .endm |
38 | #elif defined(CONFIG_CPU_XSCALE) | 38 | #elif defined(CONFIG_CPU_XSCALE) |
39 | .macro loadsp, rb | 39 | .macro loadsp, rb, tmp |
40 | .endm | 40 | .endm |
41 | .macro writeb, ch, rb | 41 | .macro writeb, ch, rb |
42 | mcr p14, 0, \ch, c8, c0, 0 | 42 | mcr p14, 0, \ch, c8, c0, 0 |
43 | .endm | 43 | .endm |
44 | #else | 44 | #else |
45 | .macro loadsp, rb | 45 | .macro loadsp, rb, tmp |
46 | .endm | 46 | .endm |
47 | .macro writeb, ch, rb | 47 | .macro writeb, ch, rb |
48 | mcr p14, 0, \ch, c1, c0, 0 | 48 | mcr p14, 0, \ch, c1, c0, 0 |
@@ -58,7 +58,7 @@ wait: mrc p14, 0, pc, c0, c1, 0 | |||
58 | .endm | 58 | .endm |
59 | 59 | ||
60 | #if defined(CONFIG_ARCH_SA1100) | 60 | #if defined(CONFIG_ARCH_SA1100) |
61 | .macro loadsp, rb | 61 | .macro loadsp, rb, tmp |
62 | mov \rb, #0x80000000 @ physical base address | 62 | mov \rb, #0x80000000 @ physical base address |
63 | #ifdef CONFIG_DEBUG_LL_SER3 | 63 | #ifdef CONFIG_DEBUG_LL_SER3 |
64 | add \rb, \rb, #0x00050000 @ Ser3 | 64 | add \rb, \rb, #0x00050000 @ Ser3 |
@@ -67,13 +67,13 @@ wait: mrc p14, 0, pc, c0, c1, 0 | |||
67 | #endif | 67 | #endif |
68 | .endm | 68 | .endm |
69 | #elif defined(CONFIG_ARCH_S3C2410) | 69 | #elif defined(CONFIG_ARCH_S3C2410) |
70 | .macro loadsp, rb | 70 | .macro loadsp, rb, tmp |
71 | mov \rb, #0x50000000 | 71 | mov \rb, #0x50000000 |
72 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT | 72 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
73 | .endm | 73 | .endm |
74 | #else | 74 | #else |
75 | .macro loadsp, rb | 75 | .macro loadsp, rb, tmp |
76 | addruart \rb | 76 | addruart \rb, \tmp |
77 | .endm | 77 | .endm |
78 | #endif | 78 | #endif |
79 | #endif | 79 | #endif |
@@ -1025,7 +1025,7 @@ phex: adr r3, phexbuf | |||
1025 | strb r2, [r3, r1] | 1025 | strb r2, [r3, r1] |
1026 | b 1b | 1026 | b 1b |
1027 | 1027 | ||
1028 | puts: loadsp r3 | 1028 | puts: loadsp r3, r1 |
1029 | 1: ldrb r2, [r0], #1 | 1029 | 1: ldrb r2, [r0], #1 |
1030 | teq r2, #0 | 1030 | teq r2, #0 |
1031 | moveq pc, lr | 1031 | moveq pc, lr |
@@ -1042,7 +1042,7 @@ puts: loadsp r3 | |||
1042 | putc: | 1042 | putc: |
1043 | mov r2, r0 | 1043 | mov r2, r0 |
1044 | mov r0, #0 | 1044 | mov r0, #0 |
1045 | loadsp r3 | 1045 | loadsp r3, r1 |
1046 | b 2b | 1046 | b 2b |
1047 | 1047 | ||
1048 | memdump: mov r12, r0 | 1048 | memdump: mov r12, r0 |
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 56a0d116d271..d32bc71c1f78 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c | |||
@@ -23,8 +23,8 @@ unsigned int __machine_arch_type; | |||
23 | #include <linux/compiler.h> /* for inline */ | 23 | #include <linux/compiler.h> /* for inline */ |
24 | #include <linux/types.h> /* for size_t */ | 24 | #include <linux/types.h> /* for size_t */ |
25 | #include <linux/stddef.h> /* for NULL */ | 25 | #include <linux/stddef.h> /* for NULL */ |
26 | #include <asm/string.h> | ||
27 | #include <linux/linkage.h> | 26 | #include <linux/linkage.h> |
27 | #include <asm/string.h> | ||
28 | 28 | ||
29 | #include <asm/unaligned.h> | 29 | #include <asm/unaligned.h> |
30 | 30 | ||
@@ -117,57 +117,7 @@ static void putstr(const char *ptr) | |||
117 | 117 | ||
118 | #endif | 118 | #endif |
119 | 119 | ||
120 | #define __ptr_t void * | 120 | void *memcpy(void *__dest, __const void *__src, size_t __n) |
121 | |||
122 | #define memzero(s,n) __memzero(s,n) | ||
123 | |||
124 | /* | ||
125 | * Optimised C version of memzero for the ARM. | ||
126 | */ | ||
127 | void __memzero (__ptr_t s, size_t n) | ||
128 | { | ||
129 | union { void *vp; unsigned long *ulp; unsigned char *ucp; } u; | ||
130 | int i; | ||
131 | |||
132 | u.vp = s; | ||
133 | |||
134 | for (i = n >> 5; i > 0; i--) { | ||
135 | *u.ulp++ = 0; | ||
136 | *u.ulp++ = 0; | ||
137 | *u.ulp++ = 0; | ||
138 | *u.ulp++ = 0; | ||
139 | *u.ulp++ = 0; | ||
140 | *u.ulp++ = 0; | ||
141 | *u.ulp++ = 0; | ||
142 | *u.ulp++ = 0; | ||
143 | } | ||
144 | |||
145 | if (n & 1 << 4) { | ||
146 | *u.ulp++ = 0; | ||
147 | *u.ulp++ = 0; | ||
148 | *u.ulp++ = 0; | ||
149 | *u.ulp++ = 0; | ||
150 | } | ||
151 | |||
152 | if (n & 1 << 3) { | ||
153 | *u.ulp++ = 0; | ||
154 | *u.ulp++ = 0; | ||
155 | } | ||
156 | |||
157 | if (n & 1 << 2) | ||
158 | *u.ulp++ = 0; | ||
159 | |||
160 | if (n & 1 << 1) { | ||
161 | *u.ucp++ = 0; | ||
162 | *u.ucp++ = 0; | ||
163 | } | ||
164 | |||
165 | if (n & 1) | ||
166 | *u.ucp++ = 0; | ||
167 | } | ||
168 | |||
169 | static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src, | ||
170 | size_t __n) | ||
171 | { | 121 | { |
172 | int i = 0; | 122 | int i = 0; |
173 | unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src; | 123 | unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src; |
@@ -204,59 +154,20 @@ static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src, | |||
204 | /* | 154 | /* |
205 | * gzip delarations | 155 | * gzip delarations |
206 | */ | 156 | */ |
207 | #define STATIC static | ||
208 | |||
209 | /* Diagnostic functions */ | ||
210 | #ifdef DEBUG | ||
211 | # define Assert(cond,msg) {if(!(cond)) error(msg);} | ||
212 | # define Trace(x) fprintf x | ||
213 | # define Tracev(x) {if (verbose) fprintf x ;} | ||
214 | # define Tracevv(x) {if (verbose>1) fprintf x ;} | ||
215 | # define Tracec(c,x) {if (verbose && (c)) fprintf x ;} | ||
216 | # define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} | ||
217 | #else | ||
218 | # define Assert(cond,msg) | ||
219 | # define Trace(x) | ||
220 | # define Tracev(x) | ||
221 | # define Tracevv(x) | ||
222 | # define Tracec(c,x) | ||
223 | # define Tracecv(c,x) | ||
224 | #endif | ||
225 | |||
226 | static void error(char *m); | ||
227 | |||
228 | extern char input_data[]; | 157 | extern char input_data[]; |
229 | extern char input_data_end[]; | 158 | extern char input_data_end[]; |
230 | 159 | ||
231 | static unsigned char *output_data; | 160 | unsigned char *output_data; |
232 | static unsigned long output_ptr; | 161 | unsigned long output_ptr; |
233 | |||
234 | static void error(char *m); | ||
235 | 162 | ||
236 | static void putstr(const char *); | 163 | unsigned long free_mem_ptr; |
237 | 164 | unsigned long free_mem_end_ptr; | |
238 | static unsigned long free_mem_ptr; | ||
239 | static unsigned long free_mem_end_ptr; | ||
240 | |||
241 | #ifdef STANDALONE_DEBUG | ||
242 | #define NO_INFLATE_MALLOC | ||
243 | #endif | ||
244 | |||
245 | #define ARCH_HAS_DECOMP_WDOG | ||
246 | |||
247 | #ifdef CONFIG_KERNEL_GZIP | ||
248 | #include "../../../../lib/decompress_inflate.c" | ||
249 | #endif | ||
250 | |||
251 | #ifdef CONFIG_KERNEL_LZO | ||
252 | #include "../../../../lib/decompress_unlzo.c" | ||
253 | #endif | ||
254 | 165 | ||
255 | #ifndef arch_error | 166 | #ifndef arch_error |
256 | #define arch_error(x) | 167 | #define arch_error(x) |
257 | #endif | 168 | #endif |
258 | 169 | ||
259 | static void error(char *x) | 170 | void error(char *x) |
260 | { | 171 | { |
261 | arch_error(x); | 172 | arch_error(x); |
262 | 173 | ||
@@ -272,6 +183,8 @@ asmlinkage void __div0(void) | |||
272 | error("Attempting division by 0!"); | 183 | error("Attempting division by 0!"); |
273 | } | 184 | } |
274 | 185 | ||
186 | extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); | ||
187 | |||
275 | #ifndef STANDALONE_DEBUG | 188 | #ifndef STANDALONE_DEBUG |
276 | 189 | ||
277 | unsigned long | 190 | unsigned long |
@@ -292,8 +205,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, | |||
292 | output_ptr = get_unaligned_le32(tmp); | 205 | output_ptr = get_unaligned_le32(tmp); |
293 | 206 | ||
294 | putstr("Uncompressing Linux..."); | 207 | putstr("Uncompressing Linux..."); |
295 | decompress(input_data, input_data_end - input_data, | 208 | do_decompress(input_data, input_data_end - input_data, |
296 | NULL, NULL, output_data, NULL, error); | 209 | output_data, error); |
297 | putstr(" done, booting the kernel.\n"); | 210 | putstr(" done, booting the kernel.\n"); |
298 | return output_ptr; | 211 | return output_ptr; |
299 | } | 212 | } |
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index a5924b9b88bd..7ca9ecff652f 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in | |||
@@ -14,6 +14,13 @@ SECTIONS | |||
14 | /DISCARD/ : { | 14 | /DISCARD/ : { |
15 | *(.ARM.exidx*) | 15 | *(.ARM.exidx*) |
16 | *(.ARM.extab*) | 16 | *(.ARM.extab*) |
17 | /* | ||
18 | * Discard any r/w data - this produces a link error if we have any, | ||
19 | * which is required for PIC decompression. Local data generates | ||
20 | * GOTOFF relocations, which prevents it being relocated independently | ||
21 | * of the text/got segments. | ||
22 | */ | ||
23 | *(.data) | ||
17 | } | 24 | } |
18 | 25 | ||
19 | . = TEXT_START; | 26 | . = TEXT_START; |
@@ -40,7 +47,6 @@ SECTIONS | |||
40 | .got : { *(.got) } | 47 | .got : { *(.got) } |
41 | _got_end = .; | 48 | _got_end = .; |
42 | .got.plt : { *(.got.plt) } | 49 | .got.plt : { *(.got.plt) } |
43 | .data : { *(.data) } | ||
44 | _edata = .; | 50 | _edata = .; |
45 | 51 | ||
46 | . = BSS_START; | 52 | . = BSS_START; |
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index cc32c1e54a59..cc0a932bbea9 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
@@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size, | |||
277 | * We don't need to sync the DMA buffer since | 277 | * We don't need to sync the DMA buffer since |
278 | * it was allocated via the coherent allocators. | 278 | * it was allocated via the coherent allocators. |
279 | */ | 279 | */ |
280 | dma_cache_maint(ptr, size, dir); | 280 | __dma_single_cpu_to_dev(ptr, size, dir); |
281 | } | 281 | } |
282 | 282 | ||
283 | return dma_addr; | 283 | return dma_addr; |
@@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr, | |||
315 | __cpuc_flush_dcache_area(ptr, size); | 315 | __cpuc_flush_dcache_area(ptr, size); |
316 | } | 316 | } |
317 | free_safe_buffer(dev->archdata.dmabounce, buf); | 317 | free_safe_buffer(dev->archdata.dmabounce, buf); |
318 | } else { | ||
319 | __dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir); | ||
318 | } | 320 | } |
319 | } | 321 | } |
320 | 322 | ||
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index f232941de8ab..1cf999ade4bc 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
@@ -18,6 +18,7 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | |||
21 | #include <linux/init.h> | 22 | #include <linux/init.h> |
22 | #include <linux/list.h> | 23 | #include <linux/list.h> |
23 | #include <linux/io.h> | 24 | #include <linux/io.h> |
@@ -28,48 +29,6 @@ | |||
28 | #include <asm/mach/irq.h> | 29 | #include <asm/mach/irq.h> |
29 | #include <asm/hardware/vic.h> | 30 | #include <asm/hardware/vic.h> |
30 | 31 | ||
31 | static void vic_ack_irq(unsigned int irq) | ||
32 | { | ||
33 | void __iomem *base = get_irq_chip_data(irq); | ||
34 | irq &= 31; | ||
35 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | ||
36 | /* moreover, clear the soft-triggered, in case it was the reason */ | ||
37 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | ||
38 | } | ||
39 | |||
40 | static void vic_mask_irq(unsigned int irq) | ||
41 | { | ||
42 | void __iomem *base = get_irq_chip_data(irq); | ||
43 | irq &= 31; | ||
44 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | ||
45 | } | ||
46 | |||
47 | static void vic_unmask_irq(unsigned int irq) | ||
48 | { | ||
49 | void __iomem *base = get_irq_chip_data(irq); | ||
50 | irq &= 31; | ||
51 | writel(1 << irq, base + VIC_INT_ENABLE); | ||
52 | } | ||
53 | |||
54 | /** | ||
55 | * vic_init2 - common initialisation code | ||
56 | * @base: Base of the VIC. | ||
57 | * | ||
58 | * Common initialisation code for registeration | ||
59 | * and resume. | ||
60 | */ | ||
61 | static void vic_init2(void __iomem *base) | ||
62 | { | ||
63 | int i; | ||
64 | |||
65 | for (i = 0; i < 16; i++) { | ||
66 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | ||
67 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | ||
68 | } | ||
69 | |||
70 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | ||
71 | } | ||
72 | |||
73 | #if defined(CONFIG_PM) | 32 | #if defined(CONFIG_PM) |
74 | /** | 33 | /** |
75 | * struct vic_device - VIC PM device | 34 | * struct vic_device - VIC PM device |
@@ -99,13 +58,34 @@ struct vic_device { | |||
99 | /* we cannot allocate memory when VICs are initially registered */ | 58 | /* we cannot allocate memory when VICs are initially registered */ |
100 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; | 59 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; |
101 | 60 | ||
61 | static int vic_id; | ||
62 | |||
102 | static inline struct vic_device *to_vic(struct sys_device *sys) | 63 | static inline struct vic_device *to_vic(struct sys_device *sys) |
103 | { | 64 | { |
104 | return container_of(sys, struct vic_device, sysdev); | 65 | return container_of(sys, struct vic_device, sysdev); |
105 | } | 66 | } |
67 | #endif /* CONFIG_PM */ | ||
106 | 68 | ||
107 | static int vic_id; | 69 | /** |
70 | * vic_init2 - common initialisation code | ||
71 | * @base: Base of the VIC. | ||
72 | * | ||
73 | * Common initialisation code for registeration | ||
74 | * and resume. | ||
75 | */ | ||
76 | static void vic_init2(void __iomem *base) | ||
77 | { | ||
78 | int i; | ||
79 | |||
80 | for (i = 0; i < 16; i++) { | ||
81 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | ||
82 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | ||
83 | } | ||
84 | |||
85 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | ||
86 | } | ||
108 | 87 | ||
88 | #if defined(CONFIG_PM) | ||
109 | static int vic_class_resume(struct sys_device *dev) | 89 | static int vic_class_resume(struct sys_device *dev) |
110 | { | 90 | { |
111 | struct vic_device *vic = to_vic(dev); | 91 | struct vic_device *vic = to_vic(dev); |
@@ -159,31 +139,6 @@ struct sysdev_class vic_class = { | |||
159 | }; | 139 | }; |
160 | 140 | ||
161 | /** | 141 | /** |
162 | * vic_pm_register - Register a VIC for later power management control | ||
163 | * @base: The base address of the VIC. | ||
164 | * @irq: The base IRQ for the VIC. | ||
165 | * @resume_sources: bitmask of interrupts allowed for resume sources. | ||
166 | * | ||
167 | * Register the VIC with the system device tree so that it can be notified | ||
168 | * of suspend and resume requests and ensure that the correct actions are | ||
169 | * taken to re-instate the settings on resume. | ||
170 | */ | ||
171 | static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) | ||
172 | { | ||
173 | struct vic_device *v; | ||
174 | |||
175 | if (vic_id >= ARRAY_SIZE(vic_devices)) | ||
176 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); | ||
177 | else { | ||
178 | v = &vic_devices[vic_id]; | ||
179 | v->base = base; | ||
180 | v->resume_sources = resume_sources; | ||
181 | v->irq = irq; | ||
182 | vic_id++; | ||
183 | } | ||
184 | } | ||
185 | |||
186 | /** | ||
187 | * vic_pm_init - initicall to register VIC pm | 142 | * vic_pm_init - initicall to register VIC pm |
188 | * | 143 | * |
189 | * This is called via late_initcall() to register | 144 | * This is called via late_initcall() to register |
@@ -219,9 +174,60 @@ static int __init vic_pm_init(void) | |||
219 | 174 | ||
220 | return 0; | 175 | return 0; |
221 | } | 176 | } |
222 | |||
223 | late_initcall(vic_pm_init); | 177 | late_initcall(vic_pm_init); |
224 | 178 | ||
179 | /** | ||
180 | * vic_pm_register - Register a VIC for later power management control | ||
181 | * @base: The base address of the VIC. | ||
182 | * @irq: The base IRQ for the VIC. | ||
183 | * @resume_sources: bitmask of interrupts allowed for resume sources. | ||
184 | * | ||
185 | * Register the VIC with the system device tree so that it can be notified | ||
186 | * of suspend and resume requests and ensure that the correct actions are | ||
187 | * taken to re-instate the settings on resume. | ||
188 | */ | ||
189 | static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) | ||
190 | { | ||
191 | struct vic_device *v; | ||
192 | |||
193 | if (vic_id >= ARRAY_SIZE(vic_devices)) | ||
194 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); | ||
195 | else { | ||
196 | v = &vic_devices[vic_id]; | ||
197 | v->base = base; | ||
198 | v->resume_sources = resume_sources; | ||
199 | v->irq = irq; | ||
200 | vic_id++; | ||
201 | } | ||
202 | } | ||
203 | #else | ||
204 | static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } | ||
205 | #endif /* CONFIG_PM */ | ||
206 | |||
207 | static void vic_ack_irq(unsigned int irq) | ||
208 | { | ||
209 | void __iomem *base = get_irq_chip_data(irq); | ||
210 | irq &= 31; | ||
211 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | ||
212 | /* moreover, clear the soft-triggered, in case it was the reason */ | ||
213 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | ||
214 | } | ||
215 | |||
216 | static void vic_mask_irq(unsigned int irq) | ||
217 | { | ||
218 | void __iomem *base = get_irq_chip_data(irq); | ||
219 | irq &= 31; | ||
220 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | ||
221 | } | ||
222 | |||
223 | static void vic_unmask_irq(unsigned int irq) | ||
224 | { | ||
225 | void __iomem *base = get_irq_chip_data(irq); | ||
226 | irq &= 31; | ||
227 | writel(1 << irq, base + VIC_INT_ENABLE); | ||
228 | } | ||
229 | |||
230 | #if defined(CONFIG_PM) | ||
225 | static struct vic_device *vic_from_irq(unsigned int irq) | 231 | static struct vic_device *vic_from_irq(unsigned int irq) |
226 | { | 232 | { |
227 | struct vic_device *v = vic_devices; | 233 | struct vic_device *v = vic_devices; |
@@ -255,10 +261,7 @@ static int vic_set_wake(unsigned int irq, unsigned int on) | |||
255 | 261 | ||
256 | return 0; | 262 | return 0; |
257 | } | 263 | } |
258 | |||
259 | #else | 264 | #else |
260 | static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } | ||
261 | |||
262 | #define vic_set_wake NULL | 265 | #define vic_set_wake NULL |
263 | #endif /* CONFIG_PM */ | 266 | #endif /* CONFIG_PM */ |
264 | 267 | ||
@@ -270,9 +273,62 @@ static struct irq_chip vic_chip = { | |||
270 | .set_wake = vic_set_wake, | 273 | .set_wake = vic_set_wake, |
271 | }; | 274 | }; |
272 | 275 | ||
273 | /* The PL190 cell from ARM has been modified by ST, so handle both here */ | 276 | /* |
274 | static void vik_init_st(void __iomem *base, unsigned int irq_start, | 277 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. |
275 | u32 vic_sources); | 278 | * The original cell has 32 interrupts, while the modified one has 64, |
279 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | ||
280 | * the probe function is called twice, with base set to offset 000 | ||
281 | * and 020 within the page. We call this "second block". | ||
282 | */ | ||
283 | static void __init vic_init_st(void __iomem *base, unsigned int irq_start, | ||
284 | u32 vic_sources) | ||
285 | { | ||
286 | unsigned int i; | ||
287 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | ||
288 | |||
289 | /* Disable all interrupts initially. */ | ||
290 | |||
291 | writel(0, base + VIC_INT_SELECT); | ||
292 | writel(0, base + VIC_INT_ENABLE); | ||
293 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | ||
294 | writel(0, base + VIC_IRQ_STATUS); | ||
295 | writel(0, base + VIC_ITCR); | ||
296 | writel(~0, base + VIC_INT_SOFT_CLEAR); | ||
297 | |||
298 | /* | ||
299 | * Make sure we clear all existing interrupts. The vector registers | ||
300 | * in this cell are after the second block of general registers, | ||
301 | * so we can address them using standard offsets, but only from | ||
302 | * the second base address, which is 0x20 in the page | ||
303 | */ | ||
304 | if (vic_2nd_block) { | ||
305 | writel(0, base + VIC_PL190_VECT_ADDR); | ||
306 | for (i = 0; i < 19; i++) { | ||
307 | unsigned int value; | ||
308 | |||
309 | value = readl(base + VIC_PL190_VECT_ADDR); | ||
310 | writel(value, base + VIC_PL190_VECT_ADDR); | ||
311 | } | ||
312 | /* ST has 16 vectors as well, but we don't enable them by now */ | ||
313 | for (i = 0; i < 16; i++) { | ||
314 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | ||
315 | writel(0, reg); | ||
316 | } | ||
317 | |||
318 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | ||
319 | } | ||
320 | |||
321 | for (i = 0; i < 32; i++) { | ||
322 | if (vic_sources & (1 << i)) { | ||
323 | unsigned int irq = irq_start + i; | ||
324 | |||
325 | set_irq_chip(irq, &vic_chip); | ||
326 | set_irq_chip_data(irq, base); | ||
327 | set_irq_handler(irq, handle_level_irq); | ||
328 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
329 | } | ||
330 | } | ||
331 | } | ||
276 | 332 | ||
277 | /** | 333 | /** |
278 | * vic_init - initialise a vectored interrupt controller | 334 | * vic_init - initialise a vectored interrupt controller |
@@ -299,7 +355,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, | |||
299 | 355 | ||
300 | switch(vendor) { | 356 | switch(vendor) { |
301 | case AMBA_VENDOR_ST: | 357 | case AMBA_VENDOR_ST: |
302 | vik_init_st(base, irq_start, vic_sources); | 358 | vic_init_st(base, irq_start, vic_sources); |
303 | return; | 359 | return; |
304 | default: | 360 | default: |
305 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); | 361 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); |
@@ -343,60 +399,3 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, | |||
343 | 399 | ||
344 | vic_pm_register(base, irq_start, resume_sources); | 400 | vic_pm_register(base, irq_start, resume_sources); |
345 | } | 401 | } |
346 | |||
347 | /* | ||
348 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | ||
349 | * The original cell has 32 interrupts, while the modified one has 64, | ||
350 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | ||
351 | * the probe function is called twice, with base set to offset 000 | ||
352 | * and 020 within the page. We call this "second block". | ||
353 | */ | ||
354 | static void __init vik_init_st(void __iomem *base, unsigned int irq_start, | ||
355 | u32 vic_sources) | ||
356 | { | ||
357 | unsigned int i; | ||
358 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | ||
359 | |||
360 | /* Disable all interrupts initially. */ | ||
361 | |||
362 | writel(0, base + VIC_INT_SELECT); | ||
363 | writel(0, base + VIC_INT_ENABLE); | ||
364 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | ||
365 | writel(0, base + VIC_IRQ_STATUS); | ||
366 | writel(0, base + VIC_ITCR); | ||
367 | writel(~0, base + VIC_INT_SOFT_CLEAR); | ||
368 | |||
369 | /* | ||
370 | * Make sure we clear all existing interrupts. The vector registers | ||
371 | * in this cell are after the second block of general registers, | ||
372 | * so we can address them using standard offsets, but only from | ||
373 | * the second base address, which is 0x20 in the page | ||
374 | */ | ||
375 | if (vic_2nd_block) { | ||
376 | writel(0, base + VIC_PL190_VECT_ADDR); | ||
377 | for (i = 0; i < 19; i++) { | ||
378 | unsigned int value; | ||
379 | |||
380 | value = readl(base + VIC_PL190_VECT_ADDR); | ||
381 | writel(value, base + VIC_PL190_VECT_ADDR); | ||
382 | } | ||
383 | /* ST has 16 vectors as well, but we don't enable them by now */ | ||
384 | for (i = 0; i < 16; i++) { | ||
385 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | ||
386 | writel(0, reg); | ||
387 | } | ||
388 | |||
389 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | ||
390 | } | ||
391 | |||
392 | for (i = 0; i < 32; i++) { | ||
393 | if (vic_sources & (1 << i)) { | ||
394 | unsigned int irq = irq_start + i; | ||
395 | |||
396 | set_irq_chip(irq, &vic_chip); | ||
397 | set_irq_chip_data(irq, base); | ||
398 | set_irq_handler(irq, handle_level_irq); | ||
399 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
400 | } | ||
401 | } | ||
402 | } | ||
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig new file mode 100644 index 000000000000..76d724b8041a --- /dev/null +++ b/arch/arm/configs/at572d940hfek_defconfig | |||
@@ -0,0 +1,1640 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.28-rc7 | ||
4 | # Fri Dec 5 10:58:47 2008 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | CONFIG_GENERIC_TIME=y | ||
10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
11 | CONFIG_MMU=y | ||
12 | # CONFIG_NO_IOPORT is not set | ||
13 | CONFIG_GENERIC_HARDIRQS=y | ||
14 | CONFIG_STACKTRACE_SUPPORT=y | ||
15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
16 | CONFIG_LOCKDEP_SUPPORT=y | ||
17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
23 | CONFIG_GENERIC_HWEIGHT=y | ||
24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
28 | |||
29 | # | ||
30 | # General setup | ||
31 | # | ||
32 | CONFIG_EXPERIMENTAL=y | ||
33 | CONFIG_BROKEN_ON_SMP=y | ||
34 | CONFIG_LOCK_KERNEL=y | ||
35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
36 | CONFIG_LOCALVERSION="-AT572D940HF" | ||
37 | # CONFIG_LOCALVERSION_AUTO is not set | ||
38 | CONFIG_SWAP=y | ||
39 | CONFIG_SYSVIPC=y | ||
40 | CONFIG_SYSVIPC_SYSCTL=y | ||
41 | CONFIG_POSIX_MQUEUE=y | ||
42 | CONFIG_BSD_PROCESS_ACCT=y | ||
43 | CONFIG_BSD_PROCESS_ACCT_V3=y | ||
44 | CONFIG_TASKSTATS=y | ||
45 | # CONFIG_TASK_DELAY_ACCT is not set | ||
46 | CONFIG_TASK_XACCT=y | ||
47 | CONFIG_TASK_IO_ACCOUNTING=y | ||
48 | CONFIG_AUDIT=y | ||
49 | # CONFIG_IKCONFIG is not set | ||
50 | CONFIG_LOG_BUF_SHIFT=17 | ||
51 | CONFIG_CGROUPS=y | ||
52 | # CONFIG_CGROUP_DEBUG is not set | ||
53 | # CONFIG_CGROUP_NS is not set | ||
54 | # CONFIG_CGROUP_FREEZER is not set | ||
55 | # CONFIG_CGROUP_DEVICE is not set | ||
56 | CONFIG_GROUP_SCHED=y | ||
57 | CONFIG_FAIR_GROUP_SCHED=y | ||
58 | CONFIG_RT_GROUP_SCHED=y | ||
59 | # CONFIG_USER_SCHED is not set | ||
60 | CONFIG_CGROUP_SCHED=y | ||
61 | CONFIG_CGROUP_CPUACCT=y | ||
62 | # CONFIG_RESOURCE_COUNTERS is not set | ||
63 | CONFIG_SYSFS_DEPRECATED=y | ||
64 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
65 | CONFIG_RELAY=y | ||
66 | # CONFIG_NAMESPACES is not set | ||
67 | CONFIG_BLK_DEV_INITRD=y | ||
68 | CONFIG_INITRAMFS_SOURCE="" | ||
69 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
70 | CONFIG_SYSCTL=y | ||
71 | CONFIG_EMBEDDED=y | ||
72 | CONFIG_UID16=y | ||
73 | CONFIG_SYSCTL_SYSCALL=y | ||
74 | CONFIG_KALLSYMS=y | ||
75 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
76 | CONFIG_HOTPLUG=y | ||
77 | CONFIG_PRINTK=y | ||
78 | CONFIG_BUG=y | ||
79 | CONFIG_ELF_CORE=y | ||
80 | CONFIG_COMPAT_BRK=y | ||
81 | CONFIG_BASE_FULL=y | ||
82 | CONFIG_FUTEX=y | ||
83 | CONFIG_ANON_INODES=y | ||
84 | CONFIG_EPOLL=y | ||
85 | CONFIG_SIGNALFD=y | ||
86 | CONFIG_TIMERFD=y | ||
87 | CONFIG_EVENTFD=y | ||
88 | CONFIG_SHMEM=y | ||
89 | CONFIG_AIO=y | ||
90 | CONFIG_VM_EVENT_COUNTERS=y | ||
91 | CONFIG_SLAB=y | ||
92 | # CONFIG_SLUB is not set | ||
93 | # CONFIG_SLOB is not set | ||
94 | CONFIG_PROFILING=y | ||
95 | CONFIG_MARKERS=y | ||
96 | CONFIG_OPROFILE=m | ||
97 | CONFIG_HAVE_OPROFILE=y | ||
98 | CONFIG_KPROBES=y | ||
99 | CONFIG_KRETPROBES=y | ||
100 | CONFIG_HAVE_KPROBES=y | ||
101 | CONFIG_HAVE_KRETPROBES=y | ||
102 | CONFIG_HAVE_CLK=y | ||
103 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
104 | CONFIG_SLABINFO=y | ||
105 | CONFIG_RT_MUTEXES=y | ||
106 | # CONFIG_TINY_SHMEM is not set | ||
107 | CONFIG_BASE_SMALL=0 | ||
108 | CONFIG_MODULES=y | ||
109 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
110 | CONFIG_MODULE_UNLOAD=y | ||
111 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
112 | CONFIG_MODVERSIONS=y | ||
113 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
114 | CONFIG_KMOD=y | ||
115 | CONFIG_BLOCK=y | ||
116 | # CONFIG_LBD is not set | ||
117 | CONFIG_BLK_DEV_IO_TRACE=y | ||
118 | # CONFIG_LSF is not set | ||
119 | # CONFIG_BLK_DEV_BSG is not set | ||
120 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
121 | |||
122 | # | ||
123 | # IO Schedulers | ||
124 | # | ||
125 | CONFIG_IOSCHED_NOOP=y | ||
126 | CONFIG_IOSCHED_AS=y | ||
127 | CONFIG_IOSCHED_DEADLINE=y | ||
128 | CONFIG_IOSCHED_CFQ=y | ||
129 | # CONFIG_DEFAULT_AS is not set | ||
130 | # CONFIG_DEFAULT_DEADLINE is not set | ||
131 | CONFIG_DEFAULT_CFQ=y | ||
132 | # CONFIG_DEFAULT_NOOP is not set | ||
133 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
134 | CONFIG_CLASSIC_RCU=y | ||
135 | # CONFIG_FREEZER is not set | ||
136 | |||
137 | # | ||
138 | # System Type | ||
139 | # | ||
140 | # CONFIG_ARCH_AAEC2000 is not set | ||
141 | # CONFIG_ARCH_INTEGRATOR is not set | ||
142 | # CONFIG_ARCH_REALVIEW is not set | ||
143 | # CONFIG_ARCH_VERSATILE is not set | ||
144 | CONFIG_ARCH_AT91=y | ||
145 | # CONFIG_ARCH_CLPS7500 is not set | ||
146 | # CONFIG_ARCH_CLPS711X is not set | ||
147 | # CONFIG_ARCH_EBSA110 is not set | ||
148 | # CONFIG_ARCH_EP93XX is not set | ||
149 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
150 | # CONFIG_ARCH_NETX is not set | ||
151 | # CONFIG_ARCH_H720X is not set | ||
152 | # CONFIG_ARCH_IMX is not set | ||
153 | # CONFIG_ARCH_IOP13XX is not set | ||
154 | # CONFIG_ARCH_IOP32X is not set | ||
155 | # CONFIG_ARCH_IOP33X is not set | ||
156 | # CONFIG_ARCH_IXP23XX is not set | ||
157 | # CONFIG_ARCH_IXP2000 is not set | ||
158 | # CONFIG_ARCH_IXP4XX is not set | ||
159 | # CONFIG_ARCH_L7200 is not set | ||
160 | # CONFIG_ARCH_KIRKWOOD is not set | ||
161 | # CONFIG_ARCH_KS8695 is not set | ||
162 | # CONFIG_ARCH_NS9XXX is not set | ||
163 | # CONFIG_ARCH_LOKI is not set | ||
164 | # CONFIG_ARCH_MV78XX0 is not set | ||
165 | # CONFIG_ARCH_MXC is not set | ||
166 | # CONFIG_ARCH_ORION5X is not set | ||
167 | # CONFIG_ARCH_PNX4008 is not set | ||
168 | # CONFIG_ARCH_PXA is not set | ||
169 | # CONFIG_ARCH_RPC is not set | ||
170 | # CONFIG_ARCH_SA1100 is not set | ||
171 | # CONFIG_ARCH_S3C2410 is not set | ||
172 | # CONFIG_ARCH_SHARK is not set | ||
173 | # CONFIG_ARCH_LH7A40X is not set | ||
174 | # CONFIG_ARCH_DAVINCI is not set | ||
175 | # CONFIG_ARCH_OMAP is not set | ||
176 | # CONFIG_ARCH_MSM is not set | ||
177 | |||
178 | # | ||
179 | # Boot options | ||
180 | # | ||
181 | |||
182 | # | ||
183 | # Power management | ||
184 | # | ||
185 | |||
186 | # | ||
187 | # Atmel AT91 System-on-Chip | ||
188 | # | ||
189 | # CONFIG_ARCH_AT91RM9200 is not set | ||
190 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
191 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
192 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
193 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
194 | # CONFIG_ARCH_AT91SAM9G20 is not set | ||
195 | # CONFIG_ARCH_AT91CAP9 is not set | ||
196 | # CONFIG_ARCH_AT91X40 is not set | ||
197 | CONFIG_ARCH_AT572D940HF=y | ||
198 | CONFIG_AT91_PMC_UNIT=y | ||
199 | |||
200 | # | ||
201 | # AT572D940HF Board Type | ||
202 | # | ||
203 | CONFIG_MACH_AT572D940HFEB=y | ||
204 | |||
205 | # | ||
206 | # AT91 Board Options | ||
207 | # | ||
208 | # CONFIG_MTD_AT91_DATAFLASH_CARD is not set | ||
209 | # CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set | ||
210 | CONFIG_NUM_SERIAL=3 | ||
211 | |||
212 | # | ||
213 | # AT91 Feature Selections | ||
214 | # | ||
215 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | ||
216 | CONFIG_AT91_TIMER_HZ=100 | ||
217 | CONFIG_AT91_EARLY_DBGU=y | ||
218 | # CONFIG_AT91_EARLY_USART0 is not set | ||
219 | # CONFIG_AT91_EARLY_USART1 is not set | ||
220 | # CONFIG_AT91_EARLY_USART2 is not set | ||
221 | # CONFIG_AT91_EARLY_USART3 is not set | ||
222 | # CONFIG_AT91_EARLY_USART4 is not set | ||
223 | # CONFIG_AT91_EARLY_USART5 is not set | ||
224 | |||
225 | # | ||
226 | # Processor Type | ||
227 | # | ||
228 | CONFIG_CPU_32=y | ||
229 | CONFIG_CPU_ARM926T=y | ||
230 | CONFIG_CPU_32v5=y | ||
231 | CONFIG_CPU_ABRT_EV5TJ=y | ||
232 | CONFIG_CPU_PABRT_NOIFAR=y | ||
233 | CONFIG_CPU_CACHE_VIVT=y | ||
234 | CONFIG_CPU_COPY_V4WB=y | ||
235 | CONFIG_CPU_TLB_V4WBI=y | ||
236 | CONFIG_CPU_CP15=y | ||
237 | CONFIG_CPU_CP15_MMU=y | ||
238 | |||
239 | # | ||
240 | # Processor Features | ||
241 | # | ||
242 | CONFIG_ARM_THUMB=y | ||
243 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
244 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
245 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
246 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
247 | # CONFIG_OUTER_CACHE is not set | ||
248 | |||
249 | # | ||
250 | # Bus support | ||
251 | # | ||
252 | # CONFIG_PCI_SYSCALL is not set | ||
253 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
254 | # CONFIG_PCCARD is not set | ||
255 | |||
256 | # | ||
257 | # Kernel Features | ||
258 | # | ||
259 | CONFIG_TICK_ONESHOT=y | ||
260 | CONFIG_NO_HZ=y | ||
261 | CONFIG_HIGH_RES_TIMERS=y | ||
262 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
263 | CONFIG_VMSPLIT_3G=y | ||
264 | # CONFIG_VMSPLIT_2G is not set | ||
265 | # CONFIG_VMSPLIT_1G is not set | ||
266 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
267 | CONFIG_PREEMPT=y | ||
268 | CONFIG_HZ=100 | ||
269 | # CONFIG_AEABI is not set | ||
270 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
271 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
272 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
273 | CONFIG_SELECT_MEMORY_MODEL=y | ||
274 | CONFIG_FLATMEM_MANUAL=y | ||
275 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
276 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
277 | CONFIG_FLATMEM=y | ||
278 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
279 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
280 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
281 | CONFIG_RESOURCES_64BIT=y | ||
282 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
283 | CONFIG_ZONE_DMA_FLAG=0 | ||
284 | CONFIG_VIRT_TO_BUS=y | ||
285 | CONFIG_UNEVICTABLE_LRU=y | ||
286 | # CONFIG_LEDS is not set | ||
287 | CONFIG_ALIGNMENT_TRAP=y | ||
288 | |||
289 | # | ||
290 | # Boot options | ||
291 | # | ||
292 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
293 | CONFIG_ZBOOT_ROM_BSS=0 | ||
294 | CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181" | ||
295 | # CONFIG_XIP_KERNEL is not set | ||
296 | CONFIG_KEXEC=y | ||
297 | CONFIG_ATAGS_PROC=y | ||
298 | |||
299 | # | ||
300 | # CPU Power Management | ||
301 | # | ||
302 | # CONFIG_CPU_IDLE is not set | ||
303 | |||
304 | # | ||
305 | # Floating point emulation | ||
306 | # | ||
307 | |||
308 | # | ||
309 | # At least one emulation must be selected | ||
310 | # | ||
311 | CONFIG_FPE_NWFPE=y | ||
312 | CONFIG_FPE_NWFPE_XP=y | ||
313 | # CONFIG_FPE_FASTFPE is not set | ||
314 | # CONFIG_VFP is not set | ||
315 | |||
316 | # | ||
317 | # Userspace binary formats | ||
318 | # | ||
319 | CONFIG_BINFMT_ELF=y | ||
320 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
321 | CONFIG_HAVE_AOUT=y | ||
322 | # CONFIG_BINFMT_AOUT is not set | ||
323 | # CONFIG_BINFMT_MISC is not set | ||
324 | # CONFIG_ARTHUR is not set | ||
325 | |||
326 | # | ||
327 | # Power management options | ||
328 | # | ||
329 | # CONFIG_PM is not set | ||
330 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
331 | CONFIG_NET=y | ||
332 | |||
333 | # | ||
334 | # Networking options | ||
335 | # | ||
336 | CONFIG_PACKET=m | ||
337 | CONFIG_PACKET_MMAP=y | ||
338 | CONFIG_UNIX=y | ||
339 | # CONFIG_NET_KEY is not set | ||
340 | CONFIG_INET=y | ||
341 | # CONFIG_IP_MULTICAST is not set | ||
342 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
343 | CONFIG_IP_FIB_HASH=y | ||
344 | # CONFIG_IP_PNP is not set | ||
345 | # CONFIG_NET_IPIP is not set | ||
346 | # CONFIG_NET_IPGRE is not set | ||
347 | # CONFIG_ARPD is not set | ||
348 | # CONFIG_SYN_COOKIES is not set | ||
349 | # CONFIG_INET_AH is not set | ||
350 | # CONFIG_INET_ESP is not set | ||
351 | # CONFIG_INET_IPCOMP is not set | ||
352 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
353 | # CONFIG_INET_TUNNEL is not set | ||
354 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
355 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
356 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
357 | # CONFIG_INET_LRO is not set | ||
358 | # CONFIG_INET_DIAG is not set | ||
359 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
360 | CONFIG_TCP_CONG_CUBIC=y | ||
361 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
362 | # CONFIG_TCP_MD5SIG is not set | ||
363 | # CONFIG_IPV6 is not set | ||
364 | # CONFIG_NETWORK_SECMARK is not set | ||
365 | # CONFIG_NETFILTER is not set | ||
366 | # CONFIG_IP_DCCP is not set | ||
367 | CONFIG_IP_SCTP=m | ||
368 | # CONFIG_SCTP_DBG_MSG is not set | ||
369 | # CONFIG_SCTP_DBG_OBJCNT is not set | ||
370 | # CONFIG_SCTP_HMAC_NONE is not set | ||
371 | # CONFIG_SCTP_HMAC_SHA1 is not set | ||
372 | CONFIG_SCTP_HMAC_MD5=y | ||
373 | # CONFIG_TIPC is not set | ||
374 | # CONFIG_ATM is not set | ||
375 | # CONFIG_BRIDGE is not set | ||
376 | # CONFIG_NET_DSA is not set | ||
377 | # CONFIG_VLAN_8021Q is not set | ||
378 | # CONFIG_DECNET is not set | ||
379 | # CONFIG_LLC2 is not set | ||
380 | # CONFIG_IPX is not set | ||
381 | # CONFIG_ATALK is not set | ||
382 | # CONFIG_X25 is not set | ||
383 | # CONFIG_LAPB is not set | ||
384 | # CONFIG_ECONET is not set | ||
385 | # CONFIG_WAN_ROUTER is not set | ||
386 | # CONFIG_NET_SCHED is not set | ||
387 | |||
388 | # | ||
389 | # Network testing | ||
390 | # | ||
391 | CONFIG_NET_PKTGEN=m | ||
392 | CONFIG_NET_TCPPROBE=m | ||
393 | # CONFIG_HAMRADIO is not set | ||
394 | CONFIG_CAN=m | ||
395 | CONFIG_CAN_RAW=m | ||
396 | CONFIG_CAN_BCM=m | ||
397 | |||
398 | # | ||
399 | # CAN Device Drivers | ||
400 | # | ||
401 | CONFIG_CAN_VCAN=m | ||
402 | CONFIG_CAN_DEBUG_DEVICES=y | ||
403 | # CONFIG_IRDA is not set | ||
404 | # CONFIG_BT is not set | ||
405 | # CONFIG_AF_RXRPC is not set | ||
406 | # CONFIG_PHONET is not set | ||
407 | CONFIG_WIRELESS=y | ||
408 | # CONFIG_CFG80211 is not set | ||
409 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
410 | CONFIG_WIRELESS_EXT=y | ||
411 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
412 | # CONFIG_MAC80211 is not set | ||
413 | CONFIG_IEEE80211=m | ||
414 | # CONFIG_IEEE80211_DEBUG is not set | ||
415 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
416 | # CONFIG_IEEE80211_CRYPT_CCMP is not set | ||
417 | # CONFIG_IEEE80211_CRYPT_TKIP is not set | ||
418 | # CONFIG_RFKILL is not set | ||
419 | # CONFIG_NET_9P is not set | ||
420 | |||
421 | # | ||
422 | # Device Drivers | ||
423 | # | ||
424 | |||
425 | # | ||
426 | # Generic Driver Options | ||
427 | # | ||
428 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
429 | CONFIG_STANDALONE=y | ||
430 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
431 | CONFIG_FW_LOADER=y | ||
432 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
433 | CONFIG_EXTRA_FIRMWARE="" | ||
434 | # CONFIG_SYS_HYPERVISOR is not set | ||
435 | CONFIG_CONNECTOR=m | ||
436 | CONFIG_MTD=m | ||
437 | CONFIG_MTD_DEBUG=y | ||
438 | CONFIG_MTD_DEBUG_VERBOSE=1 | ||
439 | CONFIG_MTD_CONCAT=m | ||
440 | CONFIG_MTD_PARTITIONS=y | ||
441 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
442 | # CONFIG_MTD_AFS_PARTS is not set | ||
443 | # CONFIG_MTD_AR7_PARTS is not set | ||
444 | |||
445 | # | ||
446 | # User Modules And Translation Layers | ||
447 | # | ||
448 | CONFIG_MTD_CHAR=m | ||
449 | CONFIG_MTD_BLKDEVS=m | ||
450 | CONFIG_MTD_BLOCK=m | ||
451 | CONFIG_MTD_BLOCK_RO=m | ||
452 | CONFIG_FTL=m | ||
453 | CONFIG_NFTL=m | ||
454 | CONFIG_NFTL_RW=y | ||
455 | CONFIG_INFTL=m | ||
456 | CONFIG_RFD_FTL=m | ||
457 | CONFIG_SSFDC=m | ||
458 | CONFIG_MTD_OOPS=m | ||
459 | |||
460 | # | ||
461 | # RAM/ROM/Flash chip drivers | ||
462 | # | ||
463 | CONFIG_MTD_CFI=m | ||
464 | CONFIG_MTD_JEDECPROBE=m | ||
465 | CONFIG_MTD_GEN_PROBE=m | ||
466 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
467 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
468 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
469 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
470 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
471 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
472 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
473 | CONFIG_MTD_CFI_I1=y | ||
474 | CONFIG_MTD_CFI_I2=y | ||
475 | # CONFIG_MTD_CFI_I4 is not set | ||
476 | # CONFIG_MTD_CFI_I8 is not set | ||
477 | CONFIG_MTD_CFI_INTELEXT=m | ||
478 | CONFIG_MTD_CFI_AMDSTD=m | ||
479 | CONFIG_MTD_CFI_STAA=m | ||
480 | CONFIG_MTD_CFI_UTIL=m | ||
481 | CONFIG_MTD_RAM=m | ||
482 | CONFIG_MTD_ROM=m | ||
483 | CONFIG_MTD_ABSENT=m | ||
484 | |||
485 | # | ||
486 | # Mapping drivers for chip access | ||
487 | # | ||
488 | CONFIG_MTD_COMPLEX_MAPPINGS=y | ||
489 | CONFIG_MTD_PHYSMAP=m | ||
490 | CONFIG_MTD_PHYSMAP_START=0x8000000 | ||
491 | CONFIG_MTD_PHYSMAP_LEN=0x4000000 | ||
492 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
493 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
494 | # CONFIG_MTD_IMPA7 is not set | ||
495 | CONFIG_MTD_PLATRAM=m | ||
496 | |||
497 | # | ||
498 | # Self-contained MTD device drivers | ||
499 | # | ||
500 | CONFIG_MTD_DATAFLASH=m | ||
501 | # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set | ||
502 | # CONFIG_MTD_DATAFLASH_OTP is not set | ||
503 | CONFIG_MTD_M25P80=m | ||
504 | CONFIG_M25PXX_USE_FAST_READ=y | ||
505 | CONFIG_MTD_SLRAM=m | ||
506 | CONFIG_MTD_PHRAM=m | ||
507 | CONFIG_MTD_MTDRAM=m | ||
508 | CONFIG_MTDRAM_TOTAL_SIZE=4096 | ||
509 | CONFIG_MTDRAM_ERASE_SIZE=128 | ||
510 | CONFIG_MTD_BLOCK2MTD=m | ||
511 | |||
512 | # | ||
513 | # Disk-On-Chip Device Drivers | ||
514 | # | ||
515 | # CONFIG_MTD_DOC2000 is not set | ||
516 | # CONFIG_MTD_DOC2001 is not set | ||
517 | # CONFIG_MTD_DOC2001PLUS is not set | ||
518 | CONFIG_MTD_NAND=m | ||
519 | CONFIG_MTD_NAND_VERIFY_WRITE=y | ||
520 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
521 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
522 | # CONFIG_MTD_NAND_GPIO is not set | ||
523 | CONFIG_MTD_NAND_IDS=m | ||
524 | CONFIG_MTD_NAND_DISKONCHIP=m | ||
525 | # CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set | ||
526 | CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 | ||
527 | # CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set | ||
528 | # CONFIG_MTD_NAND_ATMEL is not set | ||
529 | CONFIG_MTD_NAND_NANDSIM=m | ||
530 | CONFIG_MTD_NAND_PLATFORM=m | ||
531 | CONFIG_MTD_ALAUDA=m | ||
532 | # CONFIG_MTD_ONENAND is not set | ||
533 | |||
534 | # | ||
535 | # UBI - Unsorted block images | ||
536 | # | ||
537 | CONFIG_MTD_UBI=m | ||
538 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
539 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
540 | CONFIG_MTD_UBI_GLUEBI=y | ||
541 | |||
542 | # | ||
543 | # UBI debugging options | ||
544 | # | ||
545 | # CONFIG_MTD_UBI_DEBUG is not set | ||
546 | # CONFIG_PARPORT is not set | ||
547 | CONFIG_BLK_DEV=y | ||
548 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
549 | CONFIG_BLK_DEV_LOOP=y | ||
550 | CONFIG_BLK_DEV_CRYPTOLOOP=m | ||
551 | CONFIG_BLK_DEV_NBD=m | ||
552 | # CONFIG_BLK_DEV_UB is not set | ||
553 | CONFIG_BLK_DEV_RAM=y | ||
554 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
555 | CONFIG_BLK_DEV_RAM_SIZE=65536 | ||
556 | # CONFIG_BLK_DEV_XIP is not set | ||
557 | # CONFIG_CDROM_PKTCDVD is not set | ||
558 | # CONFIG_ATA_OVER_ETH is not set | ||
559 | CONFIG_MISC_DEVICES=y | ||
560 | CONFIG_ATMEL_TCLIB=y | ||
561 | CONFIG_ATMEL_TCB_CLKSRC=y | ||
562 | CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0 | ||
563 | # CONFIG_EEPROM_93CX6 is not set | ||
564 | # CONFIG_ICS932S401 is not set | ||
565 | CONFIG_ATMEL_SSC=m | ||
566 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
567 | # CONFIG_C2PORT is not set | ||
568 | CONFIG_HAVE_IDE=y | ||
569 | # CONFIG_IDE is not set | ||
570 | |||
571 | # | ||
572 | # SCSI device support | ||
573 | # | ||
574 | CONFIG_RAID_ATTRS=m | ||
575 | CONFIG_SCSI=m | ||
576 | CONFIG_SCSI_DMA=y | ||
577 | CONFIG_SCSI_TGT=m | ||
578 | # CONFIG_SCSI_NETLINK is not set | ||
579 | # CONFIG_SCSI_PROC_FS is not set | ||
580 | |||
581 | # | ||
582 | # SCSI support type (disk, tape, CD-ROM) | ||
583 | # | ||
584 | CONFIG_BLK_DEV_SD=m | ||
585 | # CONFIG_CHR_DEV_ST is not set | ||
586 | # CONFIG_CHR_DEV_OSST is not set | ||
587 | CONFIG_BLK_DEV_SR=m | ||
588 | # CONFIG_BLK_DEV_SR_VENDOR is not set | ||
589 | CONFIG_CHR_DEV_SG=m | ||
590 | CONFIG_CHR_DEV_SCH=m | ||
591 | |||
592 | # | ||
593 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
594 | # | ||
595 | CONFIG_SCSI_MULTI_LUN=y | ||
596 | CONFIG_SCSI_CONSTANTS=y | ||
597 | CONFIG_SCSI_LOGGING=y | ||
598 | CONFIG_SCSI_SCAN_ASYNC=y | ||
599 | CONFIG_SCSI_WAIT_SCAN=m | ||
600 | |||
601 | # | ||
602 | # SCSI Transports | ||
603 | # | ||
604 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
605 | # CONFIG_SCSI_FC_ATTRS is not set | ||
606 | CONFIG_SCSI_ISCSI_ATTRS=m | ||
607 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
608 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
609 | CONFIG_SCSI_LOWLEVEL=y | ||
610 | # CONFIG_ISCSI_TCP is not set | ||
611 | # CONFIG_SCSI_DEBUG is not set | ||
612 | # CONFIG_SCSI_DH is not set | ||
613 | # CONFIG_ATA is not set | ||
614 | # CONFIG_MD is not set | ||
615 | CONFIG_NETDEVICES=y | ||
616 | CONFIG_DUMMY=m | ||
617 | CONFIG_BONDING=m | ||
618 | CONFIG_MACVLAN=m | ||
619 | CONFIG_EQUALIZER=m | ||
620 | CONFIG_TUN=m | ||
621 | CONFIG_VETH=m | ||
622 | CONFIG_PHYLIB=y | ||
623 | |||
624 | # | ||
625 | # MII PHY device drivers | ||
626 | # | ||
627 | CONFIG_MARVELL_PHY=m | ||
628 | CONFIG_DAVICOM_PHY=m | ||
629 | CONFIG_QSEMI_PHY=m | ||
630 | CONFIG_LXT_PHY=m | ||
631 | CONFIG_CICADA_PHY=m | ||
632 | CONFIG_VITESSE_PHY=m | ||
633 | CONFIG_SMSC_PHY=m | ||
634 | CONFIG_BROADCOM_PHY=m | ||
635 | CONFIG_ICPLUS_PHY=m | ||
636 | # CONFIG_REALTEK_PHY is not set | ||
637 | # CONFIG_FIXED_PHY is not set | ||
638 | CONFIG_MDIO_BITBANG=m | ||
639 | CONFIG_NET_ETHERNET=y | ||
640 | CONFIG_MII=m | ||
641 | CONFIG_MACB=y | ||
642 | # CONFIG_AX88796 is not set | ||
643 | # CONFIG_SMC91X is not set | ||
644 | # CONFIG_DM9000 is not set | ||
645 | # CONFIG_ENC28J60 is not set | ||
646 | # CONFIG_SMC911X is not set | ||
647 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
648 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
649 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
650 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
651 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
652 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
653 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
654 | # CONFIG_B44 is not set | ||
655 | # CONFIG_NETDEV_1000 is not set | ||
656 | # CONFIG_NETDEV_10000 is not set | ||
657 | |||
658 | # | ||
659 | # Wireless LAN | ||
660 | # | ||
661 | CONFIG_WLAN_PRE80211=y | ||
662 | CONFIG_STRIP=m | ||
663 | CONFIG_WLAN_80211=y | ||
664 | CONFIG_LIBERTAS=m | ||
665 | CONFIG_LIBERTAS_USB=m | ||
666 | CONFIG_LIBERTAS_SDIO=m | ||
667 | # CONFIG_LIBERTAS_DEBUG is not set | ||
668 | CONFIG_USB_ZD1201=m | ||
669 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
670 | # CONFIG_IWLWIFI_LEDS is not set | ||
671 | CONFIG_HOSTAP=m | ||
672 | CONFIG_HOSTAP_FIRMWARE=y | ||
673 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
674 | |||
675 | # | ||
676 | # USB Network Adapters | ||
677 | # | ||
678 | CONFIG_USB_CATC=m | ||
679 | CONFIG_USB_KAWETH=m | ||
680 | CONFIG_USB_PEGASUS=m | ||
681 | CONFIG_USB_RTL8150=m | ||
682 | CONFIG_USB_USBNET=m | ||
683 | CONFIG_USB_NET_AX8817X=m | ||
684 | CONFIG_USB_NET_CDCETHER=m | ||
685 | CONFIG_USB_NET_DM9601=m | ||
686 | # CONFIG_USB_NET_SMSC95XX is not set | ||
687 | CONFIG_USB_NET_GL620A=m | ||
688 | CONFIG_USB_NET_NET1080=m | ||
689 | CONFIG_USB_NET_PLUSB=m | ||
690 | CONFIG_USB_NET_MCS7830=m | ||
691 | CONFIG_USB_NET_RNDIS_HOST=m | ||
692 | CONFIG_USB_NET_CDC_SUBSET=m | ||
693 | CONFIG_USB_ALI_M5632=y | ||
694 | CONFIG_USB_AN2720=y | ||
695 | CONFIG_USB_BELKIN=y | ||
696 | CONFIG_USB_ARMLINUX=y | ||
697 | CONFIG_USB_EPSON2888=y | ||
698 | CONFIG_USB_KC2190=y | ||
699 | # CONFIG_USB_NET_ZAURUS is not set | ||
700 | # CONFIG_WAN is not set | ||
701 | # CONFIG_PPP is not set | ||
702 | # CONFIG_SLIP is not set | ||
703 | # CONFIG_NETCONSOLE is not set | ||
704 | # CONFIG_NETPOLL is not set | ||
705 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
706 | # CONFIG_ISDN is not set | ||
707 | |||
708 | # | ||
709 | # Input device support | ||
710 | # | ||
711 | CONFIG_INPUT=y | ||
712 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
713 | CONFIG_INPUT_POLLDEV=m | ||
714 | |||
715 | # | ||
716 | # Userland interfaces | ||
717 | # | ||
718 | CONFIG_INPUT_MOUSEDEV=m | ||
719 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
720 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
721 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
722 | # CONFIG_INPUT_JOYDEV is not set | ||
723 | CONFIG_INPUT_EVDEV=m | ||
724 | CONFIG_INPUT_EVBUG=m | ||
725 | |||
726 | # | ||
727 | # Input Device Drivers | ||
728 | # | ||
729 | CONFIG_INPUT_KEYBOARD=y | ||
730 | CONFIG_KEYBOARD_ATKBD=y | ||
731 | CONFIG_KEYBOARD_SUNKBD=m | ||
732 | CONFIG_KEYBOARD_LKKBD=m | ||
733 | CONFIG_KEYBOARD_XTKBD=m | ||
734 | CONFIG_KEYBOARD_NEWTON=m | ||
735 | CONFIG_KEYBOARD_STOWAWAY=m | ||
736 | CONFIG_KEYBOARD_GPIO=m | ||
737 | CONFIG_INPUT_MOUSE=y | ||
738 | CONFIG_MOUSE_PS2=m | ||
739 | CONFIG_MOUSE_PS2_ALPS=y | ||
740 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
741 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
742 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
743 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
744 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
745 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
746 | CONFIG_MOUSE_SERIAL=m | ||
747 | CONFIG_MOUSE_APPLETOUCH=m | ||
748 | # CONFIG_MOUSE_BCM5974 is not set | ||
749 | CONFIG_MOUSE_VSXXXAA=m | ||
750 | CONFIG_MOUSE_GPIO=m | ||
751 | # CONFIG_INPUT_JOYSTICK is not set | ||
752 | # CONFIG_INPUT_TABLET is not set | ||
753 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
754 | CONFIG_INPUT_MISC=y | ||
755 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
756 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
757 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
758 | # CONFIG_INPUT_POWERMATE is not set | ||
759 | # CONFIG_INPUT_YEALINK is not set | ||
760 | # CONFIG_INPUT_CM109 is not set | ||
761 | CONFIG_INPUT_UINPUT=m | ||
762 | |||
763 | # | ||
764 | # Hardware I/O ports | ||
765 | # | ||
766 | CONFIG_SERIO=y | ||
767 | CONFIG_SERIO_SERPORT=m | ||
768 | CONFIG_SERIO_LIBPS2=y | ||
769 | CONFIG_SERIO_RAW=m | ||
770 | # CONFIG_GAMEPORT is not set | ||
771 | |||
772 | # | ||
773 | # Character devices | ||
774 | # | ||
775 | CONFIG_VT=y | ||
776 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
777 | CONFIG_VT_CONSOLE=y | ||
778 | CONFIG_HW_CONSOLE=y | ||
779 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
780 | CONFIG_DEVKMEM=y | ||
781 | CONFIG_SERIAL_NONSTANDARD=y | ||
782 | CONFIG_N_HDLC=m | ||
783 | # CONFIG_RISCOM8 is not set | ||
784 | CONFIG_SPECIALIX=m | ||
785 | CONFIG_RIO=m | ||
786 | # CONFIG_RIO_OLDPCI is not set | ||
787 | CONFIG_STALDRV=y | ||
788 | |||
789 | # | ||
790 | # Serial drivers | ||
791 | # | ||
792 | # CONFIG_SERIAL_8250 is not set | ||
793 | |||
794 | # | ||
795 | # Non-8250 serial port support | ||
796 | # | ||
797 | CONFIG_SERIAL_ATMEL=y | ||
798 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
799 | CONFIG_SERIAL_ATMEL_PDC=y | ||
800 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
801 | CONFIG_SERIAL_CORE=y | ||
802 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
803 | CONFIG_UNIX98_PTYS=y | ||
804 | CONFIG_LEGACY_PTYS=y | ||
805 | CONFIG_LEGACY_PTY_COUNT=256 | ||
806 | CONFIG_IPMI_HANDLER=m | ||
807 | # CONFIG_IPMI_PANIC_EVENT is not set | ||
808 | CONFIG_IPMI_DEVICE_INTERFACE=m | ||
809 | CONFIG_IPMI_SI=m | ||
810 | CONFIG_IPMI_WATCHDOG=m | ||
811 | CONFIG_IPMI_POWEROFF=m | ||
812 | CONFIG_HW_RANDOM=y | ||
813 | CONFIG_NVRAM=m | ||
814 | CONFIG_R3964=m | ||
815 | CONFIG_RAW_DRIVER=m | ||
816 | CONFIG_MAX_RAW_DEVS=256 | ||
817 | CONFIG_TCG_TPM=m | ||
818 | CONFIG_TCG_NSC=m | ||
819 | CONFIG_TCG_ATMEL=m | ||
820 | CONFIG_I2C=m | ||
821 | CONFIG_I2C_BOARDINFO=y | ||
822 | CONFIG_I2C_CHARDEV=m | ||
823 | CONFIG_I2C_HELPER_AUTO=y | ||
824 | |||
825 | # | ||
826 | # I2C Hardware Bus support | ||
827 | # | ||
828 | |||
829 | # | ||
830 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
831 | # | ||
832 | # CONFIG_I2C_GPIO is not set | ||
833 | # CONFIG_I2C_OCORES is not set | ||
834 | # CONFIG_I2C_SIMTEC is not set | ||
835 | |||
836 | # | ||
837 | # External I2C/SMBus adapter drivers | ||
838 | # | ||
839 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
840 | # CONFIG_I2C_TAOS_EVM is not set | ||
841 | # CONFIG_I2C_TINY_USB is not set | ||
842 | |||
843 | # | ||
844 | # Other I2C/SMBus bus drivers | ||
845 | # | ||
846 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
847 | # CONFIG_I2C_STUB is not set | ||
848 | |||
849 | # | ||
850 | # Miscellaneous I2C Chip support | ||
851 | # | ||
852 | CONFIG_DS1682=m | ||
853 | # CONFIG_AT24 is not set | ||
854 | CONFIG_SENSORS_EEPROM=m | ||
855 | CONFIG_SENSORS_PCF8574=m | ||
856 | # CONFIG_PCF8575 is not set | ||
857 | # CONFIG_SENSORS_PCA9539 is not set | ||
858 | CONFIG_SENSORS_PCF8591=m | ||
859 | CONFIG_SENSORS_MAX6875=m | ||
860 | CONFIG_SENSORS_TSL2550=m | ||
861 | # CONFIG_I2C_DEBUG_CORE is not set | ||
862 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
863 | # CONFIG_I2C_DEBUG_BUS is not set | ||
864 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
865 | CONFIG_SPI=y | ||
866 | CONFIG_SPI_MASTER=y | ||
867 | |||
868 | # | ||
869 | # SPI Master Controller Drivers | ||
870 | # | ||
871 | CONFIG_SPI_ATMEL=y | ||
872 | CONFIG_SPI_BITBANG=m | ||
873 | |||
874 | # | ||
875 | # SPI Protocol Masters | ||
876 | # | ||
877 | CONFIG_SPI_AT25=m | ||
878 | CONFIG_SPI_SPIDEV=m | ||
879 | # CONFIG_SPI_TLE62X0 is not set | ||
880 | # CONFIG_W1 is not set | ||
881 | # CONFIG_POWER_SUPPLY is not set | ||
882 | # CONFIG_HWMON is not set | ||
883 | # CONFIG_THERMAL is not set | ||
884 | # CONFIG_THERMAL_HWMON is not set | ||
885 | # CONFIG_WATCHDOG is not set | ||
886 | CONFIG_SSB_POSSIBLE=y | ||
887 | |||
888 | # | ||
889 | # Sonics Silicon Backplane | ||
890 | # | ||
891 | # CONFIG_SSB is not set | ||
892 | |||
893 | # | ||
894 | # Multifunction device drivers | ||
895 | # | ||
896 | # CONFIG_MFD_CORE is not set | ||
897 | # CONFIG_MFD_SM501 is not set | ||
898 | # CONFIG_HTC_PASIC3 is not set | ||
899 | # CONFIG_MFD_TMIO is not set | ||
900 | # CONFIG_MFD_T7L66XB is not set | ||
901 | # CONFIG_MFD_TC6387XB is not set | ||
902 | # CONFIG_MFD_WM8400 is not set | ||
903 | # CONFIG_MFD_WM8350_I2C is not set | ||
904 | |||
905 | # | ||
906 | # Multimedia devices | ||
907 | # | ||
908 | |||
909 | # | ||
910 | # Multimedia core support | ||
911 | # | ||
912 | # CONFIG_VIDEO_DEV is not set | ||
913 | # CONFIG_DVB_CORE is not set | ||
914 | # CONFIG_VIDEO_MEDIA is not set | ||
915 | |||
916 | # | ||
917 | # Multimedia drivers | ||
918 | # | ||
919 | # CONFIG_DAB is not set | ||
920 | |||
921 | # | ||
922 | # Graphics support | ||
923 | # | ||
924 | # CONFIG_VGASTATE is not set | ||
925 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
926 | # CONFIG_FB is not set | ||
927 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
928 | |||
929 | # | ||
930 | # Display device support | ||
931 | # | ||
932 | # CONFIG_DISPLAY_SUPPORT is not set | ||
933 | |||
934 | # | ||
935 | # Console display driver support | ||
936 | # | ||
937 | # CONFIG_VGA_CONSOLE is not set | ||
938 | CONFIG_DUMMY_CONSOLE=y | ||
939 | CONFIG_SOUND=m | ||
940 | CONFIG_SOUND_OSS_CORE=y | ||
941 | CONFIG_SND=m | ||
942 | CONFIG_SND_TIMER=m | ||
943 | CONFIG_SND_PCM=m | ||
944 | CONFIG_SND_HWDEP=m | ||
945 | CONFIG_SND_RAWMIDI=m | ||
946 | CONFIG_SND_SEQUENCER=m | ||
947 | CONFIG_SND_SEQ_DUMMY=m | ||
948 | CONFIG_SND_OSSEMUL=y | ||
949 | CONFIG_SND_MIXER_OSS=m | ||
950 | CONFIG_SND_PCM_OSS=m | ||
951 | # CONFIG_SND_PCM_OSS_PLUGINS is not set | ||
952 | CONFIG_SND_SEQUENCER_OSS=y | ||
953 | CONFIG_SND_DYNAMIC_MINORS=y | ||
954 | CONFIG_SND_SUPPORT_OLD_API=y | ||
955 | # CONFIG_SND_VERBOSE_PROCFS is not set | ||
956 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
957 | # CONFIG_SND_DEBUG is not set | ||
958 | CONFIG_SND_DRIVERS=y | ||
959 | CONFIG_SND_DUMMY=m | ||
960 | CONFIG_SND_VIRMIDI=m | ||
961 | # CONFIG_SND_MTPAV is not set | ||
962 | # CONFIG_SND_SERIAL_U16550 is not set | ||
963 | # CONFIG_SND_MPU401 is not set | ||
964 | CONFIG_SND_ARM=y | ||
965 | CONFIG_SND_SPI=y | ||
966 | # CONFIG_SND_AT73C213 is not set | ||
967 | CONFIG_SND_USB=y | ||
968 | CONFIG_SND_USB_AUDIO=m | ||
969 | CONFIG_SND_USB_CAIAQ=m | ||
970 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
971 | # CONFIG_SND_SOC is not set | ||
972 | # CONFIG_SOUND_PRIME is not set | ||
973 | CONFIG_HID_SUPPORT=y | ||
974 | CONFIG_HID=m | ||
975 | # CONFIG_HID_DEBUG is not set | ||
976 | CONFIG_HIDRAW=y | ||
977 | |||
978 | # | ||
979 | # USB Input Devices | ||
980 | # | ||
981 | CONFIG_USB_HID=m | ||
982 | # CONFIG_HID_PID is not set | ||
983 | CONFIG_USB_HIDDEV=y | ||
984 | |||
985 | # | ||
986 | # USB HID Boot Protocol drivers | ||
987 | # | ||
988 | CONFIG_USB_KBD=m | ||
989 | CONFIG_USB_MOUSE=m | ||
990 | |||
991 | # | ||
992 | # Special HID drivers | ||
993 | # | ||
994 | CONFIG_HID_COMPAT=y | ||
995 | CONFIG_HID_A4TECH=m | ||
996 | CONFIG_HID_APPLE=m | ||
997 | CONFIG_HID_BELKIN=m | ||
998 | CONFIG_HID_BRIGHT=m | ||
999 | CONFIG_HID_CHERRY=m | ||
1000 | CONFIG_HID_CHICONY=m | ||
1001 | CONFIG_HID_CYPRESS=m | ||
1002 | CONFIG_HID_DELL=m | ||
1003 | CONFIG_HID_EZKEY=m | ||
1004 | CONFIG_HID_GYRATION=m | ||
1005 | CONFIG_HID_LOGITECH=m | ||
1006 | # CONFIG_LOGITECH_FF is not set | ||
1007 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
1008 | CONFIG_HID_MICROSOFT=m | ||
1009 | CONFIG_HID_MONTEREY=m | ||
1010 | CONFIG_HID_PANTHERLORD=m | ||
1011 | # CONFIG_PANTHERLORD_FF is not set | ||
1012 | CONFIG_HID_PETALYNX=m | ||
1013 | CONFIG_HID_SAMSUNG=m | ||
1014 | CONFIG_HID_SONY=m | ||
1015 | CONFIG_HID_SUNPLUS=m | ||
1016 | # CONFIG_THRUSTMASTER_FF is not set | ||
1017 | # CONFIG_ZEROPLUS_FF is not set | ||
1018 | CONFIG_USB_SUPPORT=y | ||
1019 | CONFIG_USB_ARCH_HAS_HCD=y | ||
1020 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
1021 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
1022 | CONFIG_USB=y | ||
1023 | # CONFIG_USB_DEBUG is not set | ||
1024 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
1025 | |||
1026 | # | ||
1027 | # Miscellaneous USB options | ||
1028 | # | ||
1029 | CONFIG_USB_DEVICEFS=y | ||
1030 | # CONFIG_USB_DEVICE_CLASS is not set | ||
1031 | CONFIG_USB_DYNAMIC_MINORS=y | ||
1032 | # CONFIG_USB_OTG is not set | ||
1033 | # CONFIG_USB_OTG_WHITELIST is not set | ||
1034 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
1035 | CONFIG_USB_MON=y | ||
1036 | # CONFIG_USB_WUSB is not set | ||
1037 | # CONFIG_USB_WUSB_CBAF is not set | ||
1038 | |||
1039 | # | ||
1040 | # USB Host Controller Drivers | ||
1041 | # | ||
1042 | # CONFIG_USB_C67X00_HCD is not set | ||
1043 | # CONFIG_USB_ISP116X_HCD is not set | ||
1044 | CONFIG_USB_OHCI_HCD=y | ||
1045 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
1046 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
1047 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
1048 | # CONFIG_USB_SL811_HCD is not set | ||
1049 | # CONFIG_USB_R8A66597_HCD is not set | ||
1050 | # CONFIG_USB_HWA_HCD is not set | ||
1051 | # CONFIG_USB_MUSB_HDRC is not set | ||
1052 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
1053 | |||
1054 | # | ||
1055 | # USB Device Class drivers | ||
1056 | # | ||
1057 | # CONFIG_USB_ACM is not set | ||
1058 | # CONFIG_USB_PRINTER is not set | ||
1059 | # CONFIG_USB_WDM is not set | ||
1060 | # CONFIG_USB_TMC is not set | ||
1061 | |||
1062 | # | ||
1063 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
1064 | # | ||
1065 | |||
1066 | # | ||
1067 | # see USB_STORAGE Help for more information | ||
1068 | # | ||
1069 | CONFIG_USB_STORAGE=m | ||
1070 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
1071 | CONFIG_USB_STORAGE_DATAFAB=y | ||
1072 | CONFIG_USB_STORAGE_FREECOM=y | ||
1073 | CONFIG_USB_STORAGE_ISD200=y | ||
1074 | CONFIG_USB_STORAGE_DPCM=y | ||
1075 | CONFIG_USB_STORAGE_USBAT=y | ||
1076 | CONFIG_USB_STORAGE_SDDR09=y | ||
1077 | CONFIG_USB_STORAGE_SDDR55=y | ||
1078 | CONFIG_USB_STORAGE_JUMPSHOT=y | ||
1079 | CONFIG_USB_STORAGE_ALAUDA=y | ||
1080 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
1081 | CONFIG_USB_STORAGE_KARMA=y | ||
1082 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
1083 | CONFIG_USB_LIBUSUAL=y | ||
1084 | |||
1085 | # | ||
1086 | # USB Imaging devices | ||
1087 | # | ||
1088 | # CONFIG_USB_MDC800 is not set | ||
1089 | # CONFIG_USB_MICROTEK is not set | ||
1090 | |||
1091 | # | ||
1092 | # USB port drivers | ||
1093 | # | ||
1094 | CONFIG_USB_SERIAL=m | ||
1095 | CONFIG_USB_EZUSB=y | ||
1096 | CONFIG_USB_SERIAL_GENERIC=y | ||
1097 | # CONFIG_USB_SERIAL_AIRCABLE is not set | ||
1098 | # CONFIG_USB_SERIAL_ARK3116 is not set | ||
1099 | # CONFIG_USB_SERIAL_BELKIN is not set | ||
1100 | # CONFIG_USB_SERIAL_CH341 is not set | ||
1101 | # CONFIG_USB_SERIAL_WHITEHEAT is not set | ||
1102 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | ||
1103 | # CONFIG_USB_SERIAL_CP2101 is not set | ||
1104 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set | ||
1105 | # CONFIG_USB_SERIAL_EMPEG is not set | ||
1106 | # CONFIG_USB_SERIAL_FTDI_SIO is not set | ||
1107 | # CONFIG_USB_SERIAL_FUNSOFT is not set | ||
1108 | # CONFIG_USB_SERIAL_VISOR is not set | ||
1109 | # CONFIG_USB_SERIAL_IPAQ is not set | ||
1110 | # CONFIG_USB_SERIAL_IR is not set | ||
1111 | # CONFIG_USB_SERIAL_EDGEPORT is not set | ||
1112 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set | ||
1113 | # CONFIG_USB_SERIAL_GARMIN is not set | ||
1114 | # CONFIG_USB_SERIAL_IPW is not set | ||
1115 | # CONFIG_USB_SERIAL_IUU is not set | ||
1116 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | ||
1117 | # CONFIG_USB_SERIAL_KEYSPAN is not set | ||
1118 | # CONFIG_USB_SERIAL_KLSI is not set | ||
1119 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set | ||
1120 | # CONFIG_USB_SERIAL_MCT_U232 is not set | ||
1121 | # CONFIG_USB_SERIAL_MOS7720 is not set | ||
1122 | # CONFIG_USB_SERIAL_MOS7840 is not set | ||
1123 | # CONFIG_USB_SERIAL_MOTOROLA is not set | ||
1124 | # CONFIG_USB_SERIAL_NAVMAN is not set | ||
1125 | CONFIG_USB_SERIAL_PL2303=m | ||
1126 | # CONFIG_USB_SERIAL_OTI6858 is not set | ||
1127 | CONFIG_USB_SERIAL_SPCP8X5=m | ||
1128 | # CONFIG_USB_SERIAL_HP4X is not set | ||
1129 | # CONFIG_USB_SERIAL_SAFE is not set | ||
1130 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | ||
1131 | # CONFIG_USB_SERIAL_TI is not set | ||
1132 | # CONFIG_USB_SERIAL_CYBERJACK is not set | ||
1133 | # CONFIG_USB_SERIAL_XIRCOM is not set | ||
1134 | # CONFIG_USB_SERIAL_OPTION is not set | ||
1135 | # CONFIG_USB_SERIAL_OMNINET is not set | ||
1136 | CONFIG_USB_SERIAL_DEBUG=m | ||
1137 | |||
1138 | # | ||
1139 | # USB Miscellaneous drivers | ||
1140 | # | ||
1141 | CONFIG_USB_EMI62=m | ||
1142 | CONFIG_USB_EMI26=m | ||
1143 | CONFIG_USB_ADUTUX=m | ||
1144 | # CONFIG_USB_SEVSEG is not set | ||
1145 | # CONFIG_USB_RIO500 is not set | ||
1146 | # CONFIG_USB_LEGOTOWER is not set | ||
1147 | # CONFIG_USB_LCD is not set | ||
1148 | # CONFIG_USB_BERRY_CHARGE is not set | ||
1149 | # CONFIG_USB_LED is not set | ||
1150 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
1151 | # CONFIG_USB_CYTHERM is not set | ||
1152 | # CONFIG_USB_PHIDGET is not set | ||
1153 | # CONFIG_USB_IDMOUSE is not set | ||
1154 | # CONFIG_USB_FTDI_ELAN is not set | ||
1155 | # CONFIG_USB_APPLEDISPLAY is not set | ||
1156 | # CONFIG_USB_LD is not set | ||
1157 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
1158 | # CONFIG_USB_IOWARRIOR is not set | ||
1159 | CONFIG_USB_TEST=m | ||
1160 | # CONFIG_USB_ISIGHTFW is not set | ||
1161 | # CONFIG_USB_VST is not set | ||
1162 | CONFIG_USB_GADGET=m | ||
1163 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
1164 | CONFIG_USB_GADGET_DEBUG_FS=y | ||
1165 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
1166 | CONFIG_USB_GADGET_SELECTED=y | ||
1167 | CONFIG_USB_GADGET_AT91=y | ||
1168 | CONFIG_USB_AT91=m | ||
1169 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
1170 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
1171 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
1172 | # CONFIG_USB_GADGET_OMAP is not set | ||
1173 | # CONFIG_USB_GADGET_PXA25X is not set | ||
1174 | # CONFIG_USB_GADGET_PXA27X is not set | ||
1175 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
1176 | # CONFIG_USB_GADGET_M66592 is not set | ||
1177 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
1178 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
1179 | # CONFIG_USB_GADGET_NET2280 is not set | ||
1180 | # CONFIG_USB_GADGET_GOKU is not set | ||
1181 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
1182 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
1183 | CONFIG_USB_ZERO=m | ||
1184 | CONFIG_USB_ETH=m | ||
1185 | CONFIG_USB_ETH_RNDIS=y | ||
1186 | CONFIG_USB_GADGETFS=m | ||
1187 | CONFIG_USB_FILE_STORAGE=m | ||
1188 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
1189 | CONFIG_USB_G_SERIAL=m | ||
1190 | CONFIG_USB_MIDI_GADGET=m | ||
1191 | # CONFIG_USB_G_PRINTER is not set | ||
1192 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
1193 | CONFIG_MMC=y | ||
1194 | # CONFIG_MMC_DEBUG is not set | ||
1195 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
1196 | |||
1197 | # | ||
1198 | # MMC/SD/SDIO Card Drivers | ||
1199 | # | ||
1200 | CONFIG_MMC_BLOCK=y | ||
1201 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
1202 | CONFIG_SDIO_UART=m | ||
1203 | # CONFIG_MMC_TEST is not set | ||
1204 | |||
1205 | # | ||
1206 | # MMC/SD/SDIO Host Controller Drivers | ||
1207 | # | ||
1208 | # CONFIG_MMC_SDHCI is not set | ||
1209 | CONFIG_MMC_AT91=y | ||
1210 | CONFIG_MMC_SPI=m | ||
1211 | # CONFIG_MEMSTICK is not set | ||
1212 | # CONFIG_ACCESSIBILITY is not set | ||
1213 | CONFIG_NEW_LEDS=y | ||
1214 | CONFIG_LEDS_CLASS=m | ||
1215 | |||
1216 | # | ||
1217 | # LED drivers | ||
1218 | # | ||
1219 | # CONFIG_LEDS_PCA9532 is not set | ||
1220 | CONFIG_LEDS_GPIO=m | ||
1221 | # CONFIG_LEDS_PCA955X is not set | ||
1222 | |||
1223 | # | ||
1224 | # LED Triggers | ||
1225 | # | ||
1226 | CONFIG_LEDS_TRIGGERS=y | ||
1227 | CONFIG_LEDS_TRIGGER_TIMER=m | ||
1228 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m | ||
1229 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
1230 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
1231 | CONFIG_RTC_LIB=y | ||
1232 | CONFIG_RTC_CLASS=y | ||
1233 | CONFIG_RTC_HCTOSYS=y | ||
1234 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
1235 | # CONFIG_RTC_DEBUG is not set | ||
1236 | |||
1237 | # | ||
1238 | # RTC interfaces | ||
1239 | # | ||
1240 | CONFIG_RTC_INTF_SYSFS=y | ||
1241 | CONFIG_RTC_INTF_PROC=y | ||
1242 | CONFIG_RTC_INTF_DEV=y | ||
1243 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | ||
1244 | # CONFIG_RTC_DRV_TEST is not set | ||
1245 | |||
1246 | # | ||
1247 | # I2C RTC drivers | ||
1248 | # | ||
1249 | CONFIG_RTC_DRV_DS1307=m | ||
1250 | # CONFIG_RTC_DRV_DS1374 is not set | ||
1251 | # CONFIG_RTC_DRV_DS1672 is not set | ||
1252 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
1253 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
1254 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
1255 | # CONFIG_RTC_DRV_X1205 is not set | ||
1256 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
1257 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
1258 | # CONFIG_RTC_DRV_M41T80 is not set | ||
1259 | # CONFIG_RTC_DRV_S35390A is not set | ||
1260 | # CONFIG_RTC_DRV_FM3130 is not set | ||
1261 | # CONFIG_RTC_DRV_RX8581 is not set | ||
1262 | |||
1263 | # | ||
1264 | # SPI RTC drivers | ||
1265 | # | ||
1266 | # CONFIG_RTC_DRV_M41T94 is not set | ||
1267 | CONFIG_RTC_DRV_DS1305=y | ||
1268 | # CONFIG_RTC_DRV_DS1390 is not set | ||
1269 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
1270 | # CONFIG_RTC_DRV_R9701 is not set | ||
1271 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
1272 | # CONFIG_RTC_DRV_DS3234 is not set | ||
1273 | |||
1274 | # | ||
1275 | # Platform RTC drivers | ||
1276 | # | ||
1277 | # CONFIG_RTC_DRV_CMOS is not set | ||
1278 | # CONFIG_RTC_DRV_DS1286 is not set | ||
1279 | # CONFIG_RTC_DRV_DS1511 is not set | ||
1280 | # CONFIG_RTC_DRV_DS1553 is not set | ||
1281 | # CONFIG_RTC_DRV_DS1742 is not set | ||
1282 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
1283 | # CONFIG_RTC_DRV_M48T86 is not set | ||
1284 | # CONFIG_RTC_DRV_M48T35 is not set | ||
1285 | # CONFIG_RTC_DRV_M48T59 is not set | ||
1286 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
1287 | # CONFIG_RTC_DRV_V3020 is not set | ||
1288 | |||
1289 | # | ||
1290 | # on-CPU RTC drivers | ||
1291 | # | ||
1292 | # CONFIG_RTC_DRV_AT91SAM9 is not set | ||
1293 | # CONFIG_DMADEVICES is not set | ||
1294 | # CONFIG_REGULATOR is not set | ||
1295 | # CONFIG_UIO is not set | ||
1296 | |||
1297 | # | ||
1298 | # File systems | ||
1299 | # | ||
1300 | CONFIG_EXT2_FS=y | ||
1301 | CONFIG_EXT2_FS_XATTR=y | ||
1302 | CONFIG_EXT2_FS_POSIX_ACL=y | ||
1303 | CONFIG_EXT2_FS_SECURITY=y | ||
1304 | # CONFIG_EXT2_FS_XIP is not set | ||
1305 | CONFIG_EXT3_FS=y | ||
1306 | CONFIG_EXT3_FS_XATTR=y | ||
1307 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
1308 | CONFIG_EXT3_FS_SECURITY=y | ||
1309 | # CONFIG_EXT4_FS is not set | ||
1310 | CONFIG_JBD=y | ||
1311 | CONFIG_JBD_DEBUG=y | ||
1312 | CONFIG_FS_MBCACHE=y | ||
1313 | CONFIG_REISERFS_FS=m | ||
1314 | CONFIG_REISERFS_CHECK=y | ||
1315 | CONFIG_REISERFS_PROC_INFO=y | ||
1316 | CONFIG_REISERFS_FS_XATTR=y | ||
1317 | CONFIG_REISERFS_FS_POSIX_ACL=y | ||
1318 | CONFIG_REISERFS_FS_SECURITY=y | ||
1319 | # CONFIG_JFS_FS is not set | ||
1320 | CONFIG_FS_POSIX_ACL=y | ||
1321 | CONFIG_FILE_LOCKING=y | ||
1322 | # CONFIG_XFS_FS is not set | ||
1323 | # CONFIG_OCFS2_FS is not set | ||
1324 | CONFIG_DNOTIFY=y | ||
1325 | CONFIG_INOTIFY=y | ||
1326 | CONFIG_INOTIFY_USER=y | ||
1327 | # CONFIG_QUOTA is not set | ||
1328 | # CONFIG_AUTOFS_FS is not set | ||
1329 | # CONFIG_AUTOFS4_FS is not set | ||
1330 | CONFIG_FUSE_FS=m | ||
1331 | CONFIG_GENERIC_ACL=y | ||
1332 | |||
1333 | # | ||
1334 | # CD-ROM/DVD Filesystems | ||
1335 | # | ||
1336 | # CONFIG_ISO9660_FS is not set | ||
1337 | # CONFIG_UDF_FS is not set | ||
1338 | |||
1339 | # | ||
1340 | # DOS/FAT/NT Filesystems | ||
1341 | # | ||
1342 | CONFIG_FAT_FS=y | ||
1343 | CONFIG_MSDOS_FS=m | ||
1344 | CONFIG_VFAT_FS=y | ||
1345 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
1346 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
1347 | CONFIG_NTFS_FS=m | ||
1348 | # CONFIG_NTFS_DEBUG is not set | ||
1349 | CONFIG_NTFS_RW=y | ||
1350 | |||
1351 | # | ||
1352 | # Pseudo filesystems | ||
1353 | # | ||
1354 | CONFIG_PROC_FS=y | ||
1355 | CONFIG_PROC_SYSCTL=y | ||
1356 | CONFIG_PROC_PAGE_MONITOR=y | ||
1357 | CONFIG_SYSFS=y | ||
1358 | CONFIG_TMPFS=y | ||
1359 | CONFIG_TMPFS_POSIX_ACL=y | ||
1360 | # CONFIG_HUGETLB_PAGE is not set | ||
1361 | CONFIG_CONFIGFS_FS=m | ||
1362 | |||
1363 | # | ||
1364 | # Miscellaneous filesystems | ||
1365 | # | ||
1366 | # CONFIG_ADFS_FS is not set | ||
1367 | # CONFIG_AFFS_FS is not set | ||
1368 | # CONFIG_HFS_FS is not set | ||
1369 | # CONFIG_HFSPLUS_FS is not set | ||
1370 | # CONFIG_BEFS_FS is not set | ||
1371 | # CONFIG_BFS_FS is not set | ||
1372 | # CONFIG_EFS_FS is not set | ||
1373 | CONFIG_JFFS2_FS=m | ||
1374 | CONFIG_JFFS2_FS_DEBUG=0 | ||
1375 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
1376 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
1377 | # CONFIG_JFFS2_SUMMARY is not set | ||
1378 | # CONFIG_JFFS2_FS_XATTR is not set | ||
1379 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
1380 | CONFIG_JFFS2_ZLIB=y | ||
1381 | CONFIG_JFFS2_LZO=y | ||
1382 | CONFIG_JFFS2_RTIME=y | ||
1383 | # CONFIG_JFFS2_RUBIN is not set | ||
1384 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
1385 | # CONFIG_JFFS2_CMODE_PRIORITY is not set | ||
1386 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
1387 | CONFIG_JFFS2_CMODE_FAVOURLZO=y | ||
1388 | # CONFIG_UBIFS_FS is not set | ||
1389 | CONFIG_CRAMFS=m | ||
1390 | # CONFIG_VXFS_FS is not set | ||
1391 | # CONFIG_MINIX_FS is not set | ||
1392 | # CONFIG_OMFS_FS is not set | ||
1393 | # CONFIG_HPFS_FS is not set | ||
1394 | # CONFIG_QNX4FS_FS is not set | ||
1395 | # CONFIG_ROMFS_FS is not set | ||
1396 | # CONFIG_SYSV_FS is not set | ||
1397 | # CONFIG_UFS_FS is not set | ||
1398 | CONFIG_NETWORK_FILESYSTEMS=y | ||
1399 | CONFIG_NFS_FS=m | ||
1400 | CONFIG_NFS_V3=y | ||
1401 | CONFIG_NFS_V3_ACL=y | ||
1402 | CONFIG_NFS_V4=y | ||
1403 | CONFIG_NFSD=m | ||
1404 | CONFIG_NFSD_V2_ACL=y | ||
1405 | CONFIG_NFSD_V3=y | ||
1406 | CONFIG_NFSD_V3_ACL=y | ||
1407 | CONFIG_NFSD_V4=y | ||
1408 | CONFIG_LOCKD=m | ||
1409 | CONFIG_LOCKD_V4=y | ||
1410 | CONFIG_EXPORTFS=m | ||
1411 | CONFIG_NFS_ACL_SUPPORT=m | ||
1412 | CONFIG_NFS_COMMON=y | ||
1413 | CONFIG_SUNRPC=m | ||
1414 | CONFIG_SUNRPC_GSS=m | ||
1415 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
1416 | CONFIG_RPCSEC_GSS_KRB5=m | ||
1417 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
1418 | # CONFIG_SMB_FS is not set | ||
1419 | CONFIG_CIFS=m | ||
1420 | # CONFIG_CIFS_STATS is not set | ||
1421 | CONFIG_CIFS_WEAK_PW_HASH=y | ||
1422 | # CONFIG_CIFS_XATTR is not set | ||
1423 | # CONFIG_CIFS_DEBUG2 is not set | ||
1424 | # CONFIG_CIFS_EXPERIMENTAL is not set | ||
1425 | # CONFIG_NCP_FS is not set | ||
1426 | # CONFIG_CODA_FS is not set | ||
1427 | # CONFIG_AFS_FS is not set | ||
1428 | |||
1429 | # | ||
1430 | # Partition Types | ||
1431 | # | ||
1432 | CONFIG_PARTITION_ADVANCED=y | ||
1433 | # CONFIG_ACORN_PARTITION is not set | ||
1434 | # CONFIG_OSF_PARTITION is not set | ||
1435 | # CONFIG_AMIGA_PARTITION is not set | ||
1436 | # CONFIG_ATARI_PARTITION is not set | ||
1437 | CONFIG_MAC_PARTITION=y | ||
1438 | CONFIG_MSDOS_PARTITION=y | ||
1439 | CONFIG_BSD_DISKLABEL=y | ||
1440 | CONFIG_MINIX_SUBPARTITION=y | ||
1441 | CONFIG_SOLARIS_X86_PARTITION=y | ||
1442 | CONFIG_UNIXWARE_DISKLABEL=y | ||
1443 | CONFIG_LDM_PARTITION=y | ||
1444 | CONFIG_LDM_DEBUG=y | ||
1445 | CONFIG_SGI_PARTITION=y | ||
1446 | # CONFIG_ULTRIX_PARTITION is not set | ||
1447 | CONFIG_SUN_PARTITION=y | ||
1448 | # CONFIG_KARMA_PARTITION is not set | ||
1449 | # CONFIG_EFI_PARTITION is not set | ||
1450 | # CONFIG_SYSV68_PARTITION is not set | ||
1451 | CONFIG_NLS=y | ||
1452 | CONFIG_NLS_DEFAULT="cp437" | ||
1453 | CONFIG_NLS_CODEPAGE_437=y | ||
1454 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
1455 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
1456 | CONFIG_NLS_CODEPAGE_850=m | ||
1457 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
1458 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
1459 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
1460 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
1461 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
1462 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
1463 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
1464 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
1465 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
1466 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
1467 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
1468 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
1469 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
1470 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
1471 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
1472 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
1473 | # CONFIG_NLS_ISO8859_8 is not set | ||
1474 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
1475 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
1476 | CONFIG_NLS_ASCII=y | ||
1477 | CONFIG_NLS_ISO8859_1=y | ||
1478 | # CONFIG_NLS_ISO8859_2 is not set | ||
1479 | # CONFIG_NLS_ISO8859_3 is not set | ||
1480 | # CONFIG_NLS_ISO8859_4 is not set | ||
1481 | # CONFIG_NLS_ISO8859_5 is not set | ||
1482 | # CONFIG_NLS_ISO8859_6 is not set | ||
1483 | # CONFIG_NLS_ISO8859_7 is not set | ||
1484 | # CONFIG_NLS_ISO8859_9 is not set | ||
1485 | # CONFIG_NLS_ISO8859_13 is not set | ||
1486 | # CONFIG_NLS_ISO8859_14 is not set | ||
1487 | # CONFIG_NLS_ISO8859_15 is not set | ||
1488 | # CONFIG_NLS_KOI8_R is not set | ||
1489 | # CONFIG_NLS_KOI8_U is not set | ||
1490 | CONFIG_NLS_UTF8=m | ||
1491 | CONFIG_DLM=m | ||
1492 | # CONFIG_DLM_DEBUG is not set | ||
1493 | |||
1494 | # | ||
1495 | # Kernel hacking | ||
1496 | # | ||
1497 | CONFIG_PRINTK_TIME=y | ||
1498 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
1499 | CONFIG_ENABLE_MUST_CHECK=y | ||
1500 | CONFIG_FRAME_WARN=1024 | ||
1501 | CONFIG_MAGIC_SYSRQ=y | ||
1502 | CONFIG_UNUSED_SYMBOLS=y | ||
1503 | CONFIG_DEBUG_FS=y | ||
1504 | # CONFIG_HEADERS_CHECK is not set | ||
1505 | # CONFIG_DEBUG_KERNEL is not set | ||
1506 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
1507 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
1508 | CONFIG_FRAME_POINTER=y | ||
1509 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
1510 | # CONFIG_LATENCYTOP is not set | ||
1511 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
1512 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
1513 | |||
1514 | # | ||
1515 | # Tracers | ||
1516 | # | ||
1517 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
1518 | # CONFIG_SAMPLES is not set | ||
1519 | CONFIG_HAVE_ARCH_KGDB=y | ||
1520 | # CONFIG_DEBUG_USER is not set | ||
1521 | |||
1522 | # | ||
1523 | # Security options | ||
1524 | # | ||
1525 | # CONFIG_KEYS is not set | ||
1526 | # CONFIG_SECURITY is not set | ||
1527 | CONFIG_SECURITYFS=y | ||
1528 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
1529 | CONFIG_CRYPTO=y | ||
1530 | |||
1531 | # | ||
1532 | # Crypto core or helper | ||
1533 | # | ||
1534 | # CONFIG_CRYPTO_FIPS is not set | ||
1535 | CONFIG_CRYPTO_ALGAPI=y | ||
1536 | CONFIG_CRYPTO_AEAD=y | ||
1537 | CONFIG_CRYPTO_BLKCIPHER=y | ||
1538 | CONFIG_CRYPTO_HASH=y | ||
1539 | CONFIG_CRYPTO_RNG=y | ||
1540 | CONFIG_CRYPTO_MANAGER=y | ||
1541 | CONFIG_CRYPTO_GF128MUL=m | ||
1542 | # CONFIG_CRYPTO_NULL is not set | ||
1543 | # CONFIG_CRYPTO_CRYPTD is not set | ||
1544 | # CONFIG_CRYPTO_AUTHENC is not set | ||
1545 | # CONFIG_CRYPTO_TEST is not set | ||
1546 | |||
1547 | # | ||
1548 | # Authenticated Encryption with Associated Data | ||
1549 | # | ||
1550 | # CONFIG_CRYPTO_CCM is not set | ||
1551 | # CONFIG_CRYPTO_GCM is not set | ||
1552 | # CONFIG_CRYPTO_SEQIV is not set | ||
1553 | |||
1554 | # | ||
1555 | # Block modes | ||
1556 | # | ||
1557 | CONFIG_CRYPTO_CBC=m | ||
1558 | # CONFIG_CRYPTO_CTR is not set | ||
1559 | # CONFIG_CRYPTO_CTS is not set | ||
1560 | CONFIG_CRYPTO_ECB=m | ||
1561 | # CONFIG_CRYPTO_LRW is not set | ||
1562 | # CONFIG_CRYPTO_PCBC is not set | ||
1563 | # CONFIG_CRYPTO_XTS is not set | ||
1564 | |||
1565 | # | ||
1566 | # Hash modes | ||
1567 | # | ||
1568 | CONFIG_CRYPTO_HMAC=y | ||
1569 | # CONFIG_CRYPTO_XCBC is not set | ||
1570 | |||
1571 | # | ||
1572 | # Digest | ||
1573 | # | ||
1574 | # CONFIG_CRYPTO_CRC32C is not set | ||
1575 | # CONFIG_CRYPTO_MD4 is not set | ||
1576 | CONFIG_CRYPTO_MD5=y | ||
1577 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
1578 | # CONFIG_CRYPTO_RMD128 is not set | ||
1579 | # CONFIG_CRYPTO_RMD160 is not set | ||
1580 | # CONFIG_CRYPTO_RMD256 is not set | ||
1581 | # CONFIG_CRYPTO_RMD320 is not set | ||
1582 | CONFIG_CRYPTO_SHA1=m | ||
1583 | # CONFIG_CRYPTO_SHA256 is not set | ||
1584 | # CONFIG_CRYPTO_SHA512 is not set | ||
1585 | # CONFIG_CRYPTO_TGR192 is not set | ||
1586 | # CONFIG_CRYPTO_WP512 is not set | ||
1587 | |||
1588 | # | ||
1589 | # Ciphers | ||
1590 | # | ||
1591 | # CONFIG_CRYPTO_AES is not set | ||
1592 | # CONFIG_CRYPTO_ANUBIS is not set | ||
1593 | CONFIG_CRYPTO_ARC4=m | ||
1594 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
1595 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
1596 | # CONFIG_CRYPTO_CAST5 is not set | ||
1597 | # CONFIG_CRYPTO_CAST6 is not set | ||
1598 | CONFIG_CRYPTO_DES=m | ||
1599 | # CONFIG_CRYPTO_FCRYPT is not set | ||
1600 | # CONFIG_CRYPTO_KHAZAD is not set | ||
1601 | # CONFIG_CRYPTO_SALSA20 is not set | ||
1602 | # CONFIG_CRYPTO_SEED is not set | ||
1603 | # CONFIG_CRYPTO_SERPENT is not set | ||
1604 | # CONFIG_CRYPTO_TEA is not set | ||
1605 | # CONFIG_CRYPTO_TWOFISH is not set | ||
1606 | |||
1607 | # | ||
1608 | # Compression | ||
1609 | # | ||
1610 | # CONFIG_CRYPTO_DEFLATE is not set | ||
1611 | # CONFIG_CRYPTO_LZO is not set | ||
1612 | |||
1613 | # | ||
1614 | # Random Number Generation | ||
1615 | # | ||
1616 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
1617 | # CONFIG_CRYPTO_HW is not set | ||
1618 | |||
1619 | # | ||
1620 | # Library routines | ||
1621 | # | ||
1622 | CONFIG_BITREVERSE=y | ||
1623 | CONFIG_CRC_CCITT=m | ||
1624 | CONFIG_CRC16=m | ||
1625 | # CONFIG_CRC_T10DIF is not set | ||
1626 | CONFIG_CRC_ITU_T=m | ||
1627 | CONFIG_CRC32=y | ||
1628 | CONFIG_CRC7=m | ||
1629 | CONFIG_LIBCRC32C=m | ||
1630 | CONFIG_AUDIT_GENERIC=y | ||
1631 | CONFIG_ZLIB_INFLATE=m | ||
1632 | CONFIG_ZLIB_DEFLATE=m | ||
1633 | CONFIG_LZO_COMPRESS=m | ||
1634 | CONFIG_LZO_DECOMPRESS=m | ||
1635 | CONFIG_REED_SOLOMON=m | ||
1636 | CONFIG_REED_SOLOMON_DEC16=y | ||
1637 | CONFIG_PLIST=y | ||
1638 | CONFIG_HAS_IOMEM=y | ||
1639 | CONFIG_HAS_IOPORT=y | ||
1640 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index 3de640ac294b..c48d7b893869 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig | |||
@@ -242,10 +242,13 @@ CONFIG_CPU_CP15_MMU=y | |||
242 | # CONFIG_CPU_DCACHE_DISABLE is not set | 242 | # CONFIG_CPU_DCACHE_DISABLE is not set |
243 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 243 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
244 | CONFIG_HAS_TLS_REG=y | 244 | CONFIG_HAS_TLS_REG=y |
245 | CONFIG_OUTER_CACHE=y | ||
246 | CONFIG_CACHE_L2X0=y | ||
245 | CONFIG_ARM_L1_CACHE_SHIFT=5 | 247 | CONFIG_ARM_L1_CACHE_SHIFT=5 |
246 | # CONFIG_ARM_ERRATA_430973 is not set | 248 | # CONFIG_ARM_ERRATA_430973 is not set |
247 | # CONFIG_ARM_ERRATA_458693 is not set | 249 | # CONFIG_ARM_ERRATA_458693 is not set |
248 | # CONFIG_ARM_ERRATA_460075 is not set | 250 | # CONFIG_ARM_ERRATA_460075 is not set |
251 | CONFIG_PL310_ERRATA_588369=y | ||
249 | CONFIG_ARM_GIC=y | 252 | CONFIG_ARM_GIC=y |
250 | 253 | ||
251 | # | 254 | # |
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index d0daeab2234e..e8ddec2cb158 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h | |||
@@ -235,6 +235,234 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) | |||
235 | #define smp_mb__before_atomic_inc() smp_mb() | 235 | #define smp_mb__before_atomic_inc() smp_mb() |
236 | #define smp_mb__after_atomic_inc() smp_mb() | 236 | #define smp_mb__after_atomic_inc() smp_mb() |
237 | 237 | ||
238 | #ifndef CONFIG_GENERIC_ATOMIC64 | ||
239 | typedef struct { | ||
240 | u64 __aligned(8) counter; | ||
241 | } atomic64_t; | ||
242 | |||
243 | #define ATOMIC64_INIT(i) { (i) } | ||
244 | |||
245 | static inline u64 atomic64_read(atomic64_t *v) | ||
246 | { | ||
247 | u64 result; | ||
248 | |||
249 | __asm__ __volatile__("@ atomic64_read\n" | ||
250 | " ldrexd %0, %H0, [%1]" | ||
251 | : "=&r" (result) | ||
252 | : "r" (&v->counter) | ||
253 | ); | ||
254 | |||
255 | return result; | ||
256 | } | ||
257 | |||
258 | static inline void atomic64_set(atomic64_t *v, u64 i) | ||
259 | { | ||
260 | u64 tmp; | ||
261 | |||
262 | __asm__ __volatile__("@ atomic64_set\n" | ||
263 | "1: ldrexd %0, %H0, [%1]\n" | ||
264 | " strexd %0, %2, %H2, [%1]\n" | ||
265 | " teq %0, #0\n" | ||
266 | " bne 1b" | ||
267 | : "=&r" (tmp) | ||
268 | : "r" (&v->counter), "r" (i) | ||
269 | : "cc"); | ||
270 | } | ||
271 | |||
272 | static inline void atomic64_add(u64 i, atomic64_t *v) | ||
273 | { | ||
274 | u64 result; | ||
275 | unsigned long tmp; | ||
276 | |||
277 | __asm__ __volatile__("@ atomic64_add\n" | ||
278 | "1: ldrexd %0, %H0, [%2]\n" | ||
279 | " adds %0, %0, %3\n" | ||
280 | " adc %H0, %H0, %H3\n" | ||
281 | " strexd %1, %0, %H0, [%2]\n" | ||
282 | " teq %1, #0\n" | ||
283 | " bne 1b" | ||
284 | : "=&r" (result), "=&r" (tmp) | ||
285 | : "r" (&v->counter), "r" (i) | ||
286 | : "cc"); | ||
287 | } | ||
288 | |||
289 | static inline u64 atomic64_add_return(u64 i, atomic64_t *v) | ||
290 | { | ||
291 | u64 result; | ||
292 | unsigned long tmp; | ||
293 | |||
294 | smp_mb(); | ||
295 | |||
296 | __asm__ __volatile__("@ atomic64_add_return\n" | ||
297 | "1: ldrexd %0, %H0, [%2]\n" | ||
298 | " adds %0, %0, %3\n" | ||
299 | " adc %H0, %H0, %H3\n" | ||
300 | " strexd %1, %0, %H0, [%2]\n" | ||
301 | " teq %1, #0\n" | ||
302 | " bne 1b" | ||
303 | : "=&r" (result), "=&r" (tmp) | ||
304 | : "r" (&v->counter), "r" (i) | ||
305 | : "cc"); | ||
306 | |||
307 | smp_mb(); | ||
308 | |||
309 | return result; | ||
310 | } | ||
311 | |||
312 | static inline void atomic64_sub(u64 i, atomic64_t *v) | ||
313 | { | ||
314 | u64 result; | ||
315 | unsigned long tmp; | ||
316 | |||
317 | __asm__ __volatile__("@ atomic64_sub\n" | ||
318 | "1: ldrexd %0, %H0, [%2]\n" | ||
319 | " subs %0, %0, %3\n" | ||
320 | " sbc %H0, %H0, %H3\n" | ||
321 | " strexd %1, %0, %H0, [%2]\n" | ||
322 | " teq %1, #0\n" | ||
323 | " bne 1b" | ||
324 | : "=&r" (result), "=&r" (tmp) | ||
325 | : "r" (&v->counter), "r" (i) | ||
326 | : "cc"); | ||
327 | } | ||
328 | |||
329 | static inline u64 atomic64_sub_return(u64 i, atomic64_t *v) | ||
330 | { | ||
331 | u64 result; | ||
332 | unsigned long tmp; | ||
333 | |||
334 | smp_mb(); | ||
335 | |||
336 | __asm__ __volatile__("@ atomic64_sub_return\n" | ||
337 | "1: ldrexd %0, %H0, [%2]\n" | ||
338 | " subs %0, %0, %3\n" | ||
339 | " sbc %H0, %H0, %H3\n" | ||
340 | " strexd %1, %0, %H0, [%2]\n" | ||
341 | " teq %1, #0\n" | ||
342 | " bne 1b" | ||
343 | : "=&r" (result), "=&r" (tmp) | ||
344 | : "r" (&v->counter), "r" (i) | ||
345 | : "cc"); | ||
346 | |||
347 | smp_mb(); | ||
348 | |||
349 | return result; | ||
350 | } | ||
351 | |||
352 | static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new) | ||
353 | { | ||
354 | u64 oldval; | ||
355 | unsigned long res; | ||
356 | |||
357 | smp_mb(); | ||
358 | |||
359 | do { | ||
360 | __asm__ __volatile__("@ atomic64_cmpxchg\n" | ||
361 | "ldrexd %1, %H1, [%2]\n" | ||
362 | "mov %0, #0\n" | ||
363 | "teq %1, %3\n" | ||
364 | "teqeq %H1, %H3\n" | ||
365 | "strexdeq %0, %4, %H4, [%2]" | ||
366 | : "=&r" (res), "=&r" (oldval) | ||
367 | : "r" (&ptr->counter), "r" (old), "r" (new) | ||
368 | : "cc"); | ||
369 | } while (res); | ||
370 | |||
371 | smp_mb(); | ||
372 | |||
373 | return oldval; | ||
374 | } | ||
375 | |||
376 | static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new) | ||
377 | { | ||
378 | u64 result; | ||
379 | unsigned long tmp; | ||
380 | |||
381 | smp_mb(); | ||
382 | |||
383 | __asm__ __volatile__("@ atomic64_xchg\n" | ||
384 | "1: ldrexd %0, %H0, [%2]\n" | ||
385 | " strexd %1, %3, %H3, [%2]\n" | ||
386 | " teq %1, #0\n" | ||
387 | " bne 1b" | ||
388 | : "=&r" (result), "=&r" (tmp) | ||
389 | : "r" (&ptr->counter), "r" (new) | ||
390 | : "cc"); | ||
391 | |||
392 | smp_mb(); | ||
393 | |||
394 | return result; | ||
395 | } | ||
396 | |||
397 | static inline u64 atomic64_dec_if_positive(atomic64_t *v) | ||
398 | { | ||
399 | u64 result; | ||
400 | unsigned long tmp; | ||
401 | |||
402 | smp_mb(); | ||
403 | |||
404 | __asm__ __volatile__("@ atomic64_dec_if_positive\n" | ||
405 | "1: ldrexd %0, %H0, [%2]\n" | ||
406 | " subs %0, %0, #1\n" | ||
407 | " sbc %H0, %H0, #0\n" | ||
408 | " teq %H0, #0\n" | ||
409 | " bmi 2f\n" | ||
410 | " strexd %1, %0, %H0, [%2]\n" | ||
411 | " teq %1, #0\n" | ||
412 | " bne 1b\n" | ||
413 | "2:" | ||
414 | : "=&r" (result), "=&r" (tmp) | ||
415 | : "r" (&v->counter) | ||
416 | : "cc"); | ||
417 | |||
418 | smp_mb(); | ||
419 | |||
420 | return result; | ||
421 | } | ||
422 | |||
423 | static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u) | ||
424 | { | ||
425 | u64 val; | ||
426 | unsigned long tmp; | ||
427 | int ret = 1; | ||
428 | |||
429 | smp_mb(); | ||
430 | |||
431 | __asm__ __volatile__("@ atomic64_add_unless\n" | ||
432 | "1: ldrexd %0, %H0, [%3]\n" | ||
433 | " teq %0, %4\n" | ||
434 | " teqeq %H0, %H4\n" | ||
435 | " moveq %1, #0\n" | ||
436 | " beq 2f\n" | ||
437 | " adds %0, %0, %5\n" | ||
438 | " adc %H0, %H0, %H5\n" | ||
439 | " strexd %2, %0, %H0, [%3]\n" | ||
440 | " teq %2, #0\n" | ||
441 | " bne 1b\n" | ||
442 | "2:" | ||
443 | : "=&r" (val), "=&r" (ret), "=&r" (tmp) | ||
444 | : "r" (&v->counter), "r" (u), "r" (a) | ||
445 | : "cc"); | ||
446 | |||
447 | if (ret) | ||
448 | smp_mb(); | ||
449 | |||
450 | return ret; | ||
451 | } | ||
452 | |||
453 | #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0) | ||
454 | #define atomic64_inc(v) atomic64_add(1LL, (v)) | ||
455 | #define atomic64_inc_return(v) atomic64_add_return(1LL, (v)) | ||
456 | #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0) | ||
457 | #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0) | ||
458 | #define atomic64_dec(v) atomic64_sub(1LL, (v)) | ||
459 | #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v)) | ||
460 | #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) | ||
461 | #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) | ||
462 | |||
463 | #else /* !CONFIG_GENERIC_ATOMIC64 */ | ||
464 | #include <asm-generic/atomic64.h> | ||
465 | #endif | ||
238 | #include <asm-generic/atomic-long.h> | 466 | #include <asm-generic/atomic-long.h> |
239 | #endif | 467 | #endif |
240 | #endif | 468 | #endif |
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index c77d2fa1f6e5..8148a009273a 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h | |||
@@ -196,21 +196,6 @@ | |||
196 | * DMA Cache Coherency | 196 | * DMA Cache Coherency |
197 | * =================== | 197 | * =================== |
198 | * | 198 | * |
199 | * dma_inv_range(start, end) | ||
200 | * | ||
201 | * Invalidate (discard) the specified virtual address range. | ||
202 | * May not write back any entries. If 'start' or 'end' | ||
203 | * are not cache line aligned, those lines must be written | ||
204 | * back. | ||
205 | * - start - virtual start address | ||
206 | * - end - virtual end address | ||
207 | * | ||
208 | * dma_clean_range(start, end) | ||
209 | * | ||
210 | * Clean (write back) the specified virtual address range. | ||
211 | * - start - virtual start address | ||
212 | * - end - virtual end address | ||
213 | * | ||
214 | * dma_flush_range(start, end) | 199 | * dma_flush_range(start, end) |
215 | * | 200 | * |
216 | * Clean and invalidate the specified virtual address range. | 201 | * Clean and invalidate the specified virtual address range. |
@@ -227,8 +212,9 @@ struct cpu_cache_fns { | |||
227 | void (*coherent_user_range)(unsigned long, unsigned long); | 212 | void (*coherent_user_range)(unsigned long, unsigned long); |
228 | void (*flush_kern_dcache_area)(void *, size_t); | 213 | void (*flush_kern_dcache_area)(void *, size_t); |
229 | 214 | ||
230 | void (*dma_inv_range)(const void *, const void *); | 215 | void (*dma_map_area)(const void *, size_t, int); |
231 | void (*dma_clean_range)(const void *, const void *); | 216 | void (*dma_unmap_area)(const void *, size_t, int); |
217 | |||
232 | void (*dma_flush_range)(const void *, const void *); | 218 | void (*dma_flush_range)(const void *, const void *); |
233 | }; | 219 | }; |
234 | 220 | ||
@@ -258,8 +244,8 @@ extern struct cpu_cache_fns cpu_cache; | |||
258 | * is visible to DMA, or data written by DMA to system memory is | 244 | * is visible to DMA, or data written by DMA to system memory is |
259 | * visible to the CPU. | 245 | * visible to the CPU. |
260 | */ | 246 | */ |
261 | #define dmac_inv_range cpu_cache.dma_inv_range | 247 | #define dmac_map_area cpu_cache.dma_map_area |
262 | #define dmac_clean_range cpu_cache.dma_clean_range | 248 | #define dmac_unmap_area cpu_cache.dma_unmap_area |
263 | #define dmac_flush_range cpu_cache.dma_flush_range | 249 | #define dmac_flush_range cpu_cache.dma_flush_range |
264 | 250 | ||
265 | #else | 251 | #else |
@@ -284,12 +270,12 @@ extern void __cpuc_flush_dcache_area(void *, size_t); | |||
284 | * is visible to DMA, or data written by DMA to system memory is | 270 | * is visible to DMA, or data written by DMA to system memory is |
285 | * visible to the CPU. | 271 | * visible to the CPU. |
286 | */ | 272 | */ |
287 | #define dmac_inv_range __glue(_CACHE,_dma_inv_range) | 273 | #define dmac_map_area __glue(_CACHE,_dma_map_area) |
288 | #define dmac_clean_range __glue(_CACHE,_dma_clean_range) | 274 | #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) |
289 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) | 275 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) |
290 | 276 | ||
291 | extern void dmac_inv_range(const void *, const void *); | 277 | extern void dmac_map_area(const void *, size_t, int); |
292 | extern void dmac_clean_range(const void *, const void *); | 278 | extern void dmac_unmap_area(const void *, size_t, int); |
293 | extern void dmac_flush_range(const void *, const void *); | 279 | extern void dmac_flush_range(const void *, const void *); |
294 | 280 | ||
295 | #endif | 281 | #endif |
@@ -330,12 +316,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end) | |||
330 | * processes address space. Really, we want to allow our "user | 316 | * processes address space. Really, we want to allow our "user |
331 | * space" model to handle this. | 317 | * space" model to handle this. |
332 | */ | 318 | */ |
333 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | 319 | extern void copy_to_user_page(struct vm_area_struct *, struct page *, |
334 | do { \ | 320 | unsigned long, void *, const void *, unsigned long); |
335 | memcpy(dst, src, len); \ | ||
336 | flush_ptrace_access(vma, page, vaddr, dst, len, 1);\ | ||
337 | } while (0) | ||
338 | |||
339 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | 321 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
340 | do { \ | 322 | do { \ |
341 | memcpy(dst, src, len); \ | 323 | memcpy(dst, src, len); \ |
@@ -369,17 +351,6 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig | |||
369 | } | 351 | } |
370 | } | 352 | } |
371 | 353 | ||
372 | static inline void | ||
373 | vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | ||
374 | unsigned long uaddr, void *kaddr, | ||
375 | unsigned long len, int write) | ||
376 | { | ||
377 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { | ||
378 | unsigned long addr = (unsigned long)kaddr; | ||
379 | __cpuc_coherent_kern_range(addr, addr + len); | ||
380 | } | ||
381 | } | ||
382 | |||
383 | #ifndef CONFIG_CPU_CACHE_VIPT | 354 | #ifndef CONFIG_CPU_CACHE_VIPT |
384 | #define flush_cache_mm(mm) \ | 355 | #define flush_cache_mm(mm) \ |
385 | vivt_flush_cache_mm(mm) | 356 | vivt_flush_cache_mm(mm) |
@@ -387,15 +358,10 @@ vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | |||
387 | vivt_flush_cache_range(vma,start,end) | 358 | vivt_flush_cache_range(vma,start,end) |
388 | #define flush_cache_page(vma,addr,pfn) \ | 359 | #define flush_cache_page(vma,addr,pfn) \ |
389 | vivt_flush_cache_page(vma,addr,pfn) | 360 | vivt_flush_cache_page(vma,addr,pfn) |
390 | #define flush_ptrace_access(vma,page,ua,ka,len,write) \ | ||
391 | vivt_flush_ptrace_access(vma,page,ua,ka,len,write) | ||
392 | #else | 361 | #else |
393 | extern void flush_cache_mm(struct mm_struct *mm); | 362 | extern void flush_cache_mm(struct mm_struct *mm); |
394 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | 363 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
395 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); | 364 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); |
396 | extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | ||
397 | unsigned long uaddr, void *kaddr, | ||
398 | unsigned long len, int write); | ||
399 | #endif | 365 | #endif |
400 | 366 | ||
401 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) | 367 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index a96300bf83fd..256ee1c9f51a 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h | |||
@@ -57,18 +57,58 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) | |||
57 | #endif | 57 | #endif |
58 | 58 | ||
59 | /* | 59 | /* |
60 | * DMA-consistent mapping functions. These allocate/free a region of | 60 | * The DMA API is built upon the notion of "buffer ownership". A buffer |
61 | * uncached, unwrite-buffered mapped memory space for use with DMA | 61 | * is either exclusively owned by the CPU (and therefore may be accessed |
62 | * devices. This is the "generic" version. The PCI specific version | 62 | * by it) or exclusively owned by the DMA device. These helper functions |
63 | * is in pci.h | 63 | * represent the transitions between these two ownership states. |
64 | * | 64 | * |
65 | * Note: Drivers should NOT use this function directly, as it will break | 65 | * Note, however, that on later ARMs, this notion does not work due to |
66 | * platforms with CONFIG_DMABOUNCE. | 66 | * speculative prefetches. We model our approach on the assumption that |
67 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | 67 | * the CPU does do speculative prefetches, which means we clean caches |
68 | * before transfers and delay cache invalidation until transfer completion. | ||
69 | * | ||
70 | * Private support functions: these are not part of the API and are | ||
71 | * liable to change. Drivers must not use these. | ||
68 | */ | 72 | */ |
69 | extern void dma_cache_maint(const void *kaddr, size_t size, int rw); | 73 | static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size, |
70 | extern void dma_cache_maint_page(struct page *page, unsigned long offset, | 74 | enum dma_data_direction dir) |
71 | size_t size, int rw); | 75 | { |
76 | extern void ___dma_single_cpu_to_dev(const void *, size_t, | ||
77 | enum dma_data_direction); | ||
78 | |||
79 | if (!arch_is_coherent()) | ||
80 | ___dma_single_cpu_to_dev(kaddr, size, dir); | ||
81 | } | ||
82 | |||
83 | static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size, | ||
84 | enum dma_data_direction dir) | ||
85 | { | ||
86 | extern void ___dma_single_dev_to_cpu(const void *, size_t, | ||
87 | enum dma_data_direction); | ||
88 | |||
89 | if (!arch_is_coherent()) | ||
90 | ___dma_single_dev_to_cpu(kaddr, size, dir); | ||
91 | } | ||
92 | |||
93 | static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | ||
94 | size_t size, enum dma_data_direction dir) | ||
95 | { | ||
96 | extern void ___dma_page_cpu_to_dev(struct page *, unsigned long, | ||
97 | size_t, enum dma_data_direction); | ||
98 | |||
99 | if (!arch_is_coherent()) | ||
100 | ___dma_page_cpu_to_dev(page, off, size, dir); | ||
101 | } | ||
102 | |||
103 | static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off, | ||
104 | size_t size, enum dma_data_direction dir) | ||
105 | { | ||
106 | extern void ___dma_page_dev_to_cpu(struct page *, unsigned long, | ||
107 | size_t, enum dma_data_direction); | ||
108 | |||
109 | if (!arch_is_coherent()) | ||
110 | ___dma_page_dev_to_cpu(page, off, size, dir); | ||
111 | } | ||
72 | 112 | ||
73 | /* | 113 | /* |
74 | * Return whether the given device DMA address mask can be supported | 114 | * Return whether the given device DMA address mask can be supported |
@@ -304,8 +344,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, | |||
304 | { | 344 | { |
305 | BUG_ON(!valid_dma_direction(dir)); | 345 | BUG_ON(!valid_dma_direction(dir)); |
306 | 346 | ||
307 | if (!arch_is_coherent()) | 347 | __dma_single_cpu_to_dev(cpu_addr, size, dir); |
308 | dma_cache_maint(cpu_addr, size, dir); | ||
309 | 348 | ||
310 | return virt_to_dma(dev, cpu_addr); | 349 | return virt_to_dma(dev, cpu_addr); |
311 | } | 350 | } |
@@ -329,8 +368,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
329 | { | 368 | { |
330 | BUG_ON(!valid_dma_direction(dir)); | 369 | BUG_ON(!valid_dma_direction(dir)); |
331 | 370 | ||
332 | if (!arch_is_coherent()) | 371 | __dma_page_cpu_to_dev(page, offset, size, dir); |
333 | dma_cache_maint_page(page, offset, size, dir); | ||
334 | 372 | ||
335 | return page_to_dma(dev, page) + offset; | 373 | return page_to_dma(dev, page) + offset; |
336 | } | 374 | } |
@@ -352,7 +390,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
352 | static inline void dma_unmap_single(struct device *dev, dma_addr_t handle, | 390 | static inline void dma_unmap_single(struct device *dev, dma_addr_t handle, |
353 | size_t size, enum dma_data_direction dir) | 391 | size_t size, enum dma_data_direction dir) |
354 | { | 392 | { |
355 | /* nothing to do */ | 393 | __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir); |
356 | } | 394 | } |
357 | 395 | ||
358 | /** | 396 | /** |
@@ -372,7 +410,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle, | |||
372 | static inline void dma_unmap_page(struct device *dev, dma_addr_t handle, | 410 | static inline void dma_unmap_page(struct device *dev, dma_addr_t handle, |
373 | size_t size, enum dma_data_direction dir) | 411 | size_t size, enum dma_data_direction dir) |
374 | { | 412 | { |
375 | /* nothing to do */ | 413 | __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK, |
414 | size, dir); | ||
376 | } | 415 | } |
377 | #endif /* CONFIG_DMABOUNCE */ | 416 | #endif /* CONFIG_DMABOUNCE */ |
378 | 417 | ||
@@ -400,7 +439,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev, | |||
400 | { | 439 | { |
401 | BUG_ON(!valid_dma_direction(dir)); | 440 | BUG_ON(!valid_dma_direction(dir)); |
402 | 441 | ||
403 | dmabounce_sync_for_cpu(dev, handle, offset, size, dir); | 442 | if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir)) |
443 | return; | ||
444 | |||
445 | __dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir); | ||
404 | } | 446 | } |
405 | 447 | ||
406 | static inline void dma_sync_single_range_for_device(struct device *dev, | 448 | static inline void dma_sync_single_range_for_device(struct device *dev, |
@@ -412,8 +454,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev, | |||
412 | if (!dmabounce_sync_for_device(dev, handle, offset, size, dir)) | 454 | if (!dmabounce_sync_for_device(dev, handle, offset, size, dir)) |
413 | return; | 455 | return; |
414 | 456 | ||
415 | if (!arch_is_coherent()) | 457 | __dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir); |
416 | dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir); | ||
417 | } | 458 | } |
418 | 459 | ||
419 | static inline void dma_sync_single_for_cpu(struct device *dev, | 460 | static inline void dma_sync_single_for_cpu(struct device *dev, |
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index d2a59cfc30ce..c980156f3263 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h | |||
@@ -69,9 +69,16 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); | |||
69 | /* | 69 | /* |
70 | * __arm_ioremap takes CPU physical address. | 70 | * __arm_ioremap takes CPU physical address. |
71 | * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page | 71 | * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page |
72 | * The _caller variety takes a __builtin_return_address(0) value for | ||
73 | * /proc/vmalloc to use - and should only be used in non-inline functions. | ||
72 | */ | 74 | */ |
73 | extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); | 75 | extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, |
74 | extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int); | 76 | size_t, unsigned int, void *); |
77 | extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int, | ||
78 | void *); | ||
79 | |||
80 | extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); | ||
81 | extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); | ||
75 | extern void __iounmap(volatile void __iomem *addr); | 82 | extern void __iounmap(volatile void __iomem *addr); |
76 | 83 | ||
77 | /* | 84 | /* |
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index b2cc1fcd0400..8bffc3ff3acf 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h | |||
@@ -46,12 +46,4 @@ struct sys_timer { | |||
46 | extern struct sys_timer *system_timer; | 46 | extern struct sys_timer *system_timer; |
47 | extern void timer_tick(void); | 47 | extern void timer_tick(void); |
48 | 48 | ||
49 | /* | ||
50 | * Kernel time keeping support. | ||
51 | */ | ||
52 | struct timespec; | ||
53 | extern int (*set_rtc)(void); | ||
54 | extern void save_time_delta(struct timespec *delta, struct timespec *rtc); | ||
55 | extern void restore_time_delta(struct timespec *delta, struct timespec *rtc); | ||
56 | |||
57 | #endif | 49 | #endif |
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 5421d82a2572..4312ee5e3d0b 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h | |||
@@ -76,6 +76,17 @@ | |||
76 | */ | 76 | */ |
77 | #define IOREMAP_MAX_ORDER 24 | 77 | #define IOREMAP_MAX_ORDER 24 |
78 | 78 | ||
79 | /* | ||
80 | * Size of DMA-consistent memory region. Must be multiple of 2M, | ||
81 | * between 2MB and 14MB inclusive. | ||
82 | */ | ||
83 | #ifndef CONSISTENT_DMA_SIZE | ||
84 | #define CONSISTENT_DMA_SIZE SZ_2M | ||
85 | #endif | ||
86 | |||
87 | #define CONSISTENT_END (0xffe00000UL) | ||
88 | #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) | ||
89 | |||
79 | #else /* CONFIG_MMU */ | 90 | #else /* CONFIG_MMU */ |
80 | 91 | ||
81 | /* | 92 | /* |
@@ -93,11 +104,11 @@ | |||
93 | #endif | 104 | #endif |
94 | 105 | ||
95 | #ifndef PHYS_OFFSET | 106 | #ifndef PHYS_OFFSET |
96 | #define PHYS_OFFSET (CONFIG_DRAM_BASE) | 107 | #define PHYS_OFFSET UL(CONFIG_DRAM_BASE) |
97 | #endif | 108 | #endif |
98 | 109 | ||
99 | #ifndef END_MEM | 110 | #ifndef END_MEM |
100 | #define END_MEM (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE) | 111 | #define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE) |
101 | #endif | 112 | #endif |
102 | 113 | ||
103 | #ifndef PAGE_OFFSET | 114 | #ifndef PAGE_OFFSET |
@@ -113,14 +124,6 @@ | |||
113 | #endif /* !CONFIG_MMU */ | 124 | #endif /* !CONFIG_MMU */ |
114 | 125 | ||
115 | /* | 126 | /* |
116 | * Size of DMA-consistent memory region. Must be multiple of 2M, | ||
117 | * between 2MB and 14MB inclusive. | ||
118 | */ | ||
119 | #ifndef CONSISTENT_DMA_SIZE | ||
120 | #define CONSISTENT_DMA_SIZE SZ_2M | ||
121 | #endif | ||
122 | |||
123 | /* | ||
124 | * Physical vs virtual RAM address space conversion. These are | 127 | * Physical vs virtual RAM address space conversion. These are |
125 | * private definitions which should NOT be used outside memory.h | 128 | * private definitions which should NOT be used outside memory.h |
126 | * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. | 129 | * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. |
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index b561584d04a1..68870c776671 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h | |||
@@ -6,6 +6,7 @@ | |||
6 | typedef struct { | 6 | typedef struct { |
7 | #ifdef CONFIG_CPU_HAS_ASID | 7 | #ifdef CONFIG_CPU_HAS_ASID |
8 | unsigned int id; | 8 | unsigned int id; |
9 | spinlock_t id_lock; | ||
9 | #endif | 10 | #endif |
10 | unsigned int kvm_seq; | 11 | unsigned int kvm_seq; |
11 | } mm_context_t; | 12 | } mm_context_t; |
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index de6cefb329dd..a0b3cac0547c 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h | |||
@@ -43,12 +43,23 @@ void __check_kvm_seq(struct mm_struct *mm); | |||
43 | #define ASID_FIRST_VERSION (1 << ASID_BITS) | 43 | #define ASID_FIRST_VERSION (1 << ASID_BITS) |
44 | 44 | ||
45 | extern unsigned int cpu_last_asid; | 45 | extern unsigned int cpu_last_asid; |
46 | #ifdef CONFIG_SMP | ||
47 | DECLARE_PER_CPU(struct mm_struct *, current_mm); | ||
48 | #endif | ||
46 | 49 | ||
47 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); | 50 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); |
48 | void __new_context(struct mm_struct *mm); | 51 | void __new_context(struct mm_struct *mm); |
49 | 52 | ||
50 | static inline void check_context(struct mm_struct *mm) | 53 | static inline void check_context(struct mm_struct *mm) |
51 | { | 54 | { |
55 | /* | ||
56 | * This code is executed with interrupts enabled. Therefore, | ||
57 | * mm->context.id cannot be updated to the latest ASID version | ||
58 | * on a different CPU (and condition below not triggered) | ||
59 | * without first getting an IPI to reset the context. The | ||
60 | * alternative is to take a read_lock on mm->context.id_lock | ||
61 | * (after changing its type to rwlock_t). | ||
62 | */ | ||
52 | if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) | 63 | if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) |
53 | __new_context(mm); | 64 | __new_context(mm); |
54 | 65 | ||
@@ -108,6 +119,10 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
108 | __flush_icache_all(); | 119 | __flush_icache_all(); |
109 | #endif | 120 | #endif |
110 | if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { | 121 | if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { |
122 | #ifdef CONFIG_SMP | ||
123 | struct mm_struct **crt_mm = &per_cpu(current_mm, cpu); | ||
124 | *crt_mm = next; | ||
125 | #endif | ||
111 | check_context(next); | 126 | check_context(next); |
112 | cpu_switch_mm(next->pgd, next); | 127 | cpu_switch_mm(next->pgd, next); |
113 | if (cache_is_vivt()) | 128 | if (cache_is_vivt()) |
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index 3a32af4cce30..a485ac3c8696 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h | |||
@@ -117,11 +117,12 @@ | |||
117 | #endif | 117 | #endif |
118 | 118 | ||
119 | struct page; | 119 | struct page; |
120 | struct vm_area_struct; | ||
120 | 121 | ||
121 | struct cpu_user_fns { | 122 | struct cpu_user_fns { |
122 | void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr); | 123 | void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr); |
123 | void (*cpu_copy_user_highpage)(struct page *to, struct page *from, | 124 | void (*cpu_copy_user_highpage)(struct page *to, struct page *from, |
124 | unsigned long vaddr); | 125 | unsigned long vaddr, struct vm_area_struct *vma); |
125 | }; | 126 | }; |
126 | 127 | ||
127 | #ifdef MULTI_USER | 128 | #ifdef MULTI_USER |
@@ -137,7 +138,7 @@ extern struct cpu_user_fns cpu_user; | |||
137 | 138 | ||
138 | extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr); | 139 | extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr); |
139 | extern void __cpu_copy_user_highpage(struct page *to, struct page *from, | 140 | extern void __cpu_copy_user_highpage(struct page *to, struct page *from, |
140 | unsigned long vaddr); | 141 | unsigned long vaddr, struct vm_area_struct *vma); |
141 | #endif | 142 | #endif |
142 | 143 | ||
143 | #define clear_user_highpage(page,vaddr) \ | 144 | #define clear_user_highpage(page,vaddr) \ |
@@ -145,7 +146,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, | |||
145 | 146 | ||
146 | #define __HAVE_ARCH_COPY_USER_HIGHPAGE | 147 | #define __HAVE_ARCH_COPY_USER_HIGHPAGE |
147 | #define copy_user_highpage(to,from,vaddr,vma) \ | 148 | #define copy_user_highpage(to,from,vaddr,vma) \ |
148 | __cpu_copy_user_highpage(to, from, vaddr) | 149 | __cpu_copy_user_highpage(to, from, vaddr, vma) |
149 | 150 | ||
150 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) | 151 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) |
151 | extern void copy_page(void *to, const void *from); | 152 | extern void copy_page(void *to, const void *from); |
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h new file mode 100644 index 000000000000..49e3049aba32 --- /dev/null +++ b/arch/arm/include/asm/perf_event.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/include/asm/perf_event.h | ||
3 | * | ||
4 | * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #ifndef __ARM_PERF_EVENT_H__ | ||
13 | #define __ARM_PERF_EVENT_H__ | ||
14 | |||
15 | /* | ||
16 | * NOP: on *most* (read: all supported) ARM platforms, the performance | ||
17 | * counter interrupts are regular interrupts and not an NMI. This | ||
18 | * means that when we receive the interrupt we can call | ||
19 | * perf_event_do_pending() that handles all of the work with | ||
20 | * interrupts enabled. | ||
21 | */ | ||
22 | static inline void | ||
23 | set_perf_event_pending(void) | ||
24 | { | ||
25 | } | ||
26 | |||
27 | /* ARM performance counters start from 1 (in the cp15 accesses) so use the | ||
28 | * same indexes here for consistency. */ | ||
29 | #define PERF_EVENT_INDEX_OFFSET 1 | ||
30 | |||
31 | #endif /* __ARM_PERF_EVENT_H__ */ | ||
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h index b011f2e939aa..013cfcdc4839 100644 --- a/arch/arm/include/asm/pgtable-nommu.h +++ b/arch/arm/include/asm/pgtable-nommu.h | |||
@@ -86,8 +86,8 @@ extern unsigned int kobjsize(const void *objp); | |||
86 | * All 32bit addresses are effectively valid for vmalloc... | 86 | * All 32bit addresses are effectively valid for vmalloc... |
87 | * Sort of meaningless for non-VM targets. | 87 | * Sort of meaningless for non-VM targets. |
88 | */ | 88 | */ |
89 | #define VMALLOC_START 0 | 89 | #define VMALLOC_START 0UL |
90 | #define VMALLOC_END 0xffffffff | 90 | #define VMALLOC_END 0xffffffffUL |
91 | 91 | ||
92 | #define FIRST_USER_ADDRESS (0) | 92 | #define FIRST_USER_ADDRESS (0) |
93 | 93 | ||
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h new file mode 100644 index 000000000000..2829b9f981a1 --- /dev/null +++ b/arch/arm/include/asm/pmu.h | |||
@@ -0,0 +1,75 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/include/asm/pmu.h | ||
3 | * | ||
4 | * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #ifndef __ARM_PMU_H__ | ||
13 | #define __ARM_PMU_H__ | ||
14 | |||
15 | #ifdef CONFIG_CPU_HAS_PMU | ||
16 | |||
17 | struct pmu_irqs { | ||
18 | const int *irqs; | ||
19 | int num_irqs; | ||
20 | }; | ||
21 | |||
22 | /** | ||
23 | * reserve_pmu() - reserve the hardware performance counters | ||
24 | * | ||
25 | * Reserve the hardware performance counters in the system for exclusive use. | ||
26 | * The 'struct pmu_irqs' for the system is returned on success, ERR_PTR() | ||
27 | * encoded error on failure. | ||
28 | */ | ||
29 | extern const struct pmu_irqs * | ||
30 | reserve_pmu(void); | ||
31 | |||
32 | /** | ||
33 | * release_pmu() - Relinquish control of the performance counters | ||
34 | * | ||
35 | * Release the performance counters and allow someone else to use them. | ||
36 | * Callers must have disabled the counters and released IRQs before calling | ||
37 | * this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as | ||
38 | * a cookie. | ||
39 | */ | ||
40 | extern int | ||
41 | release_pmu(const struct pmu_irqs *irqs); | ||
42 | |||
43 | /** | ||
44 | * init_pmu() - Initialise the PMU. | ||
45 | * | ||
46 | * Initialise the system ready for PMU enabling. This should typically set the | ||
47 | * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do | ||
48 | * the actual hardware initialisation. | ||
49 | */ | ||
50 | extern int | ||
51 | init_pmu(void); | ||
52 | |||
53 | #else /* CONFIG_CPU_HAS_PMU */ | ||
54 | |||
55 | static inline const struct pmu_irqs * | ||
56 | reserve_pmu(void) | ||
57 | { | ||
58 | return ERR_PTR(-ENODEV); | ||
59 | } | ||
60 | |||
61 | static inline int | ||
62 | release_pmu(const struct pmu_irqs *irqs) | ||
63 | { | ||
64 | return -ENODEV; | ||
65 | } | ||
66 | |||
67 | static inline int | ||
68 | init_pmu(void) | ||
69 | { | ||
70 | return -ENODEV; | ||
71 | } | ||
72 | |||
73 | #endif /* CONFIG_CPU_HAS_PMU */ | ||
74 | |||
75 | #endif /* __ARM_PMU_H__ */ | ||
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 5ccce0a9b03c..f392fb4437af 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h | |||
@@ -223,18 +223,6 @@ extern struct meminfo meminfo; | |||
223 | #define bank_phys_end(bank) ((bank)->start + (bank)->size) | 223 | #define bank_phys_end(bank) ((bank)->start + (bank)->size) |
224 | #define bank_phys_size(bank) (bank)->size | 224 | #define bank_phys_size(bank) (bank)->size |
225 | 225 | ||
226 | /* | ||
227 | * Early command line parameters. | ||
228 | */ | ||
229 | struct early_params { | ||
230 | const char *arg; | ||
231 | void (*fn)(char **p); | ||
232 | }; | ||
233 | |||
234 | #define __early_param(name,fn) \ | ||
235 | static struct early_params __early_##fn __used \ | ||
236 | __attribute__((__section__(".early_param.init"))) = { name, fn } | ||
237 | |||
238 | #endif /* __KERNEL__ */ | 226 | #endif /* __KERNEL__ */ |
239 | 227 | ||
240 | #endif | 228 | #endif |
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index 59303e200845..e6215305544a 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h | |||
@@ -13,4 +13,9 @@ static inline int tlb_ops_need_broadcast(void) | |||
13 | return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2; | 13 | return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2; |
14 | } | 14 | } |
15 | 15 | ||
16 | static inline int cache_ops_need_broadcast(void) | ||
17 | { | ||
18 | return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1; | ||
19 | } | ||
20 | |||
16 | #endif | 21 | #endif |
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index c91c64cab922..17eb355707dd 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h | |||
@@ -5,6 +5,22 @@ | |||
5 | #error SMP not supported on pre-ARMv6 CPUs | 5 | #error SMP not supported on pre-ARMv6 CPUs |
6 | #endif | 6 | #endif |
7 | 7 | ||
8 | static inline void dsb_sev(void) | ||
9 | { | ||
10 | #if __LINUX_ARM_ARCH__ >= 7 | ||
11 | __asm__ __volatile__ ( | ||
12 | "dsb\n" | ||
13 | "sev" | ||
14 | ); | ||
15 | #elif defined(CONFIG_CPU_32v6K) | ||
16 | __asm__ __volatile__ ( | ||
17 | "mcr p15, 0, %0, c7, c10, 4\n" | ||
18 | "sev" | ||
19 | : : "r" (0) | ||
20 | ); | ||
21 | #endif | ||
22 | } | ||
23 | |||
8 | /* | 24 | /* |
9 | * ARMv6 Spin-locking. | 25 | * ARMv6 Spin-locking. |
10 | * | 26 | * |
@@ -69,13 +85,11 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) | |||
69 | 85 | ||
70 | __asm__ __volatile__( | 86 | __asm__ __volatile__( |
71 | " str %1, [%0]\n" | 87 | " str %1, [%0]\n" |
72 | #ifdef CONFIG_CPU_32v6K | ||
73 | " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ | ||
74 | " sev" | ||
75 | #endif | ||
76 | : | 88 | : |
77 | : "r" (&lock->lock), "r" (0) | 89 | : "r" (&lock->lock), "r" (0) |
78 | : "cc"); | 90 | : "cc"); |
91 | |||
92 | dsb_sev(); | ||
79 | } | 93 | } |
80 | 94 | ||
81 | /* | 95 | /* |
@@ -132,13 +146,11 @@ static inline void arch_write_unlock(arch_rwlock_t *rw) | |||
132 | 146 | ||
133 | __asm__ __volatile__( | 147 | __asm__ __volatile__( |
134 | "str %1, [%0]\n" | 148 | "str %1, [%0]\n" |
135 | #ifdef CONFIG_CPU_32v6K | ||
136 | " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ | ||
137 | " sev\n" | ||
138 | #endif | ||
139 | : | 149 | : |
140 | : "r" (&rw->lock), "r" (0) | 150 | : "r" (&rw->lock), "r" (0) |
141 | : "cc"); | 151 | : "cc"); |
152 | |||
153 | dsb_sev(); | ||
142 | } | 154 | } |
143 | 155 | ||
144 | /* write_can_lock - would write_trylock() succeed? */ | 156 | /* write_can_lock - would write_trylock() succeed? */ |
@@ -188,14 +200,12 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) | |||
188 | " strex %1, %0, [%2]\n" | 200 | " strex %1, %0, [%2]\n" |
189 | " teq %1, #0\n" | 201 | " teq %1, #0\n" |
190 | " bne 1b" | 202 | " bne 1b" |
191 | #ifdef CONFIG_CPU_32v6K | ||
192 | "\n cmp %0, #0\n" | ||
193 | " mcreq p15, 0, %0, c7, c10, 4\n" | ||
194 | " seveq" | ||
195 | #endif | ||
196 | : "=&r" (tmp), "=&r" (tmp2) | 203 | : "=&r" (tmp), "=&r" (tmp2) |
197 | : "r" (&rw->lock) | 204 | : "r" (&rw->lock) |
198 | : "cc"); | 205 | : "cc"); |
206 | |||
207 | if (tmp == 0) | ||
208 | dsb_sev(); | ||
199 | } | 209 | } |
200 | 210 | ||
201 | static inline int arch_read_trylock(arch_rwlock_t *rw) | 211 | static inline int arch_read_trylock(arch_rwlock_t *rw) |
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 058e7e90881d..ca88e6a84707 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h | |||
@@ -73,8 +73,7 @@ extern unsigned int mem_fclk_21285; | |||
73 | 73 | ||
74 | struct pt_regs; | 74 | struct pt_regs; |
75 | 75 | ||
76 | void die(const char *msg, struct pt_regs *regs, int err) | 76 | void die(const char *msg, struct pt_regs *regs, int err); |
77 | __attribute__((noreturn)); | ||
78 | 77 | ||
79 | struct siginfo; | 78 | struct siginfo; |
80 | void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, | 79 | void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, |
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 2dfb7d7a66e9..b74970ec02c4 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h | |||
@@ -115,7 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *); | |||
115 | extern void iwmmxt_task_release(struct thread_info *); | 115 | extern void iwmmxt_task_release(struct thread_info *); |
116 | extern void iwmmxt_task_switch(struct thread_info *); | 116 | extern void iwmmxt_task_switch(struct thread_info *); |
117 | 117 | ||
118 | extern void vfp_sync_state(struct thread_info *thread); | 118 | extern void vfp_sync_hwstate(struct thread_info *); |
119 | extern void vfp_flush_hwstate(struct thread_info *); | ||
119 | 120 | ||
120 | #endif | 121 | #endif |
121 | 122 | ||
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index c2f1605de359..e085e2c545eb 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -529,7 +529,8 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |||
529 | * cache entries for the kernels virtual memory range are written | 529 | * cache entries for the kernels virtual memory range are written |
530 | * back to the page. | 530 | * back to the page. |
531 | */ | 531 | */ |
532 | extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte); | 532 | extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, |
533 | pte_t *ptep); | ||
533 | 534 | ||
534 | #endif | 535 | #endif |
535 | 536 | ||
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index dd00f747e2ad..26d302c28e13 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
@@ -17,6 +17,7 @@ obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \ | |||
17 | process.o ptrace.o return_address.o setup.o signal.o \ | 17 | process.o ptrace.o return_address.o setup.o signal.o \ |
18 | sys_arm.o stacktrace.o time.o traps.o | 18 | sys_arm.o stacktrace.o time.o traps.o |
19 | 19 | ||
20 | obj-$(CONFIG_LEDS) += leds.o | ||
20 | obj-$(CONFIG_OC_ETM) += etm.o | 21 | obj-$(CONFIG_OC_ETM) += etm.o |
21 | 22 | ||
22 | obj-$(CONFIG_ISA_DMA_API) += dma.o | 23 | obj-$(CONFIG_ISA_DMA_API) += dma.o |
@@ -46,6 +47,8 @@ obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o | |||
46 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o | 47 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o |
47 | obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o | 48 | obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o |
48 | obj-$(CONFIG_IWMMXT) += iwmmxt.o | 49 | obj-$(CONFIG_IWMMXT) += iwmmxt.o |
50 | obj-$(CONFIG_CPU_HAS_PMU) += pmu.o | ||
51 | obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o | ||
49 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt | 52 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt |
50 | 53 | ||
51 | ifneq ($(CONFIG_ARCH_EBSA110),y) | 54 | ifneq ($(CONFIG_ARCH_EBSA110),y) |
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 4a881258bb17..883511522fca 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c | |||
@@ -12,6 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | #include <linux/sched.h> | 13 | #include <linux/sched.h> |
14 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
15 | #include <linux/dma-mapping.h> | ||
15 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
16 | #include <asm/thread_info.h> | 17 | #include <asm/thread_info.h> |
17 | #include <asm/memory.h> | 18 | #include <asm/memory.h> |
@@ -112,5 +113,9 @@ int main(void) | |||
112 | #ifdef MULTI_PABORT | 113 | #ifdef MULTI_PABORT |
113 | DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); | 114 | DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); |
114 | #endif | 115 | #endif |
116 | BLANK(); | ||
117 | DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); | ||
118 | DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); | ||
119 | DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); | ||
115 | return 0; | 120 | return 0; |
116 | } | 121 | } |
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 5c91addcaebc..a38b4879441d 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S | |||
@@ -24,7 +24,7 @@ | |||
24 | 24 | ||
25 | #if defined(CONFIG_CPU_V6) | 25 | #if defined(CONFIG_CPU_V6) |
26 | 26 | ||
27 | .macro addruart, rx | 27 | .macro addruart, rx, tmp |
28 | .endm | 28 | .endm |
29 | 29 | ||
30 | .macro senduart, rd, rx | 30 | .macro senduart, rd, rx |
@@ -51,7 +51,7 @@ | |||
51 | 51 | ||
52 | #elif defined(CONFIG_CPU_V7) | 52 | #elif defined(CONFIG_CPU_V7) |
53 | 53 | ||
54 | .macro addruart, rx | 54 | .macro addruart, rx, tmp |
55 | .endm | 55 | .endm |
56 | 56 | ||
57 | .macro senduart, rd, rx | 57 | .macro senduart, rd, rx |
@@ -71,7 +71,7 @@ wait: mrc p14, 0, pc, c0, c1, 0 | |||
71 | 71 | ||
72 | #elif defined(CONFIG_CPU_XSCALE) | 72 | #elif defined(CONFIG_CPU_XSCALE) |
73 | 73 | ||
74 | .macro addruart, rx | 74 | .macro addruart, rx, tmp |
75 | .endm | 75 | .endm |
76 | 76 | ||
77 | .macro senduart, rd, rx | 77 | .macro senduart, rd, rx |
@@ -98,7 +98,7 @@ wait: mrc p14, 0, pc, c0, c1, 0 | |||
98 | 98 | ||
99 | #else | 99 | #else |
100 | 100 | ||
101 | .macro addruart, rx | 101 | .macro addruart, rx, tmp |
102 | .endm | 102 | .endm |
103 | 103 | ||
104 | .macro senduart, rd, rx | 104 | .macro senduart, rd, rx |
@@ -164,7 +164,7 @@ ENDPROC(printhex2) | |||
164 | .ltorg | 164 | .ltorg |
165 | 165 | ||
166 | ENTRY(printascii) | 166 | ENTRY(printascii) |
167 | addruart r3 | 167 | addruart r3, r1 |
168 | b 2f | 168 | b 2f |
169 | 1: waituart r2, r3 | 169 | 1: waituart r2, r3 |
170 | senduart r1, r3 | 170 | senduart r1, r3 |
@@ -180,7 +180,7 @@ ENTRY(printascii) | |||
180 | ENDPROC(printascii) | 180 | ENDPROC(printascii) |
181 | 181 | ||
182 | ENTRY(printch) | 182 | ENTRY(printch) |
183 | addruart r3 | 183 | addruart r3, r1 |
184 | mov r1, r0 | 184 | mov r1, r0 |
185 | mov r0, #0 | 185 | mov r0, #0 |
186 | b 1b | 186 | b 1b |
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c new file mode 100644 index 000000000000..31a316c1777b --- /dev/null +++ b/arch/arm/kernel/leds.c | |||
@@ -0,0 +1,115 @@ | |||
1 | /* | ||
2 | * LED support code, ripped out of arch/arm/kernel/time.c | ||
3 | * | ||
4 | * Copyright (C) 1994-2001 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <linux/module.h> | ||
11 | #include <linux/init.h> | ||
12 | #include <linux/sysdev.h> | ||
13 | |||
14 | #include <asm/leds.h> | ||
15 | |||
16 | static void dummy_leds_event(led_event_t evt) | ||
17 | { | ||
18 | } | ||
19 | |||
20 | void (*leds_event)(led_event_t) = dummy_leds_event; | ||
21 | |||
22 | struct leds_evt_name { | ||
23 | const char name[8]; | ||
24 | int on; | ||
25 | int off; | ||
26 | }; | ||
27 | |||
28 | static const struct leds_evt_name evt_names[] = { | ||
29 | { "amber", led_amber_on, led_amber_off }, | ||
30 | { "blue", led_blue_on, led_blue_off }, | ||
31 | { "green", led_green_on, led_green_off }, | ||
32 | { "red", led_red_on, led_red_off }, | ||
33 | }; | ||
34 | |||
35 | static ssize_t leds_store(struct sys_device *dev, | ||
36 | struct sysdev_attribute *attr, | ||
37 | const char *buf, size_t size) | ||
38 | { | ||
39 | int ret = -EINVAL, len = strcspn(buf, " "); | ||
40 | |||
41 | if (len > 0 && buf[len] == '\0') | ||
42 | len--; | ||
43 | |||
44 | if (strncmp(buf, "claim", len) == 0) { | ||
45 | leds_event(led_claim); | ||
46 | ret = size; | ||
47 | } else if (strncmp(buf, "release", len) == 0) { | ||
48 | leds_event(led_release); | ||
49 | ret = size; | ||
50 | } else { | ||
51 | int i; | ||
52 | |||
53 | for (i = 0; i < ARRAY_SIZE(evt_names); i++) { | ||
54 | if (strlen(evt_names[i].name) != len || | ||
55 | strncmp(buf, evt_names[i].name, len) != 0) | ||
56 | continue; | ||
57 | if (strncmp(buf+len, " on", 3) == 0) { | ||
58 | leds_event(evt_names[i].on); | ||
59 | ret = size; | ||
60 | } else if (strncmp(buf+len, " off", 4) == 0) { | ||
61 | leds_event(evt_names[i].off); | ||
62 | ret = size; | ||
63 | } | ||
64 | break; | ||
65 | } | ||
66 | } | ||
67 | return ret; | ||
68 | } | ||
69 | |||
70 | static SYSDEV_ATTR(event, 0200, NULL, leds_store); | ||
71 | |||
72 | static int leds_suspend(struct sys_device *dev, pm_message_t state) | ||
73 | { | ||
74 | leds_event(led_stop); | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | static int leds_resume(struct sys_device *dev) | ||
79 | { | ||
80 | leds_event(led_start); | ||
81 | return 0; | ||
82 | } | ||
83 | |||
84 | static int leds_shutdown(struct sys_device *dev) | ||
85 | { | ||
86 | leds_event(led_halted); | ||
87 | return 0; | ||
88 | } | ||
89 | |||
90 | static struct sysdev_class leds_sysclass = { | ||
91 | .name = "leds", | ||
92 | .shutdown = leds_shutdown, | ||
93 | .suspend = leds_suspend, | ||
94 | .resume = leds_resume, | ||
95 | }; | ||
96 | |||
97 | static struct sys_device leds_device = { | ||
98 | .id = 0, | ||
99 | .cls = &leds_sysclass, | ||
100 | }; | ||
101 | |||
102 | static int __init leds_init(void) | ||
103 | { | ||
104 | int ret; | ||
105 | ret = sysdev_class_register(&leds_sysclass); | ||
106 | if (ret == 0) | ||
107 | ret = sysdev_register(&leds_device); | ||
108 | if (ret == 0) | ||
109 | ret = sysdev_create_file(&leds_device, &attr_event); | ||
110 | return ret; | ||
111 | } | ||
112 | |||
113 | device_initcall(leds_init); | ||
114 | |||
115 | EXPORT_SYMBOL(leds_event); | ||
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c new file mode 100644 index 000000000000..c54ceb3d1f97 --- /dev/null +++ b/arch/arm/kernel/perf_event.c | |||
@@ -0,0 +1,2276 @@ | |||
1 | #undef DEBUG | ||
2 | |||
3 | /* | ||
4 | * ARM performance counter support. | ||
5 | * | ||
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | ||
7 | * | ||
8 | * ARMv7 support: Jean Pihet <jpihet@mvista.com> | ||
9 | * 2010 (c) MontaVista Software, LLC. | ||
10 | * | ||
11 | * This code is based on the sparc64 perf event code, which is in turn based | ||
12 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | ||
13 | * code. | ||
14 | */ | ||
15 | #define pr_fmt(fmt) "hw perfevents: " fmt | ||
16 | |||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/perf_event.h> | ||
20 | #include <linux/spinlock.h> | ||
21 | #include <linux/uaccess.h> | ||
22 | |||
23 | #include <asm/cputype.h> | ||
24 | #include <asm/irq.h> | ||
25 | #include <asm/irq_regs.h> | ||
26 | #include <asm/pmu.h> | ||
27 | #include <asm/stacktrace.h> | ||
28 | |||
29 | static const struct pmu_irqs *pmu_irqs; | ||
30 | |||
31 | /* | ||
32 | * Hardware lock to serialize accesses to PMU registers. Needed for the | ||
33 | * read/modify/write sequences. | ||
34 | */ | ||
35 | DEFINE_SPINLOCK(pmu_lock); | ||
36 | |||
37 | /* | ||
38 | * ARMv6 supports a maximum of 3 events, starting from index 1. If we add | ||
39 | * another platform that supports more, we need to increase this to be the | ||
40 | * largest of all platforms. | ||
41 | * | ||
42 | * ARMv7 supports up to 32 events: | ||
43 | * cycle counter CCNT + 31 events counters CNT0..30. | ||
44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | ||
45 | */ | ||
46 | #define ARMPMU_MAX_HWEVENTS 33 | ||
47 | |||
48 | /* The events for a given CPU. */ | ||
49 | struct cpu_hw_events { | ||
50 | /* | ||
51 | * The events that are active on the CPU for the given index. Index 0 | ||
52 | * is reserved. | ||
53 | */ | ||
54 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; | ||
55 | |||
56 | /* | ||
57 | * A 1 bit for an index indicates that the counter is being used for | ||
58 | * an event. A 0 means that the counter can be used. | ||
59 | */ | ||
60 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | ||
61 | |||
62 | /* | ||
63 | * A 1 bit for an index indicates that the counter is actively being | ||
64 | * used. | ||
65 | */ | ||
66 | unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | ||
67 | }; | ||
68 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | ||
69 | |||
70 | struct arm_pmu { | ||
71 | char *name; | ||
72 | irqreturn_t (*handle_irq)(int irq_num, void *dev); | ||
73 | void (*enable)(struct hw_perf_event *evt, int idx); | ||
74 | void (*disable)(struct hw_perf_event *evt, int idx); | ||
75 | int (*event_map)(int evt); | ||
76 | u64 (*raw_event)(u64); | ||
77 | int (*get_event_idx)(struct cpu_hw_events *cpuc, | ||
78 | struct hw_perf_event *hwc); | ||
79 | u32 (*read_counter)(int idx); | ||
80 | void (*write_counter)(int idx, u32 val); | ||
81 | void (*start)(void); | ||
82 | void (*stop)(void); | ||
83 | int num_events; | ||
84 | u64 max_period; | ||
85 | }; | ||
86 | |||
87 | /* Set at runtime when we know what CPU type we are. */ | ||
88 | static const struct arm_pmu *armpmu; | ||
89 | |||
90 | #define HW_OP_UNSUPPORTED 0xFFFF | ||
91 | |||
92 | #define C(_x) \ | ||
93 | PERF_COUNT_HW_CACHE_##_x | ||
94 | |||
95 | #define CACHE_OP_UNSUPPORTED 0xFFFF | ||
96 | |||
97 | static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
98 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
99 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | ||
100 | |||
101 | static int | ||
102 | armpmu_map_cache_event(u64 config) | ||
103 | { | ||
104 | unsigned int cache_type, cache_op, cache_result, ret; | ||
105 | |||
106 | cache_type = (config >> 0) & 0xff; | ||
107 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | ||
108 | return -EINVAL; | ||
109 | |||
110 | cache_op = (config >> 8) & 0xff; | ||
111 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | ||
112 | return -EINVAL; | ||
113 | |||
114 | cache_result = (config >> 16) & 0xff; | ||
115 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | ||
116 | return -EINVAL; | ||
117 | |||
118 | ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result]; | ||
119 | |||
120 | if (ret == CACHE_OP_UNSUPPORTED) | ||
121 | return -ENOENT; | ||
122 | |||
123 | return ret; | ||
124 | } | ||
125 | |||
126 | static int | ||
127 | armpmu_event_set_period(struct perf_event *event, | ||
128 | struct hw_perf_event *hwc, | ||
129 | int idx) | ||
130 | { | ||
131 | s64 left = atomic64_read(&hwc->period_left); | ||
132 | s64 period = hwc->sample_period; | ||
133 | int ret = 0; | ||
134 | |||
135 | if (unlikely(left <= -period)) { | ||
136 | left = period; | ||
137 | atomic64_set(&hwc->period_left, left); | ||
138 | hwc->last_period = period; | ||
139 | ret = 1; | ||
140 | } | ||
141 | |||
142 | if (unlikely(left <= 0)) { | ||
143 | left += period; | ||
144 | atomic64_set(&hwc->period_left, left); | ||
145 | hwc->last_period = period; | ||
146 | ret = 1; | ||
147 | } | ||
148 | |||
149 | if (left > (s64)armpmu->max_period) | ||
150 | left = armpmu->max_period; | ||
151 | |||
152 | atomic64_set(&hwc->prev_count, (u64)-left); | ||
153 | |||
154 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | ||
155 | |||
156 | perf_event_update_userpage(event); | ||
157 | |||
158 | return ret; | ||
159 | } | ||
160 | |||
161 | static u64 | ||
162 | armpmu_event_update(struct perf_event *event, | ||
163 | struct hw_perf_event *hwc, | ||
164 | int idx) | ||
165 | { | ||
166 | int shift = 64 - 32; | ||
167 | s64 prev_raw_count, new_raw_count; | ||
168 | s64 delta; | ||
169 | |||
170 | again: | ||
171 | prev_raw_count = atomic64_read(&hwc->prev_count); | ||
172 | new_raw_count = armpmu->read_counter(idx); | ||
173 | |||
174 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | ||
175 | new_raw_count) != prev_raw_count) | ||
176 | goto again; | ||
177 | |||
178 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | ||
179 | delta >>= shift; | ||
180 | |||
181 | atomic64_add(delta, &event->count); | ||
182 | atomic64_sub(delta, &hwc->period_left); | ||
183 | |||
184 | return new_raw_count; | ||
185 | } | ||
186 | |||
187 | static void | ||
188 | armpmu_disable(struct perf_event *event) | ||
189 | { | ||
190 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
191 | struct hw_perf_event *hwc = &event->hw; | ||
192 | int idx = hwc->idx; | ||
193 | |||
194 | WARN_ON(idx < 0); | ||
195 | |||
196 | clear_bit(idx, cpuc->active_mask); | ||
197 | armpmu->disable(hwc, idx); | ||
198 | |||
199 | barrier(); | ||
200 | |||
201 | armpmu_event_update(event, hwc, idx); | ||
202 | cpuc->events[idx] = NULL; | ||
203 | clear_bit(idx, cpuc->used_mask); | ||
204 | |||
205 | perf_event_update_userpage(event); | ||
206 | } | ||
207 | |||
208 | static void | ||
209 | armpmu_read(struct perf_event *event) | ||
210 | { | ||
211 | struct hw_perf_event *hwc = &event->hw; | ||
212 | |||
213 | /* Don't read disabled counters! */ | ||
214 | if (hwc->idx < 0) | ||
215 | return; | ||
216 | |||
217 | armpmu_event_update(event, hwc, hwc->idx); | ||
218 | } | ||
219 | |||
220 | static void | ||
221 | armpmu_unthrottle(struct perf_event *event) | ||
222 | { | ||
223 | struct hw_perf_event *hwc = &event->hw; | ||
224 | |||
225 | /* | ||
226 | * Set the period again. Some counters can't be stopped, so when we | ||
227 | * were throttled we simply disabled the IRQ source and the counter | ||
228 | * may have been left counting. If we don't do this step then we may | ||
229 | * get an interrupt too soon or *way* too late if the overflow has | ||
230 | * happened since disabling. | ||
231 | */ | ||
232 | armpmu_event_set_period(event, hwc, hwc->idx); | ||
233 | armpmu->enable(hwc, hwc->idx); | ||
234 | } | ||
235 | |||
236 | static int | ||
237 | armpmu_enable(struct perf_event *event) | ||
238 | { | ||
239 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
240 | struct hw_perf_event *hwc = &event->hw; | ||
241 | int idx; | ||
242 | int err = 0; | ||
243 | |||
244 | /* If we don't have a space for the counter then finish early. */ | ||
245 | idx = armpmu->get_event_idx(cpuc, hwc); | ||
246 | if (idx < 0) { | ||
247 | err = idx; | ||
248 | goto out; | ||
249 | } | ||
250 | |||
251 | /* | ||
252 | * If there is an event in the counter we are going to use then make | ||
253 | * sure it is disabled. | ||
254 | */ | ||
255 | event->hw.idx = idx; | ||
256 | armpmu->disable(hwc, idx); | ||
257 | cpuc->events[idx] = event; | ||
258 | set_bit(idx, cpuc->active_mask); | ||
259 | |||
260 | /* Set the period for the event. */ | ||
261 | armpmu_event_set_period(event, hwc, idx); | ||
262 | |||
263 | /* Enable the event. */ | ||
264 | armpmu->enable(hwc, idx); | ||
265 | |||
266 | /* Propagate our changes to the userspace mapping. */ | ||
267 | perf_event_update_userpage(event); | ||
268 | |||
269 | out: | ||
270 | return err; | ||
271 | } | ||
272 | |||
273 | static struct pmu pmu = { | ||
274 | .enable = armpmu_enable, | ||
275 | .disable = armpmu_disable, | ||
276 | .unthrottle = armpmu_unthrottle, | ||
277 | .read = armpmu_read, | ||
278 | }; | ||
279 | |||
280 | static int | ||
281 | validate_event(struct cpu_hw_events *cpuc, | ||
282 | struct perf_event *event) | ||
283 | { | ||
284 | struct hw_perf_event fake_event = event->hw; | ||
285 | |||
286 | if (event->pmu && event->pmu != &pmu) | ||
287 | return 0; | ||
288 | |||
289 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | ||
290 | } | ||
291 | |||
292 | static int | ||
293 | validate_group(struct perf_event *event) | ||
294 | { | ||
295 | struct perf_event *sibling, *leader = event->group_leader; | ||
296 | struct cpu_hw_events fake_pmu; | ||
297 | |||
298 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | ||
299 | |||
300 | if (!validate_event(&fake_pmu, leader)) | ||
301 | return -ENOSPC; | ||
302 | |||
303 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | ||
304 | if (!validate_event(&fake_pmu, sibling)) | ||
305 | return -ENOSPC; | ||
306 | } | ||
307 | |||
308 | if (!validate_event(&fake_pmu, event)) | ||
309 | return -ENOSPC; | ||
310 | |||
311 | return 0; | ||
312 | } | ||
313 | |||
314 | static int | ||
315 | armpmu_reserve_hardware(void) | ||
316 | { | ||
317 | int i; | ||
318 | int err; | ||
319 | |||
320 | pmu_irqs = reserve_pmu(); | ||
321 | if (IS_ERR(pmu_irqs)) { | ||
322 | pr_warning("unable to reserve pmu\n"); | ||
323 | return PTR_ERR(pmu_irqs); | ||
324 | } | ||
325 | |||
326 | init_pmu(); | ||
327 | |||
328 | if (pmu_irqs->num_irqs < 1) { | ||
329 | pr_err("no irqs for PMUs defined\n"); | ||
330 | return -ENODEV; | ||
331 | } | ||
332 | |||
333 | for (i = 0; i < pmu_irqs->num_irqs; ++i) { | ||
334 | err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq, | ||
335 | IRQF_DISABLED, "armpmu", NULL); | ||
336 | if (err) { | ||
337 | pr_warning("unable to request IRQ%d for ARM " | ||
338 | "perf counters\n", pmu_irqs->irqs[i]); | ||
339 | break; | ||
340 | } | ||
341 | } | ||
342 | |||
343 | if (err) { | ||
344 | for (i = i - 1; i >= 0; --i) | ||
345 | free_irq(pmu_irqs->irqs[i], NULL); | ||
346 | release_pmu(pmu_irqs); | ||
347 | pmu_irqs = NULL; | ||
348 | } | ||
349 | |||
350 | return err; | ||
351 | } | ||
352 | |||
353 | static void | ||
354 | armpmu_release_hardware(void) | ||
355 | { | ||
356 | int i; | ||
357 | |||
358 | for (i = pmu_irqs->num_irqs - 1; i >= 0; --i) | ||
359 | free_irq(pmu_irqs->irqs[i], NULL); | ||
360 | armpmu->stop(); | ||
361 | |||
362 | release_pmu(pmu_irqs); | ||
363 | pmu_irqs = NULL; | ||
364 | } | ||
365 | |||
366 | static atomic_t active_events = ATOMIC_INIT(0); | ||
367 | static DEFINE_MUTEX(pmu_reserve_mutex); | ||
368 | |||
369 | static void | ||
370 | hw_perf_event_destroy(struct perf_event *event) | ||
371 | { | ||
372 | if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) { | ||
373 | armpmu_release_hardware(); | ||
374 | mutex_unlock(&pmu_reserve_mutex); | ||
375 | } | ||
376 | } | ||
377 | |||
378 | static int | ||
379 | __hw_perf_event_init(struct perf_event *event) | ||
380 | { | ||
381 | struct hw_perf_event *hwc = &event->hw; | ||
382 | int mapping, err; | ||
383 | |||
384 | /* Decode the generic type into an ARM event identifier. */ | ||
385 | if (PERF_TYPE_HARDWARE == event->attr.type) { | ||
386 | mapping = armpmu->event_map(event->attr.config); | ||
387 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { | ||
388 | mapping = armpmu_map_cache_event(event->attr.config); | ||
389 | } else if (PERF_TYPE_RAW == event->attr.type) { | ||
390 | mapping = armpmu->raw_event(event->attr.config); | ||
391 | } else { | ||
392 | pr_debug("event type %x not supported\n", event->attr.type); | ||
393 | return -EOPNOTSUPP; | ||
394 | } | ||
395 | |||
396 | if (mapping < 0) { | ||
397 | pr_debug("event %x:%llx not supported\n", event->attr.type, | ||
398 | event->attr.config); | ||
399 | return mapping; | ||
400 | } | ||
401 | |||
402 | /* | ||
403 | * Check whether we need to exclude the counter from certain modes. | ||
404 | * The ARM performance counters are on all of the time so if someone | ||
405 | * has asked us for some excludes then we have to fail. | ||
406 | */ | ||
407 | if (event->attr.exclude_kernel || event->attr.exclude_user || | ||
408 | event->attr.exclude_hv || event->attr.exclude_idle) { | ||
409 | pr_debug("ARM performance counters do not support " | ||
410 | "mode exclusion\n"); | ||
411 | return -EPERM; | ||
412 | } | ||
413 | |||
414 | /* | ||
415 | * We don't assign an index until we actually place the event onto | ||
416 | * hardware. Use -1 to signify that we haven't decided where to put it | ||
417 | * yet. For SMP systems, each core has it's own PMU so we can't do any | ||
418 | * clever allocation or constraints checking at this point. | ||
419 | */ | ||
420 | hwc->idx = -1; | ||
421 | |||
422 | /* | ||
423 | * Store the event encoding into the config_base field. config and | ||
424 | * event_base are unused as the only 2 things we need to know are | ||
425 | * the event mapping and the counter to use. The counter to use is | ||
426 | * also the indx and the config_base is the event type. | ||
427 | */ | ||
428 | hwc->config_base = (unsigned long)mapping; | ||
429 | hwc->config = 0; | ||
430 | hwc->event_base = 0; | ||
431 | |||
432 | if (!hwc->sample_period) { | ||
433 | hwc->sample_period = armpmu->max_period; | ||
434 | hwc->last_period = hwc->sample_period; | ||
435 | atomic64_set(&hwc->period_left, hwc->sample_period); | ||
436 | } | ||
437 | |||
438 | err = 0; | ||
439 | if (event->group_leader != event) { | ||
440 | err = validate_group(event); | ||
441 | if (err) | ||
442 | return -EINVAL; | ||
443 | } | ||
444 | |||
445 | return err; | ||
446 | } | ||
447 | |||
448 | const struct pmu * | ||
449 | hw_perf_event_init(struct perf_event *event) | ||
450 | { | ||
451 | int err = 0; | ||
452 | |||
453 | if (!armpmu) | ||
454 | return ERR_PTR(-ENODEV); | ||
455 | |||
456 | event->destroy = hw_perf_event_destroy; | ||
457 | |||
458 | if (!atomic_inc_not_zero(&active_events)) { | ||
459 | if (atomic_read(&active_events) > perf_max_events) { | ||
460 | atomic_dec(&active_events); | ||
461 | return ERR_PTR(-ENOSPC); | ||
462 | } | ||
463 | |||
464 | mutex_lock(&pmu_reserve_mutex); | ||
465 | if (atomic_read(&active_events) == 0) { | ||
466 | err = armpmu_reserve_hardware(); | ||
467 | } | ||
468 | |||
469 | if (!err) | ||
470 | atomic_inc(&active_events); | ||
471 | mutex_unlock(&pmu_reserve_mutex); | ||
472 | } | ||
473 | |||
474 | if (err) | ||
475 | return ERR_PTR(err); | ||
476 | |||
477 | err = __hw_perf_event_init(event); | ||
478 | if (err) | ||
479 | hw_perf_event_destroy(event); | ||
480 | |||
481 | return err ? ERR_PTR(err) : &pmu; | ||
482 | } | ||
483 | |||
484 | void | ||
485 | hw_perf_enable(void) | ||
486 | { | ||
487 | /* Enable all of the perf events on hardware. */ | ||
488 | int idx; | ||
489 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
490 | |||
491 | if (!armpmu) | ||
492 | return; | ||
493 | |||
494 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
495 | struct perf_event *event = cpuc->events[idx]; | ||
496 | |||
497 | if (!event) | ||
498 | continue; | ||
499 | |||
500 | armpmu->enable(&event->hw, idx); | ||
501 | } | ||
502 | |||
503 | armpmu->start(); | ||
504 | } | ||
505 | |||
506 | void | ||
507 | hw_perf_disable(void) | ||
508 | { | ||
509 | if (armpmu) | ||
510 | armpmu->stop(); | ||
511 | } | ||
512 | |||
513 | /* | ||
514 | * ARMv6 Performance counter handling code. | ||
515 | * | ||
516 | * ARMv6 has 2 configurable performance counters and a single cycle counter. | ||
517 | * They all share a single reset bit but can be written to zero so we can use | ||
518 | * that for a reset. | ||
519 | * | ||
520 | * The counters can't be individually enabled or disabled so when we remove | ||
521 | * one event and replace it with another we could get spurious counts from the | ||
522 | * wrong event. However, we can take advantage of the fact that the | ||
523 | * performance counters can export events to the event bus, and the event bus | ||
524 | * itself can be monitored. This requires that we *don't* export the events to | ||
525 | * the event bus. The procedure for disabling a configurable counter is: | ||
526 | * - change the counter to count the ETMEXTOUT[0] signal (0x20). This | ||
527 | * effectively stops the counter from counting. | ||
528 | * - disable the counter's interrupt generation (each counter has it's | ||
529 | * own interrupt enable bit). | ||
530 | * Once stopped, the counter value can be written as 0 to reset. | ||
531 | * | ||
532 | * To enable a counter: | ||
533 | * - enable the counter's interrupt generation. | ||
534 | * - set the new event type. | ||
535 | * | ||
536 | * Note: the dedicated cycle counter only counts cycles and can't be | ||
537 | * enabled/disabled independently of the others. When we want to disable the | ||
538 | * cycle counter, we have to just disable the interrupt reporting and start | ||
539 | * ignoring that counter. When re-enabling, we have to reset the value and | ||
540 | * enable the interrupt. | ||
541 | */ | ||
542 | |||
543 | enum armv6_perf_types { | ||
544 | ARMV6_PERFCTR_ICACHE_MISS = 0x0, | ||
545 | ARMV6_PERFCTR_IBUF_STALL = 0x1, | ||
546 | ARMV6_PERFCTR_DDEP_STALL = 0x2, | ||
547 | ARMV6_PERFCTR_ITLB_MISS = 0x3, | ||
548 | ARMV6_PERFCTR_DTLB_MISS = 0x4, | ||
549 | ARMV6_PERFCTR_BR_EXEC = 0x5, | ||
550 | ARMV6_PERFCTR_BR_MISPREDICT = 0x6, | ||
551 | ARMV6_PERFCTR_INSTR_EXEC = 0x7, | ||
552 | ARMV6_PERFCTR_DCACHE_HIT = 0x9, | ||
553 | ARMV6_PERFCTR_DCACHE_ACCESS = 0xA, | ||
554 | ARMV6_PERFCTR_DCACHE_MISS = 0xB, | ||
555 | ARMV6_PERFCTR_DCACHE_WBACK = 0xC, | ||
556 | ARMV6_PERFCTR_SW_PC_CHANGE = 0xD, | ||
557 | ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF, | ||
558 | ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10, | ||
559 | ARMV6_PERFCTR_LSU_FULL_STALL = 0x11, | ||
560 | ARMV6_PERFCTR_WBUF_DRAINED = 0x12, | ||
561 | ARMV6_PERFCTR_CPU_CYCLES = 0xFF, | ||
562 | ARMV6_PERFCTR_NOP = 0x20, | ||
563 | }; | ||
564 | |||
565 | enum armv6_counters { | ||
566 | ARMV6_CYCLE_COUNTER = 1, | ||
567 | ARMV6_COUNTER0, | ||
568 | ARMV6_COUNTER1, | ||
569 | }; | ||
570 | |||
571 | /* | ||
572 | * The hardware events that we support. We do support cache operations but | ||
573 | * we have harvard caches and no way to combine instruction and data | ||
574 | * accesses/misses in hardware. | ||
575 | */ | ||
576 | static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { | ||
577 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, | ||
578 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, | ||
579 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
580 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
581 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, | ||
582 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, | ||
583 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
584 | }; | ||
585 | |||
586 | static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
587 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
588 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
589 | [C(L1D)] = { | ||
590 | /* | ||
591 | * The performance counters don't differentiate between read | ||
592 | * and write accesses/misses so this isn't strictly correct, | ||
593 | * but it's the best we can do. Writes and reads get | ||
594 | * combined. | ||
595 | */ | ||
596 | [C(OP_READ)] = { | ||
597 | [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, | ||
598 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, | ||
599 | }, | ||
600 | [C(OP_WRITE)] = { | ||
601 | [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, | ||
602 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, | ||
603 | }, | ||
604 | [C(OP_PREFETCH)] = { | ||
605 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
606 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
607 | }, | ||
608 | }, | ||
609 | [C(L1I)] = { | ||
610 | [C(OP_READ)] = { | ||
611 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
612 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, | ||
613 | }, | ||
614 | [C(OP_WRITE)] = { | ||
615 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
616 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, | ||
617 | }, | ||
618 | [C(OP_PREFETCH)] = { | ||
619 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
620 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
621 | }, | ||
622 | }, | ||
623 | [C(LL)] = { | ||
624 | [C(OP_READ)] = { | ||
625 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
626 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
627 | }, | ||
628 | [C(OP_WRITE)] = { | ||
629 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
630 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
631 | }, | ||
632 | [C(OP_PREFETCH)] = { | ||
633 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
634 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
635 | }, | ||
636 | }, | ||
637 | [C(DTLB)] = { | ||
638 | /* | ||
639 | * The ARM performance counters can count micro DTLB misses, | ||
640 | * micro ITLB misses and main TLB misses. There isn't an event | ||
641 | * for TLB misses, so use the micro misses here and if users | ||
642 | * want the main TLB misses they can use a raw counter. | ||
643 | */ | ||
644 | [C(OP_READ)] = { | ||
645 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
646 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, | ||
647 | }, | ||
648 | [C(OP_WRITE)] = { | ||
649 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
650 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, | ||
651 | }, | ||
652 | [C(OP_PREFETCH)] = { | ||
653 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
654 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
655 | }, | ||
656 | }, | ||
657 | [C(ITLB)] = { | ||
658 | [C(OP_READ)] = { | ||
659 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
660 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, | ||
661 | }, | ||
662 | [C(OP_WRITE)] = { | ||
663 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
664 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, | ||
665 | }, | ||
666 | [C(OP_PREFETCH)] = { | ||
667 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
668 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
669 | }, | ||
670 | }, | ||
671 | [C(BPU)] = { | ||
672 | [C(OP_READ)] = { | ||
673 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
674 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
675 | }, | ||
676 | [C(OP_WRITE)] = { | ||
677 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
678 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
679 | }, | ||
680 | [C(OP_PREFETCH)] = { | ||
681 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
682 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
683 | }, | ||
684 | }, | ||
685 | }; | ||
686 | |||
687 | enum armv6mpcore_perf_types { | ||
688 | ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0, | ||
689 | ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1, | ||
690 | ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2, | ||
691 | ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3, | ||
692 | ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4, | ||
693 | ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5, | ||
694 | ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6, | ||
695 | ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7, | ||
696 | ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8, | ||
697 | ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA, | ||
698 | ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB, | ||
699 | ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC, | ||
700 | ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD, | ||
701 | ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE, | ||
702 | ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF, | ||
703 | ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10, | ||
704 | ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11, | ||
705 | ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12, | ||
706 | ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13, | ||
707 | ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF, | ||
708 | }; | ||
709 | |||
710 | /* | ||
711 | * The hardware events that we support. We do support cache operations but | ||
712 | * we have harvard caches and no way to combine instruction and data | ||
713 | * accesses/misses in hardware. | ||
714 | */ | ||
715 | static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { | ||
716 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, | ||
717 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, | ||
718 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
719 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
720 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, | ||
721 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, | ||
722 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
723 | }; | ||
724 | |||
725 | static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
726 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
727 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
728 | [C(L1D)] = { | ||
729 | [C(OP_READ)] = { | ||
730 | [C(RESULT_ACCESS)] = | ||
731 | ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, | ||
732 | [C(RESULT_MISS)] = | ||
733 | ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, | ||
734 | }, | ||
735 | [C(OP_WRITE)] = { | ||
736 | [C(RESULT_ACCESS)] = | ||
737 | ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, | ||
738 | [C(RESULT_MISS)] = | ||
739 | ARMV6MPCORE_PERFCTR_DCACHE_WRMISS, | ||
740 | }, | ||
741 | [C(OP_PREFETCH)] = { | ||
742 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
743 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
744 | }, | ||
745 | }, | ||
746 | [C(L1I)] = { | ||
747 | [C(OP_READ)] = { | ||
748 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
749 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, | ||
750 | }, | ||
751 | [C(OP_WRITE)] = { | ||
752 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
753 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, | ||
754 | }, | ||
755 | [C(OP_PREFETCH)] = { | ||
756 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
757 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
758 | }, | ||
759 | }, | ||
760 | [C(LL)] = { | ||
761 | [C(OP_READ)] = { | ||
762 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
763 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
764 | }, | ||
765 | [C(OP_WRITE)] = { | ||
766 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
767 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
768 | }, | ||
769 | [C(OP_PREFETCH)] = { | ||
770 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
771 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
772 | }, | ||
773 | }, | ||
774 | [C(DTLB)] = { | ||
775 | /* | ||
776 | * The ARM performance counters can count micro DTLB misses, | ||
777 | * micro ITLB misses and main TLB misses. There isn't an event | ||
778 | * for TLB misses, so use the micro misses here and if users | ||
779 | * want the main TLB misses they can use a raw counter. | ||
780 | */ | ||
781 | [C(OP_READ)] = { | ||
782 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
783 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, | ||
784 | }, | ||
785 | [C(OP_WRITE)] = { | ||
786 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
787 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, | ||
788 | }, | ||
789 | [C(OP_PREFETCH)] = { | ||
790 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
791 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
792 | }, | ||
793 | }, | ||
794 | [C(ITLB)] = { | ||
795 | [C(OP_READ)] = { | ||
796 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
797 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, | ||
798 | }, | ||
799 | [C(OP_WRITE)] = { | ||
800 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
801 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, | ||
802 | }, | ||
803 | [C(OP_PREFETCH)] = { | ||
804 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
805 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
806 | }, | ||
807 | }, | ||
808 | [C(BPU)] = { | ||
809 | [C(OP_READ)] = { | ||
810 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
811 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
812 | }, | ||
813 | [C(OP_WRITE)] = { | ||
814 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
815 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
816 | }, | ||
817 | [C(OP_PREFETCH)] = { | ||
818 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
819 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
820 | }, | ||
821 | }, | ||
822 | }; | ||
823 | |||
824 | static inline unsigned long | ||
825 | armv6_pmcr_read(void) | ||
826 | { | ||
827 | u32 val; | ||
828 | asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); | ||
829 | return val; | ||
830 | } | ||
831 | |||
832 | static inline void | ||
833 | armv6_pmcr_write(unsigned long val) | ||
834 | { | ||
835 | asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); | ||
836 | } | ||
837 | |||
838 | #define ARMV6_PMCR_ENABLE (1 << 0) | ||
839 | #define ARMV6_PMCR_CTR01_RESET (1 << 1) | ||
840 | #define ARMV6_PMCR_CCOUNT_RESET (1 << 2) | ||
841 | #define ARMV6_PMCR_CCOUNT_DIV (1 << 3) | ||
842 | #define ARMV6_PMCR_COUNT0_IEN (1 << 4) | ||
843 | #define ARMV6_PMCR_COUNT1_IEN (1 << 5) | ||
844 | #define ARMV6_PMCR_CCOUNT_IEN (1 << 6) | ||
845 | #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8) | ||
846 | #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9) | ||
847 | #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10) | ||
848 | #define ARMV6_PMCR_EVT_COUNT0_SHIFT 20 | ||
849 | #define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT) | ||
850 | #define ARMV6_PMCR_EVT_COUNT1_SHIFT 12 | ||
851 | #define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT) | ||
852 | |||
853 | #define ARMV6_PMCR_OVERFLOWED_MASK \ | ||
854 | (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \ | ||
855 | ARMV6_PMCR_CCOUNT_OVERFLOW) | ||
856 | |||
857 | static inline int | ||
858 | armv6_pmcr_has_overflowed(unsigned long pmcr) | ||
859 | { | ||
860 | return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK); | ||
861 | } | ||
862 | |||
863 | static inline int | ||
864 | armv6_pmcr_counter_has_overflowed(unsigned long pmcr, | ||
865 | enum armv6_counters counter) | ||
866 | { | ||
867 | int ret = 0; | ||
868 | |||
869 | if (ARMV6_CYCLE_COUNTER == counter) | ||
870 | ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW; | ||
871 | else if (ARMV6_COUNTER0 == counter) | ||
872 | ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW; | ||
873 | else if (ARMV6_COUNTER1 == counter) | ||
874 | ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW; | ||
875 | else | ||
876 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
877 | |||
878 | return ret; | ||
879 | } | ||
880 | |||
881 | static inline u32 | ||
882 | armv6pmu_read_counter(int counter) | ||
883 | { | ||
884 | unsigned long value = 0; | ||
885 | |||
886 | if (ARMV6_CYCLE_COUNTER == counter) | ||
887 | asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); | ||
888 | else if (ARMV6_COUNTER0 == counter) | ||
889 | asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); | ||
890 | else if (ARMV6_COUNTER1 == counter) | ||
891 | asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); | ||
892 | else | ||
893 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
894 | |||
895 | return value; | ||
896 | } | ||
897 | |||
898 | static inline void | ||
899 | armv6pmu_write_counter(int counter, | ||
900 | u32 value) | ||
901 | { | ||
902 | if (ARMV6_CYCLE_COUNTER == counter) | ||
903 | asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); | ||
904 | else if (ARMV6_COUNTER0 == counter) | ||
905 | asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); | ||
906 | else if (ARMV6_COUNTER1 == counter) | ||
907 | asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); | ||
908 | else | ||
909 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
910 | } | ||
911 | |||
912 | void | ||
913 | armv6pmu_enable_event(struct hw_perf_event *hwc, | ||
914 | int idx) | ||
915 | { | ||
916 | unsigned long val, mask, evt, flags; | ||
917 | |||
918 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
919 | mask = 0; | ||
920 | evt = ARMV6_PMCR_CCOUNT_IEN; | ||
921 | } else if (ARMV6_COUNTER0 == idx) { | ||
922 | mask = ARMV6_PMCR_EVT_COUNT0_MASK; | ||
923 | evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | | ||
924 | ARMV6_PMCR_COUNT0_IEN; | ||
925 | } else if (ARMV6_COUNTER1 == idx) { | ||
926 | mask = ARMV6_PMCR_EVT_COUNT1_MASK; | ||
927 | evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | | ||
928 | ARMV6_PMCR_COUNT1_IEN; | ||
929 | } else { | ||
930 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
931 | return; | ||
932 | } | ||
933 | |||
934 | /* | ||
935 | * Mask out the current event and set the counter to count the event | ||
936 | * that we're interested in. | ||
937 | */ | ||
938 | spin_lock_irqsave(&pmu_lock, flags); | ||
939 | val = armv6_pmcr_read(); | ||
940 | val &= ~mask; | ||
941 | val |= evt; | ||
942 | armv6_pmcr_write(val); | ||
943 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
944 | } | ||
945 | |||
946 | static irqreturn_t | ||
947 | armv6pmu_handle_irq(int irq_num, | ||
948 | void *dev) | ||
949 | { | ||
950 | unsigned long pmcr = armv6_pmcr_read(); | ||
951 | struct perf_sample_data data; | ||
952 | struct cpu_hw_events *cpuc; | ||
953 | struct pt_regs *regs; | ||
954 | int idx; | ||
955 | |||
956 | if (!armv6_pmcr_has_overflowed(pmcr)) | ||
957 | return IRQ_NONE; | ||
958 | |||
959 | regs = get_irq_regs(); | ||
960 | |||
961 | /* | ||
962 | * The interrupts are cleared by writing the overflow flags back to | ||
963 | * the control register. All of the other bits don't have any effect | ||
964 | * if they are rewritten, so write the whole value back. | ||
965 | */ | ||
966 | armv6_pmcr_write(pmcr); | ||
967 | |||
968 | data.addr = 0; | ||
969 | |||
970 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
971 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
972 | struct perf_event *event = cpuc->events[idx]; | ||
973 | struct hw_perf_event *hwc; | ||
974 | |||
975 | if (!test_bit(idx, cpuc->active_mask)) | ||
976 | continue; | ||
977 | |||
978 | /* | ||
979 | * We have a single interrupt for all counters. Check that | ||
980 | * each counter has overflowed before we process it. | ||
981 | */ | ||
982 | if (!armv6_pmcr_counter_has_overflowed(pmcr, idx)) | ||
983 | continue; | ||
984 | |||
985 | hwc = &event->hw; | ||
986 | armpmu_event_update(event, hwc, idx); | ||
987 | data.period = event->hw.last_period; | ||
988 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
989 | continue; | ||
990 | |||
991 | if (perf_event_overflow(event, 0, &data, regs)) | ||
992 | armpmu->disable(hwc, idx); | ||
993 | } | ||
994 | |||
995 | /* | ||
996 | * Handle the pending perf events. | ||
997 | * | ||
998 | * Note: this call *must* be run with interrupts enabled. For | ||
999 | * platforms that can have the PMU interrupts raised as a PMI, this | ||
1000 | * will not work. | ||
1001 | */ | ||
1002 | perf_event_do_pending(); | ||
1003 | |||
1004 | return IRQ_HANDLED; | ||
1005 | } | ||
1006 | |||
1007 | static void | ||
1008 | armv6pmu_start(void) | ||
1009 | { | ||
1010 | unsigned long flags, val; | ||
1011 | |||
1012 | spin_lock_irqsave(&pmu_lock, flags); | ||
1013 | val = armv6_pmcr_read(); | ||
1014 | val |= ARMV6_PMCR_ENABLE; | ||
1015 | armv6_pmcr_write(val); | ||
1016 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1017 | } | ||
1018 | |||
1019 | void | ||
1020 | armv6pmu_stop(void) | ||
1021 | { | ||
1022 | unsigned long flags, val; | ||
1023 | |||
1024 | spin_lock_irqsave(&pmu_lock, flags); | ||
1025 | val = armv6_pmcr_read(); | ||
1026 | val &= ~ARMV6_PMCR_ENABLE; | ||
1027 | armv6_pmcr_write(val); | ||
1028 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1029 | } | ||
1030 | |||
1031 | static inline int | ||
1032 | armv6pmu_event_map(int config) | ||
1033 | { | ||
1034 | int mapping = armv6_perf_map[config]; | ||
1035 | if (HW_OP_UNSUPPORTED == mapping) | ||
1036 | mapping = -EOPNOTSUPP; | ||
1037 | return mapping; | ||
1038 | } | ||
1039 | |||
1040 | static inline int | ||
1041 | armv6mpcore_pmu_event_map(int config) | ||
1042 | { | ||
1043 | int mapping = armv6mpcore_perf_map[config]; | ||
1044 | if (HW_OP_UNSUPPORTED == mapping) | ||
1045 | mapping = -EOPNOTSUPP; | ||
1046 | return mapping; | ||
1047 | } | ||
1048 | |||
1049 | static u64 | ||
1050 | armv6pmu_raw_event(u64 config) | ||
1051 | { | ||
1052 | return config & 0xff; | ||
1053 | } | ||
1054 | |||
1055 | static int | ||
1056 | armv6pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
1057 | struct hw_perf_event *event) | ||
1058 | { | ||
1059 | /* Always place a cycle counter into the cycle counter. */ | ||
1060 | if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) { | ||
1061 | if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) | ||
1062 | return -EAGAIN; | ||
1063 | |||
1064 | return ARMV6_CYCLE_COUNTER; | ||
1065 | } else { | ||
1066 | /* | ||
1067 | * For anything other than a cycle counter, try and use | ||
1068 | * counter0 and counter1. | ||
1069 | */ | ||
1070 | if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) { | ||
1071 | return ARMV6_COUNTER1; | ||
1072 | } | ||
1073 | |||
1074 | if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) { | ||
1075 | return ARMV6_COUNTER0; | ||
1076 | } | ||
1077 | |||
1078 | /* The counters are all in use. */ | ||
1079 | return -EAGAIN; | ||
1080 | } | ||
1081 | } | ||
1082 | |||
1083 | static void | ||
1084 | armv6pmu_disable_event(struct hw_perf_event *hwc, | ||
1085 | int idx) | ||
1086 | { | ||
1087 | unsigned long val, mask, evt, flags; | ||
1088 | |||
1089 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
1090 | mask = ARMV6_PMCR_CCOUNT_IEN; | ||
1091 | evt = 0; | ||
1092 | } else if (ARMV6_COUNTER0 == idx) { | ||
1093 | mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK; | ||
1094 | evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT; | ||
1095 | } else if (ARMV6_COUNTER1 == idx) { | ||
1096 | mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK; | ||
1097 | evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT; | ||
1098 | } else { | ||
1099 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
1100 | return; | ||
1101 | } | ||
1102 | |||
1103 | /* | ||
1104 | * Mask out the current event and set the counter to count the number | ||
1105 | * of ETM bus signal assertion cycles. The external reporting should | ||
1106 | * be disabled and so this should never increment. | ||
1107 | */ | ||
1108 | spin_lock_irqsave(&pmu_lock, flags); | ||
1109 | val = armv6_pmcr_read(); | ||
1110 | val &= ~mask; | ||
1111 | val |= evt; | ||
1112 | armv6_pmcr_write(val); | ||
1113 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1114 | } | ||
1115 | |||
1116 | static void | ||
1117 | armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, | ||
1118 | int idx) | ||
1119 | { | ||
1120 | unsigned long val, mask, flags, evt = 0; | ||
1121 | |||
1122 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
1123 | mask = ARMV6_PMCR_CCOUNT_IEN; | ||
1124 | } else if (ARMV6_COUNTER0 == idx) { | ||
1125 | mask = ARMV6_PMCR_COUNT0_IEN; | ||
1126 | } else if (ARMV6_COUNTER1 == idx) { | ||
1127 | mask = ARMV6_PMCR_COUNT1_IEN; | ||
1128 | } else { | ||
1129 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
1130 | return; | ||
1131 | } | ||
1132 | |||
1133 | /* | ||
1134 | * Unlike UP ARMv6, we don't have a way of stopping the counters. We | ||
1135 | * simply disable the interrupt reporting. | ||
1136 | */ | ||
1137 | spin_lock_irqsave(&pmu_lock, flags); | ||
1138 | val = armv6_pmcr_read(); | ||
1139 | val &= ~mask; | ||
1140 | val |= evt; | ||
1141 | armv6_pmcr_write(val); | ||
1142 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1143 | } | ||
1144 | |||
1145 | static const struct arm_pmu armv6pmu = { | ||
1146 | .name = "v6", | ||
1147 | .handle_irq = armv6pmu_handle_irq, | ||
1148 | .enable = armv6pmu_enable_event, | ||
1149 | .disable = armv6pmu_disable_event, | ||
1150 | .event_map = armv6pmu_event_map, | ||
1151 | .raw_event = armv6pmu_raw_event, | ||
1152 | .read_counter = armv6pmu_read_counter, | ||
1153 | .write_counter = armv6pmu_write_counter, | ||
1154 | .get_event_idx = armv6pmu_get_event_idx, | ||
1155 | .start = armv6pmu_start, | ||
1156 | .stop = armv6pmu_stop, | ||
1157 | .num_events = 3, | ||
1158 | .max_period = (1LLU << 32) - 1, | ||
1159 | }; | ||
1160 | |||
1161 | /* | ||
1162 | * ARMv6mpcore is almost identical to single core ARMv6 with the exception | ||
1163 | * that some of the events have different enumerations and that there is no | ||
1164 | * *hack* to stop the programmable counters. To stop the counters we simply | ||
1165 | * disable the interrupt reporting and update the event. When unthrottling we | ||
1166 | * reset the period and enable the interrupt reporting. | ||
1167 | */ | ||
1168 | static const struct arm_pmu armv6mpcore_pmu = { | ||
1169 | .name = "v6mpcore", | ||
1170 | .handle_irq = armv6pmu_handle_irq, | ||
1171 | .enable = armv6pmu_enable_event, | ||
1172 | .disable = armv6mpcore_pmu_disable_event, | ||
1173 | .event_map = armv6mpcore_pmu_event_map, | ||
1174 | .raw_event = armv6pmu_raw_event, | ||
1175 | .read_counter = armv6pmu_read_counter, | ||
1176 | .write_counter = armv6pmu_write_counter, | ||
1177 | .get_event_idx = armv6pmu_get_event_idx, | ||
1178 | .start = armv6pmu_start, | ||
1179 | .stop = armv6pmu_stop, | ||
1180 | .num_events = 3, | ||
1181 | .max_period = (1LLU << 32) - 1, | ||
1182 | }; | ||
1183 | |||
1184 | /* | ||
1185 | * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. | ||
1186 | * | ||
1187 | * Copied from ARMv6 code, with the low level code inspired | ||
1188 | * by the ARMv7 Oprofile code. | ||
1189 | * | ||
1190 | * Cortex-A8 has up to 4 configurable performance counters and | ||
1191 | * a single cycle counter. | ||
1192 | * Cortex-A9 has up to 31 configurable performance counters and | ||
1193 | * a single cycle counter. | ||
1194 | * | ||
1195 | * All counters can be enabled/disabled and IRQ masked separately. The cycle | ||
1196 | * counter and all 4 performance counters together can be reset separately. | ||
1197 | */ | ||
1198 | |||
1199 | #define ARMV7_PMU_CORTEX_A8_NAME "ARMv7 Cortex-A8" | ||
1200 | |||
1201 | #define ARMV7_PMU_CORTEX_A9_NAME "ARMv7 Cortex-A9" | ||
1202 | |||
1203 | /* Common ARMv7 event types */ | ||
1204 | enum armv7_perf_types { | ||
1205 | ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, | ||
1206 | ARMV7_PERFCTR_IFETCH_MISS = 0x01, | ||
1207 | ARMV7_PERFCTR_ITLB_MISS = 0x02, | ||
1208 | ARMV7_PERFCTR_DCACHE_REFILL = 0x03, | ||
1209 | ARMV7_PERFCTR_DCACHE_ACCESS = 0x04, | ||
1210 | ARMV7_PERFCTR_DTLB_REFILL = 0x05, | ||
1211 | ARMV7_PERFCTR_DREAD = 0x06, | ||
1212 | ARMV7_PERFCTR_DWRITE = 0x07, | ||
1213 | |||
1214 | ARMV7_PERFCTR_EXC_TAKEN = 0x09, | ||
1215 | ARMV7_PERFCTR_EXC_EXECUTED = 0x0A, | ||
1216 | ARMV7_PERFCTR_CID_WRITE = 0x0B, | ||
1217 | /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. | ||
1218 | * It counts: | ||
1219 | * - all branch instructions, | ||
1220 | * - instructions that explicitly write the PC, | ||
1221 | * - exception generating instructions. | ||
1222 | */ | ||
1223 | ARMV7_PERFCTR_PC_WRITE = 0x0C, | ||
1224 | ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D, | ||
1225 | ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F, | ||
1226 | ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10, | ||
1227 | ARMV7_PERFCTR_CLOCK_CYCLES = 0x11, | ||
1228 | |||
1229 | ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12, | ||
1230 | |||
1231 | ARMV7_PERFCTR_CPU_CYCLES = 0xFF | ||
1232 | }; | ||
1233 | |||
1234 | /* ARMv7 Cortex-A8 specific event types */ | ||
1235 | enum armv7_a8_perf_types { | ||
1236 | ARMV7_PERFCTR_INSTR_EXECUTED = 0x08, | ||
1237 | |||
1238 | ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E, | ||
1239 | |||
1240 | ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40, | ||
1241 | ARMV7_PERFCTR_L2_STORE_MERGED = 0x41, | ||
1242 | ARMV7_PERFCTR_L2_STORE_BUFF = 0x42, | ||
1243 | ARMV7_PERFCTR_L2_ACCESS = 0x43, | ||
1244 | ARMV7_PERFCTR_L2_CACH_MISS = 0x44, | ||
1245 | ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45, | ||
1246 | ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46, | ||
1247 | ARMV7_PERFCTR_MEMORY_REPLAY = 0x47, | ||
1248 | ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48, | ||
1249 | ARMV7_PERFCTR_L1_DATA_MISS = 0x49, | ||
1250 | ARMV7_PERFCTR_L1_INST_MISS = 0x4A, | ||
1251 | ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B, | ||
1252 | ARMV7_PERFCTR_L1_NEON_DATA = 0x4C, | ||
1253 | ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D, | ||
1254 | ARMV7_PERFCTR_L2_NEON = 0x4E, | ||
1255 | ARMV7_PERFCTR_L2_NEON_HIT = 0x4F, | ||
1256 | ARMV7_PERFCTR_L1_INST = 0x50, | ||
1257 | ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51, | ||
1258 | ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52, | ||
1259 | ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53, | ||
1260 | ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54, | ||
1261 | ARMV7_PERFCTR_OP_EXECUTED = 0x55, | ||
1262 | ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56, | ||
1263 | ARMV7_PERFCTR_CYCLES_INST = 0x57, | ||
1264 | ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58, | ||
1265 | ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59, | ||
1266 | ARMV7_PERFCTR_NEON_CYCLES = 0x5A, | ||
1267 | |||
1268 | ARMV7_PERFCTR_PMU0_EVENTS = 0x70, | ||
1269 | ARMV7_PERFCTR_PMU1_EVENTS = 0x71, | ||
1270 | ARMV7_PERFCTR_PMU_EVENTS = 0x72, | ||
1271 | }; | ||
1272 | |||
1273 | /* ARMv7 Cortex-A9 specific event types */ | ||
1274 | enum armv7_a9_perf_types { | ||
1275 | ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40, | ||
1276 | ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41, | ||
1277 | ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42, | ||
1278 | |||
1279 | ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50, | ||
1280 | ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51, | ||
1281 | |||
1282 | ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60, | ||
1283 | ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61, | ||
1284 | ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62, | ||
1285 | ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63, | ||
1286 | ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64, | ||
1287 | ARMV7_PERFCTR_DATA_EVICTION = 0x65, | ||
1288 | ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66, | ||
1289 | ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67, | ||
1290 | ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68, | ||
1291 | |||
1292 | ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E, | ||
1293 | |||
1294 | ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70, | ||
1295 | ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71, | ||
1296 | ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72, | ||
1297 | ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73, | ||
1298 | ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74, | ||
1299 | |||
1300 | ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80, | ||
1301 | ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81, | ||
1302 | ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82, | ||
1303 | ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83, | ||
1304 | ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84, | ||
1305 | ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85, | ||
1306 | ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86, | ||
1307 | |||
1308 | ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A, | ||
1309 | ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B, | ||
1310 | |||
1311 | ARMV7_PERFCTR_ISB_INST = 0x90, | ||
1312 | ARMV7_PERFCTR_DSB_INST = 0x91, | ||
1313 | ARMV7_PERFCTR_DMB_INST = 0x92, | ||
1314 | ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93, | ||
1315 | |||
1316 | ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0, | ||
1317 | ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1, | ||
1318 | ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2, | ||
1319 | ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3, | ||
1320 | ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4, | ||
1321 | ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5 | ||
1322 | }; | ||
1323 | |||
1324 | /* | ||
1325 | * Cortex-A8 HW events mapping | ||
1326 | * | ||
1327 | * The hardware events that we support. We do support cache operations but | ||
1328 | * we have harvard caches and no way to combine instruction and data | ||
1329 | * accesses/misses in hardware. | ||
1330 | */ | ||
1331 | static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { | ||
1332 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
1333 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | ||
1334 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
1335 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
1336 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
1337 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
1338 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, | ||
1339 | }; | ||
1340 | |||
1341 | static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
1342 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
1343 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
1344 | [C(L1D)] = { | ||
1345 | /* | ||
1346 | * The performance counters don't differentiate between read | ||
1347 | * and write accesses/misses so this isn't strictly correct, | ||
1348 | * but it's the best we can do. Writes and reads get | ||
1349 | * combined. | ||
1350 | */ | ||
1351 | [C(OP_READ)] = { | ||
1352 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
1353 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
1354 | }, | ||
1355 | [C(OP_WRITE)] = { | ||
1356 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
1357 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
1358 | }, | ||
1359 | [C(OP_PREFETCH)] = { | ||
1360 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1361 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1362 | }, | ||
1363 | }, | ||
1364 | [C(L1I)] = { | ||
1365 | [C(OP_READ)] = { | ||
1366 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, | ||
1367 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, | ||
1368 | }, | ||
1369 | [C(OP_WRITE)] = { | ||
1370 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, | ||
1371 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, | ||
1372 | }, | ||
1373 | [C(OP_PREFETCH)] = { | ||
1374 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1375 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1376 | }, | ||
1377 | }, | ||
1378 | [C(LL)] = { | ||
1379 | [C(OP_READ)] = { | ||
1380 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, | ||
1381 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, | ||
1382 | }, | ||
1383 | [C(OP_WRITE)] = { | ||
1384 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, | ||
1385 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, | ||
1386 | }, | ||
1387 | [C(OP_PREFETCH)] = { | ||
1388 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1389 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1390 | }, | ||
1391 | }, | ||
1392 | [C(DTLB)] = { | ||
1393 | /* | ||
1394 | * Only ITLB misses and DTLB refills are supported. | ||
1395 | * If users want the DTLB refills misses a raw counter | ||
1396 | * must be used. | ||
1397 | */ | ||
1398 | [C(OP_READ)] = { | ||
1399 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1400 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
1401 | }, | ||
1402 | [C(OP_WRITE)] = { | ||
1403 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1404 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
1405 | }, | ||
1406 | [C(OP_PREFETCH)] = { | ||
1407 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1408 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1409 | }, | ||
1410 | }, | ||
1411 | [C(ITLB)] = { | ||
1412 | [C(OP_READ)] = { | ||
1413 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1414 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
1415 | }, | ||
1416 | [C(OP_WRITE)] = { | ||
1417 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1418 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
1419 | }, | ||
1420 | [C(OP_PREFETCH)] = { | ||
1421 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1422 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1423 | }, | ||
1424 | }, | ||
1425 | [C(BPU)] = { | ||
1426 | [C(OP_READ)] = { | ||
1427 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
1428 | [C(RESULT_MISS)] | ||
1429 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
1430 | }, | ||
1431 | [C(OP_WRITE)] = { | ||
1432 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
1433 | [C(RESULT_MISS)] | ||
1434 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
1435 | }, | ||
1436 | [C(OP_PREFETCH)] = { | ||
1437 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1438 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1439 | }, | ||
1440 | }, | ||
1441 | }; | ||
1442 | |||
1443 | /* | ||
1444 | * Cortex-A9 HW events mapping | ||
1445 | */ | ||
1446 | static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { | ||
1447 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
1448 | [PERF_COUNT_HW_INSTRUCTIONS] = | ||
1449 | ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, | ||
1450 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT, | ||
1451 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS, | ||
1452 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
1453 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
1454 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, | ||
1455 | }; | ||
1456 | |||
1457 | static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
1458 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
1459 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
1460 | [C(L1D)] = { | ||
1461 | /* | ||
1462 | * The performance counters don't differentiate between read | ||
1463 | * and write accesses/misses so this isn't strictly correct, | ||
1464 | * but it's the best we can do. Writes and reads get | ||
1465 | * combined. | ||
1466 | */ | ||
1467 | [C(OP_READ)] = { | ||
1468 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
1469 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
1470 | }, | ||
1471 | [C(OP_WRITE)] = { | ||
1472 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
1473 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
1474 | }, | ||
1475 | [C(OP_PREFETCH)] = { | ||
1476 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1477 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1478 | }, | ||
1479 | }, | ||
1480 | [C(L1I)] = { | ||
1481 | [C(OP_READ)] = { | ||
1482 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1483 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
1484 | }, | ||
1485 | [C(OP_WRITE)] = { | ||
1486 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1487 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
1488 | }, | ||
1489 | [C(OP_PREFETCH)] = { | ||
1490 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1491 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1492 | }, | ||
1493 | }, | ||
1494 | [C(LL)] = { | ||
1495 | [C(OP_READ)] = { | ||
1496 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1497 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1498 | }, | ||
1499 | [C(OP_WRITE)] = { | ||
1500 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1501 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1502 | }, | ||
1503 | [C(OP_PREFETCH)] = { | ||
1504 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1505 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1506 | }, | ||
1507 | }, | ||
1508 | [C(DTLB)] = { | ||
1509 | /* | ||
1510 | * Only ITLB misses and DTLB refills are supported. | ||
1511 | * If users want the DTLB refills misses a raw counter | ||
1512 | * must be used. | ||
1513 | */ | ||
1514 | [C(OP_READ)] = { | ||
1515 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1516 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
1517 | }, | ||
1518 | [C(OP_WRITE)] = { | ||
1519 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1520 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
1521 | }, | ||
1522 | [C(OP_PREFETCH)] = { | ||
1523 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1524 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1525 | }, | ||
1526 | }, | ||
1527 | [C(ITLB)] = { | ||
1528 | [C(OP_READ)] = { | ||
1529 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1530 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
1531 | }, | ||
1532 | [C(OP_WRITE)] = { | ||
1533 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1534 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
1535 | }, | ||
1536 | [C(OP_PREFETCH)] = { | ||
1537 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1538 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1539 | }, | ||
1540 | }, | ||
1541 | [C(BPU)] = { | ||
1542 | [C(OP_READ)] = { | ||
1543 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
1544 | [C(RESULT_MISS)] | ||
1545 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
1546 | }, | ||
1547 | [C(OP_WRITE)] = { | ||
1548 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
1549 | [C(RESULT_MISS)] | ||
1550 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
1551 | }, | ||
1552 | [C(OP_PREFETCH)] = { | ||
1553 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
1554 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
1555 | }, | ||
1556 | }, | ||
1557 | }; | ||
1558 | |||
1559 | /* | ||
1560 | * Perf Events counters | ||
1561 | */ | ||
1562 | enum armv7_counters { | ||
1563 | ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */ | ||
1564 | ARMV7_COUNTER0 = 2, /* First event counter */ | ||
1565 | }; | ||
1566 | |||
1567 | /* | ||
1568 | * The cycle counter is ARMV7_CYCLE_COUNTER. | ||
1569 | * The first event counter is ARMV7_COUNTER0. | ||
1570 | * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1). | ||
1571 | */ | ||
1572 | #define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1) | ||
1573 | |||
1574 | /* | ||
1575 | * ARMv7 low level PMNC access | ||
1576 | */ | ||
1577 | |||
1578 | /* | ||
1579 | * Per-CPU PMNC: config reg | ||
1580 | */ | ||
1581 | #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ | ||
1582 | #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ | ||
1583 | #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ | ||
1584 | #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ | ||
1585 | #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ | ||
1586 | #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ | ||
1587 | #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ | ||
1588 | #define ARMV7_PMNC_N_MASK 0x1f | ||
1589 | #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ | ||
1590 | |||
1591 | /* | ||
1592 | * Available counters | ||
1593 | */ | ||
1594 | #define ARMV7_CNT0 0 /* First event counter */ | ||
1595 | #define ARMV7_CCNT 31 /* Cycle counter */ | ||
1596 | |||
1597 | /* Perf Event to low level counters mapping */ | ||
1598 | #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0) | ||
1599 | |||
1600 | /* | ||
1601 | * CNTENS: counters enable reg | ||
1602 | */ | ||
1603 | #define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
1604 | #define ARMV7_CNTENS_C (1 << ARMV7_CCNT) | ||
1605 | |||
1606 | /* | ||
1607 | * CNTENC: counters disable reg | ||
1608 | */ | ||
1609 | #define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
1610 | #define ARMV7_CNTENC_C (1 << ARMV7_CCNT) | ||
1611 | |||
1612 | /* | ||
1613 | * INTENS: counters overflow interrupt enable reg | ||
1614 | */ | ||
1615 | #define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
1616 | #define ARMV7_INTENS_C (1 << ARMV7_CCNT) | ||
1617 | |||
1618 | /* | ||
1619 | * INTENC: counters overflow interrupt disable reg | ||
1620 | */ | ||
1621 | #define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
1622 | #define ARMV7_INTENC_C (1 << ARMV7_CCNT) | ||
1623 | |||
1624 | /* | ||
1625 | * EVTSEL: Event selection reg | ||
1626 | */ | ||
1627 | #define ARMV7_EVTSEL_MASK 0x7f /* Mask for writable bits */ | ||
1628 | |||
1629 | /* | ||
1630 | * SELECT: Counter selection reg | ||
1631 | */ | ||
1632 | #define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */ | ||
1633 | |||
1634 | /* | ||
1635 | * FLAG: counters overflow flag status reg | ||
1636 | */ | ||
1637 | #define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
1638 | #define ARMV7_FLAG_C (1 << ARMV7_CCNT) | ||
1639 | #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ | ||
1640 | #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK | ||
1641 | |||
1642 | static inline unsigned long armv7_pmnc_read(void) | ||
1643 | { | ||
1644 | u32 val; | ||
1645 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); | ||
1646 | return val; | ||
1647 | } | ||
1648 | |||
1649 | static inline void armv7_pmnc_write(unsigned long val) | ||
1650 | { | ||
1651 | val &= ARMV7_PMNC_MASK; | ||
1652 | asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); | ||
1653 | } | ||
1654 | |||
1655 | static inline int armv7_pmnc_has_overflowed(unsigned long pmnc) | ||
1656 | { | ||
1657 | return pmnc & ARMV7_OVERFLOWED_MASK; | ||
1658 | } | ||
1659 | |||
1660 | static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc, | ||
1661 | enum armv7_counters counter) | ||
1662 | { | ||
1663 | int ret; | ||
1664 | |||
1665 | if (counter == ARMV7_CYCLE_COUNTER) | ||
1666 | ret = pmnc & ARMV7_FLAG_C; | ||
1667 | else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST)) | ||
1668 | ret = pmnc & ARMV7_FLAG_P(counter); | ||
1669 | else | ||
1670 | pr_err("CPU%u checking wrong counter %d overflow status\n", | ||
1671 | smp_processor_id(), counter); | ||
1672 | |||
1673 | return ret; | ||
1674 | } | ||
1675 | |||
1676 | static inline int armv7_pmnc_select_counter(unsigned int idx) | ||
1677 | { | ||
1678 | u32 val; | ||
1679 | |||
1680 | if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) { | ||
1681 | pr_err("CPU%u selecting wrong PMNC counter" | ||
1682 | " %d\n", smp_processor_id(), idx); | ||
1683 | return -1; | ||
1684 | } | ||
1685 | |||
1686 | val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; | ||
1687 | asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); | ||
1688 | |||
1689 | return idx; | ||
1690 | } | ||
1691 | |||
1692 | static inline u32 armv7pmu_read_counter(int idx) | ||
1693 | { | ||
1694 | unsigned long value = 0; | ||
1695 | |||
1696 | if (idx == ARMV7_CYCLE_COUNTER) | ||
1697 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); | ||
1698 | else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) { | ||
1699 | if (armv7_pmnc_select_counter(idx) == idx) | ||
1700 | asm volatile("mrc p15, 0, %0, c9, c13, 2" | ||
1701 | : "=r" (value)); | ||
1702 | } else | ||
1703 | pr_err("CPU%u reading wrong counter %d\n", | ||
1704 | smp_processor_id(), idx); | ||
1705 | |||
1706 | return value; | ||
1707 | } | ||
1708 | |||
1709 | static inline void armv7pmu_write_counter(int idx, u32 value) | ||
1710 | { | ||
1711 | if (idx == ARMV7_CYCLE_COUNTER) | ||
1712 | asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); | ||
1713 | else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) { | ||
1714 | if (armv7_pmnc_select_counter(idx) == idx) | ||
1715 | asm volatile("mcr p15, 0, %0, c9, c13, 2" | ||
1716 | : : "r" (value)); | ||
1717 | } else | ||
1718 | pr_err("CPU%u writing wrong counter %d\n", | ||
1719 | smp_processor_id(), idx); | ||
1720 | } | ||
1721 | |||
1722 | static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val) | ||
1723 | { | ||
1724 | if (armv7_pmnc_select_counter(idx) == idx) { | ||
1725 | val &= ARMV7_EVTSEL_MASK; | ||
1726 | asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); | ||
1727 | } | ||
1728 | } | ||
1729 | |||
1730 | static inline u32 armv7_pmnc_enable_counter(unsigned int idx) | ||
1731 | { | ||
1732 | u32 val; | ||
1733 | |||
1734 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
1735 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
1736 | pr_err("CPU%u enabling wrong PMNC counter" | ||
1737 | " %d\n", smp_processor_id(), idx); | ||
1738 | return -1; | ||
1739 | } | ||
1740 | |||
1741 | if (idx == ARMV7_CYCLE_COUNTER) | ||
1742 | val = ARMV7_CNTENS_C; | ||
1743 | else | ||
1744 | val = ARMV7_CNTENS_P(idx); | ||
1745 | |||
1746 | asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); | ||
1747 | |||
1748 | return idx; | ||
1749 | } | ||
1750 | |||
1751 | static inline u32 armv7_pmnc_disable_counter(unsigned int idx) | ||
1752 | { | ||
1753 | u32 val; | ||
1754 | |||
1755 | |||
1756 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
1757 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
1758 | pr_err("CPU%u disabling wrong PMNC counter" | ||
1759 | " %d\n", smp_processor_id(), idx); | ||
1760 | return -1; | ||
1761 | } | ||
1762 | |||
1763 | if (idx == ARMV7_CYCLE_COUNTER) | ||
1764 | val = ARMV7_CNTENC_C; | ||
1765 | else | ||
1766 | val = ARMV7_CNTENC_P(idx); | ||
1767 | |||
1768 | asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); | ||
1769 | |||
1770 | return idx; | ||
1771 | } | ||
1772 | |||
1773 | static inline u32 armv7_pmnc_enable_intens(unsigned int idx) | ||
1774 | { | ||
1775 | u32 val; | ||
1776 | |||
1777 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
1778 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
1779 | pr_err("CPU%u enabling wrong PMNC counter" | ||
1780 | " interrupt enable %d\n", smp_processor_id(), idx); | ||
1781 | return -1; | ||
1782 | } | ||
1783 | |||
1784 | if (idx == ARMV7_CYCLE_COUNTER) | ||
1785 | val = ARMV7_INTENS_C; | ||
1786 | else | ||
1787 | val = ARMV7_INTENS_P(idx); | ||
1788 | |||
1789 | asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); | ||
1790 | |||
1791 | return idx; | ||
1792 | } | ||
1793 | |||
1794 | static inline u32 armv7_pmnc_disable_intens(unsigned int idx) | ||
1795 | { | ||
1796 | u32 val; | ||
1797 | |||
1798 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
1799 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
1800 | pr_err("CPU%u disabling wrong PMNC counter" | ||
1801 | " interrupt enable %d\n", smp_processor_id(), idx); | ||
1802 | return -1; | ||
1803 | } | ||
1804 | |||
1805 | if (idx == ARMV7_CYCLE_COUNTER) | ||
1806 | val = ARMV7_INTENC_C; | ||
1807 | else | ||
1808 | val = ARMV7_INTENC_P(idx); | ||
1809 | |||
1810 | asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val)); | ||
1811 | |||
1812 | return idx; | ||
1813 | } | ||
1814 | |||
1815 | static inline u32 armv7_pmnc_getreset_flags(void) | ||
1816 | { | ||
1817 | u32 val; | ||
1818 | |||
1819 | /* Read */ | ||
1820 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); | ||
1821 | |||
1822 | /* Write to clear flags */ | ||
1823 | val &= ARMV7_FLAG_MASK; | ||
1824 | asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); | ||
1825 | |||
1826 | return val; | ||
1827 | } | ||
1828 | |||
1829 | #ifdef DEBUG | ||
1830 | static void armv7_pmnc_dump_regs(void) | ||
1831 | { | ||
1832 | u32 val; | ||
1833 | unsigned int cnt; | ||
1834 | |||
1835 | printk(KERN_INFO "PMNC registers dump:\n"); | ||
1836 | |||
1837 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); | ||
1838 | printk(KERN_INFO "PMNC =0x%08x\n", val); | ||
1839 | |||
1840 | asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); | ||
1841 | printk(KERN_INFO "CNTENS=0x%08x\n", val); | ||
1842 | |||
1843 | asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); | ||
1844 | printk(KERN_INFO "INTENS=0x%08x\n", val); | ||
1845 | |||
1846 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); | ||
1847 | printk(KERN_INFO "FLAGS =0x%08x\n", val); | ||
1848 | |||
1849 | asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); | ||
1850 | printk(KERN_INFO "SELECT=0x%08x\n", val); | ||
1851 | |||
1852 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); | ||
1853 | printk(KERN_INFO "CCNT =0x%08x\n", val); | ||
1854 | |||
1855 | for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) { | ||
1856 | armv7_pmnc_select_counter(cnt); | ||
1857 | asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); | ||
1858 | printk(KERN_INFO "CNT[%d] count =0x%08x\n", | ||
1859 | cnt-ARMV7_EVENT_CNT_TO_CNTx, val); | ||
1860 | asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); | ||
1861 | printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", | ||
1862 | cnt-ARMV7_EVENT_CNT_TO_CNTx, val); | ||
1863 | } | ||
1864 | } | ||
1865 | #endif | ||
1866 | |||
1867 | void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
1868 | { | ||
1869 | unsigned long flags; | ||
1870 | |||
1871 | /* | ||
1872 | * Enable counter and interrupt, and set the counter to count | ||
1873 | * the event that we're interested in. | ||
1874 | */ | ||
1875 | spin_lock_irqsave(&pmu_lock, flags); | ||
1876 | |||
1877 | /* | ||
1878 | * Disable counter | ||
1879 | */ | ||
1880 | armv7_pmnc_disable_counter(idx); | ||
1881 | |||
1882 | /* | ||
1883 | * Set event (if destined for PMNx counters) | ||
1884 | * We don't need to set the event if it's a cycle count | ||
1885 | */ | ||
1886 | if (idx != ARMV7_CYCLE_COUNTER) | ||
1887 | armv7_pmnc_write_evtsel(idx, hwc->config_base); | ||
1888 | |||
1889 | /* | ||
1890 | * Enable interrupt for this counter | ||
1891 | */ | ||
1892 | armv7_pmnc_enable_intens(idx); | ||
1893 | |||
1894 | /* | ||
1895 | * Enable counter | ||
1896 | */ | ||
1897 | armv7_pmnc_enable_counter(idx); | ||
1898 | |||
1899 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1900 | } | ||
1901 | |||
1902 | static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
1903 | { | ||
1904 | unsigned long flags; | ||
1905 | |||
1906 | /* | ||
1907 | * Disable counter and interrupt | ||
1908 | */ | ||
1909 | spin_lock_irqsave(&pmu_lock, flags); | ||
1910 | |||
1911 | /* | ||
1912 | * Disable counter | ||
1913 | */ | ||
1914 | armv7_pmnc_disable_counter(idx); | ||
1915 | |||
1916 | /* | ||
1917 | * Disable interrupt for this counter | ||
1918 | */ | ||
1919 | armv7_pmnc_disable_intens(idx); | ||
1920 | |||
1921 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1922 | } | ||
1923 | |||
1924 | static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) | ||
1925 | { | ||
1926 | unsigned long pmnc; | ||
1927 | struct perf_sample_data data; | ||
1928 | struct cpu_hw_events *cpuc; | ||
1929 | struct pt_regs *regs; | ||
1930 | int idx; | ||
1931 | |||
1932 | /* | ||
1933 | * Get and reset the IRQ flags | ||
1934 | */ | ||
1935 | pmnc = armv7_pmnc_getreset_flags(); | ||
1936 | |||
1937 | /* | ||
1938 | * Did an overflow occur? | ||
1939 | */ | ||
1940 | if (!armv7_pmnc_has_overflowed(pmnc)) | ||
1941 | return IRQ_NONE; | ||
1942 | |||
1943 | /* | ||
1944 | * Handle the counter(s) overflow(s) | ||
1945 | */ | ||
1946 | regs = get_irq_regs(); | ||
1947 | |||
1948 | data.addr = 0; | ||
1949 | |||
1950 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
1951 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
1952 | struct perf_event *event = cpuc->events[idx]; | ||
1953 | struct hw_perf_event *hwc; | ||
1954 | |||
1955 | if (!test_bit(idx, cpuc->active_mask)) | ||
1956 | continue; | ||
1957 | |||
1958 | /* | ||
1959 | * We have a single interrupt for all counters. Check that | ||
1960 | * each counter has overflowed before we process it. | ||
1961 | */ | ||
1962 | if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) | ||
1963 | continue; | ||
1964 | |||
1965 | hwc = &event->hw; | ||
1966 | armpmu_event_update(event, hwc, idx); | ||
1967 | data.period = event->hw.last_period; | ||
1968 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
1969 | continue; | ||
1970 | |||
1971 | if (perf_event_overflow(event, 0, &data, regs)) | ||
1972 | armpmu->disable(hwc, idx); | ||
1973 | } | ||
1974 | |||
1975 | /* | ||
1976 | * Handle the pending perf events. | ||
1977 | * | ||
1978 | * Note: this call *must* be run with interrupts enabled. For | ||
1979 | * platforms that can have the PMU interrupts raised as a PMI, this | ||
1980 | * will not work. | ||
1981 | */ | ||
1982 | perf_event_do_pending(); | ||
1983 | |||
1984 | return IRQ_HANDLED; | ||
1985 | } | ||
1986 | |||
1987 | static void armv7pmu_start(void) | ||
1988 | { | ||
1989 | unsigned long flags; | ||
1990 | |||
1991 | spin_lock_irqsave(&pmu_lock, flags); | ||
1992 | /* Enable all counters */ | ||
1993 | armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); | ||
1994 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
1995 | } | ||
1996 | |||
1997 | static void armv7pmu_stop(void) | ||
1998 | { | ||
1999 | unsigned long flags; | ||
2000 | |||
2001 | spin_lock_irqsave(&pmu_lock, flags); | ||
2002 | /* Disable all counters */ | ||
2003 | armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); | ||
2004 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
2005 | } | ||
2006 | |||
2007 | static inline int armv7_a8_pmu_event_map(int config) | ||
2008 | { | ||
2009 | int mapping = armv7_a8_perf_map[config]; | ||
2010 | if (HW_OP_UNSUPPORTED == mapping) | ||
2011 | mapping = -EOPNOTSUPP; | ||
2012 | return mapping; | ||
2013 | } | ||
2014 | |||
2015 | static inline int armv7_a9_pmu_event_map(int config) | ||
2016 | { | ||
2017 | int mapping = armv7_a9_perf_map[config]; | ||
2018 | if (HW_OP_UNSUPPORTED == mapping) | ||
2019 | mapping = -EOPNOTSUPP; | ||
2020 | return mapping; | ||
2021 | } | ||
2022 | |||
2023 | static u64 armv7pmu_raw_event(u64 config) | ||
2024 | { | ||
2025 | return config & 0xff; | ||
2026 | } | ||
2027 | |||
2028 | static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
2029 | struct hw_perf_event *event) | ||
2030 | { | ||
2031 | int idx; | ||
2032 | |||
2033 | /* Always place a cycle counter into the cycle counter. */ | ||
2034 | if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) { | ||
2035 | if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask)) | ||
2036 | return -EAGAIN; | ||
2037 | |||
2038 | return ARMV7_CYCLE_COUNTER; | ||
2039 | } else { | ||
2040 | /* | ||
2041 | * For anything other than a cycle counter, try and use | ||
2042 | * the events counters | ||
2043 | */ | ||
2044 | for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) { | ||
2045 | if (!test_and_set_bit(idx, cpuc->used_mask)) | ||
2046 | return idx; | ||
2047 | } | ||
2048 | |||
2049 | /* The counters are all in use. */ | ||
2050 | return -EAGAIN; | ||
2051 | } | ||
2052 | } | ||
2053 | |||
2054 | static struct arm_pmu armv7pmu = { | ||
2055 | .handle_irq = armv7pmu_handle_irq, | ||
2056 | .enable = armv7pmu_enable_event, | ||
2057 | .disable = armv7pmu_disable_event, | ||
2058 | .raw_event = armv7pmu_raw_event, | ||
2059 | .read_counter = armv7pmu_read_counter, | ||
2060 | .write_counter = armv7pmu_write_counter, | ||
2061 | .get_event_idx = armv7pmu_get_event_idx, | ||
2062 | .start = armv7pmu_start, | ||
2063 | .stop = armv7pmu_stop, | ||
2064 | .max_period = (1LLU << 32) - 1, | ||
2065 | }; | ||
2066 | |||
2067 | static u32 __init armv7_reset_read_pmnc(void) | ||
2068 | { | ||
2069 | u32 nb_cnt; | ||
2070 | |||
2071 | /* Initialize & Reset PMNC: C and P bits */ | ||
2072 | armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); | ||
2073 | |||
2074 | /* Read the nb of CNTx counters supported from PMNC */ | ||
2075 | nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; | ||
2076 | |||
2077 | /* Add the CPU cycles counter and return */ | ||
2078 | return nb_cnt + 1; | ||
2079 | } | ||
2080 | |||
2081 | static int __init | ||
2082 | init_hw_perf_events(void) | ||
2083 | { | ||
2084 | unsigned long cpuid = read_cpuid_id(); | ||
2085 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | ||
2086 | unsigned long part_number = (cpuid & 0xFFF0); | ||
2087 | |||
2088 | /* We only support ARM CPUs implemented by ARM at the moment. */ | ||
2089 | if (0x41 == implementor) { | ||
2090 | switch (part_number) { | ||
2091 | case 0xB360: /* ARM1136 */ | ||
2092 | case 0xB560: /* ARM1156 */ | ||
2093 | case 0xB760: /* ARM1176 */ | ||
2094 | armpmu = &armv6pmu; | ||
2095 | memcpy(armpmu_perf_cache_map, armv6_perf_cache_map, | ||
2096 | sizeof(armv6_perf_cache_map)); | ||
2097 | perf_max_events = armv6pmu.num_events; | ||
2098 | break; | ||
2099 | case 0xB020: /* ARM11mpcore */ | ||
2100 | armpmu = &armv6mpcore_pmu; | ||
2101 | memcpy(armpmu_perf_cache_map, | ||
2102 | armv6mpcore_perf_cache_map, | ||
2103 | sizeof(armv6mpcore_perf_cache_map)); | ||
2104 | perf_max_events = armv6mpcore_pmu.num_events; | ||
2105 | break; | ||
2106 | case 0xC080: /* Cortex-A8 */ | ||
2107 | armv7pmu.name = ARMV7_PMU_CORTEX_A8_NAME; | ||
2108 | memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map, | ||
2109 | sizeof(armv7_a8_perf_cache_map)); | ||
2110 | armv7pmu.event_map = armv7_a8_pmu_event_map; | ||
2111 | armpmu = &armv7pmu; | ||
2112 | |||
2113 | /* Reset PMNC and read the nb of CNTx counters | ||
2114 | supported */ | ||
2115 | armv7pmu.num_events = armv7_reset_read_pmnc(); | ||
2116 | perf_max_events = armv7pmu.num_events; | ||
2117 | break; | ||
2118 | case 0xC090: /* Cortex-A9 */ | ||
2119 | armv7pmu.name = ARMV7_PMU_CORTEX_A9_NAME; | ||
2120 | memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map, | ||
2121 | sizeof(armv7_a9_perf_cache_map)); | ||
2122 | armv7pmu.event_map = armv7_a9_pmu_event_map; | ||
2123 | armpmu = &armv7pmu; | ||
2124 | |||
2125 | /* Reset PMNC and read the nb of CNTx counters | ||
2126 | supported */ | ||
2127 | armv7pmu.num_events = armv7_reset_read_pmnc(); | ||
2128 | perf_max_events = armv7pmu.num_events; | ||
2129 | break; | ||
2130 | default: | ||
2131 | pr_info("no hardware support available\n"); | ||
2132 | perf_max_events = -1; | ||
2133 | } | ||
2134 | } | ||
2135 | |||
2136 | if (armpmu) | ||
2137 | pr_info("enabled with %s PMU driver, %d counters available\n", | ||
2138 | armpmu->name, armpmu->num_events); | ||
2139 | |||
2140 | return 0; | ||
2141 | } | ||
2142 | arch_initcall(init_hw_perf_events); | ||
2143 | |||
2144 | /* | ||
2145 | * Callchain handling code. | ||
2146 | */ | ||
2147 | static inline void | ||
2148 | callchain_store(struct perf_callchain_entry *entry, | ||
2149 | u64 ip) | ||
2150 | { | ||
2151 | if (entry->nr < PERF_MAX_STACK_DEPTH) | ||
2152 | entry->ip[entry->nr++] = ip; | ||
2153 | } | ||
2154 | |||
2155 | /* | ||
2156 | * The registers we're interested in are at the end of the variable | ||
2157 | * length saved register structure. The fp points at the end of this | ||
2158 | * structure so the address of this struct is: | ||
2159 | * (struct frame_tail *)(xxx->fp)-1 | ||
2160 | * | ||
2161 | * This code has been adapted from the ARM OProfile support. | ||
2162 | */ | ||
2163 | struct frame_tail { | ||
2164 | struct frame_tail *fp; | ||
2165 | unsigned long sp; | ||
2166 | unsigned long lr; | ||
2167 | } __attribute__((packed)); | ||
2168 | |||
2169 | /* | ||
2170 | * Get the return address for a single stackframe and return a pointer to the | ||
2171 | * next frame tail. | ||
2172 | */ | ||
2173 | static struct frame_tail * | ||
2174 | user_backtrace(struct frame_tail *tail, | ||
2175 | struct perf_callchain_entry *entry) | ||
2176 | { | ||
2177 | struct frame_tail buftail; | ||
2178 | |||
2179 | /* Also check accessibility of one struct frame_tail beyond */ | ||
2180 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | ||
2181 | return NULL; | ||
2182 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | ||
2183 | return NULL; | ||
2184 | |||
2185 | callchain_store(entry, buftail.lr); | ||
2186 | |||
2187 | /* | ||
2188 | * Frame pointers should strictly progress back up the stack | ||
2189 | * (towards higher addresses). | ||
2190 | */ | ||
2191 | if (tail >= buftail.fp) | ||
2192 | return NULL; | ||
2193 | |||
2194 | return buftail.fp - 1; | ||
2195 | } | ||
2196 | |||
2197 | static void | ||
2198 | perf_callchain_user(struct pt_regs *regs, | ||
2199 | struct perf_callchain_entry *entry) | ||
2200 | { | ||
2201 | struct frame_tail *tail; | ||
2202 | |||
2203 | callchain_store(entry, PERF_CONTEXT_USER); | ||
2204 | |||
2205 | if (!user_mode(regs)) | ||
2206 | regs = task_pt_regs(current); | ||
2207 | |||
2208 | tail = (struct frame_tail *)regs->ARM_fp - 1; | ||
2209 | |||
2210 | while (tail && !((unsigned long)tail & 0x3)) | ||
2211 | tail = user_backtrace(tail, entry); | ||
2212 | } | ||
2213 | |||
2214 | /* | ||
2215 | * Gets called by walk_stackframe() for every stackframe. This will be called | ||
2216 | * whist unwinding the stackframe and is like a subroutine return so we use | ||
2217 | * the PC. | ||
2218 | */ | ||
2219 | static int | ||
2220 | callchain_trace(struct stackframe *fr, | ||
2221 | void *data) | ||
2222 | { | ||
2223 | struct perf_callchain_entry *entry = data; | ||
2224 | callchain_store(entry, fr->pc); | ||
2225 | return 0; | ||
2226 | } | ||
2227 | |||
2228 | static void | ||
2229 | perf_callchain_kernel(struct pt_regs *regs, | ||
2230 | struct perf_callchain_entry *entry) | ||
2231 | { | ||
2232 | struct stackframe fr; | ||
2233 | |||
2234 | callchain_store(entry, PERF_CONTEXT_KERNEL); | ||
2235 | fr.fp = regs->ARM_fp; | ||
2236 | fr.sp = regs->ARM_sp; | ||
2237 | fr.lr = regs->ARM_lr; | ||
2238 | fr.pc = regs->ARM_pc; | ||
2239 | walk_stackframe(&fr, callchain_trace, entry); | ||
2240 | } | ||
2241 | |||
2242 | static void | ||
2243 | perf_do_callchain(struct pt_regs *regs, | ||
2244 | struct perf_callchain_entry *entry) | ||
2245 | { | ||
2246 | int is_user; | ||
2247 | |||
2248 | if (!regs) | ||
2249 | return; | ||
2250 | |||
2251 | is_user = user_mode(regs); | ||
2252 | |||
2253 | if (!current || !current->pid) | ||
2254 | return; | ||
2255 | |||
2256 | if (is_user && current->state != TASK_RUNNING) | ||
2257 | return; | ||
2258 | |||
2259 | if (!is_user) | ||
2260 | perf_callchain_kernel(regs, entry); | ||
2261 | |||
2262 | if (current->mm) | ||
2263 | perf_callchain_user(regs, entry); | ||
2264 | } | ||
2265 | |||
2266 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); | ||
2267 | |||
2268 | struct perf_callchain_entry * | ||
2269 | perf_callchain(struct pt_regs *regs) | ||
2270 | { | ||
2271 | struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry); | ||
2272 | |||
2273 | entry->nr = 0; | ||
2274 | perf_do_callchain(regs, entry); | ||
2275 | return entry; | ||
2276 | } | ||
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c new file mode 100644 index 000000000000..a124312e343f --- /dev/null +++ b/arch/arm/kernel/pmu.c | |||
@@ -0,0 +1,103 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/kernel/pmu.c | ||
3 | * | ||
4 | * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #include <linux/cpumask.h> | ||
13 | #include <linux/err.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/module.h> | ||
17 | |||
18 | #include <asm/pmu.h> | ||
19 | |||
20 | /* | ||
21 | * Define the IRQs for the system. We could use something like a platform | ||
22 | * device but that seems fairly heavyweight for this. Also, the performance | ||
23 | * counters can't be removed or hotplugged. | ||
24 | * | ||
25 | * Ordering is important: init_pmu() will use the ordering to set the affinity | ||
26 | * to the corresponding core. e.g. the first interrupt will go to cpu 0, the | ||
27 | * second goes to cpu 1 etc. | ||
28 | */ | ||
29 | static const int irqs[] = { | ||
30 | #if defined(CONFIG_ARCH_OMAP2) | ||
31 | 3, | ||
32 | #elif defined(CONFIG_ARCH_BCMRING) | ||
33 | IRQ_PMUIRQ, | ||
34 | #elif defined(CONFIG_MACH_REALVIEW_EB) | ||
35 | IRQ_EB11MP_PMU_CPU0, | ||
36 | IRQ_EB11MP_PMU_CPU1, | ||
37 | IRQ_EB11MP_PMU_CPU2, | ||
38 | IRQ_EB11MP_PMU_CPU3, | ||
39 | #elif defined(CONFIG_ARCH_OMAP3) | ||
40 | INT_34XX_BENCH_MPU_EMUL, | ||
41 | #elif defined(CONFIG_ARCH_IOP32X) | ||
42 | IRQ_IOP32X_CORE_PMU, | ||
43 | #elif defined(CONFIG_ARCH_IOP33X) | ||
44 | IRQ_IOP33X_CORE_PMU, | ||
45 | #elif defined(CONFIG_ARCH_PXA) | ||
46 | IRQ_PMU, | ||
47 | #endif | ||
48 | }; | ||
49 | |||
50 | static const struct pmu_irqs pmu_irqs = { | ||
51 | .irqs = irqs, | ||
52 | .num_irqs = ARRAY_SIZE(irqs), | ||
53 | }; | ||
54 | |||
55 | static volatile long pmu_lock; | ||
56 | |||
57 | const struct pmu_irqs * | ||
58 | reserve_pmu(void) | ||
59 | { | ||
60 | return test_and_set_bit_lock(0, &pmu_lock) ? ERR_PTR(-EBUSY) : | ||
61 | &pmu_irqs; | ||
62 | } | ||
63 | EXPORT_SYMBOL_GPL(reserve_pmu); | ||
64 | |||
65 | int | ||
66 | release_pmu(const struct pmu_irqs *irqs) | ||
67 | { | ||
68 | if (WARN_ON(irqs != &pmu_irqs)) | ||
69 | return -EINVAL; | ||
70 | clear_bit_unlock(0, &pmu_lock); | ||
71 | return 0; | ||
72 | } | ||
73 | EXPORT_SYMBOL_GPL(release_pmu); | ||
74 | |||
75 | static int | ||
76 | set_irq_affinity(int irq, | ||
77 | unsigned int cpu) | ||
78 | { | ||
79 | #ifdef CONFIG_SMP | ||
80 | int err = irq_set_affinity(irq, cpumask_of(cpu)); | ||
81 | if (err) | ||
82 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | ||
83 | irq, cpu); | ||
84 | return err; | ||
85 | #else | ||
86 | return 0; | ||
87 | #endif | ||
88 | } | ||
89 | |||
90 | int | ||
91 | init_pmu(void) | ||
92 | { | ||
93 | int i, err = 0; | ||
94 | |||
95 | for (i = 0; i < pmu_irqs.num_irqs; ++i) { | ||
96 | err = set_irq_affinity(pmu_irqs.irqs[i], i); | ||
97 | if (err) | ||
98 | break; | ||
99 | } | ||
100 | |||
101 | return err; | ||
102 | } | ||
103 | EXPORT_SYMBOL_GPL(init_pmu); | ||
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index a2ea3854cb3c..08f899fb76a6 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c | |||
@@ -499,10 +499,41 @@ static struct undef_hook thumb_break_hook = { | |||
499 | .fn = break_trap, | 499 | .fn = break_trap, |
500 | }; | 500 | }; |
501 | 501 | ||
502 | static int thumb2_break_trap(struct pt_regs *regs, unsigned int instr) | ||
503 | { | ||
504 | unsigned int instr2; | ||
505 | void __user *pc; | ||
506 | |||
507 | /* Check the second half of the instruction. */ | ||
508 | pc = (void __user *)(instruction_pointer(regs) + 2); | ||
509 | |||
510 | if (processor_mode(regs) == SVC_MODE) { | ||
511 | instr2 = *(u16 *) pc; | ||
512 | } else { | ||
513 | get_user(instr2, (u16 __user *)pc); | ||
514 | } | ||
515 | |||
516 | if (instr2 == 0xa000) { | ||
517 | ptrace_break(current, regs); | ||
518 | return 0; | ||
519 | } else { | ||
520 | return 1; | ||
521 | } | ||
522 | } | ||
523 | |||
524 | static struct undef_hook thumb2_break_hook = { | ||
525 | .instr_mask = 0xffff, | ||
526 | .instr_val = 0xf7f0, | ||
527 | .cpsr_mask = PSR_T_BIT, | ||
528 | .cpsr_val = PSR_T_BIT, | ||
529 | .fn = thumb2_break_trap, | ||
530 | }; | ||
531 | |||
502 | static int __init ptrace_break_init(void) | 532 | static int __init ptrace_break_init(void) |
503 | { | 533 | { |
504 | register_undef_hook(&arm_break_hook); | 534 | register_undef_hook(&arm_break_hook); |
505 | register_undef_hook(&thumb_break_hook); | 535 | register_undef_hook(&thumb_break_hook); |
536 | register_undef_hook(&thumb2_break_hook); | ||
506 | return 0; | 537 | return 0; |
507 | } | 538 | } |
508 | 539 | ||
@@ -669,7 +700,7 @@ static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data) | |||
669 | union vfp_state *vfp = &thread->vfpstate; | 700 | union vfp_state *vfp = &thread->vfpstate; |
670 | struct user_vfp __user *ufp = data; | 701 | struct user_vfp __user *ufp = data; |
671 | 702 | ||
672 | vfp_sync_state(thread); | 703 | vfp_sync_hwstate(thread); |
673 | 704 | ||
674 | /* copy the floating point registers */ | 705 | /* copy the floating point registers */ |
675 | if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, | 706 | if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, |
@@ -692,7 +723,7 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) | |||
692 | union vfp_state *vfp = &thread->vfpstate; | 723 | union vfp_state *vfp = &thread->vfpstate; |
693 | struct user_vfp __user *ufp = data; | 724 | struct user_vfp __user *ufp = data; |
694 | 725 | ||
695 | vfp_sync_state(thread); | 726 | vfp_sync_hwstate(thread); |
696 | 727 | ||
697 | /* copy the floating point registers */ | 728 | /* copy the floating point registers */ |
698 | if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, | 729 | if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, |
@@ -703,6 +734,8 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) | |||
703 | if (get_user(vfp->hard.fpscr, &ufp->fpscr)) | 734 | if (get_user(vfp->hard.fpscr, &ufp->fpscr)) |
704 | return -EFAULT; | 735 | return -EFAULT; |
705 | 736 | ||
737 | vfp_flush_hwstate(thread); | ||
738 | |||
706 | return 0; | 739 | return 0; |
707 | } | 740 | } |
708 | #endif | 741 | #endif |
@@ -712,26 +745,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
712 | int ret; | 745 | int ret; |
713 | 746 | ||
714 | switch (request) { | 747 | switch (request) { |
715 | /* | ||
716 | * read word at location "addr" in the child process. | ||
717 | */ | ||
718 | case PTRACE_PEEKTEXT: | ||
719 | case PTRACE_PEEKDATA: | ||
720 | ret = generic_ptrace_peekdata(child, addr, data); | ||
721 | break; | ||
722 | |||
723 | case PTRACE_PEEKUSR: | 748 | case PTRACE_PEEKUSR: |
724 | ret = ptrace_read_user(child, addr, (unsigned long __user *)data); | 749 | ret = ptrace_read_user(child, addr, (unsigned long __user *)data); |
725 | break; | 750 | break; |
726 | 751 | ||
727 | /* | ||
728 | * write the word at location addr. | ||
729 | */ | ||
730 | case PTRACE_POKETEXT: | ||
731 | case PTRACE_POKEDATA: | ||
732 | ret = generic_ptrace_pokedata(child, addr, data); | ||
733 | break; | ||
734 | |||
735 | case PTRACE_POKEUSR: | 752 | case PTRACE_POKEUSR: |
736 | ret = ptrace_write_user(child, addr, data); | 753 | ret = ptrace_write_user(child, addr, data); |
737 | break; | 754 | break; |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c6c57b640b6b..baf5959d639a 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
25 | #include <linux/smp.h> | 25 | #include <linux/smp.h> |
26 | #include <linux/fs.h> | 26 | #include <linux/fs.h> |
27 | #include <linux/proc_fs.h> | ||
27 | 28 | ||
28 | #include <asm/unified.h> | 29 | #include <asm/unified.h> |
29 | #include <asm/cpu.h> | 30 | #include <asm/cpu.h> |
@@ -117,7 +118,7 @@ EXPORT_SYMBOL(elf_platform); | |||
117 | 118 | ||
118 | static const char *cpu_name; | 119 | static const char *cpu_name; |
119 | static const char *machine_name; | 120 | static const char *machine_name; |
120 | static char __initdata command_line[COMMAND_LINE_SIZE]; | 121 | static char __initdata cmd_line[COMMAND_LINE_SIZE]; |
121 | 122 | ||
122 | static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; | 123 | static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; |
123 | static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; | 124 | static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; |
@@ -417,10 +418,11 @@ static int __init arm_add_memory(unsigned long start, unsigned long size) | |||
417 | * Pick out the memory size. We look for mem=size@start, | 418 | * Pick out the memory size. We look for mem=size@start, |
418 | * where start and size are "size[KkMm]" | 419 | * where start and size are "size[KkMm]" |
419 | */ | 420 | */ |
420 | static void __init early_mem(char **p) | 421 | static int __init early_mem(char *p) |
421 | { | 422 | { |
422 | static int usermem __initdata = 0; | 423 | static int usermem __initdata = 0; |
423 | unsigned long size, start; | 424 | unsigned long size, start; |
425 | char *endp; | ||
424 | 426 | ||
425 | /* | 427 | /* |
426 | * If the user specifies memory size, we | 428 | * If the user specifies memory size, we |
@@ -433,52 +435,15 @@ static void __init early_mem(char **p) | |||
433 | } | 435 | } |
434 | 436 | ||
435 | start = PHYS_OFFSET; | 437 | start = PHYS_OFFSET; |
436 | size = memparse(*p, p); | 438 | size = memparse(p, &endp); |
437 | if (**p == '@') | 439 | if (*endp == '@') |
438 | start = memparse(*p + 1, p); | 440 | start = memparse(endp + 1, NULL); |
439 | 441 | ||
440 | arm_add_memory(start, size); | 442 | arm_add_memory(start, size); |
441 | } | ||
442 | __early_param("mem=", early_mem); | ||
443 | 443 | ||
444 | /* | 444 | return 0; |
445 | * Initial parsing of the command line. | ||
446 | */ | ||
447 | static void __init parse_cmdline(char **cmdline_p, char *from) | ||
448 | { | ||
449 | char c = ' ', *to = command_line; | ||
450 | int len = 0; | ||
451 | |||
452 | for (;;) { | ||
453 | if (c == ' ') { | ||
454 | extern struct early_params __early_begin, __early_end; | ||
455 | struct early_params *p; | ||
456 | |||
457 | for (p = &__early_begin; p < &__early_end; p++) { | ||
458 | int arglen = strlen(p->arg); | ||
459 | |||
460 | if (memcmp(from, p->arg, arglen) == 0) { | ||
461 | if (to != command_line) | ||
462 | to -= 1; | ||
463 | from += arglen; | ||
464 | p->fn(&from); | ||
465 | |||
466 | while (*from != ' ' && *from != '\0') | ||
467 | from++; | ||
468 | break; | ||
469 | } | ||
470 | } | ||
471 | } | ||
472 | c = *from++; | ||
473 | if (!c) | ||
474 | break; | ||
475 | if (COMMAND_LINE_SIZE <= ++len) | ||
476 | break; | ||
477 | *to++ = c; | ||
478 | } | ||
479 | *to = '\0'; | ||
480 | *cmdline_p = command_line; | ||
481 | } | 445 | } |
446 | early_param("mem", early_mem); | ||
482 | 447 | ||
483 | static void __init | 448 | static void __init |
484 | setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz) | 449 | setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz) |
@@ -739,9 +704,15 @@ void __init setup_arch(char **cmdline_p) | |||
739 | init_mm.end_data = (unsigned long) _edata; | 704 | init_mm.end_data = (unsigned long) _edata; |
740 | init_mm.brk = (unsigned long) _end; | 705 | init_mm.brk = (unsigned long) _end; |
741 | 706 | ||
742 | memcpy(boot_command_line, from, COMMAND_LINE_SIZE); | 707 | /* parse_early_param needs a boot_command_line */ |
743 | boot_command_line[COMMAND_LINE_SIZE-1] = '\0'; | 708 | strlcpy(boot_command_line, from, COMMAND_LINE_SIZE); |
744 | parse_cmdline(cmdline_p, from); | 709 | |
710 | /* populate cmd_line too for later use, preserving boot_command_line */ | ||
711 | strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); | ||
712 | *cmdline_p = cmd_line; | ||
713 | |||
714 | parse_early_param(); | ||
715 | |||
745 | paging_init(mdesc); | 716 | paging_init(mdesc); |
746 | request_standard_resources(&meminfo, mdesc); | 717 | request_standard_resources(&meminfo, mdesc); |
747 | 718 | ||
@@ -782,9 +753,21 @@ static int __init topology_init(void) | |||
782 | 753 | ||
783 | return 0; | 754 | return 0; |
784 | } | 755 | } |
785 | |||
786 | subsys_initcall(topology_init); | 756 | subsys_initcall(topology_init); |
787 | 757 | ||
758 | #ifdef CONFIG_HAVE_PROC_CPU | ||
759 | static int __init proc_cpu_init(void) | ||
760 | { | ||
761 | struct proc_dir_entry *res; | ||
762 | |||
763 | res = proc_mkdir("cpu", NULL); | ||
764 | if (!res) | ||
765 | return -ENOMEM; | ||
766 | return 0; | ||
767 | } | ||
768 | fs_initcall(proc_cpu_init); | ||
769 | #endif | ||
770 | |||
788 | static const char *hwcap_str[] = { | 771 | static const char *hwcap_str[] = { |
789 | "swp", | 772 | "swp", |
790 | "half", | 773 | "half", |
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index d38cdf2c8276..28753805d2d1 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c | |||
@@ -10,11 +10,6 @@ | |||
10 | * | 10 | * |
11 | * This file contains the ARM-specific time handling details: | 11 | * This file contains the ARM-specific time handling details: |
12 | * reading the RTC at bootup, etc... | 12 | * reading the RTC at bootup, etc... |
13 | * | ||
14 | * 1994-07-02 Alan Modra | ||
15 | * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime | ||
16 | * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 | ||
17 | * "A Kernel Model for Precision Timekeeping" by Dave Mills | ||
18 | */ | 13 | */ |
19 | #include <linux/module.h> | 14 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
@@ -77,11 +72,6 @@ unsigned long profile_pc(struct pt_regs *regs) | |||
77 | EXPORT_SYMBOL(profile_pc); | 72 | EXPORT_SYMBOL(profile_pc); |
78 | #endif | 73 | #endif |
79 | 74 | ||
80 | /* | ||
81 | * hook for setting the RTC's idea of the current time. | ||
82 | */ | ||
83 | int (*set_rtc)(void); | ||
84 | |||
85 | #ifndef CONFIG_GENERIC_TIME | 75 | #ifndef CONFIG_GENERIC_TIME |
86 | static unsigned long dummy_gettimeoffset(void) | 76 | static unsigned long dummy_gettimeoffset(void) |
87 | { | 77 | { |
@@ -89,140 +79,6 @@ static unsigned long dummy_gettimeoffset(void) | |||
89 | } | 79 | } |
90 | #endif | 80 | #endif |
91 | 81 | ||
92 | static unsigned long next_rtc_update; | ||
93 | |||
94 | /* | ||
95 | * If we have an externally synchronized linux clock, then update | ||
96 | * CMOS clock accordingly every ~11 minutes. set_rtc() has to be | ||
97 | * called as close as possible to 500 ms before the new second | ||
98 | * starts. | ||
99 | */ | ||
100 | static inline void do_set_rtc(void) | ||
101 | { | ||
102 | if (!ntp_synced() || set_rtc == NULL) | ||
103 | return; | ||
104 | |||
105 | if (next_rtc_update && | ||
106 | time_before((unsigned long)xtime.tv_sec, next_rtc_update)) | ||
107 | return; | ||
108 | |||
109 | if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) && | ||
110 | xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1)) | ||
111 | return; | ||
112 | |||
113 | if (set_rtc()) | ||
114 | /* | ||
115 | * rtc update failed. Try again in 60s | ||
116 | */ | ||
117 | next_rtc_update = xtime.tv_sec + 60; | ||
118 | else | ||
119 | next_rtc_update = xtime.tv_sec + 660; | ||
120 | } | ||
121 | |||
122 | #ifdef CONFIG_LEDS | ||
123 | |||
124 | static void dummy_leds_event(led_event_t evt) | ||
125 | { | ||
126 | } | ||
127 | |||
128 | void (*leds_event)(led_event_t) = dummy_leds_event; | ||
129 | |||
130 | struct leds_evt_name { | ||
131 | const char name[8]; | ||
132 | int on; | ||
133 | int off; | ||
134 | }; | ||
135 | |||
136 | static const struct leds_evt_name evt_names[] = { | ||
137 | { "amber", led_amber_on, led_amber_off }, | ||
138 | { "blue", led_blue_on, led_blue_off }, | ||
139 | { "green", led_green_on, led_green_off }, | ||
140 | { "red", led_red_on, led_red_off }, | ||
141 | }; | ||
142 | |||
143 | static ssize_t leds_store(struct sys_device *dev, | ||
144 | struct sysdev_attribute *attr, | ||
145 | const char *buf, size_t size) | ||
146 | { | ||
147 | int ret = -EINVAL, len = strcspn(buf, " "); | ||
148 | |||
149 | if (len > 0 && buf[len] == '\0') | ||
150 | len--; | ||
151 | |||
152 | if (strncmp(buf, "claim", len) == 0) { | ||
153 | leds_event(led_claim); | ||
154 | ret = size; | ||
155 | } else if (strncmp(buf, "release", len) == 0) { | ||
156 | leds_event(led_release); | ||
157 | ret = size; | ||
158 | } else { | ||
159 | int i; | ||
160 | |||
161 | for (i = 0; i < ARRAY_SIZE(evt_names); i++) { | ||
162 | if (strlen(evt_names[i].name) != len || | ||
163 | strncmp(buf, evt_names[i].name, len) != 0) | ||
164 | continue; | ||
165 | if (strncmp(buf+len, " on", 3) == 0) { | ||
166 | leds_event(evt_names[i].on); | ||
167 | ret = size; | ||
168 | } else if (strncmp(buf+len, " off", 4) == 0) { | ||
169 | leds_event(evt_names[i].off); | ||
170 | ret = size; | ||
171 | } | ||
172 | break; | ||
173 | } | ||
174 | } | ||
175 | return ret; | ||
176 | } | ||
177 | |||
178 | static SYSDEV_ATTR(event, 0200, NULL, leds_store); | ||
179 | |||
180 | static int leds_suspend(struct sys_device *dev, pm_message_t state) | ||
181 | { | ||
182 | leds_event(led_stop); | ||
183 | return 0; | ||
184 | } | ||
185 | |||
186 | static int leds_resume(struct sys_device *dev) | ||
187 | { | ||
188 | leds_event(led_start); | ||
189 | return 0; | ||
190 | } | ||
191 | |||
192 | static int leds_shutdown(struct sys_device *dev) | ||
193 | { | ||
194 | leds_event(led_halted); | ||
195 | return 0; | ||
196 | } | ||
197 | |||
198 | static struct sysdev_class leds_sysclass = { | ||
199 | .name = "leds", | ||
200 | .shutdown = leds_shutdown, | ||
201 | .suspend = leds_suspend, | ||
202 | .resume = leds_resume, | ||
203 | }; | ||
204 | |||
205 | static struct sys_device leds_device = { | ||
206 | .id = 0, | ||
207 | .cls = &leds_sysclass, | ||
208 | }; | ||
209 | |||
210 | static int __init leds_init(void) | ||
211 | { | ||
212 | int ret; | ||
213 | ret = sysdev_class_register(&leds_sysclass); | ||
214 | if (ret == 0) | ||
215 | ret = sysdev_register(&leds_device); | ||
216 | if (ret == 0) | ||
217 | ret = sysdev_create_file(&leds_device, &attr_event); | ||
218 | return ret; | ||
219 | } | ||
220 | |||
221 | device_initcall(leds_init); | ||
222 | |||
223 | EXPORT_SYMBOL(leds_event); | ||
224 | #endif | ||
225 | |||
226 | #ifdef CONFIG_LEDS_TIMER | 82 | #ifdef CONFIG_LEDS_TIMER |
227 | static inline void do_leds(void) | 83 | static inline void do_leds(void) |
228 | { | 84 | { |
@@ -295,39 +151,6 @@ int do_settimeofday(struct timespec *tv) | |||
295 | EXPORT_SYMBOL(do_settimeofday); | 151 | EXPORT_SYMBOL(do_settimeofday); |
296 | #endif /* !CONFIG_GENERIC_TIME */ | 152 | #endif /* !CONFIG_GENERIC_TIME */ |
297 | 153 | ||
298 | /** | ||
299 | * save_time_delta - Save the offset between system time and RTC time | ||
300 | * @delta: pointer to timespec to store delta | ||
301 | * @rtc: pointer to timespec for current RTC time | ||
302 | * | ||
303 | * Return a delta between the system time and the RTC time, such | ||
304 | * that system time can be restored later with restore_time_delta() | ||
305 | */ | ||
306 | void save_time_delta(struct timespec *delta, struct timespec *rtc) | ||
307 | { | ||
308 | set_normalized_timespec(delta, | ||
309 | xtime.tv_sec - rtc->tv_sec, | ||
310 | xtime.tv_nsec - rtc->tv_nsec); | ||
311 | } | ||
312 | EXPORT_SYMBOL(save_time_delta); | ||
313 | |||
314 | /** | ||
315 | * restore_time_delta - Restore the current system time | ||
316 | * @delta: delta returned by save_time_delta() | ||
317 | * @rtc: pointer to timespec for current RTC time | ||
318 | */ | ||
319 | void restore_time_delta(struct timespec *delta, struct timespec *rtc) | ||
320 | { | ||
321 | struct timespec ts; | ||
322 | |||
323 | set_normalized_timespec(&ts, | ||
324 | delta->tv_sec + rtc->tv_sec, | ||
325 | delta->tv_nsec + rtc->tv_nsec); | ||
326 | |||
327 | do_settimeofday(&ts); | ||
328 | } | ||
329 | EXPORT_SYMBOL(restore_time_delta); | ||
330 | |||
331 | #ifndef CONFIG_GENERIC_CLOCKEVENTS | 154 | #ifndef CONFIG_GENERIC_CLOCKEVENTS |
332 | /* | 155 | /* |
333 | * Kernel system timer support. | 156 | * Kernel system timer support. |
@@ -336,7 +159,6 @@ void timer_tick(void) | |||
336 | { | 159 | { |
337 | profile_tick(CPU_PROFILING); | 160 | profile_tick(CPU_PROFILING); |
338 | do_leds(); | 161 | do_leds(); |
339 | do_set_rtc(); | ||
340 | write_seqlock(&xtime_lock); | 162 | write_seqlock(&xtime_lock); |
341 | do_timer(1); | 163 | do_timer(1); |
342 | write_sequnlock(&xtime_lock); | 164 | write_sequnlock(&xtime_lock); |
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 3f361a783f43..1621e5327b2a 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
@@ -12,15 +12,17 @@ | |||
12 | * 'linux/arch/arm/lib/traps.S'. Mostly a debugging aid, but will probably | 12 | * 'linux/arch/arm/lib/traps.S'. Mostly a debugging aid, but will probably |
13 | * kill the offending process. | 13 | * kill the offending process. |
14 | */ | 14 | */ |
15 | #include <linux/module.h> | ||
16 | #include <linux/signal.h> | 15 | #include <linux/signal.h> |
17 | #include <linux/spinlock.h> | ||
18 | #include <linux/personality.h> | 16 | #include <linux/personality.h> |
19 | #include <linux/kallsyms.h> | 17 | #include <linux/kallsyms.h> |
20 | #include <linux/delay.h> | 18 | #include <linux/spinlock.h> |
19 | #include <linux/uaccess.h> | ||
21 | #include <linux/hardirq.h> | 20 | #include <linux/hardirq.h> |
21 | #include <linux/kdebug.h> | ||
22 | #include <linux/module.h> | ||
23 | #include <linux/kexec.h> | ||
24 | #include <linux/delay.h> | ||
22 | #include <linux/init.h> | 25 | #include <linux/init.h> |
23 | #include <linux/uaccess.h> | ||
24 | 26 | ||
25 | #include <asm/atomic.h> | 27 | #include <asm/atomic.h> |
26 | #include <asm/cacheflush.h> | 28 | #include <asm/cacheflush.h> |
@@ -224,14 +226,21 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) | |||
224 | #define S_SMP "" | 226 | #define S_SMP "" |
225 | #endif | 227 | #endif |
226 | 228 | ||
227 | static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs) | 229 | static int __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs) |
228 | { | 230 | { |
229 | struct task_struct *tsk = thread->task; | 231 | struct task_struct *tsk = thread->task; |
230 | static int die_counter; | 232 | static int die_counter; |
233 | int ret; | ||
231 | 234 | ||
232 | printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", | 235 | printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", |
233 | str, err, ++die_counter); | 236 | str, err, ++die_counter); |
234 | sysfs_printk_last_file(); | 237 | sysfs_printk_last_file(); |
238 | |||
239 | /* trap and error numbers are mostly meaningless on ARM */ | ||
240 | ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV); | ||
241 | if (ret == NOTIFY_STOP) | ||
242 | return ret; | ||
243 | |||
235 | print_modules(); | 244 | print_modules(); |
236 | __show_regs(regs); | 245 | __show_regs(regs); |
237 | printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n", | 246 | printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n", |
@@ -243,6 +252,8 @@ static void __die(const char *str, int err, struct thread_info *thread, struct p | |||
243 | dump_backtrace(regs, tsk); | 252 | dump_backtrace(regs, tsk); |
244 | dump_instr(KERN_EMERG, regs); | 253 | dump_instr(KERN_EMERG, regs); |
245 | } | 254 | } |
255 | |||
256 | return ret; | ||
246 | } | 257 | } |
247 | 258 | ||
248 | DEFINE_SPINLOCK(die_lock); | 259 | DEFINE_SPINLOCK(die_lock); |
@@ -250,16 +261,21 @@ DEFINE_SPINLOCK(die_lock); | |||
250 | /* | 261 | /* |
251 | * This function is protected against re-entrancy. | 262 | * This function is protected against re-entrancy. |
252 | */ | 263 | */ |
253 | NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) | 264 | void die(const char *str, struct pt_regs *regs, int err) |
254 | { | 265 | { |
255 | struct thread_info *thread = current_thread_info(); | 266 | struct thread_info *thread = current_thread_info(); |
267 | int ret; | ||
256 | 268 | ||
257 | oops_enter(); | 269 | oops_enter(); |
258 | 270 | ||
259 | spin_lock_irq(&die_lock); | 271 | spin_lock_irq(&die_lock); |
260 | console_verbose(); | 272 | console_verbose(); |
261 | bust_spinlocks(1); | 273 | bust_spinlocks(1); |
262 | __die(str, err, thread, regs); | 274 | ret = __die(str, err, thread, regs); |
275 | |||
276 | if (regs && kexec_should_crash(thread->task)) | ||
277 | crash_kexec(regs); | ||
278 | |||
263 | bust_spinlocks(0); | 279 | bust_spinlocks(0); |
264 | add_taint(TAINT_DIE); | 280 | add_taint(TAINT_DIE); |
265 | spin_unlock_irq(&die_lock); | 281 | spin_unlock_irq(&die_lock); |
@@ -267,11 +283,10 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) | |||
267 | 283 | ||
268 | if (in_interrupt()) | 284 | if (in_interrupt()) |
269 | panic("Fatal exception in interrupt"); | 285 | panic("Fatal exception in interrupt"); |
270 | |||
271 | if (panic_on_oops) | 286 | if (panic_on_oops) |
272 | panic("Fatal exception"); | 287 | panic("Fatal exception"); |
273 | 288 | if (ret != NOTIFY_STOP) | |
274 | do_exit(SIGSEGV); | 289 | do_exit(SIGSEGV); |
275 | } | 290 | } |
276 | 291 | ||
277 | void arm_notify_die(const char *str, struct pt_regs *regs, | 292 | void arm_notify_die(const char *str, struct pt_regs *regs, |
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 4957e13ef55b..b16c07914b55 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
@@ -43,10 +43,6 @@ SECTIONS | |||
43 | 43 | ||
44 | INIT_SETUP(16) | 44 | INIT_SETUP(16) |
45 | 45 | ||
46 | __early_begin = .; | ||
47 | *(.early_param.init) | ||
48 | __early_end = .; | ||
49 | |||
50 | INIT_CALLS | 46 | INIT_CALLS |
51 | CON_INITCALL | 47 | CON_INITCALL |
52 | SECURITY_INITCALL | 48 | SECURITY_INITCALL |
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S index 0b6351d7c389..a9cac368bfe6 100644 --- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S +++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S | |||
@@ -10,7 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include "hardware.h" | 12 | #include "hardware.h" |
13 | .macro addruart,rx | 13 | .macro addruart, rx, tmp |
14 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
15 | tst \rx, #1 @ MMU enabled? | 15 | tst \rx, #1 @ MMU enabled? |
16 | moveq \rx, #0x80000000 @ physical | 16 | moveq \rx, #0x80000000 @ physical |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 0b2ee953f164..2db43a5ddd9b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
@@ -89,6 +89,12 @@ config ARCH_AT91CAP9 | |||
89 | select GENERIC_CLOCKEVENTS | 89 | select GENERIC_CLOCKEVENTS |
90 | select HAVE_FB_ATMEL | 90 | select HAVE_FB_ATMEL |
91 | 91 | ||
92 | config ARCH_AT572D940HF | ||
93 | bool "AT572D940HF" | ||
94 | select CPU_ARM926T | ||
95 | select GENERIC_TIME | ||
96 | select GENERIC_CLOCKEVENTS | ||
97 | |||
92 | config ARCH_AT91X40 | 98 | config ARCH_AT91X40 |
93 | bool "AT91x40" | 99 | bool "AT91x40" |
94 | 100 | ||
@@ -390,6 +396,23 @@ endif | |||
390 | 396 | ||
391 | # ---------------------------------------------------------- | 397 | # ---------------------------------------------------------- |
392 | 398 | ||
399 | if ARCH_AT572D940HF | ||
400 | |||
401 | comment "AT572D940HF Board Type" | ||
402 | |||
403 | config MACH_AT572D940HFEB | ||
404 | bool "AT572D940HF-EK" | ||
405 | depends on ARCH_AT572D940HF | ||
406 | select HAVE_AT91_DATAFLASH_CARD | ||
407 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
408 | help | ||
409 | Select this if you are using Atmel's AT572D940HF-EK evaluation kit. | ||
410 | <http://www.atmel.com/products/diopsis/default.asp> | ||
411 | |||
412 | endif | ||
413 | |||
414 | # ---------------------------------------------------------- | ||
415 | |||
393 | if ARCH_AT91X40 | 416 | if ARCH_AT91X40 |
394 | 417 | ||
395 | comment "AT91X40 Board Type" | 418 | comment "AT91X40 Board Type" |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 709fbad4a3ee..027dd570dcc3 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devi | |||
19 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o | 19 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o |
20 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o | 20 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o |
21 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o | 21 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o |
22 | obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o | ||
22 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o | 23 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o |
23 | 24 | ||
24 | # AT91RM9200 board-specific support | 25 | # AT91RM9200 board-specific support |
@@ -69,6 +70,9 @@ obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o | |||
69 | # AT91CAP9 board-specific support | 70 | # AT91CAP9 board-specific support |
70 | obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o | 71 | obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o |
71 | 72 | ||
73 | # AT572D940HF board-specific support | ||
74 | obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o | ||
75 | |||
72 | # AT91X40 board-specific support | 76 | # AT91X40 board-specific support |
73 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o | 77 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o |
74 | 78 | ||
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c new file mode 100644 index 000000000000..a6b9c68c003a --- /dev/null +++ b/arch/arm/mach-at91/at572d940hf.c | |||
@@ -0,0 +1,377 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/at572d940hf.c | ||
3 | * | ||
4 | * Antonio R. Costa <costa.antonior@gmail.com> | ||
5 | * Copyright (C) 2008 Atmel | ||
6 | * | ||
7 | * Copyright (C) 2005 SAN People | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #include <linux/module.h> | ||
26 | |||
27 | #include <asm/mach/irq.h> | ||
28 | #include <asm/mach/arch.h> | ||
29 | #include <asm/mach/map.h> | ||
30 | #include <mach/at572d940hf.h> | ||
31 | #include <mach/at91_pmc.h> | ||
32 | #include <mach/at91_rstc.h> | ||
33 | |||
34 | #include "generic.h" | ||
35 | #include "clock.h" | ||
36 | |||
37 | static struct map_desc at572d940hf_io_desc[] __initdata = { | ||
38 | { | ||
39 | .virtual = AT91_VA_BASE_SYS, | ||
40 | .pfn = __phys_to_pfn(AT91_BASE_SYS), | ||
41 | .length = SZ_16K, | ||
42 | .type = MT_DEVICE, | ||
43 | }, { | ||
44 | .virtual = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE, | ||
45 | .pfn = __phys_to_pfn(AT572D940HF_SRAM_BASE), | ||
46 | .length = AT572D940HF_SRAM_SIZE, | ||
47 | .type = MT_DEVICE, | ||
48 | }, | ||
49 | }; | ||
50 | |||
51 | /* -------------------------------------------------------------------- | ||
52 | * Clocks | ||
53 | * -------------------------------------------------------------------- */ | ||
54 | |||
55 | /* | ||
56 | * The peripheral clocks. | ||
57 | */ | ||
58 | static struct clk pioA_clk = { | ||
59 | .name = "pioA_clk", | ||
60 | .pmc_mask = 1 << AT572D940HF_ID_PIOA, | ||
61 | .type = CLK_TYPE_PERIPHERAL, | ||
62 | }; | ||
63 | static struct clk pioB_clk = { | ||
64 | .name = "pioB_clk", | ||
65 | .pmc_mask = 1 << AT572D940HF_ID_PIOB, | ||
66 | .type = CLK_TYPE_PERIPHERAL, | ||
67 | }; | ||
68 | static struct clk pioC_clk = { | ||
69 | .name = "pioC_clk", | ||
70 | .pmc_mask = 1 << AT572D940HF_ID_PIOC, | ||
71 | .type = CLK_TYPE_PERIPHERAL, | ||
72 | }; | ||
73 | static struct clk macb_clk = { | ||
74 | .name = "macb_clk", | ||
75 | .pmc_mask = 1 << AT572D940HF_ID_EMAC, | ||
76 | .type = CLK_TYPE_PERIPHERAL, | ||
77 | }; | ||
78 | static struct clk usart0_clk = { | ||
79 | .name = "usart0_clk", | ||
80 | .pmc_mask = 1 << AT572D940HF_ID_US0, | ||
81 | .type = CLK_TYPE_PERIPHERAL, | ||
82 | }; | ||
83 | static struct clk usart1_clk = { | ||
84 | .name = "usart1_clk", | ||
85 | .pmc_mask = 1 << AT572D940HF_ID_US1, | ||
86 | .type = CLK_TYPE_PERIPHERAL, | ||
87 | }; | ||
88 | static struct clk usart2_clk = { | ||
89 | .name = "usart2_clk", | ||
90 | .pmc_mask = 1 << AT572D940HF_ID_US2, | ||
91 | .type = CLK_TYPE_PERIPHERAL, | ||
92 | }; | ||
93 | static struct clk mmc_clk = { | ||
94 | .name = "mci_clk", | ||
95 | .pmc_mask = 1 << AT572D940HF_ID_MCI, | ||
96 | .type = CLK_TYPE_PERIPHERAL, | ||
97 | }; | ||
98 | static struct clk udc_clk = { | ||
99 | .name = "udc_clk", | ||
100 | .pmc_mask = 1 << AT572D940HF_ID_UDP, | ||
101 | .type = CLK_TYPE_PERIPHERAL, | ||
102 | }; | ||
103 | static struct clk twi0_clk = { | ||
104 | .name = "twi0_clk", | ||
105 | .pmc_mask = 1 << AT572D940HF_ID_TWI0, | ||
106 | .type = CLK_TYPE_PERIPHERAL, | ||
107 | }; | ||
108 | static struct clk spi0_clk = { | ||
109 | .name = "spi0_clk", | ||
110 | .pmc_mask = 1 << AT572D940HF_ID_SPI0, | ||
111 | .type = CLK_TYPE_PERIPHERAL, | ||
112 | }; | ||
113 | static struct clk spi1_clk = { | ||
114 | .name = "spi1_clk", | ||
115 | .pmc_mask = 1 << AT572D940HF_ID_SPI1, | ||
116 | .type = CLK_TYPE_PERIPHERAL, | ||
117 | }; | ||
118 | static struct clk ssc0_clk = { | ||
119 | .name = "ssc0_clk", | ||
120 | .pmc_mask = 1 << AT572D940HF_ID_SSC0, | ||
121 | .type = CLK_TYPE_PERIPHERAL, | ||
122 | }; | ||
123 | static struct clk ssc1_clk = { | ||
124 | .name = "ssc1_clk", | ||
125 | .pmc_mask = 1 << AT572D940HF_ID_SSC1, | ||
126 | .type = CLK_TYPE_PERIPHERAL, | ||
127 | }; | ||
128 | static struct clk ssc2_clk = { | ||
129 | .name = "ssc2_clk", | ||
130 | .pmc_mask = 1 << AT572D940HF_ID_SSC2, | ||
131 | .type = CLK_TYPE_PERIPHERAL, | ||
132 | }; | ||
133 | static struct clk tc0_clk = { | ||
134 | .name = "tc0_clk", | ||
135 | .pmc_mask = 1 << AT572D940HF_ID_TC0, | ||
136 | .type = CLK_TYPE_PERIPHERAL, | ||
137 | }; | ||
138 | static struct clk tc1_clk = { | ||
139 | .name = "tc1_clk", | ||
140 | .pmc_mask = 1 << AT572D940HF_ID_TC1, | ||
141 | .type = CLK_TYPE_PERIPHERAL, | ||
142 | }; | ||
143 | static struct clk tc2_clk = { | ||
144 | .name = "tc2_clk", | ||
145 | .pmc_mask = 1 << AT572D940HF_ID_TC2, | ||
146 | .type = CLK_TYPE_PERIPHERAL, | ||
147 | }; | ||
148 | static struct clk ohci_clk = { | ||
149 | .name = "ohci_clk", | ||
150 | .pmc_mask = 1 << AT572D940HF_ID_UHP, | ||
151 | .type = CLK_TYPE_PERIPHERAL, | ||
152 | }; | ||
153 | static struct clk ssc3_clk = { | ||
154 | .name = "ssc3_clk", | ||
155 | .pmc_mask = 1 << AT572D940HF_ID_SSC3, | ||
156 | .type = CLK_TYPE_PERIPHERAL, | ||
157 | }; | ||
158 | static struct clk twi1_clk = { | ||
159 | .name = "twi1_clk", | ||
160 | .pmc_mask = 1 << AT572D940HF_ID_TWI1, | ||
161 | .type = CLK_TYPE_PERIPHERAL, | ||
162 | }; | ||
163 | static struct clk can0_clk = { | ||
164 | .name = "can0_clk", | ||
165 | .pmc_mask = 1 << AT572D940HF_ID_CAN0, | ||
166 | .type = CLK_TYPE_PERIPHERAL, | ||
167 | }; | ||
168 | static struct clk can1_clk = { | ||
169 | .name = "can1_clk", | ||
170 | .pmc_mask = 1 << AT572D940HF_ID_CAN1, | ||
171 | .type = CLK_TYPE_PERIPHERAL, | ||
172 | }; | ||
173 | static struct clk mAgicV_clk = { | ||
174 | .name = "mAgicV_clk", | ||
175 | .pmc_mask = 1 << AT572D940HF_ID_MSIRQ0, | ||
176 | .type = CLK_TYPE_PERIPHERAL, | ||
177 | }; | ||
178 | |||
179 | |||
180 | static struct clk *periph_clocks[] __initdata = { | ||
181 | &pioA_clk, | ||
182 | &pioB_clk, | ||
183 | &pioC_clk, | ||
184 | &macb_clk, | ||
185 | &usart0_clk, | ||
186 | &usart1_clk, | ||
187 | &usart2_clk, | ||
188 | &mmc_clk, | ||
189 | &udc_clk, | ||
190 | &twi0_clk, | ||
191 | &spi0_clk, | ||
192 | &spi1_clk, | ||
193 | &ssc0_clk, | ||
194 | &ssc1_clk, | ||
195 | &ssc2_clk, | ||
196 | &tc0_clk, | ||
197 | &tc1_clk, | ||
198 | &tc2_clk, | ||
199 | &ohci_clk, | ||
200 | &ssc3_clk, | ||
201 | &twi1_clk, | ||
202 | &can0_clk, | ||
203 | &can1_clk, | ||
204 | &mAgicV_clk, | ||
205 | /* irq0 .. irq2 */ | ||
206 | }; | ||
207 | |||
208 | /* | ||
209 | * The five programmable clocks. | ||
210 | * You must configure pin multiplexing to bring these signals out. | ||
211 | */ | ||
212 | static struct clk pck0 = { | ||
213 | .name = "pck0", | ||
214 | .pmc_mask = AT91_PMC_PCK0, | ||
215 | .type = CLK_TYPE_PROGRAMMABLE, | ||
216 | .id = 0, | ||
217 | }; | ||
218 | static struct clk pck1 = { | ||
219 | .name = "pck1", | ||
220 | .pmc_mask = AT91_PMC_PCK1, | ||
221 | .type = CLK_TYPE_PROGRAMMABLE, | ||
222 | .id = 1, | ||
223 | }; | ||
224 | static struct clk pck2 = { | ||
225 | .name = "pck2", | ||
226 | .pmc_mask = AT91_PMC_PCK2, | ||
227 | .type = CLK_TYPE_PROGRAMMABLE, | ||
228 | .id = 2, | ||
229 | }; | ||
230 | static struct clk pck3 = { | ||
231 | .name = "pck3", | ||
232 | .pmc_mask = AT91_PMC_PCK3, | ||
233 | .type = CLK_TYPE_PROGRAMMABLE, | ||
234 | .id = 3, | ||
235 | }; | ||
236 | |||
237 | static struct clk mAgicV_mem_clk = { | ||
238 | .name = "mAgicV_mem_clk", | ||
239 | .pmc_mask = AT91_PMC_PCK4, | ||
240 | .type = CLK_TYPE_PROGRAMMABLE, | ||
241 | .id = 4, | ||
242 | }; | ||
243 | |||
244 | /* HClocks */ | ||
245 | static struct clk hck0 = { | ||
246 | .name = "hck0", | ||
247 | .pmc_mask = AT91_PMC_HCK0, | ||
248 | .type = CLK_TYPE_SYSTEM, | ||
249 | .id = 0, | ||
250 | }; | ||
251 | static struct clk hck1 = { | ||
252 | .name = "hck1", | ||
253 | .pmc_mask = AT91_PMC_HCK1, | ||
254 | .type = CLK_TYPE_SYSTEM, | ||
255 | .id = 1, | ||
256 | }; | ||
257 | |||
258 | static void __init at572d940hf_register_clocks(void) | ||
259 | { | ||
260 | int i; | ||
261 | |||
262 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | ||
263 | clk_register(periph_clocks[i]); | ||
264 | |||
265 | clk_register(&pck0); | ||
266 | clk_register(&pck1); | ||
267 | clk_register(&pck2); | ||
268 | clk_register(&pck3); | ||
269 | clk_register(&mAgicV_mem_clk); | ||
270 | |||
271 | clk_register(&hck0); | ||
272 | clk_register(&hck1); | ||
273 | } | ||
274 | |||
275 | /* -------------------------------------------------------------------- | ||
276 | * GPIO | ||
277 | * -------------------------------------------------------------------- */ | ||
278 | |||
279 | static struct at91_gpio_bank at572d940hf_gpio[] = { | ||
280 | { | ||
281 | .id = AT572D940HF_ID_PIOA, | ||
282 | .offset = AT91_PIOA, | ||
283 | .clock = &pioA_clk, | ||
284 | }, { | ||
285 | .id = AT572D940HF_ID_PIOB, | ||
286 | .offset = AT91_PIOB, | ||
287 | .clock = &pioB_clk, | ||
288 | }, { | ||
289 | .id = AT572D940HF_ID_PIOC, | ||
290 | .offset = AT91_PIOC, | ||
291 | .clock = &pioC_clk, | ||
292 | } | ||
293 | }; | ||
294 | |||
295 | static void at572d940hf_reset(void) | ||
296 | { | ||
297 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | ||
298 | } | ||
299 | |||
300 | |||
301 | /* -------------------------------------------------------------------- | ||
302 | * AT572D940HF processor initialization | ||
303 | * -------------------------------------------------------------------- */ | ||
304 | |||
305 | void __init at572d940hf_initialize(unsigned long main_clock) | ||
306 | { | ||
307 | /* Map peripherals */ | ||
308 | iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc)); | ||
309 | |||
310 | at91_arch_reset = at572d940hf_reset; | ||
311 | at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1) | ||
312 | | (1 << AT572D940HF_ID_IRQ2); | ||
313 | |||
314 | /* Init clock subsystem */ | ||
315 | at91_clock_init(main_clock); | ||
316 | |||
317 | /* Register the processor-specific clocks */ | ||
318 | at572d940hf_register_clocks(); | ||
319 | |||
320 | /* Register GPIO subsystem */ | ||
321 | at91_gpio_init(at572d940hf_gpio, 3); | ||
322 | } | ||
323 | |||
324 | /* -------------------------------------------------------------------- | ||
325 | * Interrupt initialization | ||
326 | * -------------------------------------------------------------------- */ | ||
327 | |||
328 | /* | ||
329 | * The default interrupt priority levels (0 = lowest, 7 = highest). | ||
330 | */ | ||
331 | static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = { | ||
332 | 7, /* Advanced Interrupt Controller */ | ||
333 | 7, /* System Peripherals */ | ||
334 | 0, /* Parallel IO Controller A */ | ||
335 | 0, /* Parallel IO Controller B */ | ||
336 | 0, /* Parallel IO Controller C */ | ||
337 | 3, /* Ethernet */ | ||
338 | 6, /* USART 0 */ | ||
339 | 6, /* USART 1 */ | ||
340 | 6, /* USART 2 */ | ||
341 | 0, /* Multimedia Card Interface */ | ||
342 | 4, /* USB Device Port */ | ||
343 | 0, /* Two-Wire Interface 0 */ | ||
344 | 6, /* Serial Peripheral Interface 0 */ | ||
345 | 6, /* Serial Peripheral Interface 1 */ | ||
346 | 5, /* Serial Synchronous Controller 0 */ | ||
347 | 5, /* Serial Synchronous Controller 1 */ | ||
348 | 5, /* Serial Synchronous Controller 2 */ | ||
349 | 0, /* Timer Counter 0 */ | ||
350 | 0, /* Timer Counter 1 */ | ||
351 | 0, /* Timer Counter 2 */ | ||
352 | 3, /* USB Host port */ | ||
353 | 3, /* Serial Synchronous Controller 3 */ | ||
354 | 0, /* Two-Wire Interface 1 */ | ||
355 | 0, /* CAN Controller 0 */ | ||
356 | 0, /* CAN Controller 1 */ | ||
357 | 0, /* mAgicV HALT line */ | ||
358 | 0, /* mAgicV SIRQ0 line */ | ||
359 | 0, /* mAgicV exception line */ | ||
360 | 0, /* mAgicV end of DMA line */ | ||
361 | 0, /* Advanced Interrupt Controller */ | ||
362 | 0, /* Advanced Interrupt Controller */ | ||
363 | 0, /* Advanced Interrupt Controller */ | ||
364 | }; | ||
365 | |||
366 | void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS]) | ||
367 | { | ||
368 | if (!priority) | ||
369 | priority = at572d940hf_default_irq_priority; | ||
370 | |||
371 | /* Initialize the AIC interrupt controller */ | ||
372 | at91_aic_init(priority); | ||
373 | |||
374 | /* Enable GPIO interrupts */ | ||
375 | at91_gpio_irq_setup(); | ||
376 | } | ||
377 | |||
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c new file mode 100644 index 000000000000..0fc20a240782 --- /dev/null +++ b/arch/arm/mach-at91/at572d940hf_devices.c | |||
@@ -0,0 +1,970 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/at572d940hf_devices.c | ||
3 | * | ||
4 | * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com> | ||
5 | * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> | ||
6 | * Copyright (C) 2005 David Brownell | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #include <asm/mach/arch.h> | ||
25 | #include <asm/mach/map.h> | ||
26 | |||
27 | #include <linux/dma-mapping.h> | ||
28 | #include <linux/platform_device.h> | ||
29 | |||
30 | #include <mach/board.h> | ||
31 | #include <mach/gpio.h> | ||
32 | #include <mach/at572d940hf.h> | ||
33 | #include <mach/at572d940hf_matrix.h> | ||
34 | #include <mach/at91sam9_smc.h> | ||
35 | |||
36 | #include "generic.h" | ||
37 | #include "sam9_smc.h" | ||
38 | |||
39 | |||
40 | /* -------------------------------------------------------------------- | ||
41 | * USB Host | ||
42 | * -------------------------------------------------------------------- */ | ||
43 | |||
44 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
45 | static u64 ohci_dmamask = DMA_BIT_MASK(32); | ||
46 | static struct at91_usbh_data usbh_data; | ||
47 | |||
48 | static struct resource usbh_resources[] = { | ||
49 | [0] = { | ||
50 | .start = AT572D940HF_UHP_BASE, | ||
51 | .end = AT572D940HF_UHP_BASE + SZ_1M - 1, | ||
52 | .flags = IORESOURCE_MEM, | ||
53 | }, | ||
54 | [1] = { | ||
55 | .start = AT572D940HF_ID_UHP, | ||
56 | .end = AT572D940HF_ID_UHP, | ||
57 | .flags = IORESOURCE_IRQ, | ||
58 | }, | ||
59 | }; | ||
60 | |||
61 | static struct platform_device at572d940hf_usbh_device = { | ||
62 | .name = "at91_ohci", | ||
63 | .id = -1, | ||
64 | .dev = { | ||
65 | .dma_mask = &ohci_dmamask, | ||
66 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
67 | .platform_data = &usbh_data, | ||
68 | }, | ||
69 | .resource = usbh_resources, | ||
70 | .num_resources = ARRAY_SIZE(usbh_resources), | ||
71 | }; | ||
72 | |||
73 | void __init at91_add_device_usbh(struct at91_usbh_data *data) | ||
74 | { | ||
75 | if (!data) | ||
76 | return; | ||
77 | |||
78 | usbh_data = *data; | ||
79 | platform_device_register(&at572d940hf_usbh_device); | ||
80 | |||
81 | } | ||
82 | #else | ||
83 | void __init at91_add_device_usbh(struct at91_usbh_data *data) {} | ||
84 | #endif | ||
85 | |||
86 | |||
87 | /* -------------------------------------------------------------------- | ||
88 | * USB Device (Gadget) | ||
89 | * -------------------------------------------------------------------- */ | ||
90 | |||
91 | #ifdef CONFIG_USB_GADGET_AT91 | ||
92 | static struct at91_udc_data udc_data; | ||
93 | |||
94 | static struct resource udc_resources[] = { | ||
95 | [0] = { | ||
96 | .start = AT572D940HF_BASE_UDP, | ||
97 | .end = AT572D940HF_BASE_UDP + SZ_16K - 1, | ||
98 | .flags = IORESOURCE_MEM, | ||
99 | }, | ||
100 | [1] = { | ||
101 | .start = AT572D940HF_ID_UDP, | ||
102 | .end = AT572D940HF_ID_UDP, | ||
103 | .flags = IORESOURCE_IRQ, | ||
104 | }, | ||
105 | }; | ||
106 | |||
107 | static struct platform_device at572d940hf_udc_device = { | ||
108 | .name = "at91_udc", | ||
109 | .id = -1, | ||
110 | .dev = { | ||
111 | .platform_data = &udc_data, | ||
112 | }, | ||
113 | .resource = udc_resources, | ||
114 | .num_resources = ARRAY_SIZE(udc_resources), | ||
115 | }; | ||
116 | |||
117 | void __init at91_add_device_udc(struct at91_udc_data *data) | ||
118 | { | ||
119 | if (!data) | ||
120 | return; | ||
121 | |||
122 | if (data->vbus_pin) { | ||
123 | at91_set_gpio_input(data->vbus_pin, 0); | ||
124 | at91_set_deglitch(data->vbus_pin, 1); | ||
125 | } | ||
126 | |||
127 | /* Pullup pin is handled internally */ | ||
128 | |||
129 | udc_data = *data; | ||
130 | platform_device_register(&at572d940hf_udc_device); | ||
131 | } | ||
132 | #else | ||
133 | void __init at91_add_device_udc(struct at91_udc_data *data) {} | ||
134 | #endif | ||
135 | |||
136 | |||
137 | /* -------------------------------------------------------------------- | ||
138 | * Ethernet | ||
139 | * -------------------------------------------------------------------- */ | ||
140 | |||
141 | #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) | ||
142 | static u64 eth_dmamask = DMA_BIT_MASK(32); | ||
143 | static struct at91_eth_data eth_data; | ||
144 | |||
145 | static struct resource eth_resources[] = { | ||
146 | [0] = { | ||
147 | .start = AT572D940HF_BASE_EMAC, | ||
148 | .end = AT572D940HF_BASE_EMAC + SZ_16K - 1, | ||
149 | .flags = IORESOURCE_MEM, | ||
150 | }, | ||
151 | [1] = { | ||
152 | .start = AT572D940HF_ID_EMAC, | ||
153 | .end = AT572D940HF_ID_EMAC, | ||
154 | .flags = IORESOURCE_IRQ, | ||
155 | }, | ||
156 | }; | ||
157 | |||
158 | static struct platform_device at572d940hf_eth_device = { | ||
159 | .name = "macb", | ||
160 | .id = -1, | ||
161 | .dev = { | ||
162 | .dma_mask = ð_dmamask, | ||
163 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
164 | .platform_data = ð_data, | ||
165 | }, | ||
166 | .resource = eth_resources, | ||
167 | .num_resources = ARRAY_SIZE(eth_resources), | ||
168 | }; | ||
169 | |||
170 | void __init at91_add_device_eth(struct at91_eth_data *data) | ||
171 | { | ||
172 | if (!data) | ||
173 | return; | ||
174 | |||
175 | if (data->phy_irq_pin) { | ||
176 | at91_set_gpio_input(data->phy_irq_pin, 0); | ||
177 | at91_set_deglitch(data->phy_irq_pin, 1); | ||
178 | } | ||
179 | |||
180 | /* Only RMII is supported */ | ||
181 | data->is_rmii = 1; | ||
182 | |||
183 | /* Pins used for RMII */ | ||
184 | at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */ | ||
185 | at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ | ||
186 | at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */ | ||
187 | at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */ | ||
188 | at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */ | ||
189 | at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */ | ||
190 | at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */ | ||
191 | at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */ | ||
192 | at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */ | ||
193 | at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */ | ||
194 | |||
195 | eth_data = *data; | ||
196 | platform_device_register(&at572d940hf_eth_device); | ||
197 | } | ||
198 | #else | ||
199 | void __init at91_add_device_eth(struct at91_eth_data *data) {} | ||
200 | #endif | ||
201 | |||
202 | |||
203 | /* -------------------------------------------------------------------- | ||
204 | * MMC / SD | ||
205 | * -------------------------------------------------------------------- */ | ||
206 | |||
207 | #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) | ||
208 | static u64 mmc_dmamask = DMA_BIT_MASK(32); | ||
209 | static struct at91_mmc_data mmc_data; | ||
210 | |||
211 | static struct resource mmc_resources[] = { | ||
212 | [0] = { | ||
213 | .start = AT572D940HF_BASE_MCI, | ||
214 | .end = AT572D940HF_BASE_MCI + SZ_16K - 1, | ||
215 | .flags = IORESOURCE_MEM, | ||
216 | }, | ||
217 | [1] = { | ||
218 | .start = AT572D940HF_ID_MCI, | ||
219 | .end = AT572D940HF_ID_MCI, | ||
220 | .flags = IORESOURCE_IRQ, | ||
221 | }, | ||
222 | }; | ||
223 | |||
224 | static struct platform_device at572d940hf_mmc_device = { | ||
225 | .name = "at91_mci", | ||
226 | .id = -1, | ||
227 | .dev = { | ||
228 | .dma_mask = &mmc_dmamask, | ||
229 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
230 | .platform_data = &mmc_data, | ||
231 | }, | ||
232 | .resource = mmc_resources, | ||
233 | .num_resources = ARRAY_SIZE(mmc_resources), | ||
234 | }; | ||
235 | |||
236 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) | ||
237 | { | ||
238 | if (!data) | ||
239 | return; | ||
240 | |||
241 | /* input/irq */ | ||
242 | if (data->det_pin) { | ||
243 | at91_set_gpio_input(data->det_pin, 1); | ||
244 | at91_set_deglitch(data->det_pin, 1); | ||
245 | } | ||
246 | if (data->wp_pin) | ||
247 | at91_set_gpio_input(data->wp_pin, 1); | ||
248 | if (data->vcc_pin) | ||
249 | at91_set_gpio_output(data->vcc_pin, 0); | ||
250 | |||
251 | /* CLK */ | ||
252 | at91_set_A_periph(AT91_PIN_PC22, 0); | ||
253 | |||
254 | /* CMD */ | ||
255 | at91_set_A_periph(AT91_PIN_PC23, 1); | ||
256 | |||
257 | /* DAT0, maybe DAT1..DAT3 */ | ||
258 | at91_set_A_periph(AT91_PIN_PC24, 1); | ||
259 | if (data->wire4) { | ||
260 | at91_set_A_periph(AT91_PIN_PC25, 1); | ||
261 | at91_set_A_periph(AT91_PIN_PC26, 1); | ||
262 | at91_set_A_periph(AT91_PIN_PC27, 1); | ||
263 | } | ||
264 | |||
265 | mmc_data = *data; | ||
266 | platform_device_register(&at572d940hf_mmc_device); | ||
267 | } | ||
268 | #else | ||
269 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} | ||
270 | #endif | ||
271 | |||
272 | |||
273 | /* -------------------------------------------------------------------- | ||
274 | * NAND / SmartMedia | ||
275 | * -------------------------------------------------------------------- */ | ||
276 | |||
277 | #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) | ||
278 | static struct atmel_nand_data nand_data; | ||
279 | |||
280 | #define NAND_BASE AT91_CHIPSELECT_3 | ||
281 | |||
282 | static struct resource nand_resources[] = { | ||
283 | { | ||
284 | .start = NAND_BASE, | ||
285 | .end = NAND_BASE + SZ_256M - 1, | ||
286 | .flags = IORESOURCE_MEM, | ||
287 | } | ||
288 | }; | ||
289 | |||
290 | static struct platform_device at572d940hf_nand_device = { | ||
291 | .name = "atmel_nand", | ||
292 | .id = -1, | ||
293 | .dev = { | ||
294 | .platform_data = &nand_data, | ||
295 | }, | ||
296 | .resource = nand_resources, | ||
297 | .num_resources = ARRAY_SIZE(nand_resources), | ||
298 | }; | ||
299 | |||
300 | void __init at91_add_device_nand(struct atmel_nand_data *data) | ||
301 | { | ||
302 | unsigned long csa; | ||
303 | |||
304 | if (!data) | ||
305 | return; | ||
306 | |||
307 | csa = at91_sys_read(AT91_MATRIX_EBICSA); | ||
308 | at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); | ||
309 | |||
310 | /* enable pin */ | ||
311 | if (data->enable_pin) | ||
312 | at91_set_gpio_output(data->enable_pin, 1); | ||
313 | |||
314 | /* ready/busy pin */ | ||
315 | if (data->rdy_pin) | ||
316 | at91_set_gpio_input(data->rdy_pin, 1); | ||
317 | |||
318 | /* card detect pin */ | ||
319 | if (data->det_pin) | ||
320 | at91_set_gpio_input(data->det_pin, 1); | ||
321 | |||
322 | at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */ | ||
323 | at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */ | ||
324 | at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */ | ||
325 | |||
326 | nand_data = *data; | ||
327 | platform_device_register(&at572d940hf_nand_device); | ||
328 | } | ||
329 | |||
330 | #else | ||
331 | void __init at91_add_device_nand(struct atmel_nand_data *data) {} | ||
332 | #endif | ||
333 | |||
334 | |||
335 | /* -------------------------------------------------------------------- | ||
336 | * TWI (i2c) | ||
337 | * -------------------------------------------------------------------- */ | ||
338 | |||
339 | /* | ||
340 | * Prefer the GPIO code since the TWI controller isn't robust | ||
341 | * (gets overruns and underruns under load) and can only issue | ||
342 | * repeated STARTs in one scenario (the driver doesn't yet handle them). | ||
343 | */ | ||
344 | |||
345 | #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) | ||
346 | |||
347 | static struct i2c_gpio_platform_data pdata = { | ||
348 | .sda_pin = AT91_PIN_PC7, | ||
349 | .sda_is_open_drain = 1, | ||
350 | .scl_pin = AT91_PIN_PC8, | ||
351 | .scl_is_open_drain = 1, | ||
352 | .udelay = 2, /* ~100 kHz */ | ||
353 | }; | ||
354 | |||
355 | static struct platform_device at572d940hf_twi_device { | ||
356 | .name = "i2c-gpio", | ||
357 | .id = -1, | ||
358 | .dev.platform_data = &pdata, | ||
359 | }; | ||
360 | |||
361 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) | ||
362 | { | ||
363 | at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */ | ||
364 | at91_set_multi_drive(AT91_PIN_PC7, 1); | ||
365 | |||
366 | at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */ | ||
367 | at91_set_multi_drive(AT91_PIN_PC8, 1); | ||
368 | |||
369 | i2c_register_board_info(0, devices, nr_devices); | ||
370 | platform_device_register(&at572d940hf_twi_device); | ||
371 | } | ||
372 | |||
373 | #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) | ||
374 | |||
375 | static struct resource twi0_resources[] = { | ||
376 | [0] = { | ||
377 | .start = AT572D940HF_BASE_TWI0, | ||
378 | .end = AT572D940HF_BASE_TWI0 + SZ_16K - 1, | ||
379 | .flags = IORESOURCE_MEM, | ||
380 | }, | ||
381 | [1] = { | ||
382 | .start = AT572D940HF_ID_TWI0, | ||
383 | .end = AT572D940HF_ID_TWI0, | ||
384 | .flags = IORESOURCE_IRQ, | ||
385 | }, | ||
386 | }; | ||
387 | |||
388 | static struct platform_device at572d940hf_twi0_device = { | ||
389 | .name = "at91_i2c", | ||
390 | .id = 0, | ||
391 | .resource = twi0_resources, | ||
392 | .num_resources = ARRAY_SIZE(twi0_resources), | ||
393 | }; | ||
394 | |||
395 | static struct resource twi1_resources[] = { | ||
396 | [0] = { | ||
397 | .start = AT572D940HF_BASE_TWI1, | ||
398 | .end = AT572D940HF_BASE_TWI1 + SZ_16K - 1, | ||
399 | .flags = IORESOURCE_MEM, | ||
400 | }, | ||
401 | [1] = { | ||
402 | .start = AT572D940HF_ID_TWI1, | ||
403 | .end = AT572D940HF_ID_TWI1, | ||
404 | .flags = IORESOURCE_IRQ, | ||
405 | }, | ||
406 | }; | ||
407 | |||
408 | static struct platform_device at572d940hf_twi1_device = { | ||
409 | .name = "at91_i2c", | ||
410 | .id = 1, | ||
411 | .resource = twi1_resources, | ||
412 | .num_resources = ARRAY_SIZE(twi1_resources), | ||
413 | }; | ||
414 | |||
415 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) | ||
416 | { | ||
417 | /* pins used for TWI0 interface */ | ||
418 | at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */ | ||
419 | at91_set_multi_drive(AT91_PIN_PC7, 1); | ||
420 | |||
421 | at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */ | ||
422 | at91_set_multi_drive(AT91_PIN_PC8, 1); | ||
423 | |||
424 | /* pins used for TWI1 interface */ | ||
425 | at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */ | ||
426 | at91_set_multi_drive(AT91_PIN_PC20, 1); | ||
427 | |||
428 | at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */ | ||
429 | at91_set_multi_drive(AT91_PIN_PC21, 1); | ||
430 | |||
431 | i2c_register_board_info(0, devices, nr_devices); | ||
432 | platform_device_register(&at572d940hf_twi0_device); | ||
433 | platform_device_register(&at572d940hf_twi1_device); | ||
434 | } | ||
435 | #else | ||
436 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} | ||
437 | #endif | ||
438 | |||
439 | |||
440 | /* -------------------------------------------------------------------- | ||
441 | * SPI | ||
442 | * -------------------------------------------------------------------- */ | ||
443 | |||
444 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) | ||
445 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
446 | |||
447 | static struct resource spi0_resources[] = { | ||
448 | [0] = { | ||
449 | .start = AT572D940HF_BASE_SPI0, | ||
450 | .end = AT572D940HF_BASE_SPI0 + SZ_16K - 1, | ||
451 | .flags = IORESOURCE_MEM, | ||
452 | }, | ||
453 | [1] = { | ||
454 | .start = AT572D940HF_ID_SPI0, | ||
455 | .end = AT572D940HF_ID_SPI0, | ||
456 | .flags = IORESOURCE_IRQ, | ||
457 | }, | ||
458 | }; | ||
459 | |||
460 | static struct platform_device at572d940hf_spi0_device = { | ||
461 | .name = "atmel_spi", | ||
462 | .id = 0, | ||
463 | .dev = { | ||
464 | .dma_mask = &spi_dmamask, | ||
465 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
466 | }, | ||
467 | .resource = spi0_resources, | ||
468 | .num_resources = ARRAY_SIZE(spi0_resources), | ||
469 | }; | ||
470 | |||
471 | static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; | ||
472 | |||
473 | static struct resource spi1_resources[] = { | ||
474 | [0] = { | ||
475 | .start = AT572D940HF_BASE_SPI1, | ||
476 | .end = AT572D940HF_BASE_SPI1 + SZ_16K - 1, | ||
477 | .flags = IORESOURCE_MEM, | ||
478 | }, | ||
479 | [1] = { | ||
480 | .start = AT572D940HF_ID_SPI1, | ||
481 | .end = AT572D940HF_ID_SPI1, | ||
482 | .flags = IORESOURCE_IRQ, | ||
483 | }, | ||
484 | }; | ||
485 | |||
486 | static struct platform_device at572d940hf_spi1_device = { | ||
487 | .name = "atmel_spi", | ||
488 | .id = 1, | ||
489 | .dev = { | ||
490 | .dma_mask = &spi_dmamask, | ||
491 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
492 | }, | ||
493 | .resource = spi1_resources, | ||
494 | .num_resources = ARRAY_SIZE(spi1_resources), | ||
495 | }; | ||
496 | |||
497 | static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 }; | ||
498 | |||
499 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | ||
500 | { | ||
501 | int i; | ||
502 | unsigned long cs_pin; | ||
503 | short enable_spi0 = 0; | ||
504 | short enable_spi1 = 0; | ||
505 | |||
506 | /* Choose SPI chip-selects */ | ||
507 | for (i = 0; i < nr_devices; i++) { | ||
508 | if (devices[i].controller_data) | ||
509 | cs_pin = (unsigned long) devices[i].controller_data; | ||
510 | else if (devices[i].bus_num == 0) | ||
511 | cs_pin = spi0_standard_cs[devices[i].chip_select]; | ||
512 | else | ||
513 | cs_pin = spi1_standard_cs[devices[i].chip_select]; | ||
514 | |||
515 | if (devices[i].bus_num == 0) | ||
516 | enable_spi0 = 1; | ||
517 | else | ||
518 | enable_spi1 = 1; | ||
519 | |||
520 | /* enable chip-select pin */ | ||
521 | at91_set_gpio_output(cs_pin, 1); | ||
522 | |||
523 | /* pass chip-select pin to driver */ | ||
524 | devices[i].controller_data = (void *) cs_pin; | ||
525 | } | ||
526 | |||
527 | spi_register_board_info(devices, nr_devices); | ||
528 | |||
529 | /* Configure SPI bus(es) */ | ||
530 | if (enable_spi0) { | ||
531 | at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ | ||
532 | at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ | ||
533 | at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ | ||
534 | |||
535 | at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk"); | ||
536 | platform_device_register(&at572d940hf_spi0_device); | ||
537 | } | ||
538 | if (enable_spi1) { | ||
539 | at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */ | ||
540 | at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */ | ||
541 | at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */ | ||
542 | |||
543 | at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk"); | ||
544 | platform_device_register(&at572d940hf_spi1_device); | ||
545 | } | ||
546 | } | ||
547 | #else | ||
548 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} | ||
549 | #endif | ||
550 | |||
551 | |||
552 | /* -------------------------------------------------------------------- | ||
553 | * Timer/Counter blocks | ||
554 | * -------------------------------------------------------------------- */ | ||
555 | |||
556 | #ifdef CONFIG_ATMEL_TCLIB | ||
557 | |||
558 | static struct resource tcb_resources[] = { | ||
559 | [0] = { | ||
560 | .start = AT572D940HF_BASE_TCB, | ||
561 | .end = AT572D940HF_BASE_TCB + SZ_16K - 1, | ||
562 | .flags = IORESOURCE_MEM, | ||
563 | }, | ||
564 | [1] = { | ||
565 | .start = AT572D940HF_ID_TC0, | ||
566 | .end = AT572D940HF_ID_TC0, | ||
567 | .flags = IORESOURCE_IRQ, | ||
568 | }, | ||
569 | [2] = { | ||
570 | .start = AT572D940HF_ID_TC1, | ||
571 | .end = AT572D940HF_ID_TC1, | ||
572 | .flags = IORESOURCE_IRQ, | ||
573 | }, | ||
574 | [3] = { | ||
575 | .start = AT572D940HF_ID_TC2, | ||
576 | .end = AT572D940HF_ID_TC2, | ||
577 | .flags = IORESOURCE_IRQ, | ||
578 | }, | ||
579 | }; | ||
580 | |||
581 | static struct platform_device at572d940hf_tcb_device = { | ||
582 | .name = "atmel_tcb", | ||
583 | .id = 0, | ||
584 | .resource = tcb_resources, | ||
585 | .num_resources = ARRAY_SIZE(tcb_resources), | ||
586 | }; | ||
587 | |||
588 | static void __init at91_add_device_tc(void) | ||
589 | { | ||
590 | /* this chip has a separate clock and irq for each TC channel */ | ||
591 | at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk"); | ||
592 | at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk"); | ||
593 | at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk"); | ||
594 | platform_device_register(&at572d940hf_tcb_device); | ||
595 | } | ||
596 | #else | ||
597 | static void __init at91_add_device_tc(void) { } | ||
598 | #endif | ||
599 | |||
600 | |||
601 | /* -------------------------------------------------------------------- | ||
602 | * RTT | ||
603 | * -------------------------------------------------------------------- */ | ||
604 | |||
605 | static struct resource rtt_resources[] = { | ||
606 | { | ||
607 | .start = AT91_BASE_SYS + AT91_RTT, | ||
608 | .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, | ||
609 | .flags = IORESOURCE_MEM, | ||
610 | } | ||
611 | }; | ||
612 | |||
613 | static struct platform_device at572d940hf_rtt_device = { | ||
614 | .name = "at91_rtt", | ||
615 | .id = 0, | ||
616 | .resource = rtt_resources, | ||
617 | .num_resources = ARRAY_SIZE(rtt_resources), | ||
618 | }; | ||
619 | |||
620 | static void __init at91_add_device_rtt(void) | ||
621 | { | ||
622 | platform_device_register(&at572d940hf_rtt_device); | ||
623 | } | ||
624 | |||
625 | |||
626 | /* -------------------------------------------------------------------- | ||
627 | * Watchdog | ||
628 | * -------------------------------------------------------------------- */ | ||
629 | |||
630 | #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) | ||
631 | static struct platform_device at572d940hf_wdt_device = { | ||
632 | .name = "at91_wdt", | ||
633 | .id = -1, | ||
634 | .num_resources = 0, | ||
635 | }; | ||
636 | |||
637 | static void __init at91_add_device_watchdog(void) | ||
638 | { | ||
639 | platform_device_register(&at572d940hf_wdt_device); | ||
640 | } | ||
641 | #else | ||
642 | static void __init at91_add_device_watchdog(void) {} | ||
643 | #endif | ||
644 | |||
645 | |||
646 | /* -------------------------------------------------------------------- | ||
647 | * UART | ||
648 | * -------------------------------------------------------------------- */ | ||
649 | |||
650 | #if defined(CONFIG_SERIAL_ATMEL) | ||
651 | static struct resource dbgu_resources[] = { | ||
652 | [0] = { | ||
653 | .start = AT91_VA_BASE_SYS + AT91_DBGU, | ||
654 | .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, | ||
655 | .flags = IORESOURCE_MEM, | ||
656 | }, | ||
657 | [1] = { | ||
658 | .start = AT91_ID_SYS, | ||
659 | .end = AT91_ID_SYS, | ||
660 | .flags = IORESOURCE_IRQ, | ||
661 | }, | ||
662 | }; | ||
663 | |||
664 | static struct atmel_uart_data dbgu_data = { | ||
665 | .use_dma_tx = 0, | ||
666 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | ||
667 | .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), | ||
668 | }; | ||
669 | |||
670 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | ||
671 | |||
672 | static struct platform_device at572d940hf_dbgu_device = { | ||
673 | .name = "atmel_usart", | ||
674 | .id = 0, | ||
675 | .dev = { | ||
676 | .dma_mask = &dbgu_dmamask, | ||
677 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
678 | .platform_data = &dbgu_data, | ||
679 | }, | ||
680 | .resource = dbgu_resources, | ||
681 | .num_resources = ARRAY_SIZE(dbgu_resources), | ||
682 | }; | ||
683 | |||
684 | static inline void configure_dbgu_pins(void) | ||
685 | { | ||
686 | at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ | ||
687 | at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ | ||
688 | } | ||
689 | |||
690 | static struct resource uart0_resources[] = { | ||
691 | [0] = { | ||
692 | .start = AT572D940HF_BASE_US0, | ||
693 | .end = AT572D940HF_BASE_US0 + SZ_16K - 1, | ||
694 | .flags = IORESOURCE_MEM, | ||
695 | }, | ||
696 | [1] = { | ||
697 | .start = AT572D940HF_ID_US0, | ||
698 | .end = AT572D940HF_ID_US0, | ||
699 | .flags = IORESOURCE_IRQ, | ||
700 | }, | ||
701 | }; | ||
702 | |||
703 | static struct atmel_uart_data uart0_data = { | ||
704 | .use_dma_tx = 1, | ||
705 | .use_dma_rx = 1, | ||
706 | }; | ||
707 | |||
708 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | ||
709 | |||
710 | static struct platform_device at572d940hf_uart0_device = { | ||
711 | .name = "atmel_usart", | ||
712 | .id = 1, | ||
713 | .dev = { | ||
714 | .dma_mask = &uart0_dmamask, | ||
715 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
716 | .platform_data = &uart0_data, | ||
717 | }, | ||
718 | .resource = uart0_resources, | ||
719 | .num_resources = ARRAY_SIZE(uart0_resources), | ||
720 | }; | ||
721 | |||
722 | static inline void configure_usart0_pins(unsigned pins) | ||
723 | { | ||
724 | at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */ | ||
725 | at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ | ||
726 | |||
727 | if (pins & ATMEL_UART_RTS) | ||
728 | at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */ | ||
729 | if (pins & ATMEL_UART_CTS) | ||
730 | at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */ | ||
731 | } | ||
732 | |||
733 | static struct resource uart1_resources[] = { | ||
734 | [0] = { | ||
735 | .start = AT572D940HF_BASE_US1, | ||
736 | .end = AT572D940HF_BASE_US1 + SZ_16K - 1, | ||
737 | .flags = IORESOURCE_MEM, | ||
738 | }, | ||
739 | [1] = { | ||
740 | .start = AT572D940HF_ID_US1, | ||
741 | .end = AT572D940HF_ID_US1, | ||
742 | .flags = IORESOURCE_IRQ, | ||
743 | }, | ||
744 | }; | ||
745 | |||
746 | static struct atmel_uart_data uart1_data = { | ||
747 | .use_dma_tx = 1, | ||
748 | .use_dma_rx = 1, | ||
749 | }; | ||
750 | |||
751 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | ||
752 | |||
753 | static struct platform_device at572d940hf_uart1_device = { | ||
754 | .name = "atmel_usart", | ||
755 | .id = 2, | ||
756 | .dev = { | ||
757 | .dma_mask = &uart1_dmamask, | ||
758 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
759 | .platform_data = &uart1_data, | ||
760 | }, | ||
761 | .resource = uart1_resources, | ||
762 | .num_resources = ARRAY_SIZE(uart1_resources), | ||
763 | }; | ||
764 | |||
765 | static inline void configure_usart1_pins(unsigned pins) | ||
766 | { | ||
767 | at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */ | ||
768 | at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */ | ||
769 | |||
770 | if (pins & ATMEL_UART_RTS) | ||
771 | at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */ | ||
772 | if (pins & ATMEL_UART_CTS) | ||
773 | at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */ | ||
774 | } | ||
775 | |||
776 | static struct resource uart2_resources[] = { | ||
777 | [0] = { | ||
778 | .start = AT572D940HF_BASE_US2, | ||
779 | .end = AT572D940HF_BASE_US2 + SZ_16K - 1, | ||
780 | .flags = IORESOURCE_MEM, | ||
781 | }, | ||
782 | [1] = { | ||
783 | .start = AT572D940HF_ID_US2, | ||
784 | .end = AT572D940HF_ID_US2, | ||
785 | .flags = IORESOURCE_IRQ, | ||
786 | }, | ||
787 | }; | ||
788 | |||
789 | static struct atmel_uart_data uart2_data = { | ||
790 | .use_dma_tx = 1, | ||
791 | .use_dma_rx = 1, | ||
792 | }; | ||
793 | |||
794 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | ||
795 | |||
796 | static struct platform_device at572d940hf_uart2_device = { | ||
797 | .name = "atmel_usart", | ||
798 | .id = 3, | ||
799 | .dev = { | ||
800 | .dma_mask = &uart2_dmamask, | ||
801 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
802 | .platform_data = &uart2_data, | ||
803 | }, | ||
804 | .resource = uart2_resources, | ||
805 | .num_resources = ARRAY_SIZE(uart2_resources), | ||
806 | }; | ||
807 | |||
808 | static inline void configure_usart2_pins(unsigned pins) | ||
809 | { | ||
810 | at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */ | ||
811 | at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */ | ||
812 | |||
813 | if (pins & ATMEL_UART_RTS) | ||
814 | at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */ | ||
815 | if (pins & ATMEL_UART_CTS) | ||
816 | at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */ | ||
817 | } | ||
818 | |||
819 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | ||
820 | struct platform_device *atmel_default_console_device; /* the serial console device */ | ||
821 | |||
822 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | ||
823 | { | ||
824 | struct platform_device *pdev; | ||
825 | |||
826 | switch (id) { | ||
827 | case 0: /* DBGU */ | ||
828 | pdev = &at572d940hf_dbgu_device; | ||
829 | configure_dbgu_pins(); | ||
830 | at91_clock_associate("mck", &pdev->dev, "usart"); | ||
831 | break; | ||
832 | case AT572D940HF_ID_US0: | ||
833 | pdev = &at572d940hf_uart0_device; | ||
834 | configure_usart0_pins(pins); | ||
835 | at91_clock_associate("usart0_clk", &pdev->dev, "usart"); | ||
836 | break; | ||
837 | case AT572D940HF_ID_US1: | ||
838 | pdev = &at572d940hf_uart1_device; | ||
839 | configure_usart1_pins(pins); | ||
840 | at91_clock_associate("usart1_clk", &pdev->dev, "usart"); | ||
841 | break; | ||
842 | case AT572D940HF_ID_US2: | ||
843 | pdev = &at572d940hf_uart2_device; | ||
844 | configure_usart2_pins(pins); | ||
845 | at91_clock_associate("usart2_clk", &pdev->dev, "usart"); | ||
846 | break; | ||
847 | default: | ||
848 | return; | ||
849 | } | ||
850 | pdev->id = portnr; /* update to mapped ID */ | ||
851 | |||
852 | if (portnr < ATMEL_MAX_UART) | ||
853 | at91_uarts[portnr] = pdev; | ||
854 | } | ||
855 | |||
856 | void __init at91_set_serial_console(unsigned portnr) | ||
857 | { | ||
858 | if (portnr < ATMEL_MAX_UART) | ||
859 | atmel_default_console_device = at91_uarts[portnr]; | ||
860 | } | ||
861 | |||
862 | void __init at91_add_device_serial(void) | ||
863 | { | ||
864 | int i; | ||
865 | |||
866 | for (i = 0; i < ATMEL_MAX_UART; i++) { | ||
867 | if (at91_uarts[i]) | ||
868 | platform_device_register(at91_uarts[i]); | ||
869 | } | ||
870 | |||
871 | if (!atmel_default_console_device) | ||
872 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
873 | } | ||
874 | |||
875 | #else | ||
876 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | ||
877 | void __init at91_set_serial_console(unsigned portnr) {} | ||
878 | void __init at91_add_device_serial(void) {} | ||
879 | #endif | ||
880 | |||
881 | |||
882 | /* -------------------------------------------------------------------- | ||
883 | * mAgic | ||
884 | * -------------------------------------------------------------------- */ | ||
885 | |||
886 | #ifdef CONFIG_MAGICV | ||
887 | static struct resource mAgic_resources[] = { | ||
888 | { | ||
889 | .start = AT91_MAGIC_PM_BASE, | ||
890 | .end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1, | ||
891 | .flags = IORESOURCE_MEM, | ||
892 | }, | ||
893 | { | ||
894 | .start = AT91_MAGIC_DM_I_BASE, | ||
895 | .end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1, | ||
896 | .flags = IORESOURCE_MEM, | ||
897 | }, | ||
898 | { | ||
899 | .start = AT91_MAGIC_DM_F_BASE, | ||
900 | .end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1, | ||
901 | .flags = IORESOURCE_MEM, | ||
902 | }, | ||
903 | { | ||
904 | .start = AT91_MAGIC_DM_DB_BASE, | ||
905 | .end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1, | ||
906 | .flags = IORESOURCE_MEM, | ||
907 | }, | ||
908 | { | ||
909 | .start = AT91_MAGIC_REGS_BASE, | ||
910 | .end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1, | ||
911 | .flags = IORESOURCE_MEM, | ||
912 | }, | ||
913 | { | ||
914 | .start = AT91_MAGIC_EXTPAGE_BASE, | ||
915 | .end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1, | ||
916 | .flags = IORESOURCE_MEM, | ||
917 | }, | ||
918 | { | ||
919 | .start = AT572D940HF_ID_MSIRQ0, | ||
920 | .end = AT572D940HF_ID_MSIRQ0, | ||
921 | .flags = IORESOURCE_IRQ, | ||
922 | }, | ||
923 | { | ||
924 | .start = AT572D940HF_ID_MHALT, | ||
925 | .end = AT572D940HF_ID_MHALT, | ||
926 | .flags = IORESOURCE_IRQ, | ||
927 | }, | ||
928 | { | ||
929 | .start = AT572D940HF_ID_MEXC, | ||
930 | .end = AT572D940HF_ID_MEXC, | ||
931 | .flags = IORESOURCE_IRQ, | ||
932 | }, | ||
933 | { | ||
934 | .start = AT572D940HF_ID_MEDMA, | ||
935 | .end = AT572D940HF_ID_MEDMA, | ||
936 | .flags = IORESOURCE_IRQ, | ||
937 | }, | ||
938 | }; | ||
939 | |||
940 | static struct platform_device mAgic_device = { | ||
941 | .name = "mAgic", | ||
942 | .id = -1, | ||
943 | .num_resources = ARRAY_SIZE(mAgic_resources), | ||
944 | .resource = mAgic_resources, | ||
945 | }; | ||
946 | |||
947 | void __init at91_add_device_mAgic(void) | ||
948 | { | ||
949 | platform_device_register(&mAgic_device); | ||
950 | } | ||
951 | #else | ||
952 | void __init at91_add_device_mAgic(void) {} | ||
953 | #endif | ||
954 | |||
955 | |||
956 | /* -------------------------------------------------------------------- */ | ||
957 | |||
958 | /* | ||
959 | * These devices are always present and don't need any board-specific | ||
960 | * setup. | ||
961 | */ | ||
962 | static int __init at91_add_standard_devices(void) | ||
963 | { | ||
964 | at91_add_device_rtt(); | ||
965 | at91_add_device_watchdog(); | ||
966 | at91_add_device_tc(); | ||
967 | return 0; | ||
968 | } | ||
969 | |||
970 | arch_initcall(at91_add_standard_devices); | ||
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c new file mode 100644 index 000000000000..5daff277f53e --- /dev/null +++ b/arch/arm/mach-at91/board-at572d940hf_ek.c | |||
@@ -0,0 +1,328 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-at91/board-at572d940hf_ek.c | ||
3 | * | ||
4 | * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com> | ||
5 | * Copyright (C) 2005 SAN People | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | |||
22 | #include <linux/types.h> | ||
23 | #include <linux/init.h> | ||
24 | #include <linux/mm.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | #include <linux/spi/spi.h> | ||
28 | #include <linux/spi/ds1305.h> | ||
29 | #include <linux/irq.h> | ||
30 | #include <linux/mtd/physmap.h> | ||
31 | |||
32 | #include <mach/hardware.h> | ||
33 | #include <asm/setup.h> | ||
34 | #include <asm/mach-types.h> | ||
35 | #include <asm/irq.h> | ||
36 | |||
37 | #include <asm/mach/arch.h> | ||
38 | #include <asm/mach/map.h> | ||
39 | #include <asm/mach/irq.h> | ||
40 | |||
41 | #include <mach/board.h> | ||
42 | #include <mach/gpio.h> | ||
43 | #include <mach/at91sam9_smc.h> | ||
44 | |||
45 | #include "sam9_smc.h" | ||
46 | #include "generic.h" | ||
47 | |||
48 | |||
49 | static void __init eb_map_io(void) | ||
50 | { | ||
51 | /* Initialize processor: 12.500 MHz crystal */ | ||
52 | at572d940hf_initialize(12000000); | ||
53 | |||
54 | /* DBGU on ttyS0. (Rx & Tx only) */ | ||
55 | at91_register_uart(0, 0, 0); | ||
56 | |||
57 | /* USART0 on ttyS1. (Rx & Tx only) */ | ||
58 | at91_register_uart(AT572D940HF_ID_US0, 1, 0); | ||
59 | |||
60 | /* USART1 on ttyS2. (Rx & Tx only) */ | ||
61 | at91_register_uart(AT572D940HF_ID_US1, 2, 0); | ||
62 | |||
63 | /* USART2 on ttyS3. (Tx & Rx only */ | ||
64 | at91_register_uart(AT572D940HF_ID_US2, 3, 0); | ||
65 | |||
66 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
67 | at91_set_serial_console(0); | ||
68 | } | ||
69 | |||
70 | static void __init eb_init_irq(void) | ||
71 | { | ||
72 | at572d940hf_init_interrupts(NULL); | ||
73 | } | ||
74 | |||
75 | |||
76 | /* | ||
77 | * USB Host Port | ||
78 | */ | ||
79 | static struct at91_usbh_data __initdata eb_usbh_data = { | ||
80 | .ports = 2, | ||
81 | }; | ||
82 | |||
83 | |||
84 | /* | ||
85 | * USB Device Port | ||
86 | */ | ||
87 | static struct at91_udc_data __initdata eb_udc_data = { | ||
88 | .vbus_pin = 0, /* no VBUS detection,UDC always on */ | ||
89 | .pullup_pin = 0, /* pull-up driven by UDC */ | ||
90 | }; | ||
91 | |||
92 | |||
93 | /* | ||
94 | * MCI (SD/MMC) | ||
95 | */ | ||
96 | static struct at91_mmc_data __initdata eb_mmc_data = { | ||
97 | .wire4 = 1, | ||
98 | /* .det_pin = ... not connected */ | ||
99 | /* .wp_pin = ... not connected */ | ||
100 | /* .vcc_pin = ... not connected */ | ||
101 | }; | ||
102 | |||
103 | |||
104 | /* | ||
105 | * MACB Ethernet device | ||
106 | */ | ||
107 | static struct at91_eth_data __initdata eb_eth_data = { | ||
108 | .phy_irq_pin = AT91_PIN_PB25, | ||
109 | .is_rmii = 1, | ||
110 | }; | ||
111 | |||
112 | /* | ||
113 | * NOR flash | ||
114 | */ | ||
115 | |||
116 | static struct mtd_partition eb_nor_partitions[] = { | ||
117 | { | ||
118 | .name = "Raw Environment", | ||
119 | .offset = 0, | ||
120 | .size = SZ_4M, | ||
121 | .mask_flags = 0, | ||
122 | }, | ||
123 | { | ||
124 | .name = "OS FS", | ||
125 | .offset = MTDPART_OFS_APPEND, | ||
126 | .size = 3 * SZ_1M, | ||
127 | .mask_flags = 0, | ||
128 | }, | ||
129 | { | ||
130 | .name = "APP FS", | ||
131 | .offset = MTDPART_OFS_APPEND, | ||
132 | .size = MTDPART_SIZ_FULL, | ||
133 | .mask_flags = 0, | ||
134 | }, | ||
135 | }; | ||
136 | |||
137 | static void nor_flash_set_vpp(struct map_info* mi, int i) { | ||
138 | }; | ||
139 | |||
140 | static struct physmap_flash_data nor_flash_data = { | ||
141 | .width = 4, | ||
142 | .parts = eb_nor_partitions, | ||
143 | .nr_parts = ARRAY_SIZE(eb_nor_partitions), | ||
144 | .set_vpp = nor_flash_set_vpp, | ||
145 | }; | ||
146 | |||
147 | static struct resource nor_flash_resources[] = { | ||
148 | { | ||
149 | .start = AT91_CHIPSELECT_0, | ||
150 | .end = AT91_CHIPSELECT_0 + SZ_16M - 1, | ||
151 | .flags = IORESOURCE_MEM, | ||
152 | }, | ||
153 | }; | ||
154 | |||
155 | static struct platform_device nor_flash = { | ||
156 | .name = "physmap-flash", | ||
157 | .id = 0, | ||
158 | .dev = { | ||
159 | .platform_data = &nor_flash_data, | ||
160 | }, | ||
161 | .resource = nor_flash_resources, | ||
162 | .num_resources = ARRAY_SIZE(nor_flash_resources), | ||
163 | }; | ||
164 | |||
165 | static struct sam9_smc_config __initdata eb_nor_smc_config = { | ||
166 | .ncs_read_setup = 1, | ||
167 | .nrd_setup = 1, | ||
168 | .ncs_write_setup = 1, | ||
169 | .nwe_setup = 1, | ||
170 | |||
171 | .ncs_read_pulse = 7, | ||
172 | .nrd_pulse = 7, | ||
173 | .ncs_write_pulse = 7, | ||
174 | .nwe_pulse = 7, | ||
175 | |||
176 | .read_cycle = 9, | ||
177 | .write_cycle = 9, | ||
178 | |||
179 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32, | ||
180 | .tdf_cycles = 1, | ||
181 | }; | ||
182 | |||
183 | static void __init eb_add_device_nor(void) | ||
184 | { | ||
185 | /* configure chip-select 0 (NOR) */ | ||
186 | sam9_smc_configure(0, &eb_nor_smc_config); | ||
187 | platform_device_register(&nor_flash); | ||
188 | } | ||
189 | |||
190 | /* | ||
191 | * NAND flash | ||
192 | */ | ||
193 | static struct mtd_partition __initdata eb_nand_partition[] = { | ||
194 | { | ||
195 | .name = "Partition 1", | ||
196 | .offset = 0, | ||
197 | .size = SZ_16M, | ||
198 | }, | ||
199 | { | ||
200 | .name = "Partition 2", | ||
201 | .offset = MTDPART_OFS_NXTBLK, | ||
202 | .size = MTDPART_SIZ_FULL, | ||
203 | } | ||
204 | }; | ||
205 | |||
206 | static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) | ||
207 | { | ||
208 | *num_partitions = ARRAY_SIZE(eb_nand_partition); | ||
209 | return eb_nand_partition; | ||
210 | } | ||
211 | |||
212 | static struct atmel_nand_data __initdata eb_nand_data = { | ||
213 | .ale = 22, | ||
214 | .cle = 21, | ||
215 | /* .det_pin = ... not connected */ | ||
216 | /* .rdy_pin = AT91_PIN_PC16, */ | ||
217 | .enable_pin = AT91_PIN_PA15, | ||
218 | .partition_info = nand_partitions, | ||
219 | #if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) | ||
220 | .bus_width_16 = 1, | ||
221 | #else | ||
222 | .bus_width_16 = 0, | ||
223 | #endif | ||
224 | }; | ||
225 | |||
226 | static struct sam9_smc_config __initdata eb_nand_smc_config = { | ||
227 | .ncs_read_setup = 0, | ||
228 | .nrd_setup = 0, | ||
229 | .ncs_write_setup = 1, | ||
230 | .nwe_setup = 1, | ||
231 | |||
232 | .ncs_read_pulse = 3, | ||
233 | .nrd_pulse = 3, | ||
234 | .ncs_write_pulse = 3, | ||
235 | .nwe_pulse = 3, | ||
236 | |||
237 | .read_cycle = 5, | ||
238 | .write_cycle = 5, | ||
239 | |||
240 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, | ||
241 | .tdf_cycles = 12, | ||
242 | }; | ||
243 | |||
244 | static void __init eb_add_device_nand(void) | ||
245 | { | ||
246 | /* setup bus-width (8 or 16) */ | ||
247 | if (eb_nand_data.bus_width_16) | ||
248 | eb_nand_smc_config.mode |= AT91_SMC_DBW_16; | ||
249 | else | ||
250 | eb_nand_smc_config.mode |= AT91_SMC_DBW_8; | ||
251 | |||
252 | /* configure chip-select 3 (NAND) */ | ||
253 | sam9_smc_configure(3, &eb_nand_smc_config); | ||
254 | |||
255 | at91_add_device_nand(&eb_nand_data); | ||
256 | } | ||
257 | |||
258 | |||
259 | /* | ||
260 | * SPI devices | ||
261 | */ | ||
262 | static struct resource rtc_resources[] = { | ||
263 | [0] = { | ||
264 | .start = AT572D940HF_ID_IRQ1, | ||
265 | .end = AT572D940HF_ID_IRQ1, | ||
266 | .flags = IORESOURCE_IRQ, | ||
267 | }, | ||
268 | }; | ||
269 | |||
270 | static struct ds1305_platform_data ds1306_data = { | ||
271 | .is_ds1306 = true, | ||
272 | .en_1hz = false, | ||
273 | }; | ||
274 | |||
275 | static struct spi_board_info eb_spi_devices[] = { | ||
276 | { /* RTC Dallas DS1306 */ | ||
277 | .modalias = "rtc-ds1305", | ||
278 | .chip_select = 3, | ||
279 | .mode = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA, | ||
280 | .max_speed_hz = 500000, | ||
281 | .bus_num = 0, | ||
282 | .irq = AT572D940HF_ID_IRQ1, | ||
283 | .platform_data = (void *) &ds1306_data, | ||
284 | }, | ||
285 | #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) | ||
286 | { /* Dataflash card */ | ||
287 | .modalias = "mtd_dataflash", | ||
288 | .chip_select = 0, | ||
289 | .max_speed_hz = 15 * 1000 * 1000, | ||
290 | .bus_num = 0, | ||
291 | }, | ||
292 | #endif | ||
293 | }; | ||
294 | |||
295 | static void __init eb_board_init(void) | ||
296 | { | ||
297 | /* Serial */ | ||
298 | at91_add_device_serial(); | ||
299 | /* USB Host */ | ||
300 | at91_add_device_usbh(&eb_usbh_data); | ||
301 | /* USB Device */ | ||
302 | at91_add_device_udc(&eb_udc_data); | ||
303 | /* I2C */ | ||
304 | at91_add_device_i2c(NULL, 0); | ||
305 | /* NOR */ | ||
306 | eb_add_device_nor(); | ||
307 | /* NAND */ | ||
308 | eb_add_device_nand(); | ||
309 | /* SPI */ | ||
310 | at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices)); | ||
311 | /* MMC */ | ||
312 | at91_add_device_mmc(0, &eb_mmc_data); | ||
313 | /* Ethernet */ | ||
314 | at91_add_device_eth(&eb_eth_data); | ||
315 | /* mAgic */ | ||
316 | at91_add_device_mAgic(); | ||
317 | } | ||
318 | |||
319 | MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB") | ||
320 | /* Maintainer: Atmel <costa.antonior@gmail.com> */ | ||
321 | .phys_io = AT91_BASE_SYS, | ||
322 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
323 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
324 | .timer = &at91sam926x_timer, | ||
325 | .map_io = eb_map_io, | ||
326 | .init_irq = eb_init_irq, | ||
327 | .init_machine = eb_board_init, | ||
328 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index c042dcf4725f..7f7da439341f 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
30 | 30 | ||
31 | #include "clock.h" | 31 | #include "clock.h" |
32 | #include "generic.h" | ||
32 | 33 | ||
33 | 34 | ||
34 | /* | 35 | /* |
@@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) | |||
628 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); | 629 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
629 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || | 630 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
630 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || | 631 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || |
631 | cpu_is_at91sam9g10()) { | 632 | cpu_is_at91sam9g10() || cpu_is_at572d940hf()) { |
632 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; | 633 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
633 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; | 634 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
634 | } else if (cpu_is_at91cap9()) { | 635 | } else if (cpu_is_at91cap9()) { |
@@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock) | |||
711 | /* | 712 | /* |
712 | * USB HS clock init | 713 | * USB HS clock init |
713 | */ | 714 | */ |
714 | if (cpu_has_utmi()) | 715 | if (cpu_has_utmi()) { |
715 | /* | 716 | /* |
716 | * multiplier is hard-wired to 40 | 717 | * multiplier is hard-wired to 40 |
717 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) | 718 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) |
718 | */ | 719 | */ |
719 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; | 720 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; |
721 | } | ||
720 | 722 | ||
721 | /* | 723 | /* |
722 | * USB FS clock init | 724 | * USB FS clock init |
@@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock) | |||
746 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? | 748 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? |
747 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ | 749 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
748 | } else { | 750 | } else { |
749 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ | 751 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
750 | } | 752 | } |
751 | 753 | ||
752 | /* Register the PMC's standard clocks */ | 754 | /* Register the PMC's standard clocks */ |
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index 1ba3b95ff359..6cf4b78e175d 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h | |||
@@ -22,7 +22,7 @@ struct clk { | |||
22 | struct clk *parent; | 22 | struct clk *parent; |
23 | u32 pmc_mask; | 23 | u32 pmc_mask; |
24 | void (*mode)(struct clk *, int); | 24 | void (*mode)(struct clk *, int); |
25 | unsigned id:2; /* PCK0..3, or 32k/main/a/b */ | 25 | unsigned id:3; /* PCK0..4, or 32k/main/a/b */ |
26 | unsigned type; /* clock type */ | 26 | unsigned type; /* clock type */ |
27 | u16 users; | 27 | u16 users; |
28 | }; | 28 | }; |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 88e413b38480..65c3dc5ba0d0 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
@@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock); | |||
17 | extern void __init at91sam9g45_initialize(unsigned long main_clock); | 17 | extern void __init at91sam9g45_initialize(unsigned long main_clock); |
18 | extern void __init at91x40_initialize(unsigned long main_clock); | 18 | extern void __init at91x40_initialize(unsigned long main_clock); |
19 | extern void __init at91cap9_initialize(unsigned long main_clock); | 19 | extern void __init at91cap9_initialize(unsigned long main_clock); |
20 | extern void __init at572d940hf_initialize(unsigned long main_clock); | ||
20 | 21 | ||
21 | /* Interrupts */ | 22 | /* Interrupts */ |
22 | extern void __init at91rm9200_init_interrupts(unsigned int priority[]); | 23 | extern void __init at91rm9200_init_interrupts(unsigned int priority[]); |
@@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); | |||
27 | extern void __init at91sam9g45_init_interrupts(unsigned int priority[]); | 28 | extern void __init at91sam9g45_init_interrupts(unsigned int priority[]); |
28 | extern void __init at91x40_init_interrupts(unsigned int priority[]); | 29 | extern void __init at91x40_init_interrupts(unsigned int priority[]); |
29 | extern void __init at91cap9_init_interrupts(unsigned int priority[]); | 30 | extern void __init at91cap9_init_interrupts(unsigned int priority[]); |
31 | extern void __init at572d940hf_init_interrupts(unsigned int priority[]); | ||
30 | extern void __init at91_aic_init(unsigned int priority[]); | 32 | extern void __init at91_aic_init(unsigned int priority[]); |
31 | 33 | ||
32 | /* Timer */ | 34 | /* Timer */ |
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h new file mode 100644 index 000000000000..2d9b0af9c4d5 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at572d940hf.h | |||
@@ -0,0 +1,123 @@ | |||
1 | /* | ||
2 | * include/mach/at572d940hf.h | ||
3 | * | ||
4 | * Antonio R. Costa <costa.antonior@gmail.com> | ||
5 | * Copyright (C) 2008 Atmel | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #ifndef AT572D940HF_H | ||
24 | #define AT572D940HF_H | ||
25 | |||
26 | /* | ||
27 | * Peripheral identifiers/interrupts. | ||
28 | */ | ||
29 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
30 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
31 | #define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */ | ||
32 | #define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */ | ||
33 | #define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */ | ||
34 | #define AT572D940HF_ID_EMAC 5 /* MACB ethernet controller */ | ||
35 | #define AT572D940HF_ID_US0 6 /* USART 0 */ | ||
36 | #define AT572D940HF_ID_US1 7 /* USART 1 */ | ||
37 | #define AT572D940HF_ID_US2 8 /* USART 2 */ | ||
38 | #define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */ | ||
39 | #define AT572D940HF_ID_UDP 10 /* USB Device Port */ | ||
40 | #define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface 0 */ | ||
41 | #define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
42 | #define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
43 | #define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
44 | #define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
45 | #define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
46 | #define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */ | ||
47 | #define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */ | ||
48 | #define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */ | ||
49 | #define AT572D940HF_ID_UHP 20 /* USB Host port */ | ||
50 | #define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller 3 */ | ||
51 | #define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface 1 */ | ||
52 | #define AT572D940HF_ID_CAN0 23 /* CAN Controller 0 */ | ||
53 | #define AT572D940HF_ID_CAN1 24 /* CAN Controller 1 */ | ||
54 | #define AT572D940HF_ID_MHALT 25 /* mAgicV HALT line */ | ||
55 | #define AT572D940HF_ID_MSIRQ0 26 /* mAgicV SIRQ0 line */ | ||
56 | #define AT572D940HF_ID_MEXC 27 /* mAgicV exception line */ | ||
57 | #define AT572D940HF_ID_MEDMA 28 /* mAgicV end of DMA line */ | ||
58 | #define AT572D940HF_ID_IRQ0 29 /* External Interrupt Source (IRQ0) */ | ||
59 | #define AT572D940HF_ID_IRQ1 30 /* External Interrupt Source (IRQ1) */ | ||
60 | #define AT572D940HF_ID_IRQ2 31 /* External Interrupt Source (IRQ2) */ | ||
61 | |||
62 | |||
63 | /* | ||
64 | * User Peripheral physical base addresses. | ||
65 | */ | ||
66 | #define AT572D940HF_BASE_TCB 0xfffa0000 | ||
67 | #define AT572D940HF_BASE_TC0 0xfffa0000 | ||
68 | #define AT572D940HF_BASE_TC1 0xfffa0040 | ||
69 | #define AT572D940HF_BASE_TC2 0xfffa0080 | ||
70 | #define AT572D940HF_BASE_UDP 0xfffa4000 | ||
71 | #define AT572D940HF_BASE_MCI 0xfffa8000 | ||
72 | #define AT572D940HF_BASE_TWI0 0xfffac000 | ||
73 | #define AT572D940HF_BASE_US0 0xfffb0000 | ||
74 | #define AT572D940HF_BASE_US1 0xfffb4000 | ||
75 | #define AT572D940HF_BASE_US2 0xfffb8000 | ||
76 | #define AT572D940HF_BASE_SSC0 0xfffbc000 | ||
77 | #define AT572D940HF_BASE_SSC1 0xfffc0000 | ||
78 | #define AT572D940HF_BASE_SSC2 0xfffc4000 | ||
79 | #define AT572D940HF_BASE_SPI0 0xfffc8000 | ||
80 | #define AT572D940HF_BASE_SPI1 0xfffcc000 | ||
81 | #define AT572D940HF_BASE_SSC3 0xfffd0000 | ||
82 | #define AT572D940HF_BASE_TWI1 0xfffd4000 | ||
83 | #define AT572D940HF_BASE_EMAC 0xfffd8000 | ||
84 | #define AT572D940HF_BASE_CAN0 0xfffdc000 | ||
85 | #define AT572D940HF_BASE_CAN1 0xfffe0000 | ||
86 | #define AT91_BASE_SYS 0xffffea00 | ||
87 | |||
88 | |||
89 | /* | ||
90 | * System Peripherals (offset from AT91_BASE_SYS) | ||
91 | */ | ||
92 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
93 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
94 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
95 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
96 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
97 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
98 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
99 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
100 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
101 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
102 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
103 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
104 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
105 | |||
106 | #define AT91_USART0 AT572D940HF_ID_US0 | ||
107 | #define AT91_USART1 AT572D940HF_ID_US1 | ||
108 | #define AT91_USART2 AT572D940HF_ID_US2 | ||
109 | |||
110 | |||
111 | /* | ||
112 | * Internal Memory. | ||
113 | */ | ||
114 | #define AT572D940HF_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
115 | #define AT572D940HF_SRAM_SIZE (48 * SZ_1K) /* Internal SRAM size (48Kb) */ | ||
116 | |||
117 | #define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
118 | #define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
119 | |||
120 | #define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */ | ||
121 | |||
122 | |||
123 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h new file mode 100644 index 000000000000..b6751df09488 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h | |||
@@ -0,0 +1,123 @@ | |||
1 | /* | ||
2 | * include/mach//at572d940hf_matrix.h | ||
3 | * | ||
4 | * Antonio R. Costa <costa.antonior@gmail.com> | ||
5 | * Copyright (C) 2008 Atmel | ||
6 | * | ||
7 | * Copyright (C) 2005 SAN People | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | |||
24 | #ifndef AT572D940HF_MATRIX_H | ||
25 | #define AT572D940HF_MATRIX_H | ||
26 | |||
27 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
28 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
29 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
30 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
31 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
32 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
33 | |||
34 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
35 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
36 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
37 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
38 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
39 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
40 | |||
41 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
42 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
43 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
44 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
45 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
46 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
47 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
48 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
49 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
50 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
51 | #define AT91_MATRIX_FIXED_DEFMSTR (0x7 << 18) /* Fixed Index of Default Master */ | ||
52 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
53 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
54 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
55 | |||
56 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
57 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
58 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
59 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
60 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
61 | |||
62 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
63 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
64 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
65 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
66 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
67 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
68 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
69 | |||
70 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
71 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
72 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
73 | |||
74 | #define AT91_MATRIX_SFR0 (AT91_MATRIX + 0x110) /* Special Function Register 0 */ | ||
75 | #define AT91_MATRIX_SFR1 (AT91_MATRIX + 0x114) /* Special Function Register 1 */ | ||
76 | #define AT91_MATRIX_SFR2 (AT91_MATRIX + 0x118) /* Special Function Register 2 */ | ||
77 | #define AT91_MATRIX_SFR3 (AT91_MATRIX + 0x11C) /* Special Function Register 3 */ | ||
78 | #define AT91_MATRIX_SFR4 (AT91_MATRIX + 0x120) /* Special Function Register 4 */ | ||
79 | #define AT91_MATRIX_SFR5 (AT91_MATRIX + 0x124) /* Special Function Register 5 */ | ||
80 | #define AT91_MATRIX_SFR6 (AT91_MATRIX + 0x128) /* Special Function Register 6 */ | ||
81 | #define AT91_MATRIX_SFR7 (AT91_MATRIX + 0x12C) /* Special Function Register 7 */ | ||
82 | #define AT91_MATRIX_SFR8 (AT91_MATRIX + 0x130) /* Special Function Register 8 */ | ||
83 | #define AT91_MATRIX_SFR9 (AT91_MATRIX + 0x134) /* Special Function Register 9 */ | ||
84 | #define AT91_MATRIX_SFR10 (AT91_MATRIX + 0x138) /* Special Function Register 10 */ | ||
85 | #define AT91_MATRIX_SFR11 (AT91_MATRIX + 0x13C) /* Special Function Register 11 */ | ||
86 | #define AT91_MATRIX_SFR12 (AT91_MATRIX + 0x140) /* Special Function Register 12 */ | ||
87 | #define AT91_MATRIX_SFR13 (AT91_MATRIX + 0x144) /* Special Function Register 13 */ | ||
88 | #define AT91_MATRIX_SFR14 (AT91_MATRIX + 0x148) /* Special Function Register 14 */ | ||
89 | #define AT91_MATRIX_SFR15 (AT91_MATRIX + 0x14C) /* Special Function Register 15 */ | ||
90 | |||
91 | |||
92 | /* | ||
93 | * The following registers / bits are not defined in the Datasheet (Revision A) | ||
94 | */ | ||
95 | |||
96 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x100) /* TCM Configuration Register */ | ||
97 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
98 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
99 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
100 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
101 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
102 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
103 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
104 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
105 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
106 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
107 | |||
108 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
109 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
110 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
111 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
112 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
113 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
114 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
115 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
116 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
117 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
118 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
119 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
120 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
121 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
122 | |||
123 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 64589eaaaee8..e46f93e34aab 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
@@ -32,6 +32,7 @@ | |||
32 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | 32 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ |
33 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | 33 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ |
34 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | 34 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ |
35 | #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ | ||
35 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | 36 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
36 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | 37 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ |
37 | 38 | ||
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index bb6f6a7ba5e0..ceaec6c16eb2 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h | |||
@@ -87,7 +87,7 @@ struct at91_eth_data { | |||
87 | extern void __init at91_add_device_eth(struct at91_eth_data *data); | 87 | extern void __init at91_add_device_eth(struct at91_eth_data *data); |
88 | 88 | ||
89 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ | 89 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ |
90 | || defined(CONFIG_ARCH_AT91SAM9G45) | 90 | || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF) |
91 | #define eth_platform_data at91_eth_data | 91 | #define eth_platform_data at91_eth_data |
92 | #endif | 92 | #endif |
93 | 93 | ||
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); | |||
205 | extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); | 205 | extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); |
206 | extern void __init at91_pwm_leds(struct gpio_led *leds, int nr); | 206 | extern void __init at91_pwm_leds(struct gpio_led *leds, int nr); |
207 | 207 | ||
208 | /* AT572D940HF DSP */ | ||
209 | extern void __init at91_add_device_mAgic(void); | ||
210 | |||
208 | /* FIXME: this needs a better location, but gets stuff building again */ | 211 | /* FIXME: this needs a better location, but gets stuff building again */ |
209 | extern int at91_suspend_entering_slow_clock(void); | 212 | extern int at91_suspend_entering_slow_clock(void); |
210 | 213 | ||
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index c22df30ed5e5..5a0650101d45 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
@@ -33,6 +33,8 @@ | |||
33 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | 33 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 |
34 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 | 34 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 |
35 | 35 | ||
36 | #define ARCH_ID_AT572D940HF 0x0e0303e0 | ||
37 | |||
36 | #define ARCH_ID_AT91M40800 0x14080044 | 38 | #define ARCH_ID_AT91M40800 0x14080044 |
37 | #define ARCH_ID_AT91R40807 0x44080746 | 39 | #define ARCH_ID_AT91R40807 0x44080746 |
38 | #define ARCH_ID_AT91M40807 0x14080745 | 40 | #define ARCH_ID_AT91M40807 0x14080745 |
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void) | |||
141 | #define cpu_is_at91cap9_revC() (0) | 143 | #define cpu_is_at91cap9_revC() (0) |
142 | #endif | 144 | #endif |
143 | 145 | ||
146 | #ifdef CONFIG_ARCH_AT572D940HF | ||
147 | #define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF) | ||
148 | #else | ||
149 | #define cpu_is_at572d940hf() (0) | ||
150 | #endif | ||
151 | |||
144 | /* | 152 | /* |
145 | * Since this is ARM, we will never run on any AVR32 CPU. But these | 153 | * Since this is ARM, we will never run on any AVR32 CPU. But these |
146 | * definitions may reduce clutter in common drivers. | 154 | * definitions may reduce clutter in common drivers. |
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S index 29052ba66ada..9e750a1c1b5a 100644 --- a/arch/arm/mach-at91/include/mach/debug-macro.S +++ b/arch/arm/mach-at91/include/mach/debug-macro.S | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
15 | #include <mach/at91_dbgu.h> | 15 | #include <mach/at91_dbgu.h> |
16 | 16 | ||
17 | .macro addruart,rx | 17 | .macro addruart, rx, tmp |
18 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
19 | tst \rx, #1 @ MMU enabled? | 19 | tst \rx, #1 @ MMU enabled? |
20 | ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) | 20 | ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) |
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index a0df8b022df2..3d64a75e3ed5 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h | |||
@@ -32,6 +32,8 @@ | |||
32 | #include <mach/at91cap9.h> | 32 | #include <mach/at91cap9.h> |
33 | #elif defined(CONFIG_ARCH_AT91X40) | 33 | #elif defined(CONFIG_ARCH_AT91X40) |
34 | #include <mach/at91x40.h> | 34 | #include <mach/at91x40.h> |
35 | #elif defined(CONFIG_ARCH_AT572D940HF) | ||
36 | #include <mach/at572d940hf.h> | ||
35 | #else | 37 | #else |
36 | #error "Unsupported AT91 processor" | 38 | #error "Unsupported AT91 processor" |
37 | #endif | 39 | #endif |
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h index 31ac2d97f14c..05a6e8af80c4 100644 --- a/arch/arm/mach-at91/include/mach/timex.h +++ b/arch/arm/mach-at91/include/mach/timex.h | |||
@@ -82,6 +82,11 @@ | |||
82 | #define AT91X40_MASTER_CLOCK 40000000 | 82 | #define AT91X40_MASTER_CLOCK 40000000 |
83 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) | 83 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) |
84 | 84 | ||
85 | #elif defined(CONFIG_ARCH_AT572D940HF) | ||
86 | |||
87 | #define AT572D940HF_MASTER_CLOCK 80000000 | ||
88 | #define CLOCK_TICK_RATE (AT572D940HF_MASTER_CLOCK/16) | ||
89 | |||
85 | #endif | 90 | #endif |
86 | 91 | ||
87 | #endif | 92 | #endif |
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S index 64baf9f87408..fedd8076a689 100644 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S | |||
@@ -13,7 +13,7 @@ | |||
13 | 13 | ||
14 | #include <asm/hardware/clps7111.h> | 14 | #include <asm/hardware/clps7111.h> |
15 | 15 | ||
16 | .macro addruart,rx | 16 | .macro addruart, rx, tmp |
17 | mrc p15, 0, \rx, c1, c0 | 17 | mrc p15, 0, \rx, c1, c0 |
18 | tst \rx, #1 @ MMU enabled? | 18 | tst \rx, #1 @ MMU enabled? |
19 | moveq \rx, #CLPS7111_PHYS_BASE | 19 | moveq \rx, #CLPS7111_PHYS_BASE |
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 17ab5236da66..3cd93a801d9b 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S | |||
@@ -19,7 +19,7 @@ | |||
19 | #include <linux/serial_reg.h> | 19 | #include <linux/serial_reg.h> |
20 | #define UART_SHIFT 2 | 20 | #define UART_SHIFT 2 |
21 | 21 | ||
22 | .macro addruart, rx | 22 | .macro addruart, rx, tmp |
23 | mrc p15, 0, \rx, c1, c0 | 23 | mrc p15, 0, \rx, c1, c0 |
24 | tst \rx, #1 @ MMU enabled? | 24 | tst \rx, #1 @ MMU enabled? |
25 | moveq \rx, #0x01000000 @ physical base address | 25 | moveq \rx, #0x01000000 @ physical base address |
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index 41c89386e39b..c45ba1f62a11 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h | |||
@@ -27,7 +27,7 @@ | |||
27 | /* | 27 | /* |
28 | * I/O mapping | 28 | * I/O mapping |
29 | */ | 29 | */ |
30 | #define IO_PHYS 0x01c00000 | 30 | #define IO_PHYS 0x01c00000UL |
31 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ | 31 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ |
32 | #define IO_SIZE 0x00400000 | 32 | #define IO_SIZE 0x00400000 |
33 | #define IO_VIRT (IO_PHYS + IO_OFFSET) | 33 | #define IO_VIRT (IO_PHYS + IO_OFFSET) |
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index 49912b48b1b0..a1c0b6b99edf 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c | |||
@@ -24,7 +24,7 @@ void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type) | |||
24 | if (BETWEEN(p, IO_PHYS, IO_SIZE)) | 24 | if (BETWEEN(p, IO_PHYS, IO_SIZE)) |
25 | return XLATE(p, IO_PHYS, IO_VIRT); | 25 | return XLATE(p, IO_PHYS, IO_VIRT); |
26 | 26 | ||
27 | return __arm_ioremap(p, size, type); | 27 | return __arm_ioremap_caller(p, size, type, __builtin_return_address(0)); |
28 | } | 28 | } |
29 | EXPORT_SYMBOL(davinci_ioremap); | 29 | EXPORT_SYMBOL(davinci_ioremap); |
30 | 30 | ||
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S index 9b89ec7d3040..1521d13f1d14 100644 --- a/arch/arm/mach-dove/include/mach/debug-macro.S +++ b/arch/arm/mach-dove/include/mach/debug-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | 8 | ||
9 | #include <mach/bridge-regs.h> | 9 | #include <mach/bridge-regs.h> |
10 | 10 | ||
11 | .macro addruart,rx | 11 | .macro addruart, rx, tmp |
12 | mrc p15, 0, \rx, c1, c0 | 12 | mrc p15, 0, \rx, c1, c0 |
13 | tst \rx, #1 @ MMU enabled? | 13 | tst \rx, #1 @ MMU enabled? |
14 | ldreq \rx, =DOVE_SB_REGS_PHYS_BASE | 14 | ldreq \rx, =DOVE_SB_REGS_PHYS_BASE |
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h index 8b2c974755c6..a28792cf761e 100644 --- a/arch/arm/mach-dove/include/mach/vmalloc.h +++ b/arch/arm/mach-dove/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-dove/include/mach/vmalloc.h | 2 | * arch/arm/mach-dove/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfd800000 | 5 | #define VMALLOC_END 0xfd800000UL |
diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S index 1dde8227f3a2..ebbd89f0e6c0 100644 --- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S +++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | **/ | 12 | **/ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mov \rx, #0xf0000000 | 15 | mov \rx, #0xf0000000 |
16 | orr \rx, \rx, #0x00000be0 | 16 | orr \rx, \rx, #0x00000be0 |
17 | .endm | 17 | .endm |
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 9167c3d2a5ed..3a08b18f6433 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig | |||
@@ -161,6 +161,20 @@ config MACH_MICRO9S | |||
161 | Say 'Y' here if you want your kernel to support the | 161 | Say 'Y' here if you want your kernel to support the |
162 | Contec Micro9-Slim board. | 162 | Contec Micro9-Slim board. |
163 | 163 | ||
164 | config MACH_SIM_ONE | ||
165 | bool "Support Simplemachines Sim.One board" | ||
166 | depends on EP93XX_SDCE0_PHYS_OFFSET | ||
167 | help | ||
168 | Say 'Y' here if you want your kernel to support the | ||
169 | Simplemachines Sim.One board. | ||
170 | |||
171 | config MACH_SNAPPER_CL15 | ||
172 | bool "Support Bluewater Systems Snapper CL15 Module" | ||
173 | depends on EP93XX_SDCE0_PHYS_OFFSET | ||
174 | help | ||
175 | Say 'Y' here if you want your kernel to support the Bluewater | ||
176 | Systems Snapper CL15 Module. | ||
177 | |||
164 | config MACH_TS72XX | 178 | config MACH_TS72XX |
165 | bool "Support Technologic Systems TS-72xx SBC" | 179 | bool "Support Technologic Systems TS-72xx SBC" |
166 | depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET | 180 | depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET |
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index eae6199a9891..33ee2c863d18 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile | |||
@@ -10,4 +10,6 @@ obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o | |||
10 | obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o | 10 | obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o |
11 | obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o | 11 | obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o |
12 | obj-$(CONFIG_MACH_MICRO9) += micro9.o | 12 | obj-$(CONFIG_MACH_MICRO9) += micro9.o |
13 | obj-$(CONFIG_MACH_SIM_ONE) += simone.o | ||
14 | obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o | ||
13 | obj-$(CONFIG_MACH_TS72XX) += ts72xx.o | 15 | obj-$(CONFIG_MACH_TS72XX) += ts72xx.o |
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index bb3c62196442..5f80092b6ace 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
@@ -10,6 +10,8 @@ | |||
10 | * your option) any later version. | 10 | * your option) any later version. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt | ||
14 | |||
13 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
14 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
15 | #include <linux/err.h> | 17 | #include <linux/err.h> |
@@ -446,30 +448,34 @@ static int __init ep93xx_clock_init(void) | |||
446 | { | 448 | { |
447 | u32 value; | 449 | u32 value; |
448 | 450 | ||
449 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1); | 451 | /* Determine the bootloader configured pll1 rate */ |
450 | if (!(value & 0x00800000)) { /* PLL1 bypassed? */ | 452 | value = __raw_readl(EP93XX_SYSCON_CLKSET1); |
453 | if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) | ||
451 | clk_pll1.rate = clk_xtali.rate; | 454 | clk_pll1.rate = clk_xtali.rate; |
452 | } else { | 455 | else |
453 | clk_pll1.rate = calc_pll_rate(value); | 456 | clk_pll1.rate = calc_pll_rate(value); |
454 | } | 457 | |
458 | /* Initialize the pll1 derived clocks */ | ||
455 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; | 459 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; |
456 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; | 460 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; |
457 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; | 461 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; |
458 | ep93xx_dma_clock_init(); | 462 | ep93xx_dma_clock_init(); |
459 | 463 | ||
460 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); | 464 | /* Determine the bootloader configured pll2 rate */ |
461 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ | 465 | value = __raw_readl(EP93XX_SYSCON_CLKSET2); |
466 | if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) | ||
462 | clk_pll2.rate = clk_xtali.rate; | 467 | clk_pll2.rate = clk_xtali.rate; |
463 | } else if (value & 0x00040000) { /* PLL2 enabled? */ | 468 | else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) |
464 | clk_pll2.rate = calc_pll_rate(value); | 469 | clk_pll2.rate = calc_pll_rate(value); |
465 | } else { | 470 | else |
466 | clk_pll2.rate = 0; | 471 | clk_pll2.rate = 0; |
467 | } | 472 | |
473 | /* Initialize the pll2 derived clocks */ | ||
468 | clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); | 474 | clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); |
469 | 475 | ||
470 | printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n", | 476 | pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", |
471 | clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); | 477 | clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); |
472 | printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", | 478 | pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", |
473 | clk_f.rate / 1000000, clk_h.rate / 1000000, | 479 | clk_f.rate / 1000000, clk_h.rate / 1000000, |
474 | clk_p.rate / 1000000); | 480 | clk_p.rate / 1000000); |
475 | 481 | ||
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 1f0d66561bbe..90fb591cbffa 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
@@ -14,12 +14,15 @@ | |||
14 | * your option) any later version. | 14 | * your option) any later version. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt | ||
18 | |||
17 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 20 | #include <linux/init.h> |
19 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
20 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
21 | #include <linux/dma-mapping.h> | 23 | #include <linux/dma-mapping.h> |
22 | #include <linux/timex.h> | 24 | #include <linux/timex.h> |
25 | #include <linux/irq.h> | ||
23 | #include <linux/io.h> | 26 | #include <linux/io.h> |
24 | #include <linux/gpio.h> | 27 | #include <linux/gpio.h> |
25 | #include <linux/leds.h> | 28 | #include <linux/leds.h> |
@@ -35,7 +38,6 @@ | |||
35 | 38 | ||
36 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
37 | #include <asm/mach/time.h> | 40 | #include <asm/mach/time.h> |
38 | #include <asm/mach/irq.h> | ||
39 | 41 | ||
40 | #include <asm/hardware/vic.h> | 42 | #include <asm/hardware/vic.h> |
41 | 43 | ||
@@ -82,13 +84,40 @@ void __init ep93xx_map_io(void) | |||
82 | * to use this timer for something else. We also use timer 4 for keeping | 84 | * to use this timer for something else. We also use timer 4 for keeping |
83 | * track of lost jiffies. | 85 | * track of lost jiffies. |
84 | */ | 86 | */ |
85 | static unsigned int last_jiffy_time; | 87 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) |
86 | 88 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) | |
89 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) | ||
90 | #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) | ||
91 | #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) | ||
92 | #define EP93XX_TIMER123_CONTROL_MODE (1 << 6) | ||
93 | #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) | ||
94 | #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) | ||
95 | #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) | ||
96 | #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) | ||
97 | #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) | ||
98 | #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) | ||
99 | #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) | ||
100 | #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) | ||
101 | #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) | ||
102 | #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) | ||
103 | #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) | ||
104 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) | ||
105 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) | ||
106 | |||
107 | #define EP93XX_TIMER123_CLOCK 508469 | ||
108 | #define EP93XX_TIMER4_CLOCK 983040 | ||
109 | |||
110 | #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) | ||
87 | #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) | 111 | #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) |
88 | 112 | ||
113 | static unsigned int last_jiffy_time; | ||
114 | |||
89 | static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) | 115 | static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) |
90 | { | 116 | { |
117 | /* Writing any value clears the timer interrupt */ | ||
91 | __raw_writel(1, EP93XX_TIMER1_CLEAR); | 118 | __raw_writel(1, EP93XX_TIMER1_CLEAR); |
119 | |||
120 | /* Recover lost jiffies */ | ||
92 | while ((signed long) | 121 | while ((signed long) |
93 | (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) | 122 | (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) |
94 | >= TIMER4_TICKS_PER_JIFFY) { | 123 | >= TIMER4_TICKS_PER_JIFFY) { |
@@ -107,13 +136,18 @@ static struct irqaction ep93xx_timer_irq = { | |||
107 | 136 | ||
108 | static void __init ep93xx_timer_init(void) | 137 | static void __init ep93xx_timer_init(void) |
109 | { | 138 | { |
139 | u32 tmode = EP93XX_TIMER123_CONTROL_MODE | | ||
140 | EP93XX_TIMER123_CONTROL_CLKSEL; | ||
141 | |||
110 | /* Enable periodic HZ timer. */ | 142 | /* Enable periodic HZ timer. */ |
111 | __raw_writel(0x48, EP93XX_TIMER1_CONTROL); | 143 | __raw_writel(tmode, EP93XX_TIMER1_CONTROL); |
112 | __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD); | 144 | __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); |
113 | __raw_writel(0xc8, EP93XX_TIMER1_CONTROL); | 145 | __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, |
146 | EP93XX_TIMER1_CONTROL); | ||
114 | 147 | ||
115 | /* Enable lost jiffy timer. */ | 148 | /* Enable lost jiffy timer. */ |
116 | __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH); | 149 | __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, |
150 | EP93XX_TIMER4_VALUE_HIGH); | ||
117 | 151 | ||
118 | setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); | 152 | setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); |
119 | } | 153 | } |
@@ -135,237 +169,16 @@ struct sys_timer ep93xx_timer = { | |||
135 | 169 | ||
136 | 170 | ||
137 | /************************************************************************* | 171 | /************************************************************************* |
138 | * GPIO handling for EP93xx | ||
139 | *************************************************************************/ | ||
140 | static unsigned char gpio_int_unmasked[3]; | ||
141 | static unsigned char gpio_int_enabled[3]; | ||
142 | static unsigned char gpio_int_type1[3]; | ||
143 | static unsigned char gpio_int_type2[3]; | ||
144 | static unsigned char gpio_int_debounce[3]; | ||
145 | |||
146 | /* Port ordering is: A B F */ | ||
147 | static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; | ||
148 | static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; | ||
149 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; | ||
150 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; | ||
151 | static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; | ||
152 | |||
153 | void ep93xx_gpio_update_int_params(unsigned port) | ||
154 | { | ||
155 | BUG_ON(port > 2); | ||
156 | |||
157 | __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port])); | ||
158 | |||
159 | __raw_writeb(gpio_int_type2[port], | ||
160 | EP93XX_GPIO_REG(int_type2_register_offset[port])); | ||
161 | |||
162 | __raw_writeb(gpio_int_type1[port], | ||
163 | EP93XX_GPIO_REG(int_type1_register_offset[port])); | ||
164 | |||
165 | __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], | ||
166 | EP93XX_GPIO_REG(int_en_register_offset[port])); | ||
167 | } | ||
168 | |||
169 | void ep93xx_gpio_int_mask(unsigned line) | ||
170 | { | ||
171 | gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); | ||
172 | } | ||
173 | |||
174 | void ep93xx_gpio_int_debounce(unsigned int irq, int enable) | ||
175 | { | ||
176 | int line = irq_to_gpio(irq); | ||
177 | int port = line >> 3; | ||
178 | int port_mask = 1 << (line & 7); | ||
179 | |||
180 | if (enable) | ||
181 | gpio_int_debounce[port] |= port_mask; | ||
182 | else | ||
183 | gpio_int_debounce[port] &= ~port_mask; | ||
184 | |||
185 | __raw_writeb(gpio_int_debounce[port], | ||
186 | EP93XX_GPIO_REG(int_debounce_register_offset[port])); | ||
187 | } | ||
188 | EXPORT_SYMBOL(ep93xx_gpio_int_debounce); | ||
189 | |||
190 | /************************************************************************* | ||
191 | * EP93xx IRQ handling | 172 | * EP93xx IRQ handling |
192 | *************************************************************************/ | 173 | *************************************************************************/ |
193 | static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) | 174 | extern void ep93xx_gpio_init_irq(void); |
194 | { | ||
195 | unsigned char status; | ||
196 | int i; | ||
197 | |||
198 | status = __raw_readb(EP93XX_GPIO_A_INT_STATUS); | ||
199 | for (i = 0; i < 8; i++) { | ||
200 | if (status & (1 << i)) { | ||
201 | int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; | ||
202 | generic_handle_irq(gpio_irq); | ||
203 | } | ||
204 | } | ||
205 | |||
206 | status = __raw_readb(EP93XX_GPIO_B_INT_STATUS); | ||
207 | for (i = 0; i < 8; i++) { | ||
208 | if (status & (1 << i)) { | ||
209 | int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; | ||
210 | generic_handle_irq(gpio_irq); | ||
211 | } | ||
212 | } | ||
213 | } | ||
214 | |||
215 | static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
216 | { | ||
217 | /* | ||
218 | * map discontiguous hw irq range to continous sw irq range: | ||
219 | * | ||
220 | * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) | ||
221 | */ | ||
222 | int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ | ||
223 | int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; | ||
224 | |||
225 | generic_handle_irq(gpio_irq); | ||
226 | } | ||
227 | |||
228 | static void ep93xx_gpio_irq_ack(unsigned int irq) | ||
229 | { | ||
230 | int line = irq_to_gpio(irq); | ||
231 | int port = line >> 3; | ||
232 | int port_mask = 1 << (line & 7); | ||
233 | |||
234 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | ||
235 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | ||
236 | ep93xx_gpio_update_int_params(port); | ||
237 | } | ||
238 | |||
239 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | ||
240 | } | ||
241 | |||
242 | static void ep93xx_gpio_irq_mask_ack(unsigned int irq) | ||
243 | { | ||
244 | int line = irq_to_gpio(irq); | ||
245 | int port = line >> 3; | ||
246 | int port_mask = 1 << (line & 7); | ||
247 | |||
248 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) | ||
249 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | ||
250 | |||
251 | gpio_int_unmasked[port] &= ~port_mask; | ||
252 | ep93xx_gpio_update_int_params(port); | ||
253 | |||
254 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | ||
255 | } | ||
256 | |||
257 | static void ep93xx_gpio_irq_mask(unsigned int irq) | ||
258 | { | ||
259 | int line = irq_to_gpio(irq); | ||
260 | int port = line >> 3; | ||
261 | |||
262 | gpio_int_unmasked[port] &= ~(1 << (line & 7)); | ||
263 | ep93xx_gpio_update_int_params(port); | ||
264 | } | ||
265 | |||
266 | static void ep93xx_gpio_irq_unmask(unsigned int irq) | ||
267 | { | ||
268 | int line = irq_to_gpio(irq); | ||
269 | int port = line >> 3; | ||
270 | |||
271 | gpio_int_unmasked[port] |= 1 << (line & 7); | ||
272 | ep93xx_gpio_update_int_params(port); | ||
273 | } | ||
274 | |||
275 | |||
276 | /* | ||
277 | * gpio_int_type1 controls whether the interrupt is level (0) or | ||
278 | * edge (1) triggered, while gpio_int_type2 controls whether it | ||
279 | * triggers on low/falling (0) or high/rising (1). | ||
280 | */ | ||
281 | static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | ||
282 | { | ||
283 | struct irq_desc *desc = irq_desc + irq; | ||
284 | const int gpio = irq_to_gpio(irq); | ||
285 | const int port = gpio >> 3; | ||
286 | const int port_mask = 1 << (gpio & 7); | ||
287 | |||
288 | gpio_direction_input(gpio); | ||
289 | |||
290 | switch (type) { | ||
291 | case IRQ_TYPE_EDGE_RISING: | ||
292 | gpio_int_type1[port] |= port_mask; | ||
293 | gpio_int_type2[port] |= port_mask; | ||
294 | desc->handle_irq = handle_edge_irq; | ||
295 | break; | ||
296 | case IRQ_TYPE_EDGE_FALLING: | ||
297 | gpio_int_type1[port] |= port_mask; | ||
298 | gpio_int_type2[port] &= ~port_mask; | ||
299 | desc->handle_irq = handle_edge_irq; | ||
300 | break; | ||
301 | case IRQ_TYPE_LEVEL_HIGH: | ||
302 | gpio_int_type1[port] &= ~port_mask; | ||
303 | gpio_int_type2[port] |= port_mask; | ||
304 | desc->handle_irq = handle_level_irq; | ||
305 | break; | ||
306 | case IRQ_TYPE_LEVEL_LOW: | ||
307 | gpio_int_type1[port] &= ~port_mask; | ||
308 | gpio_int_type2[port] &= ~port_mask; | ||
309 | desc->handle_irq = handle_level_irq; | ||
310 | break; | ||
311 | case IRQ_TYPE_EDGE_BOTH: | ||
312 | gpio_int_type1[port] |= port_mask; | ||
313 | /* set initial polarity based on current input level */ | ||
314 | if (gpio_get_value(gpio)) | ||
315 | gpio_int_type2[port] &= ~port_mask; /* falling */ | ||
316 | else | ||
317 | gpio_int_type2[port] |= port_mask; /* rising */ | ||
318 | desc->handle_irq = handle_edge_irq; | ||
319 | break; | ||
320 | default: | ||
321 | pr_err("ep93xx: failed to set irq type %d for gpio %d\n", | ||
322 | type, gpio); | ||
323 | return -EINVAL; | ||
324 | } | ||
325 | |||
326 | gpio_int_enabled[port] |= port_mask; | ||
327 | |||
328 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | ||
329 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | ||
330 | |||
331 | ep93xx_gpio_update_int_params(port); | ||
332 | |||
333 | return 0; | ||
334 | } | ||
335 | |||
336 | static struct irq_chip ep93xx_gpio_irq_chip = { | ||
337 | .name = "GPIO", | ||
338 | .ack = ep93xx_gpio_irq_ack, | ||
339 | .mask_ack = ep93xx_gpio_irq_mask_ack, | ||
340 | .mask = ep93xx_gpio_irq_mask, | ||
341 | .unmask = ep93xx_gpio_irq_unmask, | ||
342 | .set_type = ep93xx_gpio_irq_type, | ||
343 | }; | ||
344 | |||
345 | 175 | ||
346 | void __init ep93xx_init_irq(void) | 176 | void __init ep93xx_init_irq(void) |
347 | { | 177 | { |
348 | int gpio_irq; | ||
349 | |||
350 | vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); | 178 | vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); |
351 | vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); | 179 | vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); |
352 | 180 | ||
353 | for (gpio_irq = gpio_to_irq(0); | 181 | ep93xx_gpio_init_irq(); |
354 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { | ||
355 | set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); | ||
356 | set_irq_handler(gpio_irq, handle_level_irq); | ||
357 | set_irq_flags(gpio_irq, IRQF_VALID); | ||
358 | } | ||
359 | |||
360 | set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); | ||
361 | set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); | ||
362 | set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); | ||
363 | set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); | ||
364 | set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); | ||
365 | set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); | ||
366 | set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); | ||
367 | set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); | ||
368 | set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); | ||
369 | } | 182 | } |
370 | 183 | ||
371 | 184 | ||
@@ -572,9 +385,9 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, | |||
572 | * CMOS driver. | 385 | * CMOS driver. |
573 | */ | 386 | */ |
574 | if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT) | 387 | if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT) |
575 | pr_warning("ep93xx: sda != EEDAT, open drain has no effect\n"); | 388 | pr_warning("sda != EEDAT, open drain has no effect\n"); |
576 | if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK) | 389 | if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK) |
577 | pr_warning("ep93xx: scl != EECLK, open drain has no effect\n"); | 390 | pr_warning("scl != EECLK, open drain has no effect\n"); |
578 | 391 | ||
579 | __raw_writel((data->sda_is_open_drain << 1) | | 392 | __raw_writel((data->sda_is_open_drain << 1) | |
580 | (data->scl_is_open_drain << 0), | 393 | (data->scl_is_open_drain << 0), |
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c index dbcac9c40a28..8904ca4e2e24 100644 --- a/arch/arm/mach-ep93xx/dma-m2p.c +++ b/arch/arm/mach-ep93xx/dma-m2p.c | |||
@@ -28,6 +28,8 @@ | |||
28 | * with this implementation. | 28 | * with this implementation. |
29 | */ | 29 | */ |
30 | 30 | ||
31 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt | ||
32 | |||
31 | #include <linux/kernel.h> | 33 | #include <linux/kernel.h> |
32 | #include <linux/clk.h> | 34 | #include <linux/clk.h> |
33 | #include <linux/err.h> | 35 | #include <linux/err.h> |
@@ -173,7 +175,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id) | |||
173 | 175 | ||
174 | switch (m2p_channel_state(ch)) { | 176 | switch (m2p_channel_state(ch)) { |
175 | case STATE_IDLE: | 177 | case STATE_IDLE: |
176 | pr_crit("m2p_irq: dma interrupt without a dma buffer\n"); | 178 | pr_crit("dma interrupt without a dma buffer\n"); |
177 | BUG(); | 179 | BUG(); |
178 | break; | 180 | break; |
179 | 181 | ||
@@ -197,7 +199,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id) | |||
197 | break; | 199 | break; |
198 | 200 | ||
199 | case STATE_NEXT: | 201 | case STATE_NEXT: |
200 | pr_crit("m2p_irq: dma interrupt while next\n"); | 202 | pr_crit("dma interrupt while next\n"); |
201 | BUG(); | 203 | BUG(); |
202 | break; | 204 | break; |
203 | } | 205 | } |
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index a4a7be308000..d22d67ac8b99 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c | |||
@@ -118,12 +118,33 @@ static void __init edb93xx_register_i2c(void) | |||
118 | } | 118 | } |
119 | } | 119 | } |
120 | 120 | ||
121 | |||
122 | /************************************************************************* | ||
123 | * EDB93xx pwm | ||
124 | *************************************************************************/ | ||
125 | static void __init edb93xx_register_pwm(void) | ||
126 | { | ||
127 | if (machine_is_edb9301() || | ||
128 | machine_is_edb9302() || machine_is_edb9302a()) { | ||
129 | /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */ | ||
130 | ep93xx_register_pwm(0, 1); | ||
131 | } else if (machine_is_edb9307() || machine_is_edb9307a()) { | ||
132 | /* EP9307 only has pwm.0 (PWMOUT) */ | ||
133 | ep93xx_register_pwm(1, 0); | ||
134 | } else { | ||
135 | /* EP9312 and EP9315 have both */ | ||
136 | ep93xx_register_pwm(1, 1); | ||
137 | } | ||
138 | } | ||
139 | |||
140 | |||
121 | static void __init edb93xx_init_machine(void) | 141 | static void __init edb93xx_init_machine(void) |
122 | { | 142 | { |
123 | ep93xx_init_devices(); | 143 | ep93xx_init_devices(); |
124 | edb93xx_register_flash(); | 144 | edb93xx_register_flash(); |
125 | ep93xx_register_eth(&edb93xx_eth_data, 1); | 145 | ep93xx_register_eth(&edb93xx_eth_data, 1); |
126 | edb93xx_register_i2c(); | 146 | edb93xx_register_i2c(); |
147 | edb93xx_register_pwm(); | ||
127 | } | 148 | } |
128 | 149 | ||
129 | 150 | ||
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 1ea8871e03a9..cc377ae8c428 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c | |||
@@ -13,6 +13,8 @@ | |||
13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt | ||
17 | |||
16 | #include <linux/init.h> | 18 | #include <linux/init.h> |
17 | #include <linux/module.h> | 19 | #include <linux/module.h> |
18 | #include <linux/seq_file.h> | 20 | #include <linux/seq_file.h> |
@@ -22,6 +24,235 @@ | |||
22 | 24 | ||
23 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
24 | 26 | ||
27 | /************************************************************************* | ||
28 | * GPIO handling for EP93xx | ||
29 | *************************************************************************/ | ||
30 | static unsigned char gpio_int_unmasked[3]; | ||
31 | static unsigned char gpio_int_enabled[3]; | ||
32 | static unsigned char gpio_int_type1[3]; | ||
33 | static unsigned char gpio_int_type2[3]; | ||
34 | static unsigned char gpio_int_debounce[3]; | ||
35 | |||
36 | /* Port ordering is: A B F */ | ||
37 | static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; | ||
38 | static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; | ||
39 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; | ||
40 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; | ||
41 | static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; | ||
42 | |||
43 | void ep93xx_gpio_update_int_params(unsigned port) | ||
44 | { | ||
45 | BUG_ON(port > 2); | ||
46 | |||
47 | __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port])); | ||
48 | |||
49 | __raw_writeb(gpio_int_type2[port], | ||
50 | EP93XX_GPIO_REG(int_type2_register_offset[port])); | ||
51 | |||
52 | __raw_writeb(gpio_int_type1[port], | ||
53 | EP93XX_GPIO_REG(int_type1_register_offset[port])); | ||
54 | |||
55 | __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], | ||
56 | EP93XX_GPIO_REG(int_en_register_offset[port])); | ||
57 | } | ||
58 | |||
59 | void ep93xx_gpio_int_mask(unsigned line) | ||
60 | { | ||
61 | gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); | ||
62 | } | ||
63 | |||
64 | void ep93xx_gpio_int_debounce(unsigned int irq, int enable) | ||
65 | { | ||
66 | int line = irq_to_gpio(irq); | ||
67 | int port = line >> 3; | ||
68 | int port_mask = 1 << (line & 7); | ||
69 | |||
70 | if (enable) | ||
71 | gpio_int_debounce[port] |= port_mask; | ||
72 | else | ||
73 | gpio_int_debounce[port] &= ~port_mask; | ||
74 | |||
75 | __raw_writeb(gpio_int_debounce[port], | ||
76 | EP93XX_GPIO_REG(int_debounce_register_offset[port])); | ||
77 | } | ||
78 | EXPORT_SYMBOL(ep93xx_gpio_int_debounce); | ||
79 | |||
80 | static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
81 | { | ||
82 | unsigned char status; | ||
83 | int i; | ||
84 | |||
85 | status = __raw_readb(EP93XX_GPIO_A_INT_STATUS); | ||
86 | for (i = 0; i < 8; i++) { | ||
87 | if (status & (1 << i)) { | ||
88 | int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; | ||
89 | generic_handle_irq(gpio_irq); | ||
90 | } | ||
91 | } | ||
92 | |||
93 | status = __raw_readb(EP93XX_GPIO_B_INT_STATUS); | ||
94 | for (i = 0; i < 8; i++) { | ||
95 | if (status & (1 << i)) { | ||
96 | int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; | ||
97 | generic_handle_irq(gpio_irq); | ||
98 | } | ||
99 | } | ||
100 | } | ||
101 | |||
102 | static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
103 | { | ||
104 | /* | ||
105 | * map discontiguous hw irq range to continous sw irq range: | ||
106 | * | ||
107 | * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) | ||
108 | */ | ||
109 | int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ | ||
110 | int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; | ||
111 | |||
112 | generic_handle_irq(gpio_irq); | ||
113 | } | ||
114 | |||
115 | static void ep93xx_gpio_irq_ack(unsigned int irq) | ||
116 | { | ||
117 | int line = irq_to_gpio(irq); | ||
118 | int port = line >> 3; | ||
119 | int port_mask = 1 << (line & 7); | ||
120 | |||
121 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | ||
122 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | ||
123 | ep93xx_gpio_update_int_params(port); | ||
124 | } | ||
125 | |||
126 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | ||
127 | } | ||
128 | |||
129 | static void ep93xx_gpio_irq_mask_ack(unsigned int irq) | ||
130 | { | ||
131 | int line = irq_to_gpio(irq); | ||
132 | int port = line >> 3; | ||
133 | int port_mask = 1 << (line & 7); | ||
134 | |||
135 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) | ||
136 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | ||
137 | |||
138 | gpio_int_unmasked[port] &= ~port_mask; | ||
139 | ep93xx_gpio_update_int_params(port); | ||
140 | |||
141 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | ||
142 | } | ||
143 | |||
144 | static void ep93xx_gpio_irq_mask(unsigned int irq) | ||
145 | { | ||
146 | int line = irq_to_gpio(irq); | ||
147 | int port = line >> 3; | ||
148 | |||
149 | gpio_int_unmasked[port] &= ~(1 << (line & 7)); | ||
150 | ep93xx_gpio_update_int_params(port); | ||
151 | } | ||
152 | |||
153 | static void ep93xx_gpio_irq_unmask(unsigned int irq) | ||
154 | { | ||
155 | int line = irq_to_gpio(irq); | ||
156 | int port = line >> 3; | ||
157 | |||
158 | gpio_int_unmasked[port] |= 1 << (line & 7); | ||
159 | ep93xx_gpio_update_int_params(port); | ||
160 | } | ||
161 | |||
162 | /* | ||
163 | * gpio_int_type1 controls whether the interrupt is level (0) or | ||
164 | * edge (1) triggered, while gpio_int_type2 controls whether it | ||
165 | * triggers on low/falling (0) or high/rising (1). | ||
166 | */ | ||
167 | static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | ||
168 | { | ||
169 | struct irq_desc *desc = irq_desc + irq; | ||
170 | const int gpio = irq_to_gpio(irq); | ||
171 | const int port = gpio >> 3; | ||
172 | const int port_mask = 1 << (gpio & 7); | ||
173 | |||
174 | gpio_direction_input(gpio); | ||
175 | |||
176 | switch (type) { | ||
177 | case IRQ_TYPE_EDGE_RISING: | ||
178 | gpio_int_type1[port] |= port_mask; | ||
179 | gpio_int_type2[port] |= port_mask; | ||
180 | desc->handle_irq = handle_edge_irq; | ||
181 | break; | ||
182 | case IRQ_TYPE_EDGE_FALLING: | ||
183 | gpio_int_type1[port] |= port_mask; | ||
184 | gpio_int_type2[port] &= ~port_mask; | ||
185 | desc->handle_irq = handle_edge_irq; | ||
186 | break; | ||
187 | case IRQ_TYPE_LEVEL_HIGH: | ||
188 | gpio_int_type1[port] &= ~port_mask; | ||
189 | gpio_int_type2[port] |= port_mask; | ||
190 | desc->handle_irq = handle_level_irq; | ||
191 | break; | ||
192 | case IRQ_TYPE_LEVEL_LOW: | ||
193 | gpio_int_type1[port] &= ~port_mask; | ||
194 | gpio_int_type2[port] &= ~port_mask; | ||
195 | desc->handle_irq = handle_level_irq; | ||
196 | break; | ||
197 | case IRQ_TYPE_EDGE_BOTH: | ||
198 | gpio_int_type1[port] |= port_mask; | ||
199 | /* set initial polarity based on current input level */ | ||
200 | if (gpio_get_value(gpio)) | ||
201 | gpio_int_type2[port] &= ~port_mask; /* falling */ | ||
202 | else | ||
203 | gpio_int_type2[port] |= port_mask; /* rising */ | ||
204 | desc->handle_irq = handle_edge_irq; | ||
205 | break; | ||
206 | default: | ||
207 | pr_err("failed to set irq type %d for gpio %d\n", type, gpio); | ||
208 | return -EINVAL; | ||
209 | } | ||
210 | |||
211 | gpio_int_enabled[port] |= port_mask; | ||
212 | |||
213 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | ||
214 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | ||
215 | |||
216 | ep93xx_gpio_update_int_params(port); | ||
217 | |||
218 | return 0; | ||
219 | } | ||
220 | |||
221 | static struct irq_chip ep93xx_gpio_irq_chip = { | ||
222 | .name = "GPIO", | ||
223 | .ack = ep93xx_gpio_irq_ack, | ||
224 | .mask_ack = ep93xx_gpio_irq_mask_ack, | ||
225 | .mask = ep93xx_gpio_irq_mask, | ||
226 | .unmask = ep93xx_gpio_irq_unmask, | ||
227 | .set_type = ep93xx_gpio_irq_type, | ||
228 | }; | ||
229 | |||
230 | void __init ep93xx_gpio_init_irq(void) | ||
231 | { | ||
232 | int gpio_irq; | ||
233 | |||
234 | for (gpio_irq = gpio_to_irq(0); | ||
235 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { | ||
236 | set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); | ||
237 | set_irq_handler(gpio_irq, handle_level_irq); | ||
238 | set_irq_flags(gpio_irq, IRQF_VALID); | ||
239 | } | ||
240 | |||
241 | set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); | ||
242 | set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); | ||
243 | set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); | ||
244 | set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); | ||
245 | set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); | ||
246 | set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); | ||
247 | set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); | ||
248 | set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); | ||
249 | set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); | ||
250 | } | ||
251 | |||
252 | |||
253 | /************************************************************************* | ||
254 | * gpiolib interface for EP93xx on-chip GPIOs | ||
255 | *************************************************************************/ | ||
25 | struct ep93xx_gpio_chip { | 256 | struct ep93xx_gpio_chip { |
26 | struct gpio_chip chip; | 257 | struct gpio_chip chip; |
27 | 258 | ||
@@ -31,10 +262,6 @@ struct ep93xx_gpio_chip { | |||
31 | 262 | ||
32 | #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) | 263 | #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) |
33 | 264 | ||
34 | /* From core.c */ | ||
35 | extern void ep93xx_gpio_int_mask(unsigned line); | ||
36 | extern void ep93xx_gpio_update_int_params(unsigned port); | ||
37 | |||
38 | static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | 265 | static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
39 | { | 266 | { |
40 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | 267 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); |
diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S index 802858bc8095..5cd22444e223 100644 --- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | #include <mach/ep93xx-regs.h> | 12 | #include <mach/ep93xx-regs.h> |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base | 17 | ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base |
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index d55194a4c093..93e2ecc79ceb 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | |||
@@ -92,21 +92,6 @@ | |||
92 | 92 | ||
93 | /* APB peripherals */ | 93 | /* APB peripherals */ |
94 | #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) | 94 | #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) |
95 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) | ||
96 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) | ||
97 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) | ||
98 | #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) | ||
99 | #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) | ||
100 | #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) | ||
101 | #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) | ||
102 | #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) | ||
103 | #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) | ||
104 | #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) | ||
105 | #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) | ||
106 | #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) | ||
107 | #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) | ||
108 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) | ||
109 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) | ||
110 | 95 | ||
111 | #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) | 96 | #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) |
112 | 97 | ||
@@ -167,8 +152,11 @@ | |||
167 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16) | 152 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16) |
168 | #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) | 153 | #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) |
169 | #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) | 154 | #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) |
170 | #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) | 155 | #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) |
171 | #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) | 156 | #define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23) |
157 | #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) | ||
158 | #define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19) | ||
159 | #define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18) | ||
172 | #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) | 160 | #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) |
173 | #define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) | 161 | #define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) |
174 | #define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) | 162 | #define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) |
diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h index aed21cd3fe2d..1b3f25d03d39 100644 --- a/arch/arm/mach-ep93xx/include/mach/vmalloc.h +++ b/arch/arm/mach-ep93xx/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-ep93xx/include/mach/vmalloc.h | 2 | * arch/arm/mach-ep93xx/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe800000 | 5 | #define VMALLOC_END 0xfe800000UL |
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c new file mode 100644 index 000000000000..cd93990f1b99 --- /dev/null +++ b/arch/arm/mach-ep93xx/simone.c | |||
@@ -0,0 +1,97 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ep93xx/simone.c | ||
3 | * Simplemachines Sim.One support. | ||
4 | * | ||
5 | * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com> | ||
6 | * | ||
7 | * Based on the 2.6.24.7 support: | ||
8 | * Copyright (C) 2009 Simplemachines | ||
9 | * MMC support by Peter Ivanov <ivanovp@gmail.com>, 2007 | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or (at | ||
14 | * your option) any later version. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/mtd/physmap.h> | ||
22 | #include <linux/gpio.h> | ||
23 | #include <linux/i2c.h> | ||
24 | #include <linux/i2c-gpio.h> | ||
25 | |||
26 | #include <mach/hardware.h> | ||
27 | #include <mach/fb.h> | ||
28 | |||
29 | #include <asm/mach-types.h> | ||
30 | #include <asm/mach/arch.h> | ||
31 | |||
32 | static struct physmap_flash_data simone_flash_data = { | ||
33 | .width = 2, | ||
34 | }; | ||
35 | |||
36 | static struct resource simone_flash_resource = { | ||
37 | .start = EP93XX_CS6_PHYS_BASE, | ||
38 | .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1, | ||
39 | .flags = IORESOURCE_MEM, | ||
40 | }; | ||
41 | |||
42 | static struct platform_device simone_flash = { | ||
43 | .name = "physmap-flash", | ||
44 | .id = 0, | ||
45 | .num_resources = 1, | ||
46 | .resource = &simone_flash_resource, | ||
47 | .dev = { | ||
48 | .platform_data = &simone_flash_data, | ||
49 | }, | ||
50 | }; | ||
51 | |||
52 | static struct ep93xx_eth_data simone_eth_data = { | ||
53 | .phy_id = 1, | ||
54 | }; | ||
55 | |||
56 | static struct ep93xxfb_mach_info simone_fb_info = { | ||
57 | .num_modes = EP93XXFB_USE_MODEDB, | ||
58 | .bpp = 16, | ||
59 | .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, | ||
60 | }; | ||
61 | |||
62 | static struct i2c_gpio_platform_data simone_i2c_gpio_data = { | ||
63 | .sda_pin = EP93XX_GPIO_LINE_EEDAT, | ||
64 | .sda_is_open_drain = 0, | ||
65 | .scl_pin = EP93XX_GPIO_LINE_EECLK, | ||
66 | .scl_is_open_drain = 0, | ||
67 | .udelay = 0, | ||
68 | .timeout = 0, | ||
69 | }; | ||
70 | |||
71 | static struct i2c_board_info __initdata simone_i2c_board_info[] = { | ||
72 | { | ||
73 | I2C_BOARD_INFO("ds1337", 0x68), | ||
74 | }, | ||
75 | }; | ||
76 | |||
77 | static void __init simone_init_machine(void) | ||
78 | { | ||
79 | ep93xx_init_devices(); | ||
80 | |||
81 | platform_device_register(&simone_flash); | ||
82 | ep93xx_register_eth(&simone_eth_data, 1); | ||
83 | ep93xx_register_fb(&simone_fb_info); | ||
84 | ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, | ||
85 | ARRAY_SIZE(simone_i2c_board_info)); | ||
86 | } | ||
87 | |||
88 | MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") | ||
89 | /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */ | ||
90 | .phys_io = EP93XX_APB_PHYS_BASE, | ||
91 | .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, | ||
92 | .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, | ||
93 | .map_io = ep93xx_map_io, | ||
94 | .init_irq = ep93xx_init_irq, | ||
95 | .timer = &ep93xx_timer, | ||
96 | .init_machine = simone_init_machine, | ||
97 | MACHINE_END | ||
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c new file mode 100644 index 000000000000..51134b0382ca --- /dev/null +++ b/arch/arm/mach-ep93xx/snappercl15.c | |||
@@ -0,0 +1,172 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ep93xx/snappercl15.c | ||
3 | * Bluewater Systems Snapper CL15 system module | ||
4 | * | ||
5 | * Copyright (C) 2009 Bluewater Systems Ltd | ||
6 | * Author: Ryan Mallon <ryan@bluewatersys.com> | ||
7 | * | ||
8 | * NAND code adapted from driver by: | ||
9 | * Andre Renaud <andre@bluewatersys.com> | ||
10 | * James R. McKaskill | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License as published by | ||
14 | * the Free Software Foundation; either version 2 of the License, or (at | ||
15 | * your option) any later version. | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/gpio.h> | ||
24 | #include <linux/i2c.h> | ||
25 | #include <linux/i2c-gpio.h> | ||
26 | #include <linux/fb.h> | ||
27 | |||
28 | #include <linux/mtd/partitions.h> | ||
29 | #include <linux/mtd/nand.h> | ||
30 | |||
31 | #include <mach/hardware.h> | ||
32 | #include <mach/fb.h> | ||
33 | |||
34 | #include <asm/mach-types.h> | ||
35 | #include <asm/mach/arch.h> | ||
36 | |||
37 | #define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M) | ||
38 | |||
39 | #define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */ | ||
40 | #define SNAPPERCL15_NAND_ALE (1 << 9) /* Address latch */ | ||
41 | #define SNAPPERCL15_NAND_CLE (1 << 10) /* Command latch */ | ||
42 | #define SNAPPERCL15_NAND_CEN (1 << 11) /* Chip enable (active low) */ | ||
43 | #define SNAPPERCL15_NAND_RDY (1 << 14) /* Device ready */ | ||
44 | |||
45 | #define NAND_CTRL_ADDR(chip) (chip->IO_ADDR_W + 0x40) | ||
46 | |||
47 | static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | ||
48 | unsigned int ctrl) | ||
49 | { | ||
50 | struct nand_chip *chip = mtd->priv; | ||
51 | static u16 nand_state = SNAPPERCL15_NAND_WPN; | ||
52 | u16 set; | ||
53 | |||
54 | if (ctrl & NAND_CTRL_CHANGE) { | ||
55 | set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN; | ||
56 | |||
57 | if (ctrl & NAND_NCE) | ||
58 | set &= ~SNAPPERCL15_NAND_CEN; | ||
59 | if (ctrl & NAND_CLE) | ||
60 | set |= SNAPPERCL15_NAND_CLE; | ||
61 | if (ctrl & NAND_ALE) | ||
62 | set |= SNAPPERCL15_NAND_ALE; | ||
63 | |||
64 | nand_state &= ~(SNAPPERCL15_NAND_CEN | | ||
65 | SNAPPERCL15_NAND_CLE | | ||
66 | SNAPPERCL15_NAND_ALE); | ||
67 | nand_state |= set; | ||
68 | __raw_writew(nand_state, NAND_CTRL_ADDR(chip)); | ||
69 | } | ||
70 | |||
71 | if (cmd != NAND_CMD_NONE) | ||
72 | __raw_writew((cmd & 0xff) | nand_state, chip->IO_ADDR_W); | ||
73 | } | ||
74 | |||
75 | static int snappercl15_nand_dev_ready(struct mtd_info *mtd) | ||
76 | { | ||
77 | struct nand_chip *chip = mtd->priv; | ||
78 | |||
79 | return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY); | ||
80 | } | ||
81 | |||
82 | static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL}; | ||
83 | |||
84 | static struct mtd_partition snappercl15_nand_parts[] = { | ||
85 | { | ||
86 | .name = "Kernel", | ||
87 | .offset = 0, | ||
88 | .size = SZ_2M, | ||
89 | }, | ||
90 | { | ||
91 | .name = "Filesystem", | ||
92 | .offset = MTDPART_OFS_APPEND, | ||
93 | .size = MTDPART_SIZ_FULL, | ||
94 | }, | ||
95 | }; | ||
96 | |||
97 | static struct platform_nand_data snappercl15_nand_data = { | ||
98 | .chip = { | ||
99 | .nr_chips = 1, | ||
100 | .part_probe_types = snappercl15_nand_part_probes, | ||
101 | .partitions = snappercl15_nand_parts, | ||
102 | .nr_partitions = ARRAY_SIZE(snappercl15_nand_parts), | ||
103 | .options = NAND_NO_AUTOINCR, | ||
104 | .chip_delay = 25, | ||
105 | }, | ||
106 | .ctrl = { | ||
107 | .dev_ready = snappercl15_nand_dev_ready, | ||
108 | .cmd_ctrl = snappercl15_nand_cmd_ctrl, | ||
109 | }, | ||
110 | }; | ||
111 | |||
112 | static struct resource snappercl15_nand_resource[] = { | ||
113 | { | ||
114 | .start = SNAPPERCL15_NAND_BASE, | ||
115 | .end = SNAPPERCL15_NAND_BASE + SZ_4K - 1, | ||
116 | .flags = IORESOURCE_MEM, | ||
117 | }, | ||
118 | }; | ||
119 | |||
120 | static struct platform_device snappercl15_nand_device = { | ||
121 | .name = "gen_nand", | ||
122 | .id = -1, | ||
123 | .dev.platform_data = &snappercl15_nand_data, | ||
124 | .resource = snappercl15_nand_resource, | ||
125 | .num_resources = ARRAY_SIZE(snappercl15_nand_resource), | ||
126 | }; | ||
127 | |||
128 | static struct ep93xx_eth_data snappercl15_eth_data = { | ||
129 | .phy_id = 1, | ||
130 | }; | ||
131 | |||
132 | static struct i2c_gpio_platform_data snappercl15_i2c_gpio_data = { | ||
133 | .sda_pin = EP93XX_GPIO_LINE_EEDAT, | ||
134 | .sda_is_open_drain = 0, | ||
135 | .scl_pin = EP93XX_GPIO_LINE_EECLK, | ||
136 | .scl_is_open_drain = 0, | ||
137 | .udelay = 0, | ||
138 | .timeout = 0, | ||
139 | }; | ||
140 | |||
141 | static struct i2c_board_info __initdata snappercl15_i2c_data[] = { | ||
142 | { | ||
143 | /* Audio codec */ | ||
144 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | ||
145 | }, | ||
146 | }; | ||
147 | |||
148 | static struct ep93xxfb_mach_info snappercl15_fb_info = { | ||
149 | .num_modes = EP93XXFB_USE_MODEDB, | ||
150 | .bpp = 16, | ||
151 | }; | ||
152 | |||
153 | static void __init snappercl15_init_machine(void) | ||
154 | { | ||
155 | ep93xx_init_devices(); | ||
156 | ep93xx_register_eth(&snappercl15_eth_data, 1); | ||
157 | ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data, | ||
158 | ARRAY_SIZE(snappercl15_i2c_data)); | ||
159 | ep93xx_register_fb(&snappercl15_fb_info); | ||
160 | platform_device_register(&snappercl15_nand_device); | ||
161 | } | ||
162 | |||
163 | MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") | ||
164 | /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */ | ||
165 | .phys_io = EP93XX_APB_PHYS_BASE, | ||
166 | .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, | ||
167 | .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, | ||
168 | .map_io = ep93xx_map_io, | ||
169 | .init_irq = ep93xx_init_irq, | ||
170 | .timer = &ep93xx_timer, | ||
171 | .init_machine = snappercl15_init_machine, | ||
172 | MACHINE_END | ||
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 41febc796b1c..e3bc3f6f6b10 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c | |||
@@ -32,12 +32,13 @@ unsigned int mem_fclk_21285 = 50000000; | |||
32 | 32 | ||
33 | EXPORT_SYMBOL(mem_fclk_21285); | 33 | EXPORT_SYMBOL(mem_fclk_21285); |
34 | 34 | ||
35 | static void __init early_fclk(char **arg) | 35 | static int __init early_fclk(char *arg) |
36 | { | 36 | { |
37 | mem_fclk_21285 = simple_strtoul(*arg, arg, 0); | 37 | mem_fclk_21285 = simple_strtoul(arg, NULL, 0); |
38 | return 0; | ||
38 | } | 39 | } |
39 | 40 | ||
40 | __early_param("mem_fclk_21285=", early_fclk); | 41 | early_param("mem_fclk_21285", early_fclk); |
41 | 42 | ||
42 | static int __init parse_tag_memclk(const struct tag *tag) | 43 | static int __init parse_tag_memclk(const struct tag *tag) |
43 | { | 44 | { |
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S index 4329b8123570..60dda1318f22 100644 --- a/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S | |||
@@ -15,7 +15,7 @@ | |||
15 | 15 | ||
16 | #ifndef CONFIG_DEBUG_DC21285_PORT | 16 | #ifndef CONFIG_DEBUG_DC21285_PORT |
17 | /* For NetWinder debugging */ | 17 | /* For NetWinder debugging */ |
18 | .macro addruart,rx | 18 | .macro addruart, rx, tmp |
19 | mrc p15, 0, \rx, c1, c0 | 19 | mrc p15, 0, \rx, c1, c0 |
20 | tst \rx, #1 @ MMU enabled? | 20 | tst \rx, #1 @ MMU enabled? |
21 | moveq \rx, #0x7c000000 @ physical | 21 | moveq \rx, #0x7c000000 @ physical |
@@ -32,7 +32,7 @@ | |||
32 | .equ dc21285_high, ARMCSR_BASE & 0xff000000 | 32 | .equ dc21285_high, ARMCSR_BASE & 0xff000000 |
33 | .equ dc21285_low, ARMCSR_BASE & 0x00ffffff | 33 | .equ dc21285_low, ARMCSR_BASE & 0x00ffffff |
34 | 34 | ||
35 | .macro addruart,rx | 35 | .macro addruart, rx, tmp |
36 | mrc p15, 0, \rx, c1, c0 | 36 | mrc p15, 0, \rx, c1, c0 |
37 | tst \rx, #1 @ MMU enabled? | 37 | tst \rx, #1 @ MMU enabled? |
38 | moveq \rx, #0x42000000 | 38 | moveq \rx, #0x42000000 |
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S index d04a6eaeae14..ad477047069d 100644 --- a/arch/arm/mach-gemini/include/mach/debug-macro.S +++ b/arch/arm/mach-gemini/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | #include <mach/hardware.h> | 12 | #include <mach/hardware.h> |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | ldreq \rx, =GEMINI_UART_BASE @ physical | 17 | ldreq \rx, =GEMINI_UART_BASE @ physical |
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h index 83e536d9436c..45371eb86fcb 100644 --- a/arch/arm/mach-gemini/include/mach/vmalloc.h +++ b/arch/arm/mach-gemini/include/mach/vmalloc.h | |||
@@ -7,4 +7,4 @@ | |||
7 | * (at your option) any later version. | 7 | * (at your option) any later version. |
8 | */ | 8 | */ |
9 | 9 | ||
10 | #define VMALLOC_END 0xF0000000 | 10 | #define VMALLOC_END 0xf0000000UL |
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S index 6294a1344dda..a9ee8f0d48b7 100644 --- a/arch/arm/mach-h720x/include/mach/debug-macro.S +++ b/arch/arm/mach-h720x/include/mach/debug-macro.S | |||
@@ -14,7 +14,7 @@ | |||
14 | .equ io_virt, IO_BASE | 14 | .equ io_virt, IO_BASE |
15 | .equ io_phys, IO_START | 15 | .equ io_phys, IO_START |
16 | 16 | ||
17 | .macro addruart,rx | 17 | .macro addruart, rx, tmp |
18 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
19 | tst \rx, #1 @ MMU enabled? | 19 | tst \rx, #1 @ MMU enabled? |
20 | moveq \rx, #io_phys @ physical base address | 20 | moveq \rx, #io_phys @ physical base address |
diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S index d347d659ea30..87a6888ae011 100644 --- a/arch/arm/mach-integrator/include/mach/debug-macro.S +++ b/arch/arm/mach-integrator/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | moveq \rx, #0x16000000 @ physical base address | 17 | moveq \rx, #0x16000000 @ physical base address |
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S index 9037d2e8557c..c9d6ba46963d 100644 --- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S +++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart, rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ mmu enabled? | 16 | tst \rx, #1 @ mmu enabled? |
17 | moveq \rx, #0xff000000 @ physical | 17 | moveq \rx, #0xff000000 @ physical |
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c index 529580997814..48642e66c566 100644 --- a/arch/arm/mach-iop13xx/io.c +++ b/arch/arm/mach-iop13xx/io.c | |||
@@ -61,9 +61,9 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size, | |||
61 | (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); | 61 | (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); |
62 | break; | 62 | break; |
63 | case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: | 63 | case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: |
64 | retval = __arm_ioremap(IOP13XX_PBI_LOWER_MEM_PA + | 64 | retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA + |
65 | (cookie - IOP13XX_PBI_LOWER_MEM_RA), | 65 | (cookie - IOP13XX_PBI_LOWER_MEM_RA), |
66 | size, mtype); | 66 | size, mtype, __builtin_return_address(0)); |
67 | break; | 67 | break; |
68 | case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: | 68 | case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: |
69 | retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); | 69 | retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); |
@@ -75,7 +75,8 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size, | |||
75 | retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); | 75 | retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); |
76 | break; | 76 | break; |
77 | default: | 77 | default: |
78 | retval = __arm_ioremap(cookie, size, mtype); | 78 | retval = __arm_ioremap_caller(cookie, size, mtype, |
79 | __builtin_return_address(0)); | ||
79 | } | 80 | } |
80 | 81 | ||
81 | return retval; | 82 | return retval; |
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S index 58b01664ffba..736afe1edd1f 100644 --- a/arch/arm/mach-iop32x/include/mach/debug-macro.S +++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart, rx | 14 | .macro addruart, rx, tmp |
15 | mov \rx, #0xfe000000 @ physical as well as virtual | 15 | mov \rx, #0xfe000000 @ physical as well as virtual |
16 | orr \rx, \rx, #0x00800000 @ location of the UART | 16 | orr \rx, \rx, #0x00800000 @ location of the UART |
17 | .endm | 17 | .endm |
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h index 85ceb09d85f0..c4862d48e583 100644 --- a/arch/arm/mach-iop32x/include/mach/vmalloc.h +++ b/arch/arm/mach-iop32x/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-iop32x/include/mach/vmalloc.h | 2 | * arch/arm/mach-iop32x/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe000000 | 5 | #define VMALLOC_END 0xfe000000UL |
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S index a60c9ef05cc3..addb2da78422 100644 --- a/arch/arm/mach-iop33x/include/mach/debug-macro.S +++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart, rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ mmu enabled? | 16 | tst \rx, #1 @ mmu enabled? |
17 | moveq \rx, #0xff000000 @ physical | 17 | moveq \rx, #0xff000000 @ physical |
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h index f9f99dea9bc4..48331dc23704 100644 --- a/arch/arm/mach-iop33x/include/mach/vmalloc.h +++ b/arch/arm/mach-iop33x/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-iop33x/include/mach/vmalloc.h | 2 | * arch/arm/mach-iop33x/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe000000 | 5 | #define VMALLOC_END 0xfe000000UL |
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S index 904ff56d2246..6a827681680f 100644 --- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | moveq \rx, #0xc0000000 @ Physical base | 17 | moveq \rx, #0xc0000000 @ Physical base |
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h index d195e35aed3b..61c8dae24f95 100644 --- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h +++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h | |||
@@ -17,4 +17,4 @@ | |||
17 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | 17 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced |
18 | * area for the same reason. ;) | 18 | * area for the same reason. ;) |
19 | */ | 19 | */ |
20 | #define VMALLOC_END 0xfb000000 | 20 | #define VMALLOC_END 0xfb000000UL |
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S index 905db3188724..a82e375465e2 100644 --- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S | |||
@@ -12,7 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | #include <mach/ixp23xx.h> | 13 | #include <mach/ixp23xx.h> |
14 | 14 | ||
15 | .macro addruart,rx | 15 | .macro addruart, rx, tmp |
16 | mrc p15, 0, \rx, c1, c0 | 16 | mrc p15, 0, \rx, c1, c0 |
17 | tst \rx, #1 @ mmu enabled? | 17 | tst \rx, #1 @ mmu enabled? |
18 | ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical | 18 | ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical |
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h index dd519f678d10..896c56a1c00e 100644 --- a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h +++ b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h | |||
@@ -7,4 +7,4 @@ | |||
7 | * specific static I/O. | 7 | * specific static I/O. |
8 | */ | 8 | */ |
9 | 9 | ||
10 | #define VMALLOC_END (0xec000000) | 10 | #define VMALLOC_END (0xec000000UL) |
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 3bbf40f6d964..71728d36d501 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -427,6 +427,17 @@ static void __init ixp4xx_clocksource_init(void) | |||
427 | } | 427 | } |
428 | 428 | ||
429 | /* | 429 | /* |
430 | * sched_clock() | ||
431 | */ | ||
432 | unsigned long long sched_clock(void) | ||
433 | { | ||
434 | cycle_t cyc = ixp4xx_get_cycles(NULL); | ||
435 | struct clocksource *cs = &clocksource_ixp4xx; | ||
436 | |||
437 | return clocksource_cyc2ns(cyc, cs->mult, cs->shift); | ||
438 | } | ||
439 | |||
440 | /* | ||
430 | * clockevents | 441 | * clockevents |
431 | */ | 442 | */ |
432 | static int ixp4xx_set_next_event(unsigned long evt, | 443 | static int ixp4xx_set_next_event(unsigned long evt, |
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S index 7c6a6912acde..893873eb2a0d 100644 --- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S | |||
@@ -10,7 +10,7 @@ | |||
10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | .macro addruart,rx | 13 | .macro addruart, rx, tmp |
14 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
15 | tst \rx, #1 @ MMU enabled? | 15 | tst \rx, #1 @ MMU enabled? |
16 | moveq \rx, #0xc8000000 | 16 | moveq \rx, #0xc8000000 |
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h index 7b3580b53adf..9bcd64d59854 100644 --- a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h +++ b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-ixp4xx/include/mach/vmalloc.h | 2 | * arch/arm/mach-ixp4xx/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | #define VMALLOC_END (0xFF000000) | 4 | #define VMALLOC_END (0xff000000UL) |
5 | 5 | ||
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S index a4a55c199d77..d0606774dea7 100644 --- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S +++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | 8 | ||
9 | #include <mach/bridge-regs.h> | 9 | #include <mach/bridge-regs.h> |
10 | 10 | ||
11 | .macro addruart,rx | 11 | .macro addruart, rx, tmp |
12 | mrc p15, 0, \rx, c1, c0 | 12 | mrc p15, 0, \rx, c1, c0 |
13 | tst \rx, #1 @ MMU enabled? | 13 | tst \rx, #1 @ MMU enabled? |
14 | ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE | 14 | ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE |
diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h index 8f48260dcdad..bf162ca3d2c1 100644 --- a/arch/arm/mach-kirkwood/include/mach/vmalloc.h +++ b/arch/arm/mach-kirkwood/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-kirkwood/include/mach/vmalloc.h | 2 | * arch/arm/mach-kirkwood/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe800000 | 5 | #define VMALLOC_END 0xfe800000UL |
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S index 3782c3559497..cf2095da2372 100644 --- a/arch/arm/mach-ks8695/include/mach/debug-macro.S +++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
15 | #include <mach/regs-uart.h> | 15 | #include <mach/regs-uart.h> |
16 | 16 | ||
17 | .macro addruart, rx | 17 | .macro addruart, rx, tmp |
18 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
19 | tst \rx, #1 @ MMU enabled? | 19 | tst \rx, #1 @ MMU enabled? |
20 | ldreq \rx, =KS8695_UART_PA @ physical base address | 20 | ldreq \rx, =KS8695_UART_PA @ physical base address |
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S index 34eed2a63e69..b69ed344c7c9 100644 --- a/arch/arm/mach-l7200/include/mach/debug-macro.S +++ b/arch/arm/mach-l7200/include/mach/debug-macro.S | |||
@@ -14,7 +14,7 @@ | |||
14 | .equ io_virt, IO_BASE | 14 | .equ io_virt, IO_BASE |
15 | .equ io_phys, IO_START | 15 | .equ io_phys, IO_START |
16 | 16 | ||
17 | .macro addruart,rx | 17 | .macro addruart, rx, tmp |
18 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
19 | tst \rx, #1 @ MMU enabled? | 19 | tst \rx, #1 @ MMU enabled? |
20 | moveq \rx, #io_phys @ physical base address | 20 | moveq \rx, #io_phys @ physical base address |
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S index 85141ed5383d..c0dcbbba22ba 100644 --- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S +++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S | |||
@@ -14,7 +14,7 @@ | |||
14 | @ It is not known if this will be appropriate for every 40x | 14 | @ It is not known if this will be appropriate for every 40x |
15 | @ board. | 15 | @ board. |
16 | 16 | ||
17 | .macro addruart,rx | 17 | .macro addruart, rx, tmp |
18 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
19 | tst \rx, #1 @ MMU enabled? | 19 | tst \rx, #1 @ MMU enabled? |
20 | mov \rx, #0x00000700 @ offset from base | 20 | mov \rx, #0x00000700 @ offset from base |
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h index 3fbd49490bb9..d62da7358b16 100644 --- a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h +++ b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h | |||
@@ -7,4 +7,4 @@ | |||
7 | * version 2 as published by the Free Software Foundation. | 7 | * version 2 as published by the Free Software Foundation. |
8 | * | 8 | * |
9 | */ | 9 | */ |
10 | #define VMALLOC_END (0xe8000000) | 10 | #define VMALLOC_END (0xe8000000UL) |
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S index a8c20bd2f951..3136c913a92c 100644 --- a/arch/arm/mach-loki/include/mach/debug-macro.S +++ b/arch/arm/mach-loki/include/mach/debug-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | 8 | ||
9 | #include <mach/loki.h> | 9 | #include <mach/loki.h> |
10 | 10 | ||
11 | .macro addruart,rx | 11 | .macro addruart, rx, tmp |
12 | mrc p15, 0, \rx, c1, c0 | 12 | mrc p15, 0, \rx, c1, c0 |
13 | tst \rx, #1 @ MMU enabled? | 13 | tst \rx, #1 @ MMU enabled? |
14 | ldreq \rx, =LOKI_REGS_PHYS_BASE | 14 | ldreq \rx, =LOKI_REGS_PHYS_BASE |
diff --git a/arch/arm/mach-loki/include/mach/vmalloc.h b/arch/arm/mach-loki/include/mach/vmalloc.h index 8dc3bfcbf9f0..5dcbd865443f 100644 --- a/arch/arm/mach-loki/include/mach/vmalloc.h +++ b/arch/arm/mach-loki/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-loki/include/mach/vmalloc.h | 2 | * arch/arm/mach-loki/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe800000 | 5 | #define VMALLOC_END 0xfe800000UL |
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S index a850f87de51d..76deff238e1c 100644 --- a/arch/arm/mach-mmp/include/mach/debug-macro.S +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | 11 | ||
12 | #include <mach/addr-map.h> | 12 | #include <mach/addr-map.h> |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | ldreq \rx, =APB_PHYS_BASE @ physical | 17 | ldreq \rx, =APB_PHYS_BASE @ physical |
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h index b60ccaf9fee7..1d0bac003ad0 100644 --- a/arch/arm/mach-mmp/include/mach/vmalloc.h +++ b/arch/arm/mach-mmp/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * linux/arch/arm/mach-mmp/include/mach/vmalloc.h | 2 | * linux/arch/arm/mach-mmp/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe000000 | 5 | #define VMALLOC_END 0xfe000000UL |
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index d48747ebcd3d..528750f307e9 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S | |||
@@ -20,7 +20,7 @@ | |||
20 | #include <mach/msm_iomap.h> | 20 | #include <mach/msm_iomap.h> |
21 | 21 | ||
22 | #ifdef CONFIG_MSM_DEBUG_UART | 22 | #ifdef CONFIG_MSM_DEBUG_UART |
23 | .macro addruart,rx | 23 | .macro addruart, rx, tmp |
24 | @ see if the MMU is enabled and select appropriate base address | 24 | @ see if the MMU is enabled and select appropriate base address |
25 | mrc p15, 0, \rx, c1, c0 | 25 | mrc p15, 0, \rx, c1, c0 |
26 | tst \rx, #1 | 26 | tst \rx, #1 |
@@ -40,7 +40,7 @@ | |||
40 | beq 1001b | 40 | beq 1001b |
41 | .endm | 41 | .endm |
42 | #else | 42 | #else |
43 | .macro addruart,rx | 43 | .macro addruart, rx, tmp |
44 | .endm | 44 | .endm |
45 | 45 | ||
46 | .macro senduart,rd,rx | 46 | .macro senduart,rd,rx |
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 1c5e7dac086f..05f96b780aa6 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c | |||
@@ -76,5 +76,6 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | |||
76 | mtype = MT_DEVICE_NONSHARED; | 76 | mtype = MT_DEVICE_NONSHARED; |
77 | } | 77 | } |
78 | 78 | ||
79 | return __arm_ioremap(phys_addr, size, mtype); | 79 | return __arm_ioremap_caller(phys_addr, size, mtype, |
80 | __builtin_return_address(0)); | ||
80 | } | 81 | } |
diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S index a06442fbd341..cd81689c4621 100644 --- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S +++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | 8 | ||
9 | #include <mach/mv78xx0.h> | 9 | #include <mach/mv78xx0.h> |
10 | 10 | ||
11 | .macro addruart,rx | 11 | .macro addruart, rx, tmp |
12 | mrc p15, 0, \rx, c1, c0 | 12 | mrc p15, 0, \rx, c1, c0 |
13 | tst \rx, #1 @ MMU enabled? | 13 | tst \rx, #1 @ MMU enabled? |
14 | ldreq \rx, =MV78XX0_REGS_PHYS_BASE | 14 | ldreq \rx, =MV78XX0_REGS_PHYS_BASE |
diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h index 1c4954386a84..ba26fe98e640 100644 --- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h +++ b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-mv78xx0/include/mach/vmalloc.h | 2 | * arch/arm/mach-mv78xx0/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfe000000 | 5 | #define VMALLOC_END 0xfe000000UL |
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S index 11b9d5b46390..e96339e71d88 100644 --- a/arch/arm/mach-netx/include/mach/debug-macro.S +++ b/arch/arm/mach-netx/include/mach/debug-macro.S | |||
@@ -13,7 +13,7 @@ | |||
13 | 13 | ||
14 | #include "hardware.h" | 14 | #include "hardware.h" |
15 | 15 | ||
16 | .macro addruart,rx | 16 | .macro addruart, rx, tmp |
17 | mrc p15, 0, \rx, c1, c0 | 17 | mrc p15, 0, \rx, c1, c0 |
18 | tst \rx, #1 @ MMU enabled? | 18 | tst \rx, #1 @ MMU enabled? |
19 | moveq \rx, #0x00100000 @ physical | 19 | moveq \rx, #0x00100000 @ physical |
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S index e876990e1569..4f92acfba954 100644 --- a/arch/arm/mach-nomadik/include/mach/debug-macro.S +++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S | |||
@@ -10,7 +10,7 @@ | |||
10 | * | 10 | * |
11 | */ | 11 | */ |
12 | 12 | ||
13 | .macro addruart,rx | 13 | .macro addruart, rx, tmp |
14 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
15 | tst \rx, #1 @ MMU enabled? | 15 | tst \rx, #1 @ MMU enabled? |
16 | moveq \rx, #0x10000000 @ physical base address | 16 | moveq \rx, #0x10000000 @ physical base address |
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h index be12e31ea528..f83d574d9445 100644 --- a/arch/arm/mach-nomadik/include/mach/vmalloc.h +++ b/arch/arm/mach-nomadik/include/mach/vmalloc.h | |||
@@ -1,2 +1,2 @@ | |||
1 | 1 | ||
2 | #define VMALLOC_END 0xe8000000 | 2 | #define VMALLOC_END 0xe8000000UL |
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S index c9530fba00aa..0859336a8e6d 100644 --- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S +++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | 11 | ||
12 | #include <mach/regs-board-a9m9750dev.h> | 12 | #include <mach/regs-board-a9m9750dev.h> |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 | 16 | tst \rx, #1 |
17 | ldreq \rx, =NS9XXX_CSxSTAT_PHYS(0) | 17 | ldreq \rx, =NS9XXX_CSxSTAT_PHYS(0) |
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h index fe964d3bcc47..c8651974c4b0 100644 --- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h +++ b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h | |||
@@ -11,6 +11,6 @@ | |||
11 | #ifndef __ASM_ARCH_VMALLOC_H | 11 | #ifndef __ASM_ARCH_VMALLOC_H |
12 | #define __ASM_ARCH_VMALLOC_H | 12 | #define __ASM_ARCH_VMALLOC_H |
13 | 13 | ||
14 | #define VMALLOC_END (0xf0000000) | 14 | #define VMALLOC_END (0xf0000000UL) |
15 | 15 | ||
16 | #endif /* ifndef __ASM_ARCH_VMALLOC_H */ | 16 | #endif /* ifndef __ASM_ARCH_VMALLOC_H */ |
diff --git a/arch/arm/mach-nuc93x/Kconfig b/arch/arm/mach-nuc93x/Kconfig new file mode 100644 index 000000000000..2bc40a280fad --- /dev/null +++ b/arch/arm/mach-nuc93x/Kconfig | |||
@@ -0,0 +1,19 @@ | |||
1 | if ARCH_NUC93X | ||
2 | |||
3 | config CPU_NUC932 | ||
4 | bool | ||
5 | help | ||
6 | Support for NUC932 of Nuvoton NUC93X CPUs. | ||
7 | |||
8 | menu "NUC932 Machines" | ||
9 | |||
10 | config MACH_NUC932EVB | ||
11 | bool "Nuvoton NUC932 Evaluation Board" | ||
12 | default y | ||
13 | select CPU_NUC932 | ||
14 | help | ||
15 | Say Y here if you are using the Nuvoton NUC932EVB | ||
16 | |||
17 | endmenu | ||
18 | |||
19 | endif | ||
diff --git a/arch/arm/mach-nuc93x/Makefile b/arch/arm/mach-nuc93x/Makefile new file mode 100644 index 000000000000..440e2dec6c8a --- /dev/null +++ b/arch/arm/mach-nuc93x/Makefile | |||
@@ -0,0 +1,14 @@ | |||
1 | # | ||
2 | # Makefile for the linux kernel. | ||
3 | # | ||
4 | |||
5 | # Object file lists. | ||
6 | |||
7 | obj-y := irq.o time.o dev.o cpu.o clock.o | ||
8 | # NUC932 CPU support files | ||
9 | |||
10 | obj-$(CONFIG_CPU_NUC932) += nuc932.o | ||
11 | |||
12 | # machine support | ||
13 | |||
14 | obj-$(CONFIG_MACH_NUC932EVB) += mach-nuc932evb.o | ||
diff --git a/arch/arm/mach-nuc93x/Makefile.boot b/arch/arm/mach-nuc93x/Makefile.boot new file mode 100644 index 000000000000..a057b546b6e5 --- /dev/null +++ b/arch/arm/mach-nuc93x/Makefile.boot | |||
@@ -0,0 +1,3 @@ | |||
1 | zreladdr-y := 0x00008000 | ||
2 | params_phys-y := 0x00000100 | ||
3 | |||
diff --git a/arch/arm/mach-nuc93x/clock.c b/arch/arm/mach-nuc93x/clock.c new file mode 100644 index 000000000000..0521efbc48c9 --- /dev/null +++ b/arch/arm/mach-nuc93x/clock.c | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/clock.c | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/list.h> | ||
16 | #include <linux/errno.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/string.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/spinlock.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/io.h> | ||
23 | |||
24 | #include <mach/hardware.h> | ||
25 | |||
26 | #include "clock.h" | ||
27 | |||
28 | static DEFINE_SPINLOCK(clocks_lock); | ||
29 | |||
30 | int clk_enable(struct clk *clk) | ||
31 | { | ||
32 | unsigned long flags; | ||
33 | |||
34 | spin_lock_irqsave(&clocks_lock, flags); | ||
35 | if (clk->enabled++ == 0) | ||
36 | (clk->enable)(clk, 1); | ||
37 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | EXPORT_SYMBOL(clk_enable); | ||
42 | |||
43 | void clk_disable(struct clk *clk) | ||
44 | { | ||
45 | unsigned long flags; | ||
46 | |||
47 | WARN_ON(clk->enabled == 0); | ||
48 | |||
49 | spin_lock_irqsave(&clocks_lock, flags); | ||
50 | if (--clk->enabled == 0) | ||
51 | (clk->enable)(clk, 0); | ||
52 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
53 | } | ||
54 | EXPORT_SYMBOL(clk_disable); | ||
55 | |||
56 | unsigned long clk_get_rate(struct clk *clk) | ||
57 | { | ||
58 | return 27000000; | ||
59 | } | ||
60 | EXPORT_SYMBOL(clk_get_rate); | ||
61 | |||
62 | void nuc93x_clk_enable(struct clk *clk, int enable) | ||
63 | { | ||
64 | unsigned int clocks = clk->cken; | ||
65 | unsigned long clken; | ||
66 | |||
67 | clken = __raw_readl(NUC93X_VA_CLKPWR); | ||
68 | |||
69 | if (enable) | ||
70 | clken |= clocks; | ||
71 | else | ||
72 | clken &= ~clocks; | ||
73 | |||
74 | __raw_writel(clken, NUC93X_VA_CLKPWR); | ||
75 | } | ||
76 | |||
77 | void clks_register(struct clk_lookup *clks, size_t num) | ||
78 | { | ||
79 | int i; | ||
80 | |||
81 | for (i = 0; i < num; i++) | ||
82 | clkdev_add(&clks[i]); | ||
83 | } | ||
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h new file mode 100644 index 000000000000..18e51be4816f --- /dev/null +++ b/arch/arm/mach-nuc93x/clock.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/clock.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License. | ||
11 | */ | ||
12 | |||
13 | #include <asm/clkdev.h> | ||
14 | |||
15 | void nuc93x_clk_enable(struct clk *clk, int enable); | ||
16 | void clks_register(struct clk_lookup *clks, size_t num); | ||
17 | |||
18 | struct clk { | ||
19 | unsigned long cken; | ||
20 | unsigned int enabled; | ||
21 | void (*enable)(struct clk *, int enable); | ||
22 | }; | ||
23 | |||
24 | #define DEFINE_CLK(_name, _ctrlbit) \ | ||
25 | struct clk clk_##_name = { \ | ||
26 | .enable = nuc93x_clk_enable, \ | ||
27 | .cken = (1 << _ctrlbit), \ | ||
28 | } | ||
29 | |||
30 | #define DEF_CLKLOOK(_clk, _devname, _conname) \ | ||
31 | { \ | ||
32 | .clk = _clk, \ | ||
33 | .dev_id = _devname, \ | ||
34 | .con_id = _conname, \ | ||
35 | } | ||
36 | |||
diff --git a/arch/arm/mach-nuc93x/cpu.c b/arch/arm/mach-nuc93x/cpu.c new file mode 100644 index 000000000000..f6ff5d87354c --- /dev/null +++ b/arch/arm/mach-nuc93x/cpu.c | |||
@@ -0,0 +1,135 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/cpu.c | ||
3 | * | ||
4 | * Copyright (c) 2009 Nuvoton corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * NUC93x series cpu common support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation;version 2 of the License. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/types.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/list.h> | ||
20 | #include <linux/timer.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/platform_device.h> | ||
23 | #include <linux/io.h> | ||
24 | #include <linux/serial_8250.h> | ||
25 | #include <linux/delay.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach/map.h> | ||
29 | #include <asm/mach/irq.h> | ||
30 | #include <asm/irq.h> | ||
31 | |||
32 | #include <mach/hardware.h> | ||
33 | #include <mach/regs-serial.h> | ||
34 | #include <mach/regs-clock.h> | ||
35 | #include <mach/regs-ebi.h> | ||
36 | |||
37 | #include "cpu.h" | ||
38 | #include "clock.h" | ||
39 | |||
40 | /* Initial IO mappings */ | ||
41 | |||
42 | static struct map_desc nuc93x_iodesc[] __initdata = { | ||
43 | IODESC_ENT(IRQ), | ||
44 | IODESC_ENT(GCR), | ||
45 | IODESC_ENT(UART), | ||
46 | IODESC_ENT(TIMER), | ||
47 | IODESC_ENT(EBI), | ||
48 | }; | ||
49 | |||
50 | /* Initial nuc932 clock declarations. */ | ||
51 | static DEFINE_CLK(audio, 2); | ||
52 | static DEFINE_CLK(sd, 3); | ||
53 | static DEFINE_CLK(jpg, 4); | ||
54 | static DEFINE_CLK(video, 5); | ||
55 | static DEFINE_CLK(vpost, 6); | ||
56 | static DEFINE_CLK(2d, 7); | ||
57 | static DEFINE_CLK(gpu, 8); | ||
58 | static DEFINE_CLK(gdma, 9); | ||
59 | static DEFINE_CLK(adc, 10); | ||
60 | static DEFINE_CLK(uart, 11); | ||
61 | static DEFINE_CLK(spi, 12); | ||
62 | static DEFINE_CLK(pwm, 13); | ||
63 | static DEFINE_CLK(timer, 14); | ||
64 | static DEFINE_CLK(wdt, 15); | ||
65 | static DEFINE_CLK(ac97, 16); | ||
66 | static DEFINE_CLK(i2s, 16); | ||
67 | static DEFINE_CLK(usbck, 17); | ||
68 | static DEFINE_CLK(usb48, 18); | ||
69 | static DEFINE_CLK(usbh, 19); | ||
70 | static DEFINE_CLK(i2c, 20); | ||
71 | static DEFINE_CLK(ext, 0); | ||
72 | |||
73 | static struct clk_lookup nuc932_clkregs[] = { | ||
74 | DEF_CLKLOOK(&clk_audio, "nuc932-audio", NULL), | ||
75 | DEF_CLKLOOK(&clk_sd, "nuc932-sd", NULL), | ||
76 | DEF_CLKLOOK(&clk_jpg, "nuc932-jpg", "NULL"), | ||
77 | DEF_CLKLOOK(&clk_video, "nuc932-video", "NULL"), | ||
78 | DEF_CLKLOOK(&clk_vpost, "nuc932-vpost", NULL), | ||
79 | DEF_CLKLOOK(&clk_2d, "nuc932-2d", NULL), | ||
80 | DEF_CLKLOOK(&clk_gpu, "nuc932-gpu", NULL), | ||
81 | DEF_CLKLOOK(&clk_gdma, "nuc932-gdma", "NULL"), | ||
82 | DEF_CLKLOOK(&clk_adc, "nuc932-adc", NULL), | ||
83 | DEF_CLKLOOK(&clk_uart, NULL, "uart"), | ||
84 | DEF_CLKLOOK(&clk_spi, "nuc932-spi", NULL), | ||
85 | DEF_CLKLOOK(&clk_pwm, "nuc932-pwm", NULL), | ||
86 | DEF_CLKLOOK(&clk_timer, NULL, "timer"), | ||
87 | DEF_CLKLOOK(&clk_wdt, "nuc932-wdt", NULL), | ||
88 | DEF_CLKLOOK(&clk_ac97, "nuc932-ac97", NULL), | ||
89 | DEF_CLKLOOK(&clk_i2s, "nuc932-i2s", NULL), | ||
90 | DEF_CLKLOOK(&clk_usbck, "nuc932-usbck", NULL), | ||
91 | DEF_CLKLOOK(&clk_usb48, "nuc932-usb48", NULL), | ||
92 | DEF_CLKLOOK(&clk_usbh, "nuc932-usbh", NULL), | ||
93 | DEF_CLKLOOK(&clk_i2c, "nuc932-i2c", NULL), | ||
94 | DEF_CLKLOOK(&clk_ext, NULL, "ext"), | ||
95 | }; | ||
96 | |||
97 | /* Initial serial platform data */ | ||
98 | |||
99 | struct plat_serial8250_port nuc93x_uart_data[] = { | ||
100 | NUC93X_8250PORT(UART0), | ||
101 | {}, | ||
102 | }; | ||
103 | |||
104 | struct platform_device nuc93x_serial_device = { | ||
105 | .name = "serial8250", | ||
106 | .id = PLAT8250_DEV_PLATFORM, | ||
107 | .dev = { | ||
108 | .platform_data = nuc93x_uart_data, | ||
109 | }, | ||
110 | }; | ||
111 | |||
112 | /*Init NUC93x evb io*/ | ||
113 | |||
114 | void __init nuc93x_map_io(struct map_desc *mach_desc, int mach_size) | ||
115 | { | ||
116 | unsigned long idcode = 0x0; | ||
117 | |||
118 | iotable_init(mach_desc, mach_size); | ||
119 | iotable_init(nuc93x_iodesc, ARRAY_SIZE(nuc93x_iodesc)); | ||
120 | |||
121 | idcode = __raw_readl(NUC93XPDID); | ||
122 | if (idcode == NUC932_CPUID) | ||
123 | printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode); | ||
124 | else | ||
125 | printk(KERN_ERR "CPU type detect error!\n"); | ||
126 | |||
127 | } | ||
128 | |||
129 | /*Init NUC93x clock*/ | ||
130 | |||
131 | void __init nuc93x_init_clocks(void) | ||
132 | { | ||
133 | clks_register(nuc932_clkregs, ARRAY_SIZE(nuc932_clkregs)); | ||
134 | } | ||
135 | |||
diff --git a/arch/arm/mach-nuc93x/cpu.h b/arch/arm/mach-nuc93x/cpu.h new file mode 100644 index 000000000000..9def28197bc9 --- /dev/null +++ b/arch/arm/mach-nuc93x/cpu.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/cpu.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Header file for NUC93X CPU support | ||
8 | * | ||
9 | * Wan ZongShun <mcuos.com@gmail.com> | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | * | ||
15 | */ | ||
16 | |||
17 | #define IODESC_ENT(y) \ | ||
18 | { \ | ||
19 | .virtual = (unsigned long)NUC93X_VA_##y, \ | ||
20 | .pfn = __phys_to_pfn(NUC93X_PA_##y), \ | ||
21 | .length = NUC93X_SZ_##y, \ | ||
22 | .type = MT_DEVICE, \ | ||
23 | } | ||
24 | |||
25 | #define NUC93X_8250PORT(name) \ | ||
26 | { \ | ||
27 | .membase = name##_BA, \ | ||
28 | .mapbase = name##_PA, \ | ||
29 | .irq = IRQ_##name, \ | ||
30 | .uartclk = 57139200, \ | ||
31 | .regshift = 2, \ | ||
32 | .iotype = UPIO_MEM, \ | ||
33 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ | ||
34 | } | ||
35 | |||
36 | /*Cpu identifier register*/ | ||
37 | |||
38 | #define NUC93XPDID NUC93X_VA_GCR | ||
39 | #define NUC932_CPUID 0x29550091 | ||
40 | |||
41 | /* extern file from cpu.c */ | ||
42 | |||
43 | extern void nuc93x_clock_source(struct device *dev, unsigned char *src); | ||
44 | extern void nuc93x_init_clocks(void); | ||
45 | extern void nuc93x_map_io(struct map_desc *mach_desc, int mach_size); | ||
46 | extern void nuc93x_board_init(struct platform_device **device, int size); | ||
47 | extern struct platform_device nuc93x_serial_device; | ||
48 | |||
diff --git a/arch/arm/mach-nuc93x/dev.c b/arch/arm/mach-nuc93x/dev.c new file mode 100644 index 000000000000..a962ae9578d6 --- /dev/null +++ b/arch/arm/mach-nuc93x/dev.c | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/dev.c | ||
3 | * | ||
4 | * Copyright (C) 2009 Nuvoton corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License as | ||
10 | * published by the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/types.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/list.h> | ||
18 | #include <linux/timer.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | |||
22 | #include <asm/mach/arch.h> | ||
23 | #include <asm/mach/map.h> | ||
24 | #include <asm/mach/irq.h> | ||
25 | #include <asm/mach-types.h> | ||
26 | |||
27 | #include "cpu.h" | ||
28 | |||
29 | /*Here should be your evb resourse,such as LCD*/ | ||
30 | |||
31 | static struct platform_device *nuc93x_public_dev[] __initdata = { | ||
32 | &nuc93x_serial_device, | ||
33 | }; | ||
34 | |||
35 | /* Provide adding specific CPU platform devices API */ | ||
36 | |||
37 | void __init nuc93x_board_init(struct platform_device **device, int size) | ||
38 | { | ||
39 | platform_add_devices(device, size); | ||
40 | platform_add_devices(nuc93x_public_dev, ARRAY_SIZE(nuc93x_public_dev)); | ||
41 | } | ||
42 | |||
diff --git a/arch/arm/mach-nuc93x/include/mach/clkdev.h b/arch/arm/mach-nuc93x/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __ASM_MACH_CLKDEV_H | ||
2 | #define __ASM_MACH_CLKDEV_H | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do { } while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/entry-macro.S b/arch/arm/mach-nuc93x/include/mach/entry-macro.S new file mode 100644 index 000000000000..1352cbda3797 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/entry-macro.S | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/entry-macro.S | ||
3 | * | ||
4 | * This file is licensed under the terms of the GNU General Public | ||
5 | * License version 2. This program is licensed "as is" without any | ||
6 | * warranty of any kind, whether express or implied. | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #include <mach/hardware.h> | ||
11 | #include <mach/regs-irq.h> | ||
12 | |||
13 | .macro get_irqnr_preamble, base, tmp | ||
14 | .endm | ||
15 | |||
16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
17 | .endm | ||
18 | |||
19 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
20 | |||
21 | mov \base, #AIC_BA | ||
22 | |||
23 | ldr \irqnr, [ \base, #AIC_IPER] | ||
24 | ldr \irqnr, [ \base, #AIC_ISNR] | ||
25 | cmp \irqnr, #0 | ||
26 | |||
27 | .endm | ||
28 | |||
29 | /* currently don't need an disable_fiq macro */ | ||
30 | |||
31 | .macro disable_fiq | ||
32 | .endm | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/hardware.h b/arch/arm/mach-nuc93x/include/mach/hardware.h new file mode 100644 index 000000000000..fb5c6fcb142e --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/hardware.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/hardware.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_HARDWARE_H | ||
17 | #define __ASM_ARCH_HARDWARE_H | ||
18 | |||
19 | #include <asm/sizes.h> | ||
20 | #include <mach/map.h> | ||
21 | |||
22 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h new file mode 100644 index 000000000000..72e5051c7534 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/io.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/io.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARM_ARCH_IO_H | ||
17 | #define __ASM_ARM_ARCH_IO_H | ||
18 | |||
19 | #define IO_SPACE_LIMIT 0xffffffff | ||
20 | |||
21 | /* | ||
22 | * 1:1 mapping for ioremapped regions. | ||
23 | */ | ||
24 | |||
25 | #define __mem_pci(a) (a) | ||
26 | #define __io(a) __typesafe_io(a) | ||
27 | |||
28 | #endif | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/irqs.h b/arch/arm/mach-nuc93x/include/mach/irqs.h new file mode 100644 index 000000000000..7c4aa71edb44 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/irqs.h | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_IRQS_H | ||
15 | #define __ASM_ARCH_IRQS_H | ||
16 | |||
17 | #define NUC93X_IRQ(x) (x) | ||
18 | |||
19 | /* Main cpu interrupts */ | ||
20 | |||
21 | #define IRQ_WDT NUC93X_IRQ(1) | ||
22 | #define IRQ_IRQ0 NUC93X_IRQ(2) | ||
23 | #define IRQ_IRQ1 NUC93X_IRQ(3) | ||
24 | #define IRQ_IRQ2 NUC93X_IRQ(4) | ||
25 | #define IRQ_IRQ3 NUC93X_IRQ(5) | ||
26 | #define IRQ_USBH NUC93X_IRQ(6) | ||
27 | #define IRQ_APU NUC93X_IRQ(7) | ||
28 | #define IRQ_VPOST NUC93X_IRQ(8) | ||
29 | #define IRQ_ADC NUC93X_IRQ(9) | ||
30 | #define IRQ_UART0 NUC93X_IRQ(10) | ||
31 | #define IRQ_TIMER0 NUC93X_IRQ(11) | ||
32 | #define IRQ_GPU0 NUC93X_IRQ(12) | ||
33 | #define IRQ_GPU1 NUC93X_IRQ(13) | ||
34 | #define IRQ_GPU2 NUC93X_IRQ(14) | ||
35 | #define IRQ_GPU3 NUC93X_IRQ(15) | ||
36 | #define IRQ_GPU4 NUC93X_IRQ(16) | ||
37 | #define IRQ_VIN NUC93X_IRQ(17) | ||
38 | #define IRQ_USBD NUC93X_IRQ(18) | ||
39 | #define IRQ_VRAMLD NUC93X_IRQ(19) | ||
40 | #define IRQ_GDMA0 NUC93X_IRQ(20) | ||
41 | #define IRQ_GDMA1 NUC93X_IRQ(21) | ||
42 | #define IRQ_SDIO NUC93X_IRQ(22) | ||
43 | #define IRQ_FMI NUC93X_IRQ(22) | ||
44 | #define IRQ_JPEG NUC93X_IRQ(23) | ||
45 | #define IRQ_SPI0 NUC93X_IRQ(24) | ||
46 | #define IRQ_SPI1 NUC93X_IRQ(25) | ||
47 | #define IRQ_RTC NUC93X_IRQ(26) | ||
48 | #define IRQ_PWM0 NUC93X_IRQ(27) | ||
49 | #define IRQ_PWM1 NUC93X_IRQ(28) | ||
50 | #define IRQ_PWM2 NUC93X_IRQ(29) | ||
51 | #define IRQ_PWM3 NUC93X_IRQ(30) | ||
52 | #define IRQ_I2SAC97 NUC93X_IRQ(31) | ||
53 | #define IRQ_CAP0 IRQ_PWM0 | ||
54 | #define IRQ_CAP1 IRQ_PWM1 | ||
55 | #define IRQ_CAP2 IRQ_PWM2 | ||
56 | #define IRQ_CAP3 IRQ_PWM3 | ||
57 | #define NR_IRQS (IRQ_I2SAC97 + 1) | ||
58 | |||
59 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/map.h b/arch/arm/mach-nuc93x/include/mach/map.h new file mode 100644 index 000000000000..fd0b5e89f0e7 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/map.h | |||
@@ -0,0 +1,139 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/map.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_MAP_H | ||
15 | #define __ASM_ARCH_MAP_H | ||
16 | |||
17 | #define MAP_OFFSET (0xfff00000) | ||
18 | #define CLK_OFFSET (0x10) | ||
19 | |||
20 | #ifndef __ASSEMBLY__ | ||
21 | #define NUC93X_ADDR(x) ((void __iomem *)(0xF0000000 + ((x)&(~MAP_OFFSET)))) | ||
22 | #else | ||
23 | #define NUC93X_ADDR(x) (0xF0000000 + ((x)&(~MAP_OFFSET))) | ||
24 | #endif | ||
25 | |||
26 | /* | ||
27 | * nuc932 hardware register definition | ||
28 | */ | ||
29 | |||
30 | #define NUC93X_PA_IRQ (0xFFF83000) | ||
31 | #define NUC93X_PA_GCR (0xFFF00000) | ||
32 | #define NUC93X_PA_EBI (0xFFF01000) | ||
33 | #define NUC93X_PA_UART (0xFFF80000) | ||
34 | #define NUC93X_PA_TIMER (0xFFF81000) | ||
35 | #define NUC93X_PA_GPIO (0xFFF84000) | ||
36 | #define NUC93X_PA_GDMA (0xFFF03000) | ||
37 | #define NUC93X_PA_USBHOST (0xFFF0d000) | ||
38 | #define NUC93X_PA_I2C (0xFFF89000) | ||
39 | #define NUC93X_PA_LCD (0xFFF06000) | ||
40 | #define NUC93X_PA_GE (0xFFF05000) | ||
41 | #define NUC93X_PA_ADC (0xFFF85000) | ||
42 | #define NUC93X_PA_RTC (0xFFF87000) | ||
43 | #define NUC93X_PA_PWM (0xFFF82000) | ||
44 | #define NUC93X_PA_ACTL (0xFFF0a000) | ||
45 | #define NUC93X_PA_USBDEV (0xFFF0C000) | ||
46 | #define NUC93X_PA_JEPEG (0xFFF0e000) | ||
47 | #define NUC93X_PA_CACHE_T (0xFFF60000) | ||
48 | #define NUC93X_PA_VRAM (0xFFF0b000) | ||
49 | #define NUC93X_PA_DMAC (0xFFF09000) | ||
50 | #define NUC93X_PA_I2SM (0xFFF08000) | ||
51 | #define NUC93X_PA_CACHE (0xFFF02000) | ||
52 | #define NUC93X_PA_GPU (0xFFF04000) | ||
53 | #define NUC93X_PA_VIDEOIN (0xFFF07000) | ||
54 | #define NUC93X_PA_SPI0 (0xFFF86000) | ||
55 | #define NUC93X_PA_SPI1 (0xFFF88000) | ||
56 | |||
57 | /* | ||
58 | * nuc932 virtual address mapping. | ||
59 | * interrupt controller is the first thing we put in, to make | ||
60 | * the assembly code for the irq detection easier | ||
61 | */ | ||
62 | |||
63 | #define NUC93X_VA_IRQ NUC93X_ADDR(0x00000000) | ||
64 | #define NUC93X_SZ_IRQ SZ_4K | ||
65 | |||
66 | #define NUC93X_VA_GCR NUC93X_ADDR(NUC93X_PA_IRQ) | ||
67 | #define NUC93X_VA_CLKPWR (NUC93X_VA_GCR+CLK_OFFSET) | ||
68 | #define NUC93X_SZ_GCR SZ_4K | ||
69 | |||
70 | /* EBI management */ | ||
71 | |||
72 | #define NUC93X_VA_EBI NUC93X_ADDR(NUC93X_PA_EBI) | ||
73 | #define NUC93X_SZ_EBI SZ_4K | ||
74 | |||
75 | /* UARTs */ | ||
76 | |||
77 | #define NUC93X_VA_UART NUC93X_ADDR(NUC93X_PA_UART) | ||
78 | #define NUC93X_SZ_UART SZ_4K | ||
79 | |||
80 | /* Timers */ | ||
81 | |||
82 | #define NUC93X_VA_TIMER NUC93X_ADDR(NUC93X_PA_TIMER) | ||
83 | #define NUC93X_SZ_TIMER SZ_4K | ||
84 | |||
85 | /* GPIO ports */ | ||
86 | |||
87 | #define NUC93X_VA_GPIO NUC93X_ADDR(NUC93X_PA_GPIO) | ||
88 | #define NUC93X_SZ_GPIO SZ_4K | ||
89 | |||
90 | /* GDMA control */ | ||
91 | |||
92 | #define NUC93X_VA_GDMA NUC93X_ADDR(NUC93X_PA_GDMA) | ||
93 | #define NUC93X_SZ_GDMA SZ_4K | ||
94 | |||
95 | /* I2C hardware controller */ | ||
96 | |||
97 | #define NUC93X_VA_I2C NUC93X_ADDR(NUC93X_PA_I2C) | ||
98 | #define NUC93X_SZ_I2C SZ_4K | ||
99 | |||
100 | /* LCD controller*/ | ||
101 | |||
102 | #define NUC93X_VA_LCD NUC93X_ADDR(NUC93X_PA_LCD) | ||
103 | #define NUC93X_SZ_LCD SZ_4K | ||
104 | |||
105 | /* 2D controller*/ | ||
106 | |||
107 | #define NUC93X_VA_GE NUC93X_ADDR(NUC93X_PA_GE) | ||
108 | #define NUC93X_SZ_GE SZ_4K | ||
109 | |||
110 | /* ADC */ | ||
111 | |||
112 | #define NUC93X_VA_ADC NUC93X_ADDR(NUC93X_PA_ADC) | ||
113 | #define NUC93X_SZ_ADC SZ_4K | ||
114 | |||
115 | /* RTC */ | ||
116 | |||
117 | #define NUC93X_VA_RTC NUC93X_ADDR(NUC93X_PA_RTC) | ||
118 | #define NUC93X_SZ_RTC SZ_4K | ||
119 | |||
120 | /* Pulse Width Modulation(PWM) Registers */ | ||
121 | |||
122 | #define NUC93X_VA_PWM NUC93X_ADDR(NUC93X_PA_PWM) | ||
123 | #define NUC93X_SZ_PWM SZ_4K | ||
124 | |||
125 | /* Audio Controller controller */ | ||
126 | |||
127 | #define NUC93X_VA_ACTL NUC93X_ADDR(NUC93X_PA_ACTL) | ||
128 | #define NUC93X_SZ_ACTL SZ_4K | ||
129 | |||
130 | /* USB Device port */ | ||
131 | |||
132 | #define NUC93X_VA_USBDEV NUC93X_ADDR(NUC93X_PA_USBDEV) | ||
133 | #define NUC93X_SZ_USBDEV SZ_4K | ||
134 | |||
135 | /* USB host controller*/ | ||
136 | #define NUC93X_VA_USBHOST NUC93X_ADDR(NUC93X_PA_USBHOST) | ||
137 | #define NUC93X_SZ_USBHOST SZ_4K | ||
138 | |||
139 | #endif /* __ASM_ARCH_MAP_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h new file mode 100644 index 000000000000..323ab0db3f7d --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/memory.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/memory.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_MEMORY_H | ||
17 | #define __ASM_ARCH_MEMORY_H | ||
18 | |||
19 | #define PHYS_OFFSET UL(0x00000000) | ||
20 | |||
21 | #endif | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-clock.h b/arch/arm/mach-nuc93x/include/mach/regs-clock.h new file mode 100644 index 000000000000..5cb2954fbec2 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/regs-clock.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/regs-clock.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
15 | #define __ASM_ARCH_REGS_CLOCK_H | ||
16 | |||
17 | /* Clock Control Registers */ | ||
18 | #define CLK_BA NUC93X_VA_CLKPWR | ||
19 | #define REG_CLKEN (CLK_BA + 0x00) | ||
20 | #define REG_CLKSEL (CLK_BA + 0x04) | ||
21 | #define REG_CLKDIV (CLK_BA + 0x08) | ||
22 | #define REG_PLLCON0 (CLK_BA + 0x0C) | ||
23 | #define REG_PLLCON1 (CLK_BA + 0x10) | ||
24 | #define REG_PMCON (CLK_BA + 0x14) | ||
25 | #define REG_IRQWAKECON (CLK_BA + 0x18) | ||
26 | #define REG_IRQWAKEFLAG (CLK_BA + 0x1C) | ||
27 | #define REG_IPSRST (CLK_BA + 0x20) | ||
28 | #define REG_CLKEN1 (CLK_BA + 0x24) | ||
29 | #define REG_CLKDIV1 (CLK_BA + 0x28) | ||
30 | |||
31 | /* Define PLL freq setting */ | ||
32 | #define PLL_DISABLE 0x12B63 | ||
33 | #define PLL_66MHZ 0x2B63 | ||
34 | #define PLL_100MHZ 0x4F64 | ||
35 | #define PLL_120MHZ 0x4F63 | ||
36 | #define PLL_166MHZ 0x4124 | ||
37 | #define PLL_200MHZ 0x4F24 | ||
38 | |||
39 | /* Define AHB:CPUFREQ ratio */ | ||
40 | #define AHB_CPUCLK_1_1 0x00 | ||
41 | #define AHB_CPUCLK_1_2 0x01 | ||
42 | #define AHB_CPUCLK_1_4 0x02 | ||
43 | #define AHB_CPUCLK_1_8 0x03 | ||
44 | |||
45 | /* Define APB:AHB ratio */ | ||
46 | #define APB_AHB_1_2 0x01 | ||
47 | #define APB_AHB_1_4 0x02 | ||
48 | #define APB_AHB_1_8 0x03 | ||
49 | |||
50 | /* Define clock skew */ | ||
51 | #define DEFAULTSKEW 0x48 | ||
52 | |||
53 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h new file mode 100644 index 000000000000..3c72550e28e4 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/regs-ebi.h | ||
3 | * | ||
4 | * Copyright (c) 2009 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_EBI_H | ||
15 | #define __ASM_ARCH_REGS_EBI_H | ||
16 | |||
17 | /* EBI Control Registers */ | ||
18 | |||
19 | #define EBI_BA NUC93X_VA_EBI | ||
20 | #define REG_EBICON (EBI_BA + 0x00) | ||
21 | #define REG_ROMCON (EBI_BA + 0x04) | ||
22 | #define REG_SDCONF0 (EBI_BA + 0x08) | ||
23 | #define REG_SDCONF1 (EBI_BA + 0x0C) | ||
24 | #define REG_SDTIME0 (EBI_BA + 0x10) | ||
25 | #define REG_SDTIME1 (EBI_BA + 0x14) | ||
26 | #define REG_EXT0CON (EBI_BA + 0x18) | ||
27 | #define REG_EXT1CON (EBI_BA + 0x1C) | ||
28 | #define REG_EXT2CON (EBI_BA + 0x20) | ||
29 | #define REG_EXT3CON (EBI_BA + 0x24) | ||
30 | #define REG_EXT4CON (EBI_BA + 0x28) | ||
31 | #define REG_CKSKEW (EBI_BA + 0x2C) | ||
32 | |||
33 | #endif /* __ASM_ARCH_REGS_EBI_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h new file mode 100644 index 000000000000..23021592de51 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/regs-irq.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/regs-irq.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef ___ASM_ARCH_REGS_IRQ_H | ||
17 | #define ___ASM_ARCH_REGS_IRQ_H | ||
18 | |||
19 | /* Advance Interrupt Controller (AIC) Registers */ | ||
20 | |||
21 | #define AIC_BA NUC93X_VA_IRQ | ||
22 | |||
23 | #define REG_AIC_IRQSC (AIC_BA+0x80) | ||
24 | #define REG_AIC_GEN (AIC_BA+0x84) | ||
25 | #define REG_AIC_GASR (AIC_BA+0x88) | ||
26 | #define REG_AIC_GSCR (AIC_BA+0x8C) | ||
27 | #define REG_AIC_IRSR (AIC_BA+0x100) | ||
28 | #define REG_AIC_IASR (AIC_BA+0x104) | ||
29 | #define REG_AIC_ISR (AIC_BA+0x108) | ||
30 | #define REG_AIC_IPER (AIC_BA+0x10C) | ||
31 | #define REG_AIC_ISNR (AIC_BA+0x110) | ||
32 | #define REG_AIC_IMR (AIC_BA+0x114) | ||
33 | #define REG_AIC_OISR (AIC_BA+0x118) | ||
34 | #define REG_AIC_MECR (AIC_BA+0x120) | ||
35 | #define REG_AIC_MDCR (AIC_BA+0x124) | ||
36 | #define REG_AIC_SSCR (AIC_BA+0x128) | ||
37 | #define REG_AIC_SCCR (AIC_BA+0x12C) | ||
38 | #define REG_AIC_EOSCR (AIC_BA+0x130) | ||
39 | #define AIC_IPER (0x10C) | ||
40 | #define AIC_ISNR (0x110) | ||
41 | |||
42 | #endif /* ___ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-serial.h b/arch/arm/mach-nuc93x/include/mach/regs-serial.h new file mode 100644 index 000000000000..767a047a8bc2 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/regs-serial.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/regs-serial.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARM_REGS_SERIAL_H | ||
17 | #define __ASM_ARM_REGS_SERIAL_H | ||
18 | |||
19 | #define UART0_BA NUC93X_VA_UART | ||
20 | #define UART1_BA (NUC93X_VA_UART+0x100) | ||
21 | |||
22 | #define UART0_PA NUC93X_PA_UART | ||
23 | #define UART1_PA (NUC93X_PA_UART+0x100) | ||
24 | |||
25 | |||
26 | #ifndef __ASSEMBLY__ | ||
27 | |||
28 | struct nuc93x_uart_clksrc { | ||
29 | const char *name; | ||
30 | unsigned int divisor; | ||
31 | unsigned int min_baud; | ||
32 | unsigned int max_baud; | ||
33 | }; | ||
34 | |||
35 | struct nuc93x_uartcfg { | ||
36 | unsigned char hwport; | ||
37 | unsigned char unused; | ||
38 | unsigned short flags; | ||
39 | unsigned long uart_flags; | ||
40 | |||
41 | unsigned long ucon; | ||
42 | unsigned long ulcon; | ||
43 | unsigned long ufcon; | ||
44 | |||
45 | struct nuc93x_uart_clksrc *clocks; | ||
46 | unsigned int clocks_size; | ||
47 | }; | ||
48 | |||
49 | #endif /* __ASSEMBLY__ */ | ||
50 | |||
51 | #endif /* __ASM_ARM_REGS_SERIAL_H */ | ||
52 | |||
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-timer.h b/arch/arm/mach-nuc93x/include/mach/regs-timer.h new file mode 100644 index 000000000000..394be9614d36 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/regs-timer.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/regs-timer.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_REGS_TIMER_H | ||
17 | #define __ASM_ARCH_REGS_TIMER_H | ||
18 | |||
19 | /* Timer Registers */ | ||
20 | |||
21 | #define TMR_BA NUC93X_VA_TIMER | ||
22 | #define REG_TCSR0 (TMR_BA+0x00) | ||
23 | #define REG_TICR0 (TMR_BA+0x08) | ||
24 | #define REG_TDR0 (TMR_BA+0x10) | ||
25 | #define REG_TISR (TMR_BA+0x18) | ||
26 | #define REG_WTCR (TMR_BA+0x1C) | ||
27 | |||
28 | #endif /* __ASM_ARCH_REGS_TIMER_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/system.h b/arch/arm/mach-nuc93x/include/mach/system.h new file mode 100644 index 000000000000..d26bd9a52844 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/system.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * arch/arm/machnuc93x/include/mach/system.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * Based on arch/arm/mach-s3c2410/include/mach/system.h | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #include <asm/proc-fns.h> | ||
19 | |||
20 | static void arch_idle(void) | ||
21 | { | ||
22 | } | ||
23 | |||
24 | static void arch_reset(char mode, const char *cmd) | ||
25 | { | ||
26 | cpu_reset(0); | ||
27 | } | ||
28 | |||
diff --git a/arch/arm/mach-nuc93x/include/mach/timex.h b/arch/arm/mach-nuc93x/include/mach/timex.h new file mode 100644 index 000000000000..0c719cc91aa9 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/timex.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/timex.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * Based on arch/arm/mach-s3c2410/include/mach/timex.h | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_TIMEX_H | ||
19 | #define __ASM_ARCH_TIMEX_H | ||
20 | |||
21 | /* CLOCK_TICK_RATE Now, I don't use it. */ | ||
22 | |||
23 | #define CLOCK_TICK_RATE 27000000 | ||
24 | |||
25 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h new file mode 100644 index 000000000000..73082cd61e84 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/uncompress.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
19 | #define __ASM_ARCH_UNCOMPRESS_H | ||
20 | |||
21 | /* Defines for UART registers */ | ||
22 | |||
23 | #include <mach/regs-serial.h> | ||
24 | #include <mach/map.h> | ||
25 | #include <linux/serial_reg.h> | ||
26 | |||
27 | #define arch_decomp_wdog() | ||
28 | |||
29 | #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) | ||
30 | static u32 * uart_base = (u32 *)UART0_PA; | ||
31 | |||
32 | static void putc(int ch) | ||
33 | { | ||
34 | /* Check THRE and TEMT bits before we transmit the character. | ||
35 | */ | ||
36 | while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) | ||
37 | barrier(); | ||
38 | |||
39 | *uart_base = ch; | ||
40 | } | ||
41 | |||
42 | static inline void flush(void) | ||
43 | { | ||
44 | } | ||
45 | |||
46 | static void arch_decomp_setup(void) | ||
47 | { | ||
48 | } | ||
49 | |||
50 | #endif/* __ASM_NUC93X_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h new file mode 100644 index 000000000000..98a21b81dec0 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/vmalloc.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/include/mach/vmalloc.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Wan ZongShun <mcuos.com@gmail.com> | ||
8 | * | ||
9 | * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_VMALLOC_H | ||
19 | #define __ASM_ARCH_VMALLOC_H | ||
20 | |||
21 | #define VMALLOC_END (0xE0000000) | ||
22 | |||
23 | #endif /* __ASM_ARCH_VMALLOC_H */ | ||
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c new file mode 100644 index 000000000000..a7a88ea4ec31 --- /dev/null +++ b/arch/arm/mach-nuc93x/irq.c | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/irq.c | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation;version 2 of the License. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/ptrace.h> | ||
19 | #include <linux/sysdev.h> | ||
20 | #include <linux/io.h> | ||
21 | |||
22 | #include <asm/irq.h> | ||
23 | #include <asm/mach/irq.h> | ||
24 | |||
25 | #include <mach/hardware.h> | ||
26 | #include <mach/regs-irq.h> | ||
27 | |||
28 | static void nuc93x_irq_mask(unsigned int irq) | ||
29 | { | ||
30 | __raw_writel(1 << irq, REG_AIC_MDCR); | ||
31 | } | ||
32 | |||
33 | /* | ||
34 | * By the w90p910 spec,any irq,only write 1 | ||
35 | * to REG_AIC_EOSCR for ACK | ||
36 | */ | ||
37 | |||
38 | static void nuc93x_irq_ack(unsigned int irq) | ||
39 | { | ||
40 | __raw_writel(0x01, REG_AIC_EOSCR); | ||
41 | } | ||
42 | |||
43 | static void nuc93x_irq_unmask(unsigned int irq) | ||
44 | { | ||
45 | __raw_writel(1 << irq, REG_AIC_MECR); | ||
46 | |||
47 | } | ||
48 | |||
49 | static struct irq_chip nuc93x_irq_chip = { | ||
50 | .ack = nuc93x_irq_ack, | ||
51 | .mask = nuc93x_irq_mask, | ||
52 | .unmask = nuc93x_irq_unmask, | ||
53 | }; | ||
54 | |||
55 | void __init nuc93x_init_irq(void) | ||
56 | { | ||
57 | int irqno; | ||
58 | |||
59 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); | ||
60 | |||
61 | for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { | ||
62 | set_irq_chip(irqno, &nuc93x_irq_chip); | ||
63 | set_irq_handler(irqno, handle_level_irq); | ||
64 | set_irq_flags(irqno, IRQF_VALID); | ||
65 | } | ||
66 | } | ||
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c new file mode 100644 index 000000000000..9f79266f08e2 --- /dev/null +++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-w90x900/mach-nuc910evb.c | ||
3 | * | ||
4 | * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche | ||
5 | * | ||
6 | * Copyright (C) 2008 Nuvoton technology corporation. | ||
7 | * | ||
8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or | ||
11 | * modify it under the terms of the GNU General Public License as | ||
12 | * published by the Free Software Foundation;version 2 of the License. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | #include <asm/mach/arch.h> | ||
18 | #include <asm/mach/map.h> | ||
19 | #include <asm/mach-types.h> | ||
20 | #include <mach/map.h> | ||
21 | |||
22 | #include "nuc932.h" | ||
23 | |||
24 | static void __init nuc932evb_map_io(void) | ||
25 | { | ||
26 | nuc932_map_io(); | ||
27 | nuc932_init_clocks(); | ||
28 | nuc932_init_uartclk(); | ||
29 | } | ||
30 | |||
31 | static void __init nuc932evb_init(void) | ||
32 | { | ||
33 | nuc932_board_init(); | ||
34 | } | ||
35 | |||
36 | MACHINE_START(NUC932EVB, "NUC932EVB") | ||
37 | /* Maintainer: Wan ZongShun */ | ||
38 | .phys_io = NUC93X_PA_UART, | ||
39 | .io_pg_offst = (((u32)NUC93X_VA_UART) >> 18) & 0xfffc, | ||
40 | .boot_params = 0, | ||
41 | .map_io = nuc932evb_map_io, | ||
42 | .init_irq = nuc93x_init_irq, | ||
43 | .init_machine = nuc932evb_init, | ||
44 | .timer = &nuc93x_timer, | ||
45 | MACHINE_END | ||
diff --git a/arch/arm/mach-nuc93x/nuc932.c b/arch/arm/mach-nuc93x/nuc932.c new file mode 100644 index 000000000000..3966ead686fc --- /dev/null +++ b/arch/arm/mach-nuc93x/nuc932.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/nuc932.c | ||
3 | * | ||
4 | * Copyright (c) 2009 Nuvoton corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * NUC932 cpu support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation;version 2 of the License. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/clk.h> | ||
18 | #include <linux/err.h> | ||
19 | |||
20 | #include <asm/mach/map.h> | ||
21 | #include <mach/hardware.h> | ||
22 | |||
23 | #include "cpu.h" | ||
24 | #include "clock.h" | ||
25 | |||
26 | /* define specific CPU platform device */ | ||
27 | |||
28 | static struct platform_device *nuc932_dev[] __initdata = { | ||
29 | }; | ||
30 | |||
31 | /* define specific CPU platform io map */ | ||
32 | |||
33 | static struct map_desc nuc932evb_iodesc[] __initdata = { | ||
34 | }; | ||
35 | |||
36 | /*Init NUC932 evb io*/ | ||
37 | |||
38 | void __init nuc932_map_io(void) | ||
39 | { | ||
40 | nuc93x_map_io(nuc932evb_iodesc, ARRAY_SIZE(nuc932evb_iodesc)); | ||
41 | } | ||
42 | |||
43 | /*Init NUC932 clock*/ | ||
44 | |||
45 | void __init nuc932_init_clocks(void) | ||
46 | { | ||
47 | nuc93x_init_clocks(); | ||
48 | } | ||
49 | |||
50 | /*enable NUC932 uart clock*/ | ||
51 | |||
52 | void __init nuc932_init_uartclk(void) | ||
53 | { | ||
54 | struct clk *ck_uart = clk_get(NULL, "uart"); | ||
55 | BUG_ON(IS_ERR(ck_uart)); | ||
56 | |||
57 | clk_enable(ck_uart); | ||
58 | } | ||
59 | |||
60 | /*Init NUC932 board info*/ | ||
61 | |||
62 | void __init nuc932_board_init(void) | ||
63 | { | ||
64 | nuc93x_board_init(nuc932_dev, ARRAY_SIZE(nuc932_dev)); | ||
65 | } | ||
diff --git a/arch/arm/mach-nuc93x/nuc932.h b/arch/arm/mach-nuc93x/nuc932.h new file mode 100644 index 000000000000..9a66edd5338f --- /dev/null +++ b/arch/arm/mach-nuc93x/nuc932.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-nuc93x/nuc932.h | ||
3 | * | ||
4 | * Copyright (c) 2008 Nuvoton corporation | ||
5 | * | ||
6 | * Header file for NUC93x CPU support | ||
7 | * | ||
8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | struct map_desc; | ||
17 | struct sys_timer; | ||
18 | |||
19 | /* core initialisation functions */ | ||
20 | |||
21 | extern void nuc93x_init_irq(void); | ||
22 | extern struct sys_timer nuc93x_timer; | ||
23 | |||
24 | /* extern file from nuc932.c */ | ||
25 | |||
26 | extern void nuc932_board_init(void); | ||
27 | extern void nuc932_init_clocks(void); | ||
28 | extern void nuc932_map_io(void); | ||
29 | extern void nuc932_init_uartclk(void); | ||
diff --git a/arch/arm/mach-nuc93x/time.c b/arch/arm/mach-nuc93x/time.c new file mode 100644 index 000000000000..2f90f9dc6e30 --- /dev/null +++ b/arch/arm/mach-nuc93x/time.c | |||
@@ -0,0 +1,100 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nuc93x/time.c | ||
3 | * | ||
4 | * Copyright (c) 2009 Nuvoton technology corporation. | ||
5 | * | ||
6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/sched.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <linux/leds.h> | ||
23 | |||
24 | #include <asm/mach-types.h> | ||
25 | #include <asm/mach/irq.h> | ||
26 | #include <asm/mach/time.h> | ||
27 | |||
28 | #include <mach/system.h> | ||
29 | #include <mach/map.h> | ||
30 | #include <mach/regs-timer.h> | ||
31 | |||
32 | #define RESETINT 0x01 | ||
33 | #define PERIOD (0x01 << 27) | ||
34 | #define ONESHOT (0x00 << 27) | ||
35 | #define COUNTEN (0x01 << 30) | ||
36 | #define INTEN (0x01 << 29) | ||
37 | |||
38 | #define TICKS_PER_SEC 100 | ||
39 | #define PRESCALE 0x63 /* Divider = prescale + 1 */ | ||
40 | |||
41 | unsigned int timer0_load; | ||
42 | |||
43 | static unsigned long nuc93x_gettimeoffset(void) | ||
44 | { | ||
45 | return 0; | ||
46 | } | ||
47 | |||
48 | /*IRQ handler for the timer*/ | ||
49 | |||
50 | static irqreturn_t nuc93x_timer_interrupt(int irq, void *dev_id) | ||
51 | { | ||
52 | timer_tick(); | ||
53 | __raw_writel(0x01, REG_TISR); /* clear TIF0 */ | ||
54 | return IRQ_HANDLED; | ||
55 | } | ||
56 | |||
57 | static struct irqaction nuc93x_timer_irq = { | ||
58 | .name = "nuc93x Timer Tick", | ||
59 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
60 | .handler = nuc93x_timer_interrupt, | ||
61 | }; | ||
62 | |||
63 | /*Set up timer reg.*/ | ||
64 | |||
65 | static void nuc93x_timer_setup(void) | ||
66 | { | ||
67 | struct clk *ck_ext = clk_get(NULL, "ext"); | ||
68 | struct clk *ck_timer = clk_get(NULL, "timer"); | ||
69 | unsigned int rate, val = 0; | ||
70 | |||
71 | BUG_ON(IS_ERR(ck_ext) || IS_ERR(ck_timer)); | ||
72 | |||
73 | clk_enable(ck_timer); | ||
74 | rate = clk_get_rate(ck_ext); | ||
75 | clk_put(ck_ext); | ||
76 | rate = rate / (PRESCALE + 0x01); | ||
77 | |||
78 | /* set a known state */ | ||
79 | __raw_writel(0x00, REG_TCSR0); | ||
80 | __raw_writel(RESETINT, REG_TISR); | ||
81 | |||
82 | timer0_load = (rate / TICKS_PER_SEC); | ||
83 | __raw_writel(timer0_load, REG_TICR0); | ||
84 | |||
85 | val |= (PERIOD | COUNTEN | INTEN | PRESCALE);; | ||
86 | __raw_writel(val, REG_TCSR0); | ||
87 | |||
88 | } | ||
89 | |||
90 | static void __init nuc93x_timer_init(void) | ||
91 | { | ||
92 | nuc93x_timer_setup(); | ||
93 | setup_irq(IRQ_TIMER0, &nuc93x_timer_irq); | ||
94 | } | ||
95 | |||
96 | struct sys_timer nuc93x_timer = { | ||
97 | .init = nuc93x_timer_init, | ||
98 | .offset = nuc93x_gettimeoffset, | ||
99 | .resume = nuc93x_timer_setup | ||
100 | }; | ||
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index aedb746fc33c..8c74cab2fa8b 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | moveq \rx, #0xff000000 @ physical base address | 17 | moveq \rx, #0xff000000 @ physical base address |
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 0c6be6b4a7e2..8ba8fb5b2514 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <plat/control.h> | 28 | #include <plat/control.h> |
29 | #include <plat/timer-gp.h> | 29 | #include <plat/timer-gp.h> |
30 | #include <asm/hardware/gic.h> | 30 | #include <asm/hardware/gic.h> |
31 | #include <asm/hardware/cache-l2x0.h> | ||
31 | 32 | ||
32 | static struct platform_device sdp4430_lcd_device = { | 33 | static struct platform_device sdp4430_lcd_device = { |
33 | .name = "sdp4430_lcd", | 34 | .name = "sdp4430_lcd", |
@@ -50,6 +51,59 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = { | |||
50 | { OMAP_TAG_LCD, &sdp4430_lcd_config }, | 51 | { OMAP_TAG_LCD, &sdp4430_lcd_config }, |
51 | }; | 52 | }; |
52 | 53 | ||
54 | #ifdef CONFIG_CACHE_L2X0 | ||
55 | noinline void omap_smc1(u32 fn, u32 arg) | ||
56 | { | ||
57 | register u32 r12 asm("r12") = fn; | ||
58 | register u32 r0 asm("r0") = arg; | ||
59 | |||
60 | /* This is common routine cache secure monitor API used to | ||
61 | * modify the PL310 secure registers. | ||
62 | * r0 contains the value to be modified and "r12" contains | ||
63 | * the monitor API number. It uses few CPU registers | ||
64 | * internally and hence they need be backed up including | ||
65 | * link register "lr". | ||
66 | * Explicitly save r11 and r12 the compiler generated code | ||
67 | * won't save it. | ||
68 | */ | ||
69 | asm volatile( | ||
70 | "stmfd r13!, {r11,r12}\n" | ||
71 | "dsb\n" | ||
72 | "smc\n" | ||
73 | "ldmfd r13!, {r11,r12}\n" | ||
74 | : "+r" (r0), "+r" (r12) | ||
75 | : | ||
76 | : "r4", "r5", "r10", "lr", "cc"); | ||
77 | } | ||
78 | EXPORT_SYMBOL(omap_smc1); | ||
79 | |||
80 | static int __init omap_l2_cache_init(void) | ||
81 | { | ||
82 | void __iomem *l2cache_base; | ||
83 | |||
84 | /* To avoid code running on other OMAPs in | ||
85 | * multi-omap builds | ||
86 | */ | ||
87 | if (!cpu_is_omap44xx()) | ||
88 | return -ENODEV; | ||
89 | |||
90 | /* Static mapping, never released */ | ||
91 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); | ||
92 | BUG_ON(!l2cache_base); | ||
93 | |||
94 | /* Enable PL310 L2 Cache controller */ | ||
95 | omap_smc1(0x102, 0x1); | ||
96 | |||
97 | /* 32KB way size, 16-way associativity, | ||
98 | * parity disabled | ||
99 | */ | ||
100 | l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); | ||
101 | |||
102 | return 0; | ||
103 | } | ||
104 | early_initcall(omap_l2_cache_init); | ||
105 | #endif | ||
106 | |||
53 | static void __init gic_init_irq(void) | 107 | static void __init gic_init_irq(void) |
54 | { | 108 | { |
55 | void __iomem *base; | 109 | void __iomem *base; |
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index e9f255df9163..86979d7bd871 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | #ifdef CONFIG_ARCH_OMAP2 | 17 | #ifdef CONFIG_ARCH_OMAP2 |
diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S index c7f808bfe272..91e0e39bb23f 100644 --- a/arch/arm/mach-orion5x/include/mach/debug-macro.S +++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S | |||
@@ -10,7 +10,7 @@ | |||
10 | 10 | ||
11 | #include <mach/orion5x.h> | 11 | #include <mach/orion5x.h> |
12 | 12 | ||
13 | .macro addruart,rx | 13 | .macro addruart, rx, tmp |
14 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
15 | tst \rx, #1 @ MMU enabled? | 15 | tst \rx, #1 @ MMU enabled? |
16 | ldreq \rx, =ORION5X_REGS_PHYS_BASE | 16 | ldreq \rx, =ORION5X_REGS_PHYS_BASE |
diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h index 7147a297e97f..06b50aeff7b9 100644 --- a/arch/arm/mach-orion5x/include/mach/vmalloc.h +++ b/arch/arm/mach-orion5x/include/mach/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * arch/arm/mach-orion5x/include/mach/vmalloc.h | 2 | * arch/arm/mach-orion5x/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xfd800000 | 5 | #define VMALLOC_END 0xfd800000UL |
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S index 6d1407f319f8..6ca8bd30bf46 100644 --- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S +++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | mov \rx, #0x00090000 | 17 | mov \rx, #0x00090000 |
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S index 55d6a175ab19..01cf81393fe2 100644 --- a/arch/arm/mach-pxa/include/mach/debug-macro.S +++ b/arch/arm/mach-pxa/include/mach/debug-macro.S | |||
@@ -13,7 +13,7 @@ | |||
13 | 13 | ||
14 | #include "hardware.h" | 14 | #include "hardware.h" |
15 | 15 | ||
16 | .macro addruart,rx | 16 | .macro addruart, rx, tmp |
17 | mrc p15, 0, \rx, c1, c0 | 17 | mrc p15, 0, \rx, c1, c0 |
18 | tst \rx, #1 @ MMU enabled? | 18 | tst \rx, #1 @ MMU enabled? |
19 | moveq \rx, #0x40000000 @ physical | 19 | moveq \rx, #0x40000000 @ physical |
diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h index e90c5eeb81dd..bfecfbf5f460 100644 --- a/arch/arm/mach-pxa/include/mach/vmalloc.h +++ b/arch/arm/mach-pxa/include/mach/vmalloc.h | |||
@@ -8,4 +8,4 @@ | |||
8 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
10 | */ | 10 | */ |
11 | #define VMALLOC_END (0xe8000000) | 11 | #define VMALLOC_END (0xe8000000UL) |
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S index 932d8af18062..86622289b74e 100644 --- a/arch/arm/mach-realview/include/mach/debug-macro.S +++ b/arch/arm/mach-realview/include/mach/debug-macro.S | |||
@@ -33,7 +33,7 @@ | |||
33 | #error "Unknown RealView platform" | 33 | #error "Unknown RealView platform" |
34 | #endif | 34 | #endif |
35 | 35 | ||
36 | .macro addruart,rx | 36 | .macro addruart, rx, tmp |
37 | mrc p15, 0, \rx, c1, c0 | 37 | mrc p15, 0, \rx, c1, c0 |
38 | tst \rx, #1 @ MMU enabled? | 38 | tst \rx, #1 @ MMU enabled? |
39 | moveq \rx, #0x10000000 | 39 | moveq \rx, #0x10000000 |
diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h index fe0de1b507ac..a2a4c6861407 100644 --- a/arch/arm/mach-realview/include/mach/vmalloc.h +++ b/arch/arm/mach-realview/include/mach/vmalloc.h | |||
@@ -18,4 +18,4 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | #define VMALLOC_END 0xf8000000 | 21 | #define VMALLOC_END 0xf8000000UL |
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S index b2a939ffdcde..6fc8d66395dc 100644 --- a/arch/arm/mach-rpc/include/mach/debug-macro.S +++ b/arch/arm/mach-rpc/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | moveq \rx, #0x03000000 | 17 | moveq \rx, #0x03000000 |
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S index 4c29a89ad077..0eef78b4a6ed 100644 --- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S | |||
@@ -19,7 +19,7 @@ | |||
19 | #define S3C2410_UART1_OFF (0x4000) | 19 | #define S3C2410_UART1_OFF (0x4000) |
20 | #define SHIFT_2440TXF (14-9) | 20 | #define SHIFT_2440TXF (14-9) |
21 | 21 | ||
22 | .macro addruart, rx | 22 | .macro addruart, rx, tmp |
23 | mrc p15, 0, \rx, c1, c0 | 23 | mrc p15, 0, \rx, c1, c0 |
24 | tst \rx, #1 | 24 | tst \rx, #1 |
25 | ldreq \rx, = S3C24XX_PA_UART | 25 | ldreq \rx, = S3C24XX_PA_UART |
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S index f0ef0ab475f6..239476b81f3b 100644 --- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S | |||
@@ -10,7 +10,7 @@ | |||
10 | #include <mach/map.h> | 10 | #include <mach/map.h> |
11 | #include <plat/regs-serial.h> | 11 | #include <plat/regs-serial.h> |
12 | 12 | ||
13 | .macro addruart, rx | 13 | .macro addruart, rx, tmp |
14 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
15 | tst \rx, #1 | 15 | tst \rx, #1 |
16 | ldreq \rx, = S3C24XX_PA_UART | 16 | ldreq \rx, = S3C24XX_PA_UART |
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h index 4d4fe4849589..914656820794 100644 --- a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h +++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h | |||
@@ -12,6 +12,6 @@ | |||
12 | #ifndef __ASM_ARCH_VMALLOC_H | 12 | #ifndef __ASM_ARCH_VMALLOC_H |
13 | #define __ASM_ARCH_VMALLOC_H | 13 | #define __ASM_ARCH_VMALLOC_H |
14 | 14 | ||
15 | #define VMALLOC_END (0xE0000000) | 15 | #define VMALLOC_END (0xe0000000UL) |
16 | 16 | ||
17 | #endif /* __ASM_ARCH_VMALLOC_H */ | 17 | #endif /* __ASM_ARCH_VMALLOC_H */ |
diff --git a/arch/arm/mach-s3c6400/include/mach/debug-macro.S b/arch/arm/mach-s3c6400/include/mach/debug-macro.S index b18ac5266dfc..5c88875d6a3f 100644 --- a/arch/arm/mach-s3c6400/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S | |||
@@ -21,7 +21,7 @@ | |||
21 | * aligned and add in the offset when we load the value here. | 21 | * aligned and add in the offset when we load the value here. |
22 | */ | 22 | */ |
23 | 23 | ||
24 | .macro addruart, rx | 24 | .macro addruart, rx, tmp |
25 | mrc p15, 0, \rx, c1, c0 | 25 | mrc p15, 0, \rx, c1, c0 |
26 | tst \rx, #1 | 26 | tst \rx, #1 |
27 | ldreq \rx, = S3C_PA_UART | 27 | ldreq \rx, = S3C_PA_UART |
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S index 9d142ccf654b..e181f5789482 100644 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S | |||
@@ -22,7 +22,7 @@ | |||
22 | * aligned and add in the offset when we load the value here. | 22 | * aligned and add in the offset when we load the value here. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | .macro addruart, rx | 25 | .macro addruart, rx, tmp |
26 | mrc p15, 0, \rx, c1, c0 | 26 | mrc p15, 0, \rx, c1, c0 |
27 | tst \rx, #1 | 27 | tst \rx, #1 |
28 | ldreq \rx, = S3C_PA_UART | 28 | ldreq \rx, = S3C_PA_UART |
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S index 1f0634d92702..336adccea542 100644 --- a/arch/arm/mach-sa1100/include/mach/debug-macro.S +++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S | |||
@@ -12,7 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | #include <mach/hardware.h> | 13 | #include <mach/hardware.h> |
14 | 14 | ||
15 | .macro addruart,rx | 15 | .macro addruart, rx, tmp |
16 | mrc p15, 0, \rx, c1, c0 | 16 | mrc p15, 0, \rx, c1, c0 |
17 | tst \rx, #1 @ MMU enabled? | 17 | tst \rx, #1 @ MMU enabled? |
18 | moveq \rx, #0x80000000 @ physical base address | 18 | moveq \rx, #0x80000000 @ physical base address |
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h index ec8fdc5a3606..b3d002398480 100644 --- a/arch/arm/mach-sa1100/include/mach/vmalloc.h +++ b/arch/arm/mach-sa1100/include/mach/vmalloc.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-sa1100/include/mach/vmalloc.h | 2 | * arch/arm/mach-sa1100/include/mach/vmalloc.h |
3 | */ | 3 | */ |
4 | #define VMALLOC_END (0xe8000000) | 4 | #define VMALLOC_END (0xe8000000UL) |
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index f97a7626bd58..50f071c5bf4d 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mov \rx, #0xe0000000 | 15 | mov \rx, #0xe0000000 |
16 | orr \rx, \rx, #0x000003f8 | 16 | orr \rx, \rx, #0x000003f8 |
17 | .endm | 17 | .endm |
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index c174ed1f3691..5af71d5ba665 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c | |||
@@ -610,34 +610,34 @@ EXPORT_SYMBOL(clk_get_rate); | |||
610 | 610 | ||
611 | static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate) | 611 | static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate) |
612 | { | 612 | { |
613 | if (rate >= 18900000) | 613 | if (rate <= 18900000) |
614 | return 18900000; | 614 | return 18900000; |
615 | if (rate >= 20800000) | 615 | if (rate <= 20800000) |
616 | return 20800000; | 616 | return 20800000; |
617 | if (rate >= 23100000) | 617 | if (rate <= 23100000) |
618 | return 23100000; | 618 | return 23100000; |
619 | if (rate >= 26000000) | 619 | if (rate <= 26000000) |
620 | return 26000000; | 620 | return 26000000; |
621 | if (rate >= 29700000) | 621 | if (rate <= 29700000) |
622 | return 29700000; | 622 | return 29700000; |
623 | if (rate >= 34700000) | 623 | if (rate <= 34700000) |
624 | return 34700000; | 624 | return 34700000; |
625 | if (rate >= 41600000) | 625 | if (rate <= 41600000) |
626 | return 41600000; | 626 | return 41600000; |
627 | if (rate >= 52000000) | 627 | if (rate <= 52000000) |
628 | return 52000000; | 628 | return 52000000; |
629 | return -EINVAL; | 629 | return -EINVAL; |
630 | } | 630 | } |
631 | 631 | ||
632 | static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) | 632 | static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) |
633 | { | 633 | { |
634 | if (rate >= 13000000) | 634 | if (rate <= 13000000) |
635 | return 13000000; | 635 | return 13000000; |
636 | if (rate >= 52000000) | 636 | if (rate <= 52000000) |
637 | return 52000000; | 637 | return 52000000; |
638 | if (rate >= 104000000) | 638 | if (rate <= 104000000) |
639 | return 104000000; | 639 | return 104000000; |
640 | if (rate >= 208000000) | 640 | if (rate <= 208000000) |
641 | return 208000000; | 641 | return 208000000; |
642 | return -EINVAL; | 642 | return -EINVAL; |
643 | } | 643 | } |
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 653e25be3dd8..01b50313914c 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * arch/arm/mach-u300/core.c | 3 | * arch/arm/mach-u300/core.c |
4 | * | 4 | * |
5 | * | 5 | * |
6 | * Copyright (C) 2007-2009 ST-Ericsson AB | 6 | * Copyright (C) 2007-2010 ST-Ericsson AB |
7 | * License terms: GNU General Public License (GPL) version 2 | 7 | * License terms: GNU General Public License (GPL) version 2 |
8 | * Core platform support, IRQ handling and device definitions. | 8 | * Core platform support, IRQ handling and device definitions. |
9 | * Author: Linus Walleij <linus.walleij@stericsson.com> | 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/amba/bus.h> | 19 | #include <linux/amba/bus.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/gpio.h> | 21 | #include <linux/gpio.h> |
22 | #include <mach/coh901318.h> | ||
22 | 23 | ||
23 | #include <asm/types.h> | 24 | #include <asm/types.h> |
24 | #include <asm/setup.h> | 25 | #include <asm/setup.h> |
@@ -29,6 +30,7 @@ | |||
29 | 30 | ||
30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
31 | #include <mach/syscon.h> | 32 | #include <mach/syscon.h> |
33 | #include <mach/dma_channels.h> | ||
32 | 34 | ||
33 | #include "clock.h" | 35 | #include "clock.h" |
34 | #include "mmc.h" | 36 | #include "mmc.h" |
@@ -372,8 +374,1019 @@ static struct resource ave_resources[] = { | |||
372 | }, | 374 | }, |
373 | }; | 375 | }; |
374 | 376 | ||
377 | static struct resource dma_resource[] = { | ||
378 | { | ||
379 | .start = U300_DMAC_BASE, | ||
380 | .end = U300_DMAC_BASE + PAGE_SIZE - 1, | ||
381 | .flags = IORESOURCE_MEM, | ||
382 | }, | ||
383 | { | ||
384 | .start = IRQ_U300_DMA, | ||
385 | .end = IRQ_U300_DMA, | ||
386 | .flags = IORESOURCE_IRQ, | ||
387 | } | ||
388 | }; | ||
389 | |||
390 | #ifdef CONFIG_MACH_U300_BS335 | ||
391 | /* points out all dma slave channels. | ||
392 | * Syntax is [A1, B1, A2, B2, .... ,-1,-1] | ||
393 | * Select all channels from A to B, end of list is marked with -1,-1 | ||
394 | */ | ||
395 | static int dma_slave_channels[] = { | ||
396 | U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, | ||
397 | U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1}; | ||
398 | |||
399 | /* points out all dma memcpy channels. */ | ||
400 | static int dma_memcpy_channels[] = { | ||
401 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; | ||
402 | |||
403 | #else /* CONFIG_MACH_U300_BS335 */ | ||
404 | |||
405 | static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1}; | ||
406 | static int dma_memcpy_channels[] = { | ||
407 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1}; | ||
408 | |||
409 | #endif | ||
410 | |||
411 | /** register dma for memory access | ||
412 | * | ||
413 | * active 1 means dma intends to access memory | ||
414 | * 0 means dma wont access memory | ||
415 | */ | ||
416 | static void coh901318_access_memory_state(struct device *dev, bool active) | ||
417 | { | ||
418 | } | ||
419 | |||
420 | #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \ | ||
421 | COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \ | ||
422 | COH901318_CX_CFG_LCR_DISABLE | \ | ||
423 | COH901318_CX_CFG_TC_IRQ_ENABLE | \ | ||
424 | COH901318_CX_CFG_BE_IRQ_ENABLE) | ||
425 | #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \ | ||
426 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | ||
427 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | ||
428 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | ||
429 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | ||
430 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | ||
431 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | ||
432 | COH901318_CX_CTRL_TCP_DISABLE | \ | ||
433 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ | ||
434 | COH901318_CX_CTRL_HSP_DISABLE | \ | ||
435 | COH901318_CX_CTRL_HSS_DISABLE | \ | ||
436 | COH901318_CX_CTRL_DDMA_LEGACY | \ | ||
437 | COH901318_CX_CTRL_PRDD_SOURCE) | ||
438 | #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \ | ||
439 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | ||
440 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | ||
441 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | ||
442 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | ||
443 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | ||
444 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | ||
445 | COH901318_CX_CTRL_TCP_DISABLE | \ | ||
446 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ | ||
447 | COH901318_CX_CTRL_HSP_DISABLE | \ | ||
448 | COH901318_CX_CTRL_HSS_DISABLE | \ | ||
449 | COH901318_CX_CTRL_DDMA_LEGACY | \ | ||
450 | COH901318_CX_CTRL_PRDD_SOURCE) | ||
451 | #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \ | ||
452 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | ||
453 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | ||
454 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | ||
455 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | ||
456 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | ||
457 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | ||
458 | COH901318_CX_CTRL_TCP_DISABLE | \ | ||
459 | COH901318_CX_CTRL_TC_IRQ_ENABLE | \ | ||
460 | COH901318_CX_CTRL_HSP_DISABLE | \ | ||
461 | COH901318_CX_CTRL_HSS_DISABLE | \ | ||
462 | COH901318_CX_CTRL_DDMA_LEGACY | \ | ||
463 | COH901318_CX_CTRL_PRDD_SOURCE) | ||
464 | |||
465 | const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { | ||
466 | { | ||
467 | .number = U300_DMA_MSL_TX_0, | ||
468 | .name = "MSL TX 0", | ||
469 | .priority_high = 0, | ||
470 | .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20, | ||
471 | }, | ||
472 | { | ||
473 | .number = U300_DMA_MSL_TX_1, | ||
474 | .name = "MSL TX 1", | ||
475 | .priority_high = 0, | ||
476 | .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20, | ||
477 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
478 | COH901318_CX_CFG_LCR_DISABLE | | ||
479 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
480 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
481 | .param.ctrl_lli_chained = 0 | | ||
482 | COH901318_CX_CTRL_TC_ENABLE | | ||
483 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
484 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
485 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
486 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
487 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
488 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
489 | COH901318_CX_CTRL_TCP_DISABLE | | ||
490 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
491 | COH901318_CX_CTRL_HSP_ENABLE | | ||
492 | COH901318_CX_CTRL_HSS_DISABLE | | ||
493 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
494 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
495 | .param.ctrl_lli = 0 | | ||
496 | COH901318_CX_CTRL_TC_ENABLE | | ||
497 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
498 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
499 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
500 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
501 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
502 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
503 | COH901318_CX_CTRL_TCP_ENABLE | | ||
504 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
505 | COH901318_CX_CTRL_HSP_ENABLE | | ||
506 | COH901318_CX_CTRL_HSS_DISABLE | | ||
507 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
508 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
509 | .param.ctrl_lli_last = 0 | | ||
510 | COH901318_CX_CTRL_TC_ENABLE | | ||
511 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
512 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
513 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
514 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
515 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
516 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
517 | COH901318_CX_CTRL_TCP_ENABLE | | ||
518 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
519 | COH901318_CX_CTRL_HSP_ENABLE | | ||
520 | COH901318_CX_CTRL_HSS_DISABLE | | ||
521 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
522 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
523 | }, | ||
524 | { | ||
525 | .number = U300_DMA_MSL_TX_2, | ||
526 | .name = "MSL TX 2", | ||
527 | .priority_high = 0, | ||
528 | .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20, | ||
529 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
530 | COH901318_CX_CFG_LCR_DISABLE | | ||
531 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
532 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
533 | .param.ctrl_lli_chained = 0 | | ||
534 | COH901318_CX_CTRL_TC_ENABLE | | ||
535 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
536 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
537 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
538 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
539 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
540 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
541 | COH901318_CX_CTRL_TCP_DISABLE | | ||
542 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
543 | COH901318_CX_CTRL_HSP_ENABLE | | ||
544 | COH901318_CX_CTRL_HSS_DISABLE | | ||
545 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
546 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
547 | .param.ctrl_lli = 0 | | ||
548 | COH901318_CX_CTRL_TC_ENABLE | | ||
549 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
550 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
551 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
552 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
553 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
554 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
555 | COH901318_CX_CTRL_TCP_ENABLE | | ||
556 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
557 | COH901318_CX_CTRL_HSP_ENABLE | | ||
558 | COH901318_CX_CTRL_HSS_DISABLE | | ||
559 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
560 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
561 | .param.ctrl_lli_last = 0 | | ||
562 | COH901318_CX_CTRL_TC_ENABLE | | ||
563 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
564 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
565 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
566 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
567 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
568 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
569 | COH901318_CX_CTRL_TCP_ENABLE | | ||
570 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
571 | COH901318_CX_CTRL_HSP_ENABLE | | ||
572 | COH901318_CX_CTRL_HSS_DISABLE | | ||
573 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
574 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
575 | .desc_nbr_max = 10, | ||
576 | }, | ||
577 | { | ||
578 | .number = U300_DMA_MSL_TX_3, | ||
579 | .name = "MSL TX 3", | ||
580 | .priority_high = 0, | ||
581 | .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20, | ||
582 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
583 | COH901318_CX_CFG_LCR_DISABLE | | ||
584 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
585 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
586 | .param.ctrl_lli_chained = 0 | | ||
587 | COH901318_CX_CTRL_TC_ENABLE | | ||
588 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
589 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
590 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
591 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
592 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
593 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
594 | COH901318_CX_CTRL_TCP_DISABLE | | ||
595 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
596 | COH901318_CX_CTRL_HSP_ENABLE | | ||
597 | COH901318_CX_CTRL_HSS_DISABLE | | ||
598 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
599 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
600 | .param.ctrl_lli = 0 | | ||
601 | COH901318_CX_CTRL_TC_ENABLE | | ||
602 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
603 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
604 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
605 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
606 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
607 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
608 | COH901318_CX_CTRL_TCP_ENABLE | | ||
609 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
610 | COH901318_CX_CTRL_HSP_ENABLE | | ||
611 | COH901318_CX_CTRL_HSS_DISABLE | | ||
612 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
613 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
614 | .param.ctrl_lli_last = 0 | | ||
615 | COH901318_CX_CTRL_TC_ENABLE | | ||
616 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
617 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
618 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
619 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
620 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
621 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
622 | COH901318_CX_CTRL_TCP_ENABLE | | ||
623 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
624 | COH901318_CX_CTRL_HSP_ENABLE | | ||
625 | COH901318_CX_CTRL_HSS_DISABLE | | ||
626 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
627 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
628 | }, | ||
629 | { | ||
630 | .number = U300_DMA_MSL_TX_4, | ||
631 | .name = "MSL TX 4", | ||
632 | .priority_high = 0, | ||
633 | .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20, | ||
634 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
635 | COH901318_CX_CFG_LCR_DISABLE | | ||
636 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
637 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
638 | .param.ctrl_lli_chained = 0 | | ||
639 | COH901318_CX_CTRL_TC_ENABLE | | ||
640 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
641 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
642 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
643 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
644 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
645 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
646 | COH901318_CX_CTRL_TCP_DISABLE | | ||
647 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
648 | COH901318_CX_CTRL_HSP_ENABLE | | ||
649 | COH901318_CX_CTRL_HSS_DISABLE | | ||
650 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
651 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
652 | .param.ctrl_lli = 0 | | ||
653 | COH901318_CX_CTRL_TC_ENABLE | | ||
654 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
655 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
656 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
657 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
658 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
659 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
660 | COH901318_CX_CTRL_TCP_ENABLE | | ||
661 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
662 | COH901318_CX_CTRL_HSP_ENABLE | | ||
663 | COH901318_CX_CTRL_HSS_DISABLE | | ||
664 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
665 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
666 | .param.ctrl_lli_last = 0 | | ||
667 | COH901318_CX_CTRL_TC_ENABLE | | ||
668 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
669 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
670 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
671 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
672 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
673 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | ||
674 | COH901318_CX_CTRL_TCP_ENABLE | | ||
675 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
676 | COH901318_CX_CTRL_HSP_ENABLE | | ||
677 | COH901318_CX_CTRL_HSS_DISABLE | | ||
678 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
679 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
680 | }, | ||
681 | { | ||
682 | .number = U300_DMA_MSL_TX_5, | ||
683 | .name = "MSL TX 5", | ||
684 | .priority_high = 0, | ||
685 | .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20, | ||
686 | }, | ||
687 | { | ||
688 | .number = U300_DMA_MSL_TX_6, | ||
689 | .name = "MSL TX 6", | ||
690 | .priority_high = 0, | ||
691 | .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20, | ||
692 | }, | ||
693 | { | ||
694 | .number = U300_DMA_MSL_RX_0, | ||
695 | .name = "MSL RX 0", | ||
696 | .priority_high = 0, | ||
697 | .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220, | ||
698 | }, | ||
699 | { | ||
700 | .number = U300_DMA_MSL_RX_1, | ||
701 | .name = "MSL RX 1", | ||
702 | .priority_high = 0, | ||
703 | .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220, | ||
704 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
705 | COH901318_CX_CFG_LCR_DISABLE | | ||
706 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
707 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
708 | .param.ctrl_lli_chained = 0 | | ||
709 | COH901318_CX_CTRL_TC_ENABLE | | ||
710 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
711 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
712 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
713 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
714 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
715 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
716 | COH901318_CX_CTRL_TCP_DISABLE | | ||
717 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
718 | COH901318_CX_CTRL_HSP_ENABLE | | ||
719 | COH901318_CX_CTRL_HSS_DISABLE | | ||
720 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
721 | COH901318_CX_CTRL_PRDD_DEST, | ||
722 | .param.ctrl_lli = 0, | ||
723 | .param.ctrl_lli_last = 0 | | ||
724 | COH901318_CX_CTRL_TC_ENABLE | | ||
725 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
726 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
727 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
728 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
729 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
730 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
731 | COH901318_CX_CTRL_TCP_DISABLE | | ||
732 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
733 | COH901318_CX_CTRL_HSP_ENABLE | | ||
734 | COH901318_CX_CTRL_HSS_DISABLE | | ||
735 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
736 | COH901318_CX_CTRL_PRDD_DEST, | ||
737 | }, | ||
738 | { | ||
739 | .number = U300_DMA_MSL_RX_2, | ||
740 | .name = "MSL RX 2", | ||
741 | .priority_high = 0, | ||
742 | .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220, | ||
743 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
744 | COH901318_CX_CFG_LCR_DISABLE | | ||
745 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
746 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
747 | .param.ctrl_lli_chained = 0 | | ||
748 | COH901318_CX_CTRL_TC_ENABLE | | ||
749 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
750 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
751 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
752 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
753 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
754 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
755 | COH901318_CX_CTRL_TCP_DISABLE | | ||
756 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
757 | COH901318_CX_CTRL_HSP_ENABLE | | ||
758 | COH901318_CX_CTRL_HSS_DISABLE | | ||
759 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
760 | COH901318_CX_CTRL_PRDD_DEST, | ||
761 | .param.ctrl_lli = 0 | | ||
762 | COH901318_CX_CTRL_TC_ENABLE | | ||
763 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
764 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
765 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
766 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
767 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
768 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
769 | COH901318_CX_CTRL_TCP_DISABLE | | ||
770 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
771 | COH901318_CX_CTRL_HSP_ENABLE | | ||
772 | COH901318_CX_CTRL_HSS_DISABLE | | ||
773 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
774 | COH901318_CX_CTRL_PRDD_DEST, | ||
775 | .param.ctrl_lli_last = 0 | | ||
776 | COH901318_CX_CTRL_TC_ENABLE | | ||
777 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
778 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
779 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
780 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
781 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
782 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
783 | COH901318_CX_CTRL_TCP_DISABLE | | ||
784 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
785 | COH901318_CX_CTRL_HSP_ENABLE | | ||
786 | COH901318_CX_CTRL_HSS_DISABLE | | ||
787 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
788 | COH901318_CX_CTRL_PRDD_DEST, | ||
789 | }, | ||
790 | { | ||
791 | .number = U300_DMA_MSL_RX_3, | ||
792 | .name = "MSL RX 3", | ||
793 | .priority_high = 0, | ||
794 | .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220, | ||
795 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
796 | COH901318_CX_CFG_LCR_DISABLE | | ||
797 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
798 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
799 | .param.ctrl_lli_chained = 0 | | ||
800 | COH901318_CX_CTRL_TC_ENABLE | | ||
801 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
802 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
803 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
804 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
805 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
806 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
807 | COH901318_CX_CTRL_TCP_DISABLE | | ||
808 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
809 | COH901318_CX_CTRL_HSP_ENABLE | | ||
810 | COH901318_CX_CTRL_HSS_DISABLE | | ||
811 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
812 | COH901318_CX_CTRL_PRDD_DEST, | ||
813 | .param.ctrl_lli = 0 | | ||
814 | COH901318_CX_CTRL_TC_ENABLE | | ||
815 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
816 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
817 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
818 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
819 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
820 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
821 | COH901318_CX_CTRL_TCP_DISABLE | | ||
822 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
823 | COH901318_CX_CTRL_HSP_ENABLE | | ||
824 | COH901318_CX_CTRL_HSS_DISABLE | | ||
825 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
826 | COH901318_CX_CTRL_PRDD_DEST, | ||
827 | .param.ctrl_lli_last = 0 | | ||
828 | COH901318_CX_CTRL_TC_ENABLE | | ||
829 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
830 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
831 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
832 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
833 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
834 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
835 | COH901318_CX_CTRL_TCP_DISABLE | | ||
836 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
837 | COH901318_CX_CTRL_HSP_ENABLE | | ||
838 | COH901318_CX_CTRL_HSS_DISABLE | | ||
839 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
840 | COH901318_CX_CTRL_PRDD_DEST, | ||
841 | }, | ||
842 | { | ||
843 | .number = U300_DMA_MSL_RX_4, | ||
844 | .name = "MSL RX 4", | ||
845 | .priority_high = 0, | ||
846 | .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220, | ||
847 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
848 | COH901318_CX_CFG_LCR_DISABLE | | ||
849 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
850 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
851 | .param.ctrl_lli_chained = 0 | | ||
852 | COH901318_CX_CTRL_TC_ENABLE | | ||
853 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
854 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
855 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
856 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
857 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
858 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
859 | COH901318_CX_CTRL_TCP_DISABLE | | ||
860 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
861 | COH901318_CX_CTRL_HSP_ENABLE | | ||
862 | COH901318_CX_CTRL_HSS_DISABLE | | ||
863 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
864 | COH901318_CX_CTRL_PRDD_DEST, | ||
865 | .param.ctrl_lli = 0 | | ||
866 | COH901318_CX_CTRL_TC_ENABLE | | ||
867 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
868 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
869 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
870 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
871 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
872 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
873 | COH901318_CX_CTRL_TCP_DISABLE | | ||
874 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
875 | COH901318_CX_CTRL_HSP_ENABLE | | ||
876 | COH901318_CX_CTRL_HSS_DISABLE | | ||
877 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
878 | COH901318_CX_CTRL_PRDD_DEST, | ||
879 | .param.ctrl_lli_last = 0 | | ||
880 | COH901318_CX_CTRL_TC_ENABLE | | ||
881 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
882 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
883 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
884 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
885 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
886 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
887 | COH901318_CX_CTRL_TCP_DISABLE | | ||
888 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
889 | COH901318_CX_CTRL_HSP_ENABLE | | ||
890 | COH901318_CX_CTRL_HSS_DISABLE | | ||
891 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
892 | COH901318_CX_CTRL_PRDD_DEST, | ||
893 | }, | ||
894 | { | ||
895 | .number = U300_DMA_MSL_RX_5, | ||
896 | .name = "MSL RX 5", | ||
897 | .priority_high = 0, | ||
898 | .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220, | ||
899 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
900 | COH901318_CX_CFG_LCR_DISABLE | | ||
901 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
902 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
903 | .param.ctrl_lli_chained = 0 | | ||
904 | COH901318_CX_CTRL_TC_ENABLE | | ||
905 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
906 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
907 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
908 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
909 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
910 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
911 | COH901318_CX_CTRL_TCP_DISABLE | | ||
912 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
913 | COH901318_CX_CTRL_HSP_ENABLE | | ||
914 | COH901318_CX_CTRL_HSS_DISABLE | | ||
915 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
916 | COH901318_CX_CTRL_PRDD_DEST, | ||
917 | .param.ctrl_lli = 0 | | ||
918 | COH901318_CX_CTRL_TC_ENABLE | | ||
919 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
920 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
921 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
922 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
923 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
924 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
925 | COH901318_CX_CTRL_TCP_DISABLE | | ||
926 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
927 | COH901318_CX_CTRL_HSP_ENABLE | | ||
928 | COH901318_CX_CTRL_HSS_DISABLE | | ||
929 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
930 | COH901318_CX_CTRL_PRDD_DEST, | ||
931 | .param.ctrl_lli_last = 0 | | ||
932 | COH901318_CX_CTRL_TC_ENABLE | | ||
933 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
934 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
935 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
936 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
937 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
938 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | ||
939 | COH901318_CX_CTRL_TCP_DISABLE | | ||
940 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
941 | COH901318_CX_CTRL_HSP_ENABLE | | ||
942 | COH901318_CX_CTRL_HSS_DISABLE | | ||
943 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | ||
944 | COH901318_CX_CTRL_PRDD_DEST, | ||
945 | }, | ||
946 | { | ||
947 | .number = U300_DMA_MSL_RX_6, | ||
948 | .name = "MSL RX 6", | ||
949 | .priority_high = 0, | ||
950 | .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, | ||
951 | }, | ||
952 | { | ||
953 | .number = U300_DMA_MMCSD_RX_TX, | ||
954 | .name = "MMCSD RX TX", | ||
955 | .priority_high = 0, | ||
956 | .dev_addr = U300_MMCSD_BASE + 0x080, | ||
957 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
958 | COH901318_CX_CFG_LCR_DISABLE | | ||
959 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
960 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
961 | .param.ctrl_lli_chained = 0 | | ||
962 | COH901318_CX_CTRL_TC_ENABLE | | ||
963 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
964 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
965 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
966 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
967 | COH901318_CX_CTRL_TCP_ENABLE | | ||
968 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
969 | COH901318_CX_CTRL_HSP_ENABLE | | ||
970 | COH901318_CX_CTRL_HSS_DISABLE | | ||
971 | COH901318_CX_CTRL_DDMA_LEGACY, | ||
972 | .param.ctrl_lli = 0 | | ||
973 | COH901318_CX_CTRL_TC_ENABLE | | ||
974 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
975 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
976 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
977 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
978 | COH901318_CX_CTRL_TCP_ENABLE | | ||
979 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
980 | COH901318_CX_CTRL_HSP_ENABLE | | ||
981 | COH901318_CX_CTRL_HSS_DISABLE | | ||
982 | COH901318_CX_CTRL_DDMA_LEGACY, | ||
983 | .param.ctrl_lli_last = 0 | | ||
984 | COH901318_CX_CTRL_TC_ENABLE | | ||
985 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | ||
986 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
987 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
988 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
989 | COH901318_CX_CTRL_TCP_DISABLE | | ||
990 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
991 | COH901318_CX_CTRL_HSP_ENABLE | | ||
992 | COH901318_CX_CTRL_HSS_DISABLE | | ||
993 | COH901318_CX_CTRL_DDMA_LEGACY, | ||
994 | |||
995 | }, | ||
996 | { | ||
997 | .number = U300_DMA_MSPRO_TX, | ||
998 | .name = "MSPRO TX", | ||
999 | .priority_high = 0, | ||
1000 | }, | ||
1001 | { | ||
1002 | .number = U300_DMA_MSPRO_RX, | ||
1003 | .name = "MSPRO RX", | ||
1004 | .priority_high = 0, | ||
1005 | }, | ||
1006 | { | ||
1007 | .number = U300_DMA_UART0_TX, | ||
1008 | .name = "UART0 TX", | ||
1009 | .priority_high = 0, | ||
1010 | }, | ||
1011 | { | ||
1012 | .number = U300_DMA_UART0_RX, | ||
1013 | .name = "UART0 RX", | ||
1014 | .priority_high = 0, | ||
1015 | }, | ||
1016 | { | ||
1017 | .number = U300_DMA_APEX_TX, | ||
1018 | .name = "APEX TX", | ||
1019 | .priority_high = 0, | ||
1020 | }, | ||
1021 | { | ||
1022 | .number = U300_DMA_APEX_RX, | ||
1023 | .name = "APEX RX", | ||
1024 | .priority_high = 0, | ||
1025 | }, | ||
1026 | { | ||
1027 | .number = U300_DMA_PCM_I2S0_TX, | ||
1028 | .name = "PCM I2S0 TX", | ||
1029 | .priority_high = 1, | ||
1030 | .dev_addr = U300_PCM_I2S0_BASE + 0x14, | ||
1031 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
1032 | COH901318_CX_CFG_LCR_DISABLE | | ||
1033 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
1034 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
1035 | .param.ctrl_lli_chained = 0 | | ||
1036 | COH901318_CX_CTRL_TC_ENABLE | | ||
1037 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1038 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1039 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
1040 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1041 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
1042 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1043 | COH901318_CX_CTRL_TCP_DISABLE | | ||
1044 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1045 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1046 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1047 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1048 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
1049 | .param.ctrl_lli = 0 | | ||
1050 | COH901318_CX_CTRL_TC_ENABLE | | ||
1051 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1052 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1053 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
1054 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1055 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
1056 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1057 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1058 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1059 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1060 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1061 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1062 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
1063 | .param.ctrl_lli_last = 0 | | ||
1064 | COH901318_CX_CTRL_TC_ENABLE | | ||
1065 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1066 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1067 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
1068 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1069 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
1070 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1071 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1072 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
1073 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1074 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1075 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1076 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
1077 | }, | ||
1078 | { | ||
1079 | .number = U300_DMA_PCM_I2S0_RX, | ||
1080 | .name = "PCM I2S0 RX", | ||
1081 | .priority_high = 1, | ||
1082 | .dev_addr = U300_PCM_I2S0_BASE + 0x10, | ||
1083 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
1084 | COH901318_CX_CFG_LCR_DISABLE | | ||
1085 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
1086 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
1087 | .param.ctrl_lli_chained = 0 | | ||
1088 | COH901318_CX_CTRL_TC_ENABLE | | ||
1089 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1090 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1091 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
1092 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1093 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
1094 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1095 | COH901318_CX_CTRL_TCP_DISABLE | | ||
1096 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1097 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1098 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1099 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1100 | COH901318_CX_CTRL_PRDD_DEST, | ||
1101 | .param.ctrl_lli = 0 | | ||
1102 | COH901318_CX_CTRL_TC_ENABLE | | ||
1103 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1104 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1105 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
1106 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1107 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
1108 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1109 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1110 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1111 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1112 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1113 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1114 | COH901318_CX_CTRL_PRDD_DEST, | ||
1115 | .param.ctrl_lli_last = 0 | | ||
1116 | COH901318_CX_CTRL_TC_ENABLE | | ||
1117 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1118 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1119 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
1120 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1121 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
1122 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1123 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1124 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
1125 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1126 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1127 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1128 | COH901318_CX_CTRL_PRDD_DEST, | ||
1129 | }, | ||
1130 | { | ||
1131 | .number = U300_DMA_PCM_I2S1_TX, | ||
1132 | .name = "PCM I2S1 TX", | ||
1133 | .priority_high = 1, | ||
1134 | .dev_addr = U300_PCM_I2S1_BASE + 0x14, | ||
1135 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
1136 | COH901318_CX_CFG_LCR_DISABLE | | ||
1137 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
1138 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
1139 | .param.ctrl_lli_chained = 0 | | ||
1140 | COH901318_CX_CTRL_TC_ENABLE | | ||
1141 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1142 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1143 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
1144 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1145 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
1146 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1147 | COH901318_CX_CTRL_TCP_DISABLE | | ||
1148 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1149 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1150 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1151 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1152 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
1153 | .param.ctrl_lli = 0 | | ||
1154 | COH901318_CX_CTRL_TC_ENABLE | | ||
1155 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1156 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1157 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
1158 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1159 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
1160 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1161 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1162 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1163 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1164 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1165 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1166 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
1167 | .param.ctrl_lli_last = 0 | | ||
1168 | COH901318_CX_CTRL_TC_ENABLE | | ||
1169 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1170 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1171 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | ||
1172 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1173 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | ||
1174 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1175 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1176 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
1177 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1178 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1179 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1180 | COH901318_CX_CTRL_PRDD_SOURCE, | ||
1181 | }, | ||
1182 | { | ||
1183 | .number = U300_DMA_PCM_I2S1_RX, | ||
1184 | .name = "PCM I2S1 RX", | ||
1185 | .priority_high = 1, | ||
1186 | .dev_addr = U300_PCM_I2S1_BASE + 0x10, | ||
1187 | .param.config = COH901318_CX_CFG_CH_DISABLE | | ||
1188 | COH901318_CX_CFG_LCR_DISABLE | | ||
1189 | COH901318_CX_CFG_TC_IRQ_ENABLE | | ||
1190 | COH901318_CX_CFG_BE_IRQ_ENABLE, | ||
1191 | .param.ctrl_lli_chained = 0 | | ||
1192 | COH901318_CX_CTRL_TC_ENABLE | | ||
1193 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1194 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1195 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
1196 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1197 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
1198 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1199 | COH901318_CX_CTRL_TCP_DISABLE | | ||
1200 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1201 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1202 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1203 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1204 | COH901318_CX_CTRL_PRDD_DEST, | ||
1205 | .param.ctrl_lli = 0 | | ||
1206 | COH901318_CX_CTRL_TC_ENABLE | | ||
1207 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1208 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1209 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
1210 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1211 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
1212 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1213 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1214 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | ||
1215 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1216 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1217 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1218 | COH901318_CX_CTRL_PRDD_DEST, | ||
1219 | .param.ctrl_lli_last = 0 | | ||
1220 | COH901318_CX_CTRL_TC_ENABLE | | ||
1221 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | ||
1222 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | ||
1223 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | ||
1224 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | ||
1225 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | ||
1226 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | ||
1227 | COH901318_CX_CTRL_TCP_ENABLE | | ||
1228 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | ||
1229 | COH901318_CX_CTRL_HSP_ENABLE | | ||
1230 | COH901318_CX_CTRL_HSS_DISABLE | | ||
1231 | COH901318_CX_CTRL_DDMA_LEGACY | | ||
1232 | COH901318_CX_CTRL_PRDD_DEST, | ||
1233 | }, | ||
1234 | { | ||
1235 | .number = U300_DMA_XGAM_CDI, | ||
1236 | .name = "XGAM CDI", | ||
1237 | .priority_high = 0, | ||
1238 | }, | ||
1239 | { | ||
1240 | .number = U300_DMA_XGAM_PDI, | ||
1241 | .name = "XGAM PDI", | ||
1242 | .priority_high = 0, | ||
1243 | }, | ||
1244 | { | ||
1245 | .number = U300_DMA_SPI_TX, | ||
1246 | .name = "SPI TX", | ||
1247 | .priority_high = 0, | ||
1248 | }, | ||
1249 | { | ||
1250 | .number = U300_DMA_SPI_RX, | ||
1251 | .name = "SPI RX", | ||
1252 | .priority_high = 0, | ||
1253 | }, | ||
1254 | { | ||
1255 | .number = U300_DMA_GENERAL_PURPOSE_0, | ||
1256 | .name = "GENERAL 00", | ||
1257 | .priority_high = 0, | ||
1258 | |||
1259 | .param.config = flags_memcpy_config, | ||
1260 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1261 | .param.ctrl_lli = flags_memcpy_lli, | ||
1262 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1263 | }, | ||
1264 | { | ||
1265 | .number = U300_DMA_GENERAL_PURPOSE_1, | ||
1266 | .name = "GENERAL 01", | ||
1267 | .priority_high = 0, | ||
1268 | |||
1269 | .param.config = flags_memcpy_config, | ||
1270 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1271 | .param.ctrl_lli = flags_memcpy_lli, | ||
1272 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1273 | }, | ||
1274 | { | ||
1275 | .number = U300_DMA_GENERAL_PURPOSE_2, | ||
1276 | .name = "GENERAL 02", | ||
1277 | .priority_high = 0, | ||
1278 | |||
1279 | .param.config = flags_memcpy_config, | ||
1280 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1281 | .param.ctrl_lli = flags_memcpy_lli, | ||
1282 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1283 | }, | ||
1284 | { | ||
1285 | .number = U300_DMA_GENERAL_PURPOSE_3, | ||
1286 | .name = "GENERAL 03", | ||
1287 | .priority_high = 0, | ||
1288 | |||
1289 | .param.config = flags_memcpy_config, | ||
1290 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1291 | .param.ctrl_lli = flags_memcpy_lli, | ||
1292 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1293 | }, | ||
1294 | { | ||
1295 | .number = U300_DMA_GENERAL_PURPOSE_4, | ||
1296 | .name = "GENERAL 04", | ||
1297 | .priority_high = 0, | ||
1298 | |||
1299 | .param.config = flags_memcpy_config, | ||
1300 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1301 | .param.ctrl_lli = flags_memcpy_lli, | ||
1302 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1303 | }, | ||
1304 | { | ||
1305 | .number = U300_DMA_GENERAL_PURPOSE_5, | ||
1306 | .name = "GENERAL 05", | ||
1307 | .priority_high = 0, | ||
1308 | |||
1309 | .param.config = flags_memcpy_config, | ||
1310 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1311 | .param.ctrl_lli = flags_memcpy_lli, | ||
1312 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1313 | }, | ||
1314 | { | ||
1315 | .number = U300_DMA_GENERAL_PURPOSE_6, | ||
1316 | .name = "GENERAL 06", | ||
1317 | .priority_high = 0, | ||
1318 | |||
1319 | .param.config = flags_memcpy_config, | ||
1320 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1321 | .param.ctrl_lli = flags_memcpy_lli, | ||
1322 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1323 | }, | ||
1324 | { | ||
1325 | .number = U300_DMA_GENERAL_PURPOSE_7, | ||
1326 | .name = "GENERAL 07", | ||
1327 | .priority_high = 0, | ||
1328 | |||
1329 | .param.config = flags_memcpy_config, | ||
1330 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1331 | .param.ctrl_lli = flags_memcpy_lli, | ||
1332 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1333 | }, | ||
1334 | { | ||
1335 | .number = U300_DMA_GENERAL_PURPOSE_8, | ||
1336 | .name = "GENERAL 08", | ||
1337 | .priority_high = 0, | ||
1338 | |||
1339 | .param.config = flags_memcpy_config, | ||
1340 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1341 | .param.ctrl_lli = flags_memcpy_lli, | ||
1342 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1343 | }, | ||
1344 | #ifdef CONFIG_MACH_U300_BS335 | ||
1345 | { | ||
1346 | .number = U300_DMA_UART1_TX, | ||
1347 | .name = "UART1 TX", | ||
1348 | .priority_high = 0, | ||
1349 | }, | ||
1350 | { | ||
1351 | .number = U300_DMA_UART1_RX, | ||
1352 | .name = "UART1 RX", | ||
1353 | .priority_high = 0, | ||
1354 | } | ||
1355 | #else | ||
1356 | { | ||
1357 | .number = U300_DMA_GENERAL_PURPOSE_9, | ||
1358 | .name = "GENERAL 09", | ||
1359 | .priority_high = 0, | ||
1360 | |||
1361 | .param.config = flags_memcpy_config, | ||
1362 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1363 | .param.ctrl_lli = flags_memcpy_lli, | ||
1364 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1365 | }, | ||
1366 | { | ||
1367 | .number = U300_DMA_GENERAL_PURPOSE_10, | ||
1368 | .name = "GENERAL 10", | ||
1369 | .priority_high = 0, | ||
1370 | |||
1371 | .param.config = flags_memcpy_config, | ||
1372 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | ||
1373 | .param.ctrl_lli = flags_memcpy_lli, | ||
1374 | .param.ctrl_lli_last = flags_memcpy_lli_last, | ||
1375 | } | ||
1376 | #endif | ||
1377 | }; | ||
1378 | |||
1379 | |||
1380 | static struct coh901318_platform coh901318_platform = { | ||
1381 | .chans_slave = dma_slave_channels, | ||
1382 | .chans_memcpy = dma_memcpy_channels, | ||
1383 | .access_memory_state = coh901318_access_memory_state, | ||
1384 | .chan_conf = chan_config, | ||
1385 | .max_channels = U300_DMA_CHANNELS, | ||
1386 | }; | ||
1387 | |||
375 | static struct platform_device wdog_device = { | 1388 | static struct platform_device wdog_device = { |
376 | .name = "wdog", | 1389 | .name = "coh901327_wdog", |
377 | .id = -1, | 1390 | .id = -1, |
378 | .num_resources = ARRAY_SIZE(wdog_resources), | 1391 | .num_resources = ARRAY_SIZE(wdog_resources), |
379 | .resource = wdog_resources, | 1392 | .resource = wdog_resources, |
@@ -428,11 +1441,23 @@ static struct platform_device ave_device = { | |||
428 | .resource = ave_resources, | 1441 | .resource = ave_resources, |
429 | }; | 1442 | }; |
430 | 1443 | ||
1444 | static struct platform_device dma_device = { | ||
1445 | .name = "coh901318", | ||
1446 | .id = -1, | ||
1447 | .resource = dma_resource, | ||
1448 | .num_resources = ARRAY_SIZE(dma_resource), | ||
1449 | .dev = { | ||
1450 | .platform_data = &coh901318_platform, | ||
1451 | .coherent_dma_mask = ~0, | ||
1452 | }, | ||
1453 | }; | ||
1454 | |||
431 | /* | 1455 | /* |
432 | * Notice that AMBA devices are initialized before platform devices. | 1456 | * Notice that AMBA devices are initialized before platform devices. |
433 | * | 1457 | * |
434 | */ | 1458 | */ |
435 | static struct platform_device *platform_devs[] __initdata = { | 1459 | static struct platform_device *platform_devs[] __initdata = { |
1460 | &dma_device, | ||
436 | &i2c0_device, | 1461 | &i2c0_device, |
437 | &i2c1_device, | 1462 | &i2c1_device, |
438 | &keypad_device, | 1463 | &keypad_device, |
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c index 0b35826b7d1d..5f61fd45a0c8 100644 --- a/arch/arm/mach-u300/gpio.c +++ b/arch/arm/mach-u300/gpio.c | |||
@@ -546,7 +546,7 @@ static void gpio_set_initial_values(void) | |||
546 | for (i = 0; i < U300_GPIO_MAX; i++) { | 546 | for (i = 0; i < U300_GPIO_MAX; i++) { |
547 | val = 0; | 547 | val = 0; |
548 | for (j = 0; j < 8; j++) | 548 | for (j = 0; j < 8; j++) |
549 | val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j; | 549 | val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j); |
550 | local_irq_save(flags); | 550 | local_irq_save(flags); |
551 | writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); | 551 | writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); |
552 | local_irq_restore(flags); | 552 | local_irq_restore(flags); |
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S index f3a1cbbeeab3..ca4a028c2661 100644 --- a/arch/arm/mach-u300/include/mach/debug-macro.S +++ b/arch/arm/mach-u300/include/mach/debug-macro.S | |||
@@ -10,7 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | #include <mach/hardware.h> | 11 | #include <mach/hardware.h> |
12 | 12 | ||
13 | .macro addruart,rx | 13 | .macro addruart, rx, tmp |
14 | /* If we move the adress using MMU, use this. */ | 14 | /* If we move the adress using MMU, use this. */ |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h new file mode 100644 index 000000000000..b239149ba0d0 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/dma_channels.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * | ||
3 | * arch/arm/mach-u300/include/mach/dma_channels.h | ||
4 | * | ||
5 | * | ||
6 | * Copyright (C) 2007-2009 ST-Ericsson | ||
7 | * License terms: GNU General Public License (GPL) version 2 | ||
8 | * Map file for the U300 dma driver. | ||
9 | * Author: Per Friden <per.friden@stericsson.com> | ||
10 | */ | ||
11 | |||
12 | #ifndef DMA_CHANNELS_H | ||
13 | #define DMA_CHANNELS_H | ||
14 | |||
15 | #define U300_DMA_MSL_TX_0 0 | ||
16 | #define U300_DMA_MSL_TX_1 1 | ||
17 | #define U300_DMA_MSL_TX_2 2 | ||
18 | #define U300_DMA_MSL_TX_3 3 | ||
19 | #define U300_DMA_MSL_TX_4 4 | ||
20 | #define U300_DMA_MSL_TX_5 5 | ||
21 | #define U300_DMA_MSL_TX_6 6 | ||
22 | #define U300_DMA_MSL_RX_0 7 | ||
23 | #define U300_DMA_MSL_RX_1 8 | ||
24 | #define U300_DMA_MSL_RX_2 9 | ||
25 | #define U300_DMA_MSL_RX_3 10 | ||
26 | #define U300_DMA_MSL_RX_4 11 | ||
27 | #define U300_DMA_MSL_RX_5 12 | ||
28 | #define U300_DMA_MSL_RX_6 13 | ||
29 | #define U300_DMA_MMCSD_RX_TX 14 | ||
30 | #define U300_DMA_MSPRO_TX 15 | ||
31 | #define U300_DMA_MSPRO_RX 16 | ||
32 | #define U300_DMA_UART0_TX 17 | ||
33 | #define U300_DMA_UART0_RX 18 | ||
34 | #define U300_DMA_APEX_TX 19 | ||
35 | #define U300_DMA_APEX_RX 20 | ||
36 | #define U300_DMA_PCM_I2S0_TX 21 | ||
37 | #define U300_DMA_PCM_I2S0_RX 22 | ||
38 | #define U300_DMA_PCM_I2S1_TX 23 | ||
39 | #define U300_DMA_PCM_I2S1_RX 24 | ||
40 | #define U300_DMA_XGAM_CDI 25 | ||
41 | #define U300_DMA_XGAM_PDI 26 | ||
42 | #define U300_DMA_SPI_TX 27 | ||
43 | #define U300_DMA_SPI_RX 28 | ||
44 | #define U300_DMA_GENERAL_PURPOSE_0 29 | ||
45 | #define U300_DMA_GENERAL_PURPOSE_1 30 | ||
46 | #define U300_DMA_GENERAL_PURPOSE_2 31 | ||
47 | #define U300_DMA_GENERAL_PURPOSE_3 32 | ||
48 | #define U300_DMA_GENERAL_PURPOSE_4 33 | ||
49 | #define U300_DMA_GENERAL_PURPOSE_5 34 | ||
50 | #define U300_DMA_GENERAL_PURPOSE_6 35 | ||
51 | #define U300_DMA_GENERAL_PURPOSE_7 36 | ||
52 | #define U300_DMA_GENERAL_PURPOSE_8 37 | ||
53 | #ifdef CONFIG_MACH_U300_BS335 | ||
54 | #define U300_DMA_UART1_TX 38 | ||
55 | #define U300_DMA_UART1_RX 39 | ||
56 | #else | ||
57 | #define U300_DMA_GENERAL_PURPOSE_9 38 | ||
58 | #define U300_DMA_GENERAL_PURPOSE_10 39 | ||
59 | #endif | ||
60 | |||
61 | #ifdef CONFIG_MACH_U300_BS335 | ||
62 | #define U300_DMA_DEVICE_CHANNELS 32 | ||
63 | #else | ||
64 | #define U300_DMA_DEVICE_CHANNELS 30 | ||
65 | #endif | ||
66 | #define U300_DMA_CHANNELS 40 | ||
67 | |||
68 | |||
69 | #endif /* DMA_CHANNELS_H */ | ||
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h index b00c51a66fbe..ec423b92b81d 100644 --- a/arch/arm/mach-u300/include/mach/vmalloc.h +++ b/arch/arm/mach-u300/include/mach/vmalloc.h | |||
@@ -9,4 +9,4 @@ | |||
9 | * End must be above the I/O registers and on an even 2MiB boundary. | 9 | * End must be above the I/O registers and on an even 2MiB boundary. |
10 | * Author: Linus Walleij <linus.walleij@stericsson.com> | 10 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
11 | */ | 11 | */ |
12 | #define VMALLOC_END 0xfe800000 | 12 | #define VMALLOC_END 0xfe800000UL |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index aa5afbcc90f9..803aec1d6728 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
23 | 23 | ||
24 | #include <plat/mtu.h> | 24 | #include <plat/mtu.h> |
25 | #include <plat/i2c.h> | ||
25 | 26 | ||
26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
27 | #include <mach/setup.h> | 28 | #include <mach/setup.h> |
@@ -108,11 +109,96 @@ static struct amba_device pl022_device = { | |||
108 | .periphid = SSP_PER_ID, | 109 | .periphid = SSP_PER_ID, |
109 | }; | 110 | }; |
110 | 111 | ||
112 | static struct amba_device pl031_device = { | ||
113 | .dev = { | ||
114 | .init_name = "pl031", | ||
115 | }, | ||
116 | .res = { | ||
117 | .start = U8500_RTC_BASE, | ||
118 | .end = U8500_RTC_BASE + SZ_4K - 1, | ||
119 | .flags = IORESOURCE_MEM, | ||
120 | }, | ||
121 | .irq = {IRQ_RTC_RTT, NO_IRQ}, | ||
122 | }; | ||
123 | |||
124 | #define U8500_I2C_RESOURCES(id, size) \ | ||
125 | static struct resource u8500_i2c_resources_##id[] = { \ | ||
126 | [0] = { \ | ||
127 | .start = U8500_I2C##id##_BASE, \ | ||
128 | .end = U8500_I2C##id##_BASE + size - 1, \ | ||
129 | .flags = IORESOURCE_MEM, \ | ||
130 | }, \ | ||
131 | [1] = { \ | ||
132 | .start = IRQ_I2C##id, \ | ||
133 | .end = IRQ_I2C##id, \ | ||
134 | .flags = IORESOURCE_IRQ \ | ||
135 | } \ | ||
136 | } | ||
137 | |||
138 | U8500_I2C_RESOURCES(0, SZ_4K); | ||
139 | U8500_I2C_RESOURCES(1, SZ_4K); | ||
140 | U8500_I2C_RESOURCES(2, SZ_4K); | ||
141 | U8500_I2C_RESOURCES(3, SZ_4K); | ||
142 | |||
143 | #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ | ||
144 | static struct nmk_i2c_controller u8500_i2c_##id = { \ | ||
145 | /* \ | ||
146 | * slave data setup time, which is \ | ||
147 | * 250 ns,100ns,10ns which is 14,6,2 \ | ||
148 | * respectively for a 48 Mhz \ | ||
149 | * i2c clock \ | ||
150 | */ \ | ||
151 | .slsu = _slsu, \ | ||
152 | /* Tx FIFO threshold */ \ | ||
153 | .tft = _tft, \ | ||
154 | /* Rx FIFO threshold */ \ | ||
155 | .rft = _rft, \ | ||
156 | /* std. mode operation */ \ | ||
157 | .clk_freq = clk, \ | ||
158 | .sm = _sm, \ | ||
159 | } | ||
160 | |||
161 | /* | ||
162 | * The board uses 4 i2c controllers, initialize all of | ||
163 | * them with slave data setup time of 250 ns, | ||
164 | * Tx & Rx FIFO threshold values as 1 and standard | ||
165 | * mode of operation | ||
166 | */ | ||
167 | U8500_I2C_CONTROLLER(0, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | ||
168 | U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | ||
169 | U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | ||
170 | U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | ||
171 | |||
172 | #define U8500_I2C_PDEVICE(cid) \ | ||
173 | static struct platform_device i2c_controller##cid = { \ | ||
174 | .name = "nmk-i2c", \ | ||
175 | .id = cid, \ | ||
176 | .num_resources = 2, \ | ||
177 | .resource = u8500_i2c_resources_##cid, \ | ||
178 | .dev = { \ | ||
179 | .platform_data = &u8500_i2c_##cid \ | ||
180 | } \ | ||
181 | } | ||
182 | |||
183 | U8500_I2C_PDEVICE(0); | ||
184 | U8500_I2C_PDEVICE(1); | ||
185 | U8500_I2C_PDEVICE(2); | ||
186 | U8500_I2C_PDEVICE(3); | ||
187 | |||
111 | static struct amba_device *amba_devs[] __initdata = { | 188 | static struct amba_device *amba_devs[] __initdata = { |
112 | &uart0_device, | 189 | &uart0_device, |
113 | &uart1_device, | 190 | &uart1_device, |
114 | &uart2_device, | 191 | &uart2_device, |
115 | &pl022_device, | 192 | &pl022_device, |
193 | &pl031_device, | ||
194 | }; | ||
195 | |||
196 | /* add any platform devices here - TODO */ | ||
197 | static struct platform_device *platform_devs[] __initdata = { | ||
198 | &i2c_controller0, | ||
199 | &i2c_controller1, | ||
200 | &i2c_controller2, | ||
201 | &i2c_controller3, | ||
116 | }; | 202 | }; |
117 | 203 | ||
118 | static void __init u8500_timer_init(void) | 204 | static void __init u8500_timer_init(void) |
@@ -139,6 +225,8 @@ static void __init u8500_init_machine(void) | |||
139 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) | 225 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) |
140 | amba_device_register(amba_devs[i], &iomem_resource); | 226 | amba_device_register(amba_devs[i], &iomem_resource); |
141 | 227 | ||
228 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); | ||
229 | |||
142 | spi_register_board_info(u8500_spi_devices, | 230 | spi_register_board_info(u8500_spi_devices, |
143 | ARRAY_SIZE(u8500_spi_devices)); | 231 | ARRAY_SIZE(u8500_spi_devices)); |
144 | 232 | ||
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c index 5f05e5850f71..397bc1f9ed94 100644 --- a/arch/arm/mach-ux500/cpu-u8500.c +++ b/arch/arm/mach-ux500/cpu-u8500.c | |||
@@ -33,6 +33,7 @@ static struct platform_device *platform_devs[] __initdata = { | |||
33 | 33 | ||
34 | /* minimum static i/o mapping required to boot U8500 platforms */ | 34 | /* minimum static i/o mapping required to boot U8500 platforms */ |
35 | static struct map_desc u8500_io_desc[] __initdata = { | 35 | static struct map_desc u8500_io_desc[] __initdata = { |
36 | __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), | ||
36 | __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), | 37 | __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), |
37 | __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), | 38 | __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), |
38 | __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), | 39 | __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), |
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 8f21b6a95dce..09cbfda8aee5 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S | |||
@@ -8,12 +8,13 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | * | 9 | * |
10 | */ | 10 | */ |
11 | .macro addruart,rx | 11 | #include <mach/hardware.h> |
12 | |||
13 | .macro addruart, rx, tmp | ||
12 | mrc p15, 0, \rx, c1, c0 | 14 | mrc p15, 0, \rx, c1, c0 |
13 | tst \rx, #1 @MMU enabled? | 15 | tst \rx, #1 @ MMU enabled? |
14 | moveq \rx, #0x80000000 @MMU off, Physical address | 16 | ldreq \rx, =U8500_UART2_BASE @ no, physical address |
15 | movne \rx, #0xF0000000 @MMU on, Virtual address | 17 | ldrne \rx, =IO_ADDRESS(U8500_UART2_BASE) @ yes, virtual address |
16 | orr \rx, \rx, #0x7000 | ||
17 | .endm | 18 | .endm |
18 | 19 | ||
19 | #include <asm/hardware/debug-pl01x.S> | 20 | #include <asm/hardware/debug-pl01x.S> |
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h index 86cdbbce1842..a4945cb41172 100644 --- a/arch/arm/mach-ux500/include/mach/vmalloc.h +++ b/arch/arm/mach-ux500/include/mach/vmalloc.h | |||
@@ -15,4 +15,4 @@ | |||
15 | * along with this program; if not, write to the Free Software | 15 | * along with this program; if not, write to the Free Software |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
17 | */ | 17 | */ |
18 | #define VMALLOC_END 0xf0000000 | 18 | #define VMALLOC_END 0xf0000000UL |
diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S index b4ac00eacf68..6fea7199c626 100644 --- a/arch/arm/mach-versatile/include/mach/debug-macro.S +++ b/arch/arm/mach-versatile/include/mach/debug-macro.S | |||
@@ -11,7 +11,7 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | .macro addruart,rx | 14 | .macro addruart, rx, tmp |
15 | mrc p15, 0, \rx, c1, c0 | 15 | mrc p15, 0, \rx, c1, c0 |
16 | tst \rx, #1 @ MMU enabled? | 16 | tst \rx, #1 @ MMU enabled? |
17 | moveq \rx, #0x10000000 | 17 | moveq \rx, #0x10000000 |
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c index 6f5ca532883f..642207e18198 100644 --- a/arch/arm/mach-w90x900/cpu.c +++ b/arch/arm/mach-w90x900/cpu.c | |||
@@ -45,6 +45,7 @@ static struct map_desc nuc900_iodesc[] __initdata = { | |||
45 | IODESC_ENT(UART), | 45 | IODESC_ENT(UART), |
46 | IODESC_ENT(TIMER), | 46 | IODESC_ENT(TIMER), |
47 | IODESC_ENT(EBI), | 47 | IODESC_ENT(EBI), |
48 | IODESC_ENT(GPIO), | ||
48 | }; | 49 | }; |
49 | 50 | ||
50 | /* Initial clock declarations. */ | 51 | /* Initial clock declarations. */ |
@@ -68,6 +69,11 @@ static DEFINE_CLK(gdma, 27); | |||
68 | static DEFINE_CLK(adc, 28); | 69 | static DEFINE_CLK(adc, 28); |
69 | static DEFINE_CLK(usi, 29); | 70 | static DEFINE_CLK(usi, 29); |
70 | static DEFINE_CLK(ext, 0); | 71 | static DEFINE_CLK(ext, 0); |
72 | static DEFINE_CLK(timer0, 19); | ||
73 | static DEFINE_CLK(timer1, 20); | ||
74 | static DEFINE_CLK(timer2, 21); | ||
75 | static DEFINE_CLK(timer3, 22); | ||
76 | static DEFINE_CLK(timer4, 23); | ||
71 | 77 | ||
72 | static struct clk_lookup nuc900_clkregs[] = { | 78 | static struct clk_lookup nuc900_clkregs[] = { |
73 | DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL), | 79 | DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL), |
@@ -90,6 +96,11 @@ static struct clk_lookup nuc900_clkregs[] = { | |||
90 | DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL), | 96 | DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL), |
91 | DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL), | 97 | DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL), |
92 | DEF_CLKLOOK(&clk_ext, NULL, "ext"), | 98 | DEF_CLKLOOK(&clk_ext, NULL, "ext"), |
99 | DEF_CLKLOOK(&clk_timer0, NULL, "timer0"), | ||
100 | DEF_CLKLOOK(&clk_timer1, NULL, "timer1"), | ||
101 | DEF_CLKLOOK(&clk_timer2, NULL, "timer2"), | ||
102 | DEF_CLKLOOK(&clk_timer3, NULL, "timer3"), | ||
103 | DEF_CLKLOOK(&clk_timer4, NULL, "timer4"), | ||
93 | }; | 104 | }; |
94 | 105 | ||
95 | /* Initial serial platform data */ | 106 | /* Initial serial platform data */ |
diff --git a/arch/arm/mach-w90x900/include/mach/vmalloc.h b/arch/arm/mach-w90x900/include/mach/vmalloc.h index 2f9dfb928533..b067e44500a4 100644 --- a/arch/arm/mach-w90x900/include/mach/vmalloc.h +++ b/arch/arm/mach-w90x900/include/mach/vmalloc.h | |||
@@ -18,6 +18,6 @@ | |||
18 | #ifndef __ASM_ARCH_VMALLOC_H | 18 | #ifndef __ASM_ARCH_VMALLOC_H |
19 | #define __ASM_ARCH_VMALLOC_H | 19 | #define __ASM_ARCH_VMALLOC_H |
20 | 20 | ||
21 | #define VMALLOC_END (0xE0000000) | 21 | #define VMALLOC_END (0xe0000000UL) |
22 | 22 | ||
23 | #endif /* __ASM_ARCH_VMALLOC_H */ | 23 | #endif /* __ASM_ARCH_VMALLOC_H */ |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index baf638487a2d..c4ed9f93f646 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -399,7 +399,7 @@ config CPU_V6 | |||
399 | config CPU_32v6K | 399 | config CPU_32v6K |
400 | bool "Support ARM V6K processor extensions" if !SMP | 400 | bool "Support ARM V6K processor extensions" if !SMP |
401 | depends on CPU_V6 | 401 | depends on CPU_V6 |
402 | default y if SMP && !ARCH_MX3 | 402 | default y if SMP && !(ARCH_MX3 || ARCH_OMAP2) |
403 | help | 403 | help |
404 | Say Y here if your ARMv6 processor supports the 'K' extension. | 404 | Say Y here if your ARMv6 processor supports the 'K' extension. |
405 | This enables the kernel to use some instructions not present | 405 | This enables the kernel to use some instructions not present |
@@ -410,7 +410,7 @@ config CPU_32v6K | |||
410 | # ARMv7 | 410 | # ARMv7 |
411 | config CPU_V7 | 411 | config CPU_V7 |
412 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX | 412 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
413 | select CPU_32v6K | 413 | select CPU_32v6K if !ARCH_OMAP2 |
414 | select CPU_32v7 | 414 | select CPU_32v7 |
415 | select CPU_ABRT_EV7 | 415 | select CPU_ABRT_EV7 |
416 | select CPU_PABRT_V7 | 416 | select CPU_PABRT_V7 |
@@ -754,7 +754,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH | |||
754 | config CACHE_L2X0 | 754 | config CACHE_L2X0 |
755 | bool "Enable the L2x0 outer cache controller" | 755 | bool "Enable the L2x0 outer cache controller" |
756 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ | 756 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
757 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK | 757 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 |
758 | default y | 758 | default y |
759 | select OUTER_CACHE | 759 | select OUTER_CACHE |
760 | help | 760 | help |
@@ -779,5 +779,5 @@ config CACHE_XSC3L2 | |||
779 | 779 | ||
780 | config ARM_L1_CACHE_SHIFT | 780 | config ARM_L1_CACHE_SHIFT |
781 | int | 781 | int |
782 | default 6 if ARCH_OMAP3 || ARCH_S5PC1XX | 782 | default 6 if ARM_L1_CACHE_SHIFT_6 |
783 | default 5 | 783 | default 5 |
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index b270d6228fe2..0c5eb6983cef 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c | |||
@@ -898,11 +898,7 @@ static int __init alignment_init(void) | |||
898 | #ifdef CONFIG_PROC_FS | 898 | #ifdef CONFIG_PROC_FS |
899 | struct proc_dir_entry *res; | 899 | struct proc_dir_entry *res; |
900 | 900 | ||
901 | res = proc_mkdir("cpu", NULL); | 901 | res = create_proc_entry("cpu/alignment", S_IWUSR | S_IRUGO, NULL); |
902 | if (!res) | ||
903 | return -ENOMEM; | ||
904 | |||
905 | res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res); | ||
906 | if (!res) | 902 | if (!res) |
907 | return -ENOMEM; | 903 | return -ENOMEM; |
908 | 904 | ||
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S index a89444a3c016..7148e53e6078 100644 --- a/arch/arm/mm/cache-fa.S +++ b/arch/arm/mm/cache-fa.S | |||
@@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area) | |||
157 | * - start - virtual start address | 157 | * - start - virtual start address |
158 | * - end - virtual end address | 158 | * - end - virtual end address |
159 | */ | 159 | */ |
160 | ENTRY(fa_dma_inv_range) | 160 | fa_dma_inv_range: |
161 | tst r0, #CACHE_DLINESIZE - 1 | 161 | tst r0, #CACHE_DLINESIZE - 1 |
162 | bic r0, r0, #CACHE_DLINESIZE - 1 | 162 | bic r0, r0, #CACHE_DLINESIZE - 1 |
163 | mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry | 163 | mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry |
@@ -180,7 +180,7 @@ ENTRY(fa_dma_inv_range) | |||
180 | * - start - virtual start address | 180 | * - start - virtual start address |
181 | * - end - virtual end address | 181 | * - end - virtual end address |
182 | */ | 182 | */ |
183 | ENTRY(fa_dma_clean_range) | 183 | fa_dma_clean_range: |
184 | bic r0, r0, #CACHE_DLINESIZE - 1 | 184 | bic r0, r0, #CACHE_DLINESIZE - 1 |
185 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 185 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
186 | add r0, r0, #CACHE_DLINESIZE | 186 | add r0, r0, #CACHE_DLINESIZE |
@@ -205,6 +205,30 @@ ENTRY(fa_dma_flush_range) | |||
205 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | 205 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
206 | mov pc, lr | 206 | mov pc, lr |
207 | 207 | ||
208 | /* | ||
209 | * dma_map_area(start, size, dir) | ||
210 | * - start - kernel virtual start address | ||
211 | * - size - size of region | ||
212 | * - dir - DMA direction | ||
213 | */ | ||
214 | ENTRY(fa_dma_map_area) | ||
215 | add r1, r1, r0 | ||
216 | cmp r2, #DMA_TO_DEVICE | ||
217 | beq fa_dma_clean_range | ||
218 | bcs fa_dma_inv_range | ||
219 | b fa_dma_flush_range | ||
220 | ENDPROC(fa_dma_map_area) | ||
221 | |||
222 | /* | ||
223 | * dma_unmap_area(start, size, dir) | ||
224 | * - start - kernel virtual start address | ||
225 | * - size - size of region | ||
226 | * - dir - DMA direction | ||
227 | */ | ||
228 | ENTRY(fa_dma_unmap_area) | ||
229 | mov pc, lr | ||
230 | ENDPROC(fa_dma_unmap_area) | ||
231 | |||
208 | __INITDATA | 232 | __INITDATA |
209 | 233 | ||
210 | .type fa_cache_fns, #object | 234 | .type fa_cache_fns, #object |
@@ -215,7 +239,7 @@ ENTRY(fa_cache_fns) | |||
215 | .long fa_coherent_kern_range | 239 | .long fa_coherent_kern_range |
216 | .long fa_coherent_user_range | 240 | .long fa_coherent_user_range |
217 | .long fa_flush_kern_dcache_area | 241 | .long fa_flush_kern_dcache_area |
218 | .long fa_dma_inv_range | 242 | .long fa_dma_map_area |
219 | .long fa_dma_clean_range | 243 | .long fa_dma_unmap_area |
220 | .long fa_dma_flush_range | 244 | .long fa_dma_flush_range |
221 | .size fa_cache_fns, . - fa_cache_fns | 245 | .size fa_cache_fns, . - fa_cache_fns |
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index cb8fc6573b1b..07334632d3e2 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -42,6 +42,57 @@ static inline void cache_sync(void) | |||
42 | cache_wait(base + L2X0_CACHE_SYNC, 1); | 42 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
43 | } | 43 | } |
44 | 44 | ||
45 | static inline void l2x0_clean_line(unsigned long addr) | ||
46 | { | ||
47 | void __iomem *base = l2x0_base; | ||
48 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
49 | writel(addr, base + L2X0_CLEAN_LINE_PA); | ||
50 | } | ||
51 | |||
52 | static inline void l2x0_inv_line(unsigned long addr) | ||
53 | { | ||
54 | void __iomem *base = l2x0_base; | ||
55 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
56 | writel(addr, base + L2X0_INV_LINE_PA); | ||
57 | } | ||
58 | |||
59 | #ifdef CONFIG_PL310_ERRATA_588369 | ||
60 | static void debug_writel(unsigned long val) | ||
61 | { | ||
62 | extern void omap_smc1(u32 fn, u32 arg); | ||
63 | |||
64 | /* | ||
65 | * Texas Instrument secure monitor api to modify the | ||
66 | * PL310 Debug Control Register. | ||
67 | */ | ||
68 | omap_smc1(0x100, val); | ||
69 | } | ||
70 | |||
71 | static inline void l2x0_flush_line(unsigned long addr) | ||
72 | { | ||
73 | void __iomem *base = l2x0_base; | ||
74 | |||
75 | /* Clean by PA followed by Invalidate by PA */ | ||
76 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
77 | writel(addr, base + L2X0_CLEAN_LINE_PA); | ||
78 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
79 | writel(addr, base + L2X0_INV_LINE_PA); | ||
80 | } | ||
81 | #else | ||
82 | |||
83 | /* Optimised out for non-errata case */ | ||
84 | static inline void debug_writel(unsigned long val) | ||
85 | { | ||
86 | } | ||
87 | |||
88 | static inline void l2x0_flush_line(unsigned long addr) | ||
89 | { | ||
90 | void __iomem *base = l2x0_base; | ||
91 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | ||
92 | writel(addr, base + L2X0_CLEAN_INV_LINE_PA); | ||
93 | } | ||
94 | #endif | ||
95 | |||
45 | static inline void l2x0_inv_all(void) | 96 | static inline void l2x0_inv_all(void) |
46 | { | 97 | { |
47 | unsigned long flags; | 98 | unsigned long flags; |
@@ -62,23 +113,24 @@ static void l2x0_inv_range(unsigned long start, unsigned long end) | |||
62 | spin_lock_irqsave(&l2x0_lock, flags); | 113 | spin_lock_irqsave(&l2x0_lock, flags); |
63 | if (start & (CACHE_LINE_SIZE - 1)) { | 114 | if (start & (CACHE_LINE_SIZE - 1)) { |
64 | start &= ~(CACHE_LINE_SIZE - 1); | 115 | start &= ~(CACHE_LINE_SIZE - 1); |
65 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 116 | debug_writel(0x03); |
66 | writel(start, base + L2X0_CLEAN_INV_LINE_PA); | 117 | l2x0_flush_line(start); |
118 | debug_writel(0x00); | ||
67 | start += CACHE_LINE_SIZE; | 119 | start += CACHE_LINE_SIZE; |
68 | } | 120 | } |
69 | 121 | ||
70 | if (end & (CACHE_LINE_SIZE - 1)) { | 122 | if (end & (CACHE_LINE_SIZE - 1)) { |
71 | end &= ~(CACHE_LINE_SIZE - 1); | 123 | end &= ~(CACHE_LINE_SIZE - 1); |
72 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 124 | debug_writel(0x03); |
73 | writel(end, base + L2X0_CLEAN_INV_LINE_PA); | 125 | l2x0_flush_line(end); |
126 | debug_writel(0x00); | ||
74 | } | 127 | } |
75 | 128 | ||
76 | while (start < end) { | 129 | while (start < end) { |
77 | unsigned long blk_end = start + min(end - start, 4096UL); | 130 | unsigned long blk_end = start + min(end - start, 4096UL); |
78 | 131 | ||
79 | while (start < blk_end) { | 132 | while (start < blk_end) { |
80 | cache_wait(base + L2X0_INV_LINE_PA, 1); | 133 | l2x0_inv_line(start); |
81 | writel(start, base + L2X0_INV_LINE_PA); | ||
82 | start += CACHE_LINE_SIZE; | 134 | start += CACHE_LINE_SIZE; |
83 | } | 135 | } |
84 | 136 | ||
@@ -103,8 +155,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) | |||
103 | unsigned long blk_end = start + min(end - start, 4096UL); | 155 | unsigned long blk_end = start + min(end - start, 4096UL); |
104 | 156 | ||
105 | while (start < blk_end) { | 157 | while (start < blk_end) { |
106 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | 158 | l2x0_clean_line(start); |
107 | writel(start, base + L2X0_CLEAN_LINE_PA); | ||
108 | start += CACHE_LINE_SIZE; | 159 | start += CACHE_LINE_SIZE; |
109 | } | 160 | } |
110 | 161 | ||
@@ -128,11 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) | |||
128 | while (start < end) { | 179 | while (start < end) { |
129 | unsigned long blk_end = start + min(end - start, 4096UL); | 180 | unsigned long blk_end = start + min(end - start, 4096UL); |
130 | 181 | ||
182 | debug_writel(0x03); | ||
131 | while (start < blk_end) { | 183 | while (start < blk_end) { |
132 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 184 | l2x0_flush_line(start); |
133 | writel(start, base + L2X0_CLEAN_INV_LINE_PA); | ||
134 | start += CACHE_LINE_SIZE; | 185 | start += CACHE_LINE_SIZE; |
135 | } | 186 | } |
187 | debug_writel(0x00); | ||
136 | 188 | ||
137 | if (blk_end < end) { | 189 | if (blk_end < end) { |
138 | spin_unlock_irqrestore(&l2x0_lock, flags); | 190 | spin_unlock_irqrestore(&l2x0_lock, flags); |
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S index 2a482731ea36..c2ff3c599fee 100644 --- a/arch/arm/mm/cache-v3.S +++ b/arch/arm/mm/cache-v3.S | |||
@@ -84,20 +84,6 @@ ENTRY(v3_flush_kern_dcache_area) | |||
84 | /* FALLTHROUGH */ | 84 | /* FALLTHROUGH */ |
85 | 85 | ||
86 | /* | 86 | /* |
87 | * dma_inv_range(start, end) | ||
88 | * | ||
89 | * Invalidate (discard) the specified virtual address range. | ||
90 | * May not write back any entries. If 'start' or 'end' | ||
91 | * are not cache line aligned, those lines must be written | ||
92 | * back. | ||
93 | * | ||
94 | * - start - virtual start address | ||
95 | * - end - virtual end address | ||
96 | */ | ||
97 | ENTRY(v3_dma_inv_range) | ||
98 | /* FALLTHROUGH */ | ||
99 | |||
100 | /* | ||
101 | * dma_flush_range(start, end) | 87 | * dma_flush_range(start, end) |
102 | * | 88 | * |
103 | * Clean and invalidate the specified virtual address range. | 89 | * Clean and invalidate the specified virtual address range. |
@@ -108,18 +94,29 @@ ENTRY(v3_dma_inv_range) | |||
108 | ENTRY(v3_dma_flush_range) | 94 | ENTRY(v3_dma_flush_range) |
109 | mov r0, #0 | 95 | mov r0, #0 |
110 | mcr p15, 0, r0, c7, c0, 0 @ flush ID cache | 96 | mcr p15, 0, r0, c7, c0, 0 @ flush ID cache |
97 | mov pc, lr | ||
98 | |||
99 | /* | ||
100 | * dma_unmap_area(start, size, dir) | ||
101 | * - start - kernel virtual start address | ||
102 | * - size - size of region | ||
103 | * - dir - DMA direction | ||
104 | */ | ||
105 | ENTRY(v3_dma_unmap_area) | ||
106 | teq r2, #DMA_TO_DEVICE | ||
107 | bne v3_dma_flush_range | ||
111 | /* FALLTHROUGH */ | 108 | /* FALLTHROUGH */ |
112 | 109 | ||
113 | /* | 110 | /* |
114 | * dma_clean_range(start, end) | 111 | * dma_map_area(start, size, dir) |
115 | * | 112 | * - start - kernel virtual start address |
116 | * Clean (write back) the specified virtual address range. | 113 | * - size - size of region |
117 | * | 114 | * - dir - DMA direction |
118 | * - start - virtual start address | ||
119 | * - end - virtual end address | ||
120 | */ | 115 | */ |
121 | ENTRY(v3_dma_clean_range) | 116 | ENTRY(v3_dma_map_area) |
122 | mov pc, lr | 117 | mov pc, lr |
118 | ENDPROC(v3_dma_unmap_area) | ||
119 | ENDPROC(v3_dma_map_area) | ||
123 | 120 | ||
124 | __INITDATA | 121 | __INITDATA |
125 | 122 | ||
@@ -131,7 +128,7 @@ ENTRY(v3_cache_fns) | |||
131 | .long v3_coherent_kern_range | 128 | .long v3_coherent_kern_range |
132 | .long v3_coherent_user_range | 129 | .long v3_coherent_user_range |
133 | .long v3_flush_kern_dcache_area | 130 | .long v3_flush_kern_dcache_area |
134 | .long v3_dma_inv_range | 131 | .long v3_dma_map_area |
135 | .long v3_dma_clean_range | 132 | .long v3_dma_unmap_area |
136 | .long v3_dma_flush_range | 133 | .long v3_dma_flush_range |
137 | .size v3_cache_fns, . - v3_cache_fns | 134 | .size v3_cache_fns, . - v3_cache_fns |
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 5c7da3e372e9..4810f7e3e813 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S | |||
@@ -94,20 +94,6 @@ ENTRY(v4_flush_kern_dcache_area) | |||
94 | /* FALLTHROUGH */ | 94 | /* FALLTHROUGH */ |
95 | 95 | ||
96 | /* | 96 | /* |
97 | * dma_inv_range(start, end) | ||
98 | * | ||
99 | * Invalidate (discard) the specified virtual address range. | ||
100 | * May not write back any entries. If 'start' or 'end' | ||
101 | * are not cache line aligned, those lines must be written | ||
102 | * back. | ||
103 | * | ||
104 | * - start - virtual start address | ||
105 | * - end - virtual end address | ||
106 | */ | ||
107 | ENTRY(v4_dma_inv_range) | ||
108 | /* FALLTHROUGH */ | ||
109 | |||
110 | /* | ||
111 | * dma_flush_range(start, end) | 97 | * dma_flush_range(start, end) |
112 | * | 98 | * |
113 | * Clean and invalidate the specified virtual address range. | 99 | * Clean and invalidate the specified virtual address range. |
@@ -120,18 +106,29 @@ ENTRY(v4_dma_flush_range) | |||
120 | mov r0, #0 | 106 | mov r0, #0 |
121 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | 107 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache |
122 | #endif | 108 | #endif |
109 | mov pc, lr | ||
110 | |||
111 | /* | ||
112 | * dma_unmap_area(start, size, dir) | ||
113 | * - start - kernel virtual start address | ||
114 | * - size - size of region | ||
115 | * - dir - DMA direction | ||
116 | */ | ||
117 | ENTRY(v4_dma_unmap_area) | ||
118 | teq r2, #DMA_TO_DEVICE | ||
119 | bne v4_dma_flush_range | ||
123 | /* FALLTHROUGH */ | 120 | /* FALLTHROUGH */ |
124 | 121 | ||
125 | /* | 122 | /* |
126 | * dma_clean_range(start, end) | 123 | * dma_map_area(start, size, dir) |
127 | * | 124 | * - start - kernel virtual start address |
128 | * Clean (write back) the specified virtual address range. | 125 | * - size - size of region |
129 | * | 126 | * - dir - DMA direction |
130 | * - start - virtual start address | ||
131 | * - end - virtual end address | ||
132 | */ | 127 | */ |
133 | ENTRY(v4_dma_clean_range) | 128 | ENTRY(v4_dma_map_area) |
134 | mov pc, lr | 129 | mov pc, lr |
130 | ENDPROC(v4_dma_unmap_area) | ||
131 | ENDPROC(v4_dma_map_area) | ||
135 | 132 | ||
136 | __INITDATA | 133 | __INITDATA |
137 | 134 | ||
@@ -143,7 +140,7 @@ ENTRY(v4_cache_fns) | |||
143 | .long v4_coherent_kern_range | 140 | .long v4_coherent_kern_range |
144 | .long v4_coherent_user_range | 141 | .long v4_coherent_user_range |
145 | .long v4_flush_kern_dcache_area | 142 | .long v4_flush_kern_dcache_area |
146 | .long v4_dma_inv_range | 143 | .long v4_dma_map_area |
147 | .long v4_dma_clean_range | 144 | .long v4_dma_unmap_area |
148 | .long v4_dma_flush_range | 145 | .long v4_dma_flush_range |
149 | .size v4_cache_fns, . - v4_cache_fns | 146 | .size v4_cache_fns, . - v4_cache_fns |
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 3dbedf1ec0e7..df8368afa102 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S | |||
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range) | |||
173 | * - start - virtual start address | 173 | * - start - virtual start address |
174 | * - end - virtual end address | 174 | * - end - virtual end address |
175 | */ | 175 | */ |
176 | ENTRY(v4wb_dma_inv_range) | 176 | v4wb_dma_inv_range: |
177 | tst r0, #CACHE_DLINESIZE - 1 | 177 | tst r0, #CACHE_DLINESIZE - 1 |
178 | bic r0, r0, #CACHE_DLINESIZE - 1 | 178 | bic r0, r0, #CACHE_DLINESIZE - 1 |
179 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 179 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -194,7 +194,7 @@ ENTRY(v4wb_dma_inv_range) | |||
194 | * - start - virtual start address | 194 | * - start - virtual start address |
195 | * - end - virtual end address | 195 | * - end - virtual end address |
196 | */ | 196 | */ |
197 | ENTRY(v4wb_dma_clean_range) | 197 | v4wb_dma_clean_range: |
198 | bic r0, r0, #CACHE_DLINESIZE - 1 | 198 | bic r0, r0, #CACHE_DLINESIZE - 1 |
199 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 199 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
200 | add r0, r0, #CACHE_DLINESIZE | 200 | add r0, r0, #CACHE_DLINESIZE |
@@ -216,6 +216,30 @@ ENTRY(v4wb_dma_clean_range) | |||
216 | .globl v4wb_dma_flush_range | 216 | .globl v4wb_dma_flush_range |
217 | .set v4wb_dma_flush_range, v4wb_coherent_kern_range | 217 | .set v4wb_dma_flush_range, v4wb_coherent_kern_range |
218 | 218 | ||
219 | /* | ||
220 | * dma_map_area(start, size, dir) | ||
221 | * - start - kernel virtual start address | ||
222 | * - size - size of region | ||
223 | * - dir - DMA direction | ||
224 | */ | ||
225 | ENTRY(v4wb_dma_map_area) | ||
226 | add r1, r1, r0 | ||
227 | cmp r2, #DMA_TO_DEVICE | ||
228 | beq v4wb_dma_clean_range | ||
229 | bcs v4wb_dma_inv_range | ||
230 | b v4wb_dma_flush_range | ||
231 | ENDPROC(v4wb_dma_map_area) | ||
232 | |||
233 | /* | ||
234 | * dma_unmap_area(start, size, dir) | ||
235 | * - start - kernel virtual start address | ||
236 | * - size - size of region | ||
237 | * - dir - DMA direction | ||
238 | */ | ||
239 | ENTRY(v4wb_dma_unmap_area) | ||
240 | mov pc, lr | ||
241 | ENDPROC(v4wb_dma_unmap_area) | ||
242 | |||
219 | __INITDATA | 243 | __INITDATA |
220 | 244 | ||
221 | .type v4wb_cache_fns, #object | 245 | .type v4wb_cache_fns, #object |
@@ -226,7 +250,7 @@ ENTRY(v4wb_cache_fns) | |||
226 | .long v4wb_coherent_kern_range | 250 | .long v4wb_coherent_kern_range |
227 | .long v4wb_coherent_user_range | 251 | .long v4wb_coherent_user_range |
228 | .long v4wb_flush_kern_dcache_area | 252 | .long v4wb_flush_kern_dcache_area |
229 | .long v4wb_dma_inv_range | 253 | .long v4wb_dma_map_area |
230 | .long v4wb_dma_clean_range | 254 | .long v4wb_dma_unmap_area |
231 | .long v4wb_dma_flush_range | 255 | .long v4wb_dma_flush_range |
232 | .size v4wb_cache_fns, . - v4wb_cache_fns | 256 | .size v4wb_cache_fns, . - v4wb_cache_fns |
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index b3b7410270b4..45c70312f43b 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S | |||
@@ -142,23 +142,12 @@ ENTRY(v4wt_flush_kern_dcache_area) | |||
142 | * - start - virtual start address | 142 | * - start - virtual start address |
143 | * - end - virtual end address | 143 | * - end - virtual end address |
144 | */ | 144 | */ |
145 | ENTRY(v4wt_dma_inv_range) | 145 | v4wt_dma_inv_range: |
146 | bic r0, r0, #CACHE_DLINESIZE - 1 | 146 | bic r0, r0, #CACHE_DLINESIZE - 1 |
147 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | 147 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
148 | add r0, r0, #CACHE_DLINESIZE | 148 | add r0, r0, #CACHE_DLINESIZE |
149 | cmp r0, r1 | 149 | cmp r0, r1 |
150 | blo 1b | 150 | blo 1b |
151 | /* FALLTHROUGH */ | ||
152 | |||
153 | /* | ||
154 | * dma_clean_range(start, end) | ||
155 | * | ||
156 | * Clean the specified virtual address range. | ||
157 | * | ||
158 | * - start - virtual start address | ||
159 | * - end - virtual end address | ||
160 | */ | ||
161 | ENTRY(v4wt_dma_clean_range) | ||
162 | mov pc, lr | 151 | mov pc, lr |
163 | 152 | ||
164 | /* | 153 | /* |
@@ -172,6 +161,29 @@ ENTRY(v4wt_dma_clean_range) | |||
172 | .globl v4wt_dma_flush_range | 161 | .globl v4wt_dma_flush_range |
173 | .equ v4wt_dma_flush_range, v4wt_dma_inv_range | 162 | .equ v4wt_dma_flush_range, v4wt_dma_inv_range |
174 | 163 | ||
164 | /* | ||
165 | * dma_unmap_area(start, size, dir) | ||
166 | * - start - kernel virtual start address | ||
167 | * - size - size of region | ||
168 | * - dir - DMA direction | ||
169 | */ | ||
170 | ENTRY(v4wt_dma_unmap_area) | ||
171 | add r1, r1, r0 | ||
172 | teq r2, #DMA_TO_DEVICE | ||
173 | bne v4wt_dma_inv_range | ||
174 | /* FALLTHROUGH */ | ||
175 | |||
176 | /* | ||
177 | * dma_map_area(start, size, dir) | ||
178 | * - start - kernel virtual start address | ||
179 | * - size - size of region | ||
180 | * - dir - DMA direction | ||
181 | */ | ||
182 | ENTRY(v4wt_dma_map_area) | ||
183 | mov pc, lr | ||
184 | ENDPROC(v4wt_dma_unmap_area) | ||
185 | ENDPROC(v4wt_dma_map_area) | ||
186 | |||
175 | __INITDATA | 187 | __INITDATA |
176 | 188 | ||
177 | .type v4wt_cache_fns, #object | 189 | .type v4wt_cache_fns, #object |
@@ -182,7 +194,7 @@ ENTRY(v4wt_cache_fns) | |||
182 | .long v4wt_coherent_kern_range | 194 | .long v4wt_coherent_kern_range |
183 | .long v4wt_coherent_user_range | 195 | .long v4wt_coherent_user_range |
184 | .long v4wt_flush_kern_dcache_area | 196 | .long v4wt_flush_kern_dcache_area |
185 | .long v4wt_dma_inv_range | 197 | .long v4wt_dma_map_area |
186 | .long v4wt_dma_clean_range | 198 | .long v4wt_dma_unmap_area |
187 | .long v4wt_dma_flush_range | 199 | .long v4wt_dma_flush_range |
188 | .size v4wt_cache_fns, . - v4wt_cache_fns | 200 | .size v4wt_cache_fns, . - v4wt_cache_fns |
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 4ba0a24ce6f5..9d89c67a1cc3 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S | |||
@@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area) | |||
195 | * - start - virtual start address of region | 195 | * - start - virtual start address of region |
196 | * - end - virtual end address of region | 196 | * - end - virtual end address of region |
197 | */ | 197 | */ |
198 | ENTRY(v6_dma_inv_range) | 198 | v6_dma_inv_range: |
199 | tst r0, #D_CACHE_LINE_SIZE - 1 | 199 | tst r0, #D_CACHE_LINE_SIZE - 1 |
200 | bic r0, r0, #D_CACHE_LINE_SIZE - 1 | 200 | bic r0, r0, #D_CACHE_LINE_SIZE - 1 |
201 | #ifdef HARVARD_CACHE | 201 | #ifdef HARVARD_CACHE |
@@ -228,7 +228,7 @@ ENTRY(v6_dma_inv_range) | |||
228 | * - start - virtual start address of region | 228 | * - start - virtual start address of region |
229 | * - end - virtual end address of region | 229 | * - end - virtual end address of region |
230 | */ | 230 | */ |
231 | ENTRY(v6_dma_clean_range) | 231 | v6_dma_clean_range: |
232 | bic r0, r0, #D_CACHE_LINE_SIZE - 1 | 232 | bic r0, r0, #D_CACHE_LINE_SIZE - 1 |
233 | 1: | 233 | 1: |
234 | #ifdef HARVARD_CACHE | 234 | #ifdef HARVARD_CACHE |
@@ -263,6 +263,32 @@ ENTRY(v6_dma_flush_range) | |||
263 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | 263 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
264 | mov pc, lr | 264 | mov pc, lr |
265 | 265 | ||
266 | /* | ||
267 | * dma_map_area(start, size, dir) | ||
268 | * - start - kernel virtual start address | ||
269 | * - size - size of region | ||
270 | * - dir - DMA direction | ||
271 | */ | ||
272 | ENTRY(v6_dma_map_area) | ||
273 | add r1, r1, r0 | ||
274 | teq r2, #DMA_FROM_DEVICE | ||
275 | beq v6_dma_inv_range | ||
276 | b v6_dma_clean_range | ||
277 | ENDPROC(v6_dma_map_area) | ||
278 | |||
279 | /* | ||
280 | * dma_unmap_area(start, size, dir) | ||
281 | * - start - kernel virtual start address | ||
282 | * - size - size of region | ||
283 | * - dir - DMA direction | ||
284 | */ | ||
285 | ENTRY(v6_dma_unmap_area) | ||
286 | add r1, r1, r0 | ||
287 | teq r2, #DMA_TO_DEVICE | ||
288 | bne v6_dma_inv_range | ||
289 | mov pc, lr | ||
290 | ENDPROC(v6_dma_unmap_area) | ||
291 | |||
266 | __INITDATA | 292 | __INITDATA |
267 | 293 | ||
268 | .type v6_cache_fns, #object | 294 | .type v6_cache_fns, #object |
@@ -273,7 +299,7 @@ ENTRY(v6_cache_fns) | |||
273 | .long v6_coherent_kern_range | 299 | .long v6_coherent_kern_range |
274 | .long v6_coherent_user_range | 300 | .long v6_coherent_user_range |
275 | .long v6_flush_kern_dcache_area | 301 | .long v6_flush_kern_dcache_area |
276 | .long v6_dma_inv_range | 302 | .long v6_dma_map_area |
277 | .long v6_dma_clean_range | 303 | .long v6_dma_unmap_area |
278 | .long v6_dma_flush_range | 304 | .long v6_dma_flush_range |
279 | .size v6_cache_fns, . - v6_cache_fns | 305 | .size v6_cache_fns, . - v6_cache_fns |
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 9073db849fb4..bcd64f265870 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S | |||
@@ -216,7 +216,7 @@ ENDPROC(v7_flush_kern_dcache_area) | |||
216 | * - start - virtual start address of region | 216 | * - start - virtual start address of region |
217 | * - end - virtual end address of region | 217 | * - end - virtual end address of region |
218 | */ | 218 | */ |
219 | ENTRY(v7_dma_inv_range) | 219 | v7_dma_inv_range: |
220 | dcache_line_size r2, r3 | 220 | dcache_line_size r2, r3 |
221 | sub r3, r2, #1 | 221 | sub r3, r2, #1 |
222 | tst r0, r3 | 222 | tst r0, r3 |
@@ -240,7 +240,7 @@ ENDPROC(v7_dma_inv_range) | |||
240 | * - start - virtual start address of region | 240 | * - start - virtual start address of region |
241 | * - end - virtual end address of region | 241 | * - end - virtual end address of region |
242 | */ | 242 | */ |
243 | ENTRY(v7_dma_clean_range) | 243 | v7_dma_clean_range: |
244 | dcache_line_size r2, r3 | 244 | dcache_line_size r2, r3 |
245 | sub r3, r2, #1 | 245 | sub r3, r2, #1 |
246 | bic r0, r0, r3 | 246 | bic r0, r0, r3 |
@@ -271,6 +271,32 @@ ENTRY(v7_dma_flush_range) | |||
271 | mov pc, lr | 271 | mov pc, lr |
272 | ENDPROC(v7_dma_flush_range) | 272 | ENDPROC(v7_dma_flush_range) |
273 | 273 | ||
274 | /* | ||
275 | * dma_map_area(start, size, dir) | ||
276 | * - start - kernel virtual start address | ||
277 | * - size - size of region | ||
278 | * - dir - DMA direction | ||
279 | */ | ||
280 | ENTRY(v7_dma_map_area) | ||
281 | add r1, r1, r0 | ||
282 | teq r2, #DMA_FROM_DEVICE | ||
283 | beq v7_dma_inv_range | ||
284 | b v7_dma_clean_range | ||
285 | ENDPROC(v7_dma_map_area) | ||
286 | |||
287 | /* | ||
288 | * dma_unmap_area(start, size, dir) | ||
289 | * - start - kernel virtual start address | ||
290 | * - size - size of region | ||
291 | * - dir - DMA direction | ||
292 | */ | ||
293 | ENTRY(v7_dma_unmap_area) | ||
294 | add r1, r1, r0 | ||
295 | teq r2, #DMA_TO_DEVICE | ||
296 | bne v7_dma_inv_range | ||
297 | mov pc, lr | ||
298 | ENDPROC(v7_dma_unmap_area) | ||
299 | |||
274 | __INITDATA | 300 | __INITDATA |
275 | 301 | ||
276 | .type v7_cache_fns, #object | 302 | .type v7_cache_fns, #object |
@@ -281,7 +307,7 @@ ENTRY(v7_cache_fns) | |||
281 | .long v7_coherent_kern_range | 307 | .long v7_coherent_kern_range |
282 | .long v7_coherent_user_range | 308 | .long v7_coherent_user_range |
283 | .long v7_flush_kern_dcache_area | 309 | .long v7_flush_kern_dcache_area |
284 | .long v7_dma_inv_range | 310 | .long v7_dma_map_area |
285 | .long v7_dma_clean_range | 311 | .long v7_dma_unmap_area |
286 | .long v7_dma_flush_range | 312 | .long v7_dma_flush_range |
287 | .size v7_cache_fns, . - v7_cache_fns | 313 | .size v7_cache_fns, . - v7_cache_fns |
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index a9e22e31eaa1..b0ee9ba3cfab 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c | |||
@@ -10,12 +10,17 @@ | |||
10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
11 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
12 | #include <linux/mm.h> | 12 | #include <linux/mm.h> |
13 | #include <linux/smp.h> | ||
14 | #include <linux/percpu.h> | ||
13 | 15 | ||
14 | #include <asm/mmu_context.h> | 16 | #include <asm/mmu_context.h> |
15 | #include <asm/tlbflush.h> | 17 | #include <asm/tlbflush.h> |
16 | 18 | ||
17 | static DEFINE_SPINLOCK(cpu_asid_lock); | 19 | static DEFINE_SPINLOCK(cpu_asid_lock); |
18 | unsigned int cpu_last_asid = ASID_FIRST_VERSION; | 20 | unsigned int cpu_last_asid = ASID_FIRST_VERSION; |
21 | #ifdef CONFIG_SMP | ||
22 | DEFINE_PER_CPU(struct mm_struct *, current_mm); | ||
23 | #endif | ||
19 | 24 | ||
20 | /* | 25 | /* |
21 | * We fork()ed a process, and we need a new context for the child | 26 | * We fork()ed a process, and we need a new context for the child |
@@ -26,13 +31,109 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; | |||
26 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) | 31 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
27 | { | 32 | { |
28 | mm->context.id = 0; | 33 | mm->context.id = 0; |
34 | spin_lock_init(&mm->context.id_lock); | ||
29 | } | 35 | } |
30 | 36 | ||
37 | static void flush_context(void) | ||
38 | { | ||
39 | /* set the reserved ASID before flushing the TLB */ | ||
40 | asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); | ||
41 | isb(); | ||
42 | local_flush_tlb_all(); | ||
43 | if (icache_is_vivt_asid_tagged()) { | ||
44 | __flush_icache_all(); | ||
45 | dsb(); | ||
46 | } | ||
47 | } | ||
48 | |||
49 | #ifdef CONFIG_SMP | ||
50 | |||
51 | static void set_mm_context(struct mm_struct *mm, unsigned int asid) | ||
52 | { | ||
53 | unsigned long flags; | ||
54 | |||
55 | /* | ||
56 | * Locking needed for multi-threaded applications where the | ||
57 | * same mm->context.id could be set from different CPUs during | ||
58 | * the broadcast. This function is also called via IPI so the | ||
59 | * mm->context.id_lock has to be IRQ-safe. | ||
60 | */ | ||
61 | spin_lock_irqsave(&mm->context.id_lock, flags); | ||
62 | if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) { | ||
63 | /* | ||
64 | * Old version of ASID found. Set the new one and | ||
65 | * reset mm_cpumask(mm). | ||
66 | */ | ||
67 | mm->context.id = asid; | ||
68 | cpumask_clear(mm_cpumask(mm)); | ||
69 | } | ||
70 | spin_unlock_irqrestore(&mm->context.id_lock, flags); | ||
71 | |||
72 | /* | ||
73 | * Set the mm_cpumask(mm) bit for the current CPU. | ||
74 | */ | ||
75 | cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); | ||
76 | } | ||
77 | |||
78 | /* | ||
79 | * Reset the ASID on the current CPU. This function call is broadcast | ||
80 | * from the CPU handling the ASID rollover and holding cpu_asid_lock. | ||
81 | */ | ||
82 | static void reset_context(void *info) | ||
83 | { | ||
84 | unsigned int asid; | ||
85 | unsigned int cpu = smp_processor_id(); | ||
86 | struct mm_struct *mm = per_cpu(current_mm, cpu); | ||
87 | |||
88 | /* | ||
89 | * Check if a current_mm was set on this CPU as it might still | ||
90 | * be in the early booting stages and using the reserved ASID. | ||
91 | */ | ||
92 | if (!mm) | ||
93 | return; | ||
94 | |||
95 | smp_rmb(); | ||
96 | asid = cpu_last_asid + cpu + 1; | ||
97 | |||
98 | flush_context(); | ||
99 | set_mm_context(mm, asid); | ||
100 | |||
101 | /* set the new ASID */ | ||
102 | asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id)); | ||
103 | isb(); | ||
104 | } | ||
105 | |||
106 | #else | ||
107 | |||
108 | static inline void set_mm_context(struct mm_struct *mm, unsigned int asid) | ||
109 | { | ||
110 | mm->context.id = asid; | ||
111 | cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id())); | ||
112 | } | ||
113 | |||
114 | #endif | ||
115 | |||
31 | void __new_context(struct mm_struct *mm) | 116 | void __new_context(struct mm_struct *mm) |
32 | { | 117 | { |
33 | unsigned int asid; | 118 | unsigned int asid; |
34 | 119 | ||
35 | spin_lock(&cpu_asid_lock); | 120 | spin_lock(&cpu_asid_lock); |
121 | #ifdef CONFIG_SMP | ||
122 | /* | ||
123 | * Check the ASID again, in case the change was broadcast from | ||
124 | * another CPU before we acquired the lock. | ||
125 | */ | ||
126 | if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) { | ||
127 | cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); | ||
128 | spin_unlock(&cpu_asid_lock); | ||
129 | return; | ||
130 | } | ||
131 | #endif | ||
132 | /* | ||
133 | * At this point, it is guaranteed that the current mm (with | ||
134 | * an old ASID) isn't active on any other CPU since the ASIDs | ||
135 | * are changed simultaneously via IPI. | ||
136 | */ | ||
36 | asid = ++cpu_last_asid; | 137 | asid = ++cpu_last_asid; |
37 | if (asid == 0) | 138 | if (asid == 0) |
38 | asid = cpu_last_asid = ASID_FIRST_VERSION; | 139 | asid = cpu_last_asid = ASID_FIRST_VERSION; |
@@ -42,20 +143,15 @@ void __new_context(struct mm_struct *mm) | |||
42 | * to start a new version and flush the TLB. | 143 | * to start a new version and flush the TLB. |
43 | */ | 144 | */ |
44 | if (unlikely((asid & ~ASID_MASK) == 0)) { | 145 | if (unlikely((asid & ~ASID_MASK) == 0)) { |
45 | asid = ++cpu_last_asid; | 146 | asid = cpu_last_asid + smp_processor_id() + 1; |
46 | /* set the reserved ASID before flushing the TLB */ | 147 | flush_context(); |
47 | asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n" | 148 | #ifdef CONFIG_SMP |
48 | : | 149 | smp_wmb(); |
49 | : "r" (0)); | 150 | smp_call_function(reset_context, NULL, 1); |
50 | isb(); | 151 | #endif |
51 | flush_tlb_all(); | 152 | cpu_last_asid += NR_CPUS; |
52 | if (icache_is_vivt_asid_tagged()) { | ||
53 | __flush_icache_all(); | ||
54 | dsb(); | ||
55 | } | ||
56 | } | 153 | } |
57 | spin_unlock(&cpu_asid_lock); | ||
58 | 154 | ||
59 | cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id())); | 155 | set_mm_context(mm, asid); |
60 | mm->context.id = asid; | 156 | spin_unlock(&cpu_asid_lock); |
61 | } | 157 | } |
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c index 70997d5bee2d..5eb4fd93893d 100644 --- a/arch/arm/mm/copypage-feroceon.c +++ b/arch/arm/mm/copypage-feroceon.c | |||
@@ -68,12 +68,13 @@ feroceon_copy_user_page(void *kto, const void *kfrom) | |||
68 | } | 68 | } |
69 | 69 | ||
70 | void feroceon_copy_user_highpage(struct page *to, struct page *from, | 70 | void feroceon_copy_user_highpage(struct page *to, struct page *from, |
71 | unsigned long vaddr) | 71 | unsigned long vaddr, struct vm_area_struct *vma) |
72 | { | 72 | { |
73 | void *kto, *kfrom; | 73 | void *kto, *kfrom; |
74 | 74 | ||
75 | kto = kmap_atomic(to, KM_USER0); | 75 | kto = kmap_atomic(to, KM_USER0); |
76 | kfrom = kmap_atomic(from, KM_USER1); | 76 | kfrom = kmap_atomic(from, KM_USER1); |
77 | flush_cache_page(vma, vaddr, page_to_pfn(from)); | ||
77 | feroceon_copy_user_page(kto, kfrom); | 78 | feroceon_copy_user_page(kto, kfrom); |
78 | kunmap_atomic(kfrom, KM_USER1); | 79 | kunmap_atomic(kfrom, KM_USER1); |
79 | kunmap_atomic(kto, KM_USER0); | 80 | kunmap_atomic(kto, KM_USER0); |
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c index de9c06854ad7..f72303e1d804 100644 --- a/arch/arm/mm/copypage-v3.c +++ b/arch/arm/mm/copypage-v3.c | |||
@@ -38,7 +38,7 @@ v3_copy_user_page(void *kto, const void *kfrom) | |||
38 | } | 38 | } |
39 | 39 | ||
40 | void v3_copy_user_highpage(struct page *to, struct page *from, | 40 | void v3_copy_user_highpage(struct page *to, struct page *from, |
41 | unsigned long vaddr) | 41 | unsigned long vaddr, struct vm_area_struct *vma) |
42 | { | 42 | { |
43 | void *kto, *kfrom; | 43 | void *kto, *kfrom; |
44 | 44 | ||
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c index 7370a7142b04..598c51ad5071 100644 --- a/arch/arm/mm/copypage-v4mc.c +++ b/arch/arm/mm/copypage-v4mc.c | |||
@@ -69,7 +69,7 @@ mc_copy_user_page(void *from, void *to) | |||
69 | } | 69 | } |
70 | 70 | ||
71 | void v4_mc_copy_user_highpage(struct page *to, struct page *from, | 71 | void v4_mc_copy_user_highpage(struct page *to, struct page *from, |
72 | unsigned long vaddr) | 72 | unsigned long vaddr, struct vm_area_struct *vma) |
73 | { | 73 | { |
74 | void *kto = kmap_atomic(to, KM_USER1); | 74 | void *kto = kmap_atomic(to, KM_USER1); |
75 | 75 | ||
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c index 9ab098414227..7c2eb55cd4a9 100644 --- a/arch/arm/mm/copypage-v4wb.c +++ b/arch/arm/mm/copypage-v4wb.c | |||
@@ -48,12 +48,13 @@ v4wb_copy_user_page(void *kto, const void *kfrom) | |||
48 | } | 48 | } |
49 | 49 | ||
50 | void v4wb_copy_user_highpage(struct page *to, struct page *from, | 50 | void v4wb_copy_user_highpage(struct page *to, struct page *from, |
51 | unsigned long vaddr) | 51 | unsigned long vaddr, struct vm_area_struct *vma) |
52 | { | 52 | { |
53 | void *kto, *kfrom; | 53 | void *kto, *kfrom; |
54 | 54 | ||
55 | kto = kmap_atomic(to, KM_USER0); | 55 | kto = kmap_atomic(to, KM_USER0); |
56 | kfrom = kmap_atomic(from, KM_USER1); | 56 | kfrom = kmap_atomic(from, KM_USER1); |
57 | flush_cache_page(vma, vaddr, page_to_pfn(from)); | ||
57 | v4wb_copy_user_page(kto, kfrom); | 58 | v4wb_copy_user_page(kto, kfrom); |
58 | kunmap_atomic(kfrom, KM_USER1); | 59 | kunmap_atomic(kfrom, KM_USER1); |
59 | kunmap_atomic(kto, KM_USER0); | 60 | kunmap_atomic(kto, KM_USER0); |
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c index 300efafd6643..172e6a55458e 100644 --- a/arch/arm/mm/copypage-v4wt.c +++ b/arch/arm/mm/copypage-v4wt.c | |||
@@ -44,7 +44,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom) | |||
44 | } | 44 | } |
45 | 45 | ||
46 | void v4wt_copy_user_highpage(struct page *to, struct page *from, | 46 | void v4wt_copy_user_highpage(struct page *to, struct page *from, |
47 | unsigned long vaddr) | 47 | unsigned long vaddr, struct vm_area_struct *vma) |
48 | { | 48 | { |
49 | void *kto, *kfrom; | 49 | void *kto, *kfrom; |
50 | 50 | ||
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c index 0fa1319273de..8bca4dea6dfa 100644 --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c | |||
@@ -34,7 +34,7 @@ static DEFINE_SPINLOCK(v6_lock); | |||
34 | * attack the kernel's existing mapping of these pages. | 34 | * attack the kernel's existing mapping of these pages. |
35 | */ | 35 | */ |
36 | static void v6_copy_user_highpage_nonaliasing(struct page *to, | 36 | static void v6_copy_user_highpage_nonaliasing(struct page *to, |
37 | struct page *from, unsigned long vaddr) | 37 | struct page *from, unsigned long vaddr, struct vm_area_struct *vma) |
38 | { | 38 | { |
39 | void *kto, *kfrom; | 39 | void *kto, *kfrom; |
40 | 40 | ||
@@ -81,7 +81,7 @@ static void discard_old_kernel_data(void *kto) | |||
81 | * Copy the page, taking account of the cache colour. | 81 | * Copy the page, taking account of the cache colour. |
82 | */ | 82 | */ |
83 | static void v6_copy_user_highpage_aliasing(struct page *to, | 83 | static void v6_copy_user_highpage_aliasing(struct page *to, |
84 | struct page *from, unsigned long vaddr) | 84 | struct page *from, unsigned long vaddr, struct vm_area_struct *vma) |
85 | { | 85 | { |
86 | unsigned int offset = CACHE_COLOUR(vaddr); | 86 | unsigned int offset = CACHE_COLOUR(vaddr); |
87 | unsigned long kfrom, kto; | 87 | unsigned long kfrom, kto; |
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c index bc4525f5ab23..747ad4140fc7 100644 --- a/arch/arm/mm/copypage-xsc3.c +++ b/arch/arm/mm/copypage-xsc3.c | |||
@@ -71,12 +71,13 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom) | |||
71 | } | 71 | } |
72 | 72 | ||
73 | void xsc3_mc_copy_user_highpage(struct page *to, struct page *from, | 73 | void xsc3_mc_copy_user_highpage(struct page *to, struct page *from, |
74 | unsigned long vaddr) | 74 | unsigned long vaddr, struct vm_area_struct *vma) |
75 | { | 75 | { |
76 | void *kto, *kfrom; | 76 | void *kto, *kfrom; |
77 | 77 | ||
78 | kto = kmap_atomic(to, KM_USER0); | 78 | kto = kmap_atomic(to, KM_USER0); |
79 | kfrom = kmap_atomic(from, KM_USER1); | 79 | kfrom = kmap_atomic(from, KM_USER1); |
80 | flush_cache_page(vma, vaddr, page_to_pfn(from)); | ||
80 | xsc3_mc_copy_user_page(kto, kfrom); | 81 | xsc3_mc_copy_user_page(kto, kfrom); |
81 | kunmap_atomic(kfrom, KM_USER1); | 82 | kunmap_atomic(kfrom, KM_USER1); |
82 | kunmap_atomic(kto, KM_USER0); | 83 | kunmap_atomic(kto, KM_USER0); |
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index 76824d3e966a..9920c0ae2096 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c | |||
@@ -91,7 +91,7 @@ mc_copy_user_page(void *from, void *to) | |||
91 | } | 91 | } |
92 | 92 | ||
93 | void xscale_mc_copy_user_highpage(struct page *to, struct page *from, | 93 | void xscale_mc_copy_user_highpage(struct page *to, struct page *from, |
94 | unsigned long vaddr) | 94 | unsigned long vaddr, struct vm_area_struct *vma) |
95 | { | 95 | { |
96 | void *kto = kmap_atomic(to, KM_USER1); | 96 | void *kto = kmap_atomic(to, KM_USER1); |
97 | 97 | ||
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 26325cb5d368..0da7eccf7749 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
@@ -29,9 +29,6 @@ | |||
29 | #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" | 29 | #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" |
30 | #endif | 30 | #endif |
31 | 31 | ||
32 | #define CONSISTENT_END (0xffe00000) | ||
33 | #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) | ||
34 | |||
35 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) | 32 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) |
36 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) | 33 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) |
37 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) | 34 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) |
@@ -404,78 +401,44 @@ EXPORT_SYMBOL(dma_free_coherent); | |||
404 | * platforms with CONFIG_DMABOUNCE. | 401 | * platforms with CONFIG_DMABOUNCE. |
405 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | 402 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) |
406 | */ | 403 | */ |
407 | void dma_cache_maint(const void *start, size_t size, int direction) | 404 | void ___dma_single_cpu_to_dev(const void *kaddr, size_t size, |
405 | enum dma_data_direction dir) | ||
408 | { | 406 | { |
409 | void (*inner_op)(const void *, const void *); | 407 | unsigned long paddr; |
410 | void (*outer_op)(unsigned long, unsigned long); | 408 | |
411 | 409 | BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1)); | |
412 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1)); | ||
413 | |||
414 | switch (direction) { | ||
415 | case DMA_FROM_DEVICE: /* invalidate only */ | ||
416 | inner_op = dmac_inv_range; | ||
417 | outer_op = outer_inv_range; | ||
418 | break; | ||
419 | case DMA_TO_DEVICE: /* writeback only */ | ||
420 | inner_op = dmac_clean_range; | ||
421 | outer_op = outer_clean_range; | ||
422 | break; | ||
423 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | ||
424 | inner_op = dmac_flush_range; | ||
425 | outer_op = outer_flush_range; | ||
426 | break; | ||
427 | default: | ||
428 | BUG(); | ||
429 | } | ||
430 | 410 | ||
431 | inner_op(start, start + size); | 411 | dmac_map_area(kaddr, size, dir); |
432 | outer_op(__pa(start), __pa(start) + size); | 412 | |
413 | paddr = __pa(kaddr); | ||
414 | if (dir == DMA_FROM_DEVICE) { | ||
415 | outer_inv_range(paddr, paddr + size); | ||
416 | } else { | ||
417 | outer_clean_range(paddr, paddr + size); | ||
418 | } | ||
419 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | ||
433 | } | 420 | } |
434 | EXPORT_SYMBOL(dma_cache_maint); | 421 | EXPORT_SYMBOL(___dma_single_cpu_to_dev); |
435 | 422 | ||
436 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, | 423 | void ___dma_single_dev_to_cpu(const void *kaddr, size_t size, |
437 | size_t size, int direction) | 424 | enum dma_data_direction dir) |
438 | { | 425 | { |
439 | void *vaddr; | 426 | BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1)); |
440 | unsigned long paddr; | ||
441 | void (*inner_op)(const void *, const void *); | ||
442 | void (*outer_op)(unsigned long, unsigned long); | ||
443 | |||
444 | switch (direction) { | ||
445 | case DMA_FROM_DEVICE: /* invalidate only */ | ||
446 | inner_op = dmac_inv_range; | ||
447 | outer_op = outer_inv_range; | ||
448 | break; | ||
449 | case DMA_TO_DEVICE: /* writeback only */ | ||
450 | inner_op = dmac_clean_range; | ||
451 | outer_op = outer_clean_range; | ||
452 | break; | ||
453 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | ||
454 | inner_op = dmac_flush_range; | ||
455 | outer_op = outer_flush_range; | ||
456 | break; | ||
457 | default: | ||
458 | BUG(); | ||
459 | } | ||
460 | 427 | ||
461 | if (!PageHighMem(page)) { | 428 | /* FIXME: non-speculating: not required */ |
462 | vaddr = page_address(page) + offset; | 429 | /* don't bother invalidating if DMA to device */ |
463 | inner_op(vaddr, vaddr + size); | 430 | if (dir != DMA_TO_DEVICE) { |
464 | } else { | 431 | unsigned long paddr = __pa(kaddr); |
465 | vaddr = kmap_high_get(page); | 432 | outer_inv_range(paddr, paddr + size); |
466 | if (vaddr) { | ||
467 | vaddr += offset; | ||
468 | inner_op(vaddr, vaddr + size); | ||
469 | kunmap_high(page); | ||
470 | } | ||
471 | } | 433 | } |
472 | 434 | ||
473 | paddr = page_to_phys(page) + offset; | 435 | dmac_unmap_area(kaddr, size, dir); |
474 | outer_op(paddr, paddr + size); | ||
475 | } | 436 | } |
437 | EXPORT_SYMBOL(___dma_single_dev_to_cpu); | ||
476 | 438 | ||
477 | void dma_cache_maint_page(struct page *page, unsigned long offset, | 439 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
478 | size_t size, int dir) | 440 | size_t size, enum dma_data_direction dir, |
441 | void (*op)(const void *, size_t, int)) | ||
479 | { | 442 | { |
480 | /* | 443 | /* |
481 | * A single sg entry may refer to multiple physically contiguous | 444 | * A single sg entry may refer to multiple physically contiguous |
@@ -486,20 +449,62 @@ void dma_cache_maint_page(struct page *page, unsigned long offset, | |||
486 | size_t left = size; | 449 | size_t left = size; |
487 | do { | 450 | do { |
488 | size_t len = left; | 451 | size_t len = left; |
489 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | 452 | void *vaddr; |
490 | if (offset >= PAGE_SIZE) { | 453 | |
491 | page += offset / PAGE_SIZE; | 454 | if (PageHighMem(page)) { |
492 | offset %= PAGE_SIZE; | 455 | if (len + offset > PAGE_SIZE) { |
456 | if (offset >= PAGE_SIZE) { | ||
457 | page += offset / PAGE_SIZE; | ||
458 | offset %= PAGE_SIZE; | ||
459 | } | ||
460 | len = PAGE_SIZE - offset; | ||
493 | } | 461 | } |
494 | len = PAGE_SIZE - offset; | 462 | vaddr = kmap_high_get(page); |
463 | if (vaddr) { | ||
464 | vaddr += offset; | ||
465 | op(vaddr, len, dir); | ||
466 | kunmap_high(page); | ||
467 | } | ||
468 | } else { | ||
469 | vaddr = page_address(page) + offset; | ||
470 | op(vaddr, len, dir); | ||
495 | } | 471 | } |
496 | dma_cache_maint_contiguous(page, offset, len, dir); | ||
497 | offset = 0; | 472 | offset = 0; |
498 | page++; | 473 | page++; |
499 | left -= len; | 474 | left -= len; |
500 | } while (left); | 475 | } while (left); |
501 | } | 476 | } |
502 | EXPORT_SYMBOL(dma_cache_maint_page); | 477 | |
478 | void ___dma_page_cpu_to_dev(struct page *page, unsigned long off, | ||
479 | size_t size, enum dma_data_direction dir) | ||
480 | { | ||
481 | unsigned long paddr; | ||
482 | |||
483 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); | ||
484 | |||
485 | paddr = page_to_phys(page) + off; | ||
486 | if (dir == DMA_FROM_DEVICE) { | ||
487 | outer_inv_range(paddr, paddr + size); | ||
488 | } else { | ||
489 | outer_clean_range(paddr, paddr + size); | ||
490 | } | ||
491 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | ||
492 | } | ||
493 | EXPORT_SYMBOL(___dma_page_cpu_to_dev); | ||
494 | |||
495 | void ___dma_page_dev_to_cpu(struct page *page, unsigned long off, | ||
496 | size_t size, enum dma_data_direction dir) | ||
497 | { | ||
498 | unsigned long paddr = page_to_phys(page) + off; | ||
499 | |||
500 | /* FIXME: non-speculating: not required */ | ||
501 | /* don't bother invalidating if DMA to device */ | ||
502 | if (dir != DMA_TO_DEVICE) | ||
503 | outer_inv_range(paddr, paddr + size); | ||
504 | |||
505 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); | ||
506 | } | ||
507 | EXPORT_SYMBOL(___dma_page_dev_to_cpu); | ||
503 | 508 | ||
504 | /** | 509 | /** |
505 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | 510 | * dma_map_sg - map a set of SG buffers for streaming mode DMA |
@@ -573,8 +578,12 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |||
573 | int i; | 578 | int i; |
574 | 579 | ||
575 | for_each_sg(sg, s, nents, i) { | 580 | for_each_sg(sg, s, nents, i) { |
576 | dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, | 581 | if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, |
577 | sg_dma_len(s), dir); | 582 | sg_dma_len(s), dir)) |
583 | continue; | ||
584 | |||
585 | __dma_page_dev_to_cpu(sg_page(s), s->offset, | ||
586 | s->length, dir); | ||
578 | } | 587 | } |
579 | } | 588 | } |
580 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | 589 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); |
@@ -597,9 +606,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |||
597 | sg_dma_len(s), dir)) | 606 | sg_dma_len(s), dir)) |
598 | continue; | 607 | continue; |
599 | 608 | ||
600 | if (!arch_is_coherent()) | 609 | __dma_page_cpu_to_dev(sg_page(s), s->offset, |
601 | dma_cache_maint_page(sg_page(s), s->offset, | 610 | s->length, dir); |
602 | s->length, dir); | ||
603 | } | 611 | } |
604 | } | 612 | } |
605 | EXPORT_SYMBOL(dma_sync_sg_for_device); | 613 | EXPORT_SYMBOL(dma_sync_sg_for_device); |
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 56ee15321b00..c9b97e9836a2 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c | |||
@@ -36,28 +36,12 @@ static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE; | |||
36 | * Therefore those configurations which might call adjust_pte (those | 36 | * Therefore those configurations which might call adjust_pte (those |
37 | * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock. | 37 | * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock. |
38 | */ | 38 | */ |
39 | static int adjust_pte(struct vm_area_struct *vma, unsigned long address) | 39 | static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address, |
40 | unsigned long pfn, pte_t *ptep) | ||
40 | { | 41 | { |
41 | pgd_t *pgd; | 42 | pte_t entry = *ptep; |
42 | pmd_t *pmd; | ||
43 | pte_t *pte, entry; | ||
44 | int ret; | 43 | int ret; |
45 | 44 | ||
46 | pgd = pgd_offset(vma->vm_mm, address); | ||
47 | if (pgd_none(*pgd)) | ||
48 | goto no_pgd; | ||
49 | if (pgd_bad(*pgd)) | ||
50 | goto bad_pgd; | ||
51 | |||
52 | pmd = pmd_offset(pgd, address); | ||
53 | if (pmd_none(*pmd)) | ||
54 | goto no_pmd; | ||
55 | if (pmd_bad(*pmd)) | ||
56 | goto bad_pmd; | ||
57 | |||
58 | pte = pte_offset_map(pmd, address); | ||
59 | entry = *pte; | ||
60 | |||
61 | /* | 45 | /* |
62 | * If this page is present, it's actually being shared. | 46 | * If this page is present, it's actually being shared. |
63 | */ | 47 | */ |
@@ -68,33 +52,55 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address) | |||
68 | * fault (ie, is old), we can safely ignore any issues. | 52 | * fault (ie, is old), we can safely ignore any issues. |
69 | */ | 53 | */ |
70 | if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) { | 54 | if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) { |
71 | unsigned long pfn = pte_pfn(entry); | ||
72 | flush_cache_page(vma, address, pfn); | 55 | flush_cache_page(vma, address, pfn); |
73 | outer_flush_range((pfn << PAGE_SHIFT), | 56 | outer_flush_range((pfn << PAGE_SHIFT), |
74 | (pfn << PAGE_SHIFT) + PAGE_SIZE); | 57 | (pfn << PAGE_SHIFT) + PAGE_SIZE); |
75 | pte_val(entry) &= ~L_PTE_MT_MASK; | 58 | pte_val(entry) &= ~L_PTE_MT_MASK; |
76 | pte_val(entry) |= shared_pte_mask; | 59 | pte_val(entry) |= shared_pte_mask; |
77 | set_pte_at(vma->vm_mm, address, pte, entry); | 60 | set_pte_at(vma->vm_mm, address, ptep, entry); |
78 | flush_tlb_page(vma, address); | 61 | flush_tlb_page(vma, address); |
79 | } | 62 | } |
80 | pte_unmap(pte); | 63 | |
81 | return ret; | 64 | return ret; |
65 | } | ||
66 | |||
67 | static int adjust_pte(struct vm_area_struct *vma, unsigned long address, | ||
68 | unsigned long pfn) | ||
69 | { | ||
70 | spinlock_t *ptl; | ||
71 | pgd_t *pgd; | ||
72 | pmd_t *pmd; | ||
73 | pte_t *pte; | ||
74 | int ret; | ||
75 | |||
76 | pgd = pgd_offset(vma->vm_mm, address); | ||
77 | if (pgd_none_or_clear_bad(pgd)) | ||
78 | return 0; | ||
79 | |||
80 | pmd = pmd_offset(pgd, address); | ||
81 | if (pmd_none_or_clear_bad(pmd)) | ||
82 | return 0; | ||
82 | 83 | ||
83 | bad_pgd: | 84 | /* |
84 | pgd_ERROR(*pgd); | 85 | * This is called while another page table is mapped, so we |
85 | pgd_clear(pgd); | 86 | * must use the nested version. This also means we need to |
86 | no_pgd: | 87 | * open-code the spin-locking. |
87 | return 0; | 88 | */ |
88 | 89 | ptl = pte_lockptr(vma->vm_mm, pmd); | |
89 | bad_pmd: | 90 | pte = pte_offset_map_nested(pmd, address); |
90 | pmd_ERROR(*pmd); | 91 | spin_lock(ptl); |
91 | pmd_clear(pmd); | 92 | |
92 | no_pmd: | 93 | ret = do_adjust_pte(vma, address, pfn, pte); |
93 | return 0; | 94 | |
95 | spin_unlock(ptl); | ||
96 | pte_unmap_nested(pte); | ||
97 | |||
98 | return ret; | ||
94 | } | 99 | } |
95 | 100 | ||
96 | static void | 101 | static void |
97 | make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) | 102 | make_coherent(struct address_space *mapping, struct vm_area_struct *vma, |
103 | unsigned long addr, pte_t *ptep, unsigned long pfn) | ||
98 | { | 104 | { |
99 | struct mm_struct *mm = vma->vm_mm; | 105 | struct mm_struct *mm = vma->vm_mm; |
100 | struct vm_area_struct *mpnt; | 106 | struct vm_area_struct *mpnt; |
@@ -122,11 +128,11 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne | |||
122 | if (!(mpnt->vm_flags & VM_MAYSHARE)) | 128 | if (!(mpnt->vm_flags & VM_MAYSHARE)) |
123 | continue; | 129 | continue; |
124 | offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; | 130 | offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; |
125 | aliases += adjust_pte(mpnt, mpnt->vm_start + offset); | 131 | aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn); |
126 | } | 132 | } |
127 | flush_dcache_mmap_unlock(mapping); | 133 | flush_dcache_mmap_unlock(mapping); |
128 | if (aliases) | 134 | if (aliases) |
129 | adjust_pte(vma, addr); | 135 | do_adjust_pte(vma, addr, pfn, ptep); |
130 | else | 136 | else |
131 | flush_cache_page(vma, addr, pfn); | 137 | flush_cache_page(vma, addr, pfn); |
132 | } | 138 | } |
@@ -144,9 +150,10 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne | |||
144 | * | 150 | * |
145 | * Note that the pte lock will be held. | 151 | * Note that the pte lock will be held. |
146 | */ | 152 | */ |
147 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte) | 153 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, |
154 | pte_t *ptep) | ||
148 | { | 155 | { |
149 | unsigned long pfn = pte_pfn(pte); | 156 | unsigned long pfn = pte_pfn(*ptep); |
150 | struct address_space *mapping; | 157 | struct address_space *mapping; |
151 | struct page *page; | 158 | struct page *page; |
152 | 159 | ||
@@ -168,7 +175,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte) | |||
168 | #endif | 175 | #endif |
169 | if (mapping) { | 176 | if (mapping) { |
170 | if (cache_is_vivt()) | 177 | if (cache_is_vivt()) |
171 | make_coherent(mapping, vma, addr, pfn); | 178 | make_coherent(mapping, vma, addr, ptep, pfn); |
172 | else if (vma->vm_flags & VM_EXEC) | 179 | else if (vma->vm_flags & VM_EXEC) |
173 | __flush_icache_all(); | 180 | __flush_icache_all(); |
174 | } | 181 | } |
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 10e06801afb3..9d40c341e07e 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/page-flags.h> | 18 | #include <linux/page-flags.h> |
19 | #include <linux/sched.h> | 19 | #include <linux/sched.h> |
20 | #include <linux/highmem.h> | 20 | #include <linux/highmem.h> |
21 | #include <linux/perf_event.h> | ||
21 | 22 | ||
22 | #include <asm/system.h> | 23 | #include <asm/system.h> |
23 | #include <asm/pgtable.h> | 24 | #include <asm/pgtable.h> |
@@ -302,6 +303,12 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) | |||
302 | fault = __do_page_fault(mm, addr, fsr, tsk); | 303 | fault = __do_page_fault(mm, addr, fsr, tsk); |
303 | up_read(&mm->mmap_sem); | 304 | up_read(&mm->mmap_sem); |
304 | 305 | ||
306 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, addr); | ||
307 | if (fault & VM_FAULT_MAJOR) | ||
308 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, regs, addr); | ||
309 | else if (fault & VM_FAULT_MINOR) | ||
310 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, regs, addr); | ||
311 | |||
305 | /* | 312 | /* |
306 | * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR | 313 | * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR |
307 | */ | 314 | */ |
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 6f3a4b7a3b82..e34f095e2090 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c | |||
@@ -13,6 +13,7 @@ | |||
13 | 13 | ||
14 | #include <asm/cacheflush.h> | 14 | #include <asm/cacheflush.h> |
15 | #include <asm/cachetype.h> | 15 | #include <asm/cachetype.h> |
16 | #include <asm/smp_plat.h> | ||
16 | #include <asm/system.h> | 17 | #include <asm/system.h> |
17 | #include <asm/tlbflush.h> | 18 | #include <asm/tlbflush.h> |
18 | 19 | ||
@@ -87,13 +88,26 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig | |||
87 | if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged()) | 88 | if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged()) |
88 | __flush_icache_all(); | 89 | __flush_icache_all(); |
89 | } | 90 | } |
91 | #else | ||
92 | #define flush_pfn_alias(pfn,vaddr) do { } while (0) | ||
93 | #endif | ||
90 | 94 | ||
95 | #ifdef CONFIG_SMP | ||
96 | static void flush_ptrace_access_other(void *args) | ||
97 | { | ||
98 | __flush_icache_all(); | ||
99 | } | ||
100 | #endif | ||
101 | |||
102 | static | ||
91 | void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | 103 | void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, |
92 | unsigned long uaddr, void *kaddr, | 104 | unsigned long uaddr, void *kaddr, unsigned long len) |
93 | unsigned long len, int write) | ||
94 | { | 105 | { |
95 | if (cache_is_vivt()) { | 106 | if (cache_is_vivt()) { |
96 | vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write); | 107 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { |
108 | unsigned long addr = (unsigned long)kaddr; | ||
109 | __cpuc_coherent_kern_range(addr, addr + len); | ||
110 | } | ||
97 | return; | 111 | return; |
98 | } | 112 | } |
99 | 113 | ||
@@ -104,16 +118,37 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | |||
104 | } | 118 | } |
105 | 119 | ||
106 | /* VIPT non-aliasing cache */ | 120 | /* VIPT non-aliasing cache */ |
107 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) && | 121 | if (vma->vm_flags & VM_EXEC) { |
108 | vma->vm_flags & VM_EXEC) { | ||
109 | unsigned long addr = (unsigned long)kaddr; | 122 | unsigned long addr = (unsigned long)kaddr; |
110 | /* only flushing the kernel mapping on non-aliasing VIPT */ | ||
111 | __cpuc_coherent_kern_range(addr, addr + len); | 123 | __cpuc_coherent_kern_range(addr, addr + len); |
124 | #ifdef CONFIG_SMP | ||
125 | if (cache_ops_need_broadcast()) | ||
126 | smp_call_function(flush_ptrace_access_other, | ||
127 | NULL, 1); | ||
128 | #endif | ||
112 | } | 129 | } |
113 | } | 130 | } |
114 | #else | 131 | |
115 | #define flush_pfn_alias(pfn,vaddr) do { } while (0) | 132 | /* |
133 | * Copy user data from/to a page which is mapped into a different | ||
134 | * processes address space. Really, we want to allow our "user | ||
135 | * space" model to handle this. | ||
136 | * | ||
137 | * Note that this code needs to run on the current CPU. | ||
138 | */ | ||
139 | void copy_to_user_page(struct vm_area_struct *vma, struct page *page, | ||
140 | unsigned long uaddr, void *dst, const void *src, | ||
141 | unsigned long len) | ||
142 | { | ||
143 | #ifdef CONFIG_SMP | ||
144 | preempt_disable(); | ||
116 | #endif | 145 | #endif |
146 | memcpy(dst, src, len); | ||
147 | flush_ptrace_access(vma, page, uaddr, dst, len); | ||
148 | #ifdef CONFIG_SMP | ||
149 | preempt_enable(); | ||
150 | #endif | ||
151 | } | ||
117 | 152 | ||
118 | void __flush_dcache_page(struct address_space *mapping, struct page *page) | 153 | void __flush_dcache_page(struct address_space *mapping, struct page *page) |
119 | { | 154 | { |
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index a04ffbbbe253..7829cb5425f5 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <asm/setup.h> | 23 | #include <asm/setup.h> |
24 | #include <asm/sizes.h> | 24 | #include <asm/sizes.h> |
25 | #include <asm/tlb.h> | 25 | #include <asm/tlb.h> |
26 | #include <asm/fixmap.h> | ||
26 | 27 | ||
27 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
28 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
@@ -32,19 +33,21 @@ | |||
32 | static unsigned long phys_initrd_start __initdata = 0; | 33 | static unsigned long phys_initrd_start __initdata = 0; |
33 | static unsigned long phys_initrd_size __initdata = 0; | 34 | static unsigned long phys_initrd_size __initdata = 0; |
34 | 35 | ||
35 | static void __init early_initrd(char **p) | 36 | static int __init early_initrd(char *p) |
36 | { | 37 | { |
37 | unsigned long start, size; | 38 | unsigned long start, size; |
39 | char *endp; | ||
38 | 40 | ||
39 | start = memparse(*p, p); | 41 | start = memparse(p, &endp); |
40 | if (**p == ',') { | 42 | if (*endp == ',') { |
41 | size = memparse((*p) + 1, p); | 43 | size = memparse(endp + 1, NULL); |
42 | 44 | ||
43 | phys_initrd_start = start; | 45 | phys_initrd_start = start; |
44 | phys_initrd_size = size; | 46 | phys_initrd_size = size; |
45 | } | 47 | } |
48 | return 0; | ||
46 | } | 49 | } |
47 | __early_param("initrd=", early_initrd); | 50 | early_param("initrd", early_initrd); |
48 | 51 | ||
49 | static int __init parse_tag_initrd(const struct tag *tag) | 52 | static int __init parse_tag_initrd(const struct tag *tag) |
50 | { | 53 | { |
@@ -560,7 +563,7 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi) | |||
560 | */ | 563 | */ |
561 | void __init mem_init(void) | 564 | void __init mem_init(void) |
562 | { | 565 | { |
563 | unsigned int codesize, datasize, initsize; | 566 | unsigned long reserved_pages, free_pages; |
564 | int i, node; | 567 | int i, node; |
565 | 568 | ||
566 | #ifndef CONFIG_DISCONTIGMEM | 569 | #ifndef CONFIG_DISCONTIGMEM |
@@ -596,6 +599,33 @@ void __init mem_init(void) | |||
596 | totalram_pages += totalhigh_pages; | 599 | totalram_pages += totalhigh_pages; |
597 | #endif | 600 | #endif |
598 | 601 | ||
602 | reserved_pages = free_pages = 0; | ||
603 | |||
604 | for_each_online_node(node) { | ||
605 | pg_data_t *n = NODE_DATA(node); | ||
606 | struct page *map = pgdat_page_nr(n, 0) - n->node_start_pfn; | ||
607 | |||
608 | for_each_nodebank(i, &meminfo, node) { | ||
609 | struct membank *bank = &meminfo.bank[i]; | ||
610 | unsigned int pfn1, pfn2; | ||
611 | struct page *page, *end; | ||
612 | |||
613 | pfn1 = bank_pfn_start(bank); | ||
614 | pfn2 = bank_pfn_end(bank); | ||
615 | |||
616 | page = map + pfn1; | ||
617 | end = map + pfn2; | ||
618 | |||
619 | do { | ||
620 | if (PageReserved(page)) | ||
621 | reserved_pages++; | ||
622 | else if (!page_count(page)) | ||
623 | free_pages++; | ||
624 | page++; | ||
625 | } while (page < end); | ||
626 | } | ||
627 | } | ||
628 | |||
599 | /* | 629 | /* |
600 | * Since our memory may not be contiguous, calculate the | 630 | * Since our memory may not be contiguous, calculate the |
601 | * real number of pages we have in this system | 631 | * real number of pages we have in this system |
@@ -608,16 +638,71 @@ void __init mem_init(void) | |||
608 | } | 638 | } |
609 | printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT)); | 639 | printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT)); |
610 | 640 | ||
611 | codesize = _etext - _text; | 641 | printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n", |
612 | datasize = _end - _data; | 642 | nr_free_pages() << (PAGE_SHIFT-10), |
613 | initsize = __init_end - __init_begin; | 643 | free_pages << (PAGE_SHIFT-10), |
614 | 644 | reserved_pages << (PAGE_SHIFT-10), | |
615 | printk(KERN_NOTICE "Memory: %luKB available (%dK code, " | ||
616 | "%dK data, %dK init, %luK highmem)\n", | ||
617 | nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10, | ||
618 | datasize >> 10, initsize >> 10, | ||
619 | totalhigh_pages << (PAGE_SHIFT-10)); | 645 | totalhigh_pages << (PAGE_SHIFT-10)); |
620 | 646 | ||
647 | #define MLK(b, t) b, t, ((t) - (b)) >> 10 | ||
648 | #define MLM(b, t) b, t, ((t) - (b)) >> 20 | ||
649 | #define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K) | ||
650 | |||
651 | printk(KERN_NOTICE "Virtual kernel memory layout:\n" | ||
652 | " vector : 0x%08lx - 0x%08lx (%4ld kB)\n" | ||
653 | " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" | ||
654 | #ifdef CONFIG_MMU | ||
655 | " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n" | ||
656 | #endif | ||
657 | " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n" | ||
658 | " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n" | ||
659 | #ifdef CONFIG_HIGHMEM | ||
660 | " pkmap : 0x%08lx - 0x%08lx (%4ld MB)\n" | ||
661 | #endif | ||
662 | " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" | ||
663 | " .init : 0x%p" " - 0x%p" " (%4d kB)\n" | ||
664 | " .text : 0x%p" " - 0x%p" " (%4d kB)\n" | ||
665 | " .data : 0x%p" " - 0x%p" " (%4d kB)\n", | ||
666 | |||
667 | MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + | ||
668 | (PAGE_SIZE)), | ||
669 | MLK(FIXADDR_START, FIXADDR_TOP), | ||
670 | #ifdef CONFIG_MMU | ||
671 | MLM(CONSISTENT_BASE, CONSISTENT_END), | ||
672 | #endif | ||
673 | MLM(VMALLOC_START, VMALLOC_END), | ||
674 | MLM(PAGE_OFFSET, (unsigned long)high_memory), | ||
675 | #ifdef CONFIG_HIGHMEM | ||
676 | MLM(PKMAP_BASE, (PKMAP_BASE) + (LAST_PKMAP) * | ||
677 | (PAGE_SIZE)), | ||
678 | #endif | ||
679 | MLM(MODULES_VADDR, MODULES_END), | ||
680 | |||
681 | MLK_ROUNDUP(__init_begin, __init_end), | ||
682 | MLK_ROUNDUP(_text, _etext), | ||
683 | MLK_ROUNDUP(_data, _edata)); | ||
684 | |||
685 | #undef MLK | ||
686 | #undef MLM | ||
687 | #undef MLK_ROUNDUP | ||
688 | |||
689 | /* | ||
690 | * Check boundaries twice: Some fundamental inconsistencies can | ||
691 | * be detected at build time already. | ||
692 | */ | ||
693 | #ifdef CONFIG_MMU | ||
694 | BUILD_BUG_ON(VMALLOC_END > CONSISTENT_BASE); | ||
695 | BUG_ON(VMALLOC_END > CONSISTENT_BASE); | ||
696 | |||
697 | BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR); | ||
698 | BUG_ON(TASK_SIZE > MODULES_VADDR); | ||
699 | #endif | ||
700 | |||
701 | #ifdef CONFIG_HIGHMEM | ||
702 | BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > PAGE_OFFSET); | ||
703 | BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > PAGE_OFFSET); | ||
704 | #endif | ||
705 | |||
621 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { | 706 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { |
622 | extern int sysctl_overcommit_memory; | 707 | extern int sysctl_overcommit_memory; |
623 | /* | 708 | /* |
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 0ab75c60f7cf..28c8b950ef04 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c | |||
@@ -139,8 +139,8 @@ void __check_kvm_seq(struct mm_struct *mm) | |||
139 | * which requires the new ioremap'd region to be referenced, the CPU will | 139 | * which requires the new ioremap'd region to be referenced, the CPU will |
140 | * reference the _old_ region. | 140 | * reference the _old_ region. |
141 | * | 141 | * |
142 | * Note that get_vm_area() allocates a guard 4K page, so we need to mask | 142 | * Note that get_vm_area_caller() allocates a guard 4K page, so we need to |
143 | * the size back to 1MB aligned or we will overflow in the loop below. | 143 | * mask the size back to 1MB aligned or we will overflow in the loop below. |
144 | */ | 144 | */ |
145 | static void unmap_area_sections(unsigned long virt, unsigned long size) | 145 | static void unmap_area_sections(unsigned long virt, unsigned long size) |
146 | { | 146 | { |
@@ -254,22 +254,8 @@ remap_area_supersections(unsigned long virt, unsigned long pfn, | |||
254 | } | 254 | } |
255 | #endif | 255 | #endif |
256 | 256 | ||
257 | 257 | void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, | |
258 | /* | 258 | unsigned long offset, size_t size, unsigned int mtype, void *caller) |
259 | * Remap an arbitrary physical address space into the kernel virtual | ||
260 | * address space. Needed when the kernel wants to access high addresses | ||
261 | * directly. | ||
262 | * | ||
263 | * NOTE! We need to allow non-page-aligned mappings too: we will obviously | ||
264 | * have to convert them into an offset in a page-aligned mapping, but the | ||
265 | * caller shouldn't need to know that small detail. | ||
266 | * | ||
267 | * 'flags' are the extra L_PTE_ flags that you want to specify for this | ||
268 | * mapping. See <asm/pgtable.h> for more information. | ||
269 | */ | ||
270 | void __iomem * | ||
271 | __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, | ||
272 | unsigned int mtype) | ||
273 | { | 259 | { |
274 | const struct mem_type *type; | 260 | const struct mem_type *type; |
275 | int err; | 261 | int err; |
@@ -291,7 +277,7 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, | |||
291 | */ | 277 | */ |
292 | size = PAGE_ALIGN(offset + size); | 278 | size = PAGE_ALIGN(offset + size); |
293 | 279 | ||
294 | area = get_vm_area(size, VM_IOREMAP); | 280 | area = get_vm_area_caller(size, VM_IOREMAP, caller); |
295 | if (!area) | 281 | if (!area) |
296 | return NULL; | 282 | return NULL; |
297 | addr = (unsigned long)area->addr; | 283 | addr = (unsigned long)area->addr; |
@@ -318,10 +304,9 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, | |||
318 | flush_cache_vmap(addr, addr + size); | 304 | flush_cache_vmap(addr, addr + size); |
319 | return (void __iomem *) (offset + addr); | 305 | return (void __iomem *) (offset + addr); |
320 | } | 306 | } |
321 | EXPORT_SYMBOL(__arm_ioremap_pfn); | ||
322 | 307 | ||
323 | void __iomem * | 308 | void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size, |
324 | __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | 309 | unsigned int mtype, void *caller) |
325 | { | 310 | { |
326 | unsigned long last_addr; | 311 | unsigned long last_addr; |
327 | unsigned long offset = phys_addr & ~PAGE_MASK; | 312 | unsigned long offset = phys_addr & ~PAGE_MASK; |
@@ -334,7 +319,33 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | |||
334 | if (!size || last_addr < phys_addr) | 319 | if (!size || last_addr < phys_addr) |
335 | return NULL; | 320 | return NULL; |
336 | 321 | ||
337 | return __arm_ioremap_pfn(pfn, offset, size, mtype); | 322 | return __arm_ioremap_pfn_caller(pfn, offset, size, mtype, |
323 | caller); | ||
324 | } | ||
325 | |||
326 | /* | ||
327 | * Remap an arbitrary physical address space into the kernel virtual | ||
328 | * address space. Needed when the kernel wants to access high addresses | ||
329 | * directly. | ||
330 | * | ||
331 | * NOTE! We need to allow non-page-aligned mappings too: we will obviously | ||
332 | * have to convert them into an offset in a page-aligned mapping, but the | ||
333 | * caller shouldn't need to know that small detail. | ||
334 | */ | ||
335 | void __iomem * | ||
336 | __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, | ||
337 | unsigned int mtype) | ||
338 | { | ||
339 | return __arm_ioremap_pfn_caller(pfn, offset, size, mtype, | ||
340 | __builtin_return_address(0)); | ||
341 | } | ||
342 | EXPORT_SYMBOL(__arm_ioremap_pfn); | ||
343 | |||
344 | void __iomem * | ||
345 | __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | ||
346 | { | ||
347 | return __arm_ioremap_caller(phys_addr, size, mtype, | ||
348 | __builtin_return_address(0)); | ||
338 | } | 349 | } |
339 | EXPORT_SYMBOL(__arm_ioremap); | 350 | EXPORT_SYMBOL(__arm_ioremap); |
340 | 351 | ||
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 761ffede6a23..9d4da6ac28eb 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
@@ -100,18 +100,17 @@ static struct cachepolicy cache_policies[] __initdata = { | |||
100 | * writebuffer to be turned off. (Note: the write | 100 | * writebuffer to be turned off. (Note: the write |
101 | * buffer should not be on and the cache off). | 101 | * buffer should not be on and the cache off). |
102 | */ | 102 | */ |
103 | static void __init early_cachepolicy(char **p) | 103 | static int __init early_cachepolicy(char *p) |
104 | { | 104 | { |
105 | int i; | 105 | int i; |
106 | 106 | ||
107 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | 107 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
108 | int len = strlen(cache_policies[i].policy); | 108 | int len = strlen(cache_policies[i].policy); |
109 | 109 | ||
110 | if (memcmp(*p, cache_policies[i].policy, len) == 0) { | 110 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
111 | cachepolicy = i; | 111 | cachepolicy = i; |
112 | cr_alignment &= ~cache_policies[i].cr_mask; | 112 | cr_alignment &= ~cache_policies[i].cr_mask; |
113 | cr_no_alignment &= ~cache_policies[i].cr_mask; | 113 | cr_no_alignment &= ~cache_policies[i].cr_mask; |
114 | *p += len; | ||
115 | break; | 114 | break; |
116 | } | 115 | } |
117 | } | 116 | } |
@@ -130,36 +129,37 @@ static void __init early_cachepolicy(char **p) | |||
130 | } | 129 | } |
131 | flush_cache_all(); | 130 | flush_cache_all(); |
132 | set_cr(cr_alignment); | 131 | set_cr(cr_alignment); |
132 | return 0; | ||
133 | } | 133 | } |
134 | __early_param("cachepolicy=", early_cachepolicy); | 134 | early_param("cachepolicy", early_cachepolicy); |
135 | 135 | ||
136 | static void __init early_nocache(char **__unused) | 136 | static int __init early_nocache(char *__unused) |
137 | { | 137 | { |
138 | char *p = "buffered"; | 138 | char *p = "buffered"; |
139 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | 139 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); |
140 | early_cachepolicy(&p); | 140 | early_cachepolicy(p); |
141 | return 0; | ||
141 | } | 142 | } |
142 | __early_param("nocache", early_nocache); | 143 | early_param("nocache", early_nocache); |
143 | 144 | ||
144 | static void __init early_nowrite(char **__unused) | 145 | static int __init early_nowrite(char *__unused) |
145 | { | 146 | { |
146 | char *p = "uncached"; | 147 | char *p = "uncached"; |
147 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | 148 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); |
148 | early_cachepolicy(&p); | 149 | early_cachepolicy(p); |
150 | return 0; | ||
149 | } | 151 | } |
150 | __early_param("nowb", early_nowrite); | 152 | early_param("nowb", early_nowrite); |
151 | 153 | ||
152 | static void __init early_ecc(char **p) | 154 | static int __init early_ecc(char *p) |
153 | { | 155 | { |
154 | if (memcmp(*p, "on", 2) == 0) { | 156 | if (memcmp(p, "on", 2) == 0) |
155 | ecc_mask = PMD_PROTECTION; | 157 | ecc_mask = PMD_PROTECTION; |
156 | *p += 2; | 158 | else if (memcmp(p, "off", 3) == 0) |
157 | } else if (memcmp(*p, "off", 3) == 0) { | ||
158 | ecc_mask = 0; | 159 | ecc_mask = 0; |
159 | *p += 3; | 160 | return 0; |
160 | } | ||
161 | } | 161 | } |
162 | __early_param("ecc=", early_ecc); | 162 | early_param("ecc", early_ecc); |
163 | 163 | ||
164 | static int __init noalign_setup(char *__unused) | 164 | static int __init noalign_setup(char *__unused) |
165 | { | 165 | { |
@@ -670,9 +670,9 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M; | |||
670 | * bytes. This can be used to increase (or decrease) the vmalloc | 670 | * bytes. This can be used to increase (or decrease) the vmalloc |
671 | * area - the default is 128m. | 671 | * area - the default is 128m. |
672 | */ | 672 | */ |
673 | static void __init early_vmalloc(char **arg) | 673 | static int __init early_vmalloc(char *arg) |
674 | { | 674 | { |
675 | vmalloc_reserve = memparse(*arg, arg); | 675 | vmalloc_reserve = memparse(arg, NULL); |
676 | 676 | ||
677 | if (vmalloc_reserve < SZ_16M) { | 677 | if (vmalloc_reserve < SZ_16M) { |
678 | vmalloc_reserve = SZ_16M; | 678 | vmalloc_reserve = SZ_16M; |
@@ -687,8 +687,9 @@ static void __init early_vmalloc(char **arg) | |||
687 | "vmalloc area is too big, limiting to %luMB\n", | 687 | "vmalloc area is too big, limiting to %luMB\n", |
688 | vmalloc_reserve >> 20); | 688 | vmalloc_reserve >> 20); |
689 | } | 689 | } |
690 | return 0; | ||
690 | } | 691 | } |
691 | __early_param("vmalloc=", early_vmalloc); | 692 | early_param("vmalloc", early_vmalloc); |
692 | 693 | ||
693 | #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) | 694 | #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) |
694 | 695 | ||
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 374a8311bc84..9bfeb6b9509a 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c | |||
@@ -74,6 +74,12 @@ void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, | |||
74 | } | 74 | } |
75 | EXPORT_SYMBOL(__arm_ioremap_pfn); | 75 | EXPORT_SYMBOL(__arm_ioremap_pfn); |
76 | 76 | ||
77 | void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset, | ||
78 | size_t size, unsigned int mtype, void *caller) | ||
79 | { | ||
80 | return __arm_ioremap_pfn(pfn, offset, size, mtype); | ||
81 | } | ||
82 | |||
77 | void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size, | 83 | void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size, |
78 | unsigned int mtype) | 84 | unsigned int mtype) |
79 | { | 85 | { |
@@ -81,6 +87,12 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size, | |||
81 | } | 87 | } |
82 | EXPORT_SYMBOL(__arm_ioremap); | 88 | EXPORT_SYMBOL(__arm_ioremap); |
83 | 89 | ||
90 | void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size, | ||
91 | unsigned int mtype, void *caller) | ||
92 | { | ||
93 | return __arm_ioremap(phys_addr, size, mtype); | ||
94 | } | ||
95 | |||
84 | void __iounmap(volatile void __iomem *addr) | 96 | void __iounmap(volatile void __iomem *addr) |
85 | { | 97 | { |
86 | } | 98 | } |
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 8012e24282b2..72507c630ceb 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S | |||
@@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area) | |||
265 | * | 265 | * |
266 | * (same as v4wb) | 266 | * (same as v4wb) |
267 | */ | 267 | */ |
268 | ENTRY(arm1020_dma_inv_range) | 268 | arm1020_dma_inv_range: |
269 | mov ip, #0 | 269 | mov ip, #0 |
270 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 270 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
271 | tst r0, #CACHE_DLINESIZE - 1 | 271 | tst r0, #CACHE_DLINESIZE - 1 |
@@ -295,7 +295,7 @@ ENTRY(arm1020_dma_inv_range) | |||
295 | * | 295 | * |
296 | * (same as v4wb) | 296 | * (same as v4wb) |
297 | */ | 297 | */ |
298 | ENTRY(arm1020_dma_clean_range) | 298 | arm1020_dma_clean_range: |
299 | mov ip, #0 | 299 | mov ip, #0 |
300 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 300 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
301 | bic r0, r0, #CACHE_DLINESIZE - 1 | 301 | bic r0, r0, #CACHE_DLINESIZE - 1 |
@@ -330,6 +330,30 @@ ENTRY(arm1020_dma_flush_range) | |||
330 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 330 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
331 | mov pc, lr | 331 | mov pc, lr |
332 | 332 | ||
333 | /* | ||
334 | * dma_map_area(start, size, dir) | ||
335 | * - start - kernel virtual start address | ||
336 | * - size - size of region | ||
337 | * - dir - DMA direction | ||
338 | */ | ||
339 | ENTRY(arm1020_dma_map_area) | ||
340 | add r1, r1, r0 | ||
341 | cmp r2, #DMA_TO_DEVICE | ||
342 | beq arm1020_dma_clean_range | ||
343 | bcs arm1020_dma_inv_range | ||
344 | b arm1020_dma_flush_range | ||
345 | ENDPROC(arm1020_dma_map_area) | ||
346 | |||
347 | /* | ||
348 | * dma_unmap_area(start, size, dir) | ||
349 | * - start - kernel virtual start address | ||
350 | * - size - size of region | ||
351 | * - dir - DMA direction | ||
352 | */ | ||
353 | ENTRY(arm1020_dma_unmap_area) | ||
354 | mov pc, lr | ||
355 | ENDPROC(arm1020_dma_unmap_area) | ||
356 | |||
333 | ENTRY(arm1020_cache_fns) | 357 | ENTRY(arm1020_cache_fns) |
334 | .long arm1020_flush_kern_cache_all | 358 | .long arm1020_flush_kern_cache_all |
335 | .long arm1020_flush_user_cache_all | 359 | .long arm1020_flush_user_cache_all |
@@ -337,8 +361,8 @@ ENTRY(arm1020_cache_fns) | |||
337 | .long arm1020_coherent_kern_range | 361 | .long arm1020_coherent_kern_range |
338 | .long arm1020_coherent_user_range | 362 | .long arm1020_coherent_user_range |
339 | .long arm1020_flush_kern_dcache_area | 363 | .long arm1020_flush_kern_dcache_area |
340 | .long arm1020_dma_inv_range | 364 | .long arm1020_dma_map_area |
341 | .long arm1020_dma_clean_range | 365 | .long arm1020_dma_unmap_area |
342 | .long arm1020_dma_flush_range | 366 | .long arm1020_dma_flush_range |
343 | 367 | ||
344 | .align 5 | 368 | .align 5 |
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 41fe25d234f5..d27829805609 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S | |||
@@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area) | |||
258 | * | 258 | * |
259 | * (same as v4wb) | 259 | * (same as v4wb) |
260 | */ | 260 | */ |
261 | ENTRY(arm1020e_dma_inv_range) | 261 | arm1020e_dma_inv_range: |
262 | mov ip, #0 | 262 | mov ip, #0 |
263 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 263 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
264 | tst r0, #CACHE_DLINESIZE - 1 | 264 | tst r0, #CACHE_DLINESIZE - 1 |
@@ -284,7 +284,7 @@ ENTRY(arm1020e_dma_inv_range) | |||
284 | * | 284 | * |
285 | * (same as v4wb) | 285 | * (same as v4wb) |
286 | */ | 286 | */ |
287 | ENTRY(arm1020e_dma_clean_range) | 287 | arm1020e_dma_clean_range: |
288 | mov ip, #0 | 288 | mov ip, #0 |
289 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 289 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
290 | bic r0, r0, #CACHE_DLINESIZE - 1 | 290 | bic r0, r0, #CACHE_DLINESIZE - 1 |
@@ -316,6 +316,30 @@ ENTRY(arm1020e_dma_flush_range) | |||
316 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 316 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
317 | mov pc, lr | 317 | mov pc, lr |
318 | 318 | ||
319 | /* | ||
320 | * dma_map_area(start, size, dir) | ||
321 | * - start - kernel virtual start address | ||
322 | * - size - size of region | ||
323 | * - dir - DMA direction | ||
324 | */ | ||
325 | ENTRY(arm1020e_dma_map_area) | ||
326 | add r1, r1, r0 | ||
327 | cmp r2, #DMA_TO_DEVICE | ||
328 | beq arm1020e_dma_clean_range | ||
329 | bcs arm1020e_dma_inv_range | ||
330 | b arm1020e_dma_flush_range | ||
331 | ENDPROC(arm1020e_dma_map_area) | ||
332 | |||
333 | /* | ||
334 | * dma_unmap_area(start, size, dir) | ||
335 | * - start - kernel virtual start address | ||
336 | * - size - size of region | ||
337 | * - dir - DMA direction | ||
338 | */ | ||
339 | ENTRY(arm1020e_dma_unmap_area) | ||
340 | mov pc, lr | ||
341 | ENDPROC(arm1020e_dma_unmap_area) | ||
342 | |||
319 | ENTRY(arm1020e_cache_fns) | 343 | ENTRY(arm1020e_cache_fns) |
320 | .long arm1020e_flush_kern_cache_all | 344 | .long arm1020e_flush_kern_cache_all |
321 | .long arm1020e_flush_user_cache_all | 345 | .long arm1020e_flush_user_cache_all |
@@ -323,8 +347,8 @@ ENTRY(arm1020e_cache_fns) | |||
323 | .long arm1020e_coherent_kern_range | 347 | .long arm1020e_coherent_kern_range |
324 | .long arm1020e_coherent_user_range | 348 | .long arm1020e_coherent_user_range |
325 | .long arm1020e_flush_kern_dcache_area | 349 | .long arm1020e_flush_kern_dcache_area |
326 | .long arm1020e_dma_inv_range | 350 | .long arm1020e_dma_map_area |
327 | .long arm1020e_dma_clean_range | 351 | .long arm1020e_dma_unmap_area |
328 | .long arm1020e_dma_flush_range | 352 | .long arm1020e_dma_flush_range |
329 | 353 | ||
330 | .align 5 | 354 | .align 5 |
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 20a5b1b31a70..ce13e4a827de 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S | |||
@@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area) | |||
247 | * | 247 | * |
248 | * (same as v4wb) | 248 | * (same as v4wb) |
249 | */ | 249 | */ |
250 | ENTRY(arm1022_dma_inv_range) | 250 | arm1022_dma_inv_range: |
251 | mov ip, #0 | 251 | mov ip, #0 |
252 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 252 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
253 | tst r0, #CACHE_DLINESIZE - 1 | 253 | tst r0, #CACHE_DLINESIZE - 1 |
@@ -273,7 +273,7 @@ ENTRY(arm1022_dma_inv_range) | |||
273 | * | 273 | * |
274 | * (same as v4wb) | 274 | * (same as v4wb) |
275 | */ | 275 | */ |
276 | ENTRY(arm1022_dma_clean_range) | 276 | arm1022_dma_clean_range: |
277 | mov ip, #0 | 277 | mov ip, #0 |
278 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 278 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
279 | bic r0, r0, #CACHE_DLINESIZE - 1 | 279 | bic r0, r0, #CACHE_DLINESIZE - 1 |
@@ -305,6 +305,30 @@ ENTRY(arm1022_dma_flush_range) | |||
305 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 305 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
306 | mov pc, lr | 306 | mov pc, lr |
307 | 307 | ||
308 | /* | ||
309 | * dma_map_area(start, size, dir) | ||
310 | * - start - kernel virtual start address | ||
311 | * - size - size of region | ||
312 | * - dir - DMA direction | ||
313 | */ | ||
314 | ENTRY(arm1022_dma_map_area) | ||
315 | add r1, r1, r0 | ||
316 | cmp r2, #DMA_TO_DEVICE | ||
317 | beq arm1022_dma_clean_range | ||
318 | bcs arm1022_dma_inv_range | ||
319 | b arm1022_dma_flush_range | ||
320 | ENDPROC(arm1022_dma_map_area) | ||
321 | |||
322 | /* | ||
323 | * dma_unmap_area(start, size, dir) | ||
324 | * - start - kernel virtual start address | ||
325 | * - size - size of region | ||
326 | * - dir - DMA direction | ||
327 | */ | ||
328 | ENTRY(arm1022_dma_unmap_area) | ||
329 | mov pc, lr | ||
330 | ENDPROC(arm1022_dma_unmap_area) | ||
331 | |||
308 | ENTRY(arm1022_cache_fns) | 332 | ENTRY(arm1022_cache_fns) |
309 | .long arm1022_flush_kern_cache_all | 333 | .long arm1022_flush_kern_cache_all |
310 | .long arm1022_flush_user_cache_all | 334 | .long arm1022_flush_user_cache_all |
@@ -312,8 +336,8 @@ ENTRY(arm1022_cache_fns) | |||
312 | .long arm1022_coherent_kern_range | 336 | .long arm1022_coherent_kern_range |
313 | .long arm1022_coherent_user_range | 337 | .long arm1022_coherent_user_range |
314 | .long arm1022_flush_kern_dcache_area | 338 | .long arm1022_flush_kern_dcache_area |
315 | .long arm1022_dma_inv_range | 339 | .long arm1022_dma_map_area |
316 | .long arm1022_dma_clean_range | 340 | .long arm1022_dma_unmap_area |
317 | .long arm1022_dma_flush_range | 341 | .long arm1022_dma_flush_range |
318 | 342 | ||
319 | .align 5 | 343 | .align 5 |
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 96aedb10fcc4..636672a29c6d 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S | |||
@@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area) | |||
241 | * | 241 | * |
242 | * (same as v4wb) | 242 | * (same as v4wb) |
243 | */ | 243 | */ |
244 | ENTRY(arm1026_dma_inv_range) | 244 | arm1026_dma_inv_range: |
245 | mov ip, #0 | 245 | mov ip, #0 |
246 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 246 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
247 | tst r0, #CACHE_DLINESIZE - 1 | 247 | tst r0, #CACHE_DLINESIZE - 1 |
@@ -267,7 +267,7 @@ ENTRY(arm1026_dma_inv_range) | |||
267 | * | 267 | * |
268 | * (same as v4wb) | 268 | * (same as v4wb) |
269 | */ | 269 | */ |
270 | ENTRY(arm1026_dma_clean_range) | 270 | arm1026_dma_clean_range: |
271 | mov ip, #0 | 271 | mov ip, #0 |
272 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 272 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
273 | bic r0, r0, #CACHE_DLINESIZE - 1 | 273 | bic r0, r0, #CACHE_DLINESIZE - 1 |
@@ -299,6 +299,30 @@ ENTRY(arm1026_dma_flush_range) | |||
299 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 299 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
300 | mov pc, lr | 300 | mov pc, lr |
301 | 301 | ||
302 | /* | ||
303 | * dma_map_area(start, size, dir) | ||
304 | * - start - kernel virtual start address | ||
305 | * - size - size of region | ||
306 | * - dir - DMA direction | ||
307 | */ | ||
308 | ENTRY(arm1026_dma_map_area) | ||
309 | add r1, r1, r0 | ||
310 | cmp r2, #DMA_TO_DEVICE | ||
311 | beq arm1026_dma_clean_range | ||
312 | bcs arm1026_dma_inv_range | ||
313 | b arm1026_dma_flush_range | ||
314 | ENDPROC(arm1026_dma_map_area) | ||
315 | |||
316 | /* | ||
317 | * dma_unmap_area(start, size, dir) | ||
318 | * - start - kernel virtual start address | ||
319 | * - size - size of region | ||
320 | * - dir - DMA direction | ||
321 | */ | ||
322 | ENTRY(arm1026_dma_unmap_area) | ||
323 | mov pc, lr | ||
324 | ENDPROC(arm1026_dma_unmap_area) | ||
325 | |||
302 | ENTRY(arm1026_cache_fns) | 326 | ENTRY(arm1026_cache_fns) |
303 | .long arm1026_flush_kern_cache_all | 327 | .long arm1026_flush_kern_cache_all |
304 | .long arm1026_flush_user_cache_all | 328 | .long arm1026_flush_user_cache_all |
@@ -306,8 +330,8 @@ ENTRY(arm1026_cache_fns) | |||
306 | .long arm1026_coherent_kern_range | 330 | .long arm1026_coherent_kern_range |
307 | .long arm1026_coherent_user_range | 331 | .long arm1026_coherent_user_range |
308 | .long arm1026_flush_kern_dcache_area | 332 | .long arm1026_flush_kern_dcache_area |
309 | .long arm1026_dma_inv_range | 333 | .long arm1026_dma_map_area |
310 | .long arm1026_dma_clean_range | 334 | .long arm1026_dma_unmap_area |
311 | .long arm1026_dma_flush_range | 335 | .long arm1026_dma_flush_range |
312 | 336 | ||
313 | .align 5 | 337 | .align 5 |
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 471669e2d7cb..8be81992645d 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S | |||
@@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area) | |||
239 | * | 239 | * |
240 | * (same as v4wb) | 240 | * (same as v4wb) |
241 | */ | 241 | */ |
242 | ENTRY(arm920_dma_inv_range) | 242 | arm920_dma_inv_range: |
243 | tst r0, #CACHE_DLINESIZE - 1 | 243 | tst r0, #CACHE_DLINESIZE - 1 |
244 | bic r0, r0, #CACHE_DLINESIZE - 1 | 244 | bic r0, r0, #CACHE_DLINESIZE - 1 |
245 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 245 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -262,7 +262,7 @@ ENTRY(arm920_dma_inv_range) | |||
262 | * | 262 | * |
263 | * (same as v4wb) | 263 | * (same as v4wb) |
264 | */ | 264 | */ |
265 | ENTRY(arm920_dma_clean_range) | 265 | arm920_dma_clean_range: |
266 | bic r0, r0, #CACHE_DLINESIZE - 1 | 266 | bic r0, r0, #CACHE_DLINESIZE - 1 |
267 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 267 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
268 | add r0, r0, #CACHE_DLINESIZE | 268 | add r0, r0, #CACHE_DLINESIZE |
@@ -288,6 +288,30 @@ ENTRY(arm920_dma_flush_range) | |||
288 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 288 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
289 | mov pc, lr | 289 | mov pc, lr |
290 | 290 | ||
291 | /* | ||
292 | * dma_map_area(start, size, dir) | ||
293 | * - start - kernel virtual start address | ||
294 | * - size - size of region | ||
295 | * - dir - DMA direction | ||
296 | */ | ||
297 | ENTRY(arm920_dma_map_area) | ||
298 | add r1, r1, r0 | ||
299 | cmp r2, #DMA_TO_DEVICE | ||
300 | beq arm920_dma_clean_range | ||
301 | bcs arm920_dma_inv_range | ||
302 | b arm920_dma_flush_range | ||
303 | ENDPROC(arm920_dma_map_area) | ||
304 | |||
305 | /* | ||
306 | * dma_unmap_area(start, size, dir) | ||
307 | * - start - kernel virtual start address | ||
308 | * - size - size of region | ||
309 | * - dir - DMA direction | ||
310 | */ | ||
311 | ENTRY(arm920_dma_unmap_area) | ||
312 | mov pc, lr | ||
313 | ENDPROC(arm920_dma_unmap_area) | ||
314 | |||
291 | ENTRY(arm920_cache_fns) | 315 | ENTRY(arm920_cache_fns) |
292 | .long arm920_flush_kern_cache_all | 316 | .long arm920_flush_kern_cache_all |
293 | .long arm920_flush_user_cache_all | 317 | .long arm920_flush_user_cache_all |
@@ -295,8 +319,8 @@ ENTRY(arm920_cache_fns) | |||
295 | .long arm920_coherent_kern_range | 319 | .long arm920_coherent_kern_range |
296 | .long arm920_coherent_user_range | 320 | .long arm920_coherent_user_range |
297 | .long arm920_flush_kern_dcache_area | 321 | .long arm920_flush_kern_dcache_area |
298 | .long arm920_dma_inv_range | 322 | .long arm920_dma_map_area |
299 | .long arm920_dma_clean_range | 323 | .long arm920_dma_unmap_area |
300 | .long arm920_dma_flush_range | 324 | .long arm920_dma_flush_range |
301 | 325 | ||
302 | #endif | 326 | #endif |
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index ee111b00fa41..c0ff8e4b1074 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S | |||
@@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area) | |||
241 | * | 241 | * |
242 | * (same as v4wb) | 242 | * (same as v4wb) |
243 | */ | 243 | */ |
244 | ENTRY(arm922_dma_inv_range) | 244 | arm922_dma_inv_range: |
245 | tst r0, #CACHE_DLINESIZE - 1 | 245 | tst r0, #CACHE_DLINESIZE - 1 |
246 | bic r0, r0, #CACHE_DLINESIZE - 1 | 246 | bic r0, r0, #CACHE_DLINESIZE - 1 |
247 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 247 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -264,7 +264,7 @@ ENTRY(arm922_dma_inv_range) | |||
264 | * | 264 | * |
265 | * (same as v4wb) | 265 | * (same as v4wb) |
266 | */ | 266 | */ |
267 | ENTRY(arm922_dma_clean_range) | 267 | arm922_dma_clean_range: |
268 | bic r0, r0, #CACHE_DLINESIZE - 1 | 268 | bic r0, r0, #CACHE_DLINESIZE - 1 |
269 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 269 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
270 | add r0, r0, #CACHE_DLINESIZE | 270 | add r0, r0, #CACHE_DLINESIZE |
@@ -290,6 +290,30 @@ ENTRY(arm922_dma_flush_range) | |||
290 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 290 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
291 | mov pc, lr | 291 | mov pc, lr |
292 | 292 | ||
293 | /* | ||
294 | * dma_map_area(start, size, dir) | ||
295 | * - start - kernel virtual start address | ||
296 | * - size - size of region | ||
297 | * - dir - DMA direction | ||
298 | */ | ||
299 | ENTRY(arm922_dma_map_area) | ||
300 | add r1, r1, r0 | ||
301 | cmp r2, #DMA_TO_DEVICE | ||
302 | beq arm922_dma_clean_range | ||
303 | bcs arm922_dma_inv_range | ||
304 | b arm922_dma_flush_range | ||
305 | ENDPROC(arm922_dma_map_area) | ||
306 | |||
307 | /* | ||
308 | * dma_unmap_area(start, size, dir) | ||
309 | * - start - kernel virtual start address | ||
310 | * - size - size of region | ||
311 | * - dir - DMA direction | ||
312 | */ | ||
313 | ENTRY(arm922_dma_unmap_area) | ||
314 | mov pc, lr | ||
315 | ENDPROC(arm922_dma_unmap_area) | ||
316 | |||
293 | ENTRY(arm922_cache_fns) | 317 | ENTRY(arm922_cache_fns) |
294 | .long arm922_flush_kern_cache_all | 318 | .long arm922_flush_kern_cache_all |
295 | .long arm922_flush_user_cache_all | 319 | .long arm922_flush_user_cache_all |
@@ -297,8 +321,8 @@ ENTRY(arm922_cache_fns) | |||
297 | .long arm922_coherent_kern_range | 321 | .long arm922_coherent_kern_range |
298 | .long arm922_coherent_user_range | 322 | .long arm922_coherent_user_range |
299 | .long arm922_flush_kern_dcache_area | 323 | .long arm922_flush_kern_dcache_area |
300 | .long arm922_dma_inv_range | 324 | .long arm922_dma_map_area |
301 | .long arm922_dma_clean_range | 325 | .long arm922_dma_unmap_area |
302 | .long arm922_dma_flush_range | 326 | .long arm922_dma_flush_range |
303 | 327 | ||
304 | #endif | 328 | #endif |
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 8deb5bde58e4..3c6cffe400f6 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S | |||
@@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area) | |||
283 | * | 283 | * |
284 | * (same as v4wb) | 284 | * (same as v4wb) |
285 | */ | 285 | */ |
286 | ENTRY(arm925_dma_inv_range) | 286 | arm925_dma_inv_range: |
287 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 287 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
288 | tst r0, #CACHE_DLINESIZE - 1 | 288 | tst r0, #CACHE_DLINESIZE - 1 |
289 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 289 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -308,7 +308,7 @@ ENTRY(arm925_dma_inv_range) | |||
308 | * | 308 | * |
309 | * (same as v4wb) | 309 | * (same as v4wb) |
310 | */ | 310 | */ |
311 | ENTRY(arm925_dma_clean_range) | 311 | arm925_dma_clean_range: |
312 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 312 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
313 | bic r0, r0, #CACHE_DLINESIZE - 1 | 313 | bic r0, r0, #CACHE_DLINESIZE - 1 |
314 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 314 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -341,6 +341,30 @@ ENTRY(arm925_dma_flush_range) | |||
341 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 341 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
342 | mov pc, lr | 342 | mov pc, lr |
343 | 343 | ||
344 | /* | ||
345 | * dma_map_area(start, size, dir) | ||
346 | * - start - kernel virtual start address | ||
347 | * - size - size of region | ||
348 | * - dir - DMA direction | ||
349 | */ | ||
350 | ENTRY(arm925_dma_map_area) | ||
351 | add r1, r1, r0 | ||
352 | cmp r2, #DMA_TO_DEVICE | ||
353 | beq arm925_dma_clean_range | ||
354 | bcs arm925_dma_inv_range | ||
355 | b arm925_dma_flush_range | ||
356 | ENDPROC(arm925_dma_map_area) | ||
357 | |||
358 | /* | ||
359 | * dma_unmap_area(start, size, dir) | ||
360 | * - start - kernel virtual start address | ||
361 | * - size - size of region | ||
362 | * - dir - DMA direction | ||
363 | */ | ||
364 | ENTRY(arm925_dma_unmap_area) | ||
365 | mov pc, lr | ||
366 | ENDPROC(arm925_dma_unmap_area) | ||
367 | |||
344 | ENTRY(arm925_cache_fns) | 368 | ENTRY(arm925_cache_fns) |
345 | .long arm925_flush_kern_cache_all | 369 | .long arm925_flush_kern_cache_all |
346 | .long arm925_flush_user_cache_all | 370 | .long arm925_flush_user_cache_all |
@@ -348,8 +372,8 @@ ENTRY(arm925_cache_fns) | |||
348 | .long arm925_coherent_kern_range | 372 | .long arm925_coherent_kern_range |
349 | .long arm925_coherent_user_range | 373 | .long arm925_coherent_user_range |
350 | .long arm925_flush_kern_dcache_area | 374 | .long arm925_flush_kern_dcache_area |
351 | .long arm925_dma_inv_range | 375 | .long arm925_dma_map_area |
352 | .long arm925_dma_clean_range | 376 | .long arm925_dma_unmap_area |
353 | .long arm925_dma_flush_range | 377 | .long arm925_dma_flush_range |
354 | 378 | ||
355 | ENTRY(cpu_arm925_dcache_clean_area) | 379 | ENTRY(cpu_arm925_dcache_clean_area) |
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 64db6e275a44..75b707c9cce1 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area) | |||
246 | * | 246 | * |
247 | * (same as v4wb) | 247 | * (same as v4wb) |
248 | */ | 248 | */ |
249 | ENTRY(arm926_dma_inv_range) | 249 | arm926_dma_inv_range: |
250 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 250 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
251 | tst r0, #CACHE_DLINESIZE - 1 | 251 | tst r0, #CACHE_DLINESIZE - 1 |
252 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 252 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -271,7 +271,7 @@ ENTRY(arm926_dma_inv_range) | |||
271 | * | 271 | * |
272 | * (same as v4wb) | 272 | * (same as v4wb) |
273 | */ | 273 | */ |
274 | ENTRY(arm926_dma_clean_range) | 274 | arm926_dma_clean_range: |
275 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 275 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
276 | bic r0, r0, #CACHE_DLINESIZE - 1 | 276 | bic r0, r0, #CACHE_DLINESIZE - 1 |
277 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 277 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -304,6 +304,30 @@ ENTRY(arm926_dma_flush_range) | |||
304 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 304 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
305 | mov pc, lr | 305 | mov pc, lr |
306 | 306 | ||
307 | /* | ||
308 | * dma_map_area(start, size, dir) | ||
309 | * - start - kernel virtual start address | ||
310 | * - size - size of region | ||
311 | * - dir - DMA direction | ||
312 | */ | ||
313 | ENTRY(arm926_dma_map_area) | ||
314 | add r1, r1, r0 | ||
315 | cmp r2, #DMA_TO_DEVICE | ||
316 | beq arm926_dma_clean_range | ||
317 | bcs arm926_dma_inv_range | ||
318 | b arm926_dma_flush_range | ||
319 | ENDPROC(arm926_dma_map_area) | ||
320 | |||
321 | /* | ||
322 | * dma_unmap_area(start, size, dir) | ||
323 | * - start - kernel virtual start address | ||
324 | * - size - size of region | ||
325 | * - dir - DMA direction | ||
326 | */ | ||
327 | ENTRY(arm926_dma_unmap_area) | ||
328 | mov pc, lr | ||
329 | ENDPROC(arm926_dma_unmap_area) | ||
330 | |||
307 | ENTRY(arm926_cache_fns) | 331 | ENTRY(arm926_cache_fns) |
308 | .long arm926_flush_kern_cache_all | 332 | .long arm926_flush_kern_cache_all |
309 | .long arm926_flush_user_cache_all | 333 | .long arm926_flush_user_cache_all |
@@ -311,8 +335,8 @@ ENTRY(arm926_cache_fns) | |||
311 | .long arm926_coherent_kern_range | 335 | .long arm926_coherent_kern_range |
312 | .long arm926_coherent_user_range | 336 | .long arm926_coherent_user_range |
313 | .long arm926_flush_kern_dcache_area | 337 | .long arm926_flush_kern_dcache_area |
314 | .long arm926_dma_inv_range | 338 | .long arm926_dma_map_area |
315 | .long arm926_dma_clean_range | 339 | .long arm926_dma_unmap_area |
316 | .long arm926_dma_flush_range | 340 | .long arm926_dma_flush_range |
317 | 341 | ||
318 | ENTRY(cpu_arm926_dcache_clean_area) | 342 | ENTRY(cpu_arm926_dcache_clean_area) |
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 8196b9f401fb..1af1657819eb 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S | |||
@@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area) | |||
171 | * - start - virtual start address | 171 | * - start - virtual start address |
172 | * - end - virtual end address | 172 | * - end - virtual end address |
173 | */ | 173 | */ |
174 | ENTRY(arm940_dma_inv_range) | 174 | arm940_dma_inv_range: |
175 | mov ip, #0 | 175 | mov ip, #0 |
176 | mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments | 176 | mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments |
177 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries | 177 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries |
@@ -192,7 +192,7 @@ ENTRY(arm940_dma_inv_range) | |||
192 | * - start - virtual start address | 192 | * - start - virtual start address |
193 | * - end - virtual end address | 193 | * - end - virtual end address |
194 | */ | 194 | */ |
195 | ENTRY(arm940_dma_clean_range) | 195 | arm940_dma_clean_range: |
196 | ENTRY(cpu_arm940_dcache_clean_area) | 196 | ENTRY(cpu_arm940_dcache_clean_area) |
197 | mov ip, #0 | 197 | mov ip, #0 |
198 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 198 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
@@ -233,6 +233,30 @@ ENTRY(arm940_dma_flush_range) | |||
233 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 233 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
234 | mov pc, lr | 234 | mov pc, lr |
235 | 235 | ||
236 | /* | ||
237 | * dma_map_area(start, size, dir) | ||
238 | * - start - kernel virtual start address | ||
239 | * - size - size of region | ||
240 | * - dir - DMA direction | ||
241 | */ | ||
242 | ENTRY(arm940_dma_map_area) | ||
243 | add r1, r1, r0 | ||
244 | cmp r2, #DMA_TO_DEVICE | ||
245 | beq arm940_dma_clean_range | ||
246 | bcs arm940_dma_inv_range | ||
247 | b arm940_dma_flush_range | ||
248 | ENDPROC(arm940_dma_map_area) | ||
249 | |||
250 | /* | ||
251 | * dma_unmap_area(start, size, dir) | ||
252 | * - start - kernel virtual start address | ||
253 | * - size - size of region | ||
254 | * - dir - DMA direction | ||
255 | */ | ||
256 | ENTRY(arm940_dma_unmap_area) | ||
257 | mov pc, lr | ||
258 | ENDPROC(arm940_dma_unmap_area) | ||
259 | |||
236 | ENTRY(arm940_cache_fns) | 260 | ENTRY(arm940_cache_fns) |
237 | .long arm940_flush_kern_cache_all | 261 | .long arm940_flush_kern_cache_all |
238 | .long arm940_flush_user_cache_all | 262 | .long arm940_flush_user_cache_all |
@@ -240,8 +264,8 @@ ENTRY(arm940_cache_fns) | |||
240 | .long arm940_coherent_kern_range | 264 | .long arm940_coherent_kern_range |
241 | .long arm940_coherent_user_range | 265 | .long arm940_coherent_user_range |
242 | .long arm940_flush_kern_dcache_area | 266 | .long arm940_flush_kern_dcache_area |
243 | .long arm940_dma_inv_range | 267 | .long arm940_dma_map_area |
244 | .long arm940_dma_clean_range | 268 | .long arm940_dma_unmap_area |
245 | .long arm940_dma_flush_range | 269 | .long arm940_dma_flush_range |
246 | 270 | ||
247 | __INIT | 271 | __INIT |
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 9a951239c86c..1664b6aaff79 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S | |||
@@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area) | |||
215 | * - end - virtual end address | 215 | * - end - virtual end address |
216 | * (same as arm926) | 216 | * (same as arm926) |
217 | */ | 217 | */ |
218 | ENTRY(arm946_dma_inv_range) | 218 | arm946_dma_inv_range: |
219 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 219 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
220 | tst r0, #CACHE_DLINESIZE - 1 | 220 | tst r0, #CACHE_DLINESIZE - 1 |
221 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 221 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -240,7 +240,7 @@ ENTRY(arm946_dma_inv_range) | |||
240 | * | 240 | * |
241 | * (same as arm926) | 241 | * (same as arm926) |
242 | */ | 242 | */ |
243 | ENTRY(arm946_dma_clean_range) | 243 | arm946_dma_clean_range: |
244 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 244 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
245 | bic r0, r0, #CACHE_DLINESIZE - 1 | 245 | bic r0, r0, #CACHE_DLINESIZE - 1 |
246 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 246 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -275,6 +275,30 @@ ENTRY(arm946_dma_flush_range) | |||
275 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 275 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
276 | mov pc, lr | 276 | mov pc, lr |
277 | 277 | ||
278 | /* | ||
279 | * dma_map_area(start, size, dir) | ||
280 | * - start - kernel virtual start address | ||
281 | * - size - size of region | ||
282 | * - dir - DMA direction | ||
283 | */ | ||
284 | ENTRY(arm946_dma_map_area) | ||
285 | add r1, r1, r0 | ||
286 | cmp r2, #DMA_TO_DEVICE | ||
287 | beq arm946_dma_clean_range | ||
288 | bcs arm946_dma_inv_range | ||
289 | b arm946_dma_flush_range | ||
290 | ENDPROC(arm946_dma_map_area) | ||
291 | |||
292 | /* | ||
293 | * dma_unmap_area(start, size, dir) | ||
294 | * - start - kernel virtual start address | ||
295 | * - size - size of region | ||
296 | * - dir - DMA direction | ||
297 | */ | ||
298 | ENTRY(arm946_dma_unmap_area) | ||
299 | mov pc, lr | ||
300 | ENDPROC(arm946_dma_unmap_area) | ||
301 | |||
278 | ENTRY(arm946_cache_fns) | 302 | ENTRY(arm946_cache_fns) |
279 | .long arm946_flush_kern_cache_all | 303 | .long arm946_flush_kern_cache_all |
280 | .long arm946_flush_user_cache_all | 304 | .long arm946_flush_user_cache_all |
@@ -282,8 +306,8 @@ ENTRY(arm946_cache_fns) | |||
282 | .long arm946_coherent_kern_range | 306 | .long arm946_coherent_kern_range |
283 | .long arm946_coherent_user_range | 307 | .long arm946_coherent_user_range |
284 | .long arm946_flush_kern_dcache_area | 308 | .long arm946_flush_kern_dcache_area |
285 | .long arm946_dma_inv_range | 309 | .long arm946_dma_map_area |
286 | .long arm946_dma_clean_range | 310 | .long arm946_dma_unmap_area |
287 | .long arm946_dma_flush_range | 311 | .long arm946_dma_flush_range |
288 | 312 | ||
289 | 313 | ||
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index dbc39383e66a..53e632343849 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area) | |||
274 | * (same as v4wb) | 274 | * (same as v4wb) |
275 | */ | 275 | */ |
276 | .align 5 | 276 | .align 5 |
277 | ENTRY(feroceon_dma_inv_range) | 277 | feroceon_dma_inv_range: |
278 | tst r0, #CACHE_DLINESIZE - 1 | 278 | tst r0, #CACHE_DLINESIZE - 1 |
279 | bic r0, r0, #CACHE_DLINESIZE - 1 | 279 | bic r0, r0, #CACHE_DLINESIZE - 1 |
280 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 280 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -288,7 +288,7 @@ ENTRY(feroceon_dma_inv_range) | |||
288 | mov pc, lr | 288 | mov pc, lr |
289 | 289 | ||
290 | .align 5 | 290 | .align 5 |
291 | ENTRY(feroceon_range_dma_inv_range) | 291 | feroceon_range_dma_inv_range: |
292 | mrs r2, cpsr | 292 | mrs r2, cpsr |
293 | tst r0, #CACHE_DLINESIZE - 1 | 293 | tst r0, #CACHE_DLINESIZE - 1 |
294 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 294 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -314,7 +314,7 @@ ENTRY(feroceon_range_dma_inv_range) | |||
314 | * (same as v4wb) | 314 | * (same as v4wb) |
315 | */ | 315 | */ |
316 | .align 5 | 316 | .align 5 |
317 | ENTRY(feroceon_dma_clean_range) | 317 | feroceon_dma_clean_range: |
318 | bic r0, r0, #CACHE_DLINESIZE - 1 | 318 | bic r0, r0, #CACHE_DLINESIZE - 1 |
319 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 319 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
320 | add r0, r0, #CACHE_DLINESIZE | 320 | add r0, r0, #CACHE_DLINESIZE |
@@ -324,7 +324,7 @@ ENTRY(feroceon_dma_clean_range) | |||
324 | mov pc, lr | 324 | mov pc, lr |
325 | 325 | ||
326 | .align 5 | 326 | .align 5 |
327 | ENTRY(feroceon_range_dma_clean_range) | 327 | feroceon_range_dma_clean_range: |
328 | mrs r2, cpsr | 328 | mrs r2, cpsr |
329 | cmp r1, r0 | 329 | cmp r1, r0 |
330 | subne r1, r1, #1 @ top address is inclusive | 330 | subne r1, r1, #1 @ top address is inclusive |
@@ -367,6 +367,44 @@ ENTRY(feroceon_range_dma_flush_range) | |||
367 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 367 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
368 | mov pc, lr | 368 | mov pc, lr |
369 | 369 | ||
370 | /* | ||
371 | * dma_map_area(start, size, dir) | ||
372 | * - start - kernel virtual start address | ||
373 | * - size - size of region | ||
374 | * - dir - DMA direction | ||
375 | */ | ||
376 | ENTRY(feroceon_dma_map_area) | ||
377 | add r1, r1, r0 | ||
378 | cmp r2, #DMA_TO_DEVICE | ||
379 | beq feroceon_dma_clean_range | ||
380 | bcs feroceon_dma_inv_range | ||
381 | b feroceon_dma_flush_range | ||
382 | ENDPROC(feroceon_dma_map_area) | ||
383 | |||
384 | /* | ||
385 | * dma_map_area(start, size, dir) | ||
386 | * - start - kernel virtual start address | ||
387 | * - size - size of region | ||
388 | * - dir - DMA direction | ||
389 | */ | ||
390 | ENTRY(feroceon_range_dma_map_area) | ||
391 | add r1, r1, r0 | ||
392 | cmp r2, #DMA_TO_DEVICE | ||
393 | beq feroceon_range_dma_clean_range | ||
394 | bcs feroceon_range_dma_inv_range | ||
395 | b feroceon_range_dma_flush_range | ||
396 | ENDPROC(feroceon_range_dma_map_area) | ||
397 | |||
398 | /* | ||
399 | * dma_unmap_area(start, size, dir) | ||
400 | * - start - kernel virtual start address | ||
401 | * - size - size of region | ||
402 | * - dir - DMA direction | ||
403 | */ | ||
404 | ENTRY(feroceon_dma_unmap_area) | ||
405 | mov pc, lr | ||
406 | ENDPROC(feroceon_dma_unmap_area) | ||
407 | |||
370 | ENTRY(feroceon_cache_fns) | 408 | ENTRY(feroceon_cache_fns) |
371 | .long feroceon_flush_kern_cache_all | 409 | .long feroceon_flush_kern_cache_all |
372 | .long feroceon_flush_user_cache_all | 410 | .long feroceon_flush_user_cache_all |
@@ -374,8 +412,8 @@ ENTRY(feroceon_cache_fns) | |||
374 | .long feroceon_coherent_kern_range | 412 | .long feroceon_coherent_kern_range |
375 | .long feroceon_coherent_user_range | 413 | .long feroceon_coherent_user_range |
376 | .long feroceon_flush_kern_dcache_area | 414 | .long feroceon_flush_kern_dcache_area |
377 | .long feroceon_dma_inv_range | 415 | .long feroceon_dma_map_area |
378 | .long feroceon_dma_clean_range | 416 | .long feroceon_dma_unmap_area |
379 | .long feroceon_dma_flush_range | 417 | .long feroceon_dma_flush_range |
380 | 418 | ||
381 | ENTRY(feroceon_range_cache_fns) | 419 | ENTRY(feroceon_range_cache_fns) |
@@ -385,8 +423,8 @@ ENTRY(feroceon_range_cache_fns) | |||
385 | .long feroceon_coherent_kern_range | 423 | .long feroceon_coherent_kern_range |
386 | .long feroceon_coherent_user_range | 424 | .long feroceon_coherent_user_range |
387 | .long feroceon_range_flush_kern_dcache_area | 425 | .long feroceon_range_flush_kern_dcache_area |
388 | .long feroceon_range_dma_inv_range | 426 | .long feroceon_range_dma_map_area |
389 | .long feroceon_range_dma_clean_range | 427 | .long feroceon_dma_unmap_area |
390 | .long feroceon_range_dma_flush_range | 428 | .long feroceon_range_dma_flush_range |
391 | 429 | ||
392 | .align 5 | 430 | .align 5 |
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index 9674d36cc97d..caa31154e7db 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S | |||
@@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area) | |||
218 | * | 218 | * |
219 | * (same as v4wb) | 219 | * (same as v4wb) |
220 | */ | 220 | */ |
221 | ENTRY(mohawk_dma_inv_range) | 221 | mohawk_dma_inv_range: |
222 | tst r0, #CACHE_DLINESIZE - 1 | 222 | tst r0, #CACHE_DLINESIZE - 1 |
223 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 223 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
224 | tst r1, #CACHE_DLINESIZE - 1 | 224 | tst r1, #CACHE_DLINESIZE - 1 |
@@ -241,7 +241,7 @@ ENTRY(mohawk_dma_inv_range) | |||
241 | * | 241 | * |
242 | * (same as v4wb) | 242 | * (same as v4wb) |
243 | */ | 243 | */ |
244 | ENTRY(mohawk_dma_clean_range) | 244 | mohawk_dma_clean_range: |
245 | bic r0, r0, #CACHE_DLINESIZE - 1 | 245 | bic r0, r0, #CACHE_DLINESIZE - 1 |
246 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 246 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
247 | add r0, r0, #CACHE_DLINESIZE | 247 | add r0, r0, #CACHE_DLINESIZE |
@@ -268,6 +268,30 @@ ENTRY(mohawk_dma_flush_range) | |||
268 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 268 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
269 | mov pc, lr | 269 | mov pc, lr |
270 | 270 | ||
271 | /* | ||
272 | * dma_map_area(start, size, dir) | ||
273 | * - start - kernel virtual start address | ||
274 | * - size - size of region | ||
275 | * - dir - DMA direction | ||
276 | */ | ||
277 | ENTRY(mohawk_dma_map_area) | ||
278 | add r1, r1, r0 | ||
279 | cmp r2, #DMA_TO_DEVICE | ||
280 | beq mohawk_dma_clean_range | ||
281 | bcs mohawk_dma_inv_range | ||
282 | b mohawk_dma_flush_range | ||
283 | ENDPROC(mohawk_dma_map_area) | ||
284 | |||
285 | /* | ||
286 | * dma_unmap_area(start, size, dir) | ||
287 | * - start - kernel virtual start address | ||
288 | * - size - size of region | ||
289 | * - dir - DMA direction | ||
290 | */ | ||
291 | ENTRY(mohawk_dma_unmap_area) | ||
292 | mov pc, lr | ||
293 | ENDPROC(mohawk_dma_unmap_area) | ||
294 | |||
271 | ENTRY(mohawk_cache_fns) | 295 | ENTRY(mohawk_cache_fns) |
272 | .long mohawk_flush_kern_cache_all | 296 | .long mohawk_flush_kern_cache_all |
273 | .long mohawk_flush_user_cache_all | 297 | .long mohawk_flush_user_cache_all |
@@ -275,8 +299,8 @@ ENTRY(mohawk_cache_fns) | |||
275 | .long mohawk_coherent_kern_range | 299 | .long mohawk_coherent_kern_range |
276 | .long mohawk_coherent_user_range | 300 | .long mohawk_coherent_user_range |
277 | .long mohawk_flush_kern_dcache_area | 301 | .long mohawk_flush_kern_dcache_area |
278 | .long mohawk_dma_inv_range | 302 | .long mohawk_dma_map_area |
279 | .long mohawk_dma_clean_range | 303 | .long mohawk_dma_unmap_area |
280 | .long mohawk_dma_flush_range | 304 | .long mohawk_dma_flush_range |
281 | 305 | ||
282 | ENTRY(cpu_mohawk_dcache_clean_area) | 306 | ENTRY(cpu_mohawk_dcache_clean_area) |
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 8e4f6dca8997..e5797f1c1db7 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area) | |||
257 | * - start - virtual start address | 257 | * - start - virtual start address |
258 | * - end - virtual end address | 258 | * - end - virtual end address |
259 | */ | 259 | */ |
260 | ENTRY(xsc3_dma_inv_range) | 260 | xsc3_dma_inv_range: |
261 | tst r0, #CACHELINESIZE - 1 | 261 | tst r0, #CACHELINESIZE - 1 |
262 | bic r0, r0, #CACHELINESIZE - 1 | 262 | bic r0, r0, #CACHELINESIZE - 1 |
263 | mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line | 263 | mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line |
@@ -278,7 +278,7 @@ ENTRY(xsc3_dma_inv_range) | |||
278 | * - start - virtual start address | 278 | * - start - virtual start address |
279 | * - end - virtual end address | 279 | * - end - virtual end address |
280 | */ | 280 | */ |
281 | ENTRY(xsc3_dma_clean_range) | 281 | xsc3_dma_clean_range: |
282 | bic r0, r0, #CACHELINESIZE - 1 | 282 | bic r0, r0, #CACHELINESIZE - 1 |
283 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line | 283 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line |
284 | add r0, r0, #CACHELINESIZE | 284 | add r0, r0, #CACHELINESIZE |
@@ -304,6 +304,30 @@ ENTRY(xsc3_dma_flush_range) | |||
304 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | 304 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
305 | mov pc, lr | 305 | mov pc, lr |
306 | 306 | ||
307 | /* | ||
308 | * dma_map_area(start, size, dir) | ||
309 | * - start - kernel virtual start address | ||
310 | * - size - size of region | ||
311 | * - dir - DMA direction | ||
312 | */ | ||
313 | ENTRY(xsc3_dma_map_area) | ||
314 | add r1, r1, r0 | ||
315 | cmp r2, #DMA_TO_DEVICE | ||
316 | beq xsc3_dma_clean_range | ||
317 | bcs xsc3_dma_inv_range | ||
318 | b xsc3_dma_flush_range | ||
319 | ENDPROC(xsc3_dma_map_area) | ||
320 | |||
321 | /* | ||
322 | * dma_unmap_area(start, size, dir) | ||
323 | * - start - kernel virtual start address | ||
324 | * - size - size of region | ||
325 | * - dir - DMA direction | ||
326 | */ | ||
327 | ENTRY(xsc3_dma_unmap_area) | ||
328 | mov pc, lr | ||
329 | ENDPROC(xsc3_dma_unmap_area) | ||
330 | |||
307 | ENTRY(xsc3_cache_fns) | 331 | ENTRY(xsc3_cache_fns) |
308 | .long xsc3_flush_kern_cache_all | 332 | .long xsc3_flush_kern_cache_all |
309 | .long xsc3_flush_user_cache_all | 333 | .long xsc3_flush_user_cache_all |
@@ -311,8 +335,8 @@ ENTRY(xsc3_cache_fns) | |||
311 | .long xsc3_coherent_kern_range | 335 | .long xsc3_coherent_kern_range |
312 | .long xsc3_coherent_user_range | 336 | .long xsc3_coherent_user_range |
313 | .long xsc3_flush_kern_dcache_area | 337 | .long xsc3_flush_kern_dcache_area |
314 | .long xsc3_dma_inv_range | 338 | .long xsc3_dma_map_area |
315 | .long xsc3_dma_clean_range | 339 | .long xsc3_dma_unmap_area |
316 | .long xsc3_dma_flush_range | 340 | .long xsc3_dma_flush_range |
317 | 341 | ||
318 | ENTRY(cpu_xsc3_dcache_clean_area) | 342 | ENTRY(cpu_xsc3_dcache_clean_area) |
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 93df47265f2d..63037e2162f2 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area) | |||
315 | * - start - virtual start address | 315 | * - start - virtual start address |
316 | * - end - virtual end address | 316 | * - end - virtual end address |
317 | */ | 317 | */ |
318 | ENTRY(xscale_dma_inv_range) | 318 | xscale_dma_inv_range: |
319 | tst r0, #CACHELINESIZE - 1 | 319 | tst r0, #CACHELINESIZE - 1 |
320 | bic r0, r0, #CACHELINESIZE - 1 | 320 | bic r0, r0, #CACHELINESIZE - 1 |
321 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 321 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -336,7 +336,7 @@ ENTRY(xscale_dma_inv_range) | |||
336 | * - start - virtual start address | 336 | * - start - virtual start address |
337 | * - end - virtual end address | 337 | * - end - virtual end address |
338 | */ | 338 | */ |
339 | ENTRY(xscale_dma_clean_range) | 339 | xscale_dma_clean_range: |
340 | bic r0, r0, #CACHELINESIZE - 1 | 340 | bic r0, r0, #CACHELINESIZE - 1 |
341 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 341 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
342 | add r0, r0, #CACHELINESIZE | 342 | add r0, r0, #CACHELINESIZE |
@@ -363,6 +363,43 @@ ENTRY(xscale_dma_flush_range) | |||
363 | mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer | 363 | mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
364 | mov pc, lr | 364 | mov pc, lr |
365 | 365 | ||
366 | /* | ||
367 | * dma_map_area(start, size, dir) | ||
368 | * - start - kernel virtual start address | ||
369 | * - size - size of region | ||
370 | * - dir - DMA direction | ||
371 | */ | ||
372 | ENTRY(xscale_dma_map_area) | ||
373 | add r1, r1, r0 | ||
374 | cmp r2, #DMA_TO_DEVICE | ||
375 | beq xscale_dma_clean_range | ||
376 | bcs xscale_dma_inv_range | ||
377 | b xscale_dma_flush_range | ||
378 | ENDPROC(xscale_dma_map_area) | ||
379 | |||
380 | /* | ||
381 | * dma_map_area(start, size, dir) | ||
382 | * - start - kernel virtual start address | ||
383 | * - size - size of region | ||
384 | * - dir - DMA direction | ||
385 | */ | ||
386 | ENTRY(xscale_dma_a0_map_area) | ||
387 | add r1, r1, r0 | ||
388 | teq r2, #DMA_TO_DEVICE | ||
389 | beq xscale_dma_clean_range | ||
390 | b xscale_dma_flush_range | ||
391 | ENDPROC(xscsale_dma_a0_map_area) | ||
392 | |||
393 | /* | ||
394 | * dma_unmap_area(start, size, dir) | ||
395 | * - start - kernel virtual start address | ||
396 | * - size - size of region | ||
397 | * - dir - DMA direction | ||
398 | */ | ||
399 | ENTRY(xscale_dma_unmap_area) | ||
400 | mov pc, lr | ||
401 | ENDPROC(xscale_dma_unmap_area) | ||
402 | |||
366 | ENTRY(xscale_cache_fns) | 403 | ENTRY(xscale_cache_fns) |
367 | .long xscale_flush_kern_cache_all | 404 | .long xscale_flush_kern_cache_all |
368 | .long xscale_flush_user_cache_all | 405 | .long xscale_flush_user_cache_all |
@@ -370,8 +407,8 @@ ENTRY(xscale_cache_fns) | |||
370 | .long xscale_coherent_kern_range | 407 | .long xscale_coherent_kern_range |
371 | .long xscale_coherent_user_range | 408 | .long xscale_coherent_user_range |
372 | .long xscale_flush_kern_dcache_area | 409 | .long xscale_flush_kern_dcache_area |
373 | .long xscale_dma_inv_range | 410 | .long xscale_dma_map_area |
374 | .long xscale_dma_clean_range | 411 | .long xscale_dma_unmap_area |
375 | .long xscale_dma_flush_range | 412 | .long xscale_dma_flush_range |
376 | 413 | ||
377 | /* | 414 | /* |
@@ -394,8 +431,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns) | |||
394 | .long xscale_coherent_kern_range | 431 | .long xscale_coherent_kern_range |
395 | .long xscale_coherent_user_range | 432 | .long xscale_coherent_user_range |
396 | .long xscale_flush_kern_dcache_area | 433 | .long xscale_flush_kern_dcache_area |
397 | .long xscale_dma_flush_range | 434 | .long xscale_dma_a0_map_area |
398 | .long xscale_dma_clean_range | 435 | .long xscale_dma_unmap_area |
399 | .long xscale_dma_flush_range | 436 | .long xscale_dma_flush_range |
400 | 437 | ||
401 | ENTRY(cpu_xscale_dcache_clean_area) | 438 | ENTRY(cpu_xscale_dcache_clean_area) |
diff --git a/arch/arm/oprofile/op_model_arm11_core.c b/arch/arm/oprofile/op_model_arm11_core.c index ad80752cb9fb..ef3e2653b90c 100644 --- a/arch/arm/oprofile/op_model_arm11_core.c +++ b/arch/arm/oprofile/op_model_arm11_core.c | |||
@@ -132,7 +132,7 @@ static irqreturn_t arm11_pmu_interrupt(int irq, void *arg) | |||
132 | return IRQ_HANDLED; | 132 | return IRQ_HANDLED; |
133 | } | 133 | } |
134 | 134 | ||
135 | int arm11_request_interrupts(int *irqs, int nr) | 135 | int arm11_request_interrupts(const int *irqs, int nr) |
136 | { | 136 | { |
137 | unsigned int i; | 137 | unsigned int i; |
138 | int ret = 0; | 138 | int ret = 0; |
@@ -153,7 +153,7 @@ int arm11_request_interrupts(int *irqs, int nr) | |||
153 | return ret; | 153 | return ret; |
154 | } | 154 | } |
155 | 155 | ||
156 | void arm11_release_interrupts(int *irqs, int nr) | 156 | void arm11_release_interrupts(const int *irqs, int nr) |
157 | { | 157 | { |
158 | unsigned int i; | 158 | unsigned int i; |
159 | 159 | ||
diff --git a/arch/arm/oprofile/op_model_arm11_core.h b/arch/arm/oprofile/op_model_arm11_core.h index 6f8538e5a960..1902b99d9dfd 100644 --- a/arch/arm/oprofile/op_model_arm11_core.h +++ b/arch/arm/oprofile/op_model_arm11_core.h | |||
@@ -39,7 +39,7 @@ | |||
39 | int arm11_setup_pmu(void); | 39 | int arm11_setup_pmu(void); |
40 | int arm11_start_pmu(void); | 40 | int arm11_start_pmu(void); |
41 | int arm11_stop_pmu(void); | 41 | int arm11_stop_pmu(void); |
42 | int arm11_request_interrupts(int *, int); | 42 | int arm11_request_interrupts(const int *, int); |
43 | void arm11_release_interrupts(int *, int); | 43 | void arm11_release_interrupts(const int *, int); |
44 | 44 | ||
45 | #endif | 45 | #endif |
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c index 4ce0f9801e2e..f73ce875a395 100644 --- a/arch/arm/oprofile/op_model_mpcore.c +++ b/arch/arm/oprofile/op_model_mpcore.c | |||
@@ -32,6 +32,7 @@ | |||
32 | /* #define DEBUG */ | 32 | /* #define DEBUG */ |
33 | #include <linux/types.h> | 33 | #include <linux/types.h> |
34 | #include <linux/errno.h> | 34 | #include <linux/errno.h> |
35 | #include <linux/err.h> | ||
35 | #include <linux/sched.h> | 36 | #include <linux/sched.h> |
36 | #include <linux/oprofile.h> | 37 | #include <linux/oprofile.h> |
37 | #include <linux/interrupt.h> | 38 | #include <linux/interrupt.h> |
@@ -43,6 +44,7 @@ | |||
43 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
44 | #include <mach/board-eb.h> | 45 | #include <mach/board-eb.h> |
45 | #include <asm/system.h> | 46 | #include <asm/system.h> |
47 | #include <asm/pmu.h> | ||
46 | 48 | ||
47 | #include "op_counter.h" | 49 | #include "op_counter.h" |
48 | #include "op_arm_model.h" | 50 | #include "op_arm_model.h" |
@@ -58,6 +60,7 @@ | |||
58 | * Bitmask of used SCU counters | 60 | * Bitmask of used SCU counters |
59 | */ | 61 | */ |
60 | static unsigned int scu_em_used; | 62 | static unsigned int scu_em_used; |
63 | static const struct pmu_irqs *pmu_irqs; | ||
61 | 64 | ||
62 | /* | 65 | /* |
63 | * 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number) | 66 | * 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number) |
@@ -225,33 +228,40 @@ static int em_setup_ctrs(void) | |||
225 | return 0; | 228 | return 0; |
226 | } | 229 | } |
227 | 230 | ||
228 | static int arm11_irqs[] = { | ||
229 | [0] = IRQ_EB11MP_PMU_CPU0, | ||
230 | [1] = IRQ_EB11MP_PMU_CPU1, | ||
231 | [2] = IRQ_EB11MP_PMU_CPU2, | ||
232 | [3] = IRQ_EB11MP_PMU_CPU3 | ||
233 | }; | ||
234 | |||
235 | static int em_start(void) | 231 | static int em_start(void) |
236 | { | 232 | { |
237 | int ret; | 233 | int ret; |
238 | 234 | ||
239 | ret = arm11_request_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs)); | 235 | pmu_irqs = reserve_pmu(); |
236 | if (IS_ERR(pmu_irqs)) { | ||
237 | ret = PTR_ERR(pmu_irqs); | ||
238 | goto out; | ||
239 | } | ||
240 | |||
241 | ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); | ||
240 | if (ret == 0) { | 242 | if (ret == 0) { |
241 | em_call_function(arm11_start_pmu); | 243 | em_call_function(arm11_start_pmu); |
242 | 244 | ||
243 | ret = scu_start(); | 245 | ret = scu_start(); |
244 | if (ret) | 246 | if (ret) { |
245 | arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs)); | 247 | arm11_release_interrupts(pmu_irqs->irqs, |
248 | pmu_irqs->num_irqs); | ||
249 | } else { | ||
250 | release_pmu(pmu_irqs); | ||
251 | pmu_irqs = NULL; | ||
252 | } | ||
246 | } | 253 | } |
254 | |||
255 | out: | ||
247 | return ret; | 256 | return ret; |
248 | } | 257 | } |
249 | 258 | ||
250 | static void em_stop(void) | 259 | static void em_stop(void) |
251 | { | 260 | { |
252 | em_call_function(arm11_stop_pmu); | 261 | em_call_function(arm11_stop_pmu); |
253 | arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs)); | 262 | arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); |
254 | scu_stop(); | 263 | scu_stop(); |
264 | release_pmu(pmu_irqs); | ||
255 | } | 265 | } |
256 | 266 | ||
257 | /* | 267 | /* |
@@ -283,15 +293,7 @@ static int em_setup(void) | |||
283 | em_route_irq(IRQ_EB11MP_PMU_SCU6, 3); | 293 | em_route_irq(IRQ_EB11MP_PMU_SCU6, 3); |
284 | em_route_irq(IRQ_EB11MP_PMU_SCU7, 3); | 294 | em_route_irq(IRQ_EB11MP_PMU_SCU7, 3); |
285 | 295 | ||
286 | /* | 296 | return init_pmu(); |
287 | * Send CP15 PMU interrupts to the owner CPU. | ||
288 | */ | ||
289 | em_route_irq(IRQ_EB11MP_PMU_CPU0, 0); | ||
290 | em_route_irq(IRQ_EB11MP_PMU_CPU1, 1); | ||
291 | em_route_irq(IRQ_EB11MP_PMU_CPU2, 2); | ||
292 | em_route_irq(IRQ_EB11MP_PMU_CPU3, 3); | ||
293 | |||
294 | return 0; | ||
295 | } | 297 | } |
296 | 298 | ||
297 | struct op_arm_model_spec op_mpcore_spec = { | 299 | struct op_arm_model_spec op_mpcore_spec = { |
diff --git a/arch/arm/oprofile/op_model_v6.c b/arch/arm/oprofile/op_model_v6.c index f7d2ec5ee9a1..a22357a2fd08 100644 --- a/arch/arm/oprofile/op_model_v6.c +++ b/arch/arm/oprofile/op_model_v6.c | |||
@@ -19,39 +19,47 @@ | |||
19 | /* #define DEBUG */ | 19 | /* #define DEBUG */ |
20 | #include <linux/types.h> | 20 | #include <linux/types.h> |
21 | #include <linux/errno.h> | 21 | #include <linux/errno.h> |
22 | #include <linux/err.h> | ||
22 | #include <linux/sched.h> | 23 | #include <linux/sched.h> |
23 | #include <linux/oprofile.h> | 24 | #include <linux/oprofile.h> |
24 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
25 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
26 | #include <asm/system.h> | 27 | #include <asm/system.h> |
28 | #include <asm/pmu.h> | ||
27 | 29 | ||
28 | #include "op_counter.h" | 30 | #include "op_counter.h" |
29 | #include "op_arm_model.h" | 31 | #include "op_arm_model.h" |
30 | #include "op_model_arm11_core.h" | 32 | #include "op_model_arm11_core.h" |
31 | 33 | ||
32 | static int irqs[] = { | 34 | static const struct pmu_irqs *pmu_irqs; |
33 | #ifdef CONFIG_ARCH_OMAP2 | ||
34 | 3, | ||
35 | #endif | ||
36 | #ifdef CONFIG_ARCH_BCMRING | ||
37 | IRQ_PMUIRQ, /* for BCMRING, ARM PMU interrupt is 43 */ | ||
38 | #endif | ||
39 | }; | ||
40 | 35 | ||
41 | static void armv6_pmu_stop(void) | 36 | static void armv6_pmu_stop(void) |
42 | { | 37 | { |
43 | arm11_stop_pmu(); | 38 | arm11_stop_pmu(); |
44 | arm11_release_interrupts(irqs, ARRAY_SIZE(irqs)); | 39 | arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); |
40 | release_pmu(pmu_irqs); | ||
41 | pmu_irqs = NULL; | ||
45 | } | 42 | } |
46 | 43 | ||
47 | static int armv6_pmu_start(void) | 44 | static int armv6_pmu_start(void) |
48 | { | 45 | { |
49 | int ret; | 46 | int ret; |
50 | 47 | ||
51 | ret = arm11_request_interrupts(irqs, ARRAY_SIZE(irqs)); | 48 | pmu_irqs = reserve_pmu(); |
52 | if (ret >= 0) | 49 | if (IS_ERR(pmu_irqs)) { |
50 | ret = PTR_ERR(pmu_irqs); | ||
51 | goto out; | ||
52 | } | ||
53 | |||
54 | ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); | ||
55 | if (ret >= 0) { | ||
53 | ret = arm11_start_pmu(); | 56 | ret = arm11_start_pmu(); |
57 | } else { | ||
58 | release_pmu(pmu_irqs); | ||
59 | pmu_irqs = NULL; | ||
60 | } | ||
54 | 61 | ||
62 | out: | ||
55 | return ret; | 63 | return ret; |
56 | } | 64 | } |
57 | 65 | ||
diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c index 2088a6c0cc0e..8642d0891ae1 100644 --- a/arch/arm/oprofile/op_model_v7.c +++ b/arch/arm/oprofile/op_model_v7.c | |||
@@ -11,11 +11,14 @@ | |||
11 | */ | 11 | */ |
12 | #include <linux/types.h> | 12 | #include <linux/types.h> |
13 | #include <linux/errno.h> | 13 | #include <linux/errno.h> |
14 | #include <linux/err.h> | ||
14 | #include <linux/oprofile.h> | 15 | #include <linux/oprofile.h> |
15 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
16 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
17 | #include <linux/smp.h> | 18 | #include <linux/smp.h> |
18 | 19 | ||
20 | #include <asm/pmu.h> | ||
21 | |||
19 | #include "op_counter.h" | 22 | #include "op_counter.h" |
20 | #include "op_arm_model.h" | 23 | #include "op_arm_model.h" |
21 | #include "op_model_v7.h" | 24 | #include "op_model_v7.h" |
@@ -295,7 +298,7 @@ static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg) | |||
295 | return IRQ_HANDLED; | 298 | return IRQ_HANDLED; |
296 | } | 299 | } |
297 | 300 | ||
298 | int armv7_request_interrupts(int *irqs, int nr) | 301 | int armv7_request_interrupts(const int *irqs, int nr) |
299 | { | 302 | { |
300 | unsigned int i; | 303 | unsigned int i; |
301 | int ret = 0; | 304 | int ret = 0; |
@@ -318,7 +321,7 @@ int armv7_request_interrupts(int *irqs, int nr) | |||
318 | return ret; | 321 | return ret; |
319 | } | 322 | } |
320 | 323 | ||
321 | void armv7_release_interrupts(int *irqs, int nr) | 324 | void armv7_release_interrupts(const int *irqs, int nr) |
322 | { | 325 | { |
323 | unsigned int i; | 326 | unsigned int i; |
324 | 327 | ||
@@ -362,12 +365,7 @@ static void armv7_pmnc_dump_regs(void) | |||
362 | } | 365 | } |
363 | #endif | 366 | #endif |
364 | 367 | ||
365 | 368 | static const struct pmu_irqs *pmu_irqs; | |
366 | static int irqs[] = { | ||
367 | #ifdef CONFIG_ARCH_OMAP3 | ||
368 | INT_34XX_BENCH_MPU_EMUL, | ||
369 | #endif | ||
370 | }; | ||
371 | 369 | ||
372 | static void armv7_pmnc_stop(void) | 370 | static void armv7_pmnc_stop(void) |
373 | { | 371 | { |
@@ -375,19 +373,29 @@ static void armv7_pmnc_stop(void) | |||
375 | armv7_pmnc_dump_regs(); | 373 | armv7_pmnc_dump_regs(); |
376 | #endif | 374 | #endif |
377 | armv7_stop_pmnc(); | 375 | armv7_stop_pmnc(); |
378 | armv7_release_interrupts(irqs, ARRAY_SIZE(irqs)); | 376 | armv7_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); |
377 | release_pmu(pmu_irqs); | ||
378 | pmu_irqs = NULL; | ||
379 | } | 379 | } |
380 | 380 | ||
381 | static int armv7_pmnc_start(void) | 381 | static int armv7_pmnc_start(void) |
382 | { | 382 | { |
383 | int ret; | 383 | int ret; |
384 | 384 | ||
385 | pmu_irqs = reserve_pmu(); | ||
386 | if (IS_ERR(pmu_irqs)) | ||
387 | return PTR_ERR(pmu_irqs); | ||
388 | |||
385 | #ifdef DEBUG | 389 | #ifdef DEBUG |
386 | armv7_pmnc_dump_regs(); | 390 | armv7_pmnc_dump_regs(); |
387 | #endif | 391 | #endif |
388 | ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs)); | 392 | ret = armv7_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs); |
389 | if (ret >= 0) | 393 | if (ret >= 0) { |
390 | armv7_start_pmnc(); | 394 | armv7_start_pmnc(); |
395 | } else { | ||
396 | release_pmu(pmu_irqs); | ||
397 | pmu_irqs = NULL; | ||
398 | } | ||
391 | 399 | ||
392 | return ret; | 400 | return ret; |
393 | } | 401 | } |
diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h index 0e19bcc2e100..9ca334b39c75 100644 --- a/arch/arm/oprofile/op_model_v7.h +++ b/arch/arm/oprofile/op_model_v7.h | |||
@@ -97,7 +97,7 @@ | |||
97 | int armv7_setup_pmu(void); | 97 | int armv7_setup_pmu(void); |
98 | int armv7_start_pmu(void); | 98 | int armv7_start_pmu(void); |
99 | int armv7_stop_pmu(void); | 99 | int armv7_stop_pmu(void); |
100 | int armv7_request_interrupts(int *, int); | 100 | int armv7_request_interrupts(const int *, int); |
101 | void armv7_release_interrupts(int *, int); | 101 | void armv7_release_interrupts(const int *, int); |
102 | 102 | ||
103 | #endif | 103 | #endif |
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c index 724ab9ce2526..1d34a02048bd 100644 --- a/arch/arm/oprofile/op_model_xscale.c +++ b/arch/arm/oprofile/op_model_xscale.c | |||
@@ -17,12 +17,14 @@ | |||
17 | /* #define DEBUG */ | 17 | /* #define DEBUG */ |
18 | #include <linux/types.h> | 18 | #include <linux/types.h> |
19 | #include <linux/errno.h> | 19 | #include <linux/errno.h> |
20 | #include <linux/err.h> | ||
20 | #include <linux/sched.h> | 21 | #include <linux/sched.h> |
21 | #include <linux/oprofile.h> | 22 | #include <linux/oprofile.h> |
22 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
23 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
24 | 25 | ||
25 | #include <asm/cputype.h> | 26 | #include <asm/cputype.h> |
27 | #include <asm/pmu.h> | ||
26 | 28 | ||
27 | #include "op_counter.h" | 29 | #include "op_counter.h" |
28 | #include "op_arm_model.h" | 30 | #include "op_arm_model.h" |
@@ -33,17 +35,6 @@ | |||
33 | #define PMU_RESET (CCNT_RESET | PMN_RESET) | 35 | #define PMU_RESET (CCNT_RESET | PMN_RESET) |
34 | #define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */ | 36 | #define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */ |
35 | 37 | ||
36 | /* TODO do runtime detection */ | ||
37 | #ifdef CONFIG_ARCH_IOP32X | ||
38 | #define XSCALE_PMU_IRQ IRQ_IOP32X_CORE_PMU | ||
39 | #endif | ||
40 | #ifdef CONFIG_ARCH_IOP33X | ||
41 | #define XSCALE_PMU_IRQ IRQ_IOP33X_CORE_PMU | ||
42 | #endif | ||
43 | #ifdef CONFIG_ARCH_PXA | ||
44 | #define XSCALE_PMU_IRQ IRQ_PMU | ||
45 | #endif | ||
46 | |||
47 | /* | 38 | /* |
48 | * Different types of events that can be counted by the XScale PMU | 39 | * Different types of events that can be counted by the XScale PMU |
49 | * as used by Oprofile userspace. Here primarily for documentation | 40 | * as used by Oprofile userspace. Here primarily for documentation |
@@ -367,6 +358,8 @@ static irqreturn_t xscale_pmu_interrupt(int irq, void *arg) | |||
367 | return IRQ_HANDLED; | 358 | return IRQ_HANDLED; |
368 | } | 359 | } |
369 | 360 | ||
361 | static const struct pmu_irqs *pmu_irqs; | ||
362 | |||
370 | static void xscale_pmu_stop(void) | 363 | static void xscale_pmu_stop(void) |
371 | { | 364 | { |
372 | u32 pmnc = read_pmnc(); | 365 | u32 pmnc = read_pmnc(); |
@@ -374,20 +367,30 @@ static void xscale_pmu_stop(void) | |||
374 | pmnc &= ~PMU_ENABLE; | 367 | pmnc &= ~PMU_ENABLE; |
375 | write_pmnc(pmnc); | 368 | write_pmnc(pmnc); |
376 | 369 | ||
377 | free_irq(XSCALE_PMU_IRQ, results); | 370 | free_irq(pmu_irqs->irqs[0], results); |
371 | release_pmu(pmu_irqs); | ||
372 | pmu_irqs = NULL; | ||
378 | } | 373 | } |
379 | 374 | ||
380 | static int xscale_pmu_start(void) | 375 | static int xscale_pmu_start(void) |
381 | { | 376 | { |
382 | int ret; | 377 | int ret; |
383 | u32 pmnc = read_pmnc(); | 378 | u32 pmnc; |
379 | |||
380 | pmu_irqs = reserve_pmu(); | ||
381 | if (IS_ERR(pmu_irqs)) | ||
382 | return PTR_ERR(pmu_irqs); | ||
383 | |||
384 | pmnc = read_pmnc(); | ||
384 | 385 | ||
385 | ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, IRQF_DISABLED, | 386 | ret = request_irq(pmu_irqs->irqs[0], xscale_pmu_interrupt, |
386 | "XScale PMU", (void *)results); | 387 | IRQF_DISABLED, "XScale PMU", (void *)results); |
387 | 388 | ||
388 | if (ret < 0) { | 389 | if (ret < 0) { |
389 | printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n", | 390 | printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n", |
390 | XSCALE_PMU_IRQ); | 391 | pmu_irqs->irqs[0]); |
392 | release_pmu(pmu_irqs); | ||
393 | pmu_irqs = NULL; | ||
391 | return ret; | 394 | return ret; |
392 | } | 395 | } |
393 | 396 | ||
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c index ed0bbece0d61..e15bc17db90b 100644 --- a/arch/arm/plat-iop/io.c +++ b/arch/arm/plat-iop/io.c | |||
@@ -34,7 +34,8 @@ void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size, | |||
34 | retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie); | 34 | retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie); |
35 | break; | 35 | break; |
36 | default: | 36 | default: |
37 | retval = __arm_ioremap(cookie, size, mtype); | 37 | retval = __arm_ioremap_caller(cookie, size, mtype, |
38 | __builtin_return_address(0)); | ||
38 | } | 39 | } |
39 | 40 | ||
40 | return retval; | 41 | return retval; |
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 15b2b148a105..5a6ae1b9e1e8 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S | |||
@@ -52,7 +52,7 @@ | |||
52 | #define UART_PADDR MXC91231_UART2_BASE_ADDR | 52 | #define UART_PADDR MXC91231_UART2_BASE_ADDR |
53 | #define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) | 53 | #define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) |
54 | #endif | 54 | #endif |
55 | .macro addruart,rx | 55 | .macro addruart, rx, tmp |
56 | mrc p15, 0, \rx, c1, c0 | 56 | mrc p15, 0, \rx, c1, c0 |
57 | tst \rx, #1 @ MMU enabled? | 57 | tst \rx, #1 @ MMU enabled? |
58 | ldreq \rx, =UART_PADDR @ physical | 58 | ldreq \rx, =UART_PADDR @ physical |
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h index 62d97623412f..44243a278434 100644 --- a/arch/arm/plat-mxc/include/mach/vmalloc.h +++ b/arch/arm/plat-mxc/include/mach/vmalloc.h | |||
@@ -21,6 +21,6 @@ | |||
21 | #define __ASM_ARCH_MXC_VMALLOC_H__ | 21 | #define __ASM_ARCH_MXC_VMALLOC_H__ |
22 | 22 | ||
23 | /* vmalloc ending address */ | 23 | /* vmalloc ending address */ |
24 | #define VMALLOC_END 0xF4000000 | 24 | #define VMALLOC_END 0xf4000000UL |
25 | 25 | ||
26 | #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ | 26 | #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ |
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h new file mode 100644 index 000000000000..1621db67a53d --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/i2c.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 ST-Ericsson | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2, as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | #ifndef __PLAT_I2C_H | ||
9 | #define __PLAT_I2C_H | ||
10 | |||
11 | enum i2c_freq_mode { | ||
12 | I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */ | ||
13 | I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */ | ||
14 | I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */ | ||
15 | I2C_FREQ_MODE_HIGH_SPEED /* up to 3.4 Mb/s */ | ||
16 | }; | ||
17 | |||
18 | /** | ||
19 | * struct nmk_i2c_controller - client specific controller configuration | ||
20 | * @clk_freq: clock frequency for the operation mode | ||
21 | * @slsu: Slave data setup time in ns. | ||
22 | * The needed setup time for three modes of operation | ||
23 | * are 250ns, 100ns and 10ns respectively thus leading | ||
24 | * to the values of 14, 6, 2 for a 48 MHz i2c clk | ||
25 | * @tft: Tx FIFO Threshold in bytes | ||
26 | * @rft: Rx FIFO Threshold in bytes | ||
27 | * @sm: speed mode | ||
28 | */ | ||
29 | struct nmk_i2c_controller { | ||
30 | unsigned long clk_freq; | ||
31 | unsigned short slsu; | ||
32 | unsigned char tft; | ||
33 | unsigned char rft; | ||
34 | enum i2c_freq_mode sm; | ||
35 | }; | ||
36 | |||
37 | #endif /* __PLAT_I2C_H */ | ||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index e2ea04a4c8a1..2e3eec660864 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
@@ -22,6 +22,7 @@ config ARCH_OMAP3 | |||
22 | bool "TI OMAP3" | 22 | bool "TI OMAP3" |
23 | select CPU_V7 | 23 | select CPU_V7 |
24 | select COMMON_CLKDEV | 24 | select COMMON_CLKDEV |
25 | select ARM_L1_CACHE_SHIFT_6 | ||
25 | 26 | ||
26 | config ARCH_OMAP4 | 27 | config ARCH_OMAP4 |
27 | bool "TI OMAP4" | 28 | bool "TI OMAP4" |
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index ef870de43c29..c7d628ecb467 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h | |||
@@ -40,6 +40,7 @@ | |||
40 | #define OMAP44XX_GIC_CPU_BASE 0x48240100 | 40 | #define OMAP44XX_GIC_CPU_BASE 0x48240100 |
41 | #define OMAP44XX_SCU_BASE 0x48240000 | 41 | #define OMAP44XX_SCU_BASE 0x48240000 |
42 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 | 42 | #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 |
43 | #define OMAP44XX_L2CACHE_BASE 0x48242000 | ||
43 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 | 44 | #define OMAP44XX_WKUPGEN_BASE 0x48281000 |
44 | 45 | ||
45 | #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) | 46 | #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) |
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index 0cfd54f519c4..4cbd4fb3232c 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c | |||
@@ -128,7 +128,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) | |||
128 | return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT); | 128 | return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT); |
129 | } | 129 | } |
130 | #endif | 130 | #endif |
131 | return __arm_ioremap(p, size, type); | 131 | return __arm_ioremap_caller(p, size, type, __builtin_return_address(0)); |
132 | } | 132 | } |
133 | EXPORT_SYMBOL(omap_ioremap); | 133 | EXPORT_SYMBOL(omap_ioremap); |
134 | 134 | ||
diff --git a/arch/arm/plat-s3c/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h index bfd2ca6e3074..299d95f365c9 100644 --- a/arch/arm/plat-s3c/include/mach/vmalloc.h +++ b/arch/arm/plat-s3c/include/mach/vmalloc.h | |||
@@ -15,6 +15,6 @@ | |||
15 | #ifndef __ASM_ARCH_VMALLOC_H | 15 | #ifndef __ASM_ARCH_VMALLOC_H |
16 | #define __ASM_ARCH_VMALLOC_H | 16 | #define __ASM_ARCH_VMALLOC_H |
17 | 17 | ||
18 | #define VMALLOC_END (0xE0000000) | 18 | #define VMALLOC_END (0xe0000000UL) |
19 | 19 | ||
20 | #endif /* __ASM_ARCH_VMALLOC_H */ | 20 | #endif /* __ASM_ARCH_VMALLOC_H */ |
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S index fb3b969bf0a2..1b9348bf0e49 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S +++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S | |||
@@ -16,7 +16,7 @@ | |||
16 | * http://www.gnu.org/copyleft/gpl.html | 16 | * http://www.gnu.org/copyleft/gpl.html |
17 | */ | 17 | */ |
18 | 18 | ||
19 | .macro addruart,rx | 19 | .macro addruart, rx, tmp |
20 | mrc p15, 0, \rx, c1, c0 | 20 | mrc p15, 0, \rx, c1, c0 |
21 | tst \rx, #1 @ MMU enabled? | 21 | tst \rx, #1 @ MMU enabled? |
22 | moveq \rx, #0x80000000 @ physical base address | 22 | moveq \rx, #0x80000000 @ physical base address |
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h index 541b880c1863..943c1a29d641 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h +++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h | |||
@@ -9,4 +9,4 @@ | |||
9 | * http://www.opensource.org/licenses/gpl-license.html | 9 | * http://www.opensource.org/licenses/gpl-license.html |
10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
11 | */ | 11 | */ |
12 | #define VMALLOC_END (0xF0000000) | 12 | #define VMALLOC_END 0xf0000000UL |
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index f60a5400a25b..def19f83d812 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c | |||
@@ -430,7 +430,11 @@ static inline void vfp_pm_init(void) { } | |||
430 | * saved one. This function is used by the ptrace mechanism. | 430 | * saved one. This function is used by the ptrace mechanism. |
431 | */ | 431 | */ |
432 | #ifdef CONFIG_SMP | 432 | #ifdef CONFIG_SMP |
433 | void vfp_sync_state(struct thread_info *thread) | 433 | void vfp_sync_hwstate(struct thread_info *thread) |
434 | { | ||
435 | } | ||
436 | |||
437 | void vfp_flush_hwstate(struct thread_info *thread) | ||
434 | { | 438 | { |
435 | /* | 439 | /* |
436 | * On SMP systems, the VFP state is automatically saved at every | 440 | * On SMP systems, the VFP state is automatically saved at every |
@@ -441,35 +445,48 @@ void vfp_sync_state(struct thread_info *thread) | |||
441 | thread->vfpstate.hard.cpu = NR_CPUS; | 445 | thread->vfpstate.hard.cpu = NR_CPUS; |
442 | } | 446 | } |
443 | #else | 447 | #else |
444 | void vfp_sync_state(struct thread_info *thread) | 448 | void vfp_sync_hwstate(struct thread_info *thread) |
445 | { | 449 | { |
446 | unsigned int cpu = get_cpu(); | 450 | unsigned int cpu = get_cpu(); |
447 | u32 fpexc = fmrx(FPEXC); | ||
448 | 451 | ||
449 | /* | 452 | /* |
450 | * If VFP is enabled, the previous state was already saved and | 453 | * If the thread we're interested in is the current owner of the |
451 | * last_VFP_context updated. | 454 | * hardware VFP state, then we need to save its state. |
452 | */ | 455 | */ |
453 | if (fpexc & FPEXC_EN) | 456 | if (last_VFP_context[cpu] == &thread->vfpstate) { |
454 | goto out; | 457 | u32 fpexc = fmrx(FPEXC); |
455 | 458 | ||
456 | if (!last_VFP_context[cpu]) | 459 | /* |
457 | goto out; | 460 | * Save the last VFP state on this CPU. |
461 | */ | ||
462 | fmxr(FPEXC, fpexc | FPEXC_EN); | ||
463 | vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); | ||
464 | fmxr(FPEXC, fpexc); | ||
465 | } | ||
458 | 466 | ||
459 | /* | 467 | put_cpu(); |
460 | * Save the last VFP state on this CPU. | 468 | } |
461 | */ | 469 | |
462 | fmxr(FPEXC, fpexc | FPEXC_EN); | 470 | void vfp_flush_hwstate(struct thread_info *thread) |
463 | vfp_save_state(last_VFP_context[cpu], fpexc); | 471 | { |
464 | fmxr(FPEXC, fpexc); | 472 | unsigned int cpu = get_cpu(); |
465 | 473 | ||
466 | /* | 474 | /* |
467 | * Set the context to NULL to force a reload the next time the thread | 475 | * If the thread we're interested in is the current owner of the |
468 | * uses the VFP. | 476 | * hardware VFP state, then we need to save its state. |
469 | */ | 477 | */ |
470 | last_VFP_context[cpu] = NULL; | 478 | if (last_VFP_context[cpu] == &thread->vfpstate) { |
479 | u32 fpexc = fmrx(FPEXC); | ||
480 | |||
481 | fmxr(FPEXC, fpexc & ~FPEXC_EN); | ||
482 | |||
483 | /* | ||
484 | * Set the context to NULL to force a reload the next time | ||
485 | * the thread uses the VFP. | ||
486 | */ | ||
487 | last_VFP_context[cpu] = NULL; | ||
488 | } | ||
471 | 489 | ||
472 | out: | ||
473 | put_cpu(); | 490 | put_cpu(); |
474 | } | 491 | } |
475 | #endif | 492 | #endif |
diff --git a/arch/avr32/include/asm/pgtable.h b/arch/avr32/include/asm/pgtable.h index fecdda16f444..a9ae30c41e74 100644 --- a/arch/avr32/include/asm/pgtable.h +++ b/arch/avr32/include/asm/pgtable.h | |||
@@ -325,7 +325,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |||
325 | 325 | ||
326 | struct vm_area_struct; | 326 | struct vm_area_struct; |
327 | extern void update_mmu_cache(struct vm_area_struct * vma, | 327 | extern void update_mmu_cache(struct vm_area_struct * vma, |
328 | unsigned long address, pte_t pte); | 328 | unsigned long address, pte_t *ptep); |
329 | 329 | ||
330 | /* | 330 | /* |
331 | * Encode and decode a swap entry | 331 | * Encode and decode a swap entry |
diff --git a/arch/avr32/mm/tlb.c b/arch/avr32/mm/tlb.c index 06677be98ffb..0da23109f817 100644 --- a/arch/avr32/mm/tlb.c +++ b/arch/avr32/mm/tlb.c | |||
@@ -101,7 +101,7 @@ static void update_dtlb(unsigned long address, pte_t pte) | |||
101 | } | 101 | } |
102 | 102 | ||
103 | void update_mmu_cache(struct vm_area_struct *vma, | 103 | void update_mmu_cache(struct vm_area_struct *vma, |
104 | unsigned long address, pte_t pte) | 104 | unsigned long address, pte_t *ptep) |
105 | { | 105 | { |
106 | unsigned long flags; | 106 | unsigned long flags; |
107 | 107 | ||
@@ -110,7 +110,7 @@ void update_mmu_cache(struct vm_area_struct *vma, | |||
110 | return; | 110 | return; |
111 | 111 | ||
112 | local_irq_save(flags); | 112 | local_irq_save(flags); |
113 | update_dtlb(address, pte); | 113 | update_dtlb(address, *ptep); |
114 | local_irq_restore(flags); | 114 | local_irq_restore(flags); |
115 | } | 115 | } |
116 | 116 | ||
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h index 1fcce00f01f4..99ea6cd1b143 100644 --- a/arch/cris/include/asm/pgtable.h +++ b/arch/cris/include/asm/pgtable.h | |||
@@ -270,7 +270,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ | |||
270 | * Actually I am not sure on what this could be used for. | 270 | * Actually I am not sure on what this could be used for. |
271 | */ | 271 | */ |
272 | static inline void update_mmu_cache(struct vm_area_struct * vma, | 272 | static inline void update_mmu_cache(struct vm_area_struct * vma, |
273 | unsigned long address, pte_t pte) | 273 | unsigned long address, pte_t *ptep) |
274 | { | 274 | { |
275 | } | 275 | } |
276 | 276 | ||
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h index 22c60692b551..c18b0d32e636 100644 --- a/arch/frv/include/asm/pgtable.h +++ b/arch/frv/include/asm/pgtable.h | |||
@@ -505,7 +505,7 @@ static inline int pte_file(pte_t pte) | |||
505 | /* | 505 | /* |
506 | * preload information about a newly instantiated PTE into the SCR0/SCR1 PGE cache | 506 | * preload information about a newly instantiated PTE into the SCR0/SCR1 PGE cache |
507 | */ | 507 | */ |
508 | static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 508 | static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
509 | { | 509 | { |
510 | struct mm_struct *mm; | 510 | struct mm_struct *mm; |
511 | unsigned long ampr; | 511 | unsigned long ampr; |
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h index 69bf13857a9f..c3286f42e501 100644 --- a/arch/ia64/include/asm/pgtable.h +++ b/arch/ia64/include/asm/pgtable.h | |||
@@ -462,7 +462,7 @@ pte_same (pte_t a, pte_t b) | |||
462 | return pte_val(a) == pte_val(b); | 462 | return pte_val(a) == pte_val(b); |
463 | } | 463 | } |
464 | 464 | ||
465 | #define update_mmu_cache(vma, address, pte) do { } while (0) | 465 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
466 | 466 | ||
467 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | 467 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
468 | extern void paging_init (void); | 468 | extern void paging_init (void); |
diff --git a/arch/m32r/include/asm/tlbflush.h b/arch/m32r/include/asm/tlbflush.h index 0ef95307784e..92614b0ccf17 100644 --- a/arch/m32r/include/asm/tlbflush.h +++ b/arch/m32r/include/asm/tlbflush.h | |||
@@ -92,6 +92,6 @@ static __inline__ void __flush_tlb_all(void) | |||
92 | ); | 92 | ); |
93 | } | 93 | } |
94 | 94 | ||
95 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | 95 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); |
96 | 96 | ||
97 | #endif /* _ASM_M32R_TLBFLUSH_H */ | 97 | #endif /* _ASM_M32R_TLBFLUSH_H */ |
diff --git a/arch/m32r/mm/fault-nommu.c b/arch/m32r/mm/fault-nommu.c index 88469178ea6b..888aab1157ed 100644 --- a/arch/m32r/mm/fault-nommu.c +++ b/arch/m32r/mm/fault-nommu.c | |||
@@ -95,7 +95,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code, | |||
95 | * update_mmu_cache() | 95 | * update_mmu_cache() |
96 | *======================================================================*/ | 96 | *======================================================================*/ |
97 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, | 97 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, |
98 | pte_t pte) | 98 | pte_t *ptep) |
99 | { | 99 | { |
100 | BUG(); | 100 | BUG(); |
101 | } | 101 | } |
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c index 7274b47f4c22..28ee389e5f5a 100644 --- a/arch/m32r/mm/fault.c +++ b/arch/m32r/mm/fault.c | |||
@@ -336,7 +336,7 @@ vmalloc_fault: | |||
336 | 336 | ||
337 | addr = (address & PAGE_MASK); | 337 | addr = (address & PAGE_MASK); |
338 | set_thread_fault_code(error_code); | 338 | set_thread_fault_code(error_code); |
339 | update_mmu_cache(NULL, addr, *pte_k); | 339 | update_mmu_cache(NULL, addr, pte_k); |
340 | set_thread_fault_code(0); | 340 | set_thread_fault_code(0); |
341 | return; | 341 | return; |
342 | } | 342 | } |
@@ -349,7 +349,7 @@ vmalloc_fault: | |||
349 | #define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8)) | 349 | #define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8)) |
350 | #define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8)) | 350 | #define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8)) |
351 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, | 351 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, |
352 | pte_t pte) | 352 | pte_t *ptep) |
353 | { | 353 | { |
354 | volatile unsigned long *entry1, *entry2; | 354 | volatile unsigned long *entry1, *entry2; |
355 | unsigned long pte_data, flags; | 355 | unsigned long pte_data, flags; |
@@ -365,7 +365,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, | |||
365 | 365 | ||
366 | vaddr = (vaddr & PAGE_MASK) | get_asid(); | 366 | vaddr = (vaddr & PAGE_MASK) | get_asid(); |
367 | 367 | ||
368 | pte_data = pte_val(pte); | 368 | pte_data = pte_val(*ptep); |
369 | 369 | ||
370 | #ifdef CONFIG_CHIP_OPSP | 370 | #ifdef CONFIG_CHIP_OPSP |
371 | entry1 = (unsigned long *)ITLB_BASE; | 371 | entry1 = (unsigned long *)ITLB_BASE; |
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h index aca0e28581c7..87174c904d2b 100644 --- a/arch/m68k/include/asm/pgtable_mm.h +++ b/arch/m68k/include/asm/pgtable_mm.h | |||
@@ -115,7 +115,7 @@ extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode); | |||
115 | * they are updated on demand. | 115 | * they are updated on demand. |
116 | */ | 116 | */ |
117 | static inline void update_mmu_cache(struct vm_area_struct *vma, | 117 | static inline void update_mmu_cache(struct vm_area_struct *vma, |
118 | unsigned long address, pte_t pte) | 118 | unsigned long address, pte_t *ptep) |
119 | { | 119 | { |
120 | } | 120 | } |
121 | 121 | ||
diff --git a/arch/microblaze/include/asm/tlbflush.h b/arch/microblaze/include/asm/tlbflush.h index eb31a0e8a772..10ec70cd8735 100644 --- a/arch/microblaze/include/asm/tlbflush.h +++ b/arch/microblaze/include/asm/tlbflush.h | |||
@@ -38,7 +38,7 @@ static inline void local_flush_tlb_range(struct vm_area_struct *vma, | |||
38 | 38 | ||
39 | #define flush_tlb_kernel_range(start, end) do { } while (0) | 39 | #define flush_tlb_kernel_range(start, end) do { } while (0) |
40 | 40 | ||
41 | #define update_mmu_cache(vma, addr, pte) do { } while (0) | 41 | #define update_mmu_cache(vma, addr, ptep) do { } while (0) |
42 | 42 | ||
43 | #define flush_tlb_all local_flush_tlb_all | 43 | #define flush_tlb_all local_flush_tlb_all |
44 | #define flush_tlb_mm local_flush_tlb_mm | 44 | #define flush_tlb_mm local_flush_tlb_mm |
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 1854336e56a2..c56bf8afc099 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h | |||
@@ -362,8 +362,9 @@ extern void __update_cache(struct vm_area_struct *vma, unsigned long address, | |||
362 | pte_t pte); | 362 | pte_t pte); |
363 | 363 | ||
364 | static inline void update_mmu_cache(struct vm_area_struct *vma, | 364 | static inline void update_mmu_cache(struct vm_area_struct *vma, |
365 | unsigned long address, pte_t pte) | 365 | unsigned long address, pte_t *ptep) |
366 | { | 366 | { |
367 | pte_t pte = *ptep; | ||
367 | __update_tlb(vma, address, pte); | 368 | __update_tlb(vma, address, pte); |
368 | __update_cache(vma, address, pte); | 369 | __update_cache(vma, address, pte); |
369 | } | 370 | } |
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h index 6dc30fc827c4..16d88577f3e0 100644 --- a/arch/mn10300/include/asm/pgtable.h +++ b/arch/mn10300/include/asm/pgtable.h | |||
@@ -466,7 +466,7 @@ static inline int set_kernel_exec(unsigned long vaddr, int enable) | |||
466 | * the kernel page tables containing the necessary information by tlb-mn10300.S | 466 | * the kernel page tables containing the necessary information by tlb-mn10300.S |
467 | */ | 467 | */ |
468 | extern void update_mmu_cache(struct vm_area_struct *vma, | 468 | extern void update_mmu_cache(struct vm_area_struct *vma, |
469 | unsigned long address, pte_t pte); | 469 | unsigned long address, pte_t *ptep); |
470 | 470 | ||
471 | #endif /* !__ASSEMBLY__ */ | 471 | #endif /* !__ASSEMBLY__ */ |
472 | 472 | ||
diff --git a/arch/mn10300/mm/mmu-context.c b/arch/mn10300/mm/mmu-context.c index 31c9d27a75ae..36ba02191d40 100644 --- a/arch/mn10300/mm/mmu-context.c +++ b/arch/mn10300/mm/mmu-context.c | |||
@@ -51,9 +51,10 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) | |||
51 | /* | 51 | /* |
52 | * preemptively set a TLB entry | 52 | * preemptively set a TLB entry |
53 | */ | 53 | */ |
54 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte) | 54 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) |
55 | { | 55 | { |
56 | unsigned long pteu, ptel, cnx, flags; | 56 | unsigned long pteu, ptel, cnx, flags; |
57 | pte_t pte = *ptep; | ||
57 | 58 | ||
58 | addr &= PAGE_MASK; | 59 | addr &= PAGE_MASK; |
59 | ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2); | 60 | ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2); |
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h index a27d2e200fb2..01c15035e783 100644 --- a/arch/parisc/include/asm/pgtable.h +++ b/arch/parisc/include/asm/pgtable.h | |||
@@ -410,7 +410,7 @@ extern void paging_init (void); | |||
410 | 410 | ||
411 | #define PG_dcache_dirty PG_arch_1 | 411 | #define PG_dcache_dirty PG_arch_1 |
412 | 412 | ||
413 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | 413 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); |
414 | 414 | ||
415 | /* Encode and de-code a swap entry */ | 415 | /* Encode and de-code a swap entry */ |
416 | 416 | ||
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index b6ed34de14e1..1054baa2fc69 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c | |||
@@ -68,9 +68,9 @@ flush_cache_all_local(void) | |||
68 | EXPORT_SYMBOL(flush_cache_all_local); | 68 | EXPORT_SYMBOL(flush_cache_all_local); |
69 | 69 | ||
70 | void | 70 | void |
71 | update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 71 | update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
72 | { | 72 | { |
73 | struct page *page = pte_page(pte); | 73 | struct page *page = pte_page(*ptep); |
74 | 74 | ||
75 | if (pfn_valid(page_to_pfn(page)) && page_mapping(page) && | 75 | if (pfn_valid(page_to_pfn(page)) && page_mapping(page) && |
76 | test_bit(PG_dcache_dirty, &page->flags)) { | 76 | test_bit(PG_dcache_dirty, &page->flags)) { |
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h index 21207e54825b..89f158731ce3 100644 --- a/arch/powerpc/include/asm/pgtable.h +++ b/arch/powerpc/include/asm/pgtable.h | |||
@@ -209,7 +209,7 @@ extern void paging_init(void); | |||
209 | * corresponding HPTE into the hash table ahead of time, instead of | 209 | * corresponding HPTE into the hash table ahead of time, instead of |
210 | * waiting for the inevitable extra hash-table miss exception. | 210 | * waiting for the inevitable extra hash-table miss exception. |
211 | */ | 211 | */ |
212 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | 212 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); |
213 | 213 | ||
214 | extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr, | 214 | extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr, |
215 | unsigned long end, int write, struct page **pages, int *nr); | 215 | unsigned long end, int write, struct page **pages, int *nr); |
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index b9b152558f9c..311224cdb7ad 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c | |||
@@ -494,13 +494,13 @@ EXPORT_SYMBOL(flush_icache_user_range); | |||
494 | * This must always be called with the pte lock held. | 494 | * This must always be called with the pte lock held. |
495 | */ | 495 | */ |
496 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, | 496 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, |
497 | pte_t pte) | 497 | pte_t *ptep) |
498 | { | 498 | { |
499 | #ifdef CONFIG_PPC_STD_MMU | 499 | #ifdef CONFIG_PPC_STD_MMU |
500 | unsigned long access = 0, trap; | 500 | unsigned long access = 0, trap; |
501 | 501 | ||
502 | /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ | 502 | /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ |
503 | if (!pte_young(pte) || address >= TASK_SIZE) | 503 | if (!pte_young(*ptep) || address >= TASK_SIZE) |
504 | return; | 504 | return; |
505 | 505 | ||
506 | /* We try to figure out if we are coming from an instruction | 506 | /* We try to figure out if we are coming from an instruction |
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index e2fa79cf0614..9b5b9189c15e 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h | |||
@@ -43,7 +43,7 @@ extern void vmem_map_init(void); | |||
43 | * The S390 doesn't have any external MMU info: the kernel page | 43 | * The S390 doesn't have any external MMU info: the kernel page |
44 | * tables contain all the necessary information. | 44 | * tables contain all the necessary information. |
45 | */ | 45 | */ |
46 | #define update_mmu_cache(vma, address, pte) do { } while (0) | 46 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
47 | 47 | ||
48 | /* | 48 | /* |
49 | * ZERO_PAGE is a global shared page that is always zero: used | 49 | * ZERO_PAGE is a global shared page that is always zero: used |
diff --git a/arch/score/include/asm/pgtable.h b/arch/score/include/asm/pgtable.h index 674934b40170..ccf38f06c57d 100644 --- a/arch/score/include/asm/pgtable.h +++ b/arch/score/include/asm/pgtable.h | |||
@@ -272,8 +272,9 @@ extern void __update_cache(struct vm_area_struct *vma, | |||
272 | unsigned long address, pte_t pte); | 272 | unsigned long address, pte_t pte); |
273 | 273 | ||
274 | static inline void update_mmu_cache(struct vm_area_struct *vma, | 274 | static inline void update_mmu_cache(struct vm_area_struct *vma, |
275 | unsigned long address, pte_t pte) | 275 | unsigned long address, pte_t *ptep) |
276 | { | 276 | { |
277 | pte_t pte = *ptep; | ||
277 | __update_tlb(vma, address, pte); | 278 | __update_tlb(vma, address, pte); |
278 | __update_cache(vma, address, pte); | 279 | __update_cache(vma, address, pte); |
279 | } | 280 | } |
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h index ba3046e4f06f..1ff93ac1aa44 100644 --- a/arch/sh/include/asm/pgtable.h +++ b/arch/sh/include/asm/pgtable.h | |||
@@ -165,8 +165,9 @@ extern void __update_tlb(struct vm_area_struct *vma, | |||
165 | unsigned long address, pte_t pte); | 165 | unsigned long address, pte_t pte); |
166 | 166 | ||
167 | static inline void | 167 | static inline void |
168 | update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 168 | update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
169 | { | 169 | { |
170 | pte_t pte = *ptep; | ||
170 | __update_cache(vma, address, pte); | 171 | __update_cache(vma, address, pte); |
171 | __update_tlb(vma, address, pte); | 172 | __update_tlb(vma, address, pte); |
172 | } | 173 | } |
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 47530104e0ad..1677b5ee191d 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c | |||
@@ -371,7 +371,7 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess, | |||
371 | local_flush_tlb_one(get_asid(), address & PAGE_MASK); | 371 | local_flush_tlb_one(get_asid(), address & PAGE_MASK); |
372 | #endif | 372 | #endif |
373 | 373 | ||
374 | update_mmu_cache(NULL, address, entry); | 374 | update_mmu_cache(NULL, address, pte); |
375 | 375 | ||
376 | return 0; | 376 | return 0; |
377 | } | 377 | } |
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h index e0cabe790ec1..77f906d8cc21 100644 --- a/arch/sparc/include/asm/pgtable_32.h +++ b/arch/sparc/include/asm/pgtable_32.h | |||
@@ -330,9 +330,9 @@ BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *) | |||
330 | #define FAULT_CODE_WRITE 0x2 | 330 | #define FAULT_CODE_WRITE 0x2 |
331 | #define FAULT_CODE_USER 0x4 | 331 | #define FAULT_CODE_USER 0x4 |
332 | 332 | ||
333 | BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t) | 333 | BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t *) |
334 | 334 | ||
335 | #define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte) | 335 | #define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep) |
336 | 336 | ||
337 | BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long, | 337 | BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long, |
338 | unsigned long, unsigned int) | 338 | unsigned long, unsigned int) |
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h index f3cb790fa2ae..f5b5fa76c02d 100644 --- a/arch/sparc/include/asm/pgtable_64.h +++ b/arch/sparc/include/asm/pgtable_64.h | |||
@@ -706,7 +706,7 @@ extern unsigned long find_ecache_flush_span(unsigned long size); | |||
706 | #define mmu_unlockarea(vaddr, len) do { } while(0) | 706 | #define mmu_unlockarea(vaddr, len) do { } while(0) |
707 | 707 | ||
708 | struct vm_area_struct; | 708 | struct vm_area_struct; |
709 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | 709 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); |
710 | 710 | ||
711 | /* Encode and de-code a swap entry */ | 711 | /* Encode and de-code a swap entry */ |
712 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) | 712 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) |
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index b99f81c4906f..43e20efb2511 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c | |||
@@ -370,7 +370,7 @@ asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write, | |||
370 | unsigned long address) | 370 | unsigned long address) |
371 | { | 371 | { |
372 | extern void sun4c_update_mmu_cache(struct vm_area_struct *, | 372 | extern void sun4c_update_mmu_cache(struct vm_area_struct *, |
373 | unsigned long,pte_t); | 373 | unsigned long,pte_t *); |
374 | extern pte_t *sun4c_pte_offset_kernel(pmd_t *,unsigned long); | 374 | extern pte_t *sun4c_pte_offset_kernel(pmd_t *,unsigned long); |
375 | struct task_struct *tsk = current; | 375 | struct task_struct *tsk = current; |
376 | struct mm_struct *mm = tsk->mm; | 376 | struct mm_struct *mm = tsk->mm; |
@@ -447,7 +447,7 @@ asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write, | |||
447 | * on the CPU and doing a shrink_mmap() on this vma. | 447 | * on the CPU and doing a shrink_mmap() on this vma. |
448 | */ | 448 | */ |
449 | sun4c_update_mmu_cache (find_vma(current->mm, address), address, | 449 | sun4c_update_mmu_cache (find_vma(current->mm, address), address, |
450 | *ptep); | 450 | ptep); |
451 | else | 451 | else |
452 | do_sparc_fault(regs, text_fault, write, address); | 452 | do_sparc_fault(regs, text_fault, write, address); |
453 | } | 453 | } |
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 1886d37d411b..9245a822a2f1 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c | |||
@@ -289,12 +289,13 @@ static void flush_dcache(unsigned long pfn) | |||
289 | } | 289 | } |
290 | } | 290 | } |
291 | 291 | ||
292 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 292 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
293 | { | 293 | { |
294 | struct mm_struct *mm; | 294 | struct mm_struct *mm; |
295 | struct tsb *tsb; | 295 | struct tsb *tsb; |
296 | unsigned long tag, flags; | 296 | unsigned long tag, flags; |
297 | unsigned long tsb_index, tsb_hash_shift; | 297 | unsigned long tsb_index, tsb_hash_shift; |
298 | pte_t pte = *ptep; | ||
298 | 299 | ||
299 | if (tlb_type != hypervisor) { | 300 | if (tlb_type != hypervisor) { |
300 | unsigned long pfn = pte_pfn(pte); | 301 | unsigned long pfn = pte_pfn(pte); |
diff --git a/arch/sparc/mm/nosun4c.c b/arch/sparc/mm/nosun4c.c index 196263f895b7..4e62c27147c4 100644 --- a/arch/sparc/mm/nosun4c.c +++ b/arch/sparc/mm/nosun4c.c | |||
@@ -62,7 +62,7 @@ pte_t *sun4c_pte_offset_kernel(pmd_t *dir, unsigned long address) | |||
62 | return NULL; | 62 | return NULL; |
63 | } | 63 | } |
64 | 64 | ||
65 | void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 65 | void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
66 | { | 66 | { |
67 | } | 67 | } |
68 | 68 | ||
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index 367321a030dd..df49b200ca4c 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c | |||
@@ -694,7 +694,7 @@ extern void tsunami_setup_blockops(void); | |||
694 | * The following code is a deadwood that may be necessary when | 694 | * The following code is a deadwood that may be necessary when |
695 | * we start to make precise page flushes again. --zaitcev | 695 | * we start to make precise page flushes again. --zaitcev |
696 | */ | 696 | */ |
697 | static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte) | 697 | static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep) |
698 | { | 698 | { |
699 | #if 0 | 699 | #if 0 |
700 | static unsigned long last; | 700 | static unsigned long last; |
@@ -703,10 +703,10 @@ static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long ad | |||
703 | 703 | ||
704 | if (address == last) { | 704 | if (address == last) { |
705 | val = srmmu_hwprobe(address); | 705 | val = srmmu_hwprobe(address); |
706 | if (val != 0 && pte_val(pte) != val) { | 706 | if (val != 0 && pte_val(*ptep) != val) { |
707 | printk("swift_update_mmu_cache: " | 707 | printk("swift_update_mmu_cache: " |
708 | "addr %lx put %08x probed %08x from %p\n", | 708 | "addr %lx put %08x probed %08x from %p\n", |
709 | address, pte_val(pte), val, | 709 | address, pte_val(*ptep), val, |
710 | __builtin_return_address(0)); | 710 | __builtin_return_address(0)); |
711 | srmmu_flush_whole_tlb(); | 711 | srmmu_flush_whole_tlb(); |
712 | } | 712 | } |
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c index a89baf0d875a..18652534b91a 100644 --- a/arch/sparc/mm/sun4c.c +++ b/arch/sparc/mm/sun4c.c | |||
@@ -1887,7 +1887,7 @@ static void sun4c_check_pgt_cache(int low, int high) | |||
1887 | /* An experiment, turn off by default for now... -DaveM */ | 1887 | /* An experiment, turn off by default for now... -DaveM */ |
1888 | #define SUN4C_PRELOAD_PSEG | 1888 | #define SUN4C_PRELOAD_PSEG |
1889 | 1889 | ||
1890 | void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 1890 | void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
1891 | { | 1891 | { |
1892 | unsigned long flags; | 1892 | unsigned long flags; |
1893 | int pseg; | 1893 | int pseg; |
@@ -1929,7 +1929,7 @@ void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, p | |||
1929 | start += PAGE_SIZE; | 1929 | start += PAGE_SIZE; |
1930 | } | 1930 | } |
1931 | #ifndef SUN4C_PRELOAD_PSEG | 1931 | #ifndef SUN4C_PRELOAD_PSEG |
1932 | sun4c_put_pte(address, pte_val(pte)); | 1932 | sun4c_put_pte(address, pte_val(*ptep)); |
1933 | #endif | 1933 | #endif |
1934 | local_irq_restore(flags); | 1934 | local_irq_restore(flags); |
1935 | return; | 1935 | return; |
@@ -1940,7 +1940,7 @@ void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, p | |||
1940 | add_lru(entry); | 1940 | add_lru(entry); |
1941 | } | 1941 | } |
1942 | 1942 | ||
1943 | sun4c_put_pte(address, pte_val(pte)); | 1943 | sun4c_put_pte(address, pte_val(*ptep)); |
1944 | local_irq_restore(flags); | 1944 | local_irq_restore(flags); |
1945 | } | 1945 | } |
1946 | 1946 | ||
diff --git a/arch/um/include/asm/pgtable.h b/arch/um/include/asm/pgtable.h index 9ce3f165111a..a9f7251b4a8d 100644 --- a/arch/um/include/asm/pgtable.h +++ b/arch/um/include/asm/pgtable.h | |||
@@ -345,7 +345,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |||
345 | struct mm_struct; | 345 | struct mm_struct; |
346 | extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr); | 346 | extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr); |
347 | 347 | ||
348 | #define update_mmu_cache(vma,address,pte) do ; while (0) | 348 | #define update_mmu_cache(vma,address,ptep) do ; while (0) |
349 | 349 | ||
350 | /* Encode and de-code a swap entry */ | 350 | /* Encode and de-code a swap entry */ |
351 | #define __swp_type(x) (((x).val >> 4) & 0x3f) | 351 | #define __swp_type(x) (((x).val >> 4) & 0x3f) |
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h index 01fd9461d323..a28668396508 100644 --- a/arch/x86/include/asm/pgtable_32.h +++ b/arch/x86/include/asm/pgtable_32.h | |||
@@ -80,7 +80,7 @@ do { \ | |||
80 | * The i386 doesn't have any external MMU info: the kernel page | 80 | * The i386 doesn't have any external MMU info: the kernel page |
81 | * tables contain all the necessary information. | 81 | * tables contain all the necessary information. |
82 | */ | 82 | */ |
83 | #define update_mmu_cache(vma, address, pte) do { } while (0) | 83 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
84 | 84 | ||
85 | #endif /* !__ASSEMBLY__ */ | 85 | #endif /* !__ASSEMBLY__ */ |
86 | 86 | ||
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index c57a30117149..181be528c612 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h | |||
@@ -129,7 +129,7 @@ static inline int pgd_large(pgd_t pgd) { return 0; } | |||
129 | #define pte_unmap(pte) /* NOP */ | 129 | #define pte_unmap(pte) /* NOP */ |
130 | #define pte_unmap_nested(pte) /* NOP */ | 130 | #define pte_unmap_nested(pte) /* NOP */ |
131 | 131 | ||
132 | #define update_mmu_cache(vma, address, pte) do { } while (0) | 132 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
133 | 133 | ||
134 | /* Encode and de-code a swap entry */ | 134 | /* Encode and de-code a swap entry */ |
135 | #if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE | 135 | #if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE |
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h index a138770c358e..76bf35554117 100644 --- a/arch/xtensa/include/asm/pgtable.h +++ b/arch/xtensa/include/asm/pgtable.h | |||
@@ -394,7 +394,7 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |||
394 | #define kern_addr_valid(addr) (1) | 394 | #define kern_addr_valid(addr) (1) |
395 | 395 | ||
396 | extern void update_mmu_cache(struct vm_area_struct * vma, | 396 | extern void update_mmu_cache(struct vm_area_struct * vma, |
397 | unsigned long address, pte_t pte); | 397 | unsigned long address, pte_t *ptep); |
398 | 398 | ||
399 | /* | 399 | /* |
400 | * remap a physical page `pfn' of size `size' with page protection `prot' | 400 | * remap a physical page `pfn' of size `size' with page protection `prot' |
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index 3ba990c67676..85df4655d326 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c | |||
@@ -147,9 +147,9 @@ void flush_cache_page(struct vm_area_struct* vma, unsigned long address, | |||
147 | #endif | 147 | #endif |
148 | 148 | ||
149 | void | 149 | void |
150 | update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte) | 150 | update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep) |
151 | { | 151 | { |
152 | unsigned long pfn = pte_pfn(pte); | 152 | unsigned long pfn = pte_pfn(*ptep); |
153 | struct page *page; | 153 | struct page *page; |
154 | 154 | ||
155 | if (!pfn_valid(pfn)) | 155 | if (!pfn_valid(pfn)) |
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 90d168ad03b6..84c103a7ee13 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
@@ -2,6 +2,7 @@ | |||
2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
3 | * | 3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
5 | * Copyright (C) 2010 ST-Ericsson AB. | ||
5 | * | 6 | * |
6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
@@ -34,9 +35,6 @@ | |||
34 | 35 | ||
35 | #define DRIVER_NAME "mmci-pl18x" | 36 | #define DRIVER_NAME "mmci-pl18x" |
36 | 37 | ||
37 | #define DBG(host,fmt,args...) \ | ||
38 | pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) | ||
39 | |||
40 | static unsigned int fmax = 515633; | 38 | static unsigned int fmax = 515633; |
41 | 39 | ||
42 | /* | 40 | /* |
@@ -105,8 +103,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) | |||
105 | void __iomem *base; | 103 | void __iomem *base; |
106 | int blksz_bits; | 104 | int blksz_bits; |
107 | 105 | ||
108 | DBG(host, "blksz %04x blks %04x flags %08x\n", | 106 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
109 | data->blksz, data->blocks, data->flags); | 107 | data->blksz, data->blocks, data->flags); |
110 | 108 | ||
111 | host->data = data; | 109 | host->data = data; |
112 | host->size = data->blksz; | 110 | host->size = data->blksz; |
@@ -155,7 +153,7 @@ mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |||
155 | { | 153 | { |
156 | void __iomem *base = host->base; | 154 | void __iomem *base = host->base; |
157 | 155 | ||
158 | DBG(host, "op %02x arg %08x flags %08x\n", | 156 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
159 | cmd->opcode, cmd->arg, cmd->flags); | 157 | cmd->opcode, cmd->arg, cmd->flags); |
160 | 158 | ||
161 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | 159 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { |
@@ -184,8 +182,20 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |||
184 | { | 182 | { |
185 | if (status & MCI_DATABLOCKEND) { | 183 | if (status & MCI_DATABLOCKEND) { |
186 | host->data_xfered += data->blksz; | 184 | host->data_xfered += data->blksz; |
185 | #ifdef CONFIG_ARCH_U300 | ||
186 | /* | ||
187 | * On the U300 some signal or other is | ||
188 | * badly routed so that a data write does | ||
189 | * not properly terminate with a MCI_DATAEND | ||
190 | * status flag. This quirk will make writes | ||
191 | * work again. | ||
192 | */ | ||
193 | if (data->flags & MMC_DATA_WRITE) | ||
194 | status |= MCI_DATAEND; | ||
195 | #endif | ||
187 | } | 196 | } |
188 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | 197 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
198 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); | ||
189 | if (status & MCI_DATACRCFAIL) | 199 | if (status & MCI_DATACRCFAIL) |
190 | data->error = -EILSEQ; | 200 | data->error = -EILSEQ; |
191 | else if (status & MCI_DATATIMEOUT) | 201 | else if (status & MCI_DATATIMEOUT) |
@@ -307,7 +317,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) | |||
307 | 317 | ||
308 | status = readl(base + MMCISTATUS); | 318 | status = readl(base + MMCISTATUS); |
309 | 319 | ||
310 | DBG(host, "irq1 %08x\n", status); | 320 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
311 | 321 | ||
312 | do { | 322 | do { |
313 | unsigned long flags; | 323 | unsigned long flags; |
@@ -401,7 +411,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) | |||
401 | status &= readl(host->base + MMCIMASK0); | 411 | status &= readl(host->base + MMCIMASK0); |
402 | writel(status, host->base + MMCICLEAR); | 412 | writel(status, host->base + MMCICLEAR); |
403 | 413 | ||
404 | DBG(host, "irq0 %08x\n", status); | 414 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
405 | 415 | ||
406 | data = host->data; | 416 | data = host->data; |
407 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | 417 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| |
@@ -428,8 +438,8 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |||
428 | WARN_ON(host->mrq != NULL); | 438 | WARN_ON(host->mrq != NULL); |
429 | 439 | ||
430 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { | 440 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
431 | printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n", | 441 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
432 | mmc_hostname(mmc), mrq->data->blksz); | 442 | mrq->data->blksz); |
433 | mrq->cmd->error = -EINVAL; | 443 | mrq->cmd->error = -EINVAL; |
434 | mmc_request_done(mmc, mrq); | 444 | mmc_request_done(mmc, mrq); |
435 | return; | 445 | return; |
@@ -582,8 +592,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
582 | 592 | ||
583 | host->hw_designer = amba_manf(dev); | 593 | host->hw_designer = amba_manf(dev); |
584 | host->hw_revision = amba_rev(dev); | 594 | host->hw_revision = amba_rev(dev); |
585 | DBG(host, "designer ID = 0x%02x\n", host->hw_designer); | 595 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
586 | DBG(host, "revision = 0x%01x\n", host->hw_revision); | 596 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
587 | 597 | ||
588 | host->clk = clk_get(&dev->dev, NULL); | 598 | host->clk = clk_get(&dev->dev, NULL); |
589 | if (IS_ERR(host->clk)) { | 599 | if (IS_ERR(host->clk)) { |
@@ -608,7 +618,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
608 | if (ret < 0) | 618 | if (ret < 0) |
609 | goto clk_disable; | 619 | goto clk_disable; |
610 | host->mclk = clk_get_rate(host->clk); | 620 | host->mclk = clk_get_rate(host->clk); |
611 | DBG(host, "eventual mclk rate: %u Hz\n", host->mclk); | 621 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
622 | host->mclk); | ||
612 | } | 623 | } |
613 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); | 624 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
614 | if (!host->base) { | 625 | if (!host->base) { |
@@ -619,6 +630,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
619 | mmc->ops = &mmci_ops; | 630 | mmc->ops = &mmci_ops; |
620 | mmc->f_min = (host->mclk + 511) / 512; | 631 | mmc->f_min = (host->mclk + 511) / 512; |
621 | mmc->f_max = min(host->mclk, fmax); | 632 | mmc->f_max = min(host->mclk, fmax); |
633 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); | ||
634 | |||
622 | #ifdef CONFIG_REGULATOR | 635 | #ifdef CONFIG_REGULATOR |
623 | /* If we're using the regulator framework, try to fetch a regulator */ | 636 | /* If we're using the regulator framework, try to fetch a regulator */ |
624 | host->vcc = regulator_get(&dev->dev, "vmmc"); | 637 | host->vcc = regulator_get(&dev->dev, "vmmc"); |
@@ -712,7 +725,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
712 | 725 | ||
713 | mmc_add_host(mmc); | 726 | mmc_add_host(mmc); |
714 | 727 | ||
715 | printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", | 728 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
716 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), | 729 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
717 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); | 730 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
718 | 731 | ||
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c index 0264b117893b..c256aacfa954 100644 --- a/drivers/rtc/rtc-pl031.c +++ b/drivers/rtc/rtc-pl031.c | |||
@@ -7,6 +7,9 @@ | |||
7 | * | 7 | * |
8 | * Copyright 2006 (c) MontaVista Software, Inc. | 8 | * Copyright 2006 (c) MontaVista Software, Inc. |
9 | * | 9 | * |
10 | * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> | ||
11 | * Copyright 2010 (c) ST-Ericsson AB | ||
12 | * | ||
10 | * This program is free software; you can redistribute it and/or | 13 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License | 14 | * modify it under the terms of the GNU General Public License |
12 | * as published by the Free Software Foundation; either version | 15 | * as published by the Free Software Foundation; either version |
@@ -18,6 +21,9 @@ | |||
18 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
19 | #include <linux/amba/bus.h> | 22 | #include <linux/amba/bus.h> |
20 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/bcd.h> | ||
25 | #include <linux/delay.h> | ||
26 | #include <linux/version.h> | ||
21 | 27 | ||
22 | /* | 28 | /* |
23 | * Register definitions | 29 | * Register definitions |
@@ -30,35 +36,207 @@ | |||
30 | #define RTC_RIS 0x14 /* Raw interrupt status register */ | 36 | #define RTC_RIS 0x14 /* Raw interrupt status register */ |
31 | #define RTC_MIS 0x18 /* Masked interrupt status register */ | 37 | #define RTC_MIS 0x18 /* Masked interrupt status register */ |
32 | #define RTC_ICR 0x1c /* Interrupt clear register */ | 38 | #define RTC_ICR 0x1c /* Interrupt clear register */ |
39 | /* ST variants have additional timer functionality */ | ||
40 | #define RTC_TDR 0x20 /* Timer data read register */ | ||
41 | #define RTC_TLR 0x24 /* Timer data load register */ | ||
42 | #define RTC_TCR 0x28 /* Timer control register */ | ||
43 | #define RTC_YDR 0x30 /* Year data read register */ | ||
44 | #define RTC_YMR 0x34 /* Year match register */ | ||
45 | #define RTC_YLR 0x38 /* Year data load register */ | ||
46 | |||
47 | #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */ | ||
48 | |||
49 | #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */ | ||
50 | |||
51 | /* Common bit definitions for Interrupt status and control registers */ | ||
52 | #define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */ | ||
53 | #define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */ | ||
54 | |||
55 | /* Common bit definations for ST v2 for reading/writing time */ | ||
56 | #define RTC_SEC_SHIFT 0 | ||
57 | #define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */ | ||
58 | #define RTC_MIN_SHIFT 6 | ||
59 | #define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */ | ||
60 | #define RTC_HOUR_SHIFT 12 | ||
61 | #define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */ | ||
62 | #define RTC_WDAY_SHIFT 17 | ||
63 | #define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */ | ||
64 | #define RTC_MDAY_SHIFT 20 | ||
65 | #define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */ | ||
66 | #define RTC_MON_SHIFT 25 | ||
67 | #define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */ | ||
68 | |||
69 | #define RTC_TIMER_FREQ 32768 | ||
33 | 70 | ||
34 | struct pl031_local { | 71 | struct pl031_local { |
35 | struct rtc_device *rtc; | 72 | struct rtc_device *rtc; |
36 | void __iomem *base; | 73 | void __iomem *base; |
74 | u8 hw_designer; | ||
75 | u8 hw_revision:4; | ||
37 | }; | 76 | }; |
38 | 77 | ||
39 | static irqreturn_t pl031_interrupt(int irq, void *dev_id) | 78 | static int pl031_alarm_irq_enable(struct device *dev, |
79 | unsigned int enabled) | ||
80 | { | ||
81 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
82 | unsigned long imsc; | ||
83 | |||
84 | /* Clear any pending alarm interrupts. */ | ||
85 | writel(RTC_BIT_AI, ldata->base + RTC_ICR); | ||
86 | |||
87 | imsc = readl(ldata->base + RTC_IMSC); | ||
88 | |||
89 | if (enabled == 1) | ||
90 | writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC); | ||
91 | else | ||
92 | writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC); | ||
93 | |||
94 | return 0; | ||
95 | } | ||
96 | |||
97 | /* | ||
98 | * Convert Gregorian date to ST v2 RTC format. | ||
99 | */ | ||
100 | static int pl031_stv2_tm_to_time(struct device *dev, | ||
101 | struct rtc_time *tm, unsigned long *st_time, | ||
102 | unsigned long *bcd_year) | ||
103 | { | ||
104 | int year = tm->tm_year + 1900; | ||
105 | int wday = tm->tm_wday; | ||
106 | |||
107 | /* wday masking is not working in hardware so wday must be valid */ | ||
108 | if (wday < -1 || wday > 6) { | ||
109 | dev_err(dev, "invalid wday value %d\n", tm->tm_wday); | ||
110 | return -EINVAL; | ||
111 | } else if (wday == -1) { | ||
112 | /* wday is not provided, calculate it here */ | ||
113 | unsigned long time; | ||
114 | struct rtc_time calc_tm; | ||
115 | |||
116 | rtc_tm_to_time(tm, &time); | ||
117 | rtc_time_to_tm(time, &calc_tm); | ||
118 | wday = calc_tm.tm_wday; | ||
119 | } | ||
120 | |||
121 | *bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8); | ||
122 | |||
123 | *st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT) | ||
124 | | (tm->tm_mday << RTC_MDAY_SHIFT) | ||
125 | | ((wday + 1) << RTC_WDAY_SHIFT) | ||
126 | | (tm->tm_hour << RTC_HOUR_SHIFT) | ||
127 | | (tm->tm_min << RTC_MIN_SHIFT) | ||
128 | | (tm->tm_sec << RTC_SEC_SHIFT); | ||
129 | |||
130 | return 0; | ||
131 | } | ||
132 | |||
133 | /* | ||
134 | * Convert ST v2 RTC format to Gregorian date. | ||
135 | */ | ||
136 | static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year, | ||
137 | struct rtc_time *tm) | ||
138 | { | ||
139 | tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100); | ||
140 | tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1; | ||
141 | tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT); | ||
142 | tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1; | ||
143 | tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT); | ||
144 | tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT); | ||
145 | tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT); | ||
146 | |||
147 | tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); | ||
148 | tm->tm_year -= 1900; | ||
149 | |||
150 | return 0; | ||
151 | } | ||
152 | |||
153 | static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm) | ||
154 | { | ||
155 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
156 | |||
157 | pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR), | ||
158 | readl(ldata->base + RTC_YDR), tm); | ||
159 | |||
160 | return 0; | ||
161 | } | ||
162 | |||
163 | static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm) | ||
164 | { | ||
165 | unsigned long time; | ||
166 | unsigned long bcd_year; | ||
167 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
168 | int ret; | ||
169 | |||
170 | ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year); | ||
171 | if (ret == 0) { | ||
172 | writel(bcd_year, ldata->base + RTC_YLR); | ||
173 | writel(time, ldata->base + RTC_LR); | ||
174 | } | ||
175 | |||
176 | return ret; | ||
177 | } | ||
178 | |||
179 | static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | ||
40 | { | 180 | { |
41 | struct rtc_device *rtc = dev_id; | 181 | struct pl031_local *ldata = dev_get_drvdata(dev); |
182 | int ret; | ||
42 | 183 | ||
43 | rtc_update_irq(rtc, 1, RTC_AF); | 184 | ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR), |
185 | readl(ldata->base + RTC_YMR), &alarm->time); | ||
44 | 186 | ||
45 | return IRQ_HANDLED; | 187 | alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; |
188 | alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; | ||
189 | |||
190 | return ret; | ||
46 | } | 191 | } |
47 | 192 | ||
48 | static int pl031_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | 193 | static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
49 | { | 194 | { |
50 | struct pl031_local *ldata = dev_get_drvdata(dev); | 195 | struct pl031_local *ldata = dev_get_drvdata(dev); |
196 | unsigned long time; | ||
197 | unsigned long bcd_year; | ||
198 | int ret; | ||
199 | |||
200 | /* At the moment, we can only deal with non-wildcarded alarm times. */ | ||
201 | ret = rtc_valid_tm(&alarm->time); | ||
202 | if (ret == 0) { | ||
203 | ret = pl031_stv2_tm_to_time(dev, &alarm->time, | ||
204 | &time, &bcd_year); | ||
205 | if (ret == 0) { | ||
206 | writel(bcd_year, ldata->base + RTC_YMR); | ||
207 | writel(time, ldata->base + RTC_MR); | ||
208 | |||
209 | pl031_alarm_irq_enable(dev, alarm->enabled); | ||
210 | } | ||
211 | } | ||
212 | |||
213 | return ret; | ||
214 | } | ||
215 | |||
216 | static irqreturn_t pl031_interrupt(int irq, void *dev_id) | ||
217 | { | ||
218 | struct pl031_local *ldata = dev_id; | ||
219 | unsigned long rtcmis; | ||
220 | unsigned long events = 0; | ||
221 | |||
222 | rtcmis = readl(ldata->base + RTC_MIS); | ||
223 | if (rtcmis) { | ||
224 | writel(rtcmis, ldata->base + RTC_ICR); | ||
225 | |||
226 | if (rtcmis & RTC_BIT_AI) | ||
227 | events |= (RTC_AF | RTC_IRQF); | ||
228 | |||
229 | /* Timer interrupt is only available in ST variants */ | ||
230 | if ((rtcmis & RTC_BIT_PI) && | ||
231 | (ldata->hw_designer == AMBA_VENDOR_ST)) | ||
232 | events |= (RTC_PF | RTC_IRQF); | ||
233 | |||
234 | rtc_update_irq(ldata->rtc, 1, events); | ||
51 | 235 | ||
52 | switch (cmd) { | 236 | return IRQ_HANDLED; |
53 | case RTC_AIE_OFF: | ||
54 | writel(1, ldata->base + RTC_MIS); | ||
55 | return 0; | ||
56 | case RTC_AIE_ON: | ||
57 | writel(0, ldata->base + RTC_MIS); | ||
58 | return 0; | ||
59 | } | 237 | } |
60 | 238 | ||
61 | return -ENOIOCTLCMD; | 239 | return IRQ_NONE; |
62 | } | 240 | } |
63 | 241 | ||
64 | static int pl031_read_time(struct device *dev, struct rtc_time *tm) | 242 | static int pl031_read_time(struct device *dev, struct rtc_time *tm) |
@@ -74,11 +252,14 @@ static int pl031_set_time(struct device *dev, struct rtc_time *tm) | |||
74 | { | 252 | { |
75 | unsigned long time; | 253 | unsigned long time; |
76 | struct pl031_local *ldata = dev_get_drvdata(dev); | 254 | struct pl031_local *ldata = dev_get_drvdata(dev); |
255 | int ret; | ||
77 | 256 | ||
78 | rtc_tm_to_time(tm, &time); | 257 | ret = rtc_tm_to_time(tm, &time); |
79 | writel(time, ldata->base + RTC_LR); | ||
80 | 258 | ||
81 | return 0; | 259 | if (ret == 0) |
260 | writel(time, ldata->base + RTC_LR); | ||
261 | |||
262 | return ret; | ||
82 | } | 263 | } |
83 | 264 | ||
84 | static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | 265 | static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
@@ -86,8 +267,9 @@ static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
86 | struct pl031_local *ldata = dev_get_drvdata(dev); | 267 | struct pl031_local *ldata = dev_get_drvdata(dev); |
87 | 268 | ||
88 | rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time); | 269 | rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time); |
89 | alarm->pending = readl(ldata->base + RTC_RIS); | 270 | |
90 | alarm->enabled = readl(ldata->base + RTC_IMSC); | 271 | alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; |
272 | alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; | ||
91 | 273 | ||
92 | return 0; | 274 | return 0; |
93 | } | 275 | } |
@@ -96,22 +278,71 @@ static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
96 | { | 278 | { |
97 | struct pl031_local *ldata = dev_get_drvdata(dev); | 279 | struct pl031_local *ldata = dev_get_drvdata(dev); |
98 | unsigned long time; | 280 | unsigned long time; |
281 | int ret; | ||
282 | |||
283 | /* At the moment, we can only deal with non-wildcarded alarm times. */ | ||
284 | ret = rtc_valid_tm(&alarm->time); | ||
285 | if (ret == 0) { | ||
286 | ret = rtc_tm_to_time(&alarm->time, &time); | ||
287 | if (ret == 0) { | ||
288 | writel(time, ldata->base + RTC_MR); | ||
289 | pl031_alarm_irq_enable(dev, alarm->enabled); | ||
290 | } | ||
291 | } | ||
292 | |||
293 | return ret; | ||
294 | } | ||
295 | |||
296 | /* Periodic interrupt is only available in ST variants. */ | ||
297 | static int pl031_irq_set_state(struct device *dev, int enabled) | ||
298 | { | ||
299 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
300 | |||
301 | if (enabled == 1) { | ||
302 | /* Clear any pending timer interrupt. */ | ||
303 | writel(RTC_BIT_PI, ldata->base + RTC_ICR); | ||
304 | |||
305 | writel(readl(ldata->base + RTC_IMSC) | RTC_BIT_PI, | ||
306 | ldata->base + RTC_IMSC); | ||
99 | 307 | ||
100 | rtc_tm_to_time(&alarm->time, &time); | 308 | /* Now start the timer */ |
309 | writel(readl(ldata->base + RTC_TCR) | RTC_TCR_EN, | ||
310 | ldata->base + RTC_TCR); | ||
101 | 311 | ||
102 | writel(time, ldata->base + RTC_MR); | 312 | } else { |
103 | writel(!alarm->enabled, ldata->base + RTC_MIS); | 313 | writel(readl(ldata->base + RTC_IMSC) & (~RTC_BIT_PI), |
314 | ldata->base + RTC_IMSC); | ||
315 | |||
316 | /* Also stop the timer */ | ||
317 | writel(readl(ldata->base + RTC_TCR) & (~RTC_TCR_EN), | ||
318 | ldata->base + RTC_TCR); | ||
319 | } | ||
320 | /* Wait at least 1 RTC32 clock cycle to ensure next access | ||
321 | * to RTC_TCR will succeed. | ||
322 | */ | ||
323 | udelay(40); | ||
104 | 324 | ||
105 | return 0; | 325 | return 0; |
106 | } | 326 | } |
107 | 327 | ||
108 | static const struct rtc_class_ops pl031_ops = { | 328 | static int pl031_irq_set_freq(struct device *dev, int freq) |
109 | .ioctl = pl031_ioctl, | 329 | { |
110 | .read_time = pl031_read_time, | 330 | struct pl031_local *ldata = dev_get_drvdata(dev); |
111 | .set_time = pl031_set_time, | 331 | |
112 | .read_alarm = pl031_read_alarm, | 332 | /* Cant set timer if it is already enabled */ |
113 | .set_alarm = pl031_set_alarm, | 333 | if (readl(ldata->base + RTC_TCR) & RTC_TCR_EN) { |
114 | }; | 334 | dev_err(dev, "can't change frequency while timer enabled\n"); |
335 | return -EINVAL; | ||
336 | } | ||
337 | |||
338 | /* If self start bit in RTC_TCR is set timer will start here, | ||
339 | * but we never set that bit. Instead we start the timer when | ||
340 | * set_state is called with enabled == 1. | ||
341 | */ | ||
342 | writel(RTC_TIMER_FREQ / freq, ldata->base + RTC_TLR); | ||
343 | |||
344 | return 0; | ||
345 | } | ||
115 | 346 | ||
116 | static int pl031_remove(struct amba_device *adev) | 347 | static int pl031_remove(struct amba_device *adev) |
117 | { | 348 | { |
@@ -131,18 +362,20 @@ static int pl031_probe(struct amba_device *adev, struct amba_id *id) | |||
131 | { | 362 | { |
132 | int ret; | 363 | int ret; |
133 | struct pl031_local *ldata; | 364 | struct pl031_local *ldata; |
365 | struct rtc_class_ops *ops = id->data; | ||
134 | 366 | ||
135 | ret = amba_request_regions(adev, NULL); | 367 | ret = amba_request_regions(adev, NULL); |
136 | if (ret) | 368 | if (ret) |
137 | goto err_req; | 369 | goto err_req; |
138 | 370 | ||
139 | ldata = kmalloc(sizeof(struct pl031_local), GFP_KERNEL); | 371 | ldata = kzalloc(sizeof(struct pl031_local), GFP_KERNEL); |
140 | if (!ldata) { | 372 | if (!ldata) { |
141 | ret = -ENOMEM; | 373 | ret = -ENOMEM; |
142 | goto out; | 374 | goto out; |
143 | } | 375 | } |
144 | 376 | ||
145 | ldata->base = ioremap(adev->res.start, resource_size(&adev->res)); | 377 | ldata->base = ioremap(adev->res.start, resource_size(&adev->res)); |
378 | |||
146 | if (!ldata->base) { | 379 | if (!ldata->base) { |
147 | ret = -ENOMEM; | 380 | ret = -ENOMEM; |
148 | goto out_no_remap; | 381 | goto out_no_remap; |
@@ -150,24 +383,36 @@ static int pl031_probe(struct amba_device *adev, struct amba_id *id) | |||
150 | 383 | ||
151 | amba_set_drvdata(adev, ldata); | 384 | amba_set_drvdata(adev, ldata); |
152 | 385 | ||
153 | if (request_irq(adev->irq[0], pl031_interrupt, IRQF_DISABLED, | 386 | ldata->hw_designer = amba_manf(adev); |
154 | "rtc-pl031", ldata->rtc)) { | 387 | ldata->hw_revision = amba_rev(adev); |
155 | ret = -EIO; | 388 | |
156 | goto out_no_irq; | 389 | dev_dbg(&adev->dev, "designer ID = 0x%02x\n", ldata->hw_designer); |
157 | } | 390 | dev_dbg(&adev->dev, "revision = 0x%01x\n", ldata->hw_revision); |
158 | 391 | ||
159 | ldata->rtc = rtc_device_register("pl031", &adev->dev, &pl031_ops, | 392 | /* Enable the clockwatch on ST Variants */ |
160 | THIS_MODULE); | 393 | if ((ldata->hw_designer == AMBA_VENDOR_ST) && |
394 | (ldata->hw_revision > 1)) | ||
395 | writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN, | ||
396 | ldata->base + RTC_CR); | ||
397 | |||
398 | ldata->rtc = rtc_device_register("pl031", &adev->dev, ops, | ||
399 | THIS_MODULE); | ||
161 | if (IS_ERR(ldata->rtc)) { | 400 | if (IS_ERR(ldata->rtc)) { |
162 | ret = PTR_ERR(ldata->rtc); | 401 | ret = PTR_ERR(ldata->rtc); |
163 | goto out_no_rtc; | 402 | goto out_no_rtc; |
164 | } | 403 | } |
165 | 404 | ||
405 | if (request_irq(adev->irq[0], pl031_interrupt, | ||
406 | IRQF_DISABLED | IRQF_SHARED, "rtc-pl031", ldata)) { | ||
407 | ret = -EIO; | ||
408 | goto out_no_irq; | ||
409 | } | ||
410 | |||
166 | return 0; | 411 | return 0; |
167 | 412 | ||
168 | out_no_rtc: | ||
169 | free_irq(adev->irq[0], ldata->rtc); | ||
170 | out_no_irq: | 413 | out_no_irq: |
414 | rtc_device_unregister(ldata->rtc); | ||
415 | out_no_rtc: | ||
171 | iounmap(ldata->base); | 416 | iounmap(ldata->base); |
172 | amba_set_drvdata(adev, NULL); | 417 | amba_set_drvdata(adev, NULL); |
173 | out_no_remap: | 418 | out_no_remap: |
@@ -175,13 +420,57 @@ out_no_remap: | |||
175 | out: | 420 | out: |
176 | amba_release_regions(adev); | 421 | amba_release_regions(adev); |
177 | err_req: | 422 | err_req: |
423 | |||
178 | return ret; | 424 | return ret; |
179 | } | 425 | } |
180 | 426 | ||
427 | /* Operations for the original ARM version */ | ||
428 | static struct rtc_class_ops arm_pl031_ops = { | ||
429 | .read_time = pl031_read_time, | ||
430 | .set_time = pl031_set_time, | ||
431 | .read_alarm = pl031_read_alarm, | ||
432 | .set_alarm = pl031_set_alarm, | ||
433 | .alarm_irq_enable = pl031_alarm_irq_enable, | ||
434 | }; | ||
435 | |||
436 | /* The First ST derivative */ | ||
437 | static struct rtc_class_ops stv1_pl031_ops = { | ||
438 | .read_time = pl031_read_time, | ||
439 | .set_time = pl031_set_time, | ||
440 | .read_alarm = pl031_read_alarm, | ||
441 | .set_alarm = pl031_set_alarm, | ||
442 | .alarm_irq_enable = pl031_alarm_irq_enable, | ||
443 | .irq_set_state = pl031_irq_set_state, | ||
444 | .irq_set_freq = pl031_irq_set_freq, | ||
445 | }; | ||
446 | |||
447 | /* And the second ST derivative */ | ||
448 | static struct rtc_class_ops stv2_pl031_ops = { | ||
449 | .read_time = pl031_stv2_read_time, | ||
450 | .set_time = pl031_stv2_set_time, | ||
451 | .read_alarm = pl031_stv2_read_alarm, | ||
452 | .set_alarm = pl031_stv2_set_alarm, | ||
453 | .alarm_irq_enable = pl031_alarm_irq_enable, | ||
454 | .irq_set_state = pl031_irq_set_state, | ||
455 | .irq_set_freq = pl031_irq_set_freq, | ||
456 | }; | ||
457 | |||
181 | static struct amba_id pl031_ids[] __initdata = { | 458 | static struct amba_id pl031_ids[] __initdata = { |
182 | { | 459 | { |
183 | .id = 0x00041031, | 460 | .id = 0x00041031, |
184 | .mask = 0x000fffff, | 461 | .mask = 0x000fffff, |
462 | .data = &arm_pl031_ops, | ||
463 | }, | ||
464 | /* ST Micro variants */ | ||
465 | { | ||
466 | .id = 0x00180031, | ||
467 | .mask = 0x00ffffff, | ||
468 | .data = &stv1_pl031_ops, | ||
469 | }, | ||
470 | { | ||
471 | .id = 0x00280031, | ||
472 | .mask = 0x00ffffff, | ||
473 | .data = &stv2_pl031_ops, | ||
185 | }, | 474 | }, |
186 | {0, 0}, | 475 | {0, 0}, |
187 | }; | 476 | }; |
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c index ef7adc8135dd..ce6c35333ff7 100644 --- a/drivers/serial/amba-pl011.c +++ b/drivers/serial/amba-pl011.c | |||
@@ -71,6 +71,7 @@ struct uart_amba_port { | |||
71 | unsigned int im; /* interrupt mask */ | 71 | unsigned int im; /* interrupt mask */ |
72 | unsigned int old_status; | 72 | unsigned int old_status; |
73 | unsigned int ifls; /* vendor-specific */ | 73 | unsigned int ifls; /* vendor-specific */ |
74 | bool autorts; | ||
74 | }; | 75 | }; |
75 | 76 | ||
76 | /* There is by now at least one vendor with differing details, so handle it */ | 77 | /* There is by now at least one vendor with differing details, so handle it */ |
@@ -308,6 +309,11 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
308 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | 309 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); |
309 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | 310 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); |
310 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | 311 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); |
312 | |||
313 | if (uap->autorts) { | ||
314 | /* We need to disable auto-RTS if we want to turn RTS off */ | ||
315 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | ||
316 | } | ||
311 | #undef TIOCMBIT | 317 | #undef TIOCMBIT |
312 | 318 | ||
313 | writew(cr, uap->port.membase + UART011_CR); | 319 | writew(cr, uap->port.membase + UART011_CR); |
@@ -437,6 +443,7 @@ static void pl011_shutdown(struct uart_port *port) | |||
437 | /* | 443 | /* |
438 | * disable the port | 444 | * disable the port |
439 | */ | 445 | */ |
446 | uap->autorts = false; | ||
440 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); | 447 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
441 | 448 | ||
442 | /* | 449 | /* |
@@ -456,6 +463,7 @@ static void | |||
456 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, | 463 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
457 | struct ktermios *old) | 464 | struct ktermios *old) |
458 | { | 465 | { |
466 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
459 | unsigned int lcr_h, old_cr; | 467 | unsigned int lcr_h, old_cr; |
460 | unsigned long flags; | 468 | unsigned long flags; |
461 | unsigned int baud, quot; | 469 | unsigned int baud, quot; |
@@ -532,6 +540,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, | |||
532 | old_cr = readw(port->membase + UART011_CR); | 540 | old_cr = readw(port->membase + UART011_CR); |
533 | writew(0, port->membase + UART011_CR); | 541 | writew(0, port->membase + UART011_CR); |
534 | 542 | ||
543 | if (termios->c_cflag & CRTSCTS) { | ||
544 | if (old_cr & UART011_CR_RTS) | ||
545 | old_cr |= UART011_CR_RTSEN; | ||
546 | |||
547 | old_cr |= UART011_CR_CTSEN; | ||
548 | uap->autorts = true; | ||
549 | } else { | ||
550 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | ||
551 | uap->autorts = false; | ||
552 | } | ||
553 | |||
535 | /* Set baud rate */ | 554 | /* Set baud rate */ |
536 | writew(quot & 0x3f, port->membase + UART011_FBRD); | 555 | writew(quot & 0x3f, port->membase + UART011_FBRD); |
537 | writew(quot >> 6, port->membase + UART011_IBRD); | 556 | writew(quot >> 6, port->membase + UART011_IBRD); |
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c index ff5bbb9c43c9..9aeb68113100 100644 --- a/drivers/spi/amba-pl022.c +++ b/drivers/spi/amba-pl022.c | |||
@@ -363,6 +363,7 @@ struct pl022 { | |||
363 | void *rx_end; | 363 | void *rx_end; |
364 | enum ssp_reading read; | 364 | enum ssp_reading read; |
365 | enum ssp_writing write; | 365 | enum ssp_writing write; |
366 | u32 exp_fifo_level; | ||
366 | }; | 367 | }; |
367 | 368 | ||
368 | /** | 369 | /** |
@@ -501,6 +502,9 @@ static int flush(struct pl022 *pl022) | |||
501 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | 502 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
502 | readw(SSP_DR(pl022->virtbase)); | 503 | readw(SSP_DR(pl022->virtbase)); |
503 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | 504 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); |
505 | |||
506 | pl022->exp_fifo_level = 0; | ||
507 | |||
504 | return limit; | 508 | return limit; |
505 | } | 509 | } |
506 | 510 | ||
@@ -583,10 +587,9 @@ static void readwriter(struct pl022 *pl022) | |||
583 | * errons in 8bit wide transfers on ARM variants (just 8 words | 587 | * errons in 8bit wide transfers on ARM variants (just 8 words |
584 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | 588 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
585 | * | 589 | * |
586 | * FIXME: currently we have no logic to account for this. | 590 | * To prevent this issue, the TX FIFO is only filled to the |
587 | * perhaps there is even something broken in HW regarding | 591 | * unused RX FIFO fill length, regardless of what the TX |
588 | * 8bit transfers (it doesn't fail on 16bit) so this needs | 592 | * FIFO status flag indicates. |
589 | * more investigation... | ||
590 | */ | 593 | */ |
591 | dev_dbg(&pl022->adev->dev, | 594 | dev_dbg(&pl022->adev->dev, |
592 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | 595 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
@@ -613,11 +616,12 @@ static void readwriter(struct pl022 *pl022) | |||
613 | break; | 616 | break; |
614 | } | 617 | } |
615 | pl022->rx += (pl022->cur_chip->n_bytes); | 618 | pl022->rx += (pl022->cur_chip->n_bytes); |
619 | pl022->exp_fifo_level--; | ||
616 | } | 620 | } |
617 | /* | 621 | /* |
618 | * Write as much as you can, while keeping an eye on the RX FIFO! | 622 | * Write as much as possible up to the RX FIFO size |
619 | */ | 623 | */ |
620 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) | 624 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
621 | && (pl022->tx < pl022->tx_end)) { | 625 | && (pl022->tx < pl022->tx_end)) { |
622 | switch (pl022->write) { | 626 | switch (pl022->write) { |
623 | case WRITING_NULL: | 627 | case WRITING_NULL: |
@@ -634,6 +638,7 @@ static void readwriter(struct pl022 *pl022) | |||
634 | break; | 638 | break; |
635 | } | 639 | } |
636 | pl022->tx += (pl022->cur_chip->n_bytes); | 640 | pl022->tx += (pl022->cur_chip->n_bytes); |
641 | pl022->exp_fifo_level++; | ||
637 | /* | 642 | /* |
638 | * This inner reader takes care of things appearing in the RX | 643 | * This inner reader takes care of things appearing in the RX |
639 | * FIFO as we're transmitting. This will happen a lot since the | 644 | * FIFO as we're transmitting. This will happen a lot since the |
@@ -660,6 +665,7 @@ static void readwriter(struct pl022 *pl022) | |||
660 | break; | 665 | break; |
661 | } | 666 | } |
662 | pl022->rx += (pl022->cur_chip->n_bytes); | 667 | pl022->rx += (pl022->cur_chip->n_bytes); |
668 | pl022->exp_fifo_level--; | ||
663 | } | 669 | } |
664 | } | 670 | } |
665 | /* | 671 | /* |
diff --git a/mm/hugetlb.c b/mm/hugetlb.c index e91b81b63670..94cd94df56e3 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c | |||
@@ -2088,7 +2088,7 @@ static void set_huge_ptep_writable(struct vm_area_struct *vma, | |||
2088 | 2088 | ||
2089 | entry = pte_mkwrite(pte_mkdirty(huge_ptep_get(ptep))); | 2089 | entry = pte_mkwrite(pte_mkdirty(huge_ptep_get(ptep))); |
2090 | if (huge_ptep_set_access_flags(vma, address, ptep, entry, 1)) { | 2090 | if (huge_ptep_set_access_flags(vma, address, ptep, entry, 1)) { |
2091 | update_mmu_cache(vma, address, entry); | 2091 | update_mmu_cache(vma, address, ptep); |
2092 | } | 2092 | } |
2093 | } | 2093 | } |
2094 | 2094 | ||
@@ -2559,7 +2559,7 @@ int hugetlb_fault(struct mm_struct *mm, struct vm_area_struct *vma, | |||
2559 | entry = pte_mkyoung(entry); | 2559 | entry = pte_mkyoung(entry); |
2560 | if (huge_ptep_set_access_flags(vma, address, ptep, entry, | 2560 | if (huge_ptep_set_access_flags(vma, address, ptep, entry, |
2561 | flags & FAULT_FLAG_WRITE)) | 2561 | flags & FAULT_FLAG_WRITE)) |
2562 | update_mmu_cache(vma, address, entry); | 2562 | update_mmu_cache(vma, address, ptep); |
2563 | 2563 | ||
2564 | out_page_table_lock: | 2564 | out_page_table_lock: |
2565 | spin_unlock(&mm->page_table_lock); | 2565 | spin_unlock(&mm->page_table_lock); |
diff --git a/mm/memory.c b/mm/memory.c index 09e4b1be7b67..72fb5f39bccc 100644 --- a/mm/memory.c +++ b/mm/memory.c | |||
@@ -1593,7 +1593,7 @@ static int insert_pfn(struct vm_area_struct *vma, unsigned long addr, | |||
1593 | /* Ok, finally just insert the thing.. */ | 1593 | /* Ok, finally just insert the thing.. */ |
1594 | entry = pte_mkspecial(pfn_pte(pfn, prot)); | 1594 | entry = pte_mkspecial(pfn_pte(pfn, prot)); |
1595 | set_pte_at(mm, addr, pte, entry); | 1595 | set_pte_at(mm, addr, pte, entry); |
1596 | update_mmu_cache(vma, addr, entry); /* XXX: why not for insert_page? */ | 1596 | update_mmu_cache(vma, addr, pte); /* XXX: why not for insert_page? */ |
1597 | 1597 | ||
1598 | retval = 0; | 1598 | retval = 0; |
1599 | out_unlock: | 1599 | out_unlock: |
@@ -2116,7 +2116,7 @@ reuse: | |||
2116 | entry = pte_mkyoung(orig_pte); | 2116 | entry = pte_mkyoung(orig_pte); |
2117 | entry = maybe_mkwrite(pte_mkdirty(entry), vma); | 2117 | entry = maybe_mkwrite(pte_mkdirty(entry), vma); |
2118 | if (ptep_set_access_flags(vma, address, page_table, entry,1)) | 2118 | if (ptep_set_access_flags(vma, address, page_table, entry,1)) |
2119 | update_mmu_cache(vma, address, entry); | 2119 | update_mmu_cache(vma, address, page_table); |
2120 | ret |= VM_FAULT_WRITE; | 2120 | ret |= VM_FAULT_WRITE; |
2121 | goto unlock; | 2121 | goto unlock; |
2122 | } | 2122 | } |
@@ -2185,7 +2185,7 @@ gotten: | |||
2185 | * new page to be mapped directly into the secondary page table. | 2185 | * new page to be mapped directly into the secondary page table. |
2186 | */ | 2186 | */ |
2187 | set_pte_at_notify(mm, address, page_table, entry); | 2187 | set_pte_at_notify(mm, address, page_table, entry); |
2188 | update_mmu_cache(vma, address, entry); | 2188 | update_mmu_cache(vma, address, page_table); |
2189 | if (old_page) { | 2189 | if (old_page) { |
2190 | /* | 2190 | /* |
2191 | * Only after switching the pte to the new page may | 2191 | * Only after switching the pte to the new page may |
@@ -2629,7 +2629,7 @@ static int do_swap_page(struct mm_struct *mm, struct vm_area_struct *vma, | |||
2629 | } | 2629 | } |
2630 | 2630 | ||
2631 | /* No need to invalidate - it was non-present before */ | 2631 | /* No need to invalidate - it was non-present before */ |
2632 | update_mmu_cache(vma, address, pte); | 2632 | update_mmu_cache(vma, address, page_table); |
2633 | unlock: | 2633 | unlock: |
2634 | pte_unmap_unlock(page_table, ptl); | 2634 | pte_unmap_unlock(page_table, ptl); |
2635 | out: | 2635 | out: |
@@ -2694,7 +2694,7 @@ setpte: | |||
2694 | set_pte_at(mm, address, page_table, entry); | 2694 | set_pte_at(mm, address, page_table, entry); |
2695 | 2695 | ||
2696 | /* No need to invalidate - it was non-present before */ | 2696 | /* No need to invalidate - it was non-present before */ |
2697 | update_mmu_cache(vma, address, entry); | 2697 | update_mmu_cache(vma, address, page_table); |
2698 | unlock: | 2698 | unlock: |
2699 | pte_unmap_unlock(page_table, ptl); | 2699 | pte_unmap_unlock(page_table, ptl); |
2700 | return 0; | 2700 | return 0; |
@@ -2855,7 +2855,7 @@ static int __do_fault(struct mm_struct *mm, struct vm_area_struct *vma, | |||
2855 | set_pte_at(mm, address, page_table, entry); | 2855 | set_pte_at(mm, address, page_table, entry); |
2856 | 2856 | ||
2857 | /* no need to invalidate: a not-present page won't be cached */ | 2857 | /* no need to invalidate: a not-present page won't be cached */ |
2858 | update_mmu_cache(vma, address, entry); | 2858 | update_mmu_cache(vma, address, page_table); |
2859 | } else { | 2859 | } else { |
2860 | if (charged) | 2860 | if (charged) |
2861 | mem_cgroup_uncharge_page(page); | 2861 | mem_cgroup_uncharge_page(page); |
@@ -2992,7 +2992,7 @@ static inline int handle_pte_fault(struct mm_struct *mm, | |||
2992 | } | 2992 | } |
2993 | entry = pte_mkyoung(entry); | 2993 | entry = pte_mkyoung(entry); |
2994 | if (ptep_set_access_flags(vma, address, pte, entry, flags & FAULT_FLAG_WRITE)) { | 2994 | if (ptep_set_access_flags(vma, address, pte, entry, flags & FAULT_FLAG_WRITE)) { |
2995 | update_mmu_cache(vma, address, entry); | 2995 | update_mmu_cache(vma, address, pte); |
2996 | } else { | 2996 | } else { |
2997 | /* | 2997 | /* |
2998 | * This is needed only for protection faults but the arch code | 2998 | * This is needed only for protection faults but the arch code |
diff --git a/mm/migrate.c b/mm/migrate.c index efddbf0926b2..e58e5da25b91 100644 --- a/mm/migrate.c +++ b/mm/migrate.c | |||
@@ -134,7 +134,7 @@ static int remove_migration_pte(struct page *new, struct vm_area_struct *vma, | |||
134 | page_add_file_rmap(new); | 134 | page_add_file_rmap(new); |
135 | 135 | ||
136 | /* No need to invalidate - it was non-present before */ | 136 | /* No need to invalidate - it was non-present before */ |
137 | update_mmu_cache(vma, addr, pte); | 137 | update_mmu_cache(vma, addr, ptep); |
138 | unlock: | 138 | unlock: |
139 | pte_unmap_unlock(ptep, ptl); | 139 | pte_unmap_unlock(ptep, ptl); |
140 | out: | 140 | out: |