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-rw-r--r--Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt15
1 files changed, 12 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
index 4c8ade8b340b..ba797d3e6326 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -3,7 +3,7 @@ Tegra SOC USB PHY
3The device node for Tegra SOC USB PHY: 3The device node for Tegra SOC USB PHY:
4 4
5Required properties : 5Required properties :
6 - compatible : Should be "nvidia,tegra20-usb-phy". 6 - compatible : Should be "nvidia,tegra<chip>-usb-phy".
7 - reg : Defines the following set of registers, in the order listed: 7 - reg : Defines the following set of registers, in the order listed:
8 - The PHY's own register set. 8 - The PHY's own register set.
9 Always present. 9 Always present.
@@ -24,17 +24,26 @@ Required properties :
24Required properties for phy_type == ulpi: 24Required properties for phy_type == ulpi:
25 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 25 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
26 26
27Required PHY timing params for utmi phy: 27Required PHY timing params for utmi phy, for all chips:
28 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before 28 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
29 start of sync launches RxActive 29 start of sync launches RxActive
30 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store 30 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
31 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait 31 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
32 before declare IDLE. 32 before declare IDLE.
33 - nvidia,term-range-adj : Range adjusment on terminations 33 - nvidia,term-range-adj : Range adjusment on terminations
34 - nvidia,xcvr-setup : HS driver output control 34 - Either one of the following for HS driver output control:
35 - nvidia,xcvr-setup : integer, uses the provided value.
36 - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
37 from the on-chip fuses
38 If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
35 - nvidia,xcvr-lsfslew : LS falling slew rate control. 39 - nvidia,xcvr-lsfslew : LS falling slew rate control.
36 - nvidia,xcvr-lsrslew : LS rising slew rate control. 40 - nvidia,xcvr-lsrslew : LS rising slew rate control.
37 41
42Required PHY timing params for utmi phy, only on Tegra30 and above:
43 - nvidia,xcvr-hsslew : HS slew rate control.
44 - nvidia,hssquelch-level : HS squelch detector level.
45 - nvidia,hsdiscon-level : HS disconnect detector level.
46
38Optional properties: 47Optional properties:
39 - nvidia,has-legacy-mode : boolean indicates whether this controller can 48 - nvidia,has-legacy-mode : boolean indicates whether this controller can
40 operate in legacy mode (as APX 2500 / 2600). In legacy mode some 49 operate in legacy mode (as APX 2500 / 2600). In legacy mode some