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-rw-r--r--Documentation/devicetree/bindings/arm/primecell.txt6
-rw-r--r--Documentation/devicetree/bindings/clock/calxeda.txt17
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt117
-rw-r--r--Documentation/devicetree/bindings/clock/fixed-clock.txt21
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/boot/dts/highbank.dts91
-rw-r--r--arch/arm/mach-highbank/Makefile2
-rw-r--r--arch/arm/mach-highbank/clock.c62
-rw-r--r--arch/arm/mach-highbank/highbank.c7
-rw-r--r--arch/arm/mach-integrator/core.c55
-rw-r--r--arch/arm/mach-integrator/include/mach/clkdev.h26
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c8
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c69
-rw-r--r--arch/arm/mach-u300/Makefile2
-rw-r--r--arch/arm/mach-u300/clock.c1504
-rw-r--r--arch/arm/mach-u300/clock.h50
-rw-r--r--arch/arm/mach-u300/core.c21
-rw-r--r--arch/arm/mach-u300/timer.c2
-rw-r--r--drivers/clk/Kconfig7
-rw-r--r--drivers/clk/Makefile8
-rw-r--r--drivers/clk/clk-divider.c189
-rw-r--r--drivers/clk/clk-fixed-factor.c2
-rw-r--r--drivers/clk/clk-fixed-rate.c25
-rw-r--r--drivers/clk/clk-gate.c2
-rw-r--r--drivers/clk/clk-highbank.c346
-rw-r--r--drivers/clk/clk-mux.c2
-rw-r--r--drivers/clk/clk-u300.c746
-rw-r--r--drivers/clk/clk-wm831x.c428
-rw-r--r--drivers/clk/clk.c144
-rw-r--r--drivers/clk/clkdev.c77
-rw-r--r--drivers/clk/mxs/clk-imx23.c3
-rw-r--r--drivers/clk/mxs/clk-imx28.c13
-rw-r--r--drivers/clk/versatile/Makefile3
-rw-r--r--drivers/clk/versatile/clk-icst.c100
-rw-r--r--drivers/clk/versatile/clk-icst.h10
-rw-r--r--drivers/clk/versatile/clk-integrator.c111
-rw-r--r--include/linux/clk-private.h22
-rw-r--r--include/linux/clk-provider.h31
-rw-r--r--include/linux/clk.h20
-rw-r--r--include/linux/platform_data/clk-integrator.h1
-rw-r--r--include/linux/platform_data/clk-u300.h1
42 files changed, 2536 insertions, 1824 deletions
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
index 951ca46789d4..64fc82bc8928 100644
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ b/Documentation/devicetree/bindings/arm/primecell.txt
@@ -13,11 +13,17 @@ Required properties:
13Optional properties: 13Optional properties:
14 14
15- arm,primecell-periphid : Value to override the h/w value with 15- arm,primecell-periphid : Value to override the h/w value with
16- clocks : From common clock binding. First clock is phandle to clock for apb
17 pclk. Additional clocks are optional and specific to those peripherals.
18- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
16 19
17Example: 20Example:
18 21
19serial@fff36000 { 22serial@fff36000 {
20 compatible = "arm,pl011", "arm,primecell"; 23 compatible = "arm,pl011", "arm,primecell";
21 arm,primecell-periphid = <0x00341011>; 24 arm,primecell-periphid = <0x00341011>;
25 clocks = <&pclk>;
26 clock-names = "apb_pclk";
27
22}; 28};
23 29
diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
new file mode 100644
index 000000000000..0a6ac1bdcda1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/calxeda.txt
@@ -0,0 +1,17 @@
1Device Tree Clock bindings for Calxeda highbank platform
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "calxeda,hb-pll-clock" - for a PLL clock
10 "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
11 A9 clock.
12 "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
13 "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
14- reg : shall be the control register offset from SYSREGs base for the clock.
15- clocks : shall be the input parent clock phandle for the clock. This is
16 either an oscillator or a pll output.
17- #clock-cells : from common clock binding; shall be set to 0.
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
new file mode 100644
index 000000000000..eb65d417f8c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -0,0 +1,117 @@
1This binding is a work-in-progress, and are based on some experimental
2work by benh[1].
3
4Sources of clock signal can be represented by any node in the device
5tree. Those nodes are designated as clock providers. Clock consumer
6nodes use a phandle and clock specifier pair to connect clock provider
7outputs to clock inputs. Similar to the gpio specifiers, a clock
8specifier is an array of one more more cells identifying the clock
9output on a device. The length of a clock specifier is defined by the
10value of a #clock-cells property in the clock provider node.
11
12[1] http://patchwork.ozlabs.org/patch/31551/
13
14==Clock providers==
15
16Required properties:
17#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
18 with a single clock output and 1 for nodes with multiple
19 clock outputs.
20
21Optional properties:
22clock-output-names: Recommended to be a list of strings of clock output signal
23 names indexed by the first cell in the clock specifier.
24 However, the meaning of clock-output-names is domain
25 specific to the clock provider, and is only provided to
26 encourage using the same meaning for the majority of clock
27 providers. This format may not work for clock providers
28 using a complex clock specifier format. In those cases it
29 is recommended to omit this property and create a binding
30 specific names property.
31
32 Clock consumer nodes must never directly reference
33 the provider's clock-output-names property.
34
35For example:
36
37 oscillator {
38 #clock-cells = <1>;
39 clock-output-names = "ckil", "ckih";
40 };
41
42- this node defines a device with two clock outputs, the first named
43 "ckil" and the second named "ckih". Consumer nodes always reference
44 clocks by index. The names should reflect the clock output signal
45 names for the device.
46
47==Clock consumers==
48
49Required properties:
50clocks: List of phandle and clock specifier pairs, one pair
51 for each clock input to the device. Note: if the
52 clock provider specifies '0' for #clock-cells, then
53 only the phandle portion of the pair will appear.
54
55Optional properties:
56clock-names: List of clock input name strings sorted in the same
57 order as the clocks property. Consumers drivers
58 will use clock-names to match clock input names
59 with clocks specifiers.
60clock-ranges: Empty property indicating that child nodes can inherit named
61 clocks from this node. Useful for bus nodes to provide a
62 clock to their children.
63
64For example:
65
66 device {
67 clocks = <&osc 1>, <&ref 0>;
68 clock-names = "baud", "register";
69 };
70
71
72This represents a device with two clock inputs, named "baud" and "register".
73The baud clock is connected to output 1 of the &osc device, and the register
74clock is connected to output 0 of the &ref.
75
76==Example==
77
78 /* external oscillator */
79 osc: oscillator {
80 compatible = "fixed-clock";
81 #clock-cells = <1>;
82 clock-frequency = <32678>;
83 clock-output-names = "osc";
84 };
85
86 /* phase-locked-loop device, generates a higher frequency clock
87 * from the external oscillator reference */
88 pll: pll@4c000 {
89 compatible = "vendor,some-pll-interface"
90 #clock-cells = <1>;
91 clocks = <&osc 0>;
92 clock-names = "ref";
93 reg = <0x4c000 0x1000>;
94 clock-output-names = "pll", "pll-switched";
95 };
96
97 /* UART, using the low frequency oscillator for the baud clock,
98 * and the high frequency switched PLL output for register
99 * clocking */
100 uart@a000 {
101 compatible = "fsl,imx-uart";
102 reg = <0xa000 0x1000>;
103 interrupts = <33>;
104 clocks = <&osc 0>, <&pll 1>;
105 clock-names = "baud", "register";
106 };
107
108This DT fragment defines three devices: an external oscillator to provide a
109low-frequency reference clock, a PLL device to generate a higher frequency
110clock signal, and a UART.
111
112* The oscillator is fixed-frequency, and provides one clock output, named "osc".
113* The PLL is both a clock provider and a clock consumer. It uses the clock
114 signal generated by the external oscillator, and provides two output signals
115 ("pll" and "pll-switched").
116* The UART has its baud clock connected the external oscillator and its
117 register clock connected to the PLL clock (the "pll-switched" signal)
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
new file mode 100644
index 000000000000..0b1fe7824093
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-clock.txt
@@ -0,0 +1,21 @@
1Binding for simple fixed-rate clock sources.
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be "fixed-clock".
9- #clock-cells : from common clock binding; shall be set to 0.
10- clock-frequency : frequency of clock in Hz. Should be a single cell.
11
12Optional properties:
13- gpios : From common gpio binding; gpio connection to clock enable pin.
14- clock-output-names : From common clock binding.
15
16Example:
17 clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <1000000000>;
21 };
diff --git a/MAINTAINERS b/MAINTAINERS
index cd8a3f61a79c..9b8a5daaf403 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7605,6 +7605,7 @@ W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
7605S: Supported 7605S: Supported
7606F: Documentation/hwmon/wm83?? 7606F: Documentation/hwmon/wm83??
7607F: arch/arm/mach-s3c64xx/mach-crag6410* 7607F: arch/arm/mach-s3c64xx/mach-crag6410*
7608F: drivers/clk/clk-wm83*.c
7608F: drivers/leds/leds-wm83*.c 7609F: drivers/leds/leds-wm83*.c
7609F: drivers/hwmon/wm83??-hwmon.c 7610F: drivers/hwmon/wm83??-hwmon.c
7610F: drivers/input/misc/wm831x-on.c 7611F: drivers/input/misc/wm831x-on.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c7e6d208fa8d..b25c9d3c379a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -273,8 +273,8 @@ config ARCH_INTEGRATOR
273 bool "ARM Ltd. Integrator family" 273 bool "ARM Ltd. Integrator family"
274 select ARM_AMBA 274 select ARM_AMBA
275 select ARCH_HAS_CPUFREQ 275 select ARCH_HAS_CPUFREQ
276 select CLKDEV_LOOKUP 276 select COMMON_CLK
277 select HAVE_MACH_CLKDEV 277 select CLK_VERSATILE
278 select HAVE_TCM 278 select HAVE_TCM
279 select ICST 279 select ICST
280 select GENERIC_CLOCKEVENTS 280 select GENERIC_CLOCKEVENTS
@@ -336,6 +336,7 @@ config ARCH_VEXPRESS
336 select ICST 336 select ICST
337 select NO_IOPORT 337 select NO_IOPORT
338 select PLAT_VERSATILE 338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLOCK
339 select PLAT_VERSATILE_CLCD 340 select PLAT_VERSATILE_CLCD
340 select REGULATOR_FIXED_VOLTAGE if REGULATOR 341 select REGULATOR_FIXED_VOLTAGE if REGULATOR
341 help 342 help
@@ -372,6 +373,7 @@ config ARCH_HIGHBANK
372 select ARM_TIMER_SP804 373 select ARM_TIMER_SP804
373 select CACHE_L2X0 374 select CACHE_L2X0
374 select CLKDEV_LOOKUP 375 select CLKDEV_LOOKUP
376 select COMMON_CLK
375 select CPU_V7 377 select CPU_V7
376 select GENERIC_CLOCKEVENTS 378 select GENERIC_CLOCKEVENTS
377 select HAVE_ARM_SCU 379 select HAVE_ARM_SCU
@@ -929,7 +931,7 @@ config ARCH_U300
929 select ARM_VIC 931 select ARM_VIC
930 select GENERIC_CLOCKEVENTS 932 select GENERIC_CLOCKEVENTS
931 select CLKDEV_LOOKUP 933 select CLKDEV_LOOKUP
932 select HAVE_MACH_CLKDEV 934 select COMMON_CLK
933 select GENERIC_GPIO 935 select GENERIC_GPIO
934 select ARCH_REQUIRE_GPIOLIB 936 select ARCH_REQUIRE_GPIOLIB
935 help 937 help
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 83e72294aefb..2e1cfa00c25b 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Calxeda, Inc. 2 * Copyright 2011-2012 Calxeda, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,7 @@
24 compatible = "calxeda,highbank"; 24 compatible = "calxeda,highbank";
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <1>; 26 #size-cells = <1>;
27 clock-ranges;
27 28
28 cpus { 29 cpus {
29 #address-cells = <1>; 30 #address-cells = <1>;
@@ -33,24 +34,32 @@
33 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
34 reg = <0>; 35 reg = <0>;
35 next-level-cache = <&L2>; 36 next-level-cache = <&L2>;
37 clocks = <&a9pll>;
38 clock-names = "cpu";
36 }; 39 };
37 40
38 cpu@1 { 41 cpu@1 {
39 compatible = "arm,cortex-a9"; 42 compatible = "arm,cortex-a9";
40 reg = <1>; 43 reg = <1>;
41 next-level-cache = <&L2>; 44 next-level-cache = <&L2>;
45 clocks = <&a9pll>;
46 clock-names = "cpu";
42 }; 47 };
43 48
44 cpu@2 { 49 cpu@2 {
45 compatible = "arm,cortex-a9"; 50 compatible = "arm,cortex-a9";
46 reg = <2>; 51 reg = <2>;
47 next-level-cache = <&L2>; 52 next-level-cache = <&L2>;
53 clocks = <&a9pll>;
54 clock-names = "cpu";
48 }; 55 };
49 56
50 cpu@3 { 57 cpu@3 {
51 compatible = "arm,cortex-a9"; 58 compatible = "arm,cortex-a9";
52 reg = <3>; 59 reg = <3>;
53 next-level-cache = <&L2>; 60 next-level-cache = <&L2>;
61 clocks = <&a9pll>;
62 clock-names = "cpu";
54 }; 63 };
55 }; 64 };
56 65
@@ -75,12 +84,14 @@
75 compatible = "arm,cortex-a9-twd-timer"; 84 compatible = "arm,cortex-a9-twd-timer";
76 reg = <0xfff10600 0x20>; 85 reg = <0xfff10600 0x20>;
77 interrupts = <1 13 0xf01>; 86 interrupts = <1 13 0xf01>;
87 clocks = <&a9periphclk>;
78 }; 88 };
79 89
80 watchdog@fff10620 { 90 watchdog@fff10620 {
81 compatible = "arm,cortex-a9-twd-wdt"; 91 compatible = "arm,cortex-a9-twd-wdt";
82 reg = <0xfff10620 0x20>; 92 reg = <0xfff10620 0x20>;
83 interrupts = <1 14 0xf01>; 93 interrupts = <1 14 0xf01>;
94 clocks = <&a9periphclk>;
84 }; 95 };
85 96
86 intc: interrupt-controller@fff11000 { 97 intc: interrupt-controller@fff11000 {
@@ -116,12 +127,15 @@
116 compatible = "calxeda,hb-sdhci"; 127 compatible = "calxeda,hb-sdhci";
117 reg = <0xffe0e000 0x1000>; 128 reg = <0xffe0e000 0x1000>;
118 interrupts = <0 90 4>; 129 interrupts = <0 90 4>;
130 clocks = <&eclk>;
119 }; 131 };
120 132
121 ipc@fff20000 { 133 ipc@fff20000 {
122 compatible = "arm,pl320", "arm,primecell"; 134 compatible = "arm,pl320", "arm,primecell";
123 reg = <0xfff20000 0x1000>; 135 reg = <0xfff20000 0x1000>;
124 interrupts = <0 7 4>; 136 interrupts = <0 7 4>;
137 clocks = <&pclk>;
138 clock-names = "apb_pclk";
125 }; 139 };
126 140
127 gpioe: gpio@fff30000 { 141 gpioe: gpio@fff30000 {
@@ -130,6 +144,8 @@
130 gpio-controller; 144 gpio-controller;
131 reg = <0xfff30000 0x1000>; 145 reg = <0xfff30000 0x1000>;
132 interrupts = <0 14 4>; 146 interrupts = <0 14 4>;
147 clocks = <&pclk>;
148 clock-names = "apb_pclk";
133 }; 149 };
134 150
135 gpiof: gpio@fff31000 { 151 gpiof: gpio@fff31000 {
@@ -138,6 +154,8 @@
138 gpio-controller; 154 gpio-controller;
139 reg = <0xfff31000 0x1000>; 155 reg = <0xfff31000 0x1000>;
140 interrupts = <0 15 4>; 156 interrupts = <0 15 4>;
157 clocks = <&pclk>;
158 clock-names = "apb_pclk";
141 }; 159 };
142 160
143 gpiog: gpio@fff32000 { 161 gpiog: gpio@fff32000 {
@@ -146,6 +164,8 @@
146 gpio-controller; 164 gpio-controller;
147 reg = <0xfff32000 0x1000>; 165 reg = <0xfff32000 0x1000>;
148 interrupts = <0 16 4>; 166 interrupts = <0 16 4>;
167 clocks = <&pclk>;
168 clock-names = "apb_pclk";
149 }; 169 };
150 170
151 gpioh: gpio@fff33000 { 171 gpioh: gpio@fff33000 {
@@ -154,24 +174,32 @@
154 gpio-controller; 174 gpio-controller;
155 reg = <0xfff33000 0x1000>; 175 reg = <0xfff33000 0x1000>;
156 interrupts = <0 17 4>; 176 interrupts = <0 17 4>;
177 clocks = <&pclk>;
178 clock-names = "apb_pclk";
157 }; 179 };
158 180
159 timer { 181 timer {
160 compatible = "arm,sp804", "arm,primecell"; 182 compatible = "arm,sp804", "arm,primecell";
161 reg = <0xfff34000 0x1000>; 183 reg = <0xfff34000 0x1000>;
162 interrupts = <0 18 4>; 184 interrupts = <0 18 4>;
185 clocks = <&pclk>;
186 clock-names = "apb_pclk";
163 }; 187 };
164 188
165 rtc@fff35000 { 189 rtc@fff35000 {
166 compatible = "arm,pl031", "arm,primecell"; 190 compatible = "arm,pl031", "arm,primecell";
167 reg = <0xfff35000 0x1000>; 191 reg = <0xfff35000 0x1000>;
168 interrupts = <0 19 4>; 192 interrupts = <0 19 4>;
193 clocks = <&pclk>;
194 clock-names = "apb_pclk";
169 }; 195 };
170 196
171 serial@fff36000 { 197 serial@fff36000 {
172 compatible = "arm,pl011", "arm,primecell"; 198 compatible = "arm,pl011", "arm,primecell";
173 reg = <0xfff36000 0x1000>; 199 reg = <0xfff36000 0x1000>;
174 interrupts = <0 20 4>; 200 interrupts = <0 20 4>;
201 clocks = <&pclk>;
202 clock-names = "apb_pclk";
175 }; 203 };
176 204
177 smic@fff3a000 { 205 smic@fff3a000 {
@@ -186,12 +214,73 @@
186 sregs@fff3c000 { 214 sregs@fff3c000 {
187 compatible = "calxeda,hb-sregs"; 215 compatible = "calxeda,hb-sregs";
188 reg = <0xfff3c000 0x1000>; 216 reg = <0xfff3c000 0x1000>;
217
218 clocks {
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 osc: oscillator {
223 #clock-cells = <0>;
224 compatible = "fixed-clock";
225 clock-frequency = <33333000>;
226 };
227
228 ddrpll: ddrpll {
229 #clock-cells = <0>;
230 compatible = "calxeda,hb-pll-clock";
231 clocks = <&osc>;
232 reg = <0x108>;
233 };
234
235 a9pll: a9pll {
236 #clock-cells = <0>;
237 compatible = "calxeda,hb-pll-clock";
238 clocks = <&osc>;
239 reg = <0x100>;
240 };
241
242 a9periphclk: a9periphclk {
243 #clock-cells = <0>;
244 compatible = "calxeda,hb-a9periph-clock";
245 clocks = <&a9pll>;
246 reg = <0x104>;
247 };
248
249 a9bclk: a9bclk {
250 #clock-cells = <0>;
251 compatible = "calxeda,hb-a9bus-clock";
252 clocks = <&a9pll>;
253 reg = <0x104>;
254 };
255
256 emmcpll: emmcpll {
257 #clock-cells = <0>;
258 compatible = "calxeda,hb-pll-clock";
259 clocks = <&osc>;
260 reg = <0x10C>;
261 };
262
263 eclk: eclk {
264 #clock-cells = <0>;
265 compatible = "calxeda,hb-emmc-clock";
266 clocks = <&emmcpll>;
267 reg = <0x114>;
268 };
269
270 pclk: pclk {
271 #clock-cells = <0>;
272 compatible = "fixed-clock";
273 clock-frequency = <150000000>;
274 };
275 };
189 }; 276 };
190 277
191 dma@fff3d000 { 278 dma@fff3d000 {
192 compatible = "arm,pl330", "arm,primecell"; 279 compatible = "arm,pl330", "arm,primecell";
193 reg = <0xfff3d000 0x1000>; 280 reg = <0xfff3d000 0x1000>;
194 interrupts = <0 92 4>; 281 interrupts = <0 92 4>;
282 clocks = <&pclk>;
283 clock-names = "apb_pclk";
195 }; 284 };
196 285
197 ethernet@fff50000 { 286 ethernet@fff50000 {
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index ded4652ada80..3ec8bdd25d09 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -1,4 +1,4 @@
1obj-y := clock.o highbank.o system.o smc.o 1obj-y := highbank.o system.o smc.o
2 2
3plus_sec := $(call as-instr,.arch_extension sec,+sec) 3plus_sec := $(call as-instr,.arch_extension sec,+sec)
4AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) 4AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-highbank/clock.c b/arch/arm/mach-highbank/clock.c
deleted file mode 100644
index c25a2ae4fde1..000000000000
--- a/arch/arm/mach-highbank/clock.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/clk.h>
20#include <linux/clkdev.h>
21
22struct clk {
23 unsigned long rate;
24};
25
26int clk_enable(struct clk *clk)
27{
28 return 0;
29}
30
31void clk_disable(struct clk *clk)
32{}
33
34unsigned long clk_get_rate(struct clk *clk)
35{
36 return clk->rate;
37}
38
39long clk_round_rate(struct clk *clk, unsigned long rate)
40{
41 return clk->rate;
42}
43
44int clk_set_rate(struct clk *clk, unsigned long rate)
45{
46 return 0;
47}
48
49static struct clk eclk = { .rate = 200000000 };
50static struct clk pclk = { .rate = 150000000 };
51
52static struct clk_lookup lookups[] = {
53 { .clk = &pclk, .con_id = "apb_pclk", },
54 { .clk = &pclk, .dev_id = "sp804", },
55 { .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
56 { .clk = &pclk, .dev_id = "fff36000.serial", },
57};
58
59void __init highbank_clocks_init(void)
60{
61 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
62}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8777612b1a42..d75b0a78d88a 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -105,6 +105,11 @@ static void __init highbank_init_irq(void)
105#endif 105#endif
106} 106}
107 107
108static struct clk_lookup lookup = {
109 .dev_id = "sp804",
110 .con_id = NULL,
111};
112
108static void __init highbank_timer_init(void) 113static void __init highbank_timer_init(void)
109{ 114{
110 int irq; 115 int irq;
@@ -122,6 +127,8 @@ static void __init highbank_timer_init(void)
122 irq = irq_of_parse_and_map(np, 0); 127 irq = irq_of_parse_and_map(np, 0);
123 128
124 highbank_clocks_init(); 129 highbank_clocks_init();
130 lookup.clk = of_clk_get(np, 0);
131 clkdev_add(&lookup);
125 132
126 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); 133 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
127 sp804_clockevents_init(timer_base, irq, "timer0"); 134 sp804_clockevents_init(timer_base, irq, "timer0");
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index eaf6c6366ffa..ebf680bebdf2 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -21,7 +21,6 @@
21#include <linux/amba/bus.h> 21#include <linux/amba/bus.h>
22#include <linux/amba/serial.h> 22#include <linux/amba/serial.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h>
25 24
26#include <mach/hardware.h> 25#include <mach/hardware.h>
27#include <mach/platform.h> 26#include <mach/platform.h>
@@ -41,17 +40,17 @@ static struct amba_pl010_data integrator_uart_data;
41#define KMI0_IRQ { IRQ_KMIINT0 } 40#define KMI0_IRQ { IRQ_KMIINT0 }
42#define KMI1_IRQ { IRQ_KMIINT1 } 41#define KMI1_IRQ { IRQ_KMIINT1 }
43 42
44static AMBA_APB_DEVICE(rtc, "mb:15", 0, 43static AMBA_APB_DEVICE(rtc, "rtc", 0,
45 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL); 44 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
46 45
47static AMBA_APB_DEVICE(uart0, "mb:16", 0, 46static AMBA_APB_DEVICE(uart0, "uart0", 0,
48 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data); 47 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
49 48
50static AMBA_APB_DEVICE(uart1, "mb:17", 0, 49static AMBA_APB_DEVICE(uart1, "uart1", 0,
51 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data); 50 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
52 51
53static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL); 52static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
54static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL); 53static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
55 54
56static struct amba_device *amba_devs[] __initdata = { 55static struct amba_device *amba_devs[] __initdata = {
57 &rtc_device, 56 &rtc_device,
@@ -61,50 +60,6 @@ static struct amba_device *amba_devs[] __initdata = {
61 &kmi1_device, 60 &kmi1_device,
62}; 61};
63 62
64/*
65 * These are fixed clocks.
66 */
67static struct clk clk24mhz = {
68 .rate = 24000000,
69};
70
71static struct clk uartclk = {
72 .rate = 14745600,
73};
74
75static struct clk dummy_apb_pclk;
76
77static struct clk_lookup lookups[] = {
78 { /* Bus clock */
79 .con_id = "apb_pclk",
80 .clk = &dummy_apb_pclk,
81 }, {
82 /* Integrator/AP timer frequency */
83 .dev_id = "ap_timer",
84 .clk = &clk24mhz,
85 }, { /* UART0 */
86 .dev_id = "mb:16",
87 .clk = &uartclk,
88 }, { /* UART1 */
89 .dev_id = "mb:17",
90 .clk = &uartclk,
91 }, { /* KMI0 */
92 .dev_id = "mb:18",
93 .clk = &clk24mhz,
94 }, { /* KMI1 */
95 .dev_id = "mb:19",
96 .clk = &clk24mhz,
97 }, { /* MMCI - IntegratorCP */
98 .dev_id = "mb:1c",
99 .clk = &uartclk,
100 }
101};
102
103void __init integrator_init_early(void)
104{
105 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
106}
107
108static int __init integrator_init(void) 63static int __init integrator_init(void)
109{ 64{
110 int i; 65 int i;
diff --git a/arch/arm/mach-integrator/include/mach/clkdev.h b/arch/arm/mach-integrator/include/mach/clkdev.h
deleted file mode 100644
index bfe07679faec..000000000000
--- a/arch/arm/mach-integrator/include/mach/clkdev.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#include <linux/module.h>
5#include <plat/clock.h>
6
7struct clk {
8 unsigned long rate;
9 const struct clk_ops *ops;
10 struct module *owner;
11 const struct icst_params *params;
12 void __iomem *vcoreg;
13 void *data;
14};
15
16static inline int __clk_get(struct clk *clk)
17{
18 return try_module_get(clk->owner);
19}
20
21static inline void __clk_put(struct clk *clk)
22{
23 module_put(clk->owner);
24}
25
26#endif
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index c857501c5783..7b1055c8e0b9 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -33,6 +33,7 @@
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/platform_data/clk-integrator.h>
36#include <video/vga.h> 37#include <video/vga.h>
37 38
38#include <mach/hardware.h> 39#include <mach/hardware.h>
@@ -174,6 +175,7 @@ static void __init ap_init_irq(void)
174 175
175 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, 176 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
176 -1, INTEGRATOR_SC_VALID_INT, NULL); 177 -1, INTEGRATOR_SC_VALID_INT, NULL);
178 integrator_clk_init(false);
177} 179}
178 180
179#ifdef CONFIG_PM 181#ifdef CONFIG_PM
@@ -440,6 +442,10 @@ static void integrator_clockevent_init(unsigned long inrate)
440 0xffffU); 442 0xffffU);
441} 443}
442 444
445void __init ap_init_early(void)
446{
447}
448
443/* 449/*
444 * Set up timer(s). 450 * Set up timer(s).
445 */ 451 */
@@ -471,7 +477,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
471 .reserve = integrator_reserve, 477 .reserve = integrator_reserve,
472 .map_io = ap_map_io, 478 .map_io = ap_map_io,
473 .nr_irqs = NR_IRQS_INTEGRATOR_AP, 479 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
474 .init_early = integrator_init_early, 480 .init_early = ap_init_early,
475 .init_irq = ap_init_irq, 481 .init_irq = ap_init_irq,
476 .handle_irq = fpga_handle_irq, 482 .handle_irq = fpga_handle_irq,
477 .timer = &ap_timer, 483 .timer = &ap_timer,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a56c53608939..82d5c837cc74 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -21,8 +21,8 @@
21#include <linux/amba/mmci.h> 21#include <linux/amba/mmci.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/gfp.h> 23#include <linux/gfp.h>
24#include <linux/clkdev.h>
25#include <linux/mtd/physmap.h> 24#include <linux/mtd/physmap.h>
25#include <linux/platform_data/clk-integrator.h>
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/platform.h> 28#include <mach/platform.h>
@@ -171,65 +171,10 @@ static void __init intcp_init_irq(void)
171 171
172 fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, 172 fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
173 IRQ_CP_CPPLDINT, sic_mask, NULL); 173 IRQ_CP_CPPLDINT, sic_mask, NULL);
174 integrator_clk_init(true);
174} 175}
175 176
176/* 177/*
177 * Clock handling
178 */
179#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
180#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
181
182static const struct icst_params cp_auxvco_params = {
183 .ref = 24000000,
184 .vco_max = ICST525_VCO_MAX_5V,
185 .vco_min = ICST525_VCO_MIN,
186 .vd_min = 8,
187 .vd_max = 263,
188 .rd_min = 3,
189 .rd_max = 65,
190 .s2div = icst525_s2div,
191 .idx2s = icst525_idx2s,
192};
193
194static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
195{
196 u32 val;
197
198 val = readl(clk->vcoreg) & ~0x7ffff;
199 val |= vco.v | (vco.r << 9) | (vco.s << 16);
200
201 writel(0xa05f, CM_LOCK);
202 writel(val, clk->vcoreg);
203 writel(0, CM_LOCK);
204}
205
206static const struct clk_ops cp_auxclk_ops = {
207 .round = icst_clk_round,
208 .set = icst_clk_set,
209 .setvco = cp_auxvco_set,
210};
211
212static struct clk cp_auxclk = {
213 .ops = &cp_auxclk_ops,
214 .params = &cp_auxvco_params,
215 .vcoreg = CM_AUXOSC,
216};
217
218static struct clk sp804_clk = {
219 .rate = 1000000,
220};
221
222static struct clk_lookup cp_lookups[] = {
223 { /* CLCD */
224 .dev_id = "mb:c0",
225 .clk = &cp_auxclk,
226 }, { /* SP804 timers */
227 .dev_id = "sp804",
228 .clk = &sp804_clk,
229 },
230};
231
232/*
233 * Flash handling. 178 * Flash handling.
234 */ 179 */
235static int intcp_flash_init(struct platform_device *dev) 180static int intcp_flash_init(struct platform_device *dev)
@@ -336,10 +281,10 @@ static struct mmci_platform_data mmc_data = {
336#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } 281#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
337#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } 282#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
338 283
339static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE, 284static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
340 INTEGRATOR_CP_MMC_IRQS, &mmc_data); 285 INTEGRATOR_CP_MMC_IRQS, &mmc_data);
341 286
342static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE, 287static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
343 INTEGRATOR_CP_AACI_IRQS, NULL); 288 INTEGRATOR_CP_AACI_IRQS, NULL);
344 289
345 290
@@ -393,7 +338,7 @@ static struct clcd_board clcd_data = {
393 .remove = versatile_clcd_remove_dma, 338 .remove = versatile_clcd_remove_dma,
394}; 339};
395 340
396static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE, 341static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
397 { IRQ_CP_CLCDCINT }, &clcd_data); 342 { IRQ_CP_CLCDCINT }, &clcd_data);
398 343
399static struct amba_device *amba_devs[] __initdata = { 344static struct amba_device *amba_devs[] __initdata = {
@@ -406,10 +351,6 @@ static struct amba_device *amba_devs[] __initdata = {
406 351
407static void __init intcp_init_early(void) 352static void __init intcp_init_early(void)
408{ 353{
409 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
410
411 integrator_init_early();
412
413#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK 354#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
414 versatile_sched_clock_init(REFCOUNTER, 24000000); 355 versatile_sched_clock_init(REFCOUNTER, 24000000);
415#endif 356#endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index fd3a5c382f47..7e47d37aeb0e 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel, U300 machine. 2# Makefile for the linux kernel, U300 machine.
3# 3#
4 4
5obj-y := core.o clock.o timer.o 5obj-y := core.o timer.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
deleted file mode 100644
index 5535dd0a78c9..000000000000
--- a/arch/arm/mach-u300/clock.c
+++ /dev/null
@@ -1,1504 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/clock.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Define clocks in the app platform.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/clk.h>
20#include <linux/mutex.h>
21#include <linux/spinlock.h>
22#include <linux/debugfs.h>
23#include <linux/device.h>
24#include <linux/init.h>
25#include <linux/timer.h>
26#include <linux/io.h>
27#include <linux/seq_file.h>
28#include <linux/clkdev.h>
29
30#include <mach/hardware.h>
31#include <mach/syscon.h>
32
33#include "clock.h"
34
35/*
36 * TODO:
37 * - move all handling of the CCR register into this file and create
38 * a spinlock for the CCR register
39 * - switch to the clkdevice lookup mechanism that maps clocks to
40 * device ID:s instead when it becomes available in kernel 2.6.29.
41 * - implement rate get/set for all clocks that need it.
42 */
43
44/*
45 * Syscon clock I/O registers lock so clock requests don't collide
46 * NOTE: this is a local lock only used to lock access to clock and
47 * reset registers in syscon.
48 */
49static DEFINE_SPINLOCK(syscon_clkreg_lock);
50static DEFINE_SPINLOCK(syscon_resetreg_lock);
51
52/*
53 * The clocking hierarchy currently looks like this.
54 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
55 * The ideas is to show dependencies, so a clock higher up in the
56 * hierarchy has to be on in order for another clock to be on. Now,
57 * both CPU and DMA can actually be on top of the hierarchy, and that
58 * is not modeled currently. Instead we have the backbone AMBA bus on
59 * top. This bus cannot be programmed in any way but conceptually it
60 * needs to be active for the bridges and devices to transport data.
61 *
62 * Please be aware that a few clocks are hw controlled, which mean that
63 * the hw itself can turn on/off or change the rate of the clock when
64 * needed!
65 *
66 * AMBA bus
67 * |
68 * +- CPU
69 * +- FSMC NANDIF NAND Flash interface
70 * +- SEMI Shared Memory interface
71 * +- ISP Image Signal Processor (U335 only)
72 * +- CDS (U335 only)
73 * +- DMA Direct Memory Access Controller
74 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
75 * +- APEX
76 * +- VIDEO_ENC AVE2/3 Video Encoder
77 * +- XGAM Graphics Accelerator Controller
78 * +- AHB
79 * |
80 * +- ahb:0 AHB Bridge
81 * | |
82 * | +- ahb:1 INTCON Interrupt controller
83 * | +- ahb:3 MSPRO Memory Stick Pro controller
84 * | +- ahb:4 EMIF External Memory interface
85 * |
86 * +- fast:0 FAST bridge
87 * | |
88 * | +- fast:1 MMCSD MMC/SD card reader controller
89 * | +- fast:2 I2S0 PCM I2S channel 0 controller
90 * | +- fast:3 I2S1 PCM I2S channel 1 controller
91 * | +- fast:4 I2C0 I2C channel 0 controller
92 * | +- fast:5 I2C1 I2C channel 1 controller
93 * | +- fast:6 SPI SPI controller
94 * | +- fast:7 UART1 Secondary UART (U335 only)
95 * |
96 * +- slow:0 SLOW bridge
97 * |
98 * +- slow:1 SYSCON (not possible to control)
99 * +- slow:2 WDOG Watchdog
100 * +- slow:3 UART0 primary UART
101 * +- slow:4 TIMER_APP Application timer - used in Linux
102 * +- slow:5 KEYPAD controller
103 * +- slow:6 GPIO controller
104 * +- slow:7 RTC controller
105 * +- slow:8 BT Bus Tracer (not used currently)
106 * +- slow:9 EH Event Handler (not used currently)
107 * +- slow:a TIMER_ACC Access style timer (not used currently)
108 * +- slow:b PPM (U335 only, what is that?)
109 */
110
111/*
112 * Reset control functions. We remember if a block has been
113 * taken out of reset and don't remove the reset assertion again
114 * and vice versa. Currently we only remove resets so the
115 * enablement function is defined out.
116 */
117static void syscon_block_reset_enable(struct clk *clk)
118{
119 u16 val;
120 unsigned long iflags;
121
122 /* Not all blocks support resetting */
123 if (!clk->res_reg || !clk->res_mask)
124 return;
125 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
126 val = readw(clk->res_reg);
127 val |= clk->res_mask;
128 writew(val, clk->res_reg);
129 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
130 clk->reset = true;
131}
132
133static void syscon_block_reset_disable(struct clk *clk)
134{
135 u16 val;
136 unsigned long iflags;
137
138 /* Not all blocks support resetting */
139 if (!clk->res_reg || !clk->res_mask)
140 return;
141 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
142 val = readw(clk->res_reg);
143 val &= ~clk->res_mask;
144 writew(val, clk->res_reg);
145 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
146 clk->reset = false;
147}
148
149int __clk_get(struct clk *clk)
150{
151 u16 val;
152
153 /* The MMC and MSPRO clocks need some special set-up */
154 if (!strcmp(clk->name, "MCLK")) {
155 /* Set default MMC clock divisor to 18.9 MHz */
156 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
157 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
158 /* Disable the MMC feedback clock */
159 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
160 /* Disable MSPRO frequency */
161 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
162 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
163 }
164 if (!strcmp(clk->name, "MSPRO")) {
165 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
166 /* Disable the MMC feedback clock */
167 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
168 /* Enable MSPRO frequency */
169 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
170 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
171 }
172 return 1;
173}
174EXPORT_SYMBOL(__clk_get);
175
176void __clk_put(struct clk *clk)
177{
178}
179EXPORT_SYMBOL(__clk_put);
180
181static void syscon_clk_disable(struct clk *clk)
182{
183 unsigned long iflags;
184
185 /* Don't touch the hardware controlled clocks */
186 if (clk->hw_ctrld)
187 return;
188
189 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
190 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
191 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
192}
193
194static void syscon_clk_enable(struct clk *clk)
195{
196 unsigned long iflags;
197
198 /* Don't touch the hardware controlled clocks */
199 if (clk->hw_ctrld)
200 return;
201
202 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
203 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
204 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
205}
206
207static u16 syscon_clk_get_rate(void)
208{
209 u16 val;
210 unsigned long iflags;
211
212 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
214 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
215 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
216 return val;
217}
218
219#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
220static void enable_i2s0_vcxo(void)
221{
222 u16 val;
223 unsigned long iflags;
224
225 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
226 /* Set I2S0 to use the VCXO 26 MHz clock */
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
228 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
230 val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
232 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
233 val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
234 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
235 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
236}
237
238static void enable_i2s1_vcxo(void)
239{
240 u16 val;
241 unsigned long iflags;
242
243 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
244 /* Set I2S1 to use the VCXO 26 MHz clock */
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
246 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
248 val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
250 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
251 val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
252 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
253 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
254}
255
256static void disable_i2s0_vcxo(void)
257{
258 u16 val;
259 unsigned long iflags;
260
261 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
262 /* Disable I2S0 use of the VCXO 26 MHz clock */
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
264 val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
266 /* Deactivate VCXO if no one else is using VCXO */
267 if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
268 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
270 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
271 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
272 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
273 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
274}
275
276static void disable_i2s1_vcxo(void)
277{
278 u16 val;
279 unsigned long iflags;
280
281 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
282 /* Disable I2S1 use of the VCXO 26 MHz clock */
283 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
284 val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
285 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
286 /* Deactivate VCXO if no one else is using VCXO */
287 if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
288 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
289 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
290 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
291 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
292 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
293 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
294}
295#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
296
297
298static void syscon_clk_rate_set_mclk(unsigned long rate)
299{
300 u16 val;
301 u32 reg;
302 unsigned long iflags;
303
304 switch (rate) {
305 case 18900000:
306 val = 0x0054;
307 break;
308 case 20800000:
309 val = 0x0044;
310 break;
311 case 23100000:
312 val = 0x0043;
313 break;
314 case 26000000:
315 val = 0x0033;
316 break;
317 case 29700000:
318 val = 0x0032;
319 break;
320 case 34700000:
321 val = 0x0022;
322 break;
323 case 41600000:
324 val = 0x0021;
325 break;
326 case 52000000:
327 val = 0x0011;
328 break;
329 case 104000000:
330 val = 0x0000;
331 break;
332 default:
333 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
334 rate);
335 return;
336 }
337
338 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
339 reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
340 ~U300_SYSCON_MMF0R_MASK;
341 writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
342 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
343}
344
345void syscon_clk_rate_set_cpuclk(unsigned long rate)
346{
347 u16 val;
348 unsigned long iflags;
349
350 switch (rate) {
351 case 13000000:
352 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
353 break;
354 case 52000000:
355 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
356 break;
357 case 104000000:
358 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
359 break;
360 case 208000000:
361 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
362 break;
363 default:
364 return;
365 }
366 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
367 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
368 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
369 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
370 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
371}
372EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
373
374void clk_disable(struct clk *clk)
375{
376 unsigned long iflags;
377
378 spin_lock_irqsave(&clk->lock, iflags);
379 if (clk->usecount > 0 && !(--clk->usecount)) {
380 /* some blocks lack clocking registers and cannot be disabled */
381 if (clk->disable)
382 clk->disable(clk);
383 if (likely((u32)clk->parent))
384 clk_disable(clk->parent);
385 }
386#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
387 if (unlikely(!strcmp(clk->name, "I2S0")))
388 disable_i2s0_vcxo();
389 if (unlikely(!strcmp(clk->name, "I2S1")))
390 disable_i2s1_vcxo();
391#endif
392 spin_unlock_irqrestore(&clk->lock, iflags);
393}
394EXPORT_SYMBOL(clk_disable);
395
396int clk_enable(struct clk *clk)
397{
398 int ret = 0;
399 unsigned long iflags;
400
401 spin_lock_irqsave(&clk->lock, iflags);
402 if (clk->usecount++ == 0) {
403 if (likely((u32)clk->parent))
404 ret = clk_enable(clk->parent);
405
406 if (unlikely(ret != 0))
407 clk->usecount--;
408 else {
409 /* remove reset line (we never enable reset again) */
410 syscon_block_reset_disable(clk);
411 /* clocks without enable function are always on */
412 if (clk->enable)
413 clk->enable(clk);
414#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
415 if (unlikely(!strcmp(clk->name, "I2S0")))
416 enable_i2s0_vcxo();
417 if (unlikely(!strcmp(clk->name, "I2S1")))
418 enable_i2s1_vcxo();
419#endif
420 }
421 }
422 spin_unlock_irqrestore(&clk->lock, iflags);
423 return ret;
424
425}
426EXPORT_SYMBOL(clk_enable);
427
428/* Returns the clock rate in Hz */
429static unsigned long clk_get_rate_cpuclk(struct clk *clk)
430{
431 u16 val;
432
433 val = syscon_clk_get_rate();
434
435 switch (val) {
436 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
437 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
438 return 13000000;
439 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
440 return 52000000;
441 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
442 return 104000000;
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
444 return 208000000;
445 default:
446 break;
447 }
448 return clk->rate;
449}
450
451static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
452{
453 u16 val;
454
455 val = syscon_clk_get_rate();
456
457 switch (val) {
458 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
459 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
460 return 6500000;
461 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
462 return 26000000;
463 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
464 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
465 return 52000000;
466 default:
467 break;
468 }
469 return clk->rate;
470
471}
472
473static unsigned long clk_get_rate_emif_clk(struct clk *clk)
474{
475 u16 val;
476
477 val = syscon_clk_get_rate();
478
479 switch (val) {
480 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
481 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
482 return 13000000;
483 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
484 return 52000000;
485 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
486 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
487 return 104000000;
488 default:
489 break;
490 }
491 return clk->rate;
492
493}
494
495static unsigned long clk_get_rate_xgamclk(struct clk *clk)
496{
497 u16 val;
498
499 val = syscon_clk_get_rate();
500
501 switch (val) {
502 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
503 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
504 return 6500000;
505 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
506 return 26000000;
507 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
508 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
509 return 52000000;
510 default:
511 break;
512 }
513
514 return clk->rate;
515}
516
517static unsigned long clk_get_rate_mclk(struct clk *clk)
518{
519 u16 val;
520
521 val = syscon_clk_get_rate();
522
523 switch (val) {
524 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
525 /*
526 * Here, the 208 MHz PLL gets shut down and the always
527 * on 13 MHz PLL used for RTC etc kicks into use
528 * instead.
529 */
530 return 13000000;
531 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
532 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
533 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
534 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
535 {
536 /*
537 * This clock is under program control. The register is
538 * divided in two nybbles, bit 7-4 gives cycles-1 to count
539 * high, bit 3-0 gives cycles-1 to count low. Distribute
540 * these with no more than 1 cycle difference between
541 * low and high and add low and high to get the actual
542 * divisor. The base PLL is 208 MHz. Writing 0x00 will
543 * divide by 1 and 1 so the highest frequency possible
544 * is 104 MHz.
545 *
546 * e.g. 0x54 =>
547 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
548 */
549 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
550 U300_SYSCON_MMF0R_MASK;
551 switch (val) {
552 case 0x0054:
553 return 18900000;
554 case 0x0044:
555 return 20800000;
556 case 0x0043:
557 return 23100000;
558 case 0x0033:
559 return 26000000;
560 case 0x0032:
561 return 29700000;
562 case 0x0022:
563 return 34700000;
564 case 0x0021:
565 return 41600000;
566 case 0x0011:
567 return 52000000;
568 case 0x0000:
569 return 104000000;
570 default:
571 break;
572 }
573 }
574 default:
575 break;
576 }
577
578 return clk->rate;
579}
580
581static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
582{
583 u16 val;
584
585 val = syscon_clk_get_rate();
586
587 switch (val) {
588 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
589 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
590 return 13000000;
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
592 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
593 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
594 return 26000000;
595 default:
596 break;
597 }
598
599 return clk->rate;
600}
601
602unsigned long clk_get_rate(struct clk *clk)
603{
604 if (clk->get_rate)
605 return clk->get_rate(clk);
606 else
607 return clk->rate;
608}
609EXPORT_SYMBOL(clk_get_rate);
610
611static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
612{
613 if (rate <= 18900000)
614 return 18900000;
615 if (rate <= 20800000)
616 return 20800000;
617 if (rate <= 23100000)
618 return 23100000;
619 if (rate <= 26000000)
620 return 26000000;
621 if (rate <= 29700000)
622 return 29700000;
623 if (rate <= 34700000)
624 return 34700000;
625 if (rate <= 41600000)
626 return 41600000;
627 if (rate <= 52000000)
628 return 52000000;
629 return -EINVAL;
630}
631
632static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
633{
634 if (rate <= 13000000)
635 return 13000000;
636 if (rate <= 52000000)
637 return 52000000;
638 if (rate <= 104000000)
639 return 104000000;
640 if (rate <= 208000000)
641 return 208000000;
642 return -EINVAL;
643}
644
645/*
646 * This adjusts a requested rate to the closest exact rate
647 * a certain clock can provide. For a fixed clock it's
648 * mostly clk->rate.
649 */
650long clk_round_rate(struct clk *clk, unsigned long rate)
651{
652 /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
653 /* Else default to fixed value */
654
655 if (clk->round_rate) {
656 return (long) clk->round_rate(clk, rate);
657 } else {
658 printk(KERN_ERR "clock: Failed to round rate of %s\n",
659 clk->name);
660 }
661 return (long) clk->rate;
662}
663EXPORT_SYMBOL(clk_round_rate);
664
665static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
666{
667 syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
668 return 0;
669}
670
671static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
672{
673 syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
674 return 0;
675}
676
677int clk_set_rate(struct clk *clk, unsigned long rate)
678{
679 /* TODO: set for EMIFCLK and AHBCLK */
680 /* Else assume the clock is fixed and fail */
681 if (clk->set_rate) {
682 return clk->set_rate(clk, rate);
683 } else {
684 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
685 clk->name, rate);
686 return -EINVAL;
687 }
688}
689EXPORT_SYMBOL(clk_set_rate);
690
691/*
692 * Clock definitions. The clock parents are set to respective
693 * bridge and the clock framework makes sure that the clocks have
694 * parents activated and are brought out of reset when in use.
695 *
696 * Clocks that have hw_ctrld = true are hw controlled, and the hw
697 * can by itself turn these clocks on and off.
698 * So in other words, we don't really have to care about them.
699 */
700
701static struct clk amba_clk = {
702 .name = "AMBA",
703 .rate = 52000000, /* this varies! */
704 .hw_ctrld = true,
705 .reset = false,
706 .lock = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
707};
708
709/*
710 * These blocks are connected directly to the AMBA bus
711 * with no bridge.
712 */
713
714static struct clk cpu_clk = {
715 .name = "CPU",
716 .parent = &amba_clk,
717 .rate = 208000000, /* this varies! */
718 .hw_ctrld = true,
719 .reset = true,
720 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
721 .res_mask = U300_SYSCON_RRR_CPU_RESET_EN,
722 .set_rate = clk_set_rate_cpuclk,
723 .get_rate = clk_get_rate_cpuclk,
724 .round_rate = clk_round_rate_cpuclk,
725 .lock = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
726};
727
728static struct clk nandif_clk = {
729 .name = "FSMC",
730 .parent = &amba_clk,
731 .hw_ctrld = false,
732 .reset = true,
733 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
734 .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN,
735 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
736 .enable = syscon_clk_enable,
737 .disable = syscon_clk_disable,
738 .lock = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
739};
740
741static struct clk semi_clk = {
742 .name = "SEMI",
743 .parent = &amba_clk,
744 .rate = 0, /* FIXME */
745 /* It is not possible to reset SEMI */
746 .hw_ctrld = false,
747 .reset = false,
748 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
749 .enable = syscon_clk_enable,
750 .disable = syscon_clk_disable,
751 .lock = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
752};
753
754#ifdef CONFIG_MACH_U300_BS335
755static struct clk isp_clk = {
756 .name = "ISP",
757 .parent = &amba_clk,
758 .rate = 0, /* FIXME */
759 .hw_ctrld = false,
760 .reset = true,
761 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
762 .res_mask = U300_SYSCON_RRR_ISP_RESET_EN,
763 .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN,
764 .enable = syscon_clk_enable,
765 .disable = syscon_clk_disable,
766 .lock = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
767};
768
769static struct clk cds_clk = {
770 .name = "CDS",
771 .parent = &amba_clk,
772 .rate = 0, /* FIXME */
773 .hw_ctrld = false,
774 .reset = true,
775 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
776 .res_mask = U300_SYSCON_RRR_CDS_RESET_EN,
777 .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN,
778 .enable = syscon_clk_enable,
779 .disable = syscon_clk_disable,
780 .lock = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
781};
782#endif
783
784static struct clk dma_clk = {
785 .name = "DMA",
786 .parent = &amba_clk,
787 .rate = 52000000, /* this varies! */
788 .hw_ctrld = true,
789 .reset = true,
790 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
791 .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN,
792 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
793 .enable = syscon_clk_enable,
794 .disable = syscon_clk_disable,
795 .lock = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
796};
797
798static struct clk aaif_clk = {
799 .name = "AAIF",
800 .parent = &amba_clk,
801 .rate = 52000000, /* this varies! */
802 .hw_ctrld = true,
803 .reset = true,
804 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
805 .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN,
806 .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN,
807 .enable = syscon_clk_enable,
808 .disable = syscon_clk_disable,
809 .lock = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
810};
811
812static struct clk apex_clk = {
813 .name = "APEX",
814 .parent = &amba_clk,
815 .rate = 0, /* FIXME */
816 .hw_ctrld = true,
817 .reset = true,
818 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
819 .res_mask = U300_SYSCON_RRR_APEX_RESET_EN,
820 .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN,
821 .enable = syscon_clk_enable,
822 .disable = syscon_clk_disable,
823 .lock = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
824};
825
826static struct clk video_enc_clk = {
827 .name = "VIDEO_ENC",
828 .parent = &amba_clk,
829 .rate = 208000000, /* this varies! */
830 .hw_ctrld = false,
831 .reset = false,
832 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
833 /* This has XGAM in the name but refers to the video encoder */
834 .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
835 .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
836 .enable = syscon_clk_enable,
837 .disable = syscon_clk_disable,
838 .lock = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
839};
840
841static struct clk xgam_clk = {
842 .name = "XGAMCLK",
843 .parent = &amba_clk,
844 .rate = 52000000, /* this varies! */
845 .hw_ctrld = false,
846 .reset = true,
847 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
848 .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN,
849 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
850 .get_rate = clk_get_rate_xgamclk,
851 .enable = syscon_clk_enable,
852 .disable = syscon_clk_disable,
853 .lock = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
854};
855
856/* This clock is used to activate the video encoder */
857static struct clk ahb_clk = {
858 .name = "AHB",
859 .parent = &amba_clk,
860 .rate = 52000000, /* this varies! */
861 .hw_ctrld = false, /* This one is set to false due to HW bug */
862 .reset = true,
863 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
864 .res_mask = U300_SYSCON_RRR_AHB_RESET_EN,
865 .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN,
866 .enable = syscon_clk_enable,
867 .disable = syscon_clk_disable,
868 .get_rate = clk_get_rate_ahb_clk,
869 .lock = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
870};
871
872
873/*
874 * Clocks on the AHB bridge
875 */
876
877static struct clk ahb_subsys_clk = {
878 .name = "AHB_SUBSYS",
879 .parent = &amba_clk,
880 .rate = 52000000, /* this varies! */
881 .hw_ctrld = true,
882 .reset = false,
883 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
884 .enable = syscon_clk_enable,
885 .disable = syscon_clk_disable,
886 .get_rate = clk_get_rate_ahb_clk,
887 .lock = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
888};
889
890static struct clk intcon_clk = {
891 .name = "INTCON",
892 .parent = &ahb_subsys_clk,
893 .rate = 52000000, /* this varies! */
894 .hw_ctrld = false,
895 .reset = true,
896 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
897 .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN,
898 /* INTCON can be reset but not clock-gated */
899 .lock = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
900
901};
902
903static struct clk mspro_clk = {
904 .name = "MSPRO",
905 .parent = &ahb_subsys_clk,
906 .rate = 0, /* FIXME */
907 .hw_ctrld = false,
908 .reset = true,
909 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
910 .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN,
911 .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN,
912 .enable = syscon_clk_enable,
913 .disable = syscon_clk_disable,
914 .lock = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
915};
916
917static struct clk emif_clk = {
918 .name = "EMIF",
919 .parent = &ahb_subsys_clk,
920 .rate = 104000000, /* this varies! */
921 .hw_ctrld = false,
922 .reset = true,
923 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
924 .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN,
925 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
926 .enable = syscon_clk_enable,
927 .disable = syscon_clk_disable,
928 .get_rate = clk_get_rate_emif_clk,
929 .lock = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
930};
931
932
933/*
934 * Clocks on the FAST bridge
935 */
936static struct clk fast_clk = {
937 .name = "FAST_BRIDGE",
938 .parent = &amba_clk,
939 .rate = 13000000, /* this varies! */
940 .hw_ctrld = true,
941 .reset = true,
942 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
943 .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
944 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
945 .enable = syscon_clk_enable,
946 .disable = syscon_clk_disable,
947 .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
948};
949
950/*
951 * The MMCI apb_pclk is hardwired to the same terminal as the
952 * external MCI clock. Thus this will be referenced twice.
953 */
954static struct clk mmcsd_clk = {
955 .name = "MCLK",
956 .parent = &fast_clk,
957 .rate = 18900000, /* this varies! */
958 .hw_ctrld = false,
959 .reset = true,
960 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
961 .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE,
962 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
963 .get_rate = clk_get_rate_mclk,
964 .set_rate = clk_set_rate_mclk,
965 .round_rate = clk_round_rate_mclk,
966 .disable = syscon_clk_disable,
967 .enable = syscon_clk_enable,
968 .lock = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
969};
970
971static struct clk i2s0_clk = {
972 .name = "i2s0",
973 .parent = &fast_clk,
974 .rate = 26000000, /* this varies! */
975 .hw_ctrld = true,
976 .reset = true,
977 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
978 .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
979 .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
980 .enable = syscon_clk_enable,
981 .disable = syscon_clk_disable,
982 .get_rate = clk_get_rate_i2s_i2c_spi,
983 .lock = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
984};
985
986static struct clk i2s1_clk = {
987 .name = "i2s1",
988 .parent = &fast_clk,
989 .rate = 26000000, /* this varies! */
990 .hw_ctrld = true,
991 .reset = true,
992 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
993 .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
994 .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
995 .enable = syscon_clk_enable,
996 .disable = syscon_clk_disable,
997 .get_rate = clk_get_rate_i2s_i2c_spi,
998 .lock = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
999};
1000
1001static struct clk i2c0_clk = {
1002 .name = "I2C0",
1003 .parent = &fast_clk,
1004 .rate = 26000000, /* this varies! */
1005 .hw_ctrld = false,
1006 .reset = true,
1007 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1008 .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
1009 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
1010 .enable = syscon_clk_enable,
1011 .disable = syscon_clk_disable,
1012 .get_rate = clk_get_rate_i2s_i2c_spi,
1013 .lock = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
1014};
1015
1016static struct clk i2c1_clk = {
1017 .name = "I2C1",
1018 .parent = &fast_clk,
1019 .rate = 26000000, /* this varies! */
1020 .hw_ctrld = false,
1021 .reset = true,
1022 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1023 .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
1024 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
1025 .enable = syscon_clk_enable,
1026 .disable = syscon_clk_disable,
1027 .get_rate = clk_get_rate_i2s_i2c_spi,
1028 .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
1029};
1030
1031/*
1032 * The SPI apb_pclk is hardwired to the same terminal as the
1033 * external SPI clock. Thus this will be referenced twice.
1034 */
1035static struct clk spi_clk = {
1036 .name = "SPI",
1037 .parent = &fast_clk,
1038 .rate = 26000000, /* this varies! */
1039 .hw_ctrld = false,
1040 .reset = true,
1041 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1042 .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1043 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
1044 .enable = syscon_clk_enable,
1045 .disable = syscon_clk_disable,
1046 .get_rate = clk_get_rate_i2s_i2c_spi,
1047 .lock = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
1048};
1049
1050#ifdef CONFIG_MACH_U300_BS335
1051static struct clk uart1_pclk = {
1052 .name = "UART1_PCLK",
1053 .parent = &fast_clk,
1054 .hw_ctrld = false,
1055 .reset = true,
1056 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1057 .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1058 .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN,
1059 .enable = syscon_clk_enable,
1060 .disable = syscon_clk_disable,
1061 .lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
1062};
1063
1064/* This one is hardwired to PLL13 */
1065static struct clk uart1_clk = {
1066 .name = "UART1_CLK",
1067 .rate = 13000000,
1068 .hw_ctrld = true,
1069 .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
1070};
1071#endif
1072
1073
1074/*
1075 * Clocks on the SLOW bridge
1076 */
1077static struct clk slow_clk = {
1078 .name = "SLOW_BRIDGE",
1079 .parent = &amba_clk,
1080 .rate = 13000000,
1081 .hw_ctrld = true,
1082 .reset = true,
1083 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1084 .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1085 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1086 .enable = syscon_clk_enable,
1087 .disable = syscon_clk_disable,
1088 .lock = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
1089};
1090
1091/* TODO: implement SYSCON clock? */
1092
1093static struct clk wdog_clk = {
1094 .name = "WDOG",
1095 .parent = &slow_clk,
1096 .hw_ctrld = false,
1097 .rate = 32768,
1098 .reset = false,
1099 /* This is always on, cannot be enabled/disabled or reset */
1100 .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
1101};
1102
1103static struct clk uart0_pclk = {
1104 .name = "UART0_PCLK",
1105 .parent = &slow_clk,
1106 .hw_ctrld = false,
1107 .reset = true,
1108 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1109 .res_mask = U300_SYSCON_RSR_UART_RESET_EN,
1110 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
1111 .enable = syscon_clk_enable,
1112 .disable = syscon_clk_disable,
1113 .lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
1114};
1115
1116/* This one is hardwired to PLL13 */
1117static struct clk uart0_clk = {
1118 .name = "UART0_CLK",
1119 .parent = &slow_clk,
1120 .rate = 13000000,
1121 .hw_ctrld = true,
1122 .lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
1123};
1124
1125static struct clk keypad_clk = {
1126 .name = "KEYPAD",
1127 .parent = &slow_clk,
1128 .rate = 32768,
1129 .hw_ctrld = false,
1130 .reset = true,
1131 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1132 .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1133 .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1134 .enable = syscon_clk_enable,
1135 .disable = syscon_clk_disable,
1136 .lock = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
1137};
1138
1139static struct clk gpio_clk = {
1140 .name = "GPIO",
1141 .parent = &slow_clk,
1142 .rate = 13000000,
1143 .hw_ctrld = true,
1144 .reset = true,
1145 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1146 .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN,
1147 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
1148 .enable = syscon_clk_enable,
1149 .disable = syscon_clk_disable,
1150 .lock = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
1151};
1152
1153static struct clk rtc_clk = {
1154 .name = "RTC",
1155 .parent = &slow_clk,
1156 .rate = 32768,
1157 .hw_ctrld = true,
1158 .reset = true,
1159 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1160 .res_mask = U300_SYSCON_RSR_RTC_RESET_EN,
1161 /* This clock is always on, cannot be enabled/disabled */
1162 .lock = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
1163};
1164
1165static struct clk bustr_clk = {
1166 .name = "BUSTR",
1167 .parent = &slow_clk,
1168 .rate = 13000000,
1169 .hw_ctrld = true,
1170 .reset = true,
1171 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1172 .res_mask = U300_SYSCON_RSR_BTR_RESET_EN,
1173 .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN,
1174 .enable = syscon_clk_enable,
1175 .disable = syscon_clk_disable,
1176 .lock = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
1177};
1178
1179static struct clk evhist_clk = {
1180 .name = "EVHIST",
1181 .parent = &slow_clk,
1182 .rate = 13000000,
1183 .hw_ctrld = true,
1184 .reset = true,
1185 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1186 .res_mask = U300_SYSCON_RSR_EH_RESET_EN,
1187 .clk_val = U300_SYSCON_SBCER_EH_CLK_EN,
1188 .enable = syscon_clk_enable,
1189 .disable = syscon_clk_disable,
1190 .lock = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
1191};
1192
1193static struct clk timer_clk = {
1194 .name = "TIMER",
1195 .parent = &slow_clk,
1196 .rate = 13000000,
1197 .hw_ctrld = true,
1198 .reset = true,
1199 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1200 .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1201 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1202 .enable = syscon_clk_enable,
1203 .disable = syscon_clk_disable,
1204 .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
1205};
1206
1207/*
1208 * There is a binary divider in the hardware that divides
1209 * the 13MHz PLL by 13 down to 1 MHz.
1210 */
1211static struct clk app_timer_clk = {
1212 .name = "TIMER_APP",
1213 .parent = &slow_clk,
1214 .rate = 1000000,
1215 .hw_ctrld = true,
1216 .reset = true,
1217 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1218 .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1219 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1220 .enable = syscon_clk_enable,
1221 .disable = syscon_clk_disable,
1222 .lock = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
1223};
1224
1225#ifdef CONFIG_MACH_U300_BS335
1226static struct clk ppm_clk = {
1227 .name = "PPM",
1228 .parent = &slow_clk,
1229 .rate = 0, /* FIXME */
1230 .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */
1231 .reset = true,
1232 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1233 .res_mask = U300_SYSCON_RSR_PPM_RESET_EN,
1234 .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN,
1235 .enable = syscon_clk_enable,
1236 .disable = syscon_clk_disable,
1237 .lock = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
1238};
1239#endif
1240
1241#define DEF_LOOKUP(devid, clkref) \
1242 { \
1243 .dev_id = devid, \
1244 .clk = clkref, \
1245 }
1246
1247#define DEF_LOOKUP_CON(devid, conid, clkref) \
1248 { \
1249 .dev_id = devid, \
1250 .con_id = conid, \
1251 .clk = clkref, \
1252 }
1253
1254/*
1255 * Here we only define clocks that are meaningful to
1256 * look up through clockdevice.
1257 */
1258static struct clk_lookup lookups[] = {
1259 /* Connected directly to the AMBA bus */
1260 DEF_LOOKUP("amba", &amba_clk),
1261 DEF_LOOKUP("cpu", &cpu_clk),
1262 DEF_LOOKUP("fsmc-nand", &nandif_clk),
1263 DEF_LOOKUP("semi", &semi_clk),
1264#ifdef CONFIG_MACH_U300_BS335
1265 DEF_LOOKUP("isp", &isp_clk),
1266 DEF_LOOKUP("cds", &cds_clk),
1267#endif
1268 DEF_LOOKUP("dma", &dma_clk),
1269 DEF_LOOKUP("msl", &aaif_clk),
1270 DEF_LOOKUP("apex", &apex_clk),
1271 DEF_LOOKUP("video_enc", &video_enc_clk),
1272 DEF_LOOKUP("xgam", &xgam_clk),
1273 DEF_LOOKUP("ahb", &ahb_clk),
1274 /* AHB bridge clocks */
1275 DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
1276 DEF_LOOKUP("intcon", &intcon_clk),
1277 DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
1278 DEF_LOOKUP("mspro", &mspro_clk),
1279 DEF_LOOKUP("pl172", &emif_clk),
1280 DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
1281 /* FAST bridge clocks */
1282 DEF_LOOKUP("fast", &fast_clk),
1283 DEF_LOOKUP("mmci", &mmcsd_clk),
1284 DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
1285 /*
1286 * The .0 and .1 identifiers on these comes from the platform device
1287 * .id field and are assigned when the platform devices are registered.
1288 */
1289 DEF_LOOKUP("i2s.0", &i2s0_clk),
1290 DEF_LOOKUP("i2s.1", &i2s1_clk),
1291 DEF_LOOKUP("stu300.0", &i2c0_clk),
1292 DEF_LOOKUP("stu300.1", &i2c1_clk),
1293 DEF_LOOKUP("pl022", &spi_clk),
1294 DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
1295#ifdef CONFIG_MACH_U300_BS335
1296 DEF_LOOKUP("uart1", &uart1_clk),
1297 DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
1298#endif
1299 /* SLOW bridge clocks */
1300 DEF_LOOKUP("slow", &slow_clk),
1301 DEF_LOOKUP("coh901327_wdog", &wdog_clk),
1302 DEF_LOOKUP("uart0", &uart0_clk),
1303 DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
1304 DEF_LOOKUP("apptimer", &app_timer_clk),
1305 DEF_LOOKUP("coh901461-keypad", &keypad_clk),
1306 DEF_LOOKUP("u300-gpio", &gpio_clk),
1307 DEF_LOOKUP("rtc-coh901331", &rtc_clk),
1308 DEF_LOOKUP("bustr", &bustr_clk),
1309 DEF_LOOKUP("evhist", &evhist_clk),
1310 DEF_LOOKUP("timer", &timer_clk),
1311#ifdef CONFIG_MACH_U300_BS335
1312 DEF_LOOKUP("ppm", &ppm_clk),
1313#endif
1314};
1315
1316static void __init clk_register(void)
1317{
1318 /* Register the lookups */
1319 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1320}
1321
1322#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1323/*
1324 * The following makes it possible to view the status (especially
1325 * reference count and reset status) for the clocks in the platform
1326 * by looking into the special file <debugfs>/u300_clocks
1327 */
1328
1329/* A list of all clocks in the platform */
1330static struct clk *clks[] = {
1331 /* Top node clock for the AMBA bus */
1332 &amba_clk,
1333 /* Connected directly to the AMBA bus */
1334 &cpu_clk,
1335 &nandif_clk,
1336 &semi_clk,
1337#ifdef CONFIG_MACH_U300_BS335
1338 &isp_clk,
1339 &cds_clk,
1340#endif
1341 &dma_clk,
1342 &aaif_clk,
1343 &apex_clk,
1344 &video_enc_clk,
1345 &xgam_clk,
1346 &ahb_clk,
1347
1348 /* AHB bridge clocks */
1349 &ahb_subsys_clk,
1350 &intcon_clk,
1351 &mspro_clk,
1352 &emif_clk,
1353 /* FAST bridge clocks */
1354 &fast_clk,
1355 &mmcsd_clk,
1356 &i2s0_clk,
1357 &i2s1_clk,
1358 &i2c0_clk,
1359 &i2c1_clk,
1360 &spi_clk,
1361#ifdef CONFIG_MACH_U300_BS335
1362 &uart1_clk,
1363 &uart1_pclk,
1364#endif
1365 /* SLOW bridge clocks */
1366 &slow_clk,
1367 &wdog_clk,
1368 &uart0_clk,
1369 &uart0_pclk,
1370 &app_timer_clk,
1371 &keypad_clk,
1372 &gpio_clk,
1373 &rtc_clk,
1374 &bustr_clk,
1375 &evhist_clk,
1376 &timer_clk,
1377#ifdef CONFIG_MACH_U300_BS335
1378 &ppm_clk,
1379#endif
1380};
1381
1382static int u300_clocks_show(struct seq_file *s, void *data)
1383{
1384 struct clk *clk;
1385 int i;
1386
1387 seq_printf(s, "CLOCK DEVICE RESET STATE\t" \
1388 "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1389 seq_printf(s, "---------------------------------------------" \
1390 "-----------------------------------------\n");
1391 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1392 clk = clks[i];
1393 if (clk != ERR_PTR(-ENOENT)) {
1394 /* Format clock and device name nicely */
1395 char cdp[33];
1396 int chars;
1397
1398 chars = snprintf(&cdp[0], 17, "%s", clk->name);
1399 while (chars < 16) {
1400 cdp[chars] = ' ';
1401 chars++;
1402 }
1403 chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1404 dev_name(clk->dev) : "N/A");
1405 while (chars < 16) {
1406 cdp[chars+16] = ' ';
1407 chars++;
1408 }
1409 cdp[32] = '\0';
1410 if (clk->get_rate || clk->rate != 0)
1411 seq_printf(s,
1412 "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1413 &cdp[0],
1414 clk->reset ?
1415 "ASSERTED" : "RELEASED",
1416 clk->usecount ? "ON" : "OFF",
1417 clk->usecount,
1418 clk->hw_ctrld ? "YES" : "NO ",
1419 clk_get_rate(clk));
1420 else
1421 seq_printf(s,
1422 "%s%s\t%s\t%d\t%s\t" \
1423 "(unknown rate)\n",
1424 &cdp[0],
1425 clk->reset ?
1426 "ASSERTED" : "RELEASED",
1427 clk->usecount ? "ON" : "OFF",
1428 clk->usecount,
1429 clk->hw_ctrld ? "YES" : "NO ");
1430 }
1431 }
1432 return 0;
1433}
1434
1435static int u300_clocks_open(struct inode *inode, struct file *file)
1436{
1437 return single_open(file, u300_clocks_show, NULL);
1438}
1439
1440static const struct file_operations u300_clocks_operations = {
1441 .open = u300_clocks_open,
1442 .read = seq_read,
1443 .llseek = seq_lseek,
1444 .release = single_release,
1445};
1446
1447static int __init init_clk_read_debugfs(void)
1448{
1449 /* Expose a simple debugfs interface to view all clocks */
1450 (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1451 NULL, NULL,
1452 &u300_clocks_operations);
1453 return 0;
1454}
1455/*
1456 * This needs to come in after the core_initcall() for the
1457 * overall clocks, because debugfs is not available until
1458 * the subsystems come up.
1459 */
1460module_init(init_clk_read_debugfs);
1461#endif
1462
1463int __init u300_clock_init(void)
1464{
1465 u16 val;
1466
1467 /*
1468 * FIXME: shall all this powermanagement stuff really live here???
1469 */
1470
1471 /* Set system to run at PLL208, max performance, a known state. */
1472 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1473 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1474 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1475 /* Wait for the PLL208 to lock if not locked in yet */
1476 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1477 U300_SYSCON_CSR_PLL208_LOCK_IND));
1478
1479 /* Power management enable */
1480 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1481 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1482 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1483
1484 clk_register();
1485
1486 /*
1487 * Some of these may be on when we boot the system so make sure they
1488 * are turned OFF.
1489 */
1490 syscon_block_reset_enable(&timer_clk);
1491 timer_clk.disable(&timer_clk);
1492
1493 /*
1494 * These shall be turned on by default when we boot the system
1495 * so make sure they are ON. (Adding CPU here is a bit too much.)
1496 * These clocks will be claimed by drivers later.
1497 */
1498 syscon_block_reset_disable(&semi_clk);
1499 syscon_block_reset_disable(&emif_clk);
1500 clk_enable(&semi_clk);
1501 clk_enable(&emif_clk);
1502
1503 return 0;
1504}
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
deleted file mode 100644
index 4f50ca8f901e..000000000000
--- a/arch/arm/mach-u300/clock.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-u300/include/mach/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * Copyright (C) 2007-2009 ST-Ericsson AB
8 * Adopted to ST-Ericsson U300 platforms by
9 * Jonas Aaberg <jonas.aberg@stericsson.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#ifndef __MACH_CLOCK_H
18#define __MACH_CLOCK_H
19
20#include <linux/clk.h>
21
22struct clk {
23 struct list_head node;
24 struct module *owner;
25 struct device *dev;
26 const char *name;
27 struct clk *parent;
28
29 spinlock_t lock;
30 unsigned long rate;
31 bool reset;
32 __u16 clk_val;
33 __s8 usecount;
34 void __iomem * res_reg;
35 __u16 res_mask;
36
37 bool hw_ctrld;
38
39 void (*recalc) (struct clk *);
40 int (*set_rate) (struct clk *, unsigned long);
41 unsigned long (*get_rate) (struct clk *);
42 unsigned long (*round_rate) (struct clk *, unsigned long);
43 void (*init) (struct clk *);
44 void (*enable) (struct clk *);
45 void (*disable) (struct clk *);
46};
47
48int u300_clock_init(void);
49
50#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 33339745d432..03acf1883ec7 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -30,6 +30,7 @@
30#include <linux/pinctrl/consumer.h> 30#include <linux/pinctrl/consumer.h>
31#include <linux/pinctrl/pinconf-generic.h> 31#include <linux/pinctrl/pinconf-generic.h>
32#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
33#include <linux/platform_data/clk-u300.h>
33 34
34#include <asm/types.h> 35#include <asm/types.h>
35#include <asm/setup.h> 36#include <asm/setup.h>
@@ -44,7 +45,6 @@
44#include <mach/dma_channels.h> 45#include <mach/dma_channels.h>
45#include <mach/gpio-u300.h> 46#include <mach/gpio-u300.h>
46 47
47#include "clock.h"
48#include "spi.h" 48#include "spi.h"
49#include "i2c.h" 49#include "i2c.h"
50#include "u300-gpio.h" 50#include "u300-gpio.h"
@@ -1658,12 +1658,20 @@ void __init u300_init_irq(void)
1658 int i; 1658 int i;
1659 1659
1660 /* initialize clocking early, we want to clock the INTCON */ 1660 /* initialize clocking early, we want to clock the INTCON */
1661 u300_clock_init(); 1661 u300_clk_init(U300_SYSCON_VBASE);
1662
1663 /* Bootstrap EMIF and SEMI clocks */
1664 clk = clk_get_sys("pl172", NULL);
1665 BUG_ON(IS_ERR(clk));
1666 clk_prepare_enable(clk);
1667 clk = clk_get_sys("semi", NULL);
1668 BUG_ON(IS_ERR(clk));
1669 clk_prepare_enable(clk);
1662 1670
1663 /* Clock the interrupt controller */ 1671 /* Clock the interrupt controller */
1664 clk = clk_get_sys("intcon", NULL); 1672 clk = clk_get_sys("intcon", NULL);
1665 BUG_ON(IS_ERR(clk)); 1673 BUG_ON(IS_ERR(clk));
1666 clk_enable(clk); 1674 clk_prepare_enable(clk);
1667 1675
1668 for (i = 0; i < U300_VIC_IRQS_END; i++) 1676 for (i = 0; i < U300_VIC_IRQS_END; i++)
1669 set_bit(i, (unsigned long *) &mask[0]); 1677 set_bit(i, (unsigned long *) &mask[0]);
@@ -1811,13 +1819,6 @@ void __init u300_init_devices(void)
1811 /* Check what platform we run and print some status information */ 1819 /* Check what platform we run and print some status information */
1812 u300_init_check_chip(); 1820 u300_init_check_chip();
1813 1821
1814 /* Set system to run at PLL208, max performance, a known state. */
1815 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1816 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1817 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1818 /* Wait for the PLL208 to lock if not locked in yet */
1819 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1820 U300_SYSCON_CSR_PLL208_LOCK_IND));
1821 /* Initialize SPI device with some board specifics */ 1822 /* Initialize SPI device with some board specifics */
1822 u300_spi_init(&pl022_device); 1823 u300_spi_init(&pl022_device);
1823 1824
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index bc1c7897e82d..56ac06d38ec1 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -354,7 +354,7 @@ static void __init u300_timer_init(void)
354 /* Clock the interrupt controller */ 354 /* Clock the interrupt controller */
355 clk = clk_get_sys("apptimer", NULL); 355 clk = clk_get_sys("apptimer", NULL);
356 BUG_ON(IS_ERR(clk)); 356 BUG_ON(IS_ERR(clk));
357 clk_enable(clk); 357 clk_prepare_enable(clk);
358 rate = clk_get_rate(clk); 358 rate = clk_get_rate(clk);
359 359
360 setup_sched_clock(u300_read_sched_clock, 32, rate); 360 setup_sched_clock(u300_read_sched_clock, 32, rate);
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4864407e3fc4..3f99b9099658 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -34,4 +34,11 @@ config COMMON_CLK_DEBUG
34 clk_flags, clk_prepare_count, clk_enable_count & 34 clk_flags, clk_prepare_count, clk_enable_count &
35 clk_notifier_count. 35 clk_notifier_count.
36 36
37config COMMON_CLK_WM831X
38 tristate "Clock driver for WM831x/2x PMICs"
39 depends on MFD_WM831X
40 ---help---
41 Supports the clocking subsystem of the WM831x/2x series of
42 PMICs from Wolfson Microlectronics.
43
37endmenu 44endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3669761d1bac..5869ea387054 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,9 +1,15 @@
1 1# common clock types
2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o 2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ 3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
4 clk-mux.o clk-divider.o clk-fixed-factor.o 4 clk-mux.o clk-divider.o clk-fixed-factor.o
5# SoCs specific 5# SoCs specific
6obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 6obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
7obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
7obj-$(CONFIG_ARCH_MXS) += mxs/ 8obj-$(CONFIG_ARCH_MXS) += mxs/
8obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 9obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
9obj-$(CONFIG_PLAT_SPEAR) += spear/ 10obj-$(CONFIG_PLAT_SPEAR) += spear/
11obj-$(CONFIG_ARCH_U300) += clk-u300.o
12obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/
13
14# Chip specific
15obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8ea11b444528..a9204c69148d 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,18 +30,89 @@
30#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 30#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31 31
32#define div_mask(d) ((1 << (d->width)) - 1) 32#define div_mask(d) ((1 << (d->width)) - 1)
33#define is_power_of_two(i) !(i & ~i)
34
35static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
36{
37 unsigned int maxdiv = 0;
38 const struct clk_div_table *clkt;
39
40 for (clkt = table; clkt->div; clkt++)
41 if (clkt->div > maxdiv)
42 maxdiv = clkt->div;
43 return maxdiv;
44}
45
46static unsigned int _get_maxdiv(struct clk_divider *divider)
47{
48 if (divider->flags & CLK_DIVIDER_ONE_BASED)
49 return div_mask(divider);
50 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
51 return 1 << div_mask(divider);
52 if (divider->table)
53 return _get_table_maxdiv(divider->table);
54 return div_mask(divider) + 1;
55}
56
57static unsigned int _get_table_div(const struct clk_div_table *table,
58 unsigned int val)
59{
60 const struct clk_div_table *clkt;
61
62 for (clkt = table; clkt->div; clkt++)
63 if (clkt->val == val)
64 return clkt->div;
65 return 0;
66}
67
68static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
69{
70 if (divider->flags & CLK_DIVIDER_ONE_BASED)
71 return val;
72 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
73 return 1 << val;
74 if (divider->table)
75 return _get_table_div(divider->table, val);
76 return val + 1;
77}
78
79static unsigned int _get_table_val(const struct clk_div_table *table,
80 unsigned int div)
81{
82 const struct clk_div_table *clkt;
83
84 for (clkt = table; clkt->div; clkt++)
85 if (clkt->div == div)
86 return clkt->val;
87 return 0;
88}
89
90static unsigned int _get_val(struct clk_divider *divider, u8 div)
91{
92 if (divider->flags & CLK_DIVIDER_ONE_BASED)
93 return div;
94 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
95 return __ffs(div);
96 if (divider->table)
97 return _get_table_val(divider->table, div);
98 return div - 1;
99}
33 100
34static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 101static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate) 102 unsigned long parent_rate)
36{ 103{
37 struct clk_divider *divider = to_clk_divider(hw); 104 struct clk_divider *divider = to_clk_divider(hw);
38 unsigned int div; 105 unsigned int div, val;
39 106
40 div = readl(divider->reg) >> divider->shift; 107 val = readl(divider->reg) >> divider->shift;
41 div &= div_mask(divider); 108 val &= div_mask(divider);
42 109
43 if (!(divider->flags & CLK_DIVIDER_ONE_BASED)) 110 div = _get_div(divider, val);
44 div++; 111 if (!div) {
112 WARN(1, "%s: Invalid divisor for clock %s\n", __func__,
113 __clk_get_name(hw->clk));
114 return parent_rate;
115 }
45 116
46 return parent_rate / div; 117 return parent_rate / div;
47} 118}
@@ -52,6 +123,26 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
52 */ 123 */
53#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) 124#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
54 125
126static bool _is_valid_table_div(const struct clk_div_table *table,
127 unsigned int div)
128{
129 const struct clk_div_table *clkt;
130
131 for (clkt = table; clkt->div; clkt++)
132 if (clkt->div == div)
133 return true;
134 return false;
135}
136
137static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
138{
139 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
140 return is_power_of_two(div);
141 if (divider->table)
142 return _is_valid_table_div(divider->table, div);
143 return true;
144}
145
55static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 146static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
56 unsigned long *best_parent_rate) 147 unsigned long *best_parent_rate)
57{ 148{
@@ -62,10 +153,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
62 if (!rate) 153 if (!rate)
63 rate = 1; 154 rate = 1;
64 155
65 maxdiv = (1 << divider->width); 156 maxdiv = _get_maxdiv(divider);
66
67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
68 maxdiv--;
69 157
70 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { 158 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
71 parent_rate = *best_parent_rate; 159 parent_rate = *best_parent_rate;
@@ -82,6 +170,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
82 maxdiv = min(ULONG_MAX / rate, maxdiv); 170 maxdiv = min(ULONG_MAX / rate, maxdiv);
83 171
84 for (i = 1; i <= maxdiv; i++) { 172 for (i = 1; i <= maxdiv; i++) {
173 if (!_is_valid_div(divider, i))
174 continue;
85 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 175 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
86 MULT_ROUND_UP(rate, i)); 176 MULT_ROUND_UP(rate, i));
87 now = parent_rate / i; 177 now = parent_rate / i;
@@ -93,9 +183,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
93 } 183 }
94 184
95 if (!bestdiv) { 185 if (!bestdiv) {
96 bestdiv = (1 << divider->width); 186 bestdiv = _get_maxdiv(divider);
97 if (divider->flags & CLK_DIVIDER_ONE_BASED)
98 bestdiv--;
99 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1); 187 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
100 } 188 }
101 189
@@ -115,24 +203,22 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
115 unsigned long parent_rate) 203 unsigned long parent_rate)
116{ 204{
117 struct clk_divider *divider = to_clk_divider(hw); 205 struct clk_divider *divider = to_clk_divider(hw);
118 unsigned int div; 206 unsigned int div, value;
119 unsigned long flags = 0; 207 unsigned long flags = 0;
120 u32 val; 208 u32 val;
121 209
122 div = parent_rate / rate; 210 div = parent_rate / rate;
211 value = _get_val(divider, div);
123 212
124 if (!(divider->flags & CLK_DIVIDER_ONE_BASED)) 213 if (value > div_mask(divider))
125 div--; 214 value = div_mask(divider);
126
127 if (div > div_mask(divider))
128 div = div_mask(divider);
129 215
130 if (divider->lock) 216 if (divider->lock)
131 spin_lock_irqsave(divider->lock, flags); 217 spin_lock_irqsave(divider->lock, flags);
132 218
133 val = readl(divider->reg); 219 val = readl(divider->reg);
134 val &= ~(div_mask(divider) << divider->shift); 220 val &= ~(div_mask(divider) << divider->shift);
135 val |= div << divider->shift; 221 val |= value << divider->shift;
136 writel(val, divider->reg); 222 writel(val, divider->reg);
137 223
138 if (divider->lock) 224 if (divider->lock)
@@ -148,22 +234,11 @@ const struct clk_ops clk_divider_ops = {
148}; 234};
149EXPORT_SYMBOL_GPL(clk_divider_ops); 235EXPORT_SYMBOL_GPL(clk_divider_ops);
150 236
151/** 237static struct clk *_register_divider(struct device *dev, const char *name,
152 * clk_register_divider - register a divider clock with the clock framework
153 * @dev: device registering this clock
154 * @name: name of this clock
155 * @parent_name: name of clock's parent
156 * @flags: framework-specific flags
157 * @reg: register address to adjust divider
158 * @shift: number of bits to shift the bitfield
159 * @width: width of the bitfield
160 * @clk_divider_flags: divider-specific flags for this clock
161 * @lock: shared register lock for this clock
162 */
163struct clk *clk_register_divider(struct device *dev, const char *name,
164 const char *parent_name, unsigned long flags, 238 const char *parent_name, unsigned long flags,
165 void __iomem *reg, u8 shift, u8 width, 239 void __iomem *reg, u8 shift, u8 width,
166 u8 clk_divider_flags, spinlock_t *lock) 240 u8 clk_divider_flags, const struct clk_div_table *table,
241 spinlock_t *lock)
167{ 242{
168 struct clk_divider *div; 243 struct clk_divider *div;
169 struct clk *clk; 244 struct clk *clk;
@@ -178,7 +253,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
178 253
179 init.name = name; 254 init.name = name;
180 init.ops = &clk_divider_ops; 255 init.ops = &clk_divider_ops;
181 init.flags = flags; 256 init.flags = flags | CLK_IS_BASIC;
182 init.parent_names = (parent_name ? &parent_name: NULL); 257 init.parent_names = (parent_name ? &parent_name: NULL);
183 init.num_parents = (parent_name ? 1 : 0); 258 init.num_parents = (parent_name ? 1 : 0);
184 259
@@ -189,6 +264,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
189 div->flags = clk_divider_flags; 264 div->flags = clk_divider_flags;
190 div->lock = lock; 265 div->lock = lock;
191 div->hw.init = &init; 266 div->hw.init = &init;
267 div->table = table;
192 268
193 /* register the clock */ 269 /* register the clock */
194 clk = clk_register(dev, &div->hw); 270 clk = clk_register(dev, &div->hw);
@@ -198,3 +274,48 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
198 274
199 return clk; 275 return clk;
200} 276}
277
278/**
279 * clk_register_divider - register a divider clock with the clock framework
280 * @dev: device registering this clock
281 * @name: name of this clock
282 * @parent_name: name of clock's parent
283 * @flags: framework-specific flags
284 * @reg: register address to adjust divider
285 * @shift: number of bits to shift the bitfield
286 * @width: width of the bitfield
287 * @clk_divider_flags: divider-specific flags for this clock
288 * @lock: shared register lock for this clock
289 */
290struct clk *clk_register_divider(struct device *dev, const char *name,
291 const char *parent_name, unsigned long flags,
292 void __iomem *reg, u8 shift, u8 width,
293 u8 clk_divider_flags, spinlock_t *lock)
294{
295 return _register_divider(dev, name, parent_name, flags, reg, shift,
296 width, clk_divider_flags, NULL, lock);
297}
298
299/**
300 * clk_register_divider_table - register a table based divider clock with
301 * the clock framework
302 * @dev: device registering this clock
303 * @name: name of this clock
304 * @parent_name: name of clock's parent
305 * @flags: framework-specific flags
306 * @reg: register address to adjust divider
307 * @shift: number of bits to shift the bitfield
308 * @width: width of the bitfield
309 * @clk_divider_flags: divider-specific flags for this clock
310 * @table: array of divider/value pairs ending with a div set to 0
311 * @lock: shared register lock for this clock
312 */
313struct clk *clk_register_divider_table(struct device *dev, const char *name,
314 const char *parent_name, unsigned long flags,
315 void __iomem *reg, u8 shift, u8 width,
316 u8 clk_divider_flags, const struct clk_div_table *table,
317 spinlock_t *lock)
318{
319 return _register_divider(dev, name, parent_name, flags, reg, shift,
320 width, clk_divider_flags, table, lock);
321}
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index c8c003e217ad..a4899855c0f6 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -82,7 +82,7 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
82 82
83 init.name = name; 83 init.name = name;
84 init.ops = &clk_fixed_factor_ops; 84 init.ops = &clk_fixed_factor_ops;
85 init.flags = flags; 85 init.flags = flags | CLK_IS_BASIC;
86 init.parent_names = &parent_name; 86 init.parent_names = &parent_name;
87 init.num_parents = 1; 87 init.num_parents = 1;
88 88
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index cbd246229786..f5ec0eebd4d7 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -14,6 +14,7 @@
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/of.h>
17 18
18/* 19/*
19 * DOC: basic fixed-rate clock that cannot gate 20 * DOC: basic fixed-rate clock that cannot gate
@@ -63,7 +64,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
63 64
64 init.name = name; 65 init.name = name;
65 init.ops = &clk_fixed_rate_ops; 66 init.ops = &clk_fixed_rate_ops;
66 init.flags = flags; 67 init.flags = flags | CLK_IS_BASIC;
67 init.parent_names = (parent_name ? &parent_name: NULL); 68 init.parent_names = (parent_name ? &parent_name: NULL);
68 init.num_parents = (parent_name ? 1 : 0); 69 init.num_parents = (parent_name ? 1 : 0);
69 70
@@ -79,3 +80,25 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
79 80
80 return clk; 81 return clk;
81} 82}
83
84#ifdef CONFIG_OF
85/**
86 * of_fixed_clk_setup() - Setup function for simple fixed rate clock
87 */
88void __init of_fixed_clk_setup(struct device_node *node)
89{
90 struct clk *clk;
91 const char *clk_name = node->name;
92 u32 rate;
93
94 if (of_property_read_u32(node, "clock-frequency", &rate))
95 return;
96
97 of_property_read_string(node, "clock-output-names", &clk_name);
98
99 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
100 if (clk)
101 of_clk_add_provider(node, of_clk_src_simple_get, clk);
102}
103EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
104#endif
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 578465e04be6..15114febfd92 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -130,7 +130,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
130 130
131 init.name = name; 131 init.name = name;
132 init.ops = &clk_gate_ops; 132 init.ops = &clk_gate_ops;
133 init.flags = flags; 133 init.flags = flags | CLK_IS_BASIC;
134 init.parent_names = (parent_name ? &parent_name: NULL); 134 init.parent_names = (parent_name ? &parent_name: NULL);
135 init.num_parents = (parent_name ? 1 : 0); 135 init.num_parents = (parent_name ? 1 : 0);
136 136
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
new file mode 100644
index 000000000000..52fecadf004a
--- /dev/null
+++ b/drivers/clk/clk-highbank.c
@@ -0,0 +1,346 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/err.h>
20#include <linux/clk-provider.h>
21#include <linux/io.h>
22#include <linux/of.h>
23
24extern void __iomem *sregs_base;
25
26#define HB_PLL_LOCK_500 0x20000000
27#define HB_PLL_LOCK 0x10000000
28#define HB_PLL_DIVF_SHIFT 20
29#define HB_PLL_DIVF_MASK 0x0ff00000
30#define HB_PLL_DIVQ_SHIFT 16
31#define HB_PLL_DIVQ_MASK 0x00070000
32#define HB_PLL_DIVR_SHIFT 8
33#define HB_PLL_DIVR_MASK 0x00001f00
34#define HB_PLL_RANGE_SHIFT 4
35#define HB_PLL_RANGE_MASK 0x00000070
36#define HB_PLL_BYPASS 0x00000008
37#define HB_PLL_RESET 0x00000004
38#define HB_PLL_EXT_BYPASS 0x00000002
39#define HB_PLL_EXT_ENA 0x00000001
40
41#define HB_PLL_VCO_MIN_FREQ 2133000000
42#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
43#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
44
45#define HB_A9_BCLK_DIV_MASK 0x00000006
46#define HB_A9_BCLK_DIV_SHIFT 1
47#define HB_A9_PCLK_DIV 0x00000001
48
49struct hb_clk {
50 struct clk_hw hw;
51 void __iomem *reg;
52 char *parent_name;
53};
54#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
55
56static int clk_pll_prepare(struct clk_hw *hwclk)
57 {
58 struct hb_clk *hbclk = to_hb_clk(hwclk);
59 u32 reg;
60
61 reg = readl(hbclk->reg);
62 reg &= ~HB_PLL_RESET;
63 writel(reg, hbclk->reg);
64
65 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
66 ;
67 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
68 ;
69
70 return 0;
71}
72
73static void clk_pll_unprepare(struct clk_hw *hwclk)
74{
75 struct hb_clk *hbclk = to_hb_clk(hwclk);
76 u32 reg;
77
78 reg = readl(hbclk->reg);
79 reg |= HB_PLL_RESET;
80 writel(reg, hbclk->reg);
81}
82
83static int clk_pll_enable(struct clk_hw *hwclk)
84{
85 struct hb_clk *hbclk = to_hb_clk(hwclk);
86 u32 reg;
87
88 reg = readl(hbclk->reg);
89 reg |= HB_PLL_EXT_ENA;
90 writel(reg, hbclk->reg);
91
92 return 0;
93}
94
95static void clk_pll_disable(struct clk_hw *hwclk)
96{
97 struct hb_clk *hbclk = to_hb_clk(hwclk);
98 u32 reg;
99
100 reg = readl(hbclk->reg);
101 reg &= ~HB_PLL_EXT_ENA;
102 writel(reg, hbclk->reg);
103}
104
105static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
106 unsigned long parent_rate)
107{
108 struct hb_clk *hbclk = to_hb_clk(hwclk);
109 unsigned long divf, divq, vco_freq, reg;
110
111 reg = readl(hbclk->reg);
112 if (reg & HB_PLL_EXT_BYPASS)
113 return parent_rate;
114
115 divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
116 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
117 vco_freq = parent_rate * (divf + 1);
118
119 return vco_freq / (1 << divq);
120}
121
122static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
123 u32 *pdivq, u32 *pdivf)
124{
125 u32 divq, divf;
126 unsigned long vco_freq;
127
128 if (rate < HB_PLL_MIN_FREQ)
129 rate = HB_PLL_MIN_FREQ;
130 if (rate > HB_PLL_MAX_FREQ)
131 rate = HB_PLL_MAX_FREQ;
132
133 for (divq = 1; divq <= 6; divq++) {
134 if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
135 break;
136 }
137
138 vco_freq = rate * (1 << divq);
139 divf = (vco_freq + (ref_freq / 2)) / ref_freq;
140 divf--;
141
142 *pdivq = divq;
143 *pdivf = divf;
144}
145
146static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
147 unsigned long *parent_rate)
148{
149 u32 divq, divf;
150 unsigned long ref_freq = *parent_rate;
151
152 clk_pll_calc(rate, ref_freq, &divq, &divf);
153
154 return (ref_freq * (divf + 1)) / (1 << divq);
155}
156
157static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
158 unsigned long parent_rate)
159{
160 struct hb_clk *hbclk = to_hb_clk(hwclk);
161 u32 divq, divf;
162 u32 reg;
163
164 clk_pll_calc(rate, parent_rate, &divq, &divf);
165
166 reg = readl(hbclk->reg);
167 if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
168 /* Need to re-lock PLL, so put it into bypass mode */
169 reg |= HB_PLL_EXT_BYPASS;
170 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
171
172 writel(reg | HB_PLL_RESET, hbclk->reg);
173 reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
174 reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
175 writel(reg | HB_PLL_RESET, hbclk->reg);
176 writel(reg, hbclk->reg);
177
178 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
179 ;
180 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
181 ;
182 reg |= HB_PLL_EXT_ENA;
183 reg &= ~HB_PLL_EXT_BYPASS;
184 } else {
185 reg &= ~HB_PLL_DIVQ_MASK;
186 reg |= divq << HB_PLL_DIVQ_SHIFT;
187 }
188 writel(reg, hbclk->reg);
189
190 return 0;
191}
192
193static const struct clk_ops clk_pll_ops = {
194 .prepare = clk_pll_prepare,
195 .unprepare = clk_pll_unprepare,
196 .enable = clk_pll_enable,
197 .disable = clk_pll_disable,
198 .recalc_rate = clk_pll_recalc_rate,
199 .round_rate = clk_pll_round_rate,
200 .set_rate = clk_pll_set_rate,
201};
202
203static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
204 unsigned long parent_rate)
205{
206 struct hb_clk *hbclk = to_hb_clk(hwclk);
207 u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
208 return parent_rate / div;
209}
210
211static const struct clk_ops a9periphclk_ops = {
212 .recalc_rate = clk_cpu_periphclk_recalc_rate,
213};
214
215static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
216 unsigned long parent_rate)
217{
218 struct hb_clk *hbclk = to_hb_clk(hwclk);
219 u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
220
221 return parent_rate / (div + 2);
222}
223
224static const struct clk_ops a9bclk_ops = {
225 .recalc_rate = clk_cpu_a9bclk_recalc_rate,
226};
227
228static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
229 unsigned long parent_rate)
230{
231 struct hb_clk *hbclk = to_hb_clk(hwclk);
232 u32 div;
233
234 div = readl(hbclk->reg) & 0x1f;
235 div++;
236 div *= 2;
237
238 return parent_rate / div;
239}
240
241static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
242 unsigned long *parent_rate)
243{
244 u32 div;
245
246 div = *parent_rate / rate;
247 div++;
248 div &= ~0x1;
249
250 return *parent_rate / div;
251}
252
253static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
254 unsigned long parent_rate)
255{
256 struct hb_clk *hbclk = to_hb_clk(hwclk);
257 u32 div;
258
259 div = parent_rate / rate;
260 if (div & 0x1)
261 return -EINVAL;
262
263 writel(div >> 1, hbclk->reg);
264 return 0;
265}
266
267static const struct clk_ops periclk_ops = {
268 .recalc_rate = clk_periclk_recalc_rate,
269 .round_rate = clk_periclk_round_rate,
270 .set_rate = clk_periclk_set_rate,
271};
272
273static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
274{
275 u32 reg;
276 struct clk *clk;
277 struct hb_clk *hb_clk;
278 const char *clk_name = node->name;
279 const char *parent_name;
280 struct clk_init_data init;
281 int rc;
282
283 rc = of_property_read_u32(node, "reg", &reg);
284 if (WARN_ON(rc))
285 return NULL;
286
287 hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
288 if (WARN_ON(!hb_clk))
289 return NULL;
290
291 hb_clk->reg = sregs_base + reg;
292
293 of_property_read_string(node, "clock-output-names", &clk_name);
294
295 init.name = clk_name;
296 init.ops = ops;
297 init.flags = 0;
298 parent_name = of_clk_get_parent_name(node, 0);
299 init.parent_names = &parent_name;
300 init.num_parents = 1;
301
302 hb_clk->hw.init = &init;
303
304 clk = clk_register(NULL, &hb_clk->hw);
305 if (WARN_ON(IS_ERR(clk))) {
306 kfree(hb_clk);
307 return NULL;
308 }
309 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
310 return clk;
311}
312
313static void __init hb_pll_init(struct device_node *node)
314{
315 hb_clk_init(node, &clk_pll_ops);
316}
317
318static void __init hb_a9periph_init(struct device_node *node)
319{
320 hb_clk_init(node, &a9periphclk_ops);
321}
322
323static void __init hb_a9bus_init(struct device_node *node)
324{
325 struct clk *clk = hb_clk_init(node, &a9bclk_ops);
326 clk_prepare_enable(clk);
327}
328
329static void __init hb_emmc_init(struct device_node *node)
330{
331 hb_clk_init(node, &periclk_ops);
332}
333
334static const __initconst struct of_device_id clk_match[] = {
335 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
336 { .compatible = "calxeda,hb-pll-clock", .data = hb_pll_init, },
337 { .compatible = "calxeda,hb-a9periph-clock", .data = hb_a9periph_init, },
338 { .compatible = "calxeda,hb-a9bus-clock", .data = hb_a9bus_init, },
339 { .compatible = "calxeda,hb-emmc-clock", .data = hb_emmc_init, },
340 {}
341};
342
343void __init highbank_clocks_init(void)
344{
345 of_clk_init(clk_match);
346}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index fd36a8ea73d9..508c032edce4 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -106,7 +106,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
106 106
107 init.name = name; 107 init.name = name;
108 init.ops = &clk_mux_ops; 108 init.ops = &clk_mux_ops;
109 init.flags = flags; 109 init.flags = flags | CLK_IS_BASIC;
110 init.parent_names = parent_names; 110 init.parent_names = parent_names;
111 init.num_parents = num_parents; 111 init.num_parents = num_parents;
112 112
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
new file mode 100644
index 000000000000..a15f7928fb11
--- /dev/null
+++ b/drivers/clk/clk-u300.c
@@ -0,0 +1,746 @@
1/*
2 * U300 clock implementation
3 * Copyright (C) 2007-2012 ST-Ericsson AB
4 * License terms: GNU General Public License (GPL) version 2
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7 */
8#include <linux/clk.h>
9#include <linux/clkdev.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/clk-provider.h>
13#include <linux/spinlock.h>
14#include <mach/syscon.h>
15
16/*
17 * The clocking hierarchy currently looks like this.
18 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
19 * The ideas is to show dependencies, so a clock higher up in the
20 * hierarchy has to be on in order for another clock to be on. Now,
21 * both CPU and DMA can actually be on top of the hierarchy, and that
22 * is not modeled currently. Instead we have the backbone AMBA bus on
23 * top. This bus cannot be programmed in any way but conceptually it
24 * needs to be active for the bridges and devices to transport data.
25 *
26 * Please be aware that a few clocks are hw controlled, which mean that
27 * the hw itself can turn on/off or change the rate of the clock when
28 * needed!
29 *
30 * AMBA bus
31 * |
32 * +- CPU
33 * +- FSMC NANDIF NAND Flash interface
34 * +- SEMI Shared Memory interface
35 * +- ISP Image Signal Processor (U335 only)
36 * +- CDS (U335 only)
37 * +- DMA Direct Memory Access Controller
38 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
39 * +- APEX
40 * +- VIDEO_ENC AVE2/3 Video Encoder
41 * +- XGAM Graphics Accelerator Controller
42 * +- AHB
43 * |
44 * +- ahb:0 AHB Bridge
45 * | |
46 * | +- ahb:1 INTCON Interrupt controller
47 * | +- ahb:3 MSPRO Memory Stick Pro controller
48 * | +- ahb:4 EMIF External Memory interface
49 * |
50 * +- fast:0 FAST bridge
51 * | |
52 * | +- fast:1 MMCSD MMC/SD card reader controller
53 * | +- fast:2 I2S0 PCM I2S channel 0 controller
54 * | +- fast:3 I2S1 PCM I2S channel 1 controller
55 * | +- fast:4 I2C0 I2C channel 0 controller
56 * | +- fast:5 I2C1 I2C channel 1 controller
57 * | +- fast:6 SPI SPI controller
58 * | +- fast:7 UART1 Secondary UART (U335 only)
59 * |
60 * +- slow:0 SLOW bridge
61 * |
62 * +- slow:1 SYSCON (not possible to control)
63 * +- slow:2 WDOG Watchdog
64 * +- slow:3 UART0 primary UART
65 * +- slow:4 TIMER_APP Application timer - used in Linux
66 * +- slow:5 KEYPAD controller
67 * +- slow:6 GPIO controller
68 * +- slow:7 RTC controller
69 * +- slow:8 BT Bus Tracer (not used currently)
70 * +- slow:9 EH Event Handler (not used currently)
71 * +- slow:a TIMER_ACC Access style timer (not used currently)
72 * +- slow:b PPM (U335 only, what is that?)
73 */
74
75/* Global syscon virtual base */
76static void __iomem *syscon_vbase;
77
78/**
79 * struct clk_syscon - U300 syscon clock
80 * @hw: corresponding clock hardware entry
81 * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
82 * and does not need any magic pokes to be enabled/disabled
83 * @reset: state holder, whether this block's reset line is asserted or not
84 * @res_reg: reset line enable/disable flag register
85 * @res_bit: bit for resetting or taking this consumer out of reset
86 * @en_reg: clock line enable/disable flag register
87 * @en_bit: bit for enabling/disabling this consumer clock line
88 * @clk_val: magic value to poke in the register to enable/disable
89 * this one clock
90 */
91struct clk_syscon {
92 struct clk_hw hw;
93 bool hw_ctrld;
94 bool reset;
95 void __iomem *res_reg;
96 u8 res_bit;
97 void __iomem *en_reg;
98 u8 en_bit;
99 u16 clk_val;
100};
101
102#define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
103
104static DEFINE_SPINLOCK(syscon_resetreg_lock);
105
106/*
107 * Reset control functions. We remember if a block has been
108 * taken out of reset and don't remove the reset assertion again
109 * and vice versa. Currently we only remove resets so the
110 * enablement function is defined out.
111 */
112static void syscon_block_reset_enable(struct clk_syscon *sclk)
113{
114 unsigned long iflags;
115 u16 val;
116
117 /* Not all blocks support resetting */
118 if (!sclk->res_reg)
119 return;
120 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
121 val = readw(sclk->res_reg);
122 val |= BIT(sclk->res_bit);
123 writew(val, sclk->res_reg);
124 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
125 sclk->reset = true;
126}
127
128static void syscon_block_reset_disable(struct clk_syscon *sclk)
129{
130 unsigned long iflags;
131 u16 val;
132
133 /* Not all blocks support resetting */
134 if (!sclk->res_reg)
135 return;
136 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
137 val = readw(sclk->res_reg);
138 val &= ~BIT(sclk->res_bit);
139 writew(val, sclk->res_reg);
140 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
141 sclk->reset = false;
142}
143
144static int syscon_clk_prepare(struct clk_hw *hw)
145{
146 struct clk_syscon *sclk = to_syscon(hw);
147
148 /* If the block is in reset, bring it out */
149 if (sclk->reset)
150 syscon_block_reset_disable(sclk);
151 return 0;
152}
153
154static void syscon_clk_unprepare(struct clk_hw *hw)
155{
156 struct clk_syscon *sclk = to_syscon(hw);
157
158 /* Please don't force the console into reset */
159 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
160 return;
161 /* When unpreparing, force block into reset */
162 if (!sclk->reset)
163 syscon_block_reset_enable(sclk);
164}
165
166static int syscon_clk_enable(struct clk_hw *hw)
167{
168 struct clk_syscon *sclk = to_syscon(hw);
169
170 /* Don't touch the hardware controlled clocks */
171 if (sclk->hw_ctrld)
172 return 0;
173 /* These cannot be controlled */
174 if (sclk->clk_val == 0xFFFFU)
175 return 0;
176
177 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
178 return 0;
179}
180
181static void syscon_clk_disable(struct clk_hw *hw)
182{
183 struct clk_syscon *sclk = to_syscon(hw);
184
185 /* Don't touch the hardware controlled clocks */
186 if (sclk->hw_ctrld)
187 return;
188 if (sclk->clk_val == 0xFFFFU)
189 return;
190 /* Please don't disable the console port */
191 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
192 return;
193
194 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
195}
196
197static int syscon_clk_is_enabled(struct clk_hw *hw)
198{
199 struct clk_syscon *sclk = to_syscon(hw);
200 u16 val;
201
202 /* If no enable register defined, it's always-on */
203 if (!sclk->en_reg)
204 return 1;
205
206 val = readw(sclk->en_reg);
207 val &= BIT(sclk->en_bit);
208
209 return val ? 1 : 0;
210}
211
212static u16 syscon_get_perf(void)
213{
214 u16 val;
215
216 val = readw(syscon_vbase + U300_SYSCON_CCR);
217 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
218 return val;
219}
220
221static unsigned long
222syscon_clk_recalc_rate(struct clk_hw *hw,
223 unsigned long parent_rate)
224{
225 struct clk_syscon *sclk = to_syscon(hw);
226 u16 perf = syscon_get_perf();
227
228 switch(sclk->clk_val) {
229 case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
230 case U300_SYSCON_SBCER_I2C0_CLK_EN:
231 case U300_SYSCON_SBCER_I2C1_CLK_EN:
232 case U300_SYSCON_SBCER_MMC_CLK_EN:
233 case U300_SYSCON_SBCER_SPI_CLK_EN:
234 /* The FAST clocks have one progression */
235 switch(perf) {
236 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
237 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
238 return 13000000;
239 default:
240 return parent_rate; /* 26 MHz */
241 }
242 case U300_SYSCON_SBCER_DMAC_CLK_EN:
243 case U300_SYSCON_SBCER_NANDIF_CLK_EN:
244 case U300_SYSCON_SBCER_XGAM_CLK_EN:
245 /* AMBA interconnect peripherals */
246 switch(perf) {
247 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
248 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
249 return 6500000;
250 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
251 return 26000000;
252 default:
253 return parent_rate; /* 52 MHz */
254 }
255 case U300_SYSCON_SBCER_SEMI_CLK_EN:
256 case U300_SYSCON_SBCER_EMIF_CLK_EN:
257 /* EMIF speeds */
258 switch(perf) {
259 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
260 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
261 return 13000000;
262 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
263 return 52000000;
264 default:
265 return 104000000;
266 }
267 case U300_SYSCON_SBCER_CPU_CLK_EN:
268 /* And the fast CPU clock */
269 switch(perf) {
270 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
271 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
272 return 13000000;
273 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
274 return 52000000;
275 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
276 return 104000000;
277 default:
278 return parent_rate; /* 208 MHz */
279 }
280 default:
281 /*
282 * The SLOW clocks and default just inherit the rate of
283 * their parent (typically PLL13 13 MHz).
284 */
285 return parent_rate;
286 }
287}
288
289static long
290syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
291 unsigned long *prate)
292{
293 struct clk_syscon *sclk = to_syscon(hw);
294
295 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
296 return *prate;
297 /* We really only support setting the rate of the CPU clock */
298 if (rate <= 13000000)
299 return 13000000;
300 if (rate <= 52000000)
301 return 52000000;
302 if (rate <= 104000000)
303 return 104000000;
304 return 208000000;
305}
306
307static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long parent_rate)
309{
310 struct clk_syscon *sclk = to_syscon(hw);
311 u16 val;
312
313 /* We only support setting the rate of the CPU clock */
314 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
315 return -EINVAL;
316 switch (rate) {
317 case 13000000:
318 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
319 break;
320 case 52000000:
321 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
322 break;
323 case 104000000:
324 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
325 break;
326 case 208000000:
327 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
328 break;
329 default:
330 return -EINVAL;
331 }
332 val |= readw(syscon_vbase + U300_SYSCON_CCR) &
333 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
334 writew(val, syscon_vbase + U300_SYSCON_CCR);
335 return 0;
336}
337
338static const struct clk_ops syscon_clk_ops = {
339 .prepare = syscon_clk_prepare,
340 .unprepare = syscon_clk_unprepare,
341 .enable = syscon_clk_enable,
342 .disable = syscon_clk_disable,
343 .is_enabled = syscon_clk_is_enabled,
344 .recalc_rate = syscon_clk_recalc_rate,
345 .round_rate = syscon_clk_round_rate,
346 .set_rate = syscon_clk_set_rate,
347};
348
349static struct clk * __init
350syscon_clk_register(struct device *dev, const char *name,
351 const char *parent_name, unsigned long flags,
352 bool hw_ctrld,
353 void __iomem *res_reg, u8 res_bit,
354 void __iomem *en_reg, u8 en_bit,
355 u16 clk_val)
356{
357 struct clk *clk;
358 struct clk_syscon *sclk;
359 struct clk_init_data init;
360
361 sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
362 if (!sclk) {
363 pr_err("could not allocate syscon clock %s\n",
364 name);
365 return ERR_PTR(-ENOMEM);
366 }
367 init.name = name;
368 init.ops = &syscon_clk_ops;
369 init.flags = flags;
370 init.parent_names = (parent_name ? &parent_name : NULL);
371 init.num_parents = (parent_name ? 1 : 0);
372 sclk->hw.init = &init;
373 sclk->hw_ctrld = hw_ctrld;
374 /* Assume the block is in reset at registration */
375 sclk->reset = true;
376 sclk->res_reg = res_reg;
377 sclk->res_bit = res_bit;
378 sclk->en_reg = en_reg;
379 sclk->en_bit = en_bit;
380 sclk->clk_val = clk_val;
381
382 clk = clk_register(dev, &sclk->hw);
383 if (IS_ERR(clk))
384 kfree(sclk);
385
386 return clk;
387}
388
389/**
390 * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
391 * @hw: corresponding clock hardware entry
392 * @is_mspro: if this is the memory stick clock rather than MMC/SD
393 */
394struct clk_mclk {
395 struct clk_hw hw;
396 bool is_mspro;
397};
398
399#define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
400
401static int mclk_clk_prepare(struct clk_hw *hw)
402{
403 struct clk_mclk *mclk = to_mclk(hw);
404 u16 val;
405
406 /* The MMC and MSPRO clocks need some special set-up */
407 if (!mclk->is_mspro) {
408 /* Set default MMC clock divisor to 18.9 MHz */
409 writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
410 val = readw(syscon_vbase + U300_SYSCON_MMCR);
411 /* Disable the MMC feedback clock */
412 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
413 /* Disable MSPRO frequency */
414 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
415 writew(val, syscon_vbase + U300_SYSCON_MMCR);
416 } else {
417 val = readw(syscon_vbase + U300_SYSCON_MMCR);
418 /* Disable the MMC feedback clock */
419 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
420 /* Enable MSPRO frequency */
421 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
422 writew(val, syscon_vbase + U300_SYSCON_MMCR);
423 }
424
425 return 0;
426}
427
428static unsigned long
429mclk_clk_recalc_rate(struct clk_hw *hw,
430 unsigned long parent_rate)
431{
432 u16 perf = syscon_get_perf();
433
434 switch (perf) {
435 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
436 /*
437 * Here, the 208 MHz PLL gets shut down and the always
438 * on 13 MHz PLL used for RTC etc kicks into use
439 * instead.
440 */
441 return 13000000;
442 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
444 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
445 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
446 {
447 /*
448 * This clock is under program control. The register is
449 * divided in two nybbles, bit 7-4 gives cycles-1 to count
450 * high, bit 3-0 gives cycles-1 to count low. Distribute
451 * these with no more than 1 cycle difference between
452 * low and high and add low and high to get the actual
453 * divisor. The base PLL is 208 MHz. Writing 0x00 will
454 * divide by 1 and 1 so the highest frequency possible
455 * is 104 MHz.
456 *
457 * e.g. 0x54 =>
458 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
459 */
460 u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
461 U300_SYSCON_MMF0R_MASK;
462 switch (val) {
463 case 0x0054:
464 return 18900000;
465 case 0x0044:
466 return 20800000;
467 case 0x0043:
468 return 23100000;
469 case 0x0033:
470 return 26000000;
471 case 0x0032:
472 return 29700000;
473 case 0x0022:
474 return 34700000;
475 case 0x0021:
476 return 41600000;
477 case 0x0011:
478 return 52000000;
479 case 0x0000:
480 return 104000000;
481 default:
482 break;
483 }
484 }
485 default:
486 break;
487 }
488 return parent_rate;
489}
490
491static long
492mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
493 unsigned long *prate)
494{
495 if (rate <= 18900000)
496 return 18900000;
497 if (rate <= 20800000)
498 return 20800000;
499 if (rate <= 23100000)
500 return 23100000;
501 if (rate <= 26000000)
502 return 26000000;
503 if (rate <= 29700000)
504 return 29700000;
505 if (rate <= 34700000)
506 return 34700000;
507 if (rate <= 41600000)
508 return 41600000;
509 /* Highest rate */
510 return 52000000;
511}
512
513static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
514 unsigned long parent_rate)
515{
516 u16 val;
517 u16 reg;
518
519 switch (rate) {
520 case 18900000:
521 val = 0x0054;
522 break;
523 case 20800000:
524 val = 0x0044;
525 break;
526 case 23100000:
527 val = 0x0043;
528 break;
529 case 26000000:
530 val = 0x0033;
531 break;
532 case 29700000:
533 val = 0x0032;
534 break;
535 case 34700000:
536 val = 0x0022;
537 break;
538 case 41600000:
539 val = 0x0021;
540 break;
541 case 52000000:
542 val = 0x0011;
543 break;
544 case 104000000:
545 val = 0x0000;
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
552 ~U300_SYSCON_MMF0R_MASK;
553 writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
554 return 0;
555}
556
557static const struct clk_ops mclk_ops = {
558 .prepare = mclk_clk_prepare,
559 .recalc_rate = mclk_clk_recalc_rate,
560 .round_rate = mclk_clk_round_rate,
561 .set_rate = mclk_clk_set_rate,
562};
563
564static struct clk * __init
565mclk_clk_register(struct device *dev, const char *name,
566 const char *parent_name, bool is_mspro)
567{
568 struct clk *clk;
569 struct clk_mclk *mclk;
570 struct clk_init_data init;
571
572 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
573 if (!mclk) {
574 pr_err("could not allocate MMC/SD clock %s\n",
575 name);
576 return ERR_PTR(-ENOMEM);
577 }
578 init.name = "mclk";
579 init.ops = &mclk_ops;
580 init.flags = 0;
581 init.parent_names = (parent_name ? &parent_name : NULL);
582 init.num_parents = (parent_name ? 1 : 0);
583 mclk->hw.init = &init;
584 mclk->is_mspro = is_mspro;
585
586 clk = clk_register(dev, &mclk->hw);
587 if (IS_ERR(clk))
588 kfree(mclk);
589
590 return clk;
591}
592
593void __init u300_clk_init(void __iomem *base)
594{
595 u16 val;
596 struct clk *clk;
597
598 syscon_vbase = base;
599
600 /* Set system to run at PLL208, max performance, a known state. */
601 val = readw(syscon_vbase + U300_SYSCON_CCR);
602 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
603 writew(val, syscon_vbase + U300_SYSCON_CCR);
604 /* Wait for the PLL208 to lock if not locked in yet */
605 while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
606 U300_SYSCON_CSR_PLL208_LOCK_IND));
607
608 /* Power management enable */
609 val = readw(syscon_vbase + U300_SYSCON_PMCR);
610 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
611 writew(val, syscon_vbase + U300_SYSCON_PMCR);
612
613 /* These are always available (RTC and PLL13) */
614 clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
615 CLK_IS_ROOT, 32768);
616 /* The watchdog sits directly on the 32 kHz clock */
617 clk_register_clkdev(clk, NULL, "coh901327_wdog");
618 clk = clk_register_fixed_rate(NULL, "pll13", NULL,
619 CLK_IS_ROOT, 13000000);
620
621 /* These derive from PLL208 */
622 clk = clk_register_fixed_rate(NULL, "pll208", NULL,
623 CLK_IS_ROOT, 208000000);
624 clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
625 0, 1, 1);
626 clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
627 0, 1, 2);
628 clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
629 0, 1, 4);
630 /* The 52 MHz is divided down to 26 MHz */
631 clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
632 0, 1, 2);
633
634 /* Directly on the AMBA interconnect */
635 clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
636 syscon_vbase + U300_SYSCON_RRR, 3,
637 syscon_vbase + U300_SYSCON_CERR, 3,
638 U300_SYSCON_SBCER_CPU_CLK_EN);
639 clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
640 syscon_vbase + U300_SYSCON_RRR, 4,
641 syscon_vbase + U300_SYSCON_CERR, 4,
642 U300_SYSCON_SBCER_DMAC_CLK_EN);
643 clk_register_clkdev(clk, NULL, "dma");
644 clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
645 syscon_vbase + U300_SYSCON_RRR, 6,
646 syscon_vbase + U300_SYSCON_CERR, 6,
647 U300_SYSCON_SBCER_NANDIF_CLK_EN);
648 clk_register_clkdev(clk, NULL, "fsmc-nand");
649 clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
650 syscon_vbase + U300_SYSCON_RRR, 8,
651 syscon_vbase + U300_SYSCON_CERR, 8,
652 U300_SYSCON_SBCER_XGAM_CLK_EN);
653 clk_register_clkdev(clk, NULL, "xgam");
654 clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
655 syscon_vbase + U300_SYSCON_RRR, 9,
656 syscon_vbase + U300_SYSCON_CERR, 9,
657 U300_SYSCON_SBCER_SEMI_CLK_EN);
658 clk_register_clkdev(clk, NULL, "semi");
659
660 /* AHB bridge clocks */
661 clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
662 syscon_vbase + U300_SYSCON_RRR, 10,
663 syscon_vbase + U300_SYSCON_CERR, 10,
664 U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
665 clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
666 syscon_vbase + U300_SYSCON_RRR, 12,
667 syscon_vbase + U300_SYSCON_CERR, 12,
668 /* Cannot be enabled, just taken out of reset */
669 0xFFFFU);
670 clk_register_clkdev(clk, NULL, "intcon");
671 clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
672 syscon_vbase + U300_SYSCON_RRR, 5,
673 syscon_vbase + U300_SYSCON_CERR, 5,
674 U300_SYSCON_SBCER_EMIF_CLK_EN);
675 clk_register_clkdev(clk, NULL, "pl172");
676
677 /* FAST bridge clocks */
678 clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
679 syscon_vbase + U300_SYSCON_RFR, 0,
680 syscon_vbase + U300_SYSCON_CEFR, 0,
681 U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
682 clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
683 syscon_vbase + U300_SYSCON_RFR, 1,
684 syscon_vbase + U300_SYSCON_CEFR, 1,
685 U300_SYSCON_SBCER_I2C0_CLK_EN);
686 clk_register_clkdev(clk, NULL, "stu300.0");
687 clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
688 syscon_vbase + U300_SYSCON_RFR, 2,
689 syscon_vbase + U300_SYSCON_CEFR, 2,
690 U300_SYSCON_SBCER_I2C1_CLK_EN);
691 clk_register_clkdev(clk, NULL, "stu300.1");
692 clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
693 syscon_vbase + U300_SYSCON_RFR, 5,
694 syscon_vbase + U300_SYSCON_CEFR, 5,
695 U300_SYSCON_SBCER_MMC_CLK_EN);
696 clk_register_clkdev(clk, "apb_pclk", "mmci");
697 clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
698 syscon_vbase + U300_SYSCON_RFR, 6,
699 syscon_vbase + U300_SYSCON_CEFR, 6,
700 U300_SYSCON_SBCER_SPI_CLK_EN);
701 /* The SPI has no external clock for the outward bus, uses the pclk */
702 clk_register_clkdev(clk, NULL, "pl022");
703 clk_register_clkdev(clk, "apb_pclk", "pl022");
704
705 /* SLOW bridge clocks */
706 clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
707 syscon_vbase + U300_SYSCON_RSR, 0,
708 syscon_vbase + U300_SYSCON_CESR, 0,
709 U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
710 clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
711 syscon_vbase + U300_SYSCON_RSR, 1,
712 syscon_vbase + U300_SYSCON_CESR, 1,
713 U300_SYSCON_SBCER_UART_CLK_EN);
714 /* Same clock is used for APB and outward bus */
715 clk_register_clkdev(clk, NULL, "uart0");
716 clk_register_clkdev(clk, "apb_pclk", "uart0");
717 clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
718 syscon_vbase + U300_SYSCON_RSR, 4,
719 syscon_vbase + U300_SYSCON_CESR, 4,
720 U300_SYSCON_SBCER_GPIO_CLK_EN);
721 clk_register_clkdev(clk, NULL, "u300-gpio");
722 clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
723 syscon_vbase + U300_SYSCON_RSR, 5,
724 syscon_vbase + U300_SYSCON_CESR, 6,
725 U300_SYSCON_SBCER_KEYPAD_CLK_EN);
726 clk_register_clkdev(clk, NULL, "coh901461-keypad");
727 clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
728 syscon_vbase + U300_SYSCON_RSR, 6,
729 /* No clock enable register bit */
730 NULL, 0, 0xFFFFU);
731 clk_register_clkdev(clk, NULL, "rtc-coh901331");
732 clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
733 syscon_vbase + U300_SYSCON_RSR, 7,
734 syscon_vbase + U300_SYSCON_CESR, 7,
735 U300_SYSCON_SBCER_APP_TMR_CLK_EN);
736 clk_register_clkdev(clk, NULL, "apptimer");
737 clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
738 syscon_vbase + U300_SYSCON_RSR, 8,
739 syscon_vbase + U300_SYSCON_CESR, 8,
740 U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
741 clk_register_clkdev(clk, NULL, "timer");
742
743 /* Then this special MMC/SD clock */
744 clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
745 clk_register_clkdev(clk, NULL, "mmci");
746}
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
new file mode 100644
index 000000000000..e7b7765e85f3
--- /dev/null
+++ b/drivers/clk/clk-wm831x.c
@@ -0,0 +1,428 @@
1/*
2 * WM831x clock control
3 *
4 * Copyright 2011-2 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/delay.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/platform_device.h>
21#include <linux/mfd/wm831x/core.h>
22
23struct wm831x_clk {
24 struct wm831x *wm831x;
25 struct clk_hw xtal_hw;
26 struct clk_hw fll_hw;
27 struct clk_hw clkout_hw;
28 struct clk *xtal;
29 struct clk *fll;
30 struct clk *clkout;
31 bool xtal_ena;
32};
33
34static int wm831x_xtal_is_enabled(struct clk_hw *hw)
35{
36 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
37 xtal_hw);
38
39 return clkdata->xtal_ena;
40}
41
42static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
43 unsigned long parent_rate)
44{
45 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
46 xtal_hw);
47
48 if (clkdata->xtal_ena)
49 return 32768;
50 else
51 return 0;
52}
53
54static const struct clk_ops wm831x_xtal_ops = {
55 .is_enabled = wm831x_xtal_is_enabled,
56 .recalc_rate = wm831x_xtal_recalc_rate,
57};
58
59static struct clk_init_data wm831x_xtal_init = {
60 .name = "xtal",
61 .ops = &wm831x_xtal_ops,
62 .flags = CLK_IS_ROOT,
63};
64
65static const unsigned long wm831x_fll_auto_rates[] = {
66 2048000,
67 11289600,
68 12000000,
69 12288000,
70 19200000,
71 22579600,
72 24000000,
73 24576000,
74};
75
76static int wm831x_fll_is_enabled(struct clk_hw *hw)
77{
78 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
79 fll_hw);
80 struct wm831x *wm831x = clkdata->wm831x;
81 int ret;
82
83 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
84 if (ret < 0) {
85 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
86 ret);
87 return true;
88 }
89
90 return (ret & WM831X_FLL_ENA) != 0;
91}
92
93static int wm831x_fll_prepare(struct clk_hw *hw)
94{
95 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
96 fll_hw);
97 struct wm831x *wm831x = clkdata->wm831x;
98 int ret;
99
100 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
101 WM831X_FLL_ENA, WM831X_FLL_ENA);
102 if (ret != 0)
103 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
104
105 usleep_range(2000, 2000);
106
107 return ret;
108}
109
110static void wm831x_fll_unprepare(struct clk_hw *hw)
111{
112 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
113 fll_hw);
114 struct wm831x *wm831x = clkdata->wm831x;
115 int ret;
116
117 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
118 if (ret != 0)
119 dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
120}
121
122static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
123 unsigned long parent_rate)
124{
125 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
126 fll_hw);
127 struct wm831x *wm831x = clkdata->wm831x;
128 int ret;
129
130 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
131 if (ret < 0) {
132 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
133 ret);
134 return 0;
135 }
136
137 if (ret & WM831X_FLL_AUTO)
138 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
139
140 dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
141
142 return 0;
143}
144
145static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
146 unsigned long *unused)
147{
148 int best = 0;
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
152 if (abs(wm831x_fll_auto_rates[i] - rate) <
153 abs(wm831x_fll_auto_rates[best] - rate))
154 best = i;
155
156 return wm831x_fll_auto_rates[best];
157}
158
159static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
161{
162 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
163 fll_hw);
164 struct wm831x *wm831x = clkdata->wm831x;
165 int i;
166
167 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
168 if (wm831x_fll_auto_rates[i] == rate)
169 break;
170 if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
171 return -EINVAL;
172
173 if (wm831x_fll_is_enabled(hw))
174 return -EPERM;
175
176 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
177 WM831X_FLL_AUTO_FREQ_MASK, i);
178}
179
180static const char *wm831x_fll_parents[] = {
181 "xtal",
182 "clkin",
183};
184
185static u8 wm831x_fll_get_parent(struct clk_hw *hw)
186{
187 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
188 fll_hw);
189 struct wm831x *wm831x = clkdata->wm831x;
190 int ret;
191
192 /* AUTO mode is always clocked from the crystal */
193 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
194 if (ret < 0) {
195 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
196 ret);
197 return 0;
198 }
199
200 if (ret & WM831X_FLL_AUTO)
201 return 0;
202
203 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
204 if (ret < 0) {
205 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
206 ret);
207 return 0;
208 }
209
210 switch (ret & WM831X_FLL_CLK_SRC_MASK) {
211 case 0:
212 return 0;
213 case 1:
214 return 1;
215 default:
216 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
217 ret & WM831X_FLL_CLK_SRC_MASK);
218 return 0;
219 }
220}
221
222static const struct clk_ops wm831x_fll_ops = {
223 .is_enabled = wm831x_fll_is_enabled,
224 .prepare = wm831x_fll_prepare,
225 .unprepare = wm831x_fll_unprepare,
226 .round_rate = wm831x_fll_round_rate,
227 .recalc_rate = wm831x_fll_recalc_rate,
228 .set_rate = wm831x_fll_set_rate,
229 .get_parent = wm831x_fll_get_parent,
230};
231
232static struct clk_init_data wm831x_fll_init = {
233 .name = "fll",
234 .ops = &wm831x_fll_ops,
235 .parent_names = wm831x_fll_parents,
236 .num_parents = ARRAY_SIZE(wm831x_fll_parents),
237 .flags = CLK_SET_RATE_GATE,
238};
239
240static int wm831x_clkout_is_enabled(struct clk_hw *hw)
241{
242 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
243 clkout_hw);
244 struct wm831x *wm831x = clkdata->wm831x;
245 int ret;
246
247 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
248 if (ret < 0) {
249 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
250 ret);
251 return true;
252 }
253
254 return (ret & WM831X_CLKOUT_ENA) != 0;
255}
256
257static int wm831x_clkout_prepare(struct clk_hw *hw)
258{
259 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
260 clkout_hw);
261 struct wm831x *wm831x = clkdata->wm831x;
262 int ret;
263
264 ret = wm831x_reg_unlock(wm831x);
265 if (ret != 0) {
266 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
267 return ret;
268 }
269
270 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
271 WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
272 if (ret != 0)
273 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
274
275 wm831x_reg_lock(wm831x);
276
277 return ret;
278}
279
280static void wm831x_clkout_unprepare(struct clk_hw *hw)
281{
282 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
283 clkout_hw);
284 struct wm831x *wm831x = clkdata->wm831x;
285 int ret;
286
287 ret = wm831x_reg_unlock(wm831x);
288 if (ret != 0) {
289 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
290 return;
291 }
292
293 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
294 WM831X_CLKOUT_ENA, 0);
295 if (ret != 0)
296 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
297
298 wm831x_reg_lock(wm831x);
299}
300
301static const char *wm831x_clkout_parents[] = {
302 "xtal",
303 "fll",
304};
305
306static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
307{
308 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
309 clkout_hw);
310 struct wm831x *wm831x = clkdata->wm831x;
311 int ret;
312
313 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
314 if (ret < 0) {
315 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
316 ret);
317 return 0;
318 }
319
320 if (ret & WM831X_CLKOUT_SRC)
321 return 0;
322 else
323 return 1;
324}
325
326static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
327{
328 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
329 clkout_hw);
330 struct wm831x *wm831x = clkdata->wm831x;
331
332 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
333 WM831X_CLKOUT_SRC,
334 parent << WM831X_CLKOUT_SRC_SHIFT);
335}
336
337static const struct clk_ops wm831x_clkout_ops = {
338 .is_enabled = wm831x_clkout_is_enabled,
339 .prepare = wm831x_clkout_prepare,
340 .unprepare = wm831x_clkout_unprepare,
341 .get_parent = wm831x_clkout_get_parent,
342 .set_parent = wm831x_clkout_set_parent,
343};
344
345static struct clk_init_data wm831x_clkout_init = {
346 .name = "clkout",
347 .ops = &wm831x_clkout_ops,
348 .parent_names = wm831x_clkout_parents,
349 .num_parents = ARRAY_SIZE(wm831x_clkout_parents),
350 .flags = CLK_SET_RATE_PARENT,
351};
352
353static __devinit int wm831x_clk_probe(struct platform_device *pdev)
354{
355 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
356 struct wm831x_clk *clkdata;
357 int ret;
358
359 clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
360 if (!clkdata)
361 return -ENOMEM;
362
363 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
364 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
365 if (ret < 0) {
366 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
367 ret);
368 return ret;
369 }
370 clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
371
372 clkdata->xtal_hw.init = &wm831x_xtal_init;
373 clkdata->xtal = clk_register(&pdev->dev, &clkdata->xtal_hw);
374 if (!clkdata->xtal)
375 return -EINVAL;
376
377 clkdata->fll_hw.init = &wm831x_fll_init;
378 clkdata->fll = clk_register(&pdev->dev, &clkdata->fll_hw);
379 if (!clkdata->fll) {
380 ret = -EINVAL;
381 goto err_xtal;
382 }
383
384 clkdata->clkout_hw.init = &wm831x_clkout_init;
385 clkdata->clkout = clk_register(&pdev->dev, &clkdata->clkout_hw);
386 if (!clkdata->clkout) {
387 ret = -EINVAL;
388 goto err_fll;
389 }
390
391 dev_set_drvdata(&pdev->dev, clkdata);
392
393 return 0;
394
395err_fll:
396 clk_unregister(clkdata->fll);
397err_xtal:
398 clk_unregister(clkdata->xtal);
399 return ret;
400}
401
402static int __devexit wm831x_clk_remove(struct platform_device *pdev)
403{
404 struct wm831x_clk *clkdata = dev_get_drvdata(&pdev->dev);
405
406 clk_unregister(clkdata->clkout);
407 clk_unregister(clkdata->fll);
408 clk_unregister(clkdata->xtal);
409
410 return 0;
411}
412
413static struct platform_driver wm831x_clk_driver = {
414 .probe = wm831x_clk_probe,
415 .remove = __devexit_p(wm831x_clk_remove),
416 .driver = {
417 .name = "wm831x-clk",
418 .owner = THIS_MODULE,
419 },
420};
421
422module_platform_driver(wm831x_clk_driver);
423
424/* Module information */
425MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
426MODULE_DESCRIPTION("WM831x clock driver");
427MODULE_LICENSE("GPL");
428MODULE_ALIAS("platform:wm831x-clk");
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9a1eb0cfa95f..c87fdd710560 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -16,6 +16,7 @@
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/of.h>
19 20
20static DEFINE_SPINLOCK(enable_lock); 21static DEFINE_SPINLOCK(enable_lock);
21static DEFINE_MUTEX(prepare_lock); 22static DEFINE_MUTEX(prepare_lock);
@@ -1235,8 +1236,8 @@ int __clk_init(struct device *dev, struct clk *clk)
1235 * If clk->parents is not NULL we skip this entire block. This allows 1236 * If clk->parents is not NULL we skip this entire block. This allows
1236 * for clock drivers to statically initialize clk->parents. 1237 * for clock drivers to statically initialize clk->parents.
1237 */ 1238 */
1238 if (clk->num_parents && !clk->parents) { 1239 if (clk->num_parents > 1 && !clk->parents) {
1239 clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents), 1240 clk->parents = kzalloc((sizeof(struct clk*) * clk->num_parents),
1240 GFP_KERNEL); 1241 GFP_KERNEL);
1241 /* 1242 /*
1242 * __clk_lookup returns NULL for parents that have not been 1243 * __clk_lookup returns NULL for parents that have not been
@@ -1550,3 +1551,142 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
1550 return ret; 1551 return ret;
1551} 1552}
1552EXPORT_SYMBOL_GPL(clk_notifier_unregister); 1553EXPORT_SYMBOL_GPL(clk_notifier_unregister);
1554
1555#ifdef CONFIG_OF
1556/**
1557 * struct of_clk_provider - Clock provider registration structure
1558 * @link: Entry in global list of clock providers
1559 * @node: Pointer to device tree node of clock provider
1560 * @get: Get clock callback. Returns NULL or a struct clk for the
1561 * given clock specifier
1562 * @data: context pointer to be passed into @get callback
1563 */
1564struct of_clk_provider {
1565 struct list_head link;
1566
1567 struct device_node *node;
1568 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
1569 void *data;
1570};
1571
1572static LIST_HEAD(of_clk_providers);
1573static DEFINE_MUTEX(of_clk_lock);
1574
1575struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1576 void *data)
1577{
1578 return data;
1579}
1580EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
1581
1582/**
1583 * of_clk_add_provider() - Register a clock provider for a node
1584 * @np: Device node pointer associated with clock provider
1585 * @clk_src_get: callback for decoding clock
1586 * @data: context pointer for @clk_src_get callback.
1587 */
1588int of_clk_add_provider(struct device_node *np,
1589 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
1590 void *data),
1591 void *data)
1592{
1593 struct of_clk_provider *cp;
1594
1595 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
1596 if (!cp)
1597 return -ENOMEM;
1598
1599 cp->node = of_node_get(np);
1600 cp->data = data;
1601 cp->get = clk_src_get;
1602
1603 mutex_lock(&of_clk_lock);
1604 list_add(&cp->link, &of_clk_providers);
1605 mutex_unlock(&of_clk_lock);
1606 pr_debug("Added clock from %s\n", np->full_name);
1607
1608 return 0;
1609}
1610EXPORT_SYMBOL_GPL(of_clk_add_provider);
1611
1612/**
1613 * of_clk_del_provider() - Remove a previously registered clock provider
1614 * @np: Device node pointer associated with clock provider
1615 */
1616void of_clk_del_provider(struct device_node *np)
1617{
1618 struct of_clk_provider *cp;
1619
1620 mutex_lock(&of_clk_lock);
1621 list_for_each_entry(cp, &of_clk_providers, link) {
1622 if (cp->node == np) {
1623 list_del(&cp->link);
1624 of_node_put(cp->node);
1625 kfree(cp);
1626 break;
1627 }
1628 }
1629 mutex_unlock(&of_clk_lock);
1630}
1631EXPORT_SYMBOL_GPL(of_clk_del_provider);
1632
1633struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
1634{
1635 struct of_clk_provider *provider;
1636 struct clk *clk = ERR_PTR(-ENOENT);
1637
1638 /* Check if we have such a provider in our array */
1639 mutex_lock(&of_clk_lock);
1640 list_for_each_entry(provider, &of_clk_providers, link) {
1641 if (provider->node == clkspec->np)
1642 clk = provider->get(clkspec, provider->data);
1643 if (!IS_ERR(clk))
1644 break;
1645 }
1646 mutex_unlock(&of_clk_lock);
1647
1648 return clk;
1649}
1650
1651const char *of_clk_get_parent_name(struct device_node *np, int index)
1652{
1653 struct of_phandle_args clkspec;
1654 const char *clk_name;
1655 int rc;
1656
1657 if (index < 0)
1658 return NULL;
1659
1660 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
1661 &clkspec);
1662 if (rc)
1663 return NULL;
1664
1665 if (of_property_read_string_index(clkspec.np, "clock-output-names",
1666 clkspec.args_count ? clkspec.args[0] : 0,
1667 &clk_name) < 0)
1668 clk_name = clkspec.np->name;
1669
1670 of_node_put(clkspec.np);
1671 return clk_name;
1672}
1673EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
1674
1675/**
1676 * of_clk_init() - Scan and init clock providers from the DT
1677 * @matches: array of compatible values and init functions for providers.
1678 *
1679 * This function scans the device tree for matching clock providers and
1680 * calls their initialization functions
1681 */
1682void __init of_clk_init(const struct of_device_id *matches)
1683{
1684 struct device_node *np;
1685
1686 for_each_matching_node(np, matches) {
1687 const struct of_device_id *match = of_match_node(matches, np);
1688 of_clk_init_cb_t clk_init_cb = match->data;
1689 clk_init_cb(np);
1690 }
1691}
1692#endif
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index c535cf8c5770..d423c9bdd71a 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -19,10 +19,80 @@
19#include <linux/mutex.h> 19#include <linux/mutex.h>
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/clkdev.h> 21#include <linux/clkdev.h>
22#include <linux/of.h>
22 23
23static LIST_HEAD(clocks); 24static LIST_HEAD(clocks);
24static DEFINE_MUTEX(clocks_mutex); 25static DEFINE_MUTEX(clocks_mutex);
25 26
27#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
28struct clk *of_clk_get(struct device_node *np, int index)
29{
30 struct of_phandle_args clkspec;
31 struct clk *clk;
32 int rc;
33
34 if (index < 0)
35 return ERR_PTR(-EINVAL);
36
37 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
38 &clkspec);
39 if (rc)
40 return ERR_PTR(rc);
41
42 clk = of_clk_get_from_provider(&clkspec);
43 of_node_put(clkspec.np);
44 return clk;
45}
46EXPORT_SYMBOL(of_clk_get);
47
48/**
49 * of_clk_get_by_name() - Parse and lookup a clock referenced by a device node
50 * @np: pointer to clock consumer node
51 * @name: name of consumer's clock input, or NULL for the first clock reference
52 *
53 * This function parses the clocks and clock-names properties,
54 * and uses them to look up the struct clk from the registered list of clock
55 * providers.
56 */
57struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
58{
59 struct clk *clk = ERR_PTR(-ENOENT);
60
61 /* Walk up the tree of devices looking for a clock that matches */
62 while (np) {
63 int index = 0;
64
65 /*
66 * For named clocks, first look up the name in the
67 * "clock-names" property. If it cannot be found, then
68 * index will be an error code, and of_clk_get() will fail.
69 */
70 if (name)
71 index = of_property_match_string(np, "clock-names", name);
72 clk = of_clk_get(np, index);
73 if (!IS_ERR(clk))
74 break;
75 else if (name && index >= 0) {
76 pr_err("ERROR: could not get clock %s:%s(%i)\n",
77 np->full_name, name ? name : "", index);
78 return clk;
79 }
80
81 /*
82 * No matching clock found on this node. If the parent node
83 * has a "clock-ranges" property, then we can try one of its
84 * clocks.
85 */
86 np = np->parent;
87 if (np && !of_get_property(np, "clock-ranges", NULL))
88 break;
89 }
90
91 return clk;
92}
93EXPORT_SYMBOL(of_clk_get_by_name);
94#endif
95
26/* 96/*
27 * Find the correct struct clk for the device and connection ID. 97 * Find the correct struct clk for the device and connection ID.
28 * We do slightly fuzzy matching here: 98 * We do slightly fuzzy matching here:
@@ -83,6 +153,13 @@ EXPORT_SYMBOL(clk_get_sys);
83struct clk *clk_get(struct device *dev, const char *con_id) 153struct clk *clk_get(struct device *dev, const char *con_id)
84{ 154{
85 const char *dev_id = dev ? dev_name(dev) : NULL; 155 const char *dev_id = dev ? dev_name(dev) : NULL;
156 struct clk *clk;
157
158 if (dev) {
159 clk = of_clk_get_by_name(dev->of_node, con_id);
160 if (!IS_ERR(clk) && __clk_get(clk))
161 return clk;
162 }
86 163
87 return clk_get_sys(dev_id, con_id); 164 return clk_get_sys(dev_id, con_id);
88} 165}
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index db2391c054ee..844043ad0fe4 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -106,7 +106,7 @@ static struct clk_lookup lcdif_lookups[] = {
106 106
107static struct clk_lookup gpmi_lookups[] = { 107static struct clk_lookup gpmi_lookups[] = {
108 { .dev_id = "imx23-gpmi-nand", }, 108 { .dev_id = "imx23-gpmi-nand", },
109 { .dev_id = "8000c000.gpmi", }, 109 { .dev_id = "8000c000.gpmi-nand", },
110}; 110};
111 111
112static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 112static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
@@ -189,6 +189,7 @@ int __init mx23_clocks_init(void)
189 } 189 }
190 190
191 clk_register_clkdev(clks[clk32k], NULL, "timrot"); 191 clk_register_clkdev(clks[clk32k], NULL, "timrot");
192 clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
192 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); 193 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
193 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); 194 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
194 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); 195 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 7fad6c8c13d2..e3aab67b3eb7 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
112 112
113 /* 113 /*
114 * 480 MHz seems too high to be ssp clock source directly, 114 * 480 MHz seems too high to be ssp clock source directly,
115 * so set frac0 to get a 288 MHz ref_io0. 115 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
116 */ 116 */
117 val = readl_relaxed(FRAC0); 117 val = readl_relaxed(FRAC0);
118 val &= ~(0x3f << BP_FRAC0_IO0FRAC); 118 val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
119 val |= 30 << BP_FRAC0_IO0FRAC; 119 val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
120 writel_relaxed(val, FRAC0); 120 writel_relaxed(val, FRAC0);
121} 121}
122 122
@@ -174,7 +174,7 @@ static struct clk_lookup lcdif_lookups[] = {
174 174
175static struct clk_lookup gpmi_lookups[] = { 175static struct clk_lookup gpmi_lookups[] = {
176 { .dev_id = "imx28-gpmi-nand", }, 176 { .dev_id = "imx28-gpmi-nand", },
177 { .dev_id = "8000c000.gpmi", }, 177 { .dev_id = "8000c000.gpmi-nand", },
178}; 178};
179 179
180static struct clk_lookup fec_lookups[] = { 180static struct clk_lookup fec_lookups[] = {
@@ -314,6 +314,7 @@ int __init mx28_clocks_init(void)
314 314
315 clk_register_clkdev(clks[clk32k], NULL, "timrot"); 315 clk_register_clkdev(clks[clk32k], NULL, "timrot");
316 clk_register_clkdev(clks[enet_out], NULL, "enet_out"); 316 clk_register_clkdev(clks[enet_out], NULL, "enet_out");
317 clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
317 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); 318 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
318 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); 319 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
319 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); 320 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
@@ -328,6 +329,10 @@ int __init mx28_clocks_init(void)
328 clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups)); 329 clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
329 clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups)); 330 clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
330 clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups)); 331 clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
332 clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
333 clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
334 clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
335 clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
331 336
332 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 337 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
333 clk_prepare_enable(clks[clks_init_on[i]]); 338 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/clk/versatile/Makefile b/drivers/clk/versatile/Makefile
new file mode 100644
index 000000000000..50cf6a2ee693
--- /dev/null
+++ b/drivers/clk/versatile/Makefile
@@ -0,0 +1,3 @@
1# Makefile for Versatile-specific clocks
2obj-$(CONFIG_ICST) += clk-icst.o
3obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o
diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
new file mode 100644
index 000000000000..f555b50a5fa5
--- /dev/null
+++ b/drivers/clk/versatile/clk-icst.c
@@ -0,0 +1,100 @@
1/*
2 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
3 * We wrap the custom interface from <asm/hardware/icst.h> into the generic
4 * clock framework.
5 *
6 * TODO: when all ARM reference designs are migrated to generic clocks, the
7 * ICST clock code from the ARM tree should probably be merged into this
8 * file.
9 */
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/err.h>
13#include <linux/clk-provider.h>
14
15#include "clk-icst.h"
16
17/**
18 * struct clk_icst - ICST VCO clock wrapper
19 * @hw: corresponding clock hardware entry
20 * @params: parameters for this ICST instance
21 * @rate: current rate
22 * @setvco: function to commit ICST settings to hardware
23 */
24struct clk_icst {
25 struct clk_hw hw;
26 const struct icst_params *params;
27 unsigned long rate;
28 struct icst_vco (*getvco)(void);
29 void (*setvco)(struct icst_vco);
30};
31
32#define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
33
34static unsigned long icst_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 struct clk_icst *icst = to_icst(hw);
38 struct icst_vco vco;
39
40 vco = icst->getvco();
41 icst->rate = icst_hz(icst->params, vco);
42 return icst->rate;
43}
44
45static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
46 unsigned long *prate)
47{
48 struct clk_icst *icst = to_icst(hw);
49 struct icst_vco vco;
50
51 vco = icst_hz_to_vco(icst->params, rate);
52 return icst_hz(icst->params, vco);
53}
54
55static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
56 unsigned long parent_rate)
57{
58 struct clk_icst *icst = to_icst(hw);
59 struct icst_vco vco;
60
61 vco = icst_hz_to_vco(icst->params, rate);
62 icst->rate = icst_hz(icst->params, vco);
63 icst->setvco(vco);
64 return 0;
65}
66
67static const struct clk_ops icst_ops = {
68 .recalc_rate = icst_recalc_rate,
69 .round_rate = icst_round_rate,
70 .set_rate = icst_set_rate,
71};
72
73struct clk * __init icst_clk_register(struct device *dev,
74 const struct clk_icst_desc *desc)
75{
76 struct clk *clk;
77 struct clk_icst *icst;
78 struct clk_init_data init;
79
80 icst = kzalloc(sizeof(struct clk_icst), GFP_KERNEL);
81 if (!icst) {
82 pr_err("could not allocate ICST clock!\n");
83 return ERR_PTR(-ENOMEM);
84 }
85 init.name = "icst";
86 init.ops = &icst_ops;
87 init.flags = CLK_IS_ROOT;
88 init.parent_names = NULL;
89 init.num_parents = 0;
90 icst->hw.init = &init;
91 icst->params = desc->params;
92 icst->getvco = desc->getvco;
93 icst->setvco = desc->setvco;
94
95 clk = clk_register(dev, &icst->hw);
96 if (IS_ERR(clk))
97 kfree(icst);
98
99 return clk;
100}
diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h
new file mode 100644
index 000000000000..71b4c56c1410
--- /dev/null
+++ b/drivers/clk/versatile/clk-icst.h
@@ -0,0 +1,10 @@
1#include <asm/hardware/icst.h>
2
3struct clk_icst_desc {
4 const struct icst_params *params;
5 struct icst_vco (*getvco)(void);
6 void (*setvco)(struct icst_vco);
7};
8
9struct clk *icst_clk_register(struct device *dev,
10 const struct clk_icst_desc *desc);
diff --git a/drivers/clk/versatile/clk-integrator.c b/drivers/clk/versatile/clk-integrator.c
new file mode 100644
index 000000000000..a5053921bf7f
--- /dev/null
+++ b/drivers/clk/versatile/clk-integrator.c
@@ -0,0 +1,111 @@
1#include <linux/clk.h>
2#include <linux/clkdev.h>
3#include <linux/err.h>
4#include <linux/io.h>
5#include <linux/clk-provider.h>
6
7#include <mach/hardware.h>
8#include <mach/platform.h>
9
10#include "clk-icst.h"
11
12/*
13 * Implementation of the ARM Integrator/AP and Integrator/CP clock tree.
14 * Inspired by portions of:
15 * plat-versatile/clock.c and plat-versatile/include/plat/clock.h
16 */
17#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
18#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
19
20/**
21 * cp_auxvco_get() - get ICST VCO settings for the Integrator/CP
22 * @vco: ICST VCO parameters to update with hardware status
23 */
24static struct icst_vco cp_auxvco_get(void)
25{
26 u32 val;
27 struct icst_vco vco;
28
29 val = readl(CM_AUXOSC);
30 vco.v = val & 0x1ff;
31 vco.r = (val >> 9) & 0x7f;
32 vco.s = (val >> 16) & 03;
33 return vco;
34}
35
36/**
37 * cp_auxvco_set() - commit changes to Integrator/CP ICST VCO
38 * @vco: ICST VCO parameters to commit
39 */
40static void cp_auxvco_set(struct icst_vco vco)
41{
42 u32 val;
43
44 val = readl(CM_AUXOSC) & ~0x7ffff;
45 val |= vco.v | (vco.r << 9) | (vco.s << 16);
46
47 /* This magic unlocks the CM VCO so it can be controlled */
48 writel(0xa05f, CM_LOCK);
49 writel(val, CM_AUXOSC);
50 /* This locks the CM again */
51 writel(0, CM_LOCK);
52}
53
54static const struct icst_params cp_auxvco_params = {
55 .ref = 24000000,
56 .vco_max = ICST525_VCO_MAX_5V,
57 .vco_min = ICST525_VCO_MIN,
58 .vd_min = 8,
59 .vd_max = 263,
60 .rd_min = 3,
61 .rd_max = 65,
62 .s2div = icst525_s2div,
63 .idx2s = icst525_idx2s,
64};
65
66static const struct clk_icst_desc __initdata cp_icst_desc = {
67 .params = &cp_auxvco_params,
68 .getvco = cp_auxvco_get,
69 .setvco = cp_auxvco_set,
70};
71
72/*
73 * integrator_clk_init() - set up the integrator clock tree
74 * @is_cp: pass true if it's the Integrator/CP else AP is assumed
75 */
76void __init integrator_clk_init(bool is_cp)
77{
78 struct clk *clk;
79
80 /* APB clock dummy */
81 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
82 clk_register_clkdev(clk, "apb_pclk", NULL);
83
84 /* UART reference clock */
85 clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
86 14745600);
87 clk_register_clkdev(clk, NULL, "uart0");
88 clk_register_clkdev(clk, NULL, "uart1");
89 if (is_cp)
90 clk_register_clkdev(clk, NULL, "mmci");
91
92 /* 24 MHz clock */
93 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
94 24000000);
95 clk_register_clkdev(clk, NULL, "kmi0");
96 clk_register_clkdev(clk, NULL, "kmi1");
97 if (!is_cp)
98 clk_register_clkdev(clk, NULL, "ap_timer");
99
100 if (!is_cp)
101 return;
102
103 /* 1 MHz clock */
104 clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
105 1000000);
106 clk_register_clkdev(clk, NULL, "sp804");
107
108 /* ICST VCO clock used on the Integrator/CP CLCD */
109 clk = icst_clk_register(NULL, &cp_icst_desc);
110 clk_register_clkdev(clk, NULL, "clcd");
111}
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index eb3f84bc5325..9c7f5807824b 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -64,7 +64,7 @@ struct clk {
64 .parent_names = _parent_names, \ 64 .parent_names = _parent_names, \
65 .num_parents = ARRAY_SIZE(_parent_names), \ 65 .num_parents = ARRAY_SIZE(_parent_names), \
66 .parents = _parents, \ 66 .parents = _parents, \
67 .flags = _flags, \ 67 .flags = _flags | CLK_IS_BASIC, \
68 } 68 }
69 69
70#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ 70#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
@@ -103,9 +103,9 @@ struct clk {
103 DEFINE_CLK(_name, clk_gate_ops, _flags, \ 103 DEFINE_CLK(_name, clk_gate_ops, _flags, \
104 _name##_parent_names, _name##_parents); 104 _name##_parent_names, _name##_parents);
105 105
106#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ 106#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
107 _flags, _reg, _shift, _width, \ 107 _flags, _reg, _shift, _width, \
108 _divider_flags, _lock) \ 108 _divider_flags, _table, _lock) \
109 static struct clk _name; \ 109 static struct clk _name; \
110 static const char *_name##_parent_names[] = { \ 110 static const char *_name##_parent_names[] = { \
111 _parent_name, \ 111 _parent_name, \
@@ -121,11 +121,27 @@ struct clk {
121 .shift = _shift, \ 121 .shift = _shift, \
122 .width = _width, \ 122 .width = _width, \
123 .flags = _divider_flags, \ 123 .flags = _divider_flags, \
124 .table = _table, \
124 .lock = _lock, \ 125 .lock = _lock, \
125 }; \ 126 }; \
126 DEFINE_CLK(_name, clk_divider_ops, _flags, \ 127 DEFINE_CLK(_name, clk_divider_ops, _flags, \
127 _name##_parent_names, _name##_parents); 128 _name##_parent_names, _name##_parents);
128 129
130#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
131 _flags, _reg, _shift, _width, \
132 _divider_flags, _lock) \
133 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
134 _flags, _reg, _shift, _width, \
135 _divider_flags, NULL, _lock)
136
137#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
138 _parent_ptr, _flags, _reg, \
139 _shift, _width, _divider_flags, \
140 _table, _lock) \
141 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
142 _flags, _reg, _shift, _width, \
143 _divider_flags, _table, _lock) \
144
129#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ 145#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
130 _reg, _shift, _width, \ 146 _reg, _shift, _width, \
131 _mux_flags, _lock) \ 147 _mux_flags, _lock) \
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4a0b483986c3..77335fac943e 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -25,6 +25,7 @@
25#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 25#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
28 29
29struct clk_hw; 30struct clk_hw;
30 31
@@ -143,7 +144,7 @@ struct clk_init_data {
143 */ 144 */
144struct clk_hw { 145struct clk_hw {
145 struct clk *clk; 146 struct clk *clk;
146 struct clk_init_data *init; 147 const struct clk_init_data *init;
147}; 148};
148 149
149/* 150/*
@@ -171,6 +172,8 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
171 const char *parent_name, unsigned long flags, 172 const char *parent_name, unsigned long flags,
172 unsigned long fixed_rate); 173 unsigned long fixed_rate);
173 174
175void of_fixed_clk_setup(struct device_node *np);
176
174/** 177/**
175 * struct clk_gate - gating clock 178 * struct clk_gate - gating clock
176 * 179 *
@@ -203,6 +206,11 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
203 void __iomem *reg, u8 bit_idx, 206 void __iomem *reg, u8 bit_idx,
204 u8 clk_gate_flags, spinlock_t *lock); 207 u8 clk_gate_flags, spinlock_t *lock);
205 208
209struct clk_div_table {
210 unsigned int val;
211 unsigned int div;
212};
213
206/** 214/**
207 * struct clk_divider - adjustable divider clock 215 * struct clk_divider - adjustable divider clock
208 * 216 *
@@ -210,6 +218,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
210 * @reg: register containing the divider 218 * @reg: register containing the divider
211 * @shift: shift to the divider bit field 219 * @shift: shift to the divider bit field
212 * @width: width of the divider bit field 220 * @width: width of the divider bit field
221 * @table: array of value/divider pairs, last entry should have div = 0
213 * @lock: register lock 222 * @lock: register lock
214 * 223 *
215 * Clock with an adjustable divider affecting its output frequency. Implements 224 * Clock with an adjustable divider affecting its output frequency. Implements
@@ -229,6 +238,7 @@ struct clk_divider {
229 u8 shift; 238 u8 shift;
230 u8 width; 239 u8 width;
231 u8 flags; 240 u8 flags;
241 const struct clk_div_table *table;
232 spinlock_t *lock; 242 spinlock_t *lock;
233}; 243};
234 244
@@ -240,6 +250,11 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
240 const char *parent_name, unsigned long flags, 250 const char *parent_name, unsigned long flags,
241 void __iomem *reg, u8 shift, u8 width, 251 void __iomem *reg, u8 shift, u8 width,
242 u8 clk_divider_flags, spinlock_t *lock); 252 u8 clk_divider_flags, spinlock_t *lock);
253struct clk *clk_register_divider_table(struct device *dev, const char *name,
254 const char *parent_name, unsigned long flags,
255 void __iomem *reg, u8 shift, u8 width,
256 u8 clk_divider_flags, const struct clk_div_table *table,
257 spinlock_t *lock);
243 258
244/** 259/**
245 * struct clk_mux - multiplexer clock 260 * struct clk_mux - multiplexer clock
@@ -334,5 +349,19 @@ void __clk_unprepare(struct clk *clk);
334void __clk_reparent(struct clk *clk, struct clk *new_parent); 349void __clk_reparent(struct clk *clk, struct clk *new_parent);
335unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 350unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
336 351
352struct of_device_id;
353
354typedef void (*of_clk_init_cb_t)(struct device_node *);
355
356int of_clk_add_provider(struct device_node *np,
357 struct clk *(*clk_src_get)(struct of_phandle_args *args,
358 void *data),
359 void *data);
360void of_clk_del_provider(struct device_node *np);
361struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
362 void *data);
363const char *of_clk_get_parent_name(struct device_node *np, int index);
364void of_clk_init(const struct of_device_id *matches);
365
337#endif /* CONFIG_COMMON_CLK */ 366#endif /* CONFIG_COMMON_CLK */
338#endif /* CLK_PROVIDER_H */ 367#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index f6fb40c8bf97..2fd6a4234531 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -12,6 +12,7 @@
12#ifndef __LINUX_CLK_H 12#ifndef __LINUX_CLK_H
13#define __LINUX_CLK_H 13#define __LINUX_CLK_H
14 14
15#include <linux/err.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/notifier.h> 17#include <linux/notifier.h>
17 18
@@ -310,4 +311,23 @@ struct clk *clk_get_sys(const char *dev_id, const char *con_id);
310int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, 311int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
311 struct device *dev); 312 struct device *dev);
312 313
314struct device_node;
315struct of_phandle_args;
316
317#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
318struct clk *of_clk_get(struct device_node *np, int index);
319struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
320struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);
321#else
322static inline struct clk *of_clk_get(struct device_node *np, int index)
323{
324 return ERR_PTR(-ENOENT);
325}
326static inline struct clk *of_clk_get_by_name(struct device_node *np,
327 const char *name)
328{
329 return ERR_PTR(-ENOENT);
330}
331#endif
332
313#endif 333#endif
diff --git a/include/linux/platform_data/clk-integrator.h b/include/linux/platform_data/clk-integrator.h
new file mode 100644
index 000000000000..83fe9c283bb8
--- /dev/null
+++ b/include/linux/platform_data/clk-integrator.h
@@ -0,0 +1 @@
void integrator_clk_init(bool is_cp);
diff --git a/include/linux/platform_data/clk-u300.h b/include/linux/platform_data/clk-u300.h
new file mode 100644
index 000000000000..8429e73911a1
--- /dev/null
+++ b/include/linux/platform_data/clk-u300.h
@@ -0,0 +1 @@
void __init u300_clk_init(void __iomem *base);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 23:46:01 -0500